From ralf@linux-mips.org Mon Feb 1 03:18:44 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 01 Feb 2010 03:18:52 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:42434 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1493297Ab0BACSo (ORCPT ); Mon, 1 Feb 2010 03:18:44 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id o112Iu6R009066; Mon, 1 Feb 2010 03:18:57 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id o112ItGc009062; Mon, 1 Feb 2010 03:18:55 +0100 Date: Mon, 1 Feb 2010 03:18:54 +0100 From: Ralf Baechle To: Guenter Roeck Cc: "Maciej W. Rozycki" , David Daney , "linux-mips@linux-mips.org" Subject: Re: Kernel crash in 2.6.32.6 / bcm1480 with 16k page size Message-ID: <20100201021854.GA8572@linux-mips.org> References: <20100129151220.GA3882@ericsson.com> <4B6316D2.1060006@caviumnetworks.com> <20100129180619.GA20113@linux-mips.org> <20100129183926.GB9895@ericsson.com> <4B632F60.4000604@caviumnetworks.com> <20100129192532.GA11123@ericsson.com> <4B6336F1.8070208@caviumnetworks.com> <20100129195801.GC11123@ericsson.com> <20100131165503.GA18523@ericsson.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20100131165503.GA18523@ericsson.com> User-Agent: Mutt/1.5.20 (2009-08-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25796 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Sun, Jan 31, 2010 at 08:55:03AM -0800, Guenter Roeck wrote: > > The size of the address space can be probed via CP0 registers (for MIPS > > architecture processors that is). No need to add any CPU dependencies > > (except from legacy 64-bit MIPS processors perhaps). > > > That would help. Do you happen to know which CP0 register(s) to look for ? > I browsed through the MIPS 5K and 20Kc manuals, but didn't find it. Write a value with all bits set to c0_entryhi, then read it back again. The set bits in the VPN2 bitfield will indicate the size of the virtual address range supported. The MIPS64 documentation also calls this value SEGBITS. The nice thing about this probe is that it is supported for all 64-bit MIPS processors except the R8000 which has an entirely different TLB scheme anyway. Similarly it is possible to probe the physical address range in either c0_entrylo0 or c0_entrylo1. This is also of interest on 32-bit processors. Ralf From ydgoo9@gmail.com Mon Feb 1 05:38:50 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 01 Feb 2010 05:38:54 +0100 (CET) Received: from mail-px0-f181.google.com ([209.85.216.181]:56630 "EHLO mail-px0-f181.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491109Ab0BAEiu convert rfc822-to-8bit (ORCPT ); Mon, 1 Feb 2010 05:38:50 +0100 Received: by pxi11 with SMTP id 11so3691982pxi.22 for ; Sun, 31 Jan 2010 20:38:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:in-reply-to:references :date:message-id:subject:from:to:content-type :content-transfer-encoding; bh=odC0p4YoMigSNBR0oOC34kx5Qno9xVqDZSn2Aivg3cg=; b=c//+Iq6pZlR/J9+18rPpPpmL2kQcTVit/LIDJqAZtKJg7uwg3khXAyKZV4gLTli4qQ v+lMDxsmeOCYN4GtjqADE9REGg+5okFYI/PWUrDBdws0i1oLB1fxwnSxu7Jc+4lN29rT BYWflLhvZOsqwda442PnJJOnJkF2wKKi+oQqw= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :content-type:content-transfer-encoding; b=CLSQoYjvWFJZlAzuevCGFhzqkkLqD2eU/oJSRj4RTeqIoAbdqrBL6035mcTFRcEAGm Vtft1IABds4BkIj9+LtAh9qVeY6PzC3V9Q+X7w7UeVbnln5gStI8ZZImLAHypUx/yTM1 giRMX2rI36SVp4VUDmpuFBj5DfsYWdUd1PkSw= MIME-Version: 1.0 Received: by 10.140.82.42 with SMTP id f42mr2818896rvb.163.1264999122356; Sun, 31 Jan 2010 20:38:42 -0800 (PST) In-Reply-To: <20100129155303.GB3376@woodpecker.gentoo.org> References: <38dc7fce1001290227v746c0a3dp4b3d81a58e73cf83@mail.gmail.com> <20100129155303.GB3376@woodpecker.gentoo.org> Date: Mon, 1 Feb 2010 13:38:42 +0900 Message-ID: <38dc7fce1001312038n6238ce9bga92df61ba04317dd@mail.gmail.com> Subject: Re: GCC 4.4.2(mips) with -mplt option From: YD To: YD , linux-mips Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25797 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ydgoo9@gmail.com Precedence: bulk X-list: linux-mips I saw the toolchain for MIPS from broadcom(GCC-4.2.0, uClibc-0.9.29) does support -mplt option. I assumed they patched some code for uClibc and GCC also. I hope I could find some patch like it. but I did not find yet. On Sat, Jan 30, 2010 at 12:53 AM, Zhang Le wrote: > On 19:27 Fri 29 Jan     , YD wrote: >> Hello, >> >> I have built the toolchain using the buildroot ( GCC 4.4.2 with >> uClibc-0.9.30.1 ) > > I think you need to check if uClibc supports this feature. > -mplt need support from libc, specifically dynamic loader, ld.so. > >> >> Everything works well but when I compiled with -mplt option, always it >> fails with Segmentation fault. >> >> I read some articles that with -mplt option, preformance will be 10% >> highter than without plt option. >> >> I don't know why this fails everytime. please help me... >> >> #include >> int main() >> { >>  printf("Hello world \n"); return 0; >> } >> >> #mipsel-linux-gcc  -o a a.c >>  Hello world >> #mipsel-linux-gcc -mplt -o a a.c >>  Segmentation fault >> #mipsel-linux-gcc -mplt -no-shared -o a a.c >>  Segmentation fault >> #mipsel-linux-gcc -mplt -no-shared -mabicalls -o a a.c >>  Segmentation fault > > And -no-shared is actually not needed > http://gcc.gnu.org/ml/gcc/2008-12/msg00010.html > > You should be able to verify this by 'mipsel-linux-gcc -v' > > Zhang, Le > From wuzhangjin@gmail.com Mon Feb 1 07:35:33 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 01 Feb 2010 07:35:38 +0100 (CET) Received: from mail-iw0-f183.google.com ([209.85.223.183]:61088 "EHLO mail-iw0-f183.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491852Ab0BAGfd (ORCPT ); Mon, 1 Feb 2010 07:35:33 +0100 Received: by iwn13 with SMTP id 13so252669iwn.20 for ; Sun, 31 Jan 2010 22:35:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:subject:from:reply-to:to:cc :in-reply-to:references:content-type:organization:date:message-id :mime-version:x-mailer:content-transfer-encoding; bh=lQ7CVHceWGeOru1CECZ0uuHJX+bNelRNB5k81G4+aeQ=; b=WiMzVm1UY3xXREoj1CkEOFQrDaEthR+2H+tw5svfC87a2l/7NiL7yH7AG7ZAFMUYRJ nyksI4TMAR71Zxf9K8pLUwWwcm1stntC/7KugD9V8Zmuzc/Ywt0ETY0yF1etQKY/lWJB Y+bHdfaqy/o7A/TGoEIeB6ZAB92+mtwEIAe0Y= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=subject:from:reply-to:to:cc:in-reply-to:references:content-type :organization:date:message-id:mime-version:x-mailer :content-transfer-encoding; b=wrdWfZtygx4ykurAyriu/o/qOXY9rtHU2BomiPeQIyb0JWmHKWzgLkZCzopGPbY66g sjrb/d/K+697bdxcyeUgI+xdU0/EM3Kqqy/fd4bFHY2emZNEXnuu1pOJ3DK332lHp9RP ZrGoN0GI5m/S09bhBsWYBQF/vxbGR/CgSrBpE= Received: by 10.231.148.83 with SMTP id o19mr279622ibv.39.1265006125863; Sun, 31 Jan 2010 22:35:25 -0800 (PST) Received: from ?192.168.2.212? ([202.201.14.140]) by mx.google.com with ESMTPS id 21sm5141367iwn.10.2010.01.31.22.35.23 (version=TLSv1/SSLv3 cipher=RC4-MD5); Sun, 31 Jan 2010 22:35:25 -0800 (PST) Subject: Re: [PATCH 1/3] MIPS: AR7 whitespace hacking From: Wu Zhangjin Reply-To: wuzhangjin@gmail.com To: Alexander Clouter Cc: linux-mips@linux-mips.org In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Organization: DSLab, Lanzhou University, China Date: Mon, 01 Feb 2010 14:29:17 +0800 Message-ID: <1265005758.31984.8.camel@falcon> Mime-Version: 1.0 X-Mailer: Evolution 2.28.2 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25798 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips On Sun, 2010-01-31 at 19:38 +0000, Alexander Clouter wrote: > MIPS: AR7 whitespace hacking > > Signed-off-by: Alexander Clouter [...] > void __init prom_free_prom_memory(void) > diff --git a/arch/mips/ar7/platform.c b/arch/mips/ar7/platform.c > index c591f69..76a358e 100644 > --- a/arch/mips/ar7/platform.c > +++ b/arch/mips/ar7/platform.c > @@ -42,39 +42,42 @@ > #include > #include > > +/***************************************************************************** > + * VLYNQ Bus > + ****************************************************************************/ Why not simply use: /* VLYNQ Bus */ You have deleted lots of whitespaces, but added more *. [...] > +/***************************************************************************** > + * Flash > + ****************************************************************************/ [...] > + > +/***************************************************************************** > + * Ethernet > + ****************************************************************************/ [...] > + > +/***************************************************************************** > + * USB > + ****************************************************************************/ > + [...] > > +/***************************************************************************** > + * LEDs > + ****************************************************************************/ [...] > +/***************************************************************************** > + * Watchdog > + ****************************************************************************/ [...] > + > +/***************************************************************************** > + * Init > + ****************************************************************************/ [...] > > @@ -70,7 +71,6 @@ console_initcall(ar7_init_console); > * Initializes basic routines and structures pointers, memory size (as > * given by the bios and saves the command line. > */ > - > void __init plat_mem_setup(void) > { > unsigned long io_base; > @@ -88,6 +88,5 @@ void __init plat_mem_setup(void) > prom_meminit(); > > printk(KERN_INFO "%s, ID: 0x%04x, Revision: 0x%02x\n", > - get_system_type(), > - ar7_chip_id(), ar7_chip_rev()); > + get_system_type(), ar7_chip_id(), ar7_chip_rev()); > } Perhaps you can use pr_info() instead of printk(KERN_INFO) too, of course, if there are more printk(KERN_...), you can replace them by pr_xxx defined in include/linux/kernel.h Best Regards, Wu Zhangjin From wuzhangjin@gmail.com Mon Feb 1 07:38:59 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 01 Feb 2010 07:39:02 +0100 (CET) Received: from mail-iw0-f183.google.com ([209.85.223.183]:47455 "EHLO mail-iw0-f183.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491852Ab0BAGi7 (ORCPT ); Mon, 1 Feb 2010 07:38:59 +0100 Received: by iwn13 with SMTP id 13so254491iwn.20 for ; Sun, 31 Jan 2010 22:38:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:subject:from:reply-to:to:cc :in-reply-to:references:content-type:organization:date:message-id :mime-version:x-mailer:content-transfer-encoding; bh=oI84IL5wgTWFsyM2LwmGGXgIuAwXEjhhHfys4o7Rpgg=; b=b2bFuQ5CtuLDhFjIIYsbBUP2qK3gHM6+cXljLR+ZaITfHLbGhZrpYuUk8X7oUgWu1D D2guBhegOEtNSZqYG03RrgqlGlVCRlrzLy0rcdw+5nB/g/c5YHl1zhP7zDzEL7sCAuZD ihlm3WbIJPu1N2GQssESOaKi7pThuB1B0SgkY= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=subject:from:reply-to:to:cc:in-reply-to:references:content-type :organization:date:message-id:mime-version:x-mailer :content-transfer-encoding; b=O/lmP11HCdlMbN0MwJzuQYrulfdIRqH5Tk9g4wsHk/ExpsR4jzia4gn1xd3mIy2QJD 2wxOKcF6rjlmFovYiO4J6hx5YM28aLTzlDoxDhyq3Mhc221EF7zpf85VbnStbDZmYZGy szI+ieeVArg73cIDYCKhI0ISAr2wbecTQrccA= Received: by 10.231.85.198 with SMTP id p6mr3503398ibl.65.1265006333178; Sun, 31 Jan 2010 22:38:53 -0800 (PST) Received: from ?192.168.2.212? ([202.201.14.140]) by mx.google.com with ESMTPS id 20sm3140910iwn.9.2010.01.31.22.38.51 (version=TLSv1/SSLv3 cipher=RC4-MD5); Sun, 31 Jan 2010 22:38:52 -0800 (PST) Subject: Re: [PATCH 3/3] MIPS: AR7 make ar7_register_devices much more durable From: Wu Zhangjin Reply-To: wuzhangjin@gmail.com To: Alexander Clouter Cc: linux-mips@linux-mips.org In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Organization: DSLab, Lanzhou University, China Date: Mon, 01 Feb 2010 14:32:51 +0800 Message-ID: <1265005971.31984.10.camel@falcon> Mime-Version: 1.0 X-Mailer: Evolution 2.28.2 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25799 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips On Sun, 2010-01-31 at 19:39 +0000, Alexander Clouter wrote: > MIPS: AR7 make ar7_register_devices much more durable > All of the printk(KERN_XXX stuff can be replaced by pr_xxx defined in include/linux/kernel.h Regards, Wu Zhangjin From andi@rhlx01.hs-esslingen.de Mon Feb 1 07:39:39 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 01 Feb 2010 07:39:45 +0100 (CET) Received: from rhlx01.hs-esslingen.de ([129.143.116.10]:46215 "EHLO rhlx01.hs-esslingen.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491770Ab0BAGjj (ORCPT ); Mon, 1 Feb 2010 07:39:39 +0100 Received: by rhlx01.hs-esslingen.de (Postfix, from userid 102) id 13CF34004C; Mon, 1 Feb 2010 07:39:35 +0100 (CET) Date: Mon, 1 Feb 2010 07:39:35 +0100 From: Andreas Mohr To: Alan Stern Cc: Maxime Bizon , David Brownell , linux-usb@vger.kernel.org, Ralf Baechle , linux-mips@linux-mips.org Subject: Re: [PATCH 2/2] USB: add Broadcom 63xx integrated EHCI controller support. Message-ID: <20100201063934.GA13692@rhlx01.hs-esslingen.de> References: <1264874071-28851-3-git-send-email-mbizon@freebox.fr> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: X-Priority: none User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25800 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: andi@lisas.de Precedence: bulk X-list: linux-mips On Sat, Jan 30, 2010 at 09:11:45PM -0500, Alan Stern wrote: > On Sat, 30 Jan 2010, Maxime Bizon wrote: > > +static const struct hc_driver ehci_bcm63xx_hc_driver = { > > + .description = hcd_name, > > + .product_desc = "BCM63XX integrated EHCI controller", > > + .hcd_priv_size = sizeof(struct ehci_hcd), > > + > > + .irq = ehci_irq, > > + .flags = HCD_MEMORY | HCD_USB2, > > + > > + .reset = ehci_bcm63xx_setup, > > + .start = ehci_run, > > + .stop = ehci_stop, > > + .shutdown = ehci_shutdown, > > + > > + .urb_enqueue = ehci_urb_enqueue, > > + .urb_dequeue = ehci_urb_dequeue, > > + .endpoint_disable = ehci_endpoint_disable, > > + > > + .get_frame_number = ehci_get_frame, > > + > > + .hub_status_data = ehci_hub_status_data, > > + .hub_control = ehci_hub_control, > > + .bus_suspend = ehci_bus_suspend, > > + .bus_resume = ehci_bus_resume, > > + .relinquish_port = ehci_relinquish_port, > > + .port_handed_over = ehci_port_handed_over, > > +}; > > You'll run into trouble if you don't include the standard > endpoint_reset method pointer. > > Alan Stern And one will run into even more trouble (as did I! hung ports galore...) if one doesn't include the .clear_tt_buffer_complete callback either, due to using an outdated non-mainline-synchronized host driver (that was Broadcom as well, ehci-ssb.c). The best thing to do is a full review of all _diffs_ in _all_ usb host kernel files in even moderately recent times (say 2.6.23 - 2.6.33) and add every missing required item to these bcm63xx host files, too. Is your code coming from OpenWrt too by chance? :-P Kudos to Alan for catching this problem during review (probably he was still alerted by my miserable luck) HTH, Andreas Mohr P.S.: yup I should get ehci-ssb.c cleaned up and submitted soon. From mlistz@gmail.com Mon Feb 1 09:18:04 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 01 Feb 2010 09:18:12 +0100 (CET) Received: from mail-px0-f181.google.com ([209.85.216.181]:39063 "EHLO mail-px0-f181.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491876Ab0BAISE (ORCPT ); Mon, 1 Feb 2010 09:18:04 +0100 Received: by pxi11 with SMTP id 11so3860325pxi.22 for ; Mon, 01 Feb 2010 00:17:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:date:message-id:subject :from:to:cc:content-type; bh=MCKFwehyzSIScMV5YXj/qup352Q1UPICsr780eg/gns=; b=p0DzbDc2rNabX/B4PVfcJRftWT8ntCL+Z2XSIktAxjMg0wnbyxldlYlBARGwNlb0Qv AaA67BQRDa1UuoYpXC0cJ+GdAzieuX7kq8VVJxPgL08OjwMQNIryHhprjaFkQch02eP8 EsbdcdyOaILl9alZAhb1MexHp7AMsXbDm6c8M= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:date:message-id:subject:from:to:cc:content-type; b=OVDRz+X8c9i01VTsjOaSlA9NYfoUfrX158iGdaknwe1EliZBwGYMhlCNz3R+lWfC/Y qmaKsITlYcgaH6pGFu/Ln97igsa7oq6BIkfro55JmOcFw4E5lrImGgWxsGjs36gbtuvf A7zSXXEwoRFWqTK4zfRZrl7tT//znJc0Q43P8= MIME-Version: 1.0 Received: by 10.142.6.9 with SMTP id 9mr2888260wff.257.1265012277392; Mon, 01 Feb 2010 00:17:57 -0800 (PST) Date: Mon, 1 Feb 2010 16:17:57 +0800 Message-ID: Subject: cavium reference board, sdk 1.9.0 and the latest linux kernel From: Zhuang Yuyao To: David Daney Cc: linux-mips@linux-mips.org Content-Type: multipart/mixed; boundary=00504502ba4f6e361a047e859fe4 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25801 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mlistz@gmail.com Precedence: bulk X-list: linux-mips --00504502ba4f6e361a047e859fe4 Content-Type: text/plain; charset=ISO-8859-1 Hi, Currently I am working on a cavium CN56xx reference board using cavium sdk 1.9.0. the linux kernel bundled in sdk is 2.6.27. which works fine on the reference board. but while i am trying to use the latest linux kernel, ie. 2.6.31, 2.6.32, 2.6.33-rc4, i encountered the same problem: "Kernel panic - not syncing: Attempted to kill init!". here is the boot log (initramfs is compiled into the kernel, the linux config file is attached to this mail): Bytes transferred = 66099593 (3f09989 hex), 1965 Kbytes/sec argv[2]: root=/dev/ram0 argv[3]: rw argv[4]: panic=1 argv[5]: init=/linuxrc argv[6]: coremask=0xfff argv[7]: console=ttyS1,115200 ELF file is 64 bit Attempting to allocate memory for ELF segment: addr: 0xffffffff81100000 (adjusted to: 0x0000000001100000), size 0x25e6e30 Allocated memory for ELF segment: addr: 0xffffffff81100000, size 0x25e6e30 Processing PHDR 0 Loading 25b5a80 bytes at ffffffff81100000 Clearing 313b0 bytes at ffffffff836b5a80 ## Loading Linux kernel with entry point: 0xffffffff81105f10 ... Bootloader: Done loading app on coremask: 0xfff Linux version 2.6.31 (root@R710) (gcc version 4.3.3 (Cavium Networks Version: 1_9_0 build 80) ) #17 SMP PREEMPT Tue Jan 19 01:19:220 CVMSEG size: 2 cache lines (256 bytes) CPU revision is: 000d0409 (Cavium Octeon) Checking for the multiply/shift bug... no. Checking for the daddiu bug... no. Determined physical RAM map: memory: 00000000022ce000 @ 00000000013e8000 (usable) memory: 000000000c800000 @ 0000000003700000 (usable) memory: 0000000011800000 @ 0000000020000000 (usable) Wasting 326144 bytes for tracking 5096 unused pages Initrd not found or empty - disabling initrd Zone PFN ranges: Normal 0x000013e8 -> 0x00031800 Movable zone start PFN for each node early_node_map[3] active PFN ranges 0: 0x000013e8 -> 0x000036b6 0: 0x00003700 -> 0x0000ff00 0: 0x00020000 -> 0x00031800 Built 1 zonelists in Zone order, mobility grouping on. Total pages: 128701 Kernel command line: bootoctlinux 0x20000000 root=/dev/ram0 rw panic=1 init=/linuxrc coremask=0xfff console=ttyS1,115200 PID hash table entries: 2048 (order: 11, 16384 bytes) Dentry cache hash table entries: 65536 (order: 7, 524288 bytes) Inode-cache hash table entries: 32768 (order: 6, 262144 bytes) Primary instruction cache 32kB, virtually tagged, 4 way, 64 sets, linesize 128 bytes. Primary data cache 16kB, 64-way, 2 sets, linesize 128 bytes. Memory: 477572k/527160k available (2185k kernel code, 49004k reserved, 788k data, 35640k init, 0k highmem) NR_IRQS:152 console [ttyS1] enabled Calibrating delay using timer specific routine.. 1602.37 BogoMIPS (lpj=3204755) Security Framework initialized Mount-cache hash table entries: 256 Checking for the daddi bug... no. SMP: Booting CPU01 (CoreId 1)... CPU revision is: 000d0409 (Cavium Octeon) Calibrating delay using timer specific routine.. 1601.69 BogoMIPS (lpj=3203395) SMP: Booting CPU02 (CoreId 2)... CPU revision is: 000d0409 (Cavium Octeon) Calibrating delay using timer specific routine.. 1601.80 BogoMIPS (lpj=3203612) SMP: Booting CPU03 (CoreId 3)... CPU revision is: 000d0409 (Cavium Octeon) Calibrating delay using timer specific routine.. 1601.68 BogoMIPS (lpj=3203378) SMP: Booting CPU04 (CoreId 4)... CPU revision is: 000d0409 (Cavium Octeon) Calibrating delay using timer specific routine.. 1601.80 BogoMIPS (lpj=3203610) SMP: Booting CPU05 (CoreId 5)... CPU revision is: 000d0409 (Cavium Octeon) Calibrating delay using timer specific routine.. 1601.68 BogoMIPS (lpj=3203375) SMP: Booting CPU06 (CoreId 6)... CPU revision is: 000d0409 (Cavium Octeon) Calibrating delay using timer specific routine.. 1601.80 BogoMIPS (lpj=3203606) SMP: Booting CPU07 (CoreId 7)... CPU revision is: 000d0409 (Cavium Octeon) Calibrating delay using timer specific routine.. 1601.68 BogoMIPS (lpj=3203376) SMP: Booting CPU08 (CoreId 8)... CPU revision is: 000d0409 (Cavium Octeon) Calibrating delay using timer specific routine.. 1601.80 BogoMIPS (lpj=3203607) SMP: Booting CPU09 (CoreId 9)... CPU revision is: 000d0409 (Cavium Octeon) Calibrating delay using timer specific routine.. 1601.68 BogoMIPS (lpj=3203376) SMP: Booting CPU10 (CoreId 10)... CPU revision is: 000d0409 (Cavium Octeon) Calibrating delay using timer specific routine.. 1601.80 BogoMIPS (lpj=3203605) SMP: Booting CPU11 (CoreId 11)... CPU revision is: 000d0409 (Cavium Octeon) Calibrating delay using timer specific routine.. 1601.61 BogoMIPS (lpj=3203229) Brought up 12 CPUs NET: Registered protocol family 16 bio: create slab at 0 NET: Registered protocol family 2 IP route cache hash table entries: 16384 (order: 5, 131072 bytes) TCP established hash table entries: 65536 (order: 8, 1048576 bytes) TCP bind hash table entries: 65536 (order: 9, 2097152 bytes) TCP: Hash tables configured (established 65536 bind 65536) TCP reno registered NET: Registered protocol family 1 msgmni has been set to 933 alg: No test for stdrng (krng) io scheduler noop registered io scheduler anticipatory registered io scheduler deadline registered io scheduler cfq registered (default) Serial: 8250/16550 driver, 2 ports, IRQ sharing disabled serial8250.0: ttyS1 at MMIO 0x1180000000c00 (irq = 59) is a OCTEON brd: module loaded loop: module loaded TCP cubic registered NET: Registered protocol family 17 Bootbus flash: Setting flash for 64MB flash at 0x1bc00000 drivers/mtd/chips/cfi_probe.c:166 phys_mapped_flash: Found 1 x16 devices at 0x0 in 16-bit bank Amd/Fujitsu Extended Query Table at 0x0040 phys_mapped_flash: CFI does not contain boot bank location. Assuming top. number of CFI chips: 1 cfi_cmdset_0002: Disabling erase-suspend-program due to code brokenness. Creating 4 MTD partitions on "phys_mapped_flash": 0x000000080000-0x000000680000 : "O60H BOOT" 0x000000680000-0x000003f80000 : "O60H ROOT" 0x000000000000-0x000000080000 : "U-BOOT" 0x000003f80000-0x000004000000 : "U-BOOT(env)" Freeing unused kernel memory: 35640k freed Kernel panic - not syncing: Attempted to kill init! Rebooting in 1 seconds.. U-Boot 1.1.1 (Development build) (Build time: May 25 2009 - 16:32:17) EBH5600 board revision major:1, minor:0 OCTEON CN5650-NSP pass 2.1, Core clock: 800 MHz, DDR clock: 400 MHz (800 Mhz data rate) Warning: Board descriptor tuple not found in eeprom, using defaults DRAM: 4096 MB Flash: 64 MB Clearing DRAM........ done BIST check passed. My question is, what is the current status of octeon plus cn56xx support in official linux kernel release? Is cavium cn56xx reference board supported? If the answer is 'yes', how can I make the latest kernel and boot it successfully on the reference board? Thanks very much. I will be glad to provide more information if required. Zhuang Yuyao --00504502ba4f6e361a047e859fe4 Content-Type: application/octet-stream; name="cavium.config" Content-Disposition: attachment; filename="cavium.config" Content-Transfer-Encoding: base64 X-Attachment-Id: f_g54zbal40 IwojIEF1dG9tYXRpY2FsbHkgZ2VuZXJhdGVkIG1ha2UgY29uZmlnOiBkb24ndCBlZGl0CiMgTGlu dXgga2VybmVsIHZlcnNpb246IDIuNi4zMQojIFR1ZSBKYW4gMTkgMDE6MTg6NDMgMjAxMAojCkNP TkZJR19NSVBTPXkKCiMKIyBNYWNoaW5lIHNlbGVjdGlvbgojCiMgQ09ORklHX01BQ0hfQUxDSEVN WSBpcyBub3Qgc2V0CiMgQ09ORklHX0FSNyBpcyBub3Qgc2V0CiMgQ09ORklHX0JBU0xFUl9FWENJ VEUgaXMgbm90IHNldAojIENPTkZJR19CQ000N1hYIGlzIG5vdCBzZXQKIyBDT05GSUdfTUlQU19D T0JBTFQgaXMgbm90IHNldAojIENPTkZJR19NQUNIX0RFQ1NUQVRJT04gaXMgbm90IHNldAojIENP TkZJR19NQUNIX0pBWlogaXMgbm90IHNldAojIENPTkZJR19MQVNBVCBpcyBub3Qgc2V0CiMgQ09O RklHX0xFTU9URV9GVUxPTkcgaXMgbm90IHNldAojIENPTkZJR19NSVBTX01BTFRBIGlzIG5vdCBz ZXQKIyBDT05GSUdfTUlQU19TSU0gaXMgbm90IHNldAojIENPTkZJR19ORUNfTUFSS0VJTlMgaXMg bm90IHNldAojIENPTkZJR19NQUNIX1ZSNDFYWCBpcyBub3Qgc2V0CiMgQ09ORklHX05YUF9TVEIy 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SMTP id 1so899799ewy.26 for ; Mon, 01 Feb 2010 00:51:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:sender:from:organization:to :subject:date:user-agent:cc:references:in-reply-to:mime-version :content-type:content-transfer-encoding:message-id; bh=M0DqParK0kgfzBaPKu4J832ECEtSE9PCeCem025Ykuo=; b=FSSIOM+OdDde8Ru2UsoAKW0++xNHVU7cQq1V2bApoDp/Zv8B+O0H+mBu0wkEpjhstb xGtAcXWMTmGtQvG2O6bE3k1tbCD17Sa6ExVnsLbLEI0s1+rViVlYrQ+K4MHnN22KdkX0 25Gz2K8OLam1gaMqxw9gunlfammLFlJgfX1uw= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:from:organization:to:subject:date:user-agent:cc:references :in-reply-to:mime-version:content-type:content-transfer-encoding :message-id; b=Vjut6yNUvlwEb6l42fMUmaive3JdeTcirz4yV1ifRi3fj7qxAi/5pBMNqpG5stwSxX 1lmLXYEcKobkCGKucugF6dEZGlLvaWMMrpHiJAOhhQZlVxU5/1QoZeZ6j05ldrUEkyzM ZMJvFpgRvkW6ouDhlMJMHNzB4hizcQ8oiHbXs= Received: by 10.213.109.205 with SMTP id k13mr1754126ebp.44.1265014314505; Mon, 01 Feb 2010 00:51:54 -0800 (PST) Received: from flexo.localnet (bobafett.staff.proxad.net [213.228.1.121]) by mx.google.com with ESMTPS id 15sm3488593ewy.12.2010.02.01.00.51.52 (version=SSLv3 cipher=RC4-MD5); Mon, 01 Feb 2010 00:51:53 -0800 (PST) From: Florian Fainelli Organization: OpenWrt To: Alexander Clouter Subject: Re: [PATCH 0/3] AR7 cleanups and fixes Date: Mon, 1 Feb 2010 09:51:27 +0100 User-Agent: KMail/1.12.2 (Linux/2.6.31-17-server; KDE/4.3.2; x86_64; ; ) Cc: linux-mips@linux-mips.org References: <0p2h37-ch6.ln1@chipmunk.wormnet.eu> In-Reply-To: <0p2h37-ch6.ln1@chipmunk.wormnet.eu> MIME-Version: 1.0 Content-Type: Text/Plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <201002010951.27270.florian@openwrt.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25802 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips Hi Alexander, On Sunday 31 January 2010 20:37:36 Alexander Clouter wrote: > A number of patches I have already run by Florian Fainelli and now that > the GPIO[1] and CLK[2] patches are in, I can submit my generic AR7 > cleanup and fixup patches: > 1. whitespace cleanups > 2. fix usb slave mem range mistype > 3. make ar7_register_devices much more durable > > So these patches should apply to the linux-queue...hopefully. Feel free to add my Acked-by, on those 3 patches once you addresses Wu's comments. Thank you. -- Regards, Florian From wuzhangjin@gmail.com Mon Feb 1 09:57:55 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 01 Feb 2010 09:58:00 +0100 (CET) Received: from mail-iw0-f183.google.com ([209.85.223.183]:34447 "EHLO mail-iw0-f183.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491929Ab0BAI5z (ORCPT ); Mon, 1 Feb 2010 09:57:55 +0100 Received: by iwn13 with SMTP id 13so333049iwn.20 for ; Mon, 01 Feb 2010 00:57:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:subject:from:reply-to:to:cc :in-reply-to:references:content-type:organization:date:message-id :mime-version:x-mailer:content-transfer-encoding; bh=59ImsTZtIjmUtc5MOMHVgajKTh+tFGxPZgyZ/hFCoY4=; b=tHYDmi3w1fWJ/vPXtC39wKoFYgnOdrq6GgJydV5QqtVNxlrlhh7w4FTplMI11MmotP GYUnnXAg1uZiYKFw4tF/T+xbNBUgzdmtyRpzP7uDgTZBit/NEWzjF7TW+UcNnBO1Za/H uXlLrhUxJO5MUQO1DjJqIyvqivAUuN1l6tKjM= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=subject:from:reply-to:to:cc:in-reply-to:references:content-type :organization:date:message-id:mime-version:x-mailer :content-transfer-encoding; b=n8Cpi60LANC1qrCwOezUfWXJYjKeFrWe1UMIEuMb0nC4AoJepWJJDnSJN+srTGF60p IjOIk7UuQqCeCBsbLM7o5pyANGb6C+l86EUeVsjfvbq6arIb8Fomj57A1zdPkezRv07O JMf+QaYrIOoPzoRxH/HDFux4ldL8uiZLdNrgM= Received: by 10.231.169.67 with SMTP id x3mr3133804iby.76.1265014668736; Mon, 01 Feb 2010 00:57:48 -0800 (PST) Received: from ?192.168.2.212? ([202.201.14.140]) by mx.google.com with ESMTPS id 21sm5255359iwn.14.2010.02.01.00.57.45 (version=TLSv1/SSLv3 cipher=RC4-MD5); Mon, 01 Feb 2010 00:57:47 -0800 (PST) Subject: Re: [PATCH] powertv: Fix support for timer interrupts when using >64 external IRQs From: Wu Zhangjin Reply-To: wuzhangjin@gmail.com To: mbizon@freebox.fr Cc: David VomLehn , linux-mips@linux-mips.org, ralf@linux-mips.org In-Reply-To: <1264864218.32192.1.camel@sakura.staff.proxad.net> References: <20091222014922.GA30164@dvomlehn-lnx2.corp.sa.net> <1264864218.32192.1.camel@sakura.staff.proxad.net> Content-Type: text/plain; charset="UTF-8" Organization: DSLab, Lanzhou University, China Date: Mon, 01 Feb 2010 16:47:56 +0800 Message-ID: <1265014076.14427.1.camel@falcon> Mime-Version: 1.0 X-Mailer: Evolution 2.28.2 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25803 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips On Sat, 2010-01-30 at 16:10 +0100, Maxime Bizon wrote: > On Mon, 2009-12-21 at 17:49 -0800, David VomLehn wrote: > > Hi, > > > if (cpu_has_mips_r2) { > > - cp0_compare_irq = (read_c0_intctl() >> 29) & 7; > > - cp0_perfcount_irq = (read_c0_intctl() >> 26) & 7; > > + cp0_compare_irq_shift = CAUSEB_TI - CAUSEB_IP; > > + cp0_compare_irq = (read_c0_intctl() >> INTCTLB_IPTI) & 7; > > + cp0_perfcount_irq = (read_c0_intctl() >> INTCTLB_IPPCI) & 7; > > This patch breaks at least bcm63xx, because cp0_compare_irq_shift is not > initialized when cpu_has_mips_r2 is false. Yes, that patch have broken the CEVT_R4K support in the archs whose cpu_has_mips_r2 is false. I will send a piece of patch to fix it. Thanks & Regards, Wu Zhangjin From wuzhangjin@gmail.com Mon Feb 1 10:17:11 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 01 Feb 2010 10:17:15 +0100 (CET) Received: from mail-iw0-f183.google.com ([209.85.223.183]:44210 "EHLO mail-iw0-f183.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491988Ab0BAJRL (ORCPT ); Mon, 1 Feb 2010 10:17:11 +0100 Received: by iwn13 with SMTP id 13so345223iwn.20 for ; Mon, 01 Feb 2010 01:17:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer; bh=q29LBEgUBABxQbj20SsOUBh/SZYhpdRH20sJxLf9MmQ=; b=ECulLcDcCgyGZkpR3x3ao1Z115OdkJCSX+kFprpFHEYU4S5apvaVtUeRFxDrnsjjHy axL6MX1KcgQmA+dGzNwpQWCs4Zgzqjq3eS2yq3JtyB4vlJqQIHF7Ug5r5IFQRBtR9ACJ 3X+s23HG4/stBEsH6cFalhtf3T7aY4Zuqvn+A= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer; b=iq+EpXwmUGFfunV5d0+29ZMhdJoyUgiSp8j51jrhRssumTyyphKYOMln6+5piSA976 tGzTZx/1gZ7F8712GFC7gk+0FCBYKrPofsGqiawSCr4839JVqcef9krOA1Ffa9Nb1xeH QQ4Xxa0Si9qxVQdhY9aPmo0ahJPNSVc9S277Y= Received: by 10.231.145.70 with SMTP id c6mr1080716ibv.36.1265015824434; Mon, 01 Feb 2010 01:17:04 -0800 (PST) Received: from localhost.localdomain ([202.201.14.140]) by mx.google.com with ESMTPS id 23sm5287272iwn.15.2010.02.01.01.17.01 (version=TLSv1/SSLv3 cipher=RC4-MD5); Mon, 01 Feb 2010 01:17:03 -0800 (PST) From: Wu Zhangjin To: ralf@linux-mips.org Cc: David VomLehn , mbizon@freebox.fr, linux-mips@linux-mips.org, Wu Zhangjin Subject: [PATCH urgent] MIPS: Fixup of the r4k timer Date: Mon, 1 Feb 2010 17:10:55 +0800 Message-Id: <1265015455-32553-1-git-send-email-wuzhangjin@gmail.com> X-Mailer: git-send-email 1.6.6 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25804 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips From: Wu Zhangjin As reported by Maxime Bizon, the commit "MIPS: PowerTV: Fix support for timer interrupts with > 64 external IRQs" have broken the r4k timer since it didn't initialize the cp0_compare_irq_shift variable used in c0_compare_int_pending() on the architectures whose cpu_has_mips_r2 is false. This patch fixes it via initializing the cp0_compare_irq_shift as the cp0_compare_irq used in the old c0_compare_int_pending(). Reported-by: Maxime Bizon Signed-off-by: Wu Zhangjin --- arch/mips/kernel/traps.c | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index 338dfe8..31b204b 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -1501,6 +1501,7 @@ void __cpuinit per_cpu_trap_init(void) cp0_perfcount_irq = -1; } else { cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ; + cp0_compare_irq_shift = cp0_compare_irq; cp0_perfcount_irq = -1; } -- 1.6.6 From f.fainelli@gmail.com Mon Feb 1 10:28:09 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 01 Feb 2010 10:28:14 +0100 (CET) Received: from mail-ew0-f209.google.com ([209.85.219.209]:60368 "EHLO mail-ew0-f209.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491968Ab0BAJ2J (ORCPT ); Mon, 1 Feb 2010 10:28:09 +0100 Received: by ewy1 with SMTP id 1so934305ewy.26 for ; Mon, 01 Feb 2010 01:28:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:sender:from:date:subject :mime-version:x-uid:x-length:organization:to:cc:content-type :content-transfer-encoding:message-id; bh=5TKzJZl21hUDpkOFhz206kqhzn2qGGreMr/Xg/3Ki0M=; b=aKmb5pTcq2Pw8XU3WWPQkchjFHpVQjdkkcGnTk3FzAPQ1kb8hefdLwhMSEWPsnCMGJ /pFOW2oGbnvZjRjDeioRep4iUpZWkSOraIE/O+zw8dJlJYapwOGhLuKMnP8SmQl3QujY 7ri69UggtPJ8mWkEqWh/7jGTsaxNxcd+NkCD8= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:from:date:subject:mime-version:x-uid:x-length:organization :to:cc:content-type:content-transfer-encoding:message-id; b=fO3VBh6txjCRm+i7hg3ntdD3awcqn/ktstXRmPIFOu2vgo9reRxQAj4g5Lj6U7BRaU z/OPTR4hc72+l7QQC6rDUtfpiDu8aZoG7fwGX0rUlmxSeIfqdFCgmw8K5p1hMYaVYoNF oUtrvZvx52IRVBAiBoi/sBYGh7zAwSu7VnwV8= Received: by 10.213.66.5 with SMTP id l5mr4107762ebi.15.1265016483381; Mon, 01 Feb 2010 01:28:03 -0800 (PST) Received: from flexo.localnet (bobafett.staff.proxad.net [213.228.1.121]) by mx.google.com with ESMTPS id 16sm3513328ewy.10.2010.02.01.01.28.02 (version=SSLv3 cipher=RC4-MD5); Mon, 01 Feb 2010 01:28:02 -0800 (PST) From: Florian Fainelli Date: Mon, 1 Feb 2010 10:27:37 +0100 Subject: [PATCH urgent] MIPS: fix micro-assembly overflow in set_except_vector MIME-Version: 1.0 X-UID: 166 X-Length: 1852 Organization: OpenWrt To: Ralf Baechle Cc: linux-mips@linux-mips.org Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <201002011027.37521.florian@openwrt.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25805 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips Commit 24a6d9866c5f15ba7e5b14dc17be4b6edba21d0e broke the installation of handlers for boards which have their handlers above a 1 << 26 address. Fix this by making sure that jump_mask does not excess 0xfc000000 and add the missing ~ operator to jump_mask when jumping to the handler address. Reported-by: Maxime Bizon Signed-off-by: Florian Fainelli --- diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index 7693929..40d94c3 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -1279,11 +1279,11 @@ void __init *set_except_vector(int n, void *addr) exception_handlers[n] = handler; if (n == 0 && cpu_has_divec) { - unsigned long jump_mask = ~((1 << 28) - 1); + unsigned long jump_mask = ~((1 << 26) - 1); u32 *buf = (u32 *)(ebase + 0x200); unsigned int k0 = 26; if ((handler & jump_mask) == ((ebase + 0x200) & jump_mask)) { - uasm_i_j(&buf, handler & jump_mask); + uasm_i_j(&buf, handler & ~jump_mask); uasm_i_nop(&buf); } else { UASM_i_LA(&buf, k0, handler); From sgi-linux-mips@m.gmane.org Mon Feb 1 11:08:38 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 01 Feb 2010 11:08:43 +0100 (CET) Received: from lo.gmane.org ([80.91.229.12]:56645 "EHLO lo.gmane.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492016Ab0BAKIh (ORCPT ); Mon, 1 Feb 2010 11:08:37 +0100 Received: from list by lo.gmane.org with local (Exim 4.69) (envelope-from ) id 1NbtCr-0007lS-8i for linux-mips@linux-mips.org; Mon, 01 Feb 2010 11:08:33 +0100 Received: from chipmunk.wormnet.eu ([195.195.131.226]) by main.gmane.org with esmtp (Gmexim 0.1 (Debian)) id 1AlnuQ-0007hv-00 for ; Mon, 01 Feb 2010 11:08:33 +0100 Received: from alex by chipmunk.wormnet.eu with local (Gmexim 0.1 (Debian)) id 1AlnuQ-0007hv-00 for ; Mon, 01 Feb 2010 11:08:33 +0100 X-Injected-Via-Gmane: http://gmane.org/ To: linux-mips@linux-mips.org From: Alexander Clouter Subject: Re: [PATCH 1/3] MIPS: AR7 whitespace hacking Date: Mon, 1 Feb 2010 10:03:45 +0000 Lines: 53 Message-ID: <1hli37-4t9.ln1@chipmunk.wormnet.eu> References: <1265005758.31984.8.camel@falcon> X-Complaints-To: usenet@ger.gmane.org X-Gmane-NNTP-Posting-Host: chipmunk.wormnet.eu User-Agent: tin/1.9.3-20080506 ("Dalintober") (UNIX) (Linux/2.6.26-2-sparc64-smp (sparc64)) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25806 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: alex@digriz.org.uk Precedence: bulk X-list: linux-mips Wu Zhangjin wrote: > >> +/***************************************************************************** >> + * VLYNQ Bus >> + ****************************************************************************/ > > Why not simply use: > > /* VLYNQ Bus */ > > You have deleted lots of whitespaces, but added more *. > "good enough for ARM[1]" :) Compromise on this instead? ---- /* * VLYNQ Bus */ ---- >> @@ -70,7 +71,6 @@ console_initcall(ar7_init_console); >> * Initializes basic routines and structures pointers, memory size (as >> * given by the bios and saves the command line. >> */ >> - >> void __init plat_mem_setup(void) >> { >> unsigned long io_base; >> @@ -88,6 +88,5 @@ void __init plat_mem_setup(void) >> prom_meminit(); >> >> printk(KERN_INFO "%s, ID: 0x%04x, Revision: 0x%02x\n", >> - get_system_type(), >> - ar7_chip_id(), ar7_chip_rev()); >> + get_system_type(), ar7_chip_id(), ar7_chip_rev()); >> } > > Perhaps you can use pr_info() instead of printk(KERN_INFO) too, of > course, if there are more printk(KERN_...), you can replace them by > pr_xxx defined in include/linux/kernel.h > I'm not responsible for that printk()...although the others I will admit to :) I'll roll out a replacement later today hopefully. Cheers -- Alexander Clouter .sigmonster says: Vini, vidi, Linux! -- Unknown source From wuzhangjin@gmail.com Mon Feb 1 12:19:25 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 01 Feb 2010 12:19:29 +0100 (CET) Received: from mail-px0-f181.google.com ([209.85.216.181]:40335 "EHLO mail-px0-f181.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492078Ab0BALTZ (ORCPT ); Mon, 1 Feb 2010 12:19:25 +0100 Received: by pxi11 with SMTP id 11so4007532pxi.22 for ; Mon, 01 Feb 2010 03:19:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer; bh=t7okXqjZNkmvJrjNBkLmk7wO3rQO1Zp6jlZQvNd/cBQ=; b=cv5B5RQGxlMhNUOP0oa49ULuHAc4lKqVrkRkc2krTRK/UvDF6yiHwHOeIFVW1A4/Nj D+cy/SikJIML7QGX+yeSFy5zhftnyog4Qs2hLKI5HLLKXpP0nZPXB3njdS7jFgEoZETc OuDZIwHXp5kx1gdmJaAKJD0v6x1FL/qo2jm9s= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer; b=kaTbFBWIvwub4beQVwZQF+D7+/1aWpEaILs4NBWJ2c5OmVYgqavhxL5pSZlIMzHj3r BLrtwS7npklGrGMM8mK4QzdxgmBxHi4dQC3rUm8edwIsSgb8z/sIPMDRCXdWsj1De5j9 0FsjGnn9Vrp3IYpZ/hUW5zDtkeWXRk8t9kG+A= Received: by 10.142.2.9 with SMTP id 9mr2964481wfb.290.1265023157082; Mon, 01 Feb 2010 03:19:17 -0800 (PST) Received: from localhost.localdomain ([202.201.14.140]) by mx.google.com with ESMTPS id 22sm561769pzk.10.2010.02.01.03.19.14 (version=TLSv1/SSLv3 cipher=RC4-MD5); Mon, 01 Feb 2010 03:19:16 -0800 (PST) From: Wu Zhangjin To: Ralf Baechle Cc: David Daney , "linux-mips@linux-mips.org" , Wu Zhangjin Subject: [PATCH -queue 1/3] MIPS: add a common mips_sched_clock() Date: Mon, 1 Feb 2010 19:13:10 +0800 Message-Id: <198fc72d92823547c9be132616fd2ebc2091ff39.1265022593.git.wuzhangjin@gmail.com> X-Mailer: git-send-email 1.6.6 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25807 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips From: Wu Zhangjin Because the high resolution sched_clock() for r4k has the same overflow problem and solution mentioned in "MIPS: Octeon: Use non-overflowing arithmetic in sched_clock". "With typical mult and shift values, the calculation for Octeon's sched_clock overflows when using 64-bit arithmetic. Use 128-bit calculations instead." To reduce the duplication, This patch abstracts the solution into an inline funciton mips_sched_clock() into arch/mips/include/asm/time.h from arch/mips/cavium-octeon/csrc-octeon.c. Two patches for Cavium and R4K will be sent out respectively to use this common function. Signed-off-by: Wu Zhangjin --- arch/mips/include/asm/time.h | 30 ++++++++++++++++++++++++++++++ 1 files changed, 30 insertions(+), 0 deletions(-) diff --git a/arch/mips/include/asm/time.h b/arch/mips/include/asm/time.h index c7f1bfe..f7bd5ce 100644 --- a/arch/mips/include/asm/time.h +++ b/arch/mips/include/asm/time.h @@ -96,4 +96,34 @@ static inline void clockevent_set_clock(struct clock_event_device *cd, clockevents_calc_mult_shift(cd, clock, 4); } +static inline unsigned long long mips_sched_clock(struct clocksource *cs, u64 cnt) +{ + /* 64-bit arithmatic can overflow, so use 128-bit. */ +#if (__GNUC__ < 4) || ((__GNUC__ == 4) && (__GNUC_MINOR__ <= 3)) + u64 t1, t2, t3; + unsigned long long rv; + u64 mult = cs->mult; + u64 shift = cs->shift; + + asm ( + "dmultu\t%[cnt],%[mult]\n\t" + "nor\t%[t1],$0,%[shift]\n\t" + "mfhi\t%[t2]\n\t" + "mflo\t%[t3]\n\t" + "dsll\t%[t2],%[t2],1\n\t" + "dsrlv\t%[rv],%[t3],%[shift]\n\t" + "dsllv\t%[t1],%[t2],%[t1]\n\t" + "or\t%[rv],%[t1],%[rv]\n\t" + : [rv] "=&r" (rv), [t1] "=&r" (t1), [t2] "=&r" (t2), [t3] "=&r" (t3) + : [cnt] "r" (cnt), [mult] "r" (mult), [shift] "r" (shift) + : "hi", "lo"); + return rv; +#else /* GCC > 4.3 do it the easy way. */ + unsigned int __attribute__((mode(TI))) t = cnt; + + t = (t * cs->mult) >> cs->shift; + return (unsigned long long)t; +#endif +} + #endif /* _ASM_TIME_H */ -- 1.6.6 From wuzhangjin@gmail.com Mon Feb 1 12:19:48 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 01 Feb 2010 12:19:52 +0100 (CET) Received: from mail-px0-f181.google.com ([209.85.216.181]:58984 "EHLO mail-px0-f181.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492107Ab0BALT1 (ORCPT ); Mon, 1 Feb 2010 12:19:27 +0100 Received: by pxi11 with SMTP id 11so4007578pxi.22 for ; Mon, 01 Feb 2010 03:19:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer:in-reply-to:references:in-reply-to:references; bh=Taw54d6HxZCWf19QELob/RZAiSAVVMVmABgwKW8FVEE=; b=lE4WkeSwsMfbBF6GO64ZQIAoahNJgJYTODhsaV68Mn3KP54UrrJ6s9c2rgbnHMtr0p P3pQHzRYtF8UpYu4ownl9KlUctTN8zFc7Pxy7WyJgHxpK18DXZ92vTP0WqPtaSHOHnza OS00W6tACe2e1SwKv6p6q32ioFh61hORCDhxQ= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; b=e1h4ICdA4/fY9xeb08+ONW/v3woj3HBve0ITTPeSYWo7f9JbtZ8jGNJOx1+GZqR+vT 0PK0GR7PD9AMK8mNMIv4kINVGy9EyIocXHwRkiDrfczM3SzihyyINuHBDv0ccEZhEemR 7a5ColKLW+mhhQemKxtJgVAmGjzGZhUziZ5AQ= Received: by 10.142.118.2 with SMTP id q2mr2997045wfc.292.1265023160498; Mon, 01 Feb 2010 03:19:20 -0800 (PST) Received: from localhost.localdomain ([202.201.14.140]) by mx.google.com with ESMTPS id 22sm561769pzk.10.2010.02.01.03.19.18 (version=TLSv1/SSLv3 cipher=RC4-MD5); Mon, 01 Feb 2010 03:19:19 -0800 (PST) From: Wu Zhangjin To: Ralf Baechle Cc: David Daney , "linux-mips@linux-mips.org" , Wu Zhangjin Subject: [PATCH -queue 2/3] MIPS: cavium-octeon: rewrite the sched_clock() based on mips_sched_clock() Date: Mon, 1 Feb 2010 19:13:11 +0800 Message-Id: X-Mailer: git-send-email 1.6.6 In-Reply-To: <198fc72d92823547c9be132616fd2ebc2091ff39.1265022593.git.wuzhangjin@gmail.com> References: <198fc72d92823547c9be132616fd2ebc2091ff39.1265022593.git.wuzhangjin@gmail.com> In-Reply-To: <198fc72d92823547c9be132616fd2ebc2091ff39.1265022593.git.wuzhangjin@gmail.com> References: <198fc72d92823547c9be132616fd2ebc2091ff39.1265022593.git.wuzhangjin@gmail.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25808 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips From: Wu Zhangjin The commit "MIPS: add a common mips_sched_clock()" have abstracted the solution of the 64bit calculation's overflow problem into a common mips_sched_clock() function in arch/mips/include/asm/time.h, This patch just rewrites the sched_clock() for cavium-octeon on it. Signed-off-by: Wu Zhangjin --- arch/mips/cavium-octeon/csrc-octeon.c | 27 +-------------------------- 1 files changed, 1 insertions(+), 26 deletions(-) diff --git a/arch/mips/cavium-octeon/csrc-octeon.c b/arch/mips/cavium-octeon/csrc-octeon.c index 0bf4bbe..53b1c32 100644 --- a/arch/mips/cavium-octeon/csrc-octeon.c +++ b/arch/mips/cavium-octeon/csrc-octeon.c @@ -52,34 +52,9 @@ static struct clocksource clocksource_mips = { unsigned long long notrace sched_clock(void) { - /* 64-bit arithmatic can overflow, so use 128-bit. */ -#if (__GNUC__ < 4) || ((__GNUC__ == 4) && (__GNUC_MINOR__ <= 3)) - u64 t1, t2, t3; - unsigned long long rv; - u64 mult = clocksource_mips.mult; - u64 shift = clocksource_mips.shift; u64 cnt = read_c0_cvmcount(); - asm ( - "dmultu\t%[cnt],%[mult]\n\t" - "nor\t%[t1],$0,%[shift]\n\t" - "mfhi\t%[t2]\n\t" - "mflo\t%[t3]\n\t" - "dsll\t%[t2],%[t2],1\n\t" - "dsrlv\t%[rv],%[t3],%[shift]\n\t" - "dsllv\t%[t1],%[t2],%[t1]\n\t" - "or\t%[rv],%[t1],%[rv]\n\t" - : [rv] "=&r" (rv), [t1] "=&r" (t1), [t2] "=&r" (t2), [t3] "=&r" (t3) - : [cnt] "r" (cnt), [mult] "r" (mult), [shift] "r" (shift) - : "hi", "lo"); - return rv; -#else - /* GCC > 4.3 do it the easy way. */ - unsigned int __attribute__((mode(TI))) t; - t = read_c0_cvmcount(); - t = t * clocksource_mips.mult; - return (unsigned long long)(t >> clocksource_mips.shift); -#endif + return mips_sched_clock(&clocksource_mips, cnt); } void __init plat_time_init(void) -- 1.6.6 From wuzhangjin@gmail.com Mon Feb 1 12:20:11 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 01 Feb 2010 12:20:18 +0100 (CET) Received: from mail-px0-f181.google.com ([209.85.216.181]:49507 "EHLO mail-px0-f181.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492127Ab0BALTb (ORCPT ); Mon, 1 Feb 2010 12:19:31 +0100 Received: by pxi11 with SMTP id 11so4007616pxi.22 for ; Mon, 01 Feb 2010 03:19:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer:in-reply-to:references:in-reply-to:references; bh=neHg06tC7/Qo8R1SH2eZh9Dd5zAxpZcWF7Y/ymje6uc=; b=f/wGYH9OR+AmAJ3Nti3OMUgk0EE2stXluPoOkSQCQa6TmozQkpj3jld6s0Tk89qJHp 0FR1W+xM+sdrN1ai9TJ0x+7i+lTxIyX4zOzXvhKea6wuLuSEQe6AQtX1ULtXNLNxgdHF CoI4O7F3bNk44LcjPo5fTE4dSFWnTCDuebPCA= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; b=dKAFXPsRvrf55JxOYqZOJE6qu6jVJTnSveHUAvmcSPBgz92yHRzzZBO+zYypKicC/t Vk/F/vwiE/2oDyjSfZeKGi0UjioouBtSsas4+4DVcoLaCN+k8ptwoR6f751R+na/nwC/ YOH5bfwNv3qI5YwkljgnFVtD9Gr5of1c1JQZQ= Received: by 10.142.60.4 with SMTP id i4mr3003776wfa.296.1265023163482; Mon, 01 Feb 2010 03:19:23 -0800 (PST) Received: from localhost.localdomain ([202.201.14.140]) by mx.google.com with ESMTPS id 22sm561769pzk.10.2010.02.01.03.19.21 (version=TLSv1/SSLv3 cipher=RC4-MD5); Mon, 01 Feb 2010 03:19:23 -0800 (PST) From: Wu Zhangjin To: Ralf Baechle Cc: David Daney , "linux-mips@linux-mips.org" , Wu Zhangjin Subject: [PATCH -queue v8 3/3] MIPS: r4k: Add a high resolution sched_clock() Date: Mon, 1 Feb 2010 19:13:12 +0800 Message-Id: <9b83e460caf96b638c3dec30a2d49bb445797d28.1265022593.git.wuzhangjin@gmail.com> X-Mailer: git-send-email 1.6.6 In-Reply-To: References: <198fc72d92823547c9be132616fd2ebc2091ff39.1265022593.git.wuzhangjin@gmail.com> In-Reply-To: <198fc72d92823547c9be132616fd2ebc2091ff39.1265022593.git.wuzhangjin@gmail.com> References: <198fc72d92823547c9be132616fd2ebc2091ff39.1265022593.git.wuzhangjin@gmail.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25809 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips From: Wu Zhangjin (v7 -> v8: O Make it works with the exisiting clocksource_mips.mult, clocksource_mips.shift and copes with the 64bit calculation's overflow problem with the method introduced by David Daney in "MIPS: Octeon: Use non-overflowing arithmetic in sched_clock". To reduce the duplication, I have abstracted an inline mips_sched_clock() function to arch/mips/include/asm/time.h from arch/mips/cavium-octeon/csrc-octeon.c. v6 -> v7: O Make it depends on !CPU_FREQ and CPU_HAS_FIXED_C0_COUNT This sched_clock() is only available with the processor has fixed cp0 MIPS count register or even has dynamic cp0 MIPS count register but with CPU_FREQ disabled. NOTE: If your processor has fixed c0 count, please select CPU_HAS_FIXED_C0_COUNT for it and send a related patch to Ralf. v5 -> v6: o hard-codes the cycle2ns_scale_factor as 8 for 30(cs->shift) is too big. With 30, the return value of sched_clock() will also overflow quickly. o moves the sched_clock() back into csrc-r4k.c as David and Sergei recommended. o inits c0 count as zero for PRINTK_TIME=y. o drops the HR_SCHED_CLCOK option for the current sched_clock() is stable enough to replace the jiffies based one. ) This patch adds a cnt32_to_63() and MIPS c0 count based sched_clock(), which provides high resolution. Without it, the Ftrace for MIPS will give useless timestamp information. Because cnt32_to_63() needs to be called at least once per half period to work properly, Differ from the old version, this v2 revision set up a kernel timer to ensure the requirement of some MIPSs which have short c0 count period. And also, we init the c0 count as ZERO(just as jiffies does) in time_init() before plat_time_init(), without it, PRINTK_TIME=y will get wrong timestamp information. (NOTE: some platforms have initiazlied c0 count as zero, but some not, this may introduce some duplication, perhaps a new patch is needed to remove the initialized of c0 count in the platforms later?) This is originally from arch/arm/plat-orion/time.c This revision works well for function graph tracer now, and also, PRINTK_TIME=y will get normal timestamp informatin. Signed-off-by: Wu Zhangjin --- arch/mips/Kconfig | 12 +++++++++++ arch/mips/kernel/csrc-r4k.c | 45 +++++++++++++++++++++++++++++++++++++++++++ arch/mips/kernel/time.c | 5 ++++ 3 files changed, 62 insertions(+), 0 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 8741671..1a76ab7 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -1933,6 +1933,18 @@ config NR_CPUS source "kernel/time/Kconfig" # +# High Resolution sched_clock() support +# + +config CPU_HAS_FIXED_C0_COUNT + bool + +config CPU_SUPPORTS_HR_SCHED_CLOCK + bool + depends on CPU_HAS_FIXED_C0_COUNT || !CPU_FREQ + default y + +# # Timer Interrupt Frequency Configuration # diff --git a/arch/mips/kernel/csrc-r4k.c b/arch/mips/kernel/csrc-r4k.c index e95a3cd..89473ba 100644 --- a/arch/mips/kernel/csrc-r4k.c +++ b/arch/mips/kernel/csrc-r4k.c @@ -6,7 +6,9 @@ * Copyright (C) 2007 by Ralf Baechle */ #include +#include #include +#include #include @@ -22,6 +24,47 @@ static struct clocksource clocksource_mips = { .flags = CLOCK_SOURCE_IS_CONTINUOUS, }; +#ifdef CONFIG_CPU_SUPPORTS_HR_SCHED_CLOCK +/* + * MIPS sched_clock implementation. + * + * Because the hardware timer period is quite short and because cnt32_to_63() + * needs to be called at least once per half period to work properly, a kernel + * timer is set up to ensure this requirement is always met. + * + * Please refer to include/linux/cnt32_to_63.h, arch/arm/plat-orion/time.c and + * arch/mips/include/asm/time.h (mips_sched_clock) + */ +unsigned long long notrace sched_clock(void) +{ + u64 cnt = cnt32_to_63(read_c0_count()); + + if (cnt & 0x8000000000000000) + cnt &= 0x7fffffffffffffff; + + return mips_sched_clock(&clocksource_mips, cnt); +} + +static struct timer_list cnt32_to_63_keepwarm_timer; + +static void cnt32_to_63_keepwarm(unsigned long data) +{ + mod_timer(&cnt32_to_63_keepwarm_timer, round_jiffies(jiffies + data)); + sched_clock(); +} +#endif + +static inline void setup_hres_sched_clock(unsigned long clock) +{ +#ifdef CONFIG_CPU_SUPPORTS_HR_SCHED_CLOCK + unsigned long data; + + data = 0x80000000UL / clock * HZ; + setup_timer(&cnt32_to_63_keepwarm_timer, cnt32_to_63_keepwarm, data); + mod_timer(&cnt32_to_63_keepwarm_timer, round_jiffies(jiffies + data)); +#endif +} + int __init init_r4k_clocksource(void) { if (!cpu_has_counter || !mips_hpt_frequency) @@ -32,6 +75,8 @@ int __init init_r4k_clocksource(void) clocksource_set_clock(&clocksource_mips, mips_hpt_frequency); + setup_hres_sched_clock(mips_hpt_frequency); + clocksource_register(&clocksource_mips); return 0; diff --git a/arch/mips/kernel/time.c b/arch/mips/kernel/time.c index fb74974..86cf18a 100644 --- a/arch/mips/kernel/time.c +++ b/arch/mips/kernel/time.c @@ -119,6 +119,11 @@ static __init int cpu_has_mfc0_count_bug(void) void __init time_init(void) { +#ifdef CONFIG_CPU_SUPPORTS_HR_SCHED_CLOCK + if (!mips_clockevent_init() || !cpu_has_mfc0_count_bug()) + write_c0_count(0); +#endif + plat_time_init(); if (!mips_clockevent_init() || !cpu_has_mfc0_count_bug()) -- 1.6.6 From yuasa.linux@gmail.com Mon Feb 1 14:07:47 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 01 Feb 2010 14:07:52 +0100 (CET) Received: from mail-yx0-f193.google.com ([209.85.210.193]:60393 "EHLO mail-yx0-f193.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492317Ab0BANHr (ORCPT ); Mon, 1 Feb 2010 14:07:47 +0100 Received: by yxe31 with SMTP id 31so4014536yxe.21 for ; Mon, 01 Feb 2010 05:07:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:sender:date:from:to:cc :subject:message-id:x-mailer:mime-version:content-type :content-transfer-encoding; bh=qQNYuBD/iBjcpdnpnWq6cPRBFMcZFW2wXvqamsPswoc=; b=AjlKUq7CnDRBcB9roAC95xMlFDrvyBHNDQMUBQCCsYS5uI5wsux106/Y0ND15PQfQg +vtCWT5RYHx9ECjlEOZdTfc0zuzZNsY0iG9+VaF/nSE7+eGjRi+5HVJWWIkKgFIjSkWa 50LaZEp0T8+UnRV/YhZzFrMoiVco4BT8FVcaU= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:date:from:to:cc:subject:message-id:x-mailer:mime-version :content-type:content-transfer-encoding; b=o17LKNBhrfOWSX2M0jmj1fHtFV2ylXqTmCFJTBL4jY+pxVKZmfRqOrepxAApU83Sk8 Bsb+bI7s+8hhMj/r6xeEYWTRy/PVPbnso8NbM0JPo6hVeRwvUvzweEkQO00+qS/BD0EL R8QdJWLqbDDf6+5sQ/4ikI6XrmIu+Nyc2bHwY= Received: by 10.100.245.11 with SMTP id s11mr5255670anh.2.1265029661295; Mon, 01 Feb 2010 05:07:41 -0800 (PST) Received: from ypsilon.skybright.jp (sannin29006.nirai.ne.jp [203.160.29.6]) by mx.google.com with ESMTPS id 13sm3270986gxk.1.2010.02.01.05.07.38 (version=TLSv1/SSLv3 cipher=RC4-MD5); Mon, 01 Feb 2010 05:07:40 -0800 (PST) Date: Mon, 1 Feb 2010 22:05:57 +0900 From: Yoichi Yuasa To: Ralf Baechle Cc: yuasa@linux-mips.org, linux-mips Subject: [PATCH -queue 1/2] MIPS: Alchemy: remove prom_getcmdline() Message-Id: <20100201220557.729e7061.yuasa@linux-mips.org> X-Mailer: Sylpheed 2.7.1 (GTK+ 2.16.6; i686-pc-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25810 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: yuasa@linux-mips.org Precedence: bulk X-list: linux-mips Signed-off-by: Yoichi Yuasa --- arch/mips/alchemy/common/prom.c | 9 +-------- arch/mips/include/asm/mach-au1x00/prom.h | 1 - 2 files changed, 1 insertions(+), 9 deletions(-) diff --git a/arch/mips/alchemy/common/prom.c b/arch/mips/alchemy/common/prom.c index 18b310b..79e099f 100644 --- a/arch/mips/alchemy/common/prom.c +++ b/arch/mips/alchemy/common/prom.c @@ -43,11 +43,6 @@ int prom_argc; char **prom_argv; char **prom_envp; -char * __init_or_module prom_getcmdline(void) -{ - return &(arcs_cmdline[0]); -} - void prom_init_cmdline(void) { char *cp; @@ -121,14 +116,12 @@ static inline void str2eaddr(unsigned char *ea, unsigned char *str) int prom_get_ethernet_addr(char *ethernet_addr) { char *ethaddr_str; - char *argptr; /* Check the environment variables first */ ethaddr_str = prom_getenv("ethaddr"); if (!ethaddr_str) { /* Check command line */ - argptr = prom_getcmdline(); - ethaddr_str = strstr(argptr, "ethaddr="); + ethaddr_str = strstr(arcs_cmdline, "ethaddr="); if (!ethaddr_str) return -1; diff --git a/arch/mips/include/asm/mach-au1x00/prom.h b/arch/mips/include/asm/mach-au1x00/prom.h index e387155..4c0e09c 100644 --- a/arch/mips/include/asm/mach-au1x00/prom.h +++ b/arch/mips/include/asm/mach-au1x00/prom.h @@ -6,7 +6,6 @@ extern char **prom_argv; extern char **prom_envp; extern void prom_init_cmdline(void); -extern char *prom_getcmdline(void); extern char *prom_getenv(char *envname); extern int prom_get_ethernet_addr(char *ethernet_addr); -- 1.6.6.1 From yuasa.linux@gmail.com Mon Feb 1 14:08:10 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 01 Feb 2010 14:08:17 +0100 (CET) Received: from mail-yx0-f193.google.com ([209.85.210.193]:35124 "EHLO mail-yx0-f193.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492354Ab0BANHw (ORCPT ); Mon, 1 Feb 2010 14:07:52 +0100 Received: by yxe31 with SMTP id 31so4014618yxe.21 for ; Mon, 01 Feb 2010 05:07:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:sender:date:from:to:cc :subject:message-id:in-reply-to:references:x-mailer:mime-version :content-type:content-transfer-encoding; bh=69CEM6EDYmDm+Dr0qFECBU2hdG47WLaz9hbQZjADxow=; b=fa1Bjooy30DntlWJkEiQPHC6M4VcJ1oQlMLYBdRex8hCbehuMzcKi/cp212vo4I2em slOUOGwIMPyiYTxlAyFGvsJsmEpTVpzJRd4BTap8HWw89q9wu10Ixr4d5qp4EKxGzGkB sEjSzw6u6ryMjKlOklb/GQcu5HgMwMIue0IyQ= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:date:from:to:cc:subject:message-id:in-reply-to:references :x-mailer:mime-version:content-type:content-transfer-encoding; b=vby4EJgxc+y7c2plOmtoHrH0nyH6dD8xmnye7A+wwobTj9GG6Xbn1WdLfpzXOzeOSj QDMzytds/tmFiI0r5bxRoeQ4gnLHtkiwfSK/jHsgmUugPvcFi4ozWLLjCAKg8tkrb7Zz 6v0OSSCJ0J5lY1o4V7wLzrGJm6+Md7fZduQM0= Received: by 10.91.193.19 with SMTP id v19mr3909147agp.4.1265029665898; Mon, 01 Feb 2010 05:07:45 -0800 (PST) Received: from ypsilon.skybright.jp (sannin29006.nirai.ne.jp [203.160.29.6]) by mx.google.com with ESMTPS id 13sm3254150gxk.13.2010.02.01.05.07.44 (version=TLSv1/SSLv3 cipher=RC4-MD5); Mon, 01 Feb 2010 05:07:45 -0800 (PST) Date: Mon, 1 Feb 2010 22:06:56 +0900 From: Yoichi Yuasa To: Ralf Baechle Cc: yuasa@linux-mips.org, linux-mips Subject: [PATCH -queue 2/2] MIPS: Alchemy: use strlcat() for the command line arguments Message-Id: <20100201220656.6aaee78c.yuasa@linux-mips.org> In-Reply-To: <20100201220557.729e7061.yuasa@linux-mips.org> References: <20100201220557.729e7061.yuasa@linux-mips.org> X-Mailer: Sylpheed 2.7.1 (GTK+ 2.16.6; i686-pc-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25811 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: yuasa@linux-mips.org Precedence: bulk X-list: linux-mips Signed-off-by: Yoichi Yuasa --- arch/mips/alchemy/common/prom.c | 19 +++++-------------- 1 files changed, 5 insertions(+), 14 deletions(-) diff --git a/arch/mips/alchemy/common/prom.c b/arch/mips/alchemy/common/prom.c index 79e099f..c29511b 100644 --- a/arch/mips/alchemy/common/prom.c +++ b/arch/mips/alchemy/common/prom.c @@ -45,22 +45,13 @@ char **prom_envp; void prom_init_cmdline(void) { - char *cp; - int actr; - - actr = 1; /* Always ignore argv[0] */ + int i; - cp = &(arcs_cmdline[0]); - while (actr < prom_argc) { - strcpy(cp, prom_argv[actr]); - cp += strlen(prom_argv[actr]); - *cp++ = ' '; - actr++; + for (i = 1; i < prom_argc; i++) { + strlcat(arcs_cmdline, prom_argv[i], COMMAND_LINE_SIZE); + if (i < (prom_argc - 1)) + strlcat(arcs_cmdline, " ", COMMAND_LINE_SIZE); } - if (cp != &(arcs_cmdline[0])) /* get rid of trailing space */ - --cp; - if (prom_argc > 1) - *cp = '\0'; } char *prom_getenv(char *envname) -- 1.6.6.1 From macro@linux-mips.org Mon Feb 1 15:50:27 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 01 Feb 2010 15:50:31 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:47152 "EHLO localhost.localdomain" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492407Ab0BAOu1 (ORCPT ); Mon, 1 Feb 2010 15:50:27 +0100 Date: Mon, 1 Feb 2010 14:50:27 +0000 (GMT) From: "Maciej W. Rozycki" To: Ralf Baechle cc: Guenter Roeck , David Daney , "linux-mips@linux-mips.org" Subject: Re: Kernel crash in 2.6.32.6 / bcm1480 with 16k page size In-Reply-To: <20100201021854.GA8572@linux-mips.org> Message-ID: References: <20100129151220.GA3882@ericsson.com> <4B6316D2.1060006@caviumnetworks.com> <20100129180619.GA20113@linux-mips.org> <20100129183926.GB9895@ericsson.com> <4B632F60.4000604@caviumnetworks.com> <20100129192532.GA11123@ericsson.com> <4B6336F1.8070208@caviumnetworks.com> <20100129195801.GC11123@ericsson.com> <20100131165503.GA18523@ericsson.com> <20100201021854.GA8572@linux-mips.org> User-Agent: Alpine 2.00 (LFD 1167 2008-08-23) MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25812 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: macro@linux-mips.org Precedence: bulk X-list: linux-mips On Mon, 1 Feb 2010, Ralf Baechle wrote: > Write a value with all bits set to c0_entryhi, then read it back again. > The set bits in the VPN2 bitfield will indicate the size of the virtual > address range supported. The MIPS64 documentation also calls this value > SEGBITS. The nice thing about this probe is that it is supported for > all 64-bit MIPS processors except the R8000 which has an entirely different > TLB scheme anyway. > > Similarly it is possible to probe the physical address range in either > c0_entrylo0 or c0_entrylo1. This is also of interest on 32-bit processors. Indeed -- IIRC the architecture spec calls this value PABITS. I wasn't sure about the legacy processors -- if that works with them too, then it's even better. Maciej From lists@nabble.com Mon Feb 1 16:04:21 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 01 Feb 2010 16:04:25 +0100 (CET) Received: from kuber.nabble.com ([216.139.236.158]:35857 "EHLO kuber.nabble.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492406Ab0BAPEV (ORCPT ); Mon, 1 Feb 2010 16:04:21 +0100 Received: from isper.nabble.com ([192.168.236.156]) by kuber.nabble.com with esmtp (Exim 4.63) (envelope-from ) id 1Nbxp3-0003ol-Gs for linux-mips@linux-mips.org; Mon, 01 Feb 2010 07:04:17 -0800 Message-ID: <27405624.post@talk.nabble.com> Date: Mon, 1 Feb 2010 07:04:17 -0800 (PST) From: Guenter Roeck To: linux-mips@linux-mips.org Subject: Re: Kernel crash in 2.6.32.6 / bcm1480 with 16k page size In-Reply-To: <20100201021854.GA8572@linux-mips.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Nabble-From: public@roeck-us.net References: <20100128155514.GA31611@ericsson.com> <20100129132406.GD5685@linux-mips.org> <20100129151220.GA3882@ericsson.com> <4B6316D2.1060006@caviumnetworks.com> <20100129180619.GA20113@linux-mips.org> <20100129183926.GB9895@ericsson.com> <4B632F60.4000604@caviumnetworks.com> <20100129192532.GA11123@ericsson.com> <4B6336F1.8070208@caviumnetworks.com> <20100129195801.GC11123@ericsson.com> <20100131165503.GA18523@ericsson.com> <20100201021854.GA8572@linux-mips.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25813 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: public@roeck-us.net Precedence: bulk X-list: linux-mips Ralf Baechle DL5RB wrote: > > On Sun, Jan 31, 2010 at 08:55:03AM -0800, Guenter Roeck wrote: > >> > The size of the address space can be probed via CP0 registers (for >> MIPS >> > architecture processors that is). No need to add any CPU dependencies >> > (except from legacy 64-bit MIPS processors perhaps). >> > >> That would help. Do you happen to know which CP0 register(s) to look for >> ? >> I browsed through the MIPS 5K and 20Kc manuals, but didn't find it. > > Write a value with all bits set to c0_entryhi, then read it back again. > The set bits in the VPN2 bitfield will indicate the size of the virtual > address range supported. The MIPS64 documentation also calls this value > SEGBITS. The nice thing about this probe is that it is supported for > all 64-bit MIPS processors except the R8000 which has an entirely > different > TLB scheme anyway. > > Similarly it is possible to probe the physical address range in either > c0_entrylo0 or c0_entrylo1. This is also of interest on 32-bit > processors. > > Ralf > > > Ok, I'll try that and submit a new set of patches if it works. Guenter -- View this message in context: http://old.nabble.com/Kernel-crash-in-2.6.32.6---bcm1480-with-16k-page-size-tp27358179p27405624.html Sent from the linux-mips main mailing list archive at Nabble.com. From ralf@linux-mips.org Mon Feb 1 16:25:51 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 01 Feb 2010 16:25:59 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:42517 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1492503Ab0BAPZv (ORCPT ); Mon, 1 Feb 2010 16:25:51 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id o11FQ48q030359; Mon, 1 Feb 2010 16:26:04 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id o11FQ28g030351; Mon, 1 Feb 2010 16:26:02 +0100 Date: Mon, 1 Feb 2010 16:26:01 +0100 From: Ralf Baechle To: "Maciej W. Rozycki" Cc: Guenter Roeck , David Daney , "linux-mips@linux-mips.org" Subject: Re: Kernel crash in 2.6.32.6 / bcm1480 with 16k page size Message-ID: <20100201152601.GA22640@linux-mips.org> References: <20100129180619.GA20113@linux-mips.org> <20100129183926.GB9895@ericsson.com> <4B632F60.4000604@caviumnetworks.com> <20100129192532.GA11123@ericsson.com> <4B6336F1.8070208@caviumnetworks.com> <20100129195801.GC11123@ericsson.com> <20100131165503.GA18523@ericsson.com> <20100201021854.GA8572@linux-mips.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.20 (2009-08-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25814 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Mon, Feb 01, 2010 at 02:50:27PM +0000, Maciej W. Rozycki wrote: > > Write a value with all bits set to c0_entryhi, then read it back again. > > The set bits in the VPN2 bitfield will indicate the size of the virtual > > address range supported. The MIPS64 documentation also calls this value > > SEGBITS. The nice thing about this probe is that it is supported for > > all 64-bit MIPS processors except the R8000 which has an entirely different > > TLB scheme anyway. > > > > Similarly it is possible to probe the physical address range in either > > c0_entrylo0 or c0_entrylo1. This is also of interest on 32-bit processors. > > Indeed -- IIRC the architecture spec calls this value PABITS. I wasn't > sure about the legacy processors -- if that works with them too, then it's > even better. The probing method was undocumented until MIPS64 but if you look at the format of the EntryLo register it's always been possible. The R10000 needs special treatment though - it has the UC (Uncache Attribute) field in the bits 62..63 of EntryLo; this field needs to be ignored. Ralf From ralf@linux-mips.org Mon Feb 1 16:38:27 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 01 Feb 2010 16:38:30 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:34796 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1492406Ab0BAPi0 (ORCPT ); Mon, 1 Feb 2010 16:38:26 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id o11FcgXW002267; Mon, 1 Feb 2010 16:38:42 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id o11FcgMc002257; Mon, 1 Feb 2010 16:38:42 +0100 Date: Mon, 1 Feb 2010 16:38:41 +0100 From: Ralf Baechle To: Yoichi Yuasa Cc: linux-mips Subject: Re: [PATCH -queue 1/2] MIPS: Alchemy: remove prom_getcmdline() Message-ID: <20100201153841.GC22640@linux-mips.org> References: <20100201220557.729e7061.yuasa@linux-mips.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20100201220557.729e7061.yuasa@linux-mips.org> User-Agent: Mutt/1.5.20 (2009-08-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25815 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Mon, Feb 01, 2010 at 10:05:57PM +0900, Yoichi Yuasa wrote: Thanks, queued for 2.6.34. Ralf From ralf@linux-mips.org Mon Feb 1 16:38:49 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 01 Feb 2010 16:38:59 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:34802 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1492446Ab0BAPid (ORCPT ); Mon, 1 Feb 2010 16:38:33 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id o11Fcn2t002291; Mon, 1 Feb 2010 16:38:49 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id o11FcmjO002289; Mon, 1 Feb 2010 16:38:48 +0100 Date: Mon, 1 Feb 2010 16:38:48 +0100 From: Ralf Baechle To: Yoichi Yuasa Cc: linux-mips Subject: Re: [PATCH -queue 2/2] MIPS: Alchemy: use strlcat() for the command line arguments Message-ID: <20100201153848.GD22640@linux-mips.org> References: <20100201220557.729e7061.yuasa@linux-mips.org> <20100201220656.6aaee78c.yuasa@linux-mips.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20100201220656.6aaee78c.yuasa@linux-mips.org> User-Agent: Mutt/1.5.20 (2009-08-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25816 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Mon, Feb 01, 2010 at 10:06:56PM +0900, Yoichi Yuasa wrote: Thanks, queued for 2.6.34. Ralf From David.Daney@caviumnetworks.com Mon Feb 1 18:08:25 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 01 Feb 2010 18:08:29 +0100 (CET) Received: from mail3.caviumnetworks.com ([12.108.191.235]:4776 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492506Ab0BARIZ (ORCPT ); Mon, 1 Feb 2010 18:08:25 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Mon, 01 Feb 2010 09:07:32 -0800 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Mon, 1 Feb 2010 09:07:20 -0800 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Mon, 1 Feb 2010 09:07:19 -0800 Message-ID: <4B670A45.3010105@caviumnetworks.com> Date: Mon, 01 Feb 2010 09:07:17 -0800 From: David Daney User-Agent: Thunderbird 2.0.0.21 (X11/20090320) MIME-Version: 1.0 To: Wu Zhangjin CC: Ralf Baechle , "linux-mips@linux-mips.org" Subject: Re: [PATCH -queue 1/3] MIPS: add a common mips_sched_clock() References: <198fc72d92823547c9be132616fd2ebc2091ff39.1265022593.git.wuzhangjin@gmail.com> In-Reply-To: <198fc72d92823547c9be132616fd2ebc2091ff39.1265022593.git.wuzhangjin@gmail.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 01 Feb 2010 17:07:20.0007 (UTC) FILETIME=[038AE570:01CAA361] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25817 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Wu Zhangjin wrote: > + "dmultu\t%[cnt],%[mult]\n\t" > + "nor\t%[t1],$0,%[shift]\n\t" > + "mfhi\t%[t2]\n\t" > + "mflo\t%[t3]\n\t" > + "dsll\t%[t2],%[t2],1\n\t" > + "dsrlv\t%[rv],%[t3],%[shift]\n\t" > + "dsllv\t%[t1],%[t2],%[t1]\n\t" This is unlikely to work in 32-bit kernels. David Daney From David.Daney@caviumnetworks.com Mon Feb 1 18:13:38 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 01 Feb 2010 18:13:42 +0100 (CET) Received: from mail3.caviumnetworks.com ([12.108.191.235]:4903 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492503Ab0BARNi (ORCPT ); Mon, 1 Feb 2010 18:13:38 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Mon, 01 Feb 2010 09:13:45 -0800 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Mon, 1 Feb 2010 09:13:36 -0800 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Mon, 1 Feb 2010 09:13:36 -0800 Message-ID: <4B670BC0.8030003@caviumnetworks.com> Date: Mon, 01 Feb 2010 09:13:36 -0800 From: David Daney User-Agent: Thunderbird 2.0.0.21 (X11/20090320) MIME-Version: 1.0 To: Florian Fainelli CC: Ralf Baechle , linux-mips@linux-mips.org Subject: Re: [PATCH urgent] MIPS: fix micro-assembly overflow in set_except_vector References: <201002011027.37521.florian@openwrt.org> In-Reply-To: <201002011027.37521.florian@openwrt.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 01 Feb 2010 17:13:36.0806 (UTC) FILETIME=[E421DC60:01CAA361] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25818 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Florian Fainelli wrote: > Commit 24a6d9866c5f15ba7e5b14dc17be4b6edba21d0e broke > the installation of handlers for boards which have their > handlers above a 1 << 26 address. Fix this by making sure that > jump_mask does not excess 0xfc000000 and add the missing ~ operator > to jump_mask when jumping to the handler address. > > Reported-by: Maxime Bizon > Signed-off-by: Florian Fainelli Acked-by: David Daney > --- > diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c > index 7693929..40d94c3 100644 > --- a/arch/mips/kernel/traps.c > +++ b/arch/mips/kernel/traps.c > @@ -1279,11 +1279,11 @@ void __init *set_except_vector(int n, void *addr) > > exception_handlers[n] = handler; > if (n == 0 && cpu_has_divec) { > - unsigned long jump_mask = ~((1 << 28) - 1); > + unsigned long jump_mask = ~((1 << 26) - 1); > u32 *buf = (u32 *)(ebase + 0x200); > unsigned int k0 = 26; > if ((handler & jump_mask) == ((ebase + 0x200) & jump_mask)) { > - uasm_i_j(&buf, handler & jump_mask); > + uasm_i_j(&buf, handler & ~jump_mask); > uasm_i_nop(&buf); > } else { > UASM_i_LA(&buf, k0, handler); > > > From ralf@linux-mips.org Mon Feb 1 18:45:11 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 01 Feb 2010 18:45:17 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:38363 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1492448Ab0BARpL (ORCPT ); Mon, 1 Feb 2010 18:45:11 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id o11HjENO018072; Mon, 1 Feb 2010 18:45:15 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id o11HjDEK018070; Mon, 1 Feb 2010 18:45:13 +0100 Date: Mon, 1 Feb 2010 18:45:12 +0100 From: Ralf Baechle To: Alexander Clouter Cc: linux-mips@linux-mips.org Subject: Re: [PATCH 1/3] MIPS: AR7 whitespace hacking Message-ID: <20100201174512.GA9806@linux-mips.org> References: <1265005758.31984.8.camel@falcon> <1hli37-4t9.ln1@chipmunk.wormnet.eu> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1hli37-4t9.ln1@chipmunk.wormnet.eu> User-Agent: Mutt/1.5.20 (2009-08-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25819 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Mon, Feb 01, 2010 at 10:03:45AM +0000, Alexander Clouter wrote: > From: Alexander Clouter > Date: Mon, 1 Feb 2010 10:03:45 +0000 > To: linux-mips@linux-mips.org > Subject: Re: [PATCH 1/3] MIPS: AR7 whitespace hacking > > Wu Zhangjin wrote: > > > >> +/***************************************************************************** > >> + * VLYNQ Bus > >> + ****************************************************************************/ > > > > Why not simply use: > > > > /* VLYNQ Bus */ > > > > You have deleted lots of whitespaces, but added more *. > > > "good enough for ARM[1]" :) > > Compromise on this instead? > ---- > /* > * VLYNQ Bus > */ > ---- Just did this one myself. The patch also had a reject on the lest segment of arch/mips/ar7/prom.c.rej; it seems that you've not created your patches against a recent version of the -queue tree. Either way, queued for 2.6.34. Ralf From ralf@linux-mips.org Mon Feb 1 18:55:21 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 01 Feb 2010 18:55:24 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:33289 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1492536Ab0BARzV (ORCPT ); Mon, 1 Feb 2010 18:55:21 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id o11HtPB8024229; Mon, 1 Feb 2010 18:55:25 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id o11HtOov024218; Mon, 1 Feb 2010 18:55:24 +0100 Date: Mon, 1 Feb 2010 18:55:24 +0100 From: Ralf Baechle To: Alexander Clouter Cc: linux-mips@linux-mips.org Subject: Re: [PATCH 2/3] MIPS: AR7 fix usb slave mem range mistype Message-ID: <20100201175523.GB9806@linux-mips.org> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.20 (2009-08-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25820 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Sun, Jan 31, 2010 at 07:38:52PM +0000, Alexander Clouter wrote: > MIPS: AR7 fix usb slave mem range mistype Thanks, applied. Ralf From ralf@linux-mips.org Mon Feb 1 20:01:57 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 01 Feb 2010 20:02:01 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:55631 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1492670Ab0BATB5 (ORCPT ); Mon, 1 Feb 2010 20:01:57 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id o11J21JZ009219; Mon, 1 Feb 2010 20:02:01 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id o11J20DX009216; Mon, 1 Feb 2010 20:02:00 +0100 Date: Mon, 1 Feb 2010 20:02:00 +0100 From: Ralf Baechle To: Alexander Clouter Cc: linux-mips@linux-mips.org Subject: Re: [PATCH 3/3] MIPS: AR7 make ar7_register_devices much more durable Message-ID: <20100201190159.GC9806@linux-mips.org> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.20 (2009-08-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25821 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Sun, Jan 31, 2010 at 07:39:57PM +0000, Alexander Clouter wrote: > MIPS: AR7 make ar7_register_devices much more durable patches/0070-03.patch:85: space before tab in indent. } patches/0070-03.patch:192: space before tab in indent. iounmap(bootcr); patches/0070-03.patch:208: space before tab in indent. res = platform_device_register(&ar7_wdt); error: patch failed: arch/mips/ar7/platform.c:529 error: arch/mips/ar7/platform.c: patch does not apply Grrr :-) I've fixed that up, also the pr_xxx changes suggested by Wu. Queued for 2.6.34. Thanks, Ralf From guenter.roeck@ericsson.com Mon Feb 1 21:19:52 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 01 Feb 2010 21:19:59 +0100 (CET) Received: from imr1.ericy.com ([198.24.6.9]:34821 "EHLO imr1.ericy.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492772Ab0BAUTw (ORCPT ); Mon, 1 Feb 2010 21:19:52 +0100 Received: from eusaamw0706.eamcs.ericsson.se ([147.117.20.31]) by imr1.ericy.com (8.13.1/8.13.1) with ESMTP id o11KKWjo011497; Mon, 1 Feb 2010 14:20:41 -0600 Received: from [155.53.128.103] (147.117.20.212) by eusaamw0706.eamcs.ericsson.se (147.117.20.91) with Microsoft SMTP Server id 8.1.375.2; Mon, 1 Feb 2010 15:19:35 -0500 Subject: Re: Kernel crash in 2.6.32.6 / bcm1480 with 16k page size From: Guenter Roeck Reply-To: guenter.roeck@ericsson.com To: Ralf Baechle CC: "Maciej W. Rozycki" , David Daney , "linux-mips@linux-mips.org" In-Reply-To: <20100201021854.GA8572@linux-mips.org> References: <20100129151220.GA3882@ericsson.com> <4B6316D2.1060006@caviumnetworks.com> <20100129180619.GA20113@linux-mips.org> <20100129183926.GB9895@ericsson.com> <4B632F60.4000604@caviumnetworks.com> <20100129192532.GA11123@ericsson.com> <4B6336F1.8070208@caviumnetworks.com> <20100129195801.GC11123@ericsson.com> <20100131165503.GA18523@ericsson.com> <20100201021854.GA8572@linux-mips.org> Content-Type: text/plain Organization: Ericsson Date: Mon, 1 Feb 2010 12:21:17 -0800 Message-ID: <1265055677.5825.47.camel@groeck-laptop> MIME-Version: 1.0 X-Mailer: Evolution 2.26.1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25822 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: guenter.roeck@ericsson.com Precedence: bulk X-list: linux-mips On Sun, 2010-01-31 at 21:18 -0500, Ralf Baechle wrote: > On Sun, Jan 31, 2010 at 08:55:03AM -0800, Guenter Roeck wrote: > > > > The size of the address space can be probed via CP0 registers (for MIPS > > > architecture processors that is). No need to add any CPU dependencies > > > (except from legacy 64-bit MIPS processors perhaps). > > > > > That would help. Do you happen to know which CP0 register(s) to look for ? > > I browsed through the MIPS 5K and 20Kc manuals, but didn't find it. > > Write a value with all bits set to c0_entryhi, then read it back again. > The set bits in the VPN2 bitfield will indicate the size of the virtual > address range supported. The MIPS64 documentation also calls this value > SEGBITS. The nice thing about this probe is that it is supported for > all 64-bit MIPS processors except the R8000 which has an entirely different > TLB scheme anyway. Are you sure that this doesn't work for the R8000 ? From the user's manual (section 2.1.9, EntryHi) it looks like it should work. Guenter From ralf@linux-mips.org Mon Feb 1 21:49:02 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 01 Feb 2010 21:49:06 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:36914 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1492082Ab0BAUtC (ORCPT ); Mon, 1 Feb 2010 21:49:02 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id o11KnEFA019425; Mon, 1 Feb 2010 21:49:14 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id o11KnDRU019421; Mon, 1 Feb 2010 21:49:13 +0100 Date: Mon, 1 Feb 2010 21:49:12 +0100 From: Ralf Baechle To: Guenter Roeck Cc: "Maciej W. Rozycki" , David Daney , "linux-mips@linux-mips.org" Subject: Re: Kernel crash in 2.6.32.6 / bcm1480 with 16k page size Message-ID: <20100201204912.GC17381@linux-mips.org> References: <20100129180619.GA20113@linux-mips.org> <20100129183926.GB9895@ericsson.com> <4B632F60.4000604@caviumnetworks.com> <20100129192532.GA11123@ericsson.com> <4B6336F1.8070208@caviumnetworks.com> <20100129195801.GC11123@ericsson.com> <20100131165503.GA18523@ericsson.com> <20100201021854.GA8572@linux-mips.org> <1265055677.5825.47.camel@groeck-laptop> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1265055677.5825.47.camel@groeck-laptop> User-Agent: Mutt/1.5.20 (2009-08-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25823 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Mon, Feb 01, 2010 at 12:21:17PM -0800, Guenter Roeck wrote: > > Write a value with all bits set to c0_entryhi, then read it back again. > > The set bits in the VPN2 bitfield will indicate the size of the virtual > > address range supported. The MIPS64 documentation also calls this value > > SEGBITS. The nice thing about this probe is that it is supported for > > all 64-bit MIPS processors except the R8000 which has an entirely different > > TLB scheme anyway. > > Are you sure that this doesn't work for the R8000 ? From the user's > manual (section 2.1.9, EntryHi) it looks like it should work. The probe itself will work if it's carefully written not to get fooled by difference in bits 12..18 but that's easy) but still the R8000 has a fairly different TLB architecture which Linux doesn't support - the machines are rare and none of the active developers has one. Ralf From sgi-linux-mips@m.gmane.org Mon Feb 1 22:08:33 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 01 Feb 2010 22:08:37 +0100 (CET) Received: from lo.gmane.org ([80.91.229.12]:50258 "EHLO lo.gmane.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491886Ab0BAVId (ORCPT ); Mon, 1 Feb 2010 22:08:33 +0100 Received: from list by lo.gmane.org with local (Exim 4.69) (envelope-from ) id 1Nc3VR-0001dP-QF for linux-mips@linux-mips.org; Mon, 01 Feb 2010 22:08:25 +0100 Received: from chipmunk.wormnet.eu ([195.195.131.226]) by main.gmane.org with esmtp (Gmexim 0.1 (Debian)) id 1AlnuQ-0007hv-00 for ; Mon, 01 Feb 2010 22:08:25 +0100 Received: from alex by chipmunk.wormnet.eu with local (Gmexim 0.1 (Debian)) id 1AlnuQ-0007hv-00 for ; Mon, 01 Feb 2010 22:08:25 +0100 X-Injected-Via-Gmane: http://gmane.org/ To: linux-mips@linux-mips.org From: Alexander Clouter Subject: Re: [PATCH 3/3] MIPS: AR7 make ar7_register_devices much more durable Date: Mon, 1 Feb 2010 20:15:22 +0000 Lines: 34 Message-ID: References: <20100201190159.GC9806@linux-mips.org> X-Complaints-To: usenet@ger.gmane.org X-Gmane-NNTP-Posting-Host: chipmunk.wormnet.eu User-Agent: tin/1.9.3-20080506 ("Dalintober") (UNIX) (Linux/2.6.26-2-sparc64-smp (sparc64)) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25824 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: alex@digriz.org.uk Precedence: bulk X-list: linux-mips Ralf Baechle wrote: > > On Sun, Jan 31, 2010 at 07:39:57PM +0000, Alexander Clouter wrote: > >> MIPS: AR7 make ar7_register_devices much more durable > > patches/0070-03.patch:85: space before tab in indent. > } > patches/0070-03.patch:192: space before tab in indent. > iounmap(bootcr); > patches/0070-03.patch:208: space before tab in indent. > res = platform_device_register(&ar7_wdt); > error: patch failed: arch/mips/ar7/platform.c:529 > error: arch/mips/ar7/platform.c: patch does not apply > > Grrr :-) > My grovelling apologies, I do normally worship at the altar of checkpatch.pl however my faith was recently shattered by the acceptance for lines longer than 80 chars... > I've fixed that up, also the pr_xxx changes suggested by Wu. Queued > for 2.6.34. > I have some other code for you to rewrite if you are willing? All this manual fixing up does makeme ponder if you are trying to avoid doing something else you should be doing though :) Sorry again and also my thanks -- Alexander Clouter .sigmonster says: YOW!! The land of the rising SONY!! From guenter.roeck@ericsson.com Mon Feb 1 22:10:44 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 01 Feb 2010 22:10:49 +0100 (CET) Received: from imr1.ericy.com ([198.24.6.9]:59553 "EHLO imr1.ericy.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491886Ab0BAVKo (ORCPT ); Mon, 1 Feb 2010 22:10:44 +0100 Received: from eusaamw0707.eamcs.ericsson.se ([147.117.20.32]) by imr1.ericy.com (8.13.1/8.13.1) with ESMTP id o11LBbCp003321; Mon, 1 Feb 2010 15:11:42 -0600 Received: from [155.53.128.103] (147.117.20.212) by eusaamw0707.eamcs.ericsson.se (147.117.20.92) with Microsoft SMTP Server id 8.1.375.2; Mon, 1 Feb 2010 16:10:35 -0500 Subject: Re: Kernel crash in 2.6.32.6 / bcm1480 with 16k page size From: Guenter Roeck Reply-To: guenter.roeck@ericsson.com To: Ralf Baechle CC: "Maciej W. Rozycki" , David Daney , "linux-mips@linux-mips.org" In-Reply-To: <20100201204912.GC17381@linux-mips.org> References: <20100129180619.GA20113@linux-mips.org> <20100129183926.GB9895@ericsson.com> <4B632F60.4000604@caviumnetworks.com> <20100129192532.GA11123@ericsson.com> <4B6336F1.8070208@caviumnetworks.com> <20100129195801.GC11123@ericsson.com> <20100131165503.GA18523@ericsson.com> <20100201021854.GA8572@linux-mips.org> <1265055677.5825.47.camel@groeck-laptop> <20100201204912.GC17381@linux-mips.org> Content-Type: text/plain Organization: Ericsson Date: Mon, 1 Feb 2010 13:12:17 -0800 Message-ID: <1265058737.5825.55.camel@groeck-laptop> MIME-Version: 1.0 X-Mailer: Evolution 2.26.1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25825 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: guenter.roeck@ericsson.com Precedence: bulk X-list: linux-mips On Mon, 2010-02-01 at 15:49 -0500, Ralf Baechle wrote: > On Mon, Feb 01, 2010 at 12:21:17PM -0800, Guenter Roeck wrote: > > > > Write a value with all bits set to c0_entryhi, then read it back again. > > > The set bits in the VPN2 bitfield will indicate the size of the virtual > > > address range supported. The MIPS64 documentation also calls this value > > > SEGBITS. The nice thing about this probe is that it is supported for > > > all 64-bit MIPS processors except the R8000 which has an entirely different > > > TLB scheme anyway. > > > > Are you sure that this doesn't work for the R8000 ? From the user's > > manual (section 2.1.9, EntryHi) it looks like it should work. > > The probe itself will work if it's carefully written not to get fooled by > difference in bits 12..18 but that's easy) but still the R8000 has a fairly > different TLB architecture which Linux doesn't support - the machines are > rare and none of the active developers has one. > Looks like my code should work. I'll send out a patch in a couple of minutes. Guenter From prvs=6416caa4d=groeck@redback.com Mon Feb 1 22:16:28 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 01 Feb 2010 22:16:32 +0100 (CET) Received: from mgate.redback.com ([155.53.3.41]:52606 "EHLO mgate.redback.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492169Ab0BAVQ2 (ORCPT ); Mon, 1 Feb 2010 22:16:28 +0100 X-IronPort-AV: E=Sophos;i="4.49,385,1262592000"; d="scan'208";a="7751151" Received: from prattle.redback.com ([155.53.12.9]) by mgate.redback.com with ESMTP; 01 Feb 2010 13:16:16 -0800 Received: from localhost (localhost [127.0.0.1]) by prattle.redback.com (Postfix) with ESMTP id A07AE11D231A; Mon, 1 Feb 2010 13:16:25 -0800 (PST) Received: from prattle.redback.com ([127.0.0.1]) by localhost (prattle [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 15761-04; Mon, 1 Feb 2010 13:16:25 -0800 (PST) Received: from localhost (rbos-pc-13.lab.redback.com [10.12.11.133]) by prattle.redback.com (Postfix) with ESMTP id 8EB6F11D2319; Mon, 1 Feb 2010 13:16:24 -0800 (PST) From: Guenter Roeck To: linux-mips@linux-mips.org Cc: Guenter Roeck Subject: [PATCH v2] Virtual memory size detection for 64 bit MIPS CPUs Date: Mon, 1 Feb 2010 13:00:19 -0800 Message-Id: <1265058019-21484-1-git-send-email-guenter.roeck@ericsson.com> X-Mailer: git-send-email 1.6.0.4 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25826 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: guenter.roeck@ericsson.com Precedence: bulk X-list: linux-mips Linux kernel 2.6.32 and later allocates memory from the top of virtual memory space. This patch implements virtual memory size detection for 64 bit MIPS CPUs to avoid resulting crashes. Signed-off-by: Guenter Roeck --- arch/mips/include/asm/cpu-features.h | 3 +++ arch/mips/include/asm/cpu-info.h | 1 + arch/mips/include/asm/pgtable-64.h | 4 +++- arch/mips/kernel/cpu-probe.c | 22 ++++++++++++++++++++++ 4 files changed, 29 insertions(+), 1 deletions(-) diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h index 1f4df64..284eb55 100644 --- a/arch/mips/include/asm/cpu-features.h +++ b/arch/mips/include/asm/cpu-features.h @@ -209,6 +209,9 @@ # ifndef cpu_has_64bit_addresses # define cpu_has_64bit_addresses 1 # endif +# ifndef cpu_vmbits +# define cpu_vmbits cpu_data[0].vmbits +# endif #endif #if defined(CONFIG_CPU_MIPSR2_IRQ_VI) && !defined(cpu_has_vint) diff --git a/arch/mips/include/asm/cpu-info.h b/arch/mips/include/asm/cpu-info.h index 1260443..3c694bc 100644 --- a/arch/mips/include/asm/cpu-info.h +++ b/arch/mips/include/asm/cpu-info.h @@ -58,6 +58,7 @@ struct cpuinfo_mips { struct cache_desc tcache; /* Tertiary/split secondary cache */ int srsets; /* Shadow register sets */ int core; /* physical core number */ + int vmbits; /* Virtual memory size in bits */ #if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_MIPS_MT_SMTC) /* * In the MIPS MT "SMTC" model, each TC is considered diff --git a/arch/mips/include/asm/pgtable-64.h b/arch/mips/include/asm/pgtable-64.h index 9cd5089..259ec58 100644 --- a/arch/mips/include/asm/pgtable-64.h +++ b/arch/mips/include/asm/pgtable-64.h @@ -110,7 +110,9 @@ #define VMALLOC_START MAP_BASE #define VMALLOC_END \ (VMALLOC_START + \ - PTRS_PER_PGD * PTRS_PER_PMD * PTRS_PER_PTE * PAGE_SIZE - (1UL << 32)) + min(PTRS_PER_PGD * PTRS_PER_PMD * PTRS_PER_PTE * PAGE_SIZE, \ + (1UL<vmbits = 64 - zbits; + } else + c->vmbits = 32; +} + #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \ | MIPS_CPU_COUNTER) @@ -967,6 +987,8 @@ __cpuinit void cpu_probe(void) c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1; else c->srsets = 1; + + cpu_set_vmbits(c); } __cpuinit void cpu_report(void) -- 1.6.0.4 From David.Daney@caviumnetworks.com Mon Feb 1 22:43:01 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 01 Feb 2010 22:43:08 +0100 (CET) Received: from mail3.caviumnetworks.com ([12.108.191.235]:11137 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491886Ab0BAVnB (ORCPT ); Mon, 1 Feb 2010 22:43:01 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Mon, 01 Feb 2010 13:43:05 -0800 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Mon, 1 Feb 2010 13:42:53 -0800 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Mon, 1 Feb 2010 13:42:53 -0800 Message-ID: <4B674ADD.1050306@caviumnetworks.com> Date: Mon, 01 Feb 2010 13:42:53 -0800 From: David Daney User-Agent: Thunderbird 2.0.0.21 (X11/20090320) MIME-Version: 1.0 To: Guenter Roeck CC: linux-mips@linux-mips.org Subject: Re: [PATCH v2] Virtual memory size detection for 64 bit MIPS CPUs References: <1265058019-21484-1-git-send-email-guenter.roeck@ericsson.com> In-Reply-To: <1265058019-21484-1-git-send-email-guenter.roeck@ericsson.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 01 Feb 2010 21:42:53.0554 (UTC) FILETIME=[824DF520:01CAA387] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25827 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Guenter Roeck wrote: [...] > > +static inline void cpu_set_vmbits(struct cpuinfo_mips *c) > +{ > + if (cpu_has_64bits) { > + unsigned long zbits; > + > + asm volatile(".set mips64\n" > + "and %0, 0\n" > + "dsubu %0, 1\n" > + "dmtc0 %0, $10, 0\n" > + "dmfc0 %0, $10, 0\n" > + "dsll %0, %0, 2\n" > + "dsra %0, %0, 2\n" > + "dclz %0, %0\n" > + ".set mips0\n" > + : "=r" (zbits)); > + c->vmbits = 64 - zbits; > + } else > + c->vmbits = 32; > +} > + It should be possible to express this in 'pure' C using read_c0_entryhi()/write_c0_entryhi(), also you need to be sure you are not writing 1s to any reserved bits of the register. David Daney From guenter.roeck@ericsson.com Mon Feb 1 23:03:07 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 01 Feb 2010 23:03:11 +0100 (CET) Received: from imr1.ericy.com ([198.24.6.9]:59602 "EHLO imr1.ericy.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491789Ab0BAWDH (ORCPT ); Mon, 1 Feb 2010 23:03:07 +0100 Received: from eusaamw0707.eamcs.ericsson.se ([147.117.20.32]) by imr1.ericy.com (8.13.1/8.13.1) with ESMTP id o11M3tnO026896; Mon, 1 Feb 2010 16:03:58 -0600 Received: from [155.53.128.103] (147.117.20.212) by eusaamw0707.eamcs.ericsson.se (147.117.20.92) with Microsoft SMTP Server id 8.1.375.2; Mon, 1 Feb 2010 17:02:49 -0500 Subject: Re: [PATCH v2] Virtual memory size detection for 64 bit MIPS CPUs From: Guenter Roeck Reply-To: guenter.roeck@ericsson.com To: David Daney CC: "linux-mips@linux-mips.org" In-Reply-To: <4B674ADD.1050306@caviumnetworks.com> References: <1265058019-21484-1-git-send-email-guenter.roeck@ericsson.com> <4B674ADD.1050306@caviumnetworks.com> Content-Type: text/plain Organization: Ericsson Date: Mon, 1 Feb 2010 14:04:32 -0800 Message-ID: <1265061872.5825.71.camel@groeck-laptop> MIME-Version: 1.0 X-Mailer: Evolution 2.26.1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25828 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: guenter.roeck@ericsson.com Precedence: bulk X-list: linux-mips On Mon, 2010-02-01 at 16:42 -0500, David Daney wrote: > Guenter Roeck wrote: > [...] > > > > +static inline void cpu_set_vmbits(struct cpuinfo_mips *c) > > +{ > > + if (cpu_has_64bits) { > > + unsigned long zbits; > > + > > + asm volatile(".set mips64\n" > > + "and %0, 0\n" > > + "dsubu %0, 1\n" > > + "dmtc0 %0, $10, 0\n" > > + "dmfc0 %0, $10, 0\n" > > + "dsll %0, %0, 2\n" > > + "dsra %0, %0, 2\n" > > + "dclz %0, %0\n" > > + ".set mips0\n" > > + : "=r" (zbits)); > > + c->vmbits = 64 - zbits; > > + } else > > + c->vmbits = 32; > > +} > > + > > It should be possible to express this in 'pure' C using > read_c0_entryhi()/write_c0_entryhi(), also you need to be sure you are Sure, no problem. > not writing 1s to any reserved bits of the register. > That may be tricky, since the upper bits are reserved in some architectures. For example, the 20Kc core specification says that bits 61:40 are reserved and must be written with 0. I can write, say, 0x3fffffffffff0000 to avoid writing into lower reserved bits, but that won't help for any upper reserved bits. Would that be acceptable / better ? Guenter From David.Daney@caviumnetworks.com Mon Feb 1 23:13:22 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 01 Feb 2010 23:13:25 +0100 (CET) Received: from mail3.caviumnetworks.com ([12.108.191.235]:11927 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492036Ab0BAWNW (ORCPT ); Mon, 1 Feb 2010 23:13:22 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Mon, 01 Feb 2010 14:13:28 -0800 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Mon, 1 Feb 2010 14:12:40 -0800 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Mon, 1 Feb 2010 14:12:40 -0800 Message-ID: <4B6751D8.7080805@caviumnetworks.com> Date: Mon, 01 Feb 2010 14:12:40 -0800 From: David Daney User-Agent: Thunderbird 2.0.0.21 (X11/20090320) MIME-Version: 1.0 To: guenter.roeck@ericsson.com CC: "linux-mips@linux-mips.org" Subject: Re: [PATCH v2] Virtual memory size detection for 64 bit MIPS CPUs References: <1265058019-21484-1-git-send-email-guenter.roeck@ericsson.com> <4B674ADD.1050306@caviumnetworks.com> <1265061872.5825.71.camel@groeck-laptop> In-Reply-To: <1265061872.5825.71.camel@groeck-laptop> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 8bit X-OriginalArrivalTime: 01 Feb 2010 22:12:40.0378 (UTC) FILETIME=[AB55A9A0:01CAA38B] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25829 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Guenter Roeck wrote: > On Mon, 2010-02-01 at 16:42 -0500, David Daney wrote: >> Guenter Roeck wrote: >> [...] >>> >>> +static inline void cpu_set_vmbits(struct cpuinfo_mips *c) >>> +{ >>> + if (cpu_has_64bits) { >>> + unsigned long zbits; >>> + >>> + asm volatile(".set mips64\n" >>> + "and %0, 0\n" >>> + "dsubu %0, 1\n" >>> + "dmtc0 %0, $10, 0\n" >>> + "dmfc0 %0, $10, 0\n" >>> + "dsll %0, %0, 2\n" >>> + "dsra %0, %0, 2\n" >>> + "dclz %0, %0\n" >>> + ".set mips0\n" >>> + : "=r" (zbits)); >>> + c->vmbits = 64 - zbits; >>> + } else >>> + c->vmbits = 32; >>> +} >>> + >> It should be possible to express this in 'pure' C using >> read_c0_entryhi()/write_c0_entryhi(), also you need to be sure you are > > Sure, no problem. > >> not writing 1s to any reserved bits of the register. >> > That may be tricky, since the upper bits are reserved in some > architectures. For example, the 20Kc core specification says that bits > 61:40 are reserved and must be written with 0. > > I can write, say, 0x3fffffffffff0000 to avoid writing into lower > reserved bits, but that won't help for any upper reserved bits. Would > that be acceptable / better ? The MIPS64® Privileged Resource Architecture manual might be a better reference. I would set 1s only in bits 13-63 (the VPN2 and R fields). We don't support and don't really care about VPN2X, the upper bits are really the only ones of interest here. David Daney From guenter.roeck@ericsson.com Mon Feb 1 23:33:16 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 01 Feb 2010 23:33:23 +0100 (CET) Received: from imr2.ericy.com ([198.24.6.3]:33254 "EHLO imr2.ericy.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492687Ab0BAWdQ (ORCPT ); Mon, 1 Feb 2010 23:33:16 +0100 Received: from eusaamw0706.eamcs.ericsson.se ([147.117.20.31]) by imr2.ericy.com (8.13.1/8.13.1) with ESMTP id o11MYCjT020938; Mon, 1 Feb 2010 16:34:12 -0600 Received: from [155.53.128.103] (147.117.20.212) by eusaamw0706.eamcs.ericsson.se (147.117.20.91) with Microsoft SMTP Server id 8.1.375.2; Mon, 1 Feb 2010 17:33:06 -0500 Subject: Re: [PATCH v2] Virtual memory size detection for 64 bit MIPS CPUs From: Guenter Roeck Reply-To: guenter.roeck@ericsson.com To: David Daney CC: "linux-mips@linux-mips.org" In-Reply-To: <4B6751D8.7080805@caviumnetworks.com> References: <1265058019-21484-1-git-send-email-guenter.roeck@ericsson.com> <4B674ADD.1050306@caviumnetworks.com> <1265061872.5825.71.camel@groeck-laptop> <4B6751D8.7080805@caviumnetworks.com> Content-Type: text/plain; charset="UTF-8" Organization: Ericsson Date: Mon, 1 Feb 2010 14:34:49 -0800 Message-ID: <1265063689.5825.86.camel@groeck-laptop> MIME-Version: 1.0 X-Mailer: Evolution 2.26.1 Content-Transfer-Encoding: 8bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25830 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: guenter.roeck@ericsson.com Precedence: bulk X-list: linux-mips On Mon, 2010-02-01 at 17:12 -0500, David Daney wrote: > Guenter Roeck wrote: > > On Mon, 2010-02-01 at 16:42 -0500, David Daney wrote: > >> Guenter Roeck wrote: > >> [...] > >>> > >>> +static inline void cpu_set_vmbits(struct cpuinfo_mips *c) > >>> +{ > >>> + if (cpu_has_64bits) { > >>> + unsigned long zbits; > >>> + > >>> + asm volatile(".set mips64\n" > >>> + "and %0, 0\n" > >>> + "dsubu %0, 1\n" > >>> + "dmtc0 %0, $10, 0\n" > >>> + "dmfc0 %0, $10, 0\n" > >>> + "dsll %0, %0, 2\n" > >>> + "dsra %0, %0, 2\n" > >>> + "dclz %0, %0\n" > >>> + ".set mips0\n" > >>> + : "=r" (zbits)); > >>> + c->vmbits = 64 - zbits; > >>> + } else > >>> + c->vmbits = 32; > >>> +} > >>> + > >> It should be possible to express this in 'pure' C using > >> read_c0_entryhi()/write_c0_entryhi(), also you need to be sure you are > > > > Sure, no problem. > > > >> not writing 1s to any reserved bits of the register. > >> > > That may be tricky, since the upper bits are reserved in some > > architectures. For example, the 20Kc core specification says that bits > > 61:40 are reserved and must be written with 0. > > > > I can write, say, 0x3fffffffffff0000 to avoid writing into lower > > reserved bits, but that won't help for any upper reserved bits. Would > > that be acceptable / better ? > > > The MIPS64® Privileged Resource Architecture manual might be a better > reference. > Unfortunately, the download link for that manual on mips.com seems to be broken. > I would set 1s only in bits 13-63 (the VPN2 and R fields). We don't > support and don't really care about VPN2X, the upper bits are really the > only ones of interest here. > Ok, I'll do that. This is the new code: static inline void cpu_set_vmbits(struct cpuinfo_mips *c) { if (cpu_has_64bits) { write_c0_entryhi(0xfffffffffffff000ULL); c->vmbits = __fls(read_c0_entryhi() & 0x3ffffffffffff000ULL) + 1; } else c->vmbits = 32; } Guenter From greg@kroah.com Mon Feb 1 23:37:41 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 01 Feb 2010 23:37:45 +0100 (CET) Received: from kroah.org ([198.145.64.141]:59963 "EHLO coco.kroah.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492746Ab0BAWhl (ORCPT ); Mon, 1 Feb 2010 23:37:41 +0100 Received: from localhost (c-98-246-45-209.hsd1.or.comcast.net [98.246.45.209]) (using TLSv1 with cipher DHE-RSA-AES128-SHA (128/128 bits)) (No client certificate requested) by coco.kroah.org (Postfix) with ESMTPSA id 5181148A11; Mon, 1 Feb 2010 14:37:38 -0800 (PST) Date: Mon, 1 Feb 2010 14:29:19 -0800 From: Greg KH To: Wolfram Sang Cc: Maxime Bizon , Greg Kroah-Hartman , linux-serial@vger.kernel.org, Ralf Baechle , linux-mips@linux-mips.org Subject: Re: [PATCH 2/2] bcm63xx_uart: allow more than one uart to be registered. Message-ID: <20100201222919.GD19294@kroah.com> References: <1264873377-28479-1-git-send-email-mbizon@freebox.fr> <1264873377-28479-3-git-send-email-mbizon@freebox.fr> <20100130182343.GA6971@pengutronix.de> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20100130182343.GA6971@pengutronix.de> User-Agent: Mutt/1.5.20 (2009-06-14) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25831 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: greg@kroah.com Precedence: bulk X-list: linux-mips On Sat, Jan 30, 2010 at 07:23:43PM +0100, Wolfram Sang wrote: > On Sat, Jan 30, 2010 at 06:42:57PM +0100, Maxime Bizon wrote: > > The bcm6358 CPU has two uarts, make it possible to use the second one. > > > > Signed-off-by: Maxime Bizon > > --- > > drivers/serial/bcm63xx_uart.c | 5 +++-- > > 1 files changed, 3 insertions(+), 2 deletions(-) > > > > diff --git a/drivers/serial/bcm63xx_uart.c b/drivers/serial/bcm63xx_uart.c > > index f78ede8..6ab959a 100644 > > --- a/drivers/serial/bcm63xx_uart.c > > +++ b/drivers/serial/bcm63xx_uart.c > > @@ -35,7 +35,7 @@ > > #include > > #include > > > > -#define BCM63XX_NR_UARTS 1 > > +#define BCM63XX_NR_UARTS 2 > > > > static struct uart_port ports[BCM63XX_NR_UARTS]; > > > > @@ -784,7 +784,7 @@ static struct uart_driver bcm_uart_driver = { > > .dev_name = "ttyS", > > .major = TTY_MAJOR, > > .minor = 64, > > - .nr = 1, > > + .nr = 2, > > Err, why not using the #define here? Good idea, I've tweaked the patch to do that. thanks, greg k-h From macro@linux-mips.org Mon Feb 1 23:39:04 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 01 Feb 2010 23:39:07 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:59462 "EHLO localhost.localdomain" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492330Ab0BAWjE (ORCPT ); Mon, 1 Feb 2010 23:39:04 +0100 Date: Mon, 1 Feb 2010 22:39:03 +0000 (GMT) From: "Maciej W. Rozycki" To: Guenter Roeck cc: David Daney , "linux-mips@linux-mips.org" Subject: Re: [PATCH v2] Virtual memory size detection for 64 bit MIPS CPUs In-Reply-To: <1265061872.5825.71.camel@groeck-laptop> Message-ID: References: <1265058019-21484-1-git-send-email-guenter.roeck@ericsson.com> <4B674ADD.1050306@caviumnetworks.com> <1265061872.5825.71.camel@groeck-laptop> User-Agent: Alpine 2.00 (LFD 1167 2008-08-23) MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25832 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: macro@linux-mips.org Precedence: bulk X-list: linux-mips On Mon, 1 Feb 2010, Guenter Roeck wrote: > On Mon, 2010-02-01 at 16:42 -0500, David Daney wrote: > > Guenter Roeck wrote: > > [...] > > > > > > +static inline void cpu_set_vmbits(struct cpuinfo_mips *c) > > > +{ > > > + if (cpu_has_64bits) { > > > + unsigned long zbits; > > > + > > > + asm volatile(".set mips64\n" > > > + "and %0, 0\n" > > > + "dsubu %0, 1\n" > > > + "dmtc0 %0, $10, 0\n" > > > + "dmfc0 %0, $10, 0\n" > > > + "dsll %0, %0, 2\n" > > > + "dsra %0, %0, 2\n" > > > + "dclz %0, %0\n" > > > + ".set mips0\n" > > > + : "=r" (zbits)); > > > + c->vmbits = 64 - zbits; > > > + } else > > > + c->vmbits = 32; > > > +} > > > + > > > > It should be possible to express this in 'pure' C using > > read_c0_entryhi()/write_c0_entryhi(), also you need to be sure you are > > Sure, no problem. Especially as: 1. DCLZ is not a valid MIPS III instruction; some 64-bit CPUs will fault on it. 2. You have to take care of CP0 hazards, e.g. with the R4000 if an MTC0 is immediately followed by an MFC0 accessing the same CP0 register, then the result of the latter instruction is unpredictable. Maciej From prvs=6416caa4d=groeck@redback.com Tue Feb 2 00:07:36 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 02 Feb 2010 00:07:42 +0100 (CET) Received: from mgate.redback.com ([155.53.3.41]:60397 "EHLO mgate.redback.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492839Ab0BAXHg (ORCPT ); Tue, 2 Feb 2010 00:07:36 +0100 X-IronPort-AV: E=Sophos;i="4.49,385,1262592000"; d="scan'208";a="7752597" Received: from prattle.redback.com ([155.53.12.9]) by mgate.redback.com with ESMTP; 01 Feb 2010 15:07:33 -0800 Received: from localhost (localhost [127.0.0.1]) by prattle.redback.com (Postfix) with ESMTP id 2E587129ABD6; Mon, 1 Feb 2010 15:07:33 -0800 (PST) Received: from prattle.redback.com ([127.0.0.1]) by localhost (prattle [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 07015-08; Mon, 1 Feb 2010 15:07:33 -0800 (PST) Received: from localhost (rbos-pc-13.lab.redback.com [10.12.11.133]) by prattle.redback.com (Postfix) with ESMTP id 1D266129ABD5; Mon, 1 Feb 2010 15:07:31 -0800 (PST) From: Guenter Roeck To: linux-mips@linux-mips.org Cc: Guenter Roeck Subject: [PATCH v3] Virtual memory size detection for 64 bit MIPS CPUs Date: Mon, 1 Feb 2010 14:51:26 -0800 Message-Id: <1265064686-31278-1-git-send-email-guenter.roeck@ericsson.com> X-Mailer: git-send-email 1.6.0.4 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25833 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: guenter.roeck@ericsson.com Precedence: bulk X-list: linux-mips Linux kernel 2.6.32 and later allocates memory from the top of virtual memory space. This patch implements virtual memory size detection for 64 bit MIPS CPUs to avoid resulting crashes. Signed-off-by: Guenter Roeck --- arch/mips/include/asm/cpu-features.h | 3 +++ arch/mips/include/asm/cpu-info.h | 1 + arch/mips/include/asm/pgtable-64.h | 4 +++- arch/mips/kernel/cpu-probe.c | 11 +++++++++++ 4 files changed, 18 insertions(+), 1 deletions(-) diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h index 1f4df64..284eb55 100644 --- a/arch/mips/include/asm/cpu-features.h +++ b/arch/mips/include/asm/cpu-features.h @@ -209,6 +209,9 @@ # ifndef cpu_has_64bit_addresses # define cpu_has_64bit_addresses 1 # endif +# ifndef cpu_vmbits +# define cpu_vmbits cpu_data[0].vmbits +# endif #endif #if defined(CONFIG_CPU_MIPSR2_IRQ_VI) && !defined(cpu_has_vint) diff --git a/arch/mips/include/asm/cpu-info.h b/arch/mips/include/asm/cpu-info.h index 1260443..3c694bc 100644 --- a/arch/mips/include/asm/cpu-info.h +++ b/arch/mips/include/asm/cpu-info.h @@ -58,6 +58,7 @@ struct cpuinfo_mips { struct cache_desc tcache; /* Tertiary/split secondary cache */ int srsets; /* Shadow register sets */ int core; /* physical core number */ + int vmbits; /* Virtual memory size in bits */ #if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_MIPS_MT_SMTC) /* * In the MIPS MT "SMTC" model, each TC is considered diff --git a/arch/mips/include/asm/pgtable-64.h b/arch/mips/include/asm/pgtable-64.h index 9cd5089..259ec58 100644 --- a/arch/mips/include/asm/pgtable-64.h +++ b/arch/mips/include/asm/pgtable-64.h @@ -110,7 +110,9 @@ #define VMALLOC_START MAP_BASE #define VMALLOC_END \ (VMALLOC_START + \ - PTRS_PER_PGD * PTRS_PER_PMD * PTRS_PER_PTE * PAGE_SIZE - (1UL << 32)) + min(PTRS_PER_PGD * PTRS_PER_PMD * PTRS_PER_PTE * PAGE_SIZE, \ + (1UL<vmbits = fls64(read_c0_entryhi() & 0x3ffffffffffff000ULL); + } else + c->vmbits = 32; +} + #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \ | MIPS_CPU_COUNTER) @@ -967,6 +976,8 @@ __cpuinit void cpu_probe(void) c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1; else c->srsets = 1; + + cpu_set_vmbits(c); } __cpuinit void cpu_report(void) -- 1.6.0.4 From macro@linux-mips.org Tue Feb 2 00:11:52 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 02 Feb 2010 00:11:56 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:56445 "EHLO localhost.localdomain" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492772Ab0BAXLw (ORCPT ); Tue, 2 Feb 2010 00:11:52 +0100 Date: Mon, 1 Feb 2010 23:11:52 +0000 (GMT) From: "Maciej W. Rozycki" To: Ralf Baechle cc: Guenter Roeck , David Daney , "linux-mips@linux-mips.org" Subject: Re: Kernel crash in 2.6.32.6 / bcm1480 with 16k page size In-Reply-To: <20100201152601.GA22640@linux-mips.org> Message-ID: References: <20100129180619.GA20113@linux-mips.org> <20100129183926.GB9895@ericsson.com> <4B632F60.4000604@caviumnetworks.com> <20100129192532.GA11123@ericsson.com> <4B6336F1.8070208@caviumnetworks.com> <20100129195801.GC11123@ericsson.com> <20100131165503.GA18523@ericsson.com> <20100201021854.GA8572@linux-mips.org> <20100201152601.GA22640@linux-mips.org> User-Agent: Alpine 2.00 (LFD 1167 2008-08-23) MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25834 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: macro@linux-mips.org Precedence: bulk X-list: linux-mips On Mon, 1 Feb 2010, Ralf Baechle wrote: > > Indeed -- IIRC the architecture spec calls this value PABITS. I wasn't > > sure about the legacy processors -- if that works with them too, then it's > > even better. > > The probing method was undocumented until MIPS64 but if you look at the > format of the EntryLo register it's always been possible. The R10000 Frankly, I would be concerned about some reserved bits left floating rather than hardwired to any particular logical state, but the number of chips to check is limited. At least for some of them documentation is explicit the value reported is fixed and we can take it as an indication it is likely actually the case. > needs special treatment though - it has the UC (Uncache Attribute) field > in the bits 62..63 of EntryLo; this field needs to be ignored. Well, I think masking out everything beyond what would become the bit #63 of the physical address unconditionally is a safe and reasonable way to make the approach automagically work for the R10k too. Maciej From David.Daney@caviumnetworks.com Tue Feb 2 00:53:56 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 02 Feb 2010 00:54:00 +0100 (CET) Received: from mail3.caviumnetworks.com ([12.108.191.235]:14043 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491811Ab0BAXx4 (ORCPT ); Tue, 2 Feb 2010 00:53:56 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Mon, 01 Feb 2010 15:54:01 -0800 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Mon, 1 Feb 2010 15:44:22 -0800 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Mon, 1 Feb 2010 15:44:21 -0800 Message-ID: <4B676755.10600@caviumnetworks.com> Date: Mon, 01 Feb 2010 15:44:21 -0800 From: David Daney User-Agent: Thunderbird 2.0.0.21 (X11/20090320) MIME-Version: 1.0 To: Guenter Roeck CC: linux-mips@linux-mips.org, "Maciej W. Rozycki" Subject: Re: [PATCH v3] Virtual memory size detection for 64 bit MIPS CPUs References: <1265064686-31278-1-git-send-email-guenter.roeck@ericsson.com> In-Reply-To: <1265064686-31278-1-git-send-email-guenter.roeck@ericsson.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 01 Feb 2010 23:44:21.0929 (UTC) FILETIME=[7A83B990:01CAA398] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25835 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Guenter Roeck wrote: > Linux kernel 2.6.32 and later allocates memory from the top of virtual memory > space. > > This patch implements virtual memory size detection for 64 bit MIPS CPUs > to avoid resulting crashes. > > Signed-off-by: Guenter Roeck [...] > > +static inline void cpu_set_vmbits(struct cpuinfo_mips *c) > +{ > + if (cpu_has_64bits) { > + write_c0_entryhi(0xfffffffffffff000ULL); macro indicated that we need to avoid hazards here on R4000. Perhaps adding: back_to_back_c0_hazard(); > + c->vmbits = fls64(read_c0_entryhi() & 0x3ffffffffffff000ULL); > + } else > + c->vmbits = 32; > +} > + From groeck@ericsson.com Tue Feb 2 01:08:54 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 02 Feb 2010 01:08:57 +0100 (CET) Received: from imr2.ericy.com ([198.24.6.3]:45779 "EHLO imr2.ericy.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492244Ab0BBAIx (ORCPT ); Tue, 2 Feb 2010 01:08:53 +0100 Received: from eusaamw0706.eamcs.ericsson.se ([147.117.20.31]) by imr2.ericy.com (8.13.1/8.13.1) with ESMTP id o1209naA019019; Mon, 1 Feb 2010 18:09:51 -0600 Received: from localhost (147.117.20.212) by eusaamw0706.eamcs.ericsson.se (147.117.20.91) with Microsoft SMTP Server id 8.1.375.2; Mon, 1 Feb 2010 19:08:43 -0500 Date: Mon, 1 Feb 2010 16:10:26 -0800 From: Guenter Roeck To: David Daney CC: "linux-mips@linux-mips.org" , "Maciej W. Rozycki" Subject: Re: [PATCH v3] Virtual memory size detection for 64 bit MIPS CPUs Message-ID: <20100202001026.GA6883@ericsson.com> References: <1265064686-31278-1-git-send-email-guenter.roeck@ericsson.com> <4B676755.10600@caviumnetworks.com> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <4B676755.10600@caviumnetworks.com> User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25836 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: guenter.roeck@ericsson.com Precedence: bulk X-list: linux-mips On Mon, Feb 01, 2010 at 06:44:21PM -0500, David Daney wrote: > Guenter Roeck wrote: > > Linux kernel 2.6.32 and later allocates memory from the top of virtual memory > > space. > > > > This patch implements virtual memory size detection for 64 bit MIPS CPUs > > to avoid resulting crashes. > > > > Signed-off-by: Guenter Roeck > [...] > > > > +static inline void cpu_set_vmbits(struct cpuinfo_mips *c) > > +{ > > + if (cpu_has_64bits) { > > + write_c0_entryhi(0xfffffffffffff000ULL); > > macro indicated that we need to avoid hazards here on R4000. > > Perhaps adding: > > back_to_back_c0_hazard(); > Compiler already added a nop, so I thought it wasn't necessary. Doesn't hurt either, so I'll put it in. Guenter From prvs=6426729b5=groeck@redback.com Tue Feb 2 01:19:10 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 02 Feb 2010 01:19:14 +0100 (CET) Received: from mgate.redback.com ([155.53.3.41]:18405 "EHLO mgate.redback.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492422Ab0BBATK (ORCPT ); Tue, 2 Feb 2010 01:19:10 +0100 X-IronPort-AV: E=Sophos;i="4.49,386,1262592000"; d="scan'208";a="7753395" Received: from prattle.redback.com ([155.53.12.9]) by mgate.redback.com with ESMTP; 01 Feb 2010 16:19:07 -0800 Received: from localhost (localhost [127.0.0.1]) by prattle.redback.com (Postfix) with ESMTP id 2A670E3A68A; Mon, 1 Feb 2010 16:19:07 -0800 (PST) Received: from prattle.redback.com ([127.0.0.1]) by localhost (prattle [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 06350-09; Mon, 1 Feb 2010 16:19:07 -0800 (PST) Received: from localhost (rbos-pc-13.lab.redback.com [10.12.11.133]) by prattle.redback.com (Postfix) with ESMTP id 18DF5E3A687; Mon, 1 Feb 2010 16:19:05 -0800 (PST) From: Guenter Roeck To: linux-mips@linux-mips.org Cc: Guenter Roeck Subject: [PATCH v4] Virtual memory size detection for 64 bit MIPS CPUs Date: Mon, 1 Feb 2010 16:02:59 -0800 Message-Id: <1265068979-12052-1-git-send-email-guenter.roeck@ericsson.com> X-Mailer: git-send-email 1.6.0.4 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25837 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: guenter.roeck@ericsson.com Precedence: bulk X-list: linux-mips Linux kernel 2.6.32 and later allocates memory from the top of virtual memory space. This patch implements virtual memory size detection for 64 bit MIPS CPUs to avoid resulting crashes. Signed-off-by: Guenter Roeck --- arch/mips/include/asm/cpu-features.h | 3 +++ arch/mips/include/asm/cpu-info.h | 1 + arch/mips/include/asm/pgtable-64.h | 4 +++- arch/mips/kernel/cpu-probe.c | 12 ++++++++++++ 4 files changed, 19 insertions(+), 1 deletions(-) diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h index 1f4df64..284eb55 100644 --- a/arch/mips/include/asm/cpu-features.h +++ b/arch/mips/include/asm/cpu-features.h @@ -209,6 +209,9 @@ # ifndef cpu_has_64bit_addresses # define cpu_has_64bit_addresses 1 # endif +# ifndef cpu_vmbits +# define cpu_vmbits cpu_data[0].vmbits +# endif #endif #if defined(CONFIG_CPU_MIPSR2_IRQ_VI) && !defined(cpu_has_vint) diff --git a/arch/mips/include/asm/cpu-info.h b/arch/mips/include/asm/cpu-info.h index 1260443..3c694bc 100644 --- a/arch/mips/include/asm/cpu-info.h +++ b/arch/mips/include/asm/cpu-info.h @@ -58,6 +58,7 @@ struct cpuinfo_mips { struct cache_desc tcache; /* Tertiary/split secondary cache */ int srsets; /* Shadow register sets */ int core; /* physical core number */ + int vmbits; /* Virtual memory size in bits */ #if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_MIPS_MT_SMTC) /* * In the MIPS MT "SMTC" model, each TC is considered diff --git a/arch/mips/include/asm/pgtable-64.h b/arch/mips/include/asm/pgtable-64.h index 9cd5089..259ec58 100644 --- a/arch/mips/include/asm/pgtable-64.h +++ b/arch/mips/include/asm/pgtable-64.h @@ -110,7 +110,9 @@ #define VMALLOC_START MAP_BASE #define VMALLOC_END \ (VMALLOC_START + \ - PTRS_PER_PGD * PTRS_PER_PMD * PTRS_PER_PTE * PAGE_SIZE - (1UL << 32)) + min(PTRS_PER_PGD * PTRS_PER_PMD * PTRS_PER_PTE * PAGE_SIZE, \ + (1UL<vmbits = fls64(read_c0_entryhi() & 0x3ffffffffffff000ULL); + } else + c->vmbits = 32; +} + #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \ | MIPS_CPU_COUNTER) @@ -967,6 +977,8 @@ __cpuinit void cpu_probe(void) c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1; else c->srsets = 1; + + cpu_set_vmbits(c); } __cpuinit void cpu_report(void) -- 1.6.0.4 From ed.okerson@gmail.com Tue Feb 2 02:02:09 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 02 Feb 2010 02:02:17 +0100 (CET) Received: from mail-ww0-f49.google.com ([74.125.82.49]:57770 "EHLO mail-ww0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492839Ab0BBBCJ (ORCPT ); Tue, 2 Feb 2010 02:02:09 +0100 Received: by wwg30 with SMTP id 30so658343wwg.36 for ; Mon, 01 Feb 2010 17:02:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:date:message-id:subject :from:to:content-type; bh=GaZLB6Dk3RWy4wgi2SdGToY8vYB/Pif7qxiBw6Sk2Ns=; b=vus1cn80kwnQV4HvmmvVCZymu74YmncAyw7jhGw3LkiM2Tin2lFzaoGpasdiv9UwWX goxyS3i+MHDCggLPBoesb1cue4HwRwm3KtwLi/OBXb43hKJXJCTP3efki7k8CNPGK7Yc 7ap42Fpp+DqDAH0reB14vnoNjiB2Kv+2W5ZG4= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:date:message-id:subject:from:to:content-type; b=IaenIMO/ATerVVLriSG3WBqtDagqT8qVkZwgSous2mNxVdNLQB/bfTa3MMQ7G5pwm+ Q+BBBjO/LMHzUus8Pt/UfSZXca5szwiXOGbzV/LD/xzRqhY5XQOl/Oo3XmGNkIbnIuC9 QLLxj46OQw9kdAoJgJ9YOxthmxnnFCXpxD02Q= MIME-Version: 1.0 Received: by 10.216.93.18 with SMTP id k18mr2960331wef.218.1265072524252; Mon, 01 Feb 2010 17:02:04 -0800 (PST) Date: Mon, 1 Feb 2010 19:02:04 -0600 Message-ID: <83f0348b1002011702j305c726ek18e006dc7c4087aa@mail.gmail.com> Subject: Problems compiling old code From: Ed Okerson To: linux-mips Content-Type: text/plain; charset=ISO-8859-1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25838 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ed.okerson@gmail.com Precedence: bulk X-list: linux-mips I just inherited some old code that was previously being built on Cygwin with a very old sde-gcc (2.96). When I attempt to build it on a Linux machine using a more recent cross compiler and toolchain, I get the following errors: mipsel-linux-uclibc-objcopy --output-target=binary prog prog.bin BFD: Warning: Writing section `.text' to huge (ie negative) file offset 0x86bfff4c. BFD: Warning: Writing section `.rodata' to huge (ie negative) file offset 0x86c3e97c. BFD: Warning: Writing section `.data.rel.ro' to huge (ie negative) file offset 0x86c479ec. BFD: Warning: Writing section `.data' to huge (ie negative) file offset 0x86c4896c. BFD: Warning: Writing section `.got' to huge (ie negative) file offset 0x86c4d35c. BFD: Warning: Writing section `.sdata' to huge (ie negative) file offset 0x86c4d84c. mipsel-linux-uclibc-objcopy: prog.bin: File truncated Is there a simple solution to this? My Google skills must be waning as I was unable to find anything helpful. :( Ed Okerson From mcdonald.shane@gmail.com Tue Feb 2 04:03:17 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 02 Feb 2010 04:03:22 +0100 (CET) Received: from mail-vw0-f49.google.com ([209.85.212.49]:62696 "EHLO mail-vw0-f49.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492213Ab0BBDDR (ORCPT ); Tue, 2 Feb 2010 04:03:17 +0100 Received: by vws3 with SMTP id 3so1476799vws.36 for ; Mon, 01 Feb 2010 19:03:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:in-reply-to:references :date:message-id:subject:from:to:cc:content-type; bh=l4W8h5ShC7VA6adPo88oGViBOwtN9EtYREtzTc7jvKI=; b=LNxb/lhiHI93LjMN1BDtzEq8+iIbdOIn5pLZQPPQ25gx25TblMCVH2WXgcr1WjCtqe PZeV7LwHDlv5LbDTtF7vrrh1nKL5EJOjmahyeajYzIFSmsEDYvbCc40WxvMGCUR4r4XJ 5cus+cbaJ5FD4tVRvWbeVm3VqxT6jJA8rLlgc= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type; b=BSVCy4auHc0PZYhHZaEZei3W9d+wJXXjXmJ4vl3ZuWLb+AcJsxyu9nvk8lXkHV/0yn VFhSnVRuvSDJunbpjWhye+c6yCfvE3bjSA9vfmPrEIcIUzJSGKVWHA0OlRV5CoHPMTFM XIxeKgio2HDC1R9W7IFi4pf9m8CYPYeCGM18M= MIME-Version: 1.0 Received: by 10.220.122.88 with SMTP id k24mr6961893vcr.19.1265079790189; Mon, 01 Feb 2010 19:03:10 -0800 (PST) In-Reply-To: <1265015455-32553-1-git-send-email-wuzhangjin@gmail.com> References: <1265015455-32553-1-git-send-email-wuzhangjin@gmail.com> Date: Mon, 1 Feb 2010 21:03:10 -0600 Message-ID: Subject: Re: [PATCH urgent] MIPS: Fixup of the r4k timer From: Shane McDonald To: Wu Zhangjin Cc: ralf@linux-mips.org, David VomLehn , mbizon@freebox.fr, linux-mips@linux-mips.org Content-Type: text/plain; charset=ISO-8859-1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25839 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mcdonald.shane@gmail.com Precedence: bulk X-list: linux-mips On Mon, Feb 1, 2010 at 3:10 AM, Wu Zhangjin wrote: > > From: Wu Zhangjin > > As reported by Maxime Bizon, the commit "MIPS: PowerTV: Fix support for > timer interrupts with > 64 external IRQs" have broken the r4k timer > since it didn't initialize the cp0_compare_irq_shift variable used in > c0_compare_int_pending() on the architectures whose cpu_has_mips_r2 is > false. > > This patch fixes it via initializing the cp0_compare_irq_shift as the > cp0_compare_irq used in the old c0_compare_int_pending(). > > Reported-by: Maxime Bizon > Signed-off-by: Wu Zhangjin When applied to 2.6.33-rc6, this patch fixes the problem on my RM7035C-based system. Tested-by: Shane McDonald From f.fainelli@gmail.com Tue Feb 2 10:07:10 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 02 Feb 2010 10:07:15 +0100 (CET) Received: from mail-ew0-f212.google.com ([209.85.219.212]:61760 "EHLO mail-ew0-f212.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491839Ab0BBJHK (ORCPT ); Tue, 2 Feb 2010 10:07:10 +0100 Received: by ewy4 with SMTP id 4so268608ewy.27 for ; Tue, 02 Feb 2010 01:07:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:sender:from:organization:to :subject:date:user-agent:cc:references:in-reply-to:mime-version :content-type:content-transfer-encoding:message-id; bh=6Egs0spO6FXJ48X62qjvDFsHs+c0oFPxrMCGsuaJEVo=; b=UTh96+VQ2ammSmjpoOQYzbNmwlJvGubLTCJrhdYdfEME3A+GrmwsX07xtbwM4kqHYO vT9VDqS8FIi1eGr707W9N0Pd7qhkcB/+BP0naZHs58Eu18etiEBWd1RDb6GH0/wPYXHc ty1xK6+xQVHJruaI0WhBvIhKWSA0otMzXnzBY= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:from:organization:to:subject:date:user-agent:cc:references :in-reply-to:mime-version:content-type:content-transfer-encoding :message-id; b=S5O4sdHoeujkiVdZl6FhcUAoI2Fd0h0iJmdql9Jy3FuZ49Fae5aHTUPEr9Fkz+fZyX jJGZ59sqqSJqTSXcsO+/DsU9Xu2ppYZVvI8kIJ4a1fxOVhIsAfaxWL1daoqeA3ykcKiD Y4GyXWk02CsZhatEYot8FXzDOSiBNSiZ+hkA4= Received: by 10.213.97.28 with SMTP id j28mr390459ebn.82.1265101623823; Tue, 02 Feb 2010 01:07:03 -0800 (PST) Received: from flexo.localnet (bobafett.staff.proxad.net [213.228.1.121]) by mx.google.com with ESMTPS id 16sm4346211ewy.14.2010.02.02.01.07.02 (version=SSLv3 cipher=RC4-MD5); Tue, 02 Feb 2010 01:07:02 -0800 (PST) From: Florian Fainelli Organization: OpenWrt To: Thomas Bogendoerfer Subject: Re: [PATCH urgent] MIPS: fix micro-assembly overflow in set_except_vector Date: Tue, 2 Feb 2010 10:06:35 +0100 User-Agent: KMail/1.12.2 (Linux/2.6.31-17-server; KDE/4.3.2; x86_64; ; ) Cc: Ralf Baechle , linux-mips@linux-mips.org References: <201002011027.37521.florian@openwrt.org> <20100201103628.GA15661@alpha.franken.de> In-Reply-To: <20100201103628.GA15661@alpha.franken.de> MIME-Version: 1.0 Content-Type: Text/Plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit Message-Id: <201002021006.35731.florian@openwrt.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25840 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips Hi Thomas, On Monday 01 February 2010 11:36:28 Thomas Bogendoerfer wrote: > On Mon, Feb 01, 2010 at 10:27:37AM +0100, Florian Fainelli wrote: > > Commit 24a6d9866c5f15ba7e5b14dc17be4b6edba21d0e broke > > the installation of handlers for boards which have their > > handlers above a 1 << 26 address. Fix this by making sure that > > jump_mask does not excess 0xfc000000 and add the missing ~ operator > > j can handle 28 bit jump targets (26 bit in instruction plus two 0 bits > for 32bit aligment), so 0xf000000 was IMHO fine. Corrected version below, thanks. --- From: Florian Fainelli Subject: [PATCH urgent] MIPS: fix micro-assembly overflow in set_except_vector Commit 24a6d9866c5f15ba7e5b14dc17be4b6edba21d0e broke the installation of handlers for boards which have their handlers above 0xf0000000. Fix this by adding the missing ~ operator to jump_mask when loading the handler target address into buf. Reported-by: Maxime Bizon Acked-by: David Daney Signed-off-by: Florian Fainelli --- diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index 7693929..af176b8 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -1283,7 +1283,7 @@ void __init *set_except_vector(int n, void *addr) u32 *buf = (u32 *)(ebase + 0x200); unsigned int k0 = 26; if ((handler & jump_mask) == ((ebase + 0x200) & jump_mask)) { - uasm_i_j(&buf, handler & jump_mask); + uasm_i_j(&buf, handler & ~jump_mask); uasm_i_nop(&buf); } else { UASM_i_LA(&buf, k0, handler); From f.fainelli@gmail.com Tue Feb 2 10:29:43 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 02 Feb 2010 10:29:46 +0100 (CET) Received: from mail-ew0-f212.google.com ([209.85.219.212]:59056 "EHLO mail-ew0-f212.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491916Ab0BBJ3m (ORCPT ); Tue, 2 Feb 2010 10:29:42 +0100 Received: by ewy4 with SMTP id 4so283341ewy.27 for ; Tue, 02 Feb 2010 01:29:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:sender:from:organization:to :subject:date:user-agent:cc:references:in-reply-to:mime-version :content-type:content-transfer-encoding:message-id; bh=dS52P877A5keSm9avAlhAPh1oWjyYrgwlsgsLIgbSgs=; b=YFMlXeZVt+ln9S66B4hSsD2uaiGS4ZB4ihMRM2wYYGQmuFz28O4E4PpZFVNAuF2/+F yWXmIfPUdSDvxxqZYIV8kFEmEbaZn3N8igSB2PS4mT7oO/xcb16J/pe4CwAECd6xuO2b z6E/ZJBD9FYa63AhYFFpTX3pUq5OEk5v5C+Z8= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:from:organization:to:subject:date:user-agent:cc:references :in-reply-to:mime-version:content-type:content-transfer-encoding :message-id; b=FSPJ8ctJt2KRNjmRlFbdNDlfkoFrUt3rGw+p7W6feGSikk+l66QL+mKZ2AbN0/lSA9 dAQY7KqXEUakcaA0h8G8ebtKNNHr4U5jGjvJRcA6l8kvZIi5n7BPJH4MeRc0uIpjY2ZP AOwhCEGIhPB85JdF76xpHcqj/I3qiCQSZ2Qd4= Received: by 10.213.43.81 with SMTP id v17mr606622ebe.0.1265102977383; Tue, 02 Feb 2010 01:29:37 -0800 (PST) Received: from flexo.localnet (bobafett.staff.proxad.net [213.228.1.121]) by mx.google.com with ESMTPS id 14sm4339274ewy.7.2010.02.02.01.29.35 (version=SSLv3 cipher=RC4-MD5); Tue, 02 Feb 2010 01:29:35 -0800 (PST) From: Florian Fainelli Organization: OpenWrt To: Andreas Mohr Subject: Re: [PATCH 2/2] USB: add Broadcom 63xx integrated EHCI controller support. Date: Tue, 2 Feb 2010 10:29:08 +0100 User-Agent: KMail/1.12.2 (Linux/2.6.31-17-server; KDE/4.3.2; x86_64; ; ) Cc: Alan Stern , Maxime Bizon , David Brownell , linux-usb@vger.kernel.org, Ralf Baechle , linux-mips@linux-mips.org References: <1264874071-28851-3-git-send-email-mbizon@freebox.fr> <20100201063934.GA13692@rhlx01.hs-esslingen.de> In-Reply-To: <20100201063934.GA13692@rhlx01.hs-esslingen.de> MIME-Version: 1.0 Content-Type: Text/Plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit Message-Id: <201002021029.08508.florian@openwrt.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25841 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips Hi, On Monday 01 February 2010 07:39:35 Andreas Mohr wrote: > On Sat, Jan 30, 2010 at 09:11:45PM -0500, Alan Stern wrote: > > On Sat, 30 Jan 2010, Maxime Bizon wrote: > > > +static const struct hc_driver ehci_bcm63xx_hc_driver = { > > > + .description = hcd_name, > > > + .product_desc = "BCM63XX integrated EHCI controller", > > > + .hcd_priv_size = sizeof(struct ehci_hcd), > > > + > > > + .irq = ehci_irq, > > > + .flags = HCD_MEMORY | HCD_USB2, > > > + > > > + .reset = ehci_bcm63xx_setup, > > > + .start = ehci_run, > > > + .stop = ehci_stop, > > > + .shutdown = ehci_shutdown, > > > + > > > + .urb_enqueue = ehci_urb_enqueue, > > > + .urb_dequeue = ehci_urb_dequeue, > > > + .endpoint_disable = ehci_endpoint_disable, > > > + > > > + .get_frame_number = ehci_get_frame, > > > + > > > + .hub_status_data = ehci_hub_status_data, > > > + .hub_control = ehci_hub_control, > > > + .bus_suspend = ehci_bus_suspend, > > > + .bus_resume = ehci_bus_resume, > > > + .relinquish_port = ehci_relinquish_port, > > > + .port_handed_over = ehci_port_handed_over, > > > +}; > > > > You'll run into trouble if you don't include the standard > > endpoint_reset method pointer. > > > > Alan Stern > > And one will run into even more trouble (as did I! hung ports galore...) > if one doesn't include the .clear_tt_buffer_complete callback either, > due to using an outdated non-mainline-synchronized host driver > (that was Broadcom as well, ehci-ssb.c). > The best thing to do is a full review of all _diffs_ in _all_ > usb host kernel files in even moderately recent times (say 2.6.23 - 2.6.33) > and add every missing required item to these bcm63xx host files, too. > > Is your code coming from OpenWrt too by chance? :-P It is not, Maxime wrote it from scratch, I integrated it as part of the brcm63xx port. -- Regards, Florian From yuasa.linux@gmail.com Tue Feb 2 10:40:38 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 02 Feb 2010 10:40:43 +0100 (CET) Received: from mail-gx0-f214.google.com ([209.85.217.214]:59628 "EHLO mail-gx0-f214.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491920Ab0BBJki (ORCPT ); Tue, 2 Feb 2010 10:40:38 +0100 Received: by gxk6 with SMTP id 6so3348784gxk.4 for ; Tue, 02 Feb 2010 01:40:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:sender:date:from:to:cc :subject:message-id:x-mailer:mime-version:content-type :content-transfer-encoding; bh=m9U3v3ioI75SJB5EanVHqg8X6cmZLtZ3ruaspZH3f9E=; b=GPgWtv8g15I312YwMrdaZflA1fuKdLQNhdBo4S5PqVW+Zjy0x3CSFHYNlr/kiLCwV+ YANoPs1R0/kITNayI4++N9FNTRpwqMuKaNZaI7pnYS4+LfzVfcRYbpDjxdyihpwcWJkW rL1Sx9e3Uv6/UdsQkabUnhKsjMhEemd4XnPx0= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:date:from:to:cc:subject:message-id:x-mailer:mime-version :content-type:content-transfer-encoding; b=Tsp9tMixh/i+k/+/HepxGIpJIcC4j4bFCrObiqdiAW+Lc/+bduvEG1Yut8/R6Y4mPA OIa0pkLp4lXY5OiHX4g9n/A5DU2yaacoIJ/jwUcg9qnb53J2sBbOX632XFdq0N6NrBzp Ru9nRisnLkIj+/h0o0/NO2Kud5pYr0lIhBXGE= Received: by 10.101.164.26 with SMTP id r26mr4897056ano.162.1265103631170; Tue, 02 Feb 2010 01:40:31 -0800 (PST) Received: from ypsilon.skybright.jp (sannin29006.nirai.ne.jp [203.160.29.6]) by mx.google.com with ESMTPS id 13sm3911012gxk.9.2010.02.02.01.40.26 (version=TLSv1/SSLv3 cipher=RC4-MD5); Tue, 02 Feb 2010 01:40:28 -0800 (PST) Date: Tue, 2 Feb 2010 18:40:04 +0900 From: Yoichi Yuasa To: Ralf Baechle Cc: yuasa@linux-mips.org, linux-mips , Atsushi Nemoto Subject: [PATCH] MIPS: txx9: remove forced serial console setting Message-Id: <20100202184004.efdff568.yuasa@linux-mips.org> X-Mailer: Sylpheed 2.7.1 (GTK+ 2.16.6; i686-pc-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25842 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: yuasa@linux-mips.org Precedence: bulk X-list: linux-mips It is not always used, even if it is available. Signed-off-by: Yoichi Yuasa --- arch/mips/include/asm/txx9/generic.h | 1 - arch/mips/txx9/generic/setup.c | 5 ----- arch/mips/txx9/jmr3927/setup.c | 7 ------- arch/mips/txx9/rbtx4927/setup.c | 7 ------- arch/mips/txx9/rbtx4938/setup.c | 6 ------ 5 files changed, 0 insertions(+), 26 deletions(-) diff --git a/arch/mips/include/asm/txx9/generic.h b/arch/mips/include/asm/txx9/generic.h index 827dc22..64887d3 100644 --- a/arch/mips/include/asm/txx9/generic.h +++ b/arch/mips/include/asm/txx9/generic.h @@ -42,7 +42,6 @@ struct txx9_board_vec { }; extern struct txx9_board_vec *txx9_board_vec; extern int (*txx9_irq_dispatch)(int pending); -char *prom_getcmdline(void); const char *prom_getenv(const char *name); void txx9_wdt_init(unsigned long base); void txx9_wdt_now(unsigned long base); diff --git a/arch/mips/txx9/generic/setup.c b/arch/mips/txx9/generic/setup.c index e27809b..7174d83 100644 --- a/arch/mips/txx9/generic/setup.c +++ b/arch/mips/txx9/generic/setup.c @@ -399,11 +399,6 @@ const char *get_system_type(void) return txx9_system_type; } -char * __init prom_getcmdline(void) -{ - return &(arcs_cmdline[0]); -} - const char *__init prom_getenv(const char *name) { const s32 *str; diff --git a/arch/mips/txx9/jmr3927/setup.c b/arch/mips/txx9/jmr3927/setup.c index 25e50a7..3206f76 100644 --- a/arch/mips/txx9/jmr3927/setup.c +++ b/arch/mips/txx9/jmr3927/setup.c @@ -67,8 +67,6 @@ static void jmr3927_board_init(void); static void __init jmr3927_mem_setup(void) { - char *argptr; - set_io_port_base(JMR3927_PORT_BASE + JMR3927_PCIIO); _machine_restart = jmr3927_machine_restart; @@ -97,11 +95,6 @@ static void __init jmr3927_mem_setup(void) jmr3927_board_init(); tx3927_sio_init(0, 1 << 1); /* ch1: noCTS */ -#ifdef CONFIG_SERIAL_TXX9_CONSOLE - argptr = prom_getcmdline(); - if (!strstr(argptr, "console=")) - strcat(argptr, " console=ttyS1,115200"); -#endif } static void __init jmr3927_pci_setup(void) diff --git a/arch/mips/txx9/rbtx4927/setup.c b/arch/mips/txx9/rbtx4927/setup.c index ee468ea..b15adfc 100644 --- a/arch/mips/txx9/rbtx4927/setup.c +++ b/arch/mips/txx9/rbtx4927/setup.c @@ -187,8 +187,6 @@ static void __init rbtx4937_clock_init(void); static void __init rbtx4927_mem_setup(void) { - char *argptr; - if (TX4927_REV_PCODE() == 0x4927) { rbtx4927_clock_init(); tx4927_setup(); @@ -213,11 +211,6 @@ static void __init rbtx4927_mem_setup(void) gpio_direction_output(15, 1); tx4927_sio_init(0, 0); -#ifdef CONFIG_SERIAL_TXX9_CONSOLE - argptr = prom_getcmdline(); - if (!strstr(argptr, "console=")) - strcat(argptr, " console=ttyS0,38400"); -#endif } static void __init rbtx4927_clock_init(void) diff --git a/arch/mips/txx9/rbtx4938/setup.c b/arch/mips/txx9/rbtx4938/setup.c index d66509b..d6e70da 100644 --- a/arch/mips/txx9/rbtx4938/setup.c +++ b/arch/mips/txx9/rbtx4938/setup.c @@ -153,7 +153,6 @@ static void __init rbtx4938_time_init(void) static void __init rbtx4938_mem_setup(void) { unsigned long long pcfg; - char *argptr; if (txx9_master_clock == 0) txx9_master_clock = 25000000; /* 25MHz */ @@ -168,11 +167,6 @@ static void __init rbtx4938_mem_setup(void) #endif tx4938_sio_init(7372800, 0); -#ifdef CONFIG_SERIAL_TXX9_CONSOLE - argptr = prom_getcmdline(); - if (!strstr(argptr, "console=")) - strcat(argptr, " console=ttyS0,38400"); -#endif #ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_PIO58_61 pr_info("PIOSEL: disabling both ATA and NAND selection\n"); -- 1.6.6.1 From sshtylyov@ru.mvista.com Tue Feb 2 11:04:54 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 02 Feb 2010 11:04:58 +0100 (CET) Received: from mail.dev.rtsoft.ru ([213.79.90.226]:42759 "HELO mail.dev.rtsoft.ru" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with SMTP id S1491920Ab0BBKEy (ORCPT ); Tue, 2 Feb 2010 11:04:54 +0100 Received: (qmail 25227 invoked from network); 2 Feb 2010 10:04:53 -0000 Received: from unknown (HELO ?127.0.0.1?) (192.168.1.70) by 0 with SMTP; 2 Feb 2010 10:04:53 -0000 Message-ID: <4B67F8A8.6000706@ru.mvista.com> Date: Tue, 02 Feb 2010 13:04:24 +0300 From: Sergei Shtylyov User-Agent: Thunderbird 2.0.0.23 (Windows/20090812) MIME-Version: 1.0 To: Guenter Roeck CC: linux-mips@linux-mips.org Subject: Re: [PATCH v4] Virtual memory size detection for 64 bit MIPS CPUs References: <1265068979-12052-1-git-send-email-guenter.roeck@ericsson.com> In-Reply-To: <1265068979-12052-1-git-send-email-guenter.roeck@ericsson.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25843 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sshtylyov@ru.mvista.com Precedence: bulk X-list: linux-mips Hello. Guenter Roeck wrote: > Linux kernel 2.6.32 and later allocates memory from the top of virtual memory > space. > > This patch implements virtual memory size detection for 64 bit MIPS CPUs > to avoid resulting crashes. > > Signed-off-by: Guenter Roeck > [...] > diff --git a/arch/mips/include/asm/pgtable-64.h b/arch/mips/include/asm/pgtable-64.h > index 9cd5089..259ec58 100644 > --- a/arch/mips/include/asm/pgtable-64.h > +++ b/arch/mips/include/asm/pgtable-64.h > @@ -110,7 +110,9 @@ > #define VMALLOC_START MAP_BASE > #define VMALLOC_END \ > (VMALLOC_START + \ > - PTRS_PER_PGD * PTRS_PER_PMD * PTRS_PER_PTE * PAGE_SIZE - (1UL << 32)) > + min(PTRS_PER_PGD * PTRS_PER_PMD * PTRS_PER_PTE * PAGE_SIZE, \ > + (1UL< Why you've added spaces around the second << but not around the first? Should be more consistent. > + > #if defined(CONFIG_MODULES) && defined(KBUILD_64BIT_SYM32) && \ > VMALLOC_START != CKSSEG > /* Load modules into 32bit-compatible segment. */ > diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c > index 7a51866..ac9aca1 100644 > --- a/arch/mips/kernel/cpu-probe.c > +++ b/arch/mips/kernel/cpu-probe.c > @@ -282,6 +282,16 @@ static inline int __cpu_has_fpu(void) > return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE); > } > > +static inline void cpu_set_vmbits(struct cpuinfo_mips *c) > +{ > + if (cpu_has_64bits) { > + write_c0_entryhi(0xfffffffffffff000ULL); > + back_to_back_c0_hazard(); > + c->vmbits = fls64(read_c0_entryhi() & 0x3ffffffffffff000ULL); > I don't quite understand why set bits 62-63 only to mask them off later... WBR, Sergei From prvs=6426729b5=groeck@redback.com Tue Feb 2 11:53:58 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 02 Feb 2010 11:54:06 +0100 (CET) Received: from mgate.redback.com ([155.53.3.41]:23982 "EHLO mgate.redback.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492089Ab0BBKx6 (ORCPT ); Tue, 2 Feb 2010 11:53:58 +0100 X-IronPort-AV: E=Sophos;i="4.49,389,1262592000"; d="scan'208";a="7759509" Received: from prattle.redback.com ([155.53.12.9]) by mgate.redback.com with ESMTP; 02 Feb 2010 02:53:56 -0800 Received: from localhost (localhost [127.0.0.1]) by prattle.redback.com (Postfix) with ESMTP id 596251539A9C; Tue, 2 Feb 2010 02:53:56 -0800 (PST) Received: from prattle.redback.com ([127.0.0.1]) by localhost (prattle [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 07551-09; Tue, 2 Feb 2010 02:53:56 -0800 (PST) Received: from localhost (rbos-pc-13.lab.redback.com [10.12.11.133]) by prattle.redback.com (Postfix) with ESMTP id 485A81539A9B; Tue, 2 Feb 2010 02:53:52 -0800 (PST) From: Guenter Roeck To: linux-mips@linux-mips.org Cc: Guenter Roeck Subject: [PATCH v5] Virtual memory size detection for 64 bit MIPS CPUs Date: Tue, 2 Feb 2010 02:37:41 -0800 Message-Id: <1265107061-18355-1-git-send-email-guenter.roeck@ericsson.com> X-Mailer: git-send-email 1.6.0.4 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25844 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: guenter.roeck@ericsson.com Precedence: bulk X-list: linux-mips Linux kernel 2.6.32 and later allocates memory from the top of virtual memory space. This patch implements virtual memory size detection for 64 bit MIPS CPUs to avoid resulting crashes. Signed-off-by: Guenter Roeck --- arch/mips/include/asm/cpu-features.h | 3 +++ arch/mips/include/asm/cpu-info.h | 1 + arch/mips/include/asm/pgtable-64.h | 4 +++- arch/mips/kernel/cpu-probe.c | 12 ++++++++++++ 4 files changed, 19 insertions(+), 1 deletions(-) diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h index 1f4df64..284eb55 100644 --- a/arch/mips/include/asm/cpu-features.h +++ b/arch/mips/include/asm/cpu-features.h @@ -209,6 +209,9 @@ # ifndef cpu_has_64bit_addresses # define cpu_has_64bit_addresses 1 # endif +# ifndef cpu_vmbits +# define cpu_vmbits cpu_data[0].vmbits +# endif #endif #if defined(CONFIG_CPU_MIPSR2_IRQ_VI) && !defined(cpu_has_vint) diff --git a/arch/mips/include/asm/cpu-info.h b/arch/mips/include/asm/cpu-info.h index 1260443..3c694bc 100644 --- a/arch/mips/include/asm/cpu-info.h +++ b/arch/mips/include/asm/cpu-info.h @@ -58,6 +58,7 @@ struct cpuinfo_mips { struct cache_desc tcache; /* Tertiary/split secondary cache */ int srsets; /* Shadow register sets */ int core; /* physical core number */ + int vmbits; /* Virtual memory size in bits */ #if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_MIPS_MT_SMTC) /* * In the MIPS MT "SMTC" model, each TC is considered diff --git a/arch/mips/include/asm/pgtable-64.h b/arch/mips/include/asm/pgtable-64.h index 9cd5089..8eda30b 100644 --- a/arch/mips/include/asm/pgtable-64.h +++ b/arch/mips/include/asm/pgtable-64.h @@ -110,7 +110,9 @@ #define VMALLOC_START MAP_BASE #define VMALLOC_END \ (VMALLOC_START + \ - PTRS_PER_PGD * PTRS_PER_PMD * PTRS_PER_PTE * PAGE_SIZE - (1UL << 32)) + min(PTRS_PER_PGD * PTRS_PER_PMD * PTRS_PER_PTE * PAGE_SIZE, \ + (1UL << cpu_vmbits)) - (1UL << 32)) + #if defined(CONFIG_MODULES) && defined(KBUILD_64BIT_SYM32) && \ VMALLOC_START != CKSSEG /* Load modules into 32bit-compatible segment. */ diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index 7a51866..21dc4b8 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -282,6 +282,16 @@ static inline int __cpu_has_fpu(void) return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE); } +static inline void cpu_set_vmbits(struct cpuinfo_mips *c) +{ + if (cpu_has_64bits) { + write_c0_entryhi(0x3ffffffffffff000ULL); + back_to_back_c0_hazard(); + c->vmbits = fls64(read_c0_entryhi() & 0x3ffffffffffff000ULL); + } else + c->vmbits = 32; +} + #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \ | MIPS_CPU_COUNTER) @@ -967,6 +977,8 @@ __cpuinit void cpu_probe(void) c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1; else c->srsets = 1; + + cpu_set_vmbits(c); } __cpuinit void cpu_report(void) -- 1.6.0.4 From ralf@linux-mips.org Tue Feb 2 12:42:47 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 02 Feb 2010 12:42:51 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:46597 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1492230Ab0BBLmr (ORCPT ); Tue, 2 Feb 2010 12:42:47 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id o12Bh11Z011980; Tue, 2 Feb 2010 12:43:02 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id o12Bgx9E011972; Tue, 2 Feb 2010 12:42:59 +0100 Date: Tue, 2 Feb 2010 12:42:59 +0100 From: Ralf Baechle To: Guenter Roeck Cc: David Daney , "linux-mips@linux-mips.org" , "Maciej W. Rozycki" Subject: Re: [PATCH v3] Virtual memory size detection for 64 bit MIPS CPUs Message-ID: <20100202114259.GA10837@linux-mips.org> References: <1265064686-31278-1-git-send-email-guenter.roeck@ericsson.com> <4B676755.10600@caviumnetworks.com> <20100202001026.GA6883@ericsson.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20100202001026.GA6883@ericsson.com> User-Agent: Mutt/1.5.20 (2009-08-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25845 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Mon, Feb 01, 2010 at 04:10:26PM -0800, Guenter Roeck wrote: > > > + if (cpu_has_64bits) { > > > + write_c0_entryhi(0xfffffffffffff000ULL); > > > > macro indicated that we need to avoid hazards here on R4000. A MTC0 instruction on an R4000 writes EntryHi on pipeline stage 7 but will read from the same register on stage 4 which leaves a window of 2 instructions, that is 2 NOP instructions needed. > > Perhaps adding: > > > > back_to_back_c0_hazard(); > > > Compiler already added a nop, so I thought it wasn't necessary. > Doesn't hurt either, so I'll put it in. This probe is needed as per MIPSxx architecture spec and several CPUs will missbehave without it. The 74K which of course is 32-bit but it illustrates the issue might even issue these instructions out of order. back_to_back_c0_hazard will expand into a suitable sequence to handle the pipeline hazard. And we can't trust on the compiler doing the right thing here; as explained above we might need multiple nops and some CPUs will need other instructions to deal with the hazard, for example a number of SSNOPs or an EHB instruction. Ralf From ralf@linux-mips.org Tue Feb 2 14:01:41 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 02 Feb 2010 14:01:45 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:33848 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1492262Ab0BBNBl (ORCPT ); Tue, 2 Feb 2010 14:01:41 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id o12D1sSb013930; Tue, 2 Feb 2010 14:01:54 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id o12D1rbB013929; Tue, 2 Feb 2010 14:01:53 +0100 Date: Tue, 2 Feb 2010 14:01:53 +0100 From: Ralf Baechle To: Guenter Roeck Cc: linux-mips@linux-mips.org Subject: Re: [PATCH v5] Virtual memory size detection for 64 bit MIPS CPUs Message-ID: <20100202130153.GB10837@linux-mips.org> References: <1265107061-18355-1-git-send-email-guenter.roeck@ericsson.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1265107061-18355-1-git-send-email-guenter.roeck@ericsson.com> User-Agent: Mutt/1.5.20 (2009-08-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25846 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Tue, Feb 02, 2010 at 02:37:41AM -0800, Guenter Roeck wrote: Pretty good, let the nitpicking start :-) > diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h > index 1f4df64..284eb55 100644 > --- a/arch/mips/include/asm/cpu-features.h > +++ b/arch/mips/include/asm/cpu-features.h > @@ -209,6 +209,9 @@ > # ifndef cpu_has_64bit_addresses > # define cpu_has_64bit_addresses 1 > # endif > +# ifndef cpu_vmbits > +# define cpu_vmbits cpu_data[0].vmbits > +# endif > #endif For 32-bit kernels we probably should fix cpu_vmbits to 31. #ifdef CONFIG_64BIT # ifndef cpu_vmbits # define cpu_vmbits cpu_data[0].vmbits # define __NEED_VMBITS # endif #else # #define cpu_vmbits 31 #endif > #if defined(CONFIG_CPU_MIPSR2_IRQ_VI) && !defined(cpu_has_vint) > diff --git a/arch/mips/include/asm/cpu-info.h b/arch/mips/include/asm/cpu-info.h > index 1260443..3c694bc 100644 > --- a/arch/mips/include/asm/cpu-info.h > +++ b/arch/mips/include/asm/cpu-info.h > @@ -58,6 +58,7 @@ struct cpuinfo_mips { > struct cache_desc tcache; /* Tertiary/split secondary cache */ > int srsets; /* Shadow register sets */ > int core; /* physical core number */ > + int vmbits; /* Virtual memory size in bits */ #ifdef __NEED_VMBITS int vmbits; /* Virtual memory size in bits */ #endif To do for a later separate patch - minimize the sizes of all cpuinfo_mips members; int is overkill for many members. > #if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_MIPS_MT_SMTC) > /* > * In the MIPS MT "SMTC" model, each TC is considered > diff --git a/arch/mips/include/asm/pgtable-64.h b/arch/mips/include/asm/pgtable-64.h > index 9cd5089..8eda30b 100644 > --- a/arch/mips/include/asm/pgtable-64.h > +++ b/arch/mips/include/asm/pgtable-64.h > @@ -110,7 +110,9 @@ > #define VMALLOC_START MAP_BASE > #define VMALLOC_END \ > (VMALLOC_START + \ > - PTRS_PER_PGD * PTRS_PER_PMD * PTRS_PER_PTE * PAGE_SIZE - (1UL << 32)) > + min(PTRS_PER_PGD * PTRS_PER_PMD * PTRS_PER_PTE * PAGE_SIZE, \ > + (1UL << cpu_vmbits)) - (1UL << 32)) > + This overlaps with other allocations near the top - yes, we've been living dangerous but with bottom up allocations a conflict was very, very unlikely. Dealing with them in a sane way in the VMALLOC_END macro definition is hard, so I suggest changing the definition to something like: extern unsigned long vmalloc_end; #define VMALLOC_START MAP_BASE #define VMALLOC_END vmalloc_end And initialize the value of vmalloc_end in something like the mm section of arch/mips/kernel/traps.c:per_cpu_trap_init(). There you can also ensure the value of vmalloc_end is <= FIXADDR_START. Finally probing can be used to fix yet another sin. For 64-bit kernels arch/mips/include/asm/processor.h defines TASK_SIZE: #define TASK_SIZE 0x10000000000UL This should turn into something like. #define TASK_SIZE (1UL << vmbits) This is also why I sugget to keep vmbits as 31, not 32. Hello S390 :-) > +static inline void cpu_set_vmbits(struct cpuinfo_mips *c) > +{ > + if (cpu_has_64bits) { > + write_c0_entryhi(0x3ffffffffffff000ULL); > + back_to_back_c0_hazard(); > + c->vmbits = fls64(read_c0_entryhi() & 0x3ffffffffffff000ULL); > + } else > + c->vmbits = 32; > +} With my changes suggested above this would need changing to something like: static inline void cpu_set_vmbits(struct cpuinfo_mips *c) { if (__NEED_VMBITS) { write_c0_entryhi(0x3ffffffffffff000ULL); back_to_back_c0_hazard(); c->vmbits = fls64(read_c0_entryhi() & 0x3ffffffffffff000ULL); return; } BUG(); } > #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \ > | MIPS_CPU_COUNTER) > > @@ -967,6 +977,8 @@ __cpuinit void cpu_probe(void) > c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1; > else > c->srsets = 1; > + > + cpu_set_vmbits(c); I think a name like cpu_probe_vmbits() would be clearer. Thanks, Ralf From dmitri.vorobiev@gmail.com Tue Feb 2 14:05:56 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 02 Feb 2010 14:06:05 +0100 (CET) Received: from mail-fx0-f227.google.com ([209.85.220.227]:34480 "EHLO mail-fx0-f227.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492258Ab0BBNF4 (ORCPT ); Tue, 2 Feb 2010 14:05:56 +0100 Received: by fxm27 with SMTP id 27so11073fxm.27 for ; Tue, 02 Feb 2010 05:05:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:in-reply-to:references :date:message-id:subject:from:to:cc:content-type; bh=swQIizYQEDK8IGtjBki61mrajeatRPWCHxFN1hfX4/c=; b=UFD8qrtW+CVBv27u1L6g385arALva/I8IKY2uSUxdK3y/yM099hpJiFqo9V27IBhMn SCY3r7zYAnCyjyADMbVYOKexDO78dlA6sf6BZbEcw/U4JuSynbhCe1yKf8NLgZqzbaBP i2IJvsHRyJ+NQzk4RkSJG+H/doyfl9fnx0Syw= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type; b=YpzffDVchOSgxKk6eGlPOLu2NNLK2MtTUMGDyIPAJcGxY+VBlF/c2ihHAeO2CtYrTM M4nbTEVqxU68dfSkZ96tEEi9DoC8Nhu7Xrx1Un7wRgiOQfZTRodxN5jocxH9fIGdaR7h 61ENflZtxEC+3xgBoRH3CXxFLTMvIr/egY1Tk= MIME-Version: 1.0 Received: by 10.223.5.24 with SMTP id 24mr2882511fat.103.1265115949340; Tue, 02 Feb 2010 05:05:49 -0800 (PST) In-Reply-To: <20100202130153.GB10837@linux-mips.org> References: <1265107061-18355-1-git-send-email-guenter.roeck@ericsson.com> <20100202130153.GB10837@linux-mips.org> Date: Tue, 2 Feb 2010 15:05:49 +0200 Message-ID: <90edad821002020505x6ecfd03ejb03f316d9859b9db@mail.gmail.com> Subject: Re: [PATCH v5] Virtual memory size detection for 64 bit MIPS CPUs From: Dmitri Vorobiev To: Ralf Baechle Cc: Guenter Roeck , linux-mips@linux-mips.org Content-Type: text/plain; charset=ISO-8859-1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25847 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dmitri.vorobiev@gmail.com Precedence: bulk X-list: linux-mips On Tue, Feb 2, 2010 at 3:01 PM, Ralf Baechle wrote: > On Tue, Feb 02, 2010 at 02:37:41AM -0800, Guenter Roeck wrote: > > Pretty good, let the nitpicking start :-) I haven't been following this closely enough, so maybe my question is stupid. However: will this work on SGI R5000? I'm using an Indy, so I'm quite concerned about this CPU. Thanks, Dmitri > >> diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h >> index 1f4df64..284eb55 100644 >> --- a/arch/mips/include/asm/cpu-features.h >> +++ b/arch/mips/include/asm/cpu-features.h >> @@ -209,6 +209,9 @@ >> # ifndef cpu_has_64bit_addresses >> # define cpu_has_64bit_addresses 1 >> # endif >> +# ifndef cpu_vmbits >> +# define cpu_vmbits cpu_data[0].vmbits >> +# endif >> #endif > > For 32-bit kernels we probably should fix cpu_vmbits to 31. > > #ifdef CONFIG_64BIT > # ifndef cpu_vmbits > # define cpu_vmbits cpu_data[0].vmbits > # define __NEED_VMBITS > # endif > #else > # #define cpu_vmbits 31 > #endif > >> #if defined(CONFIG_CPU_MIPSR2_IRQ_VI) && !defined(cpu_has_vint) >> diff --git a/arch/mips/include/asm/cpu-info.h b/arch/mips/include/asm/cpu-info.h >> index 1260443..3c694bc 100644 >> --- a/arch/mips/include/asm/cpu-info.h >> +++ b/arch/mips/include/asm/cpu-info.h >> @@ -58,6 +58,7 @@ struct cpuinfo_mips { >> struct cache_desc tcache; /* Tertiary/split secondary cache */ >> int srsets; /* Shadow register sets */ >> int core; /* physical core number */ >> + int vmbits; /* Virtual memory size in bits */ > > #ifdef __NEED_VMBITS > int vmbits; /* Virtual memory size in bits */ > #endif > > To do for a later separate patch - minimize the sizes of all cpuinfo_mips > members; int is overkill for many members. > >> #if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_MIPS_MT_SMTC) >> /* >> * In the MIPS MT "SMTC" model, each TC is considered >> diff --git a/arch/mips/include/asm/pgtable-64.h b/arch/mips/include/asm/pgtable-64.h >> index 9cd5089..8eda30b 100644 >> --- a/arch/mips/include/asm/pgtable-64.h >> +++ b/arch/mips/include/asm/pgtable-64.h >> @@ -110,7 +110,9 @@ >> #define VMALLOC_START MAP_BASE >> #define VMALLOC_END \ >> (VMALLOC_START + \ >> - PTRS_PER_PGD * PTRS_PER_PMD * PTRS_PER_PTE * PAGE_SIZE - (1UL << 32)) >> + min(PTRS_PER_PGD * PTRS_PER_PMD * PTRS_PER_PTE * PAGE_SIZE, \ >> + (1UL << cpu_vmbits)) - (1UL << 32)) >> + > > This overlaps with other allocations near the top - yes, we've been living > dangerous but with bottom up allocations a conflict was very, very unlikely. > > Dealing with them in a sane way in the VMALLOC_END macro definition is hard, > so I suggest changing the definition to something like: > > extern unsigned long vmalloc_end; > > #define VMALLOC_START MAP_BASE > #define VMALLOC_END vmalloc_end > > And initialize the value of vmalloc_end in something like the mm section of > arch/mips/kernel/traps.c:per_cpu_trap_init(). > > There you can also ensure the value of vmalloc_end is <= FIXADDR_START. > > Finally probing can be used to fix yet another sin. For 64-bit kernels > arch/mips/include/asm/processor.h defines TASK_SIZE: > > #define TASK_SIZE 0x10000000000UL > > This should turn into something like. > > #define TASK_SIZE (1UL << vmbits) > > This is also why I sugget to keep vmbits as 31, not 32. Hello S390 :-) > >> +static inline void cpu_set_vmbits(struct cpuinfo_mips *c) >> +{ >> + if (cpu_has_64bits) { >> + write_c0_entryhi(0x3ffffffffffff000ULL); >> + back_to_back_c0_hazard(); >> + c->vmbits = fls64(read_c0_entryhi() & 0x3ffffffffffff000ULL); >> + } else >> + c->vmbits = 32; >> +} > > With my changes suggested above this would need changing to something like: > > static inline void cpu_set_vmbits(struct cpuinfo_mips *c) > { > if (__NEED_VMBITS) { > write_c0_entryhi(0x3ffffffffffff000ULL); > back_to_back_c0_hazard(); > c->vmbits = fls64(read_c0_entryhi() & 0x3ffffffffffff000ULL); > > return; > } > > BUG(); > } > >> #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \ >> | MIPS_CPU_COUNTER) >> >> @@ -967,6 +977,8 @@ __cpuinit void cpu_probe(void) >> c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1; >> else >> c->srsets = 1; >> + >> + cpu_set_vmbits(c); > > I think a name like cpu_probe_vmbits() would be clearer. > > Thanks, > > Ralf > > From ralf@linux-mips.org Tue Feb 2 14:10:01 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 02 Feb 2010 14:10:04 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:37838 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1492245Ab0BBNKA (ORCPT ); Tue, 2 Feb 2010 14:10:00 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id o12DAGSS014197; Tue, 2 Feb 2010 14:10:16 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id o12DAGVv014196; Tue, 2 Feb 2010 14:10:16 +0100 Date: Tue, 2 Feb 2010 14:10:16 +0100 From: Ralf Baechle To: Dmitri Vorobiev Cc: Guenter Roeck , linux-mips@linux-mips.org Subject: Re: [PATCH v5] Virtual memory size detection for 64 bit MIPS CPUs Message-ID: <20100202131015.GB13987@linux-mips.org> References: <1265107061-18355-1-git-send-email-guenter.roeck@ericsson.com> <20100202130153.GB10837@linux-mips.org> <90edad821002020505x6ecfd03ejb03f316d9859b9db@mail.gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <90edad821002020505x6ecfd03ejb03f316d9859b9db@mail.gmail.com> User-Agent: Mutt/1.5.20 (2009-08-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25848 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Tue, Feb 02, 2010 at 03:05:49PM +0200, Dmitri Vorobiev wrote: > On Tue, Feb 2, 2010 at 3:01 PM, Ralf Baechle wrote: > > On Tue, Feb 02, 2010 at 02:37:41AM -0800, Guenter Roeck wrote: > > > > Pretty good, let the nitpicking start :-) > > I haven't been following this closely enough, so maybe my question is > stupid. However: will this work on SGI R5000? I'm using an Indy, so > I'm quite concerned about this CPU. The point is that your Indy right now is not working with a 64-bit kernel :) Ralf From dmitri.vorobiev@gmail.com Tue Feb 2 14:34:41 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 02 Feb 2010 14:34:45 +0100 (CET) Received: from mail-fx0-f227.google.com ([209.85.220.227]:64356 "EHLO mail-fx0-f227.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492289Ab0BBNel (ORCPT ); Tue, 2 Feb 2010 14:34:41 +0100 Received: by fxm27 with SMTP id 27so44256fxm.27 for ; Tue, 02 Feb 2010 05:34:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:in-reply-to:references :date:message-id:subject:from:to:cc:content-type; bh=ZhDOqbP4kckl3CPUFt5mVwrLiBx78az/wWrYrXoLdyw=; b=dpHNgn9eOQnYMgM0uM8lqoNljCLoEleYAEI15Ypc+mbdF2gvfPzbvfXVLkmOEKaPHA IJyAoF4kkc0Nbp689Ai9O5miaNfZBKTIy1yl0wqAY9qAhaDgsXznuVPaQN1gWr5u1UVV 8ihjCSdMlo4E7/SfguQP120JK+Am5gI/5U+ME= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type; b=VogBmfmuEmeR9GkhyZxXYEPwSfUN3EqBe5r7AuPkEiVlfZVj+40Pcra3hOsJ/jRhxq qZXV3XgmmlvOxJRcoFKjHboJKt1mliTD/u87lEnuJa37pU2MOrj+wQWpiZ05kRVM3xzQ 0ApJ1LYmpaIB6RSMt9jpmmVdMwkW/tpQSb92A= MIME-Version: 1.0 Received: by 10.223.63.193 with SMTP id c1mr6205244fai.80.1265117671595; Tue, 02 Feb 2010 05:34:31 -0800 (PST) In-Reply-To: <20100202131015.GB13987@linux-mips.org> References: <1265107061-18355-1-git-send-email-guenter.roeck@ericsson.com> <20100202130153.GB10837@linux-mips.org> <90edad821002020505x6ecfd03ejb03f316d9859b9db@mail.gmail.com> <20100202131015.GB13987@linux-mips.org> Date: Tue, 2 Feb 2010 15:34:31 +0200 Message-ID: <90edad821002020534s54c4120atb7ac183f39d44847@mail.gmail.com> Subject: Re: [PATCH v5] Virtual memory size detection for 64 bit MIPS CPUs From: Dmitri Vorobiev To: Ralf Baechle Cc: Guenter Roeck , linux-mips@linux-mips.org Content-Type: text/plain; charset=ISO-8859-1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25849 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dmitri.vorobiev@gmail.com Precedence: bulk X-list: linux-mips On Tue, Feb 2, 2010 at 3:10 PM, Ralf Baechle wrote: > On Tue, Feb 02, 2010 at 03:05:49PM +0200, Dmitri Vorobiev wrote: > >> On Tue, Feb 2, 2010 at 3:01 PM, Ralf Baechle wrote: >> > On Tue, Feb 02, 2010 at 02:37:41AM -0800, Guenter Roeck wrote: >> > >> > Pretty good, let the nitpicking start :-) >> >> I haven't been following this closely enough, so maybe my question is >> stupid. However: will this work on SGI R5000? I'm using an Indy, so >> I'm quite concerned about this CPU. > > The point is that your Indy right now is not working with a 64-bit kernel :) I know. :) What I was asking about was whether my Indy is going to work with the new scheme of calculating VMALLOC_END. Dmitri > > Ralf > From ralf@linux-mips.org Tue Feb 2 14:45:59 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 02 Feb 2010 14:46:03 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:56936 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1492247Ab0BBNp7 (ORCPT ); Tue, 2 Feb 2010 14:45:59 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id o12DkEXR015076; Tue, 2 Feb 2010 14:46:14 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id o12DkECX015074; Tue, 2 Feb 2010 14:46:14 +0100 Date: Tue, 2 Feb 2010 14:46:13 +0100 From: Ralf Baechle To: Dmitri Vorobiev Cc: Guenter Roeck , linux-mips@linux-mips.org Subject: Re: [PATCH v5] Virtual memory size detection for 64 bit MIPS CPUs Message-ID: <20100202134613.GD13987@linux-mips.org> References: <1265107061-18355-1-git-send-email-guenter.roeck@ericsson.com> <20100202130153.GB10837@linux-mips.org> <90edad821002020505x6ecfd03ejb03f316d9859b9db@mail.gmail.com> <20100202131015.GB13987@linux-mips.org> <90edad821002020534s54c4120atb7ac183f39d44847@mail.gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <90edad821002020534s54c4120atb7ac183f39d44847@mail.gmail.com> User-Agent: Mutt/1.5.20 (2009-08-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25850 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Tue, Feb 02, 2010 at 03:34:31PM +0200, Dmitri Vorobiev wrote: > >> I haven't been following this closely enough, so maybe my question is > >> stupid. However: will this work on SGI R5000? I'm using an Indy, so > >> I'm quite concerned about this CPU. > > > > The point is that your Indy right now is not working with a 64-bit kernel :) > > I know. :) > > What I was asking about was whether my Indy is going to work with the > new scheme of calculating VMALLOC_END. Of course it will. Ralf From dmitri.vorobiev@gmail.com Tue Feb 2 14:49:55 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 02 Feb 2010 14:49:58 +0100 (CET) Received: from mail-fx0-f227.google.com ([209.85.220.227]:44146 "EHLO mail-fx0-f227.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492262Ab0BBNty (ORCPT ); Tue, 2 Feb 2010 14:49:54 +0100 Received: by fxm27 with SMTP id 27so61414fxm.27 for ; Tue, 02 Feb 2010 05:49:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:in-reply-to:references :date:message-id:subject:from:to:cc:content-type; bh=j+YRzQop0cnP/ogiHMfiqcuL7p6Ovef3oy8qyyPkxpk=; b=aquum+FF2yoFaKY77TnRUEjLCjl/pOdKTRojnIt33UhuDZum78J+4zZ9B8pE2NHmcY h9I3E4GnEPsL3ObQJKgJ7/OhoDEZz+InkqguhNIJ8fwjtPJ78E/479BgIM2FZALpooUn z1FpdHVfFaKWKKjhJNfIELVEq6RGUmvgyv9Sw= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type; b=ADJ0U658exe4rqWwZyhGtfHq+sALqXOoO7jitxYhzwom5mCgp97ogErnNRcRvthn/o 5BGDmwMDC6iKMFQHWiT53M1VtJMV9DuPjyDjjGAb3sea0QtWvt9Ui0XKSyQ7t+5MZina 6+52qxQX7Bac+jeSmcbV/RVjuIv1Pearvd9Mo= MIME-Version: 1.0 Received: by 10.223.4.25 with SMTP id 25mr1229969fap.38.1265118589669; Tue, 02 Feb 2010 05:49:49 -0800 (PST) In-Reply-To: <20100202134613.GD13987@linux-mips.org> References: <1265107061-18355-1-git-send-email-guenter.roeck@ericsson.com> <20100202130153.GB10837@linux-mips.org> <90edad821002020505x6ecfd03ejb03f316d9859b9db@mail.gmail.com> <20100202131015.GB13987@linux-mips.org> <90edad821002020534s54c4120atb7ac183f39d44847@mail.gmail.com> <20100202134613.GD13987@linux-mips.org> Date: Tue, 2 Feb 2010 15:49:49 +0200 Message-ID: <90edad821002020549q8c75cbck2f2a0a0928871ec0@mail.gmail.com> Subject: Re: [PATCH v5] Virtual memory size detection for 64 bit MIPS CPUs From: Dmitri Vorobiev To: Ralf Baechle Cc: Guenter Roeck , linux-mips@linux-mips.org Content-Type: text/plain; charset=ISO-8859-1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25851 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dmitri.vorobiev@gmail.com Precedence: bulk X-list: linux-mips On Tue, Feb 2, 2010 at 3:46 PM, Ralf Baechle wrote: > On Tue, Feb 02, 2010 at 03:34:31PM +0200, Dmitri Vorobiev wrote: > >> >> I haven't been following this closely enough, so maybe my question is >> >> stupid. However: will this work on SGI R5000? I'm using an Indy, so >> >> I'm quite concerned about this CPU. >> > >> > The point is that your Indy right now is not working with a 64-bit kernel :) >> >> I know. :) >> >> What I was asking about was whether my Indy is going to work with the >> new scheme of calculating VMALLOC_END. > > Of course it will. OK, thanks! Dmitri > > Ralf > From anemo@mba.ocn.ne.jp Tue Feb 2 15:42:01 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 02 Feb 2010 15:42:05 +0100 (CET) Received: from mv-drv-hcb004.ocn.ad.jp ([118.23.109.134]:45333 "EHLO mv-drv-hcb004.ocn.ad.jp" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492289Ab0BBOmB (ORCPT ); Tue, 2 Feb 2010 15:42:01 +0100 Received: from vcmba.ocn.ne.jp (localhost.localdomain [127.0.0.1]) by mv-drv-hcb004.ocn.ad.jp (Postfix) with ESMTP id C9D3E1B4241; Tue, 2 Feb 2010 23:41:56 +0900 (JST) Received: from localhost (softbank221040169135.bbtec.net [221.40.169.135]) by vcmba.ocn.ne.jp (Postfix) with ESMTP; Tue, 2 Feb 2010 23:41:56 +0900 (JST) Date: Tue, 02 Feb 2010 23:41:50 +0900 (JST) Message-Id: <20100202.234150.39158143.anemo@mba.ocn.ne.jp> To: yuasa@linux-mips.org Cc: ralf@linux-mips.org, linux-mips@linux-mips.org Subject: Re: [PATCH] MIPS: txx9: remove forced serial console setting From: Atsushi Nemoto In-Reply-To: <20100202184004.efdff568.yuasa@linux-mips.org> References: <20100202184004.efdff568.yuasa@linux-mips.org> X-Fingerprint: 6ACA 1623 39BD 9A94 9B1A B746 CA77 FE94 2874 D52F X-Pgp-Public-Key: http://wwwkeys.pgp.net/pks/lookup?op=get&search=0x2874D52F X-Mailer: Mew version 5.2 on Emacs 22.2 / Mule 5.0 (SAKAKI) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25852 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anemo@mba.ocn.ne.jp Precedence: bulk X-list: linux-mips On Tue, 2 Feb 2010 18:40:04 +0900, Yoichi Yuasa wrote: > It is not always used, even if it is available. > > Signed-off-by: Yoichi Yuasa > --- > arch/mips/include/asm/txx9/generic.h | 1 - > arch/mips/txx9/generic/setup.c | 5 ----- > arch/mips/txx9/jmr3927/setup.c | 7 ------- > arch/mips/txx9/rbtx4927/setup.c | 7 ------- > arch/mips/txx9/rbtx4938/setup.c | 6 ------ > 5 files changed, 0 insertions(+), 26 deletions(-) Acked-by: Atsushi Nemoto From ralf@linux-mips.org Tue Feb 2 16:04:22 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 02 Feb 2010 16:04:27 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:50297 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1492258Ab0BBPEW (ORCPT ); Tue, 2 Feb 2010 16:04:22 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id o12F4aRA021380; Tue, 2 Feb 2010 16:04:38 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id o12F4YLx021362; Tue, 2 Feb 2010 16:04:34 +0100 Date: Tue, 2 Feb 2010 16:04:31 +0100 From: Ralf Baechle To: Atsushi Nemoto Cc: yuasa@linux-mips.org, linux-mips@linux-mips.org Subject: Re: [PATCH] MIPS: txx9: remove forced serial console setting Message-ID: <20100202150415.GA17149@linux-mips.org> References: <20100202184004.efdff568.yuasa@linux-mips.org> <20100202.234150.39158143.anemo@mba.ocn.ne.jp> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20100202.234150.39158143.anemo@mba.ocn.ne.jp> User-Agent: Mutt/1.5.20 (2009-08-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25853 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Tue, Feb 02, 2010 at 11:41:50PM +0900, Atsushi Nemoto wrote: > On Tue, 2 Feb 2010 18:40:04 +0900, Yoichi Yuasa wrote: > > It is not always used, even if it is available. > > > > Signed-off-by: Yoichi Yuasa > > --- > > arch/mips/include/asm/txx9/generic.h | 1 - > > arch/mips/txx9/generic/setup.c | 5 ----- > > arch/mips/txx9/jmr3927/setup.c | 7 ------- > > arch/mips/txx9/rbtx4927/setup.c | 7 ------- > > arch/mips/txx9/rbtx4938/setup.c | 6 ------ > > 5 files changed, 0 insertions(+), 26 deletions(-) > > Acked-by: Atsushi Nemoto Thanks, queued for 2.6.34. Ralf From macro@linux-mips.org Tue Feb 2 16:24:59 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 02 Feb 2010 16:25:04 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:59970 "EHLO localhost.localdomain" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492375Ab0BBPY7 (ORCPT ); Tue, 2 Feb 2010 16:24:59 +0100 Date: Tue, 2 Feb 2010 15:24:59 +0000 (GMT) From: "Maciej W. Rozycki" To: Ralf Baechle cc: Guenter Roeck , David Daney , "linux-mips@linux-mips.org" Subject: Re: [PATCH v3] Virtual memory size detection for 64 bit MIPS CPUs In-Reply-To: <20100202114259.GA10837@linux-mips.org> Message-ID: References: <1265064686-31278-1-git-send-email-guenter.roeck@ericsson.com> <4B676755.10600@caviumnetworks.com> <20100202001026.GA6883@ericsson.com> <20100202114259.GA10837@linux-mips.org> User-Agent: Alpine 2.00 (LFD 1167 2008-08-23) MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25854 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: macro@linux-mips.org Precedence: bulk X-list: linux-mips On Tue, 2 Feb 2010, Ralf Baechle wrote: > > > > + if (cpu_has_64bits) { > > > > + write_c0_entryhi(0xfffffffffffff000ULL); > > > > > > macro indicated that we need to avoid hazards here on R4000. > > A MTC0 instruction on an R4000 writes EntryHi on pipeline stage 7 but > will read from the same register on stage 4 which leaves a window of > 2 instructions, that is 2 NOP instructions needed. A footnote says: "An MTC0 of a CPR must not be immediately followed by MFC0 of the same CPR." -- that seems to imply a single intermediate instruction is sufficient, but that's not stated explicitly and obviously adding an extraneous instruction here, where performance does not matter, cannot hurt. > > > Perhaps adding: > > > > > > back_to_back_c0_hazard(); > > > > > Compiler already added a nop, so I thought it wasn't necessary. > > Doesn't hurt either, so I'll put it in. > > This probe is needed as per MIPSxx architecture spec and several CPUs will > missbehave without it. The 74K which of course is 32-bit but it > illustrates the issue might even issue these instructions out of order. > back_to_back_c0_hazard will expand into a suitable sequence to handle > the pipeline hazard. And we can't trust on the compiler doing the right > thing here; as explained above we might need multiple nops and some CPUs > will need other instructions to deal with the hazard, for example a number > of SSNOPs or an EHB instruction. I reckon there are MIPS64r2 ISA implementations out there already, so an EHB is a necessity where appropriate. Maciej From groeck@ericsson.com Tue Feb 2 17:01:43 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 02 Feb 2010 17:01:49 +0100 (CET) Received: from imr1.ericy.com ([198.24.6.9]:54474 "EHLO imr1.ericy.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492289Ab0BBQBn (ORCPT ); Tue, 2 Feb 2010 17:01:43 +0100 Received: from eusaamw0711.eamcs.ericsson.se ([147.117.20.178]) by imr1.ericy.com (8.13.1/8.13.1) with ESMTP id o12G2dZX004116; Tue, 2 Feb 2010 10:02:42 -0600 Received: from localhost (147.117.20.212) by eusaamw0711.eamcs.ericsson.se (147.117.20.179) with Microsoft SMTP Server id 8.1.375.2; Tue, 2 Feb 2010 11:01:31 -0500 Date: Tue, 2 Feb 2010 08:03:14 -0800 From: Guenter Roeck To: Ralf Baechle CC: "linux-mips@linux-mips.org" Subject: Re: [PATCH v5] Virtual memory size detection for 64 bit MIPS CPUs Message-ID: <20100202160314.GA20951@ericsson.com> References: <1265107061-18355-1-git-send-email-guenter.roeck@ericsson.com> <20100202130153.GB10837@linux-mips.org> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20100202130153.GB10837@linux-mips.org> User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25855 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: guenter.roeck@ericsson.com Precedence: bulk X-list: linux-mips On Tue, Feb 02, 2010 at 08:01:53AM -0500, Ralf Baechle wrote: > On Tue, Feb 02, 2010 at 02:37:41AM -0800, Guenter Roeck wrote: > > Pretty good, let the nitpicking start :-) > > > diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h > > index 1f4df64..284eb55 100644 > > --- a/arch/mips/include/asm/cpu-features.h > > +++ b/arch/mips/include/asm/cpu-features.h > > @@ -209,6 +209,9 @@ > > # ifndef cpu_has_64bit_addresses > > # define cpu_has_64bit_addresses 1 > > # endif > > +# ifndef cpu_vmbits > > +# define cpu_vmbits cpu_data[0].vmbits > > +# endif > > #endif > > For 32-bit kernels we probably should fix cpu_vmbits to 31. > > #ifdef CONFIG_64BIT > # ifndef cpu_vmbits > # define cpu_vmbits cpu_data[0].vmbits > # define __NEED_VMBITS > # endif > #else > # #define cpu_vmbits 31 > #endif > Makes sense in theory. However, cpu-features.h includes cpu-info.h which would need to have __NEED_VMBITS defined. So we would have a circular dependency. To avoid that, I could use CONFIG_64BIT directly whenever vmbits is used or set. vmbits would still be calculated but not used if cpu_vmbits is defined separately. Another option would be to define the vmbits variable with #ifdef CONFIG_64BIT, but populate and use it only if __NEED_VMBITS is defined. That would avoid the unnecessary calculation. Let me know what you prefer, and if you have a better idea. Right now I use the second approach. > > #if defined(CONFIG_CPU_MIPSR2_IRQ_VI) && !defined(cpu_has_vint) > > diff --git a/arch/mips/include/asm/cpu-info.h b/arch/mips/include/asm/cpu-info.h > > index 1260443..3c694bc 100644 > > --- a/arch/mips/include/asm/cpu-info.h > > +++ b/arch/mips/include/asm/cpu-info.h > > @@ -58,6 +58,7 @@ struct cpuinfo_mips { > > struct cache_desc tcache; /* Tertiary/split secondary cache */ > > int srsets; /* Shadow register sets */ > > int core; /* physical core number */ > > + int vmbits; /* Virtual memory size in bits */ > > #ifdef __NEED_VMBITS > int vmbits; /* Virtual memory size in bits */ > #endif > > To do for a later separate patch - minimize the sizes of all cpuinfo_mips > members; int is overkill for many members. > > > #if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_MIPS_MT_SMTC) > > /* > > * In the MIPS MT "SMTC" model, each TC is considered > > diff --git a/arch/mips/include/asm/pgtable-64.h b/arch/mips/include/asm/pgtable-64.h > > index 9cd5089..8eda30b 100644 > > --- a/arch/mips/include/asm/pgtable-64.h > > +++ b/arch/mips/include/asm/pgtable-64.h > > @@ -110,7 +110,9 @@ > > #define VMALLOC_START MAP_BASE > > #define VMALLOC_END \ > > (VMALLOC_START + \ > > - PTRS_PER_PGD * PTRS_PER_PMD * PTRS_PER_PTE * PAGE_SIZE - (1UL << 32)) > > + min(PTRS_PER_PGD * PTRS_PER_PMD * PTRS_PER_PTE * PAGE_SIZE, \ > > + (1UL << cpu_vmbits)) - (1UL << 32)) > > + > > This overlaps with other allocations near the top - yes, we've been living > dangerous but with bottom up allocations a conflict was very, very unlikely. > > Dealing with them in a sane way in the VMALLOC_END macro definition is hard, > so I suggest changing the definition to something like: > > extern unsigned long vmalloc_end; > > #define VMALLOC_START MAP_BASE > #define VMALLOC_END vmalloc_end > > And initialize the value of vmalloc_end in something like the mm section of > arch/mips/kernel/traps.c:per_cpu_trap_init(). > > There you can also ensure the value of vmalloc_end is <= FIXADDR_START. > FIXADDR_START is defined as 0xff000000, 0xfffe0000, or (0xff000000 - 0x20000), for all kernels. If vmalloc_end must be below FIXADDR_START, I might as well forget about the probing and just use the 32 bit define for VMALLOC_END. Am I missing something ? > Finally probing can be used to fix yet another sin. For 64-bit kernels > arch/mips/include/asm/processor.h defines TASK_SIZE: > > #define TASK_SIZE 0x10000000000UL > > This should turn into something like. > > #define TASK_SIZE (1UL << vmbits) > > This is also why I sugget to keep vmbits as 31, not 32. Hello S390 :-) > A comment at the TASK_SIZE definition says "This is hardcoded into a few places, so don't change it unless you know what you are doing". Changing it to a variable causes compilation to fail, so it looks as if there are some deeper complexities involved. I think it would be better to change TASK_SIZE in a separate commit, after making sure that the change does not break anything. So far the patch is a bug fix; this would make it into an enhancement with unknown side effects. > > +static inline void cpu_set_vmbits(struct cpuinfo_mips *c) > > +{ > > + if (cpu_has_64bits) { > > + write_c0_entryhi(0x3ffffffffffff000ULL); > > + back_to_back_c0_hazard(); > > + c->vmbits = fls64(read_c0_entryhi() & 0x3ffffffffffff000ULL); > > + } else > > + c->vmbits = 32; > > +} > > With my changes suggested above this would need changing to something like: > > static inline void cpu_set_vmbits(struct cpuinfo_mips *c) > { > if (__NEED_VMBITS) { > write_c0_entryhi(0x3ffffffffffff000ULL); > back_to_back_c0_hazard(); > c->vmbits = fls64(read_c0_entryhi() & 0x3ffffffffffff000ULL); > > return; > } > > BUG(); > } > BUG() doesn't work because it would fire if __NEED_VMBITS is false. Also, I would have to define __NEED_VMBITS as TRUE/FALSE if I want to use it in an if statement. So I decided to use #ifdef __NEED_VMBITS instead. > > #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \ > > | MIPS_CPU_COUNTER) > > > > @@ -967,6 +977,8 @@ __cpuinit void cpu_probe(void) > > c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1; > > else > > c->srsets = 1; > > + > > + cpu_set_vmbits(c); > > I think a name like cpu_probe_vmbits() would be clearer. > Agreed. Thanks, Guenter From prvs=6426729b5=groeck@redback.com Tue Feb 2 18:08:42 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 02 Feb 2010 18:08:51 +0100 (CET) Received: from mgate.redback.com ([155.53.3.41]:5650 "EHLO mgate.redback.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492411Ab0BBRIm (ORCPT ); Tue, 2 Feb 2010 18:08:42 +0100 X-IronPort-AV: E=Sophos;i="4.49,391,1262592000"; d="scan'208";a="7765305" Received: from prattle.redback.com ([155.53.12.9]) by mgate.redback.com with ESMTP; 02 Feb 2010 09:08:38 -0800 Received: from localhost (localhost [127.0.0.1]) by prattle.redback.com (Postfix) with ESMTP id B25DF15E9B52 for ; Tue, 2 Feb 2010 09:08:38 -0800 (PST) Received: from prattle.redback.com ([127.0.0.1]) by localhost (prattle [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 29799-09 for ; Tue, 2 Feb 2010 09:08:38 -0800 (PST) Received: from localhost (rbos-pc-13.lab.redback.com [10.12.11.133]) by prattle.redback.com (Postfix) with ESMTP id A256D15E9B50 for ; Tue, 2 Feb 2010 09:08:34 -0800 (PST) From: Guenter Roeck To: linux-mips@linux-mips.org Subject: [PATCH v6 00/01] Virtual memory size detection for 64 bit MIPS CPUs Date: Tue, 2 Feb 2010 08:52:19 -0800 Message-Id: <1265129540-10884-1-git-send-email-guenter.roeck@ericsson.com> X-Mailer: git-send-email 1.6.0.4 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25856 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: guenter.roeck@ericsson.com Precedence: bulk X-list: linux-mips This patchset addresses some of the most recent comments. It does not address changes to TASK_SIZE, and it does not address replacing the VMALLOC_END macro with a variable. Those changes are non-trivial and will require more discussion and/or clarification. From prvs=6426729b5=groeck@redback.com Tue Feb 2 18:09:09 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 02 Feb 2010 18:09:21 +0100 (CET) Received: from mgate.redback.com ([155.53.3.41]:5650 "EHLO mgate.redback.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492415Ab0BBRIn (ORCPT ); Tue, 2 Feb 2010 18:08:43 +0100 X-IronPort-AV: E=Sophos;i="4.49,391,1262592000"; d="scan'208";a="7765306" Received: from prattle.redback.com ([155.53.12.9]) by mgate.redback.com with ESMTP; 02 Feb 2010 09:08:38 -0800 Received: from localhost (localhost [127.0.0.1]) by prattle.redback.com (Postfix) with ESMTP id B6EAF15E9B53; Tue, 2 Feb 2010 09:08:38 -0800 (PST) Received: from prattle.redback.com ([127.0.0.1]) by localhost (prattle [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 29972-07; Tue, 2 Feb 2010 09:08:38 -0800 (PST) Received: from localhost (rbos-pc-13.lab.redback.com [10.12.11.133]) by prattle.redback.com (Postfix) with ESMTP id A66D615E9B51; Tue, 2 Feb 2010 09:08:38 -0800 (PST) From: Guenter Roeck To: linux-mips@linux-mips.org Cc: Guenter Roeck Subject: [PATCH v6 01/01] Virtual memory size detection for 64 bit MIPS CPUs Date: Tue, 2 Feb 2010 08:52:20 -0800 Message-Id: <1265129540-10884-2-git-send-email-guenter.roeck@ericsson.com> X-Mailer: git-send-email 1.6.0.4 In-Reply-To: <1265129540-10884-1-git-send-email-guenter.roeck@ericsson.com> References: <1265129540-10884-1-git-send-email-guenter.roeck@ericsson.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25857 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: guenter.roeck@ericsson.com Precedence: bulk X-list: linux-mips Linux kernel 2.6.32 and later allocates memory from the top of virtual memory space. This patch implements virtual memory size detection for 64 bit MIPS CPUs to avoid resulting crashes. Signed-off-by: Guenter Roeck --- arch/mips/include/asm/cpu-features.h | 7 +++++++ arch/mips/include/asm/cpu-info.h | 3 +++ arch/mips/include/asm/pgtable-64.h | 4 +++- arch/mips/kernel/cpu-probe.c | 11 +++++++++++ 4 files changed, 24 insertions(+), 1 deletions(-) diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h index 1f4df64..e5835dd 100644 --- a/arch/mips/include/asm/cpu-features.h +++ b/arch/mips/include/asm/cpu-features.h @@ -191,6 +191,9 @@ # ifndef cpu_has_64bit_addresses # define cpu_has_64bit_addresses 0 # endif +# ifndef cpu_vmbits +# define cpu_vmbits 31 +# endif #endif #ifdef CONFIG_64BIT @@ -209,6 +212,10 @@ # ifndef cpu_has_64bit_addresses # define cpu_has_64bit_addresses 1 # endif +# ifndef cpu_vmbits +# define cpu_vmbits cpu_data[0].vmbits +# define __NEED_VMBITS_PROBE +# endif #endif #if defined(CONFIG_CPU_MIPSR2_IRQ_VI) && !defined(cpu_has_vint) diff --git a/arch/mips/include/asm/cpu-info.h b/arch/mips/include/asm/cpu-info.h index 1260443..b39def3 100644 --- a/arch/mips/include/asm/cpu-info.h +++ b/arch/mips/include/asm/cpu-info.h @@ -58,6 +58,9 @@ struct cpuinfo_mips { struct cache_desc tcache; /* Tertiary/split secondary cache */ int srsets; /* Shadow register sets */ int core; /* physical core number */ +#ifdef CONFIG_64BIT + int vmbits; /* Virtual memory size in bits */ +#endif #if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_MIPS_MT_SMTC) /* * In the MIPS MT "SMTC" model, each TC is considered diff --git a/arch/mips/include/asm/pgtable-64.h b/arch/mips/include/asm/pgtable-64.h index 9cd5089..8eda30b 100644 --- a/arch/mips/include/asm/pgtable-64.h +++ b/arch/mips/include/asm/pgtable-64.h @@ -110,7 +110,9 @@ #define VMALLOC_START MAP_BASE #define VMALLOC_END \ (VMALLOC_START + \ - PTRS_PER_PGD * PTRS_PER_PMD * PTRS_PER_PTE * PAGE_SIZE - (1UL << 32)) + min(PTRS_PER_PGD * PTRS_PER_PMD * PTRS_PER_PTE * PAGE_SIZE, \ + (1UL << cpu_vmbits)) - (1UL << 32)) + #if defined(CONFIG_MODULES) && defined(KBUILD_64BIT_SYM32) && \ VMALLOC_START != CKSSEG /* Load modules into 32bit-compatible segment. */ diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index 7a51866..00d7124 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -282,6 +282,15 @@ static inline int __cpu_has_fpu(void) return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE); } +static inline void cpu_probe_vmbits(struct cpuinfo_mips *c) +{ +#ifdef __NEED_VMBITS_PROBE + write_c0_entryhi(0x3ffffffffffff000ULL); + back_to_back_c0_hazard(); + c->vmbits = fls64(read_c0_entryhi() & 0x3ffffffffffff000ULL); +#endif +} + #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \ | MIPS_CPU_COUNTER) @@ -967,6 +976,8 @@ __cpuinit void cpu_probe(void) c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1; else c->srsets = 1; + + cpu_probe_vmbits(c); } __cpuinit void cpu_report(void) -- 1.6.0.4 From ralf@linux-mips.org Tue Feb 2 18:50:36 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 02 Feb 2010 18:50:40 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:50130 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1492498Ab0BBRug (ORCPT ); Tue, 2 Feb 2010 18:50:36 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id o12Hopg4029965; Tue, 2 Feb 2010 18:50:52 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id o12HoogE029953; Tue, 2 Feb 2010 18:50:50 +0100 Date: Tue, 2 Feb 2010 18:50:50 +0100 From: Ralf Baechle To: Guenter Roeck Cc: linux-mips@linux-mips.org Subject: Re: [PATCH v6 00/01] Virtual memory size detection for 64 bit MIPS CPUs Message-ID: <20100202175049.GA29596@linux-mips.org> References: <1265129540-10884-1-git-send-email-guenter.roeck@ericsson.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1265129540-10884-1-git-send-email-guenter.roeck@ericsson.com> User-Agent: Mutt/1.5.20 (2009-08-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25858 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Tue, Feb 02, 2010 at 08:52:19AM -0800, Guenter Roeck wrote: > This patchset addresses some of the most recent comments. > > It does not address changes to TASK_SIZE, and it does not address replacing > the VMALLOC_END macro with a variable. Those changes are non-trivial > and will require more discussion and/or clarification. I think I'm happy with doing these in followup patches. What's most important is sorting the whole issue soon so we can release a working 2.6.33. Ralf From David.Daney@caviumnetworks.com Tue Feb 2 19:35:33 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 02 Feb 2010 19:35:37 +0100 (CET) Received: from mail3.caviumnetworks.com ([12.108.191.235]:14614 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492498Ab0BBSfd (ORCPT ); Tue, 2 Feb 2010 19:35:33 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Tue, 02 Feb 2010 10:30:17 -0800 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Tue, 2 Feb 2010 10:29:25 -0800 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Tue, 2 Feb 2010 10:29:25 -0800 Message-ID: <4B686F05.9090109@caviumnetworks.com> Date: Tue, 02 Feb 2010 10:29:25 -0800 From: David Daney User-Agent: Thunderbird 2.0.0.21 (X11/20090320) MIME-Version: 1.0 To: Guenter Roeck , Ralf Baechle CC: linux-mips@linux-mips.org Subject: Re: [PATCH v6 01/01] Virtual memory size detection for 64 bit MIPS CPUs References: <1265129540-10884-1-git-send-email-guenter.roeck@ericsson.com> <1265129540-10884-2-git-send-email-guenter.roeck@ericsson.com> In-Reply-To: <1265129540-10884-2-git-send-email-guenter.roeck@ericsson.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 02 Feb 2010 18:29:25.0586 (UTC) FILETIME=[A5D45B20:01CAA435] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25859 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Guenter Roeck wrote: > Linux kernel 2.6.32 and later allocates memory from the top of virtual memory > space. > > This patch implements virtual memory size detection for 64 bit MIPS CPUs > to avoid resulting crashes. > > Signed-off-by: Guenter Roeck Reviewed-by: David Daney > --- > arch/mips/include/asm/cpu-features.h | 7 +++++++ > arch/mips/include/asm/cpu-info.h | 3 +++ > arch/mips/include/asm/pgtable-64.h | 4 +++- > arch/mips/kernel/cpu-probe.c | 11 +++++++++++ > 4 files changed, 24 insertions(+), 1 deletions(-) > > diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h > index 1f4df64..e5835dd 100644 > --- a/arch/mips/include/asm/cpu-features.h > +++ b/arch/mips/include/asm/cpu-features.h > @@ -191,6 +191,9 @@ > # ifndef cpu_has_64bit_addresses > # define cpu_has_64bit_addresses 0 > # endif > +# ifndef cpu_vmbits > +# define cpu_vmbits 31 > +# endif > #endif > > #ifdef CONFIG_64BIT > @@ -209,6 +212,10 @@ > # ifndef cpu_has_64bit_addresses > # define cpu_has_64bit_addresses 1 > # endif > +# ifndef cpu_vmbits > +# define cpu_vmbits cpu_data[0].vmbits > +# define __NEED_VMBITS_PROBE > +# endif > #endif > > #if defined(CONFIG_CPU_MIPSR2_IRQ_VI) && !defined(cpu_has_vint) > diff --git a/arch/mips/include/asm/cpu-info.h b/arch/mips/include/asm/cpu-info.h > index 1260443..b39def3 100644 > --- a/arch/mips/include/asm/cpu-info.h > +++ b/arch/mips/include/asm/cpu-info.h > @@ -58,6 +58,9 @@ struct cpuinfo_mips { > struct cache_desc tcache; /* Tertiary/split secondary cache */ > int srsets; /* Shadow register sets */ > int core; /* physical core number */ > +#ifdef CONFIG_64BIT > + int vmbits; /* Virtual memory size in bits */ > +#endif > #if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_MIPS_MT_SMTC) > /* > * In the MIPS MT "SMTC" model, each TC is considered > diff --git a/arch/mips/include/asm/pgtable-64.h b/arch/mips/include/asm/pgtable-64.h > index 9cd5089..8eda30b 100644 > --- a/arch/mips/include/asm/pgtable-64.h > +++ b/arch/mips/include/asm/pgtable-64.h > @@ -110,7 +110,9 @@ > #define VMALLOC_START MAP_BASE > #define VMALLOC_END \ > (VMALLOC_START + \ > - PTRS_PER_PGD * PTRS_PER_PMD * PTRS_PER_PTE * PAGE_SIZE - (1UL << 32)) > + min(PTRS_PER_PGD * PTRS_PER_PMD * PTRS_PER_PTE * PAGE_SIZE, \ > + (1UL << cpu_vmbits)) - (1UL << 32)) > + > #if defined(CONFIG_MODULES) && defined(KBUILD_64BIT_SYM32) && \ > VMALLOC_START != CKSSEG > /* Load modules into 32bit-compatible segment. */ > diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c > index 7a51866..00d7124 100644 > --- a/arch/mips/kernel/cpu-probe.c > +++ b/arch/mips/kernel/cpu-probe.c > @@ -282,6 +282,15 @@ static inline int __cpu_has_fpu(void) > return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE); > } > > +static inline void cpu_probe_vmbits(struct cpuinfo_mips *c) > +{ > +#ifdef __NEED_VMBITS_PROBE > + write_c0_entryhi(0x3ffffffffffff000ULL); > + back_to_back_c0_hazard(); > + c->vmbits = fls64(read_c0_entryhi() & 0x3ffffffffffff000ULL); > +#endif > +} > + > #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \ > | MIPS_CPU_COUNTER) > > @@ -967,6 +976,8 @@ __cpuinit void cpu_probe(void) > c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1; > else > c->srsets = 1; > + > + cpu_probe_vmbits(c); > } > > __cpuinit void cpu_report(void) From ralf@linux-mips.org Tue Feb 2 19:49:44 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 02 Feb 2010 19:49:48 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:47085 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1492534Ab0BBSto (ORCPT ); Tue, 2 Feb 2010 19:49:44 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id o12Inwlk032121; Tue, 2 Feb 2010 19:49:59 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id o12Invaq032113; Tue, 2 Feb 2010 19:49:57 +0100 Date: Tue, 2 Feb 2010 19:49:56 +0100 From: Ralf Baechle To: David Daney Cc: Guenter Roeck , linux-mips@linux-mips.org Subject: Re: [PATCH v6 01/01] Virtual memory size detection for 64 bit MIPS CPUs Message-ID: <20100202184956.GB29596@linux-mips.org> References: <1265129540-10884-1-git-send-email-guenter.roeck@ericsson.com> <1265129540-10884-2-git-send-email-guenter.roeck@ericsson.com> <4B686F05.9090109@caviumnetworks.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <4B686F05.9090109@caviumnetworks.com> User-Agent: Mutt/1.5.20 (2009-08-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25860 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Tue, Feb 02, 2010 at 10:29:25AM -0800, David Daney wrote: > >Signed-off-by: Guenter Roeck > > Reviewed-by: David Daney Thanks for reviewing - as close as this to a release I appreciate a 2nd pair of eyes. Applied and will go to Linus asap. Thanks everybody, Ralf From ralf@linux-mips.org Wed Feb 3 02:18:25 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 03 Feb 2010 02:18:29 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:47383 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1492569Ab0BCBSZ (ORCPT ); Wed, 3 Feb 2010 02:18:25 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id o131IXIM012298; Wed, 3 Feb 2010 02:18:35 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id o131IVnP012296; Wed, 3 Feb 2010 02:18:31 +0100 Date: Wed, 3 Feb 2010 02:18:31 +0100 From: Ralf Baechle To: Wu Zhangjin Cc: linux-mips@linux-mips.org Subject: Re: [PATCH] Loongson: Lemote 2F: Fixup of the Makefile Message-ID: <20100203011831.GA12263@linux-mips.org> References: <1264927312-21390-1-git-send-email-wuzhangjin@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1264927312-21390-1-git-send-email-wuzhangjin@gmail.com> User-Agent: Mutt/1.5.20 (2009-08-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25861 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Sun, Jan 31, 2010 at 04:41:52PM +0800, Wu Zhangjin wrote: > From: Wu Zhangjin > > This patch removes the duplicated obj-y line. Thanks; I've folded this patch into the existing "MIPS: Loongson: Lemote-2F: Get the machine type from PMON_VER" patch. Ralf From David.Daney@caviumnetworks.com Wed Feb 3 02:19:47 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 03 Feb 2010 02:19:51 +0100 (CET) Received: from smtp2.caviumnetworks.com ([209.113.159.134]:12771 "EHLO smtp2.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492569Ab0BCBTr (ORCPT ); Wed, 3 Feb 2010 02:19:47 +0100 Received: from maexch1.caveonetworks.com (Not Verified[192.168.14.20]) by smtp2.caviumnetworks.com with MailMarshal (v6,5,4,7535) id ; Tue, 02 Feb 2010 20:14:12 -0500 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by maexch1.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Tue, 2 Feb 2010 20:19:46 -0500 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Tue, 2 Feb 2010 17:19:44 -0800 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.2/8.14.2) with ESMTP id o131Jeu4012459; Tue, 2 Feb 2010 17:19:40 -0800 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.2/8.14.2/Submit) id o131JckU012458; Tue, 2 Feb 2010 17:19:38 -0800 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: David Daney Subject: [PATCH] MIPS: Remove #if 0 r4k_update_mmu_cache_hwbug Date: Tue, 2 Feb 2010 17:19:38 -0800 Message-Id: <1265159978-12434-1-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.6.0.6 X-OriginalArrivalTime: 03 Feb 2010 01:19:44.0613 (UTC) FILETIME=[F7E9C150:01CAA46E] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25862 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips The function is #if 0ed out. There are no other occurrences of its name in the tree. It is safe to remove. Signed-off-by: David Daney --- arch/mips/mm/tlb-r4k.c | 34 ---------------------------------- 1 files changed, 0 insertions(+), 34 deletions(-) diff --git a/arch/mips/mm/tlb-r4k.c b/arch/mips/mm/tlb-r4k.c index 7de128a..e551559 100644 --- a/arch/mips/mm/tlb-r4k.c +++ b/arch/mips/mm/tlb-r4k.c @@ -337,40 +337,6 @@ void __update_tlb(struct vm_area_struct * vma, unsigned long address, pte_t pte) EXIT_CRITICAL(flags); } -#if 0 -static void r4k_update_mmu_cache_hwbug(struct vm_area_struct * vma, - unsigned long address, pte_t pte) -{ - unsigned long flags; - unsigned int asid; - pgd_t *pgdp; - pmd_t *pmdp; - pte_t *ptep; - int idx; - - ENTER_CRITICAL(flags); - address &= (PAGE_MASK << 1); - asid = read_c0_entryhi() & ASID_MASK; - write_c0_entryhi(address | asid); - pgdp = pgd_offset(vma->vm_mm, address); - mtc0_tlbw_hazard(); - tlb_probe(); - tlb_probe_hazard(); - pmdp = pmd_offset(pgdp, address); - idx = read_c0_index(); - ptep = pte_offset_map(pmdp, address); - write_c0_entrylo0(pte_val(*ptep++) >> 6); - write_c0_entrylo1(pte_val(*ptep) >> 6); - mtc0_tlbw_hazard(); - if (idx < 0) - tlb_write_random(); - else - tlb_write_indexed(); - tlbw_use_hazard(); - EXIT_CRITICAL(flags); -} -#endif - void __init add_wired_entry(unsigned long entrylo0, unsigned long entrylo1, unsigned long entryhi, unsigned long pagemask) { -- 1.6.0.6 From ralf@linux-mips.org Wed Feb 3 02:29:32 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 03 Feb 2010 02:29:36 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:60212 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1492832Ab0BCB3c (ORCPT ); Wed, 3 Feb 2010 02:29:32 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id o131Tdm5020514; Wed, 3 Feb 2010 02:29:39 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id o131TY5h020512; Wed, 3 Feb 2010 02:29:34 +0100 Date: Wed, 3 Feb 2010 02:29:34 +0100 From: Ralf Baechle To: Shane McDonald Cc: Wu Zhangjin , David VomLehn , mbizon@freebox.fr, linux-mips@linux-mips.org Subject: Re: [PATCH urgent] MIPS: Fixup of the r4k timer Message-ID: <20100203012934.GA20375@linux-mips.org> References: <1265015455-32553-1-git-send-email-wuzhangjin@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.20 (2009-08-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25863 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Mon, Feb 01, 2010 at 09:03:10PM -0600, Shane McDonald wrote: > On Mon, Feb 1, 2010 at 3:10 AM, Wu Zhangjin wrote: > > > > From: Wu Zhangjin > > > > As reported by Maxime Bizon, the commit "MIPS: PowerTV: Fix support for > > timer interrupts with > 64 external IRQs" have broken the r4k timer > > since it didn't initialize the cp0_compare_irq_shift variable used in > > c0_compare_int_pending() on the architectures whose cpu_has_mips_r2 is > > false. > > > > This patch fixes it via initializing the cp0_compare_irq_shift as the > > cp0_compare_irq used in the old c0_compare_int_pending(). > > > > Reported-by: Maxime Bizon > > Signed-off-by: Wu Zhangjin > > When applied to 2.6.33-rc6, this patch fixes the problem on my > RM7035C-based system. > > Tested-by: Shane McDonald Thanks folks, applied. Ralf From ben@fluff.org.uk Wed Feb 3 03:24:25 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 03 Feb 2010 03:24:29 +0100 (CET) Received: from aeryn.fluff.org.uk ([87.194.8.8]:49968 "EHLO kira.home.fluff.org" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1492859Ab0BCCYZ (ORCPT ); Wed, 3 Feb 2010 03:24:25 +0100 Received: from ben by kira.home.fluff.org with local (Exim 4.71) (envelope-from ) id 1NcUuS-0006Mm-JA; Wed, 03 Feb 2010 02:24:04 +0000 Date: Wed, 3 Feb 2010 02:24:04 +0000 From: Ben Dooks To: Ralf Baechle Cc: David Daney , linux-mips@linux-mips.org, linux-i2c@vger.kernel.org, ben-linux@fluff.org, khali@linux-fr.org, rade.bozic.ext@nsn.com, Michael Lawnick Subject: Re: [PATCH] I2C: Add driver for Cavium OCTEON I2C ports. Message-ID: <20100203022404.GB24325@fluff.org.uk> References: <1264711627-24304-1-git-send-email-ddaney@caviumnetworks.com> <20100128234113.GC13143@linux-mips.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20100128234113.GC13143@linux-mips.org> X-Disclaimer: These are my own opinions, so there! User-Agent: Mutt/1.5.20 (2009-06-14) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25864 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ben-linux@fluff.org Precedence: bulk X-list: linux-mips On Fri, Jan 29, 2010 at 12:41:13AM +0100, Ralf Baechle wrote: > On Thu, Jan 28, 2010 at 12:47:07PM -0800, David Daney wrote: > > Thanks, I've replaced the queue patch with this one. I'd rather avoid a cross-tree merge if possible. Is there anything stopping it being added to my next-i2c tree? > Ralf > -- > To unsubscribe from this list: send the line "unsubscribe linux-i2c" in > the body of a message to majordomo@vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html -- Ben (ben@fluff.org, http://www.fluff.org/) 'a smiley only costs 4 bytes' From David.Daney@caviumnetworks.com Wed Feb 3 03:30:36 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 03 Feb 2010 03:30:41 +0100 (CET) Received: from mail3.caviumnetworks.com ([12.108.191.235]:8623 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492781Ab0BCCag (ORCPT ); Wed, 3 Feb 2010 03:30:36 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Tue, 02 Feb 2010 18:30:42 -0800 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Tue, 2 Feb 2010 18:29:44 -0800 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Tue, 2 Feb 2010 18:29:44 -0800 Message-ID: <4B68DF98.4080501@caviumnetworks.com> Date: Tue, 02 Feb 2010 18:29:44 -0800 From: David Daney User-Agent: Thunderbird 2.0.0.21 (X11/20090320) MIME-Version: 1.0 To: Ben Dooks CC: Ralf Baechle , linux-mips@linux-mips.org, linux-i2c@vger.kernel.org, khali@linux-fr.org, rade.bozic.ext@nsn.com, Michael Lawnick Subject: Re: [PATCH] I2C: Add driver for Cavium OCTEON I2C ports. References: <1264711627-24304-1-git-send-email-ddaney@caviumnetworks.com> <20100128234113.GC13143@linux-mips.org> <20100203022404.GB24325@fluff.org.uk> In-Reply-To: <20100203022404.GB24325@fluff.org.uk> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 03 Feb 2010 02:29:44.0858 (UTC) FILETIME=[BF7447A0:01CAA478] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25865 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Ben Dooks wrote: > On Fri, Jan 29, 2010 at 12:41:13AM +0100, Ralf Baechle wrote: >> On Thu, Jan 28, 2010 at 12:47:07PM -0800, David Daney wrote: >> >> Thanks, I've replaced the queue patch with this one. > > I'd rather avoid a cross-tree merge if possible. Is there anything > stopping it being added to my next-i2c tree? > I can't speak to the logistics, but I would note that there are two related MIPS specific patches that add the platform device and register some i2c_board_info. I don't know if it would make sense to merge them all via the same path. I will let you and Ralf decide that. In any event thanks for looking at the patches, David Daney >> Ralf >> -- >> To unsubscribe from this list: send the line "unsubscribe linux-i2c" in >> the body of a message to majordomo@vger.kernel.org >> More majordomo info at http://vger.kernel.org/majordomo-info.html > From Anoop_P.A@pmc-sierra.com Wed Feb 3 12:38:02 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 03 Feb 2010 12:38:06 +0100 (CET) Received: from bby1mta02.pmc-sierra.com ([216.241.235.117]:54059 "EHLO bby1mta02.pmc-sierra.bc.ca" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492308Ab0BCLiC convert rfc822-to-8bit (ORCPT ); Wed, 3 Feb 2010 12:38:02 +0100 Received: from bby1mta02.pmc-sierra.bc.ca (localhost.pmc-sierra.bc.ca [127.0.0.1]) by localhost (Postfix) with SMTP id AB8168E00A8; Wed, 3 Feb 2010 03:37:49 -0800 (PST) Received: from bby1exg02.pmc_nt.nt.pmc-sierra.bc.ca (BBY1EXG02.pmc-sierra.bc.ca [216.241.231.167]) by bby1mta02.pmc-sierra.bc.ca (Postfix) with SMTP id 9ED538E0090; Wed, 3 Feb 2010 03:37:49 -0800 (PST) Received: from BBY1EXM11.pmc_nt.nt.pmc-sierra.bc.ca ([216.241.231.158]) by bby1exg02.pmc_nt.nt.pmc-sierra.bc.ca with Microsoft SMTPSVC(6.0.3790.3959); Wed, 3 Feb 2010 03:38:55 -0800 X-MimeOLE: Produced By Microsoft Exchange V6.5 Content-class: urn:content-classes:message MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT Subject: Cached Base address difference. Date: Wed, 3 Feb 2010 03:34:25 -0800 Message-ID: In-Reply-To: <20100203012934.GA20375@linux-mips.org> X-MS-Has-Attach: X-MS-TNEF-Correlator: Thread-Topic: Cached Base address difference. Thread-Index: AcqkcGoVEhLVXra2RxuiaAF6KL+WnQAUuWPQ References: <1265015455-32553-1-git-send-email-wuzhangjin@gmail.com> <20100203012934.GA20375@linux-mips.org> From: "Anoop P.A." To: "Ralf Baechle" , X-OriginalArrivalTime: 03 Feb 2010 11:38:55.0499 (UTC) FILETIME=[779115B0:01CAA4C5] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25866 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: Anoop_P.A@pmc-sierra.com Precedence: bulk X-list: linux-mips Hi list, I am seeing a address conflict in asm-generic/spaces.h . in spaces.h ( 64 bit)CAC_BASE has been defined as 0x9800000000000000 however see mips run says it is 0x9000000000000000 http://books.google.co.in/books?id=kk8G2gK4Tw8C&lpg=PP1&dq=see%20mips%20 run&pg=PA51#v=onepage&q=&f=false Is this intentional? Thanks Anoop From ralf@linux-mips.org Wed Feb 3 13:33:20 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 03 Feb 2010 13:33:24 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:59764 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491050Ab0BCMdU (ORCPT ); Wed, 3 Feb 2010 13:33:20 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id o13CXW7t006907; Wed, 3 Feb 2010 13:33:33 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id o13CXVvB006904; Wed, 3 Feb 2010 13:33:31 +0100 Date: Wed, 3 Feb 2010 13:33:31 +0100 From: Ralf Baechle To: "Anoop P.A." Cc: linux-mips@linux-mips.org Subject: Re: Cached Base address difference. Message-ID: <20100203123331.GB20375@linux-mips.org> References: <1265015455-32553-1-git-send-email-wuzhangjin@gmail.com> <20100203012934.GA20375@linux-mips.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.20 (2009-08-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25867 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Wed, Feb 03, 2010 at 03:34:25AM -0800, Anoop P.A. wrote: > I am seeing a address conflict in asm-generic/spaces.h . in spaces.h ( > 64 bit)CAC_BASE has been defined as 0x9800000000000000 however see mips > run says it is 0x9000000000000000 > http://books.google.co.in/books?id=kk8G2gK4Tw8C&lpg=PP1&dq=see%20mips%20 > run&pg=PA51#v=onepage&q=&f=false > > Is this intentional? defines: #ifndef CAC_BASE #ifdef CONFIG_DMA_NONCOHERENT #define CAC_BASE _AC(0x9800000000000000, UL) #else #define CAC_BASE _AC(0xa800000000000000, UL) #endif #endif No 0x9000000000000000 anywhere - and it would be wrong because it stands for uncached. Ralf From Anoop_P.A@pmc-sierra.com Wed Feb 3 14:39:26 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 03 Feb 2010 14:39:29 +0100 (CET) Received: from bby1mta03.pmc-sierra.com ([216.241.235.118]:51728 "EHLO bby1mta03.pmc-sierra.bc.ca" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492528Ab0BCNjZ convert rfc822-to-8bit (ORCPT ); Wed, 3 Feb 2010 14:39:25 +0100 Received: from bby1mta03.pmc-sierra.bc.ca (localhost.pmc-sierra.bc.ca [127.0.0.1]) by localhost (Postfix) with SMTP id 9B50E1070075; Wed, 3 Feb 2010 05:39:08 -0800 (PST) Received: from bby1exg02.pmc_nt.nt.pmc-sierra.bc.ca (BBY1EXG02.pmc-sierra.bc.ca [216.241.231.167]) by bby1mta03.pmc-sierra.bc.ca (Postfix) with SMTP id 882CF1070071; Wed, 3 Feb 2010 05:39:08 -0800 (PST) Received: from BBY1EXM11.pmc_nt.nt.pmc-sierra.bc.ca ([216.241.231.158]) by bby1exg02.pmc_nt.nt.pmc-sierra.bc.ca with Microsoft SMTPSVC(6.0.3790.3959); Wed, 3 Feb 2010 05:40:14 -0800 X-MimeOLE: Produced By Microsoft Exchange V6.5 Content-class: urn:content-classes:message MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT Subject: RE: Cached Base address difference. Date: Wed, 3 Feb 2010 05:38:28 -0800 Message-ID: In-Reply-To: <20100203123331.GB20375@linux-mips.org> X-MS-Has-Attach: X-MS-TNEF-Correlator: Thread-Topic: Cached Base address difference. Thread-Index: AcqkzRVSee764XmcQfyWF6o1Aj0l9QABtaWQ References: <1265015455-32553-1-git-send-email-wuzhangjin@gmail.com> <20100203012934.GA20375@linux-mips.org> <20100203123331.GB20375@linux-mips.org> From: "Anoop P.A." To: "Ralf Baechle" Cc: X-OriginalArrivalTime: 03 Feb 2010 13:40:14.0297 (UTC) FILETIME=[6A118490:01CAA4D6] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25868 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: Anoop_P.A@pmc-sierra.com Precedence: bulk X-list: linux-mips Hi Ralf, I am sorry if it is not clear from my last mail. What I want to convey is, "See MIPS Run" explains "window on physical memory (cached)" will start @ 0x9000_0000_0000_0000. You can see "See MIPS Run" page under suspect from this link http://books.google.co.in/books?id=kk8G2gK4Tw8C&lpg=PP1&dq=see%20mips%20 run&pg=PA51#v=onepage&q=&f=false How ever as you mentioned Linux source defines CAC_BASE 0x98000000_00000000 Thanks Anoop > -----Original Message----- > From: Ralf Baechle [mailto:ralf@linux-mips.org] > Sent: Wednesday, February 03, 2010 6:04 PM > To: Anoop P.A. > Cc: linux-mips@linux-mips.org > Subject: Re: Cached Base address difference. > > On Wed, Feb 03, 2010 at 03:34:25AM -0800, Anoop P.A. wrote: > > > I am seeing a address conflict in asm-generic/spaces.h . in spaces.h ( > > 64 bit)CAC_BASE has been defined as 0x9800000000000000 however see mips > > run says it is 0x9000000000000000 > > http://books.google.co.in/books?id=kk8G2gK4Tw8C&lpg=PP1&dq=see%20mips%20 > > run&pg=PA51#v=onepage&q=&f=false > > > > Is this intentional? > > defines: > > #ifndef CAC_BASE > #ifdef CONFIG_DMA_NONCOHERENT > #define CAC_BASE _AC(0x9800000000000000, UL) > #else > #define CAC_BASE _AC(0xa800000000000000, UL) > #endif > #endif > > No 0x9000000000000000 anywhere - and it would be wrong because it stands > for uncached. > > Ralf From ralf@linux-mips.org Wed Feb 3 14:47:30 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 03 Feb 2010 14:47:34 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:44850 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491970Ab0BCNra (ORCPT ); Wed, 3 Feb 2010 14:47:30 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id o13DlkOh010202; Wed, 3 Feb 2010 14:47:47 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id o13Dljot010201; Wed, 3 Feb 2010 14:47:45 +0100 Date: Wed, 3 Feb 2010 14:47:45 +0100 From: Ralf Baechle To: David Daney Cc: linux-mips@linux-mips.org Subject: Re: [PATCH] MIPS: Remove #if 0 r4k_update_mmu_cache_hwbug Message-ID: <20100203134744.GA9389@linux-mips.org> References: <1265159978-12434-1-git-send-email-ddaney@caviumnetworks.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1265159978-12434-1-git-send-email-ddaney@caviumnetworks.com> User-Agent: Mutt/1.5.20 (2009-08-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25869 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Tue, Feb 02, 2010 at 05:19:38PM -0800, David Daney wrote: > The function is #if 0ed out. There are no other occurrences of its > name in the tree. It is safe to remove. It had a long sad live - unused since 2.1.16 and intended to be used for an R4000 workaround. Let it rest in pieces. Queued for 2.6.34, Ralf From ralf@linux-mips.org Wed Feb 3 15:36:29 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 03 Feb 2010 15:36:32 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:41994 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1492652Ab0BCOg2 (ORCPT ); Wed, 3 Feb 2010 15:36:28 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id o13EajGi029194; Wed, 3 Feb 2010 15:36:45 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id o13EailD029190; Wed, 3 Feb 2010 15:36:44 +0100 Date: Wed, 3 Feb 2010 15:36:43 +0100 From: Ralf Baechle To: Florian Fainelli Cc: Thomas Bogendoerfer , linux-mips@linux-mips.org Subject: Re: [PATCH urgent] MIPS: fix micro-assembly overflow in set_except_vector Message-ID: <20100203143643.GA27068@linux-mips.org> References: <201002011027.37521.florian@openwrt.org> <20100201103628.GA15661@alpha.franken.de> <201002021006.35731.florian@openwrt.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <201002021006.35731.florian@openwrt.org> User-Agent: Mutt/1.5.20 (2009-08-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25870 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Tue, Feb 02, 2010 at 10:06:35AM +0100, Florian Fainelli wrote: > On Monday 01 February 2010 11:36:28 Thomas Bogendoerfer wrote: > > On Mon, Feb 01, 2010 at 10:27:37AM +0100, Florian Fainelli wrote: > > > Commit 24a6d9866c5f15ba7e5b14dc17be4b6edba21d0e broke > > > the installation of handlers for boards which have their > > > handlers above a 1 << 26 address. Fix this by making sure that > > > jump_mask does not excess 0xfc000000 and add the missing ~ operator > > > > j can handle 28 bit jump targets (26 bit in instruction plus two 0 bits > > for 32bit aligment), so 0xf000000 was IMHO fine. > > Corrected version below, thanks. Folded into the existing -queue patch. Thanks, Ralf From ralf@linux-mips.org Wed Feb 3 16:00:31 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 03 Feb 2010 16:00:39 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:54227 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1492832Ab0BCPAb (ORCPT ); Wed, 3 Feb 2010 16:00:31 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id o13F0kIp004407; Wed, 3 Feb 2010 16:00:46 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id o13F0iKu004333; Wed, 3 Feb 2010 16:00:44 +0100 Date: Wed, 3 Feb 2010 16:00:44 +0100 From: Ralf Baechle To: Wu Zhangjin Cc: Manuel Lauss , linux-mips@linux-mips.org Subject: Re: [PATCH v4] MIPS: Make the debugging of compressed kernel configurable Message-ID: <20100203150043.GA30645@linux-mips.org> References: <67a1110ea3c3276af659bc669ec87f0976121815.1264941563.git.wuzhangjin@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <67a1110ea3c3276af659bc669ec87f0976121815.1264941563.git.wuzhangjin@gmail.com> User-Agent: Mutt/1.5.20 (2009-08-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25871 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Sun, Jan 31, 2010 at 08:39:40PM +0800, Wu Zhangjin wrote: Thanks, queued for 2.6.34. Ralf From chris@mips.com Wed Feb 3 20:15:17 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 03 Feb 2010 20:15:29 +0100 (CET) Received: from dns1.mips.com ([63.167.95.197]:48920 "EHLO dns1.mips.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492715Ab0BCTPR (ORCPT ); Wed, 3 Feb 2010 20:15:17 +0100 Received: from MTVEXCHANGE.mips.com ([192.168.36.60]) by dns1.mips.com (8.13.8/8.13.8) with ESMTP id o13JF6cE009952; Wed, 3 Feb 2010 11:15:06 -0800 Received: from [192.168.65.41] ([192.168.65.41]) by MTVEXCHANGE.mips.com with Microsoft SMTPSVC(6.0.3790.3959); Wed, 3 Feb 2010 11:15:06 -0800 Message-ID: <4B69CB39.1090504@mips.com> Date: Wed, 03 Feb 2010 11:15:05 -0800 From: Chris Dearman Organization: MIPS Technologies User-Agent: Thunderbird 2.0.0.23 (X11/20090817) MIME-Version: 1.0 To: "Anoop P.A." CC: Ralf Baechle , linux-mips@linux-mips.org Subject: Re: Cached Base address difference. References: <1265015455-32553-1-git-send-email-wuzhangjin@gmail.com> <20100203012934.GA20375@linux-mips.org> <20100203123331.GB20375@linux-mips.org> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 03 Feb 2010 19:15:06.0228 (UTC) FILETIME=[31CAE340:01CAA505] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25872 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: chris@mips.com Precedence: bulk X-list: linux-mips Anoop P.A. wrote: > Hi Ralf, > > I am sorry if it is not clear from my last mail. > > What I want to convey is, > > "See MIPS Run" explains "window on physical memory (cached)" will start > @ 0x9000_0000_0000_0000. > > You can see "See MIPS Run" page under suspect from this link > http://books.google.co.in/books?id=kk8G2gK4Tw8C&lpg=PP1&dq=see%20mips%20 > run&pg=PA51#v=onepage&q=&f=false > > How ever as you mentioned Linux source defines CAC_BASE > 0x98000000_00000000 The Linux header file is correct; the cached and uncached regions are swapped in the "See MIPS Run" diagram. The full MIPS64 memory map is documented in Volume III of the architecture manual which you can download from http://www.mips.com/products/architectures/mips64/ Chris -- Chris Dearman Desk: +1 408 530 5092 Cell: +1 408 398 5531 MIPS Technologies Inc 955 East Arques Ave, Sunnyvale CA 94085 From groeck@ericsson.com Wed Feb 3 23:21:21 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 03 Feb 2010 23:21:28 +0100 (CET) Received: from imr2.ericy.com ([198.24.6.3]:54448 "EHLO imr2.ericy.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492841Ab0BCWVV (ORCPT ); Wed, 3 Feb 2010 23:21:21 +0100 Received: from eusaamw0707.eamcs.ericsson.se ([147.117.20.32]) by imr2.ericy.com (8.13.1/8.13.1) with ESMTP id o13MMH3Z032037 for ; Wed, 3 Feb 2010 16:22:24 -0600 Received: from localhost (147.117.20.212) by eusaamw0707.eamcs.ericsson.se (147.117.20.92) with Microsoft SMTP Server id 8.1.375.2; Wed, 3 Feb 2010 17:21:07 -0500 Date: Wed, 3 Feb 2010 14:22:50 -0800 From: Guenter Roeck To: linux-mips@linux-mips.org Subject: VMALLOC_END, TASK_SIZE and FIXADDR_START for 64 bit MIPS kernels Message-ID: <20100203222250.GA21139@ericsson.com> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25873 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: guenter.roeck@ericsson.com Precedence: bulk X-list: linux-mips Hi, since it came up during the review of the patch for virtual memory detection on 64 bit mips kernels, I looked further into making vmalloc_end a variable and TASK_SIZE dependent on the virtual memory size. That turned out to be relatively straightforward, and I have a working patch. The one question I still have is about FIXADDR_START. It is currently set to one of 0xff000000, 0xfffe0000, or (0xff000000 - 0x20000), depending on the target CPU. Quoting from one of the comments during the review, " ... ensure the value of vmalloc_end is <= FIXADDR_START". Obviously that is currently not the case. Is that a concern, or is it good as it is ? Thanks, Guenter From David.Daney@caviumnetworks.com Thu Feb 4 20:32:59 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 04 Feb 2010 20:33:05 +0100 (CET) Received: from mail3.caviumnetworks.com ([12.108.191.235]:17507 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1493045Ab0BDTc6 (ORCPT ); Thu, 4 Feb 2010 20:32:58 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Thu, 04 Feb 2010 11:33:02 -0800 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Thu, 4 Feb 2010 11:31:54 -0800 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Thu, 4 Feb 2010 11:31:54 -0800 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.2/8.14.2) with ESMTP id o14JVooQ001705; Thu, 4 Feb 2010 11:31:50 -0800 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.2/8.14.2/Submit) id o14JVnLV001704; Thu, 4 Feb 2010 11:31:49 -0800 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: David Daney Subject: [PATCH] MIPS: Optimize spinlocks. Date: Thu, 4 Feb 2010 11:31:49 -0800 Message-Id: <1265311909-1679-1-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.6.0.6 X-OriginalArrivalTime: 04 Feb 2010 19:31:54.0872 (UTC) FILETIME=[B5677F80:01CAA5D0] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25874 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips The current locking mechanism uses a ll/sc sequence to release a spinlock. This is slower than a wmb() followed by a store to unlock. The branching forward to .subsection 2 on sc failure slows down the contended case. So we get rid of that part too. Since we are now working on naturally aligned u16 values, we can get rid of a masking operation as the LHU already does the right thing. The ANDI are reversed for better scheduling on multi-issue CPUs On a 12 CPU 750MHz Octeon cn5750 this patch improves ipv4 UDP packet forwarding rates from 3.58*10^6 PPS to 3.99*10^6 PPS, or about 11%. Signed-off-by: David Daney --- arch/mips/include/asm/barrier.h | 6 ++ arch/mips/include/asm/spinlock.h | 118 ++++++++++++-------------------- arch/mips/include/asm/spinlock_types.h | 24 +++++-- 3 files changed, 67 insertions(+), 81 deletions(-) diff --git a/arch/mips/include/asm/barrier.h b/arch/mips/include/asm/barrier.h index a2670a2..c0884f0 100644 --- a/arch/mips/include/asm/barrier.h +++ b/arch/mips/include/asm/barrier.h @@ -168,8 +168,14 @@ #ifdef CONFIG_CPU_CAVIUM_OCTEON #define smp_mb__before_llsc() smp_wmb() +/* Cause previous writes to become visible on all CPUs as soon as possible */ +#define nudge_writes() __asm__ __volatile__(".set push\n\t" \ + ".set arch=octeon\n\t" \ + "syncw\n\t" \ + ".set pop" : : : "memory") #else #define smp_mb__before_llsc() smp_llsc_mb() +#define nudge_writes() mb() #endif #endif /* __ASM_BARRIER_H */ diff --git a/arch/mips/include/asm/spinlock.h b/arch/mips/include/asm/spinlock.h index 5f16696..396e402 100644 --- a/arch/mips/include/asm/spinlock.h +++ b/arch/mips/include/asm/spinlock.h @@ -36,9 +36,9 @@ static inline int arch_spin_is_locked(arch_spinlock_t *lock) { - unsigned int counters = ACCESS_ONCE(lock->lock); + u32 counters = ACCESS_ONCE(lock->lock); - return ((counters >> 14) ^ counters) & 0x1fff; + return ((counters >> 16) ^ counters) & 0xffff; } #define arch_spin_lock_flags(lock, flags) arch_spin_lock(lock) @@ -47,9 +47,9 @@ static inline int arch_spin_is_locked(arch_spinlock_t *lock) static inline int arch_spin_is_contended(arch_spinlock_t *lock) { - unsigned int counters = ACCESS_ONCE(lock->lock); + u32 counters = ACCESS_ONCE(lock->lock); - return (((counters >> 14) - counters) & 0x1fff) > 1; + return (((counters >> 16) - counters) & 0xffff) > 1; } #define arch_spin_is_contended arch_spin_is_contended @@ -57,6 +57,7 @@ static inline void arch_spin_lock(arch_spinlock_t *lock) { int my_ticket; int tmp; + int inc = 0x10000; if (R10000_LLSC_WAR) { __asm__ __volatile__ ( @@ -64,25 +65,24 @@ static inline void arch_spin_lock(arch_spinlock_t *lock) " .set noreorder \n" " \n" "1: ll %[ticket], %[ticket_ptr] \n" - " addiu %[my_ticket], %[ticket], 0x4000 \n" + " addu %[my_ticket], %[ticket], %[inc] \n" " sc %[my_ticket], %[ticket_ptr] \n" " beqzl %[my_ticket], 1b \n" " nop \n" - " srl %[my_ticket], %[ticket], 14 \n" - " andi %[my_ticket], %[my_ticket], 0x1fff \n" - " andi %[ticket], %[ticket], 0x1fff \n" + " srl %[my_ticket], %[ticket], 16 \n" + " andi %[ticket], %[ticket], 0xffff \n" + " andi %[my_ticket], %[my_ticket], 0xffff \n" " bne %[ticket], %[my_ticket], 4f \n" " subu %[ticket], %[my_ticket], %[ticket] \n" "2: \n" " .subsection 2 \n" - "4: andi %[ticket], %[ticket], 0x1fff \n" + "4: andi %[ticket], %[ticket], 0xffff \n" " sll %[ticket], 5 \n" " \n" "6: bnez %[ticket], 6b \n" " subu %[ticket], 1 \n" " \n" - " lw %[ticket], %[ticket_ptr] \n" - " andi %[ticket], %[ticket], 0x1fff \n" + " lhu %[ticket], %[serving_now_ptr] \n" " beq %[ticket], %[my_ticket], 2b \n" " subu %[ticket], %[my_ticket], %[ticket] \n" " b 4b \n" @@ -90,36 +90,33 @@ static inline void arch_spin_lock(arch_spinlock_t *lock) " .previous \n" " .set pop \n" : [ticket_ptr] "+m" (lock->lock), + [serving_now_ptr] "+m" (lock->h.serving_now), [ticket] "=&r" (tmp), - [my_ticket] "=&r" (my_ticket)); + [my_ticket] "=&r" (my_ticket) + : [inc] "r" (inc)); } else { __asm__ __volatile__ ( " .set push # arch_spin_lock \n" " .set noreorder \n" " \n" - " ll %[ticket], %[ticket_ptr] \n" - "1: addiu %[my_ticket], %[ticket], 0x4000 \n" + "1: ll %[ticket], %[ticket_ptr] \n" + " addu %[my_ticket], %[ticket], %[inc] \n" " sc %[my_ticket], %[ticket_ptr] \n" - " beqz %[my_ticket], 3f \n" - " nop \n" - " srl %[my_ticket], %[ticket], 14 \n" - " andi %[my_ticket], %[my_ticket], 0x1fff \n" - " andi %[ticket], %[ticket], 0x1fff \n" + " beqz %[my_ticket], 1b \n" + " srl %[my_ticket], %[ticket], 16 \n" + " andi %[ticket], %[ticket], 0xffff \n" + " andi %[my_ticket], %[my_ticket], 0xffff \n" " bne %[ticket], %[my_ticket], 4f \n" " subu %[ticket], %[my_ticket], %[ticket] \n" "2: \n" " .subsection 2 \n" - "3: b 1b \n" - " ll %[ticket], %[ticket_ptr] \n" - " \n" "4: andi %[ticket], %[ticket], 0x1fff \n" " sll %[ticket], 5 \n" " \n" "6: bnez %[ticket], 6b \n" " subu %[ticket], 1 \n" " \n" - " lw %[ticket], %[ticket_ptr] \n" - " andi %[ticket], %[ticket], 0x1fff \n" + " lhu %[ticket], %[serving_now_ptr] \n" " beq %[ticket], %[my_ticket], 2b \n" " subu %[ticket], %[my_ticket], %[ticket] \n" " b 4b \n" @@ -127,8 +124,10 @@ static inline void arch_spin_lock(arch_spinlock_t *lock) " .previous \n" " .set pop \n" : [ticket_ptr] "+m" (lock->lock), + [serving_now_ptr] "+m" (lock->h.serving_now), [ticket] "=&r" (tmp), - [my_ticket] "=&r" (my_ticket)); + [my_ticket] "=&r" (my_ticket) + : [inc] "r" (inc)); } smp_llsc_mb(); @@ -136,47 +135,16 @@ static inline void arch_spin_lock(arch_spinlock_t *lock) static inline void arch_spin_unlock(arch_spinlock_t *lock) { - int tmp; - - smp_mb__before_llsc(); - - if (R10000_LLSC_WAR) { - __asm__ __volatile__ ( - " # arch_spin_unlock \n" - "1: ll %[ticket], %[ticket_ptr] \n" - " addiu %[ticket], %[ticket], 1 \n" - " ori %[ticket], %[ticket], 0x2000 \n" - " xori %[ticket], %[ticket], 0x2000 \n" - " sc %[ticket], %[ticket_ptr] \n" - " beqzl %[ticket], 1b \n" - : [ticket_ptr] "+m" (lock->lock), - [ticket] "=&r" (tmp)); - } else { - __asm__ __volatile__ ( - " .set push # arch_spin_unlock \n" - " .set noreorder \n" - " \n" - " ll %[ticket], %[ticket_ptr] \n" - "1: addiu %[ticket], %[ticket], 1 \n" - " ori %[ticket], %[ticket], 0x2000 \n" - " xori %[ticket], %[ticket], 0x2000 \n" - " sc %[ticket], %[ticket_ptr] \n" - " beqz %[ticket], 2f \n" - " nop \n" - " \n" - " .subsection 2 \n" - "2: b 1b \n" - " ll %[ticket], %[ticket_ptr] \n" - " .previous \n" - " .set pop \n" - : [ticket_ptr] "+m" (lock->lock), - [ticket] "=&r" (tmp)); - } + unsigned int serving_now = lock->h.serving_now + 1; + wmb(); + lock->h.serving_now = (u16)serving_now; + nudge_writes(); } static inline unsigned int arch_spin_trylock(arch_spinlock_t *lock) { int tmp, tmp2, tmp3; + int inc = 0x10000; if (R10000_LLSC_WAR) { __asm__ __volatile__ ( @@ -184,11 +152,11 @@ static inline unsigned int arch_spin_trylock(arch_spinlock_t *lock) " .set noreorder \n" " \n" "1: ll %[ticket], %[ticket_ptr] \n" - " srl %[my_ticket], %[ticket], 14 \n" - " andi %[my_ticket], %[my_ticket], 0x1fff \n" - " andi %[now_serving], %[ticket], 0x1fff \n" + " srl %[my_ticket], %[ticket], 16 \n" + " andi %[my_ticket], %[my_ticket], 0xffff \n" + " andi %[now_serving], %[ticket], 0xffff \n" " bne %[my_ticket], %[now_serving], 3f \n" - " addiu %[ticket], %[ticket], 0x4000 \n" + " addu %[ticket], %[ticket], %[inc] \n" " sc %[ticket], %[ticket_ptr] \n" " beqzl %[ticket], 1b \n" " li %[ticket], 1 \n" @@ -201,33 +169,33 @@ static inline unsigned int arch_spin_trylock(arch_spinlock_t *lock) : [ticket_ptr] "+m" (lock->lock), [ticket] "=&r" (tmp), [my_ticket] "=&r" (tmp2), - [now_serving] "=&r" (tmp3)); + [now_serving] "=&r" (tmp3) + : [inc] "r" (inc)); } else { __asm__ __volatile__ ( " .set push # arch_spin_trylock \n" " .set noreorder \n" " \n" - " ll %[ticket], %[ticket_ptr] \n" - "1: srl %[my_ticket], %[ticket], 14 \n" - " andi %[my_ticket], %[my_ticket], 0x1fff \n" - " andi %[now_serving], %[ticket], 0x1fff \n" + "1: ll %[ticket], %[ticket_ptr] \n" + " srl %[my_ticket], %[ticket], 16 \n" + " andi %[my_ticket], %[my_ticket], 0xffff \n" + " andi %[now_serving], %[ticket], 0xffff \n" " bne %[my_ticket], %[now_serving], 3f \n" - " addiu %[ticket], %[ticket], 0x4000 \n" + " addu %[ticket], %[ticket], %[inc] \n" " sc %[ticket], %[ticket_ptr] \n" - " beqz %[ticket], 4f \n" + " beqz %[ticket], 1b \n" " li %[ticket], 1 \n" "2: \n" " .subsection 2 \n" "3: b 2b \n" " li %[ticket], 0 \n" - "4: b 1b \n" - " ll %[ticket], %[ticket_ptr] \n" " .previous \n" " .set pop \n" : [ticket_ptr] "+m" (lock->lock), [ticket] "=&r" (tmp), [my_ticket] "=&r" (tmp2), - [now_serving] "=&r" (tmp3)); + [now_serving] "=&r" (tmp3) + : [inc] "r" (inc)); } smp_llsc_mb(); diff --git a/arch/mips/include/asm/spinlock_types.h b/arch/mips/include/asm/spinlock_types.h index ee197c2..c52f360 100644 --- a/arch/mips/include/asm/spinlock_types.h +++ b/arch/mips/include/asm/spinlock_types.h @@ -5,16 +5,28 @@ # error "please don't include this file directly" #endif -typedef struct { +#include + +#include + +typedef union { /* - * bits 0..13: serving_now - * bits 14 : junk data - * bits 15..28: ticket + * bits 0..15 : serving_now + * bits 16..31 : ticket */ - unsigned int lock; + u32 lock; + struct { +#ifdef __BIG_ENDIAN + u16 ticket; + u16 serving_now; +#else + u16 serving_now; + u16 ticket; +#endif + } h; } arch_spinlock_t; -#define __ARCH_SPIN_LOCK_UNLOCKED { 0 } +#define __ARCH_SPIN_LOCK_UNLOCKED { .lock = 0 } typedef struct { volatile unsigned int lock; -- 1.6.0.6 From David.Daney@caviumnetworks.com Fri Feb 5 00:49:46 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 05 Feb 2010 00:49:50 +0100 (CET) Received: from mail3.caviumnetworks.com ([12.108.191.235]:5227 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1493178Ab0BDXtq (ORCPT ); Fri, 5 Feb 2010 00:49:46 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Thu, 04 Feb 2010 15:49:52 -0800 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Thu, 4 Feb 2010 15:48:55 -0800 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Thu, 4 Feb 2010 15:48:55 -0800 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.2/8.14.2) with ESMTP id o14Nmpfb002974; Thu, 4 Feb 2010 15:48:51 -0800 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.2/8.14.2/Submit) id o14Nmnmi002973; Thu, 4 Feb 2010 15:48:49 -0800 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: David Daney Subject: [PATCH] MIPS: Fix __devinit __cpuinit confusion in cpu_cache_init Date: Thu, 4 Feb 2010 15:48:49 -0800 Message-Id: <1265327329-2949-1-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.6.0.6 X-OriginalArrivalTime: 04 Feb 2010 23:48:55.0643 (UTC) FILETIME=[9CE66AB0:01CAA5F4] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25875 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips cpu_cache_init and the things it calls should all be __cpuinit instead of __devinit. Signed-off-by: David Daney --- arch/mips/mm/c-octeon.c | 4 ++-- arch/mips/mm/cache.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/mips/mm/c-octeon.c b/arch/mips/mm/c-octeon.c index e75174a..af85959 100644 --- a/arch/mips/mm/c-octeon.c +++ b/arch/mips/mm/c-octeon.c @@ -174,7 +174,7 @@ static void octeon_flush_cache_page(struct vm_area_struct *vma, * Probe Octeon's caches * */ -static void __devinit probe_octeon(void) +static void __cpuinit probe_octeon(void) { unsigned long icache_size; unsigned long dcache_size; @@ -235,7 +235,7 @@ static void __devinit probe_octeon(void) * Setup the Octeon cache flush routines * */ -void __devinit octeon_cache_init(void) +void __cpuinit octeon_cache_init(void) { extern unsigned long ebase; extern char except_vec2_octeon; diff --git a/arch/mips/mm/cache.c b/arch/mips/mm/cache.c index 102b2df..e716caf 100644 --- a/arch/mips/mm/cache.c +++ b/arch/mips/mm/cache.c @@ -155,7 +155,7 @@ static inline void setup_protection_map(void) protection_map[15] = PAGE_SHARED; } -void __devinit cpu_cache_init(void) +void __cpuinit cpu_cache_init(void) { if (cpu_has_3k_cache) { extern void __weak r3k_cache_init(void); -- 1.6.0.6 From ralf@linux-mips.org Fri Feb 5 07:36:41 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 05 Feb 2010 07:36:49 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:45585 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491914Ab0BEGgl (ORCPT ); Fri, 5 Feb 2010 07:36:41 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id o156awjQ010991; Fri, 5 Feb 2010 07:36:58 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id o156avId010989; Fri, 5 Feb 2010 07:36:57 +0100 Date: Fri, 5 Feb 2010 07:36:56 +0100 From: Ralf Baechle To: David Daney Cc: linux-mips@linux-mips.org Subject: Re: [PATCH] MIPS: Fix __devinit __cpuinit confusion in cpu_cache_init Message-ID: <20100205063656.GA10884@linux-mips.org> References: <1265327329-2949-1-git-send-email-ddaney@caviumnetworks.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1265327329-2949-1-git-send-email-ddaney@caviumnetworks.com> User-Agent: Mutt/1.5.20 (2009-08-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25876 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Thu, Feb 04, 2010 at 03:48:49PM -0800, David Daney wrote: > cpu_cache_init and the things it calls should all be __cpuinit instead > of __devinit. > > Signed-off-by: David Daney Thanks, Ralf From muthukumaranbe@gmail.com Fri Feb 5 09:05:13 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 05 Feb 2010 09:05:16 +0100 (CET) Received: from mail-fx0-f216.google.com ([209.85.220.216]:57434 "EHLO mail-fx0-f216.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491885Ab0BEIFN (ORCPT ); Fri, 5 Feb 2010 09:05:13 +0100 Received: by fxm8 with SMTP id 8so1986552fxm.26 for ; Fri, 05 Feb 2010 00:05:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:date:message-id:subject :from:to:content-type; bh=BQVG624v9Cm8y5VEcn3X0UsjtJAUlHG7BpApqSatp8g=; b=MfVXz2ijLCfnhLZ4bn21Y0AWHgCtZrBsFwNlid6/r2GXGeix8LAP/8nIUx7MfxI/9T /2tGiURRZw+l0cZ6j4Qsr7Ty54Tv0traRceJlZA/fEG13xNQRcjRGXM+fpmrP6dy4ohp TzrffPP9Hkslyyaz8uI5yDWKrLt+XViNMQDCY= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:date:message-id:subject:from:to:content-type; b=gWWcrqwfOqvtMBNLkwY0LxWBywI3eX5AMYD7Wx+Y+BIH/rbKPh0P+LzAuj6KFgneIg TGN2yxStWDzmLf4/38tTTxxt+TIZcGnYEN+YfmYZixwsergV246nRhpX+PFDPmEIqdOp zptZ413FsvkZ17IMewlSIYhh0y9xW37ko0y+0= MIME-Version: 1.0 Received: by 10.223.6.70 with SMTP id 6mr1960818fay.29.1265357107235; Fri, 05 Feb 2010 00:05:07 -0800 (PST) Date: Fri, 5 Feb 2010 08:05:07 +0000 Message-ID: <4101f55c1002050005t1d7e1b09qe988e39932dfc411@mail.gmail.com> Subject: Switch FPU emulator trap to BREAK instruction From: Muthu Kumaran To: linux-mips@linux-mips.org Content-Type: text/plain; charset=ISO-8859-1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25877 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: muthukumaranbe@gmail.com Precedence: bulk X-list: linux-mips I am using 2.6.18 linux version on MIPS32 core. One of the application is using intensive floating point operations. This hardware doesn't have FPU and also the application is not compiled for software floating point support. Hence, it is using the floating point emulation. While running that application, On a timer interrupt there is a normal integer div instruction which gives wrong result in the HI register. However, when I applied the following patch, this problem disappeared. http://kerneltrap.org/mailarchive/git-commits-head/2008/10/30/3873324 When I looked into the patch, handling of invalid instruction exception is moved from trap to break. There is no other behavioural change in this patch. I really don't understand the need for this patch, May I ask someone to explain the background information behind this patch? Is this for any known issue? Thanks. I am new to both Linux and also MIPS core. -- http://testbed.aws.cit.ie/panneer From yuasa.linux@gmail.com Fri Feb 5 15:31:50 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 05 Feb 2010 15:31:54 +0100 (CET) Received: from mail-bw0-f226.google.com ([209.85.218.226]:65145 "EHLO mail-bw0-f226.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492671Ab0BEObu (ORCPT ); Fri, 5 Feb 2010 15:31:50 +0100 Received: by bwz26 with SMTP id 26so2930219bwz.27 for ; Fri, 05 Feb 2010 06:31:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:sender:date:from:to:cc :subject:message-id:x-mailer:mime-version:content-type :content-transfer-encoding; bh=MTLGAMuDiiCeZcUH3iOiJOiWEydDfWUmjVK4EuKv60Y=; b=LzzuIqSfVNXTU96aMd/QMq9ttaDxx2tCLIo8/wbGCrDrj3jEPHi0DRHwucZyeCcnIw QgDwF1ZZNDcCyX4Jiu07QNfN7rbNvfEEOdby27jubPHT+NwSdeAI3HROHVneEIsUVFw7 EGZ7gEXS3irOjo7d2tBiLHtMINZ99zDQnbVzg= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:date:from:to:cc:subject:message-id:x-mailer:mime-version :content-type:content-transfer-encoding; b=ihFkemBDStS6n6fvcI8yEnfh/F1MtTDJAxIN6cfaie123x8CCbwWO2awXFLvX7W4WF GJUyzvEjs4F0vh2xpwKw9gyCTwx6vFxRGveb1OIsujMXrGQdn967e3fjzijL3XlrtnQW CCEzZzi7YCci9bS8fJxfEDD9A/4HbkqH1CnPg= Received: by 10.204.156.204 with SMTP id y12mr1807566bkw.3.1265380304539; Fri, 05 Feb 2010 06:31:44 -0800 (PST) Received: from ypsilon.skybright.jp (sannin29006.nirai.ne.jp [203.160.29.6]) by mx.google.com with ESMTPS id 16sm641571bwz.7.2010.02.05.06.31.40 (version=TLSv1/SSLv3 cipher=RC4-MD5); Fri, 05 Feb 2010 06:31:42 -0800 (PST) Date: Fri, 5 Feb 2010 23:28:57 +0900 From: Yoichi Yuasa To: Ralf Baechle Cc: yuasa@linux-mips.org, linux-mips Subject: [PATCH 1/2] MIPS: add 8250/16550 serial early printk driver Message-Id: <20100205232857.eb65967f.yuasa@linux-mips.org> X-Mailer: Sylpheed 2.7.1 (GTK+ 2.16.6; i686-pc-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25878 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: yuasa@linux-mips.org Precedence: bulk X-list: linux-mips Signed-off-by: Yoichi Yuasa --- arch/mips/Kconfig.debug | 8 ++++ arch/mips/include/asm/setup.h | 9 ++++ arch/mips/kernel/Makefile | 1 + arch/mips/kernel/early_printk_8250.c | 68 ++++++++++++++++++++++++++++++++++ 4 files changed, 86 insertions(+), 0 deletions(-) create mode 100644 arch/mips/kernel/early_printk_8250.c diff --git a/arch/mips/Kconfig.debug b/arch/mips/Kconfig.debug index 32a010d..f5d739c 100644 --- a/arch/mips/Kconfig.debug +++ b/arch/mips/Kconfig.debug @@ -20,6 +20,14 @@ config EARLY_PRINTK doesn't cooperate with an X server. You should normally say N here, unless you want to debug such a crash. +config EARLY_PRINTK_8250 + bool "8250/16550 and compatible serial early printk driver" + depends on EARLY_PRINTK + default n + help + If you say Y here, it will be possible to use a 8250/16550 serial + port as the boot console. + config CMDLINE_BOOL bool "Built-in kernel command line" default n diff --git a/arch/mips/include/asm/setup.h b/arch/mips/include/asm/setup.h index 50511aa..7395b7f 100644 --- a/arch/mips/include/asm/setup.h +++ b/arch/mips/include/asm/setup.h @@ -5,6 +5,15 @@ #ifdef __KERNEL__ extern void setup_early_printk(void); + +#ifdef CONFIG_EARLY_PRINTK_8250 +extern void setup_8250_early_printk_port(unsigned long base, + unsigned int reg_shift, unsigned int timeout); +#else +static inline void setup_8250_early_printk_port(unsigned long base, + unsigned int reg_shift, unsigned int timeout) {} +#endif + #endif /* __KERNEL__ */ #endif /* __SETUP_H */ diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile index 9326af5..03fc037 100644 --- a/arch/mips/kernel/Makefile +++ b/arch/mips/kernel/Makefile @@ -93,6 +93,7 @@ obj-$(CONFIG_GPIO_TXX9) += gpio_txx9.o obj-$(CONFIG_KEXEC) += machine_kexec.o relocate_kernel.o obj-$(CONFIG_EARLY_PRINTK) += early_printk.o +obj-$(CONFIG_EARLY_PRINTK_8250) += early_printk_8250.o CFLAGS_cpu-bugs64.o = $(shell if $(CC) $(KBUILD_CFLAGS) -Wa,-mdaddi -c -o /dev/null -xc /dev/null >/dev/null 2>&1; then echo "-DHAVE_AS_SET_DADDI"; fi) diff --git a/arch/mips/kernel/early_printk_8250.c b/arch/mips/kernel/early_printk_8250.c new file mode 100644 index 0000000..6faf8fd --- /dev/null +++ b/arch/mips/kernel/early_printk_8250.c @@ -0,0 +1,68 @@ +/* + * 8250/16550-type serial ports prom_putchar() + * + * Copyright (C) 2010 Yoichi Yuasa + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include +#include +#include + +static unsigned long serial8250_base; +static unsigned int serial8250_reg_shift; +static unsigned int serial8250_tx_timeout; + +void setup_8250_early_printk_port(unsigned long base, unsigned int reg_shift, + unsigned int timeout) +{ + serial8250_base = base; + serial8250_reg_shift = reg_shift; + serial8250_tx_timeout = timeout; +} + +static inline u8 serial_in(int offset) +{ + return readb((void __iomem *)serial8250_base + + (offset << serial8250_reg_shift)); +} + +static inline void serial_out(int offset, char value) +{ + writeb(value, (void __iomem *)serial8250_base + + (offset << serial8250_reg_shift)); +} + +void prom_putchar(char c) +{ + unsigned int timeout; + int status, bits; + + if (!serial8250_base) + return; + + timeout = serial8250_tx_timeout; + bits = UART_LSR_TEMT | UART_LSR_THRE; + + do { + status = serial_in(UART_LSR); + + if (--timeout == 0) + break; + } while ((status & bits) != bits); + + if (timeout) + serial_out(UART_TX, c); +} -- 1.6.6.1 From yuasa.linux@gmail.com Fri Feb 5 15:32:13 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 05 Feb 2010 15:32:19 +0100 (CET) Received: from mail-bw0-f226.google.com ([209.85.218.226]:65145 "EHLO mail-bw0-f226.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492327Ab0BEObw (ORCPT ); Fri, 5 Feb 2010 15:31:52 +0100 Received: by mail-bw0-f226.google.com with SMTP id 26so2930219bwz.27 for ; Fri, 05 Feb 2010 06:31:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:sender:date:from:to:cc :subject:message-id:in-reply-to:references:x-mailer:mime-version :content-type:content-transfer-encoding; bh=toRsyyfK3NJNbwu0r8axAZVHDTeeSKh5qnVNH6rvKfw=; b=awt7HKi3ZObqsUcFYSxNpEuaArKOq//UPnnRHj+7vrMce/nJsSuLsGxY6yZNKOn9td ABMfebMMqL5KzYsN8cCZkv039Rq7EWOH4JpDOThMkiqTF3Il1quI5wmjockq30H6E7U8 fBoEYA9n0Z7KJHb/aowgK4SMAcd6u+zFAbckE= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:date:from:to:cc:subject:message-id:in-reply-to:references :x-mailer:mime-version:content-type:content-transfer-encoding; b=rQLNDnIZsHZ21r/dwkyDuLf5NVXlfKlJbvPW4mZ6I6cHUkgNaf6baHLNoIN7vixGRe SHA0kganF2PyR1yU+60k2McDjh2sFBKUyqvkIu8hUeH7ZM/LZoEaB+p1ZtFardcwVyXK S/cIon9z9VCZyGr0/gM8yLsL9IdQNP1NcCBRA= Received: by 10.204.33.135 with SMTP id h7mr250859bkd.186.1265380312701; Fri, 05 Feb 2010 06:31:52 -0800 (PST) Received: from ypsilon.skybright.jp (sannin29006.nirai.ne.jp [203.160.29.6]) by mx.google.com with ESMTPS id 13sm647328bwz.6.2010.02.05.06.31.49 (version=TLSv1/SSLv3 cipher=RC4-MD5); Fri, 05 Feb 2010 06:31:52 -0800 (PST) Date: Fri, 5 Feb 2010 23:30:31 +0900 From: Yoichi Yuasa To: Ralf Baechle Cc: yuasa@linux-mips.org, linux-mips Subject: [PATCH 2/2] MIPS: Cobalt move to 8250/16550 serial early printk driver Message-Id: <20100205233031.38c5d6be.yuasa@linux-mips.org> In-Reply-To: <20100205232857.eb65967f.yuasa@linux-mips.org> References: <20100205232857.eb65967f.yuasa@linux-mips.org> X-Mailer: Sylpheed 2.7.1 (GTK+ 2.16.6; i686-pc-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25879 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: yuasa@linux-mips.org Precedence: bulk X-list: linux-mips Signed-off-by: Yoichi Yuasa --- arch/mips/Kconfig | 1 + arch/mips/cobalt/Makefile | 1 - arch/mips/cobalt/console.c | 20 -------------------- arch/mips/cobalt/setup.c | 3 +++ 4 files changed, 4 insertions(+), 21 deletions(-) delete mode 100644 arch/mips/cobalt/console.c diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 591ca0c..b848512 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -90,6 +90,7 @@ config MIPS_COBALT select CSRC_R4K select CEVT_GT641XX select DMA_NONCOHERENT + select EARLY_PRINTK_8250 if EARLY_PRINTK select HW_HAS_PCI select I8253 select I8259 diff --git a/arch/mips/cobalt/Makefile b/arch/mips/cobalt/Makefile index 2379262..5cfe90f 100644 --- a/arch/mips/cobalt/Makefile +++ b/arch/mips/cobalt/Makefile @@ -5,7 +5,6 @@ obj-y := buttons.o irq.o lcd.o led.o reset.o rtc.o serial.o setup.o time.o obj-$(CONFIG_PCI) += pci.o -obj-$(CONFIG_EARLY_PRINTK) += console.o obj-$(CONFIG_MTD_PHYSMAP) += mtd.o EXTRA_CFLAGS += -Werror diff --git a/arch/mips/cobalt/console.c b/arch/mips/cobalt/console.c deleted file mode 100644 index d1ba701..0000000 --- a/arch/mips/cobalt/console.c +++ /dev/null @@ -1,20 +0,0 @@ -/* - * (C) P. Horton 2006 - */ -#include -#include - -#include - -#define UART_BASE ((void __iomem *)CKSEG1ADDR(0x1c800000)) - -void prom_putchar(char c) -{ - if (cobalt_board_id <= COBALT_BRD_ID_QUBE1) - return; - - while (!(readb(UART_BASE + UART_LSR) & UART_LSR_THRE)) - ; - - writeb(c, UART_BASE + UART_TX); -} diff --git a/arch/mips/cobalt/setup.c b/arch/mips/cobalt/setup.c index ec3b2c4..9a8c2fe 100644 --- a/arch/mips/cobalt/setup.c +++ b/arch/mips/cobalt/setup.c @@ -17,6 +17,7 @@ #include #include +#include #include #include @@ -112,6 +113,8 @@ void __init prom_init(void) } add_memory_region(0x0, memsz, BOOT_MEM_RAM); + + setup_8250_early_printk_port(CKSEG1ADDR(0x1c800000), 0, 0); } void __init prom_free_prom_memory(void) -- 1.6.6.1 From David.Daney@caviumnetworks.com Fri Feb 5 18:37:13 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 05 Feb 2010 18:37:20 +0100 (CET) Received: from mail3.caviumnetworks.com ([12.108.191.235]:3534 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492052Ab0BERhN (ORCPT ); Fri, 5 Feb 2010 18:37:13 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Fri, 05 Feb 2010 09:37:17 -0800 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Fri, 5 Feb 2010 09:36:22 -0800 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Fri, 5 Feb 2010 09:36:22 -0800 Message-ID: <4B6C5714.3080603@caviumnetworks.com> Date: Fri, 05 Feb 2010 09:36:20 -0800 From: David Daney User-Agent: Thunderbird 2.0.0.21 (X11/20090320) MIME-Version: 1.0 To: Muthu Kumaran CC: linux-mips@linux-mips.org Subject: Re: Switch FPU emulator trap to BREAK instruction References: <4101f55c1002050005t1d7e1b09qe988e39932dfc411@mail.gmail.com> In-Reply-To: <4101f55c1002050005t1d7e1b09qe988e39932dfc411@mail.gmail.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 05 Feb 2010 17:36:22.0298 (UTC) FILETIME=[BBAE67A0:01CAA689] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25880 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Muthu Kumaran wrote: > I am using 2.6.18 linux version on MIPS32 core. One of the application > is using intensive floating point operations. This hardware doesn't > have FPU and also the application is not compiled for software > floating point support. > Hence, it is using the floating point emulation. > > While running that application, On a timer interrupt there is a normal > integer div instruction which gives wrong result in the HI register. > > However, when I applied the following patch, this problem disappeared. > > http://kerneltrap.org/mailarchive/git-commits-head/2008/10/30/3873324 > > When I looked into the patch, handling of invalid instruction > exception is moved from trap to break. Incorrect analysis. It was changed from an Adress Error (ADE) exception to a BREAK. > There is no other behavioural change in this patch. I really don't > understand the need for this patch, May I ask someone to explain the > background information behind this patch? Is this for any known issue? > The change log states the reason. FPU emulator delay slot emulation was failing on some systems. David Daney From muthukumaranbe@gmail.com Fri Feb 5 21:29:19 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 05 Feb 2010 21:29:22 +0100 (CET) Received: from mail-fx0-f216.google.com ([209.85.220.216]:52801 "EHLO mail-fx0-f216.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492866Ab0BEU3T convert rfc822-to-8bit (ORCPT ); Fri, 5 Feb 2010 21:29:19 +0100 Received: by fxm8 with SMTP id 8so2843462fxm.26 for ; Fri, 05 Feb 2010 12:29:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:in-reply-to:references :date:message-id:subject:from:to:cc:content-type :content-transfer-encoding; bh=zsV8Tb54eX4Oee3bTSEu13hF27faAt0sYklbXbiZDTo=; b=hRKiTLSIEDdl8IcfbKuqDNheZjcWFC+9jIOiugNNdXe2Z5mJFBuQm0xBn5RReTlMR6 izE+QAncEcKEcPohY7E2LFUr9unFD1eW3aDZPh2ebvbol3RK4DVXizrPdWpfXJ6j6WJZ L+k4+/eFlVnmNROwjL5SlFSSnw18i/C1kKi0o= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type:content-transfer-encoding; b=dH3qQOO3PvTplJVi7oHQ8OCwMzaiXMdanRPeJjaeKwTN1GP/q1jJrl4cdH1MDVJKAe VWxe6tW+V2N0OMaar77RK5Ukp2KbjwMxN5oyti/rieGz/rTdRLZQqWp28SjlvxANytoQ Au2J2L13rGq9J/uGGPC/YRK81wu65/HsT5J7M= MIME-Version: 1.0 Received: by 10.223.143.23 with SMTP id s23mr827970fau.50.1265401752997; Fri, 05 Feb 2010 12:29:12 -0800 (PST) In-Reply-To: <4B6C5714.3080603@caviumnetworks.com> References: <4101f55c1002050005t1d7e1b09qe988e39932dfc411@mail.gmail.com> <4B6C5714.3080603@caviumnetworks.com> Date: Fri, 5 Feb 2010 20:29:12 +0000 Message-ID: <4101f55c1002051229x73ddcb83ofd5d7acd44100737@mail.gmail.com> Subject: Re: Switch FPU emulator trap to BREAK instruction From: Muthu Kumaran To: David Daney Cc: linux-mips@linux-mips.org Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25881 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: muthukumaranbe@gmail.com Precedence: bulk X-list: linux-mips On 5 February 2010 17:36, David Daney wrote: > Muthu Kumaran wrote: >> >> I am using 2.6.18 linux version on MIPS32 core. One of the application >> is using intensive floating point operations. This hardware doesn't >> have FPU and also the application is not compiled for software >> floating point support. >> Hence, it is using the floating point emulation. >> >> While running that application, On a timer interrupt there is a normal >> integer div instruction which gives wrong result in the HI register. >> >> However, when I applied the following patch, this problem disappeared. >> >> http://kerneltrap.org/mailarchive/git-commits-head/2008/10/30/3873324 >> >> When I looked into the patch, handling of invalid instruction >> exception is moved from trap to break. > > Incorrect analysis.  It was changed from an Adress Error (ADE) exception to > a BREAK. > I am sorry, I interpreted from the heading. The following being inserted to emulate the delay slot. #define AdELOAD 0x8c000001 /* lw $0,1($0) */ > >> There is no other behavioural change in this patch. I really don't >> understand the need for this patch, May I ask someone to explain the >> background information behind this patch? Is this for any known issue? >> > > The change log states the reason.  FPU emulator delay slot emulation was > failing on some systems. > Thanks. In the morning, Ralf had pointed me "This is required only for the Cavium cnMIPS core; for all other cores this is just a more elegant implementation." I think, I put the question in wrong sentence. I intended to ask whether this fix impact MIPS32 core. Ralf also pointed me that this fix has nothing to do with the div error that I am seeing. If I dont have this patch, when I run intensive floating point operating, I am getting wrong result in HI register for a div operation. From David.Daney@caviumnetworks.com Sat Feb 6 00:26:52 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 06 Feb 2010 00:27:00 +0100 (CET) Received: from mail3.caviumnetworks.com ([12.108.191.235]:11616 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492265Ab0BEX0w (ORCPT ); Sat, 6 Feb 2010 00:26:52 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Fri, 05 Feb 2010 15:26:43 -0800 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Fri, 5 Feb 2010 15:26:04 -0800 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Fri, 5 Feb 2010 15:26:04 -0800 Message-ID: <4B6CA90C.1000609@caviumnetworks.com> Date: Fri, 05 Feb 2010 15:26:04 -0800 From: David Daney User-Agent: Thunderbird 2.0.0.21 (X11/20090320) MIME-Version: 1.0 To: Ralf Baechle , linux-mips Subject: [PATCH 0/4] MIPS Read Inhibit/eXecute Inhibit support. Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 05 Feb 2010 23:26:04.0793 (UTC) FILETIME=[96390E90:01CAA6BA] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25882 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips This patch set adds execute and read inhibit support. By default glibc based tool chains will create mappings for data areas of a program and shared libraries with PROT_EXEC cleared. With this patch applied, a SIGSEGV is correctly sent if an attempt is made to execute from data areas. We have been running this patch for close to a year. So far it seems to work well, so I ported it to the HEAD for your enjoyment. I will reply with the four patches. David Daney (4): MIPS: Use 64-bit stores to c0_entrylo on 64-bit kernels. MIPS: Add accessor functions and bit definitions for c0_PageGrain MIPS: Add TLBP to uasm. MIPS: Implement Read Inhibit/eXecute Inhibit arch/mips/Kconfig | 7 ++ arch/mips/include/asm/mipsregs.h | 11 +++ arch/mips/include/asm/pgtable-64.h | 4 + arch/mips/include/asm/pgtable-bits.h | 59 ++++++++++++- arch/mips/include/asm/pgtable.h | 39 ++++++++- arch/mips/include/asm/uasm.h | 1 + arch/mips/mm/cache.c | 11 +++ arch/mips/mm/fault.c | 23 +++++ arch/mips/mm/init.c | 2 +- arch/mips/mm/tlb-r4k.c | 15 +++- arch/mips/mm/tlbex.c | 165 ++++++++++++++++++++++++++++----- arch/mips/mm/uasm.c | 5 +- 12 files changed, 308 insertions(+), 34 deletions(-) From David.Daney@caviumnetworks.com Sat Feb 6 00:27:36 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 06 Feb 2010 00:27:40 +0100 (CET) Received: from mail3.caviumnetworks.com ([12.108.191.235]:11627 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492265Ab0BEX1g (ORCPT ); Sat, 6 Feb 2010 00:27:36 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Fri, 05 Feb 2010 15:27:43 -0800 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Fri, 5 Feb 2010 15:27:18 -0800 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Fri, 5 Feb 2010 15:27:18 -0800 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.2/8.14.2) with ESMTP id o15NRFgJ028559; Fri, 5 Feb 2010 15:27:15 -0800 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.2/8.14.2/Submit) id o15NRFFN028558; Fri, 5 Feb 2010 15:27:15 -0800 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: David Daney Subject: [PATCH 3/4] MIPS: Add TLBP to uasm. Date: Fri, 5 Feb 2010 15:27:10 -0800 Message-Id: <1265412431-28526-3-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.6.0.6 In-Reply-To: <4B6CA90C.1000609@caviumnetworks.com> References: <4B6CA90C.1000609@caviumnetworks.com> X-OriginalArrivalTime: 05 Feb 2010 23:27:18.0059 (UTC) FILETIME=[C1E48FB0:01CAA6BA] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25883 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips The soon to follow Read Inhibit/eXecute Inhibit patch needs TLBP support in uasm. Signed-off-by: David Daney --- arch/mips/include/asm/uasm.h | 1 + arch/mips/mm/uasm.c | 5 ++++- 2 files changed, 5 insertions(+), 1 deletions(-) diff --git a/arch/mips/include/asm/uasm.h b/arch/mips/include/asm/uasm.h index 3d153ed..b18588b 100644 --- a/arch/mips/include/asm/uasm.h +++ b/arch/mips/include/asm/uasm.h @@ -95,6 +95,7 @@ Ip_u2u1u3(_srl); Ip_u3u1u2(_subu); Ip_u2s3u1(_sw); Ip_0(_tlbp); +Ip_0(_tlbr); Ip_0(_tlbwi); Ip_0(_tlbwr); Ip_u3u1u2(_xor); diff --git a/arch/mips/mm/uasm.c b/arch/mips/mm/uasm.c index e3ca0f7..8f4f14d 100644 --- a/arch/mips/mm/uasm.c +++ b/arch/mips/mm/uasm.c @@ -63,7 +63,8 @@ enum opcode { insn_jr, insn_ld, insn_ll, insn_lld, insn_lui, insn_lw, insn_mfc0, insn_mtc0, insn_ori, insn_pref, insn_rfe, insn_sc, insn_scd, insn_sd, insn_sll, insn_sra, insn_srl, insn_subu, insn_sw, - insn_tlbp, insn_tlbwi, insn_tlbwr, insn_xor, insn_xori, insn_dins + insn_tlbp, insn_tlbr, insn_tlbwi, insn_tlbwr, insn_xor, insn_xori, + insn_dins }; struct insn { @@ -128,6 +129,7 @@ static struct insn insn_table[] __cpuinitdata = { { insn_subu, M(spec_op, 0, 0, 0, 0, subu_op), RS | RT | RD }, { insn_sw, M(sw_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, { insn_tlbp, M(cop0_op, cop_op, 0, 0, 0, tlbp_op), 0 }, + { insn_tlbr, M(cop0_op, cop_op, 0, 0, 0, tlbr_op), 0 }, { insn_tlbwi, M(cop0_op, cop_op, 0, 0, 0, tlbwi_op), 0 }, { insn_tlbwr, M(cop0_op, cop_op, 0, 0, 0, tlbwr_op), 0 }, { insn_xor, M(spec_op, 0, 0, 0, 0, xor_op), RS | RT | RD }, @@ -381,6 +383,7 @@ I_u2u1u3(_srl) I_u3u1u2(_subu) I_u2s3u1(_sw) I_0(_tlbp) +I_0(_tlbr) I_0(_tlbwi) I_0(_tlbwr) I_u3u1u2(_xor) -- 1.6.0.6 From David.Daney@caviumnetworks.com Sat Feb 6 00:27:59 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 06 Feb 2010 00:28:04 +0100 (CET) Received: from mail3.caviumnetworks.com ([12.108.191.235]:11628 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492910Ab0BEX1h (ORCPT ); Sat, 6 Feb 2010 00:27:37 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Fri, 05 Feb 2010 15:27:43 -0800 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Fri, 5 Feb 2010 15:27:18 -0800 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Fri, 5 Feb 2010 15:27:18 -0800 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.2/8.14.2) with ESMTP id o15NRFge028555; Fri, 5 Feb 2010 15:27:15 -0800 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.2/8.14.2/Submit) id o15NRFIA028554; Fri, 5 Feb 2010 15:27:15 -0800 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: David Daney Subject: [PATCH 2/4] MIPS: Add accessor functions and bit definitions for c0_PageGrain Date: Fri, 5 Feb 2010 15:27:09 -0800 Message-Id: <1265412431-28526-2-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.6.0.6 In-Reply-To: <4B6CA90C.1000609@caviumnetworks.com> References: <4B6CA90C.1000609@caviumnetworks.com> X-OriginalArrivalTime: 05 Feb 2010 23:27:18.0059 (UTC) FILETIME=[C1E48FB0:01CAA6BA] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25884 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Signed-off-by: David Daney --- arch/mips/include/asm/mipsregs.h | 11 +++++++++++ 1 files changed, 11 insertions(+), 0 deletions(-) diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h index b30819c..9893758 100644 --- a/arch/mips/include/asm/mipsregs.h +++ b/arch/mips/include/asm/mipsregs.h @@ -251,6 +251,14 @@ #define PL_256M 28 /* + * PageGrain bits + */ +#define PG_RIE (_ULCAST_(1) << 31) +#define PG_XIE (_ULCAST_(1) << 30) +#define PG_ELPA (_ULCAST_(1) << 29) +#define PG_ESP (_ULCAST_(1) << 28) + +/* * R4x00 interrupt enable / cause bits */ #define IE_SW0 (_ULCAST_(1) << 8) @@ -840,6 +848,9 @@ do { \ #define read_c0_pagemask() __read_32bit_c0_register($5, 0) #define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val) +#define read_c0_pagegrain() __read_32bit_c0_register($5, 1) +#define write_c0_pagegrain(val) __write_32bit_c0_register($5, 1, val) + #define read_c0_wired() __read_32bit_c0_register($6, 0) #define write_c0_wired(val) __write_32bit_c0_register($6, 0, val) -- 1.6.0.6 From David.Daney@caviumnetworks.com Sat Feb 6 00:28:23 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 06 Feb 2010 00:28:30 +0100 (CET) Received: from mail3.caviumnetworks.com ([12.108.191.235]:11629 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1493076Ab0BEX1h (ORCPT ); Sat, 6 Feb 2010 00:27:37 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Fri, 05 Feb 2010 15:27:43 -0800 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Fri, 5 Feb 2010 15:27:18 -0800 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Fri, 5 Feb 2010 15:27:18 -0800 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.2/8.14.2) with ESMTP id o15NRFa5028563; Fri, 5 Feb 2010 15:27:15 -0800 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.2/8.14.2/Submit) id o15NRFGc028562; Fri, 5 Feb 2010 15:27:15 -0800 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: David Daney Subject: [PATCH 4/4] MIPS: Implement Read Inhibit/eXecute Inhibit Date: Fri, 5 Feb 2010 15:27:11 -0800 Message-Id: <1265412431-28526-4-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.6.0.6 In-Reply-To: <4B6CA90C.1000609@caviumnetworks.com> References: <4B6CA90C.1000609@caviumnetworks.com> X-OriginalArrivalTime: 05 Feb 2010 23:27:18.0059 (UTC) FILETIME=[C1E48FB0:01CAA6BA] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25885 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips The SmartMIPS ASE specifies how Read Inhibit (RI) and eXecute Inhibit (XI) bits in the page tables work. The upper two bits of EntryLo{0,1} are RI and XI when the feature is enabled in the PageGrain register. SmartMIPS only covers 32-bit systems. Cavium Octeon+ extends this to 64-bit systems by continuing to place the RI and XI bits in the top of EntryLo even when EntryLo is 64-bits wide. This patch only targets Octeon+, but should be trivial to adapt for and 32-bit SmartMIPS system. Because we need to carry the RI and XI bits in the PTE, the layout of the PTE is changed. There is a two instruction overhead in the TLB refill hot path to get the EntryLo bits into the proper position. Also the TLB load exception has to probe the TLB to check if RI or XI caused the exception. Signed-off-by: David Daney --- arch/mips/Kconfig | 7 ++ arch/mips/include/asm/pgtable-64.h | 4 + arch/mips/include/asm/pgtable-bits.h | 59 ++++++++++++++- arch/mips/include/asm/pgtable.h | 39 +++++++++- arch/mips/mm/cache.c | 11 +++ arch/mips/mm/fault.c | 23 ++++++ arch/mips/mm/init.c | 2 +- arch/mips/mm/tlb-r4k.c | 15 +++- arch/mips/mm/tlbex.c | 145 ++++++++++++++++++++++++++++++---- 9 files changed, 282 insertions(+), 23 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index ed8d5b5..a79c424 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -1484,6 +1484,13 @@ config 64BIT endchoice +config USE_RI_XI_PAGE_BITS + bool "Use Read Inhibit (RI) and eXecute Inhibit (XI) page bits" + depends on CPU_CAVIUM_OCTEON + help + This option enables the kernel to enforce PROT_EXEC and + PROT_READ memory protection in mapped memory. + choice prompt "Kernel page size" default PAGE_SIZE_4KB diff --git a/arch/mips/include/asm/pgtable-64.h b/arch/mips/include/asm/pgtable-64.h index 2c1d194..9606d26 100644 --- a/arch/mips/include/asm/pgtable-64.h +++ b/arch/mips/include/asm/pgtable-64.h @@ -215,6 +215,10 @@ static inline void pud_clear(pud_t *pudp) #ifdef CONFIG_CPU_VR41XX #define pte_pfn(x) ((unsigned long)((x).pte >> (PAGE_SHIFT + 2))) #define pfn_pte(pfn, prot) __pte(((pfn) << (PAGE_SHIFT + 2)) | pgprot_val(prot)) +#elif defined(_PAGE_NO_EXEC) +/* The NO_READ and NO_EXEC added an extra two bits */ +#define pte_pfn(x) ((unsigned long)((x).pte >> (PAGE_SHIFT + 2))) +#define pfn_pte(pfn, prot) __pte(((pfn) << (PAGE_SHIFT + 2)) | pgprot_val(prot)) #else #define pte_pfn(x) ((unsigned long)((x).pte >> PAGE_SHIFT)) #define pfn_pte(pfn, prot) __pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot)) diff --git a/arch/mips/include/asm/pgtable-bits.h b/arch/mips/include/asm/pgtable-bits.h index 1073e6d..637d4f6 100644 --- a/arch/mips/include/asm/pgtable-bits.h +++ b/arch/mips/include/asm/pgtable-bits.h @@ -50,7 +50,48 @@ #define _CACHE_SHIFT 3 #define _CACHE_MASK (7<<3) -#else +#elif defined(CONFIG_USE_RI_XI_PAGE_BITS) + +/* + * When using the RI/XI bit support, we have 14 bits of flags below + * the physical address. The RI/XI bits are places such that a SRL 6 + * can strip off the software bits, then a ROTR 2 can move the RI/XI + * into bits [63:62]. This also limits physical address to 56 bits, + * which is more than we need right now. Octeon CSRs use 48 bits. + */ +#define _PAGE_PRESENT (1<<0) /* implemented in software */ +#define _PAGE_WRITE (1<<2) /* implemented in software */ +#define _PAGE_ACCESSED (1<<3) /* implemented in software */ +#define _PAGE_MODIFIED (1<<4) /* implemented in software */ +#define _PAGE_FILE (1<<4) /* set:pagecache unset:swap */ +#define _PAGE_HUGE (1<<5) /* huge tlb page */ +#define _PAGE_NO_EXEC (1<<6) /* Page cannot be executed */ +#define _PAGE_NO_READ (1<<7) /* Page cannot be read */ +#define _PAGE_GLOBAL (1<<8) +#define _PAGE_VALID (1<<9) +#define _PAGE_SILENT_READ (1<<9) /* synonym */ +#define _PAGE_DIRTY (1<<10) /* The MIPS dirty bit */ +#define _PAGE_SILENT_WRITE (1<<10) +#define _CACHE_SHIFT 11 +#define _CACHE_MASK (7<<_CACHE_SHIFT) + +#ifndef __ASSEMBLY__ +/* + * pte_to_entrylo converts a page table entry (PTE) into a Mips + * entrylo0/1 value. + */ +static inline uint64_t pte_to_entrylo(unsigned long pte_val) +{ + /* + * C has no way to express that this is a DSRL 6 followed by a + * ROTR 2. Luckily in the fast path this is done in + * assembly + */ + return (pte_val >> 8) | ((pte_val & (_PAGE_NO_EXEC | _PAGE_NO_READ)) << 56); +} +#endif + +#else /* !CONFIG_USE_RI_XI_PAGE_BITS */ #define _PAGE_PRESENT (1<<0) /* implemented in software */ #define _PAGE_READ (1<<1) /* implemented in software */ @@ -82,6 +123,18 @@ #define _CACHE_MASK (7<<9) #endif + +#ifndef __ASSEMBLY__ +/* + * pte_to_entrylo converts a page table entry (PTE) into a Mips + * entrylo0/1 value. + */ +static inline uint64_t pte_to_entrylo(unsigned long pte_val) +{ + return pte_val >> 6; +} +#endif + #endif /* defined(CONFIG_64BIT_PHYS_ADDR && defined(CONFIG_CPU_MIPS32) */ @@ -130,7 +183,11 @@ #endif +#ifdef _PAGE_NO_READ +#define __READABLE (_PAGE_SILENT_READ | _PAGE_ACCESSED) +#else #define __READABLE (_PAGE_READ | _PAGE_SILENT_READ | _PAGE_ACCESSED) +#endif #define __WRITEABLE (_PAGE_WRITE | _PAGE_SILENT_WRITE | _PAGE_MODIFIED) #define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_MODIFIED | _CACHE_MASK) diff --git a/arch/mips/include/asm/pgtable.h b/arch/mips/include/asm/pgtable.h index 02335fd..9c2e5c9 100644 --- a/arch/mips/include/asm/pgtable.h +++ b/arch/mips/include/asm/pgtable.h @@ -21,6 +21,31 @@ struct mm_struct; struct vm_area_struct; +#ifdef _PAGE_NO_READ +#define PAGE_BASE_FLAGS (_PAGE_PRESENT | _page_cachable_default) +#define PAGE_NONE __pgprot(_PAGE_PRESENT | _CACHE_CACHABLE_NONCOHERENT) +#define PAGE_SHARED __pgprot(PAGE_BASE_FLAGS | _PAGE_WRITE) +#define PAGE_COPY __pgprot(PAGE_BASE_FLAGS | _PAGE_NO_EXEC) +#define PAGE_READONLY __pgprot(PAGE_BASE_FLAGS) +#define PAGE_KERNEL __pgprot(PAGE_BASE_FLAGS | __READABLE | __WRITEABLE | _PAGE_GLOBAL) +#define __P000 __pgprot(_PAGE_PRESENT | _PAGE_NO_EXEC | _PAGE_NO_READ) +#define __P001 __pgprot(_PAGE_PRESENT | _PAGE_NO_EXEC) +#define __P010 __pgprot(_PAGE_PRESENT | _PAGE_NO_EXEC | _PAGE_NO_READ) +#define __P011 __pgprot(_PAGE_PRESENT | _PAGE_NO_EXEC) +#define __P100 __pgprot(_PAGE_PRESENT | _PAGE_NO_READ) +#define __P101 __pgprot(_PAGE_PRESENT) +#define __P110 __pgprot(_PAGE_PRESENT | _PAGE_NO_READ) +#define __P111 __pgprot(_PAGE_PRESENT) + +#define __S000 __pgprot(_PAGE_PRESENT | _PAGE_NO_EXEC | _PAGE_NO_READ) +#define __S001 __pgprot(_PAGE_PRESENT | _PAGE_NO_EXEC) +#define __S010 __pgprot(_PAGE_PRESENT | _PAGE_NO_EXEC | _PAGE_WRITE | _PAGE_NO_READ) +#define __S011 __pgprot(_PAGE_PRESENT | _PAGE_NO_EXEC | _PAGE_WRITE) +#define __S100 __pgprot(_PAGE_PRESENT | _PAGE_NO_READ) +#define __S101 __pgprot(_PAGE_PRESENT) +#define __S110 __pgprot(_PAGE_PRESENT | _PAGE_WRITE | _PAGE_NO_READ) +#define __S111 __pgprot(_PAGE_PRESENT | _PAGE_WRITE) +#else #define PAGE_NONE __pgprot(_PAGE_PRESENT | _CACHE_CACHABLE_NONCOHERENT) #define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ _page_cachable_default) @@ -36,9 +61,10 @@ struct vm_area_struct; __WRITEABLE | _PAGE_GLOBAL | _CACHE_UNCACHED) /* - * MIPS can't do page protection for execute, and considers that the same like - * read. Also, write permissions imply read permissions. This is the closest - * we can get by reasonable means.. + * If _PAGE_NO_EXEC is not defined, we can't do page protection for + * execute, and consider it to be the same as read. Also, write + * permissions imply read permissions. This is the closest we can get + * by reasonable means.. */ /* @@ -63,6 +89,8 @@ struct vm_area_struct; #define __S110 __pgprot(0) #define __S111 __pgprot(0) +#endif + extern unsigned long _page_cachable_default; /* @@ -298,8 +326,13 @@ static inline pte_t pte_mkdirty(pte_t pte) static inline pte_t pte_mkyoung(pte_t pte) { pte_val(pte) |= _PAGE_ACCESSED; +#ifdef _PAGE_NO_READ + if (!(pte_val(pte) & _PAGE_NO_READ)) + pte_val(pte) |= _PAGE_SILENT_READ; +#else if (pte_val(pte) & _PAGE_READ) pte_val(pte) |= _PAGE_SILENT_READ; +#endif return pte; } diff --git a/arch/mips/mm/cache.c b/arch/mips/mm/cache.c index e716caf..31d7f0f 100644 --- a/arch/mips/mm/cache.c +++ b/arch/mips/mm/cache.c @@ -137,6 +137,16 @@ EXPORT_SYMBOL_GPL(_page_cachable_default); static inline void setup_protection_map(void) { +#ifdef _PAGE_NO_READ + /* + * It was statically initialized with everything but the + * _page_cachable_default bits. + */ + int i; + for (i = 0; i < 16; i++) + protection_map[i] = __pgprot(pgprot_val(protection_map[i]) | + _page_cachable_default); +#else protection_map[0] = PAGE_NONE; protection_map[1] = PAGE_READONLY; protection_map[2] = PAGE_COPY; @@ -153,6 +163,7 @@ static inline void setup_protection_map(void) protection_map[13] = PAGE_READONLY; protection_map[14] = PAGE_SHARED; protection_map[15] = PAGE_SHARED; +#endif } void __cpuinit cpu_cache_init(void) diff --git a/arch/mips/mm/fault.c b/arch/mips/mm/fault.c index e97a7a2..24990be 100644 --- a/arch/mips/mm/fault.c +++ b/arch/mips/mm/fault.c @@ -99,8 +99,31 @@ good_area: if (!(vma->vm_flags & VM_WRITE)) goto bad_area; } else { +#ifdef _PAGE_NO_READ + if (address == regs->cp0_epc && !(vma->vm_flags & VM_EXEC)) { +#if 0 + pr_notice("Cpu%d[%s:%d:%0*lx:%ld:%0*lx] XI violation\n", + raw_smp_processor_id(), + current->comm, current->pid, + field, address, write, + field, regs->cp0_epc); +#endif + goto bad_area; + } + if (!(vma->vm_flags & VM_READ)) { +#if 0 + pr_notice("Cpu%d[%s:%d:%0*lx:%ld:%0*lx] RI violation\n", + raw_smp_processor_id(), + current->comm, current->pid, + field, address, write, + field, regs->cp0_epc); +#endif + goto bad_area; + } +#else if (!(vma->vm_flags & (VM_READ | VM_WRITE | VM_EXEC))) goto bad_area; +#endif } /* diff --git a/arch/mips/mm/init.c b/arch/mips/mm/init.c index 3c5b7de..9a8e9f1 100644 --- a/arch/mips/mm/init.c +++ b/arch/mips/mm/init.c @@ -143,7 +143,7 @@ void *kmap_coherent(struct page *page, unsigned long addr) #if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) entrylo = pte.pte_high; #else - entrylo = pte_val(pte) >> 6; + entrylo = pte_to_entrylo(pte.pte); #endif ENTER_CRITICAL(flags); diff --git a/arch/mips/mm/tlb-r4k.c b/arch/mips/mm/tlb-r4k.c index e551559..c9ae7a8 100644 --- a/arch/mips/mm/tlb-r4k.c +++ b/arch/mips/mm/tlb-r4k.c @@ -303,7 +303,7 @@ void __update_tlb(struct vm_area_struct * vma, unsigned long address, pte_t pte) unsigned long lo; write_c0_pagemask(PM_HUGE_MASK); ptep = (pte_t *)pmdp; - lo = pte_val(*ptep) >> 6; + lo = pte_to_entrylo(pte_val(*ptep)); write_c0_entrylo0(lo); write_c0_entrylo1(lo + (HPAGE_SIZE >> 7)); @@ -323,8 +323,8 @@ void __update_tlb(struct vm_area_struct * vma, unsigned long address, pte_t pte) ptep++; write_c0_entrylo1(ptep->pte_high); #else - write_c0_entrylo0(pte_val(*ptep++) >> 6); - write_c0_entrylo1(pte_val(*ptep) >> 6); + write_c0_entrylo0(pte_to_entrylo(pte_val(*ptep++))); + write_c0_entrylo1(pte_to_entrylo(pte_val(*ptep))); #endif mtc0_tlbw_hazard(); if (idx < 0) @@ -439,6 +439,15 @@ void __cpuinit tlb_init(void) current_cpu_type() == CPU_R12000 || current_cpu_type() == CPU_R14000) write_c0_framemask(0); + +#ifdef _PAGE_NO_READ + /* + * Enable the no read, no exec bits, and enable large virtual + * address. + */ + write_c0_pagegrain(PG_RIE | PG_XIE | PG_ELPA); +#endif + temp_tlb_entry = current_cpu_data.tlbsize - 1; /* From this point on the ARC firmware is dead. */ diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index 35431e1..3ee26aa 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -76,6 +76,8 @@ enum label_id { label_vmalloc_done, label_tlbw_hazard, label_split, + label_tlbl_goaround1, + label_tlbl_goaround2, label_nopage_tlbl, label_nopage_tlbs, label_nopage_tlbm, @@ -92,6 +94,8 @@ UASM_L_LA(_vmalloc) UASM_L_LA(_vmalloc_done) UASM_L_LA(_tlbw_hazard) UASM_L_LA(_split) +UASM_L_LA(_tlbl_goaround1) +UASM_L_LA(_tlbl_goaround2) UASM_L_LA(_nopage_tlbl) UASM_L_LA(_nopage_tlbs) UASM_L_LA(_nopage_tlbm) @@ -397,6 +401,28 @@ static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l, } #ifdef CONFIG_HUGETLB_PAGE + +static __cpuinit void build_restore_pagemask(u32 **p, + struct uasm_reloc **r, + unsigned int tmp, + enum label_id lid) +{ + /* Reset default page size */ + if (PM_DEFAULT_MASK >> 16) { + uasm_i_lui(p, tmp, PM_DEFAULT_MASK >> 16); + uasm_i_ori(p, tmp, tmp, PM_DEFAULT_MASK & 0xffff); + uasm_il_b(p, r, lid); + uasm_i_mtc0(p, tmp, C0_PAGEMASK); + } else if (PM_DEFAULT_MASK) { + uasm_i_ori(p, tmp, 0, PM_DEFAULT_MASK); + uasm_il_b(p, r, lid); + uasm_i_mtc0(p, tmp, C0_PAGEMASK); + } else { + uasm_il_b(p, r, lid); + uasm_i_mtc0(p, 0, C0_PAGEMASK); + } +} + static __cpuinit void build_huge_tlb_write_entry(u32 **p, struct uasm_label **l, struct uasm_reloc **r, @@ -410,20 +436,7 @@ static __cpuinit void build_huge_tlb_write_entry(u32 **p, build_tlb_write_entry(p, l, r, wmode); - /* Reset default page size */ - if (PM_DEFAULT_MASK >> 16) { - uasm_i_lui(p, tmp, PM_DEFAULT_MASK >> 16); - uasm_i_ori(p, tmp, tmp, PM_DEFAULT_MASK & 0xffff); - uasm_il_b(p, r, label_leave); - uasm_i_mtc0(p, tmp, C0_PAGEMASK); - } else if (PM_DEFAULT_MASK) { - uasm_i_ori(p, tmp, 0, PM_DEFAULT_MASK); - uasm_il_b(p, r, label_leave); - uasm_i_mtc0(p, tmp, C0_PAGEMASK); - } else { - uasm_il_b(p, r, label_leave); - uasm_i_mtc0(p, 0, C0_PAGEMASK); - } + build_restore_pagemask(p, r, tmp, label_leave); } /* @@ -459,7 +472,7 @@ static __cpuinit void build_huge_update_entries(u32 **p, if (!small_sequence) uasm_i_lui(p, tmp, HPAGE_SIZE >> (7 + 16)); - UASM_i_SRL(p, pte, pte, 6); /* convert to entrylo */ + build_convert_pte_to_entrylo(p, pte); UASM_i_MTC0(p, pte, C0_ENTRYLO0); /* load it */ /* convert to entrylo1 */ if (small_sequence) @@ -674,6 +687,19 @@ static void __cpuinit build_get_ptep(u32 **p, unsigned int tmp, unsigned int ptr UASM_i_ADDU(p, ptr, ptr, tmp); /* add in offset */ } +static __cpuinit __maybe_unused void build_convert_pte_to_entrylo(u32 **p, + unsigned int reg) +{ +#ifdef _PAGE_NO_READ + uasm_i_dsrl(p, reg, reg, ilog2(_PAGE_NO_EXEC)); + uasm_i_drotr(p, reg, reg, ilog2(_PAGE_GLOBAL) - ilog2(_PAGE_NO_EXEC)); +#elif defined(CONFIG_64BIT_PHYS_ADDR) + uasm_i_dsrl(p, reg, reg, 6); +#else + uasm_i_SRL(p, reg, reg, 6); +#endif +} + static void __cpuinit build_update_entries(u32 **p, unsigned int tmp, unsigned int ptep) { @@ -685,9 +711,17 @@ static void __cpuinit build_update_entries(u32 **p, unsigned int tmp, if (cpu_has_64bits) { uasm_i_ld(p, tmp, 0, ptep); /* get even pte */ uasm_i_ld(p, ptep, sizeof(pte_t), ptep); /* get odd pte */ +#ifdef _PAGE_NO_READ + uasm_i_dsrl(p, tmp, tmp, ilog2(_PAGE_NO_EXEC)); + uasm_i_dsrl(p, ptep, ptep, ilog2(_PAGE_NO_EXEC)); + uasm_i_drotr(p, tmp, tmp, ilog2(_PAGE_GLOBAL) - ilog2(_PAGE_NO_EXEC)); + UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */ + uasm_i_drotr(p, ptep, ptep, ilog2(_PAGE_GLOBAL) - ilog2(_PAGE_NO_EXEC)); +#else uasm_i_dsrl(p, tmp, tmp, 6); /* convert to entrylo0 */ UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */ uasm_i_dsrl(p, ptep, ptep, 6); /* convert to entrylo1 */ +#endif UASM_i_MTC0(p, ptep, C0_ENTRYLO1); /* load it */ } else { int pte_off_even = sizeof(pte_t) / 2; @@ -704,6 +738,15 @@ static void __cpuinit build_update_entries(u32 **p, unsigned int tmp, UASM_i_LW(p, ptep, sizeof(pte_t), ptep); /* get odd pte */ if (r45k_bvahwbug()) build_tlb_probe_entry(p); +#ifdef _PAGE_NO_READ + uasm_i_dsrl(p, tmp, tmp, ilog2(_PAGE_NO_EXEC)); + uasm_i_dsrl(p, ptep, ptep, ilog2(_PAGE_NO_EXEC)); + uasm_i_drotr(p, tmp, tmp, ilog2(_PAGE_GLOBAL) - ilog2(_PAGE_NO_EXEC)); + if (r4k_250MHZhwbug()) + UASM_i_MTC0(p, 0, C0_ENTRYLO0); + UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */ + uasm_i_drotr(p, ptep, ptep, ilog2(_PAGE_GLOBAL) - ilog2(_PAGE_NO_EXEC)); +#else UASM_i_SRL(p, tmp, tmp, 6); /* convert to entrylo0 */ if (r4k_250MHZhwbug()) UASM_i_MTC0(p, 0, C0_ENTRYLO0); @@ -711,6 +754,7 @@ static void __cpuinit build_update_entries(u32 **p, unsigned int tmp, UASM_i_SRL(p, ptep, ptep, 6); /* convert to entrylo1 */ if (r45k_bvahwbug()) uasm_i_mfc0(p, tmp, C0_INDEX); +#endif if (r4k_250MHZhwbug()) UASM_i_MTC0(p, 0, C0_ENTRYLO1); UASM_i_MTC0(p, ptep, C0_ENTRYLO1); /* load it */ @@ -989,9 +1033,14 @@ static void __cpuinit build_pte_present(u32 **p, struct uasm_reloc **r, unsigned int pte, unsigned int ptr, enum label_id lid) { +#ifdef _PAGE_NO_READ + uasm_i_andi(p, pte, pte, _PAGE_PRESENT); + uasm_il_beqz(p, r, pte, lid); +#else uasm_i_andi(p, pte, pte, _PAGE_PRESENT | _PAGE_READ); uasm_i_xori(p, pte, pte, _PAGE_PRESENT | _PAGE_READ); uasm_il_bnez(p, r, pte, lid); +#endif iPTE_LW(p, pte, ptr); } @@ -1279,6 +1328,36 @@ static void __cpuinit build_r4000_tlb_load_handler(void) build_pte_present(&p, &r, K0, K1, label_nopage_tlbl); if (m4kc_tlbp_war()) build_tlb_probe_entry(&p); + +#ifdef _PAGE_NO_READ + /* + * If the page is not _PAGE_VALID, RI or XI could not have + * triggered it. Skip the expensive test.. + */ + uasm_i_andi(&p, K0, K0, _PAGE_VALID); + uasm_il_beqz(&p, &r, K0, label_tlbl_goaround1); + + uasm_i_nop(&p); + uasm_i_tlbr(&p); + /* Examine entrylo 0 or 1 based on ptr. */ + uasm_i_andi(&p, K0, K1, sizeof(pte_t)); + uasm_i_beqz(&p, K0, 8); + + UASM_i_MFC0(&p, K0, C0_ENTRYLO0); /* load it in the delay slot*/ + UASM_i_MFC0(&p, K0, C0_ENTRYLO1); /* load it if ptr is odd */ + /* + * If the entryLo (now in K0) is valid (bit 1), RI or XI must + * have triggered it. + */ + uasm_i_andi(&p, K0, K0, 2); + uasm_il_bnez(&p, &r, K0, label_nopage_tlbl); + + + uasm_l_tlbl_goaround1(&l, p); + /* Reload the PTE value */ + iPTE_LW(&p, K0, K1); + +#endif build_make_valid(&p, &r, K0, K1); build_r4000_tlbchange_handler_tail(&p, &l, &r, K0, K1); @@ -1291,6 +1370,42 @@ static void __cpuinit build_r4000_tlb_load_handler(void) iPTE_LW(&p, K0, K1); build_pte_present(&p, &r, K0, K1, label_nopage_tlbl); build_tlb_probe_entry(&p); + +#ifdef _PAGE_NO_READ + /* + * If the page is not _PAGE_VALID, RI or XI could not have + * triggered it. Skip the expensive test.. + */ + uasm_i_andi(&p, K0, K0, _PAGE_VALID); + uasm_il_beqz(&p, &r, K0, label_tlbl_goaround2); + + uasm_i_nop(&p); + uasm_i_tlbr(&p); + /* Examine entrylo 0 or 1 based on ptr. */ + uasm_i_andi(&p, K0, K1, sizeof(pte_t)); + uasm_i_beqz(&p, K0, 8); + + UASM_i_MFC0(&p, K0, C0_ENTRYLO0); /* load it in the delay slot*/ + UASM_i_MFC0(&p, K0, C0_ENTRYLO1); /* load it if ptr is odd */ + /* + * If the entryLo (now in K0) is valid (bit 1), RI or XI must + * have triggered it. + */ + uasm_i_andi(&p, K0, K0, 2); + uasm_il_beqz(&p, &r, K0, label_tlbl_goaround2); + /* Reload the PTE value */ + iPTE_LW(&p, K0, K1); + + /* + * We clobbered C0_PAGEMASK, restore it. On the other branch + * it is restored in build_huge_tlb_write_entry. + */ + build_restore_pagemask(&p, &r, K0, label_nopage_tlbl, 0); + + uasm_l_tlbl_goaround2(&l, p); + +#endif + uasm_i_ori(&p, K0, K0, (_PAGE_ACCESSED | _PAGE_VALID)); build_huge_handler_tail(&p, &r, &l, K0, K1); #endif -- 1.6.0.6 From David.Daney@caviumnetworks.com Sat Feb 6 00:28:49 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 06 Feb 2010 00:28:55 +0100 (CET) Received: from mail3.caviumnetworks.com ([12.108.191.235]:11641 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491032Ab0BEX1i (ORCPT ); Sat, 6 Feb 2010 00:27:38 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Fri, 05 Feb 2010 15:27:43 -0800 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Fri, 5 Feb 2010 15:27:18 -0800 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Fri, 5 Feb 2010 15:27:18 -0800 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.2/8.14.2) with ESMTP id o15NRF20028551; Fri, 5 Feb 2010 15:27:15 -0800 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.2/8.14.2/Submit) id o15NRBN3028550; Fri, 5 Feb 2010 15:27:12 -0800 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: David Daney Subject: [PATCH 1/4] MIPS: Use 64-bit stores to c0_entrylo on 64-bit kernels. Date: Fri, 5 Feb 2010 15:27:08 -0800 Message-Id: <1265412431-28526-1-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.6.0.6 In-Reply-To: <4B6CA90C.1000609@caviumnetworks.com> References: <4B6CA90C.1000609@caviumnetworks.com> X-OriginalArrivalTime: 05 Feb 2010 23:27:18.0059 (UTC) FILETIME=[C1E48FB0:01CAA6BA] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25886 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips 64-bit CPUs have 64-bit c0_entrylo{0,1} registers. We should use the 64-bit dmtc0 instruction to set them. This becomes important if we want to set the RI and XI bits present in some processors. Signed-off-by: David Daney --- arch/mips/mm/tlbex.c | 20 ++++++++++---------- 1 files changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index 2c68849..35431e1 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -460,14 +460,14 @@ static __cpuinit void build_huge_update_entries(u32 **p, uasm_i_lui(p, tmp, HPAGE_SIZE >> (7 + 16)); UASM_i_SRL(p, pte, pte, 6); /* convert to entrylo */ - uasm_i_mtc0(p, pte, C0_ENTRYLO0); /* load it */ + UASM_i_MTC0(p, pte, C0_ENTRYLO0); /* load it */ /* convert to entrylo1 */ if (small_sequence) UASM_i_ADDIU(p, pte, pte, HPAGE_SIZE >> 7); else UASM_i_ADDU(p, pte, pte, tmp); - uasm_i_mtc0(p, pte, C0_ENTRYLO1); /* load it */ + UASM_i_MTC0(p, pte, C0_ENTRYLO1); /* load it */ } static __cpuinit void build_huge_handler_tail(u32 **p, @@ -686,18 +686,18 @@ static void __cpuinit build_update_entries(u32 **p, unsigned int tmp, uasm_i_ld(p, tmp, 0, ptep); /* get even pte */ uasm_i_ld(p, ptep, sizeof(pte_t), ptep); /* get odd pte */ uasm_i_dsrl(p, tmp, tmp, 6); /* convert to entrylo0 */ - uasm_i_mtc0(p, tmp, C0_ENTRYLO0); /* load it */ + UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */ uasm_i_dsrl(p, ptep, ptep, 6); /* convert to entrylo1 */ - uasm_i_mtc0(p, ptep, C0_ENTRYLO1); /* load it */ + UASM_i_MTC0(p, ptep, C0_ENTRYLO1); /* load it */ } else { int pte_off_even = sizeof(pte_t) / 2; int pte_off_odd = pte_off_even + sizeof(pte_t); /* The pte entries are pre-shifted */ uasm_i_lw(p, tmp, pte_off_even, ptep); /* get even pte */ - uasm_i_mtc0(p, tmp, C0_ENTRYLO0); /* load it */ + UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */ uasm_i_lw(p, ptep, pte_off_odd, ptep); /* get odd pte */ - uasm_i_mtc0(p, ptep, C0_ENTRYLO1); /* load it */ + UASM_i_MTC0(p, ptep, C0_ENTRYLO1); /* load it */ } #else UASM_i_LW(p, tmp, 0, ptep); /* get even pte */ @@ -706,14 +706,14 @@ static void __cpuinit build_update_entries(u32 **p, unsigned int tmp, build_tlb_probe_entry(p); UASM_i_SRL(p, tmp, tmp, 6); /* convert to entrylo0 */ if (r4k_250MHZhwbug()) - uasm_i_mtc0(p, 0, C0_ENTRYLO0); - uasm_i_mtc0(p, tmp, C0_ENTRYLO0); /* load it */ + UASM_i_MTC0(p, 0, C0_ENTRYLO0); + UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */ UASM_i_SRL(p, ptep, ptep, 6); /* convert to entrylo1 */ if (r45k_bvahwbug()) uasm_i_mfc0(p, tmp, C0_INDEX); if (r4k_250MHZhwbug()) - uasm_i_mtc0(p, 0, C0_ENTRYLO1); - uasm_i_mtc0(p, ptep, C0_ENTRYLO1); /* load it */ + UASM_i_MTC0(p, 0, C0_ENTRYLO1); + UASM_i_MTC0(p, ptep, C0_ENTRYLO1); /* load it */ #endif } -- 1.6.0.6 From julia@diku.dk Sat Feb 6 09:42:21 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 06 Feb 2010 09:42:28 +0100 (CET) Received: from mgw2.diku.dk ([130.225.96.92]:46503 "EHLO mgw2.diku.dk" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491154Ab0BFImV (ORCPT ); Sat, 6 Feb 2010 09:42:21 +0100 Received: from localhost (localhost [127.0.0.1]) by mgw2.diku.dk (Postfix) with ESMTP id 2566219BBA2; Sat, 6 Feb 2010 09:42:18 +0100 (CET) Received: from mgw2.diku.dk ([127.0.0.1]) by localhost (mgw2.diku.dk [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 07291-12; Sat, 6 Feb 2010 09:42:17 +0100 (CET) Received: from nhugin.diku.dk (nhugin.diku.dk [130.225.96.140]) by mgw2.diku.dk (Postfix) with ESMTP id 0530E19BBC5; Sat, 6 Feb 2010 09:42:17 +0100 (CET) Received: from ask.diku.dk (ask.diku.dk [130.225.96.225]) by nhugin.diku.dk (Postfix) with ESMTP id 31C5E6DF893; Sat, 6 Feb 2010 09:37:14 +0100 (CET) Received: by ask.diku.dk (Postfix, from userid 3767) id E1003200AA; Sat, 6 Feb 2010 09:42:16 +0100 (CET) Received: from localhost (localhost [127.0.0.1]) by ask.diku.dk (Postfix) with ESMTP id D93F1200A9; Sat, 6 Feb 2010 09:42:16 +0100 (CET) Date: Sat, 6 Feb 2010 09:42:16 +0100 (CET) From: Julia Lawall To: Ralf Baechle , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, kernel-janitors@vger.kernel.org Subject: [PATCH 2/11] arch/mips/sni: Correct NULL test Message-ID: MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII X-Virus-Scanned: amavisd-new at diku.dk Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25887 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: julia@diku.dk Precedence: bulk X-list: linux-mips From: Julia Lawall Test the value that was just allocated rather than the previously tested one. A simplified version of the semantic match that finds this problem is as follows: (http://coccinelle.lip6.fr/) // @r@ expression *x; expression e; identifier l; @@ if (x == NULL || ...) { ... when forall return ...; } ... when != goto l; when != x = e when != &x *x == NULL // Signed-off-by: Julia Lawall send --- arch/mips/sni/rm200.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/mips/sni/rm200.c b/arch/mips/sni/rm200.c index 46f0069..31e2583 100644 --- a/arch/mips/sni/rm200.c +++ b/arch/mips/sni/rm200.c @@ -404,7 +404,7 @@ void __init sni_rm200_i8259_irqs(void) if (!rm200_pic_master) return; rm200_pic_slave = ioremap_nocache(0x160000a0, 4); - if (!rm200_pic_master) { + if (!rm200_pic_slave) { iounmap(rm200_pic_master); return; } From tsbogend@alpha.franken.de Sat Feb 6 10:52:32 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 06 Feb 2010 10:52:39 +0100 (CET) Received: from elvis.franken.de ([193.175.24.41]:34695 "EHLO elvis.franken.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491178Ab0BFJwc (ORCPT ); Sat, 6 Feb 2010 10:52:32 +0100 Received: from uucp (helo=solo.franken.de) by elvis.franken.de with local-bsmtp (Exim 3.36 #1) id 1NdhL5-0002Oh-00; Sat, 06 Feb 2010 10:52:31 +0100 Received: by solo.franken.de (Postfix, from userid 1000) id 37976C2C79; Sat, 6 Feb 2010 10:52:18 +0100 (CET) Date: Sat, 6 Feb 2010 10:52:18 +0100 From: Thomas Bogendoerfer To: Julia Lawall Cc: Ralf Baechle , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, kernel-janitors@vger.kernel.org Subject: Re: [PATCH 2/11] arch/mips/sni: Correct NULL test Message-ID: <20100206095218.GA7185@alpha.franken.de> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25888 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: tsbogend@alpha.franken.de Precedence: bulk X-list: linux-mips On Sat, Feb 06, 2010 at 09:42:16AM +0100, Julia Lawall wrote: > From: Julia Lawall > > Test the value that was just allocated rather than the previously tested one. > > A simplified version of the semantic match that finds this problem is as > follows: (http://coccinelle.lip6.fr/) > > // > @r@ > expression *x; > expression e; > identifier l; > @@ > > if (x == NULL || ...) { > ... when forall > return ...; } > ... when != goto l; > when != x = e > when != &x > *x == NULL > // > > Signed-off-by: Julia Lawall > send > --- > arch/mips/sni/rm200.c | 2 +- > 1 files changed, 1 insertions(+), 1 deletions(-) > > diff --git a/arch/mips/sni/rm200.c b/arch/mips/sni/rm200.c > index 46f0069..31e2583 100644 > --- a/arch/mips/sni/rm200.c > +++ b/arch/mips/sni/rm200.c > @@ -404,7 +404,7 @@ void __init sni_rm200_i8259_irqs(void) > if (!rm200_pic_master) > return; > rm200_pic_slave = ioremap_nocache(0x160000a0, 4); > - if (!rm200_pic_master) { > + if (!rm200_pic_slave) { > iounmap(rm200_pic_master); > return; > } Acked-by: Thomas Bogendoerfer Thanks for fixing. Thomas. -- Crap can work. Given enough thrust pigs will fly, but it's not necessary a good idea. [ RFC1925, 2.3 ] From tsbogend@alpha.franken.de Sat Feb 6 13:16:51 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 06 Feb 2010 13:16:54 +0100 (CET) Received: from elvis.franken.de ([193.175.24.41]:37339 "EHLO elvis.franken.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492034Ab0BFMQv (ORCPT ); Sat, 6 Feb 2010 13:16:51 +0100 Received: from uucp (helo=solo.franken.de) by elvis.franken.de with local-bsmtp (Exim 3.36 #1) id 1Ndjak-0005vF-00; Sat, 06 Feb 2010 13:16:50 +0100 Received: by solo.franken.de (Postfix, from userid 1000) id 234DCC2C7A; Sat, 6 Feb 2010 13:16:22 +0100 (CET) Date: Sat, 6 Feb 2010 13:16:22 +0100 From: Thomas Bogendoerfer To: Yoichi Yuasa Cc: Ralf Baechle , linux-mips Subject: Re: [PATCH 1/2] MIPS: add 8250/16550 serial early printk driver Message-ID: <20100206121622.GA8775@alpha.franken.de> References: <20100205232857.eb65967f.yuasa@linux-mips.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20100205232857.eb65967f.yuasa@linux-mips.org> User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25889 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: tsbogend@alpha.franken.de Precedence: bulk X-list: linux-mips On Fri, Feb 05, 2010 at 11:28:57PM +0900, Yoichi Yuasa wrote: > Signed-off-by: Yoichi Yuasa > --- > arch/mips/Kconfig.debug | 8 ++++ > arch/mips/include/asm/setup.h | 9 ++++ > arch/mips/kernel/Makefile | 1 + > arch/mips/kernel/early_printk_8250.c | 68 ++++++++++++++++++++++++++++++++++ > 4 files changed, 86 insertions(+), 0 deletions(-) > create mode 100644 arch/mips/kernel/early_printk_8250.c > > diff --git a/arch/mips/Kconfig.debug b/arch/mips/Kconfig.debug > index 32a010d..f5d739c 100644 > --- a/arch/mips/Kconfig.debug > +++ b/arch/mips/Kconfig.debug > @@ -20,6 +20,14 @@ config EARLY_PRINTK > doesn't cooperate with an X server. You should normally say N here, > unless you want to debug such a crash. > > +config EARLY_PRINTK_8250 > [..] have you looked at drivers/serial/8250_early.c ? It looks like it was invented for some sort of early console on 8250 devices... Thomas. -- Crap can work. Given enough thrust pigs will fly, but it's not necessary a good idea. [ RFC1925, 2.3 ] From elendil@planet.nl Sat Feb 6 18:44:52 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 06 Feb 2010 18:44:59 +0100 (CET) Received: from Cpsmtpm-eml109.kpnxchange.com ([195.121.3.13]:62725 "EHLO CPSMTPM-EML109.kpnxchange.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492026Ab0BFRow (ORCPT ); Sat, 6 Feb 2010 18:44:52 +0100 Received: from aragorn.fjphome.nl ([77.166.180.99]) by CPSMTPM-EML109.kpnxchange.com with Microsoft SMTPSVC(7.0.6001.18000); Sat, 6 Feb 2010 18:44:45 +0100 From: Frans Pop To: linux-kernel@vger.kernel.org Subject: [PATCH 00/16] remove trailing spaces in messages Date: Sat, 6 Feb 2010 18:44:36 +0100 User-Agent: KMail/1.9.9 Cc: Benjamin Herrenschmidt , "David S. Miller" , Fenghua Yu , Helge Deller , Ingo Molnar , Jeff Dike , Jiri Kosina , Kyle McMartin , linux-alpha@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-cris-kernel@axis.com, linux-ia64@vger.kernel.org, linux-m68k@lists.linux-m68k.org, linux-mips@linux-mips.org, linux-parisc@vger.kernel.org, linux-pm@lists.linux-foundation.org, linuxppc-dev@ozlabs.org, linux-s390@vger.kernel.org, Michal Simek , microblaze-uclinux@itee.uq.edu.au, Mike Frysinger , Paul Mackerras , "Rafael J. Wysocki" , Ralf Baechle , Roman Zippel , Russell King , sparclinux@vger.kernel.org, Tony Luck , uclinux-dist-devel@blackfin.uclinux.org, user-mode-linux-devel@lists.sourceforge.net, x86@kernel.org MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Content-Disposition: inline Message-Id: <201002061844.45212.elendil@planet.nl> X-OriginalArrivalTime: 06 Feb 2010 17:44:45.0591 (UTC) FILETIME=[12149270:01CAA754] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25890 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: elendil@planet.nl Precedence: bulk X-list: linux-mips This is a first series of patches to remove trailing spaces in messages. Patches cover arch-specific code plus one fix for PM and one in Documentation. Depending on how this series is received I'll continue with other parts of the kernel. Benefits are: - general cleanup and consistency - minor reduction in kernel size and user's log file size - reduced annoyance for people writing logcheck rules The patch for m68k has been rebased against linux-next; all other patches apply against both mainline and -next (as of 5-2). Shortstat: 74 files changed, 135 insertions(+), 136 deletions(-) Frans Pop (16): alpha: remove trailing spaces in messages arm: remove trailing spaces in messages ia64: remove trailing space in messages m68k: remove trailing space in messages microblaze: remove trailing space in messages mips: remove trailing space in messages parisc: remove trailing space in messages s390: remove trailing space in messages sparc: remove trailing space in messages x86: remove trailing space in messages blackfin: remove trailing space in messages cris/trivial: remove trailing space in message powerpc: remove trailing space in messages um: remove trailing space in messages PM: remove trailing space in message trivial: remove trailing space in spidev test program From elendil@planet.nl Sat Feb 6 18:47:29 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 06 Feb 2010 18:47:34 +0100 (CET) Received: from cpsmtpm-eml101.kpnxchange.com ([195.121.3.5]:53183 "EHLO CPSMTPM-EML101.kpnxchange.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492067Ab0BFRr3 (ORCPT ); Sat, 6 Feb 2010 18:47:29 +0100 Received: from elrond.fjphome.nl ([77.166.180.99]) by CPSMTPM-EML101.kpnxchange.com with Microsoft SMTPSVC(7.0.6001.18000); Sat, 6 Feb 2010 18:47:25 +0100 Received: from aragorn.fjphome.nl ([10.19.66.13]) by elrond.fjphome.nl with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.69) (envelope-from ) id 1Ndokf-0000X0-11; Sat, 06 Feb 2010 18:47:25 +0100 Received: from fjp by aragorn.fjphome.nl with local (Exim 4.69) (envelope-from ) id 1Ndoke-00085x-AY; Sat, 06 Feb 2010 18:47:24 +0100 From: Frans Pop To: linux-kernel@vger.kernel.org Cc: Frans Pop , linux-mips@linux-mips.org, Ralf Baechle Subject: [PATCH 06/16] mips: remove trailing space in messages Date: Sat, 6 Feb 2010 18:47:13 +0100 Message-Id: <1265478443-31072-6-git-send-email-elendil@planet.nl> X-Mailer: git-send-email 1.6.6.1 In-Reply-To: <201002061844.45212.elendil@planet.nl> References: <201002061844.45212.elendil@planet.nl> X-OriginalArrivalTime: 06 Feb 2010 17:47:25.0573 (UTC) FILETIME=[716FE350:01CAA754] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25891 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: elendil@planet.nl Precedence: bulk X-list: linux-mips Signed-off-by: Frans Pop Cc: linux-mips@linux-mips.org Cc: Ralf Baechle --- arch/mips/alchemy/common/dbdma.c | 2 +- arch/mips/cavium-octeon/smp.c | 2 +- arch/mips/pmc-sierra/yosemite/atmel_read_eeprom.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/mips/alchemy/common/dbdma.c b/arch/mips/alchemy/common/dbdma.c index 5c68569..4050640 100644 --- a/arch/mips/alchemy/common/dbdma.c +++ b/arch/mips/alchemy/common/dbdma.c @@ -903,7 +903,7 @@ void au1xxx_dbdma_dump(u32 chanid) dtp = ctp->chan_dest; cp = ctp->chan_ptr; - printk(KERN_DEBUG "Chan %x, stp %x (dev %d) dtp %x (dev %d) \n", + printk(KERN_DEBUG "Chan %x, stp %x (dev %d) dtp %x (dev %d)\n", (u32)ctp, (u32)stp, stp - dbdev_tab, (u32)dtp, dtp - dbdev_tab); printk(KERN_DEBUG "desc base %x, get %x, put %x, cur %x\n", diff --git a/arch/mips/cavium-octeon/smp.c b/arch/mips/cavium-octeon/smp.c index c198efd..51e9802 100644 --- a/arch/mips/cavium-octeon/smp.c +++ b/arch/mips/cavium-octeon/smp.c @@ -327,7 +327,7 @@ static void octeon_cpu_die(unsigned int cpu) avail_coremask); } - pr_info("Reset core %d. Available Coremask = %x \n", coreid, + pr_info("Reset core %d. Available Coremask = %x\n", coreid, avail_coremask); cvmx_write_csr(CVMX_CIU_PP_RST, 1 << coreid); cvmx_write_csr(CVMX_CIU_PP_RST, 0); diff --git a/arch/mips/pmc-sierra/yosemite/atmel_read_eeprom.c b/arch/mips/pmc-sierra/yosemite/atmel_read_eeprom.c index fc990cb..d6f8bdf 100644 --- a/arch/mips/pmc-sierra/yosemite/atmel_read_eeprom.c +++ b/arch/mips/pmc-sierra/yosemite/atmel_read_eeprom.c @@ -127,7 +127,7 @@ static int recv_ack(void) if (ack) { do_idle(); - printk(KERN_ERR "Error reading the Atmel 24C32/24C64 EEPROM \n"); + printk(KERN_ERR "Error reading the Atmel 24C32/24C64 EEPROM\n"); return -1; } -- 1.6.6.1 From yuasa.linux@gmail.com Mon Feb 8 00:52:46 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 08 Feb 2010 00:52:51 +0100 (CET) Received: from mail-yw0-f186.google.com ([209.85.211.186]:53625 "EHLO mail-yw0-f186.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491981Ab0BGXwq (ORCPT ); Mon, 8 Feb 2010 00:52:46 +0100 Received: by ywh16 with SMTP id 16so186365ywh.25 for ; Sun, 07 Feb 2010 15:52:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:sender:date:from:to:cc :subject:message-id:in-reply-to:references:x-mailer:mime-version :content-type:content-transfer-encoding; bh=y390IcCrBl2sao1vDD3GLVAtIxPn+PoXa91I3hMdChI=; b=HkIejIxYj1o5tBJIQKvHq0WD1rfene00SQVcjdwMvUzXNrVCnBssfDq3ZKdQokCUZL DrEOUhaw7YFt9cR97GoVMYjOgIyEKoJmqzxYJngt1FgowdpfbTa69p+wZsORmwMXDC1n mtsUqZQqRuTk5d+6XilovxObrJJahFnN2x608= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:date:from:to:cc:subject:message-id:in-reply-to:references :x-mailer:mime-version:content-type:content-transfer-encoding; b=wES0GyyPRJJSFPsPZQwgr67HL7QPbzyNeiTNdbgEcQwKzrZ1zrK4HrD1aDTFuD+8vd AusPenv8Xvnt24iv2wLa4vvp3B8UnnCUUtwbA8jspD5+WL8lhddDlUSw7BoNUG1o/t6b GbqaPJhml5gArhK/IBxQ/dGV8fU4d4qCuNcrg= Received: by 10.101.28.3 with SMTP id f3mr7245445anj.68.1265586759555; Sun, 07 Feb 2010 15:52:39 -0800 (PST) Received: from ypsilon.skybright.jp (sannin29006.nirai.ne.jp [203.160.29.6]) by mx.google.com with ESMTPS id 13sm2482338gxk.5.2010.02.07.15.52.36 (version=TLSv1/SSLv3 cipher=RC4-MD5); Sun, 07 Feb 2010 15:52:38 -0800 (PST) Date: Mon, 8 Feb 2010 08:52:17 +0900 From: Yoichi Yuasa To: Thomas Bogendoerfer Cc: yuasa@linux-mips.org, Ralf Baechle , linux-mips Subject: Re: [PATCH 1/2] MIPS: add 8250/16550 serial early printk driver Message-Id: <20100208085217.ba16b45e.yuasa@linux-mips.org> In-Reply-To: <20100206121622.GA8775@alpha.franken.de> References: <20100205232857.eb65967f.yuasa@linux-mips.org> <20100206121622.GA8775@alpha.franken.de> X-Mailer: Sylpheed 2.7.1 (GTK+ 2.16.6; i686-pc-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25892 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: yuasa@linux-mips.org Precedence: bulk X-list: linux-mips On Sat, 6 Feb 2010 13:16:22 +0100 Thomas Bogendoerfer wrote: > On Fri, Feb 05, 2010 at 11:28:57PM +0900, Yoichi Yuasa wrote: > > Signed-off-by: Yoichi Yuasa > > --- > > arch/mips/Kconfig.debug | 8 ++++ > > arch/mips/include/asm/setup.h | 9 ++++ > > arch/mips/kernel/Makefile | 1 + > > arch/mips/kernel/early_printk_8250.c | 68 ++++++++++++++++++++++++++++++++++ > > 4 files changed, 86 insertions(+), 0 deletions(-) > > create mode 100644 arch/mips/kernel/early_printk_8250.c > > > > diff --git a/arch/mips/Kconfig.debug b/arch/mips/Kconfig.debug > > index 32a010d..f5d739c 100644 > > --- a/arch/mips/Kconfig.debug > > +++ b/arch/mips/Kconfig.debug > > @@ -20,6 +20,14 @@ config EARLY_PRINTK > > doesn't cooperate with an X server. You should normally say N here, > > unless you want to debug such a crash. > > > > +config EARLY_PRINTK_8250 > > [..] > > have you looked at drivers/serial/8250_early.c ? Yes, I have. > It looks like it > was invented for some sort of early console on 8250 devices... The early printk is registered at the early boot stage(in setup_arch()). Yoichi From sshtylyov@mvista.com Mon Feb 8 10:58:56 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 08 Feb 2010 10:59:01 +0100 (CET) Received: from [209.85.219.212] ([209.85.219.212]:57977 "EHLO mail-ew0-f212.google.com" rhost-flags-FAIL-FAIL-OK-OK) by eddie.linux-mips.org with ESMTP id S1491107Ab0BHJ64 (ORCPT ); Mon, 8 Feb 2010 10:58:56 +0100 Received: by ewy4 with SMTP id 4so835782ewy.27 for ; Mon, 08 Feb 2010 01:58:34 -0800 (PST) Received: by 10.213.100.229 with SMTP id z37mr3617046ebn.28.1265623114462; Mon, 08 Feb 2010 01:58:34 -0800 (PST) Received: from ?192.168.2.2? (ppp91-77-214-141.pppoe.mtu-net.ru [91.77.214.141]) by mx.google.com with ESMTPS id 13sm2937095ewy.13.2010.02.08.01.58.33 (version=TLSv1/SSLv3 cipher=RC4-MD5); Mon, 08 Feb 2010 01:58:33 -0800 (PST) Message-ID: <4B6FE030.1080708@ru.mvista.com> Date: Mon, 08 Feb 2010 12:58:08 +0300 From: Sergei Shtylyov User-Agent: Thunderbird 2.0.0.23 (Windows/20090812) MIME-Version: 1.0 To: Yoichi Yuasa CC: Ralf Baechle , linux-mips Subject: Re: [PATCH 1/2] MIPS: add 8250/16550 serial early printk driver References: <20100205232857.eb65967f.yuasa@linux-mips.org> In-Reply-To: <20100205232857.eb65967f.yuasa@linux-mips.org> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25893 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sshtylyov@mvista.com Precedence: bulk X-list: linux-mips Hello. Yoichi Yuasa wrote: > Signed-off-by: Yoichi Yuasa > [...] > diff --git a/arch/mips/Kconfig.debug b/arch/mips/Kconfig.debug > index 32a010d..f5d739c 100644 > --- a/arch/mips/Kconfig.debug > +++ b/arch/mips/Kconfig.debug > @@ -20,6 +20,14 @@ config EARLY_PRINTK > doesn't cooperate with an X server. You should normally say N here, > unless you want to debug such a crash. > > +config EARLY_PRINTK_8250 > + bool "8250/16550 and compatible serial early printk driver" > + depends on EARLY_PRINTK > + default n > + help > + If you say Y here, it will be possible to use a 8250/16550 serial > + port as the boot console. > + > Tab not needed here. > diff --git a/arch/mips/include/asm/setup.h b/arch/mips/include/asm/setup.h > index 50511aa..7395b7f 100644 > --- a/arch/mips/include/asm/setup.h > +++ b/arch/mips/include/asm/setup.h > @@ -5,6 +5,15 @@ > > #ifdef __KERNEL__ > extern void setup_early_printk(void); > + > +#ifdef CONFIG_EARLY_PRINTK_8250 > +extern void setup_8250_early_printk_port(unsigned long base, > + unsigned int reg_shift, unsigned int timeout); > +#else > +static inline void setup_8250_early_printk_port(unsigned long base, > + unsigned int reg_shift, unsigned int timeout) {} > +#endif > + > #endif /* __KERNEL__ */ > > #endif /* __SETUP_H */ > diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile > index 9326af5..03fc037 100644 > --- a/arch/mips/kernel/Makefile > +++ b/arch/mips/kernel/Makefile > @@ -93,6 +93,7 @@ obj-$(CONFIG_GPIO_TXX9) += gpio_txx9.o > > obj-$(CONFIG_KEXEC) += machine_kexec.o relocate_kernel.o > obj-$(CONFIG_EARLY_PRINTK) += early_printk.o > +obj-$(CONFIG_EARLY_PRINTK_8250) += early_printk_8250.o > > CFLAGS_cpu-bugs64.o = $(shell if $(CC) $(KBUILD_CFLAGS) -Wa,-mdaddi -c -o /dev/null -xc /dev/null >/dev/null 2>&1; then echo "-DHAVE_AS_SET_DADDI"; fi) > > diff --git a/arch/mips/kernel/early_printk_8250.c b/arch/mips/kernel/early_printk_8250.c > new file mode 100644 > index 0000000..6faf8fd > --- /dev/null > +++ b/arch/mips/kernel/early_printk_8250.c > @@ -0,0 +1,68 @@ > +/* > + * 8250/16550-type serial ports prom_putchar() > + * > + * Copyright (C) 2010 Yoichi Yuasa > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, write to the Free Software > + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA > + */ > +#include > +#include > +#include > + > +static unsigned long serial8250_base; > +static unsigned int serial8250_reg_shift; > +static unsigned int serial8250_tx_timeout; > + > +void setup_8250_early_printk_port(unsigned long base, unsigned int reg_shift, > + unsigned int timeout) > +{ > + serial8250_base = base; > Why not declare 'serial8250_base' as 'void __iomem *' and only cast once, here? WBR, Sergei From sshtylyov@mvista.com Mon Feb 8 11:58:50 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 08 Feb 2010 11:58:57 +0100 (CET) Received: from mail-ew0-f212.google.com ([209.85.219.212]:33309 "EHLO mail-ew0-f212.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491776Ab0BHK6u (ORCPT ); Mon, 8 Feb 2010 11:58:50 +0100 Received: by ewy4 with SMTP id 4so885319ewy.27 for ; Mon, 08 Feb 2010 02:58:43 -0800 (PST) Received: by 10.213.109.129 with SMTP id j1mr5276607ebp.79.1265626723326; Mon, 08 Feb 2010 02:58:43 -0800 (PST) Received: from ?192.168.2.2? (ppp91-77-214-141.pppoe.mtu-net.ru [91.77.214.141]) by mx.google.com with ESMTPS id 16sm2976222ewy.10.2010.02.08.02.58.41 (version=TLSv1/SSLv3 cipher=RC4-MD5); Mon, 08 Feb 2010 02:58:42 -0800 (PST) Message-ID: <4B6FEE4A.6090504@ru.mvista.com> Date: Mon, 08 Feb 2010 13:58:18 +0300 From: Sergei Shtylyov User-Agent: Thunderbird 2.0.0.23 (Windows/20090812) MIME-Version: 1.0 To: David Daney CC: linux-mips@linux-mips.org, ralf@linux-mips.org Subject: Re: [PATCH 3/4] MIPS: Add TLBP to uasm. References: <4B6CA90C.1000609@caviumnetworks.com> <1265412431-28526-3-git-send-email-ddaney@caviumnetworks.com> In-Reply-To: <1265412431-28526-3-git-send-email-ddaney@caviumnetworks.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25894 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sshtylyov@mvista.com Precedence: bulk X-list: linux-mips Hello. David Daney wrote: > The soon to follow Read Inhibit/eXecute Inhibit patch needs TLBP > But you're adding TLBR support, not TLBP? > support in uasm. > > Signed-off-by: David Daney > --- > arch/mips/include/asm/uasm.h | 1 + > arch/mips/mm/uasm.c | 5 ++++- > 2 files changed, 5 insertions(+), 1 deletions(-) > > diff --git a/arch/mips/include/asm/uasm.h b/arch/mips/include/asm/uasm.h > index 3d153ed..b18588b 100644 > --- a/arch/mips/include/asm/uasm.h > +++ b/arch/mips/include/asm/uasm.h > @@ -95,6 +95,7 @@ Ip_u2u1u3(_srl); > Ip_u3u1u2(_subu); > Ip_u2s3u1(_sw); > Ip_0(_tlbp); > +Ip_0(_tlbr); > Ip_0(_tlbwi); > Ip_0(_tlbwr); > Ip_u3u1u2(_xor); > diff --git a/arch/mips/mm/uasm.c b/arch/mips/mm/uasm.c > index e3ca0f7..8f4f14d 100644 > --- a/arch/mips/mm/uasm.c > +++ b/arch/mips/mm/uasm.c > @@ -63,7 +63,8 @@ enum opcode { > insn_jr, insn_ld, insn_ll, insn_lld, insn_lui, insn_lw, insn_mfc0, > insn_mtc0, insn_ori, insn_pref, insn_rfe, insn_sc, insn_scd, > insn_sd, insn_sll, insn_sra, insn_srl, insn_subu, insn_sw, > - insn_tlbp, insn_tlbwi, insn_tlbwr, insn_xor, insn_xori, insn_dins > + insn_tlbp, insn_tlbr, insn_tlbwi, insn_tlbwr, insn_xor, insn_xori, > + insn_dins > }; > > struct insn { > @@ -128,6 +129,7 @@ static struct insn insn_table[] __cpuinitdata = { > { insn_subu, M(spec_op, 0, 0, 0, 0, subu_op), RS | RT | RD }, > { insn_sw, M(sw_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, > { insn_tlbp, M(cop0_op, cop_op, 0, 0, 0, tlbp_op), 0 }, > + { insn_tlbr, M(cop0_op, cop_op, 0, 0, 0, tlbr_op), 0 }, > { insn_tlbwi, M(cop0_op, cop_op, 0, 0, 0, tlbwi_op), 0 }, > { insn_tlbwr, M(cop0_op, cop_op, 0, 0, 0, tlbwr_op), 0 }, > { insn_xor, M(spec_op, 0, 0, 0, 0, xor_op), RS | RT | RD }, > @@ -381,6 +383,7 @@ I_u2u1u3(_srl) > I_u3u1u2(_subu) > I_u2s3u1(_sw) > I_0(_tlbp) > +I_0(_tlbr) > I_0(_tlbwi) > I_0(_tlbwr) > I_u3u1u2(_xor) > WBR, Sergei From yuasa.linux@gmail.com Mon Feb 8 12:54:35 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 08 Feb 2010 12:54:38 +0100 (CET) Received: from mail-yw0-f186.google.com ([209.85.211.186]:63929 "EHLO mail-yw0-f186.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491821Ab0BHLyf (ORCPT ); Mon, 8 Feb 2010 12:54:35 +0100 Received: by ywh16 with SMTP id 16so518917ywh.25 for ; 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Mon, 08 Feb 2010 03:54:27 -0800 (PST) Date: Mon, 8 Feb 2010 20:54:07 +0900 From: Yoichi Yuasa To: Sergei Shtylyov Cc: yuasa@linux-mips.org, Ralf Baechle , linux-mips Subject: Re: [PATCH 1/2] MIPS: add 8250/16550 serial early printk driver Message-Id: <20100208205407.cdaa3f21.yuasa@linux-mips.org> In-Reply-To: <4B6FE030.1080708@ru.mvista.com> References: <20100205232857.eb65967f.yuasa@linux-mips.org> <4B6FE030.1080708@ru.mvista.com> X-Mailer: Sylpheed 2.7.1 (GTK+ 2.16.6; i686-pc-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25895 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: yuasa@linux-mips.org Precedence: bulk X-list: linux-mips Hello Sergei, On Mon, 08 Feb 2010 12:58:08 +0300 Sergei Shtylyov wrote: > Hello. > > Yoichi Yuasa wrote: > > > Signed-off-by: Yoichi Yuasa > > > [...] > > +config EARLY_PRINTK_8250 > > + bool "8250/16550 and compatible serial early printk driver" > > + depends on EARLY_PRINTK > > + default n > > + help > > + If you say Y here, it will be possible to use a 8250/16550 serial > > + port as the boot console. > > + > > > > Tab not needed here. thanks > > diff --git a/arch/mips/kernel/early_printk_8250.c b/arch/mips/kernel/early_printk_8250.c > > new file mode 100644 > > index 0000000..6faf8fd > > --- /dev/null > > +++ b/arch/mips/kernel/early_printk_8250.c [...] > > +static unsigned long serial8250_base; > > +static unsigned int serial8250_reg_shift; > > +static unsigned int serial8250_tx_timeout; > > + > > +void setup_8250_early_printk_port(unsigned long base, unsigned int reg_shift, > > + unsigned int timeout) > > +{ > > + serial8250_base = base; > > > > Why not declare 'serial8250_base' as 'void __iomem *' and only cast > once, here? You're right. I'll update it. Thanks, Yoichi From yuasa.linux@gmail.com Mon Feb 8 13:02:10 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 08 Feb 2010 13:02:15 +0100 (CET) Received: from mail-yw0-f186.google.com ([209.85.211.186]:43699 "EHLO mail-yw0-f186.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491133Ab0BHMCK (ORCPT ); Mon, 8 Feb 2010 13:02:10 +0100 Received: by ywh16 with SMTP id 16so523252ywh.25 for ; Mon, 08 Feb 2010 04:02:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:sender:date:from:to:cc :subject:message-id:x-mailer:mime-version:content-type :content-transfer-encoding; bh=biM2rjen1oz2RAHwA1L78YognwZUQUhj5xoPxnjeLz4=; b=DKidSaLdt7v5hiXbrIwu7UQFmxKcvtUaJ6jXN3M52PRsNo3AHCllXddGVx2pdPVaub iH4CTTV1Nz6QTD9cjzFNxyvePYeEJqeRsrwWj50t2F+FiL2nLLjR4WyU7H22K1wo0MKy +STF1Gn5PoOihjWZC4eQFluOPHb2EMEuRh/Ns= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:date:from:to:cc:subject:message-id:x-mailer:mime-version :content-type:content-transfer-encoding; b=X/yu5To12XwvAg31Jf9eaY5d1LYozW2e73JL93WSPxja5mfjc7DDwCNB9tBE9dTfj5 s7czQGlTj+jszVOzNWEAW1CSH6QZZm6CPa/Kq/Hkp+OMcs+zjFP6L1Yaxac6Bvq3thgh 8YGm7KBIvff3zrfplfFN0Bxrq/bPVgGvRsOEU= Received: by 10.101.119.13 with SMTP id w13mr7901817anm.216.1265630522135; Mon, 08 Feb 2010 04:02:02 -0800 (PST) Received: from ypsilon.skybright.jp (sannin29006.nirai.ne.jp [203.160.29.6]) by mx.google.com with ESMTPS id 15sm2873416gxk.0.2010.02.08.04.01.59 (version=TLSv1/SSLv3 cipher=RC4-MD5); Mon, 08 Feb 2010 04:02:01 -0800 (PST) Date: Mon, 8 Feb 2010 20:59:39 +0900 From: Yoichi Yuasa To: Ralf Baechle Cc: yuasa@linux-mips.org, linux-mips Subject: [PATCH -queue v2 1/2] MIPS: add 8250/16550 serial early printk driver Message-Id: <20100208205939.18497103.yuasa@linux-mips.org> X-Mailer: Sylpheed 2.7.1 (GTK+ 2.16.6; i686-pc-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25896 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: yuasa@linux-mips.org Precedence: bulk X-list: linux-mips Signed-off-by: Yoichi Yuasa --- arch/mips/Kconfig.debug | 8 ++++ arch/mips/include/asm/setup.h | 9 +++++ arch/mips/kernel/Makefile | 1 + arch/mips/kernel/early_printk_8250.c | 66 ++++++++++++++++++++++++++++++++++ 4 files changed, 84 insertions(+), 0 deletions(-) create mode 100644 arch/mips/kernel/early_printk_8250.c diff --git a/arch/mips/Kconfig.debug b/arch/mips/Kconfig.debug index 32a010d..0cceaad 100644 --- a/arch/mips/Kconfig.debug +++ b/arch/mips/Kconfig.debug @@ -20,6 +20,14 @@ config EARLY_PRINTK doesn't cooperate with an X server. You should normally say N here, unless you want to debug such a crash. +config EARLY_PRINTK_8250 + bool "8250/16550 and compatible serial early printk driver" + depends on EARLY_PRINTK + default n + help + If you say Y here, it will be possible to use a 8250/16550 serial + port as the boot console. + config CMDLINE_BOOL bool "Built-in kernel command line" default n diff --git a/arch/mips/include/asm/setup.h b/arch/mips/include/asm/setup.h index 50511aa..7395b7f 100644 --- a/arch/mips/include/asm/setup.h +++ b/arch/mips/include/asm/setup.h @@ -5,6 +5,15 @@ #ifdef __KERNEL__ extern void setup_early_printk(void); + +#ifdef CONFIG_EARLY_PRINTK_8250 +extern void setup_8250_early_printk_port(unsigned long base, + unsigned int reg_shift, unsigned int timeout); +#else +static inline void setup_8250_early_printk_port(unsigned long base, + unsigned int reg_shift, unsigned int timeout) {} +#endif + #endif /* __KERNEL__ */ #endif /* __SETUP_H */ diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile index 9326af5..03fc037 100644 --- a/arch/mips/kernel/Makefile +++ b/arch/mips/kernel/Makefile @@ -93,6 +93,7 @@ obj-$(CONFIG_GPIO_TXX9) += gpio_txx9.o obj-$(CONFIG_KEXEC) += machine_kexec.o relocate_kernel.o obj-$(CONFIG_EARLY_PRINTK) += early_printk.o +obj-$(CONFIG_EARLY_PRINTK_8250) += early_printk_8250.o CFLAGS_cpu-bugs64.o = $(shell if $(CC) $(KBUILD_CFLAGS) -Wa,-mdaddi -c -o /dev/null -xc /dev/null >/dev/null 2>&1; then echo "-DHAVE_AS_SET_DADDI"; fi) diff --git a/arch/mips/kernel/early_printk_8250.c b/arch/mips/kernel/early_printk_8250.c new file mode 100644 index 0000000..83cea37 --- /dev/null +++ b/arch/mips/kernel/early_printk_8250.c @@ -0,0 +1,66 @@ +/* + * 8250/16550-type serial ports prom_putchar() + * + * Copyright (C) 2010 Yoichi Yuasa + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include +#include +#include + +static void __iomem *serial8250_base; +static unsigned int serial8250_reg_shift; +static unsigned int serial8250_tx_timeout; + +void setup_8250_early_printk_port(unsigned long base, unsigned int reg_shift, + unsigned int timeout) +{ + serial8250_base = (void __iomem *)base; + serial8250_reg_shift = reg_shift; + serial8250_tx_timeout = timeout; +} + +static inline u8 serial_in(int offset) +{ + return readb(serial8250_base + (offset << serial8250_reg_shift)); +} + +static inline void serial_out(int offset, char value) +{ + writeb(value, serial8250_base + (offset << serial8250_reg_shift)); +} + +void prom_putchar(char c) +{ + unsigned int timeout; + int status, bits; + + if (!serial8250_base) + return; + + timeout = serial8250_tx_timeout; + bits = UART_LSR_TEMT | UART_LSR_THRE; + + do { + status = serial_in(UART_LSR); + + if (--timeout == 0) + break; + } while ((status & bits) != bits); + + if (timeout) + serial_out(UART_TX, c); +} -- 1.6.6.1 From yuasa.linux@gmail.com Mon Feb 8 13:02:34 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 08 Feb 2010 13:02:39 +0100 (CET) Received: from mail-yw0-f186.google.com ([209.85.211.186]:52095 "EHLO mail-yw0-f186.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491098Ab0BHMCP (ORCPT ); Mon, 8 Feb 2010 13:02:15 +0100 Received: by ywh16 with SMTP id 16so523322ywh.25 for ; Mon, 08 Feb 2010 04:02:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:sender:date:from:to:cc :subject:message-id:in-reply-to:references:x-mailer:mime-version :content-type:content-transfer-encoding; bh=toRsyyfK3NJNbwu0r8axAZVHDTeeSKh5qnVNH6rvKfw=; b=Y0KZOelksMpLQ/1offPLYPvAgcOyzJRQwtJKXjrLI7ocZpZryPp5yx6VFzwREj0d0I C2/V06DAnv8mqcm6Sg9st67t2K8OmKX1iNgjVzmQX5W0AmPRhji9JYZtKrWpiPN8Gajg oLjKpFJN/c82wwwsxkRz3srG+CjaaJuJg0azc= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:date:from:to:cc:subject:message-id:in-reply-to:references :x-mailer:mime-version:content-type:content-transfer-encoding; b=hiiMNQar5e2v1d34EhvCHH+d3/e6J8e+ng6mpB0PFcBTCj6/SPhnCrtUpqVF8ft3Yy iLZxBFXuVG6+wVQyWrItOep/Tnn4bht3KyqE4E89FZL2wCywYDPWLoADPFpxAC20nR5Z PGCqLt/fzsBR0tGVXmKprC/oXpbqB5hhVXYMI= Received: by 10.91.97.14 with SMTP id z14mr444573agl.0.1265630527941; Mon, 08 Feb 2010 04:02:07 -0800 (PST) Received: from ypsilon.skybright.jp (sannin29006.nirai.ne.jp [203.160.29.6]) by mx.google.com with ESMTPS id 16sm2852464gxk.11.2010.02.08.04.02.05 (version=TLSv1/SSLv3 cipher=RC4-MD5); Mon, 08 Feb 2010 04:02:06 -0800 (PST) Date: Mon, 8 Feb 2010 21:01:22 +0900 From: Yoichi Yuasa To: Ralf Baechle Cc: yuasa@linux-mips.org, linux-mips Subject: [PATCH -queue v2 2/2] MIPS: Cobalt move to 8250/16550 serial early printk driver Message-Id: <20100208210122.e9446803.yuasa@linux-mips.org> In-Reply-To: <20100208205939.18497103.yuasa@linux-mips.org> References: <20100208205939.18497103.yuasa@linux-mips.org> X-Mailer: Sylpheed 2.7.1 (GTK+ 2.16.6; i686-pc-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25897 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: yuasa@linux-mips.org Precedence: bulk X-list: linux-mips Signed-off-by: Yoichi Yuasa --- arch/mips/Kconfig | 1 + arch/mips/cobalt/Makefile | 1 - arch/mips/cobalt/console.c | 20 -------------------- arch/mips/cobalt/setup.c | 3 +++ 4 files changed, 4 insertions(+), 21 deletions(-) delete mode 100644 arch/mips/cobalt/console.c diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 591ca0c..b848512 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -90,6 +90,7 @@ config MIPS_COBALT select CSRC_R4K select CEVT_GT641XX select DMA_NONCOHERENT + select EARLY_PRINTK_8250 if EARLY_PRINTK select HW_HAS_PCI select I8253 select I8259 diff --git a/arch/mips/cobalt/Makefile b/arch/mips/cobalt/Makefile index 2379262..5cfe90f 100644 --- a/arch/mips/cobalt/Makefile +++ b/arch/mips/cobalt/Makefile @@ -5,7 +5,6 @@ obj-y := buttons.o irq.o lcd.o led.o reset.o rtc.o serial.o setup.o time.o obj-$(CONFIG_PCI) += pci.o -obj-$(CONFIG_EARLY_PRINTK) += console.o obj-$(CONFIG_MTD_PHYSMAP) += mtd.o EXTRA_CFLAGS += -Werror diff --git a/arch/mips/cobalt/console.c b/arch/mips/cobalt/console.c deleted file mode 100644 index d1ba701..0000000 --- a/arch/mips/cobalt/console.c +++ /dev/null @@ -1,20 +0,0 @@ -/* - * (C) P. Horton 2006 - */ -#include -#include - -#include - -#define UART_BASE ((void __iomem *)CKSEG1ADDR(0x1c800000)) - -void prom_putchar(char c) -{ - if (cobalt_board_id <= COBALT_BRD_ID_QUBE1) - return; - - while (!(readb(UART_BASE + UART_LSR) & UART_LSR_THRE)) - ; - - writeb(c, UART_BASE + UART_TX); -} diff --git a/arch/mips/cobalt/setup.c b/arch/mips/cobalt/setup.c index ec3b2c4..9a8c2fe 100644 --- a/arch/mips/cobalt/setup.c +++ b/arch/mips/cobalt/setup.c @@ -17,6 +17,7 @@ #include #include +#include #include #include @@ -112,6 +113,8 @@ void __init prom_init(void) } add_memory_region(0x0, memsz, BOOT_MEM_RAM); + + setup_8250_early_printk_port(CKSEG1ADDR(0x1c800000), 0, 0); } void __init prom_free_prom_memory(void) -- 1.6.6.1 From ralf@linux-mips.org Mon Feb 8 15:01:53 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 08 Feb 2010 15:01:57 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:55307 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491915Ab0BHOBx (ORCPT ); Mon, 8 Feb 2010 15:01:53 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id o18E2Epv016089; Mon, 8 Feb 2010 15:02:15 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id o18E2E7k016087; Mon, 8 Feb 2010 15:02:14 +0100 Date: Mon, 8 Feb 2010 15:02:14 +0100 From: Ralf Baechle To: Guenter Roeck Cc: linux-mips@linux-mips.org Subject: Re: VMALLOC_END, TASK_SIZE and FIXADDR_START for 64 bit MIPS kernels Message-ID: <20100208140213.GB11334@linux-mips.org> References: <20100203222250.GA21139@ericsson.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20100203222250.GA21139@ericsson.com> User-Agent: Mutt/1.5.20 (2009-08-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25898 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Wed, Feb 03, 2010 at 02:22:50PM -0800, Guenter Roeck wrote: > since it came up during the review of the patch for virtual memory detection > on 64 bit mips kernels, I looked further into making vmalloc_end > a variable and TASK_SIZE dependent on the virtual memory size. > > That turned out to be relatively straightforward, and I have a working patch. > > The one question I still have is about FIXADDR_START. It is currently > set to one of 0xff000000, 0xfffe0000, or (0xff000000 - 0x20000), > depending on the target CPU. > > Quoting from one of the comments during the review, > " ... ensure the value of vmalloc_end is <= FIXADDR_START". > > Obviously that is currently not the case. Is that a concern, or is it good as it is ? Now with allocations potencially happening top-down this is potencially a serious problem. Details would depend on details of platform, processor and kernel configuration. I said vmalloc_end is <= FIXADDR_START" but more accurately we simply need to avoid a conflict between the different virtual address space users. Some CPUs have fixed mappings in their hardware in the KSEG2/KSEG3 range; those mappings can't be overriden by a TLB mapping. To deal with that sort of architectural candy I think a call into the address space allocator for kernel virtual memory is probably nicest thing but something simplier than that would probable have to do for 2.6.34. Ralf From David.Daney@caviumnetworks.com Mon Feb 8 18:20:09 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 08 Feb 2010 18:20:13 +0100 (CET) Received: from mail3.caviumnetworks.com ([12.108.191.235]:3776 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492105Ab0BHRUJ (ORCPT ); Mon, 8 Feb 2010 18:20:09 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Mon, 08 Feb 2010 09:19:57 -0800 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Mon, 8 Feb 2010 09:19:43 -0800 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Mon, 8 Feb 2010 09:19:43 -0800 Message-ID: <4B7047AD.4010206@caviumnetworks.com> Date: Mon, 08 Feb 2010 09:19:41 -0800 From: David Daney User-Agent: Thunderbird 2.0.0.21 (X11/20090320) MIME-Version: 1.0 To: Sergei Shtylyov CC: linux-mips@linux-mips.org, ralf@linux-mips.org Subject: Re: [PATCH 3/4] MIPS: Add TLBP to uasm. References: <4B6CA90C.1000609@caviumnetworks.com> <1265412431-28526-3-git-send-email-ddaney@caviumnetworks.com> <4B6FEE4A.6090504@ru.mvista.com> In-Reply-To: <4B6FEE4A.6090504@ru.mvista.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 08 Feb 2010 17:19:43.0469 (UTC) FILETIME=[E79271D0:01CAA8E2] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25899 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Sergei Shtylyov wrote: > Hello. > > David Daney wrote: > >> The soon to follow Read Inhibit/eXecute Inhibit patch needs TLBP >> > > But you're adding TLBR support, not TLBP? > Right. I am making more changes to this patch set and will correct that. Thanks, David Daney From David.Daney@caviumnetworks.com Mon Feb 8 21:27:09 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 08 Feb 2010 21:27:31 +0100 (CET) Received: from mail3.caviumnetworks.com ([12.108.191.235]:9467 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492281Ab0BHU1J (ORCPT ); Mon, 8 Feb 2010 21:27:09 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Mon, 08 Feb 2010 12:27:14 -0800 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Mon, 8 Feb 2010 12:27:05 -0800 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Mon, 8 Feb 2010 12:27:05 -0800 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.2/8.14.2) with ESMTP id o18KR2w2005444; Mon, 8 Feb 2010 12:27:02 -0800 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.2/8.14.2/Submit) id o18KR0Mq005442; Mon, 8 Feb 2010 12:27:00 -0800 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: David Daney , Guenter Roeck Subject: [PATCH] MIPS: Don't probe reserved EntryHi bits. Date: Mon, 8 Feb 2010 12:27:00 -0800 Message-Id: <1265660820-5418-1-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.6.0.6 X-OriginalArrivalTime: 08 Feb 2010 20:27:05.0166 (UTC) FILETIME=[142546E0:01CAA8FD] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25900 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips The patch that adds cpu_probe_vmbits is erroneously writing to reserved bit 12. Since we are really only probing high bits, don't write this bit with a one. Signed-off-by: David Daney CC: Guenter Roeck --- arch/mips/kernel/cpu-probe.c | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index 2ff5f64..9ea5ca8 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -287,9 +287,9 @@ static inline int __cpu_has_fpu(void) static inline void cpu_probe_vmbits(struct cpuinfo_mips *c) { #ifdef __NEED_VMBITS_PROBE - write_c0_entryhi(0x3ffffffffffff000ULL); + write_c0_entryhi(0x3fffffffffffe000ULL); back_to_back_c0_hazard(); - c->vmbits = fls64(read_c0_entryhi() & 0x3ffffffffffff000ULL); + c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL); #endif } -- 1.6.0.6 From guenter.roeck@ericsson.com Mon Feb 8 21:34:57 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 08 Feb 2010 21:35:01 +0100 (CET) Received: from imr1.ericy.com ([198.24.6.9]:47342 "EHLO imr1.ericy.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491984Ab0BHUe5 (ORCPT ); Mon, 8 Feb 2010 21:34:57 +0100 Received: from eusaamw0712.eamcs.ericsson.se ([147.117.20.181]) by imr1.ericy.com (8.13.1/8.13.1) with ESMTP id o18Ka9Lt015312; Mon, 8 Feb 2010 14:36:14 -0600 Received: from [155.53.128.103] (147.117.20.212) by eusaamw0712.eamcs.ericsson.se (147.117.20.182) with Microsoft SMTP Server id 8.1.375.2; Mon, 8 Feb 2010 15:34:45 -0500 Subject: Re: [PATCH] MIPS: Don't probe reserved EntryHi bits. From: Guenter Roeck Reply-To: guenter.roeck@ericsson.com To: David Daney CC: "linux-mips@linux-mips.org" , "ralf@linux-mips.org" In-Reply-To: <1265660820-5418-1-git-send-email-ddaney@caviumnetworks.com> References: <1265660820-5418-1-git-send-email-ddaney@caviumnetworks.com> Content-Type: text/plain Organization: Ericsson Date: Mon, 8 Feb 2010 12:36:28 -0800 Message-ID: <1265661388.5825.151.camel@groeck-laptop> MIME-Version: 1.0 X-Mailer: Evolution 2.26.1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25901 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: guenter.roeck@ericsson.com Precedence: bulk X-list: linux-mips On Mon, 2010-02-08 at 15:27 -0500, David Daney wrote: > The patch that adds cpu_probe_vmbits is erroneously writing to > reserved bit 12. Since we are really only probing high bits, don't > write this bit with a one. > > Signed-off-by: David Daney > CC: Guenter Roeck Signed-off-by: Guenter Roeck > --- > arch/mips/kernel/cpu-probe.c | 4 ++-- > 1 files changed, 2 insertions(+), 2 deletions(-) > > diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c > index 2ff5f64..9ea5ca8 100644 > --- a/arch/mips/kernel/cpu-probe.c > +++ b/arch/mips/kernel/cpu-probe.c > @@ -287,9 +287,9 @@ static inline int __cpu_has_fpu(void) > static inline void cpu_probe_vmbits(struct cpuinfo_mips *c) > { > #ifdef __NEED_VMBITS_PROBE > - write_c0_entryhi(0x3ffffffffffff000ULL); > + write_c0_entryhi(0x3fffffffffffe000ULL); > back_to_back_c0_hazard(); > - c->vmbits = fls64(read_c0_entryhi() & 0x3ffffffffffff000ULL); > + c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL); > #endif > } > From ralf@linux-mips.org Tue Feb 9 14:16:59 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 09 Feb 2010 14:17:04 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:36057 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491841Ab0BINQ7 (ORCPT ); Tue, 9 Feb 2010 14:16:59 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id o19DHMuu016941; Tue, 9 Feb 2010 14:17:22 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id o19DHKK6016939; Tue, 9 Feb 2010 14:17:20 +0100 Date: Tue, 9 Feb 2010 14:17:20 +0100 From: Ralf Baechle To: Guenter Roeck Cc: David Daney , "linux-mips@linux-mips.org" Subject: Re: [PATCH] MIPS: Don't probe reserved EntryHi bits. Message-ID: <20100209131720.GA16712@linux-mips.org> References: <1265660820-5418-1-git-send-email-ddaney@caviumnetworks.com> <1265661388.5825.151.camel@groeck-laptop> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1265661388.5825.151.camel@groeck-laptop> User-Agent: Mutt/1.5.20 (2009-08-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25902 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Mon, Feb 08, 2010 at 12:36:28PM -0800, Guenter Roeck wrote: > On Mon, 2010-02-08 at 15:27 -0500, David Daney wrote: > > The patch that adds cpu_probe_vmbits is erroneously writing to > > reserved bit 12. Since we are really only probing high bits, don't > > write this bit with a one. > > > > Signed-off-by: David Daney > > CC: Guenter Roeck > > Signed-off-by: Guenter Roeck Acked-by: you meant. Patch applied. Thanks folks, Ralf From David.Daney@caviumnetworks.com Thu Feb 11 00:08:40 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 11 Feb 2010 00:08:44 +0100 (CET) Received: from mail3.caviumnetworks.com ([12.108.191.235]:15820 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492360Ab0BJXIk (ORCPT ); Thu, 11 Feb 2010 00:08:40 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Wed, 10 Feb 2010 15:08:45 -0800 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Wed, 10 Feb 2010 15:08:35 -0800 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Wed, 10 Feb 2010 15:08:35 -0800 Message-ID: <4B733C71.8030304@caviumnetworks.com> Date: Wed, 10 Feb 2010 15:08:33 -0800 From: David Daney User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.7) Gecko/20100120 Fedora/3.0.1-1.fc11 Thunderbird/3.0.1 MIME-Version: 1.0 To: Ralf Baechle , linux-mips Subject: [PATCH 0/6] MIPS Read Inhibit/eXecute Inhibit support (v2). Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 10 Feb 2010 23:08:35.0267 (UTC) FILETIME=[F8B8D930:01CAAAA5] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25903 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips This patch set adds execute and read inhibit support. By default glibc based tool chains will create mappings for data areas of a program and shared libraries with PROT_EXEC cleared. With this patch applied, a SIGSEGV is correctly sent if an attempt is made to execute from data areas. The first three patch just make a few tweaks in preperation for the main body of the patch in 4/6. The last two turn on the feature for some Octeon CPUs. I will reply with the six patches. David Daney (6): MIPS: Use 64-bit stores to c0_entrylo on 64-bit kernels. MIPS: Add accessor functions and bit definitions for c0_PageGrain MIPS: Add TLBR and ROTR to uasm. MIPS: Implement Read Inhibit/eXecute Inhibit MIPS: Give Octeon+ CPUs their own cputype. MIPS: Enable Read Inhibit/eXecute Inhibit for Octeon+ CPUs arch/mips/include/asm/cpu-features.h | 3 + arch/mips/include/asm/cpu.h | 2 +- .../asm/mach-cavium-octeon/cpu-feature-overrides.h | 3 + arch/mips/include/asm/mipsregs.h | 11 ++ arch/mips/include/asm/pgtable-32.h | 4 +- arch/mips/include/asm/pgtable-64.h | 4 +- arch/mips/include/asm/pgtable-bits.h | 105 ++++++++++-- arch/mips/include/asm/pgtable.h | 26 ++- arch/mips/include/asm/uasm.h | 4 + arch/mips/kernel/cpu-probe.c | 6 +- arch/mips/mm/c-octeon.c | 7 +- arch/mips/mm/cache.c | 53 ++++-- arch/mips/mm/fault.c | 27 +++- arch/mips/mm/init.c | 2 +- arch/mips/mm/tlb-r4k.c | 19 ++- arch/mips/mm/tlbex.c | 183 ++++++++++++++++---- arch/mips/mm/uasm.c | 9 +- 17 files changed, 375 insertions(+), 93 deletions(-) From David.Daney@caviumnetworks.com Thu Feb 11 00:13:50 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 11 Feb 2010 00:13:53 +0100 (CET) Received: from mail3.caviumnetworks.com ([12.108.191.235]:15978 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492360Ab0BJXNu (ORCPT ); Thu, 11 Feb 2010 00:13:50 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Wed, 10 Feb 2010 15:13:57 -0800 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Wed, 10 Feb 2010 15:12:52 -0800 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Wed, 10 Feb 2010 15:12:52 -0800 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.3/8.14.2) with ESMTP id o1ANCncl005827; Wed, 10 Feb 2010 15:12:49 -0800 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.3/8.14.3/Submit) id o1ANCn3R005826; Wed, 10 Feb 2010 15:12:49 -0800 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: David Daney Subject: [PATCH 2/6] MIPS: Add accessor functions and bit definitions for c0_PageGrain Date: Wed, 10 Feb 2010 15:12:45 -0800 Message-Id: <1265843569-5786-2-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.6.2.5 In-Reply-To: <4B733C71.8030304@caviumnetworks.com> References: <4B733C71.8030304@caviumnetworks.com> X-OriginalArrivalTime: 10 Feb 2010 23:12:52.0410 (UTC) FILETIME=[91FDC1A0:01CAAAA6] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25904 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Signed-off-by: David Daney --- arch/mips/include/asm/mipsregs.h | 11 +++++++++++ 1 files changed, 11 insertions(+), 0 deletions(-) diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h index b30819c..9893758 100644 --- a/arch/mips/include/asm/mipsregs.h +++ b/arch/mips/include/asm/mipsregs.h @@ -251,6 +251,14 @@ #define PL_256M 28 /* + * PageGrain bits + */ +#define PG_RIE (_ULCAST_(1) << 31) +#define PG_XIE (_ULCAST_(1) << 30) +#define PG_ELPA (_ULCAST_(1) << 29) +#define PG_ESP (_ULCAST_(1) << 28) + +/* * R4x00 interrupt enable / cause bits */ #define IE_SW0 (_ULCAST_(1) << 8) @@ -840,6 +848,9 @@ do { \ #define read_c0_pagemask() __read_32bit_c0_register($5, 0) #define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val) +#define read_c0_pagegrain() __read_32bit_c0_register($5, 1) +#define write_c0_pagegrain(val) __write_32bit_c0_register($5, 1, val) + #define read_c0_wired() __read_32bit_c0_register($6, 0) #define write_c0_wired(val) __write_32bit_c0_register($6, 0, val) -- 1.6.2.5 From David.Daney@caviumnetworks.com Thu Feb 11 00:14:11 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 11 Feb 2010 00:14:18 +0100 (CET) Received: from mail3.caviumnetworks.com ([12.108.191.235]:15982 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492372Ab0BJXNu (ORCPT ); Thu, 11 Feb 2010 00:13:50 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Wed, 10 Feb 2010 15:13:58 -0800 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Wed, 10 Feb 2010 15:12:52 -0800 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Wed, 10 Feb 2010 15:12:52 -0800 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.3/8.14.2) with ESMTP id o1ANCo9r005839; Wed, 10 Feb 2010 15:12:50 -0800 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.3/8.14.3/Submit) id o1ANCoHL005838; Wed, 10 Feb 2010 15:12:50 -0800 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: David Daney Subject: [PATCH 5/6] MIPS: Give Octeon+ CPUs their own cputype. Date: Wed, 10 Feb 2010 15:12:48 -0800 Message-Id: <1265843569-5786-5-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.6.2.5 In-Reply-To: <4B733C71.8030304@caviumnetworks.com> References: <4B733C71.8030304@caviumnetworks.com> X-OriginalArrivalTime: 10 Feb 2010 23:12:52.0410 (UTC) FILETIME=[91FDC1A0:01CAAAA6] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25905 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips This allows us to treat them differently at runtime. Signed-off-by: David Daney --- arch/mips/include/asm/cpu.h | 2 +- arch/mips/kernel/cpu-probe.c | 6 +++++- arch/mips/mm/c-octeon.c | 7 ++++--- 3 files changed, 10 insertions(+), 5 deletions(-) diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h index cf373a9..a5acda4 100644 --- a/arch/mips/include/asm/cpu.h +++ b/arch/mips/include/asm/cpu.h @@ -224,7 +224,7 @@ enum cpu_type_enum { * MIPS64 class processors */ CPU_5KC, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2, - CPU_CAVIUM_OCTEON, + CPU_CAVIUM_OCTEON, CPU_CAVIUM_OCTEON_PLUS, CPU_LAST }; diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index 9ea5ca8..ee67aac 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -162,6 +162,7 @@ void __init check_wait(void) case CPU_BCM6348: case CPU_BCM6358: case CPU_CAVIUM_OCTEON: + case CPU_CAVIUM_OCTEON_PLUS: cpu_wait = r4k_wait; break; @@ -911,11 +912,14 @@ static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu) case PRID_IMP_CAVIUM_CN38XX: case PRID_IMP_CAVIUM_CN31XX: case PRID_IMP_CAVIUM_CN30XX: + c->cputype = CPU_CAVIUM_OCTEON; + goto name_and_platform; case PRID_IMP_CAVIUM_CN58XX: case PRID_IMP_CAVIUM_CN56XX: case PRID_IMP_CAVIUM_CN50XX: case PRID_IMP_CAVIUM_CN52XX: - c->cputype = CPU_CAVIUM_OCTEON; + c->cputype = CPU_CAVIUM_OCTEON_PLUS; +name_and_platform: __cpu_name[cpu] = "Cavium Octeon"; if (cpu == 0) __elf_platform = "octeon"; diff --git a/arch/mips/mm/c-octeon.c b/arch/mips/mm/c-octeon.c index af85959..0f9c488 100644 --- a/arch/mips/mm/c-octeon.c +++ b/arch/mips/mm/c-octeon.c @@ -183,6 +183,7 @@ static void __cpuinit probe_octeon(void) switch (c->cputype) { case CPU_CAVIUM_OCTEON: + case CPU_CAVIUM_OCTEON_PLUS: config1 = read_c0_config1(); c->icache.linesz = 2 << ((config1 >> 19) & 7); c->icache.sets = 64 << ((config1 >> 22) & 7); @@ -192,10 +193,10 @@ static void __cpuinit probe_octeon(void) c->icache.sets * c->icache.ways * c->icache.linesz; c->icache.waybit = ffs(icache_size / c->icache.ways) - 1; c->dcache.linesz = 128; - if (OCTEON_IS_MODEL(OCTEON_CN3XXX)) - c->dcache.sets = 1; /* CN3XXX has one Dcache set */ - else + if (c->cputype == CPU_CAVIUM_OCTEON_PLUS) c->dcache.sets = 2; /* CN5XXX has two Dcache sets */ + else + c->dcache.sets = 1; /* CN3XXX has one Dcache set */ c->dcache.ways = 64; dcache_size = c->dcache.sets * c->dcache.ways * c->dcache.linesz; -- 1.6.2.5 From David.Daney@caviumnetworks.com Thu Feb 11 00:14:36 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 11 Feb 2010 00:14:44 +0100 (CET) Received: from mail3.caviumnetworks.com ([12.108.191.235]:15981 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492365Ab0BJXNv (ORCPT ); Thu, 11 Feb 2010 00:13:51 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Wed, 10 Feb 2010 15:13:57 -0800 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Wed, 10 Feb 2010 15:12:52 -0800 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Wed, 10 Feb 2010 15:12:52 -0800 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.3/8.14.2) with ESMTP id o1ANCofT005835; Wed, 10 Feb 2010 15:12:50 -0800 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.3/8.14.3/Submit) id o1ANCoen005834; Wed, 10 Feb 2010 15:12:50 -0800 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: David Daney Subject: [PATCH 4/6] MIPS: Implement Read Inhibit/eXecute Inhibit Date: Wed, 10 Feb 2010 15:12:47 -0800 Message-Id: <1265843569-5786-4-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.6.2.5 In-Reply-To: <4B733C71.8030304@caviumnetworks.com> References: <4B733C71.8030304@caviumnetworks.com> X-OriginalArrivalTime: 10 Feb 2010 23:12:52.0425 (UTC) FILETIME=[92000B90:01CAAAA6] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25906 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips The SmartMIPS ASE specifies how Read Inhibit (RI) and eXecute Inhibit (XI) bits in the page tables work. The upper two bits of EntryLo{0,1} are RI and XI when the feature is enabled in the PageGrain register. SmartMIPS only covers 32-bit systems. Cavium Octeon+ extends this to 64-bit systems by continuing to place the RI and XI bits in the top of EntryLo even when EntryLo is 64-bits wide. Because we need to carry the RI and XI bits in the PTE, the layout of the PTE is changed. There is a two instruction overhead in the TLB refill hot path to get the EntryLo bits into the proper position. Also the TLB load exception has to probe the TLB to check if RI or XI caused the exception. Also of note is that the layout of the PTE bits is done at compile and runtime rather than statically. In the 32-bit case this allows for the same number of PFN bits as before the patch as the _PAGE_HUGE is not supported in 32-bit kernels (we have _PAGE_NO_EXEC and _PAGE_NO_READ instead of _PAGE_READ and _PAGE_HUGE). The patch is tested on Cavium Octeon+, but should also work on 32-bit systems with the Smart-MIPS ASE. Signed-off-by: David Daney --- arch/mips/include/asm/cpu-features.h | 3 + arch/mips/include/asm/pgtable-32.h | 4 +- arch/mips/include/asm/pgtable-64.h | 4 +- arch/mips/include/asm/pgtable-bits.h | 105 ++++++++++++++++++--- arch/mips/include/asm/pgtable.h | 26 +++-- arch/mips/mm/cache.c | 53 ++++++++--- arch/mips/mm/fault.c | 27 +++++- arch/mips/mm/init.c | 2 +- arch/mips/mm/tlb-r4k.c | 19 +++- arch/mips/mm/tlbex.c | 169 ++++++++++++++++++++++++++++------ 10 files changed, 333 insertions(+), 79 deletions(-) diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h index 272c5ef..ac73ced 100644 --- a/arch/mips/include/asm/cpu-features.h +++ b/arch/mips/include/asm/cpu-features.h @@ -95,6 +95,9 @@ #ifndef cpu_has_smartmips #define cpu_has_smartmips (cpu_data[0].ases & MIPS_ASE_SMARTMIPS) #endif +#ifndef kernel_uses_smartmips_rixi +#define kernel_uses_smartmips_rixi 0 +#endif #ifndef cpu_has_vtag_icache #define cpu_has_vtag_icache (cpu_data[0].icache.flags & MIPS_CACHE_VTAG) #endif diff --git a/arch/mips/include/asm/pgtable-32.h b/arch/mips/include/asm/pgtable-32.h index 55813d6..ae90412 100644 --- a/arch/mips/include/asm/pgtable-32.h +++ b/arch/mips/include/asm/pgtable-32.h @@ -127,8 +127,8 @@ pfn_pte(unsigned long pfn, pgprot_t prot) #define pte_pfn(x) ((unsigned long)((x).pte >> (PAGE_SHIFT + 2))) #define pfn_pte(pfn, prot) __pte(((pfn) << (PAGE_SHIFT + 2)) | pgprot_val(prot)) #else -#define pte_pfn(x) ((unsigned long)((x).pte >> PAGE_SHIFT)) -#define pfn_pte(pfn, prot) __pte(((unsigned long long)(pfn) << PAGE_SHIFT) | pgprot_val(prot)) +#define pte_pfn(x) ((unsigned long)((x).pte >> _PFN_SHIFT)) +#define pfn_pte(pfn, prot) __pte(((unsigned long long)(pfn) << _PFN_SHIFT) | pgprot_val(prot)) #endif #endif /* defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) */ diff --git a/arch/mips/include/asm/pgtable-64.h b/arch/mips/include/asm/pgtable-64.h index 2c1d194..adc2093 100644 --- a/arch/mips/include/asm/pgtable-64.h +++ b/arch/mips/include/asm/pgtable-64.h @@ -216,8 +216,8 @@ static inline void pud_clear(pud_t *pudp) #define pte_pfn(x) ((unsigned long)((x).pte >> (PAGE_SHIFT + 2))) #define pfn_pte(pfn, prot) __pte(((pfn) << (PAGE_SHIFT + 2)) | pgprot_val(prot)) #else -#define pte_pfn(x) ((unsigned long)((x).pte >> PAGE_SHIFT)) -#define pfn_pte(pfn, prot) __pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot)) +#define pte_pfn(x) ((unsigned long)((x).pte >> _PFN_SHIFT)) +#define pfn_pte(pfn, prot) __pte(((pfn) << _PFN_SHIFT) | pgprot_val(prot)) #endif #define __pgd_offset(address) pgd_index(address) diff --git a/arch/mips/include/asm/pgtable-bits.h b/arch/mips/include/asm/pgtable-bits.h index 1073e6d..a2e646f 100644 --- a/arch/mips/include/asm/pgtable-bits.h +++ b/arch/mips/include/asm/pgtable-bits.h @@ -50,7 +50,7 @@ #define _CACHE_SHIFT 3 #define _CACHE_MASK (7<<3) -#else +#elif defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) #define _PAGE_PRESENT (1<<0) /* implemented in software */ #define _PAGE_READ (1<<1) /* implemented in software */ @@ -59,8 +59,6 @@ #define _PAGE_MODIFIED (1<<4) /* implemented in software */ #define _PAGE_FILE (1<<4) /* set:pagecache unset:swap */ -#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) - #define _PAGE_GLOBAL (1<<8) #define _PAGE_VALID (1<<9) #define _PAGE_SILENT_READ (1<<9) /* synonym */ @@ -68,22 +66,99 @@ #define _PAGE_SILENT_WRITE (1<<10) #define _CACHE_UNCACHED (1<<11) #define _CACHE_MASK (1<<11) +#define _PFN_SHIFT PAGE_SHIFT + +#else /* 'Normal' r4K case */ +/* + * When using the RI/XI bit support, we have 13 bits of flags below + * the physical address. The RI/XI bits are placed such that a SRL 5 + * can strip off the software bits, then a ROTR 2 can move the RI/XI + * into bits [63:62]. This also limits physical address to 56 bits, + * which is more than we need right now. + */ +/* implemented in software */ +#define _PAGE_PRESENT_SHIFT (0) +#define _PAGE_PRESENT (1 << _PAGE_PRESENT_SHIFT) +/* implemented in software, should be unused if kernel_uses_smartmips_rixi. */ +#define _PAGE_READ_SHIFT (kernel_uses_smartmips_rixi ? _PAGE_PRESENT_SHIFT : _PAGE_PRESENT_SHIFT + 1) +#define _PAGE_READ ({if (kernel_uses_smartmips_rixi) BUG(); 1 << _PAGE_READ_SHIFT; }) +/* implemented in software */ +#define _PAGE_WRITE_SHIFT (_PAGE_READ_SHIFT + 1) +#define _PAGE_WRITE (1 << _PAGE_WRITE_SHIFT) +/* implemented in software */ +#define _PAGE_ACCESSED_SHIFT (_PAGE_WRITE_SHIFT + 1) +#define _PAGE_ACCESSED (1 << _PAGE_ACCESSED_SHIFT) +/* implemented in software */ +#define _PAGE_MODIFIED_SHIFT (_PAGE_ACCESSED_SHIFT + 1) +#define _PAGE_MODIFIED (1 << _PAGE_MODIFIED_SHIFT) +/* set:pagecache unset:swap */ +#define _PAGE_FILE (_PAGE_MODIFIED) + +#ifdef CONFIG_HUGETLB_PAGE +/* huge tlb page */ +#define _PAGE_HUGE_SHIFT (_PAGE_MODIFIED_SHIFT + 1) +#define _PAGE_HUGE (1 << _PAGE_HUGE_SHIFT) #else +#define _PAGE_HUGE_SHIFT (_PAGE_MODIFIED_SHIFT) +#define _PAGE_HUGE ({BUG(); 1; }) /* Dummy value */ +#endif -#define _PAGE_R4KBUG (1<<5) /* workaround for r4k bug */ -#define _PAGE_HUGE (1<<5) /* huge tlb page */ -#define _PAGE_GLOBAL (1<<6) -#define _PAGE_VALID (1<<7) -#define _PAGE_SILENT_READ (1<<7) /* synonym */ -#define _PAGE_DIRTY (1<<8) /* The MIPS dirty bit */ -#define _PAGE_SILENT_WRITE (1<<8) -#define _CACHE_SHIFT 9 -#define _CACHE_MASK (7<<9) +/* Page cannot be executed */ +#define _PAGE_NO_EXEC_SHIFT (kernel_uses_smartmips_rixi ? _PAGE_HUGE_SHIFT + 1 : _PAGE_HUGE_SHIFT) +#define _PAGE_NO_EXEC ({if (!kernel_uses_smartmips_rixi) BUG(); 1 << _PAGE_NO_EXEC_SHIFT; }) + +/* Page cannot be read */ +#define _PAGE_NO_READ_SHIFT (kernel_uses_smartmips_rixi ? _PAGE_NO_EXEC_SHIFT + 1 : _PAGE_NO_EXEC_SHIFT) +#define _PAGE_NO_READ ({if (!kernel_uses_smartmips_rixi) BUG(); 1 << _PAGE_NO_READ_SHIFT; }) + +#define _PAGE_GLOBAL_SHIFT (_PAGE_NO_READ_SHIFT + 1) +#define _PAGE_GLOBAL (1 << _PAGE_GLOBAL_SHIFT) + +#define _PAGE_VALID_SHIFT (_PAGE_GLOBAL_SHIFT + 1) +#define _PAGE_VALID (1 << _PAGE_VALID_SHIFT) +/* synonym */ +#define _PAGE_SILENT_READ (_PAGE_VALID) + +/* The MIPS dirty bit */ +#define _PAGE_DIRTY_SHIFT (_PAGE_VALID_SHIFT + 1) +#define _PAGE_DIRTY (1 << _PAGE_DIRTY_SHIFT) +#define _PAGE_SILENT_WRITE (_PAGE_DIRTY) + +#define _CACHE_SHIFT (_PAGE_DIRTY_SHIFT + 1) +#define _CACHE_MASK (7 << _CACHE_SHIFT) + +#define _PFN_SHIFT (PAGE_SHIFT - 12 + _CACHE_SHIFT + 3) +#define _PFN_MASK (~((1 << (_PFN_SHIFT)) - 1)) -#endif #endif /* defined(CONFIG_64BIT_PHYS_ADDR && defined(CONFIG_CPU_MIPS32) */ +#ifndef __ASSEMBLY__ +/* + * pte_to_entrylo converts a page table entry (PTE) into a Mips + * entrylo0/1 value. + */ +static inline uint64_t pte_to_entrylo(unsigned long pte_val) +{ + if (kernel_uses_smartmips_rixi) { + int sa; +#ifdef CONFIG_32BIT + sa = 31 - _PAGE_NO_READ_SHIFT; +#else + sa = 63 - _PAGE_NO_READ_SHIFT; +#endif + /* + * C has no way to express that this is a DSRL 5 + * followed by a ROTR 2. Luckily in the fast path + * this is done in assembly + */ + return (pte_val >> _PAGE_GLOBAL_SHIFT) | + ((pte_val & (_PAGE_NO_EXEC | _PAGE_NO_READ)) << sa); + } + + return pte_val >> _PAGE_GLOBAL_SHIFT; +} +#endif /* * Cache attributes @@ -130,9 +205,9 @@ #endif -#define __READABLE (_PAGE_READ | _PAGE_SILENT_READ | _PAGE_ACCESSED) +#define __READABLE (_PAGE_SILENT_READ | _PAGE_ACCESSED | (kernel_uses_smartmips_rixi ? 0 : _PAGE_READ)) #define __WRITEABLE (_PAGE_WRITE | _PAGE_SILENT_WRITE | _PAGE_MODIFIED) -#define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_MODIFIED | _CACHE_MASK) +#define _PAGE_CHG_MASK (_PFN_MASK | _PAGE_ACCESSED | _PAGE_MODIFIED | _CACHE_MASK) #endif /* _ASM_PGTABLE_BITS_H */ diff --git a/arch/mips/include/asm/pgtable.h b/arch/mips/include/asm/pgtable.h index 02335fd..93598ba 100644 --- a/arch/mips/include/asm/pgtable.h +++ b/arch/mips/include/asm/pgtable.h @@ -22,23 +22,24 @@ struct mm_struct; struct vm_area_struct; #define PAGE_NONE __pgprot(_PAGE_PRESENT | _CACHE_CACHABLE_NONCOHERENT) -#define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ +#define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_WRITE | (kernel_uses_smartmips_rixi ? 0 : _PAGE_READ) | \ _page_cachable_default) -#define PAGE_COPY __pgprot(_PAGE_PRESENT | _PAGE_READ | \ - _page_cachable_default) -#define PAGE_READONLY __pgprot(_PAGE_PRESENT | _PAGE_READ | \ +#define PAGE_COPY __pgprot(_PAGE_PRESENT | (kernel_uses_smartmips_rixi ? 0 : _PAGE_READ) | \ + (kernel_uses_smartmips_rixi ? _PAGE_NO_EXEC : 0) | _page_cachable_default) +#define PAGE_READONLY __pgprot(_PAGE_PRESENT | (kernel_uses_smartmips_rixi ? 0 : _PAGE_READ) | \ _page_cachable_default) #define PAGE_KERNEL __pgprot(_PAGE_PRESENT | __READABLE | __WRITEABLE | \ _PAGE_GLOBAL | _page_cachable_default) -#define PAGE_USERIO __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \ +#define PAGE_USERIO __pgprot(_PAGE_PRESENT | (kernel_uses_smartmips_rixi ? 0 : _PAGE_READ) | _PAGE_WRITE | \ _page_cachable_default) #define PAGE_KERNEL_UNCACHED __pgprot(_PAGE_PRESENT | __READABLE | \ __WRITEABLE | _PAGE_GLOBAL | _CACHE_UNCACHED) /* - * MIPS can't do page protection for execute, and considers that the same like - * read. Also, write permissions imply read permissions. This is the closest - * we can get by reasonable means.. + * If _PAGE_NO_EXEC is not defined, we can't do page protection for + * execute, and consider it to be the same as read. Also, write + * permissions imply read permissions. This is the closest we can get + * by reasonable means.. */ /* @@ -298,8 +299,13 @@ static inline pte_t pte_mkdirty(pte_t pte) static inline pte_t pte_mkyoung(pte_t pte) { pte_val(pte) |= _PAGE_ACCESSED; - if (pte_val(pte) & _PAGE_READ) - pte_val(pte) |= _PAGE_SILENT_READ; + if (kernel_uses_smartmips_rixi) { + if (!(pte_val(pte) & _PAGE_NO_READ)) + pte_val(pte) |= _PAGE_SILENT_READ; + } else { + if (pte_val(pte) & _PAGE_READ) + pte_val(pte) |= _PAGE_SILENT_READ; + } return pte; } diff --git a/arch/mips/mm/cache.c b/arch/mips/mm/cache.c index e716caf..be8627b 100644 --- a/arch/mips/mm/cache.c +++ b/arch/mips/mm/cache.c @@ -137,22 +137,43 @@ EXPORT_SYMBOL_GPL(_page_cachable_default); static inline void setup_protection_map(void) { - protection_map[0] = PAGE_NONE; - protection_map[1] = PAGE_READONLY; - protection_map[2] = PAGE_COPY; - protection_map[3] = PAGE_COPY; - protection_map[4] = PAGE_READONLY; - protection_map[5] = PAGE_READONLY; - protection_map[6] = PAGE_COPY; - protection_map[7] = PAGE_COPY; - protection_map[8] = PAGE_NONE; - protection_map[9] = PAGE_READONLY; - protection_map[10] = PAGE_SHARED; - protection_map[11] = PAGE_SHARED; - protection_map[12] = PAGE_READONLY; - protection_map[13] = PAGE_READONLY; - protection_map[14] = PAGE_SHARED; - protection_map[15] = PAGE_SHARED; + if (kernel_uses_smartmips_rixi) { + protection_map[0] = __pgprot(_page_cachable_default | _PAGE_PRESENT | _PAGE_NO_EXEC | _PAGE_NO_READ); + protection_map[1] = __pgprot(_page_cachable_default | _PAGE_PRESENT | _PAGE_NO_EXEC); + protection_map[2] = __pgprot(_page_cachable_default | _PAGE_PRESENT | _PAGE_NO_EXEC | _PAGE_NO_READ); + protection_map[3] = __pgprot(_page_cachable_default | _PAGE_PRESENT | _PAGE_NO_EXEC); + protection_map[4] = __pgprot(_page_cachable_default | _PAGE_PRESENT | _PAGE_NO_READ); + protection_map[5] = __pgprot(_page_cachable_default | _PAGE_PRESENT); + protection_map[6] = __pgprot(_page_cachable_default | _PAGE_PRESENT | _PAGE_NO_READ); + protection_map[7] = __pgprot(_page_cachable_default | _PAGE_PRESENT); + + protection_map[8] = __pgprot(_page_cachable_default | _PAGE_PRESENT | _PAGE_NO_EXEC | _PAGE_NO_READ); + protection_map[9] = __pgprot(_page_cachable_default | _PAGE_PRESENT | _PAGE_NO_EXEC); + protection_map[10] = __pgprot(_page_cachable_default | _PAGE_PRESENT | _PAGE_NO_EXEC | _PAGE_WRITE | _PAGE_NO_READ); + protection_map[11] = __pgprot(_page_cachable_default | _PAGE_PRESENT | _PAGE_NO_EXEC | _PAGE_WRITE); + protection_map[12] = __pgprot(_page_cachable_default | _PAGE_PRESENT | _PAGE_NO_READ); + protection_map[13] = __pgprot(_page_cachable_default | _PAGE_PRESENT); + protection_map[14] = __pgprot(_page_cachable_default | _PAGE_PRESENT | _PAGE_WRITE | _PAGE_NO_READ); + protection_map[15] = __pgprot(_page_cachable_default | _PAGE_PRESENT | _PAGE_WRITE); + + } else { + protection_map[0] = PAGE_NONE; + protection_map[1] = PAGE_READONLY; + protection_map[2] = PAGE_COPY; + protection_map[3] = PAGE_COPY; + protection_map[4] = PAGE_READONLY; + protection_map[5] = PAGE_READONLY; + protection_map[6] = PAGE_COPY; + protection_map[7] = PAGE_COPY; + protection_map[8] = PAGE_NONE; + protection_map[9] = PAGE_READONLY; + protection_map[10] = PAGE_SHARED; + protection_map[11] = PAGE_SHARED; + protection_map[12] = PAGE_READONLY; + protection_map[13] = PAGE_READONLY; + protection_map[14] = PAGE_SHARED; + protection_map[15] = PAGE_SHARED; + } } void __cpuinit cpu_cache_init(void) diff --git a/arch/mips/mm/fault.c b/arch/mips/mm/fault.c index e97a7a2..b78f7d9 100644 --- a/arch/mips/mm/fault.c +++ b/arch/mips/mm/fault.c @@ -99,8 +99,31 @@ good_area: if (!(vma->vm_flags & VM_WRITE)) goto bad_area; } else { - if (!(vma->vm_flags & (VM_READ | VM_WRITE | VM_EXEC))) - goto bad_area; + if (kernel_uses_smartmips_rixi) { + if (address == regs->cp0_epc && !(vma->vm_flags & VM_EXEC)) { +#if 0 + pr_notice("Cpu%d[%s:%d:%0*lx:%ld:%0*lx] XI violation\n", + raw_smp_processor_id(), + current->comm, current->pid, + field, address, write, + field, regs->cp0_epc); +#endif + goto bad_area; + } + if (!(vma->vm_flags & VM_READ)) { +#if 0 + pr_notice("Cpu%d[%s:%d:%0*lx:%ld:%0*lx] RI violation\n", + raw_smp_processor_id(), + current->comm, current->pid, + field, address, write, + field, regs->cp0_epc); +#endif + goto bad_area; + } + } else { + if (!(vma->vm_flags & (VM_READ | VM_WRITE | VM_EXEC))) + goto bad_area; + } } /* diff --git a/arch/mips/mm/init.c b/arch/mips/mm/init.c index 3c5b7de..f34c264 100644 --- a/arch/mips/mm/init.c +++ b/arch/mips/mm/init.c @@ -143,7 +143,7 @@ void *kmap_coherent(struct page *page, unsigned long addr) #if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) entrylo = pte.pte_high; #else - entrylo = pte_val(pte) >> 6; + entrylo = pte_to_entrylo(pte_val(pte)); #endif ENTER_CRITICAL(flags); diff --git a/arch/mips/mm/tlb-r4k.c b/arch/mips/mm/tlb-r4k.c index e551559..1032e71 100644 --- a/arch/mips/mm/tlb-r4k.c +++ b/arch/mips/mm/tlb-r4k.c @@ -303,7 +303,7 @@ void __update_tlb(struct vm_area_struct * vma, unsigned long address, pte_t pte) unsigned long lo; write_c0_pagemask(PM_HUGE_MASK); ptep = (pte_t *)pmdp; - lo = pte_val(*ptep) >> 6; + lo = pte_to_entrylo(pte_val(*ptep)); write_c0_entrylo0(lo); write_c0_entrylo1(lo + (HPAGE_SIZE >> 7)); @@ -323,8 +323,8 @@ void __update_tlb(struct vm_area_struct * vma, unsigned long address, pte_t pte) ptep++; write_c0_entrylo1(ptep->pte_high); #else - write_c0_entrylo0(pte_val(*ptep++) >> 6); - write_c0_entrylo1(pte_val(*ptep) >> 6); + write_c0_entrylo0(pte_to_entrylo(pte_val(*ptep++))); + write_c0_entrylo1(pte_to_entrylo(pte_val(*ptep))); #endif mtc0_tlbw_hazard(); if (idx < 0) @@ -439,6 +439,19 @@ void __cpuinit tlb_init(void) current_cpu_type() == CPU_R12000 || current_cpu_type() == CPU_R14000) write_c0_framemask(0); + + if (kernel_uses_smartmips_rixi) { + /* + * Enable the no read, no exec bits, and enable large virtual + * address. + */ + u32 pg = PG_RIE | PG_XIE; +#ifdef CONFIG_64BIT + pg |= PG_ELPA; +#endif + write_c0_pagegrain(pg); + } + temp_tlb_entry = current_cpu_data.tlbsize - 1; /* From this point on the ARC firmware is dead. */ diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index 35431e1..ec60bd5 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -76,6 +76,8 @@ enum label_id { label_vmalloc_done, label_tlbw_hazard, label_split, + label_tlbl_goaround1, + label_tlbl_goaround2, label_nopage_tlbl, label_nopage_tlbs, label_nopage_tlbm, @@ -92,6 +94,8 @@ UASM_L_LA(_vmalloc) UASM_L_LA(_vmalloc_done) UASM_L_LA(_tlbw_hazard) UASM_L_LA(_split) +UASM_L_LA(_tlbl_goaround1) +UASM_L_LA(_tlbl_goaround2) UASM_L_LA(_nopage_tlbl) UASM_L_LA(_nopage_tlbs) UASM_L_LA(_nopage_tlbm) @@ -396,36 +400,60 @@ static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l, } } -#ifdef CONFIG_HUGETLB_PAGE -static __cpuinit void build_huge_tlb_write_entry(u32 **p, - struct uasm_label **l, - struct uasm_reloc **r, - unsigned int tmp, - enum tlb_write_entry wmode) +static __cpuinit __maybe_unused void build_convert_pte_to_entrylo(u32 **p, + unsigned int reg) { - /* Set huge page tlb entry size */ - uasm_i_lui(p, tmp, PM_HUGE_MASK >> 16); - uasm_i_ori(p, tmp, tmp, PM_HUGE_MASK & 0xffff); - uasm_i_mtc0(p, tmp, C0_PAGEMASK); + if (kernel_uses_smartmips_rixi) { + UASM_i_SRL(p, reg, reg, ilog2(_PAGE_NO_EXEC)); + UASM_i_ROTR(p, reg, reg, ilog2(_PAGE_GLOBAL) - ilog2(_PAGE_NO_EXEC)); + } else { +#ifdef CONFIG_64BIT_PHYS_ADDR + uasm_i_dsrl(p, reg, reg, ilog2(_PAGE_GLOBAL)); +#else + UASM_i_SRL(p, reg, reg, ilog2(_PAGE_GLOBAL)); +#endif + } +} - build_tlb_write_entry(p, l, r, wmode); +#ifdef CONFIG_HUGETLB_PAGE +static __cpuinit void build_restore_pagemask(u32 **p, + struct uasm_reloc **r, + unsigned int tmp, + enum label_id lid) +{ /* Reset default page size */ if (PM_DEFAULT_MASK >> 16) { uasm_i_lui(p, tmp, PM_DEFAULT_MASK >> 16); uasm_i_ori(p, tmp, tmp, PM_DEFAULT_MASK & 0xffff); - uasm_il_b(p, r, label_leave); + uasm_il_b(p, r, lid); uasm_i_mtc0(p, tmp, C0_PAGEMASK); } else if (PM_DEFAULT_MASK) { uasm_i_ori(p, tmp, 0, PM_DEFAULT_MASK); - uasm_il_b(p, r, label_leave); + uasm_il_b(p, r, lid); uasm_i_mtc0(p, tmp, C0_PAGEMASK); } else { - uasm_il_b(p, r, label_leave); + uasm_il_b(p, r, lid); uasm_i_mtc0(p, 0, C0_PAGEMASK); } } +static __cpuinit void build_huge_tlb_write_entry(u32 **p, + struct uasm_label **l, + struct uasm_reloc **r, + unsigned int tmp, + enum tlb_write_entry wmode) +{ + /* Set huge page tlb entry size */ + uasm_i_lui(p, tmp, PM_HUGE_MASK >> 16); + uasm_i_ori(p, tmp, tmp, PM_HUGE_MASK & 0xffff); + uasm_i_mtc0(p, tmp, C0_PAGEMASK); + + build_tlb_write_entry(p, l, r, wmode); + + build_restore_pagemask(p, r, tmp, label_leave); +} + /* * Check if Huge PTE is present, if so then jump to LABEL. */ @@ -459,7 +487,7 @@ static __cpuinit void build_huge_update_entries(u32 **p, if (!small_sequence) uasm_i_lui(p, tmp, HPAGE_SIZE >> (7 + 16)); - UASM_i_SRL(p, pte, pte, 6); /* convert to entrylo */ + build_convert_pte_to_entrylo(p, pte); UASM_i_MTC0(p, pte, C0_ENTRYLO0); /* load it */ /* convert to entrylo1 */ if (small_sequence) @@ -685,9 +713,17 @@ static void __cpuinit build_update_entries(u32 **p, unsigned int tmp, if (cpu_has_64bits) { uasm_i_ld(p, tmp, 0, ptep); /* get even pte */ uasm_i_ld(p, ptep, sizeof(pte_t), ptep); /* get odd pte */ - uasm_i_dsrl(p, tmp, tmp, 6); /* convert to entrylo0 */ - UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */ - uasm_i_dsrl(p, ptep, ptep, 6); /* convert to entrylo1 */ + if (kernel_uses_smartmips_rixi) { + UASM_i_SRL(p, tmp, tmp, ilog2(_PAGE_NO_EXEC)); + UASM_i_SRL(p, ptep, ptep, ilog2(_PAGE_NO_EXEC)); + UASM_i_ROTR(p, tmp, tmp, ilog2(_PAGE_GLOBAL) - ilog2(_PAGE_NO_EXEC)); + UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */ + UASM_i_ROTR(p, ptep, ptep, ilog2(_PAGE_GLOBAL) - ilog2(_PAGE_NO_EXEC)); + } else { + uasm_i_dsrl(p, tmp, tmp, ilog2(_PAGE_GLOBAL)); /* convert to entrylo0 */ + UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */ + uasm_i_dsrl(p, ptep, ptep, ilog2(_PAGE_GLOBAL)); /* convert to entrylo1 */ + } UASM_i_MTC0(p, ptep, C0_ENTRYLO1); /* load it */ } else { int pte_off_even = sizeof(pte_t) / 2; @@ -704,13 +740,23 @@ static void __cpuinit build_update_entries(u32 **p, unsigned int tmp, UASM_i_LW(p, ptep, sizeof(pte_t), ptep); /* get odd pte */ if (r45k_bvahwbug()) build_tlb_probe_entry(p); - UASM_i_SRL(p, tmp, tmp, 6); /* convert to entrylo0 */ - if (r4k_250MHZhwbug()) - UASM_i_MTC0(p, 0, C0_ENTRYLO0); - UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */ - UASM_i_SRL(p, ptep, ptep, 6); /* convert to entrylo1 */ - if (r45k_bvahwbug()) - uasm_i_mfc0(p, tmp, C0_INDEX); + if (kernel_uses_smartmips_rixi) { + UASM_i_SRL(p, tmp, tmp, ilog2(_PAGE_NO_EXEC)); + UASM_i_SRL(p, ptep, ptep, ilog2(_PAGE_NO_EXEC)); + UASM_i_ROTR(p, tmp, tmp, ilog2(_PAGE_GLOBAL) - ilog2(_PAGE_NO_EXEC)); + if (r4k_250MHZhwbug()) + UASM_i_MTC0(p, 0, C0_ENTRYLO0); + UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */ + UASM_i_ROTR(p, ptep, ptep, ilog2(_PAGE_GLOBAL) - ilog2(_PAGE_NO_EXEC)); + } else { + UASM_i_SRL(p, tmp, tmp, 6); /* convert to entrylo0 */ + if (r4k_250MHZhwbug()) + UASM_i_MTC0(p, 0, C0_ENTRYLO0); + UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */ + UASM_i_SRL(p, ptep, ptep, 6); /* convert to entrylo1 */ + if (r45k_bvahwbug()) + uasm_i_mfc0(p, tmp, C0_INDEX); + } if (r4k_250MHZhwbug()) UASM_i_MTC0(p, 0, C0_ENTRYLO1); UASM_i_MTC0(p, ptep, C0_ENTRYLO1); /* load it */ @@ -989,9 +1035,14 @@ static void __cpuinit build_pte_present(u32 **p, struct uasm_reloc **r, unsigned int pte, unsigned int ptr, enum label_id lid) { - uasm_i_andi(p, pte, pte, _PAGE_PRESENT | _PAGE_READ); - uasm_i_xori(p, pte, pte, _PAGE_PRESENT | _PAGE_READ); - uasm_il_bnez(p, r, pte, lid); + if (kernel_uses_smartmips_rixi) { + uasm_i_andi(p, pte, pte, _PAGE_PRESENT); + uasm_il_beqz(p, r, pte, lid); + } else { + uasm_i_andi(p, pte, pte, _PAGE_PRESENT | _PAGE_READ); + uasm_i_xori(p, pte, pte, _PAGE_PRESENT | _PAGE_READ); + uasm_il_bnez(p, r, pte, lid); + } iPTE_LW(p, pte, ptr); } @@ -1279,6 +1330,34 @@ static void __cpuinit build_r4000_tlb_load_handler(void) build_pte_present(&p, &r, K0, K1, label_nopage_tlbl); if (m4kc_tlbp_war()) build_tlb_probe_entry(&p); + + if (kernel_uses_smartmips_rixi) { + /* + * If the page is not _PAGE_VALID, RI or XI could not + * have triggered it. Skip the expensive test.. + */ + uasm_i_andi(&p, K0, K0, _PAGE_VALID); + uasm_il_beqz(&p, &r, K0, label_tlbl_goaround1); + uasm_i_nop(&p); + + uasm_i_tlbr(&p); + /* Examine entrylo 0 or 1 based on ptr. */ + uasm_i_andi(&p, K0, K1, sizeof(pte_t)); + uasm_i_beqz(&p, K0, 8); + + UASM_i_MFC0(&p, K0, C0_ENTRYLO0); /* load it in the delay slot*/ + UASM_i_MFC0(&p, K0, C0_ENTRYLO1); /* load it if ptr is odd */ + /* + * If the entryLo (now in K0) is valid (bit 1), RI or + * XI must have triggered it. + */ + uasm_i_andi(&p, K0, K0, 2); + uasm_il_bnez(&p, &r, K0, label_nopage_tlbl); + + uasm_l_tlbl_goaround1(&l, p); + /* Reload the PTE value */ + iPTE_LW(&p, K0, K1); + } build_make_valid(&p, &r, K0, K1); build_r4000_tlbchange_handler_tail(&p, &l, &r, K0, K1); @@ -1291,6 +1370,40 @@ static void __cpuinit build_r4000_tlb_load_handler(void) iPTE_LW(&p, K0, K1); build_pte_present(&p, &r, K0, K1, label_nopage_tlbl); build_tlb_probe_entry(&p); + + if (kernel_uses_smartmips_rixi) { + /* + * If the page is not _PAGE_VALID, RI or XI could not + * have triggered it. Skip the expensive test.. + */ + uasm_i_andi(&p, K0, K0, _PAGE_VALID); + uasm_il_beqz(&p, &r, K0, label_tlbl_goaround2); + uasm_i_nop(&p); + + uasm_i_tlbr(&p); + /* Examine entrylo 0 or 1 based on ptr. */ + uasm_i_andi(&p, K0, K1, sizeof(pte_t)); + uasm_i_beqz(&p, K0, 8); + + UASM_i_MFC0(&p, K0, C0_ENTRYLO0); /* load it in the delay slot*/ + UASM_i_MFC0(&p, K0, C0_ENTRYLO1); /* load it if ptr is odd */ + /* + * If the entryLo (now in K0) is valid (bit 1), RI or + * XI must have triggered it. + */ + uasm_i_andi(&p, K0, K0, 2); + uasm_il_beqz(&p, &r, K0, label_tlbl_goaround2); + /* Reload the PTE value */ + iPTE_LW(&p, K0, K1); + + /* + * We clobbered C0_PAGEMASK, restore it. On the other branch + * it is restored in build_huge_tlb_write_entry. + */ + build_restore_pagemask(&p, &r, K0, label_nopage_tlbl); + + uasm_l_tlbl_goaround2(&l, p); + } uasm_i_ori(&p, K0, K0, (_PAGE_ACCESSED | _PAGE_VALID)); build_huge_handler_tail(&p, &r, &l, K0, K1); #endif -- 1.6.2.5 From David.Daney@caviumnetworks.com Thu Feb 11 00:15:02 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 11 Feb 2010 00:15:07 +0100 (CET) Received: from mail3.caviumnetworks.com ([12.108.191.235]:15983 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492377Ab0BJXNw (ORCPT ); Thu, 11 Feb 2010 00:13:52 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Wed, 10 Feb 2010 15:13:58 -0800 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Wed, 10 Feb 2010 15:12:52 -0800 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Wed, 10 Feb 2010 15:12:52 -0800 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.3/8.14.2) with ESMTP id o1ANCnvJ005831; Wed, 10 Feb 2010 15:12:49 -0800 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.3/8.14.3/Submit) id o1ANCn86005830; Wed, 10 Feb 2010 15:12:49 -0800 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: David Daney Subject: [PATCH 3/6] MIPS: Add TLBR and ROTR to uasm. Date: Wed, 10 Feb 2010 15:12:46 -0800 Message-Id: <1265843569-5786-3-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.6.2.5 In-Reply-To: <4B733C71.8030304@caviumnetworks.com> References: <4B733C71.8030304@caviumnetworks.com> X-OriginalArrivalTime: 10 Feb 2010 23:12:52.0410 (UTC) FILETIME=[91FDC1A0:01CAAAA6] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25907 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips The soon to follow Read Inhibit/eXecute Inhibit patch needs TLBR and ROTR support in uasm. We also add a UASM_i_ROTR macro. Signed-off-by: David Daney --- arch/mips/include/asm/uasm.h | 4 ++++ arch/mips/mm/uasm.c | 9 +++++++-- 2 files changed, 11 insertions(+), 2 deletions(-) diff --git a/arch/mips/include/asm/uasm.h b/arch/mips/include/asm/uasm.h index 3d153ed..b99bd07 100644 --- a/arch/mips/include/asm/uasm.h +++ b/arch/mips/include/asm/uasm.h @@ -92,9 +92,11 @@ Ip_u2s3u1(_sd); Ip_u2u1u3(_sll); Ip_u2u1u3(_sra); Ip_u2u1u3(_srl); +Ip_u2u1u3(_rotr); Ip_u3u1u2(_subu); Ip_u2s3u1(_sw); Ip_0(_tlbp); +Ip_0(_tlbr); Ip_0(_tlbwi); Ip_0(_tlbwr); Ip_u3u1u2(_xor); @@ -129,6 +131,7 @@ static inline void __cpuinit uasm_l##lb(struct uasm_label **lab, u32 *addr) \ # define UASM_i_SLL(buf, rs, rt, sh) uasm_i_dsll(buf, rs, rt, sh) # define UASM_i_SRA(buf, rs, rt, sh) uasm_i_dsra(buf, rs, rt, sh) # define UASM_i_SRL(buf, rs, rt, sh) uasm_i_dsrl(buf, rs, rt, sh) +# define UASM_i_ROTR(buf, rs, rt, sh) uasm_i_drotr(buf, rs, rt, sh) # define UASM_i_MFC0(buf, rt, rd...) uasm_i_dmfc0(buf, rt, rd) # define UASM_i_MTC0(buf, rt, rd...) uasm_i_dmtc0(buf, rt, rd) # define UASM_i_ADDIU(buf, rs, rt, val) uasm_i_daddiu(buf, rs, rt, val) @@ -142,6 +145,7 @@ static inline void __cpuinit uasm_l##lb(struct uasm_label **lab, u32 *addr) \ # define UASM_i_SLL(buf, rs, rt, sh) uasm_i_sll(buf, rs, rt, sh) # define UASM_i_SRA(buf, rs, rt, sh) uasm_i_sra(buf, rs, rt, sh) # define UASM_i_SRL(buf, rs, rt, sh) uasm_i_srl(buf, rs, rt, sh) +# define UASM_i_ROTR(buf, rs, rt, sh) uasm_i_rotr(buf, rs, rt, sh) # define UASM_i_MFC0(buf, rt, rd...) uasm_i_mfc0(buf, rt, rd) # define UASM_i_MTC0(buf, rt, rd...) uasm_i_mtc0(buf, rt, rd) # define UASM_i_ADDIU(buf, rs, rt, val) uasm_i_addiu(buf, rs, rt, val) diff --git a/arch/mips/mm/uasm.c b/arch/mips/mm/uasm.c index e3ca0f7..1581e98 100644 --- a/arch/mips/mm/uasm.c +++ b/arch/mips/mm/uasm.c @@ -62,8 +62,9 @@ enum opcode { insn_dsrl32, insn_drotr, insn_dsubu, insn_eret, insn_j, insn_jal, insn_jr, insn_ld, insn_ll, insn_lld, insn_lui, insn_lw, insn_mfc0, insn_mtc0, insn_ori, insn_pref, insn_rfe, insn_sc, insn_scd, - insn_sd, insn_sll, insn_sra, insn_srl, insn_subu, insn_sw, - insn_tlbp, insn_tlbwi, insn_tlbwr, insn_xor, insn_xori, insn_dins + insn_sd, insn_sll, insn_sra, insn_srl, insn_rotr, insn_subu, insn_sw, + insn_tlbp, insn_tlbr, insn_tlbwi, insn_tlbwr, insn_xor, insn_xori, + insn_dins }; struct insn { @@ -125,9 +126,11 @@ static struct insn insn_table[] __cpuinitdata = { { insn_sll, M(spec_op, 0, 0, 0, 0, sll_op), RT | RD | RE }, { insn_sra, M(spec_op, 0, 0, 0, 0, sra_op), RT | RD | RE }, { insn_srl, M(spec_op, 0, 0, 0, 0, srl_op), RT | RD | RE }, + { insn_rotr, M(spec_op, 1, 0, 0, 0, srl_op), RT | RD | RE }, { insn_subu, M(spec_op, 0, 0, 0, 0, subu_op), RS | RT | RD }, { insn_sw, M(sw_op, 0, 0, 0, 0, 0), RS | RT | SIMM }, { insn_tlbp, M(cop0_op, cop_op, 0, 0, 0, tlbp_op), 0 }, + { insn_tlbr, M(cop0_op, cop_op, 0, 0, 0, tlbr_op), 0 }, { insn_tlbwi, M(cop0_op, cop_op, 0, 0, 0, tlbwi_op), 0 }, { insn_tlbwr, M(cop0_op, cop_op, 0, 0, 0, tlbwr_op), 0 }, { insn_xor, M(spec_op, 0, 0, 0, 0, xor_op), RS | RT | RD }, @@ -378,9 +381,11 @@ I_u2s3u1(_sd) I_u2u1u3(_sll) I_u2u1u3(_sra) I_u2u1u3(_srl) +I_u2u1u3(_rotr) I_u3u1u2(_subu) I_u2s3u1(_sw) I_0(_tlbp) +I_0(_tlbr) I_0(_tlbwi) I_0(_tlbwr) I_u3u1u2(_xor) -- 1.6.2.5 From David.Daney@caviumnetworks.com Thu Feb 11 00:15:25 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 11 Feb 2010 00:15:30 +0100 (CET) Received: from mail3.caviumnetworks.com ([12.108.191.235]:15984 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492380Ab0BJXNw (ORCPT ); Thu, 11 Feb 2010 00:13:52 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Wed, 10 Feb 2010 15:13:58 -0800 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Wed, 10 Feb 2010 15:12:52 -0800 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Wed, 10 Feb 2010 15:12:52 -0800 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.3/8.14.2) with ESMTP id o1ANCnkm005823; Wed, 10 Feb 2010 15:12:49 -0800 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.3/8.14.3/Submit) id o1ANCnuB005822; Wed, 10 Feb 2010 15:12:49 -0800 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: David Daney Subject: [PATCH 1/6] MIPS: Use 64-bit stores to c0_entrylo on 64-bit kernels. Date: Wed, 10 Feb 2010 15:12:44 -0800 Message-Id: <1265843569-5786-1-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.6.2.5 In-Reply-To: <4B733C71.8030304@caviumnetworks.com> References: <4B733C71.8030304@caviumnetworks.com> X-OriginalArrivalTime: 10 Feb 2010 23:12:52.0425 (UTC) FILETIME=[92000B90:01CAAAA6] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25908 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips 64-bit CPUs have 64-bit c0_entrylo{0,1} registers. We should use the 64-bit dmtc0 instruction to set them. This becomes important if we want to set the RI and XI bits present in some processors. Signed-off-by: David Daney --- arch/mips/mm/tlbex.c | 20 ++++++++++---------- 1 files changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index 2c68849..35431e1 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -460,14 +460,14 @@ static __cpuinit void build_huge_update_entries(u32 **p, uasm_i_lui(p, tmp, HPAGE_SIZE >> (7 + 16)); UASM_i_SRL(p, pte, pte, 6); /* convert to entrylo */ - uasm_i_mtc0(p, pte, C0_ENTRYLO0); /* load it */ + UASM_i_MTC0(p, pte, C0_ENTRYLO0); /* load it */ /* convert to entrylo1 */ if (small_sequence) UASM_i_ADDIU(p, pte, pte, HPAGE_SIZE >> 7); else UASM_i_ADDU(p, pte, pte, tmp); - uasm_i_mtc0(p, pte, C0_ENTRYLO1); /* load it */ + UASM_i_MTC0(p, pte, C0_ENTRYLO1); /* load it */ } static __cpuinit void build_huge_handler_tail(u32 **p, @@ -686,18 +686,18 @@ static void __cpuinit build_update_entries(u32 **p, unsigned int tmp, uasm_i_ld(p, tmp, 0, ptep); /* get even pte */ uasm_i_ld(p, ptep, sizeof(pte_t), ptep); /* get odd pte */ uasm_i_dsrl(p, tmp, tmp, 6); /* convert to entrylo0 */ - uasm_i_mtc0(p, tmp, C0_ENTRYLO0); /* load it */ + UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */ uasm_i_dsrl(p, ptep, ptep, 6); /* convert to entrylo1 */ - uasm_i_mtc0(p, ptep, C0_ENTRYLO1); /* load it */ + UASM_i_MTC0(p, ptep, C0_ENTRYLO1); /* load it */ } else { int pte_off_even = sizeof(pte_t) / 2; int pte_off_odd = pte_off_even + sizeof(pte_t); /* The pte entries are pre-shifted */ uasm_i_lw(p, tmp, pte_off_even, ptep); /* get even pte */ - uasm_i_mtc0(p, tmp, C0_ENTRYLO0); /* load it */ + UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */ uasm_i_lw(p, ptep, pte_off_odd, ptep); /* get odd pte */ - uasm_i_mtc0(p, ptep, C0_ENTRYLO1); /* load it */ + UASM_i_MTC0(p, ptep, C0_ENTRYLO1); /* load it */ } #else UASM_i_LW(p, tmp, 0, ptep); /* get even pte */ @@ -706,14 +706,14 @@ static void __cpuinit build_update_entries(u32 **p, unsigned int tmp, build_tlb_probe_entry(p); UASM_i_SRL(p, tmp, tmp, 6); /* convert to entrylo0 */ if (r4k_250MHZhwbug()) - uasm_i_mtc0(p, 0, C0_ENTRYLO0); - uasm_i_mtc0(p, tmp, C0_ENTRYLO0); /* load it */ + UASM_i_MTC0(p, 0, C0_ENTRYLO0); + UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */ UASM_i_SRL(p, ptep, ptep, 6); /* convert to entrylo1 */ if (r45k_bvahwbug()) uasm_i_mfc0(p, tmp, C0_INDEX); if (r4k_250MHZhwbug()) - uasm_i_mtc0(p, 0, C0_ENTRYLO1); - uasm_i_mtc0(p, ptep, C0_ENTRYLO1); /* load it */ + UASM_i_MTC0(p, 0, C0_ENTRYLO1); + UASM_i_MTC0(p, ptep, C0_ENTRYLO1); /* load it */ #endif } -- 1.6.2.5 From David.Daney@caviumnetworks.com Thu Feb 11 00:15:50 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 11 Feb 2010 00:15:54 +0100 (CET) Received: from mail3.caviumnetworks.com ([12.108.191.235]:15985 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492382Ab0BJXNx (ORCPT ); Thu, 11 Feb 2010 00:13:53 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Wed, 10 Feb 2010 15:13:58 -0800 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Wed, 10 Feb 2010 15:12:54 -0800 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Wed, 10 Feb 2010 15:12:54 -0800 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.3/8.14.2) with ESMTP id o1ANCoTU005843; Wed, 10 Feb 2010 15:12:50 -0800 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.3/8.14.3/Submit) id o1ANCogO005842; Wed, 10 Feb 2010 15:12:50 -0800 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: David Daney Subject: [PATCH 6/6] MIPS: Enable Read Inhibit/eXecute Inhibit for Octeon+ CPUs Date: Wed, 10 Feb 2010 15:12:49 -0800 Message-Id: <1265843569-5786-6-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.6.2.5 In-Reply-To: <4B733C71.8030304@caviumnetworks.com> References: <4B733C71.8030304@caviumnetworks.com> X-OriginalArrivalTime: 10 Feb 2010 23:12:54.0910 (UTC) FILETIME=[937B39E0:01CAAAA6] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25909 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Signed-off-by: David Daney --- .../asm/mach-cavium-octeon/cpu-feature-overrides.h | 3 +++ 1 files changed, 3 insertions(+), 0 deletions(-) diff --git a/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h index 425e708..bbf0540 100644 --- a/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h +++ b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h @@ -58,6 +58,9 @@ #define cpu_has_vint 0 #define cpu_has_veic 0 #define cpu_hwrena_impl_bits 0xc0000000 + +#define kernel_uses_smartmips_rixi (cpu_data[0].cputype == CPU_CAVIUM_OCTEON_PLUS) + #define ARCH_HAS_READ_CURRENT_TIMER 1 #define ARCH_HAS_IRQ_PER_CPU 1 #define ARCH_HAS_SPINLOCK_PREFETCH 1 -- 1.6.2.5 From ralf@linux-mips.org Thu Feb 11 00:56:54 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 11 Feb 2010 00:56:57 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:46245 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1492412Ab0BJX4y (ORCPT ); Thu, 11 Feb 2010 00:56:54 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id o1ANupEW007981; Thu, 11 Feb 2010 00:56:52 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id o1ANuoPG007979; Thu, 11 Feb 2010 00:56:50 +0100 Date: Thu, 11 Feb 2010 00:56:49 +0100 From: Ralf Baechle To: David Daney Cc: linux-mips Subject: Re: [PATCH 0/6] MIPS Read Inhibit/eXecute Inhibit support (v2). Message-ID: <20100210235649.GA7975@linux-mips.org> References: <4B733C71.8030304@caviumnetworks.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <4B733C71.8030304@caviumnetworks.com> User-Agent: Mutt/1.5.20 (2009-08-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25910 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Wed, Feb 10, 2010 at 03:08:33PM -0800, David Daney wrote: > This patch set adds execute and read inhibit support. By default glibc > based tool chains will create mappings for data areas of a program and > shared libraries with PROT_EXEC cleared. With this patch applied, a > SIGSEGV is correctly sent if an attempt is made to execute from data > areas. > > The first three patch just make a few tweaks in preperation for the > main body of the patch in 4/6. The last two turn on the feature for > some Octeon CPUs. > > I will reply with the six patches. > > David Daney (6): > MIPS: Use 64-bit stores to c0_entrylo on 64-bit kernels. > MIPS: Add accessor functions and bit definitions for c0_PageGrain > MIPS: Add TLBR and ROTR to uasm. > MIPS: Implement Read Inhibit/eXecute Inhibit > MIPS: Give Octeon+ CPUs their own cputype. > MIPS: Enable Read Inhibit/eXecute Inhibit for Octeon+ CPUs Hangs on IP27 after [...] Calibrating delay loop... 178.17 BogoMIPS (lpj=89088) Dentry cache hash table entries: 262144 (order: 9, 2097152 bytes) Ralf From David.Daney@caviumnetworks.com Thu Feb 11 01:53:28 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 11 Feb 2010 01:53:31 +0100 (CET) Received: from mail3.caviumnetworks.com ([12.108.191.235]:17808 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492265Ab0BKAx2 (ORCPT ); Thu, 11 Feb 2010 01:53:28 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Wed, 10 Feb 2010 16:53:24 -0800 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Wed, 10 Feb 2010 16:53:11 -0800 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Wed, 10 Feb 2010 16:53:11 -0800 Message-ID: <4B7354F5.8080002@caviumnetworks.com> Date: Wed, 10 Feb 2010 16:53:09 -0800 From: David Daney User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.7) Gecko/20100120 Fedora/3.0.1-1.fc11 Thunderbird/3.0.1 MIME-Version: 1.0 To: Ralf Baechle CC: linux-mips Subject: Re: [PATCH 0/6] MIPS Read Inhibit/eXecute Inhibit support (v2). References: <4B733C71.8030304@caviumnetworks.com> <20100210235649.GA7975@linux-mips.org> In-Reply-To: <20100210235649.GA7975@linux-mips.org> Content-Type: multipart/mixed; boundary="------------020709000000020608050108" X-OriginalArrivalTime: 11 Feb 2010 00:53:11.0401 (UTC) FILETIME=[9596E590:01CAAAB4] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25911 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips This is a multi-part message in MIME format. --------------020709000000020608050108 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit On 02/10/2010 03:56 PM, Ralf Baechle wrote: > On Wed, Feb 10, 2010 at 03:08:33PM -0800, David Daney wrote: > >> This patch set adds execute and read inhibit support. By default glibc >> based tool chains will create mappings for data areas of a program and >> shared libraries with PROT_EXEC cleared. With this patch applied, a >> SIGSEGV is correctly sent if an attempt is made to execute from data >> areas. >> >> The first three patch just make a few tweaks in preperation for the >> main body of the patch in 4/6. The last two turn on the feature for >> some Octeon CPUs. >> >> I will reply with the six patches. >> >> David Daney (6): >> MIPS: Use 64-bit stores to c0_entrylo on 64-bit kernels. >> MIPS: Add accessor functions and bit definitions for c0_PageGrain >> MIPS: Add TLBR and ROTR to uasm. >> MIPS: Implement Read Inhibit/eXecute Inhibit >> MIPS: Give Octeon+ CPUs their own cputype. >> MIPS: Enable Read Inhibit/eXecute Inhibit for Octeon+ CPUs > > Hangs on IP27 after > > [...] > Calibrating delay loop... 178.17 BogoMIPS (lpj=89088) > Dentry cache hash table entries: 262144 (order: 9, 2097152 bytes) > Try the attached patch. David Daney --------------020709000000020608050108 Content-Type: text/plain; name="rixi-ralf.patch" Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename="rixi-ralf.patch" diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index ec60bd5..5ea0af8 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -749,11 +749,11 @@ static void __cpuinit build_update_entries(u32 **p, unsigned int tmp, UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */ UASM_i_ROTR(p, ptep, ptep, ilog2(_PAGE_GLOBAL) - ilog2(_PAGE_NO_EXEC)); } else { - UASM_i_SRL(p, tmp, tmp, 6); /* convert to entrylo0 */ + UASM_i_SRL(p, tmp, tmp, ilog2(_PAGE_GLOBAL)); /* convert to entrylo0 */ if (r4k_250MHZhwbug()) UASM_i_MTC0(p, 0, C0_ENTRYLO0); UASM_i_MTC0(p, tmp, C0_ENTRYLO0); /* load it */ - UASM_i_SRL(p, ptep, ptep, 6); /* convert to entrylo1 */ + UASM_i_SRL(p, ptep, ptep, ilog2(_PAGE_GLOBAL)); /* convert to entrylo1 */ if (r45k_bvahwbug()) uasm_i_mfc0(p, tmp, C0_INDEX); } --------------020709000000020608050108-- From yuasa.linux@gmail.com Fri Feb 12 13:37:39 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 12 Feb 2010 13:37:43 +0100 (CET) Received: from mail-yw0-f188.google.com ([209.85.211.188]:56668 "EHLO mail-yw0-f188.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491028Ab0BLMhj (ORCPT ); Fri, 12 Feb 2010 13:37:39 +0100 Received: by ywh26 with SMTP id 26so2126051ywh.26 for ; Fri, 12 Feb 2010 04:37:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:sender:date:from:to:cc :subject:message-id:x-mailer:mime-version:content-type :content-transfer-encoding; bh=vVqQH+LfNmuiz1nIFKXMHoj83gtCVsSzg4xi6J/cBcA=; b=Jyp8gljxBPBshA4sY1Ijxs7pzx0v37/7inuh/lLYkNxYiw9imugIg15TzjSWdLi/YL tayFeEr4p9n8VbI0fPBJedQsoEkrJ8aHCKmVgwuIHiCERQeuj4vr1ru4fqI6ESC22Zoi 8CHAbcsPv5zv1D2kTehiV8z+uAs99GIxA+cow= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:date:from:to:cc:subject:message-id:x-mailer:mime-version :content-type:content-transfer-encoding; b=PEBub0P4ef1QU23fGhGqaMiwy7w+/I2jC5/HPjyPfPMpZBLkLLQWI28laivJUaL/cG aUjZm9lsHXX99y6WJGoAIDGEvDU5TDTmbxXSU9BfafghzIXua67ZDxTRp7AnyZVfGoi6 UQWLskXluL6uR4+PHvaRd9zcAii7V1w877tw8= Received: by 10.101.10.2 with SMTP id n2mr1795161ani.189.1265978252473; Fri, 12 Feb 2010 04:37:32 -0800 (PST) Received: from ypsilon.skybright.jp (sannin29006.nirai.ne.jp [203.160.29.6]) by mx.google.com with ESMTPS id 14sm2431915gxk.2.2010.02.12.04.37.29 (version=TLSv1/SSLv3 cipher=RC4-MD5); Fri, 12 Feb 2010 04:37:31 -0800 (PST) Date: Fri, 12 Feb 2010 21:27:59 +0900 From: Yoichi Yuasa To: Ralf Baechle Cc: yuasa@linux-mips.org, linux-mips Subject: [PATCH -queue 1/4] MIPS: use generic current.h Message-Id: <20100212212759.76f1b52a.yuasa@linux-mips.org> X-Mailer: Sylpheed 2.7.1 (GTK+ 2.16.6; i686-pc-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25912 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: yuasa@linux-mips.org Precedence: bulk X-list: linux-mips Signed-off-by: Yoichi Yuasa --- arch/mips/include/asm/current.h | 24 +----------------------- 1 files changed, 1 insertions(+), 23 deletions(-) diff --git a/arch/mips/include/asm/current.h b/arch/mips/include/asm/current.h index 559db66..4c51401 100644 --- a/arch/mips/include/asm/current.h +++ b/arch/mips/include/asm/current.h @@ -1,23 +1 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1998, 2002 Ralf Baechle - * Copyright (C) 1999 Silicon Graphics, Inc. - */ -#ifndef _ASM_CURRENT_H -#define _ASM_CURRENT_H - -#include - -struct task_struct; - -static inline struct task_struct * get_current(void) -{ - return current_thread_info()->task; -} - -#define current get_current() - -#endif /* _ASM_CURRENT_H */ +#include -- 1.6.6.2 From yuasa.linux@gmail.com Fri Feb 12 13:38:01 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 12 Feb 2010 13:38:08 +0100 (CET) Received: from mail-yx0-f194.google.com ([209.85.210.194]:37427 "EHLO mail-yx0-f194.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491085Ab0BLMhp (ORCPT ); Fri, 12 Feb 2010 13:37:45 +0100 Received: by yxe32 with SMTP id 32so2842420yxe.0 for ; Fri, 12 Feb 2010 04:37:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:sender:date:from:to:cc :subject:message-id:in-reply-to:references:x-mailer:mime-version :content-type:content-transfer-encoding; bh=+uwruMkFH3xK1AxqG9rhuCJc/azYBMpuGxV54/1Ycbc=; b=vvPSwx7lRCf7zesOGmP5StViiDQWCS7IeMPQHlWFOIj8+e73pvZFoU+pk/Tkjb7+7k p/ilvDSHWA/07XpKVFxa5Ut94lhjz+cSnRyR0WMtDDZk891TD463jnn1MrEkuKTYGga0 XGFpIgppqbUNsG0DbnEXNybp5ZAXi/y/A0Kfc= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:date:from:to:cc:subject:message-id:in-reply-to:references :x-mailer:mime-version:content-type:content-transfer-encoding; b=eDLJVz37TXpr5RqpUNmZkdyxn0PyDGZN+iART5SmAUHMPjclxWH2LcNLc82iBZ/ZYX AmpzTtYnQPLIMC6WkZBlWj835MybyakMDgkQqwKg7uXMt12A2wncfuIOgCQVPy+rlvbN DY4cfGpO90J8payqwa60vjdCafBGkVYachsqw= Received: by 10.100.25.14 with SMTP id 14mr1835067any.158.1265978257066; Fri, 12 Feb 2010 04:37:37 -0800 (PST) Received: from ypsilon.skybright.jp (sannin29006.nirai.ne.jp [203.160.29.6]) by mx.google.com with ESMTPS id 15sm2410195gxk.8.2010.02.12.04.37.35 (version=TLSv1/SSLv3 cipher=RC4-MD5); Fri, 12 Feb 2010 04:37:36 -0800 (PST) Date: Fri, 12 Feb 2010 21:29:14 +0900 From: Yoichi Yuasa To: Ralf Baechle Cc: yuasa@linux-mips.org, linux-mips Subject: [PATCH -queue 2/4] MIPS: use generic parport.h Message-Id: <20100212212914.f04a046b.yuasa@linux-mips.org> In-Reply-To: <20100212212759.76f1b52a.yuasa@linux-mips.org> References: <20100212212759.76f1b52a.yuasa@linux-mips.org> X-Mailer: Sylpheed 2.7.1 (GTK+ 2.16.6; i686-pc-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25913 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: yuasa@linux-mips.org Precedence: bulk X-list: linux-mips Signed-off-by: Yoichi Yuasa --- arch/mips/include/asm/parport.h | 16 +--------------- 1 files changed, 1 insertions(+), 15 deletions(-) diff --git a/arch/mips/include/asm/parport.h b/arch/mips/include/asm/parport.h index f526568..cf252af 100644 --- a/arch/mips/include/asm/parport.h +++ b/arch/mips/include/asm/parport.h @@ -1,15 +1 @@ -/* - * Copyright (C) 1999, 2000 Tim Waugh - * - * This file should only be included by drivers/parport/parport_pc.c. - */ -#ifndef _ASM_PARPORT_H -#define _ASM_PARPORT_H - -static int __devinit parport_pc_find_isa_ports(int autoirq, int autodma); -static int __devinit parport_pc_find_nonpci_ports(int autoirq, int autodma) -{ - return parport_pc_find_isa_ports(autoirq, autodma); -} - -#endif /* _ASM_PARPORT_H */ +#include -- 1.6.6.2 From yuasa.linux@gmail.com Fri Feb 12 13:38:26 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 12 Feb 2010 13:38:32 +0100 (CET) Received: from mail-yw0-f188.google.com ([209.85.211.188]:56668 "EHLO mail-yw0-f188.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491087Ab0BLMhr (ORCPT ); Fri, 12 Feb 2010 13:37:47 +0100 Received: by mail-yw0-f188.google.com with SMTP id 26so2126051ywh.26 for ; Fri, 12 Feb 2010 04:37:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:sender:date:from:to:cc :subject:message-id:in-reply-to:references:x-mailer:mime-version :content-type:content-transfer-encoding; bh=5IIQkXEjvf8hvlfLIJZzTkDKvYcwK/FaENjrvLoAJhc=; b=Yw4JN467CkatHaQgcwhM13C1qUvosHTZ+dDsS3C7VNnht06g433hEcVaRf2YXnZNaR cgO0Iwf7JM9XDjfgCex32MTIFhe3xd0LScOZUTX10DbD2tHA3ozd2ywfAjVg/iTMgJ1O BWNMMjy1udakCl0/RjvX2rox0NOwfzVHmwSIc= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:date:from:to:cc:subject:message-id:in-reply-to:references :x-mailer:mime-version:content-type:content-transfer-encoding; b=fZPF7txkDh5iOO/gOArX1nit6eP/TwnOkDQVlYQYO4UppaDVLXNp5QVrutqepcw5K2 TBD9iduZMYSYRwaO0Qzj9jjBim9/mDOuLBnr4+4HWew3OT9jbJjp2cTbsnH8K7Tr52Xf 7NiKw3B0aQ5K8VU3qglcEKFQdeXqQwewrZAKU= Received: by 10.101.7.23 with SMTP id k23mr1939057ani.36.1265978266957; Fri, 12 Feb 2010 04:37:46 -0800 (PST) Received: from ypsilon.skybright.jp (sannin29006.nirai.ne.jp [203.160.29.6]) by mx.google.com with ESMTPS id 14sm2418693gxk.14.2010.02.12.04.37.44 (version=TLSv1/SSLv3 cipher=RC4-MD5); Fri, 12 Feb 2010 04:37:46 -0800 (PST) Date: Fri, 12 Feb 2010 21:35:04 +0900 From: Yoichi Yuasa To: Ralf Baechle Cc: yuasa@linux-mips.org, linux-mips Subject: [PATCH -queue 4/4] MIPS: use generic ucontext.h Message-Id: <20100212213504.366b7029.yuasa@linux-mips.org> In-Reply-To: <20100212213356.198e723b.yuasa@linux-mips.org> References: <20100212212759.76f1b52a.yuasa@linux-mips.org> <20100212212914.f04a046b.yuasa@linux-mips.org> <20100212213356.198e723b.yuasa@linux-mips.org> X-Mailer: Sylpheed 2.7.1 (GTK+ 2.16.6; i686-pc-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25914 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: yuasa@linux-mips.org Precedence: bulk X-list: linux-mips Signed-off-by: Yoichi Yuasa --- arch/mips/include/asm/ucontext.h | 22 +--------------------- 1 files changed, 1 insertions(+), 21 deletions(-) diff --git a/arch/mips/include/asm/ucontext.h b/arch/mips/include/asm/ucontext.h index 8a4b20e..9bc07b9 100644 --- a/arch/mips/include/asm/ucontext.h +++ b/arch/mips/include/asm/ucontext.h @@ -1,21 +1 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Low level exception handling - * - * Copyright (C) 1998, 1999 by Ralf Baechle - */ -#ifndef _ASM_UCONTEXT_H -#define _ASM_UCONTEXT_H - -struct ucontext { - unsigned long uc_flags; - struct ucontext *uc_link; - stack_t uc_stack; - struct sigcontext uc_mcontext; - sigset_t uc_sigmask; /* mask last for extensibility */ -}; - -#endif /* _ASM_UCONTEXT_H */ +#include -- 1.6.6.2 From yuasa.linux@gmail.com Fri Feb 12 13:38:50 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 12 Feb 2010 13:38:55 +0100 (CET) Received: from mail-gx0-f214.google.com ([209.85.217.214]:49933 "EHLO mail-gx0-f214.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491089Ab0BLMhs (ORCPT ); Fri, 12 Feb 2010 13:37:48 +0100 Received: by gxk6 with SMTP id 6so1826651gxk.4 for ; Fri, 12 Feb 2010 04:37:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:sender:date:from:to:cc :subject:message-id:in-reply-to:references:x-mailer:mime-version :content-type:content-transfer-encoding; bh=loSLtQdHIcOqIe9vm12RozVzPsLRDHzKlV3orTOV+gw=; b=pFx7Kf0Jmo61cMJ8BhJFCBJtXRRgr0f1vl45heeUWRQMevdxLpZEsZ5jfBFHhTasdj 8rdXGtN0Wy58PGxRR4Z3wlCUynMdKJxctRTgQ21n5nHkb4xpFtHSAwAbDdQYH50PeSfj 0gVGOPfpyB243bHf4iPatefz6riw32ELG0gcM= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:date:from:to:cc:subject:message-id:in-reply-to:references :x-mailer:mime-version:content-type:content-transfer-encoding; b=PrtxiM1NEHocYpWQAso/h0t5UhPVMi9KmI3HCwgOgRWQAr39KHIlnWstvJt4uQGQeR IgdJIpVT/8JwW/Ltpmvx4D43LgyuuK+PiXp8TcKXhh7BaZcEgEIc+EcMiBoqVEsf7QM8 bm8IM7BF2aXRTeP+25xZJ1tSmmIhbC01pbq3g= Received: by 10.101.7.29 with SMTP id k29mr1954461ani.12.1265978261739; Fri, 12 Feb 2010 04:37:41 -0800 (PST) Received: from ypsilon.skybright.jp (sannin29006.nirai.ne.jp [203.160.29.6]) by mx.google.com with ESMTPS id 16sm2413492gxk.15.2010.02.12.04.37.39 (version=TLSv1/SSLv3 cipher=RC4-MD5); Fri, 12 Feb 2010 04:37:41 -0800 (PST) Date: Fri, 12 Feb 2010 21:33:56 +0900 From: Yoichi Yuasa To: Ralf Baechle Cc: yuasa@linux-mips.org, linux-mips Subject: [PATCH -queue 3/4] MIPS: use generic serial.h Message-Id: <20100212213356.198e723b.yuasa@linux-mips.org> In-Reply-To: <20100212212914.f04a046b.yuasa@linux-mips.org> References: <20100212212759.76f1b52a.yuasa@linux-mips.org> <20100212212914.f04a046b.yuasa@linux-mips.org> X-Mailer: Sylpheed 2.7.1 (GTK+ 2.16.6; i686-pc-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25915 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: yuasa@linux-mips.org Precedence: bulk X-list: linux-mips Signed-off-by: Yoichi Yuasa --- arch/mips/include/asm/serial.h | 23 +---------------------- 1 files changed, 1 insertions(+), 22 deletions(-) diff --git a/arch/mips/include/asm/serial.h b/arch/mips/include/asm/serial.h index c07ebd8..a0cb0ca 100644 --- a/arch/mips/include/asm/serial.h +++ b/arch/mips/include/asm/serial.h @@ -1,22 +1 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1999 by Ralf Baechle - * Copyright (C) 1999, 2000 Silicon Graphics, Inc. - */ -#ifndef _ASM_SERIAL_H -#define _ASM_SERIAL_H - - -/* - * This assumes you have a 1.8432 MHz clock for your UART. - * - * It'd be nice if someone built a serial card with a 24.576 MHz - * clock, since the 16550A is capable of handling a top speed of 1.5 - * megabits/second; but this requires the faster clock. - */ -#define BASE_BAUD (1843200 / 16) - -#endif /* _ASM_SERIAL_H */ +#include -- 1.6.6.2 From manuel.lauss@googlemail.com Sun Feb 14 21:16:43 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 14 Feb 2010 21:16:47 +0100 (CET) Received: from mail-fx0-f224.google.com ([209.85.220.224]:59654 "EHLO mail-fx0-f224.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491925Ab0BNUQn (ORCPT ); Sun, 14 Feb 2010 21:16:43 +0100 Received: by fxm24 with SMTP id 24so4367317fxm.0 for ; Sun, 14 Feb 2010 12:16:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=domainkey-signature:mime-version:received:in-reply-to:references :date:message-id:subject:from:to:cc:content-type; bh=ACDiICNnozgUrUucR3zs1M4OF8MADs+lKC2SlRPX63Q=; b=VqHKavBCsPPYRbjLsYNxR1j4OEe3NMaAKqOmdDmprxGuZft+uVC0l/wYdvWgHuFKBo 63gOgSnYCkRBAGPgWHkcDo7/EM9lV2galwjJb1/eu6vjK3DTQOwn0ybiau3UfLgvbrf6 4+zR14O3Bf40mQJdm9NF1hgI2OjZ387MoA58M= DomainKey-Signature: a=rsa-sha1; c=nofws; d=googlemail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type; b=mQgv7A+F+i9XwbjWLENmhiUVS3+euClDioP2poH06iG5AI59JrKmVB3Q0pbZ4p/tOR 5CcydhLHOnrTgUqh/N1VI0aj4k59ciC6FWPcE06og99EaYyrr79DBC9f8Q773jdfb7KU SnAy3K8bmVg9zkSbBsqdM0puDPWXYPc2AtHhk= MIME-Version: 1.0 Received: by 10.223.7.69 with SMTP id c5mr4948085fac.14.1266178596578; Sun, 14 Feb 2010 12:16:36 -0800 (PST) In-Reply-To: <1265843569-5786-4-git-send-email-ddaney@caviumnetworks.com> References: <4B733C71.8030304@caviumnetworks.com> <1265843569-5786-4-git-send-email-ddaney@caviumnetworks.com> Date: Sun, 14 Feb 2010 21:16:36 +0100 Message-ID: Subject: Re: [PATCH 4/6] MIPS: Implement Read Inhibit/eXecute Inhibit From: Manuel Lauss To: David Daney Cc: linux-mips@linux-mips.org, ralf@linux-mips.org Content-Type: text/plain; charset=ISO-8859-1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25916 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips Hi David, this patch breaks my Alchemy builds: Using /mnt/data/_home/mano/db1200/kernel/linux-2.6.git as source for kernel GEN /mnt/data/_home/mano/db1200/kernel/kbuild-linux-2.6.git/Makefile CHK include/linux/version.h CHK include/generated/utsrelease.h UPD include/generated/utsrelease.h CC arch/mips/kernel/asm-offsets.s In file included from /mnt/data/_home/mano/db1200/kernel/linux-2.6.git/arch/mips/include/asm/io.h:25, from /mnt/data/_home/mano/db1200/kernel/linux-2.6.git/arch/mips/include/asm/page.h:46, from /mnt/data/_home/mano/db1200/kernel/linux-2.6.git/include/linux/mm_types.h:15, from /mnt/data/_home/mano/db1200/kernel/linux-2.6.git/include/linux/sched.h:63, from /mnt/data/_home/mano/db1200/kernel/linux-2.6.git/arch/mips/kernel/asm-offsets.c:13: /mnt/data/_home/mano/db1200/kernel/linux-2.6.git/arch/mips/include/asm/pgtable-bits.h: In function 'pte_to_entrylo': /mnt/data/_home/mano/db1200/kernel/linux-2.6.git/arch/mips/include/asm/pgtable-bits.h:146: error: '_PAGE_NO_READ_SHIFT' undeclared (first use in this function) /mnt/data/_home/mano/db1200/kernel/linux-2.6.git/arch/mips/include/asm/pgtable-bits.h:146: error: (Each undeclared identifier is reported only once /mnt/data/_home/mano/db1200/kernel/linux-2.6.git/arch/mips/include/asm/pgtable-bits.h:146: error: for each function it appears in.) /mnt/data/_home/mano/db1200/kernel/linux-2.6.git/arch/mips/include/asm/pgtable-bits.h:155: error: '_PAGE_GLOBAL_SHIFT' undeclared (first use in this function) /mnt/data/_home/mano/db1200/kernel/linux-2.6.git/arch/mips/include/asm/pgtable-bits.h:156: error: '_PAGE_NO_EXEC' undeclared (first use in this function) /mnt/data/_home/mano/db1200/kernel/linux-2.6.git/arch/mips/include/asm/pgtable-bits.h:156: error: '_PAGE_NO_READ' undeclared (first use in this function) In file included from /mnt/data/_home/mano/db1200/kernel/linux-2.6.git/include/linux/mm.h:39, from /mnt/data/_home/mano/db1200/kernel/linux-2.6.git/arch/mips/kernel/asm-offsets.c:14: /mnt/data/_home/mano/db1200/kernel/linux-2.6.git/arch/mips/include/asm/pgtable.h: In function 'pte_modify': /mnt/data/_home/mano/db1200/kernel/linux-2.6.git/arch/mips/include/asm/pgtable.h:351: error: '_PFN_MASK' undeclared (first use in this function) make[2]: *** [arch/mips/kernel/asm-offsets.s] Error 1 make[1]: *** [prepare0] Error 2 make: *** [sub-make] Error 2 Thanks! Manuel Lauss From david.s.daney@gmail.com Mon Feb 15 02:18:04 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 15 Feb 2010 02:18:08 +0100 (CET) Received: from mail-yw0-f187.google.com ([209.85.211.187]:58805 "EHLO mail-yw0-f187.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492046Ab0BOBSE (ORCPT ); Mon, 15 Feb 2010 02:18:04 +0100 Received: by ywh17 with SMTP id 17so4120695ywh.23 for ; Sun, 14 Feb 2010 17:17:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:message-id:date:from :user-agent:mime-version:to:cc:subject:references:in-reply-to :content-type:content-transfer-encoding; bh=pSVCPE7dT9pQpZgn2fqnpAL4DZdvvKJQ7pWK1YHlYHY=; b=rfhHJB4OKHn8GbIkjIo25FbRntkWoL+s4deBJyyazlrNqaTkOChf13kiJS9PMGwyMn qvtmdUClojnoj77EzOCGPc7Py7nbiab9zycyur2M798UfrUUQf3KJRDcDMoB7uYeXN9Z Iv970fixmSX0MMg+QhwoCUWHn2rQG0I1DB04s= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=message-id:date:from:user-agent:mime-version:to:cc:subject :references:in-reply-to:content-type:content-transfer-encoding; b=hZGUqO1pybmFPWZn7SKjF5nBdh3eY7Kql08LxoHWW9xkBfpiUHwB7CjCZIvcZLCRBj iJlYoB8P2k9xHYXIp0h8P6cx47reC4AFq6Nei5kHkuafUKtHJzp6DRMANP2DUh3lvOGk ql2oHLDSyVwioFbZIUAq4pL5BF7iUTIANCALs= Received: by 10.151.92.5 with SMTP id u5mr1323107ybl.114.1266196677559; Sun, 14 Feb 2010 17:17:57 -0800 (PST) Received: from dd_xps.caveonetworks.com (adsl-67-124-151-61.dsl.pltn13.pacbell.net [67.124.151.61]) by mx.google.com with ESMTPS id 9sm2138027yxf.41.2010.02.14.17.17.55 (version=TLSv1/SSLv3 cipher=RC4-MD5); Sun, 14 Feb 2010 17:17:56 -0800 (PST) Message-ID: <4B78A0C1.1070509@gmail.com> Date: Sun, 14 Feb 2010 17:17:53 -0800 From: David Daney User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.7) Gecko/20100120 Fedora/3.0.1-1.fc11 Thunderbird/3.0.1 MIME-Version: 1.0 To: Manuel Lauss CC: David Daney , linux-mips@linux-mips.org, ralf@linux-mips.org Subject: Re: [PATCH 4/6] MIPS: Implement Read Inhibit/eXecute Inhibit References: <4B733C71.8030304@caviumnetworks.com> <1265843569-5786-4-git-send-email-ddaney@caviumnetworks.com> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25917 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: david.s.daney@gmail.com Precedence: bulk X-list: linux-mips On 02/14/2010 12:16 PM, Manuel Lauss wrote: > Hi David, > > this patch breaks my Alchemy builds: > > Using /mnt/data/_home/mano/db1200/kernel/linux-2.6.git as source for kernel > GEN /mnt/data/_home/mano/db1200/kernel/kbuild-linux-2.6.git/Makefile > CHK include/linux/version.h > CHK include/generated/utsrelease.h > UPD include/generated/utsrelease.h > CC arch/mips/kernel/asm-offsets.s > In file included from > /mnt/data/_home/mano/db1200/kernel/linux-2.6.git/arch/mips/include/asm/io.h:25, > from > /mnt/data/_home/mano/db1200/kernel/linux-2.6.git/arch/mips/include/asm/page.h:46, > from > /mnt/data/_home/mano/db1200/kernel/linux-2.6.git/include/linux/mm_types.h:15, > from > /mnt/data/_home/mano/db1200/kernel/linux-2.6.git/include/linux/sched.h:63, > from > /mnt/data/_home/mano/db1200/kernel/linux-2.6.git/arch/mips/kernel/asm-offsets.c:13: > /mnt/data/_home/mano/db1200/kernel/linux-2.6.git/arch/mips/include/asm/pgtable-bits.h: > In function 'pte_to_entrylo': > /mnt/data/_home/mano/db1200/kernel/linux-2.6.git/arch/mips/include/asm/pgtable-bits.h:146: > error: '_PAGE_NO_READ_SHIFT' undeclared (first use in this function) > /mnt/data/_home/mano/db1200/kernel/linux-2.6.git/arch/mips/include/asm/pgtable-bits.h:146: > error: (Each undeclared identifier is reported only once > /mnt/data/_home/mano/db1200/kernel/linux-2.6.git/arch/mips/include/asm/pgtable-bits.h:146: > error: for each function it appears in.) > /mnt/data/_home/mano/db1200/kernel/linux-2.6.git/arch/mips/include/asm/pgtable-bits.h:155: > error: '_PAGE_GLOBAL_SHIFT' undeclared (first use in this function) > /mnt/data/_home/mano/db1200/kernel/linux-2.6.git/arch/mips/include/asm/pgtable-bits.h:156: > error: '_PAGE_NO_EXEC' undeclared (first use in this function) > /mnt/data/_home/mano/db1200/kernel/linux-2.6.git/arch/mips/include/asm/pgtable-bits.h:156: > error: '_PAGE_NO_READ' undeclared (first use in this function) > In file included from > /mnt/data/_home/mano/db1200/kernel/linux-2.6.git/include/linux/mm.h:39, > from > /mnt/data/_home/mano/db1200/kernel/linux-2.6.git/arch/mips/kernel/asm-offsets.c:14: > /mnt/data/_home/mano/db1200/kernel/linux-2.6.git/arch/mips/include/asm/pgtable.h: > In function 'pte_modify': > /mnt/data/_home/mano/db1200/kernel/linux-2.6.git/arch/mips/include/asm/pgtable.h:351: > error: '_PFN_MASK' undeclared (first use in this function) > make[2]: *** [arch/mips/kernel/asm-offsets.s] Error 1 > make[1]: *** [prepare0] Error 2 > make: *** [sub-make] Error 2 > Whoops! I will endeavor to fix this. Thanks for testing, David Daney From david.s.daney@gmail.com Mon Feb 15 03:08:34 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 15 Feb 2010 03:08:37 +0100 (CET) Received: from mail-yx0-f194.google.com ([209.85.210.194]:52798 "EHLO mail-yx0-f194.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492125Ab0BOCIe (ORCPT ); Mon, 15 Feb 2010 03:08:34 +0100 Received: by yxe32 with SMTP id 32so4281054yxe.0 for ; Sun, 14 Feb 2010 18:08:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:message-id:date:from :user-agent:mime-version:to:cc:subject:references:in-reply-to :content-type; bh=joZl54JJ4ilC+2KWc/1VE3n+yPOrZTm45AaVcipozto=; b=arwOhkDbWAl0HCyo9fsuIpBqw514GwMLh4kETMmXRkSitmo6XNKiFCIzHTRXABw15W oXA8lcfp1UPchSosZXlxHg5nrmeUH4M7WUVUqEyFipaYuqDsdPwqxUJb5r7E+9bEP9in lxteLIev/K6owuM0kHnxFRAXj2fDtouVId44o= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=message-id:date:from:user-agent:mime-version:to:cc:subject :references:in-reply-to:content-type; b=KoZm69duqP8Nf5CQfjPR1umZYqsdwbkTbOba6rJDysbg1xkUx101FoScvJce1YSmTF GOdsmZVEABU2rRPbdEJy61wC/NX+oYtH+nCeC7zFHZr0dfbHTBZSiRNcL8BZSiTy6fXK K5HGX5pY9NyyrfsahpyC8Z9Yx15pD36Au/GhQ= Received: by 10.150.175.1 with SMTP id x1mr2906899ybe.37.1266199707063; Sun, 14 Feb 2010 18:08:27 -0800 (PST) Received: from dd_xps.caveonetworks.com (adsl-67-124-151-61.dsl.pltn13.pacbell.net [67.124.151.61]) by mx.google.com with ESMTPS id 15sm4113943gxk.0.2010.02.14.18.08.25 (version=TLSv1/SSLv3 cipher=RC4-MD5); Sun, 14 Feb 2010 18:08:26 -0800 (PST) Message-ID: <4B78AC97.8030404@gmail.com> Date: Sun, 14 Feb 2010 18:08:23 -0800 From: David Daney User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.7) Gecko/20100120 Fedora/3.0.1-1.fc11 Thunderbird/3.0.1 MIME-Version: 1.0 To: Manuel Lauss CC: David Daney , linux-mips@linux-mips.org, ralf@linux-mips.org Subject: Re: [PATCH 4/6] MIPS: Implement Read Inhibit/eXecute Inhibit References: <4B733C71.8030304@caviumnetworks.com> <1265843569-5786-4-git-send-email-ddaney@caviumnetworks.com> <4B78A0C1.1070509@gmail.com> In-Reply-To: <4B78A0C1.1070509@gmail.com> Content-Type: multipart/mixed; boundary="------------050708080304060801080702" Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25918 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: david.s.daney@gmail.com Precedence: bulk X-list: linux-mips This is a multi-part message in MIME format. --------------050708080304060801080702 Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 8bit On 02/14/2010 05:17 PM, David Daney wrote: > On 02/14/2010 12:16 PM, Manuel Lauss wrote: >> Hi David, >> >> this patch breaks my Alchemy builds: >> >> Using /mnt/data/_home/mano/db1200/kernel/linux-2.6.git as source for >> kernel >> GEN /mnt/data/_home/mano/db1200/kernel/kbuild-linux-2.6.git/Makefile >> CHK include/linux/version.h >> CHK include/generated/utsrelease.h >> UPD include/generated/utsrelease.h >> CC arch/mips/kernel/asm-offsets.s >> In file included from >> /mnt/data/_home/mano/db1200/kernel/linux-2.6.git/arch/mips/include/asm/io.h:25, >> >> from >> /mnt/data/_home/mano/db1200/kernel/linux-2.6.git/arch/mips/include/asm/page.h:46, >> >> from >> /mnt/data/_home/mano/db1200/kernel/linux-2.6.git/include/linux/mm_types.h:15, >> >> from >> /mnt/data/_home/mano/db1200/kernel/linux-2.6.git/include/linux/sched.h:63, >> >> from >> /mnt/data/_home/mano/db1200/kernel/linux-2.6.git/arch/mips/kernel/asm-offsets.c:13: >> >> /mnt/data/_home/mano/db1200/kernel/linux-2.6.git/arch/mips/include/asm/pgtable-bits.h: >> >> In function 'pte_to_entrylo': >> /mnt/data/_home/mano/db1200/kernel/linux-2.6.git/arch/mips/include/asm/pgtable-bits.h:146: >> >> error: '_PAGE_NO_READ_SHIFT' undeclared (first use in this function) >> /mnt/data/_home/mano/db1200/kernel/linux-2.6.git/arch/mips/include/asm/pgtable-bits.h:146: >> >> error: (Each undeclared identifier is reported only once >> /mnt/data/_home/mano/db1200/kernel/linux-2.6.git/arch/mips/include/asm/pgtable-bits.h:146: >> >> error: for each function it appears in.) >> /mnt/data/_home/mano/db1200/kernel/linux-2.6.git/arch/mips/include/asm/pgtable-bits.h:155: >> >> error: '_PAGE_GLOBAL_SHIFT' undeclared (first use in this function) >> /mnt/data/_home/mano/db1200/kernel/linux-2.6.git/arch/mips/include/asm/pgtable-bits.h:156: >> >> error: '_PAGE_NO_EXEC' undeclared (first use in this function) >> /mnt/data/_home/mano/db1200/kernel/linux-2.6.git/arch/mips/include/asm/pgtable-bits.h:156: >> >> error: '_PAGE_NO_READ' undeclared (first use in this function) >> In file included from >> /mnt/data/_home/mano/db1200/kernel/linux-2.6.git/include/linux/mm.h:39, >> from >> /mnt/data/_home/mano/db1200/kernel/linux-2.6.git/arch/mips/kernel/asm-offsets.c:14: >> >> /mnt/data/_home/mano/db1200/kernel/linux-2.6.git/arch/mips/include/asm/pgtable.h: >> >> In function 'pte_modify': >> /mnt/data/_home/mano/db1200/kernel/linux-2.6.git/arch/mips/include/asm/pgtable.h:351: >> >> error: '_PFN_MASK' undeclared (first use in this function) >> make[2]: *** [arch/mips/kernel/asm-offsets.s] Error 1 >> make[1]: *** [prepare0] Error 2 >> make: *** [sub-make] Error 2 > Whoops! I will endeavor to fix this. Try the attached patch, it allows me to build an au1000 kernel. But since I don't have harware, I cannot test it. I started with pb1500_defconfig, but had to disable au1000_eth.c: drivers/net/au1000_eth.c: In function ‘au1000_probe’: drivers/net/au1000_eth.c:1009: error: implicit declaration of function ‘DECLARE_MAC_BUF’ drivers/net/au1000_eth.c:1009: error: ‘ethaddr’ undeclared (first use in this function) drivers/net/au1000_eth.c:1009: error: (Each undeclared identifier is reported only once drivers/net/au1000_eth.c:1009: error: for each function it appears in.) David Daney. --------------050708080304060801080702 Content-Type: text/plain; name="dd.patch" Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename="dd.patch" MIPS: Fix RIXI patch for au1000 processors. Signed-off-by: David Daney --- arch/mips/include/asm/pgtable-bits.h | 20 +++++++++++++++----- 1 files changed, 15 insertions(+), 5 deletions(-) diff --git a/arch/mips/include/asm/pgtable-bits.h b/arch/mips/include/asm/pgtable-bits.h index a2e646f..47ca734 100644 --- a/arch/mips/include/asm/pgtable-bits.h +++ b/arch/mips/include/asm/pgtable-bits.h @@ -66,7 +66,6 @@ #define _PAGE_SILENT_WRITE (1<<10) #define _CACHE_UNCACHED (1<<11) #define _CACHE_MASK (1<<11) -#define _PFN_SHIFT PAGE_SHIFT #else /* 'Normal' r4K case */ /* @@ -129,10 +128,22 @@ #define _CACHE_MASK (7 << _CACHE_SHIFT) #define _PFN_SHIFT (PAGE_SHIFT - 12 + _CACHE_SHIFT + 3) -#define _PFN_MASK (~((1 << (_PFN_SHIFT)) - 1)) #endif /* defined(CONFIG_64BIT_PHYS_ADDR && defined(CONFIG_CPU_MIPS32) */ +#ifndef _PFN_SHIFT +#define _PFN_SHIFT PAGE_SHIFT +#endif +#define _PFN_MASK (~((1 << (_PFN_SHIFT)) - 1)) + +#ifndef _PAGE_NO_READ +#define _PAGE_NO_READ ({BUG(); 0; }) +#define _PAGE_NO_READ_SHIFT ({BUG(); 0; }) +#endif +#ifndef _PAGE_NO_EXEC +#define _PAGE_NO_EXEC ({BUG(); 0; }) +#endif + #ifndef __ASSEMBLY__ /* * pte_to_entrylo converts a page table entry (PTE) into a Mips @@ -152,11 +163,10 @@ static inline uint64_t pte_to_entrylo(unsigned long pte_val) * followed by a ROTR 2. Luckily in the fast path * this is done in assembly */ - return (pte_val >> _PAGE_GLOBAL_SHIFT) | + return (pte_val >> ilog2(_PAGE_GLOBAL)) | ((pte_val & (_PAGE_NO_EXEC | _PAGE_NO_READ)) << sa); } - - return pte_val >> _PAGE_GLOBAL_SHIFT; + return pte_val >> ilog2(_PAGE_GLOBAL); } #endif --------------050708080304060801080702-- From manuel.lauss@googlemail.com Mon Feb 15 18:34:11 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 15 Feb 2010 18:34:16 +0100 (CET) Received: from mail-fx0-f216.google.com ([209.85.220.216]:55668 "EHLO mail-fx0-f216.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491954Ab0BOReL convert rfc822-to-8bit (ORCPT ); Mon, 15 Feb 2010 18:34:11 +0100 Received: by fxm8 with SMTP id 8so5242687fxm.26 for ; Mon, 15 Feb 2010 09:34:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=domainkey-signature:mime-version:received:in-reply-to:references :date:message-id:subject:from:to:cc:content-type :content-transfer-encoding; bh=/liblPNUalx04Eglgi9UWBM9Szw48iqZzQ3bC9PG9dg=; b=ENNYp3AgBWt8jDarELas5flTNz1xf3v2UuFFJ5NjnCpPunGST2kjUlB+g+sE0sYzUF Gt/0fK2Wq9ug+7L0T97Vnnjq1JeSLqP4iI4OqVlQN4BDIrFwjDGw9yQ2hdp0GtPwcvq3 eXt85kuzbvzwN2ZdCbuQyzuOWHP+zPNhKFz54= DomainKey-Signature: a=rsa-sha1; c=nofws; d=googlemail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type:content-transfer-encoding; b=QDsFF/YF6s7IBGln92Lp8osOF1dPWk7PfXGTQa8STTtlUPnjoA6CwgprcjSGi6O+31 G0l0fT5lp5HxUjOg+Q6P8gy6DgObD+Ai+D01Z9Ph5ctonKV5GfQYBHO9gCFRRaillEGH F550by2QpcvAsXaJWuTmUBAd7WsKGwaHw3VgI= MIME-Version: 1.0 Received: by 10.223.6.88 with SMTP id 24mr3553855fay.2.1266255244895; Mon, 15 Feb 2010 09:34:04 -0800 (PST) In-Reply-To: <4B78AC97.8030404@gmail.com> References: <4B733C71.8030304@caviumnetworks.com> <1265843569-5786-4-git-send-email-ddaney@caviumnetworks.com> <4B78A0C1.1070509@gmail.com> <4B78AC97.8030404@gmail.com> Date: Mon, 15 Feb 2010 18:34:04 +0100 Message-ID: Subject: Re: [PATCH 4/6] MIPS: Implement Read Inhibit/eXecute Inhibit From: Manuel Lauss To: David Daney Cc: David Daney , linux-mips@linux-mips.org, ralf@linux-mips.org Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 8BIT Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25919 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips Hi David, On Mon, Feb 15, 2010 at 3:08 AM, David Daney wrote: >> On 02/14/2010 12:16 PM, Manuel Lauss wrote: >>> this patch breaks my Alchemy builds: > Try the attached patch, it allows me to build an au1000 kernel. But since I > don't have harware, I cannot test it. Boots my userspace, thank you! > I started with pb1500_defconfig, but had to disable au1000_eth.c: > > drivers/net/au1000_eth.c: In function ‘au1000_probe’: > drivers/net/au1000_eth.c:1009: error: implicit declaration of function > ‘DECLARE_MAC_BUF’ > drivers/net/au1000_eth.c:1009: error: ‘ethaddr’ undeclared (first use in > this function) > drivers/net/au1000_eth.c:1009: error: (Each undeclared identifier is > reported only once > drivers/net/au1000_eth.c:1009: error: for each function it appears in.) I'll try to fix this; usually I only build db1200_defconfig. Manuel From David.Daney@caviumnetworks.com Mon Feb 15 18:38:43 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 15 Feb 2010 18:38:47 +0100 (CET) Received: from mail3.caviumnetworks.com ([12.108.191.235]:17473 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492094Ab0BORin (ORCPT ); Mon, 15 Feb 2010 18:38:43 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Mon, 15 Feb 2010 09:38:50 -0800 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Mon, 15 Feb 2010 09:38:39 -0800 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Mon, 15 Feb 2010 09:38:39 -0800 Message-ID: <4B79869F.2040700@caviumnetworks.com> Date: Mon, 15 Feb 2010 09:38:39 -0800 From: David Daney User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.7) Gecko/20100120 Fedora/3.0.1-1.fc12 Thunderbird/3.0.1 MIME-Version: 1.0 To: Manuel Lauss CC: David Daney , linux-mips@linux-mips.org, ralf@linux-mips.org Subject: Re: [PATCH 4/6] MIPS: Implement Read Inhibit/eXecute Inhibit References: <4B733C71.8030304@caviumnetworks.com> <1265843569-5786-4-git-send-email-ddaney@caviumnetworks.com> <4B78A0C1.1070509@gmail.com> <4B78AC97.8030404@gmail.com> In-Reply-To: Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 8bit X-OriginalArrivalTime: 15 Feb 2010 17:38:39.0921 (UTC) FILETIME=[B5D78210:01CAAE65] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25920 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips On 02/15/2010 09:34 AM, Manuel Lauss wrote: > Hi David, > > On Mon, Feb 15, 2010 at 3:08 AM, David Daney wrote: >>> On 02/14/2010 12:16 PM, Manuel Lauss wrote: > >>>> this patch breaks my Alchemy builds: > >> Try the attached patch, it allows me to build an au1000 kernel. But since I >> don't have harware, I cannot test it. > > Boots my userspace, thank you! > Ok. I am working on a functionally equivalent, but slightly cleaner patch. Thanks for your patience, David Daney > >> I started with pb1500_defconfig, but had to disable au1000_eth.c: >> >> drivers/net/au1000_eth.c: In function ‘au1000_probe’: >> drivers/net/au1000_eth.c:1009: error: implicit declaration of function >> ‘DECLARE_MAC_BUF’ >> drivers/net/au1000_eth.c:1009: error: ‘ethaddr’ undeclared (first use in >> this function) >> drivers/net/au1000_eth.c:1009: error: (Each undeclared identifier is >> reported only once >> drivers/net/au1000_eth.c:1009: error: for each function it appears in.) > > I'll try to fix this; usually I only build db1200_defconfig. > > Manuel > From David.Daney@caviumnetworks.com Mon Feb 15 19:34:04 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 15 Feb 2010 19:34:07 +0100 (CET) Received: from mail3.caviumnetworks.com ([12.108.191.235]:18438 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492112Ab0BOSeE (ORCPT ); Mon, 15 Feb 2010 19:34:04 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Mon, 15 Feb 2010 10:34:11 -0800 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Mon, 15 Feb 2010 10:34:00 -0800 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Mon, 15 Feb 2010 10:34:00 -0800 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.3/8.14.2) with ESMTP id o1FIXw90017879; Mon, 15 Feb 2010 10:33:58 -0800 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.3/8.14.3/Submit) id o1FIXu0o017878; Mon, 15 Feb 2010 10:33:56 -0800 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: David Daney Subject: [PATCH] MIPS: Fix RIXI patch for au1000 processors. Date: Mon, 15 Feb 2010 10:33:21 -0800 Message-Id: <1266258801-17841-1-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.6.6 X-OriginalArrivalTime: 15 Feb 2010 18:34:00.0919 (UTC) FILETIME=[714F9670:01CAAE6D] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25921 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Several macros need to be defined even though they are only used in dead code paths. Signed-off-by: David Daney --- arch/mips/include/asm/pgtable-bits.h | 25 ++++++++++++++++++++----- 1 files changed, 20 insertions(+), 5 deletions(-) diff --git a/arch/mips/include/asm/pgtable-bits.h b/arch/mips/include/asm/pgtable-bits.h index a2e646f..e9fe7e9 100644 --- a/arch/mips/include/asm/pgtable-bits.h +++ b/arch/mips/include/asm/pgtable-bits.h @@ -66,7 +66,6 @@ #define _PAGE_SILENT_WRITE (1<<10) #define _CACHE_UNCACHED (1<<11) #define _CACHE_MASK (1<<11) -#define _PFN_SHIFT PAGE_SHIFT #else /* 'Normal' r4K case */ /* @@ -129,10 +128,26 @@ #define _CACHE_MASK (7 << _CACHE_SHIFT) #define _PFN_SHIFT (PAGE_SHIFT - 12 + _CACHE_SHIFT + 3) -#define _PFN_MASK (~((1 << (_PFN_SHIFT)) - 1)) #endif /* defined(CONFIG_64BIT_PHYS_ADDR && defined(CONFIG_CPU_MIPS32) */ +#ifndef _PFN_SHIFT +#define _PFN_SHIFT PAGE_SHIFT +#endif +#define _PFN_MASK (~((1 << (_PFN_SHIFT)) - 1)) + +#ifndef _PAGE_NO_READ +#define _PAGE_NO_READ ({BUG(); 0; }) +#define _PAGE_NO_READ_SHIFT ({BUG(); 0; }) +#endif +#ifndef _PAGE_NO_EXEC +#define _PAGE_NO_EXEC ({BUG(); 0; }) +#endif +#ifndef _PAGE_GLOBAL_SHIFT +#define _PAGE_GLOBAL_SHIFT ilog2(_PAGE_GLOBAL) +#endif + + #ifndef __ASSEMBLY__ /* * pte_to_entrylo converts a page table entry (PTE) into a Mips @@ -148,9 +163,9 @@ static inline uint64_t pte_to_entrylo(unsigned long pte_val) sa = 63 - _PAGE_NO_READ_SHIFT; #endif /* - * C has no way to express that this is a DSRL 5 - * followed by a ROTR 2. Luckily in the fast path - * this is done in assembly + * C has no way to express that this is a DSRL + * _PAGE_NO_EXEC_SHIFT followed by a ROTR 2. Luckily + * in the fast path this is done in assembly */ return (pte_val >> _PAGE_GLOBAL_SHIFT) | ((pte_val & (_PAGE_NO_EXEC | _PAGE_NO_READ)) << sa); -- 1.6.6 From manuel.lauss@googlemail.com Mon Feb 15 20:43:05 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 15 Feb 2010 20:43:09 +0100 (CET) Received: from mail-fx0-f210.google.com ([209.85.220.210]:58847 "EHLO mail-fx0-f210.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492162Ab0BOTnF (ORCPT ); Mon, 15 Feb 2010 20:43:05 +0100 Received: by fxm2 with SMTP id 2so2276081fxm.27 for ; Mon, 15 Feb 2010 11:42:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer; bh=eugNmN2OyxRKYqiSg1FcAVkcbzagt4J1mnEUYH/QI1c=; b=dfkX4ahaN/7RkGG40as9N7yhShxzne5LeO+duh5+n4LjyN4TzY7zEnFQ8yC9YO5Lt9 SaO5v7MlaDYnFeqkaYCh9nK6cGtuSNn4jgd4qddRye1WNlQBRZKUfTK77wFQyHqyb0Hf N5B5I6kn3k4cjZHqPowFGku8DZqclypwtMj20= DomainKey-Signature: a=rsa-sha1; c=nofws; d=googlemail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer; b=Q5qNozqDFfjI/WOIhovsKSHoBkzA1PrbAhhgqWgpIc/9vm6wP2npjTj+ICAITZyCTF 6YWwLgibWSh7NzVfvjg4WhkxGlB3w01HJXz7RMqic4w1ebKSJh1NekeBUh7CqScsbaAL KBq2TkHZLbgAg8CnvwaN+pVdgWsDGWRWgWrPc= Received: by 10.223.100.150 with SMTP id y22mr6184177fan.99.1266262978161; Mon, 15 Feb 2010 11:42:58 -0800 (PST) Received: from localhost.localdomain (p5496BF25.dip.t-dialin.net [84.150.191.37]) by mx.google.com with ESMTPS id b17sm10661729fka.16.2010.02.15.11.42.55 (version=TLSv1/SSLv3 cipher=RC4-MD5); Mon, 15 Feb 2010 11:42:55 -0800 (PST) From: Manuel Lauss To: Linux-MIPS , =?UTF-8?q?Ralf=20B=E4chle?= Cc: Manuel Lauss Subject: [PATCH -queue] MIPS/net: fix au1000_eth.c build and warnings Date: Mon, 15 Feb 2010 20:43:37 +0100 Message-Id: <1266263017-6874-1-git-send-email-manuel.lauss@gmail.com> X-Mailer: git-send-email 1.6.6.1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25922 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips - buildfix: DECLARE_MAC_BUF was removed recently. - remove various warnings spit out during build Only compile-tested. Signed-off-by: Manuel Lauss --- Hi Ralf! Please fold this into the patch titled "NET: au1000-eth: convert to platform_driver model" in mips-queue, thank you! drivers/net/au1000_eth.c | 14 +++++++------- 1 files changed, 7 insertions(+), 7 deletions(-) diff --git a/drivers/net/au1000_eth.c b/drivers/net/au1000_eth.c index 1acf2c1..6e5a68e 100644 --- a/drivers/net/au1000_eth.c +++ b/drivers/net/au1000_eth.c @@ -397,11 +397,12 @@ static int mii_probe (struct net_device *dev) /* find the first (lowest address) non-attached PHY on * the MAC0 MII bus */ for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) { - if (aup->mac_id == 1) - break; struct phy_device *const tmp_phydev = aup->mii_bus->phy_map[phy_addr]; + if (aup->mac_id == 1) + break; + if (!tmp_phydev) continue; /* no PHY here... */ @@ -650,7 +651,6 @@ static int au1000_init(struct net_device *dev) static inline void update_rx_stats(struct net_device *dev, u32 status) { - struct au1000_private *aup = netdev_priv(dev); struct net_device_stats *ps = &dev->stats; ps->rx_packets++; @@ -908,7 +908,7 @@ static netdev_tx_t au1000_tx(struct sk_buff *skb, struct net_device *dev) } pDB = aup->tx_db_inuse[aup->tx_head]; - skb_copy_from_linear_data(skb, pDB->vaddr, skb->len); + skb_copy_from_linear_data(skb, (void *)pDB->vaddr, skb->len); if (skb->len < ETH_ZLEN) { for (i=skb->len; ivaddr)[i] = 0; @@ -1006,7 +1006,7 @@ static int __devinit au1000_probe(struct platform_device *pdev) db_dest_t *pDB, *pDBfree; int irq, i, err = 0; struct resource *base, *macen; - DECLARE_MAC_BUF(ethaddr); + char ethaddr[6]; base = platform_get_resource(pdev, IORESOURCE_MEM, 0); if (!base) { @@ -1207,8 +1207,8 @@ static int __devinit au1000_probe(struct platform_device *pdev) goto err_out; } - printk("%s: Au1xx0 Ethernet found at 0x%x, irq %d\n", - dev->name, base->start, irq); + printk("%s: Au1xx0 Ethernet found at 0x%lx, irq %d\n", + dev->name, (unsigned long)base->start, irq); if (version_printed++ == 0) printk("%s version %s %s\n", DRV_NAME, DRV_VERSION, DRV_AUTHOR); -- 1.6.6.1 From David.Daney@caviumnetworks.com Mon Feb 15 21:12:25 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 15 Feb 2010 21:12:29 +0100 (CET) Received: from mail3.caviumnetworks.com ([12.108.191.235]:19937 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492094Ab0BOUMZ (ORCPT ); Mon, 15 Feb 2010 21:12:25 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Mon, 15 Feb 2010 12:12:32 -0800 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Mon, 15 Feb 2010 12:12:22 -0800 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Mon, 15 Feb 2010 12:12:22 -0800 Message-ID: <4B79AAA6.60005@caviumnetworks.com> Date: Mon, 15 Feb 2010 12:12:22 -0800 From: David Daney User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.7) Gecko/20100120 Fedora/3.0.1-1.fc12 Thunderbird/3.0.1 MIME-Version: 1.0 To: ralf.baechle@gmail.com, linux-mips , Netdev , Greg Kroah-Hartman Subject: [PATCH 0/4] Improvements to octeon_ethernet. Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 15 Feb 2010 20:12:22.0488 (UTC) FILETIME=[2EEB8D80:01CAAE7B] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25923 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Here are a couple of improvements to the octeon_ethernet in drivers/staging/octeon. The first patch is just cleanup, the rest are genuine bug fixes. I will reply with the four patches. We may want to merge via Ralf's linux-mips.org tree as Octeon is infact a MIPS based SOC and he has a bunch of other patches queued there that these depend on. David Daney (4): Staging: octeon: remove unneeded includes Staging: Octeon: Run phy bus accesses on a workqueue. MIPS: Octeon: Do proper acknowledgment of CIU timer interrupts. Staging: Octeon: Free transmit SKBs in a timely manner. arch/mips/cavium-octeon/octeon-irq.c | 67 +++++++++++++- drivers/staging/octeon/Kconfig | 1 - drivers/staging/octeon/ethernet-defines.h | 5 +- drivers/staging/octeon/ethernet-mdio.h | 1 - drivers/staging/octeon/ethernet-rgmii.c | 56 +++++++++--- drivers/staging/octeon/ethernet-sgmii.c | 1 - drivers/staging/octeon/ethernet-spi.c | 1 - drivers/staging/octeon/ethernet-tx.c | 137 ++++++++++++++++++++++------ drivers/staging/octeon/ethernet-tx.h | 6 +- drivers/staging/octeon/ethernet-xaui.c | 1 - drivers/staging/octeon/ethernet.c | 141 ++++++++++++++++------------- drivers/staging/octeon/octeon-ethernet.h | 11 ++- 12 files changed, 303 insertions(+), 125 deletions(-) From David.Daney@caviumnetworks.com Mon Feb 15 21:13:35 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 15 Feb 2010 21:13:39 +0100 (CET) Received: from mail3.caviumnetworks.com ([12.108.191.235]:19974 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492143Ab0BOUNf (ORCPT ); Mon, 15 Feb 2010 21:13:35 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Mon, 15 Feb 2010 12:13:43 -0800 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Mon, 15 Feb 2010 12:13:33 -0800 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Mon, 15 Feb 2010 12:13:32 -0800 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.3/8.14.2) with ESMTP id o1FKDTOU003548; Mon, 15 Feb 2010 12:13:29 -0800 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.3/8.14.3/Submit) id o1FKDSgD003547; Mon, 15 Feb 2010 12:13:28 -0800 From: David Daney To: ralf@linux-mips.org, linux-mips@linux-mips.org, netdev@vger.kernel.org, gregkh@suse.de Cc: David Daney Subject: [PATCH 1/4] Staging: octeon: remove unneeded includes Date: Mon, 15 Feb 2010 12:13:16 -0800 Message-Id: <1266264799-3510-1-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.6.6 In-Reply-To: <4B79AAA6.60005@caviumnetworks.com> References: <4B79AAA6.60005@caviumnetworks.com> X-OriginalArrivalTime: 15 Feb 2010 20:13:32.0801 (UTC) FILETIME=[58D47710:01CAAE7B] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25924 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Signed-off-by: David Daney --- drivers/staging/octeon/ethernet-mdio.h | 1 - drivers/staging/octeon/ethernet-rgmii.c | 1 - drivers/staging/octeon/ethernet-sgmii.c | 1 - drivers/staging/octeon/ethernet-spi.c | 1 - drivers/staging/octeon/ethernet-xaui.c | 1 - drivers/staging/octeon/ethernet.c | 1 - 6 files changed, 0 insertions(+), 6 deletions(-) diff --git a/drivers/staging/octeon/ethernet-mdio.h b/drivers/staging/octeon/ethernet-mdio.h index 55d0614..a417d4f 100644 --- a/drivers/staging/octeon/ethernet-mdio.h +++ b/drivers/staging/octeon/ethernet-mdio.h @@ -32,7 +32,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/staging/octeon/ethernet-rgmii.c b/drivers/staging/octeon/ethernet-rgmii.c index 3820f1e..f90d46e 100644 --- a/drivers/staging/octeon/ethernet-rgmii.c +++ b/drivers/staging/octeon/ethernet-rgmii.c @@ -26,7 +26,6 @@ **********************************************************************/ #include #include -#include #include #include diff --git a/drivers/staging/octeon/ethernet-sgmii.c b/drivers/staging/octeon/ethernet-sgmii.c index 6061d01..2d8589e 100644 --- a/drivers/staging/octeon/ethernet-sgmii.c +++ b/drivers/staging/octeon/ethernet-sgmii.c @@ -26,7 +26,6 @@ **********************************************************************/ #include #include -#include #include #include diff --git a/drivers/staging/octeon/ethernet-spi.c b/drivers/staging/octeon/ethernet-spi.c index 00dc0f4..b58b897 100644 --- a/drivers/staging/octeon/ethernet-spi.c +++ b/drivers/staging/octeon/ethernet-spi.c @@ -26,7 +26,6 @@ **********************************************************************/ #include #include -#include #include #include diff --git a/drivers/staging/octeon/ethernet-xaui.c b/drivers/staging/octeon/ethernet-xaui.c index ee3dc41..3fca1cc 100644 --- a/drivers/staging/octeon/ethernet-xaui.c +++ b/drivers/staging/octeon/ethernet-xaui.c @@ -26,7 +26,6 @@ **********************************************************************/ #include #include -#include #include #include diff --git a/drivers/staging/octeon/ethernet.c b/drivers/staging/octeon/ethernet.c index 9d63202..5afece0 100644 --- a/drivers/staging/octeon/ethernet.c +++ b/drivers/staging/octeon/ethernet.c @@ -29,7 +29,6 @@ #include #include #include -#include #include #include -- 1.6.6 From David.Daney@caviumnetworks.com Mon Feb 15 21:13:57 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 15 Feb 2010 21:14:03 +0100 (CET) Received: from mail3.caviumnetworks.com ([12.108.191.235]:19967 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492094Ab0BOUNf (ORCPT ); Mon, 15 Feb 2010 21:13:35 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Mon, 15 Feb 2010 12:13:42 -0800 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Mon, 15 Feb 2010 12:13:32 -0800 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Mon, 15 Feb 2010 12:13:32 -0800 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.3/8.14.2) with ESMTP id o1FKDUaK003552; Mon, 15 Feb 2010 12:13:30 -0800 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.3/8.14.3/Submit) id o1FKDTsk003551; Mon, 15 Feb 2010 12:13:29 -0800 From: David Daney To: ralf@linux-mips.org, linux-mips@linux-mips.org, netdev@vger.kernel.org, gregkh@suse.de Cc: David Daney Subject: [PATCH 2/4] Staging: Octeon: Run phy bus accesses on a workqueue. Date: Mon, 15 Feb 2010 12:13:17 -0800 Message-Id: <1266264799-3510-2-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.6.6 In-Reply-To: <4B79AAA6.60005@caviumnetworks.com> References: <4B79AAA6.60005@caviumnetworks.com> X-OriginalArrivalTime: 15 Feb 2010 20:13:32.0801 (UTC) FILETIME=[58D47710:01CAAE7B] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25925 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips When directly accessing a phy, we must acquire the mdio bus lock. To do that we cannot be in interrupt context, so we need to move these operations to a workqueue. Signed-off-by: David Daney --- drivers/staging/octeon/ethernet-rgmii.c | 55 +++++++++++---- drivers/staging/octeon/ethernet.c | 113 +++++++++++++++++------------- drivers/staging/octeon/octeon-ethernet.h | 4 + 3 files changed, 109 insertions(+), 63 deletions(-) diff --git a/drivers/staging/octeon/ethernet-rgmii.c b/drivers/staging/octeon/ethernet-rgmii.c index f90d46e..a0d4d4b 100644 --- a/drivers/staging/octeon/ethernet-rgmii.c +++ b/drivers/staging/octeon/ethernet-rgmii.c @@ -26,6 +26,7 @@ **********************************************************************/ #include #include +#include #include #include @@ -47,14 +48,20 @@ static int number_rgmii_ports; static void cvm_oct_rgmii_poll(struct net_device *dev) { struct octeon_ethernet *priv = netdev_priv(dev); - unsigned long flags; + unsigned long flags = 0; cvmx_helper_link_info_t link_info; + int use_global_register_lock = (priv->phydev == NULL); - /* - * Take the global register lock since we are going to touch - * registers that affect more than one port. - */ - spin_lock_irqsave(&global_register_lock, flags); + BUG_ON(in_interrupt()); + if (use_global_register_lock) { + /* + * Take the global register lock since we are going to + * touch registers that affect more than one port. + */ + spin_lock_irqsave(&global_register_lock, flags); + } else { + mutex_lock(&priv->phydev->bus->mdio_lock); + } link_info = cvmx_helper_link_get(priv->port); if (link_info.u64 == priv->link_info) { @@ -114,7 +121,11 @@ static void cvm_oct_rgmii_poll(struct net_device *dev) dev->name); } } - spin_unlock_irqrestore(&global_register_lock, flags); + + if (use_global_register_lock) + spin_unlock_irqrestore(&global_register_lock, flags); + else + mutex_unlock(&priv->phydev->bus->mdio_lock); return; } @@ -150,7 +161,12 @@ static void cvm_oct_rgmii_poll(struct net_device *dev) link_info = cvmx_helper_link_autoconf(priv->port); priv->link_info = link_info.u64; } - spin_unlock_irqrestore(&global_register_lock, flags); + + if (use_global_register_lock) + spin_unlock_irqrestore(&global_register_lock, flags); + else { + mutex_unlock(&priv->phydev->bus->mdio_lock); + } if (priv->phydev == NULL) { /* Tell core. */ @@ -212,8 +228,11 @@ static irqreturn_t cvm_oct_rgmii_rml_interrupt(int cpl, void *dev_id) struct net_device *dev = cvm_oct_device[cvmx_helper_get_ipd_port (interface, index)]; - if (dev) - cvm_oct_rgmii_poll(dev); + struct octeon_ethernet *priv = netdev_priv(dev); + + if (dev && !atomic_read(&cvm_oct_poll_queue_stopping)) + queue_work(cvm_oct_poll_queue, &priv->port_work); + gmx_rx_int_reg.u64 = 0; gmx_rx_int_reg.s.phy_dupx = 1; gmx_rx_int_reg.s.phy_link = 1; @@ -251,8 +270,11 @@ static irqreturn_t cvm_oct_rgmii_rml_interrupt(int cpl, void *dev_id) struct net_device *dev = cvm_oct_device[cvmx_helper_get_ipd_port (interface, index)]; - if (dev) - cvm_oct_rgmii_poll(dev); + struct octeon_ethernet *priv = netdev_priv(dev); + + if (dev && !atomic_read(&cvm_oct_poll_queue_stopping)) + queue_work(cvm_oct_poll_queue, &priv->port_work); + gmx_rx_int_reg.u64 = 0; gmx_rx_int_reg.s.phy_dupx = 1; gmx_rx_int_reg.s.phy_link = 1; @@ -301,6 +323,12 @@ int cvm_oct_rgmii_stop(struct net_device *dev) return 0; } +static void cvm_oct_rgmii_immediate_poll(struct work_struct *work) +{ + struct octeon_ethernet *priv = container_of(work, struct octeon_ethernet, port_work); + cvm_oct_rgmii_poll(cvm_oct_device[priv->port]); +} + int cvm_oct_rgmii_init(struct net_device *dev) { struct octeon_ethernet *priv = netdev_priv(dev); @@ -308,7 +336,7 @@ int cvm_oct_rgmii_init(struct net_device *dev) cvm_oct_common_init(dev); dev->netdev_ops->ndo_stop(dev); - + INIT_WORK(&priv->port_work, cvm_oct_rgmii_immediate_poll); /* * Due to GMX errata in CN3XXX series chips, it is necessary * to take the link down immediately when the PHY changes @@ -396,4 +424,5 @@ void cvm_oct_rgmii_uninit(struct net_device *dev) number_rgmii_ports--; if (number_rgmii_ports == 0) free_irq(OCTEON_IRQ_RML, &number_rgmii_ports); + cancel_work_sync(&priv->port_work); } diff --git a/drivers/staging/octeon/ethernet.c b/drivers/staging/octeon/ethernet.c index 5afece0..1771c10 100644 --- a/drivers/staging/octeon/ethernet.c +++ b/drivers/staging/octeon/ethernet.c @@ -123,9 +123,16 @@ MODULE_PARM_DESC(rx_napi_weight, "The NAPI WEIGHT parameter."); static unsigned int cvm_oct_mac_addr_offset; /** - * Periodic timer to check auto negotiation + * cvm_oct_poll_queue - Workqueue for polling operations. */ -static struct timer_list cvm_oct_poll_timer; +struct workqueue_struct *cvm_oct_poll_queue; + +/** + * cvm_oct_poll_queue_stopping - flag to indicate polling should stop. + * + * Set to one right before cvm_oct_poll_queue is destroyed. + */ +atomic_t cvm_oct_poll_queue_stopping = ATOMIC_INIT(0); /** * Array of every ethernet device owned by this driver indexed by @@ -133,47 +140,39 @@ static struct timer_list cvm_oct_poll_timer; */ struct net_device *cvm_oct_device[TOTAL_NUMBER_OF_PORTS]; -/** - * Periodic timer tick for slow management operations - * - * @arg: Device to check - */ -static void cvm_do_timer(unsigned long arg) +static void cvm_oct_rx_refill_worker(struct work_struct *work); +static DECLARE_DELAYED_WORK(cvm_oct_rx_refill_work, cvm_oct_rx_refill_worker); + +static void cvm_oct_rx_refill_worker(struct work_struct *work) { - static int port; - if (port < CVMX_PIP_NUM_INPUT_PORTS) { - if (cvm_oct_device[port]) { - struct octeon_ethernet *priv = netdev_priv(cvm_oct_device[port]); - if (priv->poll) - priv->poll(cvm_oct_device[port]); - cvm_oct_free_tx_skbs(priv); - cvm_oct_device[port]->netdev_ops->ndo_get_stats(cvm_oct_device[port]); - } - port++; - /* - * Poll the next port in a 50th of a second. This - * spreads the polling of ports out a little bit. - */ - mod_timer(&cvm_oct_poll_timer, jiffies + HZ/50); - } else { - port = 0; - /* - * FPA 0 may have been drained, try to refill it if we - * need more than num_packet_buffers / 2, otherwise - * normal receive processing will refill it. If it - * were drained, no packets could be received so - * cvm_oct_napi_poll would never be invoked to do the - * refill. - */ - cvm_oct_rx_refill_pool(num_packet_buffers / 2); - /* - * All ports have been polled. Start the next iteration through - * the ports in one second. - */ - mod_timer(&cvm_oct_poll_timer, jiffies + HZ); - } + /* + * FPA 0 may have been drained, try to refill it if we need + * more than num_packet_buffers / 2, otherwise normal receive + * processing will refill it. If it were drained, no packets + * could be received so cvm_oct_napi_poll would never be + * invoked to do the refill. + */ + cvm_oct_rx_refill_pool(num_packet_buffers / 2); + + if (!atomic_read(&cvm_oct_poll_queue_stopping)) + queue_delayed_work(cvm_oct_poll_queue, + &cvm_oct_rx_refill_work, HZ); } +static void cvm_oct_tx_clean_worker(struct work_struct *work) +{ + struct octeon_ethernet *priv = container_of(work, + struct octeon_ethernet, + tx_clean_work.work); + + if (priv->poll) + priv->poll(cvm_oct_device[priv->port]); + cvm_oct_free_tx_skbs(priv); + cvm_oct_device[priv->port]->netdev_ops->ndo_get_stats(cvm_oct_device[priv->port]); + if (!atomic_read(&cvm_oct_poll_queue_stopping)) + queue_delayed_work(cvm_oct_poll_queue, &priv->tx_clean_work, HZ); + } + /** * Configure common hardware for all interfaces */ @@ -624,6 +623,12 @@ static int __init cvm_oct_init_module(void) else cvm_oct_mac_addr_offset = 0; + cvm_oct_poll_queue = create_singlethread_workqueue("octeon-ethernet"); + if (cvm_oct_poll_queue == NULL) { + pr_err("octeon-ethernet: Cannot create workqueue"); + return -ENOMEM; + } + cvm_oct_proc_initialize(); cvm_oct_configure_common_hw(); @@ -719,7 +724,9 @@ static int __init cvm_oct_init_module(void) /* Initialize the device private structure. */ priv = netdev_priv(dev); - memset(priv, 0, sizeof(struct octeon_ethernet)); + + INIT_DELAYED_WORK(&priv->tx_clean_work, + cvm_oct_tx_clean_worker); priv->imode = imode; priv->port = port; @@ -785,17 +792,15 @@ static int __init cvm_oct_init_module(void) fau -= cvmx_pko_get_num_queues(priv->port) * sizeof(uint32_t); + queue_delayed_work(cvm_oct_poll_queue, + &priv->tx_clean_work, HZ); } } } cvm_oct_rx_initialize(); - /* Enable the poll timer for checking RGMII status */ - init_timer(&cvm_oct_poll_timer); - cvm_oct_poll_timer.data = 0; - cvm_oct_poll_timer.function = cvm_do_timer; - mod_timer(&cvm_oct_poll_timer, jiffies + HZ); + queue_delayed_work(cvm_oct_poll_queue, &cvm_oct_rx_refill_work, HZ); return 0; } @@ -817,20 +822,28 @@ static void __exit cvm_oct_cleanup_module(void) /* Free the interrupt handler */ free_irq(OCTEON_IRQ_WORKQ0 + pow_receive_group, cvm_oct_device); - del_timer(&cvm_oct_poll_timer); + atomic_inc_return(&cvm_oct_poll_queue_stopping); + cancel_delayed_work_sync(&cvm_oct_rx_refill_work); + cvm_oct_rx_shutdown(); cvmx_pko_disable(); /* Free the ethernet devices */ for (port = 0; port < TOTAL_NUMBER_OF_PORTS; port++) { if (cvm_oct_device[port]) { - cvm_oct_tx_shutdown(cvm_oct_device[port]); - unregister_netdev(cvm_oct_device[port]); - kfree(cvm_oct_device[port]); + struct net_device *dev = cvm_oct_device[port]; + struct octeon_ethernet *priv = netdev_priv(dev); + cancel_delayed_work_sync(&priv->tx_clean_work); + + cvm_oct_tx_shutdown(dev); + unregister_netdev(dev); + kfree(dev); cvm_oct_device[port] = NULL; } } + destroy_workqueue(cvm_oct_poll_queue); + cvmx_pko_shutdown(); cvm_oct_proc_shutdown(); diff --git a/drivers/staging/octeon/octeon-ethernet.h b/drivers/staging/octeon/octeon-ethernet.h index 40b6956..8d09210 100644 --- a/drivers/staging/octeon/octeon-ethernet.h +++ b/drivers/staging/octeon/octeon-ethernet.h @@ -61,6 +61,8 @@ struct octeon_ethernet { void (*poll) (struct net_device *dev); struct hrtimer tx_restart_timer; ktime_t tx_restart_interval; + struct delayed_work tx_clean_work; + struct work_struct port_work; /* may be unused. */ }; /** @@ -97,6 +99,8 @@ extern int pow_send_group; extern int pow_receive_group; extern char pow_send_list[]; extern struct net_device *cvm_oct_device[]; +extern struct workqueue_struct *cvm_oct_poll_queue; +extern atomic_t cvm_oct_poll_queue_stopping; extern int max_rx_cpus; extern int rx_napi_weight; -- 1.6.6 From David.Daney@caviumnetworks.com Mon Feb 15 21:14:21 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 15 Feb 2010 21:14:29 +0100 (CET) Received: from mail3.caviumnetworks.com ([12.108.191.235]:19970 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492178Ab0BOUNf (ORCPT ); Mon, 15 Feb 2010 21:13:35 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Mon, 15 Feb 2010 12:13:42 -0800 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Mon, 15 Feb 2010 12:13:32 -0800 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Mon, 15 Feb 2010 12:13:32 -0800 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.3/8.14.2) with ESMTP id o1FKDU8q003560; Mon, 15 Feb 2010 12:13:30 -0800 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.3/8.14.3/Submit) id o1FKDUDc003559; Mon, 15 Feb 2010 12:13:30 -0800 From: David Daney To: ralf@linux-mips.org, linux-mips@linux-mips.org, netdev@vger.kernel.org, gregkh@suse.de Cc: David Daney Subject: [PATCH 4/4] Staging: Octeon: Free transmit SKBs in a timely manner. Date: Mon, 15 Feb 2010 12:13:19 -0800 Message-Id: <1266264799-3510-4-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.6.6 In-Reply-To: <4B79AAA6.60005@caviumnetworks.com> References: <4B79AAA6.60005@caviumnetworks.com> X-OriginalArrivalTime: 15 Feb 2010 20:13:32.0817 (UTC) FILETIME=[58D6E810:01CAAE7B] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25926 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips If we wait for the once-per-second cleanup to free transmit SKBs, sockets with small transmit buffer sizes might spend most of their time blocked waiting for the cleanup. Normally we do a cleanup for each transmitted packet. We add a watchdog type timer so that we also schedule a timeout for 150uS after a packet is transmitted. The watchdog is reset for each transmitted packet, so for high packet rates, it never expires. At these high rates, the cleanups are done for each packet so the extra watchdog initiated cleanups are not needed. Signed-off-by: David Daney --- drivers/staging/octeon/Kconfig | 1 - drivers/staging/octeon/ethernet-defines.h | 5 +- drivers/staging/octeon/ethernet-tx.c | 137 +++++++++++++++++++++++------ drivers/staging/octeon/ethernet-tx.h | 6 +- drivers/staging/octeon/ethernet.c | 47 +++++----- drivers/staging/octeon/octeon-ethernet.h | 9 +-- 6 files changed, 142 insertions(+), 63 deletions(-) diff --git a/drivers/staging/octeon/Kconfig b/drivers/staging/octeon/Kconfig index 579b8f1..638ad6b 100644 --- a/drivers/staging/octeon/Kconfig +++ b/drivers/staging/octeon/Kconfig @@ -3,7 +3,6 @@ config OCTEON_ETHERNET depends on CPU_CAVIUM_OCTEON select PHYLIB select MDIO_OCTEON - select HIGH_RES_TIMERS help This driver supports the builtin ethernet ports on Cavium Networks' products in the Octeon family. This driver supports the diff --git a/drivers/staging/octeon/ethernet-defines.h b/drivers/staging/octeon/ethernet-defines.h index 00a8561..6a2cd50 100644 --- a/drivers/staging/octeon/ethernet-defines.h +++ b/drivers/staging/octeon/ethernet-defines.h @@ -95,10 +95,11 @@ /*#define DONT_WRITEBACK(x) 0 */ /* Maximum number of SKBs to try to free per xmit packet. */ -#define MAX_SKB_TO_FREE 10 #define MAX_OUT_QUEUE_DEPTH 1000 -#define FAU_NUM_PACKET_BUFFERS_TO_FREE (CVMX_FAU_REG_END - sizeof(uint32_t)) +#define FAU_TOTAL_TX_TO_CLEAN (CVMX_FAU_REG_END - sizeof(uint32_t)) +#define FAU_NUM_PACKET_BUFFERS_TO_FREE (FAU_TOTAL_TX_TO_CLEAN - sizeof(uint32_t)) + #define TOTAL_NUMBER_OF_PORTS (CVMX_PIP_NUM_INPUT_PORTS+1) diff --git a/drivers/staging/octeon/ethernet-tx.c b/drivers/staging/octeon/ethernet-tx.c index 62258bd..5175247 100644 --- a/drivers/staging/octeon/ethernet-tx.c +++ b/drivers/staging/octeon/ethernet-tx.c @@ -48,6 +48,7 @@ #include "cvmx-wqe.h" #include "cvmx-fau.h" +#include "cvmx-pip.h" #include "cvmx-pko.h" #include "cvmx-helper.h" @@ -66,6 +67,11 @@ #define GET_SKBUFF_QOS(skb) 0 #endif +static void cvm_oct_tx_do_cleanup(unsigned long arg); +static DECLARE_TASKLET(cvm_oct_tx_cleanup_tasklet, cvm_oct_tx_do_cleanup, 0); + +/* Maximum number of SKBs to try to free per xmit packet. */ +#define MAX_SKB_TO_FREE (MAX_OUT_QUEUE_DEPTH * 2) static inline int32_t cvm_oct_adjust_skb_to_free(int32_t skb_to_free, int fau) { @@ -77,10 +83,24 @@ static inline int32_t cvm_oct_adjust_skb_to_free(int32_t skb_to_free, int fau) return skb_to_free; } -void cvm_oct_free_tx_skbs(struct octeon_ethernet *priv) +static void cvm_oct_kick_tx_poll_watchdog(void) +{ + union cvmx_ciu_timx ciu_timx; + ciu_timx.u64 = 0; + ciu_timx.s.one_shot = 1; + ciu_timx.s.len = cvm_oct_tx_poll_interval; + cvmx_write_csr(CVMX_CIU_TIMX(1), ciu_timx.u64); +} + +void cvm_oct_free_tx_skbs(struct net_device *dev) { int32_t skb_to_free; int qos, queues_per_port; + int total_freed = 0; + int total_remaining = 0; + unsigned long flags; + struct octeon_ethernet *priv = netdev_priv(dev); + queues_per_port = cvmx_pko_get_num_queues(priv->port); /* Drain any pending packets in the free list */ for (qos = 0; qos < queues_per_port; qos++) { @@ -89,24 +109,31 @@ void cvm_oct_free_tx_skbs(struct octeon_ethernet *priv) skb_to_free = cvmx_fau_fetch_and_add32(priv->fau+qos*4, MAX_SKB_TO_FREE); skb_to_free = cvm_oct_adjust_skb_to_free(skb_to_free, priv->fau+qos*4); - while (skb_to_free > 0) { - dev_kfree_skb_any(skb_dequeue(&priv->tx_free_list[qos])); - skb_to_free--; + + total_freed += skb_to_free; + if (skb_to_free > 0) { + struct sk_buff *to_free_list = NULL; + spin_lock_irqsave(&priv->tx_free_list[qos].lock, flags); + while (skb_to_free > 0) { + struct sk_buff *t = __skb_dequeue(&priv->tx_free_list[qos]); + t->next = to_free_list; + to_free_list = t; + skb_to_free--; + } + spin_unlock_irqrestore(&priv->tx_free_list[qos].lock, flags); + /* Do the actual freeing outside of the lock. */ + while (to_free_list) { + struct sk_buff *t = to_free_list; + to_free_list = to_free_list->next; + dev_kfree_skb_any(t); + } } + total_remaining += skb_queue_len(&priv->tx_free_list[qos]); } -} - -enum hrtimer_restart cvm_oct_restart_tx(struct hrtimer *timer) -{ - struct octeon_ethernet *priv = container_of(timer, struct octeon_ethernet, tx_restart_timer); - struct net_device *dev = cvm_oct_device[priv->port]; - - cvm_oct_free_tx_skbs(priv); - - if (netif_queue_stopped(dev)) + if (total_freed >= 0 && netif_queue_stopped(dev)) netif_wake_queue(dev); - - return HRTIMER_NORESTART; + if (total_remaining) + cvm_oct_kick_tx_poll_watchdog(); } /** @@ -129,6 +156,7 @@ int cvm_oct_xmit(struct sk_buff *skb, struct net_device *dev) struct sk_buff *to_free_list; int32_t skb_to_free; int32_t buffers_to_free; + u32 total_to_clean; unsigned long flags; #if REUSE_SKBUFFS_WITHOUT_FREE unsigned char *fpa_head; @@ -232,7 +260,6 @@ int cvm_oct_xmit(struct sk_buff *skb, struct net_device *dev) pko_command.s.subone0 = 1; pko_command.s.dontfree = 1; - pko_command.s.reg0 = priv->fau + qos * 4; /* Build the PKO buffer pointer */ hw_buffer.u64 = 0; @@ -327,7 +354,6 @@ int cvm_oct_xmit(struct sk_buff *skb, struct net_device *dev) * We can use this buffer in the FPA. We don't need the FAU * update anymore */ - pko_command.s.reg0 = 0; pko_command.s.dontfree = 0; hw_buffer.s.back = ((unsigned long)skb->data >> 7) - ((unsigned long)fpa_head >> 7); @@ -384,15 +410,17 @@ dont_put_skbuff_in_hw: * If we're sending faster than the receive can free them then * don't do the HW free. */ - if ((buffers_to_free < -100) && !pko_command.s.dontfree) { + if ((buffers_to_free < -100) && !pko_command.s.dontfree) pko_command.s.dontfree = 1; - pko_command.s.reg0 = priv->fau + qos * 4; - } - if (pko_command.s.dontfree) + if (pko_command.s.dontfree) { queue_type = QUEUE_CORE; - else + pko_command.s.reg0 = priv->fau+qos*4; + } else { queue_type = QUEUE_HW; + } + if (USE_ASYNC_IOBDMA) + cvmx_fau_async_fetch_and_add32(CVMX_SCR_SCRATCH, FAU_TOTAL_TX_TO_CLEAN, 1); spin_lock_irqsave(&priv->tx_free_list[qos].lock, flags); @@ -402,10 +430,7 @@ dont_put_skbuff_in_hw: /* Drop the lock when notifying the core. */ spin_unlock_irqrestore(&priv->tx_free_list[qos].lock, flags); netif_stop_queue(dev); - hrtimer_start(&priv->tx_restart_timer, - priv->tx_restart_interval, HRTIMER_MODE_REL); spin_lock_irqsave(&priv->tx_free_list[qos].lock, flags); - } else { /* If not using normal queueing. */ queue_type = QUEUE_DROP; @@ -460,11 +485,27 @@ skip_xmit: } if (USE_ASYNC_IOBDMA) { + CVMX_SYNCIOBDMA; + total_to_clean = cvmx_scratch_read64(CVMX_SCR_SCRATCH); /* Restore the scratch area */ cvmx_scratch_write64(CVMX_SCR_SCRATCH, old_scratch); cvmx_scratch_write64(CVMX_SCR_SCRATCH + 8, old_scratch2); + } else { + total_to_clean = cvmx_fau_fetch_and_add32(FAU_TOTAL_TX_TO_CLEAN, 1); } + if (total_to_clean & 0x3ff) { + /* + * Schedule the cleanup tasklet every 1024 packets for + * the pathological case of high traffic on one port + * delaying clean up of packets on a different port + * that is blocked waiting for the cleanup. + */ + tasklet_schedule(&cvm_oct_tx_cleanup_tasklet); + } + + cvm_oct_kick_tx_poll_watchdog(); + return NETDEV_TX_OK; } @@ -624,7 +665,7 @@ int cvm_oct_xmit_pow(struct sk_buff *skb, struct net_device *dev) * * @dev: Device being shutdown */ -void cvm_oct_tx_shutdown(struct net_device *dev) +void cvm_oct_tx_shutdown_dev(struct net_device *dev) { struct octeon_ethernet *priv = netdev_priv(dev); unsigned long flags; @@ -638,3 +679,45 @@ void cvm_oct_tx_shutdown(struct net_device *dev) spin_unlock_irqrestore(&priv->tx_free_list[qos].lock, flags); } } + +static void cvm_oct_tx_do_cleanup(unsigned long arg) +{ + int port; + + for (port = 0; port < TOTAL_NUMBER_OF_PORTS; port++) { + if (cvm_oct_device[port]) { + struct net_device *dev = cvm_oct_device[port]; + cvm_oct_free_tx_skbs(dev); + } + } +} + +static irqreturn_t cvm_oct_tx_cleanup_watchdog(int cpl, void *dev_id) +{ + /* Disable the interrupt. */ + cvmx_write_csr(CVMX_CIU_TIMX(1), 0); + /* Do the work in the tasklet. */ + tasklet_schedule(&cvm_oct_tx_cleanup_tasklet); + return IRQ_HANDLED; +} + +void cvm_oct_tx_initialize(void) +{ + int i; + + /* Disable the interrupt. */ + cvmx_write_csr(CVMX_CIU_TIMX(1), 0); + /* Register an IRQ hander for to receive CIU_TIMX(1) interrupts */ + i = request_irq(OCTEON_IRQ_TIMER1, + cvm_oct_tx_cleanup_watchdog, 0, + "Ethernet", cvm_oct_device); + + if (i) + panic("Could not acquire Ethernet IRQ %d\n", OCTEON_IRQ_TIMER1); +} + +void cvm_oct_tx_shutdown(void) +{ + /* Free the interrupt handler */ + free_irq(OCTEON_IRQ_TIMER1, cvm_oct_device); +} diff --git a/drivers/staging/octeon/ethernet-tx.h b/drivers/staging/octeon/ethernet-tx.h index b628d8c..547680c 100644 --- a/drivers/staging/octeon/ethernet-tx.h +++ b/drivers/staging/octeon/ethernet-tx.h @@ -29,6 +29,6 @@ int cvm_oct_xmit(struct sk_buff *skb, struct net_device *dev); int cvm_oct_xmit_pow(struct sk_buff *skb, struct net_device *dev); int cvm_oct_transmit_qos(struct net_device *dev, void *work_queue_entry, int do_free, int qos); -void cvm_oct_tx_shutdown(struct net_device *dev); -void cvm_oct_free_tx_skbs(struct octeon_ethernet *priv); -enum hrtimer_restart cvm_oct_restart_tx(struct hrtimer *timer); +void cvm_oct_tx_initialize(void); +void cvm_oct_tx_shutdown(void); +void cvm_oct_tx_shutdown_dev(struct net_device *dev); diff --git a/drivers/staging/octeon/ethernet.c b/drivers/staging/octeon/ethernet.c index 1771c10..f2ec8a6 100644 --- a/drivers/staging/octeon/ethernet.c +++ b/drivers/staging/octeon/ethernet.c @@ -140,6 +140,8 @@ atomic_t cvm_oct_poll_queue_stopping = ATOMIC_INIT(0); */ struct net_device *cvm_oct_device[TOTAL_NUMBER_OF_PORTS]; +u64 cvm_oct_tx_poll_interval; + static void cvm_oct_rx_refill_worker(struct work_struct *work); static DECLARE_DELAYED_WORK(cvm_oct_rx_refill_work, cvm_oct_rx_refill_worker); @@ -159,18 +161,19 @@ static void cvm_oct_rx_refill_worker(struct work_struct *work) &cvm_oct_rx_refill_work, HZ); } -static void cvm_oct_tx_clean_worker(struct work_struct *work) +static void cvm_oct_preiodic_worker(struct work_struct *work) { struct octeon_ethernet *priv = container_of(work, struct octeon_ethernet, - tx_clean_work.work); + port_periodic_work.work); if (priv->poll) priv->poll(cvm_oct_device[priv->port]); - cvm_oct_free_tx_skbs(priv); + cvm_oct_device[priv->port]->netdev_ops->ndo_get_stats(cvm_oct_device[priv->port]); + if (!atomic_read(&cvm_oct_poll_queue_stopping)) - queue_delayed_work(cvm_oct_poll_queue, &priv->tx_clean_work, HZ); + queue_delayed_work(cvm_oct_poll_queue, &priv->port_periodic_work, HZ); } /** @@ -662,6 +665,9 @@ static int __init cvm_oct_init_module(void) */ cvmx_fau_atomic_write32(FAU_NUM_PACKET_BUFFERS_TO_FREE, 0); + /* Initialize the FAU used for counting tx SKBs that need to be freed */ + cvmx_fau_atomic_write32(FAU_TOTAL_TX_TO_CLEAN, 0); + if ((pow_send_group != -1)) { struct net_device *dev; pr_info("\tConfiguring device for POW only access\n"); @@ -670,18 +676,6 @@ static int __init cvm_oct_init_module(void) /* Initialize the device private structure. */ struct octeon_ethernet *priv = netdev_priv(dev); - hrtimer_init(&priv->tx_restart_timer, - CLOCK_MONOTONIC, - HRTIMER_MODE_REL); - priv->tx_restart_timer.function = cvm_oct_restart_tx; - - /* - * Default for 10GE 5000nS enough time to - * transmit about 100 64byte packtes. 1GE - * interfaces will get 50000nS below. - */ - priv->tx_restart_interval = ktime_set(0, 5000); - dev->netdev_ops = &cvm_oct_pow_netdev_ops; priv->imode = CVMX_HELPER_INTERFACE_MODE_DISABLED; priv->port = CVMX_PIP_NUM_INPUT_PORTS; @@ -725,9 +719,8 @@ static int __init cvm_oct_init_module(void) /* Initialize the device private structure. */ priv = netdev_priv(dev); - INIT_DELAYED_WORK(&priv->tx_clean_work, - cvm_oct_tx_clean_worker); - + INIT_DELAYED_WORK(&priv->port_periodic_work, + cvm_oct_preiodic_worker); priv->imode = imode; priv->port = port; priv->queue = cvmx_pko_get_base_queue(priv->port); @@ -763,7 +756,6 @@ static int __init cvm_oct_init_module(void) case CVMX_HELPER_INTERFACE_MODE_SGMII: dev->netdev_ops = &cvm_oct_sgmii_netdev_ops; - priv->tx_restart_interval = ktime_set(0, 50000); strcpy(dev->name, "eth%d"); break; @@ -775,7 +767,6 @@ static int __init cvm_oct_init_module(void) case CVMX_HELPER_INTERFACE_MODE_RGMII: case CVMX_HELPER_INTERFACE_MODE_GMII: dev->netdev_ops = &cvm_oct_rgmii_netdev_ops; - priv->tx_restart_interval = ktime_set(0, 50000); strcpy(dev->name, "eth%d"); break; } @@ -793,13 +784,19 @@ static int __init cvm_oct_init_module(void) cvmx_pko_get_num_queues(priv->port) * sizeof(uint32_t); queue_delayed_work(cvm_oct_poll_queue, - &priv->tx_clean_work, HZ); + &priv->port_periodic_work, HZ); } } } + cvm_oct_tx_initialize(); cvm_oct_rx_initialize(); + /* + * 150 uS: about 10 1500-byte packtes at 1GE. + */ + cvm_oct_tx_poll_interval = 150 * (octeon_get_clock_rate() / 1000000); + queue_delayed_work(cvm_oct_poll_queue, &cvm_oct_rx_refill_work, HZ); return 0; @@ -826,6 +823,8 @@ static void __exit cvm_oct_cleanup_module(void) cancel_delayed_work_sync(&cvm_oct_rx_refill_work); cvm_oct_rx_shutdown(); + cvm_oct_tx_shutdown(); + cvmx_pko_disable(); /* Free the ethernet devices */ @@ -833,9 +832,9 @@ static void __exit cvm_oct_cleanup_module(void) if (cvm_oct_device[port]) { struct net_device *dev = cvm_oct_device[port]; struct octeon_ethernet *priv = netdev_priv(dev); - cancel_delayed_work_sync(&priv->tx_clean_work); + cancel_delayed_work_sync(&priv->port_periodic_work); - cvm_oct_tx_shutdown(dev); + cvm_oct_tx_shutdown_dev(dev); unregister_netdev(dev); kfree(dev); cvm_oct_device[port] = NULL; diff --git a/drivers/staging/octeon/octeon-ethernet.h b/drivers/staging/octeon/octeon-ethernet.h index 8d09210..db2a3cc 100644 --- a/drivers/staging/octeon/octeon-ethernet.h +++ b/drivers/staging/octeon/octeon-ethernet.h @@ -4,7 +4,7 @@ * Contact: support@caviumnetworks.com * This file is part of the OCTEON SDK * - * Copyright (c) 2003-2007 Cavium Networks + * Copyright (c) 2003-2010 Cavium Networks * * This file is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License, Version 2, as @@ -31,8 +31,6 @@ #ifndef OCTEON_ETHERNET_H #define OCTEON_ETHERNET_H -#include - /** * This is the definition of the Ethernet driver's private * driver state stored in netdev_priv(dev). @@ -59,9 +57,7 @@ struct octeon_ethernet { uint64_t link_info; /* Called periodically to check link status */ void (*poll) (struct net_device *dev); - struct hrtimer tx_restart_timer; - ktime_t tx_restart_interval; - struct delayed_work tx_clean_work; + struct delayed_work port_periodic_work; struct work_struct port_work; /* may be unused. */ }; @@ -101,6 +97,7 @@ extern char pow_send_list[]; extern struct net_device *cvm_oct_device[]; extern struct workqueue_struct *cvm_oct_poll_queue; extern atomic_t cvm_oct_poll_queue_stopping; +extern u64 cvm_oct_tx_poll_interval; extern int max_rx_cpus; extern int rx_napi_weight; -- 1.6.6 From David.Daney@caviumnetworks.com Mon Feb 15 21:14:47 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 15 Feb 2010 21:14:52 +0100 (CET) Received: from mail3.caviumnetworks.com ([12.108.191.235]:19978 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492184Ab0BOUNi (ORCPT ); Mon, 15 Feb 2010 21:13:38 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Mon, 15 Feb 2010 12:13:43 -0800 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Mon, 15 Feb 2010 12:13:33 -0800 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Mon, 15 Feb 2010 12:13:32 -0800 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.3/8.14.2) with ESMTP id o1FKDUOU003556; Mon, 15 Feb 2010 12:13:30 -0800 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.3/8.14.3/Submit) id o1FKDUoX003555; Mon, 15 Feb 2010 12:13:30 -0800 From: David Daney To: ralf@linux-mips.org, linux-mips@linux-mips.org, netdev@vger.kernel.org, gregkh@suse.de Cc: David Daney Subject: [PATCH 3/4] MIPS: Octeon: Do proper acknowledgment of CIU timer interrupts. Date: Mon, 15 Feb 2010 12:13:18 -0800 Message-Id: <1266264799-3510-3-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.6.6 In-Reply-To: <4B79AAA6.60005@caviumnetworks.com> References: <4B79AAA6.60005@caviumnetworks.com> X-OriginalArrivalTime: 15 Feb 2010 20:13:32.0801 (UTC) FILETIME=[58D47710:01CAAE7B] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25927 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Signed-off-by: David Daney --- arch/mips/cavium-octeon/octeon-irq.c | 67 ++++++++++++++++++++++++++++++++-- 1 files changed, 63 insertions(+), 4 deletions(-) diff --git a/arch/mips/cavium-octeon/octeon-irq.c b/arch/mips/cavium-octeon/octeon-irq.c index 1460d08..0bc79dc 100644 --- a/arch/mips/cavium-octeon/octeon-irq.c +++ b/arch/mips/cavium-octeon/octeon-irq.c @@ -51,9 +51,6 @@ static void octeon_irq_core_eoi(unsigned int irq) */ if (desc->status & IRQ_DISABLED) return; - - /* There is a race here. We should fix it. */ - /* * We don't need to disable IRQs to make these atomic since * they are already disabled earlier in the low level @@ -202,6 +199,29 @@ static void octeon_irq_ciu0_ack_v2(unsigned int irq) } /* + * CIU timer type interrupts must be acknoleged by writing a '1' bit + * to their sum0 bit. + */ +static void octeon_irq_ciu0_timer_ack(unsigned int irq) +{ + int index = cvmx_get_core_num() * 2; + uint64_t mask = 1ull << (irq - OCTEON_IRQ_WORKQ0); + cvmx_write_csr(CVMX_CIU_INTX_SUM0(index), mask); +} + +static void octeon_irq_ciu0_timer_ack_v1(unsigned int irq) +{ + octeon_irq_ciu0_timer_ack(irq); + octeon_irq_ciu0_ack(irq); +} + +static void octeon_irq_ciu0_timer_ack_v2(unsigned int irq) +{ + octeon_irq_ciu0_timer_ack(irq); + octeon_irq_ciu0_ack_v2(irq); +} + +/* * Enable the irq on the current core for chips that have the EN*_W1{S,C} * registers. */ @@ -304,6 +324,28 @@ static struct irq_chip octeon_irq_chip_ciu0 = { #endif }; +static struct irq_chip octeon_irq_chip_ciu0_timer_v2 = { + .name = "CIU0-T", + .enable = octeon_irq_ciu0_enable_v2, + .disable = octeon_irq_ciu0_disable_all_v2, + .ack = octeon_irq_ciu0_timer_ack_v2, + .eoi = octeon_irq_ciu0_eoi_v2, +#ifdef CONFIG_SMP + .set_affinity = octeon_irq_ciu0_set_affinity_v2, +#endif +}; + +static struct irq_chip octeon_irq_chip_ciu0_timer = { + .name = "CIU0-T", + .enable = octeon_irq_ciu0_enable, + .disable = octeon_irq_ciu0_disable, + .ack = octeon_irq_ciu0_timer_ack_v1, + .eoi = octeon_irq_ciu0_eoi, +#ifdef CONFIG_SMP + .set_affinity = octeon_irq_ciu0_set_affinity, +#endif +}; + static void octeon_irq_ciu1_ack(unsigned int irq) { @@ -587,6 +629,7 @@ void __init arch_init_irq(void) { int irq; struct irq_chip *chip0; + struct irq_chip *chip0_timer; struct irq_chip *chip1; #ifdef CONFIG_SMP @@ -602,9 +645,11 @@ void __init arch_init_irq(void) OCTEON_IS_MODEL(OCTEON_CN56XX_PASS2_X) || OCTEON_IS_MODEL(OCTEON_CN52XX_PASS2_X)) { chip0 = &octeon_irq_chip_ciu0_v2; + chip0_timer = &octeon_irq_chip_ciu0_timer_v2; chip1 = &octeon_irq_chip_ciu1_v2; } else { chip0 = &octeon_irq_chip_ciu0; + chip0_timer = &octeon_irq_chip_ciu0_timer; chip1 = &octeon_irq_chip_ciu1; } @@ -618,7 +663,21 @@ void __init arch_init_irq(void) /* 24 - 87 CIU_INT_SUM0 */ for (irq = OCTEON_IRQ_WORKQ0; irq <= OCTEON_IRQ_BOOTDMA; irq++) { - set_irq_chip_and_handler(irq, chip0, handle_percpu_irq); + switch (irq) { + case OCTEON_IRQ_GMX_DRP0: + case OCTEON_IRQ_GMX_DRP1: + case OCTEON_IRQ_IPD_DRP: + case OCTEON_IRQ_KEY_ZERO: + case OCTEON_IRQ_TIMER0: + case OCTEON_IRQ_TIMER1: + case OCTEON_IRQ_TIMER2: + case OCTEON_IRQ_TIMER3: + set_irq_chip_and_handler(irq, chip0_timer, handle_percpu_irq); + break; + default: + set_irq_chip_and_handler(irq, chip0, handle_percpu_irq); + break; + } } /* 88 - 151 CIU_INT_SUM1 */ -- 1.6.6 From eric.dumazet@gmail.com Mon Feb 15 21:28:04 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 15 Feb 2010 21:28:09 +0100 (CET) Received: from mail-bw0-f215.google.com ([209.85.218.215]:53412 "EHLO mail-bw0-f215.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492190Ab0BOU2E (ORCPT ); Mon, 15 Feb 2010 21:28:04 +0100 Received: by bwz7 with SMTP id 7so4290063bwz.26 for ; Mon, 15 Feb 2010 12:27:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:subject:from:to:cc :in-reply-to:references:content-type:date:message-id:mime-version :x-mailer:content-transfer-encoding; bh=9TmwcbiFEptboJxWGBqb3xk7p0x8bqiLkREGORZG/yU=; b=PeY4XH2BZpMDN8gvs6aFUFIGE9zp+DK6xsWIX+GYrXKFkME/Zb0T1qg01J/eoiK0Tp 1MwF7wf4NSUFaUGhsUyVHMG2v3X9S8Y4mtT251Og02mBZ6ubIqCDPsN4slESzmmUJoHY vN8lNmirjswQYzSZjg3/HHb50eO2C1ErLK/so= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=subject:from:to:cc:in-reply-to:references:content-type:date :message-id:mime-version:x-mailer:content-transfer-encoding; b=tKr231hEVLTUN3L7xBntxZc4wfghZkJZ1MvlE6lgM7lvlgHdTSK8nKegPIlvWp+Djx 2sIqkjksIW//5CBge3vnTyMo3z3x+XxBYJMdx2WoZoTZIHdaWy2JFmGuKt3PcNhYNdfL GXVLa8HpP18EQxs4K6Xwi0Krfc7TRtRYcC7vo= Received: by 10.204.49.88 with SMTP id u24mr3607804bkf.44.1266265678493; Mon, 15 Feb 2010 12:27:58 -0800 (PST) Received: from ?127.0.0.1? (gw1.cosmosbay.com [212.99.114.194]) by mx.google.com with ESMTPS id 16sm2848385bwz.3.2010.02.15.12.27.54 (version=SSLv3 cipher=RC4-MD5); Mon, 15 Feb 2010 12:27:55 -0800 (PST) Subject: Re: [PATCH 4/4] Staging: Octeon: Free transmit SKBs in a timely manner. From: Eric Dumazet To: David Daney Cc: ralf@linux-mips.org, linux-mips@linux-mips.org, netdev@vger.kernel.org, gregkh@suse.de In-Reply-To: <1266264799-3510-4-git-send-email-ddaney@caviumnetworks.com> References: <4B79AAA6.60005@caviumnetworks.com> <1266264799-3510-4-git-send-email-ddaney@caviumnetworks.com> Content-Type: text/plain; charset="UTF-8" Date: Mon, 15 Feb 2010 21:27:53 +0100 Message-ID: <1266265673.2859.5.camel@edumazet-laptop> Mime-Version: 1.0 X-Mailer: Evolution 2.28.1 Content-Transfer-Encoding: 8bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25928 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: eric.dumazet@gmail.com Precedence: bulk X-list: linux-mips Le lundi 15 février 2010 à 12:13 -0800, David Daney a écrit : > If we wait for the once-per-second cleanup to free transmit SKBs, > sockets with small transmit buffer sizes might spend most of their > time blocked waiting for the cleanup. > > Normally we do a cleanup for each transmitted packet. We add a > watchdog type timer so that we also schedule a timeout for 150uS after > a packet is transmitted. The watchdog is reset for each transmitted > packet, so for high packet rates, it never expires. At these high > rates, the cleanups are done for each packet so the extra watchdog > initiated cleanups are not needed. s/needed/fired/ Hmm, but re-arming a timer for each transmited packet must have a cost ? > > Signed-off-by: David Daney Is there any particular reason periodic is spelled preiodic ? > --- > } > > -static void cvm_oct_tx_clean_worker(struct work_struct *work) > +static void cvm_oct_preiodic_worker(struct work_struct *work) > { > - INIT_DELAYED_WORK(&priv->tx_clean_work, > - cvm_oct_tx_clean_worker); > - > + INIT_DELAYED_WORK(&priv->port_periodic_work, > + cvm_oct_preiodic_worker); From David.Daney@caviumnetworks.com Mon Feb 15 21:41:10 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 15 Feb 2010 21:41:14 +0100 (CET) Received: from mail3.caviumnetworks.com ([12.108.191.235]:1385 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492190Ab0BOUlK (ORCPT ); Mon, 15 Feb 2010 21:41:10 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Mon, 15 Feb 2010 12:41:18 -0800 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Mon, 15 Feb 2010 12:41:08 -0800 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Mon, 15 Feb 2010 12:41:08 -0800 Message-ID: <4B79B15F.7030506@caviumnetworks.com> Date: Mon, 15 Feb 2010 12:41:03 -0800 From: David Daney User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.7) Gecko/20100120 Fedora/3.0.1-1.fc12 Thunderbird/3.0.1 MIME-Version: 1.0 To: Eric Dumazet CC: ralf@linux-mips.org, linux-mips@linux-mips.org, netdev@vger.kernel.org, gregkh@suse.de Subject: Re: [PATCH 4/4] Staging: Octeon: Free transmit SKBs in a timely manner. References: <4B79AAA6.60005@caviumnetworks.com> <1266264799-3510-4-git-send-email-ddaney@caviumnetworks.com> <1266265673.2859.5.camel@edumazet-laptop> In-Reply-To: <1266265673.2859.5.camel@edumazet-laptop> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-OriginalArrivalTime: 15 Feb 2010 20:41:08.0265 (UTC) FILETIME=[33903990:01CAAE7F] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25929 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips On 02/15/2010 12:27 PM, Eric Dumazet wrote: > Le lundi 15 février 2010 à 12:13 -0800, David Daney a écrit : >> If we wait for the once-per-second cleanup to free transmit SKBs, >> sockets with small transmit buffer sizes might spend most of their >> time blocked waiting for the cleanup. >> >> Normally we do a cleanup for each transmitted packet. We add a >> watchdog type timer so that we also schedule a timeout for 150uS after >> a packet is transmitted. The watchdog is reset for each transmitted >> packet, so for high packet rates, it never expires. At these high >> rates, the cleanups are done for each packet so the extra watchdog >> initiated cleanups are not needed. > > s/needed/fired/ > or perhaps s/are not needed/are neither needed nor fired/ > Hmm, but re-arming a timer for each transmited packet must have a cost ? > The cost is fairly low (less than 10 processor clock cycles). We didn't add this for amusement, people actually do things like only send UDP packets from userspace. Since we can fill the transmit queue faster than it is emptied, the socket transmit buffer is quickly consumed. If we don't free the SKBs in short order, the transmitting process get to take a long sleep (until our previous once per second clean up task was run). >> >> Signed-off-by: David Daney > > Is there any particular reason periodic is spelled preiodic ? Ha! No good reason. I will correct the spelling. Thanks, David Daney > >> --- >> } >> >> -static void cvm_oct_tx_clean_worker(struct work_struct *work) >> +static void cvm_oct_preiodic_worker(struct work_struct *work) >> { > > > >> - INIT_DELAYED_WORK(&priv->tx_clean_work, >> - cvm_oct_tx_clean_worker); >> - >> + INIT_DELAYED_WORK(&priv->port_periodic_work, >> + cvm_oct_preiodic_worker); > > > > From eric.dumazet@gmail.com Mon Feb 15 22:11:22 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 15 Feb 2010 22:11:25 +0100 (CET) Received: from mail-bw0-f215.google.com ([209.85.218.215]:60274 "EHLO mail-bw0-f215.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492234Ab0BOVLW (ORCPT ); Mon, 15 Feb 2010 22:11:22 +0100 Received: by bwz7 with SMTP id 7so4319799bwz.26 for ; Mon, 15 Feb 2010 13:11:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:subject:from:to:cc :in-reply-to:references:content-type:date:message-id:mime-version :x-mailer:content-transfer-encoding; bh=Xq6Xyg+3Idj776ASAQiLwS8t/hOE18xj9DvxZkaePpk=; b=Fi6Vg6BL99KT8UyszhhugTNyjAeCg8t0KTIXpporu3pK35vI81dyh4+CZVmGIBxEwP zGBSg56m//Lut4HQtR09kG35bLmYVW4phApVBqYWA6sH00V419NKcTG3tPXeEL/sytHv domIChspIoTKUnPTnzQ0MgSx559Eay+K+7Z8Q= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=subject:from:to:cc:in-reply-to:references:content-type:date :message-id:mime-version:x-mailer:content-transfer-encoding; b=R2vBYePmaC61YWJLDdqwCccokQt911TYPcyQpAB8bn5TslEoLgJBA//LdGwyRazV3D lulv7EZu54J4wb8OvEjDn+dzq/3+2zoY+xehxkkuVNUFKt+WnpPWLg+M0DSAJH2IxB8Y vTmmCGd/kV4mubg3zmBIVW2l53gOI+2DWdYUQ= Received: by 10.204.39.211 with SMTP id h19mr1297771bke.164.1266268275147; Mon, 15 Feb 2010 13:11:15 -0800 (PST) Received: from ?127.0.0.1? (gw1.cosmosbay.com [212.99.114.194]) by mx.google.com with ESMTPS id 13sm2840106bwz.14.2010.02.15.13.11.12 (version=SSLv3 cipher=RC4-MD5); Mon, 15 Feb 2010 13:11:13 -0800 (PST) Subject: Re: [PATCH 4/4] Staging: Octeon: Free transmit SKBs in a timely manner. From: Eric Dumazet To: David Daney Cc: ralf@linux-mips.org, linux-mips@linux-mips.org, netdev@vger.kernel.org, gregkh@suse.de In-Reply-To: <4B79B15F.7030506@caviumnetworks.com> References: <4B79AAA6.60005@caviumnetworks.com> <1266264799-3510-4-git-send-email-ddaney@caviumnetworks.com> <1266265673.2859.5.camel@edumazet-laptop> <4B79B15F.7030506@caviumnetworks.com> Content-Type: text/plain; charset="UTF-8" Date: Mon, 15 Feb 2010 22:11:11 +0100 Message-ID: <1266268271.2859.22.camel@edumazet-laptop> Mime-Version: 1.0 X-Mailer: Evolution 2.28.1 Content-Transfer-Encoding: 8bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25930 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: eric.dumazet@gmail.com Precedence: bulk X-list: linux-mips Le lundi 15 février 2010 à 12:41 -0800, David Daney a écrit : > On 02/15/2010 12:27 PM, Eric Dumazet wrote: > > Le lundi 15 février 2010 à 12:13 -0800, David Daney a écrit : > >> If we wait for the once-per-second cleanup to free transmit SKBs, > >> sockets with small transmit buffer sizes might spend most of their > >> time blocked waiting for the cleanup. > >> > >> Normally we do a cleanup for each transmitted packet. We add a > >> watchdog type timer so that we also schedule a timeout for 150uS after > >> a packet is transmitted. The watchdog is reset for each transmitted > >> packet, so for high packet rates, it never expires. At these high > >> rates, the cleanups are done for each packet so the extra watchdog > >> initiated cleanups are not needed. > > > > s/needed/fired/ > > > > or perhaps s/are not needed/are neither needed nor fired/ > > > Hmm, but re-arming a timer for each transmited packet must have a cost ? > > > > The cost is fairly low (less than 10 processor clock cycles). We didn't > add this for amusement, people actually do things like only send UDP > packets from userspace. Since we can fill the transmit queue faster > than it is emptied, the socket transmit buffer is quickly consumed. If > we don't free the SKBs in short order, the transmitting process get to > take a long sleep (until our previous once per second clean up task was > run). I understand this, but traditionaly, NIC drivers dont use a timer, but a 'TX complete' interrupt, that usually fires a few us after packet submission on Gigabit speed. A fast program could try to send X small udp packets in less than 150 us, X being greater than the size of your TX ring. So your patch makes the window smaller, but it still is there (at physical layer, we'll see a burst of packets, a ~100us delay, then a second burst) From gregkh@suse.de Mon Feb 15 22:41:46 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 15 Feb 2010 22:41:50 +0100 (CET) Received: from cantor.suse.de ([195.135.220.2]:47900 "EHLO mx1.suse.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492236Ab0BOVlq (ORCPT ); Mon, 15 Feb 2010 22:41:46 +0100 Received: from relay2.suse.de (charybdis-ext.suse.de [195.135.221.2]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.suse.de (Postfix) with ESMTP id 5920D6CB00; Mon, 15 Feb 2010 22:41:46 +0100 (CET) Date: Mon, 15 Feb 2010 13:05:58 -0800 From: Greg KH To: David Daney Cc: ralf.baechle@gmail.com, linux-mips , Netdev Subject: Re: [PATCH 0/4] Improvements to octeon_ethernet. Message-ID: <20100215210558.GA27325@suse.de> References: <4B79AAA6.60005@caviumnetworks.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <4B79AAA6.60005@caviumnetworks.com> User-Agent: Mutt/1.5.17 (2007-11-01) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25931 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: gregkh@suse.de Precedence: bulk X-list: linux-mips On Mon, Feb 15, 2010 at 12:12:22PM -0800, David Daney wrote: > Here are a couple of improvements to the octeon_ethernet in > drivers/staging/octeon. The first patch is just cleanup, the rest are > genuine bug fixes. > > I will reply with the four patches. > > We may want to merge via Ralf's linux-mips.org tree as Octeon is > infact a MIPS based SOC and he has a bunch of other patches queued > there that these depend on. That's fine with me for them to go through that way. thanks, greg k-h From David.Daney@caviumnetworks.com Mon Feb 15 23:05:32 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 15 Feb 2010 23:05:36 +0100 (CET) Received: from mail3.caviumnetworks.com ([12.108.191.235]:2452 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492237Ab0BOWFc (ORCPT ); Mon, 15 Feb 2010 23:05:32 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Mon, 15 Feb 2010 14:05:38 -0800 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Mon, 15 Feb 2010 14:05:23 -0800 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Mon, 15 Feb 2010 14:05:23 -0800 Message-ID: <4B79C522.4040405@caviumnetworks.com> Date: Mon, 15 Feb 2010 14:05:22 -0800 From: David Daney User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.7) Gecko/20100120 Fedora/3.0.1-1.fc12 Thunderbird/3.0.1 MIME-Version: 1.0 To: Eric Dumazet CC: ralf@linux-mips.org, linux-mips@linux-mips.org, netdev@vger.kernel.org, gregkh@suse.de Subject: Re: [PATCH 4/4] Staging: Octeon: Free transmit SKBs in a timely manner. References: <4B79AAA6.60005@caviumnetworks.com> <1266264799-3510-4-git-send-email-ddaney@caviumnetworks.com> <1266265673.2859.5.camel@edumazet-laptop> <4B79B15F.7030506@caviumnetworks.com> <1266268271.2859.22.camel@edumazet-laptop> In-Reply-To: <1266268271.2859.22.camel@edumazet-laptop> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-OriginalArrivalTime: 15 Feb 2010 22:05:23.0251 (UTC) FILETIME=[F891E030:01CAAE8A] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25932 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips On 02/15/2010 01:11 PM, Eric Dumazet wrote: > Le lundi 15 février 2010 à 12:41 -0800, David Daney a écrit : >> On 02/15/2010 12:27 PM, Eric Dumazet wrote: >>> Le lundi 15 février 2010 à 12:13 -0800, David Daney a écrit : >>>> If we wait for the once-per-second cleanup to free transmit SKBs, >>>> sockets with small transmit buffer sizes might spend most of their >>>> time blocked waiting for the cleanup. >>>> >>>> Normally we do a cleanup for each transmitted packet. We add a >>>> watchdog type timer so that we also schedule a timeout for 150uS after >>>> a packet is transmitted. The watchdog is reset for each transmitted >>>> packet, so for high packet rates, it never expires. At these high >>>> rates, the cleanups are done for each packet so the extra watchdog >>>> initiated cleanups are not needed. >>> >>> s/needed/fired/ >>> >> >> or perhaps s/are not needed/are neither needed nor fired/ >> >>> Hmm, but re-arming a timer for each transmited packet must have a cost ? >>> >> >> The cost is fairly low (less than 10 processor clock cycles). We didn't >> add this for amusement, people actually do things like only send UDP >> packets from userspace. Since we can fill the transmit queue faster >> than it is emptied, the socket transmit buffer is quickly consumed. If >> we don't free the SKBs in short order, the transmitting process get to >> take a long sleep (until our previous once per second clean up task was >> run). > > I understand this, but traditionaly, NIC drivers dont use a timer, but a > 'TX complete' interrupt, that usually fires a few us after packet > submission on Gigabit speed. > Indeed. Lacking this type of interrupt, the watchdog seemed the best short term solution. I am investigating the possibility of feeding TX complete notifications back through the RX path where it is possible to generate interrupts. The drawback to this is that it takes a lot more CPU cycles as well as added cache pressure. > A fast program could try to send X small udp packets in less than 150 > us, X being greater than the size of your TX ring. My TX queue (it is not a ring) size can be made arbitrarily large (currently 1000). 64bytes * 1000 packets * 10 bits/packet / 10e9 bits/sec == 640uS. My watchdog will fire after less than 1/4 of the ring capacity is freed. > > So your patch makes the window smaller, but it still is there (at > physical layer, we'll see a burst of packets, a ~100us delay, then a > second burst) > With this patch, there will be no burstiness using default socket buffer sizes and packets of arbitrary size on a standard 1gig port. On the 10gig ports there is the possibility for burstiness as you aptly explain. However, in practice it would be difficult to arrange things to achieve sufficiently high packet rates, so we can live with it like this. David Daney From David.Daney@caviumnetworks.com Tue Feb 16 00:07:05 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 16 Feb 2010 00:07:11 +0100 (CET) Received: from mail3.caviumnetworks.com ([12.108.191.235]:3275 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492244Ab0BOXHF (ORCPT ); Tue, 16 Feb 2010 00:07:05 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Mon, 15 Feb 2010 15:07:11 -0800 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Mon, 15 Feb 2010 15:07:01 -0800 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Mon, 15 Feb 2010 15:07:01 -0800 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.3/8.14.2) with ESMTP id o1FN6v9M014178; Mon, 15 Feb 2010 15:06:57 -0800 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.3/8.14.3/Submit) id o1FN6t3B014177; Mon, 15 Feb 2010 15:06:55 -0800 From: David Daney To: ralf@linux-mips.org, linux-mips@linux-mips.org, netdev@vger.kernel.org, gregkh@suse.de Cc: David Daney , Eric Dumazet Subject: [PATCH 4/4] Staging: Octeon: Free transmit SKBs in a timely manner (v2). Date: Mon, 15 Feb 2010 15:06:47 -0800 Message-Id: <1266275207-14143-1-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.6.6 In-Reply-To: <1266264799-3510-4-git-send-email-ddaney@caviumnetworks.com> References: <1266264799-3510-4-git-send-email-ddaney@caviumnetworks.com> X-OriginalArrivalTime: 15 Feb 2010 23:07:01.0634 (UTC) FILETIME=[94FA5620:01CAAE93] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25933 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips If we wait for the once-per-second cleanup to free transmit SKBs, sockets with small transmit buffer sizes might spend most of their time blocked waiting for the cleanup. Normally we do a cleanup for each transmitted packet. We add a watchdog type timer so that we also schedule a timeout for 150uS after a packet is transmitted. The watchdog is reset for each transmitted packet, so for high packet rates, it never expires. At these high rates, the cleanups are done for each packet so the extra watchdog initiated cleanups are neither needed nor triggered. Signed-off-by: David Daney CC: Eric Dumazet --- This version has spelling and comment changes based on feedback from Eric Dumazet. drivers/staging/octeon/Kconfig | 1 - drivers/staging/octeon/ethernet-defines.h | 5 +- drivers/staging/octeon/ethernet-tx.c | 137 +++++++++++++++++++++++------ drivers/staging/octeon/ethernet-tx.h | 6 +- drivers/staging/octeon/ethernet.c | 47 +++++----- drivers/staging/octeon/octeon-ethernet.h | 9 +-- 6 files changed, 142 insertions(+), 63 deletions(-) diff --git a/drivers/staging/octeon/Kconfig b/drivers/staging/octeon/Kconfig index 579b8f1..638ad6b 100644 --- a/drivers/staging/octeon/Kconfig +++ b/drivers/staging/octeon/Kconfig @@ -3,7 +3,6 @@ config OCTEON_ETHERNET depends on CPU_CAVIUM_OCTEON select PHYLIB select MDIO_OCTEON - select HIGH_RES_TIMERS help This driver supports the builtin ethernet ports on Cavium Networks' products in the Octeon family. This driver supports the diff --git a/drivers/staging/octeon/ethernet-defines.h b/drivers/staging/octeon/ethernet-defines.h index 00a8561..6a2cd50 100644 --- a/drivers/staging/octeon/ethernet-defines.h +++ b/drivers/staging/octeon/ethernet-defines.h @@ -95,10 +95,11 @@ /*#define DONT_WRITEBACK(x) 0 */ /* Maximum number of SKBs to try to free per xmit packet. */ -#define MAX_SKB_TO_FREE 10 #define MAX_OUT_QUEUE_DEPTH 1000 -#define FAU_NUM_PACKET_BUFFERS_TO_FREE (CVMX_FAU_REG_END - sizeof(uint32_t)) +#define FAU_TOTAL_TX_TO_CLEAN (CVMX_FAU_REG_END - sizeof(uint32_t)) +#define FAU_NUM_PACKET_BUFFERS_TO_FREE (FAU_TOTAL_TX_TO_CLEAN - sizeof(uint32_t)) + #define TOTAL_NUMBER_OF_PORTS (CVMX_PIP_NUM_INPUT_PORTS+1) diff --git a/drivers/staging/octeon/ethernet-tx.c b/drivers/staging/octeon/ethernet-tx.c index 62258bd..5175247 100644 --- a/drivers/staging/octeon/ethernet-tx.c +++ b/drivers/staging/octeon/ethernet-tx.c @@ -48,6 +48,7 @@ #include "cvmx-wqe.h" #include "cvmx-fau.h" +#include "cvmx-pip.h" #include "cvmx-pko.h" #include "cvmx-helper.h" @@ -66,6 +67,11 @@ #define GET_SKBUFF_QOS(skb) 0 #endif +static void cvm_oct_tx_do_cleanup(unsigned long arg); +static DECLARE_TASKLET(cvm_oct_tx_cleanup_tasklet, cvm_oct_tx_do_cleanup, 0); + +/* Maximum number of SKBs to try to free per xmit packet. */ +#define MAX_SKB_TO_FREE (MAX_OUT_QUEUE_DEPTH * 2) static inline int32_t cvm_oct_adjust_skb_to_free(int32_t skb_to_free, int fau) { @@ -77,10 +83,24 @@ static inline int32_t cvm_oct_adjust_skb_to_free(int32_t skb_to_free, int fau) return skb_to_free; } -void cvm_oct_free_tx_skbs(struct octeon_ethernet *priv) +static void cvm_oct_kick_tx_poll_watchdog(void) +{ + union cvmx_ciu_timx ciu_timx; + ciu_timx.u64 = 0; + ciu_timx.s.one_shot = 1; + ciu_timx.s.len = cvm_oct_tx_poll_interval; + cvmx_write_csr(CVMX_CIU_TIMX(1), ciu_timx.u64); +} + +void cvm_oct_free_tx_skbs(struct net_device *dev) { int32_t skb_to_free; int qos, queues_per_port; + int total_freed = 0; + int total_remaining = 0; + unsigned long flags; + struct octeon_ethernet *priv = netdev_priv(dev); + queues_per_port = cvmx_pko_get_num_queues(priv->port); /* Drain any pending packets in the free list */ for (qos = 0; qos < queues_per_port; qos++) { @@ -89,24 +109,31 @@ void cvm_oct_free_tx_skbs(struct octeon_ethernet *priv) skb_to_free = cvmx_fau_fetch_and_add32(priv->fau+qos*4, MAX_SKB_TO_FREE); skb_to_free = cvm_oct_adjust_skb_to_free(skb_to_free, priv->fau+qos*4); - while (skb_to_free > 0) { - dev_kfree_skb_any(skb_dequeue(&priv->tx_free_list[qos])); - skb_to_free--; + + total_freed += skb_to_free; + if (skb_to_free > 0) { + struct sk_buff *to_free_list = NULL; + spin_lock_irqsave(&priv->tx_free_list[qos].lock, flags); + while (skb_to_free > 0) { + struct sk_buff *t = __skb_dequeue(&priv->tx_free_list[qos]); + t->next = to_free_list; + to_free_list = t; + skb_to_free--; + } + spin_unlock_irqrestore(&priv->tx_free_list[qos].lock, flags); + /* Do the actual freeing outside of the lock. */ + while (to_free_list) { + struct sk_buff *t = to_free_list; + to_free_list = to_free_list->next; + dev_kfree_skb_any(t); + } } + total_remaining += skb_queue_len(&priv->tx_free_list[qos]); } -} - -enum hrtimer_restart cvm_oct_restart_tx(struct hrtimer *timer) -{ - struct octeon_ethernet *priv = container_of(timer, struct octeon_ethernet, tx_restart_timer); - struct net_device *dev = cvm_oct_device[priv->port]; - - cvm_oct_free_tx_skbs(priv); - - if (netif_queue_stopped(dev)) + if (total_freed >= 0 && netif_queue_stopped(dev)) netif_wake_queue(dev); - - return HRTIMER_NORESTART; + if (total_remaining) + cvm_oct_kick_tx_poll_watchdog(); } /** @@ -129,6 +156,7 @@ int cvm_oct_xmit(struct sk_buff *skb, struct net_device *dev) struct sk_buff *to_free_list; int32_t skb_to_free; int32_t buffers_to_free; + u32 total_to_clean; unsigned long flags; #if REUSE_SKBUFFS_WITHOUT_FREE unsigned char *fpa_head; @@ -232,7 +260,6 @@ int cvm_oct_xmit(struct sk_buff *skb, struct net_device *dev) pko_command.s.subone0 = 1; pko_command.s.dontfree = 1; - pko_command.s.reg0 = priv->fau + qos * 4; /* Build the PKO buffer pointer */ hw_buffer.u64 = 0; @@ -327,7 +354,6 @@ int cvm_oct_xmit(struct sk_buff *skb, struct net_device *dev) * We can use this buffer in the FPA. We don't need the FAU * update anymore */ - pko_command.s.reg0 = 0; pko_command.s.dontfree = 0; hw_buffer.s.back = ((unsigned long)skb->data >> 7) - ((unsigned long)fpa_head >> 7); @@ -384,15 +410,17 @@ dont_put_skbuff_in_hw: * If we're sending faster than the receive can free them then * don't do the HW free. */ - if ((buffers_to_free < -100) && !pko_command.s.dontfree) { + if ((buffers_to_free < -100) && !pko_command.s.dontfree) pko_command.s.dontfree = 1; - pko_command.s.reg0 = priv->fau + qos * 4; - } - if (pko_command.s.dontfree) + if (pko_command.s.dontfree) { queue_type = QUEUE_CORE; - else + pko_command.s.reg0 = priv->fau+qos*4; + } else { queue_type = QUEUE_HW; + } + if (USE_ASYNC_IOBDMA) + cvmx_fau_async_fetch_and_add32(CVMX_SCR_SCRATCH, FAU_TOTAL_TX_TO_CLEAN, 1); spin_lock_irqsave(&priv->tx_free_list[qos].lock, flags); @@ -402,10 +430,7 @@ dont_put_skbuff_in_hw: /* Drop the lock when notifying the core. */ spin_unlock_irqrestore(&priv->tx_free_list[qos].lock, flags); netif_stop_queue(dev); - hrtimer_start(&priv->tx_restart_timer, - priv->tx_restart_interval, HRTIMER_MODE_REL); spin_lock_irqsave(&priv->tx_free_list[qos].lock, flags); - } else { /* If not using normal queueing. */ queue_type = QUEUE_DROP; @@ -460,11 +485,27 @@ skip_xmit: } if (USE_ASYNC_IOBDMA) { + CVMX_SYNCIOBDMA; + total_to_clean = cvmx_scratch_read64(CVMX_SCR_SCRATCH); /* Restore the scratch area */ cvmx_scratch_write64(CVMX_SCR_SCRATCH, old_scratch); cvmx_scratch_write64(CVMX_SCR_SCRATCH + 8, old_scratch2); + } else { + total_to_clean = cvmx_fau_fetch_and_add32(FAU_TOTAL_TX_TO_CLEAN, 1); } + if (total_to_clean & 0x3ff) { + /* + * Schedule the cleanup tasklet every 1024 packets for + * the pathological case of high traffic on one port + * delaying clean up of packets on a different port + * that is blocked waiting for the cleanup. + */ + tasklet_schedule(&cvm_oct_tx_cleanup_tasklet); + } + + cvm_oct_kick_tx_poll_watchdog(); + return NETDEV_TX_OK; } @@ -624,7 +665,7 @@ int cvm_oct_xmit_pow(struct sk_buff *skb, struct net_device *dev) * * @dev: Device being shutdown */ -void cvm_oct_tx_shutdown(struct net_device *dev) +void cvm_oct_tx_shutdown_dev(struct net_device *dev) { struct octeon_ethernet *priv = netdev_priv(dev); unsigned long flags; @@ -638,3 +679,45 @@ void cvm_oct_tx_shutdown(struct net_device *dev) spin_unlock_irqrestore(&priv->tx_free_list[qos].lock, flags); } } + +static void cvm_oct_tx_do_cleanup(unsigned long arg) +{ + int port; + + for (port = 0; port < TOTAL_NUMBER_OF_PORTS; port++) { + if (cvm_oct_device[port]) { + struct net_device *dev = cvm_oct_device[port]; + cvm_oct_free_tx_skbs(dev); + } + } +} + +static irqreturn_t cvm_oct_tx_cleanup_watchdog(int cpl, void *dev_id) +{ + /* Disable the interrupt. */ + cvmx_write_csr(CVMX_CIU_TIMX(1), 0); + /* Do the work in the tasklet. */ + tasklet_schedule(&cvm_oct_tx_cleanup_tasklet); + return IRQ_HANDLED; +} + +void cvm_oct_tx_initialize(void) +{ + int i; + + /* Disable the interrupt. */ + cvmx_write_csr(CVMX_CIU_TIMX(1), 0); + /* Register an IRQ hander for to receive CIU_TIMX(1) interrupts */ + i = request_irq(OCTEON_IRQ_TIMER1, + cvm_oct_tx_cleanup_watchdog, 0, + "Ethernet", cvm_oct_device); + + if (i) + panic("Could not acquire Ethernet IRQ %d\n", OCTEON_IRQ_TIMER1); +} + +void cvm_oct_tx_shutdown(void) +{ + /* Free the interrupt handler */ + free_irq(OCTEON_IRQ_TIMER1, cvm_oct_device); +} diff --git a/drivers/staging/octeon/ethernet-tx.h b/drivers/staging/octeon/ethernet-tx.h index b628d8c..547680c 100644 --- a/drivers/staging/octeon/ethernet-tx.h +++ b/drivers/staging/octeon/ethernet-tx.h @@ -29,6 +29,6 @@ int cvm_oct_xmit(struct sk_buff *skb, struct net_device *dev); int cvm_oct_xmit_pow(struct sk_buff *skb, struct net_device *dev); int cvm_oct_transmit_qos(struct net_device *dev, void *work_queue_entry, int do_free, int qos); -void cvm_oct_tx_shutdown(struct net_device *dev); -void cvm_oct_free_tx_skbs(struct octeon_ethernet *priv); -enum hrtimer_restart cvm_oct_restart_tx(struct hrtimer *timer); +void cvm_oct_tx_initialize(void); +void cvm_oct_tx_shutdown(void); +void cvm_oct_tx_shutdown_dev(struct net_device *dev); diff --git a/drivers/staging/octeon/ethernet.c b/drivers/staging/octeon/ethernet.c index 1771c10..5ee60ab 100644 --- a/drivers/staging/octeon/ethernet.c +++ b/drivers/staging/octeon/ethernet.c @@ -140,6 +140,8 @@ atomic_t cvm_oct_poll_queue_stopping = ATOMIC_INIT(0); */ struct net_device *cvm_oct_device[TOTAL_NUMBER_OF_PORTS]; +u64 cvm_oct_tx_poll_interval; + static void cvm_oct_rx_refill_worker(struct work_struct *work); static DECLARE_DELAYED_WORK(cvm_oct_rx_refill_work, cvm_oct_rx_refill_worker); @@ -159,18 +161,19 @@ static void cvm_oct_rx_refill_worker(struct work_struct *work) &cvm_oct_rx_refill_work, HZ); } -static void cvm_oct_tx_clean_worker(struct work_struct *work) +static void cvm_oct_periodic_worker(struct work_struct *work) { struct octeon_ethernet *priv = container_of(work, struct octeon_ethernet, - tx_clean_work.work); + port_periodic_work.work); if (priv->poll) priv->poll(cvm_oct_device[priv->port]); - cvm_oct_free_tx_skbs(priv); + cvm_oct_device[priv->port]->netdev_ops->ndo_get_stats(cvm_oct_device[priv->port]); + if (!atomic_read(&cvm_oct_poll_queue_stopping)) - queue_delayed_work(cvm_oct_poll_queue, &priv->tx_clean_work, HZ); + queue_delayed_work(cvm_oct_poll_queue, &priv->port_periodic_work, HZ); } /** @@ -662,6 +665,9 @@ static int __init cvm_oct_init_module(void) */ cvmx_fau_atomic_write32(FAU_NUM_PACKET_BUFFERS_TO_FREE, 0); + /* Initialize the FAU used for counting tx SKBs that need to be freed */ + cvmx_fau_atomic_write32(FAU_TOTAL_TX_TO_CLEAN, 0); + if ((pow_send_group != -1)) { struct net_device *dev; pr_info("\tConfiguring device for POW only access\n"); @@ -670,18 +676,6 @@ static int __init cvm_oct_init_module(void) /* Initialize the device private structure. */ struct octeon_ethernet *priv = netdev_priv(dev); - hrtimer_init(&priv->tx_restart_timer, - CLOCK_MONOTONIC, - HRTIMER_MODE_REL); - priv->tx_restart_timer.function = cvm_oct_restart_tx; - - /* - * Default for 10GE 5000nS enough time to - * transmit about 100 64byte packtes. 1GE - * interfaces will get 50000nS below. - */ - priv->tx_restart_interval = ktime_set(0, 5000); - dev->netdev_ops = &cvm_oct_pow_netdev_ops; priv->imode = CVMX_HELPER_INTERFACE_MODE_DISABLED; priv->port = CVMX_PIP_NUM_INPUT_PORTS; @@ -725,9 +719,8 @@ static int __init cvm_oct_init_module(void) /* Initialize the device private structure. */ priv = netdev_priv(dev); - INIT_DELAYED_WORK(&priv->tx_clean_work, - cvm_oct_tx_clean_worker); - + INIT_DELAYED_WORK(&priv->port_periodic_work, + cvm_oct_periodic_worker); priv->imode = imode; priv->port = port; priv->queue = cvmx_pko_get_base_queue(priv->port); @@ -763,7 +756,6 @@ static int __init cvm_oct_init_module(void) case CVMX_HELPER_INTERFACE_MODE_SGMII: dev->netdev_ops = &cvm_oct_sgmii_netdev_ops; - priv->tx_restart_interval = ktime_set(0, 50000); strcpy(dev->name, "eth%d"); break; @@ -775,7 +767,6 @@ static int __init cvm_oct_init_module(void) case CVMX_HELPER_INTERFACE_MODE_RGMII: case CVMX_HELPER_INTERFACE_MODE_GMII: dev->netdev_ops = &cvm_oct_rgmii_netdev_ops; - priv->tx_restart_interval = ktime_set(0, 50000); strcpy(dev->name, "eth%d"); break; } @@ -793,13 +784,19 @@ static int __init cvm_oct_init_module(void) cvmx_pko_get_num_queues(priv->port) * sizeof(uint32_t); queue_delayed_work(cvm_oct_poll_queue, - &priv->tx_clean_work, HZ); + &priv->port_periodic_work, HZ); } } } + cvm_oct_tx_initialize(); cvm_oct_rx_initialize(); + /* + * 150 uS: about 10 1500-byte packtes at 1GE. + */ + cvm_oct_tx_poll_interval = 150 * (octeon_get_clock_rate() / 1000000); + queue_delayed_work(cvm_oct_poll_queue, &cvm_oct_rx_refill_work, HZ); return 0; @@ -826,6 +823,8 @@ static void __exit cvm_oct_cleanup_module(void) cancel_delayed_work_sync(&cvm_oct_rx_refill_work); cvm_oct_rx_shutdown(); + cvm_oct_tx_shutdown(); + cvmx_pko_disable(); /* Free the ethernet devices */ @@ -833,9 +832,9 @@ static void __exit cvm_oct_cleanup_module(void) if (cvm_oct_device[port]) { struct net_device *dev = cvm_oct_device[port]; struct octeon_ethernet *priv = netdev_priv(dev); - cancel_delayed_work_sync(&priv->tx_clean_work); + cancel_delayed_work_sync(&priv->port_periodic_work); - cvm_oct_tx_shutdown(dev); + cvm_oct_tx_shutdown_dev(dev); unregister_netdev(dev); kfree(dev); cvm_oct_device[port] = NULL; diff --git a/drivers/staging/octeon/octeon-ethernet.h b/drivers/staging/octeon/octeon-ethernet.h index 8d09210..db2a3cc 100644 --- a/drivers/staging/octeon/octeon-ethernet.h +++ b/drivers/staging/octeon/octeon-ethernet.h @@ -4,7 +4,7 @@ * Contact: support@caviumnetworks.com * This file is part of the OCTEON SDK * - * Copyright (c) 2003-2007 Cavium Networks + * Copyright (c) 2003-2010 Cavium Networks * * This file is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License, Version 2, as @@ -31,8 +31,6 @@ #ifndef OCTEON_ETHERNET_H #define OCTEON_ETHERNET_H -#include - /** * This is the definition of the Ethernet driver's private * driver state stored in netdev_priv(dev). @@ -59,9 +57,7 @@ struct octeon_ethernet { uint64_t link_info; /* Called periodically to check link status */ void (*poll) (struct net_device *dev); - struct hrtimer tx_restart_timer; - ktime_t tx_restart_interval; - struct delayed_work tx_clean_work; + struct delayed_work port_periodic_work; struct work_struct port_work; /* may be unused. */ }; @@ -101,6 +97,7 @@ extern char pow_send_list[]; extern struct net_device *cvm_oct_device[]; extern struct workqueue_struct *cvm_oct_poll_queue; extern atomic_t cvm_oct_poll_queue_stopping; +extern u64 cvm_oct_tx_poll_interval; extern int max_rx_cpus; extern int rx_napi_weight; -- 1.6.6 From ralf@linux-mips.org Tue Feb 16 15:03:33 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 16 Feb 2010 15:03:36 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:34271 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491819Ab0BPODd (ORCPT ); Tue, 16 Feb 2010 15:03:33 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id o1GE3O9P004009; Tue, 16 Feb 2010 15:03:26 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id o1GE3KBA004002; Tue, 16 Feb 2010 15:03:21 +0100 Date: Tue, 16 Feb 2010 15:03:18 +0100 From: Ralf Baechle To: David Daney Cc: linux-mips@linux-mips.org Subject: Re: [PATCH] MIPS: Fix RIXI patch for au1000 processors. Message-ID: <20100216140318.GA31590@linux-mips.org> References: <1266258801-17841-1-git-send-email-ddaney@caviumnetworks.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1266258801-17841-1-git-send-email-ddaney@caviumnetworks.com> User-Agent: Mutt/1.5.20 (2009-08-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25934 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Mon, Feb 15, 2010 at 10:33:21AM -0800, David Daney wrote: > Several macros need to be defined even though they are only used in > dead code paths. Thanks, folded into the existing patch. Ralf From David.Daney@caviumnetworks.com Wed Feb 17 00:26:55 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 17 Feb 2010 00:27:00 +0100 (CET) Received: from mail3.caviumnetworks.com ([12.108.191.235]:4762 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491789Ab0BPX0y (ORCPT ); Wed, 17 Feb 2010 00:26:54 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Tue, 16 Feb 2010 15:27:00 -0800 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Tue, 16 Feb 2010 15:26:45 -0800 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Tue, 16 Feb 2010 15:26:45 -0800 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.3/8.14.2) with ESMTP id o1GNQeop020374; Tue, 16 Feb 2010 15:26:41 -0800 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.3/8.14.3/Submit) id o1GNQbdF020317; Tue, 16 Feb 2010 15:26:37 -0800 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: David Daney Subject: [PATCH] MIPS: crazy spinlock speed test. Date: Tue, 16 Feb 2010 15:26:35 -0800 Message-Id: <1266362795-20199-1-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.6.6 X-OriginalArrivalTime: 16 Feb 2010 23:26:45.0566 (UTC) FILETIME=[8111C5E0:01CAAF5F] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25935 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips This is just a test program for raw_spinlocks. The main reason I wrote it is to validate my spinlock changes that I sent in a previous patch. To use it enable CONFIG_DEBUG_FS and CONFIG_SPINLOCK_TEST then at run time do: # mount -t debugfs none /sys/kernel/debug/ # cat /sys/kernel/debug/mips/spin_single # cat /sys/kernel/debug/mips/spin_multi On my 600MHz octeon cn5860 (16 CPUs) I get spin_single spin_multi base 106885 247941 spinlock_patch 75194 219465 This shows that for uncontended locks the spinlock patch gives 41% improvement and for contended locks 12% improvement (1/time). Signed-off-by: David Daney --- arch/mips/Kconfig.debug | 7 ++ arch/mips/kernel/Makefile | 1 + arch/mips/kernel/spinlock_test.c | 141 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 149 insertions(+), 0 deletions(-) create mode 100644 arch/mips/kernel/spinlock_test.c diff --git a/arch/mips/Kconfig.debug b/arch/mips/Kconfig.debug index d8c0fd7..8354a18 100644 --- a/arch/mips/Kconfig.debug +++ b/arch/mips/Kconfig.debug @@ -131,4 +131,11 @@ config DEBUG_ZBOOT to reduce the kernel image size and speed up the booting procedure a little. +config SPINLOCK_TEST + bool "Enable spinlock timing tests in debugfs" + depends on DEBUG_FS + default n + help + Add several files to the debugfs to test spinlock speed. + endmenu diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile index 642ae95..aac78e3 100644 --- a/arch/mips/kernel/Makefile +++ b/arch/mips/kernel/Makefile @@ -93,6 +93,7 @@ obj-$(CONFIG_GPIO_TXX9) += gpio_txx9.o obj-$(CONFIG_KEXEC) += machine_kexec.o relocate_kernel.o obj-$(CONFIG_EARLY_PRINTK) += early_printk.o +obj-$(CONFIG_SPINLOCK_TEST) += spinlock_test.o CFLAGS_cpu-bugs64.o = $(shell if $(CC) $(KBUILD_CFLAGS) -Wa,-mdaddi -c -o /dev/null -xc /dev/null >/dev/null 2>&1; then echo "-DHAVE_AS_SET_DADDI"; fi) diff --git a/arch/mips/kernel/spinlock_test.c b/arch/mips/kernel/spinlock_test.c new file mode 100644 index 0000000..da61134 --- /dev/null +++ b/arch/mips/kernel/spinlock_test.c @@ -0,0 +1,141 @@ +#include +#include +#include +#include +#include +#include +#include + + +static int ss_get(void *data, u64 *val) +{ + ktime_t start, finish; + int loops; + int cont; + DEFINE_RAW_SPINLOCK(ss_spin); + + loops = 1000000; + cont = 1; + + start = ktime_get(); + + while (cont) { + raw_spin_lock(&ss_spin); + loops--; + if (loops == 0) + cont = 0; + raw_spin_unlock(&ss_spin); + } + + finish = ktime_get(); + + *val = ktime_us_delta(finish, start); + + return 0; +} + +DEFINE_SIMPLE_ATTRIBUTE(fops_ss, ss_get, NULL, "%llu\n"); + + + +struct spin_multi_state { + raw_spinlock_t lock; + atomic_t start_wait; + atomic_t enter_wait; + atomic_t exit_wait; + int loops; +}; + +struct spin_multi_per_thread { + struct spin_multi_state *state; + ktime_t start; +}; + +static int multi_other(void *data) +{ + int loops; + int cont; + struct spin_multi_per_thread *pt = data; + struct spin_multi_state *s = pt->state; + + loops = s->loops; + cont = 1; + + atomic_dec(&s->enter_wait); + + while (atomic_read(&s->enter_wait)) + ; /* spin */ + + pt->start = ktime_get(); + + atomic_dec(&s->start_wait); + + while (atomic_read(&s->start_wait)) + ; /* spin */ + + while (cont) { + raw_spin_lock(&s->lock); + loops--; + if (loops == 0) + cont = 0; + raw_spin_unlock(&s->lock); + } + + atomic_dec(&s->exit_wait); + while (atomic_read(&s->exit_wait)) + ; /* spin */ + return 0; +} + +static int multi_get(void *data, u64 *val) +{ + ktime_t finish; + struct spin_multi_state ms; + struct spin_multi_per_thread t1, t2; + + ms.lock = __RAW_SPIN_LOCK_UNLOCKED("multi_get"); + ms.loops = 1000000; + + atomic_set(&ms.start_wait, 2); + atomic_set(&ms.enter_wait, 2); + atomic_set(&ms.exit_wait, 2); + t1.state = &ms; + t2.state = &ms; + + kthread_run(multi_other, &t2, "multi_get"); + + multi_other(&t1); + + finish = ktime_get(); + + *val = ktime_us_delta(finish, t1.start); + + return 0; +} + +DEFINE_SIMPLE_ATTRIBUTE(fops_multi, multi_get, NULL, "%llu\n"); + + +extern struct dentry *mips_debugfs_dir; +static int __init spinlock_test(void) +{ + struct dentry *d; + + if (!mips_debugfs_dir) + return -ENODEV; + + d = debugfs_create_file("spin_single", S_IRUGO, + mips_debugfs_dir, NULL, + &fops_ss); + if (!d) + return -ENOMEM; + + d = debugfs_create_file("spin_multi", S_IRUGO, + mips_debugfs_dir, NULL, + &fops_multi); + if (!d) + return -ENOMEM; + + return 0; +} +device_initcall(spinlock_test); -- 1.6.6 From David.Daney@caviumnetworks.com Wed Feb 17 02:24:47 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 17 Feb 2010 02:24:54 +0100 (CET) Received: from mail3.caviumnetworks.com ([12.108.191.235]:6638 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491851Ab0BQBYr (ORCPT ); Wed, 17 Feb 2010 02:24:47 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Tue, 16 Feb 2010 17:24:26 -0800 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Tue, 16 Feb 2010 17:24:16 -0800 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Tue, 16 Feb 2010 17:24:16 -0800 Message-ID: <4B7B4540.1010700@caviumnetworks.com> Date: Tue, 16 Feb 2010 17:24:16 -0800 From: David Daney User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.7) Gecko/20100120 Fedora/3.0.1-1.fc12 Thunderbird/3.0.1 MIME-Version: 1.0 To: Ralf Baechle , linux-mips , Netdev , Greg Kroah-Hartman Subject: [PATCH 0/2] Staging: Clean up octeon Ethernet some. Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 17 Feb 2010 01:24:16.0486 (UTC) FILETIME=[EBBEC860:01CAAF6F] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25936 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips These two patches clean up some comments and get rid of the code that creates a non-standard file in /proc As with the previous octeon_ethernet patches, these can probably go via Ralf's linux-mips.org tree. I will reply with the two patches. David Daney (2): Staging: Octeon: Reformat a bunch of comments. Staging: Octeon: Remove /proc/octeon_ethernet_stats drivers/staging/octeon/Makefile | 1 - drivers/staging/octeon/ethernet-mdio.c | 6 +- drivers/staging/octeon/ethernet-mem.c | 16 ++-- drivers/staging/octeon/ethernet-proc.c | 144 ------------------------------ drivers/staging/octeon/ethernet-proc.h | 29 ------ drivers/staging/octeon/ethernet-rx.c | 17 ++-- drivers/staging/octeon/ethernet-tx.c | 14 ++-- drivers/staging/octeon/ethernet-util.h | 13 +-- drivers/staging/octeon/ethernet.c | 46 +++------- drivers/staging/octeon/octeon-ethernet.h | 7 -- 10 files changed, 44 insertions(+), 249 deletions(-) delete mode 100644 drivers/staging/octeon/ethernet-proc.c delete mode 100644 drivers/staging/octeon/ethernet-proc.h From David.Daney@caviumnetworks.com Wed Feb 17 02:25:54 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 17 Feb 2010 02:25:59 +0100 (CET) Received: from mail3.caviumnetworks.com ([12.108.191.235]:6671 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491851Ab0BQBZx (ORCPT ); Wed, 17 Feb 2010 02:25:53 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Tue, 16 Feb 2010 17:25:54 -0800 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Tue, 16 Feb 2010 17:25:44 -0800 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Tue, 16 Feb 2010 17:25:44 -0800 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.3/8.14.2) with ESMTP id o1H1PgXB001324; Tue, 16 Feb 2010 17:25:42 -0800 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.3/8.14.3/Submit) id o1H1PgAr001323; Tue, 16 Feb 2010 17:25:42 -0800 From: David Daney To: ralf@linux-mips.org, linux-mips@linux-mips.org, netdev@vger.kernel.org, gregkh@suse.de Cc: David Daney Subject: [PATCH 2/2] Staging: Octeon: Remove /proc/octeon_ethernet_stats Date: Tue, 16 Feb 2010 17:25:33 -0800 Message-Id: <1266369933-1282-2-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.6.6 In-Reply-To: <4B7B4540.1010700@caviumnetworks.com> References: <4B7B4540.1010700@caviumnetworks.com> X-OriginalArrivalTime: 17 Feb 2010 01:25:44.0596 (UTC) FILETIME=[20434D40:01CAAF70] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25937 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips This file shouldn't be in /proc, so we remove it. Signed-off-by: David Daney --- drivers/staging/octeon/Makefile | 1 - drivers/staging/octeon/ethernet-proc.c | 144 -------------------------------- drivers/staging/octeon/ethernet-proc.h | 29 ------- drivers/staging/octeon/ethernet.c | 4 - 4 files changed, 0 insertions(+), 178 deletions(-) delete mode 100644 drivers/staging/octeon/ethernet-proc.c delete mode 100644 drivers/staging/octeon/ethernet-proc.h diff --git a/drivers/staging/octeon/Makefile b/drivers/staging/octeon/Makefile index c0a583c..87447c1 100644 --- a/drivers/staging/octeon/Makefile +++ b/drivers/staging/octeon/Makefile @@ -14,7 +14,6 @@ obj-${CONFIG_OCTEON_ETHERNET} := octeon-ethernet.o octeon-ethernet-objs := ethernet.o octeon-ethernet-objs += ethernet-mdio.o octeon-ethernet-objs += ethernet-mem.o -octeon-ethernet-objs += ethernet-proc.o octeon-ethernet-objs += ethernet-rgmii.o octeon-ethernet-objs += ethernet-rx.o octeon-ethernet-objs += ethernet-sgmii.o diff --git a/drivers/staging/octeon/ethernet-proc.c b/drivers/staging/octeon/ethernet-proc.c deleted file mode 100644 index 16308d4..0000000 --- a/drivers/staging/octeon/ethernet-proc.c +++ /dev/null @@ -1,144 +0,0 @@ -/********************************************************************** - * Author: Cavium Networks - * - * Contact: support@caviumnetworks.com - * This file is part of the OCTEON SDK - * - * Copyright (c) 2003-2007 Cavium Networks - * - * This file is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, Version 2, as - * published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, but - * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or - * NONINFRINGEMENT. See the GNU General Public License for more - * details. - * - * You should have received a copy of the GNU General Public License - * along with this file; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * or visit http://www.gnu.org/licenses/. - * - * This file may also be available under a different license from Cavium. - * Contact Cavium Networks for more information -**********************************************************************/ -#include -#include -#include -#include - -#include - -#include "octeon-ethernet.h" -#include "ethernet-defines.h" - -#include "cvmx-helper.h" -#include "cvmx-pip.h" - -/** - * User is reading /proc/octeon_ethernet_stats - * - * @m: - * @v: - * Returns - */ -static int cvm_oct_stats_show(struct seq_file *m, void *v) -{ - struct octeon_ethernet *priv; - int port; - - for (port = 0; port < TOTAL_NUMBER_OF_PORTS; port++) { - - if (cvm_oct_device[port]) { - priv = netdev_priv(cvm_oct_device[port]); - - seq_printf(m, "\nOcteon Port %d (%s)\n", port, - cvm_oct_device[port]->name); - seq_printf(m, - "rx_packets: %12lu\t" - "tx_packets: %12lu\n", - priv->stats.rx_packets, - priv->stats.tx_packets); - seq_printf(m, - "rx_bytes: %12lu\t" - "tx_bytes: %12lu\n", - priv->stats.rx_bytes, priv->stats.tx_bytes); - seq_printf(m, - "rx_errors: %12lu\t" - "tx_errors: %12lu\n", - priv->stats.rx_errors, - priv->stats.tx_errors); - seq_printf(m, - "rx_dropped: %12lu\t" - "tx_dropped: %12lu\n", - priv->stats.rx_dropped, - priv->stats.tx_dropped); - seq_printf(m, - "rx_length_errors: %12lu\t" - "tx_aborted_errors: %12lu\n", - priv->stats.rx_length_errors, - priv->stats.tx_aborted_errors); - seq_printf(m, - "rx_over_errors: %12lu\t" - "tx_carrier_errors: %12lu\n", - priv->stats.rx_over_errors, - priv->stats.tx_carrier_errors); - seq_printf(m, - "rx_crc_errors: %12lu\t" - "tx_fifo_errors: %12lu\n", - priv->stats.rx_crc_errors, - priv->stats.tx_fifo_errors); - seq_printf(m, - "rx_frame_errors: %12lu\t" - "tx_heartbeat_errors: %12lu\n", - priv->stats.rx_frame_errors, - priv->stats.tx_heartbeat_errors); - seq_printf(m, - "rx_fifo_errors: %12lu\t" - "tx_window_errors: %12lu\n", - priv->stats.rx_fifo_errors, - priv->stats.tx_window_errors); - seq_printf(m, - "rx_missed_errors: %12lu\t" - "multicast: %12lu\n", - priv->stats.rx_missed_errors, - priv->stats.multicast); - } - } - - return 0; -} - -/** - * /proc/octeon_ethernet_stats was openned. Use the single_open iterator - * - * @inode: - * @file: - * Returns - */ -static int cvm_oct_stats_open(struct inode *inode, struct file *file) -{ - return single_open(file, cvm_oct_stats_show, NULL); -} - -static const struct file_operations cvm_oct_stats_operations = { - .open = cvm_oct_stats_open, - .read = seq_read, - .llseek = seq_lseek, - .release = single_release, -}; - -void cvm_oct_proc_initialize(void) -{ - struct proc_dir_entry *entry = - create_proc_entry("octeon_ethernet_stats", 0, NULL); - if (entry) - entry->proc_fops = &cvm_oct_stats_operations; -} - -void cvm_oct_proc_shutdown(void) -{ - remove_proc_entry("octeon_ethernet_stats", NULL); -} diff --git a/drivers/staging/octeon/ethernet-proc.h b/drivers/staging/octeon/ethernet-proc.h deleted file mode 100644 index 82c7d9f..0000000 --- a/drivers/staging/octeon/ethernet-proc.h +++ /dev/null @@ -1,29 +0,0 @@ -/********************************************************************* - * Author: Cavium Networks - * - * Contact: support@caviumnetworks.com - * This file is part of the OCTEON SDK - * - * Copyright (c) 2003-2007 Cavium Networks - * - * This file is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License, Version 2, as - * published by the Free Software Foundation. - * - * This file is distributed in the hope that it will be useful, but - * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty - * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or - * NONINFRINGEMENT. See the GNU General Public License for more - * details. - * - * You should have received a copy of the GNU General Public License - * along with this file; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - * or visit http://www.gnu.org/licenses/. - * - * This file may also be available under a different license from Cavium. - * Contact Cavium Networks for more information -*********************************************************************/ - -void cvm_oct_proc_initialize(void); -void cvm_oct_proc_shutdown(void); diff --git a/drivers/staging/octeon/ethernet.c b/drivers/staging/octeon/ethernet.c index 45cb4c7..02b6367 100644 --- a/drivers/staging/octeon/ethernet.c +++ b/drivers/staging/octeon/ethernet.c @@ -42,8 +42,6 @@ #include "ethernet-tx.h" #include "ethernet-mdio.h" #include "ethernet-util.h" -#include "ethernet-proc.h" - #include "cvmx-pip.h" #include "cvmx-pko.h" @@ -621,7 +619,6 @@ static int __init cvm_oct_init_module(void) return -ENOMEM; } - cvm_oct_proc_initialize(); cvm_oct_configure_common_hw(); cvmx_helper_initialize_packet_io_global(); @@ -828,7 +825,6 @@ static void __exit cvm_oct_cleanup_module(void) destroy_workqueue(cvm_oct_poll_queue); cvmx_pko_shutdown(); - cvm_oct_proc_shutdown(); cvmx_ipd_free_ptr(); -- 1.6.6 From David.Daney@caviumnetworks.com Wed Feb 17 02:26:27 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 17 Feb 2010 02:26:34 +0100 (CET) Received: from mail3.caviumnetworks.com ([12.108.191.235]:6667 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492373Ab0BQB0C (ORCPT ); Wed, 17 Feb 2010 02:26:02 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Tue, 16 Feb 2010 17:25:54 -0800 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Tue, 16 Feb 2010 17:25:44 -0800 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Tue, 16 Feb 2010 17:25:44 -0800 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.3/8.14.2) with ESMTP id o1H1PgUL001320; Tue, 16 Feb 2010 17:25:42 -0800 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.3/8.14.3/Submit) id o1H1PdKG001319; Tue, 16 Feb 2010 17:25:39 -0800 From: David Daney To: ralf@linux-mips.org, linux-mips@linux-mips.org, netdev@vger.kernel.org, gregkh@suse.de Cc: David Daney Subject: [PATCH 1/2] Staging: Octeon: Reformat a bunch of comments. Date: Tue, 16 Feb 2010 17:25:32 -0800 Message-Id: <1266369933-1282-1-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.6.6 In-Reply-To: <4B7B4540.1010700@caviumnetworks.com> References: <4B7B4540.1010700@caviumnetworks.com> X-OriginalArrivalTime: 17 Feb 2010 01:25:44.0596 (UTC) FILETIME=[20434D40:01CAAF70] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25938 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Many of the comments didn't follow kerneldoc guidlines. Signed-off-by: David Daney --- drivers/staging/octeon/ethernet-mdio.c | 6 ++-- drivers/staging/octeon/ethernet-mem.c | 16 +++++----- drivers/staging/octeon/ethernet-rx.c | 17 ++++++----- drivers/staging/octeon/ethernet-tx.c | 14 +++++----- drivers/staging/octeon/ethernet-util.h | 13 +++------ drivers/staging/octeon/ethernet.c | 42 +++++++++-------------------- drivers/staging/octeon/octeon-ethernet.h | 7 ----- 7 files changed, 44 insertions(+), 71 deletions(-) diff --git a/drivers/staging/octeon/ethernet-mdio.c b/drivers/staging/octeon/ethernet-mdio.c index 05a5cc0..7e0be8d 100644 --- a/drivers/staging/octeon/ethernet-mdio.c +++ b/drivers/staging/octeon/ethernet-mdio.c @@ -96,11 +96,11 @@ const struct ethtool_ops cvm_oct_ethtool_ops = { }; /** - * IOCTL support for PHY control - * + * cvm_oct_ioctl - IOCTL support for PHY control * @dev: Device to change * @rq: the request * @cmd: the command + * * Returns Zero on success */ int cvm_oct_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) @@ -153,7 +153,7 @@ static void cvm_oct_adjust_link(struct net_device *dev) /** - * Setup the PHY + * cvm_oct_phy_setup_device - setup the PHY * * @dev: Device to setup * diff --git a/drivers/staging/octeon/ethernet-mem.c b/drivers/staging/octeon/ethernet-mem.c index 53ed2f7..00cc91d 100644 --- a/drivers/staging/octeon/ethernet-mem.c +++ b/drivers/staging/octeon/ethernet-mem.c @@ -34,11 +34,12 @@ #include "cvmx-fpa.h" /** - * Fill the supplied hardware pool with skbuffs - * + * cvm_oct_fill_hw_skbuff - fill the supplied hardware pool with skbuffs * @pool: Pool to allocate an skbuff for * @size: Size of the buffer needed for the pool * @elements: Number of buffers to allocate + * + * Returns the actual number of buffers allocated. */ static int cvm_oct_fill_hw_skbuff(int pool, int size, int elements) { @@ -62,8 +63,7 @@ static int cvm_oct_fill_hw_skbuff(int pool, int size, int elements) } /** - * Free the supplied hardware pool of skbuffs - * + * cvm_oct_free_hw_skbuff- free hardware pool skbuffs * @pool: Pool to allocate an skbuff for * @size: Size of the buffer needed for the pool * @elements: Number of buffers to allocate @@ -91,11 +91,12 @@ static void cvm_oct_free_hw_skbuff(int pool, int size, int elements) } /** - * This function fills a hardware pool with memory. - * + * cvm_oct_fill_hw_memory - fill a hardware pool with memory. * @pool: Pool to populate * @size: Size of each buffer in the pool * @elements: Number of buffers to allocate + * + * Returns the actual number of buffers allocated. */ static int cvm_oct_fill_hw_memory(int pool, int size, int elements) { @@ -129,8 +130,7 @@ static int cvm_oct_fill_hw_memory(int pool, int size, int elements) } /** - * Free memory previously allocated with cvm_oct_fill_hw_memory - * + * cvm_oct_free_hw_memory - Free memory allocated by cvm_oct_fill_hw_memory * @pool: FPA pool to free * @size: Size of each buffer in the pool * @elements: Number of buffers that should be in the pool diff --git a/drivers/staging/octeon/ethernet-rx.c b/drivers/staging/octeon/ethernet-rx.c index b2e6ab6..cb38f9e 100644 --- a/drivers/staging/octeon/ethernet-rx.c +++ b/drivers/staging/octeon/ethernet-rx.c @@ -124,8 +124,9 @@ static void cvm_oct_no_more_work(void) } /** - * Interrupt handler. The interrupt occurs whenever the POW - * has packets in our group. + * cvm_oct_do_interrupt - interrupt handler. + * + * The interrupt occurs whenever the POW has packets in our group. * */ static irqreturn_t cvm_oct_do_interrupt(int cpl, void *dev_id) @@ -138,10 +139,9 @@ static irqreturn_t cvm_oct_do_interrupt(int cpl, void *dev_id) } /** - * This is called on receive errors, and determines if the packet - * can be dropped early-on in cvm_oct_tasklet_rx(). - * + * cvm_oct_check_rcv_error - process receive errors * @work: Work queue entry pointing to the packet. + * * Returns Non-zero if the packet can be dropped, zero otherwise. */ static inline int cvm_oct_check_rcv_error(cvmx_wqe_t *work) @@ -224,10 +224,11 @@ static inline int cvm_oct_check_rcv_error(cvmx_wqe_t *work) } /** - * The NAPI poll function. - * + * cvm_oct_napi_poll - the NAPI poll function. * @napi: The NAPI instance, or null if called from cvm_oct_poll_controller * @budget: Maximum number of packets to receive. + * + * Returns the number of packets processed. */ static int cvm_oct_napi_poll(struct napi_struct *napi, int budget) { @@ -484,7 +485,7 @@ static int cvm_oct_napi_poll(struct napi_struct *napi, int budget) #ifdef CONFIG_NET_POLL_CONTROLLER /** - * This is called when the kernel needs to manually poll the + * cvm_oct_poll_controller - poll for receive packets * device. * * @dev: Device to poll. Unused diff --git a/drivers/staging/octeon/ethernet-tx.c b/drivers/staging/octeon/ethernet-tx.c index 5175247..afc2b73 100644 --- a/drivers/staging/octeon/ethernet-tx.c +++ b/drivers/staging/octeon/ethernet-tx.c @@ -137,11 +137,11 @@ void cvm_oct_free_tx_skbs(struct net_device *dev) } /** - * Packet transmit - * + * cvm_oct_xmit - transmit a packet * @skb: Packet to send * @dev: Device info structure - * Returns Always returns zero + * + * Returns Always returns NETDEV_TX_OK */ int cvm_oct_xmit(struct sk_buff *skb, struct net_device *dev) { @@ -510,10 +510,10 @@ skip_xmit: } /** - * Packet transmit to the POW - * + * cvm_oct_xmit_pow - transmit a packet to the POW * @skb: Packet to send * @dev: Device info structure + * Returns Always returns zero */ int cvm_oct_xmit_pow(struct sk_buff *skb, struct net_device *dev) @@ -661,9 +661,9 @@ int cvm_oct_xmit_pow(struct sk_buff *skb, struct net_device *dev) } /** - * This function frees all skb that are currently queued for TX. - * + * cvm_oct_tx_shutdown_dev - free all skb that are currently queued for TX. * @dev: Device being shutdown + * */ void cvm_oct_tx_shutdown_dev(struct net_device *dev) { diff --git a/drivers/staging/octeon/ethernet-util.h b/drivers/staging/octeon/ethernet-util.h index 37b6659..2346756 100644 --- a/drivers/staging/octeon/ethernet-util.h +++ b/drivers/staging/octeon/ethernet-util.h @@ -30,10 +30,9 @@ } while (0) /** - * Given a packet data address, return a pointer to the - * beginning of the packet buffer. - * + * cvm_oct_get_buffer_ptr - convert packet data address to pointer * @packet_ptr: Packet data hardware address + * * Returns Packet buffer pointer */ static inline void *cvm_oct_get_buffer_ptr(union cvmx_buf_ptr packet_ptr) @@ -43,9 +42,7 @@ static inline void *cvm_oct_get_buffer_ptr(union cvmx_buf_ptr packet_ptr) } /** - * Given an IPD/PKO port number, return the logical interface it is - * on. - * + * INTERFACE - convert IPD port to locgical interface * @ipd_port: Port to check * * Returns Logical interface @@ -65,9 +62,7 @@ static inline int INTERFACE(int ipd_port) } /** - * Given an IPD/PKO port number, return the port's index on a - * logical interface. - * + * INDEX - convert IPD/PKO port number to the port's interface index * @ipd_port: Port to check * * Returns Index into interface port list diff --git a/drivers/staging/octeon/ethernet.c b/drivers/staging/octeon/ethernet.c index 5ee60ab..45cb4c7 100644 --- a/drivers/staging/octeon/ethernet.c +++ b/drivers/staging/octeon/ethernet.c @@ -176,9 +176,6 @@ static void cvm_oct_periodic_worker(struct work_struct *work) queue_delayed_work(cvm_oct_poll_queue, &priv->port_periodic_work, HZ); } -/** - * Configure common hardware for all interfaces - */ static __init void cvm_oct_configure_common_hw(void) { /* Setup the FPA */ @@ -198,10 +195,10 @@ static __init void cvm_oct_configure_common_hw(void) } /** - * Free a work queue entry received in a intercept callback. + * cvm_oct_free_work- Free a work queue entry + * + * @work_queue_entry: Work queue entry to free * - * @work_queue_entry: - * Work queue entry to free * Returns Zero on success, Negative on failure. */ int cvm_oct_free_work(void *work_queue_entry) @@ -228,9 +225,9 @@ int cvm_oct_free_work(void *work_queue_entry) EXPORT_SYMBOL(cvm_oct_free_work); /** - * Get the low level ethernet statistics - * + * cvm_oct_common_get_stats - get the low level ethernet statistics * @dev: Device to get the statistics from + * * Returns Pointer to the statistics */ static struct net_device_stats *cvm_oct_common_get_stats(struct net_device *dev) @@ -274,8 +271,7 @@ static struct net_device_stats *cvm_oct_common_get_stats(struct net_device *dev) } /** - * Change the link MTU. Unimplemented - * + * cvm_oct_common_change_mtu - change the link MTU * @dev: Device to change * @new_mtu: The new MTU * @@ -339,8 +335,7 @@ static int cvm_oct_common_change_mtu(struct net_device *dev, int new_mtu) } /** - * Set the multicast list. Currently unimplemented. - * + * cvm_oct_common_set_multicast_list - set the multicast list * @dev: Device to work on */ static void cvm_oct_common_set_multicast_list(struct net_device *dev) @@ -395,10 +390,10 @@ static void cvm_oct_common_set_multicast_list(struct net_device *dev) } /** - * Set the hardware MAC address for a device - * - * @dev: Device to change the MAC address for - * @addr: Address structure to change it too. MAC address is addr + 2. + * cvm_oct_common_set_mac_address - set the hardware MAC address for a device + * @dev: The device in question. + * @addr: Address structure to change it too. + * Returns Zero on success */ static int cvm_oct_common_set_mac_address(struct net_device *dev, void *addr) @@ -445,9 +440,9 @@ static int cvm_oct_common_set_mac_address(struct net_device *dev, void *addr) } /** - * Per network device initialization - * + * cvm_oct_common_init - per network device initialization * @dev: Device to initialize + * * Returns Zero on success */ int cvm_oct_common_init(struct net_device *dev) @@ -603,12 +598,6 @@ static const struct net_device_ops cvm_oct_pow_netdev_ops = { extern void octeon_mdiobus_force_mod_depencency(void); -/** - * Module/ driver initialization. Creates the linux network - * devices. - * - * Returns Zero on success - */ static int __init cvm_oct_init_module(void) { int num_interfaces; @@ -802,11 +791,6 @@ static int __init cvm_oct_init_module(void) return 0; } -/** - * Module / driver shutdown - * - * Returns Zero on success - */ static void __exit cvm_oct_cleanup_module(void) { int port; diff --git a/drivers/staging/octeon/octeon-ethernet.h b/drivers/staging/octeon/octeon-ethernet.h index db2a3cc..d581925 100644 --- a/drivers/staging/octeon/octeon-ethernet.h +++ b/drivers/staging/octeon/octeon-ethernet.h @@ -61,13 +61,6 @@ struct octeon_ethernet { struct work_struct port_work; /* may be unused. */ }; -/** - * Free a work queue entry received in a intercept callback. - * - * @work_queue_entry: - * Work queue entry to free - * Returns Zero on success, Negative on failure. - */ int cvm_oct_free_work(void *work_queue_entry); extern int cvm_oct_rgmii_init(struct net_device *dev); -- 1.6.6 From gregkh@suse.de Wed Feb 17 05:59:23 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 17 Feb 2010 05:59:27 +0100 (CET) Received: from cantor2.suse.de ([195.135.220.15]:59179 "EHLO mx2.suse.de" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491187Ab0BQE7X (ORCPT ); Wed, 17 Feb 2010 05:59:23 +0100 Received: from relay1.suse.de (charybdis-ext.suse.de [195.135.221.2]) by mx2.suse.de (Postfix) with ESMTP id B8CDA4844E; Wed, 17 Feb 2010 05:59:22 +0100 (CET) Date: Tue, 16 Feb 2010 20:58:44 -0800 From: Greg KH To: David Daney Cc: Ralf Baechle , linux-mips , Netdev Subject: Re: [PATCH 0/2] Staging: Clean up octeon Ethernet some. Message-ID: <20100217045844.GB18306@suse.de> References: <4B7B4540.1010700@caviumnetworks.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <4B7B4540.1010700@caviumnetworks.com> User-Agent: Mutt/1.5.20 (2009-06-14) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25939 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: gregkh@suse.de Precedence: bulk X-list: linux-mips On Tue, Feb 16, 2010 at 05:24:16PM -0800, David Daney wrote: > These two patches clean up some comments and get rid of the code that > creates a non-standard file in /proc > > As with the previous octeon_ethernet patches, these can probably go > via Ralf's linux-mips.org tree. Going through Ralf's tree is fine for me. thanks, greg k-h From ralf@linux-mips.org Wed Feb 17 14:54:22 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 17 Feb 2010 14:54:26 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:58576 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491070Ab0BQNyW (ORCPT ); Wed, 17 Feb 2010 14:54:22 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id o1HDsJ2W002341; Wed, 17 Feb 2010 14:54:19 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id o1HDsITa002339; Wed, 17 Feb 2010 14:54:18 +0100 Date: Wed, 17 Feb 2010 14:54:18 +0100 From: Ralf Baechle To: Yoichi Yuasa Cc: linux-mips Subject: Re: [PATCH -queue 1/4] MIPS: use generic current.h Message-ID: <20100217135418.GA1561@linux-mips.org> References: <20100212212759.76f1b52a.yuasa@linux-mips.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20100212212759.76f1b52a.yuasa@linux-mips.org> User-Agent: Mutt/1.5.20 (2009-08-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25940 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Fri, Feb 12, 2010 at 09:27:59PM +0900, Yoichi Yuasa wrote: Thanks, queued for 2.6.34. Ralf From ralf@linux-mips.org Wed Feb 17 14:54:44 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 17 Feb 2010 14:54:50 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:58584 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1492377Ab0BQNy1 (ORCPT ); Wed, 17 Feb 2010 14:54:27 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id o1HDsQSW002351; Wed, 17 Feb 2010 14:54:26 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id o1HDsQZQ002350; Wed, 17 Feb 2010 14:54:26 +0100 Date: Wed, 17 Feb 2010 14:54:26 +0100 From: Ralf Baechle To: Yoichi Yuasa Cc: linux-mips Subject: Re: [PATCH -queue 2/4] MIPS: use generic parport.h Message-ID: <20100217135426.GB1561@linux-mips.org> References: <20100212212759.76f1b52a.yuasa@linux-mips.org> <20100212212914.f04a046b.yuasa@linux-mips.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20100212212914.f04a046b.yuasa@linux-mips.org> User-Agent: Mutt/1.5.20 (2009-08-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25941 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Thanks, queued for 2.6.34. Ralf From ralf@linux-mips.org Wed Feb 17 14:55:08 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 17 Feb 2010 14:55:14 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:58587 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1492379Ab0BQNyf (ORCPT ); Wed, 17 Feb 2010 14:54:35 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id o1HDsY5E002360; Wed, 17 Feb 2010 14:54:34 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id o1HDsYIP002359; Wed, 17 Feb 2010 14:54:34 +0100 Date: Wed, 17 Feb 2010 14:54:34 +0100 From: Ralf Baechle To: Yoichi Yuasa Cc: linux-mips Subject: Re: [PATCH -queue 3/4] MIPS: use generic serial.h Message-ID: <20100217135434.GC1561@linux-mips.org> References: <20100212212759.76f1b52a.yuasa@linux-mips.org> <20100212212914.f04a046b.yuasa@linux-mips.org> <20100212213356.198e723b.yuasa@linux-mips.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20100212213356.198e723b.yuasa@linux-mips.org> User-Agent: Mutt/1.5.20 (2009-08-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25942 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Thanks, queued for 2.6.34. Ralf From ralf@linux-mips.org Wed Feb 17 14:55:32 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 17 Feb 2010 14:55:37 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:58592 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1492381Ab0BQNyn (ORCPT ); Wed, 17 Feb 2010 14:54:43 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id o1HDsggp002371; Wed, 17 Feb 2010 14:54:42 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id o1HDsg85002370; Wed, 17 Feb 2010 14:54:42 +0100 Date: Wed, 17 Feb 2010 14:54:42 +0100 From: Ralf Baechle To: Yoichi Yuasa Cc: linux-mips Subject: Re: [PATCH -queue 4/4] MIPS: use generic ucontext.h Message-ID: <20100217135442.GD1561@linux-mips.org> References: <20100212212759.76f1b52a.yuasa@linux-mips.org> <20100212212914.f04a046b.yuasa@linux-mips.org> <20100212213356.198e723b.yuasa@linux-mips.org> <20100212213504.366b7029.yuasa@linux-mips.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20100212213504.366b7029.yuasa@linux-mips.org> User-Agent: Mutt/1.5.20 (2009-08-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25943 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Thanks, queued for 2.6.34. Ralf From ralf@linux-mips.org Wed Feb 17 15:17:13 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 17 Feb 2010 15:17:16 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:44587 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1492383Ab0BQORN (ORCPT ); Wed, 17 Feb 2010 15:17:13 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id o1HEHBVv012394; Wed, 17 Feb 2010 15:17:11 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id o1HEH8uS012374; Wed, 17 Feb 2010 15:17:08 +0100 Date: Wed, 17 Feb 2010 15:17:08 +0100 From: Ralf Baechle To: David Daney Cc: linux-mips@linux-mips.org, netdev@vger.kernel.org, gregkh@suse.de Subject: Re: [PATCH 1/4] Staging: octeon: remove unneeded includes Message-ID: <20100217141707.GE1561@linux-mips.org> References: <4B79AAA6.60005@caviumnetworks.com> <1266264799-3510-1-git-send-email-ddaney@caviumnetworks.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1266264799-3510-1-git-send-email-ddaney@caviumnetworks.com> User-Agent: Mutt/1.5.20 (2009-08-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25944 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Thanks, queued for 2.6.34, Ralf From ralf@linux-mips.org Wed Feb 17 15:17:34 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 17 Feb 2010 15:17:40 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:44594 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1492386Ab0BQORU (ORCPT ); Wed, 17 Feb 2010 15:17:20 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id o1HEHIbE012401; Wed, 17 Feb 2010 15:17:18 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id o1HEHIUF012400; Wed, 17 Feb 2010 15:17:18 +0100 Date: Wed, 17 Feb 2010 15:17:18 +0100 From: Ralf Baechle To: David Daney Cc: linux-mips@linux-mips.org, netdev@vger.kernel.org, gregkh@suse.de Subject: Re: [PATCH 2/4] Staging: Octeon: Run phy bus accesses on a workqueue. Message-ID: <20100217141718.GF1561@linux-mips.org> References: <4B79AAA6.60005@caviumnetworks.com> <1266264799-3510-2-git-send-email-ddaney@caviumnetworks.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1266264799-3510-2-git-send-email-ddaney@caviumnetworks.com> User-Agent: Mutt/1.5.20 (2009-08-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25945 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Thanks, queued for 2.6.34, Ralf From ralf@linux-mips.org Wed Feb 17 15:17:58 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 17 Feb 2010 15:18:05 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:44601 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1492384Ab0BQORa (ORCPT ); Wed, 17 Feb 2010 15:17:30 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id o1HEHT7l012407; Wed, 17 Feb 2010 15:17:29 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id o1HEHST7012406; Wed, 17 Feb 2010 15:17:28 +0100 Date: Wed, 17 Feb 2010 15:17:28 +0100 From: Ralf Baechle To: David Daney Cc: linux-mips@linux-mips.org, netdev@vger.kernel.org, gregkh@suse.de Subject: Re: [PATCH 3/4] MIPS: Octeon: Do proper acknowledgment of CIU timer interrupts. Message-ID: <20100217141728.GG1561@linux-mips.org> References: <4B79AAA6.60005@caviumnetworks.com> <1266264799-3510-3-git-send-email-ddaney@caviumnetworks.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1266264799-3510-3-git-send-email-ddaney@caviumnetworks.com> User-Agent: Mutt/1.5.20 (2009-08-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25946 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Thanks, queued for 2.6.34, Ralf From ralf@linux-mips.org Wed Feb 17 15:18:23 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 17 Feb 2010 15:18:27 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:44810 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1492389Ab0BQORz (ORCPT ); Wed, 17 Feb 2010 15:17:55 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id o1HEHrSr012414; Wed, 17 Feb 2010 15:17:53 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id o1HEHqlB012413; Wed, 17 Feb 2010 15:17:52 +0100 Date: Wed, 17 Feb 2010 15:17:52 +0100 From: Ralf Baechle To: David Daney Cc: linux-mips@linux-mips.org, netdev@vger.kernel.org, gregkh@suse.de, Eric Dumazet Subject: Re: [PATCH 4/4] Staging: Octeon: Free transmit SKBs in a timely manner (v2). Message-ID: <20100217141752.GH1561@linux-mips.org> References: <1266264799-3510-4-git-send-email-ddaney@caviumnetworks.com> <1266275207-14143-1-git-send-email-ddaney@caviumnetworks.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1266275207-14143-1-git-send-email-ddaney@caviumnetworks.com> User-Agent: Mutt/1.5.20 (2009-08-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25947 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Thanks, queued for 2.6.34, Ralf From ralf@linux-mips.org Wed Feb 17 15:25:17 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 17 Feb 2010 15:25:21 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:57794 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1492388Ab0BQOZR (ORCPT ); Wed, 17 Feb 2010 15:25:17 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id o1HEP9fX018551; Wed, 17 Feb 2010 15:25:09 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id o1HEP8n9018478; Wed, 17 Feb 2010 15:25:08 +0100 Date: Wed, 17 Feb 2010 15:25:08 +0100 From: Ralf Baechle To: David Daney Cc: linux-mips@linux-mips.org, netdev@vger.kernel.org, gregkh@suse.de Subject: Re: [PATCH 1/2] Staging: Octeon: Reformat a bunch of comments. Message-ID: <20100217142508.GI1561@linux-mips.org> References: <4B7B4540.1010700@caviumnetworks.com> <1266369933-1282-1-git-send-email-ddaney@caviumnetworks.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1266369933-1282-1-git-send-email-ddaney@caviumnetworks.com> User-Agent: Mutt/1.5.20 (2009-08-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25948 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Thanks folks, queued for 2.6.23. Ralf From ralf@linux-mips.org Wed Feb 17 15:25:39 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 17 Feb 2010 15:25:45 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:57804 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1492392Ab0BQOZ0 (ORCPT ); Wed, 17 Feb 2010 15:25:26 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id o1HEPMsM019244; Wed, 17 Feb 2010 15:25:22 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id o1HEPLmd019206; Wed, 17 Feb 2010 15:25:21 +0100 Date: Wed, 17 Feb 2010 15:25:21 +0100 From: Ralf Baechle To: David Daney Cc: linux-mips@linux-mips.org, netdev@vger.kernel.org, gregkh@suse.de Subject: Re: [PATCH 2/2] Staging: Octeon: Remove /proc/octeon_ethernet_stats Message-ID: <20100217142521.GJ1561@linux-mips.org> References: <4B7B4540.1010700@caviumnetworks.com> <1266369933-1282-2-git-send-email-ddaney@caviumnetworks.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1266369933-1282-2-git-send-email-ddaney@caviumnetworks.com> User-Agent: Mutt/1.5.20 (2009-08-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25949 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Thanks folks, queued for 2.6.23. Ralf From ralf@linux-mips.org Wed Feb 17 15:58:34 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 17 Feb 2010 15:58:38 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:49024 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1492387Ab0BQO6e (ORCPT ); Wed, 17 Feb 2010 15:58:34 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id o1HEwSv9031069; Wed, 17 Feb 2010 15:58:28 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id o1HEwA5N031058; Wed, 17 Feb 2010 15:58:10 +0100 Date: Wed, 17 Feb 2010 15:58:09 +0100 From: Ralf Baechle To: Manuel Lauss Cc: Linux-MIPS , Manuel Lauss Subject: Re: [PATCH -queue] MIPS/net: fix au1000_eth.c build and warnings Message-ID: <20100217145809.GK1561@linux-mips.org> References: <1266263017-6874-1-git-send-email-manuel.lauss@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1266263017-6874-1-git-send-email-manuel.lauss@gmail.com> User-Agent: Mutt/1.5.20 (2009-08-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25950 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Mon, Feb 15, 2010 at 08:43:37PM +0100, Manuel Lauss wrote: > - buildfix: DECLARE_MAC_BUF was removed recently. > - remove various warnings spit out during build > > Only compile-tested. > > Signed-off-by: Manuel Lauss > --- > Hi Ralf! Please fold this into the patch titled > "NET: au1000-eth: convert to platform_driver model" > in mips-queue, thank you! Done - but as this is a net patch it should have been cc'ed to netdev / DaveM as well ... Ralf From f.fainelli@gmail.com Wed Feb 17 16:05:01 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 17 Feb 2010 16:05:06 +0100 (CET) Received: from mail-ew0-f223.google.com ([209.85.219.223]:55995 "EHLO mail-ew0-f223.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491122Ab0BQPFA (ORCPT ); Wed, 17 Feb 2010 16:05:00 +0100 Received: by ewy23 with SMTP id 23so1844676ewy.24 for ; Wed, 17 Feb 2010 07:04:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:sender:from:organization:to :subject:date:user-agent:cc:references:in-reply-to:mime-version :content-type:content-transfer-encoding:message-id; bh=+B7kphgBT53J28P6TT/DeH/3Uri5p/w1F50qEYPa45c=; b=vdrAM9n3/6F8GkVAohrQM4JDwCFIW87qBZ3iAkcmKFx8Wq64+g01i8+UIg1AQUF6+4 iw0DD8nEkUF1Zvn6+8+shhz2Ahc4x0iFGK+8A28NJqrgx7ng/EzJId0lxr/ndZnWn0jV joweQNZr9k/Uf5fB59u3V/+zolvfpmZu9mfno= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:from:organization:to:subject:date:user-agent:cc:references :in-reply-to:mime-version:content-type:content-transfer-encoding :message-id; b=r/yyVcBpIAUttz17F0MJUQrT2vuxmwKa6UF4sZ1b87mKKGMGWk3yqnO2EirNZ0nhLK 6/CV3irPuLYZ+N0Ebo/kyxSId/Aqj3e4LGdVeHOShJ5Y0YK3vXpmGKSGwWJW8Z3vq1TP afwNq40N6KqJ9kJ3OYJcLOmx9ao4vnxQvipC8= Received: by 10.213.109.134 with SMTP id j6mr2247956ebp.72.1266419092928; Wed, 17 Feb 2010 07:04:52 -0800 (PST) Received: from flexo.localnet (bobafett.staff.proxad.net [213.228.1.121]) by mx.google.com with ESMTPS id 13sm5937669ewy.5.2010.02.17.07.04.51 (version=SSLv3 cipher=RC4-MD5); Wed, 17 Feb 2010 07:04:51 -0800 (PST) From: Florian Fainelli Organization: OpenWrt To: Manuel Lauss Subject: Re: [PATCH -queue] MIPS/net: fix au1000_eth.c build and warnings Date: Wed, 17 Feb 2010 16:03:44 +0100 User-Agent: KMail/1.12.2 (Linux/2.6.31-17-server; KDE/4.3.2; x86_64; ; ) Cc: "Linux-MIPS" , Ralf =?utf-8?q?B=EF=BF=BDchle?= , Manuel Lauss References: <1266263017-6874-1-git-send-email-manuel.lauss@gmail.com> In-Reply-To: <1266263017-6874-1-git-send-email-manuel.lauss@gmail.com> MIME-Version: 1.0 Content-Type: Text/Plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <201002171603.44952.florian@openwrt.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25951 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips Hi Manuel, On Monday 15 February 2010 20:43:37 Manuel Lauss wrote: > - buildfix: DECLARE_MAC_BUF was removed recently. > - remove various warnings spit out during build > > Only compile-tested. > > Signed-off-by: Manuel Lauss > --- > Hi Ralf! Please fold this into the patch titled > "NET: au1000-eth: convert to platform_driver model" > in mips-queue, thank you! > > drivers/net/au1000_eth.c | 14 +++++++------- > 1 files changed, 7 insertions(+), 7 deletions(-) > > diff --git a/drivers/net/au1000_eth.c b/drivers/net/au1000_eth.c > index 1acf2c1..6e5a68e 100644 > --- a/drivers/net/au1000_eth.c > +++ b/drivers/net/au1000_eth.c > @@ -397,11 +397,12 @@ static int mii_probe (struct net_device *dev) > /* find the first (lowest address) non-attached PHY on > * the MAC0 MII bus */ > for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) { > - if (aup->mac_id == 1) > - break; > struct phy_device *const tmp_phydev = > aup->mii_bus->phy_map[phy_addr]; > > + if (aup->mac_id == 1) > + break; > + > if (!tmp_phydev) > continue; /* no PHY here... */ > > @@ -650,7 +651,6 @@ static int au1000_init(struct net_device *dev) > > static inline void update_rx_stats(struct net_device *dev, u32 status) > { > - struct au1000_private *aup = netdev_priv(dev); > struct net_device_stats *ps = &dev->stats; > > ps->rx_packets++; > @@ -908,7 +908,7 @@ static netdev_tx_t au1000_tx(struct sk_buff *skb, > struct net_device *dev) } > > pDB = aup->tx_db_inuse[aup->tx_head]; > - skb_copy_from_linear_data(skb, pDB->vaddr, skb->len); > + skb_copy_from_linear_data(skb, (void *)pDB->vaddr, skb->len); > if (skb->len < ETH_ZLEN) { > for (i=skb->len; i ((char *)pDB->vaddr)[i] = 0; > @@ -1006,7 +1006,7 @@ static int __devinit au1000_probe(struct > platform_device *pdev) db_dest_t *pDB, *pDBfree; > int irq, i, err = 0; > struct resource *base, *macen; > - DECLARE_MAC_BUF(ethaddr); > + char ethaddr[6]; That hunk is already in net-next-2.6. -- Florian -- Regards, Florian From ralf@linux-mips.org Wed Feb 17 17:35:12 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 17 Feb 2010 17:35:15 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:47988 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1492387Ab0BQQfM (ORCPT ); Wed, 17 Feb 2010 17:35:12 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id o1HGZ7lf005496; Wed, 17 Feb 2010 17:35:07 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id o1HGZ66Q005494; Wed, 17 Feb 2010 17:35:06 +0100 Date: Wed, 17 Feb 2010 17:35:05 +0100 From: Ralf Baechle To: Florian Fainelli Cc: Manuel Lauss , Linux-MIPS , Manuel Lauss Subject: Re: [PATCH -queue] MIPS/net: fix au1000_eth.c build and warnings Message-ID: <20100217163505.GL1561@linux-mips.org> References: <1266263017-6874-1-git-send-email-manuel.lauss@gmail.com> <201002171603.44952.florian@openwrt.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <201002171603.44952.florian@openwrt.org> User-Agent: Mutt/1.5.20 (2009-08-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25952 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Wed, Feb 17, 2010 at 04:03:44PM +0100, Florian Fainelli wrote: > > @@ -1006,7 +1006,7 @@ static int __devinit au1000_probe(struct > > platform_device *pdev) db_dest_t *pDB, *pDBfree; > > int irq, i, err = 0; > > struct resource *base, *macen; > > - DECLARE_MAC_BUF(ethaddr); > > + char ethaddr[6]; > > That hunk is already in net-next-2.6. Fortunately this doesn't cause a merge conflict. Ralf From David.Daney@caviumnetworks.com Thu Feb 18 20:47:51 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 18 Feb 2010 20:47:55 +0100 (CET) Received: from smtp2.caviumnetworks.com ([209.113.159.134]:2685 "EHLO smtp2.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492443Ab0BRTrv (ORCPT ); Thu, 18 Feb 2010 20:47:51 +0100 Received: from maexch1.caveonetworks.com (Not Verified[192.168.14.20]) by smtp2.caviumnetworks.com with MailMarshal (v6,5,4,7535) id ; Thu, 18 Feb 2010 14:41:48 -0500 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by maexch1.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Thu, 18 Feb 2010 14:47:49 -0500 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Thu, 18 Feb 2010 11:47:47 -0800 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.3/8.14.2) with ESMTP id o1IJlgCA000898; Thu, 18 Feb 2010 11:47:42 -0800 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.3/8.14.3/Submit) id o1IJlgKi000897; Thu, 18 Feb 2010 11:47:42 -0800 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: David Daney Subject: [PATCH 1/2] MIPS: Octeon: Replace rwlocks in irq_chip handlers with raw_spinlocks. Date: Thu, 18 Feb 2010 11:47:40 -0800 Message-Id: <1266522460-862-1-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.6.6 X-OriginalArrivalTime: 18 Feb 2010 19:47:47.0173 (UTC) FILETIME=[3ECD9950:01CAB0D3] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25953 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Signed-off-by: David Daney --- arch/mips/cavium-octeon/octeon-irq.c | 42 +++++++++++---------------------- 1 files changed, 14 insertions(+), 28 deletions(-) diff --git a/arch/mips/cavium-octeon/octeon-irq.c b/arch/mips/cavium-octeon/octeon-irq.c index 8f4a664..e0e5a59 100644 --- a/arch/mips/cavium-octeon/octeon-irq.c +++ b/arch/mips/cavium-octeon/octeon-irq.c @@ -13,8 +13,8 @@ #include #include -DEFINE_RWLOCK(octeon_irq_ciu0_rwlock); -DEFINE_RWLOCK(octeon_irq_ciu1_rwlock); +static DEFINE_RAW_SPINLOCK(octeon_irq_ciu0_lock); +static DEFINE_RAW_SPINLOCK(octeon_irq_ciu1_lock); static DEFINE_RAW_SPINLOCK(octeon_irq_msi_lock); static int octeon_coreid_for_cpu(int cpu) @@ -138,19 +138,12 @@ static void octeon_irq_ciu0_enable(unsigned int irq) uint64_t en0; int bit = irq - OCTEON_IRQ_WORKQ0; /* Bit 0-63 of EN0 */ - /* - * A read lock is used here to make sure only one core is ever - * updating the CIU enable bits at a time. During an enable - * the cores don't interfere with each other. During a disable - * the write lock stops any enables that might cause a - * problem. - */ - read_lock_irqsave(&octeon_irq_ciu0_rwlock, flags); + raw_spin_lock_irqsave(&octeon_irq_ciu0_lock, flags); en0 = cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2)); en0 |= 1ull << bit; cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), en0); cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2)); - read_unlock_irqrestore(&octeon_irq_ciu0_rwlock, flags); + raw_spin_unlock_irqrestore(&octeon_irq_ciu0_lock, flags); } static void octeon_irq_ciu0_disable(unsigned int irq) @@ -159,7 +152,7 @@ static void octeon_irq_ciu0_disable(unsigned int irq) unsigned long flags; uint64_t en0; int cpu; - write_lock_irqsave(&octeon_irq_ciu0_rwlock, flags); + raw_spin_lock_irqsave(&octeon_irq_ciu0_lock, flags); for_each_online_cpu(cpu) { int coreid = octeon_coreid_for_cpu(cpu); en0 = cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2)); @@ -171,7 +164,7 @@ static void octeon_irq_ciu0_disable(unsigned int irq) * of them are done. */ cvmx_read_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num() * 2)); - write_unlock_irqrestore(&octeon_irq_ciu0_rwlock, flags); + raw_spin_unlock_irqrestore(&octeon_irq_ciu0_lock, flags); } /* @@ -257,7 +250,7 @@ static int octeon_irq_ciu0_set_affinity(unsigned int irq, const struct cpumask * unsigned long flags; int bit = irq - OCTEON_IRQ_WORKQ0; /* Bit 0-63 of EN0 */ - write_lock_irqsave(&octeon_irq_ciu0_rwlock, flags); + raw_spin_lock_irqsave(&octeon_irq_ciu0_lock, flags); for_each_online_cpu(cpu) { int coreid = octeon_coreid_for_cpu(cpu); uint64_t en0 = @@ -273,7 +266,7 @@ static int octeon_irq_ciu0_set_affinity(unsigned int irq, const struct cpumask * * of them are done. */ cvmx_read_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num() * 2)); - write_unlock_irqrestore(&octeon_irq_ciu0_rwlock, flags); + raw_spin_unlock_irqrestore(&octeon_irq_ciu0_lock, flags); return 0; } @@ -378,19 +371,12 @@ static void octeon_irq_ciu1_enable(unsigned int irq) uint64_t en1; int bit = irq - OCTEON_IRQ_WDOG0; /* Bit 0-63 of EN1 */ - /* - * A read lock is used here to make sure only one core is ever - * updating the CIU enable bits at a time. During an enable - * the cores don't interfere with each other. During a disable - * the write lock stops any enables that might cause a - * problem. - */ - read_lock_irqsave(&octeon_irq_ciu1_rwlock, flags); + raw_spin_lock_irqsave(&octeon_irq_ciu1_lock, flags); en1 = cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1)); en1 |= 1ull << bit; cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), en1); cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1)); - read_unlock_irqrestore(&octeon_irq_ciu1_rwlock, flags); + raw_spin_unlock_irqrestore(&octeon_irq_ciu1_lock, flags); } static void octeon_irq_ciu1_disable(unsigned int irq) @@ -399,7 +385,7 @@ static void octeon_irq_ciu1_disable(unsigned int irq) unsigned long flags; uint64_t en1; int cpu; - write_lock_irqsave(&octeon_irq_ciu1_rwlock, flags); + raw_spin_lock_irqsave(&octeon_irq_ciu1_lock, flags); for_each_online_cpu(cpu) { int coreid = octeon_coreid_for_cpu(cpu); en1 = cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1)); @@ -411,7 +397,7 @@ static void octeon_irq_ciu1_disable(unsigned int irq) * of them are done. */ cvmx_read_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num() * 2 + 1)); - write_unlock_irqrestore(&octeon_irq_ciu1_rwlock, flags); + raw_spin_unlock_irqrestore(&octeon_irq_ciu1_lock, flags); } /* @@ -475,7 +461,7 @@ static int octeon_irq_ciu1_set_affinity(unsigned int irq, unsigned long flags; int bit = irq - OCTEON_IRQ_WDOG0; /* Bit 0-63 of EN1 */ - write_lock_irqsave(&octeon_irq_ciu1_rwlock, flags); + raw_spin_lock_irqsave(&octeon_irq_ciu1_lock, flags); for_each_online_cpu(cpu) { int coreid = octeon_coreid_for_cpu(cpu); uint64_t en1 = @@ -492,7 +478,7 @@ static int octeon_irq_ciu1_set_affinity(unsigned int irq, * of them are done. */ cvmx_read_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num() * 2 + 1)); - write_unlock_irqrestore(&octeon_irq_ciu1_rwlock, flags); + raw_spin_unlock_irqrestore(&octeon_irq_ciu1_lock, flags); return 0; } -- 1.6.6 From David.Daney@caviumnetworks.com Thu Feb 18 20:48:27 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 18 Feb 2010 20:48:31 +0100 (CET) Received: from smtp2.caviumnetworks.com ([209.113.159.134]:2688 "EHLO smtp2.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492443Ab0BRTs1 (ORCPT ); Thu, 18 Feb 2010 20:48:27 +0100 Received: from maexch1.caveonetworks.com (Not Verified[192.168.14.20]) by smtp2.caviumnetworks.com with MailMarshal (v6,5,4,7535) id ; Thu, 18 Feb 2010 14:42:25 -0500 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by maexch1.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Thu, 18 Feb 2010 14:48:26 -0500 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Thu, 18 Feb 2010 11:48:24 -0800 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.3/8.14.2) with ESMTP id o1IJmM3o000990; Thu, 18 Feb 2010 11:48:22 -0800 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.3/8.14.3/Submit) id o1IJmMil000989; Thu, 18 Feb 2010 11:48:22 -0800 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: David Daney Subject: [PATCH 2/2] MIPS: Octeon: Replace spinlock with raw_spinlocks in dma-octeon.c. Date: Thu, 18 Feb 2010 11:48:20 -0800 Message-Id: <1266522500-955-1-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.6.6 X-OriginalArrivalTime: 18 Feb 2010 19:48:24.0376 (UTC) FILETIME=[54FA5380:01CAB0D3] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25954 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Signed-off-by: David Daney --- arch/mips/cavium-octeon/dma-octeon.c | 10 +++++----- 1 files changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/mips/cavium-octeon/dma-octeon.c b/arch/mips/cavium-octeon/dma-octeon.c index 4b92bfc..be531ec 100644 --- a/arch/mips/cavium-octeon/dma-octeon.c +++ b/arch/mips/cavium-octeon/dma-octeon.c @@ -41,7 +41,7 @@ struct bar1_index_state { }; #ifdef CONFIG_PCI -static DEFINE_SPINLOCK(bar1_lock); +static DEFINE_RAW_SPINLOCK(bar1_lock); static struct bar1_index_state bar1_state[32]; #endif @@ -198,7 +198,7 @@ dma_addr_t octeon_map_dma_mem(struct device *dev, void *ptr, size_t size) start_index = 31; /* Only one processor can access the Bar register at once */ - spin_lock_irqsave(&bar1_lock, flags); + raw_spin_lock_irqsave(&bar1_lock, flags); /* Look through Bar1 for existing mapping that will work */ for (index = start_index; index >= 0; index--) { @@ -250,7 +250,7 @@ dma_addr_t octeon_map_dma_mem(struct device *dev, void *ptr, size_t size) (unsigned long long) physical); done_unlock: - spin_unlock_irqrestore(&bar1_lock, flags); + raw_spin_unlock_irqrestore(&bar1_lock, flags); done: pr_debug("dma_map_single 0x%llx->0x%llx\n", physical, result); return result; @@ -324,14 +324,14 @@ void octeon_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr) "Attempt to unmap an invalid address (0x%llx)\n", dma_addr); - spin_lock_irqsave(&bar1_lock, flags); + raw_spin_lock_irqsave(&bar1_lock, flags); bar1_state[index].ref_count--; if (bar1_state[index].ref_count == 0) octeon_npi_write32(CVMX_NPI_PCI_BAR1_INDEXX(index), 0); else if (unlikely(bar1_state[index].ref_count < 0)) panic("dma_unmap_single: Bar1[%u] reference count < 0\n", (int) index); - spin_unlock_irqrestore(&bar1_lock, flags); + raw_spin_unlock_irqrestore(&bar1_lock, flags); done: pr_debug("dma_unmap_single 0x%llx\n", dma_addr); return; -- 1.6.6 From ralf@linux-mips.org Thu Feb 18 21:36:27 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 18 Feb 2010 21:36:31 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:56825 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1492140Ab0BRUg1 (ORCPT ); Thu, 18 Feb 2010 21:36:27 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id o1IKaNMW017672; Thu, 18 Feb 2010 21:36:23 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id o1IKaLjl017670; Thu, 18 Feb 2010 21:36:21 +0100 Date: Thu, 18 Feb 2010 21:36:21 +0100 From: Ralf Baechle To: David Daney Cc: linux-mips@linux-mips.org Subject: Re: [PATCH 1/2] MIPS: Octeon: Replace rwlocks in irq_chip handlers with raw_spinlocks. Message-ID: <20100218203621.GA17411@linux-mips.org> References: <1266522460-862-1-git-send-email-ddaney@caviumnetworks.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1266522460-862-1-git-send-email-ddaney@caviumnetworks.com> User-Agent: Mutt/1.5.20 (2009-08-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25955 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Thu, Feb 18, 2010 at 11:47:40AM -0800, David Daney wrote: Thanks, queued for 2.6.34 as part of the great locking cleanup. Ralf From ralf@linux-mips.org Thu Feb 18 21:36:49 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 18 Feb 2010 21:36:55 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:56835 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1492453Ab0BRUgh (ORCPT ); Thu, 18 Feb 2010 21:36:37 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id o1IKaaj2017681; Thu, 18 Feb 2010 21:36:36 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id o1IKaaCK017680; Thu, 18 Feb 2010 21:36:36 +0100 Date: Thu, 18 Feb 2010 21:36:36 +0100 From: Ralf Baechle To: David Daney Cc: linux-mips@linux-mips.org Subject: Re: [PATCH 2/2] MIPS: Octeon: Replace spinlock with raw_spinlocks in dma-octeon.c. Message-ID: <20100218203636.GB17411@linux-mips.org> References: <1266522500-955-1-git-send-email-ddaney@caviumnetworks.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1266522500-955-1-git-send-email-ddaney@caviumnetworks.com> User-Agent: Mutt/1.5.20 (2009-08-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25956 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Thu, Feb 18, 2010 at 11:48:20AM -0800, David Daney wrote: Thanks, queued for 2.6.34 as part of the great locking cleanup. Ralf From David.Daney@caviumnetworks.com Fri Feb 19 01:13:53 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 19 Feb 2010 01:14:00 +0100 (CET) Received: from mail3.caviumnetworks.com ([12.108.191.235]:9515 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492155Ab0BSANx (ORCPT ); Fri, 19 Feb 2010 01:13:53 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Thu, 18 Feb 2010 16:13:59 -0800 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Thu, 18 Feb 2010 16:13:28 -0800 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Thu, 18 Feb 2010 16:13:28 -0800 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.3/8.14.2) with ESMTP id o1J0DPbJ029135; Thu, 18 Feb 2010 16:13:25 -0800 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.3/8.14.3/Submit) id o1J0DOj0029134; Thu, 18 Feb 2010 16:13:24 -0800 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: David Daney Subject: [PATCH 0/3] MIPS vdso and signal delivery optimization (v2) Date: Thu, 18 Feb 2010 16:13:02 -0800 Message-Id: <1266538385-29088-1-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.6.6 X-OriginalArrivalTime: 19 Feb 2010 00:13:28.0838 (UTC) FILETIME=[5CC6A260:01CAB0F8] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25957 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips This patch set creates a vdso and moves the signal trampolines to it from their previous home on the stack. In the original patch set: http://www.linux-mips.org/cgi-bin/mesg.cgi?a=linux-mips&i=49EE3B0F.3040506%40caviumnetworks.com I stated: Tested with a 64-bit kernel on a Cavium Octeon cn3860 where I have the following results from lmbench2: Before: n64 - Signal handler overhead: 14.517 microseconds n32 - Signal handler overhead: 14.497 microseconds o32 - Signal handler overhead: 16.637 microseconds After: n64 - Signal handler overhead: 7.935 microseconds n32 - Signal handler overhead: 7.334 microseconds o32 - Signal handler overhead: 8.628 microsecond All that is still true. Improvements from the first version: * Compiles and runs in 32-bit kernels (on qemu at least). * Updated for linux-queue based 2.6.33-rc8 David Daney (3): MIPS: Add SYSCALL to uasm. MIPS: Preliminary vdso. MIPS: Move signal trampolines off of the stack. arch/mips/include/asm/abi.h | 6 +- arch/mips/include/asm/elf.h | 4 + arch/mips/include/asm/mmu.h | 5 +- arch/mips/include/asm/mmu_context.h | 2 +- arch/mips/include/asm/processor.h | 11 +++- arch/mips/include/asm/uasm.h | 1 + arch/mips/include/asm/vdso.h | 29 +++++++++ arch/mips/kernel/Makefile | 2 +- arch/mips/kernel/signal-common.h | 5 -- arch/mips/kernel/signal.c | 86 ++++++--------------------- arch/mips/kernel/signal32.c | 55 ++++------------- arch/mips/kernel/signal_n32.c | 26 ++------ arch/mips/kernel/syscall.c | 6 ++- arch/mips/kernel/vdso.c | 112 +++++++++++++++++++++++++++++++++++ arch/mips/mm/uasm.c | 19 +++++- 15 files changed, 226 insertions(+), 143 deletions(-) create mode 100644 arch/mips/include/asm/vdso.h create mode 100644 arch/mips/kernel/vdso.c From David.Daney@caviumnetworks.com Fri Feb 19 01:14:18 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 19 Feb 2010 01:14:31 +0100 (CET) Received: from mail3.caviumnetworks.com ([12.108.191.235]:9510 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492154Ab0BSANx (ORCPT ); Fri, 19 Feb 2010 01:13:53 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Thu, 18 Feb 2010 16:13:59 -0800 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Thu, 18 Feb 2010 16:13:29 -0800 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Thu, 18 Feb 2010 16:13:28 -0800 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.3/8.14.2) with ESMTP id o1J0DQgH029147; Thu, 18 Feb 2010 16:13:26 -0800 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.3/8.14.3/Submit) id o1J0DQpg029146; Thu, 18 Feb 2010 16:13:26 -0800 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: David Daney Subject: [PATCH 3/3] MIPS: Move signal trampolines off of the stack. Date: Thu, 18 Feb 2010 16:13:05 -0800 Message-Id: <1266538385-29088-4-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.6.6 In-Reply-To: <1266538385-29088-1-git-send-email-ddaney@caviumnetworks.com> References: <1266538385-29088-1-git-send-email-ddaney@caviumnetworks.com> X-OriginalArrivalTime: 19 Feb 2010 00:13:28.0838 (UTC) FILETIME=[5CC6A260:01CAB0F8] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25958 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips This is a follow on to the vdso patch. Since all processes now have signal trampolines permanently mapped, we can use those instead of putting the trampoline on the stack and invalidating the corresponding icache across all CPUs. We also get rid of a bunch of ICACHE_REFILLS_WORKAROUND_WAR code. Signed-off-by: David Daney --- arch/mips/include/asm/abi.h | 6 ++- arch/mips/kernel/signal-common.h | 5 -- arch/mips/kernel/signal.c | 86 ++++++++----------------------------- arch/mips/kernel/signal32.c | 55 ++++++------------------ arch/mips/kernel/signal_n32.c | 26 +++--------- 5 files changed, 43 insertions(+), 135 deletions(-) diff --git a/arch/mips/include/asm/abi.h b/arch/mips/include/asm/abi.h index 1dd74fb..9252d9b 100644 --- a/arch/mips/include/asm/abi.h +++ b/arch/mips/include/asm/abi.h @@ -13,12 +13,14 @@ #include struct mips_abi { - int (* const setup_frame)(struct k_sigaction * ka, + int (* const setup_frame)(void *sig_return, struct k_sigaction *ka, struct pt_regs *regs, int signr, sigset_t *set); - int (* const setup_rt_frame)(struct k_sigaction * ka, + const unsigned long signal_return_offset; + int (* const setup_rt_frame)(void *sig_return, struct k_sigaction *ka, struct pt_regs *regs, int signr, sigset_t *set, siginfo_t *info); + const unsigned long rt_signal_return_offset; const unsigned long restart; }; diff --git a/arch/mips/kernel/signal-common.h b/arch/mips/kernel/signal-common.h index 6c8e8c4..10263b4 100644 --- a/arch/mips/kernel/signal-common.h +++ b/arch/mips/kernel/signal-common.h @@ -26,11 +26,6 @@ */ extern void __user *get_sigframe(struct k_sigaction *ka, struct pt_regs *regs, size_t frame_size); -/* - * install trampoline code to get back from the sig handler - */ -extern int install_sigtramp(unsigned int __user *tramp, unsigned int syscall); - /* Check and clear pending FPU exceptions in saved CSR */ extern int fpcsr_pending(unsigned int __user *fpcsr); diff --git a/arch/mips/kernel/signal.c b/arch/mips/kernel/signal.c index d0c68b5..2099d5a 100644 --- a/arch/mips/kernel/signal.c +++ b/arch/mips/kernel/signal.c @@ -32,6 +32,7 @@ #include #include #include +#include #include "signal-common.h" @@ -44,47 +45,20 @@ extern asmlinkage int _restore_fp_context(struct sigcontext __user *sc); extern asmlinkage int fpu_emulator_save_context(struct sigcontext __user *sc); extern asmlinkage int fpu_emulator_restore_context(struct sigcontext __user *sc); -/* - * Horribly complicated - with the bloody RM9000 workarounds enabled - * the signal trampolines is moving to the end of the structure so we can - * increase the alignment without breaking software compatibility. - */ -#if ICACHE_REFILLS_WORKAROUND_WAR == 0 - struct sigframe { u32 sf_ass[4]; /* argument save space for o32 */ - u32 sf_code[2]; /* signal trampoline */ + u32 sf_pad[2]; /* Was: signal trampoline */ struct sigcontext sf_sc; sigset_t sf_mask; }; struct rt_sigframe { u32 rs_ass[4]; /* argument save space for o32 */ - u32 rs_code[2]; /* signal trampoline */ + u32 rs_pad[2]; /* Was: signal trampoline */ struct siginfo rs_info; struct ucontext rs_uc; }; -#else - -struct sigframe { - u32 sf_ass[4]; /* argument save space for o32 */ - u32 sf_pad[2]; - struct sigcontext sf_sc; /* hw context */ - sigset_t sf_mask; - u32 sf_code[8] ____cacheline_aligned; /* signal trampoline */ -}; - -struct rt_sigframe { - u32 rs_ass[4]; /* argument save space for o32 */ - u32 rs_pad[2]; - struct siginfo rs_info; - struct ucontext rs_uc; - u32 rs_code[8] ____cacheline_aligned; /* signal trampoline */ -}; - -#endif - /* * Helper routines */ @@ -266,32 +240,6 @@ void __user *get_sigframe(struct k_sigaction *ka, struct pt_regs *regs, return (void __user *)((sp - frame_size) & (ICACHE_REFILLS_WORKAROUND_WAR ? ~(cpu_icache_line_size()-1) : ALMASK)); } -int install_sigtramp(unsigned int __user *tramp, unsigned int syscall) -{ - int err; - - /* - * Set up the return code ... - * - * li v0, __NR__foo_sigreturn - * syscall - */ - - err = __put_user(0x24020000 + syscall, tramp + 0); - err |= __put_user(0x0000000c , tramp + 1); - if (ICACHE_REFILLS_WORKAROUND_WAR) { - err |= __put_user(0, tramp + 2); - err |= __put_user(0, tramp + 3); - err |= __put_user(0, tramp + 4); - err |= __put_user(0, tramp + 5); - err |= __put_user(0, tramp + 6); - err |= __put_user(0, tramp + 7); - } - flush_cache_sigtramp((unsigned long) tramp); - - return err; -} - /* * Atomically swap in the new signal mask, and wait for a signal. */ @@ -484,8 +432,8 @@ badframe: } #ifdef CONFIG_TRAD_SIGNALS -static int setup_frame(struct k_sigaction * ka, struct pt_regs *regs, - int signr, sigset_t *set) +static int setup_frame(void *sig_return, struct k_sigaction *ka, + struct pt_regs *regs, int signr, sigset_t *set) { struct sigframe __user *frame; int err = 0; @@ -494,8 +442,6 @@ static int setup_frame(struct k_sigaction * ka, struct pt_regs *regs, if (!access_ok(VERIFY_WRITE, frame, sizeof (*frame))) goto give_sigsegv; - err |= install_sigtramp(frame->sf_code, __NR_sigreturn); - err |= setup_sigcontext(regs, &frame->sf_sc); err |= __copy_to_user(&frame->sf_mask, set, sizeof(*set)); if (err) @@ -515,7 +461,7 @@ static int setup_frame(struct k_sigaction * ka, struct pt_regs *regs, regs->regs[ 5] = 0; regs->regs[ 6] = (unsigned long) &frame->sf_sc; regs->regs[29] = (unsigned long) frame; - regs->regs[31] = (unsigned long) frame->sf_code; + regs->regs[31] = (unsigned long) sig_return; regs->cp0_epc = regs->regs[25] = (unsigned long) ka->sa.sa_handler; DEBUGP("SIG deliver (%s:%d): sp=0x%p pc=0x%lx ra=0x%lx\n", @@ -529,8 +475,9 @@ give_sigsegv: } #endif -static int setup_rt_frame(struct k_sigaction * ka, struct pt_regs *regs, - int signr, sigset_t *set, siginfo_t *info) +static int setup_rt_frame(void *sig_return, struct k_sigaction *ka, + struct pt_regs *regs, int signr, sigset_t *set, + siginfo_t *info) { struct rt_sigframe __user *frame; int err = 0; @@ -539,8 +486,6 @@ static int setup_rt_frame(struct k_sigaction * ka, struct pt_regs *regs, if (!access_ok(VERIFY_WRITE, frame, sizeof (*frame))) goto give_sigsegv; - err |= install_sigtramp(frame->rs_code, __NR_rt_sigreturn); - /* Create siginfo. */ err |= copy_siginfo_to_user(&frame->rs_info, info); @@ -573,7 +518,7 @@ static int setup_rt_frame(struct k_sigaction * ka, struct pt_regs *regs, regs->regs[ 5] = (unsigned long) &frame->rs_info; regs->regs[ 6] = (unsigned long) &frame->rs_uc; regs->regs[29] = (unsigned long) frame; - regs->regs[31] = (unsigned long) frame->rs_code; + regs->regs[31] = (unsigned long) sig_return; regs->cp0_epc = regs->regs[25] = (unsigned long) ka->sa.sa_handler; DEBUGP("SIG deliver (%s:%d): sp=0x%p pc=0x%lx ra=0x%lx\n", @@ -590,8 +535,11 @@ give_sigsegv: struct mips_abi mips_abi = { #ifdef CONFIG_TRAD_SIGNALS .setup_frame = setup_frame, + .signal_return_offset = offsetof(struct mips_vdso, signal_trampoline), #endif .setup_rt_frame = setup_rt_frame, + .rt_signal_return_offset = + offsetof(struct mips_vdso, rt_signal_trampoline), .restart = __NR_restart_syscall }; @@ -599,6 +547,8 @@ static int handle_signal(unsigned long sig, siginfo_t *info, struct k_sigaction *ka, sigset_t *oldset, struct pt_regs *regs) { int ret; + struct mips_abi *abi = current->thread.abi; + void *vdso = current->mm->context.vdso; switch(regs->regs[0]) { case ERESTART_RESTARTBLOCK: @@ -619,9 +569,11 @@ static int handle_signal(unsigned long sig, siginfo_t *info, regs->regs[0] = 0; /* Don't deal with this again. */ if (sig_uses_siginfo(ka)) - ret = current->thread.abi->setup_rt_frame(ka, regs, sig, oldset, info); + ret = abi->setup_rt_frame(vdso + abi->rt_signal_return_offset, + ka, regs, sig, oldset, info); else - ret = current->thread.abi->setup_frame(ka, regs, sig, oldset); + ret = abi->setup_frame(vdso + abi->signal_return_offset, + ka, regs, sig, oldset); spin_lock_irq(¤t->sighand->siglock); sigorsets(¤t->blocked, ¤t->blocked, &ka->sa.sa_mask); diff --git a/arch/mips/kernel/signal32.c b/arch/mips/kernel/signal32.c index 03abaf0..a0ed0e0 100644 --- a/arch/mips/kernel/signal32.c +++ b/arch/mips/kernel/signal32.c @@ -32,6 +32,7 @@ #include #include #include +#include #include "signal-common.h" @@ -47,8 +48,6 @@ extern asmlinkage int fpu_emulator_restore_context32(struct sigcontext32 __user /* * Including would give use the 64-bit syscall numbers ... */ -#define __NR_O32_sigreturn 4119 -#define __NR_O32_rt_sigreturn 4193 #define __NR_O32_restart_syscall 4253 /* 32-bit compatibility types */ @@ -77,47 +76,20 @@ struct ucontext32 { compat_sigset_t uc_sigmask; /* mask last for extensibility */ }; -/* - * Horribly complicated - with the bloody RM9000 workarounds enabled - * the signal trampolines is moving to the end of the structure so we can - * increase the alignment without breaking software compatibility. - */ -#if ICACHE_REFILLS_WORKAROUND_WAR == 0 - struct sigframe32 { u32 sf_ass[4]; /* argument save space for o32 */ - u32 sf_code[2]; /* signal trampoline */ + u32 sf_pad[2]; /* Was: signal trampoline */ struct sigcontext32 sf_sc; compat_sigset_t sf_mask; }; struct rt_sigframe32 { u32 rs_ass[4]; /* argument save space for o32 */ - u32 rs_code[2]; /* signal trampoline */ + u32 rs_pad[2]; /* Was: signal trampoline */ compat_siginfo_t rs_info; struct ucontext32 rs_uc; }; -#else /* ICACHE_REFILLS_WORKAROUND_WAR */ - -struct sigframe32 { - u32 sf_ass[4]; /* argument save space for o32 */ - u32 sf_pad[2]; - struct sigcontext32 sf_sc; /* hw context */ - compat_sigset_t sf_mask; - u32 sf_code[8] ____cacheline_aligned; /* signal trampoline */ -}; - -struct rt_sigframe32 { - u32 rs_ass[4]; /* argument save space for o32 */ - u32 rs_pad[2]; - compat_siginfo_t rs_info; - struct ucontext32 rs_uc; - u32 rs_code[8] __attribute__((aligned(32))); /* signal trampoline */ -}; - -#endif /* !ICACHE_REFILLS_WORKAROUND_WAR */ - /* * sigcontext handlers */ @@ -598,8 +570,8 @@ badframe: force_sig(SIGSEGV, current); } -static int setup_frame_32(struct k_sigaction * ka, struct pt_regs *regs, - int signr, sigset_t *set) +static int setup_frame_32(void *sig_return, struct k_sigaction *ka, + struct pt_regs *regs, int signr, sigset_t *set) { struct sigframe32 __user *frame; int err = 0; @@ -608,8 +580,6 @@ static int setup_frame_32(struct k_sigaction * ka, struct pt_regs *regs, if (!access_ok(VERIFY_WRITE, frame, sizeof (*frame))) goto give_sigsegv; - err |= install_sigtramp(frame->sf_code, __NR_O32_sigreturn); - err |= setup_sigcontext32(regs, &frame->sf_sc); err |= __copy_conv_sigset_to_user(&frame->sf_mask, set); @@ -630,7 +600,7 @@ static int setup_frame_32(struct k_sigaction * ka, struct pt_regs *regs, regs->regs[ 5] = 0; regs->regs[ 6] = (unsigned long) &frame->sf_sc; regs->regs[29] = (unsigned long) frame; - regs->regs[31] = (unsigned long) frame->sf_code; + regs->regs[31] = (unsigned long) sig_return; regs->cp0_epc = regs->regs[25] = (unsigned long) ka->sa.sa_handler; DEBUGP("SIG deliver (%s:%d): sp=0x%p pc=0x%lx ra=0x%lx\n", @@ -644,8 +614,9 @@ give_sigsegv: return -EFAULT; } -static int setup_rt_frame_32(struct k_sigaction * ka, struct pt_regs *regs, - int signr, sigset_t *set, siginfo_t *info) +static int setup_rt_frame_32(void *sig_return, struct k_sigaction *ka, + struct pt_regs *regs, int signr, sigset_t *set, + siginfo_t *info) { struct rt_sigframe32 __user *frame; int err = 0; @@ -655,8 +626,6 @@ static int setup_rt_frame_32(struct k_sigaction * ka, struct pt_regs *regs, if (!access_ok(VERIFY_WRITE, frame, sizeof (*frame))) goto give_sigsegv; - err |= install_sigtramp(frame->rs_code, __NR_O32_rt_sigreturn); - /* Convert (siginfo_t -> compat_siginfo_t) and copy to user. */ err |= copy_siginfo_to_user32(&frame->rs_info, info); @@ -690,7 +659,7 @@ static int setup_rt_frame_32(struct k_sigaction * ka, struct pt_regs *regs, regs->regs[ 5] = (unsigned long) &frame->rs_info; regs->regs[ 6] = (unsigned long) &frame->rs_uc; regs->regs[29] = (unsigned long) frame; - regs->regs[31] = (unsigned long) frame->rs_code; + regs->regs[31] = (unsigned long) sig_return; regs->cp0_epc = regs->regs[25] = (unsigned long) ka->sa.sa_handler; DEBUGP("SIG deliver (%s:%d): sp=0x%p pc=0x%lx ra=0x%lx\n", @@ -709,7 +678,11 @@ give_sigsegv: */ struct mips_abi mips_abi_32 = { .setup_frame = setup_frame_32, + .signal_return_offset = + offsetof(struct mips_vdso, o32_signal_trampoline), .setup_rt_frame = setup_rt_frame_32, + .rt_signal_return_offset = + offsetof(struct mips_vdso, o32_rt_signal_trampoline), .restart = __NR_O32_restart_syscall }; diff --git a/arch/mips/kernel/signal_n32.c b/arch/mips/kernel/signal_n32.c index bb277e8..2c5df81 100644 --- a/arch/mips/kernel/signal_n32.c +++ b/arch/mips/kernel/signal_n32.c @@ -39,13 +39,13 @@ #include #include #include +#include #include "signal-common.h" /* * Including would give use the 64-bit syscall numbers ... */ -#define __NR_N32_rt_sigreturn 6211 #define __NR_N32_restart_syscall 6214 extern int setup_sigcontext(struct pt_regs *, struct sigcontext __user *); @@ -67,27 +67,13 @@ struct ucontextn32 { compat_sigset_t uc_sigmask; /* mask last for extensibility */ }; -#if ICACHE_REFILLS_WORKAROUND_WAR == 0 - -struct rt_sigframe_n32 { - u32 rs_ass[4]; /* argument save space for o32 */ - u32 rs_code[2]; /* signal trampoline */ - struct compat_siginfo rs_info; - struct ucontextn32 rs_uc; -}; - -#else /* ICACHE_REFILLS_WORKAROUND_WAR */ - struct rt_sigframe_n32 { u32 rs_ass[4]; /* argument save space for o32 */ - u32 rs_pad[2]; + u32 rs_pad[2]; /* Was: signal trampoline */ struct compat_siginfo rs_info; struct ucontextn32 rs_uc; - u32 rs_code[8] ____cacheline_aligned; /* signal trampoline */ }; -#endif /* !ICACHE_REFILLS_WORKAROUND_WAR */ - extern void sigset_from_compat(sigset_t *set, compat_sigset_t *compat); asmlinkage int sysn32_rt_sigsuspend(nabi_no_regargs struct pt_regs regs) @@ -173,7 +159,7 @@ badframe: force_sig(SIGSEGV, current); } -static int setup_rt_frame_n32(struct k_sigaction * ka, +static int setup_rt_frame_n32(void *sig_return, struct k_sigaction *ka, struct pt_regs *regs, int signr, sigset_t *set, siginfo_t *info) { struct rt_sigframe_n32 __user *frame; @@ -184,8 +170,6 @@ static int setup_rt_frame_n32(struct k_sigaction * ka, if (!access_ok(VERIFY_WRITE, frame, sizeof (*frame))) goto give_sigsegv; - install_sigtramp(frame->rs_code, __NR_N32_rt_sigreturn); - /* Create siginfo. */ err |= copy_siginfo_to_user32(&frame->rs_info, info); @@ -219,7 +203,7 @@ static int setup_rt_frame_n32(struct k_sigaction * ka, regs->regs[ 5] = (unsigned long) &frame->rs_info; regs->regs[ 6] = (unsigned long) &frame->rs_uc; regs->regs[29] = (unsigned long) frame; - regs->regs[31] = (unsigned long) frame->rs_code; + regs->regs[31] = (unsigned long) sig_return; regs->cp0_epc = regs->regs[25] = (unsigned long) ka->sa.sa_handler; DEBUGP("SIG deliver (%s:%d): sp=0x%p pc=0x%lx ra=0x%lx\n", @@ -235,5 +219,7 @@ give_sigsegv: struct mips_abi mips_abi_n32 = { .setup_rt_frame = setup_rt_frame_n32, + .rt_signal_return_offset = + offsetof(struct mips_vdso, n32_rt_signal_trampoline), .restart = __NR_N32_restart_syscall }; -- 1.6.6 From David.Daney@caviumnetworks.com Fri Feb 19 01:14:49 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 19 Feb 2010 01:14:59 +0100 (CET) Received: from mail3.caviumnetworks.com ([12.108.191.235]:9513 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492152Ab0BSANx (ORCPT ); Fri, 19 Feb 2010 01:13:53 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Thu, 18 Feb 2010 16:13:59 -0800 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Thu, 18 Feb 2010 16:13:28 -0800 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Thu, 18 Feb 2010 16:13:28 -0800 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.3/8.14.2) with ESMTP id o1J0DQU9029143; Thu, 18 Feb 2010 16:13:26 -0800 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.3/8.14.3/Submit) id o1J0DQ1c029142; Thu, 18 Feb 2010 16:13:26 -0800 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: David Daney Subject: [PATCH 2/3] MIPS: Preliminary vdso. Date: Thu, 18 Feb 2010 16:13:04 -0800 Message-Id: <1266538385-29088-3-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.6.6 In-Reply-To: <1266538385-29088-1-git-send-email-ddaney@caviumnetworks.com> References: <1266538385-29088-1-git-send-email-ddaney@caviumnetworks.com> X-OriginalArrivalTime: 19 Feb 2010 00:13:28.0838 (UTC) FILETIME=[5CC6A260:01CAB0F8] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25959 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips This is a preliminary patch to add a vdso to all user processes. Still missing are ELF headers and .eh_frame information. But it is enough to allow us to move signal trampolines off of the stack. Note that emulation of branch delay slots in the FPU emulator still requires the stack. We allocate a single page (the vdso) and write all possible signal trampolines into it. The stack is moved down by one page and the vdso is mapped into this space. Signed-off-by: David Daney --- arch/mips/include/asm/elf.h | 4 + arch/mips/include/asm/mmu.h | 5 +- arch/mips/include/asm/mmu_context.h | 2 +- arch/mips/include/asm/processor.h | 11 +++- arch/mips/include/asm/vdso.h | 29 +++++++++ arch/mips/kernel/Makefile | 2 +- arch/mips/kernel/syscall.c | 6 ++- arch/mips/kernel/vdso.c | 112 +++++++++++++++++++++++++++++++++++ 8 files changed, 165 insertions(+), 6 deletions(-) create mode 100644 arch/mips/include/asm/vdso.h create mode 100644 arch/mips/kernel/vdso.c diff --git a/arch/mips/include/asm/elf.h b/arch/mips/include/asm/elf.h index e53d7be..1c3dbf0 100644 --- a/arch/mips/include/asm/elf.h +++ b/arch/mips/include/asm/elf.h @@ -367,4 +367,8 @@ extern const char *__elf_platform; #define ELF_ET_DYN_BASE (TASK_SIZE / 3 * 2) #endif +#define ARCH_HAS_SETUP_ADDITIONAL_PAGES 1 +struct linux_binprm; +extern int arch_setup_additional_pages(struct linux_binprm *bprm, + int uses_interp); #endif /* _ASM_ELF_H */ diff --git a/arch/mips/include/asm/mmu.h b/arch/mips/include/asm/mmu.h index 4063edd..c436138 100644 --- a/arch/mips/include/asm/mmu.h +++ b/arch/mips/include/asm/mmu.h @@ -1,6 +1,9 @@ #ifndef __ASM_MMU_H #define __ASM_MMU_H -typedef unsigned long mm_context_t[NR_CPUS]; +typedef struct { + unsigned long asid[NR_CPUS]; + void *vdso; +} mm_context_t; #endif /* __ASM_MMU_H */ diff --git a/arch/mips/include/asm/mmu_context.h b/arch/mips/include/asm/mmu_context.h index ada4975..73a640b 100644 --- a/arch/mips/include/asm/mmu_context.h +++ b/arch/mips/include/asm/mmu_context.h @@ -109,7 +109,7 @@ extern unsigned long smtc_asid_mask; #endif -#define cpu_context(cpu, mm) ((mm)->context[cpu]) +#define cpu_context(cpu, mm) ((mm)->context.asid[cpu]) #define cpu_asid(cpu, mm) (cpu_context((cpu), (mm)) & ASID_MASK) #define asid_cache(cpu) (cpu_data[cpu].asid_cache) diff --git a/arch/mips/include/asm/processor.h b/arch/mips/include/asm/processor.h index 087a888..ab38791 100644 --- a/arch/mips/include/asm/processor.h +++ b/arch/mips/include/asm/processor.h @@ -33,13 +33,19 @@ extern void (*cpu_wait)(void); extern unsigned int vced_count, vcei_count; +/* + * A special page (the vdso) is mapped into all processes at the very + * top of the virtual memory space. + */ +#define SPECIAL_PAGES_SIZE PAGE_SIZE + #ifdef CONFIG_32BIT /* * User space process size: 2GB. This is hardcoded into a few places, * so don't change it unless you know what you are doing. */ #define TASK_SIZE 0x7fff8000UL -#define STACK_TOP TASK_SIZE +#define STACK_TOP ((TASK_SIZE & PAGE_MASK) - SPECIAL_PAGES_SIZE) /* * This decides where the kernel will search for a free chunk of vm @@ -59,7 +65,8 @@ extern unsigned int vced_count, vcei_count; #define TASK_SIZE32 0x7fff8000UL #define TASK_SIZE 0x10000000000UL #define STACK_TOP \ - (test_thread_flag(TIF_32BIT_ADDR) ? TASK_SIZE32 : TASK_SIZE) + (((test_thread_flag(TIF_32BIT_ADDR) ? \ + TASK_SIZE32 : TASK_SIZE) & PAGE_MASK) - SPECIAL_PAGES_SIZE) /* * This decides where the kernel will search for a free chunk of vm diff --git a/arch/mips/include/asm/vdso.h b/arch/mips/include/asm/vdso.h new file mode 100644 index 0000000..cca56aa --- /dev/null +++ b/arch/mips/include/asm/vdso.h @@ -0,0 +1,29 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2009 Cavium Networks + */ + +#ifndef __ASM_VDSO_H +#define __ASM_VDSO_H + +#include + + +#ifdef CONFIG_32BIT +struct mips_vdso { + u32 signal_trampoline[2]; + u32 rt_signal_trampoline[2]; +}; +#else /* !CONFIG_32BIT */ +struct mips_vdso { + u32 o32_signal_trampoline[2]; + u32 o32_rt_signal_trampoline[2]; + u32 rt_signal_trampoline[2]; + u32 n32_rt_signal_trampoline[2]; +}; +#endif /* CONFIG_32BIT */ + +#endif /* __ASM_VDSO_H */ diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile index 924192b..642ae95 100644 --- a/arch/mips/kernel/Makefile +++ b/arch/mips/kernel/Makefile @@ -6,7 +6,7 @@ extra-y := head.o init_task.o vmlinux.lds obj-y += cpu-probe.o branch.o entry.o genex.o irq.o process.o \ ptrace.o reset.o setup.o signal.o syscall.o \ - time.o topology.o traps.o unaligned.o watch.o + time.o topology.o traps.o unaligned.o watch.o vdso.o ifdef CONFIG_FUNCTION_TRACER CFLAGS_REMOVE_ftrace.o = -pg diff --git a/arch/mips/kernel/syscall.c b/arch/mips/kernel/syscall.c index e6cb831..d15eb20 100644 --- a/arch/mips/kernel/syscall.c +++ b/arch/mips/kernel/syscall.c @@ -79,7 +79,11 @@ unsigned long arch_get_unmapped_area(struct file *filp, unsigned long addr, int do_color_align; unsigned long task_size; - task_size = STACK_TOP; +#ifdef CONFIG_32BIT + task_size = TASK_SIZE; +#else /* Must be CONFIG_64BIT*/ + task_size = test_thread_flag(TIF_32BIT_ADDR) ? TASK_SIZE32 : TASK_SIZE; +#endif if (len > task_size) return -ENOMEM; diff --git a/arch/mips/kernel/vdso.c b/arch/mips/kernel/vdso.c new file mode 100644 index 0000000..b773c11 --- /dev/null +++ b/arch/mips/kernel/vdso.c @@ -0,0 +1,112 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2009, 2010 Cavium Networks, Inc. + */ + + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +/* + * Including would give use the 64-bit syscall numbers ... + */ +#define __NR_O32_sigreturn 4119 +#define __NR_O32_rt_sigreturn 4193 +#define __NR_N32_rt_sigreturn 6211 + +static struct page *vdso_page; + +static void __init install_trampoline(u32 *tramp, unsigned int sigreturn) +{ + uasm_i_addiu(&tramp, 2, 0, sigreturn); /* li v0, sigreturn */ + uasm_i_syscall(&tramp, 0); +} + +static int __init init_vdso(void) +{ + struct mips_vdso *vdso; + + vdso_page = alloc_page(GFP_KERNEL); + if (!vdso_page) + panic("Cannot allocate vdso"); + + vdso = vmap(&vdso_page, 1, 0, PAGE_KERNEL); + if (!vdso) + panic("Cannot map vdso"); + clear_page(vdso); + + install_trampoline(vdso->rt_signal_trampoline, __NR_rt_sigreturn); +#ifdef CONFIG_32BIT + install_trampoline(vdso->signal_trampoline, __NR_sigreturn); +#else + install_trampoline(vdso->n32_rt_signal_trampoline, + __NR_N32_rt_sigreturn); + install_trampoline(vdso->o32_signal_trampoline, __NR_O32_sigreturn); + install_trampoline(vdso->o32_rt_signal_trampoline, + __NR_O32_rt_sigreturn); +#endif + + vunmap(vdso); + + pr_notice("init_vdso successfull\n"); + + return 0; +} +device_initcall(init_vdso); + +static unsigned long vdso_addr(unsigned long start) +{ + return STACK_TOP; +} + +int arch_setup_additional_pages(struct linux_binprm *bprm, int uses_interp) +{ + int ret; + unsigned long addr; + struct mm_struct *mm = current->mm; + + down_write(&mm->mmap_sem); + + addr = vdso_addr(mm->start_stack); + + addr = get_unmapped_area(NULL, addr, PAGE_SIZE, 0, 0); + if (IS_ERR_VALUE(addr)) { + ret = addr; + goto up_fail; + } + + ret = install_special_mapping(mm, addr, PAGE_SIZE, + VM_READ|VM_EXEC| + VM_MAYREAD|VM_MAYWRITE|VM_MAYEXEC| + VM_ALWAYSDUMP, + &vdso_page); + + if (ret) + goto up_fail; + + mm->context.vdso = (void *)addr; + +up_fail: + up_write(&mm->mmap_sem); + return ret; +} + +const char *arch_vma_name(struct vm_area_struct *vma) +{ + if (vma->vm_mm && vma->vm_start == (long)vma->vm_mm->context.vdso) + return "[vdso]"; + return NULL; +} -- 1.6.6 From David.Daney@caviumnetworks.com Fri Feb 19 01:15:17 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 19 Feb 2010 01:15:26 +0100 (CET) Received: from mail3.caviumnetworks.com ([12.108.191.235]:9521 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492157Ab0BSANz (ORCPT ); Fri, 19 Feb 2010 01:13:55 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Thu, 18 Feb 2010 16:13:59 -0800 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Thu, 18 Feb 2010 16:13:29 -0800 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Thu, 18 Feb 2010 16:13:28 -0800 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.3/8.14.2) with ESMTP id o1J0DQaX029139; Thu, 18 Feb 2010 16:13:26 -0800 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.3/8.14.3/Submit) id o1J0DQG5029138; Thu, 18 Feb 2010 16:13:26 -0800 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: David Daney Subject: [PATCH 1/3] MIPS: Add SYSCALL to uasm. Date: Thu, 18 Feb 2010 16:13:03 -0800 Message-Id: <1266538385-29088-2-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.6.6 In-Reply-To: <1266538385-29088-1-git-send-email-ddaney@caviumnetworks.com> References: <1266538385-29088-1-git-send-email-ddaney@caviumnetworks.com> X-OriginalArrivalTime: 19 Feb 2010 00:13:28.0838 (UTC) FILETIME=[5CC6A260:01CAB0F8] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25960 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Signed-off-by: David Daney --- arch/mips/include/asm/uasm.h | 1 + arch/mips/mm/uasm.c | 19 +++++++++++++++++-- 2 files changed, 18 insertions(+), 2 deletions(-) diff --git a/arch/mips/include/asm/uasm.h b/arch/mips/include/asm/uasm.h index b99bd07..32fe2ec 100644 --- a/arch/mips/include/asm/uasm.h +++ b/arch/mips/include/asm/uasm.h @@ -102,6 +102,7 @@ Ip_0(_tlbwr); Ip_u3u1u2(_xor); Ip_u2u1u3(_xori); Ip_u2u1msbu3(_dins); +Ip_u1(_syscall); /* Handle labels. */ struct uasm_label { diff --git a/arch/mips/mm/uasm.c b/arch/mips/mm/uasm.c index 1581e98..d22d7bc 100644 --- a/arch/mips/mm/uasm.c +++ b/arch/mips/mm/uasm.c @@ -31,7 +31,8 @@ enum fields { BIMM = 0x040, JIMM = 0x080, FUNC = 0x100, - SET = 0x200 + SET = 0x200, + SCIMM = 0x400 }; #define OP_MASK 0x3f @@ -52,6 +53,8 @@ enum fields { #define FUNC_SH 0 #define SET_MASK 0x7 #define SET_SH 0 +#define SCIMM_MASK 0xfffff +#define SCIMM_SH 6 enum opcode { insn_invalid, @@ -64,7 +67,7 @@ enum opcode { insn_mtc0, insn_ori, insn_pref, insn_rfe, insn_sc, insn_scd, insn_sd, insn_sll, insn_sra, insn_srl, insn_rotr, insn_subu, insn_sw, insn_tlbp, insn_tlbr, insn_tlbwi, insn_tlbwr, insn_xor, insn_xori, - insn_dins + insn_dins, insn_syscall }; struct insn { @@ -136,6 +139,7 @@ static struct insn insn_table[] __cpuinitdata = { { insn_xor, M(spec_op, 0, 0, 0, 0, xor_op), RS | RT | RD }, { insn_xori, M(xori_op, 0, 0, 0, 0, 0), RS | RT | UIMM }, { insn_dins, M(spec3_op, 0, 0, 0, 0, dins_op), RS | RT | RD | RE }, + { insn_syscall, M(spec_op, 0, 0, 0, 0, syscall_op), SCIMM}, { insn_invalid, 0, 0 } }; @@ -208,6 +212,14 @@ static inline __cpuinit u32 build_jimm(u32 arg) return (arg >> 2) & JIMM_MASK; } +static inline __cpuinit u32 build_scimm(u32 arg) +{ + if (arg & ~SCIMM_MASK) + printk(KERN_WARNING "Micro-assembler field overflow\n"); + + return (arg & SCIMM_MASK) << SCIMM_SH; +} + static inline __cpuinit u32 build_func(u32 arg) { if (arg & ~FUNC_MASK) @@ -266,6 +278,8 @@ static void __cpuinit build_insn(u32 **buf, enum opcode opc, ...) op |= build_func(va_arg(ap, u32)); if (ip->fields & SET) op |= build_set(va_arg(ap, u32)); + if (ip->fields & SCIMM) + op |= build_scimm(va_arg(ap, u32)); va_end(ap); **buf = op; @@ -391,6 +405,7 @@ I_0(_tlbwr) I_u3u1u2(_xor) I_u2u1u3(_xori) I_u2u1msbu3(_dins); +I_u1(_syscall); /* Handle labels. */ void __cpuinit uasm_build_label(struct uasm_label **lab, u32 *addr, int lid) -- 1.6.6 From David.Daney@caviumnetworks.com Fri Feb 19 03:03:23 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 19 Feb 2010 03:03:30 +0100 (CET) Received: from mail3.caviumnetworks.com ([12.108.191.235]:11250 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492183Ab0BSCDW (ORCPT ); Fri, 19 Feb 2010 03:03:22 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Thu, 18 Feb 2010 18:03:29 -0800 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Thu, 18 Feb 2010 18:02:19 -0800 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Thu, 18 Feb 2010 18:02:19 -0800 Message-ID: <4B7DF12B.6090802@caviumnetworks.com> Date: Thu, 18 Feb 2010 18:02:19 -0800 From: David Daney User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.7) Gecko/20100120 Fedora/3.0.1-1.fc12 Thunderbird/3.0.1 MIME-Version: 1.0 To: David Daney CC: linux-mips@linux-mips.org, ralf@linux-mips.org Subject: Re: [PATCH 0/3] MIPS vdso and signal delivery optimization (v2) References: <1266538385-29088-1-git-send-email-ddaney@caviumnetworks.com> In-Reply-To: <1266538385-29088-1-git-send-email-ddaney@caviumnetworks.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 19 Feb 2010 02:02:19.0504 (UTC) FILETIME=[915B2F00:01CAB107] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25961 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Well this patch set does cause gdb to no longer be able to generate stack traces from signal handlers, but that just means gdb needs to be fixed. We will work on that next. libgcc can unwind through signal handlers both with and without the patch. David Daney On 02/18/2010 04:13 PM, David Daney wrote: > This patch set creates a vdso and moves the signal > trampolines to it from their previous home on the stack. > > In the original patch set: > http://www.linux-mips.org/cgi-bin/mesg.cgi?a=linux-mips&i=49EE3B0F.3040506%40caviumnetworks.com > > I stated: > > Tested with a 64-bit kernel on a Cavium Octeon cn3860 where I have the > following results from lmbench2: > > Before: > n64 - Signal handler overhead: 14.517 microseconds > n32 - Signal handler overhead: 14.497 microseconds > o32 - Signal handler overhead: 16.637 microseconds > > After: > > n64 - Signal handler overhead: 7.935 microseconds > n32 - Signal handler overhead: 7.334 microseconds > o32 - Signal handler overhead: 8.628 microsecond > > All that is still true. > > Improvements from the first version: > > * Compiles and runs in 32-bit kernels (on qemu at least). > > * Updated for linux-queue based 2.6.33-rc8 > > David Daney (3): > MIPS: Add SYSCALL to uasm. > MIPS: Preliminary vdso. > MIPS: Move signal trampolines off of the stack. > > arch/mips/include/asm/abi.h | 6 +- > arch/mips/include/asm/elf.h | 4 + > arch/mips/include/asm/mmu.h | 5 +- > arch/mips/include/asm/mmu_context.h | 2 +- > arch/mips/include/asm/processor.h | 11 +++- > arch/mips/include/asm/uasm.h | 1 + > arch/mips/include/asm/vdso.h | 29 +++++++++ > arch/mips/kernel/Makefile | 2 +- > arch/mips/kernel/signal-common.h | 5 -- > arch/mips/kernel/signal.c | 86 ++++++--------------------- > arch/mips/kernel/signal32.c | 55 ++++------------- > arch/mips/kernel/signal_n32.c | 26 ++------ > arch/mips/kernel/syscall.c | 6 ++- > arch/mips/kernel/vdso.c | 112 +++++++++++++++++++++++++++++++++++ > arch/mips/mm/uasm.c | 19 +++++- > 15 files changed, 226 insertions(+), 143 deletions(-) > create mode 100644 arch/mips/include/asm/vdso.h > create mode 100644 arch/mips/kernel/vdso.c > > From ralf@linux-mips.org Fri Feb 19 14:57:32 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 19 Feb 2010 14:57:36 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:39478 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1492468Ab0BSN5c (ORCPT ); Fri, 19 Feb 2010 14:57:32 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id o1JDvT1s018845; Fri, 19 Feb 2010 14:57:30 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id o1JDvSfb018843; Fri, 19 Feb 2010 14:57:28 +0100 Date: Fri, 19 Feb 2010 14:57:27 +0100 From: Ralf Baechle To: David Daney Cc: linux-mips@linux-mips.org Subject: Re: [PATCH 0/3] MIPS vdso and signal delivery optimization (v2) Message-ID: <20100219135727.GA15581@linux-mips.org> References: <1266538385-29088-1-git-send-email-ddaney@caviumnetworks.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1266538385-29088-1-git-send-email-ddaney@caviumnetworks.com> User-Agent: Mutt/1.5.20 (2009-08-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25962 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Thu, Feb 18, 2010 at 04:13:02PM -0800, David Daney wrote: > Before: > n64 - Signal handler overhead: 14.517 microseconds > n32 - Signal handler overhead: 14.497 microseconds > o32 - Signal handler overhead: 16.637 microseconds > > After: > > n64 - Signal handler overhead: 7.935 microseconds > n32 - Signal handler overhead: 7.334 microseconds > o32 - Signal handler overhead: 8.628 microsecond On a 180MHz 2 CPU single-node IP27: Before: Signal handler installation: 3.524 microseconds Signal handler overhead: 37.009 microseconds Protection fault: 4.264 microseconds After: Signal handler installation: 3.536 microseconds Signal handler overhead: 14.331 microseconds Protection fault: 3.600 microseconds Everything meassured with very ancient O32 lmbench 2-alpha11 binaries. IP27 has processors in separate packages so the cache-to-cache overhead and thus the speedup is much higher than you have observed. In 2.4 we used to have drastically better signal latency numbers btw. I wonder where all that performance went down the drain. Ralf From ralf@linux-mips.org Fri Feb 19 15:38:47 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 19 Feb 2010 15:38:50 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:42036 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1492477Ab0BSOir (ORCPT ); Fri, 19 Feb 2010 15:38:47 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id o1JEcj1t019769; Fri, 19 Feb 2010 15:38:45 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id o1JEcifk019766; Fri, 19 Feb 2010 15:38:44 +0100 Date: Fri, 19 Feb 2010 15:38:44 +0100 From: Ralf Baechle To: David Daney Cc: linux-mips@linux-mips.org Subject: Re: [PATCH 0/3] MIPS vdso and signal delivery optimization (v2) Message-ID: <20100219143844.GA19417@linux-mips.org> References: <1266538385-29088-1-git-send-email-ddaney@caviumnetworks.com> <20100219135727.GA15581@linux-mips.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20100219135727.GA15581@linux-mips.org> User-Agent: Mutt/1.5.20 (2009-08-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25963 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Fri, Feb 19, 2010 at 02:57:27PM +0100, Ralf Baechle wrote: > > Before: > > n64 - Signal handler overhead: 14.517 microseconds > > n32 - Signal handler overhead: 14.497 microseconds > > o32 - Signal handler overhead: 16.637 microseconds > > > > After: > > > > n64 - Signal handler overhead: 7.935 microseconds > > n32 - Signal handler overhead: 7.334 microseconds > > o32 - Signal handler overhead: 8.628 microsecond > > On a 180MHz 2 CPU single-node IP27: > > Before: > Signal handler installation: 3.524 microseconds > Signal handler overhead: 37.009 microseconds > Protection fault: 4.264 microseconds > > After: > Signal handler installation: 3.536 microseconds > Signal handler overhead: 14.331 microseconds > Protection fault: 3.600 microseconds > > Everything meassured with very ancient O32 lmbench 2-alpha11 binaries. > IP27 has processors in separate packages so the cache-to-cache overhead > and thus the speedup is much higher than you have observed. I dug up an old 2.6.12-rc1 kernel binary and reran lmbench on the same system: Signal handler installation: 4.207 microseconds Signal handler overhead: 29.618 microseconds Protection fault: 2.105 microseconds And on 2.4.25: Signal handler installation: 3.674 microseconds Signal handler overhead: 8.855 microseconds Protection fault: 3.159 microseconds Ralf From David.Daney@caviumnetworks.com Fri Feb 19 23:09:04 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 19 Feb 2010 23:09:09 +0100 (CET) Received: from mail3.caviumnetworks.com ([12.108.191.235]:7506 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491925Ab0BSWJE (ORCPT ); Fri, 19 Feb 2010 23:09:04 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Fri, 19 Feb 2010 14:09:09 -0800 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Fri, 19 Feb 2010 14:08:22 -0800 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Fri, 19 Feb 2010 14:08:22 -0800 Message-ID: <4B7F0BD4.3070909@caviumnetworks.com> Date: Fri, 19 Feb 2010 14:08:20 -0800 From: David Daney User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.7) Gecko/20100120 Fedora/3.0.1-1.fc12 Thunderbird/3.0.1 MIME-Version: 1.0 To: ralf@linux-mips.org CC: linux-mips@linux-mips.org Subject: Re: [PATCH 0/3] MIPS vdso and signal delivery optimization (v2) References: <1266538385-29088-1-git-send-email-ddaney@caviumnetworks.com> <4B7DF12B.6090802@caviumnetworks.com> In-Reply-To: <4B7DF12B.6090802@caviumnetworks.com> Content-Type: multipart/mixed; boundary="------------070502040600090805080501" X-OriginalArrivalTime: 19 Feb 2010 22:08:22.0509 (UTC) FILETIME=[0D1179D0:01CAB1B0] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25964 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips This is a multi-part message in MIME format. --------------070502040600090805080501 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit On 02/18/2010 06:02 PM, David Daney wrote: > Well this patch set does cause gdb to no longer be able to generate > stack traces from signal handlers, but that just means gdb needs to be > fixed. We will work on that next. Attached is the corresponding gdb patch. I will push it into the upstream gdb. David Daney > > libgcc can unwind through signal handlers both with and without the patch. > > David Daney > > > On 02/18/2010 04:13 PM, David Daney wrote: >> This patch set creates a vdso and moves the signal >> trampolines to it from their previous home on the stack. >> >> In the original patch set: >> http://www.linux-mips.org/cgi-bin/mesg.cgi?a=linux-mips&i=49EE3B0F.3040506%40caviumnetworks.com >> >> >> I stated: >> >> Tested with a 64-bit kernel on a Cavium Octeon cn3860 where I have the >> following results from lmbench2: >> >> Before: >> n64 - Signal handler overhead: 14.517 microseconds >> n32 - Signal handler overhead: 14.497 microseconds >> o32 - Signal handler overhead: 16.637 microseconds >> >> After: >> >> n64 - Signal handler overhead: 7.935 microseconds >> n32 - Signal handler overhead: 7.334 microseconds >> o32 - Signal handler overhead: 8.628 microsecond >> >> All that is still true. >> >> Improvements from the first version: >> >> * Compiles and runs in 32-bit kernels (on qemu at least). >> >> * Updated for linux-queue based 2.6.33-rc8 >> >> David Daney (3): >> MIPS: Add SYSCALL to uasm. >> MIPS: Preliminary vdso. >> MIPS: Move signal trampolines off of the stack. >> >> arch/mips/include/asm/abi.h | 6 +- >> arch/mips/include/asm/elf.h | 4 + >> arch/mips/include/asm/mmu.h | 5 +- >> arch/mips/include/asm/mmu_context.h | 2 +- >> arch/mips/include/asm/processor.h | 11 +++- >> arch/mips/include/asm/uasm.h | 1 + >> arch/mips/include/asm/vdso.h | 29 +++++++++ >> arch/mips/kernel/Makefile | 2 +- >> arch/mips/kernel/signal-common.h | 5 -- >> arch/mips/kernel/signal.c | 86 ++++++--------------------- >> arch/mips/kernel/signal32.c | 55 ++++------------- >> arch/mips/kernel/signal_n32.c | 26 ++------ >> arch/mips/kernel/syscall.c | 6 ++- >> arch/mips/kernel/vdso.c | 112 +++++++++++++++++++++++++++++++++++ >> arch/mips/mm/uasm.c | 19 +++++- >> 15 files changed, 226 insertions(+), 143 deletions(-) >> create mode 100644 arch/mips/include/asm/vdso.h >> create mode 100644 arch/mips/kernel/vdso.c >> >> > > --------------070502040600090805080501 Content-Type: text/plain; name="gdb.patch" Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename="gdb.patch" Index: gdb/mips-linux-tdep.c =================================================================== RCS file: /cvs/src/src/gdb/mips-linux-tdep.c,v retrieving revision 1.81 diff -u -p -r1.81 mips-linux-tdep.c --- gdb/mips-linux-tdep.c 1 Jan 2010 07:31:37 -0000 1.81 +++ gdb/mips-linux-tdep.c 19 Feb 2010 21:58:32 -0000 @@ -797,7 +797,7 @@ static const struct tramp_frame mips_lin struct sigframe { u32 sf_ass[4]; [argument save space for o32] - u32 sf_code[2]; [signal trampoline] + u32 sf_code[2]; [signal trampoline or fill] struct sigcontext sf_sc; sigset_t sf_mask; }; @@ -827,7 +827,7 @@ static const struct tramp_frame mips_lin struct rt_sigframe { u32 rs_ass[4]; [argument save space for o32] - u32 rs_code[2] [signal trampoline] + u32 rs_code[2] [signal trampoline or fill] struct siginfo rs_info; struct ucontext rs_uc; }; @@ -871,7 +871,7 @@ mips_linux_o32_sigframe_init (const stru { struct gdbarch *gdbarch = get_frame_arch (this_frame); int ireg, reg_position; - CORE_ADDR sigcontext_base = func - SIGFRAME_CODE_OFFSET; + CORE_ADDR sigcontext_base = get_frame_sp (this_frame); const struct mips_regnum *regs = mips_regnum (gdbarch); CORE_ADDR regs_base; @@ -1038,7 +1038,7 @@ mips_linux_n32n64_sigframe_init (const s { struct gdbarch *gdbarch = get_frame_arch (this_frame); int ireg, reg_position; - CORE_ADDR sigcontext_base = func - SIGFRAME_CODE_OFFSET; + CORE_ADDR sigcontext_base = get_frame_sp (this_frame); const struct mips_regnum *regs = mips_regnum (gdbarch); if (self == &mips_linux_n32_rt_sigframe) --------------070502040600090805080501-- From ralf@linux-mips.org Sat Feb 20 12:31:46 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 20 Feb 2010 12:31:50 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:44672 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491850Ab0BTLbq (ORCPT ); Sat, 20 Feb 2010 12:31:46 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id o1KBVcxr004265; Sat, 20 Feb 2010 12:31:40 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id o1KBVaUI004151; Sat, 20 Feb 2010 12:31:36 +0100 Date: Sat, 20 Feb 2010 12:31:34 +0100 From: Ralf Baechle To: linux-mips@linux-mips.org, Yoichi Yuasa , Bjorn Helgaas Subject: Reverting old hack Message-ID: <20100220113134.GA27194@linux-mips.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline User-Agent: Mutt/1.5.20 (2009-08-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25965 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Below 9f7670e4ddd940d95e48997c2da51614e5fde2cf, an old hack which I committed in December '07 I think mostly for Cobalt machines. This is now getting in the way - in fact the whole loop in pcibios_fixup_device_resources() may have to go. So I wonder if this old hack is still necessary. Only testing can answer so I'm going to put a patch to revert this into the -queue tree for 2.6.34. Ralf [MIPS] PCI: Make pcibios_fixup_device_resources ignore legacy resources. There might be other reasons why a resource might be marked as fixed such as a PCI UART holding the system console but until we use IORESOURCE_PCI_FIXED that way also this will work. Signed-off-by: Ralf Baechle diff --git a/arch/mips/pci/pci.c b/arch/mips/pci/pci.c index 589b745..6e6981f 100644 --- a/arch/mips/pci/pci.c +++ b/arch/mips/pci/pci.c @@ -242,6 +242,8 @@ static void pcibios_fixup_device_resources(struct pci_dev *dev, for (i = 0; i < PCI_NUM_RESOURCES; i++) { if (!dev->resource[i].start) continue; + if (dev->resource[i].flags & IORESOURCE_PCI_FIXED) + continue; if (dev->resource[i].flags & IORESOURCE_IO) offset = hose->io_offset; else if (dev->resource[i].flags & IORESOURCE_MEM) From yuasa.linux@gmail.com Sat Feb 20 13:18:24 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 20 Feb 2010 13:18:29 +0100 (CET) Received: from mail-yx0-f193.google.com ([209.85.210.193]:54246 "EHLO mail-yx0-f193.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492127Ab0BTMSY (ORCPT ); Sat, 20 Feb 2010 13:18:24 +0100 Received: by yxe31 with SMTP id 31so1007447yxe.21 for ; Sat, 20 Feb 2010 04:18:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:sender:date:from:to:cc :subject:message-id:in-reply-to:references:x-mailer:mime-version :content-type:content-transfer-encoding; bh=EXlb4DFlbKNM3wcdVWdVPerT7abKnVz0eXNYVeNpRtY=; b=Yap7fbyFi8QGJXw70Dzn7hWrD5BIiB36AWzWrcAZrYg30OlIeSYk8vKrxe+iAPp+YS UiifQc21ogdy8BhZIxZHDPEBXOAqzzlr5xyb6iTG8FN7HucyHbLuVhXYd84DRR9EkZMx 1QJFKf4mZRN45gG3wxQMYqBSCIzL6IWbYEfNE= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:date:from:to:cc:subject:message-id:in-reply-to:references :x-mailer:mime-version:content-type:content-transfer-encoding; b=JuwztLSRRbGfZO9DIRZrkRCReEnsKTdmtbbQt9EeRWRgUPy/O/G5h5ZG9nehuHg/6B V3dY5FSkpS7aKBw86Xxxxr7g5kY0pTy9nZSebX4am8gpZGe4sEUZl54qq+oDpA4z9TbR slA6+2SV6pAOoBqsoOpHnpOpaxkuOZ0U/8x3w= Received: by 10.100.222.5 with SMTP id u5mr6873819ang.247.1266668297636; Sat, 20 Feb 2010 04:18:17 -0800 (PST) Received: from ypsilon.skybright.jp (sannin29006.nirai.ne.jp [203.160.29.6]) by mx.google.com with ESMTPS id 13sm971072gxk.8.2010.02.20.04.18.14 (version=TLSv1/SSLv3 cipher=RC4-MD5); Sat, 20 Feb 2010 04:18:16 -0800 (PST) Date: Sat, 20 Feb 2010 21:18:05 +0900 From: Yoichi Yuasa To: Ralf Baechle Cc: yuasa@linux-mips.org, linux-mips@linux-mips.org, Bjorn Helgaas Subject: Re: Reverting old hack Message-Id: <20100220211805.6a33e9e2.yuasa@linux-mips.org> In-Reply-To: <20100220113134.GA27194@linux-mips.org> References: <20100220113134.GA27194@linux-mips.org> X-Mailer: Sylpheed 2.7.1 (GTK+ 2.16.6; i686-pc-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25966 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: yuasa@linux-mips.org Precedence: bulk X-list: linux-mips Hi Ralf, On Sat, 20 Feb 2010 12:31:34 +0100 Ralf Baechle wrote: > Below 9f7670e4ddd940d95e48997c2da51614e5fde2cf, an old hack which I > committed in December '07 I think mostly for Cobalt machines. This is > now getting in the way - in fact the whole loop in > pcibios_fixup_device_resources() may have to go. So I wonder if this > old hack is still necessary. Only testing can answer so I'm going to > put a patch to revert this into the -queue tree for 2.6.34. It is still necessary for Cobalt. I got the following IDE resource errors. pata_via 0000:00:09.1: BAR 0: can't reserve [io 0xf00001f0-0xf00001f7] pata_via 0000:00:09.1: failed to request/iomap BARs for port 0 (errno=-16) pata_via 0000:00:09.1: BAR 2: can't reserve [io 0xf0000170-0xf0000177] pata_via 0000:00:09.1: failed to request/iomap BARs for port 1 (errno=-16) pata_via 0000:00:09.1: no available native port Yoichi From yuasa.linux@gmail.com Sat Feb 20 13:20:52 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 20 Feb 2010 13:20:55 +0100 (CET) Received: from mail-gx0-f224.google.com ([209.85.217.224]:49004 "EHLO mail-gx0-f224.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492127Ab0BTMUv (ORCPT ); Sat, 20 Feb 2010 13:20:51 +0100 Received: by gxk24 with SMTP id 24so1144078gxk.7 for ; Sat, 20 Feb 2010 04:20:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:sender:date:from:to:cc :subject:message-id:x-mailer:mime-version:content-type :content-transfer-encoding; bh=JL8vcaqt/N+2VgPwVXoapC3pRIQYUz+kwbEQqsQcRm8=; b=EGJ+8oJPqahZd5xzukxODwHd10ge7GjDB29xpFMZ7bP5bJYChQzbDDG5H9xSLA7nbE 1bSGUJvvqMq3ac9QFsvTVRpuQYgf6KIBxltmXIjpokW6Nq6B4b7Yj6qYz+OQ+TgjCE3O fVkKL1QN324QSLZIxFhaB4DGYqsq/BPvB4g7c= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:date:from:to:cc:subject:message-id:x-mailer:mime-version :content-type:content-transfer-encoding; b=DRDdcl7R6eVMdD+rR1mvpH7Y0u2Bq4WJgtZi1slt+rQWvpMRYDoGB7fc2JBB6KP93+ DESZTsKuGmZ8e3hGGZKARwKy4XIqknIglET9gp7uqOFBq1xqCUgUREFMNUIs9J14+pX6 dSzLUigQmpLXf8r13FIkQfg4WGzyD3N6gjEgc= Received: by 10.101.155.38 with SMTP id h38mr3749549ano.131.1266668445351; Sat, 20 Feb 2010 04:20:45 -0800 (PST) Received: from ypsilon.skybright.jp (sannin29006.nirai.ne.jp [203.160.29.6]) by mx.google.com with ESMTPS id 15sm969475gxk.10.2010.02.20.04.20.43 (version=TLSv1/SSLv3 cipher=RC4-MD5); Sat, 20 Feb 2010 04:20:44 -0800 (PST) Date: Sat, 20 Feb 2010 21:20:34 +0900 From: Yoichi Yuasa To: Ralf Baechle Cc: yuasa@linux-mips.org, linux-mips Subject: MIPS: cleanup sgialib.h Message-Id: <20100220212034.fff9dd2d.yuasa@linux-mips.org> X-Mailer: Sylpheed 2.7.1 (GTK+ 2.16.6; i686-pc-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25967 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: yuasa@linux-mips.org Precedence: bulk X-list: linux-mips The unused definitions are removed. Signed-off-by: Yoichi Yuasa --- arch/mips/include/asm/sgialib.h | 45 --------------------------------------- 1 files changed, 0 insertions(+), 45 deletions(-) diff --git a/arch/mips/include/asm/sgialib.h b/arch/mips/include/asm/sgialib.h index 63741ca..2a2f1bd 100644 --- a/arch/mips/include/asm/sgialib.h +++ b/arch/mips/include/asm/sgialib.h @@ -33,14 +33,6 @@ extern int prom_flags; extern void prom_putchar(char c); extern char prom_getchar(void); -/* Memory descriptor management. */ -#define PROM_MAX_PMEMBLOCKS 32 -struct prom_pmemblock { - LONG base; /* Within KSEG0 or XKPHYS. */ - ULONG size; /* In bytes. */ - ULONG type; /* free or prom memory */ -}; - /* Get next memory descriptor after CURR, returns first descriptor * in chain is CURR is NULL. */ @@ -51,7 +43,6 @@ extern struct linux_mdesc *prom_getmdesc(struct linux_mdesc *curr); * array. */ extern void prom_meminit(void); -extern void prom_fixup_mem_map(unsigned long start_mem, unsigned long end_mem); /* PROM device tree library routines. */ #define PROM_NULL_COMPONENT ((pcomponent *) 0) @@ -62,20 +53,6 @@ extern pcomponent *ArcGetPeer(pcomponent *this); /* Get child component of THIS. */ extern pcomponent *ArcGetChild(pcomponent *this); -/* Get parent component of CHILD. */ -extern pcomponent *prom_getparent(pcomponent *child); - -/* Copy component opaque data of component THIS into BUFFER - * if component THIS has opaque data. Returns success or - * failure status. - */ -extern long prom_getcdata(void *buffer, pcomponent *this); - -/* Other misc. component routines. */ -extern pcomponent *prom_childadd(pcomponent *this, pcomponent *tmp, void *data); -extern long prom_delcomponent(pcomponent *this); -extern pcomponent *prom_componentbypath(char *path); - /* This is called at prom_init time to identify the * ARC architecture we are running on */ @@ -88,35 +65,13 @@ extern LONG ArcSetEnvironmentVariable(PCHAR name, PCHAR value); /* ARCS command line parsing. */ extern void prom_init_cmdline(void); -/* Acquiring info about the current time, etc. */ -extern struct linux_tinfo *prom_gettinfo(void); -extern unsigned long prom_getrtime(void); - /* File operations. */ -extern long prom_getvdirent(unsigned long fd, struct linux_vdirent *ent, unsigned long num, unsigned long *cnt); -extern long prom_open(char *name, enum linux_omode md, unsigned long *fd); -extern long prom_close(unsigned long fd); extern LONG ArcRead(ULONG fd, PVOID buf, ULONG num, PULONG cnt); -extern long prom_getrstatus(unsigned long fd); extern LONG ArcWrite(ULONG fd, PVOID buf, ULONG num, PULONG cnt); -extern long prom_seek(unsigned long fd, struct linux_bigint *off, enum linux_seekmode sm); -extern long prom_mount(char *name, enum linux_mountops op); -extern long prom_getfinfo(unsigned long fd, struct linux_finfo *buf); -extern long prom_setfinfo(unsigned long fd, unsigned long flags, unsigned long msk); - -/* Running stand-along programs. */ -extern long prom_load(char *name, unsigned long end, unsigned long *pc, unsigned long *eaddr); -extern long prom_invoke(unsigned long pc, unsigned long sp, long argc, char **argv, char **envp); -extern long prom_exec(char *name, long argc, char **argv, char **envp); /* Misc. routines. */ -extern VOID prom_halt(VOID) __attribute__((noreturn)); -extern VOID prom_powerdown(VOID) __attribute__((noreturn)); -extern VOID prom_restart(VOID) __attribute__((noreturn)); extern VOID ArcReboot(VOID) __attribute__((noreturn)); extern VOID ArcEnterInteractiveMode(VOID) __attribute__((noreturn)); -extern long prom_cfgsave(VOID); -extern struct linux_sysid *prom_getsysid(VOID); extern VOID ArcFlushAllCaches(VOID); extern DISPLAY_STATUS *ArcGetDisplayStatus(ULONG FileID); -- 1.7.0 From yuasa.linux@gmail.com Sat Feb 20 13:23:40 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 20 Feb 2010 13:23:43 +0100 (CET) Received: from mail-gx0-f224.google.com ([209.85.217.224]:45684 "EHLO mail-gx0-f224.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492141Ab0BTMXk (ORCPT ); Sat, 20 Feb 2010 13:23:40 +0100 Received: by gxk24 with SMTP id 24so1146004gxk.7 for ; Sat, 20 Feb 2010 04:23:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:sender:date:from:to:cc :subject:message-id:x-mailer:mime-version:content-type :content-transfer-encoding; bh=k6C+4pl3q3FQdoajqnPIQsZ1OyVxALulHiw7vVQTxho=; b=rnFDP4h6oUZ4pzb5RDIHlGQu+9tYw6fwVFTMgXPdl/fLch+v2GoagkfmVdCgf6CIZg DgDwiTDFS/m/4i2mKyvNA8bXlEoPxJlJWyun8YML8riL0aYrqIgcykmg0AxLeGI7bjKj YediGz7qmh0v9AbcqsV7uVLGzrgDLg4tOjzeY= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:date:from:to:cc:subject:message-id:x-mailer:mime-version :content-type:content-transfer-encoding; b=MRkY3zUr7Y6xcXwgxkQZ0BWsg0zWWSSWgvsun01LhBOus2MtnhMputIwh/uetW1y5M poiuXrFl3JiHpQLUQM2BCRjoRQ7OErlwz1JZv89KfZgaZhh0xkls6FzJXS9Pl7msIjzc Y2PI7sSj3aLXFJ0xzR1530tzFaVCr7KJEUw90= Received: by 10.101.145.15 with SMTP id x15mr2376721ann.8.1266668613281; Sat, 20 Feb 2010 04:23:33 -0800 (PST) Received: from ypsilon.skybright.jp (sannin29006.nirai.ne.jp [203.160.29.6]) by mx.google.com with ESMTPS id 13sm975191gxk.8.2010.02.20.04.23.31 (version=TLSv1/SSLv3 cipher=RC4-MD5); Sat, 20 Feb 2010 04:23:32 -0800 (PST) Date: Sat, 20 Feb 2010 21:23:22 +0900 From: Yoichi Yuasa To: Ralf Baechle Cc: yuasa@linux-mips.org, linux-mips Subject: [PATCH -queue] MIPS: fix HIGHMEM build error Message-Id: <20100220212322.03c5eb09.yuasa@linux-mips.org> X-Mailer: Sylpheed 2.7.1 (GTK+ 2.16.6; i686-pc-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25968 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: yuasa@linux-mips.org Precedence: bulk X-list: linux-mips arch/mips/mm/highmem.c: In function 'kmap_init': arch/mips/mm/highmem.c:130: error: 'init_mm' undeclared (first use in this function) arch/mips/mm/highmem.c:130: error: (Each undeclared identifier is reported only once arch/mips/mm/highmem.c:130: error: for each function it appears in.) Signed-off-by: Yoichi Yuasa --- arch/mips/mm/highmem.c | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/arch/mips/mm/highmem.c b/arch/mips/mm/highmem.c index e274fda..127d732 100644 --- a/arch/mips/mm/highmem.c +++ b/arch/mips/mm/highmem.c @@ -1,5 +1,6 @@ #include #include +#include #include #include #include -- 1.7.0 From bjorn.helgaas@hp.com Sat Feb 20 16:04:35 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 20 Feb 2010 16:04:39 +0100 (CET) Received: from g5t0007.atlanta.hp.com ([15.192.0.44]:9428 "EHLO g5t0007.atlanta.hp.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492420Ab0BTPEf (ORCPT ); Sat, 20 Feb 2010 16:04:35 +0100 Received: from g5t0030.atlanta.hp.com (g5t0030.atlanta.hp.com [16.228.8.142]) by g5t0007.atlanta.hp.com (Postfix) with ESMTP id 973C614427; Sat, 20 Feb 2010 15:04:28 +0000 (UTC) Received: from ldl (ldl.fc.hp.com [15.11.146.30]) by g5t0030.atlanta.hp.com (Postfix) with ESMTP id F3719140B4; Sat, 20 Feb 2010 15:04:27 +0000 (UTC) Received: from localhost (ldl.fc.hp.com [127.0.0.1]) by ldl (Postfix) with ESMTP id C5A25CF00C7; Sat, 20 Feb 2010 08:04:27 -0700 (MST) Received: from ldl ([127.0.0.1]) by localhost (ldl.fc.hp.com [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 0n7LAvLRFmar; Sat, 20 Feb 2010 08:04:27 -0700 (MST) Received: from [192.168.1.2] (squirrel.fc.hp.com [15.11.146.57]) by ldl (Postfix) with ESMTP id 56D07CF0013; Sat, 20 Feb 2010 08:04:27 -0700 (MST) Subject: Re: Reverting old hack From: Bjorn Helgaas To: Yoichi Yuasa Cc: Ralf Baechle , linux-mips@linux-mips.org In-Reply-To: <20100220211805.6a33e9e2.yuasa@linux-mips.org> References: <20100220113134.GA27194@linux-mips.org> <20100220211805.6a33e9e2.yuasa@linux-mips.org> Content-Type: text/plain Date: Sat, 20 Feb 2010 07:57:49 -0700 Message-Id: <1266677869.1320.8.camel@dc7800.home> Mime-Version: 1.0 X-Mailer: Evolution 2.22.3.1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25969 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: bjorn.helgaas@hp.com Precedence: bulk X-list: linux-mips On Sat, 2010-02-20 at 21:18 +0900, Yoichi Yuasa wrote: > Hi Ralf, > > On Sat, 20 Feb 2010 12:31:34 +0100 > Ralf Baechle wrote: > > > Below 9f7670e4ddd940d95e48997c2da51614e5fde2cf, an old hack which I > > committed in December '07 I think mostly for Cobalt machines. This is > > now getting in the way - in fact the whole loop in > > pcibios_fixup_device_resources() may have to go. So I wonder if this > > old hack is still necessary. Only testing can answer so I'm going to > > put a patch to revert this into the -queue tree for 2.6.34. > > It is still necessary for Cobalt. > I got the following IDE resource errors. > > pata_via 0000:00:09.1: BAR 0: can't reserve [io 0xf00001f0-0xf00001f7] > pata_via 0000:00:09.1: failed to request/iomap BARs for port 0 (errno=-16) > pata_via 0000:00:09.1: BAR 2: can't reserve [io 0xf0000170-0xf0000177] > pata_via 0000:00:09.1: failed to request/iomap BARs for port 1 (errno=-16) > pata_via 0000:00:09.1: no available native port Thanks for trying that out. I'd like to understand the PCI architecture of Cobalt better. Would you mind turning on CONFIG_PCI_DEBUG and posting the dmesg log? The purpose of IORESOURCE_PCI_FIXED is to say that we shouldn't reassign the device resources. But the pcibios_fixup_device_resources() loop isn't *moving* devices, it's merely converting PCI bus addresses to CPU addresses. So I suspect that the IORESOURCE_PCI_FIXED test there is merely covering up another bug. For example, maybe 00:09.1 is an internal device that's behind a different host bridge that does no address conversion, or maybe the host bridge just handles that device specially. If something like that is happening, pcibios_bus_to_resource() should be broken for that device, and fixing that should allow us to remove the IORESOURCE_PCI_FIXED test. Bjorn From aba@not.so.argh.org Sat Feb 20 18:51:35 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 20 Feb 2010 18:51:38 +0100 (CET) Received: from alius.ayous.org ([78.46.213.165]:39211 "EHLO alius.ayous.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491954Ab0BTRvf (ORCPT ); Sat, 20 Feb 2010 18:51:35 +0100 Received: from eos.turmzimmer.net ([2001:a60:f006:aba::1]) by alius.turmzimmer.net with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.69) (envelope-from ) id 1NitUJ-0005fL-Up; Sat, 20 Feb 2010 17:51:32 +0000 Received: from aba by eos.turmzimmer.net with local (Exim 4.69) (envelope-from ) id 1NitUE-00078k-04; Sat, 20 Feb 2010 18:51:26 +0100 Date: Sat, 20 Feb 2010 18:51:25 +0100 From: Andreas Barth To: linux-mips@linux-mips.org Subject: Problems and workarounds while building octeon kernels Message-ID: <20100220175125.GQ27216@mails.so.argh.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline X-Editor: Vim http://www.vim.org/ User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25970 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: aba@not.so.argh.org Precedence: bulk X-list: linux-mips Hi, I tried to build an recent linux 2.6.33-rc something in an unstable Debian chroot. I had the following issues (plus workarounds / fixes) - please don't hesitate to ask me if you have further questions. error: arch/mips/cavium-octeon/built-in.o: In function `prom_init': (.init.text+0x974): undefined reference to `early_serial_setup' arch/mips/cavium-octeon/built-in.o: In function `prom_init': (.init.text+0x974): relocation truncated to fit: R_MIPS_26 against `early_serial_setup' arch/mips/cavium-octeon/built-in.o: In function `flash_init': fix: enabled configuration for serial console support error: flash_setup.c:(.init.text+0x12dc): undefined reference to `simple_map_init' flash_setup.c:(.init.text+0x12dc): relocation truncated to fit: R_MIPS_26 against `simple_map_init' flash_setup.c:(.init.text+0x12ec): undefined reference to `do_map_probe' flash_setup.c:(.init.text+0x12ec): relocation truncated to fit: R_MIPS_26 against `do_map_probe' flash_setup.c:(.init.text+0x1314): undefined reference to `parse_mtd_partitions' flash_setup.c:(.init.text+0x1314): relocation truncated to fit: R_MIPS_26 against `parse_mtd_partitions' flash_setup.c:(.init.text+0x1330): undefined reference to `add_mtd_partitions' flash_setup.c:(.init.text+0x1330): relocation truncated to fit: R_MIPS_26 against `add_mtd_partitions' flash_setup.c:(.init.text+0x1340): undefined reference to `add_mtd_device' flash_setup.c:(.init.text+0x1340): relocation truncated to fit: R_MIPS_26 against `add_mtd_device' fix: set drivers/mtd to y (instead of m) error: arch/mips/cavium-octeon/built-in.o: In function `sched_clock': (.text.sched_clock+0x24): undefined reference to `__lshrti3' arch/mips/cavium-octeon/built-in.o: In function `sched_clock': (.text.sched_clock+0x24): relocation truncated to fit: R_MIPS_26 against `__lshrti3' workaround: in arch/mips/cavium-octeon/csrc-octeon.c #if (__GNUC__ < 4) || ((__GNUC__ == 4) && (__GNUC_MINOR__ <= 3)) replaced by something that always uses "the ugly way" ERROR: "i8253_lock" [drivers/input/misc/pcspkr.ko] undefined! fix: disable pc speaker support Cheers, Andi From hauke@hauke-m.de Sat Feb 20 19:51:48 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 20 Feb 2010 19:51:52 +0100 (CET) Received: from [193.201.54.104] ([193.201.54.104]:56926 "EHLO hauke-m.de" rhost-flags-FAIL-FAIL-OK-OK) by eddie.linux-mips.org with ESMTP id S1492063Ab0BTSvs (ORCPT ); Sat, 20 Feb 2010 19:51:48 +0100 Received: from localhost (localhost [127.0.0.1]) by hauke-m.de (Postfix) with ESMTP id 3FB1F8587; Sat, 20 Feb 2010 19:51:27 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at hauke-m.de Received: from hauke-m.de ([127.0.0.1]) by localhost (hauke-m.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id uDuCebCU-+31; Sat, 20 Feb 2010 19:51:24 +0100 (CET) Received: from localhost.localdomain (host-091-096-211-027.ewe-ip-backbone.de [91.96.211.27]) by hauke-m.de (Postfix) with ESMTPSA id EEFB17E29; Sat, 20 Feb 2010 19:51:23 +0100 (CET) From: Hauke Mehrtens To: ralf@linux-mips.org Cc: linux-mips@linux-mips.org, Hauke Mehrtens Subject: [PATCH] MIPS: Bcm47xx: Fix 128MB RAM support Date: Sat, 20 Feb 2010 19:51:20 +0100 Message-Id: <1266691880-372-1-git-send-email-hauke@hauke-m.de> X-Mailer: git-send-email 1.6.3.3 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25971 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hauke@hauke-m.de Precedence: bulk X-list: linux-mips Ignoring the last page when ddr size is 128M. Cached accesses to last page is causing the processor to prefetch using address above 128M stepping out of the ddr address space. Signed-off-by: Hauke Mehrtens --- arch/mips/bcm47xx/prom.c | 8 ++++++++ 1 files changed, 8 insertions(+), 0 deletions(-) diff --git a/arch/mips/bcm47xx/prom.c b/arch/mips/bcm47xx/prom.c index 5efc995..0fa646c 100644 --- a/arch/mips/bcm47xx/prom.c +++ b/arch/mips/bcm47xx/prom.c @@ -141,6 +141,14 @@ static __init void prom_init_mem(void) break; } + /* Ignoring the last page when ddr size is 128M. Cached + * accesses to last page is causing the processor to prefetch + * using address above 128M stepping out of the ddr address + * space. + */ + if (mem == 0x8000000) + mem -= 0x1000; + add_memory_region(0, mem, BOOT_MEM_RAM); } -- 1.6.3.3 From bjorn.helgaas@hp.com Sun Feb 21 04:04:24 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 21 Feb 2010 04:04:27 +0100 (CET) Received: from g6t0184.atlanta.hp.com ([15.193.32.61]:6033 "EHLO g6t0184.atlanta.hp.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492238Ab0BUDEY (ORCPT ); Sun, 21 Feb 2010 04:04:24 +0100 Received: from g5t0030.atlanta.hp.com (g5t0030.atlanta.hp.com [16.228.8.142]) by g6t0184.atlanta.hp.com (Postfix) with ESMTP id 9C735C3C8; Sun, 21 Feb 2010 03:04:17 +0000 (UTC) Received: from ldl (ldl.fc.hp.com [15.11.146.30]) by g5t0030.atlanta.hp.com (Postfix) with ESMTP id 84BA91402B; Sun, 21 Feb 2010 03:04:10 +0000 (UTC) Received: from localhost (ldl.fc.hp.com [127.0.0.1]) by ldl (Postfix) with ESMTP id 50CDCCF00D8; Sat, 20 Feb 2010 20:04:10 -0700 (MST) Received: from ldl ([127.0.0.1]) by localhost (ldl.fc.hp.com [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id TmluHbeICV-a; Sat, 20 Feb 2010 20:04:10 -0700 (MST) Received: from [192.168.1.2] (squirrel.fc.hp.com [15.11.146.57]) by ldl (Postfix) with ESMTP id CCE7DCF0013; Sat, 20 Feb 2010 20:04:09 -0700 (MST) Subject: Re: Reverting old hack From: Bjorn Helgaas To: Yoichi Yuasa Cc: Ralf Baechle , linux-mips@linux-mips.org In-Reply-To: <20100220211805.6a33e9e2.yuasa@linux-mips.org> References: <20100220113134.GA27194@linux-mips.org> <20100220211805.6a33e9e2.yuasa@linux-mips.org> Content-Type: text/plain Date: Sat, 20 Feb 2010 19:57:30 -0700 Message-Id: <1266721050.1959.10.camel@dc7800.home> Mime-Version: 1.0 X-Mailer: Evolution 2.22.3.1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25972 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: bjorn.helgaas@hp.com Precedence: bulk X-list: linux-mips On Sat, 2010-02-20 at 21:18 +0900, Yoichi Yuasa wrote: > Hi Ralf, > > On Sat, 20 Feb 2010 12:31:34 +0100 > Ralf Baechle wrote: > > > Below 9f7670e4ddd940d95e48997c2da51614e5fde2cf, an old hack which I > > committed in December '07 I think mostly for Cobalt machines. This is > > now getting in the way - in fact the whole loop in > > pcibios_fixup_device_resources() may have to go. So I wonder if this > > old hack is still necessary. Only testing can answer so I'm going to > > put a patch to revert this into the -queue tree for 2.6.34. > > It is still necessary for Cobalt. > I got the following IDE resource errors. > > pata_via 0000:00:09.1: BAR 0: can't reserve [io 0xf00001f0-0xf00001f7] > pata_via 0000:00:09.1: failed to request/iomap BARs for port 0 (errno=-16) > pata_via 0000:00:09.1: BAR 2: can't reserve [io 0xf0000170-0xf0000177] > pata_via 0000:00:09.1: failed to request/iomap BARs for port 1 (errno=-16) > pata_via 0000:00:09.1: no available native port I think the problem is that cobalt_io_resource contains PCI bus addresses when it should contain CPU addresses: static struct resource cobalt_io_resource = { .start = 0x1000, .end = GT_DEF_PCI0_IO_SIZE - 1, .name = "PCI I/O", .flags = IORESOURCE_IO, }; I think .start and .end need to be adjusted by GT_DEF_PCI0_IO_BASE. Bjorn From yuasa.linux@gmail.com Sun Feb 21 08:45:50 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 21 Feb 2010 08:45:55 +0100 (CET) Received: from mail-yx0-f194.google.com ([209.85.210.194]:34714 "EHLO mail-yx0-f194.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491074Ab0BUHpu (ORCPT ); Sun, 21 Feb 2010 08:45:50 +0100 Received: by yxe32 with SMTP id 32so2542800yxe.0 for ; Sat, 20 Feb 2010 23:45:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:sender:date:from:to:cc :subject:message-id:in-reply-to:references:x-mailer:mime-version :content-type:content-transfer-encoding; bh=GXW0uUf3/JA0Ta7VDJtNFaCOlDD2uDzAWJIRKzyIyzs=; b=pc7yv3EIQ3ZRU6FSA30XwCh+szoFYbbLYZqYdgqPu27qOdak67oWHS3XIA5bjGkF1Y MuhCjz7Joj0ERLp/fYJbSMFx/dyq5gFrfiZcwMGFp5R6apRV1th9hB7h3H6gDlHsrPxO F3MeMVS9LNsoTVSiGC/ym1l/jgXq15yg0IsOg= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:date:from:to:cc:subject:message-id:in-reply-to:references :x-mailer:mime-version:content-type:content-transfer-encoding; b=CjYhaPSHc6xjqTjESOxhpeQaez74Y9GeE0FAeshLTRX7TR95qBe2g9xFAg4kj2cfVL WV/SPURvH0zwx1E+0QEwoiQtfkb+WeWz8HCN9ltcD4N45Ar3mvI8y1d2hzImcjOAQRXe 3EXyXgQmoOP6jcUP4hRbvbeat6yqQ5eiFOS+k= Received: by 10.101.207.28 with SMTP id j28mr3551106anq.193.1266738343080; Sat, 20 Feb 2010 23:45:43 -0800 (PST) Received: from ypsilon.skybright.jp (sannin29006.nirai.ne.jp [203.160.29.6]) by mx.google.com with ESMTPS id 16sm1933122gxk.13.2010.02.20.23.45.40 (version=TLSv1/SSLv3 cipher=RC4-MD5); Sat, 20 Feb 2010 23:45:42 -0800 (PST) Date: Sun, 21 Feb 2010 16:45:31 +0900 From: Yoichi Yuasa To: Bjorn Helgaas Cc: yuasa@linux-mips.org, Ralf Baechle , linux-mips@linux-mips.org Subject: Re: Reverting old hack Message-Id: <20100221164531.382b3785.yuasa@linux-mips.org> In-Reply-To: <1266677869.1320.8.camel@dc7800.home> References: <20100220113134.GA27194@linux-mips.org> <20100220211805.6a33e9e2.yuasa@linux-mips.org> <1266677869.1320.8.camel@dc7800.home> X-Mailer: Sylpheed 2.7.1 (GTK+ 2.16.6; i686-pc-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25973 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: yuasa@linux-mips.org Precedence: bulk X-list: linux-mips Hi Bjorn, On Sat, 20 Feb 2010 07:57:49 -0700 Bjorn Helgaas wrote: > On Sat, 2010-02-20 at 21:18 +0900, Yoichi Yuasa wrote: > > Hi Ralf, > > > > On Sat, 20 Feb 2010 12:31:34 +0100 > > Ralf Baechle wrote: > > > > > Below 9f7670e4ddd940d95e48997c2da51614e5fde2cf, an old hack which I > > > committed in December '07 I think mostly for Cobalt machines. This is > > > now getting in the way - in fact the whole loop in > > > pcibios_fixup_device_resources() may have to go. So I wonder if this > > > old hack is still necessary. Only testing can answer so I'm going to > > > put a patch to revert this into the -queue tree for 2.6.34. > > > > It is still necessary for Cobalt. > > I got the following IDE resource errors. > > > > pata_via 0000:00:09.1: BAR 0: can't reserve [io 0xf00001f0-0xf00001f7] > > pata_via 0000:00:09.1: failed to request/iomap BARs for port 0 (errno=-16) > > pata_via 0000:00:09.1: BAR 2: can't reserve [io 0xf0000170-0xf0000177] > > pata_via 0000:00:09.1: failed to request/iomap BARs for port 1 (errno=-16) > > pata_via 0000:00:09.1: no available native port > > Thanks for trying that out. > > I'd like to understand the PCI architecture of Cobalt better. Would you > mind turning on CONFIG_PCI_DEBUG and posting the dmesg log? If you want to know what happen, you can see my old e-mail. http://marc.info/?l=linux-kernel&m=118792430424186&w=2 > The purpose of IORESOURCE_PCI_FIXED is to say that we shouldn't reassign > the device resources. But the pcibios_fixup_device_resources() loop > isn't *moving* devices, it's merely converting PCI bus addresses to CPU > addresses. So I suspect that the IORESOURCE_PCI_FIXED test there is > merely covering up another bug. Please look at the following e-mail why this fix was not applied. http://marc.info/?l=linux-kernel&m=119690002215135&w=2 > For example, maybe 00:09.1 is an internal device that's behind a > different host bridge that does no address conversion, or maybe the host > bridge just handles that device specially. If something like that is > happening, pcibios_bus_to_resource() should be broken for that device, > and fixing that should allow us to remove the IORESOURCE_PCI_FIXED test. Yoichi From f.fainelli@gmail.com Sun Feb 21 18:46:31 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 21 Feb 2010 18:46:37 +0100 (CET) Received: from mail-ew0-f212.google.com ([209.85.219.212]:54659 "EHLO mail-ew0-f212.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491998Ab0BURqa (ORCPT ); Sun, 21 Feb 2010 18:46:30 +0100 Received: by ewy4 with SMTP id 4so565366ewy.27 for ; Sun, 21 Feb 2010 09:46:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:sender:from:date:subject :mime-version:x-uid:x-length:to:cc:reply-to:content-type :content-transfer-encoding:message-id; bh=HNwnWDKsWc10LSIWnPKgI72RMxfLqyoBZzqW1fOhnv4=; b=koruia2K1efuVBJq1cFmAxX1uKZoztMnGkINd/UIthB6WNZrdPoQ9ylFSMrwuTv3ku 3lkUhUeanMbrT9YH/InBe2TXB+hq0b/e9VI0N3nTG9u1HUehW64BlIkfoWZNw/V47Ndg q43khSAHDddNtrnyzZfE2etDeANFHFbwuTWko= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:from:date:subject:mime-version:x-uid:x-length:to:cc:reply-to :content-type:content-transfer-encoding:message-id; b=p7G9okdDuG46N9Fuk/4Of+GcflpaDcjGwP/ZymkPn2rgOnAcZJqmcYedwsNpyL1gNQ Y+m1j5S16L3uNLC0hTxpaZG9uNidhqeoUc2v7ZuNSb19pJp+YE0v0p6JKzIcfA6TrYyR bhEnkAQvbdMe7Zu/LK+GdEPMqBlHYKFl+P0mw= Received: by 10.213.96.203 with SMTP id i11mr3718654ebn.9.1266774385308; Sun, 21 Feb 2010 09:46:25 -0800 (PST) Received: from lenovo.localnet (153.44.69-86.rev.gaoland.net [86.69.44.153]) by mx.google.com with ESMTPS id 5sm7103073eyh.16.2010.02.21.09.46.23 (version=TLSv1/SSLv3 cipher=RC4-MD5); Sun, 21 Feb 2010 09:46:24 -0800 (PST) From: Florian Fainelli Date: Sun, 21 Feb 2010 18:46:22 +0100 Subject: [PATCH -queue] loongson2: fix compile error on arch/mips/oprofile/op_model_loongson2.c MIME-Version: 1.0 X-UID: 170 X-Length: 1432 To: linux-mips@linux-mips.org Cc: wuzhangjin@gmail.com, ralf@linux-mips.org Reply-To: Florian Fainelli Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <201002211846.22504.florian@openwrt.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25974 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips flags is now an unused variable, causing a build failure due to -Werror being turned on. Signed-off-by: Florian Fainelli --- diff --git a/arch/mips/oprofile/op_model_loongson2.c b/arch/mips/oprofile/op_model_loongson2.c index 2ffd47a..29e2326 100644 --- a/arch/mips/oprofile/op_model_loongson2.c +++ b/arch/mips/oprofile/op_model_loongson2.c @@ -113,7 +113,6 @@ static irqreturn_t loongson2_perfcount_handler(int irq, void *dev_id) uint64_t counter, counter1, counter2; struct pt_regs *regs = get_irq_regs(); int enabled; - unsigned long flags; /* * LOONGSON2 defines two 32-bit performance counters. From bjorn.helgaas@hp.com Mon Feb 22 01:16:08 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 22 Feb 2010 01:16:11 +0100 (CET) Received: from g6t0184.atlanta.hp.com ([15.193.32.61]:7977 "EHLO g6t0184.atlanta.hp.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492130Ab0BVAQI (ORCPT ); Mon, 22 Feb 2010 01:16:08 +0100 Received: from g5t0030.atlanta.hp.com (g5t0030.atlanta.hp.com [16.228.8.142]) by g6t0184.atlanta.hp.com (Postfix) with ESMTP id 84D24C28A; Mon, 22 Feb 2010 00:16:01 +0000 (UTC) Received: from ldl (ldl.fc.hp.com [15.11.146.30]) by g5t0030.atlanta.hp.com (Postfix) with ESMTP id 547EF14010; Mon, 22 Feb 2010 00:16:00 +0000 (UTC) Received: from localhost (ldl.fc.hp.com [127.0.0.1]) by ldl (Postfix) with ESMTP id 25C64CF0013; Sun, 21 Feb 2010 17:16:00 -0700 (MST) Received: from ldl ([127.0.0.1]) by localhost (ldl.fc.hp.com [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id nM+AIKgl2rM6; Sun, 21 Feb 2010 17:16:00 -0700 (MST) Received: from [192.168.1.2] (squirrel.fc.hp.com [15.11.146.57]) by ldl (Postfix) with ESMTP id 9FE12CF0007; Sun, 21 Feb 2010 17:15:59 -0700 (MST) Subject: Re: Reverting old hack From: Bjorn Helgaas To: Yoichi Yuasa Cc: Ralf Baechle , linux-mips@linux-mips.org In-Reply-To: <1266721050.1959.10.camel@dc7800.home> References: <20100220113134.GA27194@linux-mips.org> <20100220211805.6a33e9e2.yuasa@linux-mips.org> <1266721050.1959.10.camel@dc7800.home> Content-Type: text/plain Date: Sun, 21 Feb 2010 17:09:18 -0700 Message-Id: <1266797358.1959.12.camel@dc7800.home> Mime-Version: 1.0 X-Mailer: Evolution 2.22.3.1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25975 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: bjorn.helgaas@hp.com Precedence: bulk X-list: linux-mips On Sat, 2010-02-20 at 19:57 -0700, Bjorn Helgaas wrote: > On Sat, 2010-02-20 at 21:18 +0900, Yoichi Yuasa wrote: > > Hi Ralf, > > > > On Sat, 20 Feb 2010 12:31:34 +0100 > > Ralf Baechle wrote: > > > > > Below 9f7670e4ddd940d95e48997c2da51614e5fde2cf, an old hack which I > > > committed in December '07 I think mostly for Cobalt machines. This is > > > now getting in the way - in fact the whole loop in > > > pcibios_fixup_device_resources() may have to go. So I wonder if this > > > old hack is still necessary. Only testing can answer so I'm going to > > > put a patch to revert this into the -queue tree for 2.6.34. > > > > It is still necessary for Cobalt. > > I got the following IDE resource errors. > > > > pata_via 0000:00:09.1: BAR 0: can't reserve [io 0xf00001f0-0xf00001f7] > > pata_via 0000:00:09.1: failed to request/iomap BARs for port 0 (errno=-16) > > pata_via 0000:00:09.1: BAR 2: can't reserve [io 0xf0000170-0xf0000177] > > pata_via 0000:00:09.1: failed to request/iomap BARs for port 1 (errno=-16) > > pata_via 0000:00:09.1: no available native port > > I think the problem is that cobalt_io_resource contains PCI bus > addresses when it should contain CPU addresses: > > static struct resource cobalt_io_resource = { > .start = 0x1000, > .end = GT_DEF_PCI0_IO_SIZE - 1, > .name = "PCI I/O", > .flags = IORESOURCE_IO, > }; > > I think .start and .end need to be adjusted by GT_DEF_PCI0_IO_BASE. Sorry, this was a half-baked answer. This would probably fix the reservation conflicts, but of course we'll still have a problem when we remove the IORESOURCE_PCI_FIXED check. I'll work on it more and come up with a patch. Bjorn From bjorn.helgaas@hp.com Mon Feb 22 06:14:28 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 22 Feb 2010 06:14:34 +0100 (CET) Received: from g5t0007.atlanta.hp.com ([15.192.0.44]:47609 "EHLO g5t0007.atlanta.hp.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1490959Ab0BVFO2 (ORCPT ); Mon, 22 Feb 2010 06:14:28 +0100 Received: from g5t0030.atlanta.hp.com (g5t0030.atlanta.hp.com [16.228.8.142]) by g5t0007.atlanta.hp.com (Postfix) with ESMTP id 71909140B3; Mon, 22 Feb 2010 05:14:20 +0000 (UTC) Received: from ldl (ldl.fc.hp.com [15.11.146.30]) by g5t0030.atlanta.hp.com (Postfix) with ESMTP id 52DF014125; Mon, 22 Feb 2010 05:14:19 +0000 (UTC) Received: from localhost (ldl.fc.hp.com [127.0.0.1]) by ldl (Postfix) with ESMTP id 29401CF0013; Sun, 21 Feb 2010 22:14:19 -0700 (MST) Received: from ldl ([127.0.0.1]) by localhost (ldl.fc.hp.com [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id aMTsDgq2vZld; Sun, 21 Feb 2010 22:14:19 -0700 (MST) Received: from [192.168.1.2] (squirrel.fc.hp.com [15.11.146.57]) by ldl (Postfix) with ESMTP id 4DDABCF0007; Sun, 21 Feb 2010 22:14:18 -0700 (MST) Subject: Re: Reverting old hack From: Bjorn Helgaas To: Yoichi Yuasa Cc: Ralf Baechle , linux-mips@linux-mips.org In-Reply-To: <20100220211805.6a33e9e2.yuasa@linux-mips.org> References: <20100220113134.GA27194@linux-mips.org> <20100220211805.6a33e9e2.yuasa@linux-mips.org> Content-Type: text/plain Date: Sun, 21 Feb 2010 22:07:37 -0700 Message-Id: <1266815257.1959.23.camel@dc7800.home> Mime-Version: 1.0 X-Mailer: Evolution 2.22.3.1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25976 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: bjorn.helgaas@hp.com Precedence: bulk X-list: linux-mips On Sat, 2010-02-20 at 21:18 +0900, Yoichi Yuasa wrote: > Hi Ralf, > > On Sat, 20 Feb 2010 12:31:34 +0100 > Ralf Baechle wrote: > > > Below 9f7670e4ddd940d95e48997c2da51614e5fde2cf, an old hack which I > > committed in December '07 I think mostly for Cobalt machines. This is > > now getting in the way - in fact the whole loop in > > pcibios_fixup_device_resources() may have to go. So I wonder if this > > old hack is still necessary. Only testing can answer so I'm going to > > put a patch to revert this into the -queue tree for 2.6.34. > > It is still necessary for Cobalt. > I got the following IDE resource errors. > > pata_via 0000:00:09.1: BAR 0: can't reserve [io 0xf00001f0-0xf00001f7] > pata_via 0000:00:09.1: failed to request/iomap BARs for port 0 (errno=-16) > pata_via 0000:00:09.1: BAR 2: can't reserve [io 0xf0000170-0xf0000177] > pata_via 0000:00:09.1: failed to request/iomap BARs for port 1 (errno=-16) > pata_via 0000:00:09.1: no available native port I think Cobalt needs something like the patch below, because I think in your working system, pata_via is using I/O port 0x1f0, not 0xf00001f0. That means the the port the driver sees in the pci_dev resource is identical to the port number that appears on the PCI bus, so there is no io_offset. There are a few other places that may set non-zero io_offset values: bcm1480, bcm1480ht. txx9_alloc_pci_controller(), bridge_probe(), and octeon_pcie_setup(). I don't know whether they have similar issues. commit 7378269220d477118257d898bec9173743675f5e Author: Bjorn Helgaas Date: Sat Feb 20 07:52:29 2010 -0700 [MIPS] remove Cobalt I/O space offset On Cobalt, "inb(x)" produces an I/O port access to port "x" on the PCI bus, which means the io_offset is zero and CPU (resource) addresses are identical to PCI bus addresses. Correcting this means we can remove the IORESOURCE_PCI_FIXED check from pcibios_fixup_device_resources(). The io_map_base is used internally by pci_iomap(), inb(), and other I/O port access functions to generate an MMIO access to the address that produces the desired I/O port PCI transaction. [Cobalt plat_mem_setup() does this: set_io_port_base(CKSEG1ADDR(GT_DEF_PCI0_IO_BASE)); rather than using cobalt_pci_controller.io_map_base, but the value's the same, and I don't know enough to clean that up.] See http://lkml.org/lkml/2007/7/29/27 Signed-off-by: Bjorn Helgaas diff --git a/arch/mips/cobalt/pci.c b/arch/mips/cobalt/pci.c index cfce7af..84aa205 100644 --- a/arch/mips/cobalt/pci.c +++ b/arch/mips/cobalt/pci.c @@ -34,7 +34,6 @@ static struct pci_controller cobalt_pci_controller = { .pci_ops = >64xxx_pci0_ops, .mem_resource = &cobalt_mem_resource, .io_resource = &cobalt_io_resource, - .io_offset = 0 - GT_DEF_PCI0_IO_BASE, .io_map_base = CKSEG1ADDR(GT_DEF_PCI0_IO_BASE), }; diff --git a/arch/mips/pci/pci.c b/arch/mips/pci/pci.c index f87f5e1..38bc280 100644 --- a/arch/mips/pci/pci.c +++ b/arch/mips/pci/pci.c @@ -251,8 +251,6 @@ static void pcibios_fixup_device_resources(struct pci_dev *dev, for (i = 0; i < PCI_NUM_RESOURCES; i++) { if (!dev->resource[i].start) continue; - if (dev->resource[i].flags & IORESOURCE_PCI_FIXED) - continue; if (dev->resource[i].flags & IORESOURCE_IO) offset = hose->io_offset; else if (dev->resource[i].flags & IORESOURCE_MEM) From yuasa.linux@gmail.com Mon Feb 22 07:39:51 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 22 Feb 2010 07:39:54 +0100 (CET) Received: from mail-yx0-f194.google.com ([209.85.210.194]:56700 "EHLO mail-yx0-f194.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491187Ab0BVGjv (ORCPT ); Mon, 22 Feb 2010 07:39:51 +0100 Received: by yxe32 with SMTP id 32so4751241yxe.0 for ; Sun, 21 Feb 2010 22:39:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:sender:date:from:to:cc :subject:message-id:in-reply-to:references:x-mailer:mime-version :content-type:content-transfer-encoding; bh=VwhPodmt+FHzCF+WR+I6AO74ddvjW+H4/uTheuycIRg=; b=OEwS8v1Hb2LP7i2LoLgkJ8xYdJctpFQ74hondwyXpx1lrtYMv7WbJVHIKDzshasfUL 6h+Suw6bvXtpjjSU0wcvRriVw5jerY6HlMmjgE1OtlsISI2tnM4w1KfPHTHXSM3se0qX WAKWnqtsGcu4Q0mrSlgfrr1oK3Ab1Pm5mgUOo= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:date:from:to:cc:subject:message-id:in-reply-to:references :x-mailer:mime-version:content-type:content-transfer-encoding; b=Plxp9z6lmtVAMYtlUsE5T597E/nJvYFZM7t03NTv6sm3q2HaCvoUqxd19YH+woPFjz 3eaCn8BV0u8pTskU2vuwgU0ZtW5RsnxWPE65Q3MBVnh3XvRkL2wivNFj3bGEBIEg4R3Z dKeWC0GqfIz+LWcaGEu+XEWnukGu73Ng4t1q0= Received: by 10.101.144.1 with SMTP id w1mr2942970ann.61.1266820783149; Sun, 21 Feb 2010 22:39:43 -0800 (PST) Received: from ypsilon.skybright.jp (sannin29006.nirai.ne.jp [203.160.29.6]) by mx.google.com with ESMTPS id 14sm3058295gxk.7.2010.02.21.22.39.40 (version=TLSv1/SSLv3 cipher=RC4-MD5); Sun, 21 Feb 2010 22:39:42 -0800 (PST) Date: Mon, 22 Feb 2010 15:39:32 +0900 From: Yoichi Yuasa To: Bjorn Helgaas Cc: yuasa@linux-mips.org, Ralf Baechle , linux-mips@linux-mips.org Subject: Re: Reverting old hack Message-Id: <20100222153932.af1ddc58.yuasa@linux-mips.org> In-Reply-To: <1266815257.1959.23.camel@dc7800.home> References: <20100220113134.GA27194@linux-mips.org> <20100220211805.6a33e9e2.yuasa@linux-mips.org> <1266815257.1959.23.camel@dc7800.home> X-Mailer: Sylpheed 2.7.1 (GTK+ 2.16.6; i686-pc-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25977 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: yuasa@linux-mips.org Precedence: bulk X-list: linux-mips Hi Bjorn, On Sun, 21 Feb 2010 22:07:37 -0700 Bjorn Helgaas wrote: > On Sat, 2010-02-20 at 21:18 +0900, Yoichi Yuasa wrote: > > Hi Ralf, > > > > On Sat, 20 Feb 2010 12:31:34 +0100 > > Ralf Baechle wrote: > > > > > Below 9f7670e4ddd940d95e48997c2da51614e5fde2cf, an old hack which I > > > committed in December '07 I think mostly for Cobalt machines. This is > > > now getting in the way - in fact the whole loop in > > > pcibios_fixup_device_resources() may have to go. So I wonder if this > > > old hack is still necessary. Only testing can answer so I'm going to > > > put a patch to revert this into the -queue tree for 2.6.34. > > > > It is still necessary for Cobalt. > > I got the following IDE resource errors. > > > > pata_via 0000:00:09.1: BAR 0: can't reserve [io 0xf00001f0-0xf00001f7] > > pata_via 0000:00:09.1: failed to request/iomap BARs for port 0 (errno=-16) > > pata_via 0000:00:09.1: BAR 2: can't reserve [io 0xf0000170-0xf0000177] > > pata_via 0000:00:09.1: failed to request/iomap BARs for port 1 (errno=-16) > > pata_via 0000:00:09.1: no available native port > > I think Cobalt needs something like the patch below, because I think in > your working system, pata_via is using I/O port 0x1f0, not 0xf00001f0. > That means the the port the driver sees in the pci_dev resource is > identical to the port number that appears on the PCI bus, so there is no > io_offset. > > There are a few other places that may set non-zero io_offset values: > bcm1480, bcm1480ht. txx9_alloc_pci_controller(), bridge_probe(), and > octeon_pcie_setup(). I don't know whether they have similar issues. > > > > commit 7378269220d477118257d898bec9173743675f5e > Author: Bjorn Helgaas > Date: Sat Feb 20 07:52:29 2010 -0700 > > [MIPS] remove Cobalt I/O space offset > > On Cobalt, "inb(x)" produces an I/O port access to port "x" on the PCI > bus, which means the io_offset is zero and CPU (resource) addresses are > identical to PCI bus addresses. Correcting this means we can remove > the IORESOURCE_PCI_FIXED check from pcibios_fixup_device_resources(). > > The io_map_base is used internally by pci_iomap(), inb(), and other I/O > port access functions to generate an MMIO access to the address that > produces the desired I/O port PCI transaction. > > [Cobalt plat_mem_setup() does this: > set_io_port_base(CKSEG1ADDR(GT_DEF_PCI0_IO_BASE)); > rather than using cobalt_pci_controller.io_map_base, but the value's > the same, and I don't know enough to clean that up.] > > See http://lkml.org/lkml/2007/7/29/27 > > Signed-off-by: Bjorn Helgaas > > diff --git a/arch/mips/cobalt/pci.c b/arch/mips/cobalt/pci.c > index cfce7af..84aa205 100644 > --- a/arch/mips/cobalt/pci.c > +++ b/arch/mips/cobalt/pci.c > @@ -34,7 +34,6 @@ static struct pci_controller cobalt_pci_controller = { > .pci_ops = >64xxx_pci0_ops, > .mem_resource = &cobalt_mem_resource, > .io_resource = &cobalt_io_resource, > - .io_offset = 0 - GT_DEF_PCI0_IO_BASE, > .io_map_base = CKSEG1ADDR(GT_DEF_PCI0_IO_BASE), > }; io_offset is necessary for DEC tulip on Cobalt. It doesn't work when this patch is applied. Yoichi From ralf@linux-mips.org Mon Feb 22 14:28:39 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 22 Feb 2010 14:28:43 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:39177 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1492310Ab0BVN2j (ORCPT ); Mon, 22 Feb 2010 14:28:39 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id o1MDSVMQ005506; Mon, 22 Feb 2010 14:28:32 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id o1MDSU4l005504; Mon, 22 Feb 2010 14:28:30 +0100 Date: Mon, 22 Feb 2010 14:28:30 +0100 From: Ralf Baechle To: Bjorn Helgaas Cc: Yoichi Yuasa , linux-mips@linux-mips.org Subject: Re: Reverting old hack Message-ID: <20100222132830.GA5017@linux-mips.org> References: <20100220113134.GA27194@linux-mips.org> <20100220211805.6a33e9e2.yuasa@linux-mips.org> <1266815257.1959.23.camel@dc7800.home> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1266815257.1959.23.camel@dc7800.home> User-Agent: Mutt/1.5.20 (2009-08-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25978 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Sun, Feb 21, 2010 at 10:07:37PM -0700, Bjorn Helgaas wrote: > > > Below 9f7670e4ddd940d95e48997c2da51614e5fde2cf, an old hack which I > > > committed in December '07 I think mostly for Cobalt machines. This is > > > now getting in the way - in fact the whole loop in > > > pcibios_fixup_device_resources() may have to go. So I wonder if this > > > old hack is still necessary. Only testing can answer so I'm going to > > > put a patch to revert this into the -queue tree for 2.6.34. > > > > It is still necessary for Cobalt. > > I got the following IDE resource errors. > > > > pata_via 0000:00:09.1: BAR 0: can't reserve [io 0xf00001f0-0xf00001f7] > > pata_via 0000:00:09.1: failed to request/iomap BARs for port 0 (errno=-16) > > pata_via 0000:00:09.1: BAR 2: can't reserve [io 0xf0000170-0xf0000177] > > pata_via 0000:00:09.1: failed to request/iomap BARs for port 1 (errno=-16) > > pata_via 0000:00:09.1: no available native port > > I think Cobalt needs something like the patch below, because I think in > your working system, pata_via is using I/O port 0x1f0, not 0xf00001f0. > That means the the port the driver sees in the pci_dev resource is > identical to the port number that appears on the PCI bus, so there is no > io_offset. > > There are a few other places that may set non-zero io_offset values: > bcm1480, bcm1480ht. txx9_alloc_pci_controller(), bridge_probe(), and > octeon_pcie_setup(). I don't know whether they have similar issues. It's a while since I last looked into this but here's how things afair are working on a MIPS-based Cobalt system. The system is based on a MIPS processor and a GT-64111 system controller. Addresses within a certain CPU address range are passed to the PCI bus as I/O cycles without address cycles. Since memory is starting at CPU address zero (and has to because of the processors used), that address window has to get mapped somewhere else. So a CPU access to some virtual address gets translated to physical address 0xf00001f0. The GT-64111 passes this to the PCI bus as I/O port address 0xf00001f0. Finally the VT82C586 chip which only decodes the low 16 bits drops treats this as an I/O port space address 0x1f0. Ralf From David.Daney@caviumnetworks.com Mon Feb 22 18:42:41 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 22 Feb 2010 18:42:44 +0100 (CET) Received: from mail3.caviumnetworks.com ([12.108.191.235]:15939 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491144Ab0BVRml (ORCPT ); Mon, 22 Feb 2010 18:42:41 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Mon, 22 Feb 2010 09:42:49 -0800 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Mon, 22 Feb 2010 09:42:38 -0800 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Mon, 22 Feb 2010 09:42:38 -0800 Message-ID: <4B82C20D.9000302@caviumnetworks.com> Date: Mon, 22 Feb 2010 09:42:37 -0800 From: David Daney User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.7) Gecko/20100120 Fedora/3.0.1-1.fc12 Thunderbird/3.0.1 MIME-Version: 1.0 To: Andreas Barth CC: linux-mips@linux-mips.org Subject: Re: Problems and workarounds while building octeon kernels References: <20100220175125.GQ27216@mails.so.argh.org> In-Reply-To: <20100220175125.GQ27216@mails.so.argh.org> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 22 Feb 2010 17:42:38.0239 (UTC) FILETIME=[6CC832F0:01CAB3E6] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25979 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips On 02/20/2010 09:51 AM, Andreas Barth wrote: > Hi, > > I tried to build an recent linux 2.6.33-rc something in an unstable > Debian chroot. I had the following issues (plus workarounds / fixes) - > please don't hesitate to ask me if you have further questions. > Can you supply the .config as well as tell me the version of GCC you are using? We will endeavor to make this more robust. Thanks, David Daney > > error: > arch/mips/cavium-octeon/built-in.o: In function `prom_init': > (.init.text+0x974): undefined reference to `early_serial_setup' > arch/mips/cavium-octeon/built-in.o: In function `prom_init': > (.init.text+0x974): relocation truncated to fit: R_MIPS_26 against `early_serial_setup' > arch/mips/cavium-octeon/built-in.o: In function `flash_init': > > fix: enabled configuration for serial console support > > > error: > flash_setup.c:(.init.text+0x12dc): undefined reference to `simple_map_init' > flash_setup.c:(.init.text+0x12dc): relocation truncated to fit: R_MIPS_26 against `simple_map_init' > flash_setup.c:(.init.text+0x12ec): undefined reference to `do_map_probe' > flash_setup.c:(.init.text+0x12ec): relocation truncated to fit: R_MIPS_26 against `do_map_probe' > flash_setup.c:(.init.text+0x1314): undefined reference to `parse_mtd_partitions' > flash_setup.c:(.init.text+0x1314): relocation truncated to fit: R_MIPS_26 against `parse_mtd_partitions' > flash_setup.c:(.init.text+0x1330): undefined reference to `add_mtd_partitions' > flash_setup.c:(.init.text+0x1330): relocation truncated to fit: R_MIPS_26 against `add_mtd_partitions' > flash_setup.c:(.init.text+0x1340): undefined reference to `add_mtd_device' > flash_setup.c:(.init.text+0x1340): relocation truncated to fit: R_MIPS_26 against `add_mtd_device' > > fix: set drivers/mtd to y (instead of m) > > > > error: > arch/mips/cavium-octeon/built-in.o: In function `sched_clock': > (.text.sched_clock+0x24): undefined reference to `__lshrti3' > arch/mips/cavium-octeon/built-in.o: In function `sched_clock': > (.text.sched_clock+0x24): relocation truncated to fit: R_MIPS_26 against `__lshrti3' > > workaround: in arch/mips/cavium-octeon/csrc-octeon.c > #if (__GNUC__< 4) || ((__GNUC__ == 4)&& (__GNUC_MINOR__<= 3)) > replaced by something that always uses "the ugly way" > > > ERROR: "i8253_lock" [drivers/input/misc/pcspkr.ko] undefined! > fix: disable pc speaker support > > > Cheers, > Andi > > From ralf@linux-mips.org Mon Feb 22 20:14:43 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 22 Feb 2010 20:14:47 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:55242 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491155Ab0BVTOn (ORCPT ); Mon, 22 Feb 2010 20:14:43 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id o1MJEfOg013430; Mon, 22 Feb 2010 20:14:41 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id o1MJEeQH013428; Mon, 22 Feb 2010 20:14:40 +0100 Date: Mon, 22 Feb 2010 20:14:40 +0100 From: Ralf Baechle To: Hauke Mehrtens Cc: linux-mips@linux-mips.org Subject: Re: [PATCH] MIPS: Bcm47xx: Fix 128MB RAM support Message-ID: <20100222191440.GA12818@linux-mips.org> References: <1266691880-372-1-git-send-email-hauke@hauke-m.de> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1266691880-372-1-git-send-email-hauke@hauke-m.de> User-Agent: Mutt/1.5.20 (2009-08-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25980 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Sat, Feb 20, 2010 at 07:51:20PM +0100, Hauke Mehrtens wrote: > Ignoring the last page when ddr size is 128M. Cached > accesses to last page is causing the processor to prefetch > using address above 128M stepping out of the ddr address > space. Is this a hardware issue prefetching issue? The kernel should not try CPU prefetch instructions at all on non-coherent CPUs such as the BCM47xx. Ralf From ralf@linux-mips.org Mon Feb 22 21:22:11 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 22 Feb 2010 21:22:14 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:45614 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491765Ab0BVUWL (ORCPT ); Mon, 22 Feb 2010 21:22:11 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id o1MKM5Nh023144; Mon, 22 Feb 2010 21:22:06 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id o1MKM4vj023078; Mon, 22 Feb 2010 21:22:04 +0100 Date: Mon, 22 Feb 2010 21:22:04 +0100 From: Ralf Baechle To: Yoichi Yuasa Cc: linux-mips Subject: Re: [PATCH -queue] MIPS: fix HIGHMEM build error Message-ID: <20100222202203.GB5017@linux-mips.org> References: <20100220212322.03c5eb09.yuasa@linux-mips.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20100220212322.03c5eb09.yuasa@linux-mips.org> User-Agent: Mutt/1.5.20 (2009-08-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25981 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Sat, Feb 20, 2010 at 09:23:22PM +0900, Yoichi Yuasa wrote: Applied but to the mainline, not queue. Thanks, Ralf From hauke@hauke-m.de Mon Feb 22 21:25:43 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 22 Feb 2010 21:25:46 +0100 (CET) Received: from [193.201.54.104] ([193.201.54.104]:59274 "EHLO hauke-m.de" rhost-flags-FAIL-FAIL-OK-OK) by eddie.linux-mips.org with ESMTP id S1491791Ab0BVUZn (ORCPT ); Mon, 22 Feb 2010 21:25:43 +0100 Received: from localhost (localhost [127.0.0.1]) by hauke-m.de (Postfix) with ESMTP id 742818586; Mon, 22 Feb 2010 21:25:21 +0100 (CET) X-Virus-Scanned: Debian amavisd-new at hauke-m.de Received: from hauke-m.de ([127.0.0.1]) by localhost (hauke-m.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id fJzzj8Az0qBg; Mon, 22 Feb 2010 21:25:17 +0100 (CET) Received: from [192.168.0.10] (dyndsl-085-016-167-242.ewe-ip-backbone.de [85.16.167.242]) by hauke-m.de (Postfix) with ESMTPSA id 5D1F07E29; Mon, 22 Feb 2010 21:25:17 +0100 (CET) Message-ID: <4B82E827.8030005@hauke-m.de> Date: Mon, 22 Feb 2010 21:25:11 +0100 From: Hauke Mehrtens User-Agent: Thunderbird 2.0.0.23 (X11/20090817) MIME-Version: 1.0 To: Ralf Baechle CC: linux-mips@linux-mips.org Subject: Re: [PATCH] MIPS: Bcm47xx: Fix 128MB RAM support References: <1266691880-372-1-git-send-email-hauke@hauke-m.de> <20100222191440.GA12818@linux-mips.org> In-Reply-To: <20100222191440.GA12818@linux-mips.org> X-Enigmail-Version: 0.95.2 OpenPGP: id=95C58E7B; url=http://www.hauke-m.de/pgp-pubkey.asc Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="------------enig419BDB8C38C823CA19751534" Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25982 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hauke@hauke-m.de Precedence: bulk X-list: linux-mips This is an OpenPGP/MIME signed message (RFC 2440 and 3156) --------------enig419BDB8C38C823CA19751534 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Ralf Baechle wrote: > On Sat, Feb 20, 2010 at 07:51:20PM +0100, Hauke Mehrtens wrote: >=20 >> Ignoring the last page when ddr size is 128M. Cached >> accesses to last page is causing the processor to prefetch >> using address above 128M stepping out of the ddr address >> space. >=20 > Is this a hardware issue prefetching issue? The kernel should not try > CPU prefetch instructions at all on non-coherent CPUs such as the > BCM47xx. This is a hardware issue on the bcm47xx when 128MB ram is present. This workaround is out of broadcom's kernel sources and is included in OpenWRT for some months. Without this patch the kernel does not even print out anything and with this patch it is working. Hauke --------------enig419BDB8C38C823CA19751534 Content-Type: application/pgp-signature; name="signature.asc" Content-Description: OpenPGP digital signature Content-Disposition: attachment; filename="signature.asc" -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.9 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org iQIcBAEBAgAGBQJLgugsAAoJEIZ0px9YPRMyjCIP/RD4Z122pNakR3zM8Bri8AyO nHaRb0QhiSXfcbTCbKOabwWQIXoVK7p4UHqBn25zC494/NFCnc9TppDhitNrd5ey FC3S8FAA/SQAoObPSKOdYHY2pIUWASd2V6y4iN5npEgtVCATFX2bPYepO3UWlvR5 Ib2SYPxlvUCB2B4ugAStZ6rJ9FiLou5zV6Y0/DdsuAUiZCFvEfF6Wn8h2KJmKTNV IwUlY/xQ5P1BRZRk9+nzV20xavBCyur1Ip+TOVoeuU4n1Uircgl1q0MUXD1xmVVn i5Yqv/4S8tVYmzORQ7ihMj6Gu7DaGmy3Q0mFzmdDA9BAfQ9mj6y8Q8n3MwQwaJ44 PaXY9l0LOvhnQOOjeO9e1m4xVA5Uh21paVYzRHVTbro+olpVgI1IGaK47648wkub Dp5hdst/vJNfxcnHTVGvFN1Apmos3AfuoVdDlCcLt2DUEqJ25Cf8usRzhzKYeHnj WcCixtHbBCnDomiTAsGBt2YG+AXEEk1F2CwLveQLmqgae2UYcSUZMCovkYkxJcMI G1x9Az6r6Cu7PkSNy/kkphnXDIxeFnJkbbUkT3goYpzOXUwe6GZNpEXbsyit7NPp cOorceTjdRcCL44YRDOQbZowx64fBxcXPneEI8qZCzzHdNqIbibw2cr1sa3CqUz7 c8smT52nKZpErm52BtpH =EchS -----END PGP SIGNATURE----- --------------enig419BDB8C38C823CA19751534-- From aba@not.so.argh.org Mon Feb 22 21:26:04 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 22 Feb 2010 21:26:14 +0100 (CET) Received: from alius.ayous.org ([78.46.213.165]:60866 "EHLO alius.ayous.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491809Ab0BVUZ4 (ORCPT ); Mon, 22 Feb 2010 21:25:56 +0100 Received: from eos.turmzimmer.net ([192.168.111.2]) by alius.turmzimmer.net with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.69) (envelope-from ) id 1Njeqk-0001AP-RO; Mon, 22 Feb 2010 20:25:51 +0000 Received: from aba by eos.turmzimmer.net with local (Exim 4.69) (envelope-from ) id 1Njeqf-0003G3-G3; Mon, 22 Feb 2010 21:25:45 +0100 Date: Mon, 22 Feb 2010 21:25:45 +0100 From: Andreas Barth To: David Daney Cc: linux-mips@linux-mips.org Subject: Re: Problems and workarounds while building octeon kernels Message-ID: <20100222202545.GV27216@mails.so.argh.org> References: <20100220175125.GQ27216@mails.so.argh.org> <4B82C20D.9000302@caviumnetworks.com> MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="sT9gWZPUZYhvPS56" Content-Disposition: inline In-Reply-To: <4B82C20D.9000302@caviumnetworks.com> X-Editor: Vim http://www.vim.org/ User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25983 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: aba@not.so.argh.org Precedence: bulk X-list: linux-mips --sT9gWZPUZYhvPS56 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline * David Daney (ddaney@caviumnetworks.com) [100222 18:57]: > On 02/20/2010 09:51 AM, Andreas Barth wrote: >> I tried to build an recent linux 2.6.33-rc something in an unstable >> Debian chroot. I had the following issues (plus workarounds / fixes) - >> please don't hesitate to ask me if you have further questions. > Can you supply the .config as well as tell me the version of GCC you are > using? Attached (the compiling variant). gcc is 4.4.3-2. Cheers, Andi --sT9gWZPUZYhvPS56 Content-Type: text/plain; charset=us-ascii Content-Disposition: attachment; filename=linux-config-cavium # # Automatically generated make config: don't edit # Linux kernel version: 2.6.33-rc8 # Sat Feb 20 23:25:39 2010 # CONFIG_MIPS=y # # Machine selection # # CONFIG_MACH_ALCHEMY is not set # CONFIG_AR7 is not set # CONFIG_BCM47XX is not set # CONFIG_BCM63XX is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set # CONFIG_LASAT is not set # CONFIG_MACH_LOONGSON is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SIM is not set # CONFIG_NEC_MARKEINS is not set # CONFIG_MACH_VR41XX is not set # CONFIG_NXP_STB220 is not set # CONFIG_NXP_STB225 is not set # CONFIG_PNX8550_JBS is not set # CONFIG_PNX8550_STB810 is not set # CONFIG_PMC_MSP is not set # CONFIG_PMC_YOSEMITE is not set # CONFIG_POWERTV is not set # CONFIG_SGI_IP22 is not set # CONFIG_SGI_IP27 is not set # CONFIG_SGI_IP28 is not set # CONFIG_SGI_IP32 is not set # CONFIG_SIBYTE_CRHINE is not set # CONFIG_SIBYTE_CARMEL is not set # CONFIG_SIBYTE_CRHONE is not set # CONFIG_SIBYTE_RHONE is not set # CONFIG_SIBYTE_SWARM is not set # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_SENTOSA is not set # CONFIG_SIBYTE_BIGSUR is not set # CONFIG_SNI_RM is not set # CONFIG_MACH_TX39XX is not set # CONFIG_MACH_TX49XX is not set # CONFIG_MIKROTIK_RB532 is not set # CONFIG_WR_PPMC is not set # CONFIG_CAVIUM_OCTEON_SIMULATOR is not set CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD=y # CONFIG_ALCHEMY_GPIO_INDIRECT is not set CONFIG_CAVIUM_OCTEON_SPECIFIC_OPTIONS=y # CONFIG_CAVIUM_OCTEON_2ND_KERNEL is not set CONFIG_CAVIUM_OCTEON_HW_FIX_UNALIGNED=y CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE=1 CONFIG_CAVIUM_OCTEON_LOCK_L2=y CONFIG_CAVIUM_OCTEON_LOCK_L2_TLB=y CONFIG_CAVIUM_OCTEON_LOCK_L2_EXCEPTION=y CONFIG_CAVIUM_OCTEON_LOCK_L2_LOW_LEVEL_INTERRUPT=y CONFIG_CAVIUM_OCTEON_LOCK_L2_INTERRUPT=y CONFIG_CAVIUM_OCTEON_LOCK_L2_MEMCPY=y CONFIG_ARCH_SPARSEMEM_ENABLE=y CONFIG_LOONGSON_UART_BASE=y CONFIG_RWSEM_GENERIC_SPINLOCK=y # CONFIG_ARCH_HAS_ILOG2_U32 is not set # CONFIG_ARCH_HAS_ILOG2_U64 is not set CONFIG_ARCH_SUPPORTS_OPROFILE=y CONFIG_GENERIC_FIND_NEXT_BIT=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_GENERIC_CLOCKEVENTS=y CONFIG_GENERIC_TIME=y CONFIG_GENERIC_CMOS_UPDATE=y CONFIG_SCHED_OMIT_FRAME_POINTER=y CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y CONFIG_CEVT_R4K_LIB=y CONFIG_CEVT_R4K=y CONFIG_DMA_COHERENT=y CONFIG_SYS_HAS_EARLY_PRINTK=y # CONFIG_HOTPLUG_CPU is not set CONFIG_SYS_SUPPORTS_HOTPLUG_CPU=y # CONFIG_NO_IOPORT is not set CONFIG_CPU_BIG_ENDIAN=y # CONFIG_CPU_LITTLE_ENDIAN is not set CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y CONFIG_SYS_SUPPORTS_HUGETLBFS=y CONFIG_IRQ_CPU=y CONFIG_IRQ_CPU_OCTEON=y CONFIG_SWAP_IO_SPACE=y CONFIG_MIPS_L1_CACHE_SHIFT=7 # # CPU selection # # CONFIG_CPU_LOONGSON2E is not set # CONFIG_CPU_LOONGSON2F is not set # CONFIG_CPU_MIPS32_R1 is not set # CONFIG_CPU_MIPS32_R2 is not set # CONFIG_CPU_MIPS64_R1 is not set # CONFIG_CPU_MIPS64_R2 is not set # CONFIG_CPU_R3000 is not set # CONFIG_CPU_TX39XX is not set # CONFIG_CPU_VR41XX is not set # CONFIG_CPU_R4300 is not set # CONFIG_CPU_R4X00 is not set # CONFIG_CPU_TX49XX is not set # CONFIG_CPU_R5000 is not set # CONFIG_CPU_R5432 is not set # CONFIG_CPU_R5500 is not set # CONFIG_CPU_R6000 is not set # CONFIG_CPU_NEVADA is not set # CONFIG_CPU_R8000 is not set # CONFIG_CPU_R10000 is not set # CONFIG_CPU_RM7000 is not set # CONFIG_CPU_RM9000 is not set # CONFIG_CPU_SB1 is not set CONFIG_CPU_CAVIUM_OCTEON=y CONFIG_SYS_HAS_CPU_CAVIUM_OCTEON=y CONFIG_WEAK_ORDERING=y CONFIG_WEAK_REORDERING_BEYOND_LLSC=y CONFIG_CPU_MIPSR2=y CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y CONFIG_CPU_SUPPORTS_HUGEPAGES=y CONFIG_MIPS_PGD_C0_CONTEXT=y CONFIG_HARDWARE_WATCHPOINTS=y # # Kernel type # # CONFIG_32BIT is not set CONFIG_64BIT=y CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_8KB is not set # CONFIG_PAGE_SIZE_16KB is not set # CONFIG_PAGE_SIZE_32KB is not set # CONFIG_PAGE_SIZE_64KB is not set CONFIG_CPU_HAS_PREFETCH=y CONFIG_MIPS_MT_DISABLED=y # CONFIG_MIPS_MT_SMP is not set # CONFIG_MIPS_MT_SMTC is not set CONFIG_64BIT_PHYS_ADDR=y CONFIG_CPU_HAS_SYNC=y CONFIG_GENERIC_HARDIRQS=y CONFIG_GENERIC_IRQ_PROBE=y CONFIG_IRQ_PER_CPU=y CONFIG_CPU_SUPPORTS_HIGHMEM=y CONFIG_SYS_SUPPORTS_HIGHMEM=y CONFIG_ARCH_FLATMEM_ENABLE=y CONFIG_ARCH_POPULATES_NODE_MAP=y CONFIG_SELECT_MEMORY_MODEL=y CONFIG_FLATMEM_MANUAL=y # CONFIG_DISCONTIGMEM_MANUAL is not set # CONFIG_SPARSEMEM_MANUAL is not set CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y CONFIG_SPARSEMEM_STATIC=y CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 CONFIG_PHYS_ADDR_T_64BIT=y CONFIG_ZONE_DMA_FLAG=0 CONFIG_VIRT_TO_BUS=y # CONFIG_KSM is not set CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 CONFIG_SMP=y CONFIG_SYS_SUPPORTS_SMP=y CONFIG_NR_CPUS_DEFAULT_16=y CONFIG_NR_CPUS=16 # CONFIG_NO_HZ is not set # CONFIG_HIGH_RES_TIMERS is not set CONFIG_GENERIC_CLOCKEVENTS_BUILD=y # CONFIG_HZ_48 is not set # CONFIG_HZ_100 is not set # CONFIG_HZ_128 is not set CONFIG_HZ_250=y # CONFIG_HZ_256 is not set # CONFIG_HZ_1000 is not set # CONFIG_HZ_1024 is not set CONFIG_SYS_SUPPORTS_ARBIT_HZ=y CONFIG_HZ=250 CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set # CONFIG_KEXEC is not set CONFIG_SECCOMP=y CONFIG_LOCKDEP_SUPPORT=y CONFIG_STACKTRACE_SUPPORT=y CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" CONFIG_CONSTRUCTORS=y # # General setup # CONFIG_EXPERIMENTAL=y CONFIG_LOCK_KERNEL=y CONFIG_INIT_ENV_ARG_LIMIT=32 CONFIG_LOCALVERSION="-dsa-octeon" CONFIG_LOCALVERSION_AUTO=y CONFIG_SWAP=y CONFIG_SYSVIPC=y CONFIG_SYSVIPC_SYSCTL=y # CONFIG_POSIX_MQUEUE is not set # CONFIG_BSD_PROCESS_ACCT is not set # CONFIG_TASKSTATS is not set # CONFIG_AUDIT is not set # # RCU Subsystem # CONFIG_TREE_RCU=y # CONFIG_TREE_PREEMPT_RCU is not set # CONFIG_TINY_RCU is not set # CONFIG_RCU_TRACE is not set CONFIG_RCU_FANOUT=64 # CONFIG_RCU_FANOUT_EXACT is not set # CONFIG_TREE_RCU_TRACE is not set CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=17 # CONFIG_GROUP_SCHED is not set # CONFIG_CGROUPS is not set CONFIG_SYSFS_DEPRECATED=y CONFIG_SYSFS_DEPRECATED_V2=y # CONFIG_RELAY is not set # CONFIG_NAMESPACES is not set CONFIG_BLK_DEV_INITRD=y CONFIG_INITRAMFS_SOURCE="" CONFIG_RD_GZIP=y # CONFIG_RD_BZIP2 is not set # CONFIG_RD_LZMA is not set # CONFIG_RD_LZO is not set CONFIG_CC_OPTIMIZE_FOR_SIZE=y CONFIG_SYSCTL=y CONFIG_ANON_INODES=y CONFIG_EMBEDDED=y CONFIG_SYSCTL_SYSCALL=y CONFIG_KALLSYMS=y CONFIG_KALLSYMS_ALL=y # CONFIG_KALLSYMS_EXTRA_PASS is not set CONFIG_HOTPLUG=y CONFIG_PRINTK=y CONFIG_BUG=y CONFIG_ELF_CORE=y CONFIG_PCSPKR_PLATFORM=y CONFIG_BASE_FULL=y CONFIG_FUTEX=y CONFIG_EPOLL=y CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y CONFIG_AIO=y # # Kernel Performance Events And Counters # CONFIG_VM_EVENT_COUNTERS=y CONFIG_PCI_QUIRKS=y CONFIG_SLUB_DEBUG=y CONFIG_COMPAT_BRK=y # CONFIG_SLAB is not set CONFIG_SLUB=y # CONFIG_SLOB is not set # CONFIG_PROFILING is not set CONFIG_HAVE_OPROFILE=y CONFIG_HAVE_SYSCALL_WRAPPERS=y CONFIG_USE_GENERIC_SMP_HELPERS=y # # GCOV-based kernel profiling # # CONFIG_GCOV_KERNEL is not set CONFIG_SLOW_WORK=y # CONFIG_SLOW_WORK_DEBUG is not set CONFIG_HAVE_GENERIC_DMA_COHERENT=y CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y CONFIG_BASE_SMALL=0 CONFIG_MODULES=y CONFIG_MODULE_FORCE_LOAD=y CONFIG_MODULE_UNLOAD=y # CONFIG_MODULE_FORCE_UNLOAD is not set CONFIG_MODVERSIONS=y # CONFIG_MODULE_SRCVERSION_ALL is not set CONFIG_STOP_MACHINE=y CONFIG_BLOCK=y CONFIG_BLK_DEV_BSG=y # CONFIG_BLK_DEV_INTEGRITY is not set CONFIG_BLOCK_COMPAT=y # # IO Schedulers # CONFIG_IOSCHED_NOOP=y CONFIG_IOSCHED_DEADLINE=y CONFIG_IOSCHED_CFQ=y # CONFIG_DEFAULT_DEADLINE is not set CONFIG_DEFAULT_CFQ=y # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="cfq" # CONFIG_INLINE_SPIN_TRYLOCK is not set # CONFIG_INLINE_SPIN_TRYLOCK_BH is not set # CONFIG_INLINE_SPIN_LOCK is not set # CONFIG_INLINE_SPIN_LOCK_BH is not set # CONFIG_INLINE_SPIN_LOCK_IRQ is not set # CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set CONFIG_INLINE_SPIN_UNLOCK=y # CONFIG_INLINE_SPIN_UNLOCK_BH is not set CONFIG_INLINE_SPIN_UNLOCK_IRQ=y # CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set # CONFIG_INLINE_READ_TRYLOCK is not set # CONFIG_INLINE_READ_LOCK is not set # CONFIG_INLINE_READ_LOCK_BH is not set # CONFIG_INLINE_READ_LOCK_IRQ is not set # CONFIG_INLINE_READ_LOCK_IRQSAVE is not set CONFIG_INLINE_READ_UNLOCK=y # CONFIG_INLINE_READ_UNLOCK_BH is not set CONFIG_INLINE_READ_UNLOCK_IRQ=y # CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set # CONFIG_INLINE_WRITE_TRYLOCK is not set # CONFIG_INLINE_WRITE_LOCK is not set # CONFIG_INLINE_WRITE_LOCK_BH is not set # CONFIG_INLINE_WRITE_LOCK_IRQ is not set # CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set CONFIG_INLINE_WRITE_UNLOCK=y # CONFIG_INLINE_WRITE_UNLOCK_BH is not set CONFIG_INLINE_WRITE_UNLOCK_IRQ=y # CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set CONFIG_MUTEX_SPIN_ON_OWNER=y # CONFIG_FREEZER is not set # # Bus options (PCI, PCMCIA, EISA, ISA, TC) # CONFIG_HW_HAS_PCI=y CONFIG_PCI=y CONFIG_PCI_DOMAINS=y CONFIG_ARCH_SUPPORTS_MSI=y # CONFIG_PCI_MSI is not set CONFIG_PCI_LEGACY=y CONFIG_PCI_STUB=m CONFIG_PCI_IOV=y CONFIG_MMU=y # CONFIG_PCCARD is not set CONFIG_HOTPLUG_PCI=m # CONFIG_HOTPLUG_PCI_FAKE is not set # CONFIG_HOTPLUG_PCI_CPCI is not set # CONFIG_HOTPLUG_PCI_SHPC is not set # # Executable file formats # CONFIG_BINFMT_ELF=y # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set # CONFIG_HAVE_AOUT is not set # CONFIG_BINFMT_MISC is not set CONFIG_MIPS32_COMPAT=y CONFIG_COMPAT=y CONFIG_SYSVIPC_COMPAT=y CONFIG_MIPS32_O32=y CONFIG_MIPS32_N32=y CONFIG_BINFMT_ELF32=y # # Power management options # CONFIG_ARCH_HIBERNATION_POSSIBLE=y CONFIG_ARCH_SUSPEND_POSSIBLE=y # CONFIG_PM is not set CONFIG_NET=y # # Networking options # # CONFIG_PACKET is not set # CONFIG_UNIX is not set CONFIG_XFRM=y # CONFIG_XFRM_USER is not set # CONFIG_XFRM_SUB_POLICY is not set # CONFIG_XFRM_MIGRATE is not set # CONFIG_XFRM_STATISTICS is not set CONFIG_XFRM_IPCOMP=m # CONFIG_NET_KEY is not set CONFIG_INET=y CONFIG_IP_MULTICAST=y CONFIG_IP_ADVANCED_ROUTER=y CONFIG_ASK_IP_FIB_HASH=y # CONFIG_IP_FIB_TRIE is not set CONFIG_IP_FIB_HASH=y CONFIG_IP_MULTIPLE_TABLES=y CONFIG_IP_ROUTE_MULTIPATH=y CONFIG_IP_ROUTE_VERBOSE=y CONFIG_IP_PNP=y CONFIG_IP_PNP_DHCP=y CONFIG_IP_PNP_BOOTP=y CONFIG_IP_PNP_RARP=y CONFIG_NET_IPIP=m CONFIG_NET_IPGRE=m CONFIG_NET_IPGRE_BROADCAST=y CONFIG_IP_MROUTE=y # CONFIG_IP_PIMSM_V1 is not set # CONFIG_IP_PIMSM_V2 is not set CONFIG_ARPD=y CONFIG_SYN_COOKIES=y CONFIG_INET_AH=m CONFIG_INET_ESP=m CONFIG_INET_IPCOMP=m CONFIG_INET_XFRM_TUNNEL=m CONFIG_INET_TUNNEL=m CONFIG_INET_XFRM_MODE_TRANSPORT=y CONFIG_INET_XFRM_MODE_TUNNEL=y CONFIG_INET_XFRM_MODE_BEET=y CONFIG_INET_LRO=y CONFIG_INET_DIAG=y CONFIG_INET_TCP_DIAG=y CONFIG_TCP_CONG_ADVANCED=y CONFIG_TCP_CONG_BIC=m CONFIG_TCP_CONG_CUBIC=y CONFIG_TCP_CONG_WESTWOOD=m CONFIG_TCP_CONG_HTCP=m # CONFIG_TCP_CONG_HSTCP is not set # CONFIG_TCP_CONG_HYBLA is not set # CONFIG_TCP_CONG_VEGAS is not set # CONFIG_TCP_CONG_SCALABLE is not set # CONFIG_TCP_CONG_LP is not set # CONFIG_TCP_CONG_VENO is not set # CONFIG_TCP_CONG_YEAH is not set # CONFIG_TCP_CONG_ILLINOIS is not set # CONFIG_DEFAULT_BIC is not set CONFIG_DEFAULT_CUBIC=y # CONFIG_DEFAULT_HTCP is not set # CONFIG_DEFAULT_VEGAS is not set # CONFIG_DEFAULT_WESTWOOD is not set # CONFIG_DEFAULT_RENO is not set CONFIG_DEFAULT_TCP_CONG="cubic" CONFIG_TCP_MD5SIG=y CONFIG_IPV6=m CONFIG_IPV6_PRIVACY=y CONFIG_IPV6_ROUTER_PREF=y CONFIG_IPV6_ROUTE_INFO=y CONFIG_IPV6_OPTIMISTIC_DAD=y CONFIG_INET6_AH=m CONFIG_INET6_ESP=m CONFIG_INET6_IPCOMP=m CONFIG_IPV6_MIP6=m CONFIG_INET6_XFRM_TUNNEL=m CONFIG_INET6_TUNNEL=m CONFIG_INET6_XFRM_MODE_TRANSPORT=m CONFIG_INET6_XFRM_MODE_TUNNEL=m CONFIG_INET6_XFRM_MODE_BEET=m CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m CONFIG_IPV6_SIT=m CONFIG_IPV6_SIT_6RD=y CONFIG_IPV6_NDISC_NODETYPE=y CONFIG_IPV6_TUNNEL=m CONFIG_IPV6_MULTIPLE_TABLES=y CONFIG_IPV6_SUBTREES=y CONFIG_IPV6_MROUTE=y CONFIG_IPV6_PIMSM_V2=y # CONFIG_NETWORK_SECMARK is not set # CONFIG_NETFILTER is not set # CONFIG_IP_DCCP is not set # CONFIG_IP_SCTP is not set # CONFIG_RDS is not set # CONFIG_TIPC is not set # CONFIG_ATM is not set CONFIG_STP=m CONFIG_GARP=m CONFIG_BRIDGE=m # CONFIG_NET_DSA is not set CONFIG_VLAN_8021Q=m CONFIG_VLAN_8021Q_GVRP=y # CONFIG_DECNET is not set CONFIG_LLC=m # CONFIG_LLC2 is not set # CONFIG_IPX is not set # CONFIG_ATALK is not set # CONFIG_X25 is not set # CONFIG_LAPB is not set # CONFIG_ECONET is not set # CONFIG_WAN_ROUTER is not set # CONFIG_PHONET is not set # CONFIG_IEEE802154 is not set # CONFIG_NET_SCHED is not set # CONFIG_DCB is not set # # Network testing # # CONFIG_NET_PKTGEN is not set # CONFIG_HAMRADIO is not set # CONFIG_CAN is not set # CONFIG_IRDA is not set # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set CONFIG_FIB_RULES=y # CONFIG_WIRELESS is not set # CONFIG_WIMAX is not set # CONFIG_RFKILL is not set # CONFIG_NET_9P is not set # # Device Drivers # # # Generic Driver Options # CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_STANDALONE=y CONFIG_PREVENT_FIRMWARE_BUILD=y CONFIG_FW_LOADER=y CONFIG_FIRMWARE_IN_KERNEL=y CONFIG_EXTRA_FIRMWARE="" # CONFIG_SYS_HYPERVISOR is not set CONFIG_CONNECTOR=m CONFIG_MTD=y CONFIG_MTD_DEBUG=y CONFIG_MTD_DEBUG_VERBOSE=0 CONFIG_MTD_TESTS=m CONFIG_MTD_CONCAT=m CONFIG_MTD_PARTITIONS=y CONFIG_MTD_REDBOOT_PARTS=m CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1 CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED=y CONFIG_MTD_REDBOOT_PARTS_READONLY=y # CONFIG_MTD_CMDLINE_PARTS is not set CONFIG_MTD_AR7_PARTS=m # # User Modules And Translation Layers # CONFIG_MTD_CHAR=m CONFIG_HAVE_MTD_OTP=y CONFIG_MTD_BLKDEVS=m CONFIG_MTD_BLOCK=m CONFIG_MTD_BLOCK_RO=m CONFIG_FTL=m CONFIG_NFTL=m CONFIG_NFTL_RW=y CONFIG_INFTL=m CONFIG_RFD_FTL=m CONFIG_SSFDC=m CONFIG_MTD_OOPS=m # # RAM/ROM/Flash chip drivers # CONFIG_MTD_CFI=m CONFIG_MTD_JEDECPROBE=m CONFIG_MTD_GEN_PROBE=m CONFIG_MTD_CFI_ADV_OPTIONS=y CONFIG_MTD_CFI_NOSWAP=y # CONFIG_MTD_CFI_BE_BYTE_SWAP is not set # CONFIG_MTD_CFI_LE_BYTE_SWAP is not set CONFIG_MTD_CFI_GEOMETRY=y CONFIG_MTD_MAP_BANK_WIDTH_1=y CONFIG_MTD_MAP_BANK_WIDTH_2=y CONFIG_MTD_MAP_BANK_WIDTH_4=y CONFIG_MTD_MAP_BANK_WIDTH_8=y CONFIG_MTD_MAP_BANK_WIDTH_16=y CONFIG_MTD_MAP_BANK_WIDTH_32=y CONFIG_MTD_CFI_I1=y CONFIG_MTD_CFI_I2=y CONFIG_MTD_CFI_I4=y CONFIG_MTD_CFI_I8=y CONFIG_MTD_OTP=y CONFIG_MTD_CFI_INTELEXT=m CONFIG_MTD_CFI_AMDSTD=m CONFIG_MTD_CFI_STAA=m CONFIG_MTD_CFI_UTIL=m CONFIG_MTD_RAM=m CONFIG_MTD_ROM=m CONFIG_MTD_ABSENT=m # # Mapping drivers for chip access # CONFIG_MTD_COMPLEX_MAPPINGS=y CONFIG_MTD_PHYSMAP=m CONFIG_MTD_PHYSMAP_COMPAT=y CONFIG_MTD_PHYSMAP_START=0x8000000 CONFIG_MTD_PHYSMAP_LEN=0 CONFIG_MTD_PHYSMAP_BANKWIDTH=2 CONFIG_MTD_PCI=m CONFIG_MTD_INTEL_VR_NOR=m CONFIG_MTD_PLATRAM=m # # Self-contained MTD device drivers # CONFIG_MTD_PMC551=m CONFIG_MTD_PMC551_BUGFIX=y CONFIG_MTD_PMC551_DEBUG=y CONFIG_MTD_SLRAM=m CONFIG_MTD_PHRAM=m CONFIG_MTD_MTDRAM=m CONFIG_MTDRAM_TOTAL_SIZE=4096 CONFIG_MTDRAM_ERASE_SIZE=128 CONFIG_MTD_BLOCK2MTD=m # # Disk-On-Chip Device Drivers # CONFIG_MTD_DOC2000=m CONFIG_MTD_DOC2001=m CONFIG_MTD_DOC2001PLUS=m CONFIG_MTD_DOCPROBE=m CONFIG_MTD_DOCECC=m CONFIG_MTD_DOCPROBE_ADVANCED=y CONFIG_MTD_DOCPROBE_ADDRESS=0x0000 CONFIG_MTD_DOCPROBE_HIGH=y CONFIG_MTD_DOCPROBE_55AA=y CONFIG_MTD_NAND=m CONFIG_MTD_NAND_VERIFY_WRITE=y CONFIG_MTD_NAND_ECC_SMC=y CONFIG_MTD_NAND_MUSEUM_IDS=y CONFIG_MTD_NAND_IDS=m CONFIG_MTD_NAND_DISKONCHIP=m CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADVANCED=y CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADDRESS=0 CONFIG_MTD_NAND_DISKONCHIP_PROBE_HIGH=y CONFIG_MTD_NAND_DISKONCHIP_BBTWRITE=y CONFIG_MTD_NAND_CAFE=m CONFIG_MTD_NAND_NANDSIM=m CONFIG_MTD_NAND_PLATFORM=m # CONFIG_MTD_ALAUDA is not set CONFIG_MTD_ONENAND=m CONFIG_MTD_ONENAND_VERIFY_WRITE=y CONFIG_MTD_ONENAND_GENERIC=m CONFIG_MTD_ONENAND_OTP=y CONFIG_MTD_ONENAND_2X_PROGRAM=y CONFIG_MTD_ONENAND_SIM=m # # LPDDR flash memory drivers # CONFIG_MTD_LPDDR=m CONFIG_MTD_QINFO_PROBE=m # # UBI - Unsorted block images # CONFIG_MTD_UBI=m CONFIG_MTD_UBI_WL_THRESHOLD=4096 CONFIG_MTD_UBI_BEB_RESERVE=1 CONFIG_MTD_UBI_GLUEBI=m # # UBI debugging options # CONFIG_MTD_UBI_DEBUG=y CONFIG_MTD_UBI_DEBUG_MSG=y CONFIG_MTD_UBI_DEBUG_PARANOID=y CONFIG_MTD_UBI_DEBUG_DISABLE_BGT=y CONFIG_MTD_UBI_DEBUG_EMULATE_BITFLIPS=y CONFIG_MTD_UBI_DEBUG_EMULATE_WRITE_FAILURES=y CONFIG_MTD_UBI_DEBUG_EMULATE_ERASE_FAILURES=y # # Additional UBI debugging messages # CONFIG_MTD_UBI_DEBUG_MSG_BLD=y CONFIG_MTD_UBI_DEBUG_MSG_EBA=y CONFIG_MTD_UBI_DEBUG_MSG_WL=y CONFIG_MTD_UBI_DEBUG_MSG_IO=y # CONFIG_PARPORT is not set CONFIG_BLK_DEV=y # CONFIG_BLK_CPQ_DA is not set # CONFIG_BLK_CPQ_CISS_DA is not set # CONFIG_BLK_DEV_DAC960 is not set # CONFIG_BLK_DEV_UMEM is not set # CONFIG_BLK_DEV_COW_COMMON is not set # CONFIG_BLK_DEV_LOOP is not set # CONFIG_BLK_DEV_DRBD is not set # CONFIG_BLK_DEV_NBD is not set # CONFIG_BLK_DEV_SX8 is not set # CONFIG_BLK_DEV_UB is not set # CONFIG_BLK_DEV_RAM is not set # CONFIG_CDROM_PKTCDVD is not set # CONFIG_ATA_OVER_ETH is not set # CONFIG_BLK_DEV_HD is not set CONFIG_MISC_DEVICES=y # CONFIG_AD525X_DPOT is not set # CONFIG_PHANTOM is not set # CONFIG_SGI_IOC4 is not set CONFIG_TIFM_CORE=m CONFIG_TIFM_7XX1=m # CONFIG_ICS932S401 is not set # CONFIG_ENCLOSURE_SERVICES is not set # CONFIG_HP_ILO is not set # CONFIG_ISL29003 is not set # CONFIG_DS1682 is not set # CONFIG_C2PORT is not set # # EEPROM support # # CONFIG_EEPROM_AT24 is not set # CONFIG_EEPROM_LEGACY is not set # CONFIG_EEPROM_MAX6875 is not set # CONFIG_EEPROM_93CX6 is not set CONFIG_CB710_CORE=m # CONFIG_CB710_DEBUG is not set CONFIG_CB710_DEBUG_ASSUMPTIONS=y # CONFIG_IWMC3200TOP is not set CONFIG_HAVE_IDE=y # CONFIG_IDE is not set # # SCSI device support # # CONFIG_RAID_ATTRS is not set CONFIG_SCSI=y CONFIG_SCSI_DMA=y # CONFIG_SCSI_TGT is not set # CONFIG_SCSI_NETLINK is not set CONFIG_SCSI_PROC_FS=y # # SCSI support type (disk, tape, CD-ROM) # # CONFIG_BLK_DEV_SD is not set # CONFIG_CHR_DEV_ST is not set # CONFIG_CHR_DEV_OSST is not set # CONFIG_BLK_DEV_SR is not set # CONFIG_CHR_DEV_SG is not set # CONFIG_CHR_DEV_SCH is not set # CONFIG_SCSI_MULTI_LUN is not set # CONFIG_SCSI_CONSTANTS is not set # CONFIG_SCSI_LOGGING is not set # CONFIG_SCSI_SCAN_ASYNC is not set CONFIG_SCSI_WAIT_SCAN=m # # SCSI Transports # # CONFIG_SCSI_SPI_ATTRS is not set # CONFIG_SCSI_FC_ATTRS is not set # CONFIG_SCSI_ISCSI_ATTRS is not set CONFIG_SCSI_SAS_ATTRS=y # CONFIG_SCSI_SAS_LIBSAS is not set # CONFIG_SCSI_SRP_ATTRS is not set CONFIG_SCSI_LOWLEVEL=y # CONFIG_ISCSI_TCP is not set # CONFIG_SCSI_BNX2_ISCSI is not set # CONFIG_BE2ISCSI is not set # CONFIG_BLK_DEV_3W_XXXX_RAID is not set # CONFIG_SCSI_HPSA is not set # CONFIG_SCSI_3W_9XXX is not set # CONFIG_SCSI_3W_SAS is not set # CONFIG_SCSI_ACARD is not set # CONFIG_SCSI_AACRAID is not set # CONFIG_SCSI_AIC7XXX is not set # CONFIG_SCSI_AIC7XXX_OLD is not set # CONFIG_SCSI_AIC79XX is not set # CONFIG_SCSI_AIC94XX is not set # CONFIG_SCSI_MVSAS is not set # CONFIG_SCSI_DPT_I2O is not set # CONFIG_SCSI_ADVANSYS is not set # CONFIG_SCSI_ARCMSR is not set # CONFIG_MEGARAID_NEWGEN is not set # CONFIG_MEGARAID_LEGACY is not set # CONFIG_MEGARAID_SAS is not set # CONFIG_SCSI_MPT2SAS is not set # CONFIG_SCSI_HPTIOP is not set # CONFIG_LIBFC is not set # CONFIG_LIBFCOE is not set # CONFIG_FCOE is not set # CONFIG_SCSI_DMX3191D is not set # CONFIG_SCSI_FUTURE_DOMAIN is not set # CONFIG_SCSI_IPS is not set # CONFIG_SCSI_INITIO is not set # CONFIG_SCSI_INIA100 is not set # CONFIG_SCSI_STEX is not set # CONFIG_SCSI_SYM53C8XX_2 is not set # CONFIG_SCSI_IPR is not set # CONFIG_SCSI_QLOGIC_1280 is not set # CONFIG_SCSI_QLA_FC is not set # CONFIG_SCSI_QLA_ISCSI is not set # CONFIG_SCSI_LPFC is not set # CONFIG_SCSI_DC395x is not set # CONFIG_SCSI_DC390T is not set # CONFIG_SCSI_DEBUG is not set # CONFIG_SCSI_PMCRAID is not set # CONFIG_SCSI_PM8001 is not set # CONFIG_SCSI_SRP is not set # CONFIG_SCSI_BFA_FC is not set # CONFIG_SCSI_DH is not set # CONFIG_SCSI_OSD_INITIATOR is not set CONFIG_ATA=y # CONFIG_ATA_NONSTANDARD is not set CONFIG_ATA_VERBOSE_ERROR=y CONFIG_SATA_PMP=y # CONFIG_SATA_AHCI is not set # CONFIG_SATA_SIL24 is not set CONFIG_ATA_SFF=y CONFIG_SATA_SVW=m CONFIG_ATA_PIIX=m CONFIG_SATA_MV=m CONFIG_SATA_NV=m CONFIG_PDC_ADMA=m CONFIG_SATA_QSTOR=m CONFIG_SATA_PROMISE=m CONFIG_SATA_SX4=m CONFIG_SATA_SIL=m CONFIG_SATA_SIS=m CONFIG_SATA_ULI=m CONFIG_SATA_VIA=m CONFIG_SATA_VITESSE=m CONFIG_SATA_INIC162X=m # CONFIG_PATA_ALI is not set # CONFIG_PATA_AMD is not set # CONFIG_PATA_ARTOP is not set # CONFIG_PATA_ATP867X is not set # CONFIG_PATA_ATIIXP is not set # CONFIG_PATA_CMD640_PCI is not set # CONFIG_PATA_CMD64X is not set # CONFIG_PATA_CS5520 is not set # CONFIG_PATA_CS5530 is not set # CONFIG_PATA_CYPRESS is not set # CONFIG_PATA_EFAR is not set CONFIG_ATA_GENERIC=y # CONFIG_PATA_HPT366 is not set # CONFIG_PATA_HPT37X is not set # CONFIG_PATA_HPT3X2N is not set # CONFIG_PATA_HPT3X3 is not set # CONFIG_PATA_IT821X is not set # CONFIG_PATA_IT8213 is not set # CONFIG_PATA_JMICRON is not set # CONFIG_PATA_TRIFLEX is not set # CONFIG_PATA_MARVELL is not set # CONFIG_PATA_MPIIX is not set # CONFIG_PATA_OLDPIIX is not set # CONFIG_PATA_NETCELL is not set # CONFIG_PATA_NINJA32 is not set # CONFIG_PATA_NS87410 is not set # CONFIG_PATA_NS87415 is not set # CONFIG_PATA_OPTI is not set # CONFIG_PATA_OPTIDMA is not set # CONFIG_PATA_PDC2027X is not set # CONFIG_PATA_PDC_OLD is not set # CONFIG_PATA_RADISYS is not set # CONFIG_PATA_RDC is not set # CONFIG_PATA_RZ1000 is not set # CONFIG_PATA_SC1200 is not set # CONFIG_PATA_SERVERWORKS is not set # CONFIG_PATA_SIL680 is not set CONFIG_PATA_SIS=m # CONFIG_PATA_TOSHIBA is not set # CONFIG_PATA_VIA is not set # CONFIG_PATA_WINBOND is not set # CONFIG_PATA_PLATFORM is not set CONFIG_PATA_OCTEON_CF=y # CONFIG_PATA_SCH is not set CONFIG_MD=y CONFIG_BLK_DEV_MD=m CONFIG_MD_LINEAR=m CONFIG_MD_RAID0=m CONFIG_MD_RAID1=m CONFIG_MD_RAID10=m CONFIG_MD_RAID456=m CONFIG_MULTICORE_RAID456=y CONFIG_MD_RAID6_PQ=m CONFIG_ASYNC_RAID6_TEST=m CONFIG_MD_MULTIPATH=m CONFIG_MD_FAULTY=m CONFIG_BLK_DEV_DM=m CONFIG_DM_DEBUG=y CONFIG_DM_CRYPT=m CONFIG_DM_SNAPSHOT=m CONFIG_DM_MIRROR=m CONFIG_DM_LOG_USERSPACE=m CONFIG_DM_ZERO=m CONFIG_DM_MULTIPATH=m CONFIG_DM_MULTIPATH_QL=m CONFIG_DM_MULTIPATH_ST=m CONFIG_DM_DELAY=m CONFIG_DM_UEVENT=y CONFIG_FUSION=y # CONFIG_FUSION_SPI is not set # CONFIG_FUSION_FC is not set CONFIG_FUSION_SAS=y CONFIG_FUSION_MAX_SGE=128 CONFIG_FUSION_CTL=m CONFIG_FUSION_LOGGING=y # # IEEE 1394 (FireWire) support # # # You can enable one or both FireWire driver stacks. # # # The newer stack is recommended. # # CONFIG_FIREWIRE is not set # CONFIG_IEEE1394 is not set CONFIG_I2O=y CONFIG_I2O_LCT_NOTIFY_ON_CHANGES=y CONFIG_I2O_EXT_ADAPTEC=y CONFIG_I2O_EXT_ADAPTEC_DMA64=y # CONFIG_I2O_CONFIG is not set # CONFIG_I2O_BUS is not set # CONFIG_I2O_BLOCK is not set # CONFIG_I2O_SCSI is not set # CONFIG_I2O_PROC is not set CONFIG_NETDEVICES=y # CONFIG_DUMMY is not set CONFIG_BONDING=m # CONFIG_MACVLAN is not set # CONFIG_EQUALIZER is not set CONFIG_TUN=m # CONFIG_VETH is not set # CONFIG_ARCNET is not set CONFIG_PHYLIB=y # # MII PHY device drivers # # CONFIG_MARVELL_PHY is not set # CONFIG_DAVICOM_PHY is not set # CONFIG_QSEMI_PHY is not set # CONFIG_LXT_PHY is not set # CONFIG_CICADA_PHY is not set # CONFIG_VITESSE_PHY is not set # CONFIG_SMSC_PHY is not set # CONFIG_BROADCOM_PHY is not set # CONFIG_ICPLUS_PHY is not set # CONFIG_REALTEK_PHY is not set # CONFIG_NATIONAL_PHY is not set # CONFIG_STE10XP is not set # CONFIG_LSI_ET1011C_PHY is not set # CONFIG_FIXED_PHY is not set # CONFIG_MDIO_BITBANG is not set CONFIG_MDIO_OCTEON=y CONFIG_NET_ETHERNET=y CONFIG_MII=m # CONFIG_AX88796 is not set # CONFIG_HAPPYMEAL is not set # CONFIG_SUNGEM is not set # CONFIG_CASSINI is not set # CONFIG_NET_VENDOR_3COM is not set # CONFIG_SMC91X is not set # CONFIG_DM9000 is not set CONFIG_ETHOC=m # CONFIG_SMSC911X is not set # CONFIG_DNET is not set # CONFIG_NET_TULIP is not set # CONFIG_HP100 is not set # CONFIG_IBM_NEW_EMAC_ZMII is not set # CONFIG_IBM_NEW_EMAC_RGMII is not set # CONFIG_IBM_NEW_EMAC_TAH is not set # CONFIG_IBM_NEW_EMAC_EMAC4 is not set # CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set # CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set # CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set # CONFIG_NET_PCI is not set # CONFIG_B44 is not set # CONFIG_KS8842 is not set # CONFIG_KS8851_MLL is not set # CONFIG_ATL2 is not set CONFIG_OCTEON_MGMT_ETHERNET=y # CONFIG_NETDEV_1000 is not set # CONFIG_NETDEV_10000 is not set # CONFIG_TR is not set # CONFIG_WLAN is not set # # Enable WiMAX (Networking options) to see the WiMAX drivers # # # USB Network Adapters # # CONFIG_USB_CATC is not set # CONFIG_USB_KAWETH is not set # CONFIG_USB_PEGASUS is not set # CONFIG_USB_RTL8150 is not set # CONFIG_USB_USBNET is not set # CONFIG_WAN is not set # CONFIG_FDDI is not set # CONFIG_HIPPI is not set # CONFIG_PPP is not set # CONFIG_SLIP is not set # CONFIG_NET_FC is not set # CONFIG_NETCONSOLE is not set # CONFIG_NETPOLL is not set # CONFIG_NET_POLL_CONTROLLER is not set # CONFIG_VMXNET3 is not set # CONFIG_ISDN is not set # CONFIG_PHONE is not set # # Input device support # CONFIG_INPUT=y # CONFIG_INPUT_FF_MEMLESS is not set # CONFIG_INPUT_POLLDEV is not set # CONFIG_INPUT_SPARSEKMAP is not set # # Userland interfaces # # CONFIG_INPUT_MOUSEDEV is not set # CONFIG_INPUT_JOYDEV is not set CONFIG_INPUT_EVDEV=y CONFIG_INPUT_EVBUG=y # # Input Device Drivers # CONFIG_INPUT_KEYBOARD=y # CONFIG_KEYBOARD_ADP5588 is not set CONFIG_KEYBOARD_ATKBD=y # CONFIG_QT2160 is not set # CONFIG_KEYBOARD_LKKBD is not set # CONFIG_KEYBOARD_MAX7359 is not set # CONFIG_KEYBOARD_NEWTON is not set # CONFIG_KEYBOARD_OPENCORES is not set # CONFIG_KEYBOARD_STOWAWAY is not set # CONFIG_KEYBOARD_SUNKBD is not set # CONFIG_KEYBOARD_XTKBD is not set # CONFIG_INPUT_MOUSE is not set # CONFIG_INPUT_JOYSTICK is not set # CONFIG_INPUT_TABLET is not set # CONFIG_INPUT_TOUCHSCREEN is not set CONFIG_INPUT_MISC=y # CONFIG_INPUT_PCSPKR is not set # CONFIG_INPUT_ATI_REMOTE is not set # CONFIG_INPUT_ATI_REMOTE2 is not set # CONFIG_INPUT_KEYSPAN_REMOTE is not set # CONFIG_INPUT_POWERMATE is not set # CONFIG_INPUT_YEALINK is not set # CONFIG_INPUT_CM109 is not set # CONFIG_INPUT_UINPUT is not set # # Hardware I/O ports # CONFIG_SERIO=y CONFIG_SERIO_I8042=y CONFIG_SERIO_SERPORT=y # CONFIG_SERIO_PCIPS2 is not set CONFIG_SERIO_LIBPS2=y # CONFIG_SERIO_RAW is not set # CONFIG_SERIO_ALTERA_PS2 is not set # CONFIG_GAMEPORT is not set # # Character devices # CONFIG_VT=y CONFIG_CONSOLE_TRANSLATIONS=y CONFIG_VT_CONSOLE=y CONFIG_HW_CONSOLE=y # CONFIG_VT_HW_CONSOLE_BINDING is not set CONFIG_DEVKMEM=y # CONFIG_SERIAL_NONSTANDARD is not set # CONFIG_NOZOMI is not set # # Serial drivers # CONFIG_SERIAL_8250=y CONFIG_SERIAL_8250_CONSOLE=y CONFIG_SERIAL_8250_PCI=y CONFIG_SERIAL_8250_NR_UARTS=4 CONFIG_SERIAL_8250_RUNTIME_UARTS=4 # CONFIG_SERIAL_8250_EXTENDED is not set # # Non-8250 serial port support # CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y # CONFIG_SERIAL_JSM is not set CONFIG_UNIX98_PTYS=y # CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=256 # CONFIG_IPMI_HANDLER is not set CONFIG_HW_RANDOM=m # CONFIG_HW_RANDOM_TIMERIOMEM is not set CONFIG_HW_RANDOM_OCTEON=m # CONFIG_R3964 is not set # CONFIG_APPLICOM is not set # CONFIG_RAW_DRIVER is not set # CONFIG_TCG_TPM is not set CONFIG_DEVPORT=y CONFIG_I2C=y CONFIG_I2C_BOARDINFO=y CONFIG_I2C_COMPAT=y CONFIG_I2C_CHARDEV=m CONFIG_I2C_HELPER_AUTO=y # # I2C Hardware Bus support # # # PC SMBus host controller drivers # # CONFIG_I2C_ALI1535 is not set # CONFIG_I2C_ALI1563 is not set # CONFIG_I2C_ALI15X3 is not set # CONFIG_I2C_AMD756 is not set # CONFIG_I2C_AMD8111 is not set # CONFIG_I2C_I801 is not set # CONFIG_I2C_ISCH is not set # CONFIG_I2C_PIIX4 is not set # CONFIG_I2C_NFORCE2 is not set # CONFIG_I2C_SIS5595 is not set # CONFIG_I2C_SIS630 is not set # CONFIG_I2C_SIS96X is not set # CONFIG_I2C_VIA is not set # CONFIG_I2C_VIAPRO is not set # # I2C system bus drivers (mostly embedded / system-on-chip) # CONFIG_I2C_OCORES=m # CONFIG_I2C_SIMTEC is not set # # External I2C/SMBus adapter drivers # # CONFIG_I2C_PARPORT_LIGHT is not set # CONFIG_I2C_TAOS_EVM is not set # CONFIG_I2C_TINY_USB is not set # # Other I2C/SMBus bus drivers # # CONFIG_I2C_PCA_PLATFORM is not set # CONFIG_I2C_STUB is not set # # Miscellaneous I2C Chip support # CONFIG_SENSORS_TSL2550=m # CONFIG_I2C_DEBUG_CORE is not set # CONFIG_I2C_DEBUG_ALGO is not set # CONFIG_I2C_DEBUG_BUS is not set # CONFIG_I2C_DEBUG_CHIP is not set # CONFIG_SPI is not set # # PPS support # # CONFIG_PPS is not set # CONFIG_W1 is not set # CONFIG_POWER_SUPPLY is not set CONFIG_HWMON=y # CONFIG_HWMON_VID is not set # CONFIG_HWMON_DEBUG_CHIP is not set # # Native drivers # # CONFIG_SENSORS_AD7414 is not set # CONFIG_SENSORS_AD7418 is not set # CONFIG_SENSORS_ADM1021 is not set # CONFIG_SENSORS_ADM1025 is not set # CONFIG_SENSORS_ADM1026 is not set # CONFIG_SENSORS_ADM1029 is not set # CONFIG_SENSORS_ADM1031 is not set # CONFIG_SENSORS_ADM9240 is not set # CONFIG_SENSORS_ADT7462 is not set # CONFIG_SENSORS_ADT7470 is not set # CONFIG_SENSORS_ADT7473 is not set # CONFIG_SENSORS_ADT7475 is not set # CONFIG_SENSORS_ATXP1 is not set # CONFIG_SENSORS_DS1621 is not set # CONFIG_SENSORS_I5K_AMB is not set # CONFIG_SENSORS_F71805F is not set # CONFIG_SENSORS_F71882FG is not set # CONFIG_SENSORS_F75375S is not set # CONFIG_SENSORS_G760A is not set # CONFIG_SENSORS_GL518SM is not set # CONFIG_SENSORS_GL520SM is not set # CONFIG_SENSORS_IT87 is not set # CONFIG_SENSORS_LM63 is not set # CONFIG_SENSORS_LM73 is not set # CONFIG_SENSORS_LM75 is not set # CONFIG_SENSORS_LM77 is not set # CONFIG_SENSORS_LM78 is not set # CONFIG_SENSORS_LM80 is not set # CONFIG_SENSORS_LM83 is not set # CONFIG_SENSORS_LM85 is not set # CONFIG_SENSORS_LM87 is not set # CONFIG_SENSORS_LM90 is not set # CONFIG_SENSORS_LM92 is not set # CONFIG_SENSORS_LM93 is not set # CONFIG_SENSORS_LTC4215 is not set # CONFIG_SENSORS_LTC4245 is not set # CONFIG_SENSORS_LM95241 is not set # CONFIG_SENSORS_MAX1619 is not set # CONFIG_SENSORS_MAX6650 is not set # CONFIG_SENSORS_PC87360 is not set # CONFIG_SENSORS_PC87427 is not set # CONFIG_SENSORS_PCF8591 is not set # CONFIG_SENSORS_SIS5595 is not set # CONFIG_SENSORS_DME1737 is not set # CONFIG_SENSORS_SMSC47M1 is not set # CONFIG_SENSORS_SMSC47M192 is not set # CONFIG_SENSORS_SMSC47B397 is not set # CONFIG_SENSORS_ADS7828 is not set # CONFIG_SENSORS_AMC6821 is not set # CONFIG_SENSORS_THMC50 is not set # CONFIG_SENSORS_TMP401 is not set # CONFIG_SENSORS_TMP421 is not set # CONFIG_SENSORS_VIA686A is not set # CONFIG_SENSORS_VT1211 is not set # CONFIG_SENSORS_VT8231 is not set # CONFIG_SENSORS_W83781D is not set # CONFIG_SENSORS_W83791D is not set # CONFIG_SENSORS_W83792D is not set # CONFIG_SENSORS_W83793 is not set # CONFIG_SENSORS_W83L785TS is not set # CONFIG_SENSORS_W83L786NG is not set # CONFIG_SENSORS_W83627HF is not set # CONFIG_SENSORS_W83627EHF is not set # CONFIG_SENSORS_LIS3_I2C is not set # CONFIG_THERMAL is not set CONFIG_WATCHDOG=y # CONFIG_WATCHDOG_NOWAYOUT is not set # # Watchdog Device Drivers # # CONFIG_SOFT_WATCHDOG is not set # CONFIG_ALIM7101_WDT is not set # # PCI-based Watchdog Cards # # CONFIG_PCIPCWATCHDOG is not set # CONFIG_WDTPCI is not set # # USB-based Watchdog Cards # # CONFIG_USBPCWATCHDOG is not set CONFIG_SSB_POSSIBLE=y # # Sonics Silicon Backplane # # CONFIG_SSB is not set # # Multifunction device drivers # # CONFIG_MFD_CORE is not set # CONFIG_MFD_SM501 is not set # CONFIG_HTC_PASIC3 is not set # CONFIG_TWL4030_CORE is not set # CONFIG_MFD_TMIO is not set # CONFIG_PMIC_DA903X is not set # CONFIG_PMIC_ADP5520 is not set # CONFIG_MFD_WM8400 is not set # CONFIG_MFD_WM831X is not set # CONFIG_MFD_WM8350_I2C is not set # CONFIG_MFD_PCF50633 is not set # CONFIG_AB3100_CORE is not set # CONFIG_MFD_88PM8607 is not set # CONFIG_REGULATOR is not set CONFIG_MEDIA_SUPPORT=y # # Multimedia core support # # CONFIG_VIDEO_DEV is not set # CONFIG_DVB_CORE is not set # CONFIG_VIDEO_MEDIA is not set # # Multimedia drivers # CONFIG_IR_CORE=y CONFIG_VIDEO_IR=y # CONFIG_DAB is not set # # Graphics support # CONFIG_VGA_ARB=y # CONFIG_DRM is not set # CONFIG_VGASTATE is not set # CONFIG_VIDEO_OUTPUT_CONTROL is not set # CONFIG_FB is not set # CONFIG_BACKLIGHT_LCD_SUPPORT is not set # # Display device support # # CONFIG_DISPLAY_SUPPORT is not set # # Console display driver support # CONFIG_VGA_CONSOLE=y # CONFIG_VGACON_SOFT_SCROLLBACK is not set CONFIG_DUMMY_CONSOLE=y # CONFIG_SOUND is not set CONFIG_HID_SUPPORT=y CONFIG_HID=y # CONFIG_HIDRAW is not set # # USB Input Devices # CONFIG_USB_HID=m # CONFIG_HID_PID is not set # CONFIG_USB_HIDDEV is not set # # USB HID Boot Protocol drivers # # CONFIG_USB_KBD is not set # CONFIG_USB_MOUSE is not set # # Special HID drivers # # CONFIG_HID_A4TECH is not set # CONFIG_HID_APPLE is not set # CONFIG_HID_BELKIN is not set # CONFIG_HID_CHERRY is not set # CONFIG_HID_CHICONY is not set # CONFIG_HID_CYPRESS is not set # CONFIG_HID_DRAGONRISE is not set # CONFIG_HID_EZKEY is not set # CONFIG_HID_KYE is not set # CONFIG_HID_GYRATION is not set # CONFIG_HID_TWINHAN is not set # CONFIG_HID_KENSINGTON is not set # CONFIG_HID_LOGITECH is not set # CONFIG_HID_MICROSOFT is not set # CONFIG_HID_MONTEREY is not set # CONFIG_HID_NTRIG is not set # CONFIG_HID_PANTHERLORD is not set # CONFIG_HID_PETALYNX is not set # CONFIG_HID_SAMSUNG is not set # CONFIG_HID_SONY is not set # CONFIG_HID_SUNPLUS is not set # CONFIG_HID_GREENASIA is not set # CONFIG_HID_SMARTJOYPLUS is not set # CONFIG_HID_TOPSEED is not set # CONFIG_HID_THRUSTMASTER is not set # CONFIG_HID_ZEROPLUS is not set CONFIG_USB_SUPPORT=y CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB_ARCH_HAS_OHCI=y CONFIG_USB_ARCH_HAS_EHCI=y CONFIG_USB=m # CONFIG_USB_DEBUG is not set # CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set # # Miscellaneous USB options # # CONFIG_USB_DEVICEFS is not set CONFIG_USB_DEVICE_CLASS=y # CONFIG_USB_DYNAMIC_MINORS is not set # CONFIG_USB_OTG is not set # CONFIG_USB_OTG_WHITELIST is not set # CONFIG_USB_OTG_BLACKLIST_HUB is not set CONFIG_USB_MON=m # CONFIG_USB_WUSB is not set # CONFIG_USB_WUSB_CBAF is not set # # USB Host Controller Drivers # # CONFIG_USB_C67X00_HCD is not set # CONFIG_USB_XHCI_HCD is not set # CONFIG_USB_EHCI_HCD is not set # CONFIG_USB_OXU210HP_HCD is not set # CONFIG_USB_ISP116X_HCD is not set # CONFIG_USB_ISP1760_HCD is not set # CONFIG_USB_ISP1362_HCD is not set CONFIG_USB_OHCI_HCD=m # CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set # CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set CONFIG_USB_OHCI_LITTLE_ENDIAN=y # CONFIG_USB_UHCI_HCD is not set # CONFIG_USB_SL811_HCD is not set # CONFIG_USB_R8A66597_HCD is not set # CONFIG_USB_WHCI_HCD is not set # CONFIG_USB_HWA_HCD is not set # # Enable Host or Gadget support to see Inventra options # # # USB Device Class drivers # # CONFIG_USB_ACM is not set # CONFIG_USB_PRINTER is not set # CONFIG_USB_WDM is not set # CONFIG_USB_TMC is not set # # NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may # # # also be needed; see USB_STORAGE Help for more info # CONFIG_USB_STORAGE=m # CONFIG_USB_STORAGE_DEBUG is not set # CONFIG_USB_STORAGE_DATAFAB is not set # CONFIG_USB_STORAGE_FREECOM is not set # CONFIG_USB_STORAGE_ISD200 is not set # CONFIG_USB_STORAGE_USBAT is not set # CONFIG_USB_STORAGE_SDDR09 is not set # CONFIG_USB_STORAGE_SDDR55 is not set # CONFIG_USB_STORAGE_JUMPSHOT is not set # CONFIG_USB_STORAGE_ALAUDA is not set # CONFIG_USB_STORAGE_ONETOUCH is not set # CONFIG_USB_STORAGE_KARMA is not set # CONFIG_USB_STORAGE_CYPRESS_ATACB is not set # CONFIG_USB_LIBUSUAL is not set # # USB Imaging devices # # CONFIG_USB_MDC800 is not set # CONFIG_USB_MICROTEK is not set # # USB port drivers # # CONFIG_USB_SERIAL is not set # # USB Miscellaneous drivers # # CONFIG_USB_EMI62 is not set # CONFIG_USB_EMI26 is not set # CONFIG_USB_ADUTUX is not set # CONFIG_USB_SEVSEG is not set # CONFIG_USB_RIO500 is not set # CONFIG_USB_LEGOTOWER is not set # CONFIG_USB_LCD is not set # CONFIG_USB_BERRY_CHARGE is not set # CONFIG_USB_LED is not set # CONFIG_USB_CYPRESS_CY7C63 is not set # CONFIG_USB_CYTHERM is not set # CONFIG_USB_IDMOUSE is not set # CONFIG_USB_FTDI_ELAN is not set # CONFIG_USB_APPLEDISPLAY is not set # CONFIG_USB_LD is not set # CONFIG_USB_TRANCEVIBRATOR is not set # CONFIG_USB_IOWARRIOR is not set # CONFIG_USB_TEST is not set # CONFIG_USB_ISIGHTFW is not set # CONFIG_USB_VST is not set # CONFIG_USB_GADGET is not set # # OTG and related infrastructure # # CONFIG_NOP_USB_XCEIV is not set # CONFIG_UWB is not set CONFIG_MMC=y CONFIG_MMC_DEBUG=y CONFIG_MMC_UNSAFE_RESUME=y # # MMC/SD/SDIO Card Drivers # CONFIG_MMC_BLOCK=y CONFIG_MMC_BLOCK_BOUNCE=y CONFIG_SDIO_UART=m CONFIG_MMC_TEST=m # # MMC/SD/SDIO Host Controller Drivers # CONFIG_MMC_SDHCI=m CONFIG_MMC_SDHCI_PCI=m CONFIG_MMC_RICOH_MMC=m CONFIG_MMC_SDHCI_PLTFM=m # CONFIG_MMC_AT91 is not set # CONFIG_MMC_ATMELMCI is not set CONFIG_MMC_TIFM_SD=m CONFIG_MMC_CB710=m CONFIG_MMC_VIA_SDMMC=m CONFIG_MEMSTICK=m # CONFIG_MEMSTICK_DEBUG is not set # # MemoryStick drivers # # CONFIG_MEMSTICK_UNSAFE_RESUME is not set # CONFIG_MSPRO_BLOCK is not set # # MemoryStick Host Controller Drivers # # CONFIG_MEMSTICK_TIFM_MS is not set # CONFIG_MEMSTICK_JMICRON_38X is not set # CONFIG_NEW_LEDS is not set # CONFIG_ACCESSIBILITY is not set # CONFIG_INFINIBAND is not set CONFIG_RTC_LIB=y # CONFIG_RTC_CLASS is not set # CONFIG_DMADEVICES is not set # CONFIG_AUXDISPLAY is not set # CONFIG_UIO is not set # # TI VLYNQ # CONFIG_STAGING=y # CONFIG_STAGING_EXCLUDE_BUILD is not set # CONFIG_USB_IP_COMMON is not set # CONFIG_ECHO is not set # CONFIG_COMEDI is not set # CONFIG_ASUS_OLED is not set # CONFIG_ALTERA_PCIE_CHDMA is not set # CONFIG_INPUT_MIMIO is not set # CONFIG_TRANZPORT is not set # # Qualcomm MSM Camera And Video # # # Camera Sensor Selection # # CONFIG_INPUT_GPIO is not set # CONFIG_POHMELFS is not set # CONFIG_B3DFG is not set # CONFIG_IDE_PHISON is not set # CONFIG_PLAN9AUTH is not set CONFIG_OCTEON_ETHERNET=y # CONFIG_VME_BUS is not set # # RAR Register Driver # # CONFIG_RAR_REGISTER is not set # CONFIG_IIO is not set # CONFIG_RAMZSWAP is not set # CONFIG_STRIP is not set # # File systems # CONFIG_EXT2_FS=y # CONFIG_EXT2_FS_XATTR is not set # CONFIG_EXT2_FS_XIP is not set CONFIG_EXT3_FS=y # CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set CONFIG_EXT3_FS_XATTR=y # CONFIG_EXT3_FS_POSIX_ACL is not set # CONFIG_EXT3_FS_SECURITY is not set CONFIG_EXT4_FS=m CONFIG_EXT4_FS_XATTR=y # CONFIG_EXT4_FS_POSIX_ACL is not set # CONFIG_EXT4_FS_SECURITY is not set # CONFIG_EXT4_DEBUG is not set CONFIG_JBD=y # CONFIG_JBD_DEBUG is not set CONFIG_JBD2=m # CONFIG_JBD2_DEBUG is not set CONFIG_FS_MBCACHE=y # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set CONFIG_FS_POSIX_ACL=y # CONFIG_XFS_FS is not set # CONFIG_GFS2_FS is not set # CONFIG_OCFS2_FS is not set # CONFIG_BTRFS_FS is not set # CONFIG_NILFS2_FS is not set CONFIG_FILE_LOCKING=y CONFIG_FSNOTIFY=y CONFIG_DNOTIFY=y CONFIG_INOTIFY=y CONFIG_INOTIFY_USER=y # CONFIG_QUOTA is not set # CONFIG_AUTOFS_FS is not set # CONFIG_AUTOFS4_FS is not set CONFIG_FUSE_FS=m CONFIG_CUSE=m # # Caches # CONFIG_FSCACHE=m # CONFIG_FSCACHE_STATS is not set # CONFIG_FSCACHE_HISTOGRAM is not set # CONFIG_FSCACHE_DEBUG is not set # CONFIG_FSCACHE_OBJECT_LIST is not set CONFIG_CACHEFILES=m # CONFIG_CACHEFILES_DEBUG is not set # CONFIG_CACHEFILES_HISTOGRAM is not set # # CD-ROM/DVD Filesystems # # CONFIG_ISO9660_FS is not set # CONFIG_UDF_FS is not set # # DOS/FAT/NT Filesystems # # CONFIG_MSDOS_FS is not set # CONFIG_VFAT_FS is not set # CONFIG_NTFS_FS is not set # # Pseudo filesystems # CONFIG_PROC_FS=y # CONFIG_PROC_KCORE is not set CONFIG_PROC_SYSCTL=y CONFIG_PROC_PAGE_MONITOR=y CONFIG_SYSFS=y # CONFIG_TMPFS is not set # CONFIG_HUGETLBFS is not set # CONFIG_HUGETLB_PAGE is not set # CONFIG_CONFIGFS_FS is not set CONFIG_MISC_FILESYSTEMS=y # CONFIG_ADFS_FS is not set # CONFIG_AFFS_FS is not set # CONFIG_HFS_FS is not set # CONFIG_HFSPLUS_FS is not set # CONFIG_BEFS_FS is not set # CONFIG_BFS_FS is not set # CONFIG_EFS_FS is not set CONFIG_JFFS2_FS=m CONFIG_JFFS2_FS_DEBUG=0 CONFIG_JFFS2_FS_WRITEBUFFER=y # CONFIG_JFFS2_FS_WBUF_VERIFY is not set CONFIG_JFFS2_SUMMARY=y CONFIG_JFFS2_FS_XATTR=y CONFIG_JFFS2_FS_POSIX_ACL=y CONFIG_JFFS2_FS_SECURITY=y CONFIG_JFFS2_COMPRESSION_OPTIONS=y CONFIG_JFFS2_ZLIB=y # CONFIG_JFFS2_LZO is not set CONFIG_JFFS2_RTIME=y # CONFIG_JFFS2_RUBIN is not set # CONFIG_JFFS2_CMODE_NONE is not set CONFIG_JFFS2_CMODE_PRIORITY=y # CONFIG_JFFS2_CMODE_SIZE is not set # CONFIG_JFFS2_CMODE_FAVOURLZO is not set # CONFIG_UBIFS_FS is not set # CONFIG_CRAMFS is not set CONFIG_SQUASHFS=y CONFIG_SQUASHFS_EMBEDDED=y CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 # CONFIG_VXFS_FS is not set CONFIG_MINIX_FS=y # CONFIG_OMFS_FS is not set # CONFIG_HPFS_FS is not set # CONFIG_QNX4FS_FS is not set # CONFIG_ROMFS_FS is not set # CONFIG_SYSV_FS is not set # CONFIG_UFS_FS is not set CONFIG_NETWORK_FILESYSTEMS=y # CONFIG_NFS_FS is not set # CONFIG_NFSD is not set # CONFIG_SMB_FS is not set # CONFIG_CIFS is not set # CONFIG_NCP_FS is not set # CONFIG_CODA_FS is not set # CONFIG_AFS_FS is not set # # Partition Types # CONFIG_PARTITION_ADVANCED=y # CONFIG_ACORN_PARTITION is not set # CONFIG_OSF_PARTITION is not set # CONFIG_AMIGA_PARTITION is not set # CONFIG_ATARI_PARTITION is not set # CONFIG_MAC_PARTITION is not set CONFIG_MSDOS_PARTITION=y # CONFIG_BSD_DISKLABEL is not set # CONFIG_MINIX_SUBPARTITION is not set # CONFIG_SOLARIS_X86_PARTITION is not set # CONFIG_UNIXWARE_DISKLABEL is not set # CONFIG_LDM_PARTITION is not set # CONFIG_SGI_PARTITION is not set # CONFIG_ULTRIX_PARTITION is not set # CONFIG_SUN_PARTITION is not set # CONFIG_KARMA_PARTITION is not set # CONFIG_EFI_PARTITION is not set # CONFIG_SYSV68_PARTITION is not set CONFIG_NLS=m CONFIG_NLS_DEFAULT="iso8859-1" # CONFIG_NLS_CODEPAGE_437 is not set # CONFIG_NLS_CODEPAGE_737 is not set # CONFIG_NLS_CODEPAGE_775 is not set # CONFIG_NLS_CODEPAGE_850 is not set # CONFIG_NLS_CODEPAGE_852 is not set # CONFIG_NLS_CODEPAGE_855 is not set # CONFIG_NLS_CODEPAGE_857 is not set # CONFIG_NLS_CODEPAGE_860 is not set # CONFIG_NLS_CODEPAGE_861 is not set # CONFIG_NLS_CODEPAGE_862 is not set # CONFIG_NLS_CODEPAGE_863 is not set # CONFIG_NLS_CODEPAGE_864 is not set # CONFIG_NLS_CODEPAGE_865 is not set # CONFIG_NLS_CODEPAGE_866 is not set # CONFIG_NLS_CODEPAGE_869 is not set # CONFIG_NLS_CODEPAGE_936 is not set # CONFIG_NLS_CODEPAGE_950 is not set # CONFIG_NLS_CODEPAGE_932 is not set # CONFIG_NLS_CODEPAGE_949 is not set # CONFIG_NLS_CODEPAGE_874 is not set # CONFIG_NLS_ISO8859_8 is not set # CONFIG_NLS_CODEPAGE_1250 is not set # CONFIG_NLS_CODEPAGE_1251 is not set # CONFIG_NLS_ASCII is not set # CONFIG_NLS_ISO8859_1 is not set # CONFIG_NLS_ISO8859_2 is not set # CONFIG_NLS_ISO8859_3 is not set # CONFIG_NLS_ISO8859_4 is not set # CONFIG_NLS_ISO8859_5 is not set # CONFIG_NLS_ISO8859_6 is not set # CONFIG_NLS_ISO8859_7 is not set # CONFIG_NLS_ISO8859_9 is not set # CONFIG_NLS_ISO8859_13 is not set # CONFIG_NLS_ISO8859_14 is not set # CONFIG_NLS_ISO8859_15 is not set # CONFIG_NLS_KOI8_R is not set # CONFIG_NLS_KOI8_U is not set # CONFIG_NLS_UTF8 is not set # CONFIG_DLM is not set # # Kernel hacking # CONFIG_TRACE_IRQFLAGS_SUPPORT=y # CONFIG_PRINTK_TIME is not set CONFIG_ENABLE_WARN_DEPRECATED=y CONFIG_ENABLE_MUST_CHECK=y CONFIG_FRAME_WARN=2048 # CONFIG_MAGIC_SYSRQ is not set # CONFIG_STRIP_ASM_SYMS is not set # CONFIG_UNUSED_SYMBOLS is not set CONFIG_DEBUG_FS=y # CONFIG_HEADERS_CHECK is not set # CONFIG_DEBUG_KERNEL is not set # CONFIG_SLUB_DEBUG_ON is not set # CONFIG_SLUB_STATS is not set # CONFIG_DEBUG_MEMORY_INIT is not set CONFIG_RCU_CPU_STALL_DETECTOR=y # CONFIG_SYSCTL_SYSCALL_CHECK is not set CONFIG_HAVE_FUNCTION_TRACER=y CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y CONFIG_HAVE_DYNAMIC_FTRACE=y CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y CONFIG_TRACING_SUPPORT=y # CONFIG_FTRACE is not set # CONFIG_DYNAMIC_DEBUG is not set # CONFIG_SAMPLES is not set CONFIG_HAVE_ARCH_KGDB=y CONFIG_EARLY_PRINTK=y # CONFIG_CMDLINE_BOOL is not set # # Security options # # CONFIG_KEYS is not set # CONFIG_SECURITY is not set # CONFIG_SECURITYFS is not set # CONFIG_DEFAULT_SECURITY_SELINUX is not set # CONFIG_DEFAULT_SECURITY_SMACK is not set # CONFIG_DEFAULT_SECURITY_TOMOYO is not set CONFIG_DEFAULT_SECURITY_DAC=y CONFIG_DEFAULT_SECURITY="" CONFIG_XOR_BLOCKS=m CONFIG_ASYNC_CORE=m CONFIG_ASYNC_MEMCPY=m CONFIG_ASYNC_XOR=m CONFIG_ASYNC_PQ=m CONFIG_ASYNC_RAID6_RECOV=m CONFIG_CRYPTO=y # # Crypto core or helper # # CONFIG_CRYPTO_FIPS is not set CONFIG_CRYPTO_ALGAPI=y CONFIG_CRYPTO_ALGAPI2=y CONFIG_CRYPTO_AEAD=m CONFIG_CRYPTO_AEAD2=y CONFIG_CRYPTO_BLKCIPHER=m CONFIG_CRYPTO_BLKCIPHER2=y CONFIG_CRYPTO_HASH=y CONFIG_CRYPTO_HASH2=y CONFIG_CRYPTO_RNG=m CONFIG_CRYPTO_RNG2=y CONFIG_CRYPTO_PCOMP=y CONFIG_CRYPTO_MANAGER=m CONFIG_CRYPTO_MANAGER2=y # CONFIG_CRYPTO_GF128MUL is not set # CONFIG_CRYPTO_NULL is not set CONFIG_CRYPTO_WORKQUEUE=y # CONFIG_CRYPTO_CRYPTD is not set CONFIG_CRYPTO_AUTHENC=m # CONFIG_CRYPTO_TEST is not set # # Authenticated Encryption with Associated Data # # CONFIG_CRYPTO_CCM is not set # CONFIG_CRYPTO_GCM is not set # CONFIG_CRYPTO_SEQIV is not set # # Block modes # CONFIG_CRYPTO_CBC=m # CONFIG_CRYPTO_CTR is not set # CONFIG_CRYPTO_CTS is not set # CONFIG_CRYPTO_ECB is not set # CONFIG_CRYPTO_LRW is not set # CONFIG_CRYPTO_PCBC is not set # CONFIG_CRYPTO_XTS is not set # # Hash modes # CONFIG_CRYPTO_HMAC=m # CONFIG_CRYPTO_XCBC is not set # CONFIG_CRYPTO_VMAC is not set # # Digest # # CONFIG_CRYPTO_CRC32C is not set # CONFIG_CRYPTO_GHASH is not set # CONFIG_CRYPTO_MD4 is not set CONFIG_CRYPTO_MD5=y # CONFIG_CRYPTO_MICHAEL_MIC is not set # CONFIG_CRYPTO_RMD128 is not set # CONFIG_CRYPTO_RMD160 is not set # CONFIG_CRYPTO_RMD256 is not set # CONFIG_CRYPTO_RMD320 is not set CONFIG_CRYPTO_SHA1=m # CONFIG_CRYPTO_SHA256 is not set # CONFIG_CRYPTO_SHA512 is not set # CONFIG_CRYPTO_TGR192 is not set # CONFIG_CRYPTO_WP512 is not set # # Ciphers # CONFIG_CRYPTO_AES=m # CONFIG_CRYPTO_ANUBIS is not set # CONFIG_CRYPTO_ARC4 is not set # CONFIG_CRYPTO_BLOWFISH is not set # CONFIG_CRYPTO_CAMELLIA is not set # CONFIG_CRYPTO_CAST5 is not set # CONFIG_CRYPTO_CAST6 is not set CONFIG_CRYPTO_DES=m # CONFIG_CRYPTO_FCRYPT is not set # CONFIG_CRYPTO_KHAZAD is not set # CONFIG_CRYPTO_SALSA20 is not set # CONFIG_CRYPTO_SEED is not set # CONFIG_CRYPTO_SERPENT is not set # CONFIG_CRYPTO_TEA is not set # CONFIG_CRYPTO_TWOFISH is not set # # Compression # CONFIG_CRYPTO_DEFLATE=m # CONFIG_CRYPTO_ZLIB is not set # CONFIG_CRYPTO_LZO is not set # # Random Number Generation # CONFIG_CRYPTO_ANSI_CPRNG=m CONFIG_CRYPTO_HW=y # CONFIG_CRYPTO_DEV_HIFN_795X is not set # CONFIG_BINARY_PRINTF is not set # # Library routines # CONFIG_BITREVERSE=y CONFIG_GENERIC_FIND_LAST_BIT=y # CONFIG_CRC_CCITT is not set CONFIG_CRC16=m # CONFIG_CRC_T10DIF is not set # CONFIG_CRC_ITU_T is not set CONFIG_CRC32=y # CONFIG_CRC7 is not set # CONFIG_LIBCRC32C is not set CONFIG_ZLIB_INFLATE=y CONFIG_ZLIB_DEFLATE=m CONFIG_DECOMPRESS_GZIP=y CONFIG_REED_SOLOMON=m CONFIG_REED_SOLOMON_DEC16=y CONFIG_HAS_IOMEM=y CONFIG_HAS_IOPORT=y CONFIG_HAS_DMA=y CONFIG_NLATTR=y --sT9gWZPUZYhvPS56-- From ralf@linux-mips.org Mon Feb 22 21:36:10 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 22 Feb 2010 21:36:14 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:42620 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-FAIL) by eddie.linux-mips.org with ESMTP id S1491834Ab0BVUgK (ORCPT ); Mon, 22 Feb 2010 21:36:10 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id o1MKa8ow003761; Mon, 22 Feb 2010 21:36:09 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id o1MKa7CE003757; Mon, 22 Feb 2010 21:36:07 +0100 Date: Mon, 22 Feb 2010 21:36:07 +0100 From: Ralf Baechle To: Hauke Mehrtens Cc: linux-mips@linux-mips.org Subject: Re: [PATCH] MIPS: Bcm47xx: Fix 128MB RAM support Message-ID: <20100222203607.GA1548@linux-mips.org> References: <1266691880-372-1-git-send-email-hauke@hauke-m.de> <20100222191440.GA12818@linux-mips.org> <4B82E827.8030005@hauke-m.de> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <4B82E827.8030005@hauke-m.de> User-Agent: Mutt/1.5.20 (2009-08-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25984 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Mon, Feb 22, 2010 at 09:25:11PM +0100, Hauke Mehrtens wrote: > > Is this a hardware issue prefetching issue? The kernel should not try > > CPU prefetch instructions at all on non-coherent CPUs such as the > > BCM47xx. > > This is a hardware issue on the bcm47xx when 128MB ram is present. This > workaround is out of broadcom's kernel sources and is included in > OpenWRT for some months. Without this patch the kernel does not even > print out anything and with this patch it is working. Thanks! I was asking to ensure this isn't a workaround for an already solved kernel software issue. Patch applied, Ralf From bjorn.helgaas@hp.com Mon Feb 22 21:55:38 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 22 Feb 2010 21:55:41 +0100 (CET) Received: from g4t0017.houston.hp.com ([15.201.24.20]:17515 "EHLO g4t0017.houston.hp.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491838Ab0BVUzh (ORCPT ); Mon, 22 Feb 2010 21:55:37 +0100 Received: from g4t0018.houston.hp.com (g4t0018.houston.hp.com [16.234.32.27]) by g4t0017.houston.hp.com (Postfix) with ESMTP id 07B08381CC; Mon, 22 Feb 2010 20:55:31 +0000 (UTC) Received: from ldl (ldl.fc.hp.com [15.11.146.30]) by g4t0018.houston.hp.com (Postfix) with ESMTP id F1081100B1; Mon, 22 Feb 2010 20:55:29 +0000 (UTC) Received: from localhost (ldl.fc.hp.com [127.0.0.1]) by ldl (Postfix) with ESMTP id DA5BDCF004A; Mon, 22 Feb 2010 13:55:29 -0700 (MST) Received: from ldl ([127.0.0.1]) by localhost (ldl.fc.hp.com [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id a3CuSBrjna+O; Mon, 22 Feb 2010 13:55:29 -0700 (MST) Received: from tigger.helgaas (lart.fc.hp.com [15.11.146.31]) by ldl (Postfix) with ESMTP id C3820CF0040; Mon, 22 Feb 2010 13:55:29 -0700 (MST) From: Bjorn Helgaas To: Yoichi Yuasa Subject: Re: Reverting old hack Date: Mon, 22 Feb 2010 13:55:28 -0700 User-Agent: KMail/1.9.10 Cc: Ralf Baechle , linux-mips@linux-mips.org References: <20100220113134.GA27194@linux-mips.org> <1266677869.1320.8.camel@dc7800.home> <20100221164531.382b3785.yuasa@linux-mips.org> In-Reply-To: <20100221164531.382b3785.yuasa@linux-mips.org> MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit Content-Disposition: inline Message-Id: <201002221355.28939.bjorn.helgaas@hp.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25985 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: bjorn.helgaas@hp.com Precedence: bulk X-list: linux-mips On Sunday 21 February 2010 12:45:31 am Yoichi Yuasa wrote: > > I'd like to understand the PCI architecture of Cobalt better. Would you > > mind turning on CONFIG_PCI_DEBUG and posting the dmesg log? > > If you want to know what happen, you can see my old e-mail. > > http://marc.info/?l=linux-kernel&m=118792430424186&w=2 There's not much detail there. It would save me a lot of time if you could collect the complete dmesg log, /proc/iomem, and /proc/ioports. Thanks, Bjorn From David.Daney@caviumnetworks.com Mon Feb 22 21:55:59 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 22 Feb 2010 21:56:05 +0100 (CET) Received: from mail3.caviumnetworks.com ([12.108.191.235]:1198 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491884Ab0BVUz6 (ORCPT ); Mon, 22 Feb 2010 21:55:58 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Mon, 22 Feb 2010 12:56:05 -0800 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Mon, 22 Feb 2010 12:55:29 -0800 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Mon, 22 Feb 2010 12:55:29 -0800 Message-ID: <4B82EF41.2050603@caviumnetworks.com> Date: Mon, 22 Feb 2010 12:55:29 -0800 From: David Daney User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.7) Gecko/20100120 Fedora/3.0.1-1.fc12 Thunderbird/3.0.1 MIME-Version: 1.0 To: Andreas Barth CC: linux-mips@linux-mips.org Subject: Re: Problems and workarounds while building octeon kernels References: <20100220175125.GQ27216@mails.so.argh.org> <4B82C20D.9000302@caviumnetworks.com> <20100222202545.GV27216@mails.so.argh.org> In-Reply-To: <20100222202545.GV27216@mails.so.argh.org> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 22 Feb 2010 20:55:29.0563 (UTC) FILETIME=[5DD41EB0:01CAB401] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25986 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips On 02/22/2010 12:25 PM, Andreas Barth wrote: > * David Daney (ddaney@caviumnetworks.com) [100222 18:57]: >> On 02/20/2010 09:51 AM, Andreas Barth wrote: >>> I tried to build an recent linux 2.6.33-rc something in an unstable >>> Debian chroot. I had the following issues (plus workarounds / fixes) - >>> please don't hesitate to ask me if you have further questions. > >> Can you supply the .config as well as tell me the version of GCC you are >> using? > > Attached (the compiling variant). It is uninteresting, I already have one that works. How about the version that provokes all the errors you mention? > > gcc is 4.4.3-2. > How about sending me the output of "gcc -x c -dM -E /dev/null" from that compiler? Thanks, David Daney From aba@not.so.argh.org Mon Feb 22 22:03:36 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 22 Feb 2010 22:03:41 +0100 (CET) Received: from alius.ayous.org ([78.46.213.165]:40902 "EHLO alius.ayous.org" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491865Ab0BVVDg (ORCPT ); Mon, 22 Feb 2010 22:03:36 +0100 Received: from eos.turmzimmer.net ([2001:a60:f006:aba::1]) by alius.turmzimmer.net with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.69) (envelope-from ) id 1NjfRG-00023e-7T; Mon, 22 Feb 2010 21:03:35 +0000 Received: from aba by eos.turmzimmer.net with local (Exim 4.69) (envelope-from ) id 1NjfRA-0003IZ-7r; Mon, 22 Feb 2010 22:03:28 +0100 Date: Mon, 22 Feb 2010 22:03:28 +0100 From: Andreas Barth To: David Daney Cc: linux-mips@linux-mips.org Subject: Re: Problems and workarounds while building octeon kernels Message-ID: <20100222210328.GW27216@mails.so.argh.org> References: <20100220175125.GQ27216@mails.so.argh.org> <4B82C20D.9000302@caviumnetworks.com> <20100222202545.GV27216@mails.so.argh.org> <4B82EF41.2050603@caviumnetworks.com> MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="cN0A5YokcrYPGsSB" Content-Disposition: inline In-Reply-To: <4B82EF41.2050603@caviumnetworks.com> X-Editor: Vim http://www.vim.org/ User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25987 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: aba@not.so.argh.org Precedence: bulk X-list: linux-mips --cN0A5YokcrYPGsSB Content-Type: text/plain; charset=us-ascii Content-Disposition: inline * David Daney (ddaney@caviumnetworks.com) [100222 21:56]: > On 02/22/2010 12:25 PM, Andreas Barth wrote: >> * David Daney (ddaney@caviumnetworks.com) [100222 18:57]: >>> On 02/20/2010 09:51 AM, Andreas Barth wrote: >>>> I tried to build an recent linux 2.6.33-rc something in an unstable >>>> Debian chroot. I had the following issues (plus workarounds / fixes) - >>>> please don't hesitate to ask me if you have further questions. >> >>> Can you supply the .config as well as tell me the version of GCC you are >>> using? >> >> Attached (the compiling variant). > > It is uninteresting, I already have one that works. How about the > version that provokes all the errors you mention? I think this one does have all the errors. Basically trying to build without serial console, drivers/mtd to m, with pc speaker support as module should provoke all the errors I had. >> gcc is 4.4.3-2. > How about sending me the output of "gcc -x c -dM -E /dev/null" from that > compiler? Attached as well. Cheers, Andi --cN0A5YokcrYPGsSB Content-Type: text/plain; charset=us-ascii Content-Disposition: attachment; filename="linux-config-cavium.1" # # Automatically generated make config: don't edit # Linux kernel version: 2.6.33-rc8 # Sat Feb 20 14:47:16 2010 # CONFIG_MIPS=y # # Machine selection # # CONFIG_MACH_ALCHEMY is not set # CONFIG_AR7 is not set # CONFIG_BCM47XX is not set # CONFIG_BCM63XX is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set # CONFIG_LASAT is not set # CONFIG_MACH_LOONGSON is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SIM is not set # CONFIG_NEC_MARKEINS is not set # CONFIG_MACH_VR41XX is not set # CONFIG_NXP_STB220 is not set # CONFIG_NXP_STB225 is not set # CONFIG_PNX8550_JBS is not set # CONFIG_PNX8550_STB810 is not set # CONFIG_PMC_MSP is not set # CONFIG_PMC_YOSEMITE is not set # CONFIG_POWERTV is not set # CONFIG_SGI_IP22 is not set # CONFIG_SGI_IP27 is not set # CONFIG_SGI_IP28 is not set # CONFIG_SGI_IP32 is not set # CONFIG_SIBYTE_CRHINE is not set # CONFIG_SIBYTE_CARMEL is not set # CONFIG_SIBYTE_CRHONE is not set # CONFIG_SIBYTE_RHONE is not set # CONFIG_SIBYTE_SWARM is not set # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_SENTOSA is not set # CONFIG_SIBYTE_BIGSUR is not set # CONFIG_SNI_RM is not set # CONFIG_MACH_TX39XX is not set # CONFIG_MACH_TX49XX is not set # CONFIG_MIKROTIK_RB532 is not set # CONFIG_WR_PPMC is not set # CONFIG_CAVIUM_OCTEON_SIMULATOR is not set CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD=y # CONFIG_ALCHEMY_GPIO_INDIRECT is not set CONFIG_CAVIUM_OCTEON_SPECIFIC_OPTIONS=y # CONFIG_CAVIUM_OCTEON_2ND_KERNEL is not set CONFIG_CAVIUM_OCTEON_HW_FIX_UNALIGNED=y CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE=1 CONFIG_CAVIUM_OCTEON_LOCK_L2=y CONFIG_CAVIUM_OCTEON_LOCK_L2_TLB=y CONFIG_CAVIUM_OCTEON_LOCK_L2_EXCEPTION=y CONFIG_CAVIUM_OCTEON_LOCK_L2_LOW_LEVEL_INTERRUPT=y CONFIG_CAVIUM_OCTEON_LOCK_L2_INTERRUPT=y CONFIG_CAVIUM_OCTEON_LOCK_L2_MEMCPY=y CONFIG_ARCH_SPARSEMEM_ENABLE=y CONFIG_LOONGSON_UART_BASE=y CONFIG_RWSEM_GENERIC_SPINLOCK=y # CONFIG_ARCH_HAS_ILOG2_U32 is not set # CONFIG_ARCH_HAS_ILOG2_U64 is not set CONFIG_ARCH_SUPPORTS_OPROFILE=y CONFIG_GENERIC_FIND_NEXT_BIT=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_GENERIC_CLOCKEVENTS=y CONFIG_GENERIC_TIME=y CONFIG_GENERIC_CMOS_UPDATE=y CONFIG_SCHED_OMIT_FRAME_POINTER=y CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y CONFIG_CEVT_R4K_LIB=y CONFIG_CEVT_R4K=y CONFIG_DMA_COHERENT=y CONFIG_SYS_HAS_EARLY_PRINTK=y # CONFIG_HOTPLUG_CPU is not set CONFIG_SYS_SUPPORTS_HOTPLUG_CPU=y # CONFIG_NO_IOPORT is not set CONFIG_CPU_BIG_ENDIAN=y # CONFIG_CPU_LITTLE_ENDIAN is not set CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y CONFIG_SYS_SUPPORTS_HUGETLBFS=y CONFIG_IRQ_CPU=y CONFIG_IRQ_CPU_OCTEON=y CONFIG_SWAP_IO_SPACE=y CONFIG_MIPS_L1_CACHE_SHIFT=7 # # CPU selection # # CONFIG_CPU_LOONGSON2E is not set # CONFIG_CPU_LOONGSON2F is not set # CONFIG_CPU_MIPS32_R1 is not set # CONFIG_CPU_MIPS32_R2 is not set # CONFIG_CPU_MIPS64_R1 is not set # CONFIG_CPU_MIPS64_R2 is not set # CONFIG_CPU_R3000 is not set # CONFIG_CPU_TX39XX is not set # CONFIG_CPU_VR41XX is not set # CONFIG_CPU_R4300 is not set # CONFIG_CPU_R4X00 is not set # CONFIG_CPU_TX49XX is not set # CONFIG_CPU_R5000 is not set # CONFIG_CPU_R5432 is not set # CONFIG_CPU_R5500 is not set # CONFIG_CPU_R6000 is not set # CONFIG_CPU_NEVADA is not set # CONFIG_CPU_R8000 is not set # CONFIG_CPU_R10000 is not set # CONFIG_CPU_RM7000 is not set # CONFIG_CPU_RM9000 is not set # CONFIG_CPU_SB1 is not set CONFIG_CPU_CAVIUM_OCTEON=y CONFIG_SYS_HAS_CPU_CAVIUM_OCTEON=y CONFIG_WEAK_ORDERING=y CONFIG_WEAK_REORDERING_BEYOND_LLSC=y CONFIG_CPU_MIPSR2=y CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y CONFIG_CPU_SUPPORTS_HUGEPAGES=y CONFIG_MIPS_PGD_C0_CONTEXT=y CONFIG_HARDWARE_WATCHPOINTS=y # # Kernel type # # CONFIG_32BIT is not set CONFIG_64BIT=y CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_8KB is not set # CONFIG_PAGE_SIZE_16KB is not set # CONFIG_PAGE_SIZE_32KB is not set # CONFIG_PAGE_SIZE_64KB is not set CONFIG_CPU_HAS_PREFETCH=y CONFIG_MIPS_MT_DISABLED=y # CONFIG_MIPS_MT_SMP is not set # CONFIG_MIPS_MT_SMTC is not set CONFIG_64BIT_PHYS_ADDR=y CONFIG_CPU_HAS_SYNC=y CONFIG_GENERIC_HARDIRQS=y CONFIG_GENERIC_IRQ_PROBE=y CONFIG_IRQ_PER_CPU=y CONFIG_CPU_SUPPORTS_HIGHMEM=y CONFIG_SYS_SUPPORTS_HIGHMEM=y CONFIG_ARCH_FLATMEM_ENABLE=y CONFIG_ARCH_POPULATES_NODE_MAP=y CONFIG_SELECT_MEMORY_MODEL=y CONFIG_FLATMEM_MANUAL=y # CONFIG_DISCONTIGMEM_MANUAL is not set # CONFIG_SPARSEMEM_MANUAL is not set CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y CONFIG_SPARSEMEM_STATIC=y CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 CONFIG_PHYS_ADDR_T_64BIT=y CONFIG_ZONE_DMA_FLAG=0 CONFIG_VIRT_TO_BUS=y # CONFIG_KSM is not set CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 CONFIG_SMP=y CONFIG_SYS_SUPPORTS_SMP=y CONFIG_NR_CPUS_DEFAULT_16=y CONFIG_NR_CPUS=16 # CONFIG_NO_HZ is not set # CONFIG_HIGH_RES_TIMERS is not set CONFIG_GENERIC_CLOCKEVENTS_BUILD=y # CONFIG_HZ_48 is not set # CONFIG_HZ_100 is not set # CONFIG_HZ_128 is not set CONFIG_HZ_250=y # CONFIG_HZ_256 is not set # CONFIG_HZ_1000 is not set # CONFIG_HZ_1024 is not set CONFIG_SYS_SUPPORTS_ARBIT_HZ=y CONFIG_HZ=250 CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set # CONFIG_KEXEC is not set CONFIG_SECCOMP=y CONFIG_LOCKDEP_SUPPORT=y CONFIG_STACKTRACE_SUPPORT=y CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" CONFIG_CONSTRUCTORS=y # # General setup # CONFIG_EXPERIMENTAL=y CONFIG_LOCK_KERNEL=y CONFIG_INIT_ENV_ARG_LIMIT=32 CONFIG_LOCALVERSION="-dsa-octeon" CONFIG_LOCALVERSION_AUTO=y CONFIG_SWAP=y CONFIG_SYSVIPC=y CONFIG_SYSVIPC_SYSCTL=y # CONFIG_POSIX_MQUEUE is not set # CONFIG_BSD_PROCESS_ACCT is not set # CONFIG_TASKSTATS is not set # CONFIG_AUDIT is not set # # RCU Subsystem # CONFIG_TREE_RCU=y # CONFIG_TREE_PREEMPT_RCU is not set # CONFIG_TINY_RCU is not set # CONFIG_RCU_TRACE is not set CONFIG_RCU_FANOUT=64 # CONFIG_RCU_FANOUT_EXACT is not set # CONFIG_TREE_RCU_TRACE is not set CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=17 # CONFIG_GROUP_SCHED is not set # CONFIG_CGROUPS is not set CONFIG_SYSFS_DEPRECATED=y CONFIG_SYSFS_DEPRECATED_V2=y # CONFIG_RELAY is not set # CONFIG_NAMESPACES is not set CONFIG_BLK_DEV_INITRD=y CONFIG_INITRAMFS_SOURCE="" CONFIG_RD_GZIP=y # CONFIG_RD_BZIP2 is not set # CONFIG_RD_LZMA is not set # CONFIG_RD_LZO is not set CONFIG_CC_OPTIMIZE_FOR_SIZE=y CONFIG_SYSCTL=y CONFIG_ANON_INODES=y CONFIG_EMBEDDED=y CONFIG_SYSCTL_SYSCALL=y CONFIG_KALLSYMS=y CONFIG_KALLSYMS_ALL=y # CONFIG_KALLSYMS_EXTRA_PASS is not set CONFIG_HOTPLUG=y CONFIG_PRINTK=y CONFIG_BUG=y CONFIG_ELF_CORE=y CONFIG_PCSPKR_PLATFORM=y CONFIG_BASE_FULL=y CONFIG_FUTEX=y CONFIG_EPOLL=y CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y CONFIG_AIO=y # # Kernel Performance Events And Counters # CONFIG_VM_EVENT_COUNTERS=y CONFIG_PCI_QUIRKS=y CONFIG_SLUB_DEBUG=y CONFIG_COMPAT_BRK=y # CONFIG_SLAB is not set CONFIG_SLUB=y # CONFIG_SLOB is not set # CONFIG_PROFILING is not set CONFIG_HAVE_OPROFILE=y CONFIG_HAVE_SYSCALL_WRAPPERS=y CONFIG_USE_GENERIC_SMP_HELPERS=y # # GCOV-based kernel profiling # # CONFIG_GCOV_KERNEL is not set CONFIG_SLOW_WORK=y # CONFIG_SLOW_WORK_DEBUG is not set CONFIG_HAVE_GENERIC_DMA_COHERENT=y CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y CONFIG_BASE_SMALL=0 CONFIG_MODULES=y CONFIG_MODULE_FORCE_LOAD=y CONFIG_MODULE_UNLOAD=y # CONFIG_MODULE_FORCE_UNLOAD is not set CONFIG_MODVERSIONS=y # CONFIG_MODULE_SRCVERSION_ALL is not set CONFIG_STOP_MACHINE=y CONFIG_BLOCK=y CONFIG_BLK_DEV_BSG=y # CONFIG_BLK_DEV_INTEGRITY is not set CONFIG_BLOCK_COMPAT=y # # IO Schedulers # CONFIG_IOSCHED_NOOP=y CONFIG_IOSCHED_DEADLINE=y CONFIG_IOSCHED_CFQ=y # CONFIG_DEFAULT_DEADLINE is not set CONFIG_DEFAULT_CFQ=y # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="cfq" # CONFIG_INLINE_SPIN_TRYLOCK is not set # CONFIG_INLINE_SPIN_TRYLOCK_BH is not set # CONFIG_INLINE_SPIN_LOCK is not set # CONFIG_INLINE_SPIN_LOCK_BH is not set # CONFIG_INLINE_SPIN_LOCK_IRQ is not set # CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set CONFIG_INLINE_SPIN_UNLOCK=y # CONFIG_INLINE_SPIN_UNLOCK_BH is not set CONFIG_INLINE_SPIN_UNLOCK_IRQ=y # CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set # CONFIG_INLINE_READ_TRYLOCK is not set # CONFIG_INLINE_READ_LOCK is not set # CONFIG_INLINE_READ_LOCK_BH is not set # CONFIG_INLINE_READ_LOCK_IRQ is not set # CONFIG_INLINE_READ_LOCK_IRQSAVE is not set CONFIG_INLINE_READ_UNLOCK=y # CONFIG_INLINE_READ_UNLOCK_BH is not set CONFIG_INLINE_READ_UNLOCK_IRQ=y # CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set # CONFIG_INLINE_WRITE_TRYLOCK is not set # CONFIG_INLINE_WRITE_LOCK is not set # CONFIG_INLINE_WRITE_LOCK_BH is not set # CONFIG_INLINE_WRITE_LOCK_IRQ is not set # CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set CONFIG_INLINE_WRITE_UNLOCK=y # CONFIG_INLINE_WRITE_UNLOCK_BH is not set CONFIG_INLINE_WRITE_UNLOCK_IRQ=y # CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set CONFIG_MUTEX_SPIN_ON_OWNER=y # CONFIG_FREEZER is not set # # Bus options (PCI, PCMCIA, EISA, ISA, TC) # CONFIG_HW_HAS_PCI=y CONFIG_PCI=y CONFIG_PCI_DOMAINS=y CONFIG_ARCH_SUPPORTS_MSI=y # CONFIG_PCI_MSI is not set CONFIG_PCI_LEGACY=y CONFIG_PCI_STUB=m CONFIG_PCI_IOV=y CONFIG_MMU=y # CONFIG_PCCARD is not set CONFIG_HOTPLUG_PCI=m # CONFIG_HOTPLUG_PCI_FAKE is not set # CONFIG_HOTPLUG_PCI_CPCI is not set # CONFIG_HOTPLUG_PCI_SHPC is not set # # Executable file formats # CONFIG_BINFMT_ELF=y # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set # CONFIG_HAVE_AOUT is not set # CONFIG_BINFMT_MISC is not set CONFIG_MIPS32_COMPAT=y CONFIG_COMPAT=y CONFIG_SYSVIPC_COMPAT=y CONFIG_MIPS32_O32=y CONFIG_MIPS32_N32=y CONFIG_BINFMT_ELF32=y # # Power management options # CONFIG_ARCH_HIBERNATION_POSSIBLE=y CONFIG_ARCH_SUSPEND_POSSIBLE=y # CONFIG_PM is not set CONFIG_NET=y # # Networking options # # CONFIG_PACKET is not set # CONFIG_UNIX is not set CONFIG_XFRM=y # CONFIG_XFRM_USER is not set # CONFIG_XFRM_SUB_POLICY is not set # CONFIG_XFRM_MIGRATE is not set # CONFIG_XFRM_STATISTICS is not set CONFIG_XFRM_IPCOMP=m # CONFIG_NET_KEY is not set CONFIG_INET=y CONFIG_IP_MULTICAST=y CONFIG_IP_ADVANCED_ROUTER=y CONFIG_ASK_IP_FIB_HASH=y # CONFIG_IP_FIB_TRIE is not set CONFIG_IP_FIB_HASH=y CONFIG_IP_MULTIPLE_TABLES=y CONFIG_IP_ROUTE_MULTIPATH=y CONFIG_IP_ROUTE_VERBOSE=y CONFIG_IP_PNP=y CONFIG_IP_PNP_DHCP=y CONFIG_IP_PNP_BOOTP=y CONFIG_IP_PNP_RARP=y CONFIG_NET_IPIP=m CONFIG_NET_IPGRE=m CONFIG_NET_IPGRE_BROADCAST=y CONFIG_IP_MROUTE=y # CONFIG_IP_PIMSM_V1 is not set # CONFIG_IP_PIMSM_V2 is not set CONFIG_ARPD=y CONFIG_SYN_COOKIES=y CONFIG_INET_AH=m CONFIG_INET_ESP=m CONFIG_INET_IPCOMP=m CONFIG_INET_XFRM_TUNNEL=m CONFIG_INET_TUNNEL=m CONFIG_INET_XFRM_MODE_TRANSPORT=y CONFIG_INET_XFRM_MODE_TUNNEL=y CONFIG_INET_XFRM_MODE_BEET=y CONFIG_INET_LRO=y CONFIG_INET_DIAG=y CONFIG_INET_TCP_DIAG=y CONFIG_TCP_CONG_ADVANCED=y CONFIG_TCP_CONG_BIC=m CONFIG_TCP_CONG_CUBIC=y CONFIG_TCP_CONG_WESTWOOD=m CONFIG_TCP_CONG_HTCP=m # CONFIG_TCP_CONG_HSTCP is not set # CONFIG_TCP_CONG_HYBLA is not set # CONFIG_TCP_CONG_VEGAS is not set # CONFIG_TCP_CONG_SCALABLE is not set # CONFIG_TCP_CONG_LP is not set # CONFIG_TCP_CONG_VENO is not set # CONFIG_TCP_CONG_YEAH is not set # CONFIG_TCP_CONG_ILLINOIS is not set # CONFIG_DEFAULT_BIC is not set CONFIG_DEFAULT_CUBIC=y # CONFIG_DEFAULT_HTCP is not set # CONFIG_DEFAULT_VEGAS is not set # CONFIG_DEFAULT_WESTWOOD is not set # CONFIG_DEFAULT_RENO is not set CONFIG_DEFAULT_TCP_CONG="cubic" CONFIG_TCP_MD5SIG=y CONFIG_IPV6=m CONFIG_IPV6_PRIVACY=y CONFIG_IPV6_ROUTER_PREF=y CONFIG_IPV6_ROUTE_INFO=y CONFIG_IPV6_OPTIMISTIC_DAD=y CONFIG_INET6_AH=m CONFIG_INET6_ESP=m CONFIG_INET6_IPCOMP=m CONFIG_IPV6_MIP6=m CONFIG_INET6_XFRM_TUNNEL=m CONFIG_INET6_TUNNEL=m CONFIG_INET6_XFRM_MODE_TRANSPORT=m CONFIG_INET6_XFRM_MODE_TUNNEL=m CONFIG_INET6_XFRM_MODE_BEET=m CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m CONFIG_IPV6_SIT=m CONFIG_IPV6_SIT_6RD=y CONFIG_IPV6_NDISC_NODETYPE=y CONFIG_IPV6_TUNNEL=m CONFIG_IPV6_MULTIPLE_TABLES=y CONFIG_IPV6_SUBTREES=y CONFIG_IPV6_MROUTE=y CONFIG_IPV6_PIMSM_V2=y # CONFIG_NETWORK_SECMARK is not set # CONFIG_NETFILTER is not set # CONFIG_IP_DCCP is not set # CONFIG_IP_SCTP is not set # CONFIG_RDS is not set # CONFIG_TIPC is not set # CONFIG_ATM is not set CONFIG_STP=m CONFIG_GARP=m CONFIG_BRIDGE=m # CONFIG_NET_DSA is not set CONFIG_VLAN_8021Q=m CONFIG_VLAN_8021Q_GVRP=y # CONFIG_DECNET is not set CONFIG_LLC=m # CONFIG_LLC2 is not set # CONFIG_IPX is not set # CONFIG_ATALK is not set # CONFIG_X25 is not set # CONFIG_LAPB is not set # CONFIG_ECONET is not set # CONFIG_WAN_ROUTER is not set # CONFIG_PHONET is not set # CONFIG_IEEE802154 is not set # CONFIG_NET_SCHED is not set # CONFIG_DCB is not set # # Network testing # # CONFIG_NET_PKTGEN is not set # CONFIG_HAMRADIO is not set # CONFIG_CAN is not set # CONFIG_IRDA is not set # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set CONFIG_FIB_RULES=y # CONFIG_WIRELESS is not set # CONFIG_WIMAX is not set # CONFIG_RFKILL is not set # CONFIG_NET_9P is not set # # Device Drivers # # # Generic Driver Options # CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_STANDALONE=y CONFIG_PREVENT_FIRMWARE_BUILD=y CONFIG_FW_LOADER=y CONFIG_FIRMWARE_IN_KERNEL=y CONFIG_EXTRA_FIRMWARE="" # CONFIG_SYS_HYPERVISOR is not set CONFIG_CONNECTOR=m CONFIG_MTD=m CONFIG_MTD_DEBUG=y CONFIG_MTD_DEBUG_VERBOSE=0 CONFIG_MTD_TESTS=m CONFIG_MTD_CONCAT=m CONFIG_MTD_PARTITIONS=y CONFIG_MTD_REDBOOT_PARTS=m CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=-1 CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED=y CONFIG_MTD_REDBOOT_PARTS_READONLY=y CONFIG_MTD_AR7_PARTS=m # # User Modules And Translation Layers # CONFIG_MTD_CHAR=m CONFIG_HAVE_MTD_OTP=y CONFIG_MTD_BLKDEVS=m CONFIG_MTD_BLOCK=m CONFIG_MTD_BLOCK_RO=m CONFIG_FTL=m CONFIG_NFTL=m CONFIG_NFTL_RW=y CONFIG_INFTL=m CONFIG_RFD_FTL=m CONFIG_SSFDC=m CONFIG_MTD_OOPS=m # # RAM/ROM/Flash chip drivers # CONFIG_MTD_CFI=m CONFIG_MTD_JEDECPROBE=m CONFIG_MTD_GEN_PROBE=m CONFIG_MTD_CFI_ADV_OPTIONS=y CONFIG_MTD_CFI_NOSWAP=y # CONFIG_MTD_CFI_BE_BYTE_SWAP is not set # CONFIG_MTD_CFI_LE_BYTE_SWAP is not set CONFIG_MTD_CFI_GEOMETRY=y CONFIG_MTD_MAP_BANK_WIDTH_1=y CONFIG_MTD_MAP_BANK_WIDTH_2=y CONFIG_MTD_MAP_BANK_WIDTH_4=y CONFIG_MTD_MAP_BANK_WIDTH_8=y CONFIG_MTD_MAP_BANK_WIDTH_16=y CONFIG_MTD_MAP_BANK_WIDTH_32=y CONFIG_MTD_CFI_I1=y CONFIG_MTD_CFI_I2=y CONFIG_MTD_CFI_I4=y CONFIG_MTD_CFI_I8=y CONFIG_MTD_OTP=y CONFIG_MTD_CFI_INTELEXT=m CONFIG_MTD_CFI_AMDSTD=m CONFIG_MTD_CFI_STAA=m CONFIG_MTD_CFI_UTIL=m CONFIG_MTD_RAM=m CONFIG_MTD_ROM=m CONFIG_MTD_ABSENT=m # # Mapping drivers for chip access # CONFIG_MTD_COMPLEX_MAPPINGS=y CONFIG_MTD_PHYSMAP=m CONFIG_MTD_PHYSMAP_COMPAT=y CONFIG_MTD_PHYSMAP_START=0x8000000 CONFIG_MTD_PHYSMAP_LEN=0 CONFIG_MTD_PHYSMAP_BANKWIDTH=2 CONFIG_MTD_PCI=m CONFIG_MTD_INTEL_VR_NOR=m CONFIG_MTD_PLATRAM=m # # Self-contained MTD device drivers # CONFIG_MTD_PMC551=m CONFIG_MTD_PMC551_BUGFIX=y CONFIG_MTD_PMC551_DEBUG=y CONFIG_MTD_SLRAM=m CONFIG_MTD_PHRAM=m CONFIG_MTD_MTDRAM=m CONFIG_MTDRAM_TOTAL_SIZE=4096 CONFIG_MTDRAM_ERASE_SIZE=128 CONFIG_MTD_BLOCK2MTD=m # # Disk-On-Chip Device Drivers # CONFIG_MTD_DOC2000=m CONFIG_MTD_DOC2001=m CONFIG_MTD_DOC2001PLUS=m CONFIG_MTD_DOCPROBE=m CONFIG_MTD_DOCECC=m CONFIG_MTD_DOCPROBE_ADVANCED=y CONFIG_MTD_DOCPROBE_ADDRESS=0x0000 CONFIG_MTD_DOCPROBE_HIGH=y CONFIG_MTD_DOCPROBE_55AA=y CONFIG_MTD_NAND=m CONFIG_MTD_NAND_VERIFY_WRITE=y CONFIG_MTD_NAND_ECC_SMC=y CONFIG_MTD_NAND_MUSEUM_IDS=y CONFIG_MTD_NAND_IDS=m CONFIG_MTD_NAND_DISKONCHIP=m CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADVANCED=y CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADDRESS=0 CONFIG_MTD_NAND_DISKONCHIP_PROBE_HIGH=y CONFIG_MTD_NAND_DISKONCHIP_BBTWRITE=y CONFIG_MTD_NAND_CAFE=m CONFIG_MTD_NAND_NANDSIM=m CONFIG_MTD_NAND_PLATFORM=m # CONFIG_MTD_ALAUDA is not set CONFIG_MTD_ONENAND=m CONFIG_MTD_ONENAND_VERIFY_WRITE=y CONFIG_MTD_ONENAND_GENERIC=m CONFIG_MTD_ONENAND_OTP=y CONFIG_MTD_ONENAND_2X_PROGRAM=y CONFIG_MTD_ONENAND_SIM=m # # LPDDR flash memory drivers # CONFIG_MTD_LPDDR=m CONFIG_MTD_QINFO_PROBE=m # # UBI - Unsorted block images # CONFIG_MTD_UBI=m CONFIG_MTD_UBI_WL_THRESHOLD=4096 CONFIG_MTD_UBI_BEB_RESERVE=1 CONFIG_MTD_UBI_GLUEBI=m # # UBI debugging options # CONFIG_MTD_UBI_DEBUG=y CONFIG_MTD_UBI_DEBUG_MSG=y CONFIG_MTD_UBI_DEBUG_PARANOID=y CONFIG_MTD_UBI_DEBUG_DISABLE_BGT=y CONFIG_MTD_UBI_DEBUG_EMULATE_BITFLIPS=y CONFIG_MTD_UBI_DEBUG_EMULATE_WRITE_FAILURES=y CONFIG_MTD_UBI_DEBUG_EMULATE_ERASE_FAILURES=y # # Additional UBI debugging messages # CONFIG_MTD_UBI_DEBUG_MSG_BLD=y CONFIG_MTD_UBI_DEBUG_MSG_EBA=y CONFIG_MTD_UBI_DEBUG_MSG_WL=y CONFIG_MTD_UBI_DEBUG_MSG_IO=y # CONFIG_PARPORT is not set CONFIG_BLK_DEV=y # CONFIG_BLK_CPQ_DA is not set # CONFIG_BLK_CPQ_CISS_DA is not set # CONFIG_BLK_DEV_DAC960 is not set # CONFIG_BLK_DEV_UMEM is not set # CONFIG_BLK_DEV_COW_COMMON is not set # CONFIG_BLK_DEV_LOOP is not set # CONFIG_BLK_DEV_DRBD is not set # CONFIG_BLK_DEV_NBD is not set # CONFIG_BLK_DEV_SX8 is not set # CONFIG_BLK_DEV_UB is not set # CONFIG_BLK_DEV_RAM is not set # CONFIG_CDROM_PKTCDVD is not set # CONFIG_ATA_OVER_ETH is not set # CONFIG_BLK_DEV_HD is not set CONFIG_MISC_DEVICES=y # CONFIG_AD525X_DPOT is not set # CONFIG_PHANTOM is not set # CONFIG_SGI_IOC4 is not set CONFIG_TIFM_CORE=m CONFIG_TIFM_7XX1=m # CONFIG_ICS932S401 is not set # CONFIG_ENCLOSURE_SERVICES is not set # CONFIG_HP_ILO is not set # CONFIG_ISL29003 is not set # CONFIG_DS1682 is not set # CONFIG_C2PORT is not set # # EEPROM support # # CONFIG_EEPROM_AT24 is not set # CONFIG_EEPROM_LEGACY is not set # CONFIG_EEPROM_MAX6875 is not set # CONFIG_EEPROM_93CX6 is not set CONFIG_CB710_CORE=m # CONFIG_CB710_DEBUG is not set CONFIG_CB710_DEBUG_ASSUMPTIONS=y # CONFIG_IWMC3200TOP is not set CONFIG_HAVE_IDE=y # CONFIG_IDE is not set # # SCSI device support # # CONFIG_RAID_ATTRS is not set CONFIG_SCSI=y CONFIG_SCSI_DMA=y # CONFIG_SCSI_TGT is not set # CONFIG_SCSI_NETLINK is not set CONFIG_SCSI_PROC_FS=y # # SCSI support type (disk, tape, CD-ROM) # # CONFIG_BLK_DEV_SD is not set # CONFIG_CHR_DEV_ST is not set # CONFIG_CHR_DEV_OSST is not set # CONFIG_BLK_DEV_SR is not set # CONFIG_CHR_DEV_SG is not set # CONFIG_CHR_DEV_SCH is not set # CONFIG_SCSI_MULTI_LUN is not set # CONFIG_SCSI_CONSTANTS is not set # CONFIG_SCSI_LOGGING is not set # CONFIG_SCSI_SCAN_ASYNC is not set CONFIG_SCSI_WAIT_SCAN=m # # SCSI Transports # # CONFIG_SCSI_SPI_ATTRS is not set # CONFIG_SCSI_FC_ATTRS is not set # CONFIG_SCSI_ISCSI_ATTRS is not set CONFIG_SCSI_SAS_ATTRS=y # CONFIG_SCSI_SAS_LIBSAS is not set # CONFIG_SCSI_SRP_ATTRS is not set CONFIG_SCSI_LOWLEVEL=y # CONFIG_ISCSI_TCP is not set # CONFIG_SCSI_BNX2_ISCSI is not set # CONFIG_BE2ISCSI is not set # CONFIG_BLK_DEV_3W_XXXX_RAID is not set # CONFIG_SCSI_HPSA is not set # CONFIG_SCSI_3W_9XXX is not set # CONFIG_SCSI_3W_SAS is not set # CONFIG_SCSI_ACARD is not set # CONFIG_SCSI_AACRAID is not set # CONFIG_SCSI_AIC7XXX is not set # CONFIG_SCSI_AIC7XXX_OLD is not set # CONFIG_SCSI_AIC79XX is not set # CONFIG_SCSI_AIC94XX is not set # CONFIG_SCSI_MVSAS is not set # CONFIG_SCSI_DPT_I2O is not set # CONFIG_SCSI_ADVANSYS is not set # CONFIG_SCSI_ARCMSR is not set # CONFIG_MEGARAID_NEWGEN is not set # CONFIG_MEGARAID_LEGACY is not set # CONFIG_MEGARAID_SAS is not set # CONFIG_SCSI_MPT2SAS is not set # CONFIG_SCSI_HPTIOP is not set # CONFIG_LIBFC is not set # CONFIG_LIBFCOE is not set # CONFIG_FCOE is not set # CONFIG_SCSI_DMX3191D is not set # CONFIG_SCSI_FUTURE_DOMAIN is not set # CONFIG_SCSI_IPS is not set # CONFIG_SCSI_INITIO is not set # CONFIG_SCSI_INIA100 is not set # CONFIG_SCSI_STEX is not set # CONFIG_SCSI_SYM53C8XX_2 is not set # CONFIG_SCSI_IPR is not set # CONFIG_SCSI_QLOGIC_1280 is not set # CONFIG_SCSI_QLA_FC is not set # CONFIG_SCSI_QLA_ISCSI is not set # CONFIG_SCSI_LPFC is not set # CONFIG_SCSI_DC395x is not set # CONFIG_SCSI_DC390T is not set # CONFIG_SCSI_DEBUG is not set # CONFIG_SCSI_PMCRAID is not set # CONFIG_SCSI_PM8001 is not set # CONFIG_SCSI_SRP is not set # CONFIG_SCSI_BFA_FC is not set # CONFIG_SCSI_DH is not set # CONFIG_SCSI_OSD_INITIATOR is not set CONFIG_ATA=y # CONFIG_ATA_NONSTANDARD is not set CONFIG_ATA_VERBOSE_ERROR=y CONFIG_SATA_PMP=y # CONFIG_SATA_AHCI is not set # CONFIG_SATA_SIL24 is not set CONFIG_ATA_SFF=y CONFIG_SATA_SVW=m CONFIG_ATA_PIIX=m CONFIG_SATA_MV=m CONFIG_SATA_NV=m CONFIG_PDC_ADMA=m CONFIG_SATA_QSTOR=m CONFIG_SATA_PROMISE=m CONFIG_SATA_SX4=m CONFIG_SATA_SIL=m CONFIG_SATA_SIS=m CONFIG_SATA_ULI=m CONFIG_SATA_VIA=m CONFIG_SATA_VITESSE=m CONFIG_SATA_INIC162X=m # CONFIG_PATA_ALI is not set # CONFIG_PATA_AMD is not set # CONFIG_PATA_ARTOP is not set # CONFIG_PATA_ATP867X is not set # CONFIG_PATA_ATIIXP is not set # CONFIG_PATA_CMD640_PCI is not set # CONFIG_PATA_CMD64X is not set # CONFIG_PATA_CS5520 is not set # CONFIG_PATA_CS5530 is not set # CONFIG_PATA_CYPRESS is not set # CONFIG_PATA_EFAR is not set CONFIG_ATA_GENERIC=y # CONFIG_PATA_HPT366 is not set # CONFIG_PATA_HPT37X is not set # CONFIG_PATA_HPT3X2N is not set # CONFIG_PATA_HPT3X3 is not set # CONFIG_PATA_IT821X is not set # CONFIG_PATA_IT8213 is not set # CONFIG_PATA_JMICRON is not set # CONFIG_PATA_TRIFLEX is not set # CONFIG_PATA_MARVELL is not set # CONFIG_PATA_MPIIX is not set # CONFIG_PATA_OLDPIIX is not set # CONFIG_PATA_NETCELL is not set # CONFIG_PATA_NINJA32 is not set # CONFIG_PATA_NS87410 is not set # CONFIG_PATA_NS87415 is not set # CONFIG_PATA_OPTI is not set # CONFIG_PATA_OPTIDMA is not set # CONFIG_PATA_PDC2027X is not set # CONFIG_PATA_PDC_OLD is not set # CONFIG_PATA_RADISYS is not set # CONFIG_PATA_RDC is not set # CONFIG_PATA_RZ1000 is not set # CONFIG_PATA_SC1200 is not set # CONFIG_PATA_SERVERWORKS is not set # CONFIG_PATA_SIL680 is not set CONFIG_PATA_SIS=m # CONFIG_PATA_TOSHIBA is not set # CONFIG_PATA_VIA is not set # CONFIG_PATA_WINBOND is not set # CONFIG_PATA_PLATFORM is not set CONFIG_PATA_OCTEON_CF=y # CONFIG_PATA_SCH is not set CONFIG_MD=y CONFIG_BLK_DEV_MD=m CONFIG_MD_LINEAR=m CONFIG_MD_RAID0=m CONFIG_MD_RAID1=m CONFIG_MD_RAID10=m CONFIG_MD_RAID456=m CONFIG_MULTICORE_RAID456=y CONFIG_MD_RAID6_PQ=m CONFIG_ASYNC_RAID6_TEST=m CONFIG_MD_MULTIPATH=m CONFIG_MD_FAULTY=m CONFIG_BLK_DEV_DM=m CONFIG_DM_DEBUG=y CONFIG_DM_CRYPT=m CONFIG_DM_SNAPSHOT=m CONFIG_DM_MIRROR=m CONFIG_DM_LOG_USERSPACE=m CONFIG_DM_ZERO=m CONFIG_DM_MULTIPATH=m CONFIG_DM_MULTIPATH_QL=m CONFIG_DM_MULTIPATH_ST=m CONFIG_DM_DELAY=m CONFIG_DM_UEVENT=y CONFIG_FUSION=y # CONFIG_FUSION_SPI is not set # CONFIG_FUSION_FC is not set CONFIG_FUSION_SAS=y CONFIG_FUSION_MAX_SGE=128 CONFIG_FUSION_CTL=m CONFIG_FUSION_LOGGING=y # # IEEE 1394 (FireWire) support # # # You can enable one or both FireWire driver stacks. # # # The newer stack is recommended. # # CONFIG_FIREWIRE is not set # CONFIG_IEEE1394 is not set CONFIG_I2O=y CONFIG_I2O_LCT_NOTIFY_ON_CHANGES=y CONFIG_I2O_EXT_ADAPTEC=y CONFIG_I2O_EXT_ADAPTEC_DMA64=y # CONFIG_I2O_CONFIG is not set # CONFIG_I2O_BUS is not set # CONFIG_I2O_BLOCK is not set # CONFIG_I2O_SCSI is not set # CONFIG_I2O_PROC is not set CONFIG_NETDEVICES=y # CONFIG_DUMMY is not set CONFIG_BONDING=m # CONFIG_MACVLAN is not set # CONFIG_EQUALIZER is not set CONFIG_TUN=m # CONFIG_VETH is not set # CONFIG_ARCNET is not set CONFIG_PHYLIB=y # # MII PHY device drivers # # CONFIG_MARVELL_PHY is not set # CONFIG_DAVICOM_PHY is not set # CONFIG_QSEMI_PHY is not set # CONFIG_LXT_PHY is not set # CONFIG_CICADA_PHY is not set # CONFIG_VITESSE_PHY is not set # CONFIG_SMSC_PHY is not set # CONFIG_BROADCOM_PHY is not set # CONFIG_ICPLUS_PHY is not set # CONFIG_REALTEK_PHY is not set # CONFIG_NATIONAL_PHY is not set # CONFIG_STE10XP is not set # CONFIG_LSI_ET1011C_PHY is not set # CONFIG_FIXED_PHY is not set # CONFIG_MDIO_BITBANG is not set CONFIG_MDIO_OCTEON=y CONFIG_NET_ETHERNET=y CONFIG_MII=m # CONFIG_AX88796 is not set # CONFIG_HAPPYMEAL is not set # CONFIG_SUNGEM is not set # CONFIG_CASSINI is not set # CONFIG_NET_VENDOR_3COM is not set # CONFIG_SMC91X is not set # CONFIG_DM9000 is not set CONFIG_ETHOC=m # CONFIG_SMSC911X is not set # CONFIG_DNET is not set # CONFIG_NET_TULIP is not set # CONFIG_HP100 is not set # CONFIG_IBM_NEW_EMAC_ZMII is not set # CONFIG_IBM_NEW_EMAC_RGMII is not set # CONFIG_IBM_NEW_EMAC_TAH is not set # CONFIG_IBM_NEW_EMAC_EMAC4 is not set # CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set # CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set # CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set # CONFIG_NET_PCI is not set # CONFIG_B44 is not set # CONFIG_KS8842 is not set # CONFIG_KS8851_MLL is not set # CONFIG_ATL2 is not set CONFIG_OCTEON_MGMT_ETHERNET=y # CONFIG_NETDEV_1000 is not set # CONFIG_NETDEV_10000 is not set # CONFIG_TR is not set # CONFIG_WLAN is not set # # Enable WiMAX (Networking options) to see the WiMAX drivers # # # USB Network Adapters # # CONFIG_USB_CATC is not set # CONFIG_USB_KAWETH is not set # CONFIG_USB_PEGASUS is not set # CONFIG_USB_RTL8150 is not set # CONFIG_USB_USBNET is not set # CONFIG_WAN is not set # CONFIG_FDDI is not set # CONFIG_HIPPI is not set # CONFIG_PPP is not set # CONFIG_SLIP is not set # CONFIG_NET_FC is not set # CONFIG_NETCONSOLE is not set # CONFIG_NETPOLL is not set # CONFIG_NET_POLL_CONTROLLER is not set # CONFIG_VMXNET3 is not set # CONFIG_ISDN is not set # CONFIG_PHONE is not set # # Input device support # CONFIG_INPUT=y CONFIG_INPUT_FF_MEMLESS=m # CONFIG_INPUT_POLLDEV is not set # CONFIG_INPUT_SPARSEKMAP is not set # # Userland interfaces # CONFIG_INPUT_MOUSEDEV=y CONFIG_INPUT_MOUSEDEV_PSAUX=y CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 # CONFIG_INPUT_JOYDEV is not set CONFIG_INPUT_EVDEV=y CONFIG_INPUT_EVBUG=y # # Input Device Drivers # CONFIG_INPUT_KEYBOARD=y # CONFIG_KEYBOARD_ADP5588 is not set CONFIG_KEYBOARD_ATKBD=y # CONFIG_QT2160 is not set # CONFIG_KEYBOARD_LKKBD is not set # CONFIG_KEYBOARD_MAX7359 is not set # CONFIG_KEYBOARD_NEWTON is not set # CONFIG_KEYBOARD_OPENCORES is not set # CONFIG_KEYBOARD_STOWAWAY is not set # CONFIG_KEYBOARD_SUNKBD is not set # CONFIG_KEYBOARD_XTKBD is not set CONFIG_INPUT_MOUSE=y CONFIG_MOUSE_PS2=y CONFIG_MOUSE_PS2_ALPS=y CONFIG_MOUSE_PS2_LOGIPS2PP=y CONFIG_MOUSE_PS2_SYNAPTICS=y CONFIG_MOUSE_PS2_TRACKPOINT=y # CONFIG_MOUSE_PS2_ELANTECH is not set # CONFIG_MOUSE_PS2_SENTELIC is not set # CONFIG_MOUSE_PS2_TOUCHKIT is not set # CONFIG_MOUSE_SERIAL is not set # CONFIG_MOUSE_APPLETOUCH is not set # CONFIG_MOUSE_BCM5974 is not set # CONFIG_MOUSE_VSXXXAA is not set # CONFIG_MOUSE_SYNAPTICS_I2C is not set # CONFIG_INPUT_JOYSTICK is not set # CONFIG_INPUT_TABLET is not set # CONFIG_INPUT_TOUCHSCREEN is not set CONFIG_INPUT_MISC=y CONFIG_INPUT_PCSPKR=m # CONFIG_INPUT_ATI_REMOTE is not set # CONFIG_INPUT_ATI_REMOTE2 is not set # CONFIG_INPUT_KEYSPAN_REMOTE is not set # CONFIG_INPUT_POWERMATE is not set # CONFIG_INPUT_YEALINK is not set # CONFIG_INPUT_CM109 is not set # CONFIG_INPUT_UINPUT is not set # # Hardware I/O ports # CONFIG_SERIO=y CONFIG_SERIO_I8042=y CONFIG_SERIO_SERPORT=y # CONFIG_SERIO_PCIPS2 is not set CONFIG_SERIO_LIBPS2=y # CONFIG_SERIO_RAW is not set # CONFIG_SERIO_ALTERA_PS2 is not set # CONFIG_GAMEPORT is not set # # Character devices # CONFIG_VT=y CONFIG_CONSOLE_TRANSLATIONS=y CONFIG_VT_CONSOLE=y CONFIG_HW_CONSOLE=y # CONFIG_VT_HW_CONSOLE_BINDING is not set CONFIG_DEVKMEM=y # CONFIG_SERIAL_NONSTANDARD is not set # CONFIG_NOZOMI is not set # # Serial drivers # # CONFIG_SERIAL_8250 is not set # # Non-8250 serial port support # # CONFIG_SERIAL_JSM is not set CONFIG_UNIX98_PTYS=y # CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=256 # CONFIG_IPMI_HANDLER is not set CONFIG_HW_RANDOM=m # CONFIG_HW_RANDOM_TIMERIOMEM is not set CONFIG_HW_RANDOM_OCTEON=m # CONFIG_R3964 is not set # CONFIG_APPLICOM is not set # CONFIG_RAW_DRIVER is not set # CONFIG_TCG_TPM is not set CONFIG_DEVPORT=y CONFIG_I2C=y CONFIG_I2C_BOARDINFO=y CONFIG_I2C_COMPAT=y CONFIG_I2C_CHARDEV=m CONFIG_I2C_HELPER_AUTO=y # # I2C Hardware Bus support # # # PC SMBus host controller drivers # # CONFIG_I2C_ALI1535 is not set # CONFIG_I2C_ALI1563 is not set # CONFIG_I2C_ALI15X3 is not set # CONFIG_I2C_AMD756 is not set # CONFIG_I2C_AMD8111 is not set # CONFIG_I2C_I801 is not set # CONFIG_I2C_ISCH is not set # CONFIG_I2C_PIIX4 is not set # CONFIG_I2C_NFORCE2 is not set # CONFIG_I2C_SIS5595 is not set # CONFIG_I2C_SIS630 is not set # CONFIG_I2C_SIS96X is not set # CONFIG_I2C_VIA is not set # CONFIG_I2C_VIAPRO is not set # # I2C system bus drivers (mostly embedded / system-on-chip) # CONFIG_I2C_OCORES=m # CONFIG_I2C_SIMTEC is not set # # External I2C/SMBus adapter drivers # # CONFIG_I2C_PARPORT_LIGHT is not set # CONFIG_I2C_TAOS_EVM is not set # CONFIG_I2C_TINY_USB is not set # # Other I2C/SMBus bus drivers # # CONFIG_I2C_PCA_PLATFORM is not set # CONFIG_I2C_STUB is not set # # Miscellaneous I2C Chip support # CONFIG_SENSORS_TSL2550=m # CONFIG_I2C_DEBUG_CORE is not set # CONFIG_I2C_DEBUG_ALGO is not set # CONFIG_I2C_DEBUG_BUS is not set # CONFIG_I2C_DEBUG_CHIP is not set # CONFIG_SPI is not set # # PPS support # # CONFIG_PPS is not set # CONFIG_W1 is not set # CONFIG_POWER_SUPPLY is not set CONFIG_HWMON=y # CONFIG_HWMON_VID is not set # CONFIG_HWMON_DEBUG_CHIP is not set # # Native drivers # # CONFIG_SENSORS_AD7414 is not set # CONFIG_SENSORS_AD7418 is not set # CONFIG_SENSORS_ADM1021 is not set # CONFIG_SENSORS_ADM1025 is not set # CONFIG_SENSORS_ADM1026 is not set # CONFIG_SENSORS_ADM1029 is not set # CONFIG_SENSORS_ADM1031 is not set # CONFIG_SENSORS_ADM9240 is not set # CONFIG_SENSORS_ADT7462 is not set # CONFIG_SENSORS_ADT7470 is not set # CONFIG_SENSORS_ADT7473 is not set # CONFIG_SENSORS_ADT7475 is not set # CONFIG_SENSORS_ATXP1 is not set # CONFIG_SENSORS_DS1621 is not set # CONFIG_SENSORS_I5K_AMB is not set # CONFIG_SENSORS_F71805F is not set # CONFIG_SENSORS_F71882FG is not set # CONFIG_SENSORS_F75375S is not set # CONFIG_SENSORS_G760A is not set # CONFIG_SENSORS_GL518SM is not set # CONFIG_SENSORS_GL520SM is not set # CONFIG_SENSORS_IT87 is not set # CONFIG_SENSORS_LM63 is not set # CONFIG_SENSORS_LM73 is not set # CONFIG_SENSORS_LM75 is not set # CONFIG_SENSORS_LM77 is not set # CONFIG_SENSORS_LM78 is not set # CONFIG_SENSORS_LM80 is not set # CONFIG_SENSORS_LM83 is not set # CONFIG_SENSORS_LM85 is not set # CONFIG_SENSORS_LM87 is not set # CONFIG_SENSORS_LM90 is not set # CONFIG_SENSORS_LM92 is not set # CONFIG_SENSORS_LM93 is not set # CONFIG_SENSORS_LTC4215 is not set # CONFIG_SENSORS_LTC4245 is not set # CONFIG_SENSORS_LM95241 is not set # CONFIG_SENSORS_MAX1619 is not set # CONFIG_SENSORS_MAX6650 is not set # CONFIG_SENSORS_PC87360 is not set # CONFIG_SENSORS_PC87427 is not set # CONFIG_SENSORS_PCF8591 is not set # CONFIG_SENSORS_SIS5595 is not set # CONFIG_SENSORS_DME1737 is not set # CONFIG_SENSORS_SMSC47M1 is not set # CONFIG_SENSORS_SMSC47M192 is not set # CONFIG_SENSORS_SMSC47B397 is not set # CONFIG_SENSORS_ADS7828 is not set # CONFIG_SENSORS_AMC6821 is not set # CONFIG_SENSORS_THMC50 is not set # CONFIG_SENSORS_TMP401 is not set # CONFIG_SENSORS_TMP421 is not set # CONFIG_SENSORS_VIA686A is not set # CONFIG_SENSORS_VT1211 is not set # CONFIG_SENSORS_VT8231 is not set # CONFIG_SENSORS_W83781D is not set # CONFIG_SENSORS_W83791D is not set # CONFIG_SENSORS_W83792D is not set # CONFIG_SENSORS_W83793 is not set # CONFIG_SENSORS_W83L785TS is not set # CONFIG_SENSORS_W83L786NG is not set # CONFIG_SENSORS_W83627HF is not set # CONFIG_SENSORS_W83627EHF is not set # CONFIG_SENSORS_LIS3_I2C is not set # CONFIG_THERMAL is not set CONFIG_WATCHDOG=y # CONFIG_WATCHDOG_NOWAYOUT is not set # # Watchdog Device Drivers # # CONFIG_SOFT_WATCHDOG is not set # CONFIG_ALIM7101_WDT is not set # # PCI-based Watchdog Cards # # CONFIG_PCIPCWATCHDOG is not set # CONFIG_WDTPCI is not set # # USB-based Watchdog Cards # # CONFIG_USBPCWATCHDOG is not set CONFIG_SSB_POSSIBLE=y # # Sonics Silicon Backplane # # CONFIG_SSB is not set # # Multifunction device drivers # # CONFIG_MFD_CORE is not set # CONFIG_MFD_SM501 is not set # CONFIG_HTC_PASIC3 is not set # CONFIG_TWL4030_CORE is not set # CONFIG_MFD_TMIO is not set # CONFIG_PMIC_DA903X is not set # CONFIG_PMIC_ADP5520 is not set # CONFIG_MFD_WM8400 is not set # CONFIG_MFD_WM831X is not set # CONFIG_MFD_WM8350_I2C is not set # CONFIG_MFD_PCF50633 is not set # CONFIG_AB3100_CORE is not set # CONFIG_MFD_88PM8607 is not set # CONFIG_REGULATOR is not set CONFIG_MEDIA_SUPPORT=y # # Multimedia core support # # CONFIG_VIDEO_DEV is not set # CONFIG_DVB_CORE is not set # CONFIG_VIDEO_MEDIA is not set # # Multimedia drivers # CONFIG_IR_CORE=y CONFIG_VIDEO_IR=y # CONFIG_DAB is not set # # Graphics support # CONFIG_VGA_ARB=y # CONFIG_DRM is not set # CONFIG_VGASTATE is not set # CONFIG_VIDEO_OUTPUT_CONTROL is not set # CONFIG_FB is not set # CONFIG_BACKLIGHT_LCD_SUPPORT is not set # # Display device support # # CONFIG_DISPLAY_SUPPORT is not set # # Console display driver support # CONFIG_VGA_CONSOLE=y # CONFIG_VGACON_SOFT_SCROLLBACK is not set CONFIG_DUMMY_CONSOLE=y # CONFIG_SOUND is not set CONFIG_HID_SUPPORT=y CONFIG_HID=y # CONFIG_HIDRAW is not set # # USB Input Devices # CONFIG_USB_HID=m # CONFIG_HID_PID is not set # CONFIG_USB_HIDDEV is not set # # USB HID Boot Protocol drivers # # CONFIG_USB_KBD is not set # CONFIG_USB_MOUSE is not set # # Special HID drivers # # CONFIG_HID_A4TECH is not set # CONFIG_HID_APPLE is not set # CONFIG_HID_BELKIN is not set # CONFIG_HID_CHERRY is not set # CONFIG_HID_CHICONY is not set # CONFIG_HID_CYPRESS is not set # CONFIG_HID_DRAGONRISE is not set # CONFIG_HID_EZKEY is not set # CONFIG_HID_KYE is not set # CONFIG_HID_GYRATION is not set # CONFIG_HID_TWINHAN is not set # CONFIG_HID_KENSINGTON is not set # CONFIG_HID_LOGITECH is not set # CONFIG_HID_MICROSOFT is not set # CONFIG_HID_MONTEREY is not set # CONFIG_HID_NTRIG is not set # CONFIG_HID_PANTHERLORD is not set # CONFIG_HID_PETALYNX is not set # CONFIG_HID_SAMSUNG is not set # CONFIG_HID_SONY is not set # CONFIG_HID_SUNPLUS is not set # CONFIG_HID_GREENASIA is not set # CONFIG_HID_SMARTJOYPLUS is not set # CONFIG_HID_TOPSEED is not set # CONFIG_HID_THRUSTMASTER is not set # CONFIG_HID_ZEROPLUS is not set CONFIG_USB_SUPPORT=y CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB_ARCH_HAS_OHCI=y CONFIG_USB_ARCH_HAS_EHCI=y CONFIG_USB=m # CONFIG_USB_DEBUG is not set # CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set # # Miscellaneous USB options # # CONFIG_USB_DEVICEFS is not set CONFIG_USB_DEVICE_CLASS=y # CONFIG_USB_DYNAMIC_MINORS is not set # CONFIG_USB_OTG is not set # CONFIG_USB_OTG_WHITELIST is not set # CONFIG_USB_OTG_BLACKLIST_HUB is not set CONFIG_USB_MON=m # CONFIG_USB_WUSB is not set # CONFIG_USB_WUSB_CBAF is not set # # USB Host Controller Drivers # # CONFIG_USB_C67X00_HCD is not set # CONFIG_USB_XHCI_HCD is not set # CONFIG_USB_EHCI_HCD is not set # CONFIG_USB_OXU210HP_HCD is not set # CONFIG_USB_ISP116X_HCD is not set # CONFIG_USB_ISP1760_HCD is not set # CONFIG_USB_ISP1362_HCD is not set CONFIG_USB_OHCI_HCD=m # CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set # CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set CONFIG_USB_OHCI_LITTLE_ENDIAN=y # CONFIG_USB_UHCI_HCD is not set # CONFIG_USB_SL811_HCD is not set # CONFIG_USB_R8A66597_HCD is not set # CONFIG_USB_WHCI_HCD is not set # CONFIG_USB_HWA_HCD is not set # # Enable Host or Gadget support to see Inventra options # # # USB Device Class drivers # # CONFIG_USB_ACM is not set # CONFIG_USB_PRINTER is not set # CONFIG_USB_WDM is not set # CONFIG_USB_TMC is not set # # NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may # # # also be needed; see USB_STORAGE Help for more info # CONFIG_USB_STORAGE=m # CONFIG_USB_STORAGE_DEBUG is not set # CONFIG_USB_STORAGE_DATAFAB is not set # CONFIG_USB_STORAGE_FREECOM is not set # CONFIG_USB_STORAGE_ISD200 is not set # CONFIG_USB_STORAGE_USBAT is not set # CONFIG_USB_STORAGE_SDDR09 is not set # CONFIG_USB_STORAGE_SDDR55 is not set # CONFIG_USB_STORAGE_JUMPSHOT is not set # CONFIG_USB_STORAGE_ALAUDA is not set # CONFIG_USB_STORAGE_ONETOUCH is not set # CONFIG_USB_STORAGE_KARMA is not set # CONFIG_USB_STORAGE_CYPRESS_ATACB is not set # CONFIG_USB_LIBUSUAL is not set # # USB Imaging devices # # CONFIG_USB_MDC800 is not set # CONFIG_USB_MICROTEK is not set # # USB port drivers # # CONFIG_USB_SERIAL is not set # # USB Miscellaneous drivers # # CONFIG_USB_EMI62 is not set # CONFIG_USB_EMI26 is not set # CONFIG_USB_ADUTUX is not set # CONFIG_USB_SEVSEG is not set # CONFIG_USB_RIO500 is not set # CONFIG_USB_LEGOTOWER is not set # CONFIG_USB_LCD is not set # CONFIG_USB_BERRY_CHARGE is not set # CONFIG_USB_LED is not set # CONFIG_USB_CYPRESS_CY7C63 is not set # CONFIG_USB_CYTHERM is not set # CONFIG_USB_IDMOUSE is not set # CONFIG_USB_FTDI_ELAN is not set # CONFIG_USB_APPLEDISPLAY is not set # CONFIG_USB_LD is not set # CONFIG_USB_TRANCEVIBRATOR is not set # CONFIG_USB_IOWARRIOR is not set # CONFIG_USB_TEST is not set # CONFIG_USB_ISIGHTFW is not set # CONFIG_USB_VST is not set # CONFIG_USB_GADGET is not set # # OTG and related infrastructure # # CONFIG_NOP_USB_XCEIV is not set # CONFIG_UWB is not set CONFIG_MMC=y CONFIG_MMC_DEBUG=y CONFIG_MMC_UNSAFE_RESUME=y # # MMC/SD/SDIO Card Drivers # CONFIG_MMC_BLOCK=y CONFIG_MMC_BLOCK_BOUNCE=y CONFIG_SDIO_UART=m CONFIG_MMC_TEST=m # # MMC/SD/SDIO Host Controller Drivers # CONFIG_MMC_SDHCI=m CONFIG_MMC_SDHCI_PCI=m CONFIG_MMC_RICOH_MMC=m CONFIG_MMC_SDHCI_PLTFM=m # CONFIG_MMC_AT91 is not set # CONFIG_MMC_ATMELMCI is not set CONFIG_MMC_TIFM_SD=m CONFIG_MMC_CB710=m CONFIG_MMC_VIA_SDMMC=m CONFIG_MEMSTICK=m # CONFIG_MEMSTICK_DEBUG is not set # # MemoryStick drivers # # CONFIG_MEMSTICK_UNSAFE_RESUME is not set # CONFIG_MSPRO_BLOCK is not set # # MemoryStick Host Controller Drivers # # CONFIG_MEMSTICK_TIFM_MS is not set # CONFIG_MEMSTICK_JMICRON_38X is not set # CONFIG_NEW_LEDS is not set # CONFIG_ACCESSIBILITY is not set # CONFIG_INFINIBAND is not set CONFIG_RTC_LIB=y # CONFIG_RTC_CLASS is not set # CONFIG_DMADEVICES is not set # CONFIG_AUXDISPLAY is not set # CONFIG_UIO is not set # # TI VLYNQ # CONFIG_STAGING=y # CONFIG_STAGING_EXCLUDE_BUILD is not set # CONFIG_USB_IP_COMMON is not set # CONFIG_ECHO is not set # CONFIG_COMEDI is not set # CONFIG_ASUS_OLED is not set # CONFIG_ALTERA_PCIE_CHDMA is not set # CONFIG_INPUT_MIMIO is not set # CONFIG_TRANZPORT is not set # # Qualcomm MSM Camera And Video # # # Camera Sensor Selection # # CONFIG_INPUT_GPIO is not set # CONFIG_POHMELFS is not set # CONFIG_B3DFG is not set # CONFIG_IDE_PHISON is not set # CONFIG_PLAN9AUTH is not set CONFIG_OCTEON_ETHERNET=y # CONFIG_VME_BUS is not set # # RAR Register Driver # # CONFIG_RAR_REGISTER is not set # CONFIG_IIO is not set # CONFIG_RAMZSWAP is not set # CONFIG_STRIP is not set # # File systems # CONFIG_EXT2_FS=y # CONFIG_EXT2_FS_XATTR is not set # CONFIG_EXT2_FS_XIP is not set CONFIG_EXT3_FS=y # CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set CONFIG_EXT3_FS_XATTR=y # CONFIG_EXT3_FS_POSIX_ACL is not set # CONFIG_EXT3_FS_SECURITY is not set CONFIG_EXT4_FS=m CONFIG_EXT4_FS_XATTR=y # CONFIG_EXT4_FS_POSIX_ACL is not set # CONFIG_EXT4_FS_SECURITY is not set # CONFIG_EXT4_DEBUG is not set CONFIG_JBD=y # CONFIG_JBD_DEBUG is not set CONFIG_JBD2=m # CONFIG_JBD2_DEBUG is not set CONFIG_FS_MBCACHE=y # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set CONFIG_FS_POSIX_ACL=y # CONFIG_XFS_FS is not set # CONFIG_GFS2_FS is not set # CONFIG_OCFS2_FS is not set # CONFIG_BTRFS_FS is not set # CONFIG_NILFS2_FS is not set CONFIG_FILE_LOCKING=y CONFIG_FSNOTIFY=y CONFIG_DNOTIFY=y CONFIG_INOTIFY=y CONFIG_INOTIFY_USER=y # CONFIG_QUOTA is not set # CONFIG_AUTOFS_FS is not set # CONFIG_AUTOFS4_FS is not set CONFIG_FUSE_FS=m CONFIG_CUSE=m # # Caches # CONFIG_FSCACHE=m # CONFIG_FSCACHE_STATS is not set # CONFIG_FSCACHE_HISTOGRAM is not set # CONFIG_FSCACHE_DEBUG is not set # CONFIG_FSCACHE_OBJECT_LIST is not set CONFIG_CACHEFILES=m # CONFIG_CACHEFILES_DEBUG is not set # CONFIG_CACHEFILES_HISTOGRAM is not set # # CD-ROM/DVD Filesystems # # CONFIG_ISO9660_FS is not set # CONFIG_UDF_FS is not set # # DOS/FAT/NT Filesystems # # CONFIG_MSDOS_FS is not set # CONFIG_VFAT_FS is not set # CONFIG_NTFS_FS is not set # # Pseudo filesystems # CONFIG_PROC_FS=y # CONFIG_PROC_KCORE is not set CONFIG_PROC_SYSCTL=y CONFIG_PROC_PAGE_MONITOR=y CONFIG_SYSFS=y # CONFIG_TMPFS is not set # CONFIG_HUGETLBFS is not set # CONFIG_HUGETLB_PAGE is not set # CONFIG_CONFIGFS_FS is not set CONFIG_MISC_FILESYSTEMS=y # CONFIG_ADFS_FS is not set # CONFIG_AFFS_FS is not set # CONFIG_HFS_FS is not set # CONFIG_HFSPLUS_FS is not set # CONFIG_BEFS_FS is not set # CONFIG_BFS_FS is not set # CONFIG_EFS_FS is not set CONFIG_JFFS2_FS=m CONFIG_JFFS2_FS_DEBUG=0 CONFIG_JFFS2_FS_WRITEBUFFER=y # CONFIG_JFFS2_FS_WBUF_VERIFY is not set CONFIG_JFFS2_SUMMARY=y CONFIG_JFFS2_FS_XATTR=y CONFIG_JFFS2_FS_POSIX_ACL=y CONFIG_JFFS2_FS_SECURITY=y CONFIG_JFFS2_COMPRESSION_OPTIONS=y CONFIG_JFFS2_ZLIB=y # CONFIG_JFFS2_LZO is not set CONFIG_JFFS2_RTIME=y # CONFIG_JFFS2_RUBIN is not set # CONFIG_JFFS2_CMODE_NONE is not set CONFIG_JFFS2_CMODE_PRIORITY=y # CONFIG_JFFS2_CMODE_SIZE is not set # CONFIG_JFFS2_CMODE_FAVOURLZO is not set # CONFIG_UBIFS_FS is not set # CONFIG_CRAMFS is not set CONFIG_SQUASHFS=y CONFIG_SQUASHFS_EMBEDDED=y CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 # CONFIG_VXFS_FS is not set CONFIG_MINIX_FS=y # CONFIG_OMFS_FS is not set # CONFIG_HPFS_FS is not set # CONFIG_QNX4FS_FS is not set # CONFIG_ROMFS_FS is not set # CONFIG_SYSV_FS is not set # CONFIG_UFS_FS is not set CONFIG_NETWORK_FILESYSTEMS=y # CONFIG_NFS_FS is not set # CONFIG_NFSD is not set # CONFIG_SMB_FS is not set # CONFIG_CIFS is not set # CONFIG_NCP_FS is not set # CONFIG_CODA_FS is not set # CONFIG_AFS_FS is not set # # Partition Types # CONFIG_PARTITION_ADVANCED=y # CONFIG_ACORN_PARTITION is not set # CONFIG_OSF_PARTITION is not set # CONFIG_AMIGA_PARTITION is not set # CONFIG_ATARI_PARTITION is not set # CONFIG_MAC_PARTITION is not set CONFIG_MSDOS_PARTITION=y # CONFIG_BSD_DISKLABEL is not set # CONFIG_MINIX_SUBPARTITION is not set # CONFIG_SOLARIS_X86_PARTITION is not set # CONFIG_UNIXWARE_DISKLABEL is not set # CONFIG_LDM_PARTITION is not set # CONFIG_SGI_PARTITION is not set # CONFIG_ULTRIX_PARTITION is not set # CONFIG_SUN_PARTITION is not set # CONFIG_KARMA_PARTITION is not set # CONFIG_EFI_PARTITION is not set # CONFIG_SYSV68_PARTITION is not set CONFIG_NLS=m CONFIG_NLS_DEFAULT="iso8859-1" # CONFIG_NLS_CODEPAGE_437 is not set # CONFIG_NLS_CODEPAGE_737 is not set # CONFIG_NLS_CODEPAGE_775 is not set # CONFIG_NLS_CODEPAGE_850 is not set # CONFIG_NLS_CODEPAGE_852 is not set # CONFIG_NLS_CODEPAGE_855 is not set # CONFIG_NLS_CODEPAGE_857 is not set # CONFIG_NLS_CODEPAGE_860 is not set # CONFIG_NLS_CODEPAGE_861 is not set # CONFIG_NLS_CODEPAGE_862 is not set # CONFIG_NLS_CODEPAGE_863 is not set # CONFIG_NLS_CODEPAGE_864 is not set # CONFIG_NLS_CODEPAGE_865 is not set # CONFIG_NLS_CODEPAGE_866 is not set # CONFIG_NLS_CODEPAGE_869 is not set # CONFIG_NLS_CODEPAGE_936 is not set # CONFIG_NLS_CODEPAGE_950 is not set # CONFIG_NLS_CODEPAGE_932 is not set # CONFIG_NLS_CODEPAGE_949 is not set # CONFIG_NLS_CODEPAGE_874 is not set # CONFIG_NLS_ISO8859_8 is not set # CONFIG_NLS_CODEPAGE_1250 is not set # CONFIG_NLS_CODEPAGE_1251 is not set # CONFIG_NLS_ASCII is not set # CONFIG_NLS_ISO8859_1 is not set # CONFIG_NLS_ISO8859_2 is not set # CONFIG_NLS_ISO8859_3 is not set # CONFIG_NLS_ISO8859_4 is not set # CONFIG_NLS_ISO8859_5 is not set # CONFIG_NLS_ISO8859_6 is not set # CONFIG_NLS_ISO8859_7 is not set # CONFIG_NLS_ISO8859_9 is not set # CONFIG_NLS_ISO8859_13 is not set # CONFIG_NLS_ISO8859_14 is not set # CONFIG_NLS_ISO8859_15 is not set # CONFIG_NLS_KOI8_R is not set # CONFIG_NLS_KOI8_U is not set # CONFIG_NLS_UTF8 is not set # CONFIG_DLM is not set # # Kernel hacking # CONFIG_TRACE_IRQFLAGS_SUPPORT=y # CONFIG_PRINTK_TIME is not set CONFIG_ENABLE_WARN_DEPRECATED=y CONFIG_ENABLE_MUST_CHECK=y CONFIG_FRAME_WARN=2048 # CONFIG_MAGIC_SYSRQ is not set # CONFIG_STRIP_ASM_SYMS is not set # CONFIG_UNUSED_SYMBOLS is not set CONFIG_DEBUG_FS=y # CONFIG_HEADERS_CHECK is not set # CONFIG_DEBUG_KERNEL is not set # CONFIG_SLUB_DEBUG_ON is not set # CONFIG_SLUB_STATS is not set # CONFIG_DEBUG_MEMORY_INIT is not set CONFIG_RCU_CPU_STALL_DETECTOR=y # CONFIG_SYSCTL_SYSCALL_CHECK is not set CONFIG_HAVE_FUNCTION_TRACER=y CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y CONFIG_HAVE_DYNAMIC_FTRACE=y CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y CONFIG_TRACING_SUPPORT=y # CONFIG_FTRACE is not set # CONFIG_DYNAMIC_DEBUG is not set # CONFIG_SAMPLES is not set CONFIG_HAVE_ARCH_KGDB=y CONFIG_EARLY_PRINTK=y # CONFIG_CMDLINE_BOOL is not set # # Security options # # CONFIG_KEYS is not set # CONFIG_SECURITY is not set # CONFIG_SECURITYFS is not set # CONFIG_DEFAULT_SECURITY_SELINUX is not set # CONFIG_DEFAULT_SECURITY_SMACK is not set # CONFIG_DEFAULT_SECURITY_TOMOYO is not set CONFIG_DEFAULT_SECURITY_DAC=y CONFIG_DEFAULT_SECURITY="" CONFIG_XOR_BLOCKS=m CONFIG_ASYNC_CORE=m CONFIG_ASYNC_MEMCPY=m CONFIG_ASYNC_XOR=m CONFIG_ASYNC_PQ=m CONFIG_ASYNC_RAID6_RECOV=m CONFIG_CRYPTO=y # # Crypto core or helper # # CONFIG_CRYPTO_FIPS is not set CONFIG_CRYPTO_ALGAPI=y CONFIG_CRYPTO_ALGAPI2=y CONFIG_CRYPTO_AEAD=m CONFIG_CRYPTO_AEAD2=y CONFIG_CRYPTO_BLKCIPHER=m CONFIG_CRYPTO_BLKCIPHER2=y CONFIG_CRYPTO_HASH=y CONFIG_CRYPTO_HASH2=y CONFIG_CRYPTO_RNG=m CONFIG_CRYPTO_RNG2=y CONFIG_CRYPTO_PCOMP=y CONFIG_CRYPTO_MANAGER=m CONFIG_CRYPTO_MANAGER2=y # CONFIG_CRYPTO_GF128MUL is not set # CONFIG_CRYPTO_NULL is not set CONFIG_CRYPTO_WORKQUEUE=y # CONFIG_CRYPTO_CRYPTD is not set CONFIG_CRYPTO_AUTHENC=m # CONFIG_CRYPTO_TEST is not set # # Authenticated Encryption with Associated Data # # CONFIG_CRYPTO_CCM is not set # CONFIG_CRYPTO_GCM is not set # CONFIG_CRYPTO_SEQIV is not set # # Block modes # CONFIG_CRYPTO_CBC=m # CONFIG_CRYPTO_CTR is not set # CONFIG_CRYPTO_CTS is not set # CONFIG_CRYPTO_ECB is not set # CONFIG_CRYPTO_LRW is not set # CONFIG_CRYPTO_PCBC is not set # CONFIG_CRYPTO_XTS is not set # # Hash modes # CONFIG_CRYPTO_HMAC=m # CONFIG_CRYPTO_XCBC is not set # CONFIG_CRYPTO_VMAC is not set # # Digest # # CONFIG_CRYPTO_CRC32C is not set # CONFIG_CRYPTO_GHASH is not set # CONFIG_CRYPTO_MD4 is not set CONFIG_CRYPTO_MD5=y # CONFIG_CRYPTO_MICHAEL_MIC is not set # CONFIG_CRYPTO_RMD128 is not set # CONFIG_CRYPTO_RMD160 is not set # CONFIG_CRYPTO_RMD256 is not set # CONFIG_CRYPTO_RMD320 is not set CONFIG_CRYPTO_SHA1=m # CONFIG_CRYPTO_SHA256 is not set # CONFIG_CRYPTO_SHA512 is not set # CONFIG_CRYPTO_TGR192 is not set # CONFIG_CRYPTO_WP512 is not set # # Ciphers # CONFIG_CRYPTO_AES=m # CONFIG_CRYPTO_ANUBIS is not set # CONFIG_CRYPTO_ARC4 is not set # CONFIG_CRYPTO_BLOWFISH is not set # CONFIG_CRYPTO_CAMELLIA is not set # CONFIG_CRYPTO_CAST5 is not set # CONFIG_CRYPTO_CAST6 is not set CONFIG_CRYPTO_DES=m # CONFIG_CRYPTO_FCRYPT is not set # CONFIG_CRYPTO_KHAZAD is not set # CONFIG_CRYPTO_SALSA20 is not set # CONFIG_CRYPTO_SEED is not set # CONFIG_CRYPTO_SERPENT is not set # CONFIG_CRYPTO_TEA is not set # CONFIG_CRYPTO_TWOFISH is not set # # Compression # CONFIG_CRYPTO_DEFLATE=m # CONFIG_CRYPTO_ZLIB is not set # CONFIG_CRYPTO_LZO is not set # # Random Number Generation # CONFIG_CRYPTO_ANSI_CPRNG=m CONFIG_CRYPTO_HW=y # CONFIG_CRYPTO_DEV_HIFN_795X is not set # CONFIG_BINARY_PRINTF is not set # # Library routines # CONFIG_BITREVERSE=y CONFIG_GENERIC_FIND_LAST_BIT=y # CONFIG_CRC_CCITT is not set CONFIG_CRC16=m # CONFIG_CRC_T10DIF is not set # CONFIG_CRC_ITU_T is not set CONFIG_CRC32=y # CONFIG_CRC7 is not set # CONFIG_LIBCRC32C is not set CONFIG_ZLIB_INFLATE=y CONFIG_ZLIB_DEFLATE=m CONFIG_DECOMPRESS_GZIP=y CONFIG_REED_SOLOMON=m CONFIG_REED_SOLOMON_DEC16=y CONFIG_HAS_IOMEM=y CONFIG_HAS_IOPORT=y CONFIG_HAS_DMA=y CONFIG_NLATTR=y --cN0A5YokcrYPGsSB Content-Type: text/plain; charset=us-ascii Content-Disposition: attachment; filename="gcc-mips.txt" #define __DBL_MIN_EXP__ (-1021) #define __HQ_FBIT__ 15 #define __SFRACT_IBIT__ 0 #define __FLT_MIN__ 1.17549435e-38F #define __UFRACT_MAX__ 0XFFFFP-16UR #define __DQ_FBIT__ 63 #define __ULFRACT_FBIT__ 32 #define __SACCUM_EPSILON__ 0x1P-7HK #define __CHAR_BIT__ 8 #define __USQ_IBIT__ 0 #define __ACCUM_FBIT__ 15 #define R3000 1 #define __USFRACT_FBIT__ 8 #define __ULLFRACT_MAX__ 0XFFFFFFFFFFFFFFFFP-64ULLR #define __WCHAR_MAX__ 2147483647 #define __LACCUM_IBIT__ 32 #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 1 #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 1 #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 1 #define __DBL_DENORM_MIN__ 4.9406564584124654e-324 #define __FLT_EVAL_METHOD__ 0 #define __unix__ 1 #define __LLACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LLK #define __FRACT_FBIT__ 15 #define _MIPS_ISA _MIPS_ISA_MIPS1 #define __UACCUM_FBIT__ 16 #define __LANGUAGE_C 1 #define __DBL_MIN_10_EXP__ (-307) #define __FINITE_MATH_ONLY__ 0 #define _MIPS_TUNE "mips1" #define __LFRACT_IBIT__ 0 #define __GNUC_PATCHLEVEL__ 3 #define __LFRACT_MAX__ 0X7FFFFFFFP-31LR #define __DEC64_MAX_EXP__ 385 #define _ABIO32 1 #define __SA_FBIT__ 15 #define __SHRT_MAX__ 32767 #define __LDBL_MAX__ 1.7976931348623157e+308L #define __FRACT_MAX__ 0X7FFFP-15R #define __UFRACT_FBIT__ 16 #define __UFRACT_MIN__ 0.0UR #define __mips_abicalls 1 #define __LANGUAGE_C__ 1 #define __UINTMAX_TYPE__ long long unsigned int #define __LLFRACT_EPSILON__ 0x1P-63LLR #define __linux 1 #define __DEC32_EPSILON__ 1E-6DF #define __unix 1 #define __ULFRACT_MAX__ 0XFFFFFFFFP-32ULR #define __TA_IBIT__ 64 #define __LDBL_MAX_EXP__ 1024 #define __MIPSEL__ 1 #define __linux__ 1 #define __ULLFRACT_MIN__ 0.0ULLR #define __SCHAR_MAX__ 127 #define __DBL_DIG__ 15 #define __LLACCUM_MIN__ (-0X1P31LLK-0X1P31LLK) #define __SQ_FBIT__ 31 #define __SIZEOF_POINTER__ 4 #define __USACCUM_IBIT__ 8 #define __USER_LABEL_PREFIX__ #define __STDC_HOSTED__ 1 #define __LDBL_HAS_INFINITY__ 1 #define __LFRACT_MIN__ (-0.5LR-0.5LR) #define __mips_fpr 32 #define __HA_IBIT__ 8 #define __TQ_IBIT__ 0 #define __FLT_EPSILON__ 1.19209290e-7F #define __mips__ 1 #define __USFRACT_IBIT__ 0 #define __LDBL_MIN__ 2.2250738585072014e-308L #define __FRACT_MIN__ (-0.5R-0.5R) #define __DEC32_MAX__ 9.999999E96DF #define __DA_IBIT__ 32 #define MIPSEL 1 #define __UQQ_FBIT__ 8 #define __SIZEOF_LONG__ 4 #define __UACCUM_MAX__ 0XFFFFFFFFP-16UK #define __DECIMAL_DIG__ 17 #define __LFRACT_EPSILON__ 0x1P-31LR #define __ULFRACT_MIN__ 0.0ULR #define __gnu_linux__ 1 #define __LDBL_HAS_QUIET_NAN__ 1 #define __ULACCUM_IBIT__ 32 #define __UACCUM_EPSILON__ 0x1P-16UK #define __GNUC__ 4 #define __ULLACCUM_MAX__ 0XFFFFFFFFFFFFFFFFP-32ULLK #define __HQ_IBIT__ 0 #define __FLT_HAS_DENORM__ 1 #define __SIZEOF_LONG_DOUBLE__ 8 #define _R3000 1 #define __BIGGEST_ALIGNMENT__ 8 #define __DQ_IBIT__ 0 #define __DBL_MAX__ 1.7976931348623157e+308 #define __ULFRACT_IBIT__ 0 #define __DBL_HAS_INFINITY__ 1 #define __ACCUM_IBIT__ 16 #define __DEC32_MIN_EXP__ (-94) #define __LACCUM_MAX__ 0X7FFFFFFFFFFFFFFFP-31LK #define __LDBL_HAS_DENORM__ 1 #define __DEC128_MAX__ 9.999999999999999999999999999999999E6144DL #define __DEC32_MIN__ 1E-95DF #define __ACCUM_MAX__ 0X7FFFFFFFP-15K #define __DBL_MAX_EXP__ 1024 #define __USACCUM_EPSILON__ 0x1P-8UHK #define __R3000__ 1 #define __DEC128_EPSILON__ 1E-33DL #define __SFRACT_MAX__ 0X7FP-7HR #define __FRACT_IBIT__ 0 #define __UACCUM_MIN__ 0.0UK #define mips 1 #define __UACCUM_IBIT__ 16 #define __LONG_LONG_MAX__ 9223372036854775807LL #define __SIZEOF_SIZE_T__ 4 #define __ULACCUM_MAX__ 0XFFFFFFFFFFFFFFFFP-32ULK #define _MIPS_ARCH_MIPS1 1 #define __SIZEOF_WINT_T__ 4 #define __SA_IBIT__ 16 #define __ULLACCUM_MIN__ 0.0ULLK #define __GXX_ABI_VERSION 1002 #define __UTA_FBIT__ 64 #define __FLT_MIN_EXP__ (-125) #define __USFRACT_MAX__ 0XFFP-8UHR #define __UFRACT_IBIT__ 0 #define _MIPSEL 1 #define __DBL_MIN__ 2.2250738585072014e-308 #define _MIPS_ARCH "mips1" #define __LACCUM_MIN__ (-0X1P31LK-0X1P31LK) #define __ULLACCUM_FBIT__ 32 #define __ULLFRACT_EPSILON__ 0x1P-64ULLR #define __DEC128_MIN__ 1E-6143DL #define __REGISTER_PREFIX__ #define __DBL_HAS_DENORM__ 1 #define __ACCUM_MIN__ (-0X1P15K-0X1P15K) #define __SQ_IBIT__ 0 #define __UHA_FBIT__ 8 #define __NO_INLINE__ 1 #define __SFRACT_MIN__ (-0.5HR-0.5HR) #define __R3000 1 #define __UTQ_FBIT__ 128 #define __FLT_MANT_DIG__ 24 #define __VERSION__ "4.4.3" #define __ULLFRACT_FBIT__ 64 #define __FRACT_EPSILON__ 0x1P-15R #define __ULACCUM_MIN__ 0.0ULK #define __UDA_FBIT__ 32 #define __LLACCUM_EPSILON__ 0x1P-31LLK #define _MIPS_TUNE_MIPS1 1 #define __USFRACT_MIN__ 0.0UHR #define __UQQ_IBIT__ 0 #define __DEC64_EPSILON__ 1E-15DD #define __DEC128_MIN_EXP__ (-6142) #define __UHQ_FBIT__ 16 #define __LLACCUM_FBIT__ 31 #define unix 1 #define __SIZE_TYPE__ unsigned int #define __UDQ_FBIT__ 64 #define __ELF__ 1 #define __ULFRACT_EPSILON__ 0x1P-32ULR #define __LLFRACT_FBIT__ 63 #define __FLT_RADIX__ 2 #define __LDBL_EPSILON__ 2.2204460492503131e-16L #define __SACCUM_MAX__ 0X7FFFP-7HK #define __SIZEOF_PTRDIFF_T__ 4 #define __LACCUM_EPSILON__ 0x1P-31LK #define __DEC32_SUBNORMAL_MIN__ 0.000001E-95DF #define _MIPS_SZPTR 32 #define __USACCUM_MAX__ 0XFFFFP-8UHK #define __SFRACT_EPSILON__ 0x1P-7HR #define __FLT_HAS_QUIET_NAN__ 1 #define __FLT_MAX_10_EXP__ 38 #define __LONG_MAX__ 2147483647L #define __DEC128_SUBNORMAL_MIN__ 0.000000000000000000000000000000001E-6143DL #define __FLT_HAS_INFINITY__ 1 #define __USA_FBIT__ 16 #define __DEC64_MAX__ 9.999999999999999E384DD #define __CHAR16_TYPE__ short unsigned int #define __DEC64_MANT_DIG__ 16 #define __SACCUM_FBIT__ 7 #define _mips 1 #define __SIZEOF_INT__ 4 #define __DEC32_MAX_EXP__ 97 #define __QQ_FBIT__ 7 #define linux 1 #define __UTA_IBIT__ 64 #define _MIPS_SZINT 32 #define __LDBL_MANT_DIG__ 53 #define __SFRACT_FBIT__ 7 #define __SACCUM_MIN__ (-0X1P7HK-0X1P7HK) #define __DBL_HAS_QUIET_NAN__ 1 #define __MIPSEL 1 #define __WCHAR_TYPE__ int #define __SIZEOF_FLOAT__ 4 #define __USQ_FBIT__ 32 #define __pic__ 1 #define __DEC64_MIN_EXP__ (-382) #define __ULLACCUM_IBIT__ 32 #define __FLT_DIG__ 6 #define __INT_MAX__ 2147483647 #define __LACCUM_FBIT__ 31 #define __USACCUM_MIN__ 0.0UHK #define __UHA_IBIT__ 8 #define __FLT_MAX_EXP__ 128 #define __UTQ_IBIT__ 0 #define _MIPS_SIM _ABIO32 #define __DBL_MANT_DIG__ 53 #define __DEC64_MIN__ 1E-383DD #define __WINT_TYPE__ unsigned int #define __SIZEOF_SHORT__ 2 #define __ULLFRACT_IBIT__ 0 #define __LDBL_MIN_EXP__ (-1021) #define _MIPS_FPSET 16 #define __UDA_IBIT__ 32 #define __LFRACT_FBIT__ 31 #define __LDBL_MAX_10_EXP__ 308 #define __DBL_EPSILON__ 2.2204460492503131e-16 #define __SIZEOF_WCHAR_T__ 4 #define __LLFRACT_MAX__ 0X7FFFFFFFFFFFFFFFP-63LLR #define __TQ_FBIT__ 127 #define __ULLACCUM_EPSILON__ 0x1P-32ULLK #define __UHQ_IBIT__ 0 #define __LLACCUM_IBIT__ 32 #define __DEC_EVAL_METHOD__ 2 #define __TA_FBIT__ 63 #define __UDQ_IBIT__ 0 #define __ACCUM_EPSILON__ 0x1P-15K #define __INTMAX_MAX__ 9223372036854775807LL #define __FLT_DENORM_MIN__ 1.40129846e-45F #define __LLFRACT_IBIT__ 0 #define __PIC__ 1 #define __CHAR32_TYPE__ unsigned int #define __FLT_MAX__ 3.40282347e+38F #define LANGUAGE_C 1 #define __USACCUM_FBIT__ 8 #define __SIZEOF_DOUBLE__ 8 #define __FLT_MIN_10_EXP__ (-37) #define __UFRACT_EPSILON__ 0x1P-16UR #define __INTMAX_TYPE__ long long int #define _LANGUAGE_C 1 #define __DEC128_MAX_EXP__ 6145 #define __GNUC_MINOR__ 4 #define __DEC32_MANT_DIG__ 7 #define __HA_FBIT__ 7 #define __DBL_MAX_10_EXP__ 308 #define __LDBL_DENORM_MIN__ 4.9406564584124654e-324L #define __STDC__ 1 #define __mips_hard_float 1 #define __PTRDIFF_TYPE__ int #define __LLFRACT_MIN__ (-0.5LLR-0.5LLR) #define __mips 1 #define __DA_FBIT__ 31 #define _MIPS_SZLONG 32 #define __USA_IBIT__ 16 #define __DEC64_SUBNORMAL_MIN__ 0.000000000000001E-383DD #define __DEC128_MANT_DIG__ 34 #define __LDBL_MIN_10_EXP__ (-307) #define __SIZEOF_LONG_LONG__ 8 #define __ULACCUM_EPSILON__ 0x1P-32ULK #define __SACCUM_IBIT__ 8 #define __LDBL_DIG__ 15 #define __GNUC_GNU_INLINE__ 1 #define __USFRACT_EPSILON__ 0x1P-8UHR #define __ULACCUM_FBIT__ 32 #define __QQ_IBIT__ 0 --cN0A5YokcrYPGsSB-- From David.Daney@caviumnetworks.com Mon Feb 22 22:24:55 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 22 Feb 2010 22:24:58 +0100 (CET) Received: from mail3.caviumnetworks.com ([12.108.191.235]:1741 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492324Ab0BVVYz (ORCPT ); Mon, 22 Feb 2010 22:24:55 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Mon, 22 Feb 2010 13:25:04 -0800 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Mon, 22 Feb 2010 13:24:32 -0800 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Mon, 22 Feb 2010 13:24:32 -0800 Message-ID: <4B82F610.8070105@caviumnetworks.com> Date: Mon, 22 Feb 2010 13:24:32 -0800 From: David Daney User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.9.1.7) Gecko/20100120 Fedora/3.0.1-1.fc12 Thunderbird/3.0.1 MIME-Version: 1.0 To: Andreas Barth CC: linux-mips@linux-mips.org Subject: Re: Problems and workarounds while building octeon kernels References: <20100220175125.GQ27216@mails.so.argh.org> In-Reply-To: <20100220175125.GQ27216@mails.so.argh.org> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 22 Feb 2010 21:24:32.0340 (UTC) FILETIME=[6C9AC940:01CAB405] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25988 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips On 02/20/2010 09:51 AM, Andreas Barth wrote: > Hi, > > I tried to build an recent linux 2.6.33-rc something in an unstable > Debian chroot. I had the following issues (plus workarounds / fixes) - > please don't hesitate to ask me if you have further questions. > I have a questions: * Were you able to produce a *bootable* kernel after your workarounds? * What did your make invocation look like? The reason I ask it that you are using a compiler that defaults to little-endian and 32-bit. Unless you did something to override these defaults, I would be surprised if you obtained something bootable. David Daney > > error: > arch/mips/cavium-octeon/built-in.o: In function `prom_init': > (.init.text+0x974): undefined reference to `early_serial_setup' > arch/mips/cavium-octeon/built-in.o: In function `prom_init': > (.init.text+0x974): relocation truncated to fit: R_MIPS_26 against `early_serial_setup' > arch/mips/cavium-octeon/built-in.o: In function `flash_init': > > fix: enabled configuration for serial console support > > > error: > flash_setup.c:(.init.text+0x12dc): undefined reference to `simple_map_init' > flash_setup.c:(.init.text+0x12dc): relocation truncated to fit: R_MIPS_26 against `simple_map_init' > flash_setup.c:(.init.text+0x12ec): undefined reference to `do_map_probe' > flash_setup.c:(.init.text+0x12ec): relocation truncated to fit: R_MIPS_26 against `do_map_probe' > flash_setup.c:(.init.text+0x1314): undefined reference to `parse_mtd_partitions' > flash_setup.c:(.init.text+0x1314): relocation truncated to fit: R_MIPS_26 against `parse_mtd_partitions' > flash_setup.c:(.init.text+0x1330): undefined reference to `add_mtd_partitions' > flash_setup.c:(.init.text+0x1330): relocation truncated to fit: R_MIPS_26 against `add_mtd_partitions' > flash_setup.c:(.init.text+0x1340): undefined reference to `add_mtd_device' > flash_setup.c:(.init.text+0x1340): relocation truncated to fit: R_MIPS_26 against `add_mtd_device' > > fix: set drivers/mtd to y (instead of m) > > > > error: > arch/mips/cavium-octeon/built-in.o: In function `sched_clock': > (.text.sched_clock+0x24): undefined reference to `__lshrti3' > arch/mips/cavium-octeon/built-in.o: In function `sched_clock': > (.text.sched_clock+0x24): relocation truncated to fit: R_MIPS_26 against `__lshrti3' > > workaround: in arch/mips/cavium-octeon/csrc-octeon.c > #if (__GNUC__< 4) || ((__GNUC__ == 4)&& (__GNUC_MINOR__<= 3)) > replaced by something that always uses "the ugly way" > > > ERROR: "i8253_lock" [drivers/input/misc/pcspkr.ko] undefined! > fix: disable pc speaker support > > > Cheers, > Andi > > From dvomlehn@cisco.com Mon Feb 22 23:37:29 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 22 Feb 2010 23:37:35 +0100 (CET) Received: from sj-iport-3.cisco.com ([171.71.176.72]:48790 "EHLO sj-iport-3.cisco.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492334Ab0BVWh3 (ORCPT ); Mon, 22 Feb 2010 23:37:29 +0100 Authentication-Results: sj-iport-3.cisco.com; dkim=neutral (message not signed) header.i=none X-IronPort-Anti-Spam-Filtered: true X-IronPort-Anti-Spam-Result: AvsEAFKWgkurR7H+/2dsb2JhbACbAXOkWJglhGsEgxU X-IronPort-AV: E=Sophos;i="4.49,521,1262563200"; d="scan'208";a="213672066" Received: from sj-core-2.cisco.com ([171.71.177.254]) by sj-iport-3.cisco.com with ESMTP; 22 Feb 2010 22:37:21 +0000 Received: from dvomlehn-lnx2.corp.sa.net ([64.101.20.155]) by sj-core-2.cisco.com (8.13.8/8.14.3) with ESMTP id o1MMbLoT020398; Mon, 22 Feb 2010 22:37:21 GMT Date: Mon, 22 Feb 2010 14:37:21 -0800 From: David VomLehn To: to@dvomlehn-lnx2.corp.sa.net, "linux-mips@linux-mips.org"@cisco.com, linux-mips@linux-mips.org Cc: ralf@linux-mips.org Subject: Eliminate duplicate opcode definition macros Message-ID: <20100222223721.GA27005@dvomlehn-lnx2.corp.sa.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25989 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dvomlehn@cisco.com Precedence: bulk X-list: linux-mips Change to different macros for assembler macros since the old names in powertv_setup.c were co-opted for use in asm/asm.h. This broken the build for the powertv platform. This patch introduces new macros based on the new macros in asm.h to take the place of the old macro values. Signed-off-by: David VomLehn --- arch/mips/powertv/powertv_setup.c | 99 ++++++++++++++++++------------------- 1 files changed, 48 insertions(+), 51 deletions(-) diff --git a/arch/mips/powertv/powertv_setup.c b/arch/mips/powertv/powertv_setup.c index 698b1ea..9bac903 100644 --- a/arch/mips/powertv/powertv_setup.c +++ b/arch/mips/powertv/powertv_setup.c @@ -32,35 +32,32 @@ #include #include #include +#include #include #include #include #include "reset.h" +#include #define VAL(n) STR(n) /* * Macros for loading addresses and storing registers: - * PTR_LA Load the address into a register - * LONG_S Store the full width of the given register. - * LONG_L Load the full width of the given register - * PTR_ADDIU Add a constant value to a register used as a pointer + * LONG_L_ Stringified version of LONG_L for use in asm() statement + * LONG_S_ Stringified version of LONG_S for use in asm() statement + * PTR_LA_ Stringified version of PTR_LA for use in asm() statement * REG_SIZE Number of 8-bit bytes in a full width register */ +#define LONG_L_ VAL(LONG_L) " " +#define LONG_S_ VAL(LONG_S) " " +#define PTR_LA_ VAL(PTR_LA) " " + #ifdef CONFIG_64BIT #warning TODO: 64-bit code needs to be verified -#define PTR_LA "dla " -#define LONG_S "sd " -#define LONG_L "ld " -#define PTR_ADDIU "daddiu " #define REG_SIZE "8" /* In bytes */ #endif #ifdef CONFIG_32BIT -#define PTR_LA "la " -#define LONG_S "sw " -#define LONG_L "lw " -#define PTR_ADDIU "addiu " #define REG_SIZE "4" /* In bytes */ #endif @@ -113,9 +110,9 @@ static int panic_handler(struct notifier_block *notifier_block, * structure. */ __asm__ __volatile__ ( ".set noat\n" - LONG_S "$at, %[at]\n" - LONG_S "$2, %[v0]\n" - LONG_S "$3, %[v1]\n" + LONG_S_ "$at, %[at]\n" + LONG_S_ "$2, %[v0]\n" + LONG_S_ "$3, %[v1]\n" : [at] "=m" (at), [v0] "=m" (v0), @@ -129,54 +126,54 @@ static int panic_handler(struct notifier_block *notifier_block, "move $at, %[pt_regs]\n" /* Argument registers */ - LONG_S "$4, " VAL(PT_R4) "($at)\n" - LONG_S "$5, " VAL(PT_R5) "($at)\n" - LONG_S "$6, " VAL(PT_R6) "($at)\n" - LONG_S "$7, " VAL(PT_R7) "($at)\n" + LONG_S_ "$4, " VAL(PT_R4) "($at)\n" + LONG_S_ "$5, " VAL(PT_R5) "($at)\n" + LONG_S_ "$6, " VAL(PT_R6) "($at)\n" + LONG_S_ "$7, " VAL(PT_R7) "($at)\n" /* Temporary regs */ - LONG_S "$8, " VAL(PT_R8) "($at)\n" - LONG_S "$9, " VAL(PT_R9) "($at)\n" - LONG_S "$10, " VAL(PT_R10) "($at)\n" - LONG_S "$11, " VAL(PT_R11) "($at)\n" - LONG_S "$12, " VAL(PT_R12) "($at)\n" - LONG_S "$13, " VAL(PT_R13) "($at)\n" - LONG_S "$14, " VAL(PT_R14) "($at)\n" - LONG_S "$15, " VAL(PT_R15) "($at)\n" + LONG_S_ "$8, " VAL(PT_R8) "($at)\n" + LONG_S_ "$9, " VAL(PT_R9) "($at)\n" + LONG_S_ "$10, " VAL(PT_R10) "($at)\n" + LONG_S_ "$11, " VAL(PT_R11) "($at)\n" + LONG_S_ "$12, " VAL(PT_R12) "($at)\n" + LONG_S_ "$13, " VAL(PT_R13) "($at)\n" + LONG_S_ "$14, " VAL(PT_R14) "($at)\n" + LONG_S_ "$15, " VAL(PT_R15) "($at)\n" /* "Saved" registers */ - LONG_S "$16, " VAL(PT_R16) "($at)\n" - LONG_S "$17, " VAL(PT_R17) "($at)\n" - LONG_S "$18, " VAL(PT_R18) "($at)\n" - LONG_S "$19, " VAL(PT_R19) "($at)\n" - LONG_S "$20, " VAL(PT_R20) "($at)\n" - LONG_S "$21, " VAL(PT_R21) "($at)\n" - LONG_S "$22, " VAL(PT_R22) "($at)\n" - LONG_S "$23, " VAL(PT_R23) "($at)\n" + LONG_S_ "$16, " VAL(PT_R16) "($at)\n" + LONG_S_ "$17, " VAL(PT_R17) "($at)\n" + LONG_S_ "$18, " VAL(PT_R18) "($at)\n" + LONG_S_ "$19, " VAL(PT_R19) "($at)\n" + LONG_S_ "$20, " VAL(PT_R20) "($at)\n" + LONG_S_ "$21, " VAL(PT_R21) "($at)\n" + LONG_S_ "$22, " VAL(PT_R22) "($at)\n" + LONG_S_ "$23, " VAL(PT_R23) "($at)\n" /* Add'l temp regs */ - LONG_S "$24, " VAL(PT_R24) "($at)\n" - LONG_S "$25, " VAL(PT_R25) "($at)\n" + LONG_S_ "$24, " VAL(PT_R24) "($at)\n" + LONG_S_ "$25, " VAL(PT_R25) "($at)\n" /* Kernel temp regs */ - LONG_S "$26, " VAL(PT_R26) "($at)\n" - LONG_S "$27, " VAL(PT_R27) "($at)\n" + LONG_S_ "$26, " VAL(PT_R26) "($at)\n" + LONG_S_ "$27, " VAL(PT_R27) "($at)\n" /* Global pointer, stack pointer, frame pointer and * return address */ - LONG_S "$gp, " VAL(PT_R28) "($at)\n" - LONG_S "$sp, " VAL(PT_R29) "($at)\n" - LONG_S "$fp, " VAL(PT_R30) "($at)\n" - LONG_S "$ra, " VAL(PT_R31) "($at)\n" + LONG_S_ "$gp, " VAL(PT_R28) "($at)\n" + LONG_S_ "$sp, " VAL(PT_R29) "($at)\n" + LONG_S_ "$fp, " VAL(PT_R30) "($at)\n" + LONG_S_ "$ra, " VAL(PT_R31) "($at)\n" /* Now we can get the $at and v0 registers back and * store them */ - LONG_L "$8, %[at]\n" - LONG_S "$8, " VAL(PT_R1) "($at)\n" - LONG_L "$8, %[v0]\n" - LONG_S "$8, " VAL(PT_R2) "($at)\n" - LONG_L "$8, %[v1]\n" - LONG_S "$8, " VAL(PT_R3) "($at)\n" + LONG_L_ "$8, %[at]\n" + LONG_S_ "$8, " VAL(PT_R1) "($at)\n" + LONG_L_ "$8, %[v0]\n" + LONG_S_ "$8, " VAL(PT_R2) "($at)\n" + LONG_L_ "$8, %[v1]\n" + LONG_S_ "$8, " VAL(PT_R3) "($at)\n" : : [at] "m" (at), @@ -191,8 +188,8 @@ static int panic_handler(struct notifier_block *notifier_block, __asm__ __volatile__ ( ".set noat\n" "1:\n" - PTR_LA "$at, 1b\n" - LONG_S "$at, %[cp0_epc]\n" + PTR_LA_ "$at, 1b\n" + LONG_S_ "$at, %[cp0_epc]\n" : [cp0_epc] "=m" (my_regs.cp0_epc) : From yuasa.linux@gmail.com Tue Feb 23 00:52:04 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 23 Feb 2010 00:52:12 +0100 (CET) Received: from mail-bw0-f215.google.com ([209.85.218.215]:43026 "EHLO mail-bw0-f215.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491794Ab0BVXwE (ORCPT ); Tue, 23 Feb 2010 00:52:04 +0100 Received: by bwz7 with SMTP id 7so2099133bwz.24 for ; Mon, 22 Feb 2010 15:51:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:sender:date:from:to:cc :subject:message-id:in-reply-to:references:x-mailer:mime-version :content-type:content-transfer-encoding; bh=n3xuzzJyGKeYJbChfb3eiU9M/daetnwDOn1ZGgx05HY=; b=fziYWZkeca2Ytp2fZsoioWVwcSsppCePXMKvhgpxyQPNBjT5s7s+xT7Kp9nQ3ttgwT 7TJ9E+jmB0roRptWYxzfok7lriwtnlauqbjzC2YEAeKsnkD7V6cFdM9eNXaoZMCKCz+Y sBsPQ30ol8UwfnW4mYSR92TjEzAFao8jedWKs= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:date:from:to:cc:subject:message-id:in-reply-to:references :x-mailer:mime-version:content-type:content-transfer-encoding; b=c3exOK+KdjEAw3FYAXLwAV/ai/W0b0qBBBEPZgsK8TXS/YaxQ8IppNkr0cwe64aglP NNgDPTP6IeIaXd5fZGc8vOAaoXZodeMRxtT4nznDl1g3vfU4hg0PiwEB4K0qe49VYLgY SH3+f0fK2EIy0WrBXJJLoZ2yMtAKVVHiklSt4= Received: by 10.204.4.150 with SMTP id 22mr3273787bkr.192.1266882717400; Mon, 22 Feb 2010 15:51:57 -0800 (PST) Received: from ypsilon.skybright.jp (sannin29006.nirai.ne.jp [203.160.29.6]) by mx.google.com with ESMTPS id 14sm1426838bwz.10.2010.02.22.15.51.52 (version=TLSv1/SSLv3 cipher=RC4-MD5); Mon, 22 Feb 2010 15:51:55 -0800 (PST) Date: Tue, 23 Feb 2010 08:51:43 +0900 From: Yoichi Yuasa To: Bjorn Helgaas Cc: yuasa@linux-mips.org, Ralf Baechle , linux-mips@linux-mips.org Subject: Re: Reverting old hack Message-Id: <20100223085143.aeb1fa53.yuasa@linux-mips.org> In-Reply-To: <201002221355.28939.bjorn.helgaas@hp.com> References: <20100220113134.GA27194@linux-mips.org> <1266677869.1320.8.camel@dc7800.home> <20100221164531.382b3785.yuasa@linux-mips.org> <201002221355.28939.bjorn.helgaas@hp.com> X-Mailer: Sylpheed 2.7.1 (GTK+ 2.16.6; i686-pc-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25990 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: yuasa@linux-mips.org Precedence: bulk X-list: linux-mips Hi Bjorn, On Mon, 22 Feb 2010 13:55:28 -0700 Bjorn Helgaas wrote: > On Sunday 21 February 2010 12:45:31 am Yoichi Yuasa wrote: > > > I'd like to understand the PCI architecture of Cobalt better. Would you > > > mind turning on CONFIG_PCI_DEBUG and posting the dmesg log? > > > > If you want to know what happen, you can see my old e-mail. > > > > http://marc.info/?l=linux-kernel&m=118792430424186&w=2 > > There's not much detail there. It would save me a lot of time if > you could collect the complete dmesg log, /proc/iomem, and /proc/ioports. It cannot boot without old hack. I just got a console capture. Yoichi ---- 2> execute console=ttyS0,115200 root=/dev/sda2 elf32: 00080000 - 004220ef (800841f0) (ffffffff.80000000) elf32: 80080000 (80080000) 3694756t + 114764t net: interface down Cobalt board ID: 5 pci 0000:00:07.0: BAR 6: assigned [mem 0x12000000-0x1203ffff pref] pci 0000:00:0c.0: BAR 6: assigned [mem 0x12040000-0x1207ffff pref] pci 0000:00:0a.0: BAR 0: assigned [mem 0x12080000-0x12080fff] pci 0000:00:0a.0: BAR 0: set to [mem 0x12080000-0x12080fff] (PCI address [0x12080000-0x12080fff] pci 0000:00:0a.1: BAR 0: assigned [mem 0x12081000-0x12081fff] pci 0000:00:0a.1: BAR 0: set to [mem 0x12081000-0x12081fff] (PCI address [0x12081000-0x12081fff] pci 0000:00:07.0: BAR 1: assigned [mem 0x12082000-0x120823ff] pci 0000:00:07.0: BAR 1: set to [mem 0x12082000-0x120823ff] (PCI address [0x12082000-0x120823ff] pci 0000:00:0c.0: BAR 1: assigned [mem 0x12082400-0x120827ff] pci 0000:00:0c.0: BAR 1: set to [mem 0x12082400-0x120827ff] (PCI address [0x12082400-0x120827ff] pci 0000:00:0a.2: BAR 0: assigned [mem 0x12082800-0x120828ff] pci 0000:00:0a.2: BAR 0: set to [mem 0x12082800-0x120828ff] (PCI address [0x12082800-0x120828ff] pci 0000:00:07.0: BAR 0: assigned [io 0x1000-0x107f] pci 0000:00:07.0: BAR 0: set to [io 0x1000-0x107f] (PCI address [0x10001000-0x1000107f] pci 0000:00:0c.0: BAR 0: assigned [io 0x1080-0x10ff] pci 0000:00:0c.0: BAR 0: set to [io 0x1080-0x10ff] (PCI address [0x10001080-0x100010ff] pci 0000:00:09.2: BAR 4: assigned [io 0x1400-0x141f] pci 0000:00:09.2: BAR 4: set to [io 0x1400-0x141f] (PCI address [0x10001400-0x1000141f] pci 0000:00:09.1: BAR 4: assigned [io 0x1420-0x142f] pci 0000:00:09.1: BAR 4: set to [io 0x1420-0x142f] (PCI address [0x10001420-0x1000142f] Switching to clocksource MIPS NET: Registered protocol family 2 IP route cache hash table entries: 1024 (order: 0, 4096 bytes) TCP established hash table entries: 4096 (order: 3, 32768 bytes) TCP bind hash table entries: 4096 (order: 2, 16384 bytes) TCP: Hash tables configured (established 4096 bind 4096) TCP reno registered UDP hash table entries: 256 (order: 0, 4096 bytes) UDP-Lite hash table entries: 256 (order: 0, 4096 bytes) NET: Registered protocol family 1 RPC: Registered udp transport module. RPC: Registered tcp transport module. RPC: Registered tcp NFSv4.1 backchannel transport module. pci 0000:00:09.0: Activating ISA DMA hang workarounds Installing knfsd (copyright (C) 1996 okir@monad.swb.de). msgmni has been set to 245 io scheduler noop registered io scheduler deadline registered io scheduler cfq registered (default) fb0: Cobalt server LCD frame buffer device Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled _serial8250.0: ttyS0 at MMIO 0x1c800000 (irq = 21) is a ST16650V2_console [ttyS0] enabled, bootconsole disabled console [ttyS0] enabled, bootconsole disabled loop: module loaded pata_via 0000:00:09.1: BAR 0: can't reserve [io 0xf00001f0-0xf00001f7] pata_via 0000:00:09.1: failed to request/iomap BARs for port 0 (errno=-16) pata_via 0000:00:09.1: BAR 2: can't reserve [io 0xf0000170-0xf0000177] pata_via 0000:00:09.1: failed to request/iomap BARs for port 1 (errno=-16) pata_via 0000:00:09.1: no available native port physmap platform flash device: 00080000 at 1fc00000 Found: AMD AM29F040 physmap-flash.0: Found 1 x8 devices at 0x0 in 8-bit bank number of JEDEC chips: 1 cmdlinepart partition parsing not available RedBoot partition parsing not available Using physmap partition information Creating 1 MTD partitions on "physmap-flash.0": 0x000000000000-0x000000080000 : "firmware" Linux Tulip driver version 1.1.15 (Feb 27, 2007) PCI: Enabling device 0000:00:07.0 (0041 -> 0043) tulip0: Old format EEPROM on 'Cobalt Microserver' board. Using substitute media control info. tulip0: EEPROM default media type Autosense. tulip0: Index #0 - Media MII (#11) described by a 21142 MII PHY (3) block. tulip0: MII transceiver #1 config 1000 status 7809 advertising 01e1. eth0: Digital DS21142/43 Tulip rev 65 at Port 0x1000, --:--:--:--:--:--, IRQ 19. PCI: Enabling device 0000:00:0c.0 (0005 -> 0007) tulip1: Old format EEPROM on 'Cobalt Microserver' board. Using substitute media control info. tulip1: EEPROM default media type Autosense. tulip1: Index #0 - Media MII (#11) described by a 21142 MII PHY (3) block. tulip1: MII transceiver #1 config 1000 status 7809 advertising 01e1. eth1: Digital DS21142/43 Tulip rev 65 at Port 0x1080, --:--:--:--:--:--, IRQ 20. input: Cobalt buttons as /devices/platform/Cobalt buttons/input/input0 rtc_cmos rtc_cmos: rtc core: registered rtc_cmos as rtc0 rtc0: alarms up to one day, 242 bytes nvram Registered led device: qube::front TCP cubic registered Initializing XFRM netlink socket NET: Registered protocol family 17 NET: Registered protocol family 15 rtc_cmos rtc_cmos: setting system clock to 2010-02-21 23:19:20 UTC (1266794360) VFS: Cannot open root device "sda2" or unknown-block(0,0) Please append a correct "root=" boot option; here are the available partitions: Kernel panic - not syncing: VFS: Unable to mount root fs on unknown-block(0,0) From bjorn.helgaas@hp.com Tue Feb 23 01:15:34 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 23 Feb 2010 01:15:42 +0100 (CET) Received: from g5t0007.atlanta.hp.com ([15.192.0.44]:27956 "EHLO g5t0007.atlanta.hp.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491970Ab0BWAPc (ORCPT ); Tue, 23 Feb 2010 01:15:32 +0100 Received: from g5t0030.atlanta.hp.com (g5t0030.atlanta.hp.com [16.228.8.142]) by g5t0007.atlanta.hp.com (Postfix) with ESMTP id 35463143E2; Tue, 23 Feb 2010 00:15:26 +0000 (UTC) Received: from ldl (ldl.fc.hp.com [15.11.146.30]) by g5t0030.atlanta.hp.com (Postfix) with ESMTP id C770C1407A; Tue, 23 Feb 2010 00:15:25 +0000 (UTC) Received: from localhost (ldl.fc.hp.com [127.0.0.1]) by ldl (Postfix) with ESMTP id 90DDACF004A; Mon, 22 Feb 2010 17:15:25 -0700 (MST) Received: from ldl ([127.0.0.1]) by localhost (ldl.fc.hp.com [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id EFMAYtJ3hrgo; Mon, 22 Feb 2010 17:15:25 -0700 (MST) Received: from tigger.helgaas (lart.fc.hp.com [15.11.146.31]) by ldl (Postfix) with ESMTP id 7B97ECF0011; Mon, 22 Feb 2010 17:15:25 -0700 (MST) From: Bjorn Helgaas To: Yoichi Yuasa Subject: Re: Reverting old hack Date: Mon, 22 Feb 2010 17:15:24 -0700 User-Agent: KMail/1.9.10 Cc: Ralf Baechle , linux-mips@linux-mips.org References: <20100220113134.GA27194@linux-mips.org> <201002221355.28939.bjorn.helgaas@hp.com> <20100223085143.aeb1fa53.yuasa@linux-mips.org> In-Reply-To: <20100223085143.aeb1fa53.yuasa@linux-mips.org> MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit Content-Disposition: inline Message-Id: <201002221715.24674.bjorn.helgaas@hp.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25991 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: bjorn.helgaas@hp.com Precedence: bulk X-list: linux-mips On Monday 22 February 2010 04:51:43 pm Yoichi Yuasa wrote: > Hi Bjorn, > > On Mon, 22 Feb 2010 13:55:28 -0700 > Bjorn Helgaas wrote: > > > On Sunday 21 February 2010 12:45:31 am Yoichi Yuasa wrote: > > > > I'd like to understand the PCI architecture of Cobalt better. Would you > > > > mind turning on CONFIG_PCI_DEBUG and posting the dmesg log? > > > > > > If you want to know what happen, you can see my old e-mail. > > > > > > http://marc.info/?l=linux-kernel&m=118792430424186&w=2 > > > > There's not much detail there. It would save me a lot of time if > > you could collect the complete dmesg log, /proc/iomem, and /proc/ioports. > > It cannot boot without old hack. I know; I meant that the information from a kernel with the old hack would be useful. But I think I'm starting to understand anyway. The Linux I/O port number space is defined here: static struct resource cobalt_io_resource = { .start = 0x1000, .end = GT_DEF_PCI0_IO_SIZE - 1, /* 0x1ffffff */ [As an aside, I'm not sure 0x1000 is the correct start -- for example, I think Linux I/O port 0x1f0 is forwarded by the host bridge.] The corresponding PCI I/O port numbers are determined by the PCI I/O decoder address, so I agree that we need the io_offset to convert between the Linux port numbers and ports that appear on the PCI bus. I think the IDE device is a problem because pci_setup_device() fills in legacy resources with ports 0x1f0-0x1f7, etc. We expect those resources to contain PCI bus addresses at this point, but we could never see those addresses on the Cobalt PCI bus (we would only see things in the range 0x10000000-0x11ffffff). When we convert 0x1f0 with pcibios_bus_to_resource() (or with pcibios_fixup_device_resources() without the IORESOURCE_PCI_FIXED hack), we get 0x1f0 + 0xf0000000 == 0xf00001f0, when we want 0x1f0 instead. > pata_via 0000:00:09.1: BAR 0: can't reserve [io 0xf00001f0-0xf00001f7] I still don't know the best way to fix this, but does this make sense so far? Bjorn From dvomlehn@cisco.com Tue Feb 23 01:31:22 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 23 Feb 2010 01:31:30 +0100 (CET) Received: from sj-iport-5.cisco.com ([171.68.10.87]:55142 "EHLO sj-iport-5.cisco.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491888Ab0BWAbW (ORCPT ); Tue, 23 Feb 2010 01:31:22 +0100 Authentication-Results: sj-iport-5.cisco.com; dkim=neutral (message not signed) header.i=none X-IronPort-Anti-Spam-Filtered: true X-IronPort-Anti-Spam-Result: AvsEAAyxgkurRN+K/2dsb2JhbACbAXOjTpgzhGsEgxU X-IronPort-AV: E=Sophos;i="4.49,521,1262563200"; d="scan'208";a="155131324" Received: from sj-core-4.cisco.com ([171.68.223.138]) by sj-iport-5.cisco.com with ESMTP; 23 Feb 2010 00:31:13 +0000 Received: from dvomlehn-lnx2.corp.sa.net ([64.101.20.155]) by sj-core-4.cisco.com (8.13.8/8.14.3) with ESMTP id o1N0VDs4007711; Tue, 23 Feb 2010 00:31:13 GMT Date: Mon, 22 Feb 2010 16:31:13 -0800 From: David VomLehn To: to@dvomlehn-lnx2.corp.sa.net, "linux-mips@linux-mips.org"@cisco.com, linux-mips@linux-mips.org Cc: ralf@linux-mips.org Subject: [V2] Eliminate duplicate opcode definition macros Message-ID: <20100223003113.GA8599@dvomlehn-lnx2.corp.sa.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25992 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dvomlehn@cisco.com Precedence: bulk X-list: linux-mips Change to different macros for assembler macros since the old names in powertv_setup.c were co-opted for use in asm/asm.h. This broken the build for the powertv platform. This patch introduces new macros based on the new macros in asm.h to take the place of the old macro values. Signed-off-by: David VomLehn --- arch/mips/powertv/powertv_setup.c | 102 ++++++++++++++++++------------------- 1 files changed, 49 insertions(+), 53 deletions(-) diff --git a/arch/mips/powertv/powertv_setup.c b/arch/mips/powertv/powertv_setup.c index 698b1ea..af2cae0 100644 --- a/arch/mips/powertv/powertv_setup.c +++ b/arch/mips/powertv/powertv_setup.c @@ -25,14 +25,15 @@ #include #include #include - #include +#include + #include #include #include #include #include -#include +#include #include #include #include "reset.h" @@ -41,26 +42,21 @@ /* * Macros for loading addresses and storing registers: - * PTR_LA Load the address into a register - * LONG_S Store the full width of the given register. - * LONG_L Load the full width of the given register - * PTR_ADDIU Add a constant value to a register used as a pointer + * LONG_L_ Stringified version of LONG_L for use in asm() statement + * LONG_S_ Stringified version of LONG_S for use in asm() statement + * PTR_LA_ Stringified version of PTR_LA for use in asm() statement * REG_SIZE Number of 8-bit bytes in a full width register */ +#define LONG_L_ VAL(LONG_L) " " +#define LONG_S_ VAL(LONG_S) " " +#define PTR_LA_ VAL(PTR_LA) " " + #ifdef CONFIG_64BIT #warning TODO: 64-bit code needs to be verified -#define PTR_LA "dla " -#define LONG_S "sd " -#define LONG_L "ld " -#define PTR_ADDIU "daddiu " #define REG_SIZE "8" /* In bytes */ #endif #ifdef CONFIG_32BIT -#define PTR_LA "la " -#define LONG_S "sw " -#define LONG_L "lw " -#define PTR_ADDIU "addiu " #define REG_SIZE "4" /* In bytes */ #endif @@ -113,9 +109,9 @@ static int panic_handler(struct notifier_block *notifier_block, * structure. */ __asm__ __volatile__ ( ".set noat\n" - LONG_S "$at, %[at]\n" - LONG_S "$2, %[v0]\n" - LONG_S "$3, %[v1]\n" + LONG_S_ "$at, %[at]\n" + LONG_S_ "$2, %[v0]\n" + LONG_S_ "$3, %[v1]\n" : [at] "=m" (at), [v0] "=m" (v0), @@ -129,54 +125,54 @@ static int panic_handler(struct notifier_block *notifier_block, "move $at, %[pt_regs]\n" /* Argument registers */ - LONG_S "$4, " VAL(PT_R4) "($at)\n" - LONG_S "$5, " VAL(PT_R5) "($at)\n" - LONG_S "$6, " VAL(PT_R6) "($at)\n" - LONG_S "$7, " VAL(PT_R7) "($at)\n" + LONG_S_ "$4, " VAL(PT_R4) "($at)\n" + LONG_S_ "$5, " VAL(PT_R5) "($at)\n" + LONG_S_ "$6, " VAL(PT_R6) "($at)\n" + LONG_S_ "$7, " VAL(PT_R7) "($at)\n" /* Temporary regs */ - LONG_S "$8, " VAL(PT_R8) "($at)\n" - LONG_S "$9, " VAL(PT_R9) "($at)\n" - LONG_S "$10, " VAL(PT_R10) "($at)\n" - LONG_S "$11, " VAL(PT_R11) "($at)\n" - LONG_S "$12, " VAL(PT_R12) "($at)\n" - LONG_S "$13, " VAL(PT_R13) "($at)\n" - LONG_S "$14, " VAL(PT_R14) "($at)\n" - LONG_S "$15, " VAL(PT_R15) "($at)\n" + LONG_S_ "$8, " VAL(PT_R8) "($at)\n" + LONG_S_ "$9, " VAL(PT_R9) "($at)\n" + LONG_S_ "$10, " VAL(PT_R10) "($at)\n" + LONG_S_ "$11, " VAL(PT_R11) "($at)\n" + LONG_S_ "$12, " VAL(PT_R12) "($at)\n" + LONG_S_ "$13, " VAL(PT_R13) "($at)\n" + LONG_S_ "$14, " VAL(PT_R14) "($at)\n" + LONG_S_ "$15, " VAL(PT_R15) "($at)\n" /* "Saved" registers */ - LONG_S "$16, " VAL(PT_R16) "($at)\n" - LONG_S "$17, " VAL(PT_R17) "($at)\n" - LONG_S "$18, " VAL(PT_R18) "($at)\n" - LONG_S "$19, " VAL(PT_R19) "($at)\n" - LONG_S "$20, " VAL(PT_R20) "($at)\n" - LONG_S "$21, " VAL(PT_R21) "($at)\n" - LONG_S "$22, " VAL(PT_R22) "($at)\n" - LONG_S "$23, " VAL(PT_R23) "($at)\n" + LONG_S_ "$16, " VAL(PT_R16) "($at)\n" + LONG_S_ "$17, " VAL(PT_R17) "($at)\n" + LONG_S_ "$18, " VAL(PT_R18) "($at)\n" + LONG_S_ "$19, " VAL(PT_R19) "($at)\n" + LONG_S_ "$20, " VAL(PT_R20) "($at)\n" + LONG_S_ "$21, " VAL(PT_R21) "($at)\n" + LONG_S_ "$22, " VAL(PT_R22) "($at)\n" + LONG_S_ "$23, " VAL(PT_R23) "($at)\n" /* Add'l temp regs */ - LONG_S "$24, " VAL(PT_R24) "($at)\n" - LONG_S "$25, " VAL(PT_R25) "($at)\n" + LONG_S_ "$24, " VAL(PT_R24) "($at)\n" + LONG_S_ "$25, " VAL(PT_R25) "($at)\n" /* Kernel temp regs */ - LONG_S "$26, " VAL(PT_R26) "($at)\n" - LONG_S "$27, " VAL(PT_R27) "($at)\n" + LONG_S_ "$26, " VAL(PT_R26) "($at)\n" + LONG_S_ "$27, " VAL(PT_R27) "($at)\n" /* Global pointer, stack pointer, frame pointer and * return address */ - LONG_S "$gp, " VAL(PT_R28) "($at)\n" - LONG_S "$sp, " VAL(PT_R29) "($at)\n" - LONG_S "$fp, " VAL(PT_R30) "($at)\n" - LONG_S "$ra, " VAL(PT_R31) "($at)\n" + LONG_S_ "$gp, " VAL(PT_R28) "($at)\n" + LONG_S_ "$sp, " VAL(PT_R29) "($at)\n" + LONG_S_ "$fp, " VAL(PT_R30) "($at)\n" + LONG_S_ "$ra, " VAL(PT_R31) "($at)\n" /* Now we can get the $at and v0 registers back and * store them */ - LONG_L "$8, %[at]\n" - LONG_S "$8, " VAL(PT_R1) "($at)\n" - LONG_L "$8, %[v0]\n" - LONG_S "$8, " VAL(PT_R2) "($at)\n" - LONG_L "$8, %[v1]\n" - LONG_S "$8, " VAL(PT_R3) "($at)\n" + LONG_L_ "$8, %[at]\n" + LONG_S_ "$8, " VAL(PT_R1) "($at)\n" + LONG_L_ "$8, %[v0]\n" + LONG_S_ "$8, " VAL(PT_R2) "($at)\n" + LONG_L_ "$8, %[v1]\n" + LONG_S_ "$8, " VAL(PT_R3) "($at)\n" : : [at] "m" (at), @@ -191,8 +187,8 @@ static int panic_handler(struct notifier_block *notifier_block, __asm__ __volatile__ ( ".set noat\n" "1:\n" - PTR_LA "$at, 1b\n" - LONG_S "$at, %[cp0_epc]\n" + PTR_LA_ "$at, 1b\n" + LONG_S_ "$at, %[cp0_epc]\n" : [cp0_epc] "=m" (my_regs.cp0_epc) : From yuasa.linux@gmail.com Tue Feb 23 01:51:14 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 23 Feb 2010 01:51:22 +0100 (CET) Received: from mail-bw0-f215.google.com ([209.85.218.215]:63000 "EHLO mail-bw0-f215.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492343Ab0BWAvO (ORCPT ); Tue, 23 Feb 2010 01:51:14 +0100 Received: by bwz7 with SMTP id 7so2124599bwz.24 for ; Mon, 22 Feb 2010 16:51:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:sender:date:from:to:cc :subject:message-id:in-reply-to:references:x-mailer:mime-version :content-type:content-transfer-encoding; bh=bck8WG4BGeouzKr2DbFalIksZnp+XuVaH9jZTD6uJaA=; b=xohag6O6tPJS6ITroAofMfRH6yxmVlpBtE5i6e9aJr9ec38XQV7rxK76xqH7idIwYe oFMsNSDcLjf0cNblh9lfoUJ+XppZaPBg0RMAat0XgE9f97YDWVnNJjEpT4rhdO377WKa JbDFE47cvTpjrTifsSAnIfRo97RTmdm+wjzBc= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:date:from:to:cc:subject:message-id:in-reply-to:references :x-mailer:mime-version:content-type:content-transfer-encoding; b=ObvMbhNPx4CfgRgXoVUpsHBxaXAQ1GoHpcT7nfdMhsj+1lyEE8xd022gmjCLO1a6dG 95pXfO0GPJqGMdXLwHV0KaIL7Enj91k5kTmcDvv+tCWJvVUE5bx57ZOMXuSxk3ql1Bxm bv0qzSxGRae+SVlsJNq9Js9/RiCHi7qCgxDTI= Received: by 10.204.49.68 with SMTP id u4mr889716bkf.57.1266886265645; Mon, 22 Feb 2010 16:51:05 -0800 (PST) Received: from ypsilon.skybright.jp (sannin29006.nirai.ne.jp [203.160.29.6]) by mx.google.com with ESMTPS id 15sm1462801bwz.8.2010.02.22.16.51.01 (version=TLSv1/SSLv3 cipher=RC4-MD5); Mon, 22 Feb 2010 16:51:04 -0800 (PST) Date: Tue, 23 Feb 2010 09:50:51 +0900 From: Yoichi Yuasa To: Bjorn Helgaas Cc: yuasa@linux-mips.org, Ralf Baechle , linux-mips@linux-mips.org Subject: Re: Reverting old hack Message-Id: <20100223095051.26a5049b.yuasa@linux-mips.org> In-Reply-To: <201002221715.24674.bjorn.helgaas@hp.com> References: <20100220113134.GA27194@linux-mips.org> <201002221355.28939.bjorn.helgaas@hp.com> <20100223085143.aeb1fa53.yuasa@linux-mips.org> <201002221715.24674.bjorn.helgaas@hp.com> X-Mailer: Sylpheed 2.7.1 (GTK+ 2.16.6; i686-pc-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25993 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: yuasa@linux-mips.org Precedence: bulk X-list: linux-mips On Mon, 22 Feb 2010 17:15:24 -0700 Bjorn Helgaas wrote: > On Monday 22 February 2010 04:51:43 pm Yoichi Yuasa wrote: > > Hi Bjorn, > > > > On Mon, 22 Feb 2010 13:55:28 -0700 > > Bjorn Helgaas wrote: > > > > > On Sunday 21 February 2010 12:45:31 am Yoichi Yuasa wrote: > > > > > I'd like to understand the PCI architecture of Cobalt better. Would you > > > > > mind turning on CONFIG_PCI_DEBUG and posting the dmesg log? > > > > > > > > If you want to know what happen, you can see my old e-mail. > > > > > > > > http://marc.info/?l=linux-kernel&m=118792430424186&w=2 > > > > > > There's not much detail there. It would save me a lot of time if > > > you could collect the complete dmesg log, /proc/iomem, and /proc/ioports. > > > > It cannot boot without old hack. > > I know; I meant that the information from a kernel with the old > hack would be useful. But I think I'm starting to understand anyway. > > The Linux I/O port number space is defined here: > > static struct resource cobalt_io_resource = { > .start = 0x1000, > .end = GT_DEF_PCI0_IO_SIZE - 1, /* 0x1ffffff */ > > [As an aside, I'm not sure 0x1000 is the correct start -- for example, > I think Linux I/O port 0x1f0 is forwarded by the host bridge.] This is the space(0x0-0xfff) for the fixed address devices(PIC, RTC, DMA(just reserved)...). $ cat /proc/ioports 00000000-0000001f : reserved 00000020-00000021 : pic1 00000060-0000006f : reserved 00000070-00000077 : rtc_cmos 00000070-00000077 : rtc0 00000080-0000008f : reserved 000000a0-000000a1 : pic2 000000c0-000000df : reserved 00000170-00000177 : pata_via 000001f0-000001f7 : pata_via 00000376-00000376 : pata_via 000003f6-000003f6 : pata_via 00001000-01ffffff : PCI I/O 00001000-0000107f : 0000:00:07.0 00001000-0000107f : tulip 00001080-000010ff : 0000:00:0c.0 00001080-000010ff : tulip 00001400-0000141f : 0000:00:09.2 00001420-0000142f : 0000:00:09.1 00001420-0000142f : pata_via > The corresponding PCI I/O port numbers are determined by the PCI > I/O decoder address, so I agree that we need the io_offset to convert > between the Linux port numbers and ports that appear on the PCI bus. > > I think the IDE device is a problem because pci_setup_device() fills > in legacy resources with ports 0x1f0-0x1f7, etc. We expect those > resources to contain PCI bus addresses at this point, but we could > never see those addresses on the Cobalt PCI bus (we would only see > things in the range 0x10000000-0x11ffffff). > > When we convert 0x1f0 with pcibios_bus_to_resource() (or with > pcibios_fixup_device_resources() without the IORESOURCE_PCI_FIXED > hack), we get 0x1f0 + 0xf0000000 == 0xf00001f0, when we want 0x1f0 > instead. > > > pata_via 0000:00:09.1: BAR 0: can't reserve [io 0xf00001f0-0xf00001f7] > > I still don't know the best way to fix this, but does this make sense > so far? That makes sense. Yoichi From shinya.kuribayashi@necel.com Tue Feb 23 06:42:49 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 23 Feb 2010 06:42:57 +0100 (CET) Received: from TYO201.gate.nec.co.jp ([202.32.8.193]:56016 "EHLO tyo201.gate.nec.co.jp" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491039Ab0BWFmt (ORCPT ); Tue, 23 Feb 2010 06:42:49 +0100 Received: from relay21.aps.necel.com ([10.29.19.50]) by tyo201.gate.nec.co.jp (8.13.8/8.13.4) with ESMTP id o1N5gJlM008652; Tue, 23 Feb 2010 14:42:42 +0900 (JST) Received: from realmbox31.aps.necel.com ([10.29.19.36] [10.29.19.36]) by relay21.aps.necel.com with ESMTP; Tue, 23 Feb 2010 14:42:42 +0900 Received: from [10.114.181.193] ([10.114.181.193] [10.114.181.193]) by mbox02.aps.necel.com with ESMTP; Tue, 23 Feb 2010 14:42:42 +0900 Message-ID: <4B836AD2.20602@necel.com> Date: Tue, 23 Feb 2010 14:42:42 +0900 From: Shinya Kuribayashi User-Agent: Thunderbird 2.0.0.23 (Windows/20090812) MIME-Version: 1.0 To: "Kevin D. Kissell" CC: Linux MIPS Org Subject: compare_change_hazard (was Re: SMTC Patches [3 of 3]) References: <48C6DD4D.9090600@paralogos.com> In-Reply-To: <48C6DD4D.9090600@paralogos.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25994 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: shinya.kuribayashi@necel.com Precedence: bulk X-list: linux-mips Hi Kevin and folks, Recently I have encountered an awkward timer interrupt behavior on a MIPS32r2 core running at 500+MHz, and find a useful comment left in the kernel. Here I have some question about compare_change_hazard(), which was introduced by the commit. See below: Kevin D. Kissell wrote: >From ac801c3b5c31eb0d53bf08538965f82f59f5f39d Mon Sep 17 00:00:00 2001 >From: Kevin D. Kissell >Date: Tue, 9 Sep 2008 21:48:52 +0200 >Subject: [PATCH] Rework of SMTC support to make it work with the new clock event > system, allowing "tickless" operation, and to make it compatible > with the use of the "wait_irqoff" idle loop. The new clocking > scheme means that the previously optional IPI instant replay > mechanism is now required, and has been made more robust. > Signed-off-by: Kevin D. Kissell > >--- > arch/mips/Kconfig | 26 +-- > arch/mips/kernel/Makefile | 1 + > arch/mips/kernel/cevt-r4k.c | 173 +++++------------ > arch/mips/kernel/cevt-smtc.c | 321 ++++++++++++++++++++++++++++++ > arch/mips/kernel/cpu-probe.c | 10 +- > arch/mips/kernel/genex.S | 4 +- > arch/mips/kernel/smtc.c | 254 +++++++++++++----------- > arch/mips/mips-boards/malta/malta_smtc.c | 9 +- > include/asm-mips/cevt-r4k.h | 46 +++++ > include/asm-mips/irqflags.h | 26 ++- > include/asm-mips/smtc.h | 8 +- > 11 files changed, 598 insertions(+), 280 deletions(-) > create mode 100644 arch/mips/kernel/cevt-smtc.c > create mode 100644 include/asm-mips/cevt-r4k.h [snip] >diff --git a/arch/mips/kernel/cevt-r4k.c b/arch/mips/kernel/cevt-r4k.c >index 24a2d90..4a4c59f 100644 >--- a/arch/mips/kernel/cevt-r4k.c >+++ b/arch/mips/kernel/cevt-r4k.c [snip] >@@ -177,7 +99,23 @@ static int c0_compare_int_pending(void) > return (read_c0_cause() >> cp0_compare_irq) & 0x100; > } > >-static int c0_compare_int_usable(void) >+/* >+ * Compare interrupt can be routed and latched outside the core, >+ * so a single execution hazard barrier may not be enough to give >+ * it time to clear as seen in the Cause register. 4 time the >+ * pipeline depth seems reasonably conservative, and empirically >+ * works better in configurations with high CPU/bus clock ratios. >+ */ >+ >+#define compare_change_hazard() \ >+ do { \ >+ irq_disable_hazard(); \ >+ irq_disable_hazard(); \ >+ irq_disable_hazard(); \ >+ irq_disable_hazard(); \ >+ } while (0) >+ >+int c0_compare_int_usable(void) > { > unsigned int delta; > unsigned int cnt; Above commets reasonably make sense and do help me, thanks :-) On the other hand, the implementation of compare_change_hazard() makes me wonder how this hazard works internally. For MIPS32r2 cores (except for Octeon), irq_disable_hazard() will be translated into "ehb" instruction, so the resulting compare_ change_hazard() is going to be compare_change_hazard: ehb ehb ehb ehb And I wonder how these instructions work. I think the first ehb instruction will clear all execution hazards created by preceding instruction(s) at that moment, this is fine. But I wonder, * HOW do subsequent three "ehb" instructions work in the pipeline? Do they make any "real" effect, or just work as "nop"? * Kevin noted that "4 time the pipeline depth seems reasonably convervative." Is current form of compare_change_hazard() implemented in accordance with his comments? * How many pipline clokcs are consumed for subsequent "ehb" instruction? and so on. I'd like to ask hardware people later, separately, but any comments are appreciated. Thanks in adavance. Shinya >@@ -187,7 +125,7 @@ static int c0_compare_int_usable(void) > */ > if (c0_compare_int_pending()) { > write_c0_compare(read_c0_count()); >- irq_disable_hazard(); >+ compare_change_hazard(); > if (c0_compare_int_pending()) > return 0; > } >@@ -196,7 +134,7 @@ static int c0_compare_int_usable(void) > cnt = read_c0_count(); > cnt += delta; > write_c0_compare(cnt); >- irq_disable_hazard(); >+ compare_change_hazard(); > if ((int)(read_c0_count() - cnt) < 0) > break; > /* increase delta if the timer was already expired */ >@@ -205,11 +143,12 @@ static int c0_compare_int_usable(void) > while ((int)(read_c0_count() - cnt) <= 0) > ; /* Wait for expiry */ > >+ compare_change_hazard(); > if (!c0_compare_int_pending()) > return 0; > > write_c0_compare(read_c0_count()); >- irq_disable_hazard(); >+ compare_change_hazard(); > if (c0_compare_int_pending()) > return 0; > -- Shinya Kuribayashi NEC Electronics From manuel.lauss@googlemail.com Tue Feb 23 18:56:55 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 23 Feb 2010 18:57:00 +0100 (CET) Received: from mail-bw0-f215.google.com ([209.85.218.215]:41941 "EHLO mail-bw0-f215.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1491978Ab0BWR4y (ORCPT ); Tue, 23 Feb 2010 18:56:54 +0100 Received: by bwz7 with SMTP id 7so2739603bwz.24 for ; Tue, 23 Feb 2010 09:56:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer; bh=bFsm9mbrKoMa4lXpF7K0Ny52QiZonU8UxyN0wPnUe2o=; b=Bx/1myWzGp++odHmC92rVHkYBmKZguc2QcX41Vga7VGYyLfiEvRGPdVkHYlzxHxBJM BaOurU/k8eY5Ypx2wS/+sFQxNZ+1K84l5CtIINf2g436r8CsmbqjGsREFlYhcLl/+yKd Rw9zKtft9k/bIiPKMtoICC2mqXoPMcqMiOZYo= DomainKey-Signature: a=rsa-sha1; c=nofws; d=googlemail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer; b=DRk8fLx8KErJ1rCSuvZV20N3inE5zSMagifcqq4a01UzTb3FjFcf2OXfglEoWubzFn gksLuh6HN0Z8pqDyifz+Bm3nXDqL9AuVHpeP/yQYXkfUHCsRDtfAEYPhDvMSkKh/2d5W MK3My81+X67s7fYGfKHtMIyjqD9R+vFh+UBRI= Received: by 10.204.32.198 with SMTP id e6mr1080159bkd.169.1266947807170; Tue, 23 Feb 2010 09:56:47 -0800 (PST) Received: from localhost.localdomain (p5496C184.dip.t-dialin.net [84.150.193.132]) by mx.google.com with ESMTPS id 15sm2025108bwz.12.2010.02.23.09.56.45 (version=TLSv1/SSLv3 cipher=RC4-MD5); Tue, 23 Feb 2010 09:56:46 -0800 (PST) From: Manuel Lauss To: Linux-MIPS Cc: Manuel Lauss Subject: [PATCH -queue] MIPS: Alchemy: devboard PM needs to save CPLD registers. Date: Tue, 23 Feb 2010 18:57:43 +0100 Message-Id: <1266947863-11738-1-git-send-email-manuel.lauss@gmail.com> X-Mailer: git-send-email 1.7.0 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25995 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips Save/restore CPLD registers when doing suspend-to-ram: fixes issues with harddisk and ethernet not working correctly when resuming on DB1200. Signed-off-by: Manuel Lauss --- arch/mips/alchemy/devboards/pm.c | 32 ++++++++++++++++++++++++++++++++ 1 files changed, 32 insertions(+), 0 deletions(-) diff --git a/arch/mips/alchemy/devboards/pm.c b/arch/mips/alchemy/devboards/pm.c index 632f986..4bbd313 100644 --- a/arch/mips/alchemy/devboards/pm.c +++ b/arch/mips/alchemy/devboards/pm.c @@ -10,6 +10,7 @@ #include #include #include +#include /* * Generic suspend userspace interface for Alchemy development boards. @@ -26,6 +27,20 @@ static unsigned long db1x_pm_last_wakesrc; static int db1x_pm_enter(suspend_state_t state) { + unsigned short bcsrs[16]; + int i, j, hasint; + + /* save CPLD regs */ + hasint = bcsr_read(BCSR_WHOAMI); + hasint = BCSR_WHOAMI_BOARD(hasint) >= BCSR_WHOAMI_DB1200; + j = (hasint) ? BCSR_MASKSET : BCSR_SYSTEM; + + for (i = BCSR_STATUS; i <= j; i++) + bcsrs[i] = bcsr_read(i); + + /* shut off hexleds */ + bcsr_write(BCSR_HEXCLEAR, 3); + /* enable GPIO based wakeup */ alchemy_gpio1_input_enable(); @@ -52,6 +67,23 @@ static int db1x_pm_enter(suspend_state_t state) /* ...and now the sandman can come! */ au_sleep(); + + /* restore CPLD regs */ + for (i = BCSR_STATUS; i <= BCSR_SYSTEM; i++) + bcsr_write(i, bcsrs[i]); + + /* restore CPLD int registers */ + if (hasint) { + bcsr_write(BCSR_INTCLR, 0xffff); + bcsr_write(BCSR_MASKCLR, 0xffff); + bcsr_write(BCSR_INTSTAT, 0xffff); + bcsr_write(BCSR_INTSET, bcsrs[BCSR_INTSET]); + bcsr_write(BCSR_MASKSET, bcsrs[BCSR_MASKSET]); + } + + /* light up hexleds */ + bcsr_write(BCSR_HEXCLEAR, 0); + return 0; } -- 1.7.0 From David.Daney@caviumnetworks.com Tue Feb 23 19:12:28 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 23 Feb 2010 19:12:32 +0100 (CET) Received: from mail3.caviumnetworks.com ([12.108.191.235]:3194 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492399Ab0BWSM2 (ORCPT ); Tue, 23 Feb 2010 19:12:28 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,7,2,8378) id ; Tue, 23 Feb 2010 10:12:35 -0800 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Tue, 23 Feb 2010 10:11:55 -0800 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Tue, 23 Feb 2010 10:11:55 -0800 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.3/8.14.2) with ESMTP id o1NIBp93008401; Tue, 23 Feb 2010 10:11:51 -0800 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.3/8.14.3/Submit) id o1NIBnbk008400; Tue, 23 Feb 2010 10:11:49 -0800 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: David Daney Subject: [PATCH] MIPS: Give Octeon+ CPUs their own __cpu_name Date: Tue, 23 Feb 2010 10:11:47 -0800 Message-Id: <1266948707-8357-1-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.6.6.1 X-OriginalArrivalTime: 23 Feb 2010 18:11:55.0869 (UTC) FILETIME=[AED300D0:01CAB4B3] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25996 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Signed-off-by: David Daney --- This couuld be rolled into the original linux-queue patch that extablishes CPU_CAVIUM_OCTEON_PLUS. arch/mips/kernel/cpu-probe.c | 7 ++++--- 1 files changed, 4 insertions(+), 3 deletions(-) diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index ee67aac..be5bb16 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -913,14 +913,15 @@ static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu) case PRID_IMP_CAVIUM_CN31XX: case PRID_IMP_CAVIUM_CN30XX: c->cputype = CPU_CAVIUM_OCTEON; - goto name_and_platform; + __cpu_name[cpu] = "Cavium Octeon"; + goto platform; case PRID_IMP_CAVIUM_CN58XX: case PRID_IMP_CAVIUM_CN56XX: case PRID_IMP_CAVIUM_CN50XX: case PRID_IMP_CAVIUM_CN52XX: c->cputype = CPU_CAVIUM_OCTEON_PLUS; -name_and_platform: - __cpu_name[cpu] = "Cavium Octeon"; + __cpu_name[cpu] = "Cavium Octeon+"; +platform: if (cpu == 0) __elf_platform = "octeon"; break; -- 1.6.6.1 From manuel.lauss@googlemail.com Tue Feb 23 19:21:35 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 23 Feb 2010 19:21:38 +0100 (CET) Received: from mail-bw0-f215.google.com ([209.85.218.215]:35946 "EHLO mail-bw0-f215.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492398Ab0BWSVf (ORCPT ); Tue, 23 Feb 2010 19:21:35 +0100 Received: by bwz7 with SMTP id 7so2763982bwz.24 for ; Tue, 23 Feb 2010 10:21:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer; bh=IVc3FI2PkNBvEf8PW4ddcYSg17ojnKgaRcjAsUrA+fU=; b=UPggQ6g2MtIAomAjZVPBHer2JF78Q6FkeF8WT1tZNACypBtgg+0dFpWLFAvBK7bzoO /Ml3OFxl6+4s5Vrm1f9sd1baRucZgoFygvPzR4dxLFyFQT0ogBZGLi9Ai8m/gpACv030 lJ/21crN0iXhTCeVRlJUUr6YoEn3sBcmPidn4= DomainKey-Signature: a=rsa-sha1; c=nofws; d=googlemail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer; b=ls4YkoxleD6+3FTue82El4TpMYtF5rxEME7YL7aXWmX7oQ/QoiJ6f6hwI7hVPTbHFz +wE7+pvSz7E/j9bNs3sqqmP/RRmLktfigb7KCWXbEIjOmJxgraE+2p8f1CkIh6kpwVkR rUx5rSqVTeAfOosbxLfkgbKf5eQplVcByXwaI= Received: by 10.204.49.82 with SMTP id u18mr3565231bkf.74.1266949289315; Tue, 23 Feb 2010 10:21:29 -0800 (PST) Received: from localhost.localdomain (p5496C184.dip.t-dialin.net [84.150.193.132]) by mx.google.com with ESMTPS id 15sm2041976bwz.12.2010.02.23.10.21.27 (version=TLSv1/SSLv3 cipher=RC4-MD5); Tue, 23 Feb 2010 10:21:28 -0800 (PST) From: Manuel Lauss To: Linux Serial Cc: Linux-MIPS , Manuel Lauss Subject: [RFC PATCH 0/2] serial 8250 platform PM hooks Date: Tue, 23 Feb 2010 19:22:25 +0100 Message-Id: <1266949347-12024-1-git-send-email-manuel.lauss@gmail.com> X-Mailer: git-send-email 1.7.0 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25997 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips The following 2 patches implement a PM hook for platform 8250 UARTs and a sample PM implementation for a MIPS SoC. Patch #1 hooks a new .pm callback in struct plat_serial8250_port to the rest of serial_core's PM infrastructure, Patch #2 implements uart power gating for Alchemy line of mips socs. With these 2 patches serial console on my test system survives suspend/resume cycles without having to resort to platform-specific hacks in the PM code. Thanks, Manuel Lauss Manuel Lauss (2): 8250: allow platform uarts to install PM callback. Alchemy: UART PM through serial framework. arch/mips/alchemy/common/platform.c | 17 +++++++++++++++++ arch/mips/alchemy/common/power.c | 35 ----------------------------------- drivers/serial/8250.c | 31 ++++++++++++++++++++++++++++--- include/linux/serial_8250.h | 6 ++++++ 4 files changed, 51 insertions(+), 38 deletions(-) From manuel.lauss@googlemail.com Tue Feb 23 19:21:57 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 23 Feb 2010 19:22:04 +0100 (CET) Received: from mail-bw0-f215.google.com ([209.85.218.215]:64350 "EHLO mail-bw0-f215.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492399Ab0BWSVh (ORCPT ); Tue, 23 Feb 2010 19:21:37 +0100 Received: by bwz7 with SMTP id 7so2764001bwz.24 for ; Tue, 23 Feb 2010 10:21:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer:in-reply-to:references; bh=ljzI/qDkZ6D2HAfNAglQ6KosIhPmDgIxmqlwVxAivTU=; b=P2w0YcR/eyr0tJQItrFoXJNkuZPgSnBg0iVPwZ7xaQJ43hOcKh8R9rSmrPwNIdrIlQ Dx3q4x9lxKFrNNMNx3sFhxpibWYWCA5RBzU8XsvOieuAMDhCZFPO5e9W66LDWvab6kN2 2TqeximnVWh9GlxGj0sNRwVaLyhetftxOAM2M= DomainKey-Signature: a=rsa-sha1; c=nofws; d=googlemail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; b=JoyAfMgGloZ6OmtR7qljaJZqX6UthptmIULH21B05Dy9JV2VRVpKu3YiTtSRCBfus/ dajR1hC7YTJ9rXmSvgT7k7KO7FbKr/aUdO0ivQZ38+DwC37TIIUWTO4pMJgk3oq3/yyy dhNpHIYkX5W2A4RmkxZ3YAZ+mMfigtkvXOt6A= Received: by 10.204.9.134 with SMTP id l6mr3565425bkl.83.1266949290980; Tue, 23 Feb 2010 10:21:30 -0800 (PST) Received: from localhost.localdomain (p5496C184.dip.t-dialin.net [84.150.193.132]) by mx.google.com with ESMTPS id 15sm2041976bwz.12.2010.02.23.10.21.29 (version=TLSv1/SSLv3 cipher=RC4-MD5); Tue, 23 Feb 2010 10:21:30 -0800 (PST) From: Manuel Lauss To: Linux Serial Cc: Linux-MIPS , Manuel Lauss Subject: [RFC PATCH 1/2] 8250: allow platform uarts to install PM callback. Date: Tue, 23 Feb 2010 19:22:26 +0100 Message-Id: <1266949347-12024-2-git-send-email-manuel.lauss@gmail.com> X-Mailer: git-send-email 1.7.0 In-Reply-To: <1266949347-12024-1-git-send-email-manuel.lauss@gmail.com> References: <1266949347-12024-1-git-send-email-manuel.lauss@gmail.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25998 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips The 8250 UART driver provides rudimentary UART PM support and a callback for systems to do more sophisticated power management. However, there is no way yet for platform_device uarts to assign something this internal callback. This patch adds a callback to struct plat_serial8250_port and a function to register this callback with 8250 driver internals. Signed-off-by: Manuel Lauss --- drivers/serial/8250.c | 31 ++++++++++++++++++++++++++++--- include/linux/serial_8250.h | 6 ++++++ 2 files changed, 34 insertions(+), 3 deletions(-) diff --git a/drivers/serial/8250.c b/drivers/serial/8250.c index a81ff7b..7802266 100644 --- a/drivers/serial/8250.c +++ b/drivers/serial/8250.c @@ -2966,7 +2966,7 @@ static int __devinit serial8250_probe(struct platform_device *dev) port.serial_out = p->serial_out; port.dev = &dev->dev; port.irqflags |= irqflag; - ret = serial8250_register_port(&port); + ret = serial8250_register_port_with_pm(&port, p->pm); if (ret < 0) { dev_err(&dev->dev, "unable to register port at index %d " "(IO%lx MEM%llx IRQ%d): %d\n", i, @@ -3078,8 +3078,10 @@ static struct uart_8250_port *serial8250_find_match_or_unused(struct uart_port * } /** - * serial8250_register_port - register a serial port + * serial8250_register_port_with_pm - register a serial port and its + * power management callback. * @port: serial port template + * @pm: PM callback for this port, can be NULL. * * Configure the serial port specified by the request. If the * port exists and is in use, it is hung up and unregistered @@ -3090,7 +3092,9 @@ static struct uart_8250_port *serial8250_find_match_or_unused(struct uart_port * * * On success the port is ready to use and the line number is returned. */ -int serial8250_register_port(struct uart_port *port) +int serial8250_register_port_with_pm(struct uart_port *port, + void(*pm)(struct uart_port *port, unsigned int state, + unsigned int old)) { struct uart_8250_port *uart; int ret = -ENOSPC; @@ -3115,6 +3119,7 @@ int serial8250_register_port(struct uart_port *port) uart->port.flags = port->flags | UPF_BOOT_AUTOCONF; uart->port.mapbase = port->mapbase; uart->port.private_data = port->private_data; + uart->pm = pm; if (port->dev) uart->port.dev = port->dev; @@ -3140,6 +3145,26 @@ int serial8250_register_port(struct uart_port *port) return ret; } +EXPORT_SYMBOL(serial8250_register_port_with_pm); + +/** + * serial8250_register_port - register a serial port + * @port: serial port template + * + * Configure the serial port specified by the request. If the + * port exists and is in use, it is hung up and unregistered + * first. + * + * The port is then probed and if necessary the IRQ is autodetected + * If this fails an error is returned. + * + * On success the port is ready to use and the line number is returned. + */ +int serial8250_register_port(struct uart_port *port) +{ + return serial8250_register_port_with_pm(port, NULL); +} + EXPORT_SYMBOL(serial8250_register_port); /** diff --git a/include/linux/serial_8250.h b/include/linux/serial_8250.h index fb46aba..25cc3fb 100644 --- a/include/linux/serial_8250.h +++ b/include/linux/serial_8250.h @@ -14,6 +14,9 @@ #include #include +typedef void(*plat8250_pm_func_t)(struct uart_port *port, unsigned int state, + unsigned int old_state); + /* * This is the platform device platform_data structure */ @@ -32,6 +35,8 @@ struct plat_serial8250_port { unsigned int type; /* If UPF_FIXED_TYPE */ unsigned int (*serial_in)(struct uart_port *, int); void (*serial_out)(struct uart_port *, int, int); + void (*pm)(struct uart_port *port, unsigned int state, + unsigned int old_state); }; /* @@ -62,6 +67,7 @@ enum { struct uart_port; int serial8250_register_port(struct uart_port *); +int serial8250_register_port_with_pm(struct uart_port *, plat8250_pm_func_t); void serial8250_unregister_port(int line); void serial8250_suspend_port(int line); void serial8250_resume_port(int line); -- 1.7.0 From manuel.lauss@googlemail.com Tue Feb 23 19:22:23 2010 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 23 Feb 2010 19:22:27 +0100 (CET) Received: from mail-bw0-f215.google.com ([209.85.218.215]:51691 "EHLO mail-bw0-f215.google.com" rhost-flags-OK-OK-OK-OK) by eddie.linux-mips.org with ESMTP id S1492408Ab0BWSVj (ORCPT ); Tue, 23 Feb 2010 19:21:39 +0100 Received: by bwz7 with SMTP id 7so2764020bwz.24 for ; Tue, 23 Feb 2010 10:21:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer:in-reply-to:references; bh=AXEIaJKpG6G4MJhf8jQlEGSHN3MGLWD4imR3TlXSjjQ=; b=Qo8Rxa4DAPYMdjjDsZTD/0Im9waoz8XMNlMqGvMxSEjHx3ABzHcEsD0Z6khEeMyTpb j0YvM64PBnaBXDyy+A1Cp97s5ZGB89gW1dCqt1klrsK2kHuZI3/xNA9GXEHU3yCUnCNd 6Kob2O0wmgbmpAHLK1qNHalE70TN/WIO1iwwE= DomainKey-Signature: a=rsa-sha1; c=nofws; d=googlemail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; b=XvqivZbeCgSYoCuv+QqKtykvromwhJdk/8N0+CucdetfEqS5mW8ZVAdER5FfVaFUD+ +4BYuzyjJiqSgHRDGn+27m3UWc0fWU6WTwlR5Hqfz8+8EAUPNQE9N2Gxd02s1hoZulmY dMpAgF7iE/URbBkvCgzaTb0NvjftiDXw2CSAM= Received: by 10.204.25.194 with SMTP id a2mr2266602bkc.191.1266949292508; Tue, 23 Feb 2010 10:21:32 -0800 (PST) Received: from localhost.localdomain (p5496C184.dip.t-dialin.net [84.150.193.132]) by mx.google.com with ESMTPS id 15sm2041976bwz.12.2010.02.23.10.21.31 (version=TLSv1/SSLv3 cipher=RC4-MD5); Tue, 23 Feb 2010 10:21:31 -0800 (PST) From: Manuel Lauss To: Linux Serial Cc: Linux-MIPS , Manuel Lauss Subject: [RFC PATCH 2/2] Alchemy: UART PM through serial framework. Date: Tue, 23 Feb 2010 19:22:27 +0100 Message-Id: <1266949347-12024-3-git-send-email-manuel.lauss@gmail.com> X-Mailer: git-send-email 1.7.0 In-Reply-To: <1266949347-12024-2-git-send-email-manuel.lauss@gmail.com> References: <1266949347-12024-1-git-send-email-manuel.lauss@gmail.com> <1266949347-12024-2-git-send-email-manuel.lauss@gmail.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 25999 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips Hook up the Alchemy on-chip uarts with the platform 8250 PM callback and enable/disable clocks to the uart blocks as needed. This allows to get rid of the devboard-specific uart pm hack in the Alchemy common code. Tested on Au1200/DB1200. Signed-off-by: Manuel Lauss --- This patch applies against Ralf Baechle's mips-queue tree. arch/mips/alchemy/common/platform.c | 17 +++++++++++++++++ arch/mips/alchemy/common/power.c | 35 ----------------------------------- 2 files changed, 17 insertions(+), 35 deletions(-) diff --git a/arch/mips/alchemy/common/platform.c b/arch/mips/alchemy/common/platform.c index 3fbe30c..a85d515 100644 --- a/arch/mips/alchemy/common/platform.c +++ b/arch/mips/alchemy/common/platform.c @@ -21,6 +21,22 @@ #include #include +static void alchemy_8250_pm(struct uart_port *port, unsigned int state, + unsigned int old_state) +{ + if (state == 0) { /* power on */ + __raw_writel(0, port->membase + UART_MOD_CNTRL); + wmb(); + __r