From ralf@linux-mips.org Sun Nov 1 07:33:07 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 01 Nov 2009 07:33:10 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:47448 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-FAIL) by ftp.linux-mips.org with ESMTP id S1492381AbZKAGdH (ORCPT ); Sun, 1 Nov 2009 07:33:07 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id nA16YQew008813; Sun, 1 Nov 2009 07:34:28 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id nA16YPAA008809; Sun, 1 Nov 2009 07:34:25 +0100 Date: Sun, 1 Nov 2009 07:34:23 +0100 From: Ralf Baechle To: Manuel Lauss Cc: Linux-MIPS , Manuel Lauss Subject: Re: [PATCH -queue v2] MIPS: Alchemy: UARTs are of type 16550A Message-ID: <20091101063421.GA4551@linux-mips.org> References: <1256762986-4416-1-git-send-email-manuel.lauss@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1256762986-4416-1-git-send-email-manuel.lauss@gmail.com> User-Agent: Mutt/1.5.19 (2009-01-05) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24594 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Wed, Oct 28, 2009 at 09:49:46PM +0100, Manuel Lauss wrote: > UART autodetection breaks on the Au1300 but the IP blocks are identical, > at least according to the datasheets. Help the 8250 driver by passing > on uart type information via platform data. > > Signed-off-by: Manuel Lauss > --- > On top of the other alchemy patches in mips-queue. Thanks, queued. Ralf From ralf@linux-mips.org Sun Nov 1 08:07:45 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 01 Nov 2009 08:07:48 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:37314 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-FAIL) by ftp.linux-mips.org with ESMTP id S1492554AbZKAHHp (ORCPT ); Sun, 1 Nov 2009 08:07:45 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id nA1794q1009535; Sun, 1 Nov 2009 08:09:04 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id nA1790L8009518; Sun, 1 Nov 2009 08:09:00 +0100 Date: Sun, 1 Nov 2009 08:09:00 +0100 From: Ralf Baechle To: Manuel Lauss Cc: Andrew Morton , linux-serial@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mips@linux-mips.org, Manuel Lauss Subject: Re: [PATCH] serial 8250: fixes for Alchemy uarts. Message-ID: <20091101070900.GB4551@linux-mips.org> References: <1256762248-4305-1-git-send-email-manuel.lauss@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1256762248-4305-1-git-send-email-manuel.lauss@gmail.com> User-Agent: Mutt/1.5.19 (2009-01-05) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24595 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Wed, Oct 28, 2009 at 09:37:28PM +0100, Manuel Lauss wrote: > Limit the amount of address space claimed for Alchemy serial ports > to 0x1000. On the Au1300, ports are only 0x1000 apart, and the > registers only extend to 0x110 at most on all supported alchemy models. > > On the Au1300 the autodetect logic no longer works and this makes > it necessary to specify the port type through platform data. Because > of this the MSR quirk needs to be moved outside the autoconfig() > function which will no longer be called when UPF_FIXED_TYPE is > specified. Andrew, looks sane to me. Since this is a MIPS patch I'd like to funnel it through the MIPS tree. Ok? Ralf From ralf@linux-mips.org Sun Nov 1 08:12:44 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 01 Nov 2009 08:12:48 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:43407 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-FAIL) by ftp.linux-mips.org with ESMTP id S1492574AbZKAHMo (ORCPT ); Sun, 1 Nov 2009 08:12:44 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id nA17E7Z8009632; Sun, 1 Nov 2009 08:14:07 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id nA17E7lv009630; Sun, 1 Nov 2009 08:14:07 +0100 Date: Sun, 1 Nov 2009 08:14:07 +0100 From: Ralf Baechle To: "wilbur.chan" Cc: Linux MIPS Mailing List Subject: Re: Problem in booting when calling calibrate_delay Message-ID: <20091101071407.GC4551@linux-mips.org> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.19 (2009-01-05) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24596 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Thu, Oct 29, 2009 at 07:51:52AM +0800, wilbur.chan wrote: > I was going to boot mips64 xlr408, which has 8 cores. The XLR is not supported by the linux-mips.org rsp. kernel.org kernel trees. > Howerver, the code seemd to stop before calling 'start_kernel---> > > calibrate_delay ' . > > So Iadded some 'printk' in calibrate_delay, to check out why it failed. > However, if I added a 'printk' in any 'if branches' in > > 'calibrate_delay ' function , the kernel would halt before calling > > > 'j start_kernel' in head.S. (in this situation ,printk seemed > > unavailable, so I wrote directlly to serial address to trace the > > kernel). > > > Can anyone tell me why this happed? When something like this happens it is in most cases caused by timer interrupt not working. Ralf From akpm@linux-foundation.org Sun Nov 1 08:16:46 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 01 Nov 2009 08:16:53 +0100 (CET) Received: from smtp1.linux-foundation.org ([140.211.169.13]:39541 "EHLO smtp1.linux-foundation.org" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492586AbZKAHQq (ORCPT ); Sun, 1 Nov 2009 08:16:46 +0100 Received: from imap1.linux-foundation.org (imap1.linux-foundation.org [140.211.169.55]) by smtp1.linux-foundation.org (8.14.2/8.13.5/Debian-3ubuntu1.1) with ESMTP id nA17Gbba027855 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Sun, 1 Nov 2009 00:16:38 -0700 Received: from y.localdomain (localhost [127.0.0.1]) by imap1.linux-foundation.org (8.13.5.20060308/8.13.5/Debian-3ubuntu1.1) with SMTP id nA17GXCS014372; Sun, 1 Nov 2009 00:16:35 -0700 Date: Sun, 1 Nov 2009 00:16:33 -0700 From: Andrew Morton To: Ralf Baechle Cc: Manuel Lauss , linux-serial@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mips@linux-mips.org, Manuel Lauss Subject: Re: [PATCH] serial 8250: fixes for Alchemy uarts. Message-Id: <20091101001633.6ce9d957.akpm@linux-foundation.org> In-Reply-To: <20091101070900.GB4551@linux-mips.org> References: <1256762248-4305-1-git-send-email-manuel.lauss@gmail.com> <20091101070900.GB4551@linux-mips.org> X-Mailer: Sylpheed 2.4.8 (GTK+ 2.12.5; x86_64-redhat-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-MIMEDefang-Filter: lf$Revision: 1.188 $ X-Scanned-By: MIMEDefang 2.63 on 140.211.169.13 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24597 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: akpm@linux-foundation.org Precedence: bulk X-list: linux-mips On Sun, 1 Nov 2009 08:09:00 +0100 Ralf Baechle wrote: > On Wed, Oct 28, 2009 at 09:37:28PM +0100, Manuel Lauss wrote: > > > Limit the amount of address space claimed for Alchemy serial ports > > to 0x1000. On the Au1300, ports are only 0x1000 apart, and the > > registers only extend to 0x110 at most on all supported alchemy models. > > > > On the Au1300 the autodetect logic no longer works and this makes > > it necessary to specify the port type through platform data. Because > > of this the MSR quirk needs to be moved outside the autoconfig() > > function which will no longer be called when UPF_FIXED_TYPE is > > specified. > > Andrew, > > looks sane to me. Since this is a MIPS patch I'd like to funnel it through > the MIPS tree. Ok? Sure. From ralf@linux-mips.org Sun Nov 1 08:41:55 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 01 Nov 2009 08:41:58 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:38618 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-FAIL) by ftp.linux-mips.org with ESMTP id S1492452AbZKAHlz (ORCPT ); Sun, 1 Nov 2009 08:41:55 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id nA17hIAr013203; Sun, 1 Nov 2009 08:43:19 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id nA17hHiW013201; Sun, 1 Nov 2009 08:43:17 +0100 Date: Sun, 1 Nov 2009 08:43:17 +0100 From: Ralf Baechle To: Chih-hung Lu Cc: Wu Zhangjin , Linux-MIPS Subject: Re: [PATCH -v1] MIPS: a few of fixups and cleanups for the compressed kernel support Message-ID: <20091101074317.GD4551@linux-mips.org> References: <1256797212-7794-1-git-send-email-wuzhangjin@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.19 (2009-01-05) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24598 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Fri, Oct 30, 2009 at 10:16:14AM +0800, Chih-hung Lu wrote: > May I ask a question, > what is the difference between "addu a0, 4" and "addiu a0, a0, 4"? That's because you are human - you're smart enough to notice the difference without even thinking about it :) The machine instructions addu and addiu differ. Addiu takes an immediate constant as it's last op. Addu takes a register instead. Now the assembler is trying to make things a little easier to us. Depending on the type of the last argument it will assemble an "addu" assembler instruction either into an addiu or addu. The other difference between the two instructions used in your example is that the first has two operands, the other three operands. If there is only two operands, the assembler will implicitly assume, that the 2nd register is the same as the first register. Or in other words, the code generated from both will be entirely identical. Ralf From miloody@gmail.com Sun Nov 1 15:18:24 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 01 Nov 2009 15:18:31 +0100 (CET) Received: from mail-pz0-f194.google.com ([209.85.222.194]:49696 "EHLO mail-pz0-f194.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492455AbZKAOSY (ORCPT ); Sun, 1 Nov 2009 15:18:24 +0100 Received: by pzk32 with SMTP id 32so2841335pzk.21 for ; Sun, 01 Nov 2009 06:18:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:date:message-id:subject :from:to:content-type; bh=Rt2L/ZB+Z17wJIaWyEFr4okbRv6QaYlauMGBX+WpmUw=; b=xtrT4Bfb//mT/CwkehSmSCMzruCCyuxLMFPSSwzjOr5hHPVkmFrJ14V/VDFxOovf6m P6HFMavxM7x1+OW1dR/GYkNR7p+78Tf3hhhDxHkIdnhpMAk4bErP2EV1qH9hr1OZdNiZ wJWXM7g40HnB3X0TniU63nwd56L/7HMxzJHWI= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:date:message-id:subject:from:to:content-type; b=yDpl2u+Hj5iLSTRTekjQEW6SsaqOUG91d/zNnPgDMhAk8eDMqi5BXPU8FZfmEs6ggO t2LiTl6Rc+kyT6KvP5FvbqXsW5rQNl5ukgTNUhKJROc/f2XKOaLZqhdFLpUnYIJc/78K J8/atAyYEYjhEFpuah7Huz2eTcYQ9PEWE+7VE= MIME-Version: 1.0 Received: by 10.142.152.1 with SMTP id z1mr324756wfd.322.1257085094528; Sun, 01 Nov 2009 06:18:14 -0800 (PST) Date: Sun, 1 Nov 2009 22:18:14 +0800 Message-ID: <3a665c760911010618u7216cd68wfbd02610d2029862@mail.gmail.com> Subject: why we use multu to implement udelay From: loody To: Linux MIPS Mailing List Content-Type: text/plain; charset=ISO-8859-1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24599 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: miloody@gmail.com Precedence: bulk X-list: linux-mips Dear all: If I search the right place in mip kernel, I find the kernel implement udelay by multu and bnez looping, in 32-bits mode. if (sizeof(long) == 4) __asm__("multu\t%2, %3" : "=h" (usecs), "=l" (lo) : "r" (usecs), "r" (lpj) : GCC_REG_ACCUM); else if (sizeof(long) == 8) __asm__("dmultu\t%2, %3" : "=h" (usecs), "=l" (lo) : "r" (usecs), "r" (lpj) : GCC_REG_ACCUM); __delay(usecs); why we doing so instead of using kernel timer function and the precision will be incorrect if the cpu runs faster or slower, right? appreciate your help, miloody From wilbur512@gmail.com Sun Nov 1 16:18:37 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 01 Nov 2009 16:18:44 +0100 (CET) Received: from mail-gx0-f227.google.com ([209.85.217.227]:38323 "EHLO mail-gx0-f227.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1493773AbZKAPSh convert rfc822-to-8bit (ORCPT ); Sun, 1 Nov 2009 16:18:37 +0100 Received: by gxk27 with SMTP id 27so431663gxk.7 for ; Sun, 01 Nov 2009 07:18:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:in-reply-to:references :date:message-id:subject:from:to:cc:content-type :content-transfer-encoding; bh=R0sNxzuV+TV78/1vjRkwuqdZb8K/8bv0t2rRAYWDA1Q=; b=K5sfSWXi28I0taRy4zKjuHu5l/G/uUKfF/NxySUFB0YzMllnIA/g06WLPOR9cF4D46 uB/FUNyw/Sa9ZWruHzHbFBrfxETBaFng3s0B8zck9+k8CFpN26JS8JGQxshdOBcTlwpA l7PGemcPpyOuyVdOS1S5enMEXseeRLvv7zrVg= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type:content-transfer-encoding; b=Jpwqu7uIYY2rgchtFoRtVBWQx/QVuLnVtEQlnjkILy6VQK5u5SJPoywVLJnkRBHw9f xi/ejdBo5EGxHV4kinxB/OHGtWuJ3ou+lkSqu2vvTW+ruv+vi01RmFQXHv2yI6yxGqHn YoZ6GCkDnsUIZkabDs95xuMJmVTp/TVX+plO8= MIME-Version: 1.0 Received: by 10.90.62.21 with SMTP id k21mr7840940aga.10.1257088711086; Sun, 01 Nov 2009 07:18:31 -0800 (PST) In-Reply-To: <20091101071407.GC4551@linux-mips.org> References: <20091101071407.GC4551@linux-mips.org> Date: Sun, 1 Nov 2009 23:18:31 +0800 Message-ID: Subject: Re: Problem in booting when calling calibrate_delay From: "wilbur.chan" To: Ralf Baechle Cc: Linux MIPS Mailing List Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24600 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wilbur512@gmail.com Precedence: bulk X-list: linux-mips 2009/11/1 Ralf Baechle : > On Thu, Oct 29, 2009 at 07:51:52AM +0800, wilbur.chan wrote: > >> Howerver, the code seemd to stop before calling 'start_kernel---> >> >> calibrate_delay ' . >> > When something like this happens it is in most cases caused by timer > interrupt not working. > >  Ralf > Hi, ralf , I found that, jiffies remain the same when booting , so calibrate_delay loop all the time , at while(ticks==jiffies); I guess it was the problem of timer interrupt as you said. Someone told me that , it might be the problem of console_init ,but I still don't know where exactly the problem is . Can you tell more about how to fix this ? Thx From ralf@linux-mips.org Mon Nov 2 06:58:19 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 02 Nov 2009 06:58:22 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:42327 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-FAIL) by ftp.linux-mips.org with ESMTP id S1492160AbZKBF6T (ORCPT ); Mon, 2 Nov 2009 06:58:19 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id nA25xca6012954; Mon, 2 Nov 2009 06:59:38 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id nA25xZ6p012951; Mon, 2 Nov 2009 06:59:35 +0100 Date: Mon, 2 Nov 2009 06:59:34 +0100 From: Ralf Baechle To: Robert Richter Cc: Wu Zhangjin , linux-mips@linux-mips.org, John Levon , oprofile-list@lists.sourceforge.net Subject: Re: [PATCH] oprofile/loongson2: rename cpu_type from godson2 to loongson2 Message-ID: <20091102055934.GA10689@linux-mips.org> References: <1256136706-27810-1-git-send-email-wuzhangjin@gmail.com> <20091021165907.GJ11972@erda.amd.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20091021165907.GJ11972@erda.amd.com> User-Agent: Mutt/1.5.19 (2009-01-05) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24601 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Wed, Oct 21, 2009 at 06:59:07PM +0200, Robert Richter wrote: > On 21.10.09 22:51:46, Wu Zhangjin wrote: > > This patch try to unify the naming method between kernel and the > > user-space oprofile tool. 'Cause loongson is used instead of godson in > > most of the places, and just confer with the developer of the user-space > > tool, we are agreed to use loongson instead, which will help a lot to > > the future maintaining. > > > > (This patch is very important to help the user-space support upstream, > > so, Ralf, could you please merge it into your -queue branch, thanks!) Applied to master, not queue. The name is part of an API, so cosmetic changes like this are to be avoided. Fortunately the oprofile code in question is still fairly new, hasn't been art of any stable kernel release yet so it better go into the kernel now than later. > > Signed-off-by: Wu Zhangjin > > Acked-by: Robert Richter > > Ralf, please apply to your tree. Ralf From ralf@linux-mips.org Mon Nov 2 07:49:12 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 02 Nov 2009 07:49:14 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:51913 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-FAIL) by ftp.linux-mips.org with ESMTP id S1492638AbZKBGtL (ORCPT ); Mon, 2 Nov 2009 07:49:11 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id nA26oZq3014317; Mon, 2 Nov 2009 07:50:35 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id nA26oYqc014308; Mon, 2 Nov 2009 07:50:34 +0100 Date: Mon, 2 Nov 2009 07:50:34 +0100 From: Ralf Baechle To: Arnaud Patard Cc: linux-mips@linux-mips.org Subject: Re: [PATCH] Fix ppoll on o32 with 64bit kernel Message-ID: <20091102065033.GA13360@linux-mips.org> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.19 (2009-01-05) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24602 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Tue, Oct 20, 2009 at 10:27:47AM +0200, Arnaud Patard wrote: > sys_ppoll syscall needs to use a compat handler on 64bit kernels with > o32 user-space. This patch wires it. > > Signed-off-by: Arnaud Patard Cute. This one applies to all kernel from 2.6.16 up. Applied, thanks! Ralf From ralf@linux-mips.org Mon Nov 2 08:16:00 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 02 Nov 2009 08:16:03 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:34616 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-FAIL) by ftp.linux-mips.org with ESMTP id S1492732AbZKBHQA (ORCPT ); Mon, 2 Nov 2009 08:16:00 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id nA27HPkU014921; Mon, 2 Nov 2009 08:17:25 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id nA27HOeZ014919; Mon, 2 Nov 2009 08:17:24 +0100 Date: Mon, 2 Nov 2009 08:17:24 +0100 From: Ralf Baechle To: loody Cc: Linux MIPS Mailing List Subject: Re: why we use multu to implement udelay Message-ID: <20091102071724.GB13360@linux-mips.org> References: <3a665c760911010618u7216cd68wfbd02610d2029862@mail.gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <3a665c760911010618u7216cd68wfbd02610d2029862@mail.gmail.com> User-Agent: Mutt/1.5.19 (2009-01-05) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24603 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Sun, Nov 01, 2009 at 10:18:14PM +0800, loody wrote: > If I search the right place in mip kernel, I find the kernel implement > udelay by multu and bnez looping, in 32-bits mode. > if (sizeof(long) == 4) > __asm__("multu\t%2, %3" > : "=h" (usecs), "=l" (lo) > : "r" (usecs), "r" (lpj) > : GCC_REG_ACCUM); > else if (sizeof(long) == 8) > __asm__("dmultu\t%2, %3" > : "=h" (usecs), "=l" (lo) > : "r" (usecs), "r" (lpj) > : GCC_REG_ACCUM); > > __delay(usecs); > why we doing so instead of using kernel timer function and the > precision will be incorrect if the cpu runs faster or slower, right? This is an old-fashioned implementation which will work even on systems where no CPU timer is available or its frequency is unknown or variable. A while ago patches were posted to use the cp0 counter instead but do to other necessary rewrites those patches went stale, so need to be reworked before they can be applied. Either way, for above restrictions the delay by looping implementation will still be needed as the fallback implementation. Ralf From ralf@linux-mips.org Mon Nov 2 12:28:36 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 02 Nov 2009 12:28:39 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:36055 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-FAIL) by ftp.linux-mips.org with ESMTP id S1493849AbZKBL2g (ORCPT ); Mon, 2 Nov 2009 12:28:36 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id nA2BTvjt003267; Mon, 2 Nov 2009 12:29:58 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id nA2BTtVO003265; Mon, 2 Nov 2009 12:29:55 +0100 Date: Mon, 2 Nov 2009 12:29:55 +0100 From: Ralf Baechle To: Manuel Lauss Cc: Florian Fainelli , linux-mips@linux-mips.org Subject: Re: [PATCH 1/2] alchemy: fix warnings in db1x00/pb1000/pb1550 board setup code Message-ID: <20091102112955.GA2821@linux-mips.org> References: <200910181604.11732.florian@openwrt.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.19 (2009-01-05) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24604 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Mon, Oct 19, 2009 at 01:12:15PM +0200, Manuel Lauss wrote: > I like it, thank you! Except that it a) does things the comments don't mention and b) doesn't apply on top of master or -queue ... Ralf From manuel.lauss@googlemail.com Mon Nov 2 12:43:26 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 02 Nov 2009 12:43:32 +0100 (CET) Received: from mail-bw0-f221.google.com ([209.85.218.221]:52643 "EHLO mail-bw0-f221.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1493838AbZKBLn0 (ORCPT ); Mon, 2 Nov 2009 12:43:26 +0100 Received: by bwz21 with SMTP id 21so6142656bwz.24 for ; Mon, 02 Nov 2009 03:43:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=domainkey-signature:mime-version:received:in-reply-to:references :date:message-id:subject:from:to:cc:content-type; bh=3zhy4PTl+VqzfJXPMsuBbS7WFVbrU6XimSyYW9G6r8A=; b=VhnOvkPuvRuoS1EqNB363nHPu2dyw3/8UljcFwPkaKTSLz4Q/KHjvx5LJLqDEc+XMN ETFQN0iUF0MydhHFOhvtUWqC/p0rxbXYnJiZBLCp/7yEkdHv77IOJh709MM/OKDMU+u1 5THKD8WjAeteuYH/kkDaGA9Ugi/KNEn9J1zso= DomainKey-Signature: a=rsa-sha1; c=nofws; d=googlemail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type; b=Zy+34hCOKQmFUoH/PQ3o5HdNthCkErUCbuvRhEPr7i6sp5wxUeAUbItJ35CKNUi7IA S8kN5NJPq/8xoLxbDNtCEalEdOdA0/5Vhvzk5BmWCNVbKWvO2egFhu5h2LkhKN5h6gxi tP3oLg60IEIIuZARh0t7XdvbvbZQGi6AVpyUM= MIME-Version: 1.0 Received: by 10.223.20.85 with SMTP id e21mr743846fab.25.1257162200693; Mon, 02 Nov 2009 03:43:20 -0800 (PST) In-Reply-To: <20091102112955.GA2821@linux-mips.org> References: <200910181604.11732.florian@openwrt.org> <20091102112955.GA2821@linux-mips.org> Date: Mon, 2 Nov 2009 12:43:20 +0100 Message-ID: Subject: Re: [PATCH 1/2] alchemy: fix warnings in db1x00/pb1000/pb1550 board setup code From: Manuel Lauss To: Ralf Baechle Cc: Florian Fainelli , linux-mips@linux-mips.org Content-Type: text/plain; charset=ISO-8859-1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24605 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips On Mon, Nov 2, 2009 at 12:29 PM, Ralf Baechle wrote: > On Mon, Oct 19, 2009 at 01:12:15PM +0200, Manuel Lauss wrote: > >> I like it, thank you! > > Except that it a) does things the comments don't mention and b) doesn't It does eliminate all the "variable may be unused"-type warnings... > apply on top of master or -queue ... It did apply against -queue when Floarian initally sent it. If he doesn't resurface in the next few days I'll send an update version. Manuel From ralf@linux-mips.org Mon Nov 2 13:59:53 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 02 Nov 2009 13:59:56 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:57608 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-FAIL) by ftp.linux-mips.org with ESMTP id S1493874AbZKBM7x (ORCPT ); Mon, 2 Nov 2009 13:59:53 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id nA2D1EFx021328; Mon, 2 Nov 2009 14:01:14 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id nA2D1DCt021327; Mon, 2 Nov 2009 14:01:13 +0100 Date: Mon, 2 Nov 2009 14:01:13 +0100 From: Ralf Baechle To: Manuel Lauss Cc: Florian Fainelli , linux-mips@linux-mips.org Subject: Re: [PATCH 1/2] alchemy: fix warnings in db1x00/pb1000/pb1550 board setup code Message-ID: <20091102130113.GA7292@linux-mips.org> References: <200910181604.11732.florian@openwrt.org> <20091102112955.GA2821@linux-mips.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.19 (2009-01-05) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24606 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Mon, Nov 02, 2009 at 12:43:20PM +0100, Manuel Lauss wrote: > On Mon, Nov 2, 2009 at 12:29 PM, Ralf Baechle wrote: > > On Mon, Oct 19, 2009 at 01:12:15PM +0200, Manuel Lauss wrote: > > > >> I like it, thank you! > > > > Except that it a) does things the comments don't mention and b) doesn't > > It does eliminate all the "variable may be unused"-type warnings... > > > > apply on top of master or -queue ... > > It did apply against -queue when Floarian initally sent it. If he doesn't > resurface in the next few days I'll send an update version. My bad. Applied now. Ralf From ralf@linux-mips.org Mon Nov 2 14:02:01 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 02 Nov 2009 14:02:04 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:34913 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-FAIL) by ftp.linux-mips.org with ESMTP id S1493878AbZKBNCB (ORCPT ); Mon, 2 Nov 2009 14:02:01 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id nA2D3Rxh021383; Mon, 2 Nov 2009 14:03:27 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id nA2D3RPA021381; Mon, 2 Nov 2009 14:03:27 +0100 Date: Mon, 2 Nov 2009 14:03:27 +0100 From: Ralf Baechle To: Florian Fainelli Cc: linux-mips@linux-mips.org, Manuel Lauss Subject: Re: [PATCH 2/2] alchemy: turn on -Werror for devboards and xss1500 Message-ID: <20091102130327.GA6205@linux-mips.org> References: <200910181604.42580.florian@openwrt.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <200910181604.42580.florian@openwrt.org> User-Agent: Mutt/1.5.19 (2009-01-05) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24607 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Sun, Oct 18, 2009 at 04:04:41PM +0200, Florian Fainelli wrote: > Warnings being suppressed, we can now turn on -Werror > for boards which did not have it already (devboards and > xss1500). > > Signed-off-by: Florian Fainelli Applied as well. Ralf From ralf@linux-mips.org Mon Nov 2 14:12:54 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 02 Nov 2009 14:12:59 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:55103 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-FAIL) by ftp.linux-mips.org with ESMTP id S1493879AbZKBNMx (ORCPT ); Mon, 2 Nov 2009 14:12:53 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id nA2DEGQD022140; Mon, 2 Nov 2009 14:14:16 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id nA2DEEvG022138; Mon, 2 Nov 2009 14:14:14 +0100 Date: Mon, 2 Nov 2009 14:14:14 +0100 From: Ralf Baechle To: Wu Zhangjin Cc: Linux-MIPS , yanh@lemote.com, huhb@lemote.com, Zhang Le , zhangfx@lemote.com Subject: Re: [PATCH -queue 1/7] [loongson] fuloong2e: Cleanup the Kconfig Message-ID: <20091102131414.GA21563@linux-mips.org> References: <83f0ebe8e34e5da49d0cb3487a7ef53f4edd69af.1255673756.git.wuzhangjin@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <83f0ebe8e34e5da49d0cb3487a7ef53f4edd69af.1255673756.git.wuzhangjin@gmail.com> User-Agent: Mutt/1.5.19 (2009-01-05) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24608 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Fri, Oct 16, 2009 at 02:17:14PM +0800, Wu Zhangjin wrote: > This patch replace the indention from whitespace to tab in > arch/mips/loongson/Kconfig. Thanks, queued for 2.6.33. Ralf From ralf@linux-mips.org Mon Nov 2 14:17:13 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 02 Nov 2009 14:17:16 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:44297 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-FAIL) by ftp.linux-mips.org with ESMTP id S1493888AbZKBNRN (ORCPT ); Mon, 2 Nov 2009 14:17:13 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id nA2DIblm022356; Mon, 2 Nov 2009 14:18:37 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id nA2DIbTg022354; Mon, 2 Nov 2009 14:18:37 +0100 Date: Mon, 2 Nov 2009 14:18:37 +0100 From: Ralf Baechle To: Wu Zhangjin Cc: Linux-MIPS , yanh@lemote.com, huhb@lemote.com, Zhang Le , zhangfx@lemote.com Subject: Re: [PATCH -queue 3/7] [loongson] early_printk: fix the variable type of uart_base Message-ID: <20091102131837.GB21563@linux-mips.org> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.19 (2009-01-05) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24609 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Fri, Oct 16, 2009 at 02:17:16PM +0800, Wu Zhangjin wrote: > The uart_base variable here is not a physical address, so, we replace it > by unsigned char *. > > Signed-off-by: Wu Zhangjin Thanks, queued for 2.6.33. Ralf From ralf@linux-mips.org Mon Nov 2 14:28:19 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 02 Nov 2009 14:28:22 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:41002 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-FAIL) by ftp.linux-mips.org with ESMTP id S1493892AbZKBN2T (ORCPT ); Mon, 2 Nov 2009 14:28:19 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id nA2DTgSE022669; Mon, 2 Nov 2009 14:29:42 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id nA2DTehS022667; Mon, 2 Nov 2009 14:29:40 +0100 Date: Mon, 2 Nov 2009 14:29:40 +0100 From: Ralf Baechle To: Wu Zhangjin Cc: Linux-MIPS , yanh@lemote.com, huhb@lemote.com, Zhang Le , zhangfx@lemote.com Subject: Re: [PATCH -queue 4/7] [loongosn] add a new serial port debug function Message-ID: <20091102132940.GC21563@linux-mips.org> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.19 (2009-01-05) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24610 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Fri, Oct 16, 2009 at 02:17:17PM +0800, Wu Zhangjin wrote: > There is an existing serial port debug function: prom_putchar(), but it > can only print one char, herein add a new prom_printf(), which works > like printk, but print to serial port, which is very important to kernel > debugging. Does this mean early_printk doesn't work for you? We rather get that to work for you than introducing something equivalent. Ralf From ralf@linux-mips.org Mon Nov 2 14:42:08 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 02 Nov 2009 14:42:11 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:54358 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-FAIL) by ftp.linux-mips.org with ESMTP id S1493895AbZKBNmI (ORCPT ); Mon, 2 Nov 2009 14:42:08 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id nA2DhQ2M023187; Mon, 2 Nov 2009 14:43:26 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id nA2DhPIs023185; Mon, 2 Nov 2009 14:43:25 +0100 Date: Mon, 2 Nov 2009 14:43:25 +0100 From: Ralf Baechle To: Wu Zhangjin Cc: Linux-MIPS , yanh@lemote.com, huhb@lemote.com, Zhang Le , zhangfx@lemote.com Subject: Re: [PATCH -queue 5/7] [loongson] add serial port support Message-ID: <20091102134325.GD21563@linux-mips.org> References: <35c04cb5cd3aa4c2d2fc3cbb471304a7f3434ebb.1255673756.git.wuzhangjin@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <35c04cb5cd3aa4c2d2fc3cbb471304a7f3434ebb.1255673756.git.wuzhangjin@gmail.com> User-Agent: Mutt/1.5.19 (2009-01-05) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24611 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Fri, Oct 16, 2009 at 02:17:18PM +0800, Wu Zhangjin wrote: > This patch add serial port support for all of the existing loongson > family machines. most of the board specific part are put in serial.c, > and the base address of the serial ports are defined as macros in > machine.h for sharing it between serial.c and early_printk.c Thanks, queued for 2.6.33. Ralf From manuel.lauss@googlemail.com Mon Nov 2 14:57:11 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 02 Nov 2009 14:57:17 +0100 (CET) Received: from mail-bw0-f221.google.com ([209.85.218.221]:65164 "EHLO mail-bw0-f221.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1493138AbZKBN5L convert rfc822-to-8bit (ORCPT ); Mon, 2 Nov 2009 14:57:11 +0100 Received: by bwz21 with SMTP id 21so6287267bwz.24 for ; Mon, 02 Nov 2009 05:57:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=domainkey-signature:mime-version:received:in-reply-to:references :date:message-id:subject:from:to:cc:content-type :content-transfer-encoding; bh=zs8JviXmnYJTQ8coPMYjyIzlGTycL6/+YF6WtAIUkis=; b=d2ggYDqlDND8Bato0+ET0E1hSBj331L+mw+tXdFGMDdDiIK0EcryVWPul0oY2MsJZN dqsbkokQb1Yqquyet0mhL2PRx1eV//ru5+151sQytJ8HQzqRNH5K4JuU0I7+T2/EijSO MtkIq9GoQoM2qCp6KGPoyle0JRyihu9/+BBvI= DomainKey-Signature: a=rsa-sha1; c=nofws; d=googlemail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type:content-transfer-encoding; b=xlI4oTH/nFAiwju5n7qFRWtFXCT6y3ILR59n8NcZBi2aq2YnCpp6A/1ISVnOdFLcs2 Yb5E4fvgulcwckvbC+7zsdvYDhKziVe5X3tlkXUCMSFwlmVSTeRW3xT7xQBtKwnRGUOZ dMJVd+nHQFhTgOx9WTA+hsTA+bBGzr3mqsx+g= MIME-Version: 1.0 Received: by 10.223.25.27 with SMTP id x27mr788684fab.7.1257170226103; Mon, 02 Nov 2009 05:57:06 -0800 (PST) In-Reply-To: <1257167962.8374.0.camel@kh-d280-64> References: <1255949617-22943-1-git-send-email-manuel.lauss@gmail.com> <1257167962.8374.0.camel@kh-d280-64> Date: Mon, 2 Nov 2009 14:57:06 +0100 Message-ID: Subject: Re: [PATCH] MIPS: Alchemy: physmap-flash for all devboards From: Manuel Lauss To: Kevin Hickey Cc: Ralf Baechle , Linux-MIPS , Manuel Lauss Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24612 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips On Mon, Nov 2, 2009 at 2:19 PM, Kevin Hickey wrote: > On Sat, 2009-10-31 at 17:13 +0100, Manuel Lauss wrote: >> Ping? Any comments? Flames? >> > I will look this over today or tomorrow.  I'm interested in this patch > but haven't had the time to review it.  Now I'll make the time :) Please do. To test swapboot, just dump yamon from the default partition, and inject it into the "User FS" partition at the appropriate offset, then boot from the swapped flash, erase the yamon partition and try to boot the normal nor layout. If you deem it acceptable, I'll send the 2 db1200 patches (core+sound) to be applied on top of it. Manuel From ralf@linux-mips.org Mon Nov 2 15:02:11 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 02 Nov 2009 15:02:14 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:43772 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-FAIL) by ftp.linux-mips.org with ESMTP id S1493898AbZKBOCL (ORCPT ); Mon, 2 Nov 2009 15:02:11 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id nA2E3Xtl024047; Mon, 2 Nov 2009 15:03:34 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id nA2E3WJL024045; Mon, 2 Nov 2009 15:03:32 +0100 Date: Mon, 2 Nov 2009 15:03:32 +0100 From: Ralf Baechle To: Wu Zhangjin Cc: Linux-MIPS , yanh@lemote.com, huhb@lemote.com, Zhang Le , zhangfx@lemote.com Subject: Re: [PATCH -queue 6/7] [loongson] remove reference from bonito64 Message-ID: <20091102140332.GE21563@linux-mips.org> References: <2aaf6778010c608858cf7af1bd46d226f89bf355.1255673756.git.wuzhangjin@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <2aaf6778010c608858cf7af1bd46d226f89bf355.1255673756.git.wuzhangjin@gmail.com> User-Agent: Mutt/1.5.19 (2009-01-05) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24613 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Fri, Oct 16, 2009 at 02:17:19PM +0800, Wu Zhangjin wrote: > There is a built-in northbridge in loongson2e/2f, which is bonito64 > compatiable, but it differs from bonito64. to avoid influencing the > original bonito64 support and make the loongson support more > maintainable, it's better to remove reference from bonito64. > > And this patch is a very important preparation for the coming loongson2f > family machines' support, all the coming patches depend on it. Thanks, queued for 2.6.33. Ralf From ralf@linux-mips.org Mon Nov 2 15:08:46 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 02 Nov 2009 15:08:49 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:44127 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-FAIL) by ftp.linux-mips.org with ESMTP id S1493906AbZKBOIq (ORCPT ); Mon, 2 Nov 2009 15:08:46 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id nA2EAAOT026986; Mon, 2 Nov 2009 15:10:10 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id nA2EA6OE026984; Mon, 2 Nov 2009 15:10:06 +0100 Date: Mon, 2 Nov 2009 15:10:06 +0100 From: Ralf Baechle To: Wu Zhangjin Cc: Linux-MIPS , yanh@lemote.com, huhb@lemote.com, Zhang Le , zhangfx@lemote.com Subject: Re: [PATCH -queue 7/7] [loongson] fuloong2e: update config file Message-ID: <20091102141006.GF21563@linux-mips.org> References: <3f07a3ecf42181a5642d734d070da4676cad51f3.1255673756.git.wuzhangjin@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <3f07a3ecf42181a5642d734d070da4676cad51f3.1255673756.git.wuzhangjin@gmail.com> User-Agent: Mutt/1.5.19 (2009-01-05) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24614 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Fri, Oct 16, 2009 at 02:17:20PM +0800, Wu Zhangjin wrote: > This patch enable Hibernation support by default, and choose SPARSEMEM > memory model to avoid Hibernation failure with FLATMEM and also save > memory wasted by FLATMEM. Thanks, queued for 2.6.33. Ralf From ralf@linux-mips.org Mon Nov 2 15:13:42 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 02 Nov 2009 15:13:48 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:54254 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-FAIL) by ftp.linux-mips.org with ESMTP id S1493911AbZKBONm (ORCPT ); Mon, 2 Nov 2009 15:13:42 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id nA2EF1L9027114; Mon, 2 Nov 2009 15:15:01 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id nA2EExnq027112; Mon, 2 Nov 2009 15:14:59 +0100 Date: Mon, 2 Nov 2009 15:14:59 +0100 From: Ralf Baechle To: Wu Zhangjin Cc: Linux-MIPS , yanh@lemote.com, huhb@lemote.com, Zhang Le , zhangfx@lemote.com Subject: Re: [PATCH -queue 2/7] [loongson] mem.c: Register reserved memory pages Message-ID: <20091102141459.GG21563@linux-mips.org> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.19 (2009-01-05) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24615 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Fri, Oct 16, 2009 at 02:17:15PM +0800, Wu Zhangjin wrote: > This patch registers the reserved pages for loongson family machines. Hmm... After our recent discussion on your hibernation issues I am wondering if this patch is actually still required or useful? Ralf From ralf@linux-mips.org Mon Nov 2 15:44:25 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 02 Nov 2009 15:44:28 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:52739 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-FAIL) by ftp.linux-mips.org with ESMTP id S1493924AbZKBOoW (ORCPT ); Mon, 2 Nov 2009 15:44:22 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id nA2EjgsF027830; Mon, 2 Nov 2009 15:45:43 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id nA2Ejf9V027828; Mon, 2 Nov 2009 15:45:41 +0100 Date: Mon, 2 Nov 2009 15:45:41 +0100 From: Ralf Baechle To: Manuel Lauss Cc: Kevin Hickey , Linux-MIPS , Manuel Lauss Subject: Re: [PATCH] MIPS: Alchemy: physmap-flash for all devboards Message-ID: <20091102144541.GA27698@linux-mips.org> References: <1255949617-22943-1-git-send-email-manuel.lauss@gmail.com> <1257167962.8374.0.camel@kh-d280-64> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: User-Agent: Mutt/1.5.19 (2009-01-05) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24616 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Mon, Nov 02, 2009 at 02:57:06PM +0100, Manuel Lauss wrote: > >> > > I will look this over today or tomorrow.  I'm interested in this patch > > but haven't had the time to review it.  Now I'll make the time :) > > Please do. To test swapboot, just dump yamon from the default partition, > and inject it into the "User FS" partition at the appropriate offset, then boot > from the swapped flash, erase the yamon partition and try to boot the > normal nor layout. > > If you deem it acceptable, I'll send the 2 db1200 patches (core+sound) > to be applied on top of it. The patch should also have been cc'ed to the linux-mtd list and maintainer. Ralf From wilbur512@gmail.com Mon Nov 2 16:13:01 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 02 Nov 2009 16:13:08 +0100 (CET) Received: from mail-gx0-f227.google.com ([209.85.217.227]:37291 "EHLO mail-gx0-f227.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1493930AbZKBPNB convert rfc822-to-8bit (ORCPT ); Mon, 2 Nov 2009 16:13:01 +0100 Received: by gxk27 with SMTP id 27so1326132gxk.7 for ; Mon, 02 Nov 2009 07:12:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:in-reply-to:references :date:message-id:subject:from:to:cc:content-type :content-transfer-encoding; bh=AAheWRTzcqsnmGvBBj3JgqTPdVoCdn58XvMSb1/CsoU=; b=L4qN6tr5/RdiXz5AjqMZR2kDs3ZoH4Wn71yudk/mwsYq4C+jURPsc1UkJTDq6s0RLn QiEIUNTffuY//qYRYGimrfRG9nhGCL5pMM9BgxzL4ZbBOTkx3JvrFS8G4H4GQQzJkzy9 eeDprSL0StLPW+DEb1Qwpn6b5Z9ffZkbQPvXQ= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type:content-transfer-encoding; b=fyxAviaxKi9IaKewatUjb/Ro4ZDydGO2/nZmanY3uGjMHd53l4sEuoLPsxBKz4bXd4 ClwC96M+Q5tUthg/wvs/qsJRGQQKz7vhD83uNil0TGNLbvb0eWNi0wno0lNkzGr4d0Aj SKQxDZmflyWIo0yIpjK76KXlDFwrUb6r2ddKw= MIME-Version: 1.0 Received: by 10.91.102.6 with SMTP id e6mr8775970agm.99.1257174772986; Mon, 02 Nov 2009 07:12:52 -0800 (PST) In-Reply-To: <20091101071407.GC4551@linux-mips.org> References: <20091101071407.GC4551@linux-mips.org> Date: Mon, 2 Nov 2009 23:12:52 +0800 Message-ID: Subject: Re: Problem in booting when calling calibrate_delay From: "wilbur.chan" To: Ralf Baechle Cc: Linux MIPS Mailing List Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24617 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wilbur512@gmail.com Precedence: bulk X-list: linux-mips 2009/11/1 Ralf Baechle : > On Thu, Oct 29, 2009 at 07:51:52AM +0800, wilbur.chan wrote: > When something like this happens it is in most cases caused by timer > interrupt not working. > >  Ralf > Today , I found that , the code never enter the do_timer function. As a matter of fact, I'm testing kexec on mips64 smp. In the end of the first kernel , I' ve used local_irq_disable and jumped directly into second kernel. However it hang at calibrate_delay. In a normal booting on mips64, I found that , do_timer was invoked after console_init. Here is my dump_stack of do_timer, in a successfully booting log: 0:Call Trace: 0:[ <834243cc>]0: dump_stack+0x8/0x34 0:[ <83451ee0>]0: do_timer+0x70/0xa8 0:[ <8342333c>]0: timer_interrupt+0x64/0x160 0:[ <834234b4>]0: ll_timer_interrupt+0x7c/0xd8 0:[ <8341d220>]0: ret_from_irq+0x0/0x4 0:[ <83443a64>]0: release_console_sem+0x1e0/0x328 0:[ <8377cf88>]0: serial8250_console_init+0x1c/0x2c 0:[ <8377ae58>]0: console_init+0x4c/0x6c 0:[ <83762dd8>]0: start_kernel+0x3e0/0x75c So, I thought that , it might be release_console_sem being failed in my second kernel of kexec when booting, but I don't know why From David.Daney@caviumnetworks.com Mon Nov 2 20:34:06 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 02 Nov 2009 20:34:13 +0100 (CET) Received: from mail3.caviumnetworks.com ([12.108.191.235]:2949 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1493937AbZKBTeG (ORCPT ); Mon, 2 Nov 2009 20:34:06 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,5,4,7535) id ; Mon, 02 Nov 2009 11:33:51 -0800 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Mon, 2 Nov 2009 11:33:52 -0800 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Mon, 2 Nov 2009 11:33:52 -0800 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.2/8.14.2) with ESMTP id nA2JXlaR029372; Mon, 2 Nov 2009 11:33:48 -0800 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.2/8.14.2/Submit) id nA2JXkcX029370; Mon, 2 Nov 2009 11:33:46 -0800 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: David Daney Subject: [PATCH] MIPS: Emulate 64-bit FPU on 64-bit CPUs. Date: Mon, 2 Nov 2009 11:33:46 -0800 Message-Id: <1257190426-29346-1-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.6.0.6 X-OriginalArrivalTime: 02 Nov 2009 19:33:52.0620 (UTC) FILETIME=[68C1EAC0:01CA5BF3] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24618 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Running a 64-bit kernel on a 64-bit CPU without an FPU would cause the emulator to run in 32-bit mode. The c0_Status.FR bit is wired to zero on systems without an FPU, so using that bit to decide how the emulator behaves doesn't allow for proper emulation on 64-bit FPU-less processors. Instead, we need to select the emulator mode based on the user-space ABI. Since the thread flag TIF_32BIT_REGS is used to set c0_Status.FR, we can just use it to decide if the emulator should be in 32-bit or 64-bit mode. Signed-off-by: David Daney --- arch/mips/math-emu/cp1emu.c | 41 +++++++++++++++++++++-------------------- 1 files changed, 21 insertions(+), 20 deletions(-) diff --git a/arch/mips/math-emu/cp1emu.c b/arch/mips/math-emu/cp1emu.c index 890f779..454b539 100644 --- a/arch/mips/math-emu/cp1emu.c +++ b/arch/mips/math-emu/cp1emu.c @@ -163,33 +163,34 @@ static int isBranchInstr(mips_instruction * i) /* * In the Linux kernel, we support selection of FPR format on the - * basis of the Status.FR bit. This does imply that, if a full 32 - * FPRs are desired, there needs to be a flip-flop that can be written - * to one at that bit position. In any case, O32 MIPS ABI uses - * only the even FPRs (Status.FR = 0). + * basis of the Status.FR bit. If an FPU is not present, the FR bit + * is hardwired to zero, which would imply a 32-bit FPU even for + * 64-bit CPUs. For 64-bit kernels with no FPU we use TIF_32BIT_REGS + * as a proxy for the FR bit so that a 64-bit FPU is emulated. In any + * case, for a 32-bit kernel which uses the O32 MIPS ABI, only the + * even FPRs are used (Status.FR = 0). */ - -#define CP0_STATUS_FR_SUPPORT - -#ifdef CP0_STATUS_FR_SUPPORT -#define FR_BIT ST0_FR +static inline int cop1_64bit(struct pt_regs *xcp) +{ + if (cpu_has_fpu) + return xcp->cp0_status & ST0_FR; +#ifdef CONFIG_64BIT + return !test_thread_flag(TIF_32BIT_REGS); #else -#define FR_BIT 0 + return 0; #endif +} + +#define SIFROMREG(si, x) ((si) = cop1_64bit(xcp) || !(x & 1) ? \ + (int)ctx->fpr[x] : (int)(ctx->fpr[x & ~1] >> 32)) -#define SIFROMREG(si, x) ((si) = \ - (xcp->cp0_status & FR_BIT) || !(x & 1) ? \ - (int)ctx->fpr[x] : \ - (int)(ctx->fpr[x & ~1] >> 32 )) -#define SITOREG(si, x) (ctx->fpr[x & ~((xcp->cp0_status & FR_BIT) == 0)] = \ - (xcp->cp0_status & FR_BIT) || !(x & 1) ? \ +#define SITOREG(si, x) (ctx->fpr[x & ~(cop1_64bit(xcp) == 0)] = \ + cop1_64bit(xcp) || !(x & 1) ? \ ctx->fpr[x & ~1] >> 32 << 32 | (u32)(si) : \ ctx->fpr[x & ~1] << 32 >> 32 | (u64)(si) << 32) -#define DIFROMREG(di, x) ((di) = \ - ctx->fpr[x & ~((xcp->cp0_status & FR_BIT) == 0)]) -#define DITOREG(di, x) (ctx->fpr[x & ~((xcp->cp0_status & FR_BIT) == 0)] \ - = (di)) +#define DIFROMREG(di, x) ((di) = ctx->fpr[x & ~(cop1_64bit(xcp) == 0)]) +#define DITOREG(di, x) (ctx->fpr[x & ~(cop1_64bit(xcp) == 0)] = (di)) #define SPFROMREG(sp, x) SIFROMREG((sp).bits, x) #define SPTOREG(sp, x) SITOREG((sp).bits, x) -- 1.6.0.6 From manuel.lauss@googlemail.com Mon Nov 2 21:21:59 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 02 Nov 2009 21:22:04 +0100 (CET) Received: from mail-ew0-f214.google.com ([209.85.219.214]:62106 "EHLO mail-ew0-f214.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1493948AbZKBUV6 (ORCPT ); Mon, 2 Nov 2009 21:21:58 +0100 Received: by ewy10 with SMTP id 10so6099690ewy.33 for ; Mon, 02 Nov 2009 12:21:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer; bh=jqE/i+EX1H2jqDvIc0yyOdSOu5opdoYLTMsPvJM/yQY=; b=D5am/0sB1/5qix9pDbheafuwQz/UbQahgYwgE2FIypqQSAiBl4Hx3ZznDDS1ikcYBZ VmCljGOswt1HOHSvVrK1Ayd3JQ+gAdo+84WYghxmOpaSPpqg3er4rK1Nas2m3EqaoaAR DLmHF2mlbWwU4M7hwJiJ20jsUU+1fIxsBTWNA= DomainKey-Signature: a=rsa-sha1; c=nofws; d=googlemail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer; b=hARQSJIG5dKzy40yyscUEUxLtKy2pVgYiYfY5U5oGQ+ob1vUe3HeZxhpc7Nci5J12y Pmc8ABmYzzz2mgsZzucSaBhJzoHbNipyOLHLTvn/3LXYe0sJMx0jwWrLojT5qjyvxeJC YfEfgx2S6kmcNpUpj83MyNZ6fK/OSE8fN8Vog= Received: by 10.216.91.13 with SMTP id g13mr376891wef.36.1257193313154; Mon, 02 Nov 2009 12:21:53 -0800 (PST) Received: from localhost.localdomain (p5496F7DD.dip.t-dialin.net [84.150.247.221]) by mx.google.com with ESMTPS id m5sm15375gve.11.2009.11.02.12.21.50 (version=TLSv1/SSLv3 cipher=RC4-MD5); Mon, 02 Nov 2009 12:21:52 -0800 (PST) From: Manuel Lauss To: Linux-MIPS Cc: Manuel Lauss Subject: [RFC PATCH 1/3] MIPS: Alchemy: extended DB1200 board support. Date: Mon, 2 Nov 2009 21:21:43 +0100 Message-Id: <1257193305-29996-1-git-send-email-manuel.lauss@gmail.com> X-Mailer: git-send-email 1.6.5.1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24619 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips Create own directory for DB1200 code and update it with new features. - SPI support: - tmp121 temperature sensor - SPI flash on DB1200 - I2C support - NE1619 sensor - AT24 eeprom - I2C/SPI can be selected at boot time via switch S6.8 - Carddetect IRQs for SD cards. - gen_nand based NAND support. - hexleds count sleep/wake transitions. Signed-off-by: Manuel Lauss --- Against mips-queue; also depends on patch "Alchemy: physmap-flash for all devboards" to build properly. arch/mips/alchemy/common/reset.c | 3 - arch/mips/alchemy/devboards/Makefile | 2 +- arch/mips/alchemy/devboards/db1200/Makefile | 1 + arch/mips/alchemy/devboards/db1200/platform.c | 510 ++++++++++++++++++++++ arch/mips/alchemy/devboards/db1200/setup.c | 137 ++++++ arch/mips/alchemy/devboards/pb1200/board_setup.c | 9 - arch/mips/alchemy/devboards/pb1200/platform.c | 34 -- arch/mips/include/asm/mach-db1x00/db1200.h | 33 +-- 8 files changed, 654 insertions(+), 75 deletions(-) create mode 100644 arch/mips/alchemy/devboards/db1200/Makefile create mode 100644 arch/mips/alchemy/devboards/db1200/platform.c create mode 100644 arch/mips/alchemy/devboards/db1200/setup.c diff --git a/arch/mips/alchemy/common/reset.c b/arch/mips/alchemy/common/reset.c index 4791011..266afd4 100644 --- a/arch/mips/alchemy/common/reset.c +++ b/arch/mips/alchemy/common/reset.c @@ -164,9 +164,6 @@ void au1000_halt(void) #ifdef CONFIG_MIPS_MIRAGE gpio_direction_output(210, 1); #endif -#ifdef CONFIG_MIPS_DB1200 - au_writew(au_readw(0xB980001C) | (1 << 14), 0xB980001C); -#endif #ifdef CONFIG_PM au_sleep(); diff --git a/arch/mips/alchemy/devboards/Makefile b/arch/mips/alchemy/devboards/Makefile index c74ef80..ecbd37f 100644 --- a/arch/mips/alchemy/devboards/Makefile +++ b/arch/mips/alchemy/devboards/Makefile @@ -11,7 +11,7 @@ obj-$(CONFIG_MIPS_PB1500) += pb1500/ obj-$(CONFIG_MIPS_PB1550) += pb1550/ obj-$(CONFIG_MIPS_DB1000) += db1x00/ obj-$(CONFIG_MIPS_DB1100) += db1x00/ -obj-$(CONFIG_MIPS_DB1200) += pb1200/ +obj-$(CONFIG_MIPS_DB1200) += db1200/ obj-$(CONFIG_MIPS_DB1500) += db1x00/ obj-$(CONFIG_MIPS_DB1550) += db1x00/ obj-$(CONFIG_MIPS_BOSPORUS) += db1x00/ diff --git a/arch/mips/alchemy/devboards/db1200/Makefile b/arch/mips/alchemy/devboards/db1200/Makefile new file mode 100644 index 0000000..17840a5 --- /dev/null +++ b/arch/mips/alchemy/devboards/db1200/Makefile @@ -0,0 +1 @@ +obj-y += setup.o platform.o diff --git a/arch/mips/alchemy/devboards/db1200/platform.c b/arch/mips/alchemy/devboards/db1200/platform.c new file mode 100644 index 0000000..5a6ef8d --- /dev/null +++ b/arch/mips/alchemy/devboards/db1200/platform.c @@ -0,0 +1,510 @@ +/* + * DBAu1200 board platform device registration + * + * Copyright (C) 2008-2009 Manuel Lauss + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include "../platform.h" + +static struct mtd_partition db1200_spiflash_parts[] = { + { + .name = "DB1200 SPI flash", + .offset = 0, + .size = MTDPART_SIZ_FULL, + }, +}; + +static struct flash_platform_data db1200_spiflash_data = { + .name = "s25fl001", + .parts = db1200_spiflash_parts, + .nr_parts = ARRAY_SIZE(db1200_spiflash_parts), + .type = "m25p10", +}; + +static struct spi_board_info db1200_spi_devs[] __initdata = { + { + /* TI TMP121AIDBVR temp sensor */ + .modalias = "tmp121", + .max_speed_hz = 2000000, + .bus_num = 0, + .chip_select = 0, + .mode = 0, + }, + { + /* Spansion S25FL001D0FMA SPI flash */ + .modalias = "m25p80", + .max_speed_hz = 50000000, + .bus_num = 0, + .chip_select = 1, + .mode = 0, + .platform_data = &db1200_spiflash_data, + }, +}; + +static struct i2c_board_info db1200_i2c_devs[] __initdata = { + { + /* AT24C04-10 I2C eeprom */ + I2C_BOARD_INFO("24c04", 0x52), + }, + { + /* Philips NE1619 temp/voltage sensor (adm1025 drv) */ + I2C_BOARD_INFO("ne1619", 0x2d), + }, + { + /* I2S audio codec WM8731 */ + I2C_BOARD_INFO("wm8731", 0x1b), + }, +}; + +/**********************************************************************/ + +static void au1200_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, + unsigned int ctrl) +{ + struct nand_chip *this = mtd->priv; + unsigned long ioaddr = (unsigned long)this->IO_ADDR_W; + + ioaddr &= 0xffffff00; + + if (ctrl & NAND_CLE) { + ioaddr += MEM_STNAND_CMD; + } else if (ctrl & NAND_ALE) { + ioaddr += MEM_STNAND_ADDR; + } else { + /* assume we want to r/w real data by default */ + ioaddr += MEM_STNAND_DATA; + } + this->IO_ADDR_R = this->IO_ADDR_W = (void __iomem *)ioaddr; + if (cmd != NAND_CMD_NONE) { + __raw_writeb(cmd, this->IO_ADDR_W); + wmb(); + } +} + +static int au1200_nand_device_ready(struct mtd_info *mtd) +{ + return __raw_readl((void __iomem *)MEM_STSTAT) & 1; +} + +static const char *db1200_part_probes[] = { "cmdlinepart", NULL }; + +static struct mtd_partition db1200_nand_parts[] = { + { + .name = "NAND FS 0", + .offset = 0, + .size = 8 * 1024 * 1024, + }, + { + .name = "NAND FS 1", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL + }, +}; + +struct platform_nand_data db1200_nand_platdata = { + .chip = { + .nr_chips = 1, + .chip_offset = 0, + .nr_partitions = ARRAY_SIZE(db1200_nand_parts), + .partitions = db1200_nand_parts, + .chip_delay = 20, + .part_probe_types = db1200_part_probes, + }, + .ctrl = { + .dev_ready = au1200_nand_device_ready, + .cmd_ctrl = au1200_nand_cmd_ctrl, + }, +}; + +static struct resource db1200_nand_res[] = { + [0] = { + .start = DB1200_NAND_PHYS_ADDR, + .end = DB1200_NAND_PHYS_ADDR + 0xff, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device db1200_nand_dev = { + .name = "gen_nand", + .num_resources = ARRAY_SIZE(db1200_nand_res), + .resource = db1200_nand_res, + .id = -1, + .dev = { + .platform_data = &db1200_nand_platdata, + } +}; + +/**********************************************************************/ + +static struct smc91x_platdata db1200_eth_data = { + .flags = SMC91X_NOWAIT | SMC91X_USE_16BIT, + .leda = RPC_LED_100_10, + .ledb = RPC_LED_TX_RX, +}; + +static struct resource db1200_eth_res[] = { + [0] = { + .start = DB1200_ETH_PHYS_ADDR, + .end = DB1200_ETH_PHYS_ADDR + 0xf, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = DB1200_ETH_INT, + .end = DB1200_ETH_INT, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device db1200_eth_dev = { + .dev = { + .platform_data = &db1200_eth_data, + }, + .name = "smc91x", + .id = -1, + .num_resources = ARRAY_SIZE(db1200_eth_res), + .resource = db1200_eth_res, +}; + +/**********************************************************************/ + +static struct resource db1200_ide_res[] = { + [0] = { + .start = DB1200_IDE_PHYS_ADDR, + .end = DB1200_IDE_PHYS_ADDR + DB1200_IDE_PHYS_LEN - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = DB1200_IDE_INT, + .end = DB1200_IDE_INT, + .flags = IORESOURCE_IRQ, + } +}; + +static u64 ide_dmamask = DMA_32BIT_MASK; + +static struct platform_device db1200_ide_dev = { + .name = "au1200-ide", + .id = 0, + .dev = { + .dma_mask = &ide_dmamask, + .coherent_dma_mask = DMA_32BIT_MASK, + }, + .num_resources = ARRAY_SIZE(db1200_ide_res), + .resource = db1200_ide_res, +}; + +/**********************************************************************/ + +static struct platform_device db1200_rtc_dev = { + .name = "rtc-au1xxx", + .id = -1, +}; + +/**********************************************************************/ + +/* SD carddetects: they're supposed to be edge-triggered, but ack + * doesn't seem to work (CPLD Rev 2). Instead, the screaming one + * is disabled and its counterpart enabled. The 500ms timeout is + * because the carddetect isn't debounced in hardware. + */ +static irqreturn_t db1200_mmc_cd(int irq, void *ptr) +{ + void(*mmc_cd)(struct mmc_host *, unsigned long); + + if (irq == DB1200_SD0_INSERT_INT) { + disable_irq_nosync(DB1200_SD0_INSERT_INT); + enable_irq(DB1200_SD0_EJECT_INT); + } else { + disable_irq_nosync(DB1200_SD0_EJECT_INT); + enable_irq(DB1200_SD0_INSERT_INT); + } + + /* link against CONFIG_MMC=m */ + mmc_cd = symbol_get(mmc_detect_change); + if (mmc_cd) { + mmc_cd(ptr, msecs_to_jiffies(500)); + symbol_put(mmc_detect_change); + } + + return IRQ_HANDLED; +} + +static int db1200_mmc_cd_setup(void *mmc_host, int en) +{ + int ret; + + if (en) { + ret = request_irq(DB1200_SD0_INSERT_INT, db1200_mmc_cd, + IRQF_DISABLED, "sd_insert", mmc_host); + if (ret) + goto out; + + ret = request_irq(DB1200_SD0_EJECT_INT, db1200_mmc_cd, + IRQF_DISABLED, "sd_eject", mmc_host); + if (ret) { + free_irq(DB1200_SD0_INSERT_INT, mmc_host); + goto out; + } + + if (bcsr_read(BCSR_SIGSTAT) & BCSR_INT_SD0INSERT) + enable_irq(DB1200_SD0_EJECT_INT); + else + enable_irq(DB1200_SD0_INSERT_INT); + + } else { + free_irq(DB1200_SD0_INSERT_INT, mmc_host); + free_irq(DB1200_SD0_EJECT_INT, mmc_host); + } + ret = 0; +out: + return ret; +} + +static void db1200_mmc_set_power(void *mmc_host, int state) +{ + if (state) { + bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_SD0PWR); + msleep(400); /* stabilization time */ + } else + bcsr_mod(BCSR_BOARD, BCSR_BOARD_SD0PWR, 0); +} + +static int db1200_mmc_card_readonly(void *mmc_host) +{ + return (bcsr_read(BCSR_STATUS) & BCSR_STATUS_SD0WP) ? 1 : 0; +} + +static int db1200_mmc_card_inserted(void *mmc_host) +{ + return (bcsr_read(BCSR_SIGSTAT) & BCSR_INT_SD0INSERT) ? 1 : 0; +} + +static void db1200_mmcled_set(struct led_classdev *led, + enum led_brightness brightness) +{ + if (brightness != LED_OFF) + bcsr_mod(BCSR_LEDS, BCSR_LEDS_LED0, 0); + else + bcsr_mod(BCSR_LEDS, 0, BCSR_LEDS_LED0); +} + +static struct led_classdev db1200_mmc_led = { + .brightness_set = db1200_mmcled_set, +}; + +/* needed by arch/mips/alchemy/common/platform.c */ +struct au1xmmc_platform_data au1xmmc_platdata[] = { + [0] = { + .cd_setup = db1200_mmc_cd_setup, + .set_power = db1200_mmc_set_power, + .card_inserted = db1200_mmc_card_inserted, + .card_readonly = db1200_mmc_card_readonly, + .led = &db1200_mmc_led, + }, +}; + +/**********************************************************************/ + +static struct resource au1200_psc0_res[] = { + [0] = { + .start = PSC0_PHYS_ADDR, + .end = PSC0_PHYS_ADDR + 0x000fffff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AU1200_PSC0_INT, + .end = AU1200_PSC0_INT, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = DSCR_CMD0_PSC0_TX, + .end = DSCR_CMD0_PSC0_TX, + .flags = IORESOURCE_DMA, + }, + [3] = { + .start = DSCR_CMD0_PSC0_RX, + .end = DSCR_CMD0_PSC0_RX, + .flags = IORESOURCE_DMA, + }, +}; + +static struct platform_device db1200_i2c_dev = { + .name = "au1xpsc_smbus", + .id = 0, /* bus number */ + .num_resources = ARRAY_SIZE(au1200_psc0_res), + .resource = au1200_psc0_res, +}; + +static void db1200_spi_cs_en(struct au1550_spi_info *spi, int cs, int pol) +{ + if (cs) + bcsr_mod(BCSR_RESETS, 0, BCSR_RESETS_SPISEL); + else + bcsr_mod(BCSR_RESETS, BCSR_RESETS_SPISEL, 0); +} + +static struct au1550_spi_info db1200_spi_platdata = { + .mainclk_hz = 50000000, /* PSC0 clock */ + .num_chipselect = 2, + .activate_cs = db1200_spi_cs_en, +}; + +static u64 spi_dmamask = DMA_32BIT_MASK; + +static struct platform_device db1200_spi_dev = { + .dev = { + .dma_mask = &spi_dmamask, + .coherent_dma_mask = DMA_32BIT_MASK, + .platform_data = &db1200_spi_platdata, + }, + .name = "au1550-spi", + .id = 0, /* bus number */ + .num_resources = ARRAY_SIZE(au1200_psc0_res), + .resource = au1200_psc0_res, +}; + +static struct platform_device *db1200_devs[] __initdata = { + NULL, /* PSC0, selected by S6.8 */ + &db1200_ide_dev, + &db1200_eth_dev, + &db1200_rtc_dev, + &db1200_nand_dev, +}; + +static int __init db1200_dev_init(void) +{ + unsigned long pfc; + unsigned short sw; + int swapped; + + i2c_register_board_info(0, db1200_i2c_devs, + ARRAY_SIZE(db1200_i2c_devs)); + spi_register_board_info(db1200_spi_devs, + ARRAY_SIZE(db1200_i2c_devs)); + + /* SWITCHES: S6.8 I2C/SPI selector (OFF=I2C ON=SPI) + */ + + /* NOTE: GPIO215 controls OTG VBUS supply. In SPI mode however + * this pin is claimed by PSC0 (unused though, but pinmux doesn't + * allow to free it without crippling the SPI interface). + * As a result, in SPI mode, OTG simply won't work (PSC0 uses + * it as an input pin which is pulled high on the boards). + */ + pfc = __raw_readl((void __iomem *)SYS_PINFUNC) & ~SYS_PINFUNC_P0A; + + /* switch off OTG VBUS supply */ + gpio_request(215, "otg-vbus"); + gpio_direction_output(215, 1); + + printk(KERN_INFO "DB1200 device configuration:\n"); + + sw = bcsr_read(BCSR_SWITCHES); + if (sw & BCSR_SWITCHES_DIP_8) { + db1200_devs[0] = &db1200_i2c_dev; + bcsr_mod(BCSR_RESETS, BCSR_RESETS_PSC0MUX, 0); + + pfc |= (2 << 17); /* GPIO2 block owns GPIO215 */ + + printk(KERN_INFO " S6.8 OFF: PSC0 mode I2C\n"); + printk(KERN_INFO " OTG port VBUS supply available!\n"); + } else { + db1200_devs[0] = &db1200_spi_dev; + bcsr_mod(BCSR_RESETS, 0, BCSR_RESETS_PSC0MUX); + + pfc |= (1 << 17); /* PSC0 owns GPIO215 */ + + printk(KERN_INFO " S6.8 ON : PSC0 mode SPI\n"); + printk(KERN_INFO " OTG port VBUS supply disabled\n"); + } + __raw_writel(pfc, (void __iomem *)SYS_PINFUNC); + wmb(); + + db1x_register_pcmcia_socket(PCMCIA_ATTR_PSEUDO_PHYS, + PCMCIA_ATTR_PSEUDO_PHYS + 0x00040000 - 1, + PCMCIA_MEM_PSEUDO_PHYS, + PCMCIA_MEM_PSEUDO_PHYS + 0x00040000 - 1, + PCMCIA_IO_PSEUDO_PHYS, + PCMCIA_IO_PSEUDO_PHYS + 0x00001000 - 1, + DB1200_PC0_INT, + DB1200_PC0_INSERT_INT, + /*DB1200_PC0_STSCHG_INT*/0, + DB1200_PC0_EJECT_INT, + 0); + + db1x_register_pcmcia_socket(PCMCIA_ATTR_PSEUDO_PHYS + 0x00400000, + PCMCIA_ATTR_PSEUDO_PHYS + 0x00440000 - 1, + PCMCIA_MEM_PSEUDO_PHYS + 0x00400000, + PCMCIA_MEM_PSEUDO_PHYS + 0x00440000 - 1, + PCMCIA_IO_PSEUDO_PHYS + 0x00400000, + PCMCIA_IO_PSEUDO_PHYS + 0x00401000 - 1, + DB1200_PC1_INT, + DB1200_PC1_INSERT_INT, + /*DB1200_PC1_STSCHG_INT*/0, + DB1200_PC1_EJECT_INT, + 1); + + swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1200_SWAPBOOT; + db1x_register_norflash(64 << 20, 2, swapped); + + return platform_add_devices(db1200_devs, ARRAY_SIZE(db1200_devs)); +} +device_initcall(db1200_dev_init); + +/* au1200fb calls these: STERBT EINEN TRAGISCHEN TOD!!! */ +int board_au1200fb_panel(void) +{ + return (bcsr_read(BCSR_SWITCHES) >> 8) & 0x0f; +} + +int board_au1200fb_panel_init(void) +{ + /* Apply power */ + bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD | + BCSR_BOARD_LCDBL); + return 0; +} + +int board_au1200fb_panel_shutdown(void) +{ + /* Remove power */ + bcsr_mod(BCSR_BOARD, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD | + BCSR_BOARD_LCDBL, 0); + return 0; +} diff --git a/arch/mips/alchemy/devboards/db1200/setup.c b/arch/mips/alchemy/devboards/db1200/setup.c new file mode 100644 index 0000000..a3458c0 --- /dev/null +++ b/arch/mips/alchemy/devboards/db1200/setup.c @@ -0,0 +1,137 @@ +/* + * Alchemy/AMD/RMI DB1200 board setup. + * + * Licensed under the terms outlined in the file COPYING in the root of + * this source archive. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +const char *get_system_type(void) +{ + return "Alchemy Db1200"; +} + +static void board_power_off(void) +{ + bcsr_write(BCSR_RESETS, 0); + bcsr_write(BCSR_SYSTEM, BCSR_SYSTEM_PWROFF | BCSR_SYSTEM_RESET); +} + +void board_reset(void) +{ + bcsr_write(BCSR_RESETS, 0); + bcsr_write(BCSR_SYSTEM, 0); +} + +void __init board_setup(void) +{ + unsigned long freq0, clksrc, div, pfc; + unsigned short whoami; + + bcsr_init(DB1200_BCSR_PHYS_ADDR, + DB1200_BCSR_PHYS_ADDR + DB1200_BCSR_HEXLED_OFS); + + whoami = bcsr_read(BCSR_WHOAMI); + printk(KERN_INFO "Alchemy/AMD/RMI DB1200 Board, CPLD Rev %d" + " Board-ID %d Daughtercard ID %d\n", + (whoami >> 4) & 0xf, (whoami >> 8) & 0xf, whoami & 0xf); + + /* SMBus/SPI on PSC0, Audio on PSC1 */ + pfc = __raw_readl((void __iomem *)SYS_PINFUNC); + pfc &= ~(SYS_PINFUNC_P0A | SYS_PINFUNC_P0B); + pfc &= ~(SYS_PINFUNC_P1A | SYS_PINFUNC_P1B | SYS_PINFUNC_FS3); + pfc |= SYS_PINFUNC_P1C; /* SPI is configured later */ + __raw_writel(pfc, (void __iomem *)SYS_PINFUNC); + wmb(); + + /* Clock configurations: PSC0: ~50MHz via Clkgen0, derived from + * CPU clock; all other clock generators off/unused. + */ + div = (get_au1x00_speed() + 25000000) / 50000000; + if (div & 1) + div++; + div = ((div >> 1) - 1) & 0xff; + + freq0 = div << SYS_FC_FRDIV0_BIT; + __raw_writel(freq0, (void __iomem *)SYS_FREQCTRL0); + wmb(); + freq0 |= SYS_FC_FE0; /* enable F0 */ + __raw_writel(freq0, (void __iomem *)SYS_FREQCTRL0); + wmb(); + + /* psc0_intclk comes 1:1 from F0 */ + clksrc = SYS_CS_MUX_FQ0 << SYS_CS_ME0_BIT; + __raw_writel(clksrc, (void __iomem *)SYS_CLKSRC); + wmb(); + + pm_power_off = board_power_off; + _machine_halt = board_power_off; + _machine_restart = (void(*)(char *))board_reset; +} + +/* use the hexleds to count the number of times the cpu has entered + * wait, the dots to indicate whether the CPU is currently idle or + * active (dots off = sleeping, dots on = working) for cases where + * the number doesn't change for a long(er) period of time. + */ +static void db1200_wait(void) +{ + __asm__(" .set push \n" + " .set mips3 \n" + " .set noreorder \n" + " cache 0x14, 0(%0) \n" + " cache 0x14, 32(%0) \n" + " cache 0x14, 64(%0) \n" + /* dots off: we're about to call wait */ + " lui $26, 0xb980 \n" + " ori $27, $0, 3 \n" + " sb $27, 0x18($26) \n" + " sync \n" + " nop \n" + " wait \n" + " nop \n" + " nop \n" + " nop \n" + " nop \n" + " nop \n" + /* dots on: there's work to do, increment cntr */ + " lui $26, 0xb980 \n" + " sb $0, 0x18($26) \n" + " lui $26, 0xb9c0 \n" + " lb $27, 0($26) \n" + " addiu $27, $27, 1 \n" + " sb $27, 0($26) \n" + " sync \n" + " .set pop \n" + : : "r" (db1200_wait)); +} + +static int __init db1200_arch_init(void) +{ + /* GPIO7 is low-level triggered CPLD cascade */ + set_irq_type(AU1200_GPIO7_INT, IRQF_TRIGGER_LOW); + bcsr_init_irq(DB1200_INT_BEGIN, DB1200_INT_END, AU1200_GPIO7_INT); + + /* do not autoenable these: CPLD has broken edge int handling, + * and the CD handler setup requires manual enabling to work + * around that. + */ + irq_to_desc(DB1200_SD0_INSERT_INT)->status |= IRQ_NOAUTOEN; + irq_to_desc(DB1200_SD0_EJECT_INT)->status |= IRQ_NOAUTOEN; + + if (cpu_wait) + cpu_wait = db1200_wait; + + return 0; +} +arch_initcall(db1200_arch_init); diff --git a/arch/mips/alchemy/devboards/pb1200/board_setup.c b/arch/mips/alchemy/devboards/pb1200/board_setup.c index e709b9e..906b6cd 100644 --- a/arch/mips/alchemy/devboards/pb1200/board_setup.c +++ b/arch/mips/alchemy/devboards/pb1200/board_setup.c @@ -60,16 +60,9 @@ void __init board_setup(void) { char *argptr; -#ifdef CONFIG_MIPS_PB1200 printk(KERN_INFO "AMD Alchemy Pb1200 Board\n"); bcsr_init(PB1200_BCSR_PHYS_ADDR, PB1200_BCSR_PHYS_ADDR + PB1200_BCSR_HEXLED_OFS); -#endif -#ifdef CONFIG_MIPS_DB1200 - printk(KERN_INFO "AMD Alchemy Db1200 Board\n"); - bcsr_init(DB1200_BCSR_PHYS_ADDR, - DB1200_BCSR_PHYS_ADDR + DB1200_BCSR_HEXLED_OFS); -#endif argptr = prom_getcmdline(); #ifdef CONFIG_SERIAL_8250_CONSOLE @@ -151,7 +144,6 @@ void __init board_setup(void) static int __init pb1200_init_irq(void) { -#ifdef CONFIG_MIPS_PB1200 /* We have a problem with CPLD rev 3. */ if (BCSR_WHOAMI_CPLD(bcsr_read(BCSR_WHOAMI)) <= 3) { printk(KERN_ERR "WARNING!!!\n"); @@ -171,7 +163,6 @@ static int __init pb1200_init_irq(void) printk(KERN_ERR "WARNING!!!\n"); panic("Game over. Your score is 0."); } -#endif set_irq_type(AU1200_GPIO7_INT, IRQF_TRIGGER_LOW); bcsr_init_irq(PB1200_INT_BEGIN, PB1200_INT_END, AU1200_GPIO7_INT); diff --git a/arch/mips/alchemy/devboards/pb1200/platform.c b/arch/mips/alchemy/devboards/pb1200/platform.c index 736d647..14e889f 100644 --- a/arch/mips/alchemy/devboards/pb1200/platform.c +++ b/arch/mips/alchemy/devboards/pb1200/platform.c @@ -68,7 +68,6 @@ static struct led_classdev pb1200mmc_led = { .brightness_set = pb1200_mmcled_set, }; -#ifndef CONFIG_MIPS_DB1200 static void pb1200mmc1_set_power(void *mmc_host, int state) { if (state) @@ -88,7 +87,6 @@ static int pb1200mmc1_card_inserted(void *mmc_host) { return (bcsr_read(BCSR_SIGSTAT) & BCSR_INT_SD1INSERT) ? 1 : 0; } -#endif const struct au1xmmc_platform_data au1xmmc_platdata[2] = { [0] = { @@ -98,7 +96,6 @@ const struct au1xmmc_platform_data au1xmmc_platdata[2] = { .cd_setup = NULL, /* use poll-timer in driver */ .led = &pb1200mmc_led, }, -#ifndef CONFIG_MIPS_DB1200 [1] = { .set_power = pb1200mmc1_set_power, .card_inserted = pb1200mmc1_card_inserted, @@ -106,7 +103,6 @@ const struct au1xmmc_platform_data au1xmmc_platdata[2] = { .cd_setup = NULL, /* use poll-timer in driver */ .led = &pb1200mmc_led, }, -#endif }; static struct resource ide_resources[] = { @@ -174,7 +170,6 @@ static int __init board_register_devices(void) { int swapped; -#ifdef CONFIG_MIPS_PB1200 db1x_register_pcmcia_socket(PCMCIA_ATTR_PSEUDO_PHYS, PCMCIA_ATTR_PSEUDO_PHYS + 0x00040000 - 1, PCMCIA_MEM_PSEUDO_PHYS, @@ -198,38 +193,9 @@ static int __init board_register_devices(void) /*PB1200_PC1_STSCHG_INT*/0, PB1200_PC1_EJECT_INT, 1); -#else - db1x_register_pcmcia_socket(PCMCIA_ATTR_PSEUDO_PHYS, - PCMCIA_ATTR_PSEUDO_PHYS + 0x00040000 - 1, - PCMCIA_MEM_PSEUDO_PHYS, - PCMCIA_MEM_PSEUDO_PHYS + 0x00040000 - 1, - PCMCIA_IO_PSEUDO_PHYS, - PCMCIA_IO_PSEUDO_PHYS + 0x00001000 - 1, - DB1200_PC0_INT, - DB1200_PC0_INSERT_INT, - /*DB1200_PC0_STSCHG_INT*/0, - DB1200_PC0_EJECT_INT, - 0); - - db1x_register_pcmcia_socket(PCMCIA_ATTR_PSEUDO_PHYS + 0x00400000, - PCMCIA_ATTR_PSEUDO_PHYS + 0x00440000 - 1, - PCMCIA_MEM_PSEUDO_PHYS + 0x00400000, - PCMCIA_MEM_PSEUDO_PHYS + 0x00440000 - 1, - PCMCIA_IO_PSEUDO_PHYS + 0x00400000, - PCMCIA_IO_PSEUDO_PHYS + 0x00401000 - 1, - DB1200_PC1_INT, - DB1200_PC1_INSERT_INT, - /*DB1200_PC1_STSCHG_INT*/0, - DB1200_PC1_EJECT_INT, - 1); -#endif swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1200_SWAPBOOT; -#ifdef CONFIG_MIPS_PB1200 db1x_register_norflash(128 * 1024 * 1024, 2, swapped); -#else - db1x_register_norflash(64 * 1024 * 1024, 2, swapped); -#endif return platform_add_devices(board_platform_devices, ARRAY_SIZE(board_platform_devices)); diff --git a/arch/mips/include/asm/mach-db1x00/db1200.h b/arch/mips/include/asm/mach-db1x00/db1200.h index 52b1d84..3404248 100644 --- a/arch/mips/include/asm/mach-db1x00/db1200.h +++ b/arch/mips/include/asm/mach-db1x00/db1200.h @@ -28,24 +28,6 @@ #include #include -#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX -#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX -#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC1_TX -#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC1_RX - -/* - * SPI and SMB are muxed on the DBAu1200 board. - * Refer to board documentation. - */ -#define SPI_PSC_BASE PSC0_BASE_ADDR -#define SMBUS_PSC_BASE PSC0_BASE_ADDR -/* - * AC'97 and I2S are muxed on the DBAu1200 board. - * Refer to board documentation. - */ -#define AC97_PSC_BASE PSC1_BASE_ADDR -#define I2S_PSC_BASE PSC1_BASE_ADDR - /* Bit positions for the different interrupt sources */ #define BCSR_INT_IDE 0x0001 #define BCSR_INT_ETH 0x0002 @@ -62,17 +44,15 @@ #define BCSR_INT_SD0INSERT 0x1000 #define BCSR_INT_SD0EJECT 0x2000 -#define SMC91C111_PHYS_ADDR 0x19000300 -#define SMC91C111_INT DB1200_ETH_INT - #define IDE_PHYS_ADDR 0x18800000 #define IDE_REG_SHIFT 5 -#define IDE_PHYS_LEN (16 << IDE_REG_SHIFT) -#define IDE_INT DB1200_IDE_INT #define IDE_DDMA_REQ DSCR_CMD0_DMA_REQ1 #define IDE_RQSIZE 128 -#define NAND_PHYS_ADDR 0x20000000 +#define DB1200_IDE_PHYS_ADDR IDE_PHYS_ADDR +#define DB1200_IDE_PHYS_LEN (16 << IDE_REG_SHIFT) +#define DB1200_ETH_PHYS_ADDR 0x19000300 +#define DB1200_NAND_PHYS_ADDR 0x20000000 /* * External Interrupts for DBAu1200 as of 8/6/2004. @@ -82,7 +62,7 @@ * Example: IDE bis pos is = 64 - 64 * ETH bit pos is = 65 - 64 */ -enum external_pb1200_ints { +enum external_db1200_ints { DB1200_INT_BEGIN = AU1000_MAX_INTR + 1, DB1200_IDE_INT = DB1200_INT_BEGIN, @@ -103,7 +83,4 @@ enum external_pb1200_ints { DB1200_INT_END = DB1200_INT_BEGIN + 15, }; -/* NAND chip select */ -#define NAND_CS 1 - #endif /* __ASM_DB1200_H */ -- 1.6.5.1 From manuel.lauss@googlemail.com Mon Nov 2 21:22:22 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 02 Nov 2009 21:22:29 +0100 (CET) Received: from ey-out-1920.google.com ([74.125.78.147]:32116 "EHLO ey-out-1920.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1493951AbZKBUV6 (ORCPT ); Mon, 2 Nov 2009 21:21:58 +0100 Received: by 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(p5496F7DD.dip.t-dialin.net [84.150.247.221]) by mx.google.com with ESMTPS id m5sm15375gve.11.2009.11.02.12.21.55 (version=TLSv1/SSLv3 cipher=RC4-MD5); Mon, 02 Nov 2009 12:21:56 -0800 (PST) From: Manuel Lauss To: Linux-MIPS Cc: Manuel Lauss Subject: [PATCH 3/3] MIPS: Alchemy: db1200 defconfig update Date: Mon, 2 Nov 2009 21:21:45 +0100 Message-Id: <1257193305-29996-3-git-send-email-manuel.lauss@gmail.com> X-Mailer: git-send-email 1.6.5.1 In-Reply-To: <1257193305-29996-2-git-send-email-manuel.lauss@gmail.com> References: <1257193305-29996-1-git-send-email-manuel.lauss@gmail.com> <1257193305-29996-2-git-send-email-manuel.lauss@gmail.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24620 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips Signed-off-by: Manuel Lauss --- arch/mips/configs/db1200_defconfig | 1481 +++++++++++++++++++++--------------- 1 files changed, 850 insertions(+), 631 deletions(-) diff --git a/arch/mips/configs/db1200_defconfig b/arch/mips/configs/db1200_defconfig index d73f1de..a7ca995 100644 --- a/arch/mips/configs/db1200_defconfig +++ b/arch/mips/configs/db1200_defconfig @@ -1,79 +1,101 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.20 -# Tue Feb 20 21:47:25 2007 +# Linux kernel version: 2.6.32-rc5 +# Mon Nov 2 21:09:28 2009 # CONFIG_MIPS=y # # Machine selection # -CONFIG_ZONE_DMA=y CONFIG_MACH_ALCHEMY=y -# CONFIG_MIPS_MTX1 is not set -# CONFIG_MIPS_BOSPORUS is not set -# CONFIG_MIPS_PB1000 is not set -# CONFIG_MIPS_PB1100 is not set -# CONFIG_MIPS_PB1500 is not set -# CONFIG_MIPS_PB1550 is not set -# CONFIG_MIPS_PB1200 is not set -# CONFIG_MIPS_DB1000 is not set -# CONFIG_MIPS_DB1100 is not set -# CONFIG_MIPS_DB1500 is not set -# CONFIG_MIPS_DB1550 is not set -CONFIG_MIPS_DB1200=y -# CONFIG_MIPS_MIRAGE is not set +# CONFIG_AR7 is not set # CONFIG_BASLER_EXCITE is not set +# CONFIG_BCM47XX is not set +# CONFIG_BCM63XX is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set +# CONFIG_LASAT is not set +# CONFIG_MACH_LOONGSON is not set # CONFIG_MIPS_MALTA is not set -# CONFIG_WR_PPMC is not set # CONFIG_MIPS_SIM is not set -# CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_MIPS_XXS1500 is not set +# CONFIG_NEC_MARKEINS is not set +# CONFIG_MACH_VR41XX is not set +# CONFIG_NXP_STB220 is not set +# CONFIG_NXP_STB225 is not set # CONFIG_PNX8550_JBS is not set # CONFIG_PNX8550_STB810 is not set -# CONFIG_MACH_VR41XX is not set +# CONFIG_PMC_MSP is not set # CONFIG_PMC_YOSEMITE is not set -# CONFIG_MARKEINS is not set # CONFIG_SGI_IP22 is not set # CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP28 is not set # CONFIG_SGI_IP32 is not set -# CONFIG_SIBYTE_BIGSUR is not set -# CONFIG_SIBYTE_SWARM is not set -# CONFIG_SIBYTE_SENTOSA is not set -# CONFIG_SIBYTE_RHONE is not set -# CONFIG_SIBYTE_CARMEL is not set -# CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CARMEL is not set # CONFIG_SIBYTE_CRHONE is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_BIGSUR is not set # CONFIG_SNI_RM is not set -# CONFIG_TOSHIBA_JMR3927 is not set -# CONFIG_TOSHIBA_RBTX4927 is not set -# CONFIG_TOSHIBA_RBTX4938 is not set +# CONFIG_MACH_TX39XX is not set +# CONFIG_MACH_TX49XX is not set +# CONFIG_MIKROTIK_RB532 is not set +# CONFIG_WR_PPMC is not set +# CONFIG_CAVIUM_OCTEON_SIMULATOR is not set +# CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD is not set +CONFIG_ALCHEMY_GPIO_AU1000=y +# CONFIG_ALCHEMY_GPIO_INDIRECT is not set +# CONFIG_MIPS_MTX1 is not set +# CONFIG_MIPS_BOSPORUS is not set +# CONFIG_MIPS_DB1000 is not set +# CONFIG_MIPS_DB1100 is not set +CONFIG_MIPS_DB1200=y +# CONFIG_MIPS_DB1500 is not set +# CONFIG_MIPS_DB1550 is not set +# CONFIG_MIPS_MIRAGE is not set +# CONFIG_MIPS_PB1000 is not set +# CONFIG_MIPS_PB1100 is not set +# CONFIG_MIPS_PB1200 is not set +# CONFIG_MIPS_PB1500 is not set +# CONFIG_MIPS_PB1550 is not set +# CONFIG_MIPS_XXS1500 is not set +CONFIG_SOC_AU1200=y +CONFIG_SOC_AU1X00=y CONFIG_RWSEM_GENERIC_SPINLOCK=y # CONFIG_ARCH_HAS_ILOG2_U32 is not set # CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_ARCH_SUPPORTS_OPROFILE=y CONFIG_GENERIC_FIND_NEXT_BIT=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_CLOCKEVENTS=y CONFIG_GENERIC_TIME=y -CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y -# CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ is not set +CONFIG_GENERIC_CMOS_UPDATE=y +CONFIG_SCHED_OMIT_FRAME_POINTER=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +CONFIG_CEVT_R4K_LIB=y +CONFIG_CSRC_R4K_LIB=y CONFIG_DMA_COHERENT=y +CONFIG_EARLY_PRINTK=y +CONFIG_SYS_HAS_EARLY_PRINTK=y CONFIG_MIPS_DISABLE_OBSOLETE_IDE=y +# CONFIG_NO_IOPORT is not set +CONFIG_GENERIC_GPIO=y # CONFIG_CPU_BIG_ENDIAN is not set CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_SYS_SUPPORTS_APM_EMULATION=y CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y -CONFIG_SOC_AU1200=y -CONFIG_SOC_AU1X00=y +CONFIG_IRQ_CPU=y CONFIG_MIPS_L1_CACHE_SHIFT=5 # # CPU selection # +# CONFIG_CPU_LOONGSON2E is not set CONFIG_CPU_MIPS32_R1=y # CONFIG_CPU_MIPS32_R2 is not set # CONFIG_CPU_MIPS64_R1 is not set @@ -86,6 +108,7 @@ CONFIG_CPU_MIPS32_R1=y # CONFIG_CPU_TX49XX is not set # CONFIG_CPU_R5000 is not set # CONFIG_CPU_R5432 is not set +# CONFIG_CPU_R5500 is not set # CONFIG_CPU_R6000 is not set # CONFIG_CPU_NEVADA is not set # CONFIG_CPU_R8000 is not set @@ -93,11 +116,13 @@ CONFIG_CPU_MIPS32_R1=y # CONFIG_CPU_RM7000 is not set # CONFIG_CPU_RM9000 is not set # CONFIG_CPU_SB1 is not set +# CONFIG_CPU_CAVIUM_OCTEON is not set CONFIG_SYS_HAS_CPU_MIPS32_R1=y CONFIG_CPU_MIPS32=y CONFIG_CPU_MIPSR1=y CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_HARDWARE_WATCHPOINTS=y # # Kernel type @@ -107,180 +132,204 @@ CONFIG_32BIT=y CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_8KB is not set # CONFIG_PAGE_SIZE_16KB is not set +# CONFIG_PAGE_SIZE_32KB is not set # CONFIG_PAGE_SIZE_64KB is not set CONFIG_CPU_HAS_PREFETCH=y CONFIG_MIPS_MT_DISABLED=y # CONFIG_MIPS_MT_SMP is not set # CONFIG_MIPS_MT_SMTC is not set -# CONFIG_MIPS_VPE_LOADER is not set CONFIG_64BIT_PHYS_ADDR=y CONFIG_CPU_HAS_SYNC=y CONFIG_GENERIC_HARDIRQS=y CONFIG_GENERIC_IRQ_PROBE=y CONFIG_CPU_SUPPORTS_HIGHMEM=y CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_ARCH_POPULATES_NODE_MAP=y CONFIG_SELECT_MEMORY_MODEL=y CONFIG_FLATMEM_MANUAL=y # CONFIG_DISCONTIGMEM_MANUAL is not set # CONFIG_SPARSEMEM_MANUAL is not set CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_SPARSEMEM_STATIC is not set +CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 -# CONFIG_RESOURCES_64BIT is not set -CONFIG_ZONE_DMA_FLAG=1 +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=0 +CONFIG_VIRT_TO_BUS=y +CONFIG_HAVE_MLOCK=y +CONFIG_HAVE_MLOCKED_PAGE_BIT=y +CONFIG_KSM=y +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y # CONFIG_HZ_48 is not set -# CONFIG_HZ_100 is not set +CONFIG_HZ_100=y # CONFIG_HZ_128 is not set # CONFIG_HZ_250 is not set # CONFIG_HZ_256 is not set -CONFIG_HZ_1000=y +# CONFIG_HZ_1000 is not set # CONFIG_HZ_1024 is not set CONFIG_SYS_SUPPORTS_ARBIT_HZ=y -CONFIG_HZ=1000 +CONFIG_HZ=100 CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set # CONFIG_KEXEC is not set +# CONFIG_SECCOMP is not set CONFIG_LOCKDEP_SUPPORT=y CONFIG_STACKTRACE_SUPPORT=y CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_CONSTRUCTORS=y # -# Code maturity level options +# General setup # CONFIG_EXPERIMENTAL=y CONFIG_BROKEN_ON_SMP=y CONFIG_INIT_ENV_ARG_LIMIT=32 - -# -# General setup -# -CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION="-db1200" CONFIG_LOCALVERSION_AUTO=y CONFIG_SWAP=y CONFIG_SYSVIPC=y -# CONFIG_IPC_NS is not set CONFIG_SYSVIPC_SYSCTL=y -# CONFIG_POSIX_MQUEUE is not set +CONFIG_POSIX_MQUEUE=y +CONFIG_POSIX_MQUEUE_SYSCTL=y # CONFIG_BSD_PROCESS_ACCT is not set # CONFIG_TASKSTATS is not set -# CONFIG_UTS_NS is not set # CONFIG_AUDIT is not set -CONFIG_IKCONFIG=y -CONFIG_IKCONFIG_PROC=y -CONFIG_SYSFS_DEPRECATED=y + +# +# RCU Subsystem +# +CONFIG_TREE_RCU=y +# CONFIG_TREE_PREEMPT_RCU is not set +# CONFIG_RCU_TRACE is not set +CONFIG_RCU_FANOUT=32 +CONFIG_RCU_FANOUT_EXACT=y +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=18 +# CONFIG_GROUP_SCHED is not set +# CONFIG_CGROUPS is not set +# CONFIG_SYSFS_DEPRECATED_V2 is not set # CONFIG_RELAY is not set -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +# CONFIG_NAMESPACES is not set +# CONFIG_BLK_DEV_INITRD is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y CONFIG_EMBEDDED=y -CONFIG_SYSCTL_SYSCALL=y -CONFIG_KALLSYMS=y -# CONFIG_KALLSYMS_EXTRA_PASS is not set +# CONFIG_SYSCTL_SYSCALL is not set +# CONFIG_KALLSYMS is not set CONFIG_HOTPLUG=y CONFIG_PRINTK=y CONFIG_BUG=y CONFIG_ELF_CORE=y +# CONFIG_PCSPKR_PLATFORM is not set CONFIG_BASE_FULL=y CONFIG_FUTEX=y CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y CONFIG_SHMEM=y -CONFIG_SLAB=y -CONFIG_VM_EVENT_COUNTERS=y -CONFIG_RT_MUTEXES=y -# CONFIG_TINY_SHMEM is not set -CONFIG_BASE_SMALL=0 +CONFIG_AIO=y + +# +# Kernel Performance Events And Counters +# +# CONFIG_VM_EVENT_COUNTERS is not set +# CONFIG_SLUB_DEBUG is not set +# CONFIG_COMPAT_BRK is not set +# CONFIG_SLAB is not set +CONFIG_SLUB=y # CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +CONFIG_HAVE_OPROFILE=y # -# Loadable module support +# GCOV-based kernel profiling # +# CONFIG_SLOW_WORK is not set +# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set CONFIG_MODULE_UNLOAD=y # CONFIG_MODULE_FORCE_UNLOAD is not set -CONFIG_MODVERSIONS=y -CONFIG_MODULE_SRCVERSION_ALL=y -CONFIG_KMOD=y - -# -# Block layer -# +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set CONFIG_BLOCK=y -# CONFIG_LBD is not set -# CONFIG_BLK_DEV_IO_TRACE is not set -# CONFIG_LSF is not set +# CONFIG_LBDAF is not set +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set # # IO Schedulers # CONFIG_IOSCHED_NOOP=y -CONFIG_IOSCHED_AS=y -CONFIG_IOSCHED_DEADLINE=y -CONFIG_IOSCHED_CFQ=y -CONFIG_DEFAULT_AS=y +# CONFIG_IOSCHED_AS is not set +# CONFIG_IOSCHED_DEADLINE is not set +# CONFIG_IOSCHED_CFQ is not set +# CONFIG_DEFAULT_AS is not set # CONFIG_DEFAULT_DEADLINE is not set # CONFIG_DEFAULT_CFQ is not set -# CONFIG_DEFAULT_NOOP is not set -CONFIG_DEFAULT_IOSCHED="anticipatory" +CONFIG_DEFAULT_NOOP=y +CONFIG_DEFAULT_IOSCHED="noop" +# CONFIG_FREEZER is not set # # Bus options (PCI, PCMCIA, EISA, ISA, TC) # +# CONFIG_ARCH_SUPPORTS_MSI is not set CONFIG_MMU=y - -# -# PCCARD (PCMCIA/CardBus) support -# -CONFIG_PCCARD=m +CONFIG_PCCARD=y # CONFIG_PCMCIA_DEBUG is not set -CONFIG_PCMCIA=m +CONFIG_PCMCIA=y CONFIG_PCMCIA_LOAD_CIS=y -CONFIG_PCMCIA_IOCTL=y +# CONFIG_PCMCIA_IOCTL is not set # # PC-card bridges # -CONFIG_PCMCIA_AU1X00=m - -# -# PCI Hotplug Support -# +# CONFIG_PCMCIA_AU1X00 is not set +CONFIG_PCMCIA_ALCHEMY_DEVBOARD=y # # Executable file formats # CONFIG_BINFMT_ELF=y -# CONFIG_BINFMT_MISC is not set +CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y +# CONFIG_HAVE_AOUT is not set +CONFIG_BINFMT_MISC=y CONFIG_TRAD_SIGNALS=y # # Power management options # +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y # CONFIG_PM is not set - -# -# Networking -# CONFIG_NET=y # # Networking options # -# CONFIG_NETDEBUG is not set CONFIG_PACKET=y -# CONFIG_PACKET_MMAP is not set +CONFIG_PACKET_MMAP=y CONFIG_UNIX=y -CONFIG_XFRM=y -CONFIG_XFRM_USER=m -# CONFIG_XFRM_SUB_POLICY is not set -CONFIG_XFRM_MIGRATE=y -CONFIG_NET_KEY=y -CONFIG_NET_KEY_MIGRATE=y +# CONFIG_NET_KEY is not set CONFIG_INET=y CONFIG_IP_MULTICAST=y # CONFIG_IP_ADVANCED_ROUTER is not set CONFIG_IP_FIB_HASH=y -# CONFIG_IP_PNP is not set +CONFIG_IP_PNP=y +# CONFIG_IP_PNP_DHCP is not set +# CONFIG_IP_PNP_BOOTP is not set +# CONFIG_IP_PNP_RARP is not set # CONFIG_NET_IPIP is not set # CONFIG_NET_IPGRE is not set # CONFIG_IP_MROUTE is not set @@ -291,107 +340,25 @@ CONFIG_IP_FIB_HASH=y # CONFIG_INET_IPCOMP is not set # CONFIG_INET_XFRM_TUNNEL is not set # CONFIG_INET_TUNNEL is not set -CONFIG_INET_XFRM_MODE_TRANSPORT=m -CONFIG_INET_XFRM_MODE_TUNNEL=m -CONFIG_INET_XFRM_MODE_BEET=m -CONFIG_INET_DIAG=y -CONFIG_INET_TCP_DIAG=y +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_LRO is not set +# CONFIG_INET_DIAG is not set # CONFIG_TCP_CONG_ADVANCED is not set CONFIG_TCP_CONG_CUBIC=y CONFIG_DEFAULT_TCP_CONG="cubic" -CONFIG_TCP_MD5SIG=y - -# -# IP: Virtual Server Configuration -# -# CONFIG_IP_VS is not set +# CONFIG_TCP_MD5SIG is not set # CONFIG_IPV6 is not set -# CONFIG_INET6_XFRM_TUNNEL is not set -# CONFIG_INET6_TUNNEL is not set -CONFIG_NETWORK_SECMARK=y -CONFIG_NETFILTER=y -# CONFIG_NETFILTER_DEBUG is not set - -# -# Core Netfilter Configuration -# -# CONFIG_NETFILTER_NETLINK is not set -CONFIG_NF_CONNTRACK_ENABLED=m -CONFIG_NF_CONNTRACK_SUPPORT=y -# CONFIG_IP_NF_CONNTRACK_SUPPORT is not set -CONFIG_NF_CONNTRACK=m -CONFIG_NF_CT_ACCT=y -CONFIG_NF_CONNTRACK_MARK=y -CONFIG_NF_CONNTRACK_SECMARK=y -CONFIG_NF_CONNTRACK_EVENTS=y -CONFIG_NF_CT_PROTO_GRE=m -CONFIG_NF_CT_PROTO_SCTP=m -CONFIG_NF_CONNTRACK_AMANDA=m -CONFIG_NF_CONNTRACK_FTP=m -CONFIG_NF_CONNTRACK_H323=m -CONFIG_NF_CONNTRACK_IRC=m -# CONFIG_NF_CONNTRACK_NETBIOS_NS is not set -CONFIG_NF_CONNTRACK_PPTP=m -CONFIG_NF_CONNTRACK_SANE=m -CONFIG_NF_CONNTRACK_SIP=m -CONFIG_NF_CONNTRACK_TFTP=m -CONFIG_NETFILTER_XTABLES=m -CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m -CONFIG_NETFILTER_XT_TARGET_MARK=m -CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m -CONFIG_NETFILTER_XT_TARGET_NFLOG=m -CONFIG_NETFILTER_XT_TARGET_SECMARK=m -CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=m -CONFIG_NETFILTER_XT_TARGET_TCPMSS=m -CONFIG_NETFILTER_XT_MATCH_COMMENT=m -CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m -CONFIG_NETFILTER_XT_MATCH_CONNMARK=m -CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m -CONFIG_NETFILTER_XT_MATCH_DCCP=m -CONFIG_NETFILTER_XT_MATCH_DSCP=m -CONFIG_NETFILTER_XT_MATCH_ESP=m -CONFIG_NETFILTER_XT_MATCH_HELPER=m -CONFIG_NETFILTER_XT_MATCH_LENGTH=m -CONFIG_NETFILTER_XT_MATCH_LIMIT=m -CONFIG_NETFILTER_XT_MATCH_MAC=m -CONFIG_NETFILTER_XT_MATCH_MARK=m -CONFIG_NETFILTER_XT_MATCH_POLICY=m -CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m -CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m -CONFIG_NETFILTER_XT_MATCH_QUOTA=m -CONFIG_NETFILTER_XT_MATCH_REALM=m -CONFIG_NETFILTER_XT_MATCH_SCTP=m -CONFIG_NETFILTER_XT_MATCH_STATE=m -CONFIG_NETFILTER_XT_MATCH_STATISTIC=m -CONFIG_NETFILTER_XT_MATCH_STRING=m -CONFIG_NETFILTER_XT_MATCH_TCPMSS=m -CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m - -# -# IP: Netfilter Configuration -# -CONFIG_NF_CONNTRACK_IPV4=m -CONFIG_NF_CONNTRACK_PROC_COMPAT=y -# CONFIG_IP_NF_QUEUE is not set -# CONFIG_IP_NF_IPTABLES is not set -# CONFIG_IP_NF_ARPTABLES is not set - -# -# DCCP Configuration (EXPERIMENTAL) -# +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETFILTER is not set # CONFIG_IP_DCCP is not set - -# -# SCTP Configuration (EXPERIMENTAL) -# # CONFIG_IP_SCTP is not set - -# -# TIPC Configuration (EXPERIMENTAL) -# +# CONFIG_RDS is not set # CONFIG_TIPC is not set # CONFIG_ATM is not set # CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set # CONFIG_VLAN_8021Q is not set # CONFIG_DECNET is not set # CONFIG_LLC2 is not set @@ -401,21 +368,26 @@ CONFIG_NF_CONNTRACK_PROC_COMPAT=y # CONFIG_LAPB is not set # CONFIG_ECONET is not set # CONFIG_WAN_ROUTER is not set - -# -# QoS and/or fair queueing -# +# CONFIG_PHONET is not set +# CONFIG_IEEE802154 is not set # CONFIG_NET_SCHED is not set -CONFIG_NET_CLS_ROUTE=y +# CONFIG_DCB is not set # # Network testing # # CONFIG_NET_PKTGEN is not set # CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set # CONFIG_IRDA is not set # CONFIG_BT is not set -# CONFIG_IEEE80211 is not set +# CONFIG_AF_RXRPC is not set +# CONFIG_WIRELESS is not set +# CONFIG_MAC80211_RC_DEFAULT_PID is not set +# CONFIG_MAC80211_RC_DEFAULT_MINSTREL is not set +# CONFIG_WIMAX is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set # # Device Drivers @@ -424,25 +396,23 @@ CONFIG_NET_CLS_ROUTE=y # # Generic Driver Options # +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +# CONFIG_DEVTMPFS is not set CONFIG_STANDALONE=y CONFIG_PREVENT_FIRMWARE_BUILD=y CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" # CONFIG_SYS_HYPERVISOR is not set - -# -# Connector - unified userspace <-> kernelspace linker -# # CONFIG_CONNECTOR is not set - -# -# Memory Technology Devices (MTD) -# CONFIG_MTD=y # CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_TESTS is not set # CONFIG_MTD_CONCAT is not set CONFIG_MTD_PARTITIONS=y # CONFIG_MTD_REDBOOT_PARTS is not set -# CONFIG_MTD_CMDLINE_PARTS is not set +CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_AR7_PARTS is not set # # User Modules And Translation Layers @@ -455,6 +425,7 @@ CONFIG_MTD_BLOCK=y # CONFIG_INFTL is not set # CONFIG_RFD_FTL is not set # CONFIG_SSFDC is not set +# CONFIG_MTD_OOPS is not set # # RAM/ROM/Flash chip drivers @@ -463,6 +434,9 @@ CONFIG_MTD_CFI=y # CONFIG_MTD_JEDECPROBE is not set CONFIG_MTD_GEN_PROBE=y # CONFIG_MTD_CFI_ADV_OPTIONS is not set +# CONFIG_MTD_CFI_NOSWAP is not set +# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set +# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set CONFIG_MTD_MAP_BANK_WIDTH_1=y CONFIG_MTD_MAP_BANK_WIDTH_2=y CONFIG_MTD_MAP_BANK_WIDTH_4=y @@ -480,19 +454,21 @@ CONFIG_MTD_CFI_UTIL=y # CONFIG_MTD_RAM is not set # CONFIG_MTD_ROM is not set # CONFIG_MTD_ABSENT is not set -# CONFIG_MTD_OBSOLETE_CHIPS is not set # # Mapping drivers for chip access # # CONFIG_MTD_COMPLEX_MAPPINGS is not set -# CONFIG_MTD_PHYSMAP is not set -CONFIG_MTD_ALCHEMY=y +CONFIG_MTD_PHYSMAP=y +# CONFIG_MTD_PHYSMAP_COMPAT is not set # CONFIG_MTD_PLATRAM is not set # # Self-contained MTD device drivers # +# CONFIG_MTD_DATAFLASH is not set +# CONFIG_MTD_M25P80 is not set +# CONFIG_MTD_SST25L is not set # CONFIG_MTD_SLRAM is not set # CONFIG_MTD_PHRAM is not set # CONFIG_MTD_MTDRAM is not set @@ -504,224 +480,129 @@ CONFIG_MTD_ALCHEMY=y # CONFIG_MTD_DOC2000 is not set # CONFIG_MTD_DOC2001 is not set # CONFIG_MTD_DOC2001PLUS is not set - -# -# NAND Flash Device Drivers -# CONFIG_MTD_NAND=y # CONFIG_MTD_NAND_VERIFY_WRITE is not set # CONFIG_MTD_NAND_ECC_SMC is not set +# CONFIG_MTD_NAND_MUSEUM_IDS is not set CONFIG_MTD_NAND_IDS=y # CONFIG_MTD_NAND_AU1550 is not set # CONFIG_MTD_NAND_DISKONCHIP is not set # CONFIG_MTD_NAND_NANDSIM is not set - -# -# OneNAND Flash Device Drivers -# +CONFIG_MTD_NAND_PLATFORM=y +# CONFIG_MTD_ALAUDA is not set # CONFIG_MTD_ONENAND is not set # -# Parallel port support -# -# CONFIG_PARPORT is not set - -# -# Plug and Play support +# LPDDR flash memory drivers # -# CONFIG_PNPACPI is not set +# CONFIG_MTD_LPDDR is not set # -# Block devices +# UBI - Unsorted block images # +# CONFIG_MTD_UBI is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y # CONFIG_BLK_DEV_COW_COMMON is not set CONFIG_BLK_DEV_LOOP=y # CONFIG_BLK_DEV_CRYPTOLOOP is not set # CONFIG_BLK_DEV_NBD is not set -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_COUNT=16 -CONFIG_BLK_DEV_RAM_SIZE=4096 -CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024 -# CONFIG_BLK_DEV_INITRD is not set +CONFIG_BLK_DEV_UB=y +# CONFIG_BLK_DEV_RAM is not set # CONFIG_CDROM_PKTCDVD is not set # CONFIG_ATA_OVER_ETH is not set - -# -# Misc devices -# - -# -# ATA/ATAPI/MFM/RLL support -# +# CONFIG_BLK_DEV_HD is not set +# CONFIG_MISC_DEVICES is not set +CONFIG_HAVE_IDE=y CONFIG_IDE=y -CONFIG_IDE_MAX_HWIFS=4 -CONFIG_BLK_DEV_IDE=y # -# Please see Documentation/ide.txt for help/info on IDE drives +# Please see Documentation/ide/ide.txt for help/info on IDE drives # +CONFIG_IDE_XFER_MODE=y +CONFIG_IDE_ATAPI=y # CONFIG_BLK_DEV_IDE_SATA is not set -CONFIG_BLK_DEV_IDEDISK=y -CONFIG_IDEDISK_MULTI_MODE=y -CONFIG_BLK_DEV_IDECS=m -# CONFIG_BLK_DEV_IDECD is not set +CONFIG_IDE_GD=y +CONFIG_IDE_GD_ATA=y +# CONFIG_IDE_GD_ATAPI is not set +CONFIG_BLK_DEV_IDECS=y +CONFIG_BLK_DEV_IDECD=y +CONFIG_BLK_DEV_IDECD_VERBOSE_ERRORS=y # CONFIG_BLK_DEV_IDETAPE is not set -# CONFIG_BLK_DEV_IDEFLOPPY is not set -# CONFIG_BLK_DEV_IDESCSI is not set -# CONFIG_IDE_TASK_IOCTL is not set +CONFIG_IDE_TASK_IOCTL=y +# CONFIG_IDE_PROC_FS is not set # # IDE chipset support/bugfixes # -CONFIG_IDE_GENERIC=y +# CONFIG_IDE_GENERIC is not set +# CONFIG_BLK_DEV_PLATFORM is not set CONFIG_BLK_DEV_IDE_AU1XXX=y CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA=y # CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA is not set -CONFIG_BLK_DEV_IDE_AU1XXX_SEQTS_PER_RQ=128 -# CONFIG_IDE_ARM is not set # CONFIG_BLK_DEV_IDEDMA is not set -# CONFIG_IDEDMA_AUTO is not set -# CONFIG_BLK_DEV_HD is not set # # SCSI device support # # CONFIG_RAID_ATTRS is not set -CONFIG_SCSI=y -CONFIG_SCSI_TGT=m +# CONFIG_SCSI is not set +# CONFIG_SCSI_DMA is not set # CONFIG_SCSI_NETLINK is not set -CONFIG_SCSI_PROC_FS=y - -# -# SCSI support type (disk, tape, CD-ROM) -# -CONFIG_BLK_DEV_SD=y -# CONFIG_CHR_DEV_ST is not set -# CONFIG_CHR_DEV_OSST is not set -CONFIG_BLK_DEV_SR=y -# CONFIG_BLK_DEV_SR_VENDOR is not set -CONFIG_CHR_DEV_SG=y -# CONFIG_CHR_DEV_SCH is not set - -# -# Some SCSI devices (e.g. CD jukebox) support multiple LUNs -# -CONFIG_SCSI_MULTI_LUN=y -# CONFIG_SCSI_CONSTANTS is not set -# CONFIG_SCSI_LOGGING is not set -CONFIG_SCSI_SCAN_ASYNC=y - -# -# SCSI Transports -# -# CONFIG_SCSI_SPI_ATTRS is not set -# CONFIG_SCSI_FC_ATTRS is not set -# CONFIG_SCSI_ISCSI_ATTRS is not set -# CONFIG_SCSI_SAS_ATTRS is not set -# CONFIG_SCSI_SAS_LIBSAS is not set - -# -# SCSI low-level drivers -# -# CONFIG_ISCSI_TCP is not set -# CONFIG_SCSI_DEBUG is not set - -# -# PCMCIA SCSI adapter support -# -# CONFIG_PCMCIA_AHA152X is not set -# CONFIG_PCMCIA_FDOMAIN is not set -# CONFIG_PCMCIA_NINJA_SCSI is not set -# CONFIG_PCMCIA_QLOGIC is not set -# CONFIG_PCMCIA_SYM53C500 is not set - -# -# Serial ATA (prod) and Parallel ATA (experimental) drivers -# # CONFIG_ATA is not set - -# -# Multi-device support (RAID and LVM) -# # CONFIG_MD is not set - -# -# Fusion MPT device support -# -# CONFIG_FUSION is not set - -# -# IEEE 1394 (FireWire) support -# - -# -# I2O device support -# - -# -# Network device support -# CONFIG_NETDEVICES=y # CONFIG_DUMMY is not set # CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set # CONFIG_EQUALIZER is not set # CONFIG_TUN is not set - -# -# PHY device support -# +# CONFIG_VETH is not set # CONFIG_PHYLIB is not set - -# -# Ethernet (10 or 100Mbit) -# CONFIG_NET_ETHERNET=y -CONFIG_MII=m +CONFIG_MII=y +# CONFIG_AX88796 is not set # CONFIG_MIPS_AU1X00_ENET is not set -# CONFIG_SMC91X is not set +CONFIG_SMC91X=y # CONFIG_DM9000 is not set - -# -# Ethernet (1000 Mbit) -# - -# -# Ethernet (10000 Mbit) -# - -# -# Token Ring devices -# - -# -# Wireless LAN (non-hamradio) -# -# CONFIG_NET_RADIO is not set - -# -# PCMCIA network device support -# +# CONFIG_ENC28J60 is not set +# CONFIG_ETHOC is not set +# CONFIG_DNET is not set +# CONFIG_IBM_NEW_EMAC_ZMII is not set +# CONFIG_IBM_NEW_EMAC_RGMII is not set +# CONFIG_IBM_NEW_EMAC_TAH is not set +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set +# CONFIG_B44 is not set +# CONFIG_KS8842 is not set +# CONFIG_KS8851 is not set +# CONFIG_KS8851_MLL is not set +# CONFIG_NETDEV_1000 is not set +# CONFIG_NETDEV_10000 is not set +# CONFIG_WLAN is not set + +# +# Enable WiMAX (Networking options) to see the WiMAX drivers +# + +# +# USB Network Adapters +# +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_USBNET is not set # CONFIG_NET_PCMCIA is not set - -# -# Wan interfaces -# # CONFIG_WAN is not set # CONFIG_PPP is not set # CONFIG_SLIP is not set -# CONFIG_SHAPER is not set # CONFIG_NETCONSOLE is not set # CONFIG_NETPOLL is not set # CONFIG_NET_POLL_CONTROLLER is not set - -# -# ISDN subsystem -# # CONFIG_ISDN is not set - -# -# Telephony Support -# # CONFIG_PHONE is not set # @@ -729,16 +610,16 @@ CONFIG_MII=m # CONFIG_INPUT=y # CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set # # Userland interfaces # CONFIG_INPUT_MOUSEDEV=y -CONFIG_INPUT_MOUSEDEV_PSAUX=y +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 # CONFIG_INPUT_JOYDEV is not set -# CONFIG_INPUT_TSDEV is not set CONFIG_INPUT_EVDEV=y # CONFIG_INPUT_EVBUG is not set @@ -748,28 +629,26 @@ CONFIG_INPUT_EVDEV=y # CONFIG_INPUT_KEYBOARD is not set # CONFIG_INPUT_MOUSE is not set # CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set # CONFIG_INPUT_TOUCHSCREEN is not set # CONFIG_INPUT_MISC is not set # # Hardware I/O ports # -CONFIG_SERIO=y -# CONFIG_SERIO_I8042 is not set -CONFIG_SERIO_SERPORT=y -# CONFIG_SERIO_LIBPS2 is not set -CONFIG_SERIO_RAW=y +# CONFIG_SERIO is not set # CONFIG_GAMEPORT is not set # # Character devices # CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y CONFIG_VT_CONSOLE=y CONFIG_HW_CONSOLE=y CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_DEVKMEM=y # CONFIG_SERIAL_NONSTANDARD is not set -# CONFIG_AU1X00_GPIO is not set # # Serial drivers @@ -777,33 +656,22 @@ CONFIG_VT_HW_CONSOLE_BINDING=y CONFIG_SERIAL_8250=y CONFIG_SERIAL_8250_CONSOLE=y # CONFIG_SERIAL_8250_CS is not set -CONFIG_SERIAL_8250_NR_UARTS=4 -CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +CONFIG_SERIAL_8250_NR_UARTS=2 +CONFIG_SERIAL_8250_RUNTIME_UARTS=2 # CONFIG_SERIAL_8250_EXTENDED is not set CONFIG_SERIAL_8250_AU1X00=y # # Non-8250 serial port support # +# CONFIG_SERIAL_MAX3100 is not set CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y CONFIG_UNIX98_PTYS=y -CONFIG_LEGACY_PTYS=y -CONFIG_LEGACY_PTY_COUNT=256 - -# -# IPMI -# +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set +# CONFIG_LEGACY_PTYS is not set # CONFIG_IPMI_HANDLER is not set - -# -# Watchdog Cards -# -# CONFIG_WATCHDOG is not set # CONFIG_HW_RANDOM is not set -# CONFIG_RTC is not set -# CONFIG_GEN_RTC is not set -# CONFIG_DTLK is not set # CONFIG_R3964 is not set # @@ -812,225 +680,606 @@ CONFIG_LEGACY_PTY_COUNT=256 # CONFIG_SYNCLINK_CS is not set # CONFIG_CARDMAN_4000 is not set # CONFIG_CARDMAN_4040 is not set +# CONFIG_IPWIRELESS is not set # CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +# CONFIG_I2C_COMPAT is not set +CONFIG_I2C_CHARDEV=y +# CONFIG_I2C_HELPER_AUTO is not set # -# TPM devices +# I2C Algorithms # -# CONFIG_TCG_TPM is not set +# CONFIG_I2C_ALGOBIT is not set +# CONFIG_I2C_ALGOPCF is not set +# CONFIG_I2C_ALGOPCA is not set # -# I2C support +# I2C Hardware Bus support # -# CONFIG_I2C is not set # -# SPI support +# I2C system bus drivers (mostly embedded / system-on-chip) # -# CONFIG_SPI is not set -# CONFIG_SPI_MASTER is not set +CONFIG_I2C_AU1550=y +# CONFIG_I2C_GPIO is not set +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_SIMTEC is not set # -# Dallas's 1-wire bus +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_TAOS_EVM is not set +# CONFIG_I2C_TINY_USB is not set + +# +# Other I2C/SMBus bus drivers +# +# CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_STUB is not set + +# +# Miscellaneous I2C Chip support +# +# CONFIG_DS1682 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# CONFIG_I2C_DEBUG_CHIP is not set +CONFIG_SPI=y +CONFIG_SPI_MASTER=y + +# +# SPI Master Controller Drivers +# +CONFIG_SPI_AU1550=y +CONFIG_SPI_BITBANG=y +# CONFIG_SPI_GPIO is not set + +# +# SPI Protocol Masters +# +# CONFIG_SPI_SPIDEV is not set +# CONFIG_SPI_TLE62X0 is not set + +# +# PPS support +# +# CONFIG_PPS is not set +CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y +CONFIG_GPIOLIB=y +CONFIG_GPIO_SYSFS=y + +# +# Memory mapped GPIO expanders: # -# CONFIG_W1 is not set # -# Hardware Monitoring support +# I2C GPIO expanders: # -# CONFIG_HWMON is not set -# CONFIG_HWMON_VID is not set +# CONFIG_GPIO_MAX732X is not set +# CONFIG_GPIO_PCA953X is not set +# CONFIG_GPIO_PCF857X is not set # -# Multimedia devices +# PCI GPIO expanders: # -# CONFIG_VIDEO_DEV is not set # -# Digital Video Broadcasting Devices +# SPI GPIO expanders: # -# CONFIG_DVB is not set +# CONFIG_GPIO_MAX7301 is not set +# CONFIG_GPIO_MCP23S08 is not set +# CONFIG_GPIO_MC33880 is not set + +# +# AC97 GPIO expanders: +# +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +CONFIG_HWMON=y +CONFIG_HWMON_VID=y +# CONFIG_HWMON_DEBUG_CHIP is not set + +# +# Native drivers +# +# CONFIG_SENSORS_AD7414 is not set +# CONFIG_SENSORS_AD7418 is not set +# CONFIG_SENSORS_ADCXX is not set +# CONFIG_SENSORS_ADM1021 is not set +CONFIG_SENSORS_ADM1025=y +# CONFIG_SENSORS_ADM1026 is not set +# CONFIG_SENSORS_ADM1029 is not set +# CONFIG_SENSORS_ADM1031 is not set +# CONFIG_SENSORS_ADM9240 is not set +# CONFIG_SENSORS_ADT7462 is not set +# CONFIG_SENSORS_ADT7470 is not set +# CONFIG_SENSORS_ADT7473 is not set +# CONFIG_SENSORS_ADT7475 is not set +# CONFIG_SENSORS_ATXP1 is not set +# CONFIG_SENSORS_DS1621 is not set +# CONFIG_SENSORS_F71805F is not set +# CONFIG_SENSORS_F71882FG is not set +# CONFIG_SENSORS_F75375S is not set +# CONFIG_SENSORS_G760A is not set +# CONFIG_SENSORS_GL518SM is not set +# CONFIG_SENSORS_GL520SM is not set +# CONFIG_SENSORS_IT87 is not set +# CONFIG_SENSORS_LM63 is not set +CONFIG_SENSORS_LM70=y +# CONFIG_SENSORS_LM75 is not set +# CONFIG_SENSORS_LM77 is not set +# CONFIG_SENSORS_LM78 is not set +# CONFIG_SENSORS_LM80 is not set +# CONFIG_SENSORS_LM83 is not set +# CONFIG_SENSORS_LM85 is not set +# CONFIG_SENSORS_LM87 is not set +# CONFIG_SENSORS_LM90 is not set +# CONFIG_SENSORS_LM92 is not set +# CONFIG_SENSORS_LM93 is not set +# CONFIG_SENSORS_LTC4215 is not set +# CONFIG_SENSORS_LTC4245 is not set +# CONFIG_SENSORS_LM95241 is not set +# CONFIG_SENSORS_MAX1111 is not set +# CONFIG_SENSORS_MAX1619 is not set +# CONFIG_SENSORS_MAX6650 is not set +# CONFIG_SENSORS_PC87360 is not set +# CONFIG_SENSORS_PC87427 is not set +# CONFIG_SENSORS_PCF8591 is not set +# CONFIG_SENSORS_SHT15 is not set +# CONFIG_SENSORS_DME1737 is not set +# CONFIG_SENSORS_SMSC47M1 is not set +# CONFIG_SENSORS_SMSC47M192 is not set +# CONFIG_SENSORS_SMSC47B397 is not set +# CONFIG_SENSORS_ADS7828 is not set +# CONFIG_SENSORS_THMC50 is not set +# CONFIG_SENSORS_TMP401 is not set +# CONFIG_SENSORS_TMP421 is not set +# CONFIG_SENSORS_VT1211 is not set +# CONFIG_SENSORS_W83781D is not set +# CONFIG_SENSORS_W83791D is not set +# CONFIG_SENSORS_W83792D is not set +# CONFIG_SENSORS_W83793 is not set +# CONFIG_SENSORS_W83L785TS is not set +# CONFIG_SENSORS_W83L786NG is not set +# CONFIG_SENSORS_W83627HF is not set +# CONFIG_SENSORS_W83627EHF is not set +# CONFIG_SENSORS_LIS3_SPI is not set +# CONFIG_THERMAL is not set +# CONFIG_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_UCB1400_CORE is not set +# CONFIG_TPS65010 is not set +# CONFIG_TWL4030_CORE is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM831X is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_MFD_PCF50633 is not set +# CONFIG_MFD_MC13783 is not set +# CONFIG_AB3100_CORE is not set +# CONFIG_EZX_PCAP is not set +# CONFIG_REGULATOR is not set +# CONFIG_MEDIA_SUPPORT is not set # # Graphics support # -# CONFIG_FIRMWARE_EDID is not set +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set CONFIG_FB=y +# CONFIG_FIRMWARE_EDID is not set +# CONFIG_FB_DDC is not set +# CONFIG_FB_BOOT_VESA_SUPPORT is not set CONFIG_FB_CFB_FILLRECT=y CONFIG_FB_CFB_COPYAREA=y CONFIG_FB_CFB_IMAGEBLIT=y +# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set +# CONFIG_FB_SYS_FILLRECT is not set +# CONFIG_FB_SYS_COPYAREA is not set +# CONFIG_FB_SYS_IMAGEBLIT is not set +# CONFIG_FB_FOREIGN_ENDIAN is not set +# CONFIG_FB_SYS_FOPS is not set # CONFIG_FB_SVGALIB is not set # CONFIG_FB_MACMODES is not set # CONFIG_FB_BACKLIGHT is not set # CONFIG_FB_MODE_HELPERS is not set # CONFIG_FB_TILEBLITTING is not set + +# +# Frame buffer hardware drivers +# # CONFIG_FB_S1D13XXX is not set CONFIG_FB_AU1200=y # CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_METRONOME is not set +# CONFIG_FB_MB862XX is not set +# CONFIG_FB_BROADSHEET is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set # # Console display driver support # -CONFIG_VGA_CONSOLE=y -# CONFIG_VGACON_SOFT_SCROLLBACK is not set +# CONFIG_VGA_CONSOLE is not set CONFIG_DUMMY_CONSOLE=y -# CONFIG_FRAMEBUFFER_CONSOLE is not set +CONFIG_FRAMEBUFFER_CONSOLE=y +# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set +# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set +CONFIG_FONTS=y +# CONFIG_FONT_8x8 is not set +CONFIG_FONT_8x16=y +# CONFIG_FONT_6x11 is not set +# CONFIG_FONT_7x14 is not set +# CONFIG_FONT_PEARL_8x8 is not set +# CONFIG_FONT_ACORN_8x8 is not set +# CONFIG_FONT_MINI_4x6 is not set +# CONFIG_FONT_SUN8x16 is not set +# CONFIG_FONT_SUN12x22 is not set +# CONFIG_FONT_10x18 is not set +# CONFIG_LOGO is not set +CONFIG_SOUND=y +# CONFIG_SOUND_OSS_CORE is not set +CONFIG_SND=y +CONFIG_SND_TIMER=y +CONFIG_SND_PCM=y +CONFIG_SND_JACK=y +# CONFIG_SND_SEQUENCER is not set +# CONFIG_SND_MIXER_OSS is not set +# CONFIG_SND_PCM_OSS is not set +# CONFIG_SND_HRTIMER is not set +CONFIG_SND_DYNAMIC_MINORS=y +# CONFIG_SND_SUPPORT_OLD_API is not set +# CONFIG_SND_VERBOSE_PROCFS is not set +# CONFIG_SND_VERBOSE_PRINTK is not set +# CONFIG_SND_DEBUG is not set +CONFIG_SND_VMASTER=y +# CONFIG_SND_RAWMIDI_SEQ is not set +# CONFIG_SND_OPL3_LIB_SEQ is not set +# CONFIG_SND_OPL4_LIB_SEQ is not set +# CONFIG_SND_SBAWE_SEQ is not set +# CONFIG_SND_EMU10K1_SEQ is not set +CONFIG_SND_AC97_CODEC=y +# CONFIG_SND_DRIVERS is not set +# CONFIG_SND_SPI is not set +# CONFIG_SND_MIPS is not set +# CONFIG_SND_USB is not set +# CONFIG_SND_PCMCIA is not set +CONFIG_SND_SOC=y +CONFIG_SND_SOC_AC97_BUS=y +CONFIG_SND_SOC_AU1XPSC=y +CONFIG_SND_SOC_AU1XPSC_I2S=y +CONFIG_SND_SOC_AU1XPSC_AC97=y +CONFIG_SND_SOC_DB1200=y +CONFIG_SND_SOC_I2C_AND_SPI=y +# CONFIG_SND_SOC_ALL_CODECS is not set +CONFIG_SND_SOC_AC97_CODEC=y +CONFIG_SND_SOC_WM8731=y +# CONFIG_SOUND_PRIME is not set +CONFIG_AC97_BUS=y +CONFIG_HID_SUPPORT=y +CONFIG_HID=y +CONFIG_HIDRAW=y + +# +# USB Input Devices +# +CONFIG_USB_HID=y +# CONFIG_HID_PID is not set +CONFIG_USB_HIDDEV=y + +# +# Special HID drivers +# +# CONFIG_HID_A4TECH is not set +# CONFIG_HID_APPLE is not set +# CONFIG_HID_BELKIN is not set +# CONFIG_HID_CHERRY is not set +# CONFIG_HID_CHICONY is not set +# CONFIG_HID_CYPRESS is not set +# CONFIG_HID_DRAGONRISE is not set +# CONFIG_HID_EZKEY is not set +# CONFIG_HID_KYE is not set +# CONFIG_HID_GYRATION is not set +# CONFIG_HID_TWINHAN is not set +# CONFIG_HID_KENSINGTON is not set +# CONFIG_HID_LOGITECH is not set +# CONFIG_HID_MICROSOFT is not set +# CONFIG_HID_MONTEREY is not set +# CONFIG_HID_NTRIG is not set +# CONFIG_HID_PANTHERLORD is not set +# CONFIG_HID_PETALYNX is not set +# CONFIG_HID_SAMSUNG is not set +# CONFIG_HID_SONY is not set +# CONFIG_HID_SUNPLUS is not set +# CONFIG_HID_GREENASIA is not set +# CONFIG_HID_SMARTJOYPLUS is not set +# CONFIG_HID_TOPSEED is not set +# CONFIG_HID_THRUSTMASTER is not set +# CONFIG_HID_ZEROPLUS is not set +CONFIG_USB_SUPPORT=y +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y +CONFIG_USB_ARCH_HAS_EHCI=y +CONFIG_USB=y +CONFIG_USB_DEBUG=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y # -# Logo configuration +# Miscellaneous USB options # -CONFIG_LOGO=y -CONFIG_LOGO_LINUX_MONO=y -CONFIG_LOGO_LINUX_VGA16=y -CONFIG_LOGO_LINUX_CLUT224=y -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set +# CONFIG_USB_DEVICEFS is not set +# CONFIG_USB_DEVICE_CLASS is not set +CONFIG_USB_DYNAMIC_MINORS=y +# CONFIG_USB_OTG is not set +# CONFIG_USB_OTG_WHITELIST is not set +# CONFIG_USB_OTG_BLACKLIST_HUB is not set +# CONFIG_USB_MON is not set +# CONFIG_USB_WUSB is not set +# CONFIG_USB_WUSB_CBAF is not set # -# Sound +# USB Host Controller Drivers # -# CONFIG_SOUND is not set +# CONFIG_USB_C67X00_HCD is not set +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y +CONFIG_USB_EHCI_TT_NEWSCHED=y +# CONFIG_USB_OXU210HP_HCD is not set +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_ISP1760_HCD is not set +# CONFIG_USB_ISP1362_HCD is not set +CONFIG_USB_OHCI_HCD=y +# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set +# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_HWA_HCD is not set # -# HID Devices +# USB Device Class drivers # -CONFIG_HID=y -# CONFIG_HID_DEBUG is not set +# CONFIG_USB_ACM is not set +# CONFIG_USB_PRINTER is not set +# CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set # -# USB support +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may # -CONFIG_USB_ARCH_HAS_HCD=y -CONFIG_USB_ARCH_HAS_OHCI=y -CONFIG_USB_ARCH_HAS_EHCI=y -# CONFIG_USB is not set # -# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' +# also be needed; see USB_STORAGE Help for more info +# +# CONFIG_USB_LIBUSUAL is not set + +# +# USB Imaging devices # +# CONFIG_USB_MDC800 is not set # -# USB Gadget Support +# USB port drivers # -CONFIG_USB_GADGET=m -# CONFIG_USB_GADGET_DEBUG_FILES is not set -# CONFIG_USB_GADGET_NET2280 is not set -# CONFIG_USB_GADGET_PXA2XX is not set -# CONFIG_USB_GADGET_GOKU is not set -# CONFIG_USB_GADGET_LH7A40X is not set -# CONFIG_USB_GADGET_OMAP is not set -# CONFIG_USB_GADGET_AT91 is not set -# CONFIG_USB_GADGET_DUMMY_HCD is not set -# CONFIG_USB_GADGET_DUALSPEED is not set +# CONFIG_USB_SERIAL is not set # -# MMC/SD Card support +# USB Miscellaneous drivers # +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_BERRY_CHARGE is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_SISUSBVGA is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_TEST is not set +# CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_VST is not set +# CONFIG_USB_GADGET is not set + +# +# OTG and related infrastructure +# +# CONFIG_USB_GPIO_VBUS is not set +# CONFIG_NOP_USB_XCEIV is not set CONFIG_MMC=y # CONFIG_MMC_DEBUG is not set -CONFIG_MMC_BLOCK=y -CONFIG_MMC_AU1X=y +# CONFIG_MMC_UNSAFE_RESUME is not set # -# LED devices +# MMC/SD/SDIO Card Drivers # -# CONFIG_NEW_LEDS is not set +CONFIG_MMC_BLOCK=y +# CONFIG_MMC_BLOCK_BOUNCE is not set +# CONFIG_SDIO_UART is not set +# CONFIG_MMC_TEST is not set # -# LED drivers +# MMC/SD/SDIO Host Controller Drivers # +# CONFIG_MMC_SDHCI is not set +CONFIG_MMC_AU1X=y +# CONFIG_MMC_AT91 is not set +# CONFIG_MMC_ATMELMCI is not set +# CONFIG_MMC_SPI is not set +# CONFIG_MEMSTICK is not set +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y # -# LED Triggers +# LED drivers # +# CONFIG_LEDS_PCA9532 is not set +# CONFIG_LEDS_GPIO is not set +# CONFIG_LEDS_LP3944 is not set +# CONFIG_LEDS_PCA955X is not set +# CONFIG_LEDS_DAC124S085 is not set +# CONFIG_LEDS_BD2802 is not set # -# InfiniBand support +# LED Triggers # +CONFIG_LEDS_TRIGGERS=y +# CONFIG_LEDS_TRIGGER_TIMER is not set +# CONFIG_LEDS_TRIGGER_IDE_DISK is not set +# CONFIG_LEDS_TRIGGER_HEARTBEAT is not set +# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set +# CONFIG_LEDS_TRIGGER_GPIO is not set +# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set # -# EDAC - error detection and reporting (RAS) (EXPERIMENTAL) +# iptables trigger is under Netfilter config (LED target) # +# CONFIG_ACCESSIBILITY is not set +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set # -# Real Time Clock +# RTC interfaces # -# CONFIG_RTC_CLASS is not set +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +# CONFIG_RTC_DRV_TEST is not set # -# DMA Engine support +# I2C RTC drivers # -# CONFIG_DMA_ENGINE is not set +# CONFIG_RTC_DRV_DS1307 is not set +# CONFIG_RTC_DRV_DS1374 is not set +# CONFIG_RTC_DRV_DS1672 is not set +# CONFIG_RTC_DRV_MAX6900 is not set +# CONFIG_RTC_DRV_RS5C372 is not set +# CONFIG_RTC_DRV_ISL1208 is not set +# CONFIG_RTC_DRV_X1205 is not set +# CONFIG_RTC_DRV_PCF8563 is not set +# CONFIG_RTC_DRV_PCF8583 is not set +# CONFIG_RTC_DRV_M41T80 is not set +# CONFIG_RTC_DRV_S35390A is not set +# CONFIG_RTC_DRV_FM3130 is not set +# CONFIG_RTC_DRV_RX8581 is not set +# CONFIG_RTC_DRV_RX8025 is not set # -# DMA Clients +# SPI RTC drivers # +# CONFIG_RTC_DRV_M41T94 is not set +# CONFIG_RTC_DRV_DS1305 is not set +# CONFIG_RTC_DRV_DS1390 is not set +# CONFIG_RTC_DRV_MAX6902 is not set +# CONFIG_RTC_DRV_R9701 is not set +# CONFIG_RTC_DRV_RS5C348 is not set +# CONFIG_RTC_DRV_DS3234 is not set +# CONFIG_RTC_DRV_PCF2123 is not set # -# DMA Devices +# Platform RTC drivers # +# CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_DS1286 is not set +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_BQ4802 is not set +# CONFIG_RTC_DRV_V3020 is not set # -# Auxiliary Display support +# on-CPU RTC drivers # +CONFIG_RTC_DRV_AU1XXX=y +# CONFIG_DMADEVICES is not set +# CONFIG_AUXDISPLAY is not set +# CONFIG_UIO is not set # -# Virtualization +# TI VLYNQ # +# CONFIG_STAGING is not set # # File systems # CONFIG_EXT2_FS=y -CONFIG_EXT2_FS_XATTR=y -CONFIG_EXT2_FS_POSIX_ACL=y -# CONFIG_EXT2_FS_SECURITY is not set +# CONFIG_EXT2_FS_XATTR is not set # CONFIG_EXT2_FS_XIP is not set -CONFIG_EXT3_FS=y -CONFIG_EXT3_FS_XATTR=y -CONFIG_EXT3_FS_POSIX_ACL=y -CONFIG_EXT3_FS_SECURITY=y -# CONFIG_EXT4DEV_FS is not set -CONFIG_JBD=y -# CONFIG_JBD_DEBUG is not set -CONFIG_FS_MBCACHE=y +# CONFIG_EXT3_FS is not set +# CONFIG_EXT4_FS is not set # CONFIG_REISERFS_FS is not set -CONFIG_JFS_FS=y -# CONFIG_JFS_POSIX_ACL is not set -# CONFIG_JFS_SECURITY is not set -# CONFIG_JFS_DEBUG is not set -# CONFIG_JFS_STATISTICS is not set -CONFIG_FS_POSIX_ACL=y +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set # CONFIG_XFS_FS is not set -# CONFIG_GFS2_FS is not set # CONFIG_OCFS2_FS is not set -# CONFIG_MINIX_FS is not set -# CONFIG_ROMFS_FS is not set +# CONFIG_BTRFS_FS is not set +# CONFIG_NILFS2_FS is not set +CONFIG_FILE_LOCKING=y +CONFIG_FSNOTIFY=y +CONFIG_DNOTIFY=y CONFIG_INOTIFY=y CONFIG_INOTIFY_USER=y # CONFIG_QUOTA is not set -CONFIG_DNOTIFY=y # CONFIG_AUTOFS_FS is not set # CONFIG_AUTOFS4_FS is not set # CONFIG_FUSE_FS is not set -CONFIG_GENERIC_ACL=y + +# +# Caches +# +# CONFIG_FSCACHE is not set # # CD-ROM/DVD Filesystems # -CONFIG_ISO9660_FS=m -CONFIG_JOLIET=y -CONFIG_ZISOFS=y -CONFIG_UDF_FS=m -CONFIG_UDF_NLS=y +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set # # DOS/FAT/NT Filesystems # -CONFIG_FAT_FS=m -CONFIG_MSDOS_FS=m -CONFIG_VFAT_FS=m -CONFIG_FAT_DEFAULT_CODEPAGE=437 -CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_MSDOS_FS is not set +# CONFIG_VFAT_FS is not set # CONFIG_NTFS_FS is not set # @@ -1039,19 +1288,15 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_PROC_SYSCTL=y +# CONFIG_PROC_PAGE_MONITOR is not set CONFIG_SYSFS=y CONFIG_TMPFS=y -CONFIG_TMPFS_POSIX_ACL=y +# CONFIG_TMPFS_POSIX_ACL is not set # CONFIG_HUGETLB_PAGE is not set -CONFIG_RAMFS=y -CONFIG_CONFIGFS_FS=m - -# -# Miscellaneous filesystems -# +# CONFIG_CONFIGFS_FS is not set +CONFIG_MISC_FILESYSTEMS=y # CONFIG_ADFS_FS is not set # CONFIG_AFFS_FS is not set -# CONFIG_ECRYPT_FS is not set # CONFIG_HFS_FS is not set # CONFIG_HFSPLUS_FS is not set # CONFIG_BEFS_FS is not set @@ -1060,27 +1305,36 @@ CONFIG_CONFIGFS_FS=m CONFIG_JFFS2_FS=y CONFIG_JFFS2_FS_DEBUG=0 CONFIG_JFFS2_FS_WRITEBUFFER=y -# CONFIG_JFFS2_SUMMARY is not set +# CONFIG_JFFS2_FS_WBUF_VERIFY is not set +CONFIG_JFFS2_SUMMARY=y # CONFIG_JFFS2_FS_XATTR is not set -# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set +CONFIG_JFFS2_COMPRESSION_OPTIONS=y CONFIG_JFFS2_ZLIB=y +CONFIG_JFFS2_LZO=y CONFIG_JFFS2_RTIME=y -# CONFIG_JFFS2_RUBIN is not set -CONFIG_CRAMFS=m +CONFIG_JFFS2_RUBIN=y +# CONFIG_JFFS2_CMODE_NONE is not set +CONFIG_JFFS2_CMODE_PRIORITY=y +# CONFIG_JFFS2_CMODE_SIZE is not set +# CONFIG_JFFS2_CMODE_FAVOURLZO is not set +# CONFIG_CRAMFS is not set +CONFIG_SQUASHFS=y +# CONFIG_SQUASHFS_EMBEDDED is not set +CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 # CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set # CONFIG_HPFS_FS is not set # CONFIG_QNX4FS_FS is not set +# CONFIG_ROMFS_FS is not set # CONFIG_SYSV_FS is not set # CONFIG_UFS_FS is not set - -# -# Network File Systems -# +CONFIG_NETWORK_FILESYSTEMS=y CONFIG_NFS_FS=y CONFIG_NFS_V3=y # CONFIG_NFS_V3_ACL is not set # CONFIG_NFS_V4 is not set -# CONFIG_NFS_DIRECTIO is not set +CONFIG_ROOT_NFS=y # CONFIG_NFSD is not set CONFIG_LOCKD=y CONFIG_LOCKD_V4=y @@ -1088,159 +1342,124 @@ CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y # CONFIG_RPCSEC_GSS_KRB5 is not set # CONFIG_RPCSEC_GSS_SPKM3 is not set -CONFIG_SMB_FS=y -# CONFIG_SMB_NLS_DEFAULT is not set +# CONFIG_SMB_FS is not set # CONFIG_CIFS is not set # CONFIG_NCP_FS is not set # CONFIG_CODA_FS is not set # CONFIG_AFS_FS is not set -# CONFIG_9P_FS is not set # # Partition Types # -# CONFIG_PARTITION_ADVANCED is not set +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +# CONFIG_OSF_PARTITION is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_ATARI_PARTITION is not set +# CONFIG_MAC_PARTITION is not set CONFIG_MSDOS_PARTITION=y - -# -# Native Language Support -# +# CONFIG_BSD_DISKLABEL is not set +# CONFIG_MINIX_SUBPARTITION is not set +# CONFIG_SOLARIS_X86_PARTITION is not set +# CONFIG_UNIXWARE_DISKLABEL is not set +# CONFIG_LDM_PARTITION is not set +# CONFIG_SGI_PARTITION is not set +# CONFIG_ULTRIX_PARTITION is not set +# CONFIG_SUN_PARTITION is not set +# CONFIG_KARMA_PARTITION is not set +CONFIG_EFI_PARTITION=y +# CONFIG_SYSV68_PARTITION is not set CONFIG_NLS=y CONFIG_NLS_DEFAULT="iso8859-1" -CONFIG_NLS_CODEPAGE_437=m -CONFIG_NLS_CODEPAGE_737=m -CONFIG_NLS_CODEPAGE_775=m -CONFIG_NLS_CODEPAGE_850=m -CONFIG_NLS_CODEPAGE_852=m -CONFIG_NLS_CODEPAGE_855=m -CONFIG_NLS_CODEPAGE_857=m -CONFIG_NLS_CODEPAGE_860=m -CONFIG_NLS_CODEPAGE_861=m -CONFIG_NLS_CODEPAGE_862=m -CONFIG_NLS_CODEPAGE_863=m -CONFIG_NLS_CODEPAGE_864=m -CONFIG_NLS_CODEPAGE_865=m -CONFIG_NLS_CODEPAGE_866=m -CONFIG_NLS_CODEPAGE_869=m -CONFIG_NLS_CODEPAGE_936=m -CONFIG_NLS_CODEPAGE_950=m -CONFIG_NLS_CODEPAGE_932=m -CONFIG_NLS_CODEPAGE_949=m -CONFIG_NLS_CODEPAGE_874=m -CONFIG_NLS_ISO8859_8=m -CONFIG_NLS_CODEPAGE_1250=m -CONFIG_NLS_CODEPAGE_1251=m -CONFIG_NLS_ASCII=m -CONFIG_NLS_ISO8859_1=m -CONFIG_NLS_ISO8859_2=m -CONFIG_NLS_ISO8859_3=m -CONFIG_NLS_ISO8859_4=m -CONFIG_NLS_ISO8859_5=m -CONFIG_NLS_ISO8859_6=m -CONFIG_NLS_ISO8859_7=m -CONFIG_NLS_ISO8859_9=m -CONFIG_NLS_ISO8859_13=m -CONFIG_NLS_ISO8859_14=m -CONFIG_NLS_ISO8859_15=m -CONFIG_NLS_KOI8_R=m -CONFIG_NLS_KOI8_U=m -CONFIG_NLS_UTF8=m - -# -# Distributed Lock Manager -# -CONFIG_DLM=m -CONFIG_DLM_TCP=y -# CONFIG_DLM_SCTP is not set -# CONFIG_DLM_DEBUG is not set - -# -# Profiling support -# -# CONFIG_PROFILING is not set +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +CONFIG_NLS_CODEPAGE_850=y +CONFIG_NLS_CODEPAGE_852=y +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +CONFIG_NLS_CODEPAGE_1250=y +# CONFIG_NLS_CODEPAGE_1251 is not set +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_ISO8859_2=y +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +CONFIG_NLS_ISO8859_15=y +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +CONFIG_NLS_UTF8=y +# CONFIG_DLM is not set # # Kernel hacking # CONFIG_TRACE_IRQFLAGS_SUPPORT=y # CONFIG_PRINTK_TIME is not set -CONFIG_ENABLE_MUST_CHECK=y -# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_ENABLE_WARN_DEPRECATED is not set +# CONFIG_ENABLE_MUST_CHECK is not set +CONFIG_FRAME_WARN=1024 +CONFIG_MAGIC_SYSRQ=y +CONFIG_STRIP_ASM_SYMS=y # CONFIG_UNUSED_SYMBOLS is not set # CONFIG_DEBUG_FS is not set # CONFIG_HEADERS_CHECK is not set # CONFIG_DEBUG_KERNEL is not set -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_CROSSCOMPILE=y -CONFIG_CMDLINE="mem=48M" +# CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +CONFIG_TRACING_SUPPORT=y +# CONFIG_FTRACE is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +CONFIG_CMDLINE="console=ttyS0,115200" # # Security options # -CONFIG_KEYS=y -CONFIG_KEYS_DEBUG_PROC_KEYS=y +# CONFIG_KEYS is not set # CONFIG_SECURITY is not set - -# -# Cryptographic options -# -CONFIG_CRYPTO=y -CONFIG_CRYPTO_ALGAPI=y -CONFIG_CRYPTO_BLKCIPHER=m -CONFIG_CRYPTO_HASH=m -CONFIG_CRYPTO_MANAGER=m -CONFIG_CRYPTO_HMAC=m -CONFIG_CRYPTO_XCBC=m -CONFIG_CRYPTO_NULL=m -CONFIG_CRYPTO_MD4=m -CONFIG_CRYPTO_MD5=y -CONFIG_CRYPTO_SHA1=m -CONFIG_CRYPTO_SHA256=m -CONFIG_CRYPTO_SHA512=m -CONFIG_CRYPTO_WP512=m -CONFIG_CRYPTO_TGR192=m -CONFIG_CRYPTO_GF128MUL=m -CONFIG_CRYPTO_ECB=m -CONFIG_CRYPTO_CBC=m -CONFIG_CRYPTO_PCBC=m -CONFIG_CRYPTO_LRW=m -CONFIG_CRYPTO_DES=m -CONFIG_CRYPTO_FCRYPT=m -CONFIG_CRYPTO_BLOWFISH=m -CONFIG_CRYPTO_TWOFISH=m -CONFIG_CRYPTO_TWOFISH_COMMON=m -CONFIG_CRYPTO_SERPENT=m -CONFIG_CRYPTO_AES=m -CONFIG_CRYPTO_CAST5=m -CONFIG_CRYPTO_CAST6=m -CONFIG_CRYPTO_TEA=m -CONFIG_CRYPTO_ARC4=m -CONFIG_CRYPTO_KHAZAD=m -CONFIG_CRYPTO_ANUBIS=m -CONFIG_CRYPTO_DEFLATE=m -CONFIG_CRYPTO_MICHAEL_MIC=m -CONFIG_CRYPTO_CRC32C=m -CONFIG_CRYPTO_CAMELLIA=m -# CONFIG_CRYPTO_TEST is not set - -# -# Hardware crypto devices -# +CONFIG_SECURITYFS=y +CONFIG_SECURITY_FILE_CAPABILITIES=y +# CONFIG_CRYPTO is not set +# CONFIG_BINARY_PRINTF is not set # # Library routines # CONFIG_BITREVERSE=y -CONFIG_CRC_CCITT=y +CONFIG_GENERIC_FIND_LAST_BIT=y +# CONFIG_CRC_CCITT is not set # CONFIG_CRC16 is not set +# CONFIG_CRC_T10DIF is not set +# CONFIG_CRC_ITU_T is not set CONFIG_CRC32=y -CONFIG_LIBCRC32C=y +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set CONFIG_ZLIB_INFLATE=y CONFIG_ZLIB_DEFLATE=y -CONFIG_TEXTSEARCH=y -CONFIG_TEXTSEARCH_KMP=m -CONFIG_TEXTSEARCH_BM=m -CONFIG_TEXTSEARCH_FSM=m -CONFIG_PLIST=y +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y CONFIG_HAS_IOMEM=y CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y +CONFIG_NLATTR=y -- 1.6.5.1 From manuel.lauss@googlemail.com Mon Nov 2 21:22:47 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 02 Nov 2009 21:22:53 +0100 (CET) Received: from mail-ew0-f214.google.com ([209.85.219.214]:39043 "EHLO mail-ew0-f214.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1493952AbZKBUWB (ORCPT ); Mon, 2 Nov 2009 21:22:01 +0100 Received: by ewy10 with SMTP id 10so6099707ewy.33 for ; Mon, 02 Nov 2009 12:21:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer:in-reply-to:references; bh=rFo7i5VRoTblMgszIjNaYkz/DuKPvRAWrnnk8fn9+zs=; b=JWEGhJzOaPLe2h7a+6QrcUYqaZ2nz5J3ixISO6BkiwyfIpFpeae+vrGEDz+1BNUKeA swTM8BqnLQyonfY88avkjsIgqeFYMSRCPHNw6QwPaWcAS45w1zqbbiTOUyQpH/aO9Eye 97Zwgfgmsmv/eCsZV+bh7Z0KJtoob/pAuAtoo= DomainKey-Signature: a=rsa-sha1; c=nofws; d=googlemail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; b=viEmm8QY/jT/rGl05UtcV9HwCGXmL+uEs2kmjoqx1eA8CfGrB8QaAdvXWEFhcWs4cl Ff1hg5SIQTWHpNVkUmyzUsCNBco3qq4Q9U938zXNdIRF8ydIRAahJJsdXK6t+QGS6uxn dfQl2zmO/3I72X8OyFxFsKnALP1ve7ZlOlMNE= Received: by 10.216.90.131 with SMTP id e3mr5372289wef.69.1257193314954; Mon, 02 Nov 2009 12:21:54 -0800 (PST) Received: from localhost.localdomain (p5496F7DD.dip.t-dialin.net [84.150.247.221]) by mx.google.com with ESMTPS id m5sm15375gve.11.2009.11.02.12.21.53 (version=TLSv1/SSLv3 cipher=RC4-MD5); Mon, 02 Nov 2009 12:21:54 -0800 (PST) From: Manuel Lauss To: Linux-MIPS Cc: Manuel Lauss , alsa-devel@alsa-project.org, Mark Brown Subject: [RFC PATCH 2/3] MIPS: Alchemy: DB1200 AC97+I2S audio support. Date: Mon, 2 Nov 2009 21:21:44 +0100 Message-Id: <1257193305-29996-2-git-send-email-manuel.lauss@gmail.com> X-Mailer: git-send-email 1.6.5.1 In-Reply-To: <1257193305-29996-1-git-send-email-manuel.lauss@gmail.com> References: <1257193305-29996-1-git-send-email-manuel.lauss@gmail.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24621 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips Machine driver for DB1200 AC97 and I2S audio systems, intended as a proper reference asoc machine for Alchemy-based systems. AC97/I2S can be selected at boot time by setting switch S6.7 Cc: alsa-devel@alsa-project.org Cc: Mark Brown Signed-off-by: Manuel Lauss --- Depends on patch "ASoC: au1x: convert to platform drivers" in Mark Brown's asoc tree to actually work. arch/mips/alchemy/devboards/db1200/platform.c | 51 +++++++++ sound/soc/au1x/Kconfig | 10 +- sound/soc/au1x/Makefile | 4 +- sound/soc/au1x/db1200.c | 141 ++++++++++++++++++++++++ sound/soc/au1x/sample-ac97.c | 144 ------------------------- 5 files changed, 200 insertions(+), 150 deletions(-) create mode 100644 sound/soc/au1x/db1200.c delete mode 100644 sound/soc/au1x/sample-ac97.c diff --git a/arch/mips/alchemy/devboards/db1200/platform.c b/arch/mips/alchemy/devboards/db1200/platform.c index 5a6ef8d..d6b3e64 100644 --- a/arch/mips/alchemy/devboards/db1200/platform.c +++ b/arch/mips/alchemy/devboards/db1200/platform.c @@ -399,12 +399,43 @@ static struct platform_device db1200_spi_dev = { .resource = au1200_psc0_res, }; +static struct resource au1200_psc1_res[] = { + [0] = { + .start = PSC1_PHYS_ADDR, + .end = PSC1_PHYS_ADDR + 0x000fffff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AU1200_PSC1_INT, + .end = AU1200_PSC1_INT, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = DSCR_CMD0_PSC1_TX, + .end = DSCR_CMD0_PSC1_TX, + .flags = IORESOURCE_DMA, + }, + [3] = { + .start = DSCR_CMD0_PSC1_RX, + .end = DSCR_CMD0_PSC1_RX, + .flags = IORESOURCE_DMA, + }, +}; + +static struct platform_device db1200_audio_dev = { + /* name assigned later based on switch setting */ + .id = 1, /* PSC ID */ + .num_resources = ARRAY_SIZE(au1200_psc1_res), + .resource = au1200_psc1_res, +}; + static struct platform_device *db1200_devs[] __initdata = { NULL, /* PSC0, selected by S6.8 */ &db1200_ide_dev, &db1200_eth_dev, &db1200_rtc_dev, &db1200_nand_dev, + &db1200_audio_dev, }; static int __init db1200_dev_init(void) @@ -419,6 +450,7 @@ static int __init db1200_dev_init(void) ARRAY_SIZE(db1200_i2c_devs)); /* SWITCHES: S6.8 I2C/SPI selector (OFF=I2C ON=SPI) + * S6.7 AC97/I2S selector (OFF=AC97 ON=I2S) */ /* NOTE: GPIO215 controls OTG VBUS supply. In SPI mode however @@ -456,6 +488,25 @@ static int __init db1200_dev_init(void) __raw_writel(pfc, (void __iomem *)SYS_PINFUNC); wmb(); + /* Audio: DIP7 selects I2S(0)/AC97(1), but need I2C for I2S! + * so: DIP7=1 || DIP8=0 => AC97, DIP7=0 && DIP8=1 => I2S + */ + sw &= BCSR_SWITCHES_DIP_8 | BCSR_SWITCHES_DIP_7; + if (sw == BCSR_SWITCHES_DIP_8) { + bcsr_mod(BCSR_RESETS, 0, BCSR_RESETS_PSC1MUX); + db1200_audio_dev.name = "au1xpsc_i2s"; + printk(KERN_INFO " S6.7 ON : PSC1 mode I2S\n"); + } else { + bcsr_mod(BCSR_RESETS, BCSR_RESETS_PSC1MUX, 0); + db1200_audio_dev.name = "au1xpsc_ac97"; + printk(KERN_INFO " S6.7 OFF: PSC1 mode AC97\n"); + } + + /* Audio PSC clock is supplied externally. (FIXME: platdata!!) */ + __raw_writel(PSC_SEL_CLK_SERCLK, + (void __iomem *)KSEG1ADDR(PSC1_PHYS_ADDR) + PSC_SEL_OFFSET); + wmb(); + db1x_register_pcmcia_socket(PCMCIA_ATTR_PSEUDO_PHYS, PCMCIA_ATTR_PSEUDO_PHYS + 0x00040000 - 1, PCMCIA_MEM_PSEUDO_PHYS, diff --git a/sound/soc/au1x/Kconfig b/sound/soc/au1x/Kconfig index 410a893..4b67140 100644 --- a/sound/soc/au1x/Kconfig +++ b/sound/soc/au1x/Kconfig @@ -22,11 +22,13 @@ config SND_SOC_AU1XPSC_AC97 ## ## Boards ## -config SND_SOC_SAMPLE_PSC_AC97 - tristate "Sample Au12x0/Au1550 PSC AC97 sound machine" +config SND_SOC_DB1200 + tristate "DB1200 AC97+I2S audio support" depends on SND_SOC_AU1XPSC select SND_SOC_AU1XPSC_AC97 select SND_SOC_AC97_CODEC + select SND_SOC_AU1XPSC_I2S + select SND_SOC_WM8731 help - This is a sample AC97 sound machine for use in Au12x0/Au1550 - based systems which have audio on PSC1 (e.g. Db1200 demoboard). + Select this option to enable audio (AC97 or I2S) on the + Alchemy/AMD/RMI DB1200 demoboard. diff --git a/sound/soc/au1x/Makefile b/sound/soc/au1x/Makefile index 6c6950b..1687307 100644 --- a/sound/soc/au1x/Makefile +++ b/sound/soc/au1x/Makefile @@ -8,6 +8,6 @@ obj-$(CONFIG_SND_SOC_AU1XPSC_I2S) += snd-soc-au1xpsc-i2s.o obj-$(CONFIG_SND_SOC_AU1XPSC_AC97) += snd-soc-au1xpsc-ac97.o # Boards -snd-soc-sample-ac97-objs := sample-ac97.o +snd-soc-db1200-objs := db1200.o -obj-$(CONFIG_SND_SOC_SAMPLE_PSC_AC97) += snd-soc-sample-ac97.o +obj-$(CONFIG_SND_SOC_DB1200) += snd-soc-db1200.o diff --git a/sound/soc/au1x/db1200.c b/sound/soc/au1x/db1200.c new file mode 100644 index 0000000..cdf7be1 --- /dev/null +++ b/sound/soc/au1x/db1200.c @@ -0,0 +1,141 @@ +/* + * DB1200 ASoC audio fabric support code. + * + * (c) 2008-9 Manuel Lauss + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../codecs/ac97.h" +#include "../codecs/wm8731.h" +#include "psc.h" + +/*------------------------- AC97 PART ---------------------------*/ + +static struct snd_soc_dai_link db1200_ac97_dai = { + .name = "AC97", + .stream_name = "AC97 HiFi", + .cpu_dai = &au1xpsc_ac97_dai, + .codec_dai = &ac97_dai, +}; + +static struct snd_soc_card db1200_ac97_machine = { + .name = "DB1200_AC97", + .dai_link = &db1200_ac97_dai, + .num_links = 1, + .platform = &au1xpsc_soc_platform, +}; + +static struct snd_soc_device db1200_ac97_devdata = { + .card = &db1200_ac97_machine, + .codec_dev = &soc_codec_dev_ac97, +}; + +/*------------------------- I2S PART ---------------------------*/ + +static int db1200_i2s_startup(struct snd_pcm_substream *substream) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_dai *codec_dai = rtd->dai->codec_dai; + struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai; + int ret; + + /* WM8731 has its own 12MHz crystal */ + snd_soc_dai_set_sysclk(codec_dai, WM8731_SYSCLK, + 12000000, SND_SOC_CLOCK_IN); + + /* codec is bitclock and lrclk master */ + ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_LEFT_J | + SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBM_CFM); + if (ret < 0) + goto out; + + ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_LEFT_J | + SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBM_CFM); + if (ret < 0) + goto out; + + ret = 0; +out: + return ret; +} + +static struct snd_soc_ops db1200_i2s_wm8731_ops = { + .startup = db1200_i2s_startup, +}; + +static struct snd_soc_dai_link db1200_i2s_dai = { + .name = "WM8731", + .stream_name = "WM8731 PCM", + .cpu_dai = &au1xpsc_i2s_dai, + .codec_dai = &wm8731_dai, + .ops = &db1200_i2s_wm8731_ops, +}; + +static struct snd_soc_card db1200_i2s_machine = { + .name = "DB1200_I2S", + .dai_link = &db1200_i2s_dai, + .num_links = 1, + .platform = &au1xpsc_soc_platform, +}; + +static struct snd_soc_device db1200_i2s_devdata = { + .card = &db1200_i2s_machine, + .codec_dev = &soc_codec_dev_wm8731, +}; + +/*------------------------- COMMON PART ---------------------------*/ + +static struct platform_device *db1200_asoc_dev; + +static int __init db1200_audio_load(void) +{ + int ret; + + ret = -ENOMEM; + db1200_asoc_dev = platform_device_alloc("soc-audio", -1); + if (!db1200_asoc_dev) + goto out; + + /* DB1200 board setup set PSC1MUX to preferred audio device */ + if (bcsr_read(BCSR_RESETS) & BCSR_RESETS_PSC1MUX) + platform_set_drvdata(db1200_asoc_dev, &db1200_i2s_devdata); + else + platform_set_drvdata(db1200_asoc_dev, &db1200_ac97_devdata); + + db1200_ac97_devdata.dev = &db1200_asoc_dev->dev; + db1200_i2s_devdata.dev = &db1200_asoc_dev->dev; + ret = platform_device_add(db1200_asoc_dev); + + if (ret) { + platform_device_put(db1200_asoc_dev); + db1200_asoc_dev = NULL; + } +out: + return ret; +} + +static void __exit db1200_audio_unload(void) +{ + platform_device_unregister(db1200_asoc_dev); +} + +module_init(db1200_audio_load); +module_exit(db1200_audio_unload); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("DB1200 ASoC audio support"); +MODULE_AUTHOR("Manuel Lauss"); diff --git a/sound/soc/au1x/sample-ac97.c b/sound/soc/au1x/sample-ac97.c deleted file mode 100644 index 27683eb..0000000 --- a/sound/soc/au1x/sample-ac97.c +++ /dev/null @@ -1,144 +0,0 @@ -/* - * Sample Au12x0/Au1550 PSC AC97 sound machine. - * - * Copyright (c) 2007-2008 Manuel Lauss - * - * This program is free software; you can redistribute it and/or modify - * it under the terms outlined in the file COPYING at the root of this - * source archive. - * - * This is a very generic AC97 sound machine driver for boards which - * have (AC97) audio at PSC1 (e.g. DB1200 demoboards). - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "../codecs/ac97.h" -#include "psc.h" - -static int au1xpsc_sample_ac97_init(struct snd_soc_codec *codec) -{ - snd_soc_dapm_sync(codec); - return 0; -} - -static struct snd_soc_dai_link au1xpsc_sample_ac97_dai = { - .name = "AC97", - .stream_name = "AC97 HiFi", - .cpu_dai = &au1xpsc_ac97_dai, /* see psc-ac97.c */ - .codec_dai = &ac97_dai, /* see codecs/ac97.c */ - .init = au1xpsc_sample_ac97_init, - .ops = NULL, -}; - -static struct snd_soc_card au1xpsc_sample_ac97_machine = { - .name = "Au1xxx PSC AC97 Audio", - .dai_link = &au1xpsc_sample_ac97_dai, - .num_links = 1, -}; - -static struct snd_soc_device au1xpsc_sample_ac97_devdata = { - .card = &au1xpsc_sample_ac97_machine, - .platform = &au1xpsc_soc_platform, /* see dbdma2.c */ - .codec_dev = &soc_codec_dev_ac97, -}; - -static struct resource au1xpsc_psc1_res[] = { - [0] = { - .start = CPHYSADDR(PSC1_BASE_ADDR), - .end = CPHYSADDR(PSC1_BASE_ADDR) + 0x000fffff, - .flags = IORESOURCE_MEM, - }, - [1] = { -#ifdef CONFIG_SOC_AU1200 - .start = AU1200_PSC1_INT, - .end = AU1200_PSC1_INT, -#elif defined(CONFIG_SOC_AU1550) - .start = AU1550_PSC1_INT, - .end = AU1550_PSC1_INT, -#endif - .flags = IORESOURCE_IRQ, - }, - [2] = { - .start = DSCR_CMD0_PSC1_TX, - .end = DSCR_CMD0_PSC1_TX, - .flags = IORESOURCE_DMA, - }, - [3] = { - .start = DSCR_CMD0_PSC1_RX, - .end = DSCR_CMD0_PSC1_RX, - .flags = IORESOURCE_DMA, - }, -}; - -static struct platform_device *au1xpsc_sample_ac97_dev; - -static int __init au1xpsc_sample_ac97_load(void) -{ - int ret; - -#ifdef CONFIG_SOC_AU1200 - unsigned long io; - - /* modify sys_pinfunc for AC97 on PSC1 */ - io = au_readl(SYS_PINFUNC); - io |= SYS_PINFUNC_P1C; - io &= ~(SYS_PINFUNC_P1A | SYS_PINFUNC_P1B); - au_writel(io, SYS_PINFUNC); - au_sync(); -#endif - - ret = -ENOMEM; - - /* setup PSC clock source for AC97 part: external clock provided - * by codec. The psc-ac97.c driver depends on this setting! - */ - au_writel(PSC_SEL_CLK_SERCLK, PSC1_BASE_ADDR + PSC_SEL_OFFSET); - au_sync(); - - au1xpsc_sample_ac97_dev = platform_device_alloc("soc-audio", -1); - if (!au1xpsc_sample_ac97_dev) - goto out; - - au1xpsc_sample_ac97_dev->resource = - kmemdup(au1xpsc_psc1_res, sizeof(struct resource) * - ARRAY_SIZE(au1xpsc_psc1_res), GFP_KERNEL); - au1xpsc_sample_ac97_dev->num_resources = ARRAY_SIZE(au1xpsc_psc1_res); - au1xpsc_sample_ac97_dev->id = 1; - - platform_set_drvdata(au1xpsc_sample_ac97_dev, - &au1xpsc_sample_ac97_devdata); - au1xpsc_sample_ac97_devdata.dev = &au1xpsc_sample_ac97_dev->dev; - ret = platform_device_add(au1xpsc_sample_ac97_dev); - - if (ret) { - platform_device_put(au1xpsc_sample_ac97_dev); - au1xpsc_sample_ac97_dev = NULL; - } - -out: - return ret; -} - -static void __exit au1xpsc_sample_ac97_exit(void) -{ - platform_device_unregister(au1xpsc_sample_ac97_dev); -} - -module_init(au1xpsc_sample_ac97_load); -module_exit(au1xpsc_sample_ac97_exit); - -MODULE_LICENSE("GPL"); -MODULE_DESCRIPTION("Au1xxx PSC sample AC97 machine"); -MODULE_AUTHOR("Manuel Lauss "); -- 1.6.5.1 From fweisbec@gmail.com Mon Nov 2 22:44:02 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 02 Nov 2009 22:44:09 +0100 (CET) Received: from mail-ew0-f214.google.com ([209.85.219.214]:56555 "EHLO mail-ew0-f214.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1493403AbZKBVoC (ORCPT ); Mon, 2 Nov 2009 22:44:02 +0100 Received: by ewy10 with SMTP id 10so6183175ewy.33 for ; Mon, 02 Nov 2009 13:43:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:received:date:from:to:cc :subject:message-id:references:mime-version:content-type :content-disposition:in-reply-to:user-agent; bh=OgCrKQYn9/oybKjIMgyo8odG+anVCej79+JUffsvlBk=; b=WFwEfg4GHRtMUYjC2sL4T4UY3ksu9WYWylAGb17GOoPRvNwxoPVEgIp6fT5PfxeqYQ CBkEoHfvaryaLaig6sYhFR/zzzZ5kiOL9jrZxQjY0knyaR5Yz8PqNBmY0bVw8pwX83VF BO3dgKvSmcr8jMGwOcm9eLRRcXQ2JYnamaZx4= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=date:from:to:cc:subject:message-id:references:mime-version :content-type:content-disposition:in-reply-to:user-agent; b=F6wh4sZinmOFvy2YheS+kAVAzANDnMjvIFqg10SQatyZDqepDolyEHYTCCY8efeG7d GqQfspsrpK+biSmcbcm0Sf5amsIJq08/i+rzoFaah8/ViTMi7dFXnu6VGIEVQh0EGjPp kL3OVI476Xboa19AjxzX2zHkfJ3D1orJOd3ls= Received: by 10.216.85.197 with SMTP id u47mr5329765wee.133.1257198235670; Mon, 02 Nov 2009 13:43:55 -0800 (PST) Received: from nowhere (ADijon-552-1-8-120.w92-138.abo.wanadoo.fr [92.138.147.120]) by mx.google.com with ESMTPS id 23sm9161166eya.44.2009.11.02.13.43.51 (version=SSLv3 cipher=RC4-MD5); Mon, 02 Nov 2009 13:43:53 -0800 (PST) Received: by nowhere (nbSMTP-1.00) for uid 1000 (using TLSv1/SSLv3 with cipher RC4-MD5 (128/128 bits)) fweisbec@gmail.com; Mon, 2 Nov 2009 22:43:56 +0100 (CET) Date: Mon, 2 Nov 2009 22:43:55 +0100 From: Frederic Weisbecker To: Wu Zhangjin Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, rostedt@goodmis.org, Thomas Gleixner , Ralf Baechle , Nicholas Mc Guire , Richard Sandiford , David Daney , Adam Nemet , Patrik Kluba Subject: Re: [PATCH -v5 08/11] tracing: not trace mips_timecounter_init() in MIPS Message-ID: <20091102214351.GI4880@nowhere> References: <2f73eae542c47ac5bbb9f7280e6c0271d193e90d.1256483735.git.wuzhangjin@gmail.com> <3e0c2d7d8b8f196a8153beb41ea7f3cbf42b3d84.1256483735.git.wuzhangjin@gmail.com> <54c417629e91f40b2bbb4e08cda2a4e6527824c0.1256483735.git.wuzhangjin@gmail.com> <29bccff04932e993ecd9f516d8b6dcf84e2ceecf.1256483735.git.wuzhangjin@gmail.com> <72f2270f7b6e01ca7a4cdf4ac8c21778e5d9652f.1256483735.git.wuzhangjin@gmail.com> <6140dd8f4e1783e5ac30977cf008bb98e4698322.1256483735.git.wuzhangjin@gmail.com> <49b3c441a57f4db423732f81432a3450ccb3240e.1256483735.git.wuzhangjin@gmail.com> <1256550156.5642.148.camel@falcon> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1256550156.5642.148.camel@falcon> User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24622 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: fweisbec@gmail.com Precedence: bulk X-list: linux-mips On Mon, Oct 26, 2009 at 05:42:36PM +0800, Wu Zhangjin wrote: > On Mon, 2009-10-26 at 01:27 +0100, Frederic Weisbecker wrote: > > 2009/10/25 Wu Zhangjin : > > > -static inline u64 mips_timecounter_read(void) > > > +static inline u64 notrace mips_timecounter_read(void) > > > > > > You don't need to set notrace functions, unless their addresses > > are referenced somewhere, which unfortunately might happen > > for some functions but this is rare. > > > > Okay, Will remove it. Oops, a word has escaped from my above sentence. I wanted to say: "You don't need to set notrace to inline functions" :) > > Hmm yeah this is not very nice to do that in core functions because > > of a specific arch problem. > > At least you have __notrace_funcgraph, this is a notrace > > that only applies if CONFIG_FUNCTION_GRAPH_TRACER > > so that it's still traceable by the function tracer in this case. > > > > But I would rather see a __mips_notrace on these two core functions. > > What about this: __arch_notrace? If the arch need this, define it, > otherwise, ignore it! if only graph tracer need it, define it in "#ifdef > CONFIG_FUNCTION_GRAPH_TRACER ... #endif". The problem is that archs may want to disable tracing on different places. For example mips wants to disable tracing in timecounter_read_delta, but another arch may want to disable tracing somewhere else. We'll then have several unrelated __arch_notrace. One that is relevant for mips, another that is relevant for arch_foo, but all of them will apply for all arch that have defined a __arch_notrace. It's true that __mips_notrace is not very elegant as it looks like a specific arch annotation intruder. But at least that gives us a per arch filter granularity. If only static ftrace could disappear, we could keep only dynamic ftrace and we would then be able to filter dynamically. But I'm not sure it's a good idea for archs integration. From wilbur512@gmail.com Tue Nov 3 00:33:51 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 03 Nov 2009 00:33:57 +0100 (CET) Received: from mail-yx0-f204.google.com ([209.85.210.204]:56514 "EHLO mail-yx0-f204.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1493440AbZKBXdv (ORCPT ); Tue, 3 Nov 2009 00:33:51 +0100 Received: by yxe42 with SMTP id 42so5603010yxe.22 for ; Mon, 02 Nov 2009 15:33:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:date:message-id:subject :from:to:content-type; bh=7F6twuMJaeisfHuSsK6bW6lGzxJK1QbCvHP4/4cALZU=; b=qIpcee11Zw9Gj/S4BCg3aAxnEQ2oMcbf1Yk1uNDAae+l5j8E+KRfhyefziBhlgRh/D 2GveKk3uJHoU8Pte+NIZnK2SlmRJpxJLaWJuAMnnHLidZrbqiTSW9S92eIovS2Xq991R Ql3s0B9LtrqCfP4DQKmeU7uQPDuOwOQc90LHM= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:date:message-id:subject:from:to:content-type; b=ZSPG0ZwSs61dmq6SSzJbThO4bj45mdcnI+dQNXTOxtFMPfhMuJHcv+SypNFxalDt6q QMrPDl2ZTY7vtlH7bb9aVKR7s1QReMuZSxh6h9LLERZomxZxsMadhaJWCicgb8hr7zVL 4zsLCfYjpADGzNyESxc8nnSeGJFC1PNUHCjjU= MIME-Version: 1.0 Received: by 10.90.62.4 with SMTP id k4mr1896548aga.56.1257204824420; Mon, 02 Nov 2009 15:33:44 -0800 (PST) Date: Tue, 3 Nov 2009 07:33:44 +0800 Message-ID: Subject: mips64 smp kexec failed booting at timer interrupt From: "wilbur.chan" To: kexec@lists.infradead.org, Linux MIPS Mailing List Content-Type: text/plain; charset=ISO-8859-1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24623 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wilbur512@gmail.com Precedence: bulk X-list: linux-mips I ' m using kexec on a mips64 smp board. http://lists.infradead.org/pipermail/kexec/2008-June/001909.html By now , the second kernel has halt at start_kernel --> calibrate_delay, and I found that it was because of jiffies was not changing. So it might be the failure of installation for timer interrupt , or timer interrupt did not trigger. Before jumped into second kernel, local_irq_disable was called at each CPU , and only one of CPU was enable to jump into second kernel, while the others loop at relocate_kernel all the time. After I got dump_stack log of the firts kernel, I found that, do_timer was invoked right after console_init -->release_console_sem , it seemed that , timer interrupt would be triggered by release_console_sem . here is the dump_stack info of do_timer of first kernel: 0:Call Trace: 0:[ <834243cc>]0: dump_stack+0x8/0x34 0:[ <83451ee0>]0: do_timer+0x70/0xa8 0:[ <8342333c>]0: timer_interrupt+0x64/0x160 0:[ <834234b4>]0: ll_timer_interrupt+0x7c/0xd8 0:[ <8341d220>]0: ret_from_irq+0x0/0x4 0:[ <83443a64>]0: release_console_sem+0x1e0/0x328 0:[ <8377cf88>]0: serial8250_console_init+0x1c/0x2c 0:[ <8377ae58>]0: console_init+0x4c/0x6c 0:[ <83762dd8>]0: start_kernel+0x3e0/0x75c Any one know how to fix it? or how to enable the timer interrupt in second kernel? Thx From myuboot@fastmail.fm Tue Nov 3 00:54:11 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 03 Nov 2009 00:54:17 +0100 (CET) Received: from out4.smtp.messagingengine.com ([66.111.4.28]:50879 "EHLO out4.smtp.messagingengine.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1493961AbZKBXyL (ORCPT ); Tue, 3 Nov 2009 00:54:11 +0100 Received: from compute1.internal (compute1.internal [10.202.2.41]) by gateway1.messagingengine.com (Postfix) with ESMTP id 652D4BE49D; Mon, 2 Nov 2009 18:54:09 -0500 (EST) Received: from web8.messagingengine.com ([10.202.2.217]) by compute1.internal (MEProxy); Mon, 02 Nov 2009 18:54:09 -0500 DKIM-Signature: v=1; a=rsa-sha1; c=relaxed/relaxed; d=messagingengine.com; h=message-id:from:to:cc:mime-version:content-transfer-encoding:content-type:in-reply-to:references:subject:date; s=smtpout; bh=3fA6qLwogNQIr5/OdupuPfyakQk=; b=aC91UXON69tfLkkFFIN6Nbdf7trptqTpi2AAyG+4oWdU38Iil6I68A7GtbINwbl2J1bgbJwY6goAaIctJtpeXSfN0CgP4tlxjQ1asCGoQyeDt6ex4qKyOEs7ABL5976rBH+2cTCZZ9Rly/u6ZZi7XxqMeDmAlIrpplEBz1J2zhQ= Received: by web8.messagingengine.com (Postfix, from userid 99) id 2B50D16666; Mon, 2 Nov 2009 18:54:09 -0500 (EST) Message-Id: <1257206049.25795.1343240289@webmail.messagingengine.com> X-Sasl-Enc: X/hn4I7LZwVTOOyezzJ0exHVb2NtTGq6VqE9625qpp7R 1257206049 From: myuboot@fastmail.fm To: "Shmulik Ladkani" Cc: "Sergei Shtylyov" , "Florian Fainelli" , linux-kernel@vger.kernel.org, "linux-mips" , shmulik@jungo.com MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii" X-Mailer: MessagingEngine.com Webmail Interface In-Reply-To: <20091029102652.76d42b8c@pixies.home.jungo.com> References: <1255735395.30097.1340523469@webmail.messagingengine.com><4AD906D8.3020404@caviumnetworks.com><1255996564.10560.1340920621@webmail.messagingengine.com><200910200817.24018.florian@openwrt.org><1256676013.24305.1342273367@webmail.messagingengine.com><20091028103551.0b4052d8@pixies.home.jungo.com><4AE82520.4090607@ru.mvista.com><1256758575.4093.1342456105@webmail.messagingengine.com> <20091029102652.76d42b8c@pixies.home.jungo.com> Subject: Re: serial port 8250 messed up after coverting from little endian to big endian on kernel 2.6.31 Date: Mon, 02 Nov 2009 17:54:09 -0600 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24624 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: myuboot@fastmail.fm Precedence: bulk X-list: linux-mips The CONFIG_SWAP_IO_SPACE was set to Y, but I don't even see it using xconfig or menuconfig. So I set it manually to n into .config file and then did a compile - I am using buildroot. But somehow the value always comes back to y after I type in command "make". The kernel image still messes up the console after the console is handovered from early printk to really ttyS01. Thanks. On Thu, 29 Oct 2009 10:26 +0200, "Shmulik Ladkani" wrote: > On Wed, 28 Oct 2009 14:36:15 -0500 myuboot@fastmail.fm wrote: > > I just tried UPIO_MEM32 without adding a offset of 3. But the result is > > bad - after the kernel initializes the serial console, the console print > > out messes up. The early printk is fine because the u-boot initialises > > the serial port fine. > > > > Did I miss anything? Thanks again for your help. > > I guess you did fine with UPIO_MEM32. > > Keeping the UPIO_MEM32 approach, I suggest also to fiddle Y/N with > CONFIG_SWAP_IO_SPACE (might be that you have it set to Y while you don't > really need it, or vice versa). > This is since 'readl' uses 'ioswabl' for (potential) byte-swapping of the > read > value. Take a look at asm/io.h and mangle-port.h. > > Most important, read your hardware documentation to determine correct > access > to the memory mapped serial registers. > > -- > Shmulik Ladkani Jungo Ltd. From David.Daney@caviumnetworks.com Tue Nov 3 01:17:55 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 03 Nov 2009 01:18:02 +0100 (CET) Received: from mail3.caviumnetworks.com ([12.108.191.235]:10797 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1493951AbZKCARz (ORCPT ); Tue, 3 Nov 2009 01:17:55 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,5,4,7535) id ; Mon, 02 Nov 2009 16:13:22 -0800 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Mon, 2 Nov 2009 16:12:43 -0800 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Mon, 2 Nov 2009 16:12:43 -0800 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.2/8.14.2) with ESMTP id nA30Ccwk014543; Mon, 2 Nov 2009 16:12:38 -0800 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.2/8.14.2/Submit) id nA30CZrg014541; Mon, 2 Nov 2009 16:12:35 -0800 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: David Daney Subject: [PATCH] MIPS: Make collection of FPU emulator statistics optional. Date: Mon, 2 Nov 2009 16:12:35 -0800 Message-Id: <1257207155-14517-1-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.6.0.6 X-OriginalArrivalTime: 03 Nov 2009 00:12:43.0269 (UTC) FILETIME=[5D005B50:01CA5C1A] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24625 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips On SMP systems, the collection of statistics can cause cache line bouncing in the lines associated with the counters. Make the statistics configurable so this can be avoided. Also we need to make the counters atomic_t so that they can be reliably modified on SMP systems. Signed-off-by: David Daney --- arch/mips/Kconfig | 13 +++++++ arch/mips/include/asm/fpu_emulator.h | 23 +++++++++--- arch/mips/math-emu/cp1emu.c | 66 ++++++++++++++++++++------------- arch/mips/math-emu/dsemul.c | 4 +- 4 files changed, 72 insertions(+), 34 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index a4aea20..804e664 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -2030,6 +2030,19 @@ config SECCOMP If unsure, say Y. Only embedded should say N here. +config MIPS_FPU_EMULATOR_STATS + bool "Enable FPU emulator statistics" + depends on DEBUG_FS + default n + help + The FPU emulator can collect statistics about how many times + it has been invoked. On SMP systems making heavy use of the + emulator, the overhead of keeping the statistics may be + large. The statistics may be read from the files in + /sys/kernel/debug/mips/fpuemustats. + + If unsure, say N. + endmenu config LOCKDEP_SUPPORT diff --git a/arch/mips/include/asm/fpu_emulator.h b/arch/mips/include/asm/fpu_emulator.h index e518957..bbe2849 100644 --- a/arch/mips/include/asm/fpu_emulator.h +++ b/arch/mips/include/asm/fpu_emulator.h @@ -25,18 +25,29 @@ #include #include +#include struct mips_fpu_emulator_stats { - unsigned int emulated; - unsigned int loads; - unsigned int stores; - unsigned int cp1ops; - unsigned int cp1xops; - unsigned int errors; + atomic_t emulated; + atomic_t loads; + atomic_t stores; + atomic_t cp1ops; + atomic_t cp1xops; + atomic_t errors; }; +#ifdef CONFIG_MIPS_FPU_EMULATOR_STATS + extern struct mips_fpu_emulator_stats fpuemustats; +#define MIPS_FPU_EMU_INC_STATS(M) atomic_inc(&fpuemustats.M) + +#else + +#define MIPS_FPU_EMU_INC_STATS(M) do { } while (0) + +#endif + extern int mips_dsemul(struct pt_regs *regs, mips_instruction ir, unsigned long cpc); extern int do_dsemulret(struct pt_regs *xcp); diff --git a/arch/mips/math-emu/cp1emu.c b/arch/mips/math-emu/cp1emu.c index 454b539..46e12af 100644 --- a/arch/mips/math-emu/cp1emu.c +++ b/arch/mips/math-emu/cp1emu.c @@ -35,6 +35,7 @@ * better performance by compiling with -msoft-float! */ #include +#include #include #include @@ -68,7 +69,9 @@ static int fpux_emu(struct pt_regs *, /* Further private data for which no space exists in mips_fpu_struct */ +#ifdef CONFIG_MIPS_FPU_EMULATOR_STATS struct mips_fpu_emulator_stats fpuemustats; +#endif /* Control registers */ @@ -209,7 +212,7 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx) unsigned int cond; if (get_user(ir, (mips_instruction __user *) xcp->cp0_epc)) { - fpuemustats.errors++; + MIPS_FPU_EMU_INC_STATS(errors); return SIGBUS; } @@ -240,7 +243,7 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx) return SIGILL; } if (get_user(ir, (mips_instruction __user *) emulpc)) { - fpuemustats.errors++; + MIPS_FPU_EMU_INC_STATS(errors); return SIGBUS; } /* __compute_return_epc() will have updated cp0_epc */ @@ -253,16 +256,16 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx) } emul: - fpuemustats.emulated++; + MIPS_FPU_EMU_INC_STATS(emulated); switch (MIPSInst_OPCODE(ir)) { case ldc1_op:{ u64 __user *va = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] + MIPSInst_SIMM(ir)); u64 val; - fpuemustats.loads++; + MIPS_FPU_EMU_INC_STATS(loads); if (get_user(val, va)) { - fpuemustats.errors++; + MIPS_FPU_EMU_INC_STATS(errors); return SIGBUS; } DITOREG(val, MIPSInst_RT(ir)); @@ -274,10 +277,10 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx) MIPSInst_SIMM(ir)); u64 val; - fpuemustats.stores++; + MIPS_FPU_EMU_INC_STATS(stores); DIFROMREG(val, MIPSInst_RT(ir)); if (put_user(val, va)) { - fpuemustats.errors++; + MIPS_FPU_EMU_INC_STATS(errors); return SIGBUS; } break; @@ -288,9 +291,9 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx) MIPSInst_SIMM(ir)); u32 val; - fpuemustats.loads++; + MIPS_FPU_EMU_INC_STATS(loads); if (get_user(val, va)) { - fpuemustats.errors++; + MIPS_FPU_EMU_INC_STATS(errors); return SIGBUS; } SITOREG(val, MIPSInst_RT(ir)); @@ -302,10 +305,10 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx) MIPSInst_SIMM(ir)); u32 val; - fpuemustats.stores++; + MIPS_FPU_EMU_INC_STATS(stores); SIFROMREG(val, MIPSInst_RT(ir)); if (put_user(val, va)) { - fpuemustats.errors++; + MIPS_FPU_EMU_INC_STATS(errors); return SIGBUS; } break; @@ -429,7 +432,7 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx) if (get_user(ir, (mips_instruction __user *) xcp->cp0_epc)) { - fpuemustats.errors++; + MIPS_FPU_EMU_INC_STATS(errors); return SIGBUS; } @@ -595,7 +598,7 @@ static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx, { unsigned rcsr = 0; /* resulting csr */ - fpuemustats.cp1xops++; + MIPS_FPU_EMU_INC_STATS(cp1xops); switch (MIPSInst_FMA_FFMT(ir)) { case s_fmt:{ /* 0 */ @@ -610,9 +613,9 @@ static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx, va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + xcp->regs[MIPSInst_FT(ir)]); - fpuemustats.loads++; + MIPS_FPU_EMU_INC_STATS(loads); if (get_user(val, va)) { - fpuemustats.errors++; + MIPS_FPU_EMU_INC_STATS(errors); return SIGBUS; } SITOREG(val, MIPSInst_FD(ir)); @@ -622,11 +625,11 @@ static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx, va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + xcp->regs[MIPSInst_FT(ir)]); - fpuemustats.stores++; + MIPS_FPU_EMU_INC_STATS(stores); SIFROMREG(val, MIPSInst_FS(ir)); if (put_user(val, va)) { - fpuemustats.errors++; + MIPS_FPU_EMU_INC_STATS(errors); return SIGBUS; } break; @@ -687,9 +690,9 @@ static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx, va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + xcp->regs[MIPSInst_FT(ir)]); - fpuemustats.loads++; + MIPS_FPU_EMU_INC_STATS(loads); if (get_user(val, va)) { - fpuemustats.errors++; + MIPS_FPU_EMU_INC_STATS(errors); return SIGBUS; } DITOREG(val, MIPSInst_FD(ir)); @@ -699,10 +702,10 @@ static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx, va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + xcp->regs[MIPSInst_FT(ir)]); - fpuemustats.stores++; + MIPS_FPU_EMU_INC_STATS(stores); DIFROMREG(val, MIPSInst_FS(ir)); if (put_user(val, va)) { - fpuemustats.errors++; + MIPS_FPU_EMU_INC_STATS(errors); return SIGBUS; } break; @@ -769,7 +772,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx, #endif } rv; /* resulting value */ - fpuemustats.cp1ops++; + MIPS_FPU_EMU_INC_STATS(cp1ops); switch (rfmt = (MIPSInst_FFMT(ir) & 0xf)) { case s_fmt:{ /* 0 */ union { @@ -1240,7 +1243,7 @@ int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx, prevepc = xcp->cp0_epc; if (get_user(insn, (mips_instruction __user *) xcp->cp0_epc)) { - fpuemustats.errors++; + MIPS_FPU_EMU_INC_STATS(errors); return SIGBUS; } if (insn == 0) @@ -1275,7 +1278,17 @@ int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx, return sig; } -#ifdef CONFIG_DEBUG_FS +#ifdef CONFIG_MIPS_FPU_EMULATOR_STATS + +static int fpuemu_atomic_t_get(void *data, u64 *val) +{ + *val = atomic_read((atomic_t *)data); + return 0; +} + +DEFINE_SIMPLE_ATTRIBUTE(fops_fpuemu_atomic_t_ro, + fpuemu_atomic_t_get, NULL, "%llu\n"); + extern struct dentry *mips_debugfs_dir; static int __init debugfs_fpuemu(void) { @@ -1283,7 +1296,7 @@ static int __init debugfs_fpuemu(void) int i; static struct { const char *name; - unsigned int *v; + atomic_t *v; } vars[] __initdata = { { "emulated", &fpuemustats.emulated }, { "loads", &fpuemustats.loads }, @@ -1299,7 +1312,8 @@ static int __init debugfs_fpuemu(void) if (!dir) return -ENOMEM; for (i = 0; i < ARRAY_SIZE(vars); i++) { - d = debugfs_create_u32(vars[i].name, S_IRUGO, dir, vars[i].v); + d = debugfs_create_file(vars[i].name, S_IRUGO, dir, vars[i].v, + &fops_fpuemu_atomic_t_ro); if (!d) return -ENOMEM; } diff --git a/arch/mips/math-emu/dsemul.c b/arch/mips/math-emu/dsemul.c index df7b9d9..36d975a 100644 --- a/arch/mips/math-emu/dsemul.c +++ b/arch/mips/math-emu/dsemul.c @@ -98,7 +98,7 @@ int mips_dsemul(struct pt_regs *regs, mips_instruction ir, unsigned long cpc) err |= __put_user(cpc, &fr->epc); if (unlikely(err)) { - fpuemustats.errors++; + MIPS_FPU_EMU_INC_STATS(errors); return SIGBUS; } @@ -136,7 +136,7 @@ int do_dsemulret(struct pt_regs *xcp) err |= __get_user(cookie, &fr->cookie); if (unlikely(err || (insn != BREAK_MATH) || (cookie != BD_COOKIE))) { - fpuemustats.errors++; + MIPS_FPU_EMU_INC_STATS(errors); return 0; } -- 1.6.0.6 From wuzhangjin@gmail.com Tue Nov 3 02:21:11 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 03 Nov 2009 02:21:17 +0100 (CET) Received: from mail-yw0-f173.google.com ([209.85.211.173]:38813 "EHLO mail-yw0-f173.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1493982AbZKCBVL (ORCPT ); Tue, 3 Nov 2009 02:21:11 +0100 Received: by ywh3 with SMTP id 3so5662464ywh.22 for ; Mon, 02 Nov 2009 17:21:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:subject:from:reply-to:to:cc :in-reply-to:references:content-type:organization:date:message-id :mime-version:x-mailer:content-transfer-encoding; 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([222.92.8.142]) by mx.google.com with ESMTPS id 34sm2775485yxf.29.2009.11.02.17.20.58 (version=TLSv1/SSLv3 cipher=RC4-MD5); Mon, 02 Nov 2009 17:21:03 -0800 (PST) Subject: Re: [PATCH -queue 2/7] [loongson] mem.c: Register reserved memory pages From: Wu Zhangjin Reply-To: wuzhangjin@gmail.com To: Ralf Baechle Cc: Linux-MIPS , yanh@lemote.com, huhb@lemote.com, Zhang Le , zhangfx@lemote.com In-Reply-To: <20091102141459.GG21563@linux-mips.org> References: <20091102141459.GG21563@linux-mips.org> Content-Type: text/plain; charset="UTF-8" Organization: DSLab, Lanzhou University, China Date: Tue, 03 Nov 2009 09:21:05 +0800 Message-ID: <1257211265.3528.17.camel@falcon.domain.org> Mime-Version: 1.0 X-Mailer: Evolution 2.28.1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24626 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips On Mon, 2009-11-02 at 15:14 +0100, Ralf Baechle wrote: > On Fri, Oct 16, 2009 at 02:17:15PM +0800, Wu Zhangjin wrote: > > > This patch registers the reserved pages for loongson family machines. > > Hmm... After our recent discussion on your hibernation issues I am > wondering if this patch is actually still required or useful? It does not help the hibernation issue, but helps to clear the memory layout to the users(cat /proc/iomem), is this a need? Seems some of the other architectures, including some MIPS variants have registed the reserved space, so, could you please apply it? Thanks & Regards, Wu Zhangjin From wuzhangjin@gmail.com Tue Nov 3 02:34:31 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 03 Nov 2009 02:34:37 +0100 (CET) Received: from mail-yw0-f173.google.com ([209.85.211.173]:55698 "EHLO mail-yw0-f173.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1493988AbZKCBea (ORCPT ); Tue, 3 Nov 2009 02:34:30 +0100 Received: by ywh3 with SMTP id 3so5671634ywh.22 for ; Mon, 02 Nov 2009 17:34:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:subject:from:reply-to:to:cc :in-reply-to:references:content-type:organization:date:message-id :mime-version:x-mailer:content-transfer-encoding; bh=VTjuaelzKNhTSnmPbqbzgjbKBfDrQkNEYVgHu4u4oKo=; b=X2EQDShms7onFZCf5ecCYk1rfNHWR1jp+eKSqS1J56w29IUB4xJlTAPuExX6cRkO4f REkj1aOT1mUUynKiCQKf+26MLL3Izw4vm4wrlCZgRIAmmCfAuSumaNWBzZckTvuAni6A V9+s57jtP24gQG3Po+7CFoiTL2Dyq+sIJcWb0= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=subject:from:reply-to:to:cc:in-reply-to:references:content-type :organization:date:message-id:mime-version:x-mailer :content-transfer-encoding; b=TSjcCbXGOGyRkeDD3YAsrym5JhnFS1pJ96OWyZRQGj4smkXOS1dJYLioDgXHCZNtoD GSBMYIPsNf8pjYK9cNMkpWMXj6JOYdXV0x8vMGzV2Gss+i/MWJzPo05eBwzd+8JUf9FU sf17ooykN/OLqEF/HYNdy2Xtr+DAcMfjAHb60= Received: by 10.150.104.13 with SMTP id b13mr9380356ybc.17.1257212063834; Mon, 02 Nov 2009 17:34:23 -0800 (PST) Received: from ?172.16.2.101? ([222.92.8.142]) by mx.google.com with ESMTPS id 22sm2306120ywh.0.2009.11.02.17.34.18 (version=TLSv1/SSLv3 cipher=RC4-MD5); Mon, 02 Nov 2009 17:34:23 -0800 (PST) Subject: Re: [PATCH -v5 08/11] tracing: not trace mips_timecounter_init() in MIPS From: Wu Zhangjin Reply-To: wuzhangjin@gmail.com To: Frederic Weisbecker Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, rostedt@goodmis.org, Thomas Gleixner , Ralf Baechle , Nicholas Mc Guire , Richard Sandiford , David Daney , Adam Nemet , Patrik Kluba In-Reply-To: <20091102214351.GI4880@nowhere> References: <2f73eae542c47ac5bbb9f7280e6c0271d193e90d.1256483735.git.wuzhangjin@gmail.com> <3e0c2d7d8b8f196a8153beb41ea7f3cbf42b3d84.1256483735.git.wuzhangjin@gmail.com> <54c417629e91f40b2bbb4e08cda2a4e6527824c0.1256483735.git.wuzhangjin@gmail.com> <29bccff04932e993ecd9f516d8b6dcf84e2ceecf.1256483735.git.wuzhangjin@gmail.com> <72f2270f7b6e01ca7a4cdf4ac8c21778e5d9652f.1256483735.git.wuzhangjin@gmail.com> <6140dd8f4e1783e5ac30977cf008bb98e4698322.1256483735.git.wuzhangjin@gmail.com> <49b3c441a57f4db423732f81432a3450ccb3240e.1256483735.git.wuzhangjin@gmail.com> <1256550156.5642.148.camel@falcon> <20091102214351.GI4880@nowhere> Content-Type: text/plain; charset="UTF-8" Organization: DSLab, Lanzhou University, China Date: Tue, 03 Nov 2009 09:34:25 +0800 Message-ID: <1257212065.3528.28.camel@falcon.domain.org> Mime-Version: 1.0 X-Mailer: Evolution 2.28.1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24627 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips Hi, On Mon, 2009-11-02 at 22:43 +0100, Frederic Weisbecker wrote: [...] > > > > -static inline u64 mips_timecounter_read(void) > > > > +static inline u64 notrace mips_timecounter_read(void) > > > > > > > > > You don't need to set notrace functions, unless their addresses > > > are referenced somewhere, which unfortunately might happen > > > for some functions but this is rare. > > > > > > > Okay, Will remove it. > > > > Oops, a word has escaped from my above sentence. I wanted to say: > > "You don't need to set notrace to inline functions" :) > > Thanks ;) I have got your meaning at that time, and have removed them with inline functions. > > > But I would rather see a __mips_notrace on these two core functions. > > > > What about this: __arch_notrace? If the arch need this, define it, > > otherwise, ignore it! if only graph tracer need it, define it in "#ifdef > > CONFIG_FUNCTION_GRAPH_TRACER ... #endif". > > The problem is that archs may want to disable tracing on different > places. > For example mips wants to disable tracing in timecounter_read_delta, > but another arch may want to disable tracing somewhere else. > > We'll then have several unrelated __arch_notrace. One that is relevant > for mips, another that is relevant for arch_foo, but all of them will > apply for all arch that have defined a __arch_notrace. > > It's true that __mips_notrace is not very elegant as it looks like > a specific arch annotation intruder. > > But at least that gives us a per arch filter granularity. > > If only static ftrace could disappear, we could keep only dynamic > ftrace and we would then be able to filter dynamically. > But I'm not sure it's a good idea for archs integration. > Got it. Thanks & Regards, Wu Zhangjin From ralf@linux-mips.org Tue Nov 3 05:25:48 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 03 Nov 2009 05:25:53 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:59173 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-FAIL) by ftp.linux-mips.org with ESMTP id S1491894AbZKCEZs (ORCPT ); Tue, 3 Nov 2009 05:25:48 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id nA34RDqW015257; Tue, 3 Nov 2009 05:27:13 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id nA34RCOe015255; Tue, 3 Nov 2009 05:27:12 +0100 Date: Tue, 3 Nov 2009 05:27:12 +0100 From: Ralf Baechle To: David Daney Cc: linux-mips@linux-mips.org Subject: Re: [PATCH] MIPS: Emulate 64-bit FPU on 64-bit CPUs. Message-ID: <20091103042712.GA14423@linux-mips.org> References: <1257190426-29346-1-git-send-email-ddaney@caviumnetworks.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1257190426-29346-1-git-send-email-ddaney@caviumnetworks.com> User-Agent: Mutt/1.5.19 (2009-01-05) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24628 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Mon, Nov 02, 2009 at 11:33:46AM -0800, David Daney wrote: > Running a 64-bit kernel on a 64-bit CPU without an FPU would cause the > emulator to run in 32-bit mode. The c0_Status.FR bit is wired to zero > on systems without an FPU, so using that bit to decide how the > emulator behaves doesn't allow for proper emulation on 64-bit FPU-less > processors. > > Instead, we need to select the emulator mode based on the user-space > ABI. Since the thread flag TIF_32BIT_REGS is used to set > c0_Status.FR, we can just use it to decide if the emulator should be > in 32-bit or 64-bit mode. Thanks, applied! Ralf From ralf@linux-mips.org Tue Nov 3 10:36:22 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 03 Nov 2009 10:36:28 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:40477 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-FAIL) by ftp.linux-mips.org with ESMTP id S1492462AbZKCJgW (ORCPT ); Tue, 3 Nov 2009 10:36:22 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id nA39bjv4023602; Tue, 3 Nov 2009 10:37:46 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id nA39bhNF023600; Tue, 3 Nov 2009 10:37:43 +0100 Date: Tue, 3 Nov 2009 10:37:43 +0100 From: Ralf Baechle To: Thomas Bogendoerfer Cc: David Daney , linux-mips@linux-mips.org Subject: Re: [PATCH] MIPS: Make collection of FPU emulator statistics optional. Message-ID: <20091103093743.GA23235@linux-mips.org> References: <1257207155-14517-1-git-send-email-ddaney@caviumnetworks.com> <20091103093024.GA6425@alpha.franken.de> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20091103093024.GA6425@alpha.franken.de> User-Agent: Mutt/1.5.19 (2009-01-05) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24629 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Tue, Nov 03, 2009 at 10:30:24AM +0100, Thomas Bogendoerfer wrote: > On Mon, Nov 02, 2009 at 04:12:35PM -0800, David Daney wrote: > > On SMP systems, the collection of statistics can cause cache line > > bouncing in the lines associated with the counters. Make the > > statistics configurable so this can be avoided. Also we need to make > > the counters atomic_t so that they can be reliably modified on SMP > > systems. > > how about making it a per_cpu thing and avoid the atomic instructions ? Working on that. The tricky part is that statistics may end up somewhat inaccurate when a reader iterates over the per-CPU array of stats to add them all up. I've not found a solution for that yet but then again it should not be something which actually would cause pain. Ralf From ralf@linux-mips.org Tue Nov 3 11:19:47 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 03 Nov 2009 11:19:50 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:42984 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-FAIL) by ftp.linux-mips.org with ESMTP id S1492522AbZKCKTr (ORCPT ); Tue, 3 Nov 2009 11:19:47 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id nA3ALCRW024671; Tue, 3 Nov 2009 11:21:13 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id nA3ALCxw024669; Tue, 3 Nov 2009 11:21:12 +0100 Date: Tue, 3 Nov 2009 11:21:12 +0100 From: Ralf Baechle To: Thomas Bogendoerfer Cc: David Daney , linux-mips@linux-mips.org Subject: Re: [PATCH] MIPS: Make collection of FPU emulator statistics optional. Message-ID: <20091103102112.GA24619@linux-mips.org> References: <1257207155-14517-1-git-send-email-ddaney@caviumnetworks.com> <20091103093024.GA6425@alpha.franken.de> <20091103093743.GA23235@linux-mips.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20091103093743.GA23235@linux-mips.org> User-Agent: Mutt/1.5.19 (2009-01-05) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24630 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Tue, Nov 03, 2009 at 10:37:43AM +0100, Ralf Baechle wrote: > > On Mon, Nov 02, 2009 at 04:12:35PM -0800, David Daney wrote: > > > On SMP systems, the collection of statistics can cause cache line > > > bouncing in the lines associated with the counters. Make the > > > statistics configurable so this can be avoided. Also we need to make > > > the counters atomic_t so that they can be reliably modified on SMP > > > systems. > > > > how about making it a per_cpu thing and avoid the atomic instructions ? > > Working on that. The tricky part is that statistics may end up somewhat > inaccurate when a reader iterates over the per-CPU array of stats to add > them all up. I've not found a solution for that yet but then again it > should not be something which actually would cause pain. Or more useful than a global statistics would be per process stats. How should a useful interface look like? Ralf From broonie@opensource.wolfsonmicro.com Tue Nov 3 11:43:43 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 03 Nov 2009 11:43:50 +0100 (CET) Received: from opensource.wolfsonmicro.com ([80.75.67.52]:37497 "EHLO opensource2.wolfsonmicro.com" rhost-flags-OK-OK-OK-FAIL) by ftp.linux-mips.org with ESMTP id S1492640AbZKCKnn (ORCPT ); Tue, 3 Nov 2009 11:43:43 +0100 Received: by opensource2.wolfsonmicro.com (Postfix, from userid 1001) id 5DAB4769353; Tue, 3 Nov 2009 10:43:37 +0000 (GMT) Date: Tue, 3 Nov 2009 10:43:37 +0000 From: Mark Brown To: Manuel Lauss Cc: Linux-MIPS , Manuel Lauss , alsa-devel@alsa-project.org Subject: Re: [RFC PATCH 2/3] MIPS: Alchemy: DB1200 AC97+I2S audio support. Message-ID: <20091103104337.GA26068@opensource.wolfsonmicro.com> References: <1257193305-29996-1-git-send-email-manuel.lauss@gmail.com> <1257193305-29996-2-git-send-email-manuel.lauss@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1257193305-29996-2-git-send-email-manuel.lauss@gmail.com> X-Cookie: You are always busy. User-Agent: Mutt/1.5.17+20080114 (2008-01-14) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24631 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: broonie@opensource.wolfsonmicro.com Precedence: bulk X-list: linux-mips On Mon, Nov 02, 2009 at 09:21:44PM +0100, Manuel Lauss wrote: > Machine driver for DB1200 AC97 and I2S audio systems, intended as a > proper reference asoc machine for Alchemy-based systems. > AC97/I2S can be selected at boot time by setting switch S6.7 > > Cc: alsa-devel@alsa-project.org > Cc: Mark Brown > Signed-off-by: Manuel Lauss This looks good for me. The patch touches both ASoC and MIPS trees - I'm happy with it being merged though either. From manuel.lauss@googlemail.com Tue Nov 3 12:00:26 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 03 Nov 2009 12:00:32 +0100 (CET) Received: from mail-bw0-f221.google.com ([209.85.218.221]:46621 "EHLO mail-bw0-f221.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492488AbZKCLA0 convert rfc822-to-8bit (ORCPT ); Tue, 3 Nov 2009 12:00:26 +0100 Received: by bwz21 with SMTP id 21so7376491bwz.24 for ; Tue, 03 Nov 2009 03:00:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=domainkey-signature:mime-version:received:in-reply-to:references :date:message-id:subject:from:to:cc:content-type :content-transfer-encoding; bh=aumaoU3oI9QiklaCjaVx2Ydyf1j0792gr99oYvUrwqU=; b=WE8Amo11mwmn+ZCBGwqDcNHYKGnwF8zXqZOgb64iJMUYEy8tVqNWkW5GDST0rhnSYJ /m+nt2KrWtHjWaAFsXHH58Zz/+Y1aIwsHDeOEMp5Gd0YJOACVH8lp1sgTvrz2bineccb K5DhGwxymdfWf0pR/eVH/zkrB+Q2LFrVJ7drk= DomainKey-Signature: a=rsa-sha1; c=nofws; d=googlemail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type:content-transfer-encoding; b=Unja0W2u4ifhS5REKSCZd0VgvnPjO+OGWF5BKg/bXeSEJkHnWPBC53M0wLJMbq4/9x tsp3imuP2BnaZRtN4MD1rcIvVw3/9tID128pJ4T+RT4odfQ5RF5pwXavTw0EJPDOgTX6 kRiC/VcfBiOYAnBIZxYOeo7ULcIgtnG9p9j+4= MIME-Version: 1.0 Received: by 10.223.6.17 with SMTP id 17mr938223fax.93.1257246019789; Tue, 03 Nov 2009 03:00:19 -0800 (PST) In-Reply-To: <20091103104337.GA26068@opensource.wolfsonmicro.com> References: <1257193305-29996-1-git-send-email-manuel.lauss@gmail.com> <1257193305-29996-2-git-send-email-manuel.lauss@gmail.com> <20091103104337.GA26068@opensource.wolfsonmicro.com> Date: Tue, 3 Nov 2009 12:00:19 +0100 Message-ID: Subject: Re: [RFC PATCH 2/3] MIPS: Alchemy: DB1200 AC97+I2S audio support. From: Manuel Lauss To: Mark Brown Cc: Linux-MIPS , Manuel Lauss , alsa-devel@alsa-project.org Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24632 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips On Tue, Nov 3, 2009 at 11:43 AM, Mark Brown wrote: > On Mon, Nov 02, 2009 at 09:21:44PM +0100, Manuel Lauss wrote: >> Machine driver for DB1200 AC97 and I2S audio systems, intended as a >> proper reference asoc machine for Alchemy-based systems. >> AC97/I2S can be selected at boot time by setting switch S6.7 >> >> Cc: alsa-devel@alsa-project.org >> Cc: Mark Brown >> Signed-off-by: Manuel Lauss > > This looks good for me.  The patch touches both ASoC and MIPS trees - > I'm happy with it being merged though either. Thanks for having a look! I'd rather have it go through the MIPS tree, otherwise there's a higher chance of merge conflicts. Manuel Lauss From broonie@sirena.org.uk Tue Nov 3 12:13:34 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 03 Nov 2009 12:13:41 +0100 (CET) Received: from cassiel.sirena.org.uk ([80.68.93.111]:38938 "EHLO cassiel.sirena.org.uk" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492245AbZKCLNe (ORCPT ); Tue, 3 Nov 2009 12:13:34 +0100 Received: from broonie by cassiel.sirena.org.uk with local (Exim 4.69) (envelope-from ) id 1N5HKO-0007fs-68; Tue, 03 Nov 2009 11:13:32 +0000 Date: Tue, 3 Nov 2009 11:13:32 +0000 From: Mark Brown To: Manuel Lauss Cc: Linux-MIPS , alsa-devel@alsa-project.org, Manuel Lauss Subject: Re: [alsa-devel] [RFC PATCH 2/3] MIPS: Alchemy: DB1200 AC97+I2S audio support. Message-ID: <20091103111331.GA29431@sirena.org.uk> References: <1257193305-29996-1-git-send-email-manuel.lauss@gmail.com> <1257193305-29996-2-git-send-email-manuel.lauss@gmail.com> <20091103104337.GA26068@opensource.wolfsonmicro.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: X-Cookie: Your password is pitifully obvious. User-Agent: Mutt/1.5.18 (2008-05-17) X-SA-Exim-Connect-IP: X-SA-Exim-Mail-From: broonie@sirena.org.uk X-SA-Exim-Scanned: No (on cassiel.sirena.org.uk); SAEximRunCond expanded to false Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24633 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: broonie@opensource.wolfsonmicro.com Precedence: bulk X-list: linux-mips On Tue, Nov 03, 2009 at 12:00:19PM +0100, Manuel Lauss wrote: > On Tue, Nov 3, 2009 at 11:43 AM, Mark Brown > > This looks good for me. ?The patch touches both ASoC and MIPS trees - > > I'm happy with it being merged though either. > Thanks for having a look! I'd rather have it go through the MIPS tree, > otherwise there's a higher chance of merge conflicts. That's fine for me: Acked-by: Mark Brown and if there's any merge issues we can sort them out later. From ralf@linux-mips.org Tue Nov 3 13:17:12 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 03 Nov 2009 13:17:17 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:36731 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-FAIL) by ftp.linux-mips.org with ESMTP id S1492861AbZKCMRM (ORCPT ); Tue, 3 Nov 2009 13:17:12 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id nA3CIcnt027492 for ; Tue, 3 Nov 2009 13:18:39 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id nA3CIcM1027490 for linux-mips@linux-mips.org; Tue, 3 Nov 2009 13:18:38 +0100 Date: Tue, 3 Nov 2009 13:18:38 +0100 From: Ralf Baechle To: linux-mips@linux-mips.org Subject: addinitrd deletion Message-ID: <20091103121838.GA27403@linux-mips.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline User-Agent: Mutt/1.5.19 (2009-01-05) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24634 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Does anybody still see any use for addinitrd? If not I'm going to delete it. Ralf From linus.ml.walleij@gmail.com Tue Nov 3 14:51:50 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 03 Nov 2009 14:51:57 +0100 (CET) Received: from mail-bw0-f221.google.com ([209.85.218.221]:37270 "EHLO mail-bw0-f221.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492370AbZKCNvu convert rfc822-to-8bit (ORCPT ); Tue, 3 Nov 2009 14:51:50 +0100 Received: by bwz21 with SMTP id 21so7562525bwz.24 for ; Tue, 03 Nov 2009 05:51:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:in-reply-to:references :date:message-id:subject:from:to:cc:content-type :content-transfer-encoding; bh=8ZkPcMGP42Xcs+idWTxXEVBk47m+ARs72sG01biypAM=; b=q/hOeF4LjB+c8vhmPZe/HQ3S/gHYOgprKWj2IowIC0uzYk0+jAjQjJiYN9A1MG+Glm GeosKiyPb2dPWhz2k4+zVjGvhIIyCmmWCTvUALURMvHr2NVd80vap6C4gG+iNa00UUWU g3uFgof80SYyA6AcJ8ZXh7s6/5ry4heYZXKs4= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type:content-transfer-encoding; b=HdQ/i/EF2yJyeswXdZY+BWkHA0KjSITcy1iKKeFfv1peMR8P3JrYPRTO+G6qt4A7xA LK2nQDhVaR9n7BsGuavU/1CgT3PXSQDrdzBXWQt5Qd5Idxwmp0yXbRsBzWbzUsy3SRHk oEVf/Gkp5Ev/JwbTO3kI8p0W0se8X/OMq1Log= MIME-Version: 1.0 Received: by 10.204.32.16 with SMTP id a16mr4717249bkd.190.1257256301602; Tue, 03 Nov 2009 05:51:41 -0800 (PST) In-Reply-To: <63386a3d0910251518i42149642g183f2d3f6c43384f@mail.gmail.com> References: <1256078002-27919-1-git-send-email-linus.walleij@stericsson.com> <63386a3d0910251518i42149642g183f2d3f6c43384f@mail.gmail.com> Date: Tue, 3 Nov 2009 14:51:41 +0100 Message-ID: <63386a3d0911030551j1accd6fby7038895df544385b@mail.gmail.com> Subject: Re: [PATCH] Make MIPS dynamic clocksource/clockevent clock code generic v2 From: Linus Walleij To: Thomas Gleixner Cc: Linus Walleij , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mips@linux-mips.org, Mikael Pettersson , Ralf Baechle Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24635 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: linus.ml.walleij@gmail.com Precedence: bulk X-list: linux-mips 2009/10/25 Linus Walleij : > 2009/10/21 Linus Walleij : > >> Changes v1->v2: >> - Fixed Mikaels comments: spelling, terminology. >> - Kept the functions inline: all uses and foreseen uses >>  are once per kernel and all are in __init or __cpuinit sections. >> - Unable to break out common code - the code is not common and >>  implementing two execution paths will be more awkward. >> - Hoping the tglx likes it anyway. > > Ping on tglx on this, I will uninline the functions if you think > it's better in the long run, just tell me, else can you pick this > patch? Ping again... Linus Walleij From ralf@linux-mips.org Tue Nov 3 16:24:54 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 03 Nov 2009 16:25:00 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:47516 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-FAIL) by ftp.linux-mips.org with ESMTP id S1493363AbZKCPYy (ORCPT ); Tue, 3 Nov 2009 16:24:54 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id nA3FQEP3001798; Tue, 3 Nov 2009 16:26:15 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id nA3FQDM6001796; Tue, 3 Nov 2009 16:26:13 +0100 Date: Tue, 3 Nov 2009 16:26:13 +0100 From: Ralf Baechle To: Manuel Lauss Cc: Linux-MIPS , Manuel Lauss , David Woodhouse Subject: Re: [PATCH] MIPS: Alchemy: physmap-flash for all devboards Message-ID: <20091103152613.GA1742@linux-mips.org> References: <1255949617-22943-1-git-send-email-manuel.lauss@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1255949617-22943-1-git-send-email-manuel.lauss@gmail.com> User-Agent: Mutt/1.5.19 (2009-01-05) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24636 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Mon, Oct 19, 2009 at 12:53:37PM +0200, Manuel Lauss wrote: > Replace the devboard NOR MTD mapping driver with physmap-flash support. > Also honor the "swapboot" switch settings wrt. to the layout of the > NOR partitions. > > Signed-off-by: Manuel Lauss Thanks, with David's Ack (from IRC) queued for -2.6.33. Ralf From ralf@linux-mips.org Tue Nov 3 16:26:40 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 03 Nov 2009 16:26:43 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:40158 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-FAIL) by ftp.linux-mips.org with ESMTP id S1493363AbZKCP0k (ORCPT ); Tue, 3 Nov 2009 16:26:40 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id nA3FS7mu001856; Tue, 3 Nov 2009 16:28:07 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id nA3FS7Cw001854; Tue, 3 Nov 2009 16:28:07 +0100 Date: Tue, 3 Nov 2009 16:28:07 +0100 From: Ralf Baechle To: Manuel Lauss Cc: Linux-MIPS , Manuel Lauss Subject: Re: [RFC PATCH 1/3] MIPS: Alchemy: extended DB1200 board support. Message-ID: <20091103152807.GB1742@linux-mips.org> References: <1257193305-29996-1-git-send-email-manuel.lauss@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1257193305-29996-1-git-send-email-manuel.lauss@gmail.com> User-Agent: Mutt/1.5.19 (2009-01-05) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24637 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Mon, Nov 02, 2009 at 09:21:43PM +0100, Manuel Lauss wrote: > Create own directory for DB1200 code and update it with new features. > > - SPI support: > - tmp121 temperature sensor > - SPI flash on DB1200 > - I2C support > - NE1619 sensor > - AT24 eeprom > - I2C/SPI can be selected at boot time via switch S6.8 > - Carddetect IRQs for SD cards. > - gen_nand based NAND support. > - hexleds count sleep/wake transitions. > > Signed-off-by: Manuel Lauss Thanks, queued for 2.6.33. Ralf From ralf@linux-mips.org Tue Nov 3 16:29:17 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 03 Nov 2009 16:29:20 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:40382 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-FAIL) by ftp.linux-mips.org with ESMTP id S1493384AbZKCP3R (ORCPT ); Tue, 3 Nov 2009 16:29:17 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id nA3FUfQT001932; Tue, 3 Nov 2009 16:30:41 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id nA3FUeW2001929; Tue, 3 Nov 2009 16:30:40 +0100 Date: Tue, 3 Nov 2009 16:30:40 +0100 From: Ralf Baechle To: Manuel Lauss Cc: Linux-MIPS , Manuel Lauss , alsa-devel@alsa-project.org, Mark Brown Subject: Re: [RFC PATCH 2/3] MIPS: Alchemy: DB1200 AC97+I2S audio support. Message-ID: <20091103153040.GC1742@linux-mips.org> References: <1257193305-29996-1-git-send-email-manuel.lauss@gmail.com> <1257193305-29996-2-git-send-email-manuel.lauss@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1257193305-29996-2-git-send-email-manuel.lauss@gmail.com> User-Agent: Mutt/1.5.19 (2009-01-05) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24638 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Mon, Nov 02, 2009 at 09:21:44PM +0100, Manuel Lauss wrote: > Machine driver for DB1200 AC97 and I2S audio systems, intended as a > proper reference asoc machine for Alchemy-based systems. > AC97/I2S can be selected at boot time by setting switch S6.7 > > Cc: alsa-devel@alsa-project.org > Cc: Mark Brown > Signed-off-by: Manuel Lauss > --- > Depends on patch "ASoC: au1x: convert to platform drivers" in > Mark Brown's asoc tree to actually work. Queued for 2.6.33. I've not seen the dependency but I hope there is no harm in getting things merged out of order? Thanks, Ralf From manuel.lauss@googlemail.com Tue Nov 3 16:30:38 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 03 Nov 2009 16:30:44 +0100 (CET) Received: from mail-bw0-f221.google.com ([209.85.218.221]:64215 "EHLO mail-bw0-f221.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1493371AbZKCPai convert rfc822-to-8bit (ORCPT ); Tue, 3 Nov 2009 16:30:38 +0100 Received: by bwz21 with SMTP id 21so7672998bwz.24 for ; Tue, 03 Nov 2009 07:30:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=domainkey-signature:mime-version:received:in-reply-to:references :date:message-id:subject:from:to:cc:content-type :content-transfer-encoding; bh=RA4fC8DR++2aTqigWIFOQXZHy27yTSV7ScVxbMw3TdE=; b=lly9YDEzXpH6rguEiLUudlGGwbgSTUtkuII6Hez4I+D5y4TyRAeuoLrhe/Ow966IVy U5gnzn4V/diVBdpG26IADzs1N9TQtsnGqFPLZ+xkx9hlK5itTExT1QEcGyd5nKPoG/cr AA5tGlHTIo/OwhVWZvN3lP33TB5uk8y35O+pI= DomainKey-Signature: a=rsa-sha1; c=nofws; d=googlemail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type:content-transfer-encoding; b=oj92RkBXEcSqLJlYWyCCYPc0by9CBHrBP7blJXSTZJFZhq3RLP3ddkWrRNFe+zdnlY bcm0ml017FXeXHxqGzWf6MOU32wTfB0FDIpepbiC6E0fLhacCAH0SRMc2bJXTsPYpx0W +z05YZJNarjjriG0DzYbTUjcYDOuaZ72D96Mg= MIME-Version: 1.0 Received: by 10.223.73.20 with SMTP id o20mr16648faj.71.1257262227102; Tue, 03 Nov 2009 07:30:27 -0800 (PST) In-Reply-To: <20091103153040.GC1742@linux-mips.org> References: <1257193305-29996-1-git-send-email-manuel.lauss@gmail.com> <1257193305-29996-2-git-send-email-manuel.lauss@gmail.com> <20091103153040.GC1742@linux-mips.org> Date: Tue, 3 Nov 2009 16:30:26 +0100 Message-ID: Subject: Re: [RFC PATCH 2/3] MIPS: Alchemy: DB1200 AC97+I2S audio support. From: Manuel Lauss To: Ralf Baechle Cc: Linux-MIPS , Manuel Lauss , alsa-devel@alsa-project.org, Mark Brown Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24639 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips On Tue, Nov 3, 2009 at 4:30 PM, Ralf Baechle wrote: > On Mon, Nov 02, 2009 at 09:21:44PM +0100, Manuel Lauss wrote: > >> Machine driver for DB1200 AC97 and I2S audio systems, intended as a >> proper reference asoc machine for Alchemy-based systems. >> AC97/I2S can be selected at boot time by setting switch S6.7 >> >> Cc: alsa-devel@alsa-project.org >> Cc: Mark Brown >> Signed-off-by: Manuel Lauss >> --- >> Depends on patch "ASoC: au1x: convert to platform drivers" in >> Mark Brown's asoc tree to actually work. > > Queued for 2.6.33.  I've not seen the dependency but I hope there is no > harm in getting things merged out of order? You just won't get any sound if the other patch isnt applied first, no build failures of oopses. Manuel From tglx@linutronix.de Tue Nov 3 16:32:20 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 03 Nov 2009 16:32:27 +0100 (CET) Received: from www.tglx.de ([62.245.132.106]:58351 "EHLO www.tglx.de" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1493371AbZKCPcU (ORCPT ); Tue, 3 Nov 2009 16:32:20 +0100 Received: from localhost (www.tglx.de [127.0.0.1]) by www.tglx.de (8.13.8/8.13.8/TGLX-2007100201) with ESMTP id nA3FTfBc029842 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Tue, 3 Nov 2009 16:29:42 +0100 Date: Tue, 3 Nov 2009 16:29:41 +0100 (CET) From: Thomas Gleixner To: Linus Walleij cc: Linus Walleij , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mips@linux-mips.org, Mikael Pettersson , Ralf Baechle Subject: Re: [PATCH] Make MIPS dynamic clocksource/clockevent clock code generic v2 In-Reply-To: <63386a3d0911030551j1accd6fby7038895df544385b@mail.gmail.com> Message-ID: References: <1256078002-27919-1-git-send-email-linus.walleij@stericsson.com> <63386a3d0910251518i42149642g183f2d3f6c43384f@mail.gmail.com> <63386a3d0911030551j1accd6fby7038895df544385b@mail.gmail.com> User-Agent: Alpine 2.00 (LFD 1167 2008-08-23) MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII X-Virus-Scanned: clamav-milter 0.95.1 at www.tglx.de X-Virus-Status: Clean Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24640 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: tglx@linutronix.de Precedence: bulk X-list: linux-mips On Tue, 3 Nov 2009, Linus Walleij wrote: > > Ping on tglx on this, I will uninline the functions if you think > > it's better in the long run, just tell me, else can you pick this > > patch? > > Ping again... Still catching up with mail backlog. Will come to this in the next days. tglx From ralf@linux-mips.org Tue Nov 3 16:33:52 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 03 Nov 2009 16:33:55 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:49232 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-FAIL) by ftp.linux-mips.org with ESMTP id S1493388AbZKCPdw (ORCPT ); Tue, 3 Nov 2009 16:33:52 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id nA3FZIbX008911; Tue, 3 Nov 2009 16:35:18 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id nA3FZIId008909; Tue, 3 Nov 2009 16:35:18 +0100 Date: Tue, 3 Nov 2009 16:35:18 +0100 From: Ralf Baechle To: Manuel Lauss Cc: Linux-MIPS , Manuel Lauss , alsa-devel@alsa-project.org, Mark Brown Subject: Re: [RFC PATCH 2/3] MIPS: Alchemy: DB1200 AC97+I2S audio support. Message-ID: <20091103153518.GA5999@linux-mips.org> References: <1257193305-29996-1-git-send-email-manuel.lauss@gmail.com> <1257193305-29996-2-git-send-email-manuel.lauss@gmail.com> <20091103153040.GC1742@linux-mips.org> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: User-Agent: Mutt/1.5.19 (2009-01-05) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24641 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Tue, Nov 03, 2009 at 04:30:26PM +0100, Manuel Lauss wrote: > > On Tue, Nov 3, 2009 at 4:30 PM, Ralf Baechle wrote: > > On Mon, Nov 02, 2009 at 09:21:44PM +0100, Manuel Lauss wrote: > > > >> Machine driver for DB1200 AC97 and I2S audio systems, intended as a > >> proper reference asoc machine for Alchemy-based systems. > >> AC97/I2S can be selected at boot time by setting switch S6.7 > >> > >> Cc: alsa-devel@alsa-project.org > >> Cc: Mark Brown > >> Signed-off-by: Manuel Lauss > >> --- > >> Depends on patch "ASoC: au1x: convert to platform drivers" in > >> Mark Brown's asoc tree to actually work. > > > > Queued for 2.6.33.  I've not seen the dependency but I hope there is no > > harm in getting things merged out of order? > > You just won't get any sound if the other patch isnt applied first, > no build failures of oopses. With Mark's approval I'd not mind merging the other patch through the MIPS tree as well then. Ralf From manuel.lauss@googlemail.com Tue Nov 3 16:34:44 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 03 Nov 2009 16:34:50 +0100 (CET) Received: from mail-bw0-f221.google.com ([209.85.218.221]:64598 "EHLO mail-bw0-f221.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1493388AbZKCPeo convert rfc822-to-8bit (ORCPT ); Tue, 3 Nov 2009 16:34:44 +0100 Received: by bwz21 with SMTP id 21so7677804bwz.24 for ; Tue, 03 Nov 2009 07:34:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=domainkey-signature:mime-version:received:in-reply-to:references :date:message-id:subject:from:to:cc:content-type :content-transfer-encoding; bh=JWZdHMg3Bvv+fRk2OMj86M4QazS6FT1kezMKGTfqxRQ=; b=UfCknXYCxULmu9iHMOSU03IPJJXmpwFJhgooceIY/6oJM8jtm4HdBAHnaJkqkP9px3 qHnwXxl4LU4u6HRk3wfCRgqcIuujIu/NDFzJOAzNLdiG1GgF8LvbHLG4tKnOTi8aKWGs S6IZn83HIvLIPiDOG7sy9O8m23zxtkB+8U1zw= DomainKey-Signature: a=rsa-sha1; c=nofws; d=googlemail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type:content-transfer-encoding; b=Qlxy6m5XS+LSa+yYfJ9RYupYWf4JStI7sfJD1iykCZOJeFAk2O+kgbH9VNrfOCtAGa //BPxooFdMzuEAH6sOih1/DAZl4PitYRuE1SbM7FZYB6CyBXIRk7i+OKwKp4Fl4mWdSw b4rbTaMBkCBb6MgPr6Tvwkf1Ly9BCsuAm02ao= MIME-Version: 1.0 Received: by 10.223.16.72 with SMTP id n8mr22568faa.26.1257262478052; Tue, 03 Nov 2009 07:34:38 -0800 (PST) In-Reply-To: <20091103153518.GA5999@linux-mips.org> References: <1257193305-29996-1-git-send-email-manuel.lauss@gmail.com> <1257193305-29996-2-git-send-email-manuel.lauss@gmail.com> <20091103153040.GC1742@linux-mips.org> <20091103153518.GA5999@linux-mips.org> Date: Tue, 3 Nov 2009 16:34:37 +0100 Message-ID: Subject: Re: [RFC PATCH 2/3] MIPS: Alchemy: DB1200 AC97+I2S audio support. From: Manuel Lauss To: Ralf Baechle Cc: Linux-MIPS , Manuel Lauss , alsa-devel@alsa-project.org, Mark Brown Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24642 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips On Tue, Nov 3, 2009 at 4:35 PM, Ralf Baechle wrote: > On Tue, Nov 03, 2009 at 04:30:26PM +0100, Manuel Lauss wrote: > >> >> On Tue, Nov 3, 2009 at 4:30 PM, Ralf Baechle wrote: >> > On Mon, Nov 02, 2009 at 09:21:44PM +0100, Manuel Lauss wrote: >> > >> >> Machine driver for DB1200 AC97 and I2S audio systems, intended as a >> >> proper reference asoc machine for Alchemy-based systems. >> >> AC97/I2S can be selected at boot time by setting switch S6.7 >> >> >> >> Cc: alsa-devel@alsa-project.org >> >> Cc: Mark Brown >> >> Signed-off-by: Manuel Lauss >> >> --- >> >> Depends on patch "ASoC: au1x: convert to platform drivers" in >> >> Mark Brown's asoc tree to actually work. >> > >> > Queued for 2.6.33.  I've not seen the dependency but I hope there is no >> > harm in getting things merged out of order? >> >> You just won't get any sound if the other patch isnt applied first, >> no build failures of oopses. > > With Mark's approval I'd not mind merging the other patch through the MIPS > tree as well then. AFAIK Takashi already pulled it into the alsa tree for .33 From khickey@netlogicmicro.com Tue Nov 3 16:41:27 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 03 Nov 2009 16:41:33 +0100 (CET) Received: from mail.netlogicmicro.com ([64.0.7.62]:4568 "EHLO orion5.netlogicmicro.com" rhost-flags-OK-OK-OK-FAIL) by ftp.linux-mips.org with ESMTP id S1493381AbZKCPl1 convert rfc822-to-8bit (ORCPT ); Tue, 3 Nov 2009 16:41:27 +0100 Received: from orion8.netlogicmicro.com ([10.1.1.7]) by orion5.netlogicmicro.com with InterScan Message Security Suite; Tue, 03 Nov 2009 07:42:06 -0800 Received: from 12.234.128.66 ([12.234.128.66]) by orion8.netlogicmicro.com ([10.1.1.7]) with Microsoft Exchange Server HTTP-DAV ;Tue, 3 Nov 2009 15:42:06 +0000 Received: from kh-t3500 by 12.239.216.94; 03 Nov 2009 09:41:03 -0600 Subject: Re: [RFC PATCH 1/3] MIPS: Alchemy: extended DB1200 board support. From: Kevin Hickey To: Manuel Lauss Cc: Linux-MIPS , Manuel Lauss In-Reply-To: <1257193305-29996-1-git-send-email-manuel.lauss@gmail.com> References: <1257193305-29996-1-git-send-email-manuel.lauss@gmail.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8BIT Date: Tue, 03 Nov 2009 09:41:03 -0600 Message-ID: <1257262863.29642.8.camel@localhost> Mime-Version: 1.0 X-Mailer: Evolution 2.28.1 X-imss-version: 2.054 X-imss-result: Passed X-imss-scanInfo: M:P L:N SM:0 X-imss-tmaseResult: TT:0 TS:0.0000 TC:00 TRN:0 TV:5.6.1016(16988.000) X-imss-scores: Clean:99.90000 C:2 M:3 S:5 R:5 X-imss-settings: Baseline:2 C:4 M:4 S:4 R:4 (0.1500 0.1500) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24643 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: khickey@netlogicmicro.com Precedence: bulk X-list: linux-mips On Mon, 2009-11-02 at 21:21 +0100, Manuel Lauss wrote: > Create own directory for DB1200 code and update it with new features. > > - SPI support: > - tmp121 temperature sensor > - SPI flash on DB1200 > - I2C support > - NE1619 sensor > - AT24 eeprom > - I2C/SPI can be selected at boot time via switch S6.8 > - Carddetect IRQs for SD cards. > - gen_nand based NAND support. > - hexleds count sleep/wake transitions. > > Signed-off-by: Manuel Lauss > --- The code in this patch all looks good to me. I don't understand how much value is added by using the hex LEDs for counting sleep/wake transitions. In our internal builds, we use the hex LEDs for displaying the last interrupt serviced (useful on hangs/crashes and for getting a general sense of what the hardware is working on), the dots blink on timer ticks (often every 100 or 1000 depending on the clock) and the Idle state is shown on LED0. I don't really have any strong attachment to those usages, but they've served us well. Otherwise this looks good to me. Hope this isn't too late (I saw the email saying it was queued come in as I typed this one). =Kevin From khickey@netlogicmicro.com Tue Nov 3 16:42:05 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 03 Nov 2009 16:42:12 +0100 (CET) Received: from mail.netlogicmicro.com ([64.0.7.62]:4600 "EHLO orion5.netlogicmicro.com" rhost-flags-OK-OK-OK-FAIL) by ftp.linux-mips.org with ESMTP id S1493480AbZKCPmF convert rfc822-to-8bit (ORCPT ); Tue, 3 Nov 2009 16:42:05 +0100 Received: from orion8.netlogicmicro.com ([10.1.1.7]) by orion5.netlogicmicro.com with InterScan Message Security Suite; Tue, 03 Nov 2009 07:42:55 -0800 Received: from 12.234.128.66 ([12.234.128.66]) by orion8.netlogicmicro.com ([10.1.1.7]) with Microsoft Exchange Server HTTP-DAV ;Tue, 3 Nov 2009 15:42:54 +0000 Received: from kh-t3500 by 12.239.216.94; 03 Nov 2009 09:41:52 -0600 Subject: Re: addinitrd deletion From: Kevin Hickey To: Ralf Baechle Cc: linux-mips@linux-mips.org In-Reply-To: <20091103121838.GA27403@linux-mips.org> References: <20091103121838.GA27403@linux-mips.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8BIT Date: Tue, 03 Nov 2009 09:41:52 -0600 Message-ID: <1257262912.29642.9.camel@localhost> Mime-Version: 1.0 X-Mailer: Evolution 2.28.1 X-imss-version: 2.054 X-imss-result: Passed X-imss-scanInfo: M:P L:N SM:0 X-imss-tmaseResult: TT:0 TS:0.0000 TC:00 TRN:0 TV:5.6.1016(16988.000) X-imss-scores: Clean:96.78905 C:2 M:3 S:5 R:5 X-imss-settings: Baseline:2 C:4 M:4 S:4 R:4 (0.1500 0.1500) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24644 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: khickey@netlogicmicro.com Precedence: bulk X-list: linux-mips On Tue, 2009-11-03 at 13:18 +0100, Ralf Baechle wrote: > Does anybody still see any use for addinitrd? If not I'm going to delete > it. > FWIW I do not... =Kevin From manuel.lauss@googlemail.com Tue Nov 3 16:44:10 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 03 Nov 2009 16:44:16 +0100 (CET) Received: from mail-bw0-f221.google.com ([209.85.218.221]:39154 "EHLO mail-bw0-f221.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1493483AbZKCPoK convert rfc822-to-8bit (ORCPT ); Tue, 3 Nov 2009 16:44:10 +0100 Received: by bwz21 with SMTP id 21so7688305bwz.24 for ; Tue, 03 Nov 2009 07:44:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=domainkey-signature:mime-version:received:in-reply-to:references :date:message-id:subject:from:to:cc:content-type :content-transfer-encoding; bh=BPnXrtba1op9PgX6J67aioR/EHyQACTTM+I2iV5SZlk=; b=Ix2jOsgZygauOCmMmd1m4uiCzFFekGg+nLfdwglUiXvoqblkiVa+hACMDXfz+Mk5kT wT6vpMPf/pWz8vg9yosK17MKv90VYBznBJUEY4zQh7eEcA9NJxisGYnpJYXDeIZ+S/mp AtyxFHBjyPv5jf9wrZNhdy/W3am7hSfIt4ct4= DomainKey-Signature: a=rsa-sha1; c=nofws; d=googlemail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type:content-transfer-encoding; b=IEgSi5c2artJgbcOtNuvNdMPlxuKmqAuVt2x/X3If5G7ljO3oOdl/0mqkXKbQlZXyE E7SMyrb1kHqxLUn+pPZi6ZYxL0zdeWMGftlV0gemLKy5hf4I7aPDob8ozNMHtDozM9q+ +DOGP0HtoISZp00wdcJUX0pV+8TGuVYooQtwk= MIME-Version: 1.0 Received: by 10.223.161.212 with SMTP id s20mr27413fax.2.1257263044844; Tue, 03 Nov 2009 07:44:04 -0800 (PST) In-Reply-To: <1257262863.29642.8.camel@localhost> References: <1257193305-29996-1-git-send-email-manuel.lauss@gmail.com> <1257262863.29642.8.camel@localhost> Date: Tue, 3 Nov 2009 16:44:04 +0100 Message-ID: Subject: Re: [RFC PATCH 1/3] MIPS: Alchemy: extended DB1200 board support. From: Manuel Lauss To: Kevin Hickey Cc: Linux-MIPS , Manuel Lauss Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24645 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips On Tue, Nov 3, 2009 at 4:41 PM, Kevin Hickey wrote: > On Mon, 2009-11-02 at 21:21 +0100, Manuel Lauss wrote: >> Create own directory for DB1200 code and update it with new features. >> >> - SPI support: >>   - tmp121 temperature sensor >>   - SPI flash on DB1200 >> - I2C support >>   - NE1619 sensor >>   - AT24 eeprom >> - I2C/SPI can be selected at boot time via switch S6.8 >> - Carddetect IRQs for SD cards. >> - gen_nand based NAND support. >> - hexleds count sleep/wake transitions. >> >> Signed-off-by: Manuel Lauss >> --- > > The code in this patch all looks good to me.  I don't understand how > much value is added by using the hex LEDs for counting sleep/wake > transitions.  In our internal builds, we use the hex LEDs for displaying > the last interrupt serviced (useful on hangs/crashes and for getting a > general sense of what the hardware is working on), the dots blink on > timer ticks (often every 100 or 1000 depending on the clock) and the > Idle state is shown on LED0.  I don't really have any strong attachment > to those usages, but they've served us well. I admit it has limited value.. I initially used it to find out how many wakeups per second are happening with and without high-speed usb devices attached. I left it in because I couldn't come up with any other uses. Please feel free to change it any time. Manuel From khickey@netlogicmicro.com Tue Nov 3 16:47:16 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 03 Nov 2009 16:47:23 +0100 (CET) Received: from mail.netlogicmicro.com ([64.0.7.62]:4857 "EHLO orion5.netlogicmicro.com" rhost-flags-OK-OK-OK-FAIL) by ftp.linux-mips.org with ESMTP id S1493489AbZKCPrQ convert rfc822-to-8bit (ORCPT ); Tue, 3 Nov 2009 16:47:16 +0100 Received: from orion8.netlogicmicro.com ([10.1.1.7]) by orion5.netlogicmicro.com with InterScan Message Security Suite; Tue, 03 Nov 2009 07:48:06 -0800 Received: from 12.234.128.66 ([12.234.128.66]) by orion8.netlogicmicro.com ([10.1.1.7]) with Microsoft Exchange Server HTTP-DAV ;Tue, 3 Nov 2009 15:48:05 +0000 Received: from kh-t3500 by 12.239.216.94; 03 Nov 2009 09:47:03 -0600 Subject: Re: [RFC PATCH 1/3] MIPS: Alchemy: extended DB1200 board support. From: Kevin Hickey To: Manuel Lauss Cc: Linux-MIPS , Manuel Lauss In-Reply-To: References: <1257193305-29996-1-git-send-email-manuel.lauss@gmail.com> <1257262863.29642.8.camel@localhost> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8BIT Date: Tue, 03 Nov 2009 09:47:03 -0600 Message-ID: <1257263223.29642.12.camel@localhost> Mime-Version: 1.0 X-Mailer: Evolution 2.28.1 X-imss-version: 2.054 X-imss-result: Passed X-imss-scanInfo: M:P L:N SM:0 X-imss-tmaseResult: TT:0 TS:0.0000 TC:00 TRN:0 TV:5.6.1016(16988.000) X-imss-scores: Clean:99.90000 C:2 M:3 S:5 R:5 X-imss-settings: Baseline:2 C:4 M:4 S:4 R:4 (0.1500 0.1500) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24646 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: khickey@netlogicmicro.com Precedence: bulk X-list: linux-mips On Tue, 2009-11-03 at 16:44 +0100, Manuel Lauss wrote: > On Tue, Nov 3, 2009 at 4:41 PM, Kevin Hickey wrote: > > On Mon, 2009-11-02 at 21:21 +0100, Manuel Lauss wrote: > >> Create own directory for DB1200 code and update it with new features. > >> > >> - SPI support: > >> - tmp121 temperature sensor > >> - SPI flash on DB1200 > >> - I2C support > >> - NE1619 sensor > >> - AT24 eeprom > >> - I2C/SPI can be selected at boot time via switch S6.8 > >> - Carddetect IRQs for SD cards. > >> - gen_nand based NAND support. > >> - hexleds count sleep/wake transitions. > >> > >> Signed-off-by: Manuel Lauss > >> --- > > > > The code in this patch all looks good to me. I don't understand how > > much value is added by using the hex LEDs for counting sleep/wake > > transitions. In our internal builds, we use the hex LEDs for displaying > > the last interrupt serviced (useful on hangs/crashes and for getting a > > general sense of what the hardware is working on), the dots blink on > > timer ticks (often every 100 or 1000 depending on the clock) and the > > Idle state is shown on LED0. I don't really have any strong attachment > > to those usages, but they've served us well. > > I admit it has limited value.. I initially used it to find out how many wakeups > per second are happening with and without high-speed usb devices attached. > I left it in because I couldn't come up with any other uses. Please feel free > to change it any time. Fair enough. If I get some time down the line I'll look into that. In the meantime this patch has a lot of value so it should probably just stay as it is. Again, if it's not too late: Acked-by: Kevin Hickey =Kevin From ralf@linux-mips.org Tue Nov 3 16:47:41 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 03 Nov 2009 16:47:45 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:47858 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-FAIL) by ftp.linux-mips.org with ESMTP id S1493490AbZKCPr1 (ORCPT ); Tue, 3 Nov 2009 16:47:27 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id nA3FmtmR009265; Tue, 3 Nov 2009 16:48:55 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id nA3FmsgX009263; Tue, 3 Nov 2009 16:48:54 +0100 Date: Tue, 3 Nov 2009 16:48:54 +0100 From: Ralf Baechle To: Kevin Hickey Cc: linux-mips@linux-mips.org Subject: Re: addinitrd deletion Message-ID: <20091103154854.GA9161@linux-mips.org> References: <20091103121838.GA27403@linux-mips.org> <1257262912.29642.9.camel@localhost> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1257262912.29642.9.camel@localhost> User-Agent: Mutt/1.5.19 (2009-01-05) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24647 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Tue, Nov 03, 2009 at 09:41:52AM -0600, Kevin Hickey wrote: > On Tue, 2009-11-03 at 13:18 +0100, Ralf Baechle wrote: > > Does anybody still see any use for addinitrd? If not I'm going to delete > > it. > > > FWIW I do not... Well, I've already queued a patch to delete addinitrd and everything else that belongs to it. So this question was one of these "speak up or forever hold your peace" kind of questions :-) I see you have a fancy new email address. Cheers, Ralf From khickey@netlogicmicro.com Tue Nov 3 16:52:57 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 03 Nov 2009 16:53:03 +0100 (CET) Received: from mail.netlogicmicro.com ([64.0.7.62]:1054 "EHLO orion5.netlogicmicro.com" rhost-flags-OK-OK-OK-FAIL) by ftp.linux-mips.org with ESMTP id S1493995AbZKCPw5 convert rfc822-to-8bit (ORCPT ); Tue, 3 Nov 2009 16:52:57 +0100 Received: from orion8.netlogicmicro.com ([10.1.1.7]) by orion5.netlogicmicro.com with InterScan Message Security Suite; Tue, 03 Nov 2009 07:53:50 -0800 Received: from 12.234.128.66 ([12.234.128.66]) by orion8.netlogicmicro.com ([10.1.1.7]) with Microsoft Exchange Server HTTP-DAV ;Tue, 3 Nov 2009 15:53:49 +0000 Received: from kh-t3500 by 12.239.216.94; 03 Nov 2009 09:52:47 -0600 Subject: Re: addinitrd deletion From: Kevin Hickey To: Ralf Baechle Cc: linux-mips@linux-mips.org In-Reply-To: <20091103154854.GA9161@linux-mips.org> References: <20091103121838.GA27403@linux-mips.org> <1257262912.29642.9.camel@localhost> <20091103154854.GA9161@linux-mips.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8BIT Date: Tue, 03 Nov 2009 09:52:46 -0600 Message-ID: <1257263566.29642.13.camel@localhost> Mime-Version: 1.0 X-Mailer: Evolution 2.28.1 X-imss-version: 2.054 X-imss-result: Passed X-imss-scanInfo: M:P L:N SM:0 X-imss-tmaseResult: TT:0 TS:0.0000 TC:00 TRN:0 TV:5.6.1016(16988.000) X-imss-scores: Clean:99.90000 C:2 M:3 S:5 R:5 X-imss-settings: Baseline:2 C:4 M:4 S:4 R:4 (0.1500 0.1500) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24648 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: khickey@netlogicmicro.com Precedence: bulk X-list: linux-mips On Tue, 2009-11-03 at 16:48 +0100, Ralf Baechle wrote: > On Tue, Nov 03, 2009 at 09:41:52AM -0600, Kevin Hickey wrote: > > > On Tue, 2009-11-03 at 13:18 +0100, Ralf Baechle wrote: > > > Does anybody still see any use for addinitrd? If not I'm going to delete > > > it. > > > > > FWIW I do not... > > Well, I've already queued a patch to delete addinitrd and everything else > that belongs to it. So this question was one of these "speak up or forever > hold your peace" kind of questions :-) Then I guess it's good for me that I don't use it :) > > I see you have a fancy new email address. Yup. RMI Corporation is now Netlogic Microsystems. They wasted no time in changing our email addresses. =Kevin From ralf@linux-mips.org Tue Nov 3 17:15:58 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 03 Nov 2009 17:16:01 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:45529 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-FAIL) by ftp.linux-mips.org with ESMTP id S1494020AbZKCQP6 (ORCPT ); Tue, 3 Nov 2009 17:15:58 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id nA3GHLEZ015398; Tue, 3 Nov 2009 17:17:21 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id nA3GHIge015396; Tue, 3 Nov 2009 17:17:18 +0100 Date: Tue, 3 Nov 2009 17:17:18 +0100 From: Ralf Baechle To: Wu Zhangjin Cc: Linux-MIPS , yanh@lemote.com, huhb@lemote.com, Zhang Le , zhangfx@lemote.com Subject: Re: [PATCH -queue 2/7] [loongson] mem.c: Register reserved memory pages Message-ID: <20091103161718.GB5999@linux-mips.org> References: <20091102141459.GG21563@linux-mips.org> <1257211265.3528.17.camel@falcon.domain.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1257211265.3528.17.camel@falcon.domain.org> User-Agent: Mutt/1.5.19 (2009-01-05) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24649 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Tue, Nov 03, 2009 at 09:21:05AM +0800, Wu Zhangjin wrote: > > Hmm... After our recent discussion on your hibernation issues I am > > wondering if this patch is actually still required or useful? > > It does not help the hibernation issue, but helps to clear the memory > layout to the users(cat /proc/iomem), is this a need? > > Seems some of the other architectures, including some MIPS variants have > registed the reserved space, so, could you please apply it? Thanks, also queued for 2.6.33. Ralf From manuel.lauss@googlemail.com Tue Nov 3 20:27:00 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 03 Nov 2009 20:27:05 +0100 (CET) Received: from ey-out-1920.google.com ([74.125.78.148]:59244 "EHLO ey-out-1920.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1494030AbZKCT1A (ORCPT ); Tue, 3 Nov 2009 20:27:00 +0100 Received: by ey-out-1920.google.com with SMTP id 5so1176585eyb.52 for ; Tue, 03 Nov 2009 11:26:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer; bh=KHp3E4NkozXbLGyBEN25sSpZk5jA2OgCjvjzkvkia84=; b=eKOGbHPJeYx7u813NQAyFiR3GLNiILKnahsvEipdQyYsTfa5AXbDd3Wqqz1jwTA35v vGa43wOkzRps+WrTvSQRcGt49kgpzuIyptCSjNf+j+iHUUn88+DUgFzthXARP2pU3TVa hqafTEwKz/CbmG8fftP5esdP5mUSpPDNQOed0= DomainKey-Signature: a=rsa-sha1; c=nofws; d=googlemail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer; b=kLi2GW2L3UHXRtfKRZQBjhydsjLgrX71pIWgVekk6Bju+/zhJVLFolZYVW/aRarGoQ UTQ0+ufxhYNLn2tPD/gA2OSEG8elsioYfFXLMF9cWjBc53ixk3KmoBo9ACvKhovoUJF+ w5lwCOVB0ZlH+LCPJCXc5E4PGLWejIcgT33lM= Received: by 10.216.90.18 with SMTP id d18mr158902wef.225.1257276417824; Tue, 03 Nov 2009 11:26:57 -0800 (PST) Received: from localhost.localdomain (p5496F342.dip.t-dialin.net [84.150.243.66]) by mx.google.com with ESMTPS id p10sm1157027gvf.29.2009.11.03.11.26.55 (version=TLSv1/SSLv3 cipher=RC4-MD5); Tue, 03 Nov 2009 11:26:56 -0800 (PST) From: Manuel Lauss To: Linux-MIPS Cc: Kevin Hickey , Manuel Lauss Subject: [RFC PATCH -queue 0/2] DB1300 support Date: Tue, 3 Nov 2009 20:27:01 +0100 Message-Id: <1257276423-26413-1-git-send-email-manuel.lauss@gmail.com> X-Mailer: git-send-email 1.6.5.2 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24650 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips Here are 2 patches against current mips-queue which add Au1300 and Db1300 devboard support. It's a work-in-progress, and has one serious flaw: I can't get the serial console to work reliably once kernel starts booting userpsace. Enabling debugging shows the enabling the proper irq, however hardly any interrupts arrive unless massive amounts of debug info (by way of the irq dispatcher) is dumped out to it. Once userspace has booted, and most debig output has been hidden (echo 0 0 0 0 > /proc/sys/kernel/printk) it continues to work as it should for a few bytes, then it dies. Judging from the debug logs it seems the UART generates far less interrupts than for example the au1200 ones. Until its figured out what's going on, please take the opportunity to have a look at the code and suggest better ways to implement things and bugs. Thanks! Manuel Lauss (2): MIPS: Alchemy: Au1300 SoC support Alchemy: DB1300 support WIP WIP WIP arch/mips/Makefile | 7 + arch/mips/alchemy/Kconfig | 31 +- arch/mips/alchemy/common/Makefile | 9 +- arch/mips/alchemy/common/dbdma.c | 48 +- arch/mips/alchemy/common/gpioint.c | 374 +++++++ arch/mips/alchemy/common/gpiolib-au1300.c | 54 + arch/mips/alchemy/common/platform.c | 9 + arch/mips/alchemy/common/power.c | 18 +- arch/mips/alchemy/common/time.c | 1 + arch/mips/alchemy/devboards/Makefile | 1 + arch/mips/alchemy/devboards/db1300/Makefile | 2 + arch/mips/alchemy/devboards/db1300/platform.c | 234 +++++ arch/mips/alchemy/devboards/db1300/setup.c | 158 +++ arch/mips/alchemy/devboards/prom.c | 4 + arch/mips/configs/db1300_defconfig | 1160 ++++++++++++++++++++++ arch/mips/include/asm/cpu.h | 8 + arch/mips/include/asm/mach-au1x00/au1000.h | 189 ++++ arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h | 33 + arch/mips/include/asm/mach-au1x00/gpio-au1300.h | 211 ++++ arch/mips/include/asm/mach-au1x00/gpio.h | 4 + arch/mips/include/asm/mach-db1x00/bcsr.h | 3 + arch/mips/include/asm/mach-db1x00/db1300.h | 37 + arch/mips/kernel/cpu-probe.c | 18 + drivers/i2c/busses/Kconfig | 2 +- drivers/pcmcia/db1xxx_ss.c | 14 +- drivers/spi/Kconfig | 2 +- drivers/video/Kconfig | 10 +- 27 files changed, 2613 insertions(+), 28 deletions(-) create mode 100644 arch/mips/alchemy/common/gpioint.c create mode 100644 arch/mips/alchemy/common/gpiolib-au1300.c create mode 100644 arch/mips/alchemy/devboards/db1300/Makefile create mode 100644 arch/mips/alchemy/devboards/db1300/platform.c create mode 100644 arch/mips/alchemy/devboards/db1300/setup.c create mode 100644 arch/mips/configs/db1300_defconfig create mode 100644 arch/mips/include/asm/mach-au1x00/gpio-au1300.h create mode 100644 arch/mips/include/asm/mach-db1x00/db1300.h From manuel.lauss@googlemail.com Tue Nov 3 20:27:23 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 03 Nov 2009 20:27:30 +0100 (CET) Received: from mail-ew0-f216.google.com ([209.85.219.216]:37407 "EHLO mail-ew0-f216.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1494032AbZKCT1H (ORCPT ); Tue, 3 Nov 2009 20:27:07 +0100 Received: by ewy12 with SMTP id 12so963634ewy.0 for ; Tue, 03 Nov 2009 11:27:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer:in-reply-to:references; bh=CStglZw6E/lQ0bCBs3dxBD85T68wvIcAQK3zR8E00UU=; b=UefaKs1RjHGgBEG8mbfTGFja/ji1m+dKhoeGfDUO7eyBl0oV9BmIPTQPoyDq+pa3W+ 4gH8HuxefEZaLzdi8qnIg2E7F85Jnn1eYyA6X8jkwMZQFtf1O3kq/8muh2w10HOhLR5K grvGt+PAlIf83Se/5/6cA2ciNIihgIoPF6AjI= DomainKey-Signature: a=rsa-sha1; c=nofws; d=googlemail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; b=agx4BfVIVy6YmqnW+fWQTueVOy47fI5jJ1AmbibejC+SxfeqYW/BCa+HYLtwKMHfY0 llnk8Jcd6lzDuDSasaj76sa4qGqy4HTkninXkgcQ4tZgWSoe9uqpRyRM8RLRdvcA+6uP wzBY6pqem17PS3YYOeq/zf8hGlMZCUUqn8U2c= Received: by 10.216.87.68 with SMTP id x46mr167431wee.2.1257276419936; Tue, 03 Nov 2009 11:26:59 -0800 (PST) Received: from localhost.localdomain (p5496F342.dip.t-dialin.net [84.150.243.66]) by mx.google.com with ESMTPS id p10sm1157027gvf.29.2009.11.03.11.26.57 (version=TLSv1/SSLv3 cipher=RC4-MD5); Tue, 03 Nov 2009 11:26:59 -0800 (PST) From: Manuel Lauss To: Linux-MIPS Cc: Kevin Hickey , Manuel Lauss Subject: [RFC PATCH -queue 1/2] MIPS: Alchemy: Au1300 SoC support Date: Tue, 3 Nov 2009 20:27:02 +0100 Message-Id: <1257276423-26413-2-git-send-email-manuel.lauss@gmail.com> X-Mailer: git-send-email 1.6.5.2 In-Reply-To: <1257276423-26413-1-git-send-email-manuel.lauss@gmail.com> References: <1257276423-26413-1-git-send-email-manuel.lauss@gmail.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24651 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips Add support for the Au1300 SoC: New GPIO/Interrupt controller code, basic integration. doesn't work quite right yet: serial console uart doesn't generate enough interrupts. --- arch/mips/alchemy/Kconfig | 23 +- arch/mips/alchemy/common/Makefile | 9 +- arch/mips/alchemy/common/dbdma.c | 48 +++- arch/mips/alchemy/common/gpioint.c | 374 ++++++++++++++++++++++ arch/mips/alchemy/common/gpiolib-au1300.c | 54 +++ arch/mips/alchemy/common/platform.c | 9 + arch/mips/alchemy/common/power.c | 18 +- arch/mips/alchemy/common/time.c | 1 + arch/mips/include/asm/cpu.h | 8 + arch/mips/include/asm/mach-au1x00/au1000.h | 189 +++++++++++ arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h | 33 ++ arch/mips/include/asm/mach-au1x00/gpio-au1300.h | 211 ++++++++++++ arch/mips/include/asm/mach-au1x00/gpio.h | 4 + arch/mips/kernel/cpu-probe.c | 18 + drivers/i2c/busses/Kconfig | 2 +- drivers/spi/Kconfig | 2 +- drivers/video/Kconfig | 10 +- 17 files changed, 987 insertions(+), 26 deletions(-) create mode 100644 arch/mips/alchemy/common/gpioint.c create mode 100644 arch/mips/alchemy/common/gpiolib-au1300.c create mode 100644 arch/mips/include/asm/mach-au1x00/gpio-au1300.h diff --git a/arch/mips/alchemy/Kconfig b/arch/mips/alchemy/Kconfig index 22f4ff5..478699e 100644 --- a/arch/mips/alchemy/Kconfig +++ b/arch/mips/alchemy/Kconfig @@ -1,5 +1,9 @@ -# au1000-style gpio -config ALCHEMY_GPIO_AU1000 +# au1000-style GPIO and interrupt controller +config ALCHEMY_GPIOINT_AU1000 + bool + +# au1300-style GPIO/INT controller +config ALCHEMY_GPIOINT_AU1300 bool # select this in your board config if you don't want to use the gpio @@ -133,27 +137,32 @@ endchoice config SOC_AU1000 bool select SOC_AU1X00 - select ALCHEMY_GPIO_AU1000 + select ALCHEMY_GPIOINT_AU1000 config SOC_AU1100 bool select SOC_AU1X00 - select ALCHEMY_GPIO_AU1000 + select ALCHEMY_GPIOINT_AU1000 config SOC_AU1500 bool select SOC_AU1X00 - select ALCHEMY_GPIO_AU1000 + select ALCHEMY_GPIOINT_AU1000 config SOC_AU1550 bool select SOC_AU1X00 - select ALCHEMY_GPIO_AU1000 + select ALCHEMY_GPIOINT_AU1000 config SOC_AU1200 bool select SOC_AU1X00 - select ALCHEMY_GPIO_AU1000 + select ALCHEMY_GPIOINT_AU1000 + +config SOC_AU1300 + bool + select SOC_AU1X00 + select ALCHEMY_GPIOINT_AU1300 config SOC_AU1X00 bool diff --git a/arch/mips/alchemy/common/Makefile b/arch/mips/alchemy/common/Makefile index abf0eb1..fd983c0 100644 --- a/arch/mips/alchemy/common/Makefile +++ b/arch/mips/alchemy/common/Makefile @@ -5,14 +5,17 @@ # Makefile for the Alchemy Au1xx0 CPUs, generic files. # -obj-y += prom.o irq.o time.o reset.o \ - clocks.o platform.o power.o setup.o \ +obj-y += prom.o time.o reset.o clocks.o platform.o power.o setup.o \ sleeper.o dma.o dbdma.o +obj-$(CONFIG_ALCHEMY_GPIOINT_AU1000) += irq.o +obj-$(CONFIG_ALCHEMY_GPIOINT_AU1300) += gpioint.o + # optional gpiolib support ifeq ($(CONFIG_ALCHEMY_GPIO_INDIRECT),) ifeq ($(CONFIG_GPIOLIB),y) - obj-$(CONFIG_ALCHEMY_GPIO_AU1000) += gpiolib-au1000.o + obj-$(CONFIG_ALCHEMY_GPIOINT_AU1000) += gpiolib-au1000.o + obj-$(CONFIG_ALCHEMY_GPIOINT_AU1300) += gpiolib-au1300.o endif endif diff --git a/arch/mips/alchemy/common/dbdma.c b/arch/mips/alchemy/common/dbdma.c index 4cab5a6..2e2787a 100644 --- a/arch/mips/alchemy/common/dbdma.c +++ b/arch/mips/alchemy/common/dbdma.c @@ -39,8 +39,6 @@ #include #include -#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) - /* * The Descriptor Based DMA supports up to 16 channels. * @@ -150,6 +148,47 @@ static dbdev_tab_t dbdev_tab[] = { #endif /* CONFIG_SOC_AU1200 */ +#ifdef CONFIG_SOC_AU1300 + { DSCR_CMD0_UART0_TX, DEV_FLAGS_OUT, 0, 8, 0x10100004, 0, 0 }, + { DSCR_CMD0_UART0_RX, DEV_FLAGS_IN, 0, 8, 0x10100000, 0, 0 }, + { DSCR_CMD0_UART1_TX, DEV_FLAGS_OUT, 0, 8, 0x01011004, 0, 0 }, + { DSCR_CMD0_UART1_RX, DEV_FLAGS_IN, 0, 8, 0x10101000, 0, 0 }, + { DSCR_CMD0_UART2_TX, DEV_FLAGS_OUT, 0, 8, 0x01012004, 0, 0 }, + { DSCR_CMD0_UART2_RX, DEV_FLAGS_IN, 0, 8, 0x10102000, 0, 0 }, + { DSCR_CMD0_UART3_TX, DEV_FLAGS_OUT, 0, 8, 0x01013004, 0, 0 }, + { DSCR_CMD0_UART3_RX, DEV_FLAGS_IN, 0, 8, 0x10103000, 0, 0 }, + + { DSCR_CMD0_SDMS_TX0, DEV_FLAGS_OUT, 4, 8, 0x10600000, 0, 0 }, + { DSCR_CMD0_SDMS_RX0, DEV_FLAGS_IN, 4, 8, 0x10600004, 0, 0 }, + { DSCR_CMD0_SDMS_TX1, DEV_FLAGS_OUT, 8, 8, 0x10601000, 0, 0 }, + { DSCR_CMD0_SDMS_RX1, DEV_FLAGS_IN, 8, 8, 0x10601004, 0, 0 }, + + { DSCR_CMD0_AES_RX, DEV_FLAGS_IN , 4, 32, 0x10300008, 0, 0 }, + { DSCR_CMD0_AES_TX, DEV_FLAGS_OUT, 4, 32, 0x10300004, 0, 0 }, + + { DSCR_CMD0_PSC0_TX, DEV_FLAGS_OUT, 0, 16, 0x10a0001c, 0, 0 }, + { DSCR_CMD0_PSC0_RX, DEV_FLAGS_IN, 0, 16, 0x10a0001c, 0, 0 }, + { DSCR_CMD0_PSC1_TX, DEV_FLAGS_OUT, 0, 16, 0x10a0101c, 0, 0 }, + { DSCR_CMD0_PSC1_RX, DEV_FLAGS_IN, 0, 16, 0x10a0101c, 0, 0 }, + { DSCR_CMD0_PSC2_TX, DEV_FLAGS_OUT, 0, 16, 0x10a0201c, 0, 0 }, + { DSCR_CMD0_PSC2_RX, DEV_FLAGS_IN, 0, 16, 0x10a0201c, 0, 0 }, + { DSCR_CMD0_PSC3_TX, DEV_FLAGS_OUT, 0, 16, 0x10a0301c, 0, 0 }, + { DSCR_CMD0_PSC3_RX, DEV_FLAGS_IN, 0, 16, 0x10a0301c, 0, 0 }, + + { DSCR_CMD0_LCD, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, + { DSCR_CMD0_NAND_FLASH, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 }, + + { DSCR_CMD0_SDMS_TX2, DEV_FLAGS_OUT, 4, 8, 0x10602000, 0, 0 }, + { DSCR_CMD0_SDMS_RX2, DEV_FLAGS_IN, 4, 8, 0x10602004, 0, 0 }, + + { DSCR_CMD0_CIM_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, + + { DSCR_CMD0_UDMA, DEV_FLAGS_ANYUSE, 0, 32, 0x14001810, 0, 0 }, + + { DSCR_CMD0_DMA_REQ0, 0, 0, 0, 0x00000000, 0, 0 }, + { DSCR_CMD0_DMA_REQ1, 0, 0, 0, 0x00000000, 0, 0 }, +#endif /* CONFIG_SOC_AU1300 */ + { DSCR_CMD0_THROTTLE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, { DSCR_CMD0_ALWAYS, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, @@ -1040,6 +1079,9 @@ static int __init au1xxx_dbdma_init(void) case ALCHEMY_CPU_AU1200: irq_nr = AU1200_DDMA_INT; break; + case ALCHEMY_CPU_AU1300: + irq_nr = AU1300_DDMA_INT; + break; default: return -ENODEV; } @@ -1056,5 +1098,3 @@ static int __init au1xxx_dbdma_init(void) return ret; } subsys_initcall(au1xxx_dbdma_init); - -#endif /* defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) */ diff --git a/arch/mips/alchemy/common/gpioint.c b/arch/mips/alchemy/common/gpioint.c new file mode 100644 index 0000000..98f3b1b --- /dev/null +++ b/arch/mips/alchemy/common/gpioint.c @@ -0,0 +1,374 @@ +/* + * gpioint.c - Au1300 GPIO+Interrupt controller support. + * + * Copyright (c) 2009 Manuel Lauss + * + * licensed under the GPLv2. + */ + +#include +#include +#include +#include + +#include +#include +#include + +#if 1 +#define DBG(x...) printk(KERN_INFO "GPIC " x) +#else +#define DBG(x...) +#endif + +static int au1300_gpic_settype(unsigned int irq, unsigned int type); + +/* setup for known onchip sources */ +static struct gpic_devint_data { + int irq; /* linux IRQ number */ + int type; /* IRQ_TYPE_ */ + int prio; /* irq priority, 0 highest, 3 lowest */ + int setdev; /* assign to device function? */ +} au1300_devints[] __initdata = { + /* multifunction pins */ + { AU1300_UART1_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0, }, + { AU1300_UART2_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0, }, + { AU1300_UART3_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0, }, + { AU1300_SD1_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0, }, + { AU1300_SD2_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0, }, + { AU1300_PSC0_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0, }, + { AU1300_PSC1_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0, }, + { AU1300_PSC2_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0, }, + { AU1300_PSC3_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0, }, + { AU1300_NAND_INT, IRQ_TYPE_LEVEL_HIGH, 1, 0, }, + + /* au1300 internal device ints */ + { AU1300_DDMA_INT, IRQ_TYPE_LEVEL_HIGH, 1, 1, }, + { AU1300_MMU_INT, IRQ_TYPE_LEVEL_HIGH, 1, 1, }, + { AU1300_MPU_INT, IRQ_TYPE_LEVEL_HIGH, 1, 1, }, + { AU1300_GPU_INT, IRQ_TYPE_LEVEL_HIGH, 1, 1, }, + { AU1300_UDMA_INT, IRQ_TYPE_LEVEL_HIGH, 1, 1, }, + { AU1300_TOY_INT, IRQ_TYPE_EDGE_RISING, 1, 1, }, + { AU1300_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 1, 1, }, + { AU1300_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 1, 1, }, + { AU1300_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1, 1, }, + { AU1300_RTC_INT, IRQ_TYPE_EDGE_RISING, 1, 1, }, + { AU1300_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 1, 1, }, + { AU1300_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 1, 1, }, + { AU1300_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0, 1, }, + { AU1300_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 1, 1, }, + { AU1300_SD0_INT, IRQ_TYPE_LEVEL_HIGH, 1, 1, }, + { AU1300_USB_INT, IRQ_TYPE_LEVEL_HIGH, 1, 1, }, + { AU1300_LCD_INT, IRQ_TYPE_LEVEL_HIGH, 1, 1, }, + { AU1300_BSA_INT, IRQ_TYPE_LEVEL_HIGH, 1, 1, }, + { AU1300_MPE_INT, IRQ_TYPE_EDGE_RISING, 1, 1, }, + { AU1300_ITE_INT, IRQ_TYPE_LEVEL_HIGH, 1, 1, }, + { AU1300_AES_INT, IRQ_TYPE_LEVEL_HIGH, 1, 1, }, + { AU1300_CIM_INT, IRQ_TYPE_LEVEL_HIGH, 1, 1, }, + + { -1, }, /* terminator */ +}; + + +/** + * au1300_gpic_modcfg - change PIN configuration. + * @pin: pin to change (0-based GPIO number from datasheet). + * @clr: clear all bits set in 'clr'. + * @set: set these bits. + * + * modifies a pins' configuration register, bits set in @clr will + * be cleared in the register, and bits in @set will be set in the reg. + */ +void au1300_gpic_modcfg(int pin, unsigned long clr, unsigned long set) +{ + unsigned long l; + void __iomem *r; + + r = AU1300_GPIC_ADDR + (pin * 4); + + l = __raw_readl(r + AU1300_GPIC_PINCFG); + l &= ~clr; + l |= set; + __raw_writel(l, r + AU1300_GPIC_PINCFG); + wmb(); + + DBG("MODCFG(%03d) %08lx %08lx -> %08lx\n", pin, clr, set, l); +} +EXPORT_SYMBOL_GPL(au1300_gpic_modcfg); /* used by GPIO code too */ + +/** + * au1300_irq_set_idlewake - allow irq to wake CPU from 'wait' state. + * @irq: irq to change permission of. + * @allow: set 1 to allow @irq to wake CPU from 'wait'. + * + * Allow/Disallow an IRQ line to wake the CPU from 'wait' states. By + * default all unmasked IRQs are allowed to wake the CPU, this function + * should be used to override this if required. + */ +void au1300_irq_set_idlewake(int irq, int allow) +{ + irq -= AU1300_FIRST_INT; + au1300_gpic_modcfg(irq, GPIC_CFG_IDLEWAKE, + allow ? GPIC_CFG_IDLEWAKE : 0); + + DBG("SETIDLEWAKE(%03d) %d\n", irq, allow); +} +EXPORT_SYMBOL_GPL(au1300_irq_set_idlewake); + +/** + * au1300_pinfunc_to_gpio - assign a pin as GPIO input (GPIO ctrl). + * @pin: pin (0-based GPIO number from datasheet). + * + * Assigns a GPIO pin to the GPIO controller, so its level can either + * be read or set through the generic GPIO functions. + * If you need a GPOUT, use au1300_gpio_set_value(pin, 0/1). + */ +void au1300_pinfunc_to_gpio(enum au1300_multifunc_pins pin) +{ + /* switch to GPIN. Usually pin==gpio */ + au1300_gpio_direction_input(pin + AU1300_GPIO_BASE); + + DBG("PIN2GPIN(%03d)\n", (int)pin); +} +EXPORT_SYMBOL_GPL(au1300_pinfunc_to_gpio); + +/** + * au1300_pinfunc_to_dev - assign a pin to the device function. + * @pin: pin (0-based GPIO number from datasheet). + * + * Assigns a GPIO pin to its associated device function; the pin will be + * driven by the device and not through GPIO functions. + */ +void au1300_pinfunc_to_dev(enum au1300_multifunc_pins pin) +{ + void __iomem *r = AU1300_GPIC_ADDR; + unsigned long bit; + + r += AU1300_GPIO_TO_BANK(pin) * 4; + bit = 1 << AU1300_GPIO_TO_BIT(pin); + __raw_writel(bit, r + AU1300_GPIC_DEVSEL); + wmb(); + + DBG("PIN2DEV(%03d)\n", (int)pin); +} +EXPORT_SYMBOL_GPL(au1300_pinfunc_to_dev); + +/** + * au1300_set_irq_priority - set internal priority of IRQ. + * @irq: irq to set priority. + * @p: priority (0 = highest, 3 = lowest). + */ +void au1300_set_irq_priority(unsigned int irq, int p) +{ + irq -= AU1300_FIRST_INT; + au1300_gpic_modcfg(irq, GPIC_CFG_IL_MASK, GPIC_CFG_IL_SET(p)); +} +EXPORT_SYMBOL_GPL(au1300_set_irq_priority); + +/** + * au1300_set_dbdma_gpio - assign a gpio to one of the DBDMA triggers. + * @dchan: dbdma trigger select (0, 1). + * @pin: pin to assign as trigger. + * + * DBDMA controller has 2 external trigger sources; this function + * assigns a GPIO to the selected trigger. + */ +void au1300_set_dbdma_gpio(int dchan, unsigned int pin) +{ + unsigned long r; + + if ((dchan >= 0) && (dchan <= 1)) { + r = __raw_readl(AU1300_GPIC_ADDR + AU1300_GPIC_DMASEL); + r &= ~(0xff << (8 * dchan)); + r |= (pin & 0x7f) << (8 * dchan); + __raw_writel(r, AU1300_GPIC_ADDR + AU1300_GPIC_DMASEL); + wmb(); + } +} + +/**********************************************************************/ + +static void au1300_gpic_mask(unsigned int irq) +{ + void __iomem *r = AU1300_GPIC_ADDR; + unsigned long bit; + + irq -= AU1300_FIRST_INT; + r += AU1300_GPIO_TO_BANK(irq) * 4; + bit = 1 << AU1300_GPIO_TO_BIT(irq); + __raw_writel(bit, r + AU1300_GPIC_IDIS); + wmb(); +} + +static void au1300_gpic_unmask(unsigned int irq) +{ + void __iomem *r = AU1300_GPIC_ADDR; + unsigned long bit; + + irq -= AU1300_FIRST_INT; + r += AU1300_GPIO_TO_BANK(irq) * 4; + bit = 1 << AU1300_GPIO_TO_BIT(irq); + __raw_writel(bit, r + AU1300_GPIC_IEN); + wmb(); +} + +static void au1300_gpic_maskack(unsigned int irq) +{ + unsigned long bit; + void __iomem *r; + + irq -= AU1300_FIRST_INT; + r = AU1300_GPIC_ADDR + (AU1300_GPIO_TO_BANK(irq) * 4); + bit = 1 << AU1300_GPIO_TO_BIT(irq); + __raw_writel(bit, r + AU1300_GPIC_IPEND); /* ack */ + __raw_writel(bit, r + AU1300_GPIC_IDIS); + wmb(); +} + +static void au1300_gpic_ack(unsigned int irq) +{ + unsigned long bit; + void __iomem *r; + + irq -= AU1300_FIRST_INT; + r = AU1300_GPIC_ADDR + (AU1300_GPIO_TO_BANK(irq) * 4); + bit = 1 << AU1300_GPIO_TO_BIT(irq); + __raw_writel(bit, r + AU1300_GPIC_IPEND); /* ack */ + wmb(); +} + +static unsigned int au1300_gpic_startup(unsigned int irq) +{ + au1300_gpic_modcfg(irq - AU1300_FIRST_INT, 0, GPIC_CFG_IDLEWAKE); + au1300_gpic_unmask(irq); + return 0; +} + +static void au1300_gpic_shutdown(unsigned int irq) +{ + au1300_gpic_maskack(irq); + au1300_gpic_modcfg(irq - AU1300_FIRST_INT, GPIC_CFG_IDLEWAKE, 0); +} + +static struct irq_chip au1300_gpic = { + .name = "Au1300-GPIOINT", + .startup = au1300_gpic_startup, + .shutdown = au1300_gpic_shutdown, + .ack = au1300_gpic_ack, + .mask = au1300_gpic_mask, + .mask_ack = au1300_gpic_maskack, + .unmask = au1300_gpic_unmask, + .set_type = au1300_gpic_settype, +}; + +#define SICHN(i, h, n) \ + set_irq_chip_and_handler_name(i, &au1300_gpic, h, n) + +static int au1300_gpic_settype(unsigned int irq, unsigned int type) +{ + unsigned long s; + int ret; + + ret = 0; + switch (type) { + case IRQ_TYPE_LEVEL_HIGH: + s = GPIC_CFG_IC_LEVEL_HIGH; + SICHN(irq, handle_level_irq, "hilevel"); + break; + case IRQ_TYPE_LEVEL_LOW: + s = GPIC_CFG_IC_LEVEL_LOW; + SICHN(irq, handle_level_irq, "lolevel"); + break; + case IRQ_TYPE_EDGE_RISING: + s = GPIC_CFG_IC_EDGE_RISE; + SICHN(irq, handle_edge_irq, "riseedge"); + break; + case IRQ_TYPE_EDGE_FALLING: + s = GPIC_CFG_IC_EDGE_FALL; + SICHN(irq, handle_edge_irq, "falledge"); + break; + case IRQ_TYPE_EDGE_BOTH: + s = GPIC_CFG_IC_EDGE_BOTH; + SICHN(irq, handle_edge_irq, "bothedge"); + break; + case IRQ_TYPE_NONE: + s = GPIC_CFG_IC_OFF; + SICHN(irq, handle_level_irq, "disabled"); + break; + default: + return -EINVAL; + } + + au1300_gpic_modcfg(irq - AU1300_FIRST_INT, GPIC_CFG_IC_MASK, s); + + return ret; +} + +void __init arch_init_irq(void) +{ + int i; + void __iomem *bank_phys; + struct gpic_devint_data *dints; + + DBG("INIT START\n"); + + mips_cpu_irq_init(); + + /* disable & ack all possible on-chip sources */ + for (i = 0; i < 4; i++) { + bank_phys = AU1300_GPIC_ADDR + (i * 4); + __raw_writel(~0UL, bank_phys + AU1300_GPIC_IPEND); + __raw_writel(~0UL, bank_phys + AU1300_GPIC_IDIS); + wmb(); + } + + /* register all possible irq sources, with 2nd highest priority */ + for (i = AU1300_FIRST_INT; i <= AU1300_LAST_INT; i++) { + au1300_set_irq_priority(i, 1); + au1300_gpic_settype(i, IRQ_TYPE_NONE); + } + + /* setup known on-chip sources */ + dints = &au1300_devints[0]; + while (dints->irq != -1) { + i = dints->irq; + au1300_gpic_settype(i, dints->type); + au1300_set_irq_priority(i, dints->prio); + + /* assign to device function immediately? */ + if (dints->setdev) + au1300_pinfunc_to_dev(au1300_irq_to_gpio(i)); + + dints++; + } + + set_c0_status(IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3); + + DBG("INIT DONE\n"); +} + +void plat_irq_dispatch(void) +{ + unsigned long c = read_c0_cause() & read_c0_status(); + int d; + +/* DBG("INT CnM %08lx\n", c); */ + + if (c & CAUSEF_IP7) /* c0 timer */ + d = MIPS_CPU_IRQ_BASE + 7; + else if (c & (CAUSEF_IP2 | CAUSEF_IP3 | CAUSEF_IP4 | CAUSEF_IP5)) { + d = __raw_readl(AU1300_GPIC_ADDR + AU1300_GPIC_PRIENC); +/* XXX: HACK */ + if ((d != 87) && (d != 25)) + DBG("INT GPIC %d\n", d); +/* XXX */ + d += AU1300_FIRST_INT; + } else + goto spurious; + + do_IRQ(d); + return; +spurious: + DBG("SPURIOUS\n"); + spurious_interrupt(); +} diff --git a/arch/mips/alchemy/common/gpiolib-au1300.c b/arch/mips/alchemy/common/gpiolib-au1300.c new file mode 100644 index 0000000..661cc6f --- /dev/null +++ b/arch/mips/alchemy/common/gpiolib-au1300.c @@ -0,0 +1,54 @@ +/* + * Au1300-style GPIO/INT Controller GPIOLIB support + */ + +#include +#include +#include +#include +#include + +#include + +static int _gpic_get(struct gpio_chip *chip, unsigned int off) +{ + return au1300_gpio_get_value(off + AU1300_GPIO_BASE); +} + +static void _gpic_set(struct gpio_chip *chip, unsigned int off, int v) +{ + au1300_gpio_set_value(off + AU1300_GPIO_BASE, v); +} + +static int _gpic_direction_input(struct gpio_chip *chip, unsigned int off) +{ + return au1300_gpio_direction_input(off + AU1300_GPIO_BASE); +} + +static int _gpic_direction_output(struct gpio_chip *chip, unsigned int off, + int v) +{ + return au1300_gpio_direction_output(off + AU1300_GPIO_BASE, v); +} + +static int _gpic_gpio_to_irq(struct gpio_chip *chip, unsigned int off) +{ + return au1300_gpio_to_irq(off + AU1300_GPIO_BASE); +} + +static struct gpio_chip au1300_gpiochip = { + .label = "au1300", + .direction_input = _gpic_direction_input, + .direction_output = _gpic_direction_output, + .get = _gpic_get, + .set = _gpic_set, + .to_irq = _gpic_gpio_to_irq, + .base = AU1300_GPIO_BASE, + .ngpio = AU1300_GPIO_NUM, +}; + +static int __init au1300_gpiochip_init(void) +{ + return gpiochip_add(&au1300_gpiochip); +} +arch_initcall(au1300_gpiochip_init); diff --git a/arch/mips/alchemy/common/platform.c b/arch/mips/alchemy/common/platform.c index e47b035..6716570 100644 --- a/arch/mips/alchemy/common/platform.c +++ b/arch/mips/alchemy/common/platform.c @@ -69,6 +69,11 @@ static struct plat_serial8250_port au1x00_uart_data[] = { #elif defined(CONFIG_SOC_AU1200) PORT(UART0_PHYS_ADDR, AU1200_UART0_INT), PORT(UART1_PHYS_ADDR, AU1200_UART1_INT), +#elif defined(CONFIG_SOC_AU1300) + PORT(AU1300_UART0_PHYS_ADDR, AU1300_UART0_INT), + PORT(AU1300_UART1_PHYS_ADDR, AU1300_UART1_INT), + PORT(AU1300_UART2_PHYS_ADDR, AU1300_UART2_INT), + PORT(AU1300_UART3_PHYS_ADDR, AU1300_UART3_INT), #endif #endif /* CONFIG_SERIAL_8250_AU1X00 */ { }, @@ -82,6 +87,7 @@ static struct platform_device au1xx0_uart_device = { }, }; +#ifdef FOR_PLATFORM_C_USB_HOST_INT /* OHCI (USB full speed host controller) */ static struct resource au1xxx_usb_ohci_resources[] = { [0] = { @@ -109,6 +115,7 @@ static struct platform_device au1xxx_usb_ohci_device = { .num_resources = ARRAY_SIZE(au1xxx_usb_ohci_resources), .resource = au1xxx_usb_ohci_resources, }; +#endif /*** AU1100 LCD controller ***/ @@ -345,7 +352,9 @@ static struct platform_device pbdb_smbus_device = { static struct platform_device *au1xxx_platform_devices[] __initdata = { &au1xx0_uart_device, +#ifdef FOR_PLATFORM_C_USB_HOST_INT &au1xxx_usb_ohci_device, +#endif #ifdef CONFIG_FB_AU1100 &au1100_lcd_device, #endif diff --git a/arch/mips/alchemy/common/power.c b/arch/mips/alchemy/common/power.c index cf37e27..334e6f2 100644 --- a/arch/mips/alchemy/common/power.c +++ b/arch/mips/alchemy/common/power.c @@ -36,7 +36,8 @@ #include #include -#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) +#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) || \ + defined(CONFIG_SOC_AU1300) #include #endif @@ -52,7 +53,9 @@ * We only have to save/restore registers that aren't otherwise * done as part of a driver pm_* function. */ +#ifndef CONFIG_SOC_AU1300 static unsigned int sleep_usb[2]; +#endif static unsigned int sleep_sys_clocks[5]; static unsigned int sleep_sys_pinfunc; static unsigned int sleep_static_memctlr[4][3]; @@ -61,7 +64,8 @@ static unsigned int sleep_static_memctlr[4][3]; static void save_core_regs(void) { #ifndef CONFIG_SOC_AU1200 - /* Shutdown USB host/device. */ +#ifndef CONFIG_SOC_AU1300 +/* Shutdown USB host/device. */ sleep_usb[0] = au_readl(USB_HOST_CONFIG); /* There appears to be some undocumented reset register.... */ @@ -73,7 +77,7 @@ static void save_core_regs(void) sleep_usb[1] = au_readl(USBD_ENABLE); au_writel(0, USBD_ENABLE); au_sync(); - +#endif /* au1300 */ #else /* AU1200 */ /* enable access to OTG mmio so we can save OTG CAP/MUX. @@ -112,7 +116,8 @@ static void save_core_regs(void) sleep_static_memctlr[3][1] = au_readl(MEM_STTIME3); sleep_static_memctlr[3][2] = au_readl(MEM_STADDR3); -#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) +#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) || \ + defined(CONFIG_SOC_AU1300) au1xxx_dbdma_suspend(); #endif } @@ -136,9 +141,11 @@ static void restore_core_regs(void) au_sync(); #ifndef CONFIG_SOC_AU1200 +#ifndef CONFIG_SOC_AU1300 au_writel(sleep_usb[0], USB_HOST_CONFIG); au_writel(sleep_usb[1], USBD_ENABLE); au_sync(); +#endif #else /* enable accces to OTG memory */ au_writel(au_readl(USB_MSR_BASE + 4) | (1 << 6), USB_MSR_BASE + 4); @@ -167,7 +174,8 @@ static void restore_core_regs(void) restore_au1xxx_intctl(); -#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) +#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) || \ + defined(CONFIG_AOC_AU1300) au1xxx_dbdma_resume(); #endif } diff --git a/arch/mips/alchemy/common/time.c b/arch/mips/alchemy/common/time.c index 2aecb2f..db82325 100644 --- a/arch/mips/alchemy/common/time.c +++ b/arch/mips/alchemy/common/time.c @@ -179,6 +179,7 @@ static int alchemy_m2inttab[] __initdata = { AU1100_RTC_MATCH2_INT, AU1550_RTC_MATCH2_INT, AU1200_RTC_MATCH2_INT, + AU1300_RTC_MATCH2_INT, }; void __init plat_time_init(void) diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h index 4b96d1a..cd883c8 100644 --- a/arch/mips/include/asm/cpu.h +++ b/arch/mips/include/asm/cpu.h @@ -33,6 +33,7 @@ #define PRID_COMP_TOSHIBA 0x070000 #define PRID_COMP_LSI 0x080000 #define PRID_COMP_LEXRA 0x0b0000 +#define PRID_COMP_RMI 0x0c0000 #define PRID_COMP_CAVIUM 0x0d0000 @@ -121,6 +122,13 @@ #define PRID_REV_BCM6368 0x0030 /* + * These are the PRID's for when 23:16 == PRID_COMP_RMI + */ + +#define PRID_IMP_AU13XX 0x8000 + + +/* * These are the PRID's for when 23:16 == PRID_COMP_CAVIUM */ diff --git a/arch/mips/include/asm/mach-au1x00/au1000.h b/arch/mips/include/asm/mach-au1x00/au1000.h index e049d15..17373f9 100644 --- a/arch/mips/include/asm/mach-au1x00/au1000.h +++ b/arch/mips/include/asm/mach-au1x00/au1000.h @@ -136,6 +136,7 @@ static inline int au1xxx_cpu_needs_config_od(void) #define ALCHEMY_CPU_AU1100 2 #define ALCHEMY_CPU_AU1550 3 #define ALCHEMY_CPU_AU1200 4 +#define ALCHEMY_CPU_AU1300 5 static inline int alchemy_get_cputype(void) { @@ -155,6 +156,9 @@ static inline int alchemy_get_cputype(void) case 0x04030000: return ALCHEMY_CPU_AU1200; break; + case 0x800c0000: + return ALCHEMY_CPU_AU1300; + break; } return ALCHEMY_CPU_UNKNOWN; @@ -179,6 +183,71 @@ static inline void alchemy_uart_putchar(u32 uart_phys, u8 c) wmb(); } +/* Multifunction pins: Each of these pins can either be assigned to the + * GPIO controller or a on-chip peripheral. + * Call "au1300_pinfunc_to_dev()" or "au1300_pinfunc_to_gpio()" to + * assign one of these to either the GPIO controller or the device. + */ +enum au1300_multifunc_pins { + /* wake-from-str pins 0-3 */ + AU1300_PIN_WAKE0 = 0, AU1300_PIN_WAKE1, AU1300_PIN_WAKE2, + AU1300_PIN_WAKE3, + /* external clock sources for PSCs: 4-5 */ + AU1300_PIN_EXTCLK0, AU1300_PIN_EXTCLK1, + /* 8bit MMC interface on SD0: 6-9 */ + AU1300_PIN_SD0DAT4, AU1300_PIN_SD0DAT5, AU1300_PIN_SD0DAT6, + AU1300_PIN_SD0DAT7, + /* aux clk input for freqgen 3: 10 */ + AU1300_PIN_FG3AUX, + /* UART1 pins: 11-18 */ + AU1300_PIN_U1RI, AU1300_PIN_U1DCD, AU1300_PIN_U1DSR, + AU1300_PIN_U1CTS, AU1300_PIN_U1RTS, AU1300_PIN_U1DTR, + AU1300_PIN_U1RX, AU1300_PIN_U1TX, + /* UART0 pins: 19-24 */ + AU1300_PIN_U0RI, AU1300_PIN_U0DCD, AU1300_PIN_U0DSR, + AU1300_PIN_U0CTS, AU1300_PIN_U0RTS, AU1300_PIN_U0DTR, + /* UART2: 25-26 */ + AU1300_PIN_U2RX, AU1300_PIN_U2TX, + /* UART3: 27-28 */ + AU1300_PIN_U3RX, AU1300_PIN_U3TX, + /* LCD controller PWMs, ext pixclock: 29-31 */ + AU1300_PIN_LCDPWM0, AU1300_PIN_LCDPWM1, AU1300_PIN_LCDCLKIN, + /* SD1 interface: 32-37 */ + AU1300_PIN_SD1DAT0, AU1300_PIN_SD1DAT1, AU1300_PIN_SD1DAT2, + AU1300_PIN_SD1DAT3, AU1300_PIN_SD1CMD, AU1300_PIN_SD1CLK, + /* SD2 interface: 38-43 */ + AU1300_PIN_SD2DAT0, AU1300_PIN_SD2DAT1, AU1300_PIN_SD2DAT2, + AU1300_PIN_SD2DAT3, AU1300_PIN_SD2CMD, AU1300_PIN_SD2CLK, + /* PSC0/1 clocks: 44-45 */ + AU1300_PIN_PSC0CLK, AU1300_PIN_PSC1CLK, + /* PSCs: 46-49/50-53/54-57/58-61 */ + AU1300_PIN_PSC0SYNC0, AU1300_PIN_PSC0SYNC1, AU1300_PIN_PSC0D0, + AU1300_PIN_PSC0D1, + AU1300_PIN_PSC1SYNC0, AU1300_PIN_PSC1SYNC1, AU1300_PIN_PSC1D0, + AU1300_PIN_PSC1D1, + AU1300_PIN_PSC2SYNC0, AU1300_PIN_PSC2SYNC1, AU1300_PIN_PSC2D0, + AU1300_PIN_PSC2D1, + AU1300_PIN_PSC3SYNC0, AU1300_PIN_PSC3SYNC1, AU1300_PIN_PSC3D0, + AU1300_PIN_PSC3D1, + /* PCMCIA interface: 62-70 */ + AU1300_PIN_PCE2, AU1300_PIN_PCE1, AU1300_PIN_PIOS16, + AU1300_PIN_PIOR, AU1300_PIN_PWE, AU1300_PIN_PWAIT, + AU1300_PIN_PREG, AU1300_PIN_POE, AU1300_PIN_PIOW, + /* camera interface H/V sync inputs: 71-72 */ + AU1300_PIN_CIMLS, AU1300_PIN_CIMFS, + /* PSC2/3 clocks: 73-74 */ + AU1300_PIN_PSC2CLK, AU1300_PIN_PSC3CLK, +}; + +/* arch/mips/alchemy/common/gpioint.c */ +extern void au1300_gpic_modcfg(int gpio, unsigned long clr, + unsigned long set); +extern void au1300_irq_set_idlewake(int irq, int allow); +extern void au1300_pinfunc_to_gpio(enum au1300_multifunc_pins pin); +extern void au1300_pinfunc_to_dev(enum au1300_multifunc_pins pin); +extern void au1300_set_irq_priority(unsigned int irq, int p); +extern void au1300_set_dbdma_gpio(int dchan, unsigned int gpio); + /* arch/mips/au1000/common/clocks.c */ extern void set_au1x00_speed(unsigned int new_freq); extern unsigned int get_au1x00_speed(void); @@ -521,6 +590,44 @@ enum soc_au1200_ints { #endif /* !defined (_LANGUAGE_ASSEMBLY) */ +/* Au1300 peripheral interrupt numbers */ +#define AU1300_FIRST_INT (MIPS_CPU_IRQ_BASE + 8) +#define AU1300_UART1_INT (AU1300_FIRST_INT + 17) +#define AU1300_UART2_INT (AU1300_FIRST_INT + 25) +#define AU1300_UART3_INT (AU1300_FIRST_INT + 27) +#define AU1300_SD1_INT (AU1300_FIRST_INT + 32) +#define AU1300_SD2_INT (AU1300_FIRST_INT + 38) +#define AU1300_PSC0_INT (AU1300_FIRST_INT + 48) +#define AU1300_PSC1_INT (AU1300_FIRST_INT + 52) +#define AU1300_PSC2_INT (AU1300_FIRST_INT + 56) +#define AU1300_PSC3_INT (AU1300_FIRST_INT + 60) +#define AU1300_NAND_INT (AU1300_FIRST_INT + 62) +#define AU1300_DDMA_INT (AU1300_FIRST_INT + 75) +#define AU1300_MMU_INT (AU1300_FIRST_INT + 76) +#define AU1300_MPU_INT (AU1300_FIRST_INT + 77) +#define AU1300_GPU_INT (AU1300_FIRST_INT + 78) +#define AU1300_UDMA_INT (AU1300_FIRST_INT + 79) +#define AU1300_TOY_INT (AU1300_FIRST_INT + 80) +#define AU1300_TOY_MATCH0_INT (AU1300_FIRST_INT + 81) +#define AU1300_TOY_MATCH1_INT (AU1300_FIRST_INT + 82) +#define AU1300_TOY_MATCH2_INT (AU1300_FIRST_INT + 83) +#define AU1300_RTC_INT (AU1300_FIRST_INT + 84) +#define AU1300_RTC_MATCH0_INT (AU1300_FIRST_INT + 85) +#define AU1300_RTC_MATCH1_INT (AU1300_FIRST_INT + 86) +#define AU1300_RTC_MATCH2_INT (AU1300_FIRST_INT + 87) +#define AU1300_UART0_INT (AU1300_FIRST_INT + 88) +#define AU1300_SD0_INT (AU1300_FIRST_INT + 89) +#define AU1300_USB_INT (AU1300_FIRST_INT + 90) +#define AU1300_LCD_INT (AU1300_FIRST_INT + 91) +#define AU1300_BSA_INT (AU1300_FIRST_INT + 92) +#define AU1300_MPE_INT (AU1300_FIRST_INT + 93) +#define AU1300_ITE_INT (AU1300_FIRST_INT + 94) +#define AU1300_AES_INT (AU1300_FIRST_INT + 95) +#define AU1300_CIM_INT (AU1300_FIRST_INT + 96) +#define AU1300_LAST_INT AU1300_CIM_INT + +/**********************************************************************/ + /* * SDRAM register offsets */ @@ -808,6 +915,43 @@ enum soc_au1200_ints { #define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL #endif +/**********************************************************************/ + +#ifdef CONFIG_SOC_AU1300 +#define AU1300_ROM_PHYS_ADDR 0x10000000 +#define AU1300_OTP_PHYS_ADDR 0x10002000 +#define AU1300_UART0_PHYS_ADDR 0x10100000 +#define AU1300_UART1_PHYS_ADDR 0x10101000 +#define AU1300_UART2_PHYS_ADDR 0x10102000 +#define AU1300_UART3_PHYS_ADDR 0x10103000 +#define AU1300_GPIC_PHYS_ADDR 0x10200000 +#define AU1300_AES_PHYS_ADDR 0x10300000 +#define AU1300_GPU_PHYS_ADDR 0x10500000 +#define AU1300_SD0_PHYS_ADDR 0x10600000 +#define AU1300_SD1_PHYS_ADDR 0x10601000 +#define AU1300_SD2_PHYS_ADDR 0x10602000 +#define AU1300_SYS_PHYS_ADDR 0x10900000 +#define AU1300_PSC0_PHYS_ADDR 0x10A00000 +#define AU1300_PSC1_PHYS_ADDR 0x10A01000 +#define AU1300_PSC2_PHYS_ADDR 0x10A02000 +#define AU1300_PSC3_PHYS_ADDR 0x10A03000 +#define AU1300_VSS_PHYS_ADDR 0x11003000 + +#define AU1300_MEM_PHYS_ADDR 0x14000000 +#define AU1300_STATIC_PHYS_ADDR 0x14001000 +#define AU1300_UDMA_PHYS_ADDR 0x14001800 +#define AU1300_DDMA_PHYS_ADDR 0x14002000 +#define AU1300_CIM_PHYS_ADDR 0x14004000 +#define AU1300_MAEITE_PHYS_ADDR 0x14010000 +#define AU1300_MAEMPE_PHYS_ADDR 0x14014000 +#define AU1300_USB_PHYS_ADDR 0x14020000 +#define AU1300_MAEBSA_PHYS_ADDR 0x14030000 +#define AU1300_LCD_PHYS_ADDR 0x15000000 +#define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL +#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL +#define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL +#endif + /* Static Bus Controller */ #define MEM_STCFG0 0xB4001000 #define MEM_STTIME0 0xB4001004 @@ -910,6 +1054,50 @@ enum soc_au1200_ints { #define IC1_TESTBIT 0xB1800080 +/* + * Au1300 GPIO+INT controller (GPIC) register offsets and bits + */ +#define AU1300_GPIC_PINVAL 0x0000 +#define AU1300_GPIC_PINVALCLR 0x0010 +#define AU1300_GPIC_IPEND 0x0020 +#define AU1300_GPIC_PRIENC 0x0030 +#define AU1300_GPIC_IEN 0x0040 +#define AU1300_GPIC_IDIS 0x0050 +#define AU1300_GPIC_DMASEL 0x0060 +#define AU1300_GPIC_DEVSEL 0x0080 +#define AU1300_GPIC_DEVCLR 0x0090 +/* pin configuration space. one 32bit register for each gpio starting here */ +#define AU1300_GPIC_PINCFG 0x1000 + +#define AU1300_GPIO_TO_BIT(gpio) \ + ((gpio) & 0x1f) + +#define AU1300_GPIO_TO_BANK(gpio) \ + ((gpio) >> 5) + +/* Pin Control bits: who owns the pin, what does it do */ +#define GPIC_CFG_PC_GPIN 0 +#define GPIC_CFG_PC_DEV 1 +#define GPIC_CFG_PC_GPOLOW 2 +#define GPIC_CFG_PC_GPOHIGH 3 +#define GPIC_CFG_PC_MASK 3 + +/* assign pin to MIPS IRQ line */ +#define GPIC_CFG_IL_SET(x) (((x) & 3) << 2) +#define GPIC_CFG_IL_MASK (3 << 2) + +/* pin interrupt type setup */ +#define GPIC_CFG_IC_OFF (0 << 4) +#define GPIC_CFG_IC_LEVEL_LOW (1 << 4) +#define GPIC_CFG_IC_LEVEL_HIGH (2 << 4) +#define GPIC_CFG_IC_EDGE_FALL (5 << 4) +#define GPIC_CFG_IC_EDGE_RISE (6 << 4) +#define GPIC_CFG_IC_EDGE_BOTH (7 << 4) +#define GPIC_CFG_IC_MASK (7 << 4) + +/* allow interrupt to wake cpu from 'wait' */ +#define GPIC_CFG_IDLEWAKE (1 << 7) + /* Au1000 */ #ifdef CONFIG_SOC_AU1000 @@ -1008,6 +1196,7 @@ enum soc_au1200_ints { #endif /* CONFIG_SOC_AU1200 */ + /* Programmable Counters 0 and 1 */ #define SYS_BASE 0xB1900000 #define SYS_COUNTER_CNTRL (SYS_BASE + 0x14) diff --git a/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h b/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h index c098b45..5662aa7 100644 --- a/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h +++ b/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h @@ -195,6 +195,39 @@ typedef volatile struct au1xxx_ddma_desc { #define DSCR_CMD0_CIM_SYNC 26 #endif /* CONFIG_SOC_AU1200 */ +#ifdef CONFIG_SOC_AU1300 +#define DSCR_CMD0_UART0_TX 0 +#define DSCR_CMD0_UART0_RX 1 +#define DSCR_CMD0_UART1_TX 2 +#define DSCR_CMD0_UART1_RX 3 +#define DSCR_CMD0_UART2_TX 4 +#define DSCR_CMD0_UART2_RX 5 +#define DSCR_CMD0_UART3_TX 6 +#define DSCR_CMD0_UART3_RX 7 +#define DSCR_CMD0_SDMS_TX0 8 +#define DSCR_CMD0_SDMS_RX0 9 +#define DSCR_CMD0_SDMS_TX1 10 +#define DSCR_CMD0_SDMS_RX1 11 +#define DSCR_CMD0_AES_TX 12 +#define DSCR_CMD0_AES_RX 13 +#define DSCR_CMD0_PSC0_TX 14 +#define DSCR_CMD0_PSC0_RX 15 +#define DSCR_CMD0_PSC1_TX 16 +#define DSCR_CMD0_PSC1_RX 17 +#define DSCR_CMD0_PSC2_TX 18 +#define DSCR_CMD0_PSC2_RX 19 +#define DSCR_CMD0_PSC3_TX 20 +#define DSCR_CMD0_PSC3_RX 21 +#define DSCR_CMD0_LCD 22 +#define DSCR_CMD0_NAND_FLASH 23 +#define DSCR_CMD0_SDMS_TX2 24 +#define DSCR_CMD0_SDMS_RX2 25 +#define DSCR_CMD0_CIM_SYNC 26 +#define DSCR_CMD0_UDMA 27 +#define DSCR_CMD0_DMA_REQ0 28 +#define DSCR_CMD0_DMA_REQ1 29 +#endif /* CONFIG_SOC_AU1300 */ + #define DSCR_CMD0_THROTTLE 30 #define DSCR_CMD0_ALWAYS 31 #define DSCR_NDEV_IDS 32 diff --git a/arch/mips/include/asm/mach-au1x00/gpio-au1300.h b/arch/mips/include/asm/mach-au1x00/gpio-au1300.h new file mode 100644 index 0000000..76e2ff1 --- /dev/null +++ b/arch/mips/include/asm/mach-au1x00/gpio-au1300.h @@ -0,0 +1,211 @@ +/* + * gpio-au1300.h -- inlinable GPIO control for Au1300 + * + * Copyright (c) 2009 Manuel Lauss + */ + +#ifndef _GPIO_AU1300_H_ +#define _GPIO_AU1300_H_ + +#include +#include +#include + +/* 75 GPIOs in one block, yay! */ +#define AU1300_GPIO_BASE 0 +#define AU1300_GPIO_NUM 75 +#define AU1300_GPIO_MAX (AU1300_GPIO_BASE + AU1300_GPIO_NUM - 1) + +#define AU1300_GPIC_ADDR \ + (void __iomem *)KSEG1ADDR(AU1300_GPIC_PHYS_ADDR) + +static inline int au1300_gpio_get_value(int gpio) +{ + void __iomem *roff; + int bit; + + gpio -= AU1300_GPIO_BASE; + + bit = 1 << AU1300_GPIO_TO_BIT(gpio); + roff = AU1300_GPIC_ADDR; + roff += (AU1300_GPIO_TO_BANK(gpio) * 4); + return __raw_readl(roff + AU1300_GPIC_PINVAL) & bit; +} + +static inline int au1300_gpio_direction_input(int gpio) +{ + unsigned long bit; + void __iomem *roff; + + gpio -= AU1300_GPIO_BASE; + + roff = AU1300_GPIC_ADDR; + roff += AU1300_GPIO_TO_BANK(gpio) * 4; + bit = 1 << AU1300_GPIO_TO_BIT(gpio); + __raw_writel(bit, roff + AU1300_GPIC_DEVCLR); + wmb(); + + return 0; +} + +static inline int au1300_gpio_set_value(int gpio, int v) +{ + unsigned long bit; + void __iomem *roff; + + gpio -= AU1300_GPIO_BASE; + + /* bah das ist viel zu kompliziert. Wie waers mit einem + * registersatz in den ich einfach die nummer des pins, den + * ich manipulieren moechte, hineinschreibe? Oder noch + * besser, neue cpu opcodes fuer gpio: + * agsol a0 ("alchemy set gpio output low" a0 = gpio pin nummer) + * agsoh a0 ( ditto fuer set high ) + * agso a0, a1 (set gpio output, a1 = level) + * agg a0 ( get gpio ) + * agsi a0 ( set gpio to input ) + * keinen MIPS CPx dafuer, gleicher schmarrn. + */ + roff = AU1300_GPIC_ADDR; + roff += AU1300_GPIO_TO_BANK(gpio) * 4; + roff += (v) ? AU1300_GPIC_PINVAL : AU1300_GPIC_PINVALCLR; + bit = 1 << AU1300_GPIO_TO_BIT(gpio); + __raw_writel(bit, roff); + wmb(); + + return 0; +} + +static inline int au1300_gpio_direction_output(int gpio, int v) +{ + /* hw switches to output automatically */ + return au1300_gpio_set_value(gpio, v); +} + +static inline int au1300_gpio_to_irq(int gpio) +{ + return AU1300_FIRST_INT + (gpio - AU1300_GPIO_BASE); +} + +static inline int au1300_irq_to_gpio(int irq) +{ + return (irq - AU1300_FIRST_INT) + AU1300_GPIO_BASE; +} + +static inline int au1300_gpio_is_valid(int gpio) +{ + return ((gpio >= AU1300_GPIO_BASE) && (gpio <= AU1300_GPIO_MAX)); +} + +static inline int au1300_gpio_cansleep(int gpio) +{ + return 0; +} + +static inline void alchemy_gpio1_input_enable(void) +{} + +/**********************************************************************/ + +/* Linux gpio framework integration. +* +* 4 use cases of Alchemy GPIOS: +*(1) GPIOLIB=y, ALCHEMY_GPIO_INDIRECT=y: +* Board must register gpiochips. +*(2) GPIOLIB=y, ALCHEMY_GPIO_INDIRECT=n: +* A gpiochip for the 75 GPIOs is registered. +* +*(3) GPIOLIB=n, ALCHEMY_GPIO_INDIRECT=y: +* the boards' gpio.h must provide the linux gpio wrapper functions, +* +*(4) GPIOLIB=n, ALCHEMY_GPIO_INDIRECT=n: +* inlinable gpio functions are provided which enable access to the +* Au1300 gpios only by using the numbers straight out of the data- +* sheets. + +* Cases 1 and 3 are intended for boards which want to provide their own +* GPIO namespace and -operations (i.e. for example you have 8 GPIOs +* which are in part provided by spare Au1300 GPIO pins and in part by +* an external FPGA but you still want them to be accssible in linux +* as gpio0-7. The board can of course use the alchemy_gpioX_* functions +* as required). +*/ + +#ifndef CONFIG_GPIOLIB + + +#ifndef CONFIG_ALCHEMY_GPIO_INDIRECT /* case (4) */ + +static inline int gpio_direction_input(int gpio) +{ + return au1300_gpio_direction_input(gpio); +} + +static inline int gpio_direction_output(int gpio, int v) +{ + return au1300_gpio_direction_output(gpio, v); +} + +static inline int gpio_get_value(int gpio) +{ + return au1300_gpio_get_value(gpio); +} + +static inline void gpio_set_value(int gpio, int v) +{ + au1300_gpio_set_value(gpio, v); +} + +static inline int gpio_is_valid(int gpio) +{ + return au1300_gpio_is_valid(gpio); +} + +static inline int gpio_cansleep(int gpio) +{ + return au1300_gpio_cansleep(gpio); +} + +static inline int gpio_to_irq(int gpio) +{ + return au1300_gpio_to_irq(gpio); +} + +static inline int irq_to_gpio(int irq) +{ + return au1300_irq_to_gpio(irq); +} + +static inline int gpio_request(unsigned gpio, const char *label) +{ + return 0; +} + +static inline void gpio_free(unsigned gpio) +{ +} + +#endif /* !CONFIG_ALCHEMY_GPIO_INDIRECT */ + + +#else /* CONFIG GPIOLIB */ + + +/* using gpiolib to provide up to 2 gpio_chips for on-chip gpios */ +#ifndef CONFIG_ALCHEMY_GPIO_INDIRECT /* case (2) */ + +/* get everything through gpiolib */ +#define gpio_to_irq __gpio_to_irq +#define gpio_get_value __gpio_get_value +#define gpio_set_value __gpio_set_value +#define gpio_cansleep __gpio_cansleep +#define irq_to_gpio au1300_irq_to_gpio + +#include + +#endif /* !CONFIG_ALCHEMY_GPIO_INDIRECT */ + + +#endif /* !CONFIG_GPIOLIB */ + +#endif /* _GPIO_AU1300_H_ */ diff --git a/arch/mips/include/asm/mach-au1x00/gpio.h b/arch/mips/include/asm/mach-au1x00/gpio.h index f9b7d41..8bd5de8 100644 --- a/arch/mips/include/asm/mach-au1x00/gpio.h +++ b/arch/mips/include/asm/mach-au1x00/gpio.h @@ -5,6 +5,10 @@ #include +#elif defined(CONFIG_SOC_AU1300) + +#include + #endif #endif /* _ALCHEMY_GPIO_H_ */ diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index 7a51866..0b2607a 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -802,6 +802,21 @@ static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu) } } +static inline void cpu_probe_rmi(struct cpuinfo_mips *c, int cpu) +{ + decode_configs(c); + + switch (c->processor_id & 0xff00) { + case PRID_IMP_AU13XX: + c->cputype = CPU_ALCHEMY; + __cpu_name[cpu] = "Au13xx"; + break; + default: + panic("Unknown RMI core!\n"); + break; + } +} + static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu) { decode_configs(c); @@ -936,6 +951,9 @@ __cpuinit void cpu_probe(void) case PRID_COMP_NXP: cpu_probe_nxp(c, cpu); break; + case PRID_COMP_RMI: + cpu_probe_rmi(c, cpu); + break; case PRID_COMP_CAVIUM: cpu_probe_cavium(c, cpu); break; diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig index 737335f..17efcc7 100644 --- a/drivers/i2c/busses/Kconfig +++ b/drivers/i2c/busses/Kconfig @@ -294,7 +294,7 @@ config I2C_AT91 config I2C_AU1550 tristate "Au1550/Au1200 SMBus interface" - depends on SOC_AU1550 || SOC_AU1200 + depends on SOC_AU1550 || SOC_AU1200 || SOC_AU1300 help If you say yes to this option, support will be included for the Au1550 and Au1200 SMBus interface. diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 4b6f7cb..ed6b082 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -68,7 +68,7 @@ config SPI_BFIN config SPI_AU1550 tristate "Au1550/Au12x0 SPI Controller" - depends on (SOC_AU1550 || SOC_AU1200) && EXPERIMENTAL + depends on (SOC_AU1550 || SOC_AU1200 || SOC_AU1300) && EXPERIMENTAL select SPI_BITBANG help If you say yes to this option, support will be included for the diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index 9bbb285..df075da 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -1662,15 +1662,15 @@ config FB_AU1100 au1100fb:panel=. config FB_AU1200 - bool "Au1200 LCD Driver" - depends on (FB = y) && MIPS && SOC_AU1200 + bool "Au1200/Au1300 LCD Driver" + depends on (FB = y) && (SOC_AU1200 || SOC_AU1300) select FB_CFB_FILLRECT select FB_CFB_COPYAREA select FB_CFB_IMAGEBLIT help - This is the framebuffer driver for the AMD Au1200 SOC. It can drive - various panels and CRTs by passing in kernel cmd line option - au1200fb:panel=. + This is the framebuffer driver for the AMD Au1200/Au1300 SOCs. + It can drive various panels and CRTs by passing in kernel + cmdline option au1200fb:panel=. source "drivers/video/geode/Kconfig" -- 1.6.5.2 From manuel.lauss@googlemail.com Tue Nov 3 20:27:48 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 03 Nov 2009 20:27:56 +0100 (CET) Received: from mail-ew0-f216.google.com ([209.85.219.216]:58380 "EHLO mail-ew0-f216.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1494033AbZKCT1H (ORCPT ); Tue, 3 Nov 2009 20:27:07 +0100 Received: by ewy12 with SMTP id 12so963691ewy.0 for ; Tue, 03 Nov 2009 11:27:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer:in-reply-to:references; bh=rEWDKg/mBKnELbegnCjBiJ+qRDLGSTfHVX56k/Bm2s0=; b=oh0hl7LQaljLmsiOqzVbi59mBD5LoplyAjybGnnrXWgsYHyw0BfavAepkQcUzbCZfA afcD4es/tKJhC0i7xmgf2lqQv/WHUzCpVLLuI9V56ya+heCFknfK4vZaEdx/NFRH9qTA qHYpavvsAllg8V/OgRo/mC2XJMSZTu25ffUV8= DomainKey-Signature: a=rsa-sha1; c=nofws; d=googlemail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; b=QA7G6Inzn8NGJSLfbUd2fCMFEdGeOKR83tMwXbOf9NVHY99HUBOz2Ei9+WPkVzSVDx NdXlIAILyVCK1LMmqYCzkZsGUCG/SlHZX3uj63AhT1lvkzLY3x4Gxhi/GTmhX/a0AtZO qFQq/fyfiCkKcWhRONHvYJkP7ufUun80d/6Tg= Received: by 10.216.87.143 with SMTP id y15mr209938wee.39.1257276422115; Tue, 03 Nov 2009 11:27:02 -0800 (PST) Received: from localhost.localdomain (p5496F342.dip.t-dialin.net [84.150.243.66]) by mx.google.com with ESMTPS id p10sm1157027gvf.29.2009.11.03.11.27.00 (version=TLSv1/SSLv3 cipher=RC4-MD5); Tue, 03 Nov 2009 11:27:01 -0800 (PST) From: Manuel Lauss To: Linux-MIPS Cc: Kevin Hickey , Manuel Lauss Subject: [RFC PATCH -queue 2/2] Alchemy: DB1300 support. Date: Tue, 3 Nov 2009 20:27:03 +0100 Message-Id: <1257276423-26413-3-git-send-email-manuel.lauss@gmail.com> X-Mailer: git-send-email 1.6.5.2 In-Reply-To: <1257276423-26413-2-git-send-email-manuel.lauss@gmail.com> References: <1257276423-26413-1-git-send-email-manuel.lauss@gmail.com> <1257276423-26413-2-git-send-email-manuel.lauss@gmail.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24652 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips VERY basic DB1300 board support, WORK IN PROGRESS --- arch/mips/Makefile | 7 + arch/mips/alchemy/Kconfig | 8 + arch/mips/alchemy/devboards/Makefile | 1 + arch/mips/alchemy/devboards/db1300/Makefile | 2 + arch/mips/alchemy/devboards/db1300/platform.c | 234 +++++ arch/mips/alchemy/devboards/db1300/setup.c | 158 ++++ arch/mips/alchemy/devboards/prom.c | 4 + arch/mips/configs/db1300_defconfig | 1160 +++++++++++++++++++++++++ arch/mips/include/asm/mach-db1x00/bcsr.h | 3 + arch/mips/include/asm/mach-db1x00/db1300.h | 37 + drivers/pcmcia/db1xxx_ss.c | 14 +- 11 files changed, 1626 insertions(+), 2 deletions(-) create mode 100644 arch/mips/alchemy/devboards/db1300/Makefile create mode 100644 arch/mips/alchemy/devboards/db1300/platform.c create mode 100644 arch/mips/alchemy/devboards/db1300/setup.c create mode 100644 arch/mips/configs/db1300_defconfig create mode 100644 arch/mips/include/asm/mach-db1x00/db1300.h diff --git a/arch/mips/Makefile b/arch/mips/Makefile index 77f5021..f40eda4 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -266,6 +266,13 @@ cflags-$(CONFIG_MIPS_DB1200) += -I$(srctree)/arch/mips/include/asm/mach-db1x00 load-$(CONFIG_MIPS_DB1200) += 0xffffffff80100000 # +# RMI DBAu1300 development platform +# +core-$(CONFIG_MIPS_DB1300) += arch/mips/alchemy/devboards/ +cflags-$(CONFIG_MIPS_DB1300) += -I$(srctree)/arch/mips/include/asm/mach-db1x00 +load-$(CONFIG_MIPS_DB1300) += 0xffffffff80100000 + +# # AMD Alchemy Bosporus eval board # core-$(CONFIG_MIPS_BOSPORUS) += arch/mips/alchemy/devboards/ diff --git a/arch/mips/alchemy/Kconfig b/arch/mips/alchemy/Kconfig index 478699e..2478d7b 100644 --- a/arch/mips/alchemy/Kconfig +++ b/arch/mips/alchemy/Kconfig @@ -56,6 +56,14 @@ config MIPS_DB1200 select SYS_SUPPORTS_LITTLE_ENDIAN select SYS_HAS_EARLY_PRINTK +config MIPS_DB1300 + bool "RMI DB1300 board" + select SOC_AU1300 + select DMA_COHERENT + select MIPS_DISABLE_OBSOLETE_IDE + select SYS_SUPPORTS_LITTLE_ENDIAN + select SYS_HAS_EARLY_PRINTK + config MIPS_DB1500 bool "Alchemy DB1500 board" select SOC_AU1500 diff --git a/arch/mips/alchemy/devboards/Makefile b/arch/mips/alchemy/devboards/Makefile index ecbd37f..b6e9465 100644 --- a/arch/mips/alchemy/devboards/Makefile +++ b/arch/mips/alchemy/devboards/Makefile @@ -16,5 +16,6 @@ obj-$(CONFIG_MIPS_DB1500) += db1x00/ obj-$(CONFIG_MIPS_DB1550) += db1x00/ obj-$(CONFIG_MIPS_BOSPORUS) += db1x00/ obj-$(CONFIG_MIPS_MIRAGE) += db1x00/ +obj-$(CONFIG_MIPS_DB1300) += db1300/ EXTRA_CFLAGS += -Werror diff --git a/arch/mips/alchemy/devboards/db1300/Makefile b/arch/mips/alchemy/devboards/db1300/Makefile new file mode 100644 index 0000000..3d74c2f --- /dev/null +++ b/arch/mips/alchemy/devboards/db1300/Makefile @@ -0,0 +1,2 @@ +obj-y := setup.o platform.o + diff --git a/arch/mips/alchemy/devboards/db1300/platform.c b/arch/mips/alchemy/devboards/db1300/platform.c new file mode 100644 index 0000000..e276fdf --- /dev/null +++ b/arch/mips/alchemy/devboards/db1300/platform.c @@ -0,0 +1,234 @@ +/* + * DBAu1300 platform initialization + */ + +#include +#include +#include +#include /* KEY_* codes */ +#include +#include +#include + +#include +#include +#include +#include +#include + +#include "../platform.h" + +static struct resource db1300_eth_res[] = { + [0] = { + .start = DB1300_ETH_PHYS_ADDR, + .end = DB1300_ETH_PHYS_END, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = DB1300_ETH_INT, + .end = DB1300_ETH_INT, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct smsc911x_platform_config db1300_eth_config = { + .phy_interface = PHY_INTERFACE_MODE_MII, + .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW, + .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL, + .flags = SMSC911X_USE_32BIT, +}; + +static struct platform_device db1300_eth_dev = { + .name = "smsc911x", + .id = -1, + .num_resources = ARRAY_SIZE(db1300_eth_res), + .resource = db1300_eth_res, + .dev = { + .platform_data = &db1300_eth_config, + }, +}; + +static struct resource au1300_psc1_res[] = { + [0] = { + .start = AU1300_PSC1_PHYS_ADDR, + .end = AU1300_PSC1_PHYS_ADDR + 0x0fff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AU1300_PSC1_INT, + .end = AU1300_PSC1_INT, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = DSCR_CMD0_PSC1_TX, + .end = DSCR_CMD0_PSC1_TX, + .flags = IORESOURCE_DMA, + }, + [3] = { + .start = DSCR_CMD0_PSC1_RX, + .end = DSCR_CMD0_PSC1_RX, + .flags = IORESOURCE_DMA, + }, +}; + +static struct platform_device db1300_ac97_dev = { + .name = "au1xpsc_ac97", + .id = 0, + .num_resources = ARRAY_SIZE(au1300_psc1_res), + .resource = au1300_psc1_res, +}; + +static struct resource au1300_psc2_res[] = { + [0] = { + .start = AU1300_PSC2_PHYS_ADDR, + .end = AU1300_PSC2_PHYS_ADDR + 0x0fff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AU1300_PSC2_INT, + .end = AU1300_PSC2_INT, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = DSCR_CMD0_PSC2_TX, + .end = DSCR_CMD0_PSC2_TX, + .flags = IORESOURCE_DMA, + }, + [3] = { + .start = DSCR_CMD0_PSC2_RX, + .end = DSCR_CMD0_PSC2_RX, + .flags = IORESOURCE_DMA, + }, +}; + +static struct platform_device db1300_i2s_dev = { + .name = "au1xpsc_i2s", + .id = 1, + .num_resources = ARRAY_SIZE(au1300_psc2_res), + .resource = au1300_psc2_res, +}; + +static struct resource au1300_psc3_res[] = { + [0] = { + .start = AU1300_PSC3_PHYS_ADDR, + .end = AU1300_PSC3_PHYS_ADDR + 0x0fff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AU1300_PSC3_INT, + .end = AU1300_PSC3_INT, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = DSCR_CMD0_PSC3_TX, + .end = DSCR_CMD0_PSC3_TX, + .flags = IORESOURCE_DMA, + }, + [3] = { + .start = DSCR_CMD0_PSC3_RX, + .end = DSCR_CMD0_PSC3_RX, + .flags = IORESOURCE_DMA, + }, +}; + +static struct platform_device db1300_i2c_dev = { + .name = "au1xpsc_smbus", + .id = 0, /* bus number */ + .num_resources = ARRAY_SIZE(au1300_psc3_res), + .resource = au1300_psc3_res, +}; + +/* FIXME: keys not yet correctly assigned. orientation: from display */ +static struct gpio_keys_button db1300_5waysw_buttons[] = { + { + .code = KEY_UP, + .gpio = AU1300_PIN_LCDPWM0, + .type = EV_KEY, + .debounce_interval = 1, + }, + { + .code = KEY_DOWN, + .gpio = AU1300_PIN_PSC2SYNC1, + .type = EV_KEY, + .debounce_interval = 1, + }, + { + .code = KEY_LEFT, + .gpio = AU1300_PIN_WAKE1, + .type = EV_KEY, + .debounce_interval = 1, + }, + { + .code = KEY_RIGHT, + .gpio = AU1300_PIN_WAKE2, + .type = EV_KEY, + .debounce_interval = 1, + }, + { + .code = KEY_ENTER, + .gpio = AU1300_PIN_WAKE3, + .type = EV_KEY, + .debounce_interval = 1, + }, +}; + +static struct gpio_keys_platform_data db1300_5waysw_data = { + .buttons = db1300_5waysw_buttons, + .nbuttons = ARRAY_SIZE(db1300_5waysw_buttons), + .rep = 1, +}; + +static struct platform_device db1300_5waysw_dev = { + .name = "gpio_keys", + .dev = { + .platform_data = &db1300_5waysw_data, + }, +}; + +static struct platform_device *db1300_devs[] = { + &db1300_eth_dev, + &db1300_i2c_dev, + &db1300_ac97_dev, + &db1300_i2s_dev, + &db1300_5waysw_dev, +}; + +static int __init db1300_device_init(void) +{ + int swapped; + + /* Audio PSC clock is supplied by codecs (PSC0, 1) */ + __raw_writel(PSC_SEL_CLK_SERCLK, + (void __iomem *)KSEG1ADDR(AU1300_PSC0_PHYS_ADDR) + PSC_SEL_OFFSET); + __raw_writel(PSC_SEL_CLK_SERCLK, + (void __iomem *)KSEG1ADDR(AU1300_PSC1_PHYS_ADDR) + PSC_SEL_OFFSET); + wmb(); + + swapped = bcsr_read(BCSR_STATUS) & BCSR_STATUS_DB1200_SWAPBOOT; + db1x_register_norflash(64 * 1024 * 1024, 2, swapped); + + return platform_add_devices(db1300_devs, ARRAY_SIZE(db1300_devs)); +} +device_initcall(db1300_device_init); + +/* au1200fb calls these: STERBT EINEN TRAGISCHEN TOD!!! */ +int board_au1200fb_panel(void) +{ + return (bcsr_read(BCSR_SWITCHES) >> 8) & 0x0f; +} + +int board_au1200fb_panel_init(void) +{ + /* Apply power */ + bcsr_mod(BCSR_BOARD, 0, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD | + BCSR_BOARD_LCDBL); + return 0; +} + +int board_au1200fb_panel_shutdown(void) +{ + /* Remove power */ + bcsr_mod(BCSR_BOARD, BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD | + BCSR_BOARD_LCDBL, 0); + return 0; +} diff --git a/arch/mips/alchemy/devboards/db1300/setup.c b/arch/mips/alchemy/devboards/db1300/setup.c new file mode 100644 index 0000000..60b6430 --- /dev/null +++ b/arch/mips/alchemy/devboards/db1300/setup.c @@ -0,0 +1,158 @@ +/* + * DB1300 board setup + * + * Copyright (c) 2009 Manuel Lauss + */ + +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +/* multifunction pins to assign to GPIO controller */ +static int db1300_gpio_pins[] __initdata = { + AU1300_PIN_LCDPWM0, AU1300_PIN_PSC2SYNC1, AU1300_PIN_WAKE1, + AU1300_PIN_WAKE2, AU1300_PIN_WAKE3, AU1300_PIN_FG3AUX, + AU1300_PIN_EXTCLK1, + + -1, /* terminator */ +}; + +/* multifunction pins to assign to device functions */ +static int db1300_dev_pins[] __initdata = { + /* wake-from-str pins 0-3 */ + AU1300_PIN_WAKE0, + /* external clock sources for PSC0 */ + AU1300_PIN_EXTCLK0, + /* 8bit MMC interface on SD0: 6-9 */ + AU1300_PIN_SD0DAT4, AU1300_PIN_SD0DAT5, AU1300_PIN_SD0DAT6, + AU1300_PIN_SD0DAT7, + /* UART1 pins: 11-18 */ + AU1300_PIN_U1RI, AU1300_PIN_U1DCD, AU1300_PIN_U1DSR, + AU1300_PIN_U1CTS, AU1300_PIN_U1RTS, AU1300_PIN_U1DTR, + AU1300_PIN_U1RX, AU1300_PIN_U1TX, + /* UART0 pins: 19-24 */ + AU1300_PIN_U0RI, AU1300_PIN_U0DCD, AU1300_PIN_U0DSR, + AU1300_PIN_U0CTS, AU1300_PIN_U0RTS, AU1300_PIN_U0DTR, + /* UART2: 25-26 */ + AU1300_PIN_U2RX, AU1300_PIN_U2TX, + /* UART3: 27-28 */ + AU1300_PIN_U3RX, AU1300_PIN_U3TX, + /* LCD controller PWMs, ext pixclock: 30-31 */ + AU1300_PIN_LCDPWM1, AU1300_PIN_LCDCLKIN, + /* SD1 interface: 32-37 */ + AU1300_PIN_SD1DAT0, AU1300_PIN_SD1DAT1, AU1300_PIN_SD1DAT2, + AU1300_PIN_SD1DAT3, AU1300_PIN_SD1CMD, AU1300_PIN_SD1CLK, + /* SD2 interface: 38-43 */ + AU1300_PIN_SD2DAT0, AU1300_PIN_SD2DAT1, AU1300_PIN_SD2DAT2, + AU1300_PIN_SD2DAT3, AU1300_PIN_SD2CMD, AU1300_PIN_SD2CLK, + /* PSC0/1 clocks: 44-45 */ + AU1300_PIN_PSC0CLK, AU1300_PIN_PSC1CLK, + /* PSCs: 46-49/50-53/54-57/58-61 */ + AU1300_PIN_PSC0SYNC0, AU1300_PIN_PSC0SYNC1, AU1300_PIN_PSC0D0, + AU1300_PIN_PSC0D1, + AU1300_PIN_PSC1SYNC0, AU1300_PIN_PSC1SYNC1, AU1300_PIN_PSC1D0, + AU1300_PIN_PSC1D1, + AU1300_PIN_PSC2SYNC0, AU1300_PIN_PSC2D0, + AU1300_PIN_PSC2D1, + AU1300_PIN_PSC3SYNC0, AU1300_PIN_PSC3SYNC1, AU1300_PIN_PSC3D0, + AU1300_PIN_PSC3D1, + /* PCMCIA interface: 62-70 */ + AU1300_PIN_PCE2, AU1300_PIN_PCE1, AU1300_PIN_PIOS16, + AU1300_PIN_PIOR, AU1300_PIN_PWE, AU1300_PIN_PWAIT, + AU1300_PIN_PREG, AU1300_PIN_POE, AU1300_PIN_PIOW, + /* camera interface H/V sync inputs: 71-72 */ + AU1300_PIN_CIMLS, AU1300_PIN_CIMFS, + /* PSC2/3 clocks: 73-74 */ + AU1300_PIN_PSC2CLK, AU1300_PIN_PSC3CLK, + -1, /* terminator */ +}; + +static void __init db1300_gpio_config(void) +{ + int *i; + + i = &db1300_dev_pins[0]; + while (*i != -1) + au1300_pinfunc_to_dev(*i++); + + i = &db1300_gpio_pins[0]; + while (*i != -1) + au1300_gpio_direction_input(*i++);/* implies pin_to_gpio */ + + au1300_set_dbdma_gpio(1, AU1300_PIN_FG3AUX); +} + +char *get_system_type(void) +{ + return "RMI DBAu1300 Development Platform"; +} + +static void board_power_off(void) +{ + bcsr_write(BCSR_RESETS, 0); + bcsr_write(BCSR_SYSTEM, BCSR_SYSTEM_PWROFF | BCSR_SYSTEM_RESET); +} + +void board_reset(void) +{ + bcsr_write(BCSR_RESETS, 0); + bcsr_write(BCSR_SYSTEM, 0); +} + +static inline void enable_uart(unsigned long phys) +{ + void __iomem *addr = (void __iomem *)KSEG1ADDR(phys); + + /* enable clock */ + __raw_writel(1, addr + 0x100); + wmb(); + /* deassert reset */ + __raw_writel(3, addr + 0x100); + wmb(); +} + +void __init board_setup(void) +{ + unsigned short whoami; + + db1300_gpio_config(); + bcsr_init(DB1300_BCSR_PHYS_ADDR, + DB1300_BCSR_PHYS_ADDR + DB1300_BCSR_HEXLED_OFS); + + whoami = bcsr_read(BCSR_WHOAMI); + printk(KERN_INFO "RMI DBAu1300 Development Platform.\n\t" + "BoardID %d CPLD Rev %d DCID %d\n", + BCSR_WHOAMI_BOARD(whoami), BCSR_WHOAMI_CPLD(whoami), + BCSR_WHOAMI_DCID(whoami)); + + /* enable UARTs, YAMON only enables #2 */ + enable_uart(AU1300_UART0_PHYS_ADDR); + enable_uart(AU1300_UART1_PHYS_ADDR); + enable_uart(AU1300_UART3_PHYS_ADDR); + + pm_power_off = board_power_off; + _machine_halt = board_power_off; + _machine_restart = (void(*)(char *))board_reset; +} + +static int __init db1300_arch_init(void) +{ + int cpldirq; + + cpldirq = au1300_gpio_to_irq(AU1300_PIN_EXTCLK1); + + set_irq_type(cpldirq, IRQF_TRIGGER_HIGH); + bcsr_init_irq(DB1300_FIRST_INT, DB1300_LAST_INT, cpldirq); + + return 0; +} +arch_initcall(db1300_arch_init); diff --git a/arch/mips/alchemy/devboards/prom.c b/arch/mips/alchemy/devboards/prom.c index b30df5c..347186f 100644 --- a/arch/mips/alchemy/devboards/prom.c +++ b/arch/mips/alchemy/devboards/prom.c @@ -63,5 +63,9 @@ void __init prom_init(void) void prom_putchar(unsigned char c) { +#ifdef CONFIG_MIPS_DB1300 + alchemy_uart_putchar(AU1300_UART2_PHYS_ADDR, c); +#else alchemy_uart_putchar(UART0_PHYS_ADDR, c); +#endif } diff --git a/arch/mips/configs/db1300_defconfig b/arch/mips/configs/db1300_defconfig new file mode 100644 index 0000000..f1224e5 --- /dev/null +++ b/arch/mips/configs/db1300_defconfig @@ -0,0 +1,1160 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.32-rc5 +# Tue Nov 3 19:14:32 2009 +# +CONFIG_MIPS=y + +# +# Machine selection +# +CONFIG_MACH_ALCHEMY=y +# CONFIG_AR7 is not set +# CONFIG_BASLER_EXCITE is not set +# CONFIG_BCM47XX is not set +# CONFIG_BCM63XX is not set +# CONFIG_MIPS_COBALT is not set +# CONFIG_MACH_DECSTATION is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_LASAT is not set +# CONFIG_MACH_LOONGSON is not set +# CONFIG_MIPS_MALTA is not set +# CONFIG_MIPS_SIM is not set +# CONFIG_NEC_MARKEINS is not set +# CONFIG_MACH_VR41XX is not set +# CONFIG_NXP_STB220 is not set +# CONFIG_NXP_STB225 is not set +# CONFIG_PNX8550_JBS is not set +# CONFIG_PNX8550_STB810 is not set +# CONFIG_PMC_MSP is not set +# CONFIG_PMC_YOSEMITE is not set +# CONFIG_SGI_IP22 is not set +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP28 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_CRHONE is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_BIGSUR is not set +# CONFIG_SNI_RM is not set +# CONFIG_MACH_TX39XX is not set +# CONFIG_MACH_TX49XX is not set +# CONFIG_MIKROTIK_RB532 is not set +# CONFIG_WR_PPMC is not set +# CONFIG_CAVIUM_OCTEON_SIMULATOR is not set +# CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD is not set +CONFIG_ALCHEMY_GPIOINT_AU1300=y +# CONFIG_ALCHEMY_GPIO_INDIRECT is not set +# CONFIG_MIPS_MTX1 is not set +# CONFIG_MIPS_BOSPORUS is not set +# CONFIG_MIPS_DB1000 is not set +# CONFIG_MIPS_DB1100 is not set +# CONFIG_MIPS_DB1200 is not set +CONFIG_MIPS_DB1300=y +# CONFIG_MIPS_DB1500 is not set +# CONFIG_MIPS_DB1550 is not set +# CONFIG_MIPS_MIRAGE is not set +# CONFIG_MIPS_PB1000 is not set +# CONFIG_MIPS_PB1100 is not set +# CONFIG_MIPS_PB1200 is not set +# CONFIG_MIPS_PB1500 is not set +# CONFIG_MIPS_PB1550 is not set +# CONFIG_MIPS_XXS1500 is not set +CONFIG_SOC_AU1300=y +CONFIG_SOC_AU1X00=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_ARCH_SUPPORTS_OPROFILE=y +CONFIG_GENERIC_FIND_NEXT_BIT=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CMOS_UPDATE=y +CONFIG_SCHED_OMIT_FRAME_POINTER=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +CONFIG_CEVT_R4K_LIB=y +CONFIG_CSRC_R4K_LIB=y +CONFIG_DMA_COHERENT=y +CONFIG_EARLY_PRINTK=y +CONFIG_SYS_HAS_EARLY_PRINTK=y +CONFIG_MIPS_DISABLE_OBSOLETE_IDE=y +# CONFIG_NO_IOPORT is not set +CONFIG_GENERIC_GPIO=y +# CONFIG_CPU_BIG_ENDIAN is not set +CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y +CONFIG_IRQ_CPU=y +CONFIG_MIPS_L1_CACHE_SHIFT=5 + +# +# CPU selection +# +# CONFIG_CPU_LOONGSON2E is not set +CONFIG_CPU_MIPS32_R1=y +# CONFIG_CPU_MIPS32_R2 is not set +# CONFIG_CPU_MIPS64_R1 is not set +# CONFIG_CPU_MIPS64_R2 is not set +# CONFIG_CPU_R3000 is not set +# CONFIG_CPU_TX39XX is not set +# CONFIG_CPU_VR41XX is not set +# CONFIG_CPU_R4300 is not set +# CONFIG_CPU_R4X00 is not set +# CONFIG_CPU_TX49XX is not set +# CONFIG_CPU_R5000 is not set +# CONFIG_CPU_R5432 is not set +# CONFIG_CPU_R5500 is not set +# CONFIG_CPU_R6000 is not set +# CONFIG_CPU_NEVADA is not set +# CONFIG_CPU_R8000 is not set +# CONFIG_CPU_R10000 is not set +# CONFIG_CPU_RM7000 is not set +# CONFIG_CPU_RM9000 is not set +# CONFIG_CPU_SB1 is not set +# CONFIG_CPU_CAVIUM_OCTEON is not set +CONFIG_SYS_HAS_CPU_MIPS32_R1=y +CONFIG_CPU_MIPS32=y +CONFIG_CPU_MIPSR1=y +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_HARDWARE_WATCHPOINTS=y + +# +# Kernel type +# +CONFIG_32BIT=y +# CONFIG_64BIT is not set +CONFIG_PAGE_SIZE_4KB=y +# CONFIG_PAGE_SIZE_8KB is not set +# CONFIG_PAGE_SIZE_16KB is not set +# CONFIG_PAGE_SIZE_32KB is not set +# CONFIG_PAGE_SIZE_64KB is not set +CONFIG_CPU_HAS_PREFETCH=y +CONFIG_MIPS_MT_DISABLED=y +# CONFIG_MIPS_MT_SMP is not set +# CONFIG_MIPS_MT_SMTC is not set +CONFIG_64BIT_PHYS_ADDR=y +CONFIG_CPU_HAS_SYNC=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_CPU_SUPPORTS_HIGHMEM=y +CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_ARCH_POPULATES_NODE_MAP=y +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=0 +CONFIG_VIRT_TO_BUS=y +CONFIG_HAVE_MLOCK=y +CONFIG_HAVE_MLOCKED_PAGE_BIT=y +# CONFIG_KSM is not set +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +# CONFIG_HZ_48 is not set +CONFIG_HZ_100=y +# CONFIG_HZ_128 is not set +# CONFIG_HZ_250 is not set +# CONFIG_HZ_256 is not set +# CONFIG_HZ_1000 is not set +# CONFIG_HZ_1024 is not set +CONFIG_SYS_SUPPORTS_ARBIT_HZ=y +CONFIG_HZ=100 +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set +# CONFIG_PREEMPT is not set +# CONFIG_KEXEC is not set +# CONFIG_SECCOMP is not set +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_CONSTRUCTORS=y + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="-db1300" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_POSIX_MQUEUE=y +CONFIG_POSIX_MQUEUE_SYSCTL=y +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_AUDIT is not set + +# +# RCU Subsystem +# +CONFIG_TREE_RCU=y +# CONFIG_TREE_PREEMPT_RCU is not set +# CONFIG_RCU_TRACE is not set +CONFIG_RCU_FANOUT=4 +CONFIG_RCU_FANOUT_EXACT=y +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=17 +# CONFIG_GROUP_SCHED is not set +# CONFIG_CGROUPS is not set +# CONFIG_SYSFS_DEPRECATED_V2 is not set +# CONFIG_RELAY is not set +# CONFIG_NAMESPACES is not set +# CONFIG_BLK_DEV_INITRD is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +CONFIG_EMBEDDED=y +# CONFIG_SYSCTL_SYSCALL is not set +CONFIG_KALLSYMS=y +CONFIG_KALLSYMS_ALL=y +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +# CONFIG_PCSPKR_PLATFORM is not set +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y + +# +# Kernel Performance Events And Counters +# +# CONFIG_VM_EVENT_COUNTERS is not set +# CONFIG_SLUB_DEBUG is not set +CONFIG_COMPAT_BRK=y +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +CONFIG_HAVE_OPROFILE=y + +# +# GCOV-based kernel profiling +# +# CONFIG_SLOW_WORK is not set +# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_BLOCK=y +# CONFIG_LBDAF is not set +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +# CONFIG_IOSCHED_AS is not set +# CONFIG_IOSCHED_DEADLINE is not set +# CONFIG_IOSCHED_CFQ is not set +# CONFIG_DEFAULT_AS is not set +# CONFIG_DEFAULT_DEADLINE is not set +# CONFIG_DEFAULT_CFQ is not set +CONFIG_DEFAULT_NOOP=y +CONFIG_DEFAULT_IOSCHED="noop" +# CONFIG_FREEZER is not set + +# +# Bus options (PCI, PCMCIA, EISA, ISA, TC) +# +# CONFIG_ARCH_SUPPORTS_MSI is not set +CONFIG_MMU=y +CONFIG_PCCARD=y +# CONFIG_PCMCIA_DEBUG is not set +CONFIG_PCMCIA=y +CONFIG_PCMCIA_LOAD_CIS=y +# CONFIG_PCMCIA_IOCTL is not set + +# +# PC-card bridges +# +# CONFIG_PCMCIA_AU1X00 is not set +CONFIG_PCMCIA_ALCHEMY_DEVBOARD=y + +# +# Executable file formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set +# CONFIG_BINFMT_MISC is not set +CONFIG_TRAD_SIGNALS=y + +# +# Power management options +# +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +# CONFIG_PM is not set +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_PACKET_MMAP=y +CONFIG_UNIX=y +# CONFIG_NET_KEY is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +# CONFIG_IP_PNP_BOOTP is not set +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_IP_MROUTE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +CONFIG_INET_LRO=y +# CONFIG_INET_DIAG is not set +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +# CONFIG_IPV6 is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_RDS is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_PHONET is not set +# CONFIG_IEEE802154 is not set +# CONFIG_NET_SCHED is not set +# CONFIG_DCB is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set +# CONFIG_WIRELESS is not set +# CONFIG_WIMAX is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +# CONFIG_DEVTMPFS is not set +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_CONNECTOR is not set +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_TESTS is not set +# CONFIG_MTD_CONCAT is not set +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_AR7_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_MTD_OOPS is not set + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=y +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_GEN_PROBE=y +# CONFIG_MTD_CFI_ADV_OPTIONS is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_CFI_INTELEXT is not set +CONFIG_MTD_CFI_AMDSTD=y +# CONFIG_MTD_CFI_STAA is not set +CONFIG_MTD_CFI_UTIL=y +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +CONFIG_MTD_PHYSMAP=y +# CONFIG_MTD_PHYSMAP_COMPAT is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_DATAFLASH is not set +# CONFIG_MTD_M25P80 is not set +# CONFIG_MTD_SST25L is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +CONFIG_MTD_NAND=y +# CONFIG_MTD_NAND_VERIFY_WRITE is not set +# CONFIG_MTD_NAND_ECC_SMC is not set +# CONFIG_MTD_NAND_MUSEUM_IDS is not set +CONFIG_MTD_NAND_IDS=y +# CONFIG_MTD_NAND_DISKONCHIP is not set +# CONFIG_MTD_NAND_NANDSIM is not set +CONFIG_MTD_NAND_PLATFORM=y +# CONFIG_MTD_ONENAND is not set + +# +# LPDDR flash memory drivers +# +# CONFIG_MTD_LPDDR is not set + +# +# UBI - Unsorted block images +# +# CONFIG_MTD_UBI is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=y +# CONFIG_BLK_DEV_CRYPTOLOOP is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_RAM is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +# CONFIG_BLK_DEV_HD is not set +# CONFIG_MISC_DEVICES is not set +CONFIG_HAVE_IDE=y +CONFIG_IDE=y + +# +# Please see Documentation/ide/ide.txt for help/info on IDE drives +# +# CONFIG_BLK_DEV_IDE_SATA is not set +CONFIG_IDE_GD=y +CONFIG_IDE_GD_ATA=y +# CONFIG_IDE_GD_ATAPI is not set +CONFIG_BLK_DEV_IDECS=y +# CONFIG_BLK_DEV_IDECD is not set +# CONFIG_BLK_DEV_IDETAPE is not set +CONFIG_IDE_TASK_IOCTL=y +# CONFIG_IDE_PROC_FS is not set + +# +# IDE chipset support/bugfixes +# +# CONFIG_IDE_GENERIC is not set +# CONFIG_BLK_DEV_PLATFORM is not set +# CONFIG_BLK_DEV_IDEDMA is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +# CONFIG_SCSI is not set +# CONFIG_SCSI_DMA is not set +# CONFIG_SCSI_NETLINK is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_VETH is not set +CONFIG_PHYLIB=y + +# +# MII PHY device drivers +# +# CONFIG_MARVELL_PHY is not set +# CONFIG_DAVICOM_PHY is not set +# CONFIG_QSEMI_PHY is not set +# CONFIG_LXT_PHY is not set +# CONFIG_CICADA_PHY is not set +# CONFIG_VITESSE_PHY is not set +CONFIG_SMSC_PHY=y +# CONFIG_BROADCOM_PHY is not set +# CONFIG_ICPLUS_PHY is not set +# CONFIG_REALTEK_PHY is not set +# CONFIG_NATIONAL_PHY is not set +# CONFIG_STE10XP is not set +# CONFIG_LSI_ET1011C_PHY is not set +# CONFIG_FIXED_PHY is not set +# CONFIG_MDIO_BITBANG is not set +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +# CONFIG_AX88796 is not set +# CONFIG_MIPS_AU1X00_ENET is not set +# CONFIG_SMC91X is not set +# CONFIG_DM9000 is not set +# CONFIG_ENC28J60 is not set +# CONFIG_ETHOC is not set +CONFIG_SMSC911X=y +# CONFIG_DNET is not set +# CONFIG_IBM_NEW_EMAC_ZMII is not set +# CONFIG_IBM_NEW_EMAC_RGMII is not set +# CONFIG_IBM_NEW_EMAC_TAH is not set +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set +# CONFIG_B44 is not set +# CONFIG_KS8842 is not set +# CONFIG_KS8851 is not set +# CONFIG_KS8851_MLL is not set +# CONFIG_NETDEV_1000 is not set +# CONFIG_NETDEV_10000 is not set +# CONFIG_WLAN is not set + +# +# Enable WiMAX (Networking options) to see the WiMAX drivers +# +# CONFIG_NET_PCMCIA is not set +# CONFIG_WAN is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_ISDN is not set +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set + +# +# Userland interfaces +# +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +# CONFIG_KEYBOARD_ADP5588 is not set +# CONFIG_KEYBOARD_ATKBD is not set +# CONFIG_QT2160 is not set +# CONFIG_KEYBOARD_LKKBD is not set +CONFIG_KEYBOARD_GPIO=y +# CONFIG_KEYBOARD_MATRIX is not set +# CONFIG_KEYBOARD_MAX7359 is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_OPENCORES is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_XTKBD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +CONFIG_INPUT_MISC=y +CONFIG_INPUT_UINPUT=y +# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_DEVKMEM=y +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +# CONFIG_SERIAL_8250_CS is not set +CONFIG_SERIAL_8250_NR_UARTS=4 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +# CONFIG_SERIAL_8250_EXTENDED is not set +CONFIG_SERIAL_8250_AU1X00=y + +# +# Non-8250 serial port support +# +# CONFIG_SERIAL_MAX3100 is not set +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_UNIX98_PTYS=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=256 +# CONFIG_IPMI_HANDLER is not set +# CONFIG_HW_RANDOM is not set +# CONFIG_R3964 is not set + +# +# PCMCIA character devices +# +# CONFIG_SYNCLINK_CS is not set +# CONFIG_CARDMAN_4000 is not set +# CONFIG_CARDMAN_4040 is not set +# CONFIG_IPWIRELESS is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +# CONFIG_I2C_COMPAT is not set +CONFIG_I2C_CHARDEV=y +# CONFIG_I2C_HELPER_AUTO is not set + +# +# I2C Algorithms +# +# CONFIG_I2C_ALGOBIT is not set +# CONFIG_I2C_ALGOPCF is not set +# CONFIG_I2C_ALGOPCA is not set + +# +# I2C Hardware Bus support +# + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +CONFIG_I2C_AU1550=y +# CONFIG_I2C_GPIO is not set +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_SIMTEC is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_TAOS_EVM is not set + +# +# Other I2C/SMBus bus drivers +# +# CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_STUB is not set + +# +# Miscellaneous I2C Chip support +# +# CONFIG_DS1682 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# CONFIG_I2C_DEBUG_CHIP is not set +CONFIG_SPI=y +# CONFIG_SPI_DEBUG is not set +CONFIG_SPI_MASTER=y + +# +# SPI Master Controller Drivers +# +# CONFIG_SPI_AU1550 is not set +# CONFIG_SPI_BITBANG is not set +# CONFIG_SPI_GPIO is not set + +# +# SPI Protocol Masters +# +# CONFIG_SPI_SPIDEV is not set +# CONFIG_SPI_TLE62X0 is not set + +# +# PPS support +# +# CONFIG_PPS is not set +CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y +CONFIG_GPIOLIB=y +CONFIG_DEBUG_GPIO=y +# CONFIG_GPIO_SYSFS is not set + +# +# Memory mapped GPIO expanders: +# + +# +# I2C GPIO expanders: +# +# CONFIG_GPIO_MAX732X is not set +# CONFIG_GPIO_PCA953X is not set +# CONFIG_GPIO_PCF857X is not set + +# +# PCI GPIO expanders: +# + +# +# SPI GPIO expanders: +# +# CONFIG_GPIO_MAX7301 is not set +# CONFIG_GPIO_MCP23S08 is not set +# CONFIG_GPIO_MC33880 is not set + +# +# AC97 GPIO expanders: +# +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +CONFIG_HWMON=y +CONFIG_HWMON_VID=y +# CONFIG_HWMON_DEBUG_CHIP is not set + +# +# Native drivers +# +# CONFIG_SENSORS_AD7414 is not set +# CONFIG_SENSORS_AD7418 is not set +# CONFIG_SENSORS_ADCXX is not set +# CONFIG_SENSORS_ADM1021 is not set +CONFIG_SENSORS_ADM1025=y +# CONFIG_SENSORS_ADM1026 is not set +# CONFIG_SENSORS_ADM1029 is not set +# CONFIG_SENSORS_ADM1031 is not set +# CONFIG_SENSORS_ADM9240 is not set +# CONFIG_SENSORS_ADT7462 is not set +# CONFIG_SENSORS_ADT7470 is not set +# CONFIG_SENSORS_ADT7473 is not set +# CONFIG_SENSORS_ADT7475 is not set +# CONFIG_SENSORS_ATXP1 is not set +# CONFIG_SENSORS_DS1621 is not set +# CONFIG_SENSORS_F71805F is not set +# CONFIG_SENSORS_F71882FG is not set +# CONFIG_SENSORS_F75375S is not set +# CONFIG_SENSORS_G760A is not set +# CONFIG_SENSORS_GL518SM is not set +# CONFIG_SENSORS_GL520SM is not set +# CONFIG_SENSORS_IT87 is not set +# CONFIG_SENSORS_LM63 is not set +# CONFIG_SENSORS_LM70 is not set +# CONFIG_SENSORS_LM75 is not set +# CONFIG_SENSORS_LM77 is not set +# CONFIG_SENSORS_LM78 is not set +# CONFIG_SENSORS_LM80 is not set +# CONFIG_SENSORS_LM83 is not set +# CONFIG_SENSORS_LM85 is not set +# CONFIG_SENSORS_LM87 is not set +# CONFIG_SENSORS_LM90 is not set +# CONFIG_SENSORS_LM92 is not set +# CONFIG_SENSORS_LM93 is not set +# CONFIG_SENSORS_LTC4215 is not set +# CONFIG_SENSORS_LTC4245 is not set +# CONFIG_SENSORS_LM95241 is not set +# CONFIG_SENSORS_MAX1111 is not set +# CONFIG_SENSORS_MAX1619 is not set +# CONFIG_SENSORS_MAX6650 is not set +# CONFIG_SENSORS_PC87360 is not set +# CONFIG_SENSORS_PC87427 is not set +# CONFIG_SENSORS_PCF8591 is not set +# CONFIG_SENSORS_SHT15 is not set +# CONFIG_SENSORS_DME1737 is not set +# CONFIG_SENSORS_SMSC47M1 is not set +# CONFIG_SENSORS_SMSC47M192 is not set +# CONFIG_SENSORS_SMSC47B397 is not set +# CONFIG_SENSORS_ADS7828 is not set +# CONFIG_SENSORS_THMC50 is not set +# CONFIG_SENSORS_TMP401 is not set +# CONFIG_SENSORS_TMP421 is not set +# CONFIG_SENSORS_VT1211 is not set +# CONFIG_SENSORS_W83781D is not set +# CONFIG_SENSORS_W83791D is not set +# CONFIG_SENSORS_W83792D is not set +# CONFIG_SENSORS_W83793 is not set +# CONFIG_SENSORS_W83L785TS is not set +# CONFIG_SENSORS_W83L786NG is not set +# CONFIG_SENSORS_W83627HF is not set +# CONFIG_SENSORS_W83627EHF is not set +# CONFIG_SENSORS_LIS3_SPI is not set +# CONFIG_THERMAL is not set +# CONFIG_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_TPS65010 is not set +# CONFIG_TWL4030_CORE is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM831X is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_MFD_PCF50633 is not set +# CONFIG_MFD_MC13783 is not set +# CONFIG_AB3100_CORE is not set +# CONFIG_EZX_PCAP is not set +# CONFIG_REGULATOR is not set +# CONFIG_MEDIA_SUPPORT is not set + +# +# Graphics support +# +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +# CONFIG_FB is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +# CONFIG_SOUND is not set +# CONFIG_HID_SUPPORT is not set +# CONFIG_USB_SUPPORT is not set +# CONFIG_MMC is not set +# CONFIG_MEMSTICK is not set +# CONFIG_NEW_LEDS is not set +# CONFIG_ACCESSIBILITY is not set +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +# CONFIG_RTC_DRV_TEST is not set + +# +# I2C RTC drivers +# +# CONFIG_RTC_DRV_DS1307 is not set +# CONFIG_RTC_DRV_DS1374 is not set +# CONFIG_RTC_DRV_DS1672 is not set +# CONFIG_RTC_DRV_MAX6900 is not set +# CONFIG_RTC_DRV_RS5C372 is not set +# CONFIG_RTC_DRV_ISL1208 is not set +# CONFIG_RTC_DRV_X1205 is not set +# CONFIG_RTC_DRV_PCF8563 is not set +# CONFIG_RTC_DRV_PCF8583 is not set +# CONFIG_RTC_DRV_M41T80 is not set +# CONFIG_RTC_DRV_S35390A is not set +# CONFIG_RTC_DRV_FM3130 is not set +# CONFIG_RTC_DRV_RX8581 is not set +# CONFIG_RTC_DRV_RX8025 is not set + +# +# SPI RTC drivers +# +# CONFIG_RTC_DRV_M41T94 is not set +# CONFIG_RTC_DRV_DS1305 is not set +# CONFIG_RTC_DRV_DS1390 is not set +# CONFIG_RTC_DRV_MAX6902 is not set +# CONFIG_RTC_DRV_R9701 is not set +# CONFIG_RTC_DRV_RS5C348 is not set +# CONFIG_RTC_DRV_DS3234 is not set +# CONFIG_RTC_DRV_PCF2123 is not set + +# +# Platform RTC drivers +# +# CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_DS1286 is not set +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_BQ4802 is not set +# CONFIG_RTC_DRV_V3020 is not set + +# +# on-CPU RTC drivers +# +CONFIG_RTC_DRV_AU1XXX=y +# CONFIG_DMADEVICES is not set +# CONFIG_AUXDISPLAY is not set +# CONFIG_UIO is not set + +# +# TI VLYNQ +# +# CONFIG_STAGING is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +# CONFIG_EXT3_FS is not set +# CONFIG_EXT4_FS is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +# CONFIG_XFS_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_BTRFS_FS is not set +# CONFIG_NILFS2_FS is not set +CONFIG_FILE_LOCKING=y +CONFIG_FSNOTIFY=y +CONFIG_DNOTIFY=y +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# Caches +# +# CONFIG_FSCACHE is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +# CONFIG_MSDOS_FS is not set +# CONFIG_VFAT_FS is not set +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +# CONFIG_PROC_KCORE is not set +CONFIG_PROC_SYSCTL=y +# CONFIG_PROC_PAGE_MONITOR is not set +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set +# CONFIG_MISC_FILESYSTEMS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set +CONFIG_ROOT_NFS=y +# CONFIG_NFSD is not set +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_RPCSEC_GSS_KRB5 is not set +# CONFIG_RPCSEC_GSS_SPKM3 is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y +# CONFIG_NLS is not set +# CONFIG_DLM is not set + +# +# Kernel hacking +# +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +# CONFIG_MAGIC_SYSRQ is not set +CONFIG_STRIP_ASM_SYMS=y +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +CONFIG_DEBUG_KERNEL=y +CONFIG_IRQ_DEBUG=y +# CONFIG_DEBUG_SHIRQ is not set +# CONFIG_DETECT_SOFTLOCKUP is not set +# CONFIG_DETECT_HUNG_TASK is not set +# CONFIG_SCHED_DEBUG is not set +# CONFIG_SCHEDSTATS is not set +# CONFIG_TIMER_STATS is not set +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_RT_MUTEX_TESTER is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_PROVE_LOCKING is not set +# CONFIG_LOCK_STAT is not set +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_DEBUG_KOBJECT is not set +CONFIG_DEBUG_INFO=y +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_WRITECOUNT is not set +# CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_DEBUG_LIST is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_DEBUG_CREDENTIALS is not set +# CONFIG_BOOT_PRINTK_DELAY is not set +# CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set +# CONFIG_FAULT_INJECTION is not set +# CONFIG_PAGE_POISONING is not set +CONFIG_TRACING_SUPPORT=y +# CONFIG_FTRACE is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_KGDB is not set +CONFIG_CMDLINE="console=ttyS2,115200 root=/dev/nfs nfsroot=192.168.0.242:/var/chroot/mips,v3,tcp ip=192.168.0.68:192.168.0.242:192.168.0.1:255.255.255.0:db1300:eth0:off init=/linuxrc" +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_RUNTIME_DEBUG is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set +CONFIG_SECURITYFS=y +CONFIG_SECURITY_FILE_CAPABILITIES=y +# CONFIG_CRYPTO is not set +# CONFIG_BINARY_PRINTF is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_GENERIC_FIND_LAST_BIT=y +# CONFIG_CRC_CCITT is not set +# CONFIG_CRC16 is not set +# CONFIG_CRC_T10DIF is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y +CONFIG_NLATTR=y diff --git a/arch/mips/include/asm/mach-db1x00/bcsr.h b/arch/mips/include/asm/mach-db1x00/bcsr.h index 618d2de..3c741c3 100644 --- a/arch/mips/include/asm/mach-db1x00/bcsr.h +++ b/arch/mips/include/asm/mach-db1x00/bcsr.h @@ -34,6 +34,8 @@ #define PB1200_BCSR_PHYS_ADDR 0x0D800000 #define PB1200_BCSR_HEXLED_OFS 0x00400000 +#define DB1300_BCSR_PHYS_ADDR 0x19800000 +#define DB1300_BCSR_HEXLED_OFS 0x00400000 enum bcsr_id { /* BCSR base 1 */ @@ -105,6 +107,7 @@ enum bcsr_whoami_boards { BCSR_WHOAMI_PB1200 = BCSR_WHOAMI_PB1200_DDR1, BCSR_WHOAMI_PB1200_DDR2, BCSR_WHOAMI_DB1200, + BCSR_WHOAMI_DB1300, }; /* STATUS reg. Unless otherwise noted, they're valid on all boards. diff --git a/arch/mips/include/asm/mach-db1x00/db1300.h b/arch/mips/include/asm/mach-db1x00/db1300.h new file mode 100644 index 0000000..ece8ae0 --- /dev/null +++ b/arch/mips/include/asm/mach-db1x00/db1300.h @@ -0,0 +1,37 @@ +/* + * RMI DB1300 board constants + */ + +#ifndef _DB1300_H_ +#define _DB1300_H_ + +#define DB1300_FIRST_INT (AU1300_LAST_INT + 1) +#define DB1300_IDE_INT (DB1300_FIRST_INT + 0) +#define DB1300_ETH_INT (DB1300_FIRST_INT + 1) +#define DB1300_CF_INT (DB1300_FIRST_INT + 2) +#define DB1300_VIDEO_INT (DB1300_FIRST_INT + 4) +#define DB1300_HDMI_INT (DB1300_FIRST_INT + 5) +#define DB1300_DC_INT (DB1300_FIRST_INT + 6) +#define DB1300_FLASH_INT (DB1300_FIRST_INT + 7) +#define DB1300_CF_INSERT_INT (DB1300_FIRST_INT + 8) +#define DB1300_CF_EJECT_INT (DB1300_FIRST_INT + 9) +#define DB1300_AC97_INT (DB1300_FIRST_INT + 10) +#define DB1300_AC97_PEN_INT (DB1300_FIRST_INT + 11) +#define DB1300_SD1_INSERT_INT (DB1300_FIRST_INT + 12) +#define DB1300_SD1_EJECT_INT (DB1300_FIRST_INT + 13) +#define DB1300_OTG_VBUS_OC_INT (DB1300_FIRST_INT + 14) +#define DB1300_HOST_VBUS_OC_INT (DB1300_FIRST_INT + 15) +#define DB1300_LAST_INT (DB1300_FIRST_INT + 15) + +#define DB1300_ETH_PHYS_ADDR 0x19000000 +#define DB1300_ETH_PHYS_END 0x197fffff + +#define DB1300_IDE_PHYS_ADDR 0x18800000 +#define DB1300_IDE_REG_SHIFT 5 +#define DB1300_IDE_PHYS_LEN (16 << DB1300_IDE_REG_SHIFT) + +#define DB1300_NAND_PHYS_ADDR 0x20000000 +#define DB1300_NAND_PHYS_END 0x20000fff + +#endif /* _DB1300_H_ */ + diff --git a/drivers/pcmcia/db1xxx_ss.c b/drivers/pcmcia/db1xxx_ss.c index b35b72b..8f94ef8 100644 --- a/drivers/pcmcia/db1xxx_ss.c +++ b/drivers/pcmcia/db1xxx_ss.c @@ -59,6 +59,7 @@ struct db1x_pcmcia_sock { #define BOARD_TYPE_DEFAULT 0 /* most boards */ #define BOARD_TYPE_DB1200 1 /* IRQs aren't gpios */ #define BOARD_TYPE_PB1100 2 /* VS bits slightly different */ +#define BOARD_TYPE_DB1300 3 /* no power control */ int board_type; }; @@ -161,7 +162,8 @@ static int db1x_pcmcia_setup_irqs(struct db1x_pcmcia_sock *sock) * ejection handler have been registered and the currently * active one disabled. */ - if (sock->board_type == BOARD_TYPE_DB1200) { + if ((sock->board_type == BOARD_TYPE_DB1200) || + (sock->board_type == BOARD_TYPE_DB1300)) { local_irq_save(flags); ret = request_irq(sock->insert_irq, db1200_pcmcia_cdirq, @@ -276,7 +278,8 @@ static int db1x_pcmcia_configure(struct pcmcia_socket *skt, } /* create new voltage code */ - cr_set |= ((v << 2) | p) << (sock->nr * 8); + if (sock->board_type != BOARD_TYPE_DB1300) + cr_set |= ((v << 2) | p) << (sock->nr * 8); changed = state->flags ^ sock->old_flags; @@ -352,6 +355,10 @@ static int db1x_pcmcia_get_status(struct pcmcia_socket *skt, /* reset de-asserted? then we're ready */ status |= (GET_RESET(cr, sock->nr)) ? SS_READY : SS_RESET; + /* DB1300: power is always on */ + if (sock->board_type == BOARD_TYPE_DB1300) + status |= SS_POWERON | SS_3VCARD; + *value = status; return 0; @@ -426,6 +433,9 @@ static int __devinit db1x_pcmcia_socket_probe(struct platform_device *pdev) case BCSR_WHOAMI_PB1200 ... BCSR_WHOAMI_DB1200: sock->board_type = BOARD_TYPE_DB1200; break; + case BCSR_WHOAMI_DB1300: + sock->board_type = BOARD_TYPE_DB1300; + break; default: printk(KERN_INFO "db1xxx-ss: unknown board %d!\n", bid); ret = -ENODEV; -- 1.6.5.2 From f.fainelli@gmail.com Tue Nov 3 22:14:37 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 03 Nov 2009 22:14:44 +0100 (CET) Received: from ey-out-1920.google.com ([74.125.78.149]:64938 "EHLO ey-out-1920.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1493581AbZKCVOh (ORCPT ); Tue, 3 Nov 2009 22:14:37 +0100 Received: by ey-out-1920.google.com with SMTP id 5so1197729eyb.52 for ; Tue, 03 Nov 2009 13:14:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:sender:from:organization:to :subject:date:user-agent:cc:references:in-reply-to:mime-version :content-type:content-transfer-encoding:message-id; bh=Iedgr+GsjpDfHdgLanvOfifS8r94Gk03FV57lsoegSw=; b=iFJpZe5T+IYGKaEm9EMfEA88zxwSBnxOl9dG257WdriEAqsA540F3EXH/ObsVsxNLl 9Nbr1dBFhLSF18HZ7fbNreyQQs66zd9opgJ22NW5VAIZmPLo8AZl4xZXcCwzgoMtvQRQ l6h37vyn9CFVzFAz+IEHRVH1EZ+oSkX0YsDaw= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:from:organization:to:subject:date:user-agent:cc:references :in-reply-to:mime-version:content-type:content-transfer-encoding :message-id; b=j7IPGBfdp9xnj4NHTteThJginTVDcILMm5Kt+JFdjyUkQ5xHGLUvfPoZKVQhyAMnEZ 3DtfMgqiEHBnfCYElfny6P/Tuu2PgXxTMsXrnr0sSlJQo+9sgk1vnjfqCr1M0zncjgaz 91showRCVr3aonPhAU5M12MIpzMeIGzBU0wgA= Received: by 10.213.68.143 with SMTP id v15mr901661ebi.45.1257282876665; Tue, 03 Nov 2009 13:14:36 -0800 (PST) Received: from flexo.localnet (bobafett.staff.proxad.net [213.228.1.121]) by mx.google.com with ESMTPS id 10sm1448080eyz.43.2009.11.03.13.14.34 (version=SSLv3 cipher=RC4-MD5); Tue, 03 Nov 2009 13:14:34 -0800 (PST) From: Florian Fainelli Organization: OpenWrt To: Sergei Shtylyov Subject: Re: [PATCH 1/2] alchemy: add au1000-eth platform device Date: Tue, 3 Nov 2009 22:14:30 +0100 User-Agent: KMail/1.12.2 (Linux/2.6.31-14-server; KDE/4.3.2; x86_64; ; ) Cc: Ralf Baechle , linux-mips@linux-mips.org, Manuel Lauss , David Miller , netdev@vger.kernel.org References: <200908170105.38154.florian@openwrt.org> <200910171048.24962.florian@openwrt.org> <4AE1DEFD.4090902@ru.mvista.com> In-Reply-To: <4AE1DEFD.4090902@ru.mvista.com> MIME-Version: 1.0 Content-Type: Text/Plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit Message-Id: <200911032214.30453.florian@openwrt.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24653 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips Hi Sergei, On Friday 23 October 2009 18:51:09 Sergei Shtylyov wrote: > Hello. > > Florian Fainelli wrote: > > Please find below and updated version, hopefully addressing most if not > > all of your comments. > > Thanks. I still have some comments on the code testing the NI2 bit. :-) This version hopefully addresses your last comments. Thanks ! -- From: Florian Fainelli Subject: [PATCH 1/2] alchemy: add au1000-eth platform device (v4) This patch makes the board code register the au1000-eth platform device. The au1000-eth platform data can be overriden with the au1xxx_override_eth_cfg function like it has to be done for the Bosporus board which uses a different MAC/PHY setup. Changes from v3: - declare a static au1000_eth_platform_data structure for bosporus and initialize it - remove parenthis and bit shifting on SYS_PF_NI2 Changes from v2: - declared the au1000-eth second driver instance platform_data - made the override function generic and pass it the port number too Changes from v1: - remove per-board platform.c file - add an override function to pass custom eth0 platform_data PHY settings Signed-off-by: Florian Fainelli --- diff --git a/arch/mips/alchemy/common/platform.c b/arch/mips/alchemy/common/platform.c index 3be14b0..3fbe30c 100644 --- a/arch/mips/alchemy/common/platform.c +++ b/arch/mips/alchemy/common/platform.c @@ -19,6 +19,7 @@ #include #include #include +#include #define PORT(_base, _irq) \ { \ @@ -326,6 +327,88 @@ static struct platform_device pbdb_smbus_device = { }; #endif +/* Macro to help defining the Ethernet MAC resources */ +#define MAC_RES(_base, _enable, _irq) \ + { \ + .start = CPHYSADDR(_base), \ + .end = CPHYSADDR(_base + 0xffff), \ + .flags = IORESOURCE_MEM, \ + }, \ + { \ + .start = CPHYSADDR(_enable), \ + .end = CPHYSADDR(_enable + 0x3), \ + .flags = IORESOURCE_MEM, \ + }, \ + { \ + .start = _irq, \ + .end = _irq, \ + .flags = IORESOURCE_IRQ \ + } + +static struct resource au1xxx_eth0_resources[] = { +#if defined(CONFIG_SOC_AU1000) + MAC_RES(AU1000_ETH0_BASE, AU1000_MAC0_ENABLE, AU1000_MAC0_DMA_INT), +#elif defined(CONFIG_SOC_AU1100) + MAC_RES(AU1100_ETH0_BASE, AU1100_MAC0_ENABLE, AU1100_MAC0_DMA_INT), +#elif defined(CONFIG_SOC_AU1550) + MAC_RES(AU1550_ETH0_BASE, AU1550_MAC0_ENABLE, AU1550_MAC0_DMA_INT), +#elif defined(CONFIG_SOC_AU1500) + MAC_RES(AU1500_ETH0_BASE, AU1500_MAC0_ENABLE, AU1500_MAC0_DMA_INT), +#endif +}; + +static struct resource au1xxx_eth1_resources[] = { +#if defined(CONFIG_SOC_AU1000) + MAC_RES(AU1000_ETH1_BASE, AU1000_MAC1_ENABLE, AU1000_MAC1_DMA_INT), +#elif defined(CONFIG_SOC_AU1550) + MAC_RES(AU1550_ETH1_BASE, AU1550_MAC1_ENABLE, AU1550_MAC1_DMA_INT), +#elif defined(CONFIG_SOC_AU1500) + MAC_RES(AU1500_ETH1_BASE, AU1500_MAC1_ENABLE, AU1500_MAC1_DMA_INT), +#endif +}; + +static struct au1000_eth_platform_data au1xxx_eth0_platform_data = { + .phy1_search_mac0 = 1, +}; + +static struct platform_device au1xxx_eth0_device = { + .name = "au1000-eth", + .id = 0, + .num_resources = ARRAY_SIZE(au1xxx_eth0_resources), + .resource = au1xxx_eth0_resources, + .dev.platform_data = &au1xxx_eth0_platform_data, +}; + +#ifndef CONFIG_SOC_AU1100 +static struct au1000_eth_platform_data au1xxx_eth1_platform_data = { + .phy1_search_mac0 = 1, +}; + +static struct platform_device au1xxx_eth1_device = { + .name = "au1000-eth", + .id = 1, + .num_resources = ARRAY_SIZE(au1xxx_eth1_resources), + .resource = au1xxx_eth1_resources, + .dev.platform_data = &au1xxx_eth1_platform_data, +}; +#endif + +void __init au1xxx_override_eth_cfg(unsigned int port, + struct au1000_eth_platform_data *eth_data) +{ + if (!eth_data || port > 1) + return; + + if (port == 0) + memcpy(&au1xxx_eth0_platform_data, eth_data, + sizeof(struct au1000_eth_platform_data)); +#ifndef CONFIG_SOC_AU1100 + else + memcpy(&au1xxx_eth1_platform_data, eth_data, + sizeof(struct au1000_eth_platform_data)); +#endif +} + static struct platform_device *au1xxx_platform_devices[] __initdata = { &au1xx0_uart_device, &au1xxx_usb_ohci_device, @@ -345,6 +428,7 @@ static struct platform_device *au1xxx_platform_devices[] __initdata = { #ifdef SMBUS_PSC_BASE &pbdb_smbus_device, #endif + &au1xxx_eth0_device, }; static int __init au1xxx_platform_init(void) @@ -356,6 +440,12 @@ static int __init au1xxx_platform_init(void) for (i = 0; au1x00_uart_data[i].flags; i++) au1x00_uart_data[i].uartclk = uartclk; +#ifndef CONFIG_SOC_AU1100 + /* Register second MAC if enabled in pinfunc */ + if (!(au_readl(SYS_PINFUNC) & (u32)SYS_PF_NI2)) + platform_device_register(&au1xxx_eth1_device); +#endif + return platform_add_devices(au1xxx_platform_devices, ARRAY_SIZE(au1xxx_platform_devices)); } diff --git a/arch/mips/alchemy/devboards/db1x00/board_setup.c b/arch/mips/alchemy/devboards/db1x00/board_setup.c index 7aee14d..ad26db2 100644 --- a/arch/mips/alchemy/devboards/db1x00/board_setup.c +++ b/arch/mips/alchemy/devboards/db1x00/board_setup.c @@ -32,6 +32,7 @@ #include #include +#include #include #include @@ -43,6 +44,18 @@ char irq_tab_alchemy[][5] __initdata = { [13] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, AU1500_PCI_INTC, AU1500_PCI_INTD }, /* IDSEL 13 - PCI slot */ }; #endif + +/* + * Micrel/Kendin 5 port switch attached to MAC0, + * MAC0 is associated with PHY address 5 (== WAN port) + * MAC1 is not associated with any PHY, since it's connected directly + * to the switch. + * no interrupts are used + */ +static struct au1000_eth_platform_data eth0_pdata = { + .phy_static_config = 1, + .phy_addr = 5, +}; #ifdef CONFIG_MIPS_BOSPORUS char irq_tab_alchemy[][5] __initdata = { @@ -50,6 +63,8 @@ char irq_tab_alchemy[][5] __initdata = { [12] = { -1, AU1500_PCI_INTA, 0xff, 0xff, 0xff }, /* IDSEL 12 - SN1741 */ [13] = { -1, AU1500_PCI_INTA, AU1500_PCI_INTB, AU1500_PCI_INTC, AU1500_PCI_INTD }, /* IDSEL 13 - PCI slot */ }; + + #endif #ifdef CONFIG_MIPS_MIRAGE @@ -103,6 +118,8 @@ void __init board_setup(void) printk(KERN_INFO "AMD Alchemy Au1100/Db1100 Board\n"); #endif #ifdef CONFIG_MIPS_BOSPORUS + au1xxx_override_eth_cfg(0, ð0_pdata); + printk(KERN_INFO "AMD Alchemy Bosporus Board\n"); #endif #ifdef CONFIG_MIPS_MIRAGE diff --git a/arch/mips/include/asm/mach-au1x00/au1xxx_eth.h b/arch/mips/include/asm/mach-au1x00/au1xxx_eth.h new file mode 100644 index 0000000..f30529e --- /dev/null +++ b/arch/mips/include/asm/mach-au1x00/au1xxx_eth.h @@ -0,0 +1,18 @@ +#ifndef __AU1X00_ETH_DATA_H +#define __AU1X00_ETH_DATA_H + +/* Platform specific PHY configuration passed to the MAC driver */ +struct au1000_eth_platform_data { + int phy_static_config; + int phy_search_highest_addr; + int phy1_search_mac0; + int phy_addr; + int phy_busid; + int phy_irq; +}; + +void __init au1xxx_override_eth_cfg(unsigned port, + struct au1000_eth_platform_data *eth_data); + +#endif /* __AU1X00_ETH_DATA_H */ + From miloody@gmail.com Wed Nov 4 03:33:24 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 04 Nov 2009 03:33:31 +0100 (CET) Received: from mail-pz0-f194.google.com ([209.85.222.194]:60430 "EHLO mail-pz0-f194.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1494059AbZKDCdY convert rfc822-to-8bit (ORCPT ); Wed, 4 Nov 2009 03:33:24 +0100 Received: by pzk32 with SMTP id 32so4521247pzk.21 for ; Tue, 03 Nov 2009 18:33:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:in-reply-to:references :date:message-id:subject:from:to:cc:content-type :content-transfer-encoding; bh=KnpxVd5lZ0/PuQEVz3+hYMUwMA6tpJVJgjIPqFklATM=; b=WNU2Hayju+wuES+ziRd7H2HFed8a9iZmYp8jPpz3jUKjWBR9oOHECwruT4kx4ORqEh 8houHNBfzswqVNyFIWWozcvMkH7lH9xoTtITq3WUZoKGTTttXI9nSBnM9vKS9CaVBRf3 MtjJTGNXZOw8r6rpkY7aM6uvbsDsbPvTy9Wz8= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type:content-transfer-encoding; b=i/CaQ44GAjaam7oQCP5BgywtEFvqeeEtKYm7wZRYC5u7fMRpj9jwy/qC3/0sNFZC3e 0KemNWdVpn3p+BC0oNQBDoRFYV9cOv/JcZm5gzfES3eONtmrAgtBzFevHOR31srX6RwB yZhkhV/GoGv1Cdo74yeFL50RCa/RsJhbbye0s= MIME-Version: 1.0 Received: by 10.142.151.5 with SMTP id y5mr83496wfd.329.1257301995103; Tue, 03 Nov 2009 18:33:15 -0800 (PST) In-Reply-To: <20091102071724.GB13360@linux-mips.org> References: <3a665c760911010618u7216cd68wfbd02610d2029862@mail.gmail.com> <20091102071724.GB13360@linux-mips.org> Date: Wed, 4 Nov 2009 10:33:14 +0800 Message-ID: <3a665c760911031833s4b8dba82o67a8e7bcc225d28f@mail.gmail.com> Subject: Re: why we use multu to implement udelay From: loody To: Ralf Baechle Cc: Linux MIPS Mailing List Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24654 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: miloody@gmail.com Precedence: bulk X-list: linux-mips Hi: thanks for your kind help :) 2009/11/2 Ralf Baechle : > On Sun, Nov 01, 2009 at 10:18:14PM +0800, loody wrote: > >> If I search the right place in mip kernel, I find the kernel implement >> udelay by multu and bnez looping, in 32-bits mode. >>       if (sizeof(long) == 4) >>               __asm__("multu\t%2, %3" >>               : "=h" (usecs), "=l" (lo) >>               : "r" (usecs), "r" (lpj) >>               : GCC_REG_ACCUM); >>       else if (sizeof(long) == 8) >>               __asm__("dmultu\t%2, %3" >>               : "=h" (usecs), "=l" (lo) >>               : "r" (usecs), "r" (lpj) >>               : GCC_REG_ACCUM); >> >>       __delay(usecs); >> why we doing so instead of using kernel timer function and the >> precision will be incorrect if the cpu runs faster or slower, right? > > This is an old-fashioned implementation which will work even on systems > where no CPU timer is available or its frequency is unknown or variable. > > A while ago patches were posted to use the cp0 counter instead but do > to other necessary rewrites those patches went stale, so need to be > reworked before they can be applied.  Either way, for above restrictions > the delay by looping implementation will still be needed as the fallback > implementation. > >  Ralf I find in the __udelay we will first calculate out the value of counter then sent to __delay for looping. The formula of counter value is like below: #if defined(CONFIG_64BIT) && (HZ == 128) usecs *= 0x0008637bd05af6c7UL; /* 2**64 / (1000000 / HZ) */ #elif defined(CONFIG_64BIT) usecs *= (0x8000000000000000UL / (500000 / HZ)); #else /* 32-bit junk follows here */ usecs *= (unsigned long) (((0x8000000000000000ULL / (500000 / HZ)) + 0x80000000ULL) >> 32); #endif Is there any rule or principle that tells us how to get this value? appreciate your help, miloody From wuzhangjin@gmail.com Wed Nov 4 06:59:16 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 04 Nov 2009 06:59:23 +0100 (CET) Received: from mail-pz0-f194.google.com ([209.85.222.194]:38234 "EHLO mail-pz0-f194.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492132AbZKDF7Q (ORCPT ); Wed, 4 Nov 2009 06:59:16 +0100 Received: by pzk32 with SMTP id 32so4621608pzk.21 for ; Tue, 03 Nov 2009 21:59:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:subject:from:reply-to:to:cc :content-type:organization:date:message-id:mime-version:x-mailer :content-transfer-encoding; bh=4+9wjNcALbJgNrRWWyl0BTpbTMtMbodJH4CMMT7Tu7A=; b=lzh7M4cWsgGqHTTDBOrI+BcC9qhvZNv5c6tVTdagT+UggzCwm0YQiyRbssUtTFZaXG /iM3x4YqHEGvZcYo2IyFNb1RrqgFN0X6C5o3AQmZb6A8hsCf7OkK76ehyWCCGoxSbnpw bHKYdZlpgrdJp+NMLBal+SMbsZFc7l1sm85ws= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=subject:from:reply-to:to:cc:content-type:organization:date :message-id:mime-version:x-mailer:content-transfer-encoding; b=nb/iCqS4EoqGFuMvvR6gj6ervviRAZi+dyz1A+z4fx6310b0aTS8TTrUpA+R90/oKK lb3BWv7LgdlwjRng11ZGSpi9ncho9UCKINVNolNsgBakO4VCReL9L2RDq2aYq+xrwQtG EhJ9kRgkkN9zc17ojwVnuH3Nsk2gdb3n0cNT0= Received: by 10.115.66.29 with SMTP id t29mr1333273wak.187.1257314346821; Tue, 03 Nov 2009 21:59:06 -0800 (PST) Received: from ?172.16.2.101? ([222.92.8.142]) by mx.google.com with ESMTPS id 21sm411051pzk.3.2009.11.03.21.59.04 (version=TLSv1/SSLv3 cipher=RC4-MD5); Tue, 03 Nov 2009 21:59:06 -0800 (PST) Subject: [-queue] arch/mips/kernel/linux32.c:304: error: implicit declaration of function 'lock_kernel' From: Wu Zhangjin Reply-To: wuzhangjin@gmail.com To: Ralf Baechle Cc: linux-mips@linux-mips.org Content-Type: text/plain; charset="UTF-8" Organization: DSLab, Lanzhou University, China Date: Wed, 04 Nov 2009 13:59:09 +0800 Message-ID: <1257314349.3778.62.camel@falcon.domain.org> Mime-Version: 1.0 X-Mailer: Evolution 2.28.1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24655 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips Hi, Ralf When I compile the queue branch of your -queue git repo, meet this error: arch/mips/kernel/linux32.c: In function 'SYSC_32_sysctl': arch/mips/kernel/linux32.c:304: error: implicit declaration of function 'lock_kernel' arch/mips/kernel/linux32.c:307: error: implicit declaration of function 'unlock_kernel' and found you have removed this header file in linux32.c in this commit: commit 0adcf22332d4da33629568fd14e00069cbf002e6 Author: Ralf Baechle Date: Tue Nov 3 23:06:18 2009 +0100 MIPS: Don't include unnecessarily. Signed-off-by: Ralf Baechle :100644 100644 938b1d0... 3676660... M arch/mips/basler/excite/excite_iodev.c :100644 100644 b77fefa... 07cc39e... M arch/mips/kernel/linux32.c :100644 100644 364f066... dcaed1b... M arch/mips/kernel/rtlx.c :100644 100644 6047752... 2bd2151... M arch/mips/kernel/vpe.c :100644 100644 15ea778... ed2453e... M arch/mips/sibyte/common/sb_tbprof.c So, revert it for linux32.c? Regards, Wu Zhangjin From ralf@linux-mips.org Wed Nov 4 07:10:38 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 04 Nov 2009 07:10:41 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:36403 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-FAIL) by ftp.linux-mips.org with ESMTP id S1492151AbZKDGKh (ORCPT ); Wed, 4 Nov 2009 07:10:37 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id nA46C5JG002769; Wed, 4 Nov 2009 07:12:05 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id nA46C5C1002767; Wed, 4 Nov 2009 07:12:05 +0100 Date: Wed, 4 Nov 2009 07:12:05 +0100 From: Ralf Baechle To: Wu Zhangjin Cc: linux-mips@linux-mips.org Subject: Re: [-queue] arch/mips/kernel/linux32.c:304: error: implicit declaration of function 'lock_kernel' Message-ID: <20091104061205.GB610@linux-mips.org> References: <1257314349.3778.62.camel@falcon.domain.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1257314349.3778.62.camel@falcon.domain.org> User-Agent: Mutt/1.5.19 (2009-01-05) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24656 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Wed, Nov 04, 2009 at 01:59:09PM +0800, Wu Zhangjin wrote: > When I compile the queue branch of your -queue git repo, meet this > error: > > arch/mips/kernel/linux32.c: In function 'SYSC_32_sysctl': > arch/mips/kernel/linux32.c:304: error: implicit declaration of function > 'lock_kernel' > arch/mips/kernel/linux32.c:307: error: implicit declaration of function > 'unlock_kernel' > > and found you have removed this header file in > linux32.c in this commit: > > commit 0adcf22332d4da33629568fd14e00069cbf002e6 > Author: Ralf Baechle > Date: Tue Nov 3 23:06:18 2009 +0100 > > MIPS: Don't include unnecessarily. > > Signed-off-by: Ralf Baechle > > :100644 100644 938b1d0... 3676660... M > arch/mips/basler/excite/excite_iodev.c > :100644 100644 b77fefa... 07cc39e... M arch/mips/kernel/linux32.c > :100644 100644 364f066... dcaed1b... M arch/mips/kernel/rtlx.c > :100644 100644 6047752... 2bd2151... M arch/mips/kernel/vpe.c > :100644 100644 15ea778... ed2453e... M > arch/mips/sibyte/common/sb_tbprof.c There is another patch from Thomas Gleixner pending which will push down the lock_kernel calls deeper into the sysctl calls. I also had that patch applied so missed that build failure. > So, revert it for linux32.c? Yes, that's what I'll do for now. Thanks! Ralf From yuasa.linux@gmail.com Wed Nov 4 08:42:03 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 04 Nov 2009 08:42:10 +0100 (CET) Received: from mail-yw0-f173.google.com ([209.85.211.173]:35826 "EHLO mail-yw0-f173.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492416AbZKDHmD (ORCPT ); Wed, 4 Nov 2009 08:42:03 +0100 Received: by ywh3 with SMTP id 3so7044819ywh.22 for ; Tue, 03 Nov 2009 23:41:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:sender:date:from:to:cc :subject:message-id:x-mailer:mime-version:content-type :content-transfer-encoding; bh=lwybjC5A4qE6NHZqdbT1DhaUCbi46JepJa5odaRRFJc=; b=SDYv4HNzGeleVsqjws3FkXYLJjxzKf81Bn1F4eNBtGsGmlLS22fobUvrINU1M8YIcS 5SdOQ6U0qE+Iy8bWaIxVfhBCvber42WRWAb3aBL/WW+x10rGQcG1BWrWg4S36j3vbBc8 Yfg5R68aCqb4B9IqUQBYDiBTHI515YG+XsHx8= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:date:from:to:cc:subject:message-id:x-mailer:mime-version :content-type:content-transfer-encoding; b=EHmPGwe0WTMD95AxWLD4odWqd2ZeGmnrHIN0fgLWmX5cMf+zJcEoaiqWq53DzkqYfz fQ5V5sdikb1AJM6/JPXkTNYWtgcYlTXa/MRnaaIWkBYufWSdTIMHY4zyeeuUcxI/DOmM CpAWjCPPMfHB0fsv3mr+Vc4jaDaTmyrVFJll0= Received: by 10.150.35.3 with SMTP id i3mr2110298ybi.128.1257320514733; Tue, 03 Nov 2009 23:41:54 -0800 (PST) Received: from ypsilon.skybright.jp (sannin29006.nirai.ne.jp [203.160.29.6]) by mx.google.com with ESMTPS id 13sm415417gxk.9.2009.11.03.23.41.51 (version=TLSv1/SSLv3 cipher=RC4-MD5); Tue, 03 Nov 2009 23:41:53 -0800 (PST) Date: Wed, 4 Nov 2009 16:41:04 +0900 From: Yoichi Yuasa To: Ralf Baechle Cc: yuasa@linux-mips.org, linux-mips@linux-mips.org Subject: [PATCH][MIPS] add DMA declare coherent memory support Message-Id: <20091104164104.9fc315af.yuasa@linux-mips.org> X-Mailer: Sylpheed 2.7.1 (GTK+ 2.16.6; i686-pc-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24657 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: yuasa@linux-mips.org Precedence: bulk X-list: linux-mips ohci-sm501 driver require dma_declare_coherent_memory(). It is used to driver's local memory allocation with dma_alloc_coherent(). This patch works without problem on TANBAC TB0287(VR4131 + SM501). Signed-off-by: Yoichi Yuasa --- arch/mips/Kconfig | 1 + arch/mips/include/asm/dma-mapping.h | 3 +-- arch/mips/mm/dma-default.c | 7 +++++++ 3 files changed, 9 insertions(+), 2 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 03bd56a..687a438 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -3,6 +3,7 @@ config MIPS default y select HAVE_IDE select HAVE_OPROFILE + select HAVE_GENERIC_DMA_COHERENT select HAVE_ARCH_KGDB # Horrible source of confusion. Die, die, die ... select EMBEDDED diff --git a/arch/mips/include/asm/dma-mapping.h b/arch/mips/include/asm/dma-mapping.h index d16afdd..808e303 100644 --- a/arch/mips/include/asm/dma-mapping.h +++ b/arch/mips/include/asm/dma-mapping.h @@ -3,6 +3,7 @@ #include #include +#include void *dma_alloc_noncoherent(struct device *dev, size_t size, dma_addr_t *dma_handle, gfp_t flag); @@ -73,7 +74,6 @@ extern int dma_is_consistent(struct device *dev, dma_addr_t dma_addr); extern void dma_cache_sync(struct device *dev, void *vaddr, size_t size, enum dma_data_direction direction); -#if 0 #define ARCH_HAS_DMA_DECLARE_COHERENT_MEMORY extern int dma_declare_coherent_memory(struct device *dev, dma_addr_t bus_addr, @@ -81,6 +81,5 @@ extern int dma_declare_coherent_memory(struct device *dev, dma_addr_t bus_addr, extern void dma_release_declared_memory(struct device *dev); extern void * dma_mark_declared_memory_occupied(struct device *dev, dma_addr_t device_addr, size_t size); -#endif #endif /* _ASM_DMA_MAPPING_H */ diff --git a/arch/mips/mm/dma-default.c b/arch/mips/mm/dma-default.c index 7e48e76..32b43bd 100644 --- a/arch/mips/mm/dma-default.c +++ b/arch/mips/mm/dma-default.c @@ -90,6 +90,9 @@ void *dma_alloc_coherent(struct device *dev, size_t size, { void *ret; + if (dma_alloc_from_coherent(dev, size, dma_handle, &ret)) + return ret; + gfp = massage_gfp_flags(dev, gfp); ret = (void *) __get_free_pages(gfp, get_order(size)); @@ -121,8 +124,12 @@ EXPORT_SYMBOL(dma_free_noncoherent); void dma_free_coherent(struct device *dev, size_t size, void *vaddr, dma_addr_t dma_handle) { + int order = get_order(size); unsigned long addr = (unsigned long) vaddr; + if (dma_release_from_coherent(dev, order, vaddr)) + return; + plat_unmap_dma_mem(dev, dma_handle, size, DMA_BIDIRECTIONAL); if (!plat_device_is_coherent(dev)) -- 1.6.5.2 From wuzhangjin@gmail.com Wed Nov 4 10:03:04 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 04 Nov 2009 10:03:11 +0100 (CET) Received: from mail-pw0-f45.google.com ([209.85.160.45]:45071 "EHLO mail-pw0-f45.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492008AbZKDJDE (ORCPT ); Wed, 4 Nov 2009 10:03:04 +0100 Received: by pwi11 with SMTP id 11so3157807pwi.24 for ; Wed, 04 Nov 2009 01:02:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer; bh=ZN38nZ0EjfzOp0YuZCAATrHZqDUosCdKCeABKnb2VsI=; b=iYZiFLX6yCFyPMjuwQ3+Y6KnQxbVmaaiKoA0xNnrdWW7vhzGeq+8HlNf9cc7IKxvHR 2Oj/2+gIrdgHIi7/OnTNF9X98iBN5/DzdM+3SdAC2Tbu/s9/YKWeZSya3d7//PM//57Z UWjLGvZJdXAKglh0htt7W7irI37pGbg/AxYF4= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer; b=H3Ki0AWBK6VH9brXJ3DMWBS+ebc+Nt11dKXycR7UqTG2B/KB/VDSP9YvX+oqZCAlfH SPuqzhMixjhWVCqLDWNfI1Z3i0quNWcTMmpVahKwXOHylxJGxwi12auSDhuY/4STn1lu J38Ud7FtcRSONUAj9AoWtOJogUQRei/A00H/s= Received: by 10.114.165.18 with SMTP id n18mr1625220wae.154.1257325376532; Wed, 04 Nov 2009 01:02:56 -0800 (PST) Received: from localhost.localdomain ([222.92.8.142]) by mx.google.com with ESMTPS id 21sm498846pzk.7.2009.11.04.01.02.50 (version=TLSv1/SSLv3 cipher=RC4-MD5); Wed, 04 Nov 2009 01:02:56 -0800 (PST) From: Wu Zhangjin To: Ralf Baechle Cc: Wu Zhangjin , linux-mips@linux-mips.org, LKML , huhb@lemote.com, yanh@lemote.com, Zhang Le , Thomas Gleixner , Nicholas Mc Guire , zhangfx@lemote.com Subject: [PATCH -queue v0 0/6] add support for Lemote's fuloong2f Date: Wed, 4 Nov 2009 17:02:44 +0800 Message-Id: X-Mailer: git-send-email 1.6.2.1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24658 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips This patchset add the basic support for fuloong2f machine made by Lemote. fuloong2f is a loongson2f based machine, it use the 2F revision of loongson processor and AMD cs5536 south bridge. The 2E revision of loongson processor is supported by the mainline kernel yet, what we added here is the 2F specific support, including a new address window configuration module support and the cpu frequency configuration support. And for the AMD cs5536 south bridge, we add relative source code to virtualize the PCI configure space to allow it can be accessed as a normal multi-function PCI device which follows the PCI-2.2 spec. Besides, the rtc and oprofile support for fuloong2f are also added. Regards, Wu Zhangjin Wu Zhangjin (6): [loongson] add basic loongson-2f support [loongson] oprofile: avoid do_IRQ for perfcounter when the interrupt is from bonito [loongson] add basic cs5536 vsm support [loongson] add basic fuloong2f support [loongson] rtc: enable legacy RTC driver on fuloong2f [loongson] add default config file for fuloong2f arch/mips/Kconfig | 20 +- arch/mips/Makefile | 3 + arch/mips/configs/fuloong2f_defconfig | 1608 ++++++++++++++++++++ .../mips/include/asm/mach-loongson/cs5536/cs5536.h | 305 ++++ .../include/asm/mach-loongson/cs5536/cs5536_pci.h | 153 ++ .../include/asm/mach-loongson/cs5536/cs5536_vsm.h | 31 + .../mips/include/asm/mach-loongson/dma-coherence.h | 4 + arch/mips/include/asm/mach-loongson/loongson.h | 84 +- arch/mips/include/asm/mach-loongson/machine.h | 8 +- arch/mips/include/asm/mach-loongson/mem.h | 25 +- arch/mips/include/asm/mach-loongson/pci.h | 28 +- arch/mips/loongson/Kconfig | 33 + arch/mips/loongson/Makefile | 6 + arch/mips/loongson/common/Makefile | 6 + arch/mips/loongson/common/bonito-irq.c | 5 + arch/mips/loongson/common/cs5536/Makefile | 8 + arch/mips/loongson/common/cs5536/cs5536_acc.c | 150 ++ arch/mips/loongson/common/cs5536/cs5536_ehci.c | 160 ++ arch/mips/loongson/common/cs5536/cs5536_ide.c | 187 +++ arch/mips/loongson/common/cs5536/cs5536_isa.c | 322 ++++ arch/mips/loongson/common/cs5536/cs5536_ohci.c | 155 ++ arch/mips/loongson/common/cs5536/cs5536_pci.c | 89 ++ arch/mips/loongson/common/init.c | 18 + arch/mips/loongson/common/mem.c | 17 + arch/mips/loongson/common/pci.c | 8 + arch/mips/loongson/fuloong-2f/Makefile | 5 + arch/mips/loongson/fuloong-2f/irq.c | 114 ++ arch/mips/loongson/fuloong-2f/reset.c | 68 + arch/mips/oprofile/op_model_loongson2.c | 3 + arch/mips/pci/Makefile | 3 +- arch/mips/pci/fixup-fuloong2f.c | 171 +++ arch/mips/pci/ops-fuloong2e.c | 154 -- arch/mips/pci/ops-loongson2.c | 207 +++ 33 files changed, 3991 insertions(+), 167 deletions(-) create mode 100644 arch/mips/configs/fuloong2f_defconfig create mode 100644 arch/mips/include/asm/mach-loongson/cs5536/cs5536.h create mode 100644 arch/mips/include/asm/mach-loongson/cs5536/cs5536_pci.h create mode 100644 arch/mips/include/asm/mach-loongson/cs5536/cs5536_vsm.h create mode 100644 arch/mips/loongson/common/cs5536/Makefile create mode 100644 arch/mips/loongson/common/cs5536/cs5536_acc.c create mode 100644 arch/mips/loongson/common/cs5536/cs5536_ehci.c create mode 100644 arch/mips/loongson/common/cs5536/cs5536_ide.c create mode 100644 arch/mips/loongson/common/cs5536/cs5536_isa.c create mode 100644 arch/mips/loongson/common/cs5536/cs5536_ohci.c create mode 100644 arch/mips/loongson/common/cs5536/cs5536_pci.c create mode 100644 arch/mips/loongson/fuloong-2f/Makefile create mode 100644 arch/mips/loongson/fuloong-2f/irq.c create mode 100644 arch/mips/loongson/fuloong-2f/reset.c create mode 100644 arch/mips/pci/fixup-fuloong2f.c delete mode 100644 arch/mips/pci/ops-fuloong2e.c create mode 100644 arch/mips/pci/ops-loongson2.c From wuzhangjin@gmail.com Wed Nov 4 10:05:11 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 04 Nov 2009 10:05:18 +0100 (CET) Received: from mail-pw0-f45.google.com ([209.85.160.45]:59763 "EHLO mail-pw0-f45.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492008AbZKDJFL (ORCPT ); Wed, 4 Nov 2009 10:05:11 +0100 Received: by pwi11 with SMTP id 11so3158630pwi.24 for ; Wed, 04 Nov 2009 01:05:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer:in-reply-to:references; bh=elmfprYDx/eqxPVxkv4yXX5qNQq4hYj54I4zCED2nvc=; b=qEZPgB/gndp+IYDBxiIMJQbRgbm/HWCjg/2Kh5Rvh84G2d1TGDZqYYQ3kQ0XtIP8fM vCbXinS78G2Tu7lvMjDQ4Yh0vy9q1UG+mYnUeCqQcmVyVDeoTnzY4So9APAuZsE8Vfsw UazYkpsbOFe2mbO6pNLBUkcMZtm43hzl0wlGk= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; b=kse6/1/K3RCobzPQvIdfTlZ9LHzs3tbF0JypIFigIg6BL82mjDjMqZxSuBAo4G0Xnk A7DEJvglr+N0LmhuGAssRHLv0UgmPt4/nkammacldBXmZcpk+Xch8Qq4hocgyyKROSuq YVDV+nKUGWaT+vcX/PQDoI3jM42T/3r5HLAAQ= Received: by 10.114.33.29 with SMTP id g29mr1572227wag.215.1257325503861; Wed, 04 Nov 2009 01:05:03 -0800 (PST) Received: from localhost.localdomain ([222.92.8.142]) by mx.google.com with ESMTPS id 22sm494617pzk.14.2009.11.04.01.04.56 (version=TLSv1/SSLv3 cipher=RC4-MD5); Wed, 04 Nov 2009 01:05:02 -0800 (PST) From: Wu Zhangjin To: Ralf Baechle Cc: Wu Zhangjin , linux-mips@linux-mips.org, LKML , huhb@lemote.com, yanh@lemote.com, Zhang Le , Thomas Gleixner , Nicholas Mc Guire , zhangfx@lemote.com, liujl@lemote.com Subject: [PATCH -queue v0 1/6] [loongson] add basic loongson-2f support Date: Wed, 4 Nov 2009 17:04:47 +0800 Message-Id: X-Mailer: git-send-email 1.6.2.1 In-Reply-To: References: Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24659 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips Loongson2F has built-in DDR2 and PCIX controller. The PCIX controller have a similar programming interface with FPGA northbridge used in Loongson2E. The main differences between loongson-2e and loongson-2f include: 1. loongson-2f has an extra address windows configuration module, which can be used to map CPU address space to DDR or PCI address space, or map the PCI-DMA address space to DDR or LIO address space. 2. loongson-2f support 8 levels of software configurable cpu frequency, which can be configured via a register(LOONGSON_CHIPCFG0). the coming cpufreq and standby support are based on this feature. herein, the module and the corresponding operations are abstracted to loongson.h. besides, the other loongson2f-specific source code are added here, including gcc 4.4 support, pci memory space, pci io space, dma address. Signed-off-by: Wu Zhangjin --- arch/mips/Kconfig | 18 ++++ arch/mips/Makefile | 2 + .../mips/include/asm/mach-loongson/dma-coherence.h | 4 + arch/mips/include/asm/mach-loongson/loongson.h | 84 +++++++++++++++++++- arch/mips/include/asm/mach-loongson/mem.h | 25 ++++-- arch/mips/include/asm/mach-loongson/pci.h | 28 ++++++- arch/mips/loongson/common/bonito-irq.c | 5 + arch/mips/loongson/common/init.c | 18 ++++ arch/mips/loongson/common/mem.c | 17 ++++ arch/mips/loongson/common/pci.c | 8 ++ 10 files changed, 199 insertions(+), 10 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index ae9fa98..8417357 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -1059,6 +1059,21 @@ config CPU_LOONGSON2E The Loongson 2E processor implements the MIPS III instruction set with many extensions. + It has an internal FPGA northbridge, which is compatiable to + bonito64. + +config CPU_LOONGSON2F + bool "Loongson 2F" + depends on SYS_HAS_CPU_LOONGSON2F + select CPU_LOONGSON2 + help + The Loongson 2F processor implements the MIPS III instruction set + with many extensions. + + Loongson2F have built-in DDR2 and PCIX controller. The PCIX controller + have a similar programming interface with FPGA northbridge used in + Loongson2E. + config CPU_MIPS32_R1 bool "MIPS32 Release 1" depends on SYS_HAS_CPU_MIPS32_R1 @@ -1303,6 +1318,9 @@ config CPU_LOONGSON2 config SYS_HAS_CPU_LOONGSON2E bool +config SYS_HAS_CPU_LOONGSON2F + bool + config SYS_HAS_CPU_MIPS32_R1 bool diff --git a/arch/mips/Makefile b/arch/mips/Makefile index ba04782..47ecded 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -125,6 +125,8 @@ cflags-$(CONFIG_CPU_TX49XX) += -march=r4600 -Wa,--trap cflags-$(CONFIG_CPU_LOONGSON2) += -Wa,--trap cflags-$(CONFIG_CPU_LOONGSON2E) += \ $(call cc-option,-march=loongson2e,-march=r4600) +cflags-$(CONFIG_CPU_LOONGSON2F) += \ + $(call cc-option,-march=loongson2f,-march=r4600) cflags-$(CONFIG_CPU_MIPS32_R1) += $(call cc-option,-march=mips32,-mips32 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS32) \ -Wa,-mips32 -Wa,--trap diff --git a/arch/mips/include/asm/mach-loongson/dma-coherence.h b/arch/mips/include/asm/mach-loongson/dma-coherence.h index 71a6851..981c75f 100644 --- a/arch/mips/include/asm/mach-loongson/dma-coherence.h +++ b/arch/mips/include/asm/mach-loongson/dma-coherence.h @@ -28,7 +28,11 @@ static inline dma_addr_t plat_map_dma_mem_page(struct device *dev, static inline unsigned long plat_dma_addr_to_phys(struct device *dev, dma_addr_t dma_addr) { +#if defined(CONFIG_CPU_LOONGSON2F) && defined(CONFIG_64BIT) + return (dma_addr > 0x8fffffff) ? dma_addr : (dma_addr & 0x0fffffff); +#else return dma_addr & 0x7fffffff; +#endif } static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr, diff --git a/arch/mips/include/asm/mach-loongson/loongson.h b/arch/mips/include/asm/mach-loongson/loongson.h index e6869aa..9e41469 100644 --- a/arch/mips/include/asm/mach-loongson/loongson.h +++ b/arch/mips/include/asm/mach-loongson/loongson.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2009 Lemote, Inc. & Institute of Computing Technology + * Copyright (C) 2009 Lemote, Inc. * Author: Wu Zhangjin * * This program is free software; you can redistribute it and/or modify it @@ -215,4 +215,86 @@ extern void mach_irq_dispatch(unsigned int pending); #define LOONGSON_PCIMAP_WIN(WIN, ADDR) \ ((((ADDR)>>26) & LOONGSON_PCIMAP_PCIMAP_LO0) << ((WIN)*6)) +/* Chip Config */ +#ifdef CONFIG_CPU_LOONGSON2F +#define LOONGSON_CHIPCFG0 LOONGSON_REG(LOONGSON_REGBASE + 0x80) +#endif + +/* + * address windows configuration module + * + * loongson2e do not have this module + */ +#if defined(CONFIG_CPU_LOONGSON2F) && defined(CONFIG_64BIT) + +/* address window config module base address */ +#define LOONGSON_ADDRWINCFG_BASE 0x3ff00000ul +#define LOONGSON_ADDRWINCFG_SIZE 0x180 + +extern unsigned long _loongson_addrwincfg_base; +#define LOONGSON_ADDRWINCFG(offset) \ + (*(volatile u64 *)(_loongson_addrwincfg_base + (offset))) + +#define CPU_WIN0_BASE LOONGSON_ADDRWINCFG(0x00) +#define CPU_WIN1_BASE LOONGSON_ADDRWINCFG(0x08) +#define CPU_WIN2_BASE LOONGSON_ADDRWINCFG(0x10) +#define CPU_WIN3_BASE LOONGSON_ADDRWINCFG(0x18) + +#define CPU_WIN0_MASK LOONGSON_ADDRWINCFG(0x20) +#define CPU_WIN1_MASK LOONGSON_ADDRWINCFG(0x28) +#define CPU_WIN2_MASK LOONGSON_ADDRWINCFG(0x30) +#define CPU_WIN3_MASK LOONGSON_ADDRWINCFG(0x38) + +#define CPU_WIN0_MMAP LOONGSON_ADDRWINCFG(0x40) +#define CPU_WIN1_MMAP LOONGSON_ADDRWINCFG(0x48) +#define CPU_WIN2_MMAP LOONGSON_ADDRWINCFG(0x50) +#define CPU_WIN3_MMAP LOONGSON_ADDRWINCFG(0x58) + +#define PCIDMA_WIN0_BASE LOONGSON_ADDRWINCFG(0x60) +#define PCIDMA_WIN1_BASE LOONGSON_ADDRWINCFG(0x68) +#define PCIDMA_WIN2_BASE LOONGSON_ADDRWINCFG(0x70) +#define PCIDMA_WIN3_BASE LOONGSON_ADDRWINCFG(0x78) + +#define PCIDMA_WIN0_MASK LOONGSON_ADDRWINCFG(0x80) +#define PCIDMA_WIN1_MASK LOONGSON_ADDRWINCFG(0x88) +#define PCIDMA_WIN2_MASK LOONGSON_ADDRWINCFG(0x90) +#define PCIDMA_WIN3_MASK LOONGSON_ADDRWINCFG(0x98) + +#define PCIDMA_WIN0_MMAP LOONGSON_ADDRWINCFG(0xa0) +#define PCIDMA_WIN1_MMAP LOONGSON_ADDRWINCFG(0xa8) +#define PCIDMA_WIN2_MMAP LOONGSON_ADDRWINCFG(0xb0) +#define PCIDMA_WIN3_MMAP LOONGSON_ADDRWINCFG(0xb8) + +#define ADDRWIN_WIN0 0 +#define ADDRWIN_WIN1 1 +#define ADDRWIN_WIN2 2 +#define ADDRWIN_WIN3 3 + +#define ADDRWIN_MAP_DST_DDR 0 +#define ADDRWIN_MAP_DST_PCI 1 +#define ADDRWIN_MAP_DST_LIO 1 + +/* + * s: CPU, PCIDMA + * d: DDR, PCI, LIO + * win: 0, 1, 2, 3 + * src: map source + * dst: map destination + * size: ~mask + 1 + */ +#define LOONGSON_ADDRWIN_CFG(s, d, w, src, dst, size) do {\ + s##_WIN##w##_BASE = (src); \ + s##_WIN##w##_MMAP = (src) | ADDRWIN_MAP_DST_##d; \ + s##_WIN##w##_MASK = ~(size-1); \ +} while (0) + +#define LOONGSON_ADDRWIN_CPUTOPCI(win, src, dst, size) \ + LOONGSON_ADDRWIN_CFG(CPU, PCI, win, src, dst, size) +#define LOONGSON_ADDRWIN_CPUTODDR(win, src, dst, size) \ + LOONGSON_ADDRWIN_CFG(CPU, DDR, win, src, dst, size) +#define LOONGSON_ADDRWIN_PCITODDR(win, src, dst, size) \ + LOONGSON_ADDRWIN_CFG(PCIDMA, DDR, win, src, dst, size) + +#endif /* ! CONFIG_CPU_LOONGSON2F && CONFIG_64BIT */ + #endif /* __ASM_MACH_LOONGSON_LOONGSON_H */ diff --git a/arch/mips/include/asm/mach-loongson/mem.h b/arch/mips/include/asm/mach-loongson/mem.h index bd7b3cb..5c6551d 100644 --- a/arch/mips/include/asm/mach-loongson/mem.h +++ b/arch/mips/include/asm/mach-loongson/mem.h @@ -12,19 +12,30 @@ #define __ASM_MACH_LOONGSON_MEM_H /* - * On Lemote Loongson 2e + * high memory space * - * the high memory space starts from 512M. - * the peripheral registers reside between 0x1000:0000 and 0x2000:0000. + * in loongson2e, starts from 512M + * in loongson2f, starts from 2G 256M */ +#ifdef CONFIG_CPU_LOONGSON2E +#define LOONGSON_HIGHMEM_START 0x20000000 +#else +#define LOONGSON_HIGHMEM_START 0x90000000 +#endif -#ifdef CONFIG_LEMOTE_FULOONG2E - -#define LOONGSON_HIGHMEM_START 0x20000000 +/* + * the peripheral registers(MMIO): + * + * On the Lemote Loongson 2e system, reside between 0x1000:0000 and 0x2000:0000. + * On the Lemote Loongson 2f system, reside between 0x1000:0000 and 0x8000:0000. + */ #define LOONGSON_MMIO_MEM_START 0x10000000 -#define LOONGSON_MMIO_MEM_END 0x20000000 +#ifdef CONFIG_CPU_LOONGSON2E +#define LOONGSON_MMIO_MEM_END 0x20000000 +#else +#define LOONGSON_MMIO_MEM_END 0x80000000 #endif #endif /* __ASM_MACH_LOONGSON_MEM_H */ diff --git a/arch/mips/include/asm/mach-loongson/pci.h b/arch/mips/include/asm/mach-loongson/pci.h index 576487c..31ba908 100644 --- a/arch/mips/include/asm/mach-loongson/pci.h +++ b/arch/mips/include/asm/mach-loongson/pci.h @@ -1,5 +1,6 @@ /* * Copyright (c) 2008 Zhang Le + * Copyright (c) 2009 Wu Zhangjin * * This program is free software; you can redistribute it * and/or modify it under the terms of the GNU General @@ -24,7 +25,30 @@ extern struct pci_ops loongson_pci_ops; -#ifdef CONFIG_LEMOTE_FULOONG2E +/* this is an offset from mips_io_port_base */ +#define LOONGSON_PCI_IO_START 0x00004000UL + +#if defined(CONFIG_CPU_LOONGSON2F) && defined(CONFIG_64BIT) + +/* + * we use address window2 to map cpu address space to pci space + * window2: cpu [1G, 2G] -> pci [1G, 2G] + * why not use window 0 & 1? because they are used by cpu when booting. + * window0: cpu [0, 256M] -> ddr [0, 256M] + * window1: cpu [256M, 512M] -> pci [256M, 512M] + */ + +/* the smallest LOONGSON_CPU_MEM_SRC can be 512M */ +#define LOONGSON_CPU_MEM_SRC 0x40000000ul /* 1G */ +#define LOONGSON_PCI_MEM_DST LOONGSON_CPU_MEM_SRC + +#define LOONGSON_PCI_MEM_START LOONGSON_PCI_MEM_DST +#define LOONGSON_PCI_MEM_END (0x80000000ul-1) /* 2G */ + +#define MMAP_CPUTOPCI_SIZE (LOONGSON_PCI_MEM_END - \ + LOONGSON_PCI_MEM_START + 1) + +#else /* loongson2f/32bit & loongson2e */ /* this pci memory space is mapped by pcimap in pci.c */ #define LOONGSON_PCI_MEM_START LOONGSON_PCILO1_BASE @@ -32,6 +56,6 @@ extern struct pci_ops loongson_pci_ops; /* this is an offset from mips_io_port_base */ #define LOONGSON_PCI_IO_START 0x00004000UL -#endif +#endif /* !(defined(CONFIG_CPU_LOONGSON2F) && defined(CONFIG_64BIT))*/ #endif /* !__ASM_MACH_LOONGSON_PCI_H_ */ diff --git a/arch/mips/loongson/common/bonito-irq.c b/arch/mips/loongson/common/bonito-irq.c index a1cbd11..9c1ddae 100644 --- a/arch/mips/loongson/common/bonito-irq.c +++ b/arch/mips/loongson/common/bonito-irq.c @@ -35,10 +35,13 @@ static struct irq_chip bonito_irq_type = { .unmask = bonito_irq_enable, }; +/* there is no need to handle dma timeout in loongson-2f based machines */ +#ifdef CONFIG_CPU_LOONGSON2E static struct irqaction dma_timeout_irqaction = { .handler = no_action, .name = "dma_timeout", }; +#endif void bonito_irq_init(void) { @@ -47,5 +50,7 @@ void bonito_irq_init(void) for (i = LOONGSON_IRQ_BASE; i < LOONGSON_IRQ_BASE + 32; i++) set_irq_chip_and_handler(i, &bonito_irq_type, handle_level_irq); +#ifdef CONFIG_CPU_LOONGSON2E setup_irq(LOONGSON_IRQ_BASE + 10, &dma_timeout_irqaction); +#endif } diff --git a/arch/mips/loongson/common/init.c b/arch/mips/loongson/common/init.c index b7e4913..4afca97 100644 --- a/arch/mips/loongson/common/init.c +++ b/arch/mips/loongson/common/init.c @@ -14,12 +14,30 @@ #include +#if defined(CONFIG_CPU_LOONGSON2F) && defined(CONFIG_64BIT) +unsigned long _loongson_addrwincfg_base; + +/* Loongson CPU address windows config space base address */ +static inline void set_loongson_addrwincfg_base(void) +{ + *(unsigned long *)&_loongson_addrwincfg_base = (unsigned long) + ioremap(LOONGSON_ADDRWINCFG_BASE, LOONGSON_ADDRWINCFG_SIZE); + barrier(); +} +#else +static inline void set_loongson_addrwincfg_base(void) +{ +} +#endif + void __init prom_init(void) { /* init base address of io space */ set_io_port_base((unsigned long) ioremap(LOONGSON_PCIIO_BASE, LOONGSON_PCIIO_SIZE)); + set_loongson_addrwincfg_base(); + prom_init_cmdline(); prom_init_env(); prom_init_memory(); diff --git a/arch/mips/loongson/common/mem.c b/arch/mips/loongson/common/mem.c index 47a20de..45991af 100644 --- a/arch/mips/loongson/common/mem.c +++ b/arch/mips/loongson/common/mem.c @@ -21,6 +21,23 @@ void __init prom_init_memory(void) add_memory_region(memsize << 20, LOONGSON_PCI_MEM_START - (memsize << 20), BOOT_MEM_RESERVED); #ifdef CONFIG_64BIT +#ifdef CONFIG_CPU_LOONGSON2F + { + int bit; + + bit = fls(memsize + highmemsize); + if (bit != ffs(memsize + highmemsize)) + bit += 20; + else + bit = bit + 20 - 1; + + /* set cpu window3 to map CPU to DDR: 2G -> 2G */ + LOONGSON_ADDRWIN_CPUTODDR(ADDRWIN_WIN3, 0x80000000ul, + 0x80000000ul, (1 << bit)); + mmiowb(); + } +#endif /* CONFIG_CPU_LOONGSON2F */ + if (highmemsize > 0) add_memory_region(LOONGSON_HIGHMEM_START, highmemsize << 20, BOOT_MEM_RAM); diff --git a/arch/mips/loongson/common/pci.c b/arch/mips/loongson/common/pci.c index a7eb8b9..eac43b8 100644 --- a/arch/mips/loongson/common/pci.c +++ b/arch/mips/loongson/common/pci.c @@ -67,6 +67,14 @@ static void __init setup_pcimap(void) /* can not change gnt to break pci transfer when device's gnt not deassert for some broken device */ LOONGSON_PXARB_CFG = 0x00fe0105ul; + +#if defined(CONFIG_CPU_LOONGSON2F) && defined(CONFIG_64BIT) + /* + * set cpu addr window2 to map CPU address space to PCI address space + */ + LOONGSON_ADDRWIN_CPUTOPCI(ADDRWIN_WIN2, LOONGSON_CPU_MEM_SRC, + LOONGSON_PCI_MEM_DST, MMAP_CPUTOPCI_SIZE); +#endif } static int __init pcibios_init(void) -- 1.6.2.1 From wuzhangjin@gmail.com Wed Nov 4 10:05:36 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 04 Nov 2009 10:05:43 +0100 (CET) Received: from mail-pw0-f45.google.com ([209.85.160.45]:59763 "EHLO mail-pw0-f45.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492615AbZKDJFX (ORCPT ); Wed, 4 Nov 2009 10:05:23 +0100 Received: by mail-pw0-f45.google.com with SMTP id 11so3158630pwi.24 for ; Wed, 04 Nov 2009 01:05:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer:in-reply-to:references; bh=AcQ4R5dJlFioqnmx7cLQvs7Sq5EDkZx7sGAVCLDY3zc=; b=hLGy3ZV7LBOnEJCi5PWy9fFDPS0ICZzonP0uOCPExeJAygYs6002hc1LvVK3e1rt/o T/6syzaQ4N5Tdvirwac3RfIIdACzCqUWGN1bC7cLXZx1tLfxiVNXaRNiu9nzIZuDGduj zidouvYPOANHIiWfgYZHDs9YN7Rns3G4YELuA= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; b=OHSqVRYFdLyc6X87mlEIpcx+jur6oHZxOaGJ5gZ1lFI8qnFiDt8vDd3D+5arhy7VNr RqpFOb4x7Y/2kI2KOHVPHW8AM4tINocSC7zWGAlEQXG2oA410+nnrVlGvrDnppL/9DZ4 gYS9e3AqYxDPCGlneGr7s/5T6ca9/A2qDzafg= Received: by 10.114.162.5 with SMTP id k5mr1681715wae.10.1257325522596; Wed, 04 Nov 2009 01:05:22 -0800 (PST) Received: from localhost.localdomain ([222.92.8.142]) by mx.google.com with ESMTPS id 20sm498158pzk.9.2009.11.04.01.05.14 (version=TLSv1/SSLv3 cipher=RC4-MD5); Wed, 04 Nov 2009 01:05:22 -0800 (PST) From: Wu Zhangjin To: Ralf Baechle Cc: Wu Zhangjin , linux-mips@linux-mips.org, LKML , huhb@lemote.com, yanh@lemote.com, Zhang Le , Thomas Gleixner , Nicholas Mc Guire , zhangfx@lemote.com, liujl@lemote.com Subject: [PATCH -queue v0 2/6] [loongson] oprofile: avoid do_IRQ for perfcounter when the interrupt is from bonito Date: Wed, 4 Nov 2009 17:05:08 +0800 Message-Id: <061879e220036f930cd1cf5a6d22fca4d2be255c.1257325319.git.wuzhangjin@gmail.com> X-Mailer: git-send-email 1.6.2.1 In-Reply-To: References: Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24660 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips In loongson2f, the IP6 is shared by bonito and perfcounter, we need to avoid do_IRQ for perfcounter when the interrupt is from bonito. This patch does it. Signed-off-by: Wu Zhangjin --- arch/mips/oprofile/op_model_loongson2.c | 3 +++ 1 files changed, 3 insertions(+), 0 deletions(-) diff --git a/arch/mips/oprofile/op_model_loongson2.c b/arch/mips/oprofile/op_model_loongson2.c index 575cd14..08d4b09 100644 --- a/arch/mips/oprofile/op_model_loongson2.c +++ b/arch/mips/oprofile/op_model_loongson2.c @@ -125,6 +125,9 @@ static irqreturn_t loongson2_perfcount_handler(int irq, void *dev_id) */ /* Check whether the irq belongs to me */ + enabled = read_c0_perfcnt() & LOONGSON2_PERFCNT_INT_EN; + if (!enabled) + return IRQ_NONE; enabled = reg.cnt1_enabled | reg.cnt2_enabled; if (!enabled) return IRQ_NONE; -- 1.6.2.1 From wuzhangjin@gmail.com Wed Nov 4 10:06:01 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 04 Nov 2009 10:06:09 +0100 (CET) Received: from mail-pw0-f45.google.com ([209.85.160.45]:59763 "EHLO mail-pw0-f45.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492677AbZKDJFm (ORCPT ); Wed, 4 Nov 2009 10:05:42 +0100 Received: by mail-pw0-f45.google.com with SMTP id 11so3158630pwi.24 for ; Wed, 04 Nov 2009 01:05:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer:in-reply-to:references; bh=w4zVIf8vQX+bXRmKFNSPzTVM7P1ByqIdrrrGA3zolfI=; b=xMzlCX+I1qOWLn67ztHW9ELysLCg5sF1U+Lyk3ztgWXqnvqXYxn+TeXQKJ1qoCXxoJ ZR5jcLwxsn2p7cpYKY1vb49JhMhzsUIVD6Ah9gRTkTbNergSQ3Oy5r4ArjCvPHuO7GWj oKdMJFRXV/BEbOeQQNIpL5LFyPjUcNsPqSjt4= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; b=WIMp94vCE6IFU05nsQ9AhHOU479yr8RXeWzCuE4MSXoOMH9zgPpnqQwyPbkamsUeYA hLIaFY5ji8RcDsCUN2V6i9t0nuCrQGHvexP/2ZHIHL8C4V6l6ZM8/dAA4GTjMo1QKwNZ cepxrno16P2lXvVw5XonmuLBAqzgR3nnzgzOg= Received: by 10.115.80.6 with SMTP id h6mr1660894wal.108.1257325541417; Wed, 04 Nov 2009 01:05:41 -0800 (PST) Received: from localhost.localdomain ([222.92.8.142]) by mx.google.com with ESMTPS id 23sm512701pxi.5.2009.11.04.01.05.33 (version=TLSv1/SSLv3 cipher=RC4-MD5); Wed, 04 Nov 2009 01:05:40 -0800 (PST) From: Wu Zhangjin To: Ralf Baechle Cc: Wu Zhangjin , linux-mips@linux-mips.org, LKML , huhb@lemote.com, yanh@lemote.com, Zhang Le , Thomas Gleixner , Nicholas Mc Guire , zhangfx@lemote.com, liujl@lemote.com Subject: [PATCH -queue v0 3/6] [loongson] add basic cs5536 vsm support Date: Wed, 4 Nov 2009 17:05:28 +0800 Message-Id: <6d5b947065d939155460c05d24d56e9fbb417680.1257325319.git.wuzhangjin@gmail.com> X-Mailer: git-send-email 1.6.2.1 In-Reply-To: References: Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24661 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips This patch provide the read/write interfaces for Virtual Support Module(VSM, includes isa, ide, acc, ohci, ehci), fuloong2f and yeeloong2f use cs5536 as their south bridge, need this lowlevel interfaces to access the devices connectted to cs5536. Signed-off-by: Wu Zhangjin --- .../mips/include/asm/mach-loongson/cs5536/cs5536.h | 305 ++++++++++++++++++ .../include/asm/mach-loongson/cs5536/cs5536_pci.h | 153 +++++++++ .../include/asm/mach-loongson/cs5536/cs5536_vsm.h | 31 ++ arch/mips/loongson/Kconfig | 3 + arch/mips/loongson/common/Makefile | 6 + arch/mips/loongson/common/cs5536/Makefile | 8 + arch/mips/loongson/common/cs5536/cs5536_acc.c | 150 +++++++++ arch/mips/loongson/common/cs5536/cs5536_ehci.c | 160 ++++++++++ arch/mips/loongson/common/cs5536/cs5536_ide.c | 187 ++++++++++++ arch/mips/loongson/common/cs5536/cs5536_isa.c | 322 ++++++++++++++++++++ arch/mips/loongson/common/cs5536/cs5536_ohci.c | 155 ++++++++++ arch/mips/loongson/common/cs5536/cs5536_pci.c | 89 ++++++ 12 files changed, 1569 insertions(+), 0 deletions(-) create mode 100644 arch/mips/include/asm/mach-loongson/cs5536/cs5536.h create mode 100644 arch/mips/include/asm/mach-loongson/cs5536/cs5536_pci.h create mode 100644 arch/mips/include/asm/mach-loongson/cs5536/cs5536_vsm.h create mode 100644 arch/mips/loongson/common/cs5536/Makefile create mode 100644 arch/mips/loongson/common/cs5536/cs5536_acc.c create mode 100644 arch/mips/loongson/common/cs5536/cs5536_ehci.c create mode 100644 arch/mips/loongson/common/cs5536/cs5536_ide.c create mode 100644 arch/mips/loongson/common/cs5536/cs5536_isa.c create mode 100644 arch/mips/loongson/common/cs5536/cs5536_ohci.c create mode 100644 arch/mips/loongson/common/cs5536/cs5536_pci.c diff --git a/arch/mips/include/asm/mach-loongson/cs5536/cs5536.h b/arch/mips/include/asm/mach-loongson/cs5536/cs5536.h new file mode 100644 index 0000000..021f77c --- /dev/null +++ b/arch/mips/include/asm/mach-loongson/cs5536/cs5536.h @@ -0,0 +1,305 @@ +/* + * The header file of cs5536 sourth bridge. + * + * Copyright (C) 2007 Lemote, Inc. + * Author : jlliu + */ + +#ifndef _CS5536_H +#define _CS5536_H + +#include + +extern void _rdmsr(u32 msr, u32 *hi, u32 *lo); +extern void _wrmsr(u32 msr, u32 hi, u32 lo); + +/* + * MSR module base + */ +#define CS5536_SB_MSR_BASE (0x00000000) +#define CS5536_GLIU_MSR_BASE (0x10000000) +#define CS5536_ILLEGAL_MSR_BASE (0x20000000) +#define CS5536_USB_MSR_BASE (0x40000000) +#define CS5536_IDE_MSR_BASE (0x60000000) +#define CS5536_DIVIL_MSR_BASE (0x80000000) +#define CS5536_ACC_MSR_BASE (0xa0000000) +#define CS5536_UNUSED_MSR_BASE (0xc0000000) +#define CS5536_GLCP_MSR_BASE (0xe0000000) + +#define SB_MSR_REG(offset) (CS5536_SB_MSR_BASE | (offset)) +#define GLIU_MSR_REG(offset) (CS5536_GLIU_MSR_BASE | (offset)) +#define ILLEGAL_MSR_REG(offset) (CS5536_ILLEGAL_MSR_BASE | (offset)) +#define USB_MSR_REG(offset) (CS5536_USB_MSR_BASE | (offset)) +#define IDE_MSR_REG(offset) (CS5536_IDE_MSR_BASE | (offset)) +#define DIVIL_MSR_REG(offset) (CS5536_DIVIL_MSR_BASE | (offset)) +#define ACC_MSR_REG(offset) (CS5536_ACC_MSR_BASE | (offset)) +#define UNUSED_MSR_REG(offset) (CS5536_UNUSED_MSR_BASE | (offset)) +#define GLCP_MSR_REG(offset) (CS5536_GLCP_MSR_BASE | (offset)) + +/* + * BAR SPACE OF VIRTUAL PCI : + * range for pci probe use, length is the actual size. + */ +/* IO space for all DIVIL modules */ +#define CS5536_IRQ_RANGE 0xffffffe0 /* USERD FOR PCI PROBE */ +#define CS5536_IRQ_LENGTH 0x20 /* THE REGS ACTUAL LENGTH */ +#define CS5536_SMB_RANGE 0xfffffff8 +#define CS5536_SMB_LENGTH 0x08 +#define CS5536_GPIO_RANGE 0xffffff00 +#define CS5536_GPIO_LENGTH 0x100 +#define CS5536_MFGPT_RANGE 0xffffffc0 +#define CS5536_MFGPT_LENGTH 0x40 +#define CS5536_ACPI_RANGE 0xffffffe0 +#define CS5536_ACPI_LENGTH 0x20 +#define CS5536_PMS_RANGE 0xffffff80 +#define CS5536_PMS_LENGTH 0x80 +/* IO space for IDE */ +#define CS5536_IDE_RANGE 0xfffffff0 +#define CS5536_IDE_LENGTH 0x10 +/* IO space for ACC */ +#define CS5536_ACC_RANGE 0xffffff80 +#define CS5536_ACC_LENGTH 0x80 +/* MEM space for ALL USB modules */ +#define CS5536_OHCI_RANGE 0xfffff000 +#define CS5536_OHCI_LENGTH 0x1000 +#define CS5536_EHCI_RANGE 0xfffff000 +#define CS5536_EHCI_LENGTH 0x1000 + +/* + * PCI MSR ACCESS + */ +#define PCI_MSR_CTRL 0xF0 +#define PCI_MSR_ADDR 0xF4 +#define PCI_MSR_DATA_LO 0xF8 +#define PCI_MSR_DATA_HI 0xFC + +/**************** MSR *****************************/ + +/* + * GLIU STANDARD MSR + */ +#define GLIU_CAP 0x00 +#define GLIU_CONFIG 0x01 +#define GLIU_SMI 0x02 +#define GLIU_ERROR 0x03 +#define GLIU_PM 0x04 +#define GLIU_DIAG 0x05 + +/* + * GLIU SPEC. MSR + */ +#define GLIU_P2D_BM0 0x20 +#define GLIU_P2D_BM1 0x21 +#define GLIU_P2D_BM2 0x22 +#define GLIU_P2D_BMK0 0x23 +#define GLIU_P2D_BMK1 0x24 +#define GLIU_P2D_BM3 0x25 +#define GLIU_P2D_BM4 0x26 +#define GLIU_COH 0x80 +#define GLIU_PAE 0x81 +#define GLIU_ARB 0x82 +#define GLIU_ASMI 0x83 +#define GLIU_AERR 0x84 +#define GLIU_DEBUG 0x85 +#define GLIU_PHY_CAP 0x86 +#define GLIU_NOUT_RESP 0x87 +#define GLIU_NOUT_WDATA 0x88 +#define GLIU_WHOAMI 0x8B +#define GLIU_SLV_DIS 0x8C +#define GLIU_IOD_BM0 0xE0 +#define GLIU_IOD_BM1 0xE1 +#define GLIU_IOD_BM2 0xE2 +#define GLIU_IOD_BM3 0xE3 +#define GLIU_IOD_BM4 0xE4 +#define GLIU_IOD_BM5 0xE5 +#define GLIU_IOD_BM6 0xE6 +#define GLIU_IOD_BM7 0xE7 +#define GLIU_IOD_BM8 0xE8 +#define GLIU_IOD_BM9 0xE9 +#define GLIU_IOD_SC0 0xEA +#define GLIU_IOD_SC1 0xEB +#define GLIU_IOD_SC2 0xEC +#define GLIU_IOD_SC3 0xED +#define GLIU_IOD_SC4 0xEE +#define GLIU_IOD_SC5 0xEF +#define GLIU_IOD_SC6 0xF0 +#define GLIU_IOD_SC7 0xF1 + +/* + * SB STANDARD + */ +#define SB_CAP 0x00 +#define SB_CONFIG 0x01 +#define SB_SMI 0x02 +#define SB_ERROR 0x03 +#define SB_MAR_ERR_EN 0x00000001 +#define SB_TAR_ERR_EN 0x00000002 +#define SB_RSVD_BIT1 0x00000004 +#define SB_EXCEP_ERR_EN 0x00000008 +#define SB_SYSE_ERR_EN 0x00000010 +#define SB_PARE_ERR_EN 0x00000020 +#define SB_TAS_ERR_EN 0x00000040 +#define SB_MAR_ERR_FLAG 0x00010000 +#define SB_TAR_ERR_FLAG 0x00020000 +#define SB_RSVD_BIT2 0x00040000 +#define SB_EXCEP_ERR_FLAG 0x00080000 +#define SB_SYSE_ERR_FLAG 0x00100000 +#define SB_PARE_ERR_FLAG 0x00200000 +#define SB_TAS_ERR_FLAG 0x00400000 +#define SB_PM 0x04 +#define SB_DIAG 0x05 + +/* + * SB SPEC. + */ +#define SB_CTRL 0x10 +#define SB_R0 0x20 +#define SB_R1 0x21 +#define SB_R2 0x22 +#define SB_R3 0x23 +#define SB_R4 0x24 +#define SB_R5 0x25 +#define SB_R6 0x26 +#define SB_R7 0x27 +#define SB_R8 0x28 +#define SB_R9 0x29 +#define SB_R10 0x2A +#define SB_R11 0x2B +#define SB_R12 0x2C +#define SB_R13 0x2D +#define SB_R14 0x2E +#define SB_R15 0x2F + +/* + * GLCP STANDARD + */ +#define GLCP_CAP 0x00 +#define GLCP_CONFIG 0x01 +#define GLCP_SMI 0x02 +#define GLCP_ERROR 0x03 +#define GLCP_PM 0x04 +#define GLCP_DIAG 0x05 + +/* + * GLCP SPEC. + */ +#define GLCP_CLK_DIS_DELAY 0x08 +#define GLCP_PM_CLK_DISABLE 0x09 +#define GLCP_GLB_PM 0x0B +#define GLCP_DBG_OUT 0x0C +#define GLCP_RSVD1 0x0D +#define GLCP_SOFT_COM 0x0E +#define SOFT_BAR_SMB_FLAG 0x00000001 +#define SOFT_BAR_GPIO_FLAG 0x00000002 +#define SOFT_BAR_MFGPT_FLAG 0x00000004 +#define SOFT_BAR_IRQ_FLAG 0x00000008 +#define SOFT_BAR_PMS_FLAG 0x00000010 +#define SOFT_BAR_ACPI_FLAG 0x00000020 +#define SOFT_BAR_IDE_FLAG 0x00000400 +#define SOFT_BAR_ACC_FLAG 0x00000800 +#define SOFT_BAR_OHCI_FLAG 0x00001000 +#define SOFT_BAR_EHCI_FLAG 0x00002000 +#define GLCP_RSVD2 0x0F +#define GLCP_CLK_OFF 0x10 +#define GLCP_CLK_ACTIVE 0x11 +#define GLCP_CLK_DISABLE 0x12 +#define GLCP_CLK4ACK 0x13 +#define GLCP_SYS_RST 0x14 +#define GLCP_RSVD3 0x15 +#define GLCP_DBG_CLK_CTRL 0x16 +#define GLCP_CHIP_REV_ID 0x17 + +/* PIC */ +#define PIC_YSEL_LOW 0x20 +#define PIC_YSEL_LOW_USB_SHIFT 8 +#define PIC_YSEL_LOW_ACC_SHIFT 16 +#define PIC_YSEL_LOW_FLASH_SHIFT 24 +#define PIC_YSEL_HIGH 0x21 +#define PIC_ZSEL_LOW 0x22 +#define PIC_ZSEL_HIGH 0x23 +#define PIC_IRQM_PRIM 0x24 +#define PIC_IRQM_LPC 0x25 +#define PIC_XIRR_STS_LOW 0x26 +#define PIC_XIRR_STS_HIGH 0x27 +#define PCI_SHDW 0x34 + +/* + * DIVIL STANDARD + */ +#define DIVIL_CAP 0x00 +#define DIVIL_CONFIG 0x01 +#define DIVIL_SMI 0x02 +#define DIVIL_ERROR 0x03 +#define DIVIL_PM 0x04 +#define DIVIL_DIAG 0x05 + +/* + * DIVIL SPEC. + */ +#define DIVIL_LBAR_IRQ 0x08 +#define DIVIL_LBAR_KEL 0x09 +#define DIVIL_LBAR_SMB 0x0B +#define DIVIL_LBAR_GPIO 0x0C +#define DIVIL_LBAR_MFGPT 0x0D +#define DIVIL_LBAR_ACPI 0x0E +#define DIVIL_LBAR_PMS 0x0F +#define DIVIL_LEG_IO 0x14 +#define DIVIL_BALL_OPTS 0x15 +#define DIVIL_SOFT_IRQ 0x16 +#define DIVIL_SOFT_RESET 0x17 + +/* MFGPT */ +#define MFGPT_IRQ 0x28 + +/* + * IDE STANDARD + */ +#define IDE_CAP 0x00 +#define IDE_CONFIG 0x01 +#define IDE_SMI 0x02 +#define IDE_ERROR 0x03 +#define IDE_PM 0x04 +#define IDE_DIAG 0x05 + +/* + * IDE SPEC. + */ +#define IDE_IO_BAR 0x08 +#define IDE_CFG 0x10 +#define IDE_DTC 0x12 +#define IDE_CAST 0x13 +#define IDE_ETC 0x14 +#define IDE_INTERNAL_PM 0x15 + +/* + * ACC STANDARD + */ +#define ACC_CAP 0x00 +#define ACC_CONFIG 0x01 +#define ACC_SMI 0x02 +#define ACC_ERROR 0x03 +#define ACC_PM 0x04 +#define ACC_DIAG 0x05 + +/* + * USB STANDARD + */ +#define USB_CAP 0x00 +#define USB_CONFIG 0x01 +#define USB_SMI 0x02 +#define USB_ERROR 0x03 +#define USB_PM 0x04 +#define USB_DIAG 0x05 + +/* + * USB SPEC. + */ +#define USB_OHCI 0x08 +#define USB_EHCI 0x09 + +/****************** NATIVE ***************************/ +/* GPIO : I/O SPACE; REG : 32BITS */ +#define GPIOL_OUT_VAL 0x00 +#define GPIOL_OUT_EN 0x04 + +#endif /* _CS5536_H */ diff --git a/arch/mips/include/asm/mach-loongson/cs5536/cs5536_pci.h b/arch/mips/include/asm/mach-loongson/cs5536/cs5536_pci.h new file mode 100644 index 0000000..0dca9c8 --- /dev/null +++ b/arch/mips/include/asm/mach-loongson/cs5536/cs5536_pci.h @@ -0,0 +1,153 @@ +/* + * the definition file of cs5536 Virtual Support Module(VSM). + * pci configuration space can be accessed through the VSM, so + * there is no need of the MSR read/write now, except the spec. + * MSR registers which are not implemented yet. + * + * Copyright (C) 2007 Lemote Inc. + * Author : jlliu, liujl@lemote.com + */ + +#ifndef _CS5536_PCI_H +#define _CS5536_PCI_H + +#include +#include + +extern void cs5536_pci_conf_write4(int function, int reg, u32 value); +extern u32 cs5536_pci_conf_read4(int function, int reg); + +#define CS5536_ACC_INTR 9 +#define CS5536_IDE_INTR 14 +#define CS5536_USB_INTR 11 +#define CS5536_MFGPT_INTR 5 +#define CS5536_UART1_INTR 4 +#define CS5536_UART2_INTR 3 + +/************** PCI BUS DEVICE FUNCTION ***************/ + +/* + * PCI bus device function + */ +#define PCI_BUS_CS5536 0 +#define PCI_IDSEL_CS5536 14 + +/********** STANDARD PCI-2.2 EXPANSION ****************/ + +/* + * PCI configuration space + * we have to virtualize the PCI configure space head, so we should + * define the necessary IDs and some others. + */ + +/* CONFIG of PCI VENDOR ID*/ +#define CFG_PCI_VENDOR_ID(mod_dev_id, sys_vendor_id) \ + (((mod_dev_id) << 16) | (sys_vendor_id)) + +/* VENDOR ID */ +#define CS5536_VENDOR_ID 0x1022 + +/* DEVICE ID */ +#define CS5536_ISA_DEVICE_ID 0x2090 +#define CS5536_IDE_DEVICE_ID 0x209a +#define CS5536_ACC_DEVICE_ID 0x2093 +#define CS5536_OHCI_DEVICE_ID 0x2094 +#define CS5536_EHCI_DEVICE_ID 0x2095 + +/* CLASS CODE : CLASS SUB-CLASS INTERFACE */ +#define CS5536_ISA_CLASS_CODE 0x060100 +#define CS5536_IDE_CLASS_CODE 0x010180 +#define CS5536_ACC_CLASS_CODE 0x040100 +#define CS5536_OHCI_CLASS_CODE 0x0C0310 +#define CS5536_EHCI_CLASS_CODE 0x0C0320 + +/* BHLC : BIST HEADER-TYPE LATENCY-TIMER CACHE-LINE-SIZE */ + +#define CFG_PCI_CACHE_LINE_SIZE(header_type, latency_timer) \ + ((PCI_NONE_BIST << 24) | ((header_type) << 16) \ + | ((latency_timer) << 8) | PCI_NORMAL_CACHE_LINE_SIZE); + +#define PCI_NONE_BIST 0x00 /* RO not implemented yet. */ +#define PCI_BRIDGE_HEADER_TYPE 0x80 /* RO */ +#define PCI_NORMAL_HEADER_TYPE 0x00 +#define PCI_NORMAL_LATENCY_TIMER 0x00 +#define PCI_NORMAL_CACHE_LINE_SIZE 0x08 /* RW */ + +/* BAR */ +#define PCI_BAR0_REG 0x10 +#define PCI_BAR1_REG 0x14 +#define PCI_BAR2_REG 0x18 +#define PCI_BAR3_REG 0x1c +#define PCI_BAR4_REG 0x20 +#define PCI_BAR5_REG 0x24 +#define PCI_BAR_COUNT 6 +#define PCI_BAR_RANGE_MASK 0xFFFFFFFF + +/* CARDBUS CIS POINTER */ +#define PCI_CARDBUS_CIS_POINTER 0x00000000 + +/* SUBSYSTEM VENDOR ID */ +#define CS5536_SUB_VENDOR_ID CS5536_VENDOR_ID + +/* SUBSYSTEM ID */ +#define CS5536_ISA_SUB_ID CS5536_ISA_DEVICE_ID +#define CS5536_IDE_SUB_ID CS5536_IDE_DEVICE_ID +#define CS5536_ACC_SUB_ID CS5536_ACC_DEVICE_ID +#define CS5536_OHCI_SUB_ID CS5536_OHCI_DEVICE_ID +#define CS5536_EHCI_SUB_ID CS5536_EHCI_DEVICE_ID + +/* EXPANSION ROM BAR */ +#define PCI_EXPANSION_ROM_BAR 0x00000000 + +/* CAPABILITIES POINTER */ +#define PCI_CAPLIST_POINTER 0x00000000 +#define PCI_CAPLIST_USB_POINTER 0x40 +/* INTERRUPT */ + +#define CFG_PCI_INTERRUPT_LINE(pin, mod_intr) \ + ((PCI_MAX_LATENCY << 24) | (PCI_MIN_GRANT << 16) | \ + ((pin) << 8) | (mod_intr)) + +#define PCI_MAX_LATENCY 0x40 +#define PCI_MIN_GRANT 0x00 +#define PCI_DEFAULT_PIN 0x01 + +/*********** EXPANSION PCI REG ************************/ + +/* + * ISA EXPANSION + */ +#define PCI_UART1_INT_REG 0x50 +#define PCI_UART2_INT_REG 0x54 +#define PCI_ISA_FIXUP_REG 0x58 + +/* + * IDE EXPANSION + */ +#define PCI_IDE_CFG_REG 0x40 +#define CS5536_IDE_FLASH_SIGNATURE 0xDEADBEEF +#define PCI_IDE_DTC_REG 0x48 +#define PCI_IDE_CAST_REG 0x4C +#define PCI_IDE_ETC_REG 0x50 +#define PCI_IDE_PM_REG 0x54 +#define PCI_IDE_INT_REG 0x60 + +/* + * ACC EXPANSION + */ +#define PCI_ACC_INT_REG 0x50 + +/* + * OHCI EXPANSION : INTTERUPT IS IMPLEMENTED BY THE OHCI + */ +#define PCI_OHCI_PM_REG 0x40 +#define PCI_OHCI_INT_REG 0x50 + +/* + * EHCI EXPANSION + */ +#define PCI_EHCI_LEGSMIEN_REG 0x50 +#define PCI_EHCI_LEGSMISTS_REG 0x54 +#define PCI_EHCI_FLADJ_REG 0x60 + +#endif /* _CS5536_PCI_H_ */ diff --git a/arch/mips/include/asm/mach-loongson/cs5536/cs5536_vsm.h b/arch/mips/include/asm/mach-loongson/cs5536/cs5536_vsm.h new file mode 100644 index 0000000..6305bea --- /dev/null +++ b/arch/mips/include/asm/mach-loongson/cs5536/cs5536_vsm.h @@ -0,0 +1,31 @@ +/* + * the read/write interfaces for Virtual Support Module(VSM) + * + * Copyright (C) 2009 Lemote, Inc. + * Author: Wu Zhangjin + */ + +#ifndef _CS5536_VSM_H +#define _CS5536_VSM_H + +#include + +typedef void (*cs5536_pci_vsm_write)(int reg, u32 value); +typedef u32 (*cs5536_pci_vsm_read)(int reg); + +#define DECLARE_CS5536_MODULE(name) \ +extern void pci_##name##_write_reg(int reg, u32 value); \ +extern u32 pci_##name##_read_reg(int reg); + +/* ide module */ +DECLARE_CS5536_MODULE(ide) +/* acc module */ +DECLARE_CS5536_MODULE(acc) +/* ohci module */ +DECLARE_CS5536_MODULE(ohci) +/* isa module */ +DECLARE_CS5536_MODULE(isa) +/* ehci module */ +DECLARE_CS5536_MODULE(ehci) + +#endif /* _CS5536_VSM_H */ diff --git a/arch/mips/loongson/Kconfig b/arch/mips/loongson/Kconfig index 818a028..b03d773 100644 --- a/arch/mips/loongson/Kconfig +++ b/arch/mips/loongson/Kconfig @@ -29,3 +29,6 @@ config LEMOTE_FULOONG2E Lemote Fuloong(2e) mini PC have a VIA686B south bridge. endchoice + +config CS5536 + bool diff --git a/arch/mips/loongson/common/Makefile b/arch/mips/loongson/common/Makefile index d21d116..d3138b8 100644 --- a/arch/mips/loongson/common/Makefile +++ b/arch/mips/loongson/common/Makefile @@ -10,3 +10,9 @@ obj-y += setup.o init.o cmdline.o env.o time.o reset.o irq.o \ # obj-$(CONFIG_EARLY_PRINTK) += early_printk.o obj-$(CONFIG_SERIAL_8250) += serial.o + +# +# Enable CS5536 Virtual Support Module(VSM) to virtulize the PCI configure +# space +# +obj-$(CONFIG_CS5536) += cs5536/ diff --git a/arch/mips/loongson/common/cs5536/Makefile b/arch/mips/loongson/common/cs5536/Makefile new file mode 100644 index 0000000..31657ee --- /dev/null +++ b/arch/mips/loongson/common/cs5536/Makefile @@ -0,0 +1,8 @@ +# +# Makefile for CS5536 support. +# + +obj-$(CONFIG_CS5536) += cs5536_pci.o cs5536_ide.o cs5536_acc.o cs5536_ohci.o \ + cs5536_isa.o cs5536_ehci.o + +EXTRA_CFLAGS += -Werror diff --git a/arch/mips/loongson/common/cs5536/cs5536_acc.c b/arch/mips/loongson/common/cs5536/cs5536_acc.c new file mode 100644 index 0000000..55b3d7a --- /dev/null +++ b/arch/mips/loongson/common/cs5536/cs5536_acc.c @@ -0,0 +1,150 @@ +/* + * the ACC Virtual Support Module of AMD CS5536 + * + * Copyright (C) 2007 Lemote, Inc. + * Author : jlliu, liujl@lemote.com + * + * Copyright (C) 2009 Lemote, Inc. + * Author: Wu Zhangjin, wuzj@lemote.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include +#include + +/* + * acc_write: acc write transfering + */ + +void pci_acc_write_reg(int reg, u32 value) +{ + u32 hi = 0, lo = value; + + switch (reg) { + case PCI_COMMAND: + _rdmsr(GLIU_MSR_REG(GLIU_PAE), &hi, &lo); + if (value & PCI_COMMAND_MASTER) + lo |= (0x03 << 8); + else + lo &= ~(0x03 << 8); + _wrmsr(GLIU_MSR_REG(GLIU_PAE), hi, lo); + break; + case PCI_STATUS: + if (value & PCI_STATUS_PARITY) { + _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo); + if (lo & SB_PARE_ERR_FLAG) { + lo = (lo & 0x0000ffff) | SB_PARE_ERR_FLAG; + _wrmsr(SB_MSR_REG(SB_ERROR), hi, lo); + } + } + break; + case PCI_BAR0_REG: + if (value == PCI_BAR_RANGE_MASK) { + _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo); + lo |= SOFT_BAR_ACC_FLAG; + _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo); + } else if (value & 0x01) { + value &= 0xfffffffc; + hi = 0xA0000000 | ((value & 0x000ff000) >> 12); + lo = 0x000fff80 | ((value & 0x00000fff) << 20); + _wrmsr(GLIU_MSR_REG(GLIU_IOD_BM1), hi, lo); + } + break; + case PCI_ACC_INT_REG: + _rdmsr(DIVIL_MSR_REG(PIC_YSEL_LOW), &hi, &lo); + /* disable all the usb interrupt in PIC */ + lo &= ~(0xf << PIC_YSEL_LOW_ACC_SHIFT); + if (value) /* enable all the acc interrupt in PIC */ + lo |= (CS5536_ACC_INTR << PIC_YSEL_LOW_ACC_SHIFT); + _wrmsr(DIVIL_MSR_REG(PIC_YSEL_LOW), hi, lo); + break; + default: + break; + } + + return; +} + +/* + * acc_read: acc read transfering + */ + +u32 pci_acc_read_reg(int reg) +{ + u32 hi, lo; + u32 conf_data = 0; + + switch (reg) { + case PCI_VENDOR_ID: + conf_data = + CFG_PCI_VENDOR_ID(CS5536_ACC_DEVICE_ID, CS5536_VENDOR_ID); + break; + case PCI_COMMAND: + _rdmsr(GLIU_MSR_REG(GLIU_IOD_BM1), &hi, &lo); + if (((lo & 0xfff00000) || (hi & 0x000000ff)) + && ((hi & 0xf0000000) == 0xa0000000)) + conf_data |= PCI_COMMAND_IO; + _rdmsr(GLIU_MSR_REG(GLIU_PAE), &hi, &lo); + if ((lo & 0x300) == 0x300) + conf_data |= PCI_COMMAND_MASTER; + break; + case PCI_STATUS: + conf_data |= PCI_STATUS_66MHZ; + conf_data |= PCI_STATUS_FAST_BACK; + _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo); + if (lo & SB_PARE_ERR_FLAG) + conf_data |= PCI_STATUS_PARITY; + conf_data |= PCI_STATUS_DEVSEL_MEDIUM; + break; + case PCI_CLASS_REVISION: + _rdmsr(ACC_MSR_REG(ACC_CAP), &hi, &lo); + conf_data = lo & 0x000000ff; + conf_data |= (CS5536_ACC_CLASS_CODE << 8); + break; + case PCI_CACHE_LINE_SIZE: + conf_data = + CFG_PCI_CACHE_LINE_SIZE(PCI_NORMAL_HEADER_TYPE, + PCI_NORMAL_LATENCY_TIMER); + break; + case PCI_BAR0_REG: + _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo); + if (lo & SOFT_BAR_ACC_FLAG) { + conf_data = CS5536_ACC_RANGE | + PCI_BASE_ADDRESS_SPACE_IO; + lo &= ~SOFT_BAR_ACC_FLAG; + _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo); + } else { + _rdmsr(GLIU_MSR_REG(GLIU_IOD_BM1), &hi, &lo); + conf_data = (hi & 0x000000ff) << 12; + conf_data |= (lo & 0xfff00000) >> 20; + conf_data |= 0x01; + conf_data &= ~0x02; + } + break; + case PCI_CARDBUS_CIS: + conf_data = PCI_CARDBUS_CIS_POINTER; + break; + case PCI_SUBSYSTEM_VENDOR_ID: + conf_data = + CFG_PCI_VENDOR_ID(CS5536_ACC_SUB_ID, CS5536_SUB_VENDOR_ID); + break; + case PCI_ROM_ADDRESS: + conf_data = PCI_EXPANSION_ROM_BAR; + break; + case PCI_CAPABILITY_LIST: + conf_data = PCI_CAPLIST_USB_POINTER; + break; + case PCI_INTERRUPT_LINE: + conf_data = + CFG_PCI_INTERRUPT_LINE(PCI_DEFAULT_PIN, CS5536_ACC_INTR); + break; + default: + break; + } + + return conf_data; +} diff --git a/arch/mips/loongson/common/cs5536/cs5536_ehci.c b/arch/mips/loongson/common/cs5536/cs5536_ehci.c new file mode 100644 index 0000000..d1d9aa9 --- /dev/null +++ b/arch/mips/loongson/common/cs5536/cs5536_ehci.c @@ -0,0 +1,160 @@ +/* + * the EHCI Virtual Support Module of AMD CS5536 + * + * Copyright (C) 2007 Lemote, Inc. + * Author : jlliu, liujl@lemote.com + * + * Copyright (C) 2009 Lemote, Inc. + * Author: Wu Zhangjin, wuzj@lemote.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include +#include + +void pci_ehci_write_reg(int reg, u32 value) +{ + u32 hi = 0, lo = value; + + switch (reg) { + case PCI_COMMAND: + _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo); + if (value & PCI_COMMAND_MASTER) + hi |= PCI_COMMAND_MASTER; + else + hi &= ~PCI_COMMAND_MASTER; + + if (value & PCI_COMMAND_MEMORY) + hi |= PCI_COMMAND_MEMORY; + else + hi &= ~PCI_COMMAND_MEMORY; + _wrmsr(USB_MSR_REG(USB_EHCI), hi, lo); + break; + case PCI_STATUS: + if (value & PCI_STATUS_PARITY) { + _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo); + if (lo & SB_PARE_ERR_FLAG) { + lo = (lo & 0x0000ffff) | SB_PARE_ERR_FLAG; + _wrmsr(SB_MSR_REG(SB_ERROR), hi, lo); + } + } + break; + case PCI_BAR0_REG: + if (value == PCI_BAR_RANGE_MASK) { + _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo); + lo |= SOFT_BAR_EHCI_FLAG; + _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo); + } else if ((value & 0x01) == 0x00) { + _wrmsr(USB_MSR_REG(USB_EHCI), hi, lo); + + value &= 0xfffffff0; + hi = 0x40000000 | ((value & 0xff000000) >> 24); + lo = 0x000fffff | ((value & 0x00fff000) << 8); + _wrmsr(GLIU_MSR_REG(GLIU_P2D_BM4), hi, lo); + } + break; + case PCI_EHCI_LEGSMIEN_REG: + _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo); + hi &= 0x003f0000; + hi |= (value & 0x3f) << 16; + _wrmsr(USB_MSR_REG(USB_EHCI), hi, lo); + break; + case PCI_EHCI_FLADJ_REG: + _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo); + hi &= ~0x00003f00; + hi |= value & 0x00003f00; + _wrmsr(USB_MSR_REG(USB_EHCI), hi, lo); + break; + default: + break; + } + + return; +} + +u32 pci_ehci_read_reg(int reg) +{ + u32 conf_data = 0; + u32 hi, lo; + + switch (reg) { + case PCI_VENDOR_ID: + conf_data = + CFG_PCI_VENDOR_ID(CS5536_EHCI_DEVICE_ID, CS5536_VENDOR_ID); + break; + case PCI_COMMAND: + _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo); + if (hi & PCI_COMMAND_MASTER) + conf_data |= PCI_COMMAND_MASTER; + if (hi & PCI_COMMAND_MEMORY) + conf_data |= PCI_COMMAND_MEMORY; + break; + case PCI_STATUS: + conf_data |= PCI_STATUS_66MHZ; + conf_data |= PCI_STATUS_FAST_BACK; + _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo); + if (lo & SB_PARE_ERR_FLAG) + conf_data |= PCI_STATUS_PARITY; + conf_data |= PCI_STATUS_DEVSEL_MEDIUM; + break; + case PCI_CLASS_REVISION: + _rdmsr(USB_MSR_REG(USB_CAP), &hi, &lo); + conf_data = lo & 0x000000ff; + conf_data |= (CS5536_EHCI_CLASS_CODE << 8); + break; + case PCI_CACHE_LINE_SIZE: + conf_data = + CFG_PCI_CACHE_LINE_SIZE(PCI_NORMAL_HEADER_TYPE, + PCI_NORMAL_LATENCY_TIMER); + break; + case PCI_BAR0_REG: + _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo); + if (lo & SOFT_BAR_EHCI_FLAG) { + conf_data = CS5536_EHCI_RANGE | + PCI_BASE_ADDRESS_SPACE_MEMORY; + lo &= ~SOFT_BAR_EHCI_FLAG; + _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo); + } else { + _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo); + conf_data = lo & 0xfffff000; + } + break; + case PCI_CARDBUS_CIS: + conf_data = PCI_CARDBUS_CIS_POINTER; + break; + case PCI_SUBSYSTEM_VENDOR_ID: + conf_data = + CFG_PCI_VENDOR_ID(CS5536_EHCI_SUB_ID, CS5536_SUB_VENDOR_ID); + break; + case PCI_ROM_ADDRESS: + conf_data = PCI_EXPANSION_ROM_BAR; + break; + case PCI_CAPABILITY_LIST: + conf_data = PCI_CAPLIST_USB_POINTER; + break; + case PCI_INTERRUPT_LINE: + conf_data = + CFG_PCI_INTERRUPT_LINE(PCI_DEFAULT_PIN, CS5536_USB_INTR); + break; + case PCI_EHCI_LEGSMIEN_REG: + _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo); + conf_data = (hi & 0x003f0000) >> 16; + break; + case PCI_EHCI_LEGSMISTS_REG: + _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo); + conf_data = (hi & 0x3f000000) >> 24; + break; + case PCI_EHCI_FLADJ_REG: + _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo); + conf_data = hi & 0x00003f00; + break; + default: + break; + } + + return conf_data; +} diff --git a/arch/mips/loongson/common/cs5536/cs5536_ide.c b/arch/mips/loongson/common/cs5536/cs5536_ide.c new file mode 100644 index 0000000..afde81c --- /dev/null +++ b/arch/mips/loongson/common/cs5536/cs5536_ide.c @@ -0,0 +1,187 @@ +/* + * the IDE Virtual Support Module of AMD CS5536 + * + * Copyright (C) 2007 Lemote, Inc. + * Author : jlliu, liujl@lemote.com + * + * Copyright (C) 2009 Lemote, Inc. + * Author: Wu Zhangjin, wuzj@lemote.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include +#include + +/* + * ide_write : ide write transfering + */ +void pci_ide_write_reg(int reg, u32 value) +{ + u32 hi = 0, lo = value; + + switch (reg) { + case PCI_COMMAND: + _rdmsr(GLIU_MSR_REG(GLIU_PAE), &hi, &lo); + if (value & PCI_COMMAND_MASTER) + lo |= (0x03 << 4); + else + lo &= ~(0x03 << 4); + _wrmsr(GLIU_MSR_REG(GLIU_PAE), hi, lo); + break; + case PCI_STATUS: + if (value & PCI_STATUS_PARITY) { + _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo); + if (lo & SB_PARE_ERR_FLAG) { + lo = (lo & 0x0000ffff) | SB_PARE_ERR_FLAG; + _wrmsr(SB_MSR_REG(SB_ERROR), hi, lo); + } + } + break; + case PCI_CACHE_LINE_SIZE: + value &= 0x0000ff00; + _rdmsr(SB_MSR_REG(SB_CTRL), &hi, &lo); + hi &= 0xffffff00; + hi |= (value >> 8); + _wrmsr(SB_MSR_REG(SB_CTRL), hi, lo); + break; + case PCI_BAR4_REG: + if (value == PCI_BAR_RANGE_MASK) { + _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo); + lo |= SOFT_BAR_IDE_FLAG; + _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo); + } else if (value & 0x01) { + lo = (value & 0xfffffff0) | 0x1; + _wrmsr(IDE_MSR_REG(IDE_IO_BAR), hi, lo); + + value &= 0xfffffffc; + hi = 0x60000000 | ((value & 0x000ff000) >> 12); + lo = 0x000ffff0 | ((value & 0x00000fff) << 20); + _wrmsr(GLIU_MSR_REG(GLIU_IOD_BM2), hi, lo); + } + break; + case PCI_IDE_CFG_REG: + if (value == CS5536_IDE_FLASH_SIGNATURE) { + _rdmsr(DIVIL_MSR_REG(DIVIL_BALL_OPTS), &hi, &lo); + lo |= 0x01; + _wrmsr(DIVIL_MSR_REG(DIVIL_BALL_OPTS), hi, lo); + } else + _wrmsr(IDE_MSR_REG(IDE_CFG), hi, lo); + break; + case PCI_IDE_DTC_REG: + _wrmsr(IDE_MSR_REG(IDE_DTC), hi, lo); + break; + case PCI_IDE_CAST_REG: + _wrmsr(IDE_MSR_REG(IDE_CAST), hi, lo); + break; + case PCI_IDE_ETC_REG: + _wrmsr(IDE_MSR_REG(IDE_ETC), hi, lo); + break; + case PCI_IDE_PM_REG: + _wrmsr(IDE_MSR_REG(IDE_INTERNAL_PM), hi, lo); + break; + default: + break; + } + + return; +} + +/* + * ide_read : ide read tranfering. + */ +u32 pci_ide_read_reg(int reg) +{ + u32 conf_data = 0; + u32 hi, lo; + + switch (reg) { + case PCI_VENDOR_ID: + conf_data = + CFG_PCI_VENDOR_ID(CS5536_IDE_DEVICE_ID, CS5536_VENDOR_ID); + break; + case PCI_COMMAND: + _rdmsr(IDE_MSR_REG(IDE_IO_BAR), &hi, &lo); + if (lo & 0xfffffff0) + conf_data |= PCI_COMMAND_IO; + _rdmsr(GLIU_MSR_REG(GLIU_PAE), &hi, &lo); + if ((lo & 0x30) == 0x30) + conf_data |= PCI_COMMAND_MASTER; + break; + case PCI_STATUS: + conf_data |= PCI_STATUS_66MHZ; + conf_data |= PCI_STATUS_FAST_BACK; + _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo); + if (lo & SB_PARE_ERR_FLAG) + conf_data |= PCI_STATUS_PARITY; + conf_data |= PCI_STATUS_DEVSEL_MEDIUM; + break; + case PCI_CLASS_REVISION: + _rdmsr(IDE_MSR_REG(IDE_CAP), &hi, &lo); + conf_data = lo & 0x000000ff; + conf_data |= (CS5536_IDE_CLASS_CODE << 8); + break; + case PCI_CACHE_LINE_SIZE: + _rdmsr(SB_MSR_REG(SB_CTRL), &hi, &lo); + hi &= 0x000000f8; + conf_data = CFG_PCI_CACHE_LINE_SIZE(PCI_NORMAL_HEADER_TYPE, hi); + break; + case PCI_BAR4_REG: + _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo); + if (lo & SOFT_BAR_IDE_FLAG) { + conf_data = CS5536_IDE_RANGE | + PCI_BASE_ADDRESS_SPACE_IO; + lo &= ~SOFT_BAR_IDE_FLAG; + _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo); + } else { + _rdmsr(IDE_MSR_REG(IDE_IO_BAR), &hi, &lo); + conf_data = lo & 0xfffffff0; + conf_data |= 0x01; + conf_data &= ~0x02; + } + break; + case PCI_CARDBUS_CIS: + conf_data = PCI_CARDBUS_CIS_POINTER; + break; + case PCI_SUBSYSTEM_VENDOR_ID: + conf_data = + CFG_PCI_VENDOR_ID(CS5536_IDE_SUB_ID, CS5536_SUB_VENDOR_ID); + break; + case PCI_ROM_ADDRESS: + conf_data = PCI_EXPANSION_ROM_BAR; + break; + case PCI_CAPABILITY_LIST: + conf_data = PCI_CAPLIST_POINTER; + break; + case PCI_INTERRUPT_LINE: + conf_data = + CFG_PCI_INTERRUPT_LINE(PCI_DEFAULT_PIN, CS5536_IDE_INTR); + break; + case PCI_IDE_CFG_REG: + _rdmsr(IDE_MSR_REG(IDE_CFG), &hi, &lo); + conf_data = lo; + break; + case PCI_IDE_DTC_REG: + _rdmsr(IDE_MSR_REG(IDE_DTC), &hi, &lo); + conf_data = lo; + break; + case PCI_IDE_CAST_REG: + _rdmsr(IDE_MSR_REG(IDE_CAST), &hi, &lo); + conf_data = lo; + break; + case PCI_IDE_ETC_REG: + _rdmsr(IDE_MSR_REG(IDE_ETC), &hi, &lo); + conf_data = lo; + case PCI_IDE_PM_REG: + _rdmsr(IDE_MSR_REG(IDE_INTERNAL_PM), &hi, &lo); + conf_data = lo; + break; + default: + break; + } + + return conf_data; +} diff --git a/arch/mips/loongson/common/cs5536/cs5536_isa.c b/arch/mips/loongson/common/cs5536/cs5536_isa.c new file mode 100644 index 0000000..c7e5f9e --- /dev/null +++ b/arch/mips/loongson/common/cs5536/cs5536_isa.c @@ -0,0 +1,322 @@ +/* + * the ISA Virtual Support Module of AMD CS5536 + * + * Copyright (C) 2007 Lemote, Inc. + * Author : jlliu, liujl@lemote.com + * + * Copyright (C) 2009 Lemote, Inc. + * Author: Wu Zhangjin, wuzj@lemote.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include +#include + +/* common variables for PCI_ISA_READ/WRITE_BAR */ +static const u32 divil_msr_reg[6] = { + DIVIL_MSR_REG(DIVIL_LBAR_SMB), DIVIL_MSR_REG(DIVIL_LBAR_GPIO), + DIVIL_MSR_REG(DIVIL_LBAR_MFGPT), DIVIL_MSR_REG(DIVIL_LBAR_IRQ), + DIVIL_MSR_REG(DIVIL_LBAR_PMS), DIVIL_MSR_REG(DIVIL_LBAR_ACPI), +}; + +static const u32 soft_bar_flag[6] = { + SOFT_BAR_SMB_FLAG, SOFT_BAR_GPIO_FLAG, SOFT_BAR_MFGPT_FLAG, + SOFT_BAR_IRQ_FLAG, SOFT_BAR_PMS_FLAG, SOFT_BAR_ACPI_FLAG, +}; + +static const u32 sb_msr_reg[6] = { + SB_MSR_REG(SB_R0), SB_MSR_REG(SB_R1), SB_MSR_REG(SB_R2), + SB_MSR_REG(SB_R3), SB_MSR_REG(SB_R4), SB_MSR_REG(SB_R5), +}; + +static const u32 bar_space_range[6] = { + CS5536_SMB_RANGE, CS5536_GPIO_RANGE, CS5536_MFGPT_RANGE, + CS5536_IRQ_RANGE, CS5536_PMS_RANGE, CS5536_ACPI_RANGE, +}; + +static const int bar_space_len[6] = { + CS5536_SMB_LENGTH, CS5536_GPIO_LENGTH, CS5536_MFGPT_LENGTH, + CS5536_IRQ_LENGTH, CS5536_PMS_LENGTH, CS5536_ACPI_LENGTH, +}; + +/* + * enable the divil module bar space. + * + * For all the DIVIL module LBAR, you should control the DIVIL LBAR reg + * and the RCONFx(0~5) reg to use the modules. + */ +static void divil_lbar_enable(void) +{ + u32 hi, lo; + int offset; + + /* + * The DIVIL IRQ is not used yet. and make the RCONF0 reserved. + */ + + for (offset = DIVIL_LBAR_SMB; offset <= DIVIL_LBAR_PMS; offset++) { + _rdmsr(DIVIL_MSR_REG(offset), &hi, &lo); + hi |= 0x01; + _wrmsr(DIVIL_MSR_REG(DIVIL_LBAR_SMB), hi, lo); + } + return; +} + +/* + * disable the divil module bar space. + */ +static void divil_lbar_disable(void) +{ + u32 hi, lo; + int offset; + + for (offset = DIVIL_LBAR_SMB; offset <= DIVIL_LBAR_PMS; offset++) { + _rdmsr(DIVIL_MSR_REG(offset), &hi, &lo); + hi &= ~0x01; + _wrmsr(DIVIL_MSR_REG(DIVIL_LBAR_SMB), hi, lo); + } + return; +} + +/* + * BAR write: write value to the n BAR + */ + +void pci_isa_write_bar(int n, u32 value) +{ + u32 hi = 0, lo = value; + + if (value == PCI_BAR_RANGE_MASK) { + _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo); + lo |= soft_bar_flag[n]; + _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo); + } else if (value & 0x01) { + /* NATIVE reg */ + hi = 0x0000f001; + lo &= bar_space_range[n]; + _wrmsr(divil_msr_reg[n], hi, lo); + + /* RCONFx is 4bytes in units for I/O space */ + hi = ((value & 0x000ffffc) << 12) | + ((bar_space_len[n] - 4) << 12) | 0x01; + lo = ((value & 0x000ffffc) << 12) | 0x01; + _wrmsr(sb_msr_reg[n], hi, lo); + } + + return; +} + +/* + * BAR read: read the n BAR + */ + +u32 pci_isa_read_bar(int n) +{ + u32 conf_data = 0; + u32 hi, lo; + + _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo); + if (lo & soft_bar_flag[n]) { + conf_data = bar_space_range[n] | PCI_BASE_ADDRESS_SPACE_IO; + lo &= ~soft_bar_flag[n]; + _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo); + } else { + _rdmsr(divil_msr_reg[n], &hi, &lo); + conf_data = lo & bar_space_range[n]; + conf_data |= 0x01; + conf_data &= ~0x02; + } + return conf_data; +} + +/* + * isa_write : isa write transfering. + * we assume that the ISA is not the BUS MASTER! + */ + +void pci_isa_write_reg(int reg, u32 value) +{ + u32 hi = 0, lo = value; + u32 temp; + + switch (reg) { + case PCI_COMMAND: + if (value & PCI_COMMAND_IO) + divil_lbar_enable(); + else + divil_lbar_disable(); + break; + case PCI_STATUS: + _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo); + temp = lo & 0x0000ffff; + if ((value & PCI_STATUS_SIG_TARGET_ABORT) && + (lo & SB_TAS_ERR_EN)) + temp |= SB_TAS_ERR_FLAG; + + if ((value & PCI_STATUS_REC_TARGET_ABORT) && + (lo & SB_TAR_ERR_EN)) + temp |= SB_TAR_ERR_FLAG; + + if ((value & PCI_STATUS_REC_MASTER_ABORT) + && (lo & SB_MAR_ERR_EN)) + temp |= SB_MAR_ERR_FLAG; + + if ((value & PCI_STATUS_DETECTED_PARITY) + && (lo & SB_PARE_ERR_EN)) + temp |= SB_PARE_ERR_FLAG; + + lo = temp; + _wrmsr(SB_MSR_REG(SB_ERROR), hi, lo); + break; + case PCI_CACHE_LINE_SIZE: + value &= 0x0000ff00; + _rdmsr(SB_MSR_REG(SB_CTRL), &hi, &lo); + hi &= 0xffffff00; + hi |= (value >> 8); + _wrmsr(SB_MSR_REG(SB_CTRL), hi, lo); + break; + case PCI_BAR0_REG: + pci_isa_write_bar(0, value); + break; + case PCI_BAR1_REG: + pci_isa_write_bar(1, value); + break; + case PCI_BAR2_REG: + pci_isa_write_bar(2, value); + break; + case PCI_BAR3_REG: + pci_isa_write_bar(3, value); + break; + case PCI_BAR4_REG: + pci_isa_write_bar(4, value); + break; + case PCI_BAR5_REG: + pci_isa_write_bar(5, value); + break; + case PCI_UART1_INT_REG: + _rdmsr(DIVIL_MSR_REG(PIC_YSEL_HIGH), &hi, &lo); + /* disable uart1 interrupt in PIC */ + lo &= ~(0xf << 24); + if (value) /* enable uart1 interrupt in PIC */ + lo |= (CS5536_UART1_INTR << 24); + _wrmsr(DIVIL_MSR_REG(PIC_YSEL_HIGH), hi, lo); + break; + case PCI_UART2_INT_REG: + _rdmsr(DIVIL_MSR_REG(PIC_YSEL_HIGH), &hi, &lo); + /* disable uart2 interrupt in PIC */ + lo &= ~(0xf << 28); + if (value) /* enable uart2 interrupt in PIC */ + lo |= (CS5536_UART2_INTR << 28); + _wrmsr(DIVIL_MSR_REG(PIC_YSEL_HIGH), hi, lo); + break; + case PCI_ISA_FIXUP_REG: + if (value) { + /* enable the TARGET ABORT/MASTER ABORT etc. */ + _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo); + lo |= 0x00000063; + _wrmsr(SB_MSR_REG(SB_ERROR), hi, lo); + } + + default: + /* ALL OTHER PCI CONFIG SPACE HEADER IS NOT IMPLEMENTED. */ + break; + } + + return; +} + +/* + * isa_read : isa read transfering. + * we assume that the ISA is not the BUS MASTER. + */ + +u32 pci_isa_read_reg(int reg) +{ + u32 conf_data = 0; + u32 hi, lo; + + switch (reg) { + case PCI_VENDOR_ID: + conf_data = + CFG_PCI_VENDOR_ID(CS5536_ISA_DEVICE_ID, CS5536_VENDOR_ID); + break; + case PCI_COMMAND: + /* we just check the first LBAR for the IO enable bit, */ + /* maybe we should changed later. */ + _rdmsr(DIVIL_MSR_REG(DIVIL_LBAR_SMB), &hi, &lo); + if (hi & 0x01) + conf_data |= PCI_COMMAND_IO; + break; + case PCI_STATUS: + conf_data |= PCI_STATUS_66MHZ; + conf_data |= PCI_STATUS_DEVSEL_MEDIUM; + conf_data |= PCI_STATUS_FAST_BACK; + + _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo); + if (lo & SB_TAS_ERR_FLAG) + conf_data |= PCI_STATUS_SIG_TARGET_ABORT; + if (lo & SB_TAR_ERR_FLAG) + conf_data |= PCI_STATUS_REC_TARGET_ABORT; + if (lo & SB_MAR_ERR_FLAG) + conf_data |= PCI_STATUS_REC_MASTER_ABORT; + if (lo & SB_PARE_ERR_FLAG) + conf_data |= PCI_STATUS_DETECTED_PARITY; + break; + case PCI_CLASS_REVISION: + _rdmsr(GLCP_MSR_REG(GLCP_CHIP_REV_ID), &hi, &lo); + conf_data = lo & 0x000000ff; + conf_data |= (CS5536_ISA_CLASS_CODE << 8); + break; + case PCI_CACHE_LINE_SIZE: + _rdmsr(SB_MSR_REG(SB_CTRL), &hi, &lo); + hi &= 0x000000f8; + conf_data = CFG_PCI_CACHE_LINE_SIZE(PCI_BRIDGE_HEADER_TYPE, hi); + break; + /* + * we only use the LBAR of DIVIL, no RCONF used. + * all of them are IO space. + */ + case PCI_BAR0_REG: + return pci_isa_read_bar(0); + break; + case PCI_BAR1_REG: + return pci_isa_read_bar(1); + break; + case PCI_BAR2_REG: + return pci_isa_read_bar(2); + break; + case PCI_BAR3_REG: + break; + case PCI_BAR4_REG: + return pci_isa_read_bar(4); + break; + case PCI_BAR5_REG: + return pci_isa_read_bar(5); + break; + case PCI_CARDBUS_CIS: + conf_data = PCI_CARDBUS_CIS_POINTER; + break; + case PCI_SUBSYSTEM_VENDOR_ID: + conf_data = + CFG_PCI_VENDOR_ID(CS5536_ISA_SUB_ID, CS5536_SUB_VENDOR_ID); + break; + case PCI_ROM_ADDRESS: + conf_data = PCI_EXPANSION_ROM_BAR; + break; + case PCI_CAPABILITY_LIST: + conf_data = PCI_CAPLIST_POINTER; + break; + case PCI_INTERRUPT_LINE: + /* no interrupt used here */ + conf_data = CFG_PCI_INTERRUPT_LINE(0x00, 0x00); + break; + default: + break; + } + + return conf_data; +} diff --git a/arch/mips/loongson/common/cs5536/cs5536_ohci.c b/arch/mips/loongson/common/cs5536/cs5536_ohci.c new file mode 100644 index 0000000..6d824fc --- /dev/null +++ b/arch/mips/loongson/common/cs5536/cs5536_ohci.c @@ -0,0 +1,155 @@ +/* + * the OHCI Virtual Support Module of AMD CS5536 + * + * Copyright (C) 2007 Lemote, Inc. + * Author : jlliu, liujl@lemote.com + * + * Copyright (C) 2009 Lemote, Inc. + * Author: Wu Zhangjin, wuzj@lemote.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include +#include + +/* + * ohci_write : ohci write transfering. + */ +void pci_ohci_write_reg(int reg, u32 value) +{ + u32 hi = 0, lo = value; + + switch (reg) { + case PCI_COMMAND: + _rdmsr(USB_MSR_REG(USB_OHCI), &hi, &lo); + if (value & PCI_COMMAND_MASTER) + hi |= PCI_COMMAND_MASTER; + else + hi &= ~PCI_COMMAND_MASTER; + + if (value & PCI_COMMAND_MEMORY) + hi |= PCI_COMMAND_MEMORY; + else + hi &= ~PCI_COMMAND_MEMORY; + _wrmsr(USB_MSR_REG(USB_OHCI), hi, lo); + break; + case PCI_STATUS: + if (value & PCI_STATUS_PARITY) { + _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo); + if (lo & SB_PARE_ERR_FLAG) { + lo = (lo & 0x0000ffff) | SB_PARE_ERR_FLAG; + _wrmsr(SB_MSR_REG(SB_ERROR), hi, lo); + } + } + break; + case PCI_BAR0_REG: + if (value == PCI_BAR_RANGE_MASK) { + _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo); + lo |= SOFT_BAR_OHCI_FLAG; + _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo); + } else if ((value & 0x01) == 0x00) { + _wrmsr(USB_MSR_REG(USB_OHCI), hi, lo); + + value &= 0xfffffff0; + hi = 0x40000000 | ((value & 0xff000000) >> 24); + lo = 0x000fffff | ((value & 0x00fff000) << 8); + _wrmsr(GLIU_MSR_REG(GLIU_P2D_BM3), hi, lo); + } + break; + case PCI_OHCI_INT_REG: + _rdmsr(DIVIL_MSR_REG(PIC_YSEL_LOW), &hi, &lo); + lo &= ~(0xf << PIC_YSEL_LOW_USB_SHIFT); + if (value) /* enable all the usb interrupt in PIC */ + lo |= (CS5536_USB_INTR << PIC_YSEL_LOW_USB_SHIFT); + _wrmsr(DIVIL_MSR_REG(PIC_YSEL_LOW), hi, lo); + break; + default: + break; + } + + return; +} + +/* + * ohci_read : ohci read transfering. + */ +u32 pci_ohci_read_reg(int reg) +{ + u32 conf_data = 0; + u32 hi, lo; + + switch (reg) { + case PCI_VENDOR_ID: + conf_data = + CFG_PCI_VENDOR_ID(CS5536_OHCI_DEVICE_ID, CS5536_VENDOR_ID); + break; + case PCI_COMMAND: + _rdmsr(USB_MSR_REG(USB_OHCI), &hi, &lo); + if (hi & PCI_COMMAND_MASTER) + conf_data |= PCI_COMMAND_MASTER; + if (hi & PCI_COMMAND_MEMORY) + conf_data |= PCI_COMMAND_MEMORY; + break; + case PCI_STATUS: + conf_data |= PCI_STATUS_66MHZ; + conf_data |= PCI_STATUS_FAST_BACK; + _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo); + if (lo & SB_PARE_ERR_FLAG) + conf_data |= PCI_STATUS_PARITY; + conf_data |= PCI_STATUS_DEVSEL_MEDIUM; + break; + case PCI_CLASS_REVISION: + _rdmsr(USB_MSR_REG(USB_CAP), &hi, &lo); + conf_data = lo & 0x000000ff; + conf_data |= (CS5536_OHCI_CLASS_CODE << 8); + break; + case PCI_CACHE_LINE_SIZE: + conf_data = + CFG_PCI_CACHE_LINE_SIZE(PCI_NORMAL_HEADER_TYPE, + PCI_NORMAL_LATENCY_TIMER); + break; + case PCI_BAR0_REG: + _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo); + if (lo & SOFT_BAR_OHCI_FLAG) { + conf_data = CS5536_OHCI_RANGE | + PCI_BASE_ADDRESS_SPACE_MEMORY; + lo &= ~SOFT_BAR_OHCI_FLAG; + _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo); + } else { + _rdmsr(USB_MSR_REG(USB_OHCI), &hi, &lo); + conf_data = lo & 0xffffff00; + conf_data &= ~0x0000000f; /* 32bit mem */ + } + break; + case PCI_CARDBUS_CIS: + conf_data = PCI_CARDBUS_CIS_POINTER; + break; + case PCI_SUBSYSTEM_VENDOR_ID: + conf_data = + CFG_PCI_VENDOR_ID(CS5536_OHCI_SUB_ID, CS5536_SUB_VENDOR_ID); + break; + case PCI_ROM_ADDRESS: + conf_data = PCI_EXPANSION_ROM_BAR; + break; + case PCI_CAPABILITY_LIST: + conf_data = PCI_CAPLIST_USB_POINTER; + break; + case PCI_INTERRUPT_LINE: + conf_data = + CFG_PCI_INTERRUPT_LINE(PCI_DEFAULT_PIN, CS5536_USB_INTR); + break; + case PCI_OHCI_INT_REG: + _rdmsr(DIVIL_MSR_REG(PIC_YSEL_LOW), &hi, &lo); + if ((lo & 0x00000f00) == CS5536_USB_INTR) + conf_data = 1; + break; + default: + break; + } + + return conf_data; +} diff --git a/arch/mips/loongson/common/cs5536/cs5536_pci.c b/arch/mips/loongson/common/cs5536/cs5536_pci.c new file mode 100644 index 0000000..a7a3d25 --- /dev/null +++ b/arch/mips/loongson/common/cs5536/cs5536_pci.c @@ -0,0 +1,89 @@ +/* + * read/write operation to the PCI config space of CS5536 + * + * Copyright (C) 2007 Lemote, Inc. + * Author : jlliu, liujl@lemote.com + * + * Copyright (C) 2009 Lemote, Inc. + * Author: Wu Zhangjin, wuzj@lemote.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * the Virtual Support Module(VSM) for virtulizing the PCI + * configure space are defined in cs5536_modulename.c respectively, + * + * after this virtulizing, user can access the PCI configure space + * directly as a normal multi-function PCI device which follows + * the PCI-2.2 spec. + */ + +#include +#include + +enum { + CS5536_FUNC_START = -1, + CS5536_ISA_FUNC, + reserved_func, + CS5536_IDE_FUNC, + CS5536_ACC_FUNC, + CS5536_OHCI_FUNC, + CS5536_EHCI_FUNC, + CS5536_FUNC_END, +}; + +static const cs5536_pci_vsm_write vsm_conf_write[] = { + [CS5536_ISA_FUNC] pci_isa_write_reg, + [reserved_func] NULL, + [CS5536_IDE_FUNC] pci_ide_write_reg, + [CS5536_ACC_FUNC] pci_acc_write_reg, + [CS5536_OHCI_FUNC] pci_ohci_write_reg, + [CS5536_EHCI_FUNC] pci_ehci_write_reg, +}; + +static const cs5536_pci_vsm_read vsm_conf_read[] = { + [CS5536_ISA_FUNC] pci_isa_read_reg, + [reserved_func] NULL, + [CS5536_IDE_FUNC] pci_ide_read_reg, + [CS5536_ACC_FUNC] pci_acc_read_reg, + [CS5536_OHCI_FUNC] pci_ohci_read_reg, + [CS5536_EHCI_FUNC] pci_ehci_read_reg, +}; + +/* + * write to PCI config space and transfer it to MSR write. + */ +void cs5536_pci_conf_write4(int function, int reg, u32 value) +{ + if ((function <= CS5536_FUNC_START) || (function >= CS5536_FUNC_END)) + return; + if ((reg < 0) || (reg > 0x100) || ((reg & 0x03) != 0)) + return; + + if (vsm_conf_write[function] != NULL) + vsm_conf_write[function](reg, value); + + return; +} + +/* + * read PCI config space and transfer it to MSR access. + */ +u32 cs5536_pci_conf_read4(int function, int reg) +{ + u32 data = 0; + + if ((function <= CS5536_FUNC_START) || (function >= CS5536_FUNC_END)) + return 0; + if ((reg < 0) || ((reg & 0x03) != 0)) + return 0; + if (reg > 0x100) + return 0xffffffff; + + if (vsm_conf_read[function] != NULL) + data = vsm_conf_read[function](reg); + + return data; +} -- 1.6.2.1 From wuzhangjin@gmail.com Wed Nov 4 10:06:27 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 04 Nov 2009 10:06:34 +0100 (CET) Received: from mail-pw0-f45.google.com ([209.85.160.45]:59763 "EHLO mail-pw0-f45.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492008AbZKDJGC (ORCPT ); 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Wed, 04 Nov 2009 01:06:01 -0800 (PST) From: Wu Zhangjin To: Ralf Baechle Cc: Wu Zhangjin , linux-mips@linux-mips.org, LKML , huhb@lemote.com, yanh@lemote.com, Zhang Le , Thomas Gleixner , Nicholas Mc Guire , zhangfx@lemote.com, liujl@lemote.com Subject: [PATCH -queue v0 4/6] [loongson] add basic fuloong2f support Date: Wed, 4 Nov 2009 17:05:47 +0800 Message-Id: <0f805f7d12c5a7cbcc125ba4a1b70113ec2047a6.1257325319.git.wuzhangjin@gmail.com> X-Mailer: git-send-email 1.6.2.1 In-Reply-To: References: Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24662 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips fuloong(2f) has an AMD CS5536 south bridge. we need to add support for it. there are several modules provided by cs5536, currently, only these modules are used in fuloong(2f) mini PC: ide, acc(audio), ohci, isa, and ehci. since the PCI operations are similiar between fuloong(2e) and fuloong(2f),yeeloong(2f) and even similiar to gdium, herein, I just rename ops-fuloong2e.c to ops-loongsgon2.c to share most of the source code. and also, the serial port support is enabled via adding a macro in machine.h. Signed-off-by: Wu Zhangjin --- arch/mips/Makefile | 1 + arch/mips/include/asm/mach-loongson/machine.h | 8 +- arch/mips/loongson/Kconfig | 30 ++++ arch/mips/loongson/Makefile | 6 + arch/mips/loongson/fuloong-2f/Makefile | 5 + arch/mips/loongson/fuloong-2f/irq.c | 114 ++++++++++++++ arch/mips/loongson/fuloong-2f/reset.c | 68 ++++++++ arch/mips/pci/Makefile | 3 +- arch/mips/pci/fixup-fuloong2f.c | 171 ++++++++++++++++++++ arch/mips/pci/ops-fuloong2e.c | 154 ------------------ arch/mips/pci/ops-loongson2.c | 207 +++++++++++++++++++++++++ 11 files changed, 611 insertions(+), 156 deletions(-) create mode 100644 arch/mips/loongson/fuloong-2f/Makefile create mode 100644 arch/mips/loongson/fuloong-2f/irq.c create mode 100644 arch/mips/loongson/fuloong-2f/reset.c create mode 100644 arch/mips/pci/fixup-fuloong2f.c delete mode 100644 arch/mips/pci/ops-fuloong2e.c create mode 100644 arch/mips/pci/ops-loongson2.c diff --git a/arch/mips/Makefile b/arch/mips/Makefile index 47ecded..65d4734 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -327,6 +327,7 @@ core-$(CONFIG_MACH_LOONGSON) +=arch/mips/loongson/ cflags-$(CONFIG_MACH_LOONGSON) += -I$(srctree)/arch/mips/include/asm/mach-loongson \ -mno-branch-likely load-$(CONFIG_LEMOTE_FULOONG2E) +=0xffffffff80100000 +load-$(CONFIG_LEMOTE_FULOONG2F) +=0xffffffff80200000 # # MIPS Malta board diff --git a/arch/mips/include/asm/mach-loongson/machine.h b/arch/mips/include/asm/mach-loongson/machine.h index ea5954c..2eb9be6 100644 --- a/arch/mips/include/asm/mach-loongson/machine.h +++ b/arch/mips/include/asm/mach-loongson/machine.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2009 Lemote, Inc. & Institute of Computing Technology + * Copyright (C) 2009 Lemote, Inc. * Author: Wu Zhangjin * * This program is free software; you can redistribute it and/or modify it @@ -17,6 +17,12 @@ #define LOONGSON_MACHTYPE MACH_LEMOTE_FL2E +#elif defined(CONFIG_LEMOTE_FULOONG2F) + +#define LOONGSON_UART_BASE (LOONGSON_PCIIO_BASE + 0x2f8) + +#define LOONGSON_MACHTYPE MACH_LEMOTE_FL2F + #endif #endif /* __ASM_MACH_LOONGSON_MACHINE_H */ diff --git a/arch/mips/loongson/Kconfig b/arch/mips/loongson/Kconfig index b03d773..8156d71 100644 --- a/arch/mips/loongson/Kconfig +++ b/arch/mips/loongson/Kconfig @@ -28,6 +28,36 @@ config LEMOTE_FULOONG2E an FPGA northbridge Lemote Fuloong(2e) mini PC have a VIA686B south bridge. + +config LEMOTE_FULOONG2F + bool "Lemote Fuloong(2f) mini-PC" + select ARCH_SPARSEMEM_ENABLE + select CEVT_R4K + select CSRC_R4K + select SYS_HAS_CPU_LOONGSON2F + select DMA_NONCOHERENT + select BOOT_ELF32 + select BOARD_SCACHE + select HW_HAS_PCI + select I8259 + select ISA + select IRQ_CPU + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_64BIT_KERNEL + select SYS_SUPPORTS_LITTLE_ENDIAN + select SYS_SUPPORTS_HIGHMEM + select SYS_HAS_EARLY_PRINTK + select GENERIC_HARDIRQS_NO__DO_IRQ + select GENERIC_ISA_DMA_SUPPORT_BROKEN + select CPU_HAS_WB + select CS5536 + help + Lemote Fuloong(2f) mini-PC board based on the Chinese Loongson-2F + CPU, which has an internal DDR and PCIX controller. the PCIX + controller have the similiar programming interface of the FPGA north + bridge of LOONGSON2E. + + Lemote Fuloong(2f) mini PC have an AMD CS5536 south bridge. endchoice config CS5536 diff --git a/arch/mips/loongson/Makefile b/arch/mips/loongson/Makefile index 39048c4..635062b 100644 --- a/arch/mips/loongson/Makefile +++ b/arch/mips/loongson/Makefile @@ -9,3 +9,9 @@ obj-$(CONFIG_MACH_LOONGSON) += common/ # obj-$(CONFIG_LEMOTE_FULOONG2E) += fuloong-2e/ + +# +# Lemote Fuloong mini-PC (Loongson 2F-based) +# + +obj-$(CONFIG_LEMOTE_FULOONG2F) += fuloong-2f/ diff --git a/arch/mips/loongson/fuloong-2f/Makefile b/arch/mips/loongson/fuloong-2f/Makefile new file mode 100644 index 0000000..010b86c --- /dev/null +++ b/arch/mips/loongson/fuloong-2f/Makefile @@ -0,0 +1,5 @@ +# +# Makefile for fuloong-2f +# + +obj-y += irq.o reset.o diff --git a/arch/mips/loongson/fuloong-2f/irq.c b/arch/mips/loongson/fuloong-2f/irq.c new file mode 100644 index 0000000..22c45fd --- /dev/null +++ b/arch/mips/loongson/fuloong-2f/irq.c @@ -0,0 +1,114 @@ +/* + * Copyright (C) 2007 Lemote Inc. + * Author: Fuxin Zhang, zhangfx@lemote.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include + +#include +#include +#include + +#include +#include + +#define LOONGSON_TIMER_IRQ (MIPS_CPU_IRQ_BASE + 7) /* cpu timer */ +#define LOONGSON_PERFCNT_IRQ (MIPS_CPU_IRQ_BASE + 6) /* cpu perf counter */ +#define LOONGSON_NORTH_BRIDGE_IRQ (MIPS_CPU_IRQ_BASE + 6) /* bonito */ +#define LOONGSON_UART_IRQ (MIPS_CPU_IRQ_BASE + 3) /* cpu serial port */ +#define LOONGSON_SOUTH_BRIDGE_IRQ (MIPS_CPU_IRQ_BASE + 2) /* i8259 */ + +#define LOONGSON_INT_BIT_INT0 (1 << 11) +#define LOONGSON_INT_BIT_INT1 (1 << 12) + +static int mach_i8259_irq(void) +{ + int irq, isr, imr; + + irq = -1; + + if ((LOONGSON_INTISR & LOONGSON_INTEN) & LOONGSON_INT_BIT_INT0) { + imr = inb(0x21) | (inb(0xa1) << 8); + isr = inb(0x20) | (inb(0xa0) << 8); + isr &= ~0x4; /* irq2 for cascade */ + isr &= ~imr; + irq = ffs(isr) - 1; + } + + return irq; +} + +static void i8259_irqdispatch(void) +{ + int irq; + + irq = mach_i8259_irq(); + if (irq >= 0) + do_IRQ(irq); + else + spurious_interrupt(); +} + +void mach_irq_dispatch(unsigned int pending) +{ + if (pending & CAUSEF_IP7) + do_IRQ(LOONGSON_TIMER_IRQ); + else if (pending & CAUSEF_IP6) { /* North Bridge, Perf counter */ +#ifdef CONFIG_OPROFILE + do_IRQ(LOONGSON2_PERFCNT_IRQ); +#endif + bonito_irqdispatch(); + } else if (pending & CAUSEF_IP3) /* CPU UART */ + do_IRQ(LOONGSON_UART_IRQ); + else if (pending & CAUSEF_IP2) /* South Bridge */ + i8259_irqdispatch(); + else + spurious_interrupt(); +} + +void __init set_irq_trigger_mode(void) +{ + /* setup cs5536 as high level trigger */ + LOONGSON_INTPOL = LOONGSON_INT_BIT_INT0 | LOONGSON_INT_BIT_INT1; + LOONGSON_INTEDGE &= ~(LOONGSON_INT_BIT_INT0 | LOONGSON_INT_BIT_INT1); +} + +static irqreturn_t ip6_action(int cpl, void *dev_id) +{ + return IRQ_HANDLED; +} + +struct irqaction ip6_irqaction = { + .handler = ip6_action, + .name = "cascade", + .flags = IRQF_SHARED, +}; + +struct irqaction cascade_irqaction = { + .handler = no_action, + .name = "cascade", +}; + +void __init mach_init_irq(void) +{ + /* init all controller + * 0-15 ------> i8259 interrupt + * 16-23 ------> mips cpu interrupt + * 32-63 ------> bonito irq + */ + + /* Sets the first-level interrupt dispatcher. */ + mips_cpu_irq_init(); + init_i8259_irqs(); + bonito_irq_init(); + + /* setup north bridge irq (bonito) */ + setup_irq(LOONGSON_NORTH_BRIDGE_IRQ, &ip6_irqaction); + /* setup source bridge irq (i8259) */ + setup_irq(LOONGSON_SOUTH_BRIDGE_IRQ, &cascade_irqaction); +} diff --git a/arch/mips/loongson/fuloong-2f/reset.c b/arch/mips/loongson/fuloong-2f/reset.c new file mode 100644 index 0000000..ac52f10 --- /dev/null +++ b/arch/mips/loongson/fuloong-2f/reset.c @@ -0,0 +1,68 @@ +/* Board-specific reboot/shutdown routines + * + * Copyright (c) 2009 Philippe Vachon + * + * Copyright (C) 2009 Lemote Inc. + * Author: Wu Zhangjin, wuzj@lemote.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include +#include +#include + +#include + +/* cs5536 is the south bridge used by fuloong2f mini PC */ +#include + +void mach_prepare_reboot(void) +{ + /* + * reset cpu to full speed, this is needed when enabling cpu frequency + * scalling + */ + LOONGSON_CHIPCFG0 |= 0x7; + + /* send a reset signal to south bridge. + * + * NOTE: if enable "Power Management" in kernel, rtl8169 will not reset + * normally with this reset operation and it will not work in PMON, but + * you can type halt command and then reboot, seems the hardware reset + * logic not work normally. + */ + { + u32 hi, lo; + _rdmsr(DIVIL_MSR_REG(DIVIL_SOFT_RESET), &hi, &lo); + lo |= 0x00000001; + _wrmsr(DIVIL_MSR_REG(DIVIL_SOFT_RESET), hi, lo); + } + /* the reset signal need about 8ms(?) to function */ + udelay(8000); +} + +void mach_prepare_shutdown(void) +{ + u32 hi, lo, val; + int gpio_base; + + /* get gpio base */ + _rdmsr(DIVIL_MSR_REG(DIVIL_LBAR_GPIO), &hi, &lo); + gpio_base = lo & 0xff00; + + /* make cs5536 gpio13 output enable */ + val = inl(gpio_base + GPIOL_OUT_EN); + val &= ~(1 << (16 + 13)); + val |= (1 << 13); + outl(val, gpio_base + GPIOL_OUT_EN); + mmiowb(); + /* make cs5536 gpio13 output low level voltage. */ + val = inl(gpio_base + GPIOL_OUT_VAL) & ~(1 << (13)); + val |= (1 << (16 + 13)); + outl(val, gpio_base + GPIOL_OUT_VAL); + mmiowb(); +} diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile index 0610c86..e7ad00b 100644 --- a/arch/mips/pci/Makefile +++ b/arch/mips/pci/Makefile @@ -28,7 +28,8 @@ obj-$(CONFIG_MIPS_COBALT) += fixup-cobalt.o obj-$(CONFIG_SOC_AU1500) += fixup-au1000.o ops-au1000.o obj-$(CONFIG_SOC_AU1550) += fixup-au1000.o ops-au1000.o obj-$(CONFIG_SOC_PNX8550) += fixup-pnx8550.o ops-pnx8550.o -obj-$(CONFIG_LEMOTE_FULOONG2E) += fixup-fuloong2e.o ops-fuloong2e.o +obj-$(CONFIG_LEMOTE_FULOONG2E) += fixup-fuloong2e.o ops-loongson2.o +obj-$(CONFIG_LEMOTE_FULOONG2F) += fixup-fuloong2f.o ops-loongson2.o obj-$(CONFIG_MIPS_MALTA) += fixup-malta.o obj-$(CONFIG_PMC_MSP7120_GW) += fixup-pmcmsp.o ops-pmcmsp.o obj-$(CONFIG_PMC_MSP7120_EVAL) += fixup-pmcmsp.o ops-pmcmsp.o diff --git a/arch/mips/pci/fixup-fuloong2f.c b/arch/mips/pci/fixup-fuloong2f.c new file mode 100644 index 0000000..994f668 --- /dev/null +++ b/arch/mips/pci/fixup-fuloong2f.c @@ -0,0 +1,171 @@ +/* + * Copyright (C) 2008 Lemote Technology + * Copyright (C) 2004 ICT CAS + * Author: Li xiaoyu, lixy@ict.ac.cn + * + * Copyright (C) 2007 Lemote, Inc. + * Author: Fuxin Zhang, zhangfx@lemote.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ +#include +#include + +#include +#include +#include + +/* PCI interrupt pins + * + * These should not be changed, or you should consider loongson2f interrupt + * register and your pci card dispatch + */ + +#define PCIA 4 +#define PCIB 5 +#define PCIC 6 +#define PCID 7 + +/* all the pci device has the PCIA pin, check the datasheet. */ +static char irq_tab[][5] __initdata = { + /* INTA INTB INTC INTD */ + {0, 0, 0, 0, 0}, /* 11: Unused */ + {0, 0, 0, 0, 0}, /* 12: Unused */ + {0, 0, 0, 0, 0}, /* 13: Unused */ + {0, 0, 0, 0, 0}, /* 14: Unused */ + {0, 0, 0, 0, 0}, /* 15: Unused */ + {0, 0, 0, 0, 0}, /* 16: Unused */ + {0, PCIA, 0, 0, 0}, /* 17: RTL8110-0 */ + {0, PCIB, 0, 0, 0}, /* 18: RTL8110-1 */ + {0, PCIC, 0, 0, 0}, /* 19: SiI3114 */ + {0, PCID, 0, 0, 0}, /* 20: 3-ports nec usb */ + {0, PCIA, PCIB, PCIC, PCID}, /* 21: PCI-SLOT */ + {0, 0, 0, 0, 0}, /* 22: Unused */ + {0, 0, 0, 0, 0}, /* 23: Unused */ + {0, 0, 0, 0, 0}, /* 24: Unused */ + {0, 0, 0, 0, 0}, /* 25: Unused */ + {0, 0, 0, 0, 0}, /* 26: Unused */ + {0, 0, 0, 0, 0}, /* 27: Unused */ +}; + +int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) +{ + int virq; + + if ((PCI_SLOT(dev->devfn) != PCI_IDSEL_CS5536) + && (PCI_SLOT(dev->devfn) < 32)) { + virq = irq_tab[slot][pin]; + printk(KERN_INFO "slot: %d, pin: %d, irq: %d\n", slot, pin, + virq + LOONGSON_IRQ_BASE); + if (virq != 0) + return LOONGSON_IRQ_BASE + virq; + else + return 0; + } else if (PCI_SLOT(dev->devfn) == PCI_IDSEL_CS5536) { /* cs5536 */ + switch (PCI_FUNC(dev->devfn)) { + case 2: + pci_write_config_byte(dev, PCI_INTERRUPT_LINE, + CS5536_IDE_INTR); + return CS5536_IDE_INTR; /* for IDE */ + case 3: + pci_write_config_byte(dev, PCI_INTERRUPT_LINE, + CS5536_ACC_INTR); + return CS5536_ACC_INTR; /* for AUDIO */ + case 4: /* for OHCI */ + case 5: /* for EHCI */ + case 6: /* for UDC */ + case 7: /* for OTG */ + pci_write_config_byte(dev, PCI_INTERRUPT_LINE, + CS5536_USB_INTR); + return CS5536_USB_INTR; + } + return dev->irq; + } else { + printk(KERN_INFO " strange pci slot number.\n"); + return 0; + } +} + +/* Do platform specific device initialization at pci_enable_device() time */ +int pcibios_plat_dev_init(struct pci_dev *dev) +{ + return 0; +} + +/* CS5536 SPEC. fixup */ +static void __init loongson_cs5536_isa_fixup(struct pci_dev *pdev) +{ + /* the uart1 and uart2 interrupt in PIC is enabled as default */ + pci_write_config_dword(pdev, PCI_UART1_INT_REG, 1); + pci_write_config_dword(pdev, PCI_UART2_INT_REG, 1); + return; +} + +static void __init loongson_cs5536_ide_fixup(struct pci_dev *pdev) +{ + /* setting the mutex pin as IDE function */ + pci_write_config_dword(pdev, PCI_IDE_CFG_REG, + CS5536_IDE_FLASH_SIGNATURE); + return; +} + +static void __init loongson_cs5536_acc_fixup(struct pci_dev *pdev) +{ + u8 val; + + /* enable the AUDIO interrupt in PIC */ + pci_write_config_dword(pdev, PCI_ACC_INT_REG, 1); + +#if 1 + pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &val); + printk(KERN_INFO "cs5536 acc latency 0x%x\n", val); + pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xc0); +#endif + return; +} + +static void __init loongson_cs5536_ohci_fixup(struct pci_dev *pdev) +{ + /* enable the OHCI interrupt in PIC */ + /* THE OHCI, EHCI, UDC, OTG are shared with interrupt in PIC */ + pci_write_config_dword(pdev, PCI_OHCI_INT_REG, 1); + return; +} + +static void __init loongson_cs5536_ehci_fixup(struct pci_dev *pdev) +{ + u32 hi, lo; + + /* Serial short detect enable */ + _rdmsr(USB_MSR_REG(USB_CONFIG), &hi, &lo); + _wrmsr(USB_MSR_REG(USB_CONFIG), (1 << 1) | (1 << 2) | (1 << 3), lo); + + /* setting the USB2.0 micro frame length */ + pci_write_config_dword(pdev, PCI_EHCI_FLADJ_REG, 0x2000); + return; +} + +static void __init loongson_nec_fixup(struct pci_dev *pdev) +{ + unsigned int val; + + pci_read_config_dword(pdev, 0xe0, &val); + /* Only 2 port be used */ + pci_write_config_dword(pdev, 0xe0, (val & ~3) | 0x2); +} + +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, + loongson_cs5536_isa_fixup); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_OHC, + loongson_cs5536_ohci_fixup); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_EHC, + loongson_cs5536_ehci_fixup); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_AUDIO, + loongson_cs5536_acc_fixup); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_IDE, + loongson_cs5536_ide_fixup); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_USB, + loongson_nec_fixup); diff --git a/arch/mips/pci/ops-fuloong2e.c b/arch/mips/pci/ops-fuloong2e.c deleted file mode 100644 index 171f65c..0000000 --- a/arch/mips/pci/ops-fuloong2e.c +++ /dev/null @@ -1,154 +0,0 @@ -/* - * fuloong2e specific PCI support. - * - * Copyright (C) 1999, 2000, 2004 MIPS Technologies, Inc. - * All rights reserved. - * Authors: Carsten Langgaard - * Maciej W. Rozycki - * - * Copyright (C) 2009 Lemote Inc. - * Author: Wu Zhangjin - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - */ -#include -#include -#include -#include - -#include - -#define PCI_ACCESS_READ 0 -#define PCI_ACCESS_WRITE 1 - -#define CFG_SPACE_REG(offset) \ - (void *)CKSEG1ADDR(LOONGSON_PCICFG_BASE | (offset)) -#define ID_SEL_BEGIN 11 -#define MAX_DEV_NUM (31 - ID_SEL_BEGIN) - - -static int loongson_pcibios_config_access(unsigned char access_type, - struct pci_bus *bus, - unsigned int devfn, int where, - u32 *data) -{ - u32 busnum = bus->number; - u32 addr, type; - u32 dummy; - void *addrp; - int device = PCI_SLOT(devfn); - int function = PCI_FUNC(devfn); - int reg = where & ~3; - - if (busnum == 0) { - /* Type 0 configuration for onboard PCI bus */ - if (device > MAX_DEV_NUM) - return -1; - - addr = (1 << (device + ID_SEL_BEGIN)) | (function << 8) | reg; - type = 0; - } else { - /* Type 1 configuration for offboard PCI bus */ - addr = (busnum << 16) | (device << 11) | (function << 8) | reg; - type = 0x10000; - } - - /* Clear aborts */ - LOONGSON_PCICMD |= LOONGSON_PCICMD_MABORT_CLR | \ - LOONGSON_PCICMD_MTABORT_CLR; - - LOONGSON_PCIMAP_CFG = (addr >> 16) | type; - - /* Flush Bonito register block */ - dummy = LOONGSON_PCIMAP_CFG; - mmiowb(); - - addrp = CFG_SPACE_REG(addr & 0xffff); - if (access_type == PCI_ACCESS_WRITE) - writel(cpu_to_le32(*data), addrp); - else - *data = le32_to_cpu(readl(addrp)); - - /* Detect Master/Target abort */ - if (LOONGSON_PCICMD & (LOONGSON_PCICMD_MABORT_CLR | - LOONGSON_PCICMD_MTABORT_CLR)) { - /* Error occurred */ - - /* Clear bits */ - LOONGSON_PCICMD |= (LOONGSON_PCICMD_MABORT_CLR | - LOONGSON_PCICMD_MTABORT_CLR); - - return -1; - } - - return 0; - -} - - -/* - * We can't address 8 and 16 bit words directly. Instead we have to - * read/write a 32bit word and mask/modify the data we actually want. - */ -static int loongson_pcibios_read(struct pci_bus *bus, unsigned int devfn, - int where, int size, u32 *val) -{ - u32 data = 0; - - if ((size == 2) && (where & 1)) - return PCIBIOS_BAD_REGISTER_NUMBER; - else if ((size == 4) && (where & 3)) - return PCIBIOS_BAD_REGISTER_NUMBER; - - if (loongson_pcibios_config_access(PCI_ACCESS_READ, bus, devfn, where, - &data)) - return -1; - - if (size == 1) - *val = (data >> ((where & 3) << 3)) & 0xff; - else if (size == 2) - *val = (data >> ((where & 3) << 3)) & 0xffff; - else - *val = data; - - return PCIBIOS_SUCCESSFUL; -} - -static int loongson_pcibios_write(struct pci_bus *bus, unsigned int devfn, - int where, int size, u32 val) -{ - u32 data = 0; - - if ((size == 2) && (where & 1)) - return PCIBIOS_BAD_REGISTER_NUMBER; - else if ((size == 4) && (where & 3)) - return PCIBIOS_BAD_REGISTER_NUMBER; - - if (size == 4) - data = val; - else { - if (loongson_pcibios_config_access(PCI_ACCESS_READ, bus, devfn, - where, &data)) - return -1; - - if (size == 1) - data = (data & ~(0xff << ((where & 3) << 3))) | - (val << ((where & 3) << 3)); - else if (size == 2) - data = (data & ~(0xffff << ((where & 3) << 3))) | - (val << ((where & 3) << 3)); - } - - if (loongson_pcibios_config_access(PCI_ACCESS_WRITE, bus, devfn, where, - &data)) - return -1; - - return PCIBIOS_SUCCESSFUL; -} - -struct pci_ops loongson_pci_ops = { - .read = loongson_pcibios_read, - .write = loongson_pcibios_write -}; diff --git a/arch/mips/pci/ops-loongson2.c b/arch/mips/pci/ops-loongson2.c new file mode 100644 index 0000000..7352142 --- /dev/null +++ b/arch/mips/pci/ops-loongson2.c @@ -0,0 +1,207 @@ +/* + * fuloong2e specific PCI support. + * + * Copyright (C) 1999, 2000, 2004 MIPS Technologies, Inc. + * All rights reserved. + * Authors: Carsten Langgaard + * Maciej W. Rozycki + * + * Copyright (C) 2009 Lemote Inc. + * Author: Wu Zhangjin + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + */ +#include +#include +#include +#include + +#include + +#ifdef CONFIG_CS5536 +#include +#include +#endif + +#define PCI_ACCESS_READ 0 +#define PCI_ACCESS_WRITE 1 + +#define CFG_SPACE_REG(offset) \ + (void *)CKSEG1ADDR(LOONGSON_PCICFG_BASE | (offset)) +#define ID_SEL_BEGIN 11 +#define MAX_DEV_NUM (31 - ID_SEL_BEGIN) + + +static int loongson_pcibios_config_access(unsigned char access_type, + struct pci_bus *bus, + unsigned int devfn, int where, + u32 *data) +{ + u32 busnum = bus->number; + u32 addr, type; + u32 dummy; + void *addrp; + int device = PCI_SLOT(devfn); + int function = PCI_FUNC(devfn); + int reg = where & ~3; + + if (busnum == 0) { + /* board-specific part,currently,only fuloong2f,yeeloong2f + * use CS5536, fuloong2e use via686b, gdium has no + * south bridge + */ +#ifdef CONFIG_CS5536 + /* cs5536_pci_conf_read4/write4() will call _rdmsr/_wrmsr() + * to access the regsters 0xf4,0xf8,0xfc, which is bigger than + * 0xf0, so, it will not go this branch, but the others. so, + * no calling dead loop here. + */ + if ((PCI_IDSEL_CS5536 == device) && (reg < 0xF0)) { + switch (access_type) { + case PCI_ACCESS_READ: + *data = cs5536_pci_conf_read4(function, reg); + break; + case PCI_ACCESS_WRITE: + cs5536_pci_conf_write4(function, reg, *data); + break; + } + return 0; + } +#endif + /* Type 0 configuration for onboard PCI bus */ + if (device > MAX_DEV_NUM) + return -1; + + addr = (1 << (device + ID_SEL_BEGIN)) | (function << 8) | reg; + type = 0; + } else { + /* Type 1 configuration for offboard PCI bus */ + addr = (busnum << 16) | (device << 11) | (function << 8) | reg; + type = 0x10000; + } + + /* Clear aborts */ + LOONGSON_PCICMD |= LOONGSON_PCICMD_MABORT_CLR | \ + LOONGSON_PCICMD_MTABORT_CLR; + + LOONGSON_PCIMAP_CFG = (addr >> 16) | type; + + /* Flush Bonito register block */ + dummy = LOONGSON_PCIMAP_CFG; + mmiowb(); + + addrp = CFG_SPACE_REG(addr & 0xffff); + if (access_type == PCI_ACCESS_WRITE) + writel(cpu_to_le32(*data), addrp); + else + *data = le32_to_cpu(readl(addrp)); + + /* Detect Master/Target abort */ + if (LOONGSON_PCICMD & (LOONGSON_PCICMD_MABORT_CLR | + LOONGSON_PCICMD_MTABORT_CLR)) { + /* Error occurred */ + + /* Clear bits */ + LOONGSON_PCICMD |= (LOONGSON_PCICMD_MABORT_CLR | + LOONGSON_PCICMD_MTABORT_CLR); + + return -1; + } + + return 0; + +} + + +/* + * We can't address 8 and 16 bit words directly. Instead we have to + * read/write a 32bit word and mask/modify the data we actually want. + */ +static int loongson_pcibios_read(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 *val) +{ + u32 data = 0; + + if ((size == 2) && (where & 1)) + return PCIBIOS_BAD_REGISTER_NUMBER; + else if ((size == 4) && (where & 3)) + return PCIBIOS_BAD_REGISTER_NUMBER; + + if (loongson_pcibios_config_access(PCI_ACCESS_READ, bus, devfn, where, + &data)) + return -1; + + if (size == 1) + *val = (data >> ((where & 3) << 3)) & 0xff; + else if (size == 2) + *val = (data >> ((where & 3) << 3)) & 0xffff; + else + *val = data; + + return PCIBIOS_SUCCESSFUL; +} + +static int loongson_pcibios_write(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 val) +{ + u32 data = 0; + + if ((size == 2) && (where & 1)) + return PCIBIOS_BAD_REGISTER_NUMBER; + else if ((size == 4) && (where & 3)) + return PCIBIOS_BAD_REGISTER_NUMBER; + + if (size == 4) + data = val; + else { + if (loongson_pcibios_config_access(PCI_ACCESS_READ, bus, devfn, + where, &data)) + return -1; + + if (size == 1) + data = (data & ~(0xff << ((where & 3) << 3))) | + (val << ((where & 3) << 3)); + else if (size == 2) + data = (data & ~(0xffff << ((where & 3) << 3))) | + (val << ((where & 3) << 3)); + } + + if (loongson_pcibios_config_access(PCI_ACCESS_WRITE, bus, devfn, where, + &data)) + return -1; + + return PCIBIOS_SUCCESSFUL; +} + +struct pci_ops loongson_pci_ops = { + .read = loongson_pcibios_read, + .write = loongson_pcibios_write +}; + +#ifdef CONFIG_CS5536 +void _rdmsr(u32 msr, u32 *hi, u32 *lo) +{ + struct pci_bus bus = { + .number = PCI_BUS_CS5536 + }; + u32 devfn = PCI_DEVFN(PCI_IDSEL_CS5536, 0); + loongson_pcibios_write(&bus, devfn, PCI_MSR_ADDR, 4, msr); + loongson_pcibios_read(&bus, devfn, PCI_MSR_DATA_LO, 4, lo); + loongson_pcibios_read(&bus, devfn, PCI_MSR_DATA_HI, 4, hi); +} +EXPORT_SYMBOL(_rdmsr); + +void _wrmsr(u32 msr, u32 hi, u32 lo) +{ + struct pci_bus bus = { + .number = PCI_BUS_CS5536 + }; + u32 devfn = PCI_DEVFN(PCI_IDSEL_CS5536, 0); + loongson_pcibios_write(&bus, devfn, PCI_MSR_ADDR, 4, msr); + loongson_pcibios_write(&bus, devfn, PCI_MSR_DATA_LO, 4, lo); + loongson_pcibios_write(&bus, devfn, PCI_MSR_DATA_HI, 4, hi); +} +EXPORT_SYMBOL(_wrmsr); +#endif -- 1.6.2.1 From wuzhangjin@gmail.com Wed Nov 4 10:06:52 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 04 Nov 2009 10:06:59 +0100 (CET) Received: from mail-pz0-f194.google.com ([209.85.222.194]:45687 "EHLO mail-pz0-f194.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492635AbZKDJG0 (ORCPT ); Wed, 4 Nov 2009 10:06:26 +0100 Received: by pzk32 with SMTP id 32so4707427pzk.21 for ; Wed, 04 Nov 2009 01:06:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer:in-reply-to:references; bh=VlbIkpAFSNzmIC7cIiqhqnxhrkxOf1q9N2cTY1gu5wU=; b=LAJEPou1JABakGomxSwuf11xQAcVJn5u8+bgWBKR4oZUkWOKW/i4OFkyjuat16fjFR ERbpLf5ODliZK+sXR2GrYiE6BaIwpnP0D8Dli6wFRVwM8pfMwl/5bf23+2rUE5oPFmMy G9xVirdGApYThfI6dJzskacGXeHxD2TnIRSaI= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; b=G1JZ2U3GTEbXD0jykF8admYWCm9q4wgYugbeMG+MwLa7ibPmwxSFYTg65LkRFHLXs6 9wRYpqpBkZ20Um64J3/fByhZjkLborMbPOz4ZIeXfrQKI9i1tm2bQ27j9RWv2kWNkmIN 5bwmp/a0w1Pf3xAkTHT8w2EdF4szxW2Agiwqc= Received: by 10.115.65.11 with SMTP id s11mr1616355wak.170.1257325580156; Wed, 04 Nov 2009 01:06:20 -0800 (PST) Received: from localhost.localdomain ([222.92.8.142]) by mx.google.com with ESMTPS id 20sm528567pxi.15.2009.11.04.01.06.14 (version=TLSv1/SSLv3 cipher=RC4-MD5); Wed, 04 Nov 2009 01:06:19 -0800 (PST) From: Wu Zhangjin To: Ralf Baechle Cc: Wu Zhangjin , linux-mips@linux-mips.org, LKML , huhb@lemote.com, yanh@lemote.com, Zhang Le , Thomas Gleixner , Nicholas Mc Guire , zhangfx@lemote.com, liujl@lemote.com Subject: [PATCH -queue v0 5/6] [loongson] rtc: enable legacy RTC driver on fuloong2f Date: Wed, 4 Nov 2009 17:06:07 +0800 Message-Id: X-Mailer: git-send-email 1.6.2.1 In-Reply-To: References: Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24663 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips RTC_LIB is selected by MIPS by default, and therefore, the legacy RTC driver is disabled. but fortunately, RTC_LIB not works on fulong, so, enabling the legcy RTC driver is needed, otherwise, the tools like hwclock will not work. because loongson family machines, including fuloong2e, fuloong2f and yeeloong2f need to enable legacy RTC driver, so we use MACH_LOONGSON here. Signed-off-by: Wu Zhangjin --- arch/mips/Kconfig | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 8417357..6a9bdda 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -7,7 +7,7 @@ config MIPS select HAVE_ARCH_KGDB # Horrible source of confusion. Die, die, die ... select EMBEDDED - select RTC_LIB if !LEMOTE_FULOONG2E + select RTC_LIB if !MACH_LOONGSON mainmenu "Linux/MIPS Kernel Configuration" -- 1.6.2.1 From wuzhangjin@gmail.com Wed Nov 4 10:07:17 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 04 Nov 2009 10:07:25 +0100 (CET) Received: from mail-px0-f188.google.com ([209.85.216.188]:37765 "EHLO mail-px0-f188.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492672AbZKDJHH (ORCPT ); Wed, 4 Nov 2009 10:07:07 +0100 Received: by pxi26 with SMTP id 26so4710487pxi.22 for ; Wed, 04 Nov 2009 01:06:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer:in-reply-to:references; bh=GuC0RcyM3UoHcfwlAUgwsq8ByaQMW8OCIeRBXk5CGpE=; b=CrYFIYTxMzlOKpBjU8hSVOLPszomePG6LYO4uCZYrICXj1OfEK6j4eooglnLfmuXCa sFMfK4AJTpoc/yjtiaXzzXQff6xJvKiJyy2pqWOVvyu1f2Ehv0KKjwaVu1AdWj0Md7+6 /H06ZB4P4Gg/NA+EdvkzqJPnEvKLJjkb3lcEM= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; b=xudwuLCPsNrjb50F0xrs8o5Kc1AtfdN+TlTVI+tg8g41P7fj+ZFcenmXZ5Up5YhYzM RC4EHYkP94KQIflEm4g0A6uILAlPNuK2WcolUZibIATQeZ0JlFCGHE+6d/+dT34vm3FJ wZ9lBGW17bqP2F6Ku1prvHyzBmAHi6UMTRfeM= Received: by 10.114.69.18 with SMTP id r18mr1619914waa.209.1257325617862; Wed, 04 Nov 2009 01:06:57 -0800 (PST) Received: from localhost.localdomain ([222.92.8.142]) by mx.google.com with ESMTPS id 21sm533593pxi.8.2009.11.04.01.06.44 (version=TLSv1/SSLv3 cipher=RC4-MD5); Wed, 04 Nov 2009 01:06:57 -0800 (PST) From: Wu Zhangjin To: Ralf Baechle Cc: Wu Zhangjin , linux-mips@linux-mips.org, LKML , huhb@lemote.com, yanh@lemote.com, Zhang Le , Thomas Gleixner , Nicholas Mc Guire , zhangfx@lemote.com, liujl@lemote.com Subject: [PATCH -queue v0 6/6] [loongson] add default config file for fuloong2f Date: Wed, 4 Nov 2009 17:06:26 +0800 Message-Id: <518b824df9e28ea625c6723711cfd7e5e12f0890.1257325319.git.wuzhangjin@gmail.com> X-Mailer: git-send-email 1.6.2.1 In-Reply-To: References: Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24664 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips Signed-off-by: Wu Zhangjin --- arch/mips/configs/fuloong2f_defconfig | 1608 +++++++++++++++++++++++++++++++++ 1 files changed, 1608 insertions(+), 0 deletions(-) create mode 100644 arch/mips/configs/fuloong2f_defconfig diff --git a/arch/mips/configs/fuloong2f_defconfig b/arch/mips/configs/fuloong2f_defconfig new file mode 100644 index 0000000..9d29cd5 --- /dev/null +++ b/arch/mips/configs/fuloong2f_defconfig @@ -0,0 +1,1608 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.32-rc6 +# Wed Nov 4 15:58:08 2009 +# +CONFIG_MIPS=y + +# +# Machine selection +# +# CONFIG_MACH_ALCHEMY is not set +# CONFIG_AR7 is not set +# CONFIG_BASLER_EXCITE is not set +# CONFIG_BCM47XX is not set +# CONFIG_BCM63XX is not set +# CONFIG_MIPS_COBALT is not set +# CONFIG_MACH_DECSTATION is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_LASAT is not set +CONFIG_MACH_LOONGSON=y +# CONFIG_MIPS_MALTA is not set +# CONFIG_MIPS_SIM is not set +# CONFIG_NEC_MARKEINS is not set +# CONFIG_MACH_VR41XX is not set +# CONFIG_NXP_STB220 is not set +# CONFIG_NXP_STB225 is not set +# CONFIG_PNX8550_JBS is not set +# CONFIG_PNX8550_STB810 is not set +# CONFIG_PMC_MSP is not set +# CONFIG_PMC_YOSEMITE is not set +# CONFIG_SGI_IP22 is not set +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP28 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_CRHONE is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_BIGSUR is not set +# CONFIG_SNI_RM is not set +# CONFIG_MACH_TX39XX is not set +# CONFIG_MACH_TX49XX is not set +# CONFIG_MIKROTIK_RB532 is not set +# CONFIG_WR_PPMC is not set +# CONFIG_CAVIUM_OCTEON_SIMULATOR is not set +# CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD is not set +# CONFIG_ALCHEMY_GPIO_INDIRECT is not set +CONFIG_ARCH_SPARSEMEM_ENABLE=y +# CONFIG_LEMOTE_FULOONG2E is not set +CONFIG_LEMOTE_FULOONG2F=y +CONFIG_CS5536=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_ARCH_SUPPORTS_OPROFILE=y +CONFIG_GENERIC_FIND_NEXT_BIT=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CMOS_UPDATE=y +CONFIG_SCHED_OMIT_FRAME_POINTER=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +CONFIG_CEVT_R4K_LIB=y +CONFIG_CEVT_R4K=y +CONFIG_CSRC_R4K_LIB=y +CONFIG_CSRC_R4K=y +CONFIG_DMA_NONCOHERENT=y +CONFIG_DMA_NEED_PCI_MAP_STATE=y +CONFIG_EARLY_PRINTK=y +CONFIG_SYS_HAS_EARLY_PRINTK=y +CONFIG_I8259=y +# CONFIG_NO_IOPORT is not set +CONFIG_GENERIC_ISA_DMA=y +CONFIG_GENERIC_ISA_DMA_SUPPORT_BROKEN=y +# CONFIG_CPU_BIG_ENDIAN is not set +CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y +CONFIG_IRQ_CPU=y +CONFIG_BOOT_ELF32=y +CONFIG_MIPS_L1_CACHE_SHIFT=5 + +# +# CPU selection +# +# CONFIG_CPU_LOONGSON2E is not set +CONFIG_CPU_LOONGSON2F=y +# CONFIG_CPU_MIPS32_R1 is not set +# CONFIG_CPU_MIPS32_R2 is not set +# CONFIG_CPU_MIPS64_R1 is not set +# CONFIG_CPU_MIPS64_R2 is not set +# CONFIG_CPU_R3000 is not set +# CONFIG_CPU_TX39XX is not set +# CONFIG_CPU_VR41XX is not set +# CONFIG_CPU_R4300 is not set +# CONFIG_CPU_R4X00 is not set +# CONFIG_CPU_TX49XX is not set +# CONFIG_CPU_R5000 is not set +# CONFIG_CPU_R5432 is not set +# CONFIG_CPU_R5500 is not set +# CONFIG_CPU_R6000 is not set +# CONFIG_CPU_NEVADA is not set +# CONFIG_CPU_R8000 is not set +# CONFIG_CPU_R10000 is not set +# CONFIG_CPU_RM7000 is not set +# CONFIG_CPU_RM9000 is not set +# CONFIG_CPU_SB1 is not set +# CONFIG_CPU_CAVIUM_OCTEON is not set +CONFIG_SYS_SUPPORTS_ZBOOT=y +CONFIG_SYS_SUPPORTS_ZBOOT_UART16550=y +CONFIG_CPU_LOONGSON2=y +CONFIG_SYS_HAS_CPU_LOONGSON2F=y +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y + +# +# Kernel type +# +# CONFIG_32BIT is not set +CONFIG_64BIT=y +# CONFIG_PAGE_SIZE_4KB is not set +# CONFIG_PAGE_SIZE_8KB is not set +CONFIG_PAGE_SIZE_16KB=y +# CONFIG_PAGE_SIZE_32KB is not set +# CONFIG_PAGE_SIZE_64KB is not set +CONFIG_BOARD_SCACHE=y +CONFIG_MIPS_MT_DISABLED=y +# CONFIG_MIPS_MT_SMP is not set +# CONFIG_MIPS_MT_SMTC is not set +CONFIG_CPU_HAS_WB=y +CONFIG_CPU_HAS_SYNC=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_CPU_SUPPORTS_HIGHMEM=y +CONFIG_SYS_SUPPORTS_HIGHMEM=y +CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_ARCH_POPULATES_NODE_MAP=y +CONFIG_SELECT_MEMORY_MODEL=y +# CONFIG_FLATMEM_MANUAL is not set +# CONFIG_DISCONTIGMEM_MANUAL is not set +CONFIG_SPARSEMEM_MANUAL=y +CONFIG_SPARSEMEM=y +CONFIG_HAVE_MEMORY_PRESENT=y +CONFIG_SPARSEMEM_STATIC=y + +# +# Memory hotplug is currently incompatible with Software Suspend +# +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +CONFIG_PHYS_ADDR_T_64BIT=y +CONFIG_ZONE_DMA_FLAG=0 +CONFIG_VIRT_TO_BUS=y +CONFIG_HAVE_MLOCK=y +CONFIG_HAVE_MLOCKED_PAGE_BIT=y +# CONFIG_KSM is not set +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +# CONFIG_HZ_48 is not set +# CONFIG_HZ_100 is not set +# CONFIG_HZ_128 is not set +CONFIG_HZ_250=y +# CONFIG_HZ_256 is not set +# CONFIG_HZ_1000 is not set +# CONFIG_HZ_1024 is not set +CONFIG_SYS_SUPPORTS_ARBIT_HZ=y +CONFIG_HZ=250 +# CONFIG_PREEMPT_NONE is not set +CONFIG_PREEMPT_VOLUNTARY=y +# CONFIG_PREEMPT is not set +# CONFIG_KEXEC is not set +# CONFIG_SECCOMP is not set +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_CONSTRUCTORS=y + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="" +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_BZIP2=y +CONFIG_HAVE_KERNEL_LZMA=y +CONFIG_KERNEL_GZIP=y +# CONFIG_KERNEL_BZIP2 is not set +# CONFIG_KERNEL_LZMA is not set +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_POSIX_MQUEUE is not set +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y +# CONFIG_TASKSTATS is not set +CONFIG_AUDIT=y + +# +# RCU Subsystem +# +CONFIG_TREE_RCU=y +# CONFIG_TREE_PREEMPT_RCU is not set +# CONFIG_RCU_TRACE is not set +CONFIG_RCU_FANOUT=64 +# CONFIG_RCU_FANOUT_EXACT is not set +# CONFIG_TREE_RCU_TRACE is not set +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=15 +# CONFIG_GROUP_SCHED is not set +# CONFIG_CGROUPS is not set +CONFIG_SYSFS_DEPRECATED=y +CONFIG_SYSFS_DEPRECATED_V2=y +# CONFIG_RELAY is not set +# CONFIG_NAMESPACES is not set +# CONFIG_BLK_DEV_INITRD is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +CONFIG_EMBEDDED=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_PCSPKR_PLATFORM=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y + +# +# Kernel Performance Events And Counters +# +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_PCI_QUIRKS=y +CONFIG_SLUB_DEBUG=y +# CONFIG_COMPAT_BRK is not set +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +CONFIG_HAVE_OPROFILE=y +CONFIG_HAVE_SYSCALL_WRAPPERS=y + +# +# GCOV-based kernel profiling +# +# CONFIG_SLOW_WORK is not set +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +CONFIG_MODVERSIONS=y +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_BLOCK=y +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set +CONFIG_BLOCK_COMPAT=y + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +# CONFIG_DEFAULT_AS is not set +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" +CONFIG_FREEZER=y + +# +# Bus options (PCI, PCMCIA, EISA, ISA, TC) +# +CONFIG_HW_HAS_PCI=y +CONFIG_PCI=y +CONFIG_PCI_DOMAINS=y +# CONFIG_ARCH_SUPPORTS_MSI is not set +CONFIG_PCI_LEGACY=y +# CONFIG_PCI_STUB is not set +# CONFIG_PCI_IOV is not set +CONFIG_ISA=y +CONFIG_MMU=y +# CONFIG_PCCARD is not set +# CONFIG_HOTPLUG_PCI is not set + +# +# Executable file formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set +# CONFIG_BINFMT_MISC is not set +CONFIG_MIPS32_COMPAT=y +CONFIG_COMPAT=y +CONFIG_SYSVIPC_COMPAT=y +CONFIG_MIPS32_O32=y +CONFIG_MIPS32_N32=y +CONFIG_BINFMT_ELF32=y + +# +# Power management options +# +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_PM=y +# CONFIG_PM_DEBUG is not set +CONFIG_PM_SLEEP=y +CONFIG_SUSPEND=y +CONFIG_SUSPEND_FREEZER=y +CONFIG_HIBERNATION_NVS=y +CONFIG_HIBERNATION=y +CONFIG_PM_STD_PARTITION="/dev/hda3" +# CONFIG_PM_RUNTIME is not set +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_PACKET_MMAP=y +CONFIG_UNIX=y +CONFIG_XFRM=y +# CONFIG_XFRM_USER is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set +# CONFIG_NET_KEY is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_ASK_IP_FIB_HASH=y +# CONFIG_IP_FIB_TRIE is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_IP_ROUTE_MULTIPATH=y +CONFIG_IP_ROUTE_VERBOSE=y +# CONFIG_IP_PNP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +CONFIG_IP_MROUTE=y +CONFIG_IP_PIMSM_V1=y +CONFIG_IP_PIMSM_V2=y +# CONFIG_ARPD is not set +CONFIG_SYN_COOKIES=y +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +CONFIG_INET_TUNNEL=m +CONFIG_INET_XFRM_MODE_TRANSPORT=m +CONFIG_INET_XFRM_MODE_TUNNEL=m +CONFIG_INET_XFRM_MODE_BEET=m +CONFIG_INET_LRO=y +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +CONFIG_TCP_CONG_ADVANCED=y +CONFIG_TCP_CONG_BIC=y +CONFIG_TCP_CONG_CUBIC=y +CONFIG_TCP_CONG_WESTWOOD=m +CONFIG_TCP_CONG_HTCP=m +# CONFIG_TCP_CONG_HSTCP is not set +# CONFIG_TCP_CONG_HYBLA is not set +# CONFIG_TCP_CONG_VEGAS is not set +# CONFIG_TCP_CONG_SCALABLE is not set +# CONFIG_TCP_CONG_LP is not set +# CONFIG_TCP_CONG_VENO is not set +# CONFIG_TCP_CONG_YEAH is not set +# CONFIG_TCP_CONG_ILLINOIS is not set +CONFIG_DEFAULT_BIC=y +# CONFIG_DEFAULT_CUBIC is not set +# CONFIG_DEFAULT_HTCP is not set +# CONFIG_DEFAULT_VEGAS is not set +# CONFIG_DEFAULT_WESTWOOD is not set +# CONFIG_DEFAULT_RENO is not set +CONFIG_DEFAULT_TCP_CONG="bic" +# CONFIG_TCP_MD5SIG is not set +CONFIG_IPV6=m +CONFIG_IPV6_PRIVACY=y +# CONFIG_IPV6_ROUTER_PREF is not set +# CONFIG_IPV6_OPTIMISTIC_DAD is not set +# CONFIG_INET6_AH is not set +# CONFIG_INET6_ESP is not set +# CONFIG_INET6_IPCOMP is not set +# CONFIG_IPV6_MIP6 is not set +# CONFIG_INET6_XFRM_TUNNEL is not set +# CONFIG_INET6_TUNNEL is not set +CONFIG_INET6_XFRM_MODE_TRANSPORT=m +CONFIG_INET6_XFRM_MODE_TUNNEL=m +CONFIG_INET6_XFRM_MODE_BEET=m +# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set +CONFIG_IPV6_SIT=m +CONFIG_IPV6_NDISC_NODETYPE=y +# CONFIG_IPV6_TUNNEL is not set +# CONFIG_IPV6_MULTIPLE_TABLES is not set +# CONFIG_IPV6_MROUTE is not set +CONFIG_NETWORK_SECMARK=y +CONFIG_NETFILTER=y +# CONFIG_NETFILTER_DEBUG is not set +CONFIG_NETFILTER_ADVANCED=y + +# +# Core Netfilter Configuration +# +# CONFIG_NETFILTER_NETLINK_QUEUE is not set +# CONFIG_NETFILTER_NETLINK_LOG is not set +# CONFIG_NF_CONNTRACK is not set +# CONFIG_NETFILTER_XTABLES is not set +# CONFIG_IP_VS is not set + +# +# IP: Netfilter Configuration +# +# CONFIG_NF_DEFRAG_IPV4 is not set +# CONFIG_IP_NF_QUEUE is not set +# CONFIG_IP_NF_IPTABLES is not set +# CONFIG_IP_NF_ARPTABLES is not set + +# +# IPv6: Netfilter Configuration +# +# CONFIG_IP6_NF_QUEUE is not set +# CONFIG_IP6_NF_IPTABLES is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_RDS is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_PHONET is not set +# CONFIG_IEEE802154 is not set +CONFIG_NET_SCHED=y + +# +# Queueing/Scheduling +# +# CONFIG_NET_SCH_CBQ is not set +# CONFIG_NET_SCH_HTB is not set +# CONFIG_NET_SCH_HFSC is not set +# CONFIG_NET_SCH_PRIO is not set +# CONFIG_NET_SCH_MULTIQ is not set +# CONFIG_NET_SCH_RED is not set +# CONFIG_NET_SCH_SFQ is not set +# CONFIG_NET_SCH_TEQL is not set +# CONFIG_NET_SCH_TBF is not set +# CONFIG_NET_SCH_GRED is not set +# CONFIG_NET_SCH_DSMARK is not set +# CONFIG_NET_SCH_NETEM is not set +# CONFIG_NET_SCH_DRR is not set +# CONFIG_NET_SCH_INGRESS is not set + +# +# Classification +# +CONFIG_NET_CLS=y +# CONFIG_NET_CLS_BASIC is not set +# CONFIG_NET_CLS_TCINDEX is not set +# CONFIG_NET_CLS_ROUTE4 is not set +# CONFIG_NET_CLS_FW is not set +# CONFIG_NET_CLS_U32 is not set +# CONFIG_NET_CLS_RSVP is not set +# CONFIG_NET_CLS_RSVP6 is not set +# CONFIG_NET_CLS_FLOW is not set +CONFIG_NET_EMATCH=y +CONFIG_NET_EMATCH_STACK=32 +# CONFIG_NET_EMATCH_CMP is not set +# CONFIG_NET_EMATCH_NBYTE is not set +# CONFIG_NET_EMATCH_U32 is not set +# CONFIG_NET_EMATCH_META is not set +# CONFIG_NET_EMATCH_TEXT is not set +CONFIG_NET_CLS_ACT=y +# CONFIG_NET_ACT_POLICE is not set +# CONFIG_NET_ACT_GACT is not set +# CONFIG_NET_ACT_MIRRED is not set +# CONFIG_NET_ACT_NAT is not set +# CONFIG_NET_ACT_PEDIT is not set +# CONFIG_NET_ACT_SIMP is not set +# CONFIG_NET_ACT_SKBEDIT is not set +CONFIG_NET_SCH_FIFO=y +# CONFIG_DCB is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set +CONFIG_FIB_RULES=y +# CONFIG_WIRELESS is not set +# CONFIG_WIMAX is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +# CONFIG_DEVTMPFS is not set +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_CONNECTOR is not set +# CONFIG_MTD is not set +# CONFIG_PARPORT is not set +# CONFIG_PNP is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_CPQ_DA is not set +# CONFIG_BLK_CPQ_CISS_DA is not set +# CONFIG_BLK_DEV_DAC960 is not set +# CONFIG_BLK_DEV_UMEM is not set +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_CRYPTOLOOP=y +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_SX8 is not set +# CONFIG_BLK_DEV_UB is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=8192 +# CONFIG_BLK_DEV_XIP is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +# CONFIG_BLK_DEV_HD is not set +CONFIG_MISC_DEVICES=y +# CONFIG_PHANTOM is not set +# CONFIG_SGI_IOC4 is not set +# CONFIG_TIFM_CORE is not set +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_HP_ILO is not set +# CONFIG_C2PORT is not set + +# +# EEPROM support +# +# CONFIG_EEPROM_93CX6 is not set +# CONFIG_CB710_CORE is not set +CONFIG_HAVE_IDE=y +CONFIG_IDE=y + +# +# Please see Documentation/ide/ide.txt for help/info on IDE drives +# +CONFIG_IDE_XFER_MODE=y +CONFIG_IDE_TIMINGS=y +# CONFIG_BLK_DEV_IDE_SATA is not set +CONFIG_IDE_GD=y +CONFIG_IDE_GD_ATA=y +# CONFIG_IDE_GD_ATAPI is not set +# CONFIG_BLK_DEV_IDECD is not set +# CONFIG_BLK_DEV_IDETAPE is not set +CONFIG_IDE_TASK_IOCTL=y +CONFIG_IDE_PROC_FS=y + +# +# IDE chipset support/bugfixes +# +# CONFIG_IDE_GENERIC is not set +# CONFIG_BLK_DEV_PLATFORM is not set +CONFIG_BLK_DEV_IDEDMA_SFF=y + +# +# PCI IDE chipsets support +# +CONFIG_BLK_DEV_IDEPCI=y +# CONFIG_IDEPCI_PCIBUS_ORDER is not set +# CONFIG_BLK_DEV_OFFBOARD is not set +CONFIG_BLK_DEV_GENERIC=y +# CONFIG_BLK_DEV_OPTI621 is not set +CONFIG_BLK_DEV_IDEDMA_PCI=y +# CONFIG_BLK_DEV_AEC62XX is not set +# CONFIG_BLK_DEV_ALI15X3 is not set +CONFIG_BLK_DEV_AMD74XX=y +# CONFIG_BLK_DEV_CMD64X is not set +# CONFIG_BLK_DEV_TRIFLEX is not set +# CONFIG_BLK_DEV_CS5520 is not set +# CONFIG_BLK_DEV_CS5530 is not set +# CONFIG_BLK_DEV_HPT366 is not set +# CONFIG_BLK_DEV_JMICRON is not set +# CONFIG_BLK_DEV_SC1200 is not set +# CONFIG_BLK_DEV_PIIX is not set +# CONFIG_BLK_DEV_IT8172 is not set +# CONFIG_BLK_DEV_IT8213 is not set +# CONFIG_BLK_DEV_IT821X is not set +# CONFIG_BLK_DEV_NS87415 is not set +# CONFIG_BLK_DEV_PDC202XX_OLD is not set +# CONFIG_BLK_DEV_PDC202XX_NEW is not set +# CONFIG_BLK_DEV_SVWKS is not set +# CONFIG_BLK_DEV_SIIMAGE is not set +# CONFIG_BLK_DEV_SLC90E66 is not set +# CONFIG_BLK_DEV_TRM290 is not set +# CONFIG_BLK_DEV_VIA82CXXX is not set +# CONFIG_BLK_DEV_TC86C001 is not set + +# +# Other IDE chipsets support +# + +# +# Note: most of these also require special kernel boot parameters +# +# CONFIG_BLK_DEV_4DRIVES is not set +# CONFIG_BLK_DEV_ALI14XX is not set +# CONFIG_BLK_DEV_DTC2278 is not set +# CONFIG_BLK_DEV_HT6560B is not set +# CONFIG_BLK_DEV_QD65XX is not set +# CONFIG_BLK_DEV_UMC8672 is not set +CONFIG_BLK_DEV_IDEDMA=y + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=m +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_NETLINK is not set +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=m +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_BLK_DEV_SR is not set +# CONFIG_CHR_DEV_SG is not set +# CONFIG_CHR_DEV_SCH is not set +CONFIG_SCSI_MULTI_LUN=y +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set +CONFIG_SCSI_WAIT_SCAN=m + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +# CONFIG_SCSI_LOWLEVEL is not set +# CONFIG_SCSI_DH is not set +# CONFIG_SCSI_OSD_INITIATOR is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +# CONFIG_FUSION is not set + +# +# IEEE 1394 (FireWire) support +# + +# +# You can enable one or both FireWire driver stacks. +# + +# +# See the help texts for more information. +# +# CONFIG_FIREWIRE is not set +# CONFIG_IEEE1394 is not set +# CONFIG_I2O is not set +CONFIG_NETDEVICES=y +# CONFIG_IFB is not set +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_VETH is not set +# CONFIG_ARCNET is not set +# CONFIG_NET_ETHERNET is not set +CONFIG_MII=m +CONFIG_NETDEV_1000=y +# CONFIG_ACENIC is not set +# CONFIG_DL2K is not set +# CONFIG_E1000 is not set +# CONFIG_E1000E is not set +# CONFIG_IP1000 is not set +# CONFIG_IGB is not set +# CONFIG_IGBVF is not set +# CONFIG_NS83820 is not set +# CONFIG_HAMACHI is not set +# CONFIG_YELLOWFIN is not set +CONFIG_R8169=m +# CONFIG_SIS190 is not set +# CONFIG_SKGE is not set +# CONFIG_SKY2 is not set +# CONFIG_VIA_VELOCITY is not set +# CONFIG_TIGON3 is not set +# CONFIG_BNX2 is not set +# CONFIG_CNIC is not set +# CONFIG_QLA3XXX is not set +# CONFIG_ATL1 is not set +# CONFIG_ATL1E is not set +# CONFIG_ATL1C is not set +# CONFIG_JME is not set +# CONFIG_NETDEV_10000 is not set +# CONFIG_TR is not set +CONFIG_WLAN=y +# CONFIG_WLAN_PRE80211 is not set +# CONFIG_WLAN_80211 is not set + +# +# Enable WiMAX (Networking options) to see the WiMAX drivers +# + +# +# USB Network Adapters +# +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_USBNET is not set +# CONFIG_WAN is not set +# CONFIG_FDDI is not set +# CONFIG_HIPPI is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_NET_FC is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_ISDN is not set +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_MOUSEDEV_PSAUX=y +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +CONFIG_DEVKMEM=y +CONFIG_SERIAL_NONSTANDARD=y +# CONFIG_COMPUTONE is not set +# CONFIG_ROCKETPORT is not set +# CONFIG_CYCLADES is not set +# CONFIG_DIGIEPCA is not set +# CONFIG_MOXA_INTELLIO is not set +# CONFIG_MOXA_SMARTIO is not set +# CONFIG_ISI is not set +# CONFIG_SYNCLINKMP is not set +# CONFIG_SYNCLINK_GT is not set +# CONFIG_N_HDLC is not set +# CONFIG_RISCOM8 is not set +# CONFIG_SPECIALIX is not set +# CONFIG_STALDRV is not set +# CONFIG_NOZOMI is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +# CONFIG_SERIAL_8250_PCI is not set +CONFIG_SERIAL_8250_NR_UARTS=16 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +CONFIG_SERIAL_8250_EXTENDED=y +CONFIG_SERIAL_8250_MANY_PORTS=y +CONFIG_SERIAL_8250_FOURPORT=y +# CONFIG_SERIAL_8250_ACCENT is not set +# CONFIG_SERIAL_8250_BOCA is not set +# CONFIG_SERIAL_8250_EXAR_ST16C554 is not set +# CONFIG_SERIAL_8250_HUB6 is not set +# CONFIG_SERIAL_8250_SHARE_IRQ is not set +# CONFIG_SERIAL_8250_DETECT_IRQ is not set +# CONFIG_SERIAL_8250_RSA is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_JSM is not set +CONFIG_UNIX98_PTYS=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=16 +# CONFIG_IPMI_HANDLER is not set +CONFIG_HW_RANDOM=y +# CONFIG_HW_RANDOM_TIMERIOMEM is not set +CONFIG_RTC=y +# CONFIG_DTLK is not set +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +CONFIG_DEVPORT=y +# CONFIG_I2C is not set +# CONFIG_SPI is not set + +# +# PPS support +# +# CONFIG_PPS is not set +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +# CONFIG_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_REGULATOR is not set +CONFIG_MEDIA_SUPPORT=m + +# +# Multimedia core support +# +CONFIG_VIDEO_DEV=m +CONFIG_VIDEO_V4L2_COMMON=m +CONFIG_VIDEO_ALLOW_V4L1=y +CONFIG_VIDEO_V4L1_COMPAT=y +# CONFIG_DVB_CORE is not set +CONFIG_VIDEO_MEDIA=m + +# +# Multimedia drivers +# +# CONFIG_MEDIA_ATTACH is not set +CONFIG_VIDEO_V4L2=m +CONFIG_VIDEO_V4L1=m +CONFIG_VIDEO_CAPTURE_DRIVERS=y +# CONFIG_VIDEO_ADV_DEBUG is not set +# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set +CONFIG_VIDEO_HELPER_CHIPS_AUTO=y +# CONFIG_VIDEO_VIVI is not set +# CONFIG_VIDEO_PMS is not set +# CONFIG_VIDEO_CPIA is not set +# CONFIG_VIDEO_CPIA2 is not set +# CONFIG_VIDEO_STRADIS is not set +CONFIG_V4L_USB_DRIVERS=y +# CONFIG_USB_VIDEO_CLASS is not set +CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y +CONFIG_USB_GSPCA=m +# CONFIG_USB_M5602 is not set +# CONFIG_USB_STV06XX is not set +# CONFIG_USB_GL860 is not set +# CONFIG_USB_GSPCA_CONEX is not set +# CONFIG_USB_GSPCA_ETOMS is not set +# CONFIG_USB_GSPCA_FINEPIX is not set +# CONFIG_USB_GSPCA_JEILINJ is not set +# CONFIG_USB_GSPCA_MARS is not set +# CONFIG_USB_GSPCA_MR97310A is not set +# CONFIG_USB_GSPCA_OV519 is not set +# CONFIG_USB_GSPCA_OV534 is not set +# CONFIG_USB_GSPCA_PAC207 is not set +# CONFIG_USB_GSPCA_PAC7311 is not set +# CONFIG_USB_GSPCA_SN9C20X is not set +# CONFIG_USB_GSPCA_SONIXB is not set +# CONFIG_USB_GSPCA_SONIXJ is not set +# CONFIG_USB_GSPCA_SPCA500 is not set +# CONFIG_USB_GSPCA_SPCA501 is not set +# CONFIG_USB_GSPCA_SPCA505 is not set +# CONFIG_USB_GSPCA_SPCA506 is not set +# CONFIG_USB_GSPCA_SPCA508 is not set +# CONFIG_USB_GSPCA_SPCA561 is not set +# CONFIG_USB_GSPCA_SQ905 is not set +# CONFIG_USB_GSPCA_SQ905C is not set +# CONFIG_USB_GSPCA_STK014 is not set +# CONFIG_USB_GSPCA_SUNPLUS is not set +# CONFIG_USB_GSPCA_T613 is not set +# CONFIG_USB_GSPCA_TV8532 is not set +# CONFIG_USB_GSPCA_VC032X is not set +# CONFIG_USB_GSPCA_ZC3XX is not set +# CONFIG_VIDEO_HDPVR is not set +# CONFIG_USB_VICAM is not set +# CONFIG_USB_IBMCAM is not set +# CONFIG_USB_KONICAWC is not set +# CONFIG_USB_QUICKCAM_MESSENGER is not set +# CONFIG_USB_ET61X251 is not set +# CONFIG_USB_OV511 is not set +# CONFIG_USB_SE401 is not set +# CONFIG_USB_SN9C102 is not set +# CONFIG_USB_STV680 is not set +# CONFIG_USB_ZC0301 is not set +# CONFIG_USB_PWC is not set +CONFIG_USB_PWC_INPUT_EVDEV=y +# CONFIG_USB_ZR364XX is not set +# CONFIG_USB_STKWEBCAM is not set +# CONFIG_USB_S2255 is not set +# CONFIG_RADIO_ADAPTERS is not set +# CONFIG_DAB is not set + +# +# Graphics support +# +CONFIG_VGA_ARB=y +# CONFIG_DRM is not set +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +CONFIG_FB=y +CONFIG_FIRMWARE_EDID=y +# CONFIG_FB_DDC is not set +CONFIG_FB_BOOT_VESA_SUPPORT=y +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y +# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set +# CONFIG_FB_SYS_FILLRECT is not set +# CONFIG_FB_SYS_COPYAREA is not set +# CONFIG_FB_SYS_IMAGEBLIT is not set +# CONFIG_FB_FOREIGN_ENDIAN is not set +# CONFIG_FB_SYS_FOPS is not set +# CONFIG_FB_SVGALIB is not set +# CONFIG_FB_MACMODES is not set +# CONFIG_FB_BACKLIGHT is not set +CONFIG_FB_MODE_HELPERS=y +CONFIG_FB_TILEBLITTING=y + +# +# Frame buffer hardware drivers +# +# CONFIG_FB_CIRRUS is not set +# CONFIG_FB_PM2 is not set +# CONFIG_FB_CYBER2000 is not set +# CONFIG_FB_ASILIANT is not set +# CONFIG_FB_IMSTT is not set +# CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_NVIDIA is not set +# CONFIG_FB_RIVA is not set +# CONFIG_FB_MATROX is not set +# CONFIG_FB_RADEON is not set +# CONFIG_FB_ATY128 is not set +# CONFIG_FB_ATY is not set +# CONFIG_FB_S3 is not set +# CONFIG_FB_SAVAGE is not set +CONFIG_FB_SIS=y +CONFIG_FB_SIS_300=y +CONFIG_FB_SIS_315=y +# CONFIG_FB_VIA is not set +# CONFIG_FB_NEOMAGIC is not set +# CONFIG_FB_KYRO is not set +# CONFIG_FB_3DFX is not set +# CONFIG_FB_VOODOO1 is not set +# CONFIG_FB_VT8623 is not set +# CONFIG_FB_TRIDENT is not set +# CONFIG_FB_ARK is not set +# CONFIG_FB_PM3 is not set +# CONFIG_FB_CARMINE is not set +# CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_METRONOME is not set +# CONFIG_FB_MB862XX is not set +# CONFIG_FB_BROADSHEET is not set +CONFIG_BACKLIGHT_LCD_SUPPORT=y +# CONFIG_LCD_CLASS_DEVICE is not set +CONFIG_BACKLIGHT_CLASS_DEVICE=y +CONFIG_BACKLIGHT_GENERIC=y + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +# CONFIG_MDA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE=y +# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set +CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y +# CONFIG_FONTS is not set +CONFIG_FONT_8x8=y +CONFIG_FONT_8x16=y +# CONFIG_LOGO is not set +CONFIG_SOUND=m +# CONFIG_SOUND_OSS_CORE is not set +CONFIG_SND=m +CONFIG_SND_TIMER=m +CONFIG_SND_PCM=m +# CONFIG_SND_SEQUENCER is not set +# CONFIG_SND_MIXER_OSS is not set +# CONFIG_SND_PCM_OSS is not set +# CONFIG_SND_HRTIMER is not set +# CONFIG_SND_RTCTIMER is not set +# CONFIG_SND_DYNAMIC_MINORS is not set +# CONFIG_SND_SUPPORT_OLD_API is not set +# CONFIG_SND_VERBOSE_PROCFS is not set +# CONFIG_SND_VERBOSE_PRINTK is not set +# CONFIG_SND_DEBUG is not set +CONFIG_SND_VMASTER=y +# CONFIG_SND_RAWMIDI_SEQ is not set +# CONFIG_SND_OPL3_LIB_SEQ is not set +# CONFIG_SND_OPL4_LIB_SEQ is not set +# CONFIG_SND_SBAWE_SEQ is not set +# CONFIG_SND_EMU10K1_SEQ is not set +CONFIG_SND_AC97_CODEC=m +# CONFIG_SND_DRIVERS is not set +CONFIG_SND_PCI=y +# CONFIG_SND_AD1889 is not set +# CONFIG_SND_ALS300 is not set +# CONFIG_SND_ALI5451 is not set +# CONFIG_SND_ATIIXP is not set +# CONFIG_SND_ATIIXP_MODEM is not set +# CONFIG_SND_AU8810 is not set +# CONFIG_SND_AU8820 is not set +# CONFIG_SND_AU8830 is not set +# CONFIG_SND_AW2 is not set +# CONFIG_SND_AZT3328 is not set +# CONFIG_SND_BT87X is not set +# CONFIG_SND_CA0106 is not set +# CONFIG_SND_CMIPCI is not set +# CONFIG_SND_OXYGEN is not set +# CONFIG_SND_CS4281 is not set +# CONFIG_SND_CS46XX is not set +CONFIG_SND_CS5535AUDIO=m +# CONFIG_SND_CTXFI is not set +# CONFIG_SND_DARLA20 is not set +# CONFIG_SND_GINA20 is not set +# CONFIG_SND_LAYLA20 is not set +# CONFIG_SND_DARLA24 is not set +# CONFIG_SND_GINA24 is not set +# CONFIG_SND_LAYLA24 is not set +# CONFIG_SND_MONA is not set +# CONFIG_SND_MIA is not set +# CONFIG_SND_ECHO3G is not set +# CONFIG_SND_INDIGO is not set +# CONFIG_SND_INDIGOIO is not set +# CONFIG_SND_INDIGODJ is not set +# CONFIG_SND_INDIGOIOX is not set +# CONFIG_SND_INDIGODJX is not set +# CONFIG_SND_EMU10K1 is not set +# CONFIG_SND_EMU10K1X is not set +# CONFIG_SND_ENS1370 is not set +# CONFIG_SND_ENS1371 is not set +# CONFIG_SND_ES1938 is not set +# CONFIG_SND_ES1968 is not set +# CONFIG_SND_FM801 is not set +# CONFIG_SND_HDA_INTEL is not set +# CONFIG_SND_HDSP is not set +# CONFIG_SND_HDSPM is not set +# CONFIG_SND_HIFIER is not set +# CONFIG_SND_ICE1712 is not set +# CONFIG_SND_ICE1724 is not set +# CONFIG_SND_INTEL8X0 is not set +# CONFIG_SND_INTEL8X0M is not set +# CONFIG_SND_KORG1212 is not set +# CONFIG_SND_LX6464ES is not set +# CONFIG_SND_MAESTRO3 is not set +# CONFIG_SND_MIXART is not set +# CONFIG_SND_NM256 is not set +# CONFIG_SND_PCXHR is not set +# CONFIG_SND_RIPTIDE is not set +# CONFIG_SND_RME32 is not set +# CONFIG_SND_RME96 is not set +# CONFIG_SND_RME9652 is not set +# CONFIG_SND_SONICVIBES is not set +# CONFIG_SND_TRIDENT is not set +# CONFIG_SND_VIA82XX is not set +# CONFIG_SND_VIA82XX_MODEM is not set +# CONFIG_SND_VIRTUOSO is not set +# CONFIG_SND_VX222 is not set +# CONFIG_SND_YMFPCI is not set +# CONFIG_SND_MIPS is not set +# CONFIG_SND_USB is not set +# CONFIG_SND_SOC is not set +# CONFIG_SOUND_PRIME is not set +CONFIG_AC97_BUS=m +CONFIG_HID_SUPPORT=y +CONFIG_HID=y +# CONFIG_HIDRAW is not set + +# +# USB Input Devices +# +CONFIG_USB_HID=y +# CONFIG_HID_PID is not set +CONFIG_USB_HIDDEV=y + +# +# Special HID drivers +# +# CONFIG_HID_A4TECH is not set +# CONFIG_HID_APPLE is not set +# CONFIG_HID_BELKIN is not set +# CONFIG_HID_CHERRY is not set +# CONFIG_HID_CHICONY is not set +# CONFIG_HID_CYPRESS is not set +# CONFIG_HID_DRAGONRISE is not set +# CONFIG_HID_EZKEY is not set +# CONFIG_HID_KYE is not set +# CONFIG_HID_GYRATION is not set +# CONFIG_HID_TWINHAN is not set +# CONFIG_HID_KENSINGTON is not set +# CONFIG_HID_LOGITECH is not set +# CONFIG_HID_MICROSOFT is not set +# CONFIG_HID_MONTEREY is not set +# CONFIG_HID_NTRIG is not set +# CONFIG_HID_PANTHERLORD is not set +# CONFIG_HID_PETALYNX is not set +# CONFIG_HID_SAMSUNG is not set +# CONFIG_HID_SONY is not set +# CONFIG_HID_SUNPLUS is not set +# CONFIG_HID_GREENASIA is not set +# CONFIG_HID_SMARTJOYPLUS is not set +# CONFIG_HID_TOPSEED is not set +# CONFIG_HID_THRUSTMASTER is not set +# CONFIG_HID_ZEROPLUS is not set +CONFIG_USB_SUPPORT=y +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y +CONFIG_USB_ARCH_HAS_EHCI=y +CONFIG_USB=y +# CONFIG_USB_DEBUG is not set +# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set + +# +# Miscellaneous USB options +# +CONFIG_USB_DEVICEFS=y +# CONFIG_USB_DEVICE_CLASS is not set +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_SUSPEND is not set +# CONFIG_USB_OTG is not set +# CONFIG_USB_OTG_WHITELIST is not set +# CONFIG_USB_OTG_BLACKLIST_HUB is not set +CONFIG_USB_MON=y +# CONFIG_USB_WUSB is not set +# CONFIG_USB_WUSB_CBAF is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_C67X00_HCD is not set +# CONFIG_USB_XHCI_HCD is not set +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y +# CONFIG_USB_EHCI_TT_NEWSCHED is not set +# CONFIG_USB_OXU210HP_HCD is not set +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_ISP1760_HCD is not set +# CONFIG_USB_ISP1362_HCD is not set +CONFIG_USB_OHCI_HCD=y +# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set +# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +# CONFIG_USB_UHCI_HCD is not set +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_WHCI_HCD is not set +# CONFIG_USB_HWA_HCD is not set + +# +# USB Device Class drivers +# +# CONFIG_USB_ACM is not set +# CONFIG_USB_PRINTER is not set +# CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may +# + +# +# also be needed; see USB_STORAGE Help for more info +# +CONFIG_USB_STORAGE=m +# CONFIG_USB_STORAGE_DEBUG is not set +CONFIG_USB_STORAGE_DATAFAB=m +CONFIG_USB_STORAGE_FREECOM=m +CONFIG_USB_STORAGE_ISD200=m +CONFIG_USB_STORAGE_USBAT=m +CONFIG_USB_STORAGE_SDDR09=m +CONFIG_USB_STORAGE_SDDR55=m +CONFIG_USB_STORAGE_JUMPSHOT=m +CONFIG_USB_STORAGE_ALAUDA=m +# CONFIG_USB_STORAGE_ONETOUCH is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set +# CONFIG_USB_LIBUSUAL is not set + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set + +# +# USB port drivers +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_BERRY_CHARGE is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_SISUSBVGA is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_TEST is not set +# CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_VST is not set +# CONFIG_USB_GADGET is not set + +# +# OTG and related infrastructure +# +# CONFIG_NOP_USB_XCEIV is not set +# CONFIG_UWB is not set +# CONFIG_MMC is not set +# CONFIG_MEMSTICK is not set +# CONFIG_NEW_LEDS is not set +# CONFIG_ACCESSIBILITY is not set +# CONFIG_INFINIBAND is not set +# CONFIG_RTC_CLASS is not set +# CONFIG_DMADEVICES is not set +# CONFIG_AUXDISPLAY is not set +# CONFIG_UIO is not set + +# +# TI VLYNQ +# +# CONFIG_STAGING is not set + +# +# File systems +# +# CONFIG_EXT2_FS is not set +CONFIG_EXT3_FS=y +# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set +CONFIG_EXT3_FS_XATTR=y +CONFIG_EXT3_FS_POSIX_ACL=y +CONFIG_EXT3_FS_SECURITY=y +# CONFIG_EXT4_FS is not set +CONFIG_JBD=y +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +CONFIG_FS_POSIX_ACL=y +# CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_BTRFS_FS is not set +# CONFIG_NILFS2_FS is not set +CONFIG_FILE_LOCKING=y +CONFIG_FSNOTIFY=y +CONFIG_DNOTIFY=y +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +CONFIG_QUOTA=y +# CONFIG_QUOTA_NETLINK_INTERFACE is not set +# CONFIG_PRINT_QUOTA_WARNING is not set +# CONFIG_QFMT_V1 is not set +# CONFIG_QFMT_V2 is not set +CONFIG_QUOTACTL=y +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# Caches +# +# CONFIG_FSCACHE is not set + +# +# CD-ROM/DVD Filesystems +# +CONFIG_ISO9660_FS=m +CONFIG_JOLIET=y +CONFIG_ZISOFS=y +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=m +# CONFIG_MSDOS_FS is not set +CONFIG_VFAT_FS=m +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_KCORE=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set +# CONFIG_MISC_FILESYSTEMS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=m +CONFIG_NFS_V3=y +CONFIG_NFS_V3_ACL=y +# CONFIG_NFS_V4 is not set +# CONFIG_NFSD is not set +CONFIG_LOCKD=m +CONFIG_LOCKD_V4=y +CONFIG_NFS_ACL_SUPPORT=m +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=m +# CONFIG_RPCSEC_GSS_KRB5 is not set +# CONFIG_RPCSEC_GSS_SPKM3 is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="utf-8" +# CONFIG_NLS_CODEPAGE_437 is not set +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set +# CONFIG_NLS_ISO8859_1 is not set +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_UTF8 is not set +# CONFIG_DLM is not set + +# +# Kernel hacking +# +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +CONFIG_MAGIC_SYSRQ=y +# CONFIG_STRIP_ASM_SYMS is not set +CONFIG_UNUSED_SYMBOLS=y +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_KERNEL is not set +# CONFIG_SLUB_DEBUG_ON is not set +# CONFIG_SLUB_STATS is not set +# CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +CONFIG_SYSCTL_SYSCALL_CHECK=y +CONFIG_TRACING_SUPPORT=y +# CONFIG_FTRACE is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +CONFIG_CMDLINE="" + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +# CONFIG_SECURITY_FILE_CAPABILITIES is not set +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_BLKCIPHER2=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_PCOMP=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +# CONFIG_CRYPTO_GF128MUL is not set +# CONFIG_CRYPTO_NULL is not set +CONFIG_CRYPTO_WORKQUEUE=y +# CONFIG_CRYPTO_CRYPTD is not set +# CONFIG_CRYPTO_AUTHENC is not set +# CONFIG_CRYPTO_TEST is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_SEQIV is not set + +# +# Block modes +# +CONFIG_CRYPTO_CBC=y +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +# CONFIG_CRYPTO_ECB is not set +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# +# CONFIG_CRYPTO_HMAC is not set +# CONFIG_CRYPTO_XCBC is not set +# CONFIG_CRYPTO_VMAC is not set + +# +# Digest +# +# CONFIG_CRYPTO_CRC32C is not set +# CONFIG_CRYPTO_GHASH is not set +# CONFIG_CRYPTO_MD4 is not set +# CONFIG_CRYPTO_MD5 is not set +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +# CONFIG_CRYPTO_SHA1 is not set +# CONFIG_CRYPTO_SHA256 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +# CONFIG_CRYPTO_AES is not set +# CONFIG_CRYPTO_ANUBIS is not set +# CONFIG_CRYPTO_ARC4 is not set +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +# CONFIG_CRYPTO_DES is not set +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TWOFISH is not set + +# +# Compression +# +# CONFIG_CRYPTO_DEFLATE is not set +# CONFIG_CRYPTO_ZLIB is not set +# CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set +# CONFIG_CRYPTO_HW is not set +# CONFIG_BINARY_PRINTF is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_GENERIC_FIND_LAST_BIT=y +# CONFIG_CRC_CCITT is not set +# CONFIG_CRC16 is not set +# CONFIG_CRC_T10DIF is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +CONFIG_AUDIT_GENERIC=y +CONFIG_ZLIB_INFLATE=m +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y +CONFIG_NLATTR=y -- 1.6.2.1 From ralf@linux-mips.org Wed Nov 4 10:42:44 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 04 Nov 2009 10:42:46 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:59618 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-FAIL) by ftp.linux-mips.org with ESMTP id S1492008AbZKDJmo (ORCPT ); Wed, 4 Nov 2009 10:42:44 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id nA49i8SO009149; Wed, 4 Nov 2009 10:44:09 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id nA49i7RT009147; Wed, 4 Nov 2009 10:44:07 +0100 Date: Wed, 4 Nov 2009 10:44:07 +0100 From: Ralf Baechle To: Yoichi Yuasa Cc: linux-mips@linux-mips.org Subject: Re: [PATCH][MIPS] add DMA declare coherent memory support Message-ID: <20091104094407.GA32639@linux-mips.org> References: <20091104164104.9fc315af.yuasa@linux-mips.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20091104164104.9fc315af.yuasa@linux-mips.org> User-Agent: Mutt/1.5.19 (2009-01-05) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24665 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Wed, Nov 04, 2009 at 04:41:04PM +0900, Yoichi Yuasa wrote: > ohci-sm501 driver require dma_declare_coherent_memory(). > It is used to driver's local memory allocation with dma_alloc_coherent(). > > This patch works without problem on TANBAC TB0287(VR4131 + SM501). I already had a modified version of this patch queued up for 2.6.33. I'll move that patch into the main tree and change the comment to make it clear that this is a required fix. Thanks, Ralf From arnaud.patard@mandriva.com Wed Nov 4 11:28:48 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 04 Nov 2009 11:28:54 +0100 (CET) Received: from mx1.moondrake.net ([212.85.150.166]:46332 "EHLO mx1.mandriva.com" rhost-flags-OK-OK-OK-FAIL) by ftp.linux-mips.org with ESMTP id S1492986AbZKDK2s (ORCPT ); Wed, 4 Nov 2009 11:28:48 +0100 Received: by mx1.mandriva.com (Postfix, from userid 501) id ED3E3274004; Wed, 4 Nov 2009 11:28:46 +0100 (CET) Received: from office-abk.mandriva.com (unknown [195.7.104.248]) (using TLSv1 with cipher ADH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.mandriva.com (Postfix) with ESMTP id E25E6274007; Wed, 4 Nov 2009 11:28:45 +0100 (CET) Received: from anduin.mandriva.com (fw2.mandriva.com [192.168.2.3]) by office-abk.mandriva.com (Postfix) with ESMTP id 3CFC582919; Wed, 4 Nov 2009 11:40:13 +0100 (CET) Received: from anduin.mandriva.com (localhost [127.0.0.1]) by anduin.mandriva.com (Postfix) with ESMTP id 88E28FF855; Wed, 4 Nov 2009 11:28:59 +0100 (CET) From: Arnaud Patard To: Wu Zhangjin Cc: Ralf Baechle , linux-mips@linux-mips.org, LKML , huhb@lemote.com, yanh@lemote.com, Zhang Le , Thomas Gleixner , Nicholas Mc Guire , zhangfx@lemote.com, liujl@lemote.com Subject: Re: [PATCH -queue v0 1/6] [loongson] add basic loongson-2f support References: Organization: Mandriva Date: Wed, 04 Nov 2009 11:28:59 +0100 In-Reply-To: (Wu Zhangjin's message of "Wed, 4 Nov 2009 17:04:47 +0800") Message-ID: User-Agent: Gnus/5.1008 (Gnus v5.10.8) Emacs/22.1 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24666 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: apatard@mandriva.com Precedence: bulk X-list: linux-mips Hi, Wu Zhangjin writes: > Loongson2F has built-in DDR2 and PCIX controller. The PCIX controller > have a similar programming interface with FPGA northbridge used in > Loongson2E. > > The main differences between loongson-2e and loongson-2f include: > > 1. loongson-2f has an extra address windows configuration module, which > can be used to map CPU address space to DDR or PCI address space, or map > the PCI-DMA address space to DDR or LIO address space. > > 2. loongson-2f support 8 levels of software configurable cpu frequency, > which can be configured via a register(LOONGSON_CHIPCFG0). the coming > cpufreq and standby support are based on this feature. > > herein, the module and the corresponding operations are abstracted to > loongson.h. > > besides, the other loongson2f-specific source code are added here, > including gcc 4.4 support, pci memory space, pci io space, dma address. > > Signed-off-by: Wu Zhangjin > --- > arch/mips/Kconfig | 18 ++++ > arch/mips/Makefile | 2 + > .../mips/include/asm/mach-loongson/dma-coherence.h | 4 + > arch/mips/include/asm/mach-loongson/loongson.h | 84 +++++++++++++++++++- > arch/mips/include/asm/mach-loongson/mem.h | 25 ++++-- > arch/mips/include/asm/mach-loongson/pci.h | 28 ++++++- > arch/mips/loongson/common/bonito-irq.c | 5 + > arch/mips/loongson/common/init.c | 18 ++++ > arch/mips/loongson/common/mem.c | 17 ++++ > arch/mips/loongson/common/pci.c | 8 ++ > 10 files changed, 199 insertions(+), 10 deletions(-) > > diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig > index ae9fa98..8417357 100644 > --- a/arch/mips/Kconfig > +++ b/arch/mips/Kconfig > @@ -1059,6 +1059,21 @@ config CPU_LOONGSON2E > The Loongson 2E processor implements the MIPS III instruction set > with many extensions. > > + It has an internal FPGA northbridge, which is compatiable to > + bonito64. > + > +config CPU_LOONGSON2F > + bool "Loongson 2F" > + depends on SYS_HAS_CPU_LOONGSON2F > + select CPU_LOONGSON2 > + help > + The Loongson 2F processor implements the MIPS III instruction set > + with many extensions. > + > + Loongson2F have built-in DDR2 and PCIX controller. The PCIX controller > + have a similar programming interface with FPGA northbridge used in > + Loongson2E. > + Small question : Why don't you restrict to 64bit kernels only ? From what I remember from some discussions with ST, trying to use a 32-bit kernel on 2f is a nice way to get troubles. It would be better imho to forbid such a configuration. As a side effect, this will remove all 'defined(CONFIG_64BIT)' parts of your #ifdef tests. Arnaud From arnaud.patard@mandriva.com Wed Nov 4 11:40:26 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 04 Nov 2009 11:40:32 +0100 (CET) Received: from mx1.moondrake.net ([212.85.150.166]:56408 "EHLO mx1.mandriva.com" rhost-flags-OK-OK-OK-FAIL) by ftp.linux-mips.org with ESMTP id S1493064AbZKDKk0 (ORCPT ); Wed, 4 Nov 2009 11:40:26 +0100 Received: by mx1.mandriva.com (Postfix, from userid 501) id 6112C274003; Wed, 4 Nov 2009 11:40:25 +0100 (CET) Received: from office-abk.mandriva.com (unknown [195.7.104.248]) (using TLSv1 with cipher ADH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.mandriva.com (Postfix) with ESMTP id 5A2C1274002; Wed, 4 Nov 2009 11:40:24 +0100 (CET) Received: from anduin.mandriva.com (fw2.mandriva.com [192.168.2.3]) by office-abk.mandriva.com (Postfix) with ESMTP id AF40382919; Wed, 4 Nov 2009 11:51:51 +0100 (CET) Received: from anduin.mandriva.com (localhost [127.0.0.1]) by anduin.mandriva.com (Postfix) with ESMTP id 744A0FF855; Wed, 4 Nov 2009 11:40:38 +0100 (CET) From: Arnaud Patard To: Wu Zhangjin Cc: Ralf Baechle , linux-mips@linux-mips.org, LKML , huhb@lemote.com, yanh@lemote.com, Zhang Le , Thomas Gleixner , Nicholas Mc Guire , zhangfx@lemote.com, liujl@lemote.com Subject: Re: [PATCH -queue v0 5/6] [loongson] rtc: enable legacy RTC driver on fuloong2f References: Organization: Mandriva Date: Wed, 04 Nov 2009 11:40:38 +0100 In-Reply-To: (Wu Zhangjin's message of "Wed, 4 Nov 2009 17:06:07 +0800") Message-ID: User-Agent: Gnus/5.1008 (Gnus v5.10.8) Emacs/22.1 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24667 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: apatard@mandriva.com Precedence: bulk X-list: linux-mips Wu Zhangjin writes: Hi, > RTC_LIB is selected by MIPS by default, and therefore, the legacy RTC driver is > disabled. but fortunately, RTC_LIB not works on fulong, so, enabling the legcy > RTC driver is needed, otherwise, the tools like hwclock will not work. > > because loongson family machines, including fuloong2e, fuloong2f and > yeeloong2f need to enable legacy RTC driver, so we use MACH_LOONGSON > here. There are loongson machines which are working fine with RTC_LIB (for instance the gdium which is using a m41t83 on i2c) so would be better to be more restrictive imho. Arnaud From wuzhangjin@gmail.com Wed Nov 4 12:04:21 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 04 Nov 2009 12:04:27 +0100 (CET) Received: from mail-pw0-f45.google.com ([209.85.160.45]:45979 "EHLO mail-pw0-f45.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1493132AbZKDLEV (ORCPT ); Wed, 4 Nov 2009 12:04:21 +0100 Received: by pwi11 with SMTP id 11so3205185pwi.24 for ; Wed, 04 Nov 2009 03:04:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:subject:from:reply-to:to:cc :in-reply-to:references:content-type:organization:date:message-id :mime-version:x-mailer:content-transfer-encoding; bh=3pF2SYNc2XCYGPbbl3QnmY0Kh75LZTXK79YZXqTwhWI=; b=tiCFrE7iA2LwfA0ppuNoyGBf2OlFPTBDPHwDlhMS3OVT+tAecoMD31LdYap2a2pgwR pQszf+3gd+eWAQ65J0nJ+mvcxT0qg9RlvSmIBe6qaY4XZBrOdlE1EO+5uwUy404kdL4y g23so0pWTKIsHTGv0HtPiugpHVePbpCgsRY+I= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=subject:from:reply-to:to:cc:in-reply-to:references:content-type :organization:date:message-id:mime-version:x-mailer :content-transfer-encoding; b=qBsbPrOb+PU2iq/3I8GFPP7bBADL3liZzT3E8wp6ofilvMdYUAeGWy7+OnK/uDrr2X eSfRj2EqG8/EjEMrbGNhMtczMbHFDev/ikYcs15NMrcGgBHA9C18BaTq/HFye3dFrhnL qGjlcauvC+d1/TmNkNN+0uFvmzZJquP/+O4iE= Received: by 10.114.252.2 with SMTP id z2mr1759892wah.156.1257332652369; Wed, 04 Nov 2009 03:04:12 -0800 (PST) Received: from ?172.16.2.101? ([222.92.8.142]) by mx.google.com with ESMTPS id 22sm554436pzk.2.2009.11.04.03.04.06 (version=TLSv1/SSLv3 cipher=RC4-MD5); Wed, 04 Nov 2009 03:04:11 -0800 (PST) Subject: Re: [PATCH -queue v0 1/6] [loongson] add basic loongson-2f support From: Wu Zhangjin Reply-To: wuzhangjin@gmail.com To: Arnaud Patard Cc: Ralf Baechle , linux-mips@linux-mips.org, LKML , huhb@lemote.com, yanh@lemote.com, Zhang Le , Thomas Gleixner , Nicholas Mc Guire , zhangfx@lemote.com, liujl@lemote.com In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Organization: DSLab, Lanzhou University, China Date: Wed, 04 Nov 2009 19:04:12 +0800 Message-ID: <1257332652.8716.5.camel@falcon.domain.org> Mime-Version: 1.0 X-Mailer: Evolution 2.28.1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24668 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips Hi, On Wed, 2009-11-04 at 11:28 +0100, Arnaud Patard wrote: [...] > > + > > +config CPU_LOONGSON2F > > + bool "Loongson 2F" > > + depends on SYS_HAS_CPU_LOONGSON2F > > + select CPU_LOONGSON2 > > + help > > + The Loongson 2F processor implements the MIPS III instruction set > > + with many extensions. > > + > > + Loongson2F have built-in DDR2 and PCIX controller. The PCIX controller > > + have a similar programming interface with FPGA northbridge used in > > + Loongson2E. > > + > > Small question : Why don't you restrict to 64bit kernels only ? From > what I remember from some discussions with ST, trying to use a 32-bit > kernel on 2f is a nice way to get troubles. It would be better imho to > forbid such a configuration. As a side effect, this will remove all > 'defined(CONFIG_64BIT)' parts of your #ifdef tests. > It's hard to make such a decision ;) Perhaps some guys want to play with the 32bit version. Regards, Wu Zhangjin From ralf@linux-mips.org Wed Nov 4 12:18:43 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 04 Nov 2009 12:18:45 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:57714 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-FAIL) by ftp.linux-mips.org with ESMTP id S1493207AbZKDLSm (ORCPT ); Wed, 4 Nov 2009 12:18:42 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id nA4BK3mo013729; Wed, 4 Nov 2009 12:20:04 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id nA4BJvWw013727; Wed, 4 Nov 2009 12:19:57 +0100 Date: Wed, 4 Nov 2009 12:19:57 +0100 From: Ralf Baechle To: Wu Zhangjin Cc: Arnaud Patard , linux-mips@linux-mips.org, LKML , huhb@lemote.com, yanh@lemote.com, Zhang Le , Thomas Gleixner , Nicholas Mc Guire , zhangfx@lemote.com, liujl@lemote.com Subject: Re: [PATCH -queue v0 1/6] [loongson] add basic loongson-2f support Message-ID: <20091104111957.GA13549@linux-mips.org> References: <1257332652.8716.5.camel@falcon.domain.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1257332652.8716.5.camel@falcon.domain.org> User-Agent: Mutt/1.5.19 (2009-01-05) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24669 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Wed, Nov 04, 2009 at 07:04:12PM +0800, Wu Zhangjin wrote: > > Small question : Why don't you restrict to 64bit kernels only ? From > > what I remember from some discussions with ST, trying to use a 32-bit > > kernel on 2f is a nice way to get troubles. It would be better imho to > > forbid such a configuration. As a side effect, this will remove all > > 'defined(CONFIG_64BIT)' parts of your #ifdef tests. > > > > It's hard to make such a decision ;) Perhaps some guys want to play with > the 32bit version. We have other systems where 32-bit kernel support is just remarkably ugly. We've dropped 32-bit support for the SGI IP32 aka O2 - nobody seems to even have really noticed that. The Sibyte systems would be good candidates to do the same as accesses to outside the 32-bit address space are needed very frequently. Ralf From wuzhangjin@gmail.com Wed Nov 4 12:19:04 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 04 Nov 2009 12:19:13 +0100 (CET) Received: from mail-pz0-f194.google.com ([209.85.222.194]:47341 "EHLO mail-pz0-f194.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1493188AbZKDLSy (ORCPT ); Wed, 4 Nov 2009 12:18:54 +0100 Received: by pzk32 with SMTP id 32so4765113pzk.21 for ; Wed, 04 Nov 2009 03:18:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:subject:from:reply-to:to:cc :in-reply-to:references:content-type:organization:date:message-id :mime-version:x-mailer:content-transfer-encoding; bh=vwy46/FFG5kpl3mowxK/0JajC/VrcqsMriAeYxEm0n4=; b=Mf/dS60nzsmx064e0rDIGnlw/WBaGrpikN22kubwccFu+W2VGwA1F4gSA/szxPex6f kjTFkBCy2l6RhwJ7UJUv/dz8BX0e2351pdbi6OBBLUlVJ3JX7W/65E3u+sAezerj/SJU to/mXfa2vknM+mx7VDyPyXPwqC5hNO8n3rokc= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=subject:from:reply-to:to:cc:in-reply-to:references:content-type :organization:date:message-id:mime-version:x-mailer :content-transfer-encoding; b=bWkwf5R9qWDLJZJZME5btonNRxjMnSGTUxnPhlq/EOfwuP/jW+TGk5CtbUfps9cj3G H9U23Q2ui0YwaqZPyeOuMgRsmzkf3FVSiOUv5xMT9TzF5yKiouTuV/zfXJpbS/39PZ8y lYS5UKObIKwNTCP9quNS+dewke05PQNHMfo24= Received: by 10.115.87.7 with SMTP id p7mr1770986wal.161.1257333527364; Wed, 04 Nov 2009 03:18:47 -0800 (PST) Received: from ?172.16.2.101? ([222.92.8.142]) by mx.google.com with ESMTPS id 20sm567828pxi.7.2009.11.04.03.18.40 (version=TLSv1/SSLv3 cipher=RC4-MD5); Wed, 04 Nov 2009 03:18:46 -0800 (PST) Subject: Re: [PATCH -queue v0 5/6] [loongson] rtc: enable legacy RTC driver on fuloong2f From: Wu Zhangjin Reply-To: wuzhangjin@gmail.com To: Arnaud Patard Cc: Ralf Baechle , linux-mips@linux-mips.org, LKML , huhb@lemote.com, yanh@lemote.com, Zhang Le , Thomas Gleixner , Nicholas Mc Guire , zhangfx@lemote.com, liujl@lemote.com In-Reply-To: References: Content-Type: text/plain; charset="UTF-8" Organization: DSLab, Lanzhou University, China Date: Wed, 04 Nov 2009 19:18:47 +0800 Message-ID: <1257333527.8716.20.camel@falcon.domain.org> Mime-Version: 1.0 X-Mailer: Evolution 2.28.1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24670 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips Hi, On Wed, 2009-11-04 at 11:40 +0100, Arnaud Patard wrote: > Wu Zhangjin writes: > > Hi, > > > RTC_LIB is selected by MIPS by default, and therefore, the legacy RTC driver is > > disabled. but unfortunately, RTC_LIB not works on fulong, so, enabling the legcy > > RTC driver is needed, otherwise, the tools like hwclock will not work. > > > > because loongson family machines, including fuloong2e, fuloong2f and > > yeeloong2f need to enable legacy RTC driver, so we use MACH_LOONGSON > > here. > > There are loongson machines which are working fine with RTC_LIB (for > instance the gdium which is using a m41t83 on i2c) so would be better to > be more restrictive imho. In reality, fuloong2e, fuloong2f and yeeloong2f work fine with RTC_LIB, but relative patches need to append to drivers/rtc/rtc-cmos.c and also need a RTC platform device. If what I remembered is right, Gdium also need corresponding patches to make it work with RTC_LIB. Herein, I just let the basic support for those machines work, and then, the RTC_LIB support will be sent out later. and a small question: if legacy RTC driver works well on these machines, why should we forbid people to use it? I think it's better to remove the "select RTC_LIB" line for MIPS, and then, the people will be free to choose what they want, and even for the users whose platform not support RTC_LIB. Regards, Wu Zhangjin From arnaud.patard@mandriva.com Wed Nov 4 12:34:32 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 04 Nov 2009 12:34:38 +0100 (CET) Received: from mx1.moondrake.net ([212.85.150.166]:37344 "EHLO mx1.mandriva.com" rhost-flags-OK-OK-OK-FAIL) by ftp.linux-mips.org with ESMTP id S1493074AbZKDLec (ORCPT ); Wed, 4 Nov 2009 12:34:32 +0100 Received: by mx1.mandriva.com (Postfix, from userid 501) id 1D807274004; Wed, 4 Nov 2009 12:34:31 +0100 (CET) Received: from office-abk.mandriva.com (unknown [195.7.104.248]) (using TLSv1 with cipher ADH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.mandriva.com (Postfix) with ESMTP id 094F0274003; Wed, 4 Nov 2009 12:34:30 +0100 (CET) Received: from anduin.mandriva.com (fw2.mandriva.com [192.168.2.3]) by office-abk.mandriva.com (Postfix) with ESMTP id A19F482919; Wed, 4 Nov 2009 12:45:57 +0100 (CET) Received: from anduin.mandriva.com (localhost [127.0.0.1]) by anduin.mandriva.com (Postfix) with ESMTP id 7601BFF855; Wed, 4 Nov 2009 12:34:44 +0100 (CET) From: Arnaud Patard To: wuzhangjin@gmail.com Cc: Ralf Baechle , linux-mips@linux-mips.org, LKML , huhb@lemote.com, yanh@lemote.com, Zhang Le , Thomas Gleixner , Nicholas Mc Guire , zhangfx@lemote.com, liujl@lemote.com Subject: Re: [PATCH -queue v0 5/6] [loongson] rtc: enable legacy RTC driver on fuloong2f References: <1257333527.8716.20.camel@falcon.domain.org> Organization: Mandriva Date: Wed, 04 Nov 2009 12:34:44 +0100 In-Reply-To: <1257333527.8716.20.camel@falcon.domain.org> (Wu Zhangjin's message of "Wed, 04 Nov 2009 19:18:47 +0800") Message-ID: User-Agent: Gnus/5.1008 (Gnus v5.10.8) Emacs/22.1 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24671 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: apatard@mandriva.com Precedence: bulk X-list: linux-mips Wu Zhangjin writes: > Hi, > > On Wed, 2009-11-04 at 11:40 +0100, Arnaud Patard wrote: >> Wu Zhangjin writes: >> >> Hi, >> >> > RTC_LIB is selected by MIPS by default, and therefore, the legacy RTC driver is >> > disabled. but unfortunately, RTC_LIB not works on fulong, so, enabling the legcy >> > RTC driver is needed, otherwise, the tools like hwclock will not work. >> > >> > because loongson family machines, including fuloong2e, fuloong2f and >> > yeeloong2f need to enable legacy RTC driver, so we use MACH_LOONGSON >> > here. >> >> There are loongson machines which are working fine with RTC_LIB (for >> instance the gdium which is using a m41t83 on i2c) so would be better to >> be more restrictive imho. > > In reality, fuloong2e, fuloong2f and yeeloong2f work fine with RTC_LIB, > but relative patches need to append to drivers/rtc/rtc-cmos.c and also > need a RTC platform device. If what I remembered is right, Gdium also > need corresponding patches to make it work with RTC_LIB. As I said, Gdium is using an i2c chip and the bus is made with the sm501 gpio. So except the patch for gpiolib support for ls2f, there's nothing special for RTC_LIB. It's just working out of the box (as long as you declare the platform devices but that's not what I call a problem). > > Herein, I just let the basic support for those machines work, and then, > the RTC_LIB support will be sent out later. > > and a small question: if legacy RTC driver works well on these machines, > why should we forbid people to use it? I think it's better to remove the > "select RTC_LIB" line for MIPS, and then, the people will be free to > choose what they want, and even for the users whose platform not support > RTC_LIB. Well, I though about this. If you go that way and remove the "select RTC_LIB", please check and enable it for all platforms which needs it or warn people about. Would be nice to avoid regression due to that. Arnaud From arnaud.patard@mandriva.com Wed Nov 4 12:36:14 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 04 Nov 2009 12:36:20 +0100 (CET) Received: from mx1.moondrake.net ([212.85.150.166]:37399 "EHLO mx1.mandriva.com" rhost-flags-OK-OK-OK-FAIL) by ftp.linux-mips.org with ESMTP id S1493191AbZKDLgL (ORCPT ); Wed, 4 Nov 2009 12:36:11 +0100 Received: by mx1.mandriva.com (Postfix, from userid 501) id A5709274004; Wed, 4 Nov 2009 12:36:10 +0100 (CET) Received: from office-abk.mandriva.com (unknown [195.7.104.248]) (using TLSv1 with cipher ADH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.mandriva.com (Postfix) with ESMTP id 1C119274003; Wed, 4 Nov 2009 12:36:09 +0100 (CET) Received: from anduin.mandriva.com (fw2.mandriva.com [192.168.2.3]) by office-abk.mandriva.com (Postfix) with ESMTP id AFAE382919; Wed, 4 Nov 2009 12:47:36 +0100 (CET) Received: from anduin.mandriva.com (localhost [127.0.0.1]) by anduin.mandriva.com (Postfix) with ESMTP id B5170FF855; Wed, 4 Nov 2009 12:36:23 +0100 (CET) From: Arnaud Patard To: wuzhangjin@gmail.com Cc: Ralf Baechle , linux-mips@linux-mips.org, LKML , huhb@lemote.com, yanh@lemote.com, Zhang Le , Thomas Gleixner , Nicholas Mc Guire , zhangfx@lemote.com, liujl@lemote.com Subject: Re: [PATCH -queue v0 1/6] [loongson] add basic loongson-2f support References: <1257332652.8716.5.camel@falcon.domain.org> Organization: Mandriva Date: Wed, 04 Nov 2009 12:36:23 +0100 In-Reply-To: <1257332652.8716.5.camel@falcon.domain.org> (Wu Zhangjin's message of "Wed, 04 Nov 2009 19:04:12 +0800") Message-ID: User-Agent: Gnus/5.1008 (Gnus v5.10.8) Emacs/22.1 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24672 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: apatard@mandriva.com Precedence: bulk X-list: linux-mips Wu Zhangjin writes: > Hi, > > On Wed, 2009-11-04 at 11:28 +0100, Arnaud Patard wrote: > [...] >> > + >> > +config CPU_LOONGSON2F >> > + bool "Loongson 2F" >> > + depends on SYS_HAS_CPU_LOONGSON2F >> > + select CPU_LOONGSON2 >> > + help >> > + The Loongson 2F processor implements the MIPS III instruction set >> > + with many extensions. >> > + >> > + Loongson2F have built-in DDR2 and PCIX controller. The PCIX controller >> > + have a similar programming interface with FPGA northbridge used in >> > + Loongson2E. >> > + >> >> Small question : Why don't you restrict to 64bit kernels only ? From >> what I remember from some discussions with ST, trying to use a 32-bit >> kernel on 2f is a nice way to get troubles. It would be better imho to >> forbid such a configuration. As a side effect, this will remove all >> 'defined(CONFIG_64BIT)' parts of your #ifdef tests. >> > > It's hard to make such a decision ;) Perhaps some guys want to play with > the 32bit version. It's a matter of taste : using 32 bit and getting an more or less broken machine or using 64bit and getting a working machine. I don't think a lot of people will choose the first option :) Arnaud From mbizon@freebox.fr Wed Nov 4 14:11:29 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 04 Nov 2009 14:11:35 +0100 (CET) Received: from smtp6-g21.free.fr ([212.27.42.6]:60448 "EHLO smtp6-g21.free.fr" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1493264AbZKDNL3 (ORCPT ); Wed, 4 Nov 2009 14:11:29 +0100 Received: from smtp6-g21.free.fr (localhost [127.0.0.1]) by smtp6-g21.free.fr (Postfix) with ESMTP id 4F159E081EC; Wed, 4 Nov 2009 14:11:20 +0100 (CET) Received: from [213.228.1.107] (sakura.staff.proxad.net [213.228.1.107]) by smtp6-g21.free.fr (Postfix) with ESMTP id 387D5E0811D; Wed, 4 Nov 2009 14:11:17 +0100 (CET) Subject: [PATCH] MIPS: BCM63xx: Fix serial driver compile breakage. From: Maxime Bizon Reply-To: mbizon@freebox.fr To: Ralf Baechle Cc: linux-mips@linux-mips.org Content-Type: text/plain; charset="ANSI_X3.4-1968" Organization: Freebox Date: Wed, 04 Nov 2009 14:11:15 +0100 Message-ID: <1257340275.2926.7.camel@sakura.staff.proxad.net> Mime-Version: 1.0 X-Mailer: Evolution 2.28.1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24673 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mbizon@freebox.fr Precedence: bulk X-list: linux-mips Hi Ralf, bcm63xx does not compile on current linus' tree, could you please apply the attached patch and send it to linus ? Thanks ! The driver missed a small API change while sitting in Ralf's tree, this patch makes it compile again. Signed-off-by: Maxime Bizon --- drivers/serial/bcm63xx_uart.c | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/serial/bcm63xx_uart.c b/drivers/serial/bcm63xx_uart.c index beddaa6..37ad0c4 100644 --- a/drivers/serial/bcm63xx_uart.c +++ b/drivers/serial/bcm63xx_uart.c @@ -242,7 +242,7 @@ static void bcm_uart_do_rx(struct uart_port *port) * higher than fifo size anyway since we're much faster than * serial port */ max_count = 32; - tty = port->info->port.tty; + tty = port->state->port.tty; do { unsigned int iestat, c, cstat; char flag; @@ -318,7 +318,7 @@ static void bcm_uart_do_tx(struct uart_port *port) return; } - xmit = &port->info->xmit; + xmit = &port->state->xmit; if (uart_circ_empty(xmit)) goto txq_empty; -- 1.6.3.3 -- Maxime From ralf@linux-mips.org Wed Nov 4 14:48:52 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 04 Nov 2009 14:48:54 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:44313 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-FAIL) by ftp.linux-mips.org with ESMTP id S1493272AbZKDNsv (ORCPT ); Wed, 4 Nov 2009 14:48:51 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id nA4DoI0t017455; Wed, 4 Nov 2009 14:50:18 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id nA4DoHUd017453; Wed, 4 Nov 2009 14:50:17 +0100 Date: Wed, 4 Nov 2009 14:50:17 +0100 From: Ralf Baechle To: Maxime Bizon Cc: linux-mips@linux-mips.org Subject: Re: [PATCH] MIPS: BCM63xx: Fix serial driver compile breakage. Message-ID: <20091104135017.GA15430@linux-mips.org> References: <1257340275.2926.7.camel@sakura.staff.proxad.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1257340275.2926.7.camel@sakura.staff.proxad.net> User-Agent: Mutt/1.5.19 (2009-01-05) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24674 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Wed, Nov 04, 2009 at 02:11:15PM +0100, Maxime Bizon wrote: > To: Ralf Baechle > Cc: linux-mips@linux-mips.org > bcm63xx does not compile on current linus' tree, could you please apply > the attached patch and send it to linus ? Thanks ! Will do - but (rant starts here) please remember to cc the respective mailing lists and and maintainers for drivers in the future. Ralf From ralf@linux-mips.org Wed Nov 4 15:14:26 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 04 Nov 2009 15:14:29 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:40322 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-FAIL) by ftp.linux-mips.org with ESMTP id S1493284AbZKDOO0 (ORCPT ); Wed, 4 Nov 2009 15:14:26 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id nA4EFnck018886; Wed, 4 Nov 2009 15:15:49 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id nA4EFjxM018884; Wed, 4 Nov 2009 15:15:45 +0100 Date: Wed, 4 Nov 2009 15:15:45 +0100 From: Ralf Baechle To: Wu Zhangjin Cc: Arnaud Patard , linux-mips@linux-mips.org, LKML , huhb@lemote.com, yanh@lemote.com, Zhang Le , Thomas Gleixner , Nicholas Mc Guire , zhangfx@lemote.com, liujl@lemote.com Subject: Re: [PATCH -queue v0 5/6] [loongson] rtc: enable legacy RTC driver on fuloong2f Message-ID: <20091104141545.GA18408@linux-mips.org> References: <1257333527.8716.20.camel@falcon.domain.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1257333527.8716.20.camel@falcon.domain.org> User-Agent: Mutt/1.5.19 (2009-01-05) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24675 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Wed, Nov 04, 2009 at 07:18:47PM +0800, Wu Zhangjin wrote: > In reality, fuloong2e, fuloong2f and yeeloong2f work fine with RTC_LIB, > but relative patches need to append to drivers/rtc/rtc-cmos.c and also > need a RTC platform device. If what I remembered is right, Gdium also > need corresponding patches to make it work with RTC_LIB. > > Herein, I just let the basic support for those machines work, and then, > the RTC_LIB support will be sent out later. > > and a small question: if legacy RTC driver works well on these machines, > why should we forbid people to use it? I think it's better to remove the > "select RTC_LIB" line for MIPS, and then, the people will be free to > choose what they want, and even for the users whose platform not support > RTC_LIB. RTC_LIB is the way to go; the non-RTC_LIB drivers are there only for backward compatbility. A grep through the defcconfig files for all platforms on all architectures finds that by now all have set CONFIG_RTC_LIB and the remaining users of CONFIG_RTC, CONFIG_JS_RTC, CONFIG_GEN_RTC, CONFIG_EFI_RTC, CONFIG_DS1302 (which all depend on !RTC_LIB) are all defconfig files which seem to be slowly bitrotting. Time to axe !RTC_LIB? I'm tempted. Ralf From wuzhangjin@gmail.com Wed Nov 4 16:16:58 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 04 Nov 2009 16:17:05 +0100 (CET) Received: from mail-ew0-f216.google.com ([209.85.219.216]:37744 "EHLO mail-ew0-f216.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492399AbZKDPQ6 (ORCPT ); Wed, 4 Nov 2009 16:16:58 +0100 Received: by ewy12 with SMTP id 12so1820770ewy.0 for ; Wed, 04 Nov 2009 07:16:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:subject:from:reply-to:to:cc :in-reply-to:references:content-type:organization:date:message-id :mime-version:x-mailer:content-transfer-encoding; bh=uPMiYkTdkl/bcsbqmGdJ4svWR1DrMHF05znDJbFE0n0=; b=UtPpQb4DM0LuGyH89CV/trUAR/MQ898DJDxexDNObvlrlu5zaU2/cAhLSufgPalCBB K8QwKoYEe/V/OyMG4NbTjOpgeXlfdMUXHs3669q047aCOG86DlbsxgP0i+lh1zWR47Wa 3hVRmJjQAWCA/CgyufgMRTbYSbDyqyczUreYE= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=subject:from:reply-to:to:cc:in-reply-to:references:content-type :organization:date:message-id:mime-version:x-mailer :content-transfer-encoding; b=X65MgGcuFV1iA73nwyA2+dtzzpK7nUAiIg5lN9+v+1vB2v2OSZalswDGiZLVS0cRhM /kQRX3F+UL9zgRk76/ABBUabfLull1NjKyTebpIna5RLxCVA2lFGqqacfxd9h1QTnCmZ m6faFwaf8r0w6gfM5Gtg45wskpcjWqoIor7Rs= Received: by 10.216.93.12 with SMTP id k12mr484165wef.195.1257347813157; Wed, 04 Nov 2009 07:16:53 -0800 (PST) Received: from ?172.16.2.101? ([222.92.8.142]) by mx.google.com with ESMTPS id u14sm3429709gvf.18.2009.11.04.07.16.47 (version=TLSv1/SSLv3 cipher=RC4-MD5); Wed, 04 Nov 2009 07:16:52 -0800 (PST) Subject: Re: [PATCH -queue v0 5/6] [loongson] rtc: enable legacy RTC driver on fuloong2f From: Wu Zhangjin Reply-To: wuzhangjin@gmail.com To: Ralf Baechle Cc: Arnaud Patard , linux-mips@linux-mips.org, LKML , huhb@lemote.com, yanh@lemote.com, Zhang Le , Thomas Gleixner , Nicholas Mc Guire , zhangfx@lemote.com, liujl@lemote.com In-Reply-To: <20091104141545.GA18408@linux-mips.org> References: <1257333527.8716.20.camel@falcon.domain.org> <20091104141545.GA18408@linux-mips.org> Content-Type: text/plain; charset="UTF-8" Organization: DSLab, Lanzhou University, China Date: Wed, 04 Nov 2009 23:12:59 +0800 Message-ID: <1257347585.16033.0.camel@falcon.domain.org> Mime-Version: 1.0 X-Mailer: Evolution 2.28.1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24676 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips On Wed, 2009-11-04 at 15:15 +0100, Ralf Baechle wrote: > On Wed, Nov 04, 2009 at 07:18:47PM +0800, Wu Zhangjin wrote: > > > In reality, fuloong2e, fuloong2f and yeeloong2f work fine with RTC_LIB, > > but relative patches need to append to drivers/rtc/rtc-cmos.c and also > > need a RTC platform device. If what I remembered is right, Gdium also > > need corresponding patches to make it work with RTC_LIB. > > > > Herein, I just let the basic support for those machines work, and then, > > the RTC_LIB support will be sent out later. > > > > and a small question: if legacy RTC driver works well on these machines, > > why should we forbid people to use it? I think it's better to remove the > > "select RTC_LIB" line for MIPS, and then, the people will be free to > > choose what they want, and even for the users whose platform not support > > RTC_LIB. > > RTC_LIB is the way to go; the non-RTC_LIB drivers are there only for > backward compatbility. A grep through the defcconfig files for all > platforms on all architectures finds that by now all have set > CONFIG_RTC_LIB and the remaining users of CONFIG_RTC, CONFIG_JS_RTC, > CONFIG_GEN_RTC, CONFIG_EFI_RTC, CONFIG_DS1302 (which all depend on !RTC_LIB) > are all defconfig files which seem to be slowly bitrotting. > > Time to axe !RTC_LIB? I'm tempted. > Okay, later, I will send the patches for RTC_LIB support asap, I'm testing it currently ;) Regards, Wu Zhangjin From wuzhangjin@gmail.com Wed Nov 4 16:23:58 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 04 Nov 2009 16:24:04 +0100 (CET) Received: from mail-ew0-f216.google.com ([209.85.219.216]:44262 "EHLO mail-ew0-f216.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492399AbZKDPX6 (ORCPT ); Wed, 4 Nov 2009 16:23:58 +0100 Received: by ewy12 with SMTP id 12so1828128ewy.0 for ; Wed, 04 Nov 2009 07:23:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:subject:from:reply-to:to:cc :in-reply-to:references:content-type:organization:date:message-id :mime-version:x-mailer:content-transfer-encoding; bh=AnNvKBXmPjvwrqfCK9AAwLHT4O9zTlbdBN+2pifycIk=; b=Orzm4My4bypcuEN7i4emLg1S1rf9cTz9Ll1TaXVOyFfqBaZI6hSoYhlYDFghq2ZMMc Aqjzk0seHdVNxuJ1IgCEdl9ilpVlJLQA8kdcjww9Y/2LAMmbunwLUoyt0+SnmQDnTnHx 7qRkEXyWqGB6G+4k+FCNCCeMACBmMBK49UsYI= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=subject:from:reply-to:to:cc:in-reply-to:references:content-type :organization:date:message-id:mime-version:x-mailer :content-transfer-encoding; b=NqOSNuxSMdZbf2gusNnmuDT0GMnoyrNV3EvMWchzzwJdLpicGVP18r5H0/CIbp8eJU scwY6fTaqoiQag+jEsk4IzqkcrR+eku0zOyarcz3viY9GWg0IEIP25pa5DfcHJf8/qGD NmTD3kc4TNdf/XFFgV9+OfEl4UrrFSaJ5aviA= Received: by 10.216.90.21 with SMTP id d21mr504493wef.85.1257348228015; Wed, 04 Nov 2009 07:23:48 -0800 (PST) Received: from ?172.16.2.101? ([222.92.8.142]) by mx.google.com with ESMTPS id t2sm3468832gve.27.2009.11.04.07.23.42 (version=TLSv1/SSLv3 cipher=RC4-MD5); Wed, 04 Nov 2009 07:23:47 -0800 (PST) Subject: Re: [PATCH -queue v0 1/6] [loongson] add basic loongson-2f support From: Wu Zhangjin Reply-To: wuzhangjin@gmail.com To: Ralf Baechle Cc: Arnaud Patard , linux-mips@linux-mips.org, LKML , huhb@lemote.com, yanh@lemote.com, Zhang Le , Thomas Gleixner , Nicholas Mc Guire , zhangfx@lemote.com, liujl@lemote.com In-Reply-To: <20091104111957.GA13549@linux-mips.org> References: <1257332652.8716.5.camel@falcon.domain.org> <20091104111957.GA13549@linux-mips.org> Content-Type: text/plain; charset="UTF-8" Organization: DSLab, Lanzhou University, China Date: Wed, 04 Nov 2009 23:23:46 +0800 Message-ID: <1257348226.16033.4.camel@falcon.domain.org> Mime-Version: 1.0 X-Mailer: Evolution 2.28.1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24677 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips Hi, On Wed, 2009-11-04 at 12:19 +0100, Ralf Baechle wrote: > On Wed, Nov 04, 2009 at 07:04:12PM +0800, Wu Zhangjin wrote: > > > > Small question : Why don't you restrict to 64bit kernels only ? From > > > what I remember from some discussions with ST, trying to use a 32-bit > > > kernel on 2f is a nice way to get troubles. It would be better imho to > > > forbid such a configuration. As a side effect, this will remove all > > > 'defined(CONFIG_64BIT)' parts of your #ifdef tests. > > > > > > > It's hard to make such a decision ;) Perhaps some guys want to play with > > the 32bit version. > > We have other systems where 32-bit kernel support is just remarkably ugly. > We've dropped 32-bit support for the SGI IP32 aka O2 - nobody seems to even > have really noticed that. The Sibyte systems would be good candidates to do > the same as accesses to outside the 32-bit address space are needed very > frequently. > So, we really remove the 32bit support? 1312 config CPU_LOONGSON2 1313 bool 1314 select CPU_SUPPORTS_32BIT_KERNEL --> remove it? 1315 select CPU_SUPPORTS_64BIT_KERNEL 1316 select CPU_SUPPORTS_HIGHMEM If you all agree, I will send a new patch to remove the above line and resend the corresponding patches without 32bit support, and removed the relative CONFIG_64BIT lines in the patches too. Regards, Wu Zhangjin From wuzhangjin@gmail.com Wed Nov 4 16:49:35 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 04 Nov 2009 16:49:41 +0100 (CET) Received: from ey-out-1920.google.com ([74.125.78.146]:30678 "EHLO ey-out-1920.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492428AbZKDPtf (ORCPT ); Wed, 4 Nov 2009 16:49:35 +0100 Received: by ey-out-1920.google.com with SMTP id 3so1034361eyh.0 for ; Wed, 04 Nov 2009 07:49:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer; bh=HOQSeZ/FNM3eCDt4OL6hUbwqaeP9eZ6tUZEzVq+EmhQ=; b=BqIQVdCmsSbWbL9OgA81mmA90hzaZA9mK8FxWhFlE/K469RmCTMY3ZnqQVqqDFUou+ xsJm7bRoU9HRkbLLCIZRNccLJNUkYDcxdb29akOVM22aQ1Htyc9Tv9lMyY+hJXZ8WNSL 4GKF7jNUL3m+3YB8hbkUGUtFq+AEugzgGCIo0= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer; b=eUkVqZ0eIDiNFDeCAYijh/iqAxRAf7mJHuLT3HhDy/FB5MfzFuKHMGzQw91vdiSOG0 y6GPbQilcZuQu/6PzCHY7x1iWHEQe3nf9QcTDMnXflDZvhtxpMNNApRTfqRno0tCUBiD xgGiBdzfam04NJcvjPPLnykNW2lPMkw68jWss= Received: by 10.216.93.68 with SMTP id k46mr494926wef.161.1257349773065; Wed, 04 Nov 2009 07:49:33 -0800 (PST) Received: from localhost.localdomain ([222.92.8.142]) by mx.google.com with ESMTPS id q9sm3529060gve.0.2009.11.04.07.49.29 (version=TLSv1/SSLv3 cipher=RC4-MD5); Wed, 04 Nov 2009 07:49:32 -0800 (PST) From: Wu Zhangjin To: Ralf Baechle Cc: Arnaud Patard , Wu Zhangjin , linux-mips@linux-mips.org, rtc-linux@googlegroups.com Subject: [PATCH 1/2] RTC: enable RTC_LIB for fuloong2e and fuloong2f Date: Wed, 4 Nov 2009 23:49:22 +0800 Message-Id: <1257349762-21407-1-git-send-email-wuzhangjin@gmail.com> X-Mailer: git-send-email 1.6.2.1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24678 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips This patch fixes the following warning with RTC_LIB on MIPS: drivers/rtc/rtc-cmos.c:697:2: warning: #warning Assuming 128 bytes of RTC+NVRAM address space, not 64 bytes. and also, enables the RTC_DM_BINARY support. without this support, RTC_LIB of fuloong2e and fuloong2f does not work. The platform RTC device driver is coming in the next patch. Signed-off-by: Wu Zhangjin --- drivers/rtc/rtc-cmos.c | 8 ++++---- 1 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/rtc/rtc-cmos.c b/drivers/rtc/rtc-cmos.c index f7a4701..820bdad 100644 --- a/drivers/rtc/rtc-cmos.c +++ b/drivers/rtc/rtc-cmos.c @@ -691,7 +691,8 @@ cmos_do_probe(struct device *dev, struct resource *ports, int rtc_irq) */ #if defined(CONFIG_ATARI) address_space = 64; -#elif defined(__i386__) || defined(__x86_64__) || defined(__arm__) || defined(__sparc__) +#elif defined(__i386__) || defined(__x86_64__) || defined(__arm__) \ + || defined(__sparc__) || defined(__mips__) address_space = 128; #else #warning Assuming 128 bytes of RTC+NVRAM address space, not 64 bytes. @@ -756,9 +757,8 @@ cmos_do_probe(struct device *dev, struct resource *ports, int rtc_irq) /* FIXME teach the alarm code how to handle binary mode; * doesn't know 12-hour mode either. */ - if (is_valid_irq(rtc_irq) && - (!(rtc_control & RTC_24H) || (rtc_control & (RTC_DM_BINARY)))) { - dev_dbg(dev, "only 24-hr BCD mode supported\n"); + if (is_valid_irq(rtc_irq) && !(rtc_control & RTC_24H)) { + dev_dbg(dev, "only 24-hr supported\n"); retval = -ENXIO; goto cleanup1; } -- 1.6.2.1 From wuzhangjin@gmail.com Wed Nov 4 16:49:59 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 04 Nov 2009 16:50:07 +0100 (CET) Received: from ey-out-1920.google.com ([74.125.78.147]:29720 "EHLO ey-out-1920.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1493336AbZKDPt5 (ORCPT ); Wed, 4 Nov 2009 16:49:57 +0100 Received: by ey-out-1920.google.com with SMTP id 5so1345976eyb.52 for ; Wed, 04 Nov 2009 07:49:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer; bh=pXg76eGKgVLobzobc1iTlMyzb4x1a8DF/jeBTMBXkbY=; b=NBkyM2dizG2BDe6dGW3Syh5exJfOSQyhloaThkpKkmxiKexsnYxmbwzEK+qHVzfQU8 LNeye/Wpiq+Rp+z7leG5ltK2P2hQZCzewkOtB4TYbj6rhpNVItG9XFyo+5Pzbzj7MGrX /u4V4uSAr21NXFD6Wdq+qP3LvRYjj8llh9OiY= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer; b=QfFI5voY8/lL2vZ/6p8QLF/mrbpBLPUrrjmsXRfh3a59FMJnZkn+Z2LP3q5FQWlT2/ gJO9ZhMqAVGN0l1GrnQKloG8q5EQLjwICxmamXlDd2Jt2YMK/OecfVReqskqJsxFcWKK /Yeo0sbAwVs1LY5QfcQ6X0++TNaKann3HUxMI= Received: by 10.216.86.142 with SMTP id w14mr495451wee.74.1257349796606; Wed, 04 Nov 2009 07:49:56 -0800 (PST) Received: from localhost.localdomain ([222.92.8.142]) by mx.google.com with ESMTPS id x6sm3550035gvf.1.2009.11.04.07.49.50 (version=TLSv1/SSLv3 cipher=RC4-MD5); Wed, 04 Nov 2009 07:49:55 -0800 (PST) From: Wu Zhangjin To: Ralf Baechle Cc: Arnaud Patard , Wu Zhangjin , linux-mips@linux-mips.org, rtc-linux@googlegroups.com Subject: [PATCH 2/2] [loongson] fuloong: add RTC_LIB Support Date: Wed, 4 Nov 2009 23:49:44 +0800 Message-Id: <1257349784-21444-1-git-send-email-wuzhangjin@gmail.com> X-Mailer: git-send-email 1.6.2.1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24679 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips This patch add the RTC_LIB support for fuloong2e,fuloong2f. To make hwclock work with it normally, please do: kernel configuration: Device Drivers ---> <*> Real Time Clock ---> <*> PC-style 'CMOS' user-space configuration: $ mknod /dev/rtc0 c 254 0 /dev/rtc0 is the default RTC device file. of course, if udevd is installed, ignore the above user-space configuration. Signed-off-by: Wu Zhangjin --- arch/mips/loongson/common/Makefile | 7 +++++ arch/mips/loongson/common/rtc.c | 45 ++++++++++++++++++++++++++++++++++++ 2 files changed, 52 insertions(+), 0 deletions(-) create mode 100644 arch/mips/loongson/common/rtc.c diff --git a/arch/mips/loongson/common/Makefile b/arch/mips/loongson/common/Makefile index d3138b8..d2184c8 100644 --- a/arch/mips/loongson/common/Makefile +++ b/arch/mips/loongson/common/Makefile @@ -16,3 +16,10 @@ obj-$(CONFIG_SERIAL_8250) += serial.o # space # obj-$(CONFIG_CS5536) += cs5536/ + +# +# Enable RTC Class support +# +# please enable CONFIG_RTC_DRV_CMOS +# +obj-$(CONFIG_RTC_DRV_CMOS) += rtc.o diff --git a/arch/mips/loongson/common/rtc.c b/arch/mips/loongson/common/rtc.c new file mode 100644 index 0000000..fe9464a --- /dev/null +++ b/arch/mips/loongson/common/rtc.c @@ -0,0 +1,45 @@ +/* + * Registration of Cobalt RTC platform device. + * + * Copyright (C) 2007 Yoichi Yuasa + * Copyright (C) 2009 Wu Zhangjin + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include +#include +#include +#include + +static struct resource rtc_cmos_resource[] = { + { + .start = RTC_PORT(0), + .end = RTC_PORT(1), + .flags = IORESOURCE_IO, + }, + { + .start = RTC_IRQ, + .end = RTC_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device rtc_cmos_device = { + .name = "rtc_cmos", + .id = -1, + .num_resources = ARRAY_SIZE(rtc_cmos_resource), + .resource = rtc_cmos_resource +}; + +static __init int rtc_cmos_init(void) +{ + platform_device_register(&rtc_cmos_device); + + return 0; +} + +device_initcall(rtc_cmos_init); -- 1.6.2.1 From arnaud.patard@mandriva.com Wed Nov 4 17:03:36 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 04 Nov 2009 17:03:43 +0100 (CET) Received: from mx1.moondrake.net ([212.85.150.166]:57011 "EHLO mx1.mandriva.com" rhost-flags-OK-OK-OK-FAIL) by ftp.linux-mips.org with ESMTP id S1493355AbZKDQDg (ORCPT ); Wed, 4 Nov 2009 17:03:36 +0100 Received: by mx1.mandriva.com (Postfix, from userid 501) id 8247127C003; Wed, 4 Nov 2009 17:03:35 +0100 (CET) Received: from office-abk.mandriva.com (unknown [195.7.104.248]) (using TLSv1 with cipher ADH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.mandriva.com (Postfix) with ESMTP id B5ED927C002; Wed, 4 Nov 2009 17:03:34 +0100 (CET) Received: from anduin.mandriva.com (fw2.mandriva.com [192.168.2.3]) by office-abk.mandriva.com (Postfix) with ESMTP id 696B4828ED; Wed, 4 Nov 2009 17:15:02 +0100 (CET) Received: from anduin.mandriva.com (localhost [127.0.0.1]) by anduin.mandriva.com (Postfix) with ESMTP id 9CC50FF855; Wed, 4 Nov 2009 17:03:35 +0100 (CET) From: Arnaud Patard To: Wu Zhangjin Cc: Ralf Baechle , linux-mips@linux-mips.org, rtc-linux@googlegroups.com Subject: Re: [PATCH 2/2] [loongson] fuloong: add RTC_LIB Support References: <1257349784-21444-1-git-send-email-wuzhangjin@gmail.com> Organization: Mandriva Date: Wed, 04 Nov 2009 17:03:35 +0100 In-Reply-To: <1257349784-21444-1-git-send-email-wuzhangjin@gmail.com> (Wu Zhangjin's message of "Wed, 4 Nov 2009 23:49:44 +0800") Message-ID: User-Agent: Gnus/5.1008 (Gnus v5.10.8) Emacs/22.1 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24680 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: apatard@mandriva.com Precedence: bulk X-list: linux-mips Wu Zhangjin writes: Hi, > + * Registration of Cobalt RTC platform device. Of Cobalt platform device ? I thought we were on loongson :) > + * > + * Copyright (C) 2007 Yoichi Yuasa > + * Copyright (C) 2009 Wu Zhangjin > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; either version 2 of the License, or > + * (at your option) any later version. > + */ > + > +#include > +#include > +#include > +#include > + > +static struct resource rtc_cmos_resource[] = { > + { > + .start = RTC_PORT(0), > + .end = RTC_PORT(1), > + .flags = IORESOURCE_IO, > + }, > + { > + .start = RTC_IRQ, > + .end = RTC_IRQ, > + .flags = IORESOURCE_IRQ, > + }, > +}; > + > +static struct platform_device rtc_cmos_device = { > + .name = "rtc_cmos", > + .id = -1, > + .num_resources = ARRAY_SIZE(rtc_cmos_resource), > + .resource = rtc_cmos_resource > +}; > + > +static __init int rtc_cmos_init(void) > +{ > + platform_device_register(&rtc_cmos_device); > + > + return 0; what about return platform_device_register(&rtc_cmos_device); ? Arnaud From wilbur512@gmail.com Wed Nov 4 17:19:15 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 04 Nov 2009 17:19:22 +0100 (CET) Received: from mail-yw0-f173.google.com ([209.85.211.173]:43309 "EHLO mail-yw0-f173.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492496AbZKDQTP (ORCPT ); Wed, 4 Nov 2009 17:19:15 +0100 Received: by ywh3 with SMTP id 3so7477655ywh.22 for ; Wed, 04 Nov 2009 08:19:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:date:message-id:subject :from:to:content-type; bh=52oulsJJ9bYYDhA6K65T1ABxLjaZQ9nx4lmmTHeoDn4=; b=WhEg8y7ndXAZqqfAQwMVmBThiAgaf9cTz4wX2hp091coqN/g1yMpnRKONXFSidui4F gWWEYGaDSJDv7tMM4M/p8VwU3sQYfDTRyPyqeiAmRBN9IfzCSfNwGWSSERBO3fSUBDyc AeV4wJrR9zzCELYJcLfEyrjYhf/tL99dPygyo= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:date:message-id:subject:from:to:content-type; b=Y5pdkzRWrkBikQwV8XvTW2UHbKbwDAK3fKqClKZP0aUZjEixMKiC11jtlxikQHkLwe ob+u473S5zo8qtcQ/yjKWo1AX0OzO3Xnr5rqu8DW/f3yL2FGGTqZPfN1p5EG7U5U51kN xj9W6DQegexaPOCiu1rtRjaskNCow20TXN+7U= MIME-Version: 1.0 Received: by 10.91.19.4 with SMTP id w4mr3813635agi.0.1257351542566; Wed, 04 Nov 2009 08:19:02 -0800 (PST) Date: Thu, 5 Nov 2009 00:19:02 +0800 Message-ID: Subject: mips timer could not work From: "wilbur.chan" To: Linux MIPS Mailing List Content-Type: multipart/alternative; boundary=001485f547900d6e6c04778df829 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24681 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wilbur512@gmail.com Precedence: bulk X-list: linux-mips --001485f547900d6e6c04778df829 Content-Type: text/plain; charset=ISO-8859-1 Hi all, This is a linux mips newbie's problem when he tried to boot a mips64 board . The timer seemed not working properly when booting. He has checked the count and compare register , found that , count register increased all the time ,however, compare register remained unchanged , non zero. he also checked the cause register ,the exception code was zero,indicating an external interrupt. And he found that ,timer interrupt seemed not triggered , for he has put some illegal code in handle_int function, but not found kernel even complained of that, so he guess that, no external interrupt(timer intterrupt) was triggered in this situation. Can someone here tell how to solve this problem? Thank in advance regards, --001485f547900d6e6c04778df829 Content-Type: text/html; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable
Hi=A0 all,
=A0
This is a linux mips newbie's =A0problem when he tried to=A0 boot = a mips64 board .
=A0
The timer seemed not working properly when booting.
=A0
He has =A0checked the count and compare register , found that , count = register =A0increased=A0 all the time ,however, compare register remained u= nchanged , non zero.
=A0
he=A0also checked the cause register ,the exception code was zero,indi= cating an external interrupt.
=A0
And=A0he found that ,timer =A0interrupt seemed not triggered , for=A0h= e has =A0put some illegal code in handle_int function,=A0but not found=A0ke= rnel=A0even complained=A0of that,
=A0
=A0so he guess that, no external interrupt(timer intterrupt) =A0was tr= iggered in this situation.
=A0
Can someone here tell =A0how to solve this problem? Thank=A0 in advanc= e
=A0
regards,
=A0
=A0
--001485f547900d6e6c04778df829-- From ralf@linux-mips.org Wed Nov 4 17:25:25 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 04 Nov 2009 17:25:28 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:39637 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-FAIL) by ftp.linux-mips.org with ESMTP id S1493367AbZKDQZZ (ORCPT ); Wed, 4 Nov 2009 17:25:25 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id nA4GQp9x022014; Wed, 4 Nov 2009 17:26:52 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id nA4GQoP0022012; Wed, 4 Nov 2009 17:26:50 +0100 Date: Wed, 4 Nov 2009 17:26:50 +0100 From: Ralf Baechle To: Wu Zhangjin Cc: Arnaud Patard , linux-mips@linux-mips.org, rtc-linux@googlegroups.com Subject: Re: [PATCH 1/2] RTC: enable RTC_LIB for fuloong2e and fuloong2f Message-ID: <20091104162650.GB18408@linux-mips.org> References: <1257349762-21407-1-git-send-email-wuzhangjin@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1257349762-21407-1-git-send-email-wuzhangjin@gmail.com> User-Agent: Mutt/1.5.19 (2009-01-05) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24682 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Wed, Nov 04, 2009 at 11:49:22PM +0800, Wu Zhangjin wrote: > diff --git a/drivers/rtc/rtc-cmos.c b/drivers/rtc/rtc-cmos.c > index f7a4701..820bdad 100644 > --- a/drivers/rtc/rtc-cmos.c > +++ b/drivers/rtc/rtc-cmos.c > @@ -691,7 +691,8 @@ cmos_do_probe(struct device *dev, struct resource *ports, int rtc_irq) > */ > #if defined(CONFIG_ATARI) > address_space = 64; > -#elif defined(__i386__) || defined(__x86_64__) || defined(__arm__) || defined(__sparc__) > +#elif defined(__i386__) || defined(__x86_64__) || defined(__arm__) \ > + || defined(__sparc__) || defined(__mips__) > address_space = 128; > #else > #warning Assuming 128 bytes of RTC+NVRAM address space, not 64 bytes. I'd like to see at least this first segment included for 2.6.32 already. Ralf From ralf@linux-mips.org Wed Nov 4 21:14:04 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 04 Nov 2009 21:14:07 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:44910 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-FAIL) by ftp.linux-mips.org with ESMTP id S1493654AbZKDUOE (ORCPT ); Wed, 4 Nov 2009 21:14:04 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id nA4KFPtA027742; Wed, 4 Nov 2009 21:15:26 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id nA4KFK0E027740; Wed, 4 Nov 2009 21:15:20 +0100 Date: Wed, 4 Nov 2009 21:15:20 +0100 From: Ralf Baechle To: Wu Zhangjin Cc: Arnaud Patard , linux-mips@linux-mips.org, LKML , huhb@lemote.com, yanh@lemote.com, Zhang Le , Thomas Gleixner , Nicholas Mc Guire , zhangfx@lemote.com, liujl@lemote.com Subject: Re: [PATCH -queue v0 1/6] [loongson] add basic loongson-2f support Message-ID: <20091104201520.GA26504@linux-mips.org> References: <1257332652.8716.5.camel@falcon.domain.org> <20091104111957.GA13549@linux-mips.org> <1257348226.16033.4.camel@falcon.domain.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1257348226.16033.4.camel@falcon.domain.org> User-Agent: Mutt/1.5.19 (2009-01-05) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24683 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Wed, Nov 04, 2009 at 11:23:46PM +0800, Wu Zhangjin wrote: > > We have other systems where 32-bit kernel support is just remarkably ugly. > > We've dropped 32-bit support for the SGI IP32 aka O2 - nobody seems to even > > have really noticed that. The Sibyte systems would be good candidates to do > > the same as accesses to outside the 32-bit address space are needed very > > frequently. > > > > So, we really remove the 32bit support? > > 1312 config CPU_LOONGSON2 > 1313 bool > 1314 select CPU_SUPPORTS_32BIT_KERNEL --> remove it? > 1315 select CPU_SUPPORTS_64BIT_KERNEL > 1316 select CPU_SUPPORTS_HIGHMEM > > If you all agree, I will send a new patch to remove the above line and > resend the corresponding patches without 32bit support, and removed the > relative CONFIG_64BIT lines in the patches too. If you need highmem with 32-bit (and with Loongson systems I assume that virtually all systems will have enough RAM to require that) then you're almost certainly better off going 64-bit. Highmem takes a performance toll which for some workloads can be very significant. And while highmem won't go away any time soon it's nothing kernel performance is being tuned for, so it's only going to get worse into the future so I'd not waste time on highmem unless I have to. Ralf From wuzhangjin@gmail.com Thu Nov 5 01:37:30 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 05 Nov 2009 01:37:37 +0100 (CET) Received: from mail-yw0-f173.google.com ([209.85.211.173]:35388 "EHLO mail-yw0-f173.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1494099AbZKEAha (ORCPT ); Thu, 5 Nov 2009 01:37:30 +0100 Received: by ywh3 with SMTP id 3so8006957ywh.22 for ; Wed, 04 Nov 2009 16:37:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:subject:from:reply-to:to:cc :in-reply-to:references:content-type:organization:date:message-id :mime-version:x-mailer:content-transfer-encoding; bh=qlyOp/tMpKSzF2liOHuc9GT7/qcuKuT/k5VVbnEiiEs=; b=t5OH9EletdWzU7ueg2uTtPN32yp5spzSzRdHMxCUrxeZC6PqNsV94vl3eA+ExlTdEZ jJsYnZNKc1qJ2gzd30QAUmkAKW2dYzd7g8jhyvL/yF9e4ylSVMAgnM7O2xxsvt3jSjPl ijN/+pyq8QjE2Y/HlCILEBqN4edTboDXh/JlE= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=subject:from:reply-to:to:cc:in-reply-to:references:content-type :organization:date:message-id:mime-version:x-mailer :content-transfer-encoding; b=SGcByZXWn0BprzcoS1YPfEraVhtIJL8R25PtxN+QO52Vu1UQX1rvABsy4nVWg9smgq nVMOmjTtoOJNGD23IOdfMCz/Ig3/+6aOVUJkij8e21SbA4YkZAQofMqClFkM7YVdQ/7A 6RlLduzNV4b0Cl9HCiYR8GbicqULBPJAr7GUs= Received: by 10.91.28.2 with SMTP id f2mr4638848agj.16.1257381442175; Wed, 04 Nov 2009 16:37:22 -0800 (PST) Received: from ?172.16.2.101? ([222.92.8.142]) by mx.google.com with ESMTPS id 7sm711587yxd.26.2009.11.04.16.37.18 (version=TLSv1/SSLv3 cipher=RC4-MD5); Wed, 04 Nov 2009 16:37:21 -0800 (PST) Subject: Re: [PATCH 2/2] [loongson] fuloong: add RTC_LIB Support From: Wu Zhangjin Reply-To: wuzhangjin@gmail.com To: Arnaud Patard Cc: Ralf Baechle , linux-mips@linux-mips.org, rtc-linux@googlegroups.com In-Reply-To: References: <1257349784-21444-1-git-send-email-wuzhangjin@gmail.com> Content-Type: text/plain; charset="UTF-8" Organization: DSLab, Lanzhou University, China Date: Thu, 05 Nov 2009 08:37:23 +0800 Message-ID: <1257381443.16033.6.camel@falcon.domain.org> Mime-Version: 1.0 X-Mailer: Evolution 2.28.1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24684 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips Hi, On Wed, 2009-11-04 at 17:03 +0100, Arnaud Patard wrote: > Wu Zhangjin writes: > Hi, > > > + * Registration of Cobalt RTC platform device. > > Of Cobalt platform device ? I thought we were on loongson :) > Ooh, I just copied the header ;) will remove it later. > > + * > > + * Copyright (C) 2007 Yoichi Yuasa > > + * Copyright (C) 2009 Wu Zhangjin > > + * > > + * This program is free software; you can redistribute it and/or modify > > + * it under the terms of the GNU General Public License as published by > > + * the Free Software Foundation; either version 2 of the License, or > > + * (at your option) any later version. > > + */ > > + > > +#include > > +#include > > +#include > > +#include > > + > > +static struct resource rtc_cmos_resource[] = { > > + { > > + .start = RTC_PORT(0), > > + .end = RTC_PORT(1), > > + .flags = IORESOURCE_IO, > > + }, > > + { > > + .start = RTC_IRQ, > > + .end = RTC_IRQ, > > + .flags = IORESOURCE_IRQ, > > + }, > > +}; > > + > > +static struct platform_device rtc_cmos_device = { > > + .name = "rtc_cmos", > > + .id = -1, > > + .num_resources = ARRAY_SIZE(rtc_cmos_resource), > > + .resource = rtc_cmos_resource > > +}; > > + > > +static __init int rtc_cmos_init(void) > > +{ > > + platform_device_register(&rtc_cmos_device); > > + > > + return 0; > > what about return platform_device_register(&rtc_cmos_device); ? > > Okay, later. Regards, Wu Zhangjin From wuzhangjin@gmail.com Thu Nov 5 01:44:37 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 05 Nov 2009 01:44:43 +0100 (CET) Received: from mail-yx0-f204.google.com ([209.85.210.204]:60674 "EHLO mail-yx0-f204.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1494102AbZKEAoh (ORCPT ); Thu, 5 Nov 2009 01:44:37 +0100 Received: by yxe42 with SMTP id 42so8034300yxe.22 for ; Wed, 04 Nov 2009 16:44:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:subject:from:reply-to:to:cc :in-reply-to:references:content-type:organization:date:message-id :mime-version:x-mailer:content-transfer-encoding; bh=Lp5eXAxVRv60txsFWkTY0kwpcIkaDT7HlIECJ9CANYo=; b=tdJSAEPCjYfGuD2oeSCOer0HshZSv8TkKQ//SRsoguH8c06sGN/e/NjEeeHRg6Orfe zscsKQCAlAGYQU3r07abMUJi6O/nMrSWv4h5rJTa9r3NCRjbtKNbsTtiaJsWzZEkbxpE vnQTdyGenCDnG0lggqjXDyL7R82WoidWhaKoY= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=subject:from:reply-to:to:cc:in-reply-to:references:content-type :organization:date:message-id:mime-version:x-mailer :content-transfer-encoding; b=TCwXkorIiHw4wnWG1dGT8XM26SwVaICc3Lxp500nUWaWZL/Ag1J0bOMh+ZveL6JVzs oGQaMwaxN95TzT26/qMZ1qad5+U3SZ0bUHAEJBs+KnGoQ88afi8569dwML7rbH32fE4a QdNC6eILFHO1aBOQYDcPt3Dejp3WMXst0Du18= Received: by 10.90.18.33 with SMTP id 33mr4212705agr.113.1257381869953; Wed, 04 Nov 2009 16:44:29 -0800 (PST) Received: from ?172.16.2.101? ([222.92.8.142]) by mx.google.com with ESMTPS id 5sm710230yxg.64.2009.11.04.16.44.26 (version=TLSv1/SSLv3 cipher=RC4-MD5); Wed, 04 Nov 2009 16:44:29 -0800 (PST) Subject: Re: [PATCH 1/2] RTC: enable RTC_LIB for fuloong2e and fuloong2f From: Wu Zhangjin Reply-To: wuzhangjin@gmail.com To: Ralf Baechle Cc: Arnaud Patard , linux-mips@linux-mips.org, rtc-linux@googlegroups.com In-Reply-To: <20091104162650.GB18408@linux-mips.org> References: <1257349762-21407-1-git-send-email-wuzhangjin@gmail.com> <20091104162650.GB18408@linux-mips.org> Content-Type: text/plain; charset="UTF-8" Organization: DSLab, Lanzhou University, China Date: Thu, 05 Nov 2009 08:44:30 +0800 Message-ID: <1257381870.16033.7.camel@falcon.domain.org> Mime-Version: 1.0 X-Mailer: Evolution 2.28.1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24685 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips On Wed, 2009-11-04 at 17:26 +0100, Ralf Baechle wrote: > On Wed, Nov 04, 2009 at 11:49:22PM +0800, Wu Zhangjin wrote: > > > diff --git a/drivers/rtc/rtc-cmos.c b/drivers/rtc/rtc-cmos.c > > index f7a4701..820bdad 100644 > > --- a/drivers/rtc/rtc-cmos.c > > +++ b/drivers/rtc/rtc-cmos.c > > @@ -691,7 +691,8 @@ cmos_do_probe(struct device *dev, struct resource *ports, int rtc_irq) > > */ > > #if defined(CONFIG_ATARI) > > address_space = 64; > > -#elif defined(__i386__) || defined(__x86_64__) || defined(__arm__) || defined(__sparc__) > > +#elif defined(__i386__) || defined(__x86_64__) || defined(__arm__) \ > > + || defined(__sparc__) || defined(__mips__) > > address_space = 128; > > #else > > #warning Assuming 128 bytes of RTC+NVRAM address space, not 64 bytes. > > I'd like to see at least this first segment included for 2.6.32 already. > Will split it out for 2.6.32. Regards, Wu Zhangjin From wuzhangjin@gmail.com Thu Nov 5 02:21:34 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 05 Nov 2009 02:21:41 +0100 (CET) Received: from mail-pw0-f45.google.com ([209.85.160.45]:57118 "EHLO mail-pw0-f45.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1494108AbZKEBVe (ORCPT ); Thu, 5 Nov 2009 02:21:34 +0100 Received: by pwi11 with SMTP id 11so3664671pwi.24 for ; Wed, 04 Nov 2009 17:21:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer; bh=tc7vz03WIlXtccCmDS5L0kynSxbxLiFdEDkFSR9ZESQ=; b=ph+tbL5Lbuy+0YBZBDyI3uuoyjsfjZVKcUZzGE9QuEyb1BWc+JmJXqlAY8kGiUFGRK nvas2c5tV7ZiO7ATDWdSrczHAflaFedei43P6qgnqh1gnpoX7r8jHdm3rc6dYDpofuW9 yQJvNUsRKR0QI17Z9YH2u7h5yILFprOOB7vlI= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer; b=gyf5Nlg7g3ksqEN4xBEBF9Hm/1sh4riKVxtVBXubkbBKctQVa3m235iCRYfZI8YrTM CkYRxgscH2v/piZVGdg3ZROAYs8hRqsUhEfCfTqLEDhCZQOVUEkPv9RdhDGibXbG+Pq9 I2QnfSgkI/knrwlLCbxLJEBXCUYXqtw/ZHDAU= Received: by 10.114.4.14 with SMTP id 14mr3517968wad.224.1257384085058; Wed, 04 Nov 2009 17:21:25 -0800 (PST) Received: from localhost.localdomain ([222.92.8.142]) by mx.google.com with ESMTPS id 22sm955953pxi.6.2009.11.04.17.21.21 (version=TLSv1/SSLv3 cipher=RC4-MD5); Wed, 04 Nov 2009 17:21:24 -0800 (PST) From: Wu Zhangjin To: Paul Gortmaker , Alessandro Zummo , Ralf Baechle , Arnaud Patard Cc: linux-mips@linux-mips.org, rtc-linux@googlegroups.com, Wu Zhangjin Subject: [PATCH v1 0/3] add RTC_LIB support for loongson family machines Date: Thu, 5 Nov 2009 09:21:15 +0800 Message-Id: X-Mailer: git-send-email 1.6.2.1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24686 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips The coming three patchs add RTC_LIB support for loongson family machines, which incorporated the feedback of the first patchset from Ralf and Arnaud Patard. Hi, Paul Gortmaker or Alessandro Zummo, could you please help to apply the first two patches to linux-2.6.32? And the third patch is for the queue branch of Ralf's -queue git repo. Regards, Wu Zhangjin Wu Zhangjin (3): RTC: rtc-cmos.c: fix warning for MIPS RTC: rtc-cmos.c: enable RTC_DM_BINARY of RTC_LIB for fuloong2e and fuloong2f [loongson] RTC: Registration of Loongson RTC platform device arch/mips/loongson/common/Makefile | 6 +++++ arch/mips/loongson/common/rtc.c | 43 ++++++++++++++++++++++++++++++++++++ drivers/rtc/rtc-cmos.c | 8 +++--- 3 files changed, 53 insertions(+), 4 deletions(-) create mode 100644 arch/mips/loongson/common/rtc.c From wuzhangjin@gmail.com Thu Nov 5 02:22:14 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 05 Nov 2009 02:22:21 +0100 (CET) Received: from mail-px0-f176.google.com ([209.85.216.176]:54482 "EHLO mail-px0-f176.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1494105AbZKEBWO (ORCPT ); Thu, 5 Nov 2009 02:22:14 +0100 Received: by pxi6 with SMTP id 6so295117pxi.0 for ; Wed, 04 Nov 2009 17:22:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer:in-reply-to:references; bh=sJ+iOluJCQ6sc76Zjx2FFM67odmKGDgVhE1XhWkBvgA=; b=l8znhImNDpd7gfSazP6MxmuAif61OnhCG+bTSbunKCmbYmayA28zCWsquKd52LaWxT 8PXBP/Pb80qazJI+rzqi7mYLh0cqpUsjt+4SUQYYSY/b9UHCzuD0E8OcQWr1w772UcJU 1dMYTmY5k2cP19dtFInTHqB1CW8IC1f8Dz5l4= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; b=Pjx4kUkkHiOCuSO9RQ38ejcsMU6+/F7FszrbBW1b1EQgbmPxKJxF5eNNKmGK2a4MmV oSBbjMd0fR+S++51leKOzGEFiaTOIhGt4ZDEcyCOiIdD7D+T0CSBIB9wbRHVeOavQE22 zNL8lCxjlqc2/2NYAIEWnNG9QT3O0YvJcd/Gk= Received: by 10.114.164.20 with SMTP id m20mr3479872wae.216.1257384124740; Wed, 04 Nov 2009 17:22:04 -0800 (PST) Received: from localhost.localdomain ([222.92.8.142]) by mx.google.com with ESMTPS id 23sm125816pxi.13.2009.11.04.17.22.00 (version=TLSv1/SSLv3 cipher=RC4-MD5); Wed, 04 Nov 2009 17:22:04 -0800 (PST) From: Wu Zhangjin To: Paul Gortmaker , Alessandro Zummo Cc: linux-mips@linux-mips.org, rtc-linux@googlegroups.com, Wu Zhangjin Subject: [PATCH v1 1/3] RTC: rtc-cmos.c: fix warning for MIPS Date: Thu, 5 Nov 2009 09:21:54 +0800 Message-Id: X-Mailer: git-send-email 1.6.2.1 In-Reply-To: References: Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24687 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips This patch fixes the following warning with RTC_LIB on MIPS: drivers/rtc/rtc-cmos.c:697:2: warning: #warning Assuming 128 bytes of RTC+NVRAM address space, not 64 bytes. Signed-off-by: Wu Zhangjin --- drivers/rtc/rtc-cmos.c | 3 ++- 1 files changed, 2 insertions(+), 1 deletions(-) diff --git a/drivers/rtc/rtc-cmos.c b/drivers/rtc/rtc-cmos.c index f7a4701..21e48f7 100644 --- a/drivers/rtc/rtc-cmos.c +++ b/drivers/rtc/rtc-cmos.c @@ -691,7 +691,8 @@ cmos_do_probe(struct device *dev, struct resource *ports, int rtc_irq) */ #if defined(CONFIG_ATARI) address_space = 64; -#elif defined(__i386__) || defined(__x86_64__) || defined(__arm__) || defined(__sparc__) +#elif defined(__i386__) || defined(__x86_64__) || defined(__arm__) \ + || defined(__sparc__) || defined(__mips__) address_space = 128; #else #warning Assuming 128 bytes of RTC+NVRAM address space, not 64 bytes. -- 1.6.2.1 From wuzhangjin@gmail.com Thu Nov 5 02:22:39 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 05 Nov 2009 02:22:46 +0100 (CET) Received: from mail-pw0-f45.google.com ([209.85.160.45]:63638 "EHLO mail-pw0-f45.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1494109AbZKEBWZ (ORCPT ); Thu, 5 Nov 2009 02:22:25 +0100 Received: by pwi11 with SMTP id 11so3665067pwi.24 for ; Wed, 04 Nov 2009 17:22:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer:in-reply-to:references; bh=NPftuhRaJYz4+H8IsD9Pn3875PTOFXmVM8IhiNpvzV4=; b=XzAKdzLiyVdkQydOebXrxB33lHxBz72fNVZ4yQMTCCzrrT5g5SZQTIaXqbC+b7v8FR ARUyfKySudyLr1YNX5mG8xXkH3iseK9JPiOsMFDKPA8RZWQlaj/vEQcYopVR2hn0mCLq lDiULNtf44raWv0e7BfSO7kuo0njtyacEOK6I= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; b=imnv9FRvB9gLbJlebZyFvdcdgubmu8dKrUb+OzZgamy6JEKn21WNM37B693hlu5XRl IxGRuW8TlbQRaXI6RGGcpkJXGZEX6idv9yhvqWhwFsbZtsdeeiaRytWgAAdJWUYFdQkV rGjPKsnhyQSU7IZ4Ut7a3D3MYAbbU0GxnXHh0= Received: by 10.115.85.16 with SMTP id n16mr3555691wal.123.1257384137977; Wed, 04 Nov 2009 17:22:17 -0800 (PST) Received: from localhost.localdomain ([222.92.8.142]) by mx.google.com with ESMTPS id 22sm902654pzk.6.2009.11.04.17.22.15 (version=TLSv1/SSLv3 cipher=RC4-MD5); Wed, 04 Nov 2009 17:22:17 -0800 (PST) From: Wu Zhangjin To: Paul Gortmaker , Alessandro Zummo Cc: linux-mips@linux-mips.org, rtc-linux@googlegroups.com, Wu Zhangjin Subject: [PATCH v1 2/3] RTC: rtc-cmos.c: enable RTC_DM_BINARY of RTC_LIB for fuloong2e and fuloong2f Date: Thu, 5 Nov 2009 09:22:09 +0800 Message-Id: X-Mailer: git-send-email 1.6.2.1 In-Reply-To: References: Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24688 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips This patch enables the RTC_DM_BINARY support for RTC_LIB of fuloong2e and fuloong2f. without it, RTC_LIB not work on those machines. The platform RTC device driver is coming in the next patch. Signed-off-by: Wu Zhangjin --- drivers/rtc/rtc-cmos.c | 5 ++--- 1 files changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/rtc/rtc-cmos.c b/drivers/rtc/rtc-cmos.c index 21e48f7..820bdad 100644 --- a/drivers/rtc/rtc-cmos.c +++ b/drivers/rtc/rtc-cmos.c @@ -757,9 +757,8 @@ cmos_do_probe(struct device *dev, struct resource *ports, int rtc_irq) /* FIXME teach the alarm code how to handle binary mode; * doesn't know 12-hour mode either. */ - if (is_valid_irq(rtc_irq) && - (!(rtc_control & RTC_24H) || (rtc_control & (RTC_DM_BINARY)))) { - dev_dbg(dev, "only 24-hr BCD mode supported\n"); + if (is_valid_irq(rtc_irq) && !(rtc_control & RTC_24H)) { + dev_dbg(dev, "only 24-hr supported\n"); retval = -ENXIO; goto cleanup1; } -- 1.6.2.1 From wuzhangjin@gmail.com Thu Nov 5 02:24:28 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 05 Nov 2009 02:24:35 +0100 (CET) Received: from mail-pw0-f45.google.com ([209.85.160.45]:58138 "EHLO mail-pw0-f45.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1494105AbZKEBY2 (ORCPT ); Thu, 5 Nov 2009 02:24:28 +0100 Received: by pwi11 with SMTP id 11so3666014pwi.24 for ; Wed, 04 Nov 2009 17:24:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer:in-reply-to:references; bh=2on5FOJXrA9KtJSD8vnSTyMwTNogkrYX6cvxtxNM7HM=; b=tLGadlXgxRvYF76J7TIiZj2JGZQUj/EQ8zETB9kDBYhH1qJQjErUBfSJ6VAyGPaeDo fnSpHq/xSC7PHRNlUFLyMLs7AbgWEJ9X+3DWYfNkEJfzX1POddvUB1tP9sWfjrn3cSey 7NpiMj3z+90vsDmuV63H91/6eLKh7hE4wPk3Y= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; b=l3PF5DlqtudQ9IM79d8fI+Lx1HkML2t89cDsjw+JVFh/+MTwMugzFVDna9GDDY8UzJ gcvrLcylSshJpbuEO3oDGdQcCQjlupDzlFNd+iMFiJbLt99lemupPZZjta8hqsg7daQF T5Uoz5YH5vNUnxaE30PSqU+TLBR5Ghb4A9SrU= Received: by 10.114.7.39 with SMTP id 39mr3497440wag.188.1257384261352; Wed, 04 Nov 2009 17:24:21 -0800 (PST) Received: from localhost.localdomain ([222.92.8.142]) by mx.google.com with ESMTPS id 23sm913705pzk.0.2009.11.04.17.24.16 (version=TLSv1/SSLv3 cipher=RC4-MD5); Wed, 04 Nov 2009 17:24:20 -0800 (PST) From: Wu Zhangjin To: Ralf Baechle , Arnaud Patard Cc: linux-mips@linux-mips.org, rtc-linux@googlegroups.com, Paul Gortmaker , Alessandro Zummo , Wu Zhangjin Subject: [PATCH v1 3/3] [loongson] RTC: Registration of Loongson RTC platform device Date: Thu, 5 Nov 2009 09:24:10 +0800 Message-Id: X-Mailer: git-send-email 1.6.2.1 In-Reply-To: References: Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24689 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips This patch add the RTC_LIB support for fuloong2e,fuloong2f. To make hwclock work with it normally, please do: kernel configuration: Device Drivers ---> <*> Real Time Clock ---> <*> PC-style 'CMOS' user-space configuration: $ mknod /dev/rtc0 c 254 0 /dev/rtc0 is the default RTC device file. Of course, if udevd installed, ignore the above user-space configuration. Signed-off-by: Wu Zhangjin --- arch/mips/loongson/common/Makefile | 6 +++++ arch/mips/loongson/common/rtc.c | 43 ++++++++++++++++++++++++++++++++++++ 2 files changed, 49 insertions(+), 0 deletions(-) create mode 100644 arch/mips/loongson/common/rtc.c diff --git a/arch/mips/loongson/common/Makefile b/arch/mips/loongson/common/Makefile index d21d116..d1bd38c 100644 --- a/arch/mips/loongson/common/Makefile +++ b/arch/mips/loongson/common/Makefile @@ -10,3 +10,9 @@ obj-y += setup.o init.o cmdline.o env.o time.o reset.o irq.o \ # obj-$(CONFIG_EARLY_PRINTK) += early_printk.o obj-$(CONFIG_SERIAL_8250) += serial.o + +# Enable RTC Class support +# +# please enable CONFIG_RTC_DRV_CMOS +# +obj-$(CONFIG_RTC_DRV_CMOS) += rtc.o diff --git a/arch/mips/loongson/common/rtc.c b/arch/mips/loongson/common/rtc.c new file mode 100644 index 0000000..1f88791 --- /dev/null +++ b/arch/mips/loongson/common/rtc.c @@ -0,0 +1,43 @@ +/* + * Registration of Loongson RTC platform device. + * + * Copyright (C) 2007 Yoichi Yuasa + * Copyright (C) 2009 Wu Zhangjin + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include +#include +#include +#include + +static struct resource rtc_cmos_resource[] = { + { + .start = RTC_PORT(0), + .end = RTC_PORT(1), + .flags = IORESOURCE_IO, + }, + { + .start = RTC_IRQ, + .end = RTC_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device rtc_cmos_device = { + .name = "rtc_cmos", + .id = -1, + .num_resources = ARRAY_SIZE(rtc_cmos_resource), + .resource = rtc_cmos_resource +}; + +static __init int rtc_cmos_init(void) +{ + return platform_device_register(&rtc_cmos_device); +} + +device_initcall(rtc_cmos_init); -- 1.6.2.1 From wuzhangjin@gmail.com Thu Nov 5 02:39:44 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 05 Nov 2009 02:39:51 +0100 (CET) Received: from mail-pz0-f194.google.com ([209.85.222.194]:63784 "EHLO mail-pz0-f194.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1494107AbZKEBjo (ORCPT ); Thu, 5 Nov 2009 02:39:44 +0100 Received: by pzk32 with SMTP id 32so5261508pzk.21 for ; Wed, 04 Nov 2009 17:39:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:subject:from:reply-to:to:cc :in-reply-to:references:content-type:organization:date:message-id :mime-version:x-mailer:content-transfer-encoding; bh=wvSmpEiaTIreMjbEUwm7NUZlRX1dZ5Jh7xnbvgHcoaM=; b=SHblNLUXXyQfFmFXvBycpwAXbReJQOvLVa3JyRrL2jhrClasq7bEhzfmOKXFKQmzdV BpvJwo7drDzCmRyErb6USqpwljvOxE0k5mgePSAAUGmylbEd/PCyDyKwCC55HHeOzV3q 7X+eh98d+Il3EZJbZwK5URqS4e4Y9RKsVVnQ8= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=subject:from:reply-to:to:cc:in-reply-to:references:content-type :organization:date:message-id:mime-version:x-mailer :content-transfer-encoding; b=rxiAZKtTD6LxFrsjtCifOuAOsT4SXlRvrVoFzpAr0NPbTgHe5L4MLWThEdHd8gy7WD NhCi//8v36UVOP5qQRP2j8hxUMvw/+B90IL4qNrcHCH8qQtLcT+DywKILO4nv2smUUwk g4AP7FTW/xWDI4u+/lLIblUWfMgIShp9Xw+Ws= Received: by 10.114.7.9 with SMTP id 9mr3599056wag.71.1257385175839; Wed, 04 Nov 2009 17:39:35 -0800 (PST) Received: from ?172.16.2.101? ([222.92.8.142]) by mx.google.com with ESMTPS id 20sm913353pzk.5.2009.11.04.17.39.31 (version=TLSv1/SSLv3 cipher=RC4-MD5); Wed, 04 Nov 2009 17:39:35 -0800 (PST) Subject: Re: [PATCH -queue v0 1/6] [loongson] add basic loongson-2f support From: Wu Zhangjin Reply-To: wuzhangjin@gmail.com To: Ralf Baechle Cc: Arnaud Patard , linux-mips@linux-mips.org, LKML , huhb@lemote.com, yanh@lemote.com, Zhang Le , Thomas Gleixner , Nicholas Mc Guire , zhangfx@lemote.com, liujl@lemote.com In-Reply-To: <20091104201520.GA26504@linux-mips.org> References: <1257332652.8716.5.camel@falcon.domain.org> <20091104111957.GA13549@linux-mips.org> <1257348226.16033.4.camel@falcon.domain.org> <20091104201520.GA26504@linux-mips.org> Content-Type: text/plain; charset="UTF-8" Organization: DSLab, Lanzhou University, China Date: Thu, 05 Nov 2009 09:39:36 +0800 Message-ID: <1257385176.16033.17.camel@falcon.domain.org> Mime-Version: 1.0 X-Mailer: Evolution 2.28.1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24690 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips On Wed, 2009-11-04 at 21:15 +0100, Ralf Baechle wrote: > On Wed, Nov 04, 2009 at 11:23:46PM +0800, Wu Zhangjin wrote: > > > > We have other systems where 32-bit kernel support is just remarkably ugly. > > > We've dropped 32-bit support for the SGI IP32 aka O2 - nobody seems to even > > > have really noticed that. The Sibyte systems would be good candidates to do > > > the same as accesses to outside the 32-bit address space are needed very > > > frequently. > > > > > > > So, we really remove the 32bit support? > > > > 1312 config CPU_LOONGSON2 > > 1313 bool > > 1314 select CPU_SUPPORTS_32BIT_KERNEL --> remove it? > > 1315 select CPU_SUPPORTS_64BIT_KERNEL > > 1316 select CPU_SUPPORTS_HIGHMEM > > > > If you all agree, I will send a new patch to remove the above line and > > resend the corresponding patches without 32bit support, and removed the > > relative CONFIG_64BIT lines in the patches too. > > If you need highmem with 32-bit (and with Loongson systems I assume that > virtually all systems will have enough RAM to require that) then you're > almost certainly better off going 64-bit. Highmem takes a performance toll > which for some workloads can be very significant. And while highmem won't > go away any time soon it's nothing kernel performance is being tuned for, > so it's only going to get worse into the future so I'd not waste time on > highmem unless I have to. > What I have mentioned: "perhaps some guys need the 32bit version" here means, perhaps some embedded systems without enough memory and enough storage space may need the 32bit version, they not need highmem and also, the 32bit version will save some storage space for them. and I have used the 32bit version on my box and notebook(of course, only for experiments), no obvious problems. Reserve the 32bit version as an choice and select 64bit by default in the default config file? Regards, Wu Zhangjin From ralf@linux-mips.org Thu Nov 5 08:39:55 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 05 Nov 2009 08:39:59 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:49582 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-FAIL) by ftp.linux-mips.org with ESMTP id S1492026AbZKEHjz (ORCPT ); Thu, 5 Nov 2009 08:39:55 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id nA57fEWk012858; Thu, 5 Nov 2009 08:41:17 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id nA57fAjU012856; Thu, 5 Nov 2009 08:41:10 +0100 Date: Thu, 5 Nov 2009 08:41:08 +0100 From: Ralf Baechle To: Wu Zhangjin Cc: Paul Gortmaker , Alessandro Zummo , linux-mips@linux-mips.org, rtc-linux@googlegroups.com Subject: Re: [PATCH v1 1/3] RTC: rtc-cmos.c: fix warning for MIPS Message-ID: <20091105074107.GA12826@linux-mips.org> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.19 (2009-01-05) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24691 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Thu, Nov 05, 2009 at 09:21:54AM +0800, Wu Zhangjin wrote: > This patch fixes the following warning with RTC_LIB on MIPS: > > drivers/rtc/rtc-cmos.c:697:2: warning: #warning Assuming 128 bytes of > RTC+NVRAM address space, not 64 bytes. > > Signed-off-by: Wu Zhangjin Acked-by: Ralf Baechle Ralf From ralf@linux-mips.org Thu Nov 5 09:44:23 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 05 Nov 2009 09:44:26 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:43631 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-FAIL) by ftp.linux-mips.org with ESMTP id S1492050AbZKEIoX (ORCPT ); Thu, 5 Nov 2009 09:44:23 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id nA58jhpY014154; Thu, 5 Nov 2009 09:45:44 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id nA58jbUT014148; Thu, 5 Nov 2009 09:45:37 +0100 Date: Thu, 5 Nov 2009 09:45:37 +0100 From: Ralf Baechle To: Wu Zhangjin Cc: Arnaud Patard , linux-mips@linux-mips.org, LKML , huhb@lemote.com, yanh@lemote.com, Zhang Le , Thomas Gleixner , Nicholas Mc Guire , zhangfx@lemote.com, liujl@lemote.com Subject: Re: [PATCH -queue v0 1/6] [loongson] add basic loongson-2f support Message-ID: <20091105084537.GA12582@linux-mips.org> References: <1257332652.8716.5.camel@falcon.domain.org> <20091104111957.GA13549@linux-mips.org> <1257348226.16033.4.camel@falcon.domain.org> <20091104201520.GA26504@linux-mips.org> <1257385176.16033.17.camel@falcon.domain.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1257385176.16033.17.camel@falcon.domain.org> User-Agent: Mutt/1.5.19 (2009-01-05) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24692 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Thu, Nov 05, 2009 at 09:39:36AM +0800, Wu Zhangjin wrote: > > > > We have other systems where 32-bit kernel support is just remarkably ugly. > > > > We've dropped 32-bit support for the SGI IP32 aka O2 - nobody seems to even > > > > have really noticed that. The Sibyte systems would be good candidates to do > > > > the same as accesses to outside the 32-bit address space are needed very > > > > frequently. > > > > > > > > > > So, we really remove the 32bit support? > > > > > > 1312 config CPU_LOONGSON2 > > > 1313 bool > > > 1314 select CPU_SUPPORTS_32BIT_KERNEL --> remove it? > > > 1315 select CPU_SUPPORTS_64BIT_KERNEL > > > 1316 select CPU_SUPPORTS_HIGHMEM > > > > > > If you all agree, I will send a new patch to remove the above line and > > > resend the corresponding patches without 32bit support, and removed the > > > relative CONFIG_64BIT lines in the patches too. > > > > If you need highmem with 32-bit (and with Loongson systems I assume that > > virtually all systems will have enough RAM to require that) then you're > > almost certainly better off going 64-bit. Highmem takes a performance toll > > which for some workloads can be very significant. And while highmem won't > > go away any time soon it's nothing kernel performance is being tuned for, > > so it's only going to get worse into the future so I'd not waste time on > > highmem unless I have to. > > > > What I have mentioned: "perhaps some guys need the 32bit version" here > means, perhaps some embedded systems without enough memory and enough > storage space may need the 32bit version, they not need highmem and > also, the 32bit version will save some storage space for them. and I > have used the 32bit version on my box and notebook(of course, only for > experiments), no obvious problems. > > Reserve the 32bit version as an choice and select 64bit by default in > the default config file? No problem - I was just expressing my expressing my experiences on the usefulness of supporting both settings. One usually tends up favored, the other little used. Ralf From ralf@linux-mips.org Thu Nov 5 10:17:35 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 05 Nov 2009 10:17:37 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:50679 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-FAIL) by ftp.linux-mips.org with ESMTP id S1492135AbZKEJRe (ORCPT ); Thu, 5 Nov 2009 10:17:34 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id nA59InBb014772; Thu, 5 Nov 2009 10:18:49 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id nA59Ifoh014767; Thu, 5 Nov 2009 10:18:41 +0100 Date: Thu, 5 Nov 2009 10:18:41 +0100 From: Ralf Baechle To: Wu Zhangjin Cc: linux-mips@linux-mips.org, LKML , huhb@lemote.com, yanh@lemote.com, Zhang Le , Thomas Gleixner , Nicholas Mc Guire , zhangfx@lemote.com, liujl@lemote.com Subject: Re: [PATCH -queue v0 1/6] [loongson] add basic loongson-2f support Message-ID: <20091105091841.GC12582@linux-mips.org> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.19 (2009-01-05) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24693 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Wed, Nov 04, 2009 at 05:04:47PM +0800, Wu Zhangjin wrote: > diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig > index ae9fa98..8417357 100644 > --- a/arch/mips/Kconfig > +++ b/arch/mips/Kconfig > @@ -1059,6 +1059,21 @@ config CPU_LOONGSON2E > The Loongson 2E processor implements the MIPS III instruction set > with many extensions. > > + It has an internal FPGA northbridge, which is compatiable to > + bonito64. > + > +config CPU_LOONGSON2F > + bool "Loongson 2F" > + depends on SYS_HAS_CPU_LOONGSON2F > + select CPU_LOONGSON2 > + help > + The Loongson 2F processor implements the MIPS III instruction set > + with many extensions. I thought the Loongson 2E/2F were MIPS64 Release 1 compatible? > + Loongson2F have built-in DDR2 and PCIX controller. The PCIX controller > + have a similar programming interface with FPGA northbridge used in > + Loongson2E. > + > config CPU_MIPS32_R1 > bool "MIPS32 Release 1" > depends on SYS_HAS_CPU_MIPS32_R1 > @@ -1303,6 +1318,9 @@ config CPU_LOONGSON2 > config SYS_HAS_CPU_LOONGSON2E > bool > > +config SYS_HAS_CPU_LOONGSON2F > + bool > + > config SYS_HAS_CPU_MIPS32_R1 > bool > > diff --git a/arch/mips/Makefile b/arch/mips/Makefile > index ba04782..47ecded 100644 > --- a/arch/mips/Makefile > +++ b/arch/mips/Makefile > @@ -125,6 +125,8 @@ cflags-$(CONFIG_CPU_TX49XX) += -march=r4600 -Wa,--trap > cflags-$(CONFIG_CPU_LOONGSON2) += -Wa,--trap > cflags-$(CONFIG_CPU_LOONGSON2E) += \ > $(call cc-option,-march=loongson2e,-march=r4600) > +cflags-$(CONFIG_CPU_LOONGSON2F) += \ > + $(call cc-option,-march=loongson2f,-march=r4600) > > cflags-$(CONFIG_CPU_MIPS32_R1) += $(call cc-option,-march=mips32,-mips32 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS32) \ > -Wa,-mips32 -Wa,--trap > diff --git a/arch/mips/include/asm/mach-loongson/dma-coherence.h b/arch/mips/include/asm/mach-loongson/dma-coherence.h > index 71a6851..981c75f 100644 > --- a/arch/mips/include/asm/mach-loongson/dma-coherence.h > +++ b/arch/mips/include/asm/mach-loongson/dma-coherence.h > @@ -28,7 +28,11 @@ static inline dma_addr_t plat_map_dma_mem_page(struct device *dev, > static inline unsigned long plat_dma_addr_to_phys(struct device *dev, > dma_addr_t dma_addr) > { > +#if defined(CONFIG_CPU_LOONGSON2F) && defined(CONFIG_64BIT) > + return (dma_addr > 0x8fffffff) ? dma_addr : (dma_addr & 0x0fffffff); > +#else > return dma_addr & 0x7fffffff; > +#endif You're ifdefing on Loongson 2F - doesn't that mean that you can't have a kernel that supports both Loongson 2E and 2F? > } > > static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr, > diff --git a/arch/mips/include/asm/mach-loongson/loongson.h b/arch/mips/include/asm/mach-loongson/loongson.h > index e6869aa..9e41469 100644 > --- a/arch/mips/include/asm/mach-loongson/loongson.h > +++ b/arch/mips/include/asm/mach-loongson/loongson.h > @@ -1,5 +1,5 @@ > /* > - * Copyright (C) 2009 Lemote, Inc. & Institute of Computing Technology > + * Copyright (C) 2009 Lemote, Inc. > * Author: Wu Zhangjin > * > * This program is free software; you can redistribute it and/or modify it > @@ -215,4 +215,86 @@ extern void mach_irq_dispatch(unsigned int pending); > #define LOONGSON_PCIMAP_WIN(WIN, ADDR) \ > ((((ADDR)>>26) & LOONGSON_PCIMAP_PCIMAP_LO0) << ((WIN)*6)) > > +/* Chip Config */ > +#ifdef CONFIG_CPU_LOONGSON2F > +#define LOONGSON_CHIPCFG0 LOONGSON_REG(LOONGSON_REGBASE + 0x80) > +#endif > + > +/* > + * address windows configuration module > + * > + * loongson2e do not have this module > + */ > +#if defined(CONFIG_CPU_LOONGSON2F) && defined(CONFIG_64BIT) > + > +/* address window config module base address */ > +#define LOONGSON_ADDRWINCFG_BASE 0x3ff00000ul > +#define LOONGSON_ADDRWINCFG_SIZE 0x180 > + > +extern unsigned long _loongson_addrwincfg_base; > +#define LOONGSON_ADDRWINCFG(offset) \ > + (*(volatile u64 *)(_loongson_addrwincfg_base + (offset))) > + > +#define CPU_WIN0_BASE LOONGSON_ADDRWINCFG(0x00) > +#define CPU_WIN1_BASE LOONGSON_ADDRWINCFG(0x08) > +#define CPU_WIN2_BASE LOONGSON_ADDRWINCFG(0x10) > +#define CPU_WIN3_BASE LOONGSON_ADDRWINCFG(0x18) > + > +#define CPU_WIN0_MASK LOONGSON_ADDRWINCFG(0x20) > +#define CPU_WIN1_MASK LOONGSON_ADDRWINCFG(0x28) > +#define CPU_WIN2_MASK LOONGSON_ADDRWINCFG(0x30) > +#define CPU_WIN3_MASK LOONGSON_ADDRWINCFG(0x38) > + > +#define CPU_WIN0_MMAP LOONGSON_ADDRWINCFG(0x40) > +#define CPU_WIN1_MMAP LOONGSON_ADDRWINCFG(0x48) > +#define CPU_WIN2_MMAP LOONGSON_ADDRWINCFG(0x50) > +#define CPU_WIN3_MMAP LOONGSON_ADDRWINCFG(0x58) > + > +#define PCIDMA_WIN0_BASE LOONGSON_ADDRWINCFG(0x60) > +#define PCIDMA_WIN1_BASE LOONGSON_ADDRWINCFG(0x68) > +#define PCIDMA_WIN2_BASE LOONGSON_ADDRWINCFG(0x70) > +#define PCIDMA_WIN3_BASE LOONGSON_ADDRWINCFG(0x78) > + > +#define PCIDMA_WIN0_MASK LOONGSON_ADDRWINCFG(0x80) > +#define PCIDMA_WIN1_MASK LOONGSON_ADDRWINCFG(0x88) > +#define PCIDMA_WIN2_MASK LOONGSON_ADDRWINCFG(0x90) > +#define PCIDMA_WIN3_MASK LOONGSON_ADDRWINCFG(0x98) > + > +#define PCIDMA_WIN0_MMAP LOONGSON_ADDRWINCFG(0xa0) > +#define PCIDMA_WIN1_MMAP LOONGSON_ADDRWINCFG(0xa8) > +#define PCIDMA_WIN2_MMAP LOONGSON_ADDRWINCFG(0xb0) > +#define PCIDMA_WIN3_MMAP LOONGSON_ADDRWINCFG(0xb8) > + > +#define ADDRWIN_WIN0 0 > +#define ADDRWIN_WIN1 1 > +#define ADDRWIN_WIN2 2 > +#define ADDRWIN_WIN3 3 > + > +#define ADDRWIN_MAP_DST_DDR 0 > +#define ADDRWIN_MAP_DST_PCI 1 > +#define ADDRWIN_MAP_DST_LIO 1 > + > +/* > + * s: CPU, PCIDMA > + * d: DDR, PCI, LIO > + * win: 0, 1, 2, 3 > + * src: map source > + * dst: map destination > + * size: ~mask + 1 > + */ > +#define LOONGSON_ADDRWIN_CFG(s, d, w, src, dst, size) do {\ > + s##_WIN##w##_BASE = (src); \ > + s##_WIN##w##_MMAP = (src) | ADDRWIN_MAP_DST_##d; \ > + s##_WIN##w##_MASK = ~(size-1); \ > +} while (0) > + > +#define LOONGSON_ADDRWIN_CPUTOPCI(win, src, dst, size) \ > + LOONGSON_ADDRWIN_CFG(CPU, PCI, win, src, dst, size) > +#define LOONGSON_ADDRWIN_CPUTODDR(win, src, dst, size) \ > + LOONGSON_ADDRWIN_CFG(CPU, DDR, win, src, dst, size) > +#define LOONGSON_ADDRWIN_PCITODDR(win, src, dst, size) \ > + LOONGSON_ADDRWIN_CFG(PCIDMA, DDR, win, src, dst, size) > + > +#endif /* ! CONFIG_CPU_LOONGSON2F && CONFIG_64BIT */ > + > #endif /* __ASM_MACH_LOONGSON_LOONGSON_H */ > diff --git a/arch/mips/include/asm/mach-loongson/mem.h b/arch/mips/include/asm/mach-loongson/mem.h > index bd7b3cb..5c6551d 100644 > --- a/arch/mips/include/asm/mach-loongson/mem.h > +++ b/arch/mips/include/asm/mach-loongson/mem.h > @@ -12,19 +12,30 @@ > #define __ASM_MACH_LOONGSON_MEM_H > > /* > - * On Lemote Loongson 2e > + * high memory space > * > - * the high memory space starts from 512M. > - * the peripheral registers reside between 0x1000:0000 and 0x2000:0000. > + * in loongson2e, starts from 512M > + * in loongson2f, starts from 2G 256M > */ > +#ifdef CONFIG_CPU_LOONGSON2E > +#define LOONGSON_HIGHMEM_START 0x20000000 > +#else > +#define LOONGSON_HIGHMEM_START 0x90000000 > +#endif > > -#ifdef CONFIG_LEMOTE_FULOONG2E > - > -#define LOONGSON_HIGHMEM_START 0x20000000 > +/* > + * the peripheral registers(MMIO): > + * > + * On the Lemote Loongson 2e system, reside between 0x1000:0000 and 0x2000:0000. > + * On the Lemote Loongson 2f system, reside between 0x1000:0000 and 0x8000:0000. > + */ > > #define LOONGSON_MMIO_MEM_START 0x10000000 > -#define LOONGSON_MMIO_MEM_END 0x20000000 > > +#ifdef CONFIG_CPU_LOONGSON2E > +#define LOONGSON_MMIO_MEM_END 0x20000000 > +#else > +#define LOONGSON_MMIO_MEM_END 0x80000000 > #endif > > #endif /* __ASM_MACH_LOONGSON_MEM_H */ > diff --git a/arch/mips/include/asm/mach-loongson/pci.h b/arch/mips/include/asm/mach-loongson/pci.h > index 576487c..31ba908 100644 > --- a/arch/mips/include/asm/mach-loongson/pci.h > +++ b/arch/mips/include/asm/mach-loongson/pci.h > @@ -1,5 +1,6 @@ > /* > * Copyright (c) 2008 Zhang Le > + * Copyright (c) 2009 Wu Zhangjin > * > * This program is free software; you can redistribute it > * and/or modify it under the terms of the GNU General > @@ -24,7 +25,30 @@ > > extern struct pci_ops loongson_pci_ops; > > -#ifdef CONFIG_LEMOTE_FULOONG2E > +/* this is an offset from mips_io_port_base */ > +#define LOONGSON_PCI_IO_START 0x00004000UL > + > +#if defined(CONFIG_CPU_LOONGSON2F) && defined(CONFIG_64BIT) > + > +/* > + * we use address window2 to map cpu address space to pci space > + * window2: cpu [1G, 2G] -> pci [1G, 2G] > + * why not use window 0 & 1? because they are used by cpu when booting. > + * window0: cpu [0, 256M] -> ddr [0, 256M] > + * window1: cpu [256M, 512M] -> pci [256M, 512M] > + */ > + > +/* the smallest LOONGSON_CPU_MEM_SRC can be 512M */ > +#define LOONGSON_CPU_MEM_SRC 0x40000000ul /* 1G */ > +#define LOONGSON_PCI_MEM_DST LOONGSON_CPU_MEM_SRC > + > +#define LOONGSON_PCI_MEM_START LOONGSON_PCI_MEM_DST > +#define LOONGSON_PCI_MEM_END (0x80000000ul-1) /* 2G */ > + > +#define MMAP_CPUTOPCI_SIZE (LOONGSON_PCI_MEM_END - \ > + LOONGSON_PCI_MEM_START + 1) > + > +#else /* loongson2f/32bit & loongson2e */ > > /* this pci memory space is mapped by pcimap in pci.c */ > #define LOONGSON_PCI_MEM_START LOONGSON_PCILO1_BASE > @@ -32,6 +56,6 @@ extern struct pci_ops loongson_pci_ops; > /* this is an offset from mips_io_port_base */ > #define LOONGSON_PCI_IO_START 0x00004000UL > > -#endif > +#endif /* !(defined(CONFIG_CPU_LOONGSON2F) && defined(CONFIG_64BIT))*/ > > #endif /* !__ASM_MACH_LOONGSON_PCI_H_ */ > diff --git a/arch/mips/loongson/common/bonito-irq.c b/arch/mips/loongson/common/bonito-irq.c > index a1cbd11..9c1ddae 100644 > --- a/arch/mips/loongson/common/bonito-irq.c > +++ b/arch/mips/loongson/common/bonito-irq.c > @@ -35,10 +35,13 @@ static struct irq_chip bonito_irq_type = { > .unmask = bonito_irq_enable, > }; > > +/* there is no need to handle dma timeout in loongson-2f based machines */ > +#ifdef CONFIG_CPU_LOONGSON2E > static struct irqaction dma_timeout_irqaction = { > .handler = no_action, > .name = "dma_timeout", > }; > +#endif This #ifdef only seems to be used to suppress a warning. You can make that a little nicer by: #include static struct irqaction __maybe_unused dma_timeout_irqaction = { [...] }; > > void bonito_irq_init(void) > { > @@ -47,5 +50,7 @@ void bonito_irq_init(void) > for (i = LOONGSON_IRQ_BASE; i < LOONGSON_IRQ_BASE + 32; i++) > set_irq_chip_and_handler(i, &bonito_irq_type, handle_level_irq); > > +#ifdef CONFIG_CPU_LOONGSON2E > setup_irq(LOONGSON_IRQ_BASE + 10, &dma_timeout_irqaction); > +#endif > } > diff --git a/arch/mips/loongson/common/init.c b/arch/mips/loongson/common/init.c > index b7e4913..4afca97 100644 > --- a/arch/mips/loongson/common/init.c > +++ b/arch/mips/loongson/common/init.c > @@ -14,12 +14,30 @@ > > #include > > +#if defined(CONFIG_CPU_LOONGSON2F) && defined(CONFIG_64BIT) > +unsigned long _loongson_addrwincfg_base; > + > +/* Loongson CPU address windows config space base address */ > +static inline void set_loongson_addrwincfg_base(void) > +{ > + *(unsigned long *)&_loongson_addrwincfg_base = (unsigned long) > + ioremap(LOONGSON_ADDRWINCFG_BASE, LOONGSON_ADDRWINCFG_SIZE); > + barrier(); > +} > +#else > +static inline void set_loongson_addrwincfg_base(void) > +{ > +} > +#endif > + > void __init prom_init(void) > { > /* init base address of io space */ > set_io_port_base((unsigned long) > ioremap(LOONGSON_PCIIO_BASE, LOONGSON_PCIIO_SIZE)); > > + set_loongson_addrwincfg_base(); > + > prom_init_cmdline(); > prom_init_env(); > prom_init_memory(); > diff --git a/arch/mips/loongson/common/mem.c b/arch/mips/loongson/common/mem.c > index 47a20de..45991af 100644 > --- a/arch/mips/loongson/common/mem.c > +++ b/arch/mips/loongson/common/mem.c > @@ -21,6 +21,23 @@ void __init prom_init_memory(void) > add_memory_region(memsize << 20, LOONGSON_PCI_MEM_START - (memsize << > 20), BOOT_MEM_RESERVED); > #ifdef CONFIG_64BIT > +#ifdef CONFIG_CPU_LOONGSON2F > + { > + int bit; > + > + bit = fls(memsize + highmemsize); > + if (bit != ffs(memsize + highmemsize)) > + bit += 20; > + else > + bit = bit + 20 - 1; > + > + /* set cpu window3 to map CPU to DDR: 2G -> 2G */ > + LOONGSON_ADDRWIN_CPUTODDR(ADDRWIN_WIN3, 0x80000000ul, > + 0x80000000ul, (1 << bit)); > + mmiowb(); > + } > +#endif /* CONFIG_CPU_LOONGSON2F */ > + > if (highmemsize > 0) > add_memory_region(LOONGSON_HIGHMEM_START, > highmemsize << 20, BOOT_MEM_RAM); > diff --git a/arch/mips/loongson/common/pci.c b/arch/mips/loongson/common/pci.c > index a7eb8b9..eac43b8 100644 > --- a/arch/mips/loongson/common/pci.c > +++ b/arch/mips/loongson/common/pci.c > @@ -67,6 +67,14 @@ static void __init setup_pcimap(void) > /* can not change gnt to break pci transfer when device's gnt not > deassert for some broken device */ > LOONGSON_PXARB_CFG = 0x00fe0105ul; > + > +#if defined(CONFIG_CPU_LOONGSON2F) && defined(CONFIG_64BIT) > + /* > + * set cpu addr window2 to map CPU address space to PCI address space > + */ > + LOONGSON_ADDRWIN_CPUTOPCI(ADDRWIN_WIN2, LOONGSON_CPU_MEM_SRC, > + LOONGSON_PCI_MEM_DST, MMAP_CPUTOPCI_SIZE); > +#endif > } > > static int __init pcibios_init(void) > -- > 1.6.2.1 From wuzhangjin@gmail.com Thu Nov 5 10:48:56 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 05 Nov 2009 10:49:03 +0100 (CET) Received: from mail-pw0-f45.google.com ([209.85.160.45]:56697 "EHLO mail-pw0-f45.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492129AbZKEJs4 (ORCPT ); Thu, 5 Nov 2009 10:48:56 +0100 Received: by pwi11 with SMTP id 11so3894204pwi.24 for ; Thu, 05 Nov 2009 01:48:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:subject:from:reply-to:to:cc :in-reply-to:references:content-type:organization:date:message-id :mime-version:x-mailer:content-transfer-encoding; bh=4XxrFUYVIiB+tMcg4PShH5C7I54PsibDkZCaJyVQk6Y=; b=YN/n8SzAsPZyARN/1yEKisZ4DuW/m9wXyxGzcJfRZyxFZfnhJ4ViwUBluX0g4UbdKN jslRjkpCJdv8wXJMsdIsk2N1Dgv58IYsL89xPl6ogX2XrXJIcD5JHiwYmNKCUQHHCWw9 nKAZCVab3e2PGvIeVGQWs7hdjEDOEt8ullT+k= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=subject:from:reply-to:to:cc:in-reply-to:references:content-type :organization:date:message-id:mime-version:x-mailer :content-transfer-encoding; b=g/wKWlD1/GijrlTRCP0Zq+fLGZv7zq7WG2pTG4FBKLo5RdPSfQqT80qgtEa6S/jYMb avKDl87/OeJym14hwiigwS0unBDx+s0atV+tQdJbIAgMC/9b8aEYf5pe7v8ZFCZzj0eA l5IVuK0I/HNNBg4vZyQGsCwG5Tm0A2jsJvPWk= Received: by 10.115.101.15 with SMTP id d15mr4561138wam.200.1257414525538; Thu, 05 Nov 2009 01:48:45 -0800 (PST) Received: from ?172.16.2.101? ([222.92.8.142]) by mx.google.com with ESMTPS id 20sm582416pxi.15.2009.11.05.01.48.39 (version=TLSv1/SSLv3 cipher=RC4-MD5); Thu, 05 Nov 2009 01:48:45 -0800 (PST) Subject: Re: [PATCH -queue v0 1/6] [loongson] add basic loongson-2f support From: Wu Zhangjin Reply-To: wuzhangjin@gmail.com To: Ralf Baechle Cc: linux-mips@linux-mips.org, LKML , huhb@lemote.com, yanh@lemote.com, Zhang Le , Thomas Gleixner , Nicholas Mc Guire , zhangfx@lemote.com, liujl@lemote.com In-Reply-To: <20091105091841.GC12582@linux-mips.org> References: <20091105091841.GC12582@linux-mips.org> Content-Type: text/plain; charset="UTF-8" Organization: DSLab, Lanzhou University, China Date: Thu, 05 Nov 2009 17:48:43 +0800 Message-ID: <1257414523.1824.11.camel@falcon.domain.org> Mime-Version: 1.0 X-Mailer: Evolution 2.28.1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24694 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips On Thu, 2009-11-05 at 10:18 +0100, Ralf Baechle wrote: > On Wed, Nov 04, 2009 at 05:04:47PM +0800, Wu Zhangjin wrote: > > > diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig > > index ae9fa98..8417357 100644 > > --- a/arch/mips/Kconfig > > +++ b/arch/mips/Kconfig > > @@ -1059,6 +1059,21 @@ config CPU_LOONGSON2E > > The Loongson 2E processor implements the MIPS III instruction set > > with many extensions. > > > > + It has an internal FPGA northbridge, which is compatiable to > > + bonito64. > > + > > +config CPU_LOONGSON2F > > + bool "Loongson 2F" > > + depends on SYS_HAS_CPU_LOONGSON2F > > + select CPU_LOONGSON2 > > + help > > + The Loongson 2F processor implements the MIPS III instruction set > > + with many extensions. > > I thought the Loongson 2E/2F were MIPS64 Release 1 compatible? > They told me MIPS III, but added MMX instruction set ;) > > + Loongson2F have built-in DDR2 and PCIX controller. The PCIX controller > > + have a similar programming interface with FPGA northbridge used in > > + Loongson2E. > > + > > config CPU_MIPS32_R1 > > bool "MIPS32 Release 1" > > depends on SYS_HAS_CPU_MIPS32_R1 > > @@ -1303,6 +1318,9 @@ config CPU_LOONGSON2 > > config SYS_HAS_CPU_LOONGSON2E > > bool > > > > +config SYS_HAS_CPU_LOONGSON2F > > + bool > > + > > config SYS_HAS_CPU_MIPS32_R1 > > bool > > > > diff --git a/arch/mips/Makefile b/arch/mips/Makefile > > index ba04782..47ecded 100644 > > --- a/arch/mips/Makefile > > +++ b/arch/mips/Makefile > > @@ -125,6 +125,8 @@ cflags-$(CONFIG_CPU_TX49XX) += -march=r4600 -Wa,--trap > > cflags-$(CONFIG_CPU_LOONGSON2) += -Wa,--trap > > cflags-$(CONFIG_CPU_LOONGSON2E) += \ > > $(call cc-option,-march=loongson2e,-march=r4600) > > +cflags-$(CONFIG_CPU_LOONGSON2F) += \ > > + $(call cc-option,-march=loongson2f,-march=r4600) > > > > cflags-$(CONFIG_CPU_MIPS32_R1) += $(call cc-option,-march=mips32,-mips32 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS32) \ > > -Wa,-mips32 -Wa,--trap > > diff --git a/arch/mips/include/asm/mach-loongson/dma-coherence.h b/arch/mips/include/asm/mach-loongson/dma-coherence.h > > index 71a6851..981c75f 100644 > > --- a/arch/mips/include/asm/mach-loongson/dma-coherence.h > > +++ b/arch/mips/include/asm/mach-loongson/dma-coherence.h > > @@ -28,7 +28,11 @@ static inline dma_addr_t plat_map_dma_mem_page(struct device *dev, > > static inline unsigned long plat_dma_addr_to_phys(struct device *dev, > > dma_addr_t dma_addr) > > { > > +#if defined(CONFIG_CPU_LOONGSON2F) && defined(CONFIG_64BIT) > > + return (dma_addr > 0x8fffffff) ? dma_addr : (dma_addr & 0x0fffffff); > > +#else > > return dma_addr & 0x7fffffff; > > +#endif > > You're ifdefing on Loongson 2F - doesn't that mean that you can't have a > kernel that supports both Loongson 2E and 2F? > Currently, not consider it yet;) It's a little hard to cope with, should we consider it at this moment? if yes, I will try it with the help of exisiting machtype asap. but I think it's better to let it be the future job ;) > > } > > > > static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr, > > diff --git a/arch/mips/include/asm/mach-loongson/loongson.h b/arch/mips/include/asm/mach-loongson/loongson.h > > index e6869aa..9e41469 100644 > > --- a/arch/mips/include/asm/mach-loongson/loongson.h > > +++ b/arch/mips/include/asm/mach-loongson/loongson.h > > @@ -1,5 +1,5 @@ > > /* > > - * Copyright (C) 2009 Lemote, Inc. & Institute of Computing Technology > > + * Copyright (C) 2009 Lemote, Inc. > > * Author: Wu Zhangjin > > * > > * This program is free software; you can redistribute it and/or modify it > > @@ -215,4 +215,86 @@ extern void mach_irq_dispatch(unsigned int pending); > > #define LOONGSON_PCIMAP_WIN(WIN, ADDR) \ > > ((((ADDR)>>26) & LOONGSON_PCIMAP_PCIMAP_LO0) << ((WIN)*6)) > > > > +/* Chip Config */ > > +#ifdef CONFIG_CPU_LOONGSON2F > > +#define LOONGSON_CHIPCFG0 LOONGSON_REG(LOONGSON_REGBASE + 0x80) > > +#endif > > + > > +/* > > + * address windows configuration module > > + * > > + * loongson2e do not have this module > > + */ > > +#if defined(CONFIG_CPU_LOONGSON2F) && defined(CONFIG_64BIT) > > + > > +/* address window config module base address */ > > +#define LOONGSON_ADDRWINCFG_BASE 0x3ff00000ul > > +#define LOONGSON_ADDRWINCFG_SIZE 0x180 > > + > > +extern unsigned long _loongson_addrwincfg_base; > > +#define LOONGSON_ADDRWINCFG(offset) \ > > + (*(volatile u64 *)(_loongson_addrwincfg_base + (offset))) > > + > > +#define CPU_WIN0_BASE LOONGSON_ADDRWINCFG(0x00) > > +#define CPU_WIN1_BASE LOONGSON_ADDRWINCFG(0x08) > > +#define CPU_WIN2_BASE LOONGSON_ADDRWINCFG(0x10) > > +#define CPU_WIN3_BASE LOONGSON_ADDRWINCFG(0x18) > > + > > +#define CPU_WIN0_MASK LOONGSON_ADDRWINCFG(0x20) > > +#define CPU_WIN1_MASK LOONGSON_ADDRWINCFG(0x28) > > +#define CPU_WIN2_MASK LOONGSON_ADDRWINCFG(0x30) > > +#define CPU_WIN3_MASK LOONGSON_ADDRWINCFG(0x38) > > + > > +#define CPU_WIN0_MMAP LOONGSON_ADDRWINCFG(0x40) > > +#define CPU_WIN1_MMAP LOONGSON_ADDRWINCFG(0x48) > > +#define CPU_WIN2_MMAP LOONGSON_ADDRWINCFG(0x50) > > +#define CPU_WIN3_MMAP LOONGSON_ADDRWINCFG(0x58) > > + > > +#define PCIDMA_WIN0_BASE LOONGSON_ADDRWINCFG(0x60) > > +#define PCIDMA_WIN1_BASE LOONGSON_ADDRWINCFG(0x68) > > +#define PCIDMA_WIN2_BASE LOONGSON_ADDRWINCFG(0x70) > > +#define PCIDMA_WIN3_BASE LOONGSON_ADDRWINCFG(0x78) > > + > > +#define PCIDMA_WIN0_MASK LOONGSON_ADDRWINCFG(0x80) > > +#define PCIDMA_WIN1_MASK LOONGSON_ADDRWINCFG(0x88) > > +#define PCIDMA_WIN2_MASK LOONGSON_ADDRWINCFG(0x90) > > +#define PCIDMA_WIN3_MASK LOONGSON_ADDRWINCFG(0x98) > > + > > +#define PCIDMA_WIN0_MMAP LOONGSON_ADDRWINCFG(0xa0) > > +#define PCIDMA_WIN1_MMAP LOONGSON_ADDRWINCFG(0xa8) > > +#define PCIDMA_WIN2_MMAP LOONGSON_ADDRWINCFG(0xb0) > > +#define PCIDMA_WIN3_MMAP LOONGSON_ADDRWINCFG(0xb8) > > + > > +#define ADDRWIN_WIN0 0 > > +#define ADDRWIN_WIN1 1 > > +#define ADDRWIN_WIN2 2 > > +#define ADDRWIN_WIN3 3 > > + > > +#define ADDRWIN_MAP_DST_DDR 0 > > +#define ADDRWIN_MAP_DST_PCI 1 > > +#define ADDRWIN_MAP_DST_LIO 1 > > + > > +/* > > + * s: CPU, PCIDMA > > + * d: DDR, PCI, LIO > > + * win: 0, 1, 2, 3 > > + * src: map source > > + * dst: map destination > > + * size: ~mask + 1 > > + */ > > +#define LOONGSON_ADDRWIN_CFG(s, d, w, src, dst, size) do {\ > > + s##_WIN##w##_BASE = (src); \ > > + s##_WIN##w##_MMAP = (src) | ADDRWIN_MAP_DST_##d; \ > > + s##_WIN##w##_MASK = ~(size-1); \ > > +} while (0) > > + > > +#define LOONGSON_ADDRWIN_CPUTOPCI(win, src, dst, size) \ > > + LOONGSON_ADDRWIN_CFG(CPU, PCI, win, src, dst, size) > > +#define LOONGSON_ADDRWIN_CPUTODDR(win, src, dst, size) \ > > + LOONGSON_ADDRWIN_CFG(CPU, DDR, win, src, dst, size) > > +#define LOONGSON_ADDRWIN_PCITODDR(win, src, dst, size) \ > > + LOONGSON_ADDRWIN_CFG(PCIDMA, DDR, win, src, dst, size) > > + > > +#endif /* ! CONFIG_CPU_LOONGSON2F && CONFIG_64BIT */ > > + > > #endif /* __ASM_MACH_LOONGSON_LOONGSON_H */ > > diff --git a/arch/mips/include/asm/mach-loongson/mem.h b/arch/mips/include/asm/mach-loongson/mem.h > > index bd7b3cb..5c6551d 100644 > > --- a/arch/mips/include/asm/mach-loongson/mem.h > > +++ b/arch/mips/include/asm/mach-loongson/mem.h > > @@ -12,19 +12,30 @@ > > #define __ASM_MACH_LOONGSON_MEM_H > > > > /* > > - * On Lemote Loongson 2e > > + * high memory space > > * > > - * the high memory space starts from 512M. > > - * the peripheral registers reside between 0x1000:0000 and 0x2000:0000. > > + * in loongson2e, starts from 512M > > + * in loongson2f, starts from 2G 256M > > */ > > +#ifdef CONFIG_CPU_LOONGSON2E > > +#define LOONGSON_HIGHMEM_START 0x20000000 > > +#else > > +#define LOONGSON_HIGHMEM_START 0x90000000 > > +#endif > > > > -#ifdef CONFIG_LEMOTE_FULOONG2E > > - > > -#define LOONGSON_HIGHMEM_START 0x20000000 > > +/* > > + * the peripheral registers(MMIO): > > + * > > + * On the Lemote Loongson 2e system, reside between 0x1000:0000 and 0x2000:0000. > > + * On the Lemote Loongson 2f system, reside between 0x1000:0000 and 0x8000:0000. > > + */ > > > > #define LOONGSON_MMIO_MEM_START 0x10000000 > > -#define LOONGSON_MMIO_MEM_END 0x20000000 > > > > +#ifdef CONFIG_CPU_LOONGSON2E > > +#define LOONGSON_MMIO_MEM_END 0x20000000 > > +#else > > +#define LOONGSON_MMIO_MEM_END 0x80000000 > > #endif > > > > #endif /* __ASM_MACH_LOONGSON_MEM_H */ > > diff --git a/arch/mips/include/asm/mach-loongson/pci.h b/arch/mips/include/asm/mach-loongson/pci.h > > index 576487c..31ba908 100644 > > --- a/arch/mips/include/asm/mach-loongson/pci.h > > +++ b/arch/mips/include/asm/mach-loongson/pci.h > > @@ -1,5 +1,6 @@ > > /* > > * Copyright (c) 2008 Zhang Le > > + * Copyright (c) 2009 Wu Zhangjin > > * > > * This program is free software; you can redistribute it > > * and/or modify it under the terms of the GNU General > > @@ -24,7 +25,30 @@ > > > > extern struct pci_ops loongson_pci_ops; > > > > -#ifdef CONFIG_LEMOTE_FULOONG2E > > +/* this is an offset from mips_io_port_base */ > > +#define LOONGSON_PCI_IO_START 0x00004000UL > > + > > +#if defined(CONFIG_CPU_LOONGSON2F) && defined(CONFIG_64BIT) > > + > > +/* > > + * we use address window2 to map cpu address space to pci space > > + * window2: cpu [1G, 2G] -> pci [1G, 2G] > > + * why not use window 0 & 1? because they are used by cpu when booting. > > + * window0: cpu [0, 256M] -> ddr [0, 256M] > > + * window1: cpu [256M, 512M] -> pci [256M, 512M] > > + */ > > + > > +/* the smallest LOONGSON_CPU_MEM_SRC can be 512M */ > > +#define LOONGSON_CPU_MEM_SRC 0x40000000ul /* 1G */ > > +#define LOONGSON_PCI_MEM_DST LOONGSON_CPU_MEM_SRC > > + > > +#define LOONGSON_PCI_MEM_START LOONGSON_PCI_MEM_DST > > +#define LOONGSON_PCI_MEM_END (0x80000000ul-1) /* 2G */ > > + > > +#define MMAP_CPUTOPCI_SIZE (LOONGSON_PCI_MEM_END - \ > > + LOONGSON_PCI_MEM_START + 1) > > + > > +#else /* loongson2f/32bit & loongson2e */ > > > > /* this pci memory space is mapped by pcimap in pci.c */ > > #define LOONGSON_PCI_MEM_START LOONGSON_PCILO1_BASE > > @@ -32,6 +56,6 @@ extern struct pci_ops loongson_pci_ops; > > /* this is an offset from mips_io_port_base */ > > #define LOONGSON_PCI_IO_START 0x00004000UL > > > > -#endif > > +#endif /* !(defined(CONFIG_CPU_LOONGSON2F) && defined(CONFIG_64BIT))*/ > > > > #endif /* !__ASM_MACH_LOONGSON_PCI_H_ */ > > diff --git a/arch/mips/loongson/common/bonito-irq.c b/arch/mips/loongson/common/bonito-irq.c > > index a1cbd11..9c1ddae 100644 > > --- a/arch/mips/loongson/common/bonito-irq.c > > +++ b/arch/mips/loongson/common/bonito-irq.c > > @@ -35,10 +35,13 @@ static struct irq_chip bonito_irq_type = { > > .unmask = bonito_irq_enable, > > }; > > > > +/* there is no need to handle dma timeout in loongson-2f based machines */ > > +#ifdef CONFIG_CPU_LOONGSON2E > > static struct irqaction dma_timeout_irqaction = { > > .handler = no_action, > > .name = "dma_timeout", > > }; > > +#endif > > This #ifdef only seems to be used to suppress a warning. You can make > that a little nicer by: > > #include > > static struct irqaction __maybe_unused dma_timeout_irqaction = { > [...] > }; > okay, will apply it later. > > > > void bonito_irq_init(void) > > { > > @@ -47,5 +50,7 @@ void bonito_irq_init(void) > > for (i = LOONGSON_IRQ_BASE; i < LOONGSON_IRQ_BASE + 32; i++) > > set_irq_chip_and_handler(i, &bonito_irq_type, handle_level_irq); > > > > +#ifdef CONFIG_CPU_LOONGSON2E > > setup_irq(LOONGSON_IRQ_BASE + 10, &dma_timeout_irqaction); > > +#endif > > } > > diff --git a/arch/mips/loongson/common/init.c b/arch/mips/loongson/common/init.c > > index b7e4913..4afca97 100644 > > --- a/arch/mips/loongson/common/init.c > > +++ b/arch/mips/loongson/common/init.c > > @@ -14,12 +14,30 @@ > > > > #include > > > > +#if defined(CONFIG_CPU_LOONGSON2F) && defined(CONFIG_64BIT) > > +unsigned long _loongson_addrwincfg_base; > > + > > +/* Loongson CPU address windows config space base address */ > > +static inline void set_loongson_addrwincfg_base(void) > > +{ > > + *(unsigned long *)&_loongson_addrwincfg_base = (unsigned long) > > + ioremap(LOONGSON_ADDRWINCFG_BASE, LOONGSON_ADDRWINCFG_SIZE); > > + barrier(); > > +} > > +#else > > +static inline void set_loongson_addrwincfg_base(void) > > +{ > > +} > > +#endif > > + > > void __init prom_init(void) > > { > > /* init base address of io space */ > > set_io_port_base((unsigned long) > > ioremap(LOONGSON_PCIIO_BASE, LOONGSON_PCIIO_SIZE)); > > > > + set_loongson_addrwincfg_base(); > > + > > prom_init_cmdline(); > > prom_init_env(); > > prom_init_memory(); > > diff --git a/arch/mips/loongson/common/mem.c b/arch/mips/loongson/common/mem.c > > index 47a20de..45991af 100644 > > --- a/arch/mips/loongson/common/mem.c > > +++ b/arch/mips/loongson/common/mem.c > > @@ -21,6 +21,23 @@ void __init prom_init_memory(void) > > add_memory_region(memsize << 20, LOONGSON_PCI_MEM_START - (memsize << > > 20), BOOT_MEM_RESERVED); > > #ifdef CONFIG_64BIT > > +#ifdef CONFIG_CPU_LOONGSON2F > > + { > > + int bit; > > + > > + bit = fls(memsize + highmemsize); > > + if (bit != ffs(memsize + highmemsize)) > > + bit += 20; > > + else > > + bit = bit + 20 - 1; > > + > > + /* set cpu window3 to map CPU to DDR: 2G -> 2G */ > > + LOONGSON_ADDRWIN_CPUTODDR(ADDRWIN_WIN3, 0x80000000ul, > > + 0x80000000ul, (1 << bit)); > > + mmiowb(); > > + } > > +#endif /* CONFIG_CPU_LOONGSON2F */ > > + > > if (highmemsize > 0) > > add_memory_region(LOONGSON_HIGHMEM_START, > > highmemsize << 20, BOOT_MEM_RAM); > > diff --git a/arch/mips/loongson/common/pci.c b/arch/mips/loongson/common/pci.c > > index a7eb8b9..eac43b8 100644 > > --- a/arch/mips/loongson/common/pci.c > > +++ b/arch/mips/loongson/common/pci.c > > @@ -67,6 +67,14 @@ static void __init setup_pcimap(void) > > /* can not change gnt to break pci transfer when device's gnt not > > deassert for some broken device */ > > LOONGSON_PXARB_CFG = 0x00fe0105ul; > > + > > +#if defined(CONFIG_CPU_LOONGSON2F) && defined(CONFIG_64BIT) > > + /* > > + * set cpu addr window2 to map CPU address space to PCI address space > > + */ > > + LOONGSON_ADDRWIN_CPUTOPCI(ADDRWIN_WIN2, LOONGSON_CPU_MEM_SRC, > > + LOONGSON_PCI_MEM_DST, MMAP_CPUTOPCI_SIZE); > > +#endif > > } > > > > static int __init pcibios_init(void) > > -- > > 1.6.2.1 From ralf@linux-mips.org Thu Nov 5 11:27:19 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 05 Nov 2009 11:27:22 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:58532 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-FAIL) by ftp.linux-mips.org with ESMTP id S1492286AbZKEK1T (ORCPT ); Thu, 5 Nov 2009 11:27:19 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id nA5ASfdA015803; Thu, 5 Nov 2009 11:28:42 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id nA5AScOx015801; Thu, 5 Nov 2009 11:28:38 +0100 Date: Thu, 5 Nov 2009 11:28:38 +0100 From: Ralf Baechle To: Wu Zhangjin Cc: linux-mips@linux-mips.org, LKML , huhb@lemote.com, yanh@lemote.com, Zhang Le , Thomas Gleixner , Nicholas Mc Guire , zhangfx@lemote.com, liujl@lemote.com Subject: Re: [PATCH -queue v0 1/6] [loongson] add basic loongson-2f support Message-ID: <20091105102838.GF12582@linux-mips.org> References: <20091105091841.GC12582@linux-mips.org> <1257414523.1824.11.camel@falcon.domain.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1257414523.1824.11.camel@falcon.domain.org> User-Agent: Mutt/1.5.19 (2009-01-05) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24695 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Thu, Nov 05, 2009 at 05:48:43PM +0800, Wu Zhangjin wrote: > > I thought the Loongson 2E/2F were MIPS64 Release 1 compatible? > > > > They told me MIPS III, but added MMX instruction set ;) Just when I thought MIPS III was on the way out ;-) > > You're ifdefing on Loongson 2F - doesn't that mean that you can't have a > > kernel that supports both Loongson 2E and 2F? > > > > Currently, not consider it yet;) It's a little hard to cope with, should > we consider it at this moment? if yes, I will try it with the help of > exisiting machtype asap. but I think it's better to let it be the future > job ;) Fair enough - though I'm sure Linux distributions would be happy to have one kernel variant less to ship. > > static struct irqaction __maybe_unused dma_timeout_irqaction = { > > [...] > > }; > > > > okay, will apply it later. Thanks. Ralf From wuzhangjin@gmail.com Thu Nov 5 12:00:36 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 05 Nov 2009 12:00:42 +0100 (CET) Received: from mail-pz0-f194.google.com ([209.85.222.194]:60240 "EHLO mail-pz0-f194.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492306AbZKELAg (ORCPT ); Thu, 5 Nov 2009 12:00:36 +0100 Received: by pzk32 with SMTP id 32so5542115pzk.21 for ; Thu, 05 Nov 2009 03:00:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:subject:from:reply-to:to:cc :in-reply-to:references:content-type:organization:date:message-id :mime-version:x-mailer:content-transfer-encoding; bh=6Evv75u8IcigLRiZzwe7eQnrurGzgfgEc+JVowntnjA=; b=wZcpTwxVyLmOV5FTkdGHHBKyHlG5qN1ZOawIzR84tMXvFMKc5PJsNitucUqbzyefGZ QPHWkE6z7EfLB+YuohEqeBhn1FsWwrrsu/CUbznpdSj1UETqgHchQOsDLBTbFEWBQeYG kfwGLJZJCNswpJM435hqcbXUDFA1wuUGnETMg= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=subject:from:reply-to:to:cc:in-reply-to:references:content-type :organization:date:message-id:mime-version:x-mailer :content-transfer-encoding; b=A96k0644QFIW7fu/LVrJpXom+9PmlIr1qXcqr5blYY4/wxEfxz6TrVUybH1NIUyn46 lzWTAFTjbPPZyAEJQz7lL+ykelc9c+/KHrSv40geklWBlxZdmec0H9aVX+D4d0O9Olrg MwZES9X5uZQGTvMHgIiFHShBS2UQK3KjNREiU= Received: by 10.115.149.4 with SMTP id b4mr4797712wao.18.1257418826457; Thu, 05 Nov 2009 03:00:26 -0800 (PST) Received: from ?172.16.2.101? ([222.92.8.142]) by mx.google.com with ESMTPS id 20sm613625pxi.3.2009.11.05.03.00.21 (version=TLSv1/SSLv3 cipher=RC4-MD5); Thu, 05 Nov 2009 03:00:25 -0800 (PST) Subject: Re: [PATCH -queue v0 1/6] [loongson] add basic loongson-2f support From: Wu Zhangjin Reply-To: wuzhangjin@gmail.com To: Ralf Baechle Cc: linux-mips@linux-mips.org, LKML , huhb@lemote.com, yanh@lemote.com, Zhang Le , Thomas Gleixner , Nicholas Mc Guire , zhangfx@lemote.com, liujl@lemote.com In-Reply-To: <20091105102838.GF12582@linux-mips.org> References: <20091105091841.GC12582@linux-mips.org> <1257414523.1824.11.camel@falcon.domain.org> <20091105102838.GF12582@linux-mips.org> Content-Type: text/plain; charset="UTF-8" Organization: DSLab, Lanzhou University, China Date: Thu, 05 Nov 2009 19:00:16 +0800 Message-ID: <1257418816.3067.8.camel@falcon.domain.org> Mime-Version: 1.0 X-Mailer: Evolution 2.28.1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24696 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips Hi, > > > You're ifdefing on Loongson 2F - doesn't that mean that you can't have a > > > kernel that supports both Loongson 2E and 2F? > > > > > > > Currently, not consider it yet;) It's a little hard to cope with, should > > we consider it at this moment? if yes, I will try it with the help of > > exisiting machtype asap. but I think it's better to let it be the future > > job ;) > > Fair enough - though I'm sure Linux distributions would be happy to have > one kernel variant less to ship. > Yup, linux distributions will like it. but just remembered that: the instruciton set of loongson2e and loongson2f is different, -march=loongson2e, -march=loongson2f. so it will be not possible to merge them together, but I will try to merge the 2f support, so please wait for me merging fuloong2f & yeeloon2f, I will do it tonight, it is really an interesting job to do ;) Regards, Wu Zhangjin From ralf@linux-mips.org Thu Nov 5 14:14:46 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 05 Nov 2009 14:14:50 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:60590 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-FAIL) by ftp.linux-mips.org with ESMTP id S1492347AbZKENOq (ORCPT ); Thu, 5 Nov 2009 14:14:46 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id nA5DG8iu018415; Thu, 5 Nov 2009 14:16:08 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id nA5DG3kp018412; Thu, 5 Nov 2009 14:16:03 +0100 Date: Thu, 5 Nov 2009 14:16:03 +0100 From: Ralf Baechle To: Wu Zhangjin Cc: linux-mips@linux-mips.org, LKML , huhb@lemote.com, yanh@lemote.com, Zhang Le , Thomas Gleixner , Nicholas Mc Guire , zhangfx@lemote.com, liujl@lemote.com Subject: Re: [PATCH -queue v0 4/6] [loongson] add basic fuloong2f support Message-ID: <20091105131603.GA18232@linux-mips.org> References: <0f805f7d12c5a7cbcc125ba4a1b70113ec2047a6.1257325319.git.wuzhangjin@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <0f805f7d12c5a7cbcc125ba4a1b70113ec2047a6.1257325319.git.wuzhangjin@gmail.com> User-Agent: Mutt/1.5.19 (2009-01-05) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24697 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Wed, Nov 04, 2009 at 05:05:47PM +0800, Wu Zhangjin wrote: > diff --git a/arch/mips/loongson/fuloong-2f/irq.c b/arch/mips/loongson/fuloong-2f/irq.c > new file mode 100644 > index 0000000..22c45fd > --- /dev/null > +++ b/arch/mips/loongson/fuloong-2f/irq.c > @@ -0,0 +1,114 @@ > +/* > + * Copyright (C) 2007 Lemote Inc. > + * Author: Fuxin Zhang, zhangfx@lemote.com > + * > + * This program is free software; you can redistribute it and/or modify it > + * under the terms of the GNU General Public License as published by the > + * Free Software Foundation; either version 2 of the License, or (at your > + * option) any later version. > + */ > + > +#include > + > +#include > +#include > +#include > + > +#include > +#include > + > +#define LOONGSON_TIMER_IRQ (MIPS_CPU_IRQ_BASE + 7) /* cpu timer */ > +#define LOONGSON_PERFCNT_IRQ (MIPS_CPU_IRQ_BASE + 6) /* cpu perf counter */ > +#define LOONGSON_NORTH_BRIDGE_IRQ (MIPS_CPU_IRQ_BASE + 6) /* bonito */ > +#define LOONGSON_UART_IRQ (MIPS_CPU_IRQ_BASE + 3) /* cpu serial port */ > +#define LOONGSON_SOUTH_BRIDGE_IRQ (MIPS_CPU_IRQ_BASE + 2) /* i8259 */ > + > +#define LOONGSON_INT_BIT_INT0 (1 << 11) > +#define LOONGSON_INT_BIT_INT1 (1 << 12) > + > +static int mach_i8259_irq(void) > +{ > + int irq, isr, imr; > + > + irq = -1; > + > + if ((LOONGSON_INTISR & LOONGSON_INTEN) & LOONGSON_INT_BIT_INT0) { > + imr = inb(0x21) | (inb(0xa1) << 8); > + isr = inb(0x20) | (inb(0xa0) << 8); > + isr &= ~0x4; /* irq2 for cascade */ > + isr &= ~imr; > + irq = ffs(isr) - 1; > + } Any reason why you're not using i8259_irq() from here? That function not only gets the locking right, it also minimizes the number of accesses to the i8259 - which even on modern silicon can be stuningly slow. > +#if 1 > + pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &val); > + printk(KERN_INFO "cs5536 acc latency 0x%x\n", val); > + pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xc0); > +#endif Seems like left over debug code? > + return; > +} And a useless return statement at the end of a void function. Ralf From wuzhangjin@gmail.com Thu Nov 5 15:44:33 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 05 Nov 2009 15:44:39 +0100 (CET) Received: from mail-pz0-f194.google.com ([209.85.222.194]:40737 "EHLO mail-pz0-f194.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S2097292AbZKEOoc (ORCPT ); Thu, 5 Nov 2009 15:44:32 +0100 Received: by pzk32 with SMTP id 32so24115pzk.21 for ; Thu, 05 Nov 2009 06:44:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:subject:from:reply-to:to:cc :in-reply-to:references:content-type:organization:date:message-id :mime-version:x-mailer:content-transfer-encoding; bh=n5pmspPO/1jQVpMZeHWUJcc9qDGPprVPp4Z1at5utJU=; b=pkZUrzXjtdnyZNEab2iUuO/cYL3BP0IHWzbt/xkFiB72EzjCOtlbZAWm3LP1nMpNCs vq2zZQ7Wh5NxF/ggMCEQIwTvJdMv/fvCJpbho9WRSG4tltyGjPPObqgkFvPhJHzpMLfw pxAA6pPdLPzt/dKGdP5vicHgdGH876vA72PeI= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=subject:from:reply-to:to:cc:in-reply-to:references:content-type :organization:date:message-id:mime-version:x-mailer :content-transfer-encoding; b=wIyyuPKcagzj5XNLCeoMXXDOL7XqR0lDr7tXy4H3hTcH4QGjbUmH2JHN0lGwnP/Lee ZG24x28D1+ny/t4FjX2fjInPucgZagNqkGek9MdyIFPW0LHOQQ1UzWxkx2xJICeRPqE+ lkaM2IbrbEzZw+gadHXCZDUUGuceR2QlQODDw= Received: by 10.115.39.8 with SMTP id r8mr4998662waj.104.1257432265606; Thu, 05 Nov 2009 06:44:25 -0800 (PST) Received: from ?172.16.2.101? ([222.92.8.142]) by mx.google.com with ESMTPS id 20sm1235497pzk.9.2009.11.05.06.44.18 (version=TLSv1/SSLv3 cipher=RC4-MD5); Thu, 05 Nov 2009 06:44:25 -0800 (PST) Subject: Re: [PATCH -queue v0 4/6] [loongson] add basic fuloong2f support From: Wu Zhangjin Reply-To: wuzhangjin@gmail.com To: Ralf Baechle Cc: linux-mips@linux-mips.org, LKML , huhb@lemote.com, yanh@lemote.com, Zhang Le , Thomas Gleixner , Nicholas Mc Guire , zhangfx@lemote.com, liujl@lemote.com In-Reply-To: <20091105131603.GA18232@linux-mips.org> References: <0f805f7d12c5a7cbcc125ba4a1b70113ec2047a6.1257325319.git.wuzhangjin@gmail.com> <20091105131603.GA18232@linux-mips.org> Content-Type: text/plain; charset="UTF-8" Organization: DSLab, Lanzhou University, China Date: Thu, 05 Nov 2009 22:44:22 +0800 Message-ID: <1257432262.3067.42.camel@falcon.domain.org> Mime-Version: 1.0 X-Mailer: Evolution 2.28.1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24698 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips Hi, On Thu, 2009-11-05 at 14:16 +0100, Ralf Baechle wrote: > > + > > + if ((LOONGSON_INTISR & LOONGSON_INTEN) & LOONGSON_INT_BIT_INT0) { > > + imr = inb(0x21) | (inb(0xa1) << 8); > > + isr = inb(0x20) | (inb(0xa0) << 8); > > + isr &= ~0x4; /* irq2 for cascade */ > > + isr &= ~imr; > > + irq = ffs(isr) - 1; > > + } > > Any reason why you're not using i8259_irq() from here? > That function not only gets the locking right, it also minimizes the number > of accesses to the i8259 - which even on modern silicon can be stuningly > slow. > Seems there are some differences between here and the i8259_irq(), I forget the details, perhaps "Yan Hua" can give a detail explaination. > > +#if 1 > > + pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &val); > > + printk(KERN_INFO "cs5536 acc latency 0x%x\n", val); > > + pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xc0); > > +#endif > > Seems like left over debug code? > > > + return; > > +} > > And a useless return statement at the end of a void function. > Okay, will remove them later. Regards, Wu Zhangjin From ralf@linux-mips.org Thu Nov 5 18:55:42 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 05 Nov 2009 18:55:45 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:58907 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-FAIL) by ftp.linux-mips.org with ESMTP id S1492947AbZKERzm (ORCPT ); Thu, 5 Nov 2009 18:55:42 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id nA5Hv1uu024925; Thu, 5 Nov 2009 18:57:02 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id nA5HuxEt024923; Thu, 5 Nov 2009 18:56:59 +0100 Message-Id: <20091105152702.606651698@linux-mips.org> User-Agent: quilt/0.47-1 Date: Thu, 05 Nov 2009 16:26:04 +0100 From: Ralf Baechle To: Linus Torvalds Cc: Maxime Bizon , linux-mips@linux-mips.org, linux-serial@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 6/6] SERIAL: BCM63xx: Fix serial driver compile breakage. References: <20091105152555.227009519@linux-mips.org> Content-Disposition: inline; filename=0009.patch Lines: 36 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24699 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips From: Maxime Bizon The driver missed an API change. Signed-off-by: Maxime Bizon Cc: linux-mips@linux-mips.org Cc: linux-serial@vger.kernel.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Ralf Baechle drivers/serial/bcm63xx_uart.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) Index: upstream-linus/drivers/serial/bcm63xx_uart.c =================================================================== --- upstream-linus.orig/drivers/serial/bcm63xx_uart.c +++ upstream-linus/drivers/serial/bcm63xx_uart.c @@ -242,7 +242,7 @@ static void bcm_uart_do_rx(struct uart_p * higher than fifo size anyway since we're much faster than * serial port */ max_count = 32; - tty = port->info->port.tty; + tty = port->state->port.tty; do { unsigned int iestat, c, cstat; char flag; @@ -318,7 +318,7 @@ static void bcm_uart_do_tx(struct uart_p return; } - xmit = &port->info->xmit; + xmit = &port->state->xmit; if (uart_circ_empty(xmit)) goto txq_empty; From ralf@linux-mips.org Thu Nov 5 18:56:03 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 05 Nov 2009 18:56:08 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:58908 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-FAIL) by ftp.linux-mips.org with ESMTP id S1492952AbZKERzm (ORCPT ); Thu, 5 Nov 2009 18:55:42 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id nA5Hv3MU024929; Thu, 5 Nov 2009 18:57:03 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id nA5Hv20x024928; Thu, 5 Nov 2009 18:57:02 +0100 Message-Id: <20091105152702.365281887@linux-mips.org> User-Agent: quilt/0.47-1 Date: Thu, 05 Nov 2009 16:26:01 +0100 From: Ralf Baechle To: Linus Torvalds Cc: Julia Lawall , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Subject: [PATCH 5/6] VIDEO: Correct use of request_region/request_mem_region References: <20091105152555.227009519@linux-mips.org> Content-Disposition: inline; filename=0006.patch Lines: 70 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24700 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips From: Julia Lawall Geert Uytterhoeven pointed out that in the case of drivers/video/gbefb.c, the problem is actually the other way around; request_mem_region should be used instead of request_region. The semantic patch that finds/fixes this problem is as follows: (http://coccinelle.lip6.fr/) // @r1@ expression start; @@ request_region(start,...) @b1@ expression r1.start; @@ request_mem_region(start,...) @depends on !b1@ expression r1.start; expression E; @@ - release_mem_region + release_region (start,E) // Signed-off-by: Julia Lawall Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Ralf Baechle drivers/video/gbefb.c | 2 +- drivers/video/tdfxfb.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) Index: upstream-linus/drivers/video/gbefb.c =================================================================== --- upstream-linus.orig/drivers/video/gbefb.c +++ upstream-linus/drivers/video/gbefb.c @@ -1147,7 +1147,7 @@ static int __init gbefb_probe(struct pla gbefb_setup(options); #endif - if (!request_region(GBE_BASE, sizeof(struct sgi_gbe), "GBE")) { + if (!request_mem_region(GBE_BASE, sizeof(struct sgi_gbe), "GBE")) { printk(KERN_ERR "gbefb: couldn't reserve mmio region\n"); ret = -EBUSY; goto out_release_framebuffer; Index: upstream-linus/drivers/video/tdfxfb.c =================================================================== --- upstream-linus.orig/drivers/video/tdfxfb.c +++ upstream-linus/drivers/video/tdfxfb.c @@ -1571,8 +1571,8 @@ out_err_iobase: if (default_par->mtrr_handle >= 0) mtrr_del(default_par->mtrr_handle, info->fix.smem_start, info->fix.smem_len); - release_mem_region(pci_resource_start(pdev, 2), - pci_resource_len(pdev, 2)); + release_region(pci_resource_start(pdev, 2), + pci_resource_len(pdev, 2)); out_err_screenbase: if (info->screen_base) iounmap(info->screen_base); From ralf@linux-mips.org Thu Nov 5 18:56:26 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 05 Nov 2009 18:56:31 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:58912 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-FAIL) by ftp.linux-mips.org with ESMTP id S1492974AbZKERzn (ORCPT ); Thu, 5 Nov 2009 18:55:43 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id nA5Hv7Kf024945; Thu, 5 Nov 2009 18:57:07 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id nA5Hv7Xm024944; Thu, 5 Nov 2009 18:57:07 +0100 Message-Id: <20091105152702.035396736@linux-mips.org> User-Agent: quilt/0.47-1 Date: Thu, 05 Nov 2009 16:25:57 +0100 From: Ralf Baechle To: Linus Torvalds Cc: David Daney , Greg Kroah-Hartman , devel@driverdev.osuosl.org, linux-kernel@vger.kernel.org, linux-mips@linux-mips.org, netdev@vger.kernel.org Subject: [PATCH 1/6] Staging: Octeon: Fix compile error in drivers/staging/octeon/ethernet-mdio.c References: <20091105152555.227009519@linux-mips.org> Content-Disposition: inline; filename=0002.patch Lines: 27 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24701 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips From: David Daney Signed-off-by: David Daney Cc: Greg Kroah-Hartman Cc: devel@driverdev.osuosl.org Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: netdev@vger.kernel.org Signed-off-by: Ralf Baechle drivers/staging/octeon/ethernet-mdio.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) Index: upstream-linus/drivers/staging/octeon/ethernet-mdio.c =================================================================== --- upstream-linus.orig/drivers/staging/octeon/ethernet-mdio.c +++ upstream-linus/drivers/staging/octeon/ethernet-mdio.c @@ -170,7 +170,7 @@ static u32 cvm_oct_get_link(struct net_d return ret; } -struct const ethtool_ops cvm_oct_ethtool_ops = { +const struct ethtool_ops cvm_oct_ethtool_ops = { .get_drvinfo = cvm_oct_get_drvinfo, .get_settings = cvm_oct_get_settings, .set_settings = cvm_oct_set_settings, From ralf@linux-mips.org Thu Nov 5 18:56:48 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 05 Nov 2009 18:56:53 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:58913 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-FAIL) by ftp.linux-mips.org with ESMTP id S1492990AbZKERzn (ORCPT ); Thu, 5 Nov 2009 18:55:43 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id nA5Hv7jO024937; Thu, 5 Nov 2009 18:57:07 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id nA5Hv57K024936; Thu, 5 Nov 2009 18:57:05 +0100 Message-Id: <20091105152702.201728770@linux-mips.org> User-Agent: quilt/0.47-1 Date: Thu, 05 Nov 2009 16:25:59 +0100 From: Ralf Baechle To: Linus Torvalds Cc: David Daney , Greg Kroah-Hartman , devel@driverdev.osuosl.org, linux-kernel@vger.kernel.org, linux-mips@linux-mips.org, netdev@vger.kernel.org Subject: [PATCH 3/6] Staging: octeon-ethernet: Assign proper MAC addresses. References: <20091105152555.227009519@linux-mips.org> Content-Disposition: inline; filename=0004.patch Lines: 110 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24702 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips From: David Daney Allocate MAC addresses using the same method as the bootloader. This avoids changing the MAC between bootloader and kernel operation as well as avoiding duplicates and use of addresses outside of the assigned range. Signed-off-by: David Daney Cc: Greg Kroah-Hartman Cc: devel@driverdev.osuosl.org Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: netdev@vger.kernel.org Signed-off-by: Ralf Baechle drivers/staging/octeon/ethernet.c | 53 +++++++++++++++++++++++++++++--------- 1 file changed, 41 insertions(+), 12 deletions(-) Index: upstream-linus/drivers/staging/octeon/ethernet.c =================================================================== --- upstream-linus.orig/drivers/staging/octeon/ethernet.c +++ upstream-linus/drivers/staging/octeon/ethernet.c @@ -111,6 +111,16 @@ MODULE_PARM_DESC(disable_core_queueing, "\tallows packets to be sent without lock contention in the packet\n" "\tscheduler resulting in some cases in improved throughput.\n"); + +/* + * The offset from mac_addr_base that should be used for the next port + * that is configured. By convention, if any mgmt ports exist on the + * chip, they get the first mac addresses, The ports controlled by + * this driver are numbered sequencially following any mgmt addresses + * that may exist. + */ +static unsigned int cvm_oct_mac_addr_offset; + /** * Periodic timer to check auto negotiation */ @@ -474,16 +484,30 @@ static int cvm_oct_common_set_mac_addres */ int cvm_oct_common_init(struct net_device *dev) { - static int count; - char mac[8] = { 0x00, 0x00, - octeon_bootinfo->mac_addr_base[0], - octeon_bootinfo->mac_addr_base[1], - octeon_bootinfo->mac_addr_base[2], - octeon_bootinfo->mac_addr_base[3], - octeon_bootinfo->mac_addr_base[4], - octeon_bootinfo->mac_addr_base[5] + count - }; struct octeon_ethernet *priv = netdev_priv(dev); + struct sockaddr sa; + u64 mac = ((u64)(octeon_bootinfo->mac_addr_base[0] & 0xff) << 40) | + ((u64)(octeon_bootinfo->mac_addr_base[1] & 0xff) << 32) | + ((u64)(octeon_bootinfo->mac_addr_base[2] & 0xff) << 24) | + ((u64)(octeon_bootinfo->mac_addr_base[3] & 0xff) << 16) | + ((u64)(octeon_bootinfo->mac_addr_base[4] & 0xff) << 8) | + (u64)(octeon_bootinfo->mac_addr_base[5] & 0xff); + + mac += cvm_oct_mac_addr_offset; + sa.sa_data[0] = (mac >> 40) & 0xff; + sa.sa_data[1] = (mac >> 32) & 0xff; + sa.sa_data[2] = (mac >> 24) & 0xff; + sa.sa_data[3] = (mac >> 16) & 0xff; + sa.sa_data[4] = (mac >> 8) & 0xff; + sa.sa_data[5] = mac & 0xff; + + if (cvm_oct_mac_addr_offset >= octeon_bootinfo->mac_addr_count) + printk(KERN_DEBUG "%s: Using MAC outside of the assigned range:" + " %02x:%02x:%02x:%02x:%02x:%02x\n", dev->name, + sa.sa_data[0] & 0xff, sa.sa_data[1] & 0xff, + sa.sa_data[2] & 0xff, sa.sa_data[3] & 0xff, + sa.sa_data[4] & 0xff, sa.sa_data[5] & 0xff); + cvm_oct_mac_addr_offset++; /* * Force the interface to use the POW send if always_use_pow @@ -496,14 +520,12 @@ int cvm_oct_common_init(struct net_devic if (priv->queue != -1 && USE_HW_TCPUDP_CHECKSUM) dev->features |= NETIF_F_IP_CSUM; - count++; - /* We do our own locking, Linux doesn't need to */ dev->features |= NETIF_F_LLTX; SET_ETHTOOL_OPS(dev, &cvm_oct_ethtool_ops); cvm_oct_mdio_setup_device(dev); - dev->netdev_ops->ndo_set_mac_address(dev, mac); + dev->netdev_ops->ndo_set_mac_address(dev, &sa); dev->netdev_ops->ndo_change_mtu(dev, dev->mtu); /* @@ -620,6 +642,13 @@ static int __init cvm_oct_init_module(vo pr_notice("cavium-ethernet %s\n", OCTEON_ETHERNET_VERSION); + if (OCTEON_IS_MODEL(OCTEON_CN52XX)) + cvm_oct_mac_addr_offset = 2; /* First two are the mgmt ports. */ + else if (OCTEON_IS_MODEL(OCTEON_CN56XX)) + cvm_oct_mac_addr_offset = 1; /* First one is the mgmt port. */ + else + cvm_oct_mac_addr_offset = 0; + cvm_oct_proc_initialize(); cvm_oct_rx_initialize(); cvm_oct_configure_common_hw(); From ralf@linux-mips.org Thu Nov 5 18:57:11 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 05 Nov 2009 18:57:16 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:58911 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-FAIL) by ftp.linux-mips.org with ESMTP id S1493001AbZKERzn (ORCPT ); Thu, 5 Nov 2009 18:55:43 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id nA5Hv7bx024941; Thu, 5 Nov 2009 18:57:07 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id nA5Hv7gg024940; Thu, 5 Nov 2009 18:57:07 +0100 Message-Id: <20091105152702.125802957@linux-mips.org> User-Agent: quilt/0.47-1 Date: Thu, 05 Nov 2009 16:25:58 +0100 From: Ralf Baechle To: Linus Torvalds Cc: David Daney , Greg Kroah-Hartman , devel@driverdev.osuosl.org, linux-kernel@vger.kernel.org, linux-mips@linux-mips.org, netdev@vger.kernel.org Subject: [PATCH 2/6] Staging: Octeon: Use symbolic values for irq numbers. References: <20091105152555.227009519@linux-mips.org> Content-Disposition: inline; filename=0003.patch Lines: 29 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24703 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips From: David Daney In addition to being magic numbers, the irq number passed to free_irq is incorrect. We need to use the correct symbolic value instead. Signed-off-by: David Daney Cc: Greg Kroah-Hartman Cc: devel@driverdev.osuosl.org Cc: linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org Cc: netdev@vger.kernel.org Signed-off-by: Ralf Baechle drivers/staging/octeon/ethernet-spi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) Index: upstream-linus/drivers/staging/octeon/ethernet-spi.c =================================================================== --- upstream-linus.orig/drivers/staging/octeon/ethernet-spi.c +++ upstream-linus/drivers/staging/octeon/ethernet-spi.c @@ -317,6 +317,6 @@ void cvm_oct_spi_uninit(struct net_devic cvmx_write_csr(CVMX_SPXX_INT_MSK(interface), 0); cvmx_write_csr(CVMX_STXX_INT_MSK(interface), 0); } - free_irq(8 + 46, &number_spi_ports); + free_irq(OCTEON_IRQ_RML, &number_spi_ports); } } From ralf@linux-mips.org Thu Nov 5 18:57:34 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 05 Nov 2009 18:57:40 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:58922 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-FAIL) by ftp.linux-mips.org with ESMTP id S1493045AbZKERzp (ORCPT ); Thu, 5 Nov 2009 18:55:45 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id nA5Hv7Jk024949; Thu, 5 Nov 2009 18:57:07 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id nA5Hv7gp024948; Thu, 5 Nov 2009 18:57:07 +0100 Message-Id: <20091105152555.227009519@linux-mips.org> User-Agent: quilt/0.47-1 Date: Thu, 05 Nov 2009 16:25:55 +0100 From: Ralf Baechle To: Linus Torvalds Cc: David Daney , Atsushi Nemoto , Julia Lawall , Greg Kroah-Hartman , devel@driverdev.osuosl.org, David Brownell , spi-devel-general@lists.sourceforge.net, linux-kernel@vger.kernel.org, linux-mips@linux-mips.org, netdev@vger.kernel.org Subject: [PATCH 0/6] Misc driver fixes for 2.6.32 Lines: 14 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24704 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips This is a series of patches which o 1/6, 2/6, 3/6: Fixes for the Octeon ethernet driver in drivers/staging. The Octeon is a MIPS-based SOC so with permisson from Greg I'm merging these via the MIPS tree. o 4/6: A fix to a MIPS-specific SPI driver. Posted before, no comments were received. o 5/6: A fix to the resource allocation to the framebuffer of the MIPS- based SGI O2 and i686-based Visual Workstation. Also posted before, no comments were received. o 6/6: A fix to the serial driver for the BCM63xx which is a MIPS-based SOC. Ralf From David.Daney@caviumnetworks.com Thu Nov 5 20:35:20 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 05 Nov 2009 20:35:27 +0100 (CET) Received: from mail3.caviumnetworks.com ([12.108.191.235]:7923 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492681AbZKETfS (ORCPT ); Thu, 5 Nov 2009 20:35:18 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,5,4,7535) id ; Thu, 05 Nov 2009 11:35:04 -0800 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Thu, 5 Nov 2009 11:34:32 -0800 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Thu, 5 Nov 2009 11:34:32 -0800 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.2/8.14.2) with ESMTP id nA5JYRXs027907; Thu, 5 Nov 2009 11:34:27 -0800 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.2/8.14.2/Submit) id nA5JYQ1u027905; Thu, 5 Nov 2009 11:34:26 -0800 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: David Daney Subject: [PATCH] MIPS: Collect FPU emulator statistics per-CPU. Date: Thu, 5 Nov 2009 11:34:26 -0800 Message-Id: <1257449666-27880-1-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.6.0.6 X-OriginalArrivalTime: 05 Nov 2009 19:34:32.0290 (UTC) FILETIME=[FFA45420:01CA5E4E] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24705 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips On SMP systems, the collection of statistics can cause cache line bouncing in the lines associated with the counters. Also there are races incrementing the counters on multiple CPUs. To fix both problems, we collect the statistics in per-CPU variables, and add them up in the debugfs read operation. As a test I ran the LTP float_bessel test on a 12 CPU Octeon system. Without CONFIG_DEBUG_FS : 2602 seconds. With CONFIG_DEBUG_FS: 2640 seconds. With non-cpu-local atomic statistics: 14569 seconds. Signed-off-by: David Daney --- arch/mips/include/asm/fpu_emulator.h | 24 ++++++-- arch/mips/math-emu/cp1emu.c | 102 ++++++++++++++++++++-------------- arch/mips/math-emu/dsemul.c | 4 +- 3 files changed, 80 insertions(+), 50 deletions(-) diff --git a/arch/mips/include/asm/fpu_emulator.h b/arch/mips/include/asm/fpu_emulator.h index e518957..aecada6 100644 --- a/arch/mips/include/asm/fpu_emulator.h +++ b/arch/mips/include/asm/fpu_emulator.h @@ -25,17 +25,27 @@ #include #include +#include + +#ifdef CONFIG_DEBUG_FS struct mips_fpu_emulator_stats { - unsigned int emulated; - unsigned int loads; - unsigned int stores; - unsigned int cp1ops; - unsigned int cp1xops; - unsigned int errors; + local_t emulated; + local_t loads; + local_t stores; + local_t cp1ops; + local_t cp1xops; + local_t errors; }; -extern struct mips_fpu_emulator_stats fpuemustats; +DECLARE_PER_CPU(struct mips_fpu_emulator_stats, fpuemustats); + +#define MIPS_FPU_EMU_INC_STATS(M) \ + cpu_local_wrap(__local_inc(&__get_cpu_var(fpuemustats).M)) + +#else +#define MIPS_FPU_EMU_INC_STATS(M) do { } while (0) +#endif /* CONFIG_DEBUG_FS */ extern int mips_dsemul(struct pt_regs *regs, mips_instruction ir, unsigned long cpc); diff --git a/arch/mips/math-emu/cp1emu.c b/arch/mips/math-emu/cp1emu.c index 454b539..8f2f8e9 100644 --- a/arch/mips/math-emu/cp1emu.c +++ b/arch/mips/math-emu/cp1emu.c @@ -35,6 +35,7 @@ * better performance by compiling with -msoft-float! */ #include +#include #include #include @@ -68,7 +69,9 @@ static int fpux_emu(struct pt_regs *, /* Further private data for which no space exists in mips_fpu_struct */ -struct mips_fpu_emulator_stats fpuemustats; +#ifdef CONFIG_DEBUG_FS +DEFINE_PER_CPU(struct mips_fpu_emulator_stats, fpuemustats); +#endif /* Control registers */ @@ -209,7 +212,7 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx) unsigned int cond; if (get_user(ir, (mips_instruction __user *) xcp->cp0_epc)) { - fpuemustats.errors++; + MIPS_FPU_EMU_INC_STATS(errors); return SIGBUS; } @@ -240,7 +243,7 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx) return SIGILL; } if (get_user(ir, (mips_instruction __user *) emulpc)) { - fpuemustats.errors++; + MIPS_FPU_EMU_INC_STATS(errors); return SIGBUS; } /* __compute_return_epc() will have updated cp0_epc */ @@ -253,16 +256,16 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx) } emul: - fpuemustats.emulated++; + MIPS_FPU_EMU_INC_STATS(emulated); switch (MIPSInst_OPCODE(ir)) { case ldc1_op:{ u64 __user *va = (u64 __user *) (xcp->regs[MIPSInst_RS(ir)] + MIPSInst_SIMM(ir)); u64 val; - fpuemustats.loads++; + MIPS_FPU_EMU_INC_STATS(loads); if (get_user(val, va)) { - fpuemustats.errors++; + MIPS_FPU_EMU_INC_STATS(errors); return SIGBUS; } DITOREG(val, MIPSInst_RT(ir)); @@ -274,10 +277,10 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx) MIPSInst_SIMM(ir)); u64 val; - fpuemustats.stores++; + MIPS_FPU_EMU_INC_STATS(stores); DIFROMREG(val, MIPSInst_RT(ir)); if (put_user(val, va)) { - fpuemustats.errors++; + MIPS_FPU_EMU_INC_STATS(errors); return SIGBUS; } break; @@ -288,9 +291,9 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx) MIPSInst_SIMM(ir)); u32 val; - fpuemustats.loads++; + MIPS_FPU_EMU_INC_STATS(loads); if (get_user(val, va)) { - fpuemustats.errors++; + MIPS_FPU_EMU_INC_STATS(errors); return SIGBUS; } SITOREG(val, MIPSInst_RT(ir)); @@ -302,10 +305,10 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx) MIPSInst_SIMM(ir)); u32 val; - fpuemustats.stores++; + MIPS_FPU_EMU_INC_STATS(stores); SIFROMREG(val, MIPSInst_RT(ir)); if (put_user(val, va)) { - fpuemustats.errors++; + MIPS_FPU_EMU_INC_STATS(errors); return SIGBUS; } break; @@ -429,7 +432,7 @@ static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_struct *ctx) if (get_user(ir, (mips_instruction __user *) xcp->cp0_epc)) { - fpuemustats.errors++; + MIPS_FPU_EMU_INC_STATS(errors); return SIGBUS; } @@ -595,7 +598,7 @@ static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx, { unsigned rcsr = 0; /* resulting csr */ - fpuemustats.cp1xops++; + MIPS_FPU_EMU_INC_STATS(cp1xops); switch (MIPSInst_FMA_FFMT(ir)) { case s_fmt:{ /* 0 */ @@ -610,9 +613,9 @@ static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx, va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + xcp->regs[MIPSInst_FT(ir)]); - fpuemustats.loads++; + MIPS_FPU_EMU_INC_STATS(loads); if (get_user(val, va)) { - fpuemustats.errors++; + MIPS_FPU_EMU_INC_STATS(errors); return SIGBUS; } SITOREG(val, MIPSInst_FD(ir)); @@ -622,11 +625,11 @@ static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx, va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + xcp->regs[MIPSInst_FT(ir)]); - fpuemustats.stores++; + MIPS_FPU_EMU_INC_STATS(stores); SIFROMREG(val, MIPSInst_FS(ir)); if (put_user(val, va)) { - fpuemustats.errors++; + MIPS_FPU_EMU_INC_STATS(errors); return SIGBUS; } break; @@ -687,9 +690,9 @@ static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx, va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + xcp->regs[MIPSInst_FT(ir)]); - fpuemustats.loads++; + MIPS_FPU_EMU_INC_STATS(loads); if (get_user(val, va)) { - fpuemustats.errors++; + MIPS_FPU_EMU_INC_STATS(errors); return SIGBUS; } DITOREG(val, MIPSInst_FD(ir)); @@ -699,10 +702,10 @@ static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx, va = (void __user *) (xcp->regs[MIPSInst_FR(ir)] + xcp->regs[MIPSInst_FT(ir)]); - fpuemustats.stores++; + MIPS_FPU_EMU_INC_STATS(stores); DIFROMREG(val, MIPSInst_FS(ir)); if (put_user(val, va)) { - fpuemustats.errors++; + MIPS_FPU_EMU_INC_STATS(errors); return SIGBUS; } break; @@ -769,7 +772,7 @@ static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_struct *ctx, #endif } rv; /* resulting value */ - fpuemustats.cp1ops++; + MIPS_FPU_EMU_INC_STATS(cp1ops); switch (rfmt = (MIPSInst_FFMT(ir) & 0xf)) { case s_fmt:{ /* 0 */ union { @@ -1240,7 +1243,7 @@ int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx, prevepc = xcp->cp0_epc; if (get_user(insn, (mips_instruction __user *) xcp->cp0_epc)) { - fpuemustats.errors++; + MIPS_FPU_EMU_INC_STATS(errors); return SIGBUS; } if (insn == 0) @@ -1276,33 +1279,50 @@ int fpu_emulator_cop1Handler(struct pt_regs *xcp, struct mips_fpu_struct *ctx, } #ifdef CONFIG_DEBUG_FS + +static int fpuemu_stat_get(void *data, u64 *val) +{ + int cpu; + unsigned long sum = 0; + for_each_online_cpu(cpu) { + struct mips_fpu_emulator_stats *ps; + local_t *pv; + ps = &per_cpu(fpuemustats, cpu); + pv = (void *)ps + (unsigned long)data; + sum += local_read(pv); + } + *val = sum; + return 0; +} +DEFINE_SIMPLE_ATTRIBUTE(fops_fpuemu_stat, fpuemu_stat_get, NULL, "%llu\n"); + extern struct dentry *mips_debugfs_dir; static int __init debugfs_fpuemu(void) { struct dentry *d, *dir; - int i; - static struct { - const char *name; - unsigned int *v; - } vars[] __initdata = { - { "emulated", &fpuemustats.emulated }, - { "loads", &fpuemustats.loads }, - { "stores", &fpuemustats.stores }, - { "cp1ops", &fpuemustats.cp1ops }, - { "cp1xops", &fpuemustats.cp1xops }, - { "errors", &fpuemustats.errors }, - }; if (!mips_debugfs_dir) return -ENODEV; dir = debugfs_create_dir("fpuemustats", mips_debugfs_dir); if (!dir) return -ENOMEM; - for (i = 0; i < ARRAY_SIZE(vars); i++) { - d = debugfs_create_u32(vars[i].name, S_IRUGO, dir, vars[i].v); - if (!d) - return -ENOMEM; - } + +#define FPU_STAT_CREATE(M) \ + do { \ + d = debugfs_create_file(#M , S_IRUGO, dir, \ + (void *)offsetof(struct mips_fpu_emulator_stats, M), \ + &fops_fpuemu_stat); \ + if (!d) \ + return -ENOMEM; \ + } while (0) + + FPU_STAT_CREATE(emulated); + FPU_STAT_CREATE(loads); + FPU_STAT_CREATE(stores); + FPU_STAT_CREATE(cp1ops); + FPU_STAT_CREATE(cp1xops); + FPU_STAT_CREATE(errors); + return 0; } __initcall(debugfs_fpuemu); diff --git a/arch/mips/math-emu/dsemul.c b/arch/mips/math-emu/dsemul.c index df7b9d9..36d975a 100644 --- a/arch/mips/math-emu/dsemul.c +++ b/arch/mips/math-emu/dsemul.c @@ -98,7 +98,7 @@ int mips_dsemul(struct pt_regs *regs, mips_instruction ir, unsigned long cpc) err |= __put_user(cpc, &fr->epc); if (unlikely(err)) { - fpuemustats.errors++; + MIPS_FPU_EMU_INC_STATS(errors); return SIGBUS; } @@ -136,7 +136,7 @@ int do_dsemulret(struct pt_regs *xcp) err |= __get_user(cookie, &fr->cookie); if (unlikely(err || (insn != BREAK_MATH) || (cookie != BD_COOKIE))) { - fpuemustats.errors++; + MIPS_FPU_EMU_INC_STATS(errors); return 0; } -- 1.6.0.6 From David.Daney@caviumnetworks.com Thu Nov 5 20:40:53 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 05 Nov 2009 20:40:59 +0100 (CET) Received: from mail3.caviumnetworks.com ([12.108.191.235]:8070 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492952AbZKETkx (ORCPT ); Thu, 5 Nov 2009 20:40:53 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,5,4,7535) id ; Thu, 05 Nov 2009 11:39:24 -0800 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Thu, 5 Nov 2009 11:38:34 -0800 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Thu, 5 Nov 2009 11:38:34 -0800 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.2/8.14.2) with ESMTP id nA5JcWVi028004; Thu, 5 Nov 2009 11:38:32 -0800 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.2/8.14.2/Submit) id nA5JcWD6028002; Thu, 5 Nov 2009 11:38:32 -0800 From: David Daney To: ralf@linux-mips.org, linux-mips@linux-mips.org, netdev@vger.kernel.org Cc: David Daney Subject: [PATCH] netdev: Fix compile error in Octeon MGMT driver. Date: Thu, 5 Nov 2009 11:38:32 -0800 Message-Id: <1257449912-27978-1-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.6.0.6 X-OriginalArrivalTime: 05 Nov 2009 19:38:34.0356 (UTC) FILETIME=[8FECAB40:01CA5E4F] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24706 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Explicitly include linux/capability.h. Under some configurations it wasn't being indirectly included. Signed-off-by: David Daney --- This fixes a minor problem for the (already approved) patches that Ralf has queued for 2.6.33. It should probably be added to Ralf's queue. drivers/net/octeon/octeon_mgmt.c | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/drivers/net/octeon/octeon_mgmt.c b/drivers/net/octeon/octeon_mgmt.c index 83a636d..050538b 100644 --- a/drivers/net/octeon/octeon_mgmt.c +++ b/drivers/net/octeon/octeon_mgmt.c @@ -6,6 +6,7 @@ * Copyright (C) 2009 Cavium Networks */ +#include #include #include #include -- 1.6.0.6 From ralf@linux-mips.org Thu Nov 5 21:20:18 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 05 Nov 2009 21:20:20 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:59792 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-FAIL) by ftp.linux-mips.org with ESMTP id S1493049AbZKEUUS (ORCPT ); Thu, 5 Nov 2009 21:20:18 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id nA5KLf9R032715; Thu, 5 Nov 2009 21:21:42 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id nA5KLe8C032712; Thu, 5 Nov 2009 21:21:40 +0100 Date: Thu, 5 Nov 2009 21:21:40 +0100 From: Ralf Baechle To: David Daney Cc: linux-mips@linux-mips.org Subject: Re: [PATCH] MIPS: Collect FPU emulator statistics per-CPU. Message-ID: <20091105202140.GA26616@linux-mips.org> References: <1257449666-27880-1-git-send-email-ddaney@caviumnetworks.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1257449666-27880-1-git-send-email-ddaney@caviumnetworks.com> User-Agent: Mutt/1.5.19 (2009-01-05) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24707 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Thu, Nov 05, 2009 at 11:34:26AM -0800, David Daney wrote: Thanks, queued for 2.6.33. Ralf From ralf@linux-mips.org Thu Nov 5 21:44:18 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 05 Nov 2009 21:44:21 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:34543 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-FAIL) by ftp.linux-mips.org with ESMTP id S1493077AbZKEUoS (ORCPT ); Thu, 5 Nov 2009 21:44:18 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id nA5KjlKp012660; Thu, 5 Nov 2009 21:45:48 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id nA5KjlPW012658; Thu, 5 Nov 2009 21:45:47 +0100 Date: Thu, 5 Nov 2009 21:45:47 +0100 From: Ralf Baechle To: David Daney Cc: linux-mips@linux-mips.org, netdev@vger.kernel.org Subject: Re: [PATCH] netdev: Fix compile error in Octeon MGMT driver. Message-ID: <20091105204547.GA10292@linux-mips.org> References: <1257449912-27978-1-git-send-email-ddaney@caviumnetworks.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1257449912-27978-1-git-send-email-ddaney@caviumnetworks.com> User-Agent: Mutt/1.5.19 (2009-01-05) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24708 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Thu, Nov 05, 2009 at 11:38:32AM -0800, David Daney wrote: > Explicitly include linux/capability.h. Under some configurations it > wasn't being indirectly included. > > Signed-off-by: David Daney > --- > This fixes a minor problem for the (already approved) patches that > Ralf has queued for 2.6.33. It should probably be added to Ralf's > queue. > > drivers/net/octeon/octeon_mgmt.c | 1 + > 1 files changed, 1 insertions(+), 0 deletions(-) Folded into the existing patch. Thanks! Ralf From wuzhangjin@gmail.com Fri Nov 6 06:39:57 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 06 Nov 2009 06:40:04 +0100 (CET) Received: from mail-pw0-f45.google.com ([209.85.160.45]:43061 "EHLO mail-pw0-f45.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1491872AbZKFFj5 (ORCPT ); Fri, 6 Nov 2009 06:39:57 +0100 Received: by pwi15 with SMTP id 15so475225pwi.24 for ; Thu, 05 Nov 2009 21:39:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:subject:from:reply-to:to:cc :in-reply-to:references:content-type:organization:date:message-id :mime-version:x-mailer:content-transfer-encoding; bh=y0wRPV3FQS2QYBgxai75ftrOjszmsEXB8HtF9ghHwD4=; b=iCXAlY/LM0gZ7E1Klo9xUyGVsxh2IHoERwbdonuKpFdEbMVc09Y/tsjWsl5w7da7Sl dtZkzgFVNJ2Z20ky0KdA7qChvavaWHe3fSi2BitjZDXquPGer3KP3H8ZOBttFMaNgoZM 6LWsweLGA4v2OKrJRVi74euMyblNt6bf0f3Io= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=subject:from:reply-to:to:cc:in-reply-to:references:content-type :organization:date:message-id:mime-version:x-mailer :content-transfer-encoding; b=OtQ07kUJxKaBrjszk6uL0XQOMsDqnzeAVTJUt5t5hzVkMzLt42WAm+B2CbTC9bG2ld W9Va6KI4YHBuOpQjZqxPUVZcYL+l9/0lgw+PMlreff3pUPQv3c2NWOQg6PLjBLlDz6Lb 4i3tHg27PMPJpiG7xl+o/QqAWzmwD+edcrvyQ= Received: by 10.114.19.30 with SMTP id 30mr6113627was.134.1257485988509; Thu, 05 Nov 2009 21:39:48 -0800 (PST) Received: from ?172.16.2.101? ([222.92.8.142]) by mx.google.com with ESMTPS id 23sm1565058pzk.0.2009.11.05.21.39.41 (version=TLSv1/SSLv3 cipher=RC4-MD5); Thu, 05 Nov 2009 21:39:47 -0800 (PST) Subject: Re: [PATCH -queue v0 4/6] [loongson] add basic fuloong2f support From: Wu Zhangjin Reply-To: wuzhangjin@gmail.com To: Ralf Baechle Cc: linux-mips@linux-mips.org, LKML , huhb@lemote.com, yanh@lemote.com, Zhang Le , Thomas Gleixner , Nicholas Mc Guire , zhangfx@lemote.com, liujl@lemote.com In-Reply-To: <20091105131603.GA18232@linux-mips.org> References: <0f805f7d12c5a7cbcc125ba4a1b70113ec2047a6.1257325319.git.wuzhangjin@gmail.com> <20091105131603.GA18232@linux-mips.org> Content-Type: text/plain; charset="UTF-8" Organization: DSLab, Lanzhou University, China Date: Fri, 06 Nov 2009 13:39:44 +0800 Message-ID: <1257485984.2299.21.camel@falcon.domain.org> Mime-Version: 1.0 X-Mailer: Evolution 2.28.1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24709 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips On Thu, 2009-11-05 at 14:16 +0100, Ralf Baechle wrote: > On Wed, Nov 04, 2009 at 05:05:47PM +0800, Wu Zhangjin wrote: > > > diff --git a/arch/mips/loongson/fuloong-2f/irq.c b/arch/mips/loongson/fuloong-2f/irq.c > > new file mode 100644 > > index 0000000..22c45fd > > --- /dev/null > > +++ b/arch/mips/loongson/fuloong-2f/irq.c > > @@ -0,0 +1,114 @@ > > +/* > > + * Copyright (C) 2007 Lemote Inc. > > + * Author: Fuxin Zhang, zhangfx@lemote.com > > + * > > + * This program is free software; you can redistribute it and/or modify it > > + * under the terms of the GNU General Public License as published by the > > + * Free Software Foundation; either version 2 of the License, or (at your > > + * option) any later version. > > + */ > > + > > +#include > > + > > +#include > > +#include > > +#include > > + > > +#include > > +#include > > + > > +#define LOONGSON_TIMER_IRQ (MIPS_CPU_IRQ_BASE + 7) /* cpu timer */ > > +#define LOONGSON_PERFCNT_IRQ (MIPS_CPU_IRQ_BASE + 6) /* cpu perf counter */ > > +#define LOONGSON_NORTH_BRIDGE_IRQ (MIPS_CPU_IRQ_BASE + 6) /* bonito */ > > +#define LOONGSON_UART_IRQ (MIPS_CPU_IRQ_BASE + 3) /* cpu serial port */ > > +#define LOONGSON_SOUTH_BRIDGE_IRQ (MIPS_CPU_IRQ_BASE + 2) /* i8259 */ > > + > > +#define LOONGSON_INT_BIT_INT0 (1 << 11) > > +#define LOONGSON_INT_BIT_INT1 (1 << 12) > > + > > +static int mach_i8259_irq(void) > > +{ > > + int irq, isr, imr; > > + > > + irq = -1; > > + > > + if ((LOONGSON_INTISR & LOONGSON_INTEN) & LOONGSON_INT_BIT_INT0) { > > + imr = inb(0x21) | (inb(0xa1) << 8); > > + isr = inb(0x20) | (inb(0xa0) << 8); > > + isr &= ~0x4; /* irq2 for cascade */ > > + isr &= ~imr; > > + irq = ffs(isr) - 1; > > + } > > Any reason why you're not using i8259_irq() from here? > That function not only gets the locking right, it also minimizes the number > of accesses to the i8259 - which even on modern silicon can be stuningly > slow. > Hi, Ralf Just asked Yanhua, He told me there is a bug in cs5536, if using the i8259_irq() directly, we can not get the irq. and just tried it, the kernel hang on booting. Regards, Wu Zhangjin From ralf@linux-mips.org Fri Nov 6 09:29:28 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 06 Nov 2009 09:29:31 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:45015 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-FAIL) by ftp.linux-mips.org with ESMTP id S1492224AbZKFI32 (ORCPT ); Fri, 6 Nov 2009 09:29:28 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id nA68UlEa028644; Fri, 6 Nov 2009 09:30:48 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id nA68UgG2028640; Fri, 6 Nov 2009 09:30:42 +0100 Date: Fri, 6 Nov 2009 09:30:42 +0100 From: Ralf Baechle To: Wu Zhangjin Cc: linux-mips@linux-mips.org, LKML , huhb@lemote.com, yanh@lemote.com, Zhang Le , Thomas Gleixner , Nicholas Mc Guire , zhangfx@lemote.com, liujl@lemote.com Subject: Re: [PATCH -queue v0 4/6] [loongson] add basic fuloong2f support Message-ID: <20091106083042.GA17723@linux-mips.org> References: <0f805f7d12c5a7cbcc125ba4a1b70113ec2047a6.1257325319.git.wuzhangjin@gmail.com> <20091105131603.GA18232@linux-mips.org> <1257485984.2299.21.camel@falcon.domain.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1257485984.2299.21.camel@falcon.domain.org> User-Agent: Mutt/1.5.19 (2009-01-05) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24710 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Fri, Nov 06, 2009 at 01:39:44PM +0800, Wu Zhangjin wrote: > > > + if ((LOONGSON_INTISR & LOONGSON_INTEN) & LOONGSON_INT_BIT_INT0) { > > > + imr = inb(0x21) | (inb(0xa1) << 8); > > > + isr = inb(0x20) | (inb(0xa0) << 8); > > > + isr &= ~0x4; /* irq2 for cascade */ > > > + isr &= ~imr; > > > + irq = ffs(isr) - 1; > > > + } > > > > Any reason why you're not using i8259_irq() from here? > > That function not only gets the locking right, it also minimizes the number > > of accesses to the i8259 - which even on modern silicon can be stuningly > > slow. > Just asked Yanhua, He told me there is a bug in cs5536, if using the > i8259_irq() directly, we can not get the irq. and just tried it, the > kernel hang on booting. Wonderful. Even 30 years after it was built there are still new i8259 bugs :-) This is probably worth a comment in the code. Ralf From wuzhangjin@gmail.com Fri Nov 6 09:34:50 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 06 Nov 2009 09:34:56 +0100 (CET) Received: from mail-pw0-f45.google.com ([209.85.160.45]:55325 "EHLO mail-pw0-f45.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492199AbZKFIeu (ORCPT ); Fri, 6 Nov 2009 09:34:50 +0100 Received: by pwi15 with SMTP id 15so543284pwi.24 for ; Fri, 06 Nov 2009 00:34:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:subject:from:reply-to:to:cc :in-reply-to:references:content-type:organization:date:message-id :mime-version:x-mailer:content-transfer-encoding; bh=SICRChQB/BsL72aoh0mkO5ZKN4SCJTldKS+7XYaaQpk=; b=S/fqkumfaljk47dV+Z81IGK40dDzzFhSUBiTan7qd4OFts1PL1MwVTPdmTkpydLA47 ExLO6UswPXH5dpqaJO5ESuRGi6AU3q3egeqRtR/JY2okU5acPawXi5A2+8vls32W1l8L 27VSOk5qsGlSQtsiJcOSH9152X2GWEPVQV0CI= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=subject:from:reply-to:to:cc:in-reply-to:references:content-type :organization:date:message-id:mime-version:x-mailer :content-transfer-encoding; b=fQkAQYdg/Gp+VLroKUEVJGTzQQ9iPZve2cK2Rf+g4doWjVsjj6JIN+pMPSUlaViQh0 I8503DJKn1EqgrHLrqwD8zLO//8Z2BnHsOMaqAWg3h+iWGczqZnt2943PFB7PBJDlmxi YAIevvNgc/kaQuTpPUZo49JtV8ue6I5L3WfpE= Received: by 10.115.26.13 with SMTP id d13mr6349998waj.210.1257496483416; Fri, 06 Nov 2009 00:34:43 -0800 (PST) Received: from ?172.16.2.101? ([222.92.8.142]) by mx.google.com with ESMTPS id 22sm1626060pzk.14.2009.11.06.00.34.38 (version=TLSv1/SSLv3 cipher=RC4-MD5); Fri, 06 Nov 2009 00:34:43 -0800 (PST) Subject: Re: [PATCH -queue v0 4/6] [loongson] add basic fuloong2f support From: Wu Zhangjin Reply-To: wuzhangjin@gmail.com To: Ralf Baechle Cc: linux-mips@linux-mips.org, LKML , huhb@lemote.com, yanh@lemote.com, Zhang Le , Thomas Gleixner , Nicholas Mc Guire , zhangfx@lemote.com, liujl@lemote.com In-Reply-To: <20091105131603.GA18232@linux-mips.org> References: <0f805f7d12c5a7cbcc125ba4a1b70113ec2047a6.1257325319.git.wuzhangjin@gmail.com> <20091105131603.GA18232@linux-mips.org> Content-Type: text/plain; charset="UTF-8" Organization: DSLab, Lanzhou University, China Date: Fri, 06 Nov 2009 16:34:41 +0800 Message-ID: <1257496481.2299.30.camel@falcon.domain.org> Mime-Version: 1.0 X-Mailer: Evolution 2.28.1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24711 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips Hi, On Thu, 2009-11-05 at 14:16 +0100, Ralf Baechle wrote: [...] > > +static int mach_i8259_irq(void) > > +{ > > + int irq, isr, imr; > > + > > + irq = -1; > > + > > + if ((LOONGSON_INTISR & LOONGSON_INTEN) & LOONGSON_INT_BIT_INT0) { > > + imr = inb(0x21) | (inb(0xa1) << 8); > > + isr = inb(0x20) | (inb(0xa0) << 8); > > + isr &= ~0x4; /* irq2 for cascade */ > > + isr &= ~imr; > > + irq = ffs(isr) - 1; > > + } > > Any reason why you're not using i8259_irq() from here? > That function not only gets the locking right, it also minimizes the number > of accesses to the i8259 - which even on modern silicon can be stuningly > slow. Just checked it again, seems we can only access the ISR registers, but even if with this restriction, we can also optimize it to minimize the number of accesses to the i8259, this is the new version: + isr = inb(PIC_MASTER_CMD) & + ~inb(PIC_MASTER_IMR) & ~(1 << PIC_CASCADE_IR); + if (!isr) + isr = (inb(PIC_SLAVE_CMD) & ~inb(PIC_SLAVE_IMR)) << 8; Will resend it with this version. Thanks, Wu Zhangjin From wuzhangjin@gmail.com Fri Nov 6 11:06:11 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 06 Nov 2009 11:06:18 +0100 (CET) Received: from mail-pw0-f45.google.com ([209.85.160.45]:58053 "EHLO mail-pw0-f45.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492246AbZKFKGL (ORCPT ); Fri, 6 Nov 2009 11:06:11 +0100 Received: by pwi15 with SMTP id 15so578114pwi.24 for ; Fri, 06 Nov 2009 02:06:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:subject:from:reply-to:to:cc :in-reply-to:references:content-type:organization:date:message-id :mime-version:x-mailer:content-transfer-encoding; bh=Oh5P0bl7b1wMO+JvV6GC1dL0R3NGWWphhs3nCYJHBCc=; b=rmgq678u8I9xflj5keV5aRHNxzIKjXEIRF6F2bpMqcfmk+Iofsazio+ajvEFiGTeft UnTlqeO48RwR/z9WgYquaP2Q0hJSt5Wm9BNSvTzPlBIUO9VvRH9WKxBT/6XeXgn4vWlu j77hW9dUtrWw0VDYhETN/+5SBrDTCDFOAdIi4= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=subject:from:reply-to:to:cc:in-reply-to:references:content-type :organization:date:message-id:mime-version:x-mailer :content-transfer-encoding; b=xfV/sDxlZ/ReG1Hk98JXSFPYSKZFU/USVXPgSV3zt0HvAKz9kFUBiud/vwcFduGsy5 SIhwr2AuwkO1nPV812qalHyhxfqkxsvdEETY+YIzeie4C2n0OZiOG96DY0nbPz7TmHjk lc51S9qa/dCdmoGWr8lWFoNdmSAATTE8ClahA= Received: by 10.114.164.20 with SMTP id m20mr6377197wae.216.1257501963140; Fri, 06 Nov 2009 02:06:03 -0800 (PST) Received: from ?172.16.2.101? ([222.92.8.142]) by mx.google.com with ESMTPS id 23sm975954pxi.13.2009.11.06.02.05.58 (version=TLSv1/SSLv3 cipher=RC4-MD5); Fri, 06 Nov 2009 02:06:02 -0800 (PST) Subject: Re: [PATCH -queue v0 4/6] [loongson] add basic fuloong2f support From: Wu Zhangjin Reply-To: wuzhangjin@gmail.com To: Ralf Baechle Cc: linux-mips@linux-mips.org, LKML , huhb@lemote.com, yanh@lemote.com, Zhang Le , Thomas Gleixner , Nicholas Mc Guire , zhangfx@lemote.com, liujl@lemote.com In-Reply-To: <20091106083042.GA17723@linux-mips.org> References: <0f805f7d12c5a7cbcc125ba4a1b70113ec2047a6.1257325319.git.wuzhangjin@gmail.com> <20091105131603.GA18232@linux-mips.org> <1257485984.2299.21.camel@falcon.domain.org> <20091106083042.GA17723@linux-mips.org> Content-Type: text/plain; charset="UTF-8" Organization: DSLab, Lanzhou University, China Date: Fri, 06 Nov 2009 18:05:59 +0800 Message-ID: <1257501959.2299.52.camel@falcon.domain.org> Mime-Version: 1.0 X-Mailer: Evolution 2.28.1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24712 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips Hi, Ralf I will split the coming patchset as three parts? 1. fixes of old support 2. loongson2f support 3. lemote 2f family machines support is this okay? Regards, Wu Zhangjin On Fri, 2009-11-06 at 09:30 +0100, Ralf Baechle wrote: > On Fri, Nov 06, 2009 at 01:39:44PM +0800, Wu Zhangjin wrote: > > > > > + if ((LOONGSON_INTISR & LOONGSON_INTEN) & LOONGSON_INT_BIT_INT0) { > > > > + imr = inb(0x21) | (inb(0xa1) << 8); > > > > + isr = inb(0x20) | (inb(0xa0) << 8); > > > > + isr &= ~0x4; /* irq2 for cascade */ > > > > + isr &= ~imr; > > > > + irq = ffs(isr) - 1; > > > > + } > > > > > > Any reason why you're not using i8259_irq() from here? > > > That function not only gets the locking right, it also minimizes the number > > > of accesses to the i8259 - which even on modern silicon can be stuningly > > > slow. > > > Just asked Yanhua, He told me there is a bug in cs5536, if using the > > i8259_irq() directly, we can not get the irq. and just tried it, the > > kernel hang on booting. > > Wonderful. Even 30 years after it was built there are still new i8259 > bugs :-) > > This is probably worth a comment in the code. > > Ralf From wuzhangjin@gmail.com Fri Nov 6 11:35:52 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 06 Nov 2009 11:35:58 +0100 (CET) Received: from mail-px0-f188.google.com ([209.85.216.188]:41883 "EHLO mail-px0-f188.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492426AbZKFKfw (ORCPT ); Fri, 6 Nov 2009 11:35:52 +0100 Received: by pxi26 with SMTP id 26so296415pxi.21 for ; Fri, 06 Nov 2009 02:35:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer; bh=k+VZxu0sDOXgMoFq3ybbLXBZ9l5nVR5G6oBCuIpW3wk=; b=qsQQM4Qhlmwd2csOHcdeNj+XOVtlcxA/yVjXAjb0sT11zDdPG0GNK7mjrJh3vy8DU5 r8v7bhaj1+b24Qy/p0g9BqgYPTxhRMpjpl8EZeg0FjjTfGlC7Iy8SaJppAZ3GQg4vX8t 3sZsprutw9XzLVjOyUIYFGJZtYyxXNRyugqEo= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer; b=smFOcoCh4p7sfm72ycEZnrxfns+IHp5jPY3ZTs/1sPPigAo1lSN4+9/YLK7NI66GTJ h8OhaTqg0Pq303Ene4s5osNbY8C30u1YNvN7kJKKqTcBbzOPBfTO0Vcxodni3XBnFaZm z78xH7DWXlJmnUvA/fzog4To8PDQNA0t+WSSY= Received: by 10.115.132.12 with SMTP id j12mr6496486wan.121.1257503744557; Fri, 06 Nov 2009 02:35:44 -0800 (PST) Received: from localhost.localdomain ([222.92.8.142]) by mx.google.com with ESMTPS id 22sm1679219pzk.10.2009.11.06.02.35.42 (version=TLSv1/SSLv3 cipher=RC4-MD5); Fri, 06 Nov 2009 02:35:44 -0800 (PST) From: Wu Zhangjin To: Ralf Baechle Cc: linux-mips@linux-mips.org, Wu Zhangjin Subject: [PATCH -queue 0/2] cleanups of loongson support Date: Fri, 6 Nov 2009 18:35:32 +0800 Message-Id: X-Mailer: git-send-email 1.6.2.1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24713 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips The next two patches cleanup the machtype support and the serial port support, which will help to the coming support to share the same kernel image among different loongson2f family machines made by Lemote. Wu Zhangjin (2): [loongson] Cleanup the machtype support [loongson] Cleanup the serial port support arch/mips/include/asm/mach-loongson/loongson.h | 4 +++ arch/mips/include/asm/mach-loongson/machine.h | 2 - arch/mips/loongson/common/Makefile | 2 +- arch/mips/loongson/common/cmdline.c | 4 ++- arch/mips/loongson/common/early_printk.c | 11 +++++--- arch/mips/loongson/common/init.c | 11 +++++--- arch/mips/loongson/common/machtype.c | 17 +++++++----- arch/mips/loongson/common/serial.c | 15 +++++----- arch/mips/loongson/common/uart_base.c | 34 ++++++++++++++++++++++++ 9 files changed, 74 insertions(+), 26 deletions(-) create mode 100644 arch/mips/loongson/common/uart_base.c From wuzhangjin@gmail.com Fri Nov 6 11:36:17 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 06 Nov 2009 11:36:24 +0100 (CET) Received: from mail-px0-f188.google.com ([209.85.216.188]:56321 "EHLO mail-px0-f188.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492446AbZKFKfy (ORCPT ); Fri, 6 Nov 2009 11:35:54 +0100 Received: by pxi26 with SMTP id 26so296442pxi.21 for ; Fri, 06 Nov 2009 02:35:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer:in-reply-to:references:in-reply-to:references; bh=dHdF0lr83O7PBM9D1BXChl4X9xhnovCCOBawyPlNbeg=; b=taq501b9LMLRAYjKfy5E5HH1qjxLa97SNAdKg+DY/Pwt9fNDgTsnTmHpSbTlG4eiy+ mHvyBfC12h4kh3U0m08fTJ5SpWKA60J75omutV6TbyT9vs4MkQ2TV9luyYOFzAM1x4z1 aawGk/Vde1QWAG+bt7k67qd+jedDDNEdQyBx0= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; b=QqDn68oJ3kvy5ZDRfdq2KxCFdkkMwPa9DZr5HhOM6rgjxcUD/O63MEbj1vXYcz2hoe Te8vxaXGkwanq64MpaqJEi/1YLbQWaym2pAVAfuOZoxyieDT1OJ5ohlBER2qcglT2X+4 jC+Pf3jRMGieSrp2W/6V1MeXQqV1s+RvMQPt4= Received: by 10.115.132.5 with SMTP id j5mr6459474wan.129.1257503747123; Fri, 06 Nov 2009 02:35:47 -0800 (PST) Received: from localhost.localdomain ([222.92.8.142]) by mx.google.com with ESMTPS id 22sm1679219pzk.10.2009.11.06.02.35.44 (version=TLSv1/SSLv3 cipher=RC4-MD5); Fri, 06 Nov 2009 02:35:46 -0800 (PST) From: Wu Zhangjin To: Ralf Baechle Cc: linux-mips@linux-mips.org, Wu Zhangjin Subject: [PATCH -queue 1/2] [loongson] Cleanup the machtype support Date: Fri, 6 Nov 2009 18:35:33 +0800 Message-Id: <905f2e99289a26852bf8d413f0e56ef2235cac99.1257503696.git.wuzhangjin@gmail.com> X-Mailer: git-send-email 1.6.2.1 In-Reply-To: References: In-Reply-To: References: Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24714 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips We need to initialize mips_machtype as early as we can, So, we can choose corresponding code for different machines via it. This patch moves the initialization of mips_machtype to prom_init(). Signed-off-by: Wu Zhangjin --- arch/mips/include/asm/mach-loongson/loongson.h | 1 + arch/mips/loongson/common/cmdline.c | 4 +++- arch/mips/loongson/common/machtype.c | 17 ++++++++++------- 3 files changed, 14 insertions(+), 8 deletions(-) diff --git a/arch/mips/include/asm/mach-loongson/loongson.h b/arch/mips/include/asm/mach-loongson/loongson.h index e6869aa..efb2344 100644 --- a/arch/mips/include/asm/mach-loongson/loongson.h +++ b/arch/mips/include/asm/mach-loongson/loongson.h @@ -29,6 +29,7 @@ extern unsigned long memsize, highmemsize; /* loongson-specific command line, env and memory initialization */ extern void __init prom_init_memory(void); extern void __init prom_init_cmdline(void); +extern void __init prom_init_machtype(void); extern void __init prom_init_env(void); /* irq operation functions */ diff --git a/arch/mips/loongson/common/cmdline.c b/arch/mips/loongson/common/cmdline.c index 75f1b24..7ad47f2 100644 --- a/arch/mips/loongson/common/cmdline.c +++ b/arch/mips/loongson/common/cmdline.c @@ -9,7 +9,7 @@ * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology * Author: Fuxin Zhang, zhangfx@lemote.com * - * Copyright (C) 2009 Lemote Inc. & Insititute of Computing Technology + * Copyright (C) 2009 Lemote Inc. * Author: Wu Zhangjin, wuzj@lemote.com * * This program is free software; you can redistribute it and/or modify it @@ -49,4 +49,6 @@ void __init prom_init_cmdline(void) strcat(arcs_cmdline, " console=ttyS0,115200"); if ((strstr(arcs_cmdline, "root=")) == NULL) strcat(arcs_cmdline, " root=/dev/hda1"); + + prom_init_machtype(); } diff --git a/arch/mips/loongson/common/machtype.c b/arch/mips/loongson/common/machtype.c index 7b34824..87b502f 100644 --- a/arch/mips/loongson/common/machtype.c +++ b/arch/mips/loongson/common/machtype.c @@ -27,24 +27,27 @@ static const char *system_types[] = { const char *get_system_type(void) { - if (mips_machtype == MACH_UNKNOWN) - mips_machtype = LOONGSON_MACHTYPE; - return system_types[mips_machtype]; } -static __init int machtype_setup(char *str) +void __init prom_init_machtype(void) { + char *str, *p; int machtype = MACH_LEMOTE_FL2E; + mips_machtype = LOONGSON_MACHTYPE; + + str = strstr(arcs_cmdline, "machtype="); if (!str) - return -EINVAL; + return; + str += strlen("machtype="); + p = strstr(str, " "); + if (p) + *p++ = '\0'; for (; system_types[machtype]; machtype++) if (strstr(system_types[machtype], str)) { mips_machtype = machtype; break; } - return 0; } -__setup("machtype=", machtype_setup); -- 1.6.2.1 From wuzhangjin@gmail.com Fri Nov 6 11:36:42 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 06 Nov 2009 11:36:50 +0100 (CET) Received: from mail-pz0-f194.google.com ([209.85.222.194]:33306 "EHLO mail-pz0-f194.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492505AbZKFKgB (ORCPT ); Fri, 6 Nov 2009 11:36:01 +0100 Received: by pzk32 with SMTP id 32so659676pzk.21 for ; Fri, 06 Nov 2009 02:35:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer:in-reply-to:references:in-reply-to:references; bh=X0EGewEwPMN5TAxw7vHSJokO/yM+AoSrwltqkskO95E=; b=xgbbvFYYgaQXnyYFxE6AWT4ATqa9zA8kSfTbrlpK6GC2EjVYy0yhVnxM7ha2S8tgFZ tGtAAjCIEuHPhIcwViCotsIziqZE0IlZHl22O0xVz7mnKnArg17kozRAq4YlKnDqtVIl xdUq6gMmB/rBRasQvgxDcXrtt7z/JmuDoSu4A= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; b=oUdBm0ZO5PaJPWa7DiEhnXR6OsUBl/zaoDKPHvZdfds8Em7Ecw6yj99FpgZdTG6eNy 6JjnQxbkb/r8xPJxjYq/wycn6e0W4BDqRXHhaUkCL1yqORrERHySujGoc20jN2s3I/jB phMfNPwZYx5THfDhAxFVuH0pmTyg/wQdtUUuY= Received: by 10.114.242.2 with SMTP id p2mr6508546wah.153.1257503753947; Fri, 06 Nov 2009 02:35:53 -0800 (PST) Received: from localhost.localdomain ([222.92.8.142]) by mx.google.com with ESMTPS id 22sm1679219pzk.10.2009.11.06.02.35.48 (version=TLSv1/SSLv3 cipher=RC4-MD5); Fri, 06 Nov 2009 02:35:53 -0800 (PST) From: Wu Zhangjin To: Ralf Baechle Cc: linux-mips@linux-mips.org, Wu Zhangjin Subject: [PATCH -queue 2/2] [loongson] Cleanup the serial port support Date: Fri, 6 Nov 2009 18:35:34 +0800 Message-Id: X-Mailer: git-send-email 1.6.2.1 In-Reply-To: <905f2e99289a26852bf8d413f0e56ef2235cac99.1257503696.git.wuzhangjin@gmail.com> References: <905f2e99289a26852bf8d413f0e56ef2235cac99.1257503696.git.wuzhangjin@gmail.com> In-Reply-To: References: Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24715 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips To share the same kernel image amon different machines, we have added the machtype command line support. but in the old serial port implementation, we have hardcoded the uart base address as a macro in machine.h, which will break the intention of machtype. this patch fixes it, and also move the initialization of uart base address to uart_base.c to avoid remapping twice for early_printk.c and serial.c. Signed-off-by: Wu Zhangjin --- arch/mips/include/asm/mach-loongson/loongson.h | 3 ++ arch/mips/include/asm/mach-loongson/machine.h | 2 - arch/mips/loongson/common/Makefile | 2 +- arch/mips/loongson/common/early_printk.c | 11 +++++--- arch/mips/loongson/common/init.c | 11 +++++--- arch/mips/loongson/common/serial.c | 17 +++++------ arch/mips/loongson/common/uart_base.c | 34 ++++++++++++++++++++++++ 7 files changed, 60 insertions(+), 20 deletions(-) create mode 100644 arch/mips/loongson/common/uart_base.c diff --git a/arch/mips/include/asm/mach-loongson/loongson.h b/arch/mips/include/asm/mach-loongson/loongson.h index efb2344..e4818b6 100644 --- a/arch/mips/include/asm/mach-loongson/loongson.h +++ b/arch/mips/include/asm/mach-loongson/loongson.h @@ -31,6 +31,9 @@ extern void __init prom_init_memory(void); extern void __init prom_init_cmdline(void); extern void __init prom_init_machtype(void); extern void __init prom_init_env(void); +extern unsigned long _loongson_uart_base; +extern unsigned long uart8250_base[]; +extern inline void __maybe_unused prom_init_uart_base(void); /* irq operation functions */ extern void bonito_irqdispatch(void); diff --git a/arch/mips/include/asm/mach-loongson/machine.h b/arch/mips/include/asm/mach-loongson/machine.h index ea5954c..d2f5861 100644 --- a/arch/mips/include/asm/mach-loongson/machine.h +++ b/arch/mips/include/asm/mach-loongson/machine.h @@ -13,8 +13,6 @@ #ifdef CONFIG_LEMOTE_FULOONG2E -#define LOONGSON_UART_BASE (LOONGSON_PCIIO_BASE + 0x3f8) - #define LOONGSON_MACHTYPE MACH_LEMOTE_FL2E #endif diff --git a/arch/mips/loongson/common/Makefile b/arch/mips/loongson/common/Makefile index d21d116..be6adf7 100644 --- a/arch/mips/loongson/common/Makefile +++ b/arch/mips/loongson/common/Makefile @@ -3,7 +3,7 @@ # obj-y += setup.o init.o cmdline.o env.o time.o reset.o irq.o \ - pci.o bonito-irq.o mem.o machtype.o + pci.o bonito-irq.o mem.o machtype.o uart_base.o # # Early printk support diff --git a/arch/mips/loongson/common/early_printk.c b/arch/mips/loongson/common/early_printk.c index 8ec4fb2..23e7a8f 100644 --- a/arch/mips/loongson/common/early_printk.c +++ b/arch/mips/loongson/common/early_printk.c @@ -12,7 +12,6 @@ #include #include -#include #define PORT(base, offset) (u8 *)(base + offset) @@ -28,10 +27,14 @@ static inline void serial_out(unsigned char *base, int offset, int value) void prom_putchar(char c) { - unsigned char *uart_base = - (unsigned char *) ioremap_nocache(LOONGSON_UART_BASE, 8); + int timeout; + unsigned char *uart_base; - while ((serial_in(uart_base, UART_LSR) & UART_LSR_THRE) == 0) + uart_base = (unsigned char *)_loongson_uart_base; + timeout = 1024; + + while (((serial_in(uart_base, UART_LSR) & UART_LSR_THRE) == 0) && + (timeout-- > 0)) ; serial_out(uart_base, UART_TX, c); diff --git a/arch/mips/loongson/common/init.c b/arch/mips/loongson/common/init.c index b7e4913..3b1dbc1 100644 --- a/arch/mips/loongson/common/init.c +++ b/arch/mips/loongson/common/init.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2009 Lemote Inc. & Insititute of Computing Technology + * Copyright (C) 2009 Lemote Inc. * Author: Wu Zhangjin, wuzj@lemote.com * * This program is free software; you can redistribute it and/or modify it @@ -10,19 +10,22 @@ #include -#include - #include void __init prom_init(void) { - /* init base address of io space */ + /* init base address of io space */ set_io_port_base((unsigned long) ioremap(LOONGSON_PCIIO_BASE, LOONGSON_PCIIO_SIZE)); prom_init_cmdline(); prom_init_env(); prom_init_memory(); + + /*init the uart base address */ +#if defined(CONFIG_EARLY_PRINTK) || defined(CONFIG_SERIAL_8250) + prom_init_uart_base(); +#endif } void __init prom_free_prom_memory(void) diff --git a/arch/mips/loongson/common/serial.c b/arch/mips/loongson/common/serial.c index 6d341e4..dc6488c 100644 --- a/arch/mips/loongson/common/serial.c +++ b/arch/mips/loongson/common/serial.c @@ -23,7 +23,6 @@ { \ .irq = int, \ .uartclk = 1843200, \ - .iobase = (LOONGSON_UART_BASE - LOONGSON_PCIIO_BASE),\ .iotype = UPIO_PORT, \ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST, \ .regshift = 0, \ @@ -52,20 +51,20 @@ static struct plat_serial8250_port uart8250_data[][2] = { static struct platform_device uart8250_device = { .name = "serial8250", .id = PLAT8250_DEV_PLATFORM, - .dev = { - .platform_data = uart8250_data[LOONGSON_MACHTYPE], - }, }; static int __init serial_init(void) { - if (uart8250_data[LOONGSON_MACHTYPE][0].iotype == UPIO_MEM) - uart8250_data[LOONGSON_MACHTYPE][0].membase = - ioremap_nocache(LOONGSON_UART_BASE, 8); + if (uart8250_data[mips_machtype][0].iotype == UPIO_MEM) + uart8250_data[mips_machtype][0].membase = + (void __iomem *)_loongson_uart_base; + else if (uart8250_data[mips_machtype][0].iotype == UPIO_PORT) + uart8250_data[mips_machtype][0].iobase = + uart8250_base[mips_machtype] - LOONGSON_PCIIO_BASE; - platform_device_register(&uart8250_device); + uart8250_device.dev.platform_data = uart8250_data[mips_machtype]; - return 0; + return platform_device_register(&uart8250_device); } device_initcall(serial_init); diff --git a/arch/mips/loongson/common/uart_base.c b/arch/mips/loongson/common/uart_base.c new file mode 100644 index 0000000..c3db78a --- /dev/null +++ b/arch/mips/loongson/common/uart_base.c @@ -0,0 +1,34 @@ +/* + * Copyright (C) 2009 Lemote Inc. + * Author: Wu Zhangjin, wuzj@lemote.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include +#include + +#include + +unsigned long __maybe_unused _loongson_uart_base; +EXPORT_SYMBOL(_loongson_uart_base); + +unsigned long __maybe_unused uart8250_base[] = { + [MACH_LOONGSON_UNKNOWN] 0, + [MACH_LEMOTE_FL2E] (LOONGSON_PCIIO_BASE + 0x3f8), + [MACH_LEMOTE_FL2F] (LOONGSON_PCIIO_BASE + 0x2f8), + [MACH_LEMOTE_ML2F7] (LOONGSON_LIO1_BASE + 0x3f8), + [MACH_LEMOTE_YL2F89] (LOONGSON_LIO1_BASE + 0x3f8), + [MACH_DEXXON_GDIUM2F10] (LOONGSON_LIO1_BASE + 0x3f8), + [MACH_LOONGSON_END] 0, +}; +EXPORT_SYMBOL(uart8250_base); + +inline void __maybe_unused prom_init_uart_base(void) +{ + _loongson_uart_base = + (unsigned long)ioremap_nocache(uart8250_base[mips_machtype], 8); +} -- 1.6.2.1 From wuzhangjin@gmail.com Fri Nov 6 11:45:44 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 06 Nov 2009 11:45:51 +0100 (CET) Received: from mail-px0-f188.google.com ([209.85.216.188]:54806 "EHLO mail-px0-f188.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492503AbZKFKpo (ORCPT ); Fri, 6 Nov 2009 11:45:44 +0100 Received: by pxi26 with SMTP id 26so300704pxi.21 for ; Fri, 06 Nov 2009 02:45:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer; bh=9aaa+OiLua6UMflU4SOidZ37zJKSW77myhDp756Ka0s=; b=kEdBl5SfvT6byGqmmJtOvEiOIxJbNqCiD8XIPPMONOQUEq4PgGdh6UM16bWwMGLNqz KQxOR0WwuVhzRp9fkvbreIVTko3pXaRuusxyHuFffOriKJLPVHwPeodV/9go8j0v1Cuk Vi8mF4JjXO46cdMZ+WDMkV974WimzOxLEqVSQ= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer; b=ucZLRqY55CifA6yTJaf6iml0y++wXxEdRsESHjxQqIoDLrK1pXC+UPeQqD4lA7iUte RHGXxmLavUiNzmHAtx26K5VqQpEvX/pSCvWGVMHSDZqmsrtp6cHpyq15S2KPPnICOBwi zTS1Dz0DPJ5VXc56zm7XPFZCJUzA18lXDnqv0= Received: by 10.114.10.13 with SMTP id 13mr6539986waj.176.1257504337243; Fri, 06 Nov 2009 02:45:37 -0800 (PST) Received: from localhost.localdomain ([222.92.8.142]) by mx.google.com with ESMTPS id 22sm763633pxi.6.2009.11.06.02.45.34 (version=TLSv1/SSLv3 cipher=RC4-MD5); Fri, 06 Nov 2009 02:45:36 -0800 (PST) From: Wu Zhangjin To: Ralf Baechle Cc: linux-mips@linux-mips.org, Wu Zhangjin Subject: [PATCH -queue 0/2] add loongson2f support Date: Fri, 6 Nov 2009 18:45:04 +0800 Message-Id: X-Mailer: git-send-email 1.6.2.1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24716 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips The coming two patches add loongson2f support, including the basic loongson2f features support and a fix for oprofile of loongson2f. Wu Zhangjin (2): [loongson] add basic loongson-2f support [loongson] oprofile: avoid do_IRQ for perfcounter when the interrupt is from bonito arch/mips/Kconfig | 18 ++++ arch/mips/Makefile | 2 + .../mips/include/asm/mach-loongson/dma-coherence.h | 4 + arch/mips/include/asm/mach-loongson/loongson.h | 84 +++++++++++++++++++- arch/mips/include/asm/mach-loongson/mem.h | 27 +++++-- arch/mips/include/asm/mach-loongson/pci.h | 28 ++++++- arch/mips/loongson/common/bonito-irq.c | 5 +- arch/mips/loongson/common/init.c | 8 ++ arch/mips/loongson/common/mem.c | 17 ++++ arch/mips/loongson/common/pci.c | 8 ++ arch/mips/oprofile/op_model_loongson2.c | 5 +- 11 files changed, 193 insertions(+), 13 deletions(-) From wuzhangjin@gmail.com Fri Nov 6 11:46:09 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 06 Nov 2009 11:46:16 +0100 (CET) Received: from mail-px0-f188.google.com ([209.85.216.188]:52031 "EHLO mail-px0-f188.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492505AbZKFKpu (ORCPT ); Fri, 6 Nov 2009 11:45:50 +0100 Received: by pxi26 with SMTP id 26so300754pxi.21 for ; Fri, 06 Nov 2009 02:45:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer:in-reply-to:references:in-reply-to:references; bh=A+lXN30uLLxqJ1UtxxC4+rD/JIsiFymqbjP7pbBKgQ4=; b=rzoS0aFTM1nuFT7pcY7LIWGTzvCIWrBV1Yb8xW7bER+/nsUHaNK0AvGl6S429Xsfo+ wV5phODpvApmBpDeZ9eYJB0BF8zoOknrdLeI5QLCbdZSUxD/rhGj/GQkCMY3uCnfqbEE mRdNH21MVRn+VjKwKo7ztsF/PTo90OUJ7v7rk= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; b=QCF0or7Edv/y3cFkKHEA3166aUwQbfbT9cVw/k0IDUL1Ku4mlN2UQkyA74QLt9uu/A 7JPcYEfG3UiapM+s9WIcoLyghyH7nglUo93JOaoZTWn0meld99Y17LeOdEcKwFuRqBYX 3DfT5DlIyB/laSu6e4fU1HakuJqpcUxzXUc5o= Received: by 10.115.112.40 with SMTP id p40mr6494614wam.182.1257504342308; Fri, 06 Nov 2009 02:45:42 -0800 (PST) Received: from localhost.localdomain ([222.92.8.142]) by mx.google.com with ESMTPS id 22sm763633pxi.6.2009.11.06.02.45.37 (version=TLSv1/SSLv3 cipher=RC4-MD5); Fri, 06 Nov 2009 02:45:40 -0800 (PST) From: Wu Zhangjin To: Ralf Baechle Cc: linux-mips@linux-mips.org, Wu Zhangjin Subject: [PATCH -queue 1/2] [loongson] add basic loongson-2f support Date: Fri, 6 Nov 2009 18:45:05 +0800 Message-Id: X-Mailer: git-send-email 1.6.2.1 In-Reply-To: References: In-Reply-To: References: Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24717 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips Loongson2F has built-in DDR2 and PCIX controller. The PCIX controller have a similar programming interface with FPGA northbridge used in Loongson2E. The main differences between loongson-2e and loongson-2f include: 1. loongson-2f has an extra address windows configuration module, which can be used to map CPU address space to DDR or PCI address space, or map the PCI-DMA address space to DDR or LIO address space. 2. loongson-2f support 8 levels of software configurable cpu frequency, which can be configured via a register(LOONGSON_CHIPCFG0). the coming cpufreq and standby support are based on this feature. herein, the module and the corresponding operations are abstracted to loongson.h. besides, the other loongson2f-specific source code are added here, including gcc 4.4 support, pci memory space, pci io space, dma address. Signed-off-by: Wu Zhangjin --- arch/mips/Kconfig | 18 ++++ arch/mips/Makefile | 2 + .../mips/include/asm/mach-loongson/dma-coherence.h | 4 + arch/mips/include/asm/mach-loongson/loongson.h | 84 +++++++++++++++++++- arch/mips/include/asm/mach-loongson/mem.h | 27 +++++-- arch/mips/include/asm/mach-loongson/pci.h | 28 ++++++- arch/mips/loongson/common/bonito-irq.c | 5 +- arch/mips/loongson/common/init.c | 8 ++ arch/mips/loongson/common/mem.c | 17 ++++ arch/mips/loongson/common/pci.c | 8 ++ 10 files changed, 189 insertions(+), 12 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 68d2e46..d00c953 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -1059,6 +1059,21 @@ config CPU_LOONGSON2E The Loongson 2E processor implements the MIPS III instruction set with many extensions. + It has an internal FPGA northbridge, which is compatiable to + bonito64. + +config CPU_LOONGSON2F + bool "Loongson 2F" + depends on SYS_HAS_CPU_LOONGSON2F + select CPU_LOONGSON2 + help + The Loongson 2F processor implements the MIPS III instruction set + with many extensions. + + Loongson2F have built-in DDR2 and PCIX controller. The PCIX controller + have a similar programming interface with FPGA northbridge used in + Loongson2E. + config CPU_MIPS32_R1 bool "MIPS32 Release 1" depends on SYS_HAS_CPU_MIPS32_R1 @@ -1303,6 +1318,9 @@ config CPU_LOONGSON2 config SYS_HAS_CPU_LOONGSON2E bool +config SYS_HAS_CPU_LOONGSON2F + bool + config SYS_HAS_CPU_MIPS32_R1 bool diff --git a/arch/mips/Makefile b/arch/mips/Makefile index ba04782..47ecded 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -125,6 +125,8 @@ cflags-$(CONFIG_CPU_TX49XX) += -march=r4600 -Wa,--trap cflags-$(CONFIG_CPU_LOONGSON2) += -Wa,--trap cflags-$(CONFIG_CPU_LOONGSON2E) += \ $(call cc-option,-march=loongson2e,-march=r4600) +cflags-$(CONFIG_CPU_LOONGSON2F) += \ + $(call cc-option,-march=loongson2f,-march=r4600) cflags-$(CONFIG_CPU_MIPS32_R1) += $(call cc-option,-march=mips32,-mips32 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS32) \ -Wa,-mips32 -Wa,--trap diff --git a/arch/mips/include/asm/mach-loongson/dma-coherence.h b/arch/mips/include/asm/mach-loongson/dma-coherence.h index 71a6851..981c75f 100644 --- a/arch/mips/include/asm/mach-loongson/dma-coherence.h +++ b/arch/mips/include/asm/mach-loongson/dma-coherence.h @@ -28,7 +28,11 @@ static inline dma_addr_t plat_map_dma_mem_page(struct device *dev, static inline unsigned long plat_dma_addr_to_phys(struct device *dev, dma_addr_t dma_addr) { +#if defined(CONFIG_CPU_LOONGSON2F) && defined(CONFIG_64BIT) + return (dma_addr > 0x8fffffff) ? dma_addr : (dma_addr & 0x0fffffff); +#else return dma_addr & 0x7fffffff; +#endif } static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr, diff --git a/arch/mips/include/asm/mach-loongson/loongson.h b/arch/mips/include/asm/mach-loongson/loongson.h index e4818b6..e7e7a08 100644 --- a/arch/mips/include/asm/mach-loongson/loongson.h +++ b/arch/mips/include/asm/mach-loongson/loongson.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2009 Lemote, Inc. & Institute of Computing Technology + * Copyright (C) 2009 Lemote, Inc. * Author: Wu Zhangjin * * This program is free software; you can redistribute it and/or modify it @@ -219,4 +219,86 @@ extern void mach_irq_dispatch(unsigned int pending); #define LOONGSON_PCIMAP_WIN(WIN, ADDR) \ ((((ADDR)>>26) & LOONGSON_PCIMAP_PCIMAP_LO0) << ((WIN)*6)) +/* Chip Config */ +#ifdef CONFIG_CPU_LOONGSON2F +#define LOONGSON_CHIPCFG0 LOONGSON_REG(LOONGSON_REGBASE + 0x80) +#endif + +/* + * address windows configuration module + * + * loongson2e do not have this module + */ +#if defined(CONFIG_CPU_LOONGSON2F) && defined(CONFIG_64BIT) + +/* address window config module base address */ +#define LOONGSON_ADDRWINCFG_BASE 0x3ff00000ul +#define LOONGSON_ADDRWINCFG_SIZE 0x180 + +extern unsigned long _loongson_addrwincfg_base; +#define LOONGSON_ADDRWINCFG(offset) \ + (*(volatile u64 *)(_loongson_addrwincfg_base + (offset))) + +#define CPU_WIN0_BASE LOONGSON_ADDRWINCFG(0x00) +#define CPU_WIN1_BASE LOONGSON_ADDRWINCFG(0x08) +#define CPU_WIN2_BASE LOONGSON_ADDRWINCFG(0x10) +#define CPU_WIN3_BASE LOONGSON_ADDRWINCFG(0x18) + +#define CPU_WIN0_MASK LOONGSON_ADDRWINCFG(0x20) +#define CPU_WIN1_MASK LOONGSON_ADDRWINCFG(0x28) +#define CPU_WIN2_MASK LOONGSON_ADDRWINCFG(0x30) +#define CPU_WIN3_MASK LOONGSON_ADDRWINCFG(0x38) + +#define CPU_WIN0_MMAP LOONGSON_ADDRWINCFG(0x40) +#define CPU_WIN1_MMAP LOONGSON_ADDRWINCFG(0x48) +#define CPU_WIN2_MMAP LOONGSON_ADDRWINCFG(0x50) +#define CPU_WIN3_MMAP LOONGSON_ADDRWINCFG(0x58) + +#define PCIDMA_WIN0_BASE LOONGSON_ADDRWINCFG(0x60) +#define PCIDMA_WIN1_BASE LOONGSON_ADDRWINCFG(0x68) +#define PCIDMA_WIN2_BASE LOONGSON_ADDRWINCFG(0x70) +#define PCIDMA_WIN3_BASE LOONGSON_ADDRWINCFG(0x78) + +#define PCIDMA_WIN0_MASK LOONGSON_ADDRWINCFG(0x80) +#define PCIDMA_WIN1_MASK LOONGSON_ADDRWINCFG(0x88) +#define PCIDMA_WIN2_MASK LOONGSON_ADDRWINCFG(0x90) +#define PCIDMA_WIN3_MASK LOONGSON_ADDRWINCFG(0x98) + +#define PCIDMA_WIN0_MMAP LOONGSON_ADDRWINCFG(0xa0) +#define PCIDMA_WIN1_MMAP LOONGSON_ADDRWINCFG(0xa8) +#define PCIDMA_WIN2_MMAP LOONGSON_ADDRWINCFG(0xb0) +#define PCIDMA_WIN3_MMAP LOONGSON_ADDRWINCFG(0xb8) + +#define ADDRWIN_WIN0 0 +#define ADDRWIN_WIN1 1 +#define ADDRWIN_WIN2 2 +#define ADDRWIN_WIN3 3 + +#define ADDRWIN_MAP_DST_DDR 0 +#define ADDRWIN_MAP_DST_PCI 1 +#define ADDRWIN_MAP_DST_LIO 1 + +/* + * s: CPU, PCIDMA + * d: DDR, PCI, LIO + * win: 0, 1, 2, 3 + * src: map source + * dst: map destination + * size: ~mask + 1 + */ +#define LOONGSON_ADDRWIN_CFG(s, d, w, src, dst, size) do {\ + s##_WIN##w##_BASE = (src); \ + s##_WIN##w##_MMAP = (src) | ADDRWIN_MAP_DST_##d; \ + s##_WIN##w##_MASK = ~(size-1); \ +} while (0) + +#define LOONGSON_ADDRWIN_CPUTOPCI(win, src, dst, size) \ + LOONGSON_ADDRWIN_CFG(CPU, PCI, win, src, dst, size) +#define LOONGSON_ADDRWIN_CPUTODDR(win, src, dst, size) \ + LOONGSON_ADDRWIN_CFG(CPU, DDR, win, src, dst, size) +#define LOONGSON_ADDRWIN_PCITODDR(win, src, dst, size) \ + LOONGSON_ADDRWIN_CFG(PCIDMA, DDR, win, src, dst, size) + +#endif /* ! CONFIG_CPU_LOONGSON2F && CONFIG_64BIT */ + #endif /* __ASM_MACH_LOONGSON_LOONGSON_H */ diff --git a/arch/mips/include/asm/mach-loongson/mem.h b/arch/mips/include/asm/mach-loongson/mem.h index bd7b3cb..e9960f3 100644 --- a/arch/mips/include/asm/mach-loongson/mem.h +++ b/arch/mips/include/asm/mach-loongson/mem.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2009 Lemote, Inc. & Institute of Computing Technology + * Copyright (C) 2009 Lemote, Inc. * Author: Wu Zhangjin * * This program is free software; you can redistribute it and/or modify it @@ -12,19 +12,30 @@ #define __ASM_MACH_LOONGSON_MEM_H /* - * On Lemote Loongson 2e + * high memory space * - * the high memory space starts from 512M. - * the peripheral registers reside between 0x1000:0000 and 0x2000:0000. + * in loongson2e, starts from 512M + * in loongson2f, starts from 2G 256M */ +#ifdef CONFIG_CPU_LOONGSON2E +#define LOONGSON_HIGHMEM_START 0x20000000 +#else +#define LOONGSON_HIGHMEM_START 0x90000000 +#endif -#ifdef CONFIG_LEMOTE_FULOONG2E - -#define LOONGSON_HIGHMEM_START 0x20000000 +/* + * the peripheral registers(MMIO): + * + * On the Lemote Loongson 2e system, reside between 0x1000:0000 and 0x2000:0000. + * On the Lemote Loongson 2f system, reside between 0x1000:0000 and 0x8000:0000. + */ #define LOONGSON_MMIO_MEM_START 0x10000000 -#define LOONGSON_MMIO_MEM_END 0x20000000 +#ifdef CONFIG_CPU_LOONGSON2E +#define LOONGSON_MMIO_MEM_END 0x20000000 +#else +#define LOONGSON_MMIO_MEM_END 0x80000000 #endif #endif /* __ASM_MACH_LOONGSON_MEM_H */ diff --git a/arch/mips/include/asm/mach-loongson/pci.h b/arch/mips/include/asm/mach-loongson/pci.h index 576487c..31ba908 100644 --- a/arch/mips/include/asm/mach-loongson/pci.h +++ b/arch/mips/include/asm/mach-loongson/pci.h @@ -1,5 +1,6 @@ /* * Copyright (c) 2008 Zhang Le + * Copyright (c) 2009 Wu Zhangjin * * This program is free software; you can redistribute it * and/or modify it under the terms of the GNU General @@ -24,7 +25,30 @@ extern struct pci_ops loongson_pci_ops; -#ifdef CONFIG_LEMOTE_FULOONG2E +/* this is an offset from mips_io_port_base */ +#define LOONGSON_PCI_IO_START 0x00004000UL + +#if defined(CONFIG_CPU_LOONGSON2F) && defined(CONFIG_64BIT) + +/* + * we use address window2 to map cpu address space to pci space + * window2: cpu [1G, 2G] -> pci [1G, 2G] + * why not use window 0 & 1? because they are used by cpu when booting. + * window0: cpu [0, 256M] -> ddr [0, 256M] + * window1: cpu [256M, 512M] -> pci [256M, 512M] + */ + +/* the smallest LOONGSON_CPU_MEM_SRC can be 512M */ +#define LOONGSON_CPU_MEM_SRC 0x40000000ul /* 1G */ +#define LOONGSON_PCI_MEM_DST LOONGSON_CPU_MEM_SRC + +#define LOONGSON_PCI_MEM_START LOONGSON_PCI_MEM_DST +#define LOONGSON_PCI_MEM_END (0x80000000ul-1) /* 2G */ + +#define MMAP_CPUTOPCI_SIZE (LOONGSON_PCI_MEM_END - \ + LOONGSON_PCI_MEM_START + 1) + +#else /* loongson2f/32bit & loongson2e */ /* this pci memory space is mapped by pcimap in pci.c */ #define LOONGSON_PCI_MEM_START LOONGSON_PCILO1_BASE @@ -32,6 +56,6 @@ extern struct pci_ops loongson_pci_ops; /* this is an offset from mips_io_port_base */ #define LOONGSON_PCI_IO_START 0x00004000UL -#endif +#endif /* !(defined(CONFIG_CPU_LOONGSON2F) && defined(CONFIG_64BIT))*/ #endif /* !__ASM_MACH_LOONGSON_PCI_H_ */ diff --git a/arch/mips/loongson/common/bonito-irq.c b/arch/mips/loongson/common/bonito-irq.c index a1cbd11..2dc2a4c 100644 --- a/arch/mips/loongson/common/bonito-irq.c +++ b/arch/mips/loongson/common/bonito-irq.c @@ -12,6 +12,7 @@ * option) any later version. */ #include +#include #include @@ -35,7 +36,7 @@ static struct irq_chip bonito_irq_type = { .unmask = bonito_irq_enable, }; -static struct irqaction dma_timeout_irqaction = { +static struct irqaction __maybe_unused dma_timeout_irqaction = { .handler = no_action, .name = "dma_timeout", }; @@ -47,5 +48,7 @@ void bonito_irq_init(void) for (i = LOONGSON_IRQ_BASE; i < LOONGSON_IRQ_BASE + 32; i++) set_irq_chip_and_handler(i, &bonito_irq_type, handle_level_irq); +#ifdef CONFIG_CPU_LOONGSON2E setup_irq(LOONGSON_IRQ_BASE + 10, &dma_timeout_irqaction); +#endif } diff --git a/arch/mips/loongson/common/init.c b/arch/mips/loongson/common/init.c index 3b1dbc1..743d357 100644 --- a/arch/mips/loongson/common/init.c +++ b/arch/mips/loongson/common/init.c @@ -12,12 +12,20 @@ #include +/* Loongson CPU address windows config space base address */ +unsigned long __maybe_unused _loongson_addrwincfg_base; + void __init prom_init(void) { /* init base address of io space */ set_io_port_base((unsigned long) ioremap(LOONGSON_PCIIO_BASE, LOONGSON_PCIIO_SIZE)); +#if defined(CONFIG_CPU_LOONGSON2F) && defined(CONFIG_64BIT) + _loongson_addrwincfg_base = (unsigned long) + ioremap(LOONGSON_ADDRWINCFG_BASE, LOONGSON_ADDRWINCFG_SIZE); +#endif + prom_init_cmdline(); prom_init_env(); prom_init_memory(); diff --git a/arch/mips/loongson/common/mem.c b/arch/mips/loongson/common/mem.c index 47a20de..45991af 100644 --- a/arch/mips/loongson/common/mem.c +++ b/arch/mips/loongson/common/mem.c @@ -21,6 +21,23 @@ void __init prom_init_memory(void) add_memory_region(memsize << 20, LOONGSON_PCI_MEM_START - (memsize << 20), BOOT_MEM_RESERVED); #ifdef CONFIG_64BIT +#ifdef CONFIG_CPU_LOONGSON2F + { + int bit; + + bit = fls(memsize + highmemsize); + if (bit != ffs(memsize + highmemsize)) + bit += 20; + else + bit = bit + 20 - 1; + + /* set cpu window3 to map CPU to DDR: 2G -> 2G */ + LOONGSON_ADDRWIN_CPUTODDR(ADDRWIN_WIN3, 0x80000000ul, + 0x80000000ul, (1 << bit)); + mmiowb(); + } +#endif /* CONFIG_CPU_LOONGSON2F */ + if (highmemsize > 0) add_memory_region(LOONGSON_HIGHMEM_START, highmemsize << 20, BOOT_MEM_RAM); diff --git a/arch/mips/loongson/common/pci.c b/arch/mips/loongson/common/pci.c index a7eb8b9..eac43b8 100644 --- a/arch/mips/loongson/common/pci.c +++ b/arch/mips/loongson/common/pci.c @@ -67,6 +67,14 @@ static void __init setup_pcimap(void) /* can not change gnt to break pci transfer when device's gnt not deassert for some broken device */ LOONGSON_PXARB_CFG = 0x00fe0105ul; + +#if defined(CONFIG_CPU_LOONGSON2F) && defined(CONFIG_64BIT) + /* + * set cpu addr window2 to map CPU address space to PCI address space + */ + LOONGSON_ADDRWIN_CPUTOPCI(ADDRWIN_WIN2, LOONGSON_CPU_MEM_SRC, + LOONGSON_PCI_MEM_DST, MMAP_CPUTOPCI_SIZE); +#endif } static int __init pcibios_init(void) -- 1.6.2.1 From wuzhangjin@gmail.com Fri Nov 6 11:46:35 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 06 Nov 2009 11:46:42 +0100 (CET) Received: from mail-pw0-f45.google.com ([209.85.160.45]:40411 "EHLO mail-pw0-f45.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492510AbZKFKpx (ORCPT ); Fri, 6 Nov 2009 11:45:53 +0100 Received: by pwi15 with SMTP id 15so592518pwi.24 for ; Fri, 06 Nov 2009 02:45:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer:in-reply-to:references:in-reply-to:references; bh=IEwX585/EAHLeOBM95S9WJE3D3EYWQG5SFOm5HDumj8=; b=wT5uxuTX3kfjdxYFiJg4o1r9Gv7DxYVpk4SIupgNDdpJY5X+uv9Y2URtZpPJoHL0iq 7N36mMU5mWYkSMig2UPQ91MWkvKvGTW5bKo6FzIB5fD97BwTc+cwVQdfYIf+im+V95vx 4OHVSs+i/0RednGxaDN2ti3eNckKjWHXpBbFQ= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; b=HwHfRR6K9OhSZ3YPlRv2cqgDv8xVtYXdVV0ltBGrPVXGeteALVhJitri3Y2zdL+sJc OzpEXVYTcG2NKS/RwP4sCuvOdRybBcMmy77c+2Ni7aE0wLBtGOlN3AXDyo1JGaYfwsU5 2QcDnMckaAyauUKDdps9Cpo5flZcJZmTCzQCk= Received: by 10.115.81.24 with SMTP id i24mr1567117wal.194.1257504345768; Fri, 06 Nov 2009 02:45:45 -0800 (PST) Received: from localhost.localdomain ([222.92.8.142]) by mx.google.com with ESMTPS id 22sm763633pxi.6.2009.11.06.02.45.42 (version=TLSv1/SSLv3 cipher=RC4-MD5); Fri, 06 Nov 2009 02:45:45 -0800 (PST) From: Wu Zhangjin To: Ralf Baechle Cc: linux-mips@linux-mips.org, Wu Zhangjin Subject: [PATCH -queue 2/2] [loongson] oprofile: avoid do_IRQ for perfcounter when the interrupt is from bonito Date: Fri, 6 Nov 2009 18:45:06 +0800 Message-Id: <578fdf2cd4a665bb8b56635e2ba7384ec9059ff8.1257504242.git.wuzhangjin@gmail.com> X-Mailer: git-send-email 1.6.2.1 In-Reply-To: References: In-Reply-To: References: Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24718 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips In loongson2f, the IP6 is shared by bonito and perfcounter, we need to avoid do_IRQ for perfcounter when the interrupt is from bonito. This patch does it. Signed-off-by: Wu Zhangjin --- arch/mips/oprofile/op_model_loongson2.c | 5 ++++- 1 files changed, 4 insertions(+), 1 deletions(-) diff --git a/arch/mips/oprofile/op_model_loongson2.c b/arch/mips/oprofile/op_model_loongson2.c index 575cd14..475ff46 100644 --- a/arch/mips/oprofile/op_model_loongson2.c +++ b/arch/mips/oprofile/op_model_loongson2.c @@ -1,7 +1,7 @@ /* * Loongson2 performance counter driver for oprofile * - * Copyright (C) 2009 Lemote Inc. & Insititute of Computing Technology + * Copyright (C) 2009 Lemote Inc. * Author: Yanhua * Author: Wu Zhangjin * @@ -125,6 +125,9 @@ static irqreturn_t loongson2_perfcount_handler(int irq, void *dev_id) */ /* Check whether the irq belongs to me */ + enabled = read_c0_perfcnt() & LOONGSON2_PERFCNT_INT_EN; + if (!enabled) + return IRQ_NONE; enabled = reg.cnt1_enabled | reg.cnt2_enabled; if (!enabled) return IRQ_NONE; -- 1.6.2.1 From shinya.kuribayashi@necel.com Fri Nov 6 13:42:44 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 06 Nov 2009 13:42:51 +0100 (CET) Received: from TYO201.gate.nec.co.jp ([202.32.8.193]:44365 "EHLO tyo201.gate.nec.co.jp" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492663AbZKFMmo (ORCPT ); Fri, 6 Nov 2009 13:42:44 +0100 Received: from relay11.aps.necel.com ([10.29.19.46]) by tyo201.gate.nec.co.jp (8.13.8/8.13.4) with ESMTP id nA6CgIXk011056; Fri, 6 Nov 2009 21:42:26 +0900 (JST) Received: from realmbox31.aps.necel.com ([10.29.19.28] [10.29.19.28]) by relay11.aps.necel.com with ESMTP; Fri, 6 Nov 2009 21:42:25 +0900 Received: from [10.114.181.128] ([10.114.181.128] [10.114.181.128]) by mbox02.aps.necel.com with ESMTP; Fri, 6 Nov 2009 21:42:25 +0900 Message-ID: <4AF419B6.1000802@necel.com> Date: Fri, 06 Nov 2009 21:42:30 +0900 From: Shinya Kuribayashi User-Agent: Thunderbird 2.0.0.23 (Windows/20090812) MIME-Version: 1.0 To: baruch@tkos.co.il, ben-linux@fluff.org, linux-i2c@vger.kernel.org CC: linux-mips@linux-mips.org, linux-arm-kernel@lists.infradead.org, Shinya Kuribayashi Subject: [PATCH v2] i2c-designware updates Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24719 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: shinya.kuribayashi@necel.com Precedence: bulk X-list: linux-mips Hi Baruch and Ben, here's v2 patchset of DesignWare I2C driver (i2c-designware.c). I did all test I can do for now (including arbitration tests), and fixed more issues left in the v1 patchset. I think now the driver is in reasonable shape for the mainline, and hope gets merged. The patches which already have Baruch's Acked-by: line are logically same as the previous v1 patches. For the rest are revised version of v1 patches, or newly added in v2. There are 22 patches in total and might be slightly annoying. I'll send subsequent patches only to linux-i2c. Changes in v2 ============== * i2c-designware: Set a clock name to DW I2C clock source -> dropped. * 02/22: Don't use the IC_CLR_INTR register to clear interrupts We need to preserve IC_TX_ABRT_SOURCE value before clearing interrupts, or we can't get correct abort_source. ->Fixed * 08/22: i2c_dw_xfer_msg: Fix i2c_msg search bug The intr_mask handling is folded into the for-loop. * 15/22: i2c_dw_func: Set I2C_FUNC_SMBUS_foo bits Commit log is updated. * 01--15 (except for 02, 08, and 15) are logically same as the previous v1 patches. * For the rest (16--22) are newly added. Shinya Kuribayashi (22): i2c-designware: Consolidate to use 32-bit word accesses i2c-designware: Don't use the IC_CLR_INTR register to clear interrupts i2c-designware: Use platform_get_irq helper i2c-designware: i2c_dw_read: Use "struct dw_i2c_dev" pointer i2c-designware: i2c_dw_xfer_msg: Use "struct dw_i2c_dev" pointer i2c-designware: Remove an useless local variable "num" i2c-designware: Improved _HCNT/_LCNT calculation i2c-designware: i2c_dw_xfer_msg: Fix i2c_msg search bug i2c-designware: Process i2c_msg messages in the interrupt handler i2c-designware: Set Tx/Rx FIFO threshold levels i2c-designware: Enable RX_FULL interrupt i2c-designware: Divide i2c_dw_xfer_msg into two functions i2c-designware: i2c_dw_xfer_msg: Introduce a local "buf" pointer i2c-designware: Initialize byte count variables just prior to being used i2c-designware: i2c_dw_func: Set I2C_FUNC_SMBUS_foo bits i2c-designware: i2c_dw_read: Remove redundant target address checker i2c-designware: Process all i2c_msg messages in the interrupt handler i2c-designware: Disable TX_EMPTY when all i2c_msg msgs has been processed i2c-designware: i2c_dw_xfer_msg: Fix error handling procedures i2c-designware: Skip RX_FULL and TX_EMPTY bits on tx abort errors i2c-designware: Tx abort cleanups i2c-designware: Cosmetic cleanups drivers/i2c/busses/i2c-designware.c | 483 +++++++++++++++++++++++++---------- 1 files changed, 350 insertions(+), 133 deletions(-) -- Shinya Kuribayashi NEC Electronics From ralf@linux-mips.org Fri Nov 6 13:48:45 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 06 Nov 2009 13:48:48 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:41663 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-FAIL) by ftp.linux-mips.org with ESMTP id S1492680AbZKFMsp (ORCPT ); Fri, 6 Nov 2009 13:48:45 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id nA6CoFxk006262; Fri, 6 Nov 2009 13:50:15 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id nA6CoFEK006260; Fri, 6 Nov 2009 13:50:15 +0100 Date: Fri, 6 Nov 2009 13:50:15 +0100 From: Ralf Baechle To: Wu Zhangjin Cc: linux-mips@linux-mips.org Subject: Re: [PATCH -queue 1/2] [loongson] Cleanup the machtype support Message-ID: <20091106125015.GA31392@linux-mips.org> References: <905f2e99289a26852bf8d413f0e56ef2235cac99.1257503696.git.wuzhangjin@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <905f2e99289a26852bf8d413f0e56ef2235cac99.1257503696.git.wuzhangjin@gmail.com> User-Agent: Mutt/1.5.19 (2009-01-05) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24720 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Fri, Nov 06, 2009 at 06:35:33PM +0800, Wu Zhangjin wrote: > We need to initialize mips_machtype as early as we can, So, we can > choose corresponding code for different machines via it. > > This patch moves the initialization of mips_machtype to prom_init(). > > Signed-off-by: Wu Zhangjin Thanks, queued for 2.6.33. Ralf From ralf@linux-mips.org Fri Nov 6 13:49:06 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 06 Nov 2009 13:49:11 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:41671 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-FAIL) by ftp.linux-mips.org with ESMTP id S1492687AbZKFMtA (ORCPT ); Fri, 6 Nov 2009 13:49:00 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id nA6CoVot006269; Fri, 6 Nov 2009 13:50:31 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id nA6CoVTw006267; Fri, 6 Nov 2009 13:50:31 +0100 Date: Fri, 6 Nov 2009 13:50:30 +0100 From: Ralf Baechle To: Wu Zhangjin Cc: linux-mips@linux-mips.org Subject: Re: [PATCH -queue 2/2] [loongson] Cleanup the serial port support Message-ID: <20091106125030.GB31392@linux-mips.org> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.19 (2009-01-05) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24721 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Fri, Nov 06, 2009 at 06:35:34PM +0800, Wu Zhangjin wrote: > To share the same kernel image amon different machines, we have added > the machtype command line support. > > but in the old serial port implementation, we have hardcoded the uart > base address as a macro in machine.h, which will break the intention of > machtype. this patch fixes it, and also move the initialization of uart > base address to uart_base.c to avoid remapping twice for early_printk.c > and serial.c. > > Signed-off-by: Wu Zhangjin Thanks, queued for 2.6.33. Ralf From wuzhangjin@gmail.com Fri Nov 6 14:11:57 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 06 Nov 2009 14:12:04 +0100 (CET) Received: from mail-px0-f188.google.com ([209.85.216.188]:51511 "EHLO mail-px0-f188.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492534AbZKFNL5 (ORCPT ); Fri, 6 Nov 2009 14:11:57 +0100 Received: by pxi26 with SMTP id 26so367449pxi.21 for ; Fri, 06 Nov 2009 05:11:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer; bh=NSJd8ftbFo3hu1fY+0crJZHR4X5MoT+MxFjoKPQEsig=; b=FhJtdiPC50gWtHalwvydX+oJtg/E80YhR9qdO/MAH3rKeCM5BwTtvPEaNt6z22JsTq SiI8r+K1Y6HthiMyHH9H9xiTsd6yCEAJG68oHFP48+HEe5bfZjsxVTgqcfA1plgvkOmc 28kC4YnJDSRxZ6uQOlBvCKoJL0vLjI4fZjp7U= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer; b=nXANXSUEouJ+kF1p9EuzLo5+cFCmiJyKhGjGN/P9Lh62yfAAFzOdfCW6vlngOdEFQY aIrrKEYNbqJCXr6M3/DfAUj2SD2k0eecM7QgKuh4kRFargIs8+9njb0aFyqF+eI2O+AN o7jsE0EKtSvJymJeNfusiJGZoggsB3KKWNbRc= Received: by 10.114.162.5 with SMTP id k5mr6714339wae.10.1257513111101; Fri, 06 Nov 2009 05:11:51 -0800 (PST) Received: from localhost.localdomain ([222.92.8.142]) by mx.google.com with ESMTPS id 20sm26431pxi.7.2009.11.06.05.11.42 (version=TLSv1/SSLv3 cipher=RC4-MD5); Fri, 06 Nov 2009 05:11:50 -0800 (PST) From: Wu Zhangjin To: Ralf Baechle Cc: Arnaud Patard , zhangfx@lemote.com, yanh@lemote.com, huhb@lemote.com, Nicholas Mc Guire , Wu Zhangjin , linux-mips@linux-mips.org Subject: [PATCH -queue v1 0/7] support for lemote loongson2f machines Date: Fri, 6 Nov 2009 21:11:25 +0800 Message-Id: X-Mailer: git-send-email 1.6.2.1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24722 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips From: Wu Zhangjin This patchset add basic support for lemote loongson2f machines, including fuloong2f mini box, yeeloong2f netbook and mengloong2f netbook. All of the lemote loongson2f family machines utilize the 2f revision of loongson processor and the AMD cs5536 south bridge. The differences among these machines are very small, the most important part should be the reset/shutdown logic. so, it's possible to share the same kernel image among them, this patchset really does it! And of course, there are some other differences between the box and the netbook: 1. the netbook has a sm712 video card, whose driver is not in the mainline yet, if you only need the X window, there is an existing driver in X. but if you need a console, please add the sm712 video driver in the next patchset. This video driver is not ready to upstream but we will try to push it into drivers/staging asap. 2. the netbook has an Embedded Controller(kb3310b), which helps to do reset/shutdown management, power supply/battery management, hotkey management, display management and so forth. The corresponding platform drivers will come later. 3. the netbook has a rtl8187b wifi netcard, there is an existing driver in the mainline, but the performance is not good(and seems no rfkill support there), a better one is maintained outside the mainline and it's not that easy to upstream, but we will try it later. And what about the common parts among them: 1. cpufreq support the cpu frequency of loongson2f is software configurable(8 levels), and there is an existing external mfgpt timer provided by cs5536, So, a cpufreq dirver for loongson2f is also ready there, will come later. 2. standby support also benefit from the above feature of loongson2f, when we put loongson2f into ZERO frequency(wait mode), it will save about 2w for us, and wait there until an external interrupt take place. So, it's possible to add standby support to loongson2f family machines. the relative patches will also come later. (This -v1 patch incorporates the feedbacks from Ralf & Arnaud Patard, the main change is putting all of the loongson2f machines into lemote-2f and hope this will make the linux distributions happy!) Thanks & Regards, Wu Zhangjin Wu Zhangjin (7): [loongson] lemote-2f: add lemote loongson2f family machines support [loongson] lemote-2f: rtc: enable legacy RTC driver [loongson] lemote-2f: add basic cs5536 vsm support [loongson] lemote-2f: add pci support [loongson] lemote-2f: add irq support [loongson] lemote-2f: add reset and shutdown support [loongson] lemote-2f: add defconfig file arch/mips/Kconfig | 2 +- arch/mips/Makefile | 1 + arch/mips/configs/lemote2f_defconfig | 1794 ++++++++++++++++++++ .../mips/include/asm/mach-loongson/cs5536/cs5536.h | 305 ++++ .../include/asm/mach-loongson/cs5536/cs5536_pci.h | 153 ++ .../include/asm/mach-loongson/cs5536/cs5536_vsm.h | 31 + arch/mips/include/asm/mach-loongson/loongson.h | 7 + arch/mips/include/asm/mach-loongson/machine.h | 7 + arch/mips/loongson/Kconfig | 32 + arch/mips/loongson/Makefile | 6 + arch/mips/loongson/common/Makefile | 6 + arch/mips/loongson/common/cs5536/Makefile | 8 + arch/mips/loongson/common/cs5536/cs5536_acc.c | 148 ++ arch/mips/loongson/common/cs5536/cs5536_ehci.c | 158 ++ arch/mips/loongson/common/cs5536/cs5536_ide.c | 185 ++ arch/mips/loongson/common/cs5536/cs5536_isa.c | 316 ++++ arch/mips/loongson/common/cs5536/cs5536_ohci.c | 153 ++ arch/mips/loongson/common/cs5536/cs5536_pci.c | 87 + arch/mips/loongson/lemote-2f/Makefile | 5 + arch/mips/loongson/lemote-2f/irq.c | 130 ++ arch/mips/loongson/lemote-2f/reset.c | 163 ++ arch/mips/pci/Makefile | 3 +- arch/mips/pci/fixup-lemote2f.c | 162 ++ arch/mips/pci/ops-fuloong2e.c | 154 -- arch/mips/pci/ops-loongson2.c | 208 +++ 25 files changed, 4068 insertions(+), 156 deletions(-) create mode 100644 arch/mips/configs/lemote2f_defconfig create mode 100644 arch/mips/include/asm/mach-loongson/cs5536/cs5536.h create mode 100644 arch/mips/include/asm/mach-loongson/cs5536/cs5536_pci.h create mode 100644 arch/mips/include/asm/mach-loongson/cs5536/cs5536_vsm.h create mode 100644 arch/mips/loongson/common/cs5536/Makefile create mode 100644 arch/mips/loongson/common/cs5536/cs5536_acc.c create mode 100644 arch/mips/loongson/common/cs5536/cs5536_ehci.c create mode 100644 arch/mips/loongson/common/cs5536/cs5536_ide.c create mode 100644 arch/mips/loongson/common/cs5536/cs5536_isa.c create mode 100644 arch/mips/loongson/common/cs5536/cs5536_ohci.c create mode 100644 arch/mips/loongson/common/cs5536/cs5536_pci.c create mode 100644 arch/mips/loongson/lemote-2f/Makefile create mode 100644 arch/mips/loongson/lemote-2f/irq.c create mode 100644 arch/mips/loongson/lemote-2f/reset.c create mode 100644 arch/mips/pci/fixup-lemote2f.c delete mode 100644 arch/mips/pci/ops-fuloong2e.c create mode 100644 arch/mips/pci/ops-loongson2.c From wuzhangjin@gmail.com Fri Nov 6 14:12:22 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 06 Nov 2009 14:12:29 +0100 (CET) Received: from mail-px0-f188.google.com ([209.85.216.188]:39281 "EHLO mail-px0-f188.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492723AbZKFNMD (ORCPT ); Fri, 6 Nov 2009 14:12:03 +0100 Received: by pxi26 with SMTP id 26so367498pxi.21 for ; Fri, 06 Nov 2009 05:11:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer:in-reply-to:references:in-reply-to:references; bh=71krOEAoR9pvdrgsL5eCJSutFVZb6QsnvE11gJdZnvY=; b=AeFkcSUjIqN6Lijt8wGt8YH9KQhdCud0VCywlXoq4sdDH+UjCk6Zb2XpofsNv27G8i P5TFef+43lrq3jHc1xH/2GsE933w0kYV1v590n7f3cK9fSzpDu/ARGENRWBgEqOSy18J ae36nS73aByMk9oKq76LBZJgsHaMR3FLw1JPU= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; b=IRFDnz08X9zVSlcBj/tgZAJvOdQGRxrrWg2lvLy1hcKC8/d7v364ML87XWF7R0NUaR wc+44JZMr6HQaMvrqyQjsUsKs/2p+yabzogI7lcmZL/ZwvUcDmJSENMbitCfVazUjIE/ 3ULngrN+BubuECDNtfuQQ/6x8+gg3w322biqk= Received: by 10.115.66.10 with SMTP id t10mr6770523wak.20.1257513116316; Fri, 06 Nov 2009 05:11:56 -0800 (PST) Received: from localhost.localdomain ([222.92.8.142]) by mx.google.com with ESMTPS id 20sm26431pxi.7.2009.11.06.05.11.51 (version=TLSv1/SSLv3 cipher=RC4-MD5); Fri, 06 Nov 2009 05:11:55 -0800 (PST) From: Wu Zhangjin To: Ralf Baechle Cc: Arnaud Patard , zhangfx@lemote.com, yanh@lemote.com, huhb@lemote.com, Nicholas Mc Guire , Wu Zhangjin , linux-mips@linux-mips.org Subject: [PATCH -queue v1 1/7] [loongson] lemote-2f: add lemote loongson2f family machines support Date: Fri, 6 Nov 2009 21:11:26 +0800 Message-Id: <17e5d58a0cd7273b81c7151b7f7f2096c9694b59.1257510612.git.wuzhangjin@gmail.com> X-Mailer: git-send-email 1.6.2.1 In-Reply-To: References: In-Reply-To: References: Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24723 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips From: Wu Zhangjin This patch add a new kernel option for lemote loongson2f family machines. Lemote loongson2f family machines utilize the 2f revision of loongson processor and the AMD CS5536 south bridge. These family machines include fuloong2f mini PC, yeeloong2f notebook, LingLoong allinone PC and so forth. Signed-off-by: Wu Zhangjin --- arch/mips/Makefile | 1 + arch/mips/include/asm/mach-loongson/machine.h | 7 ++++++ arch/mips/loongson/Kconfig | 29 +++++++++++++++++++++++++ 3 files changed, 37 insertions(+), 0 deletions(-) diff --git a/arch/mips/Makefile b/arch/mips/Makefile index 47ecded..184d5be 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -327,6 +327,7 @@ core-$(CONFIG_MACH_LOONGSON) +=arch/mips/loongson/ cflags-$(CONFIG_MACH_LOONGSON) += -I$(srctree)/arch/mips/include/asm/mach-loongson \ -mno-branch-likely load-$(CONFIG_LEMOTE_FULOONG2E) +=0xffffffff80100000 +load-$(CONFIG_LEMOTE_MACH2F) +=0xffffffff80200000 # # MIPS Malta board diff --git a/arch/mips/include/asm/mach-loongson/machine.h b/arch/mips/include/asm/mach-loongson/machine.h index d2f5861..acf8359 100644 --- a/arch/mips/include/asm/mach-loongson/machine.h +++ b/arch/mips/include/asm/mach-loongson/machine.h @@ -17,4 +17,11 @@ #endif +/* use fuloong2f as the default machine of LEMOTE_MACH2F */ +#ifdef CONFIG_LEMOTE_MACH2F + +#define LOONGSON_MACHTYPE MACH_LEMOTE_FL2F + +#endif + #endif /* __ASM_MACH_LOONGSON_MACHINE_H */ diff --git a/arch/mips/loongson/Kconfig b/arch/mips/loongson/Kconfig index 818a028..9573406 100644 --- a/arch/mips/loongson/Kconfig +++ b/arch/mips/loongson/Kconfig @@ -28,4 +28,33 @@ config LEMOTE_FULOONG2E an FPGA northbridge Lemote Fuloong(2e) mini PC have a VIA686B south bridge. + +config LEMOTE_MACH2F + bool "Lemote loongson2f family machines" + select ARCH_SPARSEMEM_ENABLE + select CEVT_R4K + select CSRC_R4K + select SYS_HAS_CPU_LOONGSON2F + select DMA_NONCOHERENT + select BOOT_ELF32 + select BOARD_SCACHE + select HW_HAS_PCI + select I8259 + select ISA + select IRQ_CPU + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_64BIT_KERNEL + select SYS_SUPPORTS_LITTLE_ENDIAN + select SYS_SUPPORTS_HIGHMEM + select SYS_HAS_EARLY_PRINTK + select GENERIC_HARDIRQS_NO__DO_IRQ + select GENERIC_ISA_DMA_SUPPORT_BROKEN + select CPU_HAS_WB + select CS5536 + help + Lemote loongson2f family machines utilize the 2f revision of loongson + processor and the AMD CS5536 south bridge. + + These family machines include fuloong2f mini PC, yeeloong2f notebook, + LingLoong allinone PC and so forth. endchoice -- 1.6.2.1 From wuzhangjin@gmail.com Fri Nov 6 14:12:47 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 06 Nov 2009 14:12:53 +0100 (CET) Received: from mail-pw0-f45.google.com ([209.85.160.45]:42344 "EHLO mail-pw0-f45.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492734AbZKFNMH (ORCPT ); Fri, 6 Nov 2009 14:12:07 +0100 Received: by pwi15 with SMTP id 15so646646pwi.24 for ; Fri, 06 Nov 2009 05:12:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer:in-reply-to:references:in-reply-to:references; bh=dPUS8WnhsQugPgviv9O3ELH6TD0t5cbmEn29wS0xZ3M=; b=ks5w+hNoJq9eBJcWUQNLsZwPB34afCwObmNwgSdV3ATRrO3OTWColho98+5sryZMGt LSv3chbNKdS3DGu6Ms0OLwIIwU1nMuMfYW3dH5NzV4azTr1ISXQ+CerqKEd002iXOw1f znVFew5GzcANAz5TGjLX07ruL9xBiMI09omFs= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; b=agbWVhmc25BPuEKQsBkQyZ22+EGa+USk95DO0NEhKgErs791TcdbiG2GULNeHJmqsT tDZ1hpwr3oEWUeq9KQJT+zBgib3ywxuvVUaH8+d8WaakmdHRZKV35wrsmtlVYAfrPgv9 //LPkfwtYSZU3/jZ8YRAd7ERd13U5y/50rLD4= Received: by 10.114.187.37 with SMTP id k37mr6704124waf.49.1257513120997; Fri, 06 Nov 2009 05:12:00 -0800 (PST) Received: from localhost.localdomain ([222.92.8.142]) by mx.google.com with ESMTPS id 20sm26431pxi.7.2009.11.06.05.11.56 (version=TLSv1/SSLv3 cipher=RC4-MD5); Fri, 06 Nov 2009 05:12:00 -0800 (PST) From: Wu Zhangjin To: Ralf Baechle Cc: Arnaud Patard , zhangfx@lemote.com, yanh@lemote.com, huhb@lemote.com, Nicholas Mc Guire , Wu Zhangjin , linux-mips@linux-mips.org Subject: [PATCH -queue v1 2/7] [loongson] lemote-2f: rtc: enable legacy RTC driver Date: Fri, 6 Nov 2009 21:11:27 +0800 Message-Id: <588574ed5910292f2728072ca147add2ae342778.1257510612.git.wuzhangjin@gmail.com> X-Mailer: git-send-email 1.6.2.1 In-Reply-To: <17e5d58a0cd7273b81c7151b7f7f2096c9694b59.1257510612.git.wuzhangjin@gmail.com> References: <17e5d58a0cd7273b81c7151b7f7f2096c9694b59.1257510612.git.wuzhangjin@gmail.com> In-Reply-To: References: Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24724 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips From: Wu Zhangjin Currently, RTC_LIB is not available on loongson family machines(need extra patches to enable it), but the legacy RTC driver works well on them. Herein, We just deselect RTC_LIB and make the legacy RTC driver as a choice to not break the hwclock relative tools on these machines. After the relative patches for RTC_LIB upstream (http://www.linux-mips.org/archives/linux-mips/2009-11/msg00093.html), we will be safe to Remove this patch at that time, but currently, this is need. Signed-off-by: Wu Zhangjin --- arch/mips/Kconfig | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index d00c953..240a3ca 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -7,7 +7,7 @@ config MIPS select HAVE_ARCH_KGDB # Horrible source of confusion. Die, die, die ... select EMBEDDED - select RTC_LIB if !LEMOTE_FULOONG2E + select RTC_LIB if !MACH_LOONGSON mainmenu "Linux/MIPS Kernel Configuration" -- 1.6.2.1 From wuzhangjin@gmail.com Fri Nov 6 14:13:11 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 06 Nov 2009 14:13:18 +0100 (CET) Received: from mail-px0-f188.google.com ([209.85.216.188]:51511 "EHLO mail-px0-f188.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492739AbZKFNML (ORCPT ); Fri, 6 Nov 2009 14:12:11 +0100 Received: by mail-px0-f188.google.com with SMTP id 26so367449pxi.21 for ; Fri, 06 Nov 2009 05:12:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer:in-reply-to:references:in-reply-to:references; bh=CwtHGOc7jA0MwQiMIJgtumm0b1ojgRXQEOUYzGds3D0=; b=ORqkGTf/CWDBAQ/U5J4sQl9Y91PZOjfuEQ5poiUQaCFtKBLrg2REDrKnr9oeSTkgdP 309xA9X/unpzKbcT9cRt+NQVRlGQvwg3KnJLNM9ttb8JsEfTTeKmbQeI/7xO2t011lMN nU3jmCFq/xpUTTq7IeyXUKH7ZaC5u6Rc32AnI= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; b=o6hVDLDoSvQuaPr8lZV8nZQgn4Busjma5CQskdDKQHYlSSsccQOXGTR6+9fqWmpOc+ 5TY6CrHQENH14WDSfrBg641QBI7HRZnwt647EdHXGhBjb+A5/cd9LZp6U5wIkjNXRlis bJSc67ffxVHplUJKiICXvhHAz1Hq8fYHdACpM= Received: by 10.114.7.9 with SMTP id 9mr6661328wag.71.1257513129711; Fri, 06 Nov 2009 05:12:09 -0800 (PST) Received: from localhost.localdomain ([222.92.8.142]) by mx.google.com with ESMTPS id 20sm26431pxi.7.2009.11.06.05.12.01 (version=TLSv1/SSLv3 cipher=RC4-MD5); Fri, 06 Nov 2009 05:12:09 -0800 (PST) From: Wu Zhangjin To: Ralf Baechle Cc: Arnaud Patard , zhangfx@lemote.com, yanh@lemote.com, huhb@lemote.com, Nicholas Mc Guire , Wu Zhangjin , linux-mips@linux-mips.org Subject: [PATCH -queue v1 3/7] [loongson] lemote-2f: add basic cs5536 vsm support Date: Fri, 6 Nov 2009 21:11:28 +0800 Message-Id: <7affa8fce1f55b817aff1c64f823824f6809dd85.1257510612.git.wuzhangjin@gmail.com> X-Mailer: git-send-email 1.6.2.1 In-Reply-To: <588574ed5910292f2728072ca147add2ae342778.1257510612.git.wuzhangjin@gmail.com> References: <17e5d58a0cd7273b81c7151b7f7f2096c9694b59.1257510612.git.wuzhangjin@gmail.com> <588574ed5910292f2728072ca147add2ae342778.1257510612.git.wuzhangjin@gmail.com> In-Reply-To: References: Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24725 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips From: Wu Zhangjin Lemote loongson2f family machines use cs5536 as their south bridge, need these lowlevel interfaces to access the devices on cs5536. This patch try to virtulize the legacy devices on cs5536 as PCI devices, So, users can access the PCI configure space of cs5536 directly as a normal multi-function PCI device which follows the PCI-2.2 spec. Signed-off-by: Wu Zhangjin --- .../mips/include/asm/mach-loongson/cs5536/cs5536.h | 305 +++++++++++++++++++ .../include/asm/mach-loongson/cs5536/cs5536_pci.h | 153 ++++++++++ .../include/asm/mach-loongson/cs5536/cs5536_vsm.h | 31 ++ arch/mips/loongson/Kconfig | 3 + arch/mips/loongson/common/Makefile | 6 + arch/mips/loongson/common/cs5536/Makefile | 8 + arch/mips/loongson/common/cs5536/cs5536_acc.c | 148 +++++++++ arch/mips/loongson/common/cs5536/cs5536_ehci.c | 158 ++++++++++ arch/mips/loongson/common/cs5536/cs5536_ide.c | 185 ++++++++++++ arch/mips/loongson/common/cs5536/cs5536_isa.c | 316 ++++++++++++++++++++ arch/mips/loongson/common/cs5536/cs5536_ohci.c | 153 ++++++++++ arch/mips/loongson/common/cs5536/cs5536_pci.c | 87 ++++++ 12 files changed, 1553 insertions(+), 0 deletions(-) create mode 100644 arch/mips/include/asm/mach-loongson/cs5536/cs5536.h create mode 100644 arch/mips/include/asm/mach-loongson/cs5536/cs5536_pci.h create mode 100644 arch/mips/include/asm/mach-loongson/cs5536/cs5536_vsm.h create mode 100644 arch/mips/loongson/common/cs5536/Makefile create mode 100644 arch/mips/loongson/common/cs5536/cs5536_acc.c create mode 100644 arch/mips/loongson/common/cs5536/cs5536_ehci.c create mode 100644 arch/mips/loongson/common/cs5536/cs5536_ide.c create mode 100644 arch/mips/loongson/common/cs5536/cs5536_isa.c create mode 100644 arch/mips/loongson/common/cs5536/cs5536_ohci.c create mode 100644 arch/mips/loongson/common/cs5536/cs5536_pci.c diff --git a/arch/mips/include/asm/mach-loongson/cs5536/cs5536.h b/arch/mips/include/asm/mach-loongson/cs5536/cs5536.h new file mode 100644 index 0000000..021f77c --- /dev/null +++ b/arch/mips/include/asm/mach-loongson/cs5536/cs5536.h @@ -0,0 +1,305 @@ +/* + * The header file of cs5536 sourth bridge. + * + * Copyright (C) 2007 Lemote, Inc. + * Author : jlliu + */ + +#ifndef _CS5536_H +#define _CS5536_H + +#include + +extern void _rdmsr(u32 msr, u32 *hi, u32 *lo); +extern void _wrmsr(u32 msr, u32 hi, u32 lo); + +/* + * MSR module base + */ +#define CS5536_SB_MSR_BASE (0x00000000) +#define CS5536_GLIU_MSR_BASE (0x10000000) +#define CS5536_ILLEGAL_MSR_BASE (0x20000000) +#define CS5536_USB_MSR_BASE (0x40000000) +#define CS5536_IDE_MSR_BASE (0x60000000) +#define CS5536_DIVIL_MSR_BASE (0x80000000) +#define CS5536_ACC_MSR_BASE (0xa0000000) +#define CS5536_UNUSED_MSR_BASE (0xc0000000) +#define CS5536_GLCP_MSR_BASE (0xe0000000) + +#define SB_MSR_REG(offset) (CS5536_SB_MSR_BASE | (offset)) +#define GLIU_MSR_REG(offset) (CS5536_GLIU_MSR_BASE | (offset)) +#define ILLEGAL_MSR_REG(offset) (CS5536_ILLEGAL_MSR_BASE | (offset)) +#define USB_MSR_REG(offset) (CS5536_USB_MSR_BASE | (offset)) +#define IDE_MSR_REG(offset) (CS5536_IDE_MSR_BASE | (offset)) +#define DIVIL_MSR_REG(offset) (CS5536_DIVIL_MSR_BASE | (offset)) +#define ACC_MSR_REG(offset) (CS5536_ACC_MSR_BASE | (offset)) +#define UNUSED_MSR_REG(offset) (CS5536_UNUSED_MSR_BASE | (offset)) +#define GLCP_MSR_REG(offset) (CS5536_GLCP_MSR_BASE | (offset)) + +/* + * BAR SPACE OF VIRTUAL PCI : + * range for pci probe use, length is the actual size. + */ +/* IO space for all DIVIL modules */ +#define CS5536_IRQ_RANGE 0xffffffe0 /* USERD FOR PCI PROBE */ +#define CS5536_IRQ_LENGTH 0x20 /* THE REGS ACTUAL LENGTH */ +#define CS5536_SMB_RANGE 0xfffffff8 +#define CS5536_SMB_LENGTH 0x08 +#define CS5536_GPIO_RANGE 0xffffff00 +#define CS5536_GPIO_LENGTH 0x100 +#define CS5536_MFGPT_RANGE 0xffffffc0 +#define CS5536_MFGPT_LENGTH 0x40 +#define CS5536_ACPI_RANGE 0xffffffe0 +#define CS5536_ACPI_LENGTH 0x20 +#define CS5536_PMS_RANGE 0xffffff80 +#define CS5536_PMS_LENGTH 0x80 +/* IO space for IDE */ +#define CS5536_IDE_RANGE 0xfffffff0 +#define CS5536_IDE_LENGTH 0x10 +/* IO space for ACC */ +#define CS5536_ACC_RANGE 0xffffff80 +#define CS5536_ACC_LENGTH 0x80 +/* MEM space for ALL USB modules */ +#define CS5536_OHCI_RANGE 0xfffff000 +#define CS5536_OHCI_LENGTH 0x1000 +#define CS5536_EHCI_RANGE 0xfffff000 +#define CS5536_EHCI_LENGTH 0x1000 + +/* + * PCI MSR ACCESS + */ +#define PCI_MSR_CTRL 0xF0 +#define PCI_MSR_ADDR 0xF4 +#define PCI_MSR_DATA_LO 0xF8 +#define PCI_MSR_DATA_HI 0xFC + +/**************** MSR *****************************/ + +/* + * GLIU STANDARD MSR + */ +#define GLIU_CAP 0x00 +#define GLIU_CONFIG 0x01 +#define GLIU_SMI 0x02 +#define GLIU_ERROR 0x03 +#define GLIU_PM 0x04 +#define GLIU_DIAG 0x05 + +/* + * GLIU SPEC. MSR + */ +#define GLIU_P2D_BM0 0x20 +#define GLIU_P2D_BM1 0x21 +#define GLIU_P2D_BM2 0x22 +#define GLIU_P2D_BMK0 0x23 +#define GLIU_P2D_BMK1 0x24 +#define GLIU_P2D_BM3 0x25 +#define GLIU_P2D_BM4 0x26 +#define GLIU_COH 0x80 +#define GLIU_PAE 0x81 +#define GLIU_ARB 0x82 +#define GLIU_ASMI 0x83 +#define GLIU_AERR 0x84 +#define GLIU_DEBUG 0x85 +#define GLIU_PHY_CAP 0x86 +#define GLIU_NOUT_RESP 0x87 +#define GLIU_NOUT_WDATA 0x88 +#define GLIU_WHOAMI 0x8B +#define GLIU_SLV_DIS 0x8C +#define GLIU_IOD_BM0 0xE0 +#define GLIU_IOD_BM1 0xE1 +#define GLIU_IOD_BM2 0xE2 +#define GLIU_IOD_BM3 0xE3 +#define GLIU_IOD_BM4 0xE4 +#define GLIU_IOD_BM5 0xE5 +#define GLIU_IOD_BM6 0xE6 +#define GLIU_IOD_BM7 0xE7 +#define GLIU_IOD_BM8 0xE8 +#define GLIU_IOD_BM9 0xE9 +#define GLIU_IOD_SC0 0xEA +#define GLIU_IOD_SC1 0xEB +#define GLIU_IOD_SC2 0xEC +#define GLIU_IOD_SC3 0xED +#define GLIU_IOD_SC4 0xEE +#define GLIU_IOD_SC5 0xEF +#define GLIU_IOD_SC6 0xF0 +#define GLIU_IOD_SC7 0xF1 + +/* + * SB STANDARD + */ +#define SB_CAP 0x00 +#define SB_CONFIG 0x01 +#define SB_SMI 0x02 +#define SB_ERROR 0x03 +#define SB_MAR_ERR_EN 0x00000001 +#define SB_TAR_ERR_EN 0x00000002 +#define SB_RSVD_BIT1 0x00000004 +#define SB_EXCEP_ERR_EN 0x00000008 +#define SB_SYSE_ERR_EN 0x00000010 +#define SB_PARE_ERR_EN 0x00000020 +#define SB_TAS_ERR_EN 0x00000040 +#define SB_MAR_ERR_FLAG 0x00010000 +#define SB_TAR_ERR_FLAG 0x00020000 +#define SB_RSVD_BIT2 0x00040000 +#define SB_EXCEP_ERR_FLAG 0x00080000 +#define SB_SYSE_ERR_FLAG 0x00100000 +#define SB_PARE_ERR_FLAG 0x00200000 +#define SB_TAS_ERR_FLAG 0x00400000 +#define SB_PM 0x04 +#define SB_DIAG 0x05 + +/* + * SB SPEC. + */ +#define SB_CTRL 0x10 +#define SB_R0 0x20 +#define SB_R1 0x21 +#define SB_R2 0x22 +#define SB_R3 0x23 +#define SB_R4 0x24 +#define SB_R5 0x25 +#define SB_R6 0x26 +#define SB_R7 0x27 +#define SB_R8 0x28 +#define SB_R9 0x29 +#define SB_R10 0x2A +#define SB_R11 0x2B +#define SB_R12 0x2C +#define SB_R13 0x2D +#define SB_R14 0x2E +#define SB_R15 0x2F + +/* + * GLCP STANDARD + */ +#define GLCP_CAP 0x00 +#define GLCP_CONFIG 0x01 +#define GLCP_SMI 0x02 +#define GLCP_ERROR 0x03 +#define GLCP_PM 0x04 +#define GLCP_DIAG 0x05 + +/* + * GLCP SPEC. + */ +#define GLCP_CLK_DIS_DELAY 0x08 +#define GLCP_PM_CLK_DISABLE 0x09 +#define GLCP_GLB_PM 0x0B +#define GLCP_DBG_OUT 0x0C +#define GLCP_RSVD1 0x0D +#define GLCP_SOFT_COM 0x0E +#define SOFT_BAR_SMB_FLAG 0x00000001 +#define SOFT_BAR_GPIO_FLAG 0x00000002 +#define SOFT_BAR_MFGPT_FLAG 0x00000004 +#define SOFT_BAR_IRQ_FLAG 0x00000008 +#define SOFT_BAR_PMS_FLAG 0x00000010 +#define SOFT_BAR_ACPI_FLAG 0x00000020 +#define SOFT_BAR_IDE_FLAG 0x00000400 +#define SOFT_BAR_ACC_FLAG 0x00000800 +#define SOFT_BAR_OHCI_FLAG 0x00001000 +#define SOFT_BAR_EHCI_FLAG 0x00002000 +#define GLCP_RSVD2 0x0F +#define GLCP_CLK_OFF 0x10 +#define GLCP_CLK_ACTIVE 0x11 +#define GLCP_CLK_DISABLE 0x12 +#define GLCP_CLK4ACK 0x13 +#define GLCP_SYS_RST 0x14 +#define GLCP_RSVD3 0x15 +#define GLCP_DBG_CLK_CTRL 0x16 +#define GLCP_CHIP_REV_ID 0x17 + +/* PIC */ +#define PIC_YSEL_LOW 0x20 +#define PIC_YSEL_LOW_USB_SHIFT 8 +#define PIC_YSEL_LOW_ACC_SHIFT 16 +#define PIC_YSEL_LOW_FLASH_SHIFT 24 +#define PIC_YSEL_HIGH 0x21 +#define PIC_ZSEL_LOW 0x22 +#define PIC_ZSEL_HIGH 0x23 +#define PIC_IRQM_PRIM 0x24 +#define PIC_IRQM_LPC 0x25 +#define PIC_XIRR_STS_LOW 0x26 +#define PIC_XIRR_STS_HIGH 0x27 +#define PCI_SHDW 0x34 + +/* + * DIVIL STANDARD + */ +#define DIVIL_CAP 0x00 +#define DIVIL_CONFIG 0x01 +#define DIVIL_SMI 0x02 +#define DIVIL_ERROR 0x03 +#define DIVIL_PM 0x04 +#define DIVIL_DIAG 0x05 + +/* + * DIVIL SPEC. + */ +#define DIVIL_LBAR_IRQ 0x08 +#define DIVIL_LBAR_KEL 0x09 +#define DIVIL_LBAR_SMB 0x0B +#define DIVIL_LBAR_GPIO 0x0C +#define DIVIL_LBAR_MFGPT 0x0D +#define DIVIL_LBAR_ACPI 0x0E +#define DIVIL_LBAR_PMS 0x0F +#define DIVIL_LEG_IO 0x14 +#define DIVIL_BALL_OPTS 0x15 +#define DIVIL_SOFT_IRQ 0x16 +#define DIVIL_SOFT_RESET 0x17 + +/* MFGPT */ +#define MFGPT_IRQ 0x28 + +/* + * IDE STANDARD + */ +#define IDE_CAP 0x00 +#define IDE_CONFIG 0x01 +#define IDE_SMI 0x02 +#define IDE_ERROR 0x03 +#define IDE_PM 0x04 +#define IDE_DIAG 0x05 + +/* + * IDE SPEC. + */ +#define IDE_IO_BAR 0x08 +#define IDE_CFG 0x10 +#define IDE_DTC 0x12 +#define IDE_CAST 0x13 +#define IDE_ETC 0x14 +#define IDE_INTERNAL_PM 0x15 + +/* + * ACC STANDARD + */ +#define ACC_CAP 0x00 +#define ACC_CONFIG 0x01 +#define ACC_SMI 0x02 +#define ACC_ERROR 0x03 +#define ACC_PM 0x04 +#define ACC_DIAG 0x05 + +/* + * USB STANDARD + */ +#define USB_CAP 0x00 +#define USB_CONFIG 0x01 +#define USB_SMI 0x02 +#define USB_ERROR 0x03 +#define USB_PM 0x04 +#define USB_DIAG 0x05 + +/* + * USB SPEC. + */ +#define USB_OHCI 0x08 +#define USB_EHCI 0x09 + +/****************** NATIVE ***************************/ +/* GPIO : I/O SPACE; REG : 32BITS */ +#define GPIOL_OUT_VAL 0x00 +#define GPIOL_OUT_EN 0x04 + +#endif /* _CS5536_H */ diff --git a/arch/mips/include/asm/mach-loongson/cs5536/cs5536_pci.h b/arch/mips/include/asm/mach-loongson/cs5536/cs5536_pci.h new file mode 100644 index 0000000..0dca9c8 --- /dev/null +++ b/arch/mips/include/asm/mach-loongson/cs5536/cs5536_pci.h @@ -0,0 +1,153 @@ +/* + * the definition file of cs5536 Virtual Support Module(VSM). + * pci configuration space can be accessed through the VSM, so + * there is no need of the MSR read/write now, except the spec. + * MSR registers which are not implemented yet. + * + * Copyright (C) 2007 Lemote Inc. + * Author : jlliu, liujl@lemote.com + */ + +#ifndef _CS5536_PCI_H +#define _CS5536_PCI_H + +#include +#include + +extern void cs5536_pci_conf_write4(int function, int reg, u32 value); +extern u32 cs5536_pci_conf_read4(int function, int reg); + +#define CS5536_ACC_INTR 9 +#define CS5536_IDE_INTR 14 +#define CS5536_USB_INTR 11 +#define CS5536_MFGPT_INTR 5 +#define CS5536_UART1_INTR 4 +#define CS5536_UART2_INTR 3 + +/************** PCI BUS DEVICE FUNCTION ***************/ + +/* + * PCI bus device function + */ +#define PCI_BUS_CS5536 0 +#define PCI_IDSEL_CS5536 14 + +/********** STANDARD PCI-2.2 EXPANSION ****************/ + +/* + * PCI configuration space + * we have to virtualize the PCI configure space head, so we should + * define the necessary IDs and some others. + */ + +/* CONFIG of PCI VENDOR ID*/ +#define CFG_PCI_VENDOR_ID(mod_dev_id, sys_vendor_id) \ + (((mod_dev_id) << 16) | (sys_vendor_id)) + +/* VENDOR ID */ +#define CS5536_VENDOR_ID 0x1022 + +/* DEVICE ID */ +#define CS5536_ISA_DEVICE_ID 0x2090 +#define CS5536_IDE_DEVICE_ID 0x209a +#define CS5536_ACC_DEVICE_ID 0x2093 +#define CS5536_OHCI_DEVICE_ID 0x2094 +#define CS5536_EHCI_DEVICE_ID 0x2095 + +/* CLASS CODE : CLASS SUB-CLASS INTERFACE */ +#define CS5536_ISA_CLASS_CODE 0x060100 +#define CS5536_IDE_CLASS_CODE 0x010180 +#define CS5536_ACC_CLASS_CODE 0x040100 +#define CS5536_OHCI_CLASS_CODE 0x0C0310 +#define CS5536_EHCI_CLASS_CODE 0x0C0320 + +/* BHLC : BIST HEADER-TYPE LATENCY-TIMER CACHE-LINE-SIZE */ + +#define CFG_PCI_CACHE_LINE_SIZE(header_type, latency_timer) \ + ((PCI_NONE_BIST << 24) | ((header_type) << 16) \ + | ((latency_timer) << 8) | PCI_NORMAL_CACHE_LINE_SIZE); + +#define PCI_NONE_BIST 0x00 /* RO not implemented yet. */ +#define PCI_BRIDGE_HEADER_TYPE 0x80 /* RO */ +#define PCI_NORMAL_HEADER_TYPE 0x00 +#define PCI_NORMAL_LATENCY_TIMER 0x00 +#define PCI_NORMAL_CACHE_LINE_SIZE 0x08 /* RW */ + +/* BAR */ +#define PCI_BAR0_REG 0x10 +#define PCI_BAR1_REG 0x14 +#define PCI_BAR2_REG 0x18 +#define PCI_BAR3_REG 0x1c +#define PCI_BAR4_REG 0x20 +#define PCI_BAR5_REG 0x24 +#define PCI_BAR_COUNT 6 +#define PCI_BAR_RANGE_MASK 0xFFFFFFFF + +/* CARDBUS CIS POINTER */ +#define PCI_CARDBUS_CIS_POINTER 0x00000000 + +/* SUBSYSTEM VENDOR ID */ +#define CS5536_SUB_VENDOR_ID CS5536_VENDOR_ID + +/* SUBSYSTEM ID */ +#define CS5536_ISA_SUB_ID CS5536_ISA_DEVICE_ID +#define CS5536_IDE_SUB_ID CS5536_IDE_DEVICE_ID +#define CS5536_ACC_SUB_ID CS5536_ACC_DEVICE_ID +#define CS5536_OHCI_SUB_ID CS5536_OHCI_DEVICE_ID +#define CS5536_EHCI_SUB_ID CS5536_EHCI_DEVICE_ID + +/* EXPANSION ROM BAR */ +#define PCI_EXPANSION_ROM_BAR 0x00000000 + +/* CAPABILITIES POINTER */ +#define PCI_CAPLIST_POINTER 0x00000000 +#define PCI_CAPLIST_USB_POINTER 0x40 +/* INTERRUPT */ + +#define CFG_PCI_INTERRUPT_LINE(pin, mod_intr) \ + ((PCI_MAX_LATENCY << 24) | (PCI_MIN_GRANT << 16) | \ + ((pin) << 8) | (mod_intr)) + +#define PCI_MAX_LATENCY 0x40 +#define PCI_MIN_GRANT 0x00 +#define PCI_DEFAULT_PIN 0x01 + +/*********** EXPANSION PCI REG ************************/ + +/* + * ISA EXPANSION + */ +#define PCI_UART1_INT_REG 0x50 +#define PCI_UART2_INT_REG 0x54 +#define PCI_ISA_FIXUP_REG 0x58 + +/* + * IDE EXPANSION + */ +#define PCI_IDE_CFG_REG 0x40 +#define CS5536_IDE_FLASH_SIGNATURE 0xDEADBEEF +#define PCI_IDE_DTC_REG 0x48 +#define PCI_IDE_CAST_REG 0x4C +#define PCI_IDE_ETC_REG 0x50 +#define PCI_IDE_PM_REG 0x54 +#define PCI_IDE_INT_REG 0x60 + +/* + * ACC EXPANSION + */ +#define PCI_ACC_INT_REG 0x50 + +/* + * OHCI EXPANSION : INTTERUPT IS IMPLEMENTED BY THE OHCI + */ +#define PCI_OHCI_PM_REG 0x40 +#define PCI_OHCI_INT_REG 0x50 + +/* + * EHCI EXPANSION + */ +#define PCI_EHCI_LEGSMIEN_REG 0x50 +#define PCI_EHCI_LEGSMISTS_REG 0x54 +#define PCI_EHCI_FLADJ_REG 0x60 + +#endif /* _CS5536_PCI_H_ */ diff --git a/arch/mips/include/asm/mach-loongson/cs5536/cs5536_vsm.h b/arch/mips/include/asm/mach-loongson/cs5536/cs5536_vsm.h new file mode 100644 index 0000000..6305bea --- /dev/null +++ b/arch/mips/include/asm/mach-loongson/cs5536/cs5536_vsm.h @@ -0,0 +1,31 @@ +/* + * the read/write interfaces for Virtual Support Module(VSM) + * + * Copyright (C) 2009 Lemote, Inc. + * Author: Wu Zhangjin + */ + +#ifndef _CS5536_VSM_H +#define _CS5536_VSM_H + +#include + +typedef void (*cs5536_pci_vsm_write)(int reg, u32 value); +typedef u32 (*cs5536_pci_vsm_read)(int reg); + +#define DECLARE_CS5536_MODULE(name) \ +extern void pci_##name##_write_reg(int reg, u32 value); \ +extern u32 pci_##name##_read_reg(int reg); + +/* ide module */ +DECLARE_CS5536_MODULE(ide) +/* acc module */ +DECLARE_CS5536_MODULE(acc) +/* ohci module */ +DECLARE_CS5536_MODULE(ohci) +/* isa module */ +DECLARE_CS5536_MODULE(isa) +/* ehci module */ +DECLARE_CS5536_MODULE(ehci) + +#endif /* _CS5536_VSM_H */ diff --git a/arch/mips/loongson/Kconfig b/arch/mips/loongson/Kconfig index 9573406..3b0f5b7 100644 --- a/arch/mips/loongson/Kconfig +++ b/arch/mips/loongson/Kconfig @@ -58,3 +58,6 @@ config LEMOTE_MACH2F These family machines include fuloong2f mini PC, yeeloong2f notebook, LingLoong allinone PC and so forth. endchoice + +config CS5536 + bool diff --git a/arch/mips/loongson/common/Makefile b/arch/mips/loongson/common/Makefile index be6adf7..a82527f 100644 --- a/arch/mips/loongson/common/Makefile +++ b/arch/mips/loongson/common/Makefile @@ -10,3 +10,9 @@ obj-y += setup.o init.o cmdline.o env.o time.o reset.o irq.o \ # obj-$(CONFIG_EARLY_PRINTK) += early_printk.o obj-$(CONFIG_SERIAL_8250) += serial.o + +# +# Enable CS5536 Virtual Support Module(VSM) to virtulize the PCI configure +# space +# +obj-$(CONFIG_CS5536) += cs5536/ diff --git a/arch/mips/loongson/common/cs5536/Makefile b/arch/mips/loongson/common/cs5536/Makefile new file mode 100644 index 0000000..31657ee --- /dev/null +++ b/arch/mips/loongson/common/cs5536/Makefile @@ -0,0 +1,8 @@ +# +# Makefile for CS5536 support. +# + +obj-$(CONFIG_CS5536) += cs5536_pci.o cs5536_ide.o cs5536_acc.o cs5536_ohci.o \ + cs5536_isa.o cs5536_ehci.o + +EXTRA_CFLAGS += -Werror diff --git a/arch/mips/loongson/common/cs5536/cs5536_acc.c b/arch/mips/loongson/common/cs5536/cs5536_acc.c new file mode 100644 index 0000000..997752a --- /dev/null +++ b/arch/mips/loongson/common/cs5536/cs5536_acc.c @@ -0,0 +1,148 @@ +/* + * the ACC Virtual Support Module of AMD CS5536 + * + * Copyright (C) 2007 Lemote, Inc. + * Author : jlliu, liujl@lemote.com + * + * Copyright (C) 2009 Lemote, Inc. + * Author: Wu Zhangjin, wuzj@lemote.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include +#include + +/* + * acc_write: acc write transfering + */ + +void pci_acc_write_reg(int reg, u32 value) +{ + u32 hi = 0, lo = value; + + switch (reg) { + case PCI_COMMAND: + _rdmsr(GLIU_MSR_REG(GLIU_PAE), &hi, &lo); + if (value & PCI_COMMAND_MASTER) + lo |= (0x03 << 8); + else + lo &= ~(0x03 << 8); + _wrmsr(GLIU_MSR_REG(GLIU_PAE), hi, lo); + break; + case PCI_STATUS: + if (value & PCI_STATUS_PARITY) { + _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo); + if (lo & SB_PARE_ERR_FLAG) { + lo = (lo & 0x0000ffff) | SB_PARE_ERR_FLAG; + _wrmsr(SB_MSR_REG(SB_ERROR), hi, lo); + } + } + break; + case PCI_BAR0_REG: + if (value == PCI_BAR_RANGE_MASK) { + _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo); + lo |= SOFT_BAR_ACC_FLAG; + _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo); + } else if (value & 0x01) { + value &= 0xfffffffc; + hi = 0xA0000000 | ((value & 0x000ff000) >> 12); + lo = 0x000fff80 | ((value & 0x00000fff) << 20); + _wrmsr(GLIU_MSR_REG(GLIU_IOD_BM1), hi, lo); + } + break; + case PCI_ACC_INT_REG: + _rdmsr(DIVIL_MSR_REG(PIC_YSEL_LOW), &hi, &lo); + /* disable all the usb interrupt in PIC */ + lo &= ~(0xf << PIC_YSEL_LOW_ACC_SHIFT); + if (value) /* enable all the acc interrupt in PIC */ + lo |= (CS5536_ACC_INTR << PIC_YSEL_LOW_ACC_SHIFT); + _wrmsr(DIVIL_MSR_REG(PIC_YSEL_LOW), hi, lo); + break; + default: + break; + } +} + +/* + * acc_read: acc read transfering + */ + +u32 pci_acc_read_reg(int reg) +{ + u32 hi, lo; + u32 conf_data = 0; + + switch (reg) { + case PCI_VENDOR_ID: + conf_data = + CFG_PCI_VENDOR_ID(CS5536_ACC_DEVICE_ID, CS5536_VENDOR_ID); + break; + case PCI_COMMAND: + _rdmsr(GLIU_MSR_REG(GLIU_IOD_BM1), &hi, &lo); + if (((lo & 0xfff00000) || (hi & 0x000000ff)) + && ((hi & 0xf0000000) == 0xa0000000)) + conf_data |= PCI_COMMAND_IO; + _rdmsr(GLIU_MSR_REG(GLIU_PAE), &hi, &lo); + if ((lo & 0x300) == 0x300) + conf_data |= PCI_COMMAND_MASTER; + break; + case PCI_STATUS: + conf_data |= PCI_STATUS_66MHZ; + conf_data |= PCI_STATUS_FAST_BACK; + _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo); + if (lo & SB_PARE_ERR_FLAG) + conf_data |= PCI_STATUS_PARITY; + conf_data |= PCI_STATUS_DEVSEL_MEDIUM; + break; + case PCI_CLASS_REVISION: + _rdmsr(ACC_MSR_REG(ACC_CAP), &hi, &lo); + conf_data = lo & 0x000000ff; + conf_data |= (CS5536_ACC_CLASS_CODE << 8); + break; + case PCI_CACHE_LINE_SIZE: + conf_data = + CFG_PCI_CACHE_LINE_SIZE(PCI_NORMAL_HEADER_TYPE, + PCI_NORMAL_LATENCY_TIMER); + break; + case PCI_BAR0_REG: + _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo); + if (lo & SOFT_BAR_ACC_FLAG) { + conf_data = CS5536_ACC_RANGE | + PCI_BASE_ADDRESS_SPACE_IO; + lo &= ~SOFT_BAR_ACC_FLAG; + _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo); + } else { + _rdmsr(GLIU_MSR_REG(GLIU_IOD_BM1), &hi, &lo); + conf_data = (hi & 0x000000ff) << 12; + conf_data |= (lo & 0xfff00000) >> 20; + conf_data |= 0x01; + conf_data &= ~0x02; + } + break; + case PCI_CARDBUS_CIS: + conf_data = PCI_CARDBUS_CIS_POINTER; + break; + case PCI_SUBSYSTEM_VENDOR_ID: + conf_data = + CFG_PCI_VENDOR_ID(CS5536_ACC_SUB_ID, CS5536_SUB_VENDOR_ID); + break; + case PCI_ROM_ADDRESS: + conf_data = PCI_EXPANSION_ROM_BAR; + break; + case PCI_CAPABILITY_LIST: + conf_data = PCI_CAPLIST_USB_POINTER; + break; + case PCI_INTERRUPT_LINE: + conf_data = + CFG_PCI_INTERRUPT_LINE(PCI_DEFAULT_PIN, CS5536_ACC_INTR); + break; + default: + break; + } + + return conf_data; +} diff --git a/arch/mips/loongson/common/cs5536/cs5536_ehci.c b/arch/mips/loongson/common/cs5536/cs5536_ehci.c new file mode 100644 index 0000000..74f9c59 --- /dev/null +++ b/arch/mips/loongson/common/cs5536/cs5536_ehci.c @@ -0,0 +1,158 @@ +/* + * the EHCI Virtual Support Module of AMD CS5536 + * + * Copyright (C) 2007 Lemote, Inc. + * Author : jlliu, liujl@lemote.com + * + * Copyright (C) 2009 Lemote, Inc. + * Author: Wu Zhangjin, wuzj@lemote.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include +#include + +void pci_ehci_write_reg(int reg, u32 value) +{ + u32 hi = 0, lo = value; + + switch (reg) { + case PCI_COMMAND: + _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo); + if (value & PCI_COMMAND_MASTER) + hi |= PCI_COMMAND_MASTER; + else + hi &= ~PCI_COMMAND_MASTER; + + if (value & PCI_COMMAND_MEMORY) + hi |= PCI_COMMAND_MEMORY; + else + hi &= ~PCI_COMMAND_MEMORY; + _wrmsr(USB_MSR_REG(USB_EHCI), hi, lo); + break; + case PCI_STATUS: + if (value & PCI_STATUS_PARITY) { + _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo); + if (lo & SB_PARE_ERR_FLAG) { + lo = (lo & 0x0000ffff) | SB_PARE_ERR_FLAG; + _wrmsr(SB_MSR_REG(SB_ERROR), hi, lo); + } + } + break; + case PCI_BAR0_REG: + if (value == PCI_BAR_RANGE_MASK) { + _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo); + lo |= SOFT_BAR_EHCI_FLAG; + _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo); + } else if ((value & 0x01) == 0x00) { + _wrmsr(USB_MSR_REG(USB_EHCI), hi, lo); + + value &= 0xfffffff0; + hi = 0x40000000 | ((value & 0xff000000) >> 24); + lo = 0x000fffff | ((value & 0x00fff000) << 8); + _wrmsr(GLIU_MSR_REG(GLIU_P2D_BM4), hi, lo); + } + break; + case PCI_EHCI_LEGSMIEN_REG: + _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo); + hi &= 0x003f0000; + hi |= (value & 0x3f) << 16; + _wrmsr(USB_MSR_REG(USB_EHCI), hi, lo); + break; + case PCI_EHCI_FLADJ_REG: + _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo); + hi &= ~0x00003f00; + hi |= value & 0x00003f00; + _wrmsr(USB_MSR_REG(USB_EHCI), hi, lo); + break; + default: + break; + } +} + +u32 pci_ehci_read_reg(int reg) +{ + u32 conf_data = 0; + u32 hi, lo; + + switch (reg) { + case PCI_VENDOR_ID: + conf_data = + CFG_PCI_VENDOR_ID(CS5536_EHCI_DEVICE_ID, CS5536_VENDOR_ID); + break; + case PCI_COMMAND: + _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo); + if (hi & PCI_COMMAND_MASTER) + conf_data |= PCI_COMMAND_MASTER; + if (hi & PCI_COMMAND_MEMORY) + conf_data |= PCI_COMMAND_MEMORY; + break; + case PCI_STATUS: + conf_data |= PCI_STATUS_66MHZ; + conf_data |= PCI_STATUS_FAST_BACK; + _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo); + if (lo & SB_PARE_ERR_FLAG) + conf_data |= PCI_STATUS_PARITY; + conf_data |= PCI_STATUS_DEVSEL_MEDIUM; + break; + case PCI_CLASS_REVISION: + _rdmsr(USB_MSR_REG(USB_CAP), &hi, &lo); + conf_data = lo & 0x000000ff; + conf_data |= (CS5536_EHCI_CLASS_CODE << 8); + break; + case PCI_CACHE_LINE_SIZE: + conf_data = + CFG_PCI_CACHE_LINE_SIZE(PCI_NORMAL_HEADER_TYPE, + PCI_NORMAL_LATENCY_TIMER); + break; + case PCI_BAR0_REG: + _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo); + if (lo & SOFT_BAR_EHCI_FLAG) { + conf_data = CS5536_EHCI_RANGE | + PCI_BASE_ADDRESS_SPACE_MEMORY; + lo &= ~SOFT_BAR_EHCI_FLAG; + _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo); + } else { + _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo); + conf_data = lo & 0xfffff000; + } + break; + case PCI_CARDBUS_CIS: + conf_data = PCI_CARDBUS_CIS_POINTER; + break; + case PCI_SUBSYSTEM_VENDOR_ID: + conf_data = + CFG_PCI_VENDOR_ID(CS5536_EHCI_SUB_ID, CS5536_SUB_VENDOR_ID); + break; + case PCI_ROM_ADDRESS: + conf_data = PCI_EXPANSION_ROM_BAR; + break; + case PCI_CAPABILITY_LIST: + conf_data = PCI_CAPLIST_USB_POINTER; + break; + case PCI_INTERRUPT_LINE: + conf_data = + CFG_PCI_INTERRUPT_LINE(PCI_DEFAULT_PIN, CS5536_USB_INTR); + break; + case PCI_EHCI_LEGSMIEN_REG: + _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo); + conf_data = (hi & 0x003f0000) >> 16; + break; + case PCI_EHCI_LEGSMISTS_REG: + _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo); + conf_data = (hi & 0x3f000000) >> 24; + break; + case PCI_EHCI_FLADJ_REG: + _rdmsr(USB_MSR_REG(USB_EHCI), &hi, &lo); + conf_data = hi & 0x00003f00; + break; + default: + break; + } + + return conf_data; +} diff --git a/arch/mips/loongson/common/cs5536/cs5536_ide.c b/arch/mips/loongson/common/cs5536/cs5536_ide.c new file mode 100644 index 0000000..300c45d --- /dev/null +++ b/arch/mips/loongson/common/cs5536/cs5536_ide.c @@ -0,0 +1,185 @@ +/* + * the IDE Virtual Support Module of AMD CS5536 + * + * Copyright (C) 2007 Lemote, Inc. + * Author : jlliu, liujl@lemote.com + * + * Copyright (C) 2009 Lemote, Inc. + * Author: Wu Zhangjin, wuzj@lemote.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include +#include + +/* + * ide_write : ide write transfering + */ +void pci_ide_write_reg(int reg, u32 value) +{ + u32 hi = 0, lo = value; + + switch (reg) { + case PCI_COMMAND: + _rdmsr(GLIU_MSR_REG(GLIU_PAE), &hi, &lo); + if (value & PCI_COMMAND_MASTER) + lo |= (0x03 << 4); + else + lo &= ~(0x03 << 4); + _wrmsr(GLIU_MSR_REG(GLIU_PAE), hi, lo); + break; + case PCI_STATUS: + if (value & PCI_STATUS_PARITY) { + _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo); + if (lo & SB_PARE_ERR_FLAG) { + lo = (lo & 0x0000ffff) | SB_PARE_ERR_FLAG; + _wrmsr(SB_MSR_REG(SB_ERROR), hi, lo); + } + } + break; + case PCI_CACHE_LINE_SIZE: + value &= 0x0000ff00; + _rdmsr(SB_MSR_REG(SB_CTRL), &hi, &lo); + hi &= 0xffffff00; + hi |= (value >> 8); + _wrmsr(SB_MSR_REG(SB_CTRL), hi, lo); + break; + case PCI_BAR4_REG: + if (value == PCI_BAR_RANGE_MASK) { + _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo); + lo |= SOFT_BAR_IDE_FLAG; + _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo); + } else if (value & 0x01) { + lo = (value & 0xfffffff0) | 0x1; + _wrmsr(IDE_MSR_REG(IDE_IO_BAR), hi, lo); + + value &= 0xfffffffc; + hi = 0x60000000 | ((value & 0x000ff000) >> 12); + lo = 0x000ffff0 | ((value & 0x00000fff) << 20); + _wrmsr(GLIU_MSR_REG(GLIU_IOD_BM2), hi, lo); + } + break; + case PCI_IDE_CFG_REG: + if (value == CS5536_IDE_FLASH_SIGNATURE) { + _rdmsr(DIVIL_MSR_REG(DIVIL_BALL_OPTS), &hi, &lo); + lo |= 0x01; + _wrmsr(DIVIL_MSR_REG(DIVIL_BALL_OPTS), hi, lo); + } else + _wrmsr(IDE_MSR_REG(IDE_CFG), hi, lo); + break; + case PCI_IDE_DTC_REG: + _wrmsr(IDE_MSR_REG(IDE_DTC), hi, lo); + break; + case PCI_IDE_CAST_REG: + _wrmsr(IDE_MSR_REG(IDE_CAST), hi, lo); + break; + case PCI_IDE_ETC_REG: + _wrmsr(IDE_MSR_REG(IDE_ETC), hi, lo); + break; + case PCI_IDE_PM_REG: + _wrmsr(IDE_MSR_REG(IDE_INTERNAL_PM), hi, lo); + break; + default: + break; + } +} + +/* + * ide_read : ide read tranfering. + */ +u32 pci_ide_read_reg(int reg) +{ + u32 conf_data = 0; + u32 hi, lo; + + switch (reg) { + case PCI_VENDOR_ID: + conf_data = + CFG_PCI_VENDOR_ID(CS5536_IDE_DEVICE_ID, CS5536_VENDOR_ID); + break; + case PCI_COMMAND: + _rdmsr(IDE_MSR_REG(IDE_IO_BAR), &hi, &lo); + if (lo & 0xfffffff0) + conf_data |= PCI_COMMAND_IO; + _rdmsr(GLIU_MSR_REG(GLIU_PAE), &hi, &lo); + if ((lo & 0x30) == 0x30) + conf_data |= PCI_COMMAND_MASTER; + break; + case PCI_STATUS: + conf_data |= PCI_STATUS_66MHZ; + conf_data |= PCI_STATUS_FAST_BACK; + _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo); + if (lo & SB_PARE_ERR_FLAG) + conf_data |= PCI_STATUS_PARITY; + conf_data |= PCI_STATUS_DEVSEL_MEDIUM; + break; + case PCI_CLASS_REVISION: + _rdmsr(IDE_MSR_REG(IDE_CAP), &hi, &lo); + conf_data = lo & 0x000000ff; + conf_data |= (CS5536_IDE_CLASS_CODE << 8); + break; + case PCI_CACHE_LINE_SIZE: + _rdmsr(SB_MSR_REG(SB_CTRL), &hi, &lo); + hi &= 0x000000f8; + conf_data = CFG_PCI_CACHE_LINE_SIZE(PCI_NORMAL_HEADER_TYPE, hi); + break; + case PCI_BAR4_REG: + _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo); + if (lo & SOFT_BAR_IDE_FLAG) { + conf_data = CS5536_IDE_RANGE | + PCI_BASE_ADDRESS_SPACE_IO; + lo &= ~SOFT_BAR_IDE_FLAG; + _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo); + } else { + _rdmsr(IDE_MSR_REG(IDE_IO_BAR), &hi, &lo); + conf_data = lo & 0xfffffff0; + conf_data |= 0x01; + conf_data &= ~0x02; + } + break; + case PCI_CARDBUS_CIS: + conf_data = PCI_CARDBUS_CIS_POINTER; + break; + case PCI_SUBSYSTEM_VENDOR_ID: + conf_data = + CFG_PCI_VENDOR_ID(CS5536_IDE_SUB_ID, CS5536_SUB_VENDOR_ID); + break; + case PCI_ROM_ADDRESS: + conf_data = PCI_EXPANSION_ROM_BAR; + break; + case PCI_CAPABILITY_LIST: + conf_data = PCI_CAPLIST_POINTER; + break; + case PCI_INTERRUPT_LINE: + conf_data = + CFG_PCI_INTERRUPT_LINE(PCI_DEFAULT_PIN, CS5536_IDE_INTR); + break; + case PCI_IDE_CFG_REG: + _rdmsr(IDE_MSR_REG(IDE_CFG), &hi, &lo); + conf_data = lo; + break; + case PCI_IDE_DTC_REG: + _rdmsr(IDE_MSR_REG(IDE_DTC), &hi, &lo); + conf_data = lo; + break; + case PCI_IDE_CAST_REG: + _rdmsr(IDE_MSR_REG(IDE_CAST), &hi, &lo); + conf_data = lo; + break; + case PCI_IDE_ETC_REG: + _rdmsr(IDE_MSR_REG(IDE_ETC), &hi, &lo); + conf_data = lo; + case PCI_IDE_PM_REG: + _rdmsr(IDE_MSR_REG(IDE_INTERNAL_PM), &hi, &lo); + conf_data = lo; + break; + default: + break; + } + + return conf_data; +} diff --git a/arch/mips/loongson/common/cs5536/cs5536_isa.c b/arch/mips/loongson/common/cs5536/cs5536_isa.c new file mode 100644 index 0000000..f8b9921 --- /dev/null +++ b/arch/mips/loongson/common/cs5536/cs5536_isa.c @@ -0,0 +1,316 @@ +/* + * the ISA Virtual Support Module of AMD CS5536 + * + * Copyright (C) 2007 Lemote, Inc. + * Author : jlliu, liujl@lemote.com + * + * Copyright (C) 2009 Lemote, Inc. + * Author: Wu Zhangjin, wuzj@lemote.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include +#include + +/* common variables for PCI_ISA_READ/WRITE_BAR */ +static const u32 divil_msr_reg[6] = { + DIVIL_MSR_REG(DIVIL_LBAR_SMB), DIVIL_MSR_REG(DIVIL_LBAR_GPIO), + DIVIL_MSR_REG(DIVIL_LBAR_MFGPT), DIVIL_MSR_REG(DIVIL_LBAR_IRQ), + DIVIL_MSR_REG(DIVIL_LBAR_PMS), DIVIL_MSR_REG(DIVIL_LBAR_ACPI), +}; + +static const u32 soft_bar_flag[6] = { + SOFT_BAR_SMB_FLAG, SOFT_BAR_GPIO_FLAG, SOFT_BAR_MFGPT_FLAG, + SOFT_BAR_IRQ_FLAG, SOFT_BAR_PMS_FLAG, SOFT_BAR_ACPI_FLAG, +}; + +static const u32 sb_msr_reg[6] = { + SB_MSR_REG(SB_R0), SB_MSR_REG(SB_R1), SB_MSR_REG(SB_R2), + SB_MSR_REG(SB_R3), SB_MSR_REG(SB_R4), SB_MSR_REG(SB_R5), +}; + +static const u32 bar_space_range[6] = { + CS5536_SMB_RANGE, CS5536_GPIO_RANGE, CS5536_MFGPT_RANGE, + CS5536_IRQ_RANGE, CS5536_PMS_RANGE, CS5536_ACPI_RANGE, +}; + +static const int bar_space_len[6] = { + CS5536_SMB_LENGTH, CS5536_GPIO_LENGTH, CS5536_MFGPT_LENGTH, + CS5536_IRQ_LENGTH, CS5536_PMS_LENGTH, CS5536_ACPI_LENGTH, +}; + +/* + * enable the divil module bar space. + * + * For all the DIVIL module LBAR, you should control the DIVIL LBAR reg + * and the RCONFx(0~5) reg to use the modules. + */ +static void divil_lbar_enable(void) +{ + u32 hi, lo; + int offset; + + /* + * The DIVIL IRQ is not used yet. and make the RCONF0 reserved. + */ + + for (offset = DIVIL_LBAR_SMB; offset <= DIVIL_LBAR_PMS; offset++) { + _rdmsr(DIVIL_MSR_REG(offset), &hi, &lo); + hi |= 0x01; + _wrmsr(DIVIL_MSR_REG(DIVIL_LBAR_SMB), hi, lo); + } +} + +/* + * disable the divil module bar space. + */ +static void divil_lbar_disable(void) +{ + u32 hi, lo; + int offset; + + for (offset = DIVIL_LBAR_SMB; offset <= DIVIL_LBAR_PMS; offset++) { + _rdmsr(DIVIL_MSR_REG(offset), &hi, &lo); + hi &= ~0x01; + _wrmsr(DIVIL_MSR_REG(DIVIL_LBAR_SMB), hi, lo); + } +} + +/* + * BAR write: write value to the n BAR + */ + +void pci_isa_write_bar(int n, u32 value) +{ + u32 hi = 0, lo = value; + + if (value == PCI_BAR_RANGE_MASK) { + _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo); + lo |= soft_bar_flag[n]; + _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo); + } else if (value & 0x01) { + /* NATIVE reg */ + hi = 0x0000f001; + lo &= bar_space_range[n]; + _wrmsr(divil_msr_reg[n], hi, lo); + + /* RCONFx is 4bytes in units for I/O space */ + hi = ((value & 0x000ffffc) << 12) | + ((bar_space_len[n] - 4) << 12) | 0x01; + lo = ((value & 0x000ffffc) << 12) | 0x01; + _wrmsr(sb_msr_reg[n], hi, lo); + } +} + +/* + * BAR read: read the n BAR + */ + +u32 pci_isa_read_bar(int n) +{ + u32 conf_data = 0; + u32 hi, lo; + + _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo); + if (lo & soft_bar_flag[n]) { + conf_data = bar_space_range[n] | PCI_BASE_ADDRESS_SPACE_IO; + lo &= ~soft_bar_flag[n]; + _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo); + } else { + _rdmsr(divil_msr_reg[n], &hi, &lo); + conf_data = lo & bar_space_range[n]; + conf_data |= 0x01; + conf_data &= ~0x02; + } + return conf_data; +} + +/* + * isa_write : isa write transfering. + * we assume that the ISA is not the BUS MASTER! + */ + +void pci_isa_write_reg(int reg, u32 value) +{ + u32 hi = 0, lo = value; + u32 temp; + + switch (reg) { + case PCI_COMMAND: + if (value & PCI_COMMAND_IO) + divil_lbar_enable(); + else + divil_lbar_disable(); + break; + case PCI_STATUS: + _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo); + temp = lo & 0x0000ffff; + if ((value & PCI_STATUS_SIG_TARGET_ABORT) && + (lo & SB_TAS_ERR_EN)) + temp |= SB_TAS_ERR_FLAG; + + if ((value & PCI_STATUS_REC_TARGET_ABORT) && + (lo & SB_TAR_ERR_EN)) + temp |= SB_TAR_ERR_FLAG; + + if ((value & PCI_STATUS_REC_MASTER_ABORT) + && (lo & SB_MAR_ERR_EN)) + temp |= SB_MAR_ERR_FLAG; + + if ((value & PCI_STATUS_DETECTED_PARITY) + && (lo & SB_PARE_ERR_EN)) + temp |= SB_PARE_ERR_FLAG; + + lo = temp; + _wrmsr(SB_MSR_REG(SB_ERROR), hi, lo); + break; + case PCI_CACHE_LINE_SIZE: + value &= 0x0000ff00; + _rdmsr(SB_MSR_REG(SB_CTRL), &hi, &lo); + hi &= 0xffffff00; + hi |= (value >> 8); + _wrmsr(SB_MSR_REG(SB_CTRL), hi, lo); + break; + case PCI_BAR0_REG: + pci_isa_write_bar(0, value); + break; + case PCI_BAR1_REG: + pci_isa_write_bar(1, value); + break; + case PCI_BAR2_REG: + pci_isa_write_bar(2, value); + break; + case PCI_BAR3_REG: + pci_isa_write_bar(3, value); + break; + case PCI_BAR4_REG: + pci_isa_write_bar(4, value); + break; + case PCI_BAR5_REG: + pci_isa_write_bar(5, value); + break; + case PCI_UART1_INT_REG: + _rdmsr(DIVIL_MSR_REG(PIC_YSEL_HIGH), &hi, &lo); + /* disable uart1 interrupt in PIC */ + lo &= ~(0xf << 24); + if (value) /* enable uart1 interrupt in PIC */ + lo |= (CS5536_UART1_INTR << 24); + _wrmsr(DIVIL_MSR_REG(PIC_YSEL_HIGH), hi, lo); + break; + case PCI_UART2_INT_REG: + _rdmsr(DIVIL_MSR_REG(PIC_YSEL_HIGH), &hi, &lo); + /* disable uart2 interrupt in PIC */ + lo &= ~(0xf << 28); + if (value) /* enable uart2 interrupt in PIC */ + lo |= (CS5536_UART2_INTR << 28); + _wrmsr(DIVIL_MSR_REG(PIC_YSEL_HIGH), hi, lo); + break; + case PCI_ISA_FIXUP_REG: + if (value) { + /* enable the TARGET ABORT/MASTER ABORT etc. */ + _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo); + lo |= 0x00000063; + _wrmsr(SB_MSR_REG(SB_ERROR), hi, lo); + } + + default: + /* ALL OTHER PCI CONFIG SPACE HEADER IS NOT IMPLEMENTED. */ + break; + } +} + +/* + * isa_read : isa read transfering. + * we assume that the ISA is not the BUS MASTER. + */ + +u32 pci_isa_read_reg(int reg) +{ + u32 conf_data = 0; + u32 hi, lo; + + switch (reg) { + case PCI_VENDOR_ID: + conf_data = + CFG_PCI_VENDOR_ID(CS5536_ISA_DEVICE_ID, CS5536_VENDOR_ID); + break; + case PCI_COMMAND: + /* we just check the first LBAR for the IO enable bit, */ + /* maybe we should changed later. */ + _rdmsr(DIVIL_MSR_REG(DIVIL_LBAR_SMB), &hi, &lo); + if (hi & 0x01) + conf_data |= PCI_COMMAND_IO; + break; + case PCI_STATUS: + conf_data |= PCI_STATUS_66MHZ; + conf_data |= PCI_STATUS_DEVSEL_MEDIUM; + conf_data |= PCI_STATUS_FAST_BACK; + + _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo); + if (lo & SB_TAS_ERR_FLAG) + conf_data |= PCI_STATUS_SIG_TARGET_ABORT; + if (lo & SB_TAR_ERR_FLAG) + conf_data |= PCI_STATUS_REC_TARGET_ABORT; + if (lo & SB_MAR_ERR_FLAG) + conf_data |= PCI_STATUS_REC_MASTER_ABORT; + if (lo & SB_PARE_ERR_FLAG) + conf_data |= PCI_STATUS_DETECTED_PARITY; + break; + case PCI_CLASS_REVISION: + _rdmsr(GLCP_MSR_REG(GLCP_CHIP_REV_ID), &hi, &lo); + conf_data = lo & 0x000000ff; + conf_data |= (CS5536_ISA_CLASS_CODE << 8); + break; + case PCI_CACHE_LINE_SIZE: + _rdmsr(SB_MSR_REG(SB_CTRL), &hi, &lo); + hi &= 0x000000f8; + conf_data = CFG_PCI_CACHE_LINE_SIZE(PCI_BRIDGE_HEADER_TYPE, hi); + break; + /* + * we only use the LBAR of DIVIL, no RCONF used. + * all of them are IO space. + */ + case PCI_BAR0_REG: + return pci_isa_read_bar(0); + break; + case PCI_BAR1_REG: + return pci_isa_read_bar(1); + break; + case PCI_BAR2_REG: + return pci_isa_read_bar(2); + break; + case PCI_BAR3_REG: + break; + case PCI_BAR4_REG: + return pci_isa_read_bar(4); + break; + case PCI_BAR5_REG: + return pci_isa_read_bar(5); + break; + case PCI_CARDBUS_CIS: + conf_data = PCI_CARDBUS_CIS_POINTER; + break; + case PCI_SUBSYSTEM_VENDOR_ID: + conf_data = + CFG_PCI_VENDOR_ID(CS5536_ISA_SUB_ID, CS5536_SUB_VENDOR_ID); + break; + case PCI_ROM_ADDRESS: + conf_data = PCI_EXPANSION_ROM_BAR; + break; + case PCI_CAPABILITY_LIST: + conf_data = PCI_CAPLIST_POINTER; + break; + case PCI_INTERRUPT_LINE: + /* no interrupt used here */ + conf_data = CFG_PCI_INTERRUPT_LINE(0x00, 0x00); + break; + default: + break; + } + + return conf_data; +} diff --git a/arch/mips/loongson/common/cs5536/cs5536_ohci.c b/arch/mips/loongson/common/cs5536/cs5536_ohci.c new file mode 100644 index 0000000..59d31c3 --- /dev/null +++ b/arch/mips/loongson/common/cs5536/cs5536_ohci.c @@ -0,0 +1,153 @@ +/* + * the OHCI Virtual Support Module of AMD CS5536 + * + * Copyright (C) 2007 Lemote, Inc. + * Author : jlliu, liujl@lemote.com + * + * Copyright (C) 2009 Lemote, Inc. + * Author: Wu Zhangjin, wuzj@lemote.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include +#include + +/* + * ohci_write : ohci write transfering. + */ +void pci_ohci_write_reg(int reg, u32 value) +{ + u32 hi = 0, lo = value; + + switch (reg) { + case PCI_COMMAND: + _rdmsr(USB_MSR_REG(USB_OHCI), &hi, &lo); + if (value & PCI_COMMAND_MASTER) + hi |= PCI_COMMAND_MASTER; + else + hi &= ~PCI_COMMAND_MASTER; + + if (value & PCI_COMMAND_MEMORY) + hi |= PCI_COMMAND_MEMORY; + else + hi &= ~PCI_COMMAND_MEMORY; + _wrmsr(USB_MSR_REG(USB_OHCI), hi, lo); + break; + case PCI_STATUS: + if (value & PCI_STATUS_PARITY) { + _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo); + if (lo & SB_PARE_ERR_FLAG) { + lo = (lo & 0x0000ffff) | SB_PARE_ERR_FLAG; + _wrmsr(SB_MSR_REG(SB_ERROR), hi, lo); + } + } + break; + case PCI_BAR0_REG: + if (value == PCI_BAR_RANGE_MASK) { + _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo); + lo |= SOFT_BAR_OHCI_FLAG; + _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo); + } else if ((value & 0x01) == 0x00) { + _wrmsr(USB_MSR_REG(USB_OHCI), hi, lo); + + value &= 0xfffffff0; + hi = 0x40000000 | ((value & 0xff000000) >> 24); + lo = 0x000fffff | ((value & 0x00fff000) << 8); + _wrmsr(GLIU_MSR_REG(GLIU_P2D_BM3), hi, lo); + } + break; + case PCI_OHCI_INT_REG: + _rdmsr(DIVIL_MSR_REG(PIC_YSEL_LOW), &hi, &lo); + lo &= ~(0xf << PIC_YSEL_LOW_USB_SHIFT); + if (value) /* enable all the usb interrupt in PIC */ + lo |= (CS5536_USB_INTR << PIC_YSEL_LOW_USB_SHIFT); + _wrmsr(DIVIL_MSR_REG(PIC_YSEL_LOW), hi, lo); + break; + default: + break; + } +} + +/* + * ohci_read : ohci read transfering. + */ +u32 pci_ohci_read_reg(int reg) +{ + u32 conf_data = 0; + u32 hi, lo; + + switch (reg) { + case PCI_VENDOR_ID: + conf_data = + CFG_PCI_VENDOR_ID(CS5536_OHCI_DEVICE_ID, CS5536_VENDOR_ID); + break; + case PCI_COMMAND: + _rdmsr(USB_MSR_REG(USB_OHCI), &hi, &lo); + if (hi & PCI_COMMAND_MASTER) + conf_data |= PCI_COMMAND_MASTER; + if (hi & PCI_COMMAND_MEMORY) + conf_data |= PCI_COMMAND_MEMORY; + break; + case PCI_STATUS: + conf_data |= PCI_STATUS_66MHZ; + conf_data |= PCI_STATUS_FAST_BACK; + _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo); + if (lo & SB_PARE_ERR_FLAG) + conf_data |= PCI_STATUS_PARITY; + conf_data |= PCI_STATUS_DEVSEL_MEDIUM; + break; + case PCI_CLASS_REVISION: + _rdmsr(USB_MSR_REG(USB_CAP), &hi, &lo); + conf_data = lo & 0x000000ff; + conf_data |= (CS5536_OHCI_CLASS_CODE << 8); + break; + case PCI_CACHE_LINE_SIZE: + conf_data = + CFG_PCI_CACHE_LINE_SIZE(PCI_NORMAL_HEADER_TYPE, + PCI_NORMAL_LATENCY_TIMER); + break; + case PCI_BAR0_REG: + _rdmsr(GLCP_MSR_REG(GLCP_SOFT_COM), &hi, &lo); + if (lo & SOFT_BAR_OHCI_FLAG) { + conf_data = CS5536_OHCI_RANGE | + PCI_BASE_ADDRESS_SPACE_MEMORY; + lo &= ~SOFT_BAR_OHCI_FLAG; + _wrmsr(GLCP_MSR_REG(GLCP_SOFT_COM), hi, lo); + } else { + _rdmsr(USB_MSR_REG(USB_OHCI), &hi, &lo); + conf_data = lo & 0xffffff00; + conf_data &= ~0x0000000f; /* 32bit mem */ + } + break; + case PCI_CARDBUS_CIS: + conf_data = PCI_CARDBUS_CIS_POINTER; + break; + case PCI_SUBSYSTEM_VENDOR_ID: + conf_data = + CFG_PCI_VENDOR_ID(CS5536_OHCI_SUB_ID, CS5536_SUB_VENDOR_ID); + break; + case PCI_ROM_ADDRESS: + conf_data = PCI_EXPANSION_ROM_BAR; + break; + case PCI_CAPABILITY_LIST: + conf_data = PCI_CAPLIST_USB_POINTER; + break; + case PCI_INTERRUPT_LINE: + conf_data = + CFG_PCI_INTERRUPT_LINE(PCI_DEFAULT_PIN, CS5536_USB_INTR); + break; + case PCI_OHCI_INT_REG: + _rdmsr(DIVIL_MSR_REG(PIC_YSEL_LOW), &hi, &lo); + if ((lo & 0x00000f00) == CS5536_USB_INTR) + conf_data = 1; + break; + default: + break; + } + + return conf_data; +} diff --git a/arch/mips/loongson/common/cs5536/cs5536_pci.c b/arch/mips/loongson/common/cs5536/cs5536_pci.c new file mode 100644 index 0000000..e23f3d7 --- /dev/null +++ b/arch/mips/loongson/common/cs5536/cs5536_pci.c @@ -0,0 +1,87 @@ +/* + * read/write operation to the PCI config space of CS5536 + * + * Copyright (C) 2007 Lemote, Inc. + * Author : jlliu, liujl@lemote.com + * + * Copyright (C) 2009 Lemote, Inc. + * Author: Wu Zhangjin, wuzj@lemote.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * the Virtual Support Module(VSM) for virtulizing the PCI + * configure space are defined in cs5536_modulename.c respectively, + * + * after this virtulizing, user can access the PCI configure space + * directly as a normal multi-function PCI device which follows + * the PCI-2.2 spec. + */ + +#include +#include + +enum { + CS5536_FUNC_START = -1, + CS5536_ISA_FUNC, + reserved_func, + CS5536_IDE_FUNC, + CS5536_ACC_FUNC, + CS5536_OHCI_FUNC, + CS5536_EHCI_FUNC, + CS5536_FUNC_END, +}; + +static const cs5536_pci_vsm_write vsm_conf_write[] = { + [CS5536_ISA_FUNC] pci_isa_write_reg, + [reserved_func] NULL, + [CS5536_IDE_FUNC] pci_ide_write_reg, + [CS5536_ACC_FUNC] pci_acc_write_reg, + [CS5536_OHCI_FUNC] pci_ohci_write_reg, + [CS5536_EHCI_FUNC] pci_ehci_write_reg, +}; + +static const cs5536_pci_vsm_read vsm_conf_read[] = { + [CS5536_ISA_FUNC] pci_isa_read_reg, + [reserved_func] NULL, + [CS5536_IDE_FUNC] pci_ide_read_reg, + [CS5536_ACC_FUNC] pci_acc_read_reg, + [CS5536_OHCI_FUNC] pci_ohci_read_reg, + [CS5536_EHCI_FUNC] pci_ehci_read_reg, +}; + +/* + * write to PCI config space and transfer it to MSR write. + */ +void cs5536_pci_conf_write4(int function, int reg, u32 value) +{ + if ((function <= CS5536_FUNC_START) || (function >= CS5536_FUNC_END)) + return; + if ((reg < 0) || (reg > 0x100) || ((reg & 0x03) != 0)) + return; + + if (vsm_conf_write[function] != NULL) + vsm_conf_write[function](reg, value); +} + +/* + * read PCI config space and transfer it to MSR access. + */ +u32 cs5536_pci_conf_read4(int function, int reg) +{ + u32 data = 0; + + if ((function <= CS5536_FUNC_START) || (function >= CS5536_FUNC_END)) + return 0; + if ((reg < 0) || ((reg & 0x03) != 0)) + return 0; + if (reg > 0x100) + return 0xffffffff; + + if (vsm_conf_read[function] != NULL) + data = vsm_conf_read[function](reg); + + return data; +} -- 1.6.2.1 From wuzhangjin@gmail.com Fri Nov 6 14:13:36 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 06 Nov 2009 14:13:44 +0100 (CET) Received: from mail-pz0-f194.google.com ([209.85.222.194]:52238 "EHLO mail-pz0-f194.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492534AbZKFNMX (ORCPT ); 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Fri, 06 Nov 2009 05:12:14 -0800 (PST) From: Wu Zhangjin To: Ralf Baechle Cc: Arnaud Patard , zhangfx@lemote.com, yanh@lemote.com, huhb@lemote.com, Nicholas Mc Guire , Wu Zhangjin , linux-mips@linux-mips.org Subject: [PATCH -queue v1 4/7] [loongson] lemote-2f: add pci support Date: Fri, 6 Nov 2009 21:11:29 +0800 Message-Id: <84e7310659ae445b3b3dc68aadc8f27648c709f6.1257510612.git.wuzhangjin@gmail.com> X-Mailer: git-send-email 1.6.2.1 In-Reply-To: <7affa8fce1f55b817aff1c64f823824f6809dd85.1257510612.git.wuzhangjin@gmail.com> References: <17e5d58a0cd7273b81c7151b7f7f2096c9694b59.1257510612.git.wuzhangjin@gmail.com> <588574ed5910292f2728072ca147add2ae342778.1257510612.git.wuzhangjin@gmail.com> <7affa8fce1f55b817aff1c64f823824f6809dd85.1257510612.git.wuzhangjin@gmail.com> In-Reply-To: References: Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24726 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips From: Wu Zhangjin Most of the pci support between fuloong2e and lemote loongson2f family machines are the same, except the cs5536 support. This patch renames ops-fuloong2e.c to ops-loongson2.c and then append the cs5536 support to share most of the source code among loongson machines. Signed-off-by: Wu Zhangjin --- arch/mips/pci/Makefile | 3 +- arch/mips/pci/fixup-lemote2f.c | 162 +++++++++++++++++++++++++++++++ arch/mips/pci/ops-fuloong2e.c | 154 ----------------------------- arch/mips/pci/ops-loongson2.c | 208 ++++++++++++++++++++++++++++++++++++++++ 4 files changed, 372 insertions(+), 155 deletions(-) create mode 100644 arch/mips/pci/fixup-lemote2f.c delete mode 100644 arch/mips/pci/ops-fuloong2e.c create mode 100644 arch/mips/pci/ops-loongson2.c diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile index 0610c86..c9a0dc1 100644 --- a/arch/mips/pci/Makefile +++ b/arch/mips/pci/Makefile @@ -28,7 +28,8 @@ obj-$(CONFIG_MIPS_COBALT) += fixup-cobalt.o obj-$(CONFIG_SOC_AU1500) += fixup-au1000.o ops-au1000.o obj-$(CONFIG_SOC_AU1550) += fixup-au1000.o ops-au1000.o obj-$(CONFIG_SOC_PNX8550) += fixup-pnx8550.o ops-pnx8550.o -obj-$(CONFIG_LEMOTE_FULOONG2E) += fixup-fuloong2e.o ops-fuloong2e.o +obj-$(CONFIG_LEMOTE_FULOONG2E) += fixup-fuloong2e.o ops-loongson2.o +obj-$(CONFIG_LEMOTE_MACH2F) += fixup-lemote2f.o ops-loongson2.o obj-$(CONFIG_MIPS_MALTA) += fixup-malta.o obj-$(CONFIG_PMC_MSP7120_GW) += fixup-pmcmsp.o ops-pmcmsp.o obj-$(CONFIG_PMC_MSP7120_EVAL) += fixup-pmcmsp.o ops-pmcmsp.o diff --git a/arch/mips/pci/fixup-lemote2f.c b/arch/mips/pci/fixup-lemote2f.c new file mode 100644 index 0000000..e7c2b4d --- /dev/null +++ b/arch/mips/pci/fixup-lemote2f.c @@ -0,0 +1,162 @@ +/* + * Copyright (C) 2008 Lemote Technology + * Copyright (C) 2004 ICT CAS + * Author: Li xiaoyu, lixy@ict.ac.cn + * + * Copyright (C) 2007 Lemote, Inc. + * Author: Fuxin Zhang, zhangfx@lemote.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ +#include +#include + +#include +#include +#include + +/* PCI interrupt pins + * + * These should not be changed, or you should consider loongson2f interrupt + * register and your pci card dispatch + */ + +#define PCIA 4 +#define PCIB 5 +#define PCIC 6 +#define PCID 7 + +/* all the pci device has the PCIA pin, check the datasheet. */ +static char irq_tab[][5] __initdata = { + /* INTA INTB INTC INTD */ + {0, 0, 0, 0, 0}, /* 11: Unused */ + {0, 0, 0, 0, 0}, /* 12: Unused */ + {0, 0, 0, 0, 0}, /* 13: Unused */ + {0, 0, 0, 0, 0}, /* 14: Unused */ + {0, 0, 0, 0, 0}, /* 15: Unused */ + {0, 0, 0, 0, 0}, /* 16: Unused */ + {0, PCIA, 0, 0, 0}, /* 17: RTL8110-0 */ + {0, PCIB, 0, 0, 0}, /* 18: RTL8110-1 */ + {0, PCIC, 0, 0, 0}, /* 19: SiI3114 */ + {0, PCID, 0, 0, 0}, /* 20: 3-ports nec usb */ + {0, PCIA, PCIB, PCIC, PCID}, /* 21: PCI-SLOT */ + {0, 0, 0, 0, 0}, /* 22: Unused */ + {0, 0, 0, 0, 0}, /* 23: Unused */ + {0, 0, 0, 0, 0}, /* 24: Unused */ + {0, 0, 0, 0, 0}, /* 25: Unused */ + {0, 0, 0, 0, 0}, /* 26: Unused */ + {0, 0, 0, 0, 0}, /* 27: Unused */ +}; + +int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) +{ + int virq; + + if ((PCI_SLOT(dev->devfn) != PCI_IDSEL_CS5536) + && (PCI_SLOT(dev->devfn) < 32)) { + virq = irq_tab[slot][pin]; + printk(KERN_INFO "slot: %d, pin: %d, irq: %d\n", slot, pin, + virq + LOONGSON_IRQ_BASE); + if (virq != 0) + return LOONGSON_IRQ_BASE + virq; + else + return 0; + } else if (PCI_SLOT(dev->devfn) == PCI_IDSEL_CS5536) { /* cs5536 */ + switch (PCI_FUNC(dev->devfn)) { + case 2: + pci_write_config_byte(dev, PCI_INTERRUPT_LINE, + CS5536_IDE_INTR); + return CS5536_IDE_INTR; /* for IDE */ + case 3: + pci_write_config_byte(dev, PCI_INTERRUPT_LINE, + CS5536_ACC_INTR); + return CS5536_ACC_INTR; /* for AUDIO */ + case 4: /* for OHCI */ + case 5: /* for EHCI */ + case 6: /* for UDC */ + case 7: /* for OTG */ + pci_write_config_byte(dev, PCI_INTERRUPT_LINE, + CS5536_USB_INTR); + return CS5536_USB_INTR; + } + return dev->irq; + } else { + printk(KERN_INFO " strange pci slot number.\n"); + return 0; + } +} + +/* Do platform specific device initialization at pci_enable_device() time */ +int pcibios_plat_dev_init(struct pci_dev *dev) +{ + return 0; +} + +/* CS5536 SPEC. fixup */ +static void __init loongson_cs5536_isa_fixup(struct pci_dev *pdev) +{ + /* the uart1 and uart2 interrupt in PIC is enabled as default */ + pci_write_config_dword(pdev, PCI_UART1_INT_REG, 1); + pci_write_config_dword(pdev, PCI_UART2_INT_REG, 1); +} + +static void __init loongson_cs5536_ide_fixup(struct pci_dev *pdev) +{ + /* setting the mutex pin as IDE function */ + pci_write_config_dword(pdev, PCI_IDE_CFG_REG, + CS5536_IDE_FLASH_SIGNATURE); +} + +static void __init loongson_cs5536_acc_fixup(struct pci_dev *pdev) +{ + u8 val; + + /* enable the AUDIO interrupt in PIC */ + pci_write_config_dword(pdev, PCI_ACC_INT_REG, 1); + + pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xc0); +} + +static void __init loongson_cs5536_ohci_fixup(struct pci_dev *pdev) +{ + /* enable the OHCI interrupt in PIC */ + /* THE OHCI, EHCI, UDC, OTG are shared with interrupt in PIC */ + pci_write_config_dword(pdev, PCI_OHCI_INT_REG, 1); +} + +static void __init loongson_cs5536_ehci_fixup(struct pci_dev *pdev) +{ + u32 hi, lo; + + /* Serial short detect enable */ + _rdmsr(USB_MSR_REG(USB_CONFIG), &hi, &lo); + _wrmsr(USB_MSR_REG(USB_CONFIG), (1 << 1) | (1 << 2) | (1 << 3), lo); + + /* setting the USB2.0 micro frame length */ + pci_write_config_dword(pdev, PCI_EHCI_FLADJ_REG, 0x2000); +} + +static void __init loongson_nec_fixup(struct pci_dev *pdev) +{ + unsigned int val; + + pci_read_config_dword(pdev, 0xe0, &val); + /* Only 2 port be used */ + pci_write_config_dword(pdev, 0xe0, (val & ~3) | 0x2); +} + +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, + loongson_cs5536_isa_fixup); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_OHC, + loongson_cs5536_ohci_fixup); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_EHC, + loongson_cs5536_ehci_fixup); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_AUDIO, + loongson_cs5536_acc_fixup); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_IDE, + loongson_cs5536_ide_fixup); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_USB, + loongson_nec_fixup); diff --git a/arch/mips/pci/ops-fuloong2e.c b/arch/mips/pci/ops-fuloong2e.c deleted file mode 100644 index 171f65c..0000000 --- a/arch/mips/pci/ops-fuloong2e.c +++ /dev/null @@ -1,154 +0,0 @@ -/* - * fuloong2e specific PCI support. - * - * Copyright (C) 1999, 2000, 2004 MIPS Technologies, Inc. - * All rights reserved. - * Authors: Carsten Langgaard - * Maciej W. Rozycki - * - * Copyright (C) 2009 Lemote Inc. - * Author: Wu Zhangjin - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - */ -#include -#include -#include -#include - -#include - -#define PCI_ACCESS_READ 0 -#define PCI_ACCESS_WRITE 1 - -#define CFG_SPACE_REG(offset) \ - (void *)CKSEG1ADDR(LOONGSON_PCICFG_BASE | (offset)) -#define ID_SEL_BEGIN 11 -#define MAX_DEV_NUM (31 - ID_SEL_BEGIN) - - -static int loongson_pcibios_config_access(unsigned char access_type, - struct pci_bus *bus, - unsigned int devfn, int where, - u32 *data) -{ - u32 busnum = bus->number; - u32 addr, type; - u32 dummy; - void *addrp; - int device = PCI_SLOT(devfn); - int function = PCI_FUNC(devfn); - int reg = where & ~3; - - if (busnum == 0) { - /* Type 0 configuration for onboard PCI bus */ - if (device > MAX_DEV_NUM) - return -1; - - addr = (1 << (device + ID_SEL_BEGIN)) | (function << 8) | reg; - type = 0; - } else { - /* Type 1 configuration for offboard PCI bus */ - addr = (busnum << 16) | (device << 11) | (function << 8) | reg; - type = 0x10000; - } - - /* Clear aborts */ - LOONGSON_PCICMD |= LOONGSON_PCICMD_MABORT_CLR | \ - LOONGSON_PCICMD_MTABORT_CLR; - - LOONGSON_PCIMAP_CFG = (addr >> 16) | type; - - /* Flush Bonito register block */ - dummy = LOONGSON_PCIMAP_CFG; - mmiowb(); - - addrp = CFG_SPACE_REG(addr & 0xffff); - if (access_type == PCI_ACCESS_WRITE) - writel(cpu_to_le32(*data), addrp); - else - *data = le32_to_cpu(readl(addrp)); - - /* Detect Master/Target abort */ - if (LOONGSON_PCICMD & (LOONGSON_PCICMD_MABORT_CLR | - LOONGSON_PCICMD_MTABORT_CLR)) { - /* Error occurred */ - - /* Clear bits */ - LOONGSON_PCICMD |= (LOONGSON_PCICMD_MABORT_CLR | - LOONGSON_PCICMD_MTABORT_CLR); - - return -1; - } - - return 0; - -} - - -/* - * We can't address 8 and 16 bit words directly. Instead we have to - * read/write a 32bit word and mask/modify the data we actually want. - */ -static int loongson_pcibios_read(struct pci_bus *bus, unsigned int devfn, - int where, int size, u32 *val) -{ - u32 data = 0; - - if ((size == 2) && (where & 1)) - return PCIBIOS_BAD_REGISTER_NUMBER; - else if ((size == 4) && (where & 3)) - return PCIBIOS_BAD_REGISTER_NUMBER; - - if (loongson_pcibios_config_access(PCI_ACCESS_READ, bus, devfn, where, - &data)) - return -1; - - if (size == 1) - *val = (data >> ((where & 3) << 3)) & 0xff; - else if (size == 2) - *val = (data >> ((where & 3) << 3)) & 0xffff; - else - *val = data; - - return PCIBIOS_SUCCESSFUL; -} - -static int loongson_pcibios_write(struct pci_bus *bus, unsigned int devfn, - int where, int size, u32 val) -{ - u32 data = 0; - - if ((size == 2) && (where & 1)) - return PCIBIOS_BAD_REGISTER_NUMBER; - else if ((size == 4) && (where & 3)) - return PCIBIOS_BAD_REGISTER_NUMBER; - - if (size == 4) - data = val; - else { - if (loongson_pcibios_config_access(PCI_ACCESS_READ, bus, devfn, - where, &data)) - return -1; - - if (size == 1) - data = (data & ~(0xff << ((where & 3) << 3))) | - (val << ((where & 3) << 3)); - else if (size == 2) - data = (data & ~(0xffff << ((where & 3) << 3))) | - (val << ((where & 3) << 3)); - } - - if (loongson_pcibios_config_access(PCI_ACCESS_WRITE, bus, devfn, where, - &data)) - return -1; - - return PCIBIOS_SUCCESSFUL; -} - -struct pci_ops loongson_pci_ops = { - .read = loongson_pcibios_read, - .write = loongson_pcibios_write -}; diff --git a/arch/mips/pci/ops-loongson2.c b/arch/mips/pci/ops-loongson2.c new file mode 100644 index 0000000..9e9b28e --- /dev/null +++ b/arch/mips/pci/ops-loongson2.c @@ -0,0 +1,208 @@ +/* + * fuloong2e specific PCI support. + * + * Copyright (C) 1999, 2000, 2004 MIPS Technologies, Inc. + * All rights reserved. + * Authors: Carsten Langgaard + * Maciej W. Rozycki + * + * Copyright (C) 2009 Lemote Inc. + * Author: Wu Zhangjin + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + */ +#include +#include +#include +#include + +#include + +#ifdef CONFIG_CS5536 +#include +#include +#endif + +#define PCI_ACCESS_READ 0 +#define PCI_ACCESS_WRITE 1 + +#define CFG_SPACE_REG(offset) \ + (void *)CKSEG1ADDR(LOONGSON_PCICFG_BASE | (offset)) +#define ID_SEL_BEGIN 11 +#define MAX_DEV_NUM (31 - ID_SEL_BEGIN) + + +static int loongson_pcibios_config_access(unsigned char access_type, + struct pci_bus *bus, + unsigned int devfn, int where, + u32 *data) +{ + u32 busnum = bus->number; + u32 addr, type; + u32 dummy; + void *addrp; + int device = PCI_SLOT(devfn); + int function = PCI_FUNC(devfn); + int reg = where & ~3; + + if (busnum == 0) { + /* board-specific part,currently,only fuloong2f,yeeloong2f + * use CS5536, fuloong2e use via686b, gdium has no + * south bridge + */ +#ifdef CONFIG_CS5536 + /* cs5536_pci_conf_read4/write4() will call _rdmsr/_wrmsr() to + * access the regsters PCI_MSR_ADDR, PCI_MSR_DATA_LO, + * PCI_MSR_DATA_HI, which is bigger than 0xf0, so, it will not + * go this branch, but the others. so, no calling dead loop + * here. + */ + if ((PCI_IDSEL_CS5536 == device) && (reg < PCI_MSR_CTRL)) { + switch (access_type) { + case PCI_ACCESS_READ: + *data = cs5536_pci_conf_read4(function, reg); + break; + case PCI_ACCESS_WRITE: + cs5536_pci_conf_write4(function, reg, *data); + break; + } + return 0; + } +#endif + /* Type 0 configuration for onboard PCI bus */ + if (device > MAX_DEV_NUM) + return -1; + + addr = (1 << (device + ID_SEL_BEGIN)) | (function << 8) | reg; + type = 0; + } else { + /* Type 1 configuration for offboard PCI bus */ + addr = (busnum << 16) | (device << 11) | (function << 8) | reg; + type = 0x10000; + } + + /* Clear aborts */ + LOONGSON_PCICMD |= LOONGSON_PCICMD_MABORT_CLR | \ + LOONGSON_PCICMD_MTABORT_CLR; + + LOONGSON_PCIMAP_CFG = (addr >> 16) | type; + + /* Flush Bonito register block */ + dummy = LOONGSON_PCIMAP_CFG; + mmiowb(); + + addrp = CFG_SPACE_REG(addr & 0xffff); + if (access_type == PCI_ACCESS_WRITE) + writel(cpu_to_le32(*data), addrp); + else + *data = le32_to_cpu(readl(addrp)); + + /* Detect Master/Target abort */ + if (LOONGSON_PCICMD & (LOONGSON_PCICMD_MABORT_CLR | + LOONGSON_PCICMD_MTABORT_CLR)) { + /* Error occurred */ + + /* Clear bits */ + LOONGSON_PCICMD |= (LOONGSON_PCICMD_MABORT_CLR | + LOONGSON_PCICMD_MTABORT_CLR); + + return -1; + } + + return 0; + +} + + +/* + * We can't address 8 and 16 bit words directly. Instead we have to + * read/write a 32bit word and mask/modify the data we actually want. + */ +static int loongson_pcibios_read(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 *val) +{ + u32 data = 0; + + if ((size == 2) && (where & 1)) + return PCIBIOS_BAD_REGISTER_NUMBER; + else if ((size == 4) && (where & 3)) + return PCIBIOS_BAD_REGISTER_NUMBER; + + if (loongson_pcibios_config_access(PCI_ACCESS_READ, bus, devfn, where, + &data)) + return -1; + + if (size == 1) + *val = (data >> ((where & 3) << 3)) & 0xff; + else if (size == 2) + *val = (data >> ((where & 3) << 3)) & 0xffff; + else + *val = data; + + return PCIBIOS_SUCCESSFUL; +} + +static int loongson_pcibios_write(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 val) +{ + u32 data = 0; + + if ((size == 2) && (where & 1)) + return PCIBIOS_BAD_REGISTER_NUMBER; + else if ((size == 4) && (where & 3)) + return PCIBIOS_BAD_REGISTER_NUMBER; + + if (size == 4) + data = val; + else { + if (loongson_pcibios_config_access(PCI_ACCESS_READ, bus, devfn, + where, &data)) + return -1; + + if (size == 1) + data = (data & ~(0xff << ((where & 3) << 3))) | + (val << ((where & 3) << 3)); + else if (size == 2) + data = (data & ~(0xffff << ((where & 3) << 3))) | + (val << ((where & 3) << 3)); + } + + if (loongson_pcibios_config_access(PCI_ACCESS_WRITE, bus, devfn, where, + &data)) + return -1; + + return PCIBIOS_SUCCESSFUL; +} + +struct pci_ops loongson_pci_ops = { + .read = loongson_pcibios_read, + .write = loongson_pcibios_write +}; + +#ifdef CONFIG_CS5536 +void _rdmsr(u32 msr, u32 *hi, u32 *lo) +{ + struct pci_bus bus = { + .number = PCI_BUS_CS5536 + }; + u32 devfn = PCI_DEVFN(PCI_IDSEL_CS5536, 0); + loongson_pcibios_write(&bus, devfn, PCI_MSR_ADDR, 4, msr); + loongson_pcibios_read(&bus, devfn, PCI_MSR_DATA_LO, 4, lo); + loongson_pcibios_read(&bus, devfn, PCI_MSR_DATA_HI, 4, hi); +} +EXPORT_SYMBOL(_rdmsr); + +void _wrmsr(u32 msr, u32 hi, u32 lo) +{ + struct pci_bus bus = { + .number = PCI_BUS_CS5536 + }; + u32 devfn = PCI_DEVFN(PCI_IDSEL_CS5536, 0); + loongson_pcibios_write(&bus, devfn, PCI_MSR_ADDR, 4, msr); + loongson_pcibios_write(&bus, devfn, PCI_MSR_DATA_LO, 4, lo); + loongson_pcibios_write(&bus, devfn, PCI_MSR_DATA_HI, 4, hi); +} +EXPORT_SYMBOL(_wrmsr); +#endif -- 1.6.2.1 From wuzhangjin@gmail.com Fri Nov 6 14:14:02 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 06 Nov 2009 14:14:10 +0100 (CET) Received: from mail-pz0-f194.google.com ([209.85.222.194]:47246 "EHLO mail-pz0-f194.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492762AbZKFNM1 (ORCPT ); Fri, 6 Nov 2009 14:12:27 +0100 Received: by pzk32 with SMTP id 32so730652pzk.21 for ; Fri, 06 Nov 2009 05:12:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer:in-reply-to:references:in-reply-to:references; bh=SmthfTTmCccT5cEK7SBFhzTZ4oNKbiW0KELe58SDjgc=; b=dqegG4dY22FeuDPabtSPy44G/XQQ8wIECE60KUd2igU8s0vsWiUzm/DcRilNl8EEAt vSIAq7ZPxxsFdzUgOmTzWB9/nc4T12jFhYtjKTuTvKRnnIYpHKYv/mArlFql2eLfkCF4 FfvdX6t65Elm+qRuTAvZ6HdunUSUVcFF4y7rM= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; b=DqzR3MuM6cvBblL86ru+EYx7f4hP+fz9OwBVFpQt+b27Zj7Oe0fAg41JkTG12O48LL j081m2UsIx0EH/ysBSzzHCm5WNp4kB+MokQbbDqxWkMSkdIswHNUvvjCYyfm05mNaGkQ qy/CrdH5j8OBVF8CRyJDAJB5OIlNDE0eYuAfE= Received: by 10.115.99.4 with SMTP id b4mr6676051wam.88.1257513140167; Fri, 06 Nov 2009 05:12:20 -0800 (PST) Received: from localhost.localdomain ([222.92.8.142]) by mx.google.com with ESMTPS id 20sm26431pxi.7.2009.11.06.05.12.15 (version=TLSv1/SSLv3 cipher=RC4-MD5); Fri, 06 Nov 2009 05:12:19 -0800 (PST) From: Wu Zhangjin To: Ralf Baechle Cc: Arnaud Patard , zhangfx@lemote.com, yanh@lemote.com, huhb@lemote.com, Nicholas Mc Guire , Wu Zhangjin , linux-mips@linux-mips.org Subject: [PATCH -queue v1 5/7] [loongson] lemote-2f: add irq support Date: Fri, 6 Nov 2009 21:11:30 +0800 Message-Id: <96301eaeffac1ae45d7529760eb961a04356dfca.1257510612.git.wuzhangjin@gmail.com> X-Mailer: git-send-email 1.6.2.1 In-Reply-To: <84e7310659ae445b3b3dc68aadc8f27648c709f6.1257510612.git.wuzhangjin@gmail.com> References: <17e5d58a0cd7273b81c7151b7f7f2096c9694b59.1257510612.git.wuzhangjin@gmail.com> <588574ed5910292f2728072ca147add2ae342778.1257510612.git.wuzhangjin@gmail.com> <7affa8fce1f55b817aff1c64f823824f6809dd85.1257510612.git.wuzhangjin@gmail.com> <84e7310659ae445b3b3dc68aadc8f27648c709f6.1257510612.git.wuzhangjin@gmail.com> In-Reply-To: References: Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24727 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips From: Wu Zhangjin The common i8259_irq() will make kernel hang on booting, herein, we write our own instead. The IP6 is shared by the bonito interrupt and the perfcounter interrupt. Signed-off-by: Wu Zhangjin --- arch/mips/loongson/Makefile | 6 ++ arch/mips/loongson/lemote-2f/Makefile | 5 + arch/mips/loongson/lemote-2f/irq.c | 130 +++++++++++++++++++++++++++++++++ 3 files changed, 141 insertions(+), 0 deletions(-) create mode 100644 arch/mips/loongson/lemote-2f/Makefile create mode 100644 arch/mips/loongson/lemote-2f/irq.c diff --git a/arch/mips/loongson/Makefile b/arch/mips/loongson/Makefile index 39048c4..2b76cb0 100644 --- a/arch/mips/loongson/Makefile +++ b/arch/mips/loongson/Makefile @@ -9,3 +9,9 @@ obj-$(CONFIG_MACH_LOONGSON) += common/ # obj-$(CONFIG_LEMOTE_FULOONG2E) += fuloong-2e/ + +# +# Lemote loongson2f family machines +# + +obj-$(CONFIG_LEMOTE_MACH2F) += lemote-2f/ diff --git a/arch/mips/loongson/lemote-2f/Makefile b/arch/mips/loongson/lemote-2f/Makefile new file mode 100644 index 0000000..2e18897 --- /dev/null +++ b/arch/mips/loongson/lemote-2f/Makefile @@ -0,0 +1,5 @@ +# +# Makefile for lemote loongson2f family machines +# + +obj-y += irq.o diff --git a/arch/mips/loongson/lemote-2f/irq.c b/arch/mips/loongson/lemote-2f/irq.c new file mode 100644 index 0000000..98f6984 --- /dev/null +++ b/arch/mips/loongson/lemote-2f/irq.c @@ -0,0 +1,130 @@ +/* + * Copyright (C) 2007 Lemote Inc. + * Author: Fuxin Zhang, zhangfx@lemote.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include + +#include +#include +#include + +#include +#include + +#define LOONGSON_TIMER_IRQ (MIPS_CPU_IRQ_BASE + 7) /* cpu timer */ +#define LOONGSON_PERFCNT_IRQ (MIPS_CPU_IRQ_BASE + 6) /* cpu perf counter */ +#define LOONGSON_NORTH_BRIDGE_IRQ (MIPS_CPU_IRQ_BASE + 6) /* bonito */ +#define LOONGSON_UART_IRQ (MIPS_CPU_IRQ_BASE + 3) /* cpu serial port */ +#define LOONGSON_SOUTH_BRIDGE_IRQ (MIPS_CPU_IRQ_BASE + 2) /* i8259 */ + +#define LOONGSON_INT_BIT_INT0 (1 << 11) +#define LOONGSON_INT_BIT_INT1 (1 << 12) + +/* The common i8259_irq() make the kernel hang on booting, Seems we can not get + * the irq via the IRR directly, herein, we access the ISR instead. */ +static inline int mach_i8259_irq(void) +{ + int irq, isr; + + irq = -1; + + if ((LOONGSON_INTISR & LOONGSON_INTEN) & LOONGSON_INT_BIT_INT0) { + spin_lock(&i8259A_lock); + isr = inb(PIC_MASTER_CMD) & + ~inb(PIC_MASTER_IMR) & ~(1 << PIC_CASCADE_IR); + if (!isr) + isr = (inb(PIC_SLAVE_CMD) & ~inb(PIC_SLAVE_IMR)) << 8; + irq = ffs(isr) - 1; + if (unlikely(irq == 7)) { + /* + * This may be a spurious interrupt. + * + * Read the interrupt status register (ISR). If the most + * significant bit is not set then there is no valid + * interrupt. + */ + outb(0x0B, PIC_MASTER_ISR); /* ISR register */ + if (~inb(PIC_MASTER_ISR) & 0x80) + irq = -1; + } + spin_unlock(&i8259A_lock); + } + + return irq; +} + +static void i8259_irqdispatch(void) +{ + int irq; + + irq = mach_i8259_irq(); + if (irq >= 0) + do_IRQ(irq); + else + spurious_interrupt(); +} + +void mach_irq_dispatch(unsigned int pending) +{ + if (pending & CAUSEF_IP7) + do_IRQ(LOONGSON_TIMER_IRQ); + else if (pending & CAUSEF_IP6) { /* North Bridge, Perf counter */ +#ifdef CONFIG_OPROFILE + do_IRQ(LOONGSON2_PERFCNT_IRQ); +#endif + bonito_irqdispatch(); + } else if (pending & CAUSEF_IP3) /* CPU UART */ + do_IRQ(LOONGSON_UART_IRQ); + else if (pending & CAUSEF_IP2) /* South Bridge */ + i8259_irqdispatch(); + else + spurious_interrupt(); +} + +void __init set_irq_trigger_mode(void) +{ + /* setup cs5536 as high level trigger */ + LOONGSON_INTPOL = LOONGSON_INT_BIT_INT0 | LOONGSON_INT_BIT_INT1; + LOONGSON_INTEDGE &= ~(LOONGSON_INT_BIT_INT0 | LOONGSON_INT_BIT_INT1); +} + +static irqreturn_t ip6_action(int cpl, void *dev_id) +{ + return IRQ_HANDLED; +} + +struct irqaction ip6_irqaction = { + .handler = ip6_action, + .name = "cascade", + .flags = IRQF_SHARED, +}; + +struct irqaction cascade_irqaction = { + .handler = no_action, + .name = "cascade", +}; + +void __init mach_init_irq(void) +{ + /* init all controller + * 0-15 ------> i8259 interrupt + * 16-23 ------> mips cpu interrupt + * 32-63 ------> bonito irq + */ + + /* Sets the first-level interrupt dispatcher. */ + mips_cpu_irq_init(); + init_i8259_irqs(); + bonito_irq_init(); + + /* setup north bridge irq (bonito) */ + setup_irq(LOONGSON_NORTH_BRIDGE_IRQ, &ip6_irqaction); + /* setup source bridge irq (i8259) */ + setup_irq(LOONGSON_SOUTH_BRIDGE_IRQ, &cascade_irqaction); +} -- 1.6.2.1 From wuzhangjin@gmail.com Fri Nov 6 14:14:28 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 06 Nov 2009 14:14:35 +0100 (CET) Received: from mail-px0-f188.google.com ([209.85.216.188]:39281 "EHLO mail-px0-f188.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492770AbZKFNM3 (ORCPT ); Fri, 6 Nov 2009 14:12:29 +0100 Received: by mail-px0-f188.google.com with SMTP id 26so367498pxi.21 for ; Fri, 06 Nov 2009 05:12:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer:in-reply-to:references:in-reply-to:references; bh=JCYDZGjkpspjE36H5CPPrT09PFzL1y1hw/crXGzEy/M=; b=LJxvtaru8A/AdbVqoqb+9+njG3jcuJJ6jdDcWZfLwB9B8ZsjHdedhFR4Itmt1qCpvg P32AEnDf09WfcT2ciJxuGRbyWnCXp4cWRlTX8M29MzhLUINTXO7+of8mwLjh8K8+CMEf i1pdG8bDzobpGjbPepTc+ACmgpq+pbfprrwIA= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; b=Hk3lO21uvR4sTI6+pNliS4OkYS78HbFhVf5opsmTMcf/L/2eWKc14ew0In0vbhvM7D Uk4STWcqa255ddLNo6vMyYxEneICTZQrZ2Pr/quMJIEGUa0FCaigZiSQu7NooV/WUtIo qzxjsXmuchxdRiBrlc2L6geu//zOLG1bQIFaI= Received: by 10.114.187.3 with SMTP id k3mr6715999waf.82.1257513148686; Fri, 06 Nov 2009 05:12:28 -0800 (PST) Received: from localhost.localdomain ([222.92.8.142]) by mx.google.com with ESMTPS id 20sm26431pxi.7.2009.11.06.05.12.20 (version=TLSv1/SSLv3 cipher=RC4-MD5); Fri, 06 Nov 2009 05:12:28 -0800 (PST) From: Wu Zhangjin To: Ralf Baechle Cc: Arnaud Patard , zhangfx@lemote.com, yanh@lemote.com, huhb@lemote.com, Nicholas Mc Guire , Wu Zhangjin , linux-mips@linux-mips.org Subject: [PATCH -queue v1 6/7] [loongson] lemote-2f: add reset and shutdown support Date: Fri, 6 Nov 2009 21:11:31 +0800 Message-Id: X-Mailer: git-send-email 1.6.2.1 In-Reply-To: <96301eaeffac1ae45d7529760eb961a04356dfca.1257510612.git.wuzhangjin@gmail.com> References: <17e5d58a0cd7273b81c7151b7f7f2096c9694b59.1257510612.git.wuzhangjin@gmail.com> <588574ed5910292f2728072ca147add2ae342778.1257510612.git.wuzhangjin@gmail.com> <7affa8fce1f55b817aff1c64f823824f6809dd85.1257510612.git.wuzhangjin@gmail.com> <84e7310659ae445b3b3dc68aadc8f27648c709f6.1257510612.git.wuzhangjin@gmail.com> <96301eaeffac1ae45d7529760eb961a04356dfca.1257510612.git.wuzhangjin@gmail.com> In-Reply-To: References: Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24728 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips From: Wu Zhangjin fuloong2f, yeeloong2f and menglong2f have different reset/shutdown logic, this patch add respective support for them. Signed-off-by: Wu Zhangjin --- arch/mips/include/asm/mach-loongson/loongson.h | 7 + arch/mips/loongson/lemote-2f/Makefile | 2 +- arch/mips/loongson/lemote-2f/reset.c | 163 ++++++++++++++++++++++++ 3 files changed, 171 insertions(+), 1 deletions(-) create mode 100644 arch/mips/loongson/lemote-2f/reset.c diff --git a/arch/mips/include/asm/mach-loongson/loongson.h b/arch/mips/include/asm/mach-loongson/loongson.h index e7e7a08..5b83bea 100644 --- a/arch/mips/include/asm/mach-loongson/loongson.h +++ b/arch/mips/include/asm/mach-loongson/loongson.h @@ -42,6 +42,13 @@ extern void __init set_irq_trigger_mode(void); extern void __init mach_init_irq(void); extern void mach_irq_dispatch(unsigned int pending); +/* We need this in some places... */ +#define delay() ({ \ + int x; \ + for (x = 0; x < 100000; x++) \ + __asm__ __volatile__(""); \ +}) + #define LOONGSON_REG(x) \ (*(volatile u32 *)((char *)CKSEG1ADDR(LOONGSON_REG_BASE) + (x))) diff --git a/arch/mips/loongson/lemote-2f/Makefile b/arch/mips/loongson/lemote-2f/Makefile index 2e18897..da543b1 100644 --- a/arch/mips/loongson/lemote-2f/Makefile +++ b/arch/mips/loongson/lemote-2f/Makefile @@ -2,4 +2,4 @@ # Makefile for lemote loongson2f family machines # -obj-y += irq.o +obj-y += irq.o reset.o diff --git a/arch/mips/loongson/lemote-2f/reset.c b/arch/mips/loongson/lemote-2f/reset.c new file mode 100644 index 0000000..0459493 --- /dev/null +++ b/arch/mips/loongson/lemote-2f/reset.c @@ -0,0 +1,163 @@ +/* Board-specific reboot/shutdown routines + * + * Copyright (c) 2009 Philippe Vachon + * + * Copyright (C) 2009 Lemote Inc. + * Author: Wu Zhangjin, wuzj@lemote.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include +#include +#include + +#include + +#include + +#include + +static void reset_cpu(void) +{ + /* + * reset cpu to full speed, this is needed when enabling cpu frequency + * scalling + */ + LOONGSON_CHIPCFG0 |= 0x7; +} + +/* reset support for fuloong2f */ + +static void fl2f_reboot(void) +{ + reset_cpu(); + + /* send a reset signal to south bridge. + * + * NOTE: if enable "Power Management" in kernel, rtl8169 will not reset + * normally with this reset operation and it will not work in PMON, but + * you can type halt command and then reboot, seems the hardware reset + * logic not work normally. + */ + { + u32 hi, lo; + _rdmsr(DIVIL_MSR_REG(DIVIL_SOFT_RESET), &hi, &lo); + lo |= 0x00000001; + _wrmsr(DIVIL_MSR_REG(DIVIL_SOFT_RESET), hi, lo); + } +} + +static void fl2f_shutdown(void) +{ + u32 hi, lo, val; + int gpio_base; + + /* get gpio base */ + _rdmsr(DIVIL_MSR_REG(DIVIL_LBAR_GPIO), &hi, &lo); + gpio_base = lo & 0xff00; + + /* make cs5536 gpio13 output enable */ + val = inl(gpio_base + GPIOL_OUT_EN); + val &= ~(1 << (16 + 13)); + val |= (1 << 13); + outl(val, gpio_base + GPIOL_OUT_EN); + mmiowb(); + /* make cs5536 gpio13 output low level voltage. */ + val = inl(gpio_base + GPIOL_OUT_VAL) & ~(1 << (13)); + val |= (1 << (16 + 13)); + outl(val, gpio_base + GPIOL_OUT_VAL); + mmiowb(); +} + +/* reset support for yeeloong2f and mengloong2f notebook */ + +/* + * The following registers are determined by the EC index configuration. + * 1. fill the PORT_HIGH as EC register high part. + * 2. fill the PORT_LOW as EC register low part. + * 3. fill the PORT_DATA as EC register write data or get the data from it. + */ + +#define EC_IO_PORT_HIGH 0x0381 +#define EC_IO_PORT_LOW 0x0382 +#define EC_IO_PORT_DATA 0x0383 +#define REG_RESET_HIGH 0xF4 /* reset the machine auto-clear : rd/wr */ +#define REG_RESET_LOW 0xEC +#define BIT_RESET_ON (1 << 0) + +void ml2f_reboot(void) +{ + reset_cpu(); + + /* sending an reset signal to EC(embedded controller) */ + outb(REG_RESET_HIGH, EC_IO_PORT_HIGH); + outb(REG_RESET_LOW, EC_IO_PORT_LOW); + mmiowb(); + outb(BIT_RESET_ON, EC_IO_PORT_DATA); + mmiowb(); +} + +#define yl2f89_reboot ml2f_reboot + +/* menglong(7inches) laptop has different shutdown logic from 8.9inches */ +#define EC_SHUTDOWN_IO_PORT_HIGH 0xff2d +#define EC_SHUTDOWN_IO_PORT_LOW 0xff2e +#define EC_SHUTDOWN_IO_PORT_DATA 0xff2f +#define REG_SHUTDOWN_HIGH 0xFC +#define REG_SHUTDOWN_LOW 0x29 +#define BIT_SHUTDOWN_ON (1 << 1) + +static void ml2f_shutdown(void) +{ + u8 val; + u64 i; + + outb(REG_SHUTDOWN_HIGH, EC_SHUTDOWN_IO_PORT_HIGH); + outb(REG_SHUTDOWN_LOW, EC_SHUTDOWN_IO_PORT_LOW); + mmiowb(); + val = inb(EC_SHUTDOWN_IO_PORT_DATA); + outb(val & (~BIT_SHUTDOWN_ON), EC_SHUTDOWN_IO_PORT_DATA); + mmiowb(); + /* need enough wait here... how many microseconds needs? */ + for (i = 0; i < 0x10000; i++) + delay(); + outb(val | BIT_SHUTDOWN_ON, EC_SHUTDOWN_IO_PORT_DATA); + mmiowb(); +} + +static void yl2f89_shutdown(void) +{ + /* cpu-gpio0 output low */ + LOONGSON_GPIODATA &= ~0x00000001; + /* cpu-gpio0 as output */ + LOONGSON_GPIOIE &= ~0x00000001; +} + + +/* we only cope with the lemote 2f series */ +typedef void (*mach_reset_func)(void); +static mach_reset_func mach_reset[][2] = { + [MACH_LOONGSON_UNKNOWN] {NULL, NULL}, + [MACH_LEMOTE_FL2E] {NULL, NULL}, + [MACH_LEMOTE_FL2F] {fl2f_reboot, fl2f_shutdown}, + [MACH_LEMOTE_ML2F7] {ml2f_reboot, ml2f_shutdown}, + [MACH_LEMOTE_YL2F89] {yl2f89_reboot, yl2f89_shutdown}, + [MACH_DEXXON_GDIUM2F10] {NULL, NULL}, + [MACH_LOONGSON_END] {NULL, NULL}, +}; + +void mach_prepare_reboot(void) +{ + if (mach_reset[mips_machtype][0]) + mach_reset[mips_machtype][0](); +} + +void mach_prepare_shutdown(void) +{ + if (mach_reset[mips_machtype][1]) + mach_reset[mips_machtype][1](); +} -- 1.6.2.1 From wuzhangjin@gmail.com Fri Nov 6 14:14:53 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 06 Nov 2009 14:15:00 +0100 (CET) Received: from mail-px0-f188.google.com ([209.85.216.188]:51511 "EHLO mail-px0-f188.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492774AbZKFNMj (ORCPT ); Fri, 6 Nov 2009 14:12:39 +0100 Received: by mail-px0-f188.google.com with SMTP id 26so367449pxi.21 for ; Fri, 06 Nov 2009 05:12:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer:in-reply-to:references:in-reply-to:references; bh=zsHY7ssZ75AayV9j/RP4zVFQL8bl31yYaNDPuBUpQLY=; b=Ig5+U+NeN8hBiUVviEAgqQtNvrXal1BcXh9s7V7Yfq6pqbnkYG54h0RGHXLedwqcWN Cqs/Ebwq9a7TOJer8466538PCrZw+y+XH+e9yhhjDdMX7sBwkXqxByZQXlbcxh+TYtXC U/Bms1emyTMcpbSGg+QT5CtTY0bJENHVHCKGU= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; b=wSEmoyj37pnaUfkmLRYwlC1jpyoDXPZltOQ7STgwOzlhWlD1l5bKFS0mab1LPdgpx3 j06pYeDLczSSCPhzmhR23V+GffqZlSCShGNC007z7LrYbXgrECW4IY5hKiDdvDtL9yO5 N0wFQrfmCItXzJ3+pBKajKWzwFO7p/KWgNpis= Received: by 10.115.37.37 with SMTP id p37mr6715573waj.11.1257513157565; Fri, 06 Nov 2009 05:12:37 -0800 (PST) Received: from localhost.localdomain ([222.92.8.142]) by mx.google.com with ESMTPS id 20sm26431pxi.7.2009.11.06.05.12.29 (version=TLSv1/SSLv3 cipher=RC4-MD5); Fri, 06 Nov 2009 05:12:36 -0800 (PST) From: Wu Zhangjin To: Ralf Baechle Cc: Arnaud Patard , zhangfx@lemote.com, yanh@lemote.com, huhb@lemote.com, Nicholas Mc Guire , Wu Zhangjin , linux-mips@linux-mips.org Subject: [PATCH -queue v1 7/7] [loongson] lemote-2f: add defconfig file Date: Fri, 6 Nov 2009 21:11:32 +0800 Message-Id: <8aa69d898cd06ea718dc38756685c45bec8f46fe.1257510612.git.wuzhangjin@gmail.com> X-Mailer: git-send-email 1.6.2.1 In-Reply-To: References: <17e5d58a0cd7273b81c7151b7f7f2096c9694b59.1257510612.git.wuzhangjin@gmail.com> <588574ed5910292f2728072ca147add2ae342778.1257510612.git.wuzhangjin@gmail.com> <7affa8fce1f55b817aff1c64f823824f6809dd85.1257510612.git.wuzhangjin@gmail.com> <84e7310659ae445b3b3dc68aadc8f27648c709f6.1257510612.git.wuzhangjin@gmail.com> <96301eaeffac1ae45d7529760eb961a04356dfca.1257510612.git.wuzhangjin@gmail.com> In-Reply-To: References: Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24729 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips From: Wu Zhangjin This patch add default config file for lemote loongson2f family machines, which means we can use the same kernel image on fuloong2f, yeeloong2f and the other lemote loongson2f family machines. If you are using the old PMON, and not using the 2f box, please add a new command line argument in the boot.cfg. for example, add this argument for 8.9inches notebook: machtype=lemote-yeeloong-2f-8.9inches or simply type(if it can indicate it), machtype=8.9 please get more information from arch/mips/loongson/common/machtype.c Signed-off-by: Wu Zhangjin --- arch/mips/configs/lemote2f_defconfig | 1794 ++++++++++++++++++++++++++++++++++ 1 files changed, 1794 insertions(+), 0 deletions(-) create mode 100644 arch/mips/configs/lemote2f_defconfig diff --git a/arch/mips/configs/lemote2f_defconfig b/arch/mips/configs/lemote2f_defconfig new file mode 100644 index 0000000..6441448 --- /dev/null +++ b/arch/mips/configs/lemote2f_defconfig @@ -0,0 +1,1794 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.32-rc6 +# Fri Nov 6 20:00:54 2009 +# +CONFIG_MIPS=y + +# +# Machine selection +# +# CONFIG_MACH_ALCHEMY is not set +# CONFIG_AR7 is not set +# CONFIG_BASLER_EXCITE is not set +# CONFIG_BCM47XX is not set +# CONFIG_BCM63XX is not set +# CONFIG_MIPS_COBALT is not set +# CONFIG_MACH_DECSTATION is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_LASAT is not set +CONFIG_MACH_LOONGSON=y +# CONFIG_MIPS_MALTA is not set +# CONFIG_MIPS_SIM is not set +# CONFIG_NEC_MARKEINS is not set +# CONFIG_MACH_VR41XX is not set +# CONFIG_NXP_STB220 is not set +# CONFIG_NXP_STB225 is not set +# CONFIG_PNX8550_JBS is not set +# CONFIG_PNX8550_STB810 is not set +# CONFIG_PMC_MSP is not set +# CONFIG_PMC_YOSEMITE is not set +# CONFIG_SGI_IP22 is not set +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP28 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_CRHONE is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_BIGSUR is not set +# CONFIG_SNI_RM is not set +# CONFIG_MACH_TX39XX is not set +# CONFIG_MACH_TX49XX is not set +# CONFIG_MIKROTIK_RB532 is not set +# CONFIG_WR_PPMC is not set +# CONFIG_CAVIUM_OCTEON_SIMULATOR is not set +# CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD is not set +# CONFIG_ALCHEMY_GPIO_INDIRECT is not set +CONFIG_ARCH_SPARSEMEM_ENABLE=y +# CONFIG_LEMOTE_FULOONG2E is not set +CONFIG_LEMOTE_MACH2F=y +CONFIG_CS5536=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_ARCH_SUPPORTS_OPROFILE=y +CONFIG_GENERIC_FIND_NEXT_BIT=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CMOS_UPDATE=y +CONFIG_SCHED_OMIT_FRAME_POINTER=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +CONFIG_CEVT_R4K_LIB=y +CONFIG_CEVT_R4K=y +CONFIG_CSRC_R4K_LIB=y +CONFIG_CSRC_R4K=y +CONFIG_DMA_NONCOHERENT=y +CONFIG_DMA_NEED_PCI_MAP_STATE=y +CONFIG_EARLY_PRINTK=y +CONFIG_SYS_HAS_EARLY_PRINTK=y +CONFIG_I8259=y +# CONFIG_NO_IOPORT is not set +CONFIG_GENERIC_ISA_DMA=y +CONFIG_GENERIC_ISA_DMA_SUPPORT_BROKEN=y +# CONFIG_CPU_BIG_ENDIAN is not set +CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y +CONFIG_IRQ_CPU=y +CONFIG_BOOT_ELF32=y +CONFIG_MIPS_L1_CACHE_SHIFT=5 + +# +# CPU selection +# +# CONFIG_CPU_LOONGSON2E is not set +CONFIG_CPU_LOONGSON2F=y +# CONFIG_CPU_MIPS32_R1 is not set +# CONFIG_CPU_MIPS32_R2 is not set +# CONFIG_CPU_MIPS64_R1 is not set +# CONFIG_CPU_MIPS64_R2 is not set +# CONFIG_CPU_R3000 is not set +# CONFIG_CPU_TX39XX is not set +# CONFIG_CPU_VR41XX is not set +# CONFIG_CPU_R4300 is not set +# CONFIG_CPU_R4X00 is not set +# CONFIG_CPU_TX49XX is not set +# CONFIG_CPU_R5000 is not set +# CONFIG_CPU_R5432 is not set +# CONFIG_CPU_R5500 is not set +# CONFIG_CPU_R6000 is not set +# CONFIG_CPU_NEVADA is not set +# CONFIG_CPU_R8000 is not set +# CONFIG_CPU_R10000 is not set +# CONFIG_CPU_RM7000 is not set +# CONFIG_CPU_RM9000 is not set +# CONFIG_CPU_SB1 is not set +# CONFIG_CPU_CAVIUM_OCTEON is not set +CONFIG_SYS_SUPPORTS_ZBOOT=y +CONFIG_SYS_SUPPORTS_ZBOOT_UART16550=y +CONFIG_CPU_LOONGSON2=y +CONFIG_SYS_HAS_CPU_LOONGSON2F=y +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y + +# +# Kernel type +# +# CONFIG_32BIT is not set +CONFIG_64BIT=y +# CONFIG_PAGE_SIZE_4KB is not set +# CONFIG_PAGE_SIZE_8KB is not set +CONFIG_PAGE_SIZE_16KB=y +# CONFIG_PAGE_SIZE_32KB is not set +# CONFIG_PAGE_SIZE_64KB is not set +CONFIG_BOARD_SCACHE=y +CONFIG_MIPS_MT_DISABLED=y +# CONFIG_MIPS_MT_SMP is not set +# CONFIG_MIPS_MT_SMTC is not set +CONFIG_CPU_HAS_WB=y +CONFIG_CPU_HAS_SYNC=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_CPU_SUPPORTS_HIGHMEM=y +CONFIG_SYS_SUPPORTS_HIGHMEM=y +CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_ARCH_POPULATES_NODE_MAP=y +CONFIG_SELECT_MEMORY_MODEL=y +# CONFIG_FLATMEM_MANUAL is not set +# CONFIG_DISCONTIGMEM_MANUAL is not set +CONFIG_SPARSEMEM_MANUAL=y +CONFIG_SPARSEMEM=y +CONFIG_HAVE_MEMORY_PRESENT=y +CONFIG_SPARSEMEM_STATIC=y + +# +# Memory hotplug is currently incompatible with Software Suspend +# +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +CONFIG_PHYS_ADDR_T_64BIT=y +CONFIG_ZONE_DMA_FLAG=0 +CONFIG_VIRT_TO_BUS=y +CONFIG_HAVE_MLOCK=y +CONFIG_HAVE_MLOCKED_PAGE_BIT=y +# CONFIG_KSM is not set +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +# CONFIG_HZ_48 is not set +# CONFIG_HZ_100 is not set +# CONFIG_HZ_128 is not set +CONFIG_HZ_250=y +# CONFIG_HZ_256 is not set +# CONFIG_HZ_1000 is not set +# CONFIG_HZ_1024 is not set +CONFIG_SYS_SUPPORTS_ARBIT_HZ=y +CONFIG_HZ=250 +# CONFIG_PREEMPT_NONE is not set +# CONFIG_PREEMPT_VOLUNTARY is not set +CONFIG_PREEMPT=y +# CONFIG_KEXEC is not set +# CONFIG_SECCOMP is not set +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_CONSTRUCTORS=y + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_LOCK_KERNEL=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="" +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_BZIP2=y +CONFIG_HAVE_KERNEL_LZMA=y +# CONFIG_KERNEL_GZIP is not set +# CONFIG_KERNEL_BZIP2 is not set +CONFIG_KERNEL_LZMA=y +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_POSIX_MQUEUE is not set +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y +# CONFIG_TASKSTATS is not set +CONFIG_AUDIT=y + +# +# RCU Subsystem +# +CONFIG_TREE_RCU=y +# CONFIG_TREE_PREEMPT_RCU is not set +# CONFIG_RCU_TRACE is not set +CONFIG_RCU_FANOUT=64 +# CONFIG_RCU_FANOUT_EXACT is not set +# CONFIG_TREE_RCU_TRACE is not set +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=15 +# CONFIG_GROUP_SCHED is not set +# CONFIG_CGROUPS is not set +CONFIG_SYSFS_DEPRECATED=y +CONFIG_SYSFS_DEPRECATED_V2=y +# CONFIG_RELAY is not set +# CONFIG_NAMESPACES is not set +# CONFIG_BLK_DEV_INITRD is not set +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +CONFIG_EMBEDDED=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_PCSPKR_PLATFORM=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y + +# +# Kernel Performance Events And Counters +# +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_PCI_QUIRKS=y +CONFIG_SLUB_DEBUG=y +CONFIG_COMPAT_BRK=y +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +CONFIG_HAVE_OPROFILE=y +CONFIG_HAVE_SYSCALL_WRAPPERS=y + +# +# GCOV-based kernel profiling +# +# CONFIG_SLOW_WORK is not set +CONFIG_HAVE_GENERIC_DMA_COHERENT=y +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +CONFIG_MODVERSIONS=y +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_BLOCK=y +CONFIG_BLK_DEV_BSG=y +CONFIG_BLK_DEV_INTEGRITY=y +CONFIG_BLOCK_COMPAT=y + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +# CONFIG_DEFAULT_AS is not set +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" +CONFIG_FREEZER=y + +# +# Bus options (PCI, PCMCIA, EISA, ISA, TC) +# +CONFIG_HW_HAS_PCI=y +CONFIG_PCI=y +CONFIG_PCI_DOMAINS=y +# CONFIG_ARCH_SUPPORTS_MSI is not set +CONFIG_PCI_LEGACY=y +# CONFIG_PCI_STUB is not set +# CONFIG_PCI_IOV is not set +CONFIG_ISA=y +CONFIG_MMU=y +# CONFIG_PCCARD is not set +# CONFIG_HOTPLUG_PCI is not set + +# +# Executable file formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set +# CONFIG_BINFMT_MISC is not set +CONFIG_MIPS32_COMPAT=y +CONFIG_COMPAT=y +CONFIG_SYSVIPC_COMPAT=y +CONFIG_MIPS32_O32=y +CONFIG_MIPS32_N32=y +CONFIG_BINFMT_ELF32=y + +# +# Power management options +# +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_PM=y +# CONFIG_PM_DEBUG is not set +CONFIG_PM_SLEEP=y +CONFIG_SUSPEND=y +CONFIG_SUSPEND_FREEZER=y +CONFIG_HIBERNATION_NVS=y +CONFIG_HIBERNATION=y +CONFIG_PM_STD_PARTITION="/dev/hda3" +# CONFIG_PM_RUNTIME is not set +CONFIG_NET=y +CONFIG_COMPAT_NETLINK_MESSAGES=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_PACKET_MMAP=y +CONFIG_UNIX=y +CONFIG_XFRM=y +# CONFIG_XFRM_USER is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set +# CONFIG_NET_KEY is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_ASK_IP_FIB_HASH=y +# CONFIG_IP_FIB_TRIE is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_IP_ROUTE_MULTIPATH=y +CONFIG_IP_ROUTE_VERBOSE=y +# CONFIG_IP_PNP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +CONFIG_IP_MROUTE=y +CONFIG_IP_PIMSM_V1=y +CONFIG_IP_PIMSM_V2=y +# CONFIG_ARPD is not set +CONFIG_SYN_COOKIES=y +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +CONFIG_INET_TUNNEL=m +CONFIG_INET_XFRM_MODE_TRANSPORT=m +CONFIG_INET_XFRM_MODE_TUNNEL=m +CONFIG_INET_XFRM_MODE_BEET=m +CONFIG_INET_LRO=y +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +CONFIG_TCP_CONG_ADVANCED=y +CONFIG_TCP_CONG_BIC=y +CONFIG_TCP_CONG_CUBIC=y +CONFIG_TCP_CONG_WESTWOOD=m +CONFIG_TCP_CONG_HTCP=m +# CONFIG_TCP_CONG_HSTCP is not set +# CONFIG_TCP_CONG_HYBLA is not set +# CONFIG_TCP_CONG_VEGAS is not set +# CONFIG_TCP_CONG_SCALABLE is not set +# CONFIG_TCP_CONG_LP is not set +# CONFIG_TCP_CONG_VENO is not set +# CONFIG_TCP_CONG_YEAH is not set +# CONFIG_TCP_CONG_ILLINOIS is not set +CONFIG_DEFAULT_BIC=y +# CONFIG_DEFAULT_CUBIC is not set +# CONFIG_DEFAULT_HTCP is not set +# CONFIG_DEFAULT_VEGAS is not set +# CONFIG_DEFAULT_WESTWOOD is not set +# CONFIG_DEFAULT_RENO is not set +CONFIG_DEFAULT_TCP_CONG="bic" +# CONFIG_TCP_MD5SIG is not set +CONFIG_IPV6=m +CONFIG_IPV6_PRIVACY=y +# CONFIG_IPV6_ROUTER_PREF is not set +# CONFIG_IPV6_OPTIMISTIC_DAD is not set +# CONFIG_INET6_AH is not set +# CONFIG_INET6_ESP is not set +# CONFIG_INET6_IPCOMP is not set +# CONFIG_IPV6_MIP6 is not set +# CONFIG_INET6_XFRM_TUNNEL is not set +# CONFIG_INET6_TUNNEL is not set +CONFIG_INET6_XFRM_MODE_TRANSPORT=m +CONFIG_INET6_XFRM_MODE_TUNNEL=m +CONFIG_INET6_XFRM_MODE_BEET=m +# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set +CONFIG_IPV6_SIT=m +CONFIG_IPV6_NDISC_NODETYPE=y +# CONFIG_IPV6_TUNNEL is not set +# CONFIG_IPV6_MULTIPLE_TABLES is not set +# CONFIG_IPV6_MROUTE is not set +CONFIG_NETWORK_SECMARK=y +CONFIG_NETFILTER=y +# CONFIG_NETFILTER_DEBUG is not set +CONFIG_NETFILTER_ADVANCED=y + +# +# Core Netfilter Configuration +# +# CONFIG_NETFILTER_NETLINK_QUEUE is not set +# CONFIG_NETFILTER_NETLINK_LOG is not set +# CONFIG_NF_CONNTRACK is not set +# CONFIG_NETFILTER_XTABLES is not set +# CONFIG_IP_VS is not set + +# +# IP: Netfilter Configuration +# +# CONFIG_NF_DEFRAG_IPV4 is not set +# CONFIG_IP_NF_QUEUE is not set +# CONFIG_IP_NF_IPTABLES is not set +# CONFIG_IP_NF_ARPTABLES is not set + +# +# IPv6: Netfilter Configuration +# +# CONFIG_IP6_NF_QUEUE is not set +# CONFIG_IP6_NF_IPTABLES is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_RDS is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_PHONET is not set +# CONFIG_IEEE802154 is not set +CONFIG_NET_SCHED=y + +# +# Queueing/Scheduling +# +# CONFIG_NET_SCH_CBQ is not set +# CONFIG_NET_SCH_HTB is not set +# CONFIG_NET_SCH_HFSC is not set +# CONFIG_NET_SCH_PRIO is not set +# CONFIG_NET_SCH_MULTIQ is not set +# CONFIG_NET_SCH_RED is not set +# CONFIG_NET_SCH_SFQ is not set +# CONFIG_NET_SCH_TEQL is not set +# CONFIG_NET_SCH_TBF is not set +# CONFIG_NET_SCH_GRED is not set +# CONFIG_NET_SCH_DSMARK is not set +# CONFIG_NET_SCH_NETEM is not set +# CONFIG_NET_SCH_DRR is not set +# CONFIG_NET_SCH_INGRESS is not set + +# +# Classification +# +CONFIG_NET_CLS=y +# CONFIG_NET_CLS_BASIC is not set +# CONFIG_NET_CLS_TCINDEX is not set +# CONFIG_NET_CLS_ROUTE4 is not set +# CONFIG_NET_CLS_FW is not set +# CONFIG_NET_CLS_U32 is not set +# CONFIG_NET_CLS_RSVP is not set +# CONFIG_NET_CLS_RSVP6 is not set +# CONFIG_NET_CLS_FLOW is not set +CONFIG_NET_EMATCH=y +CONFIG_NET_EMATCH_STACK=32 +# CONFIG_NET_EMATCH_CMP is not set +# CONFIG_NET_EMATCH_NBYTE is not set +# CONFIG_NET_EMATCH_U32 is not set +# CONFIG_NET_EMATCH_META is not set +# CONFIG_NET_EMATCH_TEXT is not set +CONFIG_NET_CLS_ACT=y +# CONFIG_NET_ACT_POLICE is not set +# CONFIG_NET_ACT_GACT is not set +# CONFIG_NET_ACT_MIRRED is not set +# CONFIG_NET_ACT_NAT is not set +# CONFIG_NET_ACT_PEDIT is not set +# CONFIG_NET_ACT_SIMP is not set +# CONFIG_NET_ACT_SKBEDIT is not set +CONFIG_NET_SCH_FIFO=y +# CONFIG_DCB is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set +CONFIG_FIB_RULES=y +CONFIG_WIRELESS=y +# CONFIG_CFG80211 is not set +CONFIG_CFG80211_DEFAULT_PS_VALUE=0 +# CONFIG_WIRELESS_OLD_REGULATORY is not set +CONFIG_WIRELESS_EXT=y +CONFIG_WIRELESS_EXT_SYSFS=y +# CONFIG_LIB80211 is not set + +# +# CFG80211 needs to be enabled for MAC80211 +# +# CONFIG_WIMAX is not set +CONFIG_RFKILL=m +# CONFIG_RFKILL_INPUT is not set +# CONFIG_NET_9P is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +# CONFIG_DEVTMPFS is not set +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_CONNECTOR is not set +# CONFIG_MTD is not set +# CONFIG_PARPORT is not set +# CONFIG_PNP is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_CPQ_DA is not set +# CONFIG_BLK_CPQ_CISS_DA is not set +# CONFIG_BLK_DEV_DAC960 is not set +# CONFIG_BLK_DEV_UMEM is not set +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_CRYPTOLOOP=y +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_SX8 is not set +# CONFIG_BLK_DEV_UB is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=8192 +# CONFIG_BLK_DEV_XIP is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +# CONFIG_BLK_DEV_HD is not set +CONFIG_MISC_DEVICES=y +# CONFIG_PHANTOM is not set +# CONFIG_SGI_IOC4 is not set +# CONFIG_TIFM_CORE is not set +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_HP_ILO is not set +# CONFIG_C2PORT is not set + +# +# EEPROM support +# +# CONFIG_EEPROM_93CX6 is not set +# CONFIG_CB710_CORE is not set +CONFIG_HAVE_IDE=y +CONFIG_IDE=y + +# +# Please see Documentation/ide/ide.txt for help/info on IDE drives +# +CONFIG_IDE_XFER_MODE=y +CONFIG_IDE_TIMINGS=y +# CONFIG_BLK_DEV_IDE_SATA is not set +CONFIG_IDE_GD=y +CONFIG_IDE_GD_ATA=y +# CONFIG_IDE_GD_ATAPI is not set +# CONFIG_BLK_DEV_IDECD is not set +# CONFIG_BLK_DEV_IDETAPE is not set +CONFIG_IDE_TASK_IOCTL=y +CONFIG_IDE_PROC_FS=y + +# +# IDE chipset support/bugfixes +# +# CONFIG_IDE_GENERIC is not set +# CONFIG_BLK_DEV_PLATFORM is not set +CONFIG_BLK_DEV_IDEDMA_SFF=y + +# +# PCI IDE chipsets support +# +CONFIG_BLK_DEV_IDEPCI=y +# CONFIG_IDEPCI_PCIBUS_ORDER is not set +# CONFIG_BLK_DEV_OFFBOARD is not set +CONFIG_BLK_DEV_GENERIC=y +# CONFIG_BLK_DEV_OPTI621 is not set +CONFIG_BLK_DEV_IDEDMA_PCI=y +# CONFIG_BLK_DEV_AEC62XX is not set +# CONFIG_BLK_DEV_ALI15X3 is not set +CONFIG_BLK_DEV_AMD74XX=y +# CONFIG_BLK_DEV_CMD64X is not set +# CONFIG_BLK_DEV_TRIFLEX is not set +# CONFIG_BLK_DEV_CS5520 is not set +# CONFIG_BLK_DEV_CS5530 is not set +# CONFIG_BLK_DEV_HPT366 is not set +# CONFIG_BLK_DEV_JMICRON is not set +# CONFIG_BLK_DEV_SC1200 is not set +# CONFIG_BLK_DEV_PIIX is not set +# CONFIG_BLK_DEV_IT8172 is not set +# CONFIG_BLK_DEV_IT8213 is not set +# CONFIG_BLK_DEV_IT821X is not set +# CONFIG_BLK_DEV_NS87415 is not set +# CONFIG_BLK_DEV_PDC202XX_OLD is not set +# CONFIG_BLK_DEV_PDC202XX_NEW is not set +# CONFIG_BLK_DEV_SVWKS is not set +# CONFIG_BLK_DEV_SIIMAGE is not set +# CONFIG_BLK_DEV_SLC90E66 is not set +# CONFIG_BLK_DEV_TRM290 is not set +# CONFIG_BLK_DEV_VIA82CXXX is not set +# CONFIG_BLK_DEV_TC86C001 is not set + +# +# Other IDE chipsets support +# + +# +# Note: most of these also require special kernel boot parameters +# +# CONFIG_BLK_DEV_4DRIVES is not set +# CONFIG_BLK_DEV_ALI14XX is not set +# CONFIG_BLK_DEV_DTC2278 is not set +# CONFIG_BLK_DEV_HT6560B is not set +# CONFIG_BLK_DEV_QD65XX is not set +# CONFIG_BLK_DEV_UMC8672 is not set +CONFIG_BLK_DEV_IDEDMA=y + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=m +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_NETLINK is not set +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=m +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_BLK_DEV_SR is not set +CONFIG_CHR_DEV_SG=m +# CONFIG_CHR_DEV_SCH is not set +CONFIG_SCSI_MULTI_LUN=y +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set +CONFIG_SCSI_WAIT_SCAN=m + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +# CONFIG_SCSI_LOWLEVEL is not set +# CONFIG_SCSI_DH is not set +# CONFIG_SCSI_OSD_INITIATOR is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +# CONFIG_FUSION is not set + +# +# IEEE 1394 (FireWire) support +# + +# +# You can enable one or both FireWire driver stacks. +# + +# +# See the help texts for more information. +# +# CONFIG_FIREWIRE is not set +# CONFIG_IEEE1394 is not set +# CONFIG_I2O is not set +CONFIG_NETDEVICES=y +# CONFIG_IFB is not set +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_VETH is not set +# CONFIG_ARCNET is not set +# CONFIG_PHYLIB is not set +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +# CONFIG_AX88796 is not set +# CONFIG_HAPPYMEAL is not set +# CONFIG_SUNGEM is not set +# CONFIG_CASSINI is not set +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_NET_VENDOR_SMC is not set +# CONFIG_SMC91X is not set +# CONFIG_DM9000 is not set +# CONFIG_ETHOC is not set +# CONFIG_NET_VENDOR_RACAL is not set +# CONFIG_DNET is not set +# CONFIG_NET_TULIP is not set +# CONFIG_AT1700 is not set +# CONFIG_DEPCA is not set +# CONFIG_HP100 is not set +# CONFIG_NET_ISA is not set +# CONFIG_IBM_NEW_EMAC_ZMII is not set +# CONFIG_IBM_NEW_EMAC_RGMII is not set +# CONFIG_IBM_NEW_EMAC_TAH is not set +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set +CONFIG_NET_PCI=y +# CONFIG_PCNET32 is not set +# CONFIG_AMD8111_ETH is not set +# CONFIG_ADAPTEC_STARFIRE is not set +# CONFIG_AC3200 is not set +# CONFIG_APRICOT is not set +# CONFIG_B44 is not set +# CONFIG_FORCEDETH is not set +# CONFIG_CS89x0 is not set +# CONFIG_TC35815 is not set +# CONFIG_E100 is not set +# CONFIG_FEALNX is not set +# CONFIG_NATSEMI is not set +# CONFIG_NE2K_PCI is not set +# CONFIG_8139CP is not set +CONFIG_8139TOO=y +# CONFIG_8139TOO_PIO is not set +CONFIG_8139TOO_TUNE_TWISTER=y +# CONFIG_8139TOO_8129 is not set +# CONFIG_8139_OLD_RX_RESET is not set +# CONFIG_R6040 is not set +# CONFIG_SIS900 is not set +# CONFIG_EPIC100 is not set +# CONFIG_SMSC9420 is not set +# CONFIG_SUNDANCE is not set +# CONFIG_TLAN is not set +# CONFIG_KS8842 is not set +# CONFIG_KS8851_MLL is not set +# CONFIG_VIA_RHINE is not set +# CONFIG_SC92031 is not set +# CONFIG_ATL2 is not set +CONFIG_NETDEV_1000=y +# CONFIG_ACENIC is not set +# CONFIG_DL2K is not set +# CONFIG_E1000 is not set +# CONFIG_E1000E is not set +# CONFIG_IP1000 is not set +# CONFIG_IGB is not set +# CONFIG_IGBVF is not set +# CONFIG_NS83820 is not set +# CONFIG_HAMACHI is not set +# CONFIG_YELLOWFIN is not set +CONFIG_R8169=y +# CONFIG_SIS190 is not set +# CONFIG_SKGE is not set +# CONFIG_SKY2 is not set +# CONFIG_VIA_VELOCITY is not set +# CONFIG_TIGON3 is not set +# CONFIG_BNX2 is not set +# CONFIG_CNIC is not set +# CONFIG_QLA3XXX is not set +# CONFIG_ATL1 is not set +# CONFIG_ATL1E is not set +# CONFIG_ATL1C is not set +# CONFIG_JME is not set +# CONFIG_NETDEV_10000 is not set +# CONFIG_TR is not set +CONFIG_WLAN=y +CONFIG_WLAN_PRE80211=y +# CONFIG_STRIP is not set +# CONFIG_WAVELAN is not set +CONFIG_WLAN_80211=y +# CONFIG_LIBERTAS is not set +# CONFIG_ATMEL is not set +# CONFIG_PRISM54 is not set +# CONFIG_USB_ZD1201 is not set +# CONFIG_HOSTAP is not set + +# +# Enable WiMAX (Networking options) to see the WiMAX drivers +# + +# +# USB Network Adapters +# +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_USBNET is not set +# CONFIG_USB_HSO is not set +# CONFIG_WAN is not set +# CONFIG_FDDI is not set +# CONFIG_HIPPI is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_NET_FC is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_ISDN is not set +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_MOUSEDEV_PSAUX=y +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +CONFIG_KEYBOARD_ATKBD=y +# CONFIG_KEYBOARD_LKKBD is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_OPENCORES is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_XTKBD is not set +CONFIG_INPUT_MOUSE=y +CONFIG_MOUSE_PS2=y +# CONFIG_MOUSE_PS2_ALPS is not set +# CONFIG_MOUSE_PS2_LOGIPS2PP is not set +CONFIG_MOUSE_PS2_SYNAPTICS=y +# CONFIG_MOUSE_PS2_TRACKPOINT is not set +# CONFIG_MOUSE_PS2_ELANTECH is not set +# CONFIG_MOUSE_PS2_SENTELIC is not set +# CONFIG_MOUSE_PS2_TOUCHKIT is not set +# CONFIG_MOUSE_SERIAL is not set +# CONFIG_MOUSE_APPLETOUCH is not set +# CONFIG_MOUSE_BCM5974 is not set +# CONFIG_MOUSE_INPORT is not set +# CONFIG_MOUSE_LOGIBM is not set +# CONFIG_MOUSE_PC110PAD is not set +# CONFIG_MOUSE_VSXXXAA is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +CONFIG_SERIO_I8042=y +# CONFIG_SERIO_SERPORT is not set +# CONFIG_SERIO_PCIPS2 is not set +CONFIG_SERIO_LIBPS2=y +# CONFIG_SERIO_RAW is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +CONFIG_DEVKMEM=y +CONFIG_SERIAL_NONSTANDARD=y +# CONFIG_COMPUTONE is not set +# CONFIG_ROCKETPORT is not set +# CONFIG_CYCLADES is not set +# CONFIG_DIGIEPCA is not set +# CONFIG_MOXA_INTELLIO is not set +# CONFIG_MOXA_SMARTIO is not set +# CONFIG_ISI is not set +# CONFIG_SYNCLINKMP is not set +# CONFIG_SYNCLINK_GT is not set +# CONFIG_N_HDLC is not set +# CONFIG_RISCOM8 is not set +# CONFIG_SPECIALIX is not set +# CONFIG_STALDRV is not set +# CONFIG_NOZOMI is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +# CONFIG_SERIAL_8250_PCI is not set +CONFIG_SERIAL_8250_NR_UARTS=16 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +CONFIG_SERIAL_8250_EXTENDED=y +CONFIG_SERIAL_8250_MANY_PORTS=y +CONFIG_SERIAL_8250_FOURPORT=y +# CONFIG_SERIAL_8250_ACCENT is not set +# CONFIG_SERIAL_8250_BOCA is not set +# CONFIG_SERIAL_8250_EXAR_ST16C554 is not set +# CONFIG_SERIAL_8250_HUB6 is not set +# CONFIG_SERIAL_8250_SHARE_IRQ is not set +# CONFIG_SERIAL_8250_DETECT_IRQ is not set +# CONFIG_SERIAL_8250_RSA is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_JSM is not set +CONFIG_UNIX98_PTYS=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=16 +# CONFIG_IPMI_HANDLER is not set +CONFIG_HW_RANDOM=y +# CONFIG_HW_RANDOM_TIMERIOMEM is not set +CONFIG_RTC=y +# CONFIG_DTLK is not set +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +CONFIG_DEVPORT=y +# CONFIG_I2C is not set +# CONFIG_SPI is not set + +# +# PPS support +# +# CONFIG_PPS is not set +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +CONFIG_HWMON=y +# CONFIG_HWMON_VID is not set +# CONFIG_HWMON_DEBUG_CHIP is not set + +# +# Native drivers +# +# CONFIG_SENSORS_I5K_AMB is not set +# CONFIG_SENSORS_F71805F is not set +# CONFIG_SENSORS_F71882FG is not set +# CONFIG_SENSORS_IT87 is not set +# CONFIG_SENSORS_PC87360 is not set +# CONFIG_SENSORS_PC87427 is not set +# CONFIG_SENSORS_SIS5595 is not set +# CONFIG_SENSORS_SMSC47M1 is not set +# CONFIG_SENSORS_SMSC47B397 is not set +# CONFIG_SENSORS_VIA686A is not set +# CONFIG_SENSORS_VT1211 is not set +# CONFIG_SENSORS_VT8231 is not set +# CONFIG_SENSORS_W83627HF is not set +# CONFIG_SENSORS_W83627EHF is not set +CONFIG_THERMAL=y +# CONFIG_THERMAL_HWMON is not set +# CONFIG_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_REGULATOR is not set +CONFIG_MEDIA_SUPPORT=m + +# +# Multimedia core support +# +CONFIG_VIDEO_DEV=m +CONFIG_VIDEO_V4L2_COMMON=m +CONFIG_VIDEO_ALLOW_V4L1=y +CONFIG_VIDEO_V4L1_COMPAT=y +# CONFIG_DVB_CORE is not set +CONFIG_VIDEO_MEDIA=m + +# +# Multimedia drivers +# +# CONFIG_MEDIA_ATTACH is not set +CONFIG_VIDEO_V4L2=m +CONFIG_VIDEO_V4L1=m +CONFIG_VIDEO_CAPTURE_DRIVERS=y +# CONFIG_VIDEO_ADV_DEBUG is not set +# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set +CONFIG_VIDEO_HELPER_CHIPS_AUTO=y +# CONFIG_VIDEO_VIVI is not set +# CONFIG_VIDEO_PMS is not set +# CONFIG_VIDEO_CPIA is not set +# CONFIG_VIDEO_CPIA2 is not set +# CONFIG_VIDEO_STRADIS is not set +CONFIG_V4L_USB_DRIVERS=y +CONFIG_USB_VIDEO_CLASS=m +CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y +CONFIG_USB_GSPCA=m +# CONFIG_USB_M5602 is not set +# CONFIG_USB_STV06XX is not set +# CONFIG_USB_GL860 is not set +# CONFIG_USB_GSPCA_CONEX is not set +# CONFIG_USB_GSPCA_ETOMS is not set +# CONFIG_USB_GSPCA_FINEPIX is not set +# CONFIG_USB_GSPCA_JEILINJ is not set +# CONFIG_USB_GSPCA_MARS is not set +# CONFIG_USB_GSPCA_MR97310A is not set +# CONFIG_USB_GSPCA_OV519 is not set +# CONFIG_USB_GSPCA_OV534 is not set +# CONFIG_USB_GSPCA_PAC207 is not set +# CONFIG_USB_GSPCA_PAC7311 is not set +# CONFIG_USB_GSPCA_SN9C20X is not set +# CONFIG_USB_GSPCA_SONIXB is not set +# CONFIG_USB_GSPCA_SONIXJ is not set +# CONFIG_USB_GSPCA_SPCA500 is not set +# CONFIG_USB_GSPCA_SPCA501 is not set +# CONFIG_USB_GSPCA_SPCA505 is not set +# CONFIG_USB_GSPCA_SPCA506 is not set +# CONFIG_USB_GSPCA_SPCA508 is not set +# CONFIG_USB_GSPCA_SPCA561 is not set +# CONFIG_USB_GSPCA_SQ905 is not set +# CONFIG_USB_GSPCA_SQ905C is not set +# CONFIG_USB_GSPCA_STK014 is not set +# CONFIG_USB_GSPCA_SUNPLUS is not set +# CONFIG_USB_GSPCA_T613 is not set +# CONFIG_USB_GSPCA_TV8532 is not set +# CONFIG_USB_GSPCA_VC032X is not set +# CONFIG_USB_GSPCA_ZC3XX is not set +# CONFIG_VIDEO_HDPVR is not set +# CONFIG_USB_VICAM is not set +# CONFIG_USB_IBMCAM is not set +# CONFIG_USB_KONICAWC is not set +# CONFIG_USB_QUICKCAM_MESSENGER is not set +# CONFIG_USB_ET61X251 is not set +# CONFIG_USB_OV511 is not set +# CONFIG_USB_SE401 is not set +# CONFIG_USB_SN9C102 is not set +# CONFIG_USB_STV680 is not set +# CONFIG_USB_ZC0301 is not set +# CONFIG_USB_PWC is not set +CONFIG_USB_PWC_INPUT_EVDEV=y +# CONFIG_USB_ZR364XX is not set +# CONFIG_USB_STKWEBCAM is not set +# CONFIG_USB_S2255 is not set +# CONFIG_RADIO_ADAPTERS is not set +# CONFIG_DAB is not set + +# +# Graphics support +# +CONFIG_VGA_ARB=y +# CONFIG_DRM is not set +# CONFIG_VGASTATE is not set +CONFIG_VIDEO_OUTPUT_CONTROL=y +CONFIG_FB=y +CONFIG_FIRMWARE_EDID=y +# CONFIG_FB_DDC is not set +CONFIG_FB_BOOT_VESA_SUPPORT=y +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y +# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set +# CONFIG_FB_SYS_FILLRECT is not set +# CONFIG_FB_SYS_COPYAREA is not set +# CONFIG_FB_SYS_IMAGEBLIT is not set +# CONFIG_FB_FOREIGN_ENDIAN is not set +# CONFIG_FB_SYS_FOPS is not set +# CONFIG_FB_SVGALIB is not set +# CONFIG_FB_MACMODES is not set +# CONFIG_FB_BACKLIGHT is not set +CONFIG_FB_MODE_HELPERS=y +CONFIG_FB_TILEBLITTING=y + +# +# Frame buffer hardware drivers +# +# CONFIG_FB_CIRRUS is not set +# CONFIG_FB_PM2 is not set +# CONFIG_FB_CYBER2000 is not set +# CONFIG_FB_ASILIANT is not set +# CONFIG_FB_IMSTT is not set +# CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_NVIDIA is not set +# CONFIG_FB_RIVA is not set +# CONFIG_FB_MATROX is not set +# CONFIG_FB_RADEON is not set +# CONFIG_FB_ATY128 is not set +# CONFIG_FB_ATY is not set +# CONFIG_FB_S3 is not set +# CONFIG_FB_SAVAGE is not set +CONFIG_FB_SIS=y +CONFIG_FB_SIS_300=y +CONFIG_FB_SIS_315=y +# CONFIG_FB_VIA is not set +# CONFIG_FB_NEOMAGIC is not set +# CONFIG_FB_KYRO is not set +# CONFIG_FB_3DFX is not set +# CONFIG_FB_VOODOO1 is not set +# CONFIG_FB_VT8623 is not set +# CONFIG_FB_TRIDENT is not set +# CONFIG_FB_ARK is not set +# CONFIG_FB_PM3 is not set +# CONFIG_FB_CARMINE is not set +CONFIG_FB_SM712=y +CONFIG_FB_SM712_ACCEL=y +# CONFIG_FB_SM712_DUALHEAD is not set +# CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_METRONOME is not set +# CONFIG_FB_MB862XX is not set +# CONFIG_FB_BROADSHEET is not set +CONFIG_BACKLIGHT_LCD_SUPPORT=y +# CONFIG_LCD_CLASS_DEVICE is not set +CONFIG_BACKLIGHT_CLASS_DEVICE=y +CONFIG_BACKLIGHT_GENERIC=y + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +# CONFIG_MDA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE=y +# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set +CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y +CONFIG_FONTS=y +CONFIG_FONT_8x8=y +CONFIG_FONT_8x16=y +CONFIG_FONT_6x11=y +CONFIG_FONT_7x14=y +CONFIG_FONT_PEARL_8x8=y +CONFIG_FONT_ACORN_8x8=y +CONFIG_FONT_MINI_4x6=y +CONFIG_FONT_SUN8x16=y +CONFIG_FONT_SUN12x22=y +CONFIG_FONT_10x18=y +CONFIG_LOGO=y +# CONFIG_LOGO_LINUX_MONO is not set +# CONFIG_LOGO_LINUX_VGA16 is not set +CONFIG_LOGO_LINUX_CLUT224=y +CONFIG_SOUND=m +# CONFIG_SOUND_OSS_CORE is not set +CONFIG_SND=m +CONFIG_SND_TIMER=m +CONFIG_SND_PCM=m +# CONFIG_SND_SEQUENCER is not set +# CONFIG_SND_MIXER_OSS is not set +# CONFIG_SND_PCM_OSS is not set +# CONFIG_SND_HRTIMER is not set +# CONFIG_SND_RTCTIMER is not set +# CONFIG_SND_DYNAMIC_MINORS is not set +# CONFIG_SND_SUPPORT_OLD_API is not set +# CONFIG_SND_VERBOSE_PROCFS is not set +# CONFIG_SND_VERBOSE_PRINTK is not set +# CONFIG_SND_DEBUG is not set +CONFIG_SND_VMASTER=y +# CONFIG_SND_RAWMIDI_SEQ is not set +# CONFIG_SND_OPL3_LIB_SEQ is not set +# CONFIG_SND_OPL4_LIB_SEQ is not set +# CONFIG_SND_SBAWE_SEQ is not set +# CONFIG_SND_EMU10K1_SEQ is not set +CONFIG_SND_AC97_CODEC=m +# CONFIG_SND_DRIVERS is not set +CONFIG_SND_PCI=y +# CONFIG_SND_AD1889 is not set +# CONFIG_SND_ALS300 is not set +# CONFIG_SND_ALI5451 is not set +# CONFIG_SND_ATIIXP is not set +# CONFIG_SND_ATIIXP_MODEM is not set +# CONFIG_SND_AU8810 is not set +# CONFIG_SND_AU8820 is not set +# CONFIG_SND_AU8830 is not set +# CONFIG_SND_AW2 is not set +# CONFIG_SND_AZT3328 is not set +# CONFIG_SND_BT87X is not set +# CONFIG_SND_CA0106 is not set +# CONFIG_SND_CMIPCI is not set +# CONFIG_SND_OXYGEN is not set +# CONFIG_SND_CS4281 is not set +# CONFIG_SND_CS46XX is not set +CONFIG_SND_CS5535AUDIO=m +# CONFIG_SND_CTXFI is not set +# CONFIG_SND_DARLA20 is not set +# CONFIG_SND_GINA20 is not set +# CONFIG_SND_LAYLA20 is not set +# CONFIG_SND_DARLA24 is not set +# CONFIG_SND_GINA24 is not set +# CONFIG_SND_LAYLA24 is not set +# CONFIG_SND_MONA is not set +# CONFIG_SND_MIA is not set +# CONFIG_SND_ECHO3G is not set +# CONFIG_SND_INDIGO is not set +# CONFIG_SND_INDIGOIO is not set +# CONFIG_SND_INDIGODJ is not set +# CONFIG_SND_INDIGOIOX is not set +# CONFIG_SND_INDIGODJX is not set +# CONFIG_SND_EMU10K1 is not set +# CONFIG_SND_EMU10K1X is not set +# CONFIG_SND_ENS1370 is not set +# CONFIG_SND_ENS1371 is not set +# CONFIG_SND_ES1938 is not set +# CONFIG_SND_ES1968 is not set +# CONFIG_SND_FM801 is not set +# CONFIG_SND_HDA_INTEL is not set +# CONFIG_SND_HDSP is not set +# CONFIG_SND_HDSPM is not set +# CONFIG_SND_HIFIER is not set +# CONFIG_SND_ICE1712 is not set +# CONFIG_SND_ICE1724 is not set +# CONFIG_SND_INTEL8X0 is not set +# CONFIG_SND_INTEL8X0M is not set +# CONFIG_SND_KORG1212 is not set +# CONFIG_SND_LX6464ES is not set +# CONFIG_SND_MAESTRO3 is not set +# CONFIG_SND_MIXART is not set +# CONFIG_SND_NM256 is not set +# CONFIG_SND_PCXHR is not set +# CONFIG_SND_RIPTIDE is not set +# CONFIG_SND_RME32 is not set +# CONFIG_SND_RME96 is not set +# CONFIG_SND_RME9652 is not set +# CONFIG_SND_SONICVIBES is not set +# CONFIG_SND_TRIDENT is not set +# CONFIG_SND_VIA82XX is not set +# CONFIG_SND_VIA82XX_MODEM is not set +# CONFIG_SND_VIRTUOSO is not set +# CONFIG_SND_VX222 is not set +# CONFIG_SND_YMFPCI is not set +# CONFIG_SND_MIPS is not set +# CONFIG_SND_USB is not set +# CONFIG_SND_SOC is not set +# CONFIG_SOUND_PRIME is not set +CONFIG_AC97_BUS=m +CONFIG_HID_SUPPORT=y +CONFIG_HID=y +CONFIG_HIDRAW=y + +# +# USB Input Devices +# +CONFIG_USB_HID=y +# CONFIG_HID_PID is not set +CONFIG_USB_HIDDEV=y + +# +# Special HID drivers +# +# CONFIG_HID_A4TECH is not set +# CONFIG_HID_APPLE is not set +# CONFIG_HID_BELKIN is not set +# CONFIG_HID_CHERRY is not set +# CONFIG_HID_CHICONY is not set +# CONFIG_HID_CYPRESS is not set +# CONFIG_HID_DRAGONRISE is not set +# CONFIG_HID_EZKEY is not set +# CONFIG_HID_KYE is not set +# CONFIG_HID_GYRATION is not set +# CONFIG_HID_TWINHAN is not set +# CONFIG_HID_KENSINGTON is not set +# CONFIG_HID_LOGITECH is not set +# CONFIG_HID_MICROSOFT is not set +# CONFIG_HID_MONTEREY is not set +# CONFIG_HID_NTRIG is not set +# CONFIG_HID_PANTHERLORD is not set +# CONFIG_HID_PETALYNX is not set +# CONFIG_HID_SAMSUNG is not set +# CONFIG_HID_SONY is not set +# CONFIG_HID_SUNPLUS is not set +# CONFIG_HID_GREENASIA is not set +# CONFIG_HID_SMARTJOYPLUS is not set +# CONFIG_HID_TOPSEED is not set +# CONFIG_HID_THRUSTMASTER is not set +# CONFIG_HID_ZEROPLUS is not set +CONFIG_USB_SUPPORT=y +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y +CONFIG_USB_ARCH_HAS_EHCI=y +CONFIG_USB=y +# CONFIG_USB_DEBUG is not set +# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set + +# +# Miscellaneous USB options +# +CONFIG_USB_DEVICEFS=y +# CONFIG_USB_DEVICE_CLASS is not set +CONFIG_USB_DYNAMIC_MINORS=y +CONFIG_USB_SUSPEND=y +# CONFIG_USB_OTG is not set +CONFIG_USB_OTG_WHITELIST=y +# CONFIG_USB_OTG_BLACKLIST_HUB is not set +CONFIG_USB_MON=y +# CONFIG_USB_WUSB is not set +# CONFIG_USB_WUSB_CBAF is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_C67X00_HCD is not set +# CONFIG_USB_XHCI_HCD is not set +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y +# CONFIG_USB_EHCI_TT_NEWSCHED is not set +# CONFIG_USB_OXU210HP_HCD is not set +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_ISP1760_HCD is not set +# CONFIG_USB_ISP1362_HCD is not set +CONFIG_USB_OHCI_HCD=y +# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set +# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +CONFIG_USB_UHCI_HCD=m +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_WHCI_HCD is not set +# CONFIG_USB_HWA_HCD is not set + +# +# USB Device Class drivers +# +CONFIG_USB_ACM=m +# CONFIG_USB_PRINTER is not set +CONFIG_USB_WDM=m +# CONFIG_USB_TMC is not set + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may +# + +# +# also be needed; see USB_STORAGE Help for more info +# +CONFIG_USB_STORAGE=m +# CONFIG_USB_STORAGE_DEBUG is not set +CONFIG_USB_STORAGE_DATAFAB=m +CONFIG_USB_STORAGE_FREECOM=m +CONFIG_USB_STORAGE_ISD200=m +CONFIG_USB_STORAGE_USBAT=m +CONFIG_USB_STORAGE_SDDR09=m +CONFIG_USB_STORAGE_SDDR55=m +CONFIG_USB_STORAGE_JUMPSHOT=m +CONFIG_USB_STORAGE_ALAUDA=m +# CONFIG_USB_STORAGE_ONETOUCH is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set +# CONFIG_USB_LIBUSUAL is not set + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set + +# +# USB port drivers +# +CONFIG_USB_SERIAL=m +# CONFIG_USB_EZUSB is not set +CONFIG_USB_SERIAL_GENERIC=y +# CONFIG_USB_SERIAL_AIRCABLE is not set +# CONFIG_USB_SERIAL_ARK3116 is not set +# CONFIG_USB_SERIAL_BELKIN is not set +# CONFIG_USB_SERIAL_CH341 is not set +# CONFIG_USB_SERIAL_WHITEHEAT is not set +# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set +# CONFIG_USB_SERIAL_CP210X is not set +# CONFIG_USB_SERIAL_CYPRESS_M8 is not set +# CONFIG_USB_SERIAL_EMPEG is not set +# CONFIG_USB_SERIAL_FTDI_SIO is not set +# CONFIG_USB_SERIAL_FUNSOFT is not set +# CONFIG_USB_SERIAL_VISOR is not set +# CONFIG_USB_SERIAL_IPAQ is not set +# CONFIG_USB_SERIAL_IR is not set +# CONFIG_USB_SERIAL_EDGEPORT is not set +# CONFIG_USB_SERIAL_EDGEPORT_TI is not set +# CONFIG_USB_SERIAL_GARMIN is not set +# CONFIG_USB_SERIAL_IPW is not set +# CONFIG_USB_SERIAL_IUU is not set +# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set +# CONFIG_USB_SERIAL_KEYSPAN is not set +# CONFIG_USB_SERIAL_KLSI is not set +# CONFIG_USB_SERIAL_KOBIL_SCT is not set +# CONFIG_USB_SERIAL_MCT_U232 is not set +# CONFIG_USB_SERIAL_MOS7720 is not set +# CONFIG_USB_SERIAL_MOS7840 is not set +# CONFIG_USB_SERIAL_MOTOROLA is not set +# CONFIG_USB_SERIAL_NAVMAN is not set +# CONFIG_USB_SERIAL_PL2303 is not set +# CONFIG_USB_SERIAL_OTI6858 is not set +# CONFIG_USB_SERIAL_QUALCOMM is not set +# CONFIG_USB_SERIAL_SPCP8X5 is not set +# CONFIG_USB_SERIAL_HP4X is not set +# CONFIG_USB_SERIAL_SAFE is not set +# CONFIG_USB_SERIAL_SIEMENS_MPI is not set +# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set +# CONFIG_USB_SERIAL_SYMBOL is not set +# CONFIG_USB_SERIAL_TI is not set +# CONFIG_USB_SERIAL_CYBERJACK is not set +# CONFIG_USB_SERIAL_XIRCOM is not set +# CONFIG_USB_SERIAL_OPTION is not set +# CONFIG_USB_SERIAL_OMNINET is not set +# CONFIG_USB_SERIAL_OPTICON is not set +# CONFIG_USB_SERIAL_DEBUG is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_BERRY_CHARGE is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_SISUSBVGA is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_TEST is not set +# CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_VST is not set +# CONFIG_USB_GADGET is not set + +# +# OTG and related infrastructure +# +# CONFIG_NOP_USB_XCEIV is not set +# CONFIG_UWB is not set +# CONFIG_MMC is not set +# CONFIG_MEMSTICK is not set +# CONFIG_NEW_LEDS is not set +# CONFIG_ACCESSIBILITY is not set +# CONFIG_INFINIBAND is not set +# CONFIG_RTC_CLASS is not set +# CONFIG_DMADEVICES is not set +# CONFIG_AUXDISPLAY is not set +# CONFIG_UIO is not set + +# +# TI VLYNQ +# +# CONFIG_STAGING is not set + +# +# File systems +# +# CONFIG_EXT2_FS is not set +CONFIG_EXT3_FS=y +# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set +CONFIG_EXT3_FS_XATTR=y +CONFIG_EXT3_FS_POSIX_ACL=y +CONFIG_EXT3_FS_SECURITY=y +# CONFIG_EXT4_FS is not set +CONFIG_JBD=y +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +CONFIG_FS_POSIX_ACL=y +# CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_BTRFS_FS is not set +# CONFIG_NILFS2_FS is not set +CONFIG_FILE_LOCKING=y +CONFIG_FSNOTIFY=y +CONFIG_DNOTIFY=y +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +CONFIG_QUOTA=y +# CONFIG_QUOTA_NETLINK_INTERFACE is not set +CONFIG_PRINT_QUOTA_WARNING=y +# CONFIG_QFMT_V1 is not set +# CONFIG_QFMT_V2 is not set +CONFIG_QUOTACTL=y +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# Caches +# +# CONFIG_FSCACHE is not set + +# +# CD-ROM/DVD Filesystems +# +CONFIG_ISO9660_FS=m +CONFIG_JOLIET=y +CONFIG_ZISOFS=y +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=m +# CONFIG_MSDOS_FS is not set +CONFIG_VFAT_FS=m +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_KCORE=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set +# CONFIG_MISC_FILESYSTEMS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=m +CONFIG_NFS_V3=y +CONFIG_NFS_V3_ACL=y +# CONFIG_NFS_V4 is not set +# CONFIG_NFSD is not set +CONFIG_LOCKD=m +CONFIG_LOCKD_V4=y +CONFIG_NFS_ACL_SUPPORT=m +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=m +# CONFIG_RPCSEC_GSS_KRB5 is not set +# CONFIG_RPCSEC_GSS_SPKM3 is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="utf-8" +# CONFIG_NLS_CODEPAGE_437 is not set +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set +# CONFIG_NLS_ISO8859_1 is not set +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_UTF8 is not set +# CONFIG_DLM is not set + +# +# Kernel hacking +# +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_PRINTK_TIME=y +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +# CONFIG_MAGIC_SYSRQ is not set +CONFIG_STRIP_ASM_SYMS=y +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_KERNEL is not set +# CONFIG_SLUB_DEBUG_ON is not set +# CONFIG_SLUB_STATS is not set +# CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +CONFIG_SYSCTL_SYSCALL_CHECK=y +CONFIG_TRACING_SUPPORT=y +# CONFIG_FTRACE is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +CONFIG_CMDLINE="" + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +# CONFIG_SECURITY_FILE_CAPABILITIES is not set +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_BLKCIPHER2=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_PCOMP=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +# CONFIG_CRYPTO_GF128MUL is not set +# CONFIG_CRYPTO_NULL is not set +CONFIG_CRYPTO_WORKQUEUE=y +# CONFIG_CRYPTO_CRYPTD is not set +# CONFIG_CRYPTO_AUTHENC is not set +# CONFIG_CRYPTO_TEST is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_SEQIV is not set + +# +# Block modes +# +CONFIG_CRYPTO_CBC=y +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +# CONFIG_CRYPTO_ECB is not set +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# +# CONFIG_CRYPTO_HMAC is not set +# CONFIG_CRYPTO_XCBC is not set +# CONFIG_CRYPTO_VMAC is not set + +# +# Digest +# +# CONFIG_CRYPTO_CRC32C is not set +# CONFIG_CRYPTO_GHASH is not set +# CONFIG_CRYPTO_MD4 is not set +# CONFIG_CRYPTO_MD5 is not set +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +# CONFIG_CRYPTO_SHA1 is not set +# CONFIG_CRYPTO_SHA256 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +# CONFIG_CRYPTO_AES is not set +# CONFIG_CRYPTO_ANUBIS is not set +# CONFIG_CRYPTO_ARC4 is not set +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +# CONFIG_CRYPTO_DES is not set +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TWOFISH is not set + +# +# Compression +# +# CONFIG_CRYPTO_DEFLATE is not set +# CONFIG_CRYPTO_ZLIB is not set +# CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set +CONFIG_CRYPTO_HW=y +# CONFIG_CRYPTO_DEV_HIFN_795X is not set +# CONFIG_BINARY_PRINTF is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_GENERIC_FIND_LAST_BIT=y +# CONFIG_CRC_CCITT is not set +# CONFIG_CRC16 is not set +CONFIG_CRC_T10DIF=y +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +CONFIG_AUDIT_GENERIC=y +CONFIG_ZLIB_INFLATE=m +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y +CONFIG_NLATTR=y -- 1.6.2.1 From ralf@linux-mips.org Fri Nov 6 14:15:18 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 06 Nov 2009 14:15:23 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:58007 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-FAIL) by ftp.linux-mips.org with ESMTP id S1492785AbZKFNMj (ORCPT ); Fri, 6 Nov 2009 14:12:39 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id nA6DE7Ag011045; Fri, 6 Nov 2009 14:14:07 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id nA6DE5Jp011041; Fri, 6 Nov 2009 14:14:05 +0100 Date: Fri, 6 Nov 2009 14:14:05 +0100 From: Ralf Baechle To: Wu Zhangjin Cc: linux-mips@linux-mips.org Subject: Re: [PATCH -queue 1/2] [loongson] add basic loongson-2f support Message-ID: <20091106131405.GC31392@linux-mips.org> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.19 (2009-01-05) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24730 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Fri, Nov 06, 2009 at 06:45:05PM +0800, Wu Zhangjin wrote: > Loongson2F has built-in DDR2 and PCIX controller. The PCIX controller > have a similar programming interface with FPGA northbridge used in > Loongson2E. > > The main differences between loongson-2e and loongson-2f include: > > 1. loongson-2f has an extra address windows configuration module, which > can be used to map CPU address space to DDR or PCI address space, or map > the PCI-DMA address space to DDR or LIO address space. > > 2. loongson-2f support 8 levels of software configurable cpu frequency, > which can be configured via a register(LOONGSON_CHIPCFG0). the coming > cpufreq and standby support are based on this feature. > > herein, the module and the corresponding operations are abstracted to > loongson.h. > > besides, the other loongson2f-specific source code are added here, > including gcc 4.4 support, pci memory space, pci io space, dma address. Queued for 2.6.33. Thanks! Ralf From ralf@linux-mips.org Fri Nov 6 14:15:41 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 06 Nov 2009 14:15:45 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:58042 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-FAIL) by ftp.linux-mips.org with ESMTP id S1492747AbZKFNMr (ORCPT ); Fri, 6 Nov 2009 14:12:47 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id nA6DEHY3011062; Fri, 6 Nov 2009 14:14:17 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id nA6DEH3O011061; Fri, 6 Nov 2009 14:14:17 +0100 Date: Fri, 6 Nov 2009 14:14:17 +0100 From: Ralf Baechle To: Wu Zhangjin Cc: linux-mips@linux-mips.org Subject: Re: [PATCH -queue 2/2] [loongson] oprofile: avoid do_IRQ for perfcounter when the interrupt is from bonito Message-ID: <20091106131417.GD31392@linux-mips.org> References: <578fdf2cd4a665bb8b56635e2ba7384ec9059ff8.1257504242.git.wuzhangjin@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <578fdf2cd4a665bb8b56635e2ba7384ec9059ff8.1257504242.git.wuzhangjin@gmail.com> User-Agent: Mutt/1.5.19 (2009-01-05) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24731 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Fri, Nov 06, 2009 at 06:45:06PM +0800, Wu Zhangjin wrote: > In loongson2f, the IP6 is shared by bonito and perfcounter, we need to > avoid do_IRQ for perfcounter when the interrupt is from bonito. This > patch does it. > > Signed-off-by: Wu Zhangjin Queued for 2.6.33. Thanks! Ralf From anemo@mba.ocn.ne.jp Fri Nov 6 17:13:45 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 06 Nov 2009 17:13:51 +0100 (CET) Received: from mba.ocn.ne.jp ([122.28.14.163]:55080 "HELO smtp.mba.ocn.ne.jp" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with SMTP id S1492939AbZKFQNp (ORCPT ); Fri, 6 Nov 2009 17:13:45 +0100 Received: from localhost (p7248-ipad211funabasi.chiba.ocn.ne.jp [58.91.163.248]) by smtp.mba.ocn.ne.jp (Postfix) with ESMTP id 48E2F6ED6 for ; Sat, 7 Nov 2009 01:13:39 +0900 (JST) Date: Sat, 07 Nov 2009 01:08:39 +0900 (JST) Message-Id: <20091107.010839.246840249.anemo@mba.ocn.ne.jp> To: linux-mips@linux-mips.org Subject: COMMAND_LINE_SIZE and CONFIG_FRAME_WARN From: Atsushi Nemoto X-Fingerprint: 6ACA 1623 39BD 9A94 9B1A B746 CA77 FE94 2874 D52F X-Pgp-Public-Key: http://wwwkeys.pgp.net/pks/lookup?op=get&search=0x2874D52F X-Mailer: Mew version 5.2 on Emacs 22.2 / Mule 5.0 (SAKAKI) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24732 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anemo@mba.ocn.ne.jp Precedence: bulk X-list: linux-mips Recently COMMAND_LINE_SIZE (CL_SIZE) was extended to 4096 from 512. (commit 22242681 "MIPS: Extend COMMAND_LINE_SIZE") This cause warning if something like buf[CL_SIZE] was declared as a local variable, for example in prom_init_cmdline() on some platforms. And since many Makefiles in arch/mips enables -Werror, this cause build failure. How can we avoid this error? - do not use local array? (but dynamic allocation cannot be used in such an early stage. static array?) - are there any way to disable -Wframe-larger-than for the file or function? - make COMMAND_LINE_SIZE customizable? - use non default CONFIG_FRAME_WARN? Any comments or suggestions? --- Atsushi Nemoto From anemo@mba.ocn.ne.jp Fri Nov 6 17:15:29 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 06 Nov 2009 17:15:36 +0100 (CET) Received: from mba.ocn.ne.jp ([122.28.14.163]:61768 "HELO smtp.mba.ocn.ne.jp" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with SMTP id S1492939AbZKFQP3 (ORCPT ); Fri, 6 Nov 2009 17:15:29 +0100 Received: from localhost (p7248-ipad211funabasi.chiba.ocn.ne.jp [58.91.163.248]) by smtp.mba.ocn.ne.jp (Postfix) with ESMTP id 77BC86ED1 for ; Sat, 7 Nov 2009 01:15:26 +0900 (JST) Date: Sat, 07 Nov 2009 01:10:26 +0900 (JST) Message-Id: <20091107.011026.152514775.anemo@mba.ocn.ne.jp> To: linux-mips@linux-mips.org Subject: Re: COMMAND_LINE_SIZE and CONFIG_FRAME_WARN From: Atsushi Nemoto In-Reply-To: <20091107.010839.246840249.anemo@mba.ocn.ne.jp> References: <20091107.010839.246840249.anemo@mba.ocn.ne.jp> X-Fingerprint: 6ACA 1623 39BD 9A94 9B1A B746 CA77 FE94 2874 D52F X-Pgp-Public-Key: http://wwwkeys.pgp.net/pks/lookup?op=get&search=0x2874D52F X-Mailer: Mew version 5.2 on Emacs 22.2 / Mule 5.0 (SAKAKI) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24733 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anemo@mba.ocn.ne.jp Precedence: bulk X-list: linux-mips On Sat, 07 Nov 2009 01:08:39 +0900 (JST), Atsushi Nemoto wrote: > Recently COMMAND_LINE_SIZE (CL_SIZE) was extended to 4096 from 512. > (commit 22242681 "MIPS: Extend COMMAND_LINE_SIZE") Excuse me, old COMMAND_LINE_SIZE value was 256, not 512. --- Atsushi Nemoto From wuzhangjin@gmail.com Fri Nov 6 17:18:49 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 06 Nov 2009 17:18:56 +0100 (CET) Received: from ey-out-1920.google.com ([74.125.78.148]:50098 "EHLO ey-out-1920.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492939AbZKFQSt (ORCPT ); Fri, 6 Nov 2009 17:18:49 +0100 Received: by ey-out-1920.google.com with SMTP id 26so252385eyw.52 for ; Fri, 06 Nov 2009 08:18:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:subject:from:reply-to:to:cc :in-reply-to:references:content-type:organization:date:message-id :mime-version:x-mailer:content-transfer-encoding; bh=QqzD6zHmfa1/WAXJ/NKaDumw9p2kslWA5L7MKQURKZ0=; b=YNZimz0ang+4LoHhxUKHp3/SaAaodzYwwN95OB/iIEAoV+aQFPPC1aIZQ6vBWLa8CJ i7jjNVfr7K8ikNjIVxmBDYod61Y5h2WbA44ObgEyaGTjODYOMmIor79WOjshbwXo6N+Q lukiKSawso8tx2Q89RJ9xddUBL9gNDViUkRVg= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=subject:from:reply-to:to:cc:in-reply-to:references:content-type :organization:date:message-id:mime-version:x-mailer :content-transfer-encoding; b=tYE1I+ymgC//CMps86AHthFPMw1ZhspHlDKt1u4jmSs55MEM6/0Y+2gbzcZjEJ4Z5w x1zd+szhK0INfmPaSU7tIRDMS2Q+V8Kb2ts8B5AlfONCo0ZKErX74zjFaNtGWMdkkD63 I3ySLZ+JnxbxMRSgLnKE/GWDNhPhvYiJh0qh0= Received: by 10.216.86.83 with SMTP id v61mr843927wee.80.1257524327540; Fri, 06 Nov 2009 08:18:47 -0800 (PST) Received: from ?172.16.2.101? ([222.92.8.142]) by mx.google.com with ESMTPS id q9sm386029gve.15.2009.11.06.08.18.44 (version=TLSv1/SSLv3 cipher=RC4-MD5); Fri, 06 Nov 2009 08:18:46 -0800 (PST) Subject: Re: COMMAND_LINE_SIZE and CONFIG_FRAME_WARN From: Wu Zhangjin Reply-To: wuzhangjin@gmail.com To: Atsushi Nemoto Cc: linux-mips@linux-mips.org In-Reply-To: <20091107.010839.246840249.anemo@mba.ocn.ne.jp> References: <20091107.010839.246840249.anemo@mba.ocn.ne.jp> Content-Type: text/plain; charset="UTF-8" Organization: DSLab, Lanzhou University, China Date: Sat, 07 Nov 2009 00:18:46 +0800 Message-ID: <1257524326.8766.8.camel@falcon.domain.org> Mime-Version: 1.0 X-Mailer: Evolution 2.28.1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24734 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips On Sat, 2009-11-07 at 01:08 +0900, Atsushi Nemoto wrote: > Recently COMMAND_LINE_SIZE (CL_SIZE) was extended to 4096 from 512. > (commit 22242681 "MIPS: Extend COMMAND_LINE_SIZE") > > This cause warning if something like buf[CL_SIZE] was declared as a > local variable, for example in prom_init_cmdline() on some platforms. > > And since many Makefiles in arch/mips enables -Werror, this cause > build failure. > > How can we avoid this error? > > - do not use local array? (but dynamic allocation cannot be used in > such an early stage. static array?) > - are there any way to disable -Wframe-larger-than for the file or function? > - make COMMAND_LINE_SIZE customizable? > - use non default CONFIG_FRAME_WARN? > > Any comments or suggestions? does "static" helps this problem? Regards, Wu Zhangjin From dmitri.vorobiev@gmail.com Fri Nov 6 17:22:16 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 06 Nov 2009 17:22:23 +0100 (CET) Received: from mail-fx0-f211.google.com ([209.85.220.211]:39101 "EHLO mail-fx0-f211.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492939AbZKFQWQ (ORCPT ); Fri, 6 Nov 2009 17:22:16 +0100 Received: by fxm3 with SMTP id 3so278496fxm.24 for ; Fri, 06 Nov 2009 08:22:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:in-reply-to:references :date:message-id:subject:from:to:cc:content-type; bh=YeQAqqaOaKnkNMfC0SaJexwgro96aJYQuuHbPxGXw98=; b=V68LcFI2VzyqCaFf49uOMbBGkAm3Ft9wWFBLVWSejEzvuqCNin3fzffGKtoLwkcivd +b7CyHX4yq9oJUusoZyoOWyVl9nDLDg1WpaD3egvoBx9fZ3DRymGTcyInVnPbsORZ3Ib hBgrGkMzBGK04kOIQTsccqTpNJ6QA5XMtxWHs= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type; b=O46i4MdQ3ypgzREBfS7yeKa86OOaMabXJQC8WHWzW5O24vH4X4payrMozTaioq9tGQ +MXQyEbx8wnptqEah02XlFI+mcgVWVVvLRg6XWl1j/PsDcuaBjLcjRTSxhz4WHBuJskX x8mR6kdJq6GEw/0QjArilx6g2tzmHOBCuJUVg= MIME-Version: 1.0 Received: by 10.223.164.75 with SMTP id d11mr696322fay.17.1257524529753; Fri, 06 Nov 2009 08:22:09 -0800 (PST) In-Reply-To: <20091107.010839.246840249.anemo@mba.ocn.ne.jp> References: <20091107.010839.246840249.anemo@mba.ocn.ne.jp> Date: Fri, 6 Nov 2009 18:22:09 +0200 Message-ID: <90edad820911060822g40233a8ft28001d68186b989e@mail.gmail.com> Subject: Re: COMMAND_LINE_SIZE and CONFIG_FRAME_WARN From: Dmitri Vorobiev To: Atsushi Nemoto Cc: linux-mips@linux-mips.org Content-Type: text/plain; charset=ISO-8859-1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24735 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dmitri.vorobiev@gmail.com Precedence: bulk X-list: linux-mips On Fri, Nov 6, 2009 at 6:08 PM, Atsushi Nemoto wrote: > Recently COMMAND_LINE_SIZE (CL_SIZE) was extended to 4096 from 512. > (commit 22242681 "MIPS: Extend COMMAND_LINE_SIZE") > > This cause warning if something like buf[CL_SIZE] was declared as a > local variable, for example in prom_init_cmdline() on some platforms. > > And since many Makefiles in arch/mips enables -Werror, this cause > build failure. > > How can we avoid this error? > > - do not use local array? (but dynamic allocation cannot be used in > such an early stage. static array?) Maybe a static array marked with __initdata? Dmitri From macro@linux-mips.org Fri Nov 6 17:34:13 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 06 Nov 2009 17:34:16 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:53493 "EHLO localhost.localdomain" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492939AbZKFQeN (ORCPT ); Fri, 6 Nov 2009 17:34:13 +0100 Date: Fri, 6 Nov 2009 16:34:13 +0000 (GMT) From: "Maciej W. Rozycki" To: Atsushi Nemoto cc: linux-mips@linux-mips.org Subject: Re: COMMAND_LINE_SIZE and CONFIG_FRAME_WARN In-Reply-To: <20091107.010839.246840249.anemo@mba.ocn.ne.jp> Message-ID: References: <20091107.010839.246840249.anemo@mba.ocn.ne.jp> User-Agent: Alpine 2.00 (LFD 1167 2008-08-23) MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24736 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: macro@linux-mips.org Precedence: bulk X-list: linux-mips On Sat, 7 Nov 2009, Atsushi Nemoto wrote: > Recently COMMAND_LINE_SIZE (CL_SIZE) was extended to 4096 from 512. > (commit 22242681 "MIPS: Extend COMMAND_LINE_SIZE") > > This cause warning if something like buf[CL_SIZE] was declared as a > local variable, for example in prom_init_cmdline() on some platforms. > > And since many Makefiles in arch/mips enables -Werror, this cause > build failure. > > How can we avoid this error? > > - do not use local array? (but dynamic allocation cannot be used in > such an early stage. static array?) > - are there any way to disable -Wframe-larger-than for the file or function? > - make COMMAND_LINE_SIZE customizable? > - use non default CONFIG_FRAME_WARN? > > Any comments or suggestions? Use static storage and mark it initdata? You can certainly override -Wframe-larger-than in per-object CFLAGS too. You might also be able to use __builtin_alloca(), but this sounds like a shaky ground. ;) Maciej From dmitri.vorobiev@gmail.com Fri Nov 6 17:34:33 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 06 Nov 2009 17:34:42 +0100 (CET) Received: from mail-bw0-f221.google.com ([209.85.218.221]:41502 "EHLO mail-bw0-f221.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492983AbZKFQeS (ORCPT ); Fri, 6 Nov 2009 17:34:18 +0100 Received: by bwz21 with SMTP id 21so1344824bwz.24 for ; Fri, 06 Nov 2009 08:34:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:in-reply-to:references :date:message-id:subject:from:to:cc:content-type; bh=hWZnce3LBdQP1RP3aDxEklftz7SjDoJsY3wIUCxx7rU=; b=Ag1d4ldhtVVT2JITdDR9KgOCOS/KHoQQFKueiXzbq6WbLYV5yTbWGQ/mEvAa8ovGKD fEqByScqXVNFlQ2Bwo7tJibzuryOJromITfqeBKO6VxjaSS4cO5LL8WEU7XgwT7vxUOR CsZP/O0WQmxbnRU9N0jjvMy3D2720T6+8Dl64= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type; b=BloOUPPl8DVGzVmN3lIL8pKPsWX4xaGRPNV6SVI3b8jfVwqeftg2uX0WJ4kOAQrbb+ AGxE8b8O7nXGHPq4kmvnrdjPfDemPGLI9qhByFV8ejcqAVZL7DDzkmuRMvwRoEFCNikp mxBJ5h9nB0cuVvG8D8+40tjIl1zIyWo+nVv6Q= MIME-Version: 1.0 Received: by 10.223.14.22 with SMTP id e22mr711491faa.42.1257525250650; Fri, 06 Nov 2009 08:34:10 -0800 (PST) In-Reply-To: <90edad820911060822g40233a8ft28001d68186b989e@mail.gmail.com> References: <20091107.010839.246840249.anemo@mba.ocn.ne.jp> <90edad820911060822g40233a8ft28001d68186b989e@mail.gmail.com> Date: Fri, 6 Nov 2009 18:34:10 +0200 Message-ID: <90edad820911060834t5c14aa30t847c3b75bf7e36e@mail.gmail.com> Subject: Re: COMMAND_LINE_SIZE and CONFIG_FRAME_WARN From: Dmitri Vorobiev To: Atsushi Nemoto Cc: linux-mips@linux-mips.org Content-Type: text/plain; charset=ISO-8859-1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24737 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dmitri.vorobiev@gmail.com Precedence: bulk X-list: linux-mips On Fri, Nov 6, 2009 at 6:22 PM, Dmitri Vorobiev wrote: > On Fri, Nov 6, 2009 at 6:08 PM, Atsushi Nemoto wrote: >> Recently COMMAND_LINE_SIZE (CL_SIZE) was extended to 4096 from 512. >> (commit 22242681 "MIPS: Extend COMMAND_LINE_SIZE") >> >> This cause warning if something like buf[CL_SIZE] was declared as a >> local variable, for example in prom_init_cmdline() on some platforms. >> >> And since many Makefiles in arch/mips enables -Werror, this cause >> build failure. >> >> How can we avoid this error? >> >> - do not use local array? (but dynamic allocation cannot be used in >> such an early stage. static array?) > > Maybe a static array marked with __initdata? Also, I just thought that maybe it's possible to use a c99 variable-length array here? Like this: int n = COMMAND_LINE_SIZE; char buf[n]; This way, we don't put yet another variable in the .init.data section, unlike with the static array solution. However, this is totally untested, just a thought... Dmitri > > Dmitri > From dmitri.vorobiev@gmail.com Fri Nov 6 17:44:21 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 06 Nov 2009 17:44:28 +0100 (CET) Received: from mail-fx0-f211.google.com ([209.85.220.211]:50775 "EHLO mail-fx0-f211.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492995AbZKFQoV convert rfc822-to-8bit (ORCPT ); Fri, 6 Nov 2009 17:44:21 +0100 Received: by fxm3 with SMTP id 3so286089fxm.24 for ; Fri, 06 Nov 2009 08:44:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:in-reply-to:references :date:message-id:subject:from:to:cc:content-type :content-transfer-encoding; bh=ViQvux9M1cFrU4WYSZSmelpZp6Fuv0EVhsspoBrcGuQ=; b=vLPaUlcUmsULmgSiqoaMD4Y1TMjXOPF/xcF6AXRvqSHm1FnHjaSVKWfE2tDDwh7uxZ AdC5Ka0GUr9zYQEi7qTnzz1VCbfYcfw6o/NLimrYzR7m42Uncmj9kiJdIyDnoj/kF9lU mpgHxykxOwcdwZbff2CthxMeBfVwmFfHz2VBY= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type:content-transfer-encoding; b=UrQRpQhExG+p7eursXUuEZDxBAHQoPrr6Kk4mV3MJxH933caJZ4qfTmA5ady5Y7x29 ChEYWpmqSHO8EKe+wltB32JmUb+Po182bkwGcPfyQkdgoJdGAifOHyD2YTBr+q6Vlw0J niTdQjmuD0h3lqt/B9Ei0h37BRwXkfy6j2UkQ= MIME-Version: 1.0 Received: by 10.223.21.3 with SMTP id h3mr662205fab.39.1257525855218; Fri, 06 Nov 2009 08:44:15 -0800 (PST) In-Reply-To: <90edad820911060834t5c14aa30t847c3b75bf7e36e@mail.gmail.com> References: <20091107.010839.246840249.anemo@mba.ocn.ne.jp> <90edad820911060822g40233a8ft28001d68186b989e@mail.gmail.com> <90edad820911060834t5c14aa30t847c3b75bf7e36e@mail.gmail.com> Date: Fri, 6 Nov 2009 18:44:15 +0200 Message-ID: <90edad820911060844n14f12301jbaa63c2d62d23f92@mail.gmail.com> Subject: Re: COMMAND_LINE_SIZE and CONFIG_FRAME_WARN From: Dmitri Vorobiev To: Atsushi Nemoto Cc: linux-mips@linux-mips.org Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 8BIT Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24738 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dmitri.vorobiev@gmail.com Precedence: bulk X-list: linux-mips On Fri, Nov 6, 2009 at 6:34 PM, Dmitri Vorobiev wrote: > On Fri, Nov 6, 2009 at 6:22 PM, Dmitri Vorobiev > wrote: >> On Fri, Nov 6, 2009 at 6:08 PM, Atsushi Nemoto wrote: >>> Recently COMMAND_LINE_SIZE (CL_SIZE) was extended to 4096 from 512. >>> (commit 22242681 "MIPS: Extend COMMAND_LINE_SIZE") >>> >>> This cause warning if something like buf[CL_SIZE] was declared as a >>> local variable, for example in prom_init_cmdline() on some platforms. >>> >>> And since many Makefiles in arch/mips enables -Werror, this cause >>> build failure. >>> >>> How can we avoid this error? >>> >>> - do not use local array? (but dynamic allocation cannot be used in >>> such an early stage. static array?) >> >> Maybe a static array marked with __initdata? > > Also, I just thought that maybe it's possible to use a c99 > variable-length array here? Like this: > > int n = COMMAND_LINE_SIZE; > char buf[n]; > > This way, we don't put yet another variable in the .init.data section, > unlike with the static array solution. > > However, this is totally untested, just a thought... Just tried the variable-length array option, proves to be working: dmvo@cipher:/tmp$ cat c.c f() { char buf[4096]; } dmvo@cipher:/tmp$ cc -c -Wframe-larger-than=1024 c.c c.c: In function ‘f’: c.c:4: warning: the frame size of 4112 bytes is larger than 1024 bytes dmvo@cipher:/tmp$ cat d.c f() { int n = 4096; char buf1[n]; } dmvo@cipher:/tmp$ cc -c -Wframe-larger-than=1024 d.c Dmitri From David.Daney@caviumnetworks.com Fri Nov 6 17:53:16 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 06 Nov 2009 17:53:22 +0100 (CET) Received: from mail3.caviumnetworks.com ([12.108.191.235]:17638 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492995AbZKFQxQ (ORCPT ); Fri, 6 Nov 2009 17:53:16 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,5,4,7535) id ; Fri, 06 Nov 2009 08:53:01 -0800 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Fri, 6 Nov 2009 08:44:30 -0800 Received: from dd1.caveonetworks.com ([12.108.191.236]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Fri, 6 Nov 2009 08:44:30 -0800 Message-ID: <4AF4526B.3020502@caviumnetworks.com> Date: Fri, 06 Nov 2009 08:44:27 -0800 From: David Daney User-Agent: Thunderbird 2.0.0.21 (X11/20090320) MIME-Version: 1.0 To: Dmitri Vorobiev CC: Atsushi Nemoto , linux-mips@linux-mips.org Subject: Re: COMMAND_LINE_SIZE and CONFIG_FRAME_WARN References: <20091107.010839.246840249.anemo@mba.ocn.ne.jp> <90edad820911060822g40233a8ft28001d68186b989e@mail.gmail.com> <90edad820911060834t5c14aa30t847c3b75bf7e36e@mail.gmail.com> In-Reply-To: <90edad820911060834t5c14aa30t847c3b75bf7e36e@mail.gmail.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 06 Nov 2009 16:44:30.0023 (UTC) FILETIME=[6907AD70:01CA5F00] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24739 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Dmitri Vorobiev wrote: > On Fri, Nov 6, 2009 at 6:22 PM, Dmitri Vorobiev > wrote: >> On Fri, Nov 6, 2009 at 6:08 PM, Atsushi Nemoto wrote: >>> Recently COMMAND_LINE_SIZE (CL_SIZE) was extended to 4096 from 512. >>> (commit 22242681 "MIPS: Extend COMMAND_LINE_SIZE") >>> >>> This cause warning if something like buf[CL_SIZE] was declared as a >>> local variable, for example in prom_init_cmdline() on some platforms. >>> >>> And since many Makefiles in arch/mips enables -Werror, this cause >>> build failure. >>> >>> How can we avoid this error? >>> >>> - do not use local array? (but dynamic allocation cannot be used in >>> such an early stage. static array?) >> Maybe a static array marked with __initdata? > > Also, I just thought that maybe it's possible to use a c99 > variable-length array here? Like this: > > int n = COMMAND_LINE_SIZE; > char buf[n]; > > This way, we don't put yet another variable in the .init.data section, > unlike with the static array solution. > > However, this is totally untested, just a thought... > It depends on your concerns. You are still using 4096 bytes of stack, but you are trying to trick the compiler into not warning. If you think the warning is bogus, you should remove it for all code, not just this file. If you think the warning is valid, then you should fix the code so that it doesn't use as much stack space. David Daney From dmitri.vorobiev@gmail.com Fri Nov 6 18:08:00 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 06 Nov 2009 18:08:07 +0100 (CET) Received: from mail-bw0-f221.google.com ([209.85.218.221]:62683 "EHLO mail-bw0-f221.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1493040AbZKFRIA (ORCPT ); Fri, 6 Nov 2009 18:08:00 +0100 Received: by bwz21 with SMTP id 21so1379725bwz.24 for ; Fri, 06 Nov 2009 09:07:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:in-reply-to:references :date:message-id:subject:from:to:cc:content-type; bh=OqlBHZmp/lTAsvFMnBVr+2eArn1No3T6bU0XrKpTjC8=; b=S8HdLXn80eD1wmtcD/mKYzzNmawjRMkoUkNnKQnq1k/nlhOnaRYWOTsyg652PknksV OgOgG0Xsgkv2JGkzjBpk6VbW/B27I2IqT0AX6jBtLkskWo+x82QSoW8drOYEkXsUV6sh gjO7x1+GVG2sUrliEoZMz4ZHGi0AIjEDLHeOs= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type; b=wJXZy2gsw2CioFaIVTbdJfAVlE/QI5JgT3QjrQfD7+nWtb0vbglmK5GuF5DilyosXe Tmci/ixdlswfQje6WXrMDHwifxZB1hxduRubhi+sCYviW6KDWTaukMLoU/UVjLORmjHw fJPgb1N0yHXTgaVQCJxy5VlVUwtfb1j9KLecs= MIME-Version: 1.0 Received: by 10.223.14.22 with SMTP id e22mr717770faa.42.1257527274318; Fri, 06 Nov 2009 09:07:54 -0800 (PST) In-Reply-To: <4AF4526B.3020502@caviumnetworks.com> References: <20091107.010839.246840249.anemo@mba.ocn.ne.jp> <90edad820911060822g40233a8ft28001d68186b989e@mail.gmail.com> <90edad820911060834t5c14aa30t847c3b75bf7e36e@mail.gmail.com> <4AF4526B.3020502@caviumnetworks.com> Date: Fri, 6 Nov 2009 19:07:54 +0200 Message-ID: <90edad820911060907j4a605167xfe1ebdf0dcf7b635@mail.gmail.com> Subject: Re: COMMAND_LINE_SIZE and CONFIG_FRAME_WARN From: Dmitri Vorobiev To: David Daney Cc: Atsushi Nemoto , linux-mips@linux-mips.org Content-Type: text/plain; charset=ISO-8859-1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24740 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dmitri.vorobiev@gmail.com Precedence: bulk X-list: linux-mips On Fri, Nov 6, 2009 at 6:44 PM, David Daney wrote: > Dmitri Vorobiev wrote: >> >> On Fri, Nov 6, 2009 at 6:22 PM, Dmitri Vorobiev >> wrote: >>> >>> On Fri, Nov 6, 2009 at 6:08 PM, Atsushi Nemoto >>> wrote: >>>> >>>> Recently COMMAND_LINE_SIZE (CL_SIZE) was extended to 4096 from 512. >>>> (commit 22242681 "MIPS: Extend COMMAND_LINE_SIZE") >>>> >>>> This cause warning if something like buf[CL_SIZE] was declared as a >>>> local variable, for example in prom_init_cmdline() on some platforms. >>>> >>>> And since many Makefiles in arch/mips enables -Werror, this cause >>>> build failure. >>>> >>>> How can we avoid this error? >>>> >>>> - do not use local array? (but dynamic allocation cannot be used in >>>> such an early stage. static array?) >>> >>> Maybe a static array marked with __initdata? >> >> Also, I just thought that maybe it's possible to use a c99 >> variable-length array here? Like this: >> >> int n = COMMAND_LINE_SIZE; >> char buf[n]; >> >> This way, we don't put yet another variable in the .init.data section, >> unlike with the static array solution. >> >> However, this is totally untested, just a thought... >> > > It depends on your concerns. You are still using 4096 bytes of stack, but > you are trying to trick the compiler into not warning. > > If you think the warning is bogus, you should remove it for all code, not > just this file. If you think the warning is valid, then you should fix the > code so that it doesn't use as much stack space. Frankly, I don't think that the warning is bogus, especially if we're talking about the case of the 4K page and 32-bit kernel, and I started thinking htat probably the static array solution would be the safest bet here. Dmitri From macro@linux-mips.org Fri Nov 6 18:09:44 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 06 Nov 2009 18:09:47 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:58088 "EHLO localhost.localdomain" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1493040AbZKFRJo (ORCPT ); Fri, 6 Nov 2009 18:09:44 +0100 Date: Fri, 6 Nov 2009 17:09:44 +0000 (GMT) From: "Maciej W. Rozycki" To: David Daney cc: Dmitri Vorobiev , Atsushi Nemoto , linux-mips@linux-mips.org Subject: Re: COMMAND_LINE_SIZE and CONFIG_FRAME_WARN In-Reply-To: <4AF4526B.3020502@caviumnetworks.com> Message-ID: References: <20091107.010839.246840249.anemo@mba.ocn.ne.jp> <90edad820911060822g40233a8ft28001d68186b989e@mail.gmail.com> <90edad820911060834t5c14aa30t847c3b75bf7e36e@mail.gmail.com> <4AF4526B.3020502@caviumnetworks.com> User-Agent: Alpine 2.00 (LFD 1167 2008-08-23) MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24741 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: macro@linux-mips.org Precedence: bulk X-list: linux-mips On Fri, 6 Nov 2009, David Daney wrote: > It depends on your concerns. You are still using 4096 bytes of stack, > but you are trying to trick the compiler into not warning. > > If you think the warning is bogus, you should remove it for all code, > not just this file. If you think the warning is valid, then you should > fix the code so that it doesn't use as much stack space. My understanding is the option is for detecting unintended excessive use of stack space. If a place is known to require more space, it is justified and harmless (such as in an early bootstrap call), then I see no reason to forbid it or to imply it should be allowed globally then. Note that stack space of 4096 bytes required by a single call is functionally equivalent to four nested calls requiring 1024 bytes each, so from the practical point of view they are equivalent and during kernel startup we may know that nesting is less extensive than, say, when a syscall or an interrupt handler is being executed, where such stack consumption would be of much more concern. Maciej From macro@linux-mips.org Fri Nov 6 18:16:18 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 06 Nov 2009 18:16:21 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:49611 "EHLO localhost.localdomain" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492995AbZKFRQS (ORCPT ); Fri, 6 Nov 2009 18:16:18 +0100 Date: Fri, 6 Nov 2009 17:16:18 +0000 (GMT) From: "Maciej W. Rozycki" To: Dmitri Vorobiev cc: David Daney , Atsushi Nemoto , linux-mips@linux-mips.org Subject: Re: COMMAND_LINE_SIZE and CONFIG_FRAME_WARN In-Reply-To: <90edad820911060907j4a605167xfe1ebdf0dcf7b635@mail.gmail.com> Message-ID: References: <20091107.010839.246840249.anemo@mba.ocn.ne.jp> <90edad820911060822g40233a8ft28001d68186b989e@mail.gmail.com> <90edad820911060834t5c14aa30t847c3b75bf7e36e@mail.gmail.com> <4AF4526B.3020502@caviumnetworks.com> <90edad820911060907j4a605167xfe1ebdf0dcf7b635@mail.gmail.com> User-Agent: Alpine 2.00 (LFD 1167 2008-08-23) MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24742 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: macro@linux-mips.org Precedence: bulk X-list: linux-mips On Fri, 6 Nov 2009, Dmitri Vorobiev wrote: > > It depends on your concerns. You are still using 4096 bytes of stack, but > > you are trying to trick the compiler into not warning. > > > > If you think the warning is bogus, you should remove it for all code, not > > just this file. If you think the warning is valid, then you should fix the > > code so that it doesn't use as much stack space. > > Frankly, I don't think that the warning is bogus, especially if we're > talking about the case of the 4K page and 32-bit kernel, and I started > thinking htat probably the static array solution would be the safest > bet here. KSEG space is not paged, so who cares about the page size? You're not making additional stack page allocations, although you can overflow the space available at some point (but that's avoided if you know a priori your backtrace is not going to be deep). Static allocation has its drawbacks, for example it takes storage space (if it's initialised data) or memory space (if it's BSS) indefinitely. Maciej From dmitri.vorobiev@gmail.com Fri Nov 6 18:23:31 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 06 Nov 2009 18:23:38 +0100 (CET) Received: from mail-bw0-f221.google.com ([209.85.218.221]:62885 "EHLO mail-bw0-f221.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S2097301AbZKFRXb (ORCPT ); Fri, 6 Nov 2009 18:23:31 +0100 Received: by bwz21 with SMTP id 21so1395393bwz.24 for ; Fri, 06 Nov 2009 09:23:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:in-reply-to:references :date:message-id:subject:from:to:cc:content-type; bh=EnjWM7XUEkO9VU3J88853Tedx7TALi04AqNuXldGo+0=; b=EaRgf1F25x5emyj7bZV8dKxaavJ9InxBOuSi5Q0S0tVrq4t8Qo1KOZBl7o+jD2c0H2 2aGd8eX+w73YXdp5ezCu7XsgOYpZRlmOJAMvAuc57+DtE6C5QIDjXGFvd4VMcOA2zAmA ZHPbEtt+8iPDhzigiZDy1fqI0pFcOgpWI8wk8= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type; b=mxAQerFLrsfP/QsvOFgoC+j5lK+TwibUVN5SxymCV2yViPqOLceh0GH6gWuz40Hvnt Ibv68PTjv/HCb8gjqCbXDrF+wqBvkzj79G1+5yZ5rZoMrRp9r7LBsMosecXY5A1JCjhH alxY4ZeoZT1W+me4mNkgKYM+XdumlQXHPhYss= MIME-Version: 1.0 Received: by 10.223.6.9 with SMTP id 9mr665718fax.84.1257528205172; Fri, 06 Nov 2009 09:23:25 -0800 (PST) In-Reply-To: References: <20091107.010839.246840249.anemo@mba.ocn.ne.jp> <90edad820911060822g40233a8ft28001d68186b989e@mail.gmail.com> <90edad820911060834t5c14aa30t847c3b75bf7e36e@mail.gmail.com> <4AF4526B.3020502@caviumnetworks.com> <90edad820911060907j4a605167xfe1ebdf0dcf7b635@mail.gmail.com> Date: Fri, 6 Nov 2009 19:23:25 +0200 Message-ID: <90edad820911060923w6cd59c5dh57d123b6bc9d4219@mail.gmail.com> Subject: Re: COMMAND_LINE_SIZE and CONFIG_FRAME_WARN From: Dmitri Vorobiev To: "Maciej W. Rozycki" Cc: David Daney , Atsushi Nemoto , linux-mips@linux-mips.org Content-Type: text/plain; charset=ISO-8859-1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24743 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dmitri.vorobiev@gmail.com Precedence: bulk X-list: linux-mips On Fri, Nov 6, 2009 at 7:16 PM, Maciej W. Rozycki wrote: > On Fri, 6 Nov 2009, Dmitri Vorobiev wrote: > >> > It depends on your concerns. You are still using 4096 bytes of stack, but >> > you are trying to trick the compiler into not warning. >> > >> > If you think the warning is bogus, you should remove it for all code, not >> > just this file. If you think the warning is valid, then you should fix the >> > code so that it doesn't use as much stack space. >> >> Frankly, I don't think that the warning is bogus, especially if we're >> talking about the case of the 4K page and 32-bit kernel, and I started >> thinking htat probably the static array solution would be the safest >> bet here. > > KSEG space is not paged, so who cares about the page size? You're not > making additional stack page allocations, although you can overflow the > space available at some point (but that's avoided if you know a priori > your backtrace is not going to be deep). Static allocation has its > drawbacks, for example it takes storage space (if it's initialised data) > or memory space (if it's BSS) indefinitely. Thanks for the explanation. Then a variable-size array, I guess. Dmitri > > Maciej > From macro@linux-mips.org Fri Nov 6 18:30:53 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 06 Nov 2009 18:30:56 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:57368 "EHLO localhost.localdomain" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492866AbZKFRax (ORCPT ); Fri, 6 Nov 2009 18:30:53 +0100 Date: Fri, 6 Nov 2009 17:30:53 +0000 (GMT) From: "Maciej W. Rozycki" To: Dmitri Vorobiev cc: David Daney , Atsushi Nemoto , linux-mips@linux-mips.org Subject: Re: COMMAND_LINE_SIZE and CONFIG_FRAME_WARN In-Reply-To: <90edad820911060923w6cd59c5dh57d123b6bc9d4219@mail.gmail.com> Message-ID: References: <20091107.010839.246840249.anemo@mba.ocn.ne.jp> <90edad820911060822g40233a8ft28001d68186b989e@mail.gmail.com> <90edad820911060834t5c14aa30t847c3b75bf7e36e@mail.gmail.com> <4AF4526B.3020502@caviumnetworks.com> <90edad820911060907j4a605167xfe1ebdf0dcf7b635@mail.gmail.com> <90edad820911060923w6cd59c5dh57d123b6bc9d4219@mail.gmail.com> User-Agent: Alpine 2.00 (LFD 1167 2008-08-23) MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24744 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: macro@linux-mips.org Precedence: bulk X-list: linux-mips On Fri, 6 Nov 2009, Dmitri Vorobiev wrote: > > KSEG space is not paged, so who cares about the page size? You're not > > making additional stack page allocations, although you can overflow the > > space available at some point (but that's avoided if you know a priori > > your backtrace is not going to be deep). Static allocation has its > > drawbacks, for example it takes storage space (if it's initialised data) > > or memory space (if it's BSS) indefinitely. > > Thanks for the explanation. Then a variable-size array, I guess. Note that MIPS is at an advantage here and other architectures may have to page the kernel space, so the observation is valid for our platform code only -- for generic code (anything that goes outside arch/mips) you may have to change the assumptions. Maciej From dmitri.vorobiev@gmail.com Fri Nov 6 19:17:15 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 06 Nov 2009 19:17:22 +0100 (CET) Received: from mail-fx0-f211.google.com ([209.85.220.211]:62628 "EHLO mail-fx0-f211.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1493034AbZKFSRP convert rfc822-to-8bit (ORCPT ); Fri, 6 Nov 2009 19:17:15 +0100 Received: by fxm3 with SMTP id 3so318243fxm.24 for ; Fri, 06 Nov 2009 10:17:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:in-reply-to:references :date:message-id:subject:from:to:cc:content-type :content-transfer-encoding; bh=UrGGPXvfj1VoUReiRUmI0d9UwPg4CtpLhS1nIEf3W1Q=; b=T/bGzqVgPxAOIPjIGdzg+fbi/6uBFmUjHR+zJKMzVF6xbAZwknwfqEyoIA2d+5uMpY XPyRXUbcSbvWxP9maLRZZ6VU2gcJhiz+ZZgUBwWETRDpzSH68S60qHwi9+go6BLrd4R0 NelTz1WjjFqwWHQzyIBB/h3p/71dfemCKmBYU= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type:content-transfer-encoding; b=k1Ca4EoiZ067mK/swQfdKjjBTxpxRDcJdOhg31MltEgqGFNNEKzYL1KVY4Divl1kEC 7x9TnOdfLh4wigJz3C8QznU5bk9HAPJoH2PO263ZBAkFp4blL39gCDT+bxRf/cZ1MZuF EA1ls+5BKpu7qprc9hQR+xUum4YzbOSMdDQcw= MIME-Version: 1.0 Received: by 10.223.21.3 with SMTP id h3mr677594fab.39.1257531427029; Fri, 06 Nov 2009 10:17:07 -0800 (PST) In-Reply-To: References: <20091107.010839.246840249.anemo@mba.ocn.ne.jp> <90edad820911060822g40233a8ft28001d68186b989e@mail.gmail.com> <90edad820911060834t5c14aa30t847c3b75bf7e36e@mail.gmail.com> <4AF4526B.3020502@caviumnetworks.com> <90edad820911060907j4a605167xfe1ebdf0dcf7b635@mail.gmail.com> <90edad820911060923w6cd59c5dh57d123b6bc9d4219@mail.gmail.com> Date: Fri, 6 Nov 2009 20:17:06 +0200 Message-ID: <90edad820911061017y373cf1ale5f10b742d633b7d@mail.gmail.com> Subject: Re: COMMAND_LINE_SIZE and CONFIG_FRAME_WARN From: Dmitri Vorobiev To: "Maciej W. Rozycki" Cc: David Daney , Atsushi Nemoto , linux-mips@linux-mips.org Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24745 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dmitri.vorobiev@gmail.com Precedence: bulk X-list: linux-mips On Fri, Nov 6, 2009 at 7:30 PM, Maciej W. Rozycki wrote: > On Fri, 6 Nov 2009, Dmitri Vorobiev wrote: > >> >  KSEG space is not paged, so who cares about the page size?  You're not >> > making additional stack page allocations, although you can overflow the >> > space available at some point (but that's avoided if you know a priori >> > your backtrace is not going to be deep).  Static allocation has its >> > drawbacks, for example it takes storage space (if it's initialised data) >> > or memory space (if it's BSS) indefinitely. >> >> Thanks for the explanation. Then a variable-size array, I guess. > >  Note that MIPS is at an advantage here and other architectures may have > to page the kernel space, so the observation is valid for our platform > code only -- for generic code (anything that goes outside arch/mips) you > may have to change the assumptions. I believe that Atsushi-san was talking about the MIPS code only. Indeed, he mentioned CL_SIZE, which used to be a MIPS-specific alias to COMMAND_LINE_SIZE. Dmitri > >  Maciej > From ben@trinity.fluff.org Sat Nov 7 00:02:49 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 07 Nov 2009 00:02:56 +0100 (CET) Received: from trinity.fluff.org ([89.16.178.74]:49095 "EHLO trinity.fluff.org" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1493285AbZKFXCt (ORCPT ); Sat, 7 Nov 2009 00:02:49 +0100 Received: from ben by trinity.fluff.org with local (Exim 4.69) (envelope-from ) id 1N6XEw-0007wP-UI; Fri, 06 Nov 2009 22:25:06 +0000 Date: Fri, 6 Nov 2009 22:25:06 +0000 From: Ben Dooks To: Shinya Kuribayashi Cc: baruch@tkos.co.il, ben-linux@fluff.org, linux-i2c@vger.kernel.org, linux-mips@linux-mips.org, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v2] i2c-designware updates Message-ID: <20091106222506.GP23772@trinity.fluff.org> References: <4AF419B6.1000802@necel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <4AF419B6.1000802@necel.com> X-Disclaimer: These are my views alone. X-URL: http://www.fluff.org/ User-Agent: Mutt/1.5.18 (2008-05-17) X-SA-Exim-Connect-IP: X-SA-Exim-Mail-From: ben@trinity.fluff.org X-SA-Exim-Scanned: No (on trinity.fluff.org); SAEximRunCond expanded to false Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24746 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ben-linux@fluff.org Precedence: bulk X-list: linux-mips On Fri, Nov 06, 2009 at 09:42:30PM +0900, Shinya Kuribayashi wrote: > Hi Baruch and Ben, > > here's v2 patchset of DesignWare I2C driver (i2c-designware.c). > I did all test I can do for now (including arbitration tests), and > fixed more issues left in the v1 patchset. I think now the driver is > in reasonable shape for the mainline, and hope gets merged. > > The patches which already have Baruch's Acked-by: line are logically > same as the previous v1 patches. For the rest are revised version of > v1 patches, or newly added in v2. thanks, the first pass seems ok, will give a thorough review by next week and get a branch with them on for -next submission. -- Ben Q: What's a light-year? A: One-third less calories than a regular year. From wuzhangjin@gmail.com Sat Nov 7 11:43:37 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 07 Nov 2009 11:43:44 +0100 (CET) Received: from mail-pw0-f45.google.com ([209.85.160.45]:38156 "EHLO mail-pw0-f45.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492220AbZKGKnh (ORCPT ); Sat, 7 Nov 2009 11:43:37 +0100 Received: by pwi15 with SMTP id 15so1133848pwi.24 for ; Sat, 07 Nov 2009 02:43:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:subject:from:reply-to:to:cc :in-reply-to:references:content-type:organization:date:message-id :mime-version:x-mailer:content-transfer-encoding; bh=NCnW7gq4gEQHF5zert5f1feBUot9lS/yA6p2NZ+iX6A=; b=RZZklCfCKRJuEhOUra1sUlFazirksY2tZGqrw+yAr+Ud1H8vv76H7lmBkGx0kkINIm ijFGyzY/ZG4mCtOtwsrFfnlm50xFH+ORFVbeLpMzD/y4EFCd/hi9y8oaMSo9I4SjWVIo LX0WoHeSqxo5+XeVoKThRp6Ktgv9wCgysJUHE= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=subject:from:reply-to:to:cc:in-reply-to:references:content-type :organization:date:message-id:mime-version:x-mailer :content-transfer-encoding; b=oBIMNomW2I+0sr8iR6MLe9Mo39V4YMbR6xpDFIDKvpd5Jn/VvA+7GrmB0Rake+g6rp oNKC1Rdyb5ZSTcBQcNUnQdMNY1utPRPa5sGgSxDJWr2dGFwmarC8OQV1G1OcldvQoCR1 jHJls+2B3Y0YOmOVON3+t1TZrTwRuYXkNUev0= Received: by 10.115.84.39 with SMTP id m39mr8590988wal.62.1257590607837; Sat, 07 Nov 2009 02:43:27 -0800 (PST) Received: from ?172.16.2.101? ([222.92.8.142]) by mx.google.com with ESMTPS id 20sm557127pxi.3.2009.11.07.02.43.23 (version=TLSv1/SSLv3 cipher=RC4-MD5); Sat, 07 Nov 2009 02:43:26 -0800 (PST) Subject: Re: [PATCH -queue v1 6/7] [loongson] lemote-2f: add reset and shutdown support From: Wu Zhangjin Reply-To: wuzhangjin@gmail.com To: Ralf Baechle Cc: Arnaud Patard , zhangfx@lemote.com, yanh@lemote.com, huhb@lemote.com, Nicholas Mc Guire , linux-mips@linux-mips.org In-Reply-To: References: <17e5d58a0cd7273b81c7151b7f7f2096c9694b59.1257510612.git.wuzhangjin@gmail.com> <588574ed5910292f2728072ca147add2ae342778.1257510612.git.wuzhangjin@gmail.com> <7affa8fce1f55b817aff1c64f823824f6809dd85.1257510612.git.wuzhangjin@gmail.com> <84e7310659ae445b3b3dc68aadc8f27648c709f6.1257510612.git.wuzhangjin@gmail.com> <96301eaeffac1ae45d7529760eb961a04356dfca.1257510612.git.wuzhangjin@gmail.com> Content-Type: text/plain; charset="UTF-8" Organization: DSLab, Lanzhou University, China Date: Sat, 07 Nov 2009 18:43:01 +0800 Message-ID: <1257590581.2251.9.camel@falcon.domain.org> Mime-Version: 1.0 X-Mailer: Evolution 2.28.1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24747 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips Hi, On Fri, 2009-11-06 at 21:11 +0800, Wu Zhangjin wrote: > From: Wu Zhangjin > > fuloong2f, yeeloong2f and menglong2f have different reset/shutdown > logic, this patch add respective support for them. > > Signed-off-by: Wu Zhangjin > --- > arch/mips/include/asm/mach-loongson/loongson.h | 7 + > arch/mips/loongson/lemote-2f/Makefile | 2 +- > arch/mips/loongson/lemote-2f/reset.c | 163 ++++++++++++++++++++++++ > 3 files changed, 171 insertions(+), 1 deletions(-) > create mode 100644 arch/mips/loongson/lemote-2f/reset.c > [...] > + > +/* we only cope with the lemote 2f series */ > +typedef void (*mach_reset_func)(void); > +static mach_reset_func mach_reset[][2] = { > + [MACH_LOONGSON_UNKNOWN] {NULL, NULL}, > + [MACH_LEMOTE_FL2E] {NULL, NULL}, > + [MACH_LEMOTE_FL2F] {fl2f_reboot, fl2f_shutdown}, > + [MACH_LEMOTE_ML2F7] {ml2f_reboot, ml2f_shutdown}, > + [MACH_LEMOTE_YL2F89] {yl2f89_reboot, yl2f89_shutdown}, > + [MACH_DEXXON_GDIUM2F10] {NULL, NULL}, > + [MACH_LOONGSON_END] {NULL, NULL}, > +}; > + Here really waste some memory there, will replace it by the "switch..case" statements later. > +void mach_prepare_reboot(void) > +{ > + if (mach_reset[mips_machtype][0]) > + mach_reset[mips_machtype][0](); > +} > + > +void mach_prepare_shutdown(void) > +{ > + if (mach_reset[mips_machtype][1]) > + mach_reset[mips_machtype][1](); > +} Reagrds, Wu Zhangjin From wuzhangjin@gmail.com Sat Nov 7 11:56:00 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 07 Nov 2009 11:56:06 +0100 (CET) Received: from mail-pw0-f45.google.com ([209.85.160.45]:47401 "EHLO mail-pw0-f45.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492260AbZKGK4A (ORCPT ); Sat, 7 Nov 2009 11:56:00 +0100 Received: by pwi15 with SMTP id 15so1137204pwi.24 for ; Sat, 07 Nov 2009 02:55:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:subject:from:reply-to:to:cc :in-reply-to:references:content-type:organization:date:message-id :mime-version:x-mailer:content-transfer-encoding; bh=85nv026wuR6V8NQ8HmlCmt+nwmEFvmI5aQwZ6kofOkU=; b=NvcW+Wdt0yXeVT63cJxZpREmDhvTkszDumXDfPdZFwQ4Oz2CxJRj/gq/jD+gsro3jS nlVQYpRerYKlKflvN1HKhYvg+neiC1uFwpHNYw2cozOl0UA0HoqlJH2Qy5HILNXCfedA A9AqfKxJTPxjZfC2V0oUQJTVnInLflBsupFFc= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=subject:from:reply-to:to:cc:in-reply-to:references:content-type :organization:date:message-id:mime-version:x-mailer :content-transfer-encoding; b=SQl0gT+M6PguYC5IXHW7O5bAJnUSJrBDI3UrYDUu2X7Uv8ZNsABiUUd0g+rGVQIre2 o/XjowkUCqh4o9XleQInknZ/a1myDdWR4ZMrD2vy5F2QNb4vRs5xpzomsItE1AI0wgWb yeGGgyF17CftWSfOYahghnrpG704QCKhcTllI= Received: by 10.115.100.22 with SMTP id c22mr1916651wam.58.1257591353473; Sat, 07 Nov 2009 02:55:53 -0800 (PST) Received: from ?172.16.2.101? ([222.92.8.142]) by mx.google.com with ESMTPS id 23sm536082pzk.4.2009.11.07.02.55.49 (version=TLSv1/SSLv3 cipher=RC4-MD5); Sat, 07 Nov 2009 02:55:52 -0800 (PST) Subject: Re: [PATCH -queue v1 4/7] [loongson] lemote-2f: add pci support From: Wu Zhangjin Reply-To: wuzhangjin@gmail.com To: Ralf Baechle Cc: Arnaud Patard , zhangfx@lemote.com, yanh@lemote.com, huhb@lemote.com, Nicholas Mc Guire , linux-mips@linux-mips.org In-Reply-To: <84e7310659ae445b3b3dc68aadc8f27648c709f6.1257510612.git.wuzhangjin@gmail.com> References: <17e5d58a0cd7273b81c7151b7f7f2096c9694b59.1257510612.git.wuzhangjin@gmail.com> <588574ed5910292f2728072ca147add2ae342778.1257510612.git.wuzhangjin@gmail.com> <7affa8fce1f55b817aff1c64f823824f6809dd85.1257510612.git.wuzhangjin@gmail.com> <84e7310659ae445b3b3dc68aadc8f27648c709f6.1257510612.git.wuzhangjin@gmail.com> Content-Type: text/plain; charset="UTF-8" Organization: DSLab, Lanzhou University, China Date: Sat, 07 Nov 2009 18:55:51 +0800 Message-ID: <1257591351.2251.12.camel@falcon.domain.org> Mime-Version: 1.0 X-Mailer: Evolution 2.28.1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24748 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips On Fri, 2009-11-06 at 21:11 +0800, Wu Zhangjin wrote: > From: Wu Zhangjin > > Most of the pci support between fuloong2e and lemote loongson2f family > machines are the same, except the cs5536 support. > > This patch renames ops-fuloong2e.c to ops-loongson2.c and then append > the cs5536 support to share most of the source code among loongson > machines. [...] > + > + > +static int loongson_pcibios_config_access(unsigned char access_type, > + struct pci_bus *bus, > + unsigned int devfn, int where, > + u32 *data) > +{ > + u32 busnum = bus->number; > + u32 addr, type; > + u32 dummy; > + void *addrp; > + int device = PCI_SLOT(devfn); > + int function = PCI_FUNC(devfn); > + int reg = where & ~3; > + > + if (busnum == 0) { > + /* board-specific part,currently,only fuloong2f,yeeloong2f > + * use CS5536, fuloong2e use via686b, gdium has no > + * south bridge > + */ > +#ifdef CONFIG_CS5536 > + /* cs5536_pci_conf_read4/write4() will call _rdmsr/_wrmsr() to > + * access the regsters PCI_MSR_ADDR, PCI_MSR_DATA_LO, > + * PCI_MSR_DATA_HI, which is bigger than 0xf0, so, it will not > + * go this branch, but the others. so, no calling dead loop > + * here. > + */ > + if ((PCI_IDSEL_CS5536 == device) && (reg < PCI_MSR_CTRL)) { 0xf0 is exactly PCI_MSR_CTRL, will replace it by PCI_MSR_CTRL later. Regards, Wu Zhangjin From anemo@mba.ocn.ne.jp Sat Nov 7 18:19:24 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 07 Nov 2009 18:19:31 +0100 (CET) Received: from mba.ocn.ne.jp ([122.28.14.163]:52685 "HELO smtp.mba.ocn.ne.jp" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with SMTP id S1492879AbZKGRTY (ORCPT ); Sat, 7 Nov 2009 18:19:24 +0100 Received: from localhost (p6079-ipad307funabasi.chiba.ocn.ne.jp [123.217.184.79]) by smtp.mba.ocn.ne.jp (Postfix) with ESMTP id 5C7D671C8; Sun, 8 Nov 2009 02:19:15 +0900 (JST) Date: Sun, 08 Nov 2009 02:19:14 +0900 (JST) Message-Id: <20091108.021914.11603096.anemo@mba.ocn.ne.jp> To: dmitri.vorobiev@gmail.com Cc: macro@linux-mips.org, ddaney@caviumnetworks.com, linux-mips@linux-mips.org Subject: Re: COMMAND_LINE_SIZE and CONFIG_FRAME_WARN From: Atsushi Nemoto In-Reply-To: <90edad820911061017y373cf1ale5f10b742d633b7d@mail.gmail.com> References: <90edad820911060923w6cd59c5dh57d123b6bc9d4219@mail.gmail.com> <90edad820911061017y373cf1ale5f10b742d633b7d@mail.gmail.com> X-Fingerprint: 6ACA 1623 39BD 9A94 9B1A B746 CA77 FE94 2874 D52F X-Pgp-Public-Key: http://wwwkeys.pgp.net/pks/lookup?op=get&search=0x2874D52F X-Mailer: Mew version 5.2 on Emacs 22.2 / Mule 5.0 (SAKAKI) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24749 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anemo@mba.ocn.ne.jp Precedence: bulk X-list: linux-mips On Fri, 6 Nov 2009 20:17:06 +0200, Dmitri Vorobiev wrote: > I believe that Atsushi-san was talking about the MIPS code only. > Indeed, he mentioned CL_SIZE, which used to be a MIPS-specific alias > to COMMAND_LINE_SIZE. Yes, and I think static array is safest option now. MIPS might be able to use large stack on early bootstrap stage, but this assumption looks slightly fragile for me. And excessive zero-initialized __initdata size will not be a problem especially if vmlinux is compressed. Thank you everyone, I will post a patch soon. --- Atsushi Nemoto From anemo@mba.ocn.ne.jp Sat Nov 7 18:20:42 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 07 Nov 2009 18:20:49 +0100 (CET) Received: from mba.ocn.ne.jp ([122.28.14.163]:56616 "HELO smtp.mba.ocn.ne.jp" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with SMTP id S1492878AbZKGRUm (ORCPT ); Sat, 7 Nov 2009 18:20:42 +0100 Received: from localhost.localdomain (p6079-ipad307funabasi.chiba.ocn.ne.jp [123.217.184.79]) by smtp.mba.ocn.ne.jp (Postfix) with ESMTP id 94FFE71C9; Sun, 8 Nov 2009 02:20:38 +0900 (JST) From: Atsushi Nemoto To: linux-mips@linux-mips.org Cc: ralf@linux-mips.org Subject: [PATCH] MIPS: Make local arrays with CL_SIZE static __initdata Date: Sun, 8 Nov 2009 02:20:37 +0900 Message-Id: <1257614437-8632-1-git-send-email-anemo@mba.ocn.ne.jp> X-Mailer: git-send-email 1.5.6.5 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24750 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anemo@mba.ocn.ne.jp Precedence: bulk X-list: linux-mips Since commit 22242681 ("MIPS: Extend COMMAND_LINE_SIZE"), CL_SIZE is 4096 and local array variables with this size will cause an build failure with default CONFIG_FRAME_WARN settings. Although current users of such array variables are all early bootstrap code and might not cause real stack overflow (thread_info corruption), it would be safe to declare these arrays static with __initdata. Signed-off-by: Atsushi Nemoto --- arch/mips/bcm47xx/prom.c | 2 +- arch/mips/mti-malta/malta-memory.c | 3 ++- arch/mips/rb532/prom.c | 2 +- arch/mips/txx9/generic/setup.c | 4 ++-- 4 files changed, 6 insertions(+), 5 deletions(-) diff --git a/arch/mips/bcm47xx/prom.c b/arch/mips/bcm47xx/prom.c index 079e33d..fb284c3 100644 --- a/arch/mips/bcm47xx/prom.c +++ b/arch/mips/bcm47xx/prom.c @@ -100,7 +100,7 @@ static __init void prom_init_console(void) static __init void prom_init_cmdline(void) { - char buf[CL_SIZE]; + static char buf[CL_SIZE] __initdata; /* Get the kernel command line from CFE */ if (cfe_getenv("LINUX_CMDLINE", buf, CL_SIZE) >= 0) { diff --git a/arch/mips/mti-malta/malta-memory.c b/arch/mips/mti-malta/malta-memory.c index 61888ff..9035c64 100644 --- a/arch/mips/mti-malta/malta-memory.c +++ b/arch/mips/mti-malta/malta-memory.c @@ -54,7 +54,8 @@ static struct prom_pmemblock * __init prom_getmdesc(void) { char *memsize_str; unsigned int memsize; - char cmdline[CL_SIZE], *ptr; + char *ptr; + static char cmdline[CL_SIZE] __initdata; /* otherwise look in the environment */ memsize_str = prom_getenv("memsize"); diff --git a/arch/mips/rb532/prom.c b/arch/mips/rb532/prom.c index 46ca24d..ad5bd10 100644 --- a/arch/mips/rb532/prom.c +++ b/arch/mips/rb532/prom.c @@ -69,7 +69,7 @@ static inline unsigned long tag2ul(char *arg, const char *tag) void __init prom_setup_cmdline(void) { - char cmd_line[CL_SIZE]; + static char cmd_line[CL_SIZE] __initdata; char *cp, *board; int prom_argc; char **prom_argv, **prom_envp; diff --git a/arch/mips/txx9/generic/setup.c b/arch/mips/txx9/generic/setup.c index e10184c..d66802e 100644 --- a/arch/mips/txx9/generic/setup.c +++ b/arch/mips/txx9/generic/setup.c @@ -160,7 +160,7 @@ static void __init prom_init_cmdline(void) int argc; int *argv32; int i; /* Always ignore the "-c" at argv[0] */ - char builtin[CL_SIZE]; + static char builtin[CL_SIZE] __initdata; if (fw_arg0 >= CKSEG0 || fw_arg1 < CKSEG0) { /* @@ -315,7 +315,7 @@ static inline void txx9_cache_fixup(void) static void __init preprocess_cmdline(void) { - char cmdline[CL_SIZE]; + static char cmdline[CL_SIZE] __initdata; char *s; strcpy(cmdline, arcs_cmdline); -- 1.5.6.5 From dmitri.vorobiev@gmail.com Sat Nov 7 19:16:58 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 07 Nov 2009 19:17:06 +0100 (CET) Received: from fg-out-1718.google.com ([72.14.220.153]:43135 "EHLO fg-out-1718.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492932AbZKGSQ6 convert rfc822-to-8bit (ORCPT ); Sat, 7 Nov 2009 19:16:58 +0100 Received: by fg-out-1718.google.com with SMTP id d23so888208fga.6 for ; Sat, 07 Nov 2009 10:16:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:in-reply-to:references :date:message-id:subject:from:to:cc:content-type :content-transfer-encoding; bh=kWNCg9KEVQQID2SolBlgU7aBt8khuYlLS07Jl/y8m5A=; b=fWLUY7KWv+78sIEhzr3ZuOYSWOHnMbS+Znz/LQ+4QVPSCB/wq3LME/O2mWE3bcbGHG VWxPaT9AzdF8N0CX4MPL+8RsuGzPqqmtu271p/s4wvVEFsycSoGpVHLiO8mwgA8w2zc3 mJs6UgWUAnR98kzehhpTgaHOmNvUVI7FWPzIE= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type:content-transfer-encoding; b=XqAAGVe6sPcSnq9GeBv8vXBJQcilQyjk/TWZW8eCjYJJFzuO+5M/hV/rCLMVpTX3gl LmomLNaHrULrZy+dpOIGTCTa5ewF3nLeHZKbpeKxnJ/y+ZoUPDBYUoFxs8z9Xva9F3Y3 HuTV9QzuPqt2yXFE9kV3rVn9cR0OBxwejntKI= MIME-Version: 1.0 Received: by 10.223.145.129 with SMTP id d1mr816010fav.99.1257617817607; Sat, 07 Nov 2009 10:16:57 -0800 (PST) In-Reply-To: <1257614437-8632-1-git-send-email-anemo@mba.ocn.ne.jp> References: <1257614437-8632-1-git-send-email-anemo@mba.ocn.ne.jp> Date: Sat, 7 Nov 2009 20:16:57 +0200 Message-ID: <90edad820911071016v70e6e68bia8f0c3b6f09ceb3c@mail.gmail.com> Subject: Re: [PATCH] MIPS: Make local arrays with CL_SIZE static __initdata From: Dmitri Vorobiev To: Atsushi Nemoto Cc: linux-mips@linux-mips.org, ralf@linux-mips.org Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24751 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dmitri.vorobiev@gmail.com Precedence: bulk X-list: linux-mips On Sat, Nov 7, 2009 at 7:20 PM, Atsushi Nemoto wrote: > Since commit 22242681 ("MIPS: Extend COMMAND_LINE_SIZE"), CL_SIZE is > 4096 and local array variables with this size will cause an build > failure with default CONFIG_FRAME_WARN settings. > > Although current users of such array variables are all early bootstrap > code and might not cause real stack overflow (thread_info corruption), > it would be safe to declare these arrays static with __initdata. > > Signed-off-by: Atsushi Nemoto > --- >  arch/mips/bcm47xx/prom.c           |    2 +- >  arch/mips/mti-malta/malta-memory.c |    3 ++- >  arch/mips/rb532/prom.c             |    2 +- >  arch/mips/txx9/generic/setup.c     |    4 ++-- >  4 files changed, 6 insertions(+), 5 deletions(-) > > diff --git a/arch/mips/bcm47xx/prom.c b/arch/mips/bcm47xx/prom.c > index 079e33d..fb284c3 100644 > --- a/arch/mips/bcm47xx/prom.c > +++ b/arch/mips/bcm47xx/prom.c > @@ -100,7 +100,7 @@ static __init void prom_init_console(void) > >  static __init void prom_init_cmdline(void) >  { > -       char buf[CL_SIZE]; > +       static char buf[CL_SIZE] __initdata; If this is intended for -queue, this patch won't apply, because CL_SIZE was recently removed in favor of using CONFIG_CMDLINE_SIZE directly. Also, I think it's more common to place __initdata before the variable name, not after it, although tastes do differ. :) Thanks, Dmitri From macro@linux-mips.org Sat Nov 7 20:14:22 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 07 Nov 2009 20:14:29 +0100 (CET) Received: from localhost.localdomain ([127.0.0.1]:46960 "EHLO localhost.localdomain" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1493345AbZKGTOW (ORCPT ); Sat, 7 Nov 2009 20:14:22 +0100 Date: Sat, 7 Nov 2009 19:14:22 +0000 (GMT) From: "Maciej W. Rozycki" To: Dmitri Vorobiev cc: Atsushi Nemoto , linux-mips@linux-mips.org, ralf@linux-mips.org Subject: Re: [PATCH] MIPS: Make local arrays with CL_SIZE static __initdata In-Reply-To: <90edad820911071016v70e6e68bia8f0c3b6f09ceb3c@mail.gmail.com> Message-ID: References: <1257614437-8632-1-git-send-email-anemo@mba.ocn.ne.jp> <90edad820911071016v70e6e68bia8f0c3b6f09ceb3c@mail.gmail.com> User-Agent: Alpine 2.00 (LFD 1167 2008-08-23) MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24752 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: macro@linux-mips.org Precedence: bulk X-list: linux-mips On Sat, 7 Nov 2009, Dmitri Vorobiev wrote: > Also, I think it's more common to place __initdata before the variable > name, not after it, although tastes do differ. :) Well, disagrees. Maciej From dmitri.vorobiev@gmail.com Sat Nov 7 23:09:02 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 07 Nov 2009 23:09:10 +0100 (CET) Received: from mail-fx0-f211.google.com ([209.85.220.211]:54482 "EHLO mail-fx0-f211.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1493408AbZKGWJC convert rfc822-to-8bit (ORCPT ); Sat, 7 Nov 2009 23:09:02 +0100 Received: by fxm3 with SMTP id 3so602875fxm.24 for ; Sat, 07 Nov 2009 14:08:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:in-reply-to:references :date:message-id:subject:from:to:cc:content-type :content-transfer-encoding; bh=7+lUlPvbQEdrGn1HO0PaLy8XpR4CG3YbMCIKPvb9ICc=; b=va6zMQYd00ciH4/I1QflxRLh9ynFd6exImcCvQykYoqCUBqfaxaDfV/G8fxyMysOmn PC6udvDBqpfbNNfzPB5NGpCGOuqOFOFcZ3+/1spyyvPYqKfraPhWdPVQfQN6FSqPX2Ky R1YJb1SBmtVujd6fqGYr/5ucGWw3V4bytXYfo= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type:content-transfer-encoding; b=Ldj3DmrhLBwDY5GX0/XDCDICr7BQYFMn0JNS3mUU2QV9wqyn47DmheKH08jmt5kkqG zBc4u0r6HIZh+d1rRy1ISHXq480gnw31UU6+WmmOtn3DHm1ff0SBaXueNU5LS1OALTN9 AEZYEPUX6KxTqMh9GY3vTznLdpxrFaldGJOeo= MIME-Version: 1.0 Received: by 10.223.145.129 with SMTP id d1mr842230fav.99.1257631736528; Sat, 07 Nov 2009 14:08:56 -0800 (PST) In-Reply-To: References: <1257614437-8632-1-git-send-email-anemo@mba.ocn.ne.jp> <90edad820911071016v70e6e68bia8f0c3b6f09ceb3c@mail.gmail.com> Date: Sun, 8 Nov 2009 00:08:56 +0200 Message-ID: <90edad820911071408v16e62cb9na2b2d0030f2e1047@mail.gmail.com> Subject: Re: [PATCH] MIPS: Make local arrays with CL_SIZE static __initdata From: Dmitri Vorobiev To: "Maciej W. Rozycki" Cc: Atsushi Nemoto , linux-mips@linux-mips.org, ralf@linux-mips.org Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24753 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dmitri.vorobiev@gmail.com Precedence: bulk X-list: linux-mips On Sat, Nov 7, 2009 at 9:14 PM, Maciej W. Rozycki wrote: > On Sat, 7 Nov 2009, Dmitri Vorobiev wrote: > >> Also, I think it's more common to place __initdata before the variable >> name, not after it, although tastes do differ. :) > >  Well, disagrees. Indeed. Thanks for the correction. Dmitri > >  Maciej > From anemo@mba.ocn.ne.jp Sun Nov 8 12:50:20 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 08 Nov 2009 12:50:26 +0100 (CET) Received: from mba.ocn.ne.jp ([122.28.14.163]:61378 "HELO smtp.mba.ocn.ne.jp" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with SMTP id S1492229AbZKHLuT convert rfc822-to-8bit (ORCPT ); Sun, 8 Nov 2009 12:50:19 +0100 Received: from localhost (p5082-ipad205funabasi.chiba.ocn.ne.jp [222.146.100.82]) by smtp.mba.ocn.ne.jp (Postfix) with ESMTP id AD6DD6968; Sun, 8 Nov 2009 20:50:07 +0900 (JST) Date: Sun, 08 Nov 2009 20:50:07 +0900 (JST) Message-Id: <20091108.205007.59470244.anemo@mba.ocn.ne.jp> To: dmitri.vorobiev@gmail.com Cc: linux-mips@linux-mips.org, ralf@linux-mips.org Subject: Re: [PATCH] MIPS: Make local arrays with CL_SIZE static __initdata From: Atsushi Nemoto In-Reply-To: <90edad820911071016v70e6e68bia8f0c3b6f09ceb3c@mail.gmail.com> References: <1257614437-8632-1-git-send-email-anemo@mba.ocn.ne.jp> <90edad820911071016v70e6e68bia8f0c3b6f09ceb3c@mail.gmail.com> X-Fingerprint: 6ACA 1623 39BD 9A94 9B1A B746 CA77 FE94 2874 D52F X-Pgp-Public-Key: http://wwwkeys.pgp.net/pks/lookup?op=get&search=0x2874D52F X-Mailer: Mew version 5.2 on Emacs 22.2 / Mule 5.0 (SAKAKI) Mime-Version: 1.0 Content-Type: Text/Plain; charset=iso-8859-1 Content-Transfer-Encoding: 8BIT Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24754 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anemo@mba.ocn.ne.jp Precedence: bulk X-list: linux-mips On Sat, 7 Nov 2009 20:16:57 +0200, Dmitri Vorobiev wrote: > > --- a/arch/mips/bcm47xx/prom.c > > +++ b/arch/mips/bcm47xx/prom.c > > @@ -100,7 +100,7 @@ static __init void prom_init_console(void) > > > >  static __init void prom_init_cmdline(void) > >  { > > -       char buf[CL_SIZE]; > > +       static char buf[CL_SIZE] __initdata; > > If this is intended for -queue, this patch won't apply, because > CL_SIZE was recently removed in favor of using CONFIG_CMDLINE_SIZE > directly. Oh I missed your CL_SIZE removal patch. Anyway I want this patch for 2.6.32 since this is regression. If the CL_SIZE removal patch was merged for 2.6.32 first, I will update my patch. Othersize, your patch needs update, but I suppose we can do it easily. Of course Ralf can do it too ;) --- Atsushi Nemoto From f.fainelli@gmail.com Sun Nov 8 15:42:17 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 08 Nov 2009 15:42:24 +0100 (CET) Received: from mail-ew0-f216.google.com ([209.85.219.216]:45501 "EHLO mail-ew0-f216.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492552AbZKHOmR (ORCPT ); Sun, 8 Nov 2009 15:42:17 +0100 Received: by ewy12 with SMTP id 12so2512825ewy.0 for ; Sun, 08 Nov 2009 06:42:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:sender:from:date:subject :mime-version:x-uid:x-length:to:cc:reply-to:content-type :content-transfer-encoding:message-id; bh=/+udKPeYSONC0E0WiVDxat5RrP2D+b8bEkjZsdyGt6M=; b=dF8uqMVDa0Vgj3wSR8nvw3p5dKBucQVF/Kxm5/o3xuX5kwnttFetRHdvkUcTag7l7L DYRt9rsKf0obCI1oGyr661CdM3QZswNsCvShL26KNPLnpSOMN224joWh0ZprP5BMpnI4 vdp7ThFW9LY1/3yFj4OH6VUQUdqedpvRP3vAo= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:from:date:subject:mime-version:x-uid:x-length:to:cc:reply-to :content-type:content-transfer-encoding:message-id; b=ewrGA7YArJ9JgKVvstks6ht44uSrjZMNriMDv5ZD8mS+5Uqa+dhrn0seTkeHK10ETo xVExn0bIxztKR/8ODHE0jnHSVHUXPNQCGOqxGZrjOrFq8jzjaXh42y3Te6GhjhsoqtCj 0740EJZRKKbcnpAeT7nSC949hueDQYEG78O5s= Received: by 10.213.24.15 with SMTP id t15mr1869043ebb.89.1257691330260; Sun, 08 Nov 2009 06:42:10 -0800 (PST) Received: from lenovo.localnet (florian.mimichou.net [88.178.11.95]) by mx.google.com with ESMTPS id 10sm3695947eyz.43.2009.11.08.06.42.09 (version=TLSv1/SSLv3 cipher=RC4-MD5); Sun, 08 Nov 2009 06:42:09 -0800 (PST) From: Florian Fainelli Date: Sun, 8 Nov 2009 15:42:05 +0100 Subject: [PATCH v4] alchemy: add au1000-eth platform device MIME-Version: 1.0 X-UID: 138 X-Length: 7939 To: "linux-mips" , David Miller Cc: Ralf Baechle , netdev@vger.kernel.org Reply-To: Florian Fainelli Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <200911081542.06754.florian@openwrt.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 24755 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips This patch makes the board code register the au1000-eth platform device. The au1000-eth platform data can be overriden with the au1xxx_override_eth_cfg function like it has to be done for the Bosporus board which uses a different MAC/PHY setup. Changes from v3: - declare a static au1000_eth_platform_data structure for bosporus and initialize it - remove parenthis and bit shifting on SYS_PF_NI2 Changes from v2: - declared the au1000-eth second driver instance platform_data - made the override function generic and pass it the port number too Changes from v1: - remove per-board platform.c file - add an override function to pass custom eth0 platform_data PHY settings Signed-off-by: Florian Fainelli --- diff --git a/arch/mips/alchemy/common/platform.c b/arch/mips/alchemy/common/platform.c index 3be14b0..3fbe30c 100644 --- a/arch/mips/alchemy/common/platform.c +++ b/arch/mips/alchemy/common/platform.c @@ -19,6 +19,7 @@ #include #include #include +#include #define PORT(_base, _irq) \ { \ @@ -326,6 +327,88 @@ static struct platform_device pbdb_smbus_device = { }; #endif +/* Macro to help defining the Ethernet MAC resources */ +#define MAC_RES(_base, _enable, _irq) \ + { \ + .start = CPHYSADDR(_base), \ + .end = CPHYSADDR(_base + 0xffff), \ + .flags = IORESOURCE_MEM, \ + }, \ + { \ + .start = CPHYSADDR(_enable), \ + .end = CPHYSADDR(_enable + 0x3), \ + .flags = IORESOURCE_MEM, \ + }, \ + { \ + .start = _irq, \ + .end = _irq, \ + .flags = IORESOURCE_IRQ \ + } + +static struct resource au1xxx_eth0_resources[] = { +#if defined(CONFIG_SOC_AU1000) + MAC_RES(AU1000_ETH0_BASE, AU1000_MAC0_ENABLE, AU1000_MAC0_DMA_INT), +#elif defined(CONFIG_SOC_AU1100) + MAC_RES(AU1100_ETH0_BASE, AU1100_MAC0_ENABLE, AU1100_MAC0_DMA_INT), +#elif defined(CONFIG_SOC_AU1550) + MAC_RES(AU1550_ETH0_BASE, AU1550_MAC0_ENABLE, AU1550_MAC0_DMA_INT), +#elif defined(CONFIG_SOC_AU1500) + MAC_RES(AU1500_ETH0_BASE, AU1500_MAC0_ENABLE, AU1500_MAC0_DMA_INT), +#endif +}; + +static struct resource au1xxx_eth1_resources[] = { +#if defined(CONFIG_SOC_AU1000) + MAC_RES(AU1000_ETH1_BASE, AU1000_MAC1_ENABLE, AU1000_MAC1_DMA_INT), +#elif defined(CONFIG_SOC_AU1550) + MAC_RES(AU1550_ETH1_BASE, AU1550_MAC1_ENABLE, AU1550_MAC1_DMA_INT), +#elif defined(CONFIG_SOC_AU1500) + MAC_RES(AU1500_ETH1_BASE, AU1500_MAC1_ENABLE, AU1500_MAC1_DMA_INT), +#endif +}; + +static struct au1000_eth_platform_data au1xxx_eth0_platform_data = { + .phy1_search_mac0 = 1, +}; + +static struct platform_device au1xxx_eth0_device = { + .name = "au1000-eth", + .id = 0, + .num_resources = ARRAY_SIZE(au1xxx_eth0_resources), + .resource = au1xxx_eth0_resources, + .dev.platform_data = &au1xxx_eth0_platform_data, +}; + +#ifndef CONFIG_SOC_AU1100 +static struct au1000_eth_platform_data au1xxx_eth1_platform_data = { + .phy1_search_mac0 = 1, +}; + +static struct platform_device au1xxx_eth1_device = { + .name = "au1000-eth", + .id = 1, + .num_resources = ARRAY_SIZE(au1xxx_eth1_resources), + .resource = au1xxx_eth1_resources, + .dev.platform_data = &au1xxx_eth1_platform_data, +}; +#endif + +void __init au1xxx_override_eth_cfg(unsigned int port, + struct au1000_eth_platform_data *eth_data) +{ + if (!eth_data || port > 1) + return; + + if (port == 0) + memcpy(&au1xxx_eth0_platform_data, eth_data, + sizeof(struct au1000_eth_platform_data)); +#ifndef CONFIG_SOC_AU1100 + else + memcpy(&au1xxx_eth1_platform_data, eth_data, + sizeof(struct au1000_eth_platform_data)); +#endif +} + static struct platform_device *au1xxx_platform_devices[] __initdata = { &au1xx0_uart_device, &au1xxx_usb_ohci_device, @@ -345,6 +428,7 @@ static struct platform_device *au1xxx_platform_devices[] __initdata = { #ifdef SMBUS_PSC_BASE &pbdb_smbus_device, #endif + &au1xxx_eth0_device, }; static int __init au1