From f.fainelli@gmail.com Sat Aug 1 23:51:27 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 01 Aug 2009 23:51:33 +0200 (CEST) Received: from ey-out-1920.google.com ([74.125.78.146]:22463 "EHLO ey-out-1920.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1493079AbZHAVv0 (ORCPT ); Sat, 1 Aug 2009 23:51:26 +0200 Received: by ey-out-1920.google.com with SMTP id 13so650314eye.54 for ; Sat, 01 Aug 2009 14:51:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:sender:from:date:subject :mime-version:x-uid:x-length:to:cc:content-disposition:message-id :content-type:content-transfer-encoding; bh=z2UsN6GbeVUlW9gocuxZShCBF31gj8f96oapDZWDDe0=; b=UMRJ4oGaXu2Momv3SJrbZyi+/JGS90uDutLwvYeuqLT2C/+eOHLyUN3MIJrhIrnufY Rhdl5uqv5alAEPNKaV43G5zpddH2cfYwI8eF7Ld/UmnNYobGQS2Nw5y2QSdnqCA2dsMC a8uHenahP8MbxvcXLGdIknvtgi/vq0vXSto8c= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:from:date:subject:mime-version:x-uid:x-length:to:cc :content-disposition:message-id:content-type :content-transfer-encoding; b=mf4mE7SkN9VyLsmUMmwt6U8/+PRDLJ50GcRzVv3vyKYLV/BwIDwzjxaHwvZn25U2VD BgI6qDloKgGARCbj7/+QCyebj0fxr39FERUvH73SecX+7VwBTuC3SkW4JwGFzkxEeoN6 CBgUK4ieCqnDmjOwY/6YIJVrmQ7x4LcEhbJx8= Received: by 10.210.129.3 with SMTP id b3mr2899251ebd.34.1249163486478; Sat, 01 Aug 2009 14:51:26 -0700 (PDT) Received: from tunnel.evry (florian.mimichou.net [82.241.112.26]) by mx.google.com with ESMTPS id 28sm3891390eye.14.2009.08.01.14.51.25 (version=TLSv1/SSLv3 cipher=RC4-MD5); Sat, 01 Aug 2009 14:51:25 -0700 (PDT) From: Florian Fainelli Date: Sat, 1 Aug 2009 23:51:20 +0200 Subject: [PATCH] mtx-1: request button GPIO before setting its direction MIME-Version: 1.0 X-UID: 1099 X-Length: 2416 To: Ralf Baechle Cc: linux-mips@linux-mips.org, Manuel Lauss Content-Disposition: inline Message-Id: <200908012351.21059.florian@openwrt.org> Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23812 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips This patch fixes the following warning at boot time: WARNING: at drivers/gpio/gpiolib.c:83 0x8021d5e0() autorequest GPIO-207 Modules linked in: Call Trace:[<8011e0ec>] 0x8011e0ec [<80110a28>] 0x80110a28 [<80110a28>] 0x80110a28 [..snip..] The current code does not request the GPIO and attempts to set its direction, which is a violation of the GPIO API. This patch also unhardcode the GPIO we request and use the one we defined in the button driver. Signed-off-by: Florian Fainelli --- diff --git a/arch/mips/alchemy/mtx-1/platform.c b/arch/mips/alchemy/mtx-1/platform.c index 8b5914d..e30e42a 100644 --- a/arch/mips/alchemy/mtx-1/platform.c +++ b/arch/mips/alchemy/mtx-1/platform.c @@ -1,7 +1,7 @@ /* * MTX-1 platform devices registration * - * Copyright (C) 2007, Florian Fainelli + * Copyright (C) 2007-2009, Florian Fainelli * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -142,7 +142,17 @@ static struct __initdata platform_device * mtx1_devs[] = { static int __init mtx1_register_devices(void) { - gpio_direction_input(207); + int rc; + + rc = gpio_request(mtx1_gpio_button[0].gpio, + mtx1_gpio_button[0].desc); + if (rc < 0) { + printk(KERN_INFO "mtx1: failed to request %d\n", + mtx1_gpio_button[0].gpio); + goto out; + } + gpio_direction_input(mtx1_gpio_button[0].gpio); +out: return platform_add_devices(mtx1_devs, ARRAY_SIZE(mtx1_devs)); } From julia@diku.dk Sun Aug 2 10:49:54 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 02 Aug 2009 10:50:00 +0200 (CEST) Received: from mgw2.diku.dk ([130.225.96.92]:46359 "EHLO mgw2.diku.dk" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1491975AbZHBIty (ORCPT ); Sun, 2 Aug 2009 10:49:54 +0200 Received: from localhost (localhost [127.0.0.1]) by mgw2.diku.dk (Postfix) with ESMTP id 9B07419BB41; Sun, 2 Aug 2009 10:49:51 +0200 (CEST) Received: from mgw2.diku.dk ([127.0.0.1]) by localhost (mgw2.diku.dk [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 15265-11; Sun, 2 Aug 2009 10:49:49 +0200 (CEST) Received: from nhugin.diku.dk (nhugin.diku.dk [130.225.96.140]) by mgw2.diku.dk (Postfix) with ESMTP id 0CA8719BB7E; Sun, 2 Aug 2009 10:48:09 +0200 (CEST) Received: from ask.diku.dk (ask.diku.dk [130.225.96.225]) by nhugin.diku.dk (Postfix) with ESMTP id A10896DFCFD; Sun, 2 Aug 2009 10:47:17 +0200 (CEST) Received: by ask.diku.dk (Postfix, from userid 3767) id ED51B154E13; Sun, 2 Aug 2009 10:48:08 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by ask.diku.dk (Postfix) with ESMTP id EBCE01549A9; Sun, 2 Aug 2009 10:48:08 +0200 (CEST) Date: Sun, 2 Aug 2009 10:48:08 +0200 (CEST) From: Julia Lawall To: ralf@linux-mips.org, linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, kernel-janitors@vger.kernel.org Subject: [PATCH 10/15] arch/mips: Use DIV_ROUND_CLOSEST Message-ID: MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII X-Virus-Scanned: amavisd-new at diku.dk Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23813 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: julia@diku.dk Precedence: bulk X-list: linux-mips From: Julia Lawall The kernel.h macro DIV_ROUND_CLOSEST performs the computation (x + d/2)/d but is perhaps more readable. The semantic patch that makes this change is as follows: (http://www.emn.fr/x-info/coccinelle/) // @haskernel@ @@ #include @depends on haskernel@ expression x,__divisor; @@ - (((x) + ((__divisor) / 2)) / (__divisor)) + DIV_ROUND_CLOSEST(x,__divisor) // Signed-off-by: Julia Lawall --- arch/mips/nxp/pnx8550/common/time.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/mips/nxp/pnx8550/common/time.c b/arch/mips/nxp/pnx8550/common/time.c index 8df43e9..18b1927 100644 --- a/arch/mips/nxp/pnx8550/common/time.c +++ b/arch/mips/nxp/pnx8550/common/time.c @@ -138,7 +138,7 @@ __init void plat_time_init(void) * HZ timer interrupts per second. */ mips_hpt_frequency = 27UL * ((1000000UL * n)/(m * pow2p)); - cpj = (mips_hpt_frequency + HZ / 2) / HZ; + cpj = DIV_ROUND_CLOSEST(mips_hpt_frequency, HZ); write_c0_count(0); timer_ack(); From ralf@linux-mips.org Sun Aug 2 20:37:13 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 02 Aug 2009 20:37:20 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:42007 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492880AbZHBShN (ORCPT ); Sun, 2 Aug 2009 20:37:13 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id n72Ibgwv009068; Sun, 2 Aug 2009 19:37:42 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id n72IbeFZ009066; Sun, 2 Aug 2009 19:37:40 +0100 Date: Sun, 2 Aug 2009 19:37:40 +0100 From: Ralf Baechle To: Florian Fainelli Cc: linux-mips@linux-mips.org, Manuel Lauss Subject: Re: [PATCH] mtx-1: request button GPIO before setting its direction Message-ID: <20090802183740.GA9058@linux-mips.org> References: <200908012351.21059.florian@openwrt.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <200908012351.21059.florian@openwrt.org> User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23814 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Sat, Aug 01, 2009 at 11:51:20PM +0200, Florian Fainelli wrote: > From: Florian Fainelli > Date: Sat, 1 Aug 2009 23:51:20 +0200 > To: Ralf Baechle > Cc: linux-mips@linux-mips.org, Manuel Lauss > Subject: [PATCH] mtx-1: request button GPIO before setting its direction > Content-Type: text/plain; > charset="utf-8" > > This patch fixes the following warning at boot time: > WARNING: at drivers/gpio/gpiolib.c:83 0x8021d5e0() > autorequest GPIO-207 > Modules linked in: > Call Trace:[<8011e0ec>] 0x8011e0ec > [<80110a28>] 0x80110a28 > [<80110a28>] 0x80110a28 > [..snip..] > > The current code does not request the GPIO and attempts > to set its direction, which is a violation of the GPIO API. > This patch also unhardcode the GPIO we request and use > the one we defined in the button driver. Thanks, applied. Ralf From ralf@linux-mips.org Sun Aug 2 20:41:40 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 02 Aug 2009 20:41:47 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:36081 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492880AbZHBSlk (ORCPT ); Sun, 2 Aug 2009 20:41:40 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id n72IftTo009237; Sun, 2 Aug 2009 19:41:55 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id n72If5Q3009212; Sun, 2 Aug 2009 19:41:05 +0100 Date: Sun, 2 Aug 2009 19:41:05 +0100 From: Ralf Baechle To: Julia Lawall Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, kernel-janitors@vger.kernel.org Subject: Re: [PATCH 10/15] arch/mips: Use DIV_ROUND_CLOSEST Message-ID: <20090802184024.GB9058@linux-mips.org> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23815 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Sun, Aug 02, 2009 at 10:48:08AM +0200, Julia Lawall wrote: > > From: Julia Lawall > > The kernel.h macro DIV_ROUND_CLOSEST performs the computation (x + d/2)/d > but is perhaps more readable. Applied. Thanks Julia! Ralf From ralf@linux-mips.org Mon Aug 3 00:47:33 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 03 Aug 2009 00:47:40 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:36886 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1493098AbZHBWrd (ORCPT ); Mon, 3 Aug 2009 00:47:33 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id n72Mkufn018737; Sun, 2 Aug 2009 23:46:56 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id n72MkSx9018729; Sun, 2 Aug 2009 23:46:28 +0100 Date: Sun, 2 Aug 2009 23:46:28 +0100 From: Ralf Baechle To: Roel Kluin Cc: linux-mips@linux-mips.org, Andrew Morton Subject: Re: [PATCH] MIPS: Read buffer overflow Message-ID: <20090802224550.GA1064@linux-mips.org> References: <4A72E923.8070105@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <4A72E923.8070105@gmail.com> User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23816 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Fri, Jul 31, 2009 at 02:52:51PM +0200, Roel Kluin wrote: Thanks, applied! Ralf From ralf@linux-mips.org Mon Aug 3 10:41:24 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 03 Aug 2009 10:41:31 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:58572 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492204AbZHCIlY (ORCPT ); Mon, 3 Aug 2009 10:41:24 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id n738frbg030649; Mon, 3 Aug 2009 09:41:53 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id n738fqns030647; Mon, 3 Aug 2009 09:41:52 +0100 Date: Mon, 3 Aug 2009 09:41:52 +0100 From: Ralf Baechle To: David Daney Cc: linux-mips@linux-mips.org Subject: Re: [PATCH] MIPS: Octeon: Run IPI code with interrupts disabled. Message-ID: <20090803084152.GA30431@linux-mips.org> References: <1249075807-18619-1-git-send-email-ddaney@caviumnetworks.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1249075807-18619-1-git-send-email-ddaney@caviumnetworks.com> User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23817 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Fri, Jul 31, 2009 at 02:30:07PM -0700, David Daney wrote: > In mm/slab.c the function do_ccupdate_local requires that interrupts > be disabled. If they are not, we panic with CONFIG_DEBUG_SLAB. > > So we disable interrupts while processing IPIs. Also these are not > shared irqs, so get rid of the IRQF_SHARED flag. Yes, this one will ruin your day. Ralf From ralf@linux-mips.org Mon Aug 3 11:20:19 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 03 Aug 2009 11:20:26 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:41537 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492238AbZHCJUT (ORCPT ); Mon, 3 Aug 2009 11:20:19 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id n739KV0s008106; Mon, 3 Aug 2009 10:20:31 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id n739KUEj008090; Mon, 3 Aug 2009 10:20:30 +0100 Date: Mon, 3 Aug 2009 10:20:30 +0100 From: Ralf Baechle To: David VomLehn Cc: GCC Help Mailing List , Linux MIPS Mailing List Subject: Re: Relocation problem with MIPS kernel modules Message-ID: <20090803092030.GB30431@linux-mips.org> References: <20090730184923.GA27030@cuplxvomd02.corp.sa.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20090730184923.GA27030@cuplxvomd02.corp.sa.net> User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23818 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Thu, Jul 30, 2009 at 11:49:23AM -0700, David VomLehn wrote: > To: GCC Help Mailing List , > Linux MIPS Mailing List > Subject: Relocation problem with MIPS kernel modules > Content-Type: text/plain; charset=us-ascii > > I have a MIPS loadable kernel module that, when I try to insmod it, causes the > kernel to emit the message: > > module xyz: dangerous relocation > > This message appears in three different places in arch/mips/kernel/module.c, > but this one is coming from apply_r_mips_lo16_rel(). The module code at I'll change the messages to indicate the relocation type. > the location at which the error message is generated appears to be pretty > bland: > lw v0,28564(s1) > with the expected relocation type of R_MIPS_LO16. The relocation before it > is R_MIPS_HI16, as expected, but for a different symbol. Before *that* > is another R_MIPS_HI16 relocation entry for yet a third symbol. > > According to the MIPS ABI, for what it's worth, "Each relocation type of > R_MIPS_HI16 must have an associated R_MIPS_LO16 entry immediately following > it in the list of relocations." So, what's actually getting generated by > gcc and linker differs from the closest thing we have to an ABI of record for > MIPS processors. The GNU tools as an extension over the MIPS ABI allows an arbitrary number of R_MIPS_HI16 relocations to be followed by a R_MIPS_LO16 symbol. All relocations of this sequence must use the same symbol, of course. This is a very old extension; I think it predates the Linux/MIPS port. Ralf From dvomlehn@cisco.com Mon Aug 3 20:20:06 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 03 Aug 2009 20:20:12 +0200 (CEST) Received: from sj-iport-5.cisco.com ([171.68.10.87]:52552 "EHLO sj-iport-5.cisco.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1493342AbZHCSUG (ORCPT ); Mon, 3 Aug 2009 20:20:06 +0200 X-IronPort-Anti-Spam-Filtered: true X-IronPort-Anti-Spam-Result: ApoEAGvHdkqrR7MV/2dsb2JhbAC8LYgpjlwFhBiCNg X-IronPort-AV: E=Sophos;i="4.43,315,1246838400"; d="scan'208";a="88601563" Received: from sj-dkim-1.cisco.com ([171.71.179.21]) by sj-iport-5.cisco.com with ESMTP; 03 Aug 2009 18:19:58 +0000 Received: from sj-core-1.cisco.com (sj-core-1.cisco.com [171.71.177.237]) by sj-dkim-1.cisco.com (8.12.11/8.12.11) with ESMTP id n73IJwSx019412; Mon, 3 Aug 2009 11:19:58 -0700 Received: from cuplxvomd02.corp.sa.net ([64.101.20.155]) by sj-core-1.cisco.com (8.13.8/8.14.3) with ESMTP id n73IJwEj029315; Mon, 3 Aug 2009 18:19:58 GMT Date: Mon, 3 Aug 2009 11:19:58 -0700 From: David VomLehn To: Ralf Baechle Cc: GCC Help Mailing List , Linux MIPS Mailing List Subject: Re: Relocation problem with MIPS kernel modules Message-ID: <20090803181958.GA7009@cuplxvomd02.corp.sa.net> References: <20090730184923.GA27030@cuplxvomd02.corp.sa.net> <20090803092030.GB30431@linux-mips.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20090803092030.GB30431@linux-mips.org> User-Agent: Mutt/1.5.18 (2008-05-17) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; l=1630; t=1249323598; x=1250187598; c=relaxed/simple; s=sjdkim1004; h=Content-Type:From:Subject:Content-Transfer-Encoding:MIME-Version; d=cisco.com; i=dvomlehn@cisco.com; z=From:=20David=20VomLehn=20 |Subject:=20Re=3A=20Relocation=20problem=20with=20MIPS=20ke rnel=20modules |Sender:=20; bh=3C8FkEp8z1smxkIIQBRVbvhvmIWMqLZECLMFJs6HTUY=; b=uEDgULWT0+aYvLDz7aM8fMO2xlN3HoCpUjfCH4kdYYqqa6dUMua/h5l+X1 AkqcVd7Ysg4KfRak7lSe3ndeTcScWA77jPC+8AeOHGz55eOJQzXoVfig1OmZ 9MPUmT4z9AM0cit6sji79CJ94HoYpVxkgIwyPo2sU4m5cifxanOfQ=; Authentication-Results: sj-dkim-1; header.From=dvomlehn@cisco.com; dkim=pass ( sig from cisco.com/sjdkim1004 verified; ); Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23819 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dvomlehn@cisco.com Precedence: bulk X-list: linux-mips On Mon, Aug 03, 2009 at 10:20:30AM +0100, Ralf Baechle wrote: > On Thu, Jul 30, 2009 at 11:49:23AM -0700, David VomLehn wrote: > > > To: GCC Help Mailing List , > > Linux MIPS Mailing List > > Subject: Relocation problem with MIPS kernel modules > > Content-Type: text/plain; charset=us-ascii > > > > I have a MIPS loadable kernel module that, when I try to insmod it, causes the > > kernel to emit the message: > > > > module xyz: dangerous relocation ... > > According to the MIPS ABI, for what it's worth, "Each relocation type of > > R_MIPS_HI16 must have an associated R_MIPS_LO16 entry immediately following > > it in the list of relocations." So, what's actually getting generated by > > gcc and linker differs from the closest thing we have to an ABI of record for > > MIPS processors. > > The GNU tools as an extension over the MIPS ABI allows an arbitrary number of > R_MIPS_HI16 relocations to be followed by a R_MIPS_LO16 symbol. All > relocations of this sequence must use the same symbol, of course. This is > a very old extension; I think it predates the Linux/MIPS port. Perhaps a foolish question, but is this documented anywhere? I know there is a a document over at http://gcc.gnu.org/gcc-3.4/mips-abi.html addressing some other MIPS ABI changes, but I didn't see this one. Obviously, we could put documentation on the linux-mips Wiki, with pointers to other documents, but I'm not sure this is the right place. I'm also concerned there could be other ABI changes/extensions that need to be included. > Ralf David From David.Daney@caviumnetworks.com Mon Aug 3 20:44:58 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 03 Aug 2009 20:45:04 +0200 (CEST) Received: from smtp2.caviumnetworks.com ([209.113.159.134]:9248 "EHLO smtp2.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1493346AbZHCSo6 (ORCPT ); Mon, 3 Aug 2009 20:44:58 +0200 Received: from maexch1.caveonetworks.com (Not Verified[192.168.14.20]) by smtp2.caviumnetworks.com with MailMarshal (v6,5,4,7535) id ; Mon, 03 Aug 2009 14:44:36 -0400 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by maexch1.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Mon, 3 Aug 2009 14:44:56 -0400 Received: from dd1.caveonetworks.com ([64.169.86.201]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Mon, 3 Aug 2009 11:44:55 -0700 Message-ID: <4A773026.3030002@caviumnetworks.com> Date: Mon, 03 Aug 2009 11:44:54 -0700 From: David Daney User-Agent: Thunderbird 2.0.0.21 (X11/20090320) MIME-Version: 1.0 To: David VomLehn CC: Ralf Baechle , GCC Help Mailing List , Linux MIPS Mailing List Subject: Re: Relocation problem with MIPS kernel modules References: <20090730184923.GA27030@cuplxvomd02.corp.sa.net> <20090803092030.GB30431@linux-mips.org> <20090803181958.GA7009@cuplxvomd02.corp.sa.net> In-Reply-To: <20090803181958.GA7009@cuplxvomd02.corp.sa.net> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 03 Aug 2009 18:44:55.0028 (UTC) FILETIME=[7E39B340:01CA146A] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23820 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips David VomLehn wrote: > On Mon, Aug 03, 2009 at 10:20:30AM +0100, Ralf Baechle wrote: >> On Thu, Jul 30, 2009 at 11:49:23AM -0700, David VomLehn wrote: >> >>> To: GCC Help Mailing List , >>> Linux MIPS Mailing List >>> Subject: Relocation problem with MIPS kernel modules >>> Content-Type: text/plain; charset=us-ascii >>> >>> I have a MIPS loadable kernel module that, when I try to insmod it, causes the >>> kernel to emit the message: >>> >>> module xyz: dangerous relocation > ... >>> According to the MIPS ABI, for what it's worth, "Each relocation type of >>> R_MIPS_HI16 must have an associated R_MIPS_LO16 entry immediately following >>> it in the list of relocations." So, what's actually getting generated by >>> gcc and linker differs from the closest thing we have to an ABI of record for >>> MIPS processors. >> The GNU tools as an extension over the MIPS ABI allows an arbitrary number of >> R_MIPS_HI16 relocations to be followed by a R_MIPS_LO16 symbol. All >> relocations of this sequence must use the same symbol, of course. This is >> a very old extension; I think it predates the Linux/MIPS port. > > Perhaps a foolish question, but is this documented anywhere? What more documentation do you need? It's obvious if you read bfd/elf{32,64,xx}-mips.c :-). David Daney From ralf@linux-mips.org Mon Aug 3 21:14:02 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 03 Aug 2009 21:14:10 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:35917 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1493354AbZHCTOC (ORCPT ); Mon, 3 Aug 2009 21:14:02 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id n73JEFrQ023240; Mon, 3 Aug 2009 20:14:16 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id n73JEEEu023238; Mon, 3 Aug 2009 20:14:14 +0100 Date: Mon, 3 Aug 2009 20:14:14 +0100 From: Ralf Baechle To: David Daney Cc: David VomLehn , GCC Help Mailing List , Linux MIPS Mailing List Subject: Re: Relocation problem with MIPS kernel modules Message-ID: <20090803191413.GA22543@linux-mips.org> References: <20090730184923.GA27030@cuplxvomd02.corp.sa.net> <20090803092030.GB30431@linux-mips.org> <20090803181958.GA7009@cuplxvomd02.corp.sa.net> <4A773026.3030002@caviumnetworks.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <4A773026.3030002@caviumnetworks.com> User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23821 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Mon, Aug 03, 2009 at 11:44:54AM -0700, David Daney wrote: >>> R_MIPS_HI16 relocations to be followed by a R_MIPS_LO16 symbol. All >>> relocations of this sequence must use the same symbol, of course. This is >>> a very old extension; I think it predates the Linux/MIPS port. >> >> Perhaps a foolish question, but is this documented anywhere? > > What more documentation do you need? It's obvious if you read > bfd/elf{32,64,xx}-mips.c :-). David ist (unforutunately ...) right. I don't think this is documented anywhere. I also only learned it from reading the binutils sources. Ralf From David.Daney@caviumnetworks.com Mon Aug 3 21:34:22 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 03 Aug 2009 21:34:28 +0200 (CEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:49809 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1493354AbZHCTeV (ORCPT ); Mon, 3 Aug 2009 21:34:21 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,2,2,3503) id ; Mon, 03 Aug 2009 15:33:45 -0400 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Mon, 3 Aug 2009 12:33:25 -0700 Received: from dd1.caveonetworks.com ([64.169.86.201]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Mon, 3 Aug 2009 12:33:25 -0700 Message-ID: <4A773B85.6010004@caviumnetworks.com> Date: Mon, 03 Aug 2009 12:33:25 -0700 From: David Daney User-Agent: Thunderbird 2.0.0.21 (X11/20090320) MIME-Version: 1.0 To: Ralf Baechle CC: David VomLehn , GCC Help Mailing List , Linux MIPS Mailing List Subject: Re: Relocation problem with MIPS kernel modules References: <20090730184923.GA27030@cuplxvomd02.corp.sa.net> <20090803092030.GB30431@linux-mips.org> In-Reply-To: <20090803092030.GB30431@linux-mips.org> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 03 Aug 2009 19:33:25.0437 (UTC) FILETIME=[44F6DED0:01CA1471] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23822 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Ralf Baechle wrote: > On Thu, Jul 30, 2009 at 11:49:23AM -0700, David VomLehn wrote: > >> To: GCC Help Mailing List , >> Linux MIPS Mailing List >> Subject: Relocation problem with MIPS kernel modules >> Content-Type: text/plain; charset=us-ascii >> >> I have a MIPS loadable kernel module that, when I try to insmod it, causes the >> kernel to emit the message: >> >> module xyz: dangerous relocation >> >> This message appears in three different places in arch/mips/kernel/module.c, >> but this one is coming from apply_r_mips_lo16_rel(). The module code at > > I'll change the messages to indicate the relocation type. > >> the location at which the error message is generated appears to be pretty >> bland: >> lw v0,28564(s1) >> with the expected relocation type of R_MIPS_LO16. The relocation before it >> is R_MIPS_HI16, as expected, but for a different symbol. Before *that* >> is another R_MIPS_HI16 relocation entry for yet a third symbol. >> >> According to the MIPS ABI, for what it's worth, "Each relocation type of >> R_MIPS_HI16 must have an associated R_MIPS_LO16 entry immediately following >> it in the list of relocations." So, what's actually getting generated by >> gcc and linker differs from the closest thing we have to an ABI of record for >> MIPS processors. > > The GNU tools as an extension over the MIPS ABI allows an arbitrary number of > R_MIPS_HI16 relocations to be followed by a R_MIPS_LO16 symbol. All > relocations of this sequence must use the same symbol, of course. This is > a very old extension; I think it predates the Linux/MIPS port. > Actually I think it is the opposite: RELOCATION RECORDS FOR [.text]: OFFSET TYPE VALUE 00000000 R_MIPS_HI16 .bss+0x00000004 00000008 R_MIPS_LO16 .bss+0x00000004 00000014 R_MIPS_LO16 .bss+0x00000004 We load the hi16 value into a register and then use multiple lo16 offsets for the follow loads and stores to the same location. On a read-modify-write we only want to load the base address one time. David Daney From dvomlehn@cisco.com Mon Aug 3 22:15:37 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 03 Aug 2009 22:15:43 +0200 (CEST) Received: from sj-iport-1.cisco.com ([171.71.176.70]:53109 "EHLO sj-iport-1.cisco.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1493370AbZHCUPh (ORCPT ); Mon, 3 Aug 2009 22:15:37 +0200 X-IronPort-Anti-Spam-Filtered: true X-IronPort-Anti-Spam-Result: ApoEAAXidkqrR7O6/2dsb2JhbAC7XogpjnAFhBg X-IronPort-AV: E=Sophos;i="4.43,316,1246838400"; d="scan'208";a="222790481" Received: from sj-dkim-2.cisco.com ([171.71.179.186]) by sj-iport-1.cisco.com with ESMTP; 03 Aug 2009 20:15:21 +0000 Received: from sj-core-4.cisco.com (sj-core-4.cisco.com [171.68.223.138]) by sj-dkim-2.cisco.com (8.12.11/8.12.11) with ESMTP id n73KFLIv008779; Mon, 3 Aug 2009 13:15:21 -0700 Received: from cuplxvomd02.corp.sa.net ([64.101.20.155]) by sj-core-4.cisco.com (8.13.8/8.14.3) with ESMTP id n73KFLNm010931; Mon, 3 Aug 2009 20:15:21 GMT Date: Mon, 3 Aug 2009 13:15:21 -0700 From: David VomLehn To: David Daney Cc: Ralf Baechle , GCC Help Mailing List , Linux MIPS Mailing List Subject: Re: Relocation problem with MIPS kernel modules Message-ID: <20090803201521.GA24691@cuplxvomd02.corp.sa.net> References: <20090730184923.GA27030@cuplxvomd02.corp.sa.net> <20090803092030.GB30431@linux-mips.org> <4A773B85.6010004@caviumnetworks.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <4A773B85.6010004@caviumnetworks.com> User-Agent: Mutt/1.5.18 (2008-05-17) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; l=1679; t=1249330521; x=1250194521; c=relaxed/simple; s=sjdkim2002; h=Content-Type:From:Subject:Content-Transfer-Encoding:MIME-Version; d=cisco.com; i=dvomlehn@cisco.com; z=From:=20David=20VomLehn=20 |Subject:=20Re=3A=20Relocation=20problem=20with=20MIPS=20ke rnel=20modules |Sender:=20; bh=BwBoOYZ+vAhB+JoOza2wTtXVaHbwKtUkr8bFGcLJrbc=; b=SOeBVKorXGsXUOXnGJpcu1PJAGV+hEa0VkSvYdchQwp800eQ2GQgBNIzFp fqPCCMpqz6cELYqnxxZu101XJdnkLgLVUDzCQEfEztCuRfbsAOk78RZWfetx WIUaQpRCqj; Authentication-Results: sj-dkim-2; header.From=dvomlehn@cisco.com; dkim=pass ( sig from cisco.com/sjdkim2002 verified; ); Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23823 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dvomlehn@cisco.com Precedence: bulk X-list: linux-mips On Mon, Aug 03, 2009 at 12:33:25PM -0700, David Daney wrote: > Ralf Baechle wrote: >> On Thu, Jul 30, 2009 at 11:49:23AM -0700, David VomLehn wrote: >> >>> To: GCC Help Mailing List , >>> Linux MIPS Mailing List >>> Subject: Relocation problem with MIPS kernel modules >>> Content-Type: text/plain; charset=us-ascii >>> >>> I have a MIPS loadable kernel module that, when I try to insmod it, causes the >>> kernel to emit the message: >>> >>> module xyz: dangerous relocation ... >> >> The GNU tools as an extension over the MIPS ABI allows an arbitrary number of >> R_MIPS_HI16 relocations to be followed by a R_MIPS_LO16 symbol. All >> relocations of this sequence must use the same symbol, of course. This is >> a very old extension; I think it predates the Linux/MIPS port. >> > > Actually I think it is the opposite: > > RELOCATION RECORDS FOR [.text]: > OFFSET TYPE VALUE > 00000000 R_MIPS_HI16 .bss+0x00000004 > 00000008 R_MIPS_LO16 .bss+0x00000004 > 00000014 R_MIPS_LO16 .bss+0x00000004 > > We load the hi16 value into a register and then use multiple lo16 > offsets for the follow loads and stores to the same location. On a > read-modify-write we only want to load the base address one time. This particular case is covered by the old MIPS Processor psABI: R_MIPS_LO16 entries without an R_MIPS_HI16 entry immediately preceding are orphaned and the previously defined R_MIPS_HI16 is used for computing the addend. The code in module.c looks like it implements the extension to which Ralf refers. > David Daney David VomLehn From ralf@linux-mips.org Tue Aug 4 01:55:23 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 04 Aug 2009 01:55:30 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:54311 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1491919AbZHCXzX (ORCPT ); Tue, 4 Aug 2009 01:55:23 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id n73NtbLt028774; Tue, 4 Aug 2009 00:55:37 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id n73NtaE4028772; Tue, 4 Aug 2009 00:55:36 +0100 Date: Tue, 4 Aug 2009 00:55:36 +0100 From: Ralf Baechle To: David VomLehn Cc: David Daney , GCC Help Mailing List , Linux MIPS Mailing List Subject: Re: Relocation problem with MIPS kernel modules Message-ID: <20090803235536.GB22543@linux-mips.org> References: <20090730184923.GA27030@cuplxvomd02.corp.sa.net> <20090803092030.GB30431@linux-mips.org> <4A773B85.6010004@caviumnetworks.com> <20090803201521.GA24691@cuplxvomd02.corp.sa.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20090803201521.GA24691@cuplxvomd02.corp.sa.net> User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23824 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Mon, Aug 03, 2009 at 01:15:21PM -0700, David VomLehn wrote: > > Actually I think it is the opposite: > > > > RELOCATION RECORDS FOR [.text]: > > OFFSET TYPE VALUE > > 00000000 R_MIPS_HI16 .bss+0x00000004 > > 00000008 R_MIPS_LO16 .bss+0x00000004 > > 00000014 R_MIPS_LO16 .bss+0x00000004 > > > > We load the hi16 value into a register and then use multiple lo16 > > offsets for the follow loads and stores to the same location. On a > > read-modify-write we only want to load the base address one time. > > This particular case is covered by the old MIPS Processor psABI: > > R_MIPS_LO16 entries without an R_MIPS_HI16 entry immediately preceding > are orphaned and the previously defined R_MIPS_HI16 is used for > computing the addend. > > The code in module.c looks like it implements the extension to which Ralf > refers. Which is useful for for branch delay slot scheduling like: ... j 1f lui a0, %hi16(hello) ... j 1f lui a0, %hi16(hello) ... 1: jal printf addiu a0, %lo16(hello) hello: .asciz "hello, hola\n" The next and logical extension would be to permit multiple R_MIPS_LO16 records following a sequence of one or more R_MIPS_HI16 relocs as long as all relate to the same symbol - which would be simple to support in the kernel. Ralf From dvomlehn@cisco.com Tue Aug 4 04:18:10 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 04 Aug 2009 04:18:17 +0200 (CEST) Received: from sj-iport-6.cisco.com ([171.71.176.117]:36714 "EHLO sj-iport-6.cisco.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1491849AbZHDCSK (ORCPT ); Tue, 4 Aug 2009 04:18:10 +0200 X-IronPort-Anti-Spam-Filtered: true X-IronPort-Anti-Spam-Result: ApoEADc3d0qrR7PD/2dsb2JhbAC8PIgpjw8FgkCBWA X-IronPort-AV: E=Sophos;i="4.43,318,1246838400"; d="scan'208";a="359738060" Received: from sj-dkim-3.cisco.com ([171.71.179.195]) by sj-iport-6.cisco.com with ESMTP; 04 Aug 2009 02:18:01 +0000 Received: from sj-core-5.cisco.com (sj-core-5.cisco.com [171.71.177.238]) by sj-dkim-3.cisco.com (8.12.11/8.12.11) with ESMTP id n742I1jm009102; Mon, 3 Aug 2009 19:18:01 -0700 Received: from cuplxvomd02.corp.sa.net ([64.101.20.155]) by sj-core-5.cisco.com (8.13.8/8.14.3) with ESMTP id n742I08R001012; Tue, 4 Aug 2009 02:18:00 GMT Date: Mon, 3 Aug 2009 19:18:01 -0700 From: David VomLehn To: Ralf Baechle Cc: David Daney , GCC Help Mailing List , Linux MIPS Mailing List Subject: Re: Relocation problem with MIPS kernel modules Message-ID: <20090804021800.GA14627@cuplxvomd02.corp.sa.net> References: <20090730184923.GA27030@cuplxvomd02.corp.sa.net> <20090803092030.GB30431@linux-mips.org> <4A773B85.6010004@caviumnetworks.com> <20090803201521.GA24691@cuplxvomd02.corp.sa.net> <20090803235536.GB22543@linux-mips.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20090803235536.GB22543@linux-mips.org> User-Agent: Mutt/1.5.18 (2008-05-17) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; l=1809; t=1249352281; x=1250216281; c=relaxed/simple; s=sjdkim3002; h=Content-Type:From:Subject:Content-Transfer-Encoding:MIME-Version; d=cisco.com; i=dvomlehn@cisco.com; z=From:=20David=20VomLehn=20 |Subject:=20Re=3A=20Relocation=20problem=20with=20MIPS=20ke rnel=20modules |Sender:=20; bh=6w5qH6tFpo6FIo1bh7rrjStGktrnabyq0Oxoq+uewF4=; b=Vs1hvEHV0B9aS+StId072B4RpRhqGEC+R6Fvsx2X8Qlfuh4pss0c21q77Z Tpjo6bl3izhBaHbW+8JJWTfY+A2l2bblgOq9xzzNsdZXWCUqRTreHV60Fc+C 6A4INnBgQY; Authentication-Results: sj-dkim-3; header.From=dvomlehn@cisco.com; dkim=pass ( sig from cisco.com/sjdkim3002 verified; ); Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23825 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dvomlehn@cisco.com Precedence: bulk X-list: linux-mips On Tue, Aug 04, 2009 at 12:55:36AM +0100, Ralf Baechle wrote: > On Mon, Aug 03, 2009 at 01:15:21PM -0700, David VomLehn wrote: > > > > Actually I think it is the opposite: > > > > > > RELOCATION RECORDS FOR [.text]: > > > OFFSET TYPE VALUE > > > 00000000 R_MIPS_HI16 .bss+0x00000004 > > > 00000008 R_MIPS_LO16 .bss+0x00000004 > > > 00000014 R_MIPS_LO16 .bss+0x00000004 > > > > > > We load the hi16 value into a register and then use multiple lo16 > > > offsets for the follow loads and stores to the same location. On a > > > read-modify-write we only want to load the base address one time. > > > > This particular case is covered by the old MIPS Processor psABI: > > > > R_MIPS_LO16 entries without an R_MIPS_HI16 entry immediately preceding > > are orphaned and the previously defined R_MIPS_HI16 is used for > > computing the addend. > > > > The code in module.c looks like it implements the extension to which Ralf > > refers. > > Which is useful for for branch delay slot scheduling like: > > ... > j 1f > lui a0, %hi16(hello) > ... > j 1f > lui a0, %hi16(hello) > ... > 1: jal printf > addiu a0, %lo16(hello) > > hello: .asciz "hello, hola\n" > > The next and logical extension would be to permit multiple R_MIPS_LO16 > records following a sequence of one or more R_MIPS_HI16 relocs as long as > all relate to the same symbol - which would be simple to support in the > kernel. This is what the orphaned R_MIPS_LO16 entries mentioned in the psABI quote are all about. The existing relocation code handles this in most cases, but could be juiced up a bit to do the check to verify the symbols match between the current R_MIPS_LO16 entry and the last R_MIPS_HI16 entry. > Ralf David VomLehn From ralf@linux-mips.org Tue Aug 4 19:54:26 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 04 Aug 2009 19:54:34 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:48145 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1493090AbZHDRy0 (ORCPT ); Tue, 4 Aug 2009 19:54:26 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id n74Hsw1N022189; Tue, 4 Aug 2009 18:54:58 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id n74HsvSZ022185; Tue, 4 Aug 2009 18:54:57 +0100 Date: Tue, 4 Aug 2009 18:54:57 +0100 From: Ralf Baechle To: Tim Abbott Cc: Linux Kernel Mailing List , Sam Ravnborg , Anders Kaseorg , Nelson Elhage , linux-mips@linux-mips.org Subject: Re: [PATCH 1/3] mips: make page.h constants available to assembly. Message-ID: <20090804175457.GA20889@linux-mips.org> References: <1249073899-30145-1-git-send-email-tabbott@ksplice.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1249073899-30145-1-git-send-email-tabbott@ksplice.com> User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23826 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Fri, Jul 31, 2009 at 04:58:17PM -0400, Tim Abbott wrote: Thanks, whole series queued for 2.6.31. Ralf From ralf@linux-mips.org Tue Aug 4 20:26:56 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 04 Aug 2009 20:27:03 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:41528 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1493091AbZHDS04 (ORCPT ); Tue, 4 Aug 2009 20:26:56 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id n74IRSqM024535; Tue, 4 Aug 2009 19:27:29 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id n74IRRMG024532; Tue, 4 Aug 2009 19:27:27 +0100 Date: Tue, 4 Aug 2009 19:27:27 +0100 From: Ralf Baechle To: Atsushi Nemoto Cc: linux-mips@linux-mips.org Subject: Re: [PATCH] Fix HPAGE_SIZE redifinition Message-ID: <20090804182727.GC20889@linux-mips.org> References: <1247578629-23079-1-git-send-email-anemo@mba.ocn.ne.jp> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1247578629-23079-1-git-send-email-anemo@mba.ocn.ne.jp> User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23827 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Tue, Jul 14, 2009 at 10:37:09PM +0900, Atsushi Nemoto wrote: Thanks, applied. Ralf From f.fainelli@gmail.com Tue Aug 4 22:14:48 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 04 Aug 2009 22:14:55 +0200 (CEST) Received: from mail-ew0-f216.google.com ([209.85.219.216]:34758 "EHLO mail-ew0-f216.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1493219AbZHDUOs (ORCPT ); Tue, 4 Aug 2009 22:14:48 +0200 Received: by ewy12 with SMTP id 12so5329413ewy.0 for ; Tue, 04 Aug 2009 13:14:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:sender:from:date:subject :mime-version:x-uid:x-length:to:cc:content-type :content-transfer-encoding:content-disposition:message-id; bh=ZCiccbw7UyLTYrhvCl/Kv9USpi6cQ5rZ44Hk2b8R2QY=; b=c7BLSqMC9zEoYI091fpEY+v5vemvV/OlBR3XkTBE4fTA2doo1NvoXnqeCoCMcQwCOJ H3lF5VR9P3TYAuCaZ8z7tsZPbmNwIjlrEsW1FlST7nO7jbNdyJKrV9n/SX7bxiTwYKcg km9QtS0imSv90S9hmrDzldjOMkd7CVCm+PjNw= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:from:date:subject:mime-version:x-uid:x-length:to:cc :content-type:content-transfer-encoding:content-disposition :message-id; b=eViOqueMecAqgmqCUCs1wz51Tpw1o5i1QZzQLeD8xWoqeeOBqdHpAgY2CMgYNFzJpi 0sx+PNn5CL4+9hLFYFk0X4rKRlQYZOE4nxNzpyuGlkCGWhcL9I3+4/dtNEXtTTeH2+Dq +daoglAugWPM9Ieq8bTi1R3apwzvANS2UI7VE= Received: by 10.210.65.16 with SMTP id n16mr7142980eba.78.1249416882553; Tue, 04 Aug 2009 13:14:42 -0700 (PDT) Received: from florian (135.87.196-77.rev.gaoland.net [77.196.87.135]) by mx.google.com with ESMTPS id 28sm3074920eye.44.2009.08.04.13.14.41 (version=TLSv1/SSLv3 cipher=RC4-MD5); Tue, 04 Aug 2009 13:14:41 -0700 (PDT) From: Florian Fainelli Date: Tue, 4 Aug 2009 22:14:39 +0200 Subject: [PATCH] bcm63xx: fix build failures when CONFIG_PCI is disabled MIME-Version: 1.0 X-UID: 1112 X-Length: 3103 To: Ralf Baechle Cc: linux-mips@linux-mips.org, Maxime Bizon Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Content-Disposition: inline Message-Id: <200908042214.39866.florian@openwrt.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23828 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips This patch fixes multiple build failures when CONFIG_PCI is disabled. Since bcm63xx_sprom depends on CONFIG_SSB_PCIHOST to be set, which depends on CONFIG_PCI, bcm63xx_sprom would be unused thus causing this direct warning treated as an error: cc1: warnings being treated as errors arch/mips/bcm63xx/boards/board_bcm963xx.c:466: warning: 'bcm63xx_sprom' defined but not used Then bcm63xx_pci_enabled would not be resolved since it is declared in arch/mips/pci/pci-bcm63xx.c which is not compiled due to CONFIG_PCI being disabled. Finally, ssb_set_arch_fallback would not be resolved too, since CONFIG_SSB_PCIHOST is disabled. Signed-off-by: Florian Fainelli --- diff --git a/arch/mips/bcm63xx/boards/board_bcm963xx.c b/arch/mips/bcm63xx/boards/board_bcm963xx.c index 5add08b..683873d 100644 --- a/arch/mips/bcm63xx/boards/board_bcm963xx.c +++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c @@ -344,11 +344,13 @@ void __init board_prom_init(void) * inside arch_initcall */ val = 0; +#ifdef CONFIG_PCI if (board.has_pci) { bcm63xx_pci_enabled = 1; if (BCMCPU_IS_6348()) val |= GPIO_MODE_6348_G2_PCI; } +#endif if (board.has_pccard) { if (BCMCPU_IS_6348()) @@ -463,6 +465,7 @@ static struct platform_device mtd_dev = { * Register a sane SPROMv2 to make the on-board * bcm4318 WLAN work */ +#ifdef CONFIG_SSB_PCIHOST static struct ssb_sprom bcm63xx_sprom = { .revision = 0x02, .board_rev = 0x17, @@ -483,6 +486,7 @@ static struct ssb_sprom bcm63xx_sprom = { .boardflags_lo = 0x2848, .boardflags_hi = 0x0000, }; +#endif /* * third stage init callback, register all board devices. @@ -512,12 +516,14 @@ int __init board_register_devices(void) /* Generate MAC address for WLAN and * register our SPROM */ +#ifdef CONFIG_SSB_PCIHOST if (!board_get_mac_address(bcm63xx_sprom.il0mac)) { memcpy(bcm63xx_sprom.et0mac, bcm63xx_sprom.il0mac, ETH_ALEN); memcpy(bcm63xx_sprom.et1mac, bcm63xx_sprom.il0mac, ETH_ALEN); if (ssb_arch_set_fallback_sprom(&bcm63xx_sprom) < 0) printk(KERN_ERR "failed to register fallback SPROM\n"); } +#endif /* read base address of boot chip select (0) */ val = bcm_mpi_readl(MPI_CSBASE_REG(0)); From f.fainelli@gmail.com Tue Aug 4 22:52:50 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 04 Aug 2009 22:52:56 +0200 (CEST) Received: from mail-ew0-f216.google.com ([209.85.219.216]:33516 "EHLO mail-ew0-f216.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1493221AbZHDUwt (ORCPT ); Tue, 4 Aug 2009 22:52:49 +0200 Received: by ewy12 with SMTP id 12so5358211ewy.0 for ; Tue, 04 Aug 2009 13:52:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:sender:from:date:subject :mime-version:x-uid:x-length:to:cc:content-type :content-transfer-encoding:content-disposition:message-id; bh=xtQWb8HhG85u4wsk8TcRUU0J0z1npIHIn5m5jT4r+Oo=; b=xzHqjHOUhEEhl/ykL4BVj0SGJYsEfPU0LNJCy91LlRedMEZ5Gm2QGrxo5S/Hc52pvj Q7G05HJ2DStDSV3oocnzknAScnyM6vYAXRDDGUm2esBi995bMimseBMojCdOeoodACqw SIBtJQfK948wvO+tQiuBbDbF4SUkZ5FbhzSxY= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:from:date:subject:mime-version:x-uid:x-length:to:cc :content-type:content-transfer-encoding:content-disposition :message-id; b=HtnnDIwjECOyKTQ9F0UvLB0jKPnS4dbrrOX6hNhcksgDEqq4gaXF29vCxqYe5sNeff xVxVQa64NsQ8Lt1peCmWwMIGj5FprfKotNNMov+Cb+6zT7WMKcCum1TPNaaFogQA4sp9 QnxBhwZ1Av5DVfdEbZJtwQJeafK9KrD+kSq+Q= Received: by 10.210.44.12 with SMTP id r12mr9423326ebr.24.1249419164363; Tue, 04 Aug 2009 13:52:44 -0700 (PDT) Received: from florian (135.87.196-77.rev.gaoland.net [77.196.87.135]) by mx.google.com with ESMTPS id 10sm674108eyz.31.2009.08.04.13.52.43 (version=TLSv1/SSLv3 cipher=RC4-MD5); Tue, 04 Aug 2009 13:52:44 -0700 (PDT) From: Florian Fainelli Date: Tue, 4 Aug 2009 22:52:41 +0200 Subject: [PATCH 1/5] cpmac: fix wrong MDIO bus identifier MIME-Version: 1.0 X-UID: 1120 X-Length: 1945 To: Ralf Baechle Cc: linux-mips@linux-mips.org, netdev@vger.kernel.org, David Miller Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Content-Disposition: inline Message-Id: <200908042252.42254.florian@openwrt.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23829 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips This patch fixes the wrong MDIO bus identifier which was set to 0 unconditionaly, suitable for external switches while it is actually 1 for PHYs different than external switches which are autodetected. Signed-off-by: Florian Fainelli --- diff --git a/drivers/net/cpmac.c b/drivers/net/cpmac.c index fd5e32c..c951dd4 100644 --- a/drivers/net/cpmac.c +++ b/drivers/net/cpmac.c @@ -1109,7 +1109,7 @@ static int external_switch; static int __devinit cpmac_probe(struct platform_device *pdev) { int rc, phy_id; - char *mdio_bus_id = "0"; + char mdio_bus_id[BUS_ID_SIZE]; struct resource *mem; struct cpmac_priv *priv; struct net_device *dev; @@ -1127,7 +1127,7 @@ static int __devinit cpmac_probe(struct platform_device *pdev) if (phy_id == PHY_MAX_ADDR) { if (external_switch || dumb_switch) { - mdio_bus_id = 0; /* fixed phys bus */ + strncpy(mdio_bus_id, "0", BUS_ID_SIZE); /* fixed phys bus */ phy_id = pdev->id; } else { dev_err(&pdev->dev, "no PHY present\n"); @@ -1254,7 +1254,7 @@ int __devinit cpmac_init(void) } cpmac_mii->phy_mask = ~(mask | 0x80000000); - snprintf(cpmac_mii->id, MII_BUS_ID_SIZE, "0"); + snprintf(cpmac_mii->id, MII_BUS_ID_SIZE, "1"); res = mdiobus_register(cpmac_mii); if (res) From f.fainelli@gmail.com Tue Aug 4 22:53:14 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 04 Aug 2009 22:53:20 +0200 (CEST) Received: from mail-ew0-f216.google.com ([209.85.219.216]:33516 "EHLO mail-ew0-f216.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1493230AbZHDUww (ORCPT ); Tue, 4 Aug 2009 22:52:52 +0200 Received: by mail-ew0-f216.google.com with SMTP id 12so5358211ewy.0 for ; Tue, 04 Aug 2009 13:52:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:sender:from:date:subject :mime-version:x-uid:x-length:to:cc:content-type :content-transfer-encoding:content-disposition:message-id; bh=C0hZ8zo8gjhNmWS9qMO1Y0b7wIZ2hDvJ+HrFtvajZhw=; b=pBvPvexeg/PJVts3CKnBaMY+ucTDYDP4LyZlq53Yirrn06nGCO9rhgEk6UfJOw9sTX YdU+GXIMgKpM+i1OZ9IWD9hgmhOIRiYEY24j/TItp6mkBG236Ekz1BhTwurfkbUB3+X2 DSsXnn17w2iYQj2BsTZaZmY64yYs3c8iZ3riA= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:from:date:subject:mime-version:x-uid:x-length:to:cc :content-type:content-transfer-encoding:content-disposition :message-id; b=PpO2mVHCsqUCvzEFFUb+yyHfOJhYM4CVaY/A5r8PTl42pqAIBV8xC88BGoychYZM3B 6eSlCL7EAL2bB0Hn6/wKSQwpqM/YD5TJqY8u3/H2guY0qa65xdIC+r/HrsEZFCthRDCl EMZgynZXH+rBlzeUvDLyccZXFAYPX3Y857LMk= Received: by 10.210.86.1 with SMTP id j1mr9424416ebb.27.1249419170102; Tue, 04 Aug 2009 13:52:50 -0700 (PDT) Received: from florian (135.87.196-77.rev.gaoland.net [77.196.87.135]) by mx.google.com with ESMTPS id 5sm1445742eyf.48.2009.08.04.13.52.49 (version=TLSv1/SSLv3 cipher=RC4-MD5); Tue, 04 Aug 2009 13:52:49 -0700 (PDT) From: Florian Fainelli Date: Tue, 4 Aug 2009 22:52:47 +0200 Subject: [PATCH 2/5] ar7: add fixed PHY support for the two on-board cpmac MIME-Version: 1.0 X-UID: 1137 X-Length: 2327 To: Ralf Baechle Cc: linux-mips@linux-mips.org, netdev@vger.kernel.org, David Miller Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Content-Disposition: inline Message-Id: <200908042252.47549.florian@openwrt.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23830 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips This patch adds fixed PHY support for the two on-chip cpmac Ethernet adapters. Signed-off-by: Florian Fainelli --- diff --git a/arch/mips/ar7/platform.c b/arch/mips/ar7/platform.c index 5422449..c4737ce 100644 --- a/arch/mips/ar7/platform.c +++ b/arch/mips/ar7/platform.c @@ -33,6 +33,8 @@ #include #include #include +#include +#include #include #include @@ -209,6 +211,12 @@ static struct physmap_flash_data physmap_flash_data = { .width = 2, }; +static struct fixed_phy_status fixed_phy_status __initdata = { + .link = 1, + .speed = 100, + .duplex = 1, +}; + static struct plat_cpmac_data cpmac_low_data = { .reset_bit = 17, .power_bit = 20, @@ -530,6 +538,9 @@ static int __init ar7_register_devices(void) } if (ar7_has_high_cpmac()) { + res = fixed_phy_add(PHY_POLL, cpmac_high.id, &fixed_phy_status); + if (res && res != -ENODEV) + return res; cpmac_get_mac(1, cpmac_high_data.dev_addr); res = platform_device_register(&cpmac_high); if (res) @@ -538,6 +549,10 @@ static int __init ar7_register_devices(void) cpmac_low_data.phy_mask = 0xffffffff; } + res = fixed_phy_add(PHY_POLL, cpmac_low.id, &fixed_phy_status); + if (res && res != -ENODEV) + return res; + cpmac_get_mac(0, cpmac_low_data.dev_addr); res = platform_device_register(&cpmac_low); if (res) From f.fainelli@gmail.com Tue Aug 4 22:53:38 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 04 Aug 2009 22:53:45 +0200 (CEST) Received: from mail-ew0-f216.google.com ([209.85.219.216]:33516 "EHLO mail-ew0-f216.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1493238AbZHDUwz (ORCPT ); Tue, 4 Aug 2009 22:52:55 +0200 Received: by mail-ew0-f216.google.com with SMTP id 12so5358211ewy.0 for ; Tue, 04 Aug 2009 13:52:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:sender:from:date:subject :mime-version:x-uid:x-length:to:cc:content-type :content-transfer-encoding:content-disposition:message-id; bh=fwNcuhp3fK4B9Pxtb2MokBAolkvEYbexfYGXd63btec=; b=w/j2aq0fvjasQYECeYs1HTnT56DcTtJD45OAZRFxBRChC8+AWJoUY0Oqm+SkPUCHEU vnxbDTzbELVb6rQzM4f5M1hmZGsJ1D8t1g+k/cdTbz4rNklVXG+lhHmk/V/jv3fpu+TV V248m8plRrb2vXIsS7uubVdRRL5okGJszYvz4= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:from:date:subject:mime-version:x-uid:x-length:to:cc :content-type:content-transfer-encoding:content-disposition :message-id; b=duDKoLA3YUkpCLfS5nggebBPWofgP229YQHuVXVuOhStspxfzaySGLVrqTkS5I0a/T LlrnAhHBScvUkeuahxyJmDWySDmZg3Ae4Jqs3O9VN8HJgAvNrKqEH5HJIZgtu2Djv/lj W+GCYO0afNW57Lcmk+hS7nwcpWLX9FXUCAYC0= Received: by 10.210.44.12 with SMTP id r12mr9423505ebr.24.1249419174843; Tue, 04 Aug 2009 13:52:54 -0700 (PDT) Received: from florian (135.87.196-77.rev.gaoland.net [77.196.87.135]) by mx.google.com with ESMTPS id 10sm4361889eyz.21.2009.08.04.13.52.54 (version=TLSv1/SSLv3 cipher=RC4-MD5); Tue, 04 Aug 2009 13:52:54 -0700 (PDT) From: Florian Fainelli Date: Tue, 4 Aug 2009 22:52:52 +0200 Subject: [PATCH 3/5] cpmac: add support for fixed PHY MIME-Version: 1.0 X-UID: 1121 X-Length: 2954 To: Ralf Baechle Cc: linux-mips@linux-mips.org, netdev@vger.kernel.org, David Miller Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Content-Disposition: inline Message-Id: <200908042252.53068.florian@openwrt.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23831 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips This patch adds support for fixed PHY connected in MII mode to cpmac. We allow external and dumb_switch module parameters to override the PHY detection process since they are always connected with MDIO bus identifier 0. This lets fixed PHYs to be detected correctly and be connected to the their corresponding MDIO bus identifier. Signed-off-by: Florian Fainelli --- diff --git a/drivers/net/cpmac.c b/drivers/net/cpmac.c index c951dd4..f2fc722 100644 --- a/drivers/net/cpmac.c +++ b/drivers/net/cpmac.c @@ -1117,22 +1117,23 @@ static int __devinit cpmac_probe(struct platform_device *pdev) pdata = pdev->dev.platform_data; - for (phy_id = 0; phy_id < PHY_MAX_ADDR; phy_id++) { - if (!(pdata->phy_mask & (1 << phy_id))) - continue; - if (!cpmac_mii->phy_map[phy_id]) - continue; - break; + if (external_switch || dumb_switch) { + strncpy(mdio_bus_id, "0", BUS_ID_SIZE); /* fixed phys bus */ + phy_id = pdev->id; + } else { + for (phy_id = 0; phy_id < PHY_MAX_ADDR; phy_id++) { + if (!(pdata->phy_mask & (1 << phy_id))) + continue; + if (!cpmac_mii->phy_map[phy_id]) + continue; + strncpy(mdio_bus_id, cpmac_mii->id, BUS_ID_SIZE); + break; + } } if (phy_id == PHY_MAX_ADDR) { - if (external_switch || dumb_switch) { - strncpy(mdio_bus_id, "0", BUS_ID_SIZE); /* fixed phys bus */ - phy_id = pdev->id; - } else { - dev_err(&pdev->dev, "no PHY present\n"); - return -ENODEV; - } + dev_err(&pdev->dev, "no PHY present\n"); + return -ENODEV; } dev = alloc_etherdev_mq(sizeof(*priv), CPMAC_QUEUES); @@ -1166,8 +1167,11 @@ static int __devinit cpmac_probe(struct platform_device *pdev) priv->msg_enable = netif_msg_init(debug_level, 0xff); memcpy(dev->dev_addr, pdata->dev_addr, sizeof(dev->dev_addr)); - priv->phy = phy_connect(dev, dev_name(&cpmac_mii->phy_map[phy_id]->dev), - &cpmac_adjust_link, 0, PHY_INTERFACE_MODE_MII); + snprintf(priv->phy_name, BUS_ID_SIZE, PHY_ID_FMT, mdio_bus_id, phy_id); + + priv->phy = phy_connect(dev, priv->phy_name, &cpmac_adjust_link, 0, + PHY_INTERFACE_MODE_MII); + if (IS_ERR(priv->phy)) { if (netif_msg_drv(priv)) printk(KERN_ERR "%s: Could not attach to PHY\n", From f.fainelli@gmail.com Tue Aug 4 22:54:02 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 04 Aug 2009 22:54:09 +0200 (CEST) Received: from mail-ew0-f216.google.com ([209.85.219.216]:33516 "EHLO mail-ew0-f216.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1493245AbZHDUxB (ORCPT ); Tue, 4 Aug 2009 22:53:01 +0200 Received: by mail-ew0-f216.google.com with SMTP id 12so5358211ewy.0 for ; Tue, 04 Aug 2009 13:53:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:sender:from:date:subject :mime-version:x-uid:x-length:to:cc:content-type :content-transfer-encoding:content-disposition:message-id; bh=Pus7d8m17fZ7RFdD29x1dlmrpZPtsZ2QMPFIimTDFb0=; b=VQkfXmMI/o7e3N55kARorppyS1XxWdKzSZvMY1Km0kwVRp7lNAtmJBYmHmfgBIjqwV 4BMiP1kOlEsymbt7wxlU7bPssipfzCetOid99GcmTpWb82OcBd7uAy635YIQ7LyLoifl fNDn1A0DHy5ae+faX17EhFmmNibGZxgzmrOTU= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:from:date:subject:mime-version:x-uid:x-length:to:cc :content-type:content-transfer-encoding:content-disposition :message-id; b=YLu+ZM7wQ8/SFh8dhXkOk8zKxqz45RBODCtT5mvQomGMipooSHg1BIWy+N2nM4V1Pl aqeGLoFheHUEqS1TSCqBh8WWTY15wS6taxhMykXDrYZO+rivZzrlEgrpoNB1ZsSmTGry pCRjLTr3mQ/Zot24HOdMbj3nvLZkSMJ4GKIQ0= Received: by 10.210.87.14 with SMTP id k14mr9439942ebb.90.1249419181428; Tue, 04 Aug 2009 13:53:01 -0700 (PDT) Received: from florian (135.87.196-77.rev.gaoland.net [77.196.87.135]) by mx.google.com with ESMTPS id 28sm3160484eye.44.2009.08.04.13.53.00 (version=TLSv1/SSLv3 cipher=RC4-MD5); Tue, 04 Aug 2009 13:53:01 -0700 (PDT) From: Florian Fainelli Date: Tue, 4 Aug 2009 22:52:57 +0200 Subject: [PATCH 4/5] cpmac: wait longer after MDIO reset MIME-Version: 1.0 X-UID: 1122 X-Length: 1452 To: Ralf Baechle Cc: linux-mips@linux-mips.org, netdev@vger.kernel.org, David Miller Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Content-Disposition: inline Message-Id: <200908042252.57848.florian@openwrt.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23832 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips This patch slows down the MDIO_ALIVE busy waiting to let switches and PHY come up after reset. Previous loop was too quick for IC+175C and ADM6996C/L switches to come up. Signed-off-by: Florian Fainelli --- diff --git a/drivers/net/cpmac.c b/drivers/net/cpmac.c index f2fc722..12a521e 100644 --- a/drivers/net/cpmac.c +++ b/drivers/net/cpmac.c @@ -1245,11 +1245,11 @@ int __devinit cpmac_init(void) cpmac_mii->reset(cpmac_mii); - for (i = 0; i < 300000; i++) + for (i = 0; i < 300; i++) if ((mask = cpmac_read(cpmac_mii->priv, CPMAC_MDIO_ALIVE))) break; else - cpu_relax(); + msleep(10); mask &= 0x7fffffff; if (mask & (mask - 1)) { From f.fainelli@gmail.com Tue Aug 4 22:54:27 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 04 Aug 2009 22:54:34 +0200 (CEST) Received: from mail-ew0-f216.google.com ([209.85.219.216]:33516 "EHLO mail-ew0-f216.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1493246AbZHDUxC (ORCPT ); Tue, 4 Aug 2009 22:53:02 +0200 Received: by mail-ew0-f216.google.com with SMTP id 12so5358211ewy.0 for ; Tue, 04 Aug 2009 13:53:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:sender:from:date:subject :mime-version:x-uid:x-length:to:cc:content-type :content-transfer-encoding:content-disposition:message-id; bh=xZKilqz1apxCCbFsQ4q8gEZ+/abUd52aQXnmBLLTulA=; b=Twhs/h9d4zqgfcI7V+4Aoe42NQV0vCQ7PC5kT0iArcLrkdSwR+UUv5BMUqXndkal4v 0wvEvQZ7tIZ1Jhun0NFbkA5UGGX1150yz9gdEMRGD6o5y1ECmQNbYBbs32WWvZRUX6Oy ctL/TrUeyhEUc9+odoGXC6H1tF0PMy/Q+Cfzc= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:from:date:subject:mime-version:x-uid:x-length:to:cc :content-type:content-transfer-encoding:content-disposition :message-id; b=vmGdKj+WaYmiQSzOAaqrcqkpu+jYhucbn+E/saj4E+o0lrgfmLIbQ2xHKEZV7HJxJO tHp0TBhIVuGXwRNtuKOHvC6l0SoqGIhw8xarcFwRFzkRyHGgYfkz1N8vlB7J1XHaqFE8 lwFloJRrxBaJMMiXGw78KWC5rheha439kEjmk= Received: by 10.210.105.12 with SMTP id d12mr9179485ebc.53.1249419182020; Tue, 04 Aug 2009 13:53:02 -0700 (PDT) Received: from florian (135.87.196-77.rev.gaoland.net [77.196.87.135]) by mx.google.com with ESMTPS id 28sm3160484eye.44.2009.08.04.13.53.01 (version=TLSv1/SSLv3 cipher=RC4-MD5); Tue, 04 Aug 2009 13:53:01 -0700 (PDT) From: Florian Fainelli Date: Tue, 4 Aug 2009 22:53:00 +0200 Subject: [PATCH 5/5] cpmac: bump version to 0.5.1 MIME-Version: 1.0 X-UID: 1123 X-Length: 1299 To: Ralf Baechle Cc: linux-mips@linux-mips.org, netdev@vger.kernel.org, David Miller Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Content-Disposition: inline Message-Id: <200908042253.00563.florian@openwrt.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23833 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips Signed-off-by: Florian Fainelli --- diff --git a/drivers/net/cpmac.c b/drivers/net/cpmac.c index 12a521e..0ef7467 100644 --- a/drivers/net/cpmac.c +++ b/drivers/net/cpmac.c @@ -54,7 +54,7 @@ module_param(dumb_switch, int, 0444); MODULE_PARM_DESC(debug_level, "Number of NETIF_MSG bits to enable"); MODULE_PARM_DESC(dumb_switch, "Assume switch is not connected to MDIO bus"); -#define CPMAC_VERSION "0.5.0" +#define CPMAC_VERSION "0.5.1" /* frame size + 802.1q tag */ #define CPMAC_SKB_SIZE (ETH_FRAME_LEN + 4) #define CPMAC_QUEUES 8 From f.fainelli@gmail.com Tue Aug 4 23:09:44 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 04 Aug 2009 23:09:51 +0200 (CEST) Received: from mail-ew0-f216.google.com ([209.85.219.216]:61746 "EHLO mail-ew0-f216.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1493206AbZHDVJo (ORCPT ); Tue, 4 Aug 2009 23:09:44 +0200 Received: by ewy12 with SMTP id 12so5371125ewy.0 for ; Tue, 04 Aug 2009 14:09:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:sender:from:date:subject :mime-version:x-uid:x-length:to:cc:content-type :content-transfer-encoding:content-disposition:message-id; bh=eS/OWK3+wDWq7Xy8FqzibW030xcVvpJlJIOzK0m8/Lg=; b=GhnNldHMs1vxA491dye1iFc6/hhWcUNtZMup52VhEAkSpbNp5VoAuDes+Vz8UjJhhE WvySmuh+/P/MGzky2OYDendIgmHCKc7TfPh/bBc3Mr26J3qPqjc4hJdbDBp7e2Z4yvln lwqpMcXDw86YuO7z4/La6f4RU6xpjwni9RMJU= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:from:date:subject:mime-version:x-uid:x-length:to:cc :content-type:content-transfer-encoding:content-disposition :message-id; b=LsYxBzu67yg5N+ZYBPsRFSeYUHI5M3KtqSRGNUvqF7RWFkn1K6mtCCop1Nv8UfttYH XbXkImMfbuPvVyeyj6uSF2si/+K1WKxgLo5n2MgYHHvQSqAGJr7qeDV9bndrxWSi9ZJ7 iNSFAqIti3F/FeMc2lq4u4Rsp0LI0e9rJC8MQ= Received: by 10.210.118.14 with SMTP id q14mr9399068ebc.74.1249420179198; Tue, 04 Aug 2009 14:09:39 -0700 (PDT) Received: from florian (135.87.196-77.rev.gaoland.net [77.196.87.135]) by mx.google.com with ESMTPS id 7sm730121eyg.55.2009.08.04.14.09.38 (version=TLSv1/SSLv3 cipher=RC4-MD5); Tue, 04 Aug 2009 14:09:38 -0700 (PDT) From: Florian Fainelli Date: Tue, 4 Aug 2009 23:09:36 +0200 Subject: [PATCH] ar7: register watchdog driver only if enabled in hardware configuration MIME-Version: 1.0 X-UID: 1152 X-Length: 2294 To: Ralf Baechle Cc: linux-mips@linux-mips.org Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Content-Disposition: inline Message-Id: <200908042309.36721.florian@openwrt.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23834 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips This patch checks if the watchdog enable bit is set in the DCL register meaning that the hardware watchdog actually works and if so, register the ar7_wdt platform_device. Signed-off-by: Florian Fainelli --- diff --git a/arch/mips/ar7/platform.c b/arch/mips/ar7/platform.c index e2278c0..835f3f0 100644 --- a/arch/mips/ar7/platform.c +++ b/arch/mips/ar7/platform.c @@ -503,6 +503,7 @@ static int __init ar7_register_devices(void) { u16 chip_id; int res; + u32 *bootcr, val; #ifdef CONFIG_SERIAL_8250 static struct uart_port uart_port[2]; @@ -595,7 +596,13 @@ static int __init ar7_register_devices(void) ar7_wdt_res.end = ar7_wdt_res.start + 0x20; - res = platform_device_register(&ar7_wdt); + bootcr = (u32 *)ioremap_nocache(AR7_REGS_DCL, 4); + val = *bootcr; + iounmap(bootcr); + + /* Register watchdog only if enabled in hardware */ + if (val & AR7_WDT_HW_ENA) + res = platform_device_register(&ar7_wdt); return res; } diff --git a/arch/mips/include/asm/mach-ar7/ar7.h b/arch/mips/include/asm/mach-ar7/ar7.h index de71694..21cbbc7 100644 --- a/arch/mips/include/asm/mach-ar7/ar7.h +++ b/arch/mips/include/asm/mach-ar7/ar7.h @@ -78,6 +78,9 @@ #define AR7_REF_CLOCK 25000000 #define AR7_XTAL_CLOCK 24000000 +/* DCL */ +#define AR7_WDT_HW_ENA 0x10 + struct plat_cpmac_data { int reset_bit; int power_bit; From f.fainelli@gmail.com Tue Aug 4 23:17:58 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 04 Aug 2009 23:18:04 +0200 (CEST) Received: from mail-ew0-f216.google.com ([209.85.219.216]:53557 "EHLO mail-ew0-f216.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1493230AbZHDVR6 (ORCPT ); Tue, 4 Aug 2009 23:17:58 +0200 Received: by ewy12 with SMTP id 12so5377071ewy.0 for ; Tue, 04 Aug 2009 14:17:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:sender:from:date:subject :mime-version:x-uid:x-length:to:cc:content-type :content-transfer-encoding:content-disposition:message-id; bh=QHFcoNbUWZ2eOIC2I7ZbSHE3Zf++pAnchmmtoa6BW64=; b=XOyqR4ILvJO5f3wh1Xkn2BV/URxkXtZA3he5oxDA3TbmoFiVABFqW5z28VghR3wgvV /rtRVmyVjfNs30Q3h5Hy/x6+5WP68cOOA+/xIKRF+NsXdJIPrgBggcXDd0vf59CKWxOU gsNXKM0s4ZFCu+dJb/54ztHF09e1y8YRZ0vgI= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:from:date:subject:mime-version:x-uid:x-length:to:cc :content-type:content-transfer-encoding:content-disposition :message-id; b=KVYZ8t2KJ1UeJY4VdB2wpd6tnognb0q/9oYv7mN0pTW8I8gSXGgICTBIgCG0aDAnzo NTNr0IJnb5vHxj0OoBCem+EFew/qFYATHtEqvkKA9j/BGLjUXvhUuCEIolYtyj3jARXL m0TSbnddBS6fxgNC8cQqHbX+gKqxOHuiKmm+Y= Received: by 10.210.57.3 with SMTP id f3mr9503807eba.91.1249420672612; Tue, 04 Aug 2009 14:17:52 -0700 (PDT) Received: from florian (135.87.196-77.rev.gaoland.net [77.196.87.135]) by mx.google.com with ESMTPS id 28sm1467282eye.34.2009.08.04.14.17.50 (version=TLSv1/SSLv3 cipher=RC4-MD5); Tue, 04 Aug 2009 14:17:51 -0700 (PDT) From: Florian Fainelli Date: Tue, 4 Aug 2009 23:17:49 +0200 Subject: [PATCH 6/5] cpmac: unmark as broken MIME-Version: 1.0 X-UID: 1164 X-Length: 1251 To: Ralf Baechle Cc: linux-mips@linux-mips.org, netdev@vger.kernel.org, David Miller Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Content-Disposition: inline Message-Id: <200908042317.49497.florian@openwrt.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23835 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips Hi David, I realised afterwards that unmarking cpmac as BROKEN should have been part of the previous patch series that I sent. Sorry about that. -- From: Florian Fainelli Subject: [PATCH 6/5] cpmac: unmark as broken Starting with version 0.5.1, cpmac is no longer broken. Signed-off-by: Florian Fainelli --- diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 5f6509a..9948fa2 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -1774,7 +1774,7 @@ config SC92031 config CPMAC tristate "TI AR7 CPMAC Ethernet support (EXPERIMENTAL)" - depends on NET_ETHERNET && EXPERIMENTAL && AR7 && BROKEN + depends on NET_ETHERNET && EXPERIMENTAL && AR7 select PHYLIB help TI AR7 CPMAC Ethernet support From sgi-linux-mips@m.gmane.org Wed Aug 5 01:08:25 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 05 Aug 2009 01:08:32 +0200 (CEST) Received: from main.gmane.org ([80.91.229.2]:57608 "EHLO ciao.gmane.org" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S2097290AbZHDXIZ (ORCPT ); Wed, 5 Aug 2009 01:08:25 +0200 Received: from list by ciao.gmane.org with local (Exim 4.43) id 1MYT7E-00036s-1k for linux-mips@linux-mips.org; Tue, 04 Aug 2009 23:08:20 +0000 Received: from chipmunk.wormnet.eu ([195.195.131.226]) by main.gmane.org with esmtp (Gmexim 0.1 (Debian)) id 1AlnuQ-0007hv-00 for ; Tue, 04 Aug 2009 23:08:20 +0000 Received: from alex by chipmunk.wormnet.eu with local (Gmexim 0.1 (Debian)) id 1AlnuQ-0007hv-00 for ; Tue, 04 Aug 2009 23:08:20 +0000 X-Injected-Via-Gmane: http://gmane.org/ To: linux-mips@linux-mips.org From: Alexander Clouter Subject: Re: [PATCH] ar7: register watchdog driver only if enabled in hardware configuration Date: Tue, 4 Aug 2009 23:41:42 +0100 Lines: 59 Message-ID: <62qmk6-g11.ln1@chipmunk.wormnet.eu> References: <200908042309.36721.florian@openwrt.org> X-Complaints-To: usenet@ger.gmane.org X-Gmane-NNTP-Posting-Host: chipmunk.wormnet.eu User-Agent: tin/1.9.3-20080506 ("Dalintober") (UNIX) (Linux/2.6.26-2-sparc64-smp (sparc64)) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23836 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: alex@digriz.org.uk Precedence: bulk X-list: linux-mips Florian Fainelli wrote: > > This patch checks if the watchdog enable bit is set in the DCL > register meaning that the hardware watchdog actually works and > if so, register the ar7_wdt platform_device. > > Signed-off-by: Florian Fainelli > --- > diff --git a/arch/mips/ar7/platform.c b/arch/mips/ar7/platform.c > index e2278c0..835f3f0 100644 > --- a/arch/mips/ar7/platform.c > +++ b/arch/mips/ar7/platform.c > @@ -503,6 +503,7 @@ static int __init ar7_register_devices(void) > { > u16 chip_id; > int res; > + u32 *bootcr, val; > #ifdef CONFIG_SERIAL_8250 > static struct uart_port uart_port[2]; > > @@ -595,7 +596,13 @@ static int __init ar7_register_devices(void) > > ar7_wdt_res.end = ar7_wdt_res.start + 0x20; > > - res = platform_device_register(&ar7_wdt); > + bootcr = (u32 *)ioremap_nocache(AR7_REGS_DCL, 4); > + val = *bootcr; > + iounmap(bootcr); > + > + /* Register watchdog only if enabled in hardware */ > + if (val & AR7_WDT_HW_ENA) > + res = platform_device_register(&ar7_wdt); > I think the 'correct' way to do this is: --- void __iomem *bootcr; u32 val; ... bootcr = ioremap_nocache(AR7_REGS_DCL, 4); val = *bootcr; iounmap(bootcr); --- I'm betting this could be reduced to: --- if (ioread32(AR7_REGS_DCL) & AR7_WDT_HW_ENA) res = platform_device_register(&ar7_wdt); --- However without the hardware...I cannot test this. Cheers -- Alexander Clouter .sigmonster says: Accuracy, n.: The vice of being right From ralf@linux-mips.org Wed Aug 5 03:17:55 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 05 Aug 2009 03:18:02 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:42963 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1493301AbZHEBRz (ORCPT ); Wed, 5 Aug 2009 03:17:55 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id n751IMX0017154; Wed, 5 Aug 2009 02:18:22 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id n751IL51017153; Wed, 5 Aug 2009 02:18:21 +0100 Date: Wed, 5 Aug 2009 02:18:21 +0100 From: Ralf Baechle To: David Daney Cc: linux-mips@linux-mips.org Subject: Re: [PATCH 1/2] MIPS: Allow kernel use of ll/sc to be separate from the presence of ll/sc. Message-ID: <20090805011820.GA16950@linux-mips.org> References: <1247508920-29153-1-git-send-email-ddaney@caviumnetworks.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1247508920-29153-1-git-send-email-ddaney@caviumnetworks.com> User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23837 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Mon, Jul 13, 2009 at 11:15:19AM -0700, David Daney wrote: > On some CPUs, it is more efficient to disable and enable interrupts in > the kernel rather than use ll/sc for atomic operations. But if we > were to set cpu_has_llsc to false, we would break the userspace futex > interface (in asm/futex.h). > > We separate the two concepts, with a new predicate kernel_uses_llsc, > that lets us disable the kernel's use of ll/sc while still allowing > the futex code to use it. > > Also there were a couple of cases in bitops.h where we were using > ll/sc unconditionally even if cpu_has_llsc were false. There are > several places in assembly code where the configure variable > CONFIG_CPU_HAS_LLSC is used instead of cpu_has_llsc, so we make > cpu_has_llsc true if CONFIG_CPU_HAS_LLSC is set, for consistency. The uses in bitops.h you mentioned were not bugs; they were wrapped in #ifdef CONFIG_CPU_MIPSR2 and MIPS R2 implies having LL/SC. So for sane setups there just is no point in bothering. As discussed on IRC - this patch adds one more use of CONFIG_CPU_HAS_LLSC which really should die. So I turned the remaining CONFIG_CPU_HAS_LLSC users further upside down, removed CONFIG_CPU_HAS_LLSC and applied your patch with the necessary adjustments on top. Thanks! Ralf From ralf@linux-mips.org Wed Aug 5 03:29:32 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 05 Aug 2009 03:29:39 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:57768 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1493298AbZHEB3c (ORCPT ); Wed, 5 Aug 2009 03:29:32 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id n751U5SW017384; Wed, 5 Aug 2009 02:30:05 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id n751U4Pj017382; Wed, 5 Aug 2009 02:30:04 +0100 Date: Wed, 5 Aug 2009 02:30:04 +0100 From: Ralf Baechle To: Raghu Gandham Cc: linux-mips@linux-mips.org, chris@mips.com Subject: Re: [PATCH] Fix compiler warning in vpe.c Message-ID: <20090805013004.GB16950@linux-mips.org> References: <20090710090132.26187.54479.stgit@linux-raghu> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20090710090132.26187.54479.stgit@linux-raghu> User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23838 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Fri, Jul 10, 2009 at 02:01:32AM -0700, Raghu Gandham wrote: Applied. Thanks, Ralf From sgi-linux-mips@m.gmane.org Wed Aug 5 10:08:26 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 05 Aug 2009 10:08:32 +0200 (CEST) Received: from main.gmane.org ([80.91.229.2]:45419 "EHLO ciao.gmane.org" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492429AbZHEII0 (ORCPT ); Wed, 5 Aug 2009 10:08:26 +0200 Received: from list by ciao.gmane.org with local (Exim 4.43) id 1MYbXp-0004kr-Cx for linux-mips@linux-mips.org; Wed, 05 Aug 2009 08:08:21 +0000 Received: from chipmunk.wormnet.eu ([195.195.131.226]) by main.gmane.org with esmtp (Gmexim 0.1 (Debian)) id 1AlnuQ-0007hv-00 for ; Wed, 05 Aug 2009 08:08:21 +0000 Received: from alex by chipmunk.wormnet.eu with local (Gmexim 0.1 (Debian)) id 1AlnuQ-0007hv-00 for ; Wed, 05 Aug 2009 08:08:21 +0000 X-Injected-Via-Gmane: http://gmane.org/ To: linux-mips@linux-mips.org From: Alexander Clouter Subject: Re: [PATCH] ar7: register watchdog driver only if enabled in hardware configuration Date: Wed, 5 Aug 2009 09:00:35 +0100 Lines: 51 Message-ID: <3qqnk6-j07.ln1@chipmunk.wormnet.eu> References: <200908042309.36721.florian@openwrt.org> X-Complaints-To: usenet@ger.gmane.org X-Gmane-NNTP-Posting-Host: chipmunk.wormnet.eu User-Agent: tin/1.9.3-20080506 ("Dalintober") (UNIX) (Linux/2.6.26-2-sparc64-smp (sparc64)) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23839 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: alex@digriz.org.uk Precedence: bulk X-list: linux-mips Florian Fainelli wrote: > > This patch checks if the watchdog enable bit is set in the DCL > register meaning that the hardware watchdog actually works and > if so, register the ar7_wdt platform_device. > > Signed-off-by: Florian Fainelli > --- > diff --git a/arch/mips/ar7/platform.c b/arch/mips/ar7/platform.c > index e2278c0..835f3f0 100644 > --- a/arch/mips/ar7/platform.c > +++ b/arch/mips/ar7/platform.c > @@ -503,6 +503,7 @@ static int __init ar7_register_devices(void) > { > u16 chip_id; > int res; > + u32 *bootcr, val; > #ifdef CONFIG_SERIAL_8250 > static struct uart_port uart_port[2]; > > @@ -595,7 +596,13 @@ static int __init ar7_register_devices(void) > > ar7_wdt_res.end = ar7_wdt_res.start + 0x20; > > - res = platform_device_register(&ar7_wdt); > + bootcr = (u32 *)ioremap_nocache(AR7_REGS_DCL, 4); > + val = *bootcr; > + iounmap(bootcr); > + > + /* Register watchdog only if enabled in hardware */ > + if (val & AR7_WDT_HW_ENA) > + res = platform_device_register(&ar7_wdt); > > return res; > } > 'res' can now return NULL[1]. Solved if you do: ---- int res = -ENODEV; ---- I'm guessing this is the most apprioate? Cheers [1] I cannot see the full file annoyingly, it's not in my linux-mips git tree. -- Alexander Clouter .sigmonster says: It doesn't matter whether you win or lose -- until you lose. From sshtylyov@ru.mvista.com Wed Aug 5 10:19:15 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 05 Aug 2009 10:19:27 +0200 (CEST) Received: from h155.mvista.com ([63.81.120.155]:40439 "EHLO imap.sh.mvista.com" rhost-flags-OK-FAIL-OK-FAIL) by ftp.linux-mips.org with ESMTP id S1492443AbZHEITP (ORCPT ); Wed, 5 Aug 2009 10:19:15 +0200 Received: from [127.0.0.1] (unknown [10.150.0.9]) by imap.sh.mvista.com (Postfix) with ESMTP id 669F33ECA; Wed, 5 Aug 2009 01:19:11 -0700 (PDT) Message-ID: <4A79407B.7070604@ru.mvista.com> Date: Wed, 05 Aug 2009 12:19:07 +0400 From: Sergei Shtylyov User-Agent: Thunderbird 2.0.0.22 (Windows/20090605) MIME-Version: 1.0 To: Alexander Clouter Cc: linux-mips@linux-mips.org Subject: Re: [PATCH] ar7: register watchdog driver only if enabled in hardware configuration References: <200908042309.36721.florian@openwrt.org> <62qmk6-g11.ln1@chipmunk.wormnet.eu> In-Reply-To: <62qmk6-g11.ln1@chipmunk.wormnet.eu> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23840 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sshtylyov@ru.mvista.com Precedence: bulk X-list: linux-mips Hello. Alexander Clouter wrote: >> This patch checks if the watchdog enable bit is set in the DCL >> register meaning that the hardware watchdog actually works and >> if so, register the ar7_wdt platform_device. >> >> Signed-off-by: Florian Fainelli >> --- >> diff --git a/arch/mips/ar7/platform.c b/arch/mips/ar7/platform.c >> index e2278c0..835f3f0 100644 >> --- a/arch/mips/ar7/platform.c >> +++ b/arch/mips/ar7/platform.c >> @@ -503,6 +503,7 @@ static int __init ar7_register_devices(void) >> { >> u16 chip_id; >> int res; >> + u32 *bootcr, val; >> #ifdef CONFIG_SERIAL_8250 >> static struct uart_port uart_port[2]; >> >> @@ -595,7 +596,13 @@ static int __init ar7_register_devices(void) >> >> ar7_wdt_res.end = ar7_wdt_res.start + 0x20; >> >> - res = platform_device_register(&ar7_wdt); >> + bootcr = (u32 *)ioremap_nocache(AR7_REGS_DCL, 4); >> + val = *bootcr; >> + iounmap(bootcr); >> + >> + /* Register watchdog only if enabled in hardware */ >> + if (val & AR7_WDT_HW_ENA) >> + res = platform_device_register(&ar7_wdt); >> >> > I think the 'correct' way to do this is: > --- > void __iomem *bootcr; > u32 val; > > ... > > bootcr = ioremap_nocache(AR7_REGS_DCL, 4); > val = *bootcr; > Wait, you can't dereference a pointer to void... WBR, Sergei From alex@digriz.org.uk Wed Aug 5 10:34:12 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 05 Aug 2009 10:34:19 +0200 (CEST) Received: from chipmunk.wormnet.eu ([195.195.131.226]:44733 "EHLO chipmunk.wormnet.eu" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492443AbZHEIeM (ORCPT ); Wed, 5 Aug 2009 10:34:12 +0200 Received: by chipmunk.wormnet.eu (Postfix, from userid 1000) id 9A8FF8488D; Wed, 5 Aug 2009 09:34:11 +0100 (BST) Date: Wed, 5 Aug 2009 09:34:11 +0100 From: Alexander Clouter To: Sergei Shtylyov Cc: linux-mips@linux-mips.org Subject: Re: [PATCH] ar7: register watchdog driver only if enabled in hardware configuration Message-ID: <20090805083411.GD31078@chipmunk> References: <200908042309.36721.florian@openwrt.org> <62qmk6-g11.ln1@chipmunk.wormnet.eu> <4A79407B.7070604@ru.mvista.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <4A79407B.7070604@ru.mvista.com> Organization: diGriz X-URL: http://www.digriz.org.uk/ X-JabberID: alex@digriz.org.uk User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23841 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: alex@digriz.org.uk Precedence: bulk X-list: linux-mips Hi, * Sergei Shtylyov [2009-08-05 12:19:07+0400]: > > Hello. > > Alexander Clouter wrote: > > > I think the 'correct' way to do this is: > > --- > > void __iomem *bootcr; > > u32 val; > > > > ... > > > > bootcr = ioremap_nocache(AR7_REGS_DCL, 4); > > val = *bootcr; > > > > Wait, you can't dereference a pointer to void... > bah, ---- val = __raw_readl(bootcr); ---- Cheers -- Alexander Clouter .sigmonster says: If you keep anything long enough, you can throw it away. From ralf@linux-mips.org Wed Aug 5 11:40:34 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 05 Aug 2009 11:40:42 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:49094 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492570AbZHEJke (ORCPT ); Wed, 5 Aug 2009 11:40:34 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id n759f6Dv020847; Wed, 5 Aug 2009 10:41:06 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id n759f4Ag020843; Wed, 5 Aug 2009 10:41:04 +0100 Date: Wed, 5 Aug 2009 10:41:04 +0100 From: Ralf Baechle To: David Daney Cc: linux-mips@linux-mips.org Subject: Re: [PATCH] MIPS: Fix support for Cavium Octeon debugger stub (v2). Message-ID: <20090805094104.GA14461@linux-mips.org> References: <1246905276-8543-1-git-send-email-ddaney@caviumnetworks.com> <1246906976-19979-1-git-send-email-ddaney@caviumnetworks.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1246906976-19979-1-git-send-email-ddaney@caviumnetworks.com> User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23842 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Mon, Jul 06, 2009 at 12:02:56PM -0700, David Daney wrote: > The Cavium Octeon bootloader has a debugger stub that requires a > little help from the target application to break in. > > If configured, when we get an interrupt on the debug uart we wake up > the debugger. > > Changes from v1: Inline octeon_get_boot_debug_flag so it compiles > without CONFIG_CAVIUM_GDB. > > Signed-off-by: David Daney > --- > arch/mips/Kconfig.debug | 10 ++++++ > arch/mips/cavium-octeon/serial.c | 53 ++++++++++++++++++++++++++++++++- > arch/mips/cavium-octeon/setup.c | 2 +- > arch/mips/include/asm/octeon/octeon.h | 1 - > 4 files changed, 63 insertions(+), 3 deletions(-) > > diff --git a/arch/mips/Kconfig.debug b/arch/mips/Kconfig.debug > index 364ca89..f6a0e68 100644 > --- a/arch/mips/Kconfig.debug > +++ b/arch/mips/Kconfig.debug > @@ -42,6 +42,16 @@ config SB1XXX_CORELIS > Select compile flags that produce code that can be processed by the > Corelis mksym utility and UDB Emulator. > > +config CAVIUM_GDB > + bool "Remote GDB debugging using the Cavium Networks Multicore GDB" > + depends on DEBUG_KERNEL > + depends on CPU_CAVIUM_OCTEON > + select DEBUG_INFO > + help > + If you say Y here, it will be possible to remotely debug the MIPS > + kernel using the Cavium Networks GDB with extended SMP support. > + This is only useful for kernel hackers. If unsure, say N. > + > config RUNTIME_DEBUG > bool "Enable run-time debugging" > depends on DEBUG_KERNEL > diff --git a/arch/mips/cavium-octeon/serial.c b/arch/mips/cavium-octeon/serial.c > index 8240728..2110e68 100644 > --- a/arch/mips/cavium-octeon/serial.c > +++ b/arch/mips/cavium-octeon/serial.c > @@ -18,11 +18,60 @@ > > #include > > +#if defined(CONFIG_CAVIUM_GDB) > + > #ifdef CONFIG_GDB_CONSOLE > #define DEBUG_UART 0 > #else > #define DEBUG_UART 1 > #endif > +static irqreturn_t interrupt_debug_char(int cpl, void *dev_id) > +{ > + unsigned long lsrval; > + unsigned long tmp; > + > + lsrval = cvmx_read_csr(CVMX_MIO_UARTX_LSR(DEBUG_UART)); > + if (lsrval & 1) { > +#ifdef CONFIG_KGDB > + /* > + * The Cavium EJTAG bootmonitor stub is not compatible > + * with KGDB. We should never get here. > + */ > +#error Illegal to use both CONFIG_KGDB and CONFIG_CAVIUM_GDB > +#endif #error is only acceptable to catch bugs in Kconfig or the code itself. This #error however is triggering on .config settings including such generated by randconfig which is a PITA. So rather please ensure forbidden .configs can't be generated. Alternatively, implement things such that both config options can co-exist. Ralf From davem@davemloft.net Wed Aug 5 21:23:26 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 05 Aug 2009 21:23:33 +0200 (CEST) Received: from 74-93-104-97-Washington.hfc.comcastbusiness.net ([74.93.104.97]:54099 "EHLO sunset.davemloft.net" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1493429AbZHETXZ (ORCPT ); Wed, 5 Aug 2009 21:23:25 +0200 Received: from localhost (localhost [127.0.0.1]) by sunset.davemloft.net (Postfix) with ESMTP id BEBB6C8C4B1; Wed, 5 Aug 2009 12:23:26 -0700 (PDT) Date: Wed, 05 Aug 2009 12:23:26 -0700 (PDT) Message-Id: <20090805.122326.53960211.davem@davemloft.net> To: florian@openwrt.org Cc: ralf@linux-mips.org, linux-mips@linux-mips.org, netdev@vger.kernel.org Subject: Re: [PATCH 1/5] cpmac: fix wrong MDIO bus identifier From: David Miller In-Reply-To: <200908042252.42254.florian@openwrt.org> References: <200908042252.42254.florian@openwrt.org> X-Mailer: Mew version 6.2.51 on Emacs 22.1 / Mule 5.0 (SAKAKI) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23843 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: davem@davemloft.net Precedence: bulk X-list: linux-mips From: Florian Fainelli Date: Tue, 4 Aug 2009 22:52:41 +0200 > This patch fixes the wrong MDIO bus identifier which was > set to 0 unconditionaly, suitable for external switches while > it is actually 1 for PHYs different than external switches > which are autodetected. > > Signed-off-by: Florian Fainelli Applied to net-next-2.6 From davem@davemloft.net Wed Aug 5 21:23:50 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 05 Aug 2009 21:23:58 +0200 (CEST) Received: from 74-93-104-97-Washington.hfc.comcastbusiness.net ([74.93.104.97]:54103 "EHLO sunset.davemloft.net" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1493434AbZHETX1 (ORCPT ); Wed, 5 Aug 2009 21:23:27 +0200 Received: from localhost (localhost [127.0.0.1]) by sunset.davemloft.net (Postfix) with ESMTP id 1630CC8C4B2; Wed, 5 Aug 2009 12:23:34 -0700 (PDT) Date: Wed, 05 Aug 2009 12:23:33 -0700 (PDT) Message-Id: <20090805.122333.197124214.davem@davemloft.net> To: florian@openwrt.org Cc: ralf@linux-mips.org, linux-mips@linux-mips.org, netdev@vger.kernel.org Subject: Re: [PATCH 2/5] ar7: add fixed PHY support for the two on-board cpmac From: David Miller In-Reply-To: <200908042252.47549.florian@openwrt.org> References: <200908042252.47549.florian@openwrt.org> X-Mailer: Mew version 6.2.51 on Emacs 22.1 / Mule 5.0 (SAKAKI) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23844 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: davem@davemloft.net Precedence: bulk X-list: linux-mips From: Florian Fainelli Date: Tue, 4 Aug 2009 22:52:47 +0200 > This patch adds fixed PHY support for the two on-chip > cpmac Ethernet adapters. > > Signed-off-by: Florian Fainelli Applied to net-next-2.6 From davem@davemloft.net Wed Aug 5 21:24:15 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 05 Aug 2009 21:24:23 +0200 (CEST) Received: from 74-93-104-97-Washington.hfc.comcastbusiness.net ([74.93.104.97]:54108 "EHLO sunset.davemloft.net" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1493437AbZHETXg (ORCPT ); Wed, 5 Aug 2009 21:23:36 +0200 Received: from localhost (localhost [127.0.0.1]) by sunset.davemloft.net (Postfix) with ESMTP id A8837C8C4B1; Wed, 5 Aug 2009 12:23:42 -0700 (PDT) Date: Wed, 05 Aug 2009 12:23:42 -0700 (PDT) Message-Id: <20090805.122342.222976829.davem@davemloft.net> To: florian@openwrt.org Cc: ralf@linux-mips.org, linux-mips@linux-mips.org, netdev@vger.kernel.org Subject: Re: [PATCH 3/5] cpmac: add support for fixed PHY From: David Miller In-Reply-To: <200908042252.53068.florian@openwrt.org> References: <200908042252.53068.florian@openwrt.org> X-Mailer: Mew version 6.2.51 on Emacs 22.1 / Mule 5.0 (SAKAKI) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23845 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: davem@davemloft.net Precedence: bulk X-list: linux-mips From: Florian Fainelli Date: Tue, 4 Aug 2009 22:52:52 +0200 > This patch adds support for fixed PHY connected in MII mode > to cpmac. We allow external and dumb_switch module parameters > to override the PHY detection process since they are always connected > with MDIO bus identifier 0. This lets fixed PHYs to be detected > correctly and be connected to the their corresponding MDIO > bus identifier. > > Signed-off-by: Florian Fainelli Applied to net-next-2.6 From davem@davemloft.net Wed Aug 5 21:24:40 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 05 Aug 2009 21:24:47 +0200 (CEST) Received: from 74-93-104-97-Washington.hfc.comcastbusiness.net ([74.93.104.97]:54112 "EHLO sunset.davemloft.net" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1493440AbZHETXn (ORCPT ); Wed, 5 Aug 2009 21:23:43 +0200 Received: from localhost (localhost [127.0.0.1]) by sunset.davemloft.net (Postfix) with ESMTP id AFFF5C8C4B2; Wed, 5 Aug 2009 12:23:49 -0700 (PDT) Date: Wed, 05 Aug 2009 12:23:49 -0700 (PDT) Message-Id: <20090805.122349.80542560.davem@davemloft.net> To: florian@openwrt.org Cc: ralf@linux-mips.org, linux-mips@linux-mips.org, netdev@vger.kernel.org Subject: Re: [PATCH 4/5] cpmac: wait longer after MDIO reset From: David Miller In-Reply-To: <200908042252.57848.florian@openwrt.org> References: <200908042252.57848.florian@openwrt.org> X-Mailer: Mew version 6.2.51 on Emacs 22.1 / Mule 5.0 (SAKAKI) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23846 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: davem@davemloft.net Precedence: bulk X-list: linux-mips From: Florian Fainelli Date: Tue, 4 Aug 2009 22:52:57 +0200 > This patch slows down the MDIO_ALIVE busy waiting to let > switches and PHY come up after reset. Previous loop was > too quick for IC+175C and ADM6996C/L switches to come up. > > Signed-off-by: Florian Fainelli Applied to net-next-2.6 From davem@davemloft.net Wed Aug 5 21:25:05 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 05 Aug 2009 21:25:12 +0200 (CEST) Received: from 74-93-104-97-Washington.hfc.comcastbusiness.net ([74.93.104.97]:54116 "EHLO sunset.davemloft.net" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1493429AbZHETXw (ORCPT ); Wed, 5 Aug 2009 21:23:52 +0200 Received: from localhost (localhost [127.0.0.1]) by sunset.davemloft.net (Postfix) with ESMTP id D46C7C8C4B1; Wed, 5 Aug 2009 12:23:58 -0700 (PDT) Date: Wed, 05 Aug 2009 12:23:58 -0700 (PDT) Message-Id: <20090805.122358.178352757.davem@davemloft.net> To: florian@openwrt.org Cc: ralf@linux-mips.org, linux-mips@linux-mips.org, netdev@vger.kernel.org Subject: Re: [PATCH 5/5] cpmac: bump version to 0.5.1 From: David Miller In-Reply-To: <200908042253.00563.florian@openwrt.org> References: <200908042253.00563.florian@openwrt.org> X-Mailer: Mew version 6.2.51 on Emacs 22.1 / Mule 5.0 (SAKAKI) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23847 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: davem@davemloft.net Precedence: bulk X-list: linux-mips From: Florian Fainelli Date: Tue, 4 Aug 2009 22:53:00 +0200 > > Signed-off-by: Florian Fainelli Applied to net-next-2.6 From davem@davemloft.net Wed Aug 5 21:25:30 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 05 Aug 2009 21:25:37 +0200 (CEST) Received: from 74-93-104-97-Washington.hfc.comcastbusiness.net ([74.93.104.97]:54118 "EHLO sunset.davemloft.net" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1493443AbZHETYD (ORCPT ); Wed, 5 Aug 2009 21:24:03 +0200 Received: from localhost (localhost [127.0.0.1]) by sunset.davemloft.net (Postfix) with ESMTP id 77BEDC8C4B1; Wed, 5 Aug 2009 12:24:10 -0700 (PDT) Date: Wed, 05 Aug 2009 12:24:10 -0700 (PDT) Message-Id: <20090805.122410.124361028.davem@davemloft.net> To: florian@openwrt.org Cc: ralf@linux-mips.org, linux-mips@linux-mips.org, netdev@vger.kernel.org Subject: Re: [PATCH 6/5] cpmac: unmark as broken From: David Miller In-Reply-To: <200908042317.49497.florian@openwrt.org> References: <200908042317.49497.florian@openwrt.org> X-Mailer: Mew version 6.2.51 on Emacs 22.1 / Mule 5.0 (SAKAKI) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23848 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: davem@davemloft.net Precedence: bulk X-list: linux-mips From: Florian Fainelli Date: Tue, 4 Aug 2009 23:17:49 +0200 > Starting with version 0.5.1, cpmac is no longer broken. > > Signed-off-by: Florian Fainelli Applied to net-next-2.6 From zzt256@gmail.com Fri Aug 7 08:38:43 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 07 Aug 2009 08:38:49 +0200 (CEST) Received: from ey-out-1920.google.com ([74.125.78.147]:48120 "EHLO ey-out-1920.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492003AbZHGGin convert rfc822-to-8bit (ORCPT ); Fri, 7 Aug 2009 08:38:43 +0200 Received: by ey-out-1920.google.com with SMTP id 13so430221eye.54 for ; Thu, 06 Aug 2009 23:38:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:sender:received:in-reply-to :references:date:x-google-sender-auth:message-id:subject:from:to :content-type:content-transfer-encoding; bh=+iz0+6dV1pHl+u3eXOVOHjFieUSk+k3JxXm9tzFelb8=; b=aY6/KMkCfIrmjTiYZ2dHbGgho+WsxH9AmR+QFGN8YeZoPrkychsq5Y2gnJpo7oQfDZ yNKuQ4KcUivqWIsRmoGY7b55X3e/oqOJCdOGPFSRssTQag/+mKBTxpZzSwBtDKrLJaMh pPXK4A+pCon9NpVFZZwzPfPk6WcQqlpKRhows= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:sender:in-reply-to:references:date :x-google-sender-auth:message-id:subject:from:to:content-type :content-transfer-encoding; b=PCZi29q8OF6PkLU/C0kX0/yhAaBYl8F9c+1NFHC4jtavMA7T189UBy21FUbNYybeKV GW283UAoMh+2MOuJynCqPF1evsskNg6uXd/ie2jHhNgP3Khes8Ne8GZXuFgmnTlIAm9Q 7RSR/Hy3+iXoTfrTy5JXjZ7mV2uzg8AUsDslM= MIME-Version: 1.0 Received: by 10.216.26.77 with SMTP id b55mr158067wea.101.1249627122496; Thu, 06 Aug 2009 23:38:42 -0700 (PDT) In-Reply-To: <20090803181958.GA7009@cuplxvomd02.corp.sa.net> References: <20090730184923.GA27030@cuplxvomd02.corp.sa.net> <20090803092030.GB30431@linux-mips.org> <20090803181958.GA7009@cuplxvomd02.corp.sa.net> Date: Fri, 7 Aug 2009 08:38:42 +0200 X-Google-Sender-Auth: 296c629e3b3184fe Message-ID: Subject: Re: Relocation problem with MIPS kernel modules From: "Marshall B. Rogers" To: David VomLehn , GCC Help Mailing List , Linux MIPS Mailing List Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23849 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mbr@64.vg Precedence: bulk X-list: linux-mips @David VomLehn: This is four days overdue, but here's a big document on the 32-bit MIPS ABI: http://math-atlas.sourceforge.net/devel/assembly/mipsabi32.pdf I haven't read it all, but it seems to cover everything you would ever need, including the relocation types. Regards, Marshall On Mon, Aug 3, 2009 at 8:19 PM, David VomLehn wrote: > > On Mon, Aug 03, 2009 at 10:20:30AM +0100, Ralf Baechle wrote: > > On Thu, Jul 30, 2009 at 11:49:23AM -0700, David VomLehn wrote: > > > > > To: GCC Help Mailing List , > > >     Linux MIPS Mailing List > > > Subject: Relocation problem with MIPS kernel modules > > > Content-Type: text/plain; charset=us-ascii > > > > > > I have a MIPS loadable kernel module that, when I try to insmod it, causes the > > > kernel to emit the message: > > > > > >     module xyz: dangerous relocation > ... > > > According to the MIPS ABI, for what it's worth, "Each relocation type of > > > R_MIPS_HI16 must have an associated R_MIPS_LO16 entry immediately following > > > it in the list of relocations." So, what's actually getting generated by > > > gcc and linker differs from the closest thing we have to an ABI of record for > > > MIPS processors. > > > > The GNU tools as an extension over the MIPS ABI allows an arbitrary number of > > R_MIPS_HI16 relocations to be followed by a R_MIPS_LO16 symbol.  All > > relocations of this sequence must use the same symbol, of course.  This is > > a very old extension; I think it predates the Linux/MIPS port. > > Perhaps a foolish question, but is this documented anywhere? I know there is a > a document over at http://gcc.gnu.org/gcc-3.4/mips-abi.html addressing some > other MIPS ABI changes, but I didn't see this one. Obviously, we could put > documentation on the linux-mips Wiki, with pointers to other documents, but > I'm not sure this is the right place. I'm also concerned there could be other > ABI changes/extensions that need to be included. > > >   Ralf > > David From macro@linux-mips.org Fri Aug 7 17:29:26 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 07 Aug 2009 17:29:29 +0200 (CEST) Received: from localhost.localdomain ([127.0.0.1]:51023 "EHLO localhost.localdomain" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492759AbZHGP30 (ORCPT ); Fri, 7 Aug 2009 17:29:26 +0200 Date: Fri, 7 Aug 2009 16:29:26 +0100 (BST) From: "Maciej W. Rozycki" To: David VomLehn cc: Ralf Baechle , David Daney , GCC Help Mailing List , Linux MIPS Mailing List Subject: Re: Relocation problem with MIPS kernel modules In-Reply-To: <20090804021800.GA14627@cuplxvomd02.corp.sa.net> Message-ID: References: <20090730184923.GA27030@cuplxvomd02.corp.sa.net> <20090803092030.GB30431@linux-mips.org> <4A773B85.6010004@caviumnetworks.com> <20090803201521.GA24691@cuplxvomd02.corp.sa.net> <20090803235536.GB22543@linux-mips.org> <20090804021800.GA14627@cuplxvomd02.corp.sa.net> User-Agent: Alpine 2.00 (LFD 1167 2008-08-23) MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23850 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: macro@linux-mips.org Precedence: bulk X-list: linux-mips On Mon, 3 Aug 2009, David VomLehn wrote: > > The next and logical extension would be to permit multiple R_MIPS_LO16 > > records following a sequence of one or more R_MIPS_HI16 relocs as long as > > all relate to the same symbol - which would be simple to support in the > > kernel. > > This is what the orphaned R_MIPS_LO16 entries mentioned in the psABI quote > are all about. The existing relocation code handles this in most cases, but > could be juiced up a bit to do the check to verify the symbols match between > the current R_MIPS_LO16 entry and the last R_MIPS_HI16 entry. Note there is no need to implement Ralf's suggestion -- if multiple HI16 and LO16 relocations referring to the same symbol and addend are scattered throughout an object module, then the tools should combine them into pairs appropriately -- it does not matter exactly which ones of each are paired. Now once this has been done, a number of orphaned HI16 or LO16 relocations may remain, but there will only ever be one kind of these left and they can be attached to any of the pairs previously created. My understanding is this is exactly what BFD does (modulo any possible bugs of course, as usually). Maciej From f.fainelli@gmail.com Fri Aug 7 19:27:33 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 07 Aug 2009 19:27:40 +0200 (CEST) Received: from mail-ew0-f216.google.com ([209.85.219.216]:38282 "EHLO mail-ew0-f216.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492798AbZHGR1d convert rfc822-to-8bit (ORCPT ); Fri, 7 Aug 2009 19:27:33 +0200 Received: by ewy12 with SMTP id 12so2120801ewy.0 for ; Fri, 07 Aug 2009 10:27:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:sender:from:to:subject:date :user-agent:cc:references:in-reply-to:mime-version:content-type :content-transfer-encoding:content-disposition:message-id; bh=xRMqy0ieTMAw+aXx3furpwhWYdtl5D1vfgnpZHTXdfc=; b=DlSPFh7Rhzw4RojSDW7cq1ZShSN2IXxnz3MptVTUM3GJ1cFjzdpu61FGfe0fIvulBp OnL8iZ4/6qHLYzk3tQagfF3U04ueob834IWGuH5oq2wmgXqO3Eun2N1bxWMauDdd2rqb UmGK3qGh5l81X5kLbt2lvqF/Dr6naX02aCLek= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:from:to:subject:date:user-agent:cc:references:in-reply-to :mime-version:content-type:content-transfer-encoding :content-disposition:message-id; b=Zbw3uSHkkk8dNQ1GK7Xj6FGyvzOKwsqpSSj5svLCYr0ayoXxSDoVkv0JujW5TJGvSI MbLDXiI4MCaTbmATeOD0cZDmj2UtZtTfhAVp6q4+PimobaTHPvWibix9jYW8oHBXlfQO rKJkv8QXYmGVCqVRlmq8OgXBwY2SXAwdxlhRo= Received: by 10.210.131.6 with SMTP id e6mr1680454ebd.63.1249666048120; Fri, 07 Aug 2009 10:27:28 -0700 (PDT) Received: from ?192.168.254.2? (florian.mimichou.net [82.241.112.26]) by mx.google.com with ESMTPS id 7sm3609271eyg.5.2009.08.07.10.27.22 (version=TLSv1/SSLv3 cipher=RC4-MD5); Fri, 07 Aug 2009 10:27:24 -0700 (PDT) From: Florian Fainelli To: Alexander Clouter Subject: Re: [PATCH] ar7: register watchdog driver only if enabled in hardware configuration Date: Fri, 7 Aug 2009 19:27:19 +0200 User-Agent: KMail/1.9.9 Cc: linux-mips@linux-mips.org References: <200908042309.36721.florian@openwrt.org> <3qqnk6-j07.ln1@chipmunk.wormnet.eu> In-Reply-To: <3qqnk6-j07.ln1@chipmunk.wormnet.eu> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8BIT Content-Disposition: inline Message-Id: <200908071927.19714.florian@openwrt.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23851 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips Hey Alexander, Le Wednesday 05 August 2009 10:00:35 Alexander Clouter, vous avez écrit : > Florian Fainelli wrote: > > This patch checks if the watchdog enable bit is set in the DCL > > register meaning that the hardware watchdog actually works and > > if so, register the ar7_wdt platform_device. > > > > Signed-off-by: Florian Fainelli > > --- > > diff --git a/arch/mips/ar7/platform.c b/arch/mips/ar7/platform.c > > index e2278c0..835f3f0 100644 > > --- a/arch/mips/ar7/platform.c > > +++ b/arch/mips/ar7/platform.c > > @@ -503,6 +503,7 @@ static int __init ar7_register_devices(void) > > { > > u16 chip_id; > > int res; > > + u32 *bootcr, val; > > #ifdef CONFIG_SERIAL_8250 > > static struct uart_port uart_port[2]; > > > > @@ -595,7 +596,13 @@ static int __init ar7_register_devices(void) > > > > ar7_wdt_res.end = ar7_wdt_res.start + 0x20; > > > > - res = platform_device_register(&ar7_wdt); > > + bootcr = (u32 *)ioremap_nocache(AR7_REGS_DCL, 4); > > + val = *bootcr; > > + iounmap(bootcr); > > + > > + /* Register watchdog only if enabled in hardware */ > > + if (val & AR7_WDT_HW_ENA) > > + res = platform_device_register(&ar7_wdt); > > > > return res; > > } > > 'res' can now return NULL[1]. Solved if you do: > ---- > int res = -ENODEV; > ---- > > I'm guessing this is the most apprioate? I prefer letting this as-is, since if the watchdog was not enabled in hardware, we will not register the watchdog driver, and return the last platform_device_register call. > > Cheers > > [1] I cannot see the full file annoyingly, it's not in my linux-mips > git tree. Not sure which tree you checked out, but it is in linux-queue: http://www.linux-mips.org/git?p=linux-queue.git;a=tree;f=arch/mips/ar7;h=40ee7382dfabf05ee6c967016e42f94992655c20;hb=HEAD -- Best regards, Florian Fainelli Email: florian@openwrt.org Web: http://openwrt.org IRC: [florian] on irc.freenode.net ------------------------------- From f.fainelli@gmail.com Fri Aug 7 23:46:26 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 07 Aug 2009 23:46:32 +0200 (CEST) Received: from mail-ew0-f216.google.com ([209.85.219.216]:52655 "EHLO mail-ew0-f216.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492923AbZHGVq0 (ORCPT ); Fri, 7 Aug 2009 23:46:26 +0200 Received: by ewy12 with SMTP id 12so2282279ewy.0 for ; Fri, 07 Aug 2009 14:46:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:sender:from:to:subject:date :user-agent:cc:mime-version:content-type:content-transfer-encoding :content-disposition:message-id; bh=uExFJFgfv1E5EXxJF1zDj6iUSKGubglgj+mAs0VVURA=; b=TIU7bJcuLshZCgG+wRCo2uwDm7y4Quie1jRi1bjwuAMercqx1zVyjjn0md0YoFkW9u 9i2T3Gzja5Whhh4Seq5xu+sh9U13Z4nMdM2z7VRtMcgMgQX4fVXTbpOmgf11WandXNh2 Eltar5YsZIG6Qn4lJ4PBBGyMZ0jFCnNI13lRA= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:from:to:subject:date:user-agent:cc:mime-version:content-type :content-transfer-encoding:content-disposition:message-id; b=VdDTrqXb/wC83u/Xdr3ZjbFpWB4AVak7cMF9PR5htuPdtyeIewQUheM7TJB19c7/OJ wypNb0Z7RwntFUVlZLjgcQDiJIF5GblPdb1d/yM9bVpZh57lqVb19f/TBSlUnwEsViNV SOe2dXIVIOHzI80x2ssM5lQtAvAHRh9bGupGM= Received: by 10.210.81.9 with SMTP id e9mr25549ebb.68.1249681578421; Fri, 07 Aug 2009 14:46:18 -0700 (PDT) Received: from lenovo.mimichou.home (home.mimichou.net [82.67.132.19]) by mx.google.com with ESMTPS id 28sm1543080eye.24.2009.08.07.14.46.17 (version=TLSv1/SSLv3 cipher=RC4-MD5); Fri, 07 Aug 2009 14:46:18 -0700 (PDT) From: Florian Fainelli To: Ralf Baechle Subject: [PATCH 0/8] New BCM63xx SoC support and devices registration Date: Fri, 7 Aug 2009 23:46:14 +0200 User-Agent: KMail/1.9.9 Cc: Maxime Bizon , linux-mips@linux-mips.org MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Content-Disposition: inline Message-Id: <200908072346.15278.florian@openwrt.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23852 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips Hi Ralf, Maxime, The following 8 patches apply on top of the patch entitled "bcm63xx: fix build failures when CONFIG_PCI is disabled" Ralf, Maxime sent a patch series on June 3rd which would be great to merge so that I can rebase my serie on that one. Thanks and have a nice weekend. -- Best regards, Florian Fainelli Email: florian@openwrt.org Web: http://openwrt.org IRC: [florian] on irc.freenode.net ------------------------------- From f.fainelli@gmail.com Fri Aug 7 23:47:05 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 07 Aug 2009 23:47:12 +0200 (CEST) Received: from mail-ew0-f216.google.com ([209.85.219.216]:56610 "EHLO mail-ew0-f216.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492938AbZHGVq3 (ORCPT ); Fri, 7 Aug 2009 23:46:29 +0200 Received: by ewy12 with SMTP id 12so2282347ewy.0 for ; Fri, 07 Aug 2009 14:46:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:sender:from:date:subject :mime-version:x-uid:x-length:to:cc:content-type :content-transfer-encoding:content-disposition:message-id; bh=wHwO6TZ8bVbgzZ5wNbI5QITQlzI+F/Wkwf4dNi++5NQ=; b=Brg/UeysHnuUh131W29y9ffMLv3S2c3FoOuhc+1chS17rxcSLPyXHE4q23XEA3pK2h JMqz/baV8sx0T4E2HQP+KsFkfAV0qz7DbgnU6RNJc9+DY6iDcOjuP/93sZje5XMeUuzx RKl9MZm0HsW3ZArvb063Az96VYuKvS94LmVMg= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:from:date:subject:mime-version:x-uid:x-length:to:cc :content-type:content-transfer-encoding:content-disposition :message-id; b=ufIL0OeBq9dIkOtMA9zSy8+zZFIDvCI8umyN+EFfFpCnJTHTihiYS7F+zumyVFXCxe ZtqPWzZ/F/9aQtOuZFEs6/6ezffgPYIdAfZf5+BtPP6kjgPp9mtdKnKl1QfsfwZl06ee E1J23TZgMi/oz5fHNQGtbPvKJ74GyGu2bpvJI= Received: by 10.210.143.17 with SMTP id q17mr1938999ebd.97.1249681584244; Fri, 07 Aug 2009 14:46:24 -0700 (PDT) Received: from lenovo.mimichou.home (home.mimichou.net [82.67.132.19]) by mx.google.com with ESMTPS id 28sm2082843eye.14.2009.08.07.14.46.23 (version=TLSv1/SSLv3 cipher=RC4-MD5); Fri, 07 Aug 2009 14:46:23 -0700 (PDT) From: Florian Fainelli Date: Fri, 7 Aug 2009 23:46:21 +0200 Subject: [PATCH 1/8] bcm63xx: add infrastructure for MPI-connected VoIP DSP MIME-Version: 1.0 X-UID: 1178 X-Length: 4833 To: Ralf Baechle Cc: Maxime Bizon , linux-mips@linux-mips.org Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Content-Disposition: inline Message-Id: <200908072346.21785.florian@openwrt.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23853 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips This patch adds the required infrastructure to register a MPI and GPIO connected VoIP DSP. We will register devices in a subsequent patch. Signed-off-by: Florian Fainelli --- diff --git a/arch/mips/bcm63xx/Makefile b/arch/mips/bcm63xx/Makefile index 92d07f0..70ba038 100644 --- a/arch/mips/bcm63xx/Makefile +++ b/arch/mips/bcm63xx/Makefile @@ -4,6 +4,7 @@ obj-y += dev-pcmcia.o obj-y += dev-usb-ohci.o obj-y += dev-usb-ehci.o obj-y += dev-enet.o +obj-y += dev-dsp.o obj-$(CONFIG_EARLY_PRINTK) += early_printk.o obj-y += boards/ diff --git a/arch/mips/bcm63xx/dev-dsp.c b/arch/mips/bcm63xx/dev-dsp.c new file mode 100644 index 0000000..08a2f75 --- /dev/null +++ b/arch/mips/bcm63xx/dev-dsp.c @@ -0,0 +1,56 @@ +/* + * Broadcom BCM63xx VoIP DSP registration + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2009 Florian Fainelli + */ + +#include +#include +#include + +#include +#include +#include +#include + +static struct resource voip_dsp_resources[] = { + { + .start = -1, /* filled at runtime */ + .end = -1, /* filled at runtime */ + .flags = IORESOURCE_MEM, + }, + { + .start = -1, /* filled at runtime */ + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device bcm63xx_voip_dsp_device = { + .name = "bcm63xx-voip-dsp", + .id = 0, + .num_resources = ARRAY_SIZE(voip_dsp_resources), + .resource = voip_dsp_resources, +}; + +int __init bcm63xx_dsp_register(const struct bcm63xx_dsp_platform_data *pd) +{ + struct bcm63xx_dsp_platform_data *dpd; + u32 val; + + /* Get the memory window */ + val = bcm_mpi_readl(MPI_CSBASE_REG(pd->cs - 1)); + val &= MPI_CSBASE_BASE_MASK; + voip_dsp_resources[0].start = val; + voip_dsp_resources[0].end = val + 0xFFFFFFF; + voip_dsp_resources[1].start = pd->ext_irq; + + /* copy given platform data */ + dpd = bcm63xx_voip_dsp_device.dev.platform_data; + memcpy(dpd, pd, sizeof (*pd)); + + return platform_device_register(&bcm63xx_voip_dsp_device); +} diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_dsp.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_dsp.h new file mode 100644 index 0000000..b587d45 --- /dev/null +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_dsp.h @@ -0,0 +1,13 @@ +#ifndef __BCM63XX_DSP_H +#define __BCM63XX_DSP_H + +struct bcm63xx_dsp_platform_data { + unsigned gpio_rst; + unsigned gpio_int; + unsigned cs; + unsigned ext_irq; +}; + +int __init bcm63xx_dsp_register(const struct bcm63xx_dsp_platform_data *pd); + +#endif /* __BCM63XX_DSP_H */ diff --git a/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h b/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h index 17e4e7e..9fde025 100644 --- a/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h +++ b/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h @@ -3,6 +3,7 @@ #include #include +#include /* * flash mapping @@ -41,10 +42,14 @@ struct board_info { unsigned int has_pccard:1; unsigned int has_ohci0:1; unsigned int has_ehci0:1; + unsigned int has_dsp:1; /* ethernet config */ struct bcm63xx_enet_platform_data enet0; struct bcm63xx_enet_platform_data enet1; + + /* DSP config */ + struct bcm63xx_dsp_platform_data dsp; }; #endif /* ! BOARD_BCM963XX_H_ */ From f.fainelli@gmail.com Fri Aug 7 23:47:30 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 07 Aug 2009 23:47:37 +0200 (CEST) Received: from ey-out-1920.google.com ([74.125.78.149]:61977 "EHLO ey-out-1920.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492944AbZHGVqh (ORCPT ); Fri, 7 Aug 2009 23:46:37 +0200 Received: by ey-out-1920.google.com with SMTP id 13so537881eye.54 for ; Fri, 07 Aug 2009 14:46:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:sender:from:date:subject :mime-version:x-uid:x-length:to:cc:content-type :content-transfer-encoding:content-disposition:message-id; bh=nrzeIIAM5/t90Cxqfd+HUi4lRUiFzU6ZXabHeOmRQg8=; b=vICbOin1c/Kdbe0eX4UTFsKUtSeTdStrLy1h+poVjIhlqJS8wlhwT8jhXAAEiYqN+c 9GiMFmREpiQkiCUozRmRfOGS5r5nqDLO4GpKv9Rbs9n/Ql8V8B/om+WO0jKn7/+l+XN1 OQ56RRp31mVp/3pG3Ts25KQpu2jm5DYNNQqSU= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:from:date:subject:mime-version:x-uid:x-length:to:cc :content-type:content-transfer-encoding:content-disposition :message-id; b=n8LF5TfWk+2oqGSGc4JtLnqERlLN80EWi2ju7ZSI5QlGUQUrIKugiglr2V/CNW8nNd oYJglAxvp1LCKkUgvz+1OB2h1WolMH80lmW4MuDU7VeA2cnTFHW/zUzMho4pU/t2BSs9 XOqsWTm6YkulIGToxhXKOWMTHG6ymPsgAgo50= Received: by 10.210.131.6 with SMTP id e6mr53090ebd.29.1249681596437; Fri, 07 Aug 2009 14:46:36 -0700 (PDT) Received: from lenovo.mimichou.home (home.mimichou.net [82.67.132.19]) by mx.google.com with ESMTPS id 28sm1543779eye.24.2009.08.07.14.46.35 (version=TLSv1/SSLv3 cipher=RC4-MD5); Fri, 07 Aug 2009 14:46:35 -0700 (PDT) From: Florian Fainelli Date: Fri, 7 Aug 2009 23:46:34 +0200 Subject: [PATCH 2/8] bcm63xx: register VoIP DSP for bcm96348gw-10 and bcm96348gw designs MIME-Version: 1.0 X-UID: 1179 X-Length: 2345 To: Ralf Baechle Cc: Maxime Bizon , linux-mips@linux-mips.org Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Content-Disposition: inline Message-Id: <200908072346.34473.florian@openwrt.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23854 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips This patchs makes bcm96348gw-10 and bcm96348gw designs register the VoIP DSP platform device. Signed-off-by: Florian Fainelli --- diff --git a/arch/mips/bcm63xx/boards/board_bcm963xx.c b/arch/mips/bcm63xx/boards/board_bcm963xx.c index 683873d..668abdb 100644 --- a/arch/mips/bcm63xx/boards/board_bcm963xx.c +++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #define PFX "board_bcm963xx: " @@ -72,6 +73,14 @@ static struct board_info __initdata board_96348gw_10 = { .has_ohci0 = 1, .has_pccard = 1, .has_ehci0 = 1, + + .has_dsp = 1, + .dsp = { + .gpio_rst = 6, + .gpio_int = 34, + .cs = 2, + .ext_irq = 2, + }, }; static struct board_info __initdata board_96348gw_11 = { @@ -116,6 +125,14 @@ static struct board_info __initdata board_96348gw = { }, .has_ohci0 = 1, + + .has_dsp = 1, + .dsp = { + .gpio_rst = 6, + .gpio_int = 34, + .ext_irq = 2, + .cs = 2, + }, }; static struct board_info __initdata board_FAST2404 = { @@ -514,6 +531,9 @@ int __init board_register_devices(void) if (board.has_ehci0) bcm63xx_ehci_register(); + if (board.has_dsp) + bcm63xx_dsp_register(&board.dsp); + /* Generate MAC address for WLAN and * register our SPROM */ #ifdef CONFIG_SSB_PCIHOST From f.fainelli@gmail.com Fri Aug 7 23:47:54 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 07 Aug 2009 23:48:02 +0200 (CEST) Received: from mail-ew0-f216.google.com ([209.85.219.216]:52655 "EHLO mail-ew0-f216.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492860AbZHGVqn (ORCPT ); Fri, 7 Aug 2009 23:46:43 +0200 Received: by mail-ew0-f216.google.com with SMTP id 12so2282279ewy.0 for ; Fri, 07 Aug 2009 14:46:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:sender:from:date:subject :mime-version:x-uid:x-length:to:cc:content-type :content-transfer-encoding:content-disposition:message-id; bh=Ml0pZMlkBD3wDPvlY9oAP5vwSJqu7JH5DNwhBjZ2Xe8=; b=K64hQjPhmWCc4wC8HAukkIb0Gtbj5CxuQ4NmgMQZejD1zl8lWqOt6/+6I5DOKFYCon zuqzJosgC8AQ+lM8CAvuJHwvkBy2xoT/UvhjvbazNg3AcgA8ZFajxHNGEwQOOUCOjcLo uUpX8+CC0pHTRvf6bSLnnegGZk0viUTAFeWhI= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:from:date:subject:mime-version:x-uid:x-length:to:cc :content-type:content-transfer-encoding:content-disposition :message-id; b=TzbE6LrxLGd25icZNcr7R2+CvKi3HvY1I38go+A10z+z4vKDRZv0UZYMza/Ud282xy e2kave0xwfnfsKn8TCMWhiPTaYDoftXcfWsA9W3vltvxjgYQZ5UnlwDHIphoErPnDa3c rh6A/S0JUGWiF5MxokX6TkuDykXlQf4P7gIZg= Received: by 10.210.53.1 with SMTP id b1mr35337eba.20.1249681603082; Fri, 07 Aug 2009 14:46:43 -0700 (PDT) Received: from lenovo.mimichou.home (home.mimichou.net [82.67.132.19]) by mx.google.com with ESMTPS id 28sm4249990eye.34.2009.08.07.14.46.42 (version=TLSv1/SSLv3 cipher=RC4-MD5); Fri, 07 Aug 2009 14:46:42 -0700 (PDT) From: Florian Fainelli Date: Fri, 7 Aug 2009 23:46:40 +0200 Subject: [PATCH 3/8] bcm63xx: register GPIO-connected LEDs for known references designs MIME-Version: 1.0 X-UID: 1180 X-Length: 6287 To: Ralf Baechle Cc: Maxime Bizon , linux-mips@linux-mips.org Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Content-Disposition: inline Message-Id: <200908072346.41096.florian@openwrt.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23855 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips This patch makes the board code register GPIO-connected LEDs for which we know the mapping since they are reference designs. Signed-off-by: Florian Fainelli --- diff --git a/arch/mips/bcm63xx/boards/board_bcm963xx.c b/arch/mips/bcm63xx/boards/board_bcm963xx.c index 668abdb..8bc4966 100644 --- a/arch/mips/bcm63xx/boards/board_bcm963xx.c +++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c @@ -51,6 +51,36 @@ static struct board_info __initdata board_96348r = { .has_phy = 1, .use_internal_phy = 1, }, + + .leds = { + { + .name = "adsl-fail", + .gpio = 2, + .active_low = 1, + }, + { + .name = "ppp", + .gpio = 3, + .active_low = 1, + }, + { + .name = "ppp-fail", + .gpio = 4, + .active_low = 1, + }, + { + .name = "power", + .gpio = 0, + .active_low = 1, + .default_trigger = "default-on", + + }, + { + .name = "stop", + .gpio = 1, + .active_low = 1, + }, + }, }; static struct board_info __initdata board_96348gw_10 = { @@ -81,6 +111,35 @@ static struct board_info __initdata board_96348gw_10 = { .cs = 2, .ext_irq = 2, }, + + .leds = { + { + .name = "adsl-fail", + .gpio = 2, + .active_low = 1, + }, + { + .name = "ppp", + .gpio = 3, + .active_low = 1, + }, + { + .name = "ppp-fail", + .gpio = 4, + .active_low = 1, + }, + { + .name = "power", + .gpio = 0, + .active_low = 1, + .default_trigger = "default-on", + }, + { + .name = "stop", + .gpio = 1, + .active_low = 1, + }, + }, }; static struct board_info __initdata board_96348gw_11 = { @@ -105,6 +164,35 @@ static struct board_info __initdata board_96348gw_11 = { .has_ohci0 = 1, .has_pccard = 1, .has_ehci0 = 1, + + .leds = { + { + .name = "adsl-fail", + .gpio = 2, + .active_low = 1, + }, + { + .name = "ppp", + .gpio = 3, + .active_low = 1, + }, + { + .name = "ppp-fail", + .gpio = 4, + .active_low = 1, + }, + { + .name = "power", + .gpio = 0, + .active_low = 1, + .default_trigger = "default-on", + }, + { + .name = "stop", + .gpio = 1, + .active_low = 1, + }, + }, }; static struct board_info __initdata board_96348gw = { @@ -133,6 +221,35 @@ static struct board_info __initdata board_96348gw = { .ext_irq = 2, .cs = 2, }, + + .leds = { + { + .name = "adsl-fail", + .gpio = 2, + .active_low = 1, + }, + { + .name = "ppp", + .gpio = 3, + .active_low = 1, + }, + { + .name = "ppp-fail", + .gpio = 4, + .active_low = 1, + }, + { + .name = "power", + .gpio = 0, + .active_low = 1, + .default_trigger = "default-on", + }, + { + .name = "stop", + .gpio = 1, + .active_low = 1, + }, + }, }; static struct board_info __initdata board_FAST2404 = { @@ -225,6 +342,33 @@ static struct board_info __initdata board_96358vw = { .has_ohci0 = 1, .has_pccard = 1, .has_ehci0 = 1, + + .leds = { + { + .name = "adsl-fail", + .gpio = 15, + .active_low = 1, + }, + { + .name = "ppp", + .gpio = 22, + .active_low = 1, + }, + { + .name = "ppp-fail", + .gpio = 23, + .active_low = 1, + }, + { + .name = "power", + .gpio = 4, + .default_trigger = "default-on", + }, + { + .name = "stop", + .gpio = 5, + }, + }, }; static struct board_info __initdata board_96358vw2 = { @@ -249,6 +393,29 @@ static struct board_info __initdata board_96358vw2 = { .has_ohci0 = 1, .has_pccard = 1, .has_ehci0 = 1, + + .leds = { + { + .name = "adsl", + .gpio = 22, + .active_low = 1, + }, + { + .name = "ppp-fail", + .gpio = 23, + }, + { + .name = "power", + .gpio = 5, + .active_low = 1, + .default_trigger = "default-on", + }, + { + .name = "stop", + .gpio = 4, + .active_low = 1, + }, + }, }; static struct board_info __initdata board_AGPFS0 = { @@ -505,6 +672,14 @@ static struct ssb_sprom bcm63xx_sprom = { }; #endif +static struct gpio_led_platform_data bcm63xx_led_data; + +static struct platform_device bcm63xx_gpio_leds = { + .name = "leds-gpio", + .id = 0, + .dev.platform_data = &bcm63xx_led_data, +}; + /* * third stage init callback, register all board devices. */ @@ -553,6 +728,11 @@ int __init board_register_devices(void) platform_device_register(&mtd_dev); + bcm63xx_led_data.num_leds = ARRAY_SIZE(board.leds); + bcm63xx_led_data.leds = board.leds; + + platform_device_register(&bcm63xx_gpio_leds); + return 0; } diff --git a/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h b/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h index 9fde025..6479090 100644 --- a/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h +++ b/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h @@ -2,6 +2,8 @@ #define BOARD_BCM963XX_H_ #include +#include +#include #include #include @@ -50,6 +52,9 @@ struct board_info { /* DSP config */ struct bcm63xx_dsp_platform_data dsp; + + /* GPIO LEDs */ + struct gpio_led leds[5]; }; #endif /* ! BOARD_BCM963XX_H_ */ From f.fainelli@gmail.com Fri Aug 7 23:48:19 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 07 Aug 2009 23:48:27 +0200 (CEST) Received: from ey-out-1920.google.com ([74.125.78.148]:16508 "EHLO ey-out-1920.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492923AbZHGVrJ (ORCPT ); Fri, 7 Aug 2009 23:47:09 +0200 Received: by ey-out-1920.google.com with SMTP id 13so537922eye.54 for ; Fri, 07 Aug 2009 14:47:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:sender:from:date:subject :mime-version:x-uid:x-length:to:cc:content-type :content-transfer-encoding:content-disposition:message-id; bh=L84FbzSxBsHVlseTm02JzCBKJY4jxDFg39Fi9RotkQk=; b=Y1S88PGrUT85Nz2YZi4sxp2R1+tlITAuDIwBL203X0kQiJF2n/2gjBdg+jwyOuV2Fb myoBkzGu4p9jIM14hDJjAk6yLmpndWfUemtRqG4LbRiB9XHioiyzp310wiFMGUZJAKkR L+Okeaa1QWFjxBHJY/GGNIwAhFYoJPXLscYlc= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:from:date:subject:mime-version:x-uid:x-length:to:cc :content-type:content-transfer-encoding:content-disposition :message-id; b=QPnjUtVLWffxGRnQq/jcq2aXFj24zCXpaf2jjRXd+Pa+STJgLk/nNvakg5Vm19TKPA c5aKafeg3Y4HJjjJQ2E8yoAlbuqaWPbqj01qWaLoow1rwrC9xtEI1X1l4H3F5hZRClmo kAF3lJZBsC50mHOxL4C0WrvP0A6DwBxLwaIoI= Received: by 10.210.20.6 with SMTP id 6mr1980320ebt.59.1249681607262; Fri, 07 Aug 2009 14:46:47 -0700 (PDT) Received: from lenovo.mimichou.home (home.mimichou.net [82.67.132.19]) by mx.google.com with ESMTPS id 28sm4262227eyg.52.2009.08.07.14.46.46 (version=TLSv1/SSLv3 cipher=RC4-MD5); Fri, 07 Aug 2009 14:46:47 -0700 (PDT) From: Florian Fainelli Date: Fri, 7 Aug 2009 23:46:44 +0200 Subject: [PATCH 4/8] bcm63xx: add support for the BCM6338 SoC MIME-Version: 1.0 X-UID: 1181 X-Length: 14248 To: Ralf Baechle Cc: Maxime Bizon , linux-mips@linux-mips.org Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Content-Disposition: inline Message-Id: <200908072346.45245.florian@openwrt.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23856 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips This patch adds support for the BCM6338 SoC, it is very similar to BCM6348 except that: - the CPU frequency is not locked on PLL and is fixed - there is only one Ethernet MAC therefore the DMA zone is twice smaller Signed-off-by: Florian Fainelli --- diff --git a/arch/mips/bcm63xx/Kconfig b/arch/mips/bcm63xx/Kconfig index 8c192e7..325f69a 100644 --- a/arch/mips/bcm63xx/Kconfig +++ b/arch/mips/bcm63xx/Kconfig @@ -1,6 +1,13 @@ menu "CPU support" depends on BCM63XX +config BCM63XX_CPU_6338 + bool "support 6338 CPU" + select HW_HAS_PCI + select USB_ARCH_HAS_OHCI + select USB_OHCI_BIG_ENDIAN_DESC + select USB_OHCI_BIG_ENDIAN_MMIO + config BCM63XX_CPU_6348 bool "support 6348 CPU" select HW_HAS_PCI diff --git a/arch/mips/bcm63xx/clk.c b/arch/mips/bcm63xx/clk.c index ae1f41f..d189965 100644 --- a/arch/mips/bcm63xx/clk.c +++ b/arch/mips/bcm63xx/clk.c @@ -49,7 +49,9 @@ static void enet_misc_set(struct clk *clk, int enable) { u32 mask; - if (BCMCPU_IS_6348()) + if (BCMCPU_IS_6338()) + mask = CKCTL_6338_ENET_EN; + else if (BCMCPU_IS_6348()) mask = CKCTL_6348_ENET_EN; else /* BCMCPU_IS_6358 */ @@ -143,7 +145,9 @@ static void spi_set(struct clk *clk, int enable) { u32 mask; - if (BCMCPU_IS_6348()) + if (BCMCPU_IS_6338()) + mask = CKCTL_6338_SPI_EN; + else if (BCMCPU_IS_6348()) mask = CKCTL_6348_SPI_EN; else /* BCMCPU_IS_6358 */ diff --git a/arch/mips/bcm63xx/cpu.c b/arch/mips/bcm63xx/cpu.c index 9d6cfce..cb41855 100644 --- a/arch/mips/bcm63xx/cpu.c +++ b/arch/mips/bcm63xx/cpu.c @@ -4,6 +4,7 @@ * for more details. * * Copyright (C) 2008 Maxime Bizon + * Copyright (C) 2009 Florian Fainelli */ #include @@ -26,6 +27,42 @@ static unsigned int bcm63xx_cpu_freq; static unsigned int bcm63xx_memory_size; /* + * 6338 register sets and irqs + */ +static const unsigned long bcm96338_regs_base[] = { + [RSET_DSL_LMEM] = BCM_6338_DSL_LMEM_BASE, + [RSET_PERF] = BCM_6338_PERF_BASE, + [RSET_TIMER] = BCM_6338_TIMER_BASE, + [RSET_WDT] = BCM_6338_WDT_BASE, + [RSET_UART0] = BCM_6338_UART0_BASE, + [RSET_GPIO] = BCM_6338_GPIO_BASE, + [RSET_SPI] = BCM_6338_SPI_BASE, + [RSET_OHCI0] = BCM_6338_OHCI0_BASE, + [RSET_OHCI_PRIV] = BCM_6338_OHCI_PRIV_BASE, + [RSET_USBH_PRIV] = BCM_6338_USBH_PRIV_BASE, + [RSET_UDC0] = BCM_6338_UDC0_BASE, + [RSET_MPI] = BCM_6338_MPI_BASE, + [RSET_PCMCIA] = BCM_6338_PCMCIA_BASE, + [RSET_SDRAM] = BCM_6338_SDRAM_BASE, + [RSET_DSL] = BCM_6338_DSL_BASE, + [RSET_ENET0] = BCM_6338_ENET0_BASE, + [RSET_ENET1] = BCM_6338_ENET1_BASE, + [RSET_ENETDMA] = BCM_6338_ENETDMA_BASE, + [RSET_MEMC] = BCM_6338_MEMC_BASE, + [RSET_DDR] = BCM_6338_DDR_BASE, +}; + +static const int bcm96338_irqs[] = { + [IRQ_TIMER] = BCM_6338_TIMER_IRQ, + [IRQ_UART0] = BCM_6338_UART0_IRQ, + [IRQ_DSL] = BCM_6338_DSL_IRQ, + [IRQ_ENET0] = BCM_6338_ENET0_IRQ, + [IRQ_ENET_PHY] = BCM_6338_ENET_PHY_IRQ, + [IRQ_ENET0_RXDMA] = BCM_6338_ENET0_RXDMA_IRQ, + [IRQ_ENET0_TXDMA] = BCM_6338_ENET0_TXDMA_IRQ, +}; + +/* * 6348 register sets and irqs */ static const unsigned long bcm96348_regs_base[] = { @@ -137,6 +174,10 @@ static unsigned int detect_cpu_clock(void) { unsigned int tmp, n1 = 0, n2 = 0, m1 = 0; + /* BCM6338 has a fixed 240 Mhz frequency */ + if (BCMCPU_IS_6338()) + return 240000000; + /* * frequency depends on PLL configuration: */ @@ -170,7 +211,7 @@ static unsigned int detect_memory_size(void) unsigned int cols = 0, rows = 0, is_32bits = 0, banks = 0; u32 val; - if (BCMCPU_IS_6348()) { + if (BCMCPU_IS_6338() || BCMCPU_IS_6348()) { val = bcm_sdram_readl(SDRAM_CFG_REG); rows = (val & SDRAM_CFG_ROW_MASK) >> SDRAM_CFG_ROW_SHIFT; cols = (val & SDRAM_CFG_COL_MASK) >> SDRAM_CFG_COL_SHIFT; @@ -204,6 +245,13 @@ void __init bcm63xx_cpu_init(void) expected_cpu_id = 0; switch (c->cputype) { + /* BCM6338 as the same PrId as BCM3302 see + * arch/mips/kernel/cpu-probe.c */ + case CPU_BCM3302: + expected_cpu_id = BCM6338_CPU_ID; + bcm63xx_regs_base = bcm96338_regs_base; + bcm63xx_irqs = bcm96338_irqs; + break; case CPU_BCM6348: expected_cpu_id = BCM6348_CPU_ID; bcm63xx_regs_base = bcm96348_regs_base; diff --git a/arch/mips/bcm63xx/dev-enet.c b/arch/mips/bcm63xx/dev-enet.c index 188fa66..9f544ba 100644 --- a/arch/mips/bcm63xx/dev-enet.c +++ b/arch/mips/bcm63xx/dev-enet.c @@ -107,7 +107,10 @@ int __init bcm63xx_enet_register(int unit, if (!shared_device_registered) { shared_res[0].start = bcm63xx_regset_address(RSET_ENETDMA); shared_res[0].end = shared_res[0].start; - shared_res[0].end += RSET_ENETDMA_SIZE - 1; + if (BCMCPU_IS_6338()) + shared_res[0].end += (RSET_ENETDMA_SIZE / 2) - 1; + else + shared_res[0].end += (RSET_ENETDMA_SIZE) - 1; ret = platform_device_register(&bcm63xx_enet_shared_device); if (ret) diff --git a/arch/mips/bcm63xx/prom.c b/arch/mips/bcm63xx/prom.c index d97ceed..6a41acb 100644 --- a/arch/mips/bcm63xx/prom.c +++ b/arch/mips/bcm63xx/prom.c @@ -25,7 +25,9 @@ void __init prom_init(void) bcm_wdt_writel(WDT_STOP_2, WDT_CTL_REG); /* disable all hardware blocks clock for now */ - if (BCMCPU_IS_6348()) + if (BCMCPU_IS_6338()) + mask = CKCTL_6338_ALL_SAFE_EN; + else if (BCMCPU_IS_6348()) mask = CKCTL_6348_ALL_SAFE_EN; else /* BCMCPU_IS_6358() */ diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h index 29b61fd..3c107d0 100644 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h @@ -9,6 +9,7 @@ * compile time if only one CPU support is enabled (idea stolen from * arm mach-types) */ +#define BCM6338_CPU_ID 0x6338 #define BCM6348_CPU_ID 0x6348 #define BCM6358_CPU_ID 0x6358 @@ -17,6 +18,19 @@ u16 __bcm63xx_get_cpu_id(void); u16 bcm63xx_get_cpu_rev(void); unsigned int bcm63xx_get_cpu_freq(void); +#ifdef CONFIG_BCM63XX_CPU_6338 +# ifdef bcm63xx_get_cpu_id +# undef bcm63xx_get_cpu_id +# define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id() +# define BCMCPU_RUNTIME_DETECT +# else +# define bcm63xx_get_cpu_id() BCM6338_CPU_ID +# endif +# define BCMCPU_IS_6338() (bcm63xx_get_cpu_id() == BCM6338_CPU_ID) +#else +# define BCMCPU_IS_6338() (0) +#endif + #ifdef CONFIG_BCM63XX_CPU_6348 # ifdef bcm63xx_get_cpu_id # undef bcm63xx_get_cpu_id @@ -87,6 +101,36 @@ enum bcm63xx_regs_set { #define RSET_PCMCIA_SIZE 12 /* + * 6338 register sets base address + */ +#define BCM_6338_DSL_LMEM_BASE (0xfff00000) +#define BCM_6338_PERF_BASE (0xfffe0000) +#define BCM_6338_BB_BASE (0xfffe0100) +#define BCM_6338_TIMER_BASE (0xfffe0200) +#define BCM_6338_WDT_BASE (0xfffe021c) +#define BCM_6338_UART0_BASE (0xfffe0300) +#define BCM_6338_GPIO_BASE (0xfffe0400) +#define BCM_6338_SPI_BASE (0xfffe0c00) +#define BCM_6338_UDC0_BASE (0xdeadbeef) +#define BCM_6338_USBDMA_BASE (0xfffe2400) +#define BCM_6338_OHCI0_BASE (0xdeadbeef) +#define BCM_6338_OHCI_PRIV_BASE (0xfffe3000) +#define BCM_6338_USBH_PRIV_BASE (0xdeadbeef) +#define BCM_6338_MPI_BASE (0xfffe3160) +#define BCM_6338_PCMCIA_BASE (0xdeadbeef) +#define BCM_6338_SDRAM_REGS_BASE (0xfffe3100) +#define BCM_6338_DSL_BASE (0xfffe1000) +#define BCM_6338_SAR_BASE (0xfffe2000) +#define BCM_6338_UBUS_BASE (0xdeadbeef) +#define BCM_6338_ENET0_BASE (0xfffe2800) +#define BCM_6338_ENET1_BASE (0xdeadbeef) +#define BCM_6338_ENETDMA_BASE (0xfffe2400) +#define BCM_6338_EHCI0_BASE (0xdeadbeef) +#define BCM_6338_SDRAM_BASE (0xfffe3100) +#define BCM_6338_MEMC_BASE (0xdeadbeef) +#define BCM_6338_DDR_BASE (0xdeadbeef) + +/* * 6348 register sets base address */ #define BCM_6348_DSL_LMEM_BASE (0xfff00000) @@ -146,6 +190,52 @@ static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set) #ifdef BCMCPU_RUNTIME_DETECT return bcm63xx_regs_base[set]; #else +#ifdef CONFIG_BCM63XX_CPU_6338 + switch (set) { + case RSET_DSL_LMEM: + return BCM_6338_DSL_LMEM_BASE; + case RSET_PERF: + return BCM_6338_PERF_BASE; + case RSET_TIMER: + return BCM_6338_TIMER_BASE; + case RSET_WDT: + return BCM_6338_WDT_BASE; + case RSET_UART0: + return BCM_6338_UART0_BASE; + case RSET_GPIO: + return BCM_6338_GPIO_BASE; + case RSET_SPI: + return BCM_6338_SPI_BASE; + case RSET_UDC0: + return BCM_6338_UDC0_BASE; + case RSET_OHCI0: + return BCM_6338_OHCI0_BASE; + case RSET_OHCI_PRIV: + return BCM_6338_OHCI_PRIV_BASE; + case RSET_USBH_PRIV: + return BCM_6338_USBH_PRIV_BASE; + case RSET_MPI: + return BCM_6338_MPI_BASE; + case RSET_PCMCIA: + return BCM_6338_PCMCIA_BASE; + case RSET_DSL: + return BCM_6338_DSL_BASE; + case RSET_ENET0: + return BCM_6338_ENET0_BASE; + case RSET_ENET1: + return BCM_6338_ENET1_BASE; + case RSET_ENETDMA: + return BCM_6338_ENETDMA_BASE; + case RSET_EHCI0: + return BCM_6338_EHCI0_BASE; + case RSET_SDRAM: + return BCM_6338_SDRAM_BASE; + case RSET_MEMC: + return BCM_6338_MEMC_BASE; + case RSET_DDR: + return BCM_6338_DDR_BASE; + } +#endif #ifdef CONFIG_BCM63XX_CPU_6348 switch (set) { case RSET_DSL_LMEM: @@ -265,6 +355,27 @@ enum bcm63xx_irq { }; /* + * 6338 irqs + */ +#define BCM_6338_TIMER_IRQ (IRQ_INTERNAL_BASE + 0) +#define BCM_6338_SPI_IRQ (IRQ_INTERNAL_BASE + 1) +#define BCM_6338_UART0_IRQ (IRQ_INTERNAL_BASE + 2) +#define BCM_6338_DG_IRQ (IRQ_INTERNAL_BASE + 4) +#define BCM_6338_DSL_IRQ (IRQ_INTERNAL_BASE + 5) +#define BCM_6338_ATM_IRQ (IRQ_INTERNAL_BASE + 6) +#define BCM_6338_UDC0_IRQ (IRQ_INTERNAL_BASE + 7) +#define BCM_6338_ENET0_IRQ (IRQ_INTERNAL_BASE + 8) +#define BCM_6338_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9) +#define BCM_6338_SDRAM_IRQ (IRQ_INTERNAL_BASE + 10) +#define BCM_6338_USB_CNTL_RX_DMA_IRQ (IRQ_INTERNAL_BASE + 11) +#define BCM_6338_USB_CNTL_TX_DMA_IRQ (IRQ_INTERNAL_BASE + 12) +#define BCM_6338_USB_BULK_RX_DMA_IRQ (IRQ_INTERNAL_BASE + 13) +#define BCM_6338_USB_BULK_TX_DMA_IRQ (IRQ_INTERNAL_BASE + 14) +#define BCM_6338_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 15) +#define BCM_6338_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 16) +#define BCM_6338_SDIO_IRQ (IRQ_INTERNAL_BASE + 17) + +/* * 6348 irqs */ #define BCM_6348_TIMER_IRQ (IRQ_INTERNAL_BASE + 0) diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h index 7b1dbb3..3249e8c 100644 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h @@ -15,6 +15,20 @@ /* Clock Control register */ #define PERF_CKCTL_REG 0x4 +#define CKCTL_6338_ADSLPHY_EN (1 << 0) +#define CKCTL_6338_MPI_EN (1 << 1) +#define CKCTL_6338_DRAM_EN (1 << 2) +#define CKCTL_6338_ENET_EN (1 << 4) +#define CKCTL_6338_USBS_EN (1 << 4) +#define CKCTL_6338_SAR_EN (1 << 5) +#define CKCTL_6338_SPI_EN (1 << 9) + +#define CKCTL_6338_ALL_SAFE_EN (CKCTL_6338_ADSLPHY_EN | \ + CKCTL_6338_MPI_EN | \ + CKCTL_6338_ENET_EN | \ + CKCTL_6338_SAR_EN | \ + CKCTL_6338_SPI_EN) + #define CKCTL_6348_ADSLPHY_EN (1 << 0) #define CKCTL_6348_MPI_EN (1 << 1) #define CKCTL_6348_SDRAM_EN (1 << 2) @@ -83,6 +97,25 @@ /* Soft Reset register */ #define PERF_SOFTRESET_REG 0x28 +#define SOFTRESET_6338_SPI_MASK (1 << 0) +#define SOFTRESET_6338_ENET_MASK (1 << 2) +#define SOFTRESET_6338_USBH_MASK (1 << 3) +#define SOFTRESET_6338_USBS_MASK (1 << 4) +#define SOFTRESET_6338_ADSL_MASK (1 << 5) +#define SOFTRESET_6338_DMAMEM_MASK (1 << 6) +#define SOFTRESET_6338_SAR_MASK (1 << 7) +#define SOFTRESET_6338_ACLC_MASK (1 << 8) +#define SOFTRESET_6338_ADSLMIPSPLL_MASK (1 << 10) +#define SOFTRESET_6338_ALL (SOFTRESET_6338_SPI_MASK | \ + SOFTRESET_6338_ENET_MASK | \ + SOFTRESET_6338_USBH_MASK | \ + SOFTRESET_6338_USBS_MASK | \ + SOFTRESET_6338_ADSL_MASK | \ + SOFTRESET_6338_DMAMEM_MASK | \ + SOFTRESET_6338_SAR_MASK | \ + SOFTRESET_6338_ACLC_MASK | \ + SOFTRESET_6338_ADSLMIPSPLL_MASK) + #define SOFTRESET_6348_SPI_MASK (1 << 0) #define SOFTRESET_6348_ENET_MASK (1 << 2) #define SOFTRESET_6348_USBH_MASK (1 << 3) diff --git a/arch/mips/include/asm/mach-bcm63xx/cpu-feature-overrides.h b/arch/mips/include/asm/mach-bcm63xx/cpu-feature-overrides.h index 1a5c4b1..80c3aa2 100644 --- a/arch/mips/include/asm/mach-bcm63xx/cpu-feature-overrides.h +++ b/arch/mips/include/asm/mach-bcm63xx/cpu-feature-overrides.h @@ -24,7 +24,7 @@ #define cpu_has_smartmips 0 #define cpu_has_vtag_icache 0 -#if !defined(BCMCPU_RUNTIME_DETECT) && defined(CONFIG_BCMCPU_IS_6348) +#if !defined(BCMCPU_RUNTIME_DETECT) && (defined(CONFIG_BCMCPU_IS_6348) || defined(CONFIG_CPU_IS_6338)) #define cpu_has_dc_aliases 0 #endif From f.fainelli@gmail.com Fri Aug 7 23:48:44 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 07 Aug 2009 23:48:51 +0200 (CEST) Received: from mail-ew0-f216.google.com ([209.85.219.216]:52655 "EHLO mail-ew0-f216.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492945AbZHGVrK (ORCPT ); Fri, 7 Aug 2009 23:47:10 +0200 Received: by mail-ew0-f216.google.com with SMTP id 12so2282279ewy.0 for ; Fri, 07 Aug 2009 14:47:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:sender:from:date:subject :mime-version:x-uid:x-length:to:cc:content-type :content-transfer-encoding:content-disposition:message-id; bh=RjjUo1rC/zm9NLoUtt5P8Qr560gl1iAf7DlSLLkZ2aA=; b=tdK5BEcHWe1lh/CfwZMeij+3InPvzBVqlqBBhvmj28hfMioPd2vp3ZPUIS8uRPC+Bz b22lcn1TFteldgbJ4AvttsZs4jZveZE2hjhCZDvj/PJaPWJQouBk2cV1PeorgeQdjXAb Z57RVm1aGAcIKwtrjzix3KlW4g2HrXXNdfXJw= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:from:date:subject:mime-version:x-uid:x-length:to:cc :content-type:content-transfer-encoding:content-disposition :message-id; b=gbzqfTG07WDrkrtu4qz1ZqADWfmBhb1waaoi5GEBpwBsaOuCjSkk7eYxrR6itt0m7W 9Fb/nIak1UsUioYsVaQnehyHoHeYDc8jkXf/tP7ShGTvjstnrEWjaSaXr8FXq952Mih2 fM5B6VG5+rJmluNxGGlXi4heO8h9T9ngBppKw= Received: by 10.211.179.6 with SMTP id g6mr1992971ebp.32.1249681629854; Fri, 07 Aug 2009 14:47:09 -0700 (PDT) Received: from lenovo.mimichou.home (home.mimichou.net [82.67.132.19]) by mx.google.com with ESMTPS id 28sm4262227eyg.52.2009.08.07.14.47.09 (version=TLSv1/SSLv3 cipher=RC4-MD5); Fri, 07 Aug 2009 14:47:09 -0700 (PDT) From: Florian Fainelli Date: Fri, 7 Aug 2009 23:46:52 +0200 Subject: [PATCH 5/8] bcm63xx: add bcm96338w and bcm96338gw board support MIME-Version: 1.0 X-UID: 1182 X-Length: 3107 To: Ralf Baechle Cc: Maxime Bizon , linux-mips@linux-mips.org Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Content-Disposition: inline Message-Id: <200908072346.52578.florian@openwrt.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23857 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips This patch adds support for the bcm96338w and bcm96338gw reference designs. Tested on bcm96338w. Signed-off-by: Florian Fainelli --- diff --git a/arch/mips/bcm63xx/boards/board_bcm963xx.c b/arch/mips/bcm63xx/boards/board_bcm963xx.c index 8bc4966..e639438 100644 --- a/arch/mips/bcm63xx/boards/board_bcm963xx.c +++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c @@ -37,6 +37,93 @@ static unsigned int mac_addr_used; static struct board_info board; /* + * known 6338 boards + */ +#ifdef CONFIG_BCM63XX_CPU_6338 +static struct board_info __initdata board_96338gw = { + .name = "96338GW", + .expected_cpu_id = 0x6338, + + .has_enet0 = 1, + .enet0 = { + .force_speed_100 = 1, + .force_duplex_full = 1, + }, + + .has_ohci0 = 1, + + .leds = { + { + .name = "adsl", + .gpio = 3, + .active_low = 1, + }, + { + .name = "ses", + .gpio = 5, + .active_low = 1, + }, + { + .name = "ppp-fail", + .gpio = 4, + .active_low = 1, + }, + { + .name = "power", + .gpio = 0, + .active_low = 1, + .default_trigger = "default-on", + }, + { + .name = "stop", + .gpio = 1, + .active_low = 1, + } + }, +}; + +static struct board_info __initdata board_96338w = { + .name = "96338W", + .expected_cpu_id = 0x6338, + + .has_enet0 = 1, + .enet0 = { + .force_speed_100 = 1, + .force_duplex_full = 1, + }, + + .leds = { + { + .name = "adsl", + .gpio = 3, + .active_low = 1, + }, + { + .name = "ses", + .gpio = 5, + .active_low = 1, + }, + { + .name = "ppp-fail", + .gpio = 4, + .active_low = 1, + }, + { + .name = "power", + .gpio = 0, + .active_low = 1, + .default_trigger = "default-on", + }, + { + .name = "stop", + .gpio = 1, + .active_low = 1, + }, + }, +}; +#endif + +/* * known 6348 boards */ #ifdef CONFIG_BCM63XX_CPU_6348 @@ -445,6 +532,10 @@ static struct board_info __initdata board_AGPFS0 = { * all boards */ static const struct board_info __initdata *bcm963xx_boards[] = { +#ifdef CONFIG_BCM63XX_CPU_6338 + &board_96338gw, + &board_96338w, +#endif #ifdef CONFIG_BCM63XX_CPU_6348 &board_96348r, &board_96348gw, From f.fainelli@gmail.com Fri Aug 7 23:49:08 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 07 Aug 2009 23:49:15 +0200 (CEST) Received: from ey-out-1920.google.com ([74.125.78.145]:53606 "EHLO ey-out-1920.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492977AbZHGVrn (ORCPT ); Fri, 7 Aug 2009 23:47:43 +0200 Received: by ey-out-1920.google.com with SMTP id 13so537975eye.54 for ; Fri, 07 Aug 2009 14:47:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:sender:from:date:subject :mime-version:x-uid:x-length:to:cc:content-type :content-transfer-encoding:content-disposition:message-id; bh=Px22Q6iqwDoHgBJdPMiyxCqR2WKiWyEYIR0VCsjgUvU=; b=UjtGTeg+FEyN8+6EKsYWS0iUe+85Vu/tEIIP10TUFjzmHt3S8RtivYKVcKmVPELMnb N5A1u7m/SH76hmAJnInaiz/CJVLgvlmgXWdgMxXcqPD1+2pXc29fn9YwMJTRzOSN9Mdm xJ5woAm2BoC5R0KJCgfMHIokRhQ/EYX6+Xgwo= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:from:date:subject:mime-version:x-uid:x-length:to:cc :content-type:content-transfer-encoding:content-disposition :message-id; b=nVDiXjdmxzr0JLHJQdIaIAN4Knm0HaC/fF95/CvSQN9G16ssvwAMfDw4Mhj5mFjQfz eIXYksYeSoHI8DcUOGoJkVP26wLtCK5KlJf1DO3lwUo3AbdYsjP7lS4ZGjIZ6Y7tWgqS Wd6sUOPyvaSsWlK/SShFg1nX73ZE0Bh4p+ViA= Received: by 10.210.102.9 with SMTP id z9mr1999060ebb.16.1249681661990; Fri, 07 Aug 2009 14:47:41 -0700 (PDT) Received: from lenovo.mimichou.home (home.mimichou.net [82.67.132.19]) by mx.google.com with ESMTPS id 28sm4262227eyg.52.2009.08.07.14.47.41 (version=TLSv1/SSLv3 cipher=RC4-MD5); Fri, 07 Aug 2009 14:47:41 -0700 (PDT) From: Florian Fainelli Date: Fri, 7 Aug 2009 23:47:04 +0200 Subject: [PATCH 7/8] bcm63xx: add basic support for bcm96345gw2 design MIME-Version: 1.0 X-UID: 1184 X-Length: 2925 To: Ralf Baechle Cc: Maxime Bizon , linux-mips@linux-mips.org Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Content-Disposition: inline Message-Id: <200908072347.04899.florian@openwrt.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23858 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips This patch adds basic support for the bcm96345gw2 reference design (e.g: Siemens SE515) and make it boot up to user-space. Integrated peripherals support needs some more work. Signed-off-by: Florian Fainelli --- diff --git a/arch/mips/bcm63xx/boards/board_bcm963xx.c b/arch/mips/bcm63xx/boards/board_bcm963xx.c index e639438..17a8636 100644 --- a/arch/mips/bcm63xx/boards/board_bcm963xx.c +++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c @@ -124,6 +124,16 @@ static struct board_info __initdata board_96338w = { #endif /* + * known 6345 boards + */ +#ifdef CONFIG_BCM63XX_CPU_6345 +static struct board_info __initdata board_96345gw2 = { + .name = "96345GW2", + .expected_cpu_id = 0x6345, +}; +#endif + +/* * known 6348 boards */ #ifdef CONFIG_BCM63XX_CPU_6348 @@ -536,6 +546,9 @@ static const struct board_info __initdata *bcm963xx_boards[] = { &board_96338gw, &board_96338w, #endif +#ifdef CONFIG_BCM63XX_CPU_6345 + &board_96345gw2, +#endif #ifdef CONFIG_BCM63XX_CPU_6348 &board_96348r, &board_96348gw, @@ -562,10 +575,16 @@ void __init board_prom_init(void) u8 *boot_addr, *cfe, *p; char cfe_version[32]; u32 val; - - /* read base address of boot chip select (0) */ - val = bcm_mpi_readl(MPI_CSBASE_REG(0)); - val &= MPI_CSBASE_BASE_MASK; + + /* read base address of boot chip select (0) + * 6345 does not have MPI but boots from standard + * MIPS Flash address */ + if (BCMCPU_IS_6345()) + val = 0x1fc00000; + else { + val = bcm_mpi_readl(MPI_CSBASE_REG(0)); + val &= MPI_CSBASE_BASE_MASK; + } boot_addr = (u8 *)KSEG1ADDR(val); /* dump cfe version */ @@ -812,8 +831,12 @@ int __init board_register_devices(void) #endif /* read base address of boot chip select (0) */ - val = bcm_mpi_readl(MPI_CSBASE_REG(0)); - val &= MPI_CSBASE_BASE_MASK; + if (BCMCPU_IS_6345()) + val = 0x1fc00000; + else { + val = bcm_mpi_readl(MPI_CSBASE_REG(0)); + val &= MPI_CSBASE_BASE_MASK; + } mtd_resources[0].start = val; mtd_resources[0].end = 0x1FFFFFFF; From f.fainelli@gmail.com Fri Aug 7 23:49:32 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 07 Aug 2009 23:49:39 +0200 (CEST) Received: from mail-ew0-f216.google.com ([209.85.219.216]:34886 "EHLO mail-ew0-f216.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492978AbZHGVrs (ORCPT ); Fri, 7 Aug 2009 23:47:48 +0200 Received: by ewy12 with SMTP id 12so2283012ewy.0 for ; Fri, 07 Aug 2009 14:47:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:sender:from:date:subject :mime-version:x-uid:x-length:to:cc:content-type :content-transfer-encoding:content-disposition:message-id; bh=VajaOkDHtOJvKAIfCmp2L8FrWEEtaj1xHR/ddvvJFK4=; b=RA7IUuzms/sQGBtQeDCxDt91oZAU5pbVEqQ+Hv4onW0Vs5erV5zzWIbygdYXPVkeH6 I7rjwEEyJ8VGP290hf4SyCsIRwWV5VqnTZtfT1o2/jgaEjkxRknOhScoSIZM5MHIhb6R zvqcHidmY0JWiUTg86VPq2Oe/Q2U8l0MHi+IM= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:from:date:subject:mime-version:x-uid:x-length:to:cc :content-type:content-transfer-encoding:content-disposition :message-id; b=fEcmusTQUzdwJil7Iss6baZKw+IyTPA3cnC7lHNN6FSUS4eT12UP1bZ4SMHYj+4D+m tp9pwU1AwwTpRjtCgECtnYGvuiIeGANu0hrSO7CaYmnPxbBdxMFQNLjSdfcBZ5OZ3gAi G66/7xtZPkq4swPnjaAQaOTqjMWPcCXgF0F40= Received: by 10.210.62.3 with SMTP id k3mr1989281eba.36.1249681662952; Fri, 07 Aug 2009 14:47:42 -0700 (PDT) Received: from lenovo.mimichou.home (home.mimichou.net [82.67.132.19]) by mx.google.com with ESMTPS id 28sm4262227eyg.52.2009.08.07.14.47.42 (version=TLSv1/SSLv3 cipher=RC4-MD5); Fri, 07 Aug 2009 14:47:42 -0700 (PDT) From: Florian Fainelli Date: Fri, 7 Aug 2009 23:47:15 +0200 Subject: [PATCH 8/8] bcm63xx: prepare for on-board watchdog support MIME-Version: 1.0 X-UID: 1185 X-Length: 3927 To: Ralf Baechle Cc: linux-mips@linux-mips.org, Maxime Bizon Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Content-Disposition: inline Message-Id: <200908072347.16203.florian@openwrt.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23859 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips This patch registers the watchdog platform_device that we are going to use in the watchdog platform_driver in a subsequent patch. Signed-off-by: Florian Fainelli --- diff --git a/arch/mips/bcm63xx/Makefile b/arch/mips/bcm63xx/Makefile index 70ba038..a4abc11 100644 --- a/arch/mips/bcm63xx/Makefile +++ b/arch/mips/bcm63xx/Makefile @@ -5,6 +5,7 @@ obj-y += dev-usb-ohci.o obj-y += dev-usb-ehci.o obj-y += dev-enet.o obj-y += dev-dsp.o +obj-y += dev-wdt.o obj-$(CONFIG_EARLY_PRINTK) += early_printk.o obj-y += boards/ diff --git a/arch/mips/bcm63xx/boards/board_bcm963xx.c b/arch/mips/bcm63xx/boards/board_bcm963xx.c index 17a8636..e6a7b4f 100644 --- a/arch/mips/bcm63xx/boards/board_bcm963xx.c +++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #define PFX "board_bcm963xx: " @@ -798,6 +799,7 @@ int __init board_register_devices(void) u32 val; bcm63xx_uart_register(); + bcm63xx_wdt_register(); if (board.has_pccard) bcm63xx_pcmcia_register(); diff --git a/arch/mips/bcm63xx/dev-wdt.c b/arch/mips/bcm63xx/dev-wdt.c new file mode 100644 index 0000000..6e18489 --- /dev/null +++ b/arch/mips/bcm63xx/dev-wdt.c @@ -0,0 +1,36 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2008 Florian Fainelli + */ + +#include +#include +#include +#include + +static struct resource wdt_resources[] = { + { + .start = -1, /* filled at runtime */ + .end = -1, /* filled at runtime */ + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device bcm63xx_wdt_device = { + .name = "bcm63xx-wdt", + .id = 0, + .num_resources = ARRAY_SIZE(wdt_resources), + .resource = wdt_resources, +}; + +int __init bcm63xx_wdt_register(void) +{ + wdt_resources[0].start = bcm63xx_regset_address(RSET_WDT); + wdt_resources[0].end = wdt_resources[0].start; + wdt_resources[0].end += RSET_WDT_SIZE - 1; + + return platform_device_register(&bcm63xx_wdt_device); +} diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_wdt.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_wdt.h new file mode 100644 index 0000000..4aae2c7 --- /dev/null +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_wdt.h @@ -0,0 +1,6 @@ +#ifndef BCM63XX_DEV_WDT_H_ +#define BCM63XX_DEV_WDT_H_ + +int bcm63xx_wdt_register(void); + +#endif /* BCM63XX_DEV_WDT_H_ */ From f.fainelli@gmail.com Fri Aug 7 23:49:56 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 07 Aug 2009 23:50:04 +0200 (CEST) Received: from mail-ew0-f216.google.com ([209.85.219.216]:57177 "EHLO mail-ew0-f216.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492984AbZHGVru (ORCPT ); Fri, 7 Aug 2009 23:47:50 +0200 Received: by ewy12 with SMTP id 12so2283026ewy.0 for ; Fri, 07 Aug 2009 14:47:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:sender:from:date:subject :mime-version:x-uid:x-length:to:cc:content-type :content-transfer-encoding:content-disposition:message-id; bh=2/s/llznYIKaL0zNc7KHJ4uvf4Aappy63bH4A4yO0gk=; b=IexhnaXXqqZwqkVNutrxvCMAUzE1x2A+EE2HbvNm4uHTuNHRkC2IWwq5QXG+Mq1Tm4 2p8ccvrKcTG4XyXTC2UtYYgpMcCeGSrMZ5xRQFpHSTCvK7VrhoX6XfvBNdc8bXv8Syly NdJWwLgG+LnF4lr6cIWoEmB3E2eKeM4ZayFxc= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:from:date:subject:mime-version:x-uid:x-length:to:cc :content-type:content-transfer-encoding:content-disposition :message-id; b=bNjFbrYaAMC8c9CR1mT7nfH8OyoFF4htO5yFsj3AXF7SJq9HwJUQSmEaB1tGuZXrIk 7b+5IPsbX2G3UkXr6ArDN9TLOpktVWqbS+4mmfqoD+ImfsgHBhn+XiYrYtydoBhfzN9s 9Gd11z2mnzg012PEc3aiwDfN+ThvjSa4wTWhw= Received: by 10.210.63.18 with SMTP id l18mr1965991eba.67.1249681630865; Fri, 07 Aug 2009 14:47:10 -0700 (PDT) Received: from lenovo.mimichou.home (home.mimichou.net [82.67.132.19]) by mx.google.com with ESMTPS id 28sm4262227eyg.52.2009.08.07.14.47.10 (version=TLSv1/SSLv3 cipher=RC4-MD5); Fri, 07 Aug 2009 14:47:10 -0700 (PDT) From: Florian Fainelli Date: Fri, 7 Aug 2009 23:46:58 +0200 Subject: [PATCH 6/8] bcm63xx: add support for BCM6345 SoC MIME-Version: 1.0 X-UID: 1183 X-Length: 12527 To: Ralf Baechle Cc: Maxime Bizon , linux-mips@linux-mips.org Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Content-Disposition: inline Message-Id: <200908072346.58740.florian@openwrt.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23860 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips This patch adds support for the BCM6345 SoC. This is the very first generation of BCM63xx. A couple of modifications needs to be made: - bcm6345 does not support r4k_wait, disable it - bcm6345 does not have SPI or MPI Signed-off-by: Florian Fainelli --- diff --git a/arch/mips/bcm63xx/Kconfig b/arch/mips/bcm63xx/Kconfig index 325f69a..4aa21e8 100644 --- a/arch/mips/bcm63xx/Kconfig +++ b/arch/mips/bcm63xx/Kconfig @@ -8,6 +8,11 @@ config BCM63XX_CPU_6338 select USB_OHCI_BIG_ENDIAN_DESC select USB_OHCI_BIG_ENDIAN_MMIO +config BCM63XX_CPU_6345 + bool "support 6345 CPU" + select USB_OHCI_BIG_ENDIAN_DESC + select USB_OHCI_BIG_ENDIAN_MMIO + config BCM63XX_CPU_6348 bool "support 6348 CPU" select HW_HAS_PCI diff --git a/arch/mips/bcm63xx/clk.c b/arch/mips/bcm63xx/clk.c index d189965..4e2309a 100644 --- a/arch/mips/bcm63xx/clk.c +++ b/arch/mips/bcm63xx/clk.c @@ -51,6 +51,8 @@ static void enet_misc_set(struct clk *clk, int enable) if (BCMCPU_IS_6338()) mask = CKCTL_6338_ENET_EN; + else if (BCMCPU_IS_6345()) + mask = CKCTL_6345_ENET_EN; else if (BCMCPU_IS_6348()) mask = CKCTL_6348_ENET_EN; else diff --git a/arch/mips/bcm63xx/cpu.c b/arch/mips/bcm63xx/cpu.c index cb41855..79b76a4 100644 --- a/arch/mips/bcm63xx/cpu.c +++ b/arch/mips/bcm63xx/cpu.c @@ -63,6 +63,43 @@ static const int bcm96338_irqs[] = { }; /* + * 6345 register sets and irqs + */ +static const unsigned long bcm96345_regs_base[] = { + [RSET_DSL_LMEM] = BCM_6345_DSL_LMEM_BASE, + [RSET_PERF] = BCM_6345_PERF_BASE, + [RSET_TIMER] = BCM_6345_TIMER_BASE, + [RSET_WDT] = BCM_6345_WDT_BASE, + [RSET_UART0] = BCM_6345_UART0_BASE, + [RSET_GPIO] = BCM_6345_GPIO_BASE, + [RSET_SPI] = BCM_6345_SPI_BASE, + [RSET_UDC0] = BCM_6345_UDC0_BASE, + [RSET_OHCI0] = BCM_6345_OHCI0_BASE, + [RSET_OHCI_PRIV] = BCM_6345_OHCI_PRIV_BASE, + [RSET_USBH_PRIV] = BCM_6345_USBH_PRIV_BASE, + [RSET_MPI] = BCM_6345_MPI_BASE, + [RSET_PCMCIA] = BCM_6345_PCMCIA_BASE, + [RSET_DSL] = BCM_6345_DSL_BASE, + [RSET_ENET0] = BCM_6345_ENET0_BASE, + [RSET_ENET1] = BCM_6345_ENET1_BASE, + [RSET_ENETDMA] = BCM_6345_ENETDMA_BASE, + [RSET_EHCI0] = BCM_6345_EHCI0_BASE, + [RSET_SDRAM] = BCM_6345_SDRAM_BASE, + [RSET_MEMC] = BCM_6345_MEMC_BASE, + [RSET_DDR] = BCM_6345_DDR_BASE, +}; + +static const int bcm96345_irqs[] = { + [IRQ_TIMER] = BCM_6345_TIMER_IRQ, + [IRQ_UART0] = BCM_6345_UART0_IRQ, + [IRQ_DSL] = BCM_6345_DSL_IRQ, + [IRQ_ENET0] = BCM_6345_ENET0_IRQ, + [IRQ_ENET_PHY] = BCM_6345_ENET_PHY_IRQ, + [IRQ_ENET0_RXDMA] = BCM_6345_ENET0_RXDMA_IRQ, + [IRQ_ENET0_TXDMA] = BCM_6345_ENET0_TXDMA_IRQ, +}; + +/* * 6348 register sets and irqs */ static const unsigned long bcm96348_regs_base[] = { @@ -177,6 +214,10 @@ static unsigned int detect_cpu_clock(void) /* BCM6338 has a fixed 240 Mhz frequency */ if (BCMCPU_IS_6338()) return 240000000; + + /* BCM6345 has a fixed 140Mhz frequency */ + if (BCMCPU_IS_6345()) + return 140000000; /* * frequency depends on PLL configuration: @@ -210,6 +251,9 @@ static unsigned int detect_memory_size(void) { unsigned int cols = 0, rows = 0, is_32bits = 0, banks = 0; u32 val; + + if (BCMCPU_IS_6345()) + return (8 * 1024 * 1024); if (BCMCPU_IS_6338() || BCMCPU_IS_6348()) { val = bcm_sdram_readl(SDRAM_CFG_REG); @@ -252,6 +296,11 @@ void __init bcm63xx_cpu_init(void) bcm63xx_regs_base = bcm96338_regs_base; bcm63xx_irqs = bcm96338_irqs; break; + case CPU_BCM6345: + expected_cpu_id = BCM6345_CPU_ID; + bcm63xx_regs_base = bcm96345_regs_base; + bcm63xx_irqs = bcm96345_irqs; + break; case CPU_BCM6348: expected_cpu_id = BCM6348_CPU_ID; bcm63xx_regs_base = bcm96348_regs_base; diff --git a/arch/mips/bcm63xx/prom.c b/arch/mips/bcm63xx/prom.c index 6a41acb..d36ee03 100644 --- a/arch/mips/bcm63xx/prom.c +++ b/arch/mips/bcm63xx/prom.c @@ -27,6 +27,8 @@ void __init prom_init(void) /* disable all hardware blocks clock for now */ if (BCMCPU_IS_6338()) mask = CKCTL_6338_ALL_SAFE_EN; + else if (BCMCPU_IS_6345()) + mask = CKCTL_6345_ALL_SAFE_EN; else if (BCMCPU_IS_6348()) mask = CKCTL_6348_ALL_SAFE_EN; else diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h index 3c107d0..b12c4ac 100644 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h @@ -10,6 +10,7 @@ * arm mach-types) */ #define BCM6338_CPU_ID 0x6338 +#define BCM6345_CPU_ID 0x6345 #define BCM6348_CPU_ID 0x6348 #define BCM6358_CPU_ID 0x6358 @@ -31,6 +32,19 @@ unsigned int bcm63xx_get_cpu_freq(void); # define BCMCPU_IS_6338() (0) #endif +#ifdef CONFIG_BCM63XX_CPU_6345 +# ifdef bcm63xx_get_cpu_id +# undef bcm63xx_get_cpu_id +# define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id() +# define BCMCPU_RUNTIME_DETECT +# else +# define bcm63xx_get_cpu_id() BCM6345_CPU_ID +# endif +# define BCMCPU_IS_6345() (bcm63xx_get_cpu_id() == BCM6345_CPU_ID) +#else +# define BCMCPU_IS_6345() (0) +#endif + #ifdef CONFIG_BCM63XX_CPU_6348 # ifdef bcm63xx_get_cpu_id # undef bcm63xx_get_cpu_id @@ -131,6 +145,36 @@ enum bcm63xx_regs_set { #define BCM_6338_DDR_BASE (0xdeadbeef) /* + * 6345 register sets base address + */ +#define BCM_6345_DSL_LMEM_BASE (0xfff00000) +#define BCM_6345_PERF_BASE (0xfffe0000) +#define BCM_6345_BB_BASE (0xfffe0100) +#define BCM_6345_TIMER_BASE (0xfffe0200) +#define BCM_6345_WDT_BASE (0xfffe021c) +#define BCM_6345_UART0_BASE (0xfffe0300) +#define BCM_6345_GPIO_BASE (0xfffe0400) +#define BCM_6345_SPI_BASE (0xdeadbeef) +#define BCM_6345_UDC0_BASE (0xdeadbeef) +#define BCM_6345_USBDMA_BASE (0xfffe2800) +#define BCM_6345_ENET0_BASE (0xfffe1800) +#define BCM_6345_ENETDMA_BASE (0xfffe2800) +#define BCM_6345_PCMCIA_BASE (0xfffe2028) +#define BCM_6345_MPI_BASE (0xdeadbeef) +#define BCM_6345_OHCI0_BASE (0xfffe2100) +#define BCM_6345_OHCI_PRIV_BASE (0xfffe2200) +#define BCM_6345_USBH_PRIV_BASE (0xdeadbeef) +#define BCM_6345_SDRAM_REGS_BASE (0xfffe2300) +#define BCM_6345_DSL_BASE (0xdeadbeef) +#define BCM_6345_SAR_BASE (0xdeadbeef) +#define BCM_6345_UBUS_BASE (0xdeadbeef) +#define BCM_6345_ENET1_BASE (0xdeadbeef) +#define BCM_6345_EHCI0_BASE (0xdeadbeef) +#define BCM_6345_SDRAM_BASE (0xfffe2300) +#define BCM_6345_MEMC_BASE (0xdeadbeef) +#define BCM_6345_DDR_BASE (0xdeadbeef) + +/* * 6348 register sets base address */ #define BCM_6348_DSL_LMEM_BASE (0xfff00000) @@ -236,6 +280,52 @@ static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set) return BCM_6338_DDR_BASE; } #endif +#ifdef CONFIG_BCM63XX_CPU_6345 + switch (set) { + case RSET_DSL_LMEM: + return BCM_6345_DSL_LMEM_BASE; + case RSET_PERF: + return BCM_6345_PERF_BASE; + case RSET_TIMER: + return BCM_6345_TIMER_BASE; + case RSET_WDT: + return BCM_6345_WDT_BASE; + case RSET_UART0: + return BCM_6345_UART0_BASE; + case RSET_GPIO: + return BCM_6345_GPIO_BASE; + case RSET_SPI: + return BCM_6345_SPI_BASE; + case RSET_UDC0: + return BCM_6345_UDC0_BASE; + case RSET_OHCI0: + return BCM_6345_OHCI0_BASE; + case RSET_OHCI_PRIV: + return BCM_6345_OHCI_PRIV_BASE; + case RSET_USBH_PRIV: + return BCM_6345_USBH_PRIV_BASE; + case RSET_MPI: + return BCM_6345_MPI_BASE; + case RSET_PCMCIA: + return BCM_6345_PCMCIA_BASE; + case RSET_DSL: + return BCM_6345_DSL_BASE; + case RSET_ENET0: + return BCM_6345_ENET0_BASE; + case RSET_ENET1: + return BCM_6345_ENET1_BASE; + case RSET_ENETDMA: + return BCM_6345_ENETDMA_BASE; + case RSET_EHCI0: + return BCM_6345_EHCI0_BASE; + case RSET_SDRAM: + return BCM_6345_SDRAM_BASE; + case RSET_MEMC: + return BCM_6345_MEMC_BASE; + case RSET_DDR: + return BCM_6345_DDR_BASE; + } +#endif #ifdef CONFIG_BCM63XX_CPU_6348 switch (set) { case RSET_DSL_LMEM: @@ -376,6 +466,29 @@ enum bcm63xx_irq { #define BCM_6338_SDIO_IRQ (IRQ_INTERNAL_BASE + 17) /* + * 6345 irqs + */ +#define BCM_6345_TIMER_IRQ (IRQ_INTERNAL_BASE + 0) +#define BCM_6345_UART0_IRQ (IRQ_INTERNAL_BASE + 2) +#define BCM_6345_DSL_IRQ (IRQ_INTERNAL_BASE + 3) +#define BCM_6345_ATM_IRQ (IRQ_INTERNAL_BASE + 4) +#define BCM_6345_USB_IRQ (IRQ_INTERNAL_BASE + 5) +#define BCM_6345_ENET0_IRQ (IRQ_INTERNAL_BASE + 8) +#define BCM_6345_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 12) +#define BCM_6345_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 13 + 1) +#define BCM_6345_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 13 + 2) +#define BCM_6345_EBI_RX_IRQ (IRQ_INTERNAL_BASE + 13 + 5) +#define BCM_6345_EBI_TX_IRQ (IRQ_INTERNAL_BASE + 13 + 6) +#define BCM_6345_RESERVED_RX_IRQ (IRQ_INTERNAL_BASE + 13 + 9) +#define BCM_6345_RESERVED_TX_IRQ (IRQ_INTERNAL_BASE + 13 + 10) +#define BCM_6345_USB_BULK_RX_DMA_IRQ (IRQ_INTERNAL_BASE + 13 + 13) +#define BCM_6345_USB_BULK_TX_DMA_IRQ (IRQ_INTERNAL_BASE + 13 + 14) +#define BCM_6345_USB_CNTL_RX_DMA_IRQ (IRQ_INTERNAL_BASE + 13 + 15) +#define BCM_6345_USB_CNTL_TX_DMA_IRQ (IRQ_INTERNAL_BASE + 13 + 16) +#define BCM_6345_USB_ISO_RX_DMA_IRQ (IRQ_INTERNAL_BASE + 13 + 17) +#define BCM_6345_USB_ISO_TX_DMA_IRQ (IRQ_INTERNAL_BASE + 13 + 18) + +/* * 6348 irqs */ #define BCM_6348_TIMER_IRQ (IRQ_INTERNAL_BASE + 0) diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h index 3249e8c..48dcb43 100644 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h @@ -29,6 +29,18 @@ CKCTL_6338_SAR_EN | \ CKCTL_6338_SPI_EN) +#define CKCTL_6345_CPU_EN (1 << 0) +#define CKCTL_6345_BUS_EN (1 << 1) +#define CKCTL_6345_EBI_EN (1 << 2) +#define CKCTL_6345_UART_EN (1 << 3) +#define CKCTL_6345_ADSLPHY_EN (1 << 4) +#define CKCTL_6345_ENET_EN (1 << 7) +#define CKCTL_6345_USBH_EN (1 << 8) + +#define CKCTL_6345_ALL_SAFE_EN (CKCTL_6345_ENET_EN | \ + CKCTL_6345_USBH_EN | \ + CKCTL_6345_ADSLPHY_EN) + #define CKCTL_6348_ADSLPHY_EN (1 << 0) #define CKCTL_6348_MPI_EN (1 << 1) #define CKCTL_6348_SDRAM_EN (1 << 2) diff --git a/arch/mips/include/asm/mach-bcm63xx/cpu-feature-overrides.h b/arch/mips/include/asm/mach-bcm63xx/cpu-feature-overrides.h index 80c3aa2..71742ba 100644 --- a/arch/mips/include/asm/mach-bcm63xx/cpu-feature-overrides.h +++ b/arch/mips/include/asm/mach-bcm63xx/cpu-feature-overrides.h @@ -24,7 +24,7 @@ #define cpu_has_smartmips 0 #define cpu_has_vtag_icache 0 -#if !defined(BCMCPU_RUNTIME_DETECT) && (defined(CONFIG_BCMCPU_IS_6348) || defined(CONFIG_CPU_IS_6338)) +#if !defined(BCMCPU_RUNTIME_DETECT) && (defined(CONFIG_BCMCPU_IS_6348) || defined(CONFIG_CPU_IS_6338) || defined(CONFIG_CPU_IS_BCM6345)) #define cpu_has_dc_aliases 0 #endif diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index ae53992..251a268 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -160,7 +160,6 @@ void __init check_wait(void) case CPU_PR4450: case CPU_BCM3302: case CPU_BCM6338: - case CPU_BCM6345: case CPU_BCM6348: case CPU_BCM6358: case CPU_CAVIUM_OCTEON: From mbizon@freebox.fr Sat Aug 8 01:31:34 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 08 Aug 2009 01:31:40 +0200 (CEST) Received: from smtp6-g21.free.fr ([212.27.42.6]:57122 "EHLO smtp6-g21.free.fr" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1493163AbZHGXbd (ORCPT ); Sat, 8 Aug 2009 01:31:33 +0200 Received: from smtp6-g21.free.fr (localhost [127.0.0.1]) by smtp6-g21.free.fr (Postfix) with ESMTP id A0CFFE08089; Sat, 8 Aug 2009 01:31:25 +0200 (CEST) Received: from [127.0.0.1] (sakura.staff.proxad.net [213.228.1.107]) by smtp6-g21.free.fr (Postfix) with ESMTP id 619B9E08017; Sat, 8 Aug 2009 01:31:22 +0200 (CEST) Subject: Re: [PATCH 0/8] New BCM63xx SoC support and devices registration From: Maxime Bizon Reply-To: mbizon@freebox.fr To: Florian Fainelli Cc: Ralf Baechle , linux-mips@linux-mips.org In-Reply-To: <200908072346.15278.florian@openwrt.org> References: <200908072346.15278.florian@openwrt.org> Content-Type: text/plain Date: Sat, 08 Aug 2009 01:31:21 +0200 Message-Id: <1249687881.29189.68.camel@kero> Mime-Version: 1.0 X-Mailer: Evolution 2.26.1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23861 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mbizon@freebox.fr Precedence: bulk X-list: linux-mips On Fri, 2009-08-07 at 23:46 +0200, Florian Fainelli wrote: Hi Florian, > The following 8 patches apply on top of the patch entitled "bcm63xx: > fix build failures when CONFIG_PCI is disabled" Nice work, ack for the whole serie. I don't have any 6338 nor 6345 hardware, so I'll trust you for doing some testing if that's needed in the future. Please try to compile with and without cpu runtime detection because it's quite easy to forget to fill the registers set for each case. > Ralf, Maxime sent a patch series on June 3rd which would be great to > merge so that I can rebase my serie on that one Yup, that would be great :) -- Maxime From ralf@linux-mips.org Sat Aug 8 13:09:53 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 08 Aug 2009 13:10:00 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:35056 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492914AbZHHLJx (ORCPT ); Sat, 8 Aug 2009 13:09:53 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id n78BAUKZ021563; Sat, 8 Aug 2009 12:10:30 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id n78BATIq021560; Sat, 8 Aug 2009 12:10:29 +0100 Date: Sat, 8 Aug 2009 12:10:29 +0100 From: Ralf Baechle To: Florian Fainelli Cc: linux-mips@linux-mips.org, Maxime Bizon Subject: Re: [PATCH] bcm63xx: fix build failures when CONFIG_PCI is disabled Message-ID: <20090808111029.GA14596@linux-mips.org> References: <200908042214.39866.florian@openwrt.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <200908042214.39866.florian@openwrt.org> User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23862 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Tue, Aug 04, 2009 at 10:14:39PM +0200, Florian Fainelli wrote: > This patch fixes multiple build failures when CONFIG_PCI > is disabled. Since bcm63xx_sprom depends on CONFIG_SSB_PCIHOST > to be set, which depends on CONFIG_PCI, bcm63xx_sprom > would be unused thus causing this direct warning treated > as an error: > > cc1: warnings being treated as errors > arch/mips/bcm63xx/boards/board_bcm963xx.c:466: warning: 'bcm63xx_sprom' defined but not used > > Then bcm63xx_pci_enabled would not be resolved since it > is declared in arch/mips/pci/pci-bcm63xx.c which is not > compiled due to CONFIG_PCI being disabled. Finally, > ssb_set_arch_fallback would not be resolved too, since > CONFIG_SSB_PCIHOST is disabled. Thanks. Folded into "MIPS: BCM63XX: Add board support code." Ralf From ralf@linux-mips.org Sat Aug 8 13:59:31 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 08 Aug 2009 13:59:38 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:35870 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492961AbZHHL7b (ORCPT ); Sat, 8 Aug 2009 13:59:31 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id n78C08LQ029878; Sat, 8 Aug 2009 13:00:08 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id n78C08cI029877; Sat, 8 Aug 2009 13:00:08 +0100 Date: Sat, 8 Aug 2009 13:00:08 +0100 From: Ralf Baechle To: Florian Fainelli Cc: Maxime Bizon , linux-mips@linux-mips.org Subject: Re: [PATCH 1/8] bcm63xx: add infrastructure for MPI-connected VoIP DSP Message-ID: <20090808120008.GB14596@linux-mips.org> References: <200908072346.21785.florian@openwrt.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <200908072346.21785.florian@openwrt.org> User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23863 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Fri, Aug 07, 2009 at 11:46:21PM +0200, Florian Fainelli wrote: > This patch adds the required infrastructure to register > a MPI and GPIO connected VoIP DSP. We will register > devices in a subsequent patch. > > Signed-off-by: Florian Fainelli > --- > diff --git a/arch/mips/bcm63xx/Makefile b/arch/mips/bcm63xx/Makefile > index 92d07f0..70ba038 100644 > --- a/arch/mips/bcm63xx/Makefile > +++ b/arch/mips/bcm63xx/Makefile > @@ -4,6 +4,7 @@ obj-y += dev-pcmcia.o > obj-y += dev-usb-ohci.o > obj-y += dev-usb-ehci.o > obj-y += dev-enet.o > +obj-y += dev-dsp.o > obj-$(CONFIG_EARLY_PRINTK) += early_printk.o > > obj-y += boards/ > diff --git a/arch/mips/bcm63xx/dev-dsp.c b/arch/mips/bcm63xx/dev-dsp.c > new file mode 100644 > index 0000000..08a2f75 > --- /dev/null > +++ b/arch/mips/bcm63xx/dev-dsp.c > @@ -0,0 +1,56 @@ > +/* > + * Broadcom BCM63xx VoIP DSP registration > + * > + * This file is subject to the terms and conditions of the GNU General Public > + * License. See the file "COPYING" in the main directory of this archive > + * for more details. > + * > + * Copyright (C) 2009 Florian Fainelli ^^^ You *wham* shall *wham* not *wham* sumbit *wham* trailing *wham* whitespace :-) I cleaned that but it's really YOUR job to do that. Ralf From ralf@linux-mips.org Sat Aug 8 14:00:46 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 08 Aug 2009 14:00:53 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:35880 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492961AbZHHMAq (ORCPT ); Sat, 8 Aug 2009 14:00:46 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id n78C1NF3030279; Sat, 8 Aug 2009 13:01:23 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id n78C1NQd030278; Sat, 8 Aug 2009 13:01:23 +0100 Date: Sat, 8 Aug 2009 13:01:23 +0100 From: Ralf Baechle To: Florian Fainelli Cc: Maxime Bizon , linux-mips@linux-mips.org Subject: Re: [PATCH 2/8] bcm63xx: register VoIP DSP for bcm96348gw-10 and bcm96348gw designs Message-ID: <20090808120123.GC14596@linux-mips.org> References: <200908072346.34473.florian@openwrt.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <200908072346.34473.florian@openwrt.org> User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23864 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Fri, Aug 07, 2009 at 11:46:34PM +0200, Florian Fainelli wrote: Folded into "MIPS: BCM63XX: Add board support code." Ralf From ralf@linux-mips.org Sat Aug 8 14:09:44 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 08 Aug 2009 14:09:52 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:44576 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492941AbZHHMJo (ORCPT ); Sat, 8 Aug 2009 14:09:44 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id n78CAMaw031614; Sat, 8 Aug 2009 13:10:22 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id n78CAM6J031611; Sat, 8 Aug 2009 13:10:22 +0100 Date: Sat, 8 Aug 2009 13:10:22 +0100 From: Ralf Baechle To: Florian Fainelli Cc: Maxime Bizon , linux-mips@linux-mips.org Subject: Re: [PATCH 3/8] bcm63xx: register GPIO-connected LEDs for known references designs Message-ID: <20090808121022.GA30320@linux-mips.org> References: <200908072346.41096.florian@openwrt.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <200908072346.41096.florian@openwrt.org> User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23865 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Fri, Aug 07, 2009 at 11:46:40PM +0200, Florian Fainelli wrote: Folded into "MIPS: BCM63XX: Add board support code." Thanks! Ralf From ralf@linux-mips.org Sat Aug 8 20:47:39 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 08 Aug 2009 20:47:47 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:35877 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1493299AbZHHSrj (ORCPT ); Sat, 8 Aug 2009 20:47:39 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id n78ImHH9023030; Sat, 8 Aug 2009 19:48:17 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id n78ImG48023027; Sat, 8 Aug 2009 19:48:16 +0100 Date: Sat, 8 Aug 2009 19:48:16 +0100 From: Ralf Baechle To: Florian Fainelli Cc: Maxime Bizon , linux-mips@linux-mips.org Subject: Re: [PATCH 4/8] bcm63xx: add support for the BCM6338 SoC Message-ID: <20090808184816.GA22761@linux-mips.org> References: <200908072346.45245.florian@openwrt.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <200908072346.45245.florian@openwrt.org> User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23866 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Fri, Aug 07, 2009 at 11:46:44PM +0200, Florian Fainelli wrote: Thansk, folded into "MIPS: BCM63XX: Add integrated ethernet mac support." Ralf From ralf@linux-mips.org Sat Aug 8 20:52:58 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 08 Aug 2009 20:53:05 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:57400 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1493299AbZHHSw6 (ORCPT ); Sat, 8 Aug 2009 20:52:58 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id n78Iram0024431; Sat, 8 Aug 2009 19:53:36 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id n78IraKW024430; Sat, 8 Aug 2009 19:53:36 +0100 Date: Sat, 8 Aug 2009 19:53:36 +0100 From: Ralf Baechle To: Florian Fainelli Cc: Maxime Bizon , linux-mips@linux-mips.org Subject: Re: [PATCH 5/8] bcm63xx: add bcm96338w and bcm96338gw board support Message-ID: <20090808185336.GB22761@linux-mips.org> References: <200908072346.52578.florian@openwrt.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <200908072346.52578.florian@openwrt.org> User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23867 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Fri, Aug 07, 2009 at 11:46:52PM +0200, Florian Fainelli wrote: Folded into "MIPS: BCM63XX: Add board support code." Thanks, Ralf PS: This patch contais some more George Michael ;-) From wuzhangjin@gmail.com Sat Aug 8 20:55:23 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 08 Aug 2009 20:55:29 +0200 (CEST) Received: from wa-out-1112.google.com ([209.85.146.178]:58941 "EHLO wa-out-1112.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1493306AbZHHSzX (ORCPT ); Sat, 8 Aug 2009 20:55:23 +0200 Received: by wa-out-1112.google.com with SMTP id n4so432600wag.0 for ; Sat, 08 Aug 2009 11:55:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer; bh=qoOpqur32pDk/kuiRNI5x5Ij6JSvj9gxgG3aH86FqLk=; b=NtLH77jtMt8IVvawL66/4d9nwKCWtn9zJjMHVbgW3Pu4C7uczrteBaItfyAg/liD0j V9iXstSSc8HobL7/odqz+29I5a5AxF+MZ6w7bsAWcSIHtawBhxZIeXk67Z35Jttj0NkY WrWxe+i1JGTr69stFdKLbRl3vtbObAIUfAVPU= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer; b=wqDR0jU1eexcCP7AnW2DQ8et7XA1dJLgJplkESIQZf1YtWKsneGtmbJDqWqGnUMbo0 Rhsq82/uVIjHauoKlH43QJbyhqu3HBjMlZh2hwGbMCWSmZe5S2OHLmYtiwFBl+O9wss/ j5KiAI7WoX8xyVOMMhF4TghexEMKvOmovb/r4= Received: by 10.114.199.1 with SMTP id w1mr451571waf.179.1249757718630; Sat, 08 Aug 2009 11:55:18 -0700 (PDT) Received: from localhost.localdomain ([222.92.8.142]) by mx.google.com with ESMTPS id m17sm3994244waf.38.2009.08.08.11.55.15 (version=TLSv1/SSLv3 cipher=RC4-MD5); Sat, 08 Aug 2009 11:55:17 -0700 (PDT) From: Wu Zhangjin To: linux-mips@linux-mips.org Cc: Ralf Baechle , Wu Zhangjin Subject: [PATCH] MIPS: add support for gzip/bzip2/lzma compressed kernel images Date: Sun, 9 Aug 2009 02:55:07 +0800 Message-Id: <1249757707-8876-1-git-send-email-wuzhangjin@gmail.com> X-Mailer: git-send-email 1.6.2.1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23868 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips This patch will help to generate smaller kernel images for linux-MIPS, $ wc -c vmlinux 7465416 vmlinux $ wc -c vmlinuz 2059691 vmlinuz Have tested the 32bit kernel on Qemu/Malta and 64bit kernel on FuLoong Mini PC. both of them works well. Signed-off-by: Wu Zhangjin --- arch/mips/Kconfig | 3 + arch/mips/Makefile | 6 +- arch/mips/boot/compressed/Makefile | 52 +++++++++++ arch/mips/boot/compressed/dbg.c | 68 ++++++++++++++ arch/mips/boot/compressed/dbg.h | 5 + arch/mips/boot/compressed/decompress.c | 152 ++++++++++++++++++++++++++++++++ arch/mips/boot/compressed/dummy.c | 4 + arch/mips/boot/compressed/head.S | 85 ++++++++++++++++++ arch/mips/boot/compressed/ld.script | 152 ++++++++++++++++++++++++++++++++ 9 files changed, 526 insertions(+), 1 deletions(-) create mode 100644 arch/mips/boot/compressed/Makefile create mode 100644 arch/mips/boot/compressed/dbg.c create mode 100644 arch/mips/boot/compressed/dbg.h create mode 100644 arch/mips/boot/compressed/decompress.c create mode 100644 arch/mips/boot/compressed/dummy.c create mode 100644 arch/mips/boot/compressed/head.S create mode 100644 arch/mips/boot/compressed/ld.script diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 3ca0fe1..fae7029 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -4,6 +4,9 @@ config MIPS select HAVE_IDE select HAVE_OPROFILE select HAVE_ARCH_KGDB + select HAVE_KERNEL_GZIP + select HAVE_KERNEL_BZIP2 + select HAVE_KERNEL_LZMA # Horrible source of confusion. Die, die, die ... select EMBEDDED select RTC_LIB diff --git a/arch/mips/Makefile b/arch/mips/Makefile index 861da51..57f0146 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -709,7 +709,10 @@ vmlinux.64: vmlinux makeboot =$(Q)$(MAKE) $(build)=arch/mips/boot VMLINUX=$(vmlinux-32) $(1) -all: $(all-y) +all: $(all-y) vmlinuz + +vmlinuz: vmlinux + $(Q)$(MAKE) $(build)=arch/mips/boot/compressed $@ vmlinux.bin: $(vmlinux-32) +@$(call makeboot,$@) @@ -740,6 +743,7 @@ install: archclean: @$(MAKE) $(clean)=arch/mips/boot + @$(MAKE) $(clean)=arch/mips/boot/compressed @$(MAKE) $(clean)=arch/mips/lasat define archhelp diff --git a/arch/mips/boot/compressed/Makefile b/arch/mips/boot/compressed/Makefile new file mode 100644 index 0000000..012bdd8 --- /dev/null +++ b/arch/mips/boot/compressed/Makefile @@ -0,0 +1,52 @@ +# +# This file is subject to the terms and conditions of the GNU General Public +# License. +# +# Adapted for MIPS Pete Popov, Dan Malek +# +# Copyright (C) 1994 by Linus Torvalds +# Adapted for PowerPC by Gary Thomas +# modified by Cort (cort@cs.nmt.edu) +# +# Copyright (C) 2009 Lemote Inc. & Insititute of Computing Technology +# Author: Wu Zhangjin +# + +KBUILD_CFLAGS := $(LINUXINCLUDE) $(KBUILD_CFLAGS) -D__KERNEL__ #-DDEBUG +KBUILD_AFLAGS := $(LINUXINCLUDE) $(KBUILD_AFLAGS) -D__ASSEMBLY__ \ + -DKERNEL_ENTRY=0x$(shell $(NM) $(objtree)/$(KBUILD_IMAGE) | grep " kernel_entry" | cut -f1 -d \ ) + +OBJECTS := $(obj)/head.o $(obj)/decompress.o $(obj)/dbg.o + +OBJCOPYFLAGS_vmlinux.bin := $(OBJCOPYFLAGS) -O binary -R .comment -S +$(obj)/vmlinux.bin: $(KBUILD_IMAGE) + $(call if_changed,objcopy) + +suffix_$(CONFIG_KERNEL_GZIP) = gz +suffix_$(CONFIG_KERNEL_BZIP2) = bz2 +suffix_$(CONFIG_KERNEL_LZMA) = lzma +tool_$(CONFIG_KERNEL_GZIP) = gzip +tool_$(CONFIG_KERNEL_BZIP2) = bzip2 +tool_$(CONFIG_KERNEL_LZMA) = lzma +$(obj)/vmlinux.$(suffix_y): $(obj)/vmlinux.bin + $(call if_changed,$(tool_y)) + +$(obj)/piggy.o: $(obj)/vmlinux.$(suffix_y) $(obj)/dummy.o + $(Q)$(OBJCOPY) $(OBJCOPYFLAGS) \ + --add-section=.image=$< \ + --set-section-flags=.image=contents,alloc,load,readonly,data \ + $(obj)/dummy.o $@ + +# The start address of the compressed kernel, 81000000 > KERNEL_START + KERNEL_SIZE +LDFLAGS_vmlinuz := $(LDFLAGS) -Ttext 0x$(if $(CONFIG_64BIT),ffffffff,)81000000 -T +$(obj)/vmlinuz: $(src)/ld.script $(OBJECTS) $(obj)/piggy.o + $(call if_changed,ld) + +OBJCOPYFLAGS_vmlinuz := $(OBJCOPYFLAGS) -R .comment -R .stab -R .stabstr -R .initrd -R .sysmap +vmlinuz: $(obj)/vmlinuz + $(call if_changed,objcopy) + +clean: +clean-files += *.o \ + vmlinu* \ + $(objtree)/vmlinuz diff --git a/arch/mips/boot/compressed/dbg.c b/arch/mips/boot/compressed/dbg.c new file mode 100644 index 0000000..5c3f130 --- /dev/null +++ b/arch/mips/boot/compressed/dbg.c @@ -0,0 +1,68 @@ +/* + * MIPS-specific debug support for pre-boot environment + */ + +#ifdef DEBUG + +#include +#include +#include + +#include "dbg.h" + +#include + +#define PORT(offset) (CKSEG1ADDR(UART_BASE) + (offset)) + +static inline unsigned int serial_in(int offset) +{ + return *((char *)PORT(offset)); +} + +static inline void serial_out(int offset, int value) +{ + *((char *)PORT(offset)) = value; +} + +int putc(char c) +{ + while ((serial_in(UART_LSR) & UART_LSR_THRE) == 0) + ; + + serial_out(UART_TX, c); + + return 1; +} + +void puts(const char *s) +{ + char c; + while ((c = *s++) != '\0') { + putc(c); + if (c == '\n') + putc('\r'); + } +} + +void puthex(unsigned long val) +{ + + unsigned char buf[10]; + int i; + for (i = 7; i >= 0; i--) { + buf[i] = "0123456789ABCDEF"[val & 0x0F]; + val >>= 4; + } + buf[8] = '\0'; + puts(buf); +} + + +#else +void puts(const char *s) +{ +} +void puthex(unsigned long val) +{ +} +#endif diff --git a/arch/mips/boot/compressed/dbg.h b/arch/mips/boot/compressed/dbg.h new file mode 100644 index 0000000..b130ad0 --- /dev/null +++ b/arch/mips/boot/compressed/dbg.h @@ -0,0 +1,5 @@ +/* + * board-specific serial port + */ + +#define UART_BASE 0x1fd003f8 diff --git a/arch/mips/boot/compressed/decompress.c b/arch/mips/boot/compressed/decompress.c new file mode 100644 index 0000000..2ff8a18 --- /dev/null +++ b/arch/mips/boot/compressed/decompress.c @@ -0,0 +1,152 @@ +/* + * Misc. bootloader code for many machines. + * + * Copyright 2001 MontaVista Software Inc. + * Author: Matt Porter Derived from + * arch/ppc/boot/prep/misc.c + * + * Copyright (C) 2009 Lemote, Inc. & Institute of Computing Technology + * Author: Wu Zhangjin + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include +#include +#include + +/* These two variables specify the free mem region + * that can be used for temporary malloc area + * + * Here is toally 15M + */ +#define FREE_MEM_START CKSEG0ADDR(0x83000000) +#define FREE_MEM_END CKSEG0ADDR(0x83f00000) + +unsigned long free_mem_ptr; +unsigned long free_mem_end_ptr; +char *zimage_start; + +/* The linker tells us where the image is. */ +extern unsigned char __image_begin, __image_end; +extern unsigned char __ramdisk_begin, __ramdisk_end; +unsigned long initrd_size; + +/* debug interfaces */ +extern void puts(const char *s); +extern void puthex(unsigned long val); + +void error(char *x) +{ + puts("\n\n"); + puts(x); + puts("\n\n -- System halted"); + + while (1) + ; /* Halt */ +} + +/* activate the code for pre-boot environment */ +#define STATIC static + +#ifdef CONFIG_KERNEL_GZIP +void *memcpy(void *dest, const void *src, size_t n) +{ + int i; + const char *s = src; + char *d = dest; + + for (i = 0; i < n; i++) + d[i] = s[i]; + return dest; +} +#include "../../../../lib/decompress_inflate.c" +#endif + +#ifdef CONFIG_KERNEL_BZIP2 +void *memset(void *s, int c, size_t n) +{ + int i; + char *ss = s; + + for (i = 0; i < n; i++) + ss[i] = c; + return s; +} +#include "../../../../lib/decompress_bunzip2.c" +#endif + +#ifdef CONFIG_KERNEL_LZMA +#include "../../../../lib/decompress_unlzma.c" +#endif + +void decompress_kernel(unsigned long load_addr, int num_words, + unsigned long cksum, unsigned long *sp) +{ + extern unsigned long start; + int zimage_size; + + initrd_size = (unsigned long)(&__ramdisk_end) - + (unsigned long)(&__ramdisk_begin); + + /* + * Reveal where we were loaded at and where we + * were relocated to. + */ + puts("loaded at: "); + puthex(load_addr); + puts(" "); + puthex((unsigned long)(load_addr + (4 * num_words))); + puts("\n"); + if ((unsigned long)load_addr != (unsigned long)&start) { + puts("relocated to: "); + puthex((unsigned long)&start); + puts(" "); + puthex((unsigned long)((unsigned long)&start + + (4 * num_words))); + puts("\n"); + } + + /* + * We link ourself to an arbitrary low address. When we run, we + * relocate outself to that address. __image_beign points to + * the part of the image where the zImage is. -- Tom + */ + zimage_start = (char *)(unsigned long)(&__image_begin); + zimage_size = (unsigned long)(&__image_end) - + (unsigned long)(&__image_begin); + + /* + * The zImage and initrd will be between start and _end, so they've + * already been moved once. We're good to go now. -- Tom + */ + puts("zimage at: "); + puthex((unsigned long)zimage_start); + puts(" "); + puthex((unsigned long)(zimage_size + zimage_start)); + puts("\n"); + + if (initrd_size) { + puts("initrd at: "); + puthex((unsigned long)(&__ramdisk_begin)); + puts(" "); + puthex((unsigned long)(&__ramdisk_end)); + puts("\n"); + } + + /* assume the chunk below 8M is free */ + free_mem_ptr = FREE_MEM_START; + free_mem_end_ptr = FREE_MEM_END; + + /* Display standard Linux/MIPS boot prompt for kernel args */ + puts("Uncompressing Linux at load address "); + puthex(VMLINUX_LOAD_ADDRESS); + puts("\n"); + /* I don't like this hard coded gunzip size (fixme) */ + decompress(zimage_start, zimage_size, 0, 0, + (void *)VMLINUX_LOAD_ADDRESS, 0, error); + puts("Now, booting the kernel...\n"); +} diff --git a/arch/mips/boot/compressed/dummy.c b/arch/mips/boot/compressed/dummy.c new file mode 100644 index 0000000..31dbf45 --- /dev/null +++ b/arch/mips/boot/compressed/dummy.c @@ -0,0 +1,4 @@ +int main(void) +{ + return 0; +} diff --git a/arch/mips/boot/compressed/head.S b/arch/mips/boot/compressed/head.S new file mode 100644 index 0000000..6ac4492 --- /dev/null +++ b/arch/mips/boot/compressed/head.S @@ -0,0 +1,85 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1994, 1995 Waldorf Electronics + * Written by Ralf Baechle and Andreas Busse + * Copyright (C) 1995 - 1999 Ralf Baechle + * Copyright (C) 1996 Paul M. Antoine + * Modified for DECStation and hence R3000 support by Paul M. Antoine + * Further modifications by David S. Miller and Harald Koerfgen + * Copyright (C) 1999 Silicon Graphics, Inc. + */ +#include +#include + +#include +#include +#include +#include +#include +#include + + .set noreorder + .cprestore + LEAF(start) +start: + bal locate + nop +locate: + subu s8, ra, 8 /* Where we were loaded */ + PTR_LA sp, (.stack + 8192) + + move s0, a0 /* Save boot rom start args */ + move s1, a1 + move s2, a2 + move s3, a3 + + PTR_LA a0, start /* Where we were linked to run */ + + move a1, s8 + PTR_LA a2, _edata + subu t1, a2, a0 + srl t1, t1, 2 + + /* copy text section */ + li t0, 0 +1: lw v0, 0(a1) + nop + sw v0, 0(a0) + xor t0, t0, v0 + addu a0, 4 + bne a2, a0, 1b + addu a1, 4 + + /* Clear BSS */ + PTR_LA a0, _edata + PTR_LA a2, _end +2: sw zero, 0(a0) + bne a2, a0, 2b + addu a0, 4 + + move a0, s8 /* load address */ + move a1, t1 /* length in words */ + move a2, t0 /* checksum */ + move a3, sp + + PTR_LA ra, 1f + PTR_LA k0, decompress_kernel + jr k0 + nop +1: + + move a0, s0 + move a1, s1 + move a2, s2 + move a3, s3 + li k0, KERNEL_ENTRY + jr k0 + nop +3: + b 3b + END(start) + + .comm .stack,4096*2,4 diff --git a/arch/mips/boot/compressed/ld.script b/arch/mips/boot/compressed/ld.script new file mode 100644 index 0000000..29eaf41 --- /dev/null +++ b/arch/mips/boot/compressed/ld.script @@ -0,0 +1,152 @@ +OUTPUT_ARCH(mips) +ENTRY(start) +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + /* . = 0x81000000; */ /* 32bit */ + /* . = 0xffffffff81000000; */ /* 64bit */ + .init : { *(.init) } =0 + .text : + { + _ftext = . ; + *(.text) + *(.rodata) + *(.rodata1) + /* .gnu.warning sections are handled specially by elf32.em. */ + *(.gnu.warning) + } =0 + .kstrtab : { *(.kstrtab) } + + . = ALIGN(16); /* Exception table */ + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + __start___dbe_table = .; /* Exception table for data bus errors */ + __dbe_table : { *(__dbe_table) } + __stop___dbe_table = .; + + __start___ksymtab = .; /* Kernel symbol table */ + __ksymtab : { *(__ksymtab) } + __stop___ksymtab = .; + + _etext = .; + + . = ALIGN(8192); + .data.init_task : { *(.data.init_task) } + + /* Startup code */ + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(16); + __setup_start = .; + .setup.init : { *(.setup.init) } + __setup_end = .; + __initcall_start = .; + .initcall.init : { *(.initcall.init) } + __initcall_end = .; + . = ALIGN(4096); /* Align double page for init_task_union */ + __init_end = .; + + . = ALIGN(4096); + .data.page_aligned : { *(.data.idt) } + + . = ALIGN(32); + .data.cacheline_aligned : { *(.data.cacheline_aligned) } + + .fini : { *(.fini) } =0 + .reginfo : { *(.reginfo) } + /* Adjust the address for the data segment. We want to adjust up to + the same address within the page on the next page up. It would + be more correct to do this: + . = .; + The current expression does not correctly handle the case of a + text segment ending precisely at the end of a page; it causes the + data segment to skip a page. The above expression does not have + this problem, but it will currently (2/95) cause BFD to allocate + a single segment, combining both text and data, for this case. + This will prevent the text segment from being shared among + multiple executions of the program; I think that is more + important than losing a page of the virtual address space (note + that no actual memory is lost; the page which is skipped can not + be referenced). */ + . = .; + .data : + { + _fdata = . ; + *(.data) + + /* Put the compressed image here, so bss is on the end. */ + __image_begin = .; + *(.image) + __image_end = .; + /* Align the initial ramdisk image (INITRD) on page boundaries. */ + . = ALIGN(4096); + __ramdisk_begin = .; + *(.initrd) + __ramdisk_end = .; + . = ALIGN(4096); + + CONSTRUCTORS + } + .data1 : { *(.data1) } + _gp = . + 0x8000; + .lit8 : { *(.lit8) } + .lit4 : { *(.lit4) } + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + .got : { *(.got.plt) *(.got) } + .dynamic : { *(.dynamic) } + /* We want the small data sections together, so single-instruction offsets + can access them all, and initialized data all before uninitialized, so + we can shorten the on-disk segment size. */ + .sdata : { *(.sdata) } + . = ALIGN(4); + _edata = .; + PROVIDE (edata = .); + + __bss_start = .; + _fbss = .; + .sbss : { *(.sbss) *(.scommon) } + .bss : + { + *(.dynbss) + *(.bss) + *(COMMON) + . = ALIGN(4); + _end = . ; + PROVIDE (end = .); + } + + /* Sections to be discarded */ + /DISCARD/ : + { + *(.text.exit) + *(.data.exit) + *(.exitcall.exit) + } + + /* This is the MIPS specific mdebug section. */ + .mdebug : { *(.mdebug) } + /* These are needed for ELF backends which have not yet been + converted to the new style linker. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + /* DWARF debug sections. + Symbols in the .debug DWARF section are relative to the beginning of the + section so we begin .debug at 0. It's not clear yet what needs to happen + for the others. */ + .debug 0 : { *(.debug) } + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_sfnames 0 : { *(.debug_sfnames) } + .line 0 : { *(.line) } + /* These must appear regardless of . */ + .gptab.sdata : { *(.gptab.data) *(.gptab.sdata) } + .gptab.sbss : { *(.gptab.bss) *(.gptab.sbss) } + .comment : { *(.comment) } + .note : { *(.note) } +} -- 1.6.2.1 From ralf@linux-mips.org Sat Aug 8 21:36:29 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 08 Aug 2009 21:36:36 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:58237 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1493186AbZHHTg2 (ORCPT ); Sat, 8 Aug 2009 21:36:28 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id n78Jb6tb000674; Sat, 8 Aug 2009 20:37:06 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id n78Jb6sJ000670; Sat, 8 Aug 2009 20:37:06 +0100 Date: Sat, 8 Aug 2009 20:37:06 +0100 From: Ralf Baechle To: Florian Fainelli Cc: Maxime Bizon , linux-mips@linux-mips.org Subject: Re: [PATCH 7/8] bcm63xx: add basic support for bcm96345gw2 design Message-ID: <20090808193706.GC22761@linux-mips.org> References: <200908072347.04899.florian@openwrt.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <200908072347.04899.florian@openwrt.org> User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23869 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Fri, Aug 07, 2009 at 11:47:04PM +0200, Florian Fainelli wrote: Folded into the series. Ralf PS: More wham in this patch ... From ralf@linux-mips.org Sat Aug 8 21:39:56 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 08 Aug 2009 21:40:02 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:51421 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1493186AbZHHTj4 (ORCPT ); Sat, 8 Aug 2009 21:39:56 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id n78JeXHc001153; Sat, 8 Aug 2009 20:40:33 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id n78JeXdG001152; Sat, 8 Aug 2009 20:40:33 +0100 Date: Sat, 8 Aug 2009 20:40:33 +0100 From: Ralf Baechle To: Florian Fainelli Cc: linux-mips@linux-mips.org, Maxime Bizon Subject: Re: [PATCH 8/8] bcm63xx: prepare for on-board watchdog support Message-ID: <20090808194033.GD22761@linux-mips.org> References: <200908072347.16203.florian@openwrt.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <200908072347.16203.florian@openwrt.org> User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23870 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Fri, Aug 07, 2009 at 11:47:15PM +0200, Florian Fainelli wrote: > This patch registers the watchdog platform_device that > we are going to use in the watchdog platform_driver in > a subsequent patch. > > Signed-off-by: Florian Fainelli > --- > diff --git a/arch/mips/bcm63xx/Makefile b/arch/mips/bcm63xx/Makefile > index 70ba038..a4abc11 100644 > --- a/arch/mips/bcm63xx/Makefile > +++ b/arch/mips/bcm63xx/Makefile > @@ -5,6 +5,7 @@ obj-y += dev-usb-ohci.o > obj-y += dev-usb-ehci.o > obj-y += dev-enet.o > obj-y += dev-dsp.o > +obj-y += dev-wdt.o > obj-$(CONFIG_EARLY_PRINTK) += early_printk.o > > obj-y += boards/ > diff --git a/arch/mips/bcm63xx/boards/board_bcm963xx.c b/arch/mips/bcm63xx/boards/board_bcm963xx.c > index 17a8636..e6a7b4f 100644 > --- a/arch/mips/bcm63xx/boards/board_bcm963xx.c > +++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c > @@ -28,6 +28,7 @@ > #include > #include > #include > +#include > #include > > #define PFX "board_bcm963xx: " > @@ -798,6 +799,7 @@ int __init board_register_devices(void) > u32 val; > > bcm63xx_uart_register(); > + bcm63xx_wdt_register(); > > if (board.has_pccard) > bcm63xx_pcmcia_register(); > diff --git a/arch/mips/bcm63xx/dev-wdt.c b/arch/mips/bcm63xx/dev-wdt.c > new file mode 100644 > index 0000000..6e18489 > --- /dev/null > +++ b/arch/mips/bcm63xx/dev-wdt.c > @@ -0,0 +1,36 @@ > +/* > + * This file is subject to the terms and conditions of the GNU General Public > + * License. See the file "COPYING" in the main directory of this archive > + * for more details. > + * > + * Copyright (C) 2008 Florian Fainelli > + */ > + > +#include > +#include > +#include > +#include > + > +static struct resource wdt_resources[] = { > + { > + .start = -1, /* filled at runtime */ > + .end = -1, /* filled at runtime */ > + .flags = IORESOURCE_MEM, > + }, > +}; > + > +static struct platform_device bcm63xx_wdt_device = { > + .name = "bcm63xx-wdt", > + .id = 0, > + .num_resources = ARRAY_SIZE(wdt_resources), > + .resource = wdt_resources, > +}; > + > +int __init bcm63xx_wdt_register(void) > +{ > + wdt_resources[0].start = bcm63xx_regset_address(RSET_WDT); > + wdt_resources[0].end = wdt_resources[0].start; > + wdt_resources[0].end += RSET_WDT_SIZE - 1; > + > + return platform_device_register(&bcm63xx_wdt_device); > +} > diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_wdt.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_wdt.h > new file mode 100644 > index 0000000..4aae2c7 > --- /dev/null > +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_wdt.h > @@ -0,0 +1,6 @@ > +#ifndef BCM63XX_DEV_WDT_H_ > +#define BCM63XX_DEV_WDT_H_ > + > +int bcm63xx_wdt_register(void); > + > +#endif /* BCM63XX_DEV_WDT_H_ */ bcm63xx_dev_wdt.h only really exists to keep checpatch.pl happy - not a terribly good reason. I suggest to remove the explicit call to bcm63xx_wdt_register, make the function static and use some initfunc magic to call it and bcm63xx_dev_wdt.h can go. Ralf From geert.uytterhoeven@gmail.com Sun Aug 9 11:24:30 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 09 Aug 2009 11:24:41 +0200 (CEST) Received: from mail-pz0-f179.google.com ([209.85.222.179]:49794 "EHLO mail-pz0-f179.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492336AbZHIJYa convert rfc822-to-8bit (ORCPT ); Sun, 9 Aug 2009 11:24:30 +0200 Received: by pzk9 with SMTP id 9so2440325pzk.21 for ; Sun, 09 Aug 2009 02:24:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:in-reply-to:references :date:message-id:subject:from:to:cc:content-type :content-transfer-encoding; bh=Q3WOxl8MojeZWT3Vdz7XCVO+3c3ZYFb0gkVD0e4JeYM=; b=Y50sInO2LmGIo/rurZj4qr0h9UPnrU/qUO6eQ0n6VW8/TAZwjPzvr1K9HQGLrZxTMZ 4ah7eaaAF8gnOmoY0P9g6wvyzkQeip+xTHMHtBhLq7tkHBHr0tsqXd1sn4HrgSszcgCJ vKJyw/t0EfhYcITqBZS8n+WjXl1d8cByizyfY= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type:content-transfer-encoding; b=kNddhiIL7sye3WqW5tOE+csDchq7LSEUVn5Rzyh9+7bJubxSdqlOi4Xt0kEt9LJ87r MbFxysKXL8N6ctaoFevXTYwmORA5dzGhN7snDg2Le23C7GgDWLUuJWLpH+RtCzyBj9Wi c+pDM4YTMFEid0uVlixTutbH5StAdBC/JdUDQ= MIME-Version: 1.0 Received: by 10.142.187.6 with SMTP id k6mr243280wff.50.1249809861485; Sun, 09 Aug 2009 02:24:21 -0700 (PDT) In-Reply-To: References: Date: Sun, 9 Aug 2009 11:24:21 +0200 Message-ID: <10f740e80908090224p13d2119do9e4f4d7730ed001e@mail.gmail.com> Subject: Re: [Linux-fbdev-devel] [PATCH 3/3] drivers/video: Correct use of request_region/request_mem_region From: Geert Uytterhoeven To: Julia Lawall Cc: linux-fbdev-devel@lists.sourceforge.net, linux-kernel@vger.kernel.org, kernel-janitors@vger.kernel.org, linux-mips@linux-mips.org Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8BIT Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23871 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: geert.uytterhoeven@gmail.com Precedence: bulk X-list: linux-mips On Sun, Aug 9, 2009 at 09:44, Julia Lawall wrote: > From: Julia Lawall > > request_region should be used with release_region, not request_mem_region. > > The semantic patch that fixes this problem is as follows: > (http://coccinelle.lip6.fr/) > > // > @r1@ > expression start; > @@ > > request_region(start,...) > > @b1@ > expression r1.start; > @@ > > request_mem_region(start,...) > > @depends on !b1@ > expression r1.start; > expression E; > @@ > > - release_mem_region > + release_region >  (start,E) > // > > Signed-off-by: Julia Lawall > > --- >  drivers/video/gbefb.c  |    4 ++-- >  drivers/video/tdfxfb.c |    4 ++-- >  2 files changed, 4 insertions(+), 4 deletions(-) > > diff -u -p a/drivers/video/gbefb.c b/drivers/video/gbefb.c > --- a/drivers/video/gbefb.c > +++ b/drivers/video/gbefb.c > @@ -1246,7 +1246,7 @@ out_tiles_free: >  out_unmap: >        iounmap(gbe); >  out_release_mem_region: > -       release_mem_region(GBE_BASE, sizeof(struct sgi_gbe)); > +       release_region(GBE_BASE, sizeof(struct sgi_gbe)); GBE_BASE seems to be MMIO (it's mapped using ioremap()), so it looks like the release_mem_region() is actually correct, while the request_region() should be request_mem_region() instead >  out_release_framebuffer: >        framebuffer_release(info); > > @@ -1265,7 +1265,7 @@ static int __devexit gbefb_remove(struct >                iounmap(gbe_mem); >        dma_free_coherent(NULL, GBE_TLB_SIZE * sizeof(uint16_t), >                          (void *)gbe_tiles.cpu, gbe_tiles.dma); > -       release_mem_region(GBE_BASE, sizeof(struct sgi_gbe)); > +       release_region(GBE_BASE, sizeof(struct sgi_gbe)); Ditto. > diff -u -p a/drivers/video/tdfxfb.c b/drivers/video/tdfxfb.c > --- a/drivers/video/tdfxfb.c > +++ b/drivers/video/tdfxfb.c > @@ -1571,8 +1571,8 @@ out_err_iobase: >        if (default_par->mtrr_handle >= 0) >                mtrr_del(default_par->mtrr_handle, info->fix.smem_start, >                         info->fix.smem_len); > -       release_mem_region(pci_resource_start(pdev, 2), > -                          pci_resource_len(pdev, 2)); > +       release_region(pci_resource_start(pdev, 2), > +                      pci_resource_len(pdev, 2)); >  out_err_screenbase: >        if (info->screen_base) >                iounmap(info->screen_base); This one looks OK. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds From julia@diku.dk Sun Aug 9 11:37:17 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 09 Aug 2009 11:37:23 +0200 (CEST) Received: from mgw2.diku.dk ([130.225.96.92]:55668 "EHLO mgw2.diku.dk" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492337AbZHIJhR (ORCPT ); Sun, 9 Aug 2009 11:37:17 +0200 Received: from localhost (localhost [127.0.0.1]) by mgw2.diku.dk (Postfix) with ESMTP id 4C05419BB97; Sun, 9 Aug 2009 11:37:16 +0200 (CEST) Received: from mgw2.diku.dk ([127.0.0.1]) by localhost (mgw2.diku.dk [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 02585-05; Sun, 9 Aug 2009 11:37:13 +0200 (CEST) Received: from nhugin.diku.dk (nhugin.diku.dk [130.225.96.140]) by mgw2.diku.dk (Postfix) with ESMTP id EE11919BCCD; Sun, 9 Aug 2009 11:33:07 +0200 (CEST) Received: from ask.diku.dk (ask.diku.dk [130.225.96.225]) by nhugin.diku.dk (Postfix) with ESMTP id B45E26DFB5B; Sun, 9 Aug 2009 11:32:06 +0200 (CEST) Received: by ask.diku.dk (Postfix, from userid 3767) id B819F154F68; Sun, 9 Aug 2009 11:33:07 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by ask.diku.dk (Postfix) with ESMTP id B35A9154E41; Sun, 9 Aug 2009 11:33:07 +0200 (CEST) Date: Sun, 9 Aug 2009 11:33:07 +0200 (CEST) From: Julia Lawall To: Geert Uytterhoeven Cc: linux-fbdev-devel@lists.sourceforge.net, linux-kernel@vger.kernel.org, kernel-janitors@vger.kernel.org, linux-mips@linux-mips.org Subject: Re: [Linux-fbdev-devel] [PATCH 3/3] drivers/video: Correct use of request_region/request_mem_region In-Reply-To: <10f740e80908090224p13d2119do9e4f4d7730ed001e@mail.gmail.com> Message-ID: References: <10f740e80908090224p13d2119do9e4f4d7730ed001e@mail.gmail.com> MIME-Version: 1.0 Content-Type: MULTIPART/MIXED; BOUNDARY="-511516320-771632445-1249810387=:13271" X-Virus-Scanned: amavisd-new at diku.dk Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23872 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: julia@diku.dk Precedence: bulk X-list: linux-mips This message is in MIME format. The first part should be readable text, while the remaining parts are likely unreadable without MIME-aware tools. ---511516320-771632445-1249810387=:13271 Content-Type: TEXT/PLAIN; charset=iso-8859-1 Content-Transfer-Encoding: 8BIT Thanks forthe information. I will fix the occurrences in gbefb.c and then submit a revised vesion of the complete patch. julia On Sun, 9 Aug 2009, Geert Uytterhoeven wrote: > On Sun, Aug 9, 2009 at 09:44, Julia Lawall wrote: > > From: Julia Lawall > > > > request_region should be used with release_region, not request_mem_region. > > > > The semantic patch that fixes this problem is as follows: > > (http://coccinelle.lip6.fr/) > > > > // > > @r1@ > > expression start; > > @@ > > > > request_region(start,...) > > > > @b1@ > > expression r1.start; > > @@ > > > > request_mem_region(start,...) > > > > @depends on !b1@ > > expression r1.start; > > expression E; > > @@ > > > > - release_mem_region > > + release_region > >  (start,E) > > // > > > > Signed-off-by: Julia Lawall > > > > --- > >  drivers/video/gbefb.c  |    4 ++-- > >  drivers/video/tdfxfb.c |    4 ++-- > >  2 files changed, 4 insertions(+), 4 deletions(-) > > > > diff -u -p a/drivers/video/gbefb.c b/drivers/video/gbefb.c > > --- a/drivers/video/gbefb.c > > +++ b/drivers/video/gbefb.c > > @@ -1246,7 +1246,7 @@ out_tiles_free: > >  out_unmap: > >        iounmap(gbe); > >  out_release_mem_region: > > -       release_mem_region(GBE_BASE, sizeof(struct sgi_gbe)); > > +       release_region(GBE_BASE, sizeof(struct sgi_gbe)); > > GBE_BASE seems to be MMIO (it's mapped using ioremap()), so it looks like the > release_mem_region() is actually correct, while the request_region() should be > request_mem_region() instead > > >  out_release_framebuffer: > >        framebuffer_release(info); > > > > @@ -1265,7 +1265,7 @@ static int __devexit gbefb_remove(struct > >                iounmap(gbe_mem); > >        dma_free_coherent(NULL, GBE_TLB_SIZE * sizeof(uint16_t), > >                          (void *)gbe_tiles.cpu, gbe_tiles.dma); > > -       release_mem_region(GBE_BASE, sizeof(struct sgi_gbe)); > > +       release_region(GBE_BASE, sizeof(struct sgi_gbe)); > > Ditto. > > > diff -u -p a/drivers/video/tdfxfb.c b/drivers/video/tdfxfb.c > > --- a/drivers/video/tdfxfb.c > > +++ b/drivers/video/tdfxfb.c > > @@ -1571,8 +1571,8 @@ out_err_iobase: > >        if (default_par->mtrr_handle >= 0) > >                mtrr_del(default_par->mtrr_handle, info->fix.smem_start, > >                         info->fix.smem_len); > > -       release_mem_region(pci_resource_start(pdev, 2), > > -                          pci_resource_len(pdev, 2)); > > +       release_region(pci_resource_start(pdev, 2), > > +                      pci_resource_len(pdev, 2)); > >  out_err_screenbase: > >        if (info->screen_base) > >                iounmap(info->screen_base); > > This one looks OK. > > Gr{oetje,eeting}s, > > Geert > > -- > Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org > > In personal conversations with technical people, I call myself a hacker. But > when I'm talking to journalists I just say "programmer" or something like that. > -- Linus Torvalds > -- > To unsubscribe from this list: send the line "unsubscribe kernel-janitors" in > the body of a message to majordomo@vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html > ---511516320-771632445-1249810387=:13271-- From julia@diku.dk Sun Aug 9 11:48:42 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 09 Aug 2009 11:48:48 +0200 (CEST) Received: from mgw1.diku.dk ([130.225.96.91]:35355 "EHLO mgw1.diku.dk" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492240AbZHIJsm (ORCPT ); Sun, 9 Aug 2009 11:48:42 +0200 Received: from localhost (localhost [127.0.0.1]) by mgw1.diku.dk (Postfix) with ESMTP id B77CB52C404; Sun, 9 Aug 2009 11:48:41 +0200 (CEST) X-Virus-Scanned: amavisd-new at diku.dk Received: from mgw1.diku.dk ([127.0.0.1]) by localhost (mgw1.diku.dk [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id x+X8d9TzOqsM; Sun, 9 Aug 2009 11:48:39 +0200 (CEST) Received: from nhugin.diku.dk (nhugin.diku.dk [130.225.96.140]) by mgw1.diku.dk (Postfix) with ESMTP id C4B7952C45F; Sun, 9 Aug 2009 11:42:32 +0200 (CEST) Received: from ask.diku.dk (ask.diku.dk [130.225.96.225]) by nhugin.diku.dk (Postfix) with ESMTP id 9C2AB6DFD13; Sun, 9 Aug 2009 11:41:31 +0200 (CEST) Received: by ask.diku.dk (Postfix, from userid 3767) id A279A154F68; Sun, 9 Aug 2009 11:42:32 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by ask.diku.dk (Postfix) with ESMTP id 9F8A51549A9; Sun, 9 Aug 2009 11:42:32 +0200 (CEST) Date: Sun, 9 Aug 2009 11:42:32 +0200 (CEST) From: Julia Lawall To: Geert Uytterhoeven Cc: linux-fbdev-devel@lists.sourceforge.net, linux-kernel@vger.kernel.org, kernel-janitors@vger.kernel.org, linux-mips@linux-mips.org Subject: Re: [Linux-fbdev-devel] [PATCH 3/3] drivers/video: Correct use of request_region/request_mem_region In-Reply-To: <10f740e80908090224p13d2119do9e4f4d7730ed001e@mail.gmail.com> Message-ID: References: <10f740e80908090224p13d2119do9e4f4d7730ed001e@mail.gmail.com> MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23873 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: julia@diku.dk Precedence: bulk X-list: linux-mips From: Julia Lawall request_region should be used with release_region, not request_mem_region. Geert Uytterhoeven pointed out that in the case of drivers/video/gbefb.c, the problem is actually the other way around; request_mem_region should be used instead of request_region. The semantic patch that finds/fixes this problem is as follows: (http://coccinelle.lip6.fr/) // @r1@ expression start; @@ request_region(start,...) @b1@ expression r1.start; @@ request_mem_region(start,...) @depends on !b1@ expression r1.start; expression E; @@ - release_mem_region + release_region (start,E) // Signed-off-by: Julia Lawall --- drivers/video/gbefb.c | 2 +- drivers/video/tdfxfb.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff -u -p a/drivers/video/gbefb.c b/drivers/video/gbefb.c --- a/drivers/video/gbefb.c +++ b/drivers/video/gbefb.c @@ -1147,7 +1147,7 @@ static int __init gbefb_probe(struct pla gbefb_setup(options); #endif - if (!request_region(GBE_BASE, sizeof(struct sgi_gbe), "GBE")) { + if (!request_mem_region(GBE_BASE, sizeof(struct sgi_gbe), "GBE")) { printk(KERN_ERR "gbefb: couldn't reserve mmio region\n"); ret = -EBUSY; goto out_release_framebuffer; diff -u -p a/drivers/video/tdfxfb.c b/drivers/video/tdfxfb.c --- a/drivers/video/tdfxfb.c +++ b/drivers/video/tdfxfb.c @@ -1571,8 +1571,8 @@ out_err_iobase: if (default_par->mtrr_handle >= 0) mtrr_del(default_par->mtrr_handle, info->fix.smem_start, info->fix.smem_len); - release_mem_region(pci_resource_start(pdev, 2), - pci_resource_len(pdev, 2)); + release_region(pci_resource_start(pdev, 2), + pci_resource_len(pdev, 2)); out_err_screenbase: if (info->screen_base) iounmap(info->screen_base); From sgi-linux-mips@m.gmane.org Mon Aug 10 00:08:21 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 10 Aug 2009 00:08:27 +0200 (CEST) Received: from main.gmane.org ([80.91.229.2]:53705 "EHLO ciao.gmane.org" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1493204AbZHIWIV (ORCPT ); Mon, 10 Aug 2009 00:08:21 +0200 Received: from list by ciao.gmane.org with local (Exim 4.43) id 1MaGYq-0001fd-6Z for linux-mips@linux-mips.org; Sun, 09 Aug 2009 22:08:16 +0000 Received: from chipmunk.wormnet.eu ([195.195.131.226]) by main.gmane.org with esmtp (Gmexim 0.1 (Debian)) id 1AlnuQ-0007hv-00 for ; Sun, 09 Aug 2009 22:08:16 +0000 Received: from alex by chipmunk.wormnet.eu with local (Gmexim 0.1 (Debian)) id 1AlnuQ-0007hv-00 for ; Sun, 09 Aug 2009 22:08:16 +0000 X-Injected-Via-Gmane: http://gmane.org/ To: linux-mips@linux-mips.org From: Alexander Clouter Subject: Re: [PATCH] MIPS: add support for gzip/bzip2/lzma compressed kernel images Date: Sun, 9 Aug 2009 22:36:46 +0100 Lines: 49 Message-ID: References: <1249757707-8876-1-git-send-email-wuzhangjin@gmail.com> X-Complaints-To: usenet@ger.gmane.org X-Gmane-NNTP-Posting-Host: chipmunk.wormnet.eu User-Agent: tin/1.9.3-20080506 ("Dalintober") (UNIX) (Linux/2.6.26-2-sparc64-smp (sparc64)) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23874 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: alex@digriz.org.uk Precedence: bulk X-list: linux-mips Wu Zhangjin wrote: > > This patch will help to generate smaller kernel images for linux-MIPS, > /me gets giddy and wets himself with excitement This has made my AR7[1] based Linksys WAG54Gv2 (16MB RAM and 4MB flash, limited to a 768kB kernel) useful, finally...thanks! > $ wc -c vmlinux > 7465416 vmlinux > $ wc -c vmlinuz > 2059691 vmlinuz > > Have tested the 32bit kernel on Qemu/Malta and 64bit kernel on FuLoong > Mini PC. both of them works well. > I got it working (LZMA kernel) however you have hardcoded a lot of bits in there. It looks to my uneducated eye most of the issues lie in that getting a suitable PORT(x), KERNEL_START, KERNEL_SIZE, FREE_MEM_START and FREE_MEM_END is non-trivial on the MIPS platform currently; probably because of the lack of a generic lzma/gzip/bzip2 framework to be used with. For me I used: #define FREE_MEM_START CKSEG0ADDR(0x94a00000) #define FREE_MEM_END CKSEG0ADDR(0x94f00000) I had to replace (you probably should move this from dbg.c to dbg.h): #define PORT(offset) (CKSEG1ADDR(AR7_REGS_UART0) + (4 * offset)) The load address is awkward, but I replaced your 0x8100000 in the Makefile with 0x94400000. Now, the big question is how to work this all out at compile time. :) As a side note, I would personally leave the DEBUG non-optional and turned on as it all disappears at runtime anyway, but I'm no kernel developer :) Again, thanks for this, it truely is great stuff. Cheers [1] http://www.linux-mips.org/wiki/AR7 -- Alexander Clouter .sigmonster says: I will always love the false image I had of you. From wuzhangjin@gmail.com Mon Aug 10 09:08:05 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 10 Aug 2009 09:08:12 +0200 (CEST) Received: from wf-out-1314.google.com ([209.85.200.173]:45551 "EHLO wf-out-1314.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492456AbZHJHIF (ORCPT ); Mon, 10 Aug 2009 09:08:05 +0200 Received: by wf-out-1314.google.com with SMTP id 28so1035970wfa.21 for ; Mon, 10 Aug 2009 00:08:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer; bh=Yaa6bBnjbRRMfxSmyp+JnNJwbPgoxYQMkFwc0jb83Pg=; b=wh1zdXj5GMI+qYcLXybwl9HLagb2QKF8LicP5DH+Ax5WACe0V33Bp4wk3E+e/7YKkM jL2OWhfIGoQhDSWOotUXyMjusqvBiKmGlvw+RSDMdVrZ6W8TyZIllQyFvCgnZz4T+VQl uBnccQ8iUhZPXdGaQuvkUdNomzz3MzPyjl3T4= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer; b=sarkCzAG506RnmS/CqXhX0jT5Q9gdqV1FUJLcBLM4N4/kXiMMLlGFKhrwvVsDzZLbA K0MjUUsVS2boK7R1p4m3bSb8Db+TgQhCQlDqnQZ3zI6Ra0Jv2NOWpDUvYsCHr9XLKPw0 k4mw1XGf7b7CIAtyA0gKLE4Z2Cz0z6TpXjvM4= Received: by 10.142.143.12 with SMTP id q12mr705220wfd.146.1249888083597; Mon, 10 Aug 2009 00:08:03 -0700 (PDT) Received: from localhost.localdomain ([222.92.8.142]) by mx.google.com with ESMTPS id 22sm11025543wfd.28.2009.08.10.00.08.00 (version=TLSv1/SSLv3 cipher=RC4-MD5); Mon, 10 Aug 2009 00:08:02 -0700 (PDT) From: Wu Zhangjin To: linux-mips@linux-mips.org, Linux Kernel list Cc: Nicolas Thill , Ralf Baechle , Enrik Berkhan , Wu Zhangjin Subject: [PATCH] MIPS: AR7: fix wrong including path of rt7.h in ar7_wdt.c Date: Mon, 10 Aug 2009 15:07:54 +0800 Message-Id: <1249888074-20784-1-git-send-email-wuzhangjin@gmail.com> X-Mailer: git-send-email 1.6.2.1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23875 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips Signed-off-by: Wu Zhangjin --- drivers/watchdog/ar7_wdt.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/drivers/watchdog/ar7_wdt.c b/drivers/watchdog/ar7_wdt.c index 3fe9742..ec48e12 100644 --- a/drivers/watchdog/ar7_wdt.c +++ b/drivers/watchdog/ar7_wdt.c @@ -37,7 +37,7 @@ #include #include -#include +#include #define DRVNAME "ar7_wdt" #define LONGNAME "TI AR7 Watchdog Timer" -- 1.6.2.1 From f.fainelli@gmail.com Mon Aug 10 09:39:49 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 10 Aug 2009 09:39:55 +0200 (CEST) Received: from mail-ew0-f216.google.com ([209.85.219.216]:41843 "EHLO mail-ew0-f216.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492376AbZHJHjt convert rfc822-to-8bit (ORCPT ); Mon, 10 Aug 2009 09:39:49 +0200 Received: by ewy12 with SMTP id 12so3404110ewy.0 for ; Mon, 10 Aug 2009 00:39:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:sender:from:to:subject:date :user-agent:cc:references:in-reply-to:mime-version:content-type :content-transfer-encoding:content-disposition:message-id; bh=ZRhA308PCEXlzSRLd2Is1eX+eZas0IA7Yh2145x0/QE=; b=h0RlkxXX4pzE/+aeNFckQLB+W/wqu2fZ/sOOnA+J+d8xqwTxfkXbjtL5n+QbY9XcJa V6ek4qmCN//WD0cuKm4J78c0F5GZoVPxOXv6kq/hmA1G+mjQYMBPzq7B2XYb89UVHoF+ p2sPsOHHIPwySNTHj+vwcri8MzAo8qaPMoAvE= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:from:to:subject:date:user-agent:cc:references:in-reply-to :mime-version:content-type:content-transfer-encoding :content-disposition:message-id; b=weJE8uOw/Wh9TJfLfnJ0BQS0UKMY+NKg4C2iclJzHicZpFL9QlWdXRSnMSJK9jX0nn GAxCYxIscd1hjqClZnrDwByneSqEWgBvm7Co0534+4iWgd+XSQmvXNgOkk+1MLNOUchX QkZvlmHQ8YKs1pqYFuJjElbYfREmkYedmcTDk= Received: by 10.210.131.6 with SMTP id e6mr4805219ebd.63.1249889983984; Mon, 10 Aug 2009 00:39:43 -0700 (PDT) Received: from florian.lab.openpattern.org (lab.openpattern.org [82.240.16.241]) by mx.google.com with ESMTPS id 5sm10445602eyh.16.2009.08.10.00.39.42 (version=TLSv1/SSLv3 cipher=RC4-MD5); Mon, 10 Aug 2009 00:39:42 -0700 (PDT) From: Florian Fainelli To: Wu Zhangjin Subject: Re: [PATCH] MIPS: AR7: fix wrong including path of rt7.h in ar7_wdt.c Date: Mon, 10 Aug 2009 09:39:39 +0200 User-Agent: KMail/1.9.9 Cc: linux-mips@linux-mips.org, Linux Kernel list , Nicolas Thill , Ralf Baechle , Enrik Berkhan References: <1249888074-20784-1-git-send-email-wuzhangjin@gmail.com> In-Reply-To: <1249888074-20784-1-git-send-email-wuzhangjin@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8BIT Content-Disposition: inline Message-Id: <200908100939.40963.florian@openwrt.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23876 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips Hi Wu, Le Monday 10 August 2009 09:07:54 Wu Zhangjin, vous avez écrit : > Signed-off-by: Wu Zhangjin Thanks, but that was sent a while ago to Wim Van Sebroeck who is the watchdog subsystem maintainer. > --- > drivers/watchdog/ar7_wdt.c | 2 +- > 1 files changed, 1 insertions(+), 1 deletions(-) > > diff --git a/drivers/watchdog/ar7_wdt.c b/drivers/watchdog/ar7_wdt.c > index 3fe9742..ec48e12 100644 > --- a/drivers/watchdog/ar7_wdt.c > +++ b/drivers/watchdog/ar7_wdt.c > @@ -37,7 +37,7 @@ > #include > > #include > -#include > +#include > > #define DRVNAME "ar7_wdt" > #define LONGNAME "TI AR7 Watchdog Timer" -- Best regards, Florian Fainelli Email: florian@openwrt.org Web: http://openwrt.org IRC: [florian] on irc.freenode.net ------------------------------- From wuzhangjin@gmail.com Mon Aug 10 10:49:29 2009 Received: with ECARTIS (v1.0.0; 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Mon, 10 Aug 2009 01:49:24 -0700 (PDT) Received: from localhost.localdomain ([222.92.8.142]) by mx.google.com with ESMTPS id k41sm20596144rvb.38.2009.08.10.01.49.20 (version=TLSv1/SSLv3 cipher=RC4-MD5); Mon, 10 Aug 2009 01:49:24 -0700 (PDT) From: Wu Zhangjin To: linux-mips@linux-mips.org Cc: Ralf Baechle , Alexander Clouter , Wu Zhangjin Subject: [PATCH -v1] MIPS: add support for gzip/bzip2/lzma compressed kernel images Date: Mon, 10 Aug 2009 16:49:14 +0800 Message-Id: <1249894154-10982-1-git-send-email-wuzhangjin@gmail.com> X-Mailer: git-send-email 1.6.2.1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23877 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips This patch will help to generate smaller kernel images for linux-MIPS, Here is the effect when using lzma: $ ls -sh vmlinux 7.1M vmlinux $ ls -sh arch/mips/boot/compressed/vmlinuz 1.5M arch/mips/boot/compressed/vmlinuz Have tested the 32bit kernel on Qemu/Malta and 64bit kernel on FuLoong Mini PC. both of them work well. and this revision incorporates the feedback from Alexander Clouter , he helped to test it on AR7[1] based Linksys WAG54Gv2 and gave good suggestion on board-independence. NOTE: this should work for the other MIPS-based machines, but I have used the command bc in the Makefile to calculate the load address of the compressed kernel. I'm not sure this is suitable. perhaps I need to rewrite this part in C program or somebody help to simplify the current implementation. Signed-off-by: Wu Zhangjin --- arch/mips/Kconfig | 3 + arch/mips/Makefile | 11 ++- arch/mips/boot/compressed/Makefile | 72 +++++++++++++++ arch/mips/boot/compressed/dbg.c | 64 ++++++++++++++ arch/mips/boot/compressed/dbg.h | 19 ++++ arch/mips/boot/compressed/decompress.c | 149 +++++++++++++++++++++++++++++++ arch/mips/boot/compressed/dummy.c | 4 + arch/mips/boot/compressed/head.S | 86 ++++++++++++++++++ arch/mips/boot/compressed/ld.script | 150 ++++++++++++++++++++++++++++++++ 9 files changed, 556 insertions(+), 2 deletions(-) create mode 100644 arch/mips/boot/compressed/Makefile create mode 100644 arch/mips/boot/compressed/dbg.c create mode 100644 arch/mips/boot/compressed/dbg.h create mode 100644 arch/mips/boot/compressed/decompress.c create mode 100644 arch/mips/boot/compressed/dummy.c create mode 100644 arch/mips/boot/compressed/head.S create mode 100644 arch/mips/boot/compressed/ld.script diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 3ca0fe1..fae7029 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -4,6 +4,9 @@ config MIPS select HAVE_IDE select HAVE_OPROFILE select HAVE_ARCH_KGDB + select HAVE_KERNEL_GZIP + select HAVE_KERNEL_BZIP2 + select HAVE_KERNEL_LZMA # Horrible source of confusion. Die, die, die ... select EMBEDDED select RTC_LIB diff --git a/arch/mips/Makefile b/arch/mips/Makefile index 861da51..300b996 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -709,7 +709,10 @@ vmlinux.64: vmlinux makeboot =$(Q)$(MAKE) $(build)=arch/mips/boot VMLINUX=$(vmlinux-32) $(1) -all: $(all-y) +all: $(all-y) zImage + +zImage: vmlinux + $(Q)$(MAKE) $(build)=arch/mips/boot/compressed $@ LOADADDR=$(load-y) vmlinux.bin: $(vmlinux-32) +@$(call makeboot,$@) @@ -735,11 +738,13 @@ endif install: $(Q)install -D -m 755 vmlinux $(INSTALL_PATH)/vmlinux-$(KERNELRELEASE) + $(Q)install -D -m 755 vmlinuz $(INSTALL_PATH)/vmlinuz-$(KERNELRELEASE) $(Q)install -D -m 644 .config $(INSTALL_PATH)/config-$(KERNELRELEASE) $(Q)install -D -m 644 System.map $(INSTALL_PATH)/System.map-$(KERNELRELEASE) archclean: @$(MAKE) $(clean)=arch/mips/boot + @$(MAKE) $(clean)=arch/mips/boot/compressed @$(MAKE) $(clean)=arch/mips/lasat define archhelp @@ -747,10 +752,12 @@ define archhelp echo ' vmlinux.ecoff - ECOFF boot image' echo ' vmlinux.bin - Raw binary boot image' echo ' vmlinux.srec - SREC boot image' + echo ' vmlinuz - Compressed boot image' echo echo ' These will be default as apropriate for a configured platform.' endef CLEAN_FILES += vmlinux.32 \ vmlinux.64 \ - vmlinux.ecoff + vmlinux.ecoff \ + vmlinuz diff --git a/arch/mips/boot/compressed/Makefile b/arch/mips/boot/compressed/Makefile new file mode 100644 index 0000000..f9ccd97 --- /dev/null +++ b/arch/mips/boot/compressed/Makefile @@ -0,0 +1,72 @@ +# +# This file is subject to the terms and conditions of the GNU General Public +# License. +# +# Adapted for MIPS Pete Popov, Dan Malek +# +# Copyright (C) 1994 by Linus Torvalds +# Adapted for PowerPC by Gary Thomas +# modified by Cort (cort@cs.nmt.edu) +# +# Copyright (C) 2009 Lemote Inc. & Insititute of Computing Technology +# Author: Wu Zhangjin +# + +# The load address of the compressed kernel, VMLINUZ_LOAD_ADDRESS > VMLINUX_LOAD_ADDRESS + VMLINUX_SIZE +VMLINUX_SIZE := $(shell wc -c $(objtree)/$(KBUILD_IMAGE) 2>/dev/null | cut -d' ' -f1) +VMLINUX_SIZE := $(shell echo "obase=16;ibase=10;(($(VMLINUX_SIZE)/65536 + 1) * 65536)" | bc | cut -d'.' -f1) +VMLINUX_LOAD_ADDRESS = $(shell echo $(LOADADDR) | sed -e "s/0xffffffff//g") +VMLINUZ_LOAD_ADDRESS := $(shell echo "obase=16; ibase=16; ($(VMLINUX_LOAD_ADDRESS) + $(VMLINUX_SIZE))" | bc) +VMLINUZ_LOAD_ADDRESS := 0x$(if $(CONFIG_64BIT),ffffffff,)$(VMLINUZ_LOAD_ADDRESS) +LOADADDR := 0x$(if $(CONFIG_64BIT),ffffffff,)$(VMLINUX_LOAD_ADDRESS) + +# set the default size of the mallocing area for decompressing +BOOT_HEAP_SIZE := 0x400000 + +KBUILD_CFLAGS := $(LINUXINCLUDE) $(KBUILD_CFLAGS) -D__KERNEL__ \ + -DBOOT_HEAP_SIZE=$(BOOT_HEAP_SIZE) -D"LOADADDR=$(LOADADDR)ull" \ + +# uncomment the -DDEBUG to enable serial port debugging for your machine +# and please ensure there is a suitable serial port address defined in dbg.h +KBUILD_CFLAGS += #-DDEBUG + +KBUILD_AFLAGS := $(LINUXINCLUDE) $(KBUILD_AFLAGS) -D__ASSEMBLY__ \ + -DKERNEL_ENTRY=0x$(shell $(NM) $(objtree)/$(KBUILD_IMAGE) 2>/dev/null | grep " kernel_entry" | cut -f1 -d \ ) \ + -DBOOT_HEAP_SIZE=$(BOOT_HEAP_SIZE) + +OBJECTS := $(obj)/head.o $(obj)/decompress.o $(obj)/dbg.o + +OBJCOPYFLAGS_vmlinux.bin := $(OBJCOPYFLAGS) -O binary -R .comment -S +$(obj)/vmlinux.bin: $(KBUILD_IMAGE) + $(call if_changed,objcopy) + +suffix_$(CONFIG_KERNEL_GZIP) = gz +suffix_$(CONFIG_KERNEL_BZIP2) = bz2 +suffix_$(CONFIG_KERNEL_LZMA) = lzma +tool_$(CONFIG_KERNEL_GZIP) = gzip +tool_$(CONFIG_KERNEL_BZIP2) = bzip2 +tool_$(CONFIG_KERNEL_LZMA) = lzma +$(obj)/vmlinux.$(suffix_y): $(obj)/vmlinux.bin + $(call if_changed,$(tool_y)) + $(Q)rm -f $< + +$(obj)/piggy.o: $(obj)/vmlinux.$(suffix_y) $(obj)/dummy.o + $(Q)$(OBJCOPY) $(OBJCOPYFLAGS) \ + --add-section=.image=$< \ + --set-section-flags=.image=contents,alloc,load,readonly,data \ + $(obj)/dummy.o $@ + $(Q)rm -f $< + +LDFLAGS_vmlinuz := $(LDFLAGS) -Ttext $(VMLINUZ_LOAD_ADDRESS) -T +$(obj)/vmlinuz: $(src)/ld.script $(OBJECTS) $(obj)/piggy.o + $(call if_changed,ld) + $(Q)$(OBJCOPY) $(OBJCOPYFLAGS) -R .comment -R .stab -R .stabstr -R .initrd -R .sysmap $@ + $(Q)rm -f $(obj)/piggy.o + +zImage: $(obj)/vmlinuz + $(Q)ln -sf $< $(objtree)/vmlinuz + $(Q)echo " SYMLINK $(objtree)/vmlinuz" + +clean: +clean-files += *.o \ + vmlinu* diff --git a/arch/mips/boot/compressed/dbg.c b/arch/mips/boot/compressed/dbg.c new file mode 100644 index 0000000..04db05f --- /dev/null +++ b/arch/mips/boot/compressed/dbg.c @@ -0,0 +1,64 @@ +/* + * MIPS-specific debug support for pre-boot environment + */ + +#ifdef DEBUG + +#include +#include +#include + +#include "dbg.h" + +static inline unsigned int serial_in(int offset) +{ + return *((char *)PORT(offset)); +} + +static inline void serial_out(int offset, int value) +{ + *((char *)PORT(offset)) = value; +} + +int putc(char c) +{ + while ((serial_in(UART_LSR) & UART_LSR_THRE) == 0) + ; + + serial_out(UART_TX, c); + + return 1; +} + +void puts(const char *s) +{ + char c; + while ((c = *s++) != '\0') { + putc(c); + if (c == '\n') + putc('\r'); + } +} + +void puthex(unsigned long long val) +{ + + unsigned char buf[10]; + int i; + for (i = 7; i >= 0; i--) { + buf[i] = "0123456789ABCDEF"[val & 0x0F]; + val >>= 4; + } + buf[8] = '\0'; + puts(buf); +} + + +#else +void puts(const char *s) +{ +} +void puthex(unsigned long long val) +{ +} +#endif diff --git a/arch/mips/boot/compressed/dbg.h b/arch/mips/boot/compressed/dbg.h new file mode 100644 index 0000000..ee5f1fd --- /dev/null +++ b/arch/mips/boot/compressed/dbg.h @@ -0,0 +1,19 @@ +/* + * board-specific serial port + */ + +#include + +#ifdef CONFIG_LEMOTE_FULONG +#define UART_BASE 0x1fd003f8 +#define PORT(offset) (CKSEG1ADDR(UART_BASE) + (offset)) +#endif + +#ifdef CONFIG_AR7 +#include +#define PORT(offset) (CKSEG1ADDR(AR7_REGS_UART0) + (4 * offset)) +#endif + +#ifndef PORT +#error please define the serial port address for your own machine +#endif diff --git a/arch/mips/boot/compressed/decompress.c b/arch/mips/boot/compressed/decompress.c new file mode 100644 index 0000000..2283e61 --- /dev/null +++ b/arch/mips/boot/compressed/decompress.c @@ -0,0 +1,149 @@ +/* + * Misc. bootloader code for many machines. + * + * Copyright 2001 MontaVista Software Inc. + * Author: Matt Porter Derived from + * arch/ppc/boot/prep/misc.c + * + * Copyright (C) 2009 Lemote, Inc. & Institute of Computing Technology + * Author: Wu Zhangjin + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include +#include + +#include + +/* These two variables specify the free mem region + * that can be used for temporary malloc area + */ +unsigned long free_mem_ptr; +unsigned long free_mem_end_ptr; +char *zimage_start; + +/* The linker tells us where the image is. */ +extern unsigned char __image_begin, __image_end; +extern unsigned char __ramdisk_begin, __ramdisk_end; +unsigned long initrd_size; + +/* debug interfaces */ +extern void puts(const char *s); +extern void puthex(unsigned long long val); + +void error(char *x) +{ + puts("\n\n"); + puts(x); + puts("\n\n -- System halted"); + + while (1) + ; /* Halt */ +} + +/* activate the code for pre-boot environment */ +#define STATIC static + +#ifdef CONFIG_KERNEL_GZIP +void *memcpy(void *dest, const void *src, size_t n) +{ + int i; + const char *s = src; + char *d = dest; + + for (i = 0; i < n; i++) + d[i] = s[i]; + return dest; +} +#include "../../../../lib/decompress_inflate.c" +#endif + +#ifdef CONFIG_KERNEL_BZIP2 +void *memset(void *s, int c, size_t n) +{ + int i; + char *ss = s; + + for (i = 0; i < n; i++) + ss[i] = c; + return s; +} +#include "../../../../lib/decompress_bunzip2.c" +#endif + +#ifdef CONFIG_KERNEL_LZMA +#include "../../../../lib/decompress_unlzma.c" +#endif + +void decompress_kernel(unsigned long load_addr, int num_words, + unsigned long cksum, unsigned long boot_heap_start) +{ + extern unsigned long start; + int zimage_size; + + initrd_size = (unsigned long)(&__ramdisk_end) - + (unsigned long)(&__ramdisk_begin); + + /* + * Reveal where we were loaded at and where we + * were relocated to. + */ + puts("loaded at: "); + puthex(load_addr); + puts(" "); + puthex((unsigned long)(load_addr + (4 * num_words))); + puts("\n"); + if ((unsigned long)load_addr != (unsigned long)&start) { + puts("relocated to: "); + puthex((unsigned long)&start); + puts(" "); + puthex((unsigned long)((unsigned long)&start + + (4 * num_words))); + puts("\n"); + } + + /* + * We link ourself to an arbitrary low address. When we run, we + * relocate outself to that address. __image_beign points to + * the part of the image where the zImage is. -- Tom + */ + zimage_start = (char *)(unsigned long)(&__image_begin); + zimage_size = (unsigned long)(&__image_end) - + (unsigned long)(&__image_begin); + + /* + * The zImage and initrd will be between start and _end, so they've + * already been moved once. We're good to go now. -- Tom + */ + puts("zimage at: "); + puthex((unsigned long)zimage_start); + puts(" "); + puthex((unsigned long)(zimage_size + zimage_start)); + puts("\n"); + + if (initrd_size) { + puts("initrd at: "); + puthex((unsigned long)(&__ramdisk_begin)); + puts(" "); + puthex((unsigned long)(&__ramdisk_end)); + puts("\n"); + } + + /* this area are prepared for mallocing when decompressing */ + free_mem_ptr = boot_heap_start; + free_mem_end_ptr = boot_heap_start + BOOT_HEAP_SIZE; + + /* Display standard Linux/MIPS boot prompt for kernel args */ + puts("Uncompressing Linux at load address "); + puthex(LOADADDR); + puts("\n"); + /* Decompress the kernel with according algorithm */ + decompress(zimage_start, zimage_size, 0, 0, + (void *)LOADADDR, 0, error); + /* FIXME: is there a need to flush cache here? */ + puts("Now, booting the kernel...\n"); +} diff --git a/arch/mips/boot/compressed/dummy.c b/arch/mips/boot/compressed/dummy.c new file mode 100644 index 0000000..31dbf45 --- /dev/null +++ b/arch/mips/boot/compressed/dummy.c @@ -0,0 +1,4 @@ +int main(void) +{ + return 0; +} diff --git a/arch/mips/boot/compressed/head.S b/arch/mips/boot/compressed/head.S new file mode 100644 index 0000000..f4c29fc --- /dev/null +++ b/arch/mips/boot/compressed/head.S @@ -0,0 +1,86 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1994, 1995 Waldorf Electronics + * Written by Ralf Baechle and Andreas Busse + * Copyright (C) 1995 - 1999 Ralf Baechle + * Copyright (C) 1996 Paul M. Antoine + * Modified for DECStation and hence R3000 support by Paul M. Antoine + * Further modifications by David S. Miller and Harald Koerfgen + * Copyright (C) 1999 Silicon Graphics, Inc. + */ +#include +#include + +#include +#include +#include +#include +#include +#include + + .set noreorder + .cprestore + LEAF(start) +start: + bal locate + nop +locate: + subu s8, ra, 8 /* Where we were loaded */ + PTR_LA sp, (.stack + 8192) + + move s0, a0 /* Save boot rom start args */ + move s1, a1 + move s2, a2 + move s3, a3 + + PTR_LA a0, start /* Where we were linked to run */ + + move a1, s8 + PTR_LA a2, _edata + subu t1, a2, a0 + srl t1, t1, 2 + + /* copy text section */ + li t0, 0 +1: lw v0, 0(a1) + nop + sw v0, 0(a0) + xor t0, t0, v0 + addu a0, 4 + bne a2, a0, 1b + addu a1, 4 + + /* Clear BSS */ + PTR_LA a0, _edata + PTR_LA a2, _end +2: sw zero, 0(a0) + bne a2, a0, 2b + addu a0, 4 + + move a0, s8 /* load address */ + move a1, t1 /* length in words */ + move a2, t0 /* checksum */ + PTR_LA a3, (.heap) /* heap address */ + + PTR_LA ra, 1f + PTR_LA k0, decompress_kernel + jr k0 + nop +1: + + move a0, s0 + move a1, s1 + move a2, s2 + move a3, s3 + li k0, KERNEL_ENTRY + jr k0 + nop +3: + b 3b + END(start) + + .comm .heap, BOOT_HEAP_SIZE, 4 + .comm .stack,4096*2,4 diff --git a/arch/mips/boot/compressed/ld.script b/arch/mips/boot/compressed/ld.script new file mode 100644 index 0000000..29e9f4c --- /dev/null +++ b/arch/mips/boot/compressed/ld.script @@ -0,0 +1,150 @@ +OUTPUT_ARCH(mips) +ENTRY(start) +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + .init : { *(.init) } =0 + .text : + { + _ftext = . ; + *(.text) + *(.rodata) + *(.rodata1) + /* .gnu.warning sections are handled specially by elf32.em. */ + *(.gnu.warning) + } =0 + .kstrtab : { *(.kstrtab) } + + . = ALIGN(16); /* Exception table */ + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + __start___dbe_table = .; /* Exception table for data bus errors */ + __dbe_table : { *(__dbe_table) } + __stop___dbe_table = .; + + __start___ksymtab = .; /* Kernel symbol table */ + __ksymtab : { *(__ksymtab) } + __stop___ksymtab = .; + + _etext = .; + + . = ALIGN(8192); + .data.init_task : { *(.data.init_task) } + + /* Startup code */ + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(16); + __setup_start = .; + .setup.init : { *(.setup.init) } + __setup_end = .; + __initcall_start = .; + .initcall.init : { *(.initcall.init) } + __initcall_end = .; + . = ALIGN(4096); /* Align double page for init_task_union */ + __init_end = .; + + . = ALIGN(4096); + .data.page_aligned : { *(.data.idt) } + + . = ALIGN(32); + .data.cacheline_aligned : { *(.data.cacheline_aligned) } + + .fini : { *(.fini) } =0 + .reginfo : { *(.reginfo) } + /* Adjust the address for the data segment. We want to adjust up to + the same address within the page on the next page up. It would + be more correct to do this: + . = .; + The current expression does not correctly handle the case of a + text segment ending precisely at the end of a page; it causes the + data segment to skip a page. The above expression does not have + this problem, but it will currently (2/95) cause BFD to allocate + a single segment, combining both text and data, for this case. + This will prevent the text segment from being shared among + multiple executions of the program; I think that is more + important than losing a page of the virtual address space (note + that no actual memory is lost; the page which is skipped can not + be referenced). */ + . = .; + .data : + { + _fdata = . ; + *(.data) + + /* Put the compressed image here, so bss is on the end. */ + __image_begin = .; + *(.image) + __image_end = .; + /* Align the initial ramdisk image (INITRD) on page boundaries. */ + . = ALIGN(4096); + __ramdisk_begin = .; + *(.initrd) + __ramdisk_end = .; + . = ALIGN(4096); + + CONSTRUCTORS + } + .data1 : { *(.data1) } + _gp = . + 0x8000; + .lit8 : { *(.lit8) } + .lit4 : { *(.lit4) } + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + .got : { *(.got.plt) *(.got) } + .dynamic : { *(.dynamic) } + /* We want the small data sections together, so single-instruction offsets + can access them all, and initialized data all before uninitialized, so + we can shorten the on-disk segment size. */ + .sdata : { *(.sdata) } + . = ALIGN(4); + _edata = .; + PROVIDE (edata = .); + + __bss_start = .; + _fbss = .; + .sbss : { *(.sbss) *(.scommon) } + .bss : + { + *(.dynbss) + *(.bss) + *(COMMON) + . = ALIGN(4); + _end = . ; + PROVIDE (end = .); + } + + /* Sections to be discarded */ + /DISCARD/ : + { + *(.text.exit) + *(.data.exit) + *(.exitcall.exit) + } + + /* This is the MIPS specific mdebug section. */ + .mdebug : { *(.mdebug) } + /* These are needed for ELF backends which have not yet been + converted to the new style linker. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + /* DWARF debug sections. + Symbols in the .debug DWARF section are relative to the beginning of the + section so we begin .debug at 0. It's not clear yet what needs to happen + for the others. */ + .debug 0 : { *(.debug) } + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_sfnames 0 : { *(.debug_sfnames) } + .line 0 : { *(.line) } + /* These must appear regardless of . */ + .gptab.sdata : { *(.gptab.data) *(.gptab.sdata) } + .gptab.sbss : { *(.gptab.bss) *(.gptab.sbss) } + .comment : { *(.comment) } + .note : { *(.note) } +} -- 1.6.2.1 From wuzhangjin@gmail.com Mon Aug 10 11:12:41 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 10 Aug 2009 11:12:48 +0200 (CEST) Received: from mail-pz0-f179.google.com ([209.85.222.179]:33234 "EHLO mail-pz0-f179.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492460AbZHJJMl (ORCPT ); Mon, 10 Aug 2009 11:12:41 +0200 Received: by pzk9 with SMTP id 9so2861218pzk.21 for ; Mon, 10 Aug 2009 02:12:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:subject:from:reply-to:to:cc :in-reply-to:references:content-type:organization:date:message-id :mime-version:x-mailer:content-transfer-encoding; bh=e9XvPoeq4RGWJp1ipOtu6w/j86h/LTqn40HKPS/7a/w=; b=LgYry5oIhpVZRjx84va1MS/Sthx05HBxxAUJnD+gbHEnC0uhGr/x3EbzP1yMgtnPJS hFIOzNKFZ1YDQFKpFUK2oSZgj4EamuxqDEOf8uEvkXzL0x5gEEYW8VbCPiLKKkokgZOI AS0N49GWMb4hvhldPwRLgDbL01Oxjf75z/Y9A= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=subject:from:reply-to:to:cc:in-reply-to:references:content-type :organization:date:message-id:mime-version:x-mailer :content-transfer-encoding; b=F9yInROhBHxZ9XbHXfnghE8x8KBbgEoTA/2+LbE4JQdylgH37s10nqiO7s2tdZqcUZ t9JDooGnjtQAJrKbW/v2HAkJSPtK4cnsRcy5rLXt0LIoBm4MjsJM7ahlINewZooImDod ptyQV0m36eErghBeb9cOPdpEAV8ZlpDfkdrPY= Received: by 10.114.254.8 with SMTP id b8mr5998040wai.106.1249895554582; Mon, 10 Aug 2009 02:12:34 -0700 (PDT) Received: from ?172.16.2.101? ([222.92.8.142]) by mx.google.com with ESMTPS id l30sm6876181waf.0.2009.08.10.02.12.30 (version=TLSv1/SSLv3 cipher=RC4-MD5); Mon, 10 Aug 2009 02:12:32 -0700 (PDT) Subject: Re: [PATCH] MIPS: add support for gzip/bzip2/lzma compressed kernel images From: Wu Zhangjin Reply-To: wuzhangjin@gmail.com To: Alexander Clouter Cc: linux-mips@linux-mips.org In-Reply-To: References: <1249757707-8876-1-git-send-email-wuzhangjin@gmail.com> Content-Type: text/plain Organization: DSLab, Lanzhou University, China Date: Mon, 10 Aug 2009 17:11:40 +0800 Message-Id: <1249895500.20588.10.camel@falcon> Mime-Version: 1.0 X-Mailer: Evolution 2.26.1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23878 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips Hi, On Sun, 2009-08-09 at 22:36 +0100, Alexander Clouter wrote: > > This has made my AR7[1] based Linksys WAG54Gv2 (16MB RAM and 4MB flash, > limited to a 768kB kernel) useful, finally...thanks! > > > I got it working (LZMA kernel) however you have hardcoded a lot of bits > in there. It looks to my uneducated eye most of the issues lie in that > getting a suitable PORT(x), KERNEL_START, KERNEL_SIZE, FREE_MEM_START > and FREE_MEM_END is non-trivial on the MIPS platform currently; > probably because of the lack of a generic lzma/gzip/bzip2 framework to > be used with. > > For me I used: > #define FREE_MEM_START CKSEG0ADDR(0x94a00000) > #define FREE_MEM_END CKSEG0ADDR(0x94f00000) > > I had to replace (you probably should move this from dbg.c to dbg.h): > #define PORT(offset) (CKSEG1ADDR(AR7_REGS_UART0) + (4 * offset)) > > The load address is awkward, but I replaced your 0x8100000 in the > Makefile with 0x94400000. > > Now, the big question is how to work this all out at compile time. :) > Thanks very much for your suggestion, just rewritten it and removed almost all of the hard-coded parts(except the size of the HEAP) and a new patch was sent out. and this new one _should_ work for the other MIPS-based machines if not missed something else. looking forward to your test result on AR7 with the new patch and welcome to comment to this new E-mail thread: [PATCH -v1] MIPS: add support for gzip/bzip2/lzma compressed kernel images > As a side note, I would personally leave the DEBUG non-optional and > turned on as it all disappears at runtime anyway, but I'm no kernel > developer :) ooh, in reality, I'm looking forward to the comment of Ralf and somebody else. to my point of view, this _debug_ interface is only need to help the developers of the other MIPS variants ensure this patch work for them. Thanks & Regards, Wu Zhangjin From ralf@linux-mips.org Mon Aug 10 15:54:44 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 10 Aug 2009 15:54:51 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:60914 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492659AbZHJNyo (ORCPT ); Mon, 10 Aug 2009 15:54:44 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id n7ADtNv8027101; Mon, 10 Aug 2009 14:55:24 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id n7ADtLm5027098; Mon, 10 Aug 2009 14:55:21 +0100 Date: Mon, 10 Aug 2009 14:55:21 +0100 From: Ralf Baechle To: Alexander Clouter Cc: linux-mips@linux-mips.org Subject: Re: [PATCH] MIPS: add support for gzip/bzip2/lzma compressed kernel images Message-ID: <20090810135521.GA27737@linux-mips.org> References: <1249757707-8876-1-git-send-email-wuzhangjin@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23879 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Sun, Aug 09, 2009 at 10:36:46PM +0100, Alexander Clouter wrote: > As a side note, I would personally leave the DEBUG non-optional and > turned on as it all disappears at runtime anyway, but I'm no kernel > developer :) Printing is hardware specific; the debug code will need to be changed for practically every MIPS platform on the planet, so I'm not too fond of the idea unless somebody comes up with a cleaner infrastructure to do so. Unfortunately we're not setup very well to do configuration detection etc. in that debug code without adding tons of baggage. Ralf From ralf@linux-mips.org Mon Aug 10 17:25:31 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 10 Aug 2009 17:25:38 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:52613 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492874AbZHJPZa (ORCPT ); Mon, 10 Aug 2009 17:25:30 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id n7AFQAEd003260; Mon, 10 Aug 2009 16:26:11 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id n7AFQA4C003258; Mon, 10 Aug 2009 16:26:10 +0100 Date: Mon, 10 Aug 2009 16:26:10 +0100 From: Ralf Baechle To: "Ithamar R. Adema" Cc: Alexander Clouter , linux-mips@linux-mips.org Subject: Re: [PATCH] MIPS: add support for gzip/bzip2/lzma compressed kernel images Message-ID: <20090810152610.GA608@linux-mips.org> References: <1249757707-8876-1-git-send-email-wuzhangjin@gmail.com> <20090810135521.GA27737@linux-mips.org> <4A803455.5010304@team-embedded.nl> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <4A803455.5010304@team-embedded.nl> User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23880 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Mon, Aug 10, 2009 at 04:53:09PM +0200, Ithamar R. Adema wrote: > Ralf Baechle wrote: >> Printing is hardware specific; the debug code will need to be changed for >> practically every MIPS platform on the planet, so I'm not too fond of the >> idea unless somebody comes up with a cleaner infrastructure to do so. >> Unfortunately we're not setup very well to do configuration detection etc. >> in that debug code without adding tons of baggage. >> > Would mimicing the uncompress.h header as used in the ARM architecture > be an idea? Maybe have one that does nothing in mach-generic and let the > machines that want debug output define their own that actually does IO. > > Just a header, defining putc()-ish functions, most architectures already > have code for that, so it should be trivial for them to implement it, if > wanted... > > Just an idea... Oh, I wasn't trying to kill the debug code entirely but pointing out some difficulties. For some platforms the code would be a little larger and more complex. It could be as bad as dynamically detecting a console and running PPP to talk to it. Or having to carry fonts along and render output into a complex graphics card. but we can still deciede if the feature is useful enough on a per platform base. An implementation would probably look something like you pointed out though I haven't seen the ARM header you mentioned. Ideally code could be shared with early printk. Ralf From David.Daney@caviumnetworks.com Mon Aug 10 20:24:50 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 10 Aug 2009 20:24:57 +0200 (CEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:2114 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1493525AbZHJSYu (ORCPT ); Mon, 10 Aug 2009 20:24:50 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,2,2,3503) id ; Mon, 10 Aug 2009 14:22:24 -0400 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Mon, 10 Aug 2009 11:21:30 -0700 Received: from dd1.caveonetworks.com ([64.169.86.201]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Mon, 10 Aug 2009 11:21:30 -0700 Message-ID: <4A806529.3060609@caviumnetworks.com> Date: Mon, 10 Aug 2009 11:21:29 -0700 From: David Daney User-Agent: Thunderbird 2.0.0.21 (X11/20090320) MIME-Version: 1.0 To: Ralf Baechle , akpm@linux-foundation.org, Linus Torvalds CC: linux-mips , Linux Kernel Mailing List Subject: [PATCH 0/2] New hardware RNG for Octeon SOCs. Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 10 Aug 2009 18:21:30.0174 (UTC) FILETIME=[61C23DE0:01CA19E7] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23881 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Behold the Random Number Generator driver for Octeon! The first patch adds some port definitions and the octeon_rng platform device. The second is the driver. I am copying AKPM and Linus as there seems to be no hw_random maintainer. Since Octeon is a mips port, we might want to merge both patches via Ralf's tree. Comments? David Daney (2): MIPS: Octeon: Add hardware RNG platform device. hw_random: Add hardware RNG for Octeon SOCs. arch/mips/cavium-octeon/setup.c | 44 ++++++++ arch/mips/include/asm/octeon/cvmx-rnm-defs.h | 86 +++++++++++++++ drivers/char/hw_random/Kconfig | 13 +++ drivers/char/hw_random/Makefile | 1 + drivers/char/hw_random/octeon-rng.c | 146 ++++++++++++++++++++++++++ 5 files changed, 290 insertions(+), 0 deletions(-) create mode 100644 arch/mips/include/asm/octeon/cvmx-rnm-defs.h create mode 100644 drivers/char/hw_random/octeon-rng.c From David.Daney@caviumnetworks.com Mon Aug 10 20:38:19 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 10 Aug 2009 20:38:26 +0200 (CEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:11003 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1493380AbZHJSiT (ORCPT ); Mon, 10 Aug 2009 20:38:19 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,2,2,3503) id ; Mon, 10 Aug 2009 14:37:30 -0400 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Mon, 10 Aug 2009 11:30:29 -0700 Received: from dd1.caveonetworks.com ([64.169.86.201]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Mon, 10 Aug 2009 11:30:29 -0700 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.2/8.14.2) with ESMTP id n7AIUQhd029653; Mon, 10 Aug 2009 11:30:26 -0700 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.2/8.14.2/Submit) id n7AIUQA8029652; Mon, 10 Aug 2009 11:30:26 -0700 From: David Daney To: ralf@linux-mips.org, torvalds@linux-foundation.org, akpm@linux-foundation.org Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, David Daney Subject: [PATCH 2/2] hw_random: Add hardware RNG for Octeon SOCs. Date: Mon, 10 Aug 2009 11:30:25 -0700 Message-Id: <1249929025-29625-2-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.6.0.6 In-Reply-To: <4A806529.3060609@caviumnetworks.com> References: <4A806529.3060609@caviumnetworks.com> X-OriginalArrivalTime: 10 Aug 2009 18:30:29.0209 (UTC) FILETIME=[A30C7490:01CA19E8] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23882 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Signed-off-by: David Daney --- drivers/char/hw_random/Kconfig | 13 +++ drivers/char/hw_random/Makefile | 1 + drivers/char/hw_random/octeon-rng.c | 146 +++++++++++++++++++++++++++++++++++ 3 files changed, 160 insertions(+), 0 deletions(-) create mode 100644 drivers/char/hw_random/octeon-rng.c diff --git a/drivers/char/hw_random/Kconfig b/drivers/char/hw_random/Kconfig index ce66a70..121b782 100644 --- a/drivers/char/hw_random/Kconfig +++ b/drivers/char/hw_random/Kconfig @@ -126,6 +126,19 @@ config HW_RANDOM_OMAP If unsure, say Y. +config HW_RANDOM_OCTEON + tristate "Octeon Random Number Generator support" + depends on HW_RANDOM && CPU_CAVIUM_OCTEON + default HW_RANDOM + ---help--- + This driver provides kernel-side support for the Random Number + Generator hardware found on Octeon processors. + + To compile this driver as a module, choose M here: the + module will be called octeon-rng. + + If unsure, say Y. + config HW_RANDOM_PASEMI tristate "PA Semi HW Random Number Generator support" depends on HW_RANDOM && PPC_PASEMI diff --git a/drivers/char/hw_random/Makefile b/drivers/char/hw_random/Makefile index 676828b..5eeb130 100644 --- a/drivers/char/hw_random/Makefile +++ b/drivers/char/hw_random/Makefile @@ -17,3 +17,4 @@ obj-$(CONFIG_HW_RANDOM_PASEMI) += pasemi-rng.o obj-$(CONFIG_HW_RANDOM_VIRTIO) += virtio-rng.o obj-$(CONFIG_HW_RANDOM_TX4939) += tx4939-rng.o obj-$(CONFIG_HW_RANDOM_MXC_RNGA) += mxc-rnga.o +obj-$(CONFIG_HW_RANDOM_OCTEON) += octeon-rng.o diff --git a/drivers/char/hw_random/octeon-rng.c b/drivers/char/hw_random/octeon-rng.c new file mode 100644 index 0000000..84d33a7 --- /dev/null +++ b/drivers/char/hw_random/octeon-rng.c @@ -0,0 +1,146 @@ +/* + * Hardware Random Number Generator support for Cavium Networks + * Octeon processor family. + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2009 Cavium Networks + */ + +#include +#include +#include +#include +#include +#include + +#include +#include + +struct octeon_rng { + u64 control_status; + u64 result; +}; + +static int octeon_rng_init(struct hwrng *rng) +{ + struct octeon_rng *p = (struct octeon_rng *)rng->priv; + union cvmx_rnm_ctl_status ctl; + + ctl.u64 = 0; + ctl.s.ent_en = 1; /* Enable the entropy source. */ + ctl.s.rng_en = 1; /* Enable the RNG hardware. */ + cvmx_write_csr(p->control_status, ctl.u64); + return 0; +} + +static void octeon_rng_cleanup(struct hwrng *rng) +{ + struct octeon_rng *p = (struct octeon_rng *)rng->priv; + union cvmx_rnm_ctl_status ctl; + + ctl.u64 = 0; + /* Disable everything. */ + cvmx_write_csr(p->control_status, ctl.u64); +} + +static int octeon_rng_data_read(struct hwrng *rng, u32 *data) +{ + struct octeon_rng *p = (struct octeon_rng *)rng->priv; + + *data = cvmx_read64_uint32(p->result); + return sizeof(u32); +} + +static struct hwrng octeon_rng_ops = { + .name = "octeon", + .init = octeon_rng_init, + .cleanup = octeon_rng_cleanup, + .data_read = octeon_rng_data_read +}; + +static int __devinit octeon_rng_probe(struct platform_device *pdev) +{ + struct resource *res_ports; + struct resource *res_result; + struct octeon_rng *p; + int ret; + + p = devm_kzalloc(&pdev->dev, sizeof(*p), GFP_KERNEL); + if (!p) + return -ENOMEM; + + res_ports = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res_ports) + goto err_ports; + + res_result = platform_get_resource(pdev, IORESOURCE_MEM, 1); + if (!res_result) + goto err_ports; + + + p->control_status = (u64)devm_ioremap_nocache(&pdev->dev, + res_ports->start, + sizeof(u64)); + if (!p->control_status) + goto err_ports; + + p->result = (u64)devm_ioremap_nocache(&pdev->dev, + res_result->start, + sizeof(u64)); + if (!p->result) + goto err_r; + octeon_rng_ops.priv = (unsigned long)p; + + dev_set_drvdata(&pdev->dev, &octeon_rng_ops); + ret = hwrng_register(&octeon_rng_ops); + if (ret) + goto err; + + dev_info(&pdev->dev, "Octeon Random Number Generator\n"); + + return 0; +err: + devm_iounmap(&pdev->dev, (void *)p->control_status); +err_r: + devm_iounmap(&pdev->dev, (void *)p->result); +err_ports: + devm_kfree(&pdev->dev, p); + return -ENOENT; +} + +static int __exit octeon_rng_remove(struct platform_device *pdev) +{ + struct hwrng *rng = dev_get_drvdata(&pdev->dev); + + hwrng_unregister(rng); + + return 0; +} + +static struct platform_driver octeon_rng_driver = { + .driver = { + .name = "octeon_rng", + .owner = THIS_MODULE, + }, + .probe = octeon_rng_probe, + .remove = __exit_p(octeon_rng_remove), +}; + +static int __init octeon_rng_mod_init(void) +{ + return platform_driver_register(&octeon_rng_driver); +} + +static void __exit octeon_rng_mod_exit(void) +{ + platform_driver_unregister(&octeon_rng_driver); +} + +module_init(octeon_rng_mod_init); +module_exit(octeon_rng_mod_exit); + +MODULE_AUTHOR("David Daney"); +MODULE_LICENSE("GPL"); -- 1.6.0.6 From David.Daney@caviumnetworks.com Mon Aug 10 20:38:43 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 10 Aug 2009 20:38:50 +0200 (CEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:11032 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1493520AbZHJSiW (ORCPT ); Mon, 10 Aug 2009 20:38:22 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,2,2,3503) id ; Mon, 10 Aug 2009 14:37:30 -0400 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Mon, 10 Aug 2009 11:30:29 -0700 Received: from dd1.caveonetworks.com ([64.169.86.201]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Mon, 10 Aug 2009 11:30:29 -0700 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.2/8.14.2) with ESMTP id n7AIUQql029649; Mon, 10 Aug 2009 11:30:26 -0700 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.2/8.14.2/Submit) id n7AIUPTR029648; Mon, 10 Aug 2009 11:30:25 -0700 From: David Daney To: ralf@linux-mips.org, torvalds@linux-foundation.org, akpm@linux-foundation.org Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, David Daney Subject: [PATCH 1/2] MIPS: Octeon: Add hardware RNG platform device. Date: Mon, 10 Aug 2009 11:30:24 -0700 Message-Id: <1249929025-29625-1-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.6.0.6 In-Reply-To: <4A806529.3060609@caviumnetworks.com> References: <4A806529.3060609@caviumnetworks.com> X-OriginalArrivalTime: 10 Aug 2009 18:30:29.0225 (UTC) FILETIME=[A30EE590:01CA19E8] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23883 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Add a platform device for the Octeon Random Number Generator (RNG). Signed-off-by: David Daney --- arch/mips/cavium-octeon/setup.c | 44 +++++++++++++ arch/mips/include/asm/octeon/cvmx-rnm-defs.h | 86 ++++++++++++++++++++++++++ 2 files changed, 130 insertions(+), 0 deletions(-) create mode 100644 arch/mips/include/asm/octeon/cvmx-rnm-defs.h diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c index bc0c869..c67487a 100644 --- a/arch/mips/cavium-octeon/setup.c +++ b/arch/mips/cavium-octeon/setup.c @@ -33,6 +33,7 @@ #include #include +#include #ifdef CONFIG_CAVIUM_DECODE_RSL extern void cvmx_interrupt_rsl_decode(void); @@ -931,3 +932,46 @@ out: return ret; } device_initcall(octeon_cf_device_init); + +/* Octeon Random Number Generator. */ +static int __init octeon_rng_device_init(void) +{ + struct platform_device *pd; + struct resource rng_resources[2]; + unsigned int res_count; + int ret = 0; + + memset(rng_resources, 0, sizeof(rng_resources)); + res_count = 0; + rng_resources[res_count].flags = IORESOURCE_MEM; + rng_resources[res_count].start = XKPHYS_TO_PHYS(CVMX_RNM_CTL_STATUS); + rng_resources[res_count].end = rng_resources[res_count].start + 0xf; + res_count++; + + rng_resources[res_count].flags = IORESOURCE_MEM; + rng_resources[res_count].start = cvmx_build_io_address(8, 0); + rng_resources[res_count].end = rng_resources[res_count].start + 0x7; + res_count++; + + pd = platform_device_alloc("octeon_rng", -1); + if (!pd) { + ret = -ENOMEM; + goto out; + } + + ret = platform_device_add_resources(pd, rng_resources, res_count); + if (ret) + goto fail; + + ret = platform_device_add(pd); + if (ret) + goto fail; + + return ret; +fail: + platform_device_put(pd); + +out: + return ret; +} +device_initcall(octeon_rng_device_init); diff --git a/arch/mips/include/asm/octeon/cvmx-rnm-defs.h b/arch/mips/include/asm/octeon/cvmx-rnm-defs.h new file mode 100644 index 0000000..a25e2bc --- /dev/null +++ b/arch/mips/include/asm/octeon/cvmx-rnm-defs.h @@ -0,0 +1,86 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * along with this file; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +#ifndef __CVMX_RNM_DEFS_H__ +#define __CVMX_RNM_DEFS_H__ + +#define CVMX_RNM_BIST_STATUS \ + CVMX_ADD_IO_SEG(0x0001180040000008ull) +#define CVMX_RNM_CTL_STATUS \ + CVMX_ADD_IO_SEG(0x0001180040000000ull) + +union cvmx_rnm_bist_status { + uint64_t u64; + struct cvmx_rnm_bist_status_s { + uint64_t reserved_2_63:62; + uint64_t rrc:1; + uint64_t mem:1; + } s; + struct cvmx_rnm_bist_status_s cn30xx; + struct cvmx_rnm_bist_status_s cn31xx; + struct cvmx_rnm_bist_status_s cn38xx; + struct cvmx_rnm_bist_status_s cn38xxp2; + struct cvmx_rnm_bist_status_s cn50xx; + struct cvmx_rnm_bist_status_s cn52xx; + struct cvmx_rnm_bist_status_s cn52xxp1; + struct cvmx_rnm_bist_status_s cn56xx; + struct cvmx_rnm_bist_status_s cn56xxp1; + struct cvmx_rnm_bist_status_s cn58xx; + struct cvmx_rnm_bist_status_s cn58xxp1; +}; + +union cvmx_rnm_ctl_status { + uint64_t u64; + struct cvmx_rnm_ctl_status_s { + uint64_t reserved_9_63:55; + uint64_t ent_sel:4; + uint64_t exp_ent:1; + uint64_t rng_rst:1; + uint64_t rnm_rst:1; + uint64_t rng_en:1; + uint64_t ent_en:1; + } s; + struct cvmx_rnm_ctl_status_cn30xx { + uint64_t reserved_4_63:60; + uint64_t rng_rst:1; + uint64_t rnm_rst:1; + uint64_t rng_en:1; + uint64_t ent_en:1; + } cn30xx; + struct cvmx_rnm_ctl_status_cn30xx cn31xx; + struct cvmx_rnm_ctl_status_cn30xx cn38xx; + struct cvmx_rnm_ctl_status_cn30xx cn38xxp2; + struct cvmx_rnm_ctl_status_s cn50xx; + struct cvmx_rnm_ctl_status_s cn52xx; + struct cvmx_rnm_ctl_status_s cn52xxp1; + struct cvmx_rnm_ctl_status_s cn56xx; + struct cvmx_rnm_ctl_status_s cn56xxp1; + struct cvmx_rnm_ctl_status_s cn58xx; + struct cvmx_rnm_ctl_status_s cn58xxp1; +}; + +#endif -- 1.6.0.6 From f.fainelli@gmail.com Mon Aug 10 21:43:05 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 10 Aug 2009 21:43:11 +0200 (CEST) Received: from mail-ew0-f216.google.com ([209.85.219.216]:43230 "EHLO mail-ew0-f216.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1493404AbZHJTnF (ORCPT ); Mon, 10 Aug 2009 21:43:05 +0200 Received: by ewy12 with SMTP id 12so3914001ewy.0 for ; Mon, 10 Aug 2009 12:43:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:sender:from:date:subject :mime-version:x-uid:x-length:to:cc:content-type :content-transfer-encoding:content-disposition:message-id; bh=cw3xRnjTmFmgNUYqydMzXzY1c+waWOJI+0an7fNi2fM=; b=M6rzJGlIY6pUcxY5vGUBxnBhjZZHyvXgtMDOLYBPXb4/nBa3yduufPDUDzlXPiu0ml RRpEQEap7G7DKPn7dlj9+1afVE/IiDpwPCIT3jDhPcQyvjXxE//C6scggt8vhVwd0lk4 zooBZRicLMOimbV/KdxEoH34f6fPTGMNJNwkk= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:from:date:subject:mime-version:x-uid:x-length:to:cc :content-type:content-transfer-encoding:content-disposition :message-id; b=QmosTIUgr+1JrwpJh9Y6u1IhIW3Z2VTpMo3Frp3rCLLa94trYN4Leg2ry8xc8Reeeb AIreAulOyq2qESio7dXWXSruWToJEjE8kivgyNbMqn5w2kSgRSf7dAiuCs7hOlKbAoVP pdL35noCVQ5NvzIFVlIgcLvkj0Exa6PuwVIw0= Received: by 10.210.86.1 with SMTP id j1mr5417239ebb.27.1249933380035; Mon, 10 Aug 2009 12:43:00 -0700 (PDT) Received: from lenovo.mimichou.home (florian.mimichou.net [82.241.112.26]) by mx.google.com with ESMTPS id 28sm199482eye.54.2009.08.10.12.42.58 (version=TLSv1/SSLv3 cipher=RC4-MD5); Mon, 10 Aug 2009 12:42:58 -0700 (PDT) From: Florian Fainelli Date: Mon, 10 Aug 2009 21:42:54 +0200 Subject: [PATCH 1/2] bcm63xx: make bcm63xx_uart_register an initfunc MIME-Version: 1.0 X-UID: 1206 X-Length: 2926 To: Ralf Baechle Cc: linux-mips@linux-mips.org, Maxime Bizon Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Content-Disposition: inline Message-Id: <200908102142.56610.florian@openwrt.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23884 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips This patch removes the calls to bcm63xx_uart_register in board_bcm963xx.c and make bcm63xx_uart_register an initfunc. Allows us to remove bcm63xx_dev_uart.h which was there to make checkpatch.pl happy. Tested on my Tecom GW6x00. Signed-off-by: Florian Fainelli --- diff --git a/arch/mips/bcm63xx/boards/board_bcm963xx.c b/arch/mips/bcm63xx/boards/board_bcm963xx.c index 17a8636..1d56ef6 100644 --- a/arch/mips/bcm63xx/boards/board_bcm963xx.c +++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c @@ -22,7 +22,6 @@ #include #include #include -#include #include #include #include @@ -797,8 +796,6 @@ int __init board_register_devices(void) { u32 val; - bcm63xx_uart_register(); - if (board.has_pccard) bcm63xx_pcmcia_register(); diff --git a/arch/mips/bcm63xx/dev-uart.c b/arch/mips/bcm63xx/dev-uart.c index 5f3d89c..b051946 100644 --- a/arch/mips/bcm63xx/dev-uart.c +++ b/arch/mips/bcm63xx/dev-uart.c @@ -10,7 +10,6 @@ #include #include #include -#include static struct resource uart_resources[] = { { @@ -39,3 +38,4 @@ int __init bcm63xx_uart_register(void) uart_resources[1].start = bcm63xx_get_irq_number(IRQ_UART0); return platform_device_register(&bcm63xx_uart_device); } +arch_initcall(bcm63xx_uart_register); diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_uart.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_uart.h deleted file mode 100644 index bf348f5..0000000 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_uart.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef BCM63XX_DEV_UART_H_ -#define BCM63XX_DEV_UART_H_ - -int bcm63xx_uart_register(void); - -#endif /* BCM63XX_DEV_UART_H_ */ From f.fainelli@gmail.com Mon Aug 10 21:43:28 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 10 Aug 2009 21:43:37 +0200 (CEST) Received: from mail-ew0-f216.google.com ([209.85.219.216]:35323 "EHLO mail-ew0-f216.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1493419AbZHJTnK (ORCPT ); Mon, 10 Aug 2009 21:43:10 +0200 Received: by ewy12 with SMTP id 12so3914060ewy.0 for ; Mon, 10 Aug 2009 12:43:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:sender:from:date:subject :mime-version:x-uid:x-length:to:cc:content-type :content-transfer-encoding:content-disposition:message-id; bh=oF1JAQpfebkPA64dkIQLJv08KEWCf5X9c8/bQKnm5cU=; b=WZmjFdHI0b73CeWTXRDezCnkqGw/nkWxHGjrIOn0ZtyzBaiAD6tGVYQArrCpCuhqqh 8gqigAULY1JNgy/bAIwTNSb/tnzypwljWk3cbZQbGt+oDiISa4l7A8zl18edVtGi1ks3 dP9mBgrMlbOXeFtu3BP8Qz1b/4soN6uSK2I3Y= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:from:date:subject:mime-version:x-uid:x-length:to:cc :content-type:content-transfer-encoding:content-disposition :message-id; b=Aua4sWE4koTInpiaGF5S57nt9wl8bH+KukrBP1SEyIDP3dGER4lbG7Mo/sPBdJ9SrN 36ueATLAEn9XPtY/RMcRdVQAqO8gOyE2KGp8owBidnhAEOUJI0nMkRsfJjZ5wgjRqZrl bXaBAm6LDi/QvOaxqUw1M+861IvrK8gl9RcjU= Received: by 10.210.87.11 with SMTP id k11mr2873605ebb.68.1249933384670; Mon, 10 Aug 2009 12:43:04 -0700 (PDT) Received: from lenovo.mimichou.home (florian.mimichou.net [82.241.112.26]) by mx.google.com with ESMTPS id 7sm163185eyg.5.2009.08.10.12.43.02 (version=TLSv1/SSLv3 cipher=RC4-MD5); Mon, 10 Aug 2009 12:43:03 -0700 (PDT) From: Florian Fainelli Date: Mon, 10 Aug 2009 21:42:59 +0200 Subject: [PATCH 2/2] bcm63xx: prepare for watchdog support MIME-Version: 1.0 X-UID: 1207 X-Length: 2676 To: Ralf Baechle Cc: linux-mips@linux-mips.org, Maxime Bizon Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Content-Disposition: inline Message-Id: <200908102143.01124.florian@openwrt.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23885 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips This patch prepares the board code to register a bcm63xx_wdt platform_device that we are going to use in a subsequent patch. Signed-off-by: Florian Fainelli --- diff --git a/arch/mips/bcm63xx/Makefile b/arch/mips/bcm63xx/Makefile index 70ba038..a4abc11 100644 --- a/arch/mips/bcm63xx/Makefile +++ b/arch/mips/bcm63xx/Makefile @@ -5,6 +5,7 @@ obj-y += dev-usb-ohci.o obj-y += dev-usb-ehci.o obj-y += dev-enet.o obj-y += dev-dsp.o +obj-y += dev-wdt.o obj-$(CONFIG_EARLY_PRINTK) += early_printk.o obj-y += boards/ diff --git a/arch/mips/bcm63xx/dev-wdt.c b/arch/mips/bcm63xx/dev-wdt.c new file mode 100644 index 0000000..045bae0 --- /dev/null +++ b/arch/mips/bcm63xx/dev-wdt.c @@ -0,0 +1,37 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2008 Florian Fainelli + */ + +#include +#include +#include +#include + +static struct resource wdt_resources[] = { + { + .start = -1, /* filled at runtime */ + .end = -1, /* filled at runtime */ + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device bcm63xx_wdt_device = { + .name = "bcm63xx-wdt", + .id = 0, + .num_resources = ARRAY_SIZE(wdt_resources), + .resource = wdt_resources, +}; + +int __init bcm63xx_wdt_register(void) +{ + wdt_resources[0].start = bcm63xx_regset_address(RSET_WDT); + wdt_resources[0].end = wdt_resources[0].start; + wdt_resources[0].end += RSET_WDT_SIZE - 1; + + return platform_device_register(&bcm63xx_wdt_device); +} +arch_initcall(bcm63xx_wdt_register); From f.fainelli@gmail.com Mon Aug 10 21:47:16 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 10 Aug 2009 21:47:22 +0200 (CEST) Received: from mail-ew0-f216.google.com ([209.85.219.216]:36374 "EHLO mail-ew0-f216.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1493527AbZHJTrQ convert rfc822-to-8bit (ORCPT ); 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Mon, 10 Aug 2009 12:47:10 -0700 (PDT) Received: from lenovo.mimichou.home (florian.mimichou.net [82.241.112.26]) by mx.google.com with ESMTPS id 28sm213998eye.54.2009.08.10.12.47.07 (version=TLSv1/SSLv3 cipher=RC4-MD5); Mon, 10 Aug 2009 12:47:08 -0700 (PDT) From: Florian Fainelli To: Ralf Baechle Subject: Re: [PATCH 8/8] bcm63xx: prepare for on-board watchdog support Date: Mon, 10 Aug 2009 21:47:05 +0200 User-Agent: KMail/1.9.9 Cc: linux-mips@linux-mips.org, Maxime Bizon References: <200908072347.16203.florian@openwrt.org> <20090808194033.GD22761@linux-mips.org> In-Reply-To: <20090808194033.GD22761@linux-mips.org> MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 8BIT Content-Disposition: inline Message-Id: <200908102147.06692.florian@openwrt.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23886 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips Le Saturday 08 August 2009 21:40:33 Ralf Baechle, vous avez écrit : > On Fri, Aug 07, 2009 at 11:47:15PM +0200, Florian Fainelli wrote: > > This patch registers the watchdog platform_device that > > we are going to use in the watchdog platform_driver in > > a subsequent patch. > > > > Signed-off-by: Florian Fainelli > > --- > > diff --git a/arch/mips/bcm63xx/Makefile b/arch/mips/bcm63xx/Makefile > > index 70ba038..a4abc11 100644 > > --- a/arch/mips/bcm63xx/Makefile > > +++ b/arch/mips/bcm63xx/Makefile > > @@ -5,6 +5,7 @@ obj-y += dev-usb-ohci.o > > obj-y += dev-usb-ehci.o > > obj-y += dev-enet.o > > obj-y += dev-dsp.o > > +obj-y += dev-wdt.o > > obj-$(CONFIG_EARLY_PRINTK) += early_printk.o > > > > obj-y += boards/ > > diff --git a/arch/mips/bcm63xx/boards/board_bcm963xx.c > > b/arch/mips/bcm63xx/boards/board_bcm963xx.c index 17a8636..e6a7b4f 100644 > > --- a/arch/mips/bcm63xx/boards/board_bcm963xx.c > > +++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c > > @@ -28,6 +28,7 @@ > > #include > > #include > > #include > > +#include > > #include > > > > #define PFX "board_bcm963xx: " > > @@ -798,6 +799,7 @@ int __init board_register_devices(void) > > u32 val; > > > > bcm63xx_uart_register(); > > + bcm63xx_wdt_register(); > > > > if (board.has_pccard) > > bcm63xx_pcmcia_register(); > > diff --git a/arch/mips/bcm63xx/dev-wdt.c b/arch/mips/bcm63xx/dev-wdt.c > > new file mode 100644 > > index 0000000..6e18489 > > --- /dev/null > > +++ b/arch/mips/bcm63xx/dev-wdt.c > > @@ -0,0 +1,36 @@ > > +/* > > + * This file is subject to the terms and conditions of the GNU General > > Public + * License. See the file "COPYING" in the main directory of this > > archive + * for more details. > > + * > > + * Copyright (C) 2008 Florian Fainelli > > + */ > > + > > +#include > > +#include > > +#include > > +#include > > + > > +static struct resource wdt_resources[] = { > > + { > > + .start = -1, /* filled at runtime */ > > + .end = -1, /* filled at runtime */ > > + .flags = IORESOURCE_MEM, > > + }, > > +}; > > + > > +static struct platform_device bcm63xx_wdt_device = { > > + .name = "bcm63xx-wdt", > > + .id = 0, > > + .num_resources = ARRAY_SIZE(wdt_resources), > > + .resource = wdt_resources, > > +}; > > + > > +int __init bcm63xx_wdt_register(void) > > +{ > > + wdt_resources[0].start = bcm63xx_regset_address(RSET_WDT); > > + wdt_resources[0].end = wdt_resources[0].start; > > + wdt_resources[0].end += RSET_WDT_SIZE - 1; > > + > > + return platform_device_register(&bcm63xx_wdt_device); > > +} > > diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_wdt.h > > b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_wdt.h new file mode > > 100644 > > index 0000000..4aae2c7 > > --- /dev/null > > +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_wdt.h > > @@ -0,0 +1,6 @@ > > +#ifndef BCM63XX_DEV_WDT_H_ > > +#define BCM63XX_DEV_WDT_H_ > > + > > +int bcm63xx_wdt_register(void); > > + > > +#endif /* BCM63XX_DEV_WDT_H_ */ > > bcm63xx_dev_wdt.h only really exists to keep checpatch.pl happy - not a > terribly good reason. I suggest to remove the explicit call to > bcm63xx_wdt_register, make the function static and use some initfunc magic > to call it and bcm63xx_dev_wdt.h can go. Thanks for your comment, I just sent two follow-up patches against patch 7/8 which addresses that for the uart and watchdog registration. -- Best regards, Florian Fainelli Email: florian@openwrt.org Web: http://openwrt.org IRC: [florian] on irc.freenode.net ------------------------------- From mpm@selenic.com Mon Aug 10 21:55:50 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 10 Aug 2009 21:55:58 +0200 (CEST) Received: from waste.org ([173.11.57.241]:57446 "EHLO waste.org" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1493533AbZHJTzu (ORCPT ); Mon, 10 Aug 2009 21:55:50 +0200 Received: from [192.168.1.100] ([10.0.0.100]) (authenticated bits=0) by waste.org (8.13.8/8.13.8/Debian-3) with ESMTP id n7AJt5iP000363 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NOT); Mon, 10 Aug 2009 14:55:05 -0500 Subject: Re: [PATCH 0/2] New hardware RNG for Octeon SOCs. From: Matt Mackall To: David Daney Cc: Ralf Baechle , akpm@linux-foundation.org, Linus Torvalds , linux-mips , Linux Kernel Mailing List , Herbert Xu In-Reply-To: <4A806529.3060609@caviumnetworks.com> References: <4A806529.3060609@caviumnetworks.com> Content-Type: text/plain Date: Mon, 10 Aug 2009 14:54:54 -0500 Message-Id: <1249934094.3807.32.camel@calx> Mime-Version: 1.0 X-Mailer: Evolution 2.26.3 Content-Transfer-Encoding: 7bit X-Virus-Scanned: by amavisd-new Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23887 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mpm@selenic.com Precedence: bulk X-list: linux-mips On Mon, 2009-08-10 at 11:21 -0700, David Daney wrote: > Behold the Random Number Generator driver for Octeon! > > The first patch adds some port definitions and the octeon_rng platform > device. The second is the driver. > > I am copying AKPM and Linus as there seems to be no hw_random maintainer. These now go through Herbert Xu and I. -- http://selenic.com : development and support for Mercurial and Linux From David.Daney@caviumnetworks.com Mon Aug 10 21:57:37 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 10 Aug 2009 21:57:44 +0200 (CEST) Received: from smtp2.caviumnetworks.com ([209.113.159.134]:14900 "EHLO smtp2.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1493430AbZHJT5h (ORCPT ); Mon, 10 Aug 2009 21:57:37 +0200 Received: from maexch1.caveonetworks.com (Not Verified[192.168.14.20]) by smtp2.caviumnetworks.com with MailMarshal (v6,5,4,7535) id ; Mon, 10 Aug 2009 15:57:02 -0400 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by maexch1.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Mon, 10 Aug 2009 15:57:35 -0400 Received: from dd1.caveonetworks.com ([64.169.86.201]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Mon, 10 Aug 2009 12:57:33 -0700 Message-ID: <4A807BAD.5010708@caviumnetworks.com> Date: Mon, 10 Aug 2009 12:57:33 -0700 From: David Daney User-Agent: Thunderbird 2.0.0.21 (X11/20090320) MIME-Version: 1.0 To: Matt Mackall CC: Ralf Baechle , akpm@linux-foundation.org, Linus Torvalds , linux-mips , Linux Kernel Mailing List , Herbert Xu Subject: Re: [PATCH 0/2] New hardware RNG for Octeon SOCs. References: <4A806529.3060609@caviumnetworks.com> <1249934094.3807.32.camel@calx> In-Reply-To: <1249934094.3807.32.camel@calx> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 10 Aug 2009 19:57:33.0928 (UTC) FILETIME=[CD394E80:01CA19F4] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23888 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Matt Mackall wrote: > On Mon, 2009-08-10 at 11:21 -0700, David Daney wrote: >> Behold the Random Number Generator driver for Octeon! >> >> The first patch adds some port definitions and the octeon_rng platform >> device. The second is the driver. >> >> I am copying AKPM and Linus as there seems to be no hw_random maintainer. > > These now go through Herbert Xu and I. I had been advised of this after I sent the messages. Perhaps an entry in MAINTAINERS is in order. David Daney From joe@perches.com Mon Aug 10 22:18:56 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 10 Aug 2009 22:19:03 +0200 (CEST) Received: from 136-022.dsl.LABridge.com ([206.117.136.22]:2825 "EHLO mail.perches.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1493526AbZHJUS4 (ORCPT ); Mon, 10 Aug 2009 22:18:56 +0200 Received: from [192.168.1.158] (Joe-Laptop.home [192.168.1.158]) by mail.perches.com (8.9.3/8.9.3) with ESMTP id NAA06659; Mon, 10 Aug 2009 13:18:16 -0700 Subject: [PATCH] MAINTAINERS: Add Matt Mackall and Herbert Xu to HARDWARE RANDOM NUMBER GENERATOR From: Joe Perches To: Matt Mackall Cc: David Daney , Ralf Baechle , akpm@linux-foundation.org, Linus Torvalds , linux-mips , Linux Kernel Mailing List , Herbert Xu In-Reply-To: <1249934094.3807.32.camel@calx> References: <4A806529.3060609@caviumnetworks.com> <1249934094.3807.32.camel@calx> Content-Type: text/plain Date: Mon, 10 Aug 2009 13:18:29 -0700 Message-Id: <1249935509.8895.63.camel@Joe-Laptop.home> Mime-Version: 1.0 X-Mailer: Evolution 2.26.1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23889 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: joe@perches.com Precedence: bulk X-list: linux-mips On Mon, 2009-08-10 at 14:54 -0500, Matt Mackall wrote: > On Mon, 2009-08-10 at 11:21 -0700, David Daney wrote: > > I am copying AKPM and Linus as there seems to be no hw_random maintainer. > These now go through Herbert Xu and I. Perhaps this then: Signed-off-by: Joe Perches diff --git a/MAINTAINERS b/MAINTAINERS index b1114cf..9a27822 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2260,7 +2260,9 @@ S: Orphan F: drivers/hwmon/ HARDWARE RANDOM NUMBER GENERATOR CORE -S: Orphan +M: Matt Mackall +M: Herbert Xu +S: Odd fixes F: Documentation/hw_random.txt F: drivers/char/hw_random/ F: include/linux/hw_random.h From akpm@linux-foundation.org Tue Aug 11 00:35:42 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 11 Aug 2009 00:35:48 +0200 (CEST) Received: from smtp1.linux-foundation.org ([140.211.169.13]:51136 "EHLO smtp1.linux-foundation.org" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1493553AbZHJWfl (ORCPT ); Tue, 11 Aug 2009 00:35:41 +0200 Received: from imap1.linux-foundation.org (imap1.linux-foundation.org [140.211.169.55]) by smtp1.linux-foundation.org (8.14.2/8.13.5/Debian-3ubuntu1.1) with ESMTP id n7AMZ3xj024297 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Mon, 10 Aug 2009 15:35:04 -0700 Received: from akpm.mtv.corp.google.com (localhost [127.0.0.1]) by imap1.linux-foundation.org (8.13.5.20060308/8.13.5/Debian-3ubuntu1.1) with SMTP id n7AMZ39r024547; Mon, 10 Aug 2009 15:35:03 -0700 Date: Mon, 10 Aug 2009 15:35:03 -0700 From: Andrew Morton To: David Daney Cc: ralf@linux-mips.org, torvalds@linux-foundation.org, linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, ddaney@caviumnetworks.com Subject: Re: [PATCH 1/2] MIPS: Octeon: Add hardware RNG platform device. Message-Id: <20090810153503.07dee9c4.akpm@linux-foundation.org> In-Reply-To: <1249929025-29625-1-git-send-email-ddaney@caviumnetworks.com> References: <4A806529.3060609@caviumnetworks.com> <1249929025-29625-1-git-send-email-ddaney@caviumnetworks.com> X-Mailer: Sylpheed version 2.2.4 (GTK+ 2.8.20; i486-pc-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-MIMEDefang-Filter: lf$Revision: 1.188 $ X-Scanned-By: MIMEDefang 2.63 on 140.211.169.13 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23890 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: akpm@linux-foundation.org Precedence: bulk X-list: linux-mips On Mon, 10 Aug 2009 11:30:24 -0700 David Daney wrote: > Add a platform device for the Octeon Random Number Generator (RNG). > > ... > > device_initcall(octeon_cf_device_init); > + > +/* Octeon Random Number Generator. */ > +static int __init octeon_rng_device_init(void) > +{ > + struct platform_device *pd; > + struct resource rng_resources[2]; > + unsigned int res_count; > + int ret = 0; > + > + memset(rng_resources, 0, sizeof(rng_resources)); > + res_count = 0; > + rng_resources[res_count].flags = IORESOURCE_MEM; > + rng_resources[res_count].start = XKPHYS_TO_PHYS(CVMX_RNM_CTL_STATUS); > + rng_resources[res_count].end = rng_resources[res_count].start + 0xf; > + res_count++; > + > + rng_resources[res_count].flags = IORESOURCE_MEM; > + rng_resources[res_count].start = cvmx_build_io_address(8, 0); > + rng_resources[res_count].end = rng_resources[res_count].start + 0x7; > + res_count++; You could do strut resource rng_resources[2] = { { .flags = IORESOURCE_MEM, .start = XKPHYS_TO_PHYS(CVMX_RNM_CTL_STATUS), {etc} here. > + pd = platform_device_alloc("octeon_rng", -1); > + if (!pd) { > + ret = -ENOMEM; > + goto out; > + } > + > + ret = platform_device_add_resources(pd, rng_resources, res_count); use ARRAY_SIZE() here. > + if (ret) > + goto fail; > + > + ret = platform_device_add(pd); > + if (ret) > + goto fail; > + > + return ret; > +fail: > + platform_device_put(pd); > + > +out: > + return ret; > +} Or not bother ;) It doesn't make any difference. > --- /dev/null > +++ b/arch/mips/include/asm/octeon/cvmx-rnm-defs.h > > ... > > + uint64_t u64; > > ... > This file should include types.h (at least). From akpm@linux-foundation.org Tue Aug 11 00:36:05 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 11 Aug 2009 00:36:13 +0200 (CEST) Received: from smtp1.linux-foundation.org ([140.211.169.13]:38352 "EHLO smtp1.linux-foundation.org" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1493555AbZHJWft (ORCPT ); Tue, 11 Aug 2009 00:35:49 +0200 Received: from imap1.linux-foundation.org (imap1.linux-foundation.org [140.211.169.55]) by smtp1.linux-foundation.org (8.14.2/8.13.5/Debian-3ubuntu1.1) with ESMTP id n7AMYdiu024259 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Mon, 10 Aug 2009 15:34:40 -0700 Received: from akpm.mtv.corp.google.com (localhost [127.0.0.1]) by imap1.linux-foundation.org (8.13.5.20060308/8.13.5/Debian-3ubuntu1.1) with SMTP id n7AMYc1i023953; Mon, 10 Aug 2009 15:34:38 -0700 Date: Mon, 10 Aug 2009 15:34:38 -0700 From: Andrew Morton To: David Daney Cc: ralf@linux-mips.org, torvalds@linux-foundation.org, linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, Herbert Xu Subject: Re: [PATCH 0/2] New hardware RNG for Octeon SOCs. Message-Id: <20090810153438.542f55e0.akpm@linux-foundation.org> In-Reply-To: <4A806529.3060609@caviumnetworks.com> References: <4A806529.3060609@caviumnetworks.com> X-Mailer: Sylpheed version 2.2.4 (GTK+ 2.8.20; i486-pc-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-MIMEDefang-Filter: lf$Revision: 1.188 $ X-Scanned-By: MIMEDefang 2.63 on 140.211.169.13 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23891 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: akpm@linux-foundation.org Precedence: bulk X-list: linux-mips On Mon, 10 Aug 2009 11:21:29 -0700 David Daney wrote: > Behold the Random Number Generator driver for Octeon! Hail! > The first patch adds some port definitions and the octeon_rng platform > device. The second is the driver. > > I am copying AKPM and Linus as there seems to be no hw_random maintainer. > > Since Octeon is a mips port, we might want to merge both patches via > Ralf's tree. > > Comments? Looks OK to me - I had a couple of minor comments. Please send the patches to Herbert and Ralf - I'd normally expect one of those two gents to be the merge path for this work. From akpm@linux-foundation.org Tue Aug 11 00:36:46 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 11 Aug 2009 00:36:52 +0200 (CEST) Received: from smtp1.linux-foundation.org ([140.211.169.13]:50454 "EHLO smtp1.linux-foundation.org" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S2097300AbZHJWgq (ORCPT ); Tue, 11 Aug 2009 00:36:46 +0200 Received: from imap1.linux-foundation.org (imap1.linux-foundation.org [140.211.169.55]) by smtp1.linux-foundation.org (8.14.2/8.13.5/Debian-3ubuntu1.1) with ESMTP id n7AMZZnE024323 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Mon, 10 Aug 2009 15:35:36 -0700 Received: from akpm.mtv.corp.google.com (localhost [127.0.0.1]) by imap1.linux-foundation.org (8.13.5.20060308/8.13.5/Debian-3ubuntu1.1) with SMTP id n7AMZZYk025568; Mon, 10 Aug 2009 15:35:35 -0700 Date: Mon, 10 Aug 2009 15:35:35 -0700 From: Andrew Morton To: David Daney Cc: ralf@linux-mips.org, torvalds@linux-foundation.org, linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, ddaney@caviumnetworks.com, Herbert Xu , Matt Mackall Subject: Re: [PATCH 2/2] hw_random: Add hardware RNG for Octeon SOCs. Message-Id: <20090810153535.a1257613.akpm@linux-foundation.org> In-Reply-To: <1249929025-29625-2-git-send-email-ddaney@caviumnetworks.com> References: <4A806529.3060609@caviumnetworks.com> <1249929025-29625-2-git-send-email-ddaney@caviumnetworks.com> X-Mailer: Sylpheed version 2.2.4 (GTK+ 2.8.20; i486-pc-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-MIMEDefang-Filter: lf$Revision: 1.188 $ X-Scanned-By: MIMEDefang 2.63 on 140.211.169.13 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23892 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: akpm@linux-foundation.org Precedence: bulk X-list: linux-mips On Mon, 10 Aug 2009 11:30:25 -0700 David Daney wrote: > Now what's going on with all this typecasting? > diff --git a/drivers/char/hw_random/octeon-rng.c b/drivers/char/hw_random/octeon-rng.c > new file mode 100644 > index 0000000..84d33a7 > --- /dev/null > +++ b/drivers/char/hw_random/octeon-rng.c > @@ -0,0 +1,146 @@ > +/* > + * Hardware Random Number Generator support for Cavium Networks > + * Octeon processor family. > + * > + * This file is subject to the terms and conditions of the GNU General Public > + * License. See the file "COPYING" in the main directory of this archive > + * for more details. > + * > + * Copyright (C) 2009 Cavium Networks > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > + > +#include > +#include > + > +struct octeon_rng { > + u64 control_status; > + u64 result; > +}; > + > +static int octeon_rng_init(struct hwrng *rng) > +{ > + struct octeon_rng *p = (struct octeon_rng *)rng->priv; Here it's unavoidable because some bad person went and made hwrng.priv an `unsigned long'. I haven't checked, but I bet it should have been a void*. > + union cvmx_rnm_ctl_status ctl; > + > + ctl.u64 = 0; > + ctl.s.ent_en = 1; /* Enable the entropy source. */ > + ctl.s.rng_en = 1; /* Enable the RNG hardware. */ > + cvmx_write_csr(p->control_status, ctl.u64); > + return 0; > +} > + > +static void octeon_rng_cleanup(struct hwrng *rng) > +{ > + struct octeon_rng *p = (struct octeon_rng *)rng->priv; > + union cvmx_rnm_ctl_status ctl; > + > + ctl.u64 = 0; > + /* Disable everything. */ > + cvmx_write_csr(p->control_status, ctl.u64); > +} > + > +static int octeon_rng_data_read(struct hwrng *rng, u32 *data) > +{ > + struct octeon_rng *p = (struct octeon_rng *)rng->priv; > + > + *data = cvmx_read64_uint32(p->result); > + return sizeof(u32); > +} > + > +static struct hwrng octeon_rng_ops = { > + .name = "octeon", > + .init = octeon_rng_init, > + .cleanup = octeon_rng_cleanup, > + .data_read = octeon_rng_data_read > +}; > + > +static int __devinit octeon_rng_probe(struct platform_device *pdev) > +{ > + struct resource *res_ports; > + struct resource *res_result; > + struct octeon_rng *p; > + int ret; > + > + p = devm_kzalloc(&pdev->dev, sizeof(*p), GFP_KERNEL); > + if (!p) > + return -ENOMEM; > + > + res_ports = platform_get_resource(pdev, IORESOURCE_MEM, 0); > + if (!res_ports) > + goto err_ports; > + > + res_result = platform_get_resource(pdev, IORESOURCE_MEM, 1); > + if (!res_result) > + goto err_ports; > + > + > + p->control_status = (u64)devm_ioremap_nocache(&pdev->dev, > + res_ports->start, > + sizeof(u64)); devm_ioremap_nocache() returns a `void __iomem *'. Hence we should be recording that value in a field of type `void __iomem *'. Instead, we're wedging it into a u64. Something went wrong! > + if (!p->control_status) > + goto err_ports; > + > + p->result = (u64)devm_ioremap_nocache(&pdev->dev, > + res_result->start, > + sizeof(u64)); Ditto. > + if (!p->result) > + goto err_r; > + octeon_rng_ops.priv = (unsigned long)p; The hwrng.priv problem again. > + dev_set_drvdata(&pdev->dev, &octeon_rng_ops); > + ret = hwrng_register(&octeon_rng_ops); > + if (ret) > + goto err; > + > + dev_info(&pdev->dev, "Octeon Random Number Generator\n"); > + > + return 0; > +err: > + devm_iounmap(&pdev->dev, (void *)p->control_status); > +err_r: > + devm_iounmap(&pdev->dev, (void *)p->result); > +err_ports: > + devm_kfree(&pdev->dev, p); > + return -ENOENT; > +} > + > +static int __exit octeon_rng_remove(struct platform_device *pdev) > +{ > + struct hwrng *rng = dev_get_drvdata(&pdev->dev); > + > + hwrng_unregister(rng); > + > + return 0; > +} > + > +static struct platform_driver octeon_rng_driver = { > + .driver = { > + .name = "octeon_rng", > + .owner = THIS_MODULE, > + }, > + .probe = octeon_rng_probe, > + .remove = __exit_p(octeon_rng_remove), > +}; > + > +static int __init octeon_rng_mod_init(void) > +{ > + return platform_driver_register(&octeon_rng_driver); > +} > + > +static void __exit octeon_rng_mod_exit(void) > +{ > + platform_driver_unregister(&octeon_rng_driver); > +} > + > +module_init(octeon_rng_mod_init); > +module_exit(octeon_rng_mod_exit); > + > +MODULE_AUTHOR("David Daney"); > +MODULE_LICENSE("GPL"); Please take another look and check that the selection of types was as good as it could possibly be? Also, let's all send rude emails to Herbert over the type of hwrng.priv ;) From f.fainelli@gmail.com Tue Aug 11 15:22:34 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 11 Aug 2009 15:22:42 +0200 (CEST) Received: from ey-out-1920.google.com ([74.125.78.145]:50221 "EHLO ey-out-1920.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492897AbZHKNWR convert rfc822-to-8bit (ORCPT ); Tue, 11 Aug 2009 15:22:17 +0200 Received: by ey-out-1920.google.com with SMTP id 13so935057eye.54 for ; Tue, 11 Aug 2009 06:22:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:sender:from:to:subject:date :user-agent:cc:references:in-reply-to:mime-version:content-type :content-transfer-encoding:content-disposition:message-id; bh=vgbuLOZEPruwhiNO7H0tyXmmhqQrSPZAxTbBuV9inRs=; b=J4fKh3pj7/4uUxqYo/birF3LNhsy7S8BrpmnWKmgjBS4L+T4v22yWLPtm0UbNugQmS PhmPvVIHAxm09hekteTvaaMh+ehEVj/NY2DeHNsNsIEcfcFCGGDibwNGyDJ292LRddcA 6UEk1J4ZwcbxKBpqL9pUi9Ge8bGT2rCTVcw9I= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:from:to:subject:date:user-agent:cc:references:in-reply-to :mime-version:content-type:content-transfer-encoding :content-disposition:message-id; b=H8gl0szkKU9WpIjA/deNugXZ803r2gN0dRjchLFisTeURUK7+2i3pkAIwLAPCx4L+z DZi1YF7MqsyvPIopHwkmGOSvcDV/DRMtOYQ/4kuKIEMsx3kMMk+nUEpP6wMDI2k/DVaw p6cqbRIH8uSvYU0uxavOh3UBl+suwR+D6ncCo= Received: by 10.211.194.4 with SMTP id w4mr920881ebp.41.1249996632732; Tue, 11 Aug 2009 06:17:12 -0700 (PDT) Received: from florian.lab.openpattern.org (lab.openpattern.org [82.240.16.241]) by mx.google.com with ESMTPS id 7sm14691997eyb.50.2009.08.11.06.17.11 (version=TLSv1/SSLv3 cipher=RC4-MD5); Tue, 11 Aug 2009 06:17:12 -0700 (PDT) From: Florian Fainelli To: Wim Van Sebroeck Subject: Re: [PATCH 2/2] ar7_wdt: convert to become a platform driver Date: Tue, 11 Aug 2009 15:17:08 +0200 User-Agent: KMail/1.9.9 Cc: ralf Baechle , linux-mips@linux-mips.org References: <200907151210.20294.florian@openwrt.org> <200908111452.28418.florian@openwrt.org> <20090811130133.GH4302@infomag.iguana.be> In-Reply-To: <20090811130133.GH4302@infomag.iguana.be> MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 8BIT Content-Disposition: inline Message-Id: <200908111517.09726.florian@openwrt.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23893 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips Le Tuesday 11 August 2009 15:01:33 Wim Van Sebroeck, vous avez écrit : > Hi Florian, > > > > From: Florian Fainelli > > > Subject: [PATCH 2/2 v2] ar7_wdt: convert to become a platform driver > > > > > > This patch converts the ar7_wdt driver to become > > > a platform driver. The AR7 SoC specific identification > > > and base register calculation is performed by the board > > > code, therefore we no longer need to have access to > > > ar7_chip_id. We also remove the reboot notifier code to > > > use the platform shutdown method as Wim suggested. > > > > > > Signed-off-by: Florian Fainelli > > > Signed-off-by: Wim Van Sebroeck > > > > Any news on this patch ? > > This one was ok for me. I think we agreed that Ralf would take it up in his > tree. I can also take it up in my next tree still. Oh, I did not understand that sorry, I thought Ralf would take the first one which is MIPS-specific. -- Best regards, Florian Fainelli Email: florian@openwrt.org Web: http://openwrt.org IRC: [florian] on irc.freenode.net ------------------------------- From wim@iguana.be Tue Aug 11 15:23:40 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 11 Aug 2009 15:23:47 +0200 (CEST) Received: from mailrelay007.isp.belgacom.be ([195.238.6.173]:60222 "EHLO mailrelay007.isp.belgacom.be" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492805AbZHKNXk (ORCPT ); Tue, 11 Aug 2009 15:23:40 +0200 X-Belgacom-Dynamic: yes X-IronPort-Anti-Spam-Filtered: true X-IronPort-Anti-Spam-Result: ApoEALcHgUpR92pY/2dsb2JhbADSDgmEEAWCJw Received: from 88.106-247-81.adsl-dyn.isp.belgacom.be (HELO infomag) ([81.247.106.88]) by relay.skynet.be with ESMTP; 11 Aug 2009 15:01:34 +0200 Received: from wim by infomag with local (Exim 4.69) (envelope-from ) id 1Maqyr-00039X-UF; Tue, 11 Aug 2009 15:01:33 +0200 Date: Tue, 11 Aug 2009 15:01:33 +0200 From: Wim Van Sebroeck To: Florian Fainelli Cc: ralf Baechle , linux-mips@linux-mips.org Subject: Re: [PATCH 2/2] ar7_wdt: convert to become a platform driver Message-ID: <20090811130133.GH4302@infomag.iguana.be> References: <200907151210.20294.florian@openwrt.org> <20090718214958.GA24850@infomag.iguana.be> <200907211211.35085.florian@openwrt.org> <200908111452.28418.florian@openwrt.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <200908111452.28418.florian@openwrt.org> User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23894 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wim@iguana.be Precedence: bulk X-list: linux-mips Hi Florian, > > From: Florian Fainelli > > Subject: [PATCH 2/2 v2] ar7_wdt: convert to become a platform driver > > > > This patch converts the ar7_wdt driver to become > > a platform driver. The AR7 SoC specific identification > > and base register calculation is performed by the board > > code, therefore we no longer need to have access to > > ar7_chip_id. We also remove the reboot notifier code to > > use the platform shutdown method as Wim suggested. > > > > Signed-off-by: Florian Fainelli > > Signed-off-by: Wim Van Sebroeck > > Any news on this patch ? This one was ok for me. I think we agreed that Ralf would take it up in his tree. I can also take it up in my next tree still. Ralf, did you add the patch allready or will I do it? Thanks in advance, Kind regards, Wim. From f.fainelli@gmail.com Tue Aug 11 15:51:17 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 11 Aug 2009 15:51:23 +0200 (CEST) Received: from ey-out-1920.google.com ([74.125.78.146]:17413 "EHLO ey-out-1920.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492635AbZHKNvQ convert rfc822-to-8bit (ORCPT ); Tue, 11 Aug 2009 15:51:16 +0200 Received: by ey-out-1920.google.com with SMTP id 13so939611eye.54 for ; Tue, 11 Aug 2009 06:51:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:sender:from:to:subject:date :user-agent:cc:references:in-reply-to:mime-version:content-type :content-transfer-encoding:content-disposition:message-id; bh=VWOqSgD02snaRDWAkA84wktKwWXwTAu+sO1qPT6fHvk=; b=BhKvCtmETKnzDxAwgN0KZLDU7Exbah7kEKy7NFu/Ianw1/Nt0qlLMykmVAIopp6sEN 66GG13jcxI1BpRAKTnGanYR2BhjAfcO1qF7KldRliXB4yoj0rlHkgIvpfGbVCq5BpJm3 vRtvRsScJkAAhaFUesrx+Mo18efqztiqzSWCQ= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:from:to:subject:date:user-agent:cc:references:in-reply-to :mime-version:content-type:content-transfer-encoding :content-disposition:message-id; b=fHuYxZZlnIWkoQTb9aDvJofeNP7zsWDgOE6HBaHA7DpbMUvcW7US9ZYU06z/jFD1PQ 8NvEdgEYwNtUVnAhkK58T3Wjrbt8hIH4gy7wEf8E++W7jj1s84vfSrTCGRPuWfDS5Vtk DTC4Tdn6WksP1e8hqJY8Yu6eZeoX2remsfwfY= Received: by 10.210.70.8 with SMTP id s8mr867343eba.69.1249995161058; Tue, 11 Aug 2009 05:52:41 -0700 (PDT) Received: from florian.lab.openpattern.org (lab.openpattern.org [82.240.16.241]) by mx.google.com with ESMTPS id 7sm172871eyg.15.2009.08.11.05.52.29 (version=TLSv1/SSLv3 cipher=RC4-MD5); Tue, 11 Aug 2009 05:52:35 -0700 (PDT) From: Florian Fainelli To: Wim Van Sebroeck Subject: Re: [PATCH 2/2] ar7_wdt: convert to become a platform driver Date: Tue, 11 Aug 2009 14:52:26 +0200 User-Agent: KMail/1.9.9 Cc: Ralf Baechle , linux-mips@linux-mips.org References: <200907151210.20294.florian@openwrt.org> <20090718214958.GA24850@infomag.iguana.be> <200907211211.35085.florian@openwrt.org> In-Reply-To: <200907211211.35085.florian@openwrt.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8BIT Content-Disposition: inline Message-Id: <200908111452.28418.florian@openwrt.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23895 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips Hi Wim, Le Tuesday 21 July 2009 12:11:32 Florian Fainelli, vous avez écrit : > Hi Wim, > > Le Saturday 18 July 2009 23:49:58 Wim Van Sebroeck, vous avez écrit : > > Hi Florian, > > > > Forgot the attachment... > > > > Kind regards, > > Wim. > > > > > Hi Florian, > > > > > > > This patch converts the ar7_wdt driver to become a platform > > > > driver. The AR7 SoC specific identification and base register > > > > calculation is performed by the board code, therefore we no > > > > longer need to have access to ar7_chip_id. > > > > > > > > @@ -298,22 +285,33 @@ static struct miscdevice ar7_wdt_miscdev = { > > > > .fops = &ar7_wdt_fops, > > > > }; > > > > > > > > -static int __init ar7_wdt_init(void) > > > > +static int __init ar7_wdt_probe(struct platform_device *pdev) > > > > > > Should be __devinit . > > > > > > > +static struct platform_driver ar7_wdt_driver = { > > > > + .driver.name = "ar7_wdt", > > > > + .probe = ar7_wdt_probe, > > > > + .remove = __devexit_p(ar7_wdt_remove), > > > > +}; > > > > > > I prefer to have it as follows (so that the driver.owner field is also > > > set): static struct platform_driver ar7_wdt_driver = { > > > .probe = ar7_wdt_probe, > > > .remove = __devexit_p(ar7_wdt_remove), > > > .driver = { > > > .owner = THIS_MODULE, > > > .name = "ar7_wdt", > > > }, > > > }; > > > > > > I suggest to also change the reboot notifier code into a platform > > > shutdown method. You then get something like the attached patch > > > (untested, uncompiled and I included above 2 remarks). For the rest: > > > code is OK for me. After the __init to __devinit fix you can add my > > > signed-off-by. > > Thanks, patch updated and attached. > > > > Kind regards, > > > Wim. > > -- > From: Florian Fainelli > Subject: [PATCH 2/2 v2] ar7_wdt: convert to become a platform driver > > This patch converts the ar7_wdt driver to become > a platform driver. The AR7 SoC specific identification > and base register calculation is performed by the board > code, therefore we no longer need to have access to > ar7_chip_id. We also remove the reboot notifier code to > use the platform shutdown method as Wim suggested. > > Signed-off-by: Florian Fainelli > Signed-off-by: Wim Van Sebroeck Any news on this patch ? > -- > diff --git a/drivers/watchdog/ar7_wdt.c b/drivers/watchdog/ar7_wdt.c > index 2f8643e..82855b0 100644 > --- a/drivers/watchdog/ar7_wdt.c > +++ b/drivers/watchdog/ar7_wdt.c > @@ -28,9 +28,8 @@ > #include > #include > #include > +#include > #include > -#include > -#include > #include > #include > #include > @@ -76,24 +75,10 @@ static unsigned expect_close; > /* XXX currently fixed, allows max margin ~68.72 secs */ > #define prescale_value 0xffff > > -/* Offset of the WDT registers */ > -static unsigned long ar7_regs_wdt; > +/* Resource of the WDT registers */ > +static struct resource *ar7_regs_wdt; > /* Pointer to the remapped WDT IO space */ > static struct ar7_wdt *ar7_wdt; > -static void ar7_wdt_get_regs(void) > -{ > - u16 chip_id = ar7_chip_id(); > - switch (chip_id) { > - case AR7_CHIP_7100: > - case AR7_CHIP_7200: > - ar7_regs_wdt = AR7_REGS_WDT; > - break; > - default: > - ar7_regs_wdt = UR8_REGS_WDT; > - break; > - } > -} > - > > static void ar7_wdt_kick(u32 value) > { > @@ -202,20 +187,6 @@ static int ar7_wdt_release(struct inode *inode, struct > file *file) return 0; > } > > -static int ar7_wdt_notify_sys(struct notifier_block *this, > - unsigned long code, void *unused) > -{ > - if (code == SYS_HALT || code == SYS_POWER_OFF) > - if (!nowayout) > - ar7_wdt_disable_wdt(); > - > - return NOTIFY_DONE; > -} > - > -static struct notifier_block ar7_wdt_notifier = { > - .notifier_call = ar7_wdt_notify_sys, > -}; > - > static ssize_t ar7_wdt_write(struct file *file, const char *data, > size_t len, loff_t *ppos) > { > @@ -299,56 +270,85 @@ static struct miscdevice ar7_wdt_miscdev = { > .fops = &ar7_wdt_fops, > }; > > -static int __init ar7_wdt_init(void) > +static int __devinit ar7_wdt_probe(struct platform_device *pdev) > { > int rc; > > spin_lock_init(&wdt_lock); > > - ar7_wdt_get_regs(); > + ar7_regs_wdt = > + platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs"); > + if (!ar7_regs_wdt) { > + printk(KERN_ERR DRVNAME ": could not get registers resource\n"); > + rc = -ENODEV; > + goto out; > + } > > - if (!request_mem_region(ar7_regs_wdt, sizeof(struct ar7_wdt), > - LONGNAME)) { > + if (!request_mem_region(ar7_regs_wdt->start, > + resource_size(ar7_regs_wdt), LONGNAME)) { > printk(KERN_WARNING DRVNAME ": watchdog I/O region busy\n"); > - return -EBUSY; > + rc = -EBUSY; > + goto out; > } > > - ar7_wdt = (struct ar7_wdt *) > - ioremap(ar7_regs_wdt, sizeof(struct ar7_wdt)); > + ar7_wdt = ioremap(ar7_regs_wdt->start, resource_size(ar7_regs_wdt)); > + if (!ar7_wdt) { > + printk(KERN_ERR DRVNAME ": could not ioremap registers\n"); > + rc = -ENXIO; > + goto out; > + } > > ar7_wdt_disable_wdt(); > ar7_wdt_prescale(prescale_value); > ar7_wdt_update_margin(margin); > > - rc = register_reboot_notifier(&ar7_wdt_notifier); > - if (rc) { > - printk(KERN_ERR DRVNAME > - ": unable to register reboot notifier\n"); > - goto out_alloc; > - } > - > rc = misc_register(&ar7_wdt_miscdev); > if (rc) { > printk(KERN_ERR DRVNAME ": unable to register misc device\n"); > - goto out_register; > + goto out_alloc; > } > goto out; > > -out_register: > - unregister_reboot_notifier(&ar7_wdt_notifier); > out_alloc: > iounmap(ar7_wdt); > - release_mem_region(ar7_regs_wdt, sizeof(struct ar7_wdt)); > + release_mem_region(ar7_regs_wdt->start, resource_size(ar7_regs_wdt)); > out: > return rc; > } > > -static void __exit ar7_wdt_cleanup(void) > +static int __devexit ar7_wdt_remove(struct platform_device *pdev) > { > misc_deregister(&ar7_wdt_miscdev); > - unregister_reboot_notifier(&ar7_wdt_notifier); > iounmap(ar7_wdt); > - release_mem_region(ar7_regs_wdt, sizeof(struct ar7_wdt)); > + release_mem_region(ar7_regs_wdt->start, resource_size(ar7_regs_wdt)); > + > + return 0; > +} > + > +static void ar7_wdt_shutdown(struct platform_device *pdev) > +{ > + if (!nowayout) > + ar7_wdt_disable_wdt(); > +} > + > +static struct platform_driver ar7_wdt_driver = { > + .probe = ar7_wdt_probe, > + .remove = __devexit_p(ar7_wdt_remove), > + .shutdown = ar7_wdt_shutdown, > + .driver = { > + .owner = THIS_MODULE, > + .name = "ar7_wdt", > + }, > +}; > + > +static int __init ar7_wdt_init(void) > +{ > + return platform_driver_register(&ar7_wdt_driver); > +} > + > +static void __exit ar7_wdt_cleanup(void) > +{ > + platform_driver_unregister(&ar7_wdt_driver); > } > > module_init(ar7_wdt_init); -- Best regards, Florian Fainelli Email: florian@openwrt.org Web: http://openwrt.org IRC: [florian] on irc.freenode.net ------------------------------- From f.fainelli@gmail.com Tue Aug 11 23:20:06 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 11 Aug 2009 23:20:12 +0200 (CEST) Received: from mail-ew0-f216.google.com ([209.85.219.216]:54832 "EHLO mail-ew0-f216.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492954AbZHKVUG convert rfc822-to-8bit (ORCPT ); Tue, 11 Aug 2009 23:20:06 +0200 Received: by ewy12 with SMTP id 12so4864385ewy.0 for ; Tue, 11 Aug 2009 14:20:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:sender:from:to:subject:date :user-agent:cc:references:in-reply-to:mime-version:content-type :content-transfer-encoding:content-disposition:message-id; bh=LnQ/YSiC0XwTd4ZH/UqwjTqmaNoRbhTzk2abTlxZ+EI=; b=otaT7dha4cfXt7OVLJzh7bEP2ddKP2EF5FnUOUtEcExQwWs0rauFwqGSDYXbEiFF20 sAcFtqmZabBXxhEKLJbJmVxkuSxJhc/Ek9FgXVQTUexoacR3OPePISx1vmsxVsw38f67 q+rmV9XdKmVtLkNZc+qUD36bcJxkAKycUt/WU= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:from:to:subject:date:user-agent:cc:references:in-reply-to :mime-version:content-type:content-transfer-encoding :content-disposition:message-id; b=J88UcqHYh50H2K+IayVyw7zbeXBwkNpvXRx7oEtmoXa0hrLS80BwjcRGj/wDNM15z+ qcfx3uRKyC7ErhAPGt/BjPK1KexIMSsz14KxzDOMc8jXSFSRP+9kg9OtL8EM9pD8oefj blUMGRVe3TGfqSTY0uXkh/znNoSFbrOpZVGwY= Received: by 10.211.194.4 with SMTP id w4mr1487243ebp.41.1250025601264; Tue, 11 Aug 2009 14:20:01 -0700 (PDT) Received: from lenovo.mimichou.home (florian.mimichou.net [82.241.112.26]) by mx.google.com with ESMTPS id 28sm943217eye.34.2009.08.11.14.20.00 (version=TLSv1/SSLv3 cipher=RC4-MD5); Tue, 11 Aug 2009 14:20:00 -0700 (PDT) From: Florian Fainelli To: Alexander Clouter Subject: Re: AR7 runtime identification [was:- Re: [PATCH -v1] MIPS: add support for gzip/bzip2/lzma compressed kernel images] Date: Tue, 11 Aug 2009 23:19:56 +0200 User-Agent: KMail/1.9.9 Cc: Wu Zhangjin , linux-mips@linux-mips.org References: <1249894154-10982-1-git-send-email-wuzhangjin@gmail.com> <20090810101205.GW19816@chipmunk> <200908102342.30031.florian@openwrt.org> In-Reply-To: <200908102342.30031.florian@openwrt.org> MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 8BIT Content-Disposition: inline Message-Id: <200908112319.58367.florian@openwrt.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23896 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips Le Monday 10 August 2009 23:42:27 Florian Fainelli, vous avez écrit : > Hi Alexander, > > Le Monday 10 August 2009 12:12:05 Alexander Clouter, vous avez écrit : > > * Florian Fainelli [2009-08-10 12:06:07+0200]: > > > Hi Alexander, > > > > > > Le Monday 10 August 2009 11:03:15 Alexander Clouter, vous avez écrit : > > > > I notice in arch/mips/ar7/prom.c the while loop hangs on > > > > "(serial_in(UART_LSR) & UART_LSR_TEMT)" instead, is this because of > > > > the buggy UART's seen in some revisions of the AR7? As it stands > > > > Wu's putc() implementation works fine for me but I'm guessing it is > > > > because the UART has not much opportunity for over/underruns as not > > > > much is being sent. > > > > > > Even with the silicon bug, this should not be a problem as long as you > > > keep polling the LSR_TEMT bit in the LSR register. The problem appears > > > when running the UART with interrupts. > > > > Ahhhh, that makes sense. I'll leave Wu's code alone :) > > > > > > The UART on my board is buggy (missing/repeated characters like many > > > > others seem to get) to, but I remember seeing somewhere (in a chat > > > > you had years ago with Alan Cox if I remember correctly) the UART is > > > > not buggy on *all* AR7 based boards? Is is possible to detect a > > > > buggy UART at runtime (maybe via a AR7 revision match test)? > > > > > > Alan Cox suggested to perform some tests which I did not carry out yet. > > > By using two different hardware revisions in two different routers I > > > noticed that the silicon bug is present in TNETD7300GDU revision 4, > > > while revision 5 does not have it. > > > > > > The revision id can certainly help differentiating between the silicon > > > version, later tonight when I have access to the hardware I will > > > compare between a WAG54G and a C54APRx. I remember being them different > > > for theTNETD7300GDU rev 4 and the rev 5. > > > > Well, I was offering that I could add an extra datapoint if need be. > > There must be a way to fix up the UART without adding a 'new' UART type, > > in a clean way. I'll have a look into it tonight, but I imagine you > > have looked at this in far more detail than I could...but hey, it gives > > me something to do tonight[1]. :) > > For your information, the TNETD7300GDU is detected like this: > TI AR7 (TNETD7300), ID: 0x0005, Revision: 0x02 > > and the TNETD7300EZDW (ADSL 2+) is detected like this: > TI AR7 (TNETD7200), ID: 0x002b, Revision: 0x10 which also has the UART bug > and is wrongly detected as a TNETD7200. > > I have left the WAG54G at work and will get my hands back on it tomorow. The bad news is that my WAG54G v2 which is also a TNEDT7300GDU has this HW bug too rendering the runtime detection of the bug more difficult. -- Best regards, Florian Fainelli Email: florian@openwrt.org Web: http://openwrt.org IRC: [florian] on irc.freenode.net ------------------------------- From sgi-linux-mips@m.gmane.org Wed Aug 12 11:08:26 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 12 Aug 2009 11:08:33 +0200 (CEST) Received: from main.gmane.org ([80.91.229.2]:35591 "EHLO ciao.gmane.org" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492893AbZHLJI0 (ORCPT ); Wed, 12 Aug 2009 11:08:26 +0200 Received: from list by ciao.gmane.org with local (Exim 4.43) id 1Mb9ok-0001Xg-2F for linux-mips@linux-mips.org; Wed, 12 Aug 2009 09:08:22 +0000 Received: from chipmunk.wormnet.eu ([195.195.131.226]) by main.gmane.org with esmtp (Gmexim 0.1 (Debian)) id 1AlnuQ-0007hv-00 for ; Wed, 12 Aug 2009 09:08:22 +0000 Received: from alex by chipmunk.wormnet.eu with local (Gmexim 0.1 (Debian)) id 1AlnuQ-0007hv-00 for ; Wed, 12 Aug 2009 09:08:22 +0000 X-Injected-Via-Gmane: http://gmane.org/ To: linux-mips@linux-mips.org From: Alexander Clouter Subject: Re: AR7 runtime identification [was:- Re: [PATCH -v1] MIPS: add support for gzip/bzip2/lzma compressed kernel images] Date: Wed, 12 Aug 2009 09:37:04 +0100 Lines: 31 Message-ID: References: <1249894154-10982-1-git-send-email-wuzhangjin@gmail.com> <20090810101205.GW19816@chipmunk> <200908102342.30031.florian@openwrt.org> <200908112319.58367.florian@openwrt.org> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-15 Content-Transfer-Encoding: 8bit X-Complaints-To: usenet@ger.gmane.org X-Gmane-NNTP-Posting-Host: chipmunk.wormnet.eu User-Agent: tin/1.9.3-20080506 ("Dalintober") (UNIX) (Linux/2.6.26-2-sparc64-smp (sparc64)) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23897 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: alex@digriz.org.uk Precedence: bulk X-list: linux-mips Florian Fainelli wrote: > >> Le Monday 10 August 2009 12:12:05 Alexander Clouter, vous avez écrit : >> >> For your information, the TNETD7300GDU is detected like this: >> TI AR7 (TNETD7300), ID: 0x0005, Revision: 0x02 >> >> and the TNETD7300EZDW (ADSL 2+) is detected like this: >> TI AR7 (TNETD7200), ID: 0x002b, Revision: 0x10 which also has the UART bug >> and is wrongly detected as a TNETD7200. >> >> I have left the WAG54G at work and will get my hands back on it tomorow. > > The bad news is that my WAG54G v2 which is also a TNEDT7300GDU has this HW bug > too rendering the runtime detection of the bug more difficult. > Well, two options I guess. Another Kconfig or pass something on the command line to the kernel. I would opt for the latter as the bug does not make the machine completely unusable and if you make sure the workaround is disabled by default hopefully that will have the effect of getting people to contact you to add an extra data point. Annoyingly I'm guess we are more interested in people who do *not* have the bug and we would not hear from them as a result. Maybe if we proactively crippled their serial port.... :) Cheers -- Alexander Clouter .sigmonster says: Be braver -- you can't cross a chasm in two small jumps. From f.fainelli@gmail.com Wed Aug 12 11:19:56 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 12 Aug 2009 11:20:01 +0200 (CEST) Received: from ey-out-1920.google.com ([74.125.78.145]:4143 "EHLO ey-out-1920.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492114AbZHLJT4 convert rfc822-to-8bit (ORCPT ); Wed, 12 Aug 2009 11:19:56 +0200 Received: by ey-out-1920.google.com with SMTP id 13so4569eye.54 for ; Wed, 12 Aug 2009 02:19:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:sender:from:to:subject:date :user-agent:cc:references:in-reply-to:mime-version:content-type :content-transfer-encoding:content-disposition:message-id; bh=tMdjKw7SFVwt7WR9GKY3Ncj1ZgbgcTPkaot9moRrWeE=; b=UaPgiEOjSb1qCXR6vPenPrKAR1ajK4d0liOVps6LgouvosVRApkaVwhGAbEMSFbtr4 cxkbV9AaeRSbahTXH9tpSwFCLi9mSWw3LiZPV9WFX/HBYzW+AcUcvqB8qI6hMjYLdtHF qrA7gvv6CkTIzR7ACrLJVO/qLZx3Ly0AjbgSM= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:from:to:subject:date:user-agent:cc:references:in-reply-to :mime-version:content-type:content-transfer-encoding :content-disposition:message-id; b=s8JhetwAgrGEOXkMUR83zdiypXhYMmsLI65UWBsWWn8XogTJl56pnmM9R2lo0Epyus IQXSQvVpACVgYx5lM0+KWWM5oQ3tvJBHL1PDBT7NiFpCwBCuXgDacC0ZRcw1H3ErFsAj bjyCWGwCkRg+2jy394adGOHcbX+rai5Haa1do= Received: by 10.210.20.10 with SMTP id 10mr2183228ebt.72.1250068795397; Wed, 12 Aug 2009 02:19:55 -0700 (PDT) Received: from florian.lab.openpattern.org (lab.openpattern.org [82.240.16.241]) by mx.google.com with ESMTPS id 7sm2162415eyb.50.2009.08.12.02.19.49 (version=TLSv1/SSLv3 cipher=RC4-MD5); Wed, 12 Aug 2009 02:19:53 -0700 (PDT) From: Florian Fainelli To: Alexander Clouter Subject: Re: AR7 runtime identification [was:- Re: [PATCH -v1] MIPS: add support for gzip/bzip2/lzma compressed kernel images] Date: Wed, 12 Aug 2009 11:19:44 +0200 User-Agent: KMail/1.9.9 Cc: linux-mips@linux-mips.org References: <1249894154-10982-1-git-send-email-wuzhangjin@gmail.com> <200908112319.58367.florian@openwrt.org> In-Reply-To: MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-15" Content-Transfer-Encoding: 8BIT Content-Disposition: inline Message-Id: <200908121119.48135.florian@openwrt.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23898 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips Le Wednesday 12 August 2009 10:37:04 Alexander Clouter, vous avez écrit : > Florian Fainelli wrote: > >> Le Monday 10 August 2009 12:12:05 Alexander Clouter, vous avez écrit : > >> > >> For your information, the TNETD7300GDU is detected like this: > >> TI AR7 (TNETD7300), ID: 0x0005, Revision: 0x02 > >> > >> and the TNETD7300EZDW (ADSL 2+) is detected like this: > >> TI AR7 (TNETD7200), ID: 0x002b, Revision: 0x10 which also has the UART > >> bug and is wrongly detected as a TNETD7200. > >> > >> I have left the WAG54G at work and will get my hands back on it tomorow. > > > > The bad news is that my WAG54G v2 which is also a TNEDT7300GDU has this > > HW bug too rendering the runtime detection of the bug more difficult. > > Well, two options I guess. Another Kconfig or pass something > on the command line to the kernel. I would opt for the latter as the > bug does not make the machine completely unusable and if you make sure > the workaround is disabled by default hopefully that will have the > effect of getting people to contact you to add an extra data point. Or simply enable the workaround even for sane hardware like it is done here: https://dev.openwrt.org/browser/trunk/target/linux/ar7/patches-2.6.30/500-serial_kludge.patch as this patch has no side effect on working hardware. > > Annoyingly I'm guess we are more interested in people who do *not* have > the bug and we would not hear from them as a result. Maybe if we > proactively crippled their serial port.... :) > > Cheers > -- Cordialement, Florian Fainelli ------------------------------ -- Best regards, Florian Fainelli Email: florian@openwrt.org Web: http://openwrt.org IRC: [florian] on irc.freenode.net ------------------------------- From adobriyan@gmail.com Wed Aug 12 21:59:35 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 12 Aug 2009 21:59:42 +0200 (CEST) Received: from mail-ew0-f216.google.com ([209.85.219.216]:34329 "EHLO mail-ew0-f216.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1493605AbZHLT7f (ORCPT ); Wed, 12 Aug 2009 21:59:35 +0200 Received: by ewy12 with SMTP id 12so333319ewy.0 for ; Wed, 12 Aug 2009 12:59:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:date:from:to:cc:subject :message-id:mime-version:content-type:content-disposition:user-agent; bh=aBDF+DAb7xNe1NA4gzl4SXhExo/kp2fM9PkBmQBLCIo=; b=d6l/zi5LDzXH3tqCktkLCn5v9QqUjQohnXxkwiK9I5+P4i2OCzwaLygwN9sv+hBZEe jacWaI6bcHeBpQ8wGKgHlf5Hjveg8iN/5nqPV/JyU5nStmVMnsQ9EbihRjXtS9NRAhTN QUd+jfplibWZwSGLY+WUsE05RFPBsr0xrUQzU= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=date:from:to:cc:subject:message-id:mime-version:content-type :content-disposition:user-agent; b=CyHq966sAE3YWwGu9kOfdjNon2wC9pG+jlcIS9JZE7MOsQNCSe9ZkTRI96vZcAQvfn gmhmF7EVbtT6bJ2FxT9LlGbXQcpiBwd6fvicbgBTJJjPnTdULYTDzqSsMrrbyvSGKYsB aAAAsGSMfN7ZWn/SIaliqoD56PbfGfH9IWE6o= Received: by 10.210.144.16 with SMTP id r16mr504045ebd.22.1250107170425; Wed, 12 Aug 2009 12:59:30 -0700 (PDT) Received: from localhost ([213.171.34.225]) by mx.google.com with ESMTPS id 28sm3334585eye.4.2009.08.12.12.59.29 (version=TLSv1/SSLv3 cipher=RC4-MD5); Wed, 12 Aug 2009 12:59:30 -0700 (PDT) Date: Wed, 12 Aug 2009 23:59:27 +0400 From: Alexey Dobriyan To: ralf@linux-mips.org Cc: linux-mips@linux-mips.org Subject: [PATCH] mips: fix compilation of mips-lasat Message-ID: <20090812195927.GA2647@x200.localdomain> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23899 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: adobriyan@gmail.com Precedence: bulk X-list: linux-mips Header needed for current_cpu_data which expands to smp_processor_id(). However, linux/smp.h can't be included into asm/cpu-info.h due to horrible circular dependencies, so plug it here. Signed-off-by: Alexey Dobriyan --- arch/mips/include/asm/lasat/lasat.h | 1 + 1 file changed, 1 insertion(+) --- a/arch/mips/include/asm/lasat/lasat.h +++ b/arch/mips/include/asm/lasat/lasat.h @@ -227,6 +227,7 @@ extern void lasat_write_eeprom_info(void); * It is used for the bit-banging rtc and eeprom drivers */ #include +#include /* calculating with the slowest board with 100 MHz clock */ #define LASAT_100_DIVIDER 20 From David.Daney@caviumnetworks.com Wed Aug 12 23:24:36 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 12 Aug 2009 23:24:43 +0200 (CEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:37406 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1493617AbZHLVYg (ORCPT ); Wed, 12 Aug 2009 23:24:36 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,2,2,3503) id ; Wed, 12 Aug 2009 17:23:08 -0400 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Wed, 12 Aug 2009 14:22:52 -0700 Received: from dd1.caveonetworks.com ([64.169.86.201]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Wed, 12 Aug 2009 14:22:52 -0700 Message-ID: <4A8332AB.20105@caviumnetworks.com> Date: Wed, 12 Aug 2009 14:22:51 -0700 From: David Daney User-Agent: Thunderbird 2.0.0.21 (X11/20090320) MIME-Version: 1.0 To: =?ISO-8859-15?Q?Ralf_R=F6sch?= CC: linux-mips Subject: Re: MIPS: Avoid clobbering struct pt_regs in kthreads References: <4A832E6E.8020300@rw-gmbh.de> In-Reply-To: <4A832E6E.8020300@rw-gmbh.de> Content-Type: text/plain; charset=ISO-8859-15; format=flowed Content-Transfer-Encoding: 8bit X-OriginalArrivalTime: 12 Aug 2009 21:22:52.0254 (UTC) FILETIME=[0CCF5FE0:01CA1B93] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23900 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Ralf Rösch wrote: > Hi David, > > Sorry to say, but your commit d406c9ae84d6ef12c55a41c97c34266b2eb7ed31 > makes my TX49xx (Toshiba RISC mipsel) based system unusable. > > The kernel boots fine until the stage: > Freeing unused kernel memory: 140k freed > and then stops. > Some of our LEDS are updated as supposed, so a part of the kernel should > be running. > > Reverting your commit makes the latest 2.4.37.4 kernel usable again. > Do you have an idea what might go wrong? > I'm sorry, I can't think of anything. I would look in copy_thread and the kthread spawning code. Does TX49xx have custom versions of these? David Daney From David.Daney@caviumnetworks.com Fri Aug 14 20:25:32 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 14 Aug 2009 20:25:38 +0200 (CEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:19309 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492856AbZHNSZc (ORCPT ); Fri, 14 Aug 2009 20:25:32 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,2,2,3503) id ; Fri, 14 Aug 2009 14:25:14 -0400 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Fri, 14 Aug 2009 11:24:19 -0700 Received: from dd1.caveonetworks.com ([64.169.86.201]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Fri, 14 Aug 2009 11:24:19 -0700 Message-ID: <4A85ABD3.5040801@caviumnetworks.com> Date: Fri, 14 Aug 2009 11:24:19 -0700 From: David Daney User-Agent: Thunderbird 2.0.0.21 (X11/20090320) MIME-Version: 1.0 To: linux-mips CC: Adam Nemet Subject: .subsection madness Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 14 Aug 2009 18:24:19.0717 (UTC) FILETIME=[70777350:01CA1D0C] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23901 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips In atomic.h for atomic_add we have this gem: __asm__ __volatile__( " .set mips3 \n" "1: ll %0, %1 # atomic_add \n" " addu %0, %2 \n" " sc %0, %1 \n" " beqz %0, 2f \n" " .subsection 2 \n" "2: b 1b \n" " .previous \n" " .set mips0 \n" What is the purpose of the .subsection here? It will not affect branch prediction in the beqz as nothing happens in .subsection 2. For spin locks it is clear that this technique can help, but for atomic_add I don't think so. To make matters worse for some code the subsection is going out of branch range. David Daney From ralf@linux-mips.org Fri Aug 14 23:57:19 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 14 Aug 2009 23:57:26 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:59257 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1493092AbZHNV5T (ORCPT ); Fri, 14 Aug 2009 23:57:19 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id n7ELw0Cn008828; Fri, 14 Aug 2009 22:58:02 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id n7ELvxaY008826; Fri, 14 Aug 2009 22:57:59 +0100 Date: Fri, 14 Aug 2009 22:57:59 +0100 From: Ralf Baechle To: David Daney Cc: linux-mips , Adam Nemet Subject: Re: .subsection madness Message-ID: <20090814215759.GA8282@linux-mips.org> References: <4A85ABD3.5040801@caviumnetworks.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <4A85ABD3.5040801@caviumnetworks.com> User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23902 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Fri, Aug 14, 2009 at 11:24:19AM -0700, David Daney wrote: > In atomic.h for atomic_add we have this gem: > > __asm__ __volatile__( > " .set mips3 \n" > "1: ll %0, %1 # atomic_add \n" > " addu %0, %2 \n" > " sc %0, %1 \n" > " beqz %0, 2f \n" > " .subsection 2 \n" > "2: b 1b \n" > " .previous \n" > " .set mips0 \n" > > > What is the purpose of the .subsection here? > > It will not affect branch prediction in the beqz as nothing happens in > .subsection 2. I'm not following. Most simple branch predictors will assume a backward branch to be a loop completion branch and thus predict it as taken while we assume that the SC instruction rarely fails no matter if spinlock, bit or atomic operation. It can even help on a CPU without branch prediction like the R4000 which kills the two instruction following the delay slot for a taken branch. > For spin locks it is clear that this technique can help, but for > atomic_add I don't think so. To make matters worse for some code the > subsection is going out of branch range. That problem should have be solved by building the kernel with -ffunction-sections. Other architectures needed -ffunction-sections for the same reason. Ralf From keshav.yadav2005@gmail.com Sun Aug 16 16:21:43 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 16 Aug 2009 16:21:51 +0200 (CEST) Received: from mail-yx0-f183.google.com ([209.85.210.183]:58776 "EHLO mail-yx0-f183.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492601AbZHPOVn convert rfc822-to-8bit (ORCPT ); Sun, 16 Aug 2009 16:21:43 +0200 Received: by yxe13 with SMTP id 13so3323328yxe.22 for ; Sun, 16 Aug 2009 07:21:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:in-reply-to:references :date:message-id:subject:from:to:content-type :content-transfer-encoding; bh=2naHafWRdP5iKAYt/BGC7nGv54Cn2yJIAcxxHqBiWtQ=; b=PFMMz/BhdMidGtpO3zAHUoLEz75AppTnnzvfMpDxsgio2+DJVIpB+kFz+bMynGoBDs DWUb6s0SjfhjAqxvA2zMzkpwGueWOBWwOfZAIXc+9aEJYlvpiI22frnN5Rw6kiSRa9E9 vPAsD4zzoyDiImhi5eT2W5wG+YFPmuc8ABTrw= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :content-type:content-transfer-encoding; b=hxMwgW2Emz4sO+S2w9UnO16VT0ssz8Hbt6E8Y0ovlAiqTSXeEw2GJdpz4NwXI0F1IH HFMqqJhBJL4LrnHCXrAmiZCKKeOij4i2yBEWkX/hHuyJYnkCU2B/jep4+ideFqqSVyR8 VSNZwz16cGh2ImtuyDK4rRTIfLP7rpEcGnQvc= MIME-Version: 1.0 Received: by 10.100.33.15 with SMTP id g15mr2710028ang.188.1250432497326; Sun, 16 Aug 2009 07:21:37 -0700 (PDT) In-Reply-To: <9651e57b0908160650s2b81e48bod8fc1d50c19c8e5b@mail.gmail.com> References: <9651e57b0908160650s2b81e48bod8fc1d50c19c8e5b@mail.gmail.com> Date: Sun, 16 Aug 2009 19:51:36 +0530 Message-ID: <9651e57b0908160721g4d9893bfrcd1afcb66f3b28d1@mail.gmail.com> Subject: Fwd: mips 16 bit compilation lead to crash From: keshav yadav To: linux-mips@linux-mips.org Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23903 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: keshav.yadav2005@gmail.com Precedence: bulk X-list: linux-mips ---------- Forwarded message ---------- From: keshav yadav Date: Sun, Aug 16, 2009 at 7:20 PM Subject: mips 16 bit compilation lead to crash To: gcc-help@gcc.gnu.org, gcc-help@gnu.org Hi all, I want to use MIPS 16 bit instruction similar to ARM thumb mode. But i am getting error #mips-gcc   -mips16   -o test.o test.c /tmp/ccJFGlL0.s: Assembler messages: /tmp/ccJFGlL0.s:17: Internal error! Assertion failure in macro_build_lui at ../../gas/config/tc-mips.c line 3142 1. Is there problem in toolchain i have made ? 2. is i am giving 16 bit option to gcc correctly. Regards Keshava From wilbur512@gmail.com Sun Aug 16 18:21:02 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 16 Aug 2009 18:21:09 +0200 (CEST) Received: from mail-yw0-f176.google.com ([209.85.211.176]:64844 "EHLO mail-yw0-f176.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492222AbZHPQVC convert rfc822-to-8bit (ORCPT ); Sun, 16 Aug 2009 18:21:02 +0200 Received: by ywh6 with SMTP id 6so3486261ywh.0 for ; Sun, 16 Aug 2009 09:20:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:date:message-id:subject :from:to:cc:content-type:content-transfer-encoding; bh=l+d+wDrfBUO4qjJjW6WTuhJINl/e0ndWnys6XtjAx5E=; b=B92PwIcwA/iHfB7tG0eJO+5WcW2F6BUJ8oCOGGkTpmWxykREDkfRXogt+g/OQWd1+J iY0kgahlm9TLcavW3Q+nJvbHXP7YnenbvCdK80qzTN6zXGIgZH0sVuAWpO3H01pLVXwf YHOCHfcMfW3aLMz+LeWBUgYwvJNHfx1n1JEzU= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:date:message-id:subject:from:to:cc:content-type :content-transfer-encoding; b=wzyc55R0WQ7U59X7EyfTFKpZaasUqU8X3EpoXrPwtu7yXeA14yGMO+pjZKvkh3oaLt XhI5U96fUD5d7lAQCb+kxfS/D1q4D2U3Y/GNUXREy0jMLclS47RIJG2LXpYagK0+Cu68 PnwfG/l4cLigpXeAcTj8cOyC/20MFTrheGxdM= MIME-Version: 1.0 Received: by 10.90.103.10 with SMTP id a10mr2199337agc.2.1250439656254; Sun, 16 Aug 2009 09:20:56 -0700 (PDT) Date: Mon, 17 Aug 2009 00:20:56 +0800 Message-ID: Subject: kexec on mips failed From: "wilbur.chan" To: nschichan@freebox.fr Cc: linux-mips@linux-mips.org Content-Type: text/plain; charset=GB2312 Content-Transfer-Encoding: 8BIT Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23904 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wilbur512@gmail.com Precedence: bulk X-list: linux-mips Hi,Nicolas, I've got some problem with kexec on mips32... in your code for kexec on mips32, there is a relocate_new_kernel function . In the end of this function , it jump to kexec_start_address by 'j s1' Because I changed the kexec-tools code ,in the hope that, it simplely passed the new kernel segment data into the old kernel.(so I didn't pass the command-line segment in, in my code, there is just one segment , segment[0] = kernel_data). So I need to change register s1 to the new kernel entry address, and jump to new kernel directly. In my vmlinux, the entry is 0x802b0000£¬so I let image->start = 0x2b0000£¬and invoke relocate_new_kernel. However, whether I changed kexec_start_address to 0x802b0000 or 0x2b0000 , the 'j s1' seemed taking no effect? (I wrote 88 to address0xa1230000 before 'j s1' , it succedd .I also wrote 78 to address 0xa1230000 in the beginning of head.S of the new kernel , but failed. And I reset the board to uboot mode, used 'md 0x802b0400' to display the new kernel in ram, it is identical to the objdump content of the vmlinux. So I guess, this problem lays in the failing of 'j 0x802b0000' or 'j 0x2b0000'. I don't know why 'j s1' failed , any suggestions about this ? Thank you very much. regads, Wilbur From f.fainelli@gmail.com Mon Aug 17 00:28:38 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 17 Aug 2009 00:28:45 +0200 (CEST) Received: from mail-ew0-f216.google.com ([209.85.219.216]:50342 "EHLO mail-ew0-f216.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492954AbZHPW2i (ORCPT ); Mon, 17 Aug 2009 00:28:38 +0200 Received: by ewy12 with SMTP id 12so2258487ewy.0 for ; Sun, 16 Aug 2009 15:28:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:sender:from:date:subject :mime-version:x-uid:x-length:to:cc:content-type :content-transfer-encoding:content-disposition:message-id; bh=BkBGvb0+pg0vVjQJw5BH6bokqCEP31dS2q5+Ck2d6O8=; b=X/wq7I7Ca3tjveaEWPdm7aRgr9Gl3hRwlCWw1SIG6SXU7Hm5ltl4ob3wFEmVB/Z0hp LkWLvV2JUlpAZuQGr2aLL7KUMtSW43idzG+tcA2e4Ey2Rwdk5j6wSa0b7lTKE1RgrwH4 7je/fTr3YPnANhhYZTcFeYUbDRVM0Y0xHaVXU= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:from:date:subject:mime-version:x-uid:x-length:to:cc :content-type:content-transfer-encoding:content-disposition :message-id; b=xjWBrDuAGDlADPzC4w5FuP5E2U7dBhWs5gYed2vrZv0hk3aUc4iIBHumzvnOBAbWSi YffrRbkldOo//5uPyLcRZHygvDcBrI/WnWwMD31lxhQSURUNd2YMpsVqN/yS9pphlES2 2bkcpBgSZtWEQf8+gZOMoI2KG5kGloM09NNp0= Received: by 10.211.152.7 with SMTP id e7mr438511ebo.3.1250461711087; Sun, 16 Aug 2009 15:28:31 -0700 (PDT) Received: from lenovo.mimichou.home (florian.mimichou.net [82.241.112.26]) by mx.google.com with ESMTPS id 10sm6410197eyz.51.2009.08.16.15.28.29 (version=TLSv1/SSLv3 cipher=RC4-MD5); Sun, 16 Aug 2009 15:28:30 -0700 (PDT) From: Florian Fainelli Date: Mon, 17 Aug 2009 00:28:24 +0200 Subject: [PATCH 1/2] au1000: fix build failure for db1x00 configured for Au1100 SoC MIME-Version: 1.0 X-UID: 1223 X-Length: 2089 To: ralf Baechle Cc: linux-mips@linux-mips.org, Manuel Lauss Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Content-Disposition: inline Message-Id: <200908170028.27210.florian@openwrt.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23905 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips Hi Ralf, This patch should apply to both -master and -queue. Thanks ! -- From: Florian Fainelli Subject: [PATCH 1/2] au1000: fix build failure for db1x00 configured for Au1100 SoC This patch fixes the following warning, which becomes an error due to -Werror to be turned on: CC arch/mips/alchemy/common/gpiolib-au1000.o cc1: warnings being treated as errors arch/mips/alchemy/common/gpiolib-au1000.c: In function 'au1100_gpio2_to_irq': /home/florian/dev/kernel/linux-queue/arch/mips/include/asm/mach-au1x00/gpio-au1000.h:107: warning: control reaches end of non-void function Signed-off-by: Florian Fainelli --- diff --git a/arch/mips/include/asm/mach-au1x00/gpio-au1000.h b/arch/mips/include/asm/mach-au1x00/gpio-au1000.h index 127d4ed..4d54d40 100644 --- a/arch/mips/include/asm/mach-au1x00/gpio-au1000.h +++ b/arch/mips/include/asm/mach-au1x00/gpio-au1000.h @@ -104,6 +104,8 @@ static inline int au1100_gpio2_to_irq(int gpio) if ((gpio >= 8) && (gpio <= 15)) return MAKE_IRQ(0, 29); /* shared GPIO208_215 */ + + return -ENXIO; } #ifdef CONFIG_SOC_AU1100 From f.fainelli@gmail.com Mon Aug 17 00:29:02 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 17 Aug 2009 00:29:10 +0200 (CEST) Received: from mail-ew0-f216.google.com ([209.85.219.216]:59861 "EHLO mail-ew0-f216.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1493148AbZHPW2l (ORCPT ); Mon, 17 Aug 2009 00:28:41 +0200 Received: by ewy12 with SMTP id 12so2258545ewy.0 for ; Sun, 16 Aug 2009 15:28:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:sender:from:date:subject :mime-version:x-uid:x-length:to:cc:content-type :content-transfer-encoding:content-disposition:message-id; bh=9ymzJ8vMW8QIOT9DCBg5i4qS14k6TMsy8kXQnxXpP2M=; b=JfXZTwR/AP5JRoMtS0v2xWF/j1atmSJeOAXWOKuQi7xgrTBTUyjbTX+pF/fSuooRdc 21RxSuruOKwmqTZACYerSzHjjNe3/qj52lvRrzgBM0dZyBYjfcO5Yzekpw3fh45ibo6S 8pi5l+RjbpkQQI7YakeUX4DeMR1ImGueDmIDw= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:from:date:subject:mime-version:x-uid:x-length:to:cc :content-type:content-transfer-encoding:content-disposition :message-id; b=PW7jfb3j1Dvw6Ce99QJ25+wOVQilW6hNfKLPQCpI7OI9YQtm8/2/PzEVVP2+0vB8ha dzPWlfIG8J90eshx1NZGa877+Z/p0L1hCYxo2lFniDDh2Fzoc68ERvO9h11yYHtEB5dG Pj/jZsviL4UrJj9zqe7wdajdYsDIuEzEjenMA= Received: by 10.210.136.15 with SMTP id j15mr2373260ebd.68.1250461715565; Sun, 16 Aug 2009 15:28:35 -0700 (PDT) Received: from lenovo.mimichou.home (florian.mimichou.net [82.241.112.26]) by mx.google.com with ESMTPS id 5sm8224107eyh.56.2009.08.16.15.28.33 (version=TLSv1/SSLv3 cipher=RC4-MD5); Sun, 16 Aug 2009 15:28:34 -0700 (PDT) From: Florian Fainelli Date: Mon, 17 Aug 2009 00:28:30 +0200 Subject: [PATCH 2/2] mtx-1: fix build failures when PCI is disabled MIME-Version: 1.0 X-UID: 1224 X-Length: 1500 To: Ralf Baechle Cc: linux-mips@linux-mips.org, Manuel Lauss Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Content-Disposition: inline Message-Id: <200908170028.32023.florian@openwrt.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23906 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips When PCI is disabled the board_pci_idsel symbol cannot be resolved since it is declared in arch/mips/pci/pci-au1000.c which is not compiled. Signed-off-by: Florian Fainelli --- diff --git a/arch/mips/alchemy/mtx-1/board_setup.c b/arch/mips/alchemy/mtx-1/board_setup.c index cc32c69..c803732 100644 --- a/arch/mips/alchemy/mtx-1/board_setup.c +++ b/arch/mips/alchemy/mtx-1/board_setup.c @@ -85,7 +85,9 @@ void __init board_setup(void) alchemy_gpio_direction_output(211, 1); /* green on */ alchemy_gpio_direction_output(212, 0); /* red off */ +#ifdef CONFIG_PCI board_pci_idsel = mtx1_pci_idsel; +#endif printk(KERN_INFO "4G Systems MTX-1 Board\n"); } From f.fainelli@gmail.com Mon Aug 17 01:05:46 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 17 Aug 2009 01:05:53 +0200 (CEST) Received: from mail-ew0-f216.google.com ([209.85.219.216]:39344 "EHLO mail-ew0-f216.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1493197AbZHPXFq (ORCPT ); Mon, 17 Aug 2009 01:05:46 +0200 Received: by ewy12 with SMTP id 12so2271668ewy.0 for ; Sun, 16 Aug 2009 16:05:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:sender:from:date:subject :mime-version:x-uid:x-length:to:cc:content-type :content-transfer-encoding:content-disposition:message-id; bh=EErtHiEoR2wwl0x5zdMI/pR+93J4d2P1SiEZF/bzH6A=; b=QwHgAL4K2e8ImYs8oLUVaPQDDGaV6K+d7nqYMQgegdsJoxukhozsAwLzDH3w1jAo9L y01Cbwlz2UTy2PprGOXUhDLedzJFz9qSZxjrn+BKMPb7HwGsGYPIwjF/o+nWJXbkb1tB ah7LU+v8G36g5tReOfu6tMIq6plccnJESZCyk= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:from:date:subject:mime-version:x-uid:x-length:to:cc :content-type:content-transfer-encoding:content-disposition :message-id; b=PcXF8HQMQhCUlXn24z/EwANi9divKV9CoD7MXCZBv4qOkSNUo/CTAQ+dXAGrFqbeHO 57jDkYTiJ8lkKIupDUJqqC7wAMA+DFX+AxWqP9X66b+VrWc/L6UOMSUSI8PMfLMRoJJP t+Sq/zxizkBdBJKaCOOwQFnINEL368Y5wHv8Y= Received: by 10.210.36.10 with SMTP id j10mr6235968ebj.30.1250463941283; Sun, 16 Aug 2009 16:05:41 -0700 (PDT) Received: from lenovo.mimichou.home (florian.mimichou.net [82.241.112.26]) by mx.google.com with ESMTPS id 10sm9289654eyd.25.2009.08.16.16.05.40 (version=TLSv1/SSLv3 cipher=RC4-MD5); Sun, 16 Aug 2009 16:05:41 -0700 (PDT) From: Florian Fainelli Date: Mon, 17 Aug 2009 01:05:35 +0200 Subject: [PATCH 1/2] alchemy: add au1000-eth platform device MIME-Version: 1.0 X-UID: 1242 X-Length: 20937 To: Ralf Baechle Cc: linux-mips@linux-mips.org, Manuel Lauss , David Miller , netdev@vger.kernel.org, Sergei Shtylyov Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Content-Disposition: inline Message-Id: <200908170105.38154.florian@openwrt.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23907 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips This patch adds the board code to register a per-board au1000-eth platform device to be used wit the au1000-eth platform driver in a subsequent patch. Note that the au1000-eth driver knows about the default driver settings such that we do not need to pass any platform_data informations in most cases except db1x00. Signed-off-by: Florian Fainelli --- diff --git a/arch/mips/alchemy/devboards/db1x00/Makefile b/arch/mips/alchemy/devboards/db1x00/Makefile index 432241a..532a214 100644 --- a/arch/mips/alchemy/devboards/db1x00/Makefile +++ b/arch/mips/alchemy/devboards/db1x00/Makefile @@ -5,4 +5,4 @@ # Makefile for the Alchemy Semiconductor DBAu1xx0 boards. # -obj-y := board_setup.o irqmap.o +obj-y := board_setup.o irqmap.o platform.o diff --git a/arch/mips/alchemy/devboards/db1x00/platform.c b/arch/mips/alchemy/devboards/db1x00/platform.c new file mode 100644 index 0000000..df0d68a --- /dev/null +++ b/arch/mips/alchemy/devboards/db1x00/platform.c @@ -0,0 +1,101 @@ +/* + * Db1x00 platform devices registration + * + * Copyright (C) 2009, Florian Fainelli + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include + +#include +#include + +static struct resource au1xxx_eth0_resources[] = { +#if defined(CONFIG_SOC_AU1000) + MAC_RES(AU1000_ETH0_BASE, AU1000_MAC0_ENABLE, AU1000_MAC0_DMA_INT), +#elif defined(CONFIG_SOC_AU1100) + MAC_RES(AU1100_ETH0_BASE, AU1100_MAC0_ENABLE, AU1100_MAC0_DMA_INT), +#elif defined(CONFIG_SOC_AU1550) + MAC_RES(AU1550_ETH0_BASE, AU1550_MAC0_ENABLE, AU1550_MAC0_DMA_INT), +#elif defined(CONFIG_SOC_AU1500) + MAC_RES(AU1500_ETH0_BASE, AU1500_MAC0_ENABLE, AU1500_MAC0_DMA_INT), +#endif +}; + +static struct resource au1xxx_eth1_resources[] = { +#if defined(CONFIG_SOC_AU1000) + MAC_RES(AU1000_ETH1_BASE, AU1000_MAC1_ENABLE, AU1000_MAC1_DMA_INT), +#elif defined(CONFIG_SOC_AU1550) + MAC_RES(AU1550_ETH1_BASE, AU1550_MAC1_ENABLE, AU1550_MAC1_DMA_INT), +#elif defined(CONFIG_SOC_AU1500) + MAC_RES(AU1500_ETH1_BASE, AU1500_MAC1_ENABLE, AU1500_MAC1_DMA_INT), +#endif +}; + +/* Except for Bosporus, default is to search for a PHY on MAC0 */ +static struct au1000_eth_platform_data au1xxx_eth0_platform_data = { + .phy1_search_mac0 = 1, +}; + +static struct platform_device db1x00_eth0 = { + .name = "au1000-eth", + .id = 0, + .num_resources = ARRAY_SIZE(au1xxx_eth0_resources), + .resource = au1xxx_eth0_resources, +. .dev.platform_data = &au1xxx_eth0_platform_data, +}; + +#ifndef CONFIG_SOC_AU1100 +static struct platform_device db1x00_eth1 = { + .name = "au1000-eth", + .id = 1, + .num_resources = ARRAY_SIZE(au1xxx_eth1_resources), + .resource = au1xxx_eth1_resources, +}; +#endif + +static struct platform_device *db1x00_devs[] = { + &db1x00_eth0, +}; + +static int __init db1x00_register_devices(void) +{ +#ifdef CONFIG_MIPS_BOSPORUS + /* + * Micrel/Kendin 5 port switch attached to MAC0, + * MAC0 is associated with PHY address 5 (== WAN port) + * MAC1 is not associated with any PHY, since it's connected directly + * to the switch. + * no interrupts are used + */ + au1xxx_eth0_platform_data.phy1_search_mac0 = 0; + au1xxx_eth0_platform_data.phy_static_config = 1; + au1xxx_eth0_platform_data.phy_addr = 5; + au1xxx_eth0_platform_data.phy_busid = 0; +#endif + +#ifndef CONFIG_SOC_AU1100 + int ni; + + ni = (int)((au_readl(SYS_PINFUNC) & (u32)(SYS_PF_NI2)) >> 4); + if (!(ni + 1)) + platform_device_register(&db1x00_eth1); +#endif + + return platform_add_devices(db1x00_devs, ARRAY_SIZE(db1x00_devs)); +} +arch_initcall(db1x00_register_devices); diff --git a/arch/mips/alchemy/devboards/pb1000/Makefile b/arch/mips/alchemy/devboards/pb1000/Makefile index 97c6615..38d11bb 100644 --- a/arch/mips/alchemy/devboards/pb1000/Makefile +++ b/arch/mips/alchemy/devboards/pb1000/Makefile @@ -5,4 +5,4 @@ # Makefile for the Alchemy Semiconductor Pb1000 board. # -obj-y := board_setup.o +obj-y := board_setup.o platform.o diff --git a/arch/mips/alchemy/devboards/pb1000/platform.c b/arch/mips/alchemy/devboards/pb1000/platform.c new file mode 100644 index 0000000..621e71c --- /dev/null +++ b/arch/mips/alchemy/devboards/pb1000/platform.c @@ -0,0 +1,58 @@ +/* + * PB1000 platform devices registration + * + * Copyright (C) 2009, Florian Fainelli + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include + +#include +#include + +static struct resource au1xxx_eth0_resources[] = { + MAC_RES(AU1000_ETH0_BASE, AU1000_MAC0_ENABLE, AU1000_MAC0_DMA_INT), +}; + +static struct resource au1xxx_eth1_resources[] = { + MAC_RES(AU1000_ETH1_BASE, AU1000_MAC1_ENABLE, AU1000_MAC1_DMA_INT), +}; + +static struct platform_device pb1000_eth0 = { + .name = "au1000-eth", + .id = 0, + .num_resources = ARRAY_SIZE(au1xxx_eth0_resources), + .resource = au1xxx_eth1_resources, +}; + +static struct platform_device pb1000_eth1 = { + .name = "au1000-eth", + .id = 1, + .num_resources = ARRAY_SIZE(au1xxx_eth1_resources), + .resource = au1xxx_eth1_resources, +}; + +static struct platform_device *pb1000_devs[] = { + &pb1000_eth0, + &pb1000_eth1, +}; + +static int __init pb1000_register_devices(void) +{ + return platform_add_devices(pb1000_devs, ARRAY_SIZE(pb1000_devs)); +} +arch_initcall(pb1000_register_devices); diff --git a/arch/mips/alchemy/devboards/pb1100/Makefile b/arch/mips/alchemy/devboards/pb1100/Makefile index c586dd7..7e3756c 100644 --- a/arch/mips/alchemy/devboards/pb1100/Makefile +++ b/arch/mips/alchemy/devboards/pb1100/Makefile @@ -5,4 +5,4 @@ # Makefile for the Alchemy Semiconductor Pb1100 board. # -obj-y := board_setup.o +obj-y := board_setup.o platform.o diff --git a/arch/mips/alchemy/devboards/pb1100/platform.c b/arch/mips/alchemy/devboards/pb1100/platform.c new file mode 100644 index 0000000..9ff939c --- /dev/null +++ b/arch/mips/alchemy/devboards/pb1100/platform.c @@ -0,0 +1,47 @@ +/* + * PB1100 platform devices registration + * + * Copyright (C) 2009, Florian Fainelli + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include + +#include +#include + +static struct resource au1xxx_eth0_resources[] = { + MAC_RES(AU1100_ETH0_BASE, AU1100_MAC0_ENABLE, AU1100_MAC0_DMA_INT), +}; + +static struct platform_device pb1100_eth0 = { + .name = "au1000-eth", + .id = 0, + .num_resources = ARRAY_SIZE(au1xxx_eth0_resources), + .resource = au1xxx_eth0_resources, +}; + +static struct platform_device *pb1100_devs[] = { + &pb1100_eth0, +}; + +static int __init pb1100_register_devices(void) +{ + return platform_add_devices(pb1100_devs, ARRAY_SIZE(pb1100_devs)); +} + +arch_initcall(pb1100_register_devices); diff --git a/arch/mips/alchemy/devboards/pb1500/Makefile b/arch/mips/alchemy/devboards/pb1500/Makefile index 173b419..e83b151 100644 --- a/arch/mips/alchemy/devboards/pb1500/Makefile +++ b/arch/mips/alchemy/devboards/pb1500/Makefile @@ -5,4 +5,4 @@ # Makefile for the Alchemy Semiconductor Pb1500 board. # -obj-y := board_setup.o +obj-y := board_setup.o platform.o diff --git a/arch/mips/alchemy/devboards/pb1500/platform.c b/arch/mips/alchemy/devboards/pb1500/platform.c new file mode 100644 index 0000000..98dbe8f --- /dev/null +++ b/arch/mips/alchemy/devboards/pb1500/platform.c @@ -0,0 +1,59 @@ +/* + * PB1500 platform devices registration + * + * Copyright (C) 2009, Florian Fainelli + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include + +#include +#include + +static struct resource au1xxx_eth0_resources[] = { + MAC_RES(AU1500_ETH0_BASE, AU1500_MAC0_ENABLE, AU1500_MAC0_DMA_INT), +}; + +static struct resource au1xxx_eth1_resources[] = { + MAC_RES(AU1500_ETH1_BASE, AU1500_MAC1_ENABLE, AU1500_MAC1_DMA_INT), +}; + +static struct platform_device pb1500_eth0 = { + .name = "au1000-eth", + .id = 0, + .num_resources = ARRAY_SIZE(au1xxx_eth0_resources), + .resource = au1xxx_eth0_resources, +}; + +static struct platform_device pb1500_eth1 = { + .name = "au1000-eth", + .id = 1, + .num_resources = ARRAY_SIZE(au1xxx_eth1_resources), + .resource = au1xxx_eth1_resources, +}; + +static struct platform_device *pb1500_devs[] = { + &pb1500_eth0, + &pb1500_eth1, +}; + +static int __init pb1500_register_devices(void) +{ + return platform_add_devices(pb1500_devs, ARRAY_SIZE(pb1500_devs)); +} + +arch_initcall(pb1500_register_devices); diff --git a/arch/mips/alchemy/devboards/pb1550/Makefile b/arch/mips/alchemy/devboards/pb1550/Makefile index cff95bc..9661b6e 100644 --- a/arch/mips/alchemy/devboards/pb1550/Makefile +++ b/arch/mips/alchemy/devboards/pb1550/Makefile @@ -5,4 +5,4 @@ # Makefile for the Alchemy Semiconductor Pb1550 board. # -obj-y := board_setup.o +obj-y := board_setup.o platform.o diff --git a/arch/mips/alchemy/devboards/pb1550/platform.c b/arch/mips/alchemy/devboards/pb1550/platform.c new file mode 100644 index 0000000..c46f4ef --- /dev/null +++ b/arch/mips/alchemy/devboards/pb1550/platform.c @@ -0,0 +1,59 @@ +/* + * PB1550 platform devices registration + * + * Copyright (C) 2009, Florian Fainelli + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include + +#include +#include + +static struct resource au1xxx_eth0_resources[] = { + MAC_RES(AU1550_ETH0_BASE, AU1550_MAC0_ENABLE, AU1550_MAC0_DMA_INT), +}; + +static struct resource au1xxx_eth1_resources[] = { + MAC_RES(AU1550_ETH1_BASE, AU1550_MAC1_ENABLE, AU1550_MAC1_DMA_INT), +}; + +static struct platform_device pb1550_eth0 = { + .name = "au1000-eth", + .id = 0, + .num_resources = ARRAY_SIZE(au1xxx_eth0_resources), + .resource = au1xxx_eth0_resources, +}; + +static struct platform_device pb1550_eth1 = { + .name = "au1000-eth", + .id = 1, + .num_resources = ARRAY_SIZE(au1xxx_eth1_resources), + .resource = au1xxx_eth1_resources, +}; + +static struct platform_device *pb1550_devs[] = { + &pb1550_eth0, + &pb1550_eth1, +}; + +static int __init pb1550_register_devices(void) +{ + return platform_add_devices(pb1550_devs, ARRAY_SIZE(pb1550_devs)); +} + +arch_initcall(pb1550_register_devices); diff --git a/arch/mips/alchemy/mtx-1/platform.c b/arch/mips/alchemy/mtx-1/platform.c index e30e42a..30a7a56 100644 --- a/arch/mips/alchemy/mtx-1/platform.c +++ b/arch/mips/alchemy/mtx-1/platform.c @@ -28,6 +28,9 @@ #include #include +#include +#include + static struct gpio_keys_button mtx1_gpio_button[] = { { .gpio = 207, @@ -133,11 +136,23 @@ static struct platform_device mtx1_mtd = { .resource = &mtx1_mtd_resource, }; +static struct resource au1xxx_eth0_resources[] = { + MAC_RES(AU1500_ETH0_BASE, AU1500_MAC0_ENABLE, AU1500_MAC0_DMA_INT), +}; + +static struct platform_device mtx1_eth = { + .name = "au1000-eth", + .id = 0, + .num_resources = ARRAY_SIZE(au1xxx_eth0_resources), + .resource = au1xxx_eth0_resources, +}; + static struct __initdata platform_device * mtx1_devs[] = { &mtx1_gpio_leds, &mtx1_wdt, &mtx1_button, &mtx1_mtd, + &mtx1_eth, }; static int __init mtx1_register_devices(void) diff --git a/arch/mips/alchemy/xxs1500/Makefile b/arch/mips/alchemy/xxs1500/Makefile index db3c526..375748f 100644 --- a/arch/mips/alchemy/xxs1500/Makefile +++ b/arch/mips/alchemy/xxs1500/Makefile @@ -6,3 +6,4 @@ # lib-y := init.o board_setup.o irqmap.o +obj-y := platform.o diff --git a/arch/mips/alchemy/xxs1500/platform.c b/arch/mips/alchemy/xxs1500/platform.c new file mode 100644 index 0000000..ef7f7b7 --- /dev/null +++ b/arch/mips/alchemy/xxs1500/platform.c @@ -0,0 +1,59 @@ +/* + * XXS1500 platform devices registration + * + * Copyright (C) 2009, Florian Fainelli + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include + +#include +#include + +static struct resource au1xxx_eth0_resources[] = { + MAC_RES(AU1500_ETH0_BASE, AU1500_MAC0_ENABLE, AU1500_MAC0_DMA_INT), +}; + +static struct resource au1xxx_eth1_resources[] = { + MAC_RES(AU1500_ETH1_BASE, AU1500_MAC1_ENABLE, AU1500_MAC1_DMA_INT), +}; + +static struct platform_device xxs1500_eth0 = { + .name = "au1000-eth", + .id = 0, + .num_resources = ARRAY_SIZE(au1xxx_eth0_resources), + .resource = au1xxx_eth0_resources, +}; + +static struct platform_device xxs1500_eth1 = { + .name = "au1000-eth", + .id = 1, + .num_resources = ARRAY_SIZE(au1xxx_eth1_resources), + .resource = au1xxx_eth1_resources, +}; + +static struct platform_device *xxs1500_devs[] = { + &xxs1500_eth0, + &xxs1500_eth1, +}; + +static int __init xxs1500_register_devices(void) +{ + return platform_add_devices(xxs1500_devs, ARRAY_SIZE(xxs1500_devs)); +} + +arch_initcall(xxs1500_register_devices); diff --git a/arch/mips/include/asm/mach-au1x00/au1xxx_eth.h b/arch/mips/include/asm/mach-au1x00/au1xxx_eth.h new file mode 100644 index 0000000..6d1543e --- /dev/null +++ b/arch/mips/include/asm/mach-au1x00/au1xxx_eth.h @@ -0,0 +1,33 @@ +#ifndef __AU1X00_ETH_DATA_H +#define __AU1X00_ETH_DATA_H + +/* Macro to help defining the Ethernet MAC resources */ +#define MAC_RES(_base, _enable, _irq) \ + { \ + .start = CPHYSADDR(_base), \ + .end = CPHYSADDR(_base + 0xffff), \ + .flags = IORESOURCE_MEM, \ + }, \ + { \ + .start = CPHYSADDR(_enable), \ + .end = CPHYSADDR(_enable + 0x4), \ + .flags = IORESOURCE_MEM, \ + }, \ + { \ + .start = _irq, \ + .end = _irq, \ + .flags = IORESOURCE_IRQ \ + } + +/* Platform specific PHY configuration passed to the MAC driver */ +struct au1000_eth_platform_data { + int phy_static_config; + int phy_search_highest_addr; + int phy1_search_mac0; + int phy_addr; + int phy_busid; + int phy_irq; +}; + +#endif /* __AU1X00_ETH_DATA_H */ + From f.fainelli@gmail.com Mon Aug 17 01:06:10 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 17 Aug 2009 01:06:17 +0200 (CEST) Received: from mail-ew0-f216.google.com ([209.85.219.216]:39344 "EHLO mail-ew0-f216.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1493201AbZHPXFr (ORCPT ); Mon, 17 Aug 2009 01:05:47 +0200 Received: by mail-ew0-f216.google.com with SMTP id 12so2271668ewy.0 for ; Sun, 16 Aug 2009 16:05:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:sender:from:date:subject :mime-version:x-uid:x-length:to:cc:content-type :content-transfer-encoding:content-disposition:message-id; bh=OSVzH1RtYnzlAd2kOLZkolUbsu0tu7B2O9ADnM4t3IU=; b=Oy2g3ga/xBWDvtnDeSQYjsZbwgKF39jpQSj3wIK2Qarp2NS7QTjwMVTkEQZ/Xjflh3 62/+aKyCQiUEjj3kKrKPDA/MiEbeN8gYRqrWVI8V1drsjnT79bz9sTtK3wB0wmrVpJCU dSUZ3sf9PR9pFtuq2QJBDPa815ThXZ1qaYZOk= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:from:date:subject:mime-version:x-uid:x-length:to:cc :content-type:content-transfer-encoding:content-disposition :message-id; b=v9S2XN/a2+HuruuQViVszcE7WdAtYFcD2sQd+5l80slN6p9fb5JcojbpXzwOL+gXWT dSw0jlSjkAZAZDgyA5u12GGfKBJN8Sq2rB0hANpPlUd7ETgEHAhN+ExFbB4R3IyQ0YjR NlxLzgW2XkunUjnDP3MLWbkHcGslz4UhV0/QU= Received: by 10.210.131.6 with SMTP id e6mr5521092ebd.88.1250463947497; Sun, 16 Aug 2009 16:05:47 -0700 (PDT) Received: from lenovo.mimichou.home (florian.mimichou.net [82.241.112.26]) by mx.google.com with ESMTPS id 10sm13904503eyz.21.2009.08.16.16.05.46 (version=TLSv1/SSLv3 cipher=RC4-MD5); Sun, 16 Aug 2009 16:05:47 -0700 (PDT) From: Florian Fainelli Date: Mon, 17 Aug 2009 01:05:44 +0200 Subject: [PATCH 2/2] au1000-eth: convert to a platform driver MIME-Version: 1.0 X-UID: 1243 X-Length: 20442 To: Ralf Baechle Cc: linux-mips@linux-mips.org, Manuel Lauss , David Miller , netdev@vger.kernel.org, Sergei Shtylyov Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Content-Disposition: inline Message-Id: <200908170105.45770.florian@openwrt.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23908 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips This patch converts the au1000-eth driver to become a full platform-driver as it ought to be. We now pass PHY-speficic configurations through platform_data but for compatibility the driver still assumes the default settings (search for PHY1 on MAC0) when no platform_data is passed. Tested on my MTX-1 board. Signed-off-by: Florian Fainelli --- diff --git a/drivers/net/au1000_eth.c b/drivers/net/au1000_eth.c index 2aab1eb..57cc4f6 100644 --- a/drivers/net/au1000_eth.c +++ b/drivers/net/au1000_eth.c @@ -54,6 +54,7 @@ #include #include #include +#include #include #include @@ -62,6 +63,7 @@ #include #include +#include #include #include "au1000_eth.h" @@ -111,15 +113,15 @@ struct au1000_private *au_macs[NUM_ETH_INTERFACES]; * * PHY detection algorithm * - * If AU1XXX_PHY_STATIC_CONFIG is undefined, the PHY setup is + * If phy_static_config is undefined, the PHY setup is * autodetected: * * mii_probe() first searches the current MAC's MII bus for a PHY, - * selecting the first (or last, if AU1XXX_PHY_SEARCH_HIGHEST_ADDR is + * selecting the first (or last, if phy_search_highest_addr is * defined) PHY address not already claimed by another netdev. * * If nothing was found that way when searching for the 2nd ethernet - * controller's PHY and AU1XXX_PHY1_SEARCH_ON_MAC0 is defined, then + * controller's PHY and phy1_search_mac0 is defined, then * the first MII bus is searched as well for an unclaimed PHY; this is * needed in case of a dual-PHY accessible only through the MAC0's MII * bus. @@ -128,9 +130,7 @@ struct au1000_private *au_macs[NUM_ETH_INTERFACES]; * controller is not registered to the network subsystem. */ -/* autodetection defaults */ -#undef AU1XXX_PHY_SEARCH_HIGHEST_ADDR -#define AU1XXX_PHY1_SEARCH_ON_MAC0 +/* autodetection defaults: phy1_search_mac0 */ /* static PHY setup * @@ -147,29 +147,6 @@ struct au1000_private *au_macs[NUM_ETH_INTERFACES]; * specific irq-map */ -#if defined(CONFIG_MIPS_BOSPORUS) -/* - * Micrel/Kendin 5 port switch attached to MAC0, - * MAC0 is associated with PHY address 5 (== WAN port) - * MAC1 is not associated with any PHY, since it's connected directly - * to the switch. - * no interrupts are used - */ -# define AU1XXX_PHY_STATIC_CONFIG - -# define AU1XXX_PHY0_ADDR 5 -# define AU1XXX_PHY0_BUSID 0 -# undef AU1XXX_PHY0_IRQ - -# undef AU1XXX_PHY1_ADDR -# undef AU1XXX_PHY1_BUSID -# undef AU1XXX_PHY1_IRQ -#endif - -#if defined(AU1XXX_PHY0_BUSID) && (AU1XXX_PHY0_BUSID > 0) -# error MAC0-associated PHY attached 2nd MACs MII bus not supported yet -#endif - static void enable_mac(struct net_device *dev, int force_reset) { unsigned long flags; @@ -389,67 +366,54 @@ static int mii_probe (struct net_device *dev) struct au1000_private *const aup = netdev_priv(dev); struct phy_device *phydev = NULL; -#if defined(AU1XXX_PHY_STATIC_CONFIG) - BUG_ON(aup->mac_id < 0 || aup->mac_id > 1); + if (aup->phy_static_config) { + BUG_ON(aup->mac_id < 0 || aup->mac_id > 1); - if(aup->mac_id == 0) { /* get PHY0 */ -# if defined(AU1XXX_PHY0_ADDR) - phydev = au_macs[AU1XXX_PHY0_BUSID]->mii_bus->phy_map[AU1XXX_PHY0_ADDR]; -# else - printk (KERN_INFO DRV_NAME ":%s: using PHY-less setup\n", - dev->name); - return 0; -# endif /* defined(AU1XXX_PHY0_ADDR) */ - } else if (aup->mac_id == 1) { /* get PHY1 */ -# if defined(AU1XXX_PHY1_ADDR) - phydev = au_macs[AU1XXX_PHY1_BUSID]->mii_bus->phy_map[AU1XXX_PHY1_ADDR]; -# else - printk (KERN_INFO DRV_NAME ":%s: using PHY-less setup\n", - dev->name); + if (aup->phy_addr) + phydev = aup->mii_bus->phy_map[aup->phy_addr]; + else + printk (KERN_INFO DRV_NAME ":%s: using PHY-less setup\n", + dev->name); return 0; -# endif /* defined(AU1XXX_PHY1_ADDR) */ - } - -#else /* defined(AU1XXX_PHY_STATIC_CONFIG) */ - int phy_addr; - - /* find the first (lowest address) PHY on the current MAC's MII bus */ - for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) - if (aup->mii_bus->phy_map[phy_addr]) { - phydev = aup->mii_bus->phy_map[phy_addr]; -# if !defined(AU1XXX_PHY_SEARCH_HIGHEST_ADDR) - break; /* break out with first one found */ -# endif - } - -# if defined(AU1XXX_PHY1_SEARCH_ON_MAC0) - /* try harder to find a PHY */ - if (!phydev && (aup->mac_id == 1)) { - /* no PHY found, maybe we have a dual PHY? */ - printk (KERN_INFO DRV_NAME ": no PHY found on MAC1, " - "let's see if it's attached to MAC0...\n"); - - BUG_ON(!au_macs[0]); - - /* find the first (lowest address) non-attached PHY on - * the MAC0 MII bus */ - for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) { - struct phy_device *const tmp_phydev = - au_macs[0]->mii_bus->phy_map[phy_addr]; - - if (!tmp_phydev) - continue; /* no PHY here... */ - - if (tmp_phydev->attached_dev) - continue; /* already claimed by MAC0 */ + } else { + int phy_addr; + + /* find the first (lowest address) PHY on the current MAC's MII bus */ + for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) + if (aup->mii_bus->phy_map[phy_addr]) { + phydev = aup->mii_bus->phy_map[phy_addr]; + if (!aup->phy_search_highest_addr) + break; /* break out with first one found */ + } - phydev = tmp_phydev; - break; /* found it */ + if (aup->phy1_search_mac0) { + /* try harder to find a PHY */ + if (!phydev && (aup->mac_id == 1)) { + /* no PHY found, maybe we have a dual PHY? */ + printk (KERN_INFO DRV_NAME ": no PHY found on MAC1, " + "let's see if it's attached to MAC0...\n"); + + /* find the first (lowest address) non-attached PHY on + * the MAC0 MII bus */ + for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) { + if (aup->mac_id == 1) + break; + struct phy_device *const tmp_phydev = + aup->mii_bus->phy_map[phy_addr]; + + if (!tmp_phydev) + continue; /* no PHY here... */ + + if (tmp_phydev->attached_dev) + continue; /* already claimed by MAC0 */ + + phydev = tmp_phydev; + break; /* found it */ + } + } } } -# endif /* defined(AU1XXX_PHY1_SEARCH_OTHER_BUS) */ -#endif /* defined(AU1XXX_PHY_STATIC_CONFIG) */ if (!phydev) { printk (KERN_ERR DRV_NAME ":%s: no PHY found\n", dev->name); return -1; @@ -577,31 +541,6 @@ setup_hw_rings(struct au1000_private *aup, u32 rx_base, u32 tx_base) } } -static struct { - u32 base_addr; - u32 macen_addr; - int irq; - struct net_device *dev; -} iflist[2] = { -#ifdef CONFIG_SOC_AU1000 - {AU1000_ETH0_BASE, AU1000_MAC0_ENABLE, AU1000_MAC0_DMA_INT}, - {AU1000_ETH1_BASE, AU1000_MAC1_ENABLE, AU1000_MAC1_DMA_INT} -#endif -#ifdef CONFIG_SOC_AU1100 - {AU1100_ETH0_BASE, AU1100_MAC0_ENABLE, AU1100_MAC0_DMA_INT} -#endif -#ifdef CONFIG_SOC_AU1500 - {AU1500_ETH0_BASE, AU1500_MAC0_ENABLE, AU1500_MAC0_DMA_INT}, - {AU1500_ETH1_BASE, AU1500_MAC1_ENABLE, AU1500_MAC1_DMA_INT} -#endif -#ifdef CONFIG_SOC_AU1550 - {AU1550_ETH0_BASE, AU1550_MAC0_ENABLE, AU1550_MAC0_DMA_INT}, - {AU1550_ETH1_BASE, AU1550_MAC1_ENABLE, AU1550_MAC1_DMA_INT} -#endif -}; - -static int num_ifs; - /* * ethtool operations */ @@ -1059,46 +998,59 @@ static const struct net_device_ops au1000_netdev_ops = { .ndo_change_mtu = eth_change_mtu, }; -static struct net_device * au1000_probe(int port_num) +static int __devinit au1000_probe(struct platform_device *pdev) { static unsigned version_printed = 0; struct au1000_private *aup = NULL; + struct au1000_eth_platform_data *pd; struct net_device *dev = NULL; db_dest_t *pDB, *pDBfree; - char ethaddr[6]; - int irq, i, err; - u32 base, macen; - - if (port_num >= NUM_ETH_INTERFACES) - return NULL; + int irq, i, err = 0; + struct resource *base, *macen; + DECLARE_MAC_BUF(ethaddr); + + base = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!base) { + printk(KERN_ERR DRV_NAME ": failed to retrieve base register\n"); + err = -ENODEV; + goto out; + } - base = CPHYSADDR(iflist[port_num].base_addr ); - macen = CPHYSADDR(iflist[port_num].macen_addr); - irq = iflist[port_num].irq; + macen = platform_get_resource(pdev, IORESOURCE_MEM, 1); + if (!macen) { + printk(KERN_ERR DRV_NAME ": failed to retrieve MAC Enable register\n"); + err = -ENODEV; + goto out; + } - if (!request_mem_region( base, MAC_IOSIZE, "Au1x00 ENET") || - !request_mem_region(macen, 4, "Au1x00 ENET")) - return NULL; + irq = platform_get_irq(pdev, 0); + if (irq < 0) { + printk(KERN_ERR DRV_NAME ": failed to retrieve IRQ\n"); + err = -ENODEV; + goto out; + } - if (version_printed++ == 0) - printk("%s version %s %s\n", DRV_NAME, DRV_VERSION, DRV_AUTHOR); + if (!request_mem_region(base->start, resource_size(base), pdev->name)) { + printk(KERN_ERR DRV_NAME ": failed to request memory region for base registers\n"); + err = -ENXIO; + goto out; + } + + if (!request_mem_region(macen->start, resource_size(macen), pdev->name)) { + printk(KERN_ERR DRV_NAME ": failed to request memory region for MAC enable register\n"); + err = -ENXIO; + goto err_request; + } dev = alloc_etherdev(sizeof(struct au1000_private)); if (!dev) { printk(KERN_ERR "%s: alloc_etherdev failed\n", DRV_NAME); - return NULL; - } - - if ((err = register_netdev(dev)) != 0) { - printk(KERN_ERR "%s: Cannot register net device, error %d\n", - DRV_NAME, err); - free_netdev(dev); - return NULL; + err = -ENOMEM; + goto err_alloc; } - printk("%s: Au1xx0 Ethernet found at 0x%x, irq %d\n", - dev->name, base, irq); - + SET_NETDEV_DEV(dev, &pdev->dev); + platform_set_drvdata(pdev, dev); aup = netdev_priv(dev); spin_lock_init(&aup->lock); @@ -1109,21 +1061,29 @@ static struct net_device * au1000_probe(int port_num) (NUM_TX_BUFFS + NUM_RX_BUFFS), &aup->dma_addr, 0); if (!aup->vaddr) { - free_netdev(dev); - release_mem_region( base, MAC_IOSIZE); - release_mem_region(macen, 4); - return NULL; + printk(KERN_ERR DRV_NAME ": failed to allocate data buffers\n"); + err = -ENOMEM; + goto err_vaddr; } /* aup->mac is the base address of the MAC's registers */ - aup->mac = (volatile mac_reg_t *)iflist[port_num].base_addr; + aup->mac = (volatile mac_reg_t *)ioremap_nocache(base->start, resource_size(base)); + if (!aup->mac) { + printk(KERN_ERR DRV_NAME ": failed to ioremap MAC registers\n"); + err = -ENXIO; + goto err_remap1; + } - /* Setup some variables for quick register address access */ - aup->enable = (volatile u32 *)iflist[port_num].macen_addr; - aup->mac_id = port_num; - au_macs[port_num] = aup; + /* Setup some variables for quick register address access */ + aup->enable = (volatile u32 *)ioremap_nocache(macen->start, resource_size(macen)); + if (!aup->enable) { + printk(KERN_ERR DRV_NAME ": failed to ioremap MAC enable register\n"); + err = -ENXIO; + goto err_remap2; + } + aup->mac_id = pdev->id; - if (port_num == 0) { + if (pdev->id == 0) { if (prom_get_ethernet_addr(ethaddr) == 0) memcpy(au1000_mac_addr, ethaddr, sizeof(au1000_mac_addr)); else { @@ -1133,7 +1093,7 @@ static struct net_device * au1000_probe(int port_num) } setup_hw_rings(aup, MAC0_RX_DMA_ADDR, MAC0_TX_DMA_ADDR); - } else if (port_num == 1) + } else if (pdev->id == 1) setup_hw_rings(aup, MAC1_RX_DMA_ADDR, MAC1_TX_DMA_ADDR); /* @@ -1141,14 +1101,37 @@ static struct net_device * au1000_probe(int port_num) * to match those that are printed on their stickers */ memcpy(dev->dev_addr, au1000_mac_addr, sizeof(au1000_mac_addr)); - dev->dev_addr[5] += port_num; + dev->dev_addr[5] += pdev->id; *aup->enable = 0; aup->mac_enabled = 0; + pd = pdev->dev.platform_data; + if (!pd) { + printk(KERN_INFO DRV_NAME ": no platform_data passed, PHY search on MAC0\n"); + aup->phy1_search_mac0 = 1; + } else { + aup->phy_static_config = pd->phy_static_config; + aup->phy_search_highest_addr = pd->phy_search_highest_addr; + aup->phy1_search_mac0 = pd->phy1_search_mac0; + aup->phy_addr = pd->phy_addr; + aup->phy_busid = pd->phy_busid; + aup->phy_irq = pd->phy_irq; + } + + if (aup->phy_busid && aup->phy_busid > 0) { + printk(KERN_ERR DRV_NAME ": MAC0-associated PHY attached 2nd MACs MII" + "bus not supported yet\n"); + err = -ENODEV; + goto err_mdiobus_alloc; + } + aup->mii_bus = mdiobus_alloc(); - if (aup->mii_bus == NULL) - goto err_out; + if (aup->mii_bus == NULL) { + printk(KERN_ERR DRV_NAME ": failed to allocate mdiobus structure\n"); + err = -ENOMEM; + goto err_mdiobus_alloc; + } aup->mii_bus->priv = dev; aup->mii_bus->read = au1000_mdiobus_read; @@ -1159,23 +1142,19 @@ static struct net_device * au1000_probe(int port_num) aup->mii_bus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL); for(i = 0; i < PHY_MAX_ADDR; ++i) aup->mii_bus->irq[i] = PHY_POLL; - /* if known, set corresponding PHY IRQs */ -#if defined(AU1XXX_PHY_STATIC_CONFIG) -# if defined(AU1XXX_PHY0_IRQ) - if (AU1XXX_PHY0_BUSID == aup->mac_id) - aup->mii_bus->irq[AU1XXX_PHY0_ADDR] = AU1XXX_PHY0_IRQ; -# endif -# if defined(AU1XXX_PHY1_IRQ) - if (AU1XXX_PHY1_BUSID == aup->mac_id) - aup->mii_bus->irq[AU1XXX_PHY1_ADDR] = AU1XXX_PHY1_IRQ; -# endif -#endif - mdiobus_register(aup->mii_bus); + if (aup->phy_static_config) + if (aup->phy_irq && aup->phy_busid == aup->mac_id) + aup->mii_bus->irq[aup->phy_addr] = aup->phy_irq; + + err = mdiobus_register(aup->mii_bus); + if (err) { + printk(KERN_ERR DRV_NAME " failed to register MDIO bus\n"); + goto err_mdiobus_reg; + } - if (mii_probe(dev) != 0) { + if (mii_probe(dev) != 0) goto err_out; - } pDBfree = NULL; /* setup the data buffer descriptors and attach a buffer to each one */ @@ -1207,7 +1186,7 @@ static struct net_device * au1000_probe(int port_num) aup->tx_db_inuse[i] = pDB; } - dev->base_addr = base; + dev->base_addr = base->start; dev->irq = irq; dev->netdev_ops = &au1000_netdev_ops; SET_ETHTOOL_OPS(dev, &au1000_ethtool_ops); @@ -1219,14 +1198,24 @@ static struct net_device * au1000_probe(int port_num) */ reset_mac(dev); - return dev; + err = register_netdev(dev); + if (err) { + printk(KERN_ERR DRV_NAME "%s: Cannot register net device, aborting.\n", + dev->name); + goto err_out; + } + + printk("%s: Au1xx0 Ethernet found at 0x%x, irq %d\n", + dev->name, base->start, irq); + if (version_printed++ == 0) + printk("%s version %s %s\n", DRV_NAME, DRV_VERSION, DRV_AUTHOR); + + return 0; err_out: - if (aup->mii_bus != NULL) { + if (aup->mii_bus != NULL) mdiobus_unregister(aup->mii_bus); - mdiobus_free(aup->mii_bus); - } - + /* here we should have a valid dev plus aup-> register addresses * so we can reset the mac properly.*/ reset_mac(dev); @@ -1239,67 +1228,84 @@ err_out: if (aup->tx_db_inuse[i]) ReleaseDB(aup, aup->tx_db_inuse[i]); } +err_mdiobus_reg: + mdiobus_free(aup->mii_bus); +err_mdiobus_alloc: + iounmap(aup->enable); +err_remap2: + iounmap(aup->mac); +err_remap1: dma_free_noncoherent(NULL, MAX_BUF_SIZE * (NUM_TX_BUFFS + NUM_RX_BUFFS), (void *)aup->vaddr, aup->dma_addr); - unregister_netdev(dev); +err_vaddr: free_netdev(dev); - release_mem_region( base, MAC_IOSIZE); - release_mem_region(macen, 4); - return NULL; +err_alloc: + release_mem_region(macen->start, resource_size(macen)); +err_request: + release_mem_region(base->start, resource_size(base)); +out: + return err; } -/* - * Setup the base address and interrupt of the Au1xxx ethernet macs - * based on cpu type and whether the interface is enabled in sys_pinfunc - * register. The last interface is enabled if SYS_PF_NI2 (bit 4) is 0. - */ -static int __init au1000_init_module(void) +static int __devexit au1000_remove(struct platform_device *pdev) { - int ni = (int)((au_readl(SYS_PINFUNC) & (u32)(SYS_PF_NI2)) >> 4); - struct net_device *dev; - int i, found_one = 0; + struct net_device *dev = platform_get_drvdata(pdev); + struct au1000_private *aup = netdev_priv(dev); + int i; + struct resource *base, *macen; - num_ifs = NUM_ETH_INTERFACES - ni; + platform_set_drvdata(pdev, NULL); + + unregister_netdev(dev); + mdiobus_unregister(aup->mii_bus); + mdiobus_free(aup->mii_bus); + + for (i = 0; i < NUM_RX_DMA; i++) + if (aup->rx_db_inuse[i]) + ReleaseDB(aup, aup->rx_db_inuse[i]); + + for (i = 0; i < NUM_TX_DMA; i++) + if (aup->tx_db_inuse[i]) + ReleaseDB(aup, aup->tx_db_inuse[i]); + + dma_free_noncoherent(NULL, MAX_BUF_SIZE * + (NUM_TX_BUFFS + NUM_RX_BUFFS), + (void *)aup->vaddr, aup->dma_addr); + + iounmap(aup->mac); + iounmap(aup->enable); + + base = platform_get_resource(pdev, IORESOURCE_MEM, 0); + release_mem_region(base->start, resource_size(base)); + + macen = platform_get_resource(pdev, IORESOURCE_MEM, 1); + release_mem_region(macen->start, resource_size(macen)); + + free_netdev(dev); - for(i = 0; i < num_ifs; i++) { - dev = au1000_probe(i); - iflist[i].dev = dev; - if (dev) - found_one++; - } - if (!found_one) - return -ENODEV; return 0; } -static void __exit au1000_cleanup_module(void) +static struct platform_driver au1000_eth_driver = { + .probe = au1000_probe, + .remove = __devexit_p(au1000_remove), + .driver = { + .name = "au1000-eth", + .owner = THIS_MODULE, + }, +}; +MODULE_ALIAS("platform:au1000-eth"); + + +static int __init au1000_init_module(void) { - int i, j; - struct net_device *dev; - struct au1000_private *aup; - - for (i = 0; i < num_ifs; i++) { - dev = iflist[i].dev; - if (dev) { - aup = netdev_priv(dev); - unregister_netdev(dev); - mdiobus_unregister(aup->mii_bus); - mdiobus_free(aup->mii_bus); - for (j = 0; j < NUM_RX_DMA; j++) - if (aup->rx_db_inuse[j]) - ReleaseDB(aup, aup->rx_db_inuse[j]); - for (j = 0; j < NUM_TX_DMA; j++) - if (aup->tx_db_inuse[j]) - ReleaseDB(aup, aup->tx_db_inuse[j]); - dma_free_noncoherent(NULL, MAX_BUF_SIZE * - (NUM_TX_BUFFS + NUM_RX_BUFFS), - (void *)aup->vaddr, aup->dma_addr); - release_mem_region(dev->base_addr, MAC_IOSIZE); - release_mem_region(CPHYSADDR(iflist[i].macen_addr), 4); - free_netdev(dev); - } - } + return platform_driver_register(&au1000_eth_driver); +} + +static void __exit au1000_exit_module(void) +{ + platform_driver_unregister(&au1000_eth_driver); } module_init(au1000_init_module); -module_exit(au1000_cleanup_module); +module_exit(au1000_exit_module); diff --git a/drivers/net/au1000_eth.h b/drivers/net/au1000_eth.h index 824ecd5..f9d29a2 100644 --- a/drivers/net/au1000_eth.h +++ b/drivers/net/au1000_eth.h @@ -108,6 +108,15 @@ struct au1000_private { struct phy_device *phy_dev; struct mii_bus *mii_bus; + /* PHY configuration */ + int phy_static_config; + int phy_search_highest_addr; + int phy1_search_mac0; + + int phy_addr; + int phy_busid; + int phy_irq; + /* These variables are just for quick access to certain regs addresses. */ volatile mac_reg_t *mac; /* mac registers */ volatile u32 *enable; /* address of MAC Enable Register */ From David.Daney@caviumnetworks.com Mon Aug 17 18:20:16 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 17 Aug 2009 18:20:23 +0200 (CEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:13114 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492961AbZHQQUQ (ORCPT ); Mon, 17 Aug 2009 18:20:16 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,2,2,3503) id ; Mon, 17 Aug 2009 12:19:26 -0400 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Mon, 17 Aug 2009 09:19:25 -0700 Received: from dd1.caveonetworks.com ([64.169.86.201]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Mon, 17 Aug 2009 09:19:25 -0700 Message-ID: <4A89830B.40904@caviumnetworks.com> Date: Mon, 17 Aug 2009 09:19:23 -0700 From: David Daney User-Agent: Thunderbird 2.0.0.21 (X11/20090320) MIME-Version: 1.0 To: keshav yadav CC: linux-mips@linux-mips.org, binutils Subject: Re: Fwd: mips 16 bit compilation lead to crash References: <9651e57b0908160650s2b81e48bod8fc1d50c19c8e5b@mail.gmail.com> <9651e57b0908160721g4d9893bfrcd1afcb66f3b28d1@mail.gmail.com> In-Reply-To: <9651e57b0908160721g4d9893bfrcd1afcb66f3b28d1@mail.gmail.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 17 Aug 2009 16:19:25.0905 (UTC) FILETIME=[7D0BBC10:01CA1F56] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23909 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips The proper forum for this question is binutils@sourceware.org (now CCed). keshav yadav wrote: > ---------- Forwarded message ---------- > From: keshav yadav > Date: Sun, Aug 16, 2009 at 7:20 PM > Subject: mips 16 bit compilation lead to crash > To: gcc-help@gcc.gnu.org, gcc-help@gnu.org > > > Hi all, > > I want to use MIPS 16 bit instruction similar to ARM thumb mode. But i > am getting error > > #mips-gcc -mips16 -o test.o test.c > > /tmp/ccJFGlL0.s: Assembler messages: > /tmp/ccJFGlL0.s:17: Internal error! > Assertion failure in macro_build_lui at ../../gas/config/tc-mips.c line 3142 > > 1. Is there problem in toolchain i have made ? > 2. is i am giving 16 bit option to gcc correctly. > Your report is lacking important information: 1) Which versions of the tools are you using. 2) A self contained test case. (The contents of test.c). Because of those deficiencies, it is impossible to answer your questions. David Daney From ralf@linux-mips.org Tue Aug 18 14:23:38 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 18 Aug 2009 14:23:46 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:46926 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492689AbZHRMXi (ORCPT ); Tue, 18 Aug 2009 14:23:38 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id n7ICOSVt026465; Tue, 18 Aug 2009 13:24:28 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id n7ICORG9026463; Tue, 18 Aug 2009 13:24:27 +0100 Date: Tue, 18 Aug 2009 13:24:27 +0100 From: Ralf Baechle To: Maxime Bizon Cc: linux-mips@linux-mips.org, Florian Fainelli Subject: Re: More updates to bcm63xx Message-ID: <20090818122427.GA21399@linux-mips.org> References: <1244037747-27144-1-git-send-email-mbizon@freebox.fr> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1244037747-27144-1-git-send-email-mbizon@freebox.fr> User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23910 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Wed, Jun 03, 2009 at 04:02:19PM +0200, Maxime Bizon wrote: > Yet another list of cleanup and fixes for the bcm63xx tree, please > fold them into the existing patches. I folded all 8 patches into the existing patches for the linux-bcm63xx tree. Thanks! Ralf From mbizon@freebox.fr Tue Aug 18 16:31:37 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 18 Aug 2009 16:31:43 +0200 (CEST) Received: from smtp6-g21.free.fr ([212.27.42.6]:35124 "EHLO smtp6-g21.free.fr" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1493024AbZHRObh (ORCPT ); Tue, 18 Aug 2009 16:31:37 +0200 Received: from smtp6-g21.free.fr (localhost [127.0.0.1]) by smtp6-g21.free.fr (Postfix) with ESMTP id BDC7AE080D4; Tue, 18 Aug 2009 16:31:30 +0200 (CEST) Received: from [213.228.1.107] (sakura.staff.proxad.net [213.228.1.107]) by smtp6-g21.free.fr (Postfix) with ESMTP id D345CE080AB; Tue, 18 Aug 2009 16:31:27 +0200 (CEST) Subject: Re: More updates to bcm63xx From: Maxime Bizon Reply-To: mbizon@freebox.fr To: Ralf Baechle Cc: linux-mips@linux-mips.org, Florian Fainelli In-Reply-To: <20090818122427.GA21399@linux-mips.org> References: <1244037747-27144-1-git-send-email-mbizon@freebox.fr> <20090818122427.GA21399@linux-mips.org> Content-Type: text/plain Organization: Freebox Date: Tue, 18 Aug 2009 16:31:27 +0200 Message-Id: <1250605887.23717.188.camel@sakura.staff.proxad.net> Mime-Version: 1.0 X-Mailer: Evolution 2.26.1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23911 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mbizon@freebox.fr Precedence: bulk X-list: linux-mips On Tue, 2009-08-18 at 13:24 +0100, Ralf Baechle wrote: Hi Ralf, > I folded all 8 patches into the existing patches for the linux-bcm63xx > tree The bcm63xx tree seems wrong. The patch from Florian that adds support for 6338 & 6345 is merged with commit BCM63XX: Add integrated ethernet mac support. The final patch that adds the board code is gone. -- Maxime From ralf@linux-mips.org Tue Aug 18 16:36:17 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 18 Aug 2009 16:36:24 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:51897 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1493024AbZHROgR (ORCPT ); Tue, 18 Aug 2009 16:36:17 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id n7IEb79e002354; Tue, 18 Aug 2009 15:37:07 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id n7IEb7Sh002352; Tue, 18 Aug 2009 15:37:07 +0100 Date: Tue, 18 Aug 2009 15:37:07 +0100 From: Ralf Baechle To: Maxime Bizon Cc: linux-mips@linux-mips.org, Florian Fainelli Subject: Re: More updates to bcm63xx Message-ID: <20090818143707.GA2327@linux-mips.org> References: <1244037747-27144-1-git-send-email-mbizon@freebox.fr> <20090818122427.GA21399@linux-mips.org> <1250605887.23717.188.camel@sakura.staff.proxad.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1250605887.23717.188.camel@sakura.staff.proxad.net> User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23912 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Tue, Aug 18, 2009 at 04:31:27PM +0200, Maxime Bizon wrote: > > I folded all 8 patches into the existing patches for the linux-bcm63xx > > tree > > The bcm63xx tree seems wrong. > > The patch from Florian that adds support for 6338 & 6345 is merged with > commit BCM63XX: Add integrated ethernet mac support. > > The final patch that adds the board code is gone. I'm just folding some of the patches together. I'm aware something went wrong with the ethernet support and I'm sorting that out now. Ralf From sshtylyov@ru.mvista.com Tue Aug 18 16:55:16 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 18 Aug 2009 16:55:24 +0200 (CEST) Received: from h155.mvista.com ([63.81.120.155]:48211 "EHLO imap.sh.mvista.com" rhost-flags-OK-FAIL-OK-FAIL) by ftp.linux-mips.org with ESMTP id S1493047AbZHROzQ (ORCPT ); Tue, 18 Aug 2009 16:55:16 +0200 Received: from [192.168.11.189] (unknown [10.150.0.9]) by imap.sh.mvista.com (Postfix) with ESMTP id 3CC5B3ECA; Tue, 18 Aug 2009 07:55:12 -0700 (PDT) Message-ID: <4A8AC125.3020602@ru.mvista.com> Date: Tue, 18 Aug 2009 18:56:37 +0400 From: Sergei Shtylyov Organization: MontaVista Software Inc. User-Agent: Mozilla/5.0 (X11; U; Linux i686; rv:1.7.2) Gecko/20040803 X-Accept-Language: ru, en-us, en-gb MIME-Version: 1.0 To: Florian Fainelli Cc: Ralf Baechle , linux-mips@linux-mips.org, Manuel Lauss , David Miller , netdev@vger.kernel.org Subject: Re: [PATCH 1/2] alchemy: add au1000-eth platform device References: <200908170105.38154.florian@openwrt.org> In-Reply-To: <200908170105.38154.florian@openwrt.org> Content-Type: text/plain; charset=us-ascii; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23913 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sshtylyov@ru.mvista.com Precedence: bulk X-list: linux-mips Hello. Florian Fainelli wrote: > This patch adds the board code to register a per-board au1000-eth > platform device to be used wit the au1000-eth platform driver in a > subsequent patch. Note that the au1000-eth driver knows about the > default driver settings such that we do not need to pass any > platform_data informations in most cases except db1x00. Sigh, NAK... Please don't register the SoC device per board, do it in alchemy/common/platfrom.c and find a way to pass the board specific platform data from the board file there instead -- something like arch/arm/mach-davinci/usb.c does. > Signed-off-by: Florian Fainelli [...] > diff --git a/arch/mips/include/asm/mach-au1x00/au1xxx_eth.h b/arch/mips/include/asm/mach-au1x00/au1xxx_eth.h > new file mode 100644 > index 0000000..6d1543e > --- /dev/null > +++ b/arch/mips/include/asm/mach-au1x00/au1xxx_eth.h > @@ -0,0 +1,33 @@ > +#ifndef __AU1X00_ETH_DATA_H > +#define __AU1X00_ETH_DATA_H > + > +/* Macro to help defining the Ethernet MAC resources */ > +#define MAC_RES(_base, _enable, _irq) \ > + { \ > + .start = CPHYSADDR(_base), \ > + .end = CPHYSADDR(_base + 0xffff), \ > + .flags = IORESOURCE_MEM, \ > + }, \ > + { \ > + .start = CPHYSADDR(_enable), \ > + .end = CPHYSADDR(_enable + 0x4), \ s/4/3/. WBR, Sergei From f.fainelli@gmail.com Tue Aug 18 18:01:51 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 18 Aug 2009 18:01:58 +0200 (CEST) Received: from mail-ew0-f225.google.com ([209.85.219.225]:49445 "EHLO mail-ew0-f225.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492963AbZHRQBv convert rfc822-to-8bit (ORCPT ); Tue, 18 Aug 2009 18:01:51 +0200 Received: by ewy25 with SMTP id 25so37643879ewy.33 for ; Tue, 18 Aug 2009 09:01:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:sender:from:to:subject:date :user-agent:cc:references:in-reply-to:mime-version:content-type :content-transfer-encoding:content-disposition:message-id; bh=YdMb4ehlYr8SCHj5XZgHZ0sc4wxAxWaeU4sISMCcFPI=; b=Isj0lEwtkmDgRClx0DrRVKNXYEjPK7Hom75VoRSiWwIeOzshphEH4+Xy2Fcyhfb1Jc zGEzYXuwKDqfn2lrC6R8xNLYQLAuN8wxWV6EhOWXt7O2GzPLHp6IoxKA9Dw0mXBqsbCk 9tJ7ryOt5/FZlf2VqkZuw4hMqDHn3jzEWGnLU= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:from:to:subject:date:user-agent:cc:references:in-reply-to :mime-version:content-type:content-transfer-encoding :content-disposition:message-id; b=mWFr/sOcAPqBujxJCDKeid/5X37+2XMcCRGmz3fyqqvtwyINLaxP+3vPd2tK/F4OIG /S0pd5zW1XDlwiZrISfGyF5VoE+G4ttzPN/tWARM6DkMWfH9qnZPlOGGgo0rWm8rfcAw cH4ZfIbstjh4adpPrbPzmM6fMhVW/unguia60= Received: by 10.210.68.18 with SMTP id q18mr3882183eba.77.1250611304750; Tue, 18 Aug 2009 09:01:44 -0700 (PDT) Received: from florian.lab.openpattern.org (lab.openpattern.org [82.240.16.241]) by mx.google.com with ESMTPS id 10sm266478eyz.1.2009.08.18.09.01.44 (version=TLSv1/SSLv3 cipher=RC4-MD5); Tue, 18 Aug 2009 09:01:44 -0700 (PDT) From: Florian Fainelli To: Sergei Shtylyov Subject: Re: [PATCH 1/2] alchemy: add au1000-eth platform device Date: Tue, 18 Aug 2009 18:01:40 +0200 User-Agent: KMail/1.9.9 Cc: Ralf Baechle , linux-mips@linux-mips.org, Manuel Lauss , David Miller , netdev@vger.kernel.org References: <200908170105.38154.florian@openwrt.org> <4A8AC125.3020602@ru.mvista.com> In-Reply-To: <4A8AC125.3020602@ru.mvista.com> MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 8BIT Content-Disposition: inline Message-Id: <200908181801.41602.florian@openwrt.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23914 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips Le Tuesday 18 August 2009 16:56:37 Sergei Shtylyov, vous avez écrit : > Hello. > > Florian Fainelli wrote: > > This patch adds the board code to register a per-board au1000-eth > > platform device to be used wit the au1000-eth platform driver in a > > subsequent patch. Note that the au1000-eth driver knows about the > > default driver settings such that we do not need to pass any > > platform_data informations in most cases except db1x00. > > Sigh, NAK... > Please don't register the SoC device per board, do it in > alchemy/common/platfrom.c and find a way to pass the board specific > platform data from the board file there instead -- something like > arch/arm/mach-davinci/usb.c does. Ok, like I promised, this was the per-board device registration. Do you prefer something like this: -- From fd75b7c7fa3c05c21122c43e43260d2785475a79 Mon Sep 17 00:00:00 2001 From: Florian Fainelli Date: Tue, 18 Aug 2009 17:53:21 +0200 Subject: [PATCH] alchemy: add au1000-eth platform device (v2) This patch makes the board code register the au1000-eth platform device. The au1000-eth platform data can be overriden with the au1xxx_override_eth0_cfg function like it has to be done for the Bosporus board. Changes from v1: - remove per-board platform.c file - add an override function to pass custom eth0 platform_data PHY settings Signed-off-by: Florian Fainelli --- diff --git a/arch/mips/alchemy/common/platform.c b/arch/mips/alchemy/common/platform.c index 117f99f..559294a 100644 --- a/arch/mips/alchemy/common/platform.c +++ b/arch/mips/alchemy/common/platform.c @@ -19,6 +19,7 @@ #include #include #include +#include #define PORT(_base, _irq) \ { \ @@ -331,6 +332,76 @@ static struct platform_device pbdb_smbus_device = { }; #endif +/* Macro to help defining the Ethernet MAC resources */ +#define MAC_RES(_base, _enable, _irq) \ + { \ + .start = CPHYSADDR(_base), \ + .end = CPHYSADDR(_base + 0xffff), \ + .flags = IORESOURCE_MEM, \ + }, \ + { \ + .start = CPHYSADDR(_enable), \ + .end = CPHYSADDR(_enable + 0x3), \ + .flags = IORESOURCE_MEM, \ + }, \ + { \ + .start = _irq, \ + .end = _irq, \ + .flags = IORESOURCE_IRQ \ + } + +static struct resource au1xxx_eth0_resources[] = { +#if defined(CONFIG_SOC_AU1000) + MAC_RES(AU1000_ETH0_BASE, AU1000_MAC0_ENABLE, AU1000_MAC0_DMA_INT), +#elif defined(CONFIG_SOC_AU1100) + MAC_RES(AU1100_ETH0_BASE, AU1100_MAC0_ENABLE, AU1100_MAC0_DMA_INT), +#elif defined(CONFIG_SOC_AU1550) + MAC_RES(AU1550_ETH0_BASE, AU1550_MAC0_ENABLE, AU1550_MAC0_DMA_INT), +#elif defined(CONFIG_SOC_AU1500) + MAC_RES(AU1500_ETH0_BASE, AU1500_MAC0_ENABLE, AU1500_MAC0_DMA_INT), +#endif +}; + +static struct resource au1xxx_eth1_resources[] = { +#if defined(CONFIG_SOC_AU1000) + MAC_RES(AU1000_ETH1_BASE, AU1000_MAC1_ENABLE, AU1000_MAC1_DMA_INT), +#elif defined(CONFIG_SOC_AU1550) + MAC_RES(AU1550_ETH1_BASE, AU1550_MAC1_ENABLE, AU1550_MAC1_DMA_INT), +#elif defined(CONFIG_SOC_AU1500) + MAC_RES(AU1500_ETH1_BASE, AU1500_MAC1_ENABLE, AU1500_MAC1_DMA_INT), +#endif +}; + +static struct au1000_eth_platform_data au1xxx_eth0_platform_data = { + .phy1_search_mac0 = 1, +}; + +static struct platform_device au1xxx_eth0_device = { + .name = "au1000-eth", + .id = 0, + .num_resources = ARRAY_SIZE(au1xxx_eth0_resources), + .resource = au1xxx_eth0_resources, + .dev.platform_data = &au1xxx_eth0_platform_data, +}; + +#ifndef CONFIG_SOC_AU1100 +static struct platform_device au1xxx_eth1_device = { + .name = "au1000-eth", + .id = 1, + .num_resources = ARRAY_SIZE(au1xxx_eth1_resources), + .resource = au1xxx_eth1_resources, +}; +#endif + +void __init au1xxx_override_eth0_cfg(struct au1000_eth_platform_data *eth_data) +{ + if (!eth_data) + return; + + memcpy(&au1xxx_eth0_platform_data, eth_data, + sizeof(struct au1000_eth_platform_data)); +} + static struct platform_device *au1xxx_platform_devices[] __initdata = { &au1xx0_uart_device, &au1xxx_usb_ohci_device, @@ -351,17 +422,25 @@ static struct platform_device *au1xxx_platform_devices[] __initdata = { #ifdef SMBUS_PSC_BASE &pbdb_smbus_device, #endif + &au1xxx_eth0_device, }; static int __init au1xxx_platform_init(void) { unsigned int uartclk = get_au1x00_uart_baud_base() * 16; - int i; + int i, ni; /* Fill up uartclk. */ for (i = 0; au1x00_uart_data[i].flags; i++) au1x00_uart_data[i].uartclk = uartclk; + /* Register second MAC if enabled in pinfunc */ +#ifndef CONFIG_SOC_AU1100 + ni = (int)((au_readl(SYS_PINFUNC) & (u32)(SYS_PF_NI2)) >> 4); + if (!(ni + 1)) + platform_device_register(&au1xxx_eth1_device); +#endif + return platform_add_devices(au1xxx_platform_devices, ARRAY_SIZE(au1xxx_platform_devices)); } diff --git a/arch/mips/alchemy/devboards/db1x00/board_setup.c b/arch/mips/alchemy/devboards/db1x00/board_setup.c index de30d8e..4d2d32c 100644 --- a/arch/mips/alchemy/devboards/db1x00/board_setup.c +++ b/arch/mips/alchemy/devboards/db1x00/board_setup.c @@ -32,6 +32,7 @@ #include #include +#include #include @@ -134,6 +135,22 @@ void __init board_setup(void) printk(KERN_INFO "AMD Alchemy Au1100/Db1100 Board\n"); #endif #ifdef CONFIG_MIPS_BOSPORUS + struct au1000_eth_platform_data eth0_pdata; + + /* + * Micrel/Kendin 5 port switch attached to MAC0, + * MAC0 is associated with PHY address 5 (== WAN port) + * MAC1 is not associated with any PHY, since it's connected directly + * to the switch. + * no interrupts are used + */ + eth0_pdata.phy1_search_mac0 = 0; + eth0_pdata.phy_static_config = 1; + eth0_pdata.phy_addr = 5; + eth0_pdata.phy_busid = 0; + + au1xxx_override_eth0_cfg(ð0_pdata); + printk(KERN_INFO "AMD Alchemy Bosporus Board\n"); #endif #ifdef CONFIG_MIPS_MIRAGE diff --git a/arch/mips/include/asm/mach-au1x00/au1xxx_eth.h b/arch/mips/include/asm/mach-au1x00/au1xxx_eth.h new file mode 100644 index 0000000..876187e --- /dev/null +++ b/arch/mips/include/asm/mach-au1x00/au1xxx_eth.h @@ -0,0 +1,17 @@ +#ifndef __AU1X00_ETH_DATA_H +#define __AU1X00_ETH_DATA_H + +/* Platform specific PHY configuration passed to the MAC driver */ +struct au1000_eth_platform_data { + int phy_static_config; + int phy_search_highest_addr; + int phy1_search_mac0; + int phy_addr; + int phy_busid; + int phy_irq; +}; + +void __init au1xxx_override_eth0_cfg(struct au1000_eth_platform_data *eth_data); + +#endif /* __AU1X00_ETH_DATA_H */ + -- 1.6.3.rc3 From David.Daney@caviumnetworks.com Thu Aug 20 21:38:17 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 20 Aug 2009 21:38:23 +0200 (CEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:46584 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492793AbZHTTiR (ORCPT ); Thu, 20 Aug 2009 21:38:17 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,2,2,3503) id ; Thu, 20 Aug 2009 15:36:29 -0400 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Thu, 20 Aug 2009 12:35:59 -0700 Received: from dd1.caveonetworks.com ([64.169.86.201]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Thu, 20 Aug 2009 12:35:58 -0700 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.2/8.14.2) with ESMTP id n7KJZseJ006082; Thu, 20 Aug 2009 12:35:54 -0700 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.2/8.14.2/Submit) id n7KJZrpJ006080; Thu, 20 Aug 2009 12:35:53 -0700 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: David Daney Subject: [PATCH] MIPS: Octeon: Check all CCAs in cvmx_write_csr. Date: Thu, 20 Aug 2009 12:35:53 -0700 Message-Id: <1250796953-6056-1-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.6.0.6 X-OriginalArrivalTime: 20 Aug 2009 19:35:59.0017 (UTC) FILETIME=[71871190:01CA21CD] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23915 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips The current code only checks CCA of 0 when deciding if a dummy read is needed. Since the kernel can (and does) use other CCAs we need to mask out the CCA bits from the address. Since the address constant now fits in 16 bits, there is an added benefit that smaller code is generated. Signed-off-by: David Daney --- arch/mips/include/asm/octeon/cvmx.h | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/mips/include/asm/octeon/cvmx.h b/arch/mips/include/asm/octeon/cvmx.h index e31e3fe..9d9381e 100644 --- a/arch/mips/include/asm/octeon/cvmx.h +++ b/arch/mips/include/asm/octeon/cvmx.h @@ -271,7 +271,7 @@ static inline void cvmx_write_csr(uint64_t csr_addr, uint64_t val) * what RSL read we do, so we choose CVMX_MIO_BOOT_BIST_STAT * because it is fast and harmless. */ - if ((csr_addr >> 40) == (0x800118)) + if (((csr_addr >> 40) & 0x7ffff) == (0x118)) cvmx_read64(CVMX_MIO_BOOT_BIST_STAT); } -- 1.6.0.6 From David.Daney@caviumnetworks.com Thu Aug 20 23:10:05 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 20 Aug 2009 23:10:11 +0200 (CEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:40089 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492863AbZHTVKF (ORCPT ); Thu, 20 Aug 2009 23:10:05 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,2,2,3503) id ; Thu, 20 Aug 2009 17:08:09 -0400 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Thu, 20 Aug 2009 14:07:35 -0700 Received: from dd1.caveonetworks.com ([64.169.86.201]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Thu, 20 Aug 2009 14:07:35 -0700 Message-ID: <4A8DBB17.5020301@caviumnetworks.com> Date: Thu, 20 Aug 2009 14:07:35 -0700 From: David Daney User-Agent: Thunderbird 2.0.0.21 (X11/20090320) MIME-Version: 1.0 To: ralf@linux-mips.org, mpm@selenic.com, herbert@gondor.apana.org.au CC: linux-mips@linux-mips.org, akpm@linux-foundation.org, linux-kernel@vger.kernel.org Subject: [PATCH 0/2] New hardware RNG for Octeon SOCs (v2) Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 20 Aug 2009 21:07:35.0521 (UTC) FILETIME=[3DB30510:01CA21DA] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23916 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Based on feedback from AKPM, I have a new revision of the Octeon hardware RNG driver. The changes from v1 are minor, just eliminating some bogus casting by accessing the driver state by embedding struct hwrng in the driver data, which is now accessed with the container_of() trick. The first patch adds some port definitions and the octeon_rng platform device. The second is the driver. Since Octeon is a mips port, we might want to merge both patches via Ralf's linux-mips.org tree. David Daney (2): MIPS: Octeon: Add hardware RNG platform device. hw_random: Add hardware RNG for Octeon SOCs. arch/mips/cavium-octeon/setup.c | 43 ++++++++ arch/mips/include/asm/octeon/cvmx-rnm-defs.h | 88 +++++++++++++++ drivers/char/hw_random/Kconfig | 13 +++ drivers/char/hw_random/Makefile | 1 + drivers/char/hw_random/octeon-rng.c | 147 ++++++++++++++++++++++++++ 5 files changed, 292 insertions(+), 0 deletions(-) create mode 100644 arch/mips/include/asm/octeon/cvmx-rnm-defs.h create mode 100644 drivers/char/hw_random/octeon-rng.c From David.Daney@caviumnetworks.com Thu Aug 20 23:12:03 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 20 Aug 2009 23:12:09 +0200 (CEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:41080 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492863AbZHTVMD (ORCPT ); Thu, 20 Aug 2009 23:12:03 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,2,2,3503) id ; Thu, 20 Aug 2009 17:11:14 -0400 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Thu, 20 Aug 2009 14:10:28 -0700 Received: from dd1.caveonetworks.com ([64.169.86.201]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Thu, 20 Aug 2009 14:10:28 -0700 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.2/8.14.2) with ESMTP id n7KLAOwb006557; Thu, 20 Aug 2009 14:10:24 -0700 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.2/8.14.2/Submit) id n7KLAOO9006556; Thu, 20 Aug 2009 14:10:24 -0700 From: David Daney To: ralf@linux-mips.org, mpm@selenic.com, herbert@gondor.apana.org.au Cc: linux-mips@linux-mips.org, akpm@linux-foundation.org, linux-kernel@vger.kernel.org, David Daney Subject: [PATCH 2/2] hw_random: Add hardware RNG for Octeon SOCs. Date: Thu, 20 Aug 2009 14:10:23 -0700 Message-Id: <1250802623-6526-2-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.6.0.6 In-Reply-To: <4A8DBB17.5020301@caviumnetworks.com> References: <4A8DBB17.5020301@caviumnetworks.com> X-OriginalArrivalTime: 20 Aug 2009 21:10:28.0850 (UTC) FILETIME=[A502ED20:01CA21DA] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23917 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Signed-off-by: David Daney --- drivers/char/hw_random/Kconfig | 13 +++ drivers/char/hw_random/Makefile | 1 + drivers/char/hw_random/octeon-rng.c | 147 +++++++++++++++++++++++++++++++++++ 3 files changed, 161 insertions(+), 0 deletions(-) create mode 100644 drivers/char/hw_random/octeon-rng.c diff --git a/drivers/char/hw_random/Kconfig b/drivers/char/hw_random/Kconfig index ce66a70..121b782 100644 --- a/drivers/char/hw_random/Kconfig +++ b/drivers/char/hw_random/Kconfig @@ -126,6 +126,19 @@ config HW_RANDOM_OMAP If unsure, say Y. +config HW_RANDOM_OCTEON + tristate "Octeon Random Number Generator support" + depends on HW_RANDOM && CPU_CAVIUM_OCTEON + default HW_RANDOM + ---help--- + This driver provides kernel-side support for the Random Number + Generator hardware found on Octeon processors. + + To compile this driver as a module, choose M here: the + module will be called octeon-rng. + + If unsure, say Y. + config HW_RANDOM_PASEMI tristate "PA Semi HW Random Number Generator support" depends on HW_RANDOM && PPC_PASEMI diff --git a/drivers/char/hw_random/Makefile b/drivers/char/hw_random/Makefile index 676828b..5eeb130 100644 --- a/drivers/char/hw_random/Makefile +++ b/drivers/char/hw_random/Makefile @@ -17,3 +17,4 @@ obj-$(CONFIG_HW_RANDOM_PASEMI) += pasemi-rng.o obj-$(CONFIG_HW_RANDOM_VIRTIO) += virtio-rng.o obj-$(CONFIG_HW_RANDOM_TX4939) += tx4939-rng.o obj-$(CONFIG_HW_RANDOM_MXC_RNGA) += mxc-rnga.o +obj-$(CONFIG_HW_RANDOM_OCTEON) += octeon-rng.o diff --git a/drivers/char/hw_random/octeon-rng.c b/drivers/char/hw_random/octeon-rng.c new file mode 100644 index 0000000..54b0d9b --- /dev/null +++ b/drivers/char/hw_random/octeon-rng.c @@ -0,0 +1,147 @@ +/* + * Hardware Random Number Generator support for Cavium Networks + * Octeon processor family. + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2009 Cavium Networks + */ + +#include +#include +#include +#include +#include +#include + +#include +#include + +struct octeon_rng { + struct hwrng ops; + void __iomem *control_status; + void __iomem *result; +}; + +static int octeon_rng_init(struct hwrng *rng) +{ + union cvmx_rnm_ctl_status ctl; + struct octeon_rng *p = container_of(rng, struct octeon_rng, ops); + + ctl.u64 = 0; + ctl.s.ent_en = 1; /* Enable the entropy source. */ + ctl.s.rng_en = 1; /* Enable the RNG hardware. */ + cvmx_write_csr((u64)p->control_status, ctl.u64); + return 0; +} + +static void octeon_rng_cleanup(struct hwrng *rng) +{ + union cvmx_rnm_ctl_status ctl; + struct octeon_rng *p = container_of(rng, struct octeon_rng, ops); + + ctl.u64 = 0; + /* Disable everything. */ + cvmx_write_csr((u64)p->control_status, ctl.u64); +} + +static int octeon_rng_data_read(struct hwrng *rng, u32 *data) +{ + struct octeon_rng *p = container_of(rng, struct octeon_rng, ops); + + *data = cvmx_read64_uint32((u64)p->result); + return sizeof(u32); +} + +static int __devinit octeon_rng_probe(struct platform_device *pdev) +{ + struct resource *res_ports; + struct resource *res_result; + struct octeon_rng *rng; + int ret; + struct hwrng ops = { + .name = "octeon", + .init = octeon_rng_init, + .cleanup = octeon_rng_cleanup, + .data_read = octeon_rng_data_read + }; + + rng = devm_kzalloc(&pdev->dev, sizeof(*rng), GFP_KERNEL); + if (!rng) + return -ENOMEM; + + res_ports = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res_ports) + goto err_ports; + + res_result = platform_get_resource(pdev, IORESOURCE_MEM, 1); + if (!res_result) + goto err_ports; + + + rng->control_status = devm_ioremap_nocache(&pdev->dev, + res_ports->start, + sizeof(u64)); + if (!rng->control_status) + goto err_ports; + + rng->result = devm_ioremap_nocache(&pdev->dev, + res_result->start, + sizeof(u64)); + if (!rng->result) + goto err_r; + + rng->ops = ops; + + dev_set_drvdata(&pdev->dev, &rng->ops); + ret = hwrng_register(&rng->ops); + if (ret) + goto err; + + dev_info(&pdev->dev, "Octeon Random Number Generator\n"); + + return 0; +err: + devm_iounmap(&pdev->dev, rng->control_status); +err_r: + devm_iounmap(&pdev->dev, rng->result); +err_ports: + devm_kfree(&pdev->dev, rng); + return -ENOENT; +} + +static int __exit octeon_rng_remove(struct platform_device *pdev) +{ + struct hwrng *rng = dev_get_drvdata(&pdev->dev); + + hwrng_unregister(rng); + + return 0; +} + +static struct platform_driver octeon_rng_driver = { + .driver = { + .name = "octeon_rng", + .owner = THIS_MODULE, + }, + .probe = octeon_rng_probe, + .remove = __exit_p(octeon_rng_remove), +}; + +static int __init octeon_rng_mod_init(void) +{ + return platform_driver_register(&octeon_rng_driver); +} + +static void __exit octeon_rng_mod_exit(void) +{ + platform_driver_unregister(&octeon_rng_driver); +} + +module_init(octeon_rng_mod_init); +module_exit(octeon_rng_mod_exit); + +MODULE_AUTHOR("David Daney"); +MODULE_LICENSE("GPL"); -- 1.6.0.6 From David.Daney@caviumnetworks.com Thu Aug 20 23:12:27 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 20 Aug 2009 23:12:35 +0200 (CEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:41122 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492897AbZHTVMI (ORCPT ); Thu, 20 Aug 2009 23:12:08 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,2,2,3503) id ; Thu, 20 Aug 2009 17:11:14 -0400 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Thu, 20 Aug 2009 14:10:28 -0700 Received: from dd1.caveonetworks.com ([64.169.86.201]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Thu, 20 Aug 2009 14:10:28 -0700 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.2/8.14.2) with ESMTP id n7KLAOhr006553; Thu, 20 Aug 2009 14:10:24 -0700 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.2/8.14.2/Submit) id n7KLANUr006552; Thu, 20 Aug 2009 14:10:23 -0700 From: David Daney To: ralf@linux-mips.org, mpm@selenic.com, herbert@gondor.apana.org.au Cc: linux-mips@linux-mips.org, akpm@linux-foundation.org, linux-kernel@vger.kernel.org, David Daney Subject: [PATCH 1/2] MIPS: Octeon: Add hardware RNG platform device. Date: Thu, 20 Aug 2009 14:10:22 -0700 Message-Id: <1250802623-6526-1-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.6.0.6 In-Reply-To: <4A8DBB17.5020301@caviumnetworks.com> References: <4A8DBB17.5020301@caviumnetworks.com> X-OriginalArrivalTime: 20 Aug 2009 21:10:28.0850 (UTC) FILETIME=[A502ED20:01CA21DA] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23918 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Add a platform device for the Octeon Random Number Generator (RNG). Signed-off-by: David Daney --- arch/mips/cavium-octeon/setup.c | 43 +++++++++++++ arch/mips/include/asm/octeon/cvmx-rnm-defs.h | 88 ++++++++++++++++++++++++++ 2 files changed, 131 insertions(+), 0 deletions(-) create mode 100644 arch/mips/include/asm/octeon/cvmx-rnm-defs.h diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c index bc0c869..d8cf674 100644 --- a/arch/mips/cavium-octeon/setup.c +++ b/arch/mips/cavium-octeon/setup.c @@ -33,6 +33,7 @@ #include #include +#include #ifdef CONFIG_CAVIUM_DECODE_RSL extern void cvmx_interrupt_rsl_decode(void); @@ -931,3 +932,45 @@ out: return ret; } device_initcall(octeon_cf_device_init); + +/* Octeon Random Number Generator. */ +static int __init octeon_rng_device_init(void) +{ + struct platform_device *pd; + int ret = 0; + + struct resource rng_resources[] = { + { + .flags = IORESOURCE_MEM, + .start = XKPHYS_TO_PHYS(CVMX_RNM_CTL_STATUS), + .end = XKPHYS_TO_PHYS(CVMX_RNM_CTL_STATUS) + 0xf + }, { + .flags = IORESOURCE_MEM, + .start = cvmx_build_io_address(8, 0), + .end = cvmx_build_io_address(8, 0) + 0x7 + } + }; + + pd = platform_device_alloc("octeon_rng", -1); + if (!pd) { + ret = -ENOMEM; + goto out; + } + + ret = platform_device_add_resources(pd, rng_resources, + ARRAY_SIZE(rng_resources)); + if (ret) + goto fail; + + ret = platform_device_add(pd); + if (ret) + goto fail; + + return ret; +fail: + platform_device_put(pd); + +out: + return ret; +} +device_initcall(octeon_rng_device_init); diff --git a/arch/mips/include/asm/octeon/cvmx-rnm-defs.h b/arch/mips/include/asm/octeon/cvmx-rnm-defs.h new file mode 100644 index 0000000..4586958 --- /dev/null +++ b/arch/mips/include/asm/octeon/cvmx-rnm-defs.h @@ -0,0 +1,88 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * along with this file; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +#ifndef __CVMX_RNM_DEFS_H__ +#define __CVMX_RNM_DEFS_H__ + +#include + +#define CVMX_RNM_BIST_STATUS \ + CVMX_ADD_IO_SEG(0x0001180040000008ull) +#define CVMX_RNM_CTL_STATUS \ + CVMX_ADD_IO_SEG(0x0001180040000000ull) + +union cvmx_rnm_bist_status { + uint64_t u64; + struct cvmx_rnm_bist_status_s { + uint64_t reserved_2_63:62; + uint64_t rrc:1; + uint64_t mem:1; + } s; + struct cvmx_rnm_bist_status_s cn30xx; + struct cvmx_rnm_bist_status_s cn31xx; + struct cvmx_rnm_bist_status_s cn38xx; + struct cvmx_rnm_bist_status_s cn38xxp2; + struct cvmx_rnm_bist_status_s cn50xx; + struct cvmx_rnm_bist_status_s cn52xx; + struct cvmx_rnm_bist_status_s cn52xxp1; + struct cvmx_rnm_bist_status_s cn56xx; + struct cvmx_rnm_bist_status_s cn56xxp1; + struct cvmx_rnm_bist_status_s cn58xx; + struct cvmx_rnm_bist_status_s cn58xxp1; +}; + +union cvmx_rnm_ctl_status { + uint64_t u64; + struct cvmx_rnm_ctl_status_s { + uint64_t reserved_9_63:55; + uint64_t ent_sel:4; + uint64_t exp_ent:1; + uint64_t rng_rst:1; + uint64_t rnm_rst:1; + uint64_t rng_en:1; + uint64_t ent_en:1; + } s; + struct cvmx_rnm_ctl_status_cn30xx { + uint64_t reserved_4_63:60; + uint64_t rng_rst:1; + uint64_t rnm_rst:1; + uint64_t rng_en:1; + uint64_t ent_en:1; + } cn30xx; + struct cvmx_rnm_ctl_status_cn30xx cn31xx; + struct cvmx_rnm_ctl_status_cn30xx cn38xx; + struct cvmx_rnm_ctl_status_cn30xx cn38xxp2; + struct cvmx_rnm_ctl_status_s cn50xx; + struct cvmx_rnm_ctl_status_s cn52xx; + struct cvmx_rnm_ctl_status_s cn52xxp1; + struct cvmx_rnm_ctl_status_s cn56xx; + struct cvmx_rnm_ctl_status_s cn56xxp1; + struct cvmx_rnm_ctl_status_s cn58xx; + struct cvmx_rnm_ctl_status_s cn58xxp1; +}; + +#endif -- 1.6.0.6 From f.fainelli@gmail.com Fri Aug 21 18:53:21 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 21 Aug 2009 18:53:27 +0200 (CEST) Received: from mail-bw0-f208.google.com ([209.85.218.208]:39778 "EHLO mail-bw0-f208.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492986AbZHUQxV convert rfc822-to-8bit (ORCPT ); Fri, 21 Aug 2009 18:53:21 +0200 Received: by bwz4 with SMTP id 4so781470bwz.0 for ; Fri, 21 Aug 2009 09:53:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:sender:from:to:subject:date :user-agent:cc:references:in-reply-to:mime-version:content-type :content-transfer-encoding:content-disposition:message-id; bh=MvflFqKE750wxTG2wYd7DcLpvFSYG4F/aKyYoB3+zZw=; b=GCWjS+sds9pHNudzTpozUSgZXHGKFOXSZWMwHaI28azb+DHaY0MmozVAAku0UkTQ1c BqzIeu2tzediGWw3khBCnl5NUyKGFLop/9vwAXHuGJXnMEJtcGfO9q+OvX/QgN2cJEF6 SfExLMxNcAQadIMdwKzzkKUzP1paQsfevHaLs= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:from:to:subject:date:user-agent:cc:references:in-reply-to :mime-version:content-type:content-transfer-encoding :content-disposition:message-id; b=AB2e0VufKyofR779y0+ydgLzL5nGaYwX7s2Yiu3o/jPfo6zJtdEXCiBnWHMKwOT6WM gE5ZLGe+N6gICNzXz6Nd4esqxq7kf3rMj3+Rt9nZS6TGP1+b8ARdRhX1j4QUSzYoi2rM WvrdB1N5vSH/KLbmhV+CU5vRdj/ntFj1a1r50= Received: by 10.103.76.29 with SMTP id d29mr581358mul.50.1250873595421; Fri, 21 Aug 2009 09:53:15 -0700 (PDT) Received: from ?192.168.250.6? ([85.233.201.131]) by mx.google.com with ESMTPS id 23sm10989494mum.35.2009.08.21.09.53.09 (version=TLSv1/SSLv3 cipher=RC4-MD5); Fri, 21 Aug 2009 09:53:13 -0700 (PDT) From: Florian Fainelli To: Sergei Shtylyov Subject: Re: [PATCH 1/2] alchemy: add au1000-eth platform device Date: Fri, 21 Aug 2009 18:53:07 +0200 User-Agent: KMail/1.9.9 Cc: Ralf Baechle , linux-mips@linux-mips.org, Manuel Lauss , David Miller , netdev@vger.kernel.org References: <200908170105.38154.florian@openwrt.org> <4A8AC125.3020602@ru.mvista.com> <200908181801.41602.florian@openwrt.org> In-Reply-To: <200908181801.41602.florian@openwrt.org> MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 8BIT Content-Disposition: inline Message-Id: <200908211853.07969.florian@openwrt.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23919 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips Le Tuesday 18 August 2009 18:01:40 Florian Fainelli, vous avez écrit : > Le Tuesday 18 August 2009 16:56:37 Sergei Shtylyov, vous avez écrit : > > Hello. > > > > Florian Fainelli wrote: > > > This patch adds the board code to register a per-board au1000-eth > > > platform device to be used wit the au1000-eth platform driver in a > > > subsequent patch. Note that the au1000-eth driver knows about the > > > default driver settings such that we do not need to pass any > > > platform_data informations in most cases except db1x00. > > > > Sigh, NAK... > > Please don't register the SoC device per board, do it in > > alchemy/common/platfrom.c and find a way to pass the board specific > > platform data from the board file there instead -- something like > > arch/arm/mach-davinci/usb.c does. > > Ok, like I promised, this was the per-board device registration. Do you > prefer something like this: -- > From fd75b7c7fa3c05c21122c43e43260d2785475a79 Mon Sep 17 00:00:00 2001 > From: Florian Fainelli > Date: Tue, 18 Aug 2009 17:53:21 +0200 > Subject: [PATCH] alchemy: add au1000-eth platform device (v2) > > This patch makes the board code register the au1000-eth > platform device. The au1000-eth platform data can be > overriden with the au1xxx_override_eth0_cfg function > like it has to be done for the Bosporus board. Sergei, any comments on that version? What about you Manuel? > > Changes from v1: > - remove per-board platform.c file > - add an override function to pass custom eth0 platform_data PHY settings > > Signed-off-by: Florian Fainelli > --- > diff --git a/arch/mips/alchemy/common/platform.c > b/arch/mips/alchemy/common/platform.c index 117f99f..559294a 100644 > --- a/arch/mips/alchemy/common/platform.c > +++ b/arch/mips/alchemy/common/platform.c > @@ -19,6 +19,7 @@ > #include > #include > #include > +#include > > #define PORT(_base, _irq) \ > { \ > @@ -331,6 +332,76 @@ static struct platform_device pbdb_smbus_device = { > }; > #endif > > +/* Macro to help defining the Ethernet MAC resources */ > +#define MAC_RES(_base, _enable, _irq) \ > + { \ > + .start = CPHYSADDR(_base), \ > + .end = CPHYSADDR(_base + 0xffff), \ > + .flags = IORESOURCE_MEM, \ > + }, \ > + { \ > + .start = CPHYSADDR(_enable), \ > + .end = CPHYSADDR(_enable + 0x3), \ > + .flags = IORESOURCE_MEM, \ > + }, \ > + { \ > + .start = _irq, \ > + .end = _irq, \ > + .flags = IORESOURCE_IRQ \ > + } > + > +static struct resource au1xxx_eth0_resources[] = { > +#if defined(CONFIG_SOC_AU1000) > + MAC_RES(AU1000_ETH0_BASE, AU1000_MAC0_ENABLE, AU1000_MAC0_DMA_INT), > +#elif defined(CONFIG_SOC_AU1100) > + MAC_RES(AU1100_ETH0_BASE, AU1100_MAC0_ENABLE, AU1100_MAC0_DMA_INT), > +#elif defined(CONFIG_SOC_AU1550) > + MAC_RES(AU1550_ETH0_BASE, AU1550_MAC0_ENABLE, AU1550_MAC0_DMA_INT), > +#elif defined(CONFIG_SOC_AU1500) > + MAC_RES(AU1500_ETH0_BASE, AU1500_MAC0_ENABLE, AU1500_MAC0_DMA_INT), > +#endif > +}; > + > +static struct resource au1xxx_eth1_resources[] = { > +#if defined(CONFIG_SOC_AU1000) > + MAC_RES(AU1000_ETH1_BASE, AU1000_MAC1_ENABLE, AU1000_MAC1_DMA_INT), > +#elif defined(CONFIG_SOC_AU1550) > + MAC_RES(AU1550_ETH1_BASE, AU1550_MAC1_ENABLE, AU1550_MAC1_DMA_INT), > +#elif defined(CONFIG_SOC_AU1500) > + MAC_RES(AU1500_ETH1_BASE, AU1500_MAC1_ENABLE, AU1500_MAC1_DMA_INT), > +#endif > +}; > + > +static struct au1000_eth_platform_data au1xxx_eth0_platform_data = { > + .phy1_search_mac0 = 1, > +}; > + > +static struct platform_device au1xxx_eth0_device = { > + .name = "au1000-eth", > + .id = 0, > + .num_resources = ARRAY_SIZE(au1xxx_eth0_resources), > + .resource = au1xxx_eth0_resources, > + .dev.platform_data = &au1xxx_eth0_platform_data, > +}; > + > +#ifndef CONFIG_SOC_AU1100 > +static struct platform_device au1xxx_eth1_device = { > + .name = "au1000-eth", > + .id = 1, > + .num_resources = ARRAY_SIZE(au1xxx_eth1_resources), > + .resource = au1xxx_eth1_resources, > +}; > +#endif > + > +void __init au1xxx_override_eth0_cfg(struct au1000_eth_platform_data > *eth_data) +{ > + if (!eth_data) > + return; > + > + memcpy(&au1xxx_eth0_platform_data, eth_data, > + sizeof(struct au1000_eth_platform_data)); > +} > + > static struct platform_device *au1xxx_platform_devices[] __initdata = { > &au1xx0_uart_device, > &au1xxx_usb_ohci_device, > @@ -351,17 +422,25 @@ static struct platform_device > *au1xxx_platform_devices[] __initdata = { #ifdef SMBUS_PSC_BASE > &pbdb_smbus_device, > #endif > + &au1xxx_eth0_device, > }; > > static int __init au1xxx_platform_init(void) > { > unsigned int uartclk = get_au1x00_uart_baud_base() * 16; > - int i; > + int i, ni; > > /* Fill up uartclk. */ > for (i = 0; au1x00_uart_data[i].flags; i++) > au1x00_uart_data[i].uartclk = uartclk; > > + /* Register second MAC if enabled in pinfunc */ > +#ifndef CONFIG_SOC_AU1100 > + ni = (int)((au_readl(SYS_PINFUNC) & (u32)(SYS_PF_NI2)) >> 4); > + if (!(ni + 1)) > + platform_device_register(&au1xxx_eth1_device); > +#endif > + > return platform_add_devices(au1xxx_platform_devices, > ARRAY_SIZE(au1xxx_platform_devices)); > } > diff --git a/arch/mips/alchemy/devboards/db1x00/board_setup.c > b/arch/mips/alchemy/devboards/db1x00/board_setup.c index de30d8e..4d2d32c > 100644 > --- a/arch/mips/alchemy/devboards/db1x00/board_setup.c > +++ b/arch/mips/alchemy/devboards/db1x00/board_setup.c > @@ -32,6 +32,7 @@ > > #include > #include > +#include > > #include > > @@ -134,6 +135,22 @@ void __init board_setup(void) > printk(KERN_INFO "AMD Alchemy Au1100/Db1100 Board\n"); > #endif > #ifdef CONFIG_MIPS_BOSPORUS > + struct au1000_eth_platform_data eth0_pdata; > + > + /* > + * Micrel/Kendin 5 port switch attached to MAC0, > + * MAC0 is associated with PHY address 5 (== WAN port) > + * MAC1 is not associated with any PHY, since it's connected directly > + * to the switch. > + * no interrupts are used > + */ > + eth0_pdata.phy1_search_mac0 = 0; > + eth0_pdata.phy_static_config = 1; > + eth0_pdata.phy_addr = 5; > + eth0_pdata.phy_busid = 0; > + > + au1xxx_override_eth0_cfg(ð0_pdata); > + > printk(KERN_INFO "AMD Alchemy Bosporus Board\n"); > #endif > #ifdef CONFIG_MIPS_MIRAGE > diff --git a/arch/mips/include/asm/mach-au1x00/au1xxx_eth.h > b/arch/mips/include/asm/mach-au1x00/au1xxx_eth.h new file mode 100644 > index 0000000..876187e > --- /dev/null > +++ b/arch/mips/include/asm/mach-au1x00/au1xxx_eth.h > @@ -0,0 +1,17 @@ > +#ifndef __AU1X00_ETH_DATA_H > +#define __AU1X00_ETH_DATA_H > + > +/* Platform specific PHY configuration passed to the MAC driver */ > +struct au1000_eth_platform_data { > + int phy_static_config; > + int phy_search_highest_addr; > + int phy1_search_mac0; > + int phy_addr; > + int phy_busid; > + int phy_irq; > +}; > + > +void __init au1xxx_override_eth0_cfg(struct au1000_eth_platform_data > *eth_data); + > +#endif /* __AU1X00_ETH_DATA_H */ > + -- Best regards, Florian Fainelli Email: florian@openwrt.org Web: http://openwrt.org IRC: [florian] on irc.freenode.net ------------------------------- From manuel.lauss@googlemail.com Fri Aug 21 19:23:47 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 21 Aug 2009 19:23:53 +0200 (CEST) Received: from mail-bw0-f208.google.com ([209.85.218.208]:59758 "EHLO mail-bw0-f208.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492209AbZHURXr convert rfc822-to-8bit (ORCPT ); Fri, 21 Aug 2009 19:23:47 +0200 Received: by bwz4 with SMTP id 4so793988bwz.0 for ; Fri, 21 Aug 2009 10:23:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=domainkey-signature:mime-version:received:in-reply-to:references :date:message-id:subject:from:to:cc:content-type :content-transfer-encoding; bh=mhR+JyU1now7PawTaLc9AbtV6XjxvwugHLeo8n2Bj2Y=; b=whsY2Bb0dOcY+zi7A4G71VWr5oTRwOuzeARngTcDqgHQL1soP8xpkTgI/hu/7N1LVN SfrWErssDZAGWyETdf0kqewihYPzvcUrD2cy1t4Oei38/A24Q5EiTTcgxFD5tC8xvy7S phpvP4FHH5rzVgNE6Voi0114mmVhsA8nWtpuc= DomainKey-Signature: a=rsa-sha1; c=nofws; d=googlemail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type:content-transfer-encoding; b=RXz3JslB99FGiaThUxQCMCcIbZIeFniNhvX1ZP3Jjunz43CPHVZ+GjdMMv8eTldTbw glHB9ipgz6V0h2WsuBVPm/P2uKYBkKmrUB0KfEdA8fSgBaMAprVUQP5QqwFCMhWWlWgd cPngP00jIzxxeW9NPe4Uo0q7qE5pVrgCQuLjI= MIME-Version: 1.0 Received: by 10.223.54.152 with SMTP id q24mr321990fag.19.1250875419201; Fri, 21 Aug 2009 10:23:39 -0700 (PDT) In-Reply-To: <200908211853.07969.florian@openwrt.org> References: <200908170105.38154.florian@openwrt.org> <4A8AC125.3020602@ru.mvista.com> <200908181801.41602.florian@openwrt.org> <200908211853.07969.florian@openwrt.org> Date: Fri, 21 Aug 2009 19:23:39 +0200 Message-ID: Subject: Re: [PATCH 1/2] alchemy: add au1000-eth platform device From: Manuel Lauss To: Florian Fainelli Cc: Sergei Shtylyov , Ralf Baechle , linux-mips@linux-mips.org, David Miller , netdev@vger.kernel.org Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23920 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips Hi Florian, On Fri, Aug 21, 2009 at 6:53 PM, Florian Fainelli wrote: > Le Tuesday 18 August 2009 18:01:40 Florian Fainelli, vous avez écrit : >> Le Tuesday 18 August 2009 16:56:37 Sergei Shtylyov, vous avez écrit : >> > Hello. >> > >> > Florian Fainelli wrote: >> > > This patch adds the board code to register a per-board au1000-eth >> > > platform device to be used wit the au1000-eth platform driver in a >> > > subsequent patch. Note that the au1000-eth driver knows about the >> > > default driver settings such that we do not need to pass any >> > > platform_data informations in most cases except db1x00. >> > >> >     Sigh, NAK... >> >     Please don't register the SoC device per board, do it in >> > alchemy/common/platfrom.c and find a way to pass the board specific >> > platform data from the board file there instead -- something like >> > arch/arm/mach-davinci/usb.c does. >> >> Ok, like I promised, this was the per-board device registration. Do you >> prefer something like this: -- >> From fd75b7c7fa3c05c21122c43e43260d2785475a79 Mon Sep 17 00:00:00 2001 >> From: Florian Fainelli >> Date: Tue, 18 Aug 2009 17:53:21 +0200 >> Subject: [PATCH] alchemy: add au1000-eth platform device (v2) >> >> This patch makes the board code register the au1000-eth >> platform device. The au1000-eth platform data can be >> overriden with the au1xxx_override_eth0_cfg function >> like it has to be done for the Bosporus board. > > Sergei, any comments on that version? What about you Manuel? Obviously I *much* prefer your first version, but I'm okay with this second version too. (I usually only comment if I don't like things, so take my silence as approval). Thanks for your work! Manuel Lauss From manuel.lauss@googlemail.com Sat Aug 22 18:09:26 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 22 Aug 2009 18:09:32 +0200 (CEST) Received: from mail-bw0-f208.google.com ([209.85.218.208]:33132 "EHLO mail-bw0-f208.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492812AbZHVQJ0 (ORCPT ); Sat, 22 Aug 2009 18:09:26 +0200 Received: by bwz4 with SMTP id 4so1099359bwz.0 for ; Sat, 22 Aug 2009 09:09:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer; bh=RsZHI9T3ZCqEGGdEig3/FJrY4tKQGvDviQTAT6LK3oo=; b=Qmi2tiBcyPE7/rhVRtxf7VkdvhsH9srqlAsOXbSQH7yk1w6D+gxnJNSiAP0XDIoW/O tcPJtlRgU3sfkZENC0Yom7o+hNVLOwnhk47SywqlILSpeeQm3pM611MdGctFLC8aPJcM R612c9ldyWFjLHSi6mdOTYmbFm58VOU/aF0vA= DomainKey-Signature: a=rsa-sha1; c=nofws; d=googlemail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer; b=uRzoiVsvrrfJD1/p0qnD3khviRrBrUdUjJjvYJFCGO5DbYjzffjOdFE/7LceCxv646 bn32ldd5zE4805RXMqFnwRrpaBzkUsuR82zc3qNKTWEmctfz+IWKBhjO0/8dwdbXy1XJ NnvTma1LI8e7A0HVXGrtFmxy3FV47Acij5edU= Received: by 10.223.143.79 with SMTP id t15mr1613850fau.6.1250957361280; Sat, 22 Aug 2009 09:09:21 -0700 (PDT) Received: from localhost.localdomain (fnoeppeil48.netpark.at [217.175.205.176]) by mx.google.com with ESMTPS id c28sm4086308fka.19.2009.08.22.09.09.19 (version=TLSv1/SSLv3 cipher=RC4-MD5); Sat, 22 Aug 2009 09:09:20 -0700 (PDT) From: Manuel Lauss To: Linux-MIPS , Ralf Baechle Cc: Manuel Lauss Subject: [PATCH] Alchemy: override loops_per_jiffy detection Date: Sat, 22 Aug 2009 18:09:12 +0200 Message-Id: <1250957352-14359-1-git-send-email-manuel.lauss@gmail.com> X-Mailer: git-send-email 1.6.4 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23921 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips The loops_per_jiffy detection in generic calibrate_delay is a bit off (by ~0.5% usually); calculate the correct value based on detected core clock. BogoMIPS value will now reflect cpu core clock correctly. (Blatantly stolen from the SH port). Signed-off-by: Manuel Lauss --- arch/mips/Kconfig | 2 +- arch/mips/alchemy/common/setup.c | 11 +++++++++++ 2 files changed, 12 insertions(+), 1 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 3ca0fe1..56c8139 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -700,7 +700,7 @@ config GENERIC_HWEIGHT config GENERIC_CALIBRATE_DELAY bool - default y + default y if !MACH_ALCHEMY config GENERIC_CLOCKEVENTS bool diff --git a/arch/mips/alchemy/common/setup.c b/arch/mips/alchemy/common/setup.c index 3f036b3..5ea7e1a 100644 --- a/arch/mips/alchemy/common/setup.c +++ b/arch/mips/alchemy/common/setup.c @@ -74,6 +74,17 @@ void __init plat_mem_setup(void) iomem_resource.end = IOMEM_RESOURCE_END; } +void __cpuinit calibrate_delay(void) +{ + loops_per_jiffy = (get_au1x00_speed() >> 1) / HZ; + + printk(KERN_INFO "Calibrating delay loop (skipped)... " + "%lu.%02lu BogoMIPS PRESET (lpj=%lu)\n", + loops_per_jiffy/(500000/HZ), + (loops_per_jiffy/(5000/HZ)) % 100, + loops_per_jiffy); +} + #if defined(CONFIG_64BIT_PHYS_ADDR) /* This routine should be valid for all Au1x based boards */ phys_t __fixup_bigphys_addr(phys_t phys_addr, phys_t size) -- 1.6.3.3 From manuel.lauss@googlemail.com Sat Aug 22 18:09:50 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 22 Aug 2009 18:09:56 +0200 (CEST) Received: from mail-bw0-f208.google.com ([209.85.218.208]:33132 "EHLO mail-bw0-f208.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492936AbZHVQJb (ORCPT ); Sat, 22 Aug 2009 18:09:31 +0200 Received: by mail-bw0-f208.google.com with SMTP id 4so1099359bwz.0 for ; Sat, 22 Aug 2009 09:09:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer; bh=qqU5iqOJkK0Gmre35ek6u5BE2JR47l/oCVlvrZz9R58=; b=n9w4Iv1qpUyKSJQQqQJwEHTndI54SneCnLKGh75xaOBdTsc4av0dlWuMaJI5ApmlR1 7rAl0KOVVwGM83B3g1kvfjPBGtLVhE3ZFcT9GKn/Rkfg6RHz+8qsLridNptOGyLcz9o1 3+0bTy7oQf+3Zj8OE9IV88JZvw/PNkd/gmpDI= DomainKey-Signature: a=rsa-sha1; c=nofws; d=googlemail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer; b=hezOs9/NSjsf7PwEAzF9D43SWArry/TZAqhMF7YC2UfT7NwT7fP+I/fnmLpmfje6iJ hFpNDlZ+Obe+KdoWGYjS3NApyul7/EcJ+Vr4a7wtPRsSSmzeTnkqehxaMI/rSkk4Dd+v HfjCC397EIyMay9Cs+k6GN0USXCrEWV27Gw7o= Received: by 10.223.132.204 with SMTP id c12mr1608416fat.32.1250957370753; Sat, 22 Aug 2009 09:09:30 -0700 (PDT) Received: from localhost.localdomain (fnoeppeil48.netpark.at [217.175.205.176]) by mx.google.com with ESMTPS id p17sm4088378fka.42.2009.08.22.09.09.29 (version=TLSv1/SSLv3 cipher=RC4-MD5); Sat, 22 Aug 2009 09:09:29 -0700 (PDT) From: Manuel Lauss To: Linux-MIPS , Ralf Baechle Cc: Manuel Lauss Subject: [PATCH] Alchemy: get rid of allow_au1k_wait Date: Sat, 22 Aug 2009 18:09:27 +0200 Message-Id: <1250957367-14389-1-git-send-email-manuel.lauss@gmail.com> X-Mailer: git-send-email 1.6.4 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23922 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips Eliminate the 'allow_au1k_wait' variable. MIPS kernel installs the Alchemy-specific wait code before timer initialization; if the C0 timer must be used for timekeeping the wait function is set to NULL which means no wait implementation is available. As a sideeffect, the 'wait instruction available' output in /proc/cpuinfo now correctly indicates whether 'wait' is usable. Run-tested on DB1200. Signed-off-by: Manuel Lauss --- arch/mips/alchemy/common/time.c | 14 ++++++++------ arch/mips/kernel/cpu-probe.c | 10 +++------- 2 files changed, 11 insertions(+), 13 deletions(-) diff --git a/arch/mips/alchemy/common/time.c b/arch/mips/alchemy/common/time.c index 33fbae7..9fc0d44 100644 --- a/arch/mips/alchemy/common/time.c +++ b/arch/mips/alchemy/common/time.c @@ -36,14 +36,13 @@ #include #include +#include #include #include /* 32kHz clock enabled and detected */ #define CNTR_OK (SYS_CNTRL_E0 | SYS_CNTRL_32S) -extern int allow_au1k_wait; /* default off for CP0 Counter */ - static cycle_t au1x_counter1_read(struct clocksource *cs) { return au_readl(SYS_RTCREAD); @@ -153,13 +152,16 @@ void __init plat_time_init(void) printk(KERN_INFO "Alchemy clocksource installed\n"); - /* can now use 'wait' */ - allow_au1k_wait = 1; return; cntr_err: - /* counters unusable, use C0 counter */ + /* MIPS kernel assigns 'au1k_wait' to 'cpu_wait' before this + * function is called. Because the Alchemy counters are unusable + * the C0 timekeeping code is installed and use of the 'wait' + * instruction must be prohibited, which is done most easily by + * assigning NULL to cpu_wait. + */ + cpu_wait = NULL; r4k_clockevent_init(); init_r4k_clocksource(); - allow_au1k_wait = 0; } diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index b13b8eb..262ea9c 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -91,15 +91,11 @@ static void rm7k_wait_irqoff(void) } /* The Au1xxx wait is available only if using 32khz counter or - * external timer source, but specifically not CP0 Counter. */ -int allow_au1k_wait; - + * external timer source, but specifically not CP0 Counter. + * alchemy/common/time.c may override cpu_wait! + */ static void au1k_wait(void) { - if (!allow_au1k_wait) - return; - - /* using the wait instruction makes CP0 counter unusable */ __asm__(" .set mips3 \n" " cache 0x14, 0(%0) \n" " cache 0x14, 32(%0) \n" -- 1.6.3.1 From manuel.lauss@googlemail.com Sat Aug 22 18:10:14 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 22 Aug 2009 18:10:20 +0200 (CEST) Received: from mail-bw0-f208.google.com ([209.85.218.208]:62063 "EHLO mail-bw0-f208.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1493193AbZHVQKL (ORCPT ); Sat, 22 Aug 2009 18:10:11 +0200 Received: by bwz4 with SMTP id 4so1099528bwz.0 for ; Sat, 22 Aug 2009 09:10:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer; bh=zhRWrqz1duPgK2Cb6jUqlfvzMo9dvfiUHQwAHEUiWno=; b=G9+U9dOLl38M7m1hj6tGIqzktackaDJpdPBh0ynCGNX8qZXNage2MTr42J33Bvuuux BRdVHOmib2Ucnio34jZwYJLS91oTZus52V+XsUpmG5jGK7N394Fsat8eY28LxpjoqjVh jEgBfV0s1vFUqN+9CnVbexDPFP+pYqROnQA9A= DomainKey-Signature: a=rsa-sha1; c=nofws; d=googlemail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer; b=DYHjSRQSm7kiLsZ6IWvn52N1Md3AOWiJgPJX3a4FxlNS+6nGxZCDK97cLkyQA2FSRd ooRG4IqgI25is86d3iyQAZiqeJcM7KNEVEshoZuXQsn+6d1NvW6NhjE/C/Jvi8qfEx2q L+PdAbTkL0kaqQ1bJIyMY7OCf0ML1q+or9674= Received: by 10.223.144.201 with SMTP id a9mr1599261fav.17.1250957406283; Sat, 22 Aug 2009 09:10:06 -0700 (PDT) Received: from localhost.localdomain (fnoeppeil48.netpark.at [217.175.205.176]) by mx.google.com with ESMTPS id f31sm4121507fkf.38.2009.08.22.09.10.05 (version=TLSv1/SSLv3 cipher=RC4-MD5); Sat, 22 Aug 2009 09:10:05 -0700 (PDT) From: Manuel Lauss To: Linux-MIPS , Ralf Baechle Cc: Manuel Lauss Subject: [PATCH 0/2] RFC: Alchemy: multiple timer base address support Date: Sat, 22 Aug 2009 18:09:59 +0200 Message-Id: <1250957401-14447-1-git-send-email-manuel.lauss@gmail.com> X-Mailer: git-send-email 1.6.4 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23923 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips The Au1300 has the SYS_ block, which incorporates the 32kHz timer, PM support and other stuff, at a base address different from all previous models. The following two patches add support for runtime detection of CPU type and setup the timer on the correct base address (and as preparation for a later patchseries, also irq number for RTCMATCH2). Patch overview: #1 adds a simple CPU subtype enumerator, #2 implements the core changes. Run-tested on DB1200. Manuel Lauss (2): Alchemy: simple cpu subtype detector. Alchemy: timer: support multiple SYS_BASE addresses arch/mips/alchemy/common/time.c | 137 ++++++++++++++++++++-------- arch/mips/alchemy/devboards/pm.c | 58 +++++++----- arch/mips/include/asm/mach-au1x00/au1000.h | 66 ++++++++++++-- 3 files changed, 191 insertions(+), 70 deletions(-) From manuel.lauss@googlemail.com Sat Aug 22 18:10:37 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 22 Aug 2009 18:10:44 +0200 (CEST) Received: from mail-bw0-f208.google.com ([209.85.218.208]:33731 "EHLO mail-bw0-f208.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1493202AbZHVQKM (ORCPT ); Sat, 22 Aug 2009 18:10:12 +0200 Received: by bwz4 with SMTP id 4so1099534bwz.0 for ; Sat, 22 Aug 2009 09:10:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer:in-reply-to:references; bh=zY2EHmdN9z4T3w79JVKY8oNIiDp8aoPqXhQb4LQSuGQ=; b=milZSKJ5Qi6cY6Dle1LxUkLPlKbRhPZ4jApwBlQL7LuV17pxuCnOFcbo7RKxNxcNKA 07K+crZHG+aCf3Cf3WU4kJahtxk5UfflZHC7ofKd7bMcG2EE81jLB4Q1b9zlnMV4sYyC hUSxECQ9KM2rKB7PfYlUkXLO2AtybdxNYlhtE= DomainKey-Signature: a=rsa-sha1; c=nofws; d=googlemail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; b=Y5MrbpcR4E6uLTocKd5YoWzXo2bMYUb6oCXI9ghtHHlu8DSKua57q6cAiSiOiMgEnn eacFxOwTell7aTs8ks/4UqyyJXKxORa/CI+aFb1hgUXzbJm+lRG9lNq8cCLRZhaEPPnH V+pW35gPM+s6ZuCzPiUGPdAejTB4To2oaOiZI= Received: by 10.223.144.204 with SMTP id a12mr1591871fav.49.1250957406947; Sat, 22 Aug 2009 09:10:06 -0700 (PDT) Received: from localhost.localdomain (fnoeppeil48.netpark.at [217.175.205.176]) by mx.google.com with ESMTPS id f31sm4121507fkf.38.2009.08.22.09.10.06 (version=TLSv1/SSLv3 cipher=RC4-MD5); Sat, 22 Aug 2009 09:10:06 -0700 (PDT) From: Manuel Lauss To: Linux-MIPS , Ralf Baechle Cc: Manuel Lauss Subject: [PATCH 1/2] Alchemy: simple cpu subtype detector. Date: Sat, 22 Aug 2009 18:10:00 +0200 Message-Id: <1250957401-14447-2-git-send-email-manuel.lauss@gmail.com> X-Mailer: git-send-email 1.6.4 In-Reply-To: <1250957401-14447-1-git-send-email-manuel.lauss@gmail.com> References: <1250957401-14447-1-git-send-email-manuel.lauss@gmail.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23924 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips Signed-off-by: Manuel Lauss --- arch/mips/include/asm/mach-au1x00/au1000.h | 34 ++++++++++++++++++++++++++++ 1 files changed, 34 insertions(+), 0 deletions(-) diff --git a/arch/mips/include/asm/mach-au1x00/au1000.h b/arch/mips/include/asm/mach-au1x00/au1000.h index 854e95f..85713f8 100644 --- a/arch/mips/include/asm/mach-au1x00/au1000.h +++ b/arch/mips/include/asm/mach-au1x00/au1000.h @@ -130,6 +130,40 @@ static inline int au1xxx_cpu_needs_config_od(void) return 0; } +#define ALCHEMY_CPU_UNKNOWN -1 +#define ALCHEMY_CPU_AU1000 0 +#define ALCHEMY_CPU_AU1500 1 +#define ALCHEMY_CPU_AU1100 2 +#define ALCHEMY_CPU_AU1550 3 +#define ALCHEMY_CPU_AU1200 4 +#define ALCHEMY_CPU_AU1300 5 + +static inline int alchemy_get_cputype(void) +{ + switch (read_c0_prid() & 0xffff0000) { + case 0x00030000: + return ALCHEMY_CPU_AU1000; + break; + case 0x01030000: + return ALCHEMY_CPU_AU1500; + break; + case 0x02030000: + return ALCHEMY_CPU_AU1100; + break; + case 0x03030000: + return ALCHEMY_CPU_AU1550; + break; + case 0x04030000: + return ALCHEMY_CPU_AU1200; + break; + case 0x800c0000: + return ALCHEMY_CPU_AU1300; + break; + } + + return ALCHEMY_CPU_UNKNOWN; +} + /* arch/mips/au1000/common/clocks.c */ extern void set_au1x00_speed(unsigned int new_freq); extern unsigned int get_au1x00_speed(void); -- 1.6.4 From manuel.lauss@googlemail.com Sat Aug 22 18:11:01 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 22 Aug 2009 18:11:07 +0200 (CEST) Received: from mail-fx0-f220.google.com ([209.85.220.220]:41544 "EHLO mail-fx0-f220.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1493203AbZHVQKN (ORCPT ); Sat, 22 Aug 2009 18:10:13 +0200 Received: by fxm20 with SMTP id 20so1096675fxm.0 for ; Sat, 22 Aug 2009 09:10:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer:in-reply-to:references; bh=/zAOceF2CpoUiKgYKFCSg1sbjW3FS0pXuv3sYKxonqM=; b=p2Abu4z5xAWuLRyDxD2am2U8qyGMPv49l31qCGbWCDyg9hkekekoo/D7+6PNutetlg 63gvUUZCoKtqi5nIjeFYtH2Qd1zEAIVpMQLyT4JLz/PQRHdHfjh1QZqJ4JkoldO/RJYg +ZWbb4vKsgI4SKOHJDpjfzGE9HPss1l0GU5D4= DomainKey-Signature: a=rsa-sha1; c=nofws; d=googlemail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; b=Ht8KXbL5jlUWEKFpLvNKlPZdMKzi6o7kVxKRSNeRSwzMCZWA0AyrdeCy0l4myYqg5p rCczVsPRPGPBGXuIZ/a+/esX8zKfOGmXdDLTmQ4BAEbVbp1+8rPn/Audz4gCutQW0WIP NodOSsRRyh7nIhK6KzgLdHUJr8SkXMnIr+Zng= Received: by 10.223.161.205 with SMTP id s13mr1598628fax.27.1250957407643; Sat, 22 Aug 2009 09:10:07 -0700 (PDT) Received: from localhost.localdomain (fnoeppeil48.netpark.at [217.175.205.176]) by mx.google.com with ESMTPS id f31sm4121507fkf.38.2009.08.22.09.10.07 (version=TLSv1/SSLv3 cipher=RC4-MD5); Sat, 22 Aug 2009 09:10:07 -0700 (PDT) From: Manuel Lauss To: Linux-MIPS , Ralf Baechle Cc: Manuel Lauss Subject: [PATCH 2/2] Alchemy: timer: support multiple SYS_BASE addresses Date: Sat, 22 Aug 2009 18:10:01 +0200 Message-Id: <1250957401-14447-3-git-send-email-manuel.lauss@gmail.com> X-Mailer: git-send-email 1.6.4 In-Reply-To: <1250957401-14447-2-git-send-email-manuel.lauss@gmail.com> References: <1250957401-14447-1-git-send-email-manuel.lauss@gmail.com> <1250957401-14447-2-git-send-email-manuel.lauss@gmail.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23925 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips The Au1300 has SYS_BASE moved to another bus which has the base address of all timer-related bits changed. Add support for runtime detection of proper timer base address and irq. Signed-off-by: Manuel Lauss --- arch/mips/alchemy/common/time.c | 137 ++++++++++++++++++++-------- arch/mips/alchemy/devboards/pm.c | 58 +++++++----- arch/mips/include/asm/mach-au1x00/au1000.h | 32 +++++-- 3 files changed, 157 insertions(+), 70 deletions(-) diff --git a/arch/mips/alchemy/common/time.c b/arch/mips/alchemy/common/time.c index 9fc0d44..5ae771e 100644 --- a/arch/mips/alchemy/common/time.c +++ b/arch/mips/alchemy/common/time.c @@ -43,28 +43,47 @@ /* 32kHz clock enabled and detected */ #define CNTR_OK (SYS_CNTRL_E0 | SYS_CNTRL_32S) +struct alchemy_clocksource { + struct clocksource cs; + void __iomem *sys_base; +}; + +struct alchemy_clkevdev { + struct clock_event_device cd; + void __iomem *sys_base; +}; + static cycle_t au1x_counter1_read(struct clocksource *cs) { - return au_readl(SYS_RTCREAD); + struct alchemy_clocksource *acs = + container_of(cs, struct alchemy_clocksource, cs); + + return __raw_readl(acs->sys_base + SYS_RTCREAD_OFS); } -static struct clocksource au1x_counter1_clocksource = { - .name = "alchemy-counter1", - .read = au1x_counter1_read, - .mask = CLOCKSOURCE_MASK(32), - .flags = CLOCK_SOURCE_IS_CONTINUOUS, - .rating = 100, +static struct alchemy_clocksource au1x_counter1_clocksource = { + .cs = { + .name = "alchemy-counter1", + .read = au1x_counter1_read, + .mask = CLOCKSOURCE_MASK(32), + .flags = CLOCK_SOURCE_IS_CONTINUOUS, + .rating = 100, + }, }; static int au1x_rtcmatch2_set_next_event(unsigned long delta, - struct clock_event_device *cd) + struct clock_event_device *ced) { - delta += au_readl(SYS_RTCREAD); + struct alchemy_clkevdev *aced = + container_of(ced, struct alchemy_clkevdev, cd); + void __iomem *b = aced->sys_base; + + delta += __raw_readl(b + SYS_RTCREAD_OFS); /* wait for register access */ - while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M21) + while (__raw_readl(b + SYS_COUNTER_CNTRL_OFS) & SYS_CNTRL_M21) ; - au_writel(delta, SYS_RTCMATCH2); - au_sync(); + __raw_writel(delta, b + SYS_RTCMATCH2_OFS); + mmiowb(); return 0; } @@ -81,28 +100,33 @@ static irqreturn_t au1x_rtcmatch2_irq(int irq, void *dev_id) return IRQ_HANDLED; } -static struct clock_event_device au1x_rtcmatch2_clockdev = { - .name = "rtcmatch2", - .features = CLOCK_EVT_FEAT_ONESHOT, - .rating = 100, - .irq = AU1000_RTC_MATCH2_INT, - .set_next_event = au1x_rtcmatch2_set_next_event, - .set_mode = au1x_rtcmatch2_set_mode, - .cpumask = CPU_MASK_ALL_PTR, + +static struct alchemy_clkevdev au1x_rtcmatch2_clockdev = { + .cd = { + .name = "rtcmatch2", + .features = CLOCK_EVT_FEAT_ONESHOT, + .rating = 100, + .set_next_event = au1x_rtcmatch2_set_next_event, + .set_mode = au1x_rtcmatch2_set_mode, + .cpumask = CPU_MASK_ALL_PTR, + }, }; static struct irqaction au1x_rtcmatch2_irqaction = { .handler = au1x_rtcmatch2_irq, .flags = IRQF_DISABLED | IRQF_TIMER, .name = "timer", - .dev_id = &au1x_rtcmatch2_clockdev, + .dev_id = &au1x_rtcmatch2_clockdev.cd, }; -void __init plat_time_init(void) +static int __init alchemy_time_init(void __iomem *sys_base, int cntr_irq) { - struct clock_event_device *cd = &au1x_rtcmatch2_clockdev; + struct clock_event_device *cd = &au1x_rtcmatch2_clockdev.cd; unsigned long t; + au1x_counter1_clocksource.sys_base = sys_base; + au1x_rtcmatch2_clockdev.sys_base = sys_base; + /* Check if firmware (YAMON, ...) has enabled 32kHz and clock * has been detected. If so install the rtcmatch2 clocksource, * otherwise don't bother. Note that both bits being set is by @@ -110,51 +134,55 @@ void __init plat_time_init(void) * (the 32S bit seems to be stuck set to 1 once a single clock- * edge is detected, hence the timeouts). */ - if (CNTR_OK != (au_readl(SYS_COUNTER_CNTRL) & CNTR_OK)) - goto cntr_err; + if (CNTR_OK != (__raw_readl(sys_base + SYS_COUNTER_CNTRL_OFS) & CNTR_OK)) + return -ENODEV; /* * setup counter 1 (RTC) to tick at full speed */ t = 0xffffff; - while ((au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T1S) && --t) + while ((__raw_readl(sys_base + SYS_COUNTER_CNTRL_OFS) & SYS_CNTRL_T1S) && --t) asm volatile ("nop"); if (!t) - goto cntr_err; + return -ENODEV; - au_writel(0, SYS_RTCTRIM); /* 32.768 kHz */ - au_sync(); + __raw_writel(0, sys_base + SYS_RTCTRIM_OFS); /* 32.768 kHz */ + mmiowb(); t = 0xffffff; - while ((au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S) && --t) + while ((__raw_readl(sys_base + SYS_COUNTER_CNTRL_OFS) & SYS_CNTRL_C1S) && --t) asm volatile ("nop"); if (!t) - goto cntr_err; - au_writel(0, SYS_RTCWRITE); - au_sync(); + return -ENODEV; + + __raw_writel(0, sys_base + SYS_RTCWRITE_OFS); + mmiowb(); t = 0xffffff; - while ((au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S) && --t) + while ((__raw_readl(sys_base + SYS_COUNTER_CNTRL_OFS) & SYS_CNTRL_C1S) && --t) asm volatile ("nop"); if (!t) - goto cntr_err; + return -ENODEV; /* register counter1 clocksource and event device */ - clocksource_set_clock(&au1x_counter1_clocksource, 32768); - clocksource_register(&au1x_counter1_clocksource); + clocksource_set_clock(&au1x_counter1_clocksource.cs, 32768); + clocksource_register(&au1x_counter1_clocksource.cs); + cd->irq = cntr_irq; cd->shift = 32; cd->mult = div_sc(32768, NSEC_PER_SEC, cd->shift); cd->max_delta_ns = clockevent_delta2ns(0xffffffff, cd); cd->min_delta_ns = clockevent_delta2ns(8, cd); /* ~0.25ms */ clockevents_register_device(cd); - setup_irq(AU1000_RTC_MATCH2_INT, &au1x_rtcmatch2_irqaction); + setup_irq(cntr_irq, &au1x_rtcmatch2_irqaction); printk(KERN_INFO "Alchemy clocksource installed\n"); - return; + return 0; +} -cntr_err: +static void alchemy_use_c0_cntr(void) +{ /* MIPS kernel assigns 'au1k_wait' to 'cpu_wait' before this * function is called. Because the Alchemy counters are unusable * the C0 timekeeping code is installed and use of the 'wait' @@ -165,3 +193,32 @@ cntr_err: r4k_clockevent_init(); init_r4k_clocksource(); } + +void __init plat_time_init(void) +{ + void __iomem *io = NULL; + int irq, ret; + + switch (alchemy_get_cputype()) { + case ALCHEMY_CPU_AU1000: + case ALCHEMY_CPU_AU1500: + case ALCHEMY_CPU_AU1100: + case ALCHEMY_CPU_AU1550: + case ALCHEMY_CPU_AU1200: + io = (void __iomem *)KSEG1ADDR(SYS_PHYS_ADDR); + irq = AU1000_RTC_MATCH2_INT; + break; +/* case ALCHEMY_CPU_AU1300: + io = (void __iomem *)KSEG1ADDR(AU1300_SYS_PHYS_ADDR); + irq = AU1300_RTC_MATCH2_INT; + break; +*/ + default: + goto c0cntr; + } + + ret = alchemy_time_init(io, irq); + if (ret) +c0cntr: + alchemy_use_c0_cntr(); +} diff --git a/arch/mips/alchemy/devboards/pm.c b/arch/mips/alchemy/devboards/pm.c index 632f986..06b4bfb 100644 --- a/arch/mips/alchemy/devboards/pm.c +++ b/arch/mips/alchemy/devboards/pm.c @@ -23,6 +23,7 @@ static unsigned long db1x_pm_sleep_secs; static unsigned long db1x_pm_wakemsk; static unsigned long db1x_pm_last_wakesrc; +static void __iomem *sys_base; static int db1x_pm_enter(suspend_state_t state) { @@ -30,23 +31,24 @@ static int db1x_pm_enter(suspend_state_t state) alchemy_gpio1_input_enable(); /* clear and setup wake cause and source */ - au_writel(0, SYS_WAKEMSK); - au_sync(); - au_writel(0, SYS_WAKESRC); - au_sync(); + __raw_writel(0, sys_base + SYS_WAKEMSK_OFS); + mmiowb(); + __raw_writel(0, sys_base + SYS_WAKESRC_OFS); + mmiowb(); - au_writel(db1x_pm_wakemsk, SYS_WAKEMSK); - au_sync(); + __raw_writel(db1x_pm_wakemsk, sys_base + SYS_WAKEMSK_OFS); + mmiowb(); /* setup 1Hz-timer-based wakeup: wait for reg access */ - while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M20) + while (__raw_readl(sys_base + SYS_COUNTER_CNTRL_OFS) & SYS_CNTRL_M20) asm volatile ("nop"); - au_writel(au_readl(SYS_TOYREAD) + db1x_pm_sleep_secs, SYS_TOYMATCH2); - au_sync(); + __raw_writel(__raw_readl(sys_base + SYS_TOYREAD_OFS) + db1x_pm_sleep_secs, + sys_base + SYS_TOYMATCH2_OFS); + mmiowb(); /* wait for value to really hit the register */ - while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M20) + while (__raw_readl(sys_base + SYS_COUNTER_CNTRL_OFS) & SYS_CNTRL_M20) asm volatile ("nop"); /* ...and now the sandman can come! */ @@ -70,12 +72,12 @@ static void db1x_pm_end(void) /* read and store wakeup source, the clear the register. To * be able to clear it, WAKEMSK must be cleared first. */ - db1x_pm_last_wakesrc = au_readl(SYS_WAKESRC); - - au_writel(0, SYS_WAKEMSK); - au_writel(0, SYS_WAKESRC); - au_sync(); + db1x_pm_last_wakesrc = __raw_readl(sys_base + SYS_WAKESRC_OFS); + __raw_writel(0, sys_base + SYS_WAKEMSK_OFS); + mmiowb(); + __raw_writel(0, sys_base + SYS_WAKESRC_OFS); + mmiowb(); } static struct platform_suspend_ops db1x_pm_ops = { @@ -206,21 +208,31 @@ static struct attribute_group db1x_pmattr_group = { */ static int __init pm_init(void) { + switch (alchemy_get_cputype()) { + case ALCHEMY_CPU_AU1000: + case ALCHEMY_CPU_AU1500: + case ALCHEMY_CPU_AU1100: + case ALCHEMY_CPU_AU1550: + case ALCHEMY_CPU_AU1200: + sys_base = (void __iomem *)KSEG1ADDR(SYS_PHYS_ADDR); + break; + } + /* init TOY to tick at 1Hz if not already done. No need to wait * for confirmation since there's plenty of time from here to * the next suspend cycle. */ - if (au_readl(SYS_TOYTRIM) != 32767) { - au_writel(32767, SYS_TOYTRIM); - au_sync(); + if (__raw_readl(sys_base + SYS_TOYTRIM_OFS) != 32767) { + __raw_writel(32767, sys_base + SYS_TOYTRIM_OFS); + mmiowb(); } - db1x_pm_last_wakesrc = au_readl(SYS_WAKESRC); + db1x_pm_last_wakesrc = __raw_readl(sys_base + SYS_WAKESRC_OFS); - au_writel(0, SYS_WAKESRC); - au_sync(); - au_writel(0, SYS_WAKEMSK); - au_sync(); + __raw_writel(0, sys_base + SYS_WAKEMSK_OFS); + mmiowb(); + __raw_writel(0, sys_base + SYS_WAKESRC_OFS); + mmiowb(); suspend_set_ops(&db1x_pm_ops); diff --git a/arch/mips/include/asm/mach-au1x00/au1000.h b/arch/mips/include/asm/mach-au1x00/au1000.h index 85713f8..6aa0bab 100644 --- a/arch/mips/include/asm/mach-au1x00/au1000.h +++ b/arch/mips/include/asm/mach-au1x00/au1000.h @@ -1020,7 +1020,8 @@ enum soc_au1200_ints { /* Programmable Counters 0 and 1 */ #define SYS_BASE 0xB1900000 -#define SYS_COUNTER_CNTRL (SYS_BASE + 0x14) +#define SYS_COUNTER_CNTRL_OFS 0x14 +#define SYS_COUNTER_CNTRL (SYS_BASE + SYS_COUNTER_CNTRL_OFS) # define SYS_CNTRL_E1S (1 << 23) # define SYS_CNTRL_T1S (1 << 20) # define SYS_CNTRL_M21 (1 << 19) @@ -1049,13 +1050,20 @@ enum soc_au1200_ints { #define SYS_TOYMATCH2 (SYS_BASE + 0x10) #define SYS_TOYREAD (SYS_BASE + 0x40) +#define SYS_TOYTRIM_OFS 0 +#define SYS_TOYWRITE_OFS 4 +#define SYS_TOYMATCH0_OFS 8 +#define SYS_TOYMATCH1_OFS 0xC +#define SYS_TOYMATCH2_OFS 0x10 +#define SYS_TOYREAD_OFS 0x40 + /* Programmable Counter 1 Registers */ -#define SYS_RTCTRIM (SYS_BASE + 0x44) -#define SYS_RTCWRITE (SYS_BASE + 0x48) -#define SYS_RTCMATCH0 (SYS_BASE + 0x4C) -#define SYS_RTCMATCH1 (SYS_BASE + 0x50) -#define SYS_RTCMATCH2 (SYS_BASE + 0x54) -#define SYS_RTCREAD (SYS_BASE + 0x58) +#define SYS_RTCTRIM_OFS 0x44 +#define SYS_RTCWRITE_OFS 0x48 +#define SYS_RTCMATCH0_OFS 0x4C +#define SYS_RTCMATCH1_OFS 0x50 +#define SYS_RTCMATCH2_OFS 0x54 +#define SYS_RTCREAD_OFS 0x58 /* I2S Controller */ #define I2S_DATA 0xB1000000 @@ -1594,6 +1602,16 @@ enum soc_au1200_ints { #define SYS_SLPPWR 0xB1900078 #define SYS_SLEEP 0xB190007C +#define SYS_SCRATCH0_OFS 0x18 +#define SYS_SCRATCH1_OFS 0x1C +#define SYS_WAKEMSK_OFS 0x34 +#define SYS_ENDIAN_OFS 0x38 +#define SYS_POWERCTRL_OFS 0x3C +#define SYS_WAKESRC_OFS 0x5C +#define SYS_SLPPWR_OFS 0x78 +#define SYS_SLEEP_OFS 0x7C + + #define SYS_WAKEMSK_D2 (1 << 9) #define SYS_WAKEMSK_M2 (1 << 8) #define SYS_WAKEMSK_GPIO(x) (1 << (x)) -- 1.6.4 From herbert@gondor.apana.org.au Mon Aug 24 09:47:52 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 24 Aug 2009 09:47:58 +0200 (CEST) Received: from rhun.apana.org.au ([64.62.148.172]:35331 "EHLO arnor.apana.org.au" rhost-flags-OK-OK-OK-FAIL) by ftp.linux-mips.org with ESMTP id S1492452AbZHXHrw (ORCPT ); Mon, 24 Aug 2009 09:47:52 +0200 Received: from gondolin.me.apana.org.au ([192.168.0.6]) by arnor.apana.org.au with esmtp (Exim 4.63 #1 (Debian)) id 1MfUH7-0002oP-UF; Mon, 24 Aug 2009 17:47:34 +1000 Received: from herbert by gondolin.me.apana.org.au with local (Exim 4.69) (envelope-from ) id 1MfUH4-0008NA-8g; Mon, 24 Aug 2009 17:47:30 +1000 Date: Mon, 24 Aug 2009 17:47:30 +1000 From: Herbert Xu To: David Daney Cc: ralf@linux-mips.org, mpm@selenic.com, linux-mips@linux-mips.org, akpm@linux-foundation.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 1/2] MIPS: Octeon: Add hardware RNG platform device. Message-ID: <20090824074730.GA32067@gondor.apana.org.au> References: <4A8DBB17.5020301@caviumnetworks.com> <1250802623-6526-1-git-send-email-ddaney@caviumnetworks.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1250802623-6526-1-git-send-email-ddaney@caviumnetworks.com> User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23926 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: herbert@gondor.apana.org.au Precedence: bulk X-list: linux-mips On Thu, Aug 20, 2009 at 02:10:22PM -0700, David Daney wrote: > Add a platform device for the Octeon Random Number Generator (RNG). > > Signed-off-by: David Daney Acked-by: Herbert Xu -- Visit Openswan at http://www.openswan.org/ Email: Herbert Xu ~{PmV>HI~} Home Page: http://gondor.apana.org.au/~herbert/ PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt From herbert@gondor.apana.org.au Mon Aug 24 09:48:16 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 24 Aug 2009 09:48:22 +0200 (CEST) Received: from rhun.apana.org.au ([64.62.148.172]:35335 "EHLO arnor.apana.org.au" rhost-flags-OK-OK-OK-FAIL) by ftp.linux-mips.org with ESMTP id S1492458AbZHXHsA (ORCPT ); Mon, 24 Aug 2009 09:48:00 +0200 Received: from gondolin.me.apana.org.au ([192.168.0.6]) by arnor.apana.org.au with esmtp (Exim 4.63 #1 (Debian)) id 1MfUHK-0002oW-FL; Mon, 24 Aug 2009 17:47:46 +1000 Received: from herbert by gondolin.me.apana.org.au with local (Exim 4.69) (envelope-from ) id 1MfUHJ-0008NQ-Un; Mon, 24 Aug 2009 17:47:45 +1000 Date: Mon, 24 Aug 2009 17:47:45 +1000 From: Herbert Xu To: David Daney Cc: ralf@linux-mips.org, mpm@selenic.com, linux-mips@linux-mips.org, akpm@linux-foundation.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 2/2] hw_random: Add hardware RNG for Octeon SOCs. Message-ID: <20090824074745.GB32067@gondor.apana.org.au> References: <4A8DBB17.5020301@caviumnetworks.com> <1250802623-6526-2-git-send-email-ddaney@caviumnetworks.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1250802623-6526-2-git-send-email-ddaney@caviumnetworks.com> User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23927 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: herbert@gondor.apana.org.au Precedence: bulk X-list: linux-mips On Thu, Aug 20, 2009 at 02:10:23PM -0700, David Daney wrote: > Signed-off-by: David Daney Acked-by: Herbert Xu -- Visit Openswan at http://www.openswan.org/ Email: Herbert Xu ~{PmV>HI~} Home Page: http://gondor.apana.org.au/~herbert/ PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt From a.beregalov@gmail.com Mon Aug 24 18:25:20 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 24 Aug 2009 18:25:27 +0200 (CEST) Received: from mail-ew0-f225.google.com ([209.85.219.225]:51561 "EHLO mail-ew0-f225.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1493222AbZHXQZU (ORCPT ); Mon, 24 Aug 2009 18:25:20 +0200 Received: by ewy25 with SMTP id 25so662574ewy.33 for ; Mon, 24 Aug 2009 09:25:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer; bh=0FAt29Lw5oen9vZHjGWdbpbuWY43AxC9kCzRs43ORRA=; b=n+neJoWAeHwaw/E8ojmD6mka+m/X/F33Q8matJdXDXoDD3ABsmj3pQBtmp0OGQYnyt zOCkzpHD6KGuDfFRpoxATBM9kmdFAQa19frD6V82e09v9q0kCyLMffXcpynan0+O+3eE HiuqGPU3rWepNnEvGs47RiEgu55HK5+gVvSVc= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer; b=mZIIT2nkznP+hKSUSzYxr5bPeXVmsdpMxCuhHCWnFo8RT23bg6+ANfUkTWQ+93hfSJ MtQJvWQAGSN1suLubCXXQSFlNx4YuQWQtSHGz3q7AQ+oZ2gU26n5kWxd4UtEGwWwdQV2 DMck/rOFoxRBir8ZRbXo6IhXUohX+AZd9PQUA= Received: by 10.210.37.4 with SMTP id k4mr5429466ebk.4.1251131112954; Mon, 24 Aug 2009 09:25:12 -0700 (PDT) Received: from localhost.localdomain (bohr2.srcc.msu.ru [212.192.244.122]) by mx.google.com with ESMTPS id 7sm5580536eyg.20.2009.08.24.09.25.12 (version=TLSv1/SSLv3 cipher=RC4-MD5); Mon, 24 Aug 2009 09:25:12 -0700 (PDT) From: Alexander Beregalov To: davem@davemloft.net, netdev@vger.kernel.org, linux-mips@linux-mips.org Cc: Alexander Beregalov Subject: [PATCH 1/2] irda/au1k_ir: fix broken netdev_ops conversion Date: Mon, 24 Aug 2009 18:54:27 +0400 Message-Id: <1251125667-6509-1-git-send-email-a.beregalov@gmail.com> X-Mailer: git-send-email 1.6.3.1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23928 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: a.beregalov@gmail.com Precedence: bulk X-list: linux-mips This patch is based on commit d2f3ad4 (pxaficp-ir: remove incorrect net_device_ops). Do the same for au1k_ir. Untested. Signed-off-by: Alexander Beregalov --- drivers/net/irda/au1k_ir.c | 4 ---- 1 files changed, 0 insertions(+), 4 deletions(-) diff --git a/drivers/net/irda/au1k_ir.c b/drivers/net/irda/au1k_ir.c index c4361d4..ee1cff5 100644 --- a/drivers/net/irda/au1k_ir.c +++ b/drivers/net/irda/au1k_ir.c @@ -23,7 +23,6 @@ #include #include #include -#include #include #include #include @@ -205,9 +204,6 @@ static const struct net_device_ops au1k_irda_netdev_ops = { .ndo_start_xmit = au1k_irda_hard_xmit, .ndo_tx_timeout = au1k_tx_timeout, .ndo_do_ioctl = au1k_irda_ioctl, - .ndo_change_mtu = eth_change_mtu, - .ndo_validate_addr = eth_validate_addr, - .ndo_set_mac_address = eth_mac_addr, }; static int au1k_irda_net_init(struct net_device *dev) -- 1.6.4 From sshtylyov@ru.mvista.com Mon Aug 24 20:01:30 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 24 Aug 2009 20:01:37 +0200 (CEST) Received: from h155.mvista.com ([63.81.120.155]:57754 "EHLO imap.sh.mvista.com" rhost-flags-OK-FAIL-OK-FAIL) by ftp.linux-mips.org with ESMTP id S1493580AbZHXSBa (ORCPT ); Mon, 24 Aug 2009 20:01:30 +0200 Received: from [192.168.11.189] (unknown [10.150.0.9]) by imap.sh.mvista.com (Postfix) with ESMTP id 00CAA3EC9; Mon, 24 Aug 2009 11:01:21 -0700 (PDT) Message-ID: <4A92D5D1.60009@ru.mvista.com> Date: Mon, 24 Aug 2009 22:02:57 +0400 From: Sergei Shtylyov Organization: MontaVista Software Inc. User-Agent: Mozilla/5.0 (X11; U; Linux i686; rv:1.7.2) Gecko/20040803 X-Accept-Language: ru, en-us, en-gb MIME-Version: 1.0 To: Florian Fainelli Cc: Ralf Baechle , linux-mips@linux-mips.org, Manuel Lauss , David Miller , netdev@vger.kernel.org Subject: Re: [PATCH 1/2] alchemy: add au1000-eth platform device References: <200908170105.38154.florian@openwrt.org> <4A8AC125.3020602@ru.mvista.com> <200908181801.41602.florian@openwrt.org> In-Reply-To: <200908181801.41602.florian@openwrt.org> Content-Type: text/plain; charset=us-ascii; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23929 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sshtylyov@ru.mvista.com Precedence: bulk X-list: linux-mips Hello. Florian Fainelli wrote: >>>This patch adds the board code to register a per-board au1000-eth >>>platform device to be used wit the au1000-eth platform driver in a >>>subsequent patch. Note that the au1000-eth driver knows about the >>>default driver settings such that we do not need to pass any >>>platform_data informations in most cases except db1x00. >> Sigh, NAK... >> Please don't register the SoC device per board, do it in >>alchemy/common/platfrom.c and find a way to pass the board specific >>platform data from the board file there instead -- something like >>arch/arm/mach-davinci/usb.c does. > Ok, like I promised, this was the per-board device registration. Do you prefer something like this: I certainly do, but still not in this incarnation... :-) > -- > From fd75b7c7fa3c05c21122c43e43260d2785475a79 Mon Sep 17 00:00:00 2001 > From: Florian Fainelli > Date: Tue, 18 Aug 2009 17:53:21 +0200 > Subject: [PATCH] alchemy: add au1000-eth platform device (v2) > > This patch makes the board code register the au1000-eth > platform device. The au1000-eth platform data can be > overriden with the au1xxx_override_eth0_cfg function > like it has to be done for the Bosporus board. > > Changes from v1: > - remove per-board platform.c file > - add an override function to pass custom eth0 platform_data PHY settings > > Signed-off-by: Florian Fainelli > --- > diff --git a/arch/mips/alchemy/common/platform.c b/arch/mips/alchemy/common/platform.c > index 117f99f..559294a 100644 > --- a/arch/mips/alchemy/common/platform.c > +++ b/arch/mips/alchemy/common/platform.c > @@ -19,6 +19,7 @@ > #include > #include > #include > +#include > > #define PORT(_base, _irq) \ > { \ > @@ -331,6 +332,76 @@ static struct platform_device pbdb_smbus_device = { > }; > #endif > > +/* Macro to help defining the Ethernet MAC resources */ > +#define MAC_RES(_base, _enable, _irq) \ > + { \ > + .start = CPHYSADDR(_base), \ > + .end = CPHYSADDR(_base + 0xffff), \ > + .flags = IORESOURCE_MEM, \ > + }, \ > + { \ > + .start = CPHYSADDR(_enable), \ > + .end = CPHYSADDR(_enable + 0x3), \ > + .flags = IORESOURCE_MEM, \ > + }, \ > + { \ > + .start = _irq, \ > + .end = _irq, \ > + .flags = IORESOURCE_IRQ \ > + } > + > +static struct resource au1xxx_eth0_resources[] = { > +#if defined(CONFIG_SOC_AU1000) > + MAC_RES(AU1000_ETH0_BASE, AU1000_MAC0_ENABLE, AU1000_MAC0_DMA_INT), > +#elif defined(CONFIG_SOC_AU1100) > + MAC_RES(AU1100_ETH0_BASE, AU1100_MAC0_ENABLE, AU1100_MAC0_DMA_INT), > +#elif defined(CONFIG_SOC_AU1550) > + MAC_RES(AU1550_ETH0_BASE, AU1550_MAC0_ENABLE, AU1550_MAC0_DMA_INT), > +#elif defined(CONFIG_SOC_AU1500) > + MAC_RES(AU1500_ETH0_BASE, AU1500_MAC0_ENABLE, AU1500_MAC0_DMA_INT), > +#endif > +}; > + > +static struct resource au1xxx_eth1_resources[] = { > +#if defined(CONFIG_SOC_AU1000) > + MAC_RES(AU1000_ETH1_BASE, AU1000_MAC1_ENABLE, AU1000_MAC1_DMA_INT), > +#elif defined(CONFIG_SOC_AU1550) > + MAC_RES(AU1550_ETH1_BASE, AU1550_MAC1_ENABLE, AU1550_MAC1_DMA_INT), > +#elif defined(CONFIG_SOC_AU1500) > + MAC_RES(AU1500_ETH1_BASE, AU1500_MAC1_ENABLE, AU1500_MAC1_DMA_INT), > +#endif > +}; > + > +static struct au1000_eth_platform_data au1xxx_eth0_platform_data = { > + .phy1_search_mac0 = 1, > +}; I'm not sure that the default platfrom data is really a great idea... > +#ifndef CONFIG_SOC_AU1100 > +static struct platform_device au1xxx_eth1_device = { > + .name = "au1000-eth", > + .id = 1, > + .num_resources = ARRAY_SIZE(au1xxx_eth1_resources), > + .resource = au1xxx_eth1_resources, And where's the platfrom data for the second Ethernet? > +}; > +#endif > + > +void __init au1xxx_override_eth0_cfg(struct au1000_eth_platform_data *eth_data) > +{ > + if (!eth_data) > + return; > + > + memcpy(&au1xxx_eth0_platform_data, eth_data, > + sizeof(struct au1000_eth_platform_data)); Why not just set the pointer in au1xxx_eth0_device. And really, why not make the function more generic, with a prototype like: void __init au1xxx_override_eth_cfg(unsigned port, struct au1000_eth_platform_data *eth_data); > +} > + > static struct platform_device *au1xxx_platform_devices[] __initdata = { > &au1xx0_uart_device, > &au1xxx_usb_ohci_device, > @@ -351,17 +422,25 @@ static struct platform_device *au1xxx_platform_devices[] __initdata = { > #ifdef SMBUS_PSC_BASE > &pbdb_smbus_device, > #endif > + &au1xxx_eth0_device, > }; > > static int __init au1xxx_platform_init(void) > { > unsigned int uartclk = get_au1x00_uart_baud_base() * 16; > - int i; > + int i, ni; > > /* Fill up uartclk. */ > for (i = 0; au1x00_uart_data[i].flags; i++) > au1x00_uart_data[i].uartclk = uartclk; > > + /* Register second MAC if enabled in pinfunc */ > +#ifndef CONFIG_SOC_AU1100 > + ni = (int)((au_readl(SYS_PINFUNC) & (u32)(SYS_PF_NI2)) >> 4); > + if (!(ni + 1)) Why so complex, and how can (ni + 1) ever be 0?! :-/ Doesn't that field when 0 mean the pins configured for MAC1 and when 1 -- for GPIO? Why not just: if (!(au_readl(SYS_PINFUNC) & SYS_PF_NI2)) > + platform_device_register(&au1xxx_eth1_device); > +#endif > + WBR, Sergei From davem@davemloft.net Wed Aug 26 05:39:47 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 26 Aug 2009 05:39:54 +0200 (CEST) Received: from 74-93-104-97-Washington.hfc.comcastbusiness.net ([74.93.104.97]:56890 "EHLO sunset.davemloft.net" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1491978AbZHZDjq (ORCPT ); Wed, 26 Aug 2009 05:39:46 +0200 Received: from localhost (localhost [127.0.0.1]) by sunset.davemloft.net (Postfix) with ESMTP id C1CB5C8C1B2; Tue, 25 Aug 2009 20:39:50 -0700 (PDT) Date: Tue, 25 Aug 2009 20:39:50 -0700 (PDT) Message-Id: <20090825.203950.26330430.davem@davemloft.net> To: a.beregalov@gmail.com Cc: netdev@vger.kernel.org, linux-mips@linux-mips.org Subject: Re: [PATCH 1/2] irda/au1k_ir: fix broken netdev_ops conversion From: David Miller In-Reply-To: <1251125667-6509-1-git-send-email-a.beregalov@gmail.com> References: <1251125667-6509-1-git-send-email-a.beregalov@gmail.com> X-Mailer: Mew version 6.2.51 on Emacs 22.1 / Mule 5.0 (SAKAKI) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23930 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: davem@davemloft.net Precedence: bulk X-list: linux-mips From: Alexander Beregalov Date: Mon, 24 Aug 2009 18:54:27 +0400 > This patch is based on commit d2f3ad4 (pxaficp-ir: remove incorrect > net_device_ops). Do the same for au1k_ir. > Untested. > > Signed-off-by: Alexander Beregalov Applied. From ralf@linux-mips.org Thu Aug 27 12:57:00 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 27 Aug 2009 12:57:07 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:41108 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492350AbZH0K47 (ORCPT ); Thu, 27 Aug 2009 12:56:59 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id n7RAvwwV029899; Thu, 27 Aug 2009 11:57:58 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id n7RAvwhx029897; Thu, 27 Aug 2009 11:57:58 +0100 Date: Thu, 27 Aug 2009 11:57:58 +0100 From: Ralf Baechle To: Manuel Lauss Cc: Linux-MIPS , Manuel Lauss Subject: Re: [PATCH] Alchemy: override loops_per_jiffy detection Message-ID: <20090827105758.GA29561@linux-mips.org> References: <1250957352-14359-1-git-send-email-manuel.lauss@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1250957352-14359-1-git-send-email-manuel.lauss@gmail.com> User-Agent: Mutt/1.5.19 (2009-01-05) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23931 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Sat, Aug 22, 2009 at 06:09:12PM +0200, Manuel Lauss wrote: > The loops_per_jiffy detection in generic calibrate_delay is a bit off > (by ~0.5% usually); calculate the correct value based on detected core > clock. BogoMIPS value will now reflect cpu core clock correctly. It think this is pretty much solving a non-problem. The BogoMIPS number should only be used for various delay functions and the only give a guarantee for a minimum delay but barely any promise about accuracy of the delay. Due to interrupts consuming some CPU time and potencially producing extra cache misses the measured BogoMIPS value is expected to be a bit lower than what a naive calculation based on the CPU clock is predicting; effects that not only impact the calculation of the BogoMIPS number but also delays based on the BogoMIPS number. Here's an even easier solution: #include ... preset_lpj = ; Avoid the change to Kconfig that eventually will become messy if other systems continue along this line. Ralf From ralf@linux-mips.org Thu Aug 27 13:07:20 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 27 Aug 2009 13:07:27 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:41773 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492241AbZH0LHU (ORCPT ); Thu, 27 Aug 2009 13:07:20 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id n7RB8J9D030797; Thu, 27 Aug 2009 12:08:19 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id n7RB8Jxw030795; Thu, 27 Aug 2009 12:08:19 +0100 Date: Thu, 27 Aug 2009 12:08:19 +0100 From: Ralf Baechle To: Manuel Lauss Cc: Linux-MIPS , Manuel Lauss Subject: Re: [PATCH] Alchemy: get rid of allow_au1k_wait Message-ID: <20090827110819.GA29984@linux-mips.org> References: <1250957367-14389-1-git-send-email-manuel.lauss@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1250957367-14389-1-git-send-email-manuel.lauss@gmail.com> User-Agent: Mutt/1.5.19 (2009-01-05) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23932 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Sat, Aug 22, 2009 at 06:09:27PM +0200, Manuel Lauss wrote: > Eliminate the 'allow_au1k_wait' variable. MIPS kernel installs the > Alchemy-specific wait code before timer initialization; if the C0 > timer must be used for timekeeping the wait function is set to NULL > which means no wait implementation is available. > > As a sideeffect, the 'wait instruction available' output in > /proc/cpuinfo now correctly indicates whether 'wait' is usable. > > Run-tested on DB1200. Queued, thanks Manuel! Ralf From ralf@linux-mips.org Thu Aug 27 13:45:31 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 27 Aug 2009 13:45:39 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:60197 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492138AbZH0Lpb (ORCPT ); Thu, 27 Aug 2009 13:45:31 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id n7RBkUlR003889; Thu, 27 Aug 2009 12:46:30 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id n7RBkU8l003887; Thu, 27 Aug 2009 12:46:30 +0100 Date: Thu, 27 Aug 2009 12:46:30 +0100 From: Ralf Baechle To: Manuel Lauss Cc: Linux-MIPS , Manuel Lauss Subject: Re: [PATCH 1/2] Alchemy: simple cpu subtype detector. Message-ID: <20090827114630.GB29984@linux-mips.org> References: <1250957401-14447-1-git-send-email-manuel.lauss@gmail.com> <1250957401-14447-2-git-send-email-manuel.lauss@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1250957401-14447-2-git-send-email-manuel.lauss@gmail.com> User-Agent: Mutt/1.5.19 (2009-01-05) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23933 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Sat, Aug 22, 2009 at 06:10:00PM +0200, Manuel Lauss wrote: Queued. Thanks! Ralf From ralf@linux-mips.org Thu Aug 27 13:46:52 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 27 Aug 2009 13:46:59 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:41331 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492138AbZH0Lqw (ORCPT ); Thu, 27 Aug 2009 13:46:52 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id n7RBlqco003937; Thu, 27 Aug 2009 12:47:52 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id n7RBlpYM003935; Thu, 27 Aug 2009 12:47:51 +0100 Date: Thu, 27 Aug 2009 12:47:51 +0100 From: Ralf Baechle To: Manuel Lauss Cc: Linux-MIPS , Manuel Lauss Subject: Re: [PATCH 2/2] Alchemy: timer: support multiple SYS_BASE addresses Message-ID: <20090827114751.GC29984@linux-mips.org> References: <1250957401-14447-1-git-send-email-manuel.lauss@gmail.com> <1250957401-14447-2-git-send-email-manuel.lauss@gmail.com> <1250957401-14447-3-git-send-email-manuel.lauss@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1250957401-14447-3-git-send-email-manuel.lauss@gmail.com> User-Agent: Mutt/1.5.19 (2009-01-05) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23934 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Sat, Aug 22, 2009 at 06:10:01PM +0200, Manuel Lauss wrote: I had a a large reject on arch/mips/alchemy/common/time.c when applying this. I fixed it up but could you verify that things are ok? Patch is now also in the queue. Thanks! Ralf From ralf@linux-mips.org Thu Aug 27 13:48:07 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 27 Aug 2009 13:48:15 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:41340 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492138AbZH0LsH (ORCPT ); Thu, 27 Aug 2009 13:48:07 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id n7RBn7oQ003971; Thu, 27 Aug 2009 12:49:07 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id n7RBn7kM003969; Thu, 27 Aug 2009 12:49:07 +0100 Date: Thu, 27 Aug 2009 12:49:07 +0100 From: Ralf Baechle To: Manuel Lauss Cc: Linux-MIPS , Manuel Lauss Subject: Re: [PATCH 0/2] RFC: Alchemy: multiple timer base address support Message-ID: <20090827114907.GD29984@linux-mips.org> References: <1250957401-14447-1-git-send-email-manuel.lauss@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1250957401-14447-1-git-send-email-manuel.lauss@gmail.com> User-Agent: Mutt/1.5.19 (2009-01-05) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23935 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Sat, Aug 22, 2009 at 06:09:59PM +0200, Manuel Lauss wrote: > From: Manuel Lauss > Date: Sat, 22 Aug 2009 18:09:59 +0200 > To: Linux-MIPS , > Ralf Baechle > Cc: Manuel Lauss > Subject: [PATCH 0/2] RFC: Alchemy: multiple timer base address support Ah, I missed the "RFC" in the subject line. Lemme know if you want me to keep this in -queue or yank it out. Ralf From manuel.lauss@googlemail.com Thu Aug 27 14:09:04 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 27 Aug 2009 14:09:10 +0200 (CEST) Received: from mail-bw0-f208.google.com ([209.85.218.208]:35345 "EHLO mail-bw0-f208.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492364AbZH0MJD convert rfc822-to-8bit (ORCPT ); Thu, 27 Aug 2009 14:09:03 +0200 Received: by bwz4 with SMTP id 4so1133431bwz.0 for ; Thu, 27 Aug 2009 05:08:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=domainkey-signature:mime-version:received:in-reply-to:references :date:message-id:subject:from:to:cc:content-type :content-transfer-encoding; bh=8TDRdK6tXngO+lmQHv3aUgugzqYmWV4YsxfRAt8wgGQ=; b=sWlxMGiJzh1KlAKh8q6mK0cj+3eaiCfsR7BGCwWT+ShL2un1vejLkpYHFskB+a3S5N 0N8oUiTl/Z0KRYrG+9oIUPTQnwUYAVXRSzBQ9/BYD4UZUIvKFA6iN4VPwkGtddL+OgN/ oo814t6nraeN2Z5R+/8H6KJKaMjQxsmoJVnt4= DomainKey-Signature: a=rsa-sha1; c=nofws; d=googlemail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type:content-transfer-encoding; b=N2DuICysKzzbhjRp/eDXQEnrN9YuaZ9IW7CdCoJ08qbClrWvlUL4xxC7ltOZ8FCMVN DW1WF/sqn2DFtlPCMhtrvF8Yv77TIsQLD7CSUeS5P4Atry4uU+/sbrAgWTqnpPMtNzjd IPw7A92M6utWSkQ+m8JBD6tbket1NRr5jNZmw= MIME-Version: 1.0 Received: by 10.223.103.25 with SMTP id i25mr6606965fao.64.1251374938152; Thu, 27 Aug 2009 05:08:58 -0700 (PDT) In-Reply-To: <20090827105758.GA29561@linux-mips.org> References: <1250957352-14359-1-git-send-email-manuel.lauss@gmail.com> <20090827105758.GA29561@linux-mips.org> Date: Thu, 27 Aug 2009 14:08:58 +0200 Message-ID: Subject: Re: [PATCH] Alchemy: override loops_per_jiffy detection From: Manuel Lauss To: Ralf Baechle Cc: Linux-MIPS , Manuel Lauss Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23936 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips Hi Ralf, On Thu, Aug 27, 2009 at 12:57 PM, Ralf Baechle wrote: > On Sat, Aug 22, 2009 at 06:09:12PM +0200, Manuel Lauss wrote: > >> The loops_per_jiffy detection in generic calibrate_delay is a bit off >> (by ~0.5% usually); calculate the correct value based on detected core >> clock.  BogoMIPS value will now reflect cpu core clock correctly. > > It think this is pretty much solving a non-problem. Pretty much, yeah, and it doesn't solve it completely either. With certain frequencies the printed rate is wrong due to rouding ;-) > Here's an even easier solution: > > #include > ... >        preset_lpj = ; > > Avoid the change to Kconfig that eventually will become messy if other > systems continue along this line. Ah, much better. I'll resend a tested new version in a few hours. Thanks! Manuel Lauss From f.fainelli@gmail.com Thu Aug 27 14:48:31 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 27 Aug 2009 14:48:38 +0200 (CEST) Received: from mail-ew0-f225.google.com ([209.85.219.225]:33912 "EHLO mail-ew0-f225.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492366AbZH0Msb convert rfc822-to-8bit (ORCPT ); Thu, 27 Aug 2009 14:48:31 +0200 Received: by ewy25 with SMTP id 25so1136183ewy.33 for ; Thu, 27 Aug 2009 05:48:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:sender:from:to:subject:date :user-agent:cc:references:in-reply-to:mime-version:content-type :content-transfer-encoding:content-disposition:message-id; bh=PclOqaJ/QfH5TqUHk/9MQv1DYijLahHPQJxO2ixeolY=; b=tSYuJ/nacn+4X9v72JAKW35s8tDJDK0nW2IHaMNaMmoRrShAe16Ze4Emb59nViVL3W NN9ZVSEGpxaUvKb2pzacJp1wR/Hdae69C4vsKOz8XQfuRW6QW5Su39OU98oVrPpF8WG9 6eVmMEgdGFojWtKOd6wI0l0Vo5yNZOzWI3V0A= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:from:to:subject:date:user-agent:cc:references:in-reply-to :mime-version:content-type:content-transfer-encoding :content-disposition:message-id; b=ZOAXDHCJfdhaFDm+dNyJnOT9O2U/V5aLmeMPXtfHnMvZNU/ZI8CLET4IkdUvL4UqzP eUZehuI8M5Y7p/2gzjgP6wACLUmrKhcFfxN1XarDMz4LF7DGhxIYkX3qr+zatUNQPXgx YWB72tDL8Ri5OpXkBwQ48C8SAHwMzqzsq4l9M= Received: by 10.211.154.18 with SMTP id g18mr279799ebo.70.1251376962764; Thu, 27 Aug 2009 05:42:42 -0700 (PDT) Received: from florian.lab.openpattern.org (lab.openpattern.org [82.240.16.241]) by mx.google.com with ESMTPS id 23sm438786eya.35.2009.08.27.05.42.37 (version=TLSv1/SSLv3 cipher=RC4-MD5); Thu, 27 Aug 2009 05:42:40 -0700 (PDT) From: Florian Fainelli To: Sergei Shtylyov Subject: Re: [PATCH 1/2] alchemy: add au1000-eth platform device Date: Thu, 27 Aug 2009 14:42:34 +0200 User-Agent: KMail/1.9.9 Cc: Ralf Baechle , linux-mips@linux-mips.org, Manuel Lauss , David Miller , netdev@vger.kernel.org References: <200908170105.38154.florian@openwrt.org> <200908181801.41602.florian@openwrt.org> <4A92D5D1.60009@ru.mvista.com> In-Reply-To: <4A92D5D1.60009@ru.mvista.com> MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 8BIT Content-Disposition: inline Message-Id: <200908271442.36306.florian@openwrt.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23937 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips Hello, Le Monday 24 August 2009 20:02:57 Sergei Shtylyov, vous avez écrit : > Hello. > > Florian Fainelli wrote: > >>>This patch adds the board code to register a per-board au1000-eth > >>>platform device to be used wit the au1000-eth platform driver in a > >>>subsequent patch. Note that the au1000-eth driver knows about the > >>>default driver settings such that we do not need to pass any > >>>platform_data informations in most cases except db1x00. > >> > >> Sigh, NAK... > >> Please don't register the SoC device per board, do it in > >>alchemy/common/platfrom.c and find a way to pass the board specific > >>platform data from the board file there instead -- something like > >>arch/arm/mach-davinci/usb.c does. > > > > Ok, like I promised, this was the per-board device registration. Do you > > prefer something like this: > > I certainly do, but still not in this incarnation... :-) > > > -- > > From fd75b7c7fa3c05c21122c43e43260d2785475a79 Mon Sep 17 00:00:00 2001 > > From: Florian Fainelli > > Date: Tue, 18 Aug 2009 17:53:21 +0200 > > Subject: [PATCH] alchemy: add au1000-eth platform device (v2) > > > > This patch makes the board code register the au1000-eth > > platform device. The au1000-eth platform data can be > > overriden with the au1xxx_override_eth0_cfg function > > like it has to be done for the Bosporus board. > > > > Changes from v1: > > - remove per-board platform.c file > > - add an override function to pass custom eth0 platform_data PHY settings > > > > Signed-off-by: Florian Fainelli > > --- > > diff --git a/arch/mips/alchemy/common/platform.c > > b/arch/mips/alchemy/common/platform.c index 117f99f..559294a 100644 > > --- a/arch/mips/alchemy/common/platform.c > > +++ b/arch/mips/alchemy/common/platform.c > > @@ -19,6 +19,7 @@ > > #include > > #include > > #include > > +#include > > > > #define PORT(_base, _irq) \ > > { \ > > @@ -331,6 +332,76 @@ static struct platform_device pbdb_smbus_device = { > > }; > > #endif > > > > +/* Macro to help defining the Ethernet MAC resources */ > > +#define MAC_RES(_base, _enable, _irq) \ > > + { \ > > + .start = CPHYSADDR(_base), \ > > + .end = CPHYSADDR(_base + 0xffff), \ > > + .flags = IORESOURCE_MEM, \ > > + }, \ > > + { \ > > + .start = CPHYSADDR(_enable), \ > > + .end = CPHYSADDR(_enable + 0x3), \ > > + .flags = IORESOURCE_MEM, \ > > + }, \ > > + { \ > > + .start = _irq, \ > > + .end = _irq, \ > > + .flags = IORESOURCE_IRQ \ > > + } > > + > > +static struct resource au1xxx_eth0_resources[] = { > > +#if defined(CONFIG_SOC_AU1000) > > + MAC_RES(AU1000_ETH0_BASE, AU1000_MAC0_ENABLE, AU1000_MAC0_DMA_INT), > > +#elif defined(CONFIG_SOC_AU1100) > > + MAC_RES(AU1100_ETH0_BASE, AU1100_MAC0_ENABLE, AU1100_MAC0_DMA_INT), > > +#elif defined(CONFIG_SOC_AU1550) > > + MAC_RES(AU1550_ETH0_BASE, AU1550_MAC0_ENABLE, AU1550_MAC0_DMA_INT), > > +#elif defined(CONFIG_SOC_AU1500) > > + MAC_RES(AU1500_ETH0_BASE, AU1500_MAC0_ENABLE, AU1500_MAC0_DMA_INT), > > +#endif > > +}; > > + > > +static struct resource au1xxx_eth1_resources[] = { > > +#if defined(CONFIG_SOC_AU1000) > > + MAC_RES(AU1000_ETH1_BASE, AU1000_MAC1_ENABLE, AU1000_MAC1_DMA_INT), > > +#elif defined(CONFIG_SOC_AU1550) > > + MAC_RES(AU1550_ETH1_BASE, AU1550_MAC1_ENABLE, AU1550_MAC1_DMA_INT), > > +#elif defined(CONFIG_SOC_AU1500) > > + MAC_RES(AU1500_ETH1_BASE, AU1500_MAC1_ENABLE, AU1500_MAC1_DMA_INT), > > +#endif > > +}; > > + > > +static struct au1000_eth_platform_data au1xxx_eth0_platform_data = { > > + .phy1_search_mac0 = 1, > > +}; > > I'm not sure that the default platfrom data is really a great idea... Can you elaborate a bit more ? We actually need to make the Ethernet MAC driver aware of some PHY settings. > > > +#ifndef CONFIG_SOC_AU1100 > > +static struct platform_device au1xxx_eth1_device = { > > + .name = "au1000-eth", > > + .id = 1, > > + .num_resources = ARRAY_SIZE(au1xxx_eth1_resources), > > + .resource = au1xxx_eth1_resources, > > And where's the platfrom data for the second Ethernet? There is no need to, as the driver originally did not override any specific settings on the second MAC (afair). > > > +}; > > +#endif > > + > > +void __init au1xxx_override_eth0_cfg(struct au1000_eth_platform_data > > *eth_data) +{ > > + if (!eth_data) > > + return; > > + > > + memcpy(&au1xxx_eth0_platform_data, eth_data, > > + sizeof(struct au1000_eth_platform_data)); > > Why not just set the pointer in au1xxx_eth0_device. And really, why not > make the function more generic, with a prototype like: For the same reasons as explained below, MAC1 did not need any specific change. > > void __init au1xxx_override_eth_cfg(unsigned port, struct > au1000_eth_platform_data *eth_data); > > > +} > > + > > static struct platform_device *au1xxx_platform_devices[] __initdata = { > > &au1xx0_uart_device, > > &au1xxx_usb_ohci_device, > > @@ -351,17 +422,25 @@ static struct platform_device > > *au1xxx_platform_devices[] __initdata = { #ifdef SMBUS_PSC_BASE > > &pbdb_smbus_device, > > #endif > > + &au1xxx_eth0_device, > > }; > > > > static int __init au1xxx_platform_init(void) > > { > > unsigned int uartclk = get_au1x00_uart_baud_base() * 16; > > - int i; > > + int i, ni; > > > > /* Fill up uartclk. */ > > for (i = 0; au1x00_uart_data[i].flags; i++) > > au1x00_uart_data[i].uartclk = uartclk; > > > > + /* Register second MAC if enabled in pinfunc */ > > +#ifndef CONFIG_SOC_AU1100 > > + ni = (int)((au_readl(SYS_PINFUNC) & (u32)(SYS_PF_NI2)) >> 4); > > + if (!(ni + 1)) > > Why so complex, and how can (ni + 1) ever be 0?! :-/ This is left-over debugging stub, I will rework it. About complexity, this line is taken directly from the au1000_eth driver. > Doesn't that field when 0 mean the pins configured for MAC1 and when 1 > -- for GPIO? Why not just: > > if (!(au_readl(SYS_PINFUNC) & SYS_PF_NI2)) > > > + platform_device_register(&au1xxx_eth1_device); > > +#endif > > + > > WBR, Sergei -- Best regards, Florian Fainelli Email: florian@openwrt.org Web: http://openwrt.org IRC: [florian] on irc.freenode.net ------------------------------- From manuel.lauss@googlemail.com Thu Aug 27 14:49:54 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 27 Aug 2009 14:50:00 +0200 (CEST) Received: from mail-bw0-f208.google.com ([209.85.218.208]:35912 "EHLO mail-bw0-f208.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492415AbZH0Mty convert rfc822-to-8bit (ORCPT ); Thu, 27 Aug 2009 14:49:54 +0200 Received: by bwz4 with SMTP id 4so1162458bwz.0 for ; Thu, 27 Aug 2009 05:49:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=domainkey-signature:mime-version:received:in-reply-to:references :date:message-id:subject:from:to:cc:content-type :content-transfer-encoding; bh=oiSvMLcaDijXlimguMTDVMe3HEVvsCylxl29SI2h9MM=; b=UDlVWWHPyXDf9MtnWl9obDmbsIy4ukPQiBQjbGO7JYxJWySJbfpcRHI6RcNuX/u66w ggoDRToX+btdrzOne9LYH5hVQtrXG82Bzr1phrYvS29GjgEfpqxwWgetSbYre+lKrzuo H/VRkbq9OMpksrUccXwwSjkVcHZclebXHNL5E= DomainKey-Signature: a=rsa-sha1; c=nofws; d=googlemail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type:content-transfer-encoding; b=EWOuC5oYUf8hiwispUfvhge3g7um0pYoVthPrxwsw90AiNpa2vXRMASUvWzAJGG4zN Tti88Uu7fEPQPyEeUaCvNWXXkeXvzR+zyLre0/ommpfuysoHSu1VYet18ge8F+4f2Qqu k1lxyEnoEexXoddBEsl/wPAvogOPLAd07aXCI= MIME-Version: 1.0 Received: by 10.223.14.215 with SMTP id h23mr6707449faa.59.1251377386531; Thu, 27 Aug 2009 05:49:46 -0700 (PDT) In-Reply-To: <20090827114751.GC29984@linux-mips.org> References: <1250957401-14447-1-git-send-email-manuel.lauss@gmail.com> <1250957401-14447-2-git-send-email-manuel.lauss@gmail.com> <1250957401-14447-3-git-send-email-manuel.lauss@gmail.com> <20090827114751.GC29984@linux-mips.org> Date: Thu, 27 Aug 2009 14:49:44 +0200 Message-ID: Subject: Re: [PATCH 2/2] Alchemy: timer: support multiple SYS_BASE addresses From: Manuel Lauss To: Ralf Baechle Cc: Linux-MIPS , Manuel Lauss Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23938 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips On Thu, Aug 27, 2009 at 1:47 PM, Ralf Baechle wrote: > On Sat, Aug 22, 2009 at 06:10:01PM +0200, Manuel Lauss wrote: > > I had a a large reject on arch/mips/alchemy/common/time.c when applying > this.  I fixed it up but could you verify that things are ok?  Patch is > now also in the queue.  Thanks! Oh, sorry about that! The result looks okay. I was hoping someone with an Au1300 could give this a spin and verify that the basic idea works. Thanks! Manuel Lauss From manuel.lauss@googlemail.com Thu Aug 27 15:01:18 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 27 Aug 2009 15:01:24 +0200 (CEST) Received: from mail-fx0-f220.google.com ([209.85.220.220]:39612 "EHLO mail-fx0-f220.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492316AbZH0NBR convert rfc822-to-8bit (ORCPT ); Thu, 27 Aug 2009 15:01:17 +0200 Received: by fxm20 with SMTP id 20so1197993fxm.0 for ; Thu, 27 Aug 2009 06:01:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=domainkey-signature:mime-version:received:in-reply-to:references :date:message-id:subject:from:to:cc:content-type :content-transfer-encoding; bh=i0zIStESLgPSXir5RyuhKO6iY4sJ+gdCKI0F7o+tCVY=; b=P6fEVIlO4QwMo9FyV2x9x8/FWKvpp3adibetAmmBHss9buWUL3Ki17rT/g0ZqV4x71 4jRQK52SH9YzPd7Sk4FND7/0RJONB/l/Vy3eHL8mUD6YQI+je9xOBljy+LW3tNwjuPto Z6+ysL3UDbXPp5fs2WT8LKvWEmmLpgjCbwqQI= DomainKey-Signature: a=rsa-sha1; c=nofws; d=googlemail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type:content-transfer-encoding; b=qCgXyvz1eOw+kfRAHtTh5beVBJfTSOK+rAXNUTxhkDOlWsLp6VramLNJYgehdwZrb4 3VzpHNHXlK6ZoKBEsRX5DWYYX++lK17vCX/GDdaqWeG/zwD3PDDiDA8tRNMk8BfGg3oX H9iVaBbRljU8WW1cFAtHFcbanV/k8MXsNjuuc= MIME-Version: 1.0 Received: by 10.223.144.204 with SMTP id a12mr6580541fav.49.1251378071447; Thu, 27 Aug 2009 06:01:11 -0700 (PDT) In-Reply-To: <20090827114907.GD29984@linux-mips.org> References: <1250957401-14447-1-git-send-email-manuel.lauss@gmail.com> <20090827114907.GD29984@linux-mips.org> Date: Thu, 27 Aug 2009 15:01:11 +0200 Message-ID: Subject: Re: [PATCH 0/2] RFC: Alchemy: multiple timer base address support From: Manuel Lauss To: Ralf Baechle Cc: Linux-MIPS , Manuel Lauss Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23939 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips On Thu, Aug 27, 2009 at 1:49 PM, Ralf Baechle wrote: > On Sat, Aug 22, 2009 at 06:09:59PM +0200, Manuel Lauss wrote: >> From: Manuel Lauss >> Date: Sat, 22 Aug 2009 18:09:59 +0200 >> To: Linux-MIPS , >>       Ralf Baechle >> Cc: Manuel Lauss >> Subject: [PATCH 0/2] RFC: Alchemy: multiple timer base address support > > Ah, I missed the "RFC" in the subject line.  Lemme know if you want me to > keep this in -queue or yank it out. Please yank it for now, I'll resend diffed against -queue at a later date. Manuel Lauss From sshtylyov@ru.mvista.com Thu Aug 27 16:14:20 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 27 Aug 2009 16:14:27 +0200 (CEST) Received: from h155.mvista.com ([63.81.120.155]:24132 "EHLO imap.sh.mvista.com" rhost-flags-OK-FAIL-OK-FAIL) by ftp.linux-mips.org with ESMTP id S1492487AbZH0OOT (ORCPT ); Thu, 27 Aug 2009 16:14:19 +0200 Received: from [192.168.11.189] (unknown [10.150.0.9]) by imap.sh.mvista.com (Postfix) with ESMTP id 706DA3EC9; Thu, 27 Aug 2009 07:14:11 -0700 (PDT) Message-ID: <4A969519.7010604@ru.mvista.com> Date: Thu, 27 Aug 2009 18:15:53 +0400 From: Sergei Shtylyov Organization: MontaVista Software Inc. User-Agent: Mozilla/5.0 (X11; U; Linux i686; rv:1.7.2) Gecko/20040803 X-Accept-Language: ru, en-us, en-gb MIME-Version: 1.0 To: Florian Fainelli Cc: Ralf Baechle , linux-mips@linux-mips.org, Manuel Lauss , David Miller , netdev@vger.kernel.org Subject: Re: [PATCH 1/2] alchemy: add au1000-eth platform device References: <200908170105.38154.florian@openwrt.org> <200908181801.41602.florian@openwrt.org> <4A92D5D1.60009@ru.mvista.com> <200908271442.36306.florian@openwrt.org> In-Reply-To: <200908271442.36306.florian@openwrt.org> Content-Type: text/plain; charset=us-ascii; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23940 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sshtylyov@ru.mvista.com Precedence: bulk X-list: linux-mips Hello. Florian Fainelli wrote: >>>>>This patch adds the board code to register a per-board au1000-eth >>>>>platform device to be used wit the au1000-eth platform driver in a >>>>>subsequent patch. Note that the au1000-eth driver knows about the >>>>>default driver settings such that we do not need to pass any >>>>>platform_data informations in most cases except db1x00. >>>> Sigh, NAK... >>>> Please don't register the SoC device per board, do it in >>>>alchemy/common/platfrom.c and find a way to pass the board specific >>>>platform data from the board file there instead -- something like >>>>arch/arm/mach-davinci/usb.c does. >>>Ok, like I promised, this was the per-board device registration. Do you >>>prefer something like this: >> I certainly do, but still not in this incarnation... :-) >>>+static struct au1000_eth_platform_data au1xxx_eth0_platform_data = { >>>+ .phy1_search_mac0 = 1, >>>+}; >> I'm not sure that the default platfrom data is really a great idea... > Can you elaborate a bit more ? We actually need to make the Ethernet MAC driver aware of some PHY settings. But why do you have the platform data in *this* file, no the board files? >>>+#ifndef CONFIG_SOC_AU1100 >>>+static struct platform_device au1xxx_eth1_device = { >>>+ .name = "au1000-eth", >>>+ .id = 1, >>>+ .num_resources = ARRAY_SIZE(au1xxx_eth1_resources), >>>+ .resource = au1xxx_eth1_resources, >> And where's the platfrom data for the second Ethernet? > There is no need to, as the driver originally did not override any specific settings on the second MAC (afair). Specific settings where, in the driver? Shouldn't all such settings be bound to the platform data instead? >>>+}; >>>+#endif >>>+ >>>+void __init au1xxx_override_eth0_cfg(struct au1000_eth_platform_data >>>*eth_data) +{ >>>+ if (!eth_data) >>>+ return; >>>+ >>>+ memcpy(&au1xxx_eth0_platform_data, eth_data, >>>+ sizeof(struct au1000_eth_platform_data)); >> Why not just set the pointer in au1xxx_eth0_device. And really, why not >>make the function more generic, with a prototype like: > For the same reasons as explained below, MAC1 did not need any specific change. So, the driver can get away without platform data? What does it do in this case -- I haven't looked at that patch? >>void __init au1xxx_override_eth_cfg(unsigned port, struct >> au1000_eth_platform_data *eth_data); >>>+} >>>+ >>> static struct platform_device *au1xxx_platform_devices[] __initdata = { >>> &au1xx0_uart_device, >>> &au1xxx_usb_ohci_device, >>>@@ -351,17 +422,25 @@ static struct platform_device >>>*au1xxx_platform_devices[] __initdata = { #ifdef SMBUS_PSC_BASE >>> &pbdb_smbus_device, >>> #endif >>>+ &au1xxx_eth0_device, >>> }; >>> >>> static int __init au1xxx_platform_init(void) >>> { >>> unsigned int uartclk = get_au1x00_uart_baud_base() * 16; >>>- int i; >>>+ int i, ni; >>> >>> /* Fill up uartclk. */ >>> for (i = 0; au1x00_uart_data[i].flags; i++) >>> au1x00_uart_data[i].uartclk = uartclk; >>> >>>+ /* Register second MAC if enabled in pinfunc */ >>>+#ifndef CONFIG_SOC_AU1100 >>>+ ni = (int)((au_readl(SYS_PINFUNC) & (u32)(SYS_PF_NI2)) >> 4); >>>+ if (!(ni + 1)) >> Why so complex, and how can (ni + 1) ever be 0?! :-/ > This is left-over debugging stub, I will rework it. About complexity, this line is taken directly from the au1000_eth driver. I don't see !(ni + 1) there, only: num_ifs = NUM_ETH_INTERFACES - ni; which is correct, unlike what you've written. WBR, Sergei From ralf@linux-mips.org Thu Aug 27 16:14:44 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 27 Aug 2009 16:14:53 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:58553 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492506AbZH0OOj (ORCPT ); Thu, 27 Aug 2009 16:14:39 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id n7REFcg9009398; Thu, 27 Aug 2009 15:15:38 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id n7REFcMT009396; Thu, 27 Aug 2009 15:15:38 +0100 Date: Thu, 27 Aug 2009 15:15:38 +0100 From: Ralf Baechle To: Manuel Lauss Cc: Linux-MIPS , Manuel Lauss Subject: Re: [PATCH 0/2] RFC: Alchemy: multiple timer base address support Message-ID: <20090827141538.GE29984@linux-mips.org> References: <1250957401-14447-1-git-send-email-manuel.lauss@gmail.com> <20090827114907.GD29984@linux-mips.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.19 (2009-01-05) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23941 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Thu, Aug 27, 2009 at 03:01:11PM +0200, Manuel Lauss wrote: > Please yank it for now, I'll resend diffed against -queue at a later date. Done. Ralf From f.fainelli@gmail.com Thu Aug 27 16:55:23 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 27 Aug 2009 16:55:28 +0200 (CEST) Received: from mail-ew0-f225.google.com ([209.85.219.225]:45885 "EHLO mail-ew0-f225.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492941AbZH0OzW convert rfc822-to-8bit (ORCPT ); Thu, 27 Aug 2009 16:55:22 +0200 Received: by ewy25 with SMTP id 25so1254639ewy.33 for ; Thu, 27 Aug 2009 07:55:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:sender:from:to:subject:date :user-agent:cc:references:in-reply-to:mime-version:content-type :content-transfer-encoding:content-disposition:message-id; bh=yiPtsnI0gIMEGRrAI20G324VONu/IyiVViSvO0rQO9M=; b=htybKM/+5G3c1NvsDG/EnnqcHtLEo4K9QWUhqNNCNhsDnIuz0sDvYHasT87JM4PUYQ P4u8OJ42ZD5ngaUMrSA0MbKO5wF3DCPsRO8VVLqKtaaUw1Q0xsNBVgDDAOn9IFf7/caA LlTw1d/v+XWLQvMPYY9rIo9mZIredHpzyQsOY= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:from:to:subject:date:user-agent:cc:references:in-reply-to :mime-version:content-type:content-transfer-encoding :content-disposition:message-id; b=Va1jaS2trcI2KGTb6PRhvfYb5kf99VAMWcN7+dYSF1zuhh8eXCPYdZkd4CmgnQqN7x CsAFz4ej3ibY0FtH8ThuJRvPqboDHkchYFg9YLwKMiEAOk1UCq/W5NR9v61l9+qUn+Tc t/u8ZKaCt9x/IAp0KYzbnNBdzebKVuQb+zloE= Received: by 10.210.2.19 with SMTP id 19mr394910ebb.94.1251384916615; Thu, 27 Aug 2009 07:55:16 -0700 (PDT) Received: from florian.lab.openpattern.org (lab.openpattern.org [82.240.16.241]) by mx.google.com with ESMTPS id 28sm14276eye.20.2009.08.27.07.55.12 (version=TLSv1/SSLv3 cipher=RC4-MD5); Thu, 27 Aug 2009 07:55:14 -0700 (PDT) From: Florian Fainelli To: Sergei Shtylyov Subject: Re: [PATCH 1/2] alchemy: add au1000-eth platform device Date: Thu, 27 Aug 2009 16:55:09 +0200 User-Agent: KMail/1.9.9 Cc: Ralf Baechle , linux-mips@linux-mips.org, Manuel Lauss , David Miller , netdev@vger.kernel.org References: <200908170105.38154.florian@openwrt.org> <200908271442.36306.florian@openwrt.org> <4A969519.7010604@ru.mvista.com> In-Reply-To: <4A969519.7010604@ru.mvista.com> MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 8BIT Content-Disposition: inline Message-Id: <200908271655.11086.florian@openwrt.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23942 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips Hello, Le Thursday 27 August 2009 16:15:53 Sergei Shtylyov, vous avez écrit : > Hello. > > Florian Fainelli wrote: > >>>>>This patch adds the board code to register a per-board au1000-eth > >>>>>platform device to be used wit the au1000-eth platform driver in a > >>>>>subsequent patch. Note that the au1000-eth driver knows about the > >>>>>default driver settings such that we do not need to pass any > >>>>>platform_data informations in most cases except db1x00. > >>>> > >>>> Sigh, NAK... > >>>> Please don't register the SoC device per board, do it in > >>>>alchemy/common/platfrom.c and find a way to pass the board specific > >>>>platform data from the board file there instead -- something like > >>>>arch/arm/mach-davinci/usb.c does. > >>> > >>>Ok, like I promised, this was the per-board device registration. Do you > >>>prefer something like this: > >> > >> I certainly do, but still not in this incarnation... :-) > >> > >>>+static struct au1000_eth_platform_data au1xxx_eth0_platform_data = { > >>>+ .phy1_search_mac0 = 1, > >>>+}; > >> > >> I'm not sure that the default platfrom data is really a great idea... > > > > Can you elaborate a bit more ? We actually need to make the Ethernet MAC > > driver aware of some PHY settings. > > But why do you have the platform data in *this* file, no the board > files? The default setting is to search for a PHY on the corresponding MAC, which is the case for all boards but bosporus, thus it is in this file. No platform data at all would be fine too. > > >>>+#ifndef CONFIG_SOC_AU1100 > >>>+static struct platform_device au1xxx_eth1_device = { > >>>+ .name = "au1000-eth", > >>>+ .id = 1, > >>>+ .num_resources = ARRAY_SIZE(au1xxx_eth1_resources), > >>>+ .resource = au1xxx_eth1_resources, > >> > >> And where's the platfrom data for the second Ethernet? > > > > There is no need to, as the driver originally did not override any > > specific settings on the second MAC (afair). > > Specific settings where, in the driver? Shouldn't all such settings be > bound to the platform data instead? Yes, platform data should handle that for us, what I was trying to explain is that the driver did not configure anything specific for MAC1 already, thus there is no platfo > > >>>+}; > >>>+#endif > >>>+ > >>>+void __init au1xxx_override_eth0_cfg(struct au1000_eth_platform_data > >>>*eth_data) +{ > >>>+ if (!eth_data) > >>>+ return; > >>>+ > >>>+ memcpy(&au1xxx_eth0_platform_data, eth_data, > >>>+ sizeof(struct au1000_eth_platform_data)); > >> > >> Why not just set the pointer in au1xxx_eth0_device. And really, why > >> not make the function more generic, with a prototype like: > > > > For the same reasons as explained below, MAC1 did not need any specific > > change. > > So, the driver can get away without platform data? What does it do in > this case -- I haven't looked at that patch? In that case it searchs for a PHY attached to the MAC, this is what the driver did already. Please have a look at the patch, specifically the part which handles a NULL platform_data. > > >>void __init au1xxx_override_eth_cfg(unsigned port, struct > >> au1000_eth_platform_data *eth_data); > >> > >>>+} > >>>+ > >>> static struct platform_device *au1xxx_platform_devices[] __initdata = { > >>> &au1xx0_uart_device, > >>> &au1xxx_usb_ohci_device, > >>>@@ -351,17 +422,25 @@ static struct platform_device > >>>*au1xxx_platform_devices[] __initdata = { #ifdef SMBUS_PSC_BASE > >>> &pbdb_smbus_device, > >>> #endif > >>>+ &au1xxx_eth0_device, > >>> }; > >>> > >>> static int __init au1xxx_platform_init(void) > >>> { > >>> unsigned int uartclk = get_au1x00_uart_baud_base() * 16; > >>>- int i; > >>>+ int i, ni; > >>> > >>> /* Fill up uartclk. */ > >>> for (i = 0; au1x00_uart_data[i].flags; i++) > >>> au1x00_uart_data[i].uartclk = uartclk; > >>> > >>>+ /* Register second MAC if enabled in pinfunc */ > >>>+#ifndef CONFIG_SOC_AU1100 > >>>+ ni = (int)((au_readl(SYS_PINFUNC) & (u32)(SYS_PF_NI2)) >> 4); > >>>+ if (!(ni + 1)) > >> > >> Why so complex, and how can (ni + 1) ever be 0?! :-/ > > > > This is left-over debugging stub, I will rework it. About complexity, > > this line is taken directly from the au1000_eth driver. > > I don't see !(ni + 1) there, only: > > num_ifs = NUM_ETH_INTERFACES - ni; > > which is correct, unlike what you've written. -- Best regards, Florian Fainelli Email: florian@openwrt.org Web: http://openwrt.org IRC: [florian] on irc.freenode.net ------------------------------- From ralf@linux-mips.org Thu Aug 27 16:55:47 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 27 Aug 2009 16:55:55 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:57827 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492941AbZH0Ozr (ORCPT ); Thu, 27 Aug 2009 16:55:47 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id n7REtt3D015602; Thu, 27 Aug 2009 15:55:55 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id n7REtodA015599; Thu, 27 Aug 2009 15:55:50 +0100 Date: Thu, 27 Aug 2009 15:55:50 +0100 From: Ralf Baechle To: Herbert Xu Cc: David Daney , mpm@selenic.com, linux-mips@linux-mips.org, akpm@linux-foundation.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 1/2] MIPS: Octeon: Add hardware RNG platform device. Message-ID: <20090827145550.GF29984@linux-mips.org> References: <4A8DBB17.5020301@caviumnetworks.com> <1250802623-6526-1-git-send-email-ddaney@caviumnetworks.com> <20090824074730.GA32067@gondor.apana.org.au> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20090824074730.GA32067@gondor.apana.org.au> User-Agent: Mutt/1.5.19 (2009-01-05) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23943 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Mon, Aug 24, 2009 at 05:47:30PM +1000, Herbert Xu wrote: > > Signed-off-by: David Daney > > Acked-by: Herbert Xu Thanks folks; queued for 2.6.32. Ralf From ralf@linux-mips.org Thu Aug 27 16:56:35 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 27 Aug 2009 16:56:42 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:32964 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492965AbZH0O4f (ORCPT ); Thu, 27 Aug 2009 16:56:35 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id n7REuvmL015634; Thu, 27 Aug 2009 15:56:57 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id n7REuvtL015633; Thu, 27 Aug 2009 15:56:57 +0100 Date: Thu, 27 Aug 2009 15:56:57 +0100 From: Ralf Baechle To: Herbert Xu Cc: David Daney , mpm@selenic.com, linux-mips@linux-mips.org, akpm@linux-foundation.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 2/2] hw_random: Add hardware RNG for Octeon SOCs. Message-ID: <20090827145657.GG29984@linux-mips.org> References: <4A8DBB17.5020301@caviumnetworks.com> <1250802623-6526-2-git-send-email-ddaney@caviumnetworks.com> <20090824074745.GB32067@gondor.apana.org.au> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20090824074745.GB32067@gondor.apana.org.au> User-Agent: Mutt/1.5.19 (2009-01-05) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23944 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Mon, Aug 24, 2009 at 05:47:45PM +1000, Herbert Xu wrote: > On Thu, Aug 20, 2009 at 02:10:23PM -0700, David Daney wrote: > > Signed-off-by: David Daney > > Acked-by: Herbert Xu Queued for 2.6.32 after fixing the space followed by tab mess in Kconfig. Thanks, Ralf From manuel.lauss@googlemail.com Thu Aug 27 19:21:29 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 27 Aug 2009 19:21:36 +0200 (CEST) Received: from mail-ew0-f225.google.com ([209.85.219.225]:49405 "EHLO mail-ew0-f225.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1493077AbZH0RV3 (ORCPT ); Thu, 27 Aug 2009 19:21:29 +0200 Received: by ewy25 with SMTP id 25so1397283ewy.33 for ; Thu, 27 Aug 2009 10:21:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer; bh=CR1+DfucO1IHOj8yF1O5mSiGkZpeiJn7Dz5pz9ViUNc=; b=UqVtNbj/HwnW8lHhyfNf4pizbvbUW5by1vA0/6f1SHO/JTUdIFmqKbJ8N6d0HGowdD 8pTopu3KnJEgLxSLuf/OCtGA3YzDSt1TXbAUZY3U58XAhV5e0sSuC9XnCmOSbtHXY3pw 88dNfRGhWrN0ZqMxSPpmIqYqIPpIzkdyMTAw0= DomainKey-Signature: a=rsa-sha1; c=nofws; d=googlemail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer; b=nR8cYJWRXwJEtNx0ouuFzdFhQik8i7+GGV53M0fPXRmeVk0udEW7m6yCJOcQT8q5kX HA2W/EeJ9sZmVimq5aHXlZC8zu2xLmgCvwL+YMRk13/h3i37uEfgUk61Ow+3Di76I+Rs fVw4ZVH1/wHix4qcO92a2T8i6PiuoiQj2ZAzE= Received: by 10.216.6.198 with SMTP id 48mr1864567wen.200.1251393683295; Thu, 27 Aug 2009 10:21:23 -0700 (PDT) Received: from localhost.localdomain (p5496E57B.dip.t-dialin.net [84.150.229.123]) by mx.google.com with ESMTPS id g9sm1537564gvc.13.2009.08.27.10.21.21 (version=TLSv1/SSLv3 cipher=RC4-MD5); Thu, 27 Aug 2009 10:21:22 -0700 (PDT) From: Manuel Lauss To: Linux-MIPS , Ralf Baechle Cc: Manuel Lauss Subject: [PATCH v2] Alchemy: override loops_per_jiffy detection Date: Thu, 27 Aug 2009 19:21:18 +0200 Message-Id: <1251393678-28607-1-git-send-email-manuel.lauss@gmail.com> X-Mailer: git-send-email 1.6.4 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23945 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips loops_per_jiffy depends on coreclk speed; preset it instead of letting the kernel waste precious microseconds trying to approximate it. Signed-off-by: Manuel Lauss --- V2: no need to exclude MACH_ALCHEMY from GENERIC_CALIBRATE_DELAY setting preset_lpj early is enough. As always, run-tested on DB1200 and another Au1200 system. arch/mips/alchemy/common/setup.c | 4 ++++ 1 files changed, 4 insertions(+), 0 deletions(-) diff --git a/arch/mips/alchemy/common/setup.c b/arch/mips/alchemy/common/setup.c index 3f036b3..6184baa 100644 --- a/arch/mips/alchemy/common/setup.c +++ b/arch/mips/alchemy/common/setup.c @@ -27,6 +27,7 @@ #include #include +#include #include #include @@ -53,6 +54,9 @@ void __init plat_mem_setup(void) printk(KERN_INFO "(PRId %08x) @ %lu.%02lu MHz\n", read_c0_prid(), est_freq / 1000000, ((est_freq % 1000000) * 100) / 1000000); + /* this is faster than wasting cycles trying to approximate it */ + preset_lpj = (est_freq >> 1) / HZ; + _machine_restart = au1000_restart; _machine_halt = au1000_halt; pm_power_off = au1000_power_off; -- 1.6.4 From wim@iguana.be Thu Aug 27 22:47:27 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 27 Aug 2009 22:47:34 +0200 (CEST) Received: from mailrelay004.isp.belgacom.be ([195.238.6.170]:54332 "EHLO mailrelay004.isp.belgacom.be" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1493289AbZH0Ur1 (ORCPT ); Thu, 27 Aug 2009 22:47:27 +0200 X-Belgacom-Dynamic: yes X-IronPort-Anti-Spam-Filtered: true X-IronPort-Anti-Spam-Result: ApoEALmMlkpR92Cn/2dsb2JhbADYcQmEEAU Received: from 167.96-247-81.adsl-dyn.isp.belgacom.be (HELO infomag) ([81.247.96.167]) by relay.skynet.be with ESMTP; 27 Aug 2009 22:47:20 +0200 Received: from wim by infomag with local (Exim 4.69) (envelope-from ) id 1MglsN-00021L-Vs; Thu, 27 Aug 2009 22:47:19 +0200 Date: Thu, 27 Aug 2009 22:47:19 +0200 From: Wim Van Sebroeck To: Florian Fainelli Cc: ralf Baechle , linux-mips@linux-mips.org Subject: Re: [PATCH 2/2] ar7_wdt: convert to become a platform driver Message-ID: <20090827204719.GM29382@infomag.iguana.be> References: <200907151210.20294.florian@openwrt.org> <200908111452.28418.florian@openwrt.org> <20090811130133.GH4302@infomag.iguana.be> <200908111517.09726.florian@openwrt.org> MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="r7U+bLA8boMOj+mD" Content-Disposition: inline In-Reply-To: <200908111517.09726.florian@openwrt.org> User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23946 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wim@iguana.be Precedence: bulk X-list: linux-mips --r7U+bLA8boMOj+mD Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Hi Florian, > > > > From: Florian Fainelli > > > > Subject: [PATCH 2/2 v2] ar7_wdt: convert to become a platform driver > > > > > > > > This patch converts the ar7_wdt driver to become > > > > a platform driver. The AR7 SoC specific identification > > > > and base register calculation is performed by the board > > > > code, therefore we no longer need to have access to > > > > ar7_chip_id. We also remove the reboot notifier code to > > > > use the platform shutdown method as Wim suggested. > > > > > > > > Signed-off-by: Florian Fainelli > > > > Signed-off-by: Wim Van Sebroeck > > > > > > Any news on this patch ? > > > > This one was ok for me. I think we agreed that Ralf would take it up in his > > tree. I can also take it up in my next tree still. > > Oh, I did not understand that sorry, I thought Ralf would take the first one > which is MIPS-specific. I added the second patch to my tree, but saw that the error handling on probe could be improved. Can you test attached patch? Thanks in advance, Wim. --r7U+bLA8boMOj+mD Content-Type: text/x-diff; charset=us-ascii Content-Disposition: attachment; filename="ar7_wdt-fix-probe-errors.diff" diff --git a/drivers/watchdog/ar7_wdt.c b/drivers/watchdog/ar7_wdt.c index 82855b0..2e94b71 100644 --- a/drivers/watchdog/ar7_wdt.c +++ b/drivers/watchdog/ar7_wdt.c @@ -295,7 +295,7 @@ static int __devinit ar7_wdt_probe(struct platform_device *pdev) if (!ar7_wdt) { printk(KERN_ERR DRVNAME ": could not ioremap registers\n"); rc = -ENXIO; - goto out; + goto out_mem_region; } ar7_wdt_disable_wdt(); @@ -311,6 +311,7 @@ static int __devinit ar7_wdt_probe(struct platform_device *pdev) out_alloc: iounmap(ar7_wdt); +out_mem_region: release_mem_region(ar7_regs_wdt->start, resource_size(ar7_regs_wdt)); out: return rc; --r7U+bLA8boMOj+mD-- From miloody@gmail.com Fri Aug 28 08:41:51 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 28 Aug 2009 08:41:58 +0200 (CEST) Received: from mail-px0-f172.google.com ([209.85.216.172]:36654 "EHLO mail-px0-f172.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492384AbZH1Glv (ORCPT ); Fri, 28 Aug 2009 08:41:51 +0200 Received: by pxi2 with SMTP id 2so1676819pxi.0 for ; Thu, 27 Aug 2009 23:41:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:date:message-id:subject :from:to:content-type; bh=mrZAndV42GxvsASaBpCiRp75DrHOCIxYDKnBWTRTUKY=; b=ImXWTXAwrV2C7Sz0lfOlJ1PopJuiL0x5ULCBwto1ruWcZMyUQGLe92AeNTUqQKfME0 yeCs1TBGtdPMVjkL44u2OYp6amtVLrwWikxPPEeE8kXSxe8keE4idicnjbkCBnSgnGjK /3HfZghJv+ed2eKnYe0gbourYvBrXgsIh/2aI= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:date:message-id:subject:from:to:content-type; b=axPLC1PtzQhf5JNHPWrhaVeQISiBElptwo8oiS1qqMXwFlay6a7NxZCMJB/kcoRtFw 4LrLp4FWbqATRgkpjHJyrWuudiH/2m5JdZ4pHVgsRET3l73ix7cxm1ExGdNhBxPWMRx5 OcP+I88EhB4OwwArd5HenQeq8JNEETLl+cZMQ= MIME-Version: 1.0 Received: by 10.142.209.19 with SMTP id h19mr40444wfg.129.1251441701631; Thu, 27 Aug 2009 23:41:41 -0700 (PDT) Date: Fri, 28 Aug 2009 14:41:41 +0800 Message-ID: <3a665c760908272341h1b3d21afmda7415282c40261b@mail.gmail.com> Subject: how to make /dev/random work? From: loody To: Kernel Newbies , Linux MIPS Mailing List Content-Type: text/plain; charset=ISO-8859-1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23947 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: miloody@gmail.com Precedence: bulk X-list: linux-mips Dear all: I made linux running on Mips machine. Right now I found the /dev/random doesn't work properly, since I use "dd if=/dev/random of=/tmp/random.txt", it stops working. If I use "cat /dev/random", it will not pop out anything. Is there any setting I forget while make menuconfig or should i add another driver for /dev/random such that I can make /dev/random work? appreciate your help, miloody From ralf@linux-mips.org Fri Aug 28 09:46:09 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 28 Aug 2009 09:46:16 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:45447 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492330AbZH1HqJ (ORCPT ); Fri, 28 Aug 2009 09:46:09 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id n7S7lALU011660 for ; Fri, 28 Aug 2009 08:47:10 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id n7S7l9lw011658 for linux-mips@linux-mips.org; Fri, 28 Aug 2009 08:47:09 +0100 Date: Fri, 28 Aug 2009 08:47:09 +0100 From: Ralf Baechle To: linux-mips@linux-mips.org Subject: MTX build failure Message-ID: <20090828074709.GA11637@linux-mips.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit User-Agent: Mutt/1.5.19 (2009-01-05) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23948 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips CC drivers/input/keyboard/gpio_keys.o /home/ralf/src/linux/linux-mips/drivers/input/keyboard/gpio_keys.c: In function ‘gpio_keys_probe’: /home/ralf/src/linux/linux-mips/drivers/input/keyboard/gpio_keys.c:123: error: implicit declaration of function ‘gpio_request’ /home/ralf/src/linux/linux-mips/drivers/input/keyboard/gpio_keys.c:135: error: implicit declaration of function ‘gpio_free’ make[5]: *** [drivers/input/keyboard/gpio_keys.o] Error 1 make[4]: *** [drivers/input/keyboard] Error 2 make[3]: *** [drivers/input] Error 2 make[2]: *** [drivers] Error 2 make[1]: *** [sub-make] Error 2 Ralf From ralf@linux-mips.org Fri Aug 28 09:57:33 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 28 Aug 2009 09:57:41 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:58828 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492497AbZH1H5d (ORCPT ); Fri, 28 Aug 2009 09:57:33 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id n7S7wXt1018102; Fri, 28 Aug 2009 08:58:33 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id n7S7wXU3018100; Fri, 28 Aug 2009 08:58:33 +0100 Date: Fri, 28 Aug 2009 08:58:33 +0100 From: Ralf Baechle To: Alexey Dobriyan Cc: linux-mips@linux-mips.org Subject: Re: [PATCH] mips: fix compilation of mips-lasat Message-ID: <20090828075833.GA11775@linux-mips.org> References: <20090812195927.GA2647@x200.localdomain> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20090812195927.GA2647@x200.localdomain> User-Agent: Mutt/1.5.19 (2009-01-05) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23949 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Wed, Aug 12, 2009 at 11:59:27PM +0400, Alexey Dobriyan wrote: > Header needed for current_cpu_data which expands to smp_processor_id(). > However, linux/smp.h can't be included into asm/cpu-info.h due to > horrible circular dependencies, so plug it here. > > Signed-off-by: Alexey Dobriyan Thanks, applied! Ralf From f.fainelli@gmail.com Fri Aug 28 10:26:32 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 28 Aug 2009 10:26:38 +0200 (CEST) Received: from mail-ew0-f225.google.com ([209.85.219.225]:59920 "EHLO mail-ew0-f225.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492498AbZH1I0c convert rfc822-to-8bit (ORCPT ); Fri, 28 Aug 2009 10:26:32 +0200 Received: by ewy25 with SMTP id 25so1874429ewy.33 for ; Fri, 28 Aug 2009 01:26:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:sender:from:to:subject:date :user-agent:cc:references:in-reply-to:mime-version:content-type :content-transfer-encoding:content-disposition:message-id; bh=er2hxpAAS053UbFAON/5AotgwJIZsoA/vLHM+Y2yznA=; b=rUSWNO6/zgr2CDj82b5H7GXI0VsrtVVXZhuo0fpIU9zPYi1rg/3wQlzzjiect0CH/Y nBrS1AiJQSYRMvDytI6EENwglUmP0cbDrcTvwvebIE4ni6UrMfB34R4+H/MyTaLw+wEe egSz49nTISTem3D1vbo5HOI4hpGP6nArHwhYY= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:from:to:subject:date:user-agent:cc:references:in-reply-to :mime-version:content-type:content-transfer-encoding :content-disposition:message-id; b=OTTcFQMDah+1PqdPz8sY8qlSz8iFIdAuB3tmQIB/GI5d4NDkun3yDnzoJyMr4sEDfW L0OmGy5w1mN4NRAStloDSBdiZBC1Fpy5Dc197eUP+DUvp7/2exC0hjOdm3FFS2z+c3Ih GrIVG4P+BXbIuxsMkJkUO1BuFjxgYnV+lInqw= Received: by 10.210.93.27 with SMTP id q27mr902149ebb.9.1251447986773; Fri, 28 Aug 2009 01:26:26 -0700 (PDT) Received: from florian.lab.openpattern.org (lab.openpattern.org [82.240.16.241]) by mx.google.com with ESMTPS id 28sm1577521eye.36.2009.08.28.01.26.25 (version=TLSv1/SSLv3 cipher=RC4-MD5); Fri, 28 Aug 2009 01:26:26 -0700 (PDT) From: Florian Fainelli To: Ralf Baechle Subject: Re: MTX build failure Date: Fri, 28 Aug 2009 10:26:15 +0200 User-Agent: KMail/1.9.9 Cc: linux-mips@linux-mips.org References: <20090828074709.GA11637@linux-mips.org> In-Reply-To: <20090828074709.GA11637@linux-mips.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8BIT Content-Disposition: inline Message-Id: <200908281026.17446.florian@openwrt.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23950 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips Le Friday 28 August 2009 09:47:09 Ralf Baechle, vous avez écrit : > CC drivers/input/keyboard/gpio_keys.o > /home/ralf/src/linux/linux-mips/drivers/input/keyboard/gpio_keys.c: In > function ‘gpio_keys_probe’: > /home/ralf/src/linux/linux-mips/drivers/input/keyboard/gpio_keys.c:123: > error: implicit declaration of function ‘gpio_request’ > /home/ralf/src/linux/linux-mips/drivers/input/keyboard/gpio_keys.c:135: > error: implicit declaration of function ‘gpio_free’ make[5]: *** > [drivers/input/keyboard/gpio_keys.o] Error 1 > make[4]: *** [drivers/input/keyboard] Error 2 > make[3]: *** [drivers/input] Error 2 > make[2]: *** [drivers] Error 2 > make[1]: *** [sub-make] Error 2 Will see what happens, thanks for notifying. -- Best regards, Florian Fainelli Email: florian@openwrt.org Web: http://openwrt.org IRC: [florian] on irc.freenode.net ------------------------------- From manuel.lauss@googlemail.com Fri Aug 28 10:53:49 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 28 Aug 2009 10:53:55 +0200 (CEST) Received: from mail-bw0-f208.google.com ([209.85.218.208]:60042 "EHLO mail-bw0-f208.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492499AbZH1Ixt (ORCPT ); Fri, 28 Aug 2009 10:53:49 +0200 Received: by bwz4 with SMTP id 4so1710402bwz.0 for ; Fri, 28 Aug 2009 01:53:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=domainkey-signature:received:received:message-id:date:from :organization:user-agent:mime-version:to:cc:subject:references :in-reply-to:content-type:content-transfer-encoding; bh=vcuyUxjUaqDqwd9cfczWKXlav7BluMAy/F4xk7REW7U=; b=JBvi22lhChA5F6PbW/bEaiSj7svkdbbRY602itLbAo+PRh5TUzuPfogvtkPTV3f7Y8 CL4ZSyBp0gqHnNPKUY1aAf/lO0J+CqoaHu6KagqDs+M+4Ka6HqKZ4h+qLKGf6W7Ly7BG RBaSOe9q7bkUEwVC62mI8oaSr/PMb0OkmTLGQ= DomainKey-Signature: a=rsa-sha1; c=nofws; d=googlemail.com; s=gamma; h=message-id:date:from:organization:user-agent:mime-version:to:cc :subject:references:in-reply-to:content-type :content-transfer-encoding; b=fyPoqhauH8d4rPO1gXeldY0ZyNOc5gZTAGHegSwGHYauFRhTZ1ThCg+azuCOqXRxtw XqNJxMsDyr71X4Ta/tRq0SmezDZV8fQDK7/L/c1AZO0dWM8bIQHmPLKOW1WBS5vBVcBD RsiV6huws4CF9gRzL+y+dtlbztzQkujkOvYDo= Received: by 10.103.126.33 with SMTP id d33mr135887mun.109.1251449622927; Fri, 28 Aug 2009 01:53:42 -0700 (PDT) Received: from ?0.0.0.0? (p5496FC4A.dip.t-dialin.net [84.150.252.74]) by mx.google.com with ESMTPS id j9sm4237134mue.52.2009.08.28.01.53.39 (version=TLSv1/SSLv3 cipher=RC4-MD5); Fri, 28 Aug 2009 01:53:42 -0700 (PDT) Message-ID: <4A979B0E.106@gmail.com> Date: Fri, 28 Aug 2009 10:53:34 +0200 From: Manuel Lauss Organization: Private User-Agent: Thunderbird 2.0.0.22 (X11/20090825) MIME-Version: 1.0 To: Ralf Baechle , Florian Fainelli CC: Linux-MIPS Subject: Re: MTX build failure References: <20090828074709.GA11637@linux-mips.org> In-Reply-To: <20090828074709.GA11637@linux-mips.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23951 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips Ralf Baechle wrote: > CC drivers/input/keyboard/gpio_keys.o > /home/ralf/src/linux/linux-mips/drivers/input/keyboard/gpio_keys.c: In function ‘gpio_keys_probe’: > /home/ralf/src/linux/linux-mips/drivers/input/keyboard/gpio_keys.c:123: error: implicit declaration of function ‘gpio_request’ > /home/ralf/src/linux/linux-mips/drivers/input/keyboard/gpio_keys.c:135: error: implicit declaration of function ‘gpio_free’ > make[5]: *** [drivers/input/keyboard/gpio_keys.o] Error 1 > make[4]: *** [drivers/input/keyboard] Error 2 > make[3]: *** [drivers/input] Error 2 > make[2]: *** [drivers] Error 2 > make[1]: *** [sub-make] Error 2 Either something like the patch below, or adding stubs for gpio_request/gpio_free to asm/mach-au1x00/gpio-au1000.h in the CONFIG_GPIOLIB=n case should fix it. diff --git a/arch/mips/alchemy/Kconfig b/arch/mips/alchemy/Kconfig index 1e0a6df..f0c930a 100644 --- a/arch/mips/alchemy/Kconfig +++ b/arch/mips/alchemy/Kconfig @@ -20,6 +20,7 @@ config MIPS_MTX1 select HW_HAS_PCI select SOC_AU1500 select SYS_SUPPORTS_LITTLE_ENDIAN + select GPIOLIB config MIPS_BOSPORUS bool "Alchemy Bosporus board" Manuel Lauss From f.fainelli@gmail.com Fri Aug 28 11:08:11 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 28 Aug 2009 11:08:17 +0200 (CEST) Received: from mail-ew0-f225.google.com ([209.85.219.225]:36909 "EHLO mail-ew0-f225.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492470AbZH1JIL convert rfc822-to-8bit (ORCPT ); Fri, 28 Aug 2009 11:08:11 +0200 Received: by ewy25 with SMTP id 25so1896835ewy.33 for ; Fri, 28 Aug 2009 02:08:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:sender:from:to:subject:date :user-agent:cc:references:in-reply-to:mime-version:content-type :content-transfer-encoding:content-disposition:message-id; bh=JXnLD3uzb+dd2tBln2OifXVUepWrCQkMJfqbEsX9UiI=; b=nRGX9PNLk04wwE2k2IBb6D3Lu+VdQnYLmbStGbw05zVuz+Ecz7cg9VQC7WF+kygbWy GTa71o4XQ/B1MKk3GaARn5bVkNWTJroSAzIkTYrpxTQOk4R5ua919dz3pkkQ3oZIGoEI x+kNOg6es404k6O4pM0l/Qdlu59IuahCc3wq0= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:from:to:subject:date:user-agent:cc:references:in-reply-to :mime-version:content-type:content-transfer-encoding :content-disposition:message-id; b=PmpEOPavp7/GIvCLBO0JSBDf8BnL/0ESCyiOhO5KN5KiEMwsBF//cBaSmDhtZIPvq0 o5QVT63eUy3G7m9zHXJv9/uR75+LedJRE5Aj5YjARTRqWjipMRAU+H7+6ZrVPPhjSv88 dJE4pe64i4n0DQBe7W6nRza4F8z/qoUmTkTPA= Received: by 10.210.115.15 with SMTP id n15mr8656261ebc.43.1251450484742; Fri, 28 Aug 2009 02:08:04 -0700 (PDT) Received: from florian.lab.openpattern.org (lab.openpattern.org [82.240.16.241]) by mx.google.com with ESMTPS id 10sm1747172eyz.9.2009.08.28.02.08.03 (version=TLSv1/SSLv3 cipher=RC4-MD5); Fri, 28 Aug 2009 02:08:04 -0700 (PDT) From: Florian Fainelli To: Manuel Lauss Subject: Re: MTX build failure Date: Fri, 28 Aug 2009 11:07:59 +0200 User-Agent: KMail/1.9.9 Cc: Ralf Baechle , Linux-MIPS References: <20090828074709.GA11637@linux-mips.org> <4A979B0E.106@gmail.com> In-Reply-To: <4A979B0E.106@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8BIT Content-Disposition: inline Message-Id: <200908281108.00945.florian@openwrt.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23952 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips Le Friday 28 August 2009 10:53:34 Manuel Lauss, vous avez écrit : > Ralf Baechle wrote: > > CC drivers/input/keyboard/gpio_keys.o > > /home/ralf/src/linux/linux-mips/drivers/input/keyboard/gpio_keys.c: In > > function ‘gpio_keys_probe’: > > /home/ralf/src/linux/linux-mips/drivers/input/keyboard/gpio_keys.c:123: > > error: implicit declaration of function ‘gpio_request’ > > /home/ralf/src/linux/linux-mips/drivers/input/keyboard/gpio_keys.c:135: > > error: implicit declaration of function ‘gpio_free’ make[5]: *** > > [drivers/input/keyboard/gpio_keys.o] Error 1 > > make[4]: *** [drivers/input/keyboard] Error 2 > > make[3]: *** [drivers/input] Error 2 > > make[2]: *** [drivers] Error 2 > > make[1]: *** [sub-make] Error 2 > > Either something like the patch below, or adding stubs for > gpio_request/gpio_free to asm/mach-au1x00/gpio-au1000.h in the > CONFIG_GPIOLIB=n case should fix it. The patch below fixes it for me, so feel free to add my: Tested-by: Florian Fainelli > > diff --git a/arch/mips/alchemy/Kconfig b/arch/mips/alchemy/Kconfig > index 1e0a6df..f0c930a 100644 > --- a/arch/mips/alchemy/Kconfig > +++ b/arch/mips/alchemy/Kconfig > @@ -20,6 +20,7 @@ config MIPS_MTX1 > select HW_HAS_PCI > select SOC_AU1500 > select SYS_SUPPORTS_LITTLE_ENDIAN > + select GPIOLIB > > config MIPS_BOSPORUS > bool "Alchemy Bosporus board" > > > Manuel Lauss -- Best regards, Florian Fainelli Email: florian@openwrt.org Web: http://openwrt.org IRC: [florian] on irc.freenode.net ------------------------------- From f.fainelli@gmail.com Fri Aug 28 11:09:56 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 28 Aug 2009 11:10:01 +0200 (CEST) Received: from ey-out-1920.google.com ([74.125.78.149]:17305 "EHLO ey-out-1920.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492470AbZH1JJz convert rfc822-to-8bit (ORCPT ); Fri, 28 Aug 2009 11:09:55 +0200 Received: by ey-out-1920.google.com with SMTP id 13so356562eye.52 for ; Fri, 28 Aug 2009 02:09:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:sender:from:to:subject:date :user-agent:cc:references:in-reply-to:mime-version:content-type :content-transfer-encoding:content-disposition:message-id; bh=KP4OEAgTQWvytMk40XIbQTV4VzrLCg+xhR3dTCrR+d8=; b=iWs7Yu+h8OW0l0Klzbd/suWND315WmfknLUwiYsNtPjnqbCCU9OyjjM5sQc8x7MRH1 f2b/J/uOMgyO9BkK7KEcJVbX876SFFxtrlEq3iuWJCCvnzsi1YB+uD/gaPIl3A9xvWn+ FWEoAGxVODC7Kp+iASgz9ODk5KCwSO9b/SXq0= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:from:to:subject:date:user-agent:cc:references:in-reply-to :mime-version:content-type:content-transfer-encoding :content-disposition:message-id; b=t+LITZXEm59kY+5B+C494i4nVMpXeh0nZZ8QkIKl+5/q1u4FuPkSfipE9f6KBHdmrA fjUrafpdsfjZFmsvg+ysiwZjONvzBs94SzSuc3lY9JQKpCL1SX/ZGjY3UFheUnPk1lzE GgxXil80hchhIthjVEmePaet0H7YCGGWlc0NU= Received: by 10.211.200.7 with SMTP id c7mr10904621ebq.54.1251450594534; Fri, 28 Aug 2009 02:09:54 -0700 (PDT) Received: from florian.lab.openpattern.org (lab.openpattern.org [82.240.16.241]) by mx.google.com with ESMTPS id 10sm1373522eyd.37.2009.08.28.02.09.53 (version=TLSv1/SSLv3 cipher=RC4-MD5); Fri, 28 Aug 2009 02:09:53 -0700 (PDT) From: Florian Fainelli To: "wilbur.chan" Subject: Re: kexec on mips failed Date: Fri, 28 Aug 2009 11:09:51 +0200 User-Agent: KMail/1.9.9 Cc: nschichan@freebox.fr, linux-mips@linux-mips.org References: In-Reply-To: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8BIT Content-Disposition: inline Message-Id: <200908281109.52499.florian@openwrt.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23953 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips Hi, Le Sunday 16 August 2009 18:20:56 wilbur.chan, vous avez écrit : > Hi,Nicolas, > > > I've got some problem with kexec on mips32... > > > in your code for kexec on mips32, there is a relocate_new_kernel function . > > > In the end of this function , it jump to kexec_start_address by 'j s1' > > > > Because I changed the kexec-tools code ,in the hope that, it > simplely passed the new kernel segment data into the old kernel.(so > > I didn't pass the command-line segment in, in my code, there is just > one segment , segment[0] = kernel_data). > > > So I need to change register s1 to the new kernel entry address, and > jump to new kernel directly. > > > > In my vmlinux, the entry is 0x802b0000，so I let image->start = > 0x2b0000，and invoke relocate_new_kernel. > > > However, whether I changed kexec_start_address to 0x802b0000 or > 0x2b0000 , the 'j s1' seemed taking no effect? Should not you add a nop right after the j s1 in order to fill in the branch delay slot with an instruction which does nothing ? > > > (I wrote 88 to address0xa1230000 before 'j s1' , it succedd .I also > wrote 78 to address 0xa1230000 in the beginning > > of head.S of the new kernel , but failed. And I reset the board to > uboot mode, used 'md 0x802b0400' to display the new kernel > > in ram, it is identical to the objdump content of the vmlinux. So I > guess, this problem lays in the failing of 'j 0x802b0000' > > or 'j 0x2b0000'. I don't know why 'j s1' failed , any suggestions > about this ? Thank you very much. > > regads, > > Wilbur -- Best regards, Florian Fainelli Email: florian@openwrt.org Web: http://openwrt.org IRC: [florian] on irc.freenode.net ------------------------------- From f.fainelli@gmail.com Fri Aug 28 11:12:10 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 28 Aug 2009 11:12:15 +0200 (CEST) Received: from ey-out-1920.google.com ([74.125.78.145]:45579 "EHLO ey-out-1920.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492499AbZH1JMJ convert rfc822-to-8bit (ORCPT ); Fri, 28 Aug 2009 11:12:09 +0200 Received: by ey-out-1920.google.com with SMTP id 13so356842eye.52 for ; Fri, 28 Aug 2009 02:12:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:sender:from:to:subject:date :user-agent:cc:references:in-reply-to:mime-version:content-type :content-transfer-encoding:content-disposition:message-id; bh=mde6ccVmM1eG7sKYtNL9zcgb/P6DStnRvyvSB2iJxMI=; b=wzrWFmiRiW4VfFuJf3X9Q2xgnJTtT5VCDj8SHp9pq3AUAjwshpX9VNBq+yG6WJa5Oj qglinSUSUTwsR7byNJXswaWDJ3D2pJLvrqGsfuqt1Fc9zp7cFHlh1tdFx67dIao0Imdr SNRhY2i/QyCHjvRJEgeHQGMrrxhc0tsYUjdqI= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:from:to:subject:date:user-agent:cc:references:in-reply-to :mime-version:content-type:content-transfer-encoding :content-disposition:message-id; b=Yejy7QKaqemxpTofXCtjZIhDJBSlC6RhBG3Gu8XN4ju071UimuHIvqeEUXxEJdCSRv LwrmpEpMrkPYUQG72NgODrAp6ElUgxxuX01I7Rg2X5Nji4APf298FZLQDUMs6229Qo4r gbgiHryt7YVzkMu93bNgFFvJn3TGT1xdKrbho= Received: by 10.210.206.12 with SMTP id d12mr947161ebg.32.1251450728702; Fri, 28 Aug 2009 02:12:08 -0700 (PDT) Received: from florian.lab.openpattern.org (lab.openpattern.org [82.240.16.241]) by mx.google.com with ESMTPS id 28sm1541755eye.20.2009.08.28.02.12.07 (version=TLSv1/SSLv3 cipher=RC4-MD5); Fri, 28 Aug 2009 02:12:08 -0700 (PDT) From: Florian Fainelli To: loody Subject: Re: how to make /dev/random work? Date: Fri, 28 Aug 2009 11:12:05 +0200 User-Agent: KMail/1.9.9 Cc: Kernel Newbies , Linux MIPS Mailing List References: <3a665c760908272341h1b3d21afmda7415282c40261b@mail.gmail.com> In-Reply-To: <3a665c760908272341h1b3d21afmda7415282c40261b@mail.gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 8BIT Content-Disposition: inline Message-Id: <200908281112.06100.florian@openwrt.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23954 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips Hi, Le Friday 28 August 2009 08:41:41 loody, vous avez écrit : > Dear all: > I made linux running on Mips machine. > Right now I found the /dev/random doesn't work properly, since I use > "dd if=/dev/random of=/tmp/random.txt", it stops working. > If I use "cat /dev/random", it will not pop out anything. > > Is there any setting I forget while make menuconfig or should i add > another driver for /dev/random such that I can make /dev/random work? > appreciate your help, Could it be that your system does not generate enough entropy so you end up in having nothing going out from /dev/random ? In case your system has very little entropy, better use /dev/urandom. -- Best regards, Florian Fainelli Email: florian@openwrt.org Web: http://openwrt.org IRC: [florian] on irc.freenode.net ------------------------------- From manuel.lauss@googlemail.com Fri Aug 28 11:27:06 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 28 Aug 2009 11:27:12 +0200 (CEST) Received: from mail-bw0-f208.google.com ([209.85.218.208]:56639 "EHLO mail-bw0-f208.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492470AbZH1J1G (ORCPT ); Fri, 28 Aug 2009 11:27:06 +0200 Received: by bwz4 with SMTP id 4so1725693bwz.0 for ; Fri, 28 Aug 2009 02:27:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=domainkey-signature:received:received:message-id:date:from :organization:user-agent:mime-version:to:cc:subject:references :in-reply-to:content-type:content-transfer-encoding; bh=bBi6HY0lajcBiZ2mta3idkn/6A2UVElCPSUrujYSL58=; b=vUjIexgOxWO0h2THO1bVcsUU/ZwYYGUHuXsom7+KVqkdtbi79jyBOMrvK9cXQEkROe ZeLAxrn18bB1wvASBFINZByT4B1TomtbPXVI2xBY9h2WDdjcjg4Ok2aVVImlesZETHDu pe8jL75uDcaoOB79hJuHrfDcildc2nSuhHiSc= DomainKey-Signature: a=rsa-sha1; c=nofws; d=googlemail.com; s=gamma; h=message-id:date:from:organization:user-agent:mime-version:to:cc :subject:references:in-reply-to:content-type :content-transfer-encoding; b=KlPNv9xsHGqXfL57b+F819Poela0+/SFVBI8SF0/guZ4oVYPgPp6AVkwMBa4Rmnqcq HBmsjdeNQR+LjYFw79Xhumvluj1YETmeElIChbW1zKrY1AlynyhvVXv5uc60BdWo1DLr uAOJLU70rSLHW44l9gUnIYbF0GTqrq+gkNFoA= Received: by 10.103.125.23 with SMTP id c23mr150016mun.41.1251451621260; Fri, 28 Aug 2009 02:27:01 -0700 (PDT) Received: from ?0.0.0.0? (p5496FC4A.dip.t-dialin.net [84.150.252.74]) by mx.google.com with ESMTPS id 23sm4265695mum.35.2009.08.28.02.26.59 (version=TLSv1/SSLv3 cipher=RC4-MD5); Fri, 28 Aug 2009 02:27:00 -0700 (PDT) Message-ID: <4A97A2E2.2090108@gmail.com> Date: Fri, 28 Aug 2009 11:26:58 +0200 From: Manuel Lauss Organization: Private User-Agent: Thunderbird 2.0.0.22 (X11/20090825) MIME-Version: 1.0 To: Ralf Baechle , Florian Fainelli CC: Linux-MIPS Subject: Re: MTX build failure References: <20090828074709.GA11637@linux-mips.org> <4A979B0E.106@gmail.com> In-Reply-To: <4A979B0E.106@gmail.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23955 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips I wrote: > Ralf Baechle wrote: >> CC drivers/input/keyboard/gpio_keys.o >> /home/ralf/src/linux/linux-mips/drivers/input/keyboard/gpio_keys.c: In function ‘gpio_keys_probe’: >> /home/ralf/src/linux/linux-mips/drivers/input/keyboard/gpio_keys.c:123: error: implicit declaration of function ‘gpio_request’ >> /home/ralf/src/linux/linux-mips/drivers/input/keyboard/gpio_keys.c:135: error: implicit declaration of function ‘gpio_free’ >> make[5]: *** [drivers/input/keyboard/gpio_keys.o] Error 1 >> make[4]: *** [drivers/input/keyboard] Error 2 >> make[3]: *** [drivers/input] Error 2 >> make[2]: *** [drivers] Error 2 >> make[1]: *** [sub-make] Error 2 > > Either something like the patch below, or adding stubs for > gpio_request/gpio_free to asm/mach-au1x00/gpio-au1000.h in the > CONFIG_GPIOLIB=n case should fix it. Florian, Ralf, I prefer the latter approach; saves everyone from having to add #ifdef CONFIG_GPIOLIB around gpio_request() calls. Here's an untested patch. What do you think? If it works for you, please add it to your patchqueue! Thanks! --- From: Manuel Lauss Subject: [PATCH] Alchemy: add gpio_request/gpio_free stubs for CONFIG_GPIOLIB=n Some drivers use gpio_request/gpio_free regardless of whether gpiolib is actually built; add stubs to work around the ensuing compile failures. Signed-off-by: Manuel Lauss --- arch/mips/include/asm/mach-au1x00/gpio-au1000.h | 9 +++++++++ 1 files changed, 9 insertions(+), 0 deletions(-) diff --git a/arch/mips/include/asm/mach-au1x00/gpio-au1000.h b/arch/mips/include/asm/mach-au1x00/gpio-au1000.h index 127d4ed..feea001 100644 --- a/arch/mips/include/asm/mach-au1x00/gpio-au1000.h +++ b/arch/mips/include/asm/mach-au1x00/gpio-au1000.h @@ -578,6 +578,15 @@ static inline int irq_to_gpio(int irq) return alchemy_irq_to_gpio(irq); } +static inline int gpio_request(unsigned gpio, const char *label) +{ + return 0; +} + +static inline void gpio_free(unsigned gpio) +{ +} + #endif /* !CONFIG_ALCHEMY_GPIO_INDIRECT */ -- 1.6.4.1 From f.fainelli@gmail.com Fri Aug 28 11:58:00 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 28 Aug 2009 11:58:06 +0200 (CEST) Received: from mail-ew0-f225.google.com ([209.85.219.225]:64455 "EHLO mail-ew0-f225.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492448AbZH1J6A convert rfc822-to-8bit (ORCPT ); Fri, 28 Aug 2009 11:58:00 +0200 Received: by ewy25 with SMTP id 25so1924013ewy.33 for ; Fri, 28 Aug 2009 02:57:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:sender:from:to:subject:date :user-agent:cc:references:in-reply-to:mime-version:content-type :content-transfer-encoding:content-disposition:message-id; bh=cD1OvI3OVifavFpuAPiIa6OuD2qi0XZY/MPU33S05t4=; b=Xy4qz3zGunyLjWiPUmTIv4OEjKZmznztCsiFCH+aHFE75mTTqUuiJ9KvQ+ChWcnrSU Hbu+mODRhBua7pIUwcxwH6pQGlg/O2YsFy957hmqkA6UcjrILQ91oOzk2vnVgWGFcLpA xdd+C5Q35tS6ajidadmBd3kVydkGfBm2mu038= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:from:to:subject:date:user-agent:cc:references:in-reply-to :mime-version:content-type:content-transfer-encoding :content-disposition:message-id; b=SmzgdATHwcRGilkcCnvfJPTYbM63SYCuxjcXICtYZ1gNQstQcsd5fzPuL8ze7huK8y 52S3SVX/k5X+T0bOEBRJT0FbQG0E/+xxuGw+0awAWrJjd/jp9j+Tvzrbs8OgokJCTUxA WgWM3r/QxOFJycz5nklPqUA9E/lFHFjrZDVFo= Received: by 10.210.136.1 with SMTP id j1mr20246ebd.74.1251453472321; Fri, 28 Aug 2009 02:57:52 -0700 (PDT) Received: from florian.lab.openpattern.org (lab.openpattern.org [82.240.16.241]) by mx.google.com with ESMTPS id 7sm41136eyb.10.2009.08.28.02.57.51 (version=TLSv1/SSLv3 cipher=RC4-MD5); Fri, 28 Aug 2009 02:57:51 -0700 (PDT) From: Florian Fainelli To: Manuel Lauss Subject: Re: MTX build failure Date: Fri, 28 Aug 2009 11:57:44 +0200 User-Agent: KMail/1.9.9 Cc: Ralf Baechle , Linux-MIPS References: <20090828074709.GA11637@linux-mips.org> <4A979B0E.106@gmail.com> <4A97A2E2.2090108@gmail.com> In-Reply-To: <4A97A2E2.2090108@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8BIT Content-Disposition: inline Message-Id: <200908281157.47387.florian@openwrt.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23956 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips Le Friday 28 August 2009 11:26:58 Manuel Lauss, vous avez écrit : > I wrote: > > Ralf Baechle wrote: > >> CC drivers/input/keyboard/gpio_keys.o > >> /home/ralf/src/linux/linux-mips/drivers/input/keyboard/gpio_keys.c: In > >> function ‘gpio_keys_probe’: > >> /home/ralf/src/linux/linux-mips/drivers/input/keyboard/gpio_keys.c:123: > >> error: implicit declaration of function ‘gpio_request’ > >> /home/ralf/src/linux/linux-mips/drivers/input/keyboard/gpio_keys.c:135: > >> error: implicit declaration of function ‘gpio_free’ make[5]: *** > >> [drivers/input/keyboard/gpio_keys.o] Error 1 > >> make[4]: *** [drivers/input/keyboard] Error 2 > >> make[3]: *** [drivers/input] Error 2 > >> make[2]: *** [drivers] Error 2 > >> make[1]: *** [sub-make] Error 2 > > > > Either something like the patch below, or adding stubs for > > gpio_request/gpio_free to asm/mach-au1x00/gpio-au1000.h in the > > CONFIG_GPIOLIB=n case should fix it. > > Florian, Ralf, I prefer the latter approach; saves everyone from > having to add #ifdef CONFIG_GPIOLIB around gpio_request() calls. > > Here's an untested patch. What do you think? If it works for you, please > add it to your patchqueue! > > Thanks! > > --- > > From: Manuel Lauss > Subject: [PATCH] Alchemy: add gpio_request/gpio_free stubs for > CONFIG_GPIOLIB=n > > Some drivers use gpio_request/gpio_free regardless of whether > gpiolib is actually built; add stubs to work around the ensuing > compile failures. This is better, though fixing the gpio keyboard driver might probably be a good approach. > > Signed-off-by: Manuel Lauss Tested-by: Florian Fainelli > --- > arch/mips/include/asm/mach-au1x00/gpio-au1000.h | 9 +++++++++ > 1 files changed, 9 insertions(+), 0 deletions(-) > > diff --git a/arch/mips/include/asm/mach-au1x00/gpio-au1000.h > b/arch/mips/include/asm/mach-au1x00/gpio-au1000.h index 127d4ed..feea001 > 100644 > --- a/arch/mips/include/asm/mach-au1x00/gpio-au1000.h > +++ b/arch/mips/include/asm/mach-au1x00/gpio-au1000.h > @@ -578,6 +578,15 @@ static inline int irq_to_gpio(int irq) > return alchemy_irq_to_gpio(irq); > } > > +static inline int gpio_request(unsigned gpio, const char *label) > +{ > + return 0; > +} > + > +static inline void gpio_free(unsigned gpio) > +{ > +} > + > #endif /* !CONFIG_ALCHEMY_GPIO_INDIRECT */ > > > -- > 1.6.4.1 -- Best regards, Florian Fainelli Email: florian@openwrt.org Web: http://openwrt.org IRC: [florian] on irc.freenode.net ------------------------------- From manuel.lauss@googlemail.com Fri Aug 28 12:10:39 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 28 Aug 2009 12:10:45 +0200 (CEST) Received: from mail-bw0-f208.google.com ([209.85.218.208]:42718 "EHLO mail-bw0-f208.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492470AbZH1KKj convert rfc822-to-8bit (ORCPT ); Fri, 28 Aug 2009 12:10:39 +0200 Received: by bwz4 with SMTP id 4so1745849bwz.0 for ; Fri, 28 Aug 2009 03:10:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=domainkey-signature:mime-version:received:in-reply-to:references :date:message-id:subject:from:to:cc:content-type :content-transfer-encoding; bh=eqi9cU7fq8cOXqag19LMDUtZK0ehtDf3c4FpVSbzpPI=; b=mMIzKN0ATLLF9ErSGtXdmeQQggV2WLk/CcXP0pwys8IpCHK4Ld5L+rLL+WjjKjUE/D 2CUeqxjfATOaNxGtSN9siSdGMWpbRaYnwBHniY7J6AI+VMBT1yRUbmy0MfEjbzqTIafO tDC7FYJt+DO5oBv24OMbGDrcySYEe6ThR11Mk= DomainKey-Signature: a=rsa-sha1; c=nofws; d=googlemail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type:content-transfer-encoding; b=eH3ao+2Vpr9ENqG2ypuzlwqtIdfvA5KOwopuh0tqOgLPR56erhHMw28mLgXyQWSD8P /QEvRbs1bb5xhZZi/q6RjDioHbASxZxBrSxRPTOeuH7jX28GkD9BrE/GxH1G9orOR2Hb yWoM/l018myUenrfts7WBcE7h62cuOHiUXwuM= MIME-Version: 1.0 Received: by 10.223.1.6 with SMTP id 6mr387405fad.103.1251454232119; Fri, 28 Aug 2009 03:10:32 -0700 (PDT) In-Reply-To: <200908281157.47387.florian@openwrt.org> References: <20090828074709.GA11637@linux-mips.org> <4A979B0E.106@gmail.com> <4A97A2E2.2090108@gmail.com> <200908281157.47387.florian@openwrt.org> Date: Fri, 28 Aug 2009 12:10:32 +0200 Message-ID: Subject: Re: MTX build failure From: Manuel Lauss To: Florian Fainelli Cc: Ralf Baechle , Linux-MIPS Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 8BIT Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23957 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips On Fri, Aug 28, 2009 at 11:57 AM, Florian Fainelli wrote: > Le Friday 28 August 2009 11:26:58 Manuel Lauss, vous avez écrit : >> I wrote: >> > Ralf Baechle wrote: >> >>   CC      drivers/input/keyboard/gpio_keys.o >> >> /home/ralf/src/linux/linux-mips/drivers/input/keyboard/gpio_keys.c: In >> >> function ‘gpio_keys_probe’: >> >> /home/ralf/src/linux/linux-mips/drivers/input/keyboard/gpio_keys.c:123: >> >> error: implicit declaration of function ‘gpio_request’ >> >> /home/ralf/src/linux/linux-mips/drivers/input/keyboard/gpio_keys.c:135: >> >> error: implicit declaration of function ‘gpio_free’ make[5]: *** >> >> [drivers/input/keyboard/gpio_keys.o] Error 1 >> >> make[4]: *** [drivers/input/keyboard] Error 2 >> >> make[3]: *** [drivers/input] Error 2 >> >> make[2]: *** [drivers] Error 2 >> >> make[1]: *** [sub-make] Error 2 >> > >> > Either something like the patch below, or adding stubs for >> > gpio_request/gpio_free to asm/mach-au1x00/gpio-au1000.h in the >> > CONFIG_GPIOLIB=n case should fix it. >> >> Florian, Ralf, I prefer the latter approach;  saves everyone from >> having to add #ifdef CONFIG_GPIOLIB around gpio_request() calls. >> >> Here's an untested patch.  What do you think?  If it works for you, please >> add it to your patchqueue! >> >> Thanks! >> >> --- >> >> From: Manuel Lauss >> Subject: [PATCH] Alchemy: add gpio_request/gpio_free stubs for >> CONFIG_GPIOLIB=n >> >> Some drivers use gpio_request/gpio_free regardless of whether >> gpiolib is actually built;  add stubs to work around the ensuing >> compile failures. > > This is better, though fixing the gpio keyboard driver might probably be a good approach. As I wrote above, I don't think adding "#ifdef CONFIG_GPIOLIB" to all in-kernel users of gpio_request() is an acceptable solution; one would be to unconditionally enable GPIOLIB on Alchemy (but I like speedy gpio calls to bitbang busses...), another this patch. Thanks for testing! Manuel Lauss From ralf@linux-mips.org Fri Aug 28 15:13:06 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 28 Aug 2009 15:13:13 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:58692 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1493090AbZH1NNG (ORCPT ); Fri, 28 Aug 2009 15:13:06 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id n7SDE7ZH005635; Fri, 28 Aug 2009 14:14:07 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id n7SDE6ZA005610; Fri, 28 Aug 2009 14:14:06 +0100 Date: Fri, 28 Aug 2009 14:14:06 +0100 From: Ralf Baechle To: Manuel Lauss Cc: Florian Fainelli , Linux-MIPS Subject: Re: MTX build failure Message-ID: <20090828131406.GC24330@linux-mips.org> References: <20090828074709.GA11637@linux-mips.org> <4A979B0E.106@gmail.com> <4A97A2E2.2090108@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <4A97A2E2.2090108@gmail.com> User-Agent: Mutt/1.5.19 (2009-01-05) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23958 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Fri, Aug 28, 2009 at 11:26:58AM +0200, Manuel Lauss wrote: > I wrote: > > Ralf Baechle wrote: > >> CC drivers/input/keyboard/gpio_keys.o > >> /home/ralf/src/linux/linux-mips/drivers/input/keyboard/gpio_keys.c: In function ‘gpio_keys_probe’: > >> /home/ralf/src/linux/linux-mips/drivers/input/keyboard/gpio_keys.c:123: error: implicit declaration of function ‘gpio_request’ > >> /home/ralf/src/linux/linux-mips/drivers/input/keyboard/gpio_keys.c:135: error: implicit declaration of function ‘gpio_free’ > >> make[5]: *** [drivers/input/keyboard/gpio_keys.o] Error 1 > >> make[4]: *** [drivers/input/keyboard] Error 2 > >> make[3]: *** [drivers/input] Error 2 > >> make[2]: *** [drivers] Error 2 > >> make[1]: *** [sub-make] Error 2 > > > > Either something like the patch below, or adding stubs for > > gpio_request/gpio_free to asm/mach-au1x00/gpio-au1000.h in the > > CONFIG_GPIOLIB=n case should fix it. > > Florian, Ralf, I prefer the latter approach; saves everyone from > having to add #ifdef CONFIG_GPIOLIB around gpio_request() calls. > > Here's an untested patch. What do you think? If it works for you, please > add it to your patchqueue! Thanks, this 2nd one looks good. Applied. Ralf From nschichan@freebox.fr Fri Aug 28 15:23:57 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 28 Aug 2009 15:24:03 +0200 (CEST) Received: from smtp2-g21.free.fr ([212.27.42.2]:55677 "EHLO smtp2-g21.free.fr" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1493097AbZH1NX4 (ORCPT ); Fri, 28 Aug 2009 15:23:56 +0200 Received: from smtp2-g21.free.fr (localhost [127.0.0.1]) by smtp2-g21.free.fr (Postfix) with ESMTP id A37604B00BE; Fri, 28 Aug 2009 15:23:52 +0200 (CEST) Received: from bobafett.staff.proxad.net (bobafett.staff.proxad.net [213.228.1.121]) by smtp2-g21.free.fr (Postfix) with ESMTP id BB63F4B0121; Fri, 28 Aug 2009 15:23:49 +0200 (CEST) Received: from daria.localnet (unknown [172.18.3.120]) by bobafett.staff.proxad.net (Postfix) with ESMTP id A1B9F18003C; Fri, 28 Aug 2009 15:23:49 +0200 (CEST) From: Nicolas Schichan Organization: Freebox To: Florian Fainelli Subject: Re: kexec on mips failed Date: Fri, 28 Aug 2009 15:23:47 +0200 User-Agent: KMail/1.11.2 (Linux/2.6.28-14-generic; KDE/4.2.2; x86_64; ; ) Cc: "wilbur.chan" , linux-mips@linux-mips.org References: <200908281109.52499.florian@openwrt.org> In-Reply-To: <200908281109.52499.florian@openwrt.org> MIME-Version: 1.0 Content-Type: Text/Plain; charset="utf-8" Content-Transfer-Encoding: 7bit Content-Disposition: inline Message-Id: <200908281523.48697.nschichan@freebox.fr> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23959 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: nschichan@freebox.fr Precedence: bulk X-list: linux-mips On Friday 28 August 2009 11:09:51 am Florian Fainelli wrote: > Hi, Hi, > > However, whether I changed kexec_start_address to 0x802b0000 or > > 0x2b0000 , the 'j s1' seemed taking no effect? > > Should not you add a nop right after the j s1 in order to fill in the branch > delay slot with an instruction which does nothing ? This should not be needed since have no ".set noreorder" in the file, so the assembler should add a nop in the delay slot, after "jr s1". I have this on an objdumped relocate_kernel.o, so the assembler does add the nop: [...] 000000a4 : a4: 02200008 jr s1 a8: 00000000 nop [...] Regards, -- Nicolas Schichan From nschichan@freebox.fr Fri Aug 28 15:56:08 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 28 Aug 2009 15:56:14 +0200 (CEST) Received: from [212.27.42.10] ([212.27.42.10]:55742 "EHLO smtpfb2-g21.free.fr" rhost-flags-FAIL-FAIL-OK-OK) by ftp.linux-mips.org with ESMTP id S1493207AbZH1N4I convert rfc822-to-8bit (ORCPT ); Fri, 28 Aug 2009 15:56:08 +0200 Received: from smtp2-g21.free.fr (smtp2-g21.free.fr [212.27.42.2]) by smtpfb2-g21.free.fr (Postfix) with ESMTP id ACC39CA91EE for ; Fri, 28 Aug 2009 15:55:40 +0200 (CEST) Received: from smtp2-g21.free.fr (localhost [127.0.0.1]) by smtp2-g21.free.fr (Postfix) with ESMTP id 49BB14B01E7; Fri, 28 Aug 2009 15:54:56 +0200 (CEST) Received: from bobafett.staff.proxad.net (bobafett.staff.proxad.net [213.228.1.121]) by smtp2-g21.free.fr (Postfix) with ESMTP id 708D94B0131; Fri, 28 Aug 2009 15:54:54 +0200 (CEST) Received: from daria.localnet (unknown [172.18.3.120]) by bobafett.staff.proxad.net (Postfix) with ESMTP id 68ECA18039A; Fri, 28 Aug 2009 15:54:54 +0200 (CEST) From: Nicolas Schichan Organization: Freebox To: "wilbur.chan" Subject: Re: kexec on mips failed Date: Fri, 28 Aug 2009 15:54:53 +0200 User-Agent: KMail/1.11.2 (Linux/2.6.28-14-generic; KDE/4.2.2; x86_64; ; ) Cc: linux-mips@linux-mips.org References: In-Reply-To: MIME-Version: 1.0 Content-Type: Text/Plain; charset="gb2312" Content-Transfer-Encoding: 8BIT Content-Disposition: inline Message-Id: <200908281554.53949.nschichan@freebox.fr> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23960 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: nschichan@freebox.fr Precedence: bulk X-list: linux-mips On Sunday 16 August 2009 06:20:56 pm wilbur.chan wrote: > Hi,Nicolas, Hi, > I've got some problem with kexec on mips32... > > > in your code for kexec on mips32, there is a relocate_new_kernel function . > > > In the end of this function , it jump to kexec_start_address by 'j s1' > > > Because I changed the kexec-tools code ,in the hope that, it > simplely passed the new kernel segment data into the old kernel.(so > I didn't pass the command-line segment in, in my code, there is just > one segment , segment[0] = kernel_data). I do not know what the kexec userland code does regarding command line, but the relocate_kernel.S code does not take any action regarding command line passing (as far as I know it is bootloader dependent). > > So I need to change register s1 to the new kernel entry address, and > jump to new kernel directly. > > > > In my vmlinux, the entry is 0x802b0000£¬so I let image->start = > 0x2b0000£¬and invoke relocate_new_kernel. Normaly the userland and sys_kexec should do the right thing in setting image->start to the entry point set in the elf header of the vmlinux file. > > However, whether I changed kexec_start_address to 0x802b0000 or > 0x2b0000 , the 'j s1' seemed taking no effect? > > (I wrote 88 to address0xa1230000 before 'j s1' , it succedd .I also > wrote 78 to address 0xa1230000 in the beginning of head.S of the new > kernel , but failed. And I reset the board to uboot mode, used 'md > 0x802b0400' to display the new kernel > in ram, it is identical to the objdump content of the vmlinux. So I > guess, this problem lays in the failing of 'j 0x802b0000' or 'j > 0x2b0000'. I don't know why 'j s1' failed , any suggestions about > this ? Thank you very much. The relocation code should really jump to 0x802b0000 address, not the 0x002b0000 address, could you please check that the machine_kexec() function is invoked with image->start set to 0x802b0000 ? The other failure causes I can think about right now are that the kernel for your board expects the bootloader to set some registers (for the command line for instance), and since the kexec code does not do this, the new kernel fails early. Regards, -- Nicolas Schichan From ralf@linux-mips.org Fri Aug 28 19:06:02 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 28 Aug 2009 19:06:11 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:33206 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492951AbZH1RGC (ORCPT ); Fri, 28 Aug 2009 19:06:02 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id n7SH6uh1022363; Fri, 28 Aug 2009 18:06:57 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id n7SH6swp022300; Fri, 28 Aug 2009 18:06:54 +0100 Date: Fri, 28 Aug 2009 18:06:54 +0100 From: Ralf Baechle To: David VomLehn Cc: linux-mips@linux-mips.org Subject: Re: [PATCH 1/3] mips:powertv: Base files for Cisco Powertv platform, v3 Message-ID: <20090828170654.GA30518@linux-mips.org> References: <20090529183037.GA12464@cuplxvomd02.corp.sa.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20090529183037.GA12464@cuplxvomd02.corp.sa.net> User-Agent: Mutt/1.5.19 (2009-01-05) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23961 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Old but goldie ... Appologies for needing all eternity to come back to you on this patch. > diff --git a/arch/mips/include/asm/mach-powertv/asic.h b/arch/mips/include/asm/mach-powertv/asic.h > new file mode 100644 > index 0000000..fd02c4d > --- /dev/null > +++ b/arch/mips/include/asm/mach-powertv/asic.h > @@ -0,0 +1,109 @@ > +/* > + * asic.h > + * > + * Copyright (C) 2009 Cisco Systems, Inc. > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, write to the Free Software > + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA > + */ > + > +#ifndef _ASM_MACH_POWERTV_ASIC_H > +#define _ASM_MACH_POWERTV_ASIC_H > + > +#include > +#include > + > +#define DVR_CAPABLE (1<<0) > +#define PCIE_CAPABLE (1<<1) > +#define FFS_CAPABLE (1<<2) > +#define DISPLAY_CAPABLE (1<<3) > + > +/* Platform Family types > + * For compitability, the new value must be added in the end */ > +enum family_type { > + FAMILY_8500, > + FAMILY_8500RNG, > + FAMILY_4500, > + FAMILY_1500, > + FAMILY_8600, > + FAMILY_4600, > + FAMILY_4600VZA, > + FAMILY_8600VZB, > + FAMILY_1500VZE, > + FAMILY_1500VZF, > + FAMILIES > +}; > + > +/* Register maps for each ASIC */ > +extern const struct register_map calliope_register_map; > +extern const struct register_map cronus_register_map; > +extern const struct register_map zeus_register_map; > + > +extern struct resource dvr_cronus_resources[]; > +extern struct resource dvr_zeus_resources[]; > +extern struct resource non_dvr_calliope_resources[]; > +extern struct resource non_dvr_cronus_resources[]; > +extern struct resource non_dvr_cronuslite_resources[]; > +extern struct resource non_dvr_vz_calliope_resources[]; > +extern struct resource non_dvr_vze_calliope_resources[]; > +extern struct resource non_dvr_vzf_calliope_resources[]; > +extern struct resource non_dvr_zeus_resources[]; > + > +extern void powertv_platform_init(void); > +extern void platform_alloc_bootmem(void); > +extern enum asic_type platform_get_asic(void); > +extern enum family_type platform_get_family(void); > +extern int platform_supports_dvr(void); > +extern int platform_supports_ffs(void); > +extern int platform_supports_pcie(void); > +extern int platform_supports_display(void); > +extern void configure_platform(void); > +extern void platform_configure_usb_ehci(void); > +extern void platform_unconfigure_usb_ehci(void); > +extern void platform_configure_usb_ohci(void); > +extern void platform_unconfigure_usb_ohci(void); > + > +/* Platform Resources */ > +#define ASIC_RESOURCE_GET_EXISTS 1 > +extern struct resource *asic_resource_get(const char *name); > +extern void platform_release_memory(void *baddr, int size); > + > +/* Reboot Cause */ > +extern void set_reboot_cause(char code, unsigned int data, unsigned int data2); > +extern void set_locked_reboot_cause(char code, unsigned int data, > + unsigned int data2); > + > +enum sys_reboot_type { > + sys_unknown_reboot = 0x00, /* Unknown reboot cause */ > + sys_davic_change = 0x01, /* Reboot due to change in DAVIC > + * mode */ > + sys_user_reboot = 0x02, /* Reboot initiated by user */ > + sys_system_reboot = 0x03, /* Reboot initiated by OS */ > + sys_trap_reboot = 0x04, /* Reboot due to a CPU trap */ > + sys_silent_reboot = 0x05, /* Silent reboot */ > + sys_boot_ldr_reboot = 0x06, /* Bootloader reboot */ > + sys_power_up_reboot = 0x07, /* Power on bootup. Older > + * drivers may report as > + * userReboot. */ > + sys_code_change = 0x08, /* Reboot to take code change. > + * Older drivers may report as > + * userReboot. */ > + sys_hardware_reset = 0x09, /* HW watchdog or front-panel > + * reset button reset. Older > + * drivers may report as > + * userReboot. */ > + sys_watchdogInterrupt = 0x0A /* Pre-watchdog interrupt */ > +}; > + > +#endif /* _ASM_MACH_POWERTV_ASIC_H */ > diff --git a/arch/mips/include/asm/mach-powertv/asic_regs.h b/arch/mips/include/asm/mach-powertv/asic_regs.h > new file mode 100644 > index 0000000..32e7391 > --- /dev/null > +++ b/arch/mips/include/asm/mach-powertv/asic_regs.h > @@ -0,0 +1,146 @@ > +/* > + * asic_regs.h > + * > + * Copyright (C) 2009 Cisco Systems, Inc. > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, write to the Free Software > + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA > + */ > + > +#ifndef __ASM_MACH_POWERTV_ASIC_H_ > +#define __ASM_MACH_POWERTV_ASIC_H_ > +#include > + > +/* ASIC types */ > +enum asic_type { > + ASIC_UNKNOWN, > + ASIC_ZEUS, > + ASIC_CALLIOPE, > + ASIC_CRONUS, > + ASIC_CRONUSLITE, > + ASICS > +}; > + > +/* hardcoded values read from Chip Version registers */ > +#define CRONUS_10 0x0B4C1C20 > +#define CRONUS_11 0x0B4C1C21 > +#define CRONUSLITE_10 0x0B4C1C40 > + > +#define NAND_FLASH_BASE 0x03000000 > +#define ZEUS_IO_BASE 0x09000000 > +#define CALLIOPE_IO_BASE 0x08000000 > +#define CRONUS_IO_BASE 0x09000000 > +#define ASIC_IO_SIZE 0x01000000 > + > +/* ASIC register enumeration */ > +struct register_map { > + u32 eic_slow0_strt_add; > + u32 eic_cfg_bits; > + u32 eic_ready_status; > + > + u32 chipver3; > + u32 chipver2; > + u32 chipver1; > + u32 chipver0; > + > + u32 uart1_intstat; > + u32 uart1_inten; > + u32 uart1_config1; > + u32 uart1_config2; > + u32 uart1_divisorhi; > + u32 uart1_divisorlo; > + u32 uart1_data; > + u32 uart1_status; > + > + u32 int_stat_3; > + u32 int_stat_2; > + u32 int_stat_1; > + u32 int_stat_0; > + u32 int_config; > + u32 int_int_scan; > + u32 ien_int_3; > + u32 ien_int_2; > + u32 ien_int_1; > + u32 ien_int_0; > + u32 int_level_3_3; > + u32 int_level_3_2; > + u32 int_level_3_1; > + u32 int_level_3_0; > + u32 int_level_2_3; > + u32 int_level_2_2; > + u32 int_level_2_1; > + u32 int_level_2_0; > + u32 int_level_1_3; > + u32 int_level_1_2; > + u32 int_level_1_1; > + u32 int_level_1_0; > + u32 int_level_0_3; > + u32 int_level_0_2; > + u32 int_level_0_1; > + u32 int_level_0_0; > + u32 int_docsis_en; > + > + u32 mips_pll_setup; > + u32 usb_fs; > + u32 test_bus; > + u32 usb2_ohci_int_mask; > + u32 usb2_strap; > + u32 ehci_hcapbase; > + u32 ohci_hc_revision; > + u32 bcm1_bs_lmi_steer; > + u32 usb2_control; > + u32 usb2_stbus_obc; > + u32 usb2_stbus_mess_size; > + u32 usb2_stbus_chunk_size; > + > + u32 pcie_regs; > + u32 tim_ch; > + u32 tim_cl; > + u32 gpio_dout; > + u32 gpio_din; > + u32 gpio_dir; > + u32 watchdog; > + u32 front_panel; > + > + u32 register_maps; > +}; > + > +extern enum asic_type asic; > +extern const struct register_map *register_map; > +extern unsigned long asic_phy_base; /* Physical address of ASIC */ > +extern unsigned long asic_base; /* Virtual address of ASIC */ > + > +/* > + * Macros to interface to registers through their ioremapped address > + * asic_reg_offset Returns the offset of a given register from the start > + * of the ASIC address space > + * asic_reg_phys_addr Returns the physical address of the given register > + * asic_reg_addr Returns the iomapped virtual address of the given > + * register. > + */ > +#define asic_reg_offset(x) (register_map->x) > +#define asic_reg_phys_addr(x) (asic_phy_base + asic_reg_offset(x)) > +#define asic_reg_addr(x) \ > + ((unsigned int *) (asic_base + asic_reg_offset(x))) > + > +/* > + * The asic_reg macro is gone. It should be replaced by either asic_read or > + * asic_write, as appropriate. > + */ > + > +#define asic_read(x) readl(asic_reg_addr(x)) > +#define asic_write(v, x) writel(v, asic_reg_addr(x)) > + > +extern void asic_irq_init(void); > +#endif > diff --git a/arch/mips/include/asm/mach-powertv/dma-coherence.h b/arch/mips/include/asm/mach-powertv/dma-coherence.h > new file mode 100644 > index 0000000..da31ffb > --- /dev/null > +++ b/arch/mips/include/asm/mach-powertv/dma-coherence.h > @@ -0,0 +1,124 @@ > +/* > + * dma-coherence.h > + * > + * This file is subject to the terms and conditions of the GNU General Public > + * License. See the file "COPYING" in the main directory of this archive > + * for more details. > + * > + * Version from mach-generic modified to support PowerTV port > + * Portions Copyright (C) 2009 Cisco Systems, Inc. > + * Copyright (C) 2006 Ralf Baechle > + * > + */ > + > +#ifndef __ASM_MACH_POWERTV_DMA_COHERENCE_H > +#define __ASM_MACH_POWERTV_DMA_COHERENCE_H > + > +#include > +#include > +#include > +#include > + > +static inline bool is_kseg2(void *addr) > +{ > + return (unsigned long)addr >= KSEG2; > +} > + > +static inline unsigned long virt_to_phys_from_pte(void *addr) > +{ > + pgd_t *pgd; > + pud_t *pud; > + pmd_t *pmd; > + pte_t *ptep, pte; > + > + unsigned long virt_addr = (unsigned long)addr; > + unsigned long phys_addr = 0UL; > + > + /* get the page global directory. */ > + pgd = pgd_offset_k(virt_addr); > + > + if (!pgd_none(*pgd)) { > + /* get the page upper directory */ > + pud = pud_offset(pgd, virt_addr); > + if (!pud_none(*pud)) { > + /* get the page middle directory */ > + pmd = pmd_offset(pud, virt_addr); > + if (!pmd_none(*pmd)) { > + /* get a pointer to the page table entry */ > + ptep = pte_offset(pmd, virt_addr); > + pte = *ptep; > + /* check for a valid page */ > + if (pte_present(pte)) { > + /* get the physical address the page is > + * refering to */ > + phys_addr = (unsigned long) > + page_to_phys(pte_page(pte)); > + /* add the offset within the page */ > + phys_addr |= (virt_addr & ~PAGE_MASK); > + } > + } > + } > + } > + > + return phys_addr; > +} Ouch. What is the point of walking ptes here? DMA to vmalloc'ed memory? The layer that invokes the dma_* mappings functions should do the vmalloc to physical address translation, see for example blk_rq_map_kern in the block layer. > + > +static inline dma_addr_t plat_map_dma_mem(struct device *dev, void *addr, > + size_t size) > +{ > + if (is_kseg2(addr)) > + return phys_to_bus(virt_to_phys_from_pte(addr)); > + else > + return phys_to_bus(virt_to_phys(addr)); > +} > + > +static inline dma_addr_t plat_map_dma_mem_page(struct device *dev, > + struct page *page) > +{ > + return phys_to_bus(page_to_phys(page)); > +} > + > +static inline unsigned long plat_dma_addr_to_phys(dma_addr_t dma_addr) > +{ > + return bus_to_phys(dma_addr); > +} > + > +static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr) > +{ > +} > + > +static inline int plat_dma_supported(struct device *dev, u64 mask) > +{ > + /* > + * we fall back to GFP_DMA when the mask isn't all 1s, > + * so we can't guarantee allocations that must be > + * within a tighter range than GFP_DMA.. > + */ > + if (mask < DMA_BIT_MASK(24)) > + return 0; > + > + return 1; > +} > + > +static inline void plat_extra_sync_for_device(struct device *dev) > +{ > + return; > +} > + > +static inline int plat_dma_mapping_error(struct device *dev, > + dma_addr_t dma_addr) > +{ > + return 0; > +} > + > +static inline int plat_device_is_coherent(struct device *dev) > +{ > +#ifdef CONFIG_DMA_COHERENT > + return 1; > +#endif > +#ifdef CONFIG_DMA_NONCOHERENT > + return 0; > +#endif Do you have multiple system controllers or why do you offer both coherent and non-coherent DMA here? > +} > + > +#endif /* __ASM_MACH_POWERTV_DMA_COHERENCE_H */ > diff --git a/arch/mips/include/asm/mach-powertv/interrupts.h b/arch/mips/include/asm/mach-powertv/interrupts.h > new file mode 100644 > index 0000000..e5a92d1 > --- /dev/null > +++ b/arch/mips/include/asm/mach-powertv/interrupts.h > @@ -0,0 +1,253 @@ > +/* > + * interrupts.h > + * > + * Copyright (C) 2009 Cisco Systems, Inc. > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, write to the Free Software > + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA > + */ > + > +#ifndef _ASM_MACH_POWERTV_INTERRUPTS_H_ > +#define _ASM_MACH_POWERTV_INTERRUPTS_H_ > + > +/* > + * Defines for all of the interrupt lines > + */ > + > +#define ibase 0 > + > +/*------------- Register: int_stat_3 */ > +/* 126 unused (bit 31) */ > +#define irq_asc2video (ibase+126) /* ASC 2 Video Interrupt */ > +#define irq_asc1video (ibase+125) /* ASC 1 Video Interrupt */ > +#define irq_comms_block_wd (ibase+124) /* ASC 1 Video Interrupt */ > +#define irq_fdma_mailbox (ibase+123) /* FDMA Mailbox Output */ > +#define irq_fdma_gp (ibase+122) /* FDMA GP Output */ > +#define irq_mips_pic (ibase+121) /* MIPS Performance Counter > + * Interrupt */ > +#define irq_mips_timer (ibase+120) /* MIPS Timer Interrupt */ > +#define irq_memory_protect (ibase+119) /* Memory Protection Interrupt > + * -- Ored by glue logic inside > + * SPARC ILC (see > + * INT_MEM_PROT_STAT, below, > + * for individual interrupts) > + */ > +/* 118 unused (bit 22) */ > +#define irq_sbag (ibase+117) /* SBAG Interrupt -- Ored by > + * glue logic inside SPARC ILC > + * (see INT_SBAG_STAT, below, > + * for individual interrupts) */ > +#define irq_qam_b_fec (ibase+116) /* QAM B FEC Interrupt */ > +#define irq_qam_a_fec (ibase+115) /* QAM A FEC Interrupt */ > +/* 114 unused (bit 18) */ > +#define irq_mailbox (ibase+113) /* Mailbox Debug Interrupt -- > + * Ored by glue logic inside > + * SPARC ILC (see > + * INT_MAILBOX_STAT, below, for > + * individual interrupts) */ > +#define irq_fuse_stat1 (ibase+112) /* Fuse Status 1 */ > +#define irq_fuse_stat2 (ibase+111) /* Fuse Status 2 */ > +#define irq_fuse_stat3 (ibase+110) /* Blitter Interrupt / Fuse > + * Status 3 */ > +#define irq_blitter (ibase+110) /* Blitter Interrupt / Fuse > + * Status 3 */ > +#define irq_avc1_pp0 (ibase+109) /* AVC Decoder #1 PP0 > + * Interrupt */ > +#define irq_avc1_pp1 (ibase+108) /* AVC Decoder #1 PP1 > + * Interrupt */ > +#define irq_avc1_mbe (ibase+107) /* AVC Decoder #1 MBE > + * Interrupt */ > +#define irq_avc2_pp0 (ibase+106) /* AVC Decoder #2 PP0 > + * Interrupt */ > +#define irq_avc2_pp1 (ibase+105) /* AVC Decoder #2 PP1 > + * Interrupt */ > +#define irq_avc2_mbe (ibase+104) /* AVC Decoder #2 MBE > + * Interrupt */ > +#define irq_zbug_spi (ibase+103) /* Zbug SPI Slave Interrupt */ > +#define irq_qam_mod2 (ibase+102) /* QAM Modulator 2 DMA > + * Interrupt */ > +#define irq_ir_rx (ibase+101) /* IR RX 2 Interrupt */ > +#define irq_aud_dsp2 (ibase+100) /* Audio DSP #2 Interrupt */ > +#define irq_aud_dsp1 (ibase+99) /* Audio DSP #1 Interrupt */ > +#define irq_docsis (ibase+98) /* DOCSIS Debug Interrupt */ > +#define irq_sd_dvp1 (ibase+97) /* SD DVP #1 Interrupt */ > +#define irq_sd_dvp2 (ibase+96) /* SD DVP #2 Interrupt */ > +/*------------- Register: int_stat_2 */ > +#define irq_hd_dvp (ibase+95) /* HD DVP Interrupt */ > +#define kIrq_Prewatchdog (ibase+94) /* watchdog Pre-Interrupt */ > +#define irq_timer2 (ibase+93) /* Programmable Timer > + * Interrupt 2 */ > +#define irq_1394 (ibase+92) /* 1394 Firewire Interrupt */ > +#define irq_usbohci (ibase+91) /* USB 2.0 OHCI Interrupt */ > +#define irq_usbehci (ibase+90) /* USB 2.0 EHCI Interrupt */ > +#define irq_pciexp (ibase+89) /* PCI Express 0 Interrupt */ > +#define irq_pciexp0 (ibase+89) /* PCI Express 0 Interrupt */ > +#define irq_afe1 (ibase+88) /* AFE 1 Interrupt */ > +#define irq_sata (ibase+87) /* SATA 1 Interrupt */ > +#define irq_sata1 (ibase+87) /* SATA 1 Interrupt */ > +#define irq_dtcp (ibase+86) /* DTCP Interrupt */ > +#define irq_pciexp1 (ibase+85) /* PCI Express 1 Interrupt */ > +/* 84 unused (bit 20) */ > +/* 83 unused (bit 19) */ > +/* 82 unused (bit 18) */ > +#define irq_sata2 (ibase+81) /* SATA2 Interrupt */ > +#define irq_uart2 (ibase+80) /* UART2 Interrupt */ > +#define irq_legacy_usb (ibase+79) /* Legacy USB Host ISR (1.1 > + * Host module) */ > +#define irq_pod (ibase+78) /* POD Interrupt */ > +#define irq_slave_usb (ibase+77) /* Slave USB */ > +#define irq_denc1 (ibase+76) /* DENC #1 VTG Interrupt */ > +#define irq_vbi_vtg (ibase+75) /* VBI VTG Interrupt */ > +#define irq_afe2 (ibase+74) /* AFE 2 Interrupt */ > +#define irq_denc2 (ibase+73) /* DENC #2 VTG Interrupt */ > +#define irq_asc2 (ibase+72) /* ASC #2 Interrupt */ > +#define irq_asc1 (ibase+71) /* ASC #1 Interrupt */ > +#define irq_mod_dma (ibase+70) /* Modulator DMA Interrupt */ > +#define irq_byte_eng1 (ibase+69) /* Byte Engine Interrupt [1] */ > +#define irq_byte_eng0 (ibase+68) /* Byte Engine Interrupt [0] */ > +/* 67 unused (bit 03) */ > +/* 66 unused (bit 02) */ > +/* 65 unused (bit 01) */ > +/* 64 unused (bit 00) */ > +/*------------- Register: int_stat_1 */ > +/* 63 unused (bit 31) */ > +/* 62 unused (bit 30) */ > +/* 61 unused (bit 29) */ > +/* 60 unused (bit 28) */ > +/* 59 unused (bit 27) */ > +/* 58 unused (bit 26) */ > +/* 57 unused (bit 25) */ > +/* 56 unused (bit 24) */ > +#define irq_buf_dma_mem2mem (ibase+55) /* BufDMA Memory to Memory > + * Interrupt */ > +#define irq_buf_dma_usbtransmit (ibase+54) /* BufDMA USB Transmit > + * Interrupt */ > +#define irq_buf_dma_qpskpodtransmit (ibase+53) /* BufDMA QPSK/POD Tramsit > + * Interrupt */ > +#define irq_buf_dma_transmit_error (ibase+52) /* BufDMA Transmit Error > + * Interrupt */ > +#define irq_buf_dma_usbrecv (ibase+51) /* BufDMA USB Receive > + * Interrupt */ > +#define irq_buf_dma_qpskpodrecv (ibase+50) /* BufDMA QPSK/POD Receive > + * Interrupt */ > +#define irq_buf_dma_recv_error (ibase+49) /* BufDMA Receive Error > + * Interrupt */ > +#define irq_qamdma_transmit_play (ibase+48) /* QAMDMA Transmit/Play > + * Interrupt */ > +#define irq_qamdma_transmit_error (ibase+47) /* QAMDMA Transmit Error > + * Interrupt */ > +#define irq_qamdma_recv2high (ibase+46) /* QAMDMA Receive 2 High > + * (Chans 63-32) */ > +#define irq_qamdma_recv2low (ibase+45) /* QAMDMA Receive 2 Low > + * (Chans 31-0) */ > +#define irq_qamdma_recv1high (ibase+44) /* QAMDMA Receive 1 High > + * (Chans 63-32) */ > +#define irq_qamdma_recv1low (ibase+43) /* QAMDMA Receive 1 Low > + * (Chans 31-0) */ > +#define irq_qamdma_recv_error (ibase+42) /* QAMDMA Receive Error > + * Interrupt */ > +#define irq_mpegsplice (ibase+41) /* MPEG Splice Interrupt */ > +#define irq_deinterlace_rdy (ibase+40) /* Deinterlacer Frame Ready > + * Interrupt */ > +#define irq_ext_in0 (ibase+39) /* External Interrupt irq_in0 */ > +#define irq_gpio3 (ibase+38) /* GP I/O IRQ 3 - From GP I/O > + * Module */ > +#define irq_gpio2 (ibase+37) /* GP I/O IRQ 2 - From GP I/O > + * Module (ABE_intN) */ > +#define irq_pcrcmplt1 (ibase+36) /* PCR Capture Complete or > + * Discontinuity 1 */ > +#define irq_pcrcmplt2 (ibase+35) /* PCR Capture Complete or > + * Discontinuity 2 */ > +#define irq_parse_peierr (ibase+34) /* PID Parser Error Detect > + * (PEI) */ > +#define irq_parse_cont_err (ibase+33) /* PID Parser continuity error > + * detect */ > +#define irq_ds1framer (ibase+32) /* DS1 Framer Interrupt */ > +/*------------- Register: int_stat_0 */ > +#define irq_gpio1 (ibase+31) /* GP I/O IRQ 1 - From GP I/O > + * Module */ > +#define irq_gpio0 (ibase+30) /* GP I/O IRQ 0 - From GP I/O > + * Module */ > +#define irq_qpsk_out_aloha (ibase+29) /* QPSK Output Slotted Aloha > + * (chan 3) Transmission > + * Completed OK */ > +#define irq_qpsk_out_tdma (ibase+28) /* QPSK Output TDMA (chan 2) > + * Transmission Completed OK */ > +#define irq_qpsk_out_reserve (ibase+27) /* QPSK Output Reservation > + * (chan 1) Transmission > + * Completed OK */ > +#define irq_qpsk_out_aloha_err (ibase+26) /* QPSK Output Slotted Aloha > + * (chan 3)Transmission > + * completed with Errors. */ > +#define irq_qpsk_out_tdma_err (ibase+25) /* QPSK Output TDMA (chan 2) > + * Transmission completed with > + * Errors. */ > +#define irq_qpsk_out_rsrv_err (ibase+24) /* QPSK Output Reservation > + * (chan 1) Transmission > + * completed with Errors */ > +#define irq_aloha_fail (ibase+23) /* Unsuccessful Resend of Aloha > + * for N times. Aloha retry > + * timeout for channel 3. */ > +#define irq_timer1 (ibase+22) /* Programmable Timer > + * Interrupt */ > +#define irq_keyboard (ibase+21) /* Keyboard Module Interrupt */ > +#define irq_i2c (ibase+20) /* I2C Module Interrupt */ > +#define irq_spi (ibase+19) /* SPI Module Interrupt */ > +#define irq_irblaster (ibase+18) /* IR Blaster Interrupt */ > +#define irq_splice_detect (ibase+17) /* PID Key Change Interrupt or > + * Splice Detect Interrupt */ > +#define irq_se_micro (ibase+16) /* Secure Micro I/F Module > + * Interrupt */ > +#define irq_uart1 (ibase+15) /* UART Interrupt */ > +#define irq_irrecv (ibase+14) /* IR Receiver Interrupt */ > +#define irq_host_int1 (ibase+13) /* Host-to-Host Interrupt 1 */ > +#define irq_host_int0 (ibase+12) /* Host-to-Host Interrupt 0 */ > +#define irq_qpsk_hecerr (ibase+11) /* QPSK HEC Error Interrupt */ > +#define irq_qpsk_crcerr (ibase+10) /* QPSK AAL-5 CRC Error > + * Interrupt */ > +/* 9 unused (bit 09) */ > +/* 8 unused (bit 08) */ > +#define irq_psicrcerr (ibase+7) /* QAM PSI CRC Error > + * Interrupt */ > +#define irq_psilength_err (ibase+6) /* QAM PSI Length Error > + * Interrupt */ > +#define irq_esfforward (ibase+5) /* ESF Interrupt Mark From > + * Forward Path Reference - > + * every 3ms when forward Mbits > + * and forward slot control > + * bytes are updated. */ > +#define irq_esfreverse (ibase+4) /* ESF Interrupt Mark from > + * Reverse Path Reference - > + * delayed from forward mark by > + * the ranging delay plus a > + * fixed amount. When reverse > + * Mbits and reverse slot > + * control bytes are updated. > + * Occurs every 3ms for 3.0M and > + * 1.554 M upstream rates and > + * every 6 ms for 256K upstream > + * rate. */ > +#define irq_aloha_timeout (ibase+3) /* Slotted-Aloha timeout on > + * Channel 1. */ > +#define irq_reservation (ibase+2) /* Partial (or Incremental) > + * Reservation Message Completed > + * or Slotted aloha verify for > + * channel 1. */ > +#define irq_aloha3 (ibase+1) /* Slotted-Aloha Message Verify > + * Interrupt or Reservation > + * increment completed for > + * channel 3. */ > +#define irq_mpeg_d (ibase+0) /* MPEG Decoder Interrupt */ > +#endif /* _ASM_MACH_POWERTV_INTERRUPTS_H_ */ > + > diff --git a/arch/mips/include/asm/mach-powertv/ioremap.h b/arch/mips/include/asm/mach-powertv/ioremap.h > new file mode 100644 > index 0000000..1d3be37 > --- /dev/null > +++ b/arch/mips/include/asm/mach-powertv/ioremap.h > @@ -0,0 +1,92 @@ > +/* > + * ioremap.h > + * > + * This program is free software; you can redistribute it and/or > + * modify it under the terms of the GNU General Public License > + * as published by the Free Software Foundation; either version > + * 2 of the License, or (at your option) any later version. > + * > + * Portions Copyright (C) Cisco Systems, Inc. > + */ > +#ifndef __ASM_MACH_POWERTV_IOREMAP_H > +#define __ASM_MACH_POWERTV_IOREMAP_H > + > +#include > + > +#define LOW_MEM_BOUNDARY_PHYS 0x20000000 > +#define LOW_MEM_BOUNDARY_MASK (~(LOW_MEM_BOUNDARY_PHYS - 1)) > + > +/* > + * The bus addresses are different than the physical addresses that > + * the processor sees by an offset. This offset varies by ASIC > + * version. Define a variable to hold the offset and some macros to > + * make the conversion simpler. */ > +extern unsigned long phys_to_bus_offset; > + > +#ifdef CONFIG_HIGHMEM > +#define MEM_GAP_PHYS 0x60000000 > +/* > + * TODO: We will use the hard code for conversion between physical and > + * bus until the bootloader releases their device tree to us. > + */ > +#define phys_to_bus(x) (((x) < LOW_MEM_BOUNDARY_PHYS) ? \ > + ((x) + phys_to_bus_offset) : (x)) > +#define bus_to_phys(x) (((x) < MEM_GAP_PHYS_ADDR) ? \ > + ((x) - phys_to_bus_offset) : (x)) > +#else > +#define phys_to_bus(x) ((x) + phys_to_bus_offset) > +#define bus_to_phys(x) ((x) - phys_to_bus_offset) > +#endif > + > +/* > + * Determine whether the address we are given is for an ASIC device > + * Params: addr Address to check > + * Returns: Zero if the address is not for ASIC devices, non-zero > + * if it is. > + */ > +static inline int asic_is_device_addr(phys_t addr) > +{ > + return !((phys_t)addr & (phys_t) LOW_MEM_BOUNDARY_MASK); > +} > + > +/* > + * Determine whether the address we are given is external RAM mappable > + * into KSEG1. > + * Params: addr Address to check > + * Returns: Zero if the address is not for external RAM and > + */ > +static inline int asic_is_lowmem_ram_addr(phys_t addr) > +{ > + /* > + * The RAM always starts at the following address in the processor's > + * physical address space > + */ > + static const phys_t phys_ram_base = 0x10000000; > + phys_t bus_ram_base; > + > + bus_ram_base = phys_to_bus_offset + phys_ram_base; > + > + return addr >= bus_ram_base && > + addr < (bus_ram_base + (LOW_MEM_BOUNDARY_PHYS - phys_ram_base)); > +} > + > +/* > + * Allow physical addresses to be fixed up to help peripherals located > + * outside the low 32-bit range -- generic pass-through version. > + */ > +static inline phys_t fixup_bigphys_addr(phys_t phys_addr, phys_t size) > +{ > + return phys_addr; > +} > + > +static inline void __iomem *plat_ioremap(phys_t offset, unsigned long size, > + unsigned long flags) > +{ > + return NULL; > +} > + > +static inline int plat_iounmap(const volatile void __iomem *addr) > +{ > + return 0; > +} > +#endif /* __ASM_MACH_POWERTV_IOREMAP_H */ > diff --git a/arch/mips/include/asm/mach-powertv/war.h b/arch/mips/include/asm/mach-powertv/war.h > new file mode 100644 > index 0000000..7ac05ec > --- /dev/null > +++ b/arch/mips/include/asm/mach-powertv/war.h > @@ -0,0 +1,28 @@ > +/* > + * This file is subject to the terms and conditions of the GNU General Public > + * License. See the file "COPYING" in the main directory of this archive > + * for more details. > + * > + * This version for the PowerTV platform copied from the Malta version. > + * > + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle > + * Portions copyright (C) 2009 Cisco Systems, Inc. > + */ > +#ifndef __ASM_MACH_POWERTV_WAR_H > +#define __ASM_MACH_POWERTV_WAR_H > + > +#define R4600_V1_INDEX_ICACHEOP_WAR 0 > +#define R4600_V1_HIT_CACHEOP_WAR 0 > +#define R4600_V2_HIT_CACHEOP_WAR 0 > +#define R5432_CP0_INTERRUPT_WAR 0 > +#define BCM1250_M3_WAR 0 > +#define SIBYTE_1956_WAR 0 > +#define MIPS4K_ICACHE_REFILL_WAR 1 > +#define MIPS_CACHE_SYNC_WAR 1 > +#define TX49XX_ICACHE_INDEX_INV_WAR 0 > +#define RM9000_CDEX_SMP_WAR 0 > +#define ICACHE_REFILLS_WORKAROUND_WAR 1 > +#define R10000_LLSC_WAR 0 > +#define MIPS34K_MISSED_ITLB_WAR 0 > + > +#endif /* __ASM_MACH_POWERTV_WAR_H */ > diff --git a/arch/mips/powertv/Kconfig b/arch/mips/powertv/Kconfig > new file mode 100644 > index 0000000..fc9171e > --- /dev/null > +++ b/arch/mips/powertv/Kconfig > @@ -0,0 +1,33 @@ > +source "arch/mips/powertv/asic/Kconfig" > + > +config BOOTLOADER_DRIVER > + bool "PowerTV Bootloader Driver Support" > + default n > + depends on POWERTV > + help > + Use this option if you want to load bootloader driver. > + > +config BOOTLOADER_FAMILY > + string "POWERTV Bootloader Family string" > + default "85" > + depends on POWERTV && !BOOTLOADER_DRIVER > + help > + This value should be specified when the bootloader driver is disabled > + and must be exactly two characters long. Families supported are: > + R1 - RNG-100 R2 - RNG-200 > + A1 - Class A B1 - Class B > + E1 - Class E F1 - Class F > + 44 - 45xx 46 - 46xx > + 85 - 85xx 86 - 86xx > + > +# > +# Flag for POWERTV clock source. > +# > +config CEVT_POWERTV > + bool > + > +# > +# Flag for POWERTV clock event. > +# > +config CSRC_POWERTV > + bool > diff --git a/arch/mips/powertv/Makefile b/arch/mips/powertv/Makefile > new file mode 100644 > index 0000000..145d065 > --- /dev/null > +++ b/arch/mips/powertv/Makefile > @@ -0,0 +1,40 @@ > +# > +# Carsten Langgaard, carstenl@mips.com > +# Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. > +# > +# Carsten Langgaard, carstenl@mips.com > +# Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. > +# Portions copyright (C) 2009 Cisco Systems, Inc. > +# > +# This program is free software; you can distribute it and/or modify it > +# under the terms of the GNU General Public License (Version 2) as > +# published by the Free Software Foundation. > +# > +# This program is distributed in the hope it will be useful, but WITHOUT > +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or > +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License > +# for more details. > +# > +# You should have received a copy of the GNU General Public License along > +# with this program; if not, write to the Free Software Foundation, Inc., > +# 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. > +# > +# Makefile for the Cisco PowerTV-specific kernel interface routines > +# under Linux. > +# > + > +EXTRA_CFLAGS += -Wall -Werror > + > +obj-y := > + > +obj-$(CONFIG_POWERTV) += cmdline.o \ > + init.o \ > + memory.o \ > + reset.o \ > + time.o \ > + powertv_setup.o \ > + asic/ \ > + pci/ > + > +obj-$(CONFIG_CEVT_POWERTV) += cevt-powertv.o > +obj-$(CONFIG_CSRC_POWERTV) += csrc-powertv.o > diff --git a/arch/mips/powertv/asic/Kconfig b/arch/mips/powertv/asic/Kconfig > new file mode 100644 > index 0000000..2016bfe > --- /dev/null > +++ b/arch/mips/powertv/asic/Kconfig > @@ -0,0 +1,28 @@ > +config MIN_RUNTIME_RESOURCES > + bool "Support for minimum runtime resources" > + default n > + depends on POWERTV > + help > + Enables support for minimizing the number of (SA asic) runtime > + resources that are preallocated by the kernel. > + > +config MIN_RUNTIME_DOCSIS > + bool "Support for minimum DOCSIS resource" > + default y > + depends on MIN_RUNTIME_RESOURCES > + help > + Enables support for the preallocated DOCSIS resource. > + > +config MIN_RUNTIME_PMEM > + bool "Support for minimum PMEM resource" > + default y > + depends on MIN_RUNTIME_RESOURCES > + help > + Enables support for the preallocated Memory resource. > + > +config MIN_RUNTIME_TFTP > + bool "Support for minimum TFTP resource" > + default y > + depends on MIN_RUNTIME_RESOURCES > + help > + Enables support for the preallocated TFTP resource. > diff --git a/arch/mips/powertv/asic/Makefile b/arch/mips/powertv/asic/Makefile > new file mode 100644 > index 0000000..873d079 > --- /dev/null > +++ b/arch/mips/powertv/asic/Makefile > @@ -0,0 +1,35 @@ > +# ***************************************************************************** > +# Make file for PowerTV Asic related files > +# > +# Copyright (C) 2009 Scientific-Atlanta, Inc. > +# > +# This program is free software; you can redistribute it and/or modify > +# it under the terms of the GNU General Public License as published by > +# the Free Software Foundation; either version 2 of the License, or > +# (at your option) any later version. > +# > +# This program is distributed in the hope that it will be useful, > +# but WITHOUT ANY WARRANTY; without even the implied warranty of > +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > +# GNU General Public License for more details. > +# > +# You should have received a copy of the GNU General Public License > +# along with this program; if not, write to the Free Software > +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA > +# > +# ***************************************************************************** > + > +EXTRA_CFLAGS += -Wall -Werror > + > +obj-y := > + > +obj-$(CONFIG_POWERTV) += asic-calliope.o \ > + asic-cronus.o \ > + asic-zeus.o \ > + asic_devices.o \ > + asic_int.o \ > + irq_asic.o \ > + prealloc-calliope.o \ > + prealloc-cronus.o \ > + prealloc-cronuslite.o \ > + prealloc-zeus.o > diff --git a/arch/mips/powertv/asic/asic-calliope.c b/arch/mips/powertv/asic/asic-calliope.c > new file mode 100644 > index 0000000..3bc890b > --- /dev/null > +++ b/arch/mips/powertv/asic/asic-calliope.c > @@ -0,0 +1,99 @@ > +/* > + * asic-calliope.c > + * > + * Locations of devices in the Calliope ASIC. > + * > + * Copyright (C) 2005-2009 Scientific-Atlanta, Inc. > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, write to the Free Software > + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA > + * > + * Author: Ken Eppinett > + * David Schleef > + * > + * Description: Defines the platform resources for the SA settop. > + */ > + > +#include > + > +const struct register_map calliope_register_map = { > + .eic_slow0_strt_add = 0x800000, > + .eic_cfg_bits = 0x800038, > + .eic_ready_status = 0x80004c, > + > + .chipver3 = 0xA00800, > + .chipver2 = 0xA00804, > + .chipver1 = 0xA00808, > + .chipver0 = 0xA0080c, > + > + /* The registers of IRBlaster */ > + .uart1_intstat = 0xA01800, > + .uart1_inten = 0xA01804, > + .uart1_config1 = 0xA01808, > + .uart1_config2 = 0xA0180C, > + .uart1_divisorhi = 0xA01810, > + .uart1_divisorlo = 0xA01814, > + .uart1_data = 0xA01818, > + .uart1_status = 0xA0181C, > + > + .int_stat_3 = 0xA02800, > + .int_stat_2 = 0xA02804, > + .int_stat_1 = 0xA02808, > + .int_stat_0 = 0xA0280c, > + .int_config = 0xA02810, > + .int_int_scan = 0xA02818, > + .ien_int_3 = 0xA02830, > + .ien_int_2 = 0xA02834, > + .ien_int_1 = 0xA02838, > + .ien_int_0 = 0xA0283c, > + .int_level_3_3 = 0xA02880, > + .int_level_3_2 = 0xA02884, > + .int_level_3_1 = 0xA02888, > + .int_level_3_0 = 0xA0288c, > + .int_level_2_3 = 0xA02890, > + .int_level_2_2 = 0xA02894, > + .int_level_2_1 = 0xA02898, > + .int_level_2_0 = 0xA0289c, > + .int_level_1_3 = 0xA028a0, > + .int_level_1_2 = 0xA028a4, > + .int_level_1_1 = 0xA028a8, > + .int_level_1_0 = 0xA028ac, > + .int_level_0_3 = 0xA028b0, > + .int_level_0_2 = 0xA028b4, > + .int_level_0_1 = 0xA028b8, > + .int_level_0_0 = 0xA028bc, > + .int_docsis_en = 0xA028F4, > + > + .mips_pll_setup = 0x980000, > + .usb_fs = 0x980030, /* -default 72800028- */ > + .test_bus = 0x9800CC, > + .usb2_ohci_int_mask = 0x9A000c, > + .usb2_strap = 0x9A0014, > + .ehci_hcapbase = 0x9BFE00, > + .ohci_hc_revision = 0x9BFC00, > + .bcm1_bs_lmi_steer = 0x9E0004, > + .usb2_control = 0x9E0054, > + .usb2_stbus_obc = 0x9BFF00, > + .usb2_stbus_mess_size = 0x9BFF04, > + .usb2_stbus_chunk_size = 0x9BFF08, > + > + .pcie_regs = 0x000000, /* -doesn't exist- */ > + .tim_ch = 0xA02C10, > + .tim_cl = 0xA02C14, > + .gpio_dout = 0xA02c20, > + .gpio_din = 0xA02c24, > + .gpio_dir = 0xA02c2C, > + .watchdog = 0xA02c30, > + .front_panel = 0x000000, /* -not used- */ > +}; > diff --git a/arch/mips/powertv/asic/asic-cronus.c b/arch/mips/powertv/asic/asic-cronus.c > new file mode 100644 > index 0000000..5c2979e > --- /dev/null > +++ b/arch/mips/powertv/asic/asic-cronus.c > @@ -0,0 +1,99 @@ > +/* > + * asic-cronus.c > + * > + * Locations of devices in the Cronus ASIC > + * > + * Copyright (C) 2005-2009 Scientific-Atlanta, Inc. > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, write to the Free Software > + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA > + * > + * Author: Ken Eppinett > + * David Schleef > + * > + * Description: Defines the platform resources for the SA settop. > + */ > + > +#include > + > +const struct register_map cronus_register_map = { > + .eic_slow0_strt_add = 0x000000, > + .eic_cfg_bits = 0x000038, > + .eic_ready_status = 0x00004C, > + > + .chipver3 = 0x2A0800, > + .chipver2 = 0x2A0804, > + .chipver1 = 0x2A0808, > + .chipver0 = 0x2A080C, > + > + /* The registers of IRBlaster */ > + .uart1_intstat = 0x2A1800, > + .uart1_inten = 0x2A1804, > + .uart1_config1 = 0x2A1808, > + .uart1_config2 = 0x2A180C, > + .uart1_divisorhi = 0x2A1810, > + .uart1_divisorlo = 0x2A1814, > + .uart1_data = 0x2A1818, > + .uart1_status = 0x2A181C, > + > + .int_stat_3 = 0x2A2800, > + .int_stat_2 = 0x2A2804, > + .int_stat_1 = 0x2A2808, > + .int_stat_0 = 0x2A280C, > + .int_config = 0x2A2810, > + .int_int_scan = 0x2A2818, > + .ien_int_3 = 0x2A2830, > + .ien_int_2 = 0x2A2834, > + .ien_int_1 = 0x2A2838, > + .ien_int_0 = 0x2A283C, > + .int_level_3_3 = 0x2A2880, > + .int_level_3_2 = 0x2A2884, > + .int_level_3_1 = 0x2A2888, > + .int_level_3_0 = 0x2A288C, > + .int_level_2_3 = 0x2A2890, > + .int_level_2_2 = 0x2A2894, > + .int_level_2_1 = 0x2A2898, > + .int_level_2_0 = 0x2A289C, > + .int_level_1_3 = 0x2A28A0, > + .int_level_1_2 = 0x2A28A4, > + .int_level_1_1 = 0x2A28A8, > + .int_level_1_0 = 0x2A28AC, > + .int_level_0_3 = 0x2A28B0, > + .int_level_0_2 = 0x2A28B4, > + .int_level_0_1 = 0x2A28B8, > + .int_level_0_0 = 0x2A28BC, > + .int_docsis_en = 0x2A28F4, > + > + .mips_pll_setup = 0x1C0000, > + .usb_fs = 0x1C0018, > + .test_bus = 0x1C00CC, > + .usb2_ohci_int_mask = 0x20000C, > + .usb2_strap = 0x200014, > + .ehci_hcapbase = 0x21FE00, > + .ohci_hc_revision = 0x1E0000, > + .bcm1_bs_lmi_steer = 0x2E0008, > + .usb2_control = 0x2E004C, > + .usb2_stbus_obc = 0x21FF00, > + .usb2_stbus_mess_size = 0x21FF04, > + .usb2_stbus_chunk_size = 0x21FF08, > + > + .pcie_regs = 0x220000, > + .tim_ch = 0x2A2C10, > + .tim_cl = 0x2A2C14, > + .gpio_dout = 0x2A2C20, > + .gpio_din = 0x2A2C24, > + .gpio_dir = 0x2A2C2C, > + .watchdog = 0x2A2C30, > + .front_panel = 0x2A3800, > +}; > diff --git a/arch/mips/powertv/asic/asic-zeus.c b/arch/mips/powertv/asic/asic-zeus.c > new file mode 100644 > index 0000000..ec95abd > --- /dev/null > +++ b/arch/mips/powertv/asic/asic-zeus.c > @@ -0,0 +1,99 @@ > +/* > + * asic-zeus.c > + * > + * Locations of devices in the Zeus ASIC > + * > + * Copyright (C) 2005-2009 Scientific-Atlanta, Inc. > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, write to the Free Software > + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA > + * > + * Author: Ken Eppinett > + * David Schleef > + * > + * Description: Defines the platform resources for the SA settop. > + */ > + > +#include > + > +const struct register_map zeus_register_map = { > + .eic_slow0_strt_add = 0x000000, > + .eic_cfg_bits = 0x000038, > + .eic_ready_status = 0x00004c, > + > + .chipver3 = 0x280800, > + .chipver2 = 0x280804, > + .chipver1 = 0x280808, > + .chipver0 = 0x28080c, > + > + /* The registers of IRBlaster */ > + .uart1_intstat = 0x281800, > + .uart1_inten = 0x281804, > + .uart1_config1 = 0x281808, > + .uart1_config2 = 0x28180C, > + .uart1_divisorhi = 0x281810, > + .uart1_divisorlo = 0x281814, > + .uart1_data = 0x281818, > + .uart1_status = 0x28181C, > + > + .int_stat_3 = 0x282800, > + .int_stat_2 = 0x282804, > + .int_stat_1 = 0x282808, > + .int_stat_0 = 0x28280c, > + .int_config = 0x282810, > + .int_int_scan = 0x282818, > + .ien_int_3 = 0x282830, > + .ien_int_2 = 0x282834, > + .ien_int_1 = 0x282838, > + .ien_int_0 = 0x28283c, > + .int_level_3_3 = 0x282880, > + .int_level_3_2 = 0x282884, > + .int_level_3_1 = 0x282888, > + .int_level_3_0 = 0x28288c, > + .int_level_2_3 = 0x282890, > + .int_level_2_2 = 0x282894, > + .int_level_2_1 = 0x282898, > + .int_level_2_0 = 0x28289c, > + .int_level_1_3 = 0x2828a0, > + .int_level_1_2 = 0x2828a4, > + .int_level_1_1 = 0x2828a8, > + .int_level_1_0 = 0x2828ac, > + .int_level_0_3 = 0x2828b0, > + .int_level_0_2 = 0x2828b4, > + .int_level_0_1 = 0x2828b8, > + .int_level_0_0 = 0x2828bc, > + .int_docsis_en = 0x2828F4, > + > + .mips_pll_setup = 0x1a0000, > + .usb_fs = 0x1a0018, > + .test_bus = 0x1a0238, > + .usb2_ohci_int_mask = 0x1e000c, > + .usb2_strap = 0x1e0014, > + .ehci_hcapbase = 0x1FFE00, > + .ohci_hc_revision = 0x1FFC00, > + .bcm1_bs_lmi_steer = 0x2C0008, > + .usb2_control = 0x2c01a0, > + .usb2_stbus_obc = 0x1FFF00, > + .usb2_stbus_mess_size = 0x1FFF04, > + .usb2_stbus_chunk_size = 0x1FFF08, > + > + .pcie_regs = 0x200000, > + .tim_ch = 0x282C10, > + .tim_cl = 0x282C14, > + .gpio_dout = 0x282c20, > + .gpio_din = 0x282c24, > + .gpio_dir = 0x282c2C, > + .watchdog = 0x282c30, > + .front_panel = 0x283800, > +}; > diff --git a/arch/mips/powertv/asic/asic_devices.c b/arch/mips/powertv/asic/asic_devices.c > new file mode 100644 > index 0000000..842e2fc > --- /dev/null > +++ b/arch/mips/powertv/asic/asic_devices.c > @@ -0,0 +1,713 @@ > +/* > + * ASIC Device List Intialization > + * > + * Copyright (C) 2005-2009 Scientific-Atlanta, Inc. > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, write to the Free Software > + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA > + ***************************************************************************** > + * > + * File Name: asic_devices.c > + * > + * Author: Ken Eppinett > + * David Schleef > + * > + * Description: Defines the platform resources for the SA settop. > + * > + * NOTE: The bootloader allocates persistent memory at an address which is > + * 16 MiB below the end of the highest address in KSEG0. All fixed > + * address memory reservations must avoid this region. > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#include > +#include > +#include > + > +#ifdef CONFIG_BOOTLOADER_DRIVER > +#include > +#endif > + > +#define BOOTLDRFAMILY(byte1, byte0) (((byte1) << 8) | (byte0)) > + > +/* > + * Forward Prototypes > + */ > +static void pmem_setup_resource(void); > + > +/* > + * Global Variables > + */ > +enum asic_type asic; > + > +unsigned int platform_features; > +unsigned int platform_family; > +const struct register_map *register_map; > +EXPORT_SYMBOL(register_map); /* Exported for testing */ > +unsigned long asic_phy_base; > +unsigned long asic_base; > +EXPORT_SYMBOL(asic_base); /* Exported for testing */ > +struct resource *gp_resources; > +static bool usb_configured; > + > +/* > + * Don't recommend to use it directly, it is usually used by kernel internally. > + * Portable code should be using interfaces such as ioremp, dma_map_single, etc. > + */ > +unsigned long phys_to_bus_offset; > +EXPORT_SYMBOL(phys_to_bus_offset); > + > +/* > + * > + * IO Resource Definition > + * > + */ > + > +struct resource asic_resource = { > + .name = "ASIC Resource", > + .start = 0, > + .end = ASIC_IO_SIZE, > + .flags = IORESOURCE_MEM, > +}; > + > +/* > + * > + * USB Host Resource Definition > + * > + */ > + > +static struct resource ehci_resources[] = { > + { > + .parent = &asic_resource, > + .start = 0, > + .end = 0xff, > + .flags = IORESOURCE_MEM, > + }, > + { > + .start = irq_usbehci, > + .end = irq_usbehci, > + .flags = IORESOURCE_IRQ, > + }, > +}; > + > +static u64 ehci_dmamask = 0xffffffffULL; Use DMA_BIT_MASK(32) > + > +static struct platform_device ehci_device = { > + .name = "powertv-ehci", > + .id = 0, > + .num_resources = 2, > + .resource = ehci_resources, > + .dev = { > + .dma_mask = &ehci_dmamask, > + .coherent_dma_mask = 0xffffffff, Use DMA_BIT_MASK(32) > + }, > +}; > + > +static struct resource ohci_resources[] = { > + { > + .parent = &asic_resource, > + .start = 0, > + .end = 0xff, > + .flags = IORESOURCE_MEM, > + }, > + { > + .start = irq_usbohci, > + .end = irq_usbohci, > + .flags = IORESOURCE_IRQ, > + }, > +}; > + > +static u64 ohci_dmamask = 0xffffffffULL; Use DMA_BIT_MASK(32) > + > +static struct platform_device ohci_device = { > + .name = "powertv-ohci", > + .id = 0, > + .num_resources = 2, > + .resource = ohci_resources, > + .dev = { > + .dma_mask = &ohci_dmamask, > + .coherent_dma_mask = 0xffffffff, Use DMA_BIT_MASK(32) > + }, > +}; > + > +static struct platform_device *platform_devices[] = { > + &ehci_device, > + &ohci_device, > +}; > + > +/* > + * > + * Platform Configuration and Device Initialization > + * > + */ > +static void __init fs_update(int pe, int md, int sdiv, int disable_div_by_3) > +{ > + int en_prg, byp, pwr, nsb, val; > + int sout; > + > + sout = 1; > + en_prg = 1; > + byp = 0; > + nsb = 1; > + pwr = 1; > + > + val = ((sdiv << 29) | (md << 24) | (pe<<8) | (sout<<3) | (byp<<2) | > + (nsb<<1) | (disable_div_by_3<<5)); > + > + asic_write(val, usb_fs); > + asic_write(val | (en_prg<<4), usb_fs); > + asic_write(val | (en_prg<<4) | pwr, usb_fs); > +} > + > +/* > + * platform_get_family - determine major platform family type. > + * > + * Returns family type; -1 if none > + * > + */ > +enum family_type platform_get_family(void) > +{ > + unsigned short bootldr_family; > + static enum family_type family = -1; > + static int first_time = 1; > + > + if (first_time) { > + first_time = 0; > + > +#ifdef CONFIG_BOOTLOADER_DRIVER > + bootldr_family = (unsigned short) kbldr_GetSWFamily(); > +#else > +#if defined(CONFIG_BOOTLOADER_FAMILY) > + bootldr_family = (unsigned short) BOOTLDRFAMILY( > + CONFIG_BOOTLOADER_FAMILY[0], > + CONFIG_BOOTLOADER_FAMILY[1]); > +#else > +#error "Unknown Bootloader Family" > +#endif > +#endif > + > + pr_info("Bootloader Family = 0x%04X\n", bootldr_family); > + > + switch (bootldr_family) { > + case BOOTLDRFAMILY('R', '1'): > + family = FAMILY_1500; > + break; > + case BOOTLDRFAMILY('4', '4'): > + family = FAMILY_4500; > + break; > + case BOOTLDRFAMILY('4', '6'): > + family = FAMILY_4600; > + break; > + case BOOTLDRFAMILY('A', '1'): > + family = FAMILY_4600VZA; > + break; > + case BOOTLDRFAMILY('8', '5'): > + family = FAMILY_8500; > + break; > + case BOOTLDRFAMILY('R', '2'): > + family = FAMILY_8500RNG; > + break; > + case BOOTLDRFAMILY('8', '6'): > + family = FAMILY_8600; > + break; > + case BOOTLDRFAMILY('B', '1'): > + family = FAMILY_8600VZB; > + break; > + case BOOTLDRFAMILY('E', '1'): > + family = FAMILY_1500VZE; > + break; > + case BOOTLDRFAMILY('F', '1'): > + family = FAMILY_1500VZF; > + break; > + default: > + family = -1; > + } > + } > + > + return family; > +} > +EXPORT_SYMBOL(platform_get_family); > + > +/* > + * platform_get_asic - determine the ASIC type. > + * > + * \param none > + * > + * \return ASIC type; ASIC_UNKNOWN if none > + * > + */ > +enum asic_type platform_get_asic(void) > +{ > + return asic; > +} > +EXPORT_SYMBOL(platform_get_asic); > + > +/** > + * platform_configure_usb - usb configuration based on platform type. > + * @divide_by_3: Non-zero to divide clock setting by 3 > + */ > +static void platform_configure_usb(void) > +{ > + int divide_by_3; > + > + if (usb_configured) > + return; > + > + switch (asic) { > + case ASIC_ZEUS: > + case ASIC_CRONUS: > + case ASIC_CRONUSLITE: > + divide_by_3 = 0; > + break; > + > + case ASIC_CALLIOPE: > + divide_by_3 = 1; > + break; > + > + default: > + pr_err("Unknown ASIC type: %d\n", asic); > + divide_by_3 = 0; > + break; > + } > + > + /* Set up PLL for USB */ > + fs_update(0x0000, 0x11, 0x02, divide_by_3); > + /* turn on USB power */ > + asic_write(0, usb2_strap); > + /* Enable all OHCI interrupts */ > + asic_write(0x00000803, usb2_control); > + /* usb2_stbus_obc store32/load32 */ > + asic_write(3, usb2_stbus_obc); > + /* usb2_stbus_mess_size 2 packets */ > + asic_write(1, usb2_stbus_mess_size); > + /* usb2_stbus_chunk_size 2 packets */ > + asic_write(1, usb2_stbus_chunk_size); > + > + usb_configured = true; > +} > + > +/* > + * Set up the USB EHCI interface > + */ > +void platform_configure_usb_ehci() Not a valid C prototype - add void. > +{ platform_configure_usb(); > +} > + > +/* > + * Set up the USB OHCI interface > + */ > +void platform_configure_usb_ohci() Not a valid C prototype - add void. > +{ platform_configure_usb(); > +} > + > +/* > + * Shut the USB EHCI interface down--currently a NOP > + */ > +void platform_unconfigure_usb_ehci() Not a valid C prototype - add void. > +{ > +} > + > +/* > + * Shut the USB OHCI interface down--currently a NOP > + */ > +void platform_unconfigure_usb_ohci() Not a valid C prototype - add void. > +{ > +} > + > +/** > + * configure_platform - configuration based on platform type. > + */ > +void __init configure_platform(void) > +{ > + platform_family = platform_get_family(); > + > + switch (platform_family) { > + case FAMILY_1500: > + case FAMILY_1500VZE: > + case FAMILY_1500VZF: > + platform_features = FFS_CAPABLE; > + asic = ASIC_CALLIOPE; > + asic_phy_base = CALLIOPE_IO_BASE; > + register_map = &calliope_register_map; > + asic_base = (unsigned long)ioremap_nocache(asic_phy_base, > + ASIC_IO_SIZE); > + > + if (platform_family == FAMILY_1500VZE) { > + gp_resources = non_dvr_vze_calliope_resources; > + pr_info("Platform: 1500/Vz Class E - " > + "CALLIOPE, NON_DVR_CAPABLE\n"); > + } else if (platform_family == FAMILY_1500VZF) { > + gp_resources = non_dvr_vzf_calliope_resources; > + pr_info("Platform: 1500/Vz Class F - " > + "CALLIOPE, NON_DVR_CAPABLE\n"); > + } else { > + gp_resources = non_dvr_calliope_resources; > + pr_info("Platform: 1500/RNG100 - CALLIOPE, " > + "NON_DVR_CAPABLE\n"); > + } > + break; > + > + case FAMILY_4500: > + platform_features = FFS_CAPABLE | PCIE_CAPABLE | > + DISPLAY_CAPABLE; > + asic = ASIC_ZEUS; > + asic_phy_base = ZEUS_IO_BASE; > + register_map = &zeus_register_map; > + asic_base = (unsigned long)ioremap_nocache(asic_phy_base, > + ASIC_IO_SIZE); > + gp_resources = non_dvr_zeus_resources; > + > + pr_info("Platform: 4500 - ZEUS, NON_DVR_CAPABLE\n"); > + break; > + > + case FAMILY_4600: > + { > + unsigned int chipversion = 0; > + > + /* The settop has PCIE but it isn't used, so don't advertise > + * it*/ > + platform_features = FFS_CAPABLE | DISPLAY_CAPABLE; > + asic_phy_base = CRONUS_IO_BASE; /* same as Cronus */ > + register_map = &cronus_register_map; /* same as Cronus */ > + asic_base = (unsigned long)ioremap_nocache(asic_phy_base, > + ASIC_IO_SIZE); > + gp_resources = non_dvr_cronuslite_resources; > + > + /* ASIC version will determine if this is a real CronusLite or > + * Castrati(Cronus) */ > + chipversion = asic_read(chipver3) << 24; > + chipversion |= asic_read(chipver2) << 16; > + chipversion |= asic_read(chipver1) << 8; > + chipversion |= asic_read(chipver0); > + > + if ((chipversion == CRONUS_10) || (chipversion == CRONUS_11)) > + asic = ASIC_CRONUS; > + else > + asic = ASIC_CRONUSLITE; > + > + pr_info("Platform: 4600 - %s, NON_DVR_CAPABLE, " > + "chipversion=0x%08X\n", > + (asic == ASIC_CRONUS) ? "CRONUS" : "CRONUS LITE", > + chipversion); > + break; > + } > + case FAMILY_4600VZA: > + platform_features = FFS_CAPABLE | DISPLAY_CAPABLE; > + asic = ASIC_CRONUS; > + asic_phy_base = CRONUS_IO_BASE; > + register_map = &cronus_register_map; > + asic_base = (unsigned long)ioremap_nocache(asic_phy_base, > + ASIC_IO_SIZE); > + gp_resources = non_dvr_cronus_resources; > + > + pr_info("Platform: Vz Class A - CRONUS, NON_DVR_CAPABLE\n"); > + break; > + > + case FAMILY_8500: > + case FAMILY_8500RNG: > + platform_features = DVR_CAPABLE | PCIE_CAPABLE | > + DISPLAY_CAPABLE; > + asic = ASIC_ZEUS; > + asic_phy_base = ZEUS_IO_BASE; > + register_map = &zeus_register_map; > + asic_base = (unsigned long)ioremap_nocache(asic_phy_base, > + ASIC_IO_SIZE); > + gp_resources = dvr_zeus_resources; > + break; > + > + case FAMILY_8600: > + case FAMILY_8600VZB: > + platform_features = DVR_CAPABLE | PCIE_CAPABLE | > + DISPLAY_CAPABLE; > + asic = ASIC_CRONUS; > + asic_phy_base = CRONUS_IO_BASE; > + register_map = &cronus_register_map; > + asic_base = (unsigned long)ioremap_nocache(asic_phy_base, > + ASIC_IO_SIZE); > + gp_resources = dvr_cronus_resources; > + > + pr_info("Platform: 8600/Vz Class B - CRONUS, " > + "DVR_CAPABLE\n"); > + break; > + > + default: > + platform_features = 0; > + asic = ASIC_UNKNOWN; > + asic_phy_base = 0; > + register_map = NULL; > + gp_resources = NULL; > + > + pr_crit("Platform: UNKNOWN PLATFORM\n"); > + break; > + } > + > + platform_configure_usb(); > + > + switch (asic) { > + case ASIC_ZEUS: > + phys_to_bus_offset = 0x30000000; > + break; > + case ASIC_CALLIOPE: > + phys_to_bus_offset = 0x10000000; > + break; > + case ASIC_CRONUSLITE: > + /* Fall through */ > + case ASIC_CRONUS: > + /* > + * TODO: We suppose 0x10000000 aliases into 0x20000000- > + * 0x2XXXXXXX. If 0x10000000 aliases into 0x60000000- > + * 0x6XXXXXXX, the offset should be 0x50000000, not 0x10000000. > + */ > + phys_to_bus_offset = 0x10000000; > + break; > + default: > + phys_to_bus_offset = 0x00000000; > + break; > + } > +} > + > +/** > + * platform_devices_init - sets up USB device resourse. > + */ > +static int __init platform_devices_init(void) > +{ > + pr_notice("%s: ----- Initializing USB resources -----\n", __func__); > + > + asic_resource.start = asic_phy_base; > + asic_resource.end += asic_resource.start; > + > + ehci_resources[0].start = asic_reg_phys_addr(ehci_hcapbase); > + ehci_resources[0].end += ehci_resources[0].start; > + > + ohci_resources[0].start = asic_reg_phys_addr(ohci_hc_revision); > + ohci_resources[0].end += ohci_resources[0].start; > + > + set_io_port_base(0); > + > + platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); > + > + return 0; > +} > + > +arch_initcall(platform_devices_init); > + > +/* > + * > + * BOOTMEM ALLOCATION > + * > + */ > +/* > + * Allocates/reserves the Platform memory resources early in the boot process. > + * This ignores any resources that are designated IORESOURCE_IO > + */ > +void __init platform_alloc_bootmem(void) > +{ > + int i; > + int total = 0; > + > + /* Get persistent memory data from command line before allocating > + * resources. This need to happen before normal command line parsing > + * has been done */ > + pmem_setup_resource(); > + > + /* Loop through looking for resources that want a particular address */ > + for (i = 0; gp_resources[i].flags != 0; i++) { > + int size = gp_resources[i].end - gp_resources[i].start + 1; > + if ((gp_resources[i].start != 0) && > + ((gp_resources[i].flags & IORESOURCE_MEM) != 0)) { > + reserve_bootmem(bus_to_phys(gp_resources[i].start), > + size, 0); > + total += gp_resources[i].end - > + gp_resources[i].start + 1; > + pr_info("reserve resource %s at %08x (%u bytes)\n", > + gp_resources[i].name, gp_resources[i].start, > + gp_resources[i].end - > + gp_resources[i].start + 1); > + } > + } > + > + /* Loop through assigning addresses for those that are left */ > + for (i = 0; gp_resources[i].flags != 0; i++) { > + int size = gp_resources[i].end - gp_resources[i].start + 1; > + if ((gp_resources[i].start == 0) && > + ((gp_resources[i].flags & IORESOURCE_MEM) != 0)) { > + void *mem = alloc_bootmem_pages(size); > + > + if (mem == NULL) > + pr_err("Unable to allocate bootmem pages " > + "for %s\n", gp_resources[i].name); > + > + else { > + gp_resources[i].start = > + phys_to_bus(virt_to_phys(mem)); > + gp_resources[i].end = > + gp_resources[i].start + size - 1; > + total += size; > + pr_info("allocate resource %s at %08x " > + "(%u bytes)\n", > + gp_resources[i].name, > + gp_resources[i].start, size); > + } > + } > + } > + > + pr_info("Total Platform driver memory allocation: 0x%08x\n", total); > + > + /* indicate resources that are platform I/O related */ > + for (i = 0; gp_resources[i].flags != 0; i++) { > + if ((gp_resources[i].start != 0) && > + ((gp_resources[i].flags & IORESOURCE_IO) != 0)) { > + pr_info("reserved platform resource %s at %08x\n", > + gp_resources[i].name, gp_resources[i].start); > + } > + } > +} > + > +/* > + * > + * PERSISTENT MEMORY (PMEM) CONFIGURATION > + * > + */ > +static unsigned long pmemaddr __initdata; > + > +static int __init early_param_pmemaddr(char *p) > +{ > + pmemaddr = (unsigned long)simple_strtoul(p, NULL, 0); > + return 0; > +} > +early_param("pmemaddr", early_param_pmemaddr); > + > +static long pmemlen __initdata; > + > +static int __init early_param_pmemlen(char *p) > +{ > +/* TODO: we can use this code when and if the bootloader ever changes this */ > +#if 0 > + pmemlen = (unsigned long)simple_strtoul(p, NULL, 0); if this code is useless enough to be #if 0'ed out, consider deleting it? > +#else > + pmemlen = 0x20000; > +#endif > + return 0; > +} > +early_param("pmemlen", early_param_pmemlen); > + > +/* > + * Set up persistent memory. If we were given values, we patch the array of > + * resources. Otherwise, persistent memory may be allocated anywhere at all. > + */ > +static void __init pmem_setup_resource(void) > +{ > + struct resource *resource; > + resource = asic_resource_get("DiagPersistentMemory"); > + > + if (resource && pmemaddr && pmemlen) { > + /* The address provided by bootloader is in kseg0. Convert to > + * a bus address. */ > + resource->start = phys_to_bus(pmemaddr - 0x80000000); > + resource->end = resource->start + pmemlen - 1; > + > + pr_info("persistent memory: start=0x%x end=0x%x\n", > + resource->start, resource->end); > + } > +} > + > +/* > + * > + * RESOURCE ACCESS FUNCTIONS > + * > + */ > + > +/** > + * asic_resource_get - retrieves parameters for a platform resource. > + * @name: string to match resource > + * > + * Returns a pointer to a struct resource corresponding to the given name. > + * > + * CANNOT BE NAMED platform_resource_get, which would be the obvious choice, > + * as this function name is already declared > + */ > +struct resource *asic_resource_get(const char *name) > +{ > + int i; > + > + for (i = 0; gp_resources[i].flags != 0; i++) { > + if (strcmp(gp_resources[i].name, name) == 0) > + return &gp_resources[i]; > + } > + > + return NULL; > +} > +EXPORT_SYMBOL(asic_resource_get); > + > +/** > + * platform_release_memory - release pre-allocated memory > + * @ptr: pointer to memory to release > + * @size: size of resource > + * > + * This must only be called for memory allocated or reserved via the boot > + * memory allocator. > + */ > +void platform_release_memory(void *ptr, int size) > +{ > + unsigned long addr; > + unsigned long end; > + > + addr = ((unsigned long)ptr + (PAGE_SIZE - 1)) & PAGE_MASK; > + end = ((unsigned long)ptr + size) & PAGE_MASK; > + > + for (; addr < end; addr += PAGE_SIZE) { > + ClearPageReserved(virt_to_page(__va(addr))); > + init_page_count(virt_to_page(__va(addr))); > + free_page((unsigned long)__va(addr)); > + } > +} > +EXPORT_SYMBOL(platform_release_memory); > + > +/* > + * > + * FEATURE AVAILABILITY FUNCTIONS > + * > + */ > +int platform_supports_dvr(void) > +{ > + return (platform_features & DVR_CAPABLE) != 0; > +} > + > +int platform_supports_ffs(void) > +{ > + return (platform_features & FFS_CAPABLE) != 0; > +} > + > +int platform_supports_pcie(void) > +{ > + return (platform_features & PCIE_CAPABLE) != 0; > +} > + > +int platform_supports_display(void) > +{ > + return (platform_features & DISPLAY_CAPABLE) != 0; > +} > diff --git a/arch/mips/powertv/asic/asic_int.c b/arch/mips/powertv/asic/asic_int.c > new file mode 100644 > index 0000000..ba60bd6 > --- /dev/null > +++ b/arch/mips/powertv/asic/asic_int.c > @@ -0,0 +1,125 @@ > +/* > + * Carsten Langgaard, carstenl@mips.com > + * Copyright (C) 2000, 2001, 2004 MIPS Technologies, Inc. > + * Copyright (C) 2001 Ralf Baechle > + * Portions copyright (C) 2009 Cisco Systems, Inc. > + * > + * This program is free software; you can distribute it and/or modify it > + * under the terms of the GNU General Public License (Version 2) as > + * published by the Free Software Foundation. > + * > + * This program is distributed in the hope it will be useful, but WITHOUT > + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or > + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License > + * for more details. > + * > + * You should have received a copy of the GNU General Public License along > + * with this program; if not, write to the Free Software Foundation, Inc., > + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. > + * > + * Routines for generic manipulation of the interrupts found on the PowerTV > + * platform. > + * > + * The interrupt controller is located in the South Bridge a PIIX4 device > + * with two internal 82C95 interrupt controllers. > + */ > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#include > +#include > +#include > +#include > + > +#include > + > +static DEFINE_SPINLOCK(asic_irq_lock); > + > +static inline int get_int(void) > +{ > + unsigned long flags; > + int irq; > + > + spin_lock_irqsave(&asic_irq_lock, flags); > + > + irq = (asic_read(int_int_scan) >> 4) - 1; > + > + if (irq == 0 || irq >= NR_IRQS) > + irq = -1; > + > + spin_unlock_irqrestore(&asic_irq_lock, flags); > + > + return irq; > +} > + > +static void asic_irqdispatch(void) > +{ > + int irq; > + > + irq = get_int(); > + if (irq < 0) > + return; /* interrupt has already been cleared */ > + > + do_IRQ(irq); > +} > + > +static inline int clz(unsigned long x) > +{ > + __asm__( > + " .set push \n" > + " .set mips32 \n" > + " clz %0, %1 \n" > + " .set pop \n" > + : "=r" (x) > + : "r" (x)); > + > + return x; > +} > + > +/* > + * Version of ffs that only looks at bits 12..15. > + */ > +static inline unsigned int irq_ffs(unsigned int pending) > +{ > + return -clz(pending) + 31 - CAUSEB_IP; > +} Please use fls() from instead and get rid of clz(). For MIPS32 processors fls() is implemented using CLZ. > + > +/* > + * TODO: check how it works under EIC mode. > + */ > +asmlinkage void plat_irq_dispatch(void) > +{ > + unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM; > + int irq; > + > + irq = irq_ffs(pending); > + > + if (irq == CAUSEF_IP3) > + asic_irqdispatch(); > + else if (irq >= 0) > + do_IRQ(irq); > + else > + spurious_interrupt(); > +} > + > +void __init arch_init_irq(void) > +{ > + int i; > + > + asic_irq_init(); > + > + /* > + * Initialize interrupt exception vectors. > + */ > + if (cpu_has_veic || cpu_has_vint) { > + int nvec = cpu_has_veic ? 64 : 8; > + for (i = 0; i < nvec; i++) > + set_vi_handler(i, asic_irqdispatch); > + } > +} > diff --git a/arch/mips/powertv/asic/irq_asic.c b/arch/mips/powertv/asic/irq_asic.c > new file mode 100644 > index 0000000..b54d244 > --- /dev/null > +++ b/arch/mips/powertv/asic/irq_asic.c > @@ -0,0 +1,116 @@ > +/* > + * Portions copyright (C) 2005-2009 Scientific Atlanta > + * Portions copyright (C) 2009 Cisco Systems, Inc. > + * > + * Modified from arch/mips/kernel/irq-rm7000.c: > + * Copyright (C) 2003 Ralf Baechle > + * > + * This program is free software; you can redistribute it and/or modify it > + * under the terms of the GNU General Public License as published by the > + * Free Software Foundation; either version 2 of the License, or (at your > + * option) any later version. > + */ > +#include > +#include > +#include > + > +#include > +#include > +#include > + > +#include > + > +static inline void unmask_asic_irq(unsigned int irq) > +{ > + unsigned long enable_bit; > + > + enable_bit = (1 << (irq & 0x1f)); > + > + switch (irq >> 5) { > + case 0: > + asic_write(asic_read(ien_int_0) | enable_bit, ien_int_0); > + break; > + case 1: > + asic_write(asic_read(ien_int_1) | enable_bit, ien_int_1); > + break; > + case 2: > + asic_write(asic_read(ien_int_2) | enable_bit, ien_int_2); > + break; > + case 3: > + asic_write(asic_read(ien_int_3) | enable_bit, ien_int_3); > + break; > + default: > + BUG(); > + } > +} > + > +static inline void mask_asic_irq(unsigned int irq) > +{ > + unsigned long disable_mask; > + > + disable_mask = ~(1 << (irq & 0x1f)); > + > + switch (irq >> 5) { > + case 0: > + asic_write(asic_read(ien_int_0) & disable_mask, ien_int_0); > + break; > + case 1: > + asic_write(asic_read(ien_int_1) & disable_mask, ien_int_1); > + break; > + case 2: > + asic_write(asic_read(ien_int_2) & disable_mask, ien_int_2); > + break; > + case 3: > + asic_write(asic_read(ien_int_3) & disable_mask, ien_int_3); > + break; > + default: > + BUG(); > + } > +} > + > +static struct irq_chip asic_irq_chip = { > + .name = "ASIC Level", > + .ack = mask_asic_irq, > + .mask = mask_asic_irq, > + .mask_ack = mask_asic_irq, > + .unmask = unmask_asic_irq, > + .eoi = unmask_asic_irq, > +}; > + > +void __init asic_irq_init(void) > +{ > + int i; > + > + /* set priority to 0 */ > + write_c0_status(read_c0_status() & ~(0x0000fc00)); > + > + asic_write(0, ien_int_0); > + asic_write(0, ien_int_1); > + asic_write(0, ien_int_2); > + asic_write(0, ien_int_3); > + > + asic_write(0x0fffffff, int_level_3_3); > + asic_write(0xffffffff, int_level_3_2); > + asic_write(0xffffffff, int_level_3_1); > + asic_write(0xffffffff, int_level_3_0); > + asic_write(0xffffffff, int_level_2_3); > + asic_write(0xffffffff, int_level_2_2); > + asic_write(0xffffffff, int_level_2_1); > + asic_write(0xffffffff, int_level_2_0); > + asic_write(0xffffffff, int_level_1_3); > + asic_write(0xffffffff, int_level_1_2); > + asic_write(0xffffffff, int_level_1_1); > + asic_write(0xffffffff, int_level_1_0); > + asic_write(0xffffffff, int_level_0_3); > + asic_write(0xffffffff, int_level_0_2); > + asic_write(0xffffffff, int_level_0_1); > + asic_write(0xffffffff, int_level_0_0); > + > + asic_write(0xf, int_int_scan); > + > + /* > + * Initialize interrupt handlers. > + */ > + for (i = 0; i < NR_IRQS; i++) > + set_irq_chip_and_handler(i, &asic_irq_chip, handle_level_irq); > +} > diff --git a/arch/mips/powertv/asic/prealloc-calliope.c b/arch/mips/powertv/asic/prealloc-calliope.c > new file mode 100644 > index 0000000..6823c4c > --- /dev/null > +++ b/arch/mips/powertv/asic/prealloc-calliope.c > @@ -0,0 +1,642 @@ > +/* > + * prealloc-calliope.c > + * > + * Memory pre-allocations for Calliope boxes. > + * > + * Copyright (C) 2005-2009 Scientific-Atlanta, Inc. > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, write to the Free Software > + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA > + * > + * Author: Ken Eppinett > + * David Schleef > + */ > + > +#include > +#include > + > +/* > + * NON_DVR_CAPABLE CALLIOPE RESOURCES > + */ > +struct resource non_dvr_calliope_resources[] __initdata = > +{ > + /* > + * VIDEO / LX1 > + */ > + { > + .name = "ST231aImage", /* Delta-Mu 1 image and ram */ > + .start = 0x24000000, > + .end = 0x24200000 - 1, /*2MiB */ > + .flags = IORESOURCE_MEM, > + }, > + { > + .name = "ST231aMonitor", /*8KiB block ST231a monitor */ > + .start = 0x24200000, > + .end = 0x24202000 - 1, > + .flags = IORESOURCE_MEM, > + }, > + { > + .name = "MediaMemory1", > + .start = 0x24202000, > + .end = 0x26700000 - 1, /*~36.9MiB (32MiB - (2MiB + 8KiB)) */ > + .flags = IORESOURCE_MEM, > + }, > + /* > + * Sysaudio Driver > + */ > + { > + .name = "DSP_Image_Buff", > + .start = 0x00000000, > + .end = 0x000FFFFF, > + .flags = IORESOURCE_MEM, > + }, > + { > + .name = "ADSC_CPU_PCM_Buff", > + .start = 0x00000000, > + .end = 0x00009FFF, > + .flags = IORESOURCE_MEM, > + }, > + { > + .name = "ADSC_AUX_Buff", > + .start = 0x00000000, > + .end = 0x00003FFF, > + .flags = IORESOURCE_MEM, > + }, > + { > + .name = "ADSC_Main_Buff", > + .start = 0x00000000, > + .end = 0x00003FFF, > + .flags = IORESOURCE_MEM, > + }, > + /* > + * STAVEM driver/STAPI > + */ > + { > + .name = "AVMEMPartition0", > + .start = 0x00000000, > + .end = 0x00600000 - 1, /* 6 MB total */ > + .flags = IORESOURCE_MEM, > + }, > + /* > + * DOCSIS Subsystem > + */ > + { > + .name = "Docsis", > + .start = 0x22000000, > + .end = 0x22700000 - 1, > + .flags = IORESOURCE_MEM, > + }, > + /* > + * GHW HAL Driver > + */ > + { > + .name = "GraphicsHeap", > + .start = 0x22700000, > + .end = 0x23500000 - 1, /* 14 MB total */ > + .flags = IORESOURCE_MEM, > + }, > + /* > + * multi com buffer area > + */ > + { > + .name = "MulticomSHM", > + .start = 0x23700000, > + .end = 0x23720000 - 1, > + .flags = IORESOURCE_MEM, > + }, > + /* > + * DMA Ring buffer (don't need recording buffers) > + */ > + { > + .name = "BMM_Buffer", > + .start = 0x00000000, > + .end = 0x000AA000 - 1, > + .flags = IORESOURCE_MEM, > + }, > + /* > + * Display bins buffer for unit0 > + */ > + { > + .name = "DisplayBins0", > + .start = 0x00000000, > + .end = 0x00000FFF, /* 4 KB total */ > + .flags = IORESOURCE_MEM, > + }, > + /* > + * > + * AVFS: player HAL memory > + * > + * > + */ > + { > + .name = "AvfsDmaMem", > + .start = 0x00000000, > + .end = 0x002c4c00 - 1, /* 945K * 3 for playback */ > + .flags = IORESOURCE_MEM, > + }, > + /* > + * PMEM > + */ > + { > + .name = "DiagPersistentMemory", > + .start = 0x00000000, > + .end = 0x10000 - 1, > + .flags = IORESOURCE_MEM, > + }, > + /* > + * Smartcard > + */ > + { > + .name = "SmartCardInfo", > + .start = 0x00000000, > + .end = 0x2800 - 1, > + .flags = IORESOURCE_MEM, > + }, > + /* > + * NAND Flash > + */ > + { > + .name = "NandFlash", > + .start = NAND_FLASH_BASE, > + .end = NAND_FLASH_BASE + 0x400 - 1, > + .flags = IORESOURCE_IO, > + }, > + /* > + * Synopsys GMAC Memory Region > + */ > + { > + .name = "GMAC", > + .start = 0x00000000, > + .end = 0x00010000 - 1, > + .flags = IORESOURCE_MEM, > + }, > + /* > + * Add other resources here > + * > + */ > + /* > + * End of Resource marker > + */ Some comments just don't deserve to exist ... > + { > + .flags = 0, No need to explicitly initialize a member of the end marker; just {} will do fine. > + }, > +}; > + > +struct resource non_dvr_vz_calliope_resources[] __initdata = > +{ > + /* > + * VIDEO / LX1 > + */ > + { > + .name = "ST231aImage", /* Delta-Mu 1 image and ram */ > + .start = 0x24000000, > + .end = 0x24200000 - 1, /*2 Meg */ > + .flags = IORESOURCE_MEM, > + }, > + { > + .name = "ST231aMonitor", /* 8k block ST231a monitor */ > + .start = 0x24200000, > + .end = 0x24202000 - 1, > + .flags = IORESOURCE_MEM, > + }, > + { > + .name = "MediaMemory1", > + .start = 0x22202000, > + .end = 0x22C20B85 - 1, /* 10.12 Meg */ > + .flags = IORESOURCE_MEM, > + }, > + /* > + * Sysaudio Driver > + */ > + { > + .name = "DSP_Image_Buff", > + .start = 0x00000000, > + .end = 0x000FFFFF, > + .flags = IORESOURCE_MEM, > + }, > + { > + .name = "ADSC_CPU_PCM_Buff", > + .start = 0x00000000, > + .end = 0x00009FFF, > + .flags = IORESOURCE_MEM, > + }, > + { > + .name = "ADSC_AUX_Buff", > + .start = 0x00000000, > + .end = 0x00003FFF, > + .flags = IORESOURCE_MEM, > + }, > + { > + .name = "ADSC_Main_Buff", > + .start = 0x00000000, > + .end = 0x00003FFF, > + .flags = IORESOURCE_MEM, > + }, > + /* > + * STAVEM driver/STAPI > + */ > + { > + .name = "AVMEMPartition0", > + .start = 0x20300000, > + .end = 0x20620000-1, /*3.125 MB total */ > + .flags = IORESOURCE_MEM, > + }, > + /* > + * GHW HAL Driver > + */ > + { > + .name = "GraphicsHeap", > + .start = 0x20100000, > + .end = 0x20300000 - 1, > + .flags = IORESOURCE_MEM, > + }, > + /* > + * multi com buffer area > + */ > + { > + .name = "MulticomSHM", > + .start = 0x23900000, > + .end = 0x23920000 - 1, > + .flags = IORESOURCE_MEM, > + }, > + /* > + * DMA Ring buffer > + */ > + { > + .name = "BMM_Buffer", > + .start = 0x00000000, > + .end = 0x000AA000 - 1, > + .flags = IORESOURCE_MEM, > + }, > + /* > + * Display bins buffer for unit0 > + */ > + { > + .name = "DisplayBins0", > + .start = 0x00000000, > + .end = 0x00000FFF, > + .flags = IORESOURCE_MEM, > + }, > + /* > + * PMEM > + */ > + { > + .name = "DiagPersistentMemory", > + .start = 0x00000000, > + .end = 0x10000 - 1, > + .flags = IORESOURCE_MEM, > + }, > + /* > + * Smartcard > + */ > + { > + .name = "SmartCardInfo", > + .start = 0x00000000, > + .end = 0x2800 - 1, > + .flags = IORESOURCE_MEM, > + }, > + /* > + * NAND Flash > + */ > + { > + .name = "NandFlash", > + .start = NAND_FLASH_BASE, > + .end = NAND_FLASH_BASE+0x400 - 1, > + .flags = IORESOURCE_IO, > + }, > + /* > + * Synopsys GMAC Memory Region > + */ > + { > + .name = "GMAC", > + .start = 0x00000000, > + .end = 0x00010000 - 1, > + .flags = IORESOURCE_MEM, > + }, > + /* > + * Add other resources here > + */ > + /* > + * End of Resource marker > + */ Some comments just don't deserve to exist ... > + { > + .flags = 0, No need to explicitly initialize a member of the end marker; just {} will do fine. > + }, > +}; > + > +struct resource non_dvr_vze_calliope_resources[] __initdata = > +{ > + /* > + * VIDEO / LX1 > + */ > + { > + .name = "ST231aImage", /* Delta-Mu 1 image and ram */ > + .start = 0x22000000, > + .end = 0x22200000 - 1, /*2 Meg */ > + .flags = IORESOURCE_MEM, > + }, > + { > + .name = "ST231aMonitor", /* 8k block ST231a monitor */ > + .start = 0x22200000, > + .end = 0x22202000 - 1, > + .flags = IORESOURCE_MEM, > + }, > + { > + .name = "MediaMemory1", > + .start = 0x22202000, > + .end = 0x22C20B85 - 1, /* 10.12 Meg */ > + .flags = IORESOURCE_MEM, > + }, > + /* > + * Sysaudio Driver > + */ > + { > + .name = "DSP_Image_Buff", > + .start = 0x00000000, > + .end = 0x000FFFFF, > + .flags = IORESOURCE_MEM, > + }, > + { > + .name = "ADSC_CPU_PCM_Buff", > + .start = 0x00000000, > + .end = 0x00009FFF, > + .flags = IORESOURCE_MEM, > + }, > + { > + .name = "ADSC_AUX_Buff", > + .start = 0x00000000, > + .end = 0x00003FFF, > + .flags = IORESOURCE_MEM, > + }, > + { > + .name = "ADSC_Main_Buff", > + .start = 0x00000000, > + .end = 0x00003FFF, > + .flags = IORESOURCE_MEM, > + }, > + /* > + * STAVEM driver/STAPI > + */ > + { > + .name = "AVMEMPartition0", > + .start = 0x20396000, > + .end = 0x206B6000 - 1, /* 3.125 MB total */ > + .flags = IORESOURCE_MEM, > + }, > + /* > + * GHW HAL Driver > + */ > + { > + .name = "GraphicsHeap", > + .start = 0x20100000, > + .end = 0x20396000 - 1, > + .flags = IORESOURCE_MEM, > + }, > + /* > + * multi com buffer area > + */ > + { > + .name = "MulticomSHM", > + .start = 0x206B6000, > + .end = 0x206D6000 - 1, > + .flags = IORESOURCE_MEM, > + }, > + /* > + * DMA Ring buffer > + */ > + { > + .name = "BMM_Buffer", > + .start = 0x00000000, > + .end = 0x000AA000 - 1, > + .flags = IORESOURCE_MEM, > + }, > + /* > + * Display bins buffer for unit0 > + */ > + { > + .name = "DisplayBins0", > + .start = 0x00000000, > + .end = 0x00000FFF, > + .flags = IORESOURCE_MEM, > + }, > + /* > + * PMEM > + */ > + { > + .name = "DiagPersistentMemory", > + .start = 0x00000000, > + .end = 0x10000 - 1, > + .flags = IORESOURCE_MEM, > + }, > + /* > + * Smartcard > + */ > + { > + .name = "SmartCardInfo", > + .start = 0x00000000, > + .end = 0x2800 - 1, > + .flags = IORESOURCE_MEM, > + }, > + /* > + * NAND Flash > + */ > + { > + .name = "NandFlash", > + .start = NAND_FLASH_BASE, > + .end = NAND_FLASH_BASE+0x400 - 1, > + .flags = IORESOURCE_MEM, > + }, > + /* > + * Synopsys GMAC Memory Region > + */ > + { > + .name = "GMAC", > + .start = 0x00000000, > + .end = 0x00010000 - 1, > + .flags = IORESOURCE_MEM, > + }, > + /* > + * Add other resources here > + */ > + /* > + * End of Resource marker > + */ Some comments just don't deserve to exist ... > + { > + .flags = 0, No need to explicitly initialize a member of the end marker; just {} will do fine. > + }, > +}; > + > +struct resource non_dvr_vzf_calliope_resources[] __initdata = > +{ > + /* > + * VIDEO / LX1 > + */ > + { > + .name = "ST231aImage", /*Delta-Mu 1 image and ram */ > + .start = 0x24000000, > + .end = 0x24200000 - 1, /*2MiB */ > + .flags = IORESOURCE_MEM, > + }, > + { > + .name = "ST231aMonitor", /*8KiB block ST231a monitor */ > + .start = 0x24200000, > + .end = 0x24202000 - 1, > + .flags = IORESOURCE_MEM, > + }, > + { > + .name = "MediaMemory1", > + .start = 0x24202000, > + /* ~19.4 (21.5MiB - (2MiB + 8KiB)) */ > + .end = 0x25580000 - 1, > + .flags = IORESOURCE_MEM, > + }, > + /* > + * Sysaudio Driver > + */ > + { > + .name = "DSP_Image_Buff", > + .start = 0x00000000, > + .end = 0x000FFFFF, > + .flags = IORESOURCE_MEM, > + }, > + { > + .name = "ADSC_CPU_PCM_Buff", > + .start = 0x00000000, > + .end = 0x00009FFF, > + .flags = IORESOURCE_MEM, > + }, > + { > + .name = "ADSC_AUX_Buff", > + .start = 0x00000000, > + .end = 0x00003FFF, > + .flags = IORESOURCE_MEM, > + }, > + { > + .name = "ADSC_Main_Buff", > + .start = 0x00000000, > + .end = 0x00003FFF, > + .flags = IORESOURCE_MEM, > + }, > + /* > + * STAVEM driver/STAPI > + */ > + { > + .name = "AVMEMPartition0", > + .start = 0x00000000, > + .end = 0x00480000 - 1, /* 4.5 MB total */ > + .flags = IORESOURCE_MEM, > + }, > + /* > + * GHW HAL Driver > + */ > + { > + .name = "GraphicsHeap", > + .start = 0x22700000, > + .end = 0x23500000 - 1, /* 14 MB total */ > + .flags = IORESOURCE_MEM, > + }, > + /* > + * multi com buffer area > + */ > + { > + .name = "MulticomSHM", > + .start = 0x23700000, > + .end = 0x23720000 - 1, > + .flags = IORESOURCE_MEM, > + }, > + /* > + * DMA Ring buffer (don't need recording buffers) > + */ > + { > + .name = "BMM_Buffer", > + .start = 0x00000000, > + .end = 0x000AA000 - 1, > + .flags = IORESOURCE_MEM, > + }, > + /* > + * Display bins buffer for unit0 > + */ > + { > + .name = "DisplayBins0", > + .start = 0x00000000, > + .end = 0x00000FFF, /* 4 KB total */ > + .flags = IORESOURCE_MEM, > + }, > + /* > + * Display bins buffer for unit1 > + */ > + { > + .name = "DisplayBins1", > + .start = 0x00000000, > + .end = 0x00000FFF, /* 4 KB total */ > + .flags = IORESOURCE_MEM, > + }, > + /* > + * > + * AVFS: player HAL memory > + * > + * > + */ > + { > + .name = "AvfsDmaMem", > + .start = 0x00000000, > + .end = 0x002c4c00 - 1, /* 945K * 3 for playback */ > + .flags = IORESOURCE_MEM, > + }, > + /* > + * PMEM > + */ > + { > + .name = "DiagPersistentMemory", > + .start = 0x00000000, > + .end = 0x10000 - 1, > + .flags = IORESOURCE_MEM, > + }, > + /* > + * Smartcard > + */ > + { > + .name = "SmartCardInfo", > + .start = 0x00000000, > + .end = 0x2800 - 1, > + .flags = IORESOURCE_MEM, > + }, > + /* > + * NAND Flash > + */ > + { > + .name = "NandFlash", > + .start = NAND_FLASH_BASE, > + .end = NAND_FLASH_BASE + 0x400 - 1, > + .flags = IORESOURCE_MEM, > + }, > + /* > + * Synopsys GMAC Memory Region > + */ > + { > + .name = "GMAC", > + .start = 0x00000000, > + .end = 0x00010000 - 1, > + .flags = IORESOURCE_MEM, > + }, > + /* > + * Add other resources here > + */ > + /* > + * End of Resource marker > + */ Some comments just don't deserve to exist ... > + { > + .flags = 0, No need to explicitly initialize a member of the end marker; just {} will do fine. > + }, > +}; > diff --git a/arch/mips/powertv/asic/prealloc-cronus.c b/arch/mips/powertv/asic/prealloc-cronus.c > new file mode 100644 > index 0000000..b433efd > --- /dev/null > +++ b/arch/mips/powertv/asic/prealloc-cronus.c > @@ -0,0 +1,625 @@ > +/* > + * prealloc-cronus.c > + * > + * Memory pre-allocations for Cronus boxes. > + * > + * Copyright (C) 2005-2009 Scientific-Atlanta, Inc. > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, write to the Free Software > + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA > + * > + * Author: Ken Eppinett > + * David Schleef > + */ > + > +#include > +#include > + > +/* > + * DVR_CAPABLE CRONUS RESOURCES > + */ > +struct resource dvr_cronus_resources[] __initdata = > +{ > + /* > + * > + * VIDEO1 / LX1 > + * > + */ > + { > + .name = "ST231aImage", /* Delta-Mu 1 image and ram */ > + .start = 0x24000000, > + .end = 0x241FFFFF, /* 2MiB */ > + .flags = IORESOURCE_MEM, > + }, > + { > + .name = "ST231aMonitor", /* 8KiB block ST231a monitor */ > + .start = 0x24200000, > + .end = 0x24201FFF, > + .flags = IORESOURCE_MEM, > + }, > + { > + .name = "MediaMemory1", > + .start = 0x24202000, > + .end = 0x25FFFFFF, /*~29.9MiB (32MiB - (2MiB + 8KiB)) */ > + .flags = IORESOURCE_MEM, > + }, > + /* > + * > + * VIDEO2 / LX2 > + * > + */ > + { > + .name = "ST231bImage", /* Delta-Mu 2 image and ram */ > + .start = 0x60000000, > + .end = 0x601FFFFF, /* 2MiB */ > + .flags = IORESOURCE_IO, > + }, > + { > + .name = "ST231bMonitor", /* 8KiB block ST231b monitor */ > + .start = 0x60200000, > + .end = 0x60201FFF, > + .flags = IORESOURCE_IO, > + }, > + { > + .name = "MediaMemory2", > + .start = 0x60202000, > + .end = 0x61FFFFFF, /*~29.9MiB (32MiB - (2MiB + 8KiB)) */ > + .flags = IORESOURCE_IO, > + }, > + /* > + * > + * Sysaudio Driver > + * > + * This driver requires: > + * > + * Arbitrary Based Buffers: > + * DSP_Image_Buff - DSP code and data images (1MB) > + * ADSC_CPU_PCM_Buff - ADSC CPU PCM buffer (40KB) > + * ADSC_AUX_Buff - ADSC AUX buffer (16KB) > + * ADSC_Main_Buff - ADSC Main buffer (16KB) > + * > + */ > + { > + .name = "DSP_Image_Buff", > + .start = 0x00000000, > + .end = 0x000FFFFF, > + .flags = IORESOURCE_MEM, > + }, > + { > + .name = "ADSC_CPU_PCM_Buff", > + .start = 0x00000000, > + .end = 0x00009FFF, > + .flags = IORESOURCE_MEM, > + }, > + { > + .name = "ADSC_AUX_Buff", > + .start = 0x00000000, > + .end = 0x00003FFF, > + .flags = IORESOURCE_MEM, > + }, > + { > + .name = "ADSC_Main_Buff", > + .start = 0x00000000, > + .end = 0x00003FFF, > + .flags = IORESOURCE_MEM, > + }, > + /* > + * > + * STAVEM driver/STAPI > + * > + * This driver requires: > + * > + * Arbitrary Based Buffers: > + * This memory area is used for allocating buffers for Video decoding > + * purposes. Allocation/De-allocation within this buffer is managed > + * by the STAVMEM driver of the STAPI. They could be Decimated > + * Picture Buffers, Intermediate Buffers, as deemed necessary for > + * video decoding purposes, for any video decoders on Zeus. > + * > + */ > + { > + .name = "AVMEMPartition0", > + .start = 0x63580000, > + .end = 0x64180000 - 1, /* 12 MB total */ > + .flags = IORESOURCE_IO, > + }, > + /* > + * > + * DOCSIS Subsystem > + * > + * This driver requires: > + * > + * Arbitrary Based Buffers: > + * Docsis - > + * > + */ > + { > + .name = "Docsis", > + .start = 0x62000000, > + .end = 0x62700000 - 1, /* 7 MB total */ > + .flags = IORESOURCE_IO, > + }, > + /* > + * > + * GHW HAL Driver > + * > + * This driver requires: > + * > + * Arbitrary Based Buffers: > + * GraphicsHeap - PowerTV Graphics Heap > + * > + */ > + { > + .name = "GraphicsHeap", > + .start = 0x62700000, > + .end = 0x63500000 - 1, /* 14 MB total */ > + .flags = IORESOURCE_IO, > + }, > + /* > + * > + * multi com buffer area > + * > + * This driver requires: > + * > + * Arbitrary Based Buffers: > + * Docsis - > + * > + */ > + { > + .name = "MulticomSHM", > + .start = 0x26000000, > + .end = 0x26020000 - 1, > + .flags = IORESOURCE_MEM, > + }, > + /* > + * > + * DMA Ring buffer > + * > + * This driver requires: > + * > + * Arbitrary Based Buffers: > + * Docsis - > + * > + */ > + { > + .name = "BMM_Buffer", > + .start = 0x00000000, > + .end = 0x00280000 - 1, > + .flags = IORESOURCE_MEM, > + }, > + /* > + * > + * Display bins buffer for unit0 > + * > + * This driver requires: > + * > + * Arbitrary Based Buffers: > + * Display Bins for unit0 > + * > + */ > + { > + .name = "DisplayBins0", > + .start = 0x00000000, > + .end = 0x00000FFF, /* 4 KB total */ > + .flags = IORESOURCE_MEM, > + }, > + /* > + * > + * Display bins buffer > + * > + * This driver requires: > + * > + * Arbitrary Based Buffers: > + * Display Bins for unit1 > + * > + */ > + { > + .name = "DisplayBins1", > + .start = 0x64AD4000, > + .end = 0x64AD5000 - 1, /* 4 KB total */ > + .flags = IORESOURCE_IO, > + }, > + /* > + * > + * ITFS > + * > + * This driver requires: > + * > + * Arbitrary Based Buffers: > + * Docsis - > + * > + */ > + { > + .name = "ITFS", > + .start = 0x64180000, > + /* 815,104 bytes each for 2 ITFS partitions. */ > + .end = 0x6430DFFF, > + .flags = IORESOURCE_IO, > + }, > + /* > + * > + * AVFS > + * > + * This driver requires: > + * > + * Arbitrary Based Buffers: > + * Docsis - > + * > + */ > + { > + .name = "AvfsDmaMem", > + .start = 0x6430E000, > + /* (945K * 8) = (128K *3) 5 playbacks / 3 server */ > + .end = 0x64AD0000 - 1, > + .flags = IORESOURCE_IO, > + }, > + { > + .name = "AvfsFileSys", > + .start = 0x64AD0000, > + .end = 0x64AD1000 - 1, /* 4K */ > + .flags = IORESOURCE_IO, > + }, > + /* > + * > + * PMEM > + * > + * This driver requires: > + * > + * Arbitrary Based Buffers: > + * Persistent memory for diagnostics. > + * > + */ > + { > + .name = "DiagPersistentMemory", > + .start = 0x00000000, > + .end = 0x10000 - 1, > + .flags = IORESOURCE_MEM, > + }, > + /* > + * > + * Smartcard > + * > + * This driver requires: > + * > + * Arbitrary Based Buffers: > + * Read and write buffers for Internal/External cards > + * > + */ > + { > + .name = "SmartCardInfo", > + .start = 0x64AD1000, > + .end = 0x64AD3800 - 1, > + .flags = IORESOURCE_IO, > + }, > + /* > + * > + * KAVNET > + * NP Reset Vector - must be of the form xxCxxxxx > + * NP Image - must be video bank 1 > + * NP IPC - must be video bank 2 > + */ > + { > + .name = "NP_Reset_Vector", > + .start = 0x27c00000, > + .end = 0x27c01000 - 1, > + .flags = IORESOURCE_MEM, > + }, > + { > + .name = "NP_Image", > + .start = 0x27020000, > + .end = 0x27060000 - 1, > + .flags = IORESOURCE_MEM, > + }, > + { > + .name = "NP_IPC", > + .start = 0x63500000, > + .end = 0x63580000 - 1, > + .flags = IORESOURCE_IO, > + }, > + /* > + * Add other resources here > + */ > + /* > + * End of Resource marker > + * > + */ Some comments just don't deserve to exist ... > + { > + .flags = 0, No need to explicitly initialize a member of the end marker; just {} will do fine. > + }, > +}; > + > +/* > + * NON_DVR_CAPABLE CRONUS RESOURCES > + */ > +struct resource non_dvr_cronus_resources[] __initdata = > +{ > + /* > + * > + * VIDEO1 / LX1 > + * > + */ > + { > + .name = "ST231aImage", /* Delta-Mu 1 image and ram */ > + .start = 0x24000000, > + .end = 0x241FFFFF, /* 2MiB */ > + .flags = IORESOURCE_MEM, > + }, > + { > + .name = "ST231aMonitor", /* 8KiB block ST231a monitor */ > + .start = 0x24200000, > + .end = 0x24201FFF, > + .flags = IORESOURCE_MEM, > + }, > + { > + .name = "MediaMemory1", > + .start = 0x24202000, > + .end = 0x25FFFFFF, /*~29.9MiB (32MiB - (2MiB + 8KiB)) */ > + .flags = IORESOURCE_MEM, > + }, > + /* > + * > + * VIDEO2 / LX2 > + * > + */ > + { > + .name = "ST231bImage", /* Delta-Mu 2 image and ram */ > + .start = 0x60000000, > + .end = 0x601FFFFF, /* 2MiB */ > + .flags = IORESOURCE_IO, > + }, > + { > + .name = "ST231bMonitor", /* 8KiB block ST231b monitor */ > + .start = 0x60200000, > + .end = 0x60201FFF, > + .flags = IORESOURCE_IO, > + }, > + { > + .name = "MediaMemory2", > + .start = 0x60202000, > + .end = 0x61FFFFFF, /*~29.9MiB (32MiB - (2MiB + 8KiB)) */ > + .flags = IORESOURCE_IO, > + }, > + /* > + * > + * Sysaudio Driver > + * > + * This driver requires: > + * > + * Arbitrary Based Buffers: > + * DSP_Image_Buff - DSP code and data images (1MB) > + * ADSC_CPU_PCM_Buff - ADSC CPU PCM buffer (40KB) > + * ADSC_AUX_Buff - ADSC AUX buffer (16KB) > + * ADSC_Main_Buff - ADSC Main buffer (16KB) > + * > + */ > + { > + .name = "DSP_Image_Buff", > + .start = 0x00000000, > + .end = 0x000FFFFF, > + .flags = IORESOURCE_MEM, > + }, > + { > + .name = "ADSC_CPU_PCM_Buff", > + .start = 0x00000000, > + .end = 0x00009FFF, > + .flags = IORESOURCE_MEM, > + }, > + { > + .name = "ADSC_AUX_Buff", > + .start = 0x00000000, > + .end = 0x00003FFF, > + .flags = IORESOURCE_MEM, > + }, > + { > + .name = "ADSC_Main_Buff", > + .start = 0x00000000, > + .end = 0x00003FFF, > + .flags = IORESOURCE_MEM, > + }, > + /* > + * > + * STAVEM driver/STAPI > + * > + * This driver requires: > + * > + * Arbitrary Based Buffers: > + * This memory area is used for allocating buffers for Video decoding > + * purposes. Allocation/De-allocation within this buffer is managed > + * by the STAVMEM driver of the STAPI. They could be Decimated > + * Picture Buffers, Intermediate Buffers, as deemed necessary for > + * video decoding purposes, for any video decoders on Zeus. > + * > + */ > + { > + .name = "AVMEMPartition0", > + .start = 0x63580000, > + .end = 0x64180000 - 1, /* 12 MB total */ > + .flags = IORESOURCE_IO, > + }, > + /* > + * > + * DOCSIS Subsystem > + * > + * This driver requires: > + * > + * Arbitrary Based Buffers: > + * Docsis - > + * > + */ > + { > + .name = "Docsis", > + .start = 0x62000000, > + .end = 0x62700000 - 1, /* 7 MB total */ > + .flags = IORESOURCE_IO, > + }, > + /* > + * > + * GHW HAL Driver > + * > + * This driver requires: > + * > + * Arbitrary Based Buffers: > + * GraphicsHeap - PowerTV Graphics Heap > + * > + */ > + { > + .name = "GraphicsHeap", > + .start = 0x62700000, > + .end = 0x63500000 - 1, /* 14 MB total */ > + .flags = IORESOURCE_IO, > + }, > + /* > + * > + * multi com buffer area > + * > + * This driver requires: > + * > + * Arbitrary Based Buffers: > + * Docsis - > + * > + */ > + { > + .name = "MulticomSHM", > + .start = 0x26000000, > + .end = 0x26020000 - 1, > + .flags = IORESOURCE_MEM, > + }, > + /* > + * > + * DMA Ring buffer > + * > + * This driver requires: > + * > + * Arbitrary Based Buffers: > + * Docsis - > + * > + */ > + { > + .name = "BMM_Buffer", > + .start = 0x00000000, > + .end = 0x000AA000 - 1, > + .flags = IORESOURCE_MEM, > + }, > + /* > + * > + * Display bins buffer for unit0 > + * > + * This driver requires: > + * > + * Arbitrary Based Buffers: > + * Display Bins for unit0 > + * > + */ > + { > + .name = "DisplayBins0", > + .start = 0x00000000, > + .end = 0x00000FFF, /* 4 KB total */ > + .flags = IORESOURCE_MEM, > + }, > + /* > + * > + * Display bins buffer > + * > + * This driver requires: > + * > + * Arbitrary Based Buffers: > + * Display Bins for unit1 > + * > + */ > + { > + .name = "DisplayBins1", > + .start = 0x64AD4000, > + .end = 0x64AD5000 - 1, /* 4 KB total */ > + .flags = IORESOURCE_IO, > + }, > + /* > + * > + * AVFS: player HAL memory > + * > + * > + */ > + { > + .name = "AvfsDmaMem", > + .start = 0x6430E000, > + .end = 0x645D2C00 - 1, /* 945K * 3 for playback */ > + .flags = IORESOURCE_IO, > + }, > + /* > + * > + * PMEM > + * > + * This driver requires: > + * > + * Arbitrary Based Buffers: > + * Persistent memory for diagnostics. > + * > + */ > + { > + .name = "DiagPersistentMemory", > + .start = 0x00000000, > + .end = 0x10000 - 1, > + .flags = IORESOURCE_MEM, > + }, > + /* > + * > + * Smartcard > + * > + * This driver requires: > + * > + * Arbitrary Based Buffers: > + * Read and write buffers for Internal/External cards > + * > + */ > + { > + .name = "SmartCardInfo", > + .start = 0x64AD1000, > + .end = 0x64AD3800 - 1, > + .flags = IORESOURCE_IO, > + }, > + /* > + * > + * KAVNET > + * NP Reset Vector - must be of the form xxCxxxxx > + * NP Image - must be video bank 1 > + * NP IPC - must be video bank 2 > + */ > + { > + .name = "NP_Reset_Vector", > + .start = 0x27c00000, > + .end = 0x27c01000 - 1, > + .flags = IORESOURCE_MEM, > + }, > + { > + .name = "NP_Image", > + .start = 0x27020000, > + .end = 0x27060000 - 1, > + .flags = IORESOURCE_MEM, > + }, > + { > + .name = "NP_IPC", > + .start = 0x63500000, > + .end = 0x63580000 - 1, > + .flags = IORESOURCE_IO, > + }, > + /* > + * Add other resources here > + */ > + /* > + * End of Resource marker > + * > + */ Some comments just don't deserve to exist ... > + { > + .flags = 0, No need to explicitly initialize a member of the end marker; just {} will do fine. > + }, > +}; > diff --git a/arch/mips/powertv/asic/prealloc-cronuslite.c b/arch/mips/powertv/asic/prealloc-cronuslite.c > new file mode 100644 > index 0000000..5bba999 > --- /dev/null > +++ b/arch/mips/powertv/asic/prealloc-cronuslite.c > @@ -0,0 +1,298 @@ > +/* > + * prealloc-cronuslite.c > + * > + * Memory pre-allocations for Cronus Lite boxes. > + * > + * Copyright (C) 2005-2009 Scientific-Atlanta, Inc. > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, write to the Free Software > + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA > + * > + * Author: Ken Eppinett > + * David Schleef > + */ > + > +#include > +#include > + > +/* > + * NON_DVR_CAPABLE CRONUSLITE RESOURCES > + */ > +struct resource non_dvr_cronuslite_resources[] __initdata = > +{ > + /* > + * > + * VIDEO2 / LX2 > + * > + */ > + { > + .name = "ST231aImage", /* Delta-Mu 2 image and ram */ > + .start = 0x60000000, > + .end = 0x601FFFFF, /* 2MiB */ > + .flags = IORESOURCE_IO, > + }, > + { > + .name = "ST231aMonitor", /* 8KiB block ST231b monitor */ > + .start = 0x60200000, > + .end = 0x60201FFF, > + .flags = IORESOURCE_IO, > + }, > + { > + .name = "MediaMemory1", > + .start = 0x60202000, > + .end = 0x61FFFFFF, /*~29.9MiB (32MiB - (2MiB + 8KiB)) */ > + .flags = IORESOURCE_IO, > + }, > + /* > + * > + * Sysaudio Driver > + * > + * This driver requires: > + * > + * Arbitrary Based Buffers: > + * DSP_Image_Buff - DSP code and data images (1MB) > + * ADSC_CPU_PCM_Buff - ADSC CPU PCM buffer (40KB) > + * ADSC_AUX_Buff - ADSC AUX buffer (16KB) > + * ADSC_Main_Buff - ADSC Main buffer (16KB) > + * > + */ > + { > + .name = "DSP_Image_Buff", > + .start = 0x00000000, > + .end = 0x000FFFFF, > + .flags = IORESOURCE_MEM, > + }, > + { > + .name = "ADSC_CPU_PCM_Buff", > + .start = 0x00000000, > + .end = 0x00009FFF, > + .flags = IORESOURCE_MEM, > + }, > + { > + .name = "ADSC_AUX_Buff", > + .start = 0x00000000, > + .end = 0x00003FFF, > + .flags = IORESOURCE_MEM, > + }, > + { > + .name = "ADSC_Main_Buff", > + .start = 0x00000000, > + .end = 0x00003FFF, > + .flags = IORESOURCE_MEM, > + }, > + /* > + * > + * STAVEM driver/STAPI > + * > + * This driver requires: > + * > + * Arbitrary Based Buffers: > + * This memory area is used for allocating buffers for Video decoding > + * purposes. Allocation/De-allocation within this buffer is managed > + * by the STAVMEM driver of the STAPI. They could be Decimated > + * Picture Buffers, Intermediate Buffers, as deemed necessary for > + * video decoding purposes, for any video decoders on Zeus. > + * > + */ > + { > + .name = "AVMEMPartition0", > + .start = 0x63580000, > + .end = 0x63B80000 - 1, /* 6 MB total */ > + .flags = IORESOURCE_IO, > + }, > + /* > + * > + * DOCSIS Subsystem > + * > + * This driver requires: > + * > + * Arbitrary Based Buffers: > + * Docsis - > + * > + */ > + { > + .name = "Docsis", > + .start = 0x62000000, > + .end = 0x62700000 - 1, /* 7 MB total */ > + .flags = IORESOURCE_IO, > + }, > + /* > + * > + * GHW HAL Driver > + * > + * This driver requires: > + * > + * Arbitrary Based Buffers: > + * GraphicsHeap - PowerTV Graphics Heap > + * > + */ > + { > + .name = "GraphicsHeap", > + .start = 0x62700000, > + .end = 0x63500000 - 1, /* 14 MB total */ > + .flags = IORESOURCE_IO, > + }, > + /* > + * > + * multi com buffer area > + * > + * This driver requires: > + * > + * Arbitrary Based Buffers: > + * Docsis - > + * > + */ > + { > + .name = "MulticomSHM", > + .start = 0x26000000, > + .end = 0x26020000 - 1, > + .flags = IORESOURCE_MEM, > + }, > + /* > + * > + * DMA Ring buffer > + * > + * This driver requires: > + * > + * Arbitrary Based Buffers: > + * Docsis - > + * > + */ > + { > + .name = "BMM_Buffer", > + .start = 0x00000000, > + .end = 0x000AA000 - 1, > + .flags = IORESOURCE_MEM, > + }, > + /* > + * > + * Display bins buffer for unit0 > + * > + * This driver requires: > + * > + * Arbitrary Based Buffers: > + * Display Bins for unit0 > + * > + */ > + { > + .name = "DisplayBins0", > + .start = 0x00000000, > + .end = 0x00000FFF, /* 4 KB total */ > + .flags = IORESOURCE_MEM, > + }, > + /* > + * > + * Display bins buffer > + * > + * This driver requires: > + * > + * Arbitrary Based Buffers: > + * Display Bins for unit1 > + * > + */ > + { > + .name = "DisplayBins1", > + .start = 0x63B83000, > + .end = 0x63B84000 - 1, /* 4 KB total */ > + .flags = IORESOURCE_IO, > + }, > + /* > + * > + * AVFS: player HAL memory > + * > + * > + */ > + { > + .name = "AvfsDmaMem", > + .start = 0x63B84000, > + .end = 0x63E48C00 - 1, /* 945K * 3 for playback */ > + .flags = IORESOURCE_IO, > + }, > + /* > + * > + * PMEM > + * > + * This driver requires: > + * > + * Arbitrary Based Buffers: > + * Persistent memory for diagnostics. > + * > + */ > + { > + .name = "DiagPersistentMemory", > + .start = 0x00000000, > + .end = 0x10000 - 1, > + .flags = IORESOURCE_MEM, > + }, > + /* > + * > + * Smartcard > + * > + * This driver requires: > + * > + * Arbitrary Based Buffers: > + * Read and write buffers for Internal/External cards > + * > + */ > + { > + .name = "SmartCardInfo", > + .start = 0x63B80000, > + .end = 0x63B82800 - 1, > + .flags = IORESOURCE_IO, > + }, > + /* > + * > + * KAVNET > + * NP Reset Vector - must be of the form xxCxxxxx > + * NP Image - must be video bank 1 > + * NP IPC - must be video bank 2 > + */ > + { > + .name = "NP_Reset_Vector", > + .start = 0x27c00000, > + .end = 0x27c01000 - 1, > + .flags = IORESOURCE_MEM, > + }, > + { > + .name = "NP_Image", > + .start = 0x27020000, > + .end = 0x27060000 - 1, > + .flags = IORESOURCE_MEM, > + }, > + { > + .name = "NP_IPC", > + .start = 0x63500000, > + .end = 0x63580000 - 1, > + .flags = IORESOURCE_IO, > + }, > + /* > + * NAND Flash > + */ > + { > + .name = "NandFlash", > + .start = NAND_FLASH_BASE, > + .end = NAND_FLASH_BASE + 0x400 - 1, > + .flags = IORESOURCE_IO, > + }, > + /* > + * Add other resources here > + */ > + /* > + * End of Resource marker > + * > + */ Some comments just don't deserve to exist ... > + { > + .flags = 0, No need to explicitly initialize a member of the end marker; just {} will do fine. > + }, > +}; > diff --git a/arch/mips/powertv/asic/prealloc-zeus.c b/arch/mips/powertv/asic/prealloc-zeus.c > new file mode 100644 > index 0000000..3205954 > --- /dev/null > +++ b/arch/mips/powertv/asic/prealloc-zeus.c > @@ -0,0 +1,471 @@ > +/* > + * prealloc-zeus.c > + * > + * Memory pre-allocations for Zeus boxes. > + * > + * Copyright (C) 2005-2009 Scientific-Atlanta, Inc. > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, write to the Free Software > + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA > + * > + * Author: Ken Eppinett > + * David Schleef > + */ > + > +#include > +#include > + > +/* > + * DVR_CAPABLE RESOURCES > + */ > +struct resource dvr_zeus_resources[] __initdata = > +{ > + /* > + * > + * VIDEO1 / LX1 > + * > + */ > + { > + .name = "ST231aImage", /* Delta-Mu 1 image and ram */ > + .start = 0x20000000, > + .end = 0x201FFFFF, /* 2MiB */ > + .flags = IORESOURCE_IO, > + }, > + { > + .name = "ST231aMonitor", /* 8KiB block ST231a monitor */ > + .start = 0x20200000, > + .end = 0x20201FFF, > + .flags = IORESOURCE_IO, > + }, > + { > + .name = "MediaMemory1", > + .start = 0x20202000, > + .end = 0x21FFFFFF, /*~29.9MiB (32MiB - (2MiB + 8KiB)) */ > + .flags = IORESOURCE_IO, > + }, > + /* > + * > + * VIDEO2 / LX2 > + * > + */ > + { > + .name = "ST231bImage", /* Delta-Mu 2 image and ram */ > + .start = 0x30000000, > + .end = 0x301FFFFF, /* 2MiB */ > + .flags = IORESOURCE_IO, > + }, > + { > + .name = "ST231bMonitor", /* 8KiB block ST231b monitor */ > + .start = 0x30200000, > + .end = 0x30201FFF, > + .flags = IORESOURCE_IO, > + }, > + { > + .name = "MediaMemory2", > + .start = 0x30202000, > + .end = 0x31FFFFFF, /*~29.9MiB (32MiB - (2MiB + 8KiB)) */ > + .flags = IORESOURCE_IO, > + }, > + /* > + * > + * Sysaudio Driver > + * > + * This driver requires: > + * > + * Arbitrary Based Buffers: > + * DSP_Image_Buff - DSP code and data images (1MB) > + * ADSC_CPU_PCM_Buff - ADSC CPU PCM buffer (40KB) > + * ADSC_AUX_Buff - ADSC AUX buffer (16KB) > + * ADSC_Main_Buff - ADSC Main buffer (16KB) > + * > + */ > + { > + .name = "DSP_Image_Buff", > + .start = 0x00000000, > + .end = 0x000FFFFF, > + .flags = IORESOURCE_MEM, > + }, > + { > + .name = "ADSC_CPU_PCM_Buff", > + .start = 0x00000000, > + .end = 0x00009FFF, > + .flags = IORESOURCE_MEM, > + }, > + { > + .name = "ADSC_AUX_Buff", > + .start = 0x00000000, > + .end = 0x00003FFF, > + .flags = IORESOURCE_MEM, > + }, > + { > + .name = "ADSC_Main_Buff", > + .start = 0x00000000, > + .end = 0x00003FFF, > + .flags = IORESOURCE_MEM, > + }, > + /* > + * > + * STAVEM driver/STAPI > + * > + * This driver requires: > + * > + * Arbitrary Based Buffers: > + * This memory area is used for allocating buffers for Video decoding > + * purposes. Allocation/De-allocation within this buffer is managed > + * by the STAVMEM driver of the STAPI. They could be Decimated > + * Picture Buffers, Intermediate Buffers, as deemed necessary for > + * video decoding purposes, for any video decoders on Zeus. > + * > + */ > + { > + .name = "AVMEMPartition0", > + .start = 0x00000000, > + .end = 0x00c00000 - 1, /* 12 MB total */ > + .flags = IORESOURCE_MEM, > + }, > + /* > + * > + * DOCSIS Subsystem > + * > + * This driver requires: > + * > + * Arbitrary Based Buffers: > + * Docsis - > + * > + */ > + { > + .name = "Docsis", > + .start = 0x40100000, > + .end = 0x407fffff, > + .flags = IORESOURCE_MEM, > + }, > + /* > + * > + * GHW HAL Driver > + * > + * This driver requires: > + * > + * Arbitrary Based Buffers: > + * GraphicsHeap - PowerTV Graphics Heap > + * > + */ > + { > + .name = "GraphicsHeap", > + .start = 0x46900000, > + .end = 0x47700000 - 1, /* 14 MB total */ > + .flags = IORESOURCE_MEM, > + }, > + /* > + * > + * multi com buffer area > + * > + * This driver requires: > + * > + * Arbitrary Based Buffers: > + * Docsis - > + * > + */ > + { > + .name = "MulticomSHM", > + .start = 0x47900000, > + .end = 0x47920000 - 1, > + .flags = IORESOURCE_MEM, > + }, > + /* > + * > + * DMA Ring buffer > + * > + * This driver requires: > + * > + * Arbitrary Based Buffers: > + * Docsis - > + * > + */ > + { > + .name = "BMM_Buffer", > + .start = 0x00000000, > + .end = 0x00280000 - 1, > + .flags = IORESOURCE_MEM, > + }, > + /* > + * > + * Display bins buffer for unit0 > + * > + * This driver requires: > + * > + * Arbitrary Based Buffers: > + * Display Bins for unit0 > + * > + */ > + { > + .name = "DisplayBins0", > + .start = 0x00000000, > + .end = 0x00000FFF, /* 4 KB total */ > + .flags = IORESOURCE_MEM, > + }, > + /* > + * > + * Display bins buffer > + * > + * This driver requires: > + * > + * Arbitrary Based Buffers: > + * Display Bins for unit1 > + * > + */ > + { > + .name = "DisplayBins1", > + .start = 0x00000000, > + .end = 0x00000FFF, /* 4 KB total */ > + .flags = IORESOURCE_MEM, > + }, > + /* > + * > + * ITFS > + * > + * This driver requires: > + * > + * Arbitrary Based Buffers: > + * Docsis - > + * > + */ > + { > + .name = "ITFS", > + .start = 0x00000000, > + /* 815,104 bytes each for 2 ITFS partitions. */ > + .end = 0x0018DFFF, > + .flags = IORESOURCE_MEM, > + }, > + /* > + * > + * AVFS > + * > + * This driver requires: > + * > + * Arbitrary Based Buffers: > + * Docsis - > + * > + */ > + { > + .name = "AvfsDmaMem", > + .start = 0x00000000, > + /* (945K * 8) = (128K * 3) 5 playbacks / 3 server */ > + .end = 0x007c2000 - 1, > + .flags = IORESOURCE_MEM, > + }, > + { > + .name = "AvfsFileSys", > + .start = 0x00000000, > + .end = 0x00001000 - 1, /* 4K */ > + .flags = IORESOURCE_MEM, > + }, > + /* > + * > + * PMEM > + * > + * This driver requires: > + * > + * Arbitrary Based Buffers: > + * Persistent memory for diagnostics. > + * > + */ > + { > + .name = "DiagPersistentMemory", > + .start = 0x00000000, > + .end = 0x10000 - 1, > + .flags = IORESOURCE_MEM, > + }, > + /* > + * > + * Smartcard > + * > + * This driver requires: > + * > + * Arbitrary Based Buffers: > + * Read and write buffers for Internal/External cards > + * > + */ > + { > + .name = "SmartCardInfo", > + .start = 0x00000000, > + .end = 0x2800 - 1, > + .flags = IORESOURCE_MEM, > + }, > + /* > + * Add other resources here > + */ > + /* > + * End of Resource marker > + * > + */ Some comments just don't deserve to exist ... > + { > + .flags = 0, No need to explicitly initialize a member of the end marker; just {} will do fine. > + }, > +}; > + > +/* > + * NON_DVR_CAPABLE ZEUS RESOURCES > + */ > +struct resource non_dvr_zeus_resources[] __initdata = > +{ > + /* > + * VIDEO1 / LX1 > + */ > + { > + .name = "ST231aImage", /* Delta-Mu 1 image and ram */ > + .start = 0x20000000, > + .end = 0x201FFFFF, /* 2MiB */ > + .flags = IORESOURCE_IO, > + }, > + { > + .name = "ST231aMonitor", /* 8KiB block ST231a monitor */ > + .start = 0x20200000, > + .end = 0x20201FFF, > + .flags = IORESOURCE_IO, > + }, > + { > + .name = "MediaMemory1", > + .start = 0x20202000, > + .end = 0x21FFFFFF, /*~29.9MiB (32MiB - (2MiB + 8KiB)) */ > + .flags = IORESOURCE_IO, > + }, > + /* > + * Sysaudio Driver > + */ > + { > + .name = "DSP_Image_Buff", > + .start = 0x00000000, > + .end = 0x000FFFFF, > + .flags = IORESOURCE_MEM, > + }, > + { > + .name = "ADSC_CPU_PCM_Buff", > + .start = 0x00000000, > + .end = 0x00009FFF, > + .flags = IORESOURCE_MEM, > + }, > + { > + .name = "ADSC_AUX_Buff", > + .start = 0x00000000, > + .end = 0x00003FFF, > + .flags = IORESOURCE_MEM, > + }, > + { > + .name = "ADSC_Main_Buff", > + .start = 0x00000000, > + .end = 0x00003FFF, > + .flags = IORESOURCE_MEM, > + }, > + /* > + * STAVEM driver/STAPI > + */ > + { > + .name = "AVMEMPartition0", > + .start = 0x00000000, > + .end = 0x00600000 - 1, /* 6 MB total */ > + .flags = IORESOURCE_MEM, > + }, > + /* > + * DOCSIS Subsystem > + */ > + { > + .name = "Docsis", > + .start = 0x40100000, > + .end = 0x407fffff, > + .flags = IORESOURCE_MEM, > + }, > + /* > + * GHW HAL Driver > + */ > + { > + .name = "GraphicsHeap", > + .start = 0x46900000, > + .end = 0x47700000 - 1, /* 14 MB total */ > + .flags = IORESOURCE_MEM, > + }, > + /* > + * multi com buffer area > + */ > + { > + .name = "MulticomSHM", > + .start = 0x47900000, > + .end = 0x47920000 - 1, > + .flags = IORESOURCE_MEM, > + }, > + /* > + * DMA Ring buffer > + */ > + { > + .name = "BMM_Buffer", > + .start = 0x00000000, > + .end = 0x00280000 - 1, > + .flags = IORESOURCE_MEM, > + }, > + /* > + * Display bins buffer for unit0 > + */ > + { > + .name = "DisplayBins0", > + .start = 0x00000000, > + .end = 0x00000FFF, /* 4 KB total */ > + .flags = IORESOURCE_MEM, > + }, > + /* > + * > + * AVFS: player HAL memory > + * > + * > + */ > + { > + .name = "AvfsDmaMem", > + .start = 0x00000000, > + .end = 0x002c4c00 - 1, /* 945K * 3 for playback */ > + .flags = IORESOURCE_MEM, > + }, > + /* > + * PMEM > + */ > + { > + .name = "DiagPersistentMemory", > + .start = 0x00000000, > + .end = 0x10000 - 1, > + .flags = IORESOURCE_MEM, > + }, > + /* > + * Smartcard > + */ > + { > + .name = "SmartCardInfo", > + .start = 0x00000000, > + .end = 0x2800 - 1, > + .flags = IORESOURCE_MEM, > + }, > + /* > + * NAND Flash > + */ > + { > + .name = "NandFlash", > + .start = NAND_FLASH_BASE, > + .end = NAND_FLASH_BASE + 0x400 - 1, > + .flags = IORESOURCE_IO, > + }, > + /* > + * Add other resources here > + * > + * End of Resource marker > + */ Some comments just don't deserve to exist ... > + { > + .flags = 0, No need to explicitly initialize a member of the end marker; just {} will do fine. > + }, > +}; > diff --git a/arch/mips/powertv/cevt-powertv.c b/arch/mips/powertv/cevt-powertv.c > new file mode 100644 > index 0000000..ef7768d > --- /dev/null > +++ b/arch/mips/powertv/cevt-powertv.c > @@ -0,0 +1,165 @@ > +/* > + * Copyright (C) 2008 Scientific-Atlanta, Inc. > + * > + * This program is free software; you can redistribute it and/or > + * modify it under the terms of the GNU General Public License > + * as published by the Free Software Foundation; either version 2 > + * of the License, or (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, write to the Free Software > + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. > + */ > +/* > + * The file comes from kernel/cevt-r4k.c > + */ Do you really need this file which to a significant degree is a clone of cevt-r4k.c? Maybe you can get away with a wrapper around cevt-r4k.c. If not, please move this file to arch/mips/kernel/ > +#include > +#include > +#include > +#include > + > +#include > +#include /* Not included in linux/time.h */ > + > +#include > +#include "powertv-clock.h" > + > +static int mips_next_event(unsigned long delta, > + struct clock_event_device *evt) > +{ > + unsigned int cnt; > + int res; > + > + cnt = read_c0_count(); > + cnt += delta; > + write_c0_compare(cnt); > + res = ((int)(read_c0_count() - cnt) > 0) ? -ETIME : 0; > + return res; > +} > + > +static void mips_set_mode(enum clock_event_mode mode, > + struct clock_event_device *evt) > +{ > + /* Nothing to do ... */ > +} > + > +static DEFINE_PER_CPU(struct clock_event_device, mips_clockevent_device); > +static int cp0_timer_irq_installed; > + > +/* > + * Timer ack for an R4k-compatible timer of a known frequency. > + */ > +static void c0_timer_ack(void) > +{ > + write_c0_compare(read_c0_compare()); > +} > + > +#ifndef CONFIG_SEPARATE_PCI_TI > +/* > + * Possibly handle a performance counter interrupt. > + * Return true if the timer interrupt should not be checked > + */ > +static inline int handle_perf_irq(int r2) > +{ > + /* > + * The performance counter overflow interrupt may be shared with the > + * timer interrupt (cp0_perfcount_irq < 0). If it is and a > + * performance counter has overflowed (perf_irq() == IRQ_HANDLED) > + * and we can't reliably determine if a counter interrupt has also > + * happened (!r2) then don't check for a timer interrupt. > + */ > + return (cp0_perfcount_irq < 0) && > + perf_irq() == IRQ_HANDLED && > + !r2; > +} > +#endif > + > +static irqreturn_t c0_compare_interrupt(int irq, void *dev_id) > +{ > + const int r2 = cpu_has_mips_r2; > + struct clock_event_device *cd; > + int cpu = smp_processor_id(); > + > +#ifndef CONFIG_SEPARATE_PCI_TI > + /* > + * Suckage alert: > + * Before R2 of the architecture there was no way to see if a > + * performance counter interrupt was pending, so we have to run > + * the performance counter interrupt handler anyway. > + */ > + if (handle_perf_irq(r2)) > + return IRQ_HANDLED; > +#endif > + > + /* > + * The same applies to performance counter interrupts. But with the > + * above we now know that the reason we got here must be a timer > + * interrupt. Being the paranoiacs we are we check anyway. > + */ > + if (!r2 || (read_c0_cause() & (1 << 30))) { > + c0_timer_ack(); > + cd = &per_cpu(mips_clockevent_device, cpu); > + cd->event_handler(cd); > + } > + > + return IRQ_HANDLED; > +} > + > +static struct irqaction c0_compare_irqaction = { > + .handler = c0_compare_interrupt, > + .flags = IRQF_DISABLED | IRQF_PERCPU, > + .name = "timer", > +}; > + > +static void mips_event_handler(struct clock_event_device *dev) > +{ > +} > + > +int __cpuinit powertv_clockevent_init(void) > +{ > + uint64_t mips_freq = mips_hpt_frequency; > + unsigned int cpu = smp_processor_id(); > + struct clock_event_device *cd; > + unsigned int irq; > + > + if (!cpu_has_counter || !mips_hpt_frequency) > + return -ENXIO; > + > + > + irq = irq_mips_timer; > + > + cd = &per_cpu(mips_clockevent_device, cpu); > + > + cd->name = "MIPS"; > + cd->features = CLOCK_EVT_FEAT_ONESHOT; > + > + /* Calculate the min / max delta */ > + cd->mult = div_sc((unsigned long) mips_freq, NSEC_PER_SEC, 32); > + cd->shift = 32; > + cd->max_delta_ns = clockevent_delta2ns(0x7fffffff, cd); > + cd->min_delta_ns = clockevent_delta2ns(0x300, cd); > + > + cd->rating = 300; > + cd->irq = irq; > + cd->cpumask = get_cpu_mask(cpu); > + > + cd->set_next_event = mips_next_event; > + cd->set_mode = mips_set_mode; > + cd->event_handler = mips_event_handler; > + > + clockevents_register_device(cd); > + > + if (cp0_timer_irq_installed) > + return 0; > + > + cp0_timer_irq_installed = 1; > + > + setup_irq(irq, &c0_compare_irqaction); > + > + return 0; > +} > diff --git a/arch/mips/powertv/cmdline.c b/arch/mips/powertv/cmdline.c > new file mode 100644 > index 0000000..98d73cb > --- /dev/null > +++ b/arch/mips/powertv/cmdline.c > @@ -0,0 +1,52 @@ > +/* > + * Carsten Langgaard, carstenl@mips.com > + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. > + * Portions copyright (C) 2009 Cisco Systems, Inc. > + * > + * This program is free software; you can distribute it and/or modify it > + * under the terms of the GNU General Public License (Version 2) as > + * published by the Free Software Foundation. > + * > + * This program is distributed in the hope it will be useful, but WITHOUT > + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or > + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License > + * for more details. > + * > + * You should have received a copy of the GNU General Public License along > + * with this program; if not, write to the Free Software Foundation, Inc., > + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. > + * > + * Kernel command line creation using the prom monitor (YAMON) argc/argv. > + */ > +#include > +#include > + > +#include > + > +#include "init.h" > + > +/* > + * YAMON (32-bit PROM) pass arguments and environment as 32-bit pointer. > + * This macro take care of sign extension. > + */ > +#define prom_argv(index) ((char *)(long)_prom_argv[(index)]) > + > +char * __init prom_getcmdline(void) > +{ > + return &(arcs_cmdline[0]); > +} > + > +void __init prom_init_cmdline(void) > +{ > + int len; > + > + if (prom_argc != 1) > + return; > + > + len = strlen(arcs_cmdline); > + > + arcs_cmdline[len] = ' '; > + > + strlcpy(arcs_cmdline + len + 1, (char *)_prom_argv, > + COMMAND_LINE_SIZE - len - 1); > +} > diff --git a/arch/mips/powertv/csrc-powertv.c b/arch/mips/powertv/csrc-powertv.c > new file mode 100644 > index 0000000..a27c16c > --- /dev/null > +++ b/arch/mips/powertv/csrc-powertv.c > @@ -0,0 +1,180 @@ > +/* > + * Copyright (C) 2008 Scientific-Atlanta, Inc. > + * > + * This program is free software; you can redistribute it and/or > + * modify it under the terms of the GNU General Public License > + * as published by the Free Software Foundation; either version 2 > + * of the License, or (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, write to the Free Software > + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. > + */ > +/* > + * The file comes from kernel/csrc-r4k.c So why not simply using csrc-r4k.c? Set mips_hpt_frequency before init_r4k_clocksource() is initialized and voila. If for some reason you think you really need your own clocksource then please keep csrc-powertv.c with all the other clocksource files in arch/mips/kernel. By now we have amassed enough clock code to justify a separate time even. > + */ > +#include > +#include > + > +#include /* Not included in linux/time.h */ Which makes checkpatch.pl emit bogus warnings. I guess I should rename asm/time.h and a few other headers affected by this issue for clarity and fixup all the references. > + > +#include > +#include "powertv-clock.h" > + > +/* MIPS PLL Register Definitions */ > +#define PLL_GET_M(x) (((x) >> 8) & 0x000000FF) > +#define PLL_GET_N(x) (((x) >> 16) & 0x000000FF) > +#define PLL_GET_P(x) (((x) >> 24) & 0x00000007) > + > +/* > + * returns: Clock frequency in kHz > + */ > +unsigned int __init mips_get_pll_freq(void) > +{ > + unsigned int pll_reg, m, n, p; > + unsigned int fin = 54000; /* Base frequency in kHz */ > + unsigned int fout; > + > + /* Read PLL register setting */ > + pll_reg = asic_read(mips_pll_setup); > + m = PLL_GET_M(pll_reg); > + n = PLL_GET_N(pll_reg); > + p = PLL_GET_P(pll_reg); > + pr_info("MIPS PLL Register:0x%x M=%d N=%d P=%d\n", pll_reg, m, n, p); > + > + /* Calculate clock frequency = (2 * N * 54MHz) / (M * (2**P)) */ > + fout = ((2 * n * fin) / (m * (0x01 << p))); > + > + pr_info("MIPS Clock Freq=%d kHz\n", fout); > + > + return fout; > +} > + > +static cycle_t c0_hpt_read(struct clocksource *cs) > +{ > + return read_c0_count(); > +} > + > +static struct clocksource clocksource_mips = { > + .name = "powertv-counter", > + .read = c0_hpt_read, > + .mask = CLOCKSOURCE_MASK(32), > + .flags = CLOCK_SOURCE_IS_CONTINUOUS, > +}; > + > +static void __init powertv_c0_hpt_clocksource_init(void) > +{ > + unsigned int pll_freq = mips_get_pll_freq(); > + > + pr_info("CPU frequency %d.%02d MHz\n", pll_freq / 1000, > + (pll_freq % 1000) * 100 / 1000); > + > + mips_hpt_frequency = pll_freq / 2 * 1000; > + > + clocksource_mips.rating = 200 + mips_hpt_frequency / 10000000; > + > + clocksource_set_clock(&clocksource_mips, mips_hpt_frequency); > + > + clocksource_register(&clocksource_mips); > +} > + > +/** > + * struct tim_c - free running counter > + * @hi: High 16 bits of the counter > + * @lo: Low 32 bits of the counter > + * > + * Lays out the structure of the free running counter in memory. This counter > + * increments at a rate of 27 MHz/8 on all platforms. > + */ > +struct tim_c { > + unsigned int hi; > + unsigned int lo; > +}; > + > +static struct tim_c *tim_c; > + > +static cycle_t tim_c_read(struct clocksource *cs) > +{ > + unsigned int hi; > + unsigned int next_hi; > + unsigned int lo; > + > + hi = readl(&tim_c->hi); > + > + for (;;) { > + lo = readl(&tim_c->lo); > + next_hi = readl(&tim_c->hi); > + if (next_hi == hi) > + break; > + hi = next_hi; > + } > + > +pr_crit("%s: read %llx\n", __func__, ((u64) hi << 32) | lo); Debugging crap in a function that might be called frequently or well, is clocksource_tim_c being used at all? > + return ((u64) hi << 32) | lo; > +} > + > +#define TIM_C_SIZE 48 /* # bits in the timer */ > + > +static struct clocksource clocksource_tim_c = { > + .name = "powertv-tim_c", > + .read = tim_c_read, > + .mask = CLOCKSOURCE_MASK(TIM_C_SIZE), > + .flags = CLOCK_SOURCE_IS_CONTINUOUS, > +}; > + > +/** > + * powertv_tim_c_clocksource_init - set up a clock source for the TIM_C clock > + * > + * The hard part here is coming up with a constant k and shift s such that > + * the 48-bit TIM_C value multiplied by k doesn't overflow and that value, > + * when shifted right by s, yields the corresponding number of nanoseconds. > + * We know that TIM_C counts at 27 MHz/8, so each cycle corresponds to > + * 1 / (27,000,000/8) seconds. Multiply that by a billion and you get the > + * number of nanoseconds. Since the TIM_C value has 48 bits and the math is > + * done in 64 bits, avoiding an overflow means that k must be less than > + * 64 - 48 = 16 bits. > + */ > +static void __init powertv_tim_c_clocksource_init(void) > +{ > + int prescale; > + unsigned long dividend; > + unsigned long k; > + int s; > + const int max_k_bits = (64 - 48) - 1; > + const unsigned long billion = 1000000000; > + const unsigned long counts_per_second = 27000000 / 8; > + > + prescale = BITS_PER_LONG - ilog2(billion) - 1; > + dividend = billion << prescale; > + k = dividend / counts_per_second; > + s = ilog2(k) - max_k_bits; > + > + if (s < 0) > + s = prescale; > + > + else { > + k >>= s; > + s += prescale; > + } > + > + clocksource_tim_c.mult = k; > + clocksource_tim_c.shift = s; > + clocksource_tim_c.rating = 200; > + > + clocksource_register(&clocksource_tim_c); > + tim_c = (struct tim_c *) asic_reg_addr(tim_ch); > +} > + > +/** > + powertv_clocksource_init - initialize all clocksources > + */ > +void __init powertv_clocksource_init(void) > +{ > + powertv_c0_hpt_clocksource_init(); > + powertv_tim_c_clocksource_init(); > +} > diff --git a/arch/mips/powertv/init.c b/arch/mips/powertv/init.c > new file mode 100644 > index 0000000..5f4e4c3 > --- /dev/null > +++ b/arch/mips/powertv/init.c > @@ -0,0 +1,128 @@ > +/* > + * Copyright (C) 1999, 2000, 2004, 2005 MIPS Technologies, Inc. > + * All rights reserved. > + * Authors: Carsten Langgaard > + * Maciej W. Rozycki > + * Portions copyright (C) 2009 Cisco Systems, Inc. > + * > + * This program is free software; you can distribute it and/or modify it > + * under the terms of the GNU General Public License (Version 2) as > + * published by the Free Software Foundation. > + * > + * This program is distributed in the hope it will be useful, but WITHOUT > + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or > + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License > + * for more details. > + * > + * You should have received a copy of the GNU General Public License along > + * with this program; if not, write to the Free Software Foundation, Inc., > + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. > + * > + * PROM library initialisation code. > + */ > +#include > +#include > +#include > + > +#include > +#include > +#include > +#include > +#include > + > +#include > +#include > +#include > + > +#include "init.h" > + > +int prom_argc; > +int *_prom_argv, *_prom_envp; > +unsigned long _prom_memsize; > + > +/* > + * YAMON (32-bit PROM) pass arguments and environment as 32-bit pointer. > + * This macro take care of sign extension, if running in 64-bit mode. > + */ > +#define prom_envp(index) ((char *)(long)_prom_envp[(index)]) > + > +char *prom_getenv(char *envname) > +{ > + char *result = NULL; > + > + if (_prom_envp != NULL) { > + /* > + * Return a pointer to the given environment variable. > + * In 64-bit mode: we're using 64-bit pointers, but all pointers > + * in the PROM structures are only 32-bit, so we need some > + * workarounds, if we are running in 64-bit mode. > + */ > + int i, index = 0; > + > + i = strlen(envname); > + > + while (prom_envp(index)) { > + if (strncmp(envname, prom_envp(index), i) == 0) { > + result = prom_envp(index + 1); > + break; > + } > + index += 2; > + } > + } > + > + return result; > +} > + > +/* TODO: Verify on linux-mips mailing list that the following two */ > +/* functions are correct */ > +/* TODO: Copy NMI and EJTAG exception vectors to memory from the */ > +/* BootROM exception vectors. Flush their cache entries. test it. */ > + > +static void __init mips_nmi_setup(void) > +{ > + void *base; > +#if defined(CONFIG_CPU_MIPS32_R1) > + base = cpu_has_veic ? > + (void *)(CAC_BASE + 0xa80) : > + (void *)(CAC_BASE + 0x380); > +#elif defined(CONFIG_CPU_MIPS32_R2) > + base = (void *)0xbfc00000; > +#else > +#error NMI exception handler address not defined > +#endif > +} > + > +static void __init mips_ejtag_setup(void) > +{ > + void *base; > + > +#if defined(CONFIG_CPU_MIPS32_R1) > + base = cpu_has_veic ? > + (void *)(CAC_BASE + 0xa00) : > + (void *)(CAC_BASE + 0x300); > +#elif defined(CONFIG_CPU_MIPS32_R2) > + base = (void *)0xbfc00480; > +#else > +#error EJTAG exception handler address not defined > +#endif > +} > + > +void __init prom_init(void) > +{ > + prom_argc = fw_arg0; > + _prom_argv = (int *) fw_arg1; > + _prom_envp = (int *) fw_arg2; > + _prom_memsize = (unsigned long) fw_arg3; > + > + board_nmi_handler_setup = mips_nmi_setup; > + board_ejtag_handler_setup = mips_ejtag_setup; > + > + pr_info("\nLINUX started...\n"); > + prom_init_cmdline(); > + configure_platform(); > + prom_meminit(); > + > +#ifndef CONFIG_BOOTLOADER_DRIVER > + pr_info("\nBootloader driver isn't loaded...\n"); > +#endif > +} > diff --git a/arch/mips/powertv/init.h b/arch/mips/powertv/init.h > new file mode 100644 > index 0000000..332cfed > --- /dev/null > +++ b/arch/mips/powertv/init.h > @@ -0,0 +1,30 @@ > +/* > + * init.h > + * > + * Definitions from powertv init.c file > + * > + * Copyright (C) 2009 Cisco Systems, Inc. > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, write to the Free Software > + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA > + * > + * Author: David VomLehn > + */ > + > +#ifndef _POWERTV_INIT_H > +#define _POWERTV_INIT_H > +extern int prom_argc; > +extern int *_prom_argv; > +extern unsigned long _prom_memsize; > +#endif > diff --git a/arch/mips/powertv/memory.c b/arch/mips/powertv/memory.c > new file mode 100644 > index 0000000..4ef689c > --- /dev/null > +++ b/arch/mips/powertv/memory.c > @@ -0,0 +1,184 @@ > +/* > + * Carsten Langgaard, carstenl@mips.com > + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. > + * Portions copyright (C) 2009 Cisco Systems, Inc. > + * > + * This program is free software; you can distribute it and/or modify it > + * under the terms of the GNU General Public License (Version 2) as > + * published by the Free Software Foundation. > + * > + * This program is distributed in the hope it will be useful, but WITHOUT > + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or > + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License > + * for more details. > + * > + * You should have received a copy of the GNU General Public License along > + * with this program; if not, write to the Free Software Foundation, Inc., > + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. > + * > + * Apparently originally from arch/mips/malta-memory.c. Modified to work > + * with the PowerTV bootloader. > + */ > +#include > +#include > +#include > +#include > +#include > + > +#include > +#include > +#include > + > +#include > + > +#include "init.h" > + > +/* Memory constants */ > +#define KIBIBYTE(n) ((n) * 1024) /* Number of kibibytes */ > +#define MEBIBYTE(n) ((n) * KIBIBYTE(1024)) /* Number of mebibytes */ > +#define DEFAULT_MEMSIZE MEBIBYTE(256) /* If no memsize provided */ > +#define LOW_MEM_MAX MEBIBYTE(252) /* Max usable low mem */ > +#define RES_BOOTLDR_MEMSIZE MEBIBYTE(1) /* Memory reserved for bldr */ > +#define BOOT_MEM_SIZE KIBIBYTE(256) /* Memory reserved for bldr */ > +#define PHYS_MEM_START 0x10000000 /* Start of physical memory */ > + > +unsigned long ptv_memsize; > + > +void __init prom_meminit(void) > +{ > + char *memsize_str; > + unsigned long memsize = 0; > + unsigned int physend; > + char cmdline[CL_SIZE], *ptr; > + int low_mem; > + int high_mem; > + > + /* Check the command line first for a memsize directive */ > + strcpy(cmdline, arcs_cmdline); > + ptr = strstr(cmdline, "memsize="); > + if (ptr && (ptr != cmdline) && (*(ptr - 1) != ' ')) > + ptr = strstr(ptr, " memsize="); > + > + if (ptr) { > + memsize = memparse(ptr + 8, &ptr); > + } else { > + /* otherwise look in the environment */ > + memsize_str = prom_getenv("memsize"); > + > + if (memsize_str != NULL) { > + pr_info("prom memsize = %s\n", memsize_str); > + memsize = simple_strtol(memsize_str, NULL, 0); > + } > + > + if (memsize == 0) { > + if (_prom_memsize != 0) { > + memsize = _prom_memsize; > + pr_info("_prom_memsize = 0x%lx\n", memsize); > + /* add in memory that the bootloader doesn't > + * report */ > + memsize += BOOT_MEM_SIZE; > + } else { > + memsize = DEFAULT_MEMSIZE; > + pr_info("Memsize not passed by bootloader, " > + "defaulting to 0x%lx\n", memsize); > + } > + } > + } > + > + /* Store memsize for diagnostic purposes */ > + ptv_memsize = memsize; > + > + physend = PFN_ALIGN(&_end) - 0x80000000; > + if (memsize > LOW_MEM_MAX) { > + low_mem = LOW_MEM_MAX; > + high_mem = memsize - low_mem; > + } else { > + low_mem = memsize; > + high_mem = 0; > + } > + > +/* > + * TODO: We will use the hard code for memory configuration until > + * the bootloader releases their device tree to us. > + */ > + /* > + * Add the memory reserved for use by the bootloader to the > + * memory map. > + */ > + add_memory_region(PHYS_MEM_START, RES_BOOTLDR_MEMSIZE, > + BOOT_MEM_RESERVED); > +#ifdef CONFIG_HIGHMEM_256_128 > + /* > + * Add memory in low for general use by the kernel and its friends > + * (like drivers, applications, etc). > + */ > + add_memory_region(PHYS_MEM_START + RES_BOOTLDR_MEMSIZE, > + LOW_MEM_MAX - RES_BOOTLDR_MEMSIZE, BOOT_MEM_RAM); > + /* > + * Add the memory reserved for reset vector. > + */ > + add_memory_region(0x1fc00000, MEBIBYTE(4), BOOT_MEM_RESERVED); > + /* > + * Add the memory reserved. > + */ > + add_memory_region(0x20000000, MEBIBYTE(1024 + 75), BOOT_MEM_RESERVED); > + /* > + * Add memory in high for general use by the kernel and its friends > + * (like drivers, applications, etc). > + * > + * 75MB is reserved for devices which are using the memory in high. > + */ > + add_memory_region(0x60000000 + MEBIBYTE(75), MEBIBYTE(128 - 75), > + BOOT_MEM_RAM); > +#elif defined CONFIG_HIGHMEM_128_128 > + /* > + * Add memory in low for general use by the kernel and its friends > + * (like drivers, applications, etc). > + */ > + add_memory_region(PHYS_MEM_START + RES_BOOTLDR_MEMSIZE, > + MEBIBYTE(128) - RES_BOOTLDR_MEMSIZE, BOOT_MEM_RAM); > + /* > + * Add the memory reserved. > + */ > + add_memory_region(PHYS_MEM_START + MEBIBYTE(128), > + MEBIBYTE(128 + 1024 + 75), BOOT_MEM_RESERVED); > + /* > + * Add memory in high for general use by the kernel and its friends > + * (like drivers, applications, etc). > + * > + * 75MB is reserved for devices which are using the memory in high. > + */ > + add_memory_region(0x60000000 + MEBIBYTE(75), MEBIBYTE(128 - 75), > + BOOT_MEM_RAM); > +#else > + /* Add low memory regions for either: > + * - no-highmemory configuration case -OR- > + * - highmemory "HIGHMEM_LOWBANK_ONLY" case > + */ > + /* > + * Add memory for general use by the kernel and its friends > + * (like drivers, applications, etc). > + */ > + add_memory_region(PHYS_MEM_START + RES_BOOTLDR_MEMSIZE, > + low_mem - RES_BOOTLDR_MEMSIZE, BOOT_MEM_RAM); > + /* > + * Add the memory reserved for reset vector. > + */ > + add_memory_region(0x1fc00000, MEBIBYTE(4), BOOT_MEM_RESERVED); > +#endif > +} > + > +void __init prom_free_prom_memory(void) > +{ > + unsigned long addr; > + int i; > + > + for (i = 0; i < boot_mem_map.nr_map; i++) { > + if (boot_mem_map.map[i].type != BOOT_MEM_ROM_DATA) > + continue; > + > + addr = boot_mem_map.map[i].addr; > + free_init_pages("prom memory", > + addr, addr + boot_mem_map.map[i].size); > + } > +} > diff --git a/arch/mips/powertv/pci/Makefile b/arch/mips/powertv/pci/Makefile > new file mode 100644 > index 0000000..9249164 > --- /dev/null > +++ b/arch/mips/powertv/pci/Makefile > @@ -0,0 +1,28 @@ > +# ***************************************************************************** > +# Make file for PowerTV PCI driver > +# > +# Copyright (C) 2009 Scientific-Atlanta, Inc. > +# > +# This program is free software; you can redistribute it and/or modify > +# it under the terms of the GNU General Public License as published by > +# the Free Software Foundation; either version 2 of the License, or > +# (at your option) any later version. > +# > +# This program is distributed in the hope that it will be useful, > +# but WITHOUT ANY WARRANTY; without even the implied warranty of > +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > +# GNU General Public License for more details. > +# > +# You should have received a copy of the GNU General Public License > +# along with this program; if not, write to the Free Software > +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA > +# > +# ***************************************************************************** > + > +EXTRA_CFLAGS += -Wall -Werror > + > +obj-y := > + > +obj-$(CONFIG_PCI) += fixup-powertv.o > + > + > diff --git a/arch/mips/powertv/pci/fixup-powertv.c b/arch/mips/powertv/pci/fixup-powertv.c > new file mode 100644 > index 0000000..726bc2e > --- /dev/null > +++ b/arch/mips/powertv/pci/fixup-powertv.c > @@ -0,0 +1,36 @@ > +#include > +#include > +#include > +#include "powertv-pci.h" > + > +int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) > +{ > + return asic_pcie_map_irq(dev, slot, pin); > +} > + > +/* Do platform specific device initialization at pci_enable_device() time */ > +int pcibios_plat_dev_init(struct pci_dev *dev) > +{ > + return 0; > +} > + > +/* > + * asic_pcie_map_irq > + * > + * Parameters: > + * *dev - pointer to a pci_dev structure (not used) > + * slot - slot number (not used) > + * pin - pin number (not used) > + * > + * Return Value: > + * Returns: IRQ number (always the PCI Express IRQ number) > + * > + * Description: > + * asic_pcie_map_irq will return the IRQ number of the PCI Express interrupt. > + * > + */ > +int asic_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) > +{ > + return irq_pciexp; > +} > +EXPORT_SYMBOL(asic_pcie_map_irq); I don't see a module user of asic_pcie_map_irq()? > diff --git a/arch/mips/powertv/pci/powertv-pci.h b/arch/mips/powertv/pci/powertv-pci.h > new file mode 100644 > index 0000000..1b5886b > --- /dev/null > +++ b/arch/mips/powertv/pci/powertv-pci.h > @@ -0,0 +1,31 @@ > +/* > + * powertv-pci.c > + * > + * Copyright (C) 2009 Cisco Systems, Inc. > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, write to the Free Software > + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA > + */ > +/* > + * Local definitions for the powertv PCI code > + */ > + > +#ifndef _POWERTV_PCI_POWERTV_PCI_H_ > +#define _POWERTV_PCI_POWERTV_PCI_H_ > +extern int asic_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin); > +extern int asic_pcie_init(void); > +extern int asic_pcie_init(void); > + > +extern int log_level; > +#endif > diff --git a/arch/mips/powertv/powertv-clock.h b/arch/mips/powertv/powertv-clock.h > new file mode 100644 > index 0000000..5c1f093 > --- /dev/null > +++ b/arch/mips/powertv/powertv-clock.h > @@ -0,0 +1,30 @@ > +/* > + * powertv-clock.h > + * > + * Definitions for clocks > + * > + * Copyright (C) 2009 Cisco Systems, Inc. > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, write to the Free Software > + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA > + * > + * Author: David VomLehn > + */ > + > +#ifndef _POWERTV_POWERTV_CLOCK_H > +#define _POWERTV_POWERTV_CLOCK_H > +extern int powertv_clockevent_init(void); > +extern void powertv_clocksource_init(void); > +extern unsigned int mips_get_pll_freq(void); > +#endif > diff --git a/arch/mips/powertv/powertv_setup.c b/arch/mips/powertv/powertv_setup.c > new file mode 100644 > index 0000000..bd8ebf1 > --- /dev/null > +++ b/arch/mips/powertv/powertv_setup.c > @@ -0,0 +1,351 @@ > +/* > + * Carsten Langgaard, carstenl@mips.com > + * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. > + * Portions copyright (C) 2009 Cisco Systems, Inc. > + * > + * This program is free software; you can distribute it and/or modify it > + * under the terms of the GNU General Public License (Version 2) as > + * published by the Free Software Foundation. > + * > + * This program is distributed in the hope it will be useful, but WITHOUT > + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or > + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License > + * for more details. > + * > + * You should have received a copy of the GNU General Public License along > + * with this program; if not, write to the Free Software Foundation, Inc., > + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. > + */ > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include "reset.h" > + > +#define VAL(n) STR(n) > + > +/* > + * Macros for loading addresses and storing registers: > + * PTR_LA Load the address into a register > + * LONG_S Store the full width of the given register. > + * LONG_L Load the full width of the given register > + * PTR_ADDIU Add a constant value to a register used as a pointer > + * REG_SIZE Number of 8-bit bytes in a full width register > + */ > +#ifdef CONFIG_64BIT > +#warning TODO: 64-bit code needs to be verified > +#define PTR_LA "dla " > +#define LONG_S "sd " > +#define LONG_L "ld " > +#define PTR_ADDIU "daddiu " > +#define REG_SIZE "8" /* In bytes */ > +#endif > + > +#ifdef CONFIG_32BIT > +#define PTR_LA "la " > +#define LONG_S "sw " > +#define LONG_L "lw " > +#define PTR_ADDIU "addiu " > +#define REG_SIZE "4" /* In bytes */ > +#endif > + > +static struct pt_regs die_regs; > +static bool have_die_regs; > + > +static void register_panic_notifier(void); > +static int panic_handler(struct notifier_block *notifier_block, > + unsigned long event, void *cause_string); If you reorder the functions in this file you can get away without prototypes. > + > +const char *get_system_type(void) > +{ > + return "PowerTV"; > +} > + > +void __init plat_mem_setup(void) > +{ > + panic_on_oops = 1; > + register_panic_notifier(); > + > +#if 0 > + mips_pcibios_init(); > +#endif Dead code to be deleted? > + mips_reboot_setup(); > +} > + > +/* > + * Install a panic notifier for platform-specific diagnostics > + */ > +static void register_panic_notifier() > +{ > + static struct notifier_block panic_notifier = { > + .notifier_call = panic_handler, > + .next = NULL, No need to initialize .next. > + .priority = INT_MAX > + }; > + atomic_notifier_chain_register(&panic_notifier_list, &panic_notifier); > +} > + > +static int panic_handler(struct notifier_block *notifier_block, > + unsigned long event, void *cause_string) > +{ > + struct pt_regs my_regs; > + > + /* Save all of the registers */ > + { > + unsigned long at, v0, v1; /* Must be on the stack */ > + > + /* Start by saving $at and v0 on the stack. We use $at > + * ourselves, but it looks like the compiler may use v0 or v1 > + * to load the address of the pt_regs structure. We'll come > + * back later to store the registers in the pt_regs > + * structure. */ > + __asm__ __volatile__ ( > + ".set noat\n" > + LONG_S "$at, %[at]\n" > + LONG_S "$2, %[v0]\n" > + LONG_S "$3, %[v1]\n" > + : > + [at] "=m" (at), > + [v0] "=m" (v0), > + [v1] "=m" (v1) > + : > + : "at" > + ); > + > + __asm__ __volatile__ ( > + ".set noat\n" > + "move $at, %[pt_regs]\n" > + > + /* Argument registers */ > + LONG_S "$4, " VAL(PT_R4) "($at)\n" > + LONG_S "$5, " VAL(PT_R5) "($at)\n" > + LONG_S "$6, " VAL(PT_R6) "($at)\n" > + LONG_S "$7, " VAL(PT_R7) "($at)\n" > + > + /* Temporary regs */ > + LONG_S "$8, " VAL(PT_R8) "($at)\n" > + LONG_S "$9, " VAL(PT_R9) "($at)\n" > + LONG_S "$10, " VAL(PT_R10) "($at)\n" > + LONG_S "$11, " VAL(PT_R11) "($at)\n" > + LONG_S "$12, " VAL(PT_R12) "($at)\n" > + LONG_S "$13, " VAL(PT_R13) "($at)\n" > + LONG_S "$14, " VAL(PT_R14) "($at)\n" > + LONG_S "$15, " VAL(PT_R15) "($at)\n" > + > + /* "Saved" registers */ > + LONG_S "$16, " VAL(PT_R16) "($at)\n" > + LONG_S "$17, " VAL(PT_R17) "($at)\n" > + LONG_S "$18, " VAL(PT_R18) "($at)\n" > + LONG_S "$19, " VAL(PT_R19) "($at)\n" > + LONG_S "$20, " VAL(PT_R20) "($at)\n" > + LONG_S "$21, " VAL(PT_R21) "($at)\n" > + LONG_S "$22, " VAL(PT_R22) "($at)\n" > + LONG_S "$23, " VAL(PT_R23) "($at)\n" > + > + /* Add'l temp regs */ > + LONG_S "$24, " VAL(PT_R24) "($at)\n" > + LONG_S "$25, " VAL(PT_R25) "($at)\n" > + > + /* Kernel temp regs */ > + LONG_S "$26, " VAL(PT_R26) "($at)\n" > + LONG_S "$27, " VAL(PT_R27) "($at)\n" > + > + /* Global pointer, stack pointer, frame pointer and > + * return address */ > + LONG_S "$gp, " VAL(PT_R28) "($at)\n" > + LONG_S "$sp, " VAL(PT_R29) "($at)\n" > + LONG_S "$fp, " VAL(PT_R30) "($at)\n" > + LONG_S "$ra, " VAL(PT_R31) "($at)\n" > + > + /* Now we can get the $at and v0 registers back and > + * store them */ > + LONG_L "$8, %[at]\n" > + LONG_S "$8, " VAL(PT_R1) "($at)\n" > + LONG_L "$8, %[v0]\n" > + LONG_S "$8, " VAL(PT_R2) "($at)\n" > + LONG_L "$8, %[v1]\n" > + LONG_S "$8, " VAL(PT_R3) "($at)\n" > + : > + : > + [at] "m" (at), > + [v0] "m" (v0), > + [v1] "m" (v1), > + [pt_regs] "r" (&my_regs) > + : "at", "t0" > + ); > + > + /* Set the current EPC value to be the current location in this > + * function */ > + __asm__ __volatile__ ( > + ".set noat\n" > + "1:\n" > + PTR_LA "$at, 1b\n" > + LONG_S "$at, %[cp0_epc]\n" > + : > + [cp0_epc] "=m" (my_regs.cp0_epc) > + : > + : "at" > + ); > + > + my_regs.cp0_cause = read_c0_cause(); > + my_regs.cp0_status = read_c0_status(); > + } > + > +#ifdef CONFIG_DIAGNOSTICS > + failure_report((char *) cause_string, > + have_die_regs ? &die_regs : &my_regs); > + have_die_regs = false; > +#else > + pr_crit("I'm feeling a bit sleepy. hmmmmm... perhaps a nap would... " > + "zzzz... \n"); > +#endif What is the point of all this? Almost all registers have likely been modified since panic() was invoked so there is little point in taking a register snapshot? > + > + return NOTIFY_DONE; > +} > + > +/** > + * Platform-specific handling of oops > + * @str: Pointer to the oops string > + * @regs: Pointer to the oops registers > + * All we do here is to save the registers for subsequent printing through > + * the panic notifier. > + */ > +void platform_die(const char *str, const struct pt_regs *regs) > +{ > + /* If we already have saved registers, don't overwrite them as they > + * they apply to the initial fault */ > + > + if (!have_die_regs) { > + have_die_regs = true; > + die_regs = *regs; > + } > +} > + > +/* Information about the RF MAC address, if one was supplied on the > + * command line. */ > +static bool have_rfmac; > +static u8 rfmac[ETH_ALEN]; > + > +static int rfmac_param(char *p) > +{ > + u8 *q; > + bool is_high_nibble; > + int c; > + > + /* Skip a leading "0x", if present */ > + if (*p == '0' && *(p+1) == 'x') > + p += 2; > + > + q = rfmac; > + is_high_nibble = true; > + > + for (c = (unsigned char) *p++; > + isxdigit(c) && q - rfmac < ETH_ALEN; > + c = (unsigned char) *p++) { > + int nibble; > + > + nibble = (isdigit(c) ? (c - '0') : > + (isupper(c) ? c - 'A' + 10 : c - 'a' + 10)); > + > + if (is_high_nibble) > + *q = nibble << 4; > + else > + *q++ |= nibble; > + > + is_high_nibble = !is_high_nibble; > + } > + > + /* If we parsed all the way to the end of the parameter value and > + * parsed all ETH_ALEN bytes, we have a usable RF MAC address */ > + have_rfmac = (c == '\0' && q - rfmac == ETH_ALEN); > + > + return 0; > +} > + > +early_param("rfmac", rfmac_param); > + > +/* > + * Generate an Ethernet MAC address that has a good chance of being unique. > + * @addr: Pointer to six-byte array containing the Ethernet address > + * Generates an Ethernet MAC address that is highly likely to be unique for > + * this particular system on a network with other systems of the same type. > + * > + * The problem we are solving is that, when random_ether_addr() is used to > + * generate MAC addresses at startup, there isn't much entropy for the random > + * number generator to use and the addresses it produces are fairly likely to > + * be the same as those of other identical systems on the same local network. > + * This is true even for relatively small numbers of systems (for the reason > + * why, see the Wikipedia entry for "Birthday problem" at: > + * http://en.wikipedia.org/wiki/Birthday_problem > + * > + * The good news is that we already have a MAC address known to be unique, the > + * RF MAC address. The bad news is that this address is already in use on the > + * RF interface. Worse, the obvious trick, taking the RF MAC address and > + * turning on the locally managed bit, has already been used for other devices. > + * Still, this does give us something to work with. > + * > + * The approach we take is: > + * 1. If we can't get the RF MAC Address, just call random_ether_addr. > + * 2. Use the 24-bit NIC-specific bits of the RF MAC address as the last 24 > + * bits of the new address. This is very likely to be unique, except for > + * the current box. > + * 3. To avoid using addresses already on the current box, we set the top > + * six bits of the address with a value different from any currently > + * registered Scientific Atlanta organizationally unique identifyer > + * (OUI). This avoids duplication with any addresses on the system that > + * were generated from valid Scientific Atlanta-registered address by > + * simply flipping the locally managed bit. > + * 4. We aren't generating a multicast address, so we leave the multicast > + * bit off. Since we aren't using a registered address, we have to set > + * the locally managed bit. > + * 5. We then randomly generate the remaining 16-bits. This does two > + * things: > + * a. It allows us to call this function for more than one device > + * in this system > + * b. It ensures that things will probably still work even if > + * some device on the device network has a locally managed > + * address that matches the top six bits from step 2. > + */ > +void platform_random_ether_addr(u8 addr[ETH_ALEN]) No caller for this function nor exported to a module. > +{ > + const int num_random_bytes = 2; > + const unsigned char non_sciatl_oui_bits = 0xc0u; > + const unsigned char mac_addr_locally_managed = (1 << 1); > + > + if (!have_rfmac) { > + pr_warning("rfmac not available on command line; " > + "generating random MAC address\n"); > + random_ether_addr(addr); > + } > + > + else { Please make that } else { > + int i; > + > + /* Set the first byte to something that won't match a Scientific > + * Atlanta OUI, is locally managed, and isn't a multicast > + * address */ > + addr[0] = non_sciatl_oui_bits | mac_addr_locally_managed; > + > + /* Get some bytes of random address information */ > + get_random_bytes(&addr[1], num_random_bytes); This is probably meant to be called during early bootup when there is very little entropy available and depending on the exact details maybe even duplicate addresses. Can be hairy to solve for some systems. > + > + /* Copy over the NIC-specific bits of the RF MAC address */ > + for (i = 1 + num_random_bytes; i < ETH_ALEN; i++) > + addr[i] = rfmac[i]; > + } > +} > diff --git a/arch/mips/powertv/reset.c b/arch/mips/powertv/reset.c > new file mode 100644 > index 0000000..ec8fe80 > --- /dev/null > +++ b/arch/mips/powertv/reset.c > @@ -0,0 +1,70 @@ > +/* > + * Carsten Langgaard, carstenl@mips.com > + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. > + * Portions copyright (C) 2009 Cisco Systems, Inc. > + * > + * ######################################################################## > + * > + * This program is free software; you can distribute it and/or modify it > + * under the terms of the GNU General Public License (Version 2) as > + * published by the Free Software Foundation. > + * > + * This program is distributed in the hope it will be useful, but WITHOUT > + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or > + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License > + * for more details. > + * > + * You should have received a copy of the GNU General Public License along > + * with this program; if not, write to the Free Software Foundation, Inc., > + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. > + * > + * ######################################################################## > + * > + */ > +#include > + > +#include > +#include /* Not included by linux/reboot.h */ > + > +#ifdef CONFIG_BOOTLOADER_DRIVER > +#include > +#endif > + > +#include > +#include "reset.h" > + > +static void mips_machine_restart(char *command); > +static void mips_machine_halt(void); > + > +static void mips_machine_restart(char *command) > +{ > +#ifdef CONFIG_BOOTLOADER_DRIVER > + /* > + * Call the bootloader's reset function to ensure > + * that persistent data is flushed before hard reset > + */ > + kbldr_SetCauseAndReset(); > +#else > + writel(0x1, asic_reg_addr(watchdog)); > +#endif > +} > + > +static void mips_machine_halt(void) > +{ > +#ifdef CONFIG_BOOTLOADER_DRIVER > + /* > + * Call the bootloader's reset function to ensure > + * that persistent data is flushed before hard reset > + */ > + kbldr_SetCauseAndReset(); > +#else > + writel(0x1, asic_reg_addr(watchdog)); > +#endif > +} > + > +void mips_reboot_setup(void) > +{ > + _machine_restart = mips_machine_restart; > + _machine_halt = mips_machine_halt; > + pm_power_off = mips_machine_halt; > +} > diff --git a/arch/mips/powertv/reset.h b/arch/mips/powertv/reset.h > new file mode 100644 > index 0000000..93d58b9 > --- /dev/null > +++ b/arch/mips/powertv/reset.h > @@ -0,0 +1,28 @@ > +/* > + * reset.h > + * > + * Definitions from powertv reset.c file > + * > + * Copyright (C) 2009 Cisco Systems, Inc. > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, write to the Free Software > + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA > + * > + * Author: David VomLehn > + */ > + > +#ifndef _POWERTV_POWERTV_RESET_H > +#define _POWERTV_POWERTV_RESET_H > +extern void mips_reboot_setup(void); > +#endif This header file seems to only exist to eleminate checkpatch.pl's often bogus warning about prototypes in C files. I suggest to remove this headerfile and invoke mips_reboot_setup via some initcall, like arch_initcall(). > diff --git a/arch/mips/powertv/time.c b/arch/mips/powertv/time.c > new file mode 100644 > index 0000000..1e3e54e > --- /dev/null > +++ b/arch/mips/powertv/time.c > @@ -0,0 +1,30 @@ > +/* > + * Carsten Langgaard, carstenl@mips.com > + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. > + * Portions copyright (C) 2009 Cisco Systems, Inc. > + * > + * This program is free software; you can distribute it and/or modify it > + * under the terms of the GNU General Public License (Version 2) as > + * published by the Free Software Foundation. > + * > + * This program is distributed in the hope it will be useful, but WITHOUT > + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or > + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License > + * for more details. > + * > + * You should have received a copy of the GNU General Public License along > + * with this program; if not, write to the Free Software Foundation, Inc., > + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. > + * > + * Setting up the clock on the MIPS boards. > + */ > + > +#include > + > +#include "powertv-clock.h" > + > +void __init plat_time_init(void) > +{ > + powertv_clocksource_init(); > + powertv_clockevent_init(); > +} When re-sending, please feel free to merge patches 2/3 and 3/3 into this first one. Splitting doesn't really make much sense in this case. Ralf From ralf@linux-mips.org Sat Aug 29 01:02:06 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 29 Aug 2009 01:02:13 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:55965 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1493389AbZH1XCG (ORCPT ); Sat, 29 Aug 2009 01:02:06 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id n7SN36NR000492; Sat, 29 Aug 2009 00:03:06 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id n7SN364W000490; Sat, 29 Aug 2009 00:03:06 +0100 Date: Sat, 29 Aug 2009 00:03:05 +0100 From: Ralf Baechle To: Manuel Lauss Cc: Linux-MIPS , Manuel Lauss Subject: Re: [PATCH v2] Alchemy: override loops_per_jiffy detection Message-ID: <20090828230305.GB30518@linux-mips.org> References: <1251393678-28607-1-git-send-email-manuel.lauss@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1251393678-28607-1-git-send-email-manuel.lauss@gmail.com> User-Agent: Mutt/1.5.19 (2009-01-05) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23962 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Thu, Aug 27, 2009 at 07:21:18PM +0200, Manuel Lauss wrote: > loops_per_jiffy depends on coreclk speed; preset it instead of > letting the kernel waste precious microseconds trying to approximate it. > > Signed-off-by: Manuel Lauss Thanks, applied. Ralf From update+zj4oc66=yc09@facebookmail.com Sat Aug 29 05:21:35 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 29 Aug 2009 05:21:41 +0200 (CEST) Received: from outcampmail005.snc1.tfbnw.net ([69.63.178.190]:63889 "EHLO mx-out.facebook.com" rhost-flags-OK-OK-OK-FAIL) by ftp.linux-mips.org with ESMTP id S1491869AbZH2DVf (ORCPT ); Sat, 29 Aug 2009 05:21:35 +0200 DKIM-Signature: v=1; a=rsa-sha1; d=facebookmail.com; s=q1-2009b; c=relaxed/relaxed; q=dns/txt; i=@facebookmail.com; t=1251516081; h=From:Subject:Date:To:MIME-Version:Content-Type; bh=OLGVnEVgEJMig89l3z5PbgRN0kc=; b=YTwCdSyRfA1chpln0/1jaw1bUGgwwxXOqv1MjhJy0gc+0TY8Q7mbndvTOO1qTeK4 9zam8GGzddg5bEIGA6MT0g==; Received: from [10.18.255.176] ([10.18.255.176:17538]) by mta007.snc1.facebook.com (envelope-from ) (ecelerity 2.2.2.37 r(28805/28844)) with ECSTREAM id EA/DB-11887-1BE989A4; Fri, 28 Aug 2009 20:21:21 -0700 X-Facebook: from zuckmail ([]) by localhost.localdomain with local (ZuckMail); Date: Fri, 28 Aug 2009 20:21:21 -0700 To: "Linux-mips@linux-mips.org" From: Facebook Reply-to: Facebook Subject: Reminder: Amit Kumar Singh invited you to join Facebook... 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--b1_24c0e7afc7061c0dd6d520dbca4fb2ec-- From dvomlehn@cisco.com Mon Aug 31 02:12:36 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 31 Aug 2009 02:12:42 +0200 (CEST) Received: from sj-iport-1.cisco.com ([171.71.176.70]:56364 "EHLO sj-iport-1.cisco.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1493293AbZHaAMg (ORCPT ); Mon, 31 Aug 2009 02:12:36 +0200 X-IronPort-Anti-Spam-Filtered: true X-IronPort-Anti-Spam-Result: ApoEAKaymkqrR7MV/2dsb2JhbAC+e4hBAY4kBYQagVo X-IronPort-AV: E=Sophos;i="4.44,301,1249257600"; d="scan'208";a="235027626" Received: from sj-dkim-1.cisco.com ([171.71.179.21]) by sj-iport-1.cisco.com with ESMTP; 31 Aug 2009 00:12:22 +0000 Received: from sj-core-1.cisco.com (sj-core-1.cisco.com [171.71.177.237]) by sj-dkim-1.cisco.com (8.12.11/8.12.11) with ESMTP id n7V0CMN1019009; Sun, 30 Aug 2009 17:12:22 -0700 Received: from cuplxvomd02.corp.sa.net ([64.101.20.155]) by sj-core-1.cisco.com (8.13.8/8.14.3) with ESMTP id n7V0CMYW002911; Mon, 31 Aug 2009 00:12:22 GMT Date: Sun, 30 Aug 2009 17:12:22 -0700 From: David VomLehn To: Ralf Baechle Cc: linux-mips@linux-mips.org Subject: Re: [PATCH 1/3] mips:powertv: Base files for Cisco Powertv platform, v3 Message-ID: <20090831001222.GA8101@cuplxvomd02.corp.sa.net> References: <20090529183037.GA12464@cuplxvomd02.corp.sa.net> <20090828170654.GA30518@linux-mips.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20090828170654.GA30518@linux-mips.org> User-Agent: Mutt/1.5.18 (2008-05-17) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; l=17664; t=1251677542; x=1252541542; c=relaxed/simple; s=sjdkim1004; h=Content-Type:From:Subject:Content-Transfer-Encoding:MIME-Version; d=cisco.com; i=dvomlehn@cisco.com; z=From:=20David=20VomLehn=20 |Subject:=20Re=3A=20[PATCH=201/3]=20mips=3Apowertv=3A=20Bas e=20files=20for=20Cisco=20Powertv=0A=09platform,=20v3 |Sender:=20; bh=D32dMY3dXM19u7B9pS/sxwb4pV1ELhD5JQuIX7Ni2C0=; b=lQOEPnBB+hRVicyDfgfg09HsDhcJUwgeUnSYz8bkoLr0cSAZze7U0qSR5y OBlxMMcjZMqqZtBsfdwotd0B0+5ymHHe0ObCIOwF6LPp8I4YLUQNrBFNrooq +AKYA93rzaJM8Jvilqw1LAAFtpYKHCQRoPJg4CMflKbjNcuoeIBVo=; Authentication-Results: sj-dkim-1; header.From=dvomlehn@cisco.com; dkim=pass ( sig from cisco.com/sjdkim1004 verified; ); Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23964 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dvomlehn@cisco.com Precedence: bulk X-list: linux-mips On Fri, Aug 28, 2009 at 06:06:54PM +0100, Ralf Baechle wrote: > Old but goldie ... Appologies for needing all eternity to come back > to you on this patch. This is by far the biggest chunk. I'll follow this message with a posting that combines this chunk with the two smaller pieces. I appreciate the time you spent on reviewing this. My response are in-line. ... > > diff --git a/arch/mips/include/asm/mach-powertv/dma-coherence.h b/arch/mips/include/asm/mach-powertv/dma-coherence.h > > new file mode 100644 > > index 0000000..da31ffb > > --- /dev/null > > +++ b/arch/mips/include/asm/mach-powertv/dma-coherence.h > > @@ -0,0 +1,124 @@ > > +/* > > + * dma-coherence.h > > + * > > + * This file is subject to the terms and conditions of the GNU General Public > > + * License. See the file "COPYING" in the main directory of this archive > > + * for more details. > > + * > > + * Version from mach-generic modified to support PowerTV port > > + * Portions Copyright (C) 2009 Cisco Systems, Inc. > > + * Copyright (C) 2006 Ralf Baechle > > + * > > + */ > > + > > +#ifndef __ASM_MACH_POWERTV_DMA_COHERENCE_H > > +#define __ASM_MACH_POWERTV_DMA_COHERENCE_H > > + > > +#include > > +#include > > +#include > > +#include > > + > > +static inline bool is_kseg2(void *addr) > > +{ > > + return (unsigned long)addr >= KSEG2; > > +} > > + > > +static inline unsigned long virt_to_phys_from_pte(void *addr) > > +{ > > + pgd_t *pgd; > > + pud_t *pud; > > + pmd_t *pmd; > > + pte_t *ptep, pte; > > + > > + unsigned long virt_addr = (unsigned long)addr; > > + unsigned long phys_addr = 0UL; > > + > > + /* get the page global directory. */ > > + pgd = pgd_offset_k(virt_addr); > > + > > + if (!pgd_none(*pgd)) { > > + /* get the page upper directory */ > > + pud = pud_offset(pgd, virt_addr); > > + if (!pud_none(*pud)) { > > + /* get the page middle directory */ > > + pmd = pmd_offset(pud, virt_addr); > > + if (!pmd_none(*pmd)) { > > + /* get a pointer to the page table entry */ > > + ptep = pte_offset(pmd, virt_addr); > > + pte = *ptep; > > + /* check for a valid page */ > > + if (pte_present(pte)) { > > + /* get the physical address the page is > > + * refering to */ > > + phys_addr = (unsigned long) > > + page_to_phys(pte_page(pte)); > > + /* add the offset within the page */ > > + phys_addr |= (virt_addr & ~PAGE_MASK); > > + } > > + } > > + } > > + } > > + > > + return phys_addr; > > +} > > Ouch. What is the point of walking ptes here? DMA to vmalloc'ed memory? > The layer that invokes the dma_* mappings functions should do the > vmalloc to physical address translation, see for example blk_rq_map_kern > in the block layer. No, not for vmalloced memory. As I recall, the primary use is for kmap_atomic() pages, which don't go through the DMA subsystem. I have high memory working for 2.6.24, but it breaks on 2.6.25 or 2.6.26, so I don't have any patches for it, yet. Once this gets into the tree, I'll more time to figure out what broken there. > > +static inline int plat_device_is_coherent(struct device *dev) > > +{ > > +#ifdef CONFIG_DMA_COHERENT > > + return 1; > > +#endif > > +#ifdef CONFIG_DMA_NONCOHERENT > > + return 0; > > +#endif > > Do you have multiple system controllers or why do you offer both coherent > and non-coherent DMA here? No, it's always non-coherent. This is what kind of crud builds up when you don't synch up with the kernel tree. I'll fix this. ... > > diff --git a/arch/mips/powertv/asic/asic_devices.c b/arch/mips/powertv/asic/asic_devices.c > > new file mode 100644 > > index 0000000..842e2fc > > --- /dev/null > > +++ b/arch/mips/powertv/asic/asic_devices.c > > @@ -0,0 +1,713 @@ > > +/* > > + * ASIC Device List Intialization > > + * ... > > +static u64 ehci_dmamask = 0xffffffffULL; > > Use DMA_BIT_MASK(32) Fixed. > > +static struct platform_device ehci_device = { > > + .name = "powertv-ehci", > > + .id = 0, > > + .num_resources = 2, > > + .resource = ehci_resources, > > + .dev = { > > + .dma_mask = &ehci_dmamask, > > + .coherent_dma_mask = 0xffffffff, > > Use DMA_BIT_MASK(32) Fixed. > > +static u64 ohci_dmamask = 0xffffffffULL; > > Use DMA_BIT_MASK(32) Fixed. > > +static struct platform_device ohci_device = { > > + .name = "powertv-ohci", > > + .id = 0, > > + .num_resources = 2, > > + .resource = ohci_resources, > > + .dev = { > > + .dma_mask = &ohci_dmamask, > > + .coherent_dma_mask = 0xffffffff, > > Use DMA_BIT_MASK(32) Fixed. > > +/* > > + * Set up the USB EHCI interface > > + */ > > +void platform_configure_usb_ehci() > > Not a valid C prototype - add void. Not intended as a prototype, prototype in arch/mips/include/asm/mach-powertv/asic.h > > +/* > > + * Set up the USB OHCI interface > > + */ > > +void platform_configure_usb_ohci() > > Not a valid C prototype - add void. Not intended as a prototype, prototype in arch/mips/include/asm/mach-powertv/asic.h > > +/* > > + * Shut the USB EHCI interface down--currently a NOP > > + */ > > +void platform_unconfigure_usb_ehci() > > Not a valid C prototype - add void. Not intended as a prototype, prototype in arch/mips/include/asm/mach-powertv/asic.h > > +/* > > + * Shut the USB OHCI interface down--currently a NOP > > + */ > > +void platform_unconfigure_usb_ohci() > > Not a valid C prototype - add void. Not intended as a prototype, prototype in arch/mips/include/asm/mach-powertv/asic.h ... > > +static int __init early_param_pmemlen(char *p) > > +{ > > +/* TODO: we can use this code when and if the bootloader ever changes this */ > > +#if 0 > > + pmemlen = (unsigned long)simple_strtoul(p, NULL, 0); > > if this code is useless enough to be #if 0'ed out, consider deleting it? It's there as a reminder to the kernel team to keep bugging the bootloader team to address this. I think they came close earlier this year... ... > > diff --git a/arch/mips/powertv/asic/asic_int.c b/arch/mips/powertv/asic/asic_int.c > > new file mode 100644 > > index 0000000..ba60bd6 > > --- /dev/null > > +++ b/arch/mips/powertv/asic/asic_int.c > > @@ -0,0 +1,125 @@ ... > > +static inline unsigned int irq_ffs(unsigned int pending) > > +{ > > + return -clz(pending) + 31 - CAUSEB_IP; > > +} > > Please use fls() from instead and get rid of clz(). For > MIPS32 processors fls() is implemented using CLZ. Fixed. > > diff --git a/arch/mips/powertv/asic/prealloc-calliope.c b/arch/mips/powertv/asic/prealloc-calliope.c > > new file mode 100644 > > index 0000000..6823c4c > > --- /dev/null > > +++ b/arch/mips/powertv/asic/prealloc-calliope.c ... > > + /* > > + * Add other resources here > > + * > > + */ > > + /* > > + * End of Resource marker > > + */ > > Some comments just don't deserve to exist ... Agreed. Fixed. > > + { > > + .flags = 0, > > No need to explicitly initialize a member of the end marker; just {} will do > fine. Fixed. > Some comments just don't deserve to exist ... Fixed. > > + { > > + .flags = 0, > > No need to explicitly initialize a member of the end marker; just {} will do > fine. Fixed. > > + /* > > + * End of Resource marker > > + */ > > Some comments just don't deserve to exist ... Fixed. > > + { > > + .flags = 0, > > No need to explicitly initialize a member of the end marker; just {} will do > fine. Fixed. > > + /* > > + * End of Resource marker > > + */ > > Some comments just don't deserve to exist ... Fixed. > > + { > > + .flags = 0, > > No need to explicitly initialize a member of the end marker; just {} will do > fine. Fixed. > > diff --git a/arch/mips/powertv/asic/prealloc-cronus.c b/arch/mips/powertv/asic/prealloc-cronus.c > > new file mode 100644 > > index 0000000..b433efd > > --- /dev/null > > +++ b/arch/mips/powertv/asic/prealloc-cronus.c ... > > + /* > > + * End of Resource marker > > + * > > + */ > > Some comments just don't deserve to exist ... Fixed > > + { > > + .flags = 0, > > No need to explicitly initialize a member of the end marker; just {} will do > fine. Fixed > > +/* > > + * NON_DVR_CAPABLE CRONUS RESOURCES > > + */ > > +struct resource non_dvr_cronus_resources[] __initdata = ... > Some comments just don't deserve to exist ... Fixed > > + { > > + .flags = 0, > > No need to explicitly initialize a member of the end marker; just {} will do > fine. Fixed > > diff --git a/arch/mips/powertv/asic/prealloc-cronuslite.c b/arch/mips/powertv/asic/prealloc-cronuslite.c > > new file mode 100644 > > index 0000000..5bba999 > > --- /dev/null > > +++ b/arch/mips/powertv/asic/prealloc-cronuslite.c ... > > + /* > > + * End of Resource marker > > + * > > + */ > > Some comments just don't deserve to exist ... Fixed > > + { > > + .flags = 0, > No need to explicitly initialize a member of the end marker; just {} will do > fine. Fixed > > diff --git a/arch/mips/powertv/asic/prealloc-zeus.c b/arch/mips/powertv/asic/prealloc-zeus.c > > new file mode 100644 > > index 0000000..3205954 > > --- /dev/null > > +++ b/arch/mips/powertv/asic/prealloc-zeus.c ... > > + /* > > + * End of Resource marker > > + * > > + */ > > Some comments just don't deserve to exist ... Fixed > > + { > > + .flags = 0, > > No need to explicitly initialize a member of the end marker; just {} will do > fine. Fixed ... > > +/* > > + * NON_DVR_CAPABLE ZEUS RESOURCES > > + */ > > +struct resource non_dvr_zeus_resources[] __initdata = ... > > + /* > > + * Add other resources here > > + * > > + * End of Resource marker > > + */ > > Some comments just don't deserve to exist ... Fixed > > + { > > + .flags = 0, > > No need to explicitly initialize a member of the end marker; just {} will do > fine. Fixed > > diff --git a/arch/mips/powertv/cevt-powertv.c b/arch/mips/powertv/cevt-powertv.c > > new file mode 100644 > > index 0000000..ef7768d > > --- /dev/null > > +++ b/arch/mips/powertv/cevt-powertv.c ... > > +/* > > + * The file comes from kernel/cevt-r4k.c > > + */ > > Do you really need this file which to a significant degree is a clone of > cevt-r4k.c? Maybe you can get away with a wrapper around cevt-r4k.c. If > not, please move this file to arch/mips/kernel/ I've switched to using cevt-r4k.c. We get our IRQ numbers from an external source, so we need to use the MIPSR2-supported TI bit in the CP0 Cause register to determine whether a timer interrupt happens. This change is included in the new patch. We also need to implement a get_c0_compare_int() function, which is all that will be left in the cevt-powertv.c file. > > diff --git a/arch/mips/powertv/csrc-powertv.c b/arch/mips/powertv/csrc-powertv.c > > new file mode 100644 > > index 0000000..a27c16c > > --- /dev/null > > +++ b/arch/mips/powertv/csrc-powertv.c ... > > + * The file comes from kernel/csrc-r4k.c > > So why not simply using csrc-r4k.c? Set mips_hpt_frequency before > init_r4k_clocksource() is initialized and voila. Done. Voila. > > + */ > > +#include > > +#include > > + > > +#include /* Not included in linux/time.h */ > > Which makes checkpatch.pl emit bogus warnings. I guess I should rename > asm/time.h and a few other headers affected by this issue for clarity and > fixup all the references. That's way I have that comment in there; it's hard to remember which things can be linux/xyz.h and which must be asm/xyz.h. Renaming would be appreciated. > > + > > +static cycle_t tim_c_read(struct clocksource *cs) > > +{ > > + unsigned int hi; > > + unsigned int next_hi; > > + unsigned int lo; > > + > > + hi = readl(&tim_c->hi); > > + > > + for (;;) { > > + lo = readl(&tim_c->lo); > > + next_hi = readl(&tim_c->hi); > > + if (next_hi == hi) > > + break; > > + hi = next_hi; > > + } > > + > > +pr_crit("%s: read %llx\n", __func__, ((u64) hi << 32) | lo); > > Debugging crap in a function that might be called frequently or well, is > clocksource_tim_c being used at all? The debugging crap is fixed. As far as to whether clocksource_tim_c is being use at all, the answer is, not in this code, but it is in a pending patch. As I've mentioned previously, there are a number of patches waiting for the base Powertv code to go into the MIPS tree. > > diff --git a/arch/mips/powertv/pci/fixup-powertv.c b/arch/mips/powertv/pci/fixup-powertv.c > > new file mode 100644 > > index 0000000..726bc2e > > --- /dev/null > > +++ b/arch/mips/powertv/pci/fixup-powertv.c ... > > +int asic_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) > > +{ > > + return irq_pciexp; > > +} > > +EXPORT_SYMBOL(asic_pcie_map_irq); > > I don't see a module user of asic_pcie_map_irq()? EXPORT dropped. > > diff --git a/arch/mips/powertv/powertv_setup.c b/arch/mips/powertv/powertv_setup.c > > new file mode 100644 > > index 0000000..bd8ebf1 > > --- /dev/null > > +++ b/arch/mips/powertv/powertv_setup.c > > @@ -0,0 +1,351 @@ ... > > +static void register_panic_notifier(void); > > +static int panic_handler(struct notifier_block *notifier_block, > > + unsigned long event, void *cause_string); > > If you reorder the functions in this file you can get away without > prototypes. Fixed. > > + > > +const char *get_system_type(void) > > +{ > > + return "PowerTV"; > > +} > > + > > +void __init plat_mem_setup(void) > > +{ > > + panic_on_oops = 1; > > + register_panic_notifier(); > > + > > +#if 0 > > + mips_pcibios_init(); > > +#endif > > Dead code to be deleted? Sure looks like it to me, fixed. > > +static void register_panic_notifier() > > +{ > > + static struct notifier_block panic_notifier = { > > + .notifier_call = panic_handler, > > + .next = NULL, > > No need to initialize .next. Fixed > > +#ifdef CONFIG_DIAGNOSTICS > > + failure_report((char *) cause_string, > > + have_die_regs ? &die_regs : &my_regs); > > + have_die_regs = false; > > +#else > > + pr_crit("I'm feeling a bit sleepy. hmmmmm... perhaps a nap would... " > > + "zzzz... \n"); > > +#endif > > What is the point of all this? Almost all registers have likely been > modified since panic() was invoked so there is little point in taking a > register snapshot? It depends. There is code, for a later patch, that registers a notifier called from do_trap_or_bp. The notifier function copies the pt_regs, so that a stack backtrace can be done from that point. If panic() was called directly, we still want a backtrace and need a good set of register saved. You must save the $pc, $sp, and $s0-$s8 to do a backtrace by the rules. You could skip the rest of the registers, but saving all of them is fast, takes little code, and would be nice to have if the backtrace rules ever change. > > +void platform_random_ether_addr(u8 addr[ETH_ALEN]) > > No caller for this function nor exported to a module. Used in a patch to be released later. > > +{ > > + const int num_random_bytes = 2; > > + const unsigned char non_sciatl_oui_bits = 0xc0u; > > + const unsigned char mac_addr_locally_managed = (1 << 1); > > + > > + if (!have_rfmac) { > > + pr_warning("rfmac not available on command line; " > > + "generating random MAC address\n"); > > + random_ether_addr(addr); > > + } > > + > > + else { > > Please make that } else { I mail all patches with a script that runs checkpatch every time, so it looks like checkpatch has a small bug. This problem is fixed. > > + int i; > > + > > + /* Set the first byte to something that won't match a Scientific > > + * Atlanta OUI, is locally managed, and isn't a multicast > > + * address */ > > + addr[0] = non_sciatl_oui_bits | mac_addr_locally_managed; > > + > > + /* Get some bytes of random address information */ > > + get_random_bytes(&addr[1], num_random_bytes); > > This is probably meant to be called during early bootup when there is very > little entropy available and depending on the exact details maybe even > duplicate addresses. Can be hairy to solve for some systems. Tell me about it. There are tons of entropy later, since we funnel many video and audio streams through the box, but at boot time we are begging for random bits. > > diff --git a/arch/mips/powertv/reset.h b/arch/mips/powertv/reset.h > > new file mode 100644 > > index 0000000..93d58b9 > > --- /dev/null > > +++ b/arch/mips/powertv/reset.h ... > > +#ifndef _POWERTV_POWERTV_RESET_H > > +#define _POWERTV_POWERTV_RESET_H > > +extern void mips_reboot_setup(void); > > +#endif > > This header file seems to only exist to eleminate checkpatch.pl's often > bogus warning about prototypes in C files. I suggest to remove this > headerfile and invoke mips_reboot_setup via some initcall, like > arch_initcall(). Would that it made even that much sense. It's just that there was one tiny function in a little file that need to be called from one other place. So, I consolidated the files. Easy. Fixed. > When re-sending, please feel free to merge patches 2/3 and 3/3 into this > first one. Splitting doesn't really make much sense in this case. I'm happy to combine them. > Ralf David VL From dvomlehn@cisco.com Mon Aug 31 02:15:27 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 31 Aug 2009 02:15:37 +0200 (CEST) Received: from sj-iport-6.cisco.com ([171.71.176.117]:28855 "EHLO sj-iport-6.cisco.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1493316AbZHaAP1 (ORCPT ); Mon, 31 Aug 2009 02:15:27 +0200 X-IronPort-Anti-Spam-Filtered: true X-IronPort-Anti-Spam-Result: AswEAB+zmkqrR7O6/2dsb2JhbACcJaJaiEEBKo16BYIoBhGBW4Fa X-IronPort-AV: E=Sophos;i="4.44,301,1249257600"; d="scan'208";a="378537733" Received: from sj-dkim-2.cisco.com ([171.71.179.186]) by sj-iport-6.cisco.com with ESMTP; 31 Aug 2009 00:15:11 +0000 Received: from sj-core-5.cisco.com (sj-core-5.cisco.com [171.71.177.238]) by sj-dkim-2.cisco.com (8.12.11/8.12.11) with ESMTP id n7V0FBqm031033; Sun, 30 Aug 2009 17:15:11 -0700 Received: from cuplxvomd02.corp.sa.net ([64.101.20.155]) by sj-core-5.cisco.com (8.13.8/8.14.3) with ESMTP id n7V0FB5H016976; Mon, 31 Aug 2009 00:15:11 GMT Date: Sun, 30 Aug 2009 17:15:11 -0700 From: David VomLehn To: linux-mips@linux-mips.org Cc: ralf@linux-mips.org Subject: [PATCH] mips:powertv: Base files for Cisco Powertv platform, v4 Message-ID: <20090831001511.GA9059@cuplxvomd02.corp.sa.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline User-Agent: Mutt/1.5.18 (2008-05-17) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; l=207792; t=1251677711; x=1252541711; c=relaxed/simple; s=sjdkim2002; h=Content-Type:From:Subject:Content-Transfer-Encoding:MIME-Version; d=cisco.com; i=dvomlehn@cisco.com; z=From:=20David=20VomLehn=20 |Subject:=20[PATCH]=20mips=3Apowertv=3A=20Base=20files=20fo r=20Cisco=20Powertv=20platform,=20v4 |Sender:=20; bh=tqX6xOBXM1mRQGuh/Hyi/OV0j2nRiZhXFZ0AX5vbZdI=; b=tk+/LkpiDgRAmA2lureX7b9qxEV6E7L2AGqxfycJNl5qNsQ4sDH1IH8gZx 8xBu/G+oZhdDjrtu+rlDrwxLGQX/SFhuAVR9B2ev2oqudWXhBQ6hmv2nlAJi 3FDLRbWRa+; Authentication-Results: sj-dkim-2; header.From=dvomlehn@cisco.com; dkim=pass ( sig from cisco.com/sjdkim2002 verified; ); Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23965 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dvomlehn@cisco.com Precedence: bulk X-list: linux-mips This patch adds the Cisco Powertv cable settop box to the MIPS tree. This platform is based on a MIPS 24Kc processor with various devices integrated on the same ASIC. There are multiple models of this box, with differing configuration but the same kernel runs across the product line. This code has been out of the tree *way* too long and, though it has no checkpatch errors, it a few checkpatch warnings and other non-standard things in it. Still, you have to start sometime, so this is where things are today. Adds the Cisco PowerTV platform to the configuration and Make files so that we can build a kernel for it. Signed-off-by: David VomLehn --- arch/mips/Kconfig | 26 + arch/mips/Makefile | 8 + arch/mips/configs/powertv_defconfig | 1550 ++++++++++++++++++++ arch/mips/include/asm/mach-powertv/asic.h | 109 ++ arch/mips/include/asm/mach-powertv/asic_regs.h | 157 ++ arch/mips/include/asm/mach-powertv/dma-coherence.h | 121 ++ arch/mips/include/asm/mach-powertv/interrupts.h | 256 ++++ arch/mips/include/asm/mach-powertv/ioremap.h | 92 ++ arch/mips/include/asm/mach-powertv/irq.h | 27 + arch/mips/include/asm/mach-powertv/war.h | 28 + arch/mips/include/asm/setup.h | 2 +- arch/mips/powertv/Kconfig | 21 + arch/mips/powertv/Makefile | 40 + arch/mips/powertv/asic/Kconfig | 28 + arch/mips/powertv/asic/Makefile | 35 + arch/mips/powertv/asic/asic-calliope.c | 100 ++ arch/mips/powertv/asic/asic-cronus.c | 100 ++ arch/mips/powertv/asic/asic-zeus.c | 100 ++ arch/mips/powertv/asic/asic_devices.c | 789 ++++++++++ arch/mips/powertv/asic/asic_int.c | 125 ++ arch/mips/powertv/asic/irq_asic.c | 116 ++ arch/mips/powertv/asic/prealloc-calliope.c | 622 ++++++++ arch/mips/powertv/asic/prealloc-cronus.c | 610 ++++++++ arch/mips/powertv/asic/prealloc-cronuslite.c | 292 ++++ arch/mips/powertv/asic/prealloc-zeus.c | 461 ++++++ arch/mips/powertv/cevt-powertv.c | 175 +++ arch/mips/powertv/cmdline.c | 52 + arch/mips/powertv/csrc-powertv.c | 180 +++ arch/mips/powertv/init.c | 128 ++ arch/mips/powertv/init.h | 30 + arch/mips/powertv/memory.c | 184 +++ arch/mips/powertv/pci/Makefile | 28 + arch/mips/powertv/pci/fixup-powertv.c | 36 + arch/mips/powertv/pci/powertv-pci.h | 31 + arch/mips/powertv/powertv-clock.h | 30 + arch/mips/powertv/powertv_setup.c | 351 +++++ arch/mips/powertv/reset.c | 70 + arch/mips/powertv/reset.h | 28 + arch/mips/powertv/time.c | 30 + 39 files changed, 7167 insertions(+), 1 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 3ca0fe1..aa96089 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -333,6 +333,24 @@ config PMC_YOSEMITE Yosemite is an evaluation board for the RM9000x2 processor manufactured by PMC-Sierra. +config POWERTV + bool "Support for Cisco PowerTV Platform" + select BOOT_ELF32 + select CEVT_R4K + select CSRC_POWERTV + select DMA_NONCOHERENT + select HW_HAS_PCI + select SYS_HAS_CPU_MIPS32_R2 + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_BIG_ENDIAN + select CPU_MIPSR2_IRQ_VI + select CPU_MIPSR2_IRQ_EI + select USB_OHCI_LITTLE_ENDIAN + select SYS_SUPPORTS_HIGHMEM + select SYS_HAS_EARLY_PRINTK + help + This enables support for the Cisco PowerTV Platform. + config SGI_IP22 bool "SGI IP22 (Indy/Indigo2)" select ARC @@ -663,6 +681,7 @@ source "arch/mips/basler/excite/Kconfig" source "arch/mips/jazz/Kconfig" source "arch/mips/lasat/Kconfig" source "arch/mips/pmc-sierra/Kconfig" +source "arch/mips/powertv/Kconfig" source "arch/mips/sgi-ip27/Kconfig" source "arch/mips/sibyte/Kconfig" source "arch/mips/txx9/Kconfig" @@ -806,6 +825,13 @@ config EARLY_PRINTK config SYS_HAS_EARLY_PRINTK bool +config COMMAND_LINE_SIZE + int "Maximum size of command line passed to kernel from bootloader" + default 256 + help + Most systems work well with the default value, but some bootloaders pass more + information on the command line than others. A smaller value is good here. + config HOTPLUG_CPU bool "Support for hot-pluggable CPUs" depends on SMP && HOTPLUG && SYS_SUPPORTS_HOTPLUG_CPU diff --git a/arch/mips/Makefile b/arch/mips/Makefile index 861da51..6b4971f 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -436,6 +436,14 @@ core-$(CONFIG_NEC_MARKEINS) += arch/mips/emma/markeins/ load-$(CONFIG_NEC_MARKEINS) += 0xffffffff88100000 # +# Cisco PowerTV Platform +# +core-$(CONFIG_POWERTV) += arch/mips/powertv/ +#cflags-$(CONFIG_POWERTV) += -I$(srctree)/arch/mips/include/asm/mach-mips +cflags-$(CONFIG_POWERTV) += -I$(srctree)/arch/mips/include/asm/mach-powertv +load-$(CONFIG_POWERTV) += 0xffffffff90800000 + +# # SGI IP22 (Indy/Indigo2) # # Set the load address to >= 0xffffffff88069000 if you want to leave space for diff --git a/arch/mips/configs/powertv_defconfig b/arch/mips/configs/powertv_defconfig new file mode 100644 index 0000000..a662c08 --- /dev/null +++ b/arch/mips/configs/powertv_defconfig @@ -0,0 +1,1550 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.31-rc5 +# Fri Aug 28 14:49:33 2009 +# +CONFIG_MIPS=y + +# +# Machine selection +# +# CONFIG_MACH_ALCHEMY is not set +# CONFIG_AR7 is not set +# CONFIG_BASLER_EXCITE is not set +# CONFIG_BCM47XX is not set +# CONFIG_MIPS_COBALT is not set +# CONFIG_MACH_DECSTATION is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_LASAT is not set +# CONFIG_LEMOTE_FULONG is not set +# CONFIG_MIPS_MALTA is not set +# CONFIG_MIPS_SIM is not set +# CONFIG_NEC_MARKEINS is not set +# CONFIG_MACH_VR41XX is not set +# CONFIG_NXP_STB220 is not set +# CONFIG_NXP_STB225 is not set +# CONFIG_PNX8550_JBS is not set +# CONFIG_PNX8550_STB810 is not set +# CONFIG_PMC_MSP is not set +# CONFIG_PMC_YOSEMITE is not set +CONFIG_POWERTV=y +# CONFIG_SGI_IP22 is not set +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP28 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_CRHONE is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_BIGSUR is not set +# CONFIG_SNI_RM is not set +# CONFIG_MACH_TX39XX is not set +# CONFIG_MACH_TX49XX is not set +# CONFIG_MIKROTIK_RB532 is not set +# CONFIG_WR_PPMC is not set +# CONFIG_CAVIUM_OCTEON_SIMULATOR is not set +# CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD is not set +# CONFIG_ALCHEMY_GPIO_INDIRECT is not set +# CONFIG_MIN_RUNTIME_RESOURCES is not set +# CONFIG_BOOTLOADER_DRIVER is not set +CONFIG_BOOTLOADER_FAMILY="R2" +CONFIG_CSRC_POWERTV=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_ARCH_SUPPORTS_OPROFILE=y +CONFIG_GENERIC_FIND_NEXT_BIT=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CMOS_UPDATE=y +CONFIG_SCHED_OMIT_FRAME_POINTER=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +CONFIG_CEVT_R4K_LIB=y +CONFIG_CEVT_R4K=y +CONFIG_DMA_NONCOHERENT=y +CONFIG_DMA_NEED_PCI_MAP_STATE=y +# CONFIG_EARLY_PRINTK is not set +CONFIG_SYS_HAS_EARLY_PRINTK=y +CONFIG_COMMAND_LINE_SIZE=4096 +# CONFIG_NO_IOPORT is not set +CONFIG_CPU_BIG_ENDIAN=y +# CONFIG_CPU_LITTLE_ENDIAN is not set +CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y +CONFIG_BOOT_ELF32=y +CONFIG_MIPS_L1_CACHE_SHIFT=5 + +# +# CPU selection +# +# CONFIG_CPU_LOONGSON2 is not set +# CONFIG_CPU_MIPS32_R1 is not set +CONFIG_CPU_MIPS32_R2=y +# CONFIG_CPU_MIPS64_R1 is not set +# CONFIG_CPU_MIPS64_R2 is not set +# CONFIG_CPU_R3000 is not set +# CONFIG_CPU_TX39XX is not set +# CONFIG_CPU_VR41XX is not set +# CONFIG_CPU_R4300 is not set +# CONFIG_CPU_R4X00 is not set +# CONFIG_CPU_TX49XX is not set +# CONFIG_CPU_R5000 is not set +# CONFIG_CPU_R5432 is not set +# CONFIG_CPU_R5500 is not set +# CONFIG_CPU_R6000 is not set +# CONFIG_CPU_NEVADA is not set +# CONFIG_CPU_R8000 is not set +# CONFIG_CPU_R10000 is not set +# CONFIG_CPU_RM7000 is not set +# CONFIG_CPU_RM9000 is not set +# CONFIG_CPU_SB1 is not set +# CONFIG_CPU_CAVIUM_OCTEON is not set +CONFIG_SYS_HAS_CPU_MIPS32_R2=y +CONFIG_CPU_MIPS32=y +CONFIG_CPU_MIPSR2=y +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_HARDWARE_WATCHPOINTS=y + +# +# Kernel type +# +CONFIG_32BIT=y +# CONFIG_64BIT is not set +CONFIG_PAGE_SIZE_4KB=y +# CONFIG_PAGE_SIZE_8KB is not set +# CONFIG_PAGE_SIZE_16KB is not set +# CONFIG_PAGE_SIZE_32KB is not set +# CONFIG_PAGE_SIZE_64KB is not set +CONFIG_CPU_HAS_PREFETCH=y +CONFIG_MIPS_MT_DISABLED=y +# CONFIG_MIPS_MT_SMP is not set +# CONFIG_MIPS_MT_SMTC is not set +CONFIG_CPU_HAS_LLSC=y +CONFIG_CPU_MIPSR2_IRQ_VI=y +CONFIG_CPU_MIPSR2_IRQ_EI=y +CONFIG_CPU_HAS_SYNC=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_IRQ_PROBE=y +# CONFIG_HIGHMEM is not set +CONFIG_CPU_SUPPORTS_HIGHMEM=y +CONFIG_SYS_SUPPORTS_HIGHMEM=y +CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_ARCH_POPULATES_NODE_MAP=y +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=0 +CONFIG_VIRT_TO_BUS=y +CONFIG_HAVE_MLOCK=y +CONFIG_HAVE_MLOCKED_PAGE_BIT=y +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +# CONFIG_HZ_48 is not set +# CONFIG_HZ_100 is not set +# CONFIG_HZ_128 is not set +# CONFIG_HZ_250 is not set +# CONFIG_HZ_256 is not set +CONFIG_HZ_1000=y +# CONFIG_HZ_1024 is not set +CONFIG_SYS_SUPPORTS_ARBIT_HZ=y +CONFIG_HZ=1000 +# CONFIG_PREEMPT_NONE is not set +# CONFIG_PREEMPT_VOLUNTARY is not set +CONFIG_PREEMPT=y +# CONFIG_KEXEC is not set +# CONFIG_SECCOMP is not set +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_CONSTRUCTORS=y + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_LOCK_KERNEL=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +# CONFIG_SWAP is not set +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_AUDIT is not set + +# +# RCU Subsystem +# +CONFIG_CLASSIC_RCU=y +# CONFIG_TREE_RCU is not set +# CONFIG_PREEMPT_RCU is not set +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_PREEMPT_RCU_TRACE is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=16 +CONFIG_GROUP_SCHED=y +CONFIG_FAIR_GROUP_SCHED=y +# CONFIG_RT_GROUP_SCHED is not set +CONFIG_USER_SCHED=y +# CONFIG_CGROUP_SCHED is not set +# CONFIG_CGROUPS is not set +# CONFIG_SYSFS_DEPRECATED_V2 is not set +CONFIG_RELAY=y +# CONFIG_NAMESPACES is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +# CONFIG_RD_GZIP is not set +# CONFIG_RD_BZIP2 is not set +# CONFIG_RD_LZMA is not set +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +CONFIG_EMBEDDED=y +# CONFIG_SYSCTL_SYSCALL is not set +CONFIG_KALLSYMS=y +CONFIG_KALLSYMS_ALL=y +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +# CONFIG_PCSPKR_PLATFORM is not set +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +# CONFIG_EPOLL is not set +# CONFIG_SIGNALFD is not set +CONFIG_TIMERFD=y +# CONFIG_EVENTFD is not set +CONFIG_SHMEM=y +CONFIG_AIO=y + +# +# Performance Counters +# +# CONFIG_VM_EVENT_COUNTERS is not set +CONFIG_PCI_QUIRKS=y +# CONFIG_SLUB_DEBUG is not set +# CONFIG_STRIP_ASM_SYMS is not set +CONFIG_COMPAT_BRK=y +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +# CONFIG_MARKERS is not set +CONFIG_HAVE_OPROFILE=y + +# +# GCOV-based kernel profiling +# +# CONFIG_GCOV_KERNEL is not set +# CONFIG_SLOW_WORK is not set +# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +CONFIG_MODVERSIONS=y +CONFIG_MODULE_SRCVERSION_ALL=y +CONFIG_BLOCK=y +CONFIG_LBDAF=y +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +# CONFIG_IOSCHED_AS is not set +# CONFIG_IOSCHED_DEADLINE is not set +# CONFIG_IOSCHED_CFQ is not set +# CONFIG_DEFAULT_AS is not set +# CONFIG_DEFAULT_DEADLINE is not set +# CONFIG_DEFAULT_CFQ is not set +CONFIG_DEFAULT_NOOP=y +CONFIG_DEFAULT_IOSCHED="noop" +# CONFIG_PROBE_INITRD_HEADER is not set +# CONFIG_FREEZER is not set + +# +# Bus options (PCI, PCMCIA, EISA, ISA, TC) +# +CONFIG_HW_HAS_PCI=y +CONFIG_PCI=y +CONFIG_PCI_DOMAINS=y +# CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_PCI_LEGACY is not set +# CONFIG_PCI_DEBUG is not set +# CONFIG_PCI_STUB is not set +# CONFIG_PCI_IOV is not set +CONFIG_MMU=y +# CONFIG_PCCARD is not set +# CONFIG_HOTPLUG_PCI is not set + +# +# Executable file formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set +# CONFIG_BINFMT_MISC is not set +CONFIG_TRAD_SIGNALS=y + +# +# Power management options +# +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +# CONFIG_PM is not set +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_PACKET_MMAP=y +CONFIG_UNIX=y +CONFIG_XFRM=y +# CONFIG_XFRM_USER is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set +CONFIG_XFRM_IPCOMP=y +# CONFIG_NET_KEY is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_ASK_IP_FIB_HASH=y +# CONFIG_IP_FIB_TRIE is not set +CONFIG_IP_FIB_HASH=y +# CONFIG_IP_MULTIPLE_TABLES is not set +# CONFIG_IP_ROUTE_MULTIPATH is not set +# CONFIG_IP_ROUTE_VERBOSE is not set +CONFIG_IP_PNP=y +# CONFIG_IP_PNP_DHCP is not set +# CONFIG_IP_PNP_BOOTP is not set +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_IP_MROUTE is not set +# CONFIG_ARPD is not set +CONFIG_SYN_COOKIES=y +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_LRO is not set +# CONFIG_INET_DIAG is not set +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +CONFIG_IPV6=y +CONFIG_IPV6_PRIVACY=y +# CONFIG_IPV6_ROUTER_PREF is not set +# CONFIG_IPV6_OPTIMISTIC_DAD is not set +CONFIG_INET6_AH=y +CONFIG_INET6_ESP=y +CONFIG_INET6_IPCOMP=y +# CONFIG_IPV6_MIP6 is not set +CONFIG_INET6_XFRM_TUNNEL=y +CONFIG_INET6_TUNNEL=y +# CONFIG_INET6_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET6_XFRM_MODE_TUNNEL is not set +# CONFIG_INET6_XFRM_MODE_BEET is not set +# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set +# CONFIG_IPV6_SIT is not set +CONFIG_IPV6_TUNNEL=y +# CONFIG_IPV6_MULTIPLE_TABLES is not set +# CONFIG_IPV6_MROUTE is not set +# CONFIG_NETWORK_SECMARK is not set +CONFIG_NETFILTER=y +# CONFIG_NETFILTER_DEBUG is not set +CONFIG_NETFILTER_ADVANCED=y +# CONFIG_BRIDGE_NETFILTER is not set + +# +# Core Netfilter Configuration +# +# CONFIG_NETFILTER_NETLINK_QUEUE is not set +# CONFIG_NETFILTER_NETLINK_LOG is not set +# CONFIG_NF_CONNTRACK is not set +CONFIG_NETFILTER_XTABLES=y +# CONFIG_NETFILTER_XT_TARGET_CLASSIFY is not set +# CONFIG_NETFILTER_XT_TARGET_MARK is not set +# CONFIG_NETFILTER_XT_TARGET_NFLOG is not set +# CONFIG_NETFILTER_XT_TARGET_NFQUEUE is not set +# CONFIG_NETFILTER_XT_TARGET_RATEEST is not set +# CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set +# CONFIG_NETFILTER_XT_MATCH_COMMENT is not set +# CONFIG_NETFILTER_XT_MATCH_DCCP is not set +# CONFIG_NETFILTER_XT_MATCH_DSCP is not set +# CONFIG_NETFILTER_XT_MATCH_ESP is not set +# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set +# CONFIG_NETFILTER_XT_MATCH_HL is not set +# CONFIG_NETFILTER_XT_MATCH_IPRANGE is not set +# CONFIG_NETFILTER_XT_MATCH_LENGTH is not set +# CONFIG_NETFILTER_XT_MATCH_LIMIT is not set +# CONFIG_NETFILTER_XT_MATCH_MAC is not set +# CONFIG_NETFILTER_XT_MATCH_MARK is not set +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y +# CONFIG_NETFILTER_XT_MATCH_OWNER is not set +# CONFIG_NETFILTER_XT_MATCH_POLICY is not set +# CONFIG_NETFILTER_XT_MATCH_PKTTYPE is not set +# CONFIG_NETFILTER_XT_MATCH_QUOTA is not set +# CONFIG_NETFILTER_XT_MATCH_RATEEST is not set +# CONFIG_NETFILTER_XT_MATCH_REALM is not set +# CONFIG_NETFILTER_XT_MATCH_RECENT is not set +# CONFIG_NETFILTER_XT_MATCH_SCTP is not set +# CONFIG_NETFILTER_XT_MATCH_STATISTIC is not set +# CONFIG_NETFILTER_XT_MATCH_STRING is not set +# CONFIG_NETFILTER_XT_MATCH_TCPMSS is not set +# CONFIG_NETFILTER_XT_MATCH_TIME is not set +# CONFIG_NETFILTER_XT_MATCH_U32 is not set +# CONFIG_IP_VS is not set + +# +# IP: Netfilter Configuration +# +# CONFIG_NF_DEFRAG_IPV4 is not set +# CONFIG_IP_NF_QUEUE is not set +CONFIG_IP_NF_IPTABLES=y +# CONFIG_IP_NF_MATCH_ADDRTYPE is not set +# CONFIG_IP_NF_MATCH_AH is not set +# CONFIG_IP_NF_MATCH_ECN is not set +# CONFIG_IP_NF_MATCH_TTL is not set +CONFIG_IP_NF_FILTER=y +# CONFIG_IP_NF_TARGET_REJECT is not set +# CONFIG_IP_NF_TARGET_LOG is not set +# CONFIG_IP_NF_TARGET_ULOG is not set +# CONFIG_IP_NF_MANGLE is not set +# CONFIG_IP_NF_TARGET_TTL is not set +# CONFIG_IP_NF_RAW is not set +CONFIG_IP_NF_ARPTABLES=y +CONFIG_IP_NF_ARPFILTER=y +# CONFIG_IP_NF_ARP_MANGLE is not set + +# +# IPv6: Netfilter Configuration +# +# CONFIG_IP6_NF_QUEUE is not set +CONFIG_IP6_NF_IPTABLES=y +# CONFIG_IP6_NF_MATCH_AH is not set +# CONFIG_IP6_NF_MATCH_EUI64 is not set +# CONFIG_IP6_NF_MATCH_FRAG is not set +# CONFIG_IP6_NF_MATCH_OPTS is not set +# CONFIG_IP6_NF_MATCH_HL is not set +# CONFIG_IP6_NF_MATCH_IPV6HEADER is not set +# CONFIG_IP6_NF_MATCH_MH is not set +# CONFIG_IP6_NF_MATCH_RT is not set +# CONFIG_IP6_NF_TARGET_HL is not set +# CONFIG_IP6_NF_TARGET_LOG is not set +CONFIG_IP6_NF_FILTER=y +# CONFIG_IP6_NF_TARGET_REJECT is not set +# CONFIG_IP6_NF_MANGLE is not set +# CONFIG_IP6_NF_RAW is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +CONFIG_STP=y +CONFIG_BRIDGE=y +# CONFIG_NET_DSA is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +CONFIG_LLC=y +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_PHONET is not set +# CONFIG_IEEE802154 is not set +CONFIG_NET_SCHED=y + +# +# Queueing/Scheduling +# +# CONFIG_NET_SCH_CBQ is not set +# CONFIG_NET_SCH_HTB is not set +# CONFIG_NET_SCH_HFSC is not set +# CONFIG_NET_SCH_PRIO is not set +# CONFIG_NET_SCH_MULTIQ is not set +# CONFIG_NET_SCH_RED is not set +# CONFIG_NET_SCH_SFQ is not set +# CONFIG_NET_SCH_TEQL is not set +CONFIG_NET_SCH_TBF=y +# CONFIG_NET_SCH_GRED is not set +# CONFIG_NET_SCH_DSMARK is not set +# CONFIG_NET_SCH_NETEM is not set +# CONFIG_NET_SCH_DRR is not set + +# +# Classification +# +# CONFIG_NET_CLS_BASIC is not set +# CONFIG_NET_CLS_TCINDEX is not set +# CONFIG_NET_CLS_ROUTE4 is not set +# CONFIG_NET_CLS_FW is not set +# CONFIG_NET_CLS_U32 is not set +# CONFIG_NET_CLS_RSVP is not set +# CONFIG_NET_CLS_RSVP6 is not set +# CONFIG_NET_CLS_FLOW is not set +# CONFIG_NET_EMATCH is not set +# CONFIG_NET_CLS_ACT is not set +CONFIG_NET_SCH_FIFO=y +# CONFIG_DCB is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set +# CONFIG_WIRELESS is not set +# CONFIG_WIMAX is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_CONNECTOR is not set +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_CONCAT is not set +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_TESTS is not set +# CONFIG_MTD_REDBOOT_PARTS is not set +CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_AR7_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_MTD_OOPS is not set + +# +# RAM/ROM/Flash chip drivers +# +# CONFIG_MTD_CFI is not set +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_INTEL_VR_NOR is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_PMC551 is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +CONFIG_MTD_NAND=y +# CONFIG_MTD_NAND_VERIFY_WRITE is not set +# CONFIG_MTD_NAND_ECC_SMC is not set +# CONFIG_MTD_NAND_MUSEUM_IDS is not set +CONFIG_MTD_NAND_IDS=y +# CONFIG_MTD_NAND_DISKONCHIP is not set +# CONFIG_MTD_NAND_CAFE is not set +# CONFIG_MTD_NAND_NANDSIM is not set +# CONFIG_MTD_NAND_PLATFORM is not set +# CONFIG_MTD_ALAUDA is not set +# CONFIG_MTD_ONENAND is not set + +# +# LPDDR flash memory drivers +# +# CONFIG_MTD_LPDDR is not set + +# +# UBI - Unsorted block images +# +# CONFIG_MTD_UBI is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_CPQ_DA is not set +# CONFIG_BLK_CPQ_CISS_DA is not set +# CONFIG_BLK_DEV_DAC960 is not set +# CONFIG_BLK_DEV_UMEM is not set +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=y +# CONFIG_BLK_DEV_CRYPTOLOOP is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_SX8 is not set +# CONFIG_BLK_DEV_UB is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=32768 +# CONFIG_BLK_DEV_XIP is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +# CONFIG_BLK_DEV_HD is not set +# CONFIG_MISC_DEVICES is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_NETLINK is not set +# CONFIG_SCSI_PROC_FS is not set + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_BLK_DEV_SR is not set +# CONFIG_CHR_DEV_SG is not set +# CONFIG_CHR_DEV_SCH is not set +# CONFIG_SCSI_MULTI_LUN is not set +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set +CONFIG_SCSI_WAIT_SCAN=m + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +# CONFIG_SCSI_LOWLEVEL is not set +# CONFIG_SCSI_DH is not set +# CONFIG_SCSI_OSD_INITIATOR is not set +CONFIG_ATA=y +# CONFIG_ATA_NONSTANDARD is not set +CONFIG_SATA_PMP=y +# CONFIG_SATA_AHCI is not set +# CONFIG_SATA_SIL24 is not set +CONFIG_ATA_SFF=y +# CONFIG_SATA_SVW is not set +# CONFIG_ATA_PIIX is not set +# CONFIG_SATA_MV is not set +# CONFIG_SATA_NV is not set +# CONFIG_PDC_ADMA is not set +# CONFIG_SATA_QSTOR is not set +# CONFIG_SATA_PROMISE is not set +# CONFIG_SATA_SX4 is not set +# CONFIG_SATA_SIL is not set +# CONFIG_SATA_SIS is not set +# CONFIG_SATA_ULI is not set +# CONFIG_SATA_VIA is not set +# CONFIG_SATA_VITESSE is not set +# CONFIG_SATA_INIC162X is not set +# CONFIG_PATA_ALI is not set +# CONFIG_PATA_AMD is not set +# CONFIG_PATA_ARTOP is not set +# CONFIG_PATA_ATIIXP is not set +# CONFIG_PATA_CMD640_PCI is not set +# CONFIG_PATA_CMD64X is not set +# CONFIG_PATA_CS5520 is not set +# CONFIG_PATA_CS5530 is not set +# CONFIG_PATA_CYPRESS is not set +# CONFIG_PATA_EFAR is not set +# CONFIG_ATA_GENERIC is not set +# CONFIG_PATA_HPT366 is not set +# CONFIG_PATA_HPT37X is not set +# CONFIG_PATA_HPT3X2N is not set +# CONFIG_PATA_HPT3X3 is not set +# CONFIG_PATA_IT821X is not set +# CONFIG_PATA_IT8213 is not set +# CONFIG_PATA_JMICRON is not set +# CONFIG_PATA_TRIFLEX is not set +# CONFIG_PATA_MARVELL is not set +# CONFIG_PATA_MPIIX is not set +# CONFIG_PATA_OLDPIIX is not set +# CONFIG_PATA_NETCELL is not set +# CONFIG_PATA_NINJA32 is not set +# CONFIG_PATA_NS87410 is not set +# CONFIG_PATA_NS87415 is not set +# CONFIG_PATA_OPTI is not set +# CONFIG_PATA_OPTIDMA is not set +# CONFIG_PATA_PDC_OLD is not set +# CONFIG_PATA_RADISYS is not set +# CONFIG_PATA_RZ1000 is not set +# CONFIG_PATA_SC1200 is not set +# CONFIG_PATA_SERVERWORKS is not set +# CONFIG_PATA_PDC2027X is not set +# CONFIG_PATA_SIL680 is not set +# CONFIG_PATA_SIS is not set +# CONFIG_PATA_VIA is not set +# CONFIG_PATA_WINBOND is not set +# CONFIG_PATA_PLATFORM is not set +# CONFIG_PATA_SCH is not set +# CONFIG_MD is not set +# CONFIG_FUSION is not set + +# +# IEEE 1394 (FireWire) support +# + +# +# You can enable one or both FireWire driver stacks. +# + +# +# See the help texts for more information. +# +# CONFIG_FIREWIRE is not set +# CONFIG_IEEE1394 is not set +# CONFIG_I2O is not set +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_VETH is not set +# CONFIG_ARCNET is not set +# CONFIG_PHYLIB is not set +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +# CONFIG_AX88796 is not set +# CONFIG_HAPPYMEAL is not set +# CONFIG_SUNGEM is not set +# CONFIG_CASSINI is not set +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_SMC91X is not set +# CONFIG_DM9000 is not set +# CONFIG_ETHOC is not set +# CONFIG_DNET is not set +# CONFIG_NET_TULIP is not set +# CONFIG_HP100 is not set +# CONFIG_IBM_NEW_EMAC_ZMII is not set +# CONFIG_IBM_NEW_EMAC_RGMII is not set +# CONFIG_IBM_NEW_EMAC_TAH is not set +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set +# CONFIG_NET_PCI is not set +# CONFIG_B44 is not set +# CONFIG_KS8842 is not set +# CONFIG_ATL2 is not set +CONFIG_NETDEV_1000=y +# CONFIG_ACENIC is not set +# CONFIG_DL2K is not set +# CONFIG_E1000 is not set +# CONFIG_E1000E is not set +# CONFIG_IP1000 is not set +# CONFIG_IGB is not set +# CONFIG_IGBVF is not set +# CONFIG_NS83820 is not set +# CONFIG_HAMACHI is not set +# CONFIG_YELLOWFIN is not set +# CONFIG_R8169 is not set +# CONFIG_SIS190 is not set +# CONFIG_SKGE is not set +# CONFIG_SKY2 is not set +# CONFIG_VIA_VELOCITY is not set +# CONFIG_TIGON3 is not set +# CONFIG_BNX2 is not set +# CONFIG_CNIC is not set +# CONFIG_QLA3XXX is not set +# CONFIG_ATL1 is not set +# CONFIG_ATL1E is not set +# CONFIG_ATL1C is not set +# CONFIG_JME is not set +CONFIG_NETDEV_10000=y +# CONFIG_CHELSIO_T1 is not set +CONFIG_CHELSIO_T3_DEPENDS=y +# CONFIG_CHELSIO_T3 is not set +# CONFIG_ENIC is not set +# CONFIG_IXGBE is not set +# CONFIG_IXGB is not set +# CONFIG_S2IO is not set +# CONFIG_VXGE is not set +# CONFIG_MYRI10GE is not set +# CONFIG_NETXEN_NIC is not set +# CONFIG_NIU is not set +# CONFIG_MLX4_EN is not set +# CONFIG_MLX4_CORE is not set +# CONFIG_TEHUTI is not set +# CONFIG_BNX2X is not set +# CONFIG_QLGE is not set +# CONFIG_SFC is not set +# CONFIG_BE2NET is not set +# CONFIG_TR is not set + +# +# Wireless LAN +# +# CONFIG_WLAN_PRE80211 is not set +# CONFIG_WLAN_80211 is not set + +# +# Enable WiMAX (Networking options) to see the WiMAX drivers +# + +# +# USB Network Adapters +# +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +CONFIG_USB_RTL8150=y +# CONFIG_USB_USBNET is not set +# CONFIG_WAN is not set +# CONFIG_FDDI is not set +# CONFIG_HIPPI is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_NET_FC is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_ISDN is not set +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set + +# +# Userland interfaces +# +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +# CONFIG_VT is not set +# CONFIG_DEVKMEM is not set +# CONFIG_SERIAL_NONSTANDARD is not set +# CONFIG_NOZOMI is not set + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +# CONFIG_SERIAL_JSM is not set +CONFIG_UNIX98_PTYS=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set +# CONFIG_LEGACY_PTYS is not set +# CONFIG_IPMI_HANDLER is not set +# CONFIG_HW_RANDOM is not set +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +CONFIG_DEVPORT=y +# CONFIG_I2C is not set +# CONFIG_SPI is not set + +# +# PPS support +# +# CONFIG_PPS is not set +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +# CONFIG_THERMAL_HWMON is not set +# CONFIG_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_REGULATOR is not set +# CONFIG_MEDIA_SUPPORT is not set + +# +# Graphics support +# +# CONFIG_DRM is not set +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +# CONFIG_FB is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set +# CONFIG_SOUND is not set +CONFIG_HID_SUPPORT=y +CONFIG_HID=y +# CONFIG_HID_DEBUG is not set +# CONFIG_HIDRAW is not set + +# +# USB Input Devices +# +CONFIG_USB_HID=y +# CONFIG_HID_PID is not set +CONFIG_USB_HIDDEV=y + +# +# Special HID drivers +# +# CONFIG_HID_A4TECH is not set +# CONFIG_HID_APPLE is not set +# CONFIG_HID_BELKIN is not set +# CONFIG_HID_CHERRY is not set +# CONFIG_HID_CHICONY is not set +# CONFIG_HID_CYPRESS is not set +# CONFIG_HID_DRAGONRISE is not set +# CONFIG_HID_EZKEY is not set +# CONFIG_HID_KYE is not set +# CONFIG_HID_GYRATION is not set +# CONFIG_HID_KENSINGTON is not set +# CONFIG_HID_LOGITECH is not set +# CONFIG_HID_MICROSOFT is not set +# CONFIG_HID_MONTEREY is not set +# CONFIG_HID_NTRIG is not set +# CONFIG_HID_PANTHERLORD is not set +# CONFIG_HID_PETALYNX is not set +# CONFIG_HID_SAMSUNG is not set +# CONFIG_HID_SONY is not set +# CONFIG_HID_SUNPLUS is not set +# CONFIG_HID_GREENASIA is not set +# CONFIG_HID_SMARTJOYPLUS is not set +# CONFIG_HID_TOPSEED is not set +# CONFIG_HID_THRUSTMASTER is not set +# CONFIG_HID_ZEROPLUS is not set +CONFIG_USB_SUPPORT=y +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y +CONFIG_USB_ARCH_HAS_EHCI=y +CONFIG_USB=y +# CONFIG_USB_DEBUG is not set +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y + +# +# Miscellaneous USB options +# +CONFIG_USB_DEVICEFS=y +# CONFIG_USB_DEVICE_CLASS is not set +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_OTG is not set +# CONFIG_USB_OTG_WHITELIST is not set +# CONFIG_USB_OTG_BLACKLIST_HUB is not set +# CONFIG_USB_MON is not set +# CONFIG_USB_WUSB is not set +# CONFIG_USB_WUSB_CBAF is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_C67X00_HCD is not set +# CONFIG_USB_XHCI_HCD is not set +CONFIG_USB_EHCI_HCD=y +# CONFIG_USB_EHCI_ROOT_HUB_TT is not set +# CONFIG_USB_EHCI_TT_NEWSCHED is not set +# CONFIG_USB_OXU210HP_HCD is not set +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_ISP1760_HCD is not set +CONFIG_USB_OHCI_HCD=y +# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set +# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +# CONFIG_USB_UHCI_HCD is not set +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_WHCI_HCD is not set +# CONFIG_USB_HWA_HCD is not set + +# +# USB Device Class drivers +# +# CONFIG_USB_ACM is not set +# CONFIG_USB_PRINTER is not set +# CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may +# + +# +# also be needed; see USB_STORAGE Help for more info +# +CONFIG_USB_STORAGE=y +# CONFIG_USB_STORAGE_DEBUG is not set +# CONFIG_USB_STORAGE_DATAFAB is not set +# CONFIG_USB_STORAGE_FREECOM is not set +# CONFIG_USB_STORAGE_ISD200 is not set +# CONFIG_USB_STORAGE_USBAT is not set +# CONFIG_USB_STORAGE_SDDR09 is not set +# CONFIG_USB_STORAGE_SDDR55 is not set +# CONFIG_USB_STORAGE_JUMPSHOT is not set +# CONFIG_USB_STORAGE_ALAUDA is not set +# CONFIG_USB_STORAGE_ONETOUCH is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set +# CONFIG_USB_LIBUSUAL is not set + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set + +# +# USB port drivers +# +CONFIG_USB_SERIAL=y +CONFIG_USB_SERIAL_CONSOLE=y +# CONFIG_USB_EZUSB is not set +# CONFIG_USB_SERIAL_GENERIC is not set +# CONFIG_USB_SERIAL_AIRCABLE is not set +# CONFIG_USB_SERIAL_ARK3116 is not set +# CONFIG_USB_SERIAL_BELKIN is not set +# CONFIG_USB_SERIAL_CH341 is not set +# CONFIG_USB_SERIAL_WHITEHEAT is not set +# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set +CONFIG_USB_SERIAL_CP210X=y +# CONFIG_USB_SERIAL_CYPRESS_M8 is not set +# CONFIG_USB_SERIAL_EMPEG is not set +# CONFIG_USB_SERIAL_FTDI_SIO is not set +# CONFIG_USB_SERIAL_FUNSOFT is not set +# CONFIG_USB_SERIAL_VISOR is not set +# CONFIG_USB_SERIAL_IPAQ is not set +# CONFIG_USB_SERIAL_IR is not set +# CONFIG_USB_SERIAL_EDGEPORT is not set +# CONFIG_USB_SERIAL_EDGEPORT_TI is not set +# CONFIG_USB_SERIAL_GARMIN is not set +# CONFIG_USB_SERIAL_IPW is not set +# CONFIG_USB_SERIAL_IUU is not set +# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set +# CONFIG_USB_SERIAL_KEYSPAN is not set +# CONFIG_USB_SERIAL_KLSI is not set +# CONFIG_USB_SERIAL_KOBIL_SCT is not set +# CONFIG_USB_SERIAL_MCT_U232 is not set +# CONFIG_USB_SERIAL_MOS7720 is not set +# CONFIG_USB_SERIAL_MOS7840 is not set +# CONFIG_USB_SERIAL_MOTOROLA is not set +# CONFIG_USB_SERIAL_NAVMAN is not set +# CONFIG_USB_SERIAL_PL2303 is not set +# CONFIG_USB_SERIAL_OTI6858 is not set +# CONFIG_USB_SERIAL_QUALCOMM is not set +# CONFIG_USB_SERIAL_SPCP8X5 is not set +# CONFIG_USB_SERIAL_HP4X is not set +# CONFIG_USB_SERIAL_SAFE is not set +# CONFIG_USB_SERIAL_SIEMENS_MPI is not set +# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set +# CONFIG_USB_SERIAL_SYMBOL is not set +# CONFIG_USB_SERIAL_TI is not set +# CONFIG_USB_SERIAL_CYBERJACK is not set +# CONFIG_USB_SERIAL_XIRCOM is not set +# CONFIG_USB_SERIAL_OPTION is not set +# CONFIG_USB_SERIAL_OMNINET is not set +# CONFIG_USB_SERIAL_OPTICON is not set +# CONFIG_USB_SERIAL_DEBUG is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_BERRY_CHARGE is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_SISUSBVGA is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_TEST is not set +# CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_VST is not set +# CONFIG_USB_GADGET is not set + +# +# OTG and related infrastructure +# +# CONFIG_NOP_USB_XCEIV is not set +# CONFIG_UWB is not set +# CONFIG_MMC is not set +# CONFIG_MEMSTICK is not set +# CONFIG_NEW_LEDS is not set +# CONFIG_ACCESSIBILITY is not set +# CONFIG_INFINIBAND is not set +CONFIG_RTC_LIB=y +# CONFIG_RTC_CLASS is not set +# CONFIG_DMADEVICES is not set +# CONFIG_AUXDISPLAY is not set +# CONFIG_UIO is not set + +# +# TI VLYNQ +# +# CONFIG_STAGING is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=y +# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set +# CONFIG_EXT3_FS_XATTR is not set +# CONFIG_EXT4_FS is not set +CONFIG_JBD=y +# CONFIG_JBD_DEBUG is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +# CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_BTRFS_FS is not set +CONFIG_FILE_LOCKING=y +CONFIG_FSNOTIFY=y +# CONFIG_DNOTIFY is not set +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +CONFIG_FUSE_FS=y +# CONFIG_CUSE is not set + +# +# Caches +# +# CONFIG_FSCACHE is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +# CONFIG_MSDOS_FS is not set +# CONFIG_VFAT_FS is not set +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_KCORE=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_FS_WBUF_VERIFY is not set +# CONFIG_JFFS2_SUMMARY is not set +# CONFIG_JFFS2_FS_XATTR is not set +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set +CONFIG_JFFS2_ZLIB=y +# CONFIG_JFFS2_LZO is not set +CONFIG_JFFS2_RTIME=y +# CONFIG_JFFS2_RUBIN is not set +CONFIG_CRAMFS=y +# CONFIG_SQUASHFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +# CONFIG_NILFS2_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set +CONFIG_ROOT_NFS=y +# CONFIG_NFSD is not set +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_RPCSEC_GSS_KRB5 is not set +# CONFIG_RPCSEC_GSS_SPKM3 is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +# CONFIG_NLS_CODEPAGE_437 is not set +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set +# CONFIG_NLS_ISO8859_1 is not set +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_UTF8 is not set +# CONFIG_DLM is not set + +# +# Kernel hacking +# +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_PRINTK_TIME=y +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_UNUSED_SYMBOLS is not set +CONFIG_DEBUG_FS=y +# CONFIG_HEADERS_CHECK is not set +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_SHIRQ is not set +CONFIG_DETECT_SOFTLOCKUP=y +# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set +CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 +CONFIG_DETECT_HUNG_TASK=y +# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set +CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 +# CONFIG_SCHED_DEBUG is not set +# CONFIG_SCHEDSTATS is not set +# CONFIG_TIMER_STATS is not set +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_DEBUG_PREEMPT is not set +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_RT_MUTEX_TESTER is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_PROVE_LOCKING is not set +# CONFIG_LOCK_STAT is not set +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_DEBUG_KOBJECT is not set +CONFIG_DEBUG_INFO=y +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_WRITECOUNT is not set +# CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_DEBUG_LIST is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_BOOT_PRINTK_DELAY is not set +# CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +# CONFIG_FAULT_INJECTION is not set +# CONFIG_PAGE_POISONING is not set +CONFIG_TRACING_SUPPORT=y +CONFIG_FTRACE=y +# CONFIG_IRQSOFF_TRACER is not set +# CONFIG_PREEMPT_TRACER is not set +# CONFIG_SCHED_TRACER is not set +# CONFIG_ENABLE_DEFAULT_TRACERS is not set +# CONFIG_BOOT_TRACER is not set +CONFIG_BRANCH_PROFILE_NONE=y +# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set +# CONFIG_PROFILE_ALL_BRANCHES is not set +# CONFIG_KMEMTRACE is not set +# CONFIG_WORKQUEUE_TRACER is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_DYNAMIC_DEBUG is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_KGDB is not set +# CONFIG_KMEMCHECK is not set +CONFIG_CMDLINE="rw dhash_entries=1024 ihash_entries=1024 ip=10.0.1.3:10.0.1.1:10.0.1.1:255.255.255.0:zeus:eth0: root=/dev/nfs nfsroot=/nfsroot/cramfs,wsize=512,rsize=512,tcp nokgdb console=ttyUSB0,115200 memsize=252M" +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_RUNTIME_DEBUG is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +# CONFIG_SECURITY_FILE_CAPABILITIES is not set +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +# CONFIG_CRYPTO_FIPS is not set +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD=y +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_BLKCIPHER2=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_PCOMP=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +# CONFIG_CRYPTO_GF128MUL is not set +# CONFIG_CRYPTO_NULL is not set +CONFIG_CRYPTO_WORKQUEUE=y +# CONFIG_CRYPTO_CRYPTD is not set +CONFIG_CRYPTO_AUTHENC=y +# CONFIG_CRYPTO_TEST is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_SEQIV is not set + +# +# Block modes +# +CONFIG_CRYPTO_CBC=y +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +# CONFIG_CRYPTO_ECB is not set +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# +CONFIG_CRYPTO_HMAC=y +# CONFIG_CRYPTO_XCBC is not set + +# +# Digest +# +# CONFIG_CRYPTO_CRC32C is not set +# CONFIG_CRYPTO_MD4 is not set +CONFIG_CRYPTO_MD5=y +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +CONFIG_CRYPTO_SHA1=y +# CONFIG_CRYPTO_SHA256 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +# CONFIG_CRYPTO_AES is not set +# CONFIG_CRYPTO_ANUBIS is not set +# CONFIG_CRYPTO_ARC4 is not set +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +CONFIG_CRYPTO_DES=y +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TWOFISH is not set + +# +# Compression +# +CONFIG_CRYPTO_DEFLATE=y +# CONFIG_CRYPTO_ZLIB is not set +# CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set +# CONFIG_CRYPTO_HW is not set +# CONFIG_BINARY_PRINTF is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_GENERIC_FIND_LAST_BIT=y +# CONFIG_CRC_CCITT is not set +# CONFIG_CRC16 is not set +# CONFIG_CRC_T10DIF is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y +CONFIG_NLATTR=y diff --git a/arch/mips/include/asm/mach-powertv/asic.h b/arch/mips/include/asm/mach-powertv/asic.h new file mode 100644 index 0000000..fd02c4d --- /dev/null +++ b/arch/mips/include/asm/mach-powertv/asic.h @@ -0,0 +1,109 @@ +/* + * asic.h + * + * Copyright (C) 2009 Cisco Systems, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _ASM_MACH_POWERTV_ASIC_H +#define _ASM_MACH_POWERTV_ASIC_H + +#include +#include + +#define DVR_CAPABLE (1<<0) +#define PCIE_CAPABLE (1<<1) +#define FFS_CAPABLE (1<<2) +#define DISPLAY_CAPABLE (1<<3) + +/* Platform Family types + * For compitability, the new value must be added in the end */ +enum family_type { + FAMILY_8500, + FAMILY_8500RNG, + FAMILY_4500, + FAMILY_1500, + FAMILY_8600, + FAMILY_4600, + FAMILY_4600VZA, + FAMILY_8600VZB, + FAMILY_1500VZE, + FAMILY_1500VZF, + FAMILIES +}; + +/* Register maps for each ASIC */ +extern const struct register_map calliope_register_map; +extern const struct register_map cronus_register_map; +extern const struct register_map zeus_register_map; + +extern struct resource dvr_cronus_resources[]; +extern struct resource dvr_zeus_resources[]; +extern struct resource non_dvr_calliope_resources[]; +extern struct resource non_dvr_cronus_resources[]; +extern struct resource non_dvr_cronuslite_resources[]; +extern struct resource non_dvr_vz_calliope_resources[]; +extern struct resource non_dvr_vze_calliope_resources[]; +extern struct resource non_dvr_vzf_calliope_resources[]; +extern struct resource non_dvr_zeus_resources[]; + +extern void powertv_platform_init(void); +extern void platform_alloc_bootmem(void); +extern enum asic_type platform_get_asic(void); +extern enum family_type platform_get_family(void); +extern int platform_supports_dvr(void); +extern int platform_supports_ffs(void); +extern int platform_supports_pcie(void); +extern int platform_supports_display(void); +extern void configure_platform(void); +extern void platform_configure_usb_ehci(void); +extern void platform_unconfigure_usb_ehci(void); +extern void platform_configure_usb_ohci(void); +extern void platform_unconfigure_usb_ohci(void); + +/* Platform Resources */ +#define ASIC_RESOURCE_GET_EXISTS 1 +extern struct resource *asic_resource_get(const char *name); +extern void platform_release_memory(void *baddr, int size); + +/* Reboot Cause */ +extern void set_reboot_cause(char code, unsigned int data, unsigned int data2); +extern void set_locked_reboot_cause(char code, unsigned int data, + unsigned int data2); + +enum sys_reboot_type { + sys_unknown_reboot = 0x00, /* Unknown reboot cause */ + sys_davic_change = 0x01, /* Reboot due to change in DAVIC + * mode */ + sys_user_reboot = 0x02, /* Reboot initiated by user */ + sys_system_reboot = 0x03, /* Reboot initiated by OS */ + sys_trap_reboot = 0x04, /* Reboot due to a CPU trap */ + sys_silent_reboot = 0x05, /* Silent reboot */ + sys_boot_ldr_reboot = 0x06, /* Bootloader reboot */ + sys_power_up_reboot = 0x07, /* Power on bootup. Older + * drivers may report as + * userReboot. */ + sys_code_change = 0x08, /* Reboot to take code change. + * Older drivers may report as + * userReboot. */ + sys_hardware_reset = 0x09, /* HW watchdog or front-panel + * reset button reset. Older + * drivers may report as + * userReboot. */ + sys_watchdogInterrupt = 0x0A /* Pre-watchdog interrupt */ +}; + +#endif /* _ASM_MACH_POWERTV_ASIC_H */ diff --git a/arch/mips/include/asm/mach-powertv/asic_regs.h b/arch/mips/include/asm/mach-powertv/asic_regs.h new file mode 100644 index 0000000..ee1ad6c --- /dev/null +++ b/arch/mips/include/asm/mach-powertv/asic_regs.h @@ -0,0 +1,157 @@ +/* + * asic_regs.h + * + * Copyright (C) 2009 Cisco Systems, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __ASM_MACH_POWERTV_ASIC_H_ +#define __ASM_MACH_POWERTV_ASIC_H_ +#include + +/* ASIC types */ +enum asic_type { + ASIC_UNKNOWN, + ASIC_ZEUS, + ASIC_CALLIOPE, + ASIC_CRONUS, + ASIC_CRONUSLITE, + ASICS +}; + +/* hardcoded values read from Chip Version registers */ +#define CRONUS_10 0x0B4C1C20 +#define CRONUS_11 0x0B4C1C21 +#define CRONUSLITE_10 0x0B4C1C40 + +#define NAND_FLASH_BASE 0x03000000 +#define ZEUS_IO_BASE 0x09000000 +#define CALLIOPE_IO_BASE 0x08000000 +#define CRONUS_IO_BASE 0x09000000 +#define ASIC_IO_SIZE 0x01000000 + +/* Definitions for backward compatibility */ +#define UART1_INTSTAT uart1_intstat +#define UART1_INTEN uart1_inten +#define UART1_CONFIG1 uart1_config1 +#define UART1_CONFIG2 uart1_config2 +#define UART1_DIVISORHI uart1_divisorhi +#define UART1_DIVISORLO uart1_divisorlo +#define UART1_DATA uart1_data +#define UART1_STATUS uart1_status + +/* ASIC register enumeration */ +struct register_map { + u32 eic_slow0_strt_add; + u32 eic_cfg_bits; + u32 eic_ready_status; + + u32 chipver3; + u32 chipver2; + u32 chipver1; + u32 chipver0; + + u32 uart1_intstat; + u32 uart1_inten; + u32 uart1_config1; + u32 uart1_config2; + u32 uart1_divisorhi; + u32 uart1_divisorlo; + u32 uart1_data; + u32 uart1_status; + + u32 int_stat_3; + u32 int_stat_2; + u32 int_stat_1; + u32 int_stat_0; + u32 int_config; + u32 int_int_scan; + u32 ien_int_3; + u32 ien_int_2; + u32 ien_int_1; + u32 ien_int_0; + u32 int_level_3_3; + u32 int_level_3_2; + u32 int_level_3_1; + u32 int_level_3_0; + u32 int_level_2_3; + u32 int_level_2_2; + u32 int_level_2_1; + u32 int_level_2_0; + u32 int_level_1_3; + u32 int_level_1_2; + u32 int_level_1_1; + u32 int_level_1_0; + u32 int_level_0_3; + u32 int_level_0_2; + u32 int_level_0_1; + u32 int_level_0_0; + u32 int_docsis_en; + + u32 mips_pll_setup; + u32 usb_fs; + u32 test_bus; + u32 crt_spare; + u32 usb2_ohci_int_mask; + u32 usb2_strap; + u32 ehci_hcapbase; + u32 ohci_hc_revision; + u32 bcm1_bs_lmi_steer; + u32 usb2_control; + u32 usb2_stbus_obc; + u32 usb2_stbus_mess_size; + u32 usb2_stbus_chunk_size; + + u32 pcie_regs; + u32 tim_ch; + u32 tim_cl; + u32 gpio_dout; + u32 gpio_din; + u32 gpio_dir; + u32 watchdog; + u32 front_panel; + + u32 register_maps; +}; + +extern enum asic_type asic; +extern const struct register_map *register_map; +extern unsigned long asic_phy_base; /* Physical address of ASIC */ +extern unsigned long asic_base; /* Virtual address of ASIC */ + +/* + * Macros to interface to registers through their ioremapped address + * asic_reg_offset Returns the offset of a given register from the start + * of the ASIC address space + * asic_reg_phys_addr Returns the physical address of the given register + * asic_reg_addr Returns the iomapped virtual address of the given + * register. + */ +#define asic_reg_offset(x) (register_map->x) +#define asic_reg_phys_addr(x) (asic_phy_base + asic_reg_offset(x)) +#define asic_reg_addr(x) \ + ((unsigned int *) (asic_base + asic_reg_offset(x))) + +/* + * The asic_reg macro is gone. It should be replaced by either asic_read or + * asic_write, as appropriate. + */ + +#define asic_read(x) readl(asic_reg_addr(x)) +#define asic_write(v, x) writel(v, asic_reg_addr(x)) + +extern void asic_irq_init(void); +#endif diff --git a/arch/mips/include/asm/mach-powertv/dma-coherence.h b/arch/mips/include/asm/mach-powertv/dma-coherence.h new file mode 100644 index 0000000..e6a5d71 --- /dev/null +++ b/arch/mips/include/asm/mach-powertv/dma-coherence.h @@ -0,0 +1,121 @@ +/* + * dma-coherence.h + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Version from mach-generic modified to support PowerTV port + * Portions Copyright (C) 2009 Cisco Systems, Inc. + * Copyright (C) 2006 Ralf Baechle + * + */ + +#ifndef __ASM_MACH_POWERTV_DMA_COHERENCE_H +#define __ASM_MACH_POWERTV_DMA_COHERENCE_H + +#include +#include +#include +#include + +static inline bool is_kseg2(void *addr) +{ + return (unsigned long)addr >= KSEG2; +} + +static inline unsigned long virt_to_phys_from_pte(void *addr) +{ + pgd_t *pgd; + pud_t *pud; + pmd_t *pmd; + pte_t *ptep, pte; + + unsigned long virt_addr = (unsigned long)addr; + unsigned long phys_addr = 0UL; + + /* get the page global directory. */ + pgd = pgd_offset_k(virt_addr); + + if (!pgd_none(*pgd)) { + /* get the page upper directory */ + pud = pud_offset(pgd, virt_addr); + if (!pud_none(*pud)) { + /* get the page middle directory */ + pmd = pmd_offset(pud, virt_addr); + if (!pmd_none(*pmd)) { + /* get a pointer to the page table entry */ + ptep = pte_offset(pmd, virt_addr); + pte = *ptep; + /* check for a valid page */ + if (pte_present(pte)) { + /* get the physical address the page is + * refering to */ + phys_addr = (unsigned long) + page_to_phys(pte_page(pte)); + /* add the offset within the page */ + phys_addr |= (virt_addr & ~PAGE_MASK); + } + } + } + } + + return phys_addr; +} + +static inline dma_addr_t plat_map_dma_mem(struct device *dev, void *addr, + size_t size) +{ + if (is_kseg2(addr)) + return phys_to_bus(virt_to_phys_from_pte(addr)); + else + return phys_to_bus(virt_to_phys(addr)); +} + +static inline dma_addr_t plat_map_dma_mem_page(struct device *dev, + struct page *page) +{ + return phys_to_bus(page_to_phys(page)); +} + +static inline unsigned long plat_dma_addr_to_phys(struct device *dev, + dma_addr_t dma_addr) +{ + return bus_to_phys(dma_addr); +} + +static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr, + size_t size, enum dma_data_direction direction) +{ +} + +static inline int plat_dma_supported(struct device *dev, u64 mask) +{ + /* + * we fall back to GFP_DMA when the mask isn't all 1s, + * so we can't guarantee allocations that must be + * within a tighter range than GFP_DMA.. + */ + if (mask < DMA_BIT_MASK(24)) + return 0; + + return 1; +} + +static inline void plat_extra_sync_for_device(struct device *dev) +{ + return; +} + +static inline int plat_dma_mapping_error(struct device *dev, + dma_addr_t dma_addr) +{ + return 0; +} + +static inline int plat_device_is_coherent(struct device *dev) +{ + return 0; +} + +#endif /* __ASM_MACH_POWERTV_DMA_COHERENCE_H */ diff --git a/arch/mips/include/asm/mach-powertv/interrupts.h b/arch/mips/include/asm/mach-powertv/interrupts.h new file mode 100644 index 0000000..66cd34c --- /dev/null +++ b/arch/mips/include/asm/mach-powertv/interrupts.h @@ -0,0 +1,256 @@ +/* + * interrupts.h + * + * Copyright (C) 2009 Cisco Systems, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _ASM_MACH_POWERTV_INTERRUPTS_H_ +#define _ASM_MACH_POWERTV_INTERRUPTS_H_ + +/* + * Defines for all of the interrupt lines + */ + +/* Definitions for backward compatibility */ +#define kIrq_Uart1 irq_uart1 + +#define ibase 0 + +/*------------- Register: int_stat_3 */ +/* 126 unused (bit 31) */ +#define irq_asc2video (ibase+126) /* ASC 2 Video Interrupt */ +#define irq_asc1video (ibase+125) /* ASC 1 Video Interrupt */ +#define irq_comms_block_wd (ibase+124) /* ASC 1 Video Interrupt */ +#define irq_fdma_mailbox (ibase+123) /* FDMA Mailbox Output */ +#define irq_fdma_gp (ibase+122) /* FDMA GP Output */ +#define irq_mips_pic (ibase+121) /* MIPS Performance Counter + * Interrupt */ +#define irq_mips_timer (ibase+120) /* MIPS Timer Interrupt */ +#define irq_memory_protect (ibase+119) /* Memory Protection Interrupt + * -- Ored by glue logic inside + * SPARC ILC (see + * INT_MEM_PROT_STAT, below, + * for individual interrupts) + */ +/* 118 unused (bit 22) */ +#define irq_sbag (ibase+117) /* SBAG Interrupt -- Ored by + * glue logic inside SPARC ILC + * (see INT_SBAG_STAT, below, + * for individual interrupts) */ +#define irq_qam_b_fec (ibase+116) /* QAM B FEC Interrupt */ +#define irq_qam_a_fec (ibase+115) /* QAM A FEC Interrupt */ +/* 114 unused (bit 18) */ +#define irq_mailbox (ibase+113) /* Mailbox Debug Interrupt -- + * Ored by glue logic inside + * SPARC ILC (see + * INT_MAILBOX_STAT, below, for + * individual interrupts) */ +#define irq_fuse_stat1 (ibase+112) /* Fuse Status 1 */ +#define irq_fuse_stat2 (ibase+111) /* Fuse Status 2 */ +#define irq_fuse_stat3 (ibase+110) /* Blitter Interrupt / Fuse + * Status 3 */ +#define irq_blitter (ibase+110) /* Blitter Interrupt / Fuse + * Status 3 */ +#define irq_avc1_pp0 (ibase+109) /* AVC Decoder #1 PP0 + * Interrupt */ +#define irq_avc1_pp1 (ibase+108) /* AVC Decoder #1 PP1 + * Interrupt */ +#define irq_avc1_mbe (ibase+107) /* AVC Decoder #1 MBE + * Interrupt */ +#define irq_avc2_pp0 (ibase+106) /* AVC Decoder #2 PP0 + * Interrupt */ +#define irq_avc2_pp1 (ibase+105) /* AVC Decoder #2 PP1 + * Interrupt */ +#define irq_avc2_mbe (ibase+104) /* AVC Decoder #2 MBE + * Interrupt */ +#define irq_zbug_spi (ibase+103) /* Zbug SPI Slave Interrupt */ +#define irq_qam_mod2 (ibase+102) /* QAM Modulator 2 DMA + * Interrupt */ +#define irq_ir_rx (ibase+101) /* IR RX 2 Interrupt */ +#define irq_aud_dsp2 (ibase+100) /* Audio DSP #2 Interrupt */ +#define irq_aud_dsp1 (ibase+99) /* Audio DSP #1 Interrupt */ +#define irq_docsis (ibase+98) /* DOCSIS Debug Interrupt */ +#define irq_sd_dvp1 (ibase+97) /* SD DVP #1 Interrupt */ +#define irq_sd_dvp2 (ibase+96) /* SD DVP #2 Interrupt */ +/*------------- Register: int_stat_2 */ +#define irq_hd_dvp (ibase+95) /* HD DVP Interrupt */ +#define kIrq_Prewatchdog (ibase+94) /* watchdog Pre-Interrupt */ +#define irq_timer2 (ibase+93) /* Programmable Timer + * Interrupt 2 */ +#define irq_1394 (ibase+92) /* 1394 Firewire Interrupt */ +#define irq_usbohci (ibase+91) /* USB 2.0 OHCI Interrupt */ +#define irq_usbehci (ibase+90) /* USB 2.0 EHCI Interrupt */ +#define irq_pciexp (ibase+89) /* PCI Express 0 Interrupt */ +#define irq_pciexp0 (ibase+89) /* PCI Express 0 Interrupt */ +#define irq_afe1 (ibase+88) /* AFE 1 Interrupt */ +#define irq_sata (ibase+87) /* SATA 1 Interrupt */ +#define irq_sata1 (ibase+87) /* SATA 1 Interrupt */ +#define irq_dtcp (ibase+86) /* DTCP Interrupt */ +#define irq_pciexp1 (ibase+85) /* PCI Express 1 Interrupt */ +/* 84 unused (bit 20) */ +/* 83 unused (bit 19) */ +/* 82 unused (bit 18) */ +#define irq_sata2 (ibase+81) /* SATA2 Interrupt */ +#define irq_uart2 (ibase+80) /* UART2 Interrupt */ +#define irq_legacy_usb (ibase+79) /* Legacy USB Host ISR (1.1 + * Host module) */ +#define irq_pod (ibase+78) /* POD Interrupt */ +#define irq_slave_usb (ibase+77) /* Slave USB */ +#define irq_denc1 (ibase+76) /* DENC #1 VTG Interrupt */ +#define irq_vbi_vtg (ibase+75) /* VBI VTG Interrupt */ +#define irq_afe2 (ibase+74) /* AFE 2 Interrupt */ +#define irq_denc2 (ibase+73) /* DENC #2 VTG Interrupt */ +#define irq_asc2 (ibase+72) /* ASC #2 Interrupt */ +#define irq_asc1 (ibase+71) /* ASC #1 Interrupt */ +#define irq_mod_dma (ibase+70) /* Modulator DMA Interrupt */ +#define irq_byte_eng1 (ibase+69) /* Byte Engine Interrupt [1] */ +#define irq_byte_eng0 (ibase+68) /* Byte Engine Interrupt [0] */ +/* 67 unused (bit 03) */ +/* 66 unused (bit 02) */ +/* 65 unused (bit 01) */ +/* 64 unused (bit 00) */ +/*------------- Register: int_stat_1 */ +/* 63 unused (bit 31) */ +/* 62 unused (bit 30) */ +/* 61 unused (bit 29) */ +/* 60 unused (bit 28) */ +/* 59 unused (bit 27) */ +/* 58 unused (bit 26) */ +/* 57 unused (bit 25) */ +/* 56 unused (bit 24) */ +#define irq_buf_dma_mem2mem (ibase+55) /* BufDMA Memory to Memory + * Interrupt */ +#define irq_buf_dma_usbtransmit (ibase+54) /* BufDMA USB Transmit + * Interrupt */ +#define irq_buf_dma_qpskpodtransmit (ibase+53) /* BufDMA QPSK/POD Tramsit + * Interrupt */ +#define irq_buf_dma_transmit_error (ibase+52) /* BufDMA Transmit Error + * Interrupt */ +#define irq_buf_dma_usbrecv (ibase+51) /* BufDMA USB Receive + * Interrupt */ +#define irq_buf_dma_qpskpodrecv (ibase+50) /* BufDMA QPSK/POD Receive + * Interrupt */ +#define irq_buf_dma_recv_error (ibase+49) /* BufDMA Receive Error + * Interrupt */ +#define irq_qamdma_transmit_play (ibase+48) /* QAMDMA Transmit/Play + * Interrupt */ +#define irq_qamdma_transmit_error (ibase+47) /* QAMDMA Transmit Error + * Interrupt */ +#define irq_qamdma_recv2high (ibase+46) /* QAMDMA Receive 2 High + * (Chans 63-32) */ +#define irq_qamdma_recv2low (ibase+45) /* QAMDMA Receive 2 Low + * (Chans 31-0) */ +#define irq_qamdma_recv1high (ibase+44) /* QAMDMA Receive 1 High + * (Chans 63-32) */ +#define irq_qamdma_recv1low (ibase+43) /* QAMDMA Receive 1 Low + * (Chans 31-0) */ +#define irq_qamdma_recv_error (ibase+42) /* QAMDMA Receive Error + * Interrupt */ +#define irq_mpegsplice (ibase+41) /* MPEG Splice Interrupt */ +#define irq_deinterlace_rdy (ibase+40) /* Deinterlacer Frame Ready + * Interrupt */ +#define irq_ext_in0 (ibase+39) /* External Interrupt irq_in0 */ +#define irq_gpio3 (ibase+38) /* GP I/O IRQ 3 - From GP I/O + * Module */ +#define irq_gpio2 (ibase+37) /* GP I/O IRQ 2 - From GP I/O + * Module (ABE_intN) */ +#define irq_pcrcmplt1 (ibase+36) /* PCR Capture Complete or + * Discontinuity 1 */ +#define irq_pcrcmplt2 (ibase+35) /* PCR Capture Complete or + * Discontinuity 2 */ +#define irq_parse_peierr (ibase+34) /* PID Parser Error Detect + * (PEI) */ +#define irq_parse_cont_err (ibase+33) /* PID Parser continuity error + * detect */ +#define irq_ds1framer (ibase+32) /* DS1 Framer Interrupt */ +/*------------- Register: int_stat_0 */ +#define irq_gpio1 (ibase+31) /* GP I/O IRQ 1 - From GP I/O + * Module */ +#define irq_gpio0 (ibase+30) /* GP I/O IRQ 0 - From GP I/O + * Module */ +#define irq_qpsk_out_aloha (ibase+29) /* QPSK Output Slotted Aloha + * (chan 3) Transmission + * Completed OK */ +#define irq_qpsk_out_tdma (ibase+28) /* QPSK Output TDMA (chan 2) + * Transmission Completed OK */ +#define irq_qpsk_out_reserve (ibase+27) /* QPSK Output Reservation + * (chan 1) Transmission + * Completed OK */ +#define irq_qpsk_out_aloha_err (ibase+26) /* QPSK Output Slotted Aloha + * (chan 3)Transmission + * completed with Errors. */ +#define irq_qpsk_out_tdma_err (ibase+25) /* QPSK Output TDMA (chan 2) + * Transmission completed with + * Errors. */ +#define irq_qpsk_out_rsrv_err (ibase+24) /* QPSK Output Reservation + * (chan 1) Transmission + * completed with Errors */ +#define irq_aloha_fail (ibase+23) /* Unsuccessful Resend of Aloha + * for N times. Aloha retry + * timeout for channel 3. */ +#define irq_timer1 (ibase+22) /* Programmable Timer + * Interrupt */ +#define irq_keyboard (ibase+21) /* Keyboard Module Interrupt */ +#define irq_i2c (ibase+20) /* I2C Module Interrupt */ +#define irq_spi (ibase+19) /* SPI Module Interrupt */ +#define irq_irblaster (ibase+18) /* IR Blaster Interrupt */ +#define irq_splice_detect (ibase+17) /* PID Key Change Interrupt or + * Splice Detect Interrupt */ +#define irq_se_micro (ibase+16) /* Secure Micro I/F Module + * Interrupt */ +#define irq_uart1 (ibase+15) /* UART Interrupt */ +#define irq_irrecv (ibase+14) /* IR Receiver Interrupt */ +#define irq_host_int1 (ibase+13) /* Host-to-Host Interrupt 1 */ +#define irq_host_int0 (ibase+12) /* Host-to-Host Interrupt 0 */ +#define irq_qpsk_hecerr (ibase+11) /* QPSK HEC Error Interrupt */ +#define irq_qpsk_crcerr (ibase+10) /* QPSK AAL-5 CRC Error + * Interrupt */ +/* 9 unused (bit 09) */ +/* 8 unused (bit 08) */ +#define irq_psicrcerr (ibase+7) /* QAM PSI CRC Error + * Interrupt */ +#define irq_psilength_err (ibase+6) /* QAM PSI Length Error + * Interrupt */ +#define irq_esfforward (ibase+5) /* ESF Interrupt Mark From + * Forward Path Reference - + * every 3ms when forward Mbits + * and forward slot control + * bytes are updated. */ +#define irq_esfreverse (ibase+4) /* ESF Interrupt Mark from + * Reverse Path Reference - + * delayed from forward mark by + * the ranging delay plus a + * fixed amount. When reverse + * Mbits and reverse slot + * control bytes are updated. + * Occurs every 3ms for 3.0M and + * 1.554 M upstream rates and + * every 6 ms for 256K upstream + * rate. */ +#define irq_aloha_timeout (ibase+3) /* Slotted-Aloha timeout on + * Channel 1. */ +#define irq_reservation (ibase+2) /* Partial (or Incremental) + * Reservation Message Completed + * or Slotted aloha verify for + * channel 1. */ +#define irq_aloha3 (ibase+1) /* Slotted-Aloha Message Verify + * Interrupt or Reservation + * increment completed for + * channel 3. */ +#define irq_mpeg_d (ibase+0) /* MPEG Decoder Interrupt */ +#endif /* _ASM_MACH_POWERTV_INTERRUPTS_H_ */ + diff --git a/arch/mips/include/asm/mach-powertv/ioremap.h b/arch/mips/include/asm/mach-powertv/ioremap.h new file mode 100644 index 0000000..1d3be37 --- /dev/null +++ b/arch/mips/include/asm/mach-powertv/ioremap.h @@ -0,0 +1,92 @@ +/* + * ioremap.h + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + * + * Portions Copyright (C) Cisco Systems, Inc. + */ +#ifndef __ASM_MACH_POWERTV_IOREMAP_H +#define __ASM_MACH_POWERTV_IOREMAP_H + +#include + +#define LOW_MEM_BOUNDARY_PHYS 0x20000000 +#define LOW_MEM_BOUNDARY_MASK (~(LOW_MEM_BOUNDARY_PHYS - 1)) + +/* + * The bus addresses are different than the physical addresses that + * the processor sees by an offset. This offset varies by ASIC + * version. Define a variable to hold the offset and some macros to + * make the conversion simpler. */ +extern unsigned long phys_to_bus_offset; + +#ifdef CONFIG_HIGHMEM +#define MEM_GAP_PHYS 0x60000000 +/* + * TODO: We will use the hard code for conversion between physical and + * bus until the bootloader releases their device tree to us. + */ +#define phys_to_bus(x) (((x) < LOW_MEM_BOUNDARY_PHYS) ? \ + ((x) + phys_to_bus_offset) : (x)) +#define bus_to_phys(x) (((x) < MEM_GAP_PHYS_ADDR) ? \ + ((x) - phys_to_bus_offset) : (x)) +#else +#define phys_to_bus(x) ((x) + phys_to_bus_offset) +#define bus_to_phys(x) ((x) - phys_to_bus_offset) +#endif + +/* + * Determine whether the address we are given is for an ASIC device + * Params: addr Address to check + * Returns: Zero if the address is not for ASIC devices, non-zero + * if it is. + */ +static inline int asic_is_device_addr(phys_t addr) +{ + return !((phys_t)addr & (phys_t) LOW_MEM_BOUNDARY_MASK); +} + +/* + * Determine whether the address we are given is external RAM mappable + * into KSEG1. + * Params: addr Address to check + * Returns: Zero if the address is not for external RAM and + */ +static inline int asic_is_lowmem_ram_addr(phys_t addr) +{ + /* + * The RAM always starts at the following address in the processor's + * physical address space + */ + static const phys_t phys_ram_base = 0x10000000; + phys_t bus_ram_base; + + bus_ram_base = phys_to_bus_offset + phys_ram_base; + + return addr >= bus_ram_base && + addr < (bus_ram_base + (LOW_MEM_BOUNDARY_PHYS - phys_ram_base)); +} + +/* + * Allow physical addresses to be fixed up to help peripherals located + * outside the low 32-bit range -- generic pass-through version. + */ +static inline phys_t fixup_bigphys_addr(phys_t phys_addr, phys_t size) +{ + return phys_addr; +} + +static inline void __iomem *plat_ioremap(phys_t offset, unsigned long size, + unsigned long flags) +{ + return NULL; +} + +static inline int plat_iounmap(const volatile void __iomem *addr) +{ + return 0; +} +#endif /* __ASM_MACH_POWERTV_IOREMAP_H */ diff --git a/arch/mips/include/asm/mach-powertv/irq.h b/arch/mips/include/asm/mach-powertv/irq.h new file mode 100644 index 0000000..6ff4f67 --- /dev/null +++ b/arch/mips/include/asm/mach-powertv/irq.h @@ -0,0 +1,27 @@ +/* + * irq.h + * + * Copyright (C) 2009 Cisco Systems, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _ASM_MACH_POWERTV_IRQ_H +#define _ASM_MACH_POWERTV_IRQ_H +#include + +#define MIPS_CPU_IRQ_BASE ibase +#define NR_IRQS 127 +#endif diff --git a/arch/mips/include/asm/mach-powertv/war.h b/arch/mips/include/asm/mach-powertv/war.h new file mode 100644 index 0000000..7ac05ec --- /dev/null +++ b/arch/mips/include/asm/mach-powertv/war.h @@ -0,0 +1,28 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * This version for the PowerTV platform copied from the Malta version. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle + * Portions copyright (C) 2009 Cisco Systems, Inc. + */ +#ifndef __ASM_MACH_POWERTV_WAR_H +#define __ASM_MACH_POWERTV_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 1 +#define MIPS_CACHE_SYNC_WAR 1 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 1 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MACH_POWERTV_WAR_H */ diff --git a/arch/mips/include/asm/setup.h b/arch/mips/include/asm/setup.h index e600ced..132e397 100644 --- a/arch/mips/include/asm/setup.h +++ b/arch/mips/include/asm/setup.h @@ -1,7 +1,7 @@ #ifndef _MIPS_SETUP_H #define _MIPS_SETUP_H -#define COMMAND_LINE_SIZE 256 +#define COMMAND_LINE_SIZE CONFIG_COMMAND_LINE_SIZE #ifdef __KERNEL__ extern void setup_early_printk(void); diff --git a/arch/mips/powertv/Kconfig b/arch/mips/powertv/Kconfig new file mode 100644 index 0000000..ff0e7e3 --- /dev/null +++ b/arch/mips/powertv/Kconfig @@ -0,0 +1,21 @@ +source "arch/mips/powertv/asic/Kconfig" + +config BOOTLOADER_DRIVER + bool "PowerTV Bootloader Driver Support" + default n + depends on POWERTV + help + Use this option if you want to load bootloader driver. + +config BOOTLOADER_FAMILY + string "POWERTV Bootloader Family string" + default "85" + depends on POWERTV && !BOOTLOADER_DRIVER + help + This value should be specified when the bootloader driver is disabled + and must be exactly two characters long. Families supported are: + R1 - RNG-100 R2 - RNG-200 + A1 - Class A B1 - Class B + E1 - Class E F1 - Class F + 44 - 45xx 46 - 46xx + 85 - 85xx 86 - 86xx diff --git a/arch/mips/powertv/Makefile b/arch/mips/powertv/Makefile new file mode 100644 index 0000000..145d065 --- /dev/null +++ b/arch/mips/powertv/Makefile @@ -0,0 +1,40 @@ +# +# Carsten Langgaard, carstenl@mips.com +# Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. +# +# Carsten Langgaard, carstenl@mips.com +# Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. +# Portions copyright (C) 2009 Cisco Systems, Inc. +# +# This program is free software; you can distribute it and/or modify it +# under the terms of the GNU General Public License (Version 2) as +# published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +# for more details. +# +# You should have received a copy of the GNU General Public License along +# with this program; if not, write to the Free Software Foundation, Inc., +# 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. +# +# Makefile for the Cisco PowerTV-specific kernel interface routines +# under Linux. +# + +EXTRA_CFLAGS += -Wall -Werror + +obj-y := + +obj-$(CONFIG_POWERTV) += cmdline.o \ + init.o \ + memory.o \ + reset.o \ + time.o \ + powertv_setup.o \ + asic/ \ + pci/ + +obj-$(CONFIG_CEVT_POWERTV) += cevt-powertv.o +obj-$(CONFIG_CSRC_POWERTV) += csrc-powertv.o diff --git a/arch/mips/powertv/asic/Kconfig b/arch/mips/powertv/asic/Kconfig new file mode 100644 index 0000000..2016bfe --- /dev/null +++ b/arch/mips/powertv/asic/Kconfig @@ -0,0 +1,28 @@ +config MIN_RUNTIME_RESOURCES + bool "Support for minimum runtime resources" + default n + depends on POWERTV + help + Enables support for minimizing the number of (SA asic) runtime + resources that are preallocated by the kernel. + +config MIN_RUNTIME_DOCSIS + bool "Support for minimum DOCSIS resource" + default y + depends on MIN_RUNTIME_RESOURCES + help + Enables support for the preallocated DOCSIS resource. + +config MIN_RUNTIME_PMEM + bool "Support for minimum PMEM resource" + default y + depends on MIN_RUNTIME_RESOURCES + help + Enables support for the preallocated Memory resource. + +config MIN_RUNTIME_TFTP + bool "Support for minimum TFTP resource" + default y + depends on MIN_RUNTIME_RESOURCES + help + Enables support for the preallocated TFTP resource. diff --git a/arch/mips/powertv/asic/Makefile b/arch/mips/powertv/asic/Makefile new file mode 100644 index 0000000..873d079 --- /dev/null +++ b/arch/mips/powertv/asic/Makefile @@ -0,0 +1,35 @@ +# ***************************************************************************** +# Make file for PowerTV Asic related files +# +# Copyright (C) 2009 Scientific-Atlanta, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# +# ***************************************************************************** + +EXTRA_CFLAGS += -Wall -Werror + +obj-y := + +obj-$(CONFIG_POWERTV) += asic-calliope.o \ + asic-cronus.o \ + asic-zeus.o \ + asic_devices.o \ + asic_int.o \ + irq_asic.o \ + prealloc-calliope.o \ + prealloc-cronus.o \ + prealloc-cronuslite.o \ + prealloc-zeus.o diff --git a/arch/mips/powertv/asic/asic-calliope.c b/arch/mips/powertv/asic/asic-calliope.c new file mode 100644 index 0000000..458ef76 --- /dev/null +++ b/arch/mips/powertv/asic/asic-calliope.c @@ -0,0 +1,100 @@ +/* + * asic-calliope.c + * + * Locations of devices in the Calliope ASIC. + * + * Copyright (C) 2005-2009 Scientific-Atlanta, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + * Author: Ken Eppinett + * David Schleef + * + * Description: Defines the platform resources for the SA settop. + */ + +#include + +const struct register_map calliope_register_map = { + .eic_slow0_strt_add = 0x800000, + .eic_cfg_bits = 0x800038, + .eic_ready_status = 0x80004c, + + .chipver3 = 0xA00800, + .chipver2 = 0xA00804, + .chipver1 = 0xA00808, + .chipver0 = 0xA0080c, + + /* The registers of IRBlaster */ + .uart1_intstat = 0xA01800, + .uart1_inten = 0xA01804, + .uart1_config1 = 0xA01808, + .uart1_config2 = 0xA0180C, + .uart1_divisorhi = 0xA01810, + .uart1_divisorlo = 0xA01814, + .uart1_data = 0xA01818, + .uart1_status = 0xA0181C, + + .int_stat_3 = 0xA02800, + .int_stat_2 = 0xA02804, + .int_stat_1 = 0xA02808, + .int_stat_0 = 0xA0280c, + .int_config = 0xA02810, + .int_int_scan = 0xA02818, + .ien_int_3 = 0xA02830, + .ien_int_2 = 0xA02834, + .ien_int_1 = 0xA02838, + .ien_int_0 = 0xA0283c, + .int_level_3_3 = 0xA02880, + .int_level_3_2 = 0xA02884, + .int_level_3_1 = 0xA02888, + .int_level_3_0 = 0xA0288c, + .int_level_2_3 = 0xA02890, + .int_level_2_2 = 0xA02894, + .int_level_2_1 = 0xA02898, + .int_level_2_0 = 0xA0289c, + .int_level_1_3 = 0xA028a0, + .int_level_1_2 = 0xA028a4, + .int_level_1_1 = 0xA028a8, + .int_level_1_0 = 0xA028ac, + .int_level_0_3 = 0xA028b0, + .int_level_0_2 = 0xA028b4, + .int_level_0_1 = 0xA028b8, + .int_level_0_0 = 0xA028bc, + .int_docsis_en = 0xA028F4, + + .mips_pll_setup = 0x980000, + .usb_fs = 0x980030, /* -default 72800028- */ + .test_bus = 0x9800CC, + .crt_spare = 0x9800d4, + .usb2_ohci_int_mask = 0x9A000c, + .usb2_strap = 0x9A0014, + .ehci_hcapbase = 0x9BFE00, + .ohci_hc_revision = 0x9BFC00, + .bcm1_bs_lmi_steer = 0x9E0004, + .usb2_control = 0x9E0054, + .usb2_stbus_obc = 0x9BFF00, + .usb2_stbus_mess_size = 0x9BFF04, + .usb2_stbus_chunk_size = 0x9BFF08, + + .pcie_regs = 0x000000, /* -doesn't exist- */ + .tim_ch = 0xA02C10, + .tim_cl = 0xA02C14, + .gpio_dout = 0xA02c20, + .gpio_din = 0xA02c24, + .gpio_dir = 0xA02c2C, + .watchdog = 0xA02c30, + .front_panel = 0x000000, /* -not used- */ +}; diff --git a/arch/mips/powertv/asic/asic-cronus.c b/arch/mips/powertv/asic/asic-cronus.c new file mode 100644 index 0000000..94737eb --- /dev/null +++ b/arch/mips/powertv/asic/asic-cronus.c @@ -0,0 +1,100 @@ +/* + * asic-cronus.c + * + * Locations of devices in the Cronus ASIC + * + * Copyright (C) 2005-2009 Scientific-Atlanta, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + * Author: Ken Eppinett + * David Schleef + * + * Description: Defines the platform resources for the SA settop. + */ + +#include + +const struct register_map cronus_register_map = { + .eic_slow0_strt_add = 0x000000, + .eic_cfg_bits = 0x000038, + .eic_ready_status = 0x00004C, + + .chipver3 = 0x2A0800, + .chipver2 = 0x2A0804, + .chipver1 = 0x2A0808, + .chipver0 = 0x2A080C, + + /* The registers of IRBlaster */ + .uart1_intstat = 0x2A1800, + .uart1_inten = 0x2A1804, + .uart1_config1 = 0x2A1808, + .uart1_config2 = 0x2A180C, + .uart1_divisorhi = 0x2A1810, + .uart1_divisorlo = 0x2A1814, + .uart1_data = 0x2A1818, + .uart1_status = 0x2A181C, + + .int_stat_3 = 0x2A2800, + .int_stat_2 = 0x2A2804, + .int_stat_1 = 0x2A2808, + .int_stat_0 = 0x2A280C, + .int_config = 0x2A2810, + .int_int_scan = 0x2A2818, + .ien_int_3 = 0x2A2830, + .ien_int_2 = 0x2A2834, + .ien_int_1 = 0x2A2838, + .ien_int_0 = 0x2A283C, + .int_level_3_3 = 0x2A2880, + .int_level_3_2 = 0x2A2884, + .int_level_3_1 = 0x2A2888, + .int_level_3_0 = 0x2A288C, + .int_level_2_3 = 0x2A2890, + .int_level_2_2 = 0x2A2894, + .int_level_2_1 = 0x2A2898, + .int_level_2_0 = 0x2A289C, + .int_level_1_3 = 0x2A28A0, + .int_level_1_2 = 0x2A28A4, + .int_level_1_1 = 0x2A28A8, + .int_level_1_0 = 0x2A28AC, + .int_level_0_3 = 0x2A28B0, + .int_level_0_2 = 0x2A28B4, + .int_level_0_1 = 0x2A28B8, + .int_level_0_0 = 0x2A28BC, + .int_docsis_en = 0x2A28F4, + + .mips_pll_setup = 0x1C0000, + .usb_fs = 0x1C0018, + .test_bus = 0x1C00CC, + .crt_spare = 0x1c00d4, + .usb2_ohci_int_mask = 0x20000C, + .usb2_strap = 0x200014, + .ehci_hcapbase = 0x21FE00, + .ohci_hc_revision = 0x1E0000, + .bcm1_bs_lmi_steer = 0x2E0008, + .usb2_control = 0x2E004C, + .usb2_stbus_obc = 0x21FF00, + .usb2_stbus_mess_size = 0x21FF04, + .usb2_stbus_chunk_size = 0x21FF08, + + .pcie_regs = 0x220000, + .tim_ch = 0x2A2C10, + .tim_cl = 0x2A2C14, + .gpio_dout = 0x2A2C20, + .gpio_din = 0x2A2C24, + .gpio_dir = 0x2A2C2C, + .watchdog = 0x2A2C30, + .front_panel = 0x2A3800, +}; diff --git a/arch/mips/powertv/asic/asic-zeus.c b/arch/mips/powertv/asic/asic-zeus.c new file mode 100644 index 0000000..36200f7 --- /dev/null +++ b/arch/mips/powertv/asic/asic-zeus.c @@ -0,0 +1,100 @@ +/* + * asic-zeus.c + * + * Locations of devices in the Zeus ASIC + * + * Copyright (C) 2005-2009 Scientific-Atlanta, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + * Author: Ken Eppinett + * David Schleef + * + * Description: Defines the platform resources for the SA settop. + */ + +#include + +const struct register_map zeus_register_map = { + .eic_slow0_strt_add = 0x000000, + .eic_cfg_bits = 0x000038, + .eic_ready_status = 0x00004c, + + .chipver3 = 0x280800, + .chipver2 = 0x280804, + .chipver1 = 0x280808, + .chipver0 = 0x28080c, + + /* The registers of IRBlaster */ + .uart1_intstat = 0x281800, + .uart1_inten = 0x281804, + .uart1_config1 = 0x281808, + .uart1_config2 = 0x28180C, + .uart1_divisorhi = 0x281810, + .uart1_divisorlo = 0x281814, + .uart1_data = 0x281818, + .uart1_status = 0x28181C, + + .int_stat_3 = 0x282800, + .int_stat_2 = 0x282804, + .int_stat_1 = 0x282808, + .int_stat_0 = 0x28280c, + .int_config = 0x282810, + .int_int_scan = 0x282818, + .ien_int_3 = 0x282830, + .ien_int_2 = 0x282834, + .ien_int_1 = 0x282838, + .ien_int_0 = 0x28283c, + .int_level_3_3 = 0x282880, + .int_level_3_2 = 0x282884, + .int_level_3_1 = 0x282888, + .int_level_3_0 = 0x28288c, + .int_level_2_3 = 0x282890, + .int_level_2_2 = 0x282894, + .int_level_2_1 = 0x282898, + .int_level_2_0 = 0x28289c, + .int_level_1_3 = 0x2828a0, + .int_level_1_2 = 0x2828a4, + .int_level_1_1 = 0x2828a8, + .int_level_1_0 = 0x2828ac, + .int_level_0_3 = 0x2828b0, + .int_level_0_2 = 0x2828b4, + .int_level_0_1 = 0x2828b8, + .int_level_0_0 = 0x2828bc, + .int_docsis_en = 0x2828F4, + + .mips_pll_setup = 0x1a0000, + .usb_fs = 0x1a0018, + .test_bus = 0x1a0238, + .crt_spare = 0x1a0090, + .usb2_ohci_int_mask = 0x1e000c, + .usb2_strap = 0x1e0014, + .ehci_hcapbase = 0x1FFE00, + .ohci_hc_revision = 0x1FFC00, + .bcm1_bs_lmi_steer = 0x2C0008, + .usb2_control = 0x2c01a0, + .usb2_stbus_obc = 0x1FFF00, + .usb2_stbus_mess_size = 0x1FFF04, + .usb2_stbus_chunk_size = 0x1FFF08, + + .pcie_regs = 0x200000, + .tim_ch = 0x282C10, + .tim_cl = 0x282C14, + .gpio_dout = 0x282c20, + .gpio_din = 0x282c24, + .gpio_dir = 0x282c2C, + .watchdog = 0x282c30, + .front_panel = 0x283800, +}; diff --git a/arch/mips/powertv/asic/asic_devices.c b/arch/mips/powertv/asic/asic_devices.c new file mode 100644 index 0000000..edef822 --- /dev/null +++ b/arch/mips/powertv/asic/asic_devices.c @@ -0,0 +1,789 @@ +/* + * ASIC Device List Intialization + * + * Description: Defines the platform resources for the SA settop. + * + * Copyright (C) 2005-2009 Scientific-Atlanta, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + ***************************************************************************** + * + * File Name: asic_devices.c + * + * Author: Ken Eppinett + * David Schleef + * + * Description: Defines the platform resources for the SA settop. + * + * NOTE: The bootloader allocates persistent memory at an address which is + * 16 MiB below the end of the highest address in KSEG0. All fixed + * address memory reservations must avoid this region. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#ifdef CONFIG_BOOTLOADER_DRIVER +#include +#endif +#include + +#define BOOTLDRFAMILY(byte1, byte0) (((byte1) << 8) | (byte0)) + +/* + * Forward Prototypes + */ +static void pmem_setup_resource(void); + +/* + * Global Variables + */ +enum asic_type asic; + +unsigned int platform_features; +unsigned int platform_family; +const struct register_map *register_map; +EXPORT_SYMBOL(register_map); /* Exported for testing */ +unsigned long asic_phy_base; +unsigned long asic_base; +EXPORT_SYMBOL(asic_base); /* Exported for testing */ +struct resource *gp_resources; +static bool usb_configured; + +/* + * Don't recommend to use it directly, it is usually used by kernel internally. + * Portable code should be using interfaces such as ioremp, dma_map_single, etc. + */ +unsigned long phys_to_bus_offset; +EXPORT_SYMBOL(phys_to_bus_offset); + +/* + * + * IO Resource Definition + * + */ + +struct resource asic_resource = { + .name = "ASIC Resource", + .start = 0, + .end = ASIC_IO_SIZE, + .flags = IORESOURCE_MEM, +}; + +/* + * + * USB Host Resource Definition + * + */ + +static struct resource ehci_resources[] = { + { + .parent = &asic_resource, + .start = 0, + .end = 0xff, + .flags = IORESOURCE_MEM, + }, + { + .start = irq_usbehci, + .end = irq_usbehci, + .flags = IORESOURCE_IRQ, + }, +}; + +static u64 ehci_dmamask = DMA_BIT_MASK(32); + +static struct platform_device ehci_device = { + .name = "powertv-ehci", + .id = 0, + .num_resources = 2, + .resource = ehci_resources, + .dev = { + .dma_mask = &ehci_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, +}; + +static struct resource ohci_resources[] = { + { + .parent = &asic_resource, + .start = 0, + .end = 0xff, + .flags = IORESOURCE_MEM, + }, + { + .start = irq_usbohci, + .end = irq_usbohci, + .flags = IORESOURCE_IRQ, + }, +}; + +static u64 ohci_dmamask = DMA_BIT_MASK(32); + +static struct platform_device ohci_device = { + .name = "powertv-ohci", + .id = 0, + .num_resources = 2, + .resource = ohci_resources, + .dev = { + .dma_mask = &ohci_dmamask, + .coherent_dma_mask = DMA_BIT_MASK(32), + }, +}; + +static struct platform_device *platform_devices[] = { + &ehci_device, + &ohci_device, +}; + +/* + * + * Platform Configuration and Device Initialization + * + */ +static void __init fs_update(int pe, int md, int sdiv, int disable_div_by_3) +{ + int en_prg, byp, pwr, nsb, val; + int sout; + + sout = 1; + en_prg = 1; + byp = 0; + nsb = 1; + pwr = 1; + + val = ((sdiv << 29) | (md << 24) | (pe<<8) | (sout<<3) | (byp<<2) | + (nsb<<1) | (disable_div_by_3<<5)); + + asic_write(val, usb_fs); + asic_write(val | (en_prg<<4), usb_fs); + asic_write(val | (en_prg<<4) | pwr, usb_fs); +} + +/* + * Allow override of bootloader-specified model + */ +static char __initdata cmdline[CONFIG_COMMAND_LINE_SIZE]; +#define FORCEFAMILY_PARAM "forcefamily" + +static __init int check_forcefamily(unsigned char forced_family[2]) +{ + const char *p; + + forced_family[0] = '\0'; + forced_family[1] = '\0'; + + /* Check the command line for a forcefamily directive */ + strncpy(cmdline, arcs_cmdline, CONFIG_COMMAND_LINE_SIZE - 1); + p = strstr(cmdline, FORCEFAMILY_PARAM); + if (p && (p != cmdline) && (*(p - 1) != ' ')) + p = strstr(p, " " FORCEFAMILY_PARAM "="); + + if (p) { + p += strlen(FORCEFAMILY_PARAM "="); + + if (*p == '\0' || *(p + 1) == '\0' || + (*(p + 2) != '\0' && *(p + 2) != ' ')) + pr_err(FORCEFAMILY_PARAM " must be exactly two " + "characters long, ignoring value\n"); + + else { + forced_family[0] = *p; + forced_family[1] = *(p + 1); + } + } + + return 0; +} + +/* + * platform_set_family - determine major platform family type. + * + * Returns family type; -1 if none + * Returns the family type; -1 if none + * + */ +static __init noinline void platform_set_family(void) +{ +#define BOOTLDRFAMILY(byte1, byte0) (((byte1) << 8) | (byte0)) + + unsigned char forced_family[2]; + unsigned short bootldr_family; + + check_forcefamily(forced_family); + + if (forced_family[0] != '\0' && forced_family[1] != '\0') + bootldr_family = BOOTLDRFAMILY(forced_family[0], + forced_family[1]); + else { + +#ifdef CONFIG_BOOTLOADER_DRIVER + bootldr_family = (unsigned short) kbldr_GetSWFamily(); +#else +#if defined(CONFIG_BOOTLOADER_FAMILY) + bootldr_family = (unsigned short) BOOTLDRFAMILY( + CONFIG_BOOTLOADER_FAMILY[0], + CONFIG_BOOTLOADER_FAMILY[1]); +#else +#error "Unknown Bootloader Family" +#endif +#endif + } + + pr_info("Bootloader Family = 0x%04X\n", bootldr_family); + + switch (bootldr_family) { + case BOOTLDRFAMILY('R', '1'): + platform_family = FAMILY_1500; + break; + case BOOTLDRFAMILY('4', '4'): + platform_family = FAMILY_4500; + break; + case BOOTLDRFAMILY('4', '6'): + platform_family = FAMILY_4600; + break; + case BOOTLDRFAMILY('A', '1'): + platform_family = FAMILY_4600VZA; + break; + case BOOTLDRFAMILY('8', '5'): + platform_family = FAMILY_8500; + break; + case BOOTLDRFAMILY('R', '2'): + platform_family = FAMILY_8500RNG; + break; + case BOOTLDRFAMILY('8', '6'): + platform_family = FAMILY_8600; + break; + case BOOTLDRFAMILY('B', '1'): + platform_family = FAMILY_8600VZB; + break; + case BOOTLDRFAMILY('E', '1'): + platform_family = FAMILY_1500VZE; + break; + case BOOTLDRFAMILY('F', '1'): + platform_family = FAMILY_1500VZF; + break; + default: + platform_family = -1; + } +} + +unsigned int platform_get_family(void) +{ + return platform_family; +} +EXPORT_SYMBOL(platform_get_family); + +/* + * \brief usb_eye_configure() for optimizing the USB eye on Calliope. + * + * \param unsigned int value saved to the register. + * + * \return none + * + */ +static void __init usb_eye_configure(unsigned int value) +{ + asic_write(asic_read(crt_spare) | value, crt_spare); +} + +/* + * platform_get_asic - determine the ASIC type. + * + * \param none + * + * \return ASIC type; ASIC_UNKNOWN if none + * + */ +enum asic_type platform_get_asic(void) +{ + return asic; +} +EXPORT_SYMBOL(platform_get_asic); + +/* + * platform_configure_usb - usb configuration based on platform type. + * @bcm1_usb2_ctl: value for the BCM1_USB2_CTL register, which is + * quirky + */ +static void __init platform_configure_usb(void) +{ + u32 bcm1_usb2_ctl; + + if (usb_configured) + return; + + switch (asic) { + case ASIC_ZEUS: + fs_update(0x0000, 0x11, 0x02, 0); + bcm1_usb2_ctl = 0x803; + break; + + case ASIC_CRONUS: + case ASIC_CRONUSLITE: + fs_update(0x0000, 0x11, 0x02, 0); + bcm1_usb2_ctl = 0x803; + break; + + case ASIC_CALLIOPE: + fs_update(0x0000, 0x11, 0x02, 1); + + switch (platform_family) { + case FAMILY_1500VZE: + break; + + case FAMILY_1500VZF: + usb_eye_configure(0x003c0000); + break; + + default: + usb_eye_configure(0x00300000); + break; + } + + bcm1_usb2_ctl = 0x803; + break; + + default: + pr_err("Unknown ASIC type: %d\n", asic); + break; + } + + /* turn on USB power */ + asic_write(0, usb2_strap); + /* Enable all OHCI interrupts */ + asic_write(bcm1_usb2_ctl, usb2_control); + /* USB2_STBUS_OBC store32/load32 */ + asic_write(3, usb2_stbus_obc); + /* USB2_STBUS_MESS_SIZE 2 packets */ + asic_write(1, usb2_stbus_mess_size); + /* USB2_STBUS_CHUNK_SIZE 2 packets */ + asic_write(1, usb2_stbus_chunk_size); + + usb_configured = true; +} + +/* + * Set up the USB EHCI interface + */ +void platform_configure_usb_ehci() +{ + platform_configure_usb(); +} + +/* + * Set up the USB OHCI interface + */ +void platform_configure_usb_ohci() +{ + platform_configure_usb(); +} + +/* + * Shut the USB EHCI interface down--currently a NOP + */ +void platform_unconfigure_usb_ehci() +{ +} + +/* + * Shut the USB OHCI interface down--currently a NOP + */ +void platform_unconfigure_usb_ohci() +{ +} + +/** + * configure_platform - configuration based on platform type. + */ +void __init configure_platform(void) +{ + platform_set_family(); + + switch (platform_family) { + case FAMILY_1500: + case FAMILY_1500VZE: + case FAMILY_1500VZF: + platform_features = FFS_CAPABLE; + asic = ASIC_CALLIOPE; + asic_phy_base = CALLIOPE_IO_BASE; + register_map = &calliope_register_map; + asic_base = (unsigned long)ioremap_nocache(asic_phy_base, + ASIC_IO_SIZE); + + if (platform_family == FAMILY_1500VZE) { + gp_resources = non_dvr_vze_calliope_resources; + pr_info("Platform: 1500/Vz Class E - " + "CALLIOPE, NON_DVR_CAPABLE\n"); + } else if (platform_family == FAMILY_1500VZF) { + gp_resources = non_dvr_vzf_calliope_resources; + pr_info("Platform: 1500/Vz Class F - " + "CALLIOPE, NON_DVR_CAPABLE\n"); + } else { + gp_resources = non_dvr_calliope_resources; + pr_info("Platform: 1500/RNG100 - CALLIOPE, " + "NON_DVR_CAPABLE\n"); + } + break; + + case FAMILY_4500: + platform_features = FFS_CAPABLE | PCIE_CAPABLE | + DISPLAY_CAPABLE; + asic = ASIC_ZEUS; + asic_phy_base = ZEUS_IO_BASE; + register_map = &zeus_register_map; + asic_base = (unsigned long)ioremap_nocache(asic_phy_base, + ASIC_IO_SIZE); + gp_resources = non_dvr_zeus_resources; + + pr_info("Platform: 4500 - ZEUS, NON_DVR_CAPABLE\n"); + break; + + case FAMILY_4600: + { + unsigned int chipversion = 0; + + /* The settop has PCIE but it isn't used, so don't advertise + * it*/ + platform_features = FFS_CAPABLE | DISPLAY_CAPABLE; + asic_phy_base = CRONUS_IO_BASE; /* same as Cronus */ + register_map = &cronus_register_map; /* same as Cronus */ + asic_base = (unsigned long)ioremap_nocache(asic_phy_base, + ASIC_IO_SIZE); + gp_resources = non_dvr_cronuslite_resources; + + /* ASIC version will determine if this is a real CronusLite or + * Castrati(Cronus) */ + chipversion = asic_read(chipver3) << 24; + chipversion |= asic_read(chipver2) << 16; + chipversion |= asic_read(chipver1) << 8; + chipversion |= asic_read(chipver0); + + if ((chipversion == CRONUS_10) || (chipversion == CRONUS_11)) + asic = ASIC_CRONUS; + else + asic = ASIC_CRONUSLITE; + + pr_info("Platform: 4600 - %s, NON_DVR_CAPABLE, " + "chipversion=0x%08X\n", + (asic == ASIC_CRONUS) ? "CRONUS" : "CRONUS LITE", + chipversion); + break; + } + case FAMILY_4600VZA: + platform_features = FFS_CAPABLE | DISPLAY_CAPABLE; + asic = ASIC_CRONUS; + asic_phy_base = CRONUS_IO_BASE; + register_map = &cronus_register_map; + asic_base = (unsigned long)ioremap_nocache(asic_phy_base, + ASIC_IO_SIZE); + gp_resources = non_dvr_cronus_resources; + + pr_info("Platform: Vz Class A - CRONUS, NON_DVR_CAPABLE\n"); + break; + + case FAMILY_8500: + case FAMILY_8500RNG: + platform_features = DVR_CAPABLE | PCIE_CAPABLE | + DISPLAY_CAPABLE; + asic = ASIC_ZEUS; + asic_phy_base = ZEUS_IO_BASE; + register_map = &zeus_register_map; + asic_base = (unsigned long)ioremap_nocache(asic_phy_base, + ASIC_IO_SIZE); + gp_resources = dvr_zeus_resources; + + pr_info("Platform: 8500/RNG200 - ZEUS, DVR_CAPABLE\n"); + break; + + case FAMILY_8600: + case FAMILY_8600VZB: + platform_features = DVR_CAPABLE | PCIE_CAPABLE | + DISPLAY_CAPABLE; + asic = ASIC_CRONUS; + asic_phy_base = CRONUS_IO_BASE; + register_map = &cronus_register_map; + asic_base = (unsigned long)ioremap_nocache(asic_phy_base, + ASIC_IO_SIZE); + gp_resources = dvr_cronus_resources; + + pr_info("Platform: 8600/Vz Class B - CRONUS, " + "DVR_CAPABLE\n"); + break; + + default: + pr_crit("Platform: UNKNOWN PLATFORM\n"); + break; + } + + switch (asic) { + case ASIC_ZEUS: + phys_to_bus_offset = 0x30000000; + break; + case ASIC_CALLIOPE: + phys_to_bus_offset = 0x10000000; + break; + case ASIC_CRONUSLITE: + /* Fall through */ + case ASIC_CRONUS: + /* + * TODO: We suppose 0x10000000 aliases into 0x20000000- + * 0x2XXXXXXX. If 0x10000000 aliases into 0x60000000- + * 0x6XXXXXXX, the offset should be 0x50000000, not 0x10000000. + */ + phys_to_bus_offset = 0x10000000; + break; + default: + phys_to_bus_offset = 0x00000000; + break; + } +} + +/** + * platform_devices_init - sets up USB device resourse. + */ +static int __init platform_devices_init(void) +{ + pr_notice("%s: ----- Initializing USB resources -----\n", __func__); + + asic_resource.start = asic_phy_base; + asic_resource.end += asic_resource.start; + + ehci_resources[0].start = asic_reg_phys_addr(ehci_hcapbase); + ehci_resources[0].end += ehci_resources[0].start; + + ohci_resources[0].start = asic_reg_phys_addr(ohci_hc_revision); + ohci_resources[0].end += ohci_resources[0].start; + + set_io_port_base(0); + + platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); + + return 0; +} + +arch_initcall(platform_devices_init); + +/* + * + * BOOTMEM ALLOCATION + * + */ +/* + * Allocates/reserves the Platform memory resources early in the boot process. + * This ignores any resources that are designated IORESOURCE_IO + */ +void __init platform_alloc_bootmem(void) +{ + int i; + int total = 0; + + /* Get persistent memory data from command line before allocating + * resources. This need to happen before normal command line parsing + * has been done */ + pmem_setup_resource(); + + /* Loop through looking for resources that want a particular address */ + for (i = 0; gp_resources[i].flags != 0; i++) { + int size = gp_resources[i].end - gp_resources[i].start + 1; + if ((gp_resources[i].start != 0) && + ((gp_resources[i].flags & IORESOURCE_MEM) != 0)) { + reserve_bootmem(bus_to_phys(gp_resources[i].start), + size, 0); + total += gp_resources[i].end - + gp_resources[i].start + 1; + pr_info("reserve resource %s at %08x (%u bytes)\n", + gp_resources[i].name, gp_resources[i].start, + gp_resources[i].end - + gp_resources[i].start + 1); + } + } + + /* Loop through assigning addresses for those that are left */ + for (i = 0; gp_resources[i].flags != 0; i++) { + int size = gp_resources[i].end - gp_resources[i].start + 1; + if ((gp_resources[i].start == 0) && + ((gp_resources[i].flags & IORESOURCE_MEM) != 0)) { + void *mem = alloc_bootmem_pages(size); + + if (mem == NULL) + pr_err("Unable to allocate bootmem pages " + "for %s\n", gp_resources[i].name); + + else { + gp_resources[i].start = + phys_to_bus(virt_to_phys(mem)); + gp_resources[i].end = + gp_resources[i].start + size - 1; + total += size; + pr_info("allocate resource %s at %08x " + "(%u bytes)\n", + gp_resources[i].name, + gp_resources[i].start, size); + } + } + } + + pr_info("Total Platform driver memory allocation: 0x%08x\n", total); + + /* indicate resources that are platform I/O related */ + for (i = 0; gp_resources[i].flags != 0; i++) { + if ((gp_resources[i].start != 0) && + ((gp_resources[i].flags & IORESOURCE_IO) != 0)) { + pr_info("reserved platform resource %s at %08x\n", + gp_resources[i].name, gp_resources[i].start); + } + } +} + +/* + * + * PERSISTENT MEMORY (PMEM) CONFIGURATION + * + */ +static unsigned long pmemaddr __initdata; + +static int __init early_param_pmemaddr(char *p) +{ + pmemaddr = (unsigned long)simple_strtoul(p, NULL, 0); + return 0; +} +early_param("pmemaddr", early_param_pmemaddr); + +static long pmemlen __initdata; + +static int __init early_param_pmemlen(char *p) +{ +/* TODO: we can use this code when and if the bootloader ever changes this */ +#if 0 + pmemlen = (unsigned long)simple_strtoul(p, NULL, 0); +#else + pmemlen = 0x20000; +#endif + return 0; +} +early_param("pmemlen", early_param_pmemlen); + +/* + * Set up persistent memory. If we were given values, we patch the array of + * resources. Otherwise, persistent memory may be allocated anywhere at all. + */ +static void __init pmem_setup_resource(void) +{ + struct resource *resource; + resource = asic_resource_get("DiagPersistentMemory"); + + if (resource && pmemaddr && pmemlen) { + /* The address provided by bootloader is in kseg0. Convert to + * a bus address. */ + resource->start = phys_to_bus(pmemaddr - 0x80000000); + resource->end = resource->start + pmemlen - 1; + + pr_info("persistent memory: start=0x%x end=0x%x\n", + resource->start, resource->end); + } +} + +/* + * + * RESOURCE ACCESS FUNCTIONS + * + */ + +/** + * asic_resource_get - retrieves parameters for a platform resource. + * @name: string to match resource + * + * Returns a pointer to a struct resource corresponding to the given name. + * + * CANNOT BE NAMED platform_resource_get, which would be the obvious choice, + * as this function name is already declared + */ +struct resource *asic_resource_get(const char *name) +{ + int i; + + for (i = 0; gp_resources[i].flags != 0; i++) { + if (strcmp(gp_resources[i].name, name) == 0) + return &gp_resources[i]; + } + + return NULL; +} +EXPORT_SYMBOL(asic_resource_get); + +/** + * platform_release_memory - release pre-allocated memory + * @ptr: pointer to memory to release + * @size: size of resource + * + * This must only be called for memory allocated or reserved via the boot + * memory allocator. + */ +void platform_release_memory(void *ptr, int size) +{ + unsigned long addr; + unsigned long end; + + addr = ((unsigned long)ptr + (PAGE_SIZE - 1)) & PAGE_MASK; + end = ((unsigned long)ptr + size) & PAGE_MASK; + + for (; addr < end; addr += PAGE_SIZE) { + ClearPageReserved(virt_to_page(__va(addr))); + init_page_count(virt_to_page(__va(addr))); + free_page((unsigned long)__va(addr)); + } +} +EXPORT_SYMBOL(platform_release_memory); + +/* + * + * FEATURE AVAILABILITY FUNCTIONS + * + */ +int platform_supports_dvr(void) +{ + return (platform_features & DVR_CAPABLE) != 0; +} + +int platform_supports_ffs(void) +{ + return (platform_features & FFS_CAPABLE) != 0; +} + +int platform_supports_pcie(void) +{ + return (platform_features & PCIE_CAPABLE) != 0; +} + +int platform_supports_display(void) +{ + return (platform_features & DISPLAY_CAPABLE) != 0; +} diff --git a/arch/mips/powertv/asic/asic_int.c b/arch/mips/powertv/asic/asic_int.c new file mode 100644 index 0000000..80b2eed --- /dev/null +++ b/arch/mips/powertv/asic/asic_int.c @@ -0,0 +1,125 @@ +/* + * Carsten Langgaard, carstenl@mips.com + * Copyright (C) 2000, 2001, 2004 MIPS Technologies, Inc. + * Copyright (C) 2001 Ralf Baechle + * Portions copyright (C) 2009 Cisco Systems, Inc. + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * Routines for generic manipulation of the interrupts found on the PowerTV + * platform. + * + * The interrupt controller is located in the South Bridge a PIIX4 device + * with two internal 82C95 interrupt controllers. + */ +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include + +static DEFINE_SPINLOCK(asic_irq_lock); + +static inline int get_int(void) +{ + unsigned long flags; + int irq; + + spin_lock_irqsave(&asic_irq_lock, flags); + + irq = (asic_read(int_int_scan) >> 4) - 1; + + if (irq == 0 || irq >= NR_IRQS) + irq = -1; + + spin_unlock_irqrestore(&asic_irq_lock, flags); + + return irq; +} + +static void asic_irqdispatch(void) +{ + int irq; + + irq = get_int(); + if (irq < 0) + return; /* interrupt has already been cleared */ + + do_IRQ(irq); +} + +static inline int clz(unsigned long x) +{ + __asm__( + " .set push \n" + " .set mips32 \n" + " clz %0, %1 \n" + " .set pop \n" + : "=r" (x) + : "r" (x)); + + return x; +} + +/* + * Version of ffs that only looks at bits 12..15. + */ +static inline unsigned int irq_ffs(unsigned int pending) +{ + return fls(pending) - 1 + CAUSEB_IP; +} + +/* + * TODO: check how it works under EIC mode. + */ +asmlinkage void plat_irq_dispatch(void) +{ + unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM; + int irq; + + irq = irq_ffs(pending); + + if (irq == CAUSEF_IP3) + asic_irqdispatch(); + else if (irq >= 0) + do_IRQ(irq); + else + spurious_interrupt(); +} + +void __init arch_init_irq(void) +{ + int i; + + asic_irq_init(); + + /* + * Initialize interrupt exception vectors. + */ + if (cpu_has_veic || cpu_has_vint) { + int nvec = cpu_has_veic ? 64 : 8; + for (i = 0; i < nvec; i++) + set_vi_handler(i, asic_irqdispatch); + } +} diff --git a/arch/mips/powertv/asic/irq_asic.c b/arch/mips/powertv/asic/irq_asic.c new file mode 100644 index 0000000..b54d244 --- /dev/null +++ b/arch/mips/powertv/asic/irq_asic.c @@ -0,0 +1,116 @@ +/* + * Portions copyright (C) 2005-2009 Scientific Atlanta + * Portions copyright (C) 2009 Cisco Systems, Inc. + * + * Modified from arch/mips/kernel/irq-rm7000.c: + * Copyright (C) 2003 Ralf Baechle + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ +#include +#include +#include + +#include +#include +#include + +#include + +static inline void unmask_asic_irq(unsigned int irq) +{ + unsigned long enable_bit; + + enable_bit = (1 << (irq & 0x1f)); + + switch (irq >> 5) { + case 0: + asic_write(asic_read(ien_int_0) | enable_bit, ien_int_0); + break; + case 1: + asic_write(asic_read(ien_int_1) | enable_bit, ien_int_1); + break; + case 2: + asic_write(asic_read(ien_int_2) | enable_bit, ien_int_2); + break; + case 3: + asic_write(asic_read(ien_int_3) | enable_bit, ien_int_3); + break; + default: + BUG(); + } +} + +static inline void mask_asic_irq(unsigned int irq) +{ + unsigned long disable_mask; + + disable_mask = ~(1 << (irq & 0x1f)); + + switch (irq >> 5) { + case 0: + asic_write(asic_read(ien_int_0) & disable_mask, ien_int_0); + break; + case 1: + asic_write(asic_read(ien_int_1) & disable_mask, ien_int_1); + break; + case 2: + asic_write(asic_read(ien_int_2) & disable_mask, ien_int_2); + break; + case 3: + asic_write(asic_read(ien_int_3) & disable_mask, ien_int_3); + break; + default: + BUG(); + } +} + +static struct irq_chip asic_irq_chip = { + .name = "ASIC Level", + .ack = mask_asic_irq, + .mask = mask_asic_irq, + .mask_ack = mask_asic_irq, + .unmask = unmask_asic_irq, + .eoi = unmask_asic_irq, +}; + +void __init asic_irq_init(void) +{ + int i; + + /* set priority to 0 */ + write_c0_status(read_c0_status() & ~(0x0000fc00)); + + asic_write(0, ien_int_0); + asic_write(0, ien_int_1); + asic_write(0, ien_int_2); + asic_write(0, ien_int_3); + + asic_write(0x0fffffff, int_level_3_3); + asic_write(0xffffffff, int_level_3_2); + asic_write(0xffffffff, int_level_3_1); + asic_write(0xffffffff, int_level_3_0); + asic_write(0xffffffff, int_level_2_3); + asic_write(0xffffffff, int_level_2_2); + asic_write(0xffffffff, int_level_2_1); + asic_write(0xffffffff, int_level_2_0); + asic_write(0xffffffff, int_level_1_3); + asic_write(0xffffffff, int_level_1_2); + asic_write(0xffffffff, int_level_1_1); + asic_write(0xffffffff, int_level_1_0); + asic_write(0xffffffff, int_level_0_3); + asic_write(0xffffffff, int_level_0_2); + asic_write(0xffffffff, int_level_0_1); + asic_write(0xffffffff, int_level_0_0); + + asic_write(0xf, int_int_scan); + + /* + * Initialize interrupt handlers. + */ + for (i = 0; i < NR_IRQS; i++) + set_irq_chip_and_handler(i, &asic_irq_chip, handle_level_irq); +} diff --git a/arch/mips/powertv/asic/prealloc-calliope.c b/arch/mips/powertv/asic/prealloc-calliope.c new file mode 100644 index 0000000..0384201 --- /dev/null +++ b/arch/mips/powertv/asic/prealloc-calliope.c @@ -0,0 +1,622 @@ +/* + * prealloc-calliope.c + * + * Memory pre-allocations for Calliope boxes. + * + * Copyright (C) 2005-2009 Scientific-Atlanta, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + * Author: Ken Eppinett + * David Schleef + */ + +#include +#include + +/* + * NON_DVR_CAPABLE CALLIOPE RESOURCES + */ +struct resource non_dvr_calliope_resources[] __initdata = +{ + /* + * VIDEO / LX1 + */ + { + .name = "ST231aImage", /* Delta-Mu 1 image and ram */ + .start = 0x24000000, + .end = 0x24200000 - 1, /*2MiB */ + .flags = IORESOURCE_MEM, + }, + { + .name = "ST231aMonitor", /*8KiB block ST231a monitor */ + .start = 0x24200000, + .end = 0x24202000 - 1, + .flags = IORESOURCE_MEM, + }, + { + .name = "MediaMemory1", + .start = 0x24202000, + .end = 0x26700000 - 1, /*~36.9MiB (32MiB - (2MiB + 8KiB)) */ + .flags = IORESOURCE_MEM, + }, + /* + * Sysaudio Driver + */ + { + .name = "DSP_Image_Buff", + .start = 0x00000000, + .end = 0x000FFFFF, + .flags = IORESOURCE_MEM, + }, + { + .name = "ADSC_CPU_PCM_Buff", + .start = 0x00000000, + .end = 0x00009FFF, + .flags = IORESOURCE_MEM, + }, + { + .name = "ADSC_AUX_Buff", + .start = 0x00000000, + .end = 0x00003FFF, + .flags = IORESOURCE_MEM, + }, + { + .name = "ADSC_Main_Buff", + .start = 0x00000000, + .end = 0x00003FFF, + .flags = IORESOURCE_MEM, + }, + /* + * STAVEM driver/STAPI + */ + { + .name = "AVMEMPartition0", + .start = 0x00000000, + .end = 0x00600000 - 1, /* 6 MB total */ + .flags = IORESOURCE_MEM, + }, + /* + * DOCSIS Subsystem + */ + { + .name = "Docsis", + .start = 0x22000000, + .end = 0x22700000 - 1, + .flags = IORESOURCE_MEM, + }, + /* + * GHW HAL Driver + */ + { + .name = "GraphicsHeap", + .start = 0x22700000, + .end = 0x23500000 - 1, /* 14 MB total */ + .flags = IORESOURCE_MEM, + }, + /* + * multi com buffer area + */ + { + .name = "MulticomSHM", + .start = 0x23700000, + .end = 0x23720000 - 1, + .flags = IORESOURCE_MEM, + }, + /* + * DMA Ring buffer (don't need recording buffers) + */ + { + .name = "BMM_Buffer", + .start = 0x00000000, + .end = 0x000AA000 - 1, + .flags = IORESOURCE_MEM, + }, + /* + * Display bins buffer for unit0 + */ + { + .name = "DisplayBins0", + .start = 0x00000000, + .end = 0x00000FFF, /* 4 KB total */ + .flags = IORESOURCE_MEM, + }, + /* + * + * AVFS: player HAL memory + * + * + */ + { + .name = "AvfsDmaMem", + .start = 0x00000000, + .end = 0x002c4c00 - 1, /* 945K * 3 for playback */ + .flags = IORESOURCE_MEM, + }, + /* + * PMEM + */ + { + .name = "DiagPersistentMemory", + .start = 0x00000000, + .end = 0x10000 - 1, + .flags = IORESOURCE_MEM, + }, + /* + * Smartcard + */ + { + .name = "SmartCardInfo", + .start = 0x00000000, + .end = 0x2800 - 1, + .flags = IORESOURCE_MEM, + }, + /* + * NAND Flash + */ + { + .name = "NandFlash", + .start = NAND_FLASH_BASE, + .end = NAND_FLASH_BASE + 0x400 - 1, + .flags = IORESOURCE_IO, + }, + /* + * Synopsys GMAC Memory Region + */ + { + .name = "GMAC", + .start = 0x00000000, + .end = 0x00010000 - 1, + .flags = IORESOURCE_MEM, + }, + /* + * Add other resources here + * + */ + { }, +}; + +struct resource non_dvr_vz_calliope_resources[] __initdata = +{ + /* + * VIDEO / LX1 + */ + { + .name = "ST231aImage", /* Delta-Mu 1 image and ram */ + .start = 0x24000000, + .end = 0x24200000 - 1, /*2 Meg */ + .flags = IORESOURCE_MEM, + }, + { + .name = "ST231aMonitor", /* 8k block ST231a monitor */ + .start = 0x24200000, + .end = 0x24202000 - 1, + .flags = IORESOURCE_MEM, + }, + { + .name = "MediaMemory1", + .start = 0x22202000, + .end = 0x22C20B85 - 1, /* 10.12 Meg */ + .flags = IORESOURCE_MEM, + }, + /* + * Sysaudio Driver + */ + { + .name = "DSP_Image_Buff", + .start = 0x00000000, + .end = 0x000FFFFF, + .flags = IORESOURCE_MEM, + }, + { + .name = "ADSC_CPU_PCM_Buff", + .start = 0x00000000, + .end = 0x00009FFF, + .flags = IORESOURCE_MEM, + }, + { + .name = "ADSC_AUX_Buff", + .start = 0x00000000, + .end = 0x00003FFF, + .flags = IORESOURCE_MEM, + }, + { + .name = "ADSC_Main_Buff", + .start = 0x00000000, + .end = 0x00003FFF, + .flags = IORESOURCE_MEM, + }, + /* + * STAVEM driver/STAPI + */ + { + .name = "AVMEMPartition0", + .start = 0x20300000, + .end = 0x20620000-1, /*3.125 MB total */ + .flags = IORESOURCE_MEM, + }, + /* + * GHW HAL Driver + */ + { + .name = "GraphicsHeap", + .start = 0x20100000, + .end = 0x20300000 - 1, + .flags = IORESOURCE_MEM, + }, + /* + * multi com buffer area + */ + { + .name = "MulticomSHM", + .start = 0x23900000, + .end = 0x23920000 - 1, + .flags = IORESOURCE_MEM, + }, + /* + * DMA Ring buffer + */ + { + .name = "BMM_Buffer", + .start = 0x00000000, + .end = 0x000AA000 - 1, + .flags = IORESOURCE_MEM, + }, + /* + * Display bins buffer for unit0 + */ + { + .name = "DisplayBins0", + .start = 0x00000000, + .end = 0x00000FFF, + .flags = IORESOURCE_MEM, + }, + /* + * PMEM + */ + { + .name = "DiagPersistentMemory", + .start = 0x00000000, + .end = 0x10000 - 1, + .flags = IORESOURCE_MEM, + }, + /* + * Smartcard + */ + { + .name = "SmartCardInfo", + .start = 0x00000000, + .end = 0x2800 - 1, + .flags = IORESOURCE_MEM, + }, + /* + * NAND Flash + */ + { + .name = "NandFlash", + .start = NAND_FLASH_BASE, + .end = NAND_FLASH_BASE+0x400 - 1, + .flags = IORESOURCE_IO, + }, + /* + * Synopsys GMAC Memory Region + */ + { + .name = "GMAC", + .start = 0x00000000, + .end = 0x00010000 - 1, + .flags = IORESOURCE_MEM, + }, + /* + * Add other resources here + */ + { }, +}; + +struct resource non_dvr_vze_calliope_resources[] __initdata = +{ + /* + * VIDEO / LX1 + */ + { + .name = "ST231aImage", /* Delta-Mu 1 image and ram */ + .start = 0x22000000, + .end = 0x22200000 - 1, /*2 Meg */ + .flags = IORESOURCE_MEM, + }, + { + .name = "ST231aMonitor", /* 8k block ST231a monitor */ + .start = 0x22200000, + .end = 0x22202000 - 1, + .flags = IORESOURCE_MEM, + }, + { + .name = "MediaMemory1", + .start = 0x22202000, + .end = 0x22C20B85 - 1, /* 10.12 Meg */ + .flags = IORESOURCE_MEM, + }, + /* + * Sysaudio Driver + */ + { + .name = "DSP_Image_Buff", + .start = 0x00000000, + .end = 0x000FFFFF, + .flags = IORESOURCE_MEM, + }, + { + .name = "ADSC_CPU_PCM_Buff", + .start = 0x00000000, + .end = 0x00009FFF, + .flags = IORESOURCE_MEM, + }, + { + .name = "ADSC_AUX_Buff", + .start = 0x00000000, + .end = 0x00003FFF, + .flags = IORESOURCE_MEM, + }, + { + .name = "ADSC_Main_Buff", + .start = 0x00000000, + .end = 0x00003FFF, + .flags = IORESOURCE_MEM, + }, + /* + * STAVEM driver/STAPI + */ + { + .name = "AVMEMPartition0", + .start = 0x20396000, + .end = 0x206B6000 - 1, /* 3.125 MB total */ + .flags = IORESOURCE_MEM, + }, + /* + * GHW HAL Driver + */ + { + .name = "GraphicsHeap", + .start = 0x20100000, + .end = 0x20396000 - 1, + .flags = IORESOURCE_MEM, + }, + /* + * multi com buffer area + */ + { + .name = "MulticomSHM", + .start = 0x206B6000, + .end = 0x206D6000 - 1, + .flags = IORESOURCE_MEM, + }, + /* + * DMA Ring buffer + */ + { + .name = "BMM_Buffer", + .start = 0x00000000, + .end = 0x000AA000 - 1, + .flags = IORESOURCE_MEM, + }, + /* + * Display bins buffer for unit0 + */ + { + .name = "DisplayBins0", + .start = 0x00000000, + .end = 0x00000FFF, + .flags = IORESOURCE_MEM, + }, + /* + * PMEM + */ + { + .name = "DiagPersistentMemory", + .start = 0x00000000, + .end = 0x10000 - 1, + .flags = IORESOURCE_MEM, + }, + /* + * Smartcard + */ + { + .name = "SmartCardInfo", + .start = 0x00000000, + .end = 0x2800 - 1, + .flags = IORESOURCE_MEM, + }, + /* + * NAND Flash + */ + { + .name = "NandFlash", + .start = NAND_FLASH_BASE, + .end = NAND_FLASH_BASE+0x400 - 1, + .flags = IORESOURCE_MEM, + }, + /* + * Synopsys GMAC Memory Region + */ + { + .name = "GMAC", + .start = 0x00000000, + .end = 0x00010000 - 1, + .flags = IORESOURCE_MEM, + }, + /* + * Add other resources here + */ + { }, +}; + +struct resource non_dvr_vzf_calliope_resources[] __initdata = +{ + /* + * VIDEO / LX1 + */ + { + .name = "ST231aImage", /*Delta-Mu 1 image and ram */ + .start = 0x24000000, + .end = 0x24200000 - 1, /*2MiB */ + .flags = IORESOURCE_MEM, + }, + { + .name = "ST231aMonitor", /*8KiB block ST231a monitor */ + .start = 0x24200000, + .end = 0x24202000 - 1, + .flags = IORESOURCE_MEM, + }, + { + .name = "MediaMemory1", + .start = 0x24202000, + /* ~19.4 (21.5MiB - (2MiB + 8KiB)) */ + .end = 0x25580000 - 1, + .flags = IORESOURCE_MEM, + }, + /* + * Sysaudio Driver + */ + { + .name = "DSP_Image_Buff", + .start = 0x00000000, + .end = 0x000FFFFF, + .flags = IORESOURCE_MEM, + }, + { + .name = "ADSC_CPU_PCM_Buff", + .start = 0x00000000, + .end = 0x00009FFF, + .flags = IORESOURCE_MEM, + }, + { + .name = "ADSC_AUX_Buff", + .start = 0x00000000, + .end = 0x00003FFF, + .flags = IORESOURCE_MEM, + }, + { + .name = "ADSC_Main_Buff", + .start = 0x00000000, + .end = 0x00003FFF, + .flags = IORESOURCE_MEM, + }, + /* + * STAVEM driver/STAPI + */ + { + .name = "AVMEMPartition0", + .start = 0x00000000, + .end = 0x00480000 - 1, /* 4.5 MB total */ + .flags = IORESOURCE_MEM, + }, + /* + * GHW HAL Driver + */ + { + .name = "GraphicsHeap", + .start = 0x22700000, + .end = 0x23500000 - 1, /* 14 MB total */ + .flags = IORESOURCE_MEM, + }, + /* + * multi com buffer area + */ + { + .name = "MulticomSHM", + .start = 0x23700000, + .end = 0x23720000 - 1, + .flags = IORESOURCE_MEM, + }, + /* + * DMA Ring buffer (don't need recording buffers) + */ + { + .name = "BMM_Buffer", + .start = 0x00000000, + .end = 0x000AA000 - 1, + .flags = IORESOURCE_MEM, + }, + /* + * Display bins buffer for unit0 + */ + { + .name = "DisplayBins0", + .start = 0x00000000, + .end = 0x00000FFF, /* 4 KB total */ + .flags = IORESOURCE_MEM, + }, + /* + * Display bins buffer for unit1 + */ + { + .name = "DisplayBins1", + .start = 0x00000000, + .end = 0x00000FFF, /* 4 KB total */ + .flags = IORESOURCE_MEM, + }, + /* + * + * AVFS: player HAL memory + * + * + */ + { + .name = "AvfsDmaMem", + .start = 0x00000000, + .end = 0x002c4c00 - 1, /* 945K * 3 for playback */ + .flags = IORESOURCE_MEM, + }, + /* + * PMEM + */ + { + .name = "DiagPersistentMemory", + .start = 0x00000000, + .end = 0x10000 - 1, + .flags = IORESOURCE_MEM, + }, + /* + * Smartcard + */ + { + .name = "SmartCardInfo", + .start = 0x00000000, + .end = 0x2800 - 1, + .flags = IORESOURCE_MEM, + }, + /* + * NAND Flash + */ + { + .name = "NandFlash", + .start = NAND_FLASH_BASE, + .end = NAND_FLASH_BASE + 0x400 - 1, + .flags = IORESOURCE_MEM, + }, + /* + * Synopsys GMAC Memory Region + */ + { + .name = "GMAC", + .start = 0x00000000, + .end = 0x00010000 - 1, + .flags = IORESOURCE_MEM, + }, + /* + * Add other resources here + */ + { }, +}; diff --git a/arch/mips/powertv/asic/prealloc-cronus.c b/arch/mips/powertv/asic/prealloc-cronus.c new file mode 100644 index 0000000..4435286 --- /dev/null +++ b/arch/mips/powertv/asic/prealloc-cronus.c @@ -0,0 +1,610 @@ +/* + * prealloc-cronus.c + * + * Memory pre-allocations for Cronus boxes. + * + * Copyright (C) 2005-2009 Scientific-Atlanta, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + * Author: Ken Eppinett + * David Schleef + */ + +#include +#include + +/* + * DVR_CAPABLE CRONUS RESOURCES + */ +struct resource dvr_cronus_resources[] __initdata = +{ + /* + * + * VIDEO1 / LX1 + * + */ + { + .name = "ST231aImage", /* Delta-Mu 1 image and ram */ + .start = 0x24000000, + .end = 0x241FFFFF, /* 2MiB */ + .flags = IORESOURCE_MEM, + }, + { + .name = "ST231aMonitor", /* 8KiB block ST231a monitor */ + .start = 0x24200000, + .end = 0x24201FFF, + .flags = IORESOURCE_MEM, + }, + { + .name = "MediaMemory1", + .start = 0x24202000, + .end = 0x25FFFFFF, /*~29.9MiB (32MiB - (2MiB + 8KiB)) */ + .flags = IORESOURCE_MEM, + }, + /* + * + * VIDEO2 / LX2 + * + */ + { + .name = "ST231bImage", /* Delta-Mu 2 image and ram */ + .start = 0x60000000, + .end = 0x601FFFFF, /* 2MiB */ + .flags = IORESOURCE_IO, + }, + { + .name = "ST231bMonitor", /* 8KiB block ST231b monitor */ + .start = 0x60200000, + .end = 0x60201FFF, + .flags = IORESOURCE_IO, + }, + { + .name = "MediaMemory2", + .start = 0x60202000, + .end = 0x61FFFFFF, /*~29.9MiB (32MiB - (2MiB + 8KiB)) */ + .flags = IORESOURCE_IO, + }, + /* + * + * Sysaudio Driver + * + * This driver requires: + * + * Arbitrary Based Buffers: + * DSP_Image_Buff - DSP code and data images (1MB) + * ADSC_CPU_PCM_Buff - ADSC CPU PCM buffer (40KB) + * ADSC_AUX_Buff - ADSC AUX buffer (16KB) + * ADSC_Main_Buff - ADSC Main buffer (16KB) + * + */ + { + .name = "DSP_Image_Buff", + .start = 0x00000000, + .end = 0x000FFFFF, + .flags = IORESOURCE_MEM, + }, + { + .name = "ADSC_CPU_PCM_Buff", + .start = 0x00000000, + .end = 0x00009FFF, + .flags = IORESOURCE_MEM, + }, + { + .name = "ADSC_AUX_Buff", + .start = 0x00000000, + .end = 0x00003FFF, + .flags = IORESOURCE_MEM, + }, + { + .name = "ADSC_Main_Buff", + .start = 0x00000000, + .end = 0x00003FFF, + .flags = IORESOURCE_MEM, + }, + /* + * + * STAVEM driver/STAPI + * + * This driver requires: + * + * Arbitrary Based Buffers: + * This memory area is used for allocating buffers for Video decoding + * purposes. Allocation/De-allocation within this buffer is managed + * by the STAVMEM driver of the STAPI. They could be Decimated + * Picture Buffers, Intermediate Buffers, as deemed necessary for + * video decoding purposes, for any video decoders on Zeus. + * + */ + { + .name = "AVMEMPartition0", + .start = 0x63580000, + .end = 0x64180000 - 1, /* 12 MB total */ + .flags = IORESOURCE_IO, + }, + /* + * + * DOCSIS Subsystem + * + * This driver requires: + * + * Arbitrary Based Buffers: + * Docsis - + * + */ + { + .name = "Docsis", + .start = 0x62000000, + .end = 0x62700000 - 1, /* 7 MB total */ + .flags = IORESOURCE_IO, + }, + /* + * + * GHW HAL Driver + * + * This driver requires: + * + * Arbitrary Based Buffers: + * GraphicsHeap - PowerTV Graphics Heap + * + */ + { + .name = "GraphicsHeap", + .start = 0x62700000, + .end = 0x63500000 - 1, /* 14 MB total */ + .flags = IORESOURCE_IO, + }, + /* + * + * multi com buffer area + * + * This driver requires: + * + * Arbitrary Based Buffers: + * Docsis - + * + */ + { + .name = "MulticomSHM", + .start = 0x26000000, + .end = 0x26020000 - 1, + .flags = IORESOURCE_MEM, + }, + /* + * + * DMA Ring buffer + * + * This driver requires: + * + * Arbitrary Based Buffers: + * Docsis - + * + */ + { + .name = "BMM_Buffer", + .start = 0x00000000, + .end = 0x00280000 - 1, + .flags = IORESOURCE_MEM, + }, + /* + * + * Display bins buffer for unit0 + * + * This driver requires: + * + * Arbitrary Based Buffers: + * Display Bins for unit0 + * + */ + { + .name = "DisplayBins0", + .start = 0x00000000, + .end = 0x00000FFF, /* 4 KB total */ + .flags = IORESOURCE_MEM, + }, + /* + * + * Display bins buffer + * + * This driver requires: + * + * Arbitrary Based Buffers: + * Display Bins for unit1 + * + */ + { + .name = "DisplayBins1", + .start = 0x64AD4000, + .end = 0x64AD5000 - 1, /* 4 KB total */ + .flags = IORESOURCE_IO, + }, + /* + * + * ITFS + * + * This driver requires: + * + * Arbitrary Based Buffers: + * Docsis - + * + */ + { + .name = "ITFS", + .start = 0x64180000, + /* 815,104 bytes each for 2 ITFS partitions. */ + .end = 0x6430DFFF, + .flags = IORESOURCE_IO, + }, + /* + * + * AVFS + * + * This driver requires: + * + * Arbitrary Based Buffers: + * Docsis - + * + */ + { + .name = "AvfsDmaMem", + .start = 0x6430E000, + /* (945K * 8) = (128K *3) 5 playbacks / 3 server */ + .end = 0x64AD0000 - 1, + .flags = IORESOURCE_IO, + }, + { + .name = "AvfsFileSys", + .start = 0x64AD0000, + .end = 0x64AD1000 - 1, /* 4K */ + .flags = IORESOURCE_IO, + }, + /* + * + * PMEM + * + * This driver requires: + * + * Arbitrary Based Buffers: + * Persistent memory for diagnostics. + * + */ + { + .name = "DiagPersistentMemory", + .start = 0x00000000, + .end = 0x10000 - 1, + .flags = IORESOURCE_MEM, + }, + /* + * + * Smartcard + * + * This driver requires: + * + * Arbitrary Based Buffers: + * Read and write buffers for Internal/External cards + * + */ + { + .name = "SmartCardInfo", + .start = 0x64AD1000, + .end = 0x64AD3800 - 1, + .flags = IORESOURCE_IO, + }, + /* + * + * KAVNET + * NP Reset Vector - must be of the form xxCxxxxx + * NP Image - must be video bank 1 + * NP IPC - must be video bank 2 + */ + { + .name = "NP_Reset_Vector", + .start = 0x27c00000, + .end = 0x27c01000 - 1, + .flags = IORESOURCE_MEM, + }, + { + .name = "NP_Image", + .start = 0x27020000, + .end = 0x27060000 - 1, + .flags = IORESOURCE_MEM, + }, + { + .name = "NP_IPC", + .start = 0x63500000, + .end = 0x63580000 - 1, + .flags = IORESOURCE_IO, + }, + /* + * Add other resources here + */ + { }, +}; + +/* + * NON_DVR_CAPABLE CRONUS RESOURCES + */ +struct resource non_dvr_cronus_resources[] __initdata = +{ + /* + * + * VIDEO1 / LX1 + * + */ + { + .name = "ST231aImage", /* Delta-Mu 1 image and ram */ + .start = 0x24000000, + .end = 0x241FFFFF, /* 2MiB */ + .flags = IORESOURCE_MEM, + }, + { + .name = "ST231aMonitor", /* 8KiB block ST231a monitor */ + .start = 0x24200000, + .end = 0x24201FFF, + .flags = IORESOURCE_MEM, + }, + { + .name = "MediaMemory1", + .start = 0x24202000, + .end = 0x25FFFFFF, /*~29.9MiB (32MiB - (2MiB + 8KiB)) */ + .flags = IORESOURCE_MEM, + }, + /* + * + * VIDEO2 / LX2 + * + */ + { + .name = "ST231bImage", /* Delta-Mu 2 image and ram */ + .start = 0x60000000, + .end = 0x601FFFFF, /* 2MiB */ + .flags = IORESOURCE_IO, + }, + { + .name = "ST231bMonitor", /* 8KiB block ST231b monitor */ + .start = 0x60200000, + .end = 0x60201FFF, + .flags = IORESOURCE_IO, + }, + { + .name = "MediaMemory2", + .start = 0x60202000, + .end = 0x61FFFFFF, /*~29.9MiB (32MiB - (2MiB + 8KiB)) */ + .flags = IORESOURCE_IO, + }, + /* + * + * Sysaudio Driver + * + * This driver requires: + * + * Arbitrary Based Buffers: + * DSP_Image_Buff - DSP code and data images (1MB) + * ADSC_CPU_PCM_Buff - ADSC CPU PCM buffer (40KB) + * ADSC_AUX_Buff - ADSC AUX buffer (16KB) + * ADSC_Main_Buff - ADSC Main buffer (16KB) + * + */ + { + .name = "DSP_Image_Buff", + .start = 0x00000000, + .end = 0x000FFFFF, + .flags = IORESOURCE_MEM, + }, + { + .name = "ADSC_CPU_PCM_Buff", + .start = 0x00000000, + .end = 0x00009FFF, + .flags = IORESOURCE_MEM, + }, + { + .name = "ADSC_AUX_Buff", + .start = 0x00000000, + .end = 0x00003FFF, + .flags = IORESOURCE_MEM, + }, + { + .name = "ADSC_Main_Buff", + .start = 0x00000000, + .end = 0x00003FFF, + .flags = IORESOURCE_MEM, + }, + /* + * + * STAVEM driver/STAPI + * + * This driver requires: + * + * Arbitrary Based Buffers: + * This memory area is used for allocating buffers for Video decoding + * purposes. Allocation/De-allocation within this buffer is managed + * by the STAVMEM driver of the STAPI. They could be Decimated + * Picture Buffers, Intermediate Buffers, as deemed necessary for + * video decoding purposes, for any video decoders on Zeus. + * + */ + { + .name = "AVMEMPartition0", + .start = 0x63580000, + .end = 0x64180000 - 1, /* 12 MB total */ + .flags = IORESOURCE_IO, + }, + /* + * + * DOCSIS Subsystem + * + * This driver requires: + * + * Arbitrary Based Buffers: + * Docsis - + * + */ + { + .name = "Docsis", + .start = 0x62000000, + .end = 0x62700000 - 1, /* 7 MB total */ + .flags = IORESOURCE_IO, + }, + /* + * + * GHW HAL Driver + * + * This driver requires: + * + * Arbitrary Based Buffers: + * GraphicsHeap - PowerTV Graphics Heap + * + */ + { + .name = "GraphicsHeap", + .start = 0x62700000, + .end = 0x63500000 - 1, /* 14 MB total */ + .flags = IORESOURCE_IO, + }, + /* + * + * multi com buffer area + * + * This driver requires: + * + * Arbitrary Based Buffers: + * Docsis - + * + */ + { + .name = "MulticomSHM", + .start = 0x26000000, + .end = 0x26020000 - 1, + .flags = IORESOURCE_MEM, + }, + /* + * + * DMA Ring buffer + * + * This driver requires: + * + * Arbitrary Based Buffers: + * Docsis - + * + */ + { + .name = "BMM_Buffer", + .start = 0x00000000, + .end = 0x000AA000 - 1, + .flags = IORESOURCE_MEM, + }, + /* + * + * Display bins buffer for unit0 + * + * This driver requires: + * + * Arbitrary Based Buffers: + * Display Bins for unit0 + * + */ + { + .name = "DisplayBins0", + .start = 0x00000000, + .end = 0x00000FFF, /* 4 KB total */ + .flags = IORESOURCE_MEM, + }, + /* + * + * Display bins buffer + * + * This driver requires: + * + * Arbitrary Based Buffers: + * Display Bins for unit1 + * + */ + { + .name = "DisplayBins1", + .start = 0x64AD4000, + .end = 0x64AD5000 - 1, /* 4 KB total */ + .flags = IORESOURCE_IO, + }, + /* + * + * AVFS: player HAL memory + * + * + */ + { + .name = "AvfsDmaMem", + .start = 0x6430E000, + .end = 0x645D2C00 - 1, /* 945K * 3 for playback */ + .flags = IORESOURCE_IO, + }, + /* + * + * PMEM + * + * This driver requires: + * + * Arbitrary Based Buffers: + * Persistent memory for diagnostics. + * + */ + { + .name = "DiagPersistentMemory", + .start = 0x00000000, + .end = 0x10000 - 1, + .flags = IORESOURCE_MEM, + }, + /* + * + * Smartcard + * + * This driver requires: + * + * Arbitrary Based Buffers: + * Read and write buffers for Internal/External cards + * + */ + { + .name = "SmartCardInfo", + .start = 0x64AD1000, + .end = 0x64AD3800 - 1, + .flags = IORESOURCE_IO, + }, + /* + * + * KAVNET + * NP Reset Vector - must be of the form xxCxxxxx + * NP Image - must be video bank 1 + * NP IPC - must be video bank 2 + */ + { + .name = "NP_Reset_Vector", + .start = 0x27c00000, + .end = 0x27c01000 - 1, + .flags = IORESOURCE_MEM, + }, + { + .name = "NP_Image", + .start = 0x27020000, + .end = 0x27060000 - 1, + .flags = IORESOURCE_MEM, + }, + { + .name = "NP_IPC", + .start = 0x63500000, + .end = 0x63580000 - 1, + .flags = IORESOURCE_IO, + }, + { }, +}; diff --git a/arch/mips/powertv/asic/prealloc-cronuslite.c b/arch/mips/powertv/asic/prealloc-cronuslite.c new file mode 100644 index 0000000..2aaedd9 --- /dev/null +++ b/arch/mips/powertv/asic/prealloc-cronuslite.c @@ -0,0 +1,292 @@ +/* + * prealloc-cronuslite.c + * + * Memory pre-allocations for Cronus Lite boxes. + * + * Copyright (C) 2005-2009 Scientific-Atlanta, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + * Author: Ken Eppinett + * David Schleef + */ + +#include +#include + +/* + * NON_DVR_CAPABLE CRONUSLITE RESOURCES + */ +struct resource non_dvr_cronuslite_resources[] __initdata = +{ + /* + * + * VIDEO2 / LX2 + * + */ + { + .name = "ST231aImage", /* Delta-Mu 2 image and ram */ + .start = 0x60000000, + .end = 0x601FFFFF, /* 2MiB */ + .flags = IORESOURCE_IO, + }, + { + .name = "ST231aMonitor", /* 8KiB block ST231b monitor */ + .start = 0x60200000, + .end = 0x60201FFF, + .flags = IORESOURCE_IO, + }, + { + .name = "MediaMemory1", + .start = 0x60202000, + .end = 0x61FFFFFF, /*~29.9MiB (32MiB - (2MiB + 8KiB)) */ + .flags = IORESOURCE_IO, + }, + /* + * + * Sysaudio Driver + * + * This driver requires: + * + * Arbitrary Based Buffers: + * DSP_Image_Buff - DSP code and data images (1MB) + * ADSC_CPU_PCM_Buff - ADSC CPU PCM buffer (40KB) + * ADSC_AUX_Buff - ADSC AUX buffer (16KB) + * ADSC_Main_Buff - ADSC Main buffer (16KB) + * + */ + { + .name = "DSP_Image_Buff", + .start = 0x00000000, + .end = 0x000FFFFF, + .flags = IORESOURCE_MEM, + }, + { + .name = "ADSC_CPU_PCM_Buff", + .start = 0x00000000, + .end = 0x00009FFF, + .flags = IORESOURCE_MEM, + }, + { + .name = "ADSC_AUX_Buff", + .start = 0x00000000, + .end = 0x00003FFF, + .flags = IORESOURCE_MEM, + }, + { + .name = "ADSC_Main_Buff", + .start = 0x00000000, + .end = 0x00003FFF, + .flags = IORESOURCE_MEM, + }, + /* + * + * STAVEM driver/STAPI + * + * This driver requires: + * + * Arbitrary Based Buffers: + * This memory area is used for allocating buffers for Video decoding + * purposes. Allocation/De-allocation within this buffer is managed + * by the STAVMEM driver of the STAPI. They could be Decimated + * Picture Buffers, Intermediate Buffers, as deemed necessary for + * video decoding purposes, for any video decoders on Zeus. + * + */ + { + .name = "AVMEMPartition0", + .start = 0x63580000, + .end = 0x63B80000 - 1, /* 6 MB total */ + .flags = IORESOURCE_IO, + }, + /* + * + * DOCSIS Subsystem + * + * This driver requires: + * + * Arbitrary Based Buffers: + * Docsis - + * + */ + { + .name = "Docsis", + .start = 0x62000000, + .end = 0x62700000 - 1, /* 7 MB total */ + .flags = IORESOURCE_IO, + }, + /* + * + * GHW HAL Driver + * + * This driver requires: + * + * Arbitrary Based Buffers: + * GraphicsHeap - PowerTV Graphics Heap + * + */ + { + .name = "GraphicsHeap", + .start = 0x62700000, + .end = 0x63500000 - 1, /* 14 MB total */ + .flags = IORESOURCE_IO, + }, + /* + * + * multi com buffer area + * + * This driver requires: + * + * Arbitrary Based Buffers: + * Docsis - + * + */ + { + .name = "MulticomSHM", + .start = 0x26000000, + .end = 0x26020000 - 1, + .flags = IORESOURCE_MEM, + }, + /* + * + * DMA Ring buffer + * + * This driver requires: + * + * Arbitrary Based Buffers: + * Docsis - + * + */ + { + .name = "BMM_Buffer", + .start = 0x00000000, + .end = 0x000AA000 - 1, + .flags = IORESOURCE_MEM, + }, + /* + * + * Display bins buffer for unit0 + * + * This driver requires: + * + * Arbitrary Based Buffers: + * Display Bins for unit0 + * + */ + { + .name = "DisplayBins0", + .start = 0x00000000, + .end = 0x00000FFF, /* 4 KB total */ + .flags = IORESOURCE_MEM, + }, + /* + * + * Display bins buffer + * + * This driver requires: + * + * Arbitrary Based Buffers: + * Display Bins for unit1 + * + */ + { + .name = "DisplayBins1", + .start = 0x63B83000, + .end = 0x63B84000 - 1, /* 4 KB total */ + .flags = IORESOURCE_IO, + }, + /* + * + * AVFS: player HAL memory + * + * + */ + { + .name = "AvfsDmaMem", + .start = 0x63B84000, + .end = 0x63E48C00 - 1, /* 945K * 3 for playback */ + .flags = IORESOURCE_IO, + }, + /* + * + * PMEM + * + * This driver requires: + * + * Arbitrary Based Buffers: + * Persistent memory for diagnostics. + * + */ + { + .name = "DiagPersistentMemory", + .start = 0x00000000, + .end = 0x10000 - 1, + .flags = IORESOURCE_MEM, + }, + /* + * + * Smartcard + * + * This driver requires: + * + * Arbitrary Based Buffers: + * Read and write buffers for Internal/External cards + * + */ + { + .name = "SmartCardInfo", + .start = 0x63B80000, + .end = 0x63B82800 - 1, + .flags = IORESOURCE_IO, + }, + /* + * + * KAVNET + * NP Reset Vector - must be of the form xxCxxxxx + * NP Image - must be video bank 1 + * NP IPC - must be video bank 2 + */ + { + .name = "NP_Reset_Vector", + .start = 0x27c00000, + .end = 0x27c01000 - 1, + .flags = IORESOURCE_MEM, + }, + { + .name = "NP_Image", + .start = 0x27020000, + .end = 0x27060000 - 1, + .flags = IORESOURCE_MEM, + }, + { + .name = "NP_IPC", + .start = 0x63500000, + .end = 0x63580000 - 1, + .flags = IORESOURCE_IO, + }, + /* + * NAND Flash + */ + { + .name = "NandFlash", + .start = NAND_FLASH_BASE, + .end = NAND_FLASH_BASE + 0x400 - 1, + .flags = IORESOURCE_IO, + }, + /* + * Add other resources here + */ + { }, +}; diff --git a/arch/mips/powertv/asic/prealloc-zeus.c b/arch/mips/powertv/asic/prealloc-zeus.c new file mode 100644 index 0000000..59c79f6 --- /dev/null +++ b/arch/mips/powertv/asic/prealloc-zeus.c @@ -0,0 +1,461 @@ +/* + * prealloc-zeus.c + * + * Memory pre-allocations for Zeus boxes. + * + * Copyright (C) 2005-2009 Scientific-Atlanta, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + * Author: Ken Eppinett + * David Schleef + */ + +#include +#include + +/* + * DVR_CAPABLE RESOURCES + */ +struct resource dvr_zeus_resources[] __initdata = +{ + /* + * + * VIDEO1 / LX1 + * + */ + { + .name = "ST231aImage", /* Delta-Mu 1 image and ram */ + .start = 0x20000000, + .end = 0x201FFFFF, /* 2MiB */ + .flags = IORESOURCE_IO, + }, + { + .name = "ST231aMonitor", /* 8KiB block ST231a monitor */ + .start = 0x20200000, + .end = 0x20201FFF, + .flags = IORESOURCE_IO, + }, + { + .name = "MediaMemory1", + .start = 0x20202000, + .end = 0x21FFFFFF, /*~29.9MiB (32MiB - (2MiB + 8KiB)) */ + .flags = IORESOURCE_IO, + }, + /* + * + * VIDEO2 / LX2 + * + */ + { + .name = "ST231bImage", /* Delta-Mu 2 image and ram */ + .start = 0x30000000, + .end = 0x301FFFFF, /* 2MiB */ + .flags = IORESOURCE_IO, + }, + { + .name = "ST231bMonitor", /* 8KiB block ST231b monitor */ + .start = 0x30200000, + .end = 0x30201FFF, + .flags = IORESOURCE_IO, + }, + { + .name = "MediaMemory2", + .start = 0x30202000, + .end = 0x31FFFFFF, /*~29.9MiB (32MiB - (2MiB + 8KiB)) */ + .flags = IORESOURCE_IO, + }, + /* + * + * Sysaudio Driver + * + * This driver requires: + * + * Arbitrary Based Buffers: + * DSP_Image_Buff - DSP code and data images (1MB) + * ADSC_CPU_PCM_Buff - ADSC CPU PCM buffer (40KB) + * ADSC_AUX_Buff - ADSC AUX buffer (16KB) + * ADSC_Main_Buff - ADSC Main buffer (16KB) + * + */ + { + .name = "DSP_Image_Buff", + .start = 0x00000000, + .end = 0x000FFFFF, + .flags = IORESOURCE_MEM, + }, + { + .name = "ADSC_CPU_PCM_Buff", + .start = 0x00000000, + .end = 0x00009FFF, + .flags = IORESOURCE_MEM, + }, + { + .name = "ADSC_AUX_Buff", + .start = 0x00000000, + .end = 0x00003FFF, + .flags = IORESOURCE_MEM, + }, + { + .name = "ADSC_Main_Buff", + .start = 0x00000000, + .end = 0x00003FFF, + .flags = IORESOURCE_MEM, + }, + /* + * + * STAVEM driver/STAPI + * + * This driver requires: + * + * Arbitrary Based Buffers: + * This memory area is used for allocating buffers for Video decoding + * purposes. Allocation/De-allocation within this buffer is managed + * by the STAVMEM driver of the STAPI. They could be Decimated + * Picture Buffers, Intermediate Buffers, as deemed necessary for + * video decoding purposes, for any video decoders on Zeus. + * + */ + { + .name = "AVMEMPartition0", + .start = 0x00000000, + .end = 0x00c00000 - 1, /* 12 MB total */ + .flags = IORESOURCE_MEM, + }, + /* + * + * DOCSIS Subsystem + * + * This driver requires: + * + * Arbitrary Based Buffers: + * Docsis - + * + */ + { + .name = "Docsis", + .start = 0x40100000, + .end = 0x407fffff, + .flags = IORESOURCE_MEM, + }, + /* + * + * GHW HAL Driver + * + * This driver requires: + * + * Arbitrary Based Buffers: + * GraphicsHeap - PowerTV Graphics Heap + * + */ + { + .name = "GraphicsHeap", + .start = 0x46900000, + .end = 0x47700000 - 1, /* 14 MB total */ + .flags = IORESOURCE_MEM, + }, + /* + * + * multi com buffer area + * + * This driver requires: + * + * Arbitrary Based Buffers: + * Docsis - + * + */ + { + .name = "MulticomSHM", + .start = 0x47900000, + .end = 0x47920000 - 1, + .flags = IORESOURCE_MEM, + }, + /* + * + * DMA Ring buffer + * + * This driver requires: + * + * Arbitrary Based Buffers: + * Docsis - + * + */ + { + .name = "BMM_Buffer", + .start = 0x00000000, + .end = 0x00280000 - 1, + .flags = IORESOURCE_MEM, + }, + /* + * + * Display bins buffer for unit0 + * + * This driver requires: + * + * Arbitrary Based Buffers: + * Display Bins for unit0 + * + */ + { + .name = "DisplayBins0", + .start = 0x00000000, + .end = 0x00000FFF, /* 4 KB total */ + .flags = IORESOURCE_MEM, + }, + /* + * + * Display bins buffer + * + * This driver requires: + * + * Arbitrary Based Buffers: + * Display Bins for unit1 + * + */ + { + .name = "DisplayBins1", + .start = 0x00000000, + .end = 0x00000FFF, /* 4 KB total */ + .flags = IORESOURCE_MEM, + }, + /* + * + * ITFS + * + * This driver requires: + * + * Arbitrary Based Buffers: + * Docsis - + * + */ + { + .name = "ITFS", + .start = 0x00000000, + /* 815,104 bytes each for 2 ITFS partitions. */ + .end = 0x0018DFFF, + .flags = IORESOURCE_MEM, + }, + /* + * + * AVFS + * + * This driver requires: + * + * Arbitrary Based Buffers: + * Docsis - + * + */ + { + .name = "AvfsDmaMem", + .start = 0x00000000, + /* (945K * 8) = (128K * 3) 5 playbacks / 3 server */ + .end = 0x007c2000 - 1, + .flags = IORESOURCE_MEM, + }, + { + .name = "AvfsFileSys", + .start = 0x00000000, + .end = 0x00001000 - 1, /* 4K */ + .flags = IORESOURCE_MEM, + }, + /* + * + * PMEM + * + * This driver requires: + * + * Arbitrary Based Buffers: + * Persistent memory for diagnostics. + * + */ + { + .name = "DiagPersistentMemory", + .start = 0x00000000, + .end = 0x10000 - 1, + .flags = IORESOURCE_MEM, + }, + /* + * + * Smartcard + * + * This driver requires: + * + * Arbitrary Based Buffers: + * Read and write buffers for Internal/External cards + * + */ + { + .name = "SmartCardInfo", + .start = 0x00000000, + .end = 0x2800 - 1, + .flags = IORESOURCE_MEM, + }, + /* + * Add other resources here + */ + { }, +}; + +/* + * NON_DVR_CAPABLE ZEUS RESOURCES + */ +struct resource non_dvr_zeus_resources[] __initdata = +{ + /* + * VIDEO1 / LX1 + */ + { + .name = "ST231aImage", /* Delta-Mu 1 image and ram */ + .start = 0x20000000, + .end = 0x201FFFFF, /* 2MiB */ + .flags = IORESOURCE_IO, + }, + { + .name = "ST231aMonitor", /* 8KiB block ST231a monitor */ + .start = 0x20200000, + .end = 0x20201FFF, + .flags = IORESOURCE_IO, + }, + { + .name = "MediaMemory1", + .start = 0x20202000, + .end = 0x21FFFFFF, /*~29.9MiB (32MiB - (2MiB + 8KiB)) */ + .flags = IORESOURCE_IO, + }, + /* + * Sysaudio Driver + */ + { + .name = "DSP_Image_Buff", + .start = 0x00000000, + .end = 0x000FFFFF, + .flags = IORESOURCE_MEM, + }, + { + .name = "ADSC_CPU_PCM_Buff", + .start = 0x00000000, + .end = 0x00009FFF, + .flags = IORESOURCE_MEM, + }, + { + .name = "ADSC_AUX_Buff", + .start = 0x00000000, + .end = 0x00003FFF, + .flags = IORESOURCE_MEM, + }, + { + .name = "ADSC_Main_Buff", + .start = 0x00000000, + .end = 0x00003FFF, + .flags = IORESOURCE_MEM, + }, + /* + * STAVEM driver/STAPI + */ + { + .name = "AVMEMPartition0", + .start = 0x00000000, + .end = 0x00600000 - 1, /* 6 MB total */ + .flags = IORESOURCE_MEM, + }, + /* + * DOCSIS Subsystem + */ + { + .name = "Docsis", + .start = 0x40100000, + .end = 0x407fffff, + .flags = IORESOURCE_MEM, + }, + /* + * GHW HAL Driver + */ + { + .name = "GraphicsHeap", + .start = 0x46900000, + .end = 0x47700000 - 1, /* 14 MB total */ + .flags = IORESOURCE_MEM, + }, + /* + * multi com buffer area + */ + { + .name = "MulticomSHM", + .start = 0x47900000, + .end = 0x47920000 - 1, + .flags = IORESOURCE_MEM, + }, + /* + * DMA Ring buffer + */ + { + .name = "BMM_Buffer", + .start = 0x00000000, + .end = 0x00280000 - 1, + .flags = IORESOURCE_MEM, + }, + /* + * Display bins buffer for unit0 + */ + { + .name = "DisplayBins0", + .start = 0x00000000, + .end = 0x00000FFF, /* 4 KB total */ + .flags = IORESOURCE_MEM, + }, + /* + * + * AVFS: player HAL memory + * + * + */ + { + .name = "AvfsDmaMem", + .start = 0x00000000, + .end = 0x002c4c00 - 1, /* 945K * 3 for playback */ + .flags = IORESOURCE_MEM, + }, + /* + * PMEM + */ + { + .name = "DiagPersistentMemory", + .start = 0x00000000, + .end = 0x10000 - 1, + .flags = IORESOURCE_MEM, + }, + /* + * Smartcard + */ + { + .name = "SmartCardInfo", + .start = 0x00000000, + .end = 0x2800 - 1, + .flags = IORESOURCE_MEM, + }, + /* + * NAND Flash + */ + { + .name = "NandFlash", + .start = NAND_FLASH_BASE, + .end = NAND_FLASH_BASE + 0x400 - 1, + .flags = IORESOURCE_IO, + }, + /* + * Add other resources here + */ + { }, +}; diff --git a/arch/mips/powertv/cevt-powertv.c b/arch/mips/powertv/cevt-powertv.c new file mode 100644 index 0000000..0f7d90e --- /dev/null +++ b/arch/mips/powertv/cevt-powertv.c @@ -0,0 +1,175 @@ +/* + * Copyright (C) 2008 Scientific-Atlanta, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + */ + +#if 0 +/* + * The file comes from kernel/cevt-r4k.c + */ +#include +#include +#include +#include + +#include + +#include +#include "powertv-clock.h" + +static int mips_next_event(unsigned long delta, + struct clock_event_device *evt) +{ + unsigned int cnt; + int res; + + cnt = read_c0_count(); + cnt += delta; + write_c0_compare(cnt); + res = ((int)(read_c0_count() - cnt) > 0) ? -ETIME : 0; + return res; +} + +static void mips_set_mode(enum clock_event_mode mode, + struct clock_event_device *evt) +{ + /* Nothing to do ... */ +} + +static DEFINE_PER_CPU(struct clock_event_device, mips_clockevent_device); +static int cp0_timer_irq_installed; + +/* + * Timer ack for an R4k-compatible timer of a known frequency. + */ +static void c0_timer_ack(void) +{ + write_c0_compare(read_c0_compare()); +} + +#ifndef CONFIG_SEPARATE_PCI_TI +/* + * Possibly handle a performance counter interrupt. + * Return true if the timer interrupt should not be checked + */ +static inline int handle_perf_irq(int r2) +{ + /* + * The performance counter overflow interrupt may be shared with the + * timer interrupt (cp0_perfcount_irq < 0). If it is and a + * performance counter has overflowed (perf_irq() == IRQ_HANDLED) + * and we can't reliably determine if a counter interrupt has also + * happened (!r2) then don't check for a timer interrupt. + */ + return (cp0_perfcount_irq < 0) && + perf_irq() == IRQ_HANDLED && + !r2; +} +#endif + +static irqreturn_t c0_compare_interrupt(int irq, void *dev_id) +{ + const int r2 = cpu_has_mips_r2; + struct clock_event_device *cd; + int cpu = smp_processor_id(); + +#ifndef CONFIG_SEPARATE_PCI_TI + /* + * Suckage alert: + * Before R2 of the architecture there was no way to see if a + * performance counter interrupt was pending, so we have to run + * the performance counter interrupt handler anyway. + */ + if (handle_perf_irq(r2)) + return IRQ_HANDLED; +#endif + + /* + * The same applies to performance counter interrupts. But with the + * above we now know that the reason we got here must be a timer + * interrupt. Being the paranoiacs we are we check anyway. + */ + if (!r2 || (read_c0_cause() & (1 << 30))) { + c0_timer_ack(); + cd = &per_cpu(mips_clockevent_device, cpu); + cd->event_handler(cd); + } + + return IRQ_HANDLED; +} + +static struct irqaction c0_compare_irqaction = { + .handler = c0_compare_interrupt, + .flags = IRQF_DISABLED | IRQF_PERCPU, + .name = "timer", +}; + +static void mips_event_handler(struct clock_event_device *dev) +{ +} + +int __cpuinit powertv_clockevent_init(void) +{ + uint64_t mips_freq = mips_hpt_frequency; + unsigned int cpu = smp_processor_id(); + struct clock_event_device *cd; + unsigned int irq; + + if (!cpu_has_counter || !mips_hpt_frequency) + return -ENXIO; + + + irq = irq_mips_timer; + + cd = &per_cpu(mips_clockevent_device, cpu); + + cd->name = "MIPS"; + cd->features = CLOCK_EVT_FEAT_ONESHOT; + + /* Calculate the min / max delta */ + cd->mult = div_sc((unsigned long) mips_freq, NSEC_PER_SEC, 32); + cd->shift = 32; + cd->max_delta_ns = clockevent_delta2ns(0x7fffffff, cd); + cd->min_delta_ns = clockevent_delta2ns(0x300, cd); + + cd->rating = 300; + cd->irq = irq; + cd->cpumask = get_cpu_mask(cpu); + + cd->set_next_event = mips_next_event; + cd->set_mode = mips_set_mode; + cd->event_handler = mips_event_handler; + + clockevents_register_device(cd); + + if (cp0_timer_irq_installed) + return 0; + + cp0_timer_irq_installed = 1; + + setup_irq(irq, &c0_compare_irqaction); + + return 0; +} +#endif + +#include +#include /* Not included in linux/time.h */ + +unsigned int __cpuinit get_c0_compare_int(void) +{ + return irq_mips_timer; +} diff --git a/arch/mips/powertv/cmdline.c b/arch/mips/powertv/cmdline.c new file mode 100644 index 0000000..98d73cb --- /dev/null +++ b/arch/mips/powertv/cmdline.c @@ -0,0 +1,52 @@ +/* + * Carsten Langgaard, carstenl@mips.com + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. + * Portions copyright (C) 2009 Cisco Systems, Inc. + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * Kernel command line creation using the prom monitor (YAMON) argc/argv. + */ +#include +#include + +#include + +#include "init.h" + +/* + * YAMON (32-bit PROM) pass arguments and environment as 32-bit pointer. + * This macro take care of sign extension. + */ +#define prom_argv(index) ((char *)(long)_prom_argv[(index)]) + +char * __init prom_getcmdline(void) +{ + return &(arcs_cmdline[0]); +} + +void __init prom_init_cmdline(void) +{ + int len; + + if (prom_argc != 1) + return; + + len = strlen(arcs_cmdline); + + arcs_cmdline[len] = ' '; + + strlcpy(arcs_cmdline + len + 1, (char *)_prom_argv, + COMMAND_LINE_SIZE - len - 1); +} diff --git a/arch/mips/powertv/csrc-powertv.c b/arch/mips/powertv/csrc-powertv.c new file mode 100644 index 0000000..a27c16c --- /dev/null +++ b/arch/mips/powertv/csrc-powertv.c @@ -0,0 +1,180 @@ +/* + * Copyright (C) 2008 Scientific-Atlanta, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + */ +/* + * The file comes from kernel/csrc-r4k.c + */ +#include +#include + +#include /* Not included in linux/time.h */ + +#include +#include "powertv-clock.h" + +/* MIPS PLL Register Definitions */ +#define PLL_GET_M(x) (((x) >> 8) & 0x000000FF) +#define PLL_GET_N(x) (((x) >> 16) & 0x000000FF) +#define PLL_GET_P(x) (((x) >> 24) & 0x00000007) + +/* + * returns: Clock frequency in kHz + */ +unsigned int __init mips_get_pll_freq(void) +{ + unsigned int pll_reg, m, n, p; + unsigned int fin = 54000; /* Base frequency in kHz */ + unsigned int fout; + + /* Read PLL register setting */ + pll_reg = asic_read(mips_pll_setup); + m = PLL_GET_M(pll_reg); + n = PLL_GET_N(pll_reg); + p = PLL_GET_P(pll_reg); + pr_info("MIPS PLL Register:0x%x M=%d N=%d P=%d\n", pll_reg, m, n, p); + + /* Calculate clock frequency = (2 * N * 54MHz) / (M * (2**P)) */ + fout = ((2 * n * fin) / (m * (0x01 << p))); + + pr_info("MIPS Clock Freq=%d kHz\n", fout); + + return fout; +} + +static cycle_t c0_hpt_read(struct clocksource *cs) +{ + return read_c0_count(); +} + +static struct clocksource clocksource_mips = { + .name = "powertv-counter", + .read = c0_hpt_read, + .mask = CLOCKSOURCE_MASK(32), + .flags = CLOCK_SOURCE_IS_CONTINUOUS, +}; + +static void __init powertv_c0_hpt_clocksource_init(void) +{ + unsigned int pll_freq = mips_get_pll_freq(); + + pr_info("CPU frequency %d.%02d MHz\n", pll_freq / 1000, + (pll_freq % 1000) * 100 / 1000); + + mips_hpt_frequency = pll_freq / 2 * 1000; + + clocksource_mips.rating = 200 + mips_hpt_frequency / 10000000; + + clocksource_set_clock(&clocksource_mips, mips_hpt_frequency); + + clocksource_register(&clocksource_mips); +} + +/** + * struct tim_c - free running counter + * @hi: High 16 bits of the counter + * @lo: Low 32 bits of the counter + * + * Lays out the structure of the free running counter in memory. This counter + * increments at a rate of 27 MHz/8 on all platforms. + */ +struct tim_c { + unsigned int hi; + unsigned int lo; +}; + +static struct tim_c *tim_c; + +static cycle_t tim_c_read(struct clocksource *cs) +{ + unsigned int hi; + unsigned int next_hi; + unsigned int lo; + + hi = readl(&tim_c->hi); + + for (;;) { + lo = readl(&tim_c->lo); + next_hi = readl(&tim_c->hi); + if (next_hi == hi) + break; + hi = next_hi; + } + +pr_crit("%s: read %llx\n", __func__, ((u64) hi << 32) | lo); + return ((u64) hi << 32) | lo; +} + +#define TIM_C_SIZE 48 /* # bits in the timer */ + +static struct clocksource clocksource_tim_c = { + .name = "powertv-tim_c", + .read = tim_c_read, + .mask = CLOCKSOURCE_MASK(TIM_C_SIZE), + .flags = CLOCK_SOURCE_IS_CONTINUOUS, +}; + +/** + * powertv_tim_c_clocksource_init - set up a clock source for the TIM_C clock + * + * The hard part here is coming up with a constant k and shift s such that + * the 48-bit TIM_C value multiplied by k doesn't overflow and that value, + * when shifted right by s, yields the corresponding number of nanoseconds. + * We know that TIM_C counts at 27 MHz/8, so each cycle corresponds to + * 1 / (27,000,000/8) seconds. Multiply that by a billion and you get the + * number of nanoseconds. Since the TIM_C value has 48 bits and the math is + * done in 64 bits, avoiding an overflow means that k must be less than + * 64 - 48 = 16 bits. + */ +static void __init powertv_tim_c_clocksource_init(void) +{ + int prescale; + unsigned long dividend; + unsigned long k; + int s; + const int max_k_bits = (64 - 48) - 1; + const unsigned long billion = 1000000000; + const unsigned long counts_per_second = 27000000 / 8; + + prescale = BITS_PER_LONG - ilog2(billion) - 1; + dividend = billion << prescale; + k = dividend / counts_per_second; + s = ilog2(k) - max_k_bits; + + if (s < 0) + s = prescale; + + else { + k >>= s; + s += prescale; + } + + clocksource_tim_c.mult = k; + clocksource_tim_c.shift = s; + clocksource_tim_c.rating = 200; + + clocksource_register(&clocksource_tim_c); + tim_c = (struct tim_c *) asic_reg_addr(tim_ch); +} + +/** + powertv_clocksource_init - initialize all clocksources + */ +void __init powertv_clocksource_init(void) +{ + powertv_c0_hpt_clocksource_init(); + powertv_tim_c_clocksource_init(); +} diff --git a/arch/mips/powertv/init.c b/arch/mips/powertv/init.c new file mode 100644 index 0000000..5f4e4c3 --- /dev/null +++ b/arch/mips/powertv/init.c @@ -0,0 +1,128 @@ +/* + * Copyright (C) 1999, 2000, 2004, 2005 MIPS Technologies, Inc. + * All rights reserved. + * Authors: Carsten Langgaard + * Maciej W. Rozycki + * Portions copyright (C) 2009 Cisco Systems, Inc. + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * PROM library initialisation code. + */ +#include +#include +#include + +#include +#include +#include +#include +#include + +#include +#include +#include + +#include "init.h" + +int prom_argc; +int *_prom_argv, *_prom_envp; +unsigned long _prom_memsize; + +/* + * YAMON (32-bit PROM) pass arguments and environment as 32-bit pointer. + * This macro take care of sign extension, if running in 64-bit mode. + */ +#define prom_envp(index) ((char *)(long)_prom_envp[(index)]) + +char *prom_getenv(char *envname) +{ + char *result = NULL; + + if (_prom_envp != NULL) { + /* + * Return a pointer to the given environment variable. + * In 64-bit mode: we're using 64-bit pointers, but all pointers + * in the PROM structures are only 32-bit, so we need some + * workarounds, if we are running in 64-bit mode. + */ + int i, index = 0; + + i = strlen(envname); + + while (prom_envp(index)) { + if (strncmp(envname, prom_envp(index), i) == 0) { + result = prom_envp(index + 1); + break; + } + index += 2; + } + } + + return result; +} + +/* TODO: Verify on linux-mips mailing list that the following two */ +/* functions are correct */ +/* TODO: Copy NMI and EJTAG exception vectors to memory from the */ +/* BootROM exception vectors. Flush their cache entries. test it. */ + +static void __init mips_nmi_setup(void) +{ + void *base; +#if defined(CONFIG_CPU_MIPS32_R1) + base = cpu_has_veic ? + (void *)(CAC_BASE + 0xa80) : + (void *)(CAC_BASE + 0x380); +#elif defined(CONFIG_CPU_MIPS32_R2) + base = (void *)0xbfc00000; +#else +#error NMI exception handler address not defined +#endif +} + +static void __init mips_ejtag_setup(void) +{ + void *base; + +#if defined(CONFIG_CPU_MIPS32_R1) + base = cpu_has_veic ? + (void *)(CAC_BASE + 0xa00) : + (void *)(CAC_BASE + 0x300); +#elif defined(CONFIG_CPU_MIPS32_R2) + base = (void *)0xbfc00480; +#else +#error EJTAG exception handler address not defined +#endif +} + +void __init prom_init(void) +{ + prom_argc = fw_arg0; + _prom_argv = (int *) fw_arg1; + _prom_envp = (int *) fw_arg2; + _prom_memsize = (unsigned long) fw_arg3; + + board_nmi_handler_setup = mips_nmi_setup; + board_ejtag_handler_setup = mips_ejtag_setup; + + pr_info("\nLINUX started...\n"); + prom_init_cmdline(); + configure_platform(); + prom_meminit(); + +#ifndef CONFIG_BOOTLOADER_DRIVER + pr_info("\nBootloader driver isn't loaded...\n"); +#endif +} diff --git a/arch/mips/powertv/init.h b/arch/mips/powertv/init.h new file mode 100644 index 0000000..332cfed --- /dev/null +++ b/arch/mips/powertv/init.h @@ -0,0 +1,30 @@ +/* + * init.h + * + * Definitions from powertv init.c file + * + * Copyright (C) 2009 Cisco Systems, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + * Author: David VomLehn + */ + +#ifndef _POWERTV_INIT_H +#define _POWERTV_INIT_H +extern int prom_argc; +extern int *_prom_argv; +extern unsigned long _prom_memsize; +#endif diff --git a/arch/mips/powertv/memory.c b/arch/mips/powertv/memory.c new file mode 100644 index 0000000..4ef689c --- /dev/null +++ b/arch/mips/powertv/memory.c @@ -0,0 +1,184 @@ +/* + * Carsten Langgaard, carstenl@mips.com + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. + * Portions copyright (C) 2009 Cisco Systems, Inc. + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * Apparently originally from arch/mips/malta-memory.c. Modified to work + * with the PowerTV bootloader. + */ +#include +#include +#include +#include +#include + +#include +#include +#include + +#include + +#include "init.h" + +/* Memory constants */ +#define KIBIBYTE(n) ((n) * 1024) /* Number of kibibytes */ +#define MEBIBYTE(n) ((n) * KIBIBYTE(1024)) /* Number of mebibytes */ +#define DEFAULT_MEMSIZE MEBIBYTE(256) /* If no memsize provided */ +#define LOW_MEM_MAX MEBIBYTE(252) /* Max usable low mem */ +#define RES_BOOTLDR_MEMSIZE MEBIBYTE(1) /* Memory reserved for bldr */ +#define BOOT_MEM_SIZE KIBIBYTE(256) /* Memory reserved for bldr */ +#define PHYS_MEM_START 0x10000000 /* Start of physical memory */ + +unsigned long ptv_memsize; + +void __init prom_meminit(void) +{ + char *memsize_str; + unsigned long memsize = 0; + unsigned int physend; + char cmdline[CL_SIZE], *ptr; + int low_mem; + int high_mem; + + /* Check the command line first for a memsize directive */ + strcpy(cmdline, arcs_cmdline); + ptr = strstr(cmdline, "memsize="); + if (ptr && (ptr != cmdline) && (*(ptr - 1) != ' ')) + ptr = strstr(ptr, " memsize="); + + if (ptr) { + memsize = memparse(ptr + 8, &ptr); + } else { + /* otherwise look in the environment */ + memsize_str = prom_getenv("memsize"); + + if (memsize_str != NULL) { + pr_info("prom memsize = %s\n", memsize_str); + memsize = simple_strtol(memsize_str, NULL, 0); + } + + if (memsize == 0) { + if (_prom_memsize != 0) { + memsize = _prom_memsize; + pr_info("_prom_memsize = 0x%lx\n", memsize); + /* add in memory that the bootloader doesn't + * report */ + memsize += BOOT_MEM_SIZE; + } else { + memsize = DEFAULT_MEMSIZE; + pr_info("Memsize not passed by bootloader, " + "defaulting to 0x%lx\n", memsize); + } + } + } + + /* Store memsize for diagnostic purposes */ + ptv_memsize = memsize; + + physend = PFN_ALIGN(&_end) - 0x80000000; + if (memsize > LOW_MEM_MAX) { + low_mem = LOW_MEM_MAX; + high_mem = memsize - low_mem; + } else { + low_mem = memsize; + high_mem = 0; + } + +/* + * TODO: We will use the hard code for memory configuration until + * the bootloader releases their device tree to us. + */ + /* + * Add the memory reserved for use by the bootloader to the + * memory map. + */ + add_memory_region(PHYS_MEM_START, RES_BOOTLDR_MEMSIZE, + BOOT_MEM_RESERVED); +#ifdef CONFIG_HIGHMEM_256_128 + /* + * Add memory in low for general use by the kernel and its friends + * (like drivers, applications, etc). + */ + add_memory_region(PHYS_MEM_START + RES_BOOTLDR_MEMSIZE, + LOW_MEM_MAX - RES_BOOTLDR_MEMSIZE, BOOT_MEM_RAM); + /* + * Add the memory reserved for reset vector. + */ + add_memory_region(0x1fc00000, MEBIBYTE(4), BOOT_MEM_RESERVED); + /* + * Add the memory reserved. + */ + add_memory_region(0x20000000, MEBIBYTE(1024 + 75), BOOT_MEM_RESERVED); + /* + * Add memory in high for general use by the kernel and its friends + * (like drivers, applications, etc). + * + * 75MB is reserved for devices which are using the memory in high. + */ + add_memory_region(0x60000000 + MEBIBYTE(75), MEBIBYTE(128 - 75), + BOOT_MEM_RAM); +#elif defined CONFIG_HIGHMEM_128_128 + /* + * Add memory in low for general use by the kernel and its friends + * (like drivers, applications, etc). + */ + add_memory_region(PHYS_MEM_START + RES_BOOTLDR_MEMSIZE, + MEBIBYTE(128) - RES_BOOTLDR_MEMSIZE, BOOT_MEM_RAM); + /* + * Add the memory reserved. + */ + add_memory_region(PHYS_MEM_START + MEBIBYTE(128), + MEBIBYTE(128 + 1024 + 75), BOOT_MEM_RESERVED); + /* + * Add memory in high for general use by the kernel and its friends + * (like drivers, applications, etc). + * + * 75MB is reserved for devices which are using the memory in high. + */ + add_memory_region(0x60000000 + MEBIBYTE(75), MEBIBYTE(128 - 75), + BOOT_MEM_RAM); +#else + /* Add low memory regions for either: + * - no-highmemory configuration case -OR- + * - highmemory "HIGHMEM_LOWBANK_ONLY" case + */ + /* + * Add memory for general use by the kernel and its friends + * (like drivers, applications, etc). + */ + add_memory_region(PHYS_MEM_START + RES_BOOTLDR_MEMSIZE, + low_mem - RES_BOOTLDR_MEMSIZE, BOOT_MEM_RAM); + /* + * Add the memory reserved for reset vector. + */ + add_memory_region(0x1fc00000, MEBIBYTE(4), BOOT_MEM_RESERVED); +#endif +} + +void __init prom_free_prom_memory(void) +{ + unsigned long addr; + int i; + + for (i = 0; i < boot_mem_map.nr_map; i++) { + if (boot_mem_map.map[i].type != BOOT_MEM_ROM_DATA) + continue; + + addr = boot_mem_map.map[i].addr; + free_init_pages("prom memory", + addr, addr + boot_mem_map.map[i].size); + } +} diff --git a/arch/mips/powertv/pci/Makefile b/arch/mips/powertv/pci/Makefile new file mode 100644 index 0000000..9249164 --- /dev/null +++ b/arch/mips/powertv/pci/Makefile @@ -0,0 +1,28 @@ +# ***************************************************************************** +# Make file for PowerTV PCI driver +# +# Copyright (C) 2009 Scientific-Atlanta, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# +# ***************************************************************************** + +EXTRA_CFLAGS += -Wall -Werror + +obj-y := + +obj-$(CONFIG_PCI) += fixup-powertv.o + + diff --git a/arch/mips/powertv/pci/fixup-powertv.c b/arch/mips/powertv/pci/fixup-powertv.c new file mode 100644 index 0000000..726bc2e --- /dev/null +++ b/arch/mips/powertv/pci/fixup-powertv.c @@ -0,0 +1,36 @@ +#include +#include +#include +#include "powertv-pci.h" + +int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) +{ + return asic_pcie_map_irq(dev, slot, pin); +} + +/* Do platform specific device initialization at pci_enable_device() time */ +int pcibios_plat_dev_init(struct pci_dev *dev) +{ + return 0; +} + +/* + * asic_pcie_map_irq + * + * Parameters: + * *dev - pointer to a pci_dev structure (not used) + * slot - slot number (not used) + * pin - pin number (not used) + * + * Return Value: + * Returns: IRQ number (always the PCI Express IRQ number) + * + * Description: + * asic_pcie_map_irq will return the IRQ number of the PCI Express interrupt. + * + */ +int asic_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) +{ + return irq_pciexp; +} +EXPORT_SYMBOL(asic_pcie_map_irq); diff --git a/arch/mips/powertv/pci/powertv-pci.h b/arch/mips/powertv/pci/powertv-pci.h new file mode 100644 index 0000000..1b5886b --- /dev/null +++ b/arch/mips/powertv/pci/powertv-pci.h @@ -0,0 +1,31 @@ +/* + * powertv-pci.c + * + * Copyright (C) 2009 Cisco Systems, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +/* + * Local definitions for the powertv PCI code + */ + +#ifndef _POWERTV_PCI_POWERTV_PCI_H_ +#define _POWERTV_PCI_POWERTV_PCI_H_ +extern int asic_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin); +extern int asic_pcie_init(void); +extern int asic_pcie_init(void); + +extern int log_level; +#endif diff --git a/arch/mips/powertv/powertv-clock.h b/arch/mips/powertv/powertv-clock.h new file mode 100644 index 0000000..5c1f093 --- /dev/null +++ b/arch/mips/powertv/powertv-clock.h @@ -0,0 +1,30 @@ +/* + * powertv-clock.h + * + * Definitions for clocks + * + * Copyright (C) 2009 Cisco Systems, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + * Author: David VomLehn + */ + +#ifndef _POWERTV_POWERTV_CLOCK_H +#define _POWERTV_POWERTV_CLOCK_H +extern int powertv_clockevent_init(void); +extern void powertv_clocksource_init(void); +extern unsigned int mips_get_pll_freq(void); +#endif diff --git a/arch/mips/powertv/powertv_setup.c b/arch/mips/powertv/powertv_setup.c new file mode 100644 index 0000000..bd8ebf1 --- /dev/null +++ b/arch/mips/powertv/powertv_setup.c @@ -0,0 +1,351 @@ +/* + * Carsten Langgaard, carstenl@mips.com + * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. + * Portions copyright (C) 2009 Cisco Systems, Inc. + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "reset.h" + +#define VAL(n) STR(n) + +/* + * Macros for loading addresses and storing registers: + * PTR_LA Load the address into a register + * LONG_S Store the full width of the given register. + * LONG_L Load the full width of the given register + * PTR_ADDIU Add a constant value to a register used as a pointer + * REG_SIZE Number of 8-bit bytes in a full width register + */ +#ifdef CONFIG_64BIT +#warning TODO: 64-bit code needs to be verified +#define PTR_LA "dla " +#define LONG_S "sd " +#define LONG_L "ld " +#define PTR_ADDIU "daddiu " +#define REG_SIZE "8" /* In bytes */ +#endif + +#ifdef CONFIG_32BIT +#define PTR_LA "la " +#define LONG_S "sw " +#define LONG_L "lw " +#define PTR_ADDIU "addiu " +#define REG_SIZE "4" /* In bytes */ +#endif + +static struct pt_regs die_regs; +static bool have_die_