From macro@linux-mips.org Wed Jul 1 02:17:22 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 01 Jul 2009 02:17:30 +0200 (CEST) Received: from localhost.localdomain ([127.0.0.1]:47961 "EHLO localhost.localdomain" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1493467AbZGAARW (ORCPT ); Wed, 1 Jul 2009 02:17:22 +0200 Date: Wed, 1 Jul 2009 01:17:22 +0100 (BST) From: "Maciej W. Rozycki" To: Ralf Baechle cc: Dmitri Vorobiev , linux-mips@linux-mips.org Subject: Re: [PATCH] [MIPS] Malta: Remove unneeded function protos from malta-reset.c In-Reply-To: <20090628181702.GB20084@linux-mips.org> Message-ID: References: <1246035565-24015-1-git-send-email-dmitri.vorobiev@movial.com> <20090628181702.GB20084@linux-mips.org> User-Agent: Alpine 2.00 (LFD 1167 2008-08-23) MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23551 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: macro@linux-mips.org Precedence: bulk X-list: linux-mips On Sun, 28 Jun 2009, Ralf Baechle wrote: > There should be a tax on useless prototypes and also excessive parentheses ;-) And insufficient parentheses causing the average reader to refer to the language spec for the operator priority list. ;) Maciej From yanh@lemote.com Wed Jul 1 02:25:20 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 01 Jul 2009 02:25:26 +0200 (CEST) Received: from [222.92.8.141] ([222.92.8.141]:43249 "EHLO lemote.com" rhost-flags-FAIL-FAIL-OK-OK) by ftp.linux-mips.org with ESMTP id S1493066AbZGAAZT (ORCPT ); Wed, 1 Jul 2009 02:25:19 +0200 Received: from localhost (localhost [127.0.0.1]) by lemote.com (Postfix) with ESMTP id 7FDE73435B; Wed, 1 Jul 2009 08:13:14 +0800 (CST) X-Virus-Scanned: Debian amavisd-new at lemote.com Received: from lemote.com ([127.0.0.1]) by localhost (www.lemote.com [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 3qzwqOTFo7IA; Wed, 1 Jul 2009 08:12:59 +0800 (CST) Received: from [172.16.2.17] (unknown [222.92.8.142]) by lemote.com (Postfix) with ESMTP id DE30C34A07; Wed, 1 Jul 2009 08:12:59 +0800 (CST) Message-ID: <4A4AAB93.6040306@lemote.com> Date: Wed, 01 Jul 2009 08:19:31 +0800 From: yanhua User-Agent: Mozilla-Thunderbird 2.0.0.19 (X11/20090103) MIME-Version: 1.0 To: wuzhangjin@gmail.com CC: LKML , linux-mips@linux-mips.org, Pavel Machek , Ralf Baechle Subject: Re: [BUG] MIPS: Hibernation in the latest linux-mips:master branch not work References: <1246372868.19049.17.camel@falcon> In-Reply-To: <1246372868.19049.17.camel@falcon> Content-Type: text/plain; charset=GB2312 Content-Transfer-Encoding: 8bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23552 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: yanh@lemote.com Precedence: bulk X-list: linux-mips Wu Zhangjin д: > Hi, > > I just updated my git repository to the master branch of the latest > linux-mips git repository, and tested the STD/Hibernation support on > fuloong2e and yeeloong2f, it failed: > > when using the no_console_suspend kernel command line to debug, it > stopped on: > > PM: Shringking memory... done (1000 pages freed) > PM: Freed 160000 kbytes in 1.68 seconds (95.23 MB/s) > PM: Creating hibernation image: > PM: Need to copy 5053 pages > PM: Hibernation image created (4195 pages copied) > > and then, the number indicator light of keyboard works well, but can not > type anything. > > Are there any other information about it? such as: it just freezes there, or IDE irq lost messages after some time? Is it duplicable every time? > anybody have tested it on another platform? does it work? > > Regards, > Wu Zhangjin > > > > From macro@linux-mips.org Wed Jul 1 02:37:04 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 01 Jul 2009 02:37:07 +0200 (CEST) Received: from localhost.localdomain ([127.0.0.1]:41221 "EHLO localhost.localdomain" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492756AbZGAAhE (ORCPT ); Wed, 1 Jul 2009 02:37:04 +0200 Date: Wed, 1 Jul 2009 01:37:04 +0100 (BST) From: "Maciej W. Rozycki" To: Ralf Baechle cc: David Daney , linux-mips@linux-mips.org Subject: Re: [PATCH] MIPS: Define __arch_swab64 for all mips r2 cpus (v2). In-Reply-To: <20090629193454.GA23430@linux-mips.org> Message-ID: References: <1246294455-26866-1-git-send-email-ddaney@caviumnetworks.com> <20090629193454.GA23430@linux-mips.org> User-Agent: Alpine 2.00 (LFD 1167 2008-08-23) MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23553 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: macro@linux-mips.org Precedence: bulk X-list: linux-mips On Mon, 29 Jun 2009, Ralf Baechle wrote: > > Some CPUs implement mipsr2, but because they are a super-set of > > mips64r2 do not define CONFIG_CPU_MIPS64_R2. Cavium OCTEON falls into > > this category. We would still like to use the optimized > > implementation, so since we have already checked for > > CONFIG_CPU_MIPSR2, checking for CONFIG_64BIT instead of > > CONFIG_CPU_MIPS64_R2 is sufficient. > > > > Change from v1: Add comments about why the change is safe. > > Thanks, applied. Though this sort of patch make me thing that maybe we > rather should have treated the cnMIPS cores differently. This is a pure code generation option and it asks for "select CPU_MIPS64_R2" under CPU_OCTEON (or whatever option is used for that chip). Or something like "select ISA_MIPS64_R2" actually, as we want to keep CPU_foo as the -march=, etc. designator. IOW it looks like we lack ISA supersetting along the lines of how tools handle it. Maciej From wuzhangjin@gmail.com Wed Jul 1 02:42:57 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 01 Jul 2009 02:43:03 +0200 (CEST) Received: from mail-pz0-f173.google.com ([209.85.222.173]:65520 "EHLO mail-pz0-f173.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1493467AbZGAAm4 (ORCPT ); Wed, 1 Jul 2009 02:42:56 +0200 Received: by pzk3 with SMTP id 3so455697pzk.22 for ; Tue, 30 Jun 2009 17:37:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:subject:from:reply-to:to:cc :in-reply-to:references:content-type:organization:date:message-id :mime-version:x-mailer:content-transfer-encoding; bh=FV8MVlJrrX0IUOmNDUGpuv82Q+7eozF0fA+58wE5AM4=; b=psa4rNY0atdtXqC0kMOHC2+FQC+ZqLtp3CKNrfqd4Fpc+gCNdRM4h5kWYaQdPlp5vu pQrNWGFi8G8MQNkTQ5PbwhIeceN4bE7Mo02BKpu/7VCpCC9Xl198HDHhNzjPcWRGXh0n 5HYkysFx3MM2PhMkWMPHoOVhqoheHSBnWgdVI= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=subject:from:reply-to:to:cc:in-reply-to:references:content-type :organization:date:message-id:mime-version:x-mailer :content-transfer-encoding; b=CjRgMme691O7m7C7I7ncXb60QMhzWDs7QxpdZ+zJjsWTVmw0tDrnP56Uq0Rzywcv0X Vbduri8cz1Q1ANiX8qze+owHZ/IYn9S2hbiKmxUinsGwOslDAZ7bQ4QZ4W3T8a27ORhM FyQskDiP6kbvOtyEenVr1A3jNv6UDqftJxE7w= Received: by 10.142.240.19 with SMTP id n19mr861863wfh.198.1246408651115; Tue, 30 Jun 2009 17:37:31 -0700 (PDT) Received: from ?172.16.2.101? ([222.92.8.142]) by mx.google.com with ESMTPS id 29sm1988246wfg.1.2009.06.30.17.37.27 (version=TLSv1/SSLv3 cipher=RC4-MD5); Tue, 30 Jun 2009 17:37:30 -0700 (PDT) Subject: Re: [BUG] MIPS: Hibernation in the latest linux-mips:master branch not work From: Wu Zhangjin Reply-To: wuzhangjin@gmail.com To: yanhua Cc: LKML , linux-mips@linux-mips.org, Pavel Machek , Ralf Baechle In-Reply-To: <4A4AAB93.6040306@lemote.com> References: <1246372868.19049.17.camel@falcon> <4A4AAB93.6040306@lemote.com> Content-Type: text/plain; charset="UTF-8" Organization: DSLab, Lanzhou University, China Date: Wed, 01 Jul 2009 08:37:16 +0800 Message-Id: <1246408636.12459.3.camel@falcon> Mime-Version: 1.0 X-Mailer: Evolution 2.26.1 Content-Transfer-Encoding: 8bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23554 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips On Wed, 2009-07-01 at 08:19 +0800, yanhua wrote: > Wu Zhangjin 写道: > > Hi, > > > > I just updated my git repository to the master branch of the latest > > linux-mips git repository, and tested the STD/Hibernation support on > > fuloong2e and yeeloong2f, it failed: > > > > when using the no_console_suspend kernel command line to debug, it > > stopped on: > > > > PM: Shringking memory... done (1000 pages freed) > > PM: Freed 160000 kbytes in 1.68 seconds (95.23 MB/s) > > PM: Creating hibernation image: > > PM: Need to copy 5053 pages > > PM: Hibernation image created (4195 pages copied) > > > > and then, the number indicator light of keyboard works well, but can not > > type anything. > > > > > Are there any other information about it? such as: it just freezes > there, or IDE irq lost messages after some time? > > Is it duplicable every time? Yes, it is reproductive, I'm tracing it! Thanks! From David.Daney@caviumnetworks.com Wed Jul 1 03:19:38 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 01 Jul 2009 03:19:45 +0200 (CEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:62995 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1493470AbZGABTi (ORCPT ); Wed, 1 Jul 2009 03:19:38 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,2,2,3503) id ; Tue, 30 Jun 2009 21:14:05 -0400 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Tue, 30 Jun 2009 18:13:41 -0700 Received: from dd1.caveonetworks.com ([64.169.86.201]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Tue, 30 Jun 2009 18:13:41 -0700 Message-ID: <4A4AB845.1030906@caviumnetworks.com> Date: Tue, 30 Jun 2009 18:13:41 -0700 From: David Daney User-Agent: Thunderbird 2.0.0.21 (X11/20090320) MIME-Version: 1.0 To: "Maciej W. Rozycki" CC: Ralf Baechle , linux-mips@linux-mips.org Subject: Re: [PATCH] MIPS: Define __arch_swab64 for all mips r2 cpus (v2). References: <1246294455-26866-1-git-send-email-ddaney@caviumnetworks.com> <20090629193454.GA23430@linux-mips.org> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 01 Jul 2009 01:13:41.0640 (UTC) FILETIME=[2BECB880:01C9F9E9] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23555 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Maciej W. Rozycki wrote: > On Mon, 29 Jun 2009, Ralf Baechle wrote: > >>> Some CPUs implement mipsr2, but because they are a super-set of >>> mips64r2 do not define CONFIG_CPU_MIPS64_R2. Cavium OCTEON falls into >>> this category. We would still like to use the optimized >>> implementation, so since we have already checked for >>> CONFIG_CPU_MIPSR2, checking for CONFIG_64BIT instead of >>> CONFIG_CPU_MIPS64_R2 is sufficient. >>> >>> Change from v1: Add comments about why the change is safe. >> Thanks, applied. Though this sort of patch make me thing that maybe we >> rather should have treated the cnMIPS cores differently. > > This is a pure code generation option and it asks for "select > CPU_MIPS64_R2" under CPU_OCTEON (or whatever option is used for that > chip). Or something like "select ISA_MIPS64_R2" actually, as we want to > keep CPU_foo as the -march=, etc. designator. IOW it looks like we lack > ISA supersetting along the lines of how tools handle it. > The problem with CPU_MIPS64_R2 in the kernel is that it means two unrelated things: 1) The cpu can execute all mips64r2 ISA instructions. 2) The cpu requires that all worse case cache and execution hazards are handled. In the case of the Octeon processors, #1 is true, but we can get better performance by omitting many of the hazard barriers because they are unneeded. David Daney From macro@linux-mips.org Wed Jul 1 03:36:32 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 01 Jul 2009 03:36:35 +0200 (CEST) Received: from localhost.localdomain ([127.0.0.1]:34564 "EHLO localhost.localdomain" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492756AbZGABgb (ORCPT ); Wed, 1 Jul 2009 03:36:31 +0200 Date: Wed, 1 Jul 2009 02:36:31 +0100 (BST) From: "Maciej W. Rozycki" To: David Daney cc: Ralf Baechle , linux-mips@linux-mips.org Subject: Re: [PATCH] MIPS: Define __arch_swab64 for all mips r2 cpus (v2). In-Reply-To: <4A4AB845.1030906@caviumnetworks.com> Message-ID: References: <1246294455-26866-1-git-send-email-ddaney@caviumnetworks.com> <20090629193454.GA23430@linux-mips.org> <4A4AB845.1030906@caviumnetworks.com> User-Agent: Alpine 2.00 (LFD 1167 2008-08-23) MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23556 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: macro@linux-mips.org Precedence: bulk X-list: linux-mips On Tue, 30 Jun 2009, David Daney wrote: > The problem with CPU_MIPS64_R2 in the kernel is that it means two unrelated > things: > > 1) The cpu can execute all mips64r2 ISA instructions. > > 2) The cpu requires that all worse case cache and execution hazards are > handled. > > In the case of the Octeon processors, #1 is true, but we can get better > performance by omitting many of the hazard barriers because they are unneeded. Which is why I think a split of the semantics would be a good idea. Maciej From ralf@h5.dl5rb.org.uk Wed Jul 1 08:36:48 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 01 Jul 2009 08:36:55 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:36222 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1491965AbZGAGgr (ORCPT ); Wed, 1 Jul 2009 08:36:47 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id n616VHTw007491; Wed, 1 Jul 2009 07:31:17 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id n616VGe6007489; Wed, 1 Jul 2009 07:31:17 +0100 Date: Wed, 1 Jul 2009 07:31:16 +0100 From: Ralf Baechle To: "Maciej W. Rozycki" Cc: Dmitri Vorobiev , linux-mips@linux-mips.org Subject: Re: [PATCH] [MIPS] Malta: Remove unneeded function protos from malta-reset.c Message-ID: <20090701063116.GA6101@linux-mips.org> References: <1246035565-24015-1-git-send-email-dmitri.vorobiev@movial.com> <20090628181702.GB20084@linux-mips.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23557 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Wed, Jul 01, 2009 at 01:17:22AM +0100, Maciej W. Rozycki wrote: > > There should be a tax on useless prototypes and also excessive parentheses ;-) > > And insufficient parentheses causing the average reader to refer to the > language spec for the operator priority list. ;) Code written to require intimate knowledge of all operator priorities is probably as bad as overuse. Here a few examples: return (1); #define FOO (42) a = (b + c); a = (b + c) + d; a = (b * c) + (d * e); if ((a > b) && (a < c)) Ralf From w@1wt.eu Wed Jul 1 08:54:47 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 01 Jul 2009 08:54:55 +0200 (CEST) Received: from 1wt.eu ([62.212.114.60]:37070 "EHLO 1wt.eu" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492008AbZGAGyr (ORCPT ); Wed, 1 Jul 2009 08:54:47 +0200 Date: Wed, 1 Jul 2009 08:49:37 +0200 From: Willy Tarreau To: Frank Seidel Cc: "linux-mips@linux-mips.org" , "netdev@vger.kernel.org" Subject: Re: [PATCH] linux-2.4: br2684: fix double freeing skb Message-ID: <20090701064937.GA22396@1wt.eu> References: <4A49C9BC.6050908@sphairon.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <4A49C9BC.6050908@sphairon.com> User-Agent: Mutt/1.5.11 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23558 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: w@1wt.eu Precedence: bulk X-list: linux-mips On Tue, Jun 30, 2009 at 10:15:56AM +0200, Frank Seidel wrote: > Author: Peter Sieber > > Fix double freeing skb, see net/core/dev.c > dev_queue_xmit(). > > Signed-off-by: Peter Sieber > Signed-off-by: Frank Seidel queued for inclusion, thanks Frank! Willy From w@1wt.eu Wed Jul 1 08:55:12 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 01 Jul 2009 08:55:20 +0200 (CEST) Received: from 1wt.eu ([62.212.114.60]:37073 "EHLO 1wt.eu" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492022AbZGAGzE (ORCPT ); Wed, 1 Jul 2009 08:55:04 +0200 Date: Wed, 1 Jul 2009 08:49:54 +0200 From: Willy Tarreau To: Frank Seidel Cc: "linux-mips@linux-mips.org" Subject: Re: [PATCH] linux-2.4: usb: pr_debug ehci structure bug Message-ID: <20090701064954.GB22396@1wt.eu> References: <4A49CA71.9000604@sphairon.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <4A49CA71.9000604@sphairon.com> User-Agent: Mutt/1.5.11 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23559 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: w@1wt.eu Precedence: bulk X-list: linux-mips On Tue, Jun 30, 2009 at 10:18:57AM +0200, Frank Seidel wrote: > From: Mario Witkowski > > Ehci structure bug on pr_debug. > > Signed-off-by: Mario Witkowski > Signed-off-by: Frank Seidel queued too, thanks Frank! Willy From wuzhangjin@gmail.com Wed Jul 1 09:22:06 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 01 Jul 2009 09:22:12 +0200 (CEST) Received: from wf-out-1314.google.com ([209.85.200.169]:60296 "EHLO wf-out-1314.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492012AbZGAHWG (ORCPT ); Wed, 1 Jul 2009 09:22:06 +0200 Received: by wf-out-1314.google.com with SMTP id 28so254891wfa.21 for ; Wed, 01 Jul 2009 00:16:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:subject:from:reply-to:to:cc :in-reply-to:references:content-type:organization:date:message-id :mime-version:x-mailer:content-transfer-encoding; bh=qSqIM2hwuk5fLj9hd+QBdr7RkwXiBkKCVx9g1CYIBvw=; b=Fe71wJQ4uGbw9Qf9/cfpYajParx03KoDVPkXKoFAgpP1ucq0S6apPKsv1bjMKJGZx6 iHoIo2iGslRcVYYMRAkbpXO+qUGtaumXEU0Isye0bptYHd755Ih2i771TkOEd9I4pwh9 81RpzsLKCB/hS06wTwyhi+ojsOnNF+V506wGs= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=subject:from:reply-to:to:cc:in-reply-to:references:content-type :organization:date:message-id:mime-version:x-mailer :content-transfer-encoding; b=q07QBAgJISnamOT8oyqk8lzBKNC6TnHfybjHEsWcfAWTgTRl3CqKN18rcVyiEJi9iY tToM/N1Jam0EpPLD7/TpLtk03sF2lVk9IUAgs4ohBq2tnD6uUhX51jplDDF8/wxGSVK6 a+WOLr8K2rbcFdw60O7gCQuFjrEOfo0+mcbfU= Received: by 10.142.226.1 with SMTP id y1mr470718wfg.294.1246432600263; Wed, 01 Jul 2009 00:16:40 -0700 (PDT) Received: from ?172.16.2.101? ([222.92.8.142]) by mx.google.com with ESMTPS id 30sm3145928wfd.23.2009.07.01.00.16.36 (version=TLSv1/SSLv3 cipher=RC4-MD5); Wed, 01 Jul 2009 00:16:39 -0700 (PDT) Subject: Re: [BUG] MIPS: Hibernation in the latest linux-mips:master branch not work From: Wu Zhangjin Reply-To: wuzhangjin@gmail.com To: Ralf Baechle , linux-ide@vger.kernel.org Cc: LKML , linux-mips@linux-mips.org, Pavel Machek In-Reply-To: <20090630144540.GA18212@linux-mips.org> References: <1246372868.19049.17.camel@falcon> <20090630144540.GA18212@linux-mips.org> Content-Type: text/plain Organization: DSLab, Lanzhou University, China Date: Wed, 01 Jul 2009 15:16:10 +0800 Message-Id: <1246432570.9660.22.camel@falcon> Mime-Version: 1.0 X-Mailer: Evolution 2.26.1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23560 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips On Tue, 2009-06-30 at 15:45 +0100, Ralf Baechle wrote: > On Tue, Jun 30, 2009 at 10:41:08PM +0800, Wu Zhangjin wrote: > > > I just updated my git repository to the master branch of the latest > > linux-mips git repository, and tested the STD/Hibernation support on > > fuloong2e and yeeloong2f, it failed: > > > > when using the no_console_suspend kernel command line to debug, it > > stopped on: > > > > PM: Shringking memory... done (1000 pages freed) > > PM: Freed 160000 kbytes in 1.68 seconds (95.23 MB/s) > > PM: Creating hibernation image: > > PM: Need to copy 5053 pages > > PM: Hibernation image created (4195 pages copied) > > > > and then, the number indicator light of keyboard works well, but can not > > type anything. > > > > anybody have tested it on another platform? does it work? > > At the time of the merge I tested it on Malta and found it to be working. > Just traced it, the executing path is something like this: hibernate(kernel/power/hibernate.c) --> hibernation_snapshot --> dpm_resume_end --> dpm_resume --> device_resume --> dev->bus->resume(generic_ide_resume), dev_name(dev) = 0.0 --> blk_execute_rq { DECLARE_COMPLETION_ONSTACK(wait); ... wait_for_completion(&wait); // stop here ... } I guess there is a possible bug in the latest ide patches, I'm trying to find which one is 'bad'. the ide driver i used is VIA82CXXX chipset support. Regards, Wu Zhangjin From wuzhangjin@gmail.com Wed Jul 1 16:53:25 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 01 Jul 2009 16:53:31 +0200 (CEST) Received: from ey-out-1920.google.com ([74.125.78.144]:65160 "EHLO ey-out-1920.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1491901AbZGAOxZ (ORCPT ); Wed, 1 Jul 2009 16:53:25 +0200 Received: by ey-out-1920.google.com with SMTP id 13so288631eye.60 for ; Wed, 01 Jul 2009 07:47:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:subject:from:reply-to:to:cc :in-reply-to:references:content-type:organization:date:message-id :mime-version:x-mailer:content-transfer-encoding; bh=9SNE3RoA5diwRl22W/M4Q9oL5HQMHLjqivqM6ZGXK1U=; b=xpT9245YIPL5bAlFazlvdfo1IDGQtddE+Qr8auZ+6Je6fkYHItYk/1jKQQaFMYKPzR 2K8PyoCjNuTzTVeWcJ+cZLAALROgwpuXU87ThrOAa++DAaKM1ybG7kdOpdU1c3JDA3D+ bkB6LmQ5QWK6M632zFywO/xF6lUD2HO1lCfl4= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=subject:from:reply-to:to:cc:in-reply-to:references:content-type :organization:date:message-id:mime-version:x-mailer :content-transfer-encoding; b=o3+PSpFA+j+eYw1yTE5Kpuxxy/rYYIziPjmwBJpmvkVUPmoesqGv5WwL3Z+DEjh8sG 6Q6ye8360b/te59wO42BHjN8/N3oh673EpIR6w/UDLVHSm0xGwpnQWcSTUp/yJ6EIjsN kE7me3OtPrpiiSZ1HaiF9EFpeG7xTKDAxQ5ZY= Received: by 10.211.180.19 with SMTP id h19mr5126504ebp.22.1246459677250; Wed, 01 Jul 2009 07:47:57 -0700 (PDT) Received: from ?172.16.2.101? ([222.92.8.142]) by mx.google.com with ESMTPS id 10sm2235394eyz.1.2009.07.01.07.47.50 (version=TLSv1/SSLv3 cipher=RC4-MD5); Wed, 01 Jul 2009 07:47:56 -0700 (PDT) Subject: Re: [Bug #13663] suspend to ram regression (IDE related) From: Wu Zhangjin Reply-To: wuzhangjin@gmail.com To: Jeff Chua Cc: Etienne Basset , David Miller , rjw@sisk.pl, linux-kernel@vger.kernel.org, kernel-testers@vger.kernel.org, bzolnier@gmail.com, Ralf Baechle , linux-mips@linux-mips.org, linux-ide@vger.kernel.org In-Reply-To: References: <5Hhc7UkUKEO.A.RvE.BjASKB@chimera> <4A489775.6020102@numericable.fr> <20090629.033730.193709457.davem@davemloft.net> <4A48E307.2010208@numericable.fr> Content-Type: text/plain Organization: DSLab, Lanzhou University, China Date: Wed, 01 Jul 2009 22:47:41 +0800 Message-Id: <1246459661.9660.40.camel@falcon> Mime-Version: 1.0 X-Mailer: Evolution 2.26.1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23561 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips On Wed, 2009-07-01 at 22:31 +0800, Jeff Chua wrote: > On Tue, Jun 30, 2009 at 12:21 AM, Jeff Chua wrote: > > > I just tried, and it "seems" to work. Will try a few more cycles. > > STD/STR survived quite a few cycles now. Patch seems to be doing the > right thing. > > On Mon, Jun 29, 2009 at 11:51 PM, Etienne > Basset wrote: > > > To have STR/resume work with current git, I have to : > > > 1) apply Bart's patch > > This is not yet in Linus's tree. And much needed to really fix the problem. > > > 2) revert this commit : a1317f714af7aed60ddc182d0122477cbe36ee9b > Yes, This commit must be reverted, otherwise, STD/Hibernation will not work either. I have tested it on two different loongson-based machines: fuloong2e box and yeeloong2f netbook.(loongson is mips compatiable) Here is what i have traced: hibernate(kernel/power/hibernate.c) --> hibernation_snapshot --> dpm_resume_end --> dpm_resume --> device_resume --> dev->bus->resume(generic_ide_resume), dev_name(dev) = 0.0 --> blk_execute_rq { DECLARE_COMPLETION_ONSTACK(wait); ... wait_for_completion(&wait); // stop here ... } and I have tried to revert this part of the above patch: - - WARN_ON_ONCE(hwif->rq); repeat: prev_port = hwif->host->cur_port; + + if (drive->dev_flags & IDE_DFLAG_BLOCKED) + rq = hwif->rq; + else + WARN_ON_ONCE(hwif->rq); + it works! need more time to test! thanks! Wu Zhangjin From wuzhangjin@gmail.com Wed Jul 1 17:01:04 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 01 Jul 2009 17:01:10 +0200 (CEST) Received: from mail-ew0-f214.google.com ([209.85.219.214]:50811 "EHLO mail-ew0-f214.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1491927AbZGAPBE (ORCPT ); Wed, 1 Jul 2009 17:01:04 +0200 Received: by ewy10 with SMTP id 10so1178282ewy.0 for ; Wed, 01 Jul 2009 07:55:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:subject:from:reply-to:to:cc :in-reply-to:references:content-type:organization:date:message-id :mime-version:x-mailer:content-transfer-encoding; bh=Ps3YqgGnOzQ6rAS+PoZ1aXwq71Nr+yTykKKL9q3K+jo=; b=evJnfkYmk7Rj2zvIdXikk10yOTmYvWn4eaH6Vukoy7Ta7r5DE0SoC4FwHBh1Ix4v06 48VsqrIk5LaWzMZxMhswTNwl8Es+osZfZv3o1xrPW6XzWEwnPq/axP8SnCD/TFEi2yNd hyYbJA5hBzQqeA8ocvGzr6wAQJaR7IiJeH65I= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=subject:from:reply-to:to:cc:in-reply-to:references:content-type :organization:date:message-id:mime-version:x-mailer :content-transfer-encoding; b=DpxXpZ89DLsZHfV7cayd2wCmbH3OQBEliRM3sNbOLP5yiP9oFaj5h8uwN9Y/VqF8ye w11aEfU75RD5JhpW4W41z6nXHHy4ghSdWMCyHUF4lKT4wJh4l229Aeu2KHT4+pMg5kfC SYyhbvapSOaW7QH3JPp13UpNp3WNU0koIJEfs= Received: by 10.210.135.20 with SMTP id i20mr4858066ebd.38.1246460130421; Wed, 01 Jul 2009 07:55:30 -0700 (PDT) Received: from ?172.16.2.101? ([222.92.8.142]) by mx.google.com with ESMTPS id 5sm2976341eyf.52.2009.07.01.07.55.24 (version=TLSv1/SSLv3 cipher=RC4-MD5); Wed, 01 Jul 2009 07:55:29 -0700 (PDT) Subject: Re: [BUG] MIPS: Hibernation in the latest linux-mips:master branch not work From: Wu Zhangjin Reply-To: wuzhangjin@gmail.com To: Ralf Baechle Cc: linux-ide@vger.kernel.org, LKML , linux-mips@linux-mips.org, Pavel Machek , Bartlomiej Zolnierkiewicz , "David S. Miller" In-Reply-To: <1246432570.9660.22.camel@falcon> References: <1246372868.19049.17.camel@falcon> <20090630144540.GA18212@linux-mips.org> <1246432570.9660.22.camel@falcon> Content-Type: text/plain Organization: DSLab, Lanzhou University, China Date: Wed, 01 Jul 2009 22:55:12 +0800 Message-Id: <1246460112.9660.45.camel@falcon> Mime-Version: 1.0 X-Mailer: Evolution 2.26.1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23562 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips On Wed, 2009-07-01 at 15:16 +0800, Wu Zhangjin wrote: > On Tue, 2009-06-30 at 15:45 +0100, Ralf Baechle wrote: > > On Tue, Jun 30, 2009 at 10:41:08PM +0800, Wu Zhangjin wrote: > > > > > I just updated my git repository to the master branch of the latest > > > linux-mips git repository, and tested the STD/Hibernation support on > > > fuloong2e and yeeloong2f, it failed: > > > > > > when using the no_console_suspend kernel command line to debug, it > > > stopped on: > > > > > > PM: Shringking memory... done (1000 pages freed) > > > PM: Freed 160000 kbytes in 1.68 seconds (95.23 MB/s) > > > PM: Creating hibernation image: > > > PM: Need to copy 5053 pages > > > PM: Hibernation image created (4195 pages copied) > > > > > > and then, the number indicator light of keyboard works well, but can not > > > type anything. > > > > > > anybody have tested it on another platform? does it work? > > > > At the time of the merge I tested it on Malta and found it to be working. > > > > Just traced it, the executing path is something like this: > > hibernate(kernel/power/hibernate.c) > --> hibernation_snapshot > --> dpm_resume_end > --> dpm_resume > --> device_resume > --> dev->bus->resume(generic_ide_resume), dev_name(dev) = 0.0 > --> blk_execute_rq > { > DECLARE_COMPLETION_ONSTACK(wait); > ... > wait_for_completion(&wait); // stop here > ... > } > > I guess there is a possible bug in the latest ide patches, I'm trying to > find which one is 'bad'. > There is really a bug in one of ide patches, here it is: commit a1317f714af7aed60ddc182d0122477cbe36ee9b Author: Bartlomiej Zolnierkiewicz Date: Tue Jun 23 23:52:17 2009 -0700 ide: improve handling of Power Management requests Make hwif->rq point to PM request during PM sequence and do not allow any other types of requests to slip in (the old comment was never correct as there should be no such requests generated during PM sequence). Signed-off-by: Bartlomiej Zolnierkiewicz Signed-off-by: David S. Miller I have reverted this part of the above patch, seems works, need more tests: - - WARN_ON_ONCE(hwif->rq); repeat: prev_port = hwif->host->cur_port; + + if (drive->dev_flags & IDE_DFLAG_BLOCKED) + rq = hwif->rq; + else + WARN_ON_ONCE(hwif->rq); + please get more information from this bug report: [Bug #13663] suspend to ram regression (IDE related) http://lkml.org/lkml/2009/6/29/341 Regards! Wu Zhangjin From macro@linux-mips.org Wed Jul 1 17:46:48 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 01 Jul 2009 17:46:51 +0200 (CEST) Received: from localhost.localdomain ([127.0.0.1]:42850 "EHLO localhost.localdomain" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492039AbZGAPqs (ORCPT ); Wed, 1 Jul 2009 17:46:48 +0200 Date: Wed, 1 Jul 2009 16:46:48 +0100 (BST) From: "Maciej W. Rozycki" To: Ralf Baechle cc: Dmitri Vorobiev , linux-mips@linux-mips.org Subject: Re: [PATCH] [MIPS] Malta: Remove unneeded function protos from malta-reset.c In-Reply-To: <20090701063116.GA6101@linux-mips.org> Message-ID: References: <1246035565-24015-1-git-send-email-dmitri.vorobiev@movial.com> <20090628181702.GB20084@linux-mips.org> <20090701063116.GA6101@linux-mips.org> User-Agent: Alpine 2.00 (LFD 1167 2008-08-23) MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23563 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: macro@linux-mips.org Precedence: bulk X-list: linux-mips On Wed, 1 Jul 2009, Ralf Baechle wrote: > Code written to require intimate knowledge of all operator priorities is > probably as bad as overuse. Here a few examples: > > return (1); > #define FOO (42) > a = (b + c); > a = (b + c) + d; > a = (b * c) + (d * e); > if ((a > b) && (a < c)) Sometimes additional brackets are useful to emphasise some logical grouping of entities used, so I would accept even such a construct as: a = (b + c + d) + (e + f); to bring attention of the reader that a, b and c refer to something other than e and f, but yes, it would require explicit justification and I wouldn't consider it a blanket accept statement for such kinds of expressions. The #define case makes my eyes hurt. OTOH we require unnecessary brackets in the context of sizeof. ;) Maciej From bzolnier@gmail.com Wed Jul 1 18:21:17 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 01 Jul 2009 18:21:24 +0200 (CEST) Received: from mail-fx0-f212.google.com ([209.85.220.212]:63358 "EHLO mail-fx0-f212.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492114AbZGAQVR (ORCPT ); Wed, 1 Jul 2009 18:21:17 +0200 Received: by fxm8 with SMTP id 8so468091fxm.0 for ; Wed, 01 Jul 2009 09:15:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:subject:date :user-agent:cc:references:in-reply-to:mime-version :content-disposition:message-id:content-type :content-transfer-encoding; bh=zOjJh9hoWunbw/dAGMndm70LzBljmpJ3fEwAl42viro=; b=u6myhBT+uwkGkgRYDq/KXSeAW5oFTxbC4Bh1is4hxJejH9aCkmxXhd2NN0mxhGnLe2 RChxkR1ntXIQoOCht9Icc9at9QIZXZgIwCFsivxYZyO4q7AipSBHptXXt50Ln98QZUtP def+/2uFAf8FA2WcmcbQFHDilBu5dAuHmfAvQ= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:subject:date:user-agent:cc:references:in-reply-to :mime-version:content-disposition:message-id:content-type :content-transfer-encoding; b=WfU+9CAOiqfE1XChqJbYYcJfa1irnofHwO4ZyN5bvy69YQzIS7KnJGqVr6SsPX8kIS TPRgUdYvgywLWQso+ceh4bUh8dp7U+NcSe30Btc5S3hpyhJYapGgkOhADTRItA0hcrK1 Z/IINGx7sQLIS3DAEorpGY0skZYEa9Gn+IxAg= Received: by 10.103.173.5 with SMTP id a5mr5682861mup.15.1246464942573; Wed, 01 Jul 2009 09:15:42 -0700 (PDT) Received: from localhost.localdomain (chello089077034197.chello.pl [89.77.34.197]) by mx.google.com with ESMTPS id j2sm6654997mue.12.2009.07.01.09.15.41 (version=TLSv1/SSLv3 cipher=RC4-MD5); Wed, 01 Jul 2009 09:15:41 -0700 (PDT) From: Bartlomiej Zolnierkiewicz To: wuzhangjin@gmail.com Subject: Re: [Bug #13663] suspend to ram regression (IDE related) Date: Wed, 1 Jul 2009 18:21:25 +0200 User-Agent: KMail/1.11.4 (Linux/2.6.31-rc1-next-20090701-03251-gbe98b01-dirty; KDE/4.2.4; i686; ; ) Cc: Jeff Chua , Etienne Basset , David Miller , rjw@sisk.pl, linux-kernel@vger.kernel.org, kernel-testers@vger.kernel.org, Ralf Baechle , linux-mips@linux-mips.org, linux-ide@vger.kernel.org References: <1246459661.9660.40.camel@falcon> In-Reply-To: <1246459661.9660.40.camel@falcon> MIME-Version: 1.0 Content-Disposition: inline Message-Id: <200907011821.26091.bzolnier@gmail.com> Content-Type: Text/Plain; charset="iso-8859-15" Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23564 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: bzolnier@gmail.com Precedence: bulk X-list: linux-mips On Wednesday 01 July 2009 16:47:41 Wu Zhangjin wrote: > On Wed, 2009-07-01 at 22:31 +0800, Jeff Chua wrote: > > On Tue, Jun 30, 2009 at 12:21 AM, Jeff Chua wrote: > > > > > I just tried, and it "seems" to work. Will try a few more cycles. > > > > STD/STR survived quite a few cycles now. Patch seems to be doing the > > right thing. > > > > On Mon, Jun 29, 2009 at 11:51 PM, Etienne > > Basset wrote: > > > > > To have STR/resume work with current git, I have to : > > > > > 1) apply Bart's patch > > > > This is not yet in Linus's tree. And much needed to really fix the problem. > > > > > 2) revert this commit : a1317f714af7aed60ddc182d0122477cbe36ee9b > > > > Yes, This commit must be reverted, otherwise, STD/Hibernation will not > work either. I have tested it on two different loongson-based machines: > fuloong2e box and yeeloong2f netbook.(loongson is mips compatiable) Since it seems like Dave is taking his sweet time with doing the revert I stared at the code a bit more and I think that I finally found the bug (thanks to your debugging work for giving me the right hint!). The patch needs to take into the account a new code introduced by the recent block layer changes (commit 8f6205cd572fece673da0255d74843680f67f879): @@ -555,8 +560,11 @@ repeat: startstop = start_request(drive, rq); spin_lock_irq(&hwif->lock); - if (startstop == ide_stopped) + if (startstop == ide_stopped) { + rq = hwif->rq; + hwif->rq = NULL; goto repeat; + } } else goto plug_device; out: and not zero hwif->rq if the device is blocked. Could you try the attached patch and see if it fixes the issue? [ Dave: while I appreciate fast handling of my patches I had strongly suggested giving this particular one some extra testing (because there were a lot of changes in between the time that it has been tested against other kernel subsystems). Yet, it seems that its linux-next exposure was minimal at best.. :( ] --- drivers/ide/ide-io.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) Index: b/drivers/ide/ide-io.c =================================================================== --- a/drivers/ide/ide-io.c +++ b/drivers/ide/ide-io.c @@ -532,7 +532,8 @@ repeat: if (startstop == ide_stopped) { rq = hwif->rq; - hwif->rq = NULL; + if ((drive->dev_flags & IDE_DFLAG_BLOCKED) == 0) + hwif->rq = NULL; goto repeat; } } else From bzolnier@gmail.com Wed Jul 1 18:31:38 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 01 Jul 2009 18:31:44 +0200 (CEST) Received: from mail-fx0-f212.google.com ([209.85.220.212]:47965 "EHLO mail-fx0-f212.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492131AbZGAQbh (ORCPT ); Wed, 1 Jul 2009 18:31:37 +0200 Received: by fxm8 with SMTP id 8so476113fxm.0 for ; Wed, 01 Jul 2009 09:26:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:subject:date :user-agent:cc:references:in-reply-to:mime-version :content-disposition:message-id:content-type :content-transfer-encoding; bh=z1b4hoO9D9Jta4B3k3/fokeTJTR0PBC1Wb+B3cALty0=; b=JjjrfQ0l83Uj4kWucPCXlwLSvfiQ6TdXqqvMZU0CiLjbk8vdme5fIhHF6XSlvv6Vxg 2drSGwqgenBdAp1KLHxfbIN/Ms0hbpJ0/l3B2E+guTplLlpBOQqvR6lVpktdj4EMGRAX ttN4eHjNxQghV4VbDaC3BCRc/mxakasE2lDJY= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:subject:date:user-agent:cc:references:in-reply-to :mime-version:content-disposition:message-id:content-type :content-transfer-encoding; b=oqAYUgujPnqIWfMpBxOqQ7+Uh+/XU0cMgJyktvrP43e/AkshqKlojCV/hpqbtJj6m8 590oOr9sDKfBuQQ4lKzk4uAuoenvzEwypAiCRZc6DJ79QlqgGrn35ITw5DaYoFO3qsre fElb8ByFi5tGhbmxStTxngumTjf2fmFX9oyQ0= Received: by 10.103.175.8 with SMTP id c8mr5691891mup.117.1246465564114; Wed, 01 Jul 2009 09:26:04 -0700 (PDT) Received: from localhost.localdomain (chello089077034197.chello.pl [89.77.34.197]) by mx.google.com with ESMTPS id u9sm6795536muf.37.2009.07.01.09.26.03 (version=TLSv1/SSLv3 cipher=RC4-MD5); Wed, 01 Jul 2009 09:26:03 -0700 (PDT) From: Bartlomiej Zolnierkiewicz To: wuzhangjin@gmail.com Subject: Re: [Bug #13663] suspend to ram regression (IDE related) Date: Wed, 1 Jul 2009 18:29:15 +0200 User-Agent: KMail/1.11.4 (Linux/2.6.31-rc1-next-20090701-03251-gbe98b01-dirty; KDE/4.2.4; i686; ; ) Cc: Jeff Chua , Etienne Basset , David Miller , rjw@sisk.pl, linux-kernel@vger.kernel.org, kernel-testers@vger.kernel.org, Ralf Baechle , linux-mips@linux-mips.org, linux-ide@vger.kernel.org References: <1246459661.9660.40.camel@falcon> <200907011821.26091.bzolnier@gmail.com> In-Reply-To: <200907011821.26091.bzolnier@gmail.com> MIME-Version: 1.0 Content-Disposition: inline Message-Id: <200907011829.16850.bzolnier@gmail.com> Content-Type: Text/Plain; charset="iso-8859-15" Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23565 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: bzolnier@gmail.com Precedence: bulk X-list: linux-mips On Wednesday 01 July 2009 18:21:25 Bartlomiej Zolnierkiewicz wrote: > On Wednesday 01 July 2009 16:47:41 Wu Zhangjin wrote: > > On Wed, 2009-07-01 at 22:31 +0800, Jeff Chua wrote: > > > On Tue, Jun 30, 2009 at 12:21 AM, Jeff Chua wrote: > > > > > > > I just tried, and it "seems" to work. Will try a few more cycles. > > > > > > STD/STR survived quite a few cycles now. Patch seems to be doing the > > > right thing. > > > > > > On Mon, Jun 29, 2009 at 11:51 PM, Etienne > > > Basset wrote: > > > > > > > To have STR/resume work with current git, I have to : > > > > > > > 1) apply Bart's patch > > > > > > This is not yet in Linus's tree. And much needed to really fix the problem. > > > > > > > 2) revert this commit : a1317f714af7aed60ddc182d0122477cbe36ee9b > > > > > > > Yes, This commit must be reverted, otherwise, STD/Hibernation will not > > work either. I have tested it on two different loongson-based machines: > > fuloong2e box and yeeloong2f netbook.(loongson is mips compatiable) > > Since it seems like Dave is taking his sweet time with doing the revert > I stared at the code a bit more and I think that I finally found the bug > (thanks to your debugging work for giving me the right hint!). > > The patch needs to take into the account a new code introduced by the recent > block layer changes (commit 8f6205cd572fece673da0255d74843680f67f879): > > @@ -555,8 +560,11 @@ repeat: > startstop = start_request(drive, rq); > spin_lock_irq(&hwif->lock); > > - if (startstop == ide_stopped) > + if (startstop == ide_stopped) { > + rq = hwif->rq; > + hwif->rq = NULL; > goto repeat; > + } > } else > goto plug_device; > out: > > and not zero hwif->rq if the device is blocked. > > Could you try the attached patch and see if it fixes the issue? Here is the more complete version, also taking into the account changes in ide_intr() and ide_timer_expiry(): --- drivers/ide/ide-io.c | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) Index: b/drivers/ide/ide-io.c =================================================================== --- a/drivers/ide/ide-io.c +++ b/drivers/ide/ide-io.c @@ -532,7 +532,8 @@ repeat: if (startstop == ide_stopped) { rq = hwif->rq; - hwif->rq = NULL; + if ((drive->dev_flags & IDE_DFLAG_BLOCKED) == 0) + hwif->rq = NULL; goto repeat; } } else @@ -679,8 +680,10 @@ void ide_timer_expiry (unsigned long dat spin_lock_irq(&hwif->lock); enable_irq(hwif->irq); if (startstop == ide_stopped && hwif->polling == 0) { - rq_in_flight = hwif->rq; - hwif->rq = NULL; + if ((drive->dev_flags & IDE_DFLAG_BLOCKED) == 0) { + rq_in_flight = hwif->rq; + hwif->rq = NULL; + } ide_unlock_port(hwif); plug_device = 1; } @@ -856,8 +859,10 @@ irqreturn_t ide_intr (int irq, void *dev */ if (startstop == ide_stopped && hwif->polling == 0) { BUG_ON(hwif->handler); - rq_in_flight = hwif->rq; - hwif->rq = NULL; + if ((drive->dev_flags & IDE_DFLAG_BLOCKED) == 0) { + rq_in_flight = hwif->rq; + hwif->rq = NULL; + } ide_unlock_port(hwif); plug_device = 1; } From ralf@linux-mips.org Wed Jul 1 18:59:14 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 01 Jul 2009 18:59:17 +0200 (CEST) Received: (from localhost user: 'ralf' uid#500 fake: STDIN (ralf@eddie.linux-mips.org)) by ftp.linux-mips.org id S1491794AbZGAQ7O for <"|/home/ecartis/ecartis -s linux-mips">; Wed, 1 Jul 2009 18:59:14 +0200 Message-Id: <20090701112926.825088732@linux-mips.org> User-Agent: quilt/0.47-1 Date: Wed, 01 Jul 2009 12:29:26 +0100 From: Ralf Baechle To: linux-mips@linux-mips.org, trivial@kernel.org, linux-kernel@vger.kernel.org, linux-pcmcia@lists.infradead.org, Greg Kroah-Hartman , linux-usb@vger.kernel.org, netdev@vger.kernel.org, Maxime Bizon , Florian Fainelli Subject: [patch 00/12] Add support for Broadcom BCM63xx SoCs Content-Length: 246 Lines: 6 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-archive-position: 23566 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips This is a patch series which has been sitting in the linux-bcm63xx git repository for quite a while. I'm posting this series for it to receive the necessary review - in particular the drivers have so far been ignored virtually entirely. Ralf From ralf@linux-mips.org Wed Jul 1 19:07:10 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 01 Jul 2009 19:07:12 +0200 (CEST) Received: (from localhost user: 'ralf' uid#500 fake: STDIN (ralf@eddie.linux-mips.org)) by ftp.linux-mips.org id S1491864AbZGARHK for <"|/home/ecartis/ecartis -s linux-mips">; Wed, 1 Jul 2009 19:07:10 +0200 Message-Id: <20090701120939.353587047@linux-mips.org> User-Agent: quilt/0.47-1 Date: Wed, 01 Jul 2009 12:29:27 +0100 From: Ralf Baechle To: linux-mips@linux-mips.org Cc: Maxime Bizon , Florian Fainelli Subject: [patch 01/12] MIPS: BCM63XX: Add Broadcom 63xx CPU definitions. References: <20090701112926.825088732@linux-mips.org> Content-Disposition: inline; filename=0001.patch Content-Length: 2573 Lines: 96 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-archive-position: 23567 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips From: Maxime Bizon Todo: Nothing ever detects CPU_BCM6338 but the code tests for it anyway. Signed-off-by: Maxime Bizon Signed-off-by: Ralf Baechle arch/mips/include/asm/cpu.h | 7 +++++++ arch/mips/kernel/cpu-probe.c | 24 ++++++++++++++++++++++++ arch/mips/mm/tlbex.c | 4 ++++ 3 files changed, 35 insertions(+) --- a/arch/mips/include/asm/cpu.h +++ b/arch/mips/include/asm/cpu.h @@ -113,6 +113,12 @@ #define PRID_IMP_BCM4710 0x4000 #define PRID_IMP_BCM3302 0x9000 +#define PRID_IMP_BCM6338 0x9000 +#define PRID_IMP_BCM6345 0x8000 +#define PRID_IMP_BCM6348 0x9100 +#define PRID_IMP_BCM4350 0xA000 +#define PRID_REV_BCM6358 0x0010 +#define PRID_REV_BCM6368 0x0030 /* * These are the PRID's for when 23:16 == PRID_COMP_CAVIUM @@ -210,6 +216,7 @@ enum cpu_type_enum { */ CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K, CPU_ALCHEMY, CPU_PR4450, CPU_BCM3302, CPU_BCM4710, + CPU_BCM6338, CPU_BCM6345, CPU_BCM6348, CPU_BCM6358, /* * MIPS64 class processors --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -159,6 +159,10 @@ void __init check_wait(void) case CPU_25KF: case CPU_PR4450: case CPU_BCM3302: + case CPU_BCM6338: + case CPU_BCM6345: + case CPU_BCM6348: + case CPU_BCM6358: case CPU_CAVIUM_OCTEON: cpu_wait = r4k_wait; break; @@ -857,6 +861,7 @@ static inline void cpu_probe_broadcom(st decode_configs(c); switch (c->processor_id & 0xff00) { case PRID_IMP_BCM3302: + /* same as PRID_IMP_BCM6338 */ c->cputype = CPU_BCM3302; __cpu_name[cpu] = "Broadcom BCM3302"; break; @@ -864,6 +869,25 @@ static inline void cpu_probe_broadcom(st c->cputype = CPU_BCM4710; __cpu_name[cpu] = "Broadcom BCM4710"; break; + case PRID_IMP_BCM6345: + c->cputype = CPU_BCM6345; + __cpu_name[cpu] = "Broadcom BCM6345"; + break; + case PRID_IMP_BCM6348: + c->cputype = CPU_BCM6348; + __cpu_name[cpu] = "Broadcom BCM6348"; + break; + case PRID_IMP_BCM4350: + switch (c->processor_id & 0xf0) { + case PRID_REV_BCM6358: + c->cputype = CPU_BCM6358; + __cpu_name[cpu] = "Broadcom BCM6358"; + break; + default: + c->cputype = CPU_UNKNOWN; + break; + } + break; } } --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -321,6 +321,10 @@ static void __cpuinit build_tlb_write_en case CPU_BCM3302: case CPU_BCM4710: case CPU_LOONGSON2: + case CPU_BCM6338: + case CPU_BCM6345: + case CPU_BCM6348: + case CPU_BCM6358: case CPU_R5500: if (m4kc_tlbp_war()) uasm_i_nop(p); From ralf@linux-mips.org Wed Jul 1 19:07:29 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 01 Jul 2009 19:07:38 +0200 (CEST) Received: (from localhost user: 'ralf' uid#500 fake: STDIN (ralf@eddie.linux-mips.org)) by ftp.linux-mips.org id S1491865AbZGARHK for <"|/home/ecartis/ecartis -s linux-mips">; Wed, 1 Jul 2009 19:07:10 +0200 Message-Id: <20090701120939.442145090@linux-mips.org> User-Agent: quilt/0.47-1 Date: Wed, 01 Jul 2009 12:29:28 +0100 From: Ralf Baechle To: linux-mips@linux-mips.org Cc: Maxime Bizon , Florian Fainelli Subject: [patch 02/12] MIPS: BCM63XX: Add support for the Broadcom BCM63xx family of SOCs. References: <20090701112926.825088732@linux-mips.org> Content-Disposition: inline; filename=0002.patch Content-Length: 83141 Lines: 2874 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-archive-position: 23568 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips From: Maxime Bizon Signed-off-by: Maxime Bizon Signed-off-by: Florian Fainelli Signed-off-by: Ralf Baechle arch/mips/Kconfig | 18 arch/mips/Makefile | 7 arch/mips/bcm63xx/Kconfig | 9 arch/mips/bcm63xx/Makefile | 4 arch/mips/bcm63xx/clk.c | 220 +++ arch/mips/bcm63xx/cpu.c | 245 ++++ arch/mips/bcm63xx/cs.c | 144 ++ arch/mips/bcm63xx/early_printk.c | 30 arch/mips/bcm63xx/gpio.c | 128 ++ arch/mips/bcm63xx/irq.c | 253 ++++ arch/mips/bcm63xx/prom.c | 43 arch/mips/bcm63xx/setup.c | 111 + arch/mips/bcm63xx/timer.c | 205 +++ arch/mips/include/asm/fixmap.h | 4 arch/mips/include/asm/mach-bcm63xx/bcm63xx_clk.h | 11 arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h | 314 +++++ arch/mips/include/asm/mach-bcm63xx/bcm63xx_cs.h | 10 arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h | 10 arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h | 93 + arch/mips/include/asm/mach-bcm63xx/bcm63xx_irq.h | 15 arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 728 +++++++++++++ arch/mips/include/asm/mach-bcm63xx/bcm63xx_timer.h | 11 arch/mips/include/asm/mach-bcm63xx/cpu-feature-overrides.h | 51 arch/mips/include/asm/mach-bcm63xx/gpio.h | 17 arch/mips/include/asm/mach-bcm63xx/war.h | 25 25 files changed, 2705 insertions(+), 1 deletion(-) create mode 100644 arch/mips/bcm63xx/Kconfig create mode 100644 arch/mips/bcm63xx/Makefile create mode 100644 arch/mips/bcm63xx/clk.c create mode 100644 arch/mips/bcm63xx/cpu.c create mode 100644 arch/mips/bcm63xx/cs.c create mode 100644 arch/mips/bcm63xx/early_printk.c create mode 100644 arch/mips/bcm63xx/gpio.c create mode 100644 arch/mips/bcm63xx/irq.c create mode 100644 arch/mips/bcm63xx/prom.c create mode 100644 arch/mips/bcm63xx/setup.c create mode 100644 arch/mips/bcm63xx/timer.c create mode 100644 arch/mips/include/asm/mach-bcm63xx/bcm63xx_clk.h create mode 100644 arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h create mode 100644 arch/mips/include/asm/mach-bcm63xx/bcm63xx_cs.h create mode 100644 arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h create mode 100644 arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h create mode 100644 arch/mips/include/asm/mach-bcm63xx/bcm63xx_irq.h create mode 100644 arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h create mode 100644 arch/mips/include/asm/mach-bcm63xx/bcm63xx_timer.h create mode 100644 arch/mips/include/asm/mach-bcm63xx/cpu-feature-overrides.h create mode 100644 arch/mips/include/asm/mach-bcm63xx/gpio.h create mode 100644 arch/mips/include/asm/mach-bcm63xx/war.h --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -60,7 +60,7 @@ config BASLER_EXCITE Basler Vision Technologies AG. config BCM47XX - bool "BCM47XX based boards" + bool "Broadcom BCM47XX based boards" select CEVT_R4K select CSRC_R4K select DMA_NONCOHERENT @@ -80,6 +80,21 @@ config BCM47XX help Support for BCM47XX based boards +config BCM63XX + bool "Broadcom BCM63XX based boards" + select CEVT_R4K + select CSRC_R4K + select DMA_NONCOHERENT + select IRQ_CPU + select SYS_HAS_CPU_MIPS32_R1 + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_BIG_ENDIAN + select SYS_HAS_EARLY_PRINTK + select SWAP_IO_SPACE + select ARCH_REQUIRE_GPIOLIB + help + Support for BCM63XX based boards + config MIPS_COBALT bool "Cobalt Server" select CEVT_R4K @@ -659,6 +674,7 @@ endchoice source "arch/mips/alchemy/Kconfig" source "arch/mips/basler/excite/Kconfig" +source "arch/mips/bcm63xx/Kconfig" source "arch/mips/jazz/Kconfig" source "arch/mips/lasat/Kconfig" source "arch/mips/pmc-sierra/Kconfig" --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -560,6 +560,13 @@ cflags-$(CONFIG_BCM47XX) += -I$(srctree) load-$(CONFIG_BCM47XX) := 0xffffffff80001000 # +# Broadcom BCM63XX boards +# +core-$(CONFIG_BCM63XX) += arch/mips/bcm63xx/ +cflags-$(CONFIG_BCM63XX) += -I$(srctree)/arch/mips/include/asm/mach-bcm63xx/ +load-$(CONFIG_BCM63XX) := 0xffffffff80010000 + +# # SNI RM # core-$(CONFIG_SNI_RM) += arch/mips/sni/ --- /dev/null +++ b/arch/mips/bcm63xx/Kconfig @@ -0,0 +1,9 @@ +menu "CPU support" + depends on BCM63XX + +config BCM63XX_CPU_6348 + bool "support 6348 CPU" + +config BCM63XX_CPU_6358 + bool "support 6358 CPU" +endmenu --- /dev/null +++ b/arch/mips/bcm63xx/Makefile @@ -0,0 +1,4 @@ +obj-y += clk.o cpu.o cs.o gpio.o irq.o prom.o setup.o timer.o +obj-$(CONFIG_EARLY_PRINTK) += early_printk.o + +EXTRA_CFLAGS += -Werror --- /dev/null +++ b/arch/mips/bcm63xx/clk.c @@ -0,0 +1,220 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2008 Maxime Bizon + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +DEFINE_MUTEX(clocks_mutex); + + +static void clk_enable_unlocked(struct clk *clk) +{ + if (clk->set && (clk->usage++) == 0) + clk->set(clk, 1); +} + +static void clk_disable_unlocked(struct clk *clk) +{ + if (clk->set && (--clk->usage) == 0) + clk->set(clk, 0); +} + +static void bcm_hwclock_set(u32 mask, int enable) +{ + u32 reg; + + reg = bcm_perf_readl(PERF_CKCTL_REG); + if (enable) + reg |= mask; + else + reg &= ~mask; + bcm_perf_writel(reg, PERF_CKCTL_REG); +} + +/* + * Ethernet MAC "misc" clock: dma clocks and main clock on 6348 + */ +static void enet_misc_set(struct clk *clk, int enable) +{ + u32 mask; + + if (BCMCPU_IS_6348()) + mask = CKCTL_6348_ENET_EN; + else + /* BCMCPU_IS_6358 */ + mask = CKCTL_6358_EMUSB_EN; + bcm_hwclock_set(mask, enable); +} + +static struct clk clk_enet_misc = { + .set = enet_misc_set, +}; + +/* + * Ethernet MAC clocks: only revelant on 6358, silently enable misc + * clocks + */ +static void enetx_set(struct clk *clk, int enable) +{ + if (enable) + clk_enable_unlocked(&clk_enet_misc); + else + clk_disable_unlocked(&clk_enet_misc); + + if (BCMCPU_IS_6358()) { + u32 mask; + + if (clk->id == 0) + mask = CKCTL_6358_ENET0_EN; + else + mask = CKCTL_6358_ENET1_EN; + bcm_hwclock_set(mask, enable); + } +} + +static struct clk clk_enet0 = { + .id = 0, + .set = enetx_set, +}; + +static struct clk clk_enet1 = { + .id = 1, + .set = enetx_set, +}; + +/* + * Ethernet PHY clock + */ +static void ephy_set(struct clk *clk, int enable) +{ + if (!BCMCPU_IS_6358()) + return; + bcm_hwclock_set(CKCTL_6358_EPHY_EN, enable); +} + + +static struct clk clk_ephy = { + .set = ephy_set, +}; + +/* + * PCM clock + */ +static void pcm_set(struct clk *clk, int enable) +{ + if (!BCMCPU_IS_6358()) + return; + bcm_hwclock_set(CKCTL_6358_PCM_EN, enable); +} + +static struct clk clk_pcm = { + .set = pcm_set, +}; + +/* + * USB host clock + */ +static void usbh_set(struct clk *clk, int enable) +{ + if (!BCMCPU_IS_6348()) + return; + bcm_hwclock_set(CKCTL_6348_USBH_EN, enable); +} + +static struct clk clk_usbh = { + .set = usbh_set, +}; + +/* + * SPI clock + */ +static void spi_set(struct clk *clk, int enable) +{ + u32 mask; + + if (BCMCPU_IS_6348()) + mask = CKCTL_6348_SPI_EN; + else + /* BCMCPU_IS_6358 */ + mask = CKCTL_6358_SPI_EN; + bcm_hwclock_set(mask, enable); +} + +static struct clk clk_spi = { + .set = spi_set, +}; + +/* + * Internal peripheral clock + */ +static struct clk clk_periph = { + .rate = (50 * 1000 * 1000), +}; + + +/* + * Linux clock API implementation + */ +int clk_enable(struct clk *clk) +{ + mutex_lock(&clocks_mutex); + clk_enable_unlocked(clk); + mutex_unlock(&clocks_mutex); + return 0; +} + +EXPORT_SYMBOL(clk_enable); + +void clk_disable(struct clk *clk) +{ + mutex_lock(&clocks_mutex); + clk_disable_unlocked(clk); + mutex_unlock(&clocks_mutex); +} + +EXPORT_SYMBOL(clk_disable); + +unsigned long clk_get_rate(struct clk *clk) +{ + return clk->rate; +} + +EXPORT_SYMBOL(clk_get_rate); + +struct clk *clk_get(struct device *dev, const char *id) +{ + if (!strcmp(id, "enet0")) + return &clk_enet0; + if (!strcmp(id, "enet1")) + return &clk_enet1; + if (!strcmp(id, "ephy")) + return &clk_ephy; + if (!strcmp(id, "usbh")) + return &clk_usbh; + if (!strcmp(id, "spi")) + return &clk_spi; + if (!strcmp(id, "periph")) + return &clk_periph; + if (BCMCPU_IS_6358() && !strcmp(id, "pcm")) + return &clk_pcm; + return ERR_PTR(-ENOENT); +} + +EXPORT_SYMBOL(clk_get); + +void clk_put(struct clk *clk) +{ +} + +EXPORT_SYMBOL(clk_put); --- /dev/null +++ b/arch/mips/bcm63xx/cpu.c @@ -0,0 +1,245 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2008 Maxime Bizon + */ + +#include +#include +#include +#include +#include +#include +#include + +const unsigned long *bcm63xx_regs_base; +EXPORT_SYMBOL(bcm63xx_regs_base); + +const int *bcm63xx_irqs; +EXPORT_SYMBOL(bcm63xx_irqs); + +static u16 bcm63xx_cpu_id; +static u16 bcm63xx_cpu_rev; +static unsigned int bcm63xx_cpu_freq; +static unsigned int bcm63xx_memory_size; + +/* + * 6348 register sets and irqs + */ +static const unsigned long bcm96348_regs_base[] = { + [RSET_DSL_LMEM] = BCM_6348_DSL_LMEM_BASE, + [RSET_PERF] = BCM_6348_PERF_BASE, + [RSET_TIMER] = BCM_6348_TIMER_BASE, + [RSET_WDT] = BCM_6348_WDT_BASE, + [RSET_UART0] = BCM_6348_UART0_BASE, + [RSET_GPIO] = BCM_6348_GPIO_BASE, + [RSET_SPI] = BCM_6348_SPI_BASE, + [RSET_OHCI0] = BCM_6348_OHCI0_BASE, + [RSET_OHCI_PRIV] = BCM_6348_OHCI_PRIV_BASE, + [RSET_USBH_PRIV] = BCM_6348_USBH_PRIV_BASE, + [RSET_MPI] = BCM_6348_MPI_BASE, + [RSET_PCMCIA] = BCM_6348_PCMCIA_BASE, + [RSET_SDRAM] = BCM_6348_SDRAM_BASE, + [RSET_DSL] = BCM_6348_DSL_BASE, + [RSET_ENET0] = BCM_6348_ENET0_BASE, + [RSET_ENET1] = BCM_6348_ENET1_BASE, + [RSET_ENETDMA] = BCM_6348_ENETDMA_BASE, + [RSET_MEMC] = BCM_6348_MEMC_BASE, + [RSET_DDR] = BCM_6348_DDR_BASE, +}; + +static const int bcm96348_irqs[] = { + [IRQ_TIMER] = BCM_6348_TIMER_IRQ, + [IRQ_UART0] = BCM_6348_UART0_IRQ, + [IRQ_DSL] = BCM_6348_DSL_IRQ, + [IRQ_ENET0] = BCM_6348_ENET0_IRQ, + [IRQ_ENET1] = BCM_6348_ENET1_IRQ, + [IRQ_ENET_PHY] = BCM_6348_ENET_PHY_IRQ, + [IRQ_OHCI0] = BCM_6348_OHCI0_IRQ, + [IRQ_PCMCIA] = BCM_6348_PCMCIA_IRQ, + [IRQ_ENET0_RXDMA] = BCM_6348_ENET0_RXDMA_IRQ, + [IRQ_ENET0_TXDMA] = BCM_6348_ENET0_TXDMA_IRQ, + [IRQ_ENET1_RXDMA] = BCM_6348_ENET1_RXDMA_IRQ, + [IRQ_ENET1_TXDMA] = BCM_6348_ENET1_TXDMA_IRQ, + [IRQ_PCI] = BCM_6348_PCI_IRQ, +}; + +/* + * 6358 register sets and irqs + */ +static const unsigned long bcm96358_regs_base[] = { + [RSET_DSL_LMEM] = BCM_6358_DSL_LMEM_BASE, + [RSET_PERF] = BCM_6358_PERF_BASE, + [RSET_TIMER] = BCM_6358_TIMER_BASE, + [RSET_WDT] = BCM_6358_WDT_BASE, + [RSET_UART0] = BCM_6358_UART0_BASE, + [RSET_GPIO] = BCM_6358_GPIO_BASE, + [RSET_SPI] = BCM_6358_SPI_BASE, + [RSET_OHCI0] = BCM_6358_OHCI0_BASE, + [RSET_EHCI0] = BCM_6358_EHCI0_BASE, + [RSET_OHCI_PRIV] = BCM_6358_OHCI_PRIV_BASE, + [RSET_USBH_PRIV] = BCM_6358_USBH_PRIV_BASE, + [RSET_MPI] = BCM_6358_MPI_BASE, + [RSET_PCMCIA] = BCM_6358_PCMCIA_BASE, + [RSET_SDRAM] = BCM_6358_SDRAM_BASE, + [RSET_DSL] = BCM_6358_DSL_BASE, + [RSET_ENET0] = BCM_6358_ENET0_BASE, + [RSET_ENET1] = BCM_6358_ENET1_BASE, + [RSET_ENETDMA] = BCM_6358_ENETDMA_BASE, + [RSET_MEMC] = BCM_6358_MEMC_BASE, + [RSET_DDR] = BCM_6358_DDR_BASE, +}; + +static const int bcm96358_irqs[] = { + [IRQ_TIMER] = BCM_6358_TIMER_IRQ, + [IRQ_UART0] = BCM_6358_UART0_IRQ, + [IRQ_DSL] = BCM_6358_DSL_IRQ, + [IRQ_ENET0] = BCM_6358_ENET0_IRQ, + [IRQ_ENET1] = BCM_6358_ENET1_IRQ, + [IRQ_ENET_PHY] = BCM_6358_ENET_PHY_IRQ, + [IRQ_OHCI0] = BCM_6358_OHCI0_IRQ, + [IRQ_EHCI0] = BCM_6358_EHCI0_IRQ, + [IRQ_PCMCIA] = BCM_6358_PCMCIA_IRQ, + [IRQ_ENET0_RXDMA] = BCM_6358_ENET0_RXDMA_IRQ, + [IRQ_ENET0_TXDMA] = BCM_6358_ENET0_TXDMA_IRQ, + [IRQ_ENET1_RXDMA] = BCM_6358_ENET1_RXDMA_IRQ, + [IRQ_ENET1_TXDMA] = BCM_6358_ENET1_TXDMA_IRQ, + [IRQ_PCI] = BCM_6358_PCI_IRQ, +}; + +u16 __bcm63xx_get_cpu_id(void) +{ + return bcm63xx_cpu_id; +} + +EXPORT_SYMBOL(__bcm63xx_get_cpu_id); + +u16 bcm63xx_get_cpu_rev(void) +{ + return bcm63xx_cpu_rev; +} + +EXPORT_SYMBOL(bcm63xx_get_cpu_rev); + +unsigned int bcm63xx_get_cpu_freq(void) +{ + return bcm63xx_cpu_freq; +} + +unsigned int bcm63xx_get_memory_size(void) +{ + return bcm63xx_memory_size; +} + +static unsigned int detect_cpu_clock(void) +{ + unsigned int tmp, n1 = 0, n2 = 0, m1 = 0; + + /* + * frequency depends on PLL configuration: + */ + if (BCMCPU_IS_6348()) { + /* 16MHz * (N1 + 1) * (N2 + 2) / (M1_CPU + 1) */ + tmp = bcm_perf_readl(PERF_MIPSPLLCTL_REG); + n1 = (tmp & MIPSPLLCTL_N1_MASK) >> MIPSPLLCTL_N1_SHIFT; + n2 = (tmp & MIPSPLLCTL_N2_MASK) >> MIPSPLLCTL_N2_SHIFT; + m1 = (tmp & MIPSPLLCTL_M1CPU_MASK) >> MIPSPLLCTL_M1CPU_SHIFT; + n1 += 1; + n2 += 2; + m1 += 1; + } + + if (BCMCPU_IS_6358()) { + /* 16MHz * N1 * N2 / M1_CPU */ + tmp = bcm_ddr_readl(DDR_DMIPSPLLCFG_REG); + n1 = (tmp & DMIPSPLLCFG_N1_MASK) >> DMIPSPLLCFG_N1_SHIFT; + n2 = (tmp & DMIPSPLLCFG_N2_MASK) >> DMIPSPLLCFG_N2_SHIFT; + m1 = (tmp & DMIPSPLLCFG_M1_MASK) >> DMIPSPLLCFG_M1_SHIFT; + } + + return (16 * 1000000 * n1 * n2) / m1; +} + +/* + * attempt to detect the amount of memory installed + */ +static unsigned int detect_memory_size(void) +{ + unsigned int cols = 0, rows = 0, is_32bits = 0, banks = 0; + u32 val; + + if (BCMCPU_IS_6348()) { + val = bcm_sdram_readl(SDRAM_CFG_REG); + rows = (val & SDRAM_CFG_ROW_MASK) >> SDRAM_CFG_ROW_SHIFT; + cols = (val & SDRAM_CFG_COL_MASK) >> SDRAM_CFG_COL_SHIFT; + is_32bits = (val & SDRAM_CFG_32B_MASK) ? 1 : 0; + banks = (val & SDRAM_CFG_BANK_MASK) ? 2 : 1; + } + + if (BCMCPU_IS_6358()) { + val = bcm_memc_readl(MEMC_CFG_REG); + rows = (val & MEMC_CFG_ROW_MASK) >> MEMC_CFG_ROW_SHIFT; + cols = (val & MEMC_CFG_COL_MASK) >> MEMC_CFG_COL_SHIFT; + is_32bits = (val & MEMC_CFG_32B_MASK) ? 0 : 1; + banks = 2; + } + + /* 0 => 11 address bits ... 2 => 13 address bits */ + rows += 11; + + /* 0 => 8 address bits ... 2 => 10 address bits */ + cols += 8; + + return 1 << (cols + rows + (is_32bits + 1) + banks); +} + +void __init bcm63xx_cpu_init(void) +{ + unsigned int tmp, expected_cpu_id; + struct cpuinfo_mips *c = ¤t_cpu_data; + + /* soc registers location depends on cpu type */ + expected_cpu_id = 0; + + switch (c->cputype) { + case CPU_BCM6348: + expected_cpu_id = BCM6348_CPU_ID; + bcm63xx_regs_base = bcm96348_regs_base; + bcm63xx_irqs = bcm96348_irqs; + break; + case CPU_BCM6358: + expected_cpu_id = BCM6358_CPU_ID; + bcm63xx_regs_base = bcm96358_regs_base; + bcm63xx_irqs = bcm96358_irqs; + break; + } + + /* really early to panic, but delaying panic would not help + * since we will never get any working console */ + if (!expected_cpu_id) + panic("unsupported Broadcom CPU"); + + /* + * bcm63xx_regs_base is set, we can access soc registers + */ + + /* double check CPU type */ + tmp = bcm_perf_readl(PERF_REV_REG); + bcm63xx_cpu_id = (tmp & REV_CHIPID_MASK) >> REV_CHIPID_SHIFT; + bcm63xx_cpu_rev = (tmp & REV_REVID_MASK) >> REV_REVID_SHIFT; + + if (bcm63xx_cpu_id != expected_cpu_id) + panic("bcm63xx CPU id mismatch"); + + bcm63xx_cpu_freq = detect_cpu_clock(); + bcm63xx_memory_size = detect_memory_size(); + + printk(KERN_INFO "Detected Broadcom 0x%04x CPU revision %02x\n", + bcm63xx_cpu_id, bcm63xx_cpu_rev); + printk(KERN_INFO "CPU frequency is %u MHz\n", + bcm63xx_cpu_freq / 1000000); + printk(KERN_INFO "%uMB of RAM installed\n", + bcm63xx_memory_size >> 20); +} --- /dev/null +++ b/arch/mips/bcm63xx/cs.c @@ -0,0 +1,144 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2008 Maxime Bizon + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +static DEFINE_SPINLOCK(bcm63xx_cs_lock); + +/* + * check if given chip select exists + */ +static int is_valid_cs(unsigned int cs) +{ + if (cs > 6) + return 0; + return 1; +} + +/* + * Configure chipselect base address and size (bytes). + * Size must be a power of two between 8k and 256M. + */ +int bcm63xx_set_cs_base(unsigned int cs, u32 base, unsigned int size) +{ + unsigned long flags; + u32 val; + + if (!is_valid_cs(cs)) + return -EINVAL; + + /* sanity check on size */ + if (size != roundup_pow_of_two(size)) + return -EINVAL; + + if (size < 8 * 1024 || size > 256 * 1024 * 1024) + return -EINVAL; + + val = (base & MPI_CSBASE_BASE_MASK); + /* 8k => 0 - 256M => 15 */ + val |= (ilog2(size) - ilog2(8 * 1024)) << MPI_CSBASE_SIZE_SHIFT; + + spin_lock_irqsave(&bcm63xx_cs_lock, flags); + bcm_mpi_writel(val, MPI_CSBASE_REG(cs)); + spin_unlock_irqrestore(&bcm63xx_cs_lock, flags); + + return 0; +} + +EXPORT_SYMBOL(bcm63xx_set_cs_base); + +/* + * configure chipselect timing (ns) + */ +int bcm63xx_set_cs_timing(unsigned int cs, unsigned int wait, + unsigned int setup, unsigned int hold) +{ + unsigned long flags; + u32 val; + + if (!is_valid_cs(cs)) + return -EINVAL; + + spin_lock_irqsave(&bcm63xx_cs_lock, flags); + val = bcm_mpi_readl(MPI_CSCTL_REG(cs)); + val &= ~(MPI_CSCTL_WAIT_MASK); + val &= ~(MPI_CSCTL_SETUP_MASK); + val &= ~(MPI_CSCTL_HOLD_MASK); + val |= wait << MPI_CSCTL_WAIT_SHIFT; + val |= setup << MPI_CSCTL_SETUP_SHIFT; + val |= hold << MPI_CSCTL_HOLD_SHIFT; + bcm_mpi_writel(val, MPI_CSCTL_REG(cs)); + spin_unlock_irqrestore(&bcm63xx_cs_lock, flags); + + return 0; +} + +EXPORT_SYMBOL(bcm63xx_set_cs_timing); + +/* + * configure other chipselect parameter (data bus size, ...) + */ +int bcm63xx_set_cs_param(unsigned int cs, u32 params) +{ + unsigned long flags; + u32 val; + + if (!is_valid_cs(cs)) + return -EINVAL; + + /* none of this fields apply to pcmcia */ + if (cs == MPI_CS_PCMCIA_COMMON || + cs == MPI_CS_PCMCIA_ATTR || + cs == MPI_CS_PCMCIA_IO) + return -EINVAL; + + spin_lock_irqsave(&bcm63xx_cs_lock, flags); + val = bcm_mpi_readl(MPI_CSCTL_REG(cs)); + val &= ~(MPI_CSCTL_DATA16_MASK); + val &= ~(MPI_CSCTL_SYNCMODE_MASK); + val &= ~(MPI_CSCTL_TSIZE_MASK); + val &= ~(MPI_CSCTL_ENDIANSWAP_MASK); + val |= params; + bcm_mpi_writel(val, MPI_CSCTL_REG(cs)); + spin_unlock_irqrestore(&bcm63xx_cs_lock, flags); + + return 0; +} + +EXPORT_SYMBOL(bcm63xx_set_cs_param); + +/* + * set cs status (enable/disable) + */ +int bcm63xx_set_cs_status(unsigned int cs, int enable) +{ + unsigned long flags; + u32 val; + + if (!is_valid_cs(cs)) + return -EINVAL; + + spin_lock_irqsave(&bcm63xx_cs_lock, flags); + val = bcm_mpi_readl(MPI_CSCTL_REG(cs)); + if (enable) + val |= MPI_CSCTL_ENABLE_MASK; + else + val &= ~MPI_CSCTL_ENABLE_MASK; + bcm_mpi_writel(val, MPI_CSCTL_REG(cs)); + spin_unlock_irqrestore(&bcm63xx_cs_lock, flags); + return 0; +} + +EXPORT_SYMBOL(bcm63xx_set_cs_status); --- /dev/null +++ b/arch/mips/bcm63xx/early_printk.c @@ -0,0 +1,30 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2008 Maxime Bizon + */ + +#include +#include +#include + +static void __init wait_xfered(void) +{ + unsigned int val; + + /* wait for any previous char to be transmitted */ + do { + val = bcm_uart0_readl(UART_IR_REG); + if (val & UART_IR_STAT(UART_IR_TXEMPTY)) + break; + } while (1); +} + +void __init prom_putchar(char c) +{ + wait_xfered(); + bcm_uart0_writel(c, UART_FIFO_REG); + wait_xfered(); +} --- /dev/null +++ b/arch/mips/bcm63xx/gpio.c @@ -0,0 +1,128 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2008 Maxime Bizon + * Copyright (C) 2008 Florian Fainelli + */ + +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +static void bcm63xx_gpio_set(struct gpio_chip *chip, + unsigned gpio, int val) +{ + u32 reg; + u32 mask; + u32 tmp; + unsigned long flags; + + if (gpio >= chip->ngpio) + BUG(); + + if (gpio < 32) { + reg = GPIO_DATA_LO_REG; + mask = 1 << gpio; + } else { + reg = GPIO_DATA_HI_REG; + mask = 1 << (gpio - 32); + } + + local_irq_save(flags); + tmp = bcm_gpio_readl(reg); + if (val) + tmp |= mask; + else + tmp &= ~mask; + bcm_gpio_writel(tmp, reg); + local_irq_restore(flags); +} + +static int bcm63xx_gpio_get(struct gpio_chip *chip, unsigned gpio) +{ + u32 reg; + u32 mask; + + if (gpio >= chip->ngpio) + BUG(); + + if (gpio < 32) { + reg = GPIO_DATA_LO_REG; + mask = 1 << gpio; + } else { + reg = GPIO_DATA_HI_REG; + mask = 1 << (gpio - 32); + } + + return !!(bcm_gpio_readl(reg) & mask); +} + +static int bcm63xx_gpio_set_direction(struct gpio_chip *chip, + unsigned gpio, int dir) +{ + u32 reg; + u32 mask; + u32 tmp; + unsigned long flags; + + if (gpio >= chip->ngpio) + BUG(); + + if (gpio < 32) { + reg = GPIO_CTL_LO_REG; + mask = 1 << gpio; + } else { + reg = GPIO_CTL_HI_REG; + mask = 1 << (gpio - 32); + } + + local_irq_save(flags); + tmp = bcm_gpio_readl(reg); + if (dir == GPIO_DIR_IN) + tmp &= ~mask; + else + tmp |= mask; + bcm_gpio_writel(tmp, reg); + local_irq_restore(flags); + + return 0; +} + +static int bcm63xx_gpio_direction_input(struct gpio_chip *chip, unsigned gpio) +{ + return bcm63xx_gpio_set_direction(chip, gpio, GPIO_DIR_IN); +} + +static int bcm63xx_gpio_direction_output(struct gpio_chip *chip, + unsigned gpio, int value) +{ + bcm63xx_gpio_set(chip, gpio, value); + return bcm63xx_gpio_set_direction(chip, gpio, GPIO_DIR_OUT); +} + + +static struct gpio_chip bcm63xx_gpio_chip = { + .label = "bcm63xx-gpio", + .direction_input = bcm63xx_gpio_direction_input, + .direction_output = bcm63xx_gpio_direction_output, + .get = bcm63xx_gpio_get, + .set = bcm63xx_gpio_set, + .base = 0, + .ngpio = BCM63XX_GPIO_COUNT, +}; + +static int __init bcm63xx_gpio_init(void) +{ + printk(KERN_INFO "registering %d GPIOs\n", BCM63XX_GPIO_COUNT); + return gpiochip_add(&bcm63xx_gpio_chip); +} +arch_initcall(bcm63xx_gpio_init); --- /dev/null +++ b/arch/mips/bcm63xx/irq.c @@ -0,0 +1,253 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2008 Maxime Bizon + * Copyright (C) 2008 Nicolas Schichan + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* + * dispatch internal devices IRQ (uart, enet, watchdog, ...). do not + * prioritize any interrupt relatively to another. the static counter + * will resume the loop where it ended the last time we left this + * function. + */ +static void bcm63xx_irq_dispatch_internal(void) +{ + u32 pending; + static int i; + + pending = bcm_perf_readl(PERF_IRQMASK_REG) & + bcm_perf_readl(PERF_IRQSTAT_REG); + + if (!pending) + return ; + + while (1) { + int to_call = i; + + i = (i + 1) & 0x1f; + if (pending & (1 << to_call)) { + do_IRQ(to_call + IRQ_INTERNAL_BASE); + break; + } + } +} + +asmlinkage void plat_irq_dispatch(void) +{ + u32 cause; + + do { + cause = read_c0_cause() & read_c0_status() & ST0_IM; + + if (!cause) + break; + + if (cause & CAUSEF_IP7) + do_IRQ(7); + if (cause & CAUSEF_IP2) + bcm63xx_irq_dispatch_internal(); + if (cause & CAUSEF_IP3) + do_IRQ(IRQ_EXT_0); + if (cause & CAUSEF_IP4) + do_IRQ(IRQ_EXT_1); + if (cause & CAUSEF_IP5) + do_IRQ(IRQ_EXT_2); + if (cause & CAUSEF_IP6) + do_IRQ(IRQ_EXT_3); + } while (1); +} + +/* + * internal IRQs operations: only mask/unmask on PERF irq mask + * register. + */ +static inline void bcm63xx_internal_irq_mask(unsigned int irq) +{ + u32 mask; + + irq -= IRQ_INTERNAL_BASE; + mask = bcm_perf_readl(PERF_IRQMASK_REG); + mask &= ~(1 << irq); + bcm_perf_writel(mask, PERF_IRQMASK_REG); +} + +static void bcm63xx_internal_irq_unmask(unsigned int irq) +{ + u32 mask; + + irq -= IRQ_INTERNAL_BASE; + mask = bcm_perf_readl(PERF_IRQMASK_REG); + mask |= (1 << irq); + bcm_perf_writel(mask, PERF_IRQMASK_REG); +} + +static unsigned int bcm63xx_internal_irq_startup(unsigned int irq) +{ + bcm63xx_internal_irq_unmask(irq); + return 0; +} + +/* + * external IRQs operations: mask/unmask and clear on PERF external + * irq control register. + */ +static void bcm63xx_external_irq_mask(unsigned int irq) +{ + u32 reg; + + irq -= IRQ_EXT_BASE; + reg = bcm_perf_readl(PERF_EXTIRQ_CFG_REG); + reg &= ~EXTIRQ_CFG_MASK(irq); + bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG); +} + +static void bcm63xx_external_irq_unmask(unsigned int irq) +{ + u32 reg; + + irq -= IRQ_EXT_BASE; + reg = bcm_perf_readl(PERF_EXTIRQ_CFG_REG); + reg |= EXTIRQ_CFG_MASK(irq); + bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG); +} + +static void bcm63xx_external_irq_clear(unsigned int irq) +{ + u32 reg; + + irq -= IRQ_EXT_BASE; + reg = bcm_perf_readl(PERF_EXTIRQ_CFG_REG); + reg |= EXTIRQ_CFG_CLEAR(irq); + bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG); +} + +static unsigned int bcm63xx_external_irq_startup(unsigned int irq) +{ + set_c0_status(0x100 << (irq - IRQ_MIPS_BASE)); + irq_enable_hazard(); + bcm63xx_external_irq_unmask(irq); + return 0; +} + +static void bcm63xx_external_irq_shutdown(unsigned int irq) +{ + bcm63xx_external_irq_mask(irq); + clear_c0_status(0x100 << (irq - IRQ_MIPS_BASE)); + irq_disable_hazard(); +} + +static int bcm63xx_external_irq_set_type(unsigned int irq, + unsigned int flow_type) +{ + u32 reg; + struct irq_desc *desc = irq_desc + irq; + + irq -= IRQ_EXT_BASE; + + flow_type &= IRQ_TYPE_SENSE_MASK; + + if (flow_type == IRQ_TYPE_NONE) + flow_type = IRQ_TYPE_LEVEL_LOW; + + reg = bcm_perf_readl(PERF_EXTIRQ_CFG_REG); + switch (flow_type) { + case IRQ_TYPE_EDGE_BOTH: + reg &= ~EXTIRQ_CFG_LEVELSENSE(irq); + reg |= EXTIRQ_CFG_BOTHEDGE(irq); + break; + + case IRQ_TYPE_EDGE_RISING: + reg &= ~EXTIRQ_CFG_LEVELSENSE(irq); + reg |= EXTIRQ_CFG_SENSE(irq); + reg &= ~EXTIRQ_CFG_BOTHEDGE(irq); + break; + + case IRQ_TYPE_EDGE_FALLING: + reg &= ~EXTIRQ_CFG_LEVELSENSE(irq); + reg &= ~EXTIRQ_CFG_SENSE(irq); + reg &= ~EXTIRQ_CFG_BOTHEDGE(irq); + break; + + case IRQ_TYPE_LEVEL_HIGH: + reg |= EXTIRQ_CFG_LEVELSENSE(irq); + reg |= EXTIRQ_CFG_SENSE(irq); + break; + + case IRQ_TYPE_LEVEL_LOW: + reg |= EXTIRQ_CFG_LEVELSENSE(irq); + reg &= ~EXTIRQ_CFG_SENSE(irq); + break; + + default: + printk(KERN_ERR "bogus flow type combination given !\n"); + return -EINVAL; + } + bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG); + + if (flow_type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) { + desc->status |= IRQ_LEVEL; + desc->handle_irq = handle_level_irq; + } else { + desc->handle_irq = handle_edge_irq; + } + + return 0; +} + +static struct irq_chip bcm63xx_internal_irq_chip = { + .name = "bcm63xx_ipic", + .startup = bcm63xx_internal_irq_startup, + .shutdown = bcm63xx_internal_irq_mask, + + .mask = bcm63xx_internal_irq_mask, + .mask_ack = bcm63xx_internal_irq_mask, + .unmask = bcm63xx_internal_irq_unmask, +}; + +static struct irq_chip bcm63xx_external_irq_chip = { + .name = "bcm63xx_epic", + .startup = bcm63xx_external_irq_startup, + .shutdown = bcm63xx_external_irq_shutdown, + + .ack = bcm63xx_external_irq_clear, + + .mask = bcm63xx_external_irq_mask, + .unmask = bcm63xx_external_irq_unmask, + + .set_type = bcm63xx_external_irq_set_type, +}; + +static struct irqaction cpu_ip2_cascade_action = { + .handler = no_action, + .name = "cascade_ip2", +}; + +void __init arch_init_irq(void) +{ + int i; + + mips_cpu_irq_init(); + for (i = IRQ_INTERNAL_BASE; i < NR_IRQS; ++i) + set_irq_chip_and_handler(i, &bcm63xx_internal_irq_chip, + handle_level_irq); + + for (i = IRQ_EXT_BASE; i < IRQ_EXT_BASE + 4; ++i) + set_irq_chip_and_handler(i, &bcm63xx_external_irq_chip, + handle_edge_irq); + + setup_irq(IRQ_MIPS_BASE + 2, &cpu_ip2_cascade_action); +} --- /dev/null +++ b/arch/mips/bcm63xx/prom.c @@ -0,0 +1,43 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2008 Maxime Bizon + */ + +#include +#include +#include +#include +#include +#include + +void __init prom_init(void) +{ + u32 reg, mask; + + bcm63xx_cpu_init(); + + /* stop any running watchdog */ + bcm_wdt_writel(WDT_STOP_1, WDT_CTL_REG); + bcm_wdt_writel(WDT_STOP_2, WDT_CTL_REG); + + /* disable all hardware blocks clock for now */ + if (BCMCPU_IS_6348()) + mask = CKCTL_6348_ALL_SAFE_EN; + else + /* BCMCPU_IS_6358() */ + mask = CKCTL_6358_ALL_SAFE_EN; + + reg = bcm_perf_readl(PERF_CKCTL_REG); + reg &= ~mask; + bcm_perf_writel(reg, PERF_CKCTL_REG); + + /* assign command line from kernel config */ + strcpy(arcs_cmdline, CONFIG_CMDLINE); +} + +void __init prom_free_prom_memory(void) +{ +} --- /dev/null +++ b/arch/mips/bcm63xx/setup.c @@ -0,0 +1,111 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2008 Maxime Bizon + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +void bcm63xx_machine_halt(void) +{ + printk(KERN_INFO "System halted\n"); + while (1) + ; +} + +static void bcm6348_a1_reboot(void) +{ + u32 reg; + + /* soft reset all blocks */ + printk(KERN_INFO "soft-reseting all blocks ...\n"); + reg = bcm_perf_readl(PERF_SOFTRESET_REG); + reg &= ~SOFTRESET_6348_ALL; + bcm_perf_writel(reg, PERF_SOFTRESET_REG); + mdelay(10); + + reg = bcm_perf_readl(PERF_SOFTRESET_REG); + reg |= SOFTRESET_6348_ALL; + bcm_perf_writel(reg, PERF_SOFTRESET_REG); + mdelay(10); + + /* Jump to the power on address. */ + printk(KERN_INFO "jumping to reset vector.\n"); + /* set high vectors (base at 0xbfc00000 */ + set_c0_status(ST0_BEV | ST0_ERL); + /* run uncached in kseg0 */ + change_c0_config(CONF_CM_CMASK, CONF_CM_UNCACHED); + __flush_cache_all(); + /* remove all wired TLB entries */ + write_c0_wired(0); + __asm__ __volatile__( + "jr\t%0" + : + : "r" (0xbfc00000)); + while (1) + ; +} + +void bcm63xx_machine_reboot(void) +{ + u32 reg; + + /* mask and clear all external irq */ + reg = bcm_perf_readl(PERF_EXTIRQ_CFG_REG); + reg &= ~EXTIRQ_CFG_MASK_ALL; + reg |= EXTIRQ_CFG_CLEAR_ALL; + bcm_perf_writel(reg, PERF_EXTIRQ_CFG_REG); + + if (BCMCPU_IS_6348() && (bcm63xx_get_cpu_rev() == 0xa1)) + bcm6348_a1_reboot(); + + printk(KERN_INFO "triggering watchdog soft-reset...\n"); + bcm_perf_writel(SYS_PLL_SOFT_RESET, PERF_SYS_PLL_CTL_REG); + while (1) + ; +} + +static void __bcm63xx_machine_reboot(char *p) +{ + bcm63xx_machine_reboot(); +} + +/* + * return system type in /proc/cpuinfo + */ +const char *get_system_type(void) +{ + static char buf[128]; + sprintf(buf, "bcm963xx (0x%04x/0x%04X)", + bcm63xx_get_cpu_id(), bcm63xx_get_cpu_rev()); + return buf; +} + +void __init plat_time_init(void) +{ + mips_hpt_frequency = bcm63xx_get_cpu_freq() / 2; +} +void __init plat_mem_setup(void) +{ + add_memory_region(0, bcm63xx_get_memory_size(), BOOT_MEM_RAM); + + _machine_halt = bcm63xx_machine_halt; + _machine_restart = __bcm63xx_machine_reboot; + pm_power_off = bcm63xx_machine_halt; + + set_io_port_base(0); +} --- /dev/null +++ b/arch/mips/bcm63xx/timer.c @@ -0,0 +1,205 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2008 Maxime Bizon + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static DEFINE_SPINLOCK(timer_reg_lock); +static DEFINE_SPINLOCK(timer_data_lock); +static struct clk *periph_clk; + +static struct timer_data { + void (*cb)(void *); + void *data; +} timer_data[BCM63XX_TIMER_COUNT]; + +static irqreturn_t timer_interrupt(int irq, void *dev_id) +{ + u32 stat; + int i; + + spin_lock(&timer_reg_lock); + stat = bcm_timer_readl(TIMER_IRQSTAT_REG); + bcm_timer_writel(stat, TIMER_IRQSTAT_REG); + spin_unlock(&timer_reg_lock); + + for (i = 0; i < BCM63XX_TIMER_COUNT; i++) { + if (!(stat & TIMER_IRQSTAT_TIMER_CAUSE(i))) + continue; + + spin_lock(&timer_data_lock); + if (!timer_data[i].cb) { + spin_unlock(&timer_data_lock); + continue; + } + + timer_data[i].cb(timer_data[i].data); + spin_unlock(&timer_data_lock); + } + + return IRQ_HANDLED; +} + +int bcm63xx_timer_enable(int id) +{ + u32 reg; + unsigned long flags; + + if (id >= BCM63XX_TIMER_COUNT) + return -EINVAL; + + spin_lock_irqsave(&timer_reg_lock, flags); + + reg = bcm_timer_readl(TIMER_CTLx_REG(id)); + reg |= TIMER_CTL_ENABLE_MASK; + bcm_timer_writel(reg, TIMER_CTLx_REG(id)); + + reg = bcm_timer_readl(TIMER_IRQSTAT_REG); + reg |= TIMER_IRQSTAT_TIMER_IR_EN(id); + bcm_timer_writel(reg, TIMER_IRQSTAT_REG); + + spin_unlock_irqrestore(&timer_reg_lock, flags); + return 0; +} + +EXPORT_SYMBOL(bcm63xx_timer_enable); + +int bcm63xx_timer_disable(int id) +{ + u32 reg; + unsigned long flags; + + if (id >= BCM63XX_TIMER_COUNT) + return -EINVAL; + + spin_lock_irqsave(&timer_reg_lock, flags); + + reg = bcm_timer_readl(TIMER_CTLx_REG(id)); + reg &= ~TIMER_CTL_ENABLE_MASK; + bcm_timer_writel(reg, TIMER_CTLx_REG(id)); + + reg = bcm_timer_readl(TIMER_IRQSTAT_REG); + reg &= ~TIMER_IRQSTAT_TIMER_IR_EN(id); + bcm_timer_writel(reg, TIMER_IRQSTAT_REG); + + spin_unlock_irqrestore(&timer_reg_lock, flags); + return 0; +} + +EXPORT_SYMBOL(bcm63xx_timer_disable); + +int bcm63xx_timer_register(int id, void (*callback)(void *data), void *data) +{ + unsigned long flags; + int ret; + + if (id >= BCM63XX_TIMER_COUNT || !callback) + return -EINVAL; + + ret = 0; + spin_lock_irqsave(&timer_data_lock, flags); + if (timer_data[id].cb) { + ret = -EBUSY; + goto out; + } + + timer_data[id].cb = callback; + timer_data[id].data = data; + +out: + spin_unlock_irqrestore(&timer_data_lock, flags); + return ret; +} + +EXPORT_SYMBOL(bcm63xx_timer_register); + +void bcm63xx_timer_unregister(int id) +{ + unsigned long flags; + + if (id >= BCM63XX_TIMER_COUNT) + return; + + spin_lock_irqsave(&timer_data_lock, flags); + timer_data[id].cb = NULL; + spin_unlock_irqrestore(&timer_data_lock, flags); +} + +EXPORT_SYMBOL(bcm63xx_timer_unregister); + +unsigned int bcm63xx_timer_countdown(unsigned int countdown_us) +{ + return (clk_get_rate(periph_clk) / (1000 * 1000)) * countdown_us; +} + +EXPORT_SYMBOL(bcm63xx_timer_countdown); + +int bcm63xx_timer_set(int id, int monotonic, unsigned int countdown_us) +{ + u32 reg, countdown; + unsigned long flags; + + if (id >= BCM63XX_TIMER_COUNT) + return -EINVAL; + + countdown = bcm63xx_timer_countdown(countdown_us); + if (countdown & ~TIMER_CTL_COUNTDOWN_MASK) + return -EINVAL; + + spin_lock_irqsave(&timer_reg_lock, flags); + reg = bcm_timer_readl(TIMER_CTLx_REG(id)); + + if (monotonic) + reg &= ~TIMER_CTL_MONOTONIC_MASK; + else + reg |= TIMER_CTL_MONOTONIC_MASK; + + reg &= ~TIMER_CTL_COUNTDOWN_MASK; + reg |= countdown; + bcm_timer_writel(reg, TIMER_CTLx_REG(id)); + + spin_unlock_irqrestore(&timer_reg_lock, flags); + return 0; +} + +EXPORT_SYMBOL(bcm63xx_timer_set); + +int bcm63xx_timer_init(void) +{ + int ret, irq; + u32 reg; + + reg = bcm_timer_readl(TIMER_IRQSTAT_REG); + reg &= ~TIMER_IRQSTAT_TIMER0_IR_EN; + reg &= ~TIMER_IRQSTAT_TIMER1_IR_EN; + reg &= ~TIMER_IRQSTAT_TIMER2_IR_EN; + bcm_timer_writel(reg, TIMER_IRQSTAT_REG); + + periph_clk = clk_get(NULL, "periph"); + if (IS_ERR(periph_clk)) + return -ENODEV; + + irq = bcm63xx_get_irq_number(IRQ_TIMER); + ret = request_irq(irq, timer_interrupt, 0, "bcm63xx_timer", NULL); + if (ret) { + printk(KERN_ERR "bcm63xx_timer: failed to register irq\n"); + return ret; + } + + return 0; +} + +arch_initcall(bcm63xx_timer_init); --- a/arch/mips/include/asm/fixmap.h +++ b/arch/mips/include/asm/fixmap.h @@ -67,11 +67,15 @@ enum fixed_addresses { * the start of the fixmap, and leave one page empty * at the top of mem.. */ +#ifdef CONFIG_BCM63XX +#define FIXADDR_TOP ((unsigned long)(long)(int)0xff000000) +#else #if defined(CONFIG_CPU_TX39XX) || defined(CONFIG_CPU_TX49XX) #define FIXADDR_TOP ((unsigned long)(long)(int)(0xff000000 - 0x20000)) #else #define FIXADDR_TOP ((unsigned long)(long)(int)0xfffe0000) #endif +#endif #define FIXADDR_SIZE (__end_of_fixed_addresses << PAGE_SHIFT) #define FIXADDR_START (FIXADDR_TOP - FIXADDR_SIZE) --- /dev/null +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_clk.h @@ -0,0 +1,11 @@ +#ifndef BCM63XX_CLK_H_ +#define BCM63XX_CLK_H_ + +struct clk { + void (*set)(struct clk *, int); + unsigned int rate; + unsigned int usage; + int id; +}; + +#endif /* ! BCM63XX_CLK_H_ */ --- /dev/null +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h @@ -0,0 +1,314 @@ +#ifndef BCM63XX_CPU_H_ +#define BCM63XX_CPU_H_ + +#include +#include + +/* + * Macro to fetch bcm63xx cpu id and revision, should be optimized at + * compile time if only one CPU support is enabled (idea stolen from + * arm mach-types) + */ +#define BCM6348_CPU_ID 0x6348 +#define BCM6358_CPU_ID 0x6358 + +void __init bcm63xx_cpu_init(void); +u16 __bcm63xx_get_cpu_id(void); +u16 bcm63xx_get_cpu_rev(void); +unsigned int bcm63xx_get_cpu_freq(void); + +#ifdef CONFIG_BCM63XX_CPU_6348 +# ifdef bcm63xx_get_cpu_id +# undef bcm63xx_get_cpu_id +# define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id() +# define BCMCPU_RUNTIME_DETECT +# else +# define bcm63xx_get_cpu_id() BCM6348_CPU_ID +# endif +# define BCMCPU_IS_6348() (bcm63xx_get_cpu_id() == BCM6348_CPU_ID) +#else +# define BCMCPU_IS_6348() (0) +#endif + +#ifdef CONFIG_BCM63XX_CPU_6358 +# ifdef bcm63xx_get_cpu_id +# undef bcm63xx_get_cpu_id +# define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id() +# define BCMCPU_RUNTIME_DETECT +# else +# define bcm63xx_get_cpu_id() BCM6358_CPU_ID +# endif +# define BCMCPU_IS_6358() (bcm63xx_get_cpu_id() == BCM6358_CPU_ID) +#else +# define BCMCPU_IS_6358() (0) +#endif + +#ifndef bcm63xx_get_cpu_id +#error "No CPU support configured" +#endif + +/* + * While registers sets are (mostly) the same across 63xx CPU, base + * address of these sets do change. + */ +enum bcm63xx_regs_set { + RSET_DSL_LMEM = 0, + RSET_PERF, + RSET_TIMER, + RSET_WDT, + RSET_UART0, + RSET_GPIO, + RSET_SPI, + RSET_UDC0, + RSET_OHCI0, + RSET_OHCI_PRIV, + RSET_USBH_PRIV, + RSET_MPI, + RSET_PCMCIA, + RSET_DSL, + RSET_ENET0, + RSET_ENET1, + RSET_ENETDMA, + RSET_EHCI0, + RSET_SDRAM, + RSET_MEMC, + RSET_DDR, +}; + +#define RSET_DSL_LMEM_SIZE (64 * 1024 * 4) +#define RSET_DSL_SIZE 4096 +#define RSET_WDT_SIZE 12 +#define RSET_ENET_SIZE 2048 +#define RSET_ENETDMA_SIZE 2048 +#define RSET_UART_SIZE 24 +#define RSET_UDC_SIZE 256 +#define RSET_OHCI_SIZE 256 +#define RSET_EHCI_SIZE 256 +#define RSET_PCMCIA_SIZE 12 + +/* + * 6348 register sets base address + */ +#define BCM_6348_DSL_LMEM_BASE (0xfff00000) +#define BCM_6348_PERF_BASE (0xfffe0000) +#define BCM_6348_TIMER_BASE (0xfffe0200) +#define BCM_6348_WDT_BASE (0xfffe021c) +#define BCM_6348_UART0_BASE (0xfffe0300) +#define BCM_6348_GPIO_BASE (0xfffe0400) +#define BCM_6348_SPI_BASE (0xfffe0c00) +#define BCM_6348_UDC0_BASE (0xfffe1000) +#define BCM_6348_OHCI0_BASE (0xfffe1b00) +#define BCM_6348_OHCI_PRIV_BASE (0xfffe1c00) +#define BCM_6348_USBH_PRIV_BASE (0xdeadbeef) +#define BCM_6348_MPI_BASE (0xfffe2000) +#define BCM_6348_PCMCIA_BASE (0xfffe2054) +#define BCM_6348_SDRAM_REGS_BASE (0xfffe2300) +#define BCM_6348_DSL_BASE (0xfffe3000) +#define BCM_6348_ENET0_BASE (0xfffe6000) +#define BCM_6348_ENET1_BASE (0xfffe6800) +#define BCM_6348_ENETDMA_BASE (0xfffe7000) +#define BCM_6348_EHCI0_BASE (0xdeadbeef) +#define BCM_6348_SDRAM_BASE (0xfffe2300) +#define BCM_6348_MEMC_BASE (0xdeadbeef) +#define BCM_6348_DDR_BASE (0xdeadbeef) + +/* + * 6358 register sets base address + */ +#define BCM_6358_DSL_LMEM_BASE (0xfff00000) +#define BCM_6358_PERF_BASE (0xfffe0000) +#define BCM_6358_TIMER_BASE (0xfffe0040) +#define BCM_6358_WDT_BASE (0xfffe005c) +#define BCM_6358_UART0_BASE (0xfffe0100) +#define BCM_6358_GPIO_BASE (0xfffe0080) +#define BCM_6358_SPI_BASE (0xdeadbeef) +#define BCM_6358_UDC0_BASE (0xfffe0800) +#define BCM_6358_OHCI0_BASE (0xfffe1400) +#define BCM_6358_OHCI_PRIV_BASE (0xdeadbeef) +#define BCM_6358_USBH_PRIV_BASE (0xfffe1500) +#define BCM_6358_MPI_BASE (0xfffe1000) +#define BCM_6358_PCMCIA_BASE (0xfffe1054) +#define BCM_6358_SDRAM_REGS_BASE (0xfffe2300) +#define BCM_6358_DSL_BASE (0xfffe3000) +#define BCM_6358_ENET0_BASE (0xfffe4000) +#define BCM_6358_ENET1_BASE (0xfffe4800) +#define BCM_6358_ENETDMA_BASE (0xfffe5000) +#define BCM_6358_EHCI0_BASE (0xfffe1300) +#define BCM_6358_SDRAM_BASE (0xdeadbeef) +#define BCM_6358_MEMC_BASE (0xfffe1200) +#define BCM_6358_DDR_BASE (0xfffe12a0) + + +extern const unsigned long *bcm63xx_regs_base; + +static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set) +{ +#ifdef BCMCPU_RUNTIME_DETECT + return bcm63xx_regs_base[set]; +#else +#ifdef CONFIG_BCM63XX_CPU_6348 + switch (set) { + case RSET_DSL_LMEM: + return BCM_6348_DSL_LMEM_BASE; + case RSET_PERF: + return BCM_6348_PERF_BASE; + case RSET_TIMER: + return BCM_6348_TIMER_BASE; + case RSET_WDT: + return BCM_6348_WDT_BASE; + case RSET_UART0: + return BCM_6348_UART0_BASE; + case RSET_GPIO: + return BCM_6348_GPIO_BASE; + case RSET_SPI: + return BCM_6348_SPI_BASE; + case RSET_UDC0: + return BCM_6348_UDC0_BASE; + case RSET_OHCI0: + return BCM_6348_OHCI0_BASE; + case RSET_OHCI_PRIV: + return BCM_6348_OHCI_PRIV_BASE; + case RSET_USBH_PRIV: + return BCM_6348_USBH_PRIV_BASE; + case RSET_MPI: + return BCM_6348_MPI_BASE; + case RSET_PCMCIA: + return BCM_6348_PCMCIA_BASE; + case RSET_DSL: + return BCM_6348_DSL_BASE; + case RSET_ENET0: + return BCM_6348_ENET0_BASE; + case RSET_ENET1: + return BCM_6348_ENET1_BASE; + case RSET_ENETDMA: + return BCM_6348_ENETDMA_BASE; + case RSET_EHCI0: + return BCM_6348_EHCI0_BASE; + case RSET_SDRAM: + return BCM_6348_SDRAM_BASE; + case RSET_MEMC: + return BCM_6348_MEMC_BASE; + case RSET_DDR: + return BCM_6348_DDR_BASE; + } +#endif +#ifdef CONFIG_BCM63XX_CPU_6358 + switch (set) { + case RSET_DSL_LMEM: + return BCM_6358_DSL_LMEM_BASE; + case RSET_PERF: + return BCM_6358_PERF_BASE; + case RSET_TIMER: + return BCM_6358_TIMER_BASE; + case RSET_WDT: + return BCM_6358_WDT_BASE; + case RSET_UART0: + return BCM_6358_UART0_BASE; + case RSET_GPIO: + return BCM_6358_GPIO_BASE; + case RSET_SPI: + return BCM_6358_SPI_BASE; + case RSET_UDC0: + return BCM_6358_UDC0_BASE; + case RSET_OHCI0: + return BCM_6358_OHCI0_BASE; + case RSET_OHCI_PRIV: + return BCM_6358_OHCI_PRIV_BASE; + case RSET_USBH_PRIV: + return BCM_6358_USBH_PRIV_BASE; + case RSET_MPI: + return BCM_6358_MPI_BASE; + case RSET_PCMCIA: + return BCM_6358_PCMCIA_BASE; + case RSET_ENET0: + return BCM_6358_ENET0_BASE; + case RSET_ENET1: + return BCM_6358_ENET1_BASE; + case RSET_ENETDMA: + return BCM_6358_ENETDMA_BASE; + case RSET_DSL: + return BCM_6358_DSL_BASE; + case RSET_EHCI0: + return BCM_6358_EHCI0_BASE; + case RSET_SDRAM: + return BCM_6358_SDRAM_BASE; + case RSET_MEMC: + return BCM_6358_MEMC_BASE; + case RSET_DDR: + return BCM_6358_DDR_BASE; + } +#endif +#endif + /* unreached */ + return 0; +} + +/* + * IRQ number changes across CPU too + */ +enum bcm63xx_irq { + IRQ_TIMER = 0, + IRQ_UART0, + IRQ_DSL, + IRQ_ENET0, + IRQ_ENET1, + IRQ_ENET_PHY, + IRQ_OHCI0, + IRQ_EHCI0, + IRQ_PCMCIA0, + IRQ_ENET0_RXDMA, + IRQ_ENET0_TXDMA, + IRQ_ENET1_RXDMA, + IRQ_ENET1_TXDMA, + IRQ_PCI, + IRQ_PCMCIA, +}; + +/* + * 6348 irqs + */ +#define BCM_6348_TIMER_IRQ (IRQ_INTERNAL_BASE + 0) +#define BCM_6348_UART0_IRQ (IRQ_INTERNAL_BASE + 2) +#define BCM_6348_DSL_IRQ (IRQ_INTERNAL_BASE + 4) +#define BCM_6348_ENET1_IRQ (IRQ_INTERNAL_BASE + 7) +#define BCM_6348_ENET0_IRQ (IRQ_INTERNAL_BASE + 8) +#define BCM_6348_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9) +#define BCM_6348_OHCI0_IRQ (IRQ_INTERNAL_BASE + 12) +#define BCM_6348_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 20) +#define BCM_6348_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 21) +#define BCM_6348_ENET1_RXDMA_IRQ (IRQ_INTERNAL_BASE + 22) +#define BCM_6348_ENET1_TXDMA_IRQ (IRQ_INTERNAL_BASE + 23) +#define BCM_6348_PCMCIA_IRQ (IRQ_INTERNAL_BASE + 24) +#define BCM_6348_PCI_IRQ (IRQ_INTERNAL_BASE + 24) + +/* + * 6358 irqs + */ +#define BCM_6358_TIMER_IRQ (IRQ_INTERNAL_BASE + 0) +#define BCM_6358_UART0_IRQ (IRQ_INTERNAL_BASE + 2) +#define BCM_6358_OHCI0_IRQ (IRQ_INTERNAL_BASE + 5) +#define BCM_6358_ENET1_IRQ (IRQ_INTERNAL_BASE + 6) +#define BCM_6358_ENET0_IRQ (IRQ_INTERNAL_BASE + 8) +#define BCM_6358_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9) +#define BCM_6358_EHCI0_IRQ (IRQ_INTERNAL_BASE + 10) +#define BCM_6358_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 15) +#define BCM_6358_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 16) +#define BCM_6358_ENET1_RXDMA_IRQ (IRQ_INTERNAL_BASE + 17) +#define BCM_6358_ENET1_TXDMA_IRQ (IRQ_INTERNAL_BASE + 18) +#define BCM_6358_DSL_IRQ (IRQ_INTERNAL_BASE + 29) +#define BCM_6358_PCI_IRQ (IRQ_INTERNAL_BASE + 31) +#define BCM_6358_PCMCIA_IRQ (IRQ_INTERNAL_BASE + 24) + +extern const int *bcm63xx_irqs; + +static inline int bcm63xx_get_irq_number(enum bcm63xx_irq irq) +{ + return bcm63xx_irqs[irq]; +} + +/* + * return installed memory size + */ +unsigned int bcm63xx_get_memory_size(void); + +#endif /* !BCM63XX_CPU_H_ */ --- /dev/null +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cs.h @@ -0,0 +1,10 @@ +#ifndef BCM63XX_CS_H +#define BCM63XX_CS_H + +int bcm63xx_set_cs_base(unsigned int cs, u32 base, unsigned int size); +int bcm63xx_set_cs_timing(unsigned int cs, unsigned int wait, + unsigned int setup, unsigned int hold); +int bcm63xx_set_cs_param(unsigned int cs, u32 flags); +int bcm63xx_set_cs_status(unsigned int cs, int enable); + +#endif /* !BCM63XX_CS_H */ --- /dev/null +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h @@ -0,0 +1,10 @@ +#ifndef BCM63XX_GPIO_H +#define BCM63XX_GPIO_H + +/* all helpers will BUG() if gpio count is >= 37. */ +#define BCM63XX_GPIO_COUNT 37 + +#define GPIO_DIR_OUT 0x0 +#define GPIO_DIR_IN 0x1 + +#endif /* !BCM63XX_GPIO_H */ --- /dev/null +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h @@ -0,0 +1,93 @@ +#ifndef BCM63XX_IO_H_ +#define BCM63XX_IO_H_ + +#include "bcm63xx_cpu.h" + +/* + * Physical memory map, RAM is mapped at 0x0. + * + * Note that size MUST be a power of two. + */ +#define BCM_PCMCIA_COMMON_BASE_PA (0x20000000) +#define BCM_PCMCIA_COMMON_SIZE (16 * 1024 * 1024) +#define BCM_PCMCIA_COMMON_END_PA (BCM_PCMCIA_COMMON_BASE_PA + \ + BCM_PCMCIA_COMMON_SIZE - 1) + +#define BCM_PCMCIA_ATTR_BASE_PA (0x21000000) +#define BCM_PCMCIA_ATTR_SIZE (16 * 1024 * 1024) +#define BCM_PCMCIA_ATTR_END_PA (BCM_PCMCIA_ATTR_BASE_PA + \ + BCM_PCMCIA_ATTR_SIZE - 1) + +#define BCM_PCMCIA_IO_BASE_PA (0x22000000) +#define BCM_PCMCIA_IO_SIZE (64 * 1024) +#define BCM_PCMCIA_IO_END_PA (BCM_PCMCIA_IO_BASE_PA + \ + BCM_PCMCIA_IO_SIZE - 1) + +#define BCM_PCI_MEM_BASE_PA (0x30000000) +#define BCM_PCI_MEM_SIZE (128 * 1024 * 1024) +#define BCM_PCI_MEM_END_PA (BCM_PCI_MEM_BASE_PA + \ + BCM_PCI_MEM_SIZE - 1) + +#define BCM_PCI_IO_BASE_PA (0x08000000) +#define BCM_PCI_IO_SIZE (64 * 1024) +#define BCM_PCI_IO_END_PA (BCM_PCI_IO_BASE_PA + \ + BCM_PCI_IO_SIZE - 1) +#define BCM_PCI_IO_HALF_PA (BCM_PCI_IO_BASE_PA + \ + (BCM_PCI_IO_SIZE / 2) - 1) + +#define BCM_CB_MEM_BASE_PA (0x38000000) +#define BCM_CB_MEM_SIZE (128 * 1024 * 1024) +#define BCM_CB_MEM_END_PA (BCM_CB_MEM_BASE_PA + \ + BCM_CB_MEM_SIZE - 1) + + +/* + * Internal registers are accessed through KSEG3 + */ +#define BCM_REGS_VA(x) ((void __iomem *)(x)) + +#define bcm_readb(a) (*(volatile unsigned char *) BCM_REGS_VA(a)) +#define bcm_readw(a) (*(volatile unsigned short *) BCM_REGS_VA(a)) +#define bcm_readl(a) (*(volatile unsigned int *) BCM_REGS_VA(a)) +#define bcm_writeb(v, a) (*(volatile unsigned char *) BCM_REGS_VA((a)) = (v)) +#define bcm_writew(v, a) (*(volatile unsigned short *) BCM_REGS_VA((a)) = (v)) +#define bcm_writel(v, a) (*(volatile unsigned int *) BCM_REGS_VA((a)) = (v)) + +/* + * IO helpers to access register set for current CPU + */ +#define bcm_rset_readb(s, o) bcm_readb(bcm63xx_regset_address(s) + (o)) +#define bcm_rset_readw(s, o) bcm_readw(bcm63xx_regset_address(s) + (o)) +#define bcm_rset_readl(s, o) bcm_readl(bcm63xx_regset_address(s) + (o)) +#define bcm_rset_writeb(s, v, o) bcm_writeb((v), \ + bcm63xx_regset_address(s) + (o)) +#define bcm_rset_writew(s, v, o) bcm_writew((v), \ + bcm63xx_regset_address(s) + (o)) +#define bcm_rset_writel(s, v, o) bcm_writel((v), \ + bcm63xx_regset_address(s) + (o)) + +/* + * helpers for frequently used register sets + */ +#define bcm_perf_readl(o) bcm_rset_readl(RSET_PERF, (o)) +#define bcm_perf_writel(v, o) bcm_rset_writel(RSET_PERF, (v), (o)) +#define bcm_timer_readl(o) bcm_rset_readl(RSET_TIMER, (o)) +#define bcm_timer_writel(v, o) bcm_rset_writel(RSET_TIMER, (v), (o)) +#define bcm_wdt_readl(o) bcm_rset_readl(RSET_WDT, (o)) +#define bcm_wdt_writel(v, o) bcm_rset_writel(RSET_WDT, (v), (o)) +#define bcm_gpio_readl(o) bcm_rset_readl(RSET_GPIO, (o)) +#define bcm_gpio_writel(v, o) bcm_rset_writel(RSET_GPIO, (v), (o)) +#define bcm_uart0_readl(o) bcm_rset_readl(RSET_UART0, (o)) +#define bcm_uart0_writel(v, o) bcm_rset_writel(RSET_UART0, (v), (o)) +#define bcm_mpi_readl(o) bcm_rset_readl(RSET_MPI, (o)) +#define bcm_mpi_writel(v, o) bcm_rset_writel(RSET_MPI, (v), (o)) +#define bcm_pcmcia_readl(o) bcm_rset_readl(RSET_PCMCIA, (o)) +#define bcm_pcmcia_writel(v, o) bcm_rset_writel(RSET_PCMCIA, (v), (o)) +#define bcm_sdram_readl(o) bcm_rset_readl(RSET_SDRAM, (o)) +#define bcm_sdram_writel(v, o) bcm_rset_writel(RSET_SDRAM, (v), (o)) +#define bcm_memc_readl(o) bcm_rset_readl(RSET_MEMC, (o)) +#define bcm_memc_writel(v, o) bcm_rset_writel(RSET_MEMC, (v), (o)) +#define bcm_ddr_readl(o) bcm_rset_readl(RSET_DDR, (o)) +#define bcm_ddr_writel(v, o) bcm_rset_writel(RSET_DDR, (v), (o)) + +#endif /* ! BCM63XX_IO_H_ */ --- /dev/null +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_irq.h @@ -0,0 +1,15 @@ +#ifndef BCM63XX_IRQ_H_ +#define BCM63XX_IRQ_H_ + +#include + +#define IRQ_MIPS_BASE 0 +#define IRQ_INTERNAL_BASE 8 + +#define IRQ_EXT_BASE (IRQ_MIPS_BASE + 3) +#define IRQ_EXT_0 (IRQ_EXT_BASE + 0) +#define IRQ_EXT_1 (IRQ_EXT_BASE + 1) +#define IRQ_EXT_2 (IRQ_EXT_BASE + 2) +#define IRQ_EXT_3 (IRQ_EXT_BASE + 3) + +#endif /* ! BCM63XX_IRQ_H_ */ --- /dev/null +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h @@ -0,0 +1,728 @@ +#ifndef BCM63XX_REGS_H_ +#define BCM63XX_REGS_H_ + +/************************************************************************* + * _REG relative to RSET_PERF + *************************************************************************/ + +/* Chip Identifier / Revision register */ +#define PERF_REV_REG 0x0 +#define REV_CHIPID_SHIFT 16 +#define REV_CHIPID_MASK (0xffff << REV_CHIPID_SHIFT) +#define REV_REVID_SHIFT 0 +#define REV_REVID_MASK (0xffff << REV_REVID_SHIFT) + +/* Clock Control register */ +#define PERF_CKCTL_REG 0x4 + +#define CKCTL_6348_ADSLPHY_EN (1 << 0) +#define CKCTL_6348_MPI_EN (1 << 1) +#define CKCTL_6348_SDRAM_EN (1 << 2) +#define CKCTL_6348_M2M_EN (1 << 3) +#define CKCTL_6348_ENET_EN (1 << 4) +#define CKCTL_6348_SAR_EN (1 << 5) +#define CKCTL_6348_USBS_EN (1 << 6) +#define CKCTL_6348_USBH_EN (1 << 8) +#define CKCTL_6348_SPI_EN (1 << 9) + +#define CKCTL_6348_ALL_SAFE_EN (CKCTL_6348_ADSLPHY_EN | \ + CKCTL_6348_M2M_EN | \ + CKCTL_6348_ENET_EN | \ + CKCTL_6348_SAR_EN | \ + CKCTL_6348_USBS_EN | \ + CKCTL_6348_USBH_EN | \ + CKCTL_6348_SPI_EN) + +#define CKCTL_6358_ENET_EN (1 << 4) +#define CKCTL_6358_ADSLPHY_EN (1 << 5) +#define CKCTL_6358_PCM_EN (1 << 8) +#define CKCTL_6358_SPI_EN (1 << 9) +#define CKCTL_6358_USBS_EN (1 << 10) +#define CKCTL_6358_SAR_EN (1 << 11) +#define CKCTL_6358_EMUSB_EN (1 << 17) +#define CKCTL_6358_ENET0_EN (1 << 18) +#define CKCTL_6358_ENET1_EN (1 << 19) +#define CKCTL_6358_USBSU_EN (1 << 20) +#define CKCTL_6358_EPHY_EN (1 << 21) + +#define CKCTL_6358_ALL_SAFE_EN (CKCTL_6358_ENET_EN | \ + CKCTL_6358_ADSLPHY_EN | \ + CKCTL_6358_PCM_EN | \ + CKCTL_6358_SPI_EN | \ + CKCTL_6358_USBS_EN | \ + CKCTL_6358_SAR_EN | \ + CKCTL_6358_EMUSB_EN | \ + CKCTL_6358_ENET0_EN | \ + CKCTL_6358_ENET1_EN | \ + CKCTL_6358_USBSU_EN | \ + CKCTL_6358_EPHY_EN) + +/* System PLL Control register */ +#define PERF_SYS_PLL_CTL_REG 0x8 +#define SYS_PLL_SOFT_RESET 0x1 + +/* Interrupt Mask register */ +#define PERF_IRQMASK_REG 0xc +#define PERF_IRQSTAT_REG 0x10 + +/* Interrupt Status register */ +#define PERF_IRQSTAT_REG 0x10 + +/* External Interrupt Configuration register */ +#define PERF_EXTIRQ_CFG_REG 0x14 +#define EXTIRQ_CFG_SENSE(x) (1 << (x)) +#define EXTIRQ_CFG_STAT(x) (1 << (x + 5)) +#define EXTIRQ_CFG_CLEAR(x) (1 << (x + 10)) +#define EXTIRQ_CFG_MASK(x) (1 << (x + 15)) +#define EXTIRQ_CFG_BOTHEDGE(x) (1 << (x + 20)) +#define EXTIRQ_CFG_LEVELSENSE(x) (1 << (x + 25)) + +#define EXTIRQ_CFG_CLEAR_ALL (0xf << 10) +#define EXTIRQ_CFG_MASK_ALL (0xf << 15) + +/* Soft Reset register */ +#define PERF_SOFTRESET_REG 0x28 + +#define SOFTRESET_6348_SPI_MASK (1 << 0) +#define SOFTRESET_6348_ENET_MASK (1 << 2) +#define SOFTRESET_6348_USBH_MASK (1 << 3) +#define SOFTRESET_6348_USBS_MASK (1 << 4) +#define SOFTRESET_6348_ADSL_MASK (1 << 5) +#define SOFTRESET_6348_DMAMEM_MASK (1 << 6) +#define SOFTRESET_6348_SAR_MASK (1 << 7) +#define SOFTRESET_6348_ACLC_MASK (1 << 8) +#define SOFTRESET_6348_ADSLMIPSPLL_MASK (1 << 10) + +#define SOFTRESET_6348_ALL (SOFTRESET_6348_SPI_MASK | \ + SOFTRESET_6348_ENET_MASK | \ + SOFTRESET_6348_USBH_MASK | \ + SOFTRESET_6348_USBS_MASK | \ + SOFTRESET_6348_ADSL_MASK | \ + SOFTRESET_6348_DMAMEM_MASK | \ + SOFTRESET_6348_SAR_MASK | \ + SOFTRESET_6348_ACLC_MASK | \ + SOFTRESET_6348_ADSLMIPSPLL_MASK) + +/* MIPS PLL control register */ +#define PERF_MIPSPLLCTL_REG 0x34 +#define MIPSPLLCTL_N1_SHIFT 20 +#define MIPSPLLCTL_N1_MASK (0x7 << MIPSPLLCTL_N1_SHIFT) +#define MIPSPLLCTL_N2_SHIFT 15 +#define MIPSPLLCTL_N2_MASK (0x1f << MIPSPLLCTL_N2_SHIFT) +#define MIPSPLLCTL_M1REF_SHIFT 12 +#define MIPSPLLCTL_M1REF_MASK (0x7 << MIPSPLLCTL_M1REF_SHIFT) +#define MIPSPLLCTL_M2REF_SHIFT 9 +#define MIPSPLLCTL_M2REF_MASK (0x7 << MIPSPLLCTL_M2REF_SHIFT) +#define MIPSPLLCTL_M1CPU_SHIFT 6 +#define MIPSPLLCTL_M1CPU_MASK (0x7 << MIPSPLLCTL_M1CPU_SHIFT) +#define MIPSPLLCTL_M1BUS_SHIFT 3 +#define MIPSPLLCTL_M1BUS_MASK (0x7 << MIPSPLLCTL_M1BUS_SHIFT) +#define MIPSPLLCTL_M2BUS_SHIFT 0 +#define MIPSPLLCTL_M2BUS_MASK (0x7 << MIPSPLLCTL_M2BUS_SHIFT) + +/* ADSL PHY PLL Control register */ +#define PERF_ADSLPLLCTL_REG 0x38 +#define ADSLPLLCTL_N1_SHIFT 20 +#define ADSLPLLCTL_N1_MASK (0x7 << ADSLPLLCTL_N1_SHIFT) +#define ADSLPLLCTL_N2_SHIFT 15 +#define ADSLPLLCTL_N2_MASK (0x1f << ADSLPLLCTL_N2_SHIFT) +#define ADSLPLLCTL_M1REF_SHIFT 12 +#define ADSLPLLCTL_M1REF_MASK (0x7 << ADSLPLLCTL_M1REF_SHIFT) +#define ADSLPLLCTL_M2REF_SHIFT 9 +#define ADSLPLLCTL_M2REF_MASK (0x7 << ADSLPLLCTL_M2REF_SHIFT) +#define ADSLPLLCTL_M1CPU_SHIFT 6 +#define ADSLPLLCTL_M1CPU_MASK (0x7 << ADSLPLLCTL_M1CPU_SHIFT) +#define ADSLPLLCTL_M1BUS_SHIFT 3 +#define ADSLPLLCTL_M1BUS_MASK (0x7 << ADSLPLLCTL_M1BUS_SHIFT) +#define ADSLPLLCTL_M2BUS_SHIFT 0 +#define ADSLPLLCTL_M2BUS_MASK (0x7 << ADSLPLLCTL_M2BUS_SHIFT) + +#define ADSLPLLCTL_VAL(n1, n2, m1ref, m2ref, m1cpu, m1bus, m2bus) \ + (((n1) << ADSLPLLCTL_N1_SHIFT) | \ + ((n2) << ADSLPLLCTL_N2_SHIFT) | \ + ((m1ref) << ADSLPLLCTL_M1REF_SHIFT) | \ + ((m2ref) << ADSLPLLCTL_M2REF_SHIFT) | \ + ((m1cpu) << ADSLPLLCTL_M1CPU_SHIFT) | \ + ((m1bus) << ADSLPLLCTL_M1BUS_SHIFT) | \ + ((m2bus) << ADSLPLLCTL_M2BUS_SHIFT)) + + +/************************************************************************* + * _REG relative to RSET_TIMER + *************************************************************************/ + +#define BCM63XX_TIMER_COUNT 4 +#define TIMER_T0_ID 0 +#define TIMER_T1_ID 1 +#define TIMER_T2_ID 2 +#define TIMER_WDT_ID 3 + +/* Timer irqstat register */ +#define TIMER_IRQSTAT_REG 0 +#define TIMER_IRQSTAT_TIMER_CAUSE(x) (1 << (x)) +#define TIMER_IRQSTAT_TIMER0_CAUSE (1 << 0) +#define TIMER_IRQSTAT_TIMER1_CAUSE (1 << 1) +#define TIMER_IRQSTAT_TIMER2_CAUSE (1 << 2) +#define TIMER_IRQSTAT_WDT_CAUSE (1 << 3) +#define TIMER_IRQSTAT_TIMER_IR_EN(x) (1 << ((x) + 8)) +#define TIMER_IRQSTAT_TIMER0_IR_EN (1 << 8) +#define TIMER_IRQSTAT_TIMER1_IR_EN (1 << 9) +#define TIMER_IRQSTAT_TIMER2_IR_EN (1 << 10) + +/* Timer control register */ +#define TIMER_CTLx_REG(x) (0x4 + (x * 4)) +#define TIMER_CTL0_REG 0x4 +#define TIMER_CTL1_REG 0x8 +#define TIMER_CTL2_REG 0xC +#define TIMER_CTL_COUNTDOWN_MASK (0x3fffffff) +#define TIMER_CTL_MONOTONIC_MASK (1 << 30) +#define TIMER_CTL_ENABLE_MASK (1 << 31) + + +/************************************************************************* + * _REG relative to RSET_WDT + *************************************************************************/ + +/* Watchdog default count register */ +#define WDT_DEFVAL_REG 0x0 + +/* Watchdog control register */ +#define WDT_CTL_REG 0x4 + +/* Watchdog control register constants */ +#define WDT_START_1 (0xff00) +#define WDT_START_2 (0x00ff) +#define WDT_STOP_1 (0xee00) +#define WDT_STOP_2 (0x00ee) + +/* Watchdog reset length register */ +#define WDT_RSTLEN_REG 0x8 + + +/************************************************************************* + * _REG relative to RSET_UARTx + *************************************************************************/ + +/* UART Control Register */ +#define UART_CTL_REG 0x0 +#define UART_CTL_RXTMOUTCNT_SHIFT 0 +#define UART_CTL_RXTMOUTCNT_MASK (0x1f << UART_CTL_RXTMOUTCNT_SHIFT) +#define UART_CTL_RSTTXDN_SHIFT 5 +#define UART_CTL_RSTTXDN_MASK (1 << UART_CTL_RSTTXDN_SHIFT) +#define UART_CTL_RSTRXFIFO_SHIFT 6 +#define UART_CTL_RSTRXFIFO_MASK (1 << UART_CTL_RSTRXFIFO_SHIFT) +#define UART_CTL_RSTTXFIFO_SHIFT 7 +#define UART_CTL_RSTTXFIFO_MASK (1 << UART_CTL_RSTTXFIFO_SHIFT) +#define UART_CTL_STOPBITS_SHIFT 8 +#define UART_CTL_STOPBITS_MASK (0xf << UART_CTL_STOPBITS_SHIFT) +#define UART_CTL_STOPBITS_1 (0x7 << UART_CTL_STOPBITS_SHIFT) +#define UART_CTL_STOPBITS_2 (0xf << UART_CTL_STOPBITS_SHIFT) +#define UART_CTL_BITSPERSYM_SHIFT 12 +#define UART_CTL_BITSPERSYM_MASK (0x3 << UART_CTL_BITSPERSYM_SHIFT) +#define UART_CTL_XMITBRK_SHIFT 14 +#define UART_CTL_XMITBRK_MASK (1 << UART_CTL_XMITBRK_SHIFT) +#define UART_CTL_RSVD_SHIFT 15 +#define UART_CTL_RSVD_MASK (1 << UART_CTL_RSVD_SHIFT) +#define UART_CTL_RXPAREVEN_SHIFT 16 +#define UART_CTL_RXPAREVEN_MASK (1 << UART_CTL_RXPAREVEN_SHIFT) +#define UART_CTL_RXPAREN_SHIFT 17 +#define UART_CTL_RXPAREN_MASK (1 << UART_CTL_RXPAREN_SHIFT) +#define UART_CTL_TXPAREVEN_SHIFT 18 +#define UART_CTL_TXPAREVEN_MASK (1 << UART_CTL_TXPAREVEN_SHIFT) +#define UART_CTL_TXPAREN_SHIFT 18 +#define UART_CTL_TXPAREN_MASK (1 << UART_CTL_TXPAREN_SHIFT) +#define UART_CTL_LOOPBACK_SHIFT 20 +#define UART_CTL_LOOPBACK_MASK (1 << UART_CTL_LOOPBACK_SHIFT) +#define UART_CTL_RXEN_SHIFT 21 +#define UART_CTL_RXEN_MASK (1 << UART_CTL_RXEN_SHIFT) +#define UART_CTL_TXEN_SHIFT 22 +#define UART_CTL_TXEN_MASK (1 << UART_CTL_TXEN_SHIFT) +#define UART_CTL_BRGEN_SHIFT 23 +#define UART_CTL_BRGEN_MASK (1 << UART_CTL_BRGEN_SHIFT) + +/* UART Baudword register */ +#define UART_BAUD_REG 0x4 + +/* UART Misc Control register */ +#define UART_MCTL_REG 0x8 +#define UART_MCTL_DTR_SHIFT 0 +#define UART_MCTL_DTR_MASK (1 << UART_MCTL_DTR_SHIFT) +#define UART_MCTL_RTS_SHIFT 1 +#define UART_MCTL_RTS_MASK (1 << UART_MCTL_RTS_SHIFT) +#define UART_MCTL_RXFIFOTHRESH_SHIFT 8 +#define UART_MCTL_RXFIFOTHRESH_MASK (0xf << UART_MCTL_RXFIFOTHRESH_SHIFT) +#define UART_MCTL_TXFIFOTHRESH_SHIFT 12 +#define UART_MCTL_TXFIFOTHRESH_MASK (0xf << UART_MCTL_TXFIFOTHRESH_SHIFT) +#define UART_MCTL_RXFIFOFILL_SHIFT 16 +#define UART_MCTL_RXFIFOFILL_MASK (0x1f << UART_MCTL_RXFIFOFILL_SHIFT) +#define UART_MCTL_TXFIFOFILL_SHIFT 24 +#define UART_MCTL_TXFIFOFILL_MASK (0x1f << UART_MCTL_TXFIFOFILL_SHIFT) + +/* UART External Input Configuration register */ +#define UART_EXTINP_REG 0xc +#define UART_EXTINP_RI_SHIFT 0 +#define UART_EXTINP_RI_MASK (1 << UART_EXTINP_RI_SHIFT) +#define UART_EXTINP_CTS_SHIFT 1 +#define UART_EXTINP_CTS_MASK (1 << UART_EXTINP_CTS_SHIFT) +#define UART_EXTINP_DCD_SHIFT 2 +#define UART_EXTINP_DCD_MASK (1 << UART_EXTINP_DCD_SHIFT) +#define UART_EXTINP_DSR_SHIFT 3 +#define UART_EXTINP_DSR_MASK (1 << UART_EXTINP_DSR_SHIFT) +#define UART_EXTINP_IRSTAT(x) (1 << (x + 4)) +#define UART_EXTINP_IRMASK(x) (1 << (x + 8)) +#define UART_EXTINP_IR_RI 0 +#define UART_EXTINP_IR_CTS 1 +#define UART_EXTINP_IR_DCD 2 +#define UART_EXTINP_IR_DSR 3 +#define UART_EXTINP_RI_NOSENSE_SHIFT 16 +#define UART_EXTINP_RI_NOSENSE_MASK (1 << UART_EXTINP_RI_NOSENSE_SHIFT) +#define UART_EXTINP_CTS_NOSENSE_SHIFT 17 +#define UART_EXTINP_CTS_NOSENSE_MASK (1 << UART_EXTINP_CTS_NOSENSE_SHIFT) +#define UART_EXTINP_DCD_NOSENSE_SHIFT 18 +#define UART_EXTINP_DCD_NOSENSE_MASK (1 << UART_EXTINP_DCD_NOSENSE_SHIFT) +#define UART_EXTINP_DSR_NOSENSE_SHIFT 19 +#define UART_EXTINP_DSR_NOSENSE_MASK (1 << UART_EXTINP_DSR_NOSENSE_SHIFT) + +/* UART Interrupt register */ +#define UART_IR_REG 0x10 +#define UART_IR_MASK(x) (1 << (x + 16)) +#define UART_IR_STAT(x) (1 << (x)) +#define UART_IR_EXTIP 0 +#define UART_IR_TXUNDER 1 +#define UART_IR_TXOVER 2 +#define UART_IR_TXTRESH 3 +#define UART_IR_TXRDLATCH 4 +#define UART_IR_TXEMPTY 5 +#define UART_IR_RXUNDER 6 +#define UART_IR_RXOVER 7 +#define UART_IR_RXTIMEOUT 8 +#define UART_IR_RXFULL 9 +#define UART_IR_RXTHRESH 10 +#define UART_IR_RXNOTEMPTY 11 +#define UART_IR_RXFRAMEERR 12 +#define UART_IR_RXPARERR 13 +#define UART_IR_RXBRK 14 +#define UART_IR_TXDONE 15 + +/* UART Fifo register */ +#define UART_FIFO_REG 0x14 +#define UART_FIFO_VALID_SHIFT 0 +#define UART_FIFO_VALID_MASK 0xff +#define UART_FIFO_FRAMEERR_SHIFT 8 +#define UART_FIFO_FRAMEERR_MASK (1 << UART_FIFO_FRAMEERR_SHIFT) +#define UART_FIFO_PARERR_SHIFT 9 +#define UART_FIFO_PARERR_MASK (1 << UART_FIFO_PARERR_SHIFT) +#define UART_FIFO_BRKDET_SHIFT 10 +#define UART_FIFO_BRKDET_MASK (1 << UART_FIFO_BRKDET_SHIFT) +#define UART_FIFO_ANYERR_MASK (UART_FIFO_FRAMEERR_MASK | \ + UART_FIFO_PARERR_MASK | \ + UART_FIFO_BRKDET_MASK) + + +/************************************************************************* + * _REG relative to RSET_GPIO + *************************************************************************/ + +/* GPIO registers */ +#define GPIO_CTL_HI_REG 0x0 +#define GPIO_CTL_LO_REG 0x4 +#define GPIO_DATA_HI_REG 0x8 +#define GPIO_DATA_LO_REG 0xC + +/* GPIO mux registers and constants */ +#define GPIO_MODE_REG 0x18 + +#define GPIO_MODE_6348_G4_DIAG 0x00090000 +#define GPIO_MODE_6348_G4_UTOPIA 0x00080000 +#define GPIO_MODE_6348_G4_LEGACY_LED 0x00030000 +#define GPIO_MODE_6348_G4_MII_SNOOP 0x00020000 +#define GPIO_MODE_6348_G4_EXT_EPHY 0x00010000 +#define GPIO_MODE_6348_G3_DIAG 0x00009000 +#define GPIO_MODE_6348_G3_UTOPIA 0x00008000 +#define GPIO_MODE_6348_G3_EXT_MII 0x00007000 +#define GPIO_MODE_6348_G2_DIAG 0x00000900 +#define GPIO_MODE_6348_G2_PCI 0x00000500 +#define GPIO_MODE_6348_G1_DIAG 0x00000090 +#define GPIO_MODE_6348_G1_UTOPIA 0x00000080 +#define GPIO_MODE_6348_G1_SPI_UART 0x00000060 +#define GPIO_MODE_6348_G1_SPI_MASTER 0x00000060 +#define GPIO_MODE_6348_G1_MII_PCCARD 0x00000040 +#define GPIO_MODE_6348_G1_MII_SNOOP 0x00000020 +#define GPIO_MODE_6348_G1_EXT_EPHY 0x00000010 +#define GPIO_MODE_6348_G0_DIAG 0x00000009 +#define GPIO_MODE_6348_G0_EXT_MII 0x00000007 + +#define GPIO_MODE_6358_EXTRACS (1 << 5) +#define GPIO_MODE_6358_UART1 (1 << 6) +#define GPIO_MODE_6358_EXTRA_SPI_SS (1 << 7) +#define GPIO_MODE_6358_SERIAL_LED (1 << 10) +#define GPIO_MODE_6358_UTOPIA (1 << 12) + + +/************************************************************************* + * _REG relative to RSET_ENET + *************************************************************************/ + +/* Receiver Configuration register */ +#define ENET_RXCFG_REG 0x0 +#define ENET_RXCFG_ALLMCAST_SHIFT 1 +#define ENET_RXCFG_ALLMCAST_MASK (1 << ENET_RXCFG_ALLMCAST_SHIFT) +#define ENET_RXCFG_PROMISC_SHIFT 3 +#define ENET_RXCFG_PROMISC_MASK (1 << ENET_RXCFG_PROMISC_SHIFT) +#define ENET_RXCFG_LOOPBACK_SHIFT 4 +#define ENET_RXCFG_LOOPBACK_MASK (1 << ENET_RXCFG_LOOPBACK_SHIFT) +#define ENET_RXCFG_ENFLOW_SHIFT 5 +#define ENET_RXCFG_ENFLOW_MASK (1 << ENET_RXCFG_ENFLOW_SHIFT) + +/* Receive Maximum Length register */ +#define ENET_RXMAXLEN_REG 0x4 +#define ENET_RXMAXLEN_SHIFT 0 +#define ENET_RXMAXLEN_MASK (0x7ff << ENET_RXMAXLEN_SHIFT) + +/* Transmit Maximum Length register */ +#define ENET_TXMAXLEN_REG 0x8 +#define ENET_TXMAXLEN_SHIFT 0 +#define ENET_TXMAXLEN_MASK (0x7ff << ENET_TXMAXLEN_SHIFT) + +/* MII Status/Control register */ +#define ENET_MIISC_REG 0x10 +#define ENET_MIISC_MDCFREQDIV_SHIFT 0 +#define ENET_MIISC_MDCFREQDIV_MASK (0x7f << ENET_MIISC_MDCFREQDIV_SHIFT) +#define ENET_MIISC_PREAMBLEEN_SHIFT 7 +#define ENET_MIISC_PREAMBLEEN_MASK (1 << ENET_MIISC_PREAMBLEEN_SHIFT) + +/* MII Data register */ +#define ENET_MIIDATA_REG 0x14 +#define ENET_MIIDATA_DATA_SHIFT 0 +#define ENET_MIIDATA_DATA_MASK (0xffff << ENET_MIIDATA_DATA_SHIFT) +#define ENET_MIIDATA_TA_SHIFT 16 +#define ENET_MIIDATA_TA_MASK (0x3 << ENET_MIIDATA_TA_SHIFT) +#define ENET_MIIDATA_REG_SHIFT 18 +#define ENET_MIIDATA_REG_MASK (0x1f << ENET_MIIDATA_REG_SHIFT) +#define ENET_MIIDATA_PHYID_SHIFT 23 +#define ENET_MIIDATA_PHYID_MASK (0x1f << ENET_MIIDATA_PHYID_SHIFT) +#define ENET_MIIDATA_OP_READ_MASK (0x6 << 28) +#define ENET_MIIDATA_OP_WRITE_MASK (0x5 << 28) + +/* Ethernet Interrupt Mask register */ +#define ENET_IRMASK_REG 0x18 + +/* Ethernet Interrupt register */ +#define ENET_IR_REG 0x1c +#define ENET_IR_MII (1 << 0) +#define ENET_IR_MIB (1 << 1) +#define ENET_IR_FLOWC (1 << 2) + +/* Ethernet Control register */ +#define ENET_CTL_REG 0x2c +#define ENET_CTL_ENABLE_SHIFT 0 +#define ENET_CTL_ENABLE_MASK (1 << ENET_CTL_ENABLE_SHIFT) +#define ENET_CTL_DISABLE_SHIFT 1 +#define ENET_CTL_DISABLE_MASK (1 << ENET_CTL_DISABLE_SHIFT) +#define ENET_CTL_SRESET_SHIFT 2 +#define ENET_CTL_SRESET_MASK (1 << ENET_CTL_SRESET_SHIFT) +#define ENET_CTL_EPHYSEL_SHIFT 3 +#define ENET_CTL_EPHYSEL_MASK (1 << ENET_CTL_EPHYSEL_SHIFT) + +/* Transmit Control register */ +#define ENET_TXCTL_REG 0x30 +#define ENET_TXCTL_FD_SHIFT 0 +#define ENET_TXCTL_FD_MASK (1 << ENET_TXCTL_FD_SHIFT) + +/* Transmit Watermask register */ +#define ENET_TXWMARK_REG 0x34 +#define ENET_TXWMARK_WM_SHIFT 0 +#define ENET_TXWMARK_WM_MASK (0x3f << ENET_TXWMARK_WM_SHIFT) + +/* MIB Control register */ +#define ENET_MIBCTL_REG 0x38 +#define ENET_MIBCTL_RDCLEAR_SHIFT 0 +#define ENET_MIBCTL_RDCLEAR_MASK (1 << ENET_MIBCTL_RDCLEAR_SHIFT) + +/* Perfect Match Data Low register */ +#define ENET_PML_REG(x) (0x58 + (x) * 8) +#define ENET_PMH_REG(x) (0x5c + (x) * 8) +#define ENET_PMH_DATAVALID_SHIFT 16 +#define ENET_PMH_DATAVALID_MASK (1 << ENET_PMH_DATAVALID_SHIFT) + +/* MIB register */ +#define ENET_MIB_REG(x) (0x200 + (x) * 4) +#define ENET_MIB_REG_COUNT 55 + + +/************************************************************************* + * _REG relative to RSET_ENETDMA + *************************************************************************/ + +/* Controller Configuration Register */ +#define ENETDMA_CFG_REG (0x0) +#define ENETDMA_CFG_EN_SHIFT 0 +#define ENETDMA_CFG_EN_MASK (1 << ENETDMA_CFG_EN_SHIFT) +#define ENETDMA_CFG_FLOWCH_MASK(x) (1 << ((x >> 1) + 1)) + +/* Flow Control Descriptor Low Threshold register */ +#define ENETDMA_FLOWCL_REG(x) (0x4 + (x) * 6) + +/* Flow Control Descriptor High Threshold register */ +#define ENETDMA_FLOWCH_REG(x) (0x8 + (x) * 6) + +/* Flow Control Descriptor Buffer Alloca Threshold register */ +#define ENETDMA_BUFALLOC_REG(x) (0xc + (x) * 6) +#define ENETDMA_BUFALLOC_FORCE_SHIFT 31 +#define ENETDMA_BUFALLOC_FORCE_MASK (1 << ENETDMA_BUFALLOC_FORCE_SHIFT) + +/* Channel Configuration register */ +#define ENETDMA_CHANCFG_REG(x) (0x100 + (x) * 0x10) +#define ENETDMA_CHANCFG_EN_SHIFT 0 +#define ENETDMA_CHANCFG_EN_MASK (1 << ENETDMA_CHANCFG_EN_SHIFT) +#define ENETDMA_CHANCFG_PKTHALT_SHIFT 1 +#define ENETDMA_CHANCFG_PKTHALT_MASK (1 << ENETDMA_CHANCFG_PKTHALT_SHIFT) + +/* Interrupt Control/Status register */ +#define ENETDMA_IR_REG(x) (0x104 + (x) * 0x10) +#define ENETDMA_IR_BUFDONE_MASK (1 << 0) +#define ENETDMA_IR_PKTDONE_MASK (1 << 1) +#define ENETDMA_IR_NOTOWNER_MASK (1 << 2) + +/* Interrupt Mask register */ +#define ENETDMA_IRMASK_REG(x) (0x108 + (x) * 0x10) + +/* Maximum Burst Length */ +#define ENETDMA_MAXBURST_REG(x) (0x10C + (x) * 0x10) + +/* Ring Start Address register */ +#define ENETDMA_RSTART_REG(x) (0x200 + (x) * 0x10) + +/* State Ram Word 2 */ +#define ENETDMA_SRAM2_REG(x) (0x204 + (x) * 0x10) + +/* State Ram Word 3 */ +#define ENETDMA_SRAM3_REG(x) (0x208 + (x) * 0x10) + +/* State Ram Word 4 */ +#define ENETDMA_SRAM4_REG(x) (0x20c + (x) * 0x10) + + +/************************************************************************* + * _REG relative to RSET_OHCI_PRIV + *************************************************************************/ + +#define OHCI_PRIV_REG 0x0 +#define OHCI_PRIV_PORT1_HOST_SHIFT 0 +#define OHCI_PRIV_PORT1_HOST_MASK (1 << OHCI_PRIV_PORT1_HOST_SHIFT) +#define OHCI_PRIV_REG_SWAP_SHIFT 3 +#define OHCI_PRIV_REG_SWAP_MASK (1 << OHCI_PRIV_REG_SWAP_SHIFT) + + +/************************************************************************* + * _REG relative to RSET_USBH_PRIV + *************************************************************************/ + +#define USBH_PRIV_SWAP_REG 0x0 +#define USBH_PRIV_SWAP_EHCI_ENDN_SHIFT 4 +#define USBH_PRIV_SWAP_EHCI_ENDN_MASK (1 << USBH_PRIV_SWAP_EHCI_ENDN_SHIFT) +#define USBH_PRIV_SWAP_EHCI_DATA_SHIFT 3 +#define USBH_PRIV_SWAP_EHCI_DATA_MASK (1 << USBH_PRIV_SWAP_EHCI_DATA_SHIFT) +#define USBH_PRIV_SWAP_OHCI_ENDN_SHIFT 1 +#define USBH_PRIV_SWAP_OHCI_ENDN_MASK (1 << USBH_PRIV_SWAP_OHCI_ENDN_SHIFT) +#define USBH_PRIV_SWAP_OHCI_DATA_SHIFT 0 +#define USBH_PRIV_SWAP_OHCI_DATA_MASK (1 << USBH_PRIV_SWAP_OHCI_DATA_SHIFT) + +#define USBH_PRIV_TEST_REG 0x24 + + +/************************************************************************* + * _REG relative to RSET_MPI + *************************************************************************/ + +/* well known (hard wired) chip select */ +#define MPI_CS_PCMCIA_COMMON 4 +#define MPI_CS_PCMCIA_ATTR 5 +#define MPI_CS_PCMCIA_IO 6 + +/* Chip select base register */ +#define MPI_CSBASE_REG(x) (0x0 + (x) * 8) +#define MPI_CSBASE_BASE_SHIFT 13 +#define MPI_CSBASE_BASE_MASK (0x1ffff << MPI_CSBASE_BASE_SHIFT) +#define MPI_CSBASE_SIZE_SHIFT 0 +#define MPI_CSBASE_SIZE_MASK (0xf << MPI_CSBASE_SIZE_SHIFT) + +#define MPI_CSBASE_SIZE_8K 0 +#define MPI_CSBASE_SIZE_16K 1 +#define MPI_CSBASE_SIZE_32K 2 +#define MPI_CSBASE_SIZE_64K 3 +#define MPI_CSBASE_SIZE_128K 4 +#define MPI_CSBASE_SIZE_256K 5 +#define MPI_CSBASE_SIZE_512K 6 +#define MPI_CSBASE_SIZE_1M 7 +#define MPI_CSBASE_SIZE_2M 8 +#define MPI_CSBASE_SIZE_4M 9 +#define MPI_CSBASE_SIZE_8M 10 +#define MPI_CSBASE_SIZE_16M 11 +#define MPI_CSBASE_SIZE_32M 12 +#define MPI_CSBASE_SIZE_64M 13 +#define MPI_CSBASE_SIZE_128M 14 +#define MPI_CSBASE_SIZE_256M 15 + +/* Chip select control register */ +#define MPI_CSCTL_REG(x) (0x4 + (x) * 8) +#define MPI_CSCTL_ENABLE_MASK (1 << 0) +#define MPI_CSCTL_WAIT_SHIFT 1 +#define MPI_CSCTL_WAIT_MASK (0x7 << MPI_CSCTL_WAIT_SHIFT) +#define MPI_CSCTL_DATA16_MASK (1 << 4) +#define MPI_CSCTL_SYNCMODE_MASK (1 << 7) +#define MPI_CSCTL_TSIZE_MASK (1 << 8) +#define MPI_CSCTL_ENDIANSWAP_MASK (1 << 10) +#define MPI_CSCTL_SETUP_SHIFT 16 +#define MPI_CSCTL_SETUP_MASK (0xf << MPI_CSCTL_SETUP_SHIFT) +#define MPI_CSCTL_HOLD_SHIFT 20 +#define MPI_CSCTL_HOLD_MASK (0xf << MPI_CSCTL_HOLD_SHIFT) + +/* PCI registers */ +#define MPI_SP0_RANGE_REG 0x100 +#define MPI_SP0_REMAP_REG 0x104 +#define MPI_SP0_REMAP_ENABLE_MASK (1 << 0) +#define MPI_SP1_RANGE_REG 0x10C +#define MPI_SP1_REMAP_REG 0x110 +#define MPI_SP1_REMAP_ENABLE_MASK (1 << 0) + +#define MPI_L2PCFG_REG 0x11C +#define MPI_L2PCFG_CFG_TYPE_SHIFT 0 +#define MPI_L2PCFG_CFG_TYPE_MASK (0x3 << MPI_L2PCFG_CFG_TYPE_SHIFT) +#define MPI_L2PCFG_REG_SHIFT 2 +#define MPI_L2PCFG_REG_MASK (0x3f << MPI_L2PCFG_REG_SHIFT) +#define MPI_L2PCFG_FUNC_SHIFT 8 +#define MPI_L2PCFG_FUNC_MASK (0x7 << MPI_L2PCFG_FUNC_SHIFT) +#define MPI_L2PCFG_DEVNUM_SHIFT 11 +#define MPI_L2PCFG_DEVNUM_MASK (0x1f << MPI_L2PCFG_DEVNUM_SHIFT) +#define MPI_L2PCFG_CFG_USEREG_MASK (1 << 30) +#define MPI_L2PCFG_CFG_SEL_MASK (1 << 31) + +#define MPI_L2PMEMRANGE1_REG 0x120 +#define MPI_L2PMEMBASE1_REG 0x124 +#define MPI_L2PMEMREMAP1_REG 0x128 +#define MPI_L2PMEMRANGE2_REG 0x12C +#define MPI_L2PMEMBASE2_REG 0x130 +#define MPI_L2PMEMREMAP2_REG 0x134 +#define MPI_L2PIORANGE_REG 0x138 +#define MPI_L2PIOBASE_REG 0x13C +#define MPI_L2PIOREMAP_REG 0x140 +#define MPI_L2P_BASE_MASK (0xffff8000) +#define MPI_L2PREMAP_ENABLED_MASK (1 << 0) +#define MPI_L2PREMAP_IS_CARDBUS_MASK (1 << 2) + +#define MPI_PCIMODESEL_REG 0x144 +#define MPI_PCIMODESEL_BAR1_NOSWAP_MASK (1 << 0) +#define MPI_PCIMODESEL_BAR2_NOSWAP_MASK (1 << 1) +#define MPI_PCIMODESEL_EXT_ARB_MASK (1 << 2) +#define MPI_PCIMODESEL_PREFETCH_SHIFT 4 +#define MPI_PCIMODESEL_PREFETCH_MASK (0xf << MPI_PCIMODESEL_PREFETCH_SHIFT) + +#define MPI_LOCBUSCTL_REG 0x14C +#define MPI_LOCBUSCTL_EN_PCI_GPIO_MASK (1 << 0) +#define MPI_LOCBUSCTL_U2P_NOSWAP_MASK (1 << 1) + +#define MPI_LOCINT_REG 0x150 +#define MPI_LOCINT_MASK(x) (1 << (x + 16)) +#define MPI_LOCINT_STAT(x) (1 << (x)) +#define MPI_LOCINT_DIR_FAILED 6 +#define MPI_LOCINT_EXT_PCI_INT 7 +#define MPI_LOCINT_SERR 8 +#define MPI_LOCINT_CSERR 9 + +#define MPI_PCICFGCTL_REG 0x178 +#define MPI_PCICFGCTL_CFGADDR_SHIFT 2 +#define MPI_PCICFGCTL_CFGADDR_MASK (0x1f << MPI_PCICFGCTL_CFGADDR_SHIFT) +#define MPI_PCICFGCTL_WRITEEN_MASK (1 << 7) + +#define MPI_PCICFGDATA_REG 0x17C + +/* PCI host bridge custom register */ +#define BCMPCI_REG_TIMERS 0x40 +#define REG_TIMER_TRDY_SHIFT 0 +#define REG_TIMER_TRDY_MASK (0xff << REG_TIMER_TRDY_SHIFT) +#define REG_TIMER_RETRY_SHIFT 8 +#define REG_TIMER_RETRY_MASK (0xff << REG_TIMER_RETRY_SHIFT) + + +/************************************************************************* + * _REG relative to RSET_PCMCIA + *************************************************************************/ + +#define PCMCIA_C1_REG 0x0 +#define PCMCIA_C1_CD1_MASK (1 << 0) +#define PCMCIA_C1_CD2_MASK (1 << 1) +#define PCMCIA_C1_VS1_MASK (1 << 2) +#define PCMCIA_C1_VS2_MASK (1 << 3) +#define PCMCIA_C1_VS1OE_MASK (1 << 6) +#define PCMCIA_C1_VS2OE_MASK (1 << 7) +#define PCMCIA_C1_CBIDSEL_SHIFT (8) +#define PCMCIA_C1_CBIDSEL_MASK (0x1f << PCMCIA_C1_CBIDSEL_SHIFT) +#define PCMCIA_C1_EN_PCMCIA_GPIO_MASK (1 << 13) +#define PCMCIA_C1_EN_PCMCIA_MASK (1 << 14) +#define PCMCIA_C1_EN_CARDBUS_MASK (1 << 15) +#define PCMCIA_C1_RESET_MASK (1 << 18) + +#define PCMCIA_C2_REG 0x8 +#define PCMCIA_C2_DATA16_MASK (1 << 0) +#define PCMCIA_C2_BYTESWAP_MASK (1 << 1) +#define PCMCIA_C2_RWCOUNT_SHIFT 2 +#define PCMCIA_C2_RWCOUNT_MASK (0x3f << PCMCIA_C2_RWCOUNT_SHIFT) +#define PCMCIA_C2_INACTIVE_SHIFT 8 +#define PCMCIA_C2_INACTIVE_MASK (0x3f << PCMCIA_C2_INACTIVE_SHIFT) +#define PCMCIA_C2_SETUP_SHIFT 16 +#define PCMCIA_C2_SETUP_MASK (0x3f << PCMCIA_C2_SETUP_SHIFT) +#define PCMCIA_C2_HOLD_SHIFT 24 +#define PCMCIA_C2_HOLD_MASK (0x3f << PCMCIA_C2_HOLD_SHIFT) + + +/************************************************************************* + * _REG relative to RSET_SDRAM + *************************************************************************/ + +#define SDRAM_CFG_REG 0x0 +#define SDRAM_CFG_ROW_SHIFT 4 +#define SDRAM_CFG_ROW_MASK (0x3 << SDRAM_CFG_ROW_SHIFT) +#define SDRAM_CFG_COL_SHIFT 6 +#define SDRAM_CFG_COL_MASK (0x3 << SDRAM_CFG_COL_SHIFT) +#define SDRAM_CFG_32B_SHIFT 10 +#define SDRAM_CFG_32B_MASK (1 << SDRAM_CFG_32B_SHIFT) +#define SDRAM_CFG_BANK_SHIFT 13 +#define SDRAM_CFG_BANK_MASK (1 << SDRAM_CFG_BANK_SHIFT) + +#define SDRAM_PRIO_REG 0x2C +#define SDRAM_PRIO_MIPS_SHIFT 29 +#define SDRAM_PRIO_MIPS_MASK (1 << SDRAM_PRIO_MIPS_SHIFT) +#define SDRAM_PRIO_ADSL_SHIFT 30 +#define SDRAM_PRIO_ADSL_MASK (1 << SDRAM_PRIO_ADSL_SHIFT) +#define SDRAM_PRIO_EN_SHIFT 31 +#define SDRAM_PRIO_EN_MASK (1 << SDRAM_PRIO_EN_SHIFT) + + +/************************************************************************* + * _REG relative to RSET_MEMC + *************************************************************************/ + +#define MEMC_CFG_REG 0x4 +#define MEMC_CFG_32B_SHIFT 1 +#define MEMC_CFG_32B_MASK (1 << MEMC_CFG_32B_SHIFT) +#define MEMC_CFG_COL_SHIFT 3 +#define MEMC_CFG_COL_MASK (0x3 << MEMC_CFG_COL_SHIFT) +#define MEMC_CFG_ROW_SHIFT 6 +#define MEMC_CFG_ROW_MASK (0x3 << MEMC_CFG_ROW_SHIFT) + + +/************************************************************************* + * _REG relative to RSET_DDR + *************************************************************************/ + +#define DDR_DMIPSPLLCFG_REG 0x18 +#define DMIPSPLLCFG_M1_SHIFT 0 +#define DMIPSPLLCFG_M1_MASK (0xff << DMIPSPLLCFG_M1_SHIFT) +#define DMIPSPLLCFG_N1_SHIFT 23 +#define DMIPSPLLCFG_N1_MASK (0x3f << DMIPSPLLCFG_N1_SHIFT) +#define DMIPSPLLCFG_N2_SHIFT 29 +#define DMIPSPLLCFG_N2_MASK (0x7 << DMIPSPLLCFG_N2_SHIFT) + +#endif /* BCM63XX_REGS_H_ */ + --- /dev/null +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_timer.h @@ -0,0 +1,11 @@ +#ifndef BCM63XX_TIMER_H_ +#define BCM63XX_TIMER_H_ + +int bcm63xx_timer_register(int id, void (*callback)(void *data), void *data); +void bcm63xx_timer_unregister(int id); +int bcm63xx_timer_set(int id, int monotonic, unsigned int countdown_us); +int bcm63xx_timer_enable(int id); +int bcm63xx_timer_disable(int id); +unsigned int bcm63xx_timer_countdown(unsigned int countdown_us); + +#endif /* !BCM63XX_TIMER_H_ */ --- /dev/null +++ b/arch/mips/include/asm/mach-bcm63xx/cpu-feature-overrides.h @@ -0,0 +1,51 @@ +#ifndef __ASM_MACH_BCM963XX_CPU_FEATURE_OVERRIDES_H +#define __ASM_MACH_BCM963XX_CPU_FEATURE_OVERRIDES_H + +#include + +#define cpu_has_tlb 1 +#define cpu_has_4kex 1 +#define cpu_has_4k_cache 1 +#define cpu_has_fpu 0 +#define cpu_has_32fpr 0 +#define cpu_has_counter 1 +#define cpu_has_watch 0 +#define cpu_has_divec 1 +#define cpu_has_vce 0 +#define cpu_has_cache_cdex_p 0 +#define cpu_has_cache_cdex_s 0 +#define cpu_has_prefetch 1 +#define cpu_has_mcheck 1 +#define cpu_has_ejtag 1 +#define cpu_has_llsc 1 +#define cpu_has_mips16 0 +#define cpu_has_mdmx 0 +#define cpu_has_mips3d 0 +#define cpu_has_smartmips 0 +#define cpu_has_vtag_icache 0 + +#if !defined(BCMCPU_RUNTIME_DETECT) && defined(CONFIG_BCMCPU_IS_6348) +#define cpu_has_dc_aliases 0 +#endif + +#define cpu_has_ic_fills_f_dc 0 +#define cpu_has_pindexed_dcache 0 + +#define cpu_has_mips32r1 1 +#define cpu_has_mips32r2 0 +#define cpu_has_mips64r1 0 +#define cpu_has_mips64r2 0 + +#define cpu_has_dsp 0 +#define cpu_has_mipsmt 0 +#define cpu_has_userlocal 0 + +#define cpu_has_nofpuex 0 +#define cpu_has_64bits 0 +#define cpu_has_64bit_zero_reg 0 + +#define cpu_dcache_line_size() 16 +#define cpu_icache_line_size() 16 +#define cpu_scache_line_size() 0 + +#endif /* __ASM_MACH_BCM963XX_CPU_FEATURE_OVERRIDES_H */ --- /dev/null +++ b/arch/mips/include/asm/mach-bcm63xx/gpio.h @@ -0,0 +1,17 @@ +#ifndef __ASM_MIPS_MACH_BCM63XX_GPIO_H +#define __ASM_MIPS_MACH_BCM63XX_GPIO_H + +#include + +#define NR_BUILTIN_GPIO BCM63XX_GPIO_COUNT + +#define gpio_to_irq(gpio) NULL + +#define gpio_get_value __gpio_get_value +#define gpio_set_value __gpio_set_value + +#define gpio_cansleep __gpio_cansleep + +#include + +#endif /* __ASM_MIPS_MACH_BCM63XX_GPIO_H */ --- /dev/null +++ b/arch/mips/include/asm/mach-bcm63xx/war.h @@ -0,0 +1,25 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle + */ +#ifndef __ASM_MIPS_MACH_BCM63XX_WAR_H +#define __ASM_MIPS_MACH_BCM63XX_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 0 +#define MIPS_CACHE_SYNC_WAR 0 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 0 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MIPS_MACH_BCM63XX_WAR_H */ From ralf@linux-mips.org Wed Jul 1 19:07:56 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 01 Jul 2009 19:08:01 +0200 (CEST) Received: (from localhost user: 'ralf' uid#500 fake: STDIN (ralf@eddie.linux-mips.org)) by ftp.linux-mips.org id S1491866AbZGARHK for <"|/home/ecartis/ecartis -s linux-mips">; Wed, 1 Jul 2009 19:07:10 +0200 Message-Id: <20090701120939.528751907@linux-mips.org> User-Agent: quilt/0.47-1 Date: Wed, 01 Jul 2009 12:29:29 +0100 From: Ralf Baechle To: trivial@kernel.org, linux-kernel@vger.kernel.org Cc: linux-mips@linux-mips.org, Maxime Bizon , Florian Fainelli Subject: [patch 03/12] MIPS: BCM63XX: Add serial driver for bcm63xx integrated UART. References: <20090701112926.825088732@linux-mips.org> Content-Disposition: inline; filename=0003.patch Content-Length: 25827 Lines: 1019 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-archive-position: 23569 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips From: Maxime Bizon Signed-off-by: Maxime Bizon Signed-off-by: Ralf Baechle arch/mips/bcm63xx/Makefile | 1 arch/mips/bcm63xx/dev-uart.c | 41 arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_uart.h | 6 drivers/serial/Kconfig | 19 drivers/serial/Makefile | 1 drivers/serial/bcm63xx_uart.c | 890 ++++++++++++++++++ include/linux/serial_core.h | 2 7 files changed, 960 insertions(+) create mode 100644 arch/mips/bcm63xx/dev-uart.c create mode 100644 arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_uart.h create mode 100644 drivers/serial/bcm63xx_uart.c --- a/arch/mips/bcm63xx/Makefile +++ b/arch/mips/bcm63xx/Makefile @@ -1,4 +1,5 @@ obj-y += clk.o cpu.o cs.o gpio.o irq.o prom.o setup.o timer.o +obj-y += dev-uart.o obj-$(CONFIG_EARLY_PRINTK) += early_printk.o EXTRA_CFLAGS += -Werror --- /dev/null +++ b/arch/mips/bcm63xx/dev-uart.c @@ -0,0 +1,41 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2008 Maxime Bizon + */ + +#include +#include +#include +#include +#include + +static struct resource uart_resources[] = { + { + .start = -1, /* filled at runtime */ + .end = -1, /* filled at runtime */ + .flags = IORESOURCE_MEM, + }, + { + .start = -1, /* filled at runtime */ + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device bcm63xx_uart_device = { + .name = "bcm63xx_uart", + .id = 0, + .num_resources = ARRAY_SIZE(uart_resources), + .resource = uart_resources, +}; + +int __init bcm63xx_uart_register(void) +{ + uart_resources[0].start = bcm63xx_regset_address(RSET_UART0); + uart_resources[0].end = uart_resources[0].start; + uart_resources[0].end += RSET_UART_SIZE - 1; + uart_resources[1].start = bcm63xx_get_irq_number(IRQ_UART0); + return platform_device_register(&bcm63xx_uart_device); +} --- /dev/null +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_uart.h @@ -0,0 +1,6 @@ +#ifndef BCM63XX_DEV_UART_H_ +#define BCM63XX_DEV_UART_H_ + +int bcm63xx_uart_register(void); + +#endif /* BCM63XX_DEV_UART_H_ */ --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -1451,4 +1451,23 @@ config SERIAL_TIMBERDALE ---help--- Add support for UART controller on timberdale. +config SERIAL_BCM63XX + tristate "bcm63xx serial port support" + select SERIAL_CORE + depends on BCM63XX + help + If you have a bcm63xx CPU, you can enable its onboard + serial port by enabling this options. + + To compile this driver as a module, choose M here: the + module will be called bcm963xx_uart. + +config SERIAL_BCM63XX_CONSOLE + bool "Console on bcm63xx serial port" + depends on SERIAL_BCM63XX + select SERIAL_CORE_CONSOLE + help + If you have enabled the serial port on the bcm63xx CPU + you can make it the console by answering Y to this option. + endmenu --- a/drivers/serial/Makefile +++ b/drivers/serial/Makefile @@ -34,6 +34,7 @@ obj-$(CONFIG_SERIAL_CLPS711X) += clps711 obj-$(CONFIG_SERIAL_PXA) += pxa.o obj-$(CONFIG_SERIAL_PNX8XXX) += pnx8xxx_uart.o obj-$(CONFIG_SERIAL_SA1100) += sa1100.o +obj-$(CONFIG_SERIAL_BCM63XX) += bcm63xx_uart.o obj-$(CONFIG_SERIAL_BFIN) += bfin_5xx.o obj-$(CONFIG_SERIAL_BFIN_SPORT) += bfin_sport_uart.o obj-$(CONFIG_SERIAL_SAMSUNG) += samsung.o --- /dev/null +++ b/drivers/serial/bcm63xx_uart.c @@ -0,0 +1,890 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Derived from many drivers using generic_serial interface. + * + * Copyright (C) 2008 Maxime Bizon + * + * Serial driver for BCM63xx integrated UART. + * + * Hardware flow control was _not_ tested since I only have RX/TX on + * my board. + */ + +#if defined(CONFIG_SERIAL_BCM63XX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) +#define SUPPORT_SYSRQ +#endif + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#define BCM63XX_NR_UARTS 1 + +static struct uart_port ports[BCM63XX_NR_UARTS]; + +/* + * rx interrupt mask / stat + * + * mask: + * - rx fifo full + * - rx fifo above threshold + * - rx fifo not empty for too long + */ +#define UART_RX_INT_MASK (UART_IR_MASK(UART_IR_RXOVER) | \ + UART_IR_MASK(UART_IR_RXTHRESH) | \ + UART_IR_MASK(UART_IR_RXTIMEOUT)) + +#define UART_RX_INT_STAT (UART_IR_STAT(UART_IR_RXOVER) | \ + UART_IR_STAT(UART_IR_RXTHRESH) | \ + UART_IR_STAT(UART_IR_RXTIMEOUT)) + +/* + * tx interrupt mask / stat + * + * mask: + * - tx fifo empty + * - tx fifo below threshold + */ +#define UART_TX_INT_MASK (UART_IR_MASK(UART_IR_TXEMPTY) | \ + UART_IR_MASK(UART_IR_TXTRESH)) + +#define UART_TX_INT_STAT (UART_IR_STAT(UART_IR_TXEMPTY) | \ + UART_IR_STAT(UART_IR_TXTRESH)) + +/* + * external input interrupt + * + * mask: any edge on CTS, DCD + */ +#define UART_EXTINP_INT_MASK (UART_EXTINP_IRMASK(UART_EXTINP_IR_CTS) | \ + UART_EXTINP_IRMASK(UART_EXTINP_IR_DCD)) + +/* + * handy uart register accessor + */ +static inline unsigned int bcm_uart_readl(struct uart_port *port, + unsigned int offset) +{ + return bcm_readl(port->membase + offset); +} + +static inline void bcm_uart_writel(struct uart_port *port, + unsigned int value, unsigned int offset) +{ + bcm_writel(value, port->membase + offset); +} + +/* + * serial core request to check if uart tx fifo is empty + */ +static unsigned int bcm_uart_tx_empty(struct uart_port *port) +{ + unsigned int val; + + val = bcm_uart_readl(port, UART_IR_REG); + return (val & UART_IR_STAT(UART_IR_TXEMPTY)) ? 1 : 0; +} + +/* + * serial core request to set RTS and DTR pin state and loopback mode + */ +static void bcm_uart_set_mctrl(struct uart_port *port, unsigned int mctrl) +{ + unsigned int val; + + val = bcm_uart_readl(port, UART_MCTL_REG); + val &= ~(UART_MCTL_DTR_MASK | UART_MCTL_RTS_MASK); + /* invert of written value is reflected on the pin */ + if (!(mctrl & TIOCM_DTR)) + val |= UART_MCTL_DTR_MASK; + if (!(mctrl & TIOCM_RTS)) + val |= UART_MCTL_RTS_MASK; + bcm_uart_writel(port, val, UART_MCTL_REG); + + val = bcm_uart_readl(port, UART_CTL_REG); + if (mctrl & TIOCM_LOOP) + val |= UART_CTL_LOOPBACK_MASK; + else + val &= ~UART_CTL_LOOPBACK_MASK; + bcm_uart_writel(port, val, UART_CTL_REG); +} + +/* + * serial core request to return RI, CTS, DCD and DSR pin state + */ +static unsigned int bcm_uart_get_mctrl(struct uart_port *port) +{ + unsigned int val, mctrl; + + mctrl = 0; + val = bcm_uart_readl(port, UART_EXTINP_REG); + if (val & UART_EXTINP_RI_MASK) + mctrl |= TIOCM_RI; + if (val & UART_EXTINP_CTS_MASK) + mctrl |= TIOCM_CTS; + if (val & UART_EXTINP_DCD_MASK) + mctrl |= TIOCM_CD; + if (val & UART_EXTINP_DSR_MASK) + mctrl |= TIOCM_DSR; + return mctrl; +} + +/* + * serial core request to disable tx ASAP (used for flow control) + */ +static void bcm_uart_stop_tx(struct uart_port *port) +{ + unsigned int val; + + val = bcm_uart_readl(port, UART_CTL_REG); + val &= ~(UART_CTL_TXEN_MASK); + bcm_uart_writel(port, val, UART_CTL_REG); + + val = bcm_uart_readl(port, UART_IR_REG); + val &= ~UART_TX_INT_MASK; + bcm_uart_writel(port, val, UART_IR_REG); +} + +/* + * serial core request to (re)enable tx + */ +static void bcm_uart_start_tx(struct uart_port *port) +{ + unsigned int val; + + val = bcm_uart_readl(port, UART_IR_REG); + val |= UART_TX_INT_MASK; + bcm_uart_writel(port, val, UART_IR_REG); + + val = bcm_uart_readl(port, UART_CTL_REG); + val |= UART_CTL_TXEN_MASK; + bcm_uart_writel(port, val, UART_CTL_REG); +} + +/* + * serial core request to stop rx, called before port shutdown + */ +static void bcm_uart_stop_rx(struct uart_port *port) +{ + unsigned int val; + + val = bcm_uart_readl(port, UART_IR_REG); + val &= ~UART_RX_INT_MASK; + bcm_uart_writel(port, val, UART_IR_REG); +} + +/* + * serial core request to enable modem status interrupt reporting + */ +static void bcm_uart_enable_ms(struct uart_port *port) +{ + unsigned int val; + + val = bcm_uart_readl(port, UART_IR_REG); + val |= UART_IR_MASK(UART_IR_EXTIP); + bcm_uart_writel(port, val, UART_IR_REG); +} + +/* + * serial core request to start/stop emitting break char + */ +static void bcm_uart_break_ctl(struct uart_port *port, int ctl) +{ + unsigned long flags; + unsigned int val; + + spin_lock_irqsave(&port->lock, flags); + + val = bcm_uart_readl(port, UART_CTL_REG); + if (ctl) + val |= UART_CTL_XMITBRK_MASK; + else + val &= ~UART_CTL_XMITBRK_MASK; + bcm_uart_writel(port, val, UART_CTL_REG); + + spin_unlock_irqrestore(&port->lock, flags); +} + +/* + * return port type in string format + */ +static const char *bcm_uart_type(struct uart_port *port) +{ + return (port->type == PORT_BCM63XX) ? "bcm63xx_uart" : NULL; +} + +/* + * read all chars in rx fifo and send them to core + */ +static void bcm_uart_do_rx(struct uart_port *port) +{ + struct tty_struct *tty; + unsigned int max_count; + + /* limit number of char read in interrupt, should not be + * higher than fifo size anyway since we're much faster than + * serial port */ + max_count = 32; + tty = port->info->port.tty; + do { + unsigned int iestat, c, cstat; + char flag; + + /* get overrun/fifo empty information from ier + * register */ + iestat = bcm_uart_readl(port, UART_IR_REG); + if (!(iestat & UART_IR_STAT(UART_IR_RXNOTEMPTY))) + break; + + cstat = c = bcm_uart_readl(port, UART_FIFO_REG); + port->icount.rx++; + flag = TTY_NORMAL; + c &= 0xff; + + if (unlikely((cstat & UART_FIFO_ANYERR_MASK))) { + /* do stats first */ + if (cstat & UART_FIFO_BRKDET_MASK) { + port->icount.brk++; + if (uart_handle_break(port)) + continue; + } + + if (cstat & UART_FIFO_PARERR_MASK) + port->icount.parity++; + if (cstat & UART_FIFO_FRAMEERR_MASK) + port->icount.frame++; + + /* update flag wrt read_status_mask */ + cstat &= port->read_status_mask; + if (cstat & UART_FIFO_BRKDET_MASK) + flag = TTY_BREAK; + if (cstat & UART_FIFO_FRAMEERR_MASK) + flag = TTY_FRAME; + if (cstat & UART_FIFO_PARERR_MASK) + flag = TTY_PARITY; + } + + if (uart_handle_sysrq_char(port, c)) + continue; + + if (unlikely(iestat & UART_IR_STAT(UART_IR_RXOVER))) { + port->icount.overrun++; + tty_insert_flip_char(tty, 0, TTY_OVERRUN); + } + + if ((cstat & port->ignore_status_mask) == 0) + tty_insert_flip_char(tty, c, flag); + + } while (--max_count); + + tty_flip_buffer_push(tty); +} + +/* + * fill tx fifo with chars to send, stop when fifo is about to be full + * or when all chars have been sent. + */ +static void bcm_uart_do_tx(struct uart_port *port) +{ + struct circ_buf *xmit; + unsigned int val, max_count; + + if (port->x_char) { + bcm_uart_writel(port, port->x_char, UART_FIFO_REG); + port->icount.tx++; + port->x_char = 0; + return; + } + + if (uart_tx_stopped(port)) { + bcm_uart_stop_tx(port); + return; + } + + xmit = &port->info->xmit; + if (uart_circ_empty(xmit)) + goto txq_empty; + + val = bcm_uart_readl(port, UART_MCTL_REG); + val = (val & UART_MCTL_TXFIFOFILL_MASK) >> UART_MCTL_TXFIFOFILL_SHIFT; + max_count = port->fifosize - val; + + while (max_count--) { + unsigned int c; + + c = xmit->buf[xmit->tail]; + bcm_uart_writel(port, c, UART_FIFO_REG); + xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); + port->icount.tx++; + if (uart_circ_empty(xmit)) + break; + } + + if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) + uart_write_wakeup(port); + + if (uart_circ_empty(xmit)) + goto txq_empty; + return; + +txq_empty: + /* nothing to send, disable transmit interrupt */ + val = bcm_uart_readl(port, UART_IR_REG); + val &= ~UART_TX_INT_MASK; + bcm_uart_writel(port, val, UART_IR_REG); + return; +} + +/* + * process uart interrupt + */ +static irqreturn_t bcm_uart_interrupt(int irq, void *dev_id) +{ + struct uart_port *port; + unsigned int irqstat; + + port = dev_id; + spin_lock(&port->lock); + + irqstat = bcm_uart_readl(port, UART_IR_REG); + if (irqstat & UART_RX_INT_STAT) + bcm_uart_do_rx(port); + + if (irqstat & UART_TX_INT_STAT) + bcm_uart_do_tx(port); + + if (irqstat & UART_IR_MASK(UART_IR_EXTIP)) { + unsigned int estat; + + estat = bcm_uart_readl(port, UART_EXTINP_REG); + if (estat & UART_EXTINP_IRSTAT(UART_EXTINP_IR_CTS)) + uart_handle_cts_change(port, + estat & UART_EXTINP_CTS_MASK); + if (estat & UART_EXTINP_IRSTAT(UART_EXTINP_IR_DCD)) + uart_handle_dcd_change(port, + estat & UART_EXTINP_DCD_MASK); + } + + spin_unlock(&port->lock); + return IRQ_HANDLED; +} + +/* + * enable rx & tx operation on uart + */ +static void bcm_uart_enable(struct uart_port *port) +{ + unsigned int val; + + val = bcm_uart_readl(port, UART_CTL_REG); + val |= (UART_CTL_BRGEN_MASK | UART_CTL_TXEN_MASK | UART_CTL_RXEN_MASK); + bcm_uart_writel(port, val, UART_CTL_REG); +} + +/* + * disable rx & tx operation on uart + */ +static void bcm_uart_disable(struct uart_port *port) +{ + unsigned int val; + + val = bcm_uart_readl(port, UART_CTL_REG); + val &= ~(UART_CTL_BRGEN_MASK | UART_CTL_TXEN_MASK | + UART_CTL_RXEN_MASK); + bcm_uart_writel(port, val, UART_CTL_REG); +} + +/* + * clear all unread data in rx fifo and unsent data in tx fifo + */ +static void bcm_uart_flush(struct uart_port *port) +{ + unsigned int val; + + /* empty rx and tx fifo */ + val = bcm_uart_readl(port, UART_CTL_REG); + val |= UART_CTL_RSTRXFIFO_MASK | UART_CTL_RSTTXFIFO_MASK; + bcm_uart_writel(port, val, UART_CTL_REG); + + /* read any pending char to make sure all irq status are + * cleared */ + (void)bcm_uart_readl(port, UART_FIFO_REG); +} + +/* + * serial core request to initialize uart and start rx operation + */ +static int bcm_uart_startup(struct uart_port *port) +{ + unsigned int val; + int ret; + + /* mask all irq and flush port */ + bcm_uart_disable(port); + bcm_uart_writel(port, 0, UART_IR_REG); + bcm_uart_flush(port); + + /* clear any pending external input interrupt */ + (void)bcm_uart_readl(port, UART_EXTINP_REG); + + /* set rx/tx fifo thresh to fifo half size */ + val = bcm_uart_readl(port, UART_MCTL_REG); + val &= ~(UART_MCTL_RXFIFOTHRESH_MASK | UART_MCTL_TXFIFOTHRESH_MASK); + val |= (port->fifosize / 2) << UART_MCTL_RXFIFOTHRESH_SHIFT; + val |= (port->fifosize / 2) << UART_MCTL_TXFIFOTHRESH_SHIFT; + bcm_uart_writel(port, val, UART_MCTL_REG); + + /* set rx fifo timeout to 1 char time */ + val = bcm_uart_readl(port, UART_CTL_REG); + val &= ~UART_CTL_RXTMOUTCNT_MASK; + val |= 1 << UART_CTL_RXTMOUTCNT_SHIFT; + bcm_uart_writel(port, val, UART_CTL_REG); + + /* report any edge on dcd and cts */ + val = UART_EXTINP_INT_MASK; + val |= UART_EXTINP_DCD_NOSENSE_MASK; + val |= UART_EXTINP_CTS_NOSENSE_MASK; + bcm_uart_writel(port, val, UART_EXTINP_REG); + + /* register irq and enable rx interrupts */ + ret = request_irq(port->irq, bcm_uart_interrupt, 0, + bcm_uart_type(port), port); + if (ret) + return ret; + bcm_uart_writel(port, UART_RX_INT_MASK, UART_IR_REG); + bcm_uart_enable(port); + return 0; +} + +/* + * serial core request to flush & disable uart + */ +static void bcm_uart_shutdown(struct uart_port *port) +{ + unsigned long flags; + + spin_lock_irqsave(&port->lock, flags); + bcm_uart_writel(port, 0, UART_IR_REG); + spin_unlock_irqrestore(&port->lock, flags); + + bcm_uart_disable(port); + bcm_uart_flush(port); + free_irq(port->irq, port); +} + +/* + * serial core request to change current uart setting + */ +static void bcm_uart_set_termios(struct uart_port *port, + struct ktermios *new, + struct ktermios *old) +{ + unsigned int ctl, baud, quot, ier; + unsigned long flags; + + spin_lock_irqsave(&port->lock, flags); + + /* disable uart while changing speed */ + bcm_uart_disable(port); + bcm_uart_flush(port); + + /* update Control register */ + ctl = bcm_uart_readl(port, UART_CTL_REG); + ctl &= ~UART_CTL_BITSPERSYM_MASK; + + switch (new->c_cflag & CSIZE) { + case CS5: + ctl |= (0 << UART_CTL_BITSPERSYM_SHIFT); + break; + case CS6: + ctl |= (1 << UART_CTL_BITSPERSYM_SHIFT); + break; + case CS7: + ctl |= (2 << UART_CTL_BITSPERSYM_SHIFT); + break; + default: + ctl |= (3 << UART_CTL_BITSPERSYM_SHIFT); + break; + } + + ctl &= ~UART_CTL_STOPBITS_MASK; + if (new->c_cflag & CSTOPB) + ctl |= UART_CTL_STOPBITS_2; + else + ctl |= UART_CTL_STOPBITS_1; + + ctl &= ~(UART_CTL_RXPAREN_MASK | UART_CTL_TXPAREN_MASK); + if (new->c_cflag & PARENB) + ctl |= (UART_CTL_RXPAREN_MASK | UART_CTL_TXPAREN_MASK); + ctl &= ~(UART_CTL_RXPAREVEN_MASK | UART_CTL_TXPAREVEN_MASK); + if (new->c_cflag & PARODD) + ctl |= (UART_CTL_RXPAREVEN_MASK | UART_CTL_TXPAREVEN_MASK); + bcm_uart_writel(port, ctl, UART_CTL_REG); + + /* update Baudword register */ + baud = uart_get_baud_rate(port, new, old, 0, port->uartclk / 16); + quot = uart_get_divisor(port, baud) - 1; + bcm_uart_writel(port, quot, UART_BAUD_REG); + + /* update Interrupt register */ + ier = bcm_uart_readl(port, UART_IR_REG); + + ier &= ~UART_IR_MASK(UART_IR_EXTIP); + if (UART_ENABLE_MS(port, new->c_cflag)) + ier |= UART_IR_MASK(UART_IR_EXTIP); + + bcm_uart_writel(port, ier, UART_IR_REG); + + /* update read/ignore mask */ + port->read_status_mask = UART_FIFO_VALID_MASK; + if (new->c_iflag & INPCK) { + port->read_status_mask |= UART_FIFO_FRAMEERR_MASK; + port->read_status_mask |= UART_FIFO_PARERR_MASK; + } + if (new->c_iflag & (BRKINT)) + port->read_status_mask |= UART_FIFO_BRKDET_MASK; + + port->ignore_status_mask = 0; + if (new->c_iflag & IGNPAR) + port->ignore_status_mask |= UART_FIFO_PARERR_MASK; + if (new->c_iflag & IGNBRK) + port->ignore_status_mask |= UART_FIFO_BRKDET_MASK; + if (!(new->c_cflag & CREAD)) + port->ignore_status_mask |= UART_FIFO_VALID_MASK; + + uart_update_timeout(port, new->c_cflag, baud); + bcm_uart_enable(port); + spin_unlock_irqrestore(&port->lock, flags); +} + +/* + * serial core request to claim uart iomem + */ +static int bcm_uart_request_port(struct uart_port *port) +{ + unsigned int size; + + size = RSET_UART_SIZE; + if (!request_mem_region(port->mapbase, size, "bcm63xx")) { + dev_err(port->dev, "Memory region busy\n"); + return -EBUSY; + } + + port->membase = ioremap(port->mapbase, size); + if (!port->membase) { + dev_err(port->dev, "Unable to map registers\n"); + release_mem_region(port->mapbase, size); + return -EBUSY; + } + return 0; +} + +/* + * serial core request to release uart iomem + */ +static void bcm_uart_release_port(struct uart_port *port) +{ + release_mem_region(port->mapbase, RSET_UART_SIZE); + iounmap(port->membase); +} + +/* + * serial core request to do any port required autoconfiguration + */ +static void bcm_uart_config_port(struct uart_port *port, int flags) +{ + if (flags & UART_CONFIG_TYPE) { + if (bcm_uart_request_port(port)) + return; + port->type = PORT_BCM63XX; + } +} + +/* + * serial core request to check that port information in serinfo are + * suitable + */ +static int bcm_uart_verify_port(struct uart_port *port, + struct serial_struct *serinfo) +{ + if (port->type != PORT_BCM63XX) + return -EINVAL; + if (port->irq != serinfo->irq) + return -EINVAL; + if (port->iotype != serinfo->io_type) + return -EINVAL; + if (port->mapbase != (unsigned long)serinfo->iomem_base) + return -EINVAL; + return 0; +} + +/* serial core callbacks */ +static struct uart_ops bcm_uart_ops = { + .tx_empty = bcm_uart_tx_empty, + .get_mctrl = bcm_uart_get_mctrl, + .set_mctrl = bcm_uart_set_mctrl, + .start_tx = bcm_uart_start_tx, + .stop_tx = bcm_uart_stop_tx, + .stop_rx = bcm_uart_stop_rx, + .enable_ms = bcm_uart_enable_ms, + .break_ctl = bcm_uart_break_ctl, + .startup = bcm_uart_startup, + .shutdown = bcm_uart_shutdown, + .set_termios = bcm_uart_set_termios, + .type = bcm_uart_type, + .release_port = bcm_uart_release_port, + .request_port = bcm_uart_request_port, + .config_port = bcm_uart_config_port, + .verify_port = bcm_uart_verify_port, +}; + + + +#ifdef CONFIG_SERIAL_BCM63XX_CONSOLE +static inline void wait_for_xmitr(struct uart_port *port) +{ + unsigned int tmout; + + /* Wait up to 10ms for the character(s) to be sent. */ + tmout = 10000; + while (--tmout) { + unsigned int val; + + val = bcm_uart_readl(port, UART_IR_REG); + if (val & UART_IR_STAT(UART_IR_TXEMPTY)) + break; + udelay(1); + } + + /* Wait up to 1s for flow control if necessary */ + if (port->flags & UPF_CONS_FLOW) { + tmout = 1000000; + while (--tmout) { + unsigned int val; + + val = bcm_uart_readl(port, UART_EXTINP_REG); + if (val & UART_EXTINP_CTS_MASK) + break; + udelay(1); + } + } +} + +/* + * output given char + */ +static void bcm_console_putchar(struct uart_port *port, int ch) +{ + wait_for_xmitr(port); + bcm_uart_writel(port, ch, UART_FIFO_REG); +} + +/* + * console core request to output given string + */ +static void bcm_console_write(struct console *co, const char *s, + unsigned int count) +{ + struct uart_port *port; + unsigned long flags; + int locked; + + port = &ports[co->index]; + + local_irq_save(flags); + if (port->sysrq) { + /* bcm_uart_interrupt() already took the lock */ + locked = 0; + } else if (oops_in_progress) { + locked = spin_trylock(&port->lock); + } else { + spin_lock(&port->lock); + locked = 1; + } + + /* call helper to deal with \r\n */ + uart_console_write(port, s, count, bcm_console_putchar); + + /* and wait for char to be transmitted */ + wait_for_xmitr(port); + + if (locked) + spin_unlock(&port->lock); + local_irq_restore(flags); +} + +/* + * console core request to setup given console, find matching uart + * port and setup it. + */ +static int bcm_console_setup(struct console *co, char *options) +{ + struct uart_port *port; + int baud = 9600; + int bits = 8; + int parity = 'n'; + int flow = 'n'; + + if (co->index < 0 || co->index >= BCM63XX_NR_UARTS) + return -EINVAL; + port = &ports[co->index]; + if (!port->membase) + return -ENODEV; + if (options) + uart_parse_options(options, &baud, &parity, &bits, &flow); + + return uart_set_options(port, co, baud, parity, bits, flow); +} + +static struct uart_driver bcm_uart_driver; + +static struct console bcm63xx_console = { + .name = "ttyS", + .write = bcm_console_write, + .device = uart_console_device, + .setup = bcm_console_setup, + .flags = CON_PRINTBUFFER, + .index = -1, + .data = &bcm_uart_driver, +}; + +static int __init bcm63xx_console_init(void) +{ + register_console(&bcm63xx_console); + return 0; +} + +console_initcall(bcm63xx_console_init); + +#define BCM63XX_CONSOLE (&bcm63xx_console) +#else +#define BCM63XX_CONSOLE NULL +#endif /* CONFIG_SERIAL_BCM63XX_CONSOLE */ + +static struct uart_driver bcm_uart_driver = { + .owner = THIS_MODULE, + .driver_name = "bcm63xx_uart", + .dev_name = "ttyS", + .major = TTY_MAJOR, + .minor = 64, + .nr = 1, + .cons = BCM63XX_CONSOLE, +}; + +/* + * platform driver probe/remove callback + */ +static int __devinit bcm_uart_probe(struct platform_device *pdev) +{ + struct resource *res_mem, *res_irq; + struct uart_port *port; + struct clk *clk; + int ret; + + if (pdev->id < 0 || pdev->id >= BCM63XX_NR_UARTS) + return -EINVAL; + + if (ports[pdev->id].membase) + return -EBUSY; + + res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res_mem) + return -ENODEV; + + res_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); + if (!res_irq) + return -ENODEV; + + clk = clk_get(&pdev->dev, "periph"); + if (IS_ERR(clk)) + return -ENODEV; + + port = &ports[pdev->id]; + memset(port, 0, sizeof(*port)); + port->iotype = UPIO_MEM; + port->mapbase = res_mem->start; + port->irq = res_irq->start; + port->ops = &bcm_uart_ops; + port->flags = UPF_BOOT_AUTOCONF; + port->dev = &pdev->dev; + port->fifosize = 16; + port->uartclk = clk_get_rate(clk) / 2; + clk_put(clk); + + ret = uart_add_one_port(&bcm_uart_driver, port); + if (ret) { + kfree(port); + return ret; + } + platform_set_drvdata(pdev, port); + return 0; +} + +static int __devexit bcm_uart_remove(struct platform_device *pdev) +{ + struct uart_port *port; + + port = platform_get_drvdata(pdev); + uart_remove_one_port(&bcm_uart_driver, port); + platform_set_drvdata(pdev, NULL); + /* mark port as free */ + ports[pdev->id].membase = 0; + return 0; +} + +/* + * platform driver stuff + */ +static struct platform_driver bcm_uart_platform_driver = { + .probe = bcm_uart_probe, + .remove = __devexit_p(bcm_uart_remove), + .driver = { + .owner = THIS_MODULE, + .name = "bcm63xx_uart", + }, +}; + +static int __init bcm_uart_init(void) +{ + int ret; + + ret = uart_register_driver(&bcm_uart_driver); + if (ret) + return ret; + + ret = platform_driver_register(&bcm_uart_platform_driver); + if (ret) + uart_unregister_driver(&bcm_uart_driver); + + return ret; +} + +static void __exit bcm_uart_exit(void) +{ + platform_driver_unregister(&bcm_uart_platform_driver); + uart_unregister_driver(&bcm_uart_driver); +} + +module_init(bcm_uart_init); +module_exit(bcm_uart_exit); + +MODULE_AUTHOR("Maxime Bizon "); +MODULE_DESCRIPTION("Broadcom 63 From ralf@linux-mips.org Wed Jul 1 19:08:18 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 01 Jul 2009 19:08:23 +0200 (CEST) Received: (from localhost user: 'ralf' uid#500 fake: STDIN (ralf@eddie.linux-mips.org)) by ftp.linux-mips.org id S1491867AbZGARHK for <"|/home/ecartis/ecartis -s linux-mips">; Wed, 1 Jul 2009 19:07:10 +0200 Message-Id: <20090701120939.608878291@linux-mips.org> User-Agent: quilt/0.47-1 Date: Wed, 01 Jul 2009 12:29:30 +0100 From: Ralf Baechle To: linux-mips@linux-mips.org Cc: Maxime Bizon , Florian Fainelli Subject: [patch 04/12] MIPS: BCM63XX: Add PCI support. References: <20090701112926.825088732@linux-mips.org> Content-Disposition: inline; filename=0004.patch Content-Length: 13572 Lines: 481 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-archive-position: 23570 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips From: Maxime Bizon Signed-off-by: Maxime Bizon Signed-off-by: Ralf Baechle arch/mips/bcm63xx/Kconfig | 2 arch/mips/bcm63xx/setup.c | 2 arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_pci.h | 6 arch/mips/pci/Makefile | 2 arch/mips/pci/fixup-bcm63xx.c | 21 ++ arch/mips/pci/ops-bcm63xx.c | 179 ++++++++++++++++++ arch/mips/pci/pci-bcm63xx.c | 180 +++++++++++++++++++ arch/mips/pci/pci-bcm63xx.h | 27 ++ 8 files changed, 419 insertions(+) create mode 100644 arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_pci.h create mode 100644 arch/mips/pci/fixup-bcm63xx.c create mode 100644 arch/mips/pci/ops-bcm63xx.c create mode 100644 arch/mips/pci/pci-bcm63xx.c create mode 100644 arch/mips/pci/pci-bcm63xx.h --- a/arch/mips/bcm63xx/Kconfig +++ b/arch/mips/bcm63xx/Kconfig @@ -3,7 +3,9 @@ menu "CPU support" config BCM63XX_CPU_6348 bool "support 6348 CPU" + select HW_HAS_PCI config BCM63XX_CPU_6358 bool "support 6358 CPU" + select HW_HAS_PCI endmenu --- a/arch/mips/bcm63xx/setup.c +++ b/arch/mips/bcm63xx/setup.c @@ -108,4 +108,6 @@ void __init plat_mem_setup(void) pm_power_off = bcm63xx_machine_halt; set_io_port_base(0); + ioport_resource.start = 0; + ioport_resource.end = ~0; } --- /dev/null +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_pci.h @@ -0,0 +1,6 @@ +#ifndef BCM63XX_DEV_PCI_H_ +#define BCM63XX_DEV_PCI_H_ + +extern int bcm63xx_pci_enabled; + +#endif /* BCM63XX_DEV_PCI_H_ */ --- a/arch/mips/pci/Makefile +++ b/arch/mips/pci/Makefile @@ -16,6 +16,8 @@ obj-$(CONFIG_PCI_VR41XX) += ops-vr41xx.o obj-$(CONFIG_NEC_MARKEINS) += ops-emma2rh.o pci-emma2rh.o fixup-emma2rh.o obj-$(CONFIG_PCI_TX4927) += ops-tx4927.o obj-$(CONFIG_BCM47XX) += pci-bcm47xx.o +obj-$(CONFIG_BCM63XX) += pci-bcm63xx.o fixup-bcm63xx.o \ + ops-bcm63xx.o # # These are still pretty much in the old state, watch, go blind. --- /dev/null +++ b/arch/mips/pci/fixup-bcm63xx.c @@ -0,0 +1,21 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2008 Maxime Bizon + */ + +#include +#include +#include + +int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) +{ + return bcm63xx_get_irq_number(IRQ_PCI); +} + +int pcibios_plat_dev_init(struct pci_dev *dev) +{ + return 0; +} --- /dev/null +++ b/arch/mips/pci/ops-bcm63xx.c @@ -0,0 +1,179 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2008 Maxime Bizon + */ + +#include +#include +#include +#include +#include +#include + +#include "pci-bcm63xx.h" + +/* + * swizzle 32bits data to return only the needed part + */ +static int postprocess_read(u32 data, int where, unsigned int size) +{ + u32 ret; + + ret = 0; + switch (size) { + case 1: + ret = (data >> ((where & 3) << 3)) & 0xff; + break; + case 2: + ret = (data >> ((where & 3) << 3)) & 0xffff; + break; + case 4: + ret = data; + break; + } + return ret; +} + +static int preprocess_write(u32 orig_data, u32 val, int where, + unsigned int size) +{ + u32 ret; + + ret = 0; + switch (size) { + case 1: + ret = (orig_data & ~(0xff << ((where & 3) << 3))) | + (val << ((where & 3) << 3)); + break; + case 2: + ret = (orig_data & ~(0xffff << ((where & 3) << 3))) | + (val << ((where & 3) << 3)); + break; + case 4: + ret = val; + break; + } + return ret; +} + +/* + * setup hardware for a configuration cycle with given parameters + */ +static int bcm63xx_setup_cfg_access(int type, unsigned int busn, + unsigned int devfn, int where) +{ + unsigned int slot, func, reg; + u32 val; + + slot = PCI_SLOT(devfn); + func = PCI_FUNC(devfn); + reg = where >> 2; + + /* sanity check */ + if (slot > (MPI_L2PCFG_DEVNUM_MASK >> MPI_L2PCFG_DEVNUM_SHIFT)) + return 1; + + if (func > (MPI_L2PCFG_FUNC_MASK >> MPI_L2PCFG_FUNC_SHIFT)) + return 1; + + if (reg > (MPI_L2PCFG_REG_MASK >> MPI_L2PCFG_REG_SHIFT)) + return 1; + + /* ok, setup config access */ + val = (reg << MPI_L2PCFG_REG_SHIFT); + val |= (func << MPI_L2PCFG_FUNC_SHIFT); + val |= (slot << MPI_L2PCFG_DEVNUM_SHIFT); + val |= MPI_L2PCFG_CFG_USEREG_MASK; + val |= MPI_L2PCFG_CFG_SEL_MASK; + /* type 0 cycle for local bus, type 1 cycle for anything else */ + if (type != 0) { + /* FIXME: how to specify bus ??? */ + val |= (1 << MPI_L2PCFG_CFG_TYPE_SHIFT); + } + bcm_mpi_writel(val, MPI_L2PCFG_REG); + + return 0; +} + +static int bcm63xx_do_cfg_read(int type, unsigned int busn, + unsigned int devfn, int where, int size, + u32 *val) +{ + u32 data; + + /* two phase cycle, first we write address, then read data at + * another location, caller already has a spinlock so no need + * to add one here */ + if (bcm63xx_setup_cfg_access(type, busn, devfn, where)) + return PCIBIOS_DEVICE_NOT_FOUND; + iob(); + data = le32_to_cpu(__raw_readl(pci_iospace_start)); + /* restore IO space normal behaviour */ + bcm_mpi_writel(0, MPI_L2PCFG_REG); + + *val = postprocess_read(data, where, size); + + return PCIBIOS_SUCCESSFUL; +} + +static int bcm63xx_do_cfg_write(int type, unsigned int busn, + unsigned int devfn, int where, int size, + u32 val) +{ + u32 data; + + /* two phase cycle, first we write address, then write data to + * another location, caller already has a spinlock so no need + * to add one here */ + if (bcm63xx_setup_cfg_access(type, busn, devfn, where)) + return PCIBIOS_DEVICE_NOT_FOUND; + iob(); + + data = le32_to_cpu(__raw_readl(pci_iospace_start)); + data = preprocess_write(data, val, where, size); + + __raw_writel(cpu_to_le32(data), pci_iospace_start); + wmb(); + /* no way to know the access is done, we have to wait */ + udelay(500); + /* restore IO space normal behaviour */ + bcm_mpi_writel(0, MPI_L2PCFG_REG); + + return PCIBIOS_SUCCESSFUL; +} + +static int bcm63xx_pci_read(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 *val) +{ + int type; + + type = bus->parent ? 1 : 0; + + if (type == 0 && PCI_SLOT(devfn) == CARDBUS_PCI_IDSEL) + return PCIBIOS_DEVICE_NOT_FOUND; + + return bcm63xx_do_cfg_read(type, bus->number, devfn, + where, size, val); +} + +static int bcm63xx_pci_write(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 val) +{ + int type; + + type = bus->parent ? 1 : 0; + + if (type == 0 && PCI_SLOT(devfn) == CARDBUS_PCI_IDSEL) + return PCIBIOS_DEVICE_NOT_FOUND; + + return bcm63xx_do_cfg_write(type, bus->number, devfn, + where, size, val); +} + +struct pci_ops bcm63xx_pci_ops = { + .read = bcm63xx_pci_read, + .write = bcm63xx_pci_write +}; --- /dev/null +++ b/arch/mips/pci/pci-bcm63xx.c @@ -0,0 +1,180 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2008 Maxime Bizon + */ + +#include +#include +#include +#include +#include + +#include "pci-bcm63xx.h" + +/* + * Allow PCI to be disabled at runtime depending on board nvram + * configuration + */ +int bcm63xx_pci_enabled; + +static struct resource bcm_pci_mem_resource = { + .name = "bcm63xx PCI memory space", + .start = BCM_PCI_MEM_BASE_PA, + .end = BCM_PCI_MEM_END_PA, + .flags = IORESOURCE_MEM +}; + +static struct resource bcm_pci_io_resource = { + .name = "bcm63xx PCI IO space", + .start = BCM_PCI_IO_BASE_PA, + .end = BCM_PCI_IO_END_PA, + .flags = IORESOURCE_IO +}; + +struct pci_controller bcm63xx_controller = { + .pci_ops = &bcm63xx_pci_ops, + .io_resource = &bcm_pci_io_resource, + .mem_resource = &bcm_pci_mem_resource, +}; + +static u32 bcm63xx_int_cfg_readl(u32 reg) +{ + u32 tmp; + + tmp = reg & MPI_PCICFGCTL_CFGADDR_MASK; + tmp |= MPI_PCICFGCTL_WRITEEN_MASK; + bcm_mpi_writel(tmp, MPI_PCICFGCTL_REG); + iob(); + return bcm_mpi_readl(MPI_PCICFGDATA_REG); +} + +static void bcm63xx_int_cfg_writel(u32 val, u32 reg) +{ + u32 tmp; + + tmp = reg & MPI_PCICFGCTL_CFGADDR_MASK; + tmp |= MPI_PCICFGCTL_WRITEEN_MASK; + bcm_mpi_writel(tmp, MPI_PCICFGCTL_REG); + bcm_mpi_writel(val, MPI_PCICFGDATA_REG); +} + +void __iomem *pci_iospace_start; + +static int __init bcm63xx_pci_init(void) +{ + unsigned int mem_size; + u32 val; + + if (!BCMCPU_IS_6348() && !BCMCPU_IS_6358()) + return -ENODEV; + + if (!bcm63xx_pci_enabled) + return -ENODEV; + + /* + * configuration access are done through IO space, remap 4 + * first bytes to access it from CPU. + * + * this means that no io access from CPU should happen while + * we do a configuration cycle, but there's no way we can add + * a spinlock for each io access, so this is currently kind of + * broken on SMP. + */ + pci_iospace_start = ioremap_nocache(BCM_PCI_IO_BASE_PA, 4); + if (!pci_iospace_start) + return -ENOMEM; + + /* setup local bus to PCI access (PCI memory) */ + val = BCM_PCI_MEM_BASE_PA & MPI_L2P_BASE_MASK; + bcm_mpi_writel(val, MPI_L2PMEMBASE1_REG); + bcm_mpi_writel(~(BCM_PCI_MEM_SIZE - 1), MPI_L2PMEMRANGE1_REG); + bcm_mpi_writel(val | MPI_L2PREMAP_ENABLED_MASK, MPI_L2PMEMREMAP1_REG); + + /* set Cardbus IDSEL (type 0 cfg access on primary bus for + * this IDSEL will be done on Cardbus instead) */ + val = bcm_pcmcia_readl(PCMCIA_C1_REG); + val &= ~PCMCIA_C1_CBIDSEL_MASK; + val |= (CARDBUS_PCI_IDSEL << PCMCIA_C1_CBIDSEL_SHIFT); + bcm_pcmcia_writel(val, PCMCIA_C1_REG); + + /* disable second access windows */ + bcm_mpi_writel(0, MPI_L2PMEMREMAP2_REG); + + /* setup local bus to PCI access (IO memory), we have only 1 + * IO window for both PCI and cardbus, but it cannot handle + * both at the same time, assume standard PCI for now, if + * cardbus card has IO zone, PCI fixup will change window to + * cardbus */ + val = BCM_PCI_IO_BASE_PA & MPI_L2P_BASE_MASK; + bcm_mpi_writel(val, MPI_L2PIOBASE_REG); + bcm_mpi_writel(~(BCM_PCI_IO_SIZE - 1), MPI_L2PIORANGE_REG); + bcm_mpi_writel(val | MPI_L2PREMAP_ENABLED_MASK, MPI_L2PIOREMAP_REG); + + /* enable PCI related GPIO pins */ + bcm_mpi_writel(MPI_LOCBUSCTL_EN_PCI_GPIO_MASK, MPI_LOCBUSCTL_REG); + + /* setup PCI to local bus access, used by PCI device to target + * local RAM while bus mastering */ + bcm63xx_int_cfg_writel(0, PCI_BASE_ADDRESS_3); + if (BCMCPU_IS_6358()) + val = MPI_SP0_REMAP_ENABLE_MASK; + else + val = 0; + bcm_mpi_writel(val, MPI_SP0_REMAP_REG); + + bcm63xx_int_cfg_writel(0x0, PCI_BASE_ADDRESS_4); + bcm_mpi_writel(0, MPI_SP1_REMAP_REG); + + mem_size = bcm63xx_get_memory_size(); + + /* 6348 before rev b0 exposes only 16 MB of RAM memory through + * PCI, throw a warning if we have more memory */ + if (BCMCPU_IS_6348() && (bcm63xx_get_cpu_rev() & 0xf0) == 0xa0) { + if (mem_size > (16 * 1024 * 1024)) + printk(KERN_WARNING "bcm63xx: this CPU " + "revision cannot handle more than 16MB " + "of RAM for PCI bus mastering\n"); + } else { + /* setup sp0 range to local RAM size */ + bcm_mpi_writel(~(mem_size - 1), MPI_SP0_RANGE_REG); + bcm_mpi_writel(0, MPI_SP1_RANGE_REG); + } + + /* change host bridge retry counter to infinite number of + * retry, needed for some broadcom wifi cards with Silicon + * Backplane bus where access to srom seems very slow */ + val = bcm63xx_int_cfg_readl(BCMPCI_REG_TIMERS); + val &= ~REG_TIMER_RETRY_MASK; + bcm63xx_int_cfg_writel(val, BCMPCI_REG_TIMERS); + + /* enable memory decoder and bus mastering */ + val = bcm63xx_int_cfg_readl(PCI_COMMAND); + val |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); + bcm63xx_int_cfg_writel(val, PCI_COMMAND); + + /* enable read prefetching & disable byte swapping for bus + * mastering transfers */ + val = bcm_mpi_readl(MPI_PCIMODESEL_REG); + val &= ~MPI_PCIMODESEL_BAR1_NOSWAP_MASK; + val &= ~MPI_PCIMODESEL_BAR2_NOSWAP_MASK; + val &= ~MPI_PCIMODESEL_PREFETCH_MASK; + val |= (8 << MPI_PCIMODESEL_PREFETCH_SHIFT); + bcm_mpi_writel(val, MPI_PCIMODESEL_REG); + + /* enable pci interrupt */ + val = bcm_mpi_readl(MPI_LOCINT_REG); + val |= MPI_LOCINT_MASK(MPI_LOCINT_EXT_PCI_INT); + bcm_mpi_writel(val, MPI_LOCINT_REG); + + register_pci_controller(&bcm63xx_controller); + + /* mark memory space used for IO mapping as reserved */ + request_mem_region(BCM_PCI_IO_BASE_PA, BCM_PCI_IO_SIZE, + "bcm63xx PCI IO space"); + return 0; +} + +arch_initcall(bcm63xx_pci_init); --- /dev/null +++ b/arch/mips/pci/pci-bcm63xx.h @@ -0,0 +1,27 @@ +#ifndef PCI_BCM63XX_H_ +#define PCI_BCM63XX_H_ + +#include +#include +#include +#include + +/* + * Cardbus shares the PCI bus, but has no IDSEL, so a special id is + * reserved for it. If you have a standard PCI device at this id, you + * need to change the following definition. + */ +#define CARDBUS_PCI_IDSEL 0x8 + +/* + * defined in ops-bcm63xx.c + */ +extern struct pci_ops bcm63xx_pci_ops; +extern struct pci_ops bcm63xx_cb_ops; + +/* + * defined in pci-bcm63xx.c + */ +extern void __iomem *pci_iospace_start; + +#endif /* ! PCI_BCM63XX_H_ */ From ralf@linux-mips.org Wed Jul 1 19:08:40 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 01 Jul 2009 19:08:45 +0200 (CEST) Received: (from localhost user: 'ralf' uid#500 fake: STDIN (ralf@eddie.linux-mips.org)) by ftp.linux-mips.org id S1491869AbZGARHK for <"|/home/ecartis/ecartis -s linux-mips">; Wed, 1 Jul 2009 19:07:10 +0200 Message-Id: <20090701120939.686495768@linux-mips.org> User-Agent: quilt/0.47-1 Date: Wed, 01 Jul 2009 12:29:31 +0100 From: Ralf Baechle To: linux-mips@linux-mips.org Cc: Maxime Bizon , Florian Fainelli Subject: [patch 05/12] MIPS: BCM63XX: Change PCI code to emulate a fake cardbus bridge. References: <20090701112926.825088732@linux-mips.org> Content-Disposition: inline; filename=0005.patch Content-Length: 10058 Lines: 381 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-archive-position: 23571 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips From: Maxime Bizon Signed-off-by: Maxime Bizon Signed-off-by: Ralf Baechle arch/mips/pci/ops-bcm63xx.c | 288 ++++++++++++++++++++++++++++++++++++++++++++ arch/mips/pci/pci-bcm63xx.c | 44 ++++++ 2 files changed, 332 insertions(+) --- a/arch/mips/pci/ops-bcm63xx.c +++ b/arch/mips/pci/ops-bcm63xx.c @@ -177,3 +177,291 @@ struct pci_ops bcm63xx_pci_ops = { .read = bcm63xx_pci_read, .write = bcm63xx_pci_write }; + +#ifdef CONFIG_CARDBUS +/* + * emulate configuration read access on a cardbus bridge + */ +#define FAKE_CB_BRIDGE_SLOT 0x1e + +static int fake_cb_bridge_bus_number = -1; + +static struct { + u16 pci_command; + u8 cb_latency; + u8 subordinate_busn; + u8 cardbus_busn; + u8 pci_busn; + int bus_assigned; + u16 bridge_control; + + u32 mem_base0; + u32 mem_limit0; + u32 mem_base1; + u32 mem_limit1; + + u32 io_base0; + u32 io_limit0; + u32 io_base1; + u32 io_limit1; +} fake_cb_bridge_regs; + +static int fake_cb_bridge_read(int where, int size, u32 *val) +{ + unsigned int reg; + u32 data; + + data = 0; + reg = where >> 2; + switch (reg) { + case (PCI_VENDOR_ID >> 2): + case (PCI_CB_SUBSYSTEM_VENDOR_ID >> 2): + /* create dummy vendor/device id from our cpu id */ + data = (bcm63xx_get_cpu_id() << 16) | PCI_VENDOR_ID_BROADCOM; + break; + + case (PCI_COMMAND >> 2): + data = (PCI_STATUS_DEVSEL_SLOW << 16); + data |= fake_cb_bridge_regs.pci_command; + break; + + case (PCI_CLASS_REVISION >> 2): + data = (PCI_CLASS_BRIDGE_CARDBUS << 16); + break; + + case (PCI_CACHE_LINE_SIZE >> 2): + data = (PCI_HEADER_TYPE_CARDBUS << 16); + break; + + case (PCI_INTERRUPT_LINE >> 2): + /* bridge control */ + data = (fake_cb_bridge_regs.bridge_control << 16); + /* pin:intA line:0xff */ + data |= (0x1 << 8) | 0xff; + break; + + case (PCI_CB_PRIMARY_BUS >> 2): + data = (fake_cb_bridge_regs.cb_latency << 24); + data |= (fake_cb_bridge_regs.subordinate_busn << 16); + data |= (fake_cb_bridge_regs.cardbus_busn << 8); + data |= fake_cb_bridge_regs.pci_busn; + break; + + case (PCI_CB_MEMORY_BASE_0 >> 2): + data = fake_cb_bridge_regs.mem_base0; + break; + + case (PCI_CB_MEMORY_LIMIT_0 >> 2): + data = fake_cb_bridge_regs.mem_limit0; + break; + + case (PCI_CB_MEMORY_BASE_1 >> 2): + data = fake_cb_bridge_regs.mem_base1; + break; + + case (PCI_CB_MEMORY_LIMIT_1 >> 2): + data = fake_cb_bridge_regs.mem_limit1; + break; + + case (PCI_CB_IO_BASE_0 >> 2): + /* | 1 for 32bits io support */ + data = fake_cb_bridge_regs.io_base0 | 0x1; + break; + + case (PCI_CB_IO_LIMIT_0 >> 2): + data = fake_cb_bridge_regs.io_limit0; + break; + + case (PCI_CB_IO_BASE_1 >> 2): + /* | 1 for 32bits io support */ + data = fake_cb_bridge_regs.io_base1 | 0x1; + break; + + case (PCI_CB_IO_LIMIT_1 >> 2): + data = fake_cb_bridge_regs.io_limit1; + break; + } + + *val = postprocess_read(data, where, size); + return PCIBIOS_SUCCESSFUL; +} + +/* + * emulate configuration write access on a cardbus bridge + */ +static int fake_cb_bridge_write(int where, int size, u32 val) +{ + unsigned int reg; + u32 data, tmp; + int ret; + + ret = fake_cb_bridge_read((where & ~0x3), 4, &data); + if (ret != PCIBIOS_SUCCESSFUL) + return ret; + + data = preprocess_write(data, val, where, size); + + reg = where >> 2; + switch (reg) { + case (PCI_COMMAND >> 2): + fake_cb_bridge_regs.pci_command = (data & 0xffff); + break; + + case (PCI_CB_PRIMARY_BUS >> 2): + fake_cb_bridge_regs.cb_latency = (data >> 24) & 0xff; + fake_cb_bridge_regs.subordinate_busn = (data >> 16) & 0xff; + fake_cb_bridge_regs.cardbus_busn = (data >> 8) & 0xff; + fake_cb_bridge_regs.pci_busn = data & 0xff; + if (fake_cb_bridge_regs.cardbus_busn) + fake_cb_bridge_regs.bus_assigned = 1; + break; + + case (PCI_INTERRUPT_LINE >> 2): + tmp = (data >> 16) & 0xffff; + /* disable memory prefetch support */ + tmp &= ~PCI_CB_BRIDGE_CTL_PREFETCH_MEM0; + tmp &= ~PCI_CB_BRIDGE_CTL_PREFETCH_MEM1; + fake_cb_bridge_regs.bridge_control = tmp; + break; + + case (PCI_CB_MEMORY_BASE_0 >> 2): + fake_cb_bridge_regs.mem_base0 = data; + break; + + case (PCI_CB_MEMORY_LIMIT_0 >> 2): + fake_cb_bridge_regs.mem_limit0 = data; + break; + + case (PCI_CB_MEMORY_BASE_1 >> 2): + fake_cb_bridge_regs.mem_base1 = data; + break; + + case (PCI_CB_MEMORY_LIMIT_1 >> 2): + fake_cb_bridge_regs.mem_limit1 = data; + break; + + case (PCI_CB_IO_BASE_0 >> 2): + fake_cb_bridge_regs.io_base0 = data; + break; + + case (PCI_CB_IO_LIMIT_0 >> 2): + fake_cb_bridge_regs.io_limit0 = data; + break; + + case (PCI_CB_IO_BASE_1 >> 2): + fake_cb_bridge_regs.io_base1 = data; + break; + + case (PCI_CB_IO_LIMIT_1 >> 2): + fake_cb_bridge_regs.io_limit1 = data; + break; + } + + return PCIBIOS_SUCCESSFUL; +} + +static int bcm63xx_cb_read(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 *val) +{ + /* snoop access to slot 0x1e on root bus, we fake a cardbus + * bridge at this location */ + if (!bus->parent && PCI_SLOT(devfn) == FAKE_CB_BRIDGE_SLOT) { + fake_cb_bridge_bus_number = bus->number; + return fake_cb_bridge_read(where, size, val); + } + + /* a configuration cycle for the device behind the cardbus + * bridge is actually done as a type 0 cycle on the primary + * bus. This means that only one device can be on the cardbus + * bus */ + if (fake_cb_bridge_regs.bus_assigned && + bus->number == fake_cb_bridge_regs.cardbus_busn && + PCI_SLOT(devfn) == 0) + return bcm63xx_do_cfg_read(0, 0, + PCI_DEVFN(CARDBUS_PCI_IDSEL, 0), + where, size, val); + + return PCIBIOS_DEVICE_NOT_FOUND; +} + +static int bcm63xx_cb_write(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 val) +{ + if (!bus->parent && PCI_SLOT(devfn) == FAKE_CB_BRIDGE_SLOT) { + fake_cb_bridge_bus_number = bus->number; + return fake_cb_bridge_write(where, size, val); + } + + if (fake_cb_bridge_regs.bus_assigned && + bus->number == fake_cb_bridge_regs.cardbus_busn && + PCI_SLOT(devfn) == 0) + return bcm63xx_do_cfg_write(0, 0, + PCI_DEVFN(CARDBUS_PCI_IDSEL, 0), + where, size, val); + + return PCIBIOS_DEVICE_NOT_FOUND; +} + +struct pci_ops bcm63xx_cb_ops = { + .read = bcm63xx_cb_read, + .write = bcm63xx_cb_write, +}; + +/* + * only one IO window, so it cannot be shared by PCI and cardbus, use + * fixup to choose and detect unhandled configuration + */ +static void bcm63xx_fixup(struct pci_dev *dev) +{ + static int io_window = -1; + int i, found, new_io_window; + u32 val; + + /* look for any io resource */ + found = 0; + for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { + if (pci_resource_flags(dev, i) & IORESOURCE_IO) { + found = 1; + break; + } + } + + if (!found) + return; + + /* skip our fake bus with only cardbus bridge on it */ + if (dev->bus->number == fake_cb_bridge_bus_number) + return; + + /* find on which bus the device is */ + if (fake_cb_bridge_regs.bus_assigned && + dev->bus->number == fake_cb_bridge_regs.cardbus_busn && + PCI_SLOT(dev->devfn) == 0) + new_io_window = 1; + else + new_io_window = 0; + + if (new_io_window == io_window) + return; + + if (io_window != -1) { + printk(KERN_ERR "bcm63xx: both PCI and cardbus devices " + "need IO, which hardware cannot do\n"); + return; + } + + printk(KERN_INFO "bcm63xx: PCI IO window assigned to %s\n", + (new_io_window == 0) ? "PCI" : "cardbus"); + + val = bcm_mpi_readl(MPI_L2PIOREMAP_REG); + if (io_window) + val |= MPI_L2PREMAP_IS_CARDBUS_MASK; + else + val &= ~MPI_L2PREMAP_IS_CARDBUS_MASK; + bcm_mpi_writel(val, MPI_L2PIOREMAP_REG); + + io_window = new_io_window; +} + +DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID, PCI_ANY_ID, bcm63xx_fixup); +#endif --- a/arch/mips/pci/pci-bcm63xx.c +++ b/arch/mips/pci/pci-bcm63xx.c @@ -30,7 +30,11 @@ static struct resource bcm_pci_mem_resou static struct resource bcm_pci_io_resource = { .name = "bcm63xx PCI IO space", .start = BCM_PCI_IO_BASE_PA, +#ifdef CONFIG_CARDBUS + .end = BCM_PCI_IO_HALF_PA, +#else .end = BCM_PCI_IO_END_PA, +#endif .flags = IORESOURCE_IO }; @@ -40,6 +44,33 @@ struct pci_controller bcm63xx_controller .mem_resource = &bcm_pci_mem_resource, }; +/* + * We handle cardbus via a fake Cardbus bridge, memory and io spaces + * have to be clearly separated from PCI one since we have different + * memory decoder. + */ +#ifdef CONFIG_CARDBUS +static struct resource bcm_cb_mem_resource = { + .name = "bcm63xx Cardbus memory space", + .start = BCM_CB_MEM_BASE_PA, + .end = BCM_CB_MEM_END_PA, + .flags = IORESOURCE_MEM +}; + +static struct resource bcm_cb_io_resource = { + .name = "bcm63xx Cardbus IO space", + .start = BCM_PCI_IO_HALF_PA + 1, + .end = BCM_PCI_IO_END_PA, + .flags = IORESOURCE_IO +}; + +struct pci_controller bcm63xx_cb_controller = { + .pci_ops = &bcm63xx_cb_ops, + .io_resource = &bcm_cb_io_resource, + .mem_resource = &bcm_cb_mem_resource, +}; +#endif + static u32 bcm63xx_int_cfg_readl(u32 reg) { u32 tmp; @@ -100,8 +131,17 @@ static int __init bcm63xx_pci_init(void) val |= (CARDBUS_PCI_IDSEL << PCMCIA_C1_CBIDSEL_SHIFT); bcm_pcmcia_writel(val, PCMCIA_C1_REG); +#ifdef CONFIG_CARDBUS + /* setup local bus to PCI access (Cardbus memory) */ + val = BCM_CB_MEM_BASE_PA & MPI_L2P_BASE_MASK; + bcm_mpi_writel(val, MPI_L2PMEMBASE2_REG); + bcm_mpi_writel(~(BCM_CB_MEM_SIZE - 1), MPI_L2PMEMRANGE2_REG); + val |= MPI_L2PREMAP_ENABLED_MASK | MPI_L2PREMAP_IS_CARDBUS_MASK; + bcm_mpi_writel(val, MPI_L2PMEMREMAP2_REG); +#else /* disable second access windows */ bcm_mpi_writel(0, MPI_L2PMEMREMAP2_REG); +#endif /* setup local bus to PCI access (IO memory), we have only 1 * IO window for both PCI and cardbus, but it cannot handle @@ -171,6 +211,10 @@ static int __init bcm63xx_pci_init(void) register_pci_controller(&bcm63xx_controller); +#ifdef CONFIG_CARDBUS + register_pci_controller(&bcm63xx_cb_controller); +#endif + /* mark memory space used for IO mapping as reserved */ request_mem_region(BCM_PCI_IO_BASE_PA, BCM_PCI_IO_SIZE, "bcm63xx PCI IO space"); From ralf@linux-mips.org Wed Jul 1 19:09:02 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 01 Jul 2009 19:09:07 +0200 (CEST) Received: (from localhost user: 'ralf' uid#500 fake: STDIN (ralf@eddie.linux-mips.org)) by ftp.linux-mips.org id S1491870AbZGARHK for <"|/home/ecartis/ecartis -s linux-mips">; Wed, 1 Jul 2009 19:07:10 +0200 Message-Id: <20090701120939.765282038@linux-mips.org> User-Agent: quilt/0.47-1 Date: Wed, 01 Jul 2009 12:29:32 +0100 From: Ralf Baechle To: linux-mips@linux-mips.org, linux-pcmcia@lists.infradead.org Cc: Maxime Bizon , Florian Fainelli Subject: [patch 06/12] MIPS: BCM63XX: Add PCMCIA & Cardbus support. References: <20090701112926.825088732@linux-mips.org> Content-Disposition: inline; filename=0006.patch Content-Length: 20915 Lines: 797 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-archive-position: 23572 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips From: Maxime Bizon Signed-off-by: Maxime Bizon Signed-off-by: Ralf Baechle arch/mips/bcm63xx/Makefile | 1 arch/mips/bcm63xx/dev-pcmcia.c | 135 ++++ arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_pcmcia.h | 13 drivers/pcmcia/Kconfig | 4 drivers/pcmcia/Makefile | 1 drivers/pcmcia/bcm63xx_pcmcia.c | 521 ++++++++++++++++ drivers/pcmcia/bcm63xx_pcmcia.h | 65 + 7 files changed, 740 insertions(+) create mode 100644 arch/mips/bcm63xx/dev-pcmcia.c create mode 100644 arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_pcmcia.h create mode 100644 drivers/pcmcia/bcm63xx_pcmcia.c create mode 100644 drivers/pcmcia/bcm63xx_pcmcia.h --- a/arch/mips/bcm63xx/Makefile +++ b/arch/mips/bcm63xx/Makefile @@ -1,5 +1,6 @@ obj-y += clk.o cpu.o cs.o gpio.o irq.o prom.o setup.o timer.o obj-y += dev-uart.o +obj-y += dev-pcmcia.o obj-$(CONFIG_EARLY_PRINTK) += early_printk.o EXTRA_CFLAGS += -Werror --- /dev/null +++ b/arch/mips/bcm63xx/dev-pcmcia.c @@ -0,0 +1,135 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2008 Maxime Bizon + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static struct resource pcmcia_resources[] = { + /* pcmcia registers */ + { + .start = -1, /* filled at runtime */ + .end = -1, /* filled at runtime */ + .flags = IORESOURCE_MEM, + }, + + /* pcmcia memory zone resources */ + { + .start = BCM_PCMCIA_COMMON_BASE_PA, + .end = BCM_PCMCIA_COMMON_END_PA, + .flags = IORESOURCE_MEM, + }, + { + .start = BCM_PCMCIA_ATTR_BASE_PA, + .end = BCM_PCMCIA_ATTR_END_PA, + .flags = IORESOURCE_MEM, + }, + { + .start = BCM_PCMCIA_IO_BASE_PA, + .end = BCM_PCMCIA_IO_END_PA, + .flags = IORESOURCE_MEM, + }, + + /* PCMCIA irq */ + { + .start = -1, /* filled at runtime */ + .flags = IORESOURCE_IRQ, + }, + + /* declare PCMCIA IO resource also */ + { + .start = BCM_PCMCIA_IO_BASE_PA, + .end = BCM_PCMCIA_IO_END_PA, + .flags = IORESOURCE_IO, + }, +}; + +static struct bcm63xx_pcmcia_platform_data pd; + +static struct platform_device bcm63xx_pcmcia_device = { + .name = "bcm63xx_pcmcia", + .id = 0, + .num_resources = ARRAY_SIZE(pcmcia_resources), + .resource = pcmcia_resources, + .dev = { + .platform_data = &pd, + }, +}; + +static int __init config_pcmcia_cs(unsigned int cs, + u32 base, unsigned int size) +{ + int ret; + + ret = bcm63xx_set_cs_status(cs, 0); + if (!ret) + ret = bcm63xx_set_cs_base(cs, base, size); + if (!ret) + ret = bcm63xx_set_cs_status(cs, 1); + return ret; +} + +static const __initdata unsigned int pcmcia_cs[3][3] = { + /* cs, base address, size */ + { MPI_CS_PCMCIA_COMMON, BCM_PCMCIA_COMMON_BASE_PA, + BCM_PCMCIA_COMMON_SIZE }, + + { MPI_CS_PCMCIA_ATTR, BCM_PCMCIA_ATTR_BASE_PA, + BCM_PCMCIA_ATTR_SIZE }, + + { MPI_CS_PCMCIA_IO, BCM_PCMCIA_IO_BASE_PA, + BCM_PCMCIA_IO_SIZE }, +}; + +int __init bcm63xx_pcmcia_register(void) +{ + int ret, i; + + if (!BCMCPU_IS_6348() && !BCMCPU_IS_6358()) + return 0; + + /* use correct pcmcia ready gpio depending on processor */ + switch (bcm63xx_get_cpu_id()) { + case BCM6348_CPU_ID: + pd.ready_gpio = 22; + break; + + case BCM6358_CPU_ID: + pd.ready_gpio = 22; + break; + + default: + return -ENODEV; + } + + pcmcia_resources[0].start = bcm63xx_regset_address(RSET_PCMCIA); + pcmcia_resources[0].end = pcmcia_resources[0].start; + pcmcia_resources[0].end += RSET_PCMCIA_SIZE - 1; + pcmcia_resources[4].start = bcm63xx_get_irq_number(IRQ_PCMCIA); + + /* configure pcmcia chip selects */ + for (i = 0; i < 3; i++) { + ret = config_pcmcia_cs(pcmcia_cs[i][0], + pcmcia_cs[i][1], + pcmcia_cs[i][2]); + if (ret) + goto out_err; + } + + return platform_device_register(&bcm63xx_pcmcia_device); + +out_err: + printk(KERN_ERR "unable to set pcmcia chip select"); + return ret; +} --- /dev/null +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_pcmcia.h @@ -0,0 +1,13 @@ +#ifndef BCM63XX_DEV_PCMCIA_H_ +#define BCM63XX_DEV_PCMCIA_H_ + +/* + * PCMCIA driver platform data + */ +struct bcm63xx_pcmcia_platform_data { + unsigned int ready_gpio; +}; + +int bcm63xx_pcmcia_register(void); + +#endif /* BCM63XX_DEV_PCMCIA_H_ */ --- a/drivers/pcmcia/Kconfig +++ b/drivers/pcmcia/Kconfig @@ -192,6 +192,10 @@ config PCMCIA_AU1X00 tristate "Au1x00 pcmcia support" depends on SOC_AU1X00 && PCMCIA +config PCMCIA_BCM63XX + tristate "bcm63xx pcmcia support" + depends on BCM63XX && PCMCIA + config PCMCIA_SA1100 tristate "SA1100 support" depends on ARM && ARCH_SA1100 && PCMCIA --- a/drivers/pcmcia/Makefile +++ b/drivers/pcmcia/Makefile @@ -27,6 +27,7 @@ obj-$(CONFIG_PCMCIA_SA1111) += sa11xx_ obj-$(CONFIG_M32R_PCC) += m32r_pcc.o obj-$(CONFIG_M32R_CFC) += m32r_cfc.o obj-$(CONFIG_PCMCIA_AU1X00) += au1x00_ss.o +obj-$(CONFIG_PCMCIA_BCM63XX) += bcm63xx_pcmcia.o obj-$(CONFIG_PCMCIA_VRC4171) += vrc4171_card.o obj-$(CONFIG_PCMCIA_VRC4173) += vrc4173_cardu.o obj-$(CONFIG_OMAP_CF) += omap_cf.o --- /dev/null +++ b/drivers/pcmcia/bcm63xx_pcmcia.c @@ -0,0 +1,521 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2008 Maxime Bizon + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include "bcm63xx_pcmcia.h" + +#define PFX "bcm63xx_pcmcia: " + +#ifdef CONFIG_CARDBUS +/* if cardbus is used, platform device needs reference to actual pci + * device */ +static struct pci_dev *bcm63xx_cb_dev; +#endif + +/* + * read/write helper for pcmcia regs + */ +static inline u32 pcmcia_readl(struct bcm63xx_pcmcia_socket *skt, u32 off) +{ + return bcm_readl(skt->base + off); +} + +static inline void pcmcia_writel(struct bcm63xx_pcmcia_socket *skt, + u32 val, u32 off) +{ + bcm_writel(val, skt->base + off); +} + +/* + * (Re-)Initialise the socket, turning on status interrupts and PCMCIA + * bus. This must wait for power to stabilise so that the card status + * signals report correctly. + */ +static int bcm63xx_pcmcia_sock_init(struct pcmcia_socket *sock) +{ + struct bcm63xx_pcmcia_socket *skt; + skt = sock->driver_data; + return 0; +} + +/* + * Remove power on the socket, disable IRQs from the card. + * Turn off status interrupts, and disable the PCMCIA bus. + */ +static int bcm63xx_pcmcia_suspend(struct pcmcia_socket *sock) +{ + struct bcm63xx_pcmcia_socket *skt; + skt = sock->driver_data; + return 0; +} + +/* + * Implements the set_socket() operation for the in-kernel PCMCIA + * service (formerly SS_SetSocket in Card Services). We more or + * less punt all of this work and let the kernel handle the details + * of power configuration, reset, &c. We also record the value of + * `state' in order to regurgitate it to the PCMCIA core later. + */ +static int bcm63xx_pcmcia_set_socket(struct pcmcia_socket *sock, + socket_state_t *state) +{ + struct bcm63xx_pcmcia_socket *skt; + unsigned long flags; + u32 val; + + skt = sock->driver_data; + + spin_lock_irqsave(&skt->lock, flags); + + /* apply requested socket power */ + /* FIXME: hardware can't do this */ + + /* apply socket reset */ + val = pcmcia_readl(skt, PCMCIA_C1_REG); + if (state->flags & SS_RESET) + val |= PCMCIA_C1_RESET_MASK; + else + val &= ~PCMCIA_C1_RESET_MASK; + + /* reverse reset logic for cardbus card */ + if (skt->card_detected && (skt->card_type & CARD_CARDBUS)) + val ^= PCMCIA_C1_RESET_MASK; + + pcmcia_writel(skt, val, PCMCIA_C1_REG); + + /* keep requested state for event reporting */ + skt->requested_state = *state; + + spin_unlock_irqrestore(&skt->lock, flags); + + return 0; +} + +/* + * identity cardtype from VS[12] input, CD[12] input while only VS2 is + * floating, and CD[12] input while only VS1 is floating + */ +enum { + IN_VS1 = (1 << 0), + IN_VS2 = (1 << 1), + IN_CD1_VS2H = (1 << 2), + IN_CD2_VS2H = (1 << 3), + IN_CD1_VS1H = (1 << 4), + IN_CD2_VS1H = (1 << 5), +}; + +static const u8 vscd_to_cardtype[] = { + + /* VS1 float, VS2 float */ + [IN_VS1 | IN_VS2] = (CARD_PCCARD | CARD_5V), + + /* VS1 grounded, VS2 float */ + [IN_VS2] = (CARD_PCCARD | CARD_5V | CARD_3V), + + /* VS1 grounded, VS2 grounded */ + [0] = (CARD_PCCARD | CARD_5V | CARD_3V | CARD_XV), + + /* VS1 tied to CD1, VS2 float */ + [IN_VS1 | IN_VS2 | IN_CD1_VS1H] = (CARD_CARDBUS | CARD_3V), + + /* VS1 grounded, VS2 tied to CD2 */ + [IN_VS2 | IN_CD2_VS2H] = (CARD_CARDBUS | CARD_3V | CARD_XV), + + /* VS1 tied to CD2, VS2 grounded */ + [IN_VS1 | IN_CD2_VS1H] = (CARD_CARDBUS | CARD_3V | CARD_XV | CARD_YV), + + /* VS1 float, VS2 grounded */ + [IN_VS1] = (CARD_PCCARD | CARD_XV), + + /* VS1 float, VS2 tied to CD2 */ + [IN_VS1 | IN_VS2 | IN_CD2_VS2H] = (CARD_CARDBUS | CARD_3V), + + /* VS1 float, VS2 tied to CD1 */ + [IN_VS1 | IN_VS2 | IN_CD1_VS2H] = (CARD_CARDBUS | CARD_XV | CARD_YV), + + /* VS1 tied to CD2, VS2 float */ + [IN_VS1 | IN_VS2 | IN_CD2_VS1H] = (CARD_CARDBUS | CARD_YV), + + /* VS2 grounded, VS1 is tied to CD1, CD2 is grounded */ + [IN_VS1 | IN_CD1_VS1H] = 0, /* ignore cardbay */ +}; + +/* + * poll hardware to check card insertion status + */ +static unsigned int __get_socket_status(struct bcm63xx_pcmcia_socket *skt) +{ + unsigned int stat; + u32 val; + + stat = 0; + + /* check CD for card presence */ + val = pcmcia_readl(skt, PCMCIA_C1_REG); + + if (!(val & PCMCIA_C1_CD1_MASK) && !(val & PCMCIA_C1_CD2_MASK)) + stat |= SS_DETECT; + + /* if new insertion, detect cardtype */ + if ((stat & SS_DETECT) && !skt->card_detected) { + unsigned int stat = 0; + + /* float VS1, float VS2 */ + val |= PCMCIA_C1_VS1OE_MASK; + val |= PCMCIA_C1_VS2OE_MASK; + pcmcia_writel(skt, val, PCMCIA_C1_REG); + + /* wait for output to stabilize and read VS[12] */ + udelay(10); + val = pcmcia_readl(skt, PCMCIA_C1_REG); + stat |= (val & PCMCIA_C1_VS1_MASK) ? IN_VS1 : 0; + stat |= (val & PCMCIA_C1_VS2_MASK) ? IN_VS2 : 0; + + /* drive VS1 low, float VS2 */ + val &= ~PCMCIA_C1_VS1OE_MASK; + val |= PCMCIA_C1_VS2OE_MASK; + pcmcia_writel(skt, val, PCMCIA_C1_REG); + + /* wait for output to stabilize and read CD[12] */ + udelay(10); + val = pcmcia_readl(skt, PCMCIA_C1_REG); + stat |= (val & PCMCIA_C1_CD1_MASK) ? IN_CD1_VS2H : 0; + stat |= (val & PCMCIA_C1_CD2_MASK) ? IN_CD2_VS2H : 0; + + /* float VS1, drive VS2 low */ + val |= PCMCIA_C1_VS1OE_MASK; + val &= ~PCMCIA_C1_VS2OE_MASK; + pcmcia_writel(skt, val, PCMCIA_C1_REG); + + /* wait for output to stabilize and read CD[12] */ + udelay(10); + val = pcmcia_readl(skt, PCMCIA_C1_REG); + stat |= (val & PCMCIA_C1_CD1_MASK) ? IN_CD1_VS1H : 0; + stat |= (val & PCMCIA_C1_CD2_MASK) ? IN_CD2_VS1H : 0; + + /* guess cardtype from all this */ + skt->card_type = vscd_to_cardtype[stat]; + if (!skt->card_type) + printk(KERN_ERR PFX "unsupported card type\n"); + + /* drive both VS pin to 0 again */ + val &= ~(PCMCIA_C1_VS1OE_MASK | PCMCIA_C1_VS2OE_MASK); + + /* enable correct logic */ + val &= ~(PCMCIA_C1_EN_PCMCIA_MASK | PCMCIA_C1_EN_CARDBUS_MASK); + if (skt->card_type & CARD_PCCARD) + val |= PCMCIA_C1_EN_PCMCIA_MASK; + else + val |= PCMCIA_C1_EN_CARDBUS_MASK; + + pcmcia_writel(skt, val, PCMCIA_C1_REG); + } + skt->card_detected = (stat & SS_DETECT) ? 1 : 0; + + /* report card type/voltage */ + if (skt->card_type & CARD_CARDBUS) + stat |= SS_CARDBUS; + if (skt->card_type & CARD_3V) + stat |= SS_3VCARD; + if (skt->card_type & CARD_XV) + stat |= SS_XVCARD; + stat |= SS_POWERON; + + if (gpio_get_value(skt->pd->ready_gpio)) + stat |= SS_READY; + + return stat; +} + +/* + * core request to get current socket status + */ +static int bcm63xx_pcmcia_get_status(struct pcmcia_socket *sock, + unsigned int *status) +{ + struct bcm63xx_pcmcia_socket *skt; + + skt = sock->driver_data; + + spin_lock_bh(&skt->lock); + *status = __get_socket_status(skt); + spin_unlock_bh(&skt->lock); + + return 0; +} + +/* + * socket polling timer callback + */ +static void bcm63xx_pcmcia_poll(unsigned long data) +{ + struct bcm63xx_pcmcia_socket *skt; + unsigned int stat, events; + + skt = (struct bcm63xx_pcmcia_socket *)data; + + spin_lock_bh(&skt->lock); + + stat = __get_socket_status(skt); + + /* keep only changed bits, and mask with required one from the + * core */ + events = (stat ^ skt->old_status) & skt->requested_state.csc_mask; + skt->old_status = stat; + spin_unlock_bh(&skt->lock); + + if (events) + pcmcia_parse_events(&skt->socket, events); + + mod_timer(&skt->timer, + jiffies + msecs_to_jiffies(BCM63XX_PCMCIA_POLL_RATE)); +} + +static int bcm63xx_pcmcia_set_io_map(struct pcmcia_socket *sock, + struct pccard_io_map *map) +{ + /* this doesn't seem to be called by pcmcia layer if static + * mapping is used */ + return 0; +} + +static int bcm63xx_pcmcia_set_mem_map(struct pcmcia_socket *sock, + struct pccard_mem_map *map) +{ + struct bcm63xx_pcmcia_socket *skt; + struct resource *res; + + skt = sock->driver_data; + if (map->flags & MAP_ATTRIB) + res = skt->attr_res; + else + res = skt->common_res; + + map->static_start = res->start + map->card_start; + return 0; +} + +static struct pccard_operations bcm63xx_pcmcia_operations = { + .init = bcm63xx_pcmcia_sock_init, + .suspend = bcm63xx_pcmcia_suspend, + .get_status = bcm63xx_pcmcia_get_status, + .set_socket = bcm63xx_pcmcia_set_socket, + .set_io_map = bcm63xx_pcmcia_set_io_map, + .set_mem_map = bcm63xx_pcmcia_set_mem_map, +}; + +/* + * register pcmcia socket to core + */ +static int bcm63xx_drv_pcmcia_probe(struct platform_device *pdev) +{ + struct bcm63xx_pcmcia_socket *skt; + struct pcmcia_socket *sock; + struct resource *res, *irq_res; + unsigned int regmem_size = 0, iomem_size = 0; + u32 val; + int ret; + + skt = kzalloc(sizeof(*skt), GFP_KERNEL); + if (!skt) + return -ENOMEM; + spin_lock_init(&skt->lock); + sock = &skt->socket; + sock->driver_data = skt; + + /* make sure we have all resources we need */ + skt->common_res = platform_get_resource(pdev, IORESOURCE_MEM, 1); + skt->attr_res = platform_get_resource(pdev, IORESOURCE_MEM, 2); + irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); + skt->pd = pdev->dev.platform_data; + if (!skt->common_res || !skt->attr_res || !irq_res || !skt->pd) { + ret = -EINVAL; + goto err; + } + + /* remap pcmcia registers */ + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + regmem_size = res->end - res->start + 1; + if (!request_mem_region(res->start, regmem_size, "bcm63xx_pcmcia")) { + ret = -EINVAL; + goto err; + } + skt->reg_res = res; + + skt->base = ioremap(res->start, regmem_size); + if (!skt->base) { + ret = -ENOMEM; + goto err; + } + + /* remap io registers */ + res = platform_get_resource(pdev, IORESOURCE_MEM, 3); + iomem_size = res->end - res->start + 1; + skt->io_base = ioremap(res->start, iomem_size); + if (!skt->io_base) { + ret = -ENOMEM; + goto err; + } + + /* resources are static */ + sock->resource_ops = &pccard_static_ops; + sock->ops = &bcm63xx_pcmcia_operations; + sock->owner = THIS_MODULE; + sock->dev.parent = &pdev->dev; + sock->features = SS_CAP_STATIC_MAP | SS_CAP_PCCARD; + sock->io_offset = (unsigned long)skt->io_base; + sock->pci_irq = irq_res->start; + +#ifdef CONFIG_CARDBUS + sock->cb_dev = bcm63xx_cb_dev; + if (bcm63xx_cb_dev) + sock->features |= SS_CAP_CARDBUS; +#endif + + /* assume common & attribute memory have the same size */ + sock->map_size = skt->common_res->end - skt->common_res->start + 1; + + /* initialize polling timer */ + setup_timer(&skt->timer, bcm63xx_pcmcia_poll, (unsigned long)skt); + + /* initialize pcmcia control register, drive VS[12] to 0, + * leave CB IDSEL to the old value since it is set by the PCI + * layer */ + val = pcmcia_readl(skt, PCMCIA_C1_REG); + val &= PCMCIA_C1_CBIDSEL_MASK; + val |= PCMCIA_C1_EN_PCMCIA_GPIO_MASK; + pcmcia_writel(skt, val, PCMCIA_C1_REG); + + /* FIXME set correct pcmcia timings */ + val = PCMCIA_C2_DATA16_MASK; + val |= 10 << PCMCIA_C2_RWCOUNT_SHIFT; + val |= 6 << PCMCIA_C2_INACTIVE_SHIFT; + val |= 3 << PCMCIA_C2_SETUP_SHIFT; + val |= 3 << PCMCIA_C2_HOLD_SHIFT; + pcmcia_writel(skt, val, PCMCIA_C2_REG); + + ret = pcmcia_register_socket(sock); + if (ret) + goto err; + + /* start polling socket */ + mod_timer(&skt->timer, + jiffies + msecs_to_jiffies(BCM63XX_PCMCIA_POLL_RATE)); + + platform_set_drvdata(pdev, skt); + return 0; + +err: + if (skt->io_base) + iounmap(skt->io_base); + if (skt->base) + iounmap(skt->base); + if (skt->reg_res) + release_mem_region(skt->reg_res->start, regmem_size); + kfree(skt); + return ret; +} + +static int bcm63xx_drv_pcmcia_remove(struct platform_device *pdev) +{ + struct bcm63xx_pcmcia_socket *skt; + struct resource *res; + + skt = platform_get_drvdata(pdev); + del_timer_sync(&skt->timer); + iounmap(skt->base); + iounmap(skt->io_base); + res = skt->reg_res; + release_mem_region(res->start, res->end - res->start + 1); + kfree(skt); + return 0; +} + +struct platform_driver bcm63xx_pcmcia_driver = { + .probe = bcm63xx_drv_pcmcia_probe, + .remove = __devexit_p(bcm63xx_drv_pcmcia_remove), + .driver = { + .name = "bcm63xx_pcmcia", + .owner = THIS_MODULE, + }, +}; + +#ifdef CONFIG_CARDBUS +static int __devinit bcm63xx_cb_probe(struct pci_dev *dev, + const struct pci_device_id *id) +{ + /* keep pci device */ + bcm63xx_cb_dev = dev; + return platform_driver_register(&bcm63xx_pcmcia_driver); +} + +static void __devexit bcm63xx_cb_exit(struct pci_dev *dev) +{ + platform_driver_unregister(&bcm63xx_pcmcia_driver); + bcm63xx_cb_dev = NULL; +} + +static struct pci_device_id bcm63xx_cb_table[] = { + { + .vendor = PCI_VENDOR_ID_BROADCOM, + .device = PCI_ANY_ID, + .subvendor = PCI_VENDOR_ID_BROADCOM, + .subdevice = PCI_ANY_ID, + .class = PCI_CLASS_BRIDGE_CARDBUS << 8, + .class_mask = ~0, + }, +}; + +MODULE_DEVICE_TABLE(pci, bcm63xx_cb_table); + +static struct pci_driver bcm63xx_cardbus_driver = { + .name = "yenta_cardbus", + .id_table = bcm63xx_cb_table, + .probe = bcm63xx_cb_probe, + .remove = __devexit_p(bcm63xx_cb_exit), +}; +#endif + +/* + * if cardbus support is enabled, register our platform device after + * our fake cardbus bridge has been registered + */ +static int __init bcm63xx_pcmcia_init(void) +{ +#ifdef CONFIG_CARDBUS + return pci_register_driver(&bcm63xx_cardbus_driver); +#else + return platform_driver_register(&bcm63xx_pcmcia_driver); +#endif +} + +static void __exit bcm63xx_pcmcia_exit(void) +{ +#ifdef CONFIG_CARDBUS + return pci_unregister_driver(&bcm63xx_cardbus_driver); +#else + platform_driver_unregister(&bcm63xx_pcmcia_driver); +#endif +} + +module_init(bcm63xx_pcmcia_init); +module_exit(bcm63xx_pcmcia_exit); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Maxime Bizon "); +MODULE_DESCRIPTION("Linux PCMCIA Card Services: bcm63xx Socket Controller"); --- /dev/null +++ b/drivers/pcmcia/bcm63xx_pcmcia.h @@ -0,0 +1,65 @@ +#ifndef BCM63XX_PCMCIA_H_ +#define BCM63XX_PCMCIA_H_ + +#include +#include +#include +#include + +/* socket polling rate in ms */ +#define BCM63XX_PCMCIA_POLL_RATE 500 + +enum { + CARD_CARDBUS = (1 << 0), + + CARD_PCCARD = (1 << 1), + + CARD_5V = (1 << 2), + + CARD_3V = (1 << 3), + + CARD_XV = (1 << 4), + + CARD_YV = (1 << 5), +}; + +struct bcm63xx_pcmcia_socket { + struct pcmcia_socket socket; + + /* platform specific data */ + struct bcm63xx_pcmcia_platform_data *pd; + + /* all regs access are protected by this spinlock */ + spinlock_t lock; + + /* pcmcia registers resource */ + struct resource *reg_res; + + /* base remapped address of registers */ + void __iomem *base; + + /* whether a card is detected at the moment */ + int card_detected; + + /* type of detected card (mask of above enum) */ + u8 card_type; + + /* keep last socket status to implement event reporting */ + unsigned int old_status; + + /* backup of requested socket state */ + socket_state_t requested_state; + + /* timer used for socket status polling */ + struct timer_list timer; + + /* attribute/common memory resources */ + struct resource *attr_res; + struct resource *common_res; + struct resource *io_res; + + /* base address of io memory */ + void __iomem *io_base; +}; + +#endif /* BCM63XX_PCMCIA_H_ */ From ralf@linux-mips.org Wed Jul 1 19:09:24 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 01 Jul 2009 19:09:27 +0200 (CEST) Received: (from localhost user: 'ralf' uid#500 fake: STDIN (ralf@eddie.linux-mips.org)) by ftp.linux-mips.org id S1491871AbZGARHK for <"|/home/ecartis/ecartis -s linux-mips">; Wed, 1 Jul 2009 19:07:10 +0200 Message-Id: <20090701120939.846432854@linux-mips.org> User-Agent: quilt/0.47-1 Date: Wed, 01 Jul 2009 12:29:33 +0100 From: Ralf Baechle To: linux-mips@linux-mips.org, Greg Kroah-Hartman , linux-usb@vger.kernel.org Cc: Maxime Bizon , Florian Fainelli Subject: [patch 07/12] MIPS: BCM63XX: Add USB OHCI support. References: <20090701112926.825088732@linux-mips.org> Content-Disposition: inline; filename=0007.patch Content-Length: 8747 Lines: 311 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-archive-position: 23573 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips From: Maxime Bizon Signed-off-by: Maxime Bizon Signed-off-by: Ralf Baechle arch/mips/bcm63xx/Kconfig | 6 arch/mips/bcm63xx/Makefile | 1 arch/mips/bcm63xx/dev-usb-ohci.c | 50 ++++ arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_usb_ohci.h | 6 drivers/usb/host/ohci-bcm63xx.c | 164 ++++++++++++++ drivers/usb/host/ohci-hcd.c | 5 drivers/usb/host/ohci.h | 7 7 files changed, 238 insertions(+), 1 deletion(-) create mode 100644 arch/mips/bcm63xx/dev-usb-ohci.c create mode 100644 arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_usb_ohci.h create mode 100644 drivers/usb/host/ohci-bcm63xx.c --- a/arch/mips/bcm63xx/Kconfig +++ b/arch/mips/bcm63xx/Kconfig @@ -4,8 +4,14 @@ menu "CPU support" config BCM63XX_CPU_6348 bool "support 6348 CPU" select HW_HAS_PCI + select USB_ARCH_HAS_OHCI + select USB_OHCI_BIG_ENDIAN_DESC + select USB_OHCI_BIG_ENDIAN_MMIO config BCM63XX_CPU_6358 bool "support 6358 CPU" select HW_HAS_PCI + select USB_ARCH_HAS_OHCI + select USB_OHCI_BIG_ENDIAN_DESC + select USB_OHCI_BIG_ENDIAN_MMIO endmenu --- a/arch/mips/bcm63xx/Makefile +++ b/arch/mips/bcm63xx/Makefile @@ -1,6 +1,7 @@ obj-y += clk.o cpu.o cs.o gpio.o irq.o prom.o setup.o timer.o obj-y += dev-uart.o obj-y += dev-pcmcia.o +obj-y += dev-usb-ohci.o obj-$(CONFIG_EARLY_PRINTK) += early_printk.o EXTRA_CFLAGS += -Werror --- /dev/null +++ b/arch/mips/bcm63xx/dev-usb-ohci.c @@ -0,0 +1,50 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2008 Maxime Bizon + */ + +#include +#include +#include +#include +#include + +static struct resource ohci_resources[] = { + { + .start = -1, /* filled at runtime */ + .end = -1, /* filled at runtime */ + .flags = IORESOURCE_MEM, + }, + { + .start = -1, /* filled at runtime */ + .flags = IORESOURCE_IRQ, + }, +}; + +static u64 ohci_dmamask = ~(u32)0; + +static struct platform_device bcm63xx_ohci_device = { + .name = "bcm63xx_ohci", + .id = 0, + .num_resources = ARRAY_SIZE(ohci_resources), + .resource = ohci_resources, + .dev = { + .dma_mask = &ohci_dmamask, + .coherent_dma_mask = 0xffffffff, + }, +}; + +int __init bcm63xx_ohci_register(void) +{ + if (!BCMCPU_IS_6348() && !BCMCPU_IS_6358()) + return 0; + + ohci_resources[0].start = bcm63xx_regset_address(RSET_OHCI0); + ohci_resources[0].end = ohci_resources[0].start; + ohci_resources[0].end += RSET_OHCI_SIZE - 1; + ohci_resources[1].start = bcm63xx_get_irq_number(IRQ_OHCI0); + return platform_device_register(&bcm63xx_ohci_device); +} --- /dev/null +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_usb_ohci.h @@ -0,0 +1,6 @@ +#ifndef BCM63XX_DEV_USB_OHCI_H_ +#define BCM63XX_DEV_USB_OHCI_H_ + +int bcm63xx_ohci_register(void); + +#endif /* BCM63XX_DEV_USB_OHCI_H_ */ --- /dev/null +++ b/drivers/usb/host/ohci-bcm63xx.c @@ -0,0 +1,164 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2008 Maxime Bizon + */ + +#include +#include +#include +#include +#include +#include + +static struct clk *usb_host_clock; + +static int __devinit ohci_bcm63xx_start(struct usb_hcd *hcd) +{ + struct ohci_hcd *ohci = hcd_to_ohci(hcd); + int ret; + + ohci->num_ports = 1; + + ret = ohci_init(ohci); + if (ret < 0) + return ret; + + /* FIXME: autodetected port 2 is shared with USB slave */ + + ret = ohci_run(ohci); + if (ret < 0) { + err("can't start %s", hcd->self.bus_name); + ohci_stop(hcd); + return ret; + } + return 0; +} + +static const struct hc_driver ohci_bcm63xx_hc_driver = { + .description = hcd_name, + .product_desc = "BCM63XX integrated OHCI controller", + .hcd_priv_size = sizeof(struct ohci_hcd), + + .irq = ohci_irq, + .flags = HCD_USB11 | HCD_MEMORY, + .start = ohci_bcm63xx_start, + .stop = ohci_stop, + .shutdown = ohci_shutdown, + .urb_enqueue = ohci_urb_enqueue, + .urb_dequeue = ohci_urb_dequeue, + .endpoint_disable = ohci_endpoint_disable, + .get_frame_number = ohci_get_frame, + .hub_status_data = ohci_hub_status_data, + .hub_control = ohci_hub_control, + .start_port_reset = ohci_start_port_reset, +}; + +static int __devinit ohci_hcd_bcm63xx_drv_probe(struct platform_device *pdev) +{ + struct resource *res_mem; + struct usb_hcd *hcd; + struct ohci_hcd *ohci; + u32 reg; + int ret, irq; + + res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); + irq = platform_get_irq(pdev, 0); + if (!res_mem || irq < 0) + return -ENODEV; + + if (BCMCPU_IS_6348()) { + struct clk *clk; + /* enable USB host clock */ + clk = clk_get(&pdev->dev, "usbh"); + if (IS_ERR(clk)) + return -ENODEV; + + clk_enable(clk); + usb_host_clock = clk; + bcm_rset_writel(RSET_OHCI_PRIV, 0, OHCI_PRIV_REG); + + } else if (BCMCPU_IS_6358()) { + reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SWAP_REG); + reg &= ~USBH_PRIV_SWAP_OHCI_ENDN_MASK; + reg |= USBH_PRIV_SWAP_OHCI_DATA_MASK; + bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SWAP_REG); + /* + * The magic value comes for the original vendor BSP + * and is needed for USB to work. Datasheet does not + * help, so the magic value is used as-is. + */ + bcm_rset_writel(RSET_USBH_PRIV, 0x1c0020, USBH_PRIV_TEST_REG); + } else + return 0; + + hcd = usb_create_hcd(&ohci_bcm63xx_hc_driver, &pdev->dev, "bcm63xx"); + if (!hcd) + return -ENOMEM; + hcd->rsrc_start = res_mem->start; + hcd->rsrc_len = res_mem->end - res_mem->start + 1; + + if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, hcd_name)) { + pr_debug("request_mem_region failed\n"); + ret = -EBUSY; + goto out; + } + + hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len); + if (!hcd->regs) { + pr_debug("ioremap failed\n"); + ret = -EIO; + goto out1; + } + + ohci = hcd_to_ohci(hcd); + ohci->flags |= OHCI_QUIRK_BE_MMIO | OHCI_QUIRK_BE_DESC | + OHCI_QUIRK_FRAME_NO; + ohci_hcd_init(ohci); + + ret = usb_add_hcd(hcd, irq, IRQF_DISABLED); + if (ret) + goto out2; + + platform_set_drvdata(pdev, hcd); + return 0; + +out2: + iounmap(hcd->regs); +out1: + release_mem_region(hcd->rsrc_start, hcd->rsrc_len); +out: + usb_put_hcd(hcd); + return ret; +} + +static int __devexit ohci_hcd_bcm63xx_drv_remove(struct platform_device *pdev) +{ + struct usb_hcd *hcd; + + hcd = platform_get_drvdata(pdev); + usb_remove_hcd(hcd); + iounmap(hcd->regs); + usb_put_hcd(hcd); + release_mem_region(hcd->rsrc_start, hcd->rsrc_len); + if (usb_host_clock) { + clk_disable(usb_host_clock); + clk_put(usb_host_clock); + } + platform_set_drvdata(pdev, NULL); + return 0; +} + +static struct platform_driver ohci_hcd_bcm63xx_driver = { + .probe = ohci_hcd_bcm63xx_drv_probe, + .remove = __devexit_p(ohci_hcd_bcm63xx_drv_remove), + .shutdown = usb_hcd_platform_shutdown, + .driver = { + .name = "bcm63xx_ohci", + .owner = THIS_MODULE, + }, +}; + +MODULE_ALIAS("platform:bcm63xx_ohci"); --- a/drivers/usb/host/ohci-hcd.c +++ b/drivers/usb/host/ohci-hcd.c @@ -1047,6 +1047,11 @@ MODULE_LICENSE ("GPL"); #define PLATFORM_DRIVER usb_hcd_pnx4008_driver #endif +#ifdef CONFIG_BCM63XX +#include "ohci-bcm63xx.c" +#define PLATFORM_DRIVER ohci_hcd_bcm63xx_driver +#endif + #if defined(CONFIG_CPU_SUBTYPE_SH7720) || \ defined(CONFIG_CPU_SUBTYPE_SH7721) || \ defined(CONFIG_CPU_SUBTYPE_SH7763) || \ --- a/drivers/usb/host/ohci.h +++ b/drivers/usb/host/ohci.h @@ -536,6 +536,11 @@ static inline struct usb_hcd *ohci_to_hc #define big_endian_mmio(ohci) 0 /* only little endian */ #endif +#if defined(CONFIG_MIPS) && defined(CONFIG_BCM63XX) +#define readl_be(addr) __raw_readl((__force unsigned *)addr) +#define writel_be(val, addr) __raw_writel(val, (__force unsigned *)addr) +#endif + /* * Big-endian read/write functions are arch-specific. * Other arches can be added if/when they're needed. @@ -646,7 +651,7 @@ static inline u32 hc32_to_cpup (const st * some big-endian SOC implementations. Same thing happens with PSW access. */ -#ifdef CONFIG_PPC_MPC52xx +#if defined(CONFIG_PPC_MPC52xx) || defined(CONFIG_BCM63XX) #define big_endian_frame_no_quirk(ohci) (ohci->flags & OHCI_QUIRK_FRAME_NO) #else #define big_endian_frame_no_quirk(ohci) 0 From ralf@linux-mips.org Wed Jul 1 19:09:44 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 01 Jul 2009 19:09:48 +0200 (CEST) Received: (from localhost user: 'ralf' uid#500 fake: STDIN (ralf@eddie.linux-mips.org)) by ftp.linux-mips.org id S1491872AbZGARHK for <"|/home/ecartis/ecartis -s linux-mips">; Wed, 1 Jul 2009 19:07:10 +0200 Message-Id: <20090701120939.926196204@linux-mips.org> User-Agent: quilt/0.47-1 Date: Wed, 01 Jul 2009 12:29:34 +0100 From: Ralf Baechle To: linux-mips@linux-mips.org, Greg Kroah-Hartman , linux-usb@vger.kernel.org Cc: Maxime Bizon , Florian Fainelli Subject: [patch 08/12] MIPS: BCM63XX: Add USB EHCI support. References: <20090701112926.825088732@linux-mips.org> Content-Disposition: inline; filename=0008.patch Content-Length: 7952 Lines: 285 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-archive-position: 23574 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips From: Maxime Bizon Signed-off-by: Maxime Bizon Signed-off-by: Ralf Baechle arch/mips/bcm63xx/Kconfig | 2 arch/mips/bcm63xx/Makefile | 1 arch/mips/bcm63xx/dev-usb-ehci.c | 50 ++++ arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_usb_ehci.h | 6 drivers/usb/host/ehci-bcm63xx.c | 155 ++++++++++++++ drivers/usb/host/ehci-hcd.c | 5 drivers/usb/host/ehci.h | 5 7 files changed, 224 insertions(+) create mode 100644 arch/mips/bcm63xx/dev-usb-ehci.c create mode 100644 arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_usb_ehci.h create mode 100644 drivers/usb/host/ehci-bcm63xx.c --- a/arch/mips/bcm63xx/Kconfig +++ b/arch/mips/bcm63xx/Kconfig @@ -14,4 +14,6 @@ config BCM63XX_CPU_6358 select USB_ARCH_HAS_OHCI select USB_OHCI_BIG_ENDIAN_DESC select USB_OHCI_BIG_ENDIAN_MMIO + select USB_ARCH_HAS_EHCI + select USB_EHCI_BIG_ENDIAN_MMIO endmenu --- a/arch/mips/bcm63xx/Makefile +++ b/arch/mips/bcm63xx/Makefile @@ -2,6 +2,7 @@ obj-y += clk.o cpu.o cs.o gpio.o irq.o obj-y += dev-uart.o obj-y += dev-pcmcia.o obj-y += dev-usb-ohci.o +obj-y += dev-usb-ehci.o obj-$(CONFIG_EARLY_PRINTK) += early_printk.o EXTRA_CFLAGS += -Werror --- /dev/null +++ b/arch/mips/bcm63xx/dev-usb-ehci.c @@ -0,0 +1,50 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2008 Maxime Bizon + */ + +#include +#include +#include +#include +#include + +static struct resource ehci_resources[] = { + { + .start = -1, /* filled at runtime */ + .end = -1, /* filled at runtime */ + .flags = IORESOURCE_MEM, + }, + { + .start = -1, /* filled at runtime */ + .flags = IORESOURCE_IRQ, + }, +}; + +static u64 ehci_dmamask = ~(u32)0; + +static struct platform_device bcm63xx_ehci_device = { + .name = "bcm63xx_ehci", + .id = 0, + .num_resources = ARRAY_SIZE(ehci_resources), + .resource = ehci_resources, + .dev = { + .dma_mask = &ehci_dmamask, + .coherent_dma_mask = 0xffffffff, + }, +}; + +int __init bcm63xx_ehci_register(void) +{ + if (!BCMCPU_IS_6358()) + return 0; + + ehci_resources[0].start = bcm63xx_regset_address(RSET_EHCI0); + ehci_resources[0].end = ehci_resources[0].start; + ehci_resources[0].end += RSET_EHCI_SIZE - 1; + ehci_resources[1].start = bcm63xx_get_irq_number(IRQ_EHCI0); + return platform_device_register(&bcm63xx_ehci_device); +} --- /dev/null +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_usb_ehci.h @@ -0,0 +1,6 @@ +#ifndef BCM63XX_DEV_USB_EHCI_H_ +#define BCM63XX_DEV_USB_EHCI_H_ + +int bcm63xx_ehci_register(void); + +#endif /* BCM63XX_DEV_USB_EHCI_H_ */ --- /dev/null +++ b/drivers/usb/host/ehci-bcm63xx.c @@ -0,0 +1,155 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2008 Maxime Bizon + */ + +#include +#include +#include +#include +#include + +static int ehci_bcm63xx_setup(struct usb_hcd *hcd) +{ + struct ehci_hcd *ehci = hcd_to_ehci(hcd); + int retval; + + retval = ehci_halt(ehci); + if (retval) + return retval; + + retval = ehci_init(hcd); + if (retval) + return retval; + + hcd->has_tt = 1; + ehci_reset(ehci); + ehci_port_power(ehci, 0); + + return retval; +} + + +static const struct hc_driver ehci_bcm63xx_hc_driver = { + .description = hcd_name, + .product_desc = "BCM63XX integrated EHCI controller", + .hcd_priv_size = sizeof(struct ehci_hcd), + + .irq = ehci_irq, + .flags = HCD_MEMORY | HCD_USB2, + + .reset = ehci_bcm63xx_setup, + .start = ehci_run, + .stop = ehci_stop, + .shutdown = ehci_shutdown, + + .urb_enqueue = ehci_urb_enqueue, + .urb_dequeue = ehci_urb_dequeue, + .endpoint_disable = ehci_endpoint_disable, + + .get_frame_number = ehci_get_frame, + + .hub_status_data = ehci_hub_status_data, + .hub_control = ehci_hub_control, + .bus_suspend = ehci_bus_suspend, + .bus_resume = ehci_bus_resume, + .relinquish_port = ehci_relinquish_port, + .port_handed_over = ehci_port_handed_over, +}; + +static int __devinit ehci_hcd_bcm63xx_drv_probe(struct platform_device *pdev) +{ + struct resource *res_mem; + struct usb_hcd *hcd; + struct ehci_hcd *ehci; + u32 reg; + int ret, irq; + + res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); + irq = platform_get_irq(pdev, 0);; + if (!res_mem || irq < 0) + return -ENODEV; + + reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SWAP_REG); + reg &= ~USBH_PRIV_SWAP_EHCI_DATA_MASK; + reg |= USBH_PRIV_SWAP_EHCI_ENDN_MASK; + bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SWAP_REG); + + /* + * The magic value comes for the original vendor BSP and is + * needed for USB to work. Datasheet does not help, so the + * magic value is used as-is. + */ + bcm_rset_writel(RSET_USBH_PRIV, 0x1c0020, USBH_PRIV_TEST_REG); + + hcd = usb_create_hcd(&ehci_bcm63xx_hc_driver, &pdev->dev, "bcm63xx"); + if (!hcd) + return -ENOMEM; + hcd->rsrc_start = res_mem->start; + hcd->rsrc_len = res_mem->end - res_mem->start + 1; + + if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, hcd_name)) { + pr_debug("request_mem_region failed\n"); + ret = -EBUSY; + goto out; + } + + hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len); + if (!hcd->regs) { + pr_debug("ioremap failed\n"); + ret = -EIO; + goto out1; + } + + ehci = hcd_to_ehci(hcd); + ehci->big_endian_mmio = 1; + ehci->big_endian_desc = 0; + ehci->caps = hcd->regs; + ehci->regs = hcd->regs + + HC_LENGTH(ehci_readl(ehci, &ehci->caps->hc_capbase)); + ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params); + ehci->sbrn = 0x20; + + ret = usb_add_hcd(hcd, irq, IRQF_DISABLED); + if (ret) + goto out2; + + platform_set_drvdata(pdev, hcd); + return 0; + +out2: + iounmap(hcd->regs); +out1: + release_mem_region(hcd->rsrc_start, hcd->rsrc_len); +out: + usb_put_hcd(hcd); + return ret; +} + +static int __devexit ehci_hcd_bcm63xx_drv_remove(struct platform_device *pdev) +{ + struct usb_hcd *hcd; + + hcd = platform_get_drvdata(pdev); + usb_remove_hcd(hcd); + iounmap(hcd->regs); + usb_put_hcd(hcd); + release_mem_region(hcd->rsrc_start, hcd->rsrc_len); + platform_set_drvdata(pdev, NULL); + return 0; +} + +static struct platform_driver ehci_hcd_bcm63xx_driver = { + .probe = ehci_hcd_bcm63xx_drv_probe, + .remove = __devexit_p(ehci_hcd_bcm63xx_drv_remove), + .shutdown = usb_hcd_platform_shutdown, + .driver = { + .name = "bcm63xx_ehci", + .owner = THIS_MODULE, + }, +}; + +MODULE_ALIAS("platform:bcm63xx_ehci"); --- a/drivers/usb/host/ehci-hcd.c +++ b/drivers/usb/host/ehci-hcd.c @@ -1117,6 +1117,11 @@ MODULE_LICENSE ("GPL"); #define PLATFORM_DRIVER ixp4xx_ehci_driver #endif +#ifdef CONFIG_BCM63XX +#include "ehci-bcm63xx.c" +#define PLATFORM_DRIVER ehci_hcd_bcm63xx_driver +#endif + #if !defined(PCI_DRIVER) && !defined(PLATFORM_DRIVER) && \ !defined(PS3_SYSTEM_BUS_DRIVER) && !defined(OF_PLATFORM_DRIVER) #error "missing bus glue for ehci-hcd" --- a/drivers/usb/host/ehci.h +++ b/drivers/usb/host/ehci.h @@ -598,6 +598,11 @@ ehci_port_speed(struct ehci_hcd *ehci, u #define writel_be(val, addr) __raw_writel(val, (__force unsigned *)addr) #endif +#if defined(CONFIG_MIPS) && defined(CONFIG_BCM63XX) +#define readl_be(addr) __raw_readl((__force unsigned *)addr) +#define writel_be(val, addr) __raw_writel(val, (__force unsigned *)addr) +#endif + static inline unsigned int ehci_readl(const struct ehci_hcd *ehci, __u32 __iomem * regs) { From ralf@linux-mips.org Wed Jul 1 19:10:05 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 01 Jul 2009 19:10:10 +0200 (CEST) Received: (from localhost user: 'ralf' uid#500 fake: STDIN (ralf@eddie.linux-mips.org)) by ftp.linux-mips.org id S1491876AbZGARHL for <"|/home/ecartis/ecartis -s linux-mips">; Wed, 1 Jul 2009 19:07:11 +0200 Message-Id: <20090701120940.012332221@linux-mips.org> User-Agent: quilt/0.47-1 Date: Wed, 01 Jul 2009 12:29:35 +0100 From: Ralf Baechle To: linux-mips@linux-mips.org, netdev@vger.kernel.org Cc: Maxime Bizon , Florian Fainelli Subject: [patch 09/12] MIPS: BCM63XX: Add integrated ethernet mac support. References: <20090701112926.825088732@linux-mips.org> Content-Disposition: inline; filename=0009.patch Content-Length: 65831 Lines: 2544 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-archive-position: 23575 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips From: Maxime Bizon Signed-off-by: Maxime Bizon Signed-off-by: Florian Fainelli Signed-off-by: Ralf Baechle arch/mips/bcm63xx/Makefile | 1 arch/mips/bcm63xx/dev-enet.c | 156 + arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_enet.h | 45 drivers/net/Kconfig | 9 drivers/net/Makefile | 1 drivers/net/bcm63xx_enet.c | 1970 ++++++++++++++++++ drivers/net/bcm63xx_enet.h | 303 ++ 7 files changed, 2485 insertions(+) create mode 100644 arch/mips/bcm63xx/dev-enet.c create mode 100644 arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_enet.h create mode 100644 drivers/net/bcm63xx_enet.c create mode 100644 drivers/net/bcm63xx_enet.h --- a/arch/mips/bcm63xx/Makefile +++ b/arch/mips/bcm63xx/Makefile @@ -3,6 +3,7 @@ obj-y += dev-uart.o obj-y += dev-pcmcia.o obj-y += dev-usb-ohci.o obj-y += dev-usb-ehci.o +obj-y += dev-enet.o obj-$(CONFIG_EARLY_PRINTK) += early_printk.o EXTRA_CFLAGS += -Werror --- /dev/null +++ b/arch/mips/bcm63xx/dev-enet.c @@ -0,0 +1,156 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2008 Maxime Bizon + */ + +#include +#include +#include +#include +#include +#include + +static struct resource shared_res[] = { + { + .start = -1, /* filled at runtime */ + .end = -1, /* filled at runtime */ + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device bcm63xx_enet_shared_device = { + .name = "bcm63xx_enet_shared", + .id = 0, + .num_resources = ARRAY_SIZE(shared_res), + .resource = shared_res, +}; + +static int shared_device_registered; + +static struct resource enet0_res[] = { + { + .start = -1, /* filled at runtime */ + .end = -1, /* filled at runtime */ + .flags = IORESOURCE_MEM, + }, + { + .start = -1, /* filled at runtime */ + .flags = IORESOURCE_IRQ, + }, + { + .start = -1, /* filled at runtime */ + .flags = IORESOURCE_IRQ, + }, + { + .start = -1, /* filled at runtime */ + .flags = IORESOURCE_IRQ, + }, +}; + +static struct bcm63xx_enet_platform_data enet0_pd; + +static struct platform_device bcm63xx_enet0_device = { + .name = "bcm63xx_enet", + .id = 0, + .num_resources = ARRAY_SIZE(enet0_res), + .resource = enet0_res, + .dev = { + .platform_data = &enet0_pd, + }, +}; + +static struct resource enet1_res[] = { + { + .start = -1, /* filled at runtime */ + .end = -1, /* filled at runtime */ + .flags = IORESOURCE_MEM, + }, + { + .start = -1, /* filled at runtime */ + .flags = IORESOURCE_IRQ, + }, + { + .start = -1, /* filled at runtime */ + .flags = IORESOURCE_IRQ, + }, + { + .start = -1, /* filled at runtime */ + .flags = IORESOURCE_IRQ, + }, +}; + +static struct bcm63xx_enet_platform_data enet1_pd; + +static struct platform_device bcm63xx_enet1_device = { + .name = "bcm63xx_enet", + .id = 1, + .num_resources = ARRAY_SIZE(enet1_res), + .resource = enet1_res, + .dev = { + .platform_data = &enet1_pd, + }, +}; + +int __init bcm63xx_enet_register(int unit, + const struct bcm63xx_enet_platform_data *pd) +{ + struct platform_device *pdev; + struct bcm63xx_enet_platform_data *dpd; + int ret; + + if (unit > 1) + return -ENODEV; + + if (!shared_device_registered) { + shared_res[0].start = bcm63xx_regset_address(RSET_ENETDMA); + shared_res[0].end = shared_res[0].start; + shared_res[0].end += RSET_ENETDMA_SIZE - 1; + + ret = platform_device_register(&bcm63xx_enet_shared_device); + if (ret) + return ret; + shared_device_registered = 1; + } + + if (unit == 0) { + enet0_res[0].start = bcm63xx_regset_address(RSET_ENET0); + enet0_res[0].end = enet0_res[0].start; + enet0_res[0].end += RSET_ENET_SIZE - 1; + enet0_res[1].start = bcm63xx_get_irq_number(IRQ_ENET0); + enet0_res[2].start = bcm63xx_get_irq_number(IRQ_ENET0_RXDMA); + enet0_res[3].start = bcm63xx_get_irq_number(IRQ_ENET0_TXDMA); + pdev = &bcm63xx_enet0_device; + } else { + enet1_res[0].start = bcm63xx_regset_address(RSET_ENET1); + enet1_res[0].end = enet1_res[0].start; + enet1_res[0].end += RSET_ENET_SIZE - 1; + enet1_res[1].start = bcm63xx_get_irq_number(IRQ_ENET1); + enet1_res[2].start = bcm63xx_get_irq_number(IRQ_ENET1_RXDMA); + enet1_res[3].start = bcm63xx_get_irq_number(IRQ_ENET1_TXDMA); + pdev = &bcm63xx_enet1_device; + } + + /* copy given platform data */ + dpd = pdev->dev.platform_data; + memcpy(dpd, pd, sizeof(*pd)); + + /* adjust them in case internal phy is used */ + if (dpd->use_internal_phy) { + + /* internal phy only exists for enet0 */ + if (unit == 1) + return -ENODEV; + + dpd->phy_id = 1; + dpd->has_phy_interrupt = 1; + dpd->phy_interrupt = bcm63xx_get_irq_number(IRQ_ENET_PHY); + } + + ret = platform_device_register(pdev); + if (ret) + return ret; + return 0; +} --- /dev/null +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_enet.h @@ -0,0 +1,45 @@ +#ifndef BCM63XX_DEV_ENET_H_ +#define BCM63XX_DEV_ENET_H_ + +#include +#include + +/* + * on board ethernet platform data + */ +struct bcm63xx_enet_platform_data { + char mac_addr[ETH_ALEN]; + + int has_phy; + + /* if has_phy, then set use_internal_phy */ + int use_internal_phy; + + /* or fill phy info to use an external one */ + int phy_id; + int has_phy_interrupt; + int phy_interrupt; + + /* if has_phy, use autonegociated pause parameters or force + * them */ + int pause_auto; + int pause_rx; + int pause_tx; + + /* if !has_phy, set desired forced speed/duplex */ + int force_speed_100; + int force_duplex_full; + + /* if !has_phy, set callback to perform mii device + * init/remove */ + int (*mii_config)(struct net_device *dev, int probe, + int (*mii_read)(struct net_device *dev, + int phy_id, int reg), + void (*mii_write)(struct net_device *dev, + int phy_id, int reg, int val)); +}; + +int __init bcm63xx_enet_register(int unit, + const struct bcm63xx_enet_platform_data *pd); + +#endif /* ! BCM63XX_DEV_ENET_H_ */ --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -1919,6 +1919,15 @@ config ATL2 To compile this driver as a module, choose M here. The module will be called atl2. +config BCM63XX_ENET + tristate "Broadcom 63xx internal mac support" + depends on BCM63XX + select MII + select PHYLIB + help + This driver supports the ethernet MACs in the Broadcom 63xx + MIPS chipset family (BCM63XX). + source "drivers/net/fs_enet/Kconfig" endif # NET_ETHERNET --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -136,6 +136,7 @@ obj-$(CONFIG_B44) += b44.o obj-$(CONFIG_FORCEDETH) += forcedeth.o obj-$(CONFIG_NE_H8300) += ne-h8300.o 8390.o obj-$(CONFIG_AX88796) += ax88796.o +obj-$(CONFIG_BCM63XX_ENET) += bcm63xx_enet.o obj-$(CONFIG_TSI108_ETH) += tsi108_eth.o obj-$(CONFIG_MV643XX_ETH) += mv643xx_eth.o --- /dev/null +++ b/drivers/net/bcm63xx_enet.c @@ -0,0 +1,1970 @@ +/* + * Driver for BCM963xx builtin Ethernet mac + * + * Copyright (C) 2008 Maxime Bizon + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include "bcm63xx_enet.h" + +static char bcm_enet_driver_name[] = "bcm63xx_enet"; +static char bcm_enet_driver_version[] = "1.0"; + +static int copybreak __read_mostly = 128; +module_param(copybreak, int, 0); +MODULE_PARM_DESC(copybreak, "Receive copy threshold"); + +/* io memory shared between all devices */ +static void __iomem *bcm_enet_shared_base; + +/* + * io helpers to access mac registers + */ +static inline u32 enet_readl(struct bcm_enet_priv *priv, u32 off) +{ + return bcm_readl(priv->base + off); +} + +static inline void enet_writel(struct bcm_enet_priv *priv, + u32 val, u32 off) +{ + bcm_writel(val, priv->base + off); +} + +/* + * io helpers to access shared registers + */ +static inline u32 enet_dma_readl(struct bcm_enet_priv *priv, u32 off) +{ + return bcm_readl(bcm_enet_shared_base + off); +} + +static inline void enet_dma_writel(struct bcm_enet_priv *priv, + u32 val, u32 off) +{ + bcm_writel(val, bcm_enet_shared_base + off); +} + +/* + * write given data into mii register and wait for transfer to end + * with timeout (average measured transfer time is 25us) + */ +static int do_mdio_op(struct bcm_enet_priv *priv, unsigned int data) +{ + int limit; + + /* make sure mii interrupt status is cleared */ + enet_writel(priv, ENET_IR_MII, ENET_IR_REG); + + enet_writel(priv, data, ENET_MIIDATA_REG); + wmb(); + + /* busy wait on mii interrupt bit, with timeout */ + limit = 1000; + do { + if (enet_readl(priv, ENET_IR_REG) & ENET_IR_MII) + break; + udelay(1); + } while (limit-- >= 0); + + return (limit < 0) ? 1 : 0; +} + +/* + * MII internal read callback + */ +static int bcm_enet_mdio_read(struct bcm_enet_priv *priv, int mii_id, + int regnum) +{ + u32 tmp, val; + + tmp = regnum << ENET_MIIDATA_REG_SHIFT; + tmp |= 0x2 << ENET_MIIDATA_TA_SHIFT; + tmp |= mii_id << ENET_MIIDATA_PHYID_SHIFT; + tmp |= ENET_MIIDATA_OP_READ_MASK; + + if (do_mdio_op(priv, tmp)) + return -1; + + val = enet_readl(priv, ENET_MIIDATA_REG); + val &= 0xffff; + return val; +} + +/* + * MII internal write callback + */ +static int bcm_enet_mdio_write(struct bcm_enet_priv *priv, int mii_id, + int regnum, u16 value) +{ + u32 tmp; + + tmp = (value & 0xffff) << ENET_MIIDATA_DATA_SHIFT; + tmp |= 0x2 << ENET_MIIDATA_TA_SHIFT; + tmp |= regnum << ENET_MIIDATA_REG_SHIFT; + tmp |= mii_id << ENET_MIIDATA_PHYID_SHIFT; + tmp |= ENET_MIIDATA_OP_WRITE_MASK; + + (void)do_mdio_op(priv, tmp); + return 0; +} + +/* + * MII read callback from phylib + */ +static int bcm_enet_mdio_read_phylib(struct mii_bus *bus, int mii_id, + int regnum) +{ + return bcm_enet_mdio_read(bus->priv, mii_id, regnum); +} + +/* + * MII write callback from phylib + */ +static int bcm_enet_mdio_write_phylib(struct mii_bus *bus, int mii_id, + int regnum, u16 value) +{ + return bcm_enet_mdio_write(bus->priv, mii_id, regnum, value); +} + +/* + * MII read callback from mii core + */ +static int bcm_enet_mdio_read_mii(struct net_device *dev, int mii_id, + int regnum) +{ + return bcm_enet_mdio_read(netdev_priv(dev), mii_id, regnum); +} + +/* + * MII write callback from mii core + */ +static void bcm_enet_mdio_write_mii(struct net_device *dev, int mii_id, + int regnum, int value) +{ + bcm_enet_mdio_write(netdev_priv(dev), mii_id, regnum, value); +} + +/* + * refill rx queue + */ +static int bcm_enet_refill_rx(struct net_device *dev) +{ + struct bcm_enet_priv *priv; + + priv = netdev_priv(dev); + + while (priv->rx_desc_count < priv->rx_ring_size) { + struct bcm_enet_desc *desc; + struct sk_buff *skb; + dma_addr_t p; + int desc_idx; + u32 len_stat; + + desc_idx = priv->rx_dirty_desc; + desc = &priv->rx_desc_cpu[desc_idx]; + + if (!priv->rx_skb[desc_idx]) { + skb = netdev_alloc_skb(dev, priv->rx_skb_size); + if (!skb) + break; + priv->rx_skb[desc_idx] = skb; + + p = dma_map_single(&priv->pdev->dev, skb->data, + priv->rx_skb_size, + DMA_FROM_DEVICE); + desc->address = p; + } + + len_stat = priv->rx_skb_size << DMADESC_LENGTH_SHIFT; + len_stat |= DMADESC_OWNER_MASK; + if (priv->rx_dirty_desc == priv->rx_ring_size - 1) { + len_stat |= DMADESC_WRAP_MASK; + priv->rx_dirty_desc = 0; + } else { + priv->rx_dirty_desc++; + } + wmb(); + desc->len_stat = len_stat; + + priv->rx_desc_count++; + + /* tell dma engine we allocated one buffer */ + enet_dma_writel(priv, 1, ENETDMA_BUFALLOC_REG(priv->rx_chan)); + } + + /* If rx ring is still empty, set a timer to try allocating + * again at a later time. */ + if (priv->rx_desc_count == 0 && netif_running(dev)) { + dev_warn(&priv->pdev->dev, "unable to refill rx ring\n"); + priv->rx_timeout.expires = jiffies + HZ; + add_timer(&priv->rx_timeout); + } + + return 0; +} + +/* + * timer callback to defer refill rx queue in case we're OOM + */ +static void bcm_enet_refill_rx_timer(unsigned long data) +{ + struct net_device *dev; + struct bcm_enet_priv *priv; + + dev = (struct net_device *)data; + priv = netdev_priv(dev); + + spin_lock(&priv->rx_lock); + bcm_enet_refill_rx((struct net_device *)data); + spin_unlock(&priv->rx_lock); +} + +/* + * extract packet from rx queue + */ +static int bcm_enet_receive_queue(struct net_device *dev, int budget) +{ + struct bcm_enet_priv *priv; + struct device *kdev; + int processed; + + priv = netdev_priv(dev); + kdev = &priv->pdev->dev; + processed = 0; + + /* don't scan ring further than number of refilled + * descriptor */ + if (budget > priv->rx_desc_count) + budget = priv->rx_desc_count; + + do { + struct bcm_enet_desc *desc; + struct sk_buff *skb; + int desc_idx; + u32 len_stat; + unsigned int len; + + desc_idx = priv->rx_curr_desc; + desc = &priv->rx_desc_cpu[desc_idx]; + + /* make sure we actually read the descriptor status at + * each loop */ + rmb(); + + len_stat = desc->len_stat; + + /* break if dma ownership belongs to hw */ + if (len_stat & DMADESC_OWNER_MASK) + break; + + processed++; + priv->rx_curr_desc++; + if (priv->rx_curr_desc == priv->rx_ring_size) + priv->rx_curr_desc = 0; + priv->rx_desc_count--; + + /* if the packet does not have start of packet _and_ + * end of packet flag set, then just recycle it */ + if ((len_stat & DMADESC_ESOP_MASK) != DMADESC_ESOP_MASK) { + priv->stats.rx_dropped++; + continue; + } + + /* recycle packet if it's marked as bad */ + if (unlikely(len_stat & DMADESC_ERR_MASK)) { + priv->stats.rx_errors++; + + if (len_stat & DMADESC_OVSIZE_MASK) + priv->stats.rx_length_errors++; + if (len_stat & DMADESC_CRC_MASK) + priv->stats.rx_crc_errors++; + if (len_stat & DMADESC_UNDER_MASK) + priv->stats.rx_frame_errors++; + if (len_stat & DMADESC_OV_MASK) + priv->stats.rx_fifo_errors++; + continue; + } + + /* valid packet */ + skb = priv->rx_skb[desc_idx]; + len = (len_stat & DMADESC_LENGTH_MASK) >> DMADESC_LENGTH_SHIFT; + /* don't include FCS */ + len -= 4; + + if (len < copybreak) { + struct sk_buff *nskb; + + nskb = netdev_alloc_skb(dev, len + NET_IP_ALIGN); + if (!nskb) { + /* forget packet, just rearm desc */ + priv->stats.rx_dropped++; + continue; + } + + /* since we're copying the data, we can align + * them properly */ + skb_reserve(nskb, NET_IP_ALIGN); + dma_sync_single_for_cpu(kdev, desc->address, + len, DMA_FROM_DEVICE); + memcpy(nskb->data, skb->data, len); + dma_sync_single_for_device(kdev, desc->address, + len, DMA_FROM_DEVICE); + skb = nskb; + } else { + dma_unmap_single(&priv->pdev->dev, desc->address, + priv->rx_skb_size, DMA_FROM_DEVICE); + priv->rx_skb[desc_idx] = NULL; + } + + skb_put(skb, len); + skb->dev = dev; + skb->protocol = eth_type_trans(skb, dev); + priv->stats.rx_packets++; + priv->stats.rx_bytes += len; + dev->last_rx = jiffies; + netif_receive_skb(skb); + + } while (--budget > 0); + + if (processed || !priv->rx_desc_count) { + bcm_enet_refill_rx(dev); + + /* kick rx dma */ + enet_dma_writel(priv, ENETDMA_CHANCFG_EN_MASK, + ENETDMA_CHANCFG_REG(priv->rx_chan)); + } + + return processed; +} + + +/* + * try to or force reclaim of transmitted buffers + */ +static int bcm_enet_tx_reclaim(struct net_device *dev, int force) +{ + struct bcm_enet_priv *priv; + int released; + + priv = netdev_priv(dev); + released = 0; + + while (priv->tx_desc_count < priv->tx_ring_size) { + struct bcm_enet_desc *desc; + struct sk_buff *skb; + + /* We run in a bh and fight against start_xmit, which + * is called with bh disabled */ + spin_lock(&priv->tx_lock); + + desc = &priv->tx_desc_cpu[priv->tx_dirty_desc]; + + if (!force && (desc->len_stat & DMADESC_OWNER_MASK)) { + spin_unlock(&priv->tx_lock); + break; + } + + /* ensure other field of the descriptor were not read + * before we checked ownership */ + rmb(); + + skb = priv->tx_skb[priv->tx_dirty_desc]; + priv->tx_skb[priv->tx_dirty_desc] = NULL; + dma_unmap_single(&priv->pdev->dev, desc->address, skb->len, + DMA_TO_DEVICE); + + priv->tx_dirty_desc++; + if (priv->tx_dirty_desc == priv->tx_ring_size) + priv->tx_dirty_desc = 0; + priv->tx_desc_count++; + + spin_unlock(&priv->tx_lock); + + if (desc->len_stat & DMADESC_UNDER_MASK) + priv->stats.tx_errors++; + + dev_kfree_skb(skb); + released++; + } + + if (netif_queue_stopped(dev) && released) + netif_wake_queue(dev); + + return released; +} + +/* + * poll func, called by network core + */ +static int bcm_enet_poll(struct napi_struct *napi, int budget) +{ + struct bcm_enet_priv *priv; + struct net_device *dev; + int tx_work_done, rx_work_done; + + priv = container_of(napi, struct bcm_enet_priv, napi); + dev = priv->net_dev; + + /* ack interrupts */ + enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK, + ENETDMA_IR_REG(priv->rx_chan)); + enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK, + ENETDMA_IR_REG(priv->tx_chan)); + + /* reclaim sent skb */ + tx_work_done = bcm_enet_tx_reclaim(dev, 0); + + spin_lock(&priv->rx_lock); + rx_work_done = bcm_enet_receive_queue(dev, budget); + spin_unlock(&priv->rx_lock); + + if (rx_work_done >= budget || tx_work_done > 0) { + /* rx/tx queue is not yet empty/clean */ + return rx_work_done; + } + + /* no more packet in rx/tx queue, remove device from poll + * queue */ + napi_complete(napi); + + /* restore rx/tx interrupt */ + enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK, + ENETDMA_IRMASK_REG(priv->rx_chan)); + enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK, + ENETDMA_IRMASK_REG(priv->tx_chan)); + + return rx_work_done; +} + +/* + * mac interrupt handler + */ +static irqreturn_t bcm_enet_isr_mac(int irq, void *dev_id) +{ + struct net_device *dev; + struct bcm_enet_priv *priv; + u32 stat; + + dev = dev_id; + priv = netdev_priv(dev); + + stat = enet_readl(priv, ENET_IR_REG); + if (!(stat & ENET_IR_MIB)) + return IRQ_NONE; + + /* clear & mask interrupt */ + enet_writel(priv, ENET_IR_MIB, ENET_IR_REG); + enet_writel(priv, 0, ENET_IRMASK_REG); + + /* read mib registers in workqueue */ + schedule_work(&priv->mib_update_task); + + return IRQ_HANDLED; +} + +/* + * rx/tx dma interrupt handler + */ +static irqreturn_t bcm_enet_isr_dma(int irq, void *dev_id) +{ + struct net_device *dev; + struct bcm_enet_priv *priv; + + dev = dev_id; + priv = netdev_priv(dev); + + /* mask rx/tx interrupts */ + enet_dma_writel(priv, 0, ENETDMA_IRMASK_REG(priv->rx_chan)); + enet_dma_writel(priv, 0, ENETDMA_IRMASK_REG(priv->tx_chan)); + + napi_schedule(&priv->napi); + + return IRQ_HANDLED; +} + +/* + * tx request callback + */ +static int bcm_enet_start_xmit(struct sk_buff *skb, struct net_device *dev) +{ + struct bcm_enet_priv *priv; + struct bcm_enet_desc *desc; + u32 len_stat; + int ret; + + priv = netdev_priv(dev); + + /* lock against tx reclaim */ + spin_lock(&priv->tx_lock); + + /* make sure the tx hw queue is not full, should not happen + * since we stop queue before it's the case */ + if (unlikely(!priv->tx_desc_count)) { + netif_stop_queue(dev); + dev_err(&priv->pdev->dev, "xmit called with no tx desc " + "available?\n"); + ret = NETDEV_TX_BUSY; + goto out_unlock; + } + + /* point to the next available desc */ + desc = &priv->tx_desc_cpu[priv->tx_curr_desc]; + priv->tx_skb[priv->tx_curr_desc] = skb; + + /* fill descriptor */ + desc->address = dma_map_single(&priv->pdev->dev, skb->data, skb->len, + DMA_TO_DEVICE); + + len_stat = (skb->len << DMADESC_LENGTH_SHIFT) & DMADESC_LENGTH_MASK; + len_stat |= DMADESC_ESOP_MASK | + DMADESC_APPEND_CRC | + DMADESC_OWNER_MASK; + + priv->tx_curr_desc++; + if (priv->tx_curr_desc == priv->tx_ring_size) { + priv->tx_curr_desc = 0; + len_stat |= DMADESC_WRAP_MASK; + } + priv->tx_desc_count--; + + /* dma might be already polling, make sure we update desc + * fields in correct order */ + wmb(); + desc->len_stat = len_stat; + wmb(); + + /* kick tx dma */ + enet_dma_writel(priv, ENETDMA_CHANCFG_EN_MASK, + ENETDMA_CHANCFG_REG(priv->tx_chan)); + + /* stop queue if no more desc available */ + if (!priv->tx_desc_count) + netif_stop_queue(dev); + + priv->stats.tx_bytes += skb->len; + priv->stats.tx_packets++; + dev->trans_start = jiffies; + ret = NETDEV_TX_OK; + +out_unlock: + spin_unlock(&priv->tx_lock); + return ret; +} + +/* + * Change the interface's mac address. + */ +static int bcm_enet_set_mac_address(struct net_device *dev, void *p) +{ + struct bcm_enet_priv *priv; + struct sockaddr *addr = p; + u32 val; + + priv = netdev_priv(dev); + memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN); + + /* use perfect match register 0 to store my mac address */ + val = (dev->dev_addr[2] << 24) | (dev->dev_addr[3] << 16) | + (dev->dev_addr[4] << 8) | dev->dev_addr[5]; + enet_writel(priv, val, ENET_PML_REG(0)); + + val = (dev->dev_addr[0] << 8 | dev->dev_addr[1]); + val |= ENET_PMH_DATAVALID_MASK; + enet_writel(priv, val, ENET_PMH_REG(0)); + + return 0; +} + +/* + * Change rx mode (promiscous/allmulti) and update multicast list + */ +static void bcm_enet_set_multicast_list(struct net_device *dev) +{ + struct bcm_enet_priv *priv; + struct dev_mc_list *mc_list; + u32 val; + int i; + + priv = netdev_priv(dev); + + val = enet_readl(priv, ENET_RXCFG_REG); + + if (dev->flags & IFF_PROMISC) + val |= ENET_RXCFG_PROMISC_MASK; + else + val &= ~ENET_RXCFG_PROMISC_MASK; + + /* only 3 perfect match registers left, first one is used for + * own mac address */ + if ((dev->flags & IFF_ALLMULTI) || dev->mc_count > 3) + val |= ENET_RXCFG_ALLMCAST_MASK; + else + val &= ~ENET_RXCFG_ALLMCAST_MASK; + + /* no need to set perfect match registers if we catch all + * multicast */ + if (val & ENET_RXCFG_ALLMCAST_MASK) { + enet_writel(priv, val, ENET_RXCFG_REG); + return; + } + + for (i = 0, mc_list = dev->mc_list; + (mc_list != NULL) && (i < dev->mc_count) && (i < 3); + i++, mc_list = mc_list->next) { + u8 *dmi_addr; + u32 tmp; + + /* filter non ethernet address */ + if (mc_list->dmi_addrlen != 6) + continue; + + /* update perfect match registers */ + dmi_addr = mc_list->dmi_addr; + tmp = (dmi_addr[2] << 24) | (dmi_addr[3] << 16) | + (dmi_addr[4] << 8) | dmi_addr[5]; + enet_writel(priv, tmp, ENET_PML_REG(i + 1)); + + tmp = (dmi_addr[0] << 8 | dmi_addr[1]); + tmp |= ENET_PMH_DATAVALID_MASK; + enet_writel(priv, tmp, ENET_PMH_REG(i + 1)); + } + + for (; i < 3; i++) { + enet_writel(priv, 0, ENET_PML_REG(i + 1)); + enet_writel(priv, 0, ENET_PMH_REG(i + 1)); + } + + enet_writel(priv, val, ENET_RXCFG_REG); +} + +/* + * set mac duplex parameters + */ +static void bcm_enet_set_duplex(struct bcm_enet_priv *priv, int fullduplex) +{ + u32 val; + + val = enet_readl(priv, ENET_TXCTL_REG); + if (fullduplex) + val |= ENET_TXCTL_FD_MASK; + else + val &= ~ENET_TXCTL_FD_MASK; + enet_writel(priv, val, ENET_TXCTL_REG); +} + +/* + * set mac flow control parameters + */ +static void bcm_enet_set_flow(struct bcm_enet_priv *priv, int rx_en, int tx_en) +{ + u32 val; + + /* rx flow control (pause frame handling) */ + val = enet_readl(priv, ENET_RXCFG_REG); + if (rx_en) + val |= ENET_RXCFG_ENFLOW_MASK; + else + val &= ~ENET_RXCFG_ENFLOW_MASK; + enet_writel(priv, val, ENET_RXCFG_REG); + + /* tx flow control (pause frame generation) */ + val = enet_dma_readl(priv, ENETDMA_CFG_REG); + if (tx_en) + val |= ENETDMA_CFG_FLOWCH_MASK(priv->rx_chan); + else + val &= ~ENETDMA_CFG_FLOWCH_MASK(priv->rx_chan); + enet_dma_writel(priv, val, ENETDMA_CFG_REG); +} + +/* + * link changed callback (from phylib) + */ +static void bcm_enet_adjust_phy_link(struct net_device *dev) +{ + struct bcm_enet_priv *priv; + struct phy_device *phydev; + int status_changed; + + priv = netdev_priv(dev); + phydev = priv->phydev; + status_changed = 0; + + if (priv->old_link != phydev->link) { + status_changed = 1; + priv->old_link = phydev->link; + } + + /* reflect duplex change in mac configuration */ + if (phydev->link && phydev->duplex != priv->old_duplex) { + bcm_enet_set_duplex(priv, + (phydev->duplex == DUPLEX_FULL) ? 1 : 0); + status_changed = 1; + priv->old_duplex = phydev->duplex; + } + + /* enable flow control if remote advertise it (trust phylib to + * check that duplex is full */ + if (phydev->link && phydev->pause != priv->old_pause) { + int rx_pause_en, tx_pause_en; + + if (phydev->pause) { + /* pause was advertised by lpa and us */ + rx_pause_en = 1; + tx_pause_en = 1; + } else if (!priv->pause_auto) { + /* pause setting overrided by user */ + rx_pause_en = priv->pause_rx; + tx_pause_en = priv->pause_tx; + } else { + rx_pause_en = 0; + tx_pause_en = 0; + } + + bcm_enet_set_flow(priv, rx_pause_en, tx_pause_en); + status_changed = 1; + priv->old_pause = phydev->pause; + } + + if (status_changed) { + pr_info("%s: link %s", dev->name, phydev->link ? + "UP" : "DOWN"); + if (phydev->link) + pr_cont(" - %d/%s - flow control %s", phydev->speed, + DUPLEX_FULL == phydev->duplex ? "full" : "half", + phydev->pause == 1 ? "rx&tx" : "off"); + + pr_cont("\n"); + } +} + +/* + * link changed callback (if phylib is not used) + */ +static void bcm_enet_adjust_link(struct net_device *dev) +{ + struct bcm_enet_priv *priv; + + priv = netdev_priv(dev); + bcm_enet_set_duplex(priv, priv->force_duplex_full); + bcm_enet_set_flow(priv, priv->pause_rx, priv->pause_tx); + netif_carrier_on(dev); + + pr_info("%s: link forced UP - %d/%s - flow control %s/%s\n", + dev->name, + priv->force_speed_100 ? 100 : 10, + priv->force_duplex_full ? "full" : "half", + priv->pause_rx ? "rx" : "off", + priv->pause_tx ? "tx" : "off"); +} + +/* + * open callback, allocate dma rings & buffers and start rx operation + */ +static int bcm_enet_open(struct net_device *dev) +{ + struct bcm_enet_priv *priv; + struct sockaddr addr; + struct device *kdev; + struct phy_device *phydev; + int i, ret; + unsigned int size; + char phy_id[MII_BUS_ID_SIZE + 3]; + void *p; + u32 val; + + priv = netdev_priv(dev); + kdev = &priv->pdev->dev; + + if (priv->has_phy) { + /* connect to PHY */ + snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT, + priv->mac_id ? "1" : "0", priv->phy_id); + + phydev = phy_connect(dev, phy_id, &bcm_enet_adjust_phy_link, 0, + PHY_INTERFACE_MODE_MII); + + if (IS_ERR(phydev)) { + dev_err(kdev, "could not attach to PHY\n"); + return PTR_ERR(phydev); + } + + /* mask with MAC supported features */ + phydev->supported &= (SUPPORTED_10baseT_Half | + SUPPORTED_10baseT_Full | + SUPPORTED_100baseT_Half | + SUPPORTED_100baseT_Full | + SUPPORTED_Autoneg | + SUPPORTED_Pause | + SUPPORTED_MII); + phydev->advertising = phydev->supported; + + if (priv->pause_auto && priv->pause_rx && priv->pause_tx) + phydev->advertising |= SUPPORTED_Pause; + else + phydev->advertising &= ~SUPPORTED_Pause; + + dev_info(kdev, "attached PHY at address %d [%s]\n", + phydev->addr, phydev->drv->name); + + priv->old_link = 0; + priv->old_duplex = -1; + priv->old_pause = -1; + priv->phydev = phydev; + } + + /* mask all interrupts and request them */ + enet_writel(priv, 0, ENET_IRMASK_REG); + enet_dma_writel(priv, 0, ENETDMA_IRMASK_REG(priv->rx_chan)); + enet_dma_writel(priv, 0, ENETDMA_IRMASK_REG(priv->tx_chan)); + + ret = request_irq(dev->irq, bcm_enet_isr_mac, 0, dev->name, dev); + if (ret) + goto out_phy_disconnect; + + ret = request_irq(priv->irq_rx, bcm_enet_isr_dma, + IRQF_SAMPLE_RANDOM | IRQF_DISABLED, dev->name, dev); + if (ret) + goto out_freeirq; + + ret = request_irq(priv->irq_tx, bcm_enet_isr_dma, + IRQF_DISABLED, dev->name, dev); + if (ret) + goto out_freeirq_rx; + + /* initialize perfect match registers */ + for (i = 0; i < 4; i++) { + enet_writel(priv, 0, ENET_PML_REG(i)); + enet_writel(priv, 0, ENET_PMH_REG(i)); + } + + /* write device mac address */ + memcpy(addr.sa_data, dev->dev_addr, ETH_ALEN); + bcm_enet_set_mac_address(dev, &addr); + + /* allocate rx dma ring */ + size = priv->rx_ring_size * sizeof(struct bcm_enet_desc); + p = dma_alloc_coherent(kdev, size, &priv->rx_desc_dma, GFP_KERNEL); + if (!p) { + dev_err(kdev, "cannot allocate rx ring %u\n", size); + ret = -ENOMEM; + goto out_freeirq_tx; + } + + memset(p, 0, size); + priv->rx_desc_alloc_size = size; + priv->rx_desc_cpu = p; + + /* allocate tx dma ring */ + size = priv->tx_ring_size * sizeof(struct bcm_enet_desc); + p = dma_alloc_coherent(kdev, size, &priv->tx_desc_dma, GFP_KERNEL); + if (!p) { + dev_err(kdev, "cannot allocate tx ring\n"); + ret = -ENOMEM; + goto out_free_rx_ring; + } + + memset(p, 0, size); + priv->tx_desc_alloc_size = size; + priv->tx_desc_cpu = p; + + priv->tx_skb = kzalloc(sizeof(struct sk_buff *) * priv->tx_ring_size, + GFP_KERNEL); + if (!priv->tx_skb) { + dev_err(kdev, "cannot allocate rx skb queue\n"); + ret = -ENOMEM; + goto out_free_tx_ring; + } + + priv->tx_desc_count = priv->tx_ring_size; + priv->tx_dirty_desc = 0; + priv->tx_curr_desc = 0; + spin_lock_init(&priv->tx_lock); + + /* init & fill rx ring with skbs */ + priv->rx_skb = kzalloc(sizeof(struct sk_buff *) * priv->rx_ring_size, + GFP_KERNEL); + if (!priv->rx_skb) { + dev_err(kdev, "cannot allocate rx skb queue\n"); + ret = -ENOMEM; + goto out_free_tx_skb; + } + + priv->rx_desc_count = 0; + priv->rx_dirty_desc = 0; + priv->rx_curr_desc = 0; + + /* initialize flow control buffer allocation */ + enet_dma_writel(priv, ENETDMA_BUFALLOC_FORCE_MASK | 0, + ENETDMA_BUFALLOC_REG(priv->rx_chan)); + + if (bcm_enet_refill_rx(dev)) { + dev_err(kdev, "cannot allocate rx skb queue\n"); + ret = -ENOMEM; + goto out; + } + + /* write rx & tx ring addresses */ + enet_dma_writel(priv, priv->rx_desc_dma, + ENETDMA_RSTART_REG(priv->rx_chan)); + enet_dma_writel(priv, priv->tx_desc_dma, + ENETDMA_RSTART_REG(priv->tx_chan)); + + /* clear remaining state ram for rx & tx channel */ + enet_dma_writel(priv, 0, ENETDMA_SRAM2_REG(priv->rx_chan)); + enet_dma_writel(priv, 0, ENETDMA_SRAM2_REG(priv->tx_chan)); + enet_dma_writel(priv, 0, ENETDMA_SRAM3_REG(priv->rx_chan)); + enet_dma_writel(priv, 0, ENETDMA_SRAM3_REG(priv->tx_chan)); + enet_dma_writel(priv, 0, ENETDMA_SRAM4_REG(priv->rx_chan)); + enet_dma_writel(priv, 0, ENETDMA_SRAM4_REG(priv->tx_chan)); + + /* set max rx/tx length */ + enet_writel(priv, priv->hw_mtu, ENET_RXMAXLEN_REG); + enet_writel(priv, priv->hw_mtu, ENET_TXMAXLEN_REG); + + /* set dma maximum burst len */ + enet_dma_writel(priv, BCMENET_DMA_MAXBURST, + ENETDMA_MAXBURST_REG(priv->rx_chan)); + enet_dma_writel(priv, BCMENET_DMA_MAXBURST, + ENETDMA_MAXBURST_REG(priv->tx_chan)); + + /* set correct transmit fifo watermark */ + enet_writel(priv, BCMENET_TX_FIFO_TRESH, ENET_TXWMARK_REG); + + /* set flow control low/high threshold to 1/3 / 2/3 */ + val = priv->rx_ring_size / 3; + enet_dma_writel(priv, val, ENETDMA_FLOWCL_REG(priv->rx_chan)); + val = (priv->rx_ring_size * 2) / 3; + enet_dma_writel(priv, val, ENETDMA_FLOWCH_REG(priv->rx_chan)); + + /* all set, enable mac and interrupts, start dma engine and + * kick rx dma channel */ + wmb(); + enet_writel(priv, ENET_CTL_ENABLE_MASK, ENET_CTL_REG); + enet_dma_writel(priv, ENETDMA_CFG_EN_MASK, ENETDMA_CFG_REG); + enet_dma_writel(priv, ENETDMA_CHANCFG_EN_MASK, + ENETDMA_CHANCFG_REG(priv->rx_chan)); + + /* watch "mib counters about to overflow" interrupt */ + enet_writel(priv, ENET_IR_MIB, ENET_IR_REG); + enet_writel(priv, ENET_IR_MIB, ENET_IRMASK_REG); + + /* watch "packet transferred" interrupt in rx and tx */ + enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK, + ENETDMA_IR_REG(priv->rx_chan)); + enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK, + ENETDMA_IR_REG(priv->tx_chan)); + + /* make sure we enable napi before rx interrupt */ + napi_enable(&priv->napi); + + enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK, + ENETDMA_IRMASK_REG(priv->rx_chan)); + enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK, + ENETDMA_IRMASK_REG(priv->tx_chan)); + + if (priv->has_phy) + phy_start(priv->phydev); + else + bcm_enet_adjust_link(dev); + + netif_start_queue(dev); + return 0; + +out: + for (i = 0; i < priv->rx_ring_size; i++) { + struct bcm_enet_desc *desc; + + if (!priv->rx_skb[i]) + continue; + + desc = &priv->rx_desc_cpu[i]; + dma_unmap_single(kdev, desc->address, priv->rx_skb_size, + DMA_FROM_DEVICE); + kfree_skb(priv->rx_skb[i]); + } + kfree(priv->rx_skb); + +out_free_tx_skb: + kfree(priv->tx_skb); + +out_free_tx_ring: + dma_free_coherent(kdev, priv->tx_desc_alloc_size, + priv->tx_desc_cpu, priv->tx_desc_dma); + +out_free_rx_ring: + dma_free_coherent(kdev, priv->rx_desc_alloc_size, + priv->rx_desc_cpu, priv->rx_desc_dma); + +out_freeirq_tx: + free_irq(priv->irq_tx, dev); + +out_freeirq_rx: + free_irq(priv->irq_rx, dev); + +out_freeirq: + free_irq(dev->irq, dev); + +out_phy_disconnect: + phy_disconnect(priv->phydev); + + return ret; +} + +/* + * disable mac + */ +static void bcm_enet_disable_mac(struct bcm_enet_priv *priv) +{ + int limit; + u32 val; + + val = enet_readl(priv, ENET_CTL_REG); + val |= ENET_CTL_DISABLE_MASK; + enet_writel(priv, val, ENET_CTL_REG); + + limit = 1000; + do { + u32 val; + + val = enet_readl(priv, ENET_CTL_REG); + if (!(val & ENET_CTL_DISABLE_MASK)) + break; + udelay(1); + } while (limit--); +} + +/* + * disable dma in given channel + */ +static void bcm_enet_disable_dma(struct bcm_enet_priv *priv, int chan) +{ + int limit; + + enet_dma_writel(priv, 0, ENETDMA_CHANCFG_REG(chan)); + + limit = 1000; + do { + u32 val; + + val = enet_dma_readl(priv, ENETDMA_CHANCFG_REG(chan)); + if (!(val & ENETDMA_CHANCFG_EN_MASK)) + break; + udelay(1); + } while (limit--); +} + +/* + * stop callback + */ +static int bcm_enet_stop(struct net_device *dev) +{ + struct bcm_enet_priv *priv; + struct device *kdev; + int i; + + priv = netdev_priv(dev); + kdev = &priv->pdev->dev; + + netif_stop_queue(dev); + napi_disable(&priv->napi); + if (priv->has_phy) + phy_stop(priv->phydev); + del_timer_sync(&priv->rx_timeout); + + /* mask all interrupts */ + enet_writel(priv, 0, ENET_IRMASK_REG); + enet_dma_writel(priv, 0, ENETDMA_IRMASK_REG(priv->rx_chan)); + enet_dma_writel(priv, 0, ENETDMA_IRMASK_REG(priv->tx_chan)); + + /* make sure no mib update is scheduled */ + flush_scheduled_work(); + + /* disable dma & mac */ + bcm_enet_disable_dma(priv, priv->tx_chan); + bcm_enet_disable_dma(priv, priv->rx_chan); + bcm_enet_disable_mac(priv); + + /* force reclaim of all tx buffers */ + bcm_enet_tx_reclaim(dev, 1); + + /* free the rx skb ring */ + for (i = 0; i < priv->rx_ring_size; i++) { + struct bcm_enet_desc *desc; + + if (!priv->rx_skb[i]) + continue; + + desc = &priv->rx_desc_cpu[i]; + dma_unmap_single(kdev, desc->address, priv->rx_skb_size, + DMA_FROM_DEVICE); + kfree_skb(priv->rx_skb[i]); + } + + /* free remaining allocated memory */ + kfree(priv->rx_skb); + kfree(priv->tx_skb); + dma_free_coherent(kdev, priv->rx_desc_alloc_size, + priv->rx_desc_cpu, priv->rx_desc_dma); + dma_free_coherent(kdev, priv->tx_desc_alloc_size, + priv->tx_desc_cpu, priv->tx_desc_dma); + free_irq(priv->irq_tx, dev); + free_irq(priv->irq_rx, dev); + free_irq(dev->irq, dev); + + /* release phy */ + if (priv->has_phy) { + phy_disconnect(priv->phydev); + priv->phydev = NULL; + } + + return 0; +} + +/* + * core request to return device rx/tx stats + */ +static struct net_device_stats *bcm_enet_get_stats(struct net_device *dev) +{ + struct bcm_enet_priv *priv; + + priv = netdev_priv(dev); + return &priv->stats; +} + +/* + * ethtool callbacks + */ +struct bcm_enet_stats { + char stat_string[ETH_GSTRING_LEN]; + int sizeof_stat; + int stat_offset; + int mib_reg; +}; + +#define GEN_STAT(m) sizeof(((struct bcm_enet_priv *)0)->m), \ + offsetof(struct bcm_enet_priv, m) + +static const struct bcm_enet_stats bcm_enet_gstrings_stats[] = { + { "rx_packets", GEN_STAT(stats.rx_packets), -1 }, + { "tx_packets", GEN_STAT(stats.tx_packets), -1 }, + { "rx_bytes", GEN_STAT(stats.rx_bytes), -1 }, + { "tx_bytes", GEN_STAT(stats.tx_bytes), -1 }, + { "rx_errors", GEN_STAT(stats.rx_errors), -1 }, + { "tx_errors", GEN_STAT(stats.tx_errors), -1 }, + { "rx_dropped", GEN_STAT(stats.rx_dropped), -1 }, + { "tx_dropped", GEN_STAT(stats.tx_dropped), -1 }, + + { "rx_good_octets", GEN_STAT(mib.rx_gd_octets), ETH_MIB_RX_GD_OCTETS}, + { "rx_good_pkts", GEN_STAT(mib.rx_gd_pkts), ETH_MIB_RX_GD_PKTS }, + { "rx_broadcast", GEN_STAT(mib.rx_brdcast), ETH_MIB_RX_BRDCAST }, + { "rx_multicast", GEN_STAT(mib.rx_mult), ETH_MIB_RX_MULT }, + { "rx_64_octets", GEN_STAT(mib.rx_64), ETH_MIB_RX_64 }, + { "rx_65_127_oct", GEN_STAT(mib.rx_65_127), ETH_MIB_RX_65_127 }, + { "rx_128_255_oct", GEN_STAT(mib.rx_128_255), ETH_MIB_RX_128_255 }, + { "rx_256_511_oct", GEN_STAT(mib.rx_256_511), ETH_MIB_RX_256_511 }, + { "rx_512_1023_oct", GEN_STAT(mib.rx_512_1023), ETH_MIB_RX_512_1023 }, + { "rx_1024_max_oct", GEN_STAT(mib.rx_1024_max), ETH_MIB_RX_1024_MAX }, + { "rx_jabber", GEN_STAT(mib.rx_jab), ETH_MIB_RX_JAB }, + { "rx_oversize", GEN_STAT(mib.rx_ovr), ETH_MIB_RX_OVR }, + { "rx_fragment", GEN_STAT(mib.rx_frag), ETH_MIB_RX_FRAG }, + { "rx_dropped", GEN_STAT(mib.rx_drop), ETH_MIB_RX_DROP }, + { "rx_crc_align", GEN_STAT(mib.rx_crc_align), ETH_MIB_RX_CRC_ALIGN }, + { "rx_undersize", GEN_STAT(mib.rx_und), ETH_MIB_RX_UND }, + { "rx_crc", GEN_STAT(mib.rx_crc), ETH_MIB_RX_CRC }, + { "rx_align", GEN_STAT(mib.rx_align), ETH_MIB_RX_ALIGN }, + { "rx_symbol_error", GEN_STAT(mib.rx_sym), ETH_MIB_RX_SYM }, + { "rx_pause", GEN_STAT(mib.rx_pause), ETH_MIB_RX_PAUSE }, + { "rx_control", GEN_STAT(mib.rx_cntrl), ETH_MIB_RX_CNTRL }, + + { "tx_good_octets", GEN_STAT(mib.tx_gd_octets), ETH_MIB_TX_GD_OCTETS }, + { "tx_good_pkts", GEN_STAT(mib.tx_gd_pkts), ETH_MIB_TX_GD_PKTS }, + { "tx_broadcast", GEN_STAT(mib.tx_brdcast), ETH_MIB_TX_BRDCAST }, + { "tx_multicast", GEN_STAT(mib.tx_mult), ETH_MIB_TX_MULT }, + { "tx_64_oct", GEN_STAT(mib.tx_64), ETH_MIB_TX_64 }, + { "tx_65_127_oct", GEN_STAT(mib.tx_65_127), ETH_MIB_TX_65_127 }, + { "tx_128_255_oct", GEN_STAT(mib.tx_128_255), ETH_MIB_TX_128_255 }, + { "tx_256_511_oct", GEN_STAT(mib.tx_256_511), ETH_MIB_TX_256_511 }, + { "tx_512_1023_oct", GEN_STAT(mib.tx_512_1023), ETH_MIB_TX_512_1023}, + { "tx_1024_max_oct", GEN_STAT(mib.tx_1024_max), ETH_MIB_TX_1024_MAX }, + { "tx_jabber", GEN_STAT(mib.tx_jab), ETH_MIB_TX_JAB }, + { "tx_oversize", GEN_STAT(mib.tx_ovr), ETH_MIB_TX_OVR }, + { "tx_fragment", GEN_STAT(mib.tx_frag), ETH_MIB_TX_FRAG }, + { "tx_underrun", GEN_STAT(mib.tx_underrun), ETH_MIB_TX_UNDERRUN }, + { "tx_collisions", GEN_STAT(mib.tx_col), ETH_MIB_TX_COL }, + { "tx_single_collision", GEN_STAT(mib.tx_1_col), ETH_MIB_TX_1_COL }, + { "tx_multiple_collision", GEN_STAT(mib.tx_m_col), ETH_MIB_TX_M_COL }, + { "tx_excess_collision", GEN_STAT(mib.tx_ex_col), ETH_MIB_TX_EX_COL }, + { "tx_late_collision", GEN_STAT(mib.tx_late), ETH_MIB_TX_LATE }, + { "tx_deferred", GEN_STAT(mib.tx_def), ETH_MIB_TX_DEF }, + { "tx_carrier_sense", GEN_STAT(mib.tx_crs), ETH_MIB_TX_CRS }, + { "tx_pause", GEN_STAT(mib.tx_pause), ETH_MIB_TX_PAUSE }, + +}; + +#define BCM_ENET_STATS_LEN \ + (sizeof(bcm_enet_gstrings_stats) / sizeof(struct bcm_enet_stats)) + +static const u32 unused_mib_regs[] = { + ETH_MIB_TX_ALL_OCTETS, + ETH_MIB_TX_ALL_PKTS, + ETH_MIB_RX_ALL_OCTETS, + ETH_MIB_RX_ALL_PKTS, +}; + + +static void bcm_enet_get_drvinfo(struct net_device *netdev, + struct ethtool_drvinfo *drvinfo) +{ + strncpy(drvinfo->driver, bcm_enet_driver_name, 32); + strncpy(drvinfo->version, bcm_enet_driver_version, 32); + strncpy(drvinfo->fw_version, "N/A", 32); + strncpy(drvinfo->bus_info, "bcm63xx", 32); + drvinfo->n_stats = BCM_ENET_STATS_LEN; +} + +static int bcm_enet_get_stats_count(struct net_device *netdev) +{ + return BCM_ENET_STATS_LEN; +} + +static void bcm_enet_get_strings(struct net_device *netdev, + u32 stringset, u8 *data) +{ + int i; + + switch (stringset) { + case ETH_SS_STATS: + for (i = 0; i < BCM_ENET_STATS_LEN; i++) { + memcpy(data + i * ETH_GSTRING_LEN, + bcm_enet_gstrings_stats[i].stat_string, + ETH_GSTRING_LEN); + } + break; + } +} + +static void update_mib_counters(struct bcm_enet_priv *priv) +{ + int i; + + for (i = 0; i < BCM_ENET_STATS_LEN; i++) { + const struct bcm_enet_stats *s; + u32 val; + char *p; + + s = &bcm_enet_gstrings_stats[i]; + if (s->mib_reg == -1) + continue; + + val = enet_readl(priv, ENET_MIB_REG(s->mib_reg)); + p = (char *)priv + s->stat_offset; + + if (s->sizeof_stat == sizeof(u64)) + *(u64 *)p += val; + else + *(u32 *)p += val; + } + + /* also empty unused mib counters to make sure mib counter + * overflow interrupt is cleared */ + for (i = 0; i < ARRAY_SIZE(unused_mib_regs); i++) + (void)enet_readl(priv, ENET_MIB_REG(unused_mib_regs[i])); +} + +static void bcm_enet_update_mib_counters_defer(struct work_struct *t) +{ + struct bcm_enet_priv *priv; + + priv = container_of(t, struct bcm_enet_priv, mib_update_task); + mutex_lock(&priv->mib_update_lock); + update_mib_counters(priv); + mutex_unlock(&priv->mib_update_lock); + + /* reenable mib interrupt */ + if (netif_running(priv->net_dev)) + enet_writel(priv, ENET_IR_MIB, ENET_IRMASK_REG); +} + +static void bcm_enet_get_ethtool_stats(struct net_device *netdev, + struct ethtool_stats *stats, + u64 *data) +{ + struct bcm_enet_priv *priv; + int i; + + priv = netdev_priv(netdev); + + mutex_lock(&priv->mib_update_lock); + update_mib_counters(priv); + + for (i = 0; i < BCM_ENET_STATS_LEN; i++) { + const struct bcm_enet_stats *s; + char *p; + + s = &bcm_enet_gstrings_stats[i]; + p = (char *)priv + s->stat_offset; + data[i] = (s->sizeof_stat == sizeof(u64)) ? + *(u64 *)p : *(u32 *)p; + } + mutex_unlock(&priv->mib_update_lock); +} + +static int bcm_enet_get_settings(struct net_device *dev, + struct ethtool_cmd *cmd) +{ + struct bcm_enet_priv *priv; + + priv = netdev_priv(dev); + + cmd->maxrxpkt = 0; + cmd->maxtxpkt = 0; + + if (priv->has_phy) { + if (!priv->phydev) + return -ENODEV; + return phy_ethtool_gset(priv->phydev, cmd); + } else { + cmd->autoneg = 0; + cmd->speed = (priv->force_speed_100) ? SPEED_100 : SPEED_10; + cmd->duplex = (priv->force_duplex_full) ? + DUPLEX_FULL : DUPLEX_HALF; + cmd->supported = ADVERTISED_10baseT_Half | + ADVERTISED_10baseT_Full | + ADVERTISED_100baseT_Half | + ADVERTISED_100baseT_Full; + cmd->advertising = 0; + cmd->port = PORT_MII; + cmd->transceiver = XCVR_EXTERNAL; + } + return 0; +} + +static int bcm_enet_set_settings(struct net_device *dev, + struct ethtool_cmd *cmd) +{ + struct bcm_enet_priv *priv; + + priv = netdev_priv(dev); + if (priv->has_phy) { + if (!priv->phydev) + return -ENODEV; + return phy_ethtool_sset(priv->phydev, cmd); + } else { + + if (cmd->autoneg || + (cmd->speed != SPEED_100 && cmd->speed != SPEED_10) || + cmd->port != PORT_MII) + return -EINVAL; + + priv->force_speed_100 = (cmd->speed == SPEED_100) ? 1 : 0; + priv->force_duplex_full = (cmd->duplex == DUPLEX_FULL) ? 1 : 0; + + if (netif_running(dev)) + bcm_enet_adjust_link(dev); + return 0; + } +} + +static void bcm_enet_get_ringparam(struct net_device *dev, + struct ethtool_ringparam *ering) +{ + struct bcm_enet_priv *priv; + + priv = netdev_priv(dev); + + /* rx/tx ring is actually only limited by memory */ + ering->rx_max_pending = 8192; + ering->tx_max_pending = 8192; + ering->rx_mini_max_pending = 0; + ering->rx_jumbo_max_pending = 0; + ering->rx_pending = priv->rx_ring_size; + ering->tx_pending = priv->tx_ring_size; +} + +static int bcm_enet_set_ringparam(struct net_device *dev, + struct ethtool_ringparam *ering) +{ + struct bcm_enet_priv *priv; + int was_running; + + priv = netdev_priv(dev); + + was_running = 0; + if (netif_running(dev)) { + bcm_enet_stop(dev); + was_running = 1; + } + + priv->rx_ring_size = ering->rx_pending; + priv->tx_ring_size = ering->tx_pending; + + if (was_running) { + int err; + + err = bcm_enet_open(dev); + if (err) + dev_close(dev); + else + bcm_enet_set_multicast_list(dev); + } + return 0; +} + +static void bcm_enet_get_pauseparam(struct net_device *dev, + struct ethtool_pauseparam *ecmd) +{ + struct bcm_enet_priv *priv; + + priv = netdev_priv(dev); + ecmd->autoneg = priv->pause_auto; + ecmd->rx_pause = priv->pause_rx; + ecmd->tx_pause = priv->pause_tx; +} + +static int bcm_enet_set_pauseparam(struct net_device *dev, + struct ethtool_pauseparam *ecmd) +{ + struct bcm_enet_priv *priv; + + priv = netdev_priv(dev); + + if (priv->has_phy) { + if (ecmd->autoneg && (ecmd->rx_pause != ecmd->tx_pause)) { + /* asymetric pause mode not supported, + * actually possible but integrated PHY has RO + * asym_pause bit */ + return -EINVAL; + } + } else { + /* no pause autoneg on direct mii connection */ + if (ecmd->autoneg) + return -EINVAL; + } + + priv->pause_auto = ecmd->autoneg; + priv->pause_rx = ecmd->rx_pause; + priv->pause_tx = ecmd->tx_pause; + + return 0; +} + +static struct ethtool_ops bcm_enet_ethtool_ops = { + .get_strings = bcm_enet_get_strings, + .get_stats_count = bcm_enet_get_stats_count, + .get_ethtool_stats = bcm_enet_get_ethtool_stats, + .get_settings = bcm_enet_get_settings, + .set_settings = bcm_enet_set_settings, + .get_drvinfo = bcm_enet_get_drvinfo, + .get_link = ethtool_op_get_link, + .get_ringparam = bcm_enet_get_ringparam, + .set_ringparam = bcm_enet_set_ringparam, + .get_pauseparam = bcm_enet_get_pauseparam, + .set_pauseparam = bcm_enet_set_pauseparam, +}; + +static int bcm_enet_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) +{ + struct bcm_enet_priv *priv; + + priv = netdev_priv(dev); + if (priv->has_phy) { + if (!priv->phydev) + return -ENODEV; + return phy_mii_ioctl(priv->phydev, if_mii(rq), cmd); + } else { + struct mii_if_info mii; + + mii.dev = dev; + mii.mdio_read = bcm_enet_mdio_read_mii; + mii.mdio_write = bcm_enet_mdio_write_mii; + mii.phy_id = 0; + mii.phy_id_mask = 0x3f; + mii.reg_num_mask = 0x1f; + return generic_mii_ioctl(&mii, if_mii(rq), cmd, NULL); + } +} + +/* + * calculate actual hardware mtu + */ +static int compute_hw_mtu(struct bcm_enet_priv *priv, int mtu) +{ + int actual_mtu; + + actual_mtu = mtu; + + /* add ethernet header + vlan tag size */ + actual_mtu += VLAN_ETH_HLEN; + + if (actual_mtu < 64 || actual_mtu > BCMENET_MAX_MTU) + return -EINVAL; + + /* + * setup maximum size before we get overflow mark in + * descriptor, note that this will not prevent reception of + * big frames, they will be split into multiple buffers + * anyway + */ + priv->hw_mtu = actual_mtu; + + /* + * align rx buffer size to dma burst len, account FCS since + * it's appended + */ + priv->rx_skb_size = ALIGN(actual_mtu + ETH_FCS_LEN, + BCMENET_DMA_MAXBURST * 4); + return 0; +} + +/* + * adjust mtu, can't be called while device is running + */ +static int bcm_enet_change_mtu(struct net_device *dev, int new_mtu) +{ + int ret; + + if (netif_running(dev)) + return -EBUSY; + + ret = compute_hw_mtu(netdev_priv(dev), new_mtu); + if (ret) + return ret; + dev->mtu = new_mtu; + return 0; +} + +/* + * preinit hardware to allow mii operation while device is down + */ +static void bcm_enet_hw_preinit(struct bcm_enet_priv *priv) +{ + u32 val; + int limit; + + /* make sure mac is disabled */ + bcm_enet_disable_mac(priv); + + /* soft reset mac */ + val = ENET_CTL_SRESET_MASK; + enet_writel(priv, val, ENET_CTL_REG); + wmb(); + + limit = 1000; + do { + val = enet_readl(priv, ENET_CTL_REG); + if (!(val & ENET_CTL_SRESET_MASK)) + break; + udelay(1); + } while (limit--); + + /* select correct mii interface */ + val = enet_readl(priv, ENET_CTL_REG); + if (priv->use_external_mii) + val |= ENET_CTL_EPHYSEL_MASK; + else + val &= ~ENET_CTL_EPHYSEL_MASK; + enet_writel(priv, val, ENET_CTL_REG); + + /* turn on mdc clock */ + enet_writel(priv, (0x1f << ENET_MIISC_MDCFREQDIV_SHIFT) | + ENET_MIISC_PREAMBLEEN_MASK, ENET_MIISC_REG); + + /* set mib counters to self-clear when read */ + val = enet_readl(priv, ENET_MIBCTL_REG); + val |= ENET_MIBCTL_RDCLEAR_MASK; + enet_writel(priv, val, ENET_MIBCTL_REG); +} + +static const struct net_device_ops bcm_enet_ops = { + .ndo_open = bcm_enet_open, + .ndo_stop = bcm_enet_stop, + .ndo_start_xmit = bcm_enet_start_xmit, + .ndo_get_stats = bcm_enet_get_stats, + .ndo_set_mac_address = bcm_enet_set_mac_address, + .ndo_set_multicast_list = bcm_enet_set_multicast_list, + .ndo_do_ioctl = bcm_enet_ioctl, + .ndo_change_mtu = bcm_enet_change_mtu, +#ifdef CONFIG_NET_POLL_CONTROLLER + .ndo_poll_controller = bcm_enet_netpoll, +#endif +}; + +/* + * allocate netdevice, request register memory and register device. + */ +static int __devinit bcm_enet_probe(struct platform_device *pdev) +{ + struct bcm_enet_priv *priv; + struct net_device *dev; + struct bcm63xx_enet_platform_data *pd; + struct resource *res_mem, *res_irq, *res_irq_rx, *res_irq_tx; + struct mii_bus *bus; + const char *clk_name; + unsigned int iomem_size; + int i, ret; + + /* stop if shared driver failed, assume driver->probe will be + * called in the same order we register devices (correct ?) */ + if (!bcm_enet_shared_base) + return -ENODEV; + + res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); + res_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); + res_irq_rx = platform_get_resource(pdev, IORESOURCE_IRQ, 1); + res_irq_tx = platform_get_resource(pdev, IORESOURCE_IRQ, 2); + if (!res_mem || !res_irq || !res_irq_rx || !res_irq_tx) + return -ENODEV; + + ret = 0; + dev = alloc_etherdev(sizeof(*priv)); + if (!dev) + return -ENOMEM; + priv = netdev_priv(dev); + memset(priv, 0, sizeof(*priv)); + + ret = compute_hw_mtu(priv, dev->mtu); + if (ret) + goto out; + + iomem_size = res_mem->end - res_mem->start + 1; + if (!request_mem_region(res_mem->start, iomem_size, "bcm63xx_enet")) { + ret = -EBUSY; + goto out; + } + + priv->base = ioremap(res_mem->start, iomem_size); + if (priv->base == NULL) { + ret = -ENOMEM; + goto out_release_mem; + } + dev->irq = priv->irq = res_irq->start; + priv->irq_rx = res_irq_rx->start; + priv->irq_tx = res_irq_tx->start; + priv->mac_id = pdev->id; + + /* get rx & tx dma channel id for this mac */ + if (priv->mac_id == 0) { + priv->rx_chan = 0; + priv->tx_chan = 1; + clk_name = "enet0"; + } else { + priv->rx_chan = 2; + priv->tx_chan = 3; + clk_name = "enet1"; + } + + priv->mac_clk = clk_get(&pdev->dev, clk_name); + if (IS_ERR(priv->mac_clk)) { + ret = PTR_ERR(priv->mac_clk); + goto out_unmap; + } + clk_enable(priv->mac_clk); + + /* initialize default and fetch platform data */ + priv->rx_ring_size = BCMENET_DEF_RX_DESC; + priv->tx_ring_size = BCMENET_DEF_TX_DESC; + + pd = pdev->dev.platform_data; + if (pd) { + memcpy(dev->dev_addr, pd->mac_addr, ETH_ALEN); + priv->has_phy = pd->has_phy; + priv->phy_id = pd->phy_id; + priv->has_phy_interrupt = pd->has_phy_interrupt; + priv->phy_interrupt = pd->phy_interrupt; + priv->use_external_mii = !pd->use_internal_phy; + priv->pause_auto = pd->pause_auto; + priv->pause_rx = pd->pause_rx; + priv->pause_tx = pd->pause_tx; + priv->force_duplex_full = pd->force_duplex_full; + priv->force_speed_100 = pd->force_speed_100; + } + + if (priv->mac_id == 0 && priv->has_phy && !priv->use_external_mii) { + /* using internal PHY, enable clock */ + priv->phy_clk = clk_get(&pdev->dev, "ephy"); + if (IS_ERR(priv->phy_clk)) { + ret = PTR_ERR(priv->phy_clk); + priv->phy_clk = NULL; + goto out_put_clk_mac; + } + clk_enable(priv->phy_clk); + } + + /* do minimal hardware init to be able to probe mii bus */ + bcm_enet_hw_preinit(priv); + + /* MII bus registration */ + if (priv->has_phy) { + + priv->mii_bus = mdiobus_alloc(); + if (!priv->mii_bus) { + ret = -ENOMEM; + goto out_uninit_hw; + } + + bus = priv->mii_bus; + bus->name = "bcm63xx_enet MII bus"; + bus->parent = &pdev->dev; + bus->priv = priv; + bus->read = bcm_enet_mdio_read_phylib; + bus->write = bcm_enet_mdio_write_phylib; + sprintf(bus->id, "%d", priv->mac_id); + + /* only probe bus where we think the PHY is, because + * the mdio read operation return 0 instead of 0xffff + * if a slave is not present on hw */ + bus->phy_mask = ~(1 << priv->phy_id); + + bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL); + if (!bus->irq) { + ret = -ENOMEM; + goto out_free_mdio; + } + + if (priv->has_phy_interrupt) + bus->irq[priv->phy_id] = priv->phy_interrupt; + else + bus->irq[priv->phy_id] = PHY_POLL; + + ret = mdiobus_register(bus); + if (ret) { + dev_err(&pdev->dev, "unable to register mdio bus\n"); + goto out_free_mdio; + } + } else { + + /* run platform code to initialize PHY device */ + if (pd->mii_config && + pd->mii_config(dev, 1, bcm_enet_mdio_read_mii, + bcm_enet_mdio_write_mii)) { + dev_err(&pdev->dev, "unable to configure mdio bus\n"); + goto out_uninit_hw; + } + } + + spin_lock_init(&priv->rx_lock); + + /* init rx timeout (used for oom) */ + init_timer(&priv->rx_timeout); + priv->rx_timeout.function = bcm_enet_refill_rx_timer; + priv->rx_timeout.data = (unsigned long)dev; + + /* init the mib update lock&work */ + mutex_init(&priv->mib_update_lock); + INIT_WORK(&priv->mib_update_task, bcm_enet_update_mib_counters_defer); + + /* zero mib counters */ + for (i = 0; i < ENET_MIB_REG_COUNT; i++) + enet_writel(priv, 0, ENET_MIB_REG(i)); + + /* register netdevice */ + dev->netdev_ops = &bcm_enet_ops; + netif_napi_add(dev, &priv->napi, bcm_enet_poll, 16); + + SET_ETHTOOL_OPS(dev, &bcm_enet_ethtool_ops); + + ret = register_netdev(dev); + if (ret) + goto out_unregister_mdio; + + netif_carrier_off(dev); + platform_set_drvdata(pdev, dev); + priv->pdev = pdev; + priv->net_dev = dev; + SET_NETDEV_DEV(dev, &pdev->dev); + + return 0; + +out_unregister_mdio: + if (priv->mii_bus) { + mdiobus_unregister(priv->mii_bus); + kfree(priv->mii_bus->irq); + } + +out_free_mdio: + if (priv->mii_bus) + mdiobus_free(priv->mii_bus); + +out_uninit_hw: + /* turn off mdc clock */ + enet_writel(priv, 0, ENET_MIISC_REG); + if (priv->phy_clk) { + clk_disable(priv->phy_clk); + clk_put(priv->phy_clk); + } + +out_put_clk_mac: + clk_disable(priv->mac_clk); + clk_put(priv->mac_clk); + +out_unmap: + iounmap(priv->base); + +out_release_mem: + release_mem_region(res_mem->start, iomem_size); +out: + free_netdev(dev); + return ret; +} + + +/* + * exit func, stops hardware and unregisters netdevice + */ +static int __devexit bcm_enet_remove(struct platform_device *pdev) +{ + struct bcm_enet_priv *priv; + struct net_device *dev; + struct resource *res; + + /* stop netdevice */ + dev = platform_get_drvdata(pdev); + priv = netdev_priv(dev); + unregister_netdev(dev); + + /* turn off mdc clock */ + enet_writel(priv, 0, ENET_MIISC_REG); + + if (priv->has_phy) { + mdiobus_unregister(priv->mii_bus); + kfree(priv->mii_bus->irq); + mdiobus_free(priv->mii_bus); + } else { + struct bcm63xx_enet_platform_data *pd; + + pd = pdev->dev.platform_data; + if (pd && pd->mii_config) + pd->mii_config(dev, 0, bcm_enet_mdio_read_mii, + bcm_enet_mdio_write_mii); + } + + /* release device resources */ + iounmap(priv->base); + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + release_mem_region(res->start, res->end - res->start + 1); + + /* disable hw block clocks */ + if (priv->phy_clk) { + clk_disable(priv->phy_clk); + clk_put(priv->phy_clk); + } + clk_disable(priv->mac_clk); + clk_put(priv->mac_clk); + + free_netdev(dev); + return 0; +} + +struct platform_driver bcm63xx_enet_driver = { + .probe = bcm_enet_probe, + .remove = __devexit_p(bcm_enet_remove), + .driver = { + .name = "bcm63xx_enet", + .owner = THIS_MODULE, + }, +}; + +/* + * reserve & remap memory space shared between all macs + */ +static int __devinit bcm_enet_shared_probe(struct platform_device *pdev) +{ + struct resource *res; + unsigned int iomem_size; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) + return -ENODEV; + + iomem_size = res->end - res->start + 1; + if (!request_mem_region(res->start, iomem_size, "bcm63xx_enet_dma")) + return -EBUSY; + + bcm_enet_shared_base = ioremap(res->start, iomem_size); + if (!bcm_enet_shared_base) { + release_mem_region(res->start, iomem_size); + return -ENOMEM; + } + return 0; +} + +static int __devexit bcm_enet_shared_remove(struct platform_device *pdev) +{ + struct resource *res; + + iounmap(bcm_enet_shared_base); + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + release_mem_region(res->start, res->end - res->start + 1); + return 0; +} + +/* + * this "shared" driver is needed because both macs share a single + * address space + */ +struct platform_driver bcm63xx_enet_shared_driver = { + .probe = bcm_enet_shared_probe, + .remove = __devexit_p(bcm_enet_shared_remove), + .driver = { + .name = "bcm63xx_enet_shared", + .owner = THIS_MODULE, + }, +}; + +/* + * entry point + */ +static int __init bcm_enet_init(void) +{ + int ret; + + ret = platform_driver_register(&bcm63xx_enet_shared_driver); + if (ret) + return ret; + + ret = platform_driver_register(&bcm63xx_enet_driver); + if (ret) + platform_driver_unregister(&bcm63xx_enet_shared_driver); + + return ret; +} + +static void __exit bcm_enet_exit(void) +{ + platform_driver_unregister(&bcm63xx_enet_driver); + platform_driver_unregister(&bcm63xx_enet_shared_driver); +} + + +module_init(bcm_enet_init); +module_exit(bcm_enet_exit); + +MODULE_DESCRIPTION("BCM63xx internal ethernet mac driver"); +MODULE_AUTHOR("Maxime Bizon "); +MODULE_LICENSE("GPL"); --- /dev/null +++ b/drivers/net/bcm63xx_enet.h @@ -0,0 +1,303 @@ +#ifndef BCM63XX_ENET_H_ +#define BCM63XX_ENET_H_ + +#include +#include +#include +#include +#include + +#include +#include +#include + +/* default number of descriptor */ +#define BCMENET_DEF_RX_DESC 64 +#define BCMENET_DEF_TX_DESC 32 + +/* maximum burst len for dma (4 bytes unit) */ +#define BCMENET_DMA_MAXBURST 16 + +/* tx transmit threshold (4 bytes unit), fifo is 256 bytes, the value + * must be low enough so that a DMA transfer of above burst length can + * not overflow the fifo */ +#define BCMENET_TX_FIFO_TRESH 32 + +/* + * hardware maximum rx/tx packet size including FCS, max mtu is + * actually 2047, but if we set max rx size register to 2047 we won't + * get overflow information if packet size is 2048 or above + */ +#define BCMENET_MAX_MTU 2046 + +/* + * rx/tx dma descriptor + */ +struct bcm_enet_desc { + u32 len_stat; + u32 address; +}; + +#define DMADESC_LENGTH_SHIFT 16 +#define DMADESC_LENGTH_MASK (0xfff << DMADESC_LENGTH_SHIFT) +#define DMADESC_OWNER_MASK (1 << 15) +#define DMADESC_EOP_MASK (1 << 14) +#define DMADESC_SOP_MASK (1 << 13) +#define DMADESC_ESOP_MASK (DMADESC_EOP_MASK | DMADESC_SOP_MASK) +#define DMADESC_WRAP_MASK (1 << 12) + +#define DMADESC_UNDER_MASK (1 << 9) +#define DMADESC_APPEND_CRC (1 << 8) +#define DMADESC_OVSIZE_MASK (1 << 4) +#define DMADESC_RXER_MASK (1 << 2) +#define DMADESC_CRC_MASK (1 << 1) +#define DMADESC_OV_MASK (1 << 0) +#define DMADESC_ERR_MASK (DMADESC_UNDER_MASK | \ + DMADESC_OVSIZE_MASK | \ + DMADESC_RXER_MASK | \ + DMADESC_CRC_MASK | \ + DMADESC_OV_MASK) + + +/* + * MIB Counters register definitions +*/ +#define ETH_MIB_TX_GD_OCTETS 0 +#define ETH_MIB_TX_GD_PKTS 1 +#define ETH_MIB_TX_ALL_OCTETS 2 +#define ETH_MIB_TX_ALL_PKTS 3 +#define ETH_MIB_TX_BRDCAST 4 +#define ETH_MIB_TX_MULT 5 +#define ETH_MIB_TX_64 6 +#define ETH_MIB_TX_65_127 7 +#define ETH_MIB_TX_128_255 8 +#define ETH_MIB_TX_256_511 9 +#define ETH_MIB_TX_512_1023 10 +#define ETH_MIB_TX_1024_MAX 11 +#define ETH_MIB_TX_JAB 12 +#define ETH_MIB_TX_OVR 13 +#define ETH_MIB_TX_FRAG 14 +#define ETH_MIB_TX_UNDERRUN 15 +#define ETH_MIB_TX_COL 16 +#define ETH_MIB_TX_1_COL 17 +#define ETH_MIB_TX_M_COL 18 +#define ETH_MIB_TX_EX_COL 19 +#define ETH_MIB_TX_LATE 20 +#define ETH_MIB_TX_DEF 21 +#define ETH_MIB_TX_CRS 22 +#define ETH_MIB_TX_PAUSE 23 + +#define ETH_MIB_RX_GD_OCTETS 32 +#define ETH_MIB_RX_GD_PKTS 33 +#define ETH_MIB_RX_ALL_OCTETS 34 +#define ETH_MIB_RX_ALL_PKTS 35 +#define ETH_MIB_RX_BRDCAST 36 +#define ETH_MIB_RX_MULT 37 +#define ETH_MIB_RX_64 38 +#define ETH_MIB_RX_65_127 39 +#define ETH_MIB_RX_128_255 40 +#define ETH_MIB_RX_256_511 41 +#define ETH_MIB_RX_512_1023 42 +#define ETH_MIB_RX_1024_MAX 43 +#define ETH_MIB_RX_JAB 44 +#define ETH_MIB_RX_OVR 45 +#define ETH_MIB_RX_FRAG 46 +#define ETH_MIB_RX_DROP 47 +#define ETH_MIB_RX_CRC_ALIGN 48 +#define ETH_MIB_RX_UND 49 +#define ETH_MIB_RX_CRC 50 +#define ETH_MIB_RX_ALIGN 51 +#define ETH_MIB_RX_SYM 52 +#define ETH_MIB_RX_PAUSE 53 +#define ETH_MIB_RX_CNTRL 54 + + +struct bcm_enet_mib_counters { + u64 tx_gd_octets; + u32 tx_gd_pkts; + u32 tx_all_octets; + u32 tx_all_pkts; + u32 tx_brdcast; + u32 tx_mult; + u32 tx_64; + u32 tx_65_127; + u32 tx_128_255; + u32 tx_256_511; + u32 tx_512_1023; + u32 tx_1024_max; + u32 tx_jab; + u32 tx_ovr; + u32 tx_frag; + u32 tx_underrun; + u32 tx_col; + u32 tx_1_col; + u32 tx_m_col; + u32 tx_ex_col; + u32 tx_late; + u32 tx_def; + u32 tx_crs; + u32 tx_pause; + u64 rx_gd_octets; + u32 rx_gd_pkts; + u32 rx_all_octets; + u32 rx_all_pkts; + u32 rx_brdcast; + u32 rx_mult; + u32 rx_64; + u32 rx_65_127; + u32 rx_128_255; + u32 rx_256_511; + u32 rx_512_1023; + u32 rx_1024_max; + u32 rx_jab; + u32 rx_ovr; + u32 rx_frag; + u32 rx_drop; + u32 rx_crc_align; + u32 rx_und; + u32 rx_crc; + u32 rx_align; + u32 rx_sym; + u32 rx_pause; + u32 rx_cntrl; +}; + + +struct bcm_enet_priv { + + /* mac id (from platform device id) */ + int mac_id; + + /* base remapped address of device */ + void __iomem *base; + + /* mac irq, rx_dma irq, tx_dma irq */ + int irq; + int irq_rx; + int irq_tx; + + /* hw view of rx & tx dma ring */ + dma_addr_t rx_desc_dma; + dma_addr_t tx_desc_dma; + + /* allocated size (in bytes) for rx & tx dma ring */ + unsigned int rx_desc_alloc_size; + unsigned int tx_desc_alloc_size; + + + struct napi_struct napi; + + /* dma channel id for rx */ + int rx_chan; + + /* number of dma desc in rx ring */ + int rx_ring_size; + + /* cpu view of rx dma ring */ + struct bcm_enet_desc *rx_desc_cpu; + + /* current number of armed descriptor given to hardware for rx */ + int rx_desc_count; + + /* next rx descriptor to fetch from hardware */ + int rx_curr_desc; + + /* next dirty rx descriptor to refill */ + int rx_dirty_desc; + + /* size of allocated rx skbs */ + unsigned int rx_skb_size; + + /* list of skb given to hw for rx */ + struct sk_buff **rx_skb; + + /* used when rx skb allocation failed, so we defer rx queue + * refill */ + struct timer_list rx_timeout; + + /* lock rx_timeout against rx normal operation */ + spinlock_t rx_lock; + + + /* dma channel id for tx */ + int tx_chan; + + /* number of dma desc in tx ring */ + int tx_ring_size; + + /* cpu view of rx dma ring */ + struct bcm_enet_desc *tx_desc_cpu; + + /* number of available descriptor for tx */ + int tx_desc_count; + + /* next tx descriptor avaiable */ + int tx_curr_desc; + + /* next dirty tx descriptor to reclaim */ + int tx_dirty_desc; + + /* list of skb given to hw for tx */ + struct sk_buff **tx_skb; + + /* lock used by tx reclaim and xmit */ + spinlock_t tx_lock; + + + /* set if internal phy is ignored and external mii interface + * is selected */ + int use_external_mii; + + /* set if a phy is connected, phy address must be known, + * probing is not possible */ + int has_phy; + int phy_id; + + /* set if connected phy has an associated irq */ + int has_phy_interrupt; + int phy_interrupt; + + /* used when a phy is connected (phylib used) */ + struct mii_bus *mii_bus; + struct phy_device *phydev; + int old_link; + int old_duplex; + int old_pause; + + /* used when no phy is connected */ + int force_speed_100; + int force_duplex_full; + + /* pause parameters */ + int pause_auto; + int pause_rx; + int pause_tx; + + /* stats */ + struct net_device_stats stats; + struct bcm_enet_mib_counters mib; + + /* after mib interrupt, mib registers update is done in this + * work queue */ + struct work_struct mib_update_task; + + /* lock mib update between userspace request and workqueue */ + struct mutex mib_update_lock; + + /* mac clock */ + struct clk *mac_clk; + + /* phy clock if internal phy is used */ + struct clk *phy_clk; + + /* network device reference */ + struct net_device *net_dev; + + /* platform device reference */ + struct platform_device *pdev; + + /* maximum hardware transmit/receive size */ + unsigned int hw_mtu; +}; + +#endif /* ! BCM63XX_ENET_H_ */ From ralf@linux-mips.org Wed Jul 1 19:10:28 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 01 Jul 2009 19:10:31 +0200 (CEST) Received: (from localhost user: 'ralf' uid#500 fake: STDIN (ralf@eddie.linux-mips.org)) by ftp.linux-mips.org id S1491877AbZGARHL for <"|/home/ecartis/ecartis -s linux-mips">; Wed, 1 Jul 2009 19:07:11 +0200 Message-Id: <20090701120940.096077223@linux-mips.org> User-Agent: quilt/0.47-1 Date: Wed, 01 Jul 2009 12:29:36 +0100 From: Ralf Baechle To: linux-mips@linux-mips.org, netdev@vger.kernel.org Cc: Maxime Bizon , Florian Fainelli Subject: [patch 10/12] MIPS: BCM63XX: Add integrated ethernet PHY support for phylib. References: <20090701112926.825088732@linux-mips.org> Content-Disposition: inline; filename=0010.patch Content-Length: 4776 Lines: 172 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-archive-position: 23576 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips From: Maxime Bizon Signed-off-by: Maxime Bizon Signed-off-by: Ralf Baechle drivers/net/phy/Kconfig | 6 ++ drivers/net/phy/Makefile | 1 drivers/net/phy/bcm63xx.c | 132 ++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 139 insertions(+) create mode 100644 drivers/net/phy/bcm63xx.c --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig @@ -56,6 +56,12 @@ config BROADCOM_PHY Currently supports the BCM5411, BCM5421, BCM5461, BCM5464, BCM5481 and BCM5482 PHYs. +config BCM63XX_PHY + tristate "Drivers for Broadcom 63xx SOCs internal PHY" + depends on BCM63XX + ---help--- + Currently supports the 6348 and 6358 PHYs. + config ICPLUS_PHY tristate "Drivers for ICPlus PHYs" ---help--- --- a/drivers/net/phy/Makefile +++ b/drivers/net/phy/Makefile @@ -11,6 +11,7 @@ obj-$(CONFIG_QSEMI_PHY) += qsemi.o obj-$(CONFIG_SMSC_PHY) += smsc.o obj-$(CONFIG_VITESSE_PHY) += vitesse.o obj-$(CONFIG_BROADCOM_PHY) += broadcom.o +obj-$(CONFIG_BCM63XX_PHY) += bcm63xx.o obj-$(CONFIG_ICPLUS_PHY) += icplus.o obj-$(CONFIG_REALTEK_PHY) += realtek.o obj-$(CONFIG_LSI_ET1011C_PHY) += et1011c.o --- /dev/null +++ b/drivers/net/phy/bcm63xx.c @@ -0,0 +1,132 @@ +/* + * Driver for Broadcom 63xx SOCs integrated PHYs + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ +#include +#include + +#define MII_BCM63XX_IR 0x1a /* interrupt register */ +#define MII_BCM63XX_IR_EN 0x4000 /* global interrupt enable */ +#define MII_BCM63XX_IR_DUPLEX 0x0800 /* duplex changed */ +#define MII_BCM63XX_IR_SPEED 0x0400 /* speed changed */ +#define MII_BCM63XX_IR_LINK 0x0200 /* link changed */ +#define MII_BCM63XX_IR_GMASK 0x0100 /* global interrupt mask */ + +MODULE_DESCRIPTION("Broadcom 63xx internal PHY driver"); +MODULE_AUTHOR("Maxime Bizon "); +MODULE_LICENSE("GPL"); + +static int bcm63xx_config_init(struct phy_device *phydev) +{ + int reg, err; + + reg = phy_read(phydev, MII_BCM63XX_IR); + if (reg < 0) + return reg; + + /* Mask interrupts globally. */ + reg |= MII_BCM63XX_IR_GMASK; + err = phy_write(phydev, MII_BCM63XX_IR, reg); + if (err < 0) + return err; + + /* Unmask events we are interested in */ + reg = ~(MII_BCM63XX_IR_DUPLEX | + MII_BCM63XX_IR_SPEED | + MII_BCM63XX_IR_LINK) | + MII_BCM63XX_IR_EN; + err = phy_write(phydev, MII_BCM63XX_IR, reg); + if (err < 0) + return err; + return 0; +} + +static int bcm63xx_ack_interrupt(struct phy_device *phydev) +{ + int reg; + + /* Clear pending interrupts. */ + reg = phy_read(phydev, MII_BCM63XX_IR); + if (reg < 0) + return reg; + + return 0; +} + +static int bcm63xx_config_intr(struct phy_device *phydev) +{ + int reg, err; + + reg = phy_read(phydev, MII_BCM63XX_IR); + if (reg < 0) + return reg; + + if (phydev->interrupts == PHY_INTERRUPT_ENABLED) + reg &= ~MII_BCM63XX_IR_GMASK; + else + reg |= MII_BCM63XX_IR_GMASK; + + err = phy_write(phydev, MII_BCM63XX_IR, reg); + return err; +} + +static struct phy_driver bcm63xx_1_driver = { + .phy_id = 0x00406000, + .phy_id_mask = 0xfffffc00, + .name = "Broadcom BCM63XX (1)", + /* ASYM_PAUSE bit is marked RO in datasheet, so don't cheat */ + .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause), + .flags = PHY_HAS_INTERRUPT, + .config_init = bcm63xx_config_init, + .config_aneg = genphy_config_aneg, + .read_status = genphy_read_status, + .ack_interrupt = bcm63xx_ack_interrupt, + .config_intr = bcm63xx_config_intr, + .driver = { .owner = THIS_MODULE }, +}; + +/* same phy as above, with just a different OUI */ +static struct phy_driver bcm63xx_2_driver = { + .phy_id = 0x002bdc00, + .phy_id_mask = 0xfffffc00, + .name = "Broadcom BCM63XX (2)", + .features = (PHY_BASIC_FEATURES | SUPPORTED_Pause), + .flags = PHY_HAS_INTERRUPT, + .config_init = bcm63xx_config_init, + .config_aneg = genphy_config_aneg, + .read_status = genphy_read_status, + .ack_interrupt = bcm63xx_ack_interrupt, + .config_intr = bcm63xx_config_intr, + .driver = { .owner = THIS_MODULE }, +}; + +static int __init bcm63xx_phy_init(void) +{ + int ret; + + ret = phy_driver_register(&bcm63xx_1_driver); + if (ret) + goto out_63xx_1; + ret = phy_driver_register(&bcm63xx_2_driver); + if (ret) + goto out_63xx_2; + return ret; + +out_63xx_2: + phy_driver_unregister(&bcm63xx_1_driver); +out_63xx_1: + return ret; +} + +static void __exit bcm63xx_phy_exit(void) +{ + phy_driver_unregister(&bcm63xx_1_driver); + phy_driver_unregister(&bcm63xx_2_driver); +} + +module_init(bcm63xx_phy_init); +module_exit(bcm63xx_phy_exit); From ralf@linux-mips.org Wed Jul 1 19:10:48 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 01 Jul 2009 19:10:53 +0200 (CEST) Received: (from localhost user: 'ralf' uid#500 fake: STDIN (ralf@eddie.linux-mips.org)) by ftp.linux-mips.org id S1491878AbZGARHL for <"|/home/ecartis/ecartis -s linux-mips">; Wed, 1 Jul 2009 19:07:11 +0200 Message-Id: <20090701120940.183856745@linux-mips.org> User-Agent: quilt/0.47-1 Date: Wed, 01 Jul 2009 12:29:37 +0100 From: Ralf Baechle To: linux-mips@linux-mips.org Cc: Maxime Bizon , Florian Fainelli Subject: [patch 11/12] MIPS: BCM63XX: Add board support code. References: <20090701112926.825088732@linux-mips.org> Content-Disposition: inline; filename=0011.patch Content-Length: 16508 Lines: 741 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-archive-position: 23577 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips From: Maxime Bizon BCM6348-based: - 96348R - 96348gw - 96348GW-10 - 96348GW-11 - 96348GW-A - Sagem F@2404 - Davolink DV201AMR BCM6358-based: - 96358vw - 96358vw2 - Pirelli/Alice AGPFS0 Signed-off-by: Maxime Bizon Signed-off-by: Florian Fainelli Signed-off-by: Ralf Baechle arch/mips/bcm63xx/Kconfig | 2 arch/mips/bcm63xx/Makefile | 2 arch/mips/bcm63xx/boards/Kconfig | 11 arch/mips/bcm63xx/boards/Makefile | 3 arch/mips/bcm63xx/boards/board_bcm963xx.c | 532 ++++++++++++++++++++ arch/mips/bcm63xx/prom.c | 4 arch/mips/bcm63xx/setup.c | 16 arch/mips/include/asm/mach-bcm63xx/bcm63xx_board.h | 12 arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h | 50 + 9 files changed, 630 insertions(+), 2 deletions(-) create mode 100644 arch/mips/bcm63xx/boards/Kconfig create mode 100644 arch/mips/bcm63xx/boards/Makefile create mode 100644 arch/mips/bcm63xx/boards/board_bcm963xx.c create mode 100644 arch/mips/include/asm/mach-bcm63xx/bcm63xx_board.h create mode 100644 arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h --- a/arch/mips/bcm63xx/Kconfig +++ b/arch/mips/bcm63xx/Kconfig @@ -17,3 +17,5 @@ config BCM63XX_CPU_6358 select USB_ARCH_HAS_EHCI select USB_EHCI_BIG_ENDIAN_MMIO endmenu + +source "arch/mips/bcm63xx/boards/Kconfig" --- a/arch/mips/bcm63xx/Makefile +++ b/arch/mips/bcm63xx/Makefile @@ -6,4 +6,6 @@ obj-y += dev-usb-ehci.o obj-y += dev-enet.o obj-$(CONFIG_EARLY_PRINTK) += early_printk.o +obj-y += boards/ + EXTRA_CFLAGS += -Werror --- /dev/null +++ b/arch/mips/bcm63xx/boards/Kconfig @@ -0,0 +1,11 @@ +choice + prompt "Board support" + depends on BCM63XX + default BOARD_BCM963XX + +config BOARD_BCM963XX + bool "Generic Broadcom 963xx boards" + select SSB + help + +endchoice --- /dev/null +++ b/arch/mips/bcm63xx/boards/Makefile @@ -0,0 +1,3 @@ +obj-$(CONFIG_BOARD_BCM963XX) += board_bcm963xx.o + +EXTRA_CFLAGS += -Werror --- /dev/null +++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c @@ -0,0 +1,532 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2008 Maxime Bizon + * Copyright (C) 2008 Florian Fainelli + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define PFX "board_bcm963xx: " + +static struct bcm963xx_nvram nvram; +static unsigned int mac_addr_used; +static struct board_info board; + +/* + * known 6348 boards + */ +#ifdef CONFIG_BCM63XX_CPU_6348 +static struct board_info __initdata board_96348r = { + .name = "96348R", + .expected_cpu_id = 0x6348, + + .has_enet0 = 1, + .has_pci = 1, + + .enet0 = { + .has_phy = 1, + .use_internal_phy = 1, + }, +}; + +static struct board_info __initdata board_96348gw_10 = { + .name = "96348GW-10", + .expected_cpu_id = 0x6348, + + .has_enet0 = 1, + .has_enet1 = 1, + .has_pci = 1, + + .enet0 = { + .has_phy = 1, + .use_internal_phy = 1, + }, + .enet1 = { + .force_speed_100 = 1, + .force_duplex_full = 1, + }, + + .has_ohci0 = 1, + .has_pccard = 1, + .has_ehci0 = 1, +}; + +static struct board_info __initdata board_96348gw_11 = { + .name = "96348GW-11", + .expected_cpu_id = 0x6348, + + .has_enet0 = 1, + .has_enet1 = 1, + .has_pci = 1, + + .enet0 = { + .has_phy = 1, + .use_internal_phy = 1, + }, + + .enet1 = { + .force_speed_100 = 1, + .force_duplex_full = 1, + }, + + + .has_ohci0 = 1, + .has_pccard = 1, + .has_ehci0 = 1, +}; + +static struct board_info __initdata board_96348gw = { + .name = "96348GW", + .expected_cpu_id = 0x6348, + + .has_enet0 = 1, + .has_enet1 = 1, + .has_pci = 1, + + .enet0 = { + .has_phy = 1, + .use_internal_phy = 1, + }, + .enet1 = { + .force_speed_100 = 1, + .force_duplex_full = 1, + }, + + .has_ohci0 = 1, +}; + +static struct board_info __initdata board_FAST2404 = { + .name = "F@ST2404", + .expected_cpu_id = 0x6348, + + .has_enet0 = 1, + .has_enet1 = 1, + .has_pci = 1, + + .enet0 = { + .has_phy = 1, + .use_internal_phy = 1, + }, + + .enet1 = { + .force_speed_100 = 1, + .force_duplex_full = 1, + }, + + + .has_ohci0 = 1, + .has_pccard = 1, + .has_ehci0 = 1, +}; + +static struct board_info __initdata board_DV201AMR = { + .name = "DV201AMR", + .expected_cpu_id = 0x6348, + + .has_pci = 1, + .has_ohci0 = 1, + + .has_enet0 = 1, + .has_enet1 = 1, + .enet0 = { + .has_phy = 1, + .use_internal_phy = 1, + }, + .enet1 = { + .force_speed_100 = 1, + .force_duplex_full = 1, + }, +}; + +static struct board_info __initdata board_96348gw_a = { + .name = "96348GW-A", + .expected_cpu_id = 0x6348, + + .has_enet0 = 1, + .has_enet1 = 1, + .has_pci = 1, + + .enet0 = { + .has_phy = 1, + .use_internal_phy = 1, + }, + .enet1 = { + .force_speed_100 = 1, + .force_duplex_full = 1, + }, + + .has_ohci0 = 1, +}; +#endif + +/* + * known 6358 boards + */ +#ifdef CONFIG_BCM63XX_CPU_6358 +static struct board_info __initdata board_96358vw = { + .name = "96358VW", + .expected_cpu_id = 0x6358, + + .has_enet0 = 1, + .has_enet1 = 1, + .has_pci = 1, + + .enet0 = { + .has_phy = 1, + .use_internal_phy = 1, + }, + + .enet1 = { + .force_speed_100 = 1, + .force_duplex_full = 1, + }, + + + .has_ohci0 = 1, + .has_pccard = 1, + .has_ehci0 = 1, +}; + +static struct board_info __initdata board_96358vw2 = { + .name = "96358VW2", + .expected_cpu_id = 0x6358, + + .has_enet0 = 1, + .has_enet1 = 1, + .has_pci = 1, + + .enet0 = { + .has_phy = 1, + .use_internal_phy = 1, + }, + + .enet1 = { + .force_speed_100 = 1, + .force_duplex_full = 1, + }, + + + .has_ohci0 = 1, + .has_pccard = 1, + .has_ehci0 = 1, +}; + +static struct board_info __initdata board_AGPFS0 = { + .name = "AGPF-S0", + .expected_cpu_id = 0x6358, + + .has_enet0 = 1, + .has_enet1 = 1, + .has_pci = 1, + + .enet0 = { + .has_phy = 1, + .use_internal_phy = 1, + }, + + .enet1 = { + .force_speed_100 = 1, + .force_duplex_full = 1, + }, + + .has_ohci0 = 1, + .has_ehci0 = 1, +}; +#endif + +/* + * all boards + */ +static const struct board_info __initdata *bcm963xx_boards[] = { +#ifdef CONFIG_BCM63XX_CPU_6348 + &board_96348r, + &board_96348gw, + &board_96348gw_10, + &board_96348gw_11, + &board_FAST2404, + &board_DV201AMR, + &board_96348gw_a, +#endif + +#ifdef CONFIG_BCM63XX_CPU_6358 + &board_96358vw, + &board_96358vw2, + &board_AGPFS0, +#endif +}; + +/* + * early init callback, read nvram data from flash and checksum it + */ +void __init board_prom_init(void) +{ + unsigned int check_len, i; + u8 *boot_addr, *cfe, *p; + char cfe_version[32]; + u32 val; + + /* read base address of boot chip select (0) */ + val = bcm_mpi_readl(MPI_CSBASE_REG(0)); + val &= MPI_CSBASE_BASE_MASK; + boot_addr = (u8 *)KSEG1ADDR(val); + + /* dump cfe version */ + cfe = boot_addr + BCM963XX_CFE_VERSION_OFFSET; + if (!memcmp(cfe, "cfe-v", 5)) + snprintf(cfe_version, sizeof(cfe_version), "%u.%u.%u-%u.%u", + cfe[5], cfe[6], cfe[7], cfe[8], cfe[9]); + else + strcpy(cfe_version, "unknown"); + printk(KERN_INFO PFX "CFE version: %s\n", cfe_version); + + /* extract nvram data */ + memcpy(&nvram, boot_addr + BCM963XX_NVRAM_OFFSET, sizeof(nvram)); + + /* check checksum before using data */ + if (nvram.version <= 4) + check_len = offsetof(struct bcm963xx_nvram, checksum_old); + else + check_len = sizeof(nvram); + val = 0; + p = (u8 *)&nvram; + while (check_len--) + val += *p; + if (val) { + printk(KERN_ERR PFX "invalid nvram checksum\n"); + return; + } + + /* find board by name */ + for (i = 0; i < ARRAY_SIZE(bcm963xx_boards); i++) { + if (strncmp(nvram.name, bcm963xx_boards[i]->name, + sizeof(nvram.name))) + continue; + /* copy, board desc array is marked initdata */ + memcpy(&board, bcm963xx_boards[i], sizeof(board)); + break; + } + + /* bail out if board is not found, will complain later */ + if (!board.name[0]) { + char name[17]; + memcpy(name, nvram.name, 16); + name[16] = 0; + printk(KERN_ERR PFX "unknown bcm963xx board: %s\n", + name); + return; + } + + /* setup pin multiplexing depending on board enabled device, + * this has to be done this early since PCI init is done + * inside arch_initcall */ + val = 0; + + if (board.has_pci) { + bcm63xx_pci_enabled = 1; + if (BCMCPU_IS_6348()) + val |= GPIO_MODE_6348_G2_PCI; + } + + if (board.has_pccard) { + if (BCMCPU_IS_6348()) + val |= GPIO_MODE_6348_G1_MII_PCCARD; + } + + if (board.has_enet0 && !board.enet0.use_internal_phy) { + if (BCMCPU_IS_6348()) + val |= GPIO_MODE_6348_G3_EXT_MII | + GPIO_MODE_6348_G0_EXT_MII; + } + + if (board.has_enet1 && !board.enet1.use_internal_phy) { + if (BCMCPU_IS_6348()) + val |= GPIO_MODE_6348_G3_EXT_MII | + GPIO_MODE_6348_G0_EXT_MII; + } + + bcm_gpio_writel(val, GPIO_MODE_REG); +} + +/* + * second stage init callback, good time to panic if we couldn't + * identify on which board we're running since early printk is working + */ +void __init board_setup(void) +{ + if (!board.name[0]) + panic("unable to detect bcm963xx board"); + printk(KERN_INFO PFX "board name: %s\n", board.name); + + /* make sure we're running on expected cpu */ + if (bcm63xx_get_cpu_id() != board.expected_cpu_id) + panic("unexpected CPU for bcm963xx board"); +} + +/* + * return board name for /proc/cpuinfo + */ +const char *board_get_name(void) +{ + return board.name; +} + +/* + * register & return a new board mac address + */ +static int board_get_mac_address(u8 *mac) +{ + u8 *p; + int count; + + if (mac_addr_used >= nvram.mac_addr_count) { + printk(KERN_ERR PFX "not enough mac address\n"); + return -ENODEV; + } + + memcpy(mac, nvram.mac_addr_base, ETH_ALEN); + p = mac + ETH_ALEN - 1; + count = mac_addr_used; + + while (count--) { + do { + (*p)++; + if (*p != 0) + break; + p--; + } while (p != mac); + } + + if (p == mac) { + printk(KERN_ERR PFX "unable to fetch mac address\n"); + return -ENODEV; + } + + mac_addr_used++; + return 0; +} + +static struct mtd_partition mtd_partitions[] = { + { + .name = "cfe", + .offset = 0x0, + .size = 0x40000, + } +}; + +static struct physmap_flash_data flash_data = { + .width = 2, + .nr_parts = ARRAY_SIZE(mtd_partitions), + .parts = mtd_partitions, +}; + +static struct resource mtd_resources[] = { + { + .start = 0, /* filled at runtime */ + .end = 0, /* filled at runtime */ + .flags = IORESOURCE_MEM, + } +}; + +static struct platform_device mtd_dev = { + .name = "physmap-flash", + .resource = mtd_resources, + .num_resources = ARRAY_SIZE(mtd_resources), + .dev = { + .platform_data = &flash_data, + }, +}; + +/* + * Register a sane SPROMv2 to make the on-board + * bcm4318 WLAN work + */ +static struct ssb_sprom bcm63xx_sprom = { + .revision = 0x02, + .board_rev = 0x17, + .country_code = 0x0, + .ant_available_bg = 0x3, + .pa0b0 = 0x15ae, + .pa0b1 = 0xfa85, + .pa0b2 = 0xfe8d, + .pa1b0 = 0xffff, + .pa1b1 = 0xffff, + .pa1b2 = 0xffff, + .gpio0 = 0xff, + .gpio1 = 0xff, + .gpio2 = 0xff, + .gpio3 = 0xff, + .maxpwr_bg = 0x004c, + .itssi_bg = 0x00, + .boardflags_lo = 0x2848, + .boardflags_hi = 0x0000, +}; + +/* + * third stage init callback, register all board devices. + */ +int __init board_register_devices(void) +{ + u32 val; + + bcm63xx_uart_register(); + + if (board.has_pccard) + bcm63xx_pcmcia_register(); + + if (board.has_enet0 && + !board_get_mac_address(board.enet0.mac_addr)) + bcm63xx_enet_register(0, &board.enet0); + + if (board.has_enet1 && + !board_get_mac_address(board.enet1.mac_addr)) + bcm63xx_enet_register(1, &board.enet1); + + if (board.has_ohci0) + bcm63xx_ohci_register(); + + if (board.has_ehci0) + bcm63xx_ehci_register(); + + /* Generate MAC address for WLAN and + * register our SPROM */ + if (!board_get_mac_address(bcm63xx_sprom.il0mac)) { + memcpy(bcm63xx_sprom.et0mac, bcm63xx_sprom.il0mac, ETH_ALEN); + memcpy(bcm63xx_sprom.et1mac, bcm63xx_sprom.il0mac, ETH_ALEN); + if (ssb_arch_set_fallback_sprom(&bcm63xx_sprom) < 0) + printk(KERN_ERR "failed to register fallback SPROM\n"); + } + + /* read base address of boot chip select (0) */ + val = bcm_mpi_readl(MPI_CSBASE_REG(0)); + val &= MPI_CSBASE_BASE_MASK; + mtd_resources[0].start = val; + mtd_resources[0].end = 0x1FFFFFFF; + + platform_device_register(&mtd_dev); + + return 0; +} + --- a/arch/mips/bcm63xx/prom.c +++ b/arch/mips/bcm63xx/prom.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -36,6 +37,9 @@ void __init prom_init(void) /* assign command line from kernel config */ strcpy(arcs_cmdline, CONFIG_CMDLINE); + + /* do low level board init */ + board_prom_init(); } void __init prom_free_prom_memory(void) --- a/arch/mips/bcm63xx/setup.c +++ b/arch/mips/bcm63xx/setup.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -90,8 +91,9 @@ static void __bcm63xx_machine_reboot(cha const char *get_system_type(void) { static char buf[128]; - sprintf(buf, "bcm963xx (0x%04x/0x%04X)", - bcm63xx_get_cpu_id(), bcm63xx_get_cpu_rev()); + snprintf(buf, sizeof(buf), "bcm63xx/%s (0x%04x/0x%04X)", + board_get_name(), + bcm63xx_get_cpu_id(), bcm63xx_get_cpu_rev()); return buf; } @@ -99,6 +101,7 @@ void __init plat_time_init(void) { mips_hpt_frequency = bcm63xx_get_cpu_freq() / 2; } + void __init plat_mem_setup(void) { add_memory_region(0, bcm63xx_get_memory_size(), BOOT_MEM_RAM); @@ -110,4 +113,13 @@ void __init plat_mem_setup(void) set_io_port_base(0); ioport_resource.start = 0; ioport_resource.end = ~0; + + board_setup(); +} + +int __init bcm63xx_register_devices(void) +{ + return board_register_devices(); } + +arch_initcall(bcm63xx_register_devices); --- /dev/null +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_board.h @@ -0,0 +1,12 @@ +#ifndef BCM63XX_BOARD_H_ +#define BCM63XX_BOARD_H_ + +const char *board_get_name(void); + +void board_prom_init(void); + +void board_setup(void); + +int board_register_devices(void); + +#endif /* ! BCM63XX_BOARD_H_ */ --- /dev/null +++ b/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h @@ -0,0 +1,50 @@ +#ifndef BOARD_BCM963XX_H_ +#define BOARD_BCM963XX_H_ + +#include +#include + +/* + * flash mapping + */ +#define BCM963XX_CFE_VERSION_OFFSET 0x570 +#define BCM963XX_NVRAM_OFFSET 0x580 + +/* + * nvram structure + */ +struct bcm963xx_nvram { + u32 version; + u8 reserved1[256]; + u8 name[16]; + u32 main_tp_number; + u32 psi_size; + u32 mac_addr_count; + u8 mac_addr_base[6]; + u8 reserved2[2]; + u32 checksum_old; + u8 reserved3[720]; + u32 checksum_high; +}; + +/* + * board definition + */ +struct board_info { + u8 name[16]; + unsigned int expected_cpu_id; + + /* enabled feature/device */ + unsigned int has_enet0:1; + unsigned int has_enet1:1; + unsigned int has_pci:1; + unsigned int has_pccard:1; + unsigned int has_ohci0:1; + unsigned int has_ehci0:1; + + /* ethernet config */ + struct bcm63xx_enet_platform_data enet0; + struct bcm63xx_enet_platform_data enet1; +}; + +#endif /* ! BOARD_BCM963XX_H_ */ From ralf@linux-mips.org Wed Jul 1 19:11:10 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 01 Jul 2009 19:11:15 +0200 (CEST) Received: (from localhost user: 'ralf' uid#500 fake: STDIN (ralf@eddie.linux-mips.org)) by ftp.linux-mips.org id S1491879AbZGARHL for <"|/home/ecartis/ecartis -s linux-mips">; Wed, 1 Jul 2009 19:07:11 +0200 Message-Id: <20090701120940.303430182@linux-mips.org> User-Agent: quilt/0.47-1 Date: Wed, 01 Jul 2009 12:29:38 +0100 From: Ralf Baechle To: linux-mips@linux-mips.org Cc: Maxime Bizon , Florian Fainelli Subject: [patch 12/12] MIPS: BCM63XX: Add defconfig. References: <20090701112926.825088732@linux-mips.org> Content-Disposition: inline; filename=0012.patch Status: RO Content-Length: 24020 Lines: 986 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-archive-position: 23578 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips From: Maxime Bizon Signed-off-by: Maxime Bizon Signed-off-by: Florian Fainelli Signed-off-by: Ralf Baechle arch/mips/configs/bcm63xx_defconfig | 972 ++++++++++++++++++++++++++++++++++++ 1 file changed, 972 insertions(+) create mode 100644 arch/mips/configs/bcm63xx_defconfig --- /dev/null +++ b/arch/mips/configs/bcm63xx_defconfig @@ -0,0 +1,972 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.30-rc6 +# Sun May 31 20:17:18 2009 +# +CONFIG_MIPS=y + +# +# Machine selection +# +# CONFIG_MACH_ALCHEMY is not set +# CONFIG_BASLER_EXCITE is not set +# CONFIG_BCM47XX is not set +CONFIG_BCM63XX=y +# CONFIG_MIPS_COBALT is not set +# CONFIG_MACH_DECSTATION is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_LASAT is not set +# CONFIG_LEMOTE_FULONG is not set +# CONFIG_MIPS_MALTA is not set +# CONFIG_MIPS_SIM is not set +# CONFIG_NEC_MARKEINS is not set +# CONFIG_MACH_VR41XX is not set +# CONFIG_NXP_STB220 is not set +# CONFIG_NXP_STB225 is not set +# CONFIG_PNX8550_JBS is not set +# CONFIG_PNX8550_STB810 is not set +# CONFIG_PMC_MSP is not set +# CONFIG_PMC_YOSEMITE is not set +# CONFIG_SGI_IP22 is not set +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP28 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_CRHONE is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_BIGSUR is not set +# CONFIG_SNI_RM is not set +# CONFIG_MACH_TX39XX is not set +# CONFIG_MACH_TX49XX is not set +# CONFIG_MIKROTIK_RB532 is not set +# CONFIG_WR_PPMC is not set +# CONFIG_CAVIUM_OCTEON_SIMULATOR is not set +# CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD is not set + +# +# CPU support +# +CONFIG_BCM63XX_CPU_6348=y +CONFIG_BCM63XX_CPU_6358=y +CONFIG_BOARD_BCM963XX=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_ARCH_SUPPORTS_OPROFILE=y +CONFIG_GENERIC_FIND_NEXT_BIT=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CMOS_UPDATE=y +CONFIG_SCHED_OMIT_FRAME_POINTER=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +CONFIG_CEVT_R4K_LIB=y +CONFIG_CEVT_R4K=y +CONFIG_CSRC_R4K_LIB=y +CONFIG_CSRC_R4K=y +CONFIG_DMA_NONCOHERENT=y +CONFIG_DMA_NEED_PCI_MAP_STATE=y +CONFIG_EARLY_PRINTK=y +CONFIG_SYS_HAS_EARLY_PRINTK=y +# CONFIG_HOTPLUG_CPU is not set +# CONFIG_NO_IOPORT is not set +CONFIG_GENERIC_GPIO=y +CONFIG_CPU_BIG_ENDIAN=y +# CONFIG_CPU_LITTLE_ENDIAN is not set +CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y +CONFIG_IRQ_CPU=y +CONFIG_SWAP_IO_SPACE=y +CONFIG_MIPS_L1_CACHE_SHIFT=5 + +# +# CPU selection +# +# CONFIG_CPU_LOONGSON2 is not set +CONFIG_CPU_MIPS32_R1=y +# CONFIG_CPU_MIPS32_R2 is not set +# CONFIG_CPU_MIPS64_R1 is not set +# CONFIG_CPU_MIPS64_R2 is not set +# CONFIG_CPU_R3000 is not set +# CONFIG_CPU_TX39XX is not set +# CONFIG_CPU_VR41XX is not set +# CONFIG_CPU_R4300 is not set +# CONFIG_CPU_R4X00 is not set +# CONFIG_CPU_TX49XX is not set +# CONFIG_CPU_R5000 is not set +# CONFIG_CPU_R5432 is not set +# CONFIG_CPU_R5500 is not set +# CONFIG_CPU_R6000 is not set +# CONFIG_CPU_NEVADA is not set +# CONFIG_CPU_R8000 is not set +# CONFIG_CPU_R10000 is not set +# CONFIG_CPU_RM7000 is not set +# CONFIG_CPU_RM9000 is not set +# CONFIG_CPU_SB1 is not set +# CONFIG_CPU_CAVIUM_OCTEON is not set +CONFIG_SYS_HAS_CPU_MIPS32_R1=y +CONFIG_CPU_MIPS32=y +CONFIG_CPU_MIPSR1=y +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_HARDWARE_WATCHPOINTS=y + +# +# Kernel type +# +CONFIG_32BIT=y +# CONFIG_64BIT is not set +CONFIG_PAGE_SIZE_4KB=y +# CONFIG_PAGE_SIZE_8KB is not set +# CONFIG_PAGE_SIZE_16KB is not set +# CONFIG_PAGE_SIZE_32KB is not set +# CONFIG_PAGE_SIZE_64KB is not set +CONFIG_CPU_HAS_PREFETCH=y +CONFIG_MIPS_MT_DISABLED=y +# CONFIG_MIPS_MT_SMP is not set +# CONFIG_MIPS_MT_SMTC is not set +CONFIG_CPU_HAS_LLSC=y +CONFIG_CPU_HAS_SYNC=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_CPU_SUPPORTS_HIGHMEM=y +CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_ARCH_POPULATES_NODE_MAP=y +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=0 +CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y +CONFIG_HAVE_MLOCK=y +CONFIG_HAVE_MLOCKED_PAGE_BIT=y +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ=y +# CONFIG_HIGH_RES_TIMERS is not set +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +# CONFIG_HZ_48 is not set +# CONFIG_HZ_100 is not set +# CONFIG_HZ_128 is not set +CONFIG_HZ_250=y +# CONFIG_HZ_256 is not set +# CONFIG_HZ_1000 is not set +# CONFIG_HZ_1024 is not set +CONFIG_SYS_SUPPORTS_ARBIT_HZ=y +CONFIG_HZ=250 +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set +# CONFIG_PREEMPT is not set +# CONFIG_KEXEC is not set +# CONFIG_SECCOMP is not set +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="" +# CONFIG_LOCALVERSION_AUTO is not set +# CONFIG_SWAP is not set +# CONFIG_SYSVIPC is not set +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_AUDIT is not set + +# +# RCU Subsystem +# +CONFIG_CLASSIC_RCU=y +# CONFIG_TREE_RCU is not set +# CONFIG_PREEMPT_RCU is not set +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_PREEMPT_RCU_TRACE is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=17 +# CONFIG_GROUP_SCHED is not set +# CONFIG_CGROUPS is not set +CONFIG_SYSFS_DEPRECATED=y +CONFIG_SYSFS_DEPRECATED_V2=y +# CONFIG_RELAY is not set +# CONFIG_NAMESPACES is not set +# CONFIG_BLK_DEV_INITRD is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +CONFIG_EMBEDDED=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_EXTRA_PASS is not set +# CONFIG_STRIP_ASM_SYMS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +# CONFIG_PCSPKR_PLATFORM is not set +CONFIG_BASE_FULL=y +# CONFIG_FUTEX is not set +# CONFIG_EPOLL is not set +# CONFIG_SIGNALFD is not set +# CONFIG_TIMERFD is not set +# CONFIG_EVENTFD is not set +# CONFIG_SHMEM is not set +# CONFIG_AIO is not set +# CONFIG_VM_EVENT_COUNTERS is not set +CONFIG_PCI_QUIRKS=y +# CONFIG_SLUB_DEBUG is not set +CONFIG_COMPAT_BRK=y +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +# CONFIG_MARKERS is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_SLOW_WORK is not set +# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set +CONFIG_BASE_SMALL=0 +# CONFIG_MODULES is not set +CONFIG_BLOCK=y +# CONFIG_LBD is not set +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +# CONFIG_IOSCHED_AS is not set +# CONFIG_IOSCHED_DEADLINE is not set +# CONFIG_IOSCHED_CFQ is not set +# CONFIG_DEFAULT_AS is not set +# CONFIG_DEFAULT_DEADLINE is not set +# CONFIG_DEFAULT_CFQ is not set +CONFIG_DEFAULT_NOOP=y +CONFIG_DEFAULT_IOSCHED="noop" +# CONFIG_FREEZER is not set + +# +# Bus options (PCI, PCMCIA, EISA, ISA, TC) +# +CONFIG_HW_HAS_PCI=y +CONFIG_PCI=y +CONFIG_PCI_DOMAINS=y +# CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_PCI_LEGACY is not set +# CONFIG_PCI_STUB is not set +# CONFIG_PCI_IOV is not set +CONFIG_MMU=y +CONFIG_PCCARD=y +# CONFIG_PCMCIA_DEBUG is not set +CONFIG_PCMCIA=y +CONFIG_PCMCIA_LOAD_CIS=y +CONFIG_PCMCIA_IOCTL=y +CONFIG_CARDBUS=y + +# +# PC-card bridges +# +# CONFIG_YENTA is not set +# CONFIG_PD6729 is not set +# CONFIG_I82092 is not set +CONFIG_PCMCIA_BCM63XX=y +# CONFIG_HOTPLUG_PCI is not set + +# +# Executable file formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set +# CONFIG_BINFMT_MISC is not set +CONFIG_TRAD_SIGNALS=y + +# +# Power management options +# +CONFIG_ARCH_SUSPEND_POSSIBLE=y +# CONFIG_PM is not set +CONFIG_NET=y + +# +# Networking options +# +# CONFIG_PACKET is not set +CONFIG_UNIX=y +# CONFIG_NET_KEY is not set +CONFIG_INET=y +# CONFIG_IP_MULTICAST is not set +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +# CONFIG_IP_PNP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_LRO is not set +# CONFIG_INET_DIAG is not set +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +# CONFIG_IPV6 is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_PHONET is not set +# CONFIG_NET_SCHED is not set +# CONFIG_DCB is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set +# CONFIG_WIRELESS is not set +# CONFIG_WIMAX is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +# CONFIG_STANDALONE is not set +# CONFIG_PREVENT_FIRMWARE_BUILD is not set +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_CONNECTOR is not set +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_CONCAT is not set +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +# CONFIG_MTD_CMDLINE_PARTS is not set +# CONFIG_MTD_AR7_PARTS is not set + +# +# User Modules And Translation Layers +# +# CONFIG_MTD_CHAR is not set +# CONFIG_MTD_BLKDEVS is not set +# CONFIG_MTD_BLOCK is not set +# CONFIG_MTD_BLOCK_RO is not set +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_MTD_OOPS is not set + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=y +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_GEN_PROBE=y +# CONFIG_MTD_CFI_ADV_OPTIONS is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +CONFIG_MTD_CFI_INTELEXT=y +CONFIG_MTD_CFI_AMDSTD=y +# CONFIG_MTD_CFI_STAA is not set +CONFIG_MTD_CFI_UTIL=y +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +CONFIG_MTD_PHYSMAP=y +# CONFIG_MTD_PHYSMAP_COMPAT is not set +# CONFIG_MTD_INTEL_VR_NOR is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_PMC551 is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +# CONFIG_MTD_NAND is not set +# CONFIG_MTD_ONENAND is not set + +# +# LPDDR flash memory drivers +# +# CONFIG_MTD_LPDDR is not set + +# +# UBI - Unsorted block images +# +# CONFIG_MTD_UBI is not set +# CONFIG_PARPORT is not set +# CONFIG_BLK_DEV is not set +# CONFIG_MISC_DEVICES is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +# CONFIG_SCSI is not set +# CONFIG_SCSI_DMA is not set +# CONFIG_SCSI_NETLINK is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +# CONFIG_FUSION is not set + +# +# IEEE 1394 (FireWire) support +# + +# +# Enable only one of the two stacks, unless you know what you are doing +# +# CONFIG_FIREWIRE is not set +# CONFIG_IEEE1394 is not set +# CONFIG_I2O is not set +CONFIG_NETDEVICES=y +CONFIG_COMPAT_NET_DEV_OPS=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_VETH is not set +# CONFIG_ARCNET is not set +CONFIG_PHYLIB=y + +# +# MII PHY device drivers +# +# CONFIG_MARVELL_PHY is not set +# CONFIG_DAVICOM_PHY is not set +# CONFIG_QSEMI_PHY is not set +# CONFIG_LXT_PHY is not set +# CONFIG_CICADA_PHY is not set +# CONFIG_VITESSE_PHY is not set +# CONFIG_SMSC_PHY is not set +# CONFIG_BROADCOM_PHY is not set +CONFIG_BCM63XX_PHY=y +# CONFIG_ICPLUS_PHY is not set +# CONFIG_REALTEK_PHY is not set +# CONFIG_NATIONAL_PHY is not set +# CONFIG_STE10XP is not set +# CONFIG_LSI_ET1011C_PHY is not set +# CONFIG_FIXED_PHY is not set +# CONFIG_MDIO_BITBANG is not set +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +# CONFIG_AX88796 is not set +# CONFIG_HAPPYMEAL is not set +# CONFIG_SUNGEM is not set +# CONFIG_CASSINI is not set +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_SMC91X is not set +# CONFIG_DM9000 is not set +# CONFIG_ETHOC is not set +# CONFIG_DNET is not set +# CONFIG_NET_TULIP is not set +# CONFIG_HP100 is not set +# CONFIG_IBM_NEW_EMAC_ZMII is not set +# CONFIG_IBM_NEW_EMAC_RGMII is not set +# CONFIG_IBM_NEW_EMAC_TAH is not set +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set +# CONFIG_NET_PCI is not set +# CONFIG_B44 is not set +# CONFIG_ATL2 is not set +CONFIG_BCM63XX_ENET=y +# CONFIG_NETDEV_1000 is not set +# CONFIG_NETDEV_10000 is not set +# CONFIG_TR is not set + +# +# Wireless LAN +# +# CONFIG_WLAN_PRE80211 is not set +# CONFIG_WLAN_80211 is not set + +# +# Enable WiMAX (Networking options) to see the WiMAX drivers +# + +# +# USB Network Adapters +# +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_USBNET is not set +# CONFIG_NET_PCMCIA is not set +# CONFIG_WAN is not set +# CONFIG_FDDI is not set +# CONFIG_HIPPI is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_ISDN is not set +# CONFIG_PHONE is not set + +# +# Input device support +# +# CONFIG_INPUT is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +# CONFIG_VT is not set +# CONFIG_DEVKMEM is not set +# CONFIG_SERIAL_NONSTANDARD is not set +# CONFIG_NOZOMI is not set + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_JSM is not set +CONFIG_SERIAL_BCM63XX=y +CONFIG_SERIAL_BCM63XX_CONSOLE=y +# CONFIG_UNIX98_PTYS is not set +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=256 +# CONFIG_IPMI_HANDLER is not set +# CONFIG_HW_RANDOM is not set +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set + +# +# PCMCIA character devices +# +# CONFIG_SYNCLINK_CS is not set +# CONFIG_CARDMAN_4000 is not set +# CONFIG_CARDMAN_4040 is not set +# CONFIG_IPWIRELESS is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +CONFIG_DEVPORT=y +# CONFIG_I2C is not set +# CONFIG_SPI is not set +CONFIG_ARCH_REQUIRE_GPIOLIB=y +CONFIG_GPIOLIB=y +# CONFIG_GPIO_SYSFS is not set + +# +# Memory mapped GPIO expanders: +# + +# +# I2C GPIO expanders: +# + +# +# PCI GPIO expanders: +# +# CONFIG_GPIO_BT8XX is not set + +# +# SPI GPIO expanders: +# +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +# CONFIG_THERMAL_HWMON is not set +# CONFIG_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +CONFIG_SSB=y +CONFIG_SSB_SPROM=y +CONFIG_SSB_PCIHOST_POSSIBLE=y +CONFIG_SSB_PCIHOST=y +# CONFIG_SSB_B43_PCI_BRIDGE is not set +CONFIG_SSB_PCMCIAHOST_POSSIBLE=y +# CONFIG_SSB_PCMCIAHOST is not set +# CONFIG_SSB_SILENT is not set +# CONFIG_SSB_DEBUG is not set +CONFIG_SSB_DRIVER_PCICORE_POSSIBLE=y +# CONFIG_SSB_DRIVER_PCICORE is not set +# CONFIG_SSB_DRIVER_MIPS is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_REGULATOR is not set + +# +# Multimedia devices +# + +# +# Multimedia core support +# +# CONFIG_VIDEO_DEV is not set +# CONFIG_DVB_CORE is not set +# CONFIG_VIDEO_MEDIA is not set + +# +# Multimedia drivers +# +# CONFIG_DAB is not set + +# +# Graphics support +# +# CONFIG_DRM is not set +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +# CONFIG_FB is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +CONFIG_DISPLAY_SUPPORT=y + +# +# Display hardware drivers +# +# CONFIG_SOUND is not set +CONFIG_USB_SUPPORT=y +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y +CONFIG_USB_ARCH_HAS_EHCI=y +CONFIG_USB=y +# CONFIG_USB_DEBUG is not set +# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set + +# +# Miscellaneous USB options +# +# CONFIG_USB_DEVICEFS is not set +# CONFIG_USB_DEVICE_CLASS is not set +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_OTG is not set +# CONFIG_USB_OTG_WHITELIST is not set +# CONFIG_USB_OTG_BLACKLIST_HUB is not set +# CONFIG_USB_MON is not set +# CONFIG_USB_WUSB is not set +# CONFIG_USB_WUSB_CBAF is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_C67X00_HCD is not set +CONFIG_USB_EHCI_HCD=y +# CONFIG_USB_EHCI_ROOT_HUB_TT is not set +# CONFIG_USB_EHCI_TT_NEWSCHED is not set +CONFIG_USB_EHCI_BIG_ENDIAN_MMIO=y +# CONFIG_USB_OXU210HP_HCD is not set +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_ISP1760_HCD is not set +CONFIG_USB_OHCI_HCD=y +# CONFIG_USB_OHCI_HCD_SSB is not set +CONFIG_USB_OHCI_BIG_ENDIAN_DESC=y +CONFIG_USB_OHCI_BIG_ENDIAN_MMIO=y +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +# CONFIG_USB_UHCI_HCD is not set +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_WHCI_HCD is not set +# CONFIG_USB_HWA_HCD is not set + +# +# USB Device Class drivers +# +# CONFIG_USB_ACM is not set +# CONFIG_USB_PRINTER is not set +# CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may +# + +# +# also be needed; see USB_STORAGE Help for more info +# +# CONFIG_USB_LIBUSUAL is not set + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set + +# +# USB port drivers +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_BERRY_CHARGE is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_SISUSBVGA is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_VST is not set +# CONFIG_USB_GADGET is not set + +# +# OTG and related infrastructure +# +# CONFIG_USB_GPIO_VBUS is not set +# CONFIG_NOP_USB_XCEIV is not set +# CONFIG_UWB is not set +# CONFIG_MMC is not set +# CONFIG_MEMSTICK is not set +# CONFIG_NEW_LEDS is not set +# CONFIG_ACCESSIBILITY is not set +# CONFIG_INFINIBAND is not set +CONFIG_RTC_LIB=y +# CONFIG_RTC_CLASS is not set +# CONFIG_DMADEVICES is not set +# CONFIG_AUXDISPLAY is not set +# CONFIG_UIO is not set +# CONFIG_STAGING is not set + +# +# File systems +# +# CONFIG_EXT2_FS is not set +# CONFIG_EXT3_FS is not set +# CONFIG_EXT4_FS is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +# CONFIG_FILE_LOCKING is not set +# CONFIG_XFS_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_BTRFS_FS is not set +# CONFIG_DNOTIFY is not set +# CONFIG_INOTIFY is not set +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set + +# +# Caches +# +# CONFIG_FSCACHE is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +# CONFIG_MSDOS_FS is not set +# CONFIG_VFAT_FS is not set +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_KCORE=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_JFFS2_FS is not set +# CONFIG_CRAMFS is not set +# CONFIG_SQUASHFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +# CONFIG_NILFS2_FS is not set +# CONFIG_NETWORK_FILESYSTEMS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y +# CONFIG_NLS is not set +# CONFIG_DLM is not set + +# +# Kernel hacking +# +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +CONFIG_MAGIC_SYSRQ=y +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_KERNEL is not set +# CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +CONFIG_SYSCTL_SYSCALL_CHECK=y +CONFIG_TRACING_SUPPORT=y + +# +# Tracers +# +# CONFIG_IRQSOFF_TRACER is not set +# CONFIG_SCHED_TRACER is not set +# CONFIG_CONTEXT_SWITCH_TRACER is not set +# CONFIG_EVENT_TRACER is not set +# CONFIG_BOOT_TRACER is not set +# CONFIG_TRACE_BRANCH_PROFILING is not set +# CONFIG_KMEMTRACE is not set +# CONFIG_WORKQUEUE_TRACER is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +CONFIG_CMDLINE="console=ttyS0,115200" + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +# CONFIG_SECURITY_FILE_CAPABILITIES is not set +# CONFIG_CRYPTO is not set +# CONFIG_BINARY_PRINTF is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_GENERIC_FIND_LAST_BIT=y +# CONFIG_CRC_CCITT is not set +# CONFIG_CRC16 is not set +# CONFIG_CRC_T10DIF is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y +CONFIG_NLATTR=y From rpjday@crashcourse.ca Wed Jul 1 19:25:54 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 01 Jul 2009 19:25:59 +0200 (CEST) Received: from astoria.ccjclearline.com ([64.235.106.9]:51063 "EHLO astoria.ccjclearline.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1491784AbZGARZy (ORCPT ); Wed, 1 Jul 2009 19:25:54 +0200 Received: from cpe00142a336e11-cm001ac318e826.cpe.net.cable.rogers.com ([174.113.191.234] helo=crashcourse.ca) by astoria.ccjclearline.com with esmtpsa (TLSv1:AES256-SHA:256) (Exim 4.69) (envelope-from ) id 1MM3sN-0002Y9-3s for linux-mips@linux-mips.org; Wed, 01 Jul 2009 13:45:43 -0400 Date: Wed, 1 Jul 2009 13:18:04 -0400 (EDT) From: "Robert P. J. Day" X-X-Sender: rpjday@localhost To: linux-mips@linux-mips.org Subject: Makefile references to undefined CONFIG variables Message-ID: User-Agent: Alpine 2.00 (LFD 1167 2008-08-23) MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII X-AntiAbuse: This header was added to track abuse, please include it with any abuse report X-AntiAbuse: Primary Hostname - astoria.ccjclearline.com X-AntiAbuse: Original Domain - linux-mips.org X-AntiAbuse: Originator/Caller UID/GID - [47 12] / [47 12] X-AntiAbuse: Sender Address Domain - crashcourse.ca X-Source: X-Source-Args: X-Source-Dir: Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23579 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: rpjday@crashcourse.ca Precedence: bulk X-list: linux-mips just FYI, results from my latest tree scan -- references from Makefiles to CONFIG vars that don't seem to exist: ===== HAVE_GPIO_LIB ===== ./arch/mips/pmc-sierra/msp71xx/Makefile:obj-$(CONFIG_HAVE_GPIO_LIB) += gpio.o gpio_extended.o ===== MSPETH ===== ./arch/mips/pmc-sierra/msp71xx/Makefile:obj-$(CONFIG_MSPETH) += msp_eth.o ===== USB_MSP71XX ===== ./arch/mips/pmc-sierra/msp71xx/Makefile:obj-$(CONFIG_USB_MSP71XX) += msp_usb.o rday -- ======================================================================== Robert P. J. Day Waterloo, Ontario, CANADA Linux Consulting, Training and Annoying Kernel Pedantry. Web page: http://crashcourse.ca Linked In: http://www.linkedin.com/in/rpjday Twitter: http://twitter.com/rpjday ======================================================================== From jeff.chua.linux@gmail.com Wed Jul 1 19:33:54 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 01 Jul 2009 19:34:01 +0200 (CEST) Received: from mail-gx0-f222.google.com ([209.85.217.222]:38616 "EHLO mail-gx0-f222.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1491784AbZGARdy (ORCPT ); Wed, 1 Jul 2009 19:33:54 +0200 Received: by gxk22 with SMTP id 22so1689310gxk.0 for ; Wed, 01 Jul 2009 10:28:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:in-reply-to:references :date:message-id:subject:from:to:cc:content-type :content-transfer-encoding; bh=1yGL1iMICOo9aWRD4beDw7N8Qy0gRR1OBWXu+ibEYIw=; b=aXBNdFrmRY1q2oLl5e4bjX2ieqNYwQr9qdSXLETY6uAZBWHxm/fJZKCrTj8JIxwwxS b09Yv0vmotZAFdXa3VcD9DzRMSRH+LyhhPwdHxU1ZYo4DhASZirSTvyBi1NNh5ydm6sR quwwkEVQ6sgm8jUrPMReP+EO1jbFpgnfT/nsA= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type:content-transfer-encoding; b=Cmon2XDpjL6pdRFuUQIEgG6hQDUrNjeOuniWQeJrGe7ZoncVt5S+yg6QaCO75h72Ac ho/+jGz1fUAdUf6otrIV6JAi+Y1VOIeRTmjekS1kIDc1ETdvgZaEemmjQd2YbfrmGOS1 CVgvWfx+G2mtNHzp3KE8Mq0naq0M1n8U4RYvA= MIME-Version: 1.0 Received: by 10.90.55.3 with SMTP id d3mr8465973aga.100.1246469298890; Wed, 01 Jul 2009 10:28:18 -0700 (PDT) In-Reply-To: <200907011829.16850.bzolnier@gmail.com> References: <1246459661.9660.40.camel@falcon> <200907011821.26091.bzolnier@gmail.com> <200907011829.16850.bzolnier@gmail.com> Date: Thu, 2 Jul 2009 01:28:18 +0800 Message-ID: Subject: Re: [Bug #13663] suspend to ram regression (IDE related) From: Jeff Chua To: Bartlomiej Zolnierkiewicz Cc: wuzhangjin@gmail.com, Etienne Basset , David Miller , rjw@sisk.pl, linux-kernel@vger.kernel.org, kernel-testers@vger.kernel.org, Ralf Baechle , linux-mips@linux-mips.org, linux-ide@vger.kernel.org Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: base64 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23580 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jeff.chua.linux@gmail.com Precedence: bulk X-list: linux-mips T24gVGh1LCBKdWwgMiwgMjAwOSBhdCAxMjoyOSBBTSwgQmFydGxvbWllagpab2xuaWVya2lld2lj ejxiem9sbmllckBnbWFpbC5jb20+IHdyb3RlOgo+IEhlcmUgaXMgdGhlIG1vcmUgY29tcGxldGUg dmVyc2lvbiwgYWxzbyB0YWtpbmcgaW50byB0aGUgYWNjb3VudCBjaGFuZ2VzCj4gaW4gaWRlX2lu dHIoKSBhbmQgaWRlX3RpbWVyX2V4cGlyeSgpOgoKVGhpcyB3b3JrcyBncmVhdCBmb3IuIFN1cnZp dmVkIFNUUiwgU1RELiBJIGp1c3QgYXBwbGllZCBvbiB0b3AgdmFuaWxsYQpsYXRlc3QgTGludXMn cyBnaXQgcHVsbC4gTm90aGluZyBlbHNlIHRvIHJldmVydC4KClRoYW5rcywKSmVmZi4KCgo+IC0t LQo+IKBkcml2ZXJzL2lkZS9pZGUtaW8uYyB8IKAgMTUgKysrKysrKysrKy0tLS0tCj4goDEgZmls ZSBjaGFuZ2VkLCAxMCBpbnNlcnRpb25zKCspLCA1IGRlbGV0aW9ucygtKQo+Cj4gSW5kZXg6IGIv ZHJpdmVycy9pZGUvaWRlLWlvLmMKPiA9PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09 PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09Cj4gLS0tIGEvZHJpdmVycy9pZGUvaWRl LWlvLmMKPiArKysgYi9kcml2ZXJzL2lkZS9pZGUtaW8uYwo+IEBAIC01MzIsNyArNTMyLDggQEAg cmVwZWF0Ogo+Cj4goCCgIKAgoCCgIKAgoCCgaWYgKHN0YXJ0c3RvcCA9PSBpZGVfc3RvcHBlZCkg ewo+IKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgcnEgPSBod2lmLT5ycTsKPiAtIKAgoCCgIKAgoCCg IKAgoCCgIKAgoCBod2lmLT5ycSA9IE5VTEw7Cj4gKyCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgaWYg KChkcml2ZS0+ZGV2X2ZsYWdzICYgSURFX0RGTEFHX0JMT0NLRUQpID09IDApCj4gKyCgIKAgoCCg IKAgoCCgIKAgoCCgIKAgoCCgIKAgoCBod2lmLT5ycSA9IE5VTEw7Cj4goCCgIKAgoCCgIKAgoCCg IKAgoCCgIKBnb3RvIHJlcGVhdDsKPiCgIKAgoCCgIKAgoCCgIKB9Cj4goCCgIKAgoH0gZWxzZQo+ IEBAIC02NzksOCArNjgwLDEwIEBAIHZvaWQgaWRlX3RpbWVyX2V4cGlyeSAodW5zaWduZWQgbG9u ZyBkYXQKPiCgIKAgoCCgIKAgoCCgIKBzcGluX2xvY2tfaXJxKCZod2lmLT5sb2NrKTsKPiCgIKAg oCCgIKAgoCCgIKBlbmFibGVfaXJxKGh3aWYtPmlycSk7Cj4goCCgIKAgoCCgIKAgoCCgaWYgKHN0 YXJ0c3RvcCA9PSBpZGVfc3RvcHBlZCAmJiBod2lmLT5wb2xsaW5nID09IDApIHsKPiAtIKAgoCCg IKAgoCCgIKAgoCCgIKAgoCBycV9pbl9mbGlnaHQgPSBod2lmLT5ycTsKPiAtIKAgoCCgIKAgoCCg IKAgoCCgIKAgoCBod2lmLT5ycSA9IE5VTEw7Cj4gKyCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgaWYg KChkcml2ZS0+ZGV2X2ZsYWdzICYgSURFX0RGTEFHX0JMT0NLRUQpID09IDApIHsKPiArIKAgoCCg IKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIHJxX2luX2ZsaWdodCA9IGh3aWYtPnJxOwo+ICsgoCCg IKAgoCCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgaHdpZi0+cnEgPSBOVUxMOwo+ICsgoCCgIKAgoCCg IKAgoCCgIKAgoCCgIH0KPiCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoGlkZV91bmxvY2tfcG9ydCho d2lmKTsKPiCgIKAgoCCgIKAgoCCgIKAgoCCgIKAgoHBsdWdfZGV2aWNlID0gMTsKPiCgIKAgoCCg IKAgoCCgIKB9Cj4gQEAgLTg1Niw4ICs4NTksMTAgQEAgaXJxcmV0dXJuX3QgaWRlX2ludHIgKGlu dCBpcnEsIHZvaWQgKmRldgo+IKAgoCCgIKAgKi8KPiCgIKAgoCCgaWYgKHN0YXJ0c3RvcCA9PSBp ZGVfc3RvcHBlZCAmJiBod2lmLT5wb2xsaW5nID09IDApIHsKPiCgIKAgoCCgIKAgoCCgIKBCVUdf T04oaHdpZi0+aGFuZGxlcik7Cj4gLSCgIKAgoCCgIKAgoCCgIHJxX2luX2ZsaWdodCA9IGh3aWYt PnJxOwo+IC0goCCgIKAgoCCgIKAgoCBod2lmLT5ycSA9IE5VTEw7Cj4gKyCgIKAgoCCgIKAgoCCg IGlmICgoZHJpdmUtPmRldl9mbGFncyAmIElERV9ERkxBR19CTE9DS0VEKSA9PSAwKSB7Cj4gKyCg IKAgoCCgIKAgoCCgIKAgoCCgIKAgcnFfaW5fZmxpZ2h0ID0gaHdpZi0+cnE7Cj4gKyCgIKAgoCCg IKAgoCCgIKAgoCCgIKAgaHdpZi0+cnEgPSBOVUxMOwo+ICsgoCCgIKAgoCCgIKAgoCB9Cj4goCCg IKAgoCCgIKAgoCCgaWRlX3VubG9ja19wb3J0KGh3aWYpOwo+IKAgoCCgIKAgoCCgIKAgoHBsdWdf ZGV2aWNlID0gMTsKPiCgIKAgoCCgfQo+Cg== From ralf@h5.dl5rb.org.uk Wed Jul 1 20:12:55 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 01 Jul 2009 20:13:02 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:47976 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1491834AbZGASMz (ORCPT ); Wed, 1 Jul 2009 20:12:55 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id n61I7GUw023310; Wed, 1 Jul 2009 19:07:16 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id n61I7Fba023308; Wed, 1 Jul 2009 19:07:15 +0100 Date: Wed, 1 Jul 2009 19:07:15 +0100 From: Ralf Baechle To: Wu Zhangjin Cc: LKML , linux-mips@linux-mips.org, Pavel Machek Subject: Re: [BUG] MIPS: Hibernation in the latest linux-mips:master branch not work Message-ID: <20090701180715.GA23121@linux-mips.org> References: <1246372868.19049.17.camel@falcon> <20090630144540.GA18212@linux-mips.org> <1246374687.20482.10.camel@falcon> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1246374687.20482.10.camel@falcon> User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23581 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Tue, Jun 30, 2009 at 11:11:27PM +0800, Wu Zhangjin wrote: > hi, ralf, in the latest master branch of linux-mips git repo, seems > there is a need to select the SYS_SUPPORTS_HOTPLUG_CPU option in every > uni-processor board, otherwise, the suspend/hibernation can not be used, > because you have set: > > config ARCH_HIBERNATION_POSSIBLE > def_bool y > depends on SYS_SUPPORTS_HOTPLUG_CPU > > config ARCH_SUSPEND_POSSIBLE > def_bool y > depends on SYS_SUPPORTS_HOTPLUG_CPU > > so, the board-specific patch must be pushed by the maintainers of > boards. and if the board support SMP, they must implement the > mips-specific hotplug support, is this right? I have selected > SYS_SUPPORTS_HOTPLUG_CPU in LEMOTE_FULONG and will push a relative patch > later. I think below patch should take care of this problem. It simply assumes that all uniprocessor systems support suspend and hibernate. That's an assumption that I'm not to unhappy with though it may force us to fix a few systems. Ralf Signed-off-by: Ralf Baechle arch/mips/Kconfig | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index df1a92a..3ca0fe1 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -2168,11 +2168,11 @@ menu "Power management options" config ARCH_HIBERNATION_POSSIBLE def_bool y - depends on SYS_SUPPORTS_HOTPLUG_CPU + depends on SYS_SUPPORTS_HOTPLUG_CPU || !SMP config ARCH_SUSPEND_POSSIBLE def_bool y - depends on SYS_SUPPORTS_HOTPLUG_CPU + depends on SYS_SUPPORTS_HOTPLUG_CPU || !SMP source "kernel/power/Kconfig" From ralf@h5.dl5rb.org.uk Wed Jul 1 20:26:33 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 01 Jul 2009 20:26:40 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:56522 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1491784AbZGAS0c (ORCPT ); Wed, 1 Jul 2009 20:26:32 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id n61IKqah023611; Wed, 1 Jul 2009 19:20:52 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id n61IKpnQ023609; Wed, 1 Jul 2009 19:20:51 +0100 Date: Wed, 1 Jul 2009 19:20:51 +0100 From: Ralf Baechle To: David Daney Cc: "Maciej W. Rozycki" , linux-mips@linux-mips.org Subject: Re: [PATCH] MIPS: Define __arch_swab64 for all mips r2 cpus (v2). Message-ID: <20090701182051.GB23121@linux-mips.org> References: <1246294455-26866-1-git-send-email-ddaney@caviumnetworks.com> <20090629193454.GA23430@linux-mips.org> <4A4AB845.1030906@caviumnetworks.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <4A4AB845.1030906@caviumnetworks.com> User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23582 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Tue, Jun 30, 2009 at 06:13:41PM -0700, David Daney wrote: > The problem with CPU_MIPS64_R2 in the kernel is that it means two > unrelated things: > > 1) The cpu can execute all mips64r2 ISA instructions. > > 2) The cpu requires that all worse case cache and execution hazards are > handled. > > In the case of the Octeon processors, #1 is true, but we can get better > performance by omitting many of the hazard barriers because they are > unneeded. The most performance sensitive hazard barriers are the ones in the TLB exception handlers and they're now being handled in C code in tlbex.c which mostly does runtime decissions. I suspect the remaining hazard barriers are not a big performance thing anymore. Ralf From ralf@h5.dl5rb.org.uk Wed Jul 1 20:46:08 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 01 Jul 2009 20:46:15 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:33556 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1491816AbZGASqI (ORCPT ); Wed, 1 Jul 2009 20:46:08 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id n61IeRsC024347; Wed, 1 Jul 2009 19:40:27 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id n61IeRiE024346; Wed, 1 Jul 2009 19:40:27 +0100 Date: Wed, 1 Jul 2009 19:40:27 +0100 From: Ralf Baechle To: "Maciej W. Rozycki" Cc: David Daney , linux-mips@linux-mips.org Subject: Re: [PATCH] MIPS: Define __arch_swab64 for all mips r2 cpus (v2). Message-ID: <20090701184027.GC23121@linux-mips.org> References: <1246294455-26866-1-git-send-email-ddaney@caviumnetworks.com> <20090629193454.GA23430@linux-mips.org> <4A4AB845.1030906@caviumnetworks.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23583 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Wed, Jul 01, 2009 at 02:36:31AM +0100, Maciej W. Rozycki wrote: > > The problem with CPU_MIPS64_R2 in the kernel is that it means two unrelated > > things: > > > > 1) The cpu can execute all mips64r2 ISA instructions. > > > > 2) The cpu requires that all worse case cache and execution hazards are > > handled. > > > > In the case of the Octeon processors, #1 is true, but we can get better > > performance by omitting many of the hazard barriers because they are unneeded. > > Which is why I think a split of the semantics would be a good idea. That's the idea since a long time. There are far less uses of CONFIG_CPU_* than there used to be historically - and usually they're a bug or at least should be considered one. Ralf From David.Daney@caviumnetworks.com Wed Jul 1 21:15:12 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 01 Jul 2009 21:15:18 +0200 (CEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:50818 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1491856AbZGATPM (ORCPT ); Wed, 1 Jul 2009 21:15:12 +0200 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,2,2,3503) id ; Wed, 01 Jul 2009 15:09:17 -0400 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Wed, 1 Jul 2009 12:09:10 -0700 Received: from dd1.caveonetworks.com ([64.169.86.201]) by caexch01.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Wed, 1 Jul 2009 12:09:10 -0700 Message-ID: <4A4BB456.9090404@caviumnetworks.com> Date: Wed, 01 Jul 2009 12:09:10 -0700 From: David Daney User-Agent: Thunderbird 2.0.0.21 (X11/20090320) MIME-Version: 1.0 To: Yong Zhang CC: linux-kernel@vger.kernel.org, ralf@linux-mips.org, linux-mips Subject: Re: [PATCH] MIPS: o32 application running on 64bit kernel core dump References: <16bd35f2910f585740f4764fa1e80bf31c80d576.1242178813.git.yong.zhang@windriver.com> In-Reply-To: <16bd35f2910f585740f4764fa1e80bf31c80d576.1242178813.git.yong.zhang@windriver.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 01 Jul 2009 19:09:10.0540 (UTC) FILETIME=[6A2574C0:01C9FA7F] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23584 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Yong Zhang wrote: > If an o32 application crashes and generates a core dump on > a 64 bit kernel, the core file will not be correctly > recognized. This is because ELF_CORE_COPY_REGS and > ELF_CORE_COPY_TASK_REGS are not correctly defined for o32 > and will use the default register set which would > be CONFIG_64BIT in asm/elf.h. > > So we'll switch to use the right register defines in > this situation by checking for WANT_COMPAT_REG_H and > use the right defines of ELF_CORE_COPY_REGS and > ELF_CORE_COPY_TASK_REGS. This patch looks plausible. How was it tested? Can you still obtain good core files with at 32-bit kernel? Are usable core files obtained for all three ABIs on 64-bit kernels? Other than that, I have only the one comment below. Thanks, David Daney > > Signed-off-by: Yong Zhang > --- > arch/mips/include/asm/elf.h | 4 ++++ > arch/mips/include/asm/reg.h | 2 +- > arch/mips/kernel/binfmt_elfo32.c | 20 +++++++++++++++++--- > 3 files changed, 22 insertions(+), 4 deletions(-) > > diff --git a/arch/mips/include/asm/elf.h b/arch/mips/include/asm/elf.h > index d58f128..7990694 100644 > --- a/arch/mips/include/asm/elf.h > +++ b/arch/mips/include/asm/elf.h > @@ -316,9 +316,13 @@ extern void elf_dump_regs(elf_greg_t *, struct pt_regs *regs); > extern int dump_task_regs(struct task_struct *, elf_gregset_t *); > extern int dump_task_fpu(struct task_struct *, elf_fpregset_t *); > > +#ifndef ELF_CORE_COPY_REGS > #define ELF_CORE_COPY_REGS(elf_regs, regs) \ > elf_dump_regs((elf_greg_t *)&(elf_regs), regs); > +#endif > +#ifndef ELF_CORE_COPY_TASK_REGS > #define ELF_CORE_COPY_TASK_REGS(tsk, elf_regs) dump_task_regs(tsk, elf_regs) > +#endif > #define ELF_CORE_COPY_FPREGS(tsk, elf_fpregs) \ > dump_task_fpu(tsk, elf_fpregs) > > diff --git a/arch/mips/include/asm/reg.h b/arch/mips/include/asm/reg.h > index 634b55d..910e71a 100644 > --- a/arch/mips/include/asm/reg.h > +++ b/arch/mips/include/asm/reg.h > @@ -69,7 +69,7 @@ > > #endif > > -#ifdef CONFIG_64BIT > +#if defined(CONFIG_64BIT) && !defined(WANT_COMPAT_REG_H) > > #define EF_R0 0 > #define EF_R1 1 > diff --git a/arch/mips/kernel/binfmt_elfo32.c b/arch/mips/kernel/binfmt_elfo32.c > index e1333d7..53bc6b4 100644 > --- a/arch/mips/kernel/binfmt_elfo32.c > +++ b/arch/mips/kernel/binfmt_elfo32.c > @@ -53,6 +53,23 @@ typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG]; > #define ELF_ET_DYN_BASE (TASK32_SIZE / 3 * 2) > > #include > + > +/* > + * When this file is selected, we are definitely running a 64bit kernel. > + * So using the right regs define in asm/reg.h > + */ > +#define WANT_COMPAT_REG_H > + > +/* These MUST be defined before elf.h gets included */ > +extern void elf32_core_copy_regs(elf_gregset_t grp, struct pt_regs *regs); > +#define ELF_CORE_COPY_REGS(_dest, _regs) elf32_core_copy_regs(_dest, _regs); > +#define ELF_CORE_COPY_TASK_REGS(_tsk, _dest) \ > +({ \ > + int __res = 1; \ > + elf32_core_copy_regs((*_dest), (task_pt_regs(_tsk))); \ > + __res; \ Why does __res exist? Can't you have that last line just be '1;'? > +}) > + > #include > #include > #include > @@ -110,9 +127,6 @@ jiffies_to_compat_timeval(unsigned long jiffies, struct compat_timeval *value) > value->tv_usec = rem / NSEC_PER_USEC; > } > > -#undef ELF_CORE_COPY_REGS > -#define ELF_CORE_COPY_REGS(_dest, _regs) elf32_core_copy_regs(_dest, _regs); > - > void elf32_core_copy_regs(elf_gregset_t grp, struct pt_regs *regs) > { > int i; From ralf@h5.dl5rb.org.uk Wed Jul 1 21:25:13 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 01 Jul 2009 21:25:21 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:53287 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1491864AbZGATZN (ORCPT ); Wed, 1 Jul 2009 21:25:13 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id n61JJZtT026862; Wed, 1 Jul 2009 20:19:35 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id n61JJY8J026861; Wed, 1 Jul 2009 20:19:34 +0100 Date: Wed, 1 Jul 2009 20:19:34 +0100 From: Ralf Baechle To: Yong Zhang Cc: linux-kernel@vger.kernel.org, linux-mips@linux-mips.org Subject: Re: [PATCH] MIPS: o32 application running on 64bit kernel core dump Message-ID: <20090701191934.GE23121@linux-mips.org> References: <16bd35f2910f585740f4764fa1e80bf31c80d576.1242178813.git.yong.zhang@windriver.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <16bd35f2910f585740f4764fa1e80bf31c80d576.1242178813.git.yong.zhang@windriver.com> User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23585 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Wed, Jul 01, 2009 at 09:35:39AM +0800, Yong Zhang wrote: > +/* These MUST be defined before elf.h gets included */ This sort of ordering bug seems to become a tradition. I think it may be a good idea to insert a check like this: #ifdef ELF_CORE_COPY_REGS #error ELF_CORE_COPY_REGS should not be defined yet! #endif > +extern void elf32_core_copy_regs(elf_gregset_t grp, struct pt_regs *regs); > +#define ELF_CORE_COPY_REGS(_dest, _regs) elf32_core_copy_regs(_dest, _regs); > +#define ELF_CORE_COPY_TASK_REGS(_tsk, _dest) \ > +({ \ > + int __res = 1; \ > + elf32_core_copy_regs((*_dest), (task_pt_regs(_tsk))); \ Be very careful with parentheses in macros. This line should probably become: elf32_core_copy_regs(*(_dest), task_pt_regs(_tsk)); \ The changes to the first argument to bullet prof the macro and the change to the second one for cosmetic reasons. Ralf From etienne.basset@numericable.fr Wed Jul 1 23:36:08 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 01 Jul 2009 23:36:15 +0200 (CEST) Received: from smtp1.tech.numericable.fr ([82.216.111.37]:57770 "EHLO smtp1.tech.numericable.fr" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1491918AbZGAVgI (ORCPT ); Wed, 1 Jul 2009 23:36:08 +0200 Received: from [192.168.0.10] (abo-105-52-68.mts.modulonet.fr [85.68.52.105]) by smtp1.tech.numericable.fr (Postfix) with ESMTP id 1AC85E0811; Wed, 1 Jul 2009 23:30:32 +0200 (CEST) Message-ID: <4A4BD577.2080609@numericable.fr> Date: Wed, 01 Jul 2009 23:30:31 +0200 From: Etienne Basset User-Agent: Thunderbird 2.0.0.22 (X11/20090608) MIME-Version: 1.0 To: Jeff Chua CC: Bartlomiej Zolnierkiewicz , wuzhangjin@gmail.com, David Miller , rjw@sisk.pl, linux-kernel@vger.kernel.org, kernel-testers@vger.kernel.org, Ralf Baechle , linux-mips@linux-mips.org, linux-ide@vger.kernel.org Subject: Re: [Bug #13663] suspend to ram regression (IDE related) References: <1246459661.9660.40.camel@falcon> <200907011821.26091.bzolnier@gmail.com> <200907011829.16850.bzolnier@gmail.com> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23586 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: etienne.basset@numericable.fr Precedence: bulk X-list: linux-mips Jeff Chua wrote: > On Thu, Jul 2, 2009 at 12:29 AM, Bartlomiej > Zolnierkiewicz wrote: >> Here is the more complete version, also taking into the account changes >> in ide_intr() and ide_timer_expiry(): > > This works great for. Survived STR, STD. I just applied on top vanilla > latest Linus's git pull. Nothing else to revert. > > Thanks, > Jeff. > > i confirm, this works for me too :) thanks, Etienne >> --- >> drivers/ide/ide-io.c | 15 ++++++++++----- >> 1 file changed, 10 insertions(+), 5 deletions(-) >> >> Index: b/drivers/ide/ide-io.c >> =================================================================== >> --- a/drivers/ide/ide-io.c >> +++ b/drivers/ide/ide-io.c >> @@ -532,7 +532,8 @@ repeat: >> >> if (startstop == ide_stopped) { >> rq = hwif->rq; >> - hwif->rq = NULL; >> + if ((drive->dev_flags & IDE_DFLAG_BLOCKED) == 0) >> + hwif->rq = NULL; >> goto repeat; >> } >> } else >> @@ -679,8 +680,10 @@ void ide_timer_expiry (unsigned long dat >> spin_lock_irq(&hwif->lock); >> enable_irq(hwif->irq); >> if (startstop == ide_stopped && hwif->polling == 0) { >> - rq_in_flight = hwif->rq; >> - hwif->rq = NULL; >> + if ((drive->dev_flags & IDE_DFLAG_BLOCKED) == 0) { >> + rq_in_flight = hwif->rq; >> + hwif->rq = NULL; >> + } >> ide_unlock_port(hwif); >> plug_device = 1; >> } >> @@ -856,8 +859,10 @@ irqreturn_t ide_intr (int irq, void *dev >> */ >> if (startstop == ide_stopped && hwif->polling == 0) { >> BUG_ON(hwif->handler); >> - rq_in_flight = hwif->rq; >> - hwif->rq = NULL; >> + if ((drive->dev_flags & IDE_DFLAG_BLOCKED) == 0) { >> + rq_in_flight = hwif->rq; >> + hwif->rq = NULL; >> + } >> ide_unlock_port(hwif); >> plug_device = 1; >> } >> From ralf@h5.dl5rb.org.uk Thu Jul 2 01:53:01 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 02 Jul 2009 01:53:08 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:42116 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1491948AbZGAXxB (ORCPT ); Thu, 2 Jul 2009 01:53:01 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id n61NlJJk003966; Thu, 2 Jul 2009 00:47:19 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id n61NlI0c003964; Thu, 2 Jul 2009 00:47:18 +0100 Date: Thu, 2 Jul 2009 00:47:18 +0100 From: Ralf Baechle To: Yong Zhang Cc: linux-kernel@vger.kernel.org, linux-mips@linux-mips.org Subject: Re: [PATCH] MIPS: o32 application running on 64bit kernel core dump Message-ID: <20090701234718.GA3933@linux-mips.org> References: <16bd35f2910f585740f4764fa1e80bf31c80d576.1242178813.git.yong.zhang@windriver.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <16bd35f2910f585740f4764fa1e80bf31c80d576.1242178813.git.yong.zhang@windriver.com> User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23587 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Wed, Jul 01, 2009 at 09:35:39AM +0800, Yong Zhang wrote: Patch applied with the one issue in the macro I pointed out earlier fixed. Thanks, Ralf From wuzhangjin@gmail.com Thu Jul 2 03:10:04 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 02 Jul 2009 03:10:11 +0200 (CEST) Received: from mail-pz0-f173.google.com ([209.85.222.173]:39043 "EHLO mail-pz0-f173.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1491827AbZGBBKE (ORCPT ); Thu, 2 Jul 2009 03:10:04 +0200 Received: by pzk3 with SMTP id 3so1174409pzk.22 for ; Wed, 01 Jul 2009 18:04:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:subject:from:reply-to:to:cc :in-reply-to:references:content-type:organization:date:message-id :mime-version:x-mailer:content-transfer-encoding; bh=RrPGQz9qgBMKhapgSx/vhoOKEgRPEbAeS1ED2A/H7Z0=; b=Cz72FvicexAy7xbEOm19V7ghrCEAPazM9qh4h4PPabwDnTC8rybZhmzx+fNfGgMI1S OMDO9f7k4CyRihpTTVRT//XU9abtpaCOYBlpHCVn5wdMNFBfY/ZmoFC2pwcsYcEhLvim tXsjhCRl8LtQjbFPEzxRfrhh2pJLOE8PjiBAI= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=subject:from:reply-to:to:cc:in-reply-to:references:content-type :organization:date:message-id:mime-version:x-mailer :content-transfer-encoding; b=Fe4akczbiOVs5KgfUQS2DF/z8ZVvTVuGkuSPwkxufTof9tSvUknb7F2ELv64O0839r UPx4e7Jyzfat+OLpHuWRXPDbgVBNCWotedr4skM7SBx7TBMaHKMGPCKzQmAotXFRq7nn WE5pl3IBq5TPmDq7VASXb89qEoIpd7sXuNyFY= Received: by 10.115.107.5 with SMTP id j5mr16281321wam.105.1246496660985; Wed, 01 Jul 2009 18:04:20 -0700 (PDT) Received: from ?172.16.2.101? ([222.92.8.142]) by mx.google.com with ESMTPS id v9sm3094307wah.1.2009.07.01.18.04.16 (version=TLSv1/SSLv3 cipher=RC4-MD5); Wed, 01 Jul 2009 18:04:20 -0700 (PDT) Subject: Re: [BUG] MIPS: Hibernation in the latest linux-mips:master branch not work From: Wu Zhangjin Reply-To: wuzhangjin@gmail.com To: Ralf Baechle Cc: LKML , linux-mips@linux-mips.org, Pavel Machek In-Reply-To: <20090701180715.GA23121@linux-mips.org> References: <1246372868.19049.17.camel@falcon> <20090630144540.GA18212@linux-mips.org> <1246374687.20482.10.camel@falcon> <20090701180715.GA23121@linux-mips.org> Content-Type: text/plain Organization: DSLab, Lanzhou University, China Date: Thu, 02 Jul 2009 09:04:07 +0800 Message-Id: <1246496647.9660.46.camel@falcon> Mime-Version: 1.0 X-Mailer: Evolution 2.26.1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23588 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips On Wed, 2009-07-01 at 19:07 +0100, Ralf Baechle wrote: > On Tue, Jun 30, 2009 at 11:11:27PM +0800, Wu Zhangjin wrote: > > > hi, ralf, in the latest master branch of linux-mips git repo, seems > > there is a need to select the SYS_SUPPORTS_HOTPLUG_CPU option in every > > uni-processor board, otherwise, the suspend/hibernation can not be used, > > because you have set: > > > > config ARCH_HIBERNATION_POSSIBLE > > def_bool y > > depends on SYS_SUPPORTS_HOTPLUG_CPU > > > > config ARCH_SUSPEND_POSSIBLE > > def_bool y > > depends on SYS_SUPPORTS_HOTPLUG_CPU > > > > so, the board-specific patch must be pushed by the maintainers of > > boards. and if the board support SMP, they must implement the > > mips-specific hotplug support, is this right? I have selected > > SYS_SUPPORTS_HOTPLUG_CPU in LEMOTE_FULONG and will push a relative patch > > later. > > I think below patch should take care of this problem. It simply assumes > that all uniprocessor systems support suspend and hibernate. That's an > assumption that I'm not to unhappy with though it may force us to fix a > few systems. > This patch is better. Thanks! Wu Zhangjin > Ralf > > Signed-off-by: Ralf Baechle > > arch/mips/Kconfig | 4 ++-- > 1 files changed, 2 insertions(+), 2 deletions(-) > > diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig > index df1a92a..3ca0fe1 100644 > --- a/arch/mips/Kconfig > +++ b/arch/mips/Kconfig > @@ -2168,11 +2168,11 @@ menu "Power management options" > > config ARCH_HIBERNATION_POSSIBLE > def_bool y > - depends on SYS_SUPPORTS_HOTPLUG_CPU > + depends on SYS_SUPPORTS_HOTPLUG_CPU || !SMP > > config ARCH_SUSPEND_POSSIBLE > def_bool y > - depends on SYS_SUPPORTS_HOTPLUG_CPU > + depends on SYS_SUPPORTS_HOTPLUG_CPU || !SMP > > source "kernel/power/Kconfig" > From yong.zhang@windriver.com Thu Jul 2 03:28:57 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 02 Jul 2009 03:29:03 +0200 (CEST) Received: from mail.windriver.com ([147.11.1.11]:62379 "EHLO mail.wrs.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1491827AbZGBB25 (ORCPT ); Thu, 2 Jul 2009 03:28:57 +0200 Received: from ALA-MAIL03.corp.ad.wrs.com (ala-mail03 [147.11.57.144]) by mail.wrs.com (8.13.6/8.13.6) with ESMTP id n621N93P004531; Wed, 1 Jul 2009 18:23:09 -0700 (PDT) Received: from ala-mail06.corp.ad.wrs.com ([147.11.57.147]) by ALA-MAIL03.corp.ad.wrs.com with Microsoft SMTPSVC(6.0.3790.1830); Wed, 1 Jul 2009 18:23:08 -0700 Received: from [128.224.158.160] ([128.224.158.160]) by ala-mail06.corp.ad.wrs.com with Microsoft SMTPSVC(6.0.3790.1830); Wed, 1 Jul 2009 18:23:08 -0700 Message-ID: <4A4C0C91.2010407@windriver.com> Date: Thu, 02 Jul 2009 09:25:37 +0800 From: Yong Zhang User-Agent: Thunderbird 2.0.0.22 (X11/20090608) MIME-Version: 1.0 To: David Daney CC: linux-kernel@vger.kernel.org, ralf@linux-mips.org, linux-mips Subject: Re: [PATCH] MIPS: o32 application running on 64bit kernel core dump References: <16bd35f2910f585740f4764fa1e80bf31c80d576.1242178813.git.yong.zhang@windriver.com> <4A4BB456.9090404@caviumnetworks.com> In-Reply-To: <4A4BB456.9090404@caviumnetworks.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 02 Jul 2009 01:23:08.0790 (UTC) FILETIME=[A862B160:01C9FAB3] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23589 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: yong.zhang@windriver.com Precedence: bulk X-list: linux-mips David Daney wrote: > Yong Zhang wrote: >> If an o32 application crashes and generates a core dump on >> a 64 bit kernel, the core file will not be correctly >> recognized. This is because ELF_CORE_COPY_REGS and >> ELF_CORE_COPY_TASK_REGS are not correctly defined for o32 >> and will use the default register set which would >> be CONFIG_64BIT in asm/elf.h. >> >> So we'll switch to use the right register defines in >> this situation by checking for WANT_COMPAT_REG_H and >> use the right defines of ELF_CORE_COPY_REGS and >> ELF_CORE_COPY_TASK_REGS. > > This patch looks plausible. How was it tested? > > Can you still obtain good core files with at 32-bit kernel? Yeah, I also have tested 32-bit kernel. Actually this doesn't have any side effect on that. > > Are usable core files obtained for all three ABIs on 64-bit kernels? Tested for all three ABIs, and all does the right thing. Testing code is below: /* test.c */ #include #include #include #include #include #include #include #include #include #define MAX_THREADS 4 void foo7() { int *i=0; char c =*i; } void foo6() { int c6=1000; int i=9; while(c6--) { i=i*9+1; } printf("inside foo6\n"); foo7(); } void foo5() { int c5=1000; int i=9; while(c5--) { i=i*9+1; } printf("inside foo5\n"); foo6(); } void foo4() { int c4=1000; int i=9; while(c4--) { i=i*9+1; } printf("inside foo4\n"); foo5(); } void foo3() { int c3=1000; int i=9; while(c3--) { i=i*9+1; } printf("inside foo3\n"); foo4(); } void foo2() { int c2=1000; int i=9; while (c2--) { i=i*9+1; } printf("inside foo2\n"); foo3(); } void *foo1(void* arg) { sleep(10); foo2(); } int main() { int i=0; pthread_t *threads; pthread_attr_t pthread_attr; printf("inside main\n"); threads=(pthread_t *)malloc(MAX_THREADS*sizeof(*threads)); pthread_attr_init(&pthread_attr); for(i=0;i > Other than that, I have only the one comment below. > > Thanks, > David Daney > > >> +#define ELF_CORE_COPY_TASK_REGS(_tsk, _dest) \ >> +({ \ >> + int __res = 1; \ >> + elf32_core_copy_regs((*_dest), (task_pt_regs(_tsk))); \ >> + __res; \ > > Why does __res exist? Can't you have that last line just be '1;'? Sounds good. Just be '1;' is good. Thanks, Yong > >> +}) >> + >> #include >> #include >> #include >> @@ -110,9 +127,6 @@ jiffies_to_compat_timeval(unsigned long jiffies, >> struct compat_timeval *value) >> value->tv_usec = rem / NSEC_PER_USEC; >> } >> >> -#undef ELF_CORE_COPY_REGS >> -#define ELF_CORE_COPY_REGS(_dest, _regs) elf32_core_copy_regs(_dest, >> _regs); >> - >> void elf32_core_copy_regs(elf_gregset_t grp, struct pt_regs *regs) >> { >> int i; > > From wuzhangjin@gmail.com Thu Jul 2 03:52:36 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 02 Jul 2009 03:52:43 +0200 (CEST) Received: from wf-out-1314.google.com ([209.85.200.170]:55221 "EHLO wf-out-1314.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1491973AbZGBBwg (ORCPT ); Thu, 2 Jul 2009 03:52:36 +0200 Received: by wf-out-1314.google.com with SMTP id 28so488735wfa.21 for ; Wed, 01 Jul 2009 18:46:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:subject:from:reply-to:to:cc :in-reply-to:references:content-type:organization:date:message-id :mime-version:x-mailer:content-transfer-encoding; bh=7xsEOcp72isWMSwh6/V5XqI/FtXPTWnPl5IgjfJYIWo=; b=GT4cnpGGDNe1U/DgrZNBWb601fTxiPOEiLlofmsMiyCXEYI1x/bu9Je2HlWMm/hLuV L5kNeVuiMVKwG0uoyC26oqQ0Lco3Rhmy0fZ7PAIJc8fJ9+DS7Z5WBGD5tBt/FQKfrRLj uvaPt+oMrF2FvJRWzW50Gdv4uuNJY9v1u5pW0= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=subject:from:reply-to:to:cc:in-reply-to:references:content-type :organization:date:message-id:mime-version:x-mailer :content-transfer-encoding; b=kIaT/0C+6AQV96irABsQ9Sd/c//0NXNTXCxRyJsAi7FykGCoiIX0lJ96yfIg88588H xpeBaM9ZJUw1favt8ojXcYE7EfpQCmQh3HLSJUAZ+FbeRIcvULtHdweuTEhuQItC/3XL oBY9C98wxWF43V30ydArQcDVXke2wAxO8vV2Q= Received: by 10.142.222.19 with SMTP id u19mr1282919wfg.6.1246499216905; Wed, 01 Jul 2009 18:46:56 -0700 (PDT) Received: from ?172.16.2.101? ([222.92.8.142]) by mx.google.com with ESMTPS id 30sm5615554wfd.3.2009.07.01.18.46.50 (version=TLSv1/SSLv3 cipher=RC4-MD5); Wed, 01 Jul 2009 18:46:55 -0700 (PDT) Subject: Re: [Bug #13663] suspend to ram regression (IDE related) From: Wu Zhangjin Reply-To: wuzhangjin@gmail.com To: Bartlomiej Zolnierkiewicz Cc: Jeff Chua , Etienne Basset , David Miller , rjw@sisk.pl, linux-kernel@vger.kernel.org, kernel-testers@vger.kernel.org, Ralf Baechle , linux-mips@linux-mips.org, linux-ide@vger.kernel.org In-Reply-To: <200907011829.16850.bzolnier@gmail.com> References: <1246459661.9660.40.camel@falcon> <200907011821.26091.bzolnier@gmail.com> <200907011829.16850.bzolnier@gmail.com> Content-Type: text/plain Organization: DSLab, Lanzhou University, China Date: Thu, 02 Jul 2009 09:46:43 +0800 Message-Id: <1246499203.9660.52.camel@falcon> Mime-Version: 1.0 X-Mailer: Evolution 2.26.1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23590 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips On Wed, 2009-07-01 at 18:29 +0200, Bartlomiej Zolnierkiewicz wrote: > On Wednesday 01 July 2009 18:21:25 Bartlomiej Zolnierkiewicz wrote: > > On Wednesday 01 July 2009 16:47:41 Wu Zhangjin wrote: > > > On Wed, 2009-07-01 at 22:31 +0800, Jeff Chua wrote: > > > > On Tue, Jun 30, 2009 at 12:21 AM, Jeff Chua wrote: > > > > > > > > > I just tried, and it "seems" to work. Will try a few more cycles. > > > > > > > > STD/STR survived quite a few cycles now. Patch seems to be doing the > > > > right thing. > > > > > > > > On Mon, Jun 29, 2009 at 11:51 PM, Etienne > > > > Basset wrote: > > > > > > > > > To have STR/resume work with current git, I have to : > > > > > > > > > 1) apply Bart's patch > > > > > > > > This is not yet in Linus's tree. And much needed to really fix the problem. > > > > > > > > > 2) revert this commit : a1317f714af7aed60ddc182d0122477cbe36ee9b > > > > > > > > > > Yes, This commit must be reverted, otherwise, STD/Hibernation will not > > > work either. I have tested it on two different loongson-based machines: > > > fuloong2e box and yeeloong2f netbook.(loongson is mips compatiable) > > > > Since it seems like Dave is taking his sweet time with doing the revert > > I stared at the code a bit more and I think that I finally found the bug > > (thanks to your debugging work for giving me the right hint!). > > > > The patch needs to take into the account a new code introduced by the recent > > block layer changes (commit 8f6205cd572fece673da0255d74843680f67f879): > > > > @@ -555,8 +560,11 @@ repeat: > > startstop = start_request(drive, rq); > > spin_lock_irq(&hwif->lock); > > > > - if (startstop == ide_stopped) > > + if (startstop == ide_stopped) { > > + rq = hwif->rq; > > + hwif->rq = NULL; > > goto repeat; > > + } > > } else > > goto plug_device; > > out: > > > > and not zero hwif->rq if the device is blocked. > > > > Could you try the attached patch and see if it fixes the issue? > > Here is the more complete version, also taking into the account changes > in ide_intr() and ide_timer_expiry(): > Sorry, I can not apply this patch directly, which original version did you use? I used the one in the master branch of linux-mips development git repository. commit 5a4f13fad1ab5bd08dea78fc55321e429d83cddf Merge: ec9c45d e18ed14 Author: Linus Torvalds Date: Mon Jun 29 20:07:43 2009 -0700 Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/ide-2.6 * git://git.kernel.org/pub/scm/linux/kernel/git/davem/ide-2.6: ide: memory overrun in ide_get_identity_ioctl() on big endian machines using ioctl HDIO_OBSOLETE_IDENTITY ide: fix resume for CONFIG_BLK_DEV_IDEACPI=y ide-cd: handle fragmented packet commands gracefully ide: always kill the whole request on error ide: fix ide_kill_rq() for special ide-{floppy,tape} driver requests it this too old? should i merge another git repository? I have tried to apply it manually, but unfortunately, also not work. any other patch needed? Thanks! Wu Zhangjin > --- > drivers/ide/ide-io.c | 15 ++++++++++----- > 1 file changed, 10 insertions(+), 5 deletions(-) > > Index: b/drivers/ide/ide-io.c > =================================================================== > --- a/drivers/ide/ide-io.c > +++ b/drivers/ide/ide-io.c > @@ -532,7 +532,8 @@ repeat: > > if (startstop == ide_stopped) { > rq = hwif->rq; > - hwif->rq = NULL; > + if ((drive->dev_flags & IDE_DFLAG_BLOCKED) == 0) > + hwif->rq = NULL; > goto repeat; > } > } else > @@ -679,8 +680,10 @@ void ide_timer_expiry (unsigned long dat > spin_lock_irq(&hwif->lock); > enable_irq(hwif->irq); > if (startstop == ide_stopped && hwif->polling == 0) { > - rq_in_flight = hwif->rq; > - hwif->rq = NULL; > + if ((drive->dev_flags & IDE_DFLAG_BLOCKED) == 0) { > + rq_in_flight = hwif->rq; > + hwif->rq = NULL; > + } > ide_unlock_port(hwif); > plug_device = 1; > } > @@ -856,8 +859,10 @@ irqreturn_t ide_intr (int irq, void *dev > */ > if (startstop == ide_stopped && hwif->polling == 0) { > BUG_ON(hwif->handler); > - rq_in_flight = hwif->rq; > - hwif->rq = NULL; > + if ((drive->dev_flags & IDE_DFLAG_BLOCKED) == 0) { > + rq_in_flight = hwif->rq; > + hwif->rq = NULL; > + } > ide_unlock_port(hwif); > plug_device = 1; > } From jeff.chua.linux@gmail.com Thu Jul 2 04:15:35 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 02 Jul 2009 04:15:43 +0200 (CEST) Received: from mail-yx0-f183.google.com ([209.85.210.183]:64032 "EHLO mail-yx0-f183.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1491983AbZGBCPf (ORCPT ); Thu, 2 Jul 2009 04:15:35 +0200 Received: by yxe13 with SMTP id 13so2056394yxe.22 for ; Wed, 01 Jul 2009 19:09:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:in-reply-to:references :date:message-id:subject:from:to:cc:content-type :content-transfer-encoding; bh=KREtBvwPX95nV0FGVeLJLXCxgj2OAq7XBEd8/pj+y5M=; b=CmsQMfgeGIIrl8wxXZHiRMGsS/0NtJoD4/3S0c3IH/jJ2WGLzbL8Bu4osJOd3OrYOJ Q2SmozQIXkvg/7TiiDwGN/5cDb5vt2MTNRox1V4eHy6vAM15wfPjLKC8BVy8qQK38J1h i80Eyn2yv+JlnrPS0xKmpCbQC5KCUl6Tdf1qU= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type:content-transfer-encoding; b=vB0YX826xDiUjFU2tjN7+kAo+4fsDePfooX77XAcyPQBgmlE3l3++E3o4fEX/AMelV lrEBgDWwBup5FyMrV4esEUfHjDE3PdLIw7jrYBYzHzLCfMY7Z7tbin2NZ8nH9Ru6bbta CC/ymDOiLrl1j5TTpb1fv5FwWzrYaxJNAGBp4= MIME-Version: 1.0 Received: by 10.90.80.4 with SMTP id d4mr2063840agb.4.1246500594117; Wed, 01 Jul 2009 19:09:54 -0700 (PDT) In-Reply-To: <1246499203.9660.52.camel@falcon> References: <1246459661.9660.40.camel@falcon> <200907011821.26091.bzolnier@gmail.com> <200907011829.16850.bzolnier@gmail.com> <1246499203.9660.52.camel@falcon> Date: Thu, 2 Jul 2009 10:09:53 +0800 Message-ID: Subject: Re: [Bug #13663] suspend to ram regression (IDE related) From: Jeff Chua To: wuzhangjin@gmail.com Cc: Bartlomiej Zolnierkiewicz , Etienne Basset , David Miller , rjw@sisk.pl, linux-kernel@vger.kernel.org, kernel-testers@vger.kernel.org, Ralf Baechle , linux-mips@linux-mips.org, linux-ide@vger.kernel.org Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23591 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jeff.chua.linux@gmail.com Precedence: bulk X-list: linux-mips On Thu, Jul 2, 2009 at 9:46 AM, Wu Zhangjin wrote: > it this too old? should i merge another git repository? > I have tried to apply it manually, but unfortunately, also not work. any > other patch needed? You need to be undo those two patches below ... > On Mon, Jun 29, 2009 at 11:51 PM, Etienne Basset > To have STR/resume work with current git, I have to : > 1) apply Bart's patch > 2) revert this commit : a1317f714af7aed60ddc182d0122477cbe36ee9b or try to pull from Linus's tree and try again. Latest is now ... commit d960eea974f5e500c0dcb95a934239cc1f481cfd Author: Randy Dunlap Date: Mon Jun 29 14:54:11 2009 -0700 kernel-doc: move ignoring kmemcheck Jeff. From raghu@mips.com Thu Jul 2 04:45:50 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 02 Jul 2009 04:45:57 +0200 (CEST) Received: from dns1.mips.com ([63.167.95.197]:35883 "EHLO dns1.mips.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1491990AbZGBCpu (ORCPT ); Thu, 2 Jul 2009 04:45:50 +0200 Received: from MTVEXCHANGE.mips.com ([192.168.36.60]) by dns1.mips.com (8.13.8/8.13.8) with ESMTP id n622e4Ca016271 for ; Wed, 1 Jul 2009 19:40:04 -0700 Received: from mercury.mips.com ([192.168.64.101]) by MTVEXCHANGE.mips.com with Microsoft SMTPSVC(6.0.3790.3959); Wed, 1 Jul 2009 19:40:04 -0700 Received: from [192.168.65.97] (linux-raghu [192.168.65.97]) by mercury.mips.com (8.13.5/8.13.5) with ESMTP id n622e4lO005974; Wed, 1 Jul 2009 19:40:04 -0700 (PDT) From: Raghu Gandham Subject: [PATCH 00/15] Port changes from linux-mti To: linux-mips@linux-mips.org Cc: chris@mips.com Date: Wed, 01 Jul 2009 19:39:38 -0700 Message-ID: <20090702023938.23268.65453.stgit@linux-raghu> User-Agent: StGIT/0.14.3 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 02 Jul 2009 02:40:04.0444 (UTC) FILETIME=[678799C0:01C9FABE] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23592 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: raghu@mips.com Precedence: bulk X-list: linux-mips The following series of patches port the changes in linux-mti.git repository to the head of tree. --- Chris Dearman (9): Added coherentio command line option for DMA_NONCOHERENT kernel Add missing memory barriers for correct operation of amon_cpu_start Port of GIC related changes from MTI branch. Add debug prints during CPU intialization. APRP Patch04: Propagate final value of max_low_pfn to max_pfn [MTI] Enable PIIX4 PCI2.1 compliancy on Malta [MTI] MIPS secondary cache supports 64 byte line size. Fix accesses to device registers on MIPS boards [MTI] Clean up SPRAM support a little Jaidev Patwardhan (2): Avoid queing multiple reschedule IPI's in SMTC Avoid accessing GCMP registers when they are not present Kurt Martin (1): Do not rely on the initial state of TC/VPE bindings when doing cross VPE writes Raghu Gandham (1): Fix compiler warning in vpe.c Robin Randhawa (2): Fix absd emulation Due to some broken bitfiles, we can't trust IntCtl arch/mips/Kconfig | 1 arch/mips/include/asm/gcmpregs.h | 18 ++-- arch/mips/include/asm/gic.h | 188 ++++--------------------------------- arch/mips/include/asm/irq.h | 1 arch/mips/include/asm/smtc_ipi.h | 5 + arch/mips/include/asm/spram.h | 10 ++ arch/mips/kernel/cpu-probe.c | 8 -- arch/mips/kernel/irq-gic.c | 116 +++++++++-------------- arch/mips/kernel/setup.c | 3 - arch/mips/kernel/smp-mt.c | 10 ++ arch/mips/kernel/smtc.c | 45 ++++++++- arch/mips/kernel/spram.c | 5 - arch/mips/kernel/traps.c | 4 + arch/mips/kernel/vpe.c | 3 - arch/mips/math-emu/dp_simple.c | 11 +- arch/mips/math-emu/sp_simple.c | 3 - arch/mips/mti-malta/malta-amon.c | 7 + arch/mips/mti-malta/malta-int.c | 115 ++++++++++++++--------- arch/mips/mti-malta/malta-pci.c | 14 ++- arch/mips/mti-malta/malta-setup.c | 111 ++++++++++++++++++++++ 20 files changed, 351 insertions(+), 327 deletions(-) create mode 100644 arch/mips/include/asm/spram.h From raghu@mips.com Thu Jul 2 04:46:15 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 02 Jul 2009 04:46:23 +0200 (CEST) Received: from dns1.mips.com ([63.167.95.197]:35884 "EHLO dns1.mips.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1491996AbZGBCqC (ORCPT ); Thu, 2 Jul 2009 04:46:02 +0200 Received: from MTVEXCHANGE.mips.com ([192.168.36.60]) by dns1.mips.com (8.13.8/8.13.8) with ESMTP id n622eKX5016281 for ; Wed, 1 Jul 2009 19:40:20 -0700 Received: from mercury.mips.com ([192.168.64.101]) by MTVEXCHANGE.mips.com with Microsoft SMTPSVC(6.0.3790.3959); Wed, 1 Jul 2009 19:40:19 -0700 Received: from [192.168.65.97] (linux-raghu [192.168.65.97]) by mercury.mips.com (8.13.5/8.13.5) with ESMTP id n622eJhb005976; Wed, 1 Jul 2009 19:40:19 -0700 (PDT) From: Raghu Gandham Subject: [PATCH 01/15] Due to some broken bitfiles, we can't trust IntCtl To: linux-mips@linux-mips.org Cc: chris@mips.com Date: Wed, 01 Jul 2009 19:39:54 -0700 Message-ID: <20090702023954.23268.98988.stgit@linux-raghu> In-Reply-To: <20090702023938.23268.65453.stgit@linux-raghu> References: <20090702023938.23268.65453.stgit@linux-raghu> User-Agent: StGIT/0.14.3 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 02 Jul 2009 02:40:20.0038 (UTC) FILETIME=[70D30E60:01C9FABE] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23593 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: raghu@mips.com Precedence: bulk X-list: linux-mips From: Robin Randhawa Signed-off-by: Chris Dearman --- arch/mips/include/asm/irq.h | 1 + arch/mips/kernel/traps.c | 4 ++++ 2 files changed, 5 insertions(+), 0 deletions(-) diff --git a/arch/mips/include/asm/irq.h b/arch/mips/include/asm/irq.h index 09b08d0..ca0b5ed 100644 --- a/arch/mips/include/asm/irq.h +++ b/arch/mips/include/asm/irq.h @@ -158,6 +158,7 @@ extern void free_irqno(unsigned int irq); * IE7. Since R2 their number has to be read from the c0_intctl register. */ #define CP0_LEGACY_COMPARE_IRQ 7 +#define CP0_LEGACY_PERFCNT_IRQ 7 extern int cp0_compare_irq; extern int cp0_perfcount_irq; diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index 08f1edf..0b6e328 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -1538,7 +1538,11 @@ void __cpuinit per_cpu_trap_init(void) */ if (cpu_has_mips_r2) { cp0_compare_irq = (read_c0_intctl() >> 29) & 7; + if (!cp0_compare_irq) + cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ; cp0_perfcount_irq = (read_c0_intctl() >> 26) & 7; + if (!cp0_perfcount_irq) + cp0_perfcount_irq = CP0_LEGACY_PERFCNT_IRQ; if (cp0_perfcount_irq == cp0_compare_irq) cp0_perfcount_irq = -1; } else { From raghu@mips.com Thu Jul 2 04:46:40 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 02 Jul 2009 04:46:48 +0200 (CEST) Received: from dns1.mips.com ([63.167.95.197]:35885 "EHLO dns1.mips.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1491990AbZGBCqS (ORCPT ); Thu, 2 Jul 2009 04:46:18 +0200 Received: from MTVEXCHANGE.mips.com ([192.168.36.60]) by dns1.mips.com (8.13.8/8.13.8) with ESMTP id n622eZ3D016284 for ; Wed, 1 Jul 2009 19:40:35 -0700 Received: from mercury.mips.com ([192.168.64.101]) by MTVEXCHANGE.mips.com with Microsoft SMTPSVC(6.0.3790.3959); Wed, 1 Jul 2009 19:40:35 -0700 Received: from [192.168.65.97] (linux-raghu [192.168.65.97]) by mercury.mips.com (8.13.5/8.13.5) with ESMTP id n622eZO0005978; Wed, 1 Jul 2009 19:40:35 -0700 (PDT) From: Raghu Gandham Subject: [PATCH 02/15] Fix absd emulation To: linux-mips@linux-mips.org Cc: chris@mips.com Date: Wed, 01 Jul 2009 19:40:09 -0700 Message-ID: <20090702024009.23268.62738.stgit@linux-raghu> In-Reply-To: <20090702023938.23268.65453.stgit@linux-raghu> References: <20090702023938.23268.65453.stgit@linux-raghu> User-Agent: StGIT/0.14.3 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 02 Jul 2009 02:40:35.0460 (UTC) FILETIME=[7A044440:01C9FABE] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23594 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: raghu@mips.com Precedence: bulk X-list: linux-mips From: Robin Randhawa Signed-off-by: Chris Dearman --- arch/mips/math-emu/dp_simple.c | 11 ++++------- arch/mips/math-emu/sp_simple.c | 3 --- 2 files changed, 4 insertions(+), 10 deletions(-) diff --git a/arch/mips/math-emu/dp_simple.c b/arch/mips/math-emu/dp_simple.c index 1c555e6..6ff4655 100644 --- a/arch/mips/math-emu/dp_simple.c +++ b/arch/mips/math-emu/dp_simple.c @@ -76,15 +76,12 @@ ieee754dp ieee754dp_abs(ieee754dp x) CLEARCX; FLUSHXDP; + /* Clear sign ALWAYS, irrespective of NaN */ + DPSIGN(x) = 0; + if (xc == IEEE754_CLASS_SNAN) { SETCX(IEEE754_INVALID_OPERATION); - return ieee754dp_nanxcpt(ieee754dp_indef(), "neg"); + return ieee754dp_nanxcpt(ieee754dp_indef(), "abs"); } - - if (ieee754dp_isnan(x)) /* but not infinity */ - return ieee754dp_nanxcpt(x, "abs", x); - - /* quick fix up */ - DPSIGN(x) = 0; return x; } diff --git a/arch/mips/math-emu/sp_simple.c b/arch/mips/math-emu/sp_simple.c index 770f0f4..cdec1a2 100644 --- a/arch/mips/math-emu/sp_simple.c +++ b/arch/mips/math-emu/sp_simple.c @@ -61,9 +61,6 @@ ieee754sp ieee754sp_neg(ieee754sp x) SPSIGN(y) = SPSIGN(x); return ieee754sp_nanxcpt(y, "neg"); } - - if (ieee754sp_isnan(x)) /* but not infinity */ - return ieee754sp_nanxcpt(x, "neg", x); return x; } From raghu@mips.com Thu Jul 2 04:47:05 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 02 Jul 2009 04:47:13 +0200 (CEST) Received: from dns1.mips.com ([63.167.95.197]:35887 "EHLO dns1.mips.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492001AbZGBCqd (ORCPT ); Thu, 2 Jul 2009 04:46:33 +0200 Received: from MTVEXCHANGE.mips.com ([192.168.36.60]) by dns1.mips.com (8.13.8/8.13.8) with ESMTP id n622ephT016293 for ; Wed, 1 Jul 2009 19:40:51 -0700 Received: from mercury.mips.com ([192.168.64.101]) by MTVEXCHANGE.mips.com with Microsoft SMTPSVC(6.0.3790.3959); Wed, 1 Jul 2009 19:40:50 -0700 Received: from [192.168.65.97] (linux-raghu [192.168.65.97]) by mercury.mips.com (8.13.5/8.13.5) with ESMTP id n622eoBo005980; Wed, 1 Jul 2009 19:40:50 -0700 (PDT) From: Raghu Gandham Subject: [PATCH 03/15] [MTI] Clean up SPRAM support a little To: linux-mips@linux-mips.org Cc: chris@mips.com Date: Wed, 01 Jul 2009 19:40:25 -0700 Message-ID: <20090702024025.23268.1460.stgit@linux-raghu> In-Reply-To: <20090702023938.23268.65453.stgit@linux-raghu> References: <20090702023938.23268.65453.stgit@linux-raghu> User-Agent: StGIT/0.14.3 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 02 Jul 2009 02:40:50.0928 (UTC) FILETIME=[833C7F00:01C9FABE] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23595 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: raghu@mips.com Precedence: bulk X-list: linux-mips From: Chris Dearman Signed-off-by: Chris Dearman --- arch/mips/include/asm/spram.h | 10 ++++++++++ arch/mips/kernel/cpu-probe.c | 8 +------- arch/mips/kernel/spram.c | 5 ++--- 3 files changed, 13 insertions(+), 10 deletions(-) create mode 100644 arch/mips/include/asm/spram.h diff --git a/arch/mips/include/asm/spram.h b/arch/mips/include/asm/spram.h new file mode 100644 index 0000000..0b89006 --- /dev/null +++ b/arch/mips/include/asm/spram.h @@ -0,0 +1,10 @@ +#ifndef _MIPS_SPRAM_H +#define _MIPS_SPRAM_H + +#ifdef CONFIG_CPU_MIPSR2 +extern __init void spram_config(void); +#else +static inline void spram_config(void) { }; +#endif /* CONFIG_CPU_MIPSR2 */ + +#endif /* _MIPS_SPRAM_H */ diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index 1abe990..2d35217 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -23,7 +23,7 @@ #include #include #include - +#include /* * Not all of the MIPS CPUs have the "wait" instruction available. Moreover, * the implementation of the "wait" feature differs between CPU families. This @@ -711,12 +711,6 @@ static void __cpuinit decode_configs(struct cpuinfo_mips *c) mips_probe_watch_registers(c); } -#ifdef CONFIG_CPU_MIPSR2 -extern void spram_config(void); -#else -static inline void spram_config(void) {} -#endif - static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu) { decode_configs(c); diff --git a/arch/mips/kernel/spram.c b/arch/mips/kernel/spram.c index 6ddb507..1821d12 100644 --- a/arch/mips/kernel/spram.c +++ b/arch/mips/kernel/spram.c @@ -13,7 +13,6 @@ #include #include -#include #include #include #include @@ -198,8 +197,7 @@ static __cpuinit void probe_spram(char *type, offset += 2 * SPRAM_TAG_STRIDE; } } - -__cpuinit void spram_config(void) +void __cpuinit spram_config(void) { struct cpuinfo_mips *c = ¤t_cpu_data; unsigned int config0; @@ -208,6 +206,7 @@ __cpuinit void spram_config(void) case CPU_24K: case CPU_34K: case CPU_74K: + case CPU_1004K: config0 = read_c0_config(); /* FIXME: addresses are Malta specific */ if (config0 & (1<<24)) { From raghu@mips.com Thu Jul 2 04:47:30 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 02 Jul 2009 04:47:38 +0200 (CEST) Received: from dns1.mips.com ([63.167.95.197]:35890 "EHLO dns1.mips.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492010AbZGBCqt (ORCPT ); Thu, 2 Jul 2009 04:46:49 +0200 Received: from MTVEXCHANGE.mips.com ([192.168.36.60]) by dns1.mips.com (8.13.8/8.13.8) with ESMTP id n622f6x9016301 for ; Wed, 1 Jul 2009 19:41:06 -0700 Received: from mercury.mips.com ([192.168.64.101]) by MTVEXCHANGE.mips.com with Microsoft SMTPSVC(6.0.3790.3959); Wed, 1 Jul 2009 19:41:06 -0700 Received: from [192.168.65.97] (linux-raghu [192.168.65.97]) by mercury.mips.com (8.13.5/8.13.5) with ESMTP id n622f6Yc005998; Wed, 1 Jul 2009 19:41:06 -0700 (PDT) From: Raghu Gandham Subject: [PATCH 04/15] Fix accesses to device registers on MIPS boards To: linux-mips@linux-mips.org Cc: chris@mips.com Date: Wed, 01 Jul 2009 19:40:40 -0700 Message-ID: <20090702024040.23268.97655.stgit@linux-raghu> In-Reply-To: <20090702023938.23268.65453.stgit@linux-raghu> References: <20090702023938.23268.65453.stgit@linux-raghu> User-Agent: StGIT/0.14.3 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 02 Jul 2009 02:41:06.0381 (UTC) FILETIME=[8C726FD0:01C9FABE] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23596 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: raghu@mips.com Precedence: bulk X-list: linux-mips From: Chris Dearman This fixes the remaining problems introduced by f197465384bf7ef1af184c2ed1a4e268911a91e3 (incorrect access length & byteswapping in bigendian mode) Signed-off-by: Chris Dearman (chris@mips.com) --- arch/mips/mti-malta/malta-int.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/mips/mti-malta/malta-int.c b/arch/mips/mti-malta/malta-int.c index a8756f8..e9ba8b3 100644 --- a/arch/mips/mti-malta/malta-int.c +++ b/arch/mips/mti-malta/malta-int.c @@ -87,7 +87,7 @@ static inline int mips_pcibios_iack(void) dummy = BONITO_PCIMAP_CFG; iob(); /* sync */ - irq = readl((u32 *)_pcictrl_bonito_pcicfg); + irq = __raw_readl((u32 *)_pcictrl_bonito_pcicfg); iob(); /* sync */ irq &= 0xff; BONITO_PCIMAP_CFG = 0; From raghu@mips.com Thu Jul 2 04:48:04 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 02 Jul 2009 04:48:11 +0200 (CEST) Received: from dns1.mips.com ([63.167.95.197]:39573 "EHLO dns1.mips.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492011AbZGBCrF (ORCPT ); Thu, 2 Jul 2009 04:47:05 +0200 Received: from MTVEXCHANGE.mips.com ([192.168.36.60]) by dns1.mips.com (8.13.8/8.13.8) with ESMTP id n622fNfl016307 for ; Wed, 1 Jul 2009 19:41:23 -0700 Received: from mercury.mips.com ([192.168.64.101]) by MTVEXCHANGE.mips.com with Microsoft SMTPSVC(6.0.3790.3959); Wed, 1 Jul 2009 19:41:22 -0700 Received: from [192.168.65.97] (linux-raghu [192.168.65.97]) by mercury.mips.com (8.13.5/8.13.5) with ESMTP id n622fLWp006000; Wed, 1 Jul 2009 19:41:21 -0700 (PDT) From: Raghu Gandham Subject: [PATCH 05/15] [MTI] MIPS secondary cache supports 64 byte line size. To: linux-mips@linux-mips.org Cc: chris@mips.com Date: Wed, 01 Jul 2009 19:40:56 -0700 Message-ID: <20090702024055.23268.93650.stgit@linux-raghu> In-Reply-To: <20090702023938.23268.65453.stgit@linux-raghu> References: <20090702023938.23268.65453.stgit@linux-raghu> User-Agent: StGIT/0.14.3 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 02 Jul 2009 02:41:22.0397 (UTC) FILETIME=[95FE48D0:01C9FABE] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23597 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: raghu@mips.com Precedence: bulk X-list: linux-mips From: Chris Dearman Signed-off-by: Chris Dearman --- arch/mips/Kconfig | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index df1a92a..60c7235 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -1012,6 +1012,7 @@ config MIPS_L1_CACHE_SHIFT int default "4" if MACH_DECSTATION || MIKROTIK_RB532 default "7" if SGI_IP22 || SGI_IP27 || SGI_IP28 || SNI_RM || CPU_CAVIUM_OCTEON + default "6" if MIPS_CPU_SCACHE default "4" if PMC_MSP4200_EVAL default "5" From raghu@mips.com Thu Jul 2 04:48:37 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 02 Jul 2009 04:48:44 +0200 (CEST) Received: from dns1.mips.com ([63.167.95.197]:39575 "EHLO dns1.mips.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492014AbZGBCrU (ORCPT ); Thu, 2 Jul 2009 04:47:20 +0200 Received: from MTVEXCHANGE.mips.com ([192.168.36.60]) by dns1.mips.com (8.13.8/8.13.8) with ESMTP id n622fcCS016316 for ; Wed, 1 Jul 2009 19:41:38 -0700 Received: from mercury.mips.com ([192.168.64.101]) by MTVEXCHANGE.mips.com with Microsoft SMTPSVC(6.0.3790.3959); Wed, 1 Jul 2009 19:41:37 -0700 Received: from [192.168.65.97] (linux-raghu [192.168.65.97]) by mercury.mips.com (8.13.5/8.13.5) with ESMTP id n622fb1T006002; Wed, 1 Jul 2009 19:41:37 -0700 (PDT) From: Raghu Gandham Subject: [PATCH 06/15] [MTI] Enable PIIX4 PCI2.1 compliancy on Malta To: linux-mips@linux-mips.org Cc: chris@mips.com Date: Wed, 01 Jul 2009 19:41:12 -0700 Message-ID: <20090702024111.23268.66642.stgit@linux-raghu> In-Reply-To: <20090702023938.23268.65453.stgit@linux-raghu> References: <20090702023938.23268.65453.stgit@linux-raghu> User-Agent: StGIT/0.14.3 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 02 Jul 2009 02:41:37.0647 (UTC) FILETIME=[9F153FF0:01C9FABE] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23598 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: raghu@mips.com Precedence: bulk X-list: linux-mips From: Chris Dearman Signed-off-by: Chris Dearman --- arch/mips/mti-malta/malta-setup.c | 11 +++++++++++ 1 files changed, 11 insertions(+), 0 deletions(-) diff --git a/arch/mips/mti-malta/malta-setup.c b/arch/mips/mti-malta/malta-setup.c index dc78b89..69f5f9c 100644 --- a/arch/mips/mti-malta/malta-setup.c +++ b/arch/mips/mti-malta/malta-setup.c @@ -223,3 +223,14 @@ void __init plat_mem_setup(void) board_be_init = malta_be_init; board_be_handler = malta_be_handler; } +/* Enable PCI 2.1 compatibility in PIIX4 */ +static void __init quirk_dlcsetup(struct pci_dev *dev) +{ + u8 odlc, ndlc; + (void) pci_read_config_byte(dev, 0x82, &odlc); + /* Enable passive releases and delayed transaction */ + ndlc = odlc | 7; + (void) pci_write_config_byte(dev, 0x82, ndlc); +} +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_0, + quirk_dlcsetup); From raghu@mips.com Thu Jul 2 04:49:01 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 02 Jul 2009 04:49:08 +0200 (CEST) Received: from dns1.mips.com ([63.167.95.197]:39577 "EHLO dns1.mips.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492001AbZGBCrf (ORCPT ); Thu, 2 Jul 2009 04:47:35 +0200 Received: from MTVEXCHANGE.mips.com ([192.168.36.60]) by dns1.mips.com (8.13.8/8.13.8) with ESMTP id n622frmO016322 for ; Wed, 1 Jul 2009 19:41:53 -0700 Received: from mercury.mips.com ([192.168.64.101]) by MTVEXCHANGE.mips.com with Microsoft SMTPSVC(6.0.3790.3959); Wed, 1 Jul 2009 19:41:52 -0700 Received: from [192.168.65.97] (linux-raghu [192.168.65.97]) by mercury.mips.com (8.13.5/8.13.5) with ESMTP id n622fqfw006004; Wed, 1 Jul 2009 19:41:52 -0700 (PDT) From: Raghu Gandham Subject: [PATCH 07/15] APRP Patch04: Propagate final value of max_low_pfn to max_pfn To: linux-mips@linux-mips.org Cc: chris@mips.com Date: Wed, 01 Jul 2009 19:41:27 -0700 Message-ID: <20090702024127.23268.94902.stgit@linux-raghu> In-Reply-To: <20090702023938.23268.65453.stgit@linux-raghu> References: <20090702023938.23268.65453.stgit@linux-raghu> User-Agent: StGIT/0.14.3 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 02 Jul 2009 02:41:53.0053 (UTC) FILETIME=[A84404D0:01C9FABE] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23599 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: raghu@mips.com Precedence: bulk X-list: linux-mips From: Chris Dearman Signed-off-by: Chris Dearman --- arch/mips/kernel/setup.c | 3 ++- 1 files changed, 2 insertions(+), 1 deletions(-) diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c index 2950b97..1e9862d 100644 --- a/arch/mips/kernel/setup.c +++ b/arch/mips/kernel/setup.c @@ -326,7 +326,6 @@ static void __init bootmem_init(void) /* * Determine low and high memory ranges */ - max_pfn = max_low_pfn; if (max_low_pfn > PFN_DOWN(HIGHMEM_START)) { #ifdef CONFIG_HIGHMEM highstart_pfn = PFN_DOWN(HIGHMEM_START); @@ -334,6 +333,8 @@ static void __init bootmem_init(void) #endif max_low_pfn = PFN_DOWN(HIGHMEM_START); } + /* Propagate final value of max_low_pfn to max_pfn */ + max_pfn = max_low_pfn; /* * Initialize the boot-time allocator with low memory only. From raghu@mips.com Thu Jul 2 04:49:26 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 02 Jul 2009 04:49:34 +0200 (CEST) Received: from dns1.mips.com ([63.167.95.197]:39580 "EHLO dns1.mips.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492015AbZGBCrv (ORCPT ); Thu, 2 Jul 2009 04:47:51 +0200 Received: from MTVEXCHANGE.mips.com ([192.168.36.60]) by dns1.mips.com (8.13.8/8.13.8) with ESMTP id n622g9Xt016328 for ; Wed, 1 Jul 2009 19:42:09 -0700 Received: from mercury.mips.com ([192.168.64.101]) by MTVEXCHANGE.mips.com with Microsoft SMTPSVC(6.0.3790.3959); Wed, 1 Jul 2009 19:42:08 -0700 Received: from [192.168.65.97] (linux-raghu [192.168.65.97]) by mercury.mips.com (8.13.5/8.13.5) with ESMTP id n622g85i006006; Wed, 1 Jul 2009 19:42:08 -0700 (PDT) From: Raghu Gandham Subject: [PATCH 08/15] Fix compiler warning in vpe.c To: linux-mips@linux-mips.org Cc: chris@mips.com Date: Wed, 01 Jul 2009 19:41:42 -0700 Message-ID: <20090702024142.23268.72001.stgit@linux-raghu> In-Reply-To: <20090702023938.23268.65453.stgit@linux-raghu> References: <20090702023938.23268.65453.stgit@linux-raghu> User-Agent: StGIT/0.14.3 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 02 Jul 2009 02:42:08.0662 (UTC) FILETIME=[B191C360:01C9FABE] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23600 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: raghu@mips.com Precedence: bulk X-list: linux-mips Signed-off-by: Raghu Gandham (raghu@mips.com) --- arch/mips/kernel/vpe.c | 3 ++- 1 files changed, 2 insertions(+), 1 deletions(-) diff --git a/arch/mips/kernel/vpe.c b/arch/mips/kernel/vpe.c index 07b9ec2..3d4ef84 100644 --- a/arch/mips/kernel/vpe.c +++ b/arch/mips/kernel/vpe.c @@ -327,7 +327,8 @@ static void layout_sections(struct module *mod, const Elf_Ehdr * hdr, || (s->sh_flags & masks[m][1]) || s->sh_entsize != ~0UL) continue; - s->sh_entsize = get_offset(&mod->core_size, s); + s->sh_entsize = + get_offset((unsigned long *)&mod->core_size, s); } if (m == 0) From raghu@mips.com Thu Jul 2 04:49:51 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 02 Jul 2009 04:49:59 +0200 (CEST) Received: from dns1.mips.com ([63.167.95.197]:39583 "EHLO dns1.mips.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492004AbZGBCsH (ORCPT ); Thu, 2 Jul 2009 04:48:07 +0200 Received: from MTVEXCHANGE.mips.com ([192.168.36.60]) by dns1.mips.com (8.13.8/8.13.8) with ESMTP id n622gOTm016337 for ; Wed, 1 Jul 2009 19:42:24 -0700 Received: from mercury.mips.com ([192.168.64.101]) by MTVEXCHANGE.mips.com with Microsoft SMTPSVC(6.0.3790.3959); Wed, 1 Jul 2009 19:42:24 -0700 Received: from [192.168.65.97] (linux-raghu [192.168.65.97]) by mercury.mips.com (8.13.5/8.13.5) with ESMTP id n622gN7D006008; Wed, 1 Jul 2009 19:42:24 -0700 (PDT) From: Raghu Gandham Subject: [PATCH 09/15] Add debug prints during CPU intialization. To: linux-mips@linux-mips.org Cc: chris@mips.com Date: Wed, 01 Jul 2009 19:41:58 -0700 Message-ID: <20090702024158.23268.37787.stgit@linux-raghu> In-Reply-To: <20090702023938.23268.65453.stgit@linux-raghu> References: <20090702023938.23268.65453.stgit@linux-raghu> User-Agent: StGIT/0.14.3 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 02 Jul 2009 02:42:24.0240 (UTC) FILETIME=[BADAC700:01C9FABE] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23601 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: raghu@mips.com Precedence: bulk X-list: linux-mips From: Chris Dearman Signed-off-by: Chris Dearman --- arch/mips/kernel/smp-mt.c | 10 +++++++++- 1 files changed, 9 insertions(+), 1 deletions(-) diff --git a/arch/mips/kernel/smp-mt.c b/arch/mips/kernel/smp-mt.c index 6f7ee5a..c6c7b54 100644 --- a/arch/mips/kernel/smp-mt.c +++ b/arch/mips/kernel/smp-mt.c @@ -152,7 +152,7 @@ static void vsmp_send_ipi_mask(cpumask_t mask, unsigned int action) static void __cpuinit vsmp_init_secondary(void) { extern int gic_present; - + pr_debug("SMPMT: CPU%d: vsmp_init_secondary\n", smp_processor_id()); /* This is Malta specific: IPI,performance and timer inetrrupts */ if (gic_present) change_c0_status(ST0_IM, STATUSF_IP3 | STATUSF_IP4 | @@ -164,6 +164,8 @@ static void __cpuinit vsmp_init_secondary(void) static void __cpuinit vsmp_smp_finish(void) { + pr_debug("SMPMT: CPU%d: vsmp_smp_finish\n", smp_processor_id()); + /* CDFIXME: remove this? */ write_c0_compare(read_c0_count() + (8* mips_hpt_frequency/HZ)); @@ -178,6 +180,7 @@ static void __cpuinit vsmp_smp_finish(void) static void vsmp_cpus_done(void) { + pr_debug("SMPMT: CPU%d: vsmp_cpus_done\n", smp_processor_id()); } /* @@ -191,6 +194,8 @@ static void vsmp_cpus_done(void) static void __cpuinit vsmp_boot_secondary(int cpu, struct task_struct *idle) { struct thread_info *gp = task_thread_info(idle); + pr_debug("SMPMT: CPU%d: vsmp_boot_secondary cpu %d\n", + smp_processor_id(), cpu); dvpe(); set_c0_mvpcontrol(MVPCONTROL_VPC); @@ -232,6 +237,7 @@ static void __init vsmp_smp_setup(void) unsigned int mvpconf0, ntc, tc, ncpu = 0; unsigned int nvpe; + pr_debug("SMPMT: CPU%d: vsmp_smp_setup\n", smp_processor_id()); #ifdef CONFIG_MIPS_MT_FPAFF /* If we have an FPU, enroll ourselves in the FPU-full mask */ if (cpu_has_fpu) @@ -272,6 +278,8 @@ static void __init vsmp_smp_setup(void) static void __init vsmp_prepare_cpus(unsigned int max_cpus) { + pr_debug("SMPMT: CPU%d: vsmp_prepare_cpus %d\n", + smp_processor_id(), max_cpus); mips_mt_set_cpuoptions(); } From raghu@mips.com Thu Jul 2 04:50:17 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 02 Jul 2009 04:50:25 +0200 (CEST) Received: from dns1.mips.com ([63.167.95.197]:39584 "EHLO dns1.mips.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492020AbZGBCsW (ORCPT ); Thu, 2 Jul 2009 04:48:22 +0200 Received: from MTVEXCHANGE.mips.com ([192.168.36.60]) by dns1.mips.com (8.13.8/8.13.8) with ESMTP id n622geuq016340 for ; Wed, 1 Jul 2009 19:42:40 -0700 Received: from mercury.mips.com ([192.168.64.101]) by MTVEXCHANGE.mips.com with Microsoft SMTPSVC(6.0.3790.3959); Wed, 1 Jul 2009 19:42:39 -0700 Received: from [192.168.65.97] (linux-raghu [192.168.65.97]) by mercury.mips.com (8.13.5/8.13.5) with ESMTP id n622gd7N006010; Wed, 1 Jul 2009 19:42:39 -0700 (PDT) From: Raghu Gandham Subject: [PATCH 10/15] Port of GIC related changes from MTI branch. To: linux-mips@linux-mips.org Cc: chris@mips.com Date: Wed, 01 Jul 2009 19:42:14 -0700 Message-ID: <20090702024213.23268.52185.stgit@linux-raghu> In-Reply-To: <20090702023938.23268.65453.stgit@linux-raghu> References: <20090702023938.23268.65453.stgit@linux-raghu> User-Agent: StGIT/0.14.3 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 02 Jul 2009 02:42:39.0756 (UTC) FILETIME=[C41A54C0:01C9FABE] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23602 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: raghu@mips.com Precedence: bulk X-list: linux-mips From: Chris Dearman Signed-off-by: Chris Dearman --- arch/mips/include/asm/gcmpregs.h | 18 ++-- arch/mips/include/asm/gic.h | 188 ++++---------------------------------- arch/mips/kernel/irq-gic.c | 116 +++++++++-------------- arch/mips/mti-malta/malta-int.c | 97 ++++++++++++-------- arch/mips/mti-malta/malta-pci.c | 14 ++- 5 files changed, 142 insertions(+), 291 deletions(-) diff --git a/arch/mips/include/asm/gcmpregs.h b/arch/mips/include/asm/gcmpregs.h index 36fd969..c0cf76a 100644 --- a/arch/mips/include/asm/gcmpregs.h +++ b/arch/mips/include/asm/gcmpregs.h @@ -19,15 +19,20 @@ #define GCMP_GDB_OFS 0x8000 /* Global Debug Block */ /* Offsets to individual GCMP registers from GCMP base */ -#define GCMPOFS(block, tag, reg) (GCMP_##block##_OFS + GCMP_##tag##_##reg##_OFS) +#define GCMPOFS(block, tag, reg) \ + (GCMP_##block##_OFS + GCMP_##tag##_##reg##_OFS) +#define GCMPOFSn(block, tag, reg, n) \ + (GCMP_##block##_OFS + GCMP_##tag##_##reg##_OFS(n)) #define GCMPGCBOFS(reg) GCMPOFS(GCB, GCB, reg) +#define GCMPGCBOFSn(reg, n) GCMPOFSn(GCB, GCB, reg, n) #define GCMPCLCBOFS(reg) GCMPOFS(CLCB, CCB, reg) #define GCMPCOCBOFS(reg) GCMPOFS(COCB, CCB, reg) #define GCMPGDBOFS(reg) GCMPOFS(GDB, GDB, reg) /* GCMP register access */ #define GCMPGCB(reg) REGP(_gcmp_base, GCMPGCBOFS(reg)) +#define GCMPGCBn(reg, n) REGP(_gcmp_base, GCMPGCBOFSn(reg, n)) #define GCMPCLCB(reg) REGP(_gcmp_base, GCMPCLCBOFS(reg)) #define GCMPCOCB(reg) REGP(_gcmp_base, GCMPCOCBOFS(reg)) #define GCMPGDB(reg) REGP(_gcmp_base, GCMPGDBOFS(reg)) @@ -49,10 +54,10 @@ #define GCMP_GCB_GCMPB_GCMPBASE_MSK GCMPGCBMSK(GCMPB_GCMPBASE, 17) #define GCMP_GCB_GCMPB_CMDEFTGT_SHF 0 #define GCMP_GCB_GCMPB_CMDEFTGT_MSK GCMPGCBMSK(GCMPB_CMDEFTGT, 2) -#define GCMP_GCB_GCMPB_CMDEFTGT_MEM 0 -#define GCMP_GCB_GCMPB_CMDEFTGT_MEM1 1 -#define GCMP_GCB_GCMPB_CMDEFTGT_IOCU1 2 -#define GCMP_GCB_GCMPB_CMDEFTGT_IOCU2 3 +#define GCMP_GCB_GCMPB_CMDEFTGT_DISABLED 0 +#define GCMP_GCB_GCMPB_CMDEFTGT_MEM 1 +#define GCMP_GCB_GCMPB_CMDEFTGT_IOCU1 2 +#define GCMP_GCB_GCMPB_CMDEFTGT_IOCU2 3 #define GCMP_GCB_CCMC_OFS 0x0010 /* Global CM Control */ #define GCMP_GCB_GCSRAP_OFS 0x0020 /* Global CSR Access Privilege */ #define GCMP_GCB_GCSRAP_CMACCESS_SHF 0 @@ -115,5 +120,6 @@ #define GCMP_CCB_DBGGROUP_OFS 0x0100 /* DebugBreak Group */ extern int __init gcmp_probe(unsigned long, unsigned long); - +extern int __init gcmp_niocu(void); +extern void __init gcmp_setregion(int, unsigned long, unsigned long, int); #endif /* _ASM_GCMPREGS_H */ diff --git a/arch/mips/include/asm/gic.h b/arch/mips/include/asm/gic.h index 10292e3..9b9436a 100644 --- a/arch/mips/include/asm/gic.h +++ b/arch/mips/include/asm/gic.h @@ -12,7 +12,6 @@ #define _ASM_GICREGS_H #undef GICISBYTELITTLEENDIAN -#define GICISWORDLITTLEENDIAN /* Constants */ #define GIC_POL_POS 1 @@ -20,11 +19,7 @@ #define GIC_TRIG_EDGE 1 #define GIC_TRIG_LEVEL 0 -#if CONFIG_SMP #define GIC_NUM_INTRS (24 + NR_CPUS * 2) -#else -#define GIC_NUM_INTRS 32 -#endif #define MSK(n) ((1 << (n)) - 1) #define REG32(addr) (*(volatile unsigned int *) (addr)) @@ -70,13 +65,13 @@ #define USM_VISIBLE_SECTION_SIZE 0x10000 /* Register Map for Shared Section */ -#if defined(CONFIG_CPU_LITTLE_ENDIAN) || defined(GICISWORDLITTLEENDIAN) #define GIC_SH_CONFIG_OFS 0x0000 /* Shared Global Counter */ #define GIC_SH_COUNTER_31_00_OFS 0x0010 #define GIC_SH_COUNTER_63_32_OFS 0x0014 +#define GIC_SH_REVISIONID_OFS 0x0020 /* Interrupt Polarity */ #define GIC_SH_POL_31_0_OFS 0x0100 @@ -164,24 +159,31 @@ (GIC_SH_INTR_MAP_TO_VPE_BASE_OFS + (32 * (intr)) + (((vpe) / 32) * 4)) #define GIC_SH_MAP_TO_VPE_REG_BIT(vpe) (1 << ((vpe) % 32)) +/* Convert an interrupt number to a byte offset/bit for multi-word registers */ +#define GIC_INTR_OFS(intr) (((intr) / 32)*4) +#define GIC_INTR_BIT(intr) ((intr) % 32) + /* Polarity : Reset Value is always 0 */ #define GIC_SH_SET_POLARITY_OFS 0x0100 #define GIC_SET_POLARITY(intr, pol) \ - GICBIS(GIC_REG_ADDR(SHARED, GIC_SH_SET_POLARITY_OFS + (((intr) / 32) * 4)), (pol) << ((intr) % 32)) + GICBIS(GIC_REG_ADDR(SHARED, GIC_SH_SET_POLARITY_OFS + \ + GIC_INTR_OFS(intr)), (pol) << GIC_INTR_BIT(intr)) /* Triggering : Reset Value is always 0 */ #define GIC_SH_SET_TRIGGER_OFS 0x0180 #define GIC_SET_TRIGGER(intr, trig) \ - GICBIS(GIC_REG_ADDR(SHARED, GIC_SH_SET_TRIGGER_OFS + (((intr) / 32) * 4)), (trig) << ((intr) % 32)) + GICBIS(GIC_REG_ADDR(SHARED, GIC_SH_SET_TRIGGER_OFS + \ + GIC_INTR_OFS(intr)), (trig) << GIC_INTR_BIT(intr)) /* Mask manipulation */ #define GIC_SH_SMASK_OFS 0x0380 -#define GIC_SET_INTR_MASK(intr, val) \ - GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_SMASK_OFS + (((intr) / 32) * 4)), ((val) << ((intr) % 32))) - +#define GIC_SET_INTR_MASK(intr) \ + GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_SMASK_OFS + \ + GIC_INTR_OFS(intr)), 1 << GIC_INTR_BIT(intr)) #define GIC_SH_RMASK_OFS 0x0300 -#define GIC_CLR_INTR_MASK(intr, val) \ - GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_RMASK_OFS + (((intr) / 32) * 4)), ((val) << ((intr) % 32))) +#define GIC_CLR_INTR_MASK(intr) \ + GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_RMASK_OFS + \ + GIC_INTR_OFS(intr)), 1 << GIC_INTR_BIT(intr)) /* Register Map for Local Section */ #define GIC_VPE_CTL_OFS 0x0000 @@ -219,161 +221,6 @@ #define GIC_UMV_SH_COUNTER_31_00_OFS 0x0000 #define GIC_UMV_SH_COUNTER_63_32_OFS 0x0004 -#else /* CONFIG_CPU_BIG_ENDIAN */ - -#define GIC_SH_CONFIG_OFS 0x0000 - -/* Shared Global Counter */ -#define GIC_SH_COUNTER_31_00_OFS 0x0014 -#define GIC_SH_COUNTER_63_32_OFS 0x0010 - -/* Interrupt Polarity */ -#define GIC_SH_POL_31_0_OFS 0x0104 -#define GIC_SH_POL_63_32_OFS 0x0100 -#define GIC_SH_POL_95_64_OFS 0x010c -#define GIC_SH_POL_127_96_OFS 0x0108 -#define GIC_SH_POL_159_128_OFS 0x0114 -#define GIC_SH_POL_191_160_OFS 0x0110 -#define GIC_SH_POL_223_192_OFS 0x011c -#define GIC_SH_POL_255_224_OFS 0x0118 - -/* Edge/Level Triggering */ -#define GIC_SH_TRIG_31_0_OFS 0x0184 -#define GIC_SH_TRIG_63_32_OFS 0x0180 -#define GIC_SH_TRIG_95_64_OFS 0x018c -#define GIC_SH_TRIG_127_96_OFS 0x0188 -#define GIC_SH_TRIG_159_128_OFS 0x0194 -#define GIC_SH_TRIG_191_160_OFS 0x0190 -#define GIC_SH_TRIG_223_192_OFS 0x019c -#define GIC_SH_TRIG_255_224_OFS 0x0198 - -/* Dual Edge Triggering */ -#define GIC_SH_DUAL_31_0_OFS 0x0204 -#define GIC_SH_DUAL_63_32_OFS 0x0200 -#define GIC_SH_DUAL_95_64_OFS 0x020c -#define GIC_SH_DUAL_127_96_OFS 0x0208 -#define GIC_SH_DUAL_159_128_OFS 0x0214 -#define GIC_SH_DUAL_191_160_OFS 0x0210 -#define GIC_SH_DUAL_223_192_OFS 0x021c -#define GIC_SH_DUAL_255_224_OFS 0x0218 - -/* Set/Clear corresponding bit in Edge Detect Register */ -#define GIC_SH_WEDGE_OFS 0x0280 - -/* Reset Mask - Disables Interrupt */ -#define GIC_SH_RMASK_31_0_OFS 0x0304 -#define GIC_SH_RMASK_63_32_OFS 0x0300 -#define GIC_SH_RMASK_95_64_OFS 0x030c -#define GIC_SH_RMASK_127_96_OFS 0x0308 -#define GIC_SH_RMASK_159_128_OFS 0x0314 -#define GIC_SH_RMASK_191_160_OFS 0x0310 -#define GIC_SH_RMASK_223_192_OFS 0x031c -#define GIC_SH_RMASK_255_224_OFS 0x0318 - -/* Set Mask (WO) - Enables Interrupt */ -#define GIC_SH_SMASK_31_0_OFS 0x0384 -#define GIC_SH_SMASK_63_32_OFS 0x0380 -#define GIC_SH_SMASK_95_64_OFS 0x038c -#define GIC_SH_SMASK_127_96_OFS 0x0388 -#define GIC_SH_SMASK_159_128_OFS 0x0394 -#define GIC_SH_SMASK_191_160_OFS 0x0390 -#define GIC_SH_SMASK_223_192_OFS 0x039c -#define GIC_SH_SMASK_255_224_OFS 0x0398 - -/* Global Interrupt Mask Register (RO) - Bit Set == Interrupt enabled */ -#define GIC_SH_MASK_31_0_OFS 0x0404 -#define GIC_SH_MASK_63_32_OFS 0x0400 -#define GIC_SH_MASK_95_64_OFS 0x040c -#define GIC_SH_MASK_127_96_OFS 0x0408 -#define GIC_SH_MASK_159_128_OFS 0x0414 -#define GIC_SH_MASK_191_160_OFS 0x0410 -#define GIC_SH_MASK_223_192_OFS 0x041c -#define GIC_SH_MASK_255_224_OFS 0x0418 - -/* Pending Global Interrupts (RO) */ -#define GIC_SH_PEND_31_0_OFS 0x0484 -#define GIC_SH_PEND_63_32_OFS 0x0480 -#define GIC_SH_PEND_95_64_OFS 0x048c -#define GIC_SH_PEND_127_96_OFS 0x0488 -#define GIC_SH_PEND_159_128_OFS 0x0494 -#define GIC_SH_PEND_191_160_OFS 0x0490 -#define GIC_SH_PEND_223_192_OFS 0x049c -#define GIC_SH_PEND_255_224_OFS 0x0498 - -#define GIC_SH_INTR_MAP_TO_PIN_BASE_OFS 0x0500 - -/* Maps Interrupt X to a Pin */ -#define GIC_SH_MAP_TO_PIN(intr) \ - (GIC_SH_INTR_MAP_TO_PIN_BASE_OFS + (4 * intr)) - -#define GIC_SH_INTR_MAP_TO_VPE_BASE_OFS 0x2004 - -/* - * Maps Interrupt X to a VPE. This is more complex than the LE case, as - * odd and even registers need to be transposed. It does work - trust me! - */ -#define GIC_SH_MAP_TO_VPE_REG_OFF(intr, vpe) \ - (GIC_SH_INTR_MAP_TO_VPE_BASE_OFS + (32 * (intr)) + \ - (((((vpe) / 32) ^ 1) - 1) * 4)) -#define GIC_SH_MAP_TO_VPE_REG_BIT(vpe) (1 << ((vpe) % 32)) - -/* Polarity */ -#define GIC_SH_SET_POLARITY_OFS 0x0100 -#define GIC_SET_POLARITY(intr, pol) \ - GICBIS(GIC_REG_ADDR(SHARED, GIC_SH_SET_POLARITY_OFS + 4 + (((((intr) / 32) ^ 1) - 1) * 4)), (pol) << ((intr) % 32)) - -/* Triggering */ -#define GIC_SH_SET_TRIGGER_OFS 0x0180 -#define GIC_SET_TRIGGER(intr, trig) \ - GICBIS(GIC_REG_ADDR(SHARED, GIC_SH_SET_TRIGGER_OFS + 4 + (((((intr) / 32) ^ 1) - 1) * 4)), (trig) << ((intr) % 32)) - -/* Mask manipulation */ -#define GIC_SH_SMASK_OFS 0x0380 -#define GIC_SET_INTR_MASK(intr, val) \ - GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_SMASK_OFS + 4 + (((((intr) / 32) ^ 1) - 1) * 4)), ((val) << ((intr) % 32))) - -#define GIC_SH_RMASK_OFS 0x0300 -#define GIC_CLR_INTR_MASK(intr, val) \ - GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_RMASK_OFS + 4 + (((((intr) / 32) ^ 1) - 1) * 4)), ((val) << ((intr) % 32))) - -/* Register Map for Local Section */ -#define GIC_VPE_CTL_OFS 0x0000 -#define GIC_VPE_PEND_OFS 0x0004 -#define GIC_VPE_MASK_OFS 0x0008 -#define GIC_VPE_RMASK_OFS 0x000c -#define GIC_VPE_SMASK_OFS 0x0010 -#define GIC_VPE_WD_MAP_OFS 0x0040 -#define GIC_VPE_COMPARE_MAP_OFS 0x0044 -#define GIC_VPE_TIMER_MAP_OFS 0x0048 -#define GIC_VPE_PERFCTR_MAP_OFS 0x0050 -#define GIC_VPE_SWINT0_MAP_OFS 0x0054 -#define GIC_VPE_SWINT1_MAP_OFS 0x0058 -#define GIC_VPE_OTHER_ADDR_OFS 0x0080 -#define GIC_VPE_WD_CONFIG0_OFS 0x0090 -#define GIC_VPE_WD_COUNT0_OFS 0x0094 -#define GIC_VPE_WD_INITIAL0_OFS 0x0098 -#define GIC_VPE_COMPARE_LO_OFS 0x00a4 -#define GIC_VPE_COMPARE_HI_OFS 0x00a0 - -#define GIC_VPE_EIC_SHADOW_SET_BASE 0x0100 -#define GIC_VPE_EIC_SS(intr) \ - (GIC_EIC_SHADOW_SET_BASE + (4 * intr)) - -#define GIC_VPE_EIC_VEC_BASE 0x0800 -#define GIC_VPE_EIC_VEC(intr) \ - (GIC_VPE_EIC_VEC_BASE + (4 * intr)) - -#define GIC_VPE_TENABLE_NMI_OFS 0x1000 -#define GIC_VPE_TENABLE_YQ_OFS 0x1004 -#define GIC_VPE_TENABLE_INT_31_0_OFS 0x1080 -#define GIC_VPE_TENABLE_INT_63_32_OFS 0x1084 - -/* User Mode Visible Section Register Map */ -#define GIC_UMV_SH_COUNTER_31_00_OFS 0x0004 -#define GIC_UMV_SH_COUNTER_63_32_OFS 0x0000 - -#endif /* !LE */ - /* Masks */ #define GIC_SH_CONFIG_COUNTSTOP_SHF 28 #define GIC_SH_CONFIG_COUNTSTOP_MSK (MSK(1) << GIC_SH_CONFIG_COUNTSTOP_SHF) @@ -473,12 +320,13 @@ struct gic_intrmask_regs { * in building ipi_map. */ struct gic_intr_map { - unsigned int intrnum; /* Ext Intr Num */ unsigned int cpunum; /* Directed to this CPU */ unsigned int pin; /* Directed to this Pin */ unsigned int polarity; /* Polarity : +/- */ unsigned int trigtype; /* Trigger : Edge/Levl */ - unsigned int ipiflag; /* Is used for IPI ? */ + unsigned int flags; /* Misc flags */ +#define GIC_FLAG_IPI 0x01 +#define GIC_FLAG_TRANSPARENT 0x02 }; extern void gic_init(unsigned long gic_base_addr, diff --git a/arch/mips/kernel/irq-gic.c b/arch/mips/kernel/irq-gic.c index d2072cd..06d3506 100644 --- a/arch/mips/kernel/irq-gic.c +++ b/arch/mips/kernel/irq-gic.c @@ -14,38 +14,23 @@ static unsigned long _gic_base; -static unsigned int _irqbase, _mapsize, numvpes, numintrs; -static struct gic_intr_map *_intrmap; +static unsigned int _irqbase; +static unsigned int gic_irq_flags[GIC_NUM_INTRS]; +#define GIC_IRQ_FLAG_EDGE 0x0001 -static struct gic_pcpu_mask pcpu_masks[NR_CPUS]; +struct gic_pcpu_mask pcpu_masks[NR_CPUS]; static struct gic_pending_regs pending_regs[NR_CPUS]; static struct gic_intrmask_regs intrmask_regs[NR_CPUS]; -#define gic_wedgeb2bok 0 /* - * Can GIC handle b2b writes to wedge register? - */ -#if gic_wedgeb2bok == 0 -static DEFINE_SPINLOCK(gic_wedgeb2b_lock); -#endif - void gic_send_ipi(unsigned int intr) { -#if gic_wedgeb2bok == 0 - unsigned long flags; -#endif pr_debug("CPU%d: %s status %08x\n", smp_processor_id(), __func__, read_c0_status()); - if (!gic_wedgeb2bok) - spin_lock_irqsave(&gic_wedgeb2b_lock, flags); GICWRITE(GIC_REG(SHARED, GIC_SH_WEDGE), 0x80000000 | intr); - if (!gic_wedgeb2bok) { - (void) GIC_REG(SHARED, GIC_SH_CONFIG); - spin_unlock_irqrestore(&gic_wedgeb2b_lock, flags); - } } /* This is Malta specific and needs to be exported */ -static void vpe_local_setup(unsigned int numvpes) +static void __init vpe_local_setup(unsigned int numvpes) { int i; unsigned long timer_interrupt = 5, perf_interrupt = 5; @@ -105,44 +90,34 @@ unsigned int gic_get_int(void) static unsigned int gic_irq_startup(unsigned int irq) { - pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq); irq -= _irqbase; - GIC_SET_INTR_MASK(irq, 1); + pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq); + GIC_SET_INTR_MASK(irq); return 0; } static void gic_irq_ack(unsigned int irq) { -#if gic_wedgeb2bok == 0 - unsigned long flags; -#endif - pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq); irq -= _irqbase; - GIC_CLR_INTR_MASK(irq, 1); + pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq); + GIC_CLR_INTR_MASK(irq); - if (_intrmap[irq].trigtype == GIC_TRIG_EDGE) { - if (!gic_wedgeb2bok) - spin_lock_irqsave(&gic_wedgeb2b_lock, flags); + if (gic_irq_flags[irq] & GIC_IRQ_FLAG_EDGE) GICWRITE(GIC_REG(SHARED, GIC_SH_WEDGE), irq); - if (!gic_wedgeb2bok) { - (void) GIC_REG(SHARED, GIC_SH_CONFIG); - spin_unlock_irqrestore(&gic_wedgeb2b_lock, flags); - } - } } static void gic_mask_irq(unsigned int irq) { - pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq); irq -= _irqbase; - GIC_CLR_INTR_MASK(irq, 1); + pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq); + GIC_CLR_INTR_MASK(irq); } static void gic_unmask_irq(unsigned int irq) { - pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq); irq -= _irqbase; - GIC_SET_INTR_MASK(irq, 1); + pr_debug("CPU%d: %s: irq%d\n", smp_processor_id(), __func__, irq); + GIC_SET_INTR_MASK(irq); } #ifdef CONFIG_SMP @@ -155,9 +130,8 @@ static int gic_set_affinity(unsigned int irq, const struct cpumask *cpumask) unsigned long flags; int i; - pr_debug(KERN_DEBUG "%s called\n", __func__); irq -= _irqbase; - + pr_debug(KERN_DEBUG "%s(%d) called\n", __func__, irq); cpumask_and(&tmp, cpumask, cpu_online_mask); if (cpus_empty(tmp)) return -1; @@ -168,13 +142,6 @@ static int gic_set_affinity(unsigned int irq, const struct cpumask *cpumask) /* Re-route this IRQ */ GIC_SH_MAP_TO_VPE_SMASK(irq, first_cpu(tmp)); - /* - * FIXME: assumption that _intrmap is ordered and has no holes - */ - - /* Update the intr_map */ - _intrmap[irq].cpunum = first_cpu(tmp); - /* Update the pcpu_masks */ for (i = 0; i < NR_CPUS; i++) clear_bit(irq, pcpu_masks[i].pcpu_mask); @@ -201,8 +168,9 @@ static struct irq_chip gic_irq_controller = { #endif }; -static void __init setup_intr(unsigned int intr, unsigned int cpu, - unsigned int pin, unsigned int polarity, unsigned int trigtype) +static void __init gic_setup_intr(unsigned int intr, unsigned int cpu, + unsigned int pin, unsigned int polarity, unsigned int trigtype, + unsigned int flags) { /* Setup Intr to Pin mapping */ if (pin & GIC_MAP_TO_NMI_MSK) { @@ -227,38 +195,43 @@ static void __init setup_intr(unsigned int intr, unsigned int cpu, GIC_SET_TRIGGER(intr, trigtype); /* Init Intr Masks */ - GIC_SET_INTR_MASK(intr, 0); + GIC_CLR_INTR_MASK(intr); + /* Initialise per-cpu Interrupt software masks */ + if (flags & GIC_FLAG_IPI) + set_bit(intr, pcpu_masks[cpu].pcpu_mask); + if (flags & GIC_FLAG_TRANSPARENT) + GIC_SET_INTR_MASK(intr); + if (trigtype == GIC_TRIG_EDGE) + gic_irq_flags[intr] |= GIC_IRQ_FLAG_EDGE; } -static void __init gic_basic_init(void) +static void __init gic_basic_init(int numintrs, int numvpes, + struct gic_intr_map *intrmap, int mapsize) { unsigned int i, cpu; /* Setup defaults */ - for (i = 0; i < GIC_NUM_INTRS; i++) { + for (i = 0; i < numintrs; i++) { GIC_SET_POLARITY(i, GIC_POL_POS); GIC_SET_TRIGGER(i, GIC_TRIG_LEVEL); - GIC_SET_INTR_MASK(i, 0); + GIC_CLR_INTR_MASK(i); + if (i < GIC_NUM_INTRS) + gic_irq_flags[i] = 0; } /* Setup specifics */ - for (i = 0; i < _mapsize; i++) { - cpu = _intrmap[i].cpunum; + for (i = 0; i < mapsize; i++) { + cpu = intrmap[i].cpunum; if (cpu == X) continue; - - if (cpu == 0 && i != 0 && _intrmap[i].intrnum == 0 && - _intrmap[i].ipiflag == 0) + if (cpu == 0 && i != 0 && intrmap[i].flags == 0) continue; - - setup_intr(_intrmap[i].intrnum, - _intrmap[i].cpunum, - _intrmap[i].pin, - _intrmap[i].polarity, - _intrmap[i].trigtype); - /* Initialise per-cpu Interrupt software masks */ - if (_intrmap[i].ipiflag) - set_bit(_intrmap[i].intrnum, pcpu_masks[cpu].pcpu_mask); + gic_setup_intr(i, + intrmap[i].cpunum, + intrmap[i].pin, + intrmap[i].polarity, + intrmap[i].trigtype, + intrmap[i].flags); } vpe_local_setup(numvpes); @@ -273,12 +246,11 @@ void __init gic_init(unsigned long gic_base_addr, unsigned int irqbase) { unsigned int gicconfig; + int numvpes, numintrs; _gic_base = (unsigned long) ioremap_nocache(gic_base_addr, gic_addrspace_size); _irqbase = irqbase; - _intrmap = intr_map; - _mapsize = intr_map_size; GICREAD(GIC_REG(SHARED, GIC_SH_CONFIG), gicconfig); numintrs = (gicconfig & GIC_SH_CONFIG_NUMINTRS_MSK) >> @@ -288,7 +260,7 @@ void __init gic_init(unsigned long gic_base_addr, numvpes = (gicconfig & GIC_SH_CONFIG_NUMVPES_MSK) >> GIC_SH_CONFIG_NUMVPES_SHF; - pr_debug("%s called\n", __func__); + pr_debug("%s called\n", __FUNCTION__); - gic_basic_init(); + gic_basic_init(numintrs, numvpes, intr_map, intr_map_size); } diff --git a/arch/mips/mti-malta/malta-int.c b/arch/mips/mti-malta/malta-int.c index e9ba8b3..92e3b56 100644 --- a/arch/mips/mti-malta/malta-int.c +++ b/arch/mips/mti-malta/malta-int.c @@ -385,24 +385,26 @@ static int __initdata msc_nr_eicirqs = ARRAY_SIZE(msc_eicirqmap); * Interrupts and CPUs/Core Interrupts. The nature of the External * Interrupts is also defined here - polarity/trigger. */ + +#define GIC_CPU_NMI GIC_MAP_TO_NMI_MSK static struct gic_intr_map gic_intr_map[GIC_NUM_INTRS] = { - { GIC_EXT_INTR(0), X, X, X, X, 0 }, - { GIC_EXT_INTR(1), X, X, X, X, 0 }, - { GIC_EXT_INTR(2), X, X, X, X, 0 }, - { GIC_EXT_INTR(3), 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, 0 }, - { GIC_EXT_INTR(4), 0, GIC_CPU_INT1, GIC_POL_POS, GIC_TRIG_LEVEL, 0 }, - { GIC_EXT_INTR(5), 0, GIC_CPU_INT2, GIC_POL_POS, GIC_TRIG_LEVEL, 0 }, - { GIC_EXT_INTR(6), 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, 0 }, - { GIC_EXT_INTR(7), 0, GIC_CPU_INT4, GIC_POL_POS, GIC_TRIG_LEVEL, 0 }, - { GIC_EXT_INTR(8), 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, 0 }, - { GIC_EXT_INTR(9), 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, 0 }, - { GIC_EXT_INTR(10), X, X, X, X, 0 }, - { GIC_EXT_INTR(11), X, X, X, X, 0 }, - { GIC_EXT_INTR(12), 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, 0 }, - { GIC_EXT_INTR(13), 0, GIC_MAP_TO_NMI_MSK, GIC_POL_POS, GIC_TRIG_LEVEL, 0 }, - { GIC_EXT_INTR(14), 0, GIC_MAP_TO_NMI_MSK, GIC_POL_POS, GIC_TRIG_LEVEL, 0 }, - { GIC_EXT_INTR(15), X, X, X, X, 0 }, -/* This is the end of the general interrupts now we do IPI ones */ + { X, X, X, X, 0 }, + { X, X, X, X, 0 }, + { X, X, X, X, 0 }, + { 0, GIC_CPU_INT0, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, + { 0, GIC_CPU_INT1, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, + { 0, GIC_CPU_INT2, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, + { 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, + { 0, GIC_CPU_INT4, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, + { 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, + { 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, + { X, X, X, X, 0 }, + { X, X, X, X, 0 }, + { 0, GIC_CPU_INT3, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, + { 0, GIC_CPU_NMI, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, + { 0, GIC_CPU_NMI, GIC_POL_POS, GIC_TRIG_LEVEL, GIC_FLAG_TRANSPARENT }, + { X, X, X, X, 0 }, + /* The remainder of this table is initialised by fill_ipi_map */ }; #endif @@ -419,20 +421,35 @@ int __init gcmp_probe(unsigned long addr, unsigned long size) gcmp_present = (GCMPGCB(GCMPB) & GCMP_GCB_GCMPB_GCMPBASE_MSK) == GCMP_BASE_ADDR; if (gcmp_present) - printk(KERN_DEBUG "GCMP present\n"); + pr_debug("GCMP present\n"); return gcmp_present; } +/* Return the number of IOCU's present */ +int __init gcmp_niocu(void) +{ + return gcmp_present ? + (GCMPGCB(GC) & GCMP_GCB_GC_NUMIOCU_MSK) >> GCMP_GCB_GC_NUMIOCU_SHF : + 0; +} + +/* Set GCMP region attributes */ +void __init gcmp_setregion(int region, unsigned long base, + unsigned long mask, int type) +{ + GCMPGCBn(CMxBASE, region) = base; + GCMPGCBn(CMxMASK, region) = mask | type; +} + #if defined(CONFIG_MIPS_MT_SMP) static void __init fill_ipi_map1(int baseintr, int cpu, int cpupin) { int intr = baseintr + cpu; - gic_intr_map[intr].intrnum = GIC_EXT_INTR(intr); gic_intr_map[intr].cpunum = cpu; gic_intr_map[intr].pin = cpupin; gic_intr_map[intr].polarity = GIC_POL_POS; gic_intr_map[intr].trigtype = GIC_TRIG_EDGE; - gic_intr_map[intr].ipiflag = 1; + gic_intr_map[intr].flags = GIC_FLAG_IPI; ipi_map[cpu] |= (1 << (cpupin + 2)); } @@ -447,6 +464,12 @@ static void __init fill_ipi_map(void) } #endif +void __init arch_init_ipiirq(int irq, struct irqaction *action) +{ + setup_irq(irq, action); + set_irq_handler(irq, handle_percpu_irq); +} + void __init arch_init_irq(void) { init_i8259_irqs(); @@ -463,7 +486,7 @@ void __init arch_init_irq(void) MSC01_SC_CFG_GICPRES_MSK) >> MSC01_SC_CFG_GICPRES_SHF; } if (gic_present) - printk(KERN_DEBUG "GIC present\n"); + pr_debug("GIC present\n"); switch (mips_revision_sconid) { case MIPS_REVISION_SCON_SOCIT: @@ -526,16 +549,16 @@ void __init arch_init_irq(void) &corehi_irqaction); } -#if defined(CONFIG_MIPS_MT_SMP) if (gic_present) { /* FIXME */ int i; - +#if defined(CONFIG_MIPS_MT_SMP) gic_call_int_base = GIC_NUM_INTRS - NR_CPUS; gic_resched_int_base = gic_call_int_base - NR_CPUS; - fill_ipi_map(); - gic_init(GIC_BASE_ADDR, GIC_ADDRSPACE_SZ, gic_intr_map, ARRAY_SIZE(gic_intr_map), MIPS_GIC_IRQ_BASE); +#endif + gic_init(GIC_BASE_ADDR, GIC_ADDRSPACE_SZ, gic_intr_map, + ARRAY_SIZE(gic_intr_map), MIPS_GIC_IRQ_BASE); if (!gcmp_present) { /* Enable the GIC */ i = REG(_msc01_biu_base, MSC01_SC_CFG); @@ -543,7 +566,7 @@ void __init arch_init_irq(void) (i | (0x1 << MSC01_SC_CFG_GICENA_SHF)); pr_debug("GIC Enabled\n"); } - +#if defined(CONFIG_MIPS_MT_SMP) /* set up ipi interrupts */ if (cpu_has_vint) { set_vi_handler(MIPSCPU_INT_IPI0, malta_ipi_irqdispatch); @@ -556,16 +579,14 @@ void __init arch_init_irq(void) write_c0_status(0x1100dc00); printk("CPU%d: status register frc %08x\n", smp_processor_id(), read_c0_status()); for (i = 0; i < NR_CPUS; i++) { - setup_irq(MIPS_GIC_IRQ_BASE + - GIC_RESCHED_INT(i), &irq_resched); - setup_irq(MIPS_GIC_IRQ_BASE + - GIC_CALL_INT(i), &irq_call); - set_irq_handler(MIPS_GIC_IRQ_BASE + - GIC_RESCHED_INT(i), handle_percpu_irq); - set_irq_handler(MIPS_GIC_IRQ_BASE + - GIC_CALL_INT(i), handle_percpu_irq); + arch_init_ipiirq(MIPS_GIC_IRQ_BASE + + GIC_RESCHED_INT(i), &irq_resched); + arch_init_ipiirq(MIPS_GIC_IRQ_BASE + + GIC_CALL_INT(i), &irq_call); } +#endif } else { +#if defined(CONFIG_MIPS_MT_SMP) /* set up ipi interrupts */ if (cpu_has_veic) { set_vi_handler (MSC01E_INT_SW0, ipi_resched_dispatch); @@ -580,12 +601,8 @@ void __init arch_init_irq(void) cpu_ipi_resched_irq = MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_RESCHED_IRQ; cpu_ipi_call_irq = MIPS_CPU_IRQ_BASE + MIPS_CPU_IPI_CALL_IRQ; } - - setup_irq(cpu_ipi_resched_irq, &irq_resched); - setup_irq(cpu_ipi_call_irq, &irq_call); - - set_irq_handler(cpu_ipi_resched_irq, handle_percpu_irq); - set_irq_handler(cpu_ipi_call_irq, handle_percpu_irq); + arch_init_ipiirq(cpu_ipi_resched_irq, &irq_resched); + arch_init_ipiirq(cpu_ipi_call_irq, &irq_call); } #endif } diff --git a/arch/mips/mti-malta/malta-pci.c b/arch/mips/mti-malta/malta-pci.c index b974319..25994e6 100644 --- a/arch/mips/mti-malta/malta-pci.c +++ b/arch/mips/mti-malta/malta-pci.c @@ -27,7 +27,7 @@ #include #include - +#include #include #include #include @@ -201,7 +201,11 @@ void __init mips_pcibios_init(void) msc_mem_resource.start = start & mask; msc_mem_resource.end = (start & mask) | ~mask; msc_controller.mem_offset = (start & mask) - (map & mask); - +#ifdef CONFIG_MIPS_CMP + if (gcmp_niocu()) + gcmp_setregion(0, start, mask, + GCMP_GCB_GCMPB_CMDEFTGT_IOCU1); +#endif MSC_READ(MSC01_PCI_SC2PIOBASL, start); MSC_READ(MSC01_PCI_SC2PIOMSKL, mask); MSC_READ(MSC01_PCI_SC2PIOMAPL, map); @@ -209,7 +213,11 @@ void __init mips_pcibios_init(void) msc_io_resource.end = (map & mask) | ~mask; msc_controller.io_offset = 0; ioport_resource.end = ~mask; - +#ifdef CONFIG_MIPS_CMP + if (gcmp_niocu()) + gcmp_setregion(1, start, mask, + GCMP_GCB_GCMPB_CMDEFTGT_IOCU1); +#endif /* If ranges overlap I/O takes precedence. */ start = start & mask; end = start | ~mask; From raghu@mips.com Thu Jul 2 04:50:42 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 02 Jul 2009 04:50:49 +0200 (CEST) Received: from dns1.mips.com ([63.167.95.197]:39586 "EHLO dns1.mips.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492021AbZGBCsh (ORCPT ); Thu, 2 Jul 2009 04:48:37 +0200 Received: from MTVEXCHANGE.mips.com ([192.168.36.60]) by dns1.mips.com (8.13.8/8.13.8) with ESMTP id n622gtfY016349 for ; Wed, 1 Jul 2009 19:42:55 -0700 Received: from mercury.mips.com ([192.168.64.101]) by MTVEXCHANGE.mips.com with Microsoft SMTPSVC(6.0.3790.3959); Wed, 1 Jul 2009 19:42:55 -0700 Received: from [192.168.65.97] (linux-raghu [192.168.65.97]) by mercury.mips.com (8.13.5/8.13.5) with ESMTP id n622gtFK006012; Wed, 1 Jul 2009 19:42:55 -0700 (PDT) From: Raghu Gandham Subject: [PATCH 11/15] Add missing memory barriers for correct operation of amon_cpu_start To: linux-mips@linux-mips.org Cc: chris@mips.com Date: Wed, 01 Jul 2009 19:42:29 -0700 Message-ID: <20090702024229.23268.31816.stgit@linux-raghu> In-Reply-To: <20090702023938.23268.65453.stgit@linux-raghu> References: <20090702023938.23268.65453.stgit@linux-raghu> User-Agent: StGIT/0.14.3 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 02 Jul 2009 02:42:55.0162 (UTC) FILETIME=[CD4919A0:01C9FABE] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23603 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: raghu@mips.com Precedence: bulk X-list: linux-mips From: Chris Dearman Signed-off-by: Chris Dearman (chris@mips.com) --- arch/mips/mti-malta/malta-amon.c | 7 ++++--- 1 files changed, 4 insertions(+), 3 deletions(-) diff --git a/arch/mips/mti-malta/malta-amon.c b/arch/mips/mti-malta/malta-amon.c index df9e526..469d9b0 100644 --- a/arch/mips/mti-malta/malta-amon.c +++ b/arch/mips/mti-malta/malta-amon.c @@ -70,11 +70,12 @@ void amon_cpu_start(int cpu, launch->sp = sp; launch->a0 = a0; - /* Make sure target sees parameters before the go bit */ - smp_mb(); - + smp_wmb(); /* Target must see parameters before go */ launch->flags |= LAUNCH_FGO; + smp_wmb(); /* Target must see go before we poll */ + while ((launch->flags & LAUNCH_FGONE) == 0) ; + smp_rmb(); /* Target will be updating flags soon */ pr_debug("launch: cpu%d gone!\n", cpu); } From raghu@mips.com Thu Jul 2 04:51:07 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 02 Jul 2009 04:51:15 +0200 (CEST) Received: from dns1.mips.com ([63.167.95.197]:39588 "EHLO dns1.mips.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492025AbZGBCsx (ORCPT ); Thu, 2 Jul 2009 04:48:53 +0200 Received: from MTVEXCHANGE.mips.com ([192.168.36.60]) by dns1.mips.com (8.13.8/8.13.8) with ESMTP id n622hBWe016354 for ; Wed, 1 Jul 2009 19:43:11 -0700 Received: from mercury.mips.com ([192.168.64.101]) by MTVEXCHANGE.mips.com with Microsoft SMTPSVC(6.0.3790.3959); Wed, 1 Jul 2009 19:43:10 -0700 Received: from [192.168.65.97] (linux-raghu [192.168.65.97]) by mercury.mips.com (8.13.5/8.13.5) with ESMTP id n622hAYg006014; Wed, 1 Jul 2009 19:43:10 -0700 (PDT) From: Raghu Gandham Subject: [PATCH 12/15] Added coherentio command line option for DMA_NONCOHERENT kernel To: linux-mips@linux-mips.org Cc: chris@mips.com Date: Wed, 01 Jul 2009 19:42:45 -0700 Message-ID: <20090702024244.23268.41013.stgit@linux-raghu> In-Reply-To: <20090702023938.23268.65453.stgit@linux-raghu> References: <20090702023938.23268.65453.stgit@linux-raghu> User-Agent: StGIT/0.14.3 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 02 Jul 2009 02:43:10.0693 (UTC) FILETIME=[D68AF150:01C9FABE] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23604 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: raghu@mips.com Precedence: bulk X-list: linux-mips From: Chris Dearman Signed-off-by: Chris Dearman (chris@mips.com) --- arch/mips/mti-malta/malta-setup.c | 100 +++++++++++++++++++++++++++++++++++++ 1 files changed, 100 insertions(+), 0 deletions(-) diff --git a/arch/mips/mti-malta/malta-setup.c b/arch/mips/mti-malta/malta-setup.c index 69f5f9c..3f52c31 100644 --- a/arch/mips/mti-malta/malta-setup.c +++ b/arch/mips/mti-malta/malta-setup.c @@ -32,6 +32,7 @@ #include #include #include +#include #ifdef CONFIG_VT #include #endif @@ -105,6 +106,103 @@ static void __init fd_activate(void) } #endif +int coherentio = -1; +static int __init setcoherentio(char *str) +{ + if (coherentio < 0) + pr_info("Command line checking done before" + " plat_setup_iocoherency!!\n"); + if (coherentio == 0) + pr_info("Command line enabling coherentio" + " (this will break...)!!\n"); + + coherentio = 1; + pr_info("Hardware DMA cache coherency (command line)\n"); + return 1; +} +__setup("coherentio", setcoherentio); + +static int __init setnocoherentio(char *str) +{ + if (coherentio < 0) + pr_info("Command line checking done before" + " plat_setup_iocoherency!!\n"); + if (coherentio == 1) + pr_info("Command line disabling coherentio\n"); + + coherentio = 0; + pr_info("Software DMA cache coherency (command line)\n"); + return 1; +} +__setup("nocoherentio", setnocoherentio); + +static int __init +plat_enable_iocoherency(void) +{ + int supported = 0; + if (mips_revision_sconid == MIPS_REVISION_SCON_BONITO) { + if (BONITO_PCICACHECTRL & BONITO_PCICACHECTRL_CPUCOH_PRES) { + BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_CPUCOH_EN; + pr_info("Enabled Bonito CPU coherency\n"); + supported = 1; + } + if (strstr(prom_getcmdline(), "iobcuncached")) { + BONITO_PCICACHECTRL &= ~BONITO_PCICACHECTRL_IOBCCOH_EN; + BONITO_PCIMEMBASECFG = BONITO_PCIMEMBASECFG & + ~(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED | + BONITO_PCIMEMBASECFG_MEMBASE1_CACHED); + pr_info("Disabled Bonito IOBC coherency\n"); + } else { + BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_IOBCCOH_EN; + BONITO_PCIMEMBASECFG |= + (BONITO_PCIMEMBASECFG_MEMBASE0_CACHED | + BONITO_PCIMEMBASECFG_MEMBASE1_CACHED); + pr_info("Enabled Bonito IOBC coherency\n"); + } + } else if (gcmp_niocu() != 0) { + /* Nothing special needs to be done to enable coherency */ + pr_info("CMP IOCU detected\n"); + if ((*(unsigned int *)0xbf403000 & 0x81) != 0x81) { + pr_crit("IOCU OPERATION DISABLED BY SWITCH" + " - DEFAULTING TO SW IO COHERENCY\n"); + return 0; + } + supported = 1; + } + return supported; +} + +static void __init +plat_setup_iocoherency(void) +{ +#ifdef CONFIG_DMA_NONCOHERENT + /* + * Kernel has been configured with software coherency + * but we might choose to turn it off + */ + if (plat_enable_iocoherency()) { + if (coherentio == 0) + pr_info("Hardware DMA cache coherency supported" + " but disabled from command line\n"); + else { + coherentio = 1; + printk(KERN_INFO "Hardware DMA cache coherency\n"); + } + } else { + if (coherentio == 1) + pr_info("Hardware DMA cache coherency not supported" + " but enabled from command line\n"); + else { + coherentio = 0; + pr_info("Software DMA cache coherency\n"); + } + } +#else + if (!plat_enable_iocoherency()) + panic("Hardware DMA cache coherency not supported"); +#endif +} + #ifdef CONFIG_BLK_DEV_IDE static void __init pci_clock_check(void) { @@ -207,6 +305,8 @@ void __init plat_mem_setup(void) if (mips_revision_sconid == MIPS_REVISION_SCON_BONITO) bonito_quirks_setup(); + plat_setup_iocoherency(); + #ifdef CONFIG_BLK_DEV_IDE pci_clock_check(); #endif From raghu@mips.com Thu Jul 2 04:51:32 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 02 Jul 2009 04:51:40 +0200 (CEST) Received: from dns1.mips.com ([63.167.95.197]:39589 "EHLO dns1.mips.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492014AbZGBCtJ (ORCPT ); Thu, 2 Jul 2009 04:49:09 +0200 Received: from MTVEXCHANGE.mips.com ([192.168.36.60]) by dns1.mips.com (8.13.8/8.13.8) with ESMTP id n622hQJc016361 for ; Wed, 1 Jul 2009 19:43:26 -0700 Received: from mercury.mips.com ([192.168.64.101]) by MTVEXCHANGE.mips.com with Microsoft SMTPSVC(6.0.3790.3959); Wed, 1 Jul 2009 19:43:26 -0700 Received: from [192.168.65.97] (linux-raghu [192.168.65.97]) by mercury.mips.com (8.13.5/8.13.5) with ESMTP id n622hQWL006016; Wed, 1 Jul 2009 19:43:26 -0700 (PDT) From: Raghu Gandham Subject: [PATCH 13/15] Avoid accessing GCMP registers when they are not present To: linux-mips@linux-mips.org Cc: chris@mips.com Date: Wed, 01 Jul 2009 19:43:00 -0700 Message-ID: <20090702024300.23268.72873.stgit@linux-raghu> In-Reply-To: <20090702023938.23268.65453.stgit@linux-raghu> References: <20090702023938.23268.65453.stgit@linux-raghu> User-Agent: StGIT/0.14.3 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 02 Jul 2009 02:43:26.0365 (UTC) FILETIME=[DFE24CD0:01C9FABE] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23605 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: raghu@mips.com Precedence: bulk X-list: linux-mips From: Jaidev Patwardhan Signed-off-by: Chris Dearman --- arch/mips/mti-malta/malta-int.c | 16 +++++++++++++--- 1 files changed, 13 insertions(+), 3 deletions(-) diff --git a/arch/mips/mti-malta/malta-int.c b/arch/mips/mti-malta/malta-int.c index 92e3b56..63e7161 100644 --- a/arch/mips/mti-malta/malta-int.c +++ b/arch/mips/mti-malta/malta-int.c @@ -413,6 +413,11 @@ static struct gic_intr_map gic_intr_map[GIC_NUM_INTRS] = { */ int __init gcmp_probe(unsigned long addr, unsigned long size) { + if (mips_revision_sconid != MIPS_REVISION_SCON_ROCIT) { + gcmp_present = 0; + return gcmp_present; + } + if (gcmp_present >= 0) return gcmp_present; @@ -481,9 +486,14 @@ void __init arch_init_irq(void) GCMPGCB(GICBA) = GIC_BASE_ADDR | GCMP_GCB_GICBA_EN_MSK; gic_present = 1; } else { - _msc01_biu_base = (unsigned long) ioremap_nocache(MSC01_BIU_REG_BASE, MSC01_BIU_ADDRSPACE_SZ); - gic_present = (REG(_msc01_biu_base, MSC01_SC_CFG) & - MSC01_SC_CFG_GICPRES_MSK) >> MSC01_SC_CFG_GICPRES_SHF; + if (mips_revision_sconid == MIPS_REVISION_SCON_ROCIT) { + _msc01_biu_base = (unsigned long) + ioremap_nocache(MSC01_BIU_REG_BASE, + MSC01_BIU_ADDRSPACE_SZ); + gic_present = (REG(_msc01_biu_base, MSC01_SC_CFG) & + MSC01_SC_CFG_GICPRES_MSK) >> + MSC01_SC_CFG_GICPRES_SHF; + } } if (gic_present) pr_debug("GIC present\n"); From raghu@mips.com Thu Jul 2 04:51:57 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 02 Jul 2009 04:52:06 +0200 (CEST) Received: from dns1.mips.com ([63.167.95.197]:39591 "EHLO dns1.mips.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492030AbZGBCtY (ORCPT ); Thu, 2 Jul 2009 04:49:24 +0200 Received: from MTVEXCHANGE.mips.com ([192.168.36.60]) by dns1.mips.com (8.13.8/8.13.8) with ESMTP id n622hg88016367 for ; Wed, 1 Jul 2009 19:43:42 -0700 Received: from mercury.mips.com ([192.168.64.101]) by MTVEXCHANGE.mips.com with Microsoft SMTPSVC(6.0.3790.3959); Wed, 1 Jul 2009 19:43:41 -0700 Received: from [192.168.65.97] (linux-raghu [192.168.65.97]) by mercury.mips.com (8.13.5/8.13.5) with ESMTP id n622hfoh006018; Wed, 1 Jul 2009 19:43:41 -0700 (PDT) From: Raghu Gandham Subject: [PATCH 14/15] Avoid queing multiple reschedule IPI's in SMTC To: linux-mips@linux-mips.org Cc: chris@mips.com Date: Wed, 01 Jul 2009 19:43:16 -0700 Message-ID: <20090702024315.23268.65987.stgit@linux-raghu> In-Reply-To: <20090702023938.23268.65453.stgit@linux-raghu> References: <20090702023938.23268.65453.stgit@linux-raghu> User-Agent: StGIT/0.14.3 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 02 Jul 2009 02:43:41.0802 (UTC) FILETIME=[E915CCA0:01C9FABE] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23606 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: raghu@mips.com Precedence: bulk X-list: linux-mips From: Jaidev Patwardhan Signed-off-by: Chris Dearman --- arch/mips/include/asm/smtc_ipi.h | 5 +++-- arch/mips/kernel/smtc.c | 33 +++++++++++++++++++++++++++++---- 2 files changed, 32 insertions(+), 6 deletions(-) diff --git a/arch/mips/include/asm/smtc_ipi.h b/arch/mips/include/asm/smtc_ipi.h index 8ce5175..832b8be 100644 --- a/arch/mips/include/asm/smtc_ipi.h +++ b/arch/mips/include/asm/smtc_ipi.h @@ -23,8 +23,8 @@ struct smtc_ipi { void *arg; int dest; #ifdef SMTC_IPI_DEBUG - int sender; - long stamp; + unsigned sender; + unsigned long long stamp; #endif /* SMTC_IPI_DEBUG */ }; @@ -45,6 +45,7 @@ struct smtc_ipi_q { spinlock_t lock; struct smtc_ipi *tail; int depth; + int resched_flag; /* reschedule already queued */ }; static inline void smtc_ipi_nq(struct smtc_ipi_q *q, struct smtc_ipi *p) diff --git a/arch/mips/kernel/smtc.c b/arch/mips/kernel/smtc.c index 8a0626c..69240c4 100644 --- a/arch/mips/kernel/smtc.c +++ b/arch/mips/kernel/smtc.c @@ -75,7 +75,6 @@ unsigned long irq_hwmask[NR_IRQS]; asiduse smtc_live_asid[MAX_SMTC_TLBS][MAX_SMTC_ASIDS]; - /* * Number of InterProcessor Interrupt (IPI) message buffers to allocate */ @@ -388,6 +387,7 @@ void smtc_prepare_cpus(int cpus) IPIQ[i].head = IPIQ[i].tail = NULL; spin_lock_init(&IPIQ[i].lock); IPIQ[i].depth = 0; + IPIQ[i].resched_flag = 0; /* No reschedules queued initially */ } /* cpu_data index starts at zero */ @@ -738,11 +738,24 @@ void smtc_forward_irq(unsigned int irq) static void smtc_ipi_qdump(void) { int i; + struct smtc_ipi *temp; for (i = 0; i < NR_CPUS ;i++) { - printk("IPIQ[%d]: head = 0x%x, tail = 0x%x, depth = %d\n", + pr_info("IPIQ[%d]: head = 0x%x, tail = 0x%x, depth = %d\n", i, (unsigned)IPIQ[i].head, (unsigned)IPIQ[i].tail, IPIQ[i].depth); + temp = IPIQ[i].head; + + while (temp != IPIQ[i].tail) { + pr_debug("%d %d %d: ", temp->type, temp->dest, + (int)temp->arg); +#ifdef SMTC_IPI_DEBUG + pr_debug("%u %lu\n", temp->sender, temp->stamp); +#else + pr_debug("\n"); +#endif + temp = temp->flink; + } } } @@ -781,11 +794,15 @@ void smtc_send_ipi(int cpu, int type, unsigned int action) int mtflags; unsigned long tcrestart; extern void r4k_wait_irqoff(void), __pastwait(void); + int set_resched_flag = (type == LINUX_SMP_IPI && + action == SMP_RESCHEDULE_YOURSELF); if (cpu == smp_processor_id()) { printk("Cannot Send IPI to self!\n"); return; } + if (set_resched_flag && IPIQ[cpu].resched_flag != 0) + return; /* There is a reschedule queued already */ /* Set up a descriptor, to be delivered either promptly or queued */ pipi = smtc_ipi_dq(&freeIPIq); if (pipi == NULL) { @@ -798,6 +815,7 @@ void smtc_send_ipi(int cpu, int type, unsigned int action) pipi->dest = cpu; if (cpu_data[cpu].vpe_id != cpu_data[smp_processor_id()].vpe_id) { /* If not on same VPE, enqueue and send cross-VPE interrupt */ + IPIQ[cpu].resched_flag |= set_resched_flag; smtc_ipi_nq(&IPIQ[cpu], pipi); LOCK_CORE_PRA(); settc(cpu_data[cpu].tc_id); @@ -844,6 +862,7 @@ void smtc_send_ipi(int cpu, int type, unsigned int action) */ write_tc_c0_tchalt(0); UNLOCK_CORE_PRA(); + IPIQ[cpu].resched_flag |= set_resched_flag; smtc_ipi_nq(&IPIQ[cpu], pipi); } else { postdirect: @@ -993,12 +1012,15 @@ void deferred_smtc_ipi(void) * already enabled. */ local_irq_save(flags); - spin_lock(&q->lock); pipi = __smtc_ipi_dq(q); spin_unlock(&q->lock); - if (pipi != NULL) + if (pipi != NULL) { + if (pipi->type == LINUX_SMP_IPI && + (int)pipi->arg == SMP_RESCHEDULE_YOURSELF) + IPIQ[q].resched_flag = 0; ipi_decode(pipi); + } /* * The use of the __raw_local restore isn't * as obviously necessary here as in smtc_ipi_replay(), @@ -1079,6 +1101,9 @@ static irqreturn_t ipi_interrupt(int irq, void *dev_idm) * with interrupts off */ local_irq_save(flags); + if (pipi->type == LINUX_SMP_IPI && + (int)pipi->arg == SMP_RESCHEDULE_YOURSELF) + IPIQ[cpu].resched_flag = 0; ipi_decode(pipi); local_irq_restore(flags); } From raghu@mips.com Thu Jul 2 04:52:23 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 02 Jul 2009 04:52:31 +0200 (CEST) Received: from dns1.mips.com ([63.167.95.197]:39594 "EHLO dns1.mips.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492033AbZGBCtk (ORCPT ); Thu, 2 Jul 2009 04:49:40 +0200 Received: from MTVEXCHANGE.mips.com ([192.168.36.60]) by dns1.mips.com (8.13.8/8.13.8) with ESMTP id n622hv2L016374 for ; Wed, 1 Jul 2009 19:43:57 -0700 Received: from mercury.mips.com ([192.168.64.101]) by MTVEXCHANGE.mips.com with Microsoft SMTPSVC(6.0.3790.3959); Wed, 1 Jul 2009 19:43:57 -0700 Received: from [192.168.65.97] (linux-raghu [192.168.65.97]) by mercury.mips.com (8.13.5/8.13.5) with ESMTP id n622hv0S006020; Wed, 1 Jul 2009 19:43:57 -0700 (PDT) From: Raghu Gandham Subject: [PATCH 15/15] Do not rely on the initial state of TC/VPE bindings when doing cross VPE writes To: linux-mips@linux-mips.org Cc: chris@mips.com Date: Wed, 01 Jul 2009 19:43:31 -0700 Message-ID: <20090702024331.23268.98671.stgit@linux-raghu> In-Reply-To: <20090702023938.23268.65453.stgit@linux-raghu> References: <20090702023938.23268.65453.stgit@linux-raghu> User-Agent: StGIT/0.14.3 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 02 Jul 2009 02:43:57.0349 (UTC) FILETIME=[F25A1550:01C9FABE] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23607 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: raghu@mips.com Precedence: bulk X-list: linux-mips From: Kurt Martin Signed-off-by: Jaidev Patwardhan Signed-off-by: Chris Dearman --- arch/mips/kernel/smtc.c | 12 ++++++++++++ 1 files changed, 12 insertions(+), 0 deletions(-) diff --git a/arch/mips/kernel/smtc.c b/arch/mips/kernel/smtc.c index 69240c4..3498b82 100644 --- a/arch/mips/kernel/smtc.c +++ b/arch/mips/kernel/smtc.c @@ -481,6 +481,18 @@ void smtc_prepare_cpus(int cpus) */ if (tc != 0) { smtc_tc_setup(vpe, tc, cpu); + if (vpe != 0) { + /* + * Set MVP bit (possibly again). Do it + * here to catch CPUs that have no TCs + * bound to the VPE at reset. In that + * case, a TC must be bound to the VPE + * before we can set VPEControl[MVP] + */ + write_vpe_c0_vpeconf0( + read_vpe_c0_vpeconf0() | + VPECONF0_MVP); + } cpu++; } printk(" %d", tc); From kevink@paralogos.com Thu Jul 2 06:08:12 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 02 Jul 2009 06:08:18 +0200 (CEST) Received: from gateway10.websitewelcome.com ([69.56.148.20]:57917 "HELO gateway10.websitewelcome.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with SMTP id S1492039AbZGBEIM (ORCPT ); Thu, 2 Jul 2009 06:08:12 +0200 Received: (qmail 14955 invoked from network); 2 Jul 2009 04:08:03 -0000 Received: from gator750.hostgator.com (174.132.194.2) by gateway10.websitewelcome.com with SMTP; 2 Jul 2009 04:08:03 -0000 Received: from 216-239-45-4.google.com ([216.239.45.4]:30429 helo=epiktistes.mtv.corp.google.com) by gator750.hostgator.com with esmtpa (Exim 4.69) (envelope-from ) id 1MMDV4-000109-DM; Wed, 01 Jul 2009 23:02:18 -0500 Message-ID: <4A4C314B.2070907@paralogos.com> Date: Wed, 01 Jul 2009 21:02:19 -0700 From: "Kevin D. Kissell" User-Agent: Thunderbird 2.0.0.21 (X11/20090318) MIME-Version: 1.0 To: Raghu Gandham CC: linux-mips@linux-mips.org, chris@mips.com Subject: Re: [PATCH 15/15] Do not rely on the initial state of TC/VPE bindings when doing cross VPE writes References: <20090702023938.23268.65453.stgit@linux-raghu> <20090702024331.23268.98671.stgit@linux-raghu> In-Reply-To: <20090702024331.23268.98671.stgit@linux-raghu> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-AntiAbuse: This header was added to track abuse, please include it with any abuse report X-AntiAbuse: Primary Hostname - gator750.hostgator.com X-AntiAbuse: Original Domain - linux-mips.org X-AntiAbuse: Originator/Caller UID/GID - [47 12] / [47 12] X-AntiAbuse: Sender Address Domain - paralogos.com Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23608 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: kevink@paralogos.com Precedence: bulk X-list: linux-mips Note that, regardless of the reset state, smtc_configure_tlb() should have at least temporarily bound TC 1 to VPE1, which may be why this never seemed to be a problem on the 34K. If one wants to support designs with more than 2 VPEs, then this is probably one of the things that needs to be fixed. That having been said, rather than adding a usually-redundant write_vpe_c0_vpeconf0() in that clause, wouldn't it be cleaner to just move the MVP setting from the top of the loop to the point in the loop just after the TCs have been bound to the VPE in question, i.e., 454 if (slop) { 455 if (tc != 0) { 456 smtc_tc_setup(vpe,tc, cpu); 457 cpu++; 458 } 459 printk(" %d", tc); 460 tc++; 461 slop--; 462 } write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() | VPECONF0_MVP); 463 if (vpe != 0) { 464 /* 465 * Clear any stale software interrupts from VPE's Cause 466 */ This should definitely be OK for a 34K, because it's being executed by TC0 in VPE0 and the reset state of VPE0 has MVP set. If it weren't, smtc_configure_tlb() would have failed. Regards, Kevin K. Raghu Gandham wrote: > From: Kurt Martin > > Signed-off-by: Jaidev Patwardhan > Signed-off-by: Chris Dearman > --- > > arch/mips/kernel/smtc.c | 12 ++++++++++++ > 1 files changed, 12 insertions(+), 0 deletions(-) > > diff --git a/arch/mips/kernel/smtc.c b/arch/mips/kernel/smtc.c > index 69240c4..3498b82 100644 > --- a/arch/mips/kernel/smtc.c > +++ b/arch/mips/kernel/smtc.c > @@ -481,6 +481,18 @@ void smtc_prepare_cpus(int cpus) > */ > if (tc != 0) { > smtc_tc_setup(vpe, tc, cpu); > + if (vpe != 0) { > + /* > + * Set MVP bit (possibly again). Do it > + * here to catch CPUs that have no TCs > + * bound to the VPE at reset. In that > + * case, a TC must be bound to the VPE > + * before we can set VPEControl[MVP] > + */ > + write_vpe_c0_vpeconf0( > + read_vpe_c0_vpeconf0() | > + VPECONF0_MVP); > + } > cpu++; > } > printk(" %d", tc); > > > From pavel@ucw.cz Thu Jul 2 08:51:59 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 02 Jul 2009 08:52:05 +0200 (CEST) Received: from atrey.karlin.mff.cuni.cz ([195.113.26.193]:57227 "EHLO atrey.karlin.mff.cuni.cz" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492064AbZGBGv7 (ORCPT ); Thu, 2 Jul 2009 08:51:59 +0200 Received: by atrey.karlin.mff.cuni.cz (Postfix, from userid 512) id C3BB0F02D8; Thu, 2 Jul 2009 08:46:19 +0200 (CEST) Date: Thu, 2 Jul 2009 08:46:12 +0200 From: Pavel Machek To: Ralf Baechle Cc: Wu Zhangjin , LKML , linux-mips@linux-mips.org Subject: Re: [BUG] MIPS: Hibernation in the latest linux-mips:master branch not work Message-ID: <20090702064612.GB18157@elf.ucw.cz> References: <1246372868.19049.17.camel@falcon> <20090630144540.GA18212@linux-mips.org> <1246374687.20482.10.camel@falcon> <20090701180715.GA23121@linux-mips.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20090701180715.GA23121@linux-mips.org> X-Warning: Reading this can be dangerous to your mental health. User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23609 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: pavel@ucw.cz Precedence: bulk X-list: linux-mips On Wed 2009-07-01 19:07:15, Ralf Baechle wrote: > On Tue, Jun 30, 2009 at 11:11:27PM +0800, Wu Zhangjin wrote: > > > hi, ralf, in the latest master branch of linux-mips git repo, seems > > there is a need to select the SYS_SUPPORTS_HOTPLUG_CPU option in every > > uni-processor board, otherwise, the suspend/hibernation can not be used, > > because you have set: > > > > config ARCH_HIBERNATION_POSSIBLE > > def_bool y > > depends on SYS_SUPPORTS_HOTPLUG_CPU > > > > config ARCH_SUSPEND_POSSIBLE > > def_bool y > > depends on SYS_SUPPORTS_HOTPLUG_CPU > > > > so, the board-specific patch must be pushed by the maintainers of > > boards. and if the board support SMP, they must implement the > > mips-specific hotplug support, is this right? I have selected > > SYS_SUPPORTS_HOTPLUG_CPU in LEMOTE_FULONG and will push a relative patch > > later. > > I think below patch should take care of this problem. It simply assumes > that all uniprocessor systems support suspend and hibernate. That's an > assumption that I'm not to unhappy with though it may force us to fix a > few systems. > > Ralf > > Signed-off-by: Ralf Baechle Acked-by: Pavel Machek -- (english) http://www.livejournal.com/~pavelmachek (cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html From ralf@h5.dl5rb.org.uk Thu Jul 2 12:52:45 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 02 Jul 2009 12:52:51 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:43008 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492119AbZGBKwp (ORCPT ); Thu, 2 Jul 2009 12:52:45 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id n62AkoNm007636; Thu, 2 Jul 2009 11:46:50 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id n62AknSa007634; Thu, 2 Jul 2009 11:46:49 +0100 Date: Thu, 2 Jul 2009 11:46:49 +0100 From: Ralf Baechle To: Wu Zhangjin Cc: Bartlomiej Zolnierkiewicz , Jeff Chua , Etienne Basset , David Miller , rjw@sisk.pl, linux-kernel@vger.kernel.org, kernel-testers@vger.kernel.org, linux-mips@linux-mips.org, linux-ide@vger.kernel.org Subject: Re: [Bug #13663] suspend to ram regression (IDE related) Message-ID: <20090702104649.GC14804@linux-mips.org> References: <1246459661.9660.40.camel@falcon> <200907011821.26091.bzolnier@gmail.com> <200907011829.16850.bzolnier@gmail.com> <1246499203.9660.52.camel@falcon> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1246499203.9660.52.camel@falcon> User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23610 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Thu, Jul 02, 2009 at 09:46:43AM +0800, Wu Zhangjin wrote: > Sorry, I can not apply this patch directly, which original version did > you use? I used the one in the master branch of linux-mips development > git repository. The master branch of linux-mips.org has no IDE changes over Linus' tree. Ralf From ralf@h5.dl5rb.org.uk Thu Jul 2 12:56:14 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 02 Jul 2009 12:56:22 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:42696 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1491955AbZGBK4O (ORCPT ); Thu, 2 Jul 2009 12:56:14 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id n62AoOIV007722; Thu, 2 Jul 2009 11:50:24 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id n62AoOLU007720; Thu, 2 Jul 2009 11:50:24 +0100 Date: Thu, 2 Jul 2009 11:50:24 +0100 From: Ralf Baechle To: Wu Zhangjin Cc: LKML , linux-mips@linux-mips.org, Pavel Machek Subject: Re: [BUG] MIPS: Hibernation in the latest linux-mips:master branch not work Message-ID: <20090702105024.GD14804@linux-mips.org> References: <1246372868.19049.17.camel@falcon> <20090630144540.GA18212@linux-mips.org> <1246374687.20482.10.camel@falcon> <20090701180715.GA23121@linux-mips.org> <1246496647.9660.46.camel@falcon> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1246496647.9660.46.camel@falcon> User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23611 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Thu, Jul 02, 2009 at 09:04:07AM +0800, Wu Zhangjin wrote: > > > hi, ralf, in the latest master branch of linux-mips git repo, seems > > > there is a need to select the SYS_SUPPORTS_HOTPLUG_CPU option in every > > > uni-processor board, otherwise, the suspend/hibernation can not be used, > > > because you have set: > > > > > > config ARCH_HIBERNATION_POSSIBLE > > > def_bool y > > > depends on SYS_SUPPORTS_HOTPLUG_CPU > > > > > > config ARCH_SUSPEND_POSSIBLE > > > def_bool y > > > depends on SYS_SUPPORTS_HOTPLUG_CPU > > > > > > so, the board-specific patch must be pushed by the maintainers of > > > boards. and if the board support SMP, they must implement the > > > mips-specific hotplug support, is this right? I have selected > > > SYS_SUPPORTS_HOTPLUG_CPU in LEMOTE_FULONG and will push a relative patch > > > later. > > > > I think below patch should take care of this problem. It simply assumes > > that all uniprocessor systems support suspend and hibernate. That's an > > assumption that I'm not to unhappy with though it may force us to fix a > > few systems. > > > > This patch is better. > > Thanks! > Wu Zhangjin Thanks, patch applied. You're welcome! Ralf From MAILER-DAEMON Thu Jul 2 17:21:57 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 02 Jul 2009 17:22:03 +0200 (CEST) Received: from mail-ew0-f214.google.com ([209.85.219.214]:50091 "EHLO mail-ew0-f214.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492195AbZGBPV4 (ORCPT ); Thu, 2 Jul 2009 17:21:56 +0200 Received: by ewy10 with SMTP id 10so2090979ewy.0 for ; Thu, 02 Jul 2009 08:16:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer; bh=2a3nIkrXSlmoDjxqLvHaZs88E733Z2LZMrZPBdHU45M=; b=QPhsD3XXi95z78C4ll6FO8uHKYSrEMZJmkhpbK2JwJZABUHXCnhUq/SXqUk2ekTyqu RjI9fEaybVMvjcimzFy1poH7wJN0oys5R4bbAjpIK/0a32LGhn+36eSBbdo7GSQeWqP6 JA5Z2XTKDMmpObJJiVDsraXF/MGZQn/09wjDk= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer; b=QJQdyUkF1QsRuKNJB5lKKjEOytN/xVwmLAUh7okZFm1uXx6ROXglf1EDtqs6HFQV75 jqzMLUlmf1Gi05BuJK0fcKP1SpzU1kGV4LuWUxk/j1nNQ+EKTY6o48laBAZNqP6hULLw /gOGjJ7ifRzHOII8LmgOhJFRkQcL21oBzA71g= Received: by 10.210.19.7 with SMTP id 7mr1085417ebs.55.1246547766472; Thu, 02 Jul 2009 08:16:06 -0700 (PDT) Received: from localhost.localdomain ([222.92.8.142]) by mx.google.com with ESMTPS id 10sm60181eyd.28.2009.07.02.08.16.00 (version=TLSv1/SSLv3 cipher=RC4-MD5); Thu, 02 Jul 2009 08:16:05 -0700 (PDT) From: Wu To: linux-kernel@vger.kernel.org, linux-mips@linux-mips.org, ralf@linux-mips.org Cc: Wu Zhangjin , Yan Hua , Philippe Vachon , Zhang Le , Zhang Fuxin , loongson-dev , Liu Junliang , Erwan Lerale , Arnaud Patard Subject: [PATCH v4 00/16] Cleanup Lemote FuLoong2e Support Date: Thu, 2 Jul 2009 23:15:52 +0800 Message-Id: X-Mailer: git-send-email 1.6.2.1 Return-Path: <> X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23612 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips From: Wu Zhangjin This patch series is the -v4 version of the loongson-PATCH-v3 series, but it only include the cleanup for fuloong2e support and necessary preparation for future fuloong-2f and yeeloong-2f support. The git branch of this patch series is: git://dev.lemote.com/rt4ls.git linux-loongson/dev/fuloong2e or http://dev.lemote.com/cgit/rt4ls.git/log/?h=linux-loongson/dev/fuloong2e Wu Zhangjin (16): [loongson] eary_printk: Remove existing implementation [loongson] kgdb: Remove out-of-date board-specific source code [loongson] early_printk: add new implmentation [loongson] pm: Remove redundant source code [loongson] pm: clean up the reboot support [loongson] pci: use existing mips_io_port_base [loongson] split the implementation of prom,setup parts [loongson] clean up the coding style [loongson] pci: clean up pcimap setup [loongson] rtc: enable legacy RTC driver on fulong [loongson] add oprofile support [loongson] change naming methods [loongson] split common loongson source code out [loongson] add a machtype kernel command line argument [loongson] add gcc 4.4 support for Loongson2E [loongson] update the default config file for fuloong2e Documentation/kernel-parameters.txt | 4 + arch/mips/Kconfig | 52 +- arch/mips/Makefile | 15 +- arch/mips/configs/fulong_defconfig | 1912 -------------------- arch/mips/configs/fuloong2e_defconfig | 1819 +++++++++++++++++++ arch/mips/include/asm/bootinfo.h | 12 + .../asm/mach-lemote/cpu-feature-overrides.h | 59 - arch/mips/include/asm/mach-lemote/dma-coherence.h | 68 - arch/mips/include/asm/mach-lemote/mc146818rtc.h | 36 - arch/mips/include/asm/mach-lemote/pci.h | 30 - arch/mips/include/asm/mach-lemote/war.h | 25 - .../asm/mach-loongson/cpu-feature-overrides.h | 59 + .../mips/include/asm/mach-loongson/dma-coherence.h | 68 + arch/mips/include/asm/mach-loongson/loongson.h | 67 + arch/mips/include/asm/mach-loongson/machine.h | 22 + arch/mips/include/asm/mach-loongson/mc146818rtc.h | 36 + arch/mips/include/asm/mach-loongson/mem.h | 30 + arch/mips/include/asm/mach-loongson/pci.h | 37 + arch/mips/include/asm/mach-loongson/war.h | 25 + arch/mips/include/asm/mips-boards/bonito64.h | 2 +- arch/mips/lemote/lm2e/Makefile | 7 - arch/mips/lemote/lm2e/bonito-irq.c | 74 - arch/mips/lemote/lm2e/dbg_io.c | 146 -- arch/mips/lemote/lm2e/irq.c | 143 -- arch/mips/lemote/lm2e/mem.c | 23 - arch/mips/lemote/lm2e/pci.c | 97 - arch/mips/lemote/lm2e/prom.c | 97 - arch/mips/lemote/lm2e/reset.c | 41 - arch/mips/lemote/lm2e/setup.c | 111 -- arch/mips/loongson/Kconfig | 31 + arch/mips/loongson/Makefile | 11 + arch/mips/loongson/common/Makefile | 11 + arch/mips/loongson/common/bonito-irq.c | 51 + arch/mips/loongson/common/cmdline.c | 52 + arch/mips/loongson/common/early_printk.c | 38 + arch/mips/loongson/common/env.c | 58 + arch/mips/loongson/common/init.c | 30 + arch/mips/loongson/common/irq.c | 74 + arch/mips/loongson/common/machtype.c | 50 + arch/mips/loongson/common/mem.c | 35 + arch/mips/loongson/common/pci.c | 83 + arch/mips/loongson/common/reset.c | 39 + arch/mips/loongson/common/setup.c | 60 + arch/mips/loongson/common/time.c | 27 + arch/mips/loongson/fuloong-2e/Makefile | 7 + arch/mips/loongson/fuloong-2e/irq.c | 71 + arch/mips/loongson/fuloong-2e/reset.c | 24 + arch/mips/oprofile/Makefile | 1 + arch/mips/oprofile/common.c | 4 + arch/mips/oprofile/op_model_loongson2.c | 177 ++ arch/mips/pci/Makefile | 2 +- arch/mips/pci/fixup-fuloong2e.c | 224 +++ arch/mips/pci/fixup-lm2e.c | 242 --- arch/mips/pci/ops-bonito64.c | 4 +- 54 files changed, 3372 insertions(+), 3151 deletions(-) delete mode 100644 arch/mips/configs/fulong_defconfig create mode 100644 arch/mips/configs/fuloong2e_defconfig delete mode 100644 arch/mips/include/asm/mach-lemote/cpu-feature-overrides.h delete mode 100644 arch/mips/include/asm/mach-lemote/dma-coherence.h delete mode 100644 arch/mips/include/asm/mach-lemote/mc146818rtc.h delete mode 100644 arch/mips/include/asm/mach-lemote/pci.h delete mode 100644 arch/mips/include/asm/mach-lemote/war.h create mode 100644 arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h create mode 100644 arch/mips/include/asm/mach-loongson/dma-coherence.h create mode 100644 arch/mips/include/asm/mach-loongson/loongson.h create mode 100644 arch/mips/include/asm/mach-loongson/machine.h create mode 100644 arch/mips/include/asm/mach-loongson/mc146818rtc.h create mode 100644 arch/mips/include/asm/mach-loongson/mem.h create mode 100644 arch/mips/include/asm/mach-loongson/pci.h create mode 100644 arch/mips/include/asm/mach-loongson/war.h delete mode 100644 arch/mips/lemote/lm2e/Makefile delete mode 100644 arch/mips/lemote/lm2e/bonito-irq.c delete mode 100644 arch/mips/lemote/lm2e/dbg_io.c delete mode 100644 arch/mips/lemote/lm2e/irq.c delete mode 100644 arch/mips/lemote/lm2e/mem.c delete mode 100644 arch/mips/lemote/lm2e/pci.c delete mode 100644 arch/mips/lemote/lm2e/prom.c delete mode 100644 arch/mips/lemote/lm2e/reset.c delete mode 100644 arch/mips/lemote/lm2e/setup.c create mode 100644 arch/mips/loongson/Kconfig create mode 100644 arch/mips/loongson/Makefile create mode 100644 arch/mips/loongson/common/Makefile create mode 100644 arch/mips/loongson/common/bonito-irq.c create mode 100644 arch/mips/loongson/common/cmdline.c create mode 100644 arch/mips/loongson/common/early_printk.c create mode 100644 arch/mips/loongson/common/env.c create mode 100644 arch/mips/loongson/common/init.c create mode 100644 arch/mips/loongson/common/irq.c create mode 100644 arch/mips/loongson/common/machtype.c create mode 100644 arch/mips/loongson/common/mem.c create mode 100644 arch/mips/loongson/common/pci.c create mode 100644 arch/mips/loongson/common/reset.c create mode 100644 arch/mips/loongson/common/setup.c create mode 100644 arch/mips/loongson/common/time.c create mode 100644 arch/mips/loongson/fuloong-2e/Makefile create mode 100644 arch/mips/loongson/fuloong-2e/irq.c create mode 100644 arch/mips/loongson/fuloong-2e/reset.c create mode 100644 arch/mips/oprofile/op_model_loongson2.c create mode 100644 arch/mips/pci/fixup-fuloong2e.c delete mode 100644 arch/mips/pci/fixup-lm2e.c From wuzhangjin@gmail.com Thu Jul 2 17:24:13 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 02 Jul 2009 17:24:20 +0200 (CEST) Received: from mail-ew0-f214.google.com ([209.85.219.214]:49946 "EHLO mail-ew0-f214.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492196AbZGBPYN (ORCPT ); Thu, 2 Jul 2009 17:24:13 +0200 Received: by ewy10 with SMTP id 10so2093309ewy.0 for ; Thu, 02 Jul 2009 08:18:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer:in-reply-to:references; bh=8+9KmVDvJ2rAQPBA4FihJPrCl/XrQKisFG4GgmwVtBQ=; b=amSH/VKK1fVDusz5NxqV/cA0X8JW7x42W8oOv3OjccrSvM4hRAVs/qQHM/0x6V6kcQ OTWAOUnHxlqMWfRVbkT4C0glGEbBeKZx78uIF7I/ZmHuNYTFCU4o5yvpok6ZG9phMMi8 UWQcarK+VK47yFHxSV61h4XJJIn+Pz0XRSBPE= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; b=QagfQsN1/I8QfpyrRM/Cm8Hsa13QIB3lzhoncHBSXC8Wyv2ujRIPpnx39FxnL0PwDF JQBQe5zzR/H4MvY/X3qFDps45TGqA59VJLIkFO7dMfgznUybBZt4ubsUR+C3R6Lf46Eu FO9Bxb1DWArWDBCZCNVukkpGP8CnhNjjZnqwg= Received: by 10.210.133.2 with SMTP id g2mr1116297ebd.23.1246547902095; Thu, 02 Jul 2009 08:18:22 -0700 (PDT) Received: from localhost.localdomain ([222.92.8.142]) by mx.google.com with ESMTPS id 24sm3146677eyx.23.2009.07.02.08.18.15 (version=TLSv1/SSLv3 cipher=RC4-MD5); Thu, 02 Jul 2009 08:18:21 -0700 (PDT) From: Wu Zhangjin To: linux-kernel@vger.kernel.org, linux-mips@linux-mips.org, ralf@linux-mips.org, Jason Wessel Cc: Wu Zhangjin , Yan Hua , Philippe Vachon , Zhang Le , Zhang Fuxin , loongson-dev , Liu Junliang , Erwan Lerale , Arnaud Patard Subject: [PATCH v4 01/16] [loongson] eary_printk: Remove existing implementation Date: Thu, 2 Jul 2009 23:18:09 +0800 Message-Id: <5ba055de70110a166fdffb2871d3207c9abb4d48.1246546684.git.wuzhangjin@gmail.com> X-Mailer: git-send-email 1.6.2.1 In-Reply-To: References: Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23613 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips From: Wu Zhangjin This patch will remove the existing implementation of early_printk in fulong. for this old implementation is based on the board-specific source code(dbg_io.c), but dbg_io.c is out-of-date: as the commit: 8d60a903d986ffa26c41f0092320a3b9da20bfaf shows, dbg_io.c is not needed. it will be removed in the next patch, and the new implementation of early_printk will be added later. Signed-off-by: Wu Zhangjin --- arch/mips/lemote/lm2e/prom.c | 6 ------ 1 files changed, 0 insertions(+), 6 deletions(-) diff --git a/arch/mips/lemote/lm2e/prom.c b/arch/mips/lemote/lm2e/prom.c index 7edc15d..d78cedf 100644 --- a/arch/mips/lemote/lm2e/prom.c +++ b/arch/mips/lemote/lm2e/prom.c @@ -21,7 +21,6 @@ extern unsigned long bus_clock; extern unsigned long cpu_clock_freq; extern unsigned int memsize, highmemsize; -extern int putDebugChar(unsigned char byte); static int argc; /* pmon passes arguments in 32bit pointers */ @@ -90,8 +89,3 @@ do { \ void __init prom_free_prom_memory(void) { } - -void prom_putchar(char c) -{ - putDebugChar(c); -} -- 1.6.2.1 From wuzhangjin@gmail.com Thu Jul 2 17:25:39 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 02 Jul 2009 17:25:46 +0200 (CEST) Received: from mail-ew0-f214.google.com ([209.85.219.214]:42195 "EHLO mail-ew0-f214.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492203AbZGBPZj (ORCPT ); Thu, 2 Jul 2009 17:25:39 +0200 Received: by ewy10 with SMTP id 10so2094583ewy.0 for ; Thu, 02 Jul 2009 08:19:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer:in-reply-to:references; bh=N4GU39/OWRpoS71791R3vDXAO8U5bxj5L7UW49xJ/ys=; b=CZzV4lylTmB85XbZF0sWznm1HT2Ny0ekO0wX85vblAckEz951LDiCHHhoNSWYfixXt Bch97DmtVVZ+7vaU1b4vEZpBeyWNOHVVcuIRZhW0oKpLKHwDeL5ivY4Whu9pZOXuOkGZ oJ8pLpCcKIOF2DkZ41OmZmOpGosXH1vBzKDXc= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; b=DnFlmkfXsd43rLMvP4rS6Uo6kvLl6G7MrOc7kjxJDL8XHDYBxx2gDdimUICkoArODU QF1lBum7wf45rRahYA0+KiYdykEDB4vPxBvg2ze3uK69z5pJnG003nrtMV7U78+YuV03 Evy46WjLhirv5MJWkxppMPQszwty5UTzCcuag= Received: by 10.211.166.2 with SMTP id t2mr206547ebo.49.1246547988925; Thu, 02 Jul 2009 08:19:48 -0700 (PDT) Received: from localhost.localdomain ([222.92.8.142]) by mx.google.com with ESMTPS id 28sm37703eye.6.2009.07.02.08.19.40 (version=TLSv1/SSLv3 cipher=RC4-MD5); Thu, 02 Jul 2009 08:19:48 -0700 (PDT) From: Wu Zhangjin To: linux-kernel@vger.kernel.org, linux-mips@linux-mips.org, ralf@linux-mips.org, Jason Wessel Cc: Wu Zhangjin , Yan Hua , Philippe Vachon , Zhang Le , Zhang Fuxin , loongson-dev , Liu Junliang , Erwan Lerale , Arnaud Patard Subject: [PATCH v4 02/16] [loongson] kgdb: Remove out-of-date board-specific source code Date: Thu, 2 Jul 2009 23:19:33 +0800 Message-Id: <0e211b21ed263c482b3717e8feb9bd84e1a11839.1246546684.git.wuzhangjin@gmail.com> X-Mailer: git-send-email 1.6.2.1 In-Reply-To: References: Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23614 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips From: Wu Zhangjin as the commit: 8854700115ecf8aa6f087aa915b7b6cf18090d39 shows, the new mips-specific kgdb implementation not need this board-specific source code, just remove it. Signed-off-by: Wu Zhangjin --- arch/mips/lemote/lm2e/Makefile | 2 +- arch/mips/lemote/lm2e/dbg_io.c | 146 ---------------------------------------- 2 files changed, 1 insertions(+), 147 deletions(-) delete mode 100644 arch/mips/lemote/lm2e/dbg_io.c diff --git a/arch/mips/lemote/lm2e/Makefile b/arch/mips/lemote/lm2e/Makefile index d34671d..b0c0339 100644 --- a/arch/mips/lemote/lm2e/Makefile +++ b/arch/mips/lemote/lm2e/Makefile @@ -2,6 +2,6 @@ # Makefile for Lemote Fulong mini-PC board. # -obj-y += setup.o prom.o reset.o irq.o pci.o bonito-irq.o dbg_io.o mem.o +obj-y += setup.o prom.o reset.o irq.o pci.o bonito-irq.o mem.o EXTRA_CFLAGS += -Werror diff --git a/arch/mips/lemote/lm2e/dbg_io.c b/arch/mips/lemote/lm2e/dbg_io.c deleted file mode 100644 index 6c95da3..0000000 --- a/arch/mips/lemote/lm2e/dbg_io.c +++ /dev/null @@ -1,146 +0,0 @@ -/* - * Copyright 2001 MontaVista Software Inc. - * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net - * Copyright (C) 2000, 2001 Ralf Baechle (ralf@gnu.org) - * - * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology - * Author: Fuxin Zhang, zhangfx@lemote.com - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - * - */ - -#include -#include -#include - -#include - -#define UART16550_BAUD_2400 2400 -#define UART16550_BAUD_4800 4800 -#define UART16550_BAUD_9600 9600 -#define UART16550_BAUD_19200 19200 -#define UART16550_BAUD_38400 38400 -#define UART16550_BAUD_57600 57600 -#define UART16550_BAUD_115200 115200 - -#define UART16550_PARITY_NONE 0 -#define UART16550_PARITY_ODD 0x08 -#define UART16550_PARITY_EVEN 0x18 -#define UART16550_PARITY_MARK 0x28 -#define UART16550_PARITY_SPACE 0x38 - -#define UART16550_DATA_5BIT 0x0 -#define UART16550_DATA_6BIT 0x1 -#define UART16550_DATA_7BIT 0x2 -#define UART16550_DATA_8BIT 0x3 - -#define UART16550_STOP_1BIT 0x0 -#define UART16550_STOP_2BIT 0x4 - -/* ----------------------------------------------------- */ - -/* === CONFIG === */ -#ifdef CONFIG_64BIT -#define BASE (0xffffffffbfd003f8) -#else -#define BASE (0xbfd003f8) -#endif - -#define MAX_BAUD BASE_BAUD -/* === END OF CONFIG === */ - -#define REG_OFFSET 1 - -/* register offset */ -#define OFS_RCV_BUFFER 0 -#define OFS_TRANS_HOLD 0 -#define OFS_SEND_BUFFER 0 -#define OFS_INTR_ENABLE (1*REG_OFFSET) -#define OFS_INTR_ID (2*REG_OFFSET) -#define OFS_DATA_FORMAT (3*REG_OFFSET) -#define OFS_LINE_CONTROL (3*REG_OFFSET) -#define OFS_MODEM_CONTROL (4*REG_OFFSET) -#define OFS_RS232_OUTPUT (4*REG_OFFSET) -#define OFS_LINE_STATUS (5*REG_OFFSET) -#define OFS_MODEM_STATUS (6*REG_OFFSET) -#define OFS_RS232_INPUT (6*REG_OFFSET) -#define OFS_SCRATCH_PAD (7*REG_OFFSET) - -#define OFS_DIVISOR_LSB (0*REG_OFFSET) -#define OFS_DIVISOR_MSB (1*REG_OFFSET) - -/* memory-mapped read/write of the port */ -#define UART16550_READ(y) readb((char *)BASE + (y)) -#define UART16550_WRITE(y, z) writeb(z, (char *)BASE + (y)) - -void debugInit(u32 baud, u8 data, u8 parity, u8 stop) -{ - u32 divisor; - - /* disable interrupts */ - UART16550_WRITE(OFS_INTR_ENABLE, 0); - - /* set up buad rate */ - /* set DIAB bit */ - UART16550_WRITE(OFS_LINE_CONTROL, 0x80); - - /* set divisor */ - divisor = MAX_BAUD / baud; - UART16550_WRITE(OFS_DIVISOR_LSB, divisor & 0xff); - UART16550_WRITE(OFS_DIVISOR_MSB, (divisor & 0xff00) >> 8); - - /* clear DIAB bit */ - UART16550_WRITE(OFS_LINE_CONTROL, 0x0); - - /* set data format */ - UART16550_WRITE(OFS_DATA_FORMAT, data | parity | stop); -} - -static int remoteDebugInitialized; - -u8 getDebugChar(void) -{ - if (!remoteDebugInitialized) { - remoteDebugInitialized = 1; - debugInit(UART16550_BAUD_115200, - UART16550_DATA_8BIT, - UART16550_PARITY_NONE, UART16550_STOP_1BIT); - } - - while ((UART16550_READ(OFS_LINE_STATUS) & 0x1) == 0) ; - return UART16550_READ(OFS_RCV_BUFFER); -} - -int putDebugChar(u8 byte) -{ - if (!remoteDebugInitialized) { - remoteDebugInitialized = 1; - /* - debugInit(UART16550_BAUD_115200, - UART16550_DATA_8BIT, - UART16550_PARITY_NONE, UART16550_STOP_1BIT); */ - } - - while ((UART16550_READ(OFS_LINE_STATUS) & 0x20) == 0) ; - UART16550_WRITE(OFS_SEND_BUFFER, byte); - return 1; -} -- 1.6.2.1 From wuzhangjin@gmail.com Thu Jul 2 17:26:27 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 02 Jul 2009 17:26:33 +0200 (CEST) Received: from mail-ew0-f214.google.com ([209.85.219.214]:39931 "EHLO mail-ew0-f214.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492202AbZGBP01 (ORCPT ); Thu, 2 Jul 2009 17:26:27 +0200 Received: by ewy10 with SMTP id 10so2095301ewy.0 for ; Thu, 02 Jul 2009 08:20:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer:in-reply-to:references; bh=wHT9ztjTJqaBb+OnKZNKFUE6zNG2KRwLbU8b+rFlg5c=; b=ADAfP6qkEmJCDp1BvW79XfQyyZnKy14SKwpiTWaUnF8NX+ttnL3NhrVo6ieM+H1ms+ UXHco3BENAAedctYN+y7gK5fT1Gv6+O3xeFiIcHtUD6j+ffZzkfMxm85MMmGPUVxMdma wNIgmQeec+JRMZnf5EH6GgkroGz7X0ZoLzLDw= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; b=PhfHUoL6M1BwwR7KkK5jw3CvNcNjxO0pZz3XqaibvLrjzhzIrvGk7OmPOjX9cWNLVy b3r2j8PKajO5VROpc9nfYlJ8pcW80GlTR/dzEPwo+QJIiOGsI5ehioDdYkTcXH5ffX5u 5zrl6IPE/bzECqfzwnPrHWpLMAujYbvmXCQOY= Received: by 10.210.35.10 with SMTP id i10mr205583ebi.52.1246548036742; Thu, 02 Jul 2009 08:20:36 -0700 (PDT) Received: from localhost.localdomain ([222.92.8.142]) by mx.google.com with ESMTPS id 7sm4788640eyb.5.2009.07.02.08.20.28 (version=TLSv1/SSLv3 cipher=RC4-MD5); Thu, 02 Jul 2009 08:20:35 -0700 (PDT) From: Wu Zhangjin To: linux-kernel@vger.kernel.org, linux-mips@linux-mips.org, ralf@linux-mips.org, Jason Wessel Cc: Wu Zhangjin , Yan Hua , Philippe Vachon , Zhang Le , Zhang Fuxin , loongson-dev , Liu Junliang , Erwan Lerale , Arnaud Patard Subject: [PATCH v4 03/16] [loongson] early_printk: add new implmentation Date: Thu, 2 Jul 2009 23:20:20 +0800 Message-Id: <9e23b4150f183c0817f2abbb95525279c2006a83.1246546684.git.wuzhangjin@gmail.com> X-Mailer: git-send-email 1.6.2.1 In-Reply-To: References: Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23615 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips From: Wu Zhangjin This patch is based on the implementation in the lm2e-fixes branch of Philippe's git://git.linux-cisco.org/linux-mips.git and the malta-specific early_printk implementation. Signed-off-by: Wu Zhangjin --- arch/mips/lemote/lm2e/Makefile | 5 ++++ arch/mips/lemote/lm2e/early_printk.c | 41 ++++++++++++++++++++++++++++++++++ 2 files changed, 46 insertions(+), 0 deletions(-) create mode 100644 arch/mips/lemote/lm2e/early_printk.c diff --git a/arch/mips/lemote/lm2e/Makefile b/arch/mips/lemote/lm2e/Makefile index b0c0339..f191732 100644 --- a/arch/mips/lemote/lm2e/Makefile +++ b/arch/mips/lemote/lm2e/Makefile @@ -4,4 +4,9 @@ obj-y += setup.o prom.o reset.o irq.o pci.o bonito-irq.o mem.o +# +# Early printk support +# +obj-$(CONFIG_EARLY_PRINTK) += early_printk.o + EXTRA_CFLAGS += -Werror diff --git a/arch/mips/lemote/lm2e/early_printk.c b/arch/mips/lemote/lm2e/early_printk.c new file mode 100644 index 0000000..811c7de --- /dev/null +++ b/arch/mips/lemote/lm2e/early_printk.c @@ -0,0 +1,41 @@ +/* early printk support + * + * Copyright (c) 2009 Philippe Vachon + * Copyright (C) 2009 Lemote Inc. & Insititute of Computing Technology + * Author: Wu Zhangjin, wuzj@lemote.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ +#include +#include +#include + +#include + +#define UART_BASE (BONITO_PCIIO_BASE + 0x3f8) + +#define PORT(base, offset) (u8 *)(base + offset) + +static inline unsigned int serial_in(phys_addr_t base, int offset) +{ + return readb(PORT(base, offset)); +} + +static inline void serial_out(phys_addr_t base, int offset, int value) +{ + writeb(value, PORT(base, offset)); +} + +void prom_putchar(char c) +{ + phys_addr_t uart_base = + (phys_addr_t) ioremap_nocache(UART_BASE, 8); + + while ((serial_in(uart_base, UART_LSR) & UART_LSR_THRE) == 0) + ; + + serial_out(uart_base, UART_TX, c); +} -- 1.6.2.1 From wuzhangjin@gmail.com Thu Jul 2 17:26:56 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 02 Jul 2009 17:26:59 +0200 (CEST) Received: from mail-ew0-f214.google.com ([209.85.219.214]:39931 "EHLO mail-ew0-f214.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492203AbZGBP04 (ORCPT ); Thu, 2 Jul 2009 17:26:56 +0200 Received: by mail-ew0-f214.google.com with SMTP id 10so2095301ewy.0 for ; Thu, 02 Jul 2009 08:21:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer:in-reply-to:references; bh=aKm/7IpHnEXDxEKScWwpTKl3q0tjxhNjcE1YZwuHFf4=; b=u5GCzIEboXUnWnnElBEkx98fcN6w+zGrbtLhN94pmPAR4pvtqzkMpQXy7AcCtL2Xjk acKX78ll8bt7YAmldpNQq9X6lmmfy0Rox+1oBnTw8YpADmlVbjbCKkqY0M1AtauVstwf GEcSFakMy9t34iB01jA5IkP3+znRiJ5jnfqsg= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; b=hRGD4ER6s2KtDilNSc+GGC4kotFcCdsF7xFsgitechJ2pgUbK3law+aeq4kO1BlA62 gu6GxB/5b4eN7OXEjRbGtEqndYYGkG0LdOyEUS8E7TWseLv4YiycjRMRrRWj22KZfnf1 3FU+9Fv+I4w/Rre6neSX/tTbkKdEcEIGuzsLE= Received: by 10.210.27.14 with SMTP id a14mr1130644eba.7.1246548070978; Thu, 02 Jul 2009 08:21:10 -0700 (PDT) Received: from localhost.localdomain ([222.92.8.142]) by mx.google.com with ESMTPS id 7sm5367141eyg.7.2009.07.02.08.21.03 (version=TLSv1/SSLv3 cipher=RC4-MD5); Thu, 02 Jul 2009 08:21:10 -0700 (PDT) From: Wu Zhangjin To: linux-kernel@vger.kernel.org, linux-mips@linux-mips.org, ralf@linux-mips.org, Jason Wessel Cc: Wu Zhangjin , Yan Hua , Philippe Vachon , Zhang Le , Zhang Fuxin , loongson-dev , Liu Junliang , Erwan Lerale , Arnaud Patard Subject: [PATCH v4 04/16] [loongson] pm: Remove redundant source code Date: Thu, 2 Jul 2009 23:20:56 +0800 Message-Id: <93ba7839f73d96de29fa76647ca1fe90012a021c.1246546684.git.wuzhangjin@gmail.com> X-Mailer: git-send-email 1.6.2.1 In-Reply-To: References: Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23616 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips From: Wu Zhangjin the implmentation of loongson2e_power_off and loongson2e_halt is almostly the same, just reserve one of them. Signed-off-by: Wu Zhangjin --- arch/mips/lemote/lm2e/reset.c | 7 +------ 1 files changed, 1 insertions(+), 6 deletions(-) diff --git a/arch/mips/lemote/lm2e/reset.c b/arch/mips/lemote/lm2e/reset.c index 099387a..47ff506 100644 --- a/arch/mips/lemote/lm2e/reset.c +++ b/arch/mips/lemote/lm2e/reset.c @@ -28,14 +28,9 @@ static void loongson2e_halt(void) while (1) ; } -static void loongson2e_power_off(void) -{ - loongson2e_halt(); -} - void mips_reboot_setup(void) { _machine_restart = loongson2e_restart; _machine_halt = loongson2e_halt; - pm_power_off = loongson2e_power_off; + pm_power_off = loongson2e_halt; } -- 1.6.2.1 From wuzhangjin@gmail.com Thu Jul 2 17:27:34 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 02 Jul 2009 17:27:41 +0200 (CEST) Received: from mail-ew0-f214.google.com ([209.85.219.214]:34570 "EHLO mail-ew0-f214.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492203AbZGBP1e (ORCPT ); Thu, 2 Jul 2009 17:27:34 +0200 Received: by ewy10 with SMTP id 10so2096185ewy.0 for ; Thu, 02 Jul 2009 08:21:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer:in-reply-to:references; bh=pEMFXsJr7GfT+l3NzJoXOHTXJtdURRQ2gonPYj5lt8w=; b=mZQK8WE89rVHTG4aZLKxcb4Vu2Pr622910P5snAXtlWV8R2YVMGGCGSBVHSJYro/yE rZiZlW7PL+UsAj1P7Jya0d6L7JBReZU426IszpuEtDLBNm7rS/GIjVKnaNr2z2P5datb aXKj5TLhVOzdaCWposwHP5v/Hx8ZKlCON/bbs= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; b=UMqnZ2tnsQKYc1hprwjEYKclJ7AlI5iustZkY2KIQvFGD0uxqju1G2XrXjKLjBybdE hrkQg+HJhBkyxdciNDqBjzYqqcir0u5B4t67+WKuJXjL7AqI0hmeFzQ5s2wYBaUXMBy1 ml/MYisyvOk3+0T9N89zZ7YAQN4xBbgOHVNwM= Received: by 10.210.67.4 with SMTP id p4mr224535eba.21.1246548102437; Thu, 02 Jul 2009 08:21:42 -0700 (PDT) Received: from localhost.localdomain ([222.92.8.142]) by mx.google.com with ESMTPS id 5sm2653799eyf.42.2009.07.02.08.21.35 (version=TLSv1/SSLv3 cipher=RC4-MD5); Thu, 02 Jul 2009 08:21:41 -0700 (PDT) From: Wu Zhangjin To: linux-kernel@vger.kernel.org, linux-mips@linux-mips.org, ralf@linux-mips.org Cc: Wu Zhangjin , Yan Hua , Philippe Vachon , Zhang Le , Zhang Fuxin , loongson-dev , Liu Junliang , Erwan Lerale , Arnaud Patard Subject: [PATCH v4 05/16] [loongson] pm: clean up the reboot support Date: Thu, 2 Jul 2009 23:21:27 +0800 Message-Id: <1ec9ff2c1bbb1d27824afed422c52e8d7af24c40.1246546684.git.wuzhangjin@gmail.com> X-Mailer: git-send-email 1.6.2.1 In-Reply-To: References: Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23617 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips From: Wu Zhangjin several magic numbers have been replaced by relative macros, which will be more readable and understandable. Signed-off-by: Wu Zhangjin --- arch/mips/lemote/lm2e/reset.c | 18 ++++++++++-------- 1 files changed, 10 insertions(+), 8 deletions(-) diff --git a/arch/mips/lemote/lm2e/reset.c b/arch/mips/lemote/lm2e/reset.c index 47ff506..7758093 100644 --- a/arch/mips/lemote/lm2e/reset.c +++ b/arch/mips/lemote/lm2e/reset.c @@ -6,21 +6,23 @@ * * Copyright (C) 2007 Lemote, Inc. & Institute of Computing Technology * Author: Fuxin Zhang, zhangfx@lemote.com + * Copyright (C) 2009 Lemote, Inc. & Institute of Computing Technology + * Author: Zhangjin Wu, wuzj@lemote.com */ #include +#include #include +#include static void loongson2e_restart(char *command) { -#ifdef CONFIG_32BIT - *(unsigned long *)0xbfe00104 &= ~(1 << 2); - *(unsigned long *)0xbfe00104 |= (1 << 2); -#else - *(unsigned long *)0xffffffffbfe00104 &= ~(1 << 2); - *(unsigned long *)0xffffffffbfe00104 |= (1 << 2); -#endif - __asm__ __volatile__("jr\t%0"::"r"(0xbfc00000)); + /* do preparation for reboot */ + BONITO_BONGENCFG &= ~(1 << 2); + BONITO_BONGENCFG |= (1 << 2); + + /* reboot via jumping to boot base address */ + ((void (*)(void))ioremap_nocache(BONITO_BOOT_BASE, 4)) (); } static void loongson2e_halt(void) -- 1.6.2.1 From wuzhangjin@gmail.com Thu Jul 2 17:28:15 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 02 Jul 2009 17:28:22 +0200 (CEST) Received: from mail-ew0-f214.google.com ([209.85.219.214]:55387 "EHLO mail-ew0-f214.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492206AbZGBP2P (ORCPT ); Thu, 2 Jul 2009 17:28:15 +0200 Received: by ewy10 with SMTP id 10so2096866ewy.0 for ; Thu, 02 Jul 2009 08:22:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer:in-reply-to:references; bh=b4qZqmPxvk2zrEB0HEVlpZDNOinMHu6xUtjw1YFLokI=; b=JQJVAaPaHZuDPmG75PZ5cer0sVO7DuBvLzWPaYibuYBVzG2Etncp9yQXGx04XZ4nYF wRbdAlQ4qa4b1F7jQ65D7UVtYSglncHyl7v0ZE0nQS5npoDiurPY/iGdCorFGRe3+Yew qpPGunv3F+0FgR2LzJilPwUnURp+CItsCJY5s= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; b=DfYCH7v6lZZXcB8kUkxS1IhE/QUC9Zsfxqde8+6eyCVwYfU9WtLQcKA5Jv5YeIHwIY lLzcfkL3zGuV20obi3uAmNfP2CdN9mshs3CfXU6g1+He+slIXEdwpL6sg4oQkJOyj3wl G2eJGenicxXp4C+rzLPnMQ5uOlzwGigq1j4io= Received: by 10.211.195.15 with SMTP id x15mr1093494ebp.59.1246548144881; Thu, 02 Jul 2009 08:22:24 -0700 (PDT) Received: from localhost.localdomain ([222.92.8.142]) by mx.google.com with ESMTPS id 28sm5801515eyg.44.2009.07.02.08.22.18 (version=TLSv1/SSLv3 cipher=RC4-MD5); Thu, 02 Jul 2009 08:22:24 -0700 (PDT) From: Wu Zhangjin To: linux-kernel@vger.kernel.org, linux-mips@linux-mips.org, ralf@linux-mips.org Cc: Wu Zhangjin , Yan Hua , Philippe Vachon , Zhang Le , Zhang Fuxin , loongson-dev , Liu Junliang , Erwan Lerale , Arnaud Patard Subject: [PATCH v4 06/16] [loongson] pci: use existing mips_io_port_base Date: Thu, 2 Jul 2009 23:22:11 +0800 Message-Id: X-Mailer: git-send-email 1.6.2.1 In-Reply-To: References: Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23618 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips From: Wu Zhangjin mips_io_port_base is initialized via set_io_port_base() in arch/mips/lemote/lm2e/setup.c, we can use it directly here. Signed-off-by: Wu Zhangjin --- arch/mips/lemote/lm2e/pci.c | 5 +---- 1 files changed, 1 insertions(+), 4 deletions(-) diff --git a/arch/mips/lemote/lm2e/pci.c b/arch/mips/lemote/lm2e/pci.c index 8be03a8..152efb6 100644 --- a/arch/mips/lemote/lm2e/pci.c +++ b/arch/mips/lemote/lm2e/pci.c @@ -84,10 +84,7 @@ static int __init pcibios_init(void) { ict_pcimap(); - loongson2e_pci_controller.io_map_base = - (unsigned long) ioremap(LOONGSON2E_IO_PORT_BASE, - loongson2e_pci_io_resource.end - - loongson2e_pci_io_resource.start + 1); + loongson2e_pci_controller.io_map_base = mips_io_port_base; register_pci_controller(&loongson2e_pci_controller); -- 1.6.2.1 From wuzhangjin@gmail.com Thu Jul 2 17:28:39 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 02 Jul 2009 17:28:46 +0200 (CEST) Received: from mail-ew0-f214.google.com ([209.85.219.214]:55387 "EHLO mail-ew0-f214.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492208AbZGBP2f (ORCPT ); Thu, 2 Jul 2009 17:28:35 +0200 Received: by mail-ew0-f214.google.com with SMTP id 10so2096866ewy.0 for ; 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Thu, 02 Jul 2009 08:22:49 -0700 (PDT) From: Wu Zhangjin To: linux-kernel@vger.kernel.org, linux-mips@linux-mips.org, ralf@linux-mips.org Cc: Wu Zhangjin , Yan Hua , Philippe Vachon , Zhang Le , Zhang Fuxin , loongson-dev , Liu Junliang , Erwan Lerale , Arnaud Patard Subject: [PATCH v4 07/16] [loongson] split the implementation of prom,setup parts Date: Thu, 2 Jul 2009 23:22:36 +0800 Message-Id: X-Mailer: git-send-email 1.6.2.1 In-Reply-To: References: Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23619 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips From: Wu Zhangjin This patch split the old initilization and setup implementation to several file, one file one logic function. the other main changes include: 1. as the script/checkpatch.pl suggests, use strict_strtol instead of simple_strtol in arch/mips/lemote/lm2e/cmdline.c 2. use the existed macros in asm/mips-boards/bonito64.h as the arguments of set_io_port_base() and remove the un-needed ones in asm/mach-lemote/pci.h Signed-off-by: Wu Zhangjin --- arch/mips/include/asm/mach-lemote/pci.h | 1 - arch/mips/lemote/lm2e/Makefile | 3 +- arch/mips/lemote/lm2e/cmdline.c | 53 ++++++++++++++++++ arch/mips/lemote/lm2e/env.c | 60 ++++++++++++++++++++ arch/mips/lemote/lm2e/init.c | 34 ++++++++++++ arch/mips/lemote/lm2e/machtype.c | 15 +++++ arch/mips/lemote/lm2e/mem.c | 13 +++++ arch/mips/lemote/lm2e/prom.c | 91 ------------------------------- arch/mips/lemote/lm2e/setup.c | 33 +----------- arch/mips/lemote/lm2e/time.c | 30 ++++++++++ 10 files changed, 208 insertions(+), 125 deletions(-) create mode 100644 arch/mips/lemote/lm2e/cmdline.c create mode 100644 arch/mips/lemote/lm2e/env.c create mode 100644 arch/mips/lemote/lm2e/init.c create mode 100644 arch/mips/lemote/lm2e/machtype.c delete mode 100644 arch/mips/lemote/lm2e/prom.c create mode 100644 arch/mips/lemote/lm2e/time.c diff --git a/arch/mips/include/asm/mach-lemote/pci.h b/arch/mips/include/asm/mach-lemote/pci.h index ea6aa14..0307e49 100644 --- a/arch/mips/include/asm/mach-lemote/pci.h +++ b/arch/mips/include/asm/mach-lemote/pci.h @@ -25,6 +25,5 @@ #define LOONGSON2E_PCI_MEM_START 0x14000000UL #define LOONGSON2E_PCI_MEM_END 0x1fffffffUL #define LOONGSON2E_PCI_IO_START 0x00004000UL -#define LOONGSON2E_IO_PORT_BASE 0x1fd00000UL #endif /* !_LEMOTE_PCI_H_ */ diff --git a/arch/mips/lemote/lm2e/Makefile b/arch/mips/lemote/lm2e/Makefile index f191732..a5bc1ef 100644 --- a/arch/mips/lemote/lm2e/Makefile +++ b/arch/mips/lemote/lm2e/Makefile @@ -2,7 +2,8 @@ # Makefile for Lemote Fulong mini-PC board. # -obj-y += setup.o prom.o reset.o irq.o pci.o bonito-irq.o mem.o +obj-y += setup.o init.o reset.o irq.o pci.o bonito-irq.o mem.o \ + env.o cmdline.o time.o machtype.o # # Early printk support diff --git a/arch/mips/lemote/lm2e/cmdline.c b/arch/mips/lemote/lm2e/cmdline.c new file mode 100644 index 0000000..442b935 --- /dev/null +++ b/arch/mips/lemote/lm2e/cmdline.c @@ -0,0 +1,53 @@ +/* + * Based on Ocelot Linux port, which is + * Copyright 2001 MontaVista Software Inc. + * Author: jsun@mvista.com or jsun@junsun.net + * + * Copyright 2003 ICT CAS + * Author: Michael Guo + * + * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology + * Author: Fuxin Zhang, zhangfx@lemote.com + * + * Copyright (C) 2009 Lemote Inc. & Insititute of Computing Technology + * Author: Wu Zhangjin, wuzj@lemote.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ +#include +#include + +#include + +int prom_argc; +/* pmon passes arguments in 32bit pointers */ +int *_prom_argv; + +void __init prom_init_cmdline(void) +{ + int i; + long l; + + /* firmware arguments are initialized in head.S */ + prom_argc = fw_arg0; + _prom_argv = (int *)fw_arg1; + + /* arg[0] is "g", the rest is boot parameters */ + arcs_cmdline[0] = '\0'; + for (i = 1; i < prom_argc; i++) { + l = (long)_prom_argv[i]; + if (strlen(arcs_cmdline) + strlen(((char *)l) + 1) + >= sizeof(arcs_cmdline)) + break; + strcat(arcs_cmdline, ((char *)l)); + strcat(arcs_cmdline, " "); + } + + if ((strstr(arcs_cmdline, "console=")) == NULL) + strcat(arcs_cmdline, " console=ttyS0,115200"); + if ((strstr(arcs_cmdline, "root=")) == NULL) + strcat(arcs_cmdline, " root=/dev/hda1"); +} diff --git a/arch/mips/lemote/lm2e/env.c b/arch/mips/lemote/lm2e/env.c new file mode 100644 index 0000000..9e88409 --- /dev/null +++ b/arch/mips/lemote/lm2e/env.c @@ -0,0 +1,60 @@ +/* + * Based on Ocelot Linux port, which is + * Copyright 2001 MontaVista Software Inc. + * Author: jsun@mvista.com or jsun@junsun.net + * + * Copyright 2003 ICT CAS + * Author: Michael Guo + * + * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology + * Author: Fuxin Zhang, zhangfx@lemote.com + * + * Copyright (C) 2009 Lemote Inc. & Insititute of Computing Technology + * Author: Wu Zhangjin, wuzj@lemote.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include +#include + +#include + +unsigned long bus_clock, cpu_clock_freq; +unsigned long memsize, highmemsize; + +/* pmon passes arguments in 32bit pointers */ +int *_prom_envp; + +#define parse_even_earlier(res, option, p) \ +do { \ + if (strncmp(option, (char *)p, strlen(option)) == 0) \ + strict_strtol((char *)p + strlen(option"="), \ + 10, &res); \ +} while (0) + +void __init prom_init_env(void) +{ + long l; + + /* firmware arguments are initialized in head.S */ + _prom_envp = (int *)fw_arg2; + + l = (long)*_prom_envp; + while (l != 0) { + parse_even_earlier(bus_clock, "busclock", l); + parse_even_earlier(cpu_clock_freq, "cpuclock", l); + parse_even_earlier(memsize, "memsize", l); + parse_even_earlier(highmemsize, "highmemsize", l); + _prom_envp++; + l = (long)*_prom_envp; + } + if (memsize == 0) + memsize = 256; + + pr_info("busclock=%ld, cpuclock=%ld, memsize=%ld, highmemsize=%ld\n", + bus_clock, cpu_clock_freq, memsize, highmemsize); +} diff --git a/arch/mips/lemote/lm2e/init.c b/arch/mips/lemote/lm2e/init.c new file mode 100644 index 0000000..6fe624d --- /dev/null +++ b/arch/mips/lemote/lm2e/init.c @@ -0,0 +1,34 @@ +/* + * Copyright (C) 2009 Lemote Inc. & Insititute of Computing Technology + * Author: Wu Zhangjin, wuzj@lemote.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include +#include + +#include +#include + +extern void __init prom_init_cmdline(void); +extern void __init prom_init_env(void); +extern void __init prom_init_memory(void); + +void __init prom_init(void) +{ + /* init base address of io space */ + set_io_port_base((unsigned long) + ioremap(BONITO_PCIIO_BASE, BONITO_PCIIO_SIZE)); + + prom_init_cmdline(); + prom_init_env(); + prom_init_memory(); +} + +void __init prom_free_prom_memory(void) +{ +} diff --git a/arch/mips/lemote/lm2e/machtype.c b/arch/mips/lemote/lm2e/machtype.c new file mode 100644 index 0000000..8d803ee --- /dev/null +++ b/arch/mips/lemote/lm2e/machtype.c @@ -0,0 +1,15 @@ +/* + * Copyright (C) 2009 Lemote Inc. & Insititute of Computing Technology + * Author: Wu Zhangjin, wuzj@lemote.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +const char *get_system_type(void) +{ + return "lemote-fulong"; +} + diff --git a/arch/mips/lemote/lm2e/mem.c b/arch/mips/lemote/lm2e/mem.c index 16cd215..f24af70 100644 --- a/arch/mips/lemote/lm2e/mem.c +++ b/arch/mips/lemote/lm2e/mem.c @@ -8,6 +8,19 @@ #include #include +#include + +extern unsigned long memsize, highmemsize; + +void __init prom_init_memory(void) +{ + add_memory_region(0x0, (memsize << 20), BOOT_MEM_RAM); +#ifdef CONFIG_64BIT + if (highmemsize > 0) + add_memory_region(0x20000000, highmemsize << 20, BOOT_MEM_RAM); +#endif /* CONFIG_64BIT */ +} + /* override of arch/mips/mm/cache.c: __uncached_access */ int __uncached_access(struct file *file, unsigned long addr) { diff --git a/arch/mips/lemote/lm2e/prom.c b/arch/mips/lemote/lm2e/prom.c deleted file mode 100644 index d78cedf..0000000 --- a/arch/mips/lemote/lm2e/prom.c +++ /dev/null @@ -1,91 +0,0 @@ -/* - * Based on Ocelot Linux port, which is - * Copyright 2001 MontaVista Software Inc. - * Author: jsun@mvista.com or jsun@junsun.net - * - * Copyright 2003 ICT CAS - * Author: Michael Guo - * - * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology - * Author: Fuxin Zhang, zhangfx@lemote.com - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ -#include -#include -#include - -extern unsigned long bus_clock; -extern unsigned long cpu_clock_freq; -extern unsigned int memsize, highmemsize; - -static int argc; -/* pmon passes arguments in 32bit pointers */ -static int *arg; -static int *env; - -const char *get_system_type(void) -{ - return "lemote-fulong"; -} - -void __init prom_init_cmdline(void) -{ - int i; - long l; - - /* arg[0] is "g", the rest is boot parameters */ - arcs_cmdline[0] = '\0'; - for (i = 1; i < argc; i++) { - l = (long)arg[i]; - if (strlen(arcs_cmdline) + strlen(((char *)l) + 1) - >= sizeof(arcs_cmdline)) - break; - strcat(arcs_cmdline, ((char *)l)); - strcat(arcs_cmdline, " "); - } -} - -void __init prom_init(void) -{ - long l; - argc = fw_arg0; - arg = (int *)fw_arg1; - env = (int *)fw_arg2; - - prom_init_cmdline(); - - if ((strstr(arcs_cmdline, "console=")) == NULL) - strcat(arcs_cmdline, " console=ttyS0,115200"); - if ((strstr(arcs_cmdline, "root=")) == NULL) - strcat(arcs_cmdline, " root=/dev/hda1"); - -#define parse_even_earlier(res, option, p) \ -do { \ - if (strncmp(option, (char *)p, strlen(option)) == 0) \ - res = simple_strtol((char *)p + strlen(option"="), \ - NULL, 10); \ -} while (0) - - l = (long)*env; - while (l != 0) { - parse_even_earlier(bus_clock, "busclock", l); - parse_even_earlier(cpu_clock_freq, "cpuclock", l); - parse_even_earlier(memsize, "memsize", l); - parse_even_earlier(highmemsize, "highmemsize", l); - env++; - l = (long)*env; - } - if (memsize == 0) - memsize = 256; - - pr_info("busclock=%ld, cpuclock=%ld,memsize=%d,highmemsize=%d\n", - bus_clock, cpu_clock_freq, memsize, highmemsize); -} - -void __init prom_free_prom_memory(void) -{ -} diff --git a/arch/mips/lemote/lm2e/setup.c b/arch/mips/lemote/lm2e/setup.c index ebd6cea..1c4968f 100644 --- a/arch/mips/lemote/lm2e/setup.c +++ b/arch/mips/lemote/lm2e/setup.c @@ -26,15 +26,10 @@ * 675 Mass Ave, Cambridge, MA 02139, USA. * */ -#include #include -#include +#include -#include -#include -#include #include -#include #ifdef CONFIG_VT #include @@ -43,22 +38,6 @@ extern void mips_reboot_setup(void); -unsigned long cpu_clock_freq; -unsigned long bus_clock; -unsigned int memsize; -unsigned int highmemsize = 0; - -void __init plat_time_init(void) -{ - /* setup mips r4k timer */ - mips_hpt_frequency = cpu_clock_freq / 2; -} - -unsigned long read_persistent_clock(void) -{ - return mc146818_get_cmos_time(); -} - void (*__wbflush)(void); EXPORT_SYMBOL(__wbflush); @@ -75,19 +54,10 @@ static void wbflush_loongson2e(void) void __init plat_mem_setup(void) { - set_io_port_base((unsigned long)ioremap(LOONGSON2E_IO_PORT_BASE, - IO_SPACE_LIMIT - LOONGSON2E_PCI_IO_START + 1)); mips_reboot_setup(); __wbflush = wbflush_loongson2e; - add_memory_region(0x0, (memsize << 20), BOOT_MEM_RAM); -#ifdef CONFIG_64BIT - if (highmemsize > 0) { - add_memory_region(0x20000000, highmemsize << 20, BOOT_MEM_RAM); - } -#endif - #ifdef CONFIG_VT #if defined(CONFIG_VGA_CONSOLE) conswitchp = &vga_con; @@ -107,5 +77,4 @@ void __init plat_mem_setup(void) conswitchp = &dummy_con; #endif #endif - } diff --git a/arch/mips/lemote/lm2e/time.c b/arch/mips/lemote/lm2e/time.c new file mode 100644 index 0000000..b9d3f11 --- /dev/null +++ b/arch/mips/lemote/lm2e/time.c @@ -0,0 +1,30 @@ +/* + * Copyright (C) 2007 Lemote, Inc. & Institute of Computing Technology + * Author: Fuxin Zhang, zhangfx@lemote.com + * + * Copyright (C) 2009 Lemote Inc. & Insititute of Computing Technology + * Author: Wu Zhangjin, wuzj@lemote.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include + +#include +#include + +extern unsigned long cpu_clock_freq; + +void __init plat_time_init(void) +{ + /* setup mips r4k timer */ + mips_hpt_frequency = cpu_clock_freq / 2; +} + +unsigned long read_persistent_clock(void) +{ + return mc146818_get_cmos_time(); +} -- 1.6.2.1 From wuzhangjin@gmail.com Thu Jul 2 17:29:04 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 02 Jul 2009 17:29:11 +0200 (CEST) Received: from ey-out-1920.google.com ([74.125.78.145]:56148 "EHLO ey-out-1920.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492206AbZGBP3E (ORCPT ); Thu, 2 Jul 2009 17:29:04 +0200 Received: by ey-out-1920.google.com with SMTP id 13so514356eye.60 for ; Thu, 02 Jul 2009 08:23:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer:in-reply-to:references; bh=DC4cfAdptFUKOnUest0ZIVBWY1k8jRYl0+1uT1REjhA=; b=v1dD1yfjvQYnFNZFoVHXAeSwD3jJ80nvxOiamQVNTBmGXRp29RUgXajarxdWrcJwhJ Xct/pY84U3PtIaDw3Ij+uAzhZs+hF95UpgmPTGCsA7cwN0Gfz+f0DNoCibx7QpWMZRD7 d1pWSO4IPbQxb3HJUMNC5jbazIlJKh0cCSe8Y= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; b=eQ5nLBxap/KarrXnMupb6TIHgJkiDvAV4lVjdAcxGHIwX2DXMhnT3vrZ26aN2FUnzV egDcXLQ+jRAu7k24WJYULLiMckJm2pQVjWbG7rZtJnX/h/Pcs+wP3Ys/DDVEp7Eo2YVM fnlpkE6TMBan2ddFToYMZXYVW69DFwtMtgH9g= Received: by 10.210.20.6 with SMTP id 6mr200225ebt.59.1246548198502; Thu, 02 Jul 2009 08:23:18 -0700 (PDT) Received: from localhost.localdomain ([222.92.8.142]) by mx.google.com with ESMTPS id 23sm13481eya.29.2009.07.02.08.23.10 (version=TLSv1/SSLv3 cipher=RC4-MD5); Thu, 02 Jul 2009 08:23:17 -0700 (PDT) From: Wu Zhangjin To: linux-kernel@vger.kernel.org, linux-mips@linux-mips.org, ralf@linux-mips.org Cc: Wu Zhangjin , Yan Hua , Philippe Vachon , Zhang Le , Zhang Fuxin , loongson-dev , Liu Junliang , Erwan Lerale , Arnaud Patard Subject: [PATCH v4 08/16] [loongson] clean up the coding style Date: Thu, 2 Jul 2009 23:23:03 +0800 Message-Id: <47838a3035e4123de6b19c7de44ec2fc974270cd.1246546684.git.wuzhangjin@gmail.com> X-Mailer: git-send-email 1.6.2.1 In-Reply-To: References: Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23620 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips From: Wu Zhangjin with the help of script/checkpatch.pl, i have cleaned up the coding style. 1. remove un-needed header files and tune some comments. 2. remove some un-needed { } add a new header file loongson.h: 3. move some common header files to loongson.h 4. move some common extern declartions to loongson.h and this new header file is needed for future loongson2f support. Signed-off-by: Wu Zhangjin --- arch/mips/include/asm/mach-lemote/loongson.h | 36 +++++++++++++++++++ arch/mips/include/asm/mach-lemote/pci.h | 8 +++-- arch/mips/lemote/lm2e/bonito-irq.c | 27 +------------- arch/mips/lemote/lm2e/cmdline.c | 5 +-- arch/mips/lemote/lm2e/early_printk.c | 4 +-- arch/mips/lemote/lm2e/env.c | 6 +-- arch/mips/lemote/lm2e/init.c | 6 +--- arch/mips/lemote/lm2e/irq.c | 48 ++++---------------------- arch/mips/lemote/lm2e/mem.c | 2 +- arch/mips/lemote/lm2e/pci.c | 26 +------------- arch/mips/lemote/lm2e/reset.c | 7 ++-- arch/mips/lemote/lm2e/setup.c | 24 +------------ arch/mips/lemote/lm2e/time.c | 5 +-- arch/mips/pci/fixup-lm2e.c | 18 ---------- 14 files changed, 66 insertions(+), 156 deletions(-) create mode 100644 arch/mips/include/asm/mach-lemote/loongson.h diff --git a/arch/mips/include/asm/mach-lemote/loongson.h b/arch/mips/include/asm/mach-lemote/loongson.h new file mode 100644 index 0000000..76cc2bd --- /dev/null +++ b/arch/mips/include/asm/mach-lemote/loongson.h @@ -0,0 +1,36 @@ +/* + * Copyright (C) 2009 Lemote, Inc. & Institute of Computing Technology + * Author: Wu Zhangjin + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + */ + +#ifndef __ASM_MACH_LOONGSON_LOONGSON_H +#define __ASM_MACH_LOONGSON_LOONGSON_H + +#include +#include + +/* there is an internal bonito64-compatiable northbridge in loongson2e/2f */ +#include + +/* loongson internal northbridge initialization */ +extern void bonito_irq_init(void); + +/* loongson-based machines specific reboot setup */ +extern void mips_reboot_setup(void); + +/* environment arguments from bootloader */ +extern unsigned long bus_clock, cpu_clock_freq; +extern unsigned long memsize, highmemsize; + +/* loongson-specific command line, env and memory initialization */ +extern void __init prom_init_memory(void); +extern void __init prom_init_cmdline(void); +extern void __init prom_init_env(void); + +#endif /* __ASM_MACH_LOONGSON_LOONGSON_H */ diff --git a/arch/mips/include/asm/mach-lemote/pci.h b/arch/mips/include/asm/mach-lemote/pci.h index 0307e49..92b2f59 100644 --- a/arch/mips/include/asm/mach-lemote/pci.h +++ b/arch/mips/include/asm/mach-lemote/pci.h @@ -19,11 +19,13 @@ * 02139, USA. */ -#ifndef _LEMOTE_PCI_H_ -#define _LEMOTE_PCI_H_ +#ifndef __ASM_MACH_LEMOTE_PCI_H_ +#define __ASM_MACH_LEMOTE_PCI_H_ + +extern struct pci_ops bonito64_pci_ops; #define LOONGSON2E_PCI_MEM_START 0x14000000UL #define LOONGSON2E_PCI_MEM_END 0x1fffffffUL #define LOONGSON2E_PCI_IO_START 0x00004000UL -#endif /* !_LEMOTE_PCI_H_ */ +#endif /* !__ASM_MACH_LEMOTE_PCI_H_ */ diff --git a/arch/mips/lemote/lm2e/bonito-irq.c b/arch/mips/lemote/lm2e/bonito-irq.c index 8fc3bce..3e31e7a 100644 --- a/arch/mips/lemote/lm2e/bonito-irq.c +++ b/arch/mips/lemote/lm2e/bonito-irq.c @@ -10,32 +10,10 @@ * under the terms of the GNU General Public License as published by the * Free Software Foundation; either version 2 of the License, or (at your * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - * */ -#include -#include -#include -#include #include -#include - -#include +#include static inline void bonito_irq_enable(unsigned int irq) { @@ -66,9 +44,8 @@ void bonito_irq_init(void) { u32 i; - for (i = BONITO_IRQ_BASE; i < BONITO_IRQ_BASE + 32; i++) { + for (i = BONITO_IRQ_BASE; i < BONITO_IRQ_BASE + 32; i++) set_irq_chip_and_handler(i, &bonito_irq_type, handle_level_irq); - } setup_irq(BONITO_IRQ_BASE + 10, &dma_timeout_irqaction); } diff --git a/arch/mips/lemote/lm2e/cmdline.c b/arch/mips/lemote/lm2e/cmdline.c index 442b935..75f1b24 100644 --- a/arch/mips/lemote/lm2e/cmdline.c +++ b/arch/mips/lemote/lm2e/cmdline.c @@ -17,11 +17,10 @@ * Free Software Foundation; either version 2 of the License, or (at your * option) any later version. */ -#include -#include - #include +#include + int prom_argc; /* pmon passes arguments in 32bit pointers */ int *_prom_argv; diff --git a/arch/mips/lemote/lm2e/early_printk.c b/arch/mips/lemote/lm2e/early_printk.c index 811c7de..3e0a6ea 100644 --- a/arch/mips/lemote/lm2e/early_printk.c +++ b/arch/mips/lemote/lm2e/early_printk.c @@ -9,11 +9,9 @@ * Free Software Foundation; either version 2 of the License, or (at your * option) any later version. */ -#include -#include #include -#include +#include #define UART_BASE (BONITO_PCIIO_BASE + 0x3f8) diff --git a/arch/mips/lemote/lm2e/env.c b/arch/mips/lemote/lm2e/env.c index 9e88409..b9ef503 100644 --- a/arch/mips/lemote/lm2e/env.c +++ b/arch/mips/lemote/lm2e/env.c @@ -17,12 +17,10 @@ * Free Software Foundation; either version 2 of the License, or (at your * option) any later version. */ - -#include -#include - #include +#include + unsigned long bus_clock, cpu_clock_freq; unsigned long memsize, highmemsize; diff --git a/arch/mips/lemote/lm2e/init.c b/arch/mips/lemote/lm2e/init.c index 6fe624d..3abe927 100644 --- a/arch/mips/lemote/lm2e/init.c +++ b/arch/mips/lemote/lm2e/init.c @@ -8,15 +8,11 @@ * option) any later version. */ -#include #include #include -#include -extern void __init prom_init_cmdline(void); -extern void __init prom_init_env(void); -extern void __init prom_init_memory(void); +#include void __init prom_init(void) { diff --git a/arch/mips/lemote/lm2e/irq.c b/arch/mips/lemote/lm2e/irq.c index 1d0a09f..fb7643a 100644 --- a/arch/mips/lemote/lm2e/irq.c +++ b/arch/mips/lemote/lm2e/irq.c @@ -6,35 +6,14 @@ * under the terms of the GNU General Public License as published by the * Free Software Foundation; either version 2 of the License, or (at your * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - * */ #include -#include -#include #include -#include #include #include -#include -#include - +#include /* * the first level int-handler will jump here if it is a bonito irq */ @@ -67,27 +46,24 @@ static void i8259_irqdispatch(void) int irq; irq = i8259_irq(); - if (irq >= 0) { + if (irq >= 0) do_IRQ(irq); - } else { + else spurious_interrupt(); - } - } asmlinkage void plat_irq_dispatch(void) { unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM; - if (pending & CAUSEF_IP7) { + if (pending & CAUSEF_IP7) do_IRQ(MIPS_CPU_IRQ_BASE + 7); - } else if (pending & CAUSEF_IP5) { + else if (pending & CAUSEF_IP5) i8259_irqdispatch(); - } else if (pending & CAUSEF_IP2) { + else if (pending & CAUSEF_IP2) bonito_irqdispatch(); - } else { + else spurious_interrupt(); - } } static struct irqaction cascade_irqaction = { @@ -97,8 +73,6 @@ static struct irqaction cascade_irqaction = { void __init arch_init_irq(void) { - extern void bonito_irq_init(void); - /* * Clear all of the interrupts while we change the able around a bit. * int-handler is not on bootstrap @@ -128,16 +102,8 @@ void __init arch_init_irq(void) init_i8259_irqs(); bonito_irq_init(); - /* - printk("GPIODATA=%x, GPIOIE=%x\n", BONITO_GPIODATA, BONITO_GPIOIE); - printk("INTEN=%x, INTSET=%x, INTCLR=%x, INTISR=%x\n", - BONITO_INTEN, BONITO_INTENSET, - BONITO_INTENCLR, BONITO_INTISR); - */ - /* bonito irq at IP2 */ setup_irq(MIPS_CPU_IRQ_BASE + 2, &cascade_irqaction); /* 8259 irq at IP5 */ setup_irq(MIPS_CPU_IRQ_BASE + 5, &cascade_irqaction); - } diff --git a/arch/mips/lemote/lm2e/mem.c b/arch/mips/lemote/lm2e/mem.c index f24af70..6a7feb1 100644 --- a/arch/mips/lemote/lm2e/mem.c +++ b/arch/mips/lemote/lm2e/mem.c @@ -10,7 +10,7 @@ #include -extern unsigned long memsize, highmemsize; +#include void __init prom_init_memory(void) { diff --git a/arch/mips/lemote/lm2e/pci.c b/arch/mips/lemote/lm2e/pci.c index 152efb6..bee846e 100644 --- a/arch/mips/lemote/lm2e/pci.c +++ b/arch/mips/lemote/lm2e/pci.c @@ -1,6 +1,4 @@ /* - * pci.c - * * Copyright (C) 2007 Lemote, Inc. & Institute of Computing Technology * Author: Fuxin Zhang, zhangfx@lemote.com * @@ -8,31 +6,11 @@ * under the terms of the GNU General Public License as published by the * Free Software Foundation; either version 2 of the License, or (at your * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - * */ -#include #include -#include -#include -#include -#include -extern struct pci_ops bonito64_pci_ops; +#include +#include static struct resource loongson2e_pci_mem_resource = { .name = "LOONGSON2E PCI MEM", diff --git a/arch/mips/lemote/lm2e/reset.c b/arch/mips/lemote/lm2e/reset.c index 7758093..d89c9e4 100644 --- a/arch/mips/lemote/lm2e/reset.c +++ b/arch/mips/lemote/lm2e/reset.c @@ -10,10 +10,10 @@ * Author: Zhangjin Wu, wuzj@lemote.com */ #include -#include #include -#include + +#include static void loongson2e_restart(char *command) { @@ -27,7 +27,8 @@ static void loongson2e_restart(char *command) static void loongson2e_halt(void) { - while (1) ; + while (1) + ; } void mips_reboot_setup(void) diff --git a/arch/mips/lemote/lm2e/setup.c b/arch/mips/lemote/lm2e/setup.c index 1c4968f..655695c 100644 --- a/arch/mips/lemote/lm2e/setup.c +++ b/arch/mips/lemote/lm2e/setup.c @@ -1,7 +1,4 @@ /* - * BRIEF MODULE DESCRIPTION - * setup.c - board dependent boot routines - * * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology * Author: Fuxin Zhang, zhangfx@lemote.com * @@ -9,35 +6,18 @@ * under the terms of the GNU General Public License as published by the * Free Software Foundation; either version 2 of the License, or (at your * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - * */ -#include #include #include +#include + #ifdef CONFIG_VT #include #include #endif -extern void mips_reboot_setup(void); - void (*__wbflush)(void); EXPORT_SYMBOL(__wbflush); diff --git a/arch/mips/lemote/lm2e/time.c b/arch/mips/lemote/lm2e/time.c index b9d3f11..b13d171 100644 --- a/arch/mips/lemote/lm2e/time.c +++ b/arch/mips/lemote/lm2e/time.c @@ -10,13 +10,10 @@ * Free Software Foundation; either version 2 of the License, or (at your * option) any later version. */ - -#include - #include #include -extern unsigned long cpu_clock_freq; +#include void __init plat_time_init(void) { diff --git a/arch/mips/pci/fixup-lm2e.c b/arch/mips/pci/fixup-lm2e.c index e18ae4f..0c4c7a8 100644 --- a/arch/mips/pci/fixup-lm2e.c +++ b/arch/mips/pci/fixup-lm2e.c @@ -1,6 +1,4 @@ /* - * fixup-lm2e.c - * * Copyright (C) 2004 ICT CAS * Author: Li xiaoyu, ICT CAS * lixy@ict.ac.cn @@ -12,22 +10,6 @@ * under the terms of the GNU General Public License as published by the * Free Software Foundation; either version 2 of the License, or (at your * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - * */ #include #include -- 1.6.2.1 From wuzhangjin@gmail.com Thu Jul 2 17:29:36 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 02 Jul 2009 17:29:42 +0200 (CEST) Received: from mail-ew0-f214.google.com ([209.85.219.214]:60930 "EHLO mail-ew0-f214.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492206AbZGBP3g (ORCPT ); Thu, 2 Jul 2009 17:29:36 +0200 Received: by ewy10 with SMTP id 10so2098091ewy.0 for ; Thu, 02 Jul 2009 08:23:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer:in-reply-to:references; bh=PaOFrDF+hSYpdCa9winuGKDZUv8V7cg2vynUNIbQNuA=; b=ZHJ1v/epQm4k+Qz3rsRTsIMDK+FlAnACUhiKgusl1jvKjwn4x21EJa2wbiGlw+l0UZ mPII7dvBKHW/wDANG/LurmNPWCv5ut4KShw5dVkdsTVpmwgPk8+KDjwZWRZ2sDqxccW2 Bjt0fik/j7rbcoYgi6Kao2ttlkgYIp4AMIZwA= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; b=dDQ7iRCOUbqabPjTroFvtXFzACNl0h03RLVAGMxe7BVuatO3HYjCjArtbNATaVc40J 7wKkMLtm6phbbg4azsByyb0y5amnmKoDSov+/4MssIq3zWUBK3S3QxTVT5hCm+kltHDH WqjsLMA2w+hUM4WtNT4cyFQMQh2NlUprTP2bw= Received: by 10.210.110.5 with SMTP id i5mr1081965ebc.80.1246548225491; Thu, 02 Jul 2009 08:23:45 -0700 (PDT) Received: from localhost.localdomain ([222.92.8.142]) by mx.google.com with ESMTPS id 28sm5323930eyg.14.2009.07.02.08.23.38 (version=TLSv1/SSLv3 cipher=RC4-MD5); Thu, 02 Jul 2009 08:23:44 -0700 (PDT) From: Wu Zhangjin To: linux-kernel@vger.kernel.org, linux-mips@linux-mips.org, ralf@linux-mips.org Cc: Wu Zhangjin , Yan Hua , Philippe Vachon , Zhang Le , Zhang Fuxin , loongson-dev , Liu Junliang , Erwan Lerale , Arnaud Patard Subject: [PATCH v4 09/16] [loongson] pci: clean up pcimap setup Date: Thu, 2 Jul 2009 23:23:30 +0800 Message-Id: <6a16acdd7c6617798d87b064dedbbca26f69a153.1246546684.git.wuzhangjin@gmail.com> X-Mailer: git-send-email 1.6.2.1 In-Reply-To: References: Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23621 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips fixup the wrong original comment of pcimap, and make the source code more understandable. and also, some new extra consideration is added in. Signed-off-by: Wu Zhangjin --- arch/mips/include/asm/mach-lemote/loongson.h | 17 +++++++++++ arch/mips/include/asm/mach-lemote/pci.h | 4 +- arch/mips/lemote/lm2e/pci.c | 41 ++++++++++++++++--------- 3 files changed, 45 insertions(+), 17 deletions(-) diff --git a/arch/mips/include/asm/mach-lemote/loongson.h b/arch/mips/include/asm/mach-lemote/loongson.h index 76cc2bd..916eace 100644 --- a/arch/mips/include/asm/mach-lemote/loongson.h +++ b/arch/mips/include/asm/mach-lemote/loongson.h @@ -33,4 +33,21 @@ extern void __init prom_init_memory(void); extern void __init prom_init_cmdline(void); extern void __init prom_init_env(void); +/* PCI Configuration Registers */ +#define LOONGSON_PCI_ISR4C BONITO_PCI_REG(0x4c) + +/* PCI_Hit*_Sel_* */ + +#define LOONGSON_PCI_HIT0_SEL_L BONITO(BONITO_REGBASE + 0x50) +#define LOONGSON_PCI_HIT0_SEL_H BONITO(BONITO_REGBASE + 0x54) +#define LOONGSON_PCI_HIT1_SEL_L BONITO(BONITO_REGBASE + 0x58) +#define LOONGSON_PCI_HIT1_SEL_H BONITO(BONITO_REGBASE + 0x5c) +#define LOONGSON_PCI_HIT2_SEL_L BONITO(BONITO_REGBASE + 0x60) +#define LOONGSON_PCI_HIT2_SEL_H BONITO(BONITO_REGBASE + 0x64) + +/* PXArb Config & Status */ + +#define LOONGSON_PXARB_CFG BONITO(BONITO_REGBASE + 0x68) +#define LOONGSON_PXARB_STATUS BONITO(BONITO_REGBASE + 0x6c) + #endif /* __ASM_MACH_LOONGSON_LOONGSON_H */ diff --git a/arch/mips/include/asm/mach-lemote/pci.h b/arch/mips/include/asm/mach-lemote/pci.h index 92b2f59..3e6b130 100644 --- a/arch/mips/include/asm/mach-lemote/pci.h +++ b/arch/mips/include/asm/mach-lemote/pci.h @@ -24,8 +24,8 @@ extern struct pci_ops bonito64_pci_ops; -#define LOONGSON2E_PCI_MEM_START 0x14000000UL -#define LOONGSON2E_PCI_MEM_END 0x1fffffffUL +#define LOONGSON2E_PCI_MEM_START BONITO_PCILO1_BASE +#define LOONGSON2E_PCI_MEM_END (BONITO_PCILO1_BASE + 0x04000000 * 2) #define LOONGSON2E_PCI_IO_START 0x00004000UL #endif /* !__ASM_MACH_LEMOTE_PCI_H_ */ diff --git a/arch/mips/lemote/lm2e/pci.c b/arch/mips/lemote/lm2e/pci.c index bee846e..9812c30 100644 --- a/arch/mips/lemote/lm2e/pci.c +++ b/arch/mips/lemote/lm2e/pci.c @@ -34,33 +34,44 @@ static struct pci_controller loongson2e_pci_controller = { .io_offset = 0x00000000UL, }; -static void __init ict_pcimap(void) +static void __init setup_pcimap(void) { /* - * local to PCI mapping: [256M,512M] -> [256M,512M]; differ from PMON - * + * local to PCI mapping for CPU accessing PCI space * CPU address space [256M,448M] is window for accessing pci space - * we set pcimap_lo[0,1,2] to map it to pci space [256M,448M] - * pcimap: bit18,pcimap_2; bit[17-12],lo2;bit[11-6],lo1;bit[5-0],lo0 + * we set pcimap_lo[0,1,2] to map it to pci space[0M,64M], [320M,448M] + * + * pcimap: PCI_MAP2 PCI_Mem_Lo2 PCI_Mem_Lo1 PCI_Mem_Lo0 + * [<2G] [384M,448M] [320M,384M] [0M,64M] */ - /* 1,00 0110 ,0001 01,00 0000 */ - BONITO_PCIMAP = 0x46140; - - /* 1, 00 0010, 0000,01, 00 0000 */ - /* BONITO_PCIMAP = 0x42040; */ + BONITO_PCIMAP = BONITO_PCIMAP_PCIMAP_2 | + BONITO_PCIMAP_WIN(2, BONITO_PCILO2_BASE) | + BONITO_PCIMAP_WIN(1, BONITO_PCILO1_BASE) | + BONITO_PCIMAP_WIN(0, 0); /* - * PCI to local mapping: [2G,2G+256M] -> [0,256M] + * PCI-DMA to local mapping: [2G,2G+256M] -> [0M,256M] */ - BONITO_PCIBASE0 = 0x80000000; - BONITO_PCIBASE1 = 0x00800000; - BONITO_PCIBASE2 = 0x90000000; + BONITO_PCIBASE0 = 0x80000000ul; /* base: 2G -> mmap: 0M */ + /* size: 256M, burst transmission, pre-fetch enable, 64bit */ + LOONGSON_PCI_HIT0_SEL_L = 0xc000000cul; + LOONGSON_PCI_HIT0_SEL_H = 0xfffffffful; + LOONGSON_PCI_HIT1_SEL_L = 0x00000006ul; /* set this BAR as invalid */ + LOONGSON_PCI_HIT1_SEL_H = 0x00000000ul; + LOONGSON_PCI_HIT2_SEL_L = 0x00000006ul; /* set this BAR as invalid */ + LOONGSON_PCI_HIT2_SEL_H = 0x00000000ul; + + /* avoid deadlock of PCI reading/writing lock operation */ + LOONGSON_PCI_ISR4C = 0xd2000001ul; + /* can not change gnt to break pci transfer when device's gnt not + deassert for some broken device */ + LOONGSON_PXARB_CFG = 0x00fe0105ul; } static int __init pcibios_init(void) { - ict_pcimap(); + setup_pcimap(); loongson2e_pci_controller.io_map_base = mips_io_port_base; -- 1.6.2.1 From wuzhangjin@gmail.com Thu Jul 2 17:30:01 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 02 Jul 2009 17:30:09 +0200 (CEST) Received: from ey-out-1920.google.com ([74.125.78.148]:30431 "EHLO ey-out-1920.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492211AbZGBPaB (ORCPT ); Thu, 2 Jul 2009 17:30:01 +0200 Received: by ey-out-1920.google.com with SMTP id 13so514585eye.60 for ; Thu, 02 Jul 2009 08:24:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer:in-reply-to:references; bh=4ZiNyqmByEwQyQEPN6TXIr0jo/9Tal2W4AVO8hGPkGE=; b=f5HW2VFlfSVJGMz5L272+vMPtSrqViiPDnKO/F/5d2YmicXHBavwygOZMxbCzV3dm2 7qzPy41a0o/ClN5OSPUA3kACCJWkPKw5Ul4jW3eY6znEvBzWIxHWDIvpUpU3hZ3S+9KD LHlc3uUp4esPNOjRry/G16O9No+PQUJUeo8ss= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; b=mg9CkSVZeZbk3A91MmHVYnKE+dKpwHv610CUUn7Ae5fJ91dfjCDINjWjzVrd//gVhI Ala8di2X4diqGQFnMoTNi+QulEMvtcs6tSTIi0D76WUZPDUOB+PQfs0Vbh1yKbirO3ky Z2XsCO/PKTiez7pb51Z7sIRqD8zSnZxDwk5G4= Received: by 10.210.34.2 with SMTP id h2mr207280ebh.56.1246548255511; Thu, 02 Jul 2009 08:24:15 -0700 (PDT) Received: from localhost.localdomain ([222.92.8.142]) by mx.google.com with ESMTPS id 10sm2984694eyd.38.2009.07.02.08.24.08 (version=TLSv1/SSLv3 cipher=RC4-MD5); Thu, 02 Jul 2009 08:24:14 -0700 (PDT) From: Wu Zhangjin To: linux-kernel@vger.kernel.org, linux-mips@linux-mips.org, ralf@linux-mips.org Cc: Wu Zhangjin , Yan Hua , Philippe Vachon , Zhang Le , Zhang Fuxin , loongson-dev , Liu Junliang , Erwan Lerale , Arnaud Patard Subject: [PATCH v4 10/16] [loongson] rtc: enable legacy RTC driver on fulong Date: Thu, 2 Jul 2009 23:24:01 +0800 Message-Id: X-Mailer: git-send-email 1.6.2.1 In-Reply-To: References: Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23622 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips From: Wu Zhangjin RTC_LIB is selected by MIPS by default, and therefore, the legacy RTC driver is disabled. but fortunately, RTC_LIB not works on fulong, so, enabling the legcy RTC driver is needed, otherwise, the tools like hwclock will not work. Signed-off-by: Wu Zhangjin --- arch/mips/Kconfig | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 3ca0fe1..a383dac 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -6,7 +6,7 @@ config MIPS select HAVE_ARCH_KGDB # Horrible source of confusion. Die, die, die ... select EMBEDDED - select RTC_LIB + select RTC_LIB if !LEMOTE_FULONG mainmenu "Linux/MIPS Kernel Configuration" -- 1.6.2.1 From wuzhangjin@gmail.com Thu Jul 2 17:31:52 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 02 Jul 2009 17:31:58 +0200 (CEST) Received: from mail-ew0-f214.google.com ([209.85.219.214]:41321 "EHLO mail-ew0-f214.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492210AbZGBPbv (ORCPT ); Thu, 2 Jul 2009 17:31:51 +0200 Received: by ewy10 with SMTP id 10so2100419ewy.0 for ; Thu, 02 Jul 2009 08:26:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer:in-reply-to:references; bh=82Vjboxlt5L08nKoBwwkBMBpSO4kDdAjpXBk/EQ2+1U=; b=mBlqTKspdkhrQJdJQ1G+Aq+dkmKul8UVCUuR8PmqEWQbBoxIOmEkVBCoOMglLIY+Ih eJw5D8Rj/tHGB2sKFYWbLOWM4RBA1YhdpZZCFjCm9uOpDqdpGBs17fUNoDA9gDRjdK74 4PBoIm6OlUWCuytc6sZSb7ULVTmu56uQ996fw= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; b=BaRsmrpxrhZT88l7wfj278nx9dVD3L+Fdafd9/eUTAPqz5OHEwbGaqAwaGvUtBvc+6 HAm7xLMQjQyyxlbLxeqLWsCySx/ag7ioB8mFuDskp7ME7u61uWZmTO6o0dqOkHNk589L 5MBClYnCHj1EtFY4YIjkF9BWGqGHLyb/Rvl6U= Received: by 10.210.53.5 with SMTP id b5mr1113201eba.41.1246548361224; Thu, 02 Jul 2009 08:26:01 -0700 (PDT) Received: from localhost.localdomain ([222.92.8.142]) by mx.google.com with ESMTPS id 28sm2370274eyg.4.2009.07.02.08.25.52 (version=TLSv1/SSLv3 cipher=RC4-MD5); Thu, 02 Jul 2009 08:25:59 -0700 (PDT) From: Wu Zhangjin To: linux-kernel@vger.kernel.org, linux-mips@linux-mips.org, ralf@linux-mips.org Cc: Wu Zhangjin , Yan Hua , Philippe Vachon , Zhang Le , Zhang Fuxin , loongson-dev , Liu Junliang , Erwan Lerale , Arnaud Patard Subject: [PATCH v4 11/16] [loongson] add oprofile support Date: Thu, 2 Jul 2009 23:25:46 +0800 Message-Id: X-Mailer: git-send-email 1.6.2.1 In-Reply-To: References: Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23623 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips From: Wu Zhangjin this kernel support is needed by the user-space tool:oprofile to profile linux kernel or applications via loongson2 performance counters. you can enable this driver via CONFIG_OPROFILE = y or m. In loongson2, there are two performance counters, each one can count 16 events respectively. when anyone of the performance counter overflows, an interrupt will generate and goes to the interrupt line: MIPS_CPU_IRQ_BASE + 6 Signed-off-by: Yanhua Signed-off-by: Wu Zhangjin --- arch/mips/include/asm/mach-lemote/loongson.h | 3 + arch/mips/lemote/lm2e/irq.c | 2 + arch/mips/oprofile/Makefile | 1 + arch/mips/oprofile/common.c | 4 + arch/mips/oprofile/op_model_loongson2.c | 177 ++++++++++++++++++++++++++ 5 files changed, 187 insertions(+), 0 deletions(-) create mode 100644 arch/mips/oprofile/op_model_loongson2.c diff --git a/arch/mips/include/asm/mach-lemote/loongson.h b/arch/mips/include/asm/mach-lemote/loongson.h index 916eace..95ee4c8 100644 --- a/arch/mips/include/asm/mach-lemote/loongson.h +++ b/arch/mips/include/asm/mach-lemote/loongson.h @@ -50,4 +50,7 @@ extern void __init prom_init_env(void); #define LOONGSON_PXARB_CFG BONITO(BONITO_REGBASE + 0x68) #define LOONGSON_PXARB_STATUS BONITO(BONITO_REGBASE + 0x6c) +/* loongson2-specific perf counter IRQ */ +#define LOONGSON2_PERFCNT_IRQ (MIPS_CPU_IRQ_BASE + 6) + #endif /* __ASM_MACH_LOONGSON_LOONGSON_H */ diff --git a/arch/mips/lemote/lm2e/irq.c b/arch/mips/lemote/lm2e/irq.c index fb7643a..9585f5a 100644 --- a/arch/mips/lemote/lm2e/irq.c +++ b/arch/mips/lemote/lm2e/irq.c @@ -58,6 +58,8 @@ asmlinkage void plat_irq_dispatch(void) if (pending & CAUSEF_IP7) do_IRQ(MIPS_CPU_IRQ_BASE + 7); + else if (pending & CAUSEF_IP6) /* perf counter loverflow */ + do_IRQ(LOONGSON2_PERFCNT_IRQ); else if (pending & CAUSEF_IP5) i8259_irqdispatch(); else if (pending & CAUSEF_IP2) diff --git a/arch/mips/oprofile/Makefile b/arch/mips/oprofile/Makefile index bf3be6f..02cc65e 100644 --- a/arch/mips/oprofile/Makefile +++ b/arch/mips/oprofile/Makefile @@ -15,3 +15,4 @@ oprofile-$(CONFIG_CPU_MIPS64) += op_model_mipsxx.o oprofile-$(CONFIG_CPU_R10000) += op_model_mipsxx.o oprofile-$(CONFIG_CPU_SB1) += op_model_mipsxx.o oprofile-$(CONFIG_CPU_RM9000) += op_model_rm9000.o +oprofile-$(CONFIG_CPU_LOONGSON2) += op_model_loongson2.o diff --git a/arch/mips/oprofile/common.c b/arch/mips/oprofile/common.c index 3bf3354..7832ad2 100644 --- a/arch/mips/oprofile/common.c +++ b/arch/mips/oprofile/common.c @@ -16,6 +16,7 @@ extern struct op_mips_model op_model_mipsxx_ops __attribute__((weak)); extern struct op_mips_model op_model_rm9000_ops __attribute__((weak)); +extern struct op_mips_model op_model_loongson2_ops __attribute__((weak)); static struct op_mips_model *model; @@ -93,6 +94,9 @@ int __init oprofile_arch_init(struct oprofile_operations *ops) case CPU_RM9000: lmodel = &op_model_rm9000_ops; break; + case CPU_LOONGSON2: + lmodel = &op_model_loongson2_ops; + break; }; if (!lmodel) diff --git a/arch/mips/oprofile/op_model_loongson2.c b/arch/mips/oprofile/op_model_loongson2.c new file mode 100644 index 0000000..655cb8d --- /dev/null +++ b/arch/mips/oprofile/op_model_loongson2.c @@ -0,0 +1,177 @@ +/* + * Loongson2 performance counter driver for oprofile + * + * Copyright (C) 2009 Lemote Inc. & Insititute of Computing Technology + * Author: Yanhua + * Author: Wu Zhangjin + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + */ +#include +#include +#include + +#include /* LOONGSON2_PERFCNT_IRQ */ +#include "op_impl.h" + +/* + * a patch should be sent to oprofile with the loongson-specific support. + * otherwise, the oprofile tool will not recognize this and complain about + * "cpu_type 'unset' is not valid". + */ +#define LOONGSON2_CPU_TYPE "mips/godson2" + +#define LOONGSON2_COUNTER1_EVENT(event) ((event & 0x0f) << 5) +#define LOONGSON2_COUNTER2_EVENT(event) ((event & 0x0f) << 9) + +#define LOONGSON2_PERFCNT_EXL (1UL << 0) +#define LOONGSON2_PERFCNT_KERNEL (1UL << 1) +#define LOONGSON2_PERFCNT_SUPERVISOR (1UL << 2) +#define LOONGSON2_PERFCNT_USER (1UL << 3) +#define LOONGSON2_PERFCNT_INT_EN (1UL << 4) +#define LOONGSON2_PERFCNT_OVERFLOW (1ULL << 31) + +/* Loongson2 performance counter register */ +#define read_c0_perfctrl() __read_64bit_c0_register($24, 0) +#define write_c0_perfctrl(val) __write_64bit_c0_register($24, 0, val) +#define read_c0_perfcnt() __read_64bit_c0_register($25, 0) +#define write_c0_perfcnt(val) __write_64bit_c0_register($25, 0, val) + +static struct loongson2_register_config { + unsigned int ctrl; + unsigned long long reset_counter1; + unsigned long long reset_counter2; + int cnt1_enalbed, cnt2_enalbed; +} reg; + +DEFINE_SPINLOCK(sample_lock); + +static char *oprofid = "LoongsonPerf"; +static irqreturn_t loongson2_perfcount_handler(int irq, void *dev_id); +/* Compute all of the registers in preparation for enabling profiling. */ + +static void loongson2_reg_setup(struct op_counter_config *cfg) +{ + unsigned int ctrl = 0; + + reg.reset_counter1 = 0; + reg.reset_counter2 = 0; + /* Compute the performance counter ctrl word. */ + /* For now count kernel and user mode */ + if (cfg[0].enabled) { + ctrl |= LOONGSON2_COUNTER1_EVENT(cfg[0].event); + reg.reset_counter1 = 0x80000000ULL - cfg[0].count; + } + + if (cfg[1].enabled) { + ctrl |= LOONGSON2_COUNTER2_EVENT(cfg[1].event); + reg.reset_counter2 = (0x80000000ULL - cfg[1].count); + } + + if (cfg[0].enabled || cfg[1].enabled) { + ctrl |= LOONGSON2_PERFCNT_EXL | LOONGSON2_PERFCNT_INT_EN; + if (cfg[0].kernel || cfg[1].kernel) + ctrl |= LOONGSON2_PERFCNT_KERNEL; + if (cfg[0].user || cfg[1].user) + ctrl |= LOONGSON2_PERFCNT_USER; + } + + reg.ctrl = ctrl; + + reg.cnt1_enalbed = cfg[0].enabled; + reg.cnt2_enalbed = cfg[1].enabled; + +} + +/* Program all of the registers in preparation for enabling profiling. */ + +static void loongson2_cpu_setup(void *args) +{ + uint64_t perfcount; + + perfcount = (reg.reset_counter2 << 32) | reg.reset_counter1; + write_c0_perfcnt(perfcount); +} + +static void loongson2_cpu_start(void *args) +{ + /* Start all counters on current CPU */ + if (reg.cnt1_enalbed || reg.cnt2_enalbed) + write_c0_perfctrl(reg.ctrl); +} + +static void loongson2_cpu_stop(void *args) +{ + /* Stop all counters on current CPU */ + write_c0_perfctrl(0); + memset(®, 0, sizeof(reg)); +} + +static irqreturn_t loongson2_perfcount_handler(int irq, void *dev_id) +{ + uint64_t counter, counter1, counter2; + struct pt_regs *regs = get_irq_regs(); + int enabled; + unsigned long flags; + + /* + * LOONGSON2 defines two 32-bit performance counters. + * To avoid a race updating the registers we need to stop the counters + * while we're messing with + * them ... + */ + + /* Check whether the irq belongs to me */ + enabled = reg.cnt1_enalbed | reg.cnt2_enalbed; + if (!enabled) + return IRQ_NONE; + + counter = read_c0_perfcnt(); + counter1 = counter & 0xffffffff; + counter2 = counter >> 32; + + spin_lock_irqsave(&sample_lock, flags); + + if (counter1 & LOONGSON2_PERFCNT_OVERFLOW) { + if (reg.cnt1_enalbed) + oprofile_add_sample(regs, 0); + counter1 = reg.reset_counter1; + } + if (counter2 & LOONGSON2_PERFCNT_OVERFLOW) { + if (reg.cnt2_enalbed) + oprofile_add_sample(regs, 1); + counter2 = reg.reset_counter2; + } + + spin_unlock_irqrestore(&sample_lock, flags); + + write_c0_perfcnt((counter2 << 32) | counter1); + + return IRQ_HANDLED; +} + +static int __init loongson2_init(void) +{ + return request_irq(LOONGSON2_PERFCNT_IRQ, loongson2_perfcount_handler, + IRQF_SHARED, "Perfcounter", oprofid); +} + +static void loongson2_exit(void) +{ + write_c0_perfctrl(0); + free_irq(LOONGSON2_PERFCNT_IRQ, oprofid); +} + +struct op_mips_model op_model_loongson2_ops = { + .reg_setup = loongson2_reg_setup, + .cpu_setup = loongson2_cpu_setup, + .init = loongson2_init, + .exit = loongson2_exit, + .cpu_start = loongson2_cpu_start, + .cpu_stop = loongson2_cpu_stop, + .cpu_type = LOONGSON2_CPU_TYPE, + .num_counters = 2 +}; -- 1.6.2.1 From wuzhangjin@gmail.com Thu Jul 2 17:32:15 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 02 Jul 2009 17:32:23 +0200 (CEST) Received: from mail-ew0-f214.google.com ([209.85.219.214]:41321 "EHLO mail-ew0-f214.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492206AbZGBPcJ (ORCPT ); Thu, 2 Jul 2009 17:32:09 +0200 Received: by mail-ew0-f214.google.com with SMTP id 10so2100419ewy.0 for ; Thu, 02 Jul 2009 08:26:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer:in-reply-to:references; bh=R2FksqdoV3g4m/Z12dIRLzOtJxZjbULEOR8miZoT/NE=; b=wesCR99obTHSbwfhI/jdr3C3y4Rex96bOX4isYhk429bSXkkmJaGXfdo1MoDyhqSJL QolOSzh+hpcBvW1v2j3nSWARFtBN5kBtdo0bPS59I4gb2K8O64jeiuK+4uO2EHD5BcUQ t2N6yUlbzd9dGFKjiqjj25hVVv2LRsHoICqww= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; b=B3WIiixSvVrYlJZgJIv8Ag0pWeuA0h+LCCRq4uMwtaf91gvgbbG6Q3rmQjz5Q0I+9I mI3CZDC/grLM8DE0K/NpGpb/qaB/KMiHHn6xcl+FJtDoQw07Qg1g8ko+g1CspCMc+CDT Wy5Dll6aZ7rBQg0KFQLHUaLh4V223ZW3WUB/s= Received: by 10.210.30.1 with SMTP id d1mr225106ebd.37.1246548383328; Thu, 02 Jul 2009 08:26:23 -0700 (PDT) Received: from localhost.localdomain ([222.92.8.142]) by mx.google.com with ESMTPS id 28sm2489355eye.26.2009.07.02.08.26.15 (version=TLSv1/SSLv3 cipher=RC4-MD5); Thu, 02 Jul 2009 08:26:21 -0700 (PDT) From: Wu Zhangjin To: linux-kernel@vger.kernel.org, linux-mips@linux-mips.org, ralf@linux-mips.org Cc: Wu Zhangjin , Yan Hua , Philippe Vachon , Zhang Le , Zhang Fuxin , loongson-dev , Liu Junliang , Erwan Lerale , Arnaud Patard Subject: [PATCH v4 12/16] [loongson] change naming methods Date: Thu, 2 Jul 2009 23:26:08 +0800 Message-Id: X-Mailer: git-send-email 1.6.2.1 In-Reply-To: References: Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23624 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips to make source code of loongson sharable to the machines(such as gdium) made by the other companies, we rename arch/mips/lemote to arch/mips/loongson, asm/mach-lemote to asm/mach-loongson, and rename lm2e to the name of the machine: fuloong-2e. accordingly, FULONG are renamed to FULOONG2E to make it distinguishable to the future FULOONG2F. and also, some other relative tuning is needed. Signed-off-by: Wu Zhangjin --- arch/mips/Kconfig | 8 +- arch/mips/Makefile | 8 +- .../asm/mach-lemote/cpu-feature-overrides.h | 59 ----- arch/mips/include/asm/mach-lemote/dma-coherence.h | 68 ------ arch/mips/include/asm/mach-lemote/loongson.h | 56 ----- arch/mips/include/asm/mach-lemote/mc146818rtc.h | 36 --- arch/mips/include/asm/mach-lemote/pci.h | 31 --- arch/mips/include/asm/mach-lemote/war.h | 25 --- .../asm/mach-loongson/cpu-feature-overrides.h | 59 +++++ .../mips/include/asm/mach-loongson/dma-coherence.h | 68 ++++++ arch/mips/include/asm/mach-loongson/loongson.h | 56 +++++ arch/mips/include/asm/mach-loongson/mc146818rtc.h | 36 +++ arch/mips/include/asm/mach-loongson/pci.h | 31 +++ arch/mips/include/asm/mach-loongson/war.h | 25 +++ arch/mips/include/asm/mips-boards/bonito64.h | 2 +- arch/mips/lemote/lm2e/Makefile | 13 -- arch/mips/lemote/lm2e/bonito-irq.c | 51 ----- arch/mips/lemote/lm2e/cmdline.c | 52 ----- arch/mips/lemote/lm2e/early_printk.c | 39 ---- arch/mips/lemote/lm2e/env.c | 58 ----- arch/mips/lemote/lm2e/init.c | 30 --- arch/mips/lemote/lm2e/irq.c | 111 ---------- arch/mips/lemote/lm2e/machtype.c | 15 -- arch/mips/lemote/lm2e/mem.c | 36 --- arch/mips/lemote/lm2e/pci.c | 83 ------- arch/mips/lemote/lm2e/reset.c | 39 ---- arch/mips/lemote/lm2e/setup.c | 60 ------ arch/mips/lemote/lm2e/time.c | 27 --- arch/mips/loongson/fuloong-2e/Makefile | 13 ++ arch/mips/loongson/fuloong-2e/bonito-irq.c | 51 +++++ arch/mips/loongson/fuloong-2e/cmdline.c | 52 +++++ arch/mips/loongson/fuloong-2e/early_printk.c | 39 ++++ arch/mips/loongson/fuloong-2e/env.c | 58 +++++ arch/mips/loongson/fuloong-2e/init.c | 30 +++ arch/mips/loongson/fuloong-2e/irq.c | 111 ++++++++++ arch/mips/loongson/fuloong-2e/machtype.c | 15 ++ arch/mips/loongson/fuloong-2e/mem.c | 36 +++ arch/mips/loongson/fuloong-2e/pci.c | 83 +++++++ arch/mips/loongson/fuloong-2e/reset.c | 39 ++++ arch/mips/loongson/fuloong-2e/setup.c | 60 ++++++ arch/mips/loongson/fuloong-2e/time.c | 27 +++ arch/mips/pci/Makefile | 2 +- arch/mips/pci/fixup-fuloong2e.c | 224 ++++++++++++++++++++ arch/mips/pci/fixup-lm2e.c | 224 -------------------- arch/mips/pci/ops-bonito64.c | 4 +- 45 files changed, 1125 insertions(+), 1125 deletions(-) delete mode 100644 arch/mips/include/asm/mach-lemote/cpu-feature-overrides.h delete mode 100644 arch/mips/include/asm/mach-lemote/dma-coherence.h delete mode 100644 arch/mips/include/asm/mach-lemote/loongson.h delete mode 100644 arch/mips/include/asm/mach-lemote/mc146818rtc.h delete mode 100644 arch/mips/include/asm/mach-lemote/pci.h delete mode 100644 arch/mips/include/asm/mach-lemote/war.h create mode 100644 arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h create mode 100644 arch/mips/include/asm/mach-loongson/dma-coherence.h create mode 100644 arch/mips/include/asm/mach-loongson/loongson.h create mode 100644 arch/mips/include/asm/mach-loongson/mc146818rtc.h create mode 100644 arch/mips/include/asm/mach-loongson/pci.h create mode 100644 arch/mips/include/asm/mach-loongson/war.h delete mode 100644 arch/mips/lemote/lm2e/Makefile delete mode 100644 arch/mips/lemote/lm2e/bonito-irq.c delete mode 100644 arch/mips/lemote/lm2e/cmdline.c delete mode 100644 arch/mips/lemote/lm2e/early_printk.c delete mode 100644 arch/mips/lemote/lm2e/env.c delete mode 100644 arch/mips/lemote/lm2e/init.c delete mode 100644 arch/mips/lemote/lm2e/irq.c delete mode 100644 arch/mips/lemote/lm2e/machtype.c delete mode 100644 arch/mips/lemote/lm2e/mem.c delete mode 100644 arch/mips/lemote/lm2e/pci.c delete mode 100644 arch/mips/lemote/lm2e/reset.c delete mode 100644 arch/mips/lemote/lm2e/setup.c delete mode 100644 arch/mips/lemote/lm2e/time.c create mode 100644 arch/mips/loongson/fuloong-2e/Makefile create mode 100644 arch/mips/loongson/fuloong-2e/bonito-irq.c create mode 100644 arch/mips/loongson/fuloong-2e/cmdline.c create mode 100644 arch/mips/loongson/fuloong-2e/early_printk.c create mode 100644 arch/mips/loongson/fuloong-2e/env.c create mode 100644 arch/mips/loongson/fuloong-2e/init.c create mode 100644 arch/mips/loongson/fuloong-2e/irq.c create mode 100644 arch/mips/loongson/fuloong-2e/machtype.c create mode 100644 arch/mips/loongson/fuloong-2e/mem.c create mode 100644 arch/mips/loongson/fuloong-2e/pci.c create mode 100644 arch/mips/loongson/fuloong-2e/reset.c create mode 100644 arch/mips/loongson/fuloong-2e/setup.c create mode 100644 arch/mips/loongson/fuloong-2e/time.c create mode 100644 arch/mips/pci/fixup-fuloong2e.c delete mode 100644 arch/mips/pci/fixup-lm2e.c diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index a383dac..3414e23 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -6,7 +6,7 @@ config MIPS select HAVE_ARCH_KGDB # Horrible source of confusion. Die, die, die ... select EMBEDDED - select RTC_LIB if !LEMOTE_FULONG + select RTC_LIB if !LEMOTE_FULOONG2E mainmenu "Linux/MIPS Kernel Configuration" @@ -174,8 +174,8 @@ config LASAT select SYS_SUPPORTS_64BIT_KERNEL if BROKEN select SYS_SUPPORTS_LITTLE_ENDIAN -config LEMOTE_FULONG - bool "Lemote Fulong mini-PC" +config LEMOTE_FULOONG2E + bool "Lemote Fuloong2e mini-PC" select ARCH_SPARSEMEM_ENABLE select CEVT_R4K select CSRC_R4K @@ -196,7 +196,7 @@ config LEMOTE_FULONG select GENERIC_ISA_DMA_SUPPORT_BROKEN select CPU_HAS_WB help - Lemote Fulong mini-PC board based on the Chinese Loongson-2E CPU and + Lemote Fuloong2e mini-PC board based on the Chinese Loongson-2E CPU and an FPGA northbridge config MIPS_MALTA diff --git a/arch/mips/Makefile b/arch/mips/Makefile index 861da51..7754cbb 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -314,11 +314,11 @@ cflags-$(CONFIG_WR_PPMC) += -I$(srctree)/arch/mips/include/asm/mach-wrppmc load-$(CONFIG_WR_PPMC) += 0xffffffff80100000 # -# lemote fulong mini-PC board +# lemote fuloong2e mini-PC board # -core-$(CONFIG_LEMOTE_FULONG) +=arch/mips/lemote/lm2e/ -load-$(CONFIG_LEMOTE_FULONG) +=0xffffffff80100000 -cflags-$(CONFIG_LEMOTE_FULONG) += -I$(srctree)/arch/mips/include/asm/mach-lemote +core-$(CONFIG_LEMOTE_FULOONG2E) +=arch/mips/loongson/fuloong-2e/ +load-$(CONFIG_LEMOTE_FULOONG2E) +=0xffffffff80100000 +cflags-$(CONFIG_LEMOTE_FULOONG2E) += -I$(srctree)/arch/mips/include/asm/mach-loongson/ # # MIPS Malta board diff --git a/arch/mips/include/asm/mach-lemote/cpu-feature-overrides.h b/arch/mips/include/asm/mach-lemote/cpu-feature-overrides.h deleted file mode 100644 index 550a10d..0000000 --- a/arch/mips/include/asm/mach-lemote/cpu-feature-overrides.h +++ /dev/null @@ -1,59 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2009 Wu Zhangjin - * Copyright (C) 2009 Philippe Vachon - * Copyright (C) 2009 Zhang Le - * - * reference: /proc/cpuinfo, - * arch/mips/kernel/cpu-probe.c(cpu_probe_legacy), - * arch/mips/kernel/proc.c(show_cpuinfo), - * loongson2f user manual. - */ - -#ifndef __ASM_MACH_LEMOTE_CPU_FEATURE_OVERRIDES_H -#define __ASM_MACH_LEMOTE_CPU_FEATURE_OVERRIDES_H - -#define cpu_dcache_line_size() 32 -#define cpu_icache_line_size() 32 -#define cpu_scache_line_size() 32 - - -#define cpu_has_32fpr 1 -#define cpu_has_3k_cache 0 -#define cpu_has_4k_cache 1 -#define cpu_has_4kex 1 -#define cpu_has_64bits 1 -#define cpu_has_cache_cdex_p 0 -#define cpu_has_cache_cdex_s 0 -#define cpu_has_counter 1 -#define cpu_has_dc_aliases 1 -#define cpu_has_divec 0 -#define cpu_has_dsp 0 -#define cpu_has_ejtag 0 -#define cpu_has_fpu 1 -#define cpu_has_ic_fills_f_dc 0 -#define cpu_has_inclusive_pcaches 1 -#define cpu_has_llsc 1 -#define cpu_has_mcheck 0 -#define cpu_has_mdmx 0 -#define cpu_has_mips16 0 -#define cpu_has_mips32r1 0 -#define cpu_has_mips32r2 0 -#define cpu_has_mips3d 0 -#define cpu_has_mips64r1 0 -#define cpu_has_mips64r2 0 -#define cpu_has_mipsmt 0 -#define cpu_has_prefetch 0 -#define cpu_has_smartmips 0 -#define cpu_has_tlb 1 -#define cpu_has_tx39_cache 0 -#define cpu_has_userlocal 0 -#define cpu_has_vce 0 -#define cpu_has_vtag_icache 0 -#define cpu_has_watch 1 -#define cpu_icache_snoops_remote_store 1 - -#endif /* __ASM_MACH_LEMOTE_CPU_FEATURE_OVERRIDES_H */ diff --git a/arch/mips/include/asm/mach-lemote/dma-coherence.h b/arch/mips/include/asm/mach-lemote/dma-coherence.h deleted file mode 100644 index c8de5e7..0000000 --- a/arch/mips/include/asm/mach-lemote/dma-coherence.h +++ /dev/null @@ -1,68 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2006, 07 Ralf Baechle - * Copyright (C) 2007 Lemote, Inc. & Institute of Computing Technology - * Author: Fuxin Zhang, zhangfx@lemote.com - * - */ -#ifndef __ASM_MACH_LEMOTE_DMA_COHERENCE_H -#define __ASM_MACH_LEMOTE_DMA_COHERENCE_H - -struct device; - -static inline dma_addr_t plat_map_dma_mem(struct device *dev, void *addr, - size_t size) -{ - return virt_to_phys(addr) | 0x80000000; -} - -static inline dma_addr_t plat_map_dma_mem_page(struct device *dev, - struct page *page) -{ - return page_to_phys(page) | 0x80000000; -} - -static inline unsigned long plat_dma_addr_to_phys(struct device *dev, - dma_addr_t dma_addr) -{ - return dma_addr & 0x7fffffff; -} - -static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr, - size_t size, enum dma_data_direction direction) -{ -} - -static inline int plat_dma_supported(struct device *dev, u64 mask) -{ - /* - * we fall back to GFP_DMA when the mask isn't all 1s, - * so we can't guarantee allocations that must be - * within a tighter range than GFP_DMA.. - */ - if (mask < DMA_BIT_MASK(24)) - return 0; - - return 1; -} - -static inline void plat_extra_sync_for_device(struct device *dev) -{ - return; -} - -static inline int plat_dma_mapping_error(struct device *dev, - dma_addr_t dma_addr) -{ - return 0; -} - -static inline int plat_device_is_coherent(struct device *dev) -{ - return 0; -} - -#endif /* __ASM_MACH_LEMOTE_DMA_COHERENCE_H */ diff --git a/arch/mips/include/asm/mach-lemote/loongson.h b/arch/mips/include/asm/mach-lemote/loongson.h deleted file mode 100644 index 95ee4c8..0000000 --- a/arch/mips/include/asm/mach-lemote/loongson.h +++ /dev/null @@ -1,56 +0,0 @@ -/* - * Copyright (C) 2009 Lemote, Inc. & Institute of Computing Technology - * Author: Wu Zhangjin - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - */ - -#ifndef __ASM_MACH_LOONGSON_LOONGSON_H -#define __ASM_MACH_LOONGSON_LOONGSON_H - -#include -#include - -/* there is an internal bonito64-compatiable northbridge in loongson2e/2f */ -#include - -/* loongson internal northbridge initialization */ -extern void bonito_irq_init(void); - -/* loongson-based machines specific reboot setup */ -extern void mips_reboot_setup(void); - -/* environment arguments from bootloader */ -extern unsigned long bus_clock, cpu_clock_freq; -extern unsigned long memsize, highmemsize; - -/* loongson-specific command line, env and memory initialization */ -extern void __init prom_init_memory(void); -extern void __init prom_init_cmdline(void); -extern void __init prom_init_env(void); - -/* PCI Configuration Registers */ -#define LOONGSON_PCI_ISR4C BONITO_PCI_REG(0x4c) - -/* PCI_Hit*_Sel_* */ - -#define LOONGSON_PCI_HIT0_SEL_L BONITO(BONITO_REGBASE + 0x50) -#define LOONGSON_PCI_HIT0_SEL_H BONITO(BONITO_REGBASE + 0x54) -#define LOONGSON_PCI_HIT1_SEL_L BONITO(BONITO_REGBASE + 0x58) -#define LOONGSON_PCI_HIT1_SEL_H BONITO(BONITO_REGBASE + 0x5c) -#define LOONGSON_PCI_HIT2_SEL_L BONITO(BONITO_REGBASE + 0x60) -#define LOONGSON_PCI_HIT2_SEL_H BONITO(BONITO_REGBASE + 0x64) - -/* PXArb Config & Status */ - -#define LOONGSON_PXARB_CFG BONITO(BONITO_REGBASE + 0x68) -#define LOONGSON_PXARB_STATUS BONITO(BONITO_REGBASE + 0x6c) - -/* loongson2-specific perf counter IRQ */ -#define LOONGSON2_PERFCNT_IRQ (MIPS_CPU_IRQ_BASE + 6) - -#endif /* __ASM_MACH_LOONGSON_LOONGSON_H */ diff --git a/arch/mips/include/asm/mach-lemote/mc146818rtc.h b/arch/mips/include/asm/mach-lemote/mc146818rtc.h deleted file mode 100644 index ed5147e..0000000 --- a/arch/mips/include/asm/mach-lemote/mc146818rtc.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1998, 2001, 03, 07 by Ralf Baechle (ralf@linux-mips.org) - * - * RTC routines for PC style attached Dallas chip. - */ -#ifndef __ASM_MACH_LEMOTE_MC146818RTC_H -#define __ASM_MACH_LEMOTE_MC146818RTC_H - -#include - -#define RTC_PORT(x) (0x70 + (x)) -#define RTC_IRQ 8 - -static inline unsigned char CMOS_READ(unsigned long addr) -{ - outb_p(addr, RTC_PORT(0)); - return inb_p(RTC_PORT(1)); -} - -static inline void CMOS_WRITE(unsigned char data, unsigned long addr) -{ - outb_p(addr, RTC_PORT(0)); - outb_p(data, RTC_PORT(1)); -} - -#define RTC_ALWAYS_BCD 0 - -#ifndef mc146818_decode_year -#define mc146818_decode_year(year) ((year) < 70 ? (year) + 2000 : (year) + 1970) -#endif - -#endif /* __ASM_MACH_LEMOTE_MC146818RTC_H */ diff --git a/arch/mips/include/asm/mach-lemote/pci.h b/arch/mips/include/asm/mach-lemote/pci.h deleted file mode 100644 index 3e6b130..0000000 --- a/arch/mips/include/asm/mach-lemote/pci.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * Copyright (c) 2008 Zhang Le - * - * This program is free software; you can redistribute it - * and/or modify it under the terms of the GNU General - * Public License as published by the Free Software - * Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * This program is distributed in the hope that it will be - * useful, but WITHOUT ANY WARRANTY; without even the implied - * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR - * PURPOSE. See the GNU General Public License for more - * details. - * - * You should have received a copy of the GNU General Public - * License along with this program; if not, write to the Free - * Software Foundation, Inc., 675 Mass Ave, Cambridge, MA - * 02139, USA. - */ - -#ifndef __ASM_MACH_LEMOTE_PCI_H_ -#define __ASM_MACH_LEMOTE_PCI_H_ - -extern struct pci_ops bonito64_pci_ops; - -#define LOONGSON2E_PCI_MEM_START BONITO_PCILO1_BASE -#define LOONGSON2E_PCI_MEM_END (BONITO_PCILO1_BASE + 0x04000000 * 2) -#define LOONGSON2E_PCI_IO_START 0x00004000UL - -#endif /* !__ASM_MACH_LEMOTE_PCI_H_ */ diff --git a/arch/mips/include/asm/mach-lemote/war.h b/arch/mips/include/asm/mach-lemote/war.h deleted file mode 100644 index 05f89e0..0000000 --- a/arch/mips/include/asm/mach-lemote/war.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 2002, 2004, 2007 by Ralf Baechle - */ -#ifndef __ASM_MIPS_MACH_LEMOTE_WAR_H -#define __ASM_MIPS_MACH_LEMOTE_WAR_H - -#define R4600_V1_INDEX_ICACHEOP_WAR 0 -#define R4600_V1_HIT_CACHEOP_WAR 0 -#define R4600_V2_HIT_CACHEOP_WAR 0 -#define R5432_CP0_INTERRUPT_WAR 0 -#define BCM1250_M3_WAR 0 -#define SIBYTE_1956_WAR 0 -#define MIPS4K_ICACHE_REFILL_WAR 0 -#define MIPS_CACHE_SYNC_WAR 0 -#define TX49XX_ICACHE_INDEX_INV_WAR 0 -#define RM9000_CDEX_SMP_WAR 0 -#define ICACHE_REFILLS_WORKAROUND_WAR 0 -#define R10000_LLSC_WAR 0 -#define MIPS34K_MISSED_ITLB_WAR 0 - -#endif /* __ASM_MIPS_MACH_LEMOTE_WAR_H */ diff --git a/arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h b/arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h new file mode 100644 index 0000000..ce5b6e2 --- /dev/null +++ b/arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h @@ -0,0 +1,59 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2009 Wu Zhangjin + * Copyright (C) 2009 Philippe Vachon + * Copyright (C) 2009 Zhang Le + * + * reference: /proc/cpuinfo, + * arch/mips/kernel/cpu-probe.c(cpu_probe_legacy), + * arch/mips/kernel/proc.c(show_cpuinfo), + * loongson2f user manual. + */ + +#ifndef __ASM_MACH_LOONGSON_CPU_FEATURE_OVERRIDES_H +#define __ASM_MACH_LOONGSON_CPU_FEATURE_OVERRIDES_H + +#define cpu_dcache_line_size() 32 +#define cpu_icache_line_size() 32 +#define cpu_scache_line_size() 32 + + +#define cpu_has_32fpr 1 +#define cpu_has_3k_cache 0 +#define cpu_has_4k_cache 1 +#define cpu_has_4kex 1 +#define cpu_has_64bits 1 +#define cpu_has_cache_cdex_p 0 +#define cpu_has_cache_cdex_s 0 +#define cpu_has_counter 1 +#define cpu_has_dc_aliases 1 +#define cpu_has_divec 0 +#define cpu_has_dsp 0 +#define cpu_has_ejtag 0 +#define cpu_has_fpu 1 +#define cpu_has_ic_fills_f_dc 0 +#define cpu_has_inclusive_pcaches 1 +#define cpu_has_llsc 1 +#define cpu_has_mcheck 0 +#define cpu_has_mdmx 0 +#define cpu_has_mips16 0 +#define cpu_has_mips32r1 0 +#define cpu_has_mips32r2 0 +#define cpu_has_mips3d 0 +#define cpu_has_mips64r1 0 +#define cpu_has_mips64r2 0 +#define cpu_has_mipsmt 0 +#define cpu_has_prefetch 0 +#define cpu_has_smartmips 0 +#define cpu_has_tlb 1 +#define cpu_has_tx39_cache 0 +#define cpu_has_userlocal 0 +#define cpu_has_vce 0 +#define cpu_has_vtag_icache 0 +#define cpu_has_watch 1 +#define cpu_icache_snoops_remote_store 1 + +#endif /* __ASM_MACH_LOONGSON_CPU_FEATURE_OVERRIDES_H */ diff --git a/arch/mips/include/asm/mach-loongson/dma-coherence.h b/arch/mips/include/asm/mach-loongson/dma-coherence.h new file mode 100644 index 0000000..71a6851 --- /dev/null +++ b/arch/mips/include/asm/mach-loongson/dma-coherence.h @@ -0,0 +1,68 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2006, 07 Ralf Baechle + * Copyright (C) 2007 Lemote, Inc. & Institute of Computing Technology + * Author: Fuxin Zhang, zhangfx@lemote.com + * + */ +#ifndef __ASM_MACH_LOONGSON_DMA_COHERENCE_H +#define __ASM_MACH_LOONGSON_DMA_COHERENCE_H + +struct device; + +static inline dma_addr_t plat_map_dma_mem(struct device *dev, void *addr, + size_t size) +{ + return virt_to_phys(addr) | 0x80000000; +} + +static inline dma_addr_t plat_map_dma_mem_page(struct device *dev, + struct page *page) +{ + return page_to_phys(page) | 0x80000000; +} + +static inline unsigned long plat_dma_addr_to_phys(struct device *dev, + dma_addr_t dma_addr) +{ + return dma_addr & 0x7fffffff; +} + +static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr, + size_t size, enum dma_data_direction direction) +{ +} + +static inline int plat_dma_supported(struct device *dev, u64 mask) +{ + /* + * we fall back to GFP_DMA when the mask isn't all 1s, + * so we can't guarantee allocations that must be + * within a tighter range than GFP_DMA.. + */ + if (mask < DMA_BIT_MASK(24)) + return 0; + + return 1; +} + +static inline void plat_extra_sync_for_device(struct device *dev) +{ + return; +} + +static inline int plat_dma_mapping_error(struct device *dev, + dma_addr_t dma_addr) +{ + return 0; +} + +static inline int plat_device_is_coherent(struct device *dev) +{ + return 0; +} + +#endif /* __ASM_MACH_LOONGSON_DMA_COHERENCE_H */ diff --git a/arch/mips/include/asm/mach-loongson/loongson.h b/arch/mips/include/asm/mach-loongson/loongson.h new file mode 100644 index 0000000..95ee4c8 --- /dev/null +++ b/arch/mips/include/asm/mach-loongson/loongson.h @@ -0,0 +1,56 @@ +/* + * Copyright (C) 2009 Lemote, Inc. & Institute of Computing Technology + * Author: Wu Zhangjin + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + */ + +#ifndef __ASM_MACH_LOONGSON_LOONGSON_H +#define __ASM_MACH_LOONGSON_LOONGSON_H + +#include +#include + +/* there is an internal bonito64-compatiable northbridge in loongson2e/2f */ +#include + +/* loongson internal northbridge initialization */ +extern void bonito_irq_init(void); + +/* loongson-based machines specific reboot setup */ +extern void mips_reboot_setup(void); + +/* environment arguments from bootloader */ +extern unsigned long bus_clock, cpu_clock_freq; +extern unsigned long memsize, highmemsize; + +/* loongson-specific command line, env and memory initialization */ +extern void __init prom_init_memory(void); +extern void __init prom_init_cmdline(void); +extern void __init prom_init_env(void); + +/* PCI Configuration Registers */ +#define LOONGSON_PCI_ISR4C BONITO_PCI_REG(0x4c) + +/* PCI_Hit*_Sel_* */ + +#define LOONGSON_PCI_HIT0_SEL_L BONITO(BONITO_REGBASE + 0x50) +#define LOONGSON_PCI_HIT0_SEL_H BONITO(BONITO_REGBASE + 0x54) +#define LOONGSON_PCI_HIT1_SEL_L BONITO(BONITO_REGBASE + 0x58) +#define LOONGSON_PCI_HIT1_SEL_H BONITO(BONITO_REGBASE + 0x5c) +#define LOONGSON_PCI_HIT2_SEL_L BONITO(BONITO_REGBASE + 0x60) +#define LOONGSON_PCI_HIT2_SEL_H BONITO(BONITO_REGBASE + 0x64) + +/* PXArb Config & Status */ + +#define LOONGSON_PXARB_CFG BONITO(BONITO_REGBASE + 0x68) +#define LOONGSON_PXARB_STATUS BONITO(BONITO_REGBASE + 0x6c) + +/* loongson2-specific perf counter IRQ */ +#define LOONGSON2_PERFCNT_IRQ (MIPS_CPU_IRQ_BASE + 6) + +#endif /* __ASM_MACH_LOONGSON_LOONGSON_H */ diff --git a/arch/mips/include/asm/mach-loongson/mc146818rtc.h b/arch/mips/include/asm/mach-loongson/mc146818rtc.h new file mode 100644 index 0000000..ed7fe97 --- /dev/null +++ b/arch/mips/include/asm/mach-loongson/mc146818rtc.h @@ -0,0 +1,36 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1998, 2001, 03, 07 by Ralf Baechle (ralf@linux-mips.org) + * + * RTC routines for PC style attached Dallas chip. + */ +#ifndef __ASM_MACH_LOONGSON_MC146818RTC_H +#define __ASM_MACH_LOONGSON_MC146818RTC_H + +#include + +#define RTC_PORT(x) (0x70 + (x)) +#define RTC_IRQ 8 + +static inline unsigned char CMOS_READ(unsigned long addr) +{ + outb_p(addr, RTC_PORT(0)); + return inb_p(RTC_PORT(1)); +} + +static inline void CMOS_WRITE(unsigned char data, unsigned long addr) +{ + outb_p(addr, RTC_PORT(0)); + outb_p(data, RTC_PORT(1)); +} + +#define RTC_ALWAYS_BCD 0 + +#ifndef mc146818_decode_year +#define mc146818_decode_year(year) ((year) < 70 ? (year) + 2000 : (year) + 1970) +#endif + +#endif /* __ASM_MACH_LOONGSON_MC146818RTC_H */ diff --git a/arch/mips/include/asm/mach-loongson/pci.h b/arch/mips/include/asm/mach-loongson/pci.h new file mode 100644 index 0000000..e229b29 --- /dev/null +++ b/arch/mips/include/asm/mach-loongson/pci.h @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2008 Zhang Le + * + * This program is free software; you can redistribute it + * and/or modify it under the terms of the GNU General + * Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * This program is distributed in the hope that it will be + * useful, but WITHOUT ANY WARRANTY; without even the implied + * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR + * PURPOSE. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public + * License along with this program; if not, write to the Free + * Software Foundation, Inc., 675 Mass Ave, Cambridge, MA + * 02139, USA. + */ + +#ifndef __ASM_MACH_LOONGSON_PCI_H_ +#define __ASM_MACH_LOONGSON_PCI_H_ + +extern struct pci_ops bonito64_pci_ops; + +#define LOONGSON2E_PCI_MEM_START BONITO_PCILO1_BASE +#define LOONGSON2E_PCI_MEM_END (BONITO_PCILO1_BASE + 0x04000000 * 2) +#define LOONGSON2E_PCI_IO_START 0x00004000UL + +#endif /* !__ASM_MACH_LOONGSON_PCI_H_ */ diff --git a/arch/mips/include/asm/mach-loongson/war.h b/arch/mips/include/asm/mach-loongson/war.h new file mode 100644 index 0000000..4b971c3 --- /dev/null +++ b/arch/mips/include/asm/mach-loongson/war.h @@ -0,0 +1,25 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle + */ +#ifndef __ASM_MACH_LOONGSON_WAR_H +#define __ASM_MACH_LOONGSON_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 0 +#define MIPS_CACHE_SYNC_WAR 0 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 0 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MACH_LEMOTE_WAR_H */ diff --git a/arch/mips/include/asm/mips-boards/bonito64.h b/arch/mips/include/asm/mips-boards/bonito64.h index a0f04bb..a576ce0 100644 --- a/arch/mips/include/asm/mips-boards/bonito64.h +++ b/arch/mips/include/asm/mips-boards/bonito64.h @@ -26,7 +26,7 @@ /* offsets from base register */ #define BONITO(x) (x) -#elif defined(CONFIG_LEMOTE_FULONG) +#elif defined(CONFIG_LEMOTE_FULOONG2E) #define BONITO(x) (*(volatile u32 *)((char *)CKSEG1ADDR(BONITO_REG_BASE) + (x))) #define BONITO_IRQ_BASE 32 diff --git a/arch/mips/lemote/lm2e/Makefile b/arch/mips/lemote/lm2e/Makefile deleted file mode 100644 index a5bc1ef..0000000 --- a/arch/mips/lemote/lm2e/Makefile +++ /dev/null @@ -1,13 +0,0 @@ -# -# Makefile for Lemote Fulong mini-PC board. -# - -obj-y += setup.o init.o reset.o irq.o pci.o bonito-irq.o mem.o \ - env.o cmdline.o time.o machtype.o - -# -# Early printk support -# -obj-$(CONFIG_EARLY_PRINTK) += early_printk.o - -EXTRA_CFLAGS += -Werror diff --git a/arch/mips/lemote/lm2e/bonito-irq.c b/arch/mips/lemote/lm2e/bonito-irq.c deleted file mode 100644 index 3e31e7a..0000000 --- a/arch/mips/lemote/lm2e/bonito-irq.c +++ /dev/null @@ -1,51 +0,0 @@ -/* - * Copyright 2001 MontaVista Software Inc. - * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net - * Copyright (C) 2000, 2001 Ralf Baechle (ralf@gnu.org) - * - * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology - * Author: Fuxin Zhang, zhangfx@lemote.com - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ -#include - -#include - -static inline void bonito_irq_enable(unsigned int irq) -{ - BONITO_INTENSET = (1 << (irq - BONITO_IRQ_BASE)); - mmiowb(); -} - -static inline void bonito_irq_disable(unsigned int irq) -{ - BONITO_INTENCLR = (1 << (irq - BONITO_IRQ_BASE)); - mmiowb(); -} - -static struct irq_chip bonito_irq_type = { - .name = "bonito_irq", - .ack = bonito_irq_disable, - .mask = bonito_irq_disable, - .mask_ack = bonito_irq_disable, - .unmask = bonito_irq_enable, -}; - -static struct irqaction dma_timeout_irqaction = { - .handler = no_action, - .name = "dma_timeout", -}; - -void bonito_irq_init(void) -{ - u32 i; - - for (i = BONITO_IRQ_BASE; i < BONITO_IRQ_BASE + 32; i++) - set_irq_chip_and_handler(i, &bonito_irq_type, handle_level_irq); - - setup_irq(BONITO_IRQ_BASE + 10, &dma_timeout_irqaction); -} diff --git a/arch/mips/lemote/lm2e/cmdline.c b/arch/mips/lemote/lm2e/cmdline.c deleted file mode 100644 index 75f1b24..0000000 --- a/arch/mips/lemote/lm2e/cmdline.c +++ /dev/null @@ -1,52 +0,0 @@ -/* - * Based on Ocelot Linux port, which is - * Copyright 2001 MontaVista Software Inc. - * Author: jsun@mvista.com or jsun@junsun.net - * - * Copyright 2003 ICT CAS - * Author: Michael Guo - * - * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology - * Author: Fuxin Zhang, zhangfx@lemote.com - * - * Copyright (C) 2009 Lemote Inc. & Insititute of Computing Technology - * Author: Wu Zhangjin, wuzj@lemote.com - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ -#include - -#include - -int prom_argc; -/* pmon passes arguments in 32bit pointers */ -int *_prom_argv; - -void __init prom_init_cmdline(void) -{ - int i; - long l; - - /* firmware arguments are initialized in head.S */ - prom_argc = fw_arg0; - _prom_argv = (int *)fw_arg1; - - /* arg[0] is "g", the rest is boot parameters */ - arcs_cmdline[0] = '\0'; - for (i = 1; i < prom_argc; i++) { - l = (long)_prom_argv[i]; - if (strlen(arcs_cmdline) + strlen(((char *)l) + 1) - >= sizeof(arcs_cmdline)) - break; - strcat(arcs_cmdline, ((char *)l)); - strcat(arcs_cmdline, " "); - } - - if ((strstr(arcs_cmdline, "console=")) == NULL) - strcat(arcs_cmdline, " console=ttyS0,115200"); - if ((strstr(arcs_cmdline, "root=")) == NULL) - strcat(arcs_cmdline, " root=/dev/hda1"); -} diff --git a/arch/mips/lemote/lm2e/early_printk.c b/arch/mips/lemote/lm2e/early_printk.c deleted file mode 100644 index 3e0a6ea..0000000 --- a/arch/mips/lemote/lm2e/early_printk.c +++ /dev/null @@ -1,39 +0,0 @@ -/* early printk support - * - * Copyright (c) 2009 Philippe Vachon - * Copyright (C) 2009 Lemote Inc. & Insititute of Computing Technology - * Author: Wu Zhangjin, wuzj@lemote.com - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ -#include - -#include - -#define UART_BASE (BONITO_PCIIO_BASE + 0x3f8) - -#define PORT(base, offset) (u8 *)(base + offset) - -static inline unsigned int serial_in(phys_addr_t base, int offset) -{ - return readb(PORT(base, offset)); -} - -static inline void serial_out(phys_addr_t base, int offset, int value) -{ - writeb(value, PORT(base, offset)); -} - -void prom_putchar(char c) -{ - phys_addr_t uart_base = - (phys_addr_t) ioremap_nocache(UART_BASE, 8); - - while ((serial_in(uart_base, UART_LSR) & UART_LSR_THRE) == 0) - ; - - serial_out(uart_base, UART_TX, c); -} diff --git a/arch/mips/lemote/lm2e/env.c b/arch/mips/lemote/lm2e/env.c deleted file mode 100644 index b9ef503..0000000 --- a/arch/mips/lemote/lm2e/env.c +++ /dev/null @@ -1,58 +0,0 @@ -/* - * Based on Ocelot Linux port, which is - * Copyright 2001 MontaVista Software Inc. - * Author: jsun@mvista.com or jsun@junsun.net - * - * Copyright 2003 ICT CAS - * Author: Michael Guo - * - * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology - * Author: Fuxin Zhang, zhangfx@lemote.com - * - * Copyright (C) 2009 Lemote Inc. & Insititute of Computing Technology - * Author: Wu Zhangjin, wuzj@lemote.com - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ -#include - -#include - -unsigned long bus_clock, cpu_clock_freq; -unsigned long memsize, highmemsize; - -/* pmon passes arguments in 32bit pointers */ -int *_prom_envp; - -#define parse_even_earlier(res, option, p) \ -do { \ - if (strncmp(option, (char *)p, strlen(option)) == 0) \ - strict_strtol((char *)p + strlen(option"="), \ - 10, &res); \ -} while (0) - -void __init prom_init_env(void) -{ - long l; - - /* firmware arguments are initialized in head.S */ - _prom_envp = (int *)fw_arg2; - - l = (long)*_prom_envp; - while (l != 0) { - parse_even_earlier(bus_clock, "busclock", l); - parse_even_earlier(cpu_clock_freq, "cpuclock", l); - parse_even_earlier(memsize, "memsize", l); - parse_even_earlier(highmemsize, "highmemsize", l); - _prom_envp++; - l = (long)*_prom_envp; - } - if (memsize == 0) - memsize = 256; - - pr_info("busclock=%ld, cpuclock=%ld, memsize=%ld, highmemsize=%ld\n", - bus_clock, cpu_clock_freq, memsize, highmemsize); -} diff --git a/arch/mips/lemote/lm2e/init.c b/arch/mips/lemote/lm2e/init.c deleted file mode 100644 index 3abe927..0000000 --- a/arch/mips/lemote/lm2e/init.c +++ /dev/null @@ -1,30 +0,0 @@ -/* - * Copyright (C) 2009 Lemote Inc. & Insititute of Computing Technology - * Author: Wu Zhangjin, wuzj@lemote.com - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#include - -#include - -#include - -void __init prom_init(void) -{ - /* init base address of io space */ - set_io_port_base((unsigned long) - ioremap(BONITO_PCIIO_BASE, BONITO_PCIIO_SIZE)); - - prom_init_cmdline(); - prom_init_env(); - prom_init_memory(); -} - -void __init prom_free_prom_memory(void) -{ -} diff --git a/arch/mips/lemote/lm2e/irq.c b/arch/mips/lemote/lm2e/irq.c deleted file mode 100644 index 9585f5a..0000000 --- a/arch/mips/lemote/lm2e/irq.c +++ /dev/null @@ -1,111 +0,0 @@ -/* - * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology - * Author: Fuxin Zhang, zhangfx@lemote.com - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ -#include -#include - -#include -#include - -#include -/* - * the first level int-handler will jump here if it is a bonito irq - */ -static void bonito_irqdispatch(void) -{ - u32 int_status; - int i; - - /* workaround the IO dma problem: let cpu looping to allow DMA finish */ - int_status = BONITO_INTISR; - if (int_status & (1 << 10)) { - while (int_status & (1 << 10)) { - udelay(1); - int_status = BONITO_INTISR; - } - } - - /* Get pending sources, masked by current enables */ - int_status = BONITO_INTISR & BONITO_INTEN; - - if (int_status != 0) { - i = __ffs(int_status); - int_status &= ~(1 << i); - do_IRQ(BONITO_IRQ_BASE + i); - } -} - -static void i8259_irqdispatch(void) -{ - int irq; - - irq = i8259_irq(); - if (irq >= 0) - do_IRQ(irq); - else - spurious_interrupt(); -} - -asmlinkage void plat_irq_dispatch(void) -{ - unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM; - - if (pending & CAUSEF_IP7) - do_IRQ(MIPS_CPU_IRQ_BASE + 7); - else if (pending & CAUSEF_IP6) /* perf counter loverflow */ - do_IRQ(LOONGSON2_PERFCNT_IRQ); - else if (pending & CAUSEF_IP5) - i8259_irqdispatch(); - else if (pending & CAUSEF_IP2) - bonito_irqdispatch(); - else - spurious_interrupt(); -} - -static struct irqaction cascade_irqaction = { - .handler = no_action, - .name = "cascade", -}; - -void __init arch_init_irq(void) -{ - /* - * Clear all of the interrupts while we change the able around a bit. - * int-handler is not on bootstrap - */ - clear_c0_status(ST0_IM | ST0_BEV); - local_irq_disable(); - - /* most bonito irq should be level triggered */ - BONITO_INTEDGE = BONITO_ICU_SYSTEMERR | BONITO_ICU_MASTERERR | - BONITO_ICU_RETRYERR | BONITO_ICU_MBOXES; - BONITO_INTSTEER = 0; - - /* - * Mask out all interrupt by writing "1" to all bit position in - * the interrupt reset reg. - */ - BONITO_INTENCLR = ~0; - - /* init all controller - * 0-15 ------> i8259 interrupt - * 16-23 ------> mips cpu interrupt - * 32-63 ------> bonito irq - */ - - /* Sets the first-level interrupt dispatcher. */ - mips_cpu_irq_init(); - init_i8259_irqs(); - bonito_irq_init(); - - /* bonito irq at IP2 */ - setup_irq(MIPS_CPU_IRQ_BASE + 2, &cascade_irqaction); - /* 8259 irq at IP5 */ - setup_irq(MIPS_CPU_IRQ_BASE + 5, &cascade_irqaction); -} diff --git a/arch/mips/lemote/lm2e/machtype.c b/arch/mips/lemote/lm2e/machtype.c deleted file mode 100644 index 8d803ee..0000000 --- a/arch/mips/lemote/lm2e/machtype.c +++ /dev/null @@ -1,15 +0,0 @@ -/* - * Copyright (C) 2009 Lemote Inc. & Insititute of Computing Technology - * Author: Wu Zhangjin, wuzj@lemote.com - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -const char *get_system_type(void) -{ - return "lemote-fulong"; -} - diff --git a/arch/mips/lemote/lm2e/mem.c b/arch/mips/lemote/lm2e/mem.c deleted file mode 100644 index 6a7feb1..0000000 --- a/arch/mips/lemote/lm2e/mem.c +++ /dev/null @@ -1,36 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ -#include -#include -#include - -#include - -#include - -void __init prom_init_memory(void) -{ - add_memory_region(0x0, (memsize << 20), BOOT_MEM_RAM); -#ifdef CONFIG_64BIT - if (highmemsize > 0) - add_memory_region(0x20000000, highmemsize << 20, BOOT_MEM_RAM); -#endif /* CONFIG_64BIT */ -} - -/* override of arch/mips/mm/cache.c: __uncached_access */ -int __uncached_access(struct file *file, unsigned long addr) -{ - if (file->f_flags & O_SYNC) - return 1; - - /* - * On the Lemote Loongson 2e system, the peripheral registers - * reside between 0x1000:0000 and 0x2000:0000. - */ - return addr >= __pa(high_memory) || - ((addr >= 0x10000000) && (addr < 0x20000000)); -} diff --git a/arch/mips/lemote/lm2e/pci.c b/arch/mips/lemote/lm2e/pci.c deleted file mode 100644 index 9812c30..0000000 --- a/arch/mips/lemote/lm2e/pci.c +++ /dev/null @@ -1,83 +0,0 @@ -/* - * Copyright (C) 2007 Lemote, Inc. & Institute of Computing Technology - * Author: Fuxin Zhang, zhangfx@lemote.com - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ -#include - -#include -#include - -static struct resource loongson2e_pci_mem_resource = { - .name = "LOONGSON2E PCI MEM", - .start = LOONGSON2E_PCI_MEM_START, - .end = LOONGSON2E_PCI_MEM_END, - .flags = IORESOURCE_MEM, -}; - -static struct resource loongson2e_pci_io_resource = { - .name = "LOONGSON2E PCI IO MEM", - .start = LOONGSON2E_PCI_IO_START, - .end = IO_SPACE_LIMIT, - .flags = IORESOURCE_IO, -}; - -static struct pci_controller loongson2e_pci_controller = { - .pci_ops = &bonito64_pci_ops, - .io_resource = &loongson2e_pci_io_resource, - .mem_resource = &loongson2e_pci_mem_resource, - .mem_offset = 0x00000000UL, - .io_offset = 0x00000000UL, -}; - -static void __init setup_pcimap(void) -{ - /* - * local to PCI mapping for CPU accessing PCI space - * CPU address space [256M,448M] is window for accessing pci space - * we set pcimap_lo[0,1,2] to map it to pci space[0M,64M], [320M,448M] - * - * pcimap: PCI_MAP2 PCI_Mem_Lo2 PCI_Mem_Lo1 PCI_Mem_Lo0 - * [<2G] [384M,448M] [320M,384M] [0M,64M] - */ - BONITO_PCIMAP = BONITO_PCIMAP_PCIMAP_2 | - BONITO_PCIMAP_WIN(2, BONITO_PCILO2_BASE) | - BONITO_PCIMAP_WIN(1, BONITO_PCILO1_BASE) | - BONITO_PCIMAP_WIN(0, 0); - - /* - * PCI-DMA to local mapping: [2G,2G+256M] -> [0M,256M] - */ - BONITO_PCIBASE0 = 0x80000000ul; /* base: 2G -> mmap: 0M */ - /* size: 256M, burst transmission, pre-fetch enable, 64bit */ - LOONGSON_PCI_HIT0_SEL_L = 0xc000000cul; - LOONGSON_PCI_HIT0_SEL_H = 0xfffffffful; - LOONGSON_PCI_HIT1_SEL_L = 0x00000006ul; /* set this BAR as invalid */ - LOONGSON_PCI_HIT1_SEL_H = 0x00000000ul; - LOONGSON_PCI_HIT2_SEL_L = 0x00000006ul; /* set this BAR as invalid */ - LOONGSON_PCI_HIT2_SEL_H = 0x00000000ul; - - /* avoid deadlock of PCI reading/writing lock operation */ - LOONGSON_PCI_ISR4C = 0xd2000001ul; - - /* can not change gnt to break pci transfer when device's gnt not - deassert for some broken device */ - LOONGSON_PXARB_CFG = 0x00fe0105ul; -} - -static int __init pcibios_init(void) -{ - setup_pcimap(); - - loongson2e_pci_controller.io_map_base = mips_io_port_base; - - register_pci_controller(&loongson2e_pci_controller); - - return 0; -} - -arch_initcall(pcibios_init); diff --git a/arch/mips/lemote/lm2e/reset.c b/arch/mips/lemote/lm2e/reset.c deleted file mode 100644 index d89c9e4..0000000 --- a/arch/mips/lemote/lm2e/reset.c +++ /dev/null @@ -1,39 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * Copyright (C) 2007 Lemote, Inc. & Institute of Computing Technology - * Author: Fuxin Zhang, zhangfx@lemote.com - * Copyright (C) 2009 Lemote, Inc. & Institute of Computing Technology - * Author: Zhangjin Wu, wuzj@lemote.com - */ -#include - -#include - -#include - -static void loongson2e_restart(char *command) -{ - /* do preparation for reboot */ - BONITO_BONGENCFG &= ~(1 << 2); - BONITO_BONGENCFG |= (1 << 2); - - /* reboot via jumping to boot base address */ - ((void (*)(void))ioremap_nocache(BONITO_BOOT_BASE, 4)) (); -} - -static void loongson2e_halt(void) -{ - while (1) - ; -} - -void mips_reboot_setup(void) -{ - _machine_restart = loongson2e_restart; - _machine_halt = loongson2e_halt; - pm_power_off = loongson2e_halt; -} diff --git a/arch/mips/lemote/lm2e/setup.c b/arch/mips/lemote/lm2e/setup.c deleted file mode 100644 index 655695c..0000000 --- a/arch/mips/lemote/lm2e/setup.c +++ /dev/null @@ -1,60 +0,0 @@ -/* - * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology - * Author: Fuxin Zhang, zhangfx@lemote.com - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ -#include - -#include - -#include - -#ifdef CONFIG_VT -#include -#include -#endif - -void (*__wbflush)(void); -EXPORT_SYMBOL(__wbflush); - -static void wbflush_loongson2e(void) -{ - asm(".set\tpush\n\t" - ".set\tnoreorder\n\t" - ".set mips3\n\t" - "sync\n\t" - "nop\n\t" - ".set\tpop\n\t" - ".set mips0\n\t"); -} - -void __init plat_mem_setup(void) -{ - mips_reboot_setup(); - - __wbflush = wbflush_loongson2e; - -#ifdef CONFIG_VT -#if defined(CONFIG_VGA_CONSOLE) - conswitchp = &vga_con; - - screen_info = (struct screen_info) { - 0, 25, /* orig-x, orig-y */ - 0, /* unused */ - 0, /* orig-video-page */ - 0, /* orig-video-mode */ - 80, /* orig-video-cols */ - 0, 0, 0, /* ega_ax, ega_bx, ega_cx */ - 25, /* orig-video-lines */ - VIDEO_TYPE_VGAC, /* orig-video-isVGA */ - 16 /* orig-video-points */ - }; -#elif defined(CONFIG_DUMMY_CONSOLE) - conswitchp = &dummy_con; -#endif -#endif -} diff --git a/arch/mips/lemote/lm2e/time.c b/arch/mips/lemote/lm2e/time.c deleted file mode 100644 index b13d171..0000000 --- a/arch/mips/lemote/lm2e/time.c +++ /dev/null @@ -1,27 +0,0 @@ -/* - * Copyright (C) 2007 Lemote, Inc. & Institute of Computing Technology - * Author: Fuxin Zhang, zhangfx@lemote.com - * - * Copyright (C) 2009 Lemote Inc. & Insititute of Computing Technology - * Author: Wu Zhangjin, wuzj@lemote.com - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ -#include -#include - -#include - -void __init plat_time_init(void) -{ - /* setup mips r4k timer */ - mips_hpt_frequency = cpu_clock_freq / 2; -} - -unsigned long read_persistent_clock(void) -{ - return mc146818_get_cmos_time(); -} diff --git a/arch/mips/loongson/fuloong-2e/Makefile b/arch/mips/loongson/fuloong-2e/Makefile new file mode 100644 index 0000000..feb1d6b --- /dev/null +++ b/arch/mips/loongson/fuloong-2e/Makefile @@ -0,0 +1,13 @@ +# +# Makefile for Lemote Fuloong2e mini-PC board. +# + +obj-y += setup.o init.o reset.o irq.o pci.o bonito-irq.o mem.o \ + env.o cmdline.o time.o machtype.o + +# +# Early printk support +# +obj-$(CONFIG_EARLY_PRINTK) += early_printk.o + +EXTRA_CFLAGS += -Werror diff --git a/arch/mips/loongson/fuloong-2e/bonito-irq.c b/arch/mips/loongson/fuloong-2e/bonito-irq.c new file mode 100644 index 0000000..3e31e7a --- /dev/null +++ b/arch/mips/loongson/fuloong-2e/bonito-irq.c @@ -0,0 +1,51 @@ +/* + * Copyright 2001 MontaVista Software Inc. + * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net + * Copyright (C) 2000, 2001 Ralf Baechle (ralf@gnu.org) + * + * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology + * Author: Fuxin Zhang, zhangfx@lemote.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ +#include + +#include + +static inline void bonito_irq_enable(unsigned int irq) +{ + BONITO_INTENSET = (1 << (irq - BONITO_IRQ_BASE)); + mmiowb(); +} + +static inline void bonito_irq_disable(unsigned int irq) +{ + BONITO_INTENCLR = (1 << (irq - BONITO_IRQ_BASE)); + mmiowb(); +} + +static struct irq_chip bonito_irq_type = { + .name = "bonito_irq", + .ack = bonito_irq_disable, + .mask = bonito_irq_disable, + .mask_ack = bonito_irq_disable, + .unmask = bonito_irq_enable, +}; + +static struct irqaction dma_timeout_irqaction = { + .handler = no_action, + .name = "dma_timeout", +}; + +void bonito_irq_init(void) +{ + u32 i; + + for (i = BONITO_IRQ_BASE; i < BONITO_IRQ_BASE + 32; i++) + set_irq_chip_and_handler(i, &bonito_irq_type, handle_level_irq); + + setup_irq(BONITO_IRQ_BASE + 10, &dma_timeout_irqaction); +} diff --git a/arch/mips/loongson/fuloong-2e/cmdline.c b/arch/mips/loongson/fuloong-2e/cmdline.c new file mode 100644 index 0000000..75f1b24 --- /dev/null +++ b/arch/mips/loongson/fuloong-2e/cmdline.c @@ -0,0 +1,52 @@ +/* + * Based on Ocelot Linux port, which is + * Copyright 2001 MontaVista Software Inc. + * Author: jsun@mvista.com or jsun@junsun.net + * + * Copyright 2003 ICT CAS + * Author: Michael Guo + * + * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology + * Author: Fuxin Zhang, zhangfx@lemote.com + * + * Copyright (C) 2009 Lemote Inc. & Insititute of Computing Technology + * Author: Wu Zhangjin, wuzj@lemote.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ +#include + +#include + +int prom_argc; +/* pmon passes arguments in 32bit pointers */ +int *_prom_argv; + +void __init prom_init_cmdline(void) +{ + int i; + long l; + + /* firmware arguments are initialized in head.S */ + prom_argc = fw_arg0; + _prom_argv = (int *)fw_arg1; + + /* arg[0] is "g", the rest is boot parameters */ + arcs_cmdline[0] = '\0'; + for (i = 1; i < prom_argc; i++) { + l = (long)_prom_argv[i]; + if (strlen(arcs_cmdline) + strlen(((char *)l) + 1) + >= sizeof(arcs_cmdline)) + break; + strcat(arcs_cmdline, ((char *)l)); + strcat(arcs_cmdline, " "); + } + + if ((strstr(arcs_cmdline, "console=")) == NULL) + strcat(arcs_cmdline, " console=ttyS0,115200"); + if ((strstr(arcs_cmdline, "root=")) == NULL) + strcat(arcs_cmdline, " root=/dev/hda1"); +} diff --git a/arch/mips/loongson/fuloong-2e/early_printk.c b/arch/mips/loongson/fuloong-2e/early_printk.c new file mode 100644 index 0000000..3e0a6ea --- /dev/null +++ b/arch/mips/loongson/fuloong-2e/early_printk.c @@ -0,0 +1,39 @@ +/* early printk support + * + * Copyright (c) 2009 Philippe Vachon + * Copyright (C) 2009 Lemote Inc. & Insititute of Computing Technology + * Author: Wu Zhangjin, wuzj@lemote.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ +#include + +#include + +#define UART_BASE (BONITO_PCIIO_BASE + 0x3f8) + +#define PORT(base, offset) (u8 *)(base + offset) + +static inline unsigned int serial_in(phys_addr_t base, int offset) +{ + return readb(PORT(base, offset)); +} + +static inline void serial_out(phys_addr_t base, int offset, int value) +{ + writeb(value, PORT(base, offset)); +} + +void prom_putchar(char c) +{ + phys_addr_t uart_base = + (phys_addr_t) ioremap_nocache(UART_BASE, 8); + + while ((serial_in(uart_base, UART_LSR) & UART_LSR_THRE) == 0) + ; + + serial_out(uart_base, UART_TX, c); +} diff --git a/arch/mips/loongson/fuloong-2e/env.c b/arch/mips/loongson/fuloong-2e/env.c new file mode 100644 index 0000000..b9ef503 --- /dev/null +++ b/arch/mips/loongson/fuloong-2e/env.c @@ -0,0 +1,58 @@ +/* + * Based on Ocelot Linux port, which is + * Copyright 2001 MontaVista Software Inc. + * Author: jsun@mvista.com or jsun@junsun.net + * + * Copyright 2003 ICT CAS + * Author: Michael Guo + * + * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology + * Author: Fuxin Zhang, zhangfx@lemote.com + * + * Copyright (C) 2009 Lemote Inc. & Insititute of Computing Technology + * Author: Wu Zhangjin, wuzj@lemote.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ +#include + +#include + +unsigned long bus_clock, cpu_clock_freq; +unsigned long memsize, highmemsize; + +/* pmon passes arguments in 32bit pointers */ +int *_prom_envp; + +#define parse_even_earlier(res, option, p) \ +do { \ + if (strncmp(option, (char *)p, strlen(option)) == 0) \ + strict_strtol((char *)p + strlen(option"="), \ + 10, &res); \ +} while (0) + +void __init prom_init_env(void) +{ + long l; + + /* firmware arguments are initialized in head.S */ + _prom_envp = (int *)fw_arg2; + + l = (long)*_prom_envp; + while (l != 0) { + parse_even_earlier(bus_clock, "busclock", l); + parse_even_earlier(cpu_clock_freq, "cpuclock", l); + parse_even_earlier(memsize, "memsize", l); + parse_even_earlier(highmemsize, "highmemsize", l); + _prom_envp++; + l = (long)*_prom_envp; + } + if (memsize == 0) + memsize = 256; + + pr_info("busclock=%ld, cpuclock=%ld, memsize=%ld, highmemsize=%ld\n", + bus_clock, cpu_clock_freq, memsize, highmemsize); +} diff --git a/arch/mips/loongson/fuloong-2e/init.c b/arch/mips/loongson/fuloong-2e/init.c new file mode 100644 index 0000000..3abe927 --- /dev/null +++ b/arch/mips/loongson/fuloong-2e/init.c @@ -0,0 +1,30 @@ +/* + * Copyright (C) 2009 Lemote Inc. & Insititute of Computing Technology + * Author: Wu Zhangjin, wuzj@lemote.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include + +#include + +#include + +void __init prom_init(void) +{ + /* init base address of io space */ + set_io_port_base((unsigned long) + ioremap(BONITO_PCIIO_BASE, BONITO_PCIIO_SIZE)); + + prom_init_cmdline(); + prom_init_env(); + prom_init_memory(); +} + +void __init prom_free_prom_memory(void) +{ +} diff --git a/arch/mips/loongson/fuloong-2e/irq.c b/arch/mips/loongson/fuloong-2e/irq.c new file mode 100644 index 0000000..9585f5a --- /dev/null +++ b/arch/mips/loongson/fuloong-2e/irq.c @@ -0,0 +1,111 @@ +/* + * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology + * Author: Fuxin Zhang, zhangfx@lemote.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ +#include +#include + +#include +#include + +#include +/* + * the first level int-handler will jump here if it is a bonito irq + */ +static void bonito_irqdispatch(void) +{ + u32 int_status; + int i; + + /* workaround the IO dma problem: let cpu looping to allow DMA finish */ + int_status = BONITO_INTISR; + if (int_status & (1 << 10)) { + while (int_status & (1 << 10)) { + udelay(1); + int_status = BONITO_INTISR; + } + } + + /* Get pending sources, masked by current enables */ + int_status = BONITO_INTISR & BONITO_INTEN; + + if (int_status != 0) { + i = __ffs(int_status); + int_status &= ~(1 << i); + do_IRQ(BONITO_IRQ_BASE + i); + } +} + +static void i8259_irqdispatch(void) +{ + int irq; + + irq = i8259_irq(); + if (irq >= 0) + do_IRQ(irq); + else + spurious_interrupt(); +} + +asmlinkage void plat_irq_dispatch(void) +{ + unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM; + + if (pending & CAUSEF_IP7) + do_IRQ(MIPS_CPU_IRQ_BASE + 7); + else if (pending & CAUSEF_IP6) /* perf counter loverflow */ + do_IRQ(LOONGSON2_PERFCNT_IRQ); + else if (pending & CAUSEF_IP5) + i8259_irqdispatch(); + else if (pending & CAUSEF_IP2) + bonito_irqdispatch(); + else + spurious_interrupt(); +} + +static struct irqaction cascade_irqaction = { + .handler = no_action, + .name = "cascade", +}; + +void __init arch_init_irq(void) +{ + /* + * Clear all of the interrupts while we change the able around a bit. + * int-handler is not on bootstrap + */ + clear_c0_status(ST0_IM | ST0_BEV); + local_irq_disable(); + + /* most bonito irq should be level triggered */ + BONITO_INTEDGE = BONITO_ICU_SYSTEMERR | BONITO_ICU_MASTERERR | + BONITO_ICU_RETRYERR | BONITO_ICU_MBOXES; + BONITO_INTSTEER = 0; + + /* + * Mask out all interrupt by writing "1" to all bit position in + * the interrupt reset reg. + */ + BONITO_INTENCLR = ~0; + + /* init all controller + * 0-15 ------> i8259 interrupt + * 16-23 ------> mips cpu interrupt + * 32-63 ------> bonito irq + */ + + /* Sets the first-level interrupt dispatcher. */ + mips_cpu_irq_init(); + init_i8259_irqs(); + bonito_irq_init(); + + /* bonito irq at IP2 */ + setup_irq(MIPS_CPU_IRQ_BASE + 2, &cascade_irqaction); + /* 8259 irq at IP5 */ + setup_irq(MIPS_CPU_IRQ_BASE + 5, &cascade_irqaction); +} diff --git a/arch/mips/loongson/fuloong-2e/machtype.c b/arch/mips/loongson/fuloong-2e/machtype.c new file mode 100644 index 0000000..e03aa0d --- /dev/null +++ b/arch/mips/loongson/fuloong-2e/machtype.c @@ -0,0 +1,15 @@ +/* + * Copyright (C) 2009 Lemote Inc. & Insititute of Computing Technology + * Author: Wu Zhangjin, wuzj@lemote.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +const char *get_system_type(void) +{ + return "lemote-fuloong-2e-box"; +} + diff --git a/arch/mips/loongson/fuloong-2e/mem.c b/arch/mips/loongson/fuloong-2e/mem.c new file mode 100644 index 0000000..6a7feb1 --- /dev/null +++ b/arch/mips/loongson/fuloong-2e/mem.c @@ -0,0 +1,36 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ +#include +#include +#include + +#include + +#include + +void __init prom_init_memory(void) +{ + add_memory_region(0x0, (memsize << 20), BOOT_MEM_RAM); +#ifdef CONFIG_64BIT + if (highmemsize > 0) + add_memory_region(0x20000000, highmemsize << 20, BOOT_MEM_RAM); +#endif /* CONFIG_64BIT */ +} + +/* override of arch/mips/mm/cache.c: __uncached_access */ +int __uncached_access(struct file *file, unsigned long addr) +{ + if (file->f_flags & O_SYNC) + return 1; + + /* + * On the Lemote Loongson 2e system, the peripheral registers + * reside between 0x1000:0000 and 0x2000:0000. + */ + return addr >= __pa(high_memory) || + ((addr >= 0x10000000) && (addr < 0x20000000)); +} diff --git a/arch/mips/loongson/fuloong-2e/pci.c b/arch/mips/loongson/fuloong-2e/pci.c new file mode 100644 index 0000000..9812c30 --- /dev/null +++ b/arch/mips/loongson/fuloong-2e/pci.c @@ -0,0 +1,83 @@ +/* + * Copyright (C) 2007 Lemote, Inc. & Institute of Computing Technology + * Author: Fuxin Zhang, zhangfx@lemote.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ +#include + +#include +#include + +static struct resource loongson2e_pci_mem_resource = { + .name = "LOONGSON2E PCI MEM", + .start = LOONGSON2E_PCI_MEM_START, + .end = LOONGSON2E_PCI_MEM_END, + .flags = IORESOURCE_MEM, +}; + +static struct resource loongson2e_pci_io_resource = { + .name = "LOONGSON2E PCI IO MEM", + .start = LOONGSON2E_PCI_IO_START, + .end = IO_SPACE_LIMIT, + .flags = IORESOURCE_IO, +}; + +static struct pci_controller loongson2e_pci_controller = { + .pci_ops = &bonito64_pci_ops, + .io_resource = &loongson2e_pci_io_resource, + .mem_resource = &loongson2e_pci_mem_resource, + .mem_offset = 0x00000000UL, + .io_offset = 0x00000000UL, +}; + +static void __init setup_pcimap(void) +{ + /* + * local to PCI mapping for CPU accessing PCI space + * CPU address space [256M,448M] is window for accessing pci space + * we set pcimap_lo[0,1,2] to map it to pci space[0M,64M], [320M,448M] + * + * pcimap: PCI_MAP2 PCI_Mem_Lo2 PCI_Mem_Lo1 PCI_Mem_Lo0 + * [<2G] [384M,448M] [320M,384M] [0M,64M] + */ + BONITO_PCIMAP = BONITO_PCIMAP_PCIMAP_2 | + BONITO_PCIMAP_WIN(2, BONITO_PCILO2_BASE) | + BONITO_PCIMAP_WIN(1, BONITO_PCILO1_BASE) | + BONITO_PCIMAP_WIN(0, 0); + + /* + * PCI-DMA to local mapping: [2G,2G+256M] -> [0M,256M] + */ + BONITO_PCIBASE0 = 0x80000000ul; /* base: 2G -> mmap: 0M */ + /* size: 256M, burst transmission, pre-fetch enable, 64bit */ + LOONGSON_PCI_HIT0_SEL_L = 0xc000000cul; + LOONGSON_PCI_HIT0_SEL_H = 0xfffffffful; + LOONGSON_PCI_HIT1_SEL_L = 0x00000006ul; /* set this BAR as invalid */ + LOONGSON_PCI_HIT1_SEL_H = 0x00000000ul; + LOONGSON_PCI_HIT2_SEL_L = 0x00000006ul; /* set this BAR as invalid */ + LOONGSON_PCI_HIT2_SEL_H = 0x00000000ul; + + /* avoid deadlock of PCI reading/writing lock operation */ + LOONGSON_PCI_ISR4C = 0xd2000001ul; + + /* can not change gnt to break pci transfer when device's gnt not + deassert for some broken device */ + LOONGSON_PXARB_CFG = 0x00fe0105ul; +} + +static int __init pcibios_init(void) +{ + setup_pcimap(); + + loongson2e_pci_controller.io_map_base = mips_io_port_base; + + register_pci_controller(&loongson2e_pci_controller); + + return 0; +} + +arch_initcall(pcibios_init); diff --git a/arch/mips/loongson/fuloong-2e/reset.c b/arch/mips/loongson/fuloong-2e/reset.c new file mode 100644 index 0000000..d89c9e4 --- /dev/null +++ b/arch/mips/loongson/fuloong-2e/reset.c @@ -0,0 +1,39 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * Copyright (C) 2007 Lemote, Inc. & Institute of Computing Technology + * Author: Fuxin Zhang, zhangfx@lemote.com + * Copyright (C) 2009 Lemote, Inc. & Institute of Computing Technology + * Author: Zhangjin Wu, wuzj@lemote.com + */ +#include + +#include + +#include + +static void loongson2e_restart(char *command) +{ + /* do preparation for reboot */ + BONITO_BONGENCFG &= ~(1 << 2); + BONITO_BONGENCFG |= (1 << 2); + + /* reboot via jumping to boot base address */ + ((void (*)(void))ioremap_nocache(BONITO_BOOT_BASE, 4)) (); +} + +static void loongson2e_halt(void) +{ + while (1) + ; +} + +void mips_reboot_setup(void) +{ + _machine_restart = loongson2e_restart; + _machine_halt = loongson2e_halt; + pm_power_off = loongson2e_halt; +} diff --git a/arch/mips/loongson/fuloong-2e/setup.c b/arch/mips/loongson/fuloong-2e/setup.c new file mode 100644 index 0000000..655695c --- /dev/null +++ b/arch/mips/loongson/fuloong-2e/setup.c @@ -0,0 +1,60 @@ +/* + * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology + * Author: Fuxin Zhang, zhangfx@lemote.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ +#include + +#include + +#include + +#ifdef CONFIG_VT +#include +#include +#endif + +void (*__wbflush)(void); +EXPORT_SYMBOL(__wbflush); + +static void wbflush_loongson2e(void) +{ + asm(".set\tpush\n\t" + ".set\tnoreorder\n\t" + ".set mips3\n\t" + "sync\n\t" + "nop\n\t" + ".set\tpop\n\t" + ".set mips0\n\t"); +} + +void __init plat_mem_setup(void) +{ + mips_reboot_setup(); + + __wbflush = wbflush_loongson2e; + +#ifdef CONFIG_VT +#if defined(CONFIG_VGA_CONSOLE) + conswitchp = &vga_con; + + screen_info = (struct screen_info) { + 0, 25, /* orig-x, orig-y */ + 0, /* unused */ + 0, /* orig-video-page */ + 0, /* orig-video-mode */ + 80, /* orig-video-cols */ + 0, 0, 0, /* ega_ax, ega_bx, ega_cx */ + 25, /* orig-video-lines */ + VIDEO_TYPE_VGAC, /* orig-video-isVGA */ + 16 /* orig-video-points */ + }; +#elif defined(CONFIG_DUMMY_CONSOLE) + conswitchp = &dummy_con; +#endif +#endif +} diff --git a/arch/mips/loongson/fuloong-2e/time.c b/arch/mips/loongson/fuloong-2e/time.c new file mode 100644 index 0000000..b13d171 --- /dev/null +++ b/arch/mips/loongson/fuloong-2e/time.c @@ -0,0 +1,27 @@ +/* + * Copyright (C) 2007 Lemote, Inc. & Institute of Computing Technology + * Author: Fuxin Zhang, zhangfx@lemote.com + * + * Copyright (C) 2009 Lemote Inc. & Insititute of Computing Technology + * Author: Wu Zhangjin, wuzj@lemote.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ +#include +#include + +#include + +void __init plat_time_init(void) +{ + /* setup mips r4k timer */ + mips_hpt_frequency = cpu_clock_freq / 2; +} + +unsigned long read_persistent_clock(void) +{ + return mc146818_get_cmos_time(); +} diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile index e8a97f5..1c66fc0 100644 --- a/arch/mips/pci/Makefile +++ b/arch/mips/pci/Makefile @@ -26,7 +26,7 @@ obj-$(CONFIG_MIPS_COBALT) += fixup-cobalt.o obj-$(CONFIG_SOC_AU1500) += fixup-au1000.o ops-au1000.o obj-$(CONFIG_SOC_AU1550) += fixup-au1000.o ops-au1000.o obj-$(CONFIG_SOC_PNX8550) += fixup-pnx8550.o ops-pnx8550.o -obj-$(CONFIG_LEMOTE_FULONG) += fixup-lm2e.o ops-bonito64.o +obj-$(CONFIG_LEMOTE_FULOONG2E) += fixup-fuloong2e.o ops-bonito64.o obj-$(CONFIG_MIPS_MALTA) += fixup-malta.o obj-$(CONFIG_PMC_MSP7120_GW) += fixup-pmcmsp.o ops-pmcmsp.o obj-$(CONFIG_PMC_MSP7120_EVAL) += fixup-pmcmsp.o ops-pmcmsp.o diff --git a/arch/mips/pci/fixup-fuloong2e.c b/arch/mips/pci/fixup-fuloong2e.c new file mode 100644 index 0000000..0c4c7a8 --- /dev/null +++ b/arch/mips/pci/fixup-fuloong2e.c @@ -0,0 +1,224 @@ +/* + * Copyright (C) 2004 ICT CAS + * Author: Li xiaoyu, ICT CAS + * lixy@ict.ac.cn + * + * Copyright (C) 2007 Lemote, Inc. & Institute of Computing Technology + * Author: Fuxin Zhang, zhangfx@lemote.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ +#include +#include +#include + +/* South bridge slot number is set by the pci probe process */ +static u8 sb_slot = 5; + +int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) +{ + int irq = 0; + + if (slot == sb_slot) { + switch (PCI_FUNC(dev->devfn)) { + case 2: + irq = 10; + break; + case 3: + irq = 11; + break; + case 5: + irq = 9; + break; + } + } else { + irq = BONITO_IRQ_BASE + 25 + pin; + } + return irq; + +} + +/* Do platform specific device initialization at pci_enable_device() time */ +int pcibios_plat_dev_init(struct pci_dev *dev) +{ + return 0; +} + +static void __init loongson2e_nec_fixup(struct pci_dev *pdev) +{ + unsigned int val; + + /* Configues port 1, 2, 3, 4 to be validate*/ + pci_read_config_dword(pdev, 0xe0, &val); + pci_write_config_dword(pdev, 0xe0, (val & ~7) | 0x4); + + /* System clock is 48-MHz Oscillator. */ + pci_write_config_dword(pdev, 0xe4, 1 << 5); +} + +static void __init loongson2e_686b_func0_fixup(struct pci_dev *pdev) +{ + unsigned char c; + + sb_slot = PCI_SLOT(pdev->devfn); + + printk(KERN_INFO "via686b fix: ISA bridge\n"); + + /* Enable I/O Recovery time */ + pci_write_config_byte(pdev, 0x40, 0x08); + + /* Enable ISA refresh */ + pci_write_config_byte(pdev, 0x41, 0x01); + + /* disable ISA line buffer */ + pci_write_config_byte(pdev, 0x45, 0x00); + + /* Gate INTR, and flush line buffer */ + pci_write_config_byte(pdev, 0x46, 0xe0); + + /* Disable PCI Delay Transaction, Enable EISA ports 4D0/4D1. */ + /* pci_write_config_byte(pdev, 0x47, 0x20); */ + + /* + * enable PCI Delay Transaction, Enable EISA ports 4D0/4D1. + * enable time-out timer + */ + pci_write_config_byte(pdev, 0x47, 0xe6); + + /* + * enable level trigger on pci irqs: 9,10,11,13 + * important! without this PCI interrupts won't work + */ + outb(0x2e, 0x4d1); + + /* 512 K PCI Decode */ + pci_write_config_byte(pdev, 0x48, 0x01); + + /* Wait for PGNT before grant to ISA Master/DMA */ + pci_write_config_byte(pdev, 0x4a, 0x84); + + /* + * Plug'n'Play + * + * Parallel DRQ 3, Floppy DRQ 2 (default) + */ + pci_write_config_byte(pdev, 0x50, 0x0e); + + /* + * IRQ Routing for Floppy and Parallel port + * + * IRQ 6 for floppy, IRQ 7 for parallel port + */ + pci_write_config_byte(pdev, 0x51, 0x76); + + /* IRQ Routing for serial ports (take IRQ 3 and 4) */ + pci_write_config_byte(pdev, 0x52, 0x34); + + /* All IRQ's level triggered. */ + pci_write_config_byte(pdev, 0x54, 0x00); + + /* route PIRQA-D irq */ + pci_write_config_byte(pdev, 0x55, 0x90); /* bit 7-4, PIRQA */ + pci_write_config_byte(pdev, 0x56, 0xba); /* bit 7-4, PIRQC; */ + /* 3-0, PIRQB */ + pci_write_config_byte(pdev, 0x57, 0xd0); /* bit 7-4, PIRQD */ + + /* enable function 5/6, audio/modem */ + pci_read_config_byte(pdev, 0x85, &c); + c &= ~(0x3 << 2); + pci_write_config_byte(pdev, 0x85, c); + + printk(KERN_INFO"via686b fix: ISA bridge done\n"); +} + +static void __init loongson2e_686b_func1_fixup(struct pci_dev *pdev) +{ + printk(KERN_INFO"via686b fix: IDE\n"); + + /* Modify IDE controller setup */ + pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 48); + pci_write_config_byte(pdev, PCI_COMMAND, + PCI_COMMAND_IO | PCI_COMMAND_MEMORY | + PCI_COMMAND_MASTER); + pci_write_config_byte(pdev, 0x40, 0x0b); + /* legacy mode */ + pci_write_config_byte(pdev, 0x42, 0x09); + +#if 1/* play safe, otherwise we may see notebook's usb keyboard lockup */ + /* disable read prefetch/write post buffers */ + pci_write_config_byte(pdev, 0x41, 0x02); + + /* use 3/4 as fifo thresh hold */ + pci_write_config_byte(pdev, 0x43, 0x0a); + pci_write_config_byte(pdev, 0x44, 0x00); + + pci_write_config_byte(pdev, 0x45, 0x00); +#else + pci_write_config_byte(pdev, 0x41, 0xc2); + pci_write_config_byte(pdev, 0x43, 0x35); + pci_write_config_byte(pdev, 0x44, 0x1c); + + pci_write_config_byte(pdev, 0x45, 0x10); +#endif + + printk(KERN_INFO"via686b fix: IDE done\n"); +} + +static void __init loongson2e_686b_func2_fixup(struct pci_dev *pdev) +{ + /* irq routing */ + pci_write_config_byte(pdev, PCI_INTERRUPT_LINE, 10); +} + +static void __init loongson2e_686b_func3_fixup(struct pci_dev *pdev) +{ + /* irq routing */ + pci_write_config_byte(pdev, PCI_INTERRUPT_LINE, 11); +} + +static void __init loongson2e_686b_func5_fixup(struct pci_dev *pdev) +{ + unsigned int val; + unsigned char c; + + /* enable IO */ + pci_write_config_byte(pdev, PCI_COMMAND, + PCI_COMMAND_IO | PCI_COMMAND_MEMORY | + PCI_COMMAND_MASTER); + pci_read_config_dword(pdev, 0x4, &val); + pci_write_config_dword(pdev, 0x4, val | 1); + + /* route ac97 IRQ */ + pci_write_config_byte(pdev, 0x3c, 9); + + pci_read_config_byte(pdev, 0x8, &c); + + /* link control: enable link & SGD PCM output */ + pci_write_config_byte(pdev, 0x41, 0xcc); + + /* disable game port, FM, midi, sb, enable write to reg2c-2f */ + pci_write_config_byte(pdev, 0x42, 0x20); + + /* we are using Avance logic codec */ + pci_write_config_word(pdev, 0x2c, 0x1005); + pci_write_config_word(pdev, 0x2e, 0x4710); + pci_read_config_dword(pdev, 0x2c, &val); + + pci_write_config_byte(pdev, 0x42, 0x0); +} + +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, + loongson2e_686b_func0_fixup); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1, + loongson2e_686b_func1_fixup); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_2, + loongson2e_686b_func2_fixup); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, + loongson2e_686b_func3_fixup); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_5, + loongson2e_686b_func5_fixup); +DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_USB, + loongson2e_nec_fixup); diff --git a/arch/mips/pci/fixup-lm2e.c b/arch/mips/pci/fixup-lm2e.c deleted file mode 100644 index 0c4c7a8..0000000 --- a/arch/mips/pci/fixup-lm2e.c +++ /dev/null @@ -1,224 +0,0 @@ -/* - * Copyright (C) 2004 ICT CAS - * Author: Li xiaoyu, ICT CAS - * lixy@ict.ac.cn - * - * Copyright (C) 2007 Lemote, Inc. & Institute of Computing Technology - * Author: Fuxin Zhang, zhangfx@lemote.com - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ -#include -#include -#include - -/* South bridge slot number is set by the pci probe process */ -static u8 sb_slot = 5; - -int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) -{ - int irq = 0; - - if (slot == sb_slot) { - switch (PCI_FUNC(dev->devfn)) { - case 2: - irq = 10; - break; - case 3: - irq = 11; - break; - case 5: - irq = 9; - break; - } - } else { - irq = BONITO_IRQ_BASE + 25 + pin; - } - return irq; - -} - -/* Do platform specific device initialization at pci_enable_device() time */ -int pcibios_plat_dev_init(struct pci_dev *dev) -{ - return 0; -} - -static void __init loongson2e_nec_fixup(struct pci_dev *pdev) -{ - unsigned int val; - - /* Configues port 1, 2, 3, 4 to be validate*/ - pci_read_config_dword(pdev, 0xe0, &val); - pci_write_config_dword(pdev, 0xe0, (val & ~7) | 0x4); - - /* System clock is 48-MHz Oscillator. */ - pci_write_config_dword(pdev, 0xe4, 1 << 5); -} - -static void __init loongson2e_686b_func0_fixup(struct pci_dev *pdev) -{ - unsigned char c; - - sb_slot = PCI_SLOT(pdev->devfn); - - printk(KERN_INFO "via686b fix: ISA bridge\n"); - - /* Enable I/O Recovery time */ - pci_write_config_byte(pdev, 0x40, 0x08); - - /* Enable ISA refresh */ - pci_write_config_byte(pdev, 0x41, 0x01); - - /* disable ISA line buffer */ - pci_write_config_byte(pdev, 0x45, 0x00); - - /* Gate INTR, and flush line buffer */ - pci_write_config_byte(pdev, 0x46, 0xe0); - - /* Disable PCI Delay Transaction, Enable EISA ports 4D0/4D1. */ - /* pci_write_config_byte(pdev, 0x47, 0x20); */ - - /* - * enable PCI Delay Transaction, Enable EISA ports 4D0/4D1. - * enable time-out timer - */ - pci_write_config_byte(pdev, 0x47, 0xe6); - - /* - * enable level trigger on pci irqs: 9,10,11,13 - * important! without this PCI interrupts won't work - */ - outb(0x2e, 0x4d1); - - /* 512 K PCI Decode */ - pci_write_config_byte(pdev, 0x48, 0x01); - - /* Wait for PGNT before grant to ISA Master/DMA */ - pci_write_config_byte(pdev, 0x4a, 0x84); - - /* - * Plug'n'Play - * - * Parallel DRQ 3, Floppy DRQ 2 (default) - */ - pci_write_config_byte(pdev, 0x50, 0x0e); - - /* - * IRQ Routing for Floppy and Parallel port - * - * IRQ 6 for floppy, IRQ 7 for parallel port - */ - pci_write_config_byte(pdev, 0x51, 0x76); - - /* IRQ Routing for serial ports (take IRQ 3 and 4) */ - pci_write_config_byte(pdev, 0x52, 0x34); - - /* All IRQ's level triggered. */ - pci_write_config_byte(pdev, 0x54, 0x00); - - /* route PIRQA-D irq */ - pci_write_config_byte(pdev, 0x55, 0x90); /* bit 7-4, PIRQA */ - pci_write_config_byte(pdev, 0x56, 0xba); /* bit 7-4, PIRQC; */ - /* 3-0, PIRQB */ - pci_write_config_byte(pdev, 0x57, 0xd0); /* bit 7-4, PIRQD */ - - /* enable function 5/6, audio/modem */ - pci_read_config_byte(pdev, 0x85, &c); - c &= ~(0x3 << 2); - pci_write_config_byte(pdev, 0x85, c); - - printk(KERN_INFO"via686b fix: ISA bridge done\n"); -} - -static void __init loongson2e_686b_func1_fixup(struct pci_dev *pdev) -{ - printk(KERN_INFO"via686b fix: IDE\n"); - - /* Modify IDE controller setup */ - pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 48); - pci_write_config_byte(pdev, PCI_COMMAND, - PCI_COMMAND_IO | PCI_COMMAND_MEMORY | - PCI_COMMAND_MASTER); - pci_write_config_byte(pdev, 0x40, 0x0b); - /* legacy mode */ - pci_write_config_byte(pdev, 0x42, 0x09); - -#if 1/* play safe, otherwise we may see notebook's usb keyboard lockup */ - /* disable read prefetch/write post buffers */ - pci_write_config_byte(pdev, 0x41, 0x02); - - /* use 3/4 as fifo thresh hold */ - pci_write_config_byte(pdev, 0x43, 0x0a); - pci_write_config_byte(pdev, 0x44, 0x00); - - pci_write_config_byte(pdev, 0x45, 0x00); -#else - pci_write_config_byte(pdev, 0x41, 0xc2); - pci_write_config_byte(pdev, 0x43, 0x35); - pci_write_config_byte(pdev, 0x44, 0x1c); - - pci_write_config_byte(pdev, 0x45, 0x10); -#endif - - printk(KERN_INFO"via686b fix: IDE done\n"); -} - -static void __init loongson2e_686b_func2_fixup(struct pci_dev *pdev) -{ - /* irq routing */ - pci_write_config_byte(pdev, PCI_INTERRUPT_LINE, 10); -} - -static void __init loongson2e_686b_func3_fixup(struct pci_dev *pdev) -{ - /* irq routing */ - pci_write_config_byte(pdev, PCI_INTERRUPT_LINE, 11); -} - -static void __init loongson2e_686b_func5_fixup(struct pci_dev *pdev) -{ - unsigned int val; - unsigned char c; - - /* enable IO */ - pci_write_config_byte(pdev, PCI_COMMAND, - PCI_COMMAND_IO | PCI_COMMAND_MEMORY | - PCI_COMMAND_MASTER); - pci_read_config_dword(pdev, 0x4, &val); - pci_write_config_dword(pdev, 0x4, val | 1); - - /* route ac97 IRQ */ - pci_write_config_byte(pdev, 0x3c, 9); - - pci_read_config_byte(pdev, 0x8, &c); - - /* link control: enable link & SGD PCM output */ - pci_write_config_byte(pdev, 0x41, 0xcc); - - /* disable game port, FM, midi, sb, enable write to reg2c-2f */ - pci_write_config_byte(pdev, 0x42, 0x20); - - /* we are using Avance logic codec */ - pci_write_config_word(pdev, 0x2c, 0x1005); - pci_write_config_word(pdev, 0x2e, 0x4710); - pci_read_config_dword(pdev, 0x2c, &val); - - pci_write_config_byte(pdev, 0x42, 0x0); -} - -DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, - loongson2e_686b_func0_fixup); -DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_1, - loongson2e_686b_func1_fixup); -DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_2, - loongson2e_686b_func2_fixup); -DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, - loongson2e_686b_func3_fixup); -DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_5, - loongson2e_686b_func5_fixup); -DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_USB, - loongson2e_nec_fixup); diff --git a/arch/mips/pci/ops-bonito64.c b/arch/mips/pci/ops-bonito64.c index f742c51..54e55e7 100644 --- a/arch/mips/pci/ops-bonito64.c +++ b/arch/mips/pci/ops-bonito64.c @@ -29,7 +29,7 @@ #define PCI_ACCESS_READ 0 #define PCI_ACCESS_WRITE 1 -#ifdef CONFIG_LEMOTE_FULONG +#ifdef CONFIG_LEMOTE_FULOONG2E #define CFG_SPACE_REG(offset) (void *)CKSEG1ADDR(BONITO_PCICFG_BASE | (offset)) #define ID_SEL_BEGIN 11 #else @@ -77,7 +77,7 @@ static int bonito64_pcibios_config_access(unsigned char access_type, addrp = CFG_SPACE_REG(addr & 0xffff); if (access_type == PCI_ACCESS_WRITE) { writel(cpu_to_le32(*data), addrp); -#ifndef CONFIG_LEMOTE_FULONG +#ifndef CONFIG_LEMOTE_FULOONG2E /* Wait till done */ while (BONITO_PCIMSTAT & 0xF); #endif -- 1.6.2.1 From wuzhangjin@gmail.com Thu Jul 2 17:32:50 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 02 Jul 2009 17:32:55 +0200 (CEST) Received: from mail-ew0-f214.google.com ([209.85.219.214]:62210 "EHLO mail-ew0-f214.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492206AbZGBPcu (ORCPT ); Thu, 2 Jul 2009 17:32:50 +0200 Received: by ewy10 with SMTP id 10so2101362ewy.0 for ; Thu, 02 Jul 2009 08:26:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer:in-reply-to:references; bh=3H0s2tjGTLguJKe30mloYFAFJl3iIS54xH8kVc/WMFE=; b=LscKf6C30I3JrvJlKWIqRn1lFXy/EyupQrPebHGeAuZ5oYFa+slply9zWn/zxognO5 H7Pd6FBCmMnKQzxm5B78x9soW5gB+GK33sj8cVmRrIy5K9byEMhRWOEws1l2N6xWjAay BiYUhdaNDo2QSO9Wmch9zNs+TPL4qj35HZKOQ= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; b=H+OHENP6ZVI9zZYzwsK3+H6lpc5oWUoeIeNgc4ZCTCkSGcbp2SZSIsnp6XXc8Q6FiJ DtTmlLHhZ1BowBh9llycwdy+EM1RO3gqmsd7+HnYk6rRCohhQDZdeYZK9Lwm1e6cW539 YgyKak87mfJ8d+2x3TP9EsHXbng/tulgB+Y7U= Received: by 10.211.179.6 with SMTP id g6mr1105368ebp.49.1246548419823; Thu, 02 Jul 2009 08:26:59 -0700 (PDT) Received: from localhost.localdomain ([222.92.8.142]) by mx.google.com with ESMTPS id 7sm2508516eyb.45.2009.07.02.08.26.52 (version=TLSv1/SSLv3 cipher=RC4-MD5); Thu, 02 Jul 2009 08:26:58 -0700 (PDT) From: Wu Zhangjin To: linux-kernel@vger.kernel.org, linux-mips@linux-mips.org, ralf@linux-mips.org Cc: Wu Zhangjin , Yan Hua , Philippe Vachon , Zhang Le , Zhang Fuxin , loongson-dev , Liu Junliang , Erwan Lerale , Arnaud Patard Subject: [PATCH v4 13/16] [loongson] split common loongson source code out Date: Thu, 2 Jul 2009 23:26:45 +0800 Message-Id: <988e19d2c2ed38b3f11d07dc4556707e7d02c5aa.1246546684.git.wuzhangjin@gmail.com> X-Mailer: git-send-email 1.6.2.1 In-Reply-To: References: Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23625 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips to share common loongson source code between all of the loongson-based machines. there is a need to split it out of the fuloong-2e/ directory. at the same time, other according tuning is needed. the machine-specific parts are defined as macros in relative header file, pci.h, mem.h, machine.h. Signed-off-by: Wu Zhangjin --- arch/mips/Kconfig | 32 +++------- arch/mips/Makefile | 7 +- arch/mips/include/asm/mach-loongson/loongson.h | 11 +++ arch/mips/include/asm/mach-loongson/machine.h | 22 ++++++ arch/mips/include/asm/mach-loongson/mem.h | 30 +++++++++ arch/mips/include/asm/mach-loongson/pci.h | 12 +++- arch/mips/loongson/Kconfig | 31 +++++++++ arch/mips/loongson/Makefile | 11 +++ arch/mips/loongson/common/Makefile | 11 +++ arch/mips/loongson/common/bonito-irq.c | 51 +++++++++++++++ arch/mips/loongson/common/cmdline.c | 52 +++++++++++++++ arch/mips/loongson/common/early_printk.c | 38 +++++++++++ arch/mips/loongson/common/env.c | 58 ++++++++++++++++ arch/mips/loongson/common/init.c | 30 +++++++++ arch/mips/loongson/common/irq.c | 74 +++++++++++++++++++++ arch/mips/loongson/common/machtype.c | 17 +++++ arch/mips/loongson/common/mem.c | 35 ++++++++++ arch/mips/loongson/common/pci.c | 83 ++++++++++++++++++++++++ arch/mips/loongson/common/reset.c | 39 +++++++++++ arch/mips/loongson/common/setup.c | 60 +++++++++++++++++ arch/mips/loongson/common/time.c | 27 ++++++++ arch/mips/loongson/fuloong-2e/Makefile | 8 +-- arch/mips/loongson/fuloong-2e/bonito-irq.c | 51 --------------- arch/mips/loongson/fuloong-2e/cmdline.c | 52 --------------- arch/mips/loongson/fuloong-2e/early_printk.c | 39 ----------- arch/mips/loongson/fuloong-2e/env.c | 58 ---------------- arch/mips/loongson/fuloong-2e/init.c | 30 --------- arch/mips/loongson/fuloong-2e/irq.c | 52 ++------------- arch/mips/loongson/fuloong-2e/machtype.c | 15 ---- arch/mips/loongson/fuloong-2e/mem.c | 36 ---------- arch/mips/loongson/fuloong-2e/pci.c | 83 ------------------------ arch/mips/loongson/fuloong-2e/reset.c | 31 ++------- arch/mips/loongson/fuloong-2e/setup.c | 60 ----------------- arch/mips/loongson/fuloong-2e/time.c | 27 -------- 34 files changed, 717 insertions(+), 556 deletions(-) create mode 100644 arch/mips/include/asm/mach-loongson/machine.h create mode 100644 arch/mips/include/asm/mach-loongson/mem.h create mode 100644 arch/mips/loongson/Kconfig create mode 100644 arch/mips/loongson/Makefile create mode 100644 arch/mips/loongson/common/Makefile create mode 100644 arch/mips/loongson/common/bonito-irq.c create mode 100644 arch/mips/loongson/common/cmdline.c create mode 100644 arch/mips/loongson/common/early_printk.c create mode 100644 arch/mips/loongson/common/env.c create mode 100644 arch/mips/loongson/common/init.c create mode 100644 arch/mips/loongson/common/irq.c create mode 100644 arch/mips/loongson/common/machtype.c create mode 100644 arch/mips/loongson/common/mem.c create mode 100644 arch/mips/loongson/common/pci.c create mode 100644 arch/mips/loongson/common/reset.c create mode 100644 arch/mips/loongson/common/setup.c create mode 100644 arch/mips/loongson/common/time.c delete mode 100644 arch/mips/loongson/fuloong-2e/bonito-irq.c delete mode 100644 arch/mips/loongson/fuloong-2e/cmdline.c delete mode 100644 arch/mips/loongson/fuloong-2e/early_printk.c delete mode 100644 arch/mips/loongson/fuloong-2e/env.c delete mode 100644 arch/mips/loongson/fuloong-2e/init.c delete mode 100644 arch/mips/loongson/fuloong-2e/machtype.c delete mode 100644 arch/mips/loongson/fuloong-2e/mem.c delete mode 100644 arch/mips/loongson/fuloong-2e/pci.c delete mode 100644 arch/mips/loongson/fuloong-2e/setup.c delete mode 100644 arch/mips/loongson/fuloong-2e/time.c diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 3414e23..482dcc3 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -174,30 +174,15 @@ config LASAT select SYS_SUPPORTS_64BIT_KERNEL if BROKEN select SYS_SUPPORTS_LITTLE_ENDIAN -config LEMOTE_FULOONG2E - bool "Lemote Fuloong2e mini-PC" - select ARCH_SPARSEMEM_ENABLE - select CEVT_R4K - select CSRC_R4K - select SYS_HAS_CPU_LOONGSON2 - select DMA_NONCOHERENT - select BOOT_ELF32 - select BOARD_SCACHE - select HAVE_STD_PC_SERIAL_PORT - select HW_HAS_PCI - select I8259 - select ISA - select IRQ_CPU - select SYS_SUPPORTS_32BIT_KERNEL - select SYS_SUPPORTS_64BIT_KERNEL - select SYS_SUPPORTS_LITTLE_ENDIAN - select SYS_SUPPORTS_HIGHMEM - select SYS_HAS_EARLY_PRINTK - select GENERIC_ISA_DMA_SUPPORT_BROKEN - select CPU_HAS_WB +config MACH_LOONGSON + bool "Loongson family of machines" help - Lemote Fuloong2e mini-PC board based on the Chinese Loongson-2E CPU and - an FPGA northbridge + This enables the support of Loongson family of machines. + + Loongson is a family of general-purpose MIPS-compatible CPUs. + developed at Institute of Computing Technology (ICT), + Chinese Academy of Sciences (CAS) in the People's Republic + of China. The chief architect is Professor Weiwu Hu. config MIPS_MALTA bool "MIPS Malta board" @@ -668,6 +653,7 @@ source "arch/mips/sibyte/Kconfig" source "arch/mips/txx9/Kconfig" source "arch/mips/vr41xx/Kconfig" source "arch/mips/cavium-octeon/Kconfig" +source "arch/mips/loongson/Kconfig" endmenu diff --git a/arch/mips/Makefile b/arch/mips/Makefile index 7754cbb..94d6f58 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -314,11 +314,12 @@ cflags-$(CONFIG_WR_PPMC) += -I$(srctree)/arch/mips/include/asm/mach-wrppmc load-$(CONFIG_WR_PPMC) += 0xffffffff80100000 # -# lemote fuloong2e mini-PC board +# Loongson family # -core-$(CONFIG_LEMOTE_FULOONG2E) +=arch/mips/loongson/fuloong-2e/ +core-$(CONFIG_MACH_LOONGSON) +=arch/mips/loongson/ +cflags-$(CONFIG_MACH_LOONGSON) += -I$(srctree)/arch/mips/include/asm/mach-loongson \ + -mno-branch-likely load-$(CONFIG_LEMOTE_FULOONG2E) +=0xffffffff80100000 -cflags-$(CONFIG_LEMOTE_FULOONG2E) += -I$(srctree)/arch/mips/include/asm/mach-loongson/ # # MIPS Malta board diff --git a/arch/mips/include/asm/mach-loongson/loongson.h b/arch/mips/include/asm/mach-loongson/loongson.h index 95ee4c8..1c6d4a8 100644 --- a/arch/mips/include/asm/mach-loongson/loongson.h +++ b/arch/mips/include/asm/mach-loongson/loongson.h @@ -24,6 +24,10 @@ extern void bonito_irq_init(void); /* loongson-based machines specific reboot setup */ extern void mips_reboot_setup(void); +/* machine-specific reboot/halt operation */ +extern void mach_prepare_reboot(void); +extern void mach_prepare_shutdown(void); + /* environment arguments from bootloader */ extern unsigned long bus_clock, cpu_clock_freq; extern unsigned long memsize, highmemsize; @@ -33,6 +37,13 @@ extern void __init prom_init_memory(void); extern void __init prom_init_cmdline(void); extern void __init prom_init_env(void); +/* irq operation functions */ +extern void bonito_irqdispatch(void); +extern void __init bonito_irq_init(void); +extern void __init set_irq_trigger_mode(void); +extern void __init mach_init_irq(void); +extern void mach_irq_dispatch(unsigned int pending); + /* PCI Configuration Registers */ #define LOONGSON_PCI_ISR4C BONITO_PCI_REG(0x4c) diff --git a/arch/mips/include/asm/mach-loongson/machine.h b/arch/mips/include/asm/mach-loongson/machine.h new file mode 100644 index 0000000..8e60d36 --- /dev/null +++ b/arch/mips/include/asm/mach-loongson/machine.h @@ -0,0 +1,22 @@ +/* + * Copyright (C) 2009 Lemote, Inc. & Institute of Computing Technology + * Author: Wu Zhangjin + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#ifndef __ASM_MACH_LOONGSON_MACHINE_H +#define __ASM_MACH_LOONGSON_MACHINE_H + +#ifdef CONFIG_LEMOTE_FULOONG2E + +#define LOONGSON_UART_BASE (BONITO_PCIIO_BASE + 0x3f8) + +#define LOONGSON_MACHNAME "lemote-fuloong-2e-box" + +#endif + +#endif /* __ASM_MACH_LOONGSON_MACHINE_H */ diff --git a/arch/mips/include/asm/mach-loongson/mem.h b/arch/mips/include/asm/mach-loongson/mem.h new file mode 100644 index 0000000..bd7b3cb --- /dev/null +++ b/arch/mips/include/asm/mach-loongson/mem.h @@ -0,0 +1,30 @@ +/* + * Copyright (C) 2009 Lemote, Inc. & Institute of Computing Technology + * Author: Wu Zhangjin + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#ifndef __ASM_MACH_LOONGSON_MEM_H +#define __ASM_MACH_LOONGSON_MEM_H + +/* + * On Lemote Loongson 2e + * + * the high memory space starts from 512M. + * the peripheral registers reside between 0x1000:0000 and 0x2000:0000. + */ + +#ifdef CONFIG_LEMOTE_FULOONG2E + +#define LOONGSON_HIGHMEM_START 0x20000000 + +#define LOONGSON_MMIO_MEM_START 0x10000000 +#define LOONGSON_MMIO_MEM_END 0x20000000 + +#endif + +#endif /* __ASM_MACH_LOONGSON_MEM_H */ diff --git a/arch/mips/include/asm/mach-loongson/pci.h b/arch/mips/include/asm/mach-loongson/pci.h index e229b29..f1663ca 100644 --- a/arch/mips/include/asm/mach-loongson/pci.h +++ b/arch/mips/include/asm/mach-loongson/pci.h @@ -24,8 +24,14 @@ extern struct pci_ops bonito64_pci_ops; -#define LOONGSON2E_PCI_MEM_START BONITO_PCILO1_BASE -#define LOONGSON2E_PCI_MEM_END (BONITO_PCILO1_BASE + 0x04000000 * 2) -#define LOONGSON2E_PCI_IO_START 0x00004000UL +#ifdef CONFIG_LEMOTE_FULOONG2E + +/* this pci memory space is mapped by pcimap in pci.c */ +#define LOONGSON_PCI_MEM_START BONITO_PCILO1_BASE +#define LOONGSON_PCI_MEM_END (BONITO_PCILO1_BASE + 0x04000000 * 2) +/* this is an offset from mips_io_port_base */ +#define LOONGSON_PCI_IO_START 0x00004000UL + +#endif #endif /* !__ASM_MACH_LOONGSON_PCI_H_ */ diff --git a/arch/mips/loongson/Kconfig b/arch/mips/loongson/Kconfig new file mode 100644 index 0000000..376712a --- /dev/null +++ b/arch/mips/loongson/Kconfig @@ -0,0 +1,31 @@ +choice + prompt "Machine Type" + depends on MACH_LOONGSON + +config LEMOTE_FULOONG2E + bool "Lemote Fuloong(2e) mini-PC" + select ARCH_SPARSEMEM_ENABLE + select CEVT_R4K + select CSRC_R4K + select SYS_HAS_CPU_LOONGSON2 + select DMA_NONCOHERENT + select BOOT_ELF32 + select BOARD_SCACHE + select HW_HAS_PCI + select I8259 + select ISA + select IRQ_CPU + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_64BIT_KERNEL + select SYS_SUPPORTS_LITTLE_ENDIAN + select SYS_SUPPORTS_HIGHMEM + select SYS_HAS_EARLY_PRINTK + select GENERIC_HARDIRQS_NO__DO_IRQ + select GENERIC_ISA_DMA_SUPPORT_BROKEN + select CPU_HAS_WB + help + Lemote Fuloong(2e) mini-PC board based on the Chinese Loongson-2E CPU and + an FPGA northbridge + + Lemote Fuloong(2e) mini PC have a VIA686B south bridge. +endchoice diff --git a/arch/mips/loongson/Makefile b/arch/mips/loongson/Makefile new file mode 100644 index 0000000..39048c4 --- /dev/null +++ b/arch/mips/loongson/Makefile @@ -0,0 +1,11 @@ +# +# Common code for all Loongson based systems +# + +obj-$(CONFIG_MACH_LOONGSON) += common/ + +# +# Lemote Fuloong mini-PC (Loongson 2E-based) +# + +obj-$(CONFIG_LEMOTE_FULOONG2E) += fuloong-2e/ diff --git a/arch/mips/loongson/common/Makefile b/arch/mips/loongson/common/Makefile new file mode 100644 index 0000000..4e3889d --- /dev/null +++ b/arch/mips/loongson/common/Makefile @@ -0,0 +1,11 @@ +# +# Makefile for loongson based machines. +# + +obj-y += setup.o init.o cmdline.o env.o time.o reset.o irq.o \ + pci.o bonito-irq.o mem.o + +# +# Early printk support +# +obj-$(CONFIG_EARLY_PRINTK) += early_printk.o diff --git a/arch/mips/loongson/common/bonito-irq.c b/arch/mips/loongson/common/bonito-irq.c new file mode 100644 index 0000000..3e31e7a --- /dev/null +++ b/arch/mips/loongson/common/bonito-irq.c @@ -0,0 +1,51 @@ +/* + * Copyright 2001 MontaVista Software Inc. + * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net + * Copyright (C) 2000, 2001 Ralf Baechle (ralf@gnu.org) + * + * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology + * Author: Fuxin Zhang, zhangfx@lemote.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ +#include + +#include + +static inline void bonito_irq_enable(unsigned int irq) +{ + BONITO_INTENSET = (1 << (irq - BONITO_IRQ_BASE)); + mmiowb(); +} + +static inline void bonito_irq_disable(unsigned int irq) +{ + BONITO_INTENCLR = (1 << (irq - BONITO_IRQ_BASE)); + mmiowb(); +} + +static struct irq_chip bonito_irq_type = { + .name = "bonito_irq", + .ack = bonito_irq_disable, + .mask = bonito_irq_disable, + .mask_ack = bonito_irq_disable, + .unmask = bonito_irq_enable, +}; + +static struct irqaction dma_timeout_irqaction = { + .handler = no_action, + .name = "dma_timeout", +}; + +void bonito_irq_init(void) +{ + u32 i; + + for (i = BONITO_IRQ_BASE; i < BONITO_IRQ_BASE + 32; i++) + set_irq_chip_and_handler(i, &bonito_irq_type, handle_level_irq); + + setup_irq(BONITO_IRQ_BASE + 10, &dma_timeout_irqaction); +} diff --git a/arch/mips/loongson/common/cmdline.c b/arch/mips/loongson/common/cmdline.c new file mode 100644 index 0000000..75f1b24 --- /dev/null +++ b/arch/mips/loongson/common/cmdline.c @@ -0,0 +1,52 @@ +/* + * Based on Ocelot Linux port, which is + * Copyright 2001 MontaVista Software Inc. + * Author: jsun@mvista.com or jsun@junsun.net + * + * Copyright 2003 ICT CAS + * Author: Michael Guo + * + * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology + * Author: Fuxin Zhang, zhangfx@lemote.com + * + * Copyright (C) 2009 Lemote Inc. & Insititute of Computing Technology + * Author: Wu Zhangjin, wuzj@lemote.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ +#include + +#include + +int prom_argc; +/* pmon passes arguments in 32bit pointers */ +int *_prom_argv; + +void __init prom_init_cmdline(void) +{ + int i; + long l; + + /* firmware arguments are initialized in head.S */ + prom_argc = fw_arg0; + _prom_argv = (int *)fw_arg1; + + /* arg[0] is "g", the rest is boot parameters */ + arcs_cmdline[0] = '\0'; + for (i = 1; i < prom_argc; i++) { + l = (long)_prom_argv[i]; + if (strlen(arcs_cmdline) + strlen(((char *)l) + 1) + >= sizeof(arcs_cmdline)) + break; + strcat(arcs_cmdline, ((char *)l)); + strcat(arcs_cmdline, " "); + } + + if ((strstr(arcs_cmdline, "console=")) == NULL) + strcat(arcs_cmdline, " console=ttyS0,115200"); + if ((strstr(arcs_cmdline, "root=")) == NULL) + strcat(arcs_cmdline, " root=/dev/hda1"); +} diff --git a/arch/mips/loongson/common/early_printk.c b/arch/mips/loongson/common/early_printk.c new file mode 100644 index 0000000..bc73edc --- /dev/null +++ b/arch/mips/loongson/common/early_printk.c @@ -0,0 +1,38 @@ +/* early printk support + * + * Copyright (c) 2009 Philippe Vachon + * Copyright (C) 2009 Lemote Inc. & Insititute of Computing Technology + * Author: Wu Zhangjin, wuzj@lemote.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ +#include + +#include +#include + +#define PORT(base, offset) (u8 *)(base + offset) + +static inline unsigned int serial_in(phys_addr_t base, int offset) +{ + return readb(PORT(base, offset)); +} + +static inline void serial_out(phys_addr_t base, int offset, int value) +{ + writeb(value, PORT(base, offset)); +} + +void prom_putchar(char c) +{ + phys_addr_t uart_base = + (phys_addr_t) ioremap_nocache(LOONGSON_UART_BASE, 8); + + while ((serial_in(uart_base, UART_LSR) & UART_LSR_THRE) == 0) + ; + + serial_out(uart_base, UART_TX, c); +} diff --git a/arch/mips/loongson/common/env.c b/arch/mips/loongson/common/env.c new file mode 100644 index 0000000..b9ef503 --- /dev/null +++ b/arch/mips/loongson/common/env.c @@ -0,0 +1,58 @@ +/* + * Based on Ocelot Linux port, which is + * Copyright 2001 MontaVista Software Inc. + * Author: jsun@mvista.com or jsun@junsun.net + * + * Copyright 2003 ICT CAS + * Author: Michael Guo + * + * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology + * Author: Fuxin Zhang, zhangfx@lemote.com + * + * Copyright (C) 2009 Lemote Inc. & Insititute of Computing Technology + * Author: Wu Zhangjin, wuzj@lemote.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ +#include + +#include + +unsigned long bus_clock, cpu_clock_freq; +unsigned long memsize, highmemsize; + +/* pmon passes arguments in 32bit pointers */ +int *_prom_envp; + +#define parse_even_earlier(res, option, p) \ +do { \ + if (strncmp(option, (char *)p, strlen(option)) == 0) \ + strict_strtol((char *)p + strlen(option"="), \ + 10, &res); \ +} while (0) + +void __init prom_init_env(void) +{ + long l; + + /* firmware arguments are initialized in head.S */ + _prom_envp = (int *)fw_arg2; + + l = (long)*_prom_envp; + while (l != 0) { + parse_even_earlier(bus_clock, "busclock", l); + parse_even_earlier(cpu_clock_freq, "cpuclock", l); + parse_even_earlier(memsize, "memsize", l); + parse_even_earlier(highmemsize, "highmemsize", l); + _prom_envp++; + l = (long)*_prom_envp; + } + if (memsize == 0) + memsize = 256; + + pr_info("busclock=%ld, cpuclock=%ld, memsize=%ld, highmemsize=%ld\n", + bus_clock, cpu_clock_freq, memsize, highmemsize); +} diff --git a/arch/mips/loongson/common/init.c b/arch/mips/loongson/common/init.c new file mode 100644 index 0000000..3abe927 --- /dev/null +++ b/arch/mips/loongson/common/init.c @@ -0,0 +1,30 @@ +/* + * Copyright (C) 2009 Lemote Inc. & Insititute of Computing Technology + * Author: Wu Zhangjin, wuzj@lemote.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include + +#include + +#include + +void __init prom_init(void) +{ + /* init base address of io space */ + set_io_port_base((unsigned long) + ioremap(BONITO_PCIIO_BASE, BONITO_PCIIO_SIZE)); + + prom_init_cmdline(); + prom_init_env(); + prom_init_memory(); +} + +void __init prom_free_prom_memory(void) +{ +} diff --git a/arch/mips/loongson/common/irq.c b/arch/mips/loongson/common/irq.c new file mode 100644 index 0000000..f368c73 --- /dev/null +++ b/arch/mips/loongson/common/irq.c @@ -0,0 +1,74 @@ +/* + * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology + * Author: Fuxin Zhang, zhangfx@lemote.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ +#include +#include + +#include +/* + * the first level int-handler will jump here if it is a bonito irq + */ +void bonito_irqdispatch(void) +{ + u32 int_status; + int i; + + /* workaround the IO dma problem: let cpu looping to allow DMA finish */ + int_status = BONITO_INTISR; + if (int_status & (1 << 10)) { + while (int_status & (1 << 10)) { + udelay(1); + int_status = BONITO_INTISR; + } + } + + /* Get pending sources, masked by current enables */ + int_status = BONITO_INTISR & BONITO_INTEN; + + if (int_status != 0) { + i = __ffs(int_status); + int_status &= ~(1 << i); + do_IRQ(BONITO_IRQ_BASE + i); + } +} + +asmlinkage void plat_irq_dispatch(void) +{ + unsigned int pending; + + pending = read_c0_cause() & read_c0_status() & ST0_IM; + + /* machine-specific plat_irq_dispatch */ + mach_irq_dispatch(pending); +} + +void __init arch_init_irq(void) +{ + /* + * Clear all of the interrupts while we change the able around a bit. + * int-handler is not on bootstrap + */ + clear_c0_status(ST0_IM | ST0_BEV); + local_irq_disable(); + + /* setting irq trigger mode */ + set_irq_trigger_mode(); + + /* no steer */ + BONITO_INTSTEER = 0; + + /* + * Mask out all interrupt by writing "1" to all bit position in + * the interrupt reset reg. + */ + BONITO_INTENCLR = ~0; + + /* machine specific irq init */ + mach_init_irq(); +} diff --git a/arch/mips/loongson/common/machtype.c b/arch/mips/loongson/common/machtype.c new file mode 100644 index 0000000..845b3fb --- /dev/null +++ b/arch/mips/loongson/common/machtype.c @@ -0,0 +1,17 @@ +/* + * Copyright (C) 2009 Lemote Inc. & Insititute of Computing Technology + * Author: Wu Zhangjin, wuzj@lemote.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include + +const char *get_system_type(void) +{ + return LOONGSON_MACHNAME; +} + diff --git a/arch/mips/loongson/common/mem.c b/arch/mips/loongson/common/mem.c new file mode 100644 index 0000000..7c92f79 --- /dev/null +++ b/arch/mips/loongson/common/mem.c @@ -0,0 +1,35 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ +#include +#include +#include + +#include + +#include +#include + +void __init prom_init_memory(void) +{ + add_memory_region(0x0, (memsize << 20), BOOT_MEM_RAM); +#ifdef CONFIG_64BIT + if (highmemsize > 0) + add_memory_region(LOONGSON_HIGHMEM_START, + highmemsize << 20, BOOT_MEM_RAM); +#endif /* CONFIG_64BIT */ +} + +/* override of arch/mips/mm/cache.c: __uncached_access */ +int __uncached_access(struct file *file, unsigned long addr) +{ + if (file->f_flags & O_SYNC) + return 1; + + return addr >= __pa(high_memory) || + ((addr >= LOONGSON_MMIO_MEM_START) && + (addr < LOONGSON_MMIO_MEM_END)); +} diff --git a/arch/mips/loongson/common/pci.c b/arch/mips/loongson/common/pci.c new file mode 100644 index 0000000..a3a4abf --- /dev/null +++ b/arch/mips/loongson/common/pci.c @@ -0,0 +1,83 @@ +/* + * Copyright (C) 2007 Lemote, Inc. & Institute of Computing Technology + * Author: Fuxin Zhang, zhangfx@lemote.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ +#include + +#include +#include + +static struct resource loongson_pci_mem_resource = { + .name = "pci memory space", + .start = LOONGSON_PCI_MEM_START, + .end = LOONGSON_PCI_MEM_END, + .flags = IORESOURCE_MEM, +}; + +static struct resource loongson_pci_io_resource = { + .name = "pci io space", + .start = LOONGSON_PCI_IO_START, + .end = IO_SPACE_LIMIT, + .flags = IORESOURCE_IO, +}; + +static struct pci_controller loongson_pci_controller = { + .pci_ops = &bonito64_pci_ops, + .io_resource = &loongson_pci_io_resource, + .mem_resource = &loongson_pci_mem_resource, + .mem_offset = 0x00000000UL, + .io_offset = 0x00000000UL, +}; + +static void __init setup_pcimap(void) +{ + /* + * local to PCI mapping for CPU accessing PCI space + * CPU address space [256M,448M] is window for accessing pci space + * we set pcimap_lo[0,1,2] to map it to pci space[0M,64M], [320M,448M] + * + * pcimap: PCI_MAP2 PCI_Mem_Lo2 PCI_Mem_Lo1 PCI_Mem_Lo0 + * [<2G] [384M,448M] [320M,384M] [0M,64M] + */ + BONITO_PCIMAP = BONITO_PCIMAP_PCIMAP_2 | + BONITO_PCIMAP_WIN(2, BONITO_PCILO2_BASE) | + BONITO_PCIMAP_WIN(1, BONITO_PCILO1_BASE) | + BONITO_PCIMAP_WIN(0, 0); + + /* + * PCI-DMA to local mapping: [2G,2G+256M] -> [0M,256M] + */ + BONITO_PCIBASE0 = 0x80000000ul; /* base: 2G -> mmap: 0M */ + /* size: 256M, burst transmission, pre-fetch enable, 64bit */ + LOONGSON_PCI_HIT0_SEL_L = 0xc000000cul; + LOONGSON_PCI_HIT0_SEL_H = 0xfffffffful; + LOONGSON_PCI_HIT1_SEL_L = 0x00000006ul; /* set this BAR as invalid */ + LOONGSON_PCI_HIT1_SEL_H = 0x00000000ul; + LOONGSON_PCI_HIT2_SEL_L = 0x00000006ul; /* set this BAR as invalid */ + LOONGSON_PCI_HIT2_SEL_H = 0x00000000ul; + + /* avoid deadlock of PCI reading/writing lock operation */ + LOONGSON_PCI_ISR4C = 0xd2000001ul; + + /* can not change gnt to break pci transfer when device's gnt not + deassert for some broken device */ + LOONGSON_PXARB_CFG = 0x00fe0105ul; +} + +static int __init pcibios_init(void) +{ + setup_pcimap(); + + loongson_pci_controller.io_map_base = mips_io_port_base; + + register_pci_controller(&loongson_pci_controller); + + return 0; +} + +arch_initcall(pcibios_init); diff --git a/arch/mips/loongson/common/reset.c b/arch/mips/loongson/common/reset.c new file mode 100644 index 0000000..8f67c00 --- /dev/null +++ b/arch/mips/loongson/common/reset.c @@ -0,0 +1,39 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * Copyright (C) 2007 Lemote, Inc. & Institute of Computing Technology + * Author: Fuxin Zhang, zhangfx@lemote.com + * Copyright (C) 2009 Lemote, Inc. & Institute of Computing Technology + * Author: Zhangjin Wu, wuzj@lemote.com + */ +#include + +#include + +#include + +static void loongson_restart(char *command) +{ + /* do preparation for reboot */ + mach_prepare_reboot(); + + /* reboot via jumping to boot base address */ + ((void (*)(void))ioremap_nocache(BONITO_BOOT_BASE, 4)) (); +} + +static void loongson_halt(void) +{ + mach_prepare_shutdown(); + while (1) + ; +} + +void mips_reboot_setup(void) +{ + _machine_restart = loongson_restart; + _machine_halt = loongson_halt; + pm_power_off = loongson_halt; +} diff --git a/arch/mips/loongson/common/setup.c b/arch/mips/loongson/common/setup.c new file mode 100644 index 0000000..aaa070c --- /dev/null +++ b/arch/mips/loongson/common/setup.c @@ -0,0 +1,60 @@ +/* + * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology + * Author: Fuxin Zhang, zhangfx@lemote.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ +#include + +#include + +#include + +#ifdef CONFIG_VT +#include +#include +#endif + +void (*__wbflush)(void); +EXPORT_SYMBOL(__wbflush); + +static void wbflush_loongson(void) +{ + asm(".set\tpush\n\t" + ".set\tnoreorder\n\t" + ".set mips3\n\t" + "sync\n\t" + "nop\n\t" + ".set\tpop\n\t" + ".set mips0\n\t"); +} + +void __init plat_mem_setup(void) +{ + mips_reboot_setup(); + + __wbflush = wbflush_loongson; + +#ifdef CONFIG_VT +#if defined(CONFIG_VGA_CONSOLE) + conswitchp = &vga_con; + + screen_info = (struct screen_info) { + 0, 25, /* orig-x, orig-y */ + 0, /* unused */ + 0, /* orig-video-page */ + 0, /* orig-video-mode */ + 80, /* orig-video-cols */ + 0, 0, 0, /* ega_ax, ega_bx, ega_cx */ + 25, /* orig-video-lines */ + VIDEO_TYPE_VGAC, /* orig-video-isVGA */ + 16 /* orig-video-points */ + }; +#elif defined(CONFIG_DUMMY_CONSOLE) + conswitchp = &dummy_con; +#endif +#endif +} diff --git a/arch/mips/loongson/common/time.c b/arch/mips/loongson/common/time.c new file mode 100644 index 0000000..b13d171 --- /dev/null +++ b/arch/mips/loongson/common/time.c @@ -0,0 +1,27 @@ +/* + * Copyright (C) 2007 Lemote, Inc. & Institute of Computing Technology + * Author: Fuxin Zhang, zhangfx@lemote.com + * + * Copyright (C) 2009 Lemote Inc. & Insititute of Computing Technology + * Author: Wu Zhangjin, wuzj@lemote.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ +#include +#include + +#include + +void __init plat_time_init(void) +{ + /* setup mips r4k timer */ + mips_hpt_frequency = cpu_clock_freq / 2; +} + +unsigned long read_persistent_clock(void) +{ + return mc146818_get_cmos_time(); +} diff --git a/arch/mips/loongson/fuloong-2e/Makefile b/arch/mips/loongson/fuloong-2e/Makefile index feb1d6b..96e45c1 100644 --- a/arch/mips/loongson/fuloong-2e/Makefile +++ b/arch/mips/loongson/fuloong-2e/Makefile @@ -2,12 +2,6 @@ # Makefile for Lemote Fuloong2e mini-PC board. # -obj-y += setup.o init.o reset.o irq.o pci.o bonito-irq.o mem.o \ - env.o cmdline.o time.o machtype.o - -# -# Early printk support -# -obj-$(CONFIG_EARLY_PRINTK) += early_printk.o +obj-y += irq.o reset.o machtype.o EXTRA_CFLAGS += -Werror diff --git a/arch/mips/loongson/fuloong-2e/bonito-irq.c b/arch/mips/loongson/fuloong-2e/bonito-irq.c deleted file mode 100644 index 3e31e7a..0000000 --- a/arch/mips/loongson/fuloong-2e/bonito-irq.c +++ /dev/null @@ -1,51 +0,0 @@ -/* - * Copyright 2001 MontaVista Software Inc. - * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net - * Copyright (C) 2000, 2001 Ralf Baechle (ralf@gnu.org) - * - * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology - * Author: Fuxin Zhang, zhangfx@lemote.com - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ -#include - -#include - -static inline void bonito_irq_enable(unsigned int irq) -{ - BONITO_INTENSET = (1 << (irq - BONITO_IRQ_BASE)); - mmiowb(); -} - -static inline void bonito_irq_disable(unsigned int irq) -{ - BONITO_INTENCLR = (1 << (irq - BONITO_IRQ_BASE)); - mmiowb(); -} - -static struct irq_chip bonito_irq_type = { - .name = "bonito_irq", - .ack = bonito_irq_disable, - .mask = bonito_irq_disable, - .mask_ack = bonito_irq_disable, - .unmask = bonito_irq_enable, -}; - -static struct irqaction dma_timeout_irqaction = { - .handler = no_action, - .name = "dma_timeout", -}; - -void bonito_irq_init(void) -{ - u32 i; - - for (i = BONITO_IRQ_BASE; i < BONITO_IRQ_BASE + 32; i++) - set_irq_chip_and_handler(i, &bonito_irq_type, handle_level_irq); - - setup_irq(BONITO_IRQ_BASE + 10, &dma_timeout_irqaction); -} diff --git a/arch/mips/loongson/fuloong-2e/cmdline.c b/arch/mips/loongson/fuloong-2e/cmdline.c deleted file mode 100644 index 75f1b24..0000000 --- a/arch/mips/loongson/fuloong-2e/cmdline.c +++ /dev/null @@ -1,52 +0,0 @@ -/* - * Based on Ocelot Linux port, which is - * Copyright 2001 MontaVista Software Inc. - * Author: jsun@mvista.com or jsun@junsun.net - * - * Copyright 2003 ICT CAS - * Author: Michael Guo - * - * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology - * Author: Fuxin Zhang, zhangfx@lemote.com - * - * Copyright (C) 2009 Lemote Inc. & Insititute of Computing Technology - * Author: Wu Zhangjin, wuzj@lemote.com - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ -#include - -#include - -int prom_argc; -/* pmon passes arguments in 32bit pointers */ -int *_prom_argv; - -void __init prom_init_cmdline(void) -{ - int i; - long l; - - /* firmware arguments are initialized in head.S */ - prom_argc = fw_arg0; - _prom_argv = (int *)fw_arg1; - - /* arg[0] is "g", the rest is boot parameters */ - arcs_cmdline[0] = '\0'; - for (i = 1; i < prom_argc; i++) { - l = (long)_prom_argv[i]; - if (strlen(arcs_cmdline) + strlen(((char *)l) + 1) - >= sizeof(arcs_cmdline)) - break; - strcat(arcs_cmdline, ((char *)l)); - strcat(arcs_cmdline, " "); - } - - if ((strstr(arcs_cmdline, "console=")) == NULL) - strcat(arcs_cmdline, " console=ttyS0,115200"); - if ((strstr(arcs_cmdline, "root=")) == NULL) - strcat(arcs_cmdline, " root=/dev/hda1"); -} diff --git a/arch/mips/loongson/fuloong-2e/early_printk.c b/arch/mips/loongson/fuloong-2e/early_printk.c deleted file mode 100644 index 3e0a6ea..0000000 --- a/arch/mips/loongson/fuloong-2e/early_printk.c +++ /dev/null @@ -1,39 +0,0 @@ -/* early printk support - * - * Copyright (c) 2009 Philippe Vachon - * Copyright (C) 2009 Lemote Inc. & Insititute of Computing Technology - * Author: Wu Zhangjin, wuzj@lemote.com - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ -#include - -#include - -#define UART_BASE (BONITO_PCIIO_BASE + 0x3f8) - -#define PORT(base, offset) (u8 *)(base + offset) - -static inline unsigned int serial_in(phys_addr_t base, int offset) -{ - return readb(PORT(base, offset)); -} - -static inline void serial_out(phys_addr_t base, int offset, int value) -{ - writeb(value, PORT(base, offset)); -} - -void prom_putchar(char c) -{ - phys_addr_t uart_base = - (phys_addr_t) ioremap_nocache(UART_BASE, 8); - - while ((serial_in(uart_base, UART_LSR) & UART_LSR_THRE) == 0) - ; - - serial_out(uart_base, UART_TX, c); -} diff --git a/arch/mips/loongson/fuloong-2e/env.c b/arch/mips/loongson/fuloong-2e/env.c deleted file mode 100644 index b9ef503..0000000 --- a/arch/mips/loongson/fuloong-2e/env.c +++ /dev/null @@ -1,58 +0,0 @@ -/* - * Based on Ocelot Linux port, which is - * Copyright 2001 MontaVista Software Inc. - * Author: jsun@mvista.com or jsun@junsun.net - * - * Copyright 2003 ICT CAS - * Author: Michael Guo - * - * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology - * Author: Fuxin Zhang, zhangfx@lemote.com - * - * Copyright (C) 2009 Lemote Inc. & Insititute of Computing Technology - * Author: Wu Zhangjin, wuzj@lemote.com - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ -#include - -#include - -unsigned long bus_clock, cpu_clock_freq; -unsigned long memsize, highmemsize; - -/* pmon passes arguments in 32bit pointers */ -int *_prom_envp; - -#define parse_even_earlier(res, option, p) \ -do { \ - if (strncmp(option, (char *)p, strlen(option)) == 0) \ - strict_strtol((char *)p + strlen(option"="), \ - 10, &res); \ -} while (0) - -void __init prom_init_env(void) -{ - long l; - - /* firmware arguments are initialized in head.S */ - _prom_envp = (int *)fw_arg2; - - l = (long)*_prom_envp; - while (l != 0) { - parse_even_earlier(bus_clock, "busclock", l); - parse_even_earlier(cpu_clock_freq, "cpuclock", l); - parse_even_earlier(memsize, "memsize", l); - parse_even_earlier(highmemsize, "highmemsize", l); - _prom_envp++; - l = (long)*_prom_envp; - } - if (memsize == 0) - memsize = 256; - - pr_info("busclock=%ld, cpuclock=%ld, memsize=%ld, highmemsize=%ld\n", - bus_clock, cpu_clock_freq, memsize, highmemsize); -} diff --git a/arch/mips/loongson/fuloong-2e/init.c b/arch/mips/loongson/fuloong-2e/init.c deleted file mode 100644 index 3abe927..0000000 --- a/arch/mips/loongson/fuloong-2e/init.c +++ /dev/null @@ -1,30 +0,0 @@ -/* - * Copyright (C) 2009 Lemote Inc. & Insititute of Computing Technology - * Author: Wu Zhangjin, wuzj@lemote.com - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#include - -#include - -#include - -void __init prom_init(void) -{ - /* init base address of io space */ - set_io_port_base((unsigned long) - ioremap(BONITO_PCIIO_BASE, BONITO_PCIIO_SIZE)); - - prom_init_cmdline(); - prom_init_env(); - prom_init_memory(); -} - -void __init prom_free_prom_memory(void) -{ -} diff --git a/arch/mips/loongson/fuloong-2e/irq.c b/arch/mips/loongson/fuloong-2e/irq.c index 9585f5a..7888cf6 100644 --- a/arch/mips/loongson/fuloong-2e/irq.c +++ b/arch/mips/loongson/fuloong-2e/irq.c @@ -7,39 +7,12 @@ * Free Software Foundation; either version 2 of the License, or (at your * option) any later version. */ -#include #include #include #include #include -/* - * the first level int-handler will jump here if it is a bonito irq - */ -static void bonito_irqdispatch(void) -{ - u32 int_status; - int i; - - /* workaround the IO dma problem: let cpu looping to allow DMA finish */ - int_status = BONITO_INTISR; - if (int_status & (1 << 10)) { - while (int_status & (1 << 10)) { - udelay(1); - int_status = BONITO_INTISR; - } - } - - /* Get pending sources, masked by current enables */ - int_status = BONITO_INTISR & BONITO_INTEN; - - if (int_status != 0) { - i = __ffs(int_status); - int_status &= ~(1 << i); - do_IRQ(BONITO_IRQ_BASE + i); - } -} static void i8259_irqdispatch(void) { @@ -52,10 +25,8 @@ static void i8259_irqdispatch(void) spurious_interrupt(); } -asmlinkage void plat_irq_dispatch(void) +asmlinkage void mach_irq_dispatch(unsigned int pending) { - unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM; - if (pending & CAUSEF_IP7) do_IRQ(MIPS_CPU_IRQ_BASE + 7); else if (pending & CAUSEF_IP6) /* perf counter loverflow */ @@ -73,26 +44,15 @@ static struct irqaction cascade_irqaction = { .name = "cascade", }; -void __init arch_init_irq(void) +void __init set_irq_trigger_mode(void) { - /* - * Clear all of the interrupts while we change the able around a bit. - * int-handler is not on bootstrap - */ - clear_c0_status(ST0_IM | ST0_BEV); - local_irq_disable(); - /* most bonito irq should be level triggered */ BONITO_INTEDGE = BONITO_ICU_SYSTEMERR | BONITO_ICU_MASTERERR | - BONITO_ICU_RETRYERR | BONITO_ICU_MBOXES; - BONITO_INTSTEER = 0; - - /* - * Mask out all interrupt by writing "1" to all bit position in - * the interrupt reset reg. - */ - BONITO_INTENCLR = ~0; + BONITO_ICU_RETRYERR | BONITO_ICU_MBOXES; +} +void __init mach_init_irq(void) +{ /* init all controller * 0-15 ------> i8259 interrupt * 16-23 ------> mips cpu interrupt diff --git a/arch/mips/loongson/fuloong-2e/machtype.c b/arch/mips/loongson/fuloong-2e/machtype.c deleted file mode 100644 index e03aa0d..0000000 --- a/arch/mips/loongson/fuloong-2e/machtype.c +++ /dev/null @@ -1,15 +0,0 @@ -/* - * Copyright (C) 2009 Lemote Inc. & Insititute of Computing Technology - * Author: Wu Zhangjin, wuzj@lemote.com - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -const char *get_system_type(void) -{ - return "lemote-fuloong-2e-box"; -} - diff --git a/arch/mips/loongson/fuloong-2e/mem.c b/arch/mips/loongson/fuloong-2e/mem.c deleted file mode 100644 index 6a7feb1..0000000 --- a/arch/mips/loongson/fuloong-2e/mem.c +++ /dev/null @@ -1,36 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ -#include -#include -#include - -#include - -#include - -void __init prom_init_memory(void) -{ - add_memory_region(0x0, (memsize << 20), BOOT_MEM_RAM); -#ifdef CONFIG_64BIT - if (highmemsize > 0) - add_memory_region(0x20000000, highmemsize << 20, BOOT_MEM_RAM); -#endif /* CONFIG_64BIT */ -} - -/* override of arch/mips/mm/cache.c: __uncached_access */ -int __uncached_access(struct file *file, unsigned long addr) -{ - if (file->f_flags & O_SYNC) - return 1; - - /* - * On the Lemote Loongson 2e system, the peripheral registers - * reside between 0x1000:0000 and 0x2000:0000. - */ - return addr >= __pa(high_memory) || - ((addr >= 0x10000000) && (addr < 0x20000000)); -} diff --git a/arch/mips/loongson/fuloong-2e/pci.c b/arch/mips/loongson/fuloong-2e/pci.c deleted file mode 100644 index 9812c30..0000000 --- a/arch/mips/loongson/fuloong-2e/pci.c +++ /dev/null @@ -1,83 +0,0 @@ -/* - * Copyright (C) 2007 Lemote, Inc. & Institute of Computing Technology - * Author: Fuxin Zhang, zhangfx@lemote.com - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ -#include - -#include -#include - -static struct resource loongson2e_pci_mem_resource = { - .name = "LOONGSON2E PCI MEM", - .start = LOONGSON2E_PCI_MEM_START, - .end = LOONGSON2E_PCI_MEM_END, - .flags = IORESOURCE_MEM, -}; - -static struct resource loongson2e_pci_io_resource = { - .name = "LOONGSON2E PCI IO MEM", - .start = LOONGSON2E_PCI_IO_START, - .end = IO_SPACE_LIMIT, - .flags = IORESOURCE_IO, -}; - -static struct pci_controller loongson2e_pci_controller = { - .pci_ops = &bonito64_pci_ops, - .io_resource = &loongson2e_pci_io_resource, - .mem_resource = &loongson2e_pci_mem_resource, - .mem_offset = 0x00000000UL, - .io_offset = 0x00000000UL, -}; - -static void __init setup_pcimap(void) -{ - /* - * local to PCI mapping for CPU accessing PCI space - * CPU address space [256M,448M] is window for accessing pci space - * we set pcimap_lo[0,1,2] to map it to pci space[0M,64M], [320M,448M] - * - * pcimap: PCI_MAP2 PCI_Mem_Lo2 PCI_Mem_Lo1 PCI_Mem_Lo0 - * [<2G] [384M,448M] [320M,384M] [0M,64M] - */ - BONITO_PCIMAP = BONITO_PCIMAP_PCIMAP_2 | - BONITO_PCIMAP_WIN(2, BONITO_PCILO2_BASE) | - BONITO_PCIMAP_WIN(1, BONITO_PCILO1_BASE) | - BONITO_PCIMAP_WIN(0, 0); - - /* - * PCI-DMA to local mapping: [2G,2G+256M] -> [0M,256M] - */ - BONITO_PCIBASE0 = 0x80000000ul; /* base: 2G -> mmap: 0M */ - /* size: 256M, burst transmission, pre-fetch enable, 64bit */ - LOONGSON_PCI_HIT0_SEL_L = 0xc000000cul; - LOONGSON_PCI_HIT0_SEL_H = 0xfffffffful; - LOONGSON_PCI_HIT1_SEL_L = 0x00000006ul; /* set this BAR as invalid */ - LOONGSON_PCI_HIT1_SEL_H = 0x00000000ul; - LOONGSON_PCI_HIT2_SEL_L = 0x00000006ul; /* set this BAR as invalid */ - LOONGSON_PCI_HIT2_SEL_H = 0x00000000ul; - - /* avoid deadlock of PCI reading/writing lock operation */ - LOONGSON_PCI_ISR4C = 0xd2000001ul; - - /* can not change gnt to break pci transfer when device's gnt not - deassert for some broken device */ - LOONGSON_PXARB_CFG = 0x00fe0105ul; -} - -static int __init pcibios_init(void) -{ - setup_pcimap(); - - loongson2e_pci_controller.io_map_base = mips_io_port_base; - - register_pci_controller(&loongson2e_pci_controller); - - return 0; -} - -arch_initcall(pcibios_init); diff --git a/arch/mips/loongson/fuloong-2e/reset.c b/arch/mips/loongson/fuloong-2e/reset.c index d89c9e4..17f8237 100644 --- a/arch/mips/loongson/fuloong-2e/reset.c +++ b/arch/mips/loongson/fuloong-2e/reset.c @@ -1,39 +1,24 @@ -/* +/* Board-specific reboot/shutdown routines + * Copyright (c) 2009 Philippe Vachon + * + * Copyright (C) 2009 Lemote Inc. & Insititute of Computing Technology + * Author: Wu Zhangjin, wuzj@lemote.com + * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the * Free Software Foundation; either version 2 of the License, or (at your * option) any later version. - * - * Copyright (C) 2007 Lemote, Inc. & Institute of Computing Technology - * Author: Fuxin Zhang, zhangfx@lemote.com - * Copyright (C) 2009 Lemote, Inc. & Institute of Computing Technology - * Author: Zhangjin Wu, wuzj@lemote.com */ -#include - -#include #include -static void loongson2e_restart(char *command) +void mach_prepare_reboot(void) { - /* do preparation for reboot */ BONITO_BONGENCFG &= ~(1 << 2); BONITO_BONGENCFG |= (1 << 2); - - /* reboot via jumping to boot base address */ - ((void (*)(void))ioremap_nocache(BONITO_BOOT_BASE, 4)) (); } -static void loongson2e_halt(void) +void mach_prepare_shutdown(void) { - while (1) - ; } -void mips_reboot_setup(void) -{ - _machine_restart = loongson2e_restart; - _machine_halt = loongson2e_halt; - pm_power_off = loongson2e_halt; -} diff --git a/arch/mips/loongson/fuloong-2e/setup.c b/arch/mips/loongson/fuloong-2e/setup.c deleted file mode 100644 index 655695c..0000000 --- a/arch/mips/loongson/fuloong-2e/setup.c +++ /dev/null @@ -1,60 +0,0 @@ -/* - * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology - * Author: Fuxin Zhang, zhangfx@lemote.com - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ -#include - -#include - -#include - -#ifdef CONFIG_VT -#include -#include -#endif - -void (*__wbflush)(void); -EXPORT_SYMBOL(__wbflush); - -static void wbflush_loongson2e(void) -{ - asm(".set\tpush\n\t" - ".set\tnoreorder\n\t" - ".set mips3\n\t" - "sync\n\t" - "nop\n\t" - ".set\tpop\n\t" - ".set mips0\n\t"); -} - -void __init plat_mem_setup(void) -{ - mips_reboot_setup(); - - __wbflush = wbflush_loongson2e; - -#ifdef CONFIG_VT -#if defined(CONFIG_VGA_CONSOLE) - conswitchp = &vga_con; - - screen_info = (struct screen_info) { - 0, 25, /* orig-x, orig-y */ - 0, /* unused */ - 0, /* orig-video-page */ - 0, /* orig-video-mode */ - 80, /* orig-video-cols */ - 0, 0, 0, /* ega_ax, ega_bx, ega_cx */ - 25, /* orig-video-lines */ - VIDEO_TYPE_VGAC, /* orig-video-isVGA */ - 16 /* orig-video-points */ - }; -#elif defined(CONFIG_DUMMY_CONSOLE) - conswitchp = &dummy_con; -#endif -#endif -} diff --git a/arch/mips/loongson/fuloong-2e/time.c b/arch/mips/loongson/fuloong-2e/time.c deleted file mode 100644 index b13d171..0000000 --- a/arch/mips/loongson/fuloong-2e/time.c +++ /dev/null @@ -1,27 +0,0 @@ -/* - * Copyright (C) 2007 Lemote, Inc. & Institute of Computing Technology - * Author: Fuxin Zhang, zhangfx@lemote.com - * - * Copyright (C) 2009 Lemote Inc. & Insititute of Computing Technology - * Author: Wu Zhangjin, wuzj@lemote.com - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ -#include -#include - -#include - -void __init plat_time_init(void) -{ - /* setup mips r4k timer */ - mips_hpt_frequency = cpu_clock_freq / 2; -} - -unsigned long read_persistent_clock(void) -{ - return mc146818_get_cmos_time(); -} -- 1.6.2.1 From wuzhangjin@gmail.com Thu Jul 2 17:33:12 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 02 Jul 2009 17:33:20 +0200 (CEST) Received: from mail-ew0-f214.google.com ([209.85.219.214]:62210 "EHLO mail-ew0-f214.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492214AbZGBPdK (ORCPT ); Thu, 2 Jul 2009 17:33:10 +0200 Received: by mail-ew0-f214.google.com with SMTP id 10so2101362ewy.0 for ; Thu, 02 Jul 2009 08:27:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer:in-reply-to:references; bh=uzVk24w4HMBH7OPtI9aIFtXGGeRoQt1SJVCI3+FvZtY=; b=I38+W09OEnFrscHwpxlqd3aloc6eoY/oSScriEfmZ1DFT4u/i1pjIoHEKQIPzSQje/ XuAumUsIal/11lA3zJVLjpQp4UOv+JS+V11h/jyL4HbBiE5SIdehLpGT9xieyrLMLONi 7leeZXQImkINGEjoia/nQiFXC6Lo415a679RY= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; b=RajVVNhuN/ZvurP8zfcK0ZRI0GBP/bpfZ/xgP7Hw0+YoDdEgvLmGGXmQMSr8jK+QbN fQPZr76dDsZsFq61fRZLcfcfuJKpulWsQ3poy6gJhHDPTFhAznVgB8IgcQme1idXW9qs 3EmyRVjyP1f/beSpZGi/r7QqsLoj8glfQJV3c= Received: by 10.216.16.212 with SMTP id h62mr43068weh.201.1246548444943; Thu, 02 Jul 2009 08:27:24 -0700 (PDT) Received: from localhost.localdomain ([222.92.8.142]) by mx.google.com with ESMTPS id p10sm5885401gvf.19.2009.07.02.08.27.18 (version=TLSv1/SSLv3 cipher=RC4-MD5); Thu, 02 Jul 2009 08:27:23 -0700 (PDT) From: Wu Zhangjin To: linux-kernel@vger.kernel.org, linux-mips@linux-mips.org, ralf@linux-mips.org Cc: Wu Zhangjin , Yan Hua , Philippe Vachon , Zhang Le , Zhang Fuxin , loongson-dev , Liu Junliang , Erwan Lerale , Arnaud Patard Subject: [PATCH v4 14/16] [loongson] add a machtype kernel command line argument Date: Thu, 2 Jul 2009 23:27:12 +0800 Message-Id: X-Mailer: git-send-email 1.6.2.1 In-Reply-To: References: Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23626 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips the difference between some loongson-based machines is very small, so, if there is no necessary to add new kernel config options to cope with this difference, it will be better to share the same kernel image file between them, benefit from this, the linux distribution developers only have a need to compile the kernel one time. this machtype kernel command line argument will be used later to share the same kernel image file between two different machines(menglong & yeeloong) made by lemote. thanks very much to Zhang Le for cleaning up the machtype implementation. Signed-off-by: Wu Zhangjin --- Documentation/kernel-parameters.txt | 4 +++ arch/mips/include/asm/bootinfo.h | 12 ++++++++ arch/mips/include/asm/mach-loongson/machine.h | 2 +- arch/mips/loongson/common/Makefile | 2 +- arch/mips/loongson/common/machtype.c | 35 ++++++++++++++++++++++++- arch/mips/loongson/fuloong-2e/Makefile | 2 +- 6 files changed, 53 insertions(+), 4 deletions(-) diff --git a/Documentation/kernel-parameters.txt b/Documentation/kernel-parameters.txt index d77fbd8..3e95d29 100644 --- a/Documentation/kernel-parameters.txt +++ b/Documentation/kernel-parameters.txt @@ -1243,6 +1243,10 @@ and is between 256 and 4096 characters. It is defined in the file (machvec) in a generic kernel. Example: machvec=hpzx1_swiotlb + machtype= [Loongson] Share the same kernel image file between different + yeeloong laptop. + Example: machtype=lemote-yeeloong-2f-7inch + max_addr=nn[KMG] [KNL,BOOT,ia64] All physical memory greater than or equal to this physical address is ignored. diff --git a/arch/mips/include/asm/bootinfo.h b/arch/mips/include/asm/bootinfo.h index 610fe3a..f5dfaf6 100644 --- a/arch/mips/include/asm/bootinfo.h +++ b/arch/mips/include/asm/bootinfo.h @@ -7,6 +7,7 @@ * Copyright (C) 1995, 1996 Andreas Busse * Copyright (C) 1995, 1996 Stoned Elipot * Copyright (C) 1995, 1996 Paul M. Antoine. + * Copyright (C) 2009 Zhang Le */ #ifndef _ASM_BOOTINFO_H #define _ASM_BOOTINFO_H @@ -57,6 +58,17 @@ #define MACH_MIKROTIK_RB532 0 /* Mikrotik RouterBoard 532 */ #define MACH_MIKROTIK_RB532A 1 /* Mikrotik RouterBoard 532A */ +/* + * Valid machtype for Loongson family + */ +#define MACH_LOONGSON_UNKNOWN 0 +#define MACH_LEMOTE_FL2E 1 +#define MACH_LEMOTE_FL2F 2 +#define MACH_LEMOTE_ML2F7 3 +#define MACH_LEMOTE_YL2F89 4 +#define MACH_DEXXON_GDIUM2F10 5 +#define MACH_LOONGSON_END 6 + #define CL_SIZE COMMAND_LINE_SIZE extern char *system_type; diff --git a/arch/mips/include/asm/mach-loongson/machine.h b/arch/mips/include/asm/mach-loongson/machine.h index 8e60d36..206ea20 100644 --- a/arch/mips/include/asm/mach-loongson/machine.h +++ b/arch/mips/include/asm/mach-loongson/machine.h @@ -15,7 +15,7 @@ #define LOONGSON_UART_BASE (BONITO_PCIIO_BASE + 0x3f8) -#define LOONGSON_MACHNAME "lemote-fuloong-2e-box" +#define LOONGSON_MACHTYPE MACH_LEMOTE_FL2E #endif diff --git a/arch/mips/loongson/common/Makefile b/arch/mips/loongson/common/Makefile index 4e3889d..656b3cc 100644 --- a/arch/mips/loongson/common/Makefile +++ b/arch/mips/loongson/common/Makefile @@ -3,7 +3,7 @@ # obj-y += setup.o init.o cmdline.o env.o time.o reset.o irq.o \ - pci.o bonito-irq.o mem.o + pci.o bonito-irq.o mem.o machtype.o # # Early printk support diff --git a/arch/mips/loongson/common/machtype.c b/arch/mips/loongson/common/machtype.c index 845b3fb..7b34824 100644 --- a/arch/mips/loongson/common/machtype.c +++ b/arch/mips/loongson/common/machtype.c @@ -2,16 +2,49 @@ * Copyright (C) 2009 Lemote Inc. & Insititute of Computing Technology * Author: Wu Zhangjin, wuzj@lemote.com * + * Copyright (c) 2009 Zhang Le + * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the * Free Software Foundation; either version 2 of the License, or (at your * option) any later version. */ +#include +#include +#include #include +static const char *system_types[] = { + [MACH_LOONGSON_UNKNOWN] "unknown loongson machine", + [MACH_LEMOTE_FL2E] "lemote-fuloong-2e-box", + [MACH_LEMOTE_FL2F] "lemote-fuloong-2f-box", + [MACH_LEMOTE_ML2F7] "lemote-mengloong-2f-7inches", + [MACH_LEMOTE_YL2F89] "lemote-yeeloong-2f-8.9inches", + [MACH_DEXXON_GDIUM2F10] "dexxon-gidum-2f-10inches", + [MACH_LOONGSON_END] NULL, +}; + const char *get_system_type(void) { - return LOONGSON_MACHNAME; + if (mips_machtype == MACH_UNKNOWN) + mips_machtype = LOONGSON_MACHTYPE; + + return system_types[mips_machtype]; } +static __init int machtype_setup(char *str) +{ + int machtype = MACH_LEMOTE_FL2E; + + if (!str) + return -EINVAL; + + for (; system_types[machtype]; machtype++) + if (strstr(system_types[machtype], str)) { + mips_machtype = machtype; + break; + } + return 0; +} +__setup("machtype=", machtype_setup); diff --git a/arch/mips/loongson/fuloong-2e/Makefile b/arch/mips/loongson/fuloong-2e/Makefile index 96e45c1..3aba5fc 100644 --- a/arch/mips/loongson/fuloong-2e/Makefile +++ b/arch/mips/loongson/fuloong-2e/Makefile @@ -2,6 +2,6 @@ # Makefile for Lemote Fuloong2e mini-PC board. # -obj-y += irq.o reset.o machtype.o +obj-y += irq.o reset.o EXTRA_CFLAGS += -Werror -- 1.6.2.1 From wuzhangjin@gmail.com Thu Jul 2 17:33:47 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 02 Jul 2009 17:33:54 +0200 (CEST) Received: from mail-ew0-f214.google.com ([209.85.219.214]:36186 "EHLO mail-ew0-f214.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492214AbZGBPdr (ORCPT ); Thu, 2 Jul 2009 17:33:47 +0200 Received: by ewy10 with SMTP id 10so2102239ewy.0 for ; Thu, 02 Jul 2009 08:27:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer:in-reply-to:references; bh=c3vhbPvHysBLuDCzyKJDYhRqoY7N3vcTbhyInkiDtVA=; b=H8Yqb3yjbe2cWtYpiU2LM6rzqj8+8bCea/96fnPwqG4rVgqyhepyRRvAYz+vh3E2Vd 0bHFM6LTbX4LZKmb8n/BV8Vcp0Lz7qg2Y8pyo9hlAlq1psPaFT+B4KFKzwoCgAA2dH/m 6tyueAp2ZvukAWDXzdmqDHYKxop+H0QjStLNM= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; b=Hvu/Ud5rTebMHzmywB/ylhM+TdxhkUcJiiVAg5TTlockesb14hKy9ivnmtMIphOHty lWwKK+/DOx5ZVS3Uh+KEaBOBAGLrE9AkTFVeXXcGmwlBiWUMoqMzP2MK7HjJHKFrg9Zx bhQnMlnciOowRpRNjaP8m/WncriCVYIdLjRt0= Received: by 10.210.126.18 with SMTP id y18mr1077447ebc.87.1246548476738; Thu, 02 Jul 2009 08:27:56 -0700 (PDT) Received: from localhost.localdomain ([222.92.8.142]) by mx.google.com with ESMTPS id 23sm2131239eya.59.2009.07.02.08.27.49 (version=TLSv1/SSLv3 cipher=RC4-MD5); Thu, 02 Jul 2009 08:27:55 -0700 (PDT) From: Wu Zhangjin To: linux-kernel@vger.kernel.org, linux-mips@linux-mips.org, ralf@linux-mips.org Cc: Wu Zhangjin , Yan Hua , Philippe Vachon , Zhang Le , Zhang Fuxin , loongson-dev , Liu Junliang , Erwan Lerale , Arnaud Patard Subject: [PATCH v4 15/16] [loongson] add gcc 4.4 support for Loongson2E Date: Thu, 2 Jul 2009 23:27:41 +0800 Message-Id: X-Mailer: git-send-email 1.6.2.1 In-Reply-To: References: Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23627 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips because only gcc >=4.4 have loongson-specific support, we need to choose the suitable -march argument for gcc <= 4.3 and gcc >= 4.4, and here, we use -march=loongson2e for loongson2e. thanks goes to Arnaud Patard for suggestion of using cc-options(Documentation/kbuild/makefiles.txt). and thanks Zhang Le for introducing the new CPU_LOONGSON2E kernel option. NOTE: -mtune option is not need if -march and -mtune use the same value. Signed-off-by: Zhang Le Signed-off-by: Wu Zhangjin --- arch/mips/Kconfig | 18 +++++++++++------- arch/mips/Makefile | 6 +++++- arch/mips/loongson/Kconfig | 2 +- 3 files changed, 17 insertions(+), 9 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 482dcc3..466920a 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -1030,12 +1030,10 @@ choice prompt "CPU type" default CPU_R4X00 -config CPU_LOONGSON2 - bool "Loongson 2" - depends on SYS_HAS_CPU_LOONGSON2 - select CPU_SUPPORTS_32BIT_KERNEL - select CPU_SUPPORTS_64BIT_KERNEL - select CPU_SUPPORTS_HIGHMEM +config CPU_LOONGSON2E + bool "Loongson 2E" + depends on SYS_HAS_CPU_LOONGSON2E + select CPU_LOONGSON2 help The Loongson 2E processor implements the MIPS III instruction set with many extensions. @@ -1282,7 +1280,13 @@ config CPU_CAVIUM_OCTEON endchoice -config SYS_HAS_CPU_LOONGSON2 +config CPU_LOONGSON2 + bool + select CPU_SUPPORTS_32BIT_KERNEL + select CPU_SUPPORTS_64BIT_KERNEL + select CPU_SUPPORTS_HIGHMEM + +config SYS_HAS_CPU_LOONGSON2E bool config SYS_HAS_CPU_MIPS32_R1 diff --git a/arch/mips/Makefile b/arch/mips/Makefile index 94d6f58..1efa9aa 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -120,7 +120,11 @@ cflags-$(CONFIG_CPU_R4300) += -march=r4300 -Wa,--trap cflags-$(CONFIG_CPU_VR41XX) += -march=r4100 -Wa,--trap cflags-$(CONFIG_CPU_R4X00) += -march=r4600 -Wa,--trap cflags-$(CONFIG_CPU_TX49XX) += -march=r4600 -Wa,--trap -cflags-$(CONFIG_CPU_LOONGSON2) += -march=r4600 -Wa,--trap +# only gcc >= 4.4 have the loongson-specific support +cflags-$(CONFIG_CPU_LOONGSON2) += -Wa,--trap +cflags-$(CONFIG_CPU_LOONGSON2E) += \ + $(call cc-option,-march=loongson2e,-march=r4600) + cflags-$(CONFIG_CPU_MIPS32_R1) += $(call cc-option,-march=mips32,-mips32 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS32) \ -Wa,-mips32 -Wa,--trap cflags-$(CONFIG_CPU_MIPS32_R2) += $(call cc-option,-march=mips32r2,-mips32r2 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS32) \ diff --git a/arch/mips/loongson/Kconfig b/arch/mips/loongson/Kconfig index 376712a..d450925 100644 --- a/arch/mips/loongson/Kconfig +++ b/arch/mips/loongson/Kconfig @@ -7,7 +7,7 @@ config LEMOTE_FULOONG2E select ARCH_SPARSEMEM_ENABLE select CEVT_R4K select CSRC_R4K - select SYS_HAS_CPU_LOONGSON2 + select SYS_HAS_CPU_LOONGSON2E select DMA_NONCOHERENT select BOOT_ELF32 select BOARD_SCACHE -- 1.6.2.1 From wuzhangjin@gmail.com Thu Jul 2 17:34:11 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 02 Jul 2009 17:34:21 +0200 (CEST) Received: from mail-ew0-f214.google.com ([209.85.219.214]:36186 "EHLO mail-ew0-f214.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492219AbZGBPeG (ORCPT ); Thu, 2 Jul 2009 17:34:06 +0200 Received: by mail-ew0-f214.google.com with SMTP id 10so2102239ewy.0 for ; Thu, 02 Jul 2009 08:28:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer:in-reply-to:references; bh=WZL7XSL7YOiHbcj4GWqTkG65BWoNgqnNK/xDVaDU7MI=; b=dD6TU6I23bxECU24ziuf15vvuBLwO/nCSevilLEaxFAs6qDh4moXkXD8Lm3vOOX6qP V7LdtruV8HR8TectqGkni/HyPlrrquXRJdvao6bjz1OG/rA0Nz9klPVRLSBU171zO2ch gD+HYDBHOCNe8Uo8+00RZ1V9PXFOy6RWkgkmg= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; b=YuCqYq5+iZ/S37cIOOy2/diUd8WCfOydj5GmZNlKiTT8gSLDOt214+3K8v2bbnOjdW DRp/4muz3oS0E2bxCEP6xpN3QTmd9Z8KGxbeON860rX8oJZapiF4QuZoGkZL917bSl7o N8ph1LtFpvYFV9coci595wUyK9W0OxIjMYP34= Received: by 10.210.91.7 with SMTP id o7mr1119527ebb.25.1246548500717; Thu, 02 Jul 2009 08:28:20 -0700 (PDT) Received: from localhost.localdomain ([222.92.8.142]) by mx.google.com with ESMTPS id 10sm5073829eyz.51.2009.07.02.08.28.11 (version=TLSv1/SSLv3 cipher=RC4-MD5); Thu, 02 Jul 2009 08:28:18 -0700 (PDT) From: Wu Zhangjin To: linux-kernel@vger.kernel.org, linux-mips@linux-mips.org, ralf@linux-mips.org Cc: Wu Zhangjin , Yan Hua , Philippe Vachon , Zhang Le , Zhang Fuxin , loongson-dev , Liu Junliang , Erwan Lerale , Arnaud Patard Subject: [PATCH v4 16/16] [loongson] update the default config file for fuloong2e Date: Thu, 2 Jul 2009 23:28:04 +0800 Message-Id: X-Mailer: git-send-email 1.6.2.1 In-Reply-To: References: Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23628 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips Signed-off-by: Wu Zhangjin --- arch/mips/configs/fulong_defconfig | 1912 --------------------------------- arch/mips/configs/fuloong2e_defconfig | 1819 +++++++++++++++++++++++++++++++ 2 files changed, 1819 insertions(+), 1912 deletions(-) delete mode 100644 arch/mips/configs/fulong_defconfig create mode 100644 arch/mips/configs/fuloong2e_defconfig diff --git a/arch/mips/configs/fulong_defconfig b/arch/mips/configs/fulong_defconfig deleted file mode 100644 index 786a9bc..0000000 --- a/arch/mips/configs/fulong_defconfig +++ /dev/null @@ -1,1912 +0,0 @@ -# -# Automatically generated make config: don't edit -# Linux kernel version: 2.6.28-rc6 -# Fri Nov 28 17:53:48 2008 -# -CONFIG_MIPS=y - -# -# Machine selection -# -# CONFIG_MACH_ALCHEMY is not set -# CONFIG_BASLER_EXCITE is not set -# CONFIG_BCM47XX is not set -# CONFIG_MIPS_COBALT is not set -# CONFIG_MACH_DECSTATION is not set -# CONFIG_MACH_JAZZ is not set -# CONFIG_LASAT is not set -CONFIG_LEMOTE_FULONG=y -# CONFIG_MIPS_MALTA is not set -# CONFIG_MIPS_SIM is not set -# CONFIG_MACH_EMMA is not set -# CONFIG_MACH_VR41XX is not set -# CONFIG_NXP_STB220 is not set -# CONFIG_NXP_STB225 is not set -# CONFIG_PNX8550_JBS is not set -# CONFIG_PNX8550_STB810 is not set -# CONFIG_PMC_MSP is not set -# CONFIG_PMC_YOSEMITE is not set -# CONFIG_SGI_IP22 is not set -# CONFIG_SGI_IP27 is not set -# CONFIG_SGI_IP28 is not set -# CONFIG_SGI_IP32 is not set -# CONFIG_SIBYTE_CRHINE is not set -# CONFIG_SIBYTE_CARMEL is not set -# CONFIG_SIBYTE_CRHONE is not set -# CONFIG_SIBYTE_RHONE is not set -# CONFIG_SIBYTE_SWARM is not set -# CONFIG_SIBYTE_LITTLESUR is not set -# CONFIG_SIBYTE_SENTOSA is not set -# CONFIG_SIBYTE_BIGSUR is not set -# CONFIG_SNI_RM is not set -# CONFIG_MACH_TX39XX is not set -# CONFIG_MACH_TX49XX is not set -# CONFIG_MIKROTIK_RB532 is not set -# CONFIG_WR_PPMC is not set -CONFIG_RWSEM_GENERIC_SPINLOCK=y -# CONFIG_ARCH_HAS_ILOG2_U32 is not set -# CONFIG_ARCH_HAS_ILOG2_U64 is not set -CONFIG_ARCH_SUPPORTS_OPROFILE=y -CONFIG_GENERIC_FIND_NEXT_BIT=y -CONFIG_GENERIC_HWEIGHT=y -CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_TIME=y -CONFIG_GENERIC_CMOS_UPDATE=y -CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y -CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y -CONFIG_CEVT_R4K=y -CONFIG_CSRC_R4K=y -CONFIG_DMA_NONCOHERENT=y -CONFIG_DMA_NEED_PCI_MAP_STATE=y -CONFIG_EARLY_PRINTK=y -CONFIG_SYS_HAS_EARLY_PRINTK=y -# CONFIG_HOTPLUG_CPU is not set -CONFIG_I8259=y -# CONFIG_NO_IOPORT is not set -CONFIG_GENERIC_ISA_DMA=y -CONFIG_GENERIC_ISA_DMA_SUPPORT_BROKEN=y -# CONFIG_CPU_BIG_ENDIAN is not set -CONFIG_CPU_LITTLE_ENDIAN=y -CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y -CONFIG_IRQ_CPU=y -CONFIG_BOOT_ELF32=y -CONFIG_MIPS_L1_CACHE_SHIFT=5 -CONFIG_HAVE_STD_PC_SERIAL_PORT=y - -# -# CPU selection -# -CONFIG_CPU_LOONGSON2=y -# CONFIG_CPU_MIPS32_R1 is not set -# CONFIG_CPU_MIPS32_R2 is not set -# CONFIG_CPU_MIPS64_R1 is not set -# CONFIG_CPU_MIPS64_R2 is not set -# CONFIG_CPU_R3000 is not set -# CONFIG_CPU_TX39XX is not set -# CONFIG_CPU_VR41XX is not set -# CONFIG_CPU_R4300 is not set -# CONFIG_CPU_R4X00 is not set -# CONFIG_CPU_TX49XX is not set -# CONFIG_CPU_R5000 is not set -# CONFIG_CPU_R5432 is not set -# CONFIG_CPU_R5500 is not set -# CONFIG_CPU_R6000 is not set -# CONFIG_CPU_NEVADA is not set -# CONFIG_CPU_R8000 is not set -# CONFIG_CPU_R10000 is not set -# CONFIG_CPU_RM7000 is not set -# CONFIG_CPU_RM9000 is not set -# CONFIG_CPU_SB1 is not set -CONFIG_SYS_HAS_CPU_LOONGSON2=y -CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y -CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y -CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y -CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y - -# -# Kernel type -# -# CONFIG_32BIT is not set -CONFIG_64BIT=y -# CONFIG_PAGE_SIZE_4KB is not set -# CONFIG_PAGE_SIZE_8KB is not set -CONFIG_PAGE_SIZE_16KB=y -# CONFIG_PAGE_SIZE_64KB is not set -CONFIG_BOARD_SCACHE=y -CONFIG_MIPS_MT_DISABLED=y -# CONFIG_MIPS_MT_SMP is not set -# CONFIG_MIPS_MT_SMTC is not set -CONFIG_CPU_HAS_WB=y -CONFIG_CPU_HAS_SYNC=y -CONFIG_GENERIC_HARDIRQS=y -CONFIG_GENERIC_IRQ_PROBE=y -CONFIG_CPU_SUPPORTS_HIGHMEM=y -CONFIG_SYS_SUPPORTS_HIGHMEM=y -CONFIG_ARCH_FLATMEM_ENABLE=y -CONFIG_ARCH_POPULATES_NODE_MAP=y -CONFIG_ARCH_SPARSEMEM_ENABLE=y -CONFIG_SELECT_MEMORY_MODEL=y -CONFIG_FLATMEM_MANUAL=y -# CONFIG_DISCONTIGMEM_MANUAL is not set -# CONFIG_SPARSEMEM_MANUAL is not set -CONFIG_FLATMEM=y -CONFIG_FLAT_NODE_MEM_MAP=y -CONFIG_SPARSEMEM_STATIC=y -CONFIG_PAGEFLAGS_EXTENDED=y -CONFIG_SPLIT_PTLOCK_CPUS=4 -CONFIG_RESOURCES_64BIT=y -CONFIG_PHYS_ADDR_T_64BIT=y -CONFIG_ZONE_DMA_FLAG=0 -CONFIG_VIRT_TO_BUS=y -CONFIG_UNEVICTABLE_LRU=y -CONFIG_TICK_ONESHOT=y -CONFIG_NO_HZ=y -CONFIG_HIGH_RES_TIMERS=y -CONFIG_GENERIC_CLOCKEVENTS_BUILD=y -# CONFIG_HZ_48 is not set -# CONFIG_HZ_100 is not set -# CONFIG_HZ_128 is not set -CONFIG_HZ_250=y -# CONFIG_HZ_256 is not set -# CONFIG_HZ_1000 is not set -# CONFIG_HZ_1024 is not set -CONFIG_SYS_SUPPORTS_ARBIT_HZ=y -CONFIG_HZ=250 -# CONFIG_PREEMPT_NONE is not set -CONFIG_PREEMPT_VOLUNTARY=y -# CONFIG_PREEMPT is not set -# CONFIG_KEXEC is not set -CONFIG_SECCOMP=y -CONFIG_LOCKDEP_SUPPORT=y -CONFIG_STACKTRACE_SUPPORT=y -CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" - -# -# General setup -# -CONFIG_EXPERIMENTAL=y -CONFIG_BROKEN_ON_SMP=y -CONFIG_INIT_ENV_ARG_LIMIT=32 -CONFIG_LOCALVERSION="lm32" -# CONFIG_LOCALVERSION_AUTO is not set -CONFIG_SWAP=y -CONFIG_SYSVIPC=y -CONFIG_SYSVIPC_SYSCTL=y -CONFIG_POSIX_MQUEUE=y -CONFIG_BSD_PROCESS_ACCT=y -# CONFIG_BSD_PROCESS_ACCT_V3 is not set -# CONFIG_TASKSTATS is not set -# CONFIG_AUDIT is not set -CONFIG_IKCONFIG=y -CONFIG_IKCONFIG_PROC=y -CONFIG_LOG_BUF_SHIFT=14 -# CONFIG_CGROUPS is not set -# CONFIG_GROUP_SCHED is not set -CONFIG_SYSFS_DEPRECATED=y -CONFIG_SYSFS_DEPRECATED_V2=y -# CONFIG_RELAY is not set -CONFIG_NAMESPACES=y -# CONFIG_UTS_NS is not set -# CONFIG_IPC_NS is not set -CONFIG_USER_NS=y -CONFIG_PID_NS=y -# CONFIG_BLK_DEV_INITRD is not set -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_SYSCTL=y -CONFIG_EMBEDDED=y -CONFIG_SYSCTL_SYSCALL=y -CONFIG_KALLSYMS=y -# CONFIG_KALLSYMS_EXTRA_PASS is not set -CONFIG_HOTPLUG=y -CONFIG_PRINTK=y -CONFIG_BUG=y -CONFIG_ELF_CORE=y -# CONFIG_PCSPKR_PLATFORM is not set -# CONFIG_COMPAT_BRK is not set -CONFIG_BASE_FULL=y -CONFIG_FUTEX=y -CONFIG_ANON_INODES=y -CONFIG_EPOLL=y -CONFIG_SIGNALFD=y -CONFIG_TIMERFD=y -CONFIG_EVENTFD=y -CONFIG_SHMEM=y -CONFIG_AIO=y -CONFIG_VM_EVENT_COUNTERS=y -CONFIG_PCI_QUIRKS=y -CONFIG_SLAB=y -# CONFIG_SLUB is not set -# CONFIG_SLOB is not set -CONFIG_PROFILING=y -# CONFIG_MARKERS is not set -CONFIG_OPROFILE=m -CONFIG_HAVE_OPROFILE=y -# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set -CONFIG_SLABINFO=y -CONFIG_RT_MUTEXES=y -# CONFIG_TINY_SHMEM is not set -CONFIG_BASE_SMALL=0 -CONFIG_MODULES=y -# CONFIG_MODULE_FORCE_LOAD is not set -CONFIG_MODULE_UNLOAD=y -CONFIG_MODULE_FORCE_UNLOAD=y -# CONFIG_MODVERSIONS is not set -# CONFIG_MODULE_SRCVERSION_ALL is not set -CONFIG_KMOD=y -CONFIG_BLOCK=y -# CONFIG_BLK_DEV_IO_TRACE is not set -CONFIG_BLK_DEV_BSG=y -# CONFIG_BLK_DEV_INTEGRITY is not set -CONFIG_BLOCK_COMPAT=y - -# -# IO Schedulers -# -CONFIG_IOSCHED_NOOP=y -CONFIG_IOSCHED_AS=y -CONFIG_IOSCHED_DEADLINE=y -CONFIG_IOSCHED_CFQ=y -# CONFIG_DEFAULT_AS is not set -# CONFIG_DEFAULT_DEADLINE is not set -CONFIG_DEFAULT_CFQ=y -# CONFIG_DEFAULT_NOOP is not set -CONFIG_DEFAULT_IOSCHED="cfq" -CONFIG_CLASSIC_RCU=y -CONFIG_FREEZER=y - -# -# Bus options (PCI, PCMCIA, EISA, ISA, TC) -# -CONFIG_HW_HAS_PCI=y -CONFIG_PCI=y -CONFIG_PCI_DOMAINS=y -# CONFIG_ARCH_SUPPORTS_MSI is not set -CONFIG_PCI_LEGACY=y -CONFIG_ISA=y -CONFIG_MMU=y -# CONFIG_PCCARD is not set -# CONFIG_HOTPLUG_PCI is not set - -# -# Executable file formats -# -CONFIG_BINFMT_ELF=y -# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set -# CONFIG_HAVE_AOUT is not set -CONFIG_BINFMT_MISC=y -CONFIG_MIPS32_COMPAT=y -CONFIG_COMPAT=y -CONFIG_SYSVIPC_COMPAT=y -CONFIG_MIPS32_O32=y -CONFIG_MIPS32_N32=y -CONFIG_BINFMT_ELF32=y - -# -# Power management options -# -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_PM=y -# CONFIG_PM_DEBUG is not set -CONFIG_PM_SLEEP=y -CONFIG_SUSPEND=y -CONFIG_SUSPEND_FREEZER=y -CONFIG_NET=y - -# -# Networking options -# -CONFIG_PACKET=y -CONFIG_PACKET_MMAP=y -CONFIG_UNIX=y -CONFIG_XFRM=y -# CONFIG_XFRM_USER is not set -# CONFIG_XFRM_SUB_POLICY is not set -# CONFIG_XFRM_MIGRATE is not set -# CONFIG_XFRM_STATISTICS is not set -# CONFIG_NET_KEY is not set -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -# CONFIG_IP_ADVANCED_ROUTER is not set -CONFIG_IP_FIB_HASH=y -CONFIG_IP_PNP=y -# CONFIG_IP_PNP_DHCP is not set -CONFIG_IP_PNP_BOOTP=y -# CONFIG_IP_PNP_RARP is not set -CONFIG_NET_IPIP=m -CONFIG_NET_IPGRE=m -CONFIG_NET_IPGRE_BROADCAST=y -# CONFIG_IP_MROUTE is not set -# CONFIG_ARPD is not set -# CONFIG_SYN_COOKIES is not set -# CONFIG_INET_AH is not set -# CONFIG_INET_ESP is not set -# CONFIG_INET_IPCOMP is not set -# CONFIG_INET_XFRM_TUNNEL is not set -CONFIG_INET_TUNNEL=m -# CONFIG_INET_XFRM_MODE_TRANSPORT is not set -# CONFIG_INET_XFRM_MODE_TUNNEL is not set -CONFIG_INET_XFRM_MODE_BEET=y -# CONFIG_INET_LRO is not set -# CONFIG_INET_DIAG is not set -# CONFIG_TCP_CONG_ADVANCED is not set -CONFIG_TCP_CONG_CUBIC=y -CONFIG_DEFAULT_TCP_CONG="cubic" -# CONFIG_TCP_MD5SIG is not set -# CONFIG_IPV6 is not set -# CONFIG_NETWORK_SECMARK is not set -CONFIG_NETFILTER=y -# CONFIG_NETFILTER_DEBUG is not set -CONFIG_NETFILTER_ADVANCED=y - -# -# Core Netfilter Configuration -# -CONFIG_NETFILTER_NETLINK=m -CONFIG_NETFILTER_NETLINK_QUEUE=m -CONFIG_NETFILTER_NETLINK_LOG=m -# CONFIG_NF_CONNTRACK is not set -CONFIG_NETFILTER_XTABLES=m -CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m -# CONFIG_NETFILTER_XT_TARGET_DSCP is not set -CONFIG_NETFILTER_XT_TARGET_MARK=m -# CONFIG_NETFILTER_XT_TARGET_NFLOG is not set -CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m -CONFIG_NETFILTER_XT_TARGET_RATEEST=m -CONFIG_NETFILTER_XT_TARGET_TRACE=m -# CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set -CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m -CONFIG_NETFILTER_XT_MATCH_COMMENT=m -CONFIG_NETFILTER_XT_MATCH_DCCP=m -# CONFIG_NETFILTER_XT_MATCH_DSCP is not set -CONFIG_NETFILTER_XT_MATCH_ESP=m -# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set -CONFIG_NETFILTER_XT_MATCH_IPRANGE=m -CONFIG_NETFILTER_XT_MATCH_LENGTH=m -CONFIG_NETFILTER_XT_MATCH_LIMIT=m -CONFIG_NETFILTER_XT_MATCH_MAC=m -CONFIG_NETFILTER_XT_MATCH_MARK=m -CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m -CONFIG_NETFILTER_XT_MATCH_OWNER=m -# CONFIG_NETFILTER_XT_MATCH_POLICY is not set -CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m -CONFIG_NETFILTER_XT_MATCH_QUOTA=m -CONFIG_NETFILTER_XT_MATCH_RATEEST=m -CONFIG_NETFILTER_XT_MATCH_REALM=m -CONFIG_NETFILTER_XT_MATCH_RECENT=m -# CONFIG_NETFILTER_XT_MATCH_RECENT_PROC_COMPAT is not set -CONFIG_NETFILTER_XT_MATCH_SCTP=m -CONFIG_NETFILTER_XT_MATCH_STATISTIC=m -CONFIG_NETFILTER_XT_MATCH_STRING=m -CONFIG_NETFILTER_XT_MATCH_TCPMSS=m -CONFIG_NETFILTER_XT_MATCH_TIME=m -CONFIG_NETFILTER_XT_MATCH_U32=m -# CONFIG_IP_VS is not set - -# -# IP: Netfilter Configuration -# -# CONFIG_NF_DEFRAG_IPV4 is not set -CONFIG_IP_NF_QUEUE=m -CONFIG_IP_NF_IPTABLES=m -CONFIG_IP_NF_MATCH_ADDRTYPE=m -CONFIG_IP_NF_MATCH_AH=m -CONFIG_IP_NF_MATCH_ECN=m -CONFIG_IP_NF_MATCH_TTL=m -CONFIG_IP_NF_FILTER=m -CONFIG_IP_NF_TARGET_REJECT=m -CONFIG_IP_NF_TARGET_LOG=m -CONFIG_IP_NF_TARGET_ULOG=m -CONFIG_IP_NF_MANGLE=m -CONFIG_IP_NF_TARGET_ECN=m -CONFIG_IP_NF_TARGET_TTL=m -CONFIG_IP_NF_RAW=m -CONFIG_IP_NF_ARPTABLES=m -CONFIG_IP_NF_ARPFILTER=m -CONFIG_IP_NF_ARP_MANGLE=m -# CONFIG_IP_DCCP is not set -# CONFIG_IP_SCTP is not set -# CONFIG_TIPC is not set -# CONFIG_ATM is not set -# CONFIG_BRIDGE is not set -# CONFIG_NET_DSA is not set -# CONFIG_VLAN_8021Q is not set -# CONFIG_DECNET is not set -# CONFIG_LLC2 is not set -# CONFIG_IPX is not set -# CONFIG_ATALK is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_ECONET is not set -# CONFIG_WAN_ROUTER is not set -# CONFIG_NET_SCHED is not set -CONFIG_NET_CLS_ROUTE=y - -# -# Network testing -# -# CONFIG_NET_PKTGEN is not set -# CONFIG_HAMRADIO is not set -# CONFIG_CAN is not set -# CONFIG_IRDA is not set -# CONFIG_BT is not set -# CONFIG_AF_RXRPC is not set -CONFIG_PHONET=m -CONFIG_WIRELESS=y -# CONFIG_CFG80211 is not set -CONFIG_WIRELESS_OLD_REGULATORY=y -CONFIG_WIRELESS_EXT=y -CONFIG_WIRELESS_EXT_SYSFS=y -# CONFIG_MAC80211 is not set -CONFIG_IEEE80211=m -# CONFIG_IEEE80211_DEBUG is not set -CONFIG_IEEE80211_CRYPT_WEP=m -# CONFIG_IEEE80211_CRYPT_CCMP is not set -# CONFIG_IEEE80211_CRYPT_TKIP is not set -# CONFIG_RFKILL is not set -CONFIG_NET_9P=m -# CONFIG_NET_9P_DEBUG is not set - -# -# Device Drivers -# - -# -# Generic Driver Options -# -CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" -CONFIG_STANDALONE=y -CONFIG_PREVENT_FIRMWARE_BUILD=y -CONFIG_FW_LOADER=m -CONFIG_FIRMWARE_IN_KERNEL=y -CONFIG_EXTRA_FIRMWARE="" -# CONFIG_SYS_HYPERVISOR is not set -# CONFIG_CONNECTOR is not set -CONFIG_MTD=m -# CONFIG_MTD_DEBUG is not set -# CONFIG_MTD_CONCAT is not set -# CONFIG_MTD_PARTITIONS is not set - -# -# User Modules And Translation Layers -# -CONFIG_MTD_CHAR=m -CONFIG_MTD_BLKDEVS=m -CONFIG_MTD_BLOCK=m -# CONFIG_MTD_BLOCK_RO is not set -# CONFIG_FTL is not set -# CONFIG_NFTL is not set -# CONFIG_INFTL is not set -# CONFIG_RFD_FTL is not set -# CONFIG_SSFDC is not set -# CONFIG_MTD_OOPS is not set - -# -# RAM/ROM/Flash chip drivers -# -CONFIG_MTD_CFI=m -CONFIG_MTD_JEDECPROBE=m -CONFIG_MTD_GEN_PROBE=m -CONFIG_MTD_CFI_ADV_OPTIONS=y -CONFIG_MTD_CFI_NOSWAP=y -# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set -# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set -# CONFIG_MTD_CFI_GEOMETRY is not set -CONFIG_MTD_MAP_BANK_WIDTH_1=y -CONFIG_MTD_MAP_BANK_WIDTH_2=y -CONFIG_MTD_MAP_BANK_WIDTH_4=y -# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set -# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set -# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set -CONFIG_MTD_CFI_I1=y -CONFIG_MTD_CFI_I2=y -# CONFIG_MTD_CFI_I4 is not set -# CONFIG_MTD_CFI_I8 is not set -# CONFIG_MTD_OTP is not set -# CONFIG_MTD_CFI_INTELEXT is not set -CONFIG_MTD_CFI_AMDSTD=m -CONFIG_MTD_CFI_STAA=m -CONFIG_MTD_CFI_UTIL=m -# CONFIG_MTD_RAM is not set -# CONFIG_MTD_ROM is not set -# CONFIG_MTD_ABSENT is not set - -# -# Mapping drivers for chip access -# -# CONFIG_MTD_COMPLEX_MAPPINGS is not set -CONFIG_MTD_PHYSMAP=m -CONFIG_MTD_PHYSMAP_START=0x1fc00000 -CONFIG_MTD_PHYSMAP_LEN=0x80000 -CONFIG_MTD_PHYSMAP_BANKWIDTH=1 -# CONFIG_MTD_INTEL_VR_NOR is not set -# CONFIG_MTD_PLATRAM is not set - -# -# Self-contained MTD device drivers -# -# CONFIG_MTD_PMC551 is not set -# CONFIG_MTD_SLRAM is not set -# CONFIG_MTD_PHRAM is not set -# CONFIG_MTD_MTDRAM is not set -# CONFIG_MTD_BLOCK2MTD is not set - -# -# Disk-On-Chip Device Drivers -# -# CONFIG_MTD_DOC2000 is not set -# CONFIG_MTD_DOC2001 is not set -# CONFIG_MTD_DOC2001PLUS is not set -# CONFIG_MTD_NAND is not set -# CONFIG_MTD_ONENAND is not set - -# -# UBI - Unsorted block images -# -# CONFIG_MTD_UBI is not set -# CONFIG_PARPORT is not set -# CONFIG_PNP is not set -CONFIG_BLK_DEV=y -# CONFIG_BLK_CPQ_DA is not set -# CONFIG_BLK_CPQ_CISS_DA is not set -# CONFIG_BLK_DEV_DAC960 is not set -# CONFIG_BLK_DEV_UMEM is not set -# CONFIG_BLK_DEV_COW_COMMON is not set -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_CRYPTOLOOP=m -# CONFIG_BLK_DEV_NBD is not set -# CONFIG_BLK_DEV_SX8 is not set -# CONFIG_BLK_DEV_UB is not set -CONFIG_BLK_DEV_RAM=m -CONFIG_BLK_DEV_RAM_COUNT=16 -CONFIG_BLK_DEV_RAM_SIZE=4096 -# CONFIG_BLK_DEV_XIP is not set -CONFIG_CDROM_PKTCDVD=m -CONFIG_CDROM_PKTCDVD_BUFFERS=8 -# CONFIG_CDROM_PKTCDVD_WCACHE is not set -CONFIG_ATA_OVER_ETH=m -# CONFIG_BLK_DEV_HD is not set -# CONFIG_MISC_DEVICES is not set -CONFIG_HAVE_IDE=y -CONFIG_IDE=y - -# -# Please see Documentation/ide/ide.txt for help/info on IDE drives -# -CONFIG_IDE_TIMINGS=y -CONFIG_IDE_ATAPI=y -# CONFIG_BLK_DEV_IDE_SATA is not set -CONFIG_IDE_GD=y -CONFIG_IDE_GD_ATA=y -# CONFIG_IDE_GD_ATAPI is not set -CONFIG_BLK_DEV_IDECD=y -CONFIG_BLK_DEV_IDECD_VERBOSE_ERRORS=y -# CONFIG_BLK_DEV_IDETAPE is not set -CONFIG_BLK_DEV_IDESCSI=y -CONFIG_IDE_TASK_IOCTL=y -CONFIG_IDE_PROC_FS=y - -# -# IDE chipset support/bugfixes -# -CONFIG_IDE_GENERIC=y -# CONFIG_BLK_DEV_PLATFORM is not set -CONFIG_BLK_DEV_IDEDMA_SFF=y - -# -# PCI IDE chipsets support -# -CONFIG_BLK_DEV_IDEPCI=y -CONFIG_IDEPCI_PCIBUS_ORDER=y -# CONFIG_BLK_DEV_OFFBOARD is not set -CONFIG_BLK_DEV_GENERIC=y -# CONFIG_BLK_DEV_OPTI621 is not set -CONFIG_BLK_DEV_IDEDMA_PCI=y -# CONFIG_BLK_DEV_AEC62XX is not set -# CONFIG_BLK_DEV_ALI15X3 is not set -# CONFIG_BLK_DEV_AMD74XX is not set -# CONFIG_BLK_DEV_CMD64X is not set -# CONFIG_BLK_DEV_TRIFLEX is not set -# CONFIG_BLK_DEV_CS5520 is not set -# CONFIG_BLK_DEV_CS5530 is not set -# CONFIG_BLK_DEV_HPT366 is not set -# CONFIG_BLK_DEV_JMICRON is not set -# CONFIG_BLK_DEV_SC1200 is not set -# CONFIG_BLK_DEV_PIIX is not set -# CONFIG_BLK_DEV_IT8213 is not set -# CONFIG_BLK_DEV_IT821X is not set -# CONFIG_BLK_DEV_NS87415 is not set -# CONFIG_BLK_DEV_PDC202XX_OLD is not set -# CONFIG_BLK_DEV_PDC202XX_NEW is not set -# CONFIG_BLK_DEV_SVWKS is not set -# CONFIG_BLK_DEV_SIIMAGE is not set -# CONFIG_BLK_DEV_SLC90E66 is not set -# CONFIG_BLK_DEV_TRM290 is not set -CONFIG_BLK_DEV_VIA82CXXX=y -# CONFIG_BLK_DEV_TC86C001 is not set - -# -# Other IDE chipsets support -# - -# -# Note: most of these also require special kernel boot parameters -# -# CONFIG_BLK_DEV_4DRIVES is not set -# CONFIG_BLK_DEV_ALI14XX is not set -# CONFIG_BLK_DEV_DTC2278 is not set -# CONFIG_BLK_DEV_HT6560B is not set -# CONFIG_BLK_DEV_QD65XX is not set -# CONFIG_BLK_DEV_UMC8672 is not set -CONFIG_BLK_DEV_IDEDMA=y - -# -# SCSI device support -# -# CONFIG_RAID_ATTRS is not set -CONFIG_SCSI=y -CONFIG_SCSI_DMA=y -# CONFIG_SCSI_TGT is not set -# CONFIG_SCSI_NETLINK is not set -CONFIG_SCSI_PROC_FS=y - -# -# SCSI support type (disk, tape, CD-ROM) -# -CONFIG_BLK_DEV_SD=y -# CONFIG_CHR_DEV_ST is not set -# CONFIG_CHR_DEV_OSST is not set -CONFIG_BLK_DEV_SR=y -CONFIG_BLK_DEV_SR_VENDOR=y -CONFIG_CHR_DEV_SG=y -# CONFIG_CHR_DEV_SCH is not set - -# -# Some SCSI devices (e.g. CD jukebox) support multiple LUNs -# -# CONFIG_SCSI_MULTI_LUN is not set -CONFIG_SCSI_CONSTANTS=y -# CONFIG_SCSI_LOGGING is not set -# CONFIG_SCSI_SCAN_ASYNC is not set -CONFIG_SCSI_WAIT_SCAN=m - -# -# SCSI Transports -# -# CONFIG_SCSI_SPI_ATTRS is not set -# CONFIG_SCSI_FC_ATTRS is not set -# CONFIG_SCSI_ISCSI_ATTRS is not set -# CONFIG_SCSI_SAS_ATTRS is not set -# CONFIG_SCSI_SAS_LIBSAS is not set -# CONFIG_SCSI_SRP_ATTRS is not set -# CONFIG_SCSI_LOWLEVEL is not set -# CONFIG_SCSI_DH is not set -# CONFIG_ATA is not set -# CONFIG_MD is not set -# CONFIG_FUSION is not set - -# -# IEEE 1394 (FireWire) support -# - -# -# Enable only one of the two stacks, unless you know what you are doing -# -# CONFIG_FIREWIRE is not set -# CONFIG_IEEE1394 is not set -# CONFIG_I2O is not set -CONFIG_NETDEVICES=y -# CONFIG_DUMMY is not set -# CONFIG_BONDING is not set -CONFIG_MACVLAN=m -# CONFIG_EQUALIZER is not set -# CONFIG_TUN is not set -CONFIG_VETH=m -# CONFIG_ARCNET is not set -CONFIG_PHYLIB=m - -# -# MII PHY device drivers -# -CONFIG_MARVELL_PHY=m -CONFIG_DAVICOM_PHY=m -CONFIG_QSEMI_PHY=m -CONFIG_LXT_PHY=m -CONFIG_CICADA_PHY=m -# CONFIG_VITESSE_PHY is not set -# CONFIG_SMSC_PHY is not set -# CONFIG_BROADCOM_PHY is not set -# CONFIG_ICPLUS_PHY is not set -# CONFIG_REALTEK_PHY is not set -# CONFIG_MDIO_BITBANG is not set -CONFIG_NET_ETHERNET=y -CONFIG_MII=y -# CONFIG_AX88796 is not set -# CONFIG_HAPPYMEAL is not set -# CONFIG_SUNGEM is not set -# CONFIG_CASSINI is not set -# CONFIG_NET_VENDOR_3COM is not set -# CONFIG_NET_VENDOR_SMC is not set -# CONFIG_SMC91X is not set -# CONFIG_DM9000 is not set -# CONFIG_NET_VENDOR_RACAL is not set -# CONFIG_NET_TULIP is not set -# CONFIG_AT1700 is not set -# CONFIG_DEPCA is not set -# CONFIG_HP100 is not set -# CONFIG_NET_ISA is not set -# CONFIG_IBM_NEW_EMAC_ZMII is not set -# CONFIG_IBM_NEW_EMAC_RGMII is not set -# CONFIG_IBM_NEW_EMAC_TAH is not set -# CONFIG_IBM_NEW_EMAC_EMAC4 is not set -# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set -# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set -# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set -CONFIG_NET_PCI=y -# CONFIG_PCNET32 is not set -# CONFIG_AMD8111_ETH is not set -# CONFIG_ADAPTEC_STARFIRE is not set -# CONFIG_AC3200 is not set -# CONFIG_APRICOT is not set -# CONFIG_B44 is not set -# CONFIG_FORCEDETH is not set -# CONFIG_CS89x0 is not set -# CONFIG_TC35815 is not set -# CONFIG_EEPRO100 is not set -# CONFIG_E100 is not set -# CONFIG_FEALNX is not set -# CONFIG_NATSEMI is not set -# CONFIG_NE2K_PCI is not set -# CONFIG_8139CP is not set -CONFIG_8139TOO=y -# CONFIG_8139TOO_PIO is not set -# CONFIG_8139TOO_TUNE_TWISTER is not set -# CONFIG_8139TOO_8129 is not set -# CONFIG_8139_OLD_RX_RESET is not set -# CONFIG_R6040 is not set -# CONFIG_SIS900 is not set -# CONFIG_EPIC100 is not set -# CONFIG_SUNDANCE is not set -# CONFIG_TLAN is not set -# CONFIG_VIA_RHINE is not set -# CONFIG_SC92031 is not set -# CONFIG_ATL2 is not set -CONFIG_NETDEV_1000=y -# CONFIG_ACENIC is not set -# CONFIG_DL2K is not set -# CONFIG_E1000 is not set -# CONFIG_E1000E is not set -# CONFIG_IP1000 is not set -# CONFIG_IGB is not set -# CONFIG_NS83820 is not set -# CONFIG_HAMACHI is not set -# CONFIG_YELLOWFIN is not set -# CONFIG_R8169 is not set -# CONFIG_SIS190 is not set -# CONFIG_SKGE is not set -# CONFIG_SKY2 is not set -# CONFIG_VIA_VELOCITY is not set -# CONFIG_TIGON3 is not set -# CONFIG_BNX2 is not set -# CONFIG_QLA3XXX is not set -# CONFIG_ATL1 is not set -# CONFIG_ATL1E is not set -# CONFIG_JME is not set -CONFIG_NETDEV_10000=y -# CONFIG_CHELSIO_T1 is not set -# CONFIG_CHELSIO_T3 is not set -# CONFIG_ENIC is not set -# CONFIG_IXGBE is not set -# CONFIG_IXGB is not set -# CONFIG_S2IO is not set -# CONFIG_MYRI10GE is not set -# CONFIG_NETXEN_NIC is not set -# CONFIG_NIU is not set -# CONFIG_MLX4_EN is not set -# CONFIG_MLX4_CORE is not set -# CONFIG_TEHUTI is not set -# CONFIG_BNX2X is not set -# CONFIG_QLGE is not set -# CONFIG_SFC is not set -# CONFIG_TR is not set - -# -# Wireless LAN -# -# CONFIG_WLAN_PRE80211 is not set -# CONFIG_WLAN_80211 is not set -# CONFIG_IWLWIFI_LEDS is not set - -# -# USB Network Adapters -# -# CONFIG_USB_CATC is not set -# CONFIG_USB_KAWETH is not set -# CONFIG_USB_PEGASUS is not set -# CONFIG_USB_RTL8150 is not set -# CONFIG_USB_USBNET is not set -# CONFIG_WAN is not set -# CONFIG_FDDI is not set -# CONFIG_HIPPI is not set -CONFIG_PPP=m -CONFIG_PPP_MULTILINK=y -CONFIG_PPP_FILTER=y -CONFIG_PPP_ASYNC=m -CONFIG_PPP_SYNC_TTY=m -CONFIG_PPP_DEFLATE=m -CONFIG_PPP_BSDCOMP=m -CONFIG_PPP_MPPE=m -CONFIG_PPPOE=m -CONFIG_PPPOL2TP=m -CONFIG_SLIP=m -CONFIG_SLIP_COMPRESSED=y -CONFIG_SLHC=m -CONFIG_SLIP_SMART=y -CONFIG_SLIP_MODE_SLIP6=y -CONFIG_NET_FC=y -# CONFIG_NETCONSOLE is not set -# CONFIG_NETPOLL is not set -# CONFIG_NET_POLL_CONTROLLER is not set -# CONFIG_ISDN is not set -# CONFIG_PHONE is not set - -# -# Input device support -# -CONFIG_INPUT=y -CONFIG_INPUT_FF_MEMLESS=y -# CONFIG_INPUT_POLLDEV is not set - -# -# Userland interfaces -# -CONFIG_INPUT_MOUSEDEV=y -CONFIG_INPUT_MOUSEDEV_PSAUX=y -CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 -CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 -# CONFIG_INPUT_JOYDEV is not set -# CONFIG_INPUT_EVDEV is not set -# CONFIG_INPUT_EVBUG is not set - -# -# Input Device Drivers -# -CONFIG_INPUT_KEYBOARD=y -CONFIG_KEYBOARD_ATKBD=m -# CONFIG_KEYBOARD_SUNKBD is not set -# CONFIG_KEYBOARD_LKKBD is not set -# CONFIG_KEYBOARD_XTKBD is not set -# CONFIG_KEYBOARD_NEWTON is not set -# CONFIG_KEYBOARD_STOWAWAY is not set -CONFIG_INPUT_MOUSE=y -CONFIG_MOUSE_PS2=y -CONFIG_MOUSE_PS2_ALPS=y -CONFIG_MOUSE_PS2_LOGIPS2PP=y -CONFIG_MOUSE_PS2_SYNAPTICS=y -CONFIG_MOUSE_PS2_LIFEBOOK=y -CONFIG_MOUSE_PS2_TRACKPOINT=y -# CONFIG_MOUSE_PS2_ELANTECH is not set -# CONFIG_MOUSE_PS2_TOUCHKIT is not set -CONFIG_MOUSE_SERIAL=y -# CONFIG_MOUSE_APPLETOUCH is not set -# CONFIG_MOUSE_BCM5974 is not set -# CONFIG_MOUSE_INPORT is not set -# CONFIG_MOUSE_LOGIBM is not set -# CONFIG_MOUSE_PC110PAD is not set -# CONFIG_MOUSE_VSXXXAA is not set -# CONFIG_INPUT_JOYSTICK is not set -# CONFIG_INPUT_TABLET is not set -# CONFIG_INPUT_TOUCHSCREEN is not set -# CONFIG_INPUT_MISC is not set - -# -# Hardware I/O ports -# -CONFIG_SERIO=y -CONFIG_SERIO_I8042=y -CONFIG_SERIO_SERPORT=y -# CONFIG_SERIO_PCIPS2 is not set -CONFIG_SERIO_LIBPS2=y -# CONFIG_SERIO_RAW is not set -# CONFIG_GAMEPORT is not set - -# -# Character devices -# -CONFIG_VT=y -CONFIG_CONSOLE_TRANSLATIONS=y -CONFIG_VT_CONSOLE=y -CONFIG_HW_CONSOLE=y -# CONFIG_VT_HW_CONSOLE_BINDING is not set -CONFIG_DEVKMEM=y -# CONFIG_SERIAL_NONSTANDARD is not set -# CONFIG_NOZOMI is not set - -# -# Serial drivers -# -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_PCI=y -CONFIG_SERIAL_8250_NR_UARTS=2 -CONFIG_SERIAL_8250_RUNTIME_UARTS=2 -# CONFIG_SERIAL_8250_EXTENDED is not set - -# -# Non-8250 serial port support -# -CONFIG_SERIAL_CORE=y -CONFIG_SERIAL_CORE_CONSOLE=y -# CONFIG_SERIAL_JSM is not set -CONFIG_UNIX98_PTYS=y -CONFIG_LEGACY_PTYS=y -CONFIG_LEGACY_PTY_COUNT=256 -# CONFIG_IPMI_HANDLER is not set -CONFIG_HW_RANDOM=y -# CONFIG_DTLK is not set -# CONFIG_R3964 is not set -# CONFIG_APPLICOM is not set -# CONFIG_RAW_DRIVER is not set -# CONFIG_TCG_TPM is not set -CONFIG_DEVPORT=y -CONFIG_I2C=m -CONFIG_I2C_BOARDINFO=y -CONFIG_I2C_CHARDEV=m -CONFIG_I2C_HELPER_AUTO=y - -# -# I2C Hardware Bus support -# - -# -# PC SMBus host controller drivers -# -# CONFIG_I2C_ALI1535 is not set -# CONFIG_I2C_ALI1563 is not set -# CONFIG_I2C_ALI15X3 is not set -# CONFIG_I2C_AMD756 is not set -# CONFIG_I2C_AMD8111 is not set -# CONFIG_I2C_I801 is not set -# CONFIG_I2C_ISCH is not set -# CONFIG_I2C_PIIX4 is not set -# CONFIG_I2C_NFORCE2 is not set -# CONFIG_I2C_SIS5595 is not set -# CONFIG_I2C_SIS630 is not set -# CONFIG_I2C_SIS96X is not set -# CONFIG_I2C_VIA is not set -CONFIG_I2C_VIAPRO=m - -# -# I2C system bus drivers (mostly embedded / system-on-chip) -# -# CONFIG_I2C_OCORES is not set -# CONFIG_I2C_SIMTEC is not set - -# -# External I2C/SMBus adapter drivers -# -# CONFIG_I2C_PARPORT_LIGHT is not set -# CONFIG_I2C_TAOS_EVM is not set -# CONFIG_I2C_TINY_USB is not set - -# -# Graphics adapter I2C/DDC channel drivers -# -# CONFIG_I2C_VOODOO3 is not set - -# -# Other I2C/SMBus bus drivers -# -# CONFIG_I2C_ELEKTOR is not set -# CONFIG_I2C_PCA_ISA is not set -# CONFIG_I2C_PCA_PLATFORM is not set -# CONFIG_I2C_STUB is not set - -# -# Miscellaneous I2C Chip support -# -# CONFIG_DS1682 is not set -# CONFIG_EEPROM_AT24 is not set -# CONFIG_EEPROM_LEGACY is not set -# CONFIG_SENSORS_PCF8574 is not set -# CONFIG_PCF8575 is not set -# CONFIG_SENSORS_PCA9539 is not set -# CONFIG_SENSORS_PCF8591 is not set -# CONFIG_SENSORS_MAX6875 is not set -# CONFIG_SENSORS_TSL2550 is not set -# CONFIG_I2C_DEBUG_CORE is not set -# CONFIG_I2C_DEBUG_ALGO is not set -# CONFIG_I2C_DEBUG_BUS is not set -# CONFIG_I2C_DEBUG_CHIP is not set -# CONFIG_SPI is not set -# CONFIG_W1 is not set -# CONFIG_POWER_SUPPLY is not set -# CONFIG_HWMON is not set -# CONFIG_THERMAL is not set -# CONFIG_THERMAL_HWMON is not set -# CONFIG_WATCHDOG is not set -CONFIG_SSB_POSSIBLE=y - -# -# Sonics Silicon Backplane -# -# CONFIG_SSB is not set - -# -# Multifunction device drivers -# -# CONFIG_MFD_CORE is not set -# CONFIG_MFD_SM501 is not set -# CONFIG_HTC_PASIC3 is not set -# CONFIG_MFD_TMIO is not set -# CONFIG_MFD_WM8400 is not set -# CONFIG_MFD_WM8350_I2C is not set -# CONFIG_REGULATOR is not set - -# -# Multimedia devices -# - -# -# Multimedia core support -# -CONFIG_VIDEO_DEV=m -CONFIG_VIDEO_V4L2_COMMON=m -CONFIG_VIDEO_ALLOW_V4L1=y -CONFIG_VIDEO_V4L1_COMPAT=y -# CONFIG_DVB_CORE is not set -CONFIG_VIDEO_MEDIA=m - -# -# Multimedia drivers -# -CONFIG_MEDIA_ATTACH=y -CONFIG_MEDIA_TUNER=m -CONFIG_MEDIA_TUNER_CUSTOMIZE=y -CONFIG_MEDIA_TUNER_SIMPLE=m -CONFIG_MEDIA_TUNER_TDA8290=m -CONFIG_MEDIA_TUNER_TDA827X=m -CONFIG_MEDIA_TUNER_TDA18271=m -CONFIG_MEDIA_TUNER_TDA9887=m -CONFIG_MEDIA_TUNER_TEA5761=m -CONFIG_MEDIA_TUNER_TEA5767=m -CONFIG_MEDIA_TUNER_MT20XX=m -CONFIG_MEDIA_TUNER_MT2060=m -CONFIG_MEDIA_TUNER_MT2266=m -CONFIG_MEDIA_TUNER_MT2131=m -CONFIG_MEDIA_TUNER_QT1010=m -CONFIG_MEDIA_TUNER_XC2028=m -CONFIG_MEDIA_TUNER_XC5000=m -CONFIG_MEDIA_TUNER_MXL5005S=m -CONFIG_MEDIA_TUNER_MXL5007T=m -CONFIG_VIDEO_V4L2=m -CONFIG_VIDEO_V4L1=m -CONFIG_VIDEOBUF_GEN=m -CONFIG_VIDEOBUF_VMALLOC=m -CONFIG_VIDEOBUF_DMA_CONTIG=m -CONFIG_VIDEO_CAPTURE_DRIVERS=y -# CONFIG_VIDEO_ADV_DEBUG is not set -# CONFIG_VIDEO_FIXED_MINOR_RANGES is not set -CONFIG_VIDEO_HELPER_CHIPS_AUTO=y -# CONFIG_VIDEO_VIVI is not set -# CONFIG_VIDEO_BT848 is not set -# CONFIG_VIDEO_PMS is not set -# CONFIG_VIDEO_CPIA is not set -# CONFIG_VIDEO_CPIA2 is not set -# CONFIG_VIDEO_SAA5246A is not set -# CONFIG_VIDEO_SAA5249 is not set -# CONFIG_VIDEO_STRADIS is not set -# CONFIG_VIDEO_SAA7134 is not set -# CONFIG_VIDEO_MXB is not set -# CONFIG_VIDEO_HEXIUM_ORION is not set -# CONFIG_VIDEO_HEXIUM_GEMINI is not set -# CONFIG_VIDEO_CX88 is not set -# CONFIG_VIDEO_IVTV is not set -# CONFIG_VIDEO_CAFE_CCIC is not set -CONFIG_SOC_CAMERA=m -CONFIG_SOC_CAMERA_MT9M001=m -CONFIG_SOC_CAMERA_MT9M111=m -CONFIG_SOC_CAMERA_MT9V022=m -CONFIG_SOC_CAMERA_PLATFORM=m -CONFIG_VIDEO_SH_MOBILE_CEU=m -CONFIG_V4L_USB_DRIVERS=y -CONFIG_USB_VIDEO_CLASS=m -CONFIG_USB_VIDEO_CLASS_INPUT_EVDEV=y -CONFIG_USB_GSPCA=m -CONFIG_USB_M5602=m -CONFIG_USB_GSPCA_CONEX=m -CONFIG_USB_GSPCA_ETOMS=m -CONFIG_USB_GSPCA_FINEPIX=m -CONFIG_USB_GSPCA_MARS=m -CONFIG_USB_GSPCA_OV519=m -CONFIG_USB_GSPCA_PAC207=m -CONFIG_USB_GSPCA_PAC7311=m -CONFIG_USB_GSPCA_SONIXB=m -CONFIG_USB_GSPCA_SONIXJ=m -CONFIG_USB_GSPCA_SPCA500=m -CONFIG_USB_GSPCA_SPCA501=m -CONFIG_USB_GSPCA_SPCA505=m -CONFIG_USB_GSPCA_SPCA506=m -CONFIG_USB_GSPCA_SPCA508=m -CONFIG_USB_GSPCA_SPCA561=m -CONFIG_USB_GSPCA_STK014=m -CONFIG_USB_GSPCA_SUNPLUS=m -CONFIG_USB_GSPCA_T613=m -CONFIG_USB_GSPCA_TV8532=m -CONFIG_USB_GSPCA_VC032X=m -CONFIG_USB_GSPCA_ZC3XX=m -# CONFIG_VIDEO_PVRUSB2 is not set -# CONFIG_VIDEO_EM28XX is not set -# CONFIG_VIDEO_USBVISION is not set -CONFIG_VIDEO_USBVIDEO=m -CONFIG_USB_VICAM=m -CONFIG_USB_IBMCAM=m -CONFIG_USB_KONICAWC=m -CONFIG_USB_QUICKCAM_MESSENGER=m -CONFIG_USB_ET61X251=m -# CONFIG_VIDEO_OVCAMCHIP is not set -CONFIG_USB_OV511=m -CONFIG_USB_SE401=m -CONFIG_USB_SN9C102=m -CONFIG_USB_STV680=m -CONFIG_USB_ZC0301=m -CONFIG_USB_PWC=m -# CONFIG_USB_PWC_DEBUG is not set -# CONFIG_USB_ZR364XX is not set -CONFIG_USB_STKWEBCAM=m -CONFIG_USB_S2255=m -CONFIG_RADIO_ADAPTERS=y -# CONFIG_RADIO_CADET is not set -# CONFIG_RADIO_RTRACK is not set -# CONFIG_RADIO_RTRACK2 is not set -# CONFIG_RADIO_AZTECH is not set -# CONFIG_RADIO_GEMTEK is not set -# CONFIG_RADIO_GEMTEK_PCI is not set -# CONFIG_RADIO_MAXIRADIO is not set -# CONFIG_RADIO_MAESTRO is not set -# CONFIG_RADIO_SF16FMI is not set -# CONFIG_RADIO_SF16FMR2 is not set -# CONFIG_RADIO_TERRATEC is not set -# CONFIG_RADIO_TRUST is not set -# CONFIG_RADIO_TYPHOON is not set -# CONFIG_RADIO_ZOLTRIX is not set -# CONFIG_USB_DSBR is not set -CONFIG_USB_SI470X=m -CONFIG_USB_MR800=m -CONFIG_DAB=y -# CONFIG_USB_DABUSB is not set - -# -# Graphics support -# -# CONFIG_DRM is not set -# CONFIG_VGASTATE is not set -CONFIG_VIDEO_OUTPUT_CONTROL=m -CONFIG_FB=y -# CONFIG_FIRMWARE_EDID is not set -# CONFIG_FB_DDC is not set -# CONFIG_FB_BOOT_VESA_SUPPORT is not set -CONFIG_FB_CFB_FILLRECT=y -CONFIG_FB_CFB_COPYAREA=y -CONFIG_FB_CFB_IMAGEBLIT=y -# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set -# CONFIG_FB_SYS_FILLRECT is not set -# CONFIG_FB_SYS_COPYAREA is not set -# CONFIG_FB_SYS_IMAGEBLIT is not set -# CONFIG_FB_FOREIGN_ENDIAN is not set -# CONFIG_FB_SYS_FOPS is not set -# CONFIG_FB_SVGALIB is not set -# CONFIG_FB_MACMODES is not set -CONFIG_FB_BACKLIGHT=y -CONFIG_FB_MODE_HELPERS=y -# CONFIG_FB_TILEBLITTING is not set - -# -# Frame buffer hardware drivers -# -# CONFIG_FB_CIRRUS is not set -# CONFIG_FB_PM2 is not set -# CONFIG_FB_CYBER2000 is not set -# CONFIG_FB_ASILIANT is not set -# CONFIG_FB_IMSTT is not set -# CONFIG_FB_S1D13XXX is not set -# CONFIG_FB_NVIDIA is not set -# CONFIG_FB_RIVA is not set -# CONFIG_FB_MATROX is not set -CONFIG_FB_RADEON=y -# CONFIG_FB_RADEON_I2C is not set -CONFIG_FB_RADEON_BACKLIGHT=y -# CONFIG_FB_RADEON_DEBUG is not set -# CONFIG_FB_ATY128 is not set -# CONFIG_FB_ATY is not set -# CONFIG_FB_S3 is not set -# CONFIG_FB_SAVAGE is not set -# CONFIG_FB_SIS is not set -# CONFIG_FB_VIA is not set -# CONFIG_FB_NEOMAGIC is not set -# CONFIG_FB_KYRO is not set -# CONFIG_FB_3DFX is not set -# CONFIG_FB_VOODOO1 is not set -# CONFIG_FB_VT8623 is not set -# CONFIG_FB_TRIDENT is not set -# CONFIG_FB_ARK is not set -# CONFIG_FB_PM3 is not set -# CONFIG_FB_CARMINE is not set -# CONFIG_FB_VIRTUAL is not set -# CONFIG_FB_METRONOME is not set -# CONFIG_FB_MB862XX is not set -CONFIG_BACKLIGHT_LCD_SUPPORT=y -CONFIG_LCD_CLASS_DEVICE=m -# CONFIG_LCD_ILI9320 is not set -# CONFIG_LCD_PLATFORM is not set -CONFIG_BACKLIGHT_CLASS_DEVICE=y -# CONFIG_BACKLIGHT_CORGI is not set - -# -# Display device support -# -# CONFIG_DISPLAY_SUPPORT is not set - -# -# Console display driver support -# -# CONFIG_VGA_CONSOLE is not set -# CONFIG_MDA_CONSOLE is not set -CONFIG_DUMMY_CONSOLE=y -CONFIG_FRAMEBUFFER_CONSOLE=y -# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set -# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set -# CONFIG_FONTS is not set -CONFIG_FONT_8x8=y -CONFIG_FONT_8x16=y -# CONFIG_LOGO is not set -CONFIG_SOUND=y -CONFIG_SOUND_OSS_CORE=y -CONFIG_SND=m -CONFIG_SND_TIMER=m -CONFIG_SND_PCM=m -CONFIG_SND_RAWMIDI=m -CONFIG_SND_SEQUENCER=m -CONFIG_SND_SEQ_DUMMY=m -CONFIG_SND_OSSEMUL=y -CONFIG_SND_MIXER_OSS=m -CONFIG_SND_PCM_OSS=m -CONFIG_SND_PCM_OSS_PLUGINS=y -CONFIG_SND_SEQUENCER_OSS=y -# CONFIG_SND_DYNAMIC_MINORS is not set -CONFIG_SND_SUPPORT_OLD_API=y -CONFIG_SND_VERBOSE_PROCFS=y -# CONFIG_SND_VERBOSE_PRINTK is not set -# CONFIG_SND_DEBUG is not set -CONFIG_SND_VMASTER=y -CONFIG_SND_MPU401_UART=m -CONFIG_SND_AC97_CODEC=m -CONFIG_SND_DRIVERS=y -# CONFIG_SND_DUMMY is not set -# CONFIG_SND_VIRMIDI is not set -# CONFIG_SND_MTPAV is not set -# CONFIG_SND_SERIAL_U16550 is not set -# CONFIG_SND_MPU401 is not set -# CONFIG_SND_AC97_POWER_SAVE is not set -CONFIG_SND_PCI=y -# CONFIG_SND_AD1889 is not set -# CONFIG_SND_ALS300 is not set -# CONFIG_SND_ALI5451 is not set -# CONFIG_SND_ATIIXP is not set -# CONFIG_SND_ATIIXP_MODEM is not set -# CONFIG_SND_AU8810 is not set -# CONFIG_SND_AU8820 is not set -# CONFIG_SND_AU8830 is not set -# CONFIG_SND_AW2 is not set -# CONFIG_SND_AZT3328 is not set -# CONFIG_SND_BT87X is not set -# CONFIG_SND_CA0106 is not set -# CONFIG_SND_CMIPCI is not set -# CONFIG_SND_OXYGEN is not set -# CONFIG_SND_CS4281 is not set -# CONFIG_SND_CS46XX is not set -# CONFIG_SND_DARLA20 is not set -# CONFIG_SND_GINA20 is not set -# CONFIG_SND_LAYLA20 is not set -# CONFIG_SND_DARLA24 is not set -# CONFIG_SND_GINA24 is not set -# CONFIG_SND_LAYLA24 is not set -# CONFIG_SND_MONA is not set -# CONFIG_SND_MIA is not set -# CONFIG_SND_ECHO3G is not set -# CONFIG_SND_INDIGO is not set -# CONFIG_SND_INDIGOIO is not set -# CONFIG_SND_INDIGODJ is not set -# CONFIG_SND_EMU10K1 is not set -# CONFIG_SND_EMU10K1X is not set -# CONFIG_SND_ENS1370 is not set -# CONFIG_SND_ENS1371 is not set -# CONFIG_SND_ES1938 is not set -# CONFIG_SND_ES1968 is not set -# CONFIG_SND_FM801 is not set -# CONFIG_SND_HDA_INTEL is not set -# CONFIG_SND_HDSP is not set -# CONFIG_SND_HDSPM is not set -# CONFIG_SND_HIFIER is not set -# CONFIG_SND_ICE1712 is not set -# CONFIG_SND_ICE1724 is not set -# CONFIG_SND_INTEL8X0 is not set -# CONFIG_SND_INTEL8X0M is not set -# CONFIG_SND_KORG1212 is not set -# CONFIG_SND_MAESTRO3 is not set -# CONFIG_SND_MIXART is not set -# CONFIG_SND_NM256 is not set -# CONFIG_SND_PCXHR is not set -# CONFIG_SND_RIPTIDE is not set -# CONFIG_SND_RME32 is not set -# CONFIG_SND_RME96 is not set -# CONFIG_SND_RME9652 is not set -# CONFIG_SND_SONICVIBES is not set -# CONFIG_SND_TRIDENT is not set -CONFIG_SND_VIA82XX=m -# CONFIG_SND_VIA82XX_MODEM is not set -# CONFIG_SND_VIRTUOSO is not set -# CONFIG_SND_VX222 is not set -# CONFIG_SND_YMFPCI is not set -CONFIG_SND_MIPS=y -CONFIG_SND_USB=y -# CONFIG_SND_USB_AUDIO is not set -# CONFIG_SND_USB_CAIAQ is not set -# CONFIG_SND_SOC is not set -# CONFIG_SOUND_PRIME is not set -CONFIG_AC97_BUS=m -CONFIG_HID_SUPPORT=y -CONFIG_HID=y -# CONFIG_HID_DEBUG is not set -CONFIG_HIDRAW=y - -# -# USB Input Devices -# -CONFIG_USB_HID=m -CONFIG_HID_PID=y -CONFIG_USB_HIDDEV=y - -# -# USB HID Boot Protocol drivers -# -# CONFIG_USB_KBD is not set -# CONFIG_USB_MOUSE is not set - -# -# Special HID drivers -# -CONFIG_HID_COMPAT=y -CONFIG_HID_A4TECH=m -CONFIG_HID_APPLE=m -CONFIG_HID_BELKIN=m -CONFIG_HID_BRIGHT=m -CONFIG_HID_CHERRY=m -CONFIG_HID_CHICONY=m -CONFIG_HID_CYPRESS=m -CONFIG_HID_DELL=m -CONFIG_HID_EZKEY=m -CONFIG_HID_GYRATION=m -CONFIG_HID_LOGITECH=m -CONFIG_LOGITECH_FF=y -CONFIG_LOGIRUMBLEPAD2_FF=y -CONFIG_HID_MICROSOFT=m -CONFIG_HID_MONTEREY=m -CONFIG_HID_PANTHERLORD=m -# CONFIG_PANTHERLORD_FF is not set -CONFIG_HID_PETALYNX=m -CONFIG_HID_SAMSUNG=m -CONFIG_HID_SONY=m -CONFIG_HID_SUNPLUS=m -# CONFIG_THRUSTMASTER_FF is not set -CONFIG_ZEROPLUS_FF=m -CONFIG_USB_SUPPORT=y -CONFIG_USB_ARCH_HAS_HCD=y -CONFIG_USB_ARCH_HAS_OHCI=y -CONFIG_USB_ARCH_HAS_EHCI=y -CONFIG_USB=y -# CONFIG_USB_DEBUG is not set -CONFIG_USB_ANNOUNCE_NEW_DEVICES=y - -# -# Miscellaneous USB options -# -CONFIG_USB_DEVICEFS=y -# CONFIG_USB_DEVICE_CLASS is not set -# CONFIG_USB_DYNAMIC_MINORS is not set -# CONFIG_USB_SUSPEND is not set -# CONFIG_USB_OTG is not set -CONFIG_USB_OTG_WHITELIST=y -# CONFIG_USB_OTG_BLACKLIST_HUB is not set -# CONFIG_USB_MON is not set -# CONFIG_USB_WUSB is not set -CONFIG_USB_WUSB_CBAF=m -# CONFIG_USB_WUSB_CBAF_DEBUG is not set - -# -# USB Host Controller Drivers -# -CONFIG_USB_C67X00_HCD=m -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_EHCI_ROOT_HUB_TT=y -CONFIG_USB_EHCI_TT_NEWSCHED=y -# CONFIG_USB_ISP116X_HCD is not set -CONFIG_USB_ISP1760_HCD=m -CONFIG_USB_OHCI_HCD=y -# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set -# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set -CONFIG_USB_OHCI_LITTLE_ENDIAN=y -CONFIG_USB_UHCI_HCD=m -# CONFIG_USB_SL811_HCD is not set -CONFIG_USB_R8A66597_HCD=m -# CONFIG_USB_WHCI_HCD is not set -# CONFIG_USB_HWA_HCD is not set - -# -# USB Device Class drivers -# -CONFIG_USB_ACM=y -CONFIG_USB_PRINTER=y -CONFIG_USB_WDM=m -CONFIG_USB_TMC=m - -# -# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed; -# - -# -# see USB_STORAGE Help for more information -# -CONFIG_USB_STORAGE=y -# CONFIG_USB_STORAGE_DEBUG is not set -# CONFIG_USB_STORAGE_DATAFAB is not set -# CONFIG_USB_STORAGE_FREECOM is not set -# CONFIG_USB_STORAGE_ISD200 is not set -# CONFIG_USB_STORAGE_DPCM is not set -# CONFIG_USB_STORAGE_USBAT is not set -# CONFIG_USB_STORAGE_SDDR09 is not set -# CONFIG_USB_STORAGE_SDDR55 is not set -# CONFIG_USB_STORAGE_JUMPSHOT is not set -# CONFIG_USB_STORAGE_ALAUDA is not set -CONFIG_USB_STORAGE_ONETOUCH=y -# CONFIG_USB_STORAGE_KARMA is not set -CONFIG_USB_STORAGE_CYPRESS_ATACB=y -CONFIG_USB_LIBUSUAL=y - -# -# USB Imaging devices -# -# CONFIG_USB_MDC800 is not set -# CONFIG_USB_MICROTEK is not set - -# -# USB port drivers -# -# CONFIG_USB_SERIAL is not set - -# -# USB Miscellaneous drivers -# -# CONFIG_USB_EMI62 is not set -# CONFIG_USB_EMI26 is not set -# CONFIG_USB_ADUTUX is not set -CONFIG_USB_SEVSEG=m -# CONFIG_USB_RIO500 is not set -# CONFIG_USB_LEGOTOWER is not set -# CONFIG_USB_LCD is not set -# CONFIG_USB_BERRY_CHARGE is not set -# CONFIG_USB_LED is not set -# CONFIG_USB_CYPRESS_CY7C63 is not set -# CONFIG_USB_CYTHERM is not set -# CONFIG_USB_PHIDGET is not set -# CONFIG_USB_IDMOUSE is not set -# CONFIG_USB_FTDI_ELAN is not set -# CONFIG_USB_APPLEDISPLAY is not set -# CONFIG_USB_SISUSBVGA is not set -# CONFIG_USB_LD is not set -# CONFIG_USB_TRANCEVIBRATOR is not set -# CONFIG_USB_IOWARRIOR is not set -# CONFIG_USB_TEST is not set -CONFIG_USB_ISIGHTFW=m -CONFIG_USB_VST=m -# CONFIG_USB_GADGET is not set -# CONFIG_UWB is not set -# CONFIG_MMC is not set -# CONFIG_MEMSTICK is not set -# CONFIG_NEW_LEDS is not set -# CONFIG_ACCESSIBILITY is not set -# CONFIG_INFINIBAND is not set -CONFIG_RTC_LIB=y -CONFIG_RTC_CLASS=m - -# -# RTC interfaces -# -CONFIG_RTC_INTF_SYSFS=y -CONFIG_RTC_INTF_PROC=y -CONFIG_RTC_INTF_DEV=y -CONFIG_RTC_INTF_DEV_UIE_EMUL=y -# CONFIG_RTC_DRV_TEST is not set - -# -# I2C RTC drivers -# -# CONFIG_RTC_DRV_DS1307 is not set -# CONFIG_RTC_DRV_DS1374 is not set -# CONFIG_RTC_DRV_DS1672 is not set -# CONFIG_RTC_DRV_MAX6900 is not set -# CONFIG_RTC_DRV_RS5C372 is not set -# CONFIG_RTC_DRV_ISL1208 is not set -# CONFIG_RTC_DRV_X1205 is not set -# CONFIG_RTC_DRV_PCF8563 is not set -# CONFIG_RTC_DRV_PCF8583 is not set -# CONFIG_RTC_DRV_M41T80 is not set -# CONFIG_RTC_DRV_S35390A is not set -# CONFIG_RTC_DRV_FM3130 is not set -# CONFIG_RTC_DRV_RX8581 is not set - -# -# SPI RTC drivers -# - -# -# Platform RTC drivers -# -CONFIG_RTC_DRV_CMOS=m -# CONFIG_RTC_DRV_DS1286 is not set -# CONFIG_RTC_DRV_DS1511 is not set -# CONFIG_RTC_DRV_DS1553 is not set -# CONFIG_RTC_DRV_DS1742 is not set -# CONFIG_RTC_DRV_STK17TA8 is not set -# CONFIG_RTC_DRV_M48T86 is not set -# CONFIG_RTC_DRV_M48T35 is not set -# CONFIG_RTC_DRV_M48T59 is not set -# CONFIG_RTC_DRV_BQ4802 is not set -# CONFIG_RTC_DRV_V3020 is not set - -# -# on-CPU RTC drivers -# -# CONFIG_DMADEVICES is not set -CONFIG_UIO=m -CONFIG_UIO_CIF=m -# CONFIG_UIO_PDRV is not set -# CONFIG_UIO_PDRV_GENIRQ is not set -# CONFIG_UIO_SMX is not set -# CONFIG_UIO_SERCOS3 is not set -# CONFIG_STAGING is not set -CONFIG_STAGING_EXCLUDE_BUILD=y - -# -# File systems -# -CONFIG_EXT2_FS=y -# CONFIG_EXT2_FS_XATTR is not set -CONFIG_EXT2_FS_XIP=y -CONFIG_EXT3_FS=y -# CONFIG_EXT3_FS_XATTR is not set -CONFIG_EXT4_FS=m -CONFIG_EXT4DEV_COMPAT=y -CONFIG_EXT4_FS_XATTR=y -CONFIG_EXT4_FS_POSIX_ACL=y -CONFIG_EXT4_FS_SECURITY=y -CONFIG_FS_XIP=y -CONFIG_JBD=y -CONFIG_JBD2=m -CONFIG_FS_MBCACHE=m -CONFIG_REISERFS_FS=m -# CONFIG_REISERFS_CHECK is not set -# CONFIG_REISERFS_PROC_INFO is not set -# CONFIG_REISERFS_FS_XATTR is not set -# CONFIG_JFS_FS is not set -CONFIG_FS_POSIX_ACL=y -CONFIG_FILE_LOCKING=y -# CONFIG_XFS_FS is not set -# CONFIG_GFS2_FS is not set -# CONFIG_OCFS2_FS is not set -CONFIG_DNOTIFY=y -CONFIG_INOTIFY=y -CONFIG_INOTIFY_USER=y -# CONFIG_QUOTA is not set -CONFIG_AUTOFS_FS=y -CONFIG_AUTOFS4_FS=y -CONFIG_FUSE_FS=y - -# -# CD-ROM/DVD Filesystems -# -CONFIG_ISO9660_FS=m -CONFIG_JOLIET=y -CONFIG_ZISOFS=y -CONFIG_UDF_FS=m -CONFIG_UDF_NLS=y - -# -# DOS/FAT/NT Filesystems -# -CONFIG_FAT_FS=m -CONFIG_MSDOS_FS=m -CONFIG_VFAT_FS=m -CONFIG_FAT_DEFAULT_CODEPAGE=936 -CONFIG_FAT_DEFAULT_IOCHARSET="utf8" -CONFIG_NTFS_FS=m -# CONFIG_NTFS_DEBUG is not set -CONFIG_NTFS_RW=y - -# -# Pseudo filesystems -# -CONFIG_PROC_FS=y -CONFIG_PROC_KCORE=y -CONFIG_PROC_SYSCTL=y -CONFIG_PROC_PAGE_MONITOR=y -CONFIG_SYSFS=y -CONFIG_TMPFS=y -# CONFIG_TMPFS_POSIX_ACL is not set -# CONFIG_HUGETLB_PAGE is not set -# CONFIG_CONFIGFS_FS is not set - -# -# Miscellaneous filesystems -# -# CONFIG_ADFS_FS is not set -# CONFIG_AFFS_FS is not set -# CONFIG_HFS_FS is not set -# CONFIG_HFSPLUS_FS is not set -# CONFIG_BEFS_FS is not set -# CONFIG_BFS_FS is not set -# CONFIG_EFS_FS is not set -# CONFIG_JFFS2_FS is not set -# CONFIG_CRAMFS is not set -# CONFIG_VXFS_FS is not set -# CONFIG_MINIX_FS is not set -CONFIG_OMFS_FS=m -# CONFIG_HPFS_FS is not set -# CONFIG_QNX4FS_FS is not set -# CONFIG_ROMFS_FS is not set -# CONFIG_SYSV_FS is not set -# CONFIG_UFS_FS is not set -CONFIG_NETWORK_FILESYSTEMS=y -CONFIG_NFS_FS=m -CONFIG_NFS_V3=y -CONFIG_NFS_V3_ACL=y -CONFIG_NFS_V4=y -CONFIG_NFSD=m -CONFIG_NFSD_V2_ACL=y -CONFIG_NFSD_V3=y -CONFIG_NFSD_V3_ACL=y -CONFIG_NFSD_V4=y -CONFIG_LOCKD=m -CONFIG_LOCKD_V4=y -CONFIG_EXPORTFS=m -CONFIG_NFS_ACL_SUPPORT=m -CONFIG_NFS_COMMON=y -CONFIG_SUNRPC=m -CONFIG_SUNRPC_GSS=m -# CONFIG_SUNRPC_REGISTER_V4 is not set -CONFIG_RPCSEC_GSS_KRB5=m -# CONFIG_RPCSEC_GSS_SPKM3 is not set -CONFIG_SMB_FS=m -CONFIG_SMB_NLS_DEFAULT=y -CONFIG_SMB_NLS_REMOTE="cp936" -CONFIG_CIFS=m -CONFIG_CIFS_STATS=y -CONFIG_CIFS_STATS2=y -CONFIG_CIFS_WEAK_PW_HASH=y -CONFIG_CIFS_XATTR=y -CONFIG_CIFS_POSIX=y -CONFIG_CIFS_DEBUG2=y -CONFIG_CIFS_EXPERIMENTAL=y -# CONFIG_NCP_FS is not set -# CONFIG_CODA_FS is not set -# CONFIG_AFS_FS is not set -# CONFIG_9P_FS is not set - -# -# Partition Types -# -CONFIG_PARTITION_ADVANCED=y -# CONFIG_ACORN_PARTITION is not set -# CONFIG_OSF_PARTITION is not set -# CONFIG_AMIGA_PARTITION is not set -# CONFIG_ATARI_PARTITION is not set -# CONFIG_MAC_PARTITION is not set -CONFIG_MSDOS_PARTITION=y -# CONFIG_BSD_DISKLABEL is not set -# CONFIG_MINIX_SUBPARTITION is not set -# CONFIG_SOLARIS_X86_PARTITION is not set -# CONFIG_UNIXWARE_DISKLABEL is not set -# CONFIG_LDM_PARTITION is not set -# CONFIG_SGI_PARTITION is not set -# CONFIG_ULTRIX_PARTITION is not set -# CONFIG_SUN_PARTITION is not set -# CONFIG_KARMA_PARTITION is not set -# CONFIG_EFI_PARTITION is not set -# CONFIG_SYSV68_PARTITION is not set -CONFIG_NLS=y -CONFIG_NLS_DEFAULT="utf8" -# CONFIG_NLS_CODEPAGE_437 is not set -# CONFIG_NLS_CODEPAGE_737 is not set -# CONFIG_NLS_CODEPAGE_775 is not set -# CONFIG_NLS_CODEPAGE_850 is not set -# CONFIG_NLS_CODEPAGE_852 is not set -# CONFIG_NLS_CODEPAGE_855 is not set -# CONFIG_NLS_CODEPAGE_857 is not set -# CONFIG_NLS_CODEPAGE_860 is not set -# CONFIG_NLS_CODEPAGE_861 is not set -# CONFIG_NLS_CODEPAGE_862 is not set -# CONFIG_NLS_CODEPAGE_863 is not set -# CONFIG_NLS_CODEPAGE_864 is not set -# CONFIG_NLS_CODEPAGE_865 is not set -# CONFIG_NLS_CODEPAGE_866 is not set -# CONFIG_NLS_CODEPAGE_869 is not set -CONFIG_NLS_CODEPAGE_936=y -# CONFIG_NLS_CODEPAGE_950 is not set -# CONFIG_NLS_CODEPAGE_932 is not set -# CONFIG_NLS_CODEPAGE_949 is not set -# CONFIG_NLS_CODEPAGE_874 is not set -# CONFIG_NLS_ISO8859_8 is not set -# CONFIG_NLS_CODEPAGE_1250 is not set -# CONFIG_NLS_CODEPAGE_1251 is not set -# CONFIG_NLS_ASCII is not set -CONFIG_NLS_ISO8859_1=y -# CONFIG_NLS_ISO8859_2 is not set -# CONFIG_NLS_ISO8859_3 is not set -# CONFIG_NLS_ISO8859_4 is not set -# CONFIG_NLS_ISO8859_5 is not set -# CONFIG_NLS_ISO8859_6 is not set -# CONFIG_NLS_ISO8859_7 is not set -# CONFIG_NLS_ISO8859_9 is not set -# CONFIG_NLS_ISO8859_13 is not set -# CONFIG_NLS_ISO8859_14 is not set -# CONFIG_NLS_ISO8859_15 is not set -# CONFIG_NLS_KOI8_R is not set -# CONFIG_NLS_KOI8_U is not set -CONFIG_NLS_UTF8=y -# CONFIG_DLM is not set - -# -# Kernel hacking -# -CONFIG_TRACE_IRQFLAGS_SUPPORT=y -# CONFIG_PRINTK_TIME is not set -CONFIG_ENABLE_WARN_DEPRECATED=y -# CONFIG_ENABLE_MUST_CHECK is not set -CONFIG_FRAME_WARN=2048 -# CONFIG_MAGIC_SYSRQ is not set -# CONFIG_UNUSED_SYMBOLS is not set -# CONFIG_DEBUG_FS is not set -# CONFIG_HEADERS_CHECK is not set -# CONFIG_DEBUG_KERNEL is not set -# CONFIG_DEBUG_MEMORY_INIT is not set -# CONFIG_RCU_CPU_STALL_DETECTOR is not set -CONFIG_SYSCTL_SYSCALL_CHECK=y - -# -# Tracers -# -CONFIG_DYNAMIC_PRINTK_DEBUG=y -# CONFIG_SAMPLES is not set -CONFIG_HAVE_ARCH_KGDB=y -CONFIG_CMDLINE="" - -# -# Security options -# -# CONFIG_KEYS is not set -# CONFIG_SECURITY is not set -# CONFIG_SECURITYFS is not set -CONFIG_SECURITY_FILE_CAPABILITIES=y -CONFIG_CRYPTO=y - -# -# Crypto core or helper -# -CONFIG_CRYPTO_FIPS=y -CONFIG_CRYPTO_ALGAPI=y -CONFIG_CRYPTO_AEAD=y -CONFIG_CRYPTO_BLKCIPHER=y -CONFIG_CRYPTO_HASH=y -CONFIG_CRYPTO_RNG=y -CONFIG_CRYPTO_MANAGER=y -CONFIG_CRYPTO_GF128MUL=m -# CONFIG_CRYPTO_NULL is not set -# CONFIG_CRYPTO_CRYPTD is not set -CONFIG_CRYPTO_AUTHENC=m -# CONFIG_CRYPTO_TEST is not set - -# -# Authenticated Encryption with Associated Data -# -CONFIG_CRYPTO_CCM=m -CONFIG_CRYPTO_GCM=m -CONFIG_CRYPTO_SEQIV=m - -# -# Block modes -# -CONFIG_CRYPTO_CBC=m -CONFIG_CRYPTO_CTR=m -CONFIG_CRYPTO_CTS=m -CONFIG_CRYPTO_ECB=m -# CONFIG_CRYPTO_LRW is not set -CONFIG_CRYPTO_PCBC=m -CONFIG_CRYPTO_XTS=m - -# -# Hash modes -# -CONFIG_CRYPTO_HMAC=y -# CONFIG_CRYPTO_XCBC is not set - -# -# Digest -# -# CONFIG_CRYPTO_CRC32C is not set -# CONFIG_CRYPTO_MD4 is not set -CONFIG_CRYPTO_MD5=m -# CONFIG_CRYPTO_MICHAEL_MIC is not set -CONFIG_CRYPTO_RMD128=m -CONFIG_CRYPTO_RMD160=m -CONFIG_CRYPTO_RMD256=m -CONFIG_CRYPTO_RMD320=m -CONFIG_CRYPTO_SHA1=m -# CONFIG_CRYPTO_SHA256 is not set -# CONFIG_CRYPTO_SHA512 is not set -# CONFIG_CRYPTO_TGR192 is not set -# CONFIG_CRYPTO_WP512 is not set - -# -# Ciphers -# -CONFIG_CRYPTO_AES=m -# CONFIG_CRYPTO_ANUBIS is not set -CONFIG_CRYPTO_ARC4=m -# CONFIG_CRYPTO_BLOWFISH is not set -# CONFIG_CRYPTO_CAMELLIA is not set -# CONFIG_CRYPTO_CAST5 is not set -# CONFIG_CRYPTO_CAST6 is not set -CONFIG_CRYPTO_DES=m -# CONFIG_CRYPTO_FCRYPT is not set -# CONFIG_CRYPTO_KHAZAD is not set -CONFIG_CRYPTO_SALSA20=m -CONFIG_CRYPTO_SEED=m -# CONFIG_CRYPTO_SERPENT is not set -# CONFIG_CRYPTO_TEA is not set -# CONFIG_CRYPTO_TWOFISH is not set - -# -# Compression -# -CONFIG_CRYPTO_DEFLATE=m -CONFIG_CRYPTO_LZO=m - -# -# Random Number Generation -# -CONFIG_CRYPTO_ANSI_CPRNG=m -# CONFIG_CRYPTO_HW is not set - -# -# Library routines -# -CONFIG_BITREVERSE=y -CONFIG_CRC_CCITT=y -CONFIG_CRC16=m -# CONFIG_CRC_T10DIF is not set -CONFIG_CRC_ITU_T=m -CONFIG_CRC32=y -CONFIG_CRC7=m -# CONFIG_LIBCRC32C is not set -CONFIG_ZLIB_INFLATE=m -CONFIG_ZLIB_DEFLATE=m -CONFIG_LZO_COMPRESS=m -CONFIG_LZO_DECOMPRESS=m -CONFIG_TEXTSEARCH=y -CONFIG_TEXTSEARCH_KMP=m -CONFIG_TEXTSEARCH_BM=m -CONFIG_TEXTSEARCH_FSM=m -CONFIG_PLIST=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT=y -CONFIG_HAS_DMA=y diff --git a/arch/mips/configs/fuloong2e_defconfig b/arch/mips/configs/fuloong2e_defconfig new file mode 100644 index 0000000..0197f0d --- /dev/null +++ b/arch/mips/configs/fuloong2e_defconfig @@ -0,0 +1,1819 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.31-rc1 +# Thu Jul 2 22:37:00 2009 +# +CONFIG_MIPS=y + +# +# Machine selection +# +# CONFIG_MACH_ALCHEMY is not set +# CONFIG_AR7 is not set +# CONFIG_BASLER_EXCITE is not set +# CONFIG_BCM47XX is not set +# CONFIG_MIPS_COBALT is not set +# CONFIG_MACH_DECSTATION is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_LASAT is not set +CONFIG_MACH_LOONGSON=y +# CONFIG_MIPS_MALTA is not set +# CONFIG_MIPS_SIM is not set +# CONFIG_NEC_MARKEINS is not set +# CONFIG_MACH_VR41XX is not set +# CONFIG_NXP_STB220 is not set +# CONFIG_NXP_STB225 is not set +# CONFIG_PNX8550_JBS is not set +# CONFIG_PNX8550_STB810 is not set +# CONFIG_PMC_MSP is not set +# CONFIG_PMC_YOSEMITE is not set +# CONFIG_SGI_IP22 is not set +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP28 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_CRHONE is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_BIGSUR is not set +# CONFIG_SNI_RM is not set +# CONFIG_MACH_TX39XX is not set +# CONFIG_MACH_TX49XX is not set +# CONFIG_MIKROTIK_RB532 is not set +# CONFIG_WR_PPMC is not set +# CONFIG_CAVIUM_OCTEON_SIMULATOR is not set +# CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD is not set +# CONFIG_ALCHEMY_GPIO_INDIRECT is not set +CONFIG_ARCH_SPARSEMEM_ENABLE=y +CONFIG_LEMOTE_FULOONG2E=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_ARCH_SUPPORTS_OPROFILE=y +CONFIG_GENERIC_FIND_NEXT_BIT=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CMOS_UPDATE=y +CONFIG_SCHED_OMIT_FRAME_POINTER=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +CONFIG_CEVT_R4K_LIB=y +CONFIG_CEVT_R4K=y +CONFIG_CSRC_R4K_LIB=y +CONFIG_CSRC_R4K=y +CONFIG_DMA_NONCOHERENT=y +CONFIG_DMA_NEED_PCI_MAP_STATE=y +CONFIG_EARLY_PRINTK=y +CONFIG_SYS_HAS_EARLY_PRINTK=y +CONFIG_I8259=y +# CONFIG_NO_IOPORT is not set +CONFIG_GENERIC_ISA_DMA=y +CONFIG_GENERIC_ISA_DMA_SUPPORT_BROKEN=y +# CONFIG_CPU_BIG_ENDIAN is not set +CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y +CONFIG_IRQ_CPU=y +CONFIG_BOOT_ELF32=y +CONFIG_MIPS_L1_CACHE_SHIFT=5 + +# +# CPU selection +# +CONFIG_CPU_LOONGSON2E=y +# CONFIG_CPU_MIPS32_R1 is not set +# CONFIG_CPU_MIPS32_R2 is not set +# CONFIG_CPU_MIPS64_R1 is not set +# CONFIG_CPU_MIPS64_R2 is not set +# CONFIG_CPU_R3000 is not set +# CONFIG_CPU_TX39XX is not set +# CONFIG_CPU_VR41XX is not set +# CONFIG_CPU_R4300 is not set +# CONFIG_CPU_R4X00 is not set +# CONFIG_CPU_TX49XX is not set +# CONFIG_CPU_R5000 is not set +# CONFIG_CPU_R5432 is not set +# CONFIG_CPU_R5500 is not set +# CONFIG_CPU_R6000 is not set +# CONFIG_CPU_NEVADA is not set +# CONFIG_CPU_R8000 is not set +# CONFIG_CPU_R10000 is not set +# CONFIG_CPU_RM7000 is not set +# CONFIG_CPU_RM9000 is not set +# CONFIG_CPU_SB1 is not set +# CONFIG_CPU_CAVIUM_OCTEON is not set +CONFIG_CPU_LOONGSON2=y +CONFIG_SYS_HAS_CPU_LOONGSON2E=y +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y + +# +# Kernel type +# +# CONFIG_32BIT is not set +CONFIG_64BIT=y +# CONFIG_PAGE_SIZE_4KB is not set +# CONFIG_PAGE_SIZE_8KB is not set +CONFIG_PAGE_SIZE_16KB=y +# CONFIG_PAGE_SIZE_32KB is not set +# CONFIG_PAGE_SIZE_64KB is not set +CONFIG_BOARD_SCACHE=y +CONFIG_MIPS_MT_DISABLED=y +# CONFIG_MIPS_MT_SMP is not set +# CONFIG_MIPS_MT_SMTC is not set +CONFIG_CPU_HAS_WB=y +CONFIG_CPU_HAS_SYNC=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_CPU_SUPPORTS_HIGHMEM=y +CONFIG_SYS_SUPPORTS_HIGHMEM=y +CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_ARCH_POPULATES_NODE_MAP=y +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_SPARSEMEM_STATIC=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +CONFIG_PHYS_ADDR_T_64BIT=y +CONFIG_ZONE_DMA_FLAG=0 +CONFIG_VIRT_TO_BUS=y +CONFIG_HAVE_MLOCK=y +CONFIG_HAVE_MLOCKED_PAGE_BIT=y +CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +# CONFIG_HZ_48 is not set +# CONFIG_HZ_100 is not set +# CONFIG_HZ_128 is not set +CONFIG_HZ_250=y +# CONFIG_HZ_256 is not set +# CONFIG_HZ_1000 is not set +# CONFIG_HZ_1024 is not set +CONFIG_SYS_SUPPORTS_ARBIT_HZ=y +CONFIG_HZ=250 +# CONFIG_PREEMPT_NONE is not set +CONFIG_PREEMPT_VOLUNTARY=y +# CONFIG_PREEMPT is not set +# CONFIG_KEXEC is not set +CONFIG_SECCOMP=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" +CONFIG_CONSTRUCTORS=y + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="-fuloong2e" +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_POSIX_MQUEUE=y +CONFIG_POSIX_MQUEUE_SYSCTL=y +CONFIG_BSD_PROCESS_ACCT=y +# CONFIG_BSD_PROCESS_ACCT_V3 is not set +# CONFIG_TASKSTATS is not set +# CONFIG_AUDIT is not set + +# +# RCU Subsystem +# +CONFIG_CLASSIC_RCU=y +# CONFIG_TREE_RCU is not set +# CONFIG_PREEMPT_RCU is not set +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_PREEMPT_RCU_TRACE is not set +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_GROUP_SCHED is not set +# CONFIG_CGROUPS is not set +CONFIG_SYSFS_DEPRECATED=y +CONFIG_SYSFS_DEPRECATED_V2=y +# CONFIG_RELAY is not set +CONFIG_NAMESPACES=y +# CONFIG_UTS_NS is not set +# CONFIG_IPC_NS is not set +CONFIG_USER_NS=y +CONFIG_PID_NS=y +# CONFIG_NET_NS is not set +# CONFIG_BLK_DEV_INITRD is not set +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +CONFIG_EMBEDDED=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +# CONFIG_PCSPKR_PLATFORM is not set +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y + +# +# Performance Counters +# +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_PCI_QUIRKS=y +# CONFIG_STRIP_ASM_SYMS is not set +# CONFIG_COMPAT_BRK is not set +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +CONFIG_PROFILING=y +CONFIG_TRACEPOINTS=y +CONFIG_MARKERS=y +CONFIG_OPROFILE=m +CONFIG_HAVE_OPROFILE=y +CONFIG_HAVE_SYSCALL_WRAPPERS=y + +# +# GCOV-based kernel profiling +# +# CONFIG_GCOV_KERNEL is not set +# CONFIG_SLOW_WORK is not set +# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_BLOCK=y +CONFIG_BLK_DEV_BSG=y +# CONFIG_BLK_DEV_INTEGRITY is not set +CONFIG_BLOCK_COMPAT=y + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +# CONFIG_DEFAULT_AS is not set +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" +# CONFIG_FREEZER is not set + +# +# Bus options (PCI, PCMCIA, EISA, ISA, TC) +# +CONFIG_HW_HAS_PCI=y +CONFIG_PCI=y +CONFIG_PCI_DOMAINS=y +# CONFIG_ARCH_SUPPORTS_MSI is not set +CONFIG_PCI_LEGACY=y +# CONFIG_PCI_STUB is not set +# CONFIG_PCI_IOV is not set +CONFIG_ISA=y +CONFIG_MMU=y +# CONFIG_PCCARD is not set +# CONFIG_HOTPLUG_PCI is not set + +# +# Executable file formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set +CONFIG_BINFMT_MISC=y +CONFIG_MIPS32_COMPAT=y +CONFIG_COMPAT=y +CONFIG_SYSVIPC_COMPAT=y +CONFIG_MIPS32_O32=y +CONFIG_MIPS32_N32=y +CONFIG_BINFMT_ELF32=y + +# +# Power management options +# +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_PM=y +# CONFIG_PM_DEBUG is not set +# CONFIG_SUSPEND is not set +# CONFIG_HIBERNATION is not set +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_PACKET_MMAP=y +CONFIG_UNIX=y +CONFIG_XFRM=y +# CONFIG_XFRM_USER is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set +# CONFIG_NET_KEY is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +# CONFIG_IP_PNP_DHCP is not set +CONFIG_IP_PNP_BOOTP=y +# CONFIG_IP_PNP_RARP is not set +CONFIG_NET_IPIP=m +CONFIG_NET_IPGRE=m +CONFIG_NET_IPGRE_BROADCAST=y +# CONFIG_IP_MROUTE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +CONFIG_INET_TUNNEL=m +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +CONFIG_INET_XFRM_MODE_BEET=y +# CONFIG_INET_LRO is not set +# CONFIG_INET_DIAG is not set +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +# CONFIG_IPV6 is not set +# CONFIG_NETWORK_SECMARK is not set +CONFIG_NETFILTER=y +# CONFIG_NETFILTER_DEBUG is not set +CONFIG_NETFILTER_ADVANCED=y + +# +# Core Netfilter Configuration +# +CONFIG_NETFILTER_NETLINK=m +CONFIG_NETFILTER_NETLINK_QUEUE=m +CONFIG_NETFILTER_NETLINK_LOG=m +# CONFIG_NF_CONNTRACK is not set +# CONFIG_NETFILTER_TPROXY is not set +CONFIG_NETFILTER_XTABLES=m +CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m +# CONFIG_NETFILTER_XT_TARGET_DSCP is not set +CONFIG_NETFILTER_XT_TARGET_HL=m +CONFIG_NETFILTER_XT_TARGET_MARK=m +# CONFIG_NETFILTER_XT_TARGET_NFLOG is not set +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m +CONFIG_NETFILTER_XT_TARGET_RATEEST=m +CONFIG_NETFILTER_XT_TARGET_TRACE=m +# CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set +CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m +CONFIG_NETFILTER_XT_MATCH_COMMENT=m +CONFIG_NETFILTER_XT_MATCH_DCCP=m +# CONFIG_NETFILTER_XT_MATCH_DSCP is not set +CONFIG_NETFILTER_XT_MATCH_ESP=m +# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set +CONFIG_NETFILTER_XT_MATCH_HL=m +CONFIG_NETFILTER_XT_MATCH_IPRANGE=m +CONFIG_NETFILTER_XT_MATCH_LENGTH=m +CONFIG_NETFILTER_XT_MATCH_LIMIT=m +CONFIG_NETFILTER_XT_MATCH_MAC=m +CONFIG_NETFILTER_XT_MATCH_MARK=m +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m +CONFIG_NETFILTER_XT_MATCH_OWNER=m +# CONFIG_NETFILTER_XT_MATCH_POLICY is not set +CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m +CONFIG_NETFILTER_XT_MATCH_QUOTA=m +CONFIG_NETFILTER_XT_MATCH_RATEEST=m +CONFIG_NETFILTER_XT_MATCH_REALM=m +CONFIG_NETFILTER_XT_MATCH_RECENT=m +# CONFIG_NETFILTER_XT_MATCH_RECENT_PROC_COMPAT is not set +CONFIG_NETFILTER_XT_MATCH_SCTP=m +CONFIG_NETFILTER_XT_MATCH_STATISTIC=m +CONFIG_NETFILTER_XT_MATCH_STRING=m +CONFIG_NETFILTER_XT_MATCH_TCPMSS=m +CONFIG_NETFILTER_XT_MATCH_TIME=m +CONFIG_NETFILTER_XT_MATCH_U32=m +# CONFIG_NETFILTER_XT_MATCH_OSF is not set +# CONFIG_IP_VS is not set + +# +# IP: Netfilter Configuration +# +# CONFIG_NF_DEFRAG_IPV4 is not set +CONFIG_IP_NF_QUEUE=m +CONFIG_IP_NF_IPTABLES=m +CONFIG_IP_NF_MATCH_ADDRTYPE=m +CONFIG_IP_NF_MATCH_AH=m +CONFIG_IP_NF_MATCH_ECN=m +CONFIG_IP_NF_MATCH_TTL=m +CONFIG_IP_NF_FILTER=m +CONFIG_IP_NF_TARGET_REJECT=m +CONFIG_IP_NF_TARGET_LOG=m +CONFIG_IP_NF_TARGET_ULOG=m +CONFIG_IP_NF_MANGLE=m +CONFIG_IP_NF_TARGET_ECN=m +CONFIG_IP_NF_TARGET_TTL=m +CONFIG_IP_NF_RAW=m +CONFIG_IP_NF_ARPTABLES=m +CONFIG_IP_NF_ARPFILTER=m +CONFIG_IP_NF_ARP_MANGLE=m +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +CONFIG_PHONET=m +# CONFIG_IEEE802154 is not set +# CONFIG_NET_SCHED is not set +CONFIG_NET_CLS_ROUTE=y +# CONFIG_DCB is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_NET_DROP_MONITOR is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set +CONFIG_WIRELESS=y +# CONFIG_CFG80211 is not set +CONFIG_WIRELESS_OLD_REGULATORY=y +CONFIG_WIRELESS_EXT=y +CONFIG_WIRELESS_EXT_SYSFS=y +# CONFIG_LIB80211 is not set + +# +# CFG80211 needs to be enabled for MAC80211 +# +CONFIG_MAC80211_DEFAULT_PS_VALUE=0 +# CONFIG_WIMAX is not set +# CONFIG_RFKILL is not set +CONFIG_NET_9P=m +# CONFIG_NET_9P_DEBUG is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=m +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_CONNECTOR is not set +CONFIG_MTD=m +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_CONCAT is not set +# CONFIG_MTD_PARTITIONS is not set +# CONFIG_MTD_TESTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=m +CONFIG_MTD_BLKDEVS=m +CONFIG_MTD_BLOCK=m +# CONFIG_MTD_BLOCK_RO is not set +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_MTD_OOPS is not set + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=m +CONFIG_MTD_JEDECPROBE=m +CONFIG_MTD_GEN_PROBE=m +CONFIG_MTD_CFI_ADV_OPTIONS=y +CONFIG_MTD_CFI_NOSWAP=y +# CONFIG_MTD_CFI_BE_BYTE_SWAP is not set +# CONFIG_MTD_CFI_LE_BYTE_SWAP is not set +# CONFIG_MTD_CFI_GEOMETRY is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_OTP is not set +# CONFIG_MTD_CFI_INTELEXT is not set +CONFIG_MTD_CFI_AMDSTD=m +CONFIG_MTD_CFI_STAA=m +CONFIG_MTD_CFI_UTIL=m +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +CONFIG_MTD_PHYSMAP=m +# CONFIG_MTD_PHYSMAP_COMPAT is not set +# CONFIG_MTD_INTEL_VR_NOR is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_PMC551 is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +# CONFIG_MTD_NAND is not set +# CONFIG_MTD_ONENAND is not set + +# +# LPDDR flash memory drivers +# +# CONFIG_MTD_LPDDR is not set + +# +# UBI - Unsorted block images +# +# CONFIG_MTD_UBI is not set +# CONFIG_PARPORT is not set +# CONFIG_PNP is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_CPQ_DA is not set +# CONFIG_BLK_CPQ_CISS_DA is not set +# CONFIG_BLK_DEV_DAC960 is not set +# CONFIG_BLK_DEV_UMEM is not set +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_CRYPTOLOOP=m +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_SX8 is not set +# CONFIG_BLK_DEV_UB is not set +CONFIG_BLK_DEV_RAM=m +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=4096 +# CONFIG_BLK_DEV_XIP is not set +CONFIG_CDROM_PKTCDVD=m +CONFIG_CDROM_PKTCDVD_BUFFERS=8 +# CONFIG_CDROM_PKTCDVD_WCACHE is not set +CONFIG_ATA_OVER_ETH=m +# CONFIG_BLK_DEV_HD is not set +# CONFIG_MISC_DEVICES is not set +CONFIG_HAVE_IDE=y +CONFIG_IDE=y + +# +# Please see Documentation/ide/ide.txt for help/info on IDE drives +# +CONFIG_IDE_XFER_MODE=y +CONFIG_IDE_TIMINGS=y +CONFIG_IDE_ATAPI=y +# CONFIG_BLK_DEV_IDE_SATA is not set +CONFIG_IDE_GD=y +CONFIG_IDE_GD_ATA=y +# CONFIG_IDE_GD_ATAPI is not set +CONFIG_BLK_DEV_IDECD=y +CONFIG_BLK_DEV_IDECD_VERBOSE_ERRORS=y +# CONFIG_BLK_DEV_IDETAPE is not set +CONFIG_IDE_TASK_IOCTL=y +CONFIG_IDE_PROC_FS=y + +# +# IDE chipset support/bugfixes +# +CONFIG_IDE_GENERIC=y +# CONFIG_BLK_DEV_PLATFORM is not set +CONFIG_BLK_DEV_IDEDMA_SFF=y + +# +# PCI IDE chipsets support +# +CONFIG_BLK_DEV_IDEPCI=y +CONFIG_IDEPCI_PCIBUS_ORDER=y +# CONFIG_BLK_DEV_OFFBOARD is not set +CONFIG_BLK_DEV_GENERIC=y +# CONFIG_BLK_DEV_OPTI621 is not set +CONFIG_BLK_DEV_IDEDMA_PCI=y +# CONFIG_BLK_DEV_AEC62XX is not set +# CONFIG_BLK_DEV_ALI15X3 is not set +# CONFIG_BLK_DEV_AMD74XX is not set +# CONFIG_BLK_DEV_CMD64X is not set +# CONFIG_BLK_DEV_TRIFLEX is not set +# CONFIG_BLK_DEV_CS5520 is not set +# CONFIG_BLK_DEV_CS5530 is not set +# CONFIG_BLK_DEV_HPT366 is not set +# CONFIG_BLK_DEV_JMICRON is not set +# CONFIG_BLK_DEV_SC1200 is not set +# CONFIG_BLK_DEV_PIIX is not set +# CONFIG_BLK_DEV_IT8172 is not set +# CONFIG_BLK_DEV_IT8213 is not set +# CONFIG_BLK_DEV_IT821X is not set +# CONFIG_BLK_DEV_NS87415 is not set +# CONFIG_BLK_DEV_PDC202XX_OLD is not set +# CONFIG_BLK_DEV_PDC202XX_NEW is not set +# CONFIG_BLK_DEV_SVWKS is not set +# CONFIG_BLK_DEV_SIIMAGE is not set +# CONFIG_BLK_DEV_SLC90E66 is not set +# CONFIG_BLK_DEV_TRM290 is not set +CONFIG_BLK_DEV_VIA82CXXX=y +# CONFIG_BLK_DEV_TC86C001 is not set + +# +# Other IDE chipsets support +# + +# +# Note: most of these also require special kernel boot parameters +# +# CONFIG_BLK_DEV_4DRIVES is not set +# CONFIG_BLK_DEV_ALI14XX is not set +# CONFIG_BLK_DEV_DTC2278 is not set +# CONFIG_BLK_DEV_HT6560B is not set +# CONFIG_BLK_DEV_QD65XX is not set +# CONFIG_BLK_DEV_UMC8672 is not set +CONFIG_BLK_DEV_IDEDMA=y + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_NETLINK is not set +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +CONFIG_BLK_DEV_SR=y +CONFIG_BLK_DEV_SR_VENDOR=y +CONFIG_CHR_DEV_SG=y +# CONFIG_CHR_DEV_SCH is not set +# CONFIG_SCSI_MULTI_LUN is not set +CONFIG_SCSI_CONSTANTS=y +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set +CONFIG_SCSI_WAIT_SCAN=m + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +# CONFIG_SCSI_LOWLEVEL is not set +# CONFIG_SCSI_DH is not set +# CONFIG_SCSI_OSD_INITIATOR is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +# CONFIG_FUSION is not set + +# +# IEEE 1394 (FireWire) support +# + +# +# You can enable one or both FireWire driver stacks. +# + +# +# See the help texts for more information. +# +# CONFIG_FIREWIRE is not set +# CONFIG_IEEE1394 is not set +# CONFIG_I2O is not set +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +CONFIG_MACVLAN=m +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +CONFIG_VETH=m +# CONFIG_ARCNET is not set +CONFIG_PHYLIB=m + +# +# MII PHY device drivers +# +CONFIG_MARVELL_PHY=m +CONFIG_DAVICOM_PHY=m +CONFIG_QSEMI_PHY=m +CONFIG_LXT_PHY=m +CONFIG_CICADA_PHY=m +# CONFIG_VITESSE_PHY is not set +# CONFIG_SMSC_PHY is not set +# CONFIG_BROADCOM_PHY is not set +# CONFIG_ICPLUS_PHY is not set +# CONFIG_REALTEK_PHY is not set +# CONFIG_NATIONAL_PHY is not set +# CONFIG_STE10XP is not set +# CONFIG_LSI_ET1011C_PHY is not set +# CONFIG_MDIO_BITBANG is not set +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +# CONFIG_AX88796 is not set +# CONFIG_HAPPYMEAL is not set +# CONFIG_SUNGEM is not set +# CONFIG_CASSINI is not set +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_NET_VENDOR_SMC is not set +# CONFIG_SMC91X is not set +# CONFIG_DM9000 is not set +# CONFIG_ETHOC is not set +# CONFIG_NET_VENDOR_RACAL is not set +# CONFIG_DNET is not set +# CONFIG_NET_TULIP is not set +# CONFIG_AT1700 is not set +# CONFIG_DEPCA is not set +# CONFIG_HP100 is not set +# CONFIG_NET_ISA is not set +# CONFIG_IBM_NEW_EMAC_ZMII is not set +# CONFIG_IBM_NEW_EMAC_RGMII is not set +# CONFIG_IBM_NEW_EMAC_TAH is not set +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set +CONFIG_NET_PCI=y +# CONFIG_PCNET32 is not set +# CONFIG_AMD8111_ETH is not set +# CONFIG_ADAPTEC_STARFIRE is not set +# CONFIG_AC3200 is not set +# CONFIG_APRICOT is not set +# CONFIG_B44 is not set +# CONFIG_FORCEDETH is not set +# CONFIG_CS89x0 is not set +# CONFIG_TC35815 is not set +# CONFIG_E100 is not set +# CONFIG_FEALNX is not set +# CONFIG_NATSEMI is not set +# CONFIG_NE2K_PCI is not set +# CONFIG_8139CP is not set +CONFIG_8139TOO=y +# CONFIG_8139TOO_PIO is not set +# CONFIG_8139TOO_TUNE_TWISTER is not set +# CONFIG_8139TOO_8129 is not set +# CONFIG_8139_OLD_RX_RESET is not set +# CONFIG_R6040 is not set +# CONFIG_SIS900 is not set +# CONFIG_EPIC100 is not set +# CONFIG_SMSC9420 is not set +# CONFIG_SUNDANCE is not set +# CONFIG_TLAN is not set +# CONFIG_KS8842 is not set +# CONFIG_VIA_RHINE is not set +# CONFIG_SC92031 is not set +# CONFIG_ATL2 is not set +CONFIG_NETDEV_1000=y +# CONFIG_ACENIC is not set +# CONFIG_DL2K is not set +# CONFIG_E1000 is not set +# CONFIG_E1000E is not set +# CONFIG_IP1000 is not set +# CONFIG_IGB is not set +# CONFIG_IGBVF is not set +# CONFIG_NS83820 is not set +# CONFIG_HAMACHI is not set +# CONFIG_YELLOWFIN is not set +# CONFIG_R8169 is not set +# CONFIG_SIS190 is not set +# CONFIG_SKGE is not set +# CONFIG_SKY2 is not set +# CONFIG_VIA_VELOCITY is not set +# CONFIG_TIGON3 is not set +# CONFIG_BNX2 is not set +# CONFIG_CNIC is not set +# CONFIG_QLA3XXX is not set +# CONFIG_ATL1 is not set +# CONFIG_ATL1E is not set +# CONFIG_ATL1C is not set +# CONFIG_JME is not set +CONFIG_NETDEV_10000=y +# CONFIG_CHELSIO_T1 is not set +CONFIG_CHELSIO_T3_DEPENDS=y +# CONFIG_CHELSIO_T3 is not set +# CONFIG_ENIC is not set +# CONFIG_IXGBE is not set +# CONFIG_IXGB is not set +# CONFIG_S2IO is not set +# CONFIG_VXGE is not set +# CONFIG_MYRI10GE is not set +# CONFIG_NETXEN_NIC is not set +# CONFIG_NIU is not set +# CONFIG_MLX4_EN is not set +# CONFIG_MLX4_CORE is not set +# CONFIG_TEHUTI is not set +# CONFIG_BNX2X is not set +# CONFIG_QLGE is not set +# CONFIG_SFC is not set +# CONFIG_BE2NET is not set +# CONFIG_TR is not set + +# +# Wireless LAN +# +# CONFIG_WLAN_PRE80211 is not set +# CONFIG_WLAN_80211 is not set + +# +# Enable WiMAX (Networking options) to see the WiMAX drivers +# + +# +# USB Network Adapters +# +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_USBNET is not set +# CONFIG_WAN is not set +# CONFIG_FDDI is not set +# CONFIG_HIPPI is not set +CONFIG_PPP=m +CONFIG_PPP_MULTILINK=y +CONFIG_PPP_FILTER=y +CONFIG_PPP_ASYNC=m +CONFIG_PPP_SYNC_TTY=m +CONFIG_PPP_DEFLATE=m +CONFIG_PPP_BSDCOMP=m +CONFIG_PPP_MPPE=m +CONFIG_PPPOE=m +CONFIG_PPPOL2TP=m +CONFIG_SLIP=m +CONFIG_SLIP_COMPRESSED=y +CONFIG_SLHC=m +CONFIG_SLIP_SMART=y +CONFIG_SLIP_MODE_SLIP6=y +CONFIG_NET_FC=y +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_ISDN is not set +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y +CONFIG_INPUT_FF_MEMLESS=y +# CONFIG_INPUT_POLLDEV is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_MOUSEDEV_PSAUX=y +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +CONFIG_KEYBOARD_ATKBD=y +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_LKKBD is not set +# CONFIG_KEYBOARD_XTKBD is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +CONFIG_INPUT_MOUSE=y +CONFIG_MOUSE_PS2=y +CONFIG_MOUSE_PS2_ALPS=y +CONFIG_MOUSE_PS2_LOGIPS2PP=y +CONFIG_MOUSE_PS2_SYNAPTICS=y +CONFIG_MOUSE_PS2_TRACKPOINT=y +# CONFIG_MOUSE_PS2_ELANTECH is not set +# CONFIG_MOUSE_PS2_TOUCHKIT is not set +CONFIG_MOUSE_SERIAL=y +# CONFIG_MOUSE_APPLETOUCH is not set +# CONFIG_MOUSE_BCM5974 is not set +# CONFIG_MOUSE_INPORT is not set +# CONFIG_MOUSE_LOGIBM is not set +# CONFIG_MOUSE_PC110PAD is not set +# CONFIG_MOUSE_VSXXXAA is not set +# CONFIG_MOUSE_SYNAPTICS_I2C is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +CONFIG_SERIO_I8042=y +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_PCIPS2 is not set +CONFIG_SERIO_LIBPS2=y +# CONFIG_SERIO_RAW is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +CONFIG_DEVKMEM=y +# CONFIG_SERIAL_NONSTANDARD is not set +# CONFIG_NOZOMI is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_PCI=y +CONFIG_SERIAL_8250_NR_UARTS=2 +CONFIG_SERIAL_8250_RUNTIME_UARTS=2 +# CONFIG_SERIAL_8250_EXTENDED is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +# CONFIG_SERIAL_JSM is not set +CONFIG_UNIX98_PTYS=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=256 +# CONFIG_IPMI_HANDLER is not set +CONFIG_HW_RANDOM=y +# CONFIG_HW_RANDOM_TIMERIOMEM is not set +CONFIG_RTC=y +# CONFIG_DTLK is not set +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +CONFIG_DEVPORT=y +CONFIG_I2C=m +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_CHARDEV=m +CONFIG_I2C_HELPER_AUTO=y + +# +# I2C Hardware Bus support +# + +# +# PC SMBus host controller drivers +# +# CONFIG_I2C_ALI1535 is not set +# CONFIG_I2C_ALI1563 is not set +# CONFIG_I2C_ALI15X3 is not set +# CONFIG_I2C_AMD756 is not set +# CONFIG_I2C_AMD8111 is not set +# CONFIG_I2C_I801 is not set +# CONFIG_I2C_ISCH is not set +# CONFIG_I2C_PIIX4 is not set +# CONFIG_I2C_NFORCE2 is not set +# CONFIG_I2C_SIS5595 is not set +# CONFIG_I2C_SIS630 is not set +# CONFIG_I2C_SIS96X is not set +# CONFIG_I2C_VIA is not set +CONFIG_I2C_VIAPRO=m + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_SIMTEC is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_TAOS_EVM is not set +# CONFIG_I2C_TINY_USB is not set + +# +# Graphics adapter I2C/DDC channel drivers +# +# CONFIG_I2C_VOODOO3 is not set + +# +# Other I2C/SMBus bus drivers +# +# CONFIG_I2C_ELEKTOR is not set +# CONFIG_I2C_PCA_ISA is not set +# CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_STUB is not set + +# +# Miscellaneous I2C Chip support +# +# CONFIG_DS1682 is not set +# CONFIG_SENSORS_PCF8574 is not set +# CONFIG_PCF8575 is not set +# CONFIG_SENSORS_PCA9539 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# CONFIG_I2C_DEBUG_CHIP is not set +# CONFIG_SPI is not set + +# +# PPS support +# +# CONFIG_PPS is not set +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +# CONFIG_THERMAL_HWMON is not set +# CONFIG_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_MFD_PCF50633 is not set +# CONFIG_AB3100_CORE is not set +# CONFIG_REGULATOR is not set +# CONFIG_MEDIA_SUPPORT is not set + +# +# Graphics support +# +# CONFIG_DRM is not set +# CONFIG_VGASTATE is not set +CONFIG_VIDEO_OUTPUT_CONTROL=m +CONFIG_FB=y +# CONFIG_FIRMWARE_EDID is not set +# CONFIG_FB_DDC is not set +# CONFIG_FB_BOOT_VESA_SUPPORT is not set +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y +# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set +# CONFIG_FB_SYS_FILLRECT is not set +# CONFIG_FB_SYS_COPYAREA is not set +# CONFIG_FB_SYS_IMAGEBLIT is not set +# CONFIG_FB_FOREIGN_ENDIAN is not set +# CONFIG_FB_SYS_FOPS is not set +# CONFIG_FB_SVGALIB is not set +# CONFIG_FB_MACMODES is not set +CONFIG_FB_BACKLIGHT=y +CONFIG_FB_MODE_HELPERS=y +# CONFIG_FB_TILEBLITTING is not set + +# +# Frame buffer hardware drivers +# +# CONFIG_FB_CIRRUS is not set +# CONFIG_FB_PM2 is not set +# CONFIG_FB_CYBER2000 is not set +# CONFIG_FB_ASILIANT is not set +# CONFIG_FB_IMSTT is not set +# CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_NVIDIA is not set +# CONFIG_FB_RIVA is not set +# CONFIG_FB_MATROX is not set +CONFIG_FB_RADEON=y +# CONFIG_FB_RADEON_I2C is not set +CONFIG_FB_RADEON_BACKLIGHT=y +# CONFIG_FB_RADEON_DEBUG is not set +# CONFIG_FB_ATY128 is not set +# CONFIG_FB_ATY is not set +# CONFIG_FB_S3 is not set +# CONFIG_FB_SAVAGE is not set +# CONFIG_FB_SIS is not set +# CONFIG_FB_VIA is not set +# CONFIG_FB_NEOMAGIC is not set +# CONFIG_FB_KYRO is not set +# CONFIG_FB_3DFX is not set +# CONFIG_FB_VOODOO1 is not set +# CONFIG_FB_VT8623 is not set +# CONFIG_FB_TRIDENT is not set +# CONFIG_FB_ARK is not set +# CONFIG_FB_PM3 is not set +# CONFIG_FB_CARMINE is not set +# CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_METRONOME is not set +# CONFIG_FB_MB862XX is not set +# CONFIG_FB_BROADSHEET is not set +CONFIG_BACKLIGHT_LCD_SUPPORT=y +CONFIG_LCD_CLASS_DEVICE=m +# CONFIG_LCD_ILI9320 is not set +# CONFIG_LCD_PLATFORM is not set +CONFIG_BACKLIGHT_CLASS_DEVICE=y +CONFIG_BACKLIGHT_GENERIC=y + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +# CONFIG_MDA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE=y +# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set +# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set +# CONFIG_FONTS is not set +CONFIG_FONT_8x8=y +CONFIG_FONT_8x16=y +# CONFIG_LOGO is not set +CONFIG_SOUND=y +CONFIG_SOUND_OSS_CORE=y +CONFIG_SND=m +CONFIG_SND_TIMER=m +CONFIG_SND_PCM=m +CONFIG_SND_RAWMIDI=m +CONFIG_SND_SEQUENCER=m +CONFIG_SND_SEQ_DUMMY=m +CONFIG_SND_OSSEMUL=y +CONFIG_SND_MIXER_OSS=m +CONFIG_SND_PCM_OSS=m +CONFIG_SND_PCM_OSS_PLUGINS=y +CONFIG_SND_SEQUENCER_OSS=y +# CONFIG_SND_HRTIMER is not set +# CONFIG_SND_RTCTIMER is not set +# CONFIG_SND_DYNAMIC_MINORS is not set +CONFIG_SND_SUPPORT_OLD_API=y +CONFIG_SND_VERBOSE_PROCFS=y +# CONFIG_SND_VERBOSE_PRINTK is not set +# CONFIG_SND_DEBUG is not set +CONFIG_SND_VMASTER=y +CONFIG_SND_RAWMIDI_SEQ=m +# CONFIG_SND_OPL3_LIB_SEQ is not set +# CONFIG_SND_OPL4_LIB_SEQ is not set +# CONFIG_SND_SBAWE_SEQ is not set +# CONFIG_SND_EMU10K1_SEQ is not set +CONFIG_SND_MPU401_UART=m +CONFIG_SND_AC97_CODEC=m +CONFIG_SND_DRIVERS=y +# CONFIG_SND_DUMMY is not set +# CONFIG_SND_VIRMIDI is not set +# CONFIG_SND_MTPAV is not set +# CONFIG_SND_SERIAL_U16550 is not set +# CONFIG_SND_MPU401 is not set +# CONFIG_SND_AC97_POWER_SAVE is not set +CONFIG_SND_PCI=y +# CONFIG_SND_AD1889 is not set +# CONFIG_SND_ALS300 is not set +# CONFIG_SND_ALI5451 is not set +# CONFIG_SND_ATIIXP is not set +# CONFIG_SND_ATIIXP_MODEM is not set +# CONFIG_SND_AU8810 is not set +# CONFIG_SND_AU8820 is not set +# CONFIG_SND_AU8830 is not set +# CONFIG_SND_AW2 is not set +# CONFIG_SND_AZT3328 is not set +# CONFIG_SND_BT87X is not set +# CONFIG_SND_CA0106 is not set +# CONFIG_SND_CMIPCI is not set +# CONFIG_SND_OXYGEN is not set +# CONFIG_SND_CS4281 is not set +# CONFIG_SND_CS46XX is not set +# CONFIG_SND_CTXFI is not set +# CONFIG_SND_DARLA20 is not set +# CONFIG_SND_GINA20 is not set +# CONFIG_SND_LAYLA20 is not set +# CONFIG_SND_DARLA24 is not set +# CONFIG_SND_GINA24 is not set +# CONFIG_SND_LAYLA24 is not set +# CONFIG_SND_MONA is not set +# CONFIG_SND_MIA is not set +# CONFIG_SND_ECHO3G is not set +# CONFIG_SND_INDIGO is not set +# CONFIG_SND_INDIGOIO is not set +# CONFIG_SND_INDIGODJ is not set +# CONFIG_SND_INDIGOIOX is not set +# CONFIG_SND_INDIGODJX is not set +# CONFIG_SND_EMU10K1 is not set +# CONFIG_SND_EMU10K1X is not set +# CONFIG_SND_ENS1370 is not set +# CONFIG_SND_ENS1371 is not set +# CONFIG_SND_ES1938 is not set +# CONFIG_SND_ES1968 is not set +# CONFIG_SND_FM801 is not set +# CONFIG_SND_HDA_INTEL is not set +# CONFIG_SND_HDSP is not set +# CONFIG_SND_HDSPM is not set +# CONFIG_SND_HIFIER is not set +# CONFIG_SND_ICE1712 is not set +# CONFIG_SND_ICE1724 is not set +# CONFIG_SND_INTEL8X0 is not set +# CONFIG_SND_INTEL8X0M is not set +# CONFIG_SND_KORG1212 is not set +# CONFIG_SND_LX6464ES is not set +# CONFIG_SND_MAESTRO3 is not set +# CONFIG_SND_MIXART is not set +# CONFIG_SND_NM256 is not set +# CONFIG_SND_PCXHR is not set +# CONFIG_SND_RIPTIDE is not set +# CONFIG_SND_RME32 is not set +# CONFIG_SND_RME96 is not set +# CONFIG_SND_RME9652 is not set +# CONFIG_SND_SONICVIBES is not set +# CONFIG_SND_TRIDENT is not set +CONFIG_SND_VIA82XX=m +# CONFIG_SND_VIA82XX_MODEM is not set +# CONFIG_SND_VIRTUOSO is not set +# CONFIG_SND_VX222 is not set +# CONFIG_SND_YMFPCI is not set +CONFIG_SND_MIPS=y +CONFIG_SND_USB=y +# CONFIG_SND_USB_AUDIO is not set +# CONFIG_SND_USB_CAIAQ is not set +# CONFIG_SND_SOC is not set +# CONFIG_SOUND_PRIME is not set +CONFIG_AC97_BUS=m +CONFIG_HID_SUPPORT=y +CONFIG_HID=y +# CONFIG_HID_DEBUG is not set +CONFIG_HIDRAW=y + +# +# USB Input Devices +# +# CONFIG_USB_HID is not set +CONFIG_HID_PID=y + +# +# USB HID Boot Protocol drivers +# +CONFIG_USB_KBD=y +CONFIG_USB_MOUSE=y + +# +# Special HID drivers +# +CONFIG_USB_SUPPORT=y +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y +CONFIG_USB_ARCH_HAS_EHCI=y +CONFIG_USB=y +# CONFIG_USB_DEBUG is not set +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y + +# +# Miscellaneous USB options +# +CONFIG_USB_DEVICEFS=y +# CONFIG_USB_DEVICE_CLASS is not set +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_SUSPEND is not set +# CONFIG_USB_OTG is not set +CONFIG_USB_OTG_WHITELIST=y +# CONFIG_USB_OTG_BLACKLIST_HUB is not set +# CONFIG_USB_MON is not set +# CONFIG_USB_WUSB is not set +CONFIG_USB_WUSB_CBAF=m +# CONFIG_USB_WUSB_CBAF_DEBUG is not set + +# +# USB Host Controller Drivers +# +CONFIG_USB_C67X00_HCD=m +# CONFIG_USB_XHCI_HCD is not set +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y +CONFIG_USB_EHCI_TT_NEWSCHED=y +# CONFIG_USB_OXU210HP_HCD is not set +# CONFIG_USB_ISP116X_HCD is not set +CONFIG_USB_ISP1760_HCD=m +CONFIG_USB_OHCI_HCD=y +# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set +# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +CONFIG_USB_UHCI_HCD=m +# CONFIG_USB_SL811_HCD is not set +CONFIG_USB_R8A66597_HCD=m +# CONFIG_USB_WHCI_HCD is not set +# CONFIG_USB_HWA_HCD is not set + +# +# USB Device Class drivers +# +CONFIG_USB_ACM=y +CONFIG_USB_PRINTER=y +CONFIG_USB_WDM=m +CONFIG_USB_TMC=m + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may +# + +# +# also be needed; see USB_STORAGE Help for more info +# +CONFIG_USB_STORAGE=y +# CONFIG_USB_STORAGE_DEBUG is not set +# CONFIG_USB_STORAGE_DATAFAB is not set +# CONFIG_USB_STORAGE_FREECOM is not set +# CONFIG_USB_STORAGE_ISD200 is not set +# CONFIG_USB_STORAGE_USBAT is not set +# CONFIG_USB_STORAGE_SDDR09 is not set +# CONFIG_USB_STORAGE_SDDR55 is not set +# CONFIG_USB_STORAGE_JUMPSHOT is not set +# CONFIG_USB_STORAGE_ALAUDA is not set +CONFIG_USB_STORAGE_ONETOUCH=y +# CONFIG_USB_STORAGE_KARMA is not set +CONFIG_USB_STORAGE_CYPRESS_ATACB=y +CONFIG_USB_LIBUSUAL=y + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set + +# +# USB port drivers +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +CONFIG_USB_SEVSEG=m +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_BERRY_CHARGE is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_SISUSBVGA is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_TEST is not set +CONFIG_USB_ISIGHTFW=m +CONFIG_USB_VST=m +# CONFIG_USB_GADGET is not set + +# +# OTG and related infrastructure +# +# CONFIG_NOP_USB_XCEIV is not set +# CONFIG_UWB is not set +# CONFIG_MMC is not set +# CONFIG_MEMSTICK is not set +# CONFIG_NEW_LEDS is not set +# CONFIG_ACCESSIBILITY is not set +# CONFIG_INFINIBAND is not set +# CONFIG_RTC_CLASS is not set +# CONFIG_DMADEVICES is not set +# CONFIG_AUXDISPLAY is not set +CONFIG_UIO=m +CONFIG_UIO_CIF=m +# CONFIG_UIO_PDRV is not set +# CONFIG_UIO_PDRV_GENIRQ is not set +# CONFIG_UIO_SMX is not set +# CONFIG_UIO_AEC is not set +# CONFIG_UIO_SERCOS3 is not set + +# +# TI VLYNQ +# +# CONFIG_STAGING is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +CONFIG_EXT2_FS_XIP=y +CONFIG_EXT3_FS=y +# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set +# CONFIG_EXT3_FS_XATTR is not set +CONFIG_EXT4_FS=m +CONFIG_EXT4DEV_COMPAT=y +CONFIG_EXT4_FS_XATTR=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y +CONFIG_FS_XIP=y +CONFIG_JBD=y +# CONFIG_JBD_DEBUG is not set +CONFIG_JBD2=m +# CONFIG_JBD2_DEBUG is not set +CONFIG_FS_MBCACHE=m +CONFIG_REISERFS_FS=m +# CONFIG_REISERFS_CHECK is not set +# CONFIG_REISERFS_PROC_INFO is not set +# CONFIG_REISERFS_FS_XATTR is not set +# CONFIG_JFS_FS is not set +CONFIG_FS_POSIX_ACL=y +# CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_BTRFS_FS is not set +CONFIG_FILE_LOCKING=y +CONFIG_FSNOTIFY=y +CONFIG_DNOTIFY=y +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +CONFIG_AUTOFS_FS=y +CONFIG_AUTOFS4_FS=y +CONFIG_FUSE_FS=y +# CONFIG_CUSE is not set + +# +# Caches +# +# CONFIG_FSCACHE is not set + +# +# CD-ROM/DVD Filesystems +# +CONFIG_ISO9660_FS=m +CONFIG_JOLIET=y +CONFIG_ZISOFS=y +CONFIG_UDF_FS=m +CONFIG_UDF_NLS=y + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=m +CONFIG_MSDOS_FS=m +CONFIG_VFAT_FS=m +CONFIG_FAT_DEFAULT_CODEPAGE=936 +CONFIG_FAT_DEFAULT_IOCHARSET="utf8" +CONFIG_NTFS_FS=m +# CONFIG_NTFS_DEBUG is not set +CONFIG_NTFS_RW=y + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_KCORE=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_JFFS2_FS is not set +# CONFIG_CRAMFS is not set +# CONFIG_SQUASHFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +CONFIG_OMFS_FS=m +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +# CONFIG_NILFS2_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=m +CONFIG_NFS_V3=y +CONFIG_NFS_V3_ACL=y +CONFIG_NFS_V4=y +# CONFIG_NFS_V4_1 is not set +CONFIG_NFSD=m +CONFIG_NFSD_V2_ACL=y +CONFIG_NFSD_V3=y +CONFIG_NFSD_V3_ACL=y +CONFIG_NFSD_V4=y +CONFIG_LOCKD=m +CONFIG_LOCKD_V4=y +CONFIG_EXPORTFS=m +CONFIG_NFS_ACL_SUPPORT=m +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=m +CONFIG_SUNRPC_GSS=m +CONFIG_RPCSEC_GSS_KRB5=m +# CONFIG_RPCSEC_GSS_SPKM3 is not set +CONFIG_SMB_FS=m +CONFIG_SMB_NLS_DEFAULT=y +CONFIG_SMB_NLS_REMOTE="cp936" +CONFIG_CIFS=m +CONFIG_CIFS_STATS=y +CONFIG_CIFS_STATS2=y +CONFIG_CIFS_WEAK_PW_HASH=y +CONFIG_CIFS_XATTR=y +CONFIG_CIFS_POSIX=y +CONFIG_CIFS_DEBUG2=y +CONFIG_CIFS_EXPERIMENTAL=y +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set +# CONFIG_9P_FS is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +# CONFIG_OSF_PARTITION is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_ATARI_PARTITION is not set +# CONFIG_MAC_PARTITION is not set +CONFIG_MSDOS_PARTITION=y +# CONFIG_BSD_DISKLABEL is not set +# CONFIG_MINIX_SUBPARTITION is not set +# CONFIG_SOLARIS_X86_PARTITION is not set +# CONFIG_UNIXWARE_DISKLABEL is not set +# CONFIG_LDM_PARTITION is not set +# CONFIG_SGI_PARTITION is not set +# CONFIG_ULTRIX_PARTITION is not set +# CONFIG_SUN_PARTITION is not set +# CONFIG_KARMA_PARTITION is not set +# CONFIG_EFI_PARTITION is not set +# CONFIG_SYSV68_PARTITION is not set +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="utf8" +# CONFIG_NLS_CODEPAGE_437 is not set +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +CONFIG_NLS_CODEPAGE_936=y +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +# CONFIG_NLS_ASCII is not set +CONFIG_NLS_ISO8859_1=y +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +CONFIG_NLS_UTF8=y +# CONFIG_DLM is not set + +# +# Kernel hacking +# +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_WARN_DEPRECATED=y +# CONFIG_ENABLE_MUST_CHECK is not set +CONFIG_FRAME_WARN=2048 +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_UNUSED_SYMBOLS is not set +CONFIG_DEBUG_FS=y +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_KERNEL is not set +CONFIG_STACKTRACE=y +# CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +CONFIG_SYSCTL_SYSCALL_CHECK=y +CONFIG_NOP_TRACER=y +CONFIG_RING_BUFFER=y +CONFIG_EVENT_TRACING=y +CONFIG_CONTEXT_SWITCH_TRACER=y +CONFIG_TRACING=y +CONFIG_TRACING_SUPPORT=y +# CONFIG_FTRACE is not set +# CONFIG_DYNAMIC_DEBUG is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +CONFIG_CMDLINE="" + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +CONFIG_SECURITY_FILE_CAPABILITIES=y +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +CONFIG_CRYPTO_FIPS=y +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD=m +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_BLKCIPHER=m +CONFIG_CRYPTO_BLKCIPHER2=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG=m +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_PCOMP=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +CONFIG_CRYPTO_GF128MUL=m +# CONFIG_CRYPTO_NULL is not set +CONFIG_CRYPTO_WORKQUEUE=y +# CONFIG_CRYPTO_CRYPTD is not set +CONFIG_CRYPTO_AUTHENC=m +# CONFIG_CRYPTO_TEST is not set + +# +# Authenticated Encryption with Associated Data +# +CONFIG_CRYPTO_CCM=m +CONFIG_CRYPTO_GCM=m +CONFIG_CRYPTO_SEQIV=m + +# +# Block modes +# +CONFIG_CRYPTO_CBC=m +CONFIG_CRYPTO_CTR=m +CONFIG_CRYPTO_CTS=m +CONFIG_CRYPTO_ECB=m +# CONFIG_CRYPTO_LRW is not set +CONFIG_CRYPTO_PCBC=m +CONFIG_CRYPTO_XTS=m + +# +# Hash modes +# +CONFIG_CRYPTO_HMAC=y +# CONFIG_CRYPTO_XCBC is not set + +# +# Digest +# +# CONFIG_CRYPTO_CRC32C is not set +# CONFIG_CRYPTO_MD4 is not set +CONFIG_CRYPTO_MD5=m +# CONFIG_CRYPTO_MICHAEL_MIC is not set +CONFIG_CRYPTO_RMD128=m +CONFIG_CRYPTO_RMD160=m +CONFIG_CRYPTO_RMD256=m +CONFIG_CRYPTO_RMD320=m +CONFIG_CRYPTO_SHA1=m +# CONFIG_CRYPTO_SHA256 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +CONFIG_CRYPTO_AES=m +# CONFIG_CRYPTO_ANUBIS is not set +CONFIG_CRYPTO_ARC4=m +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +CONFIG_CRYPTO_DES=m +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +CONFIG_CRYPTO_SALSA20=m +CONFIG_CRYPTO_SEED=m +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TWOFISH is not set + +# +# Compression +# +CONFIG_CRYPTO_DEFLATE=m +# CONFIG_CRYPTO_ZLIB is not set +CONFIG_CRYPTO_LZO=m + +# +# Random Number Generation +# +CONFIG_CRYPTO_ANSI_CPRNG=m +# CONFIG_CRYPTO_HW is not set +CONFIG_BINARY_PRINTF=y + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_GENERIC_FIND_LAST_BIT=y +CONFIG_CRC_CCITT=y +CONFIG_CRC16=m +# CONFIG_CRC_T10DIF is not set +CONFIG_CRC_ITU_T=m +CONFIG_CRC32=y +CONFIG_CRC7=m +# CONFIG_LIBCRC32C is not set +CONFIG_ZLIB_INFLATE=m +CONFIG_ZLIB_DEFLATE=m +CONFIG_LZO_COMPRESS=m +CONFIG_LZO_DECOMPRESS=m +CONFIG_TEXTSEARCH=y +CONFIG_TEXTSEARCH_KMP=m +CONFIG_TEXTSEARCH_BM=m +CONFIG_TEXTSEARCH_FSM=m +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y +CONFIG_NLATTR=y -- 1.6.2.1 From yuasa.linux@gmail.com Thu Jul 2 17:45:34 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 02 Jul 2009 17:45:41 +0200 (CEST) Received: from mail-px0-f188.google.com ([209.85.216.188]:47647 "EHLO mail-px0-f188.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492027AbZGBPpe (ORCPT ); Thu, 2 Jul 2009 17:45:34 +0200 Received: by pxi26 with SMTP id 26so1590070pxi.22 for ; Thu, 02 Jul 2009 08:39:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:sender:date:from:to:cc :subject:message-id:x-mailer:mime-version:content-type :content-transfer-encoding; bh=W0CwJn6FP8eSWhNc/9Df+pb5JBSONQtG6PRnX3p4PCs=; b=jZGNBb4dBCn7tLAPIGR7uECIVj8MwbOjSq8UjGs5KGymgI3yRRZRbz9YPqO9dCv4gE 4ps5wduo3a1Y2Z/o9dbWz7LnFefBIyjWoCSLj6/nPJ/MQ2naN90znmyiawPqqrOZpLGO YLcA56EToqW/l4I+/1IvXjNGg7jmC2uog28KQ= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:date:from:to:cc:subject:message-id:x-mailer:mime-version :content-type:content-transfer-encoding; b=wFAK2AHNUbzM4sH/Cau2YtS94LkoQkVwu/rQAAhi7dbZBcEZHUVhQnF6HLfx++s4rH T3Pgjovj+TjPdoDVs7GBzwCDGD9+qv5y+0HtzEDBHCIN49E4nC/n3t5gDCjhjdMXEDwp I8adKIWMA/zNm9uor3J3I/hCW7TmKTFNckEDI= Received: by 10.142.154.14 with SMTP id b14mr99273wfe.160.1246549181345; Thu, 02 Jul 2009 08:39:41 -0700 (PDT) Received: from delta (207.5.30.125.dy.iij4u.or.jp [125.30.5.207]) by mx.google.com with ESMTPS id 9sm7114921wfc.16.2009.07.02.08.39.38 (version=TLSv1/SSLv3 cipher=RC4-MD5); Thu, 02 Jul 2009 08:39:40 -0700 (PDT) Date: Fri, 3 Jul 2009 00:39:38 +0900 From: Yoichi Yuasa To: Ralf Baechle Cc: yuasa@linux-mips.org, linux-mips , Linux Kernel Mailing List Subject: [PATCH] update Yoichi's e-mail addresses Message-Id: <20090703003938.96316cd9.yuasa@linux-mips.org> X-Mailer: Sylpheed 2.4.8 (GTK+ 2.12.9; i486-pc-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23629 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: yuasa@linux-mips.org Precedence: bulk X-list: linux-mips Signed-off-by: Yoichi Yuasa diff --git a/arch/mips/cobalt/buttons.c b/arch/mips/cobalt/buttons.c index 9e14398..4eaec8b 100644 --- a/arch/mips/cobalt/buttons.c +++ b/arch/mips/cobalt/buttons.c @@ -1,7 +1,7 @@ /* * Cobalt buttons platform device. * - * Copyright (C) 2007 Yoichi Yuasa + * Copyright (C) 2007 Yoichi Yuasa * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/arch/mips/cobalt/lcd.c b/arch/mips/cobalt/lcd.c index 0720e4f..0f1cd90 100644 --- a/arch/mips/cobalt/lcd.c +++ b/arch/mips/cobalt/lcd.c @@ -1,7 +1,7 @@ /* * Registration of Cobalt LCD platform device. * - * Copyright (C) 2008 Yoichi Yuasa + * Copyright (C) 2008 Yoichi Yuasa * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/arch/mips/cobalt/led.c b/arch/mips/cobalt/led.c index 1c6ebd4..d3ce6fa 100644 --- a/arch/mips/cobalt/led.c +++ b/arch/mips/cobalt/led.c @@ -1,7 +1,7 @@ /* * Registration of Cobalt LED platform device. * - * Copyright (C) 2007 Yoichi Yuasa + * Copyright (C) 2007 Yoichi Yuasa * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/arch/mips/cobalt/mtd.c b/arch/mips/cobalt/mtd.c index 2b088ef..691d620 100644 --- a/arch/mips/cobalt/mtd.c +++ b/arch/mips/cobalt/mtd.c @@ -1,7 +1,7 @@ /* * Registration of Cobalt MTD device. * - * Copyright (C) 2006 Yoichi Yuasa + * Copyright (C) 2006 Yoichi Yuasa * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/arch/mips/cobalt/rtc.c b/arch/mips/cobalt/rtc.c index e70794b..3ab3989 100644 --- a/arch/mips/cobalt/rtc.c +++ b/arch/mips/cobalt/rtc.c @@ -1,7 +1,7 @@ /* * Registration of Cobalt RTC platform device. * - * Copyright (C) 2007 Yoichi Yuasa + * Copyright (C) 2007 Yoichi Yuasa * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/arch/mips/cobalt/serial.c b/arch/mips/cobalt/serial.c index 53b8d0d..7cb51f5 100644 --- a/arch/mips/cobalt/serial.c +++ b/arch/mips/cobalt/serial.c @@ -1,7 +1,7 @@ /* * Registration of Cobalt UART platform device. * - * Copyright (C) 2007 Yoichi Yuasa + * Copyright (C) 2007 Yoichi Yuasa * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/arch/mips/cobalt/time.c b/arch/mips/cobalt/time.c index 4a570e7..0162f9e 100644 --- a/arch/mips/cobalt/time.c +++ b/arch/mips/cobalt/time.c @@ -1,7 +1,7 @@ /* * Cobalt time initialization. * - * Copyright (C) 2007 Yoichi Yuasa + * Copyright (C) 2007 Yoichi Yuasa * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/arch/mips/gt64120/wrppmc/serial.c b/arch/mips/gt64120/wrppmc/serial.c index 5ec1c2f..6f9d085 100644 --- a/arch/mips/gt64120/wrppmc/serial.c +++ b/arch/mips/gt64120/wrppmc/serial.c @@ -1,7 +1,7 @@ /* * Registration of WRPPMC UART platform device. * - * Copyright (C) 2007 Yoichi Yuasa + * Copyright (C) 2007 Yoichi Yuasa * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/arch/mips/include/asm/ds1287.h b/arch/mips/include/asm/ds1287.h index ba1702e..3af0b8f 100644 --- a/arch/mips/include/asm/ds1287.h +++ b/arch/mips/include/asm/ds1287.h @@ -1,7 +1,7 @@ /* * DS1287 timer functions. * - * Copyright (C) 2008 Yoichi Yuasa + * Copyright (C) 2008 Yoichi Yuasa * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/arch/mips/include/asm/irq_gt641xx.h b/arch/mips/include/asm/irq_gt641xx.h index f9a7c3a..250a240 100644 --- a/arch/mips/include/asm/irq_gt641xx.h +++ b/arch/mips/include/asm/irq_gt641xx.h @@ -1,7 +1,7 @@ /* * Galileo/Marvell GT641xx IRQ definitions. * - * Copyright (C) 2007 Yoichi Yuasa + * Copyright (C) 2007 Yoichi Yuasa * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/arch/mips/include/asm/mach-cobalt/irq.h b/arch/mips/include/asm/mach-cobalt/irq.h index 57c8c9a..9da9acf 100644 --- a/arch/mips/include/asm/mach-cobalt/irq.h +++ b/arch/mips/include/asm/mach-cobalt/irq.h @@ -8,7 +8,7 @@ * Copyright (C) 1997 Cobalt Microserver * Copyright (C) 1997, 2003 Ralf Baechle * Copyright (C) 2001-2003 Liam Davies (ldavies@agile.tv) - * Copyright (C) 2007 Yoichi Yuasa + * Copyright (C) 2007 Yoichi Yuasa */ #ifndef _ASM_COBALT_IRQ_H #define _ASM_COBALT_IRQ_H diff --git a/arch/mips/include/asm/mach-cobalt/mach-gt64120.h b/arch/mips/include/asm/mach-cobalt/mach-gt64120.h index ae9c552..f8afec3 100644 --- a/arch/mips/include/asm/mach-cobalt/mach-gt64120.h +++ b/arch/mips/include/asm/mach-cobalt/mach-gt64120.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2006 Yoichi Yuasa + * Copyright (C) 2006 Yoichi Yuasa * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/arch/mips/include/asm/vr41xx/capcella.h b/arch/mips/include/asm/vr41xx/capcella.h index e0ee05a..fcc6569 100644 --- a/arch/mips/include/asm/vr41xx/capcella.h +++ b/arch/mips/include/asm/vr41xx/capcella.h @@ -1,7 +1,7 @@ /* * capcella.h, Include file for ZAO Networks Capcella. * - * Copyright (C) 2002-2004 Yoichi Yuasa + * Copyright (C) 2002-2004 Yoichi Yuasa * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/arch/mips/include/asm/vr41xx/giu.h b/arch/mips/include/asm/vr41xx/giu.h index b369c09..6a90bc1 100644 --- a/arch/mips/include/asm/vr41xx/giu.h +++ b/arch/mips/include/asm/vr41xx/giu.h @@ -1,7 +1,7 @@ /* * Include file for NEC VR4100 series General-purpose I/O Unit. * - * Copyright (C) 2005-2009 Yoichi Yuasa + * Copyright (C) 2005-2009 Yoichi Yuasa * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/arch/mips/include/asm/vr41xx/irq.h b/arch/mips/include/asm/vr41xx/irq.h index d315dfb..b07f732 100644 --- a/arch/mips/include/asm/vr41xx/irq.h +++ b/arch/mips/include/asm/vr41xx/irq.h @@ -7,7 +7,7 @@ * Copyright (C) 2001, 2002 Paul Mundt * Copyright (C) 2002 MontaVista Software, Inc. * Copyright (C) 2002 TimeSys Corp. - * Copyright (C) 2003-2006 Yoichi Yuasa + * Copyright (C) 2003-2006 Yoichi Yuasa * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the diff --git a/arch/mips/include/asm/vr41xx/mpc30x.h b/arch/mips/include/asm/vr41xx/mpc30x.h index 1d67df8..130d09d 100644 --- a/arch/mips/include/asm/vr41xx/mpc30x.h +++ b/arch/mips/include/asm/vr41xx/mpc30x.h @@ -1,7 +1,7 @@ /* * mpc30x.h, Include file for Victor MP-C303/304. * - * Copyright (C) 2002-2004 Yoichi Yuasa + * Copyright (C) 2002-2004 Yoichi Yuasa * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/arch/mips/include/asm/vr41xx/pci.h b/arch/mips/include/asm/vr41xx/pci.h index 6fc01ce..c231a3d 100644 --- a/arch/mips/include/asm/vr41xx/pci.h +++ b/arch/mips/include/asm/vr41xx/pci.h @@ -1,7 +1,7 @@ /* * Include file for NEC VR4100 series PCI Control Unit. * - * Copyright (C) 2004-2005 Yoichi Yuasa + * Copyright (C) 2004-2005 Yoichi Yuasa * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/arch/mips/include/asm/vr41xx/siu.h b/arch/mips/include/asm/vr41xx/siu.h index da9f6e3..ca806bc 100644 --- a/arch/mips/include/asm/vr41xx/siu.h +++ b/arch/mips/include/asm/vr41xx/siu.h @@ -1,7 +1,7 @@ /* * Include file for NEC VR4100 series Serial Interface Unit. * - * Copyright (C) 2005-2008 Yoichi Yuasa + * Copyright (C) 2005-2008 Yoichi Yuasa * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/arch/mips/include/asm/vr41xx/tb0219.h b/arch/mips/include/asm/vr41xx/tb0219.h index dc981b4..c78e824 100644 --- a/arch/mips/include/asm/vr41xx/tb0219.h +++ b/arch/mips/include/asm/vr41xx/tb0219.h @@ -1,7 +1,7 @@ /* * tb0219.h, Include file for TANBAC TB0219. * - * Copyright (C) 2002-2004 Yoichi Yuasa + * Copyright (C) 2002-2004 Yoichi Yuasa * * Modified for TANBAC TB0219: * Copyright (C) 2003 Megasolution Inc. diff --git a/arch/mips/include/asm/vr41xx/tb0226.h b/arch/mips/include/asm/vr41xx/tb0226.h index de527dc..36f5f79 100644 --- a/arch/mips/include/asm/vr41xx/tb0226.h +++ b/arch/mips/include/asm/vr41xx/tb0226.h @@ -1,7 +1,7 @@ /* * tb0226.h, Include file for TANBAC TB0226. * - * Copyright (C) 2002-2004 Yoichi Yuasa + * Copyright (C) 2002-2004 Yoichi Yuasa * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/arch/mips/include/asm/vr41xx/vr41xx.h b/arch/mips/include/asm/vr41xx/vr41xx.h index 22be649..7b96a43 100644 --- a/arch/mips/include/asm/vr41xx/vr41xx.h +++ b/arch/mips/include/asm/vr41xx/vr41xx.h @@ -7,7 +7,7 @@ * Copyright (C) 2001, 2002 Paul Mundt * Copyright (C) 2002 MontaVista Software, Inc. * Copyright (C) 2002 TimeSys Corp. - * Copyright (C) 2003-2008 Yoichi Yuasa + * Copyright (C) 2003-2008 Yoichi Yuasa * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the diff --git a/arch/mips/kernel/cevt-ds1287.c b/arch/mips/kernel/cevt-ds1287.c index 1ada45e..6996da4 100644 --- a/arch/mips/kernel/cevt-ds1287.c +++ b/arch/mips/kernel/cevt-ds1287.c @@ -1,7 +1,7 @@ /* * DS1287 clockevent driver * - * Copyright (C) 2008 Yoichi Yuasa + * Copyright (C) 2008 Yoichi Yuasa * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/arch/mips/kernel/cevt-gt641xx.c b/arch/mips/kernel/cevt-gt641xx.c index e9b787f..92351e0 100644 --- a/arch/mips/kernel/cevt-gt641xx.c +++ b/arch/mips/kernel/cevt-gt641xx.c @@ -1,7 +1,7 @@ /* * GT641xx clockevent routines. * - * Copyright (C) 2007 Yoichi Yuasa + * Copyright (C) 2007 Yoichi Yuasa * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/arch/mips/kernel/csrc-ioasic.c b/arch/mips/kernel/csrc-ioasic.c index b551f48..23da108 100644 --- a/arch/mips/kernel/csrc-ioasic.c +++ b/arch/mips/kernel/csrc-ioasic.c @@ -1,7 +1,7 @@ /* * DEC I/O ASIC's counter clocksource * - * Copyright (C) 2008 Yoichi Yuasa + * Copyright (C) 2008 Yoichi Yuasa * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/arch/mips/kernel/irq-gt641xx.c b/arch/mips/kernel/irq-gt641xx.c index 1b81b13..ebcc5f7 100644 --- a/arch/mips/kernel/irq-gt641xx.c +++ b/arch/mips/kernel/irq-gt641xx.c @@ -1,7 +1,7 @@ /* * GT641xx IRQ routines. * - * Copyright (C) 2007 Yoichi Yuasa + * Copyright (C) 2007 Yoichi Yuasa * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/arch/mips/pci/fixup-capcella.c b/arch/mips/pci/fixup-capcella.c index 1416bca..1c02f57 100644 --- a/arch/mips/pci/fixup-capcella.c +++ b/arch/mips/pci/fixup-capcella.c @@ -1,7 +1,7 @@ /* * fixup-cappcela.c, The ZAO Networks Capcella specific PCI fixups. * - * Copyright (C) 2002,2004 Yoichi Yuasa + * Copyright (C) 2002,2004 Yoichi Yuasa * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/arch/mips/pci/fixup-mpc30x.c b/arch/mips/pci/fixup-mpc30x.c index 5911596..e08f49c 100644 --- a/arch/mips/pci/fixup-mpc30x.c +++ b/arch/mips/pci/fixup-mpc30x.c @@ -1,7 +1,7 @@ /* * fixup-mpc30x.c, The Victor MP-C303/304 specific PCI fixups. * - * Copyright (C) 2002,2004 Yoichi Yuasa + * Copyright (C) 2002,2004 Yoichi Yuasa * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/arch/mips/pci/fixup-tb0219.c b/arch/mips/pci/fixup-tb0219.c index ed87733..8084b17 100644 --- a/arch/mips/pci/fixup-tb0219.c +++ b/arch/mips/pci/fixup-tb0219.c @@ -2,7 +2,7 @@ * fixup-tb0219.c, The TANBAC TB0219 specific PCI fixups. * * Copyright (C) 2003 Megasolution Inc. - * Copyright (C) 2004-2005 Yoichi Yuasa + * Copyright (C) 2004-2005 Yoichi Yuasa * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/arch/mips/pci/fixup-tb0226.c b/arch/mips/pci/fixup-tb0226.c index e3eedf4..4196ccf 100644 --- a/arch/mips/pci/fixup-tb0226.c +++ b/arch/mips/pci/fixup-tb0226.c @@ -1,7 +1,7 @@ /* * fixup-tb0226.c, The TANBAC TB0226 specific PCI fixups. * - * Copyright (C) 2002-2005 Yoichi Yuasa + * Copyright (C) 2002-2005 Yoichi Yuasa * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/arch/mips/pci/fixup-tb0287.c b/arch/mips/pci/fixup-tb0287.c index 267ab3d..2fe29db 100644 --- a/arch/mips/pci/fixup-tb0287.c +++ b/arch/mips/pci/fixup-tb0287.c @@ -1,7 +1,7 @@ /* * fixup-tb0287.c, The TANBAC TB0287 specific PCI fixups. * - * Copyright (C) 2005 Yoichi Yuasa + * Copyright (C) 2005 Yoichi Yuasa * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/arch/mips/pci/ops-vr41xx.c b/arch/mips/pci/ops-vr41xx.c index 900c6b3..28962a7 100644 --- a/arch/mips/pci/ops-vr41xx.c +++ b/arch/mips/pci/ops-vr41xx.c @@ -2,8 +2,8 @@ * ops-vr41xx.c, PCI configuration routines for the PCIU of NEC VR4100 series. * * Copyright (C) 2001-2003 MontaVista Software Inc. - * Author: Yoichi Yuasa - * Copyright (C) 2004-2005 Yoichi Yuasa + * Author: Yoichi Yuasa + * Copyright (C) 2004-2005 Yoichi Yuasa * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -21,7 +21,7 @@ */ /* * Changes: - * MontaVista Software Inc. or + * MontaVista Software Inc. * - New creation, NEC VR4122 and VR4131 are supported. */ #include diff --git a/arch/mips/pci/pci-vr41xx.c b/arch/mips/pci/pci-vr41xx.c index d1e049b..5652571 100644 --- a/arch/mips/pci/pci-vr41xx.c +++ b/arch/mips/pci/pci-vr41xx.c @@ -2,8 +2,8 @@ * pci-vr41xx.c, PCI Control Unit routines for the NEC VR4100 series. * * Copyright (C) 2001-2003 MontaVista Software Inc. - * Author: Yoichi Yuasa - * Copyright (C) 2004-2008 Yoichi Yuasa + * Author: Yoichi Yuasa + * Copyright (C) 2004-2008 Yoichi Yuasa * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org) * * This program is free software; you can redistribute it and/or modify @@ -22,7 +22,7 @@ */ /* * Changes: - * MontaVista Software Inc. or + * MontaVista Software Inc. * - New creation, NEC VR4122 and VR4131 are supported. */ #include diff --git a/arch/mips/pci/pci-vr41xx.h b/arch/mips/pci/pci-vr41xx.h index 8a35e32..6b1ae2e 100644 --- a/arch/mips/pci/pci-vr41xx.h +++ b/arch/mips/pci/pci-vr41xx.h @@ -2,8 +2,8 @@ * pci-vr41xx.h, Include file for PCI Control Unit of the NEC VR4100 series. * * Copyright (C) 2002 MontaVista Software Inc. - * Author: Yoichi Yuasa - * Copyright (C) 2004-2005 Yoichi Yuasa + * Author: Yoichi Yuasa + * Copyright (C) 2004-2005 Yoichi Yuasa * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/arch/mips/vr41xx/casio-e55/setup.c b/arch/mips/vr41xx/casio-e55/setup.c index 6d9bab8..719f4a5 100644 --- a/arch/mips/vr41xx/casio-e55/setup.c +++ b/arch/mips/vr41xx/casio-e55/setup.c @@ -1,7 +1,7 @@ /* * setup.c, Setup for the CASIO CASSIOPEIA E-11/15/55/65. * - * Copyright (C) 2002-2006 Yoichi Yuasa + * Copyright (C) 2002-2006 Yoichi Yuasa * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/arch/mips/vr41xx/common/bcu.c b/arch/mips/vr41xx/common/bcu.c index d77c330..6346c59 100644 --- a/arch/mips/vr41xx/common/bcu.c +++ b/arch/mips/vr41xx/common/bcu.c @@ -2,8 +2,8 @@ * bcu.c, Bus Control Unit routines for the NEC VR4100 series. * * Copyright (C) 2002 MontaVista Software Inc. - * Author: Yoichi Yuasa - * Copyright (C) 2003-2005 Yoichi Yuasa + * Author: Yoichi Yuasa + * Copyright (C) 2003-2005 Yoichi Yuasa * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -21,11 +21,11 @@ */ /* * Changes: - * MontaVista Software Inc. or + * MontaVista Software Inc. * - New creation, NEC VR4122 and VR4131 are supported. * - Added support for NEC VR4111 and VR4121. * - * Yoichi Yuasa + * Yoichi Yuasa * - Added support for NEC VR4133. */ #include diff --git a/arch/mips/vr41xx/common/cmu.c b/arch/mips/vr41xx/common/cmu.c index ad0e8e3..8ba7d04 100644 --- a/arch/mips/vr41xx/common/cmu.c +++ b/arch/mips/vr41xx/common/cmu.c @@ -2,8 +2,8 @@ * cmu.c, Clock Mask Unit routines for the NEC VR4100 series. * * Copyright (C) 2001-2002 MontaVista Software Inc. - * Author: Yoichi Yuasa - * Copuright (C) 2003-2005 Yoichi Yuasa + * Author: Yoichi Yuasa + * Copuright (C) 2003-2005 Yoichi Yuasa * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -21,11 +21,11 @@ */ /* * Changes: - * MontaVista Software Inc. or + * MontaVista Software Inc. * - New creation, NEC VR4122 and VR4131 are supported. * - Added support for NEC VR4111 and VR4121. * - * Yoichi Yuasa + * Yoichi Yuasa * - Added support for NEC VR4133. */ #include diff --git a/arch/mips/vr41xx/common/giu.c b/arch/mips/vr41xx/common/giu.c index 2b272f1..22cc6f2 100644 --- a/arch/mips/vr41xx/common/giu.c +++ b/arch/mips/vr41xx/common/giu.c @@ -1,7 +1,7 @@ /* * NEC VR4100 series GIU platform device. * - * Copyright (C) 2007 Yoichi Yuasa + * Copyright (C) 2007 Yoichi Yuasa * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/arch/mips/vr41xx/common/icu.c b/arch/mips/vr41xx/common/icu.c index 3f23d9f..6d39e22 100644 --- a/arch/mips/vr41xx/common/icu.c +++ b/arch/mips/vr41xx/common/icu.c @@ -2,8 +2,8 @@ * icu.c, Interrupt Control Unit routines for the NEC VR4100 series. * * Copyright (C) 2001-2002 MontaVista Software Inc. - * Author: Yoichi Yuasa - * Copyright (C) 2003-2006 Yoichi Yuasa + * Author: Yoichi Yuasa + * Copyright (C) 2003-2006 Yoichi Yuasa * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -21,11 +21,11 @@ */ /* * Changes: - * MontaVista Software Inc. or + * MontaVista Software Inc. * - New creation, NEC VR4122 and VR4131 are supported. * - Added support for NEC VR4111 and VR4121. * - * Yoichi Yuasa + * Yoichi Yuasa * - Coped with INTASSIGN of NEC VR4133. */ #include diff --git a/arch/mips/vr41xx/common/init.c b/arch/mips/vr41xx/common/init.c index c649953..1386e6f 100644 --- a/arch/mips/vr41xx/common/init.c +++ b/arch/mips/vr41xx/common/init.c @@ -1,7 +1,7 @@ /* * init.c, Common initialization routines for NEC VR4100 series. * - * Copyright (C) 2003-2008 Yoichi Yuasa + * Copyright (C) 2003-2008 Yoichi Yuasa * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/arch/mips/vr41xx/common/irq.c b/arch/mips/vr41xx/common/irq.c index 9cc3891..bef0687 100644 --- a/arch/mips/vr41xx/common/irq.c +++ b/arch/mips/vr41xx/common/irq.c @@ -1,7 +1,7 @@ /* * Interrupt handing routines for NEC VR4100 series. * - * Copyright (C) 2005-2007 Yoichi Yuasa + * Copyright (C) 2005-2007 Yoichi Yuasa * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/arch/mips/vr41xx/common/pmu.c b/arch/mips/vr41xx/common/pmu.c index 028aaf7..692b4e8 100644 --- a/arch/mips/vr41xx/common/pmu.c +++ b/arch/mips/vr41xx/common/pmu.c @@ -1,7 +1,7 @@ /* * pmu.c, Power Management Unit routines for NEC VR4100 series. * - * Copyright (C) 2003-2007 Yoichi Yuasa + * Copyright (C) 2003-2007 Yoichi Yuasa * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/arch/mips/vr41xx/common/rtc.c b/arch/mips/vr41xx/common/rtc.c index 9f26c14..ebc5dcf 100644 --- a/arch/mips/vr41xx/common/rtc.c +++ b/arch/mips/vr41xx/common/rtc.c @@ -1,7 +1,7 @@ /* * NEC VR4100 series RTC platform device. * - * Copyright (C) 2007 Yoichi Yuasa + * Copyright (C) 2007 Yoichi Yuasa * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/arch/mips/vr41xx/common/siu.c b/arch/mips/vr41xx/common/siu.c index 654dee6..54eae56 100644 --- a/arch/mips/vr41xx/common/siu.c +++ b/arch/mips/vr41xx/common/siu.c @@ -1,7 +1,7 @@ /* * NEC VR4100 series SIU platform device. * - * Copyright (C) 2007-2008 Yoichi Yuasa + * Copyright (C) 2007-2008 Yoichi Yuasa * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/arch/mips/vr41xx/common/type.c b/arch/mips/vr41xx/common/type.c index e0c1ac5..ff84142 100644 --- a/arch/mips/vr41xx/common/type.c +++ b/arch/mips/vr41xx/common/type.c @@ -1,7 +1,7 @@ /* * type.c, System type for NEC VR4100 series. * - * Copyright (C) 2005 Yoichi Yuasa + * Copyright (C) 2005 Yoichi Yuasa * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/arch/mips/vr41xx/ibm-workpad/setup.c b/arch/mips/vr41xx/ibm-workpad/setup.c index 9eef297..3982f37 100644 --- a/arch/mips/vr41xx/ibm-workpad/setup.c +++ b/arch/mips/vr41xx/ibm-workpad/setup.c @@ -1,7 +1,7 @@ /* * setup.c, Setup for the IBM WorkPad z50. * - * Copyright (C) 2002-2006 Yoichi Yuasa + * Copyright (C) 2002-2006 Yoichi Yuasa * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/drivers/char/tb0219.c b/drivers/char/tb0219.c index 6062b62..b3ec9b1 100644 --- a/drivers/char/tb0219.c +++ b/drivers/char/tb0219.c @@ -1,7 +1,7 @@ /* * Driver for TANBAC TB0219 base board. * - * Copyright (C) 2005 Yoichi Yuasa + * Copyright (C) 2005 Yoichi Yuasa * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -28,7 +28,7 @@ #include #include -MODULE_AUTHOR("Yoichi Yuasa "); +MODULE_AUTHOR("Yoichi Yuasa "); MODULE_DESCRIPTION("TANBAC TB0219 base board driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/gpio/vr41xx_giu.c b/drivers/gpio/vr41xx_giu.c index f691ffa..b70e061 100644 --- a/drivers/gpio/vr41xx_giu.c +++ b/drivers/gpio/vr41xx_giu.c @@ -2,8 +2,8 @@ * Driver for NEC VR4100 series General-purpose I/O Unit. * * Copyright (C) 2002 MontaVista Software Inc. - * Author: Yoichi Yuasa - * Copyright (C) 2003-2009 Yoichi Yuasa + * Author: Yoichi Yuasa + * Copyright (C) 2003-2009 Yoichi Yuasa * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -37,7 +37,7 @@ #include #include -MODULE_AUTHOR("Yoichi Yuasa "); +MODULE_AUTHOR("Yoichi Yuasa "); MODULE_DESCRIPTION("NEC VR4100 series General-purpose I/O Unit driver"); MODULE_LICENSE("GPL"); diff --git a/drivers/input/misc/cobalt_btns.c b/drivers/input/misc/cobalt_btns.c index 2adf9cb..d114d3a 100644 --- a/drivers/input/misc/cobalt_btns.c +++ b/drivers/input/misc/cobalt_btns.c @@ -1,7 +1,7 @@ /* * Cobalt button interface driver. * - * Copyright (C) 2007-2008 Yoichi Yuasa + * Copyright (C) 2007-2008 Yoichi Yuasa * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -148,7 +148,7 @@ static int __devexit cobalt_buttons_remove(struct platform_device *pdev) return 0; } -MODULE_AUTHOR("Yoichi Yuasa "); +MODULE_AUTHOR("Yoichi Yuasa "); MODULE_DESCRIPTION("Cobalt button interface driver"); MODULE_LICENSE("GPL"); /* work with hotplug and coldplug */ diff --git a/drivers/leds/leds-cobalt-raq.c b/drivers/leds/leds-cobalt-raq.c index ff0e8c3..5f1ce81 100644 --- a/drivers/leds/leds-cobalt-raq.c +++ b/drivers/leds/leds-cobalt-raq.c @@ -1,7 +1,7 @@ /* * LEDs driver for the Cobalt Raq series. * - * Copyright (C) 2007 Yoichi Yuasa + * Copyright (C) 2007 Yoichi Yuasa * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by diff --git a/drivers/pcmcia/vrc4171_card.c b/drivers/pcmcia/vrc4171_card.c index 659421d..d4ad50d 100644 --- a/drivers/pcmcia/vrc4171_card.c +++ b/drivers/pcmcia/vrc4171_card.c @@ -1,7 +1,7 @@ /* * vrc4171_card.c, NEC VRC4171 Card Controller driver for Socket Services. * - * Copyright (C) 2003-2005 Yoichi Yuasa + * Copyright (C) 2003-2005 Yoichi Yuasa * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -32,7 +32,7 @@ #include "i82365.h" MODULE_DESCRIPTION("NEC VRC4171 Card Controllers driver for Socket Services"); -MODULE_AUTHOR("Yoichi Yuasa "); +MODULE_AUTHOR("Yoichi Yuasa "); MODULE_LICENSE("GPL"); #define CARD_MAX_SLOTS 2 diff --git a/drivers/pcmcia/vrc4173_cardu.c b/drivers/pcmcia/vrc4173_cardu.c index 812f038..9b3c158 100644 --- a/drivers/pcmcia/vrc4173_cardu.c +++ b/drivers/pcmcia/vrc4173_cardu.c @@ -6,7 +6,7 @@ * NEC VRC4173 CARDU driver for Socket Services * (This device doesn't support CardBus. it is supporting only 16bit PC Card.) * - * Copyright 2002,2003 Yoichi Yuasa + * Copyright 2002,2003 Yoichi Yuasa * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the @@ -41,7 +41,7 @@ #include "vrc4173_cardu.h" MODULE_DESCRIPTION("NEC VRC4173 CARDU driver for Socket Services"); -MODULE_AUTHOR("Yoichi Yuasa "); +MODULE_AUTHOR("Yoichi Yuasa "); MODULE_LICENSE("GPL"); static int vrc4173_cardu_slots; diff --git a/drivers/pcmcia/vrc4173_cardu.h b/drivers/pcmcia/vrc4173_cardu.h index 7d77c74..a7d9601 100644 --- a/drivers/pcmcia/vrc4173_cardu.h +++ b/drivers/pcmcia/vrc4173_cardu.h @@ -5,7 +5,7 @@ * BRIEF MODULE DESCRIPTION * Include file for NEC VRC4173 CARDU. * - * Copyright 2002 Yoichi Yuasa + * Copyright 2002 Yoichi Yuasa * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the diff --git a/drivers/rtc/rtc-vr41xx.c b/drivers/rtc/rtc-vr41xx.c index f11297a..2c839d0 100644 --- a/drivers/rtc/rtc-vr41xx.c +++ b/drivers/rtc/rtc-vr41xx.c @@ -1,7 +1,7 @@ /* * Driver for NEC VR4100 series Real Time Clock unit. * - * Copyright (C) 2003-2008 Yoichi Yuasa + * Copyright (C) 2003-2008 Yoichi Yuasa * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -33,7 +33,7 @@ #include #include -MODULE_AUTHOR("Yoichi Yuasa "); +MODULE_AUTHOR("Yoichi Yuasa "); MODULE_DESCRIPTION("NEC VR4100 series RTC driver"); MODULE_LICENSE("GPL v2"); diff --git a/drivers/serial/vr41xx_siu.c b/drivers/serial/vr41xx_siu.c index 0573f3b..dac550e 100644 --- a/drivers/serial/vr41xx_siu.c +++ b/drivers/serial/vr41xx_siu.c @@ -1,7 +1,7 @@ /* * Driver for NEC VR4100 series Serial Interface Unit. * - * Copyright (C) 2004-2008 Yoichi Yuasa + * Copyright (C) 2004-2008 Yoichi Yuasa * * Based on drivers/serial/8250.c, by Russell King. * diff --git a/drivers/video/cobalt_lcdfb.c b/drivers/video/cobalt_lcdfb.c index 7bad24e..108b89e 100644 --- a/drivers/video/cobalt_lcdfb.c +++ b/drivers/video/cobalt_lcdfb.c @@ -1,7 +1,7 @@ /* * Cobalt server LCD frame buffer driver. * - * Copyright (C) 2008 Yoichi Yuasa + * Copyright (C) 2008 Yoichi Yuasa * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by From ralf@h5.dl5rb.org.uk Thu Jul 2 17:51:26 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 02 Jul 2009 17:51:33 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:46893 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492027AbZGBPv0 (ORCPT ); Thu, 2 Jul 2009 17:51:26 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id n62FjYIB014232; Thu, 2 Jul 2009 16:45:34 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id n62FjXdD014230; Thu, 2 Jul 2009 16:45:33 +0100 Date: Thu, 2 Jul 2009 16:45:33 +0100 From: Ralf Baechle To: Yoichi Yuasa Cc: linux-mips , Linux Kernel Mailing List Subject: Re: [PATCH] update Yoichi's e-mail addresses Message-ID: <20090702154533.GA14112@linux-mips.org> References: <20090703003938.96316cd9.yuasa@linux-mips.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20090703003938.96316cd9.yuasa@linux-mips.org> User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23630 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Fri, Jul 03, 2009 at 12:39:38AM +0900, Yoichi Yuasa wrote: Thanks, applied. Ralf From bzolnier@gmail.com Thu Jul 2 18:13:41 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 02 Jul 2009 18:13:48 +0200 (CEST) Received: from mail-bw0-f217.google.com ([209.85.218.217]:51224 "EHLO mail-bw0-f217.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492225AbZGBQNl (ORCPT ); Thu, 2 Jul 2009 18:13:41 +0200 Received: by bwz17 with SMTP id 17so1824661bwz.0 for ; Thu, 02 Jul 2009 09:07:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:subject:date :user-agent:cc:references:in-reply-to:mime-version :content-disposition:message-id:content-type :content-transfer-encoding; bh=SQQSLs1YHylWx/9p9OUL9B6gOEsKTCyLShW3MgzTt7c=; b=QCKt36oKy+QZzOHtn2uhPlBtiq7hwDv0jnAeyQuhVLBCU0yKWtK9QwB9KzQFXW2R4D ZpXrOdAwcsqOZMM7+O5TRKoS7y6xZBdN59LaNtwUM7ICKyAL6y7U4OC0nMavC1TuVkiF cJki9klY44HJf13RPViQ3og7Gtq9D/0FRcbLM= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:subject:date:user-agent:cc:references:in-reply-to :mime-version:content-disposition:message-id:content-type :content-transfer-encoding; b=u3HAPR+Uuju6/ppvn+fLwGzVIeTq7uVGhJIrCJf5DW/UidR3+MCsyCR5eYBdtMqkKd liO6MTfRj9SwuGkIxkM746YLDyErCHZ9cTlsMB0GO++4yDMhPgsYAuWpK0FrYkITFRRY kpFT8b93Yc7ti5zh9mTzmPFtXAMIceTZOu0Tc= Received: by 10.103.246.1 with SMTP id y1mr105359mur.120.1246550870331; Thu, 02 Jul 2009 09:07:50 -0700 (PDT) Received: from localhost.localdomain (chello089077034197.chello.pl [89.77.34.197]) by mx.google.com with ESMTPS id 14sm12348829muo.3.2009.07.02.09.07.48 (version=TLSv1/SSLv3 cipher=RC4-MD5); Thu, 02 Jul 2009 09:07:48 -0700 (PDT) From: Bartlomiej Zolnierkiewicz To: wuzhangjin@gmail.com Subject: Re: [Bug #13663] suspend to ram regression (IDE related) Date: Thu, 2 Jul 2009 18:13:56 +0200 User-Agent: KMail/1.11.4 (Linux/2.6.30-next-20090617-09943-g5d77a4c; KDE/4.2.4; i686; ; ) Cc: Jeff Chua , Etienne Basset , David Miller , rjw@sisk.pl, linux-kernel@vger.kernel.org, kernel-testers@vger.kernel.org, Ralf Baechle , linux-mips@linux-mips.org, linux-ide@vger.kernel.org References: <200907011829.16850.bzolnier@gmail.com> <1246499203.9660.52.camel@falcon> In-Reply-To: <1246499203.9660.52.camel@falcon> MIME-Version: 1.0 Content-Disposition: inline Message-Id: <200907021813.57322.bzolnier@gmail.com> Content-Type: Text/Plain; charset="iso-8859-15" Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23631 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: bzolnier@gmail.com Precedence: bulk X-list: linux-mips On Thursday 02 July 2009 03:46:43 Wu Zhangjin wrote: > On Wed, 2009-07-01 at 18:29 +0200, Bartlomiej Zolnierkiewicz wrote: > > On Wednesday 01 July 2009 18:21:25 Bartlomiej Zolnierkiewicz wrote: > > > On Wednesday 01 July 2009 16:47:41 Wu Zhangjin wrote: > > > > On Wed, 2009-07-01 at 22:31 +0800, Jeff Chua wrote: > > > > > On Tue, Jun 30, 2009 at 12:21 AM, Jeff Chua wrote: > > > > > > > > > > > I just tried, and it "seems" to work. Will try a few more cycles. > > > > > > > > > > STD/STR survived quite a few cycles now. Patch seems to be doing the > > > > > right thing. > > > > > > > > > > On Mon, Jun 29, 2009 at 11:51 PM, Etienne > > > > > Basset wrote: > > > > > > > > > > > To have STR/resume work with current git, I have to : > > > > > > > > > > > 1) apply Bart's patch > > > > > > > > > > This is not yet in Linus's tree. And much needed to really fix the problem. > > > > > > > > > > > 2) revert this commit : a1317f714af7aed60ddc182d0122477cbe36ee9b > > > > > > > > > > > > > Yes, This commit must be reverted, otherwise, STD/Hibernation will not > > > > work either. I have tested it on two different loongson-based machines: > > > > fuloong2e box and yeeloong2f netbook.(loongson is mips compatiable) > > > > > > Since it seems like Dave is taking his sweet time with doing the revert > > > I stared at the code a bit more and I think that I finally found the bug > > > (thanks to your debugging work for giving me the right hint!). > > > > > > The patch needs to take into the account a new code introduced by the recent > > > block layer changes (commit 8f6205cd572fece673da0255d74843680f67f879): > > > > > > @@ -555,8 +560,11 @@ repeat: > > > startstop = start_request(drive, rq); > > > spin_lock_irq(&hwif->lock); > > > > > > - if (startstop == ide_stopped) > > > + if (startstop == ide_stopped) { > > > + rq = hwif->rq; > > > + hwif->rq = NULL; > > > goto repeat; > > > + } > > > } else > > > goto plug_device; > > > out: > > > > > > and not zero hwif->rq if the device is blocked. > > > > > > Could you try the attached patch and see if it fixes the issue? > > > > Here is the more complete version, also taking into the account changes > > in ide_intr() and ide_timer_expiry(): > > > > Sorry, I can not apply this patch directly, which original version did > you use? I used the one in the master branch of linux-mips development > git repository. > > commit 5a4f13fad1ab5bd08dea78fc55321e429d83cddf > Merge: ec9c45d e18ed14 > Author: Linus Torvalds > Date: Mon Jun 29 20:07:43 2009 -0700 > > Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/ide-2.6 > > * git://git.kernel.org/pub/scm/linux/kernel/git/davem/ide-2.6: > ide: memory overrun in ide_get_identity_ioctl() on big endian > machines using ioctl HDIO_OBSOLETE_IDENTITY > ide: fix resume for CONFIG_BLK_DEV_IDEACPI=y > ide-cd: handle fragmented packet commands gracefully > ide: always kill the whole request on error > ide: fix ide_kill_rq() for special ide-{floppy,tape} driver > requests > > it this too old? should i merge another git repository? Weird, I used linux-next but Linus' tree should also be fine (as it matches linux-next w.r.t. ide currently). Anyway since the patch was confirmed to fix the problem by Jeff and Etienne here is the final version for Dave. From: Bartlomiej Zolnierkiewicz Subject: [PATCH] ide: make resume work again It turns out that commit a1317f714af7aed60ddc182d0122477cbe36ee9b ("ide: improve handling of Power Management requests") needs to take into the account a new code added by the recent block layer changes in commit 8f6205cd572fece673da0255d74843680f67f879 ("ide: dequeue in-flight request") and prevent clearing of hwif->rq if the device is blocked. Thanks to Etienne, Wu and Jeff for help in fixing the issue. Reported-and-tested-by: Jeff Chua Reported-and-tested-by: Etienne Basset Reported-by: Wu Zhangjin Signed-off-by: Bartlomiej Zolnierkiewicz --- Added patch description, no other changes. drivers/ide/ide-io.c | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) Index: b/drivers/ide/ide-io.c =================================================================== --- a/drivers/ide/ide-io.c +++ b/drivers/ide/ide-io.c @@ -532,7 +532,8 @@ repeat: if (startstop == ide_stopped) { rq = hwif->rq; - hwif->rq = NULL; + if ((drive->dev_flags & IDE_DFLAG_BLOCKED) == 0) + hwif->rq = NULL; goto repeat; } } else @@ -679,8 +680,10 @@ void ide_timer_expiry (unsigned long dat spin_lock_irq(&hwif->lock); enable_irq(hwif->irq); if (startstop == ide_stopped && hwif->polling == 0) { - rq_in_flight = hwif->rq; - hwif->rq = NULL; + if ((drive->dev_flags & IDE_DFLAG_BLOCKED) == 0) { + rq_in_flight = hwif->rq; + hwif->rq = NULL; + } ide_unlock_port(hwif); plug_device = 1; } @@ -856,8 +859,10 @@ irqreturn_t ide_intr (int irq, void *dev */ if (startstop == ide_stopped && hwif->polling == 0) { BUG_ON(hwif->handler); - rq_in_flight = hwif->rq; - hwif->rq = NULL; + if ((drive->dev_flags & IDE_DFLAG_BLOCKED) == 0) { + rq_in_flight = hwif->rq; + hwif->rq = NULL; + } ide_unlock_port(hwif); plug_device = 1; } From pavel@ucw.cz Thu Jul 2 23:51:00 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 02 Jul 2009 23:51:07 +0200 (CEST) Received: from atrey.karlin.mff.cuni.cz ([195.113.26.193]:36986 "EHLO atrey.karlin.mff.cuni.cz" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492259AbZGBVvA (ORCPT ); Thu, 2 Jul 2009 23:51:00 +0200 Received: by atrey.karlin.mff.cuni.cz (Postfix, from userid 512) id 3A90BF0075; Thu, 2 Jul 2009 23:45:10 +0200 (CEST) Date: Thu, 2 Jul 2009 23:45:03 +0200 From: Pavel Machek To: Wu Zhangjin Cc: LKML , linux-mips@linux-mips.org, Ralf Baechle , Wu Zhangjin Subject: Re: [PATCH] [MIPS] Hibernation: only save pages in system ram Message-ID: <20090702214503.GC1485@ucw.cz> References: <1246373570-21090-1-git-send-email-wuzhangjin@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1246373570-21090-1-git-send-email-wuzhangjin@gmail.com> User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23632 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: pavel@ucw.cz Precedence: bulk X-list: linux-mips > arch/mips/include/asm/page.h: > > ... > #ifdef CONFIG_FLATMEM > > #define pfn_valid(pfn) ((pfn) >= ARCH_PFN_OFFSET && (pfn) < max_mapnr) > > #elif defined(CONFIG_SPARSEMEM) > > /* pfn_valid is defined in linux/mmzone.h */ > ... > > we can rewrite pfn_valid(pfn) to fix this problem, but I really do not > want to touch such a widely-used macro, so, I used another solution: Well, fixing pfn_valid() is the right way to go. It makes mips behave like other architectures. Please do that. > Signed-off-by: Wu Zhangjin NAK. -- (english) http://www.livejournal.com/~pavelmachek (cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html From raghu@mips.com Thu Jul 2 23:52:33 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 02 Jul 2009 23:52:40 +0200 (CEST) Received: from dns1.mips.com ([63.167.95.197]:35404 "EHLO dns1.mips.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492259AbZGBVwd convert rfc822-to-8bit (ORCPT ); Thu, 2 Jul 2009 23:52:33 +0200 Received: from MTVEXCHANGE.mips.com ([192.168.36.200]) by dns1.mips.com (8.13.8/8.13.8) with ESMTP id n62LkYMS002498; Thu, 2 Jul 2009 14:46:34 -0700 X-MimeOLE: Produced By Microsoft Exchange V6.5 Content-class: urn:content-classes:message MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT Subject: RE: [PATCH 15/15] Do not rely on the initial state of TC/VPE bindings when doing cross VPE writes Date: Thu, 2 Jul 2009 14:46:33 -0700 Message-ID: <94BD67F8AF3ED34FA362C662BA1F12C503BED88E@MTVEXCHANGE.mips.com> In-Reply-To: <4A4C314B.2070907@paralogos.com> X-MS-Has-Attach: X-MS-TNEF-Correlator: Thread-Topic: [PATCH 15/15] Do not rely on the initial state of TC/VPE bindings when doing cross VPE writes Thread-Index: Acn6yebEd3mdyMljTYGXo08swKSRNAAlE9eA References: <20090702023938.23268.65453.stgit@linux-raghu> <20090702024331.23268.98671.stgit@linux-raghu> <4A4C314B.2070907@paralogos.com> From: "Gandham, Raghu" To: "Kevin D. Kissell" Cc: , "Dearman, Chris" Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23633 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: raghu@mips.com Precedence: bulk X-list: linux-mips > -----Original Message----- > From: Kevin D. Kissell [mailto:kevink@paralogos.com] > Sent: Wednesday, July 01, 2009 9:02 PM > To: Gandham, Raghu > Cc: linux-mips@linux-mips.org; Dearman, Chris > Subject: Re: [PATCH 15/15] Do not rely on the initial state of TC/VPE > bindings when doing cross VPE writes > > Note that, regardless of the reset state, smtc_configure_tlb() should > have at least temporarily bound TC 1 to VPE1, which may be why this > never seemed to be a problem on the 34K. If one wants to support > designs with more than 2 VPEs, then this is probably one of the things > that needs to be fixed. That having been said, rather than adding a > usually-redundant write_vpe_c0_vpeconf0() in that clause, wouldn't it be > cleaner to just move the MVP setting from the top of the loop to the > point in the loop just after the TCs have been bound to the VPE in > question, i.e., > > 454 if (slop) { > 455 if (tc != 0) { > 456 smtc_tc_setup(vpe,tc, cpu); > 457 cpu++; > 458 } > 459 printk(" %d", tc); > 460 tc++; > 461 slop--; > 462 } > > write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() | > VPECONF0_MVP); > > 463 if (vpe != 0) { > 464 /* > 465 * Clear any stale software interrupts from > VPE's Cause > 466 */ > > This should definitely be OK for a 34K, because it's being executed by > TC0 in VPE0 and the reset state of VPE0 has MVP set. If it weren't, > smtc_configure_tlb() would have failed. > > Regards, > > Kevin K. I will resend this patch with your suggestion. Thanks, Raghu > > Raghu Gandham wrote: > > From: Kurt Martin > > > > Signed-off-by: Jaidev Patwardhan > > Signed-off-by: Chris Dearman > > --- > > > > arch/mips/kernel/smtc.c | 12 ++++++++++++ > > 1 files changed, 12 insertions(+), 0 deletions(-) > > > > diff --git a/arch/mips/kernel/smtc.c b/arch/mips/kernel/smtc.c > > index 69240c4..3498b82 100644 > > --- a/arch/mips/kernel/smtc.c > > +++ b/arch/mips/kernel/smtc.c > > @@ -481,6 +481,18 @@ void smtc_prepare_cpus(int cpus) > > */ > > if (tc != 0) { > > smtc_tc_setup(vpe, tc, cpu); > > + if (vpe != 0) { > > + /* > > + * Set MVP bit (possibly again). Do it > > + * here to catch CPUs that have no TCs > > + * bound to the VPE at reset. In that > > + * case, a TC must be bound to the VPE > > + * before we can set VPEControl[MVP] > > + */ > > + write_vpe_c0_vpeconf0( > > + read_vpe_c0_vpeconf0() | > > + VPECONF0_MVP); > > + } > > cpu++; > > } > > printk(" %d", tc); > > > > > > From kevink@paralogos.com Fri Jul 3 00:14:49 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 03 Jul 2009 00:14:55 +0200 (CEST) Received: from gateway10.websitewelcome.com ([69.93.243.28]:38334 "HELO gateway10.websitewelcome.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with SMTP id S1492291AbZGBWOt (ORCPT ); Fri, 3 Jul 2009 00:14:49 +0200 Received: (qmail 22428 invoked from network); 2 Jul 2009 22:14:37 -0000 Received: from gator750.hostgator.com (174.132.194.2) by gateway10.websitewelcome.com with SMTP; 2 Jul 2009 22:14:37 -0000 Received: from 216-239-45-4.google.com ([216.239.45.4]:31919 helo=epiktistes.mtv.corp.google.com) by gator750.hostgator.com with esmtpa (Exim 4.69) (envelope-from ) id 1MMUSY-0003U7-AQ; Thu, 02 Jul 2009 17:08:50 -0500 Message-ID: <4A4D2FF2.8080408@paralogos.com> Date: Thu, 02 Jul 2009 15:08:50 -0700 From: "Kevin D. Kissell" User-Agent: Thunderbird 2.0.0.21 (X11/20090318) MIME-Version: 1.0 To: "Gandham, Raghu" CC: linux-mips@linux-mips.org, "Dearman, Chris" Subject: Re: [PATCH 15/15] Do not rely on the initial state of TC/VPE bindings when doing cross VPE writes References: <20090702023938.23268.65453.stgit@linux-raghu> <20090702024331.23268.98671.stgit@linux-raghu> <4A4C314B.2070907@paralogos.com> <94BD67F8AF3ED34FA362C662BA1F12C503BED88E@MTVEXCHANGE.mips.com> In-Reply-To: <94BD67F8AF3ED34FA362C662BA1F12C503BED88E@MTVEXCHANGE.mips.com> Content-Type: multipart/alternative; boundary="------------040608050003040609020009" X-AntiAbuse: This header was added to track abuse, please include it with any abuse report X-AntiAbuse: Primary Hostname - gator750.hostgator.com X-AntiAbuse: Original Domain - linux-mips.org X-AntiAbuse: Originator/Caller UID/GID - [47 12] / [47 12] X-AntiAbuse: Sender Address Domain - paralogos.com Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23634 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: kevink@paralogos.com Precedence: bulk X-list: linux-mips This is a multi-part message in MIME format. --------------040608050003040609020009 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Gandham, Raghu wrote: > >> -----Original Message----- >> From: Kevin D. Kissell [mailto:kevink@paralogos.com] >> Sent: Wednesday, July 01, 2009 9:02 PM >> To: Gandham, Raghu >> Cc: linux-mips@linux-mips.org; Dearman, Chris >> Subject: Re: [PATCH 15/15] Do not rely on the initial state of TC/VPE >> bindings when doing cross VPE writes >> >> Note that, regardless of the reset state, smtc_configure_tlb() should >> have at least temporarily bound TC 1 to VPE1, which may be why this >> never seemed to be a problem on the 34K. If one wants to support >> designs with more than 2 VPEs, then this is probably one of the things >> that needs to be fixed. That having been said, rather than adding a >> usually-redundant write_vpe_c0_vpeconf0() in that clause, wouldn't it >> > be > >> cleaner to just move the MVP setting from the top of the loop to the >> point in the loop just after the TCs have been bound to the VPE in >> question, i.e., >> >> 454 if (slop) { >> 455 if (tc != 0) { >> 456 smtc_tc_setup(vpe,tc, cpu); >> 457 cpu++; >> 458 } >> 459 printk(" %d", tc); >> 460 tc++; >> 461 slop--; >> 462 } >> >> write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() | >> VPECONF0_MVP); >> >> 463 if (vpe != 0) { >> 464 /* >> 465 * Clear any stale software interrupts >> > from > >> VPE's Cause >> 466 */ >> >> This should definitely be OK for a 34K, because it's being executed by >> TC0 in VPE0 and the reset state of VPE0 has MVP set. If it weren't, >> smtc_configure_tlb() would have failed. >> >> Regards, >> >> Kevin K. >> > > > I will resend this patch with your suggestion. > > Thanks, > Raghu > Just make sure it works, first! ;o) I'm thousands of miles away from my build/test systems. Regards, Kevn K. --------------040608050003040609020009 Content-Type: text/html; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Gandham, Raghu wrote: 
  
-----Original Message-----
From: Kevin D. Kissell [mailto:kevink@paralogos.com]
Sent: Wednesday, July 01, 2009 9:02 PM
To: Gandham, Raghu
Cc: linux-mips@linux-mips.org; Dearman, Chris
Subject: Re: [PATCH 15/15] Do not rely on the initial state of TC/VPE
bindings when doing cross VPE writes

Note that, regardless of the reset state, smtc_configure_tlb() should
have at least temporarily bound TC 1 to VPE1, which may be why this
never seemed to be a problem on the 34K.  If one wants to support
designs with more than 2 VPEs, then this is probably one of the things
that needs to be fixed.  That having been said, rather than adding a
usually-redundant write_vpe_c0_vpeconf0() in that clause, wouldn't it
    
be
  
cleaner to just move the MVP setting from the top of the loop to the
point in the loop just after the TCs have been bound to the VPE in
question, i.e.,

 454                 if (slop) {
 455                         if (tc != 0) {
 456                                 smtc_tc_setup(vpe,tc, cpu);
 457                                 cpu++;
 458                         }
 459                         printk(" %d", tc);
 460                         tc++;
 461                         slop--;
 462                 }

                        write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() |
VPECONF0_MVP);

 463                 if (vpe != 0) {
 464                         /*
 465                          * Clear any stale software interrupts
    
from
  
VPE's Cause
 466                          */

This should definitely be OK for a 34K, because it's being executed by
TC0 in VPE0 and the reset state of VPE0 has MVP set.  If it weren't,
smtc_configure_tlb() would have failed.

          Regards,

          Kevin K.
    


I will resend this patch with your suggestion.

Thanks,
Raghu
Just make sure it works, first!  ;o)  I'm thousands of miles away from my build/test systems.

          Regards,

          Kevn K.
--------------040608050003040609020009-- From ralf@h5.dl5rb.org.uk Fri Jul 3 01:28:13 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 03 Jul 2009 01:28:20 +0200 (CEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:53072 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492302AbZGBX2N (ORCPT ); Fri, 3 Jul 2009 01:28:13 +0200 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id n62NM7PN017769; Fri, 3 Jul 2009 00:22:07 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id n62NM5qJ017767; Fri, 3 Jul 2009 00:22:05 +0100 Date: Fri, 3 Jul 2009 00:22:05 +0100 From: Ralf Baechle To: Wu Zhangjin Cc: LKML , linux-mips@linux-mips.org, Pavel Machek , Wu Zhangjin Subject: Re: [PATCH] [MIPS] Hibernation: only save pages in system ram Message-ID: <20090702232205.GE14804@linux-mips.org> References: <1246373570-21090-1-git-send-email-wuzhangjin@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1246373570-21090-1-git-send-email-wuzhangjin@gmail.com> User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23635 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Tue, Jun 30, 2009 at 10:52:50PM +0800, Wu Zhangjin wrote: > From: Wu Zhangjin > > when using hibernation(STD) with CONFIG_FLATMEM in linux-mips-64bit, it > fails for the current mips-specific hibernation implementation save the > pages in all of the memory space(except the nosave section) and make > there will be not enough memory left to the STD task itself, and then > fail. in reality, we only need to save the pages in system rams. > > here is the reason why it fail: > > kernel/power/snapshot.c: > > static void mark_nosave_pages(struct memory_bitmap *bm) > { > ... > if (pfn_valid(pfn)) { > ... > } > } > > arch/mips/include/asm/page.h: > > ... > #ifdef CONFIG_FLATMEM > > #define pfn_valid(pfn) ((pfn) >= ARCH_PFN_OFFSET && (pfn) < max_mapnr) > > #elif defined(CONFIG_SPARSEMEM) > > /* pfn_valid is defined in linux/mmzone.h */ > ... > > we can rewrite pfn_valid(pfn) to fix this problem, but I really do not > want to touch such a widely-used macro, so, I used another solution: > > static struct page *saveable_page(struct zone *zone, unsigned long pfn) > { > ... > if ( .... pfn_is_nosave(pfn) > return NULL; > ... > } > > and pfn_is_nosave is implemented in arch/mips/power/cpu.c, so, hacking > this one is better. No - pfn_valid() is broken, so it should be fixed. Commit 752fbeb2e3555c0d236e992f1195fd7ce30e728d introduced the breakage. It seemed to assume that the valid range for PFNs doesn't start at 0 but some higher number but got that entirely wrong.. #define ARCH_PFN_OFFSET PFN_UP(PHYS_OFFSET) #define pfn_valid(pfn) ((pfn) >= ARCH_PFN_OFFSET && (pfn) < max_mapnr) works nicely when PHYS_OFFSET is 0 - as for most MIPS systems and goes horribly wrong otherwise. So I suggest below patch. Ralf Signed-off-by: Ralf Baechle arch/mips/include/asm/page.h | 9 ++++++++- 1 files changed, 8 insertions(+), 1 deletions(-) diff --git a/arch/mips/include/asm/page.h b/arch/mips/include/asm/page.h index dc0eaa7..96a14a4 100644 --- a/arch/mips/include/asm/page.h +++ b/arch/mips/include/asm/page.h @@ -165,7 +165,14 @@ typedef struct { unsigned long pgprot; } pgprot_t; #ifdef CONFIG_FLATMEM -#define pfn_valid(pfn) ((pfn) >= ARCH_PFN_OFFSET && (pfn) < max_mapnr) +#define pfn_valid(pfn) \ +({ \ + unsigned long __pfn = (pfn); \ + /* avoid include hell */ \ + extern unsigned long min_low_pfn; \ + \ + __pfn >= min_low_pfn && __pfn < max_mapnr; \ +}) #elif defined(CONFIG_SPARSEMEM) From rjw@sisk.pl Fri Jul 3 01:28:37 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 03 Jul 2009 01:28:46 +0200 (CEST) Received: from ogre.sisk.pl ([217.79.144.158]:39960 "EHLO ogre.sisk.pl" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492308AbZGBX2U (ORCPT ); Fri, 3 Jul 2009 01:28:20 +0200 Received: from localhost (localhost.localdomain [127.0.0.1]) by ogre.sisk.pl (Postfix) with ESMTP id 8259B1481A5; Fri, 3 Jul 2009 01:16:48 +0200 (CEST) Received: from ogre.sisk.pl ([127.0.0.1]) by localhost (ogre.sisk.pl [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 17198-05; Fri, 3 Jul 2009 01:16:41 +0200 (CEST) Received: from tosh.localnet (220-bem-13.acn.waw.pl [82.210.184.220]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by ogre.sisk.pl (Postfix) with ESMTP id 906851480B1; Fri, 3 Jul 2009 01:16:41 +0200 (CEST) From: "Rafael J. Wysocki" To: Wu Zhangjin Subject: Re: [PATCH] [MIPS] Hibernation: only save pages in system ram Date: Fri, 3 Jul 2009 01:22:40 +0200 User-Agent: KMail/1.11.2 (Linux/2.6.31-rc1-rjw; KDE/4.2.4; x86_64; ; ) Cc: LKML , linux-mips@linux-mips.org, Pavel Machek , Ralf Baechle , Wu Zhangjin References: <1246373570-21090-1-git-send-email-wuzhangjin@gmail.com> In-Reply-To: <1246373570-21090-1-git-send-email-wuzhangjin@gmail.com> MIME-Version: 1.0 Content-Type: Text/Plain; charset="iso-8859-2" Content-Transfer-Encoding: 7bit Content-Disposition: inline Message-Id: <200907030122.41176.rjw@sisk.pl> X-Virus-Scanned: amavisd-new at ogre.sisk.pl using MkS_Vir for Linux Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23636 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: rjw@sisk.pl Precedence: bulk X-list: linux-mips On Tuesday 30 June 2009, Wu Zhangjin wrote: > From: Wu Zhangjin > > when using hibernation(STD) with CONFIG_FLATMEM in linux-mips-64bit, it > fails for the current mips-specific hibernation implementation save the > pages in all of the memory space(except the nosave section) and make > there will be not enough memory left to the STD task itself, and then > fail. in reality, we only need to save the pages in system rams. > > here is the reason why it fail: > > kernel/power/snapshot.c: > > static void mark_nosave_pages(struct memory_bitmap *bm) > { > ... > if (pfn_valid(pfn)) { > ... > } > } > > arch/mips/include/asm/page.h: > > ... > #ifdef CONFIG_FLATMEM > > #define pfn_valid(pfn) ((pfn) >= ARCH_PFN_OFFSET && (pfn) < max_mapnr) > > #elif defined(CONFIG_SPARSEMEM) > > /* pfn_valid is defined in linux/mmzone.h */ > ... > > we can rewrite pfn_valid(pfn) to fix this problem, but I really do not > want to touch such a widely-used macro, so, I used another solution: > > static struct page *saveable_page(struct zone *zone, unsigned long pfn) > { > ... > if ( .... pfn_is_nosave(pfn) > return NULL; > ... > } > > and pfn_is_nosave is implemented in arch/mips/power/cpu.c, so, hacking > this one is better. Not really. Could that be handled with the help of register_nosave_region() or register_nosave_region_late() instead? Best, Rafael > Signed-off-by: Wu Zhangjin > --- > arch/mips/power/cpu.c | 19 ++++++++++++++++++- > 1 files changed, 18 insertions(+), 1 deletions(-) > > diff --git a/arch/mips/power/cpu.c b/arch/mips/power/cpu.c > index 7995df4..ef472e3 100644 > --- a/arch/mips/power/cpu.c > +++ b/arch/mips/power/cpu.c > @@ -10,6 +10,7 @@ > #include > #include > #include > +#include > > static u32 saved_status; > struct pt_regs saved_regs; > @@ -34,10 +35,26 @@ void restore_processor_state(void) > restore_dsp(current); > } > > +int pfn_in_system_ram(unsigned long pfn) > +{ > + int i; > + > + for (i = 0; i < boot_mem_map.nr_map; i++) { > + if (boot_mem_map.map[i].type == BOOT_MEM_RAM) { > + if ((pfn >= (boot_mem_map.map[i].addr >> PAGE_SHIFT)) && > + ((pfn) < ((boot_mem_map.map[i].addr + > + boot_mem_map.map[i].size) >> PAGE_SHIFT))) > + return 1; > + } > + } > + return 0; > +} > + > int pfn_is_nosave(unsigned long pfn) > { > unsigned long nosave_begin_pfn = PFN_DOWN(__pa(&__nosave_begin)); > unsigned long nosave_end_pfn = PFN_UP(__pa(&__nosave_end)); > > - return (pfn >= nosave_begin_pfn) && (pfn < nosave_end_pfn); > + return ((pfn >= nosave_begin_pfn) && (pfn < nosave_end_pfn)) > + || !pfn_in_system_ram(pfn); > } From wuzhangjin@gmail.com Fri Jul 3 05:27:50 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 03 Jul 2009 05:27:57 +0200 (CEST) Received: from mail-px0-f188.google.com ([209.85.216.188]:36920 "EHLO mail-px0-f188.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1491805AbZGCD1u (ORCPT ); Fri, 3 Jul 2009 05:27:50 +0200 Received: by pxi26 with SMTP id 26so1930106pxi.22 for ; Thu, 02 Jul 2009 20:21:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:subject:from:reply-to:to:cc :in-reply-to:references:content-type:organization:date:message-id :mime-version:x-mailer:content-transfer-encoding; bh=uXm4id/EPpmJZsuSRGEd+/zGCjCCUjg9qIVyw7tazSA=; b=vaKUl9HZ+U0pjHIoJW/flqCVRSXIzeWo3fftkXsZzkJCr+O5P2YQJHl5L205ts8Eu0 rAjdviUmsnmEok6Xim2peXJ1wD5fU550Qjmq3wsS/oPrLKM7cvpxEkZHqist2Fy4RJBl MI0+a2SnmPkn18VDQsyGu0Yw3G524ngwMjfVI= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=subject:from:reply-to:to:cc:in-reply-to:references:content-type :organization:date:message-id:mime-version:x-mailer :content-transfer-encoding; b=l+1qGrKb5LsvyvkpujEVc/QezA+DZ/QcD56Z7WjiHkK7gCsLIHe9yEwXr5MdnboWTb WldI419cDUjTpV1/CzDaoGPWAdY+oDzP9OKBfvXwIS4NwttfYA2J43A1QZ7YUVcLH8HD m4eTMISCLrMG+EN5YEraYRnfq4Jgg9T3x8+/4= Received: by 10.115.60.11 with SMTP id n11mr1112511wak.116.1246591309435; Thu, 02 Jul 2009 20:21:49 -0700 (PDT) Received: from ?172.16.2.101? ([222.92.8.142]) by mx.google.com with ESMTPS id k21sm5406833waf.24.2009.07.02.20.21.45 (version=TLSv1/SSLv3 cipher=RC4-MD5); Thu, 02 Jul 2009 20:21:48 -0700 (PDT) Subject: Re: [PATCH] [MIPS] Hibernation: only save pages in system ram From: Wu Zhangjin Reply-To: wuzhangjin@gmail.com To: Ralf Baechle Cc: LKML , linux-mips@linux-mips.org, Pavel Machek , "Rafael J. Wysocki" , Bartlomiej Zolnierkiewicz In-Reply-To: <20090702232205.GE14804@linux-mips.org> References: <1246373570-21090-1-git-send-email-wuzhangjin@gmail.com> <20090702232205.GE14804@linux-mips.org> Content-Type: text/plain Organization: DSLab, Lanzhou University, China Date: Fri, 03 Jul 2009 11:21:37 +0800 Message-Id: <1246591297.27828.165.camel@falcon> Mime-Version: 1.0 X-Mailer: Evolution 2.26.1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23637 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips On Fri, 2009-07-03 at 00:22 +0100, Ralf Baechle wrote: > On Tue, Jun 30, 2009 at 10:52:50PM +0800, Wu Zhangjin wrote: > > > From: Wu Zhangjin > > > > when using hibernation(STD) with CONFIG_FLATMEM in linux-mips-64bit, it > > fails for the current mips-specific hibernation implementation save the > > pages in all of the memory space(except the nosave section) and make > > there will be not enough memory left to the STD task itself, and then > > fail. in reality, we only need to save the pages in system rams. > > > > here is the reason why it fail: > > > > kernel/power/snapshot.c: > > > > static void mark_nosave_pages(struct memory_bitmap *bm) > > { > > ... > > if (pfn_valid(pfn)) { > > ... > > } > > } > > > > arch/mips/include/asm/page.h: > > > > ... > > #ifdef CONFIG_FLATMEM > > > > #define pfn_valid(pfn) ((pfn) >= ARCH_PFN_OFFSET && (pfn) < max_mapnr) > > > > #elif defined(CONFIG_SPARSEMEM) > > > > /* pfn_valid is defined in linux/mmzone.h */ > > ... > > > > we can rewrite pfn_valid(pfn) to fix this problem, but I really do not > > want to touch such a widely-used macro, so, I used another solution: > > > > static struct page *saveable_page(struct zone *zone, unsigned long pfn) > > { > > ... > > if ( .... pfn_is_nosave(pfn) > > return NULL; > > ... > > } > > > > and pfn_is_nosave is implemented in arch/mips/power/cpu.c, so, hacking > > this one is better. > > No - pfn_valid() is broken, so it should be fixed. Commit > 752fbeb2e3555c0d236e992f1195fd7ce30e728d introduced the breakage. It > seemed to assume that the valid range for PFNs doesn't start at 0 but > some higher number but got that entirely wrong.. > > #define ARCH_PFN_OFFSET PFN_UP(PHYS_OFFSET) > #define pfn_valid(pfn) ((pfn) >= ARCH_PFN_OFFSET && (pfn) < max_mapnr) > > works nicely when PHYS_OFFSET is 0 - as for most MIPS systems and goes > horribly wrong otherwise. So I suggest below patch. Just test it with the latest master branch of linux-mips on fulong2e, Your patch works well, thanks! (BTW: of course, the ide-relative bug is also there even with Bart's patch, so, currently, I just revert this part of the ide patch: "ide: improve handling of Power Management requests" to test your patch: diff --git a/drivers/ide/ide-io.c b/drivers/ide/ide-io.c index d5f3c77..8c4608c 100644 --- a/drivers/ide/ide-io.c +++ b/drivers/ide/ide-io.c @@ -468,12 +468,12 @@ void do_ide_request(struct request_queue *q) ide_hwif_t *prev_port; repeat: prev_port = hwif->host->cur_port; - +/* if (drive->dev_flags & IDE_DFLAG_BLOCKED) rq = hwif->rq; else WARN_ON_ONCE(hwif->rq); - +*/ if (drive->dev_flags & IDE_DFLAG_SLEEPING && time_after(drive->sleep, jiffies)) { ide_unlock_port(hwif); So, I will try to test Bart's patch with linux-next, I'm cloning it currently! perhaps there is something missing in my git repo or the linux-mips git repo? because i can not apply bart's patch neither to my git repo nor to the master branch of linux-mips git repo directly, even if pulled linux-next and Davie's ide-2.6 in. ) Regards, Wu Zhangjin > > Ralf > > Signed-off-by: Ralf Baechle > > arch/mips/include/asm/page.h | 9 ++++++++- > 1 files changed, 8 insertions(+), 1 deletions(-) > > diff --git a/arch/mips/include/asm/page.h b/arch/mips/include/asm/page.h > index dc0eaa7..96a14a4 100644 > --- a/arch/mips/include/asm/page.h > +++ b/arch/mips/include/asm/page.h > @@ -165,7 +165,14 @@ typedef struct { unsigned long pgprot; } pgprot_t; > > #ifdef CONFIG_FLATMEM > > -#define pfn_valid(pfn) ((pfn) >= ARCH_PFN_OFFSET && (pfn) < max_mapnr) > +#define pfn_valid(pfn) \ > +({ \ > + unsigned long __pfn = (pfn); \ > + /* avoid include hell */ \ > + extern unsigned long min_low_pfn; \ > + \ > + __pfn >= min_low_pfn && __pfn < max_mapnr; \ > +}) > > #elif defined(CONFIG_SPARSEMEM) > From wuzhangjin@gmail.com Fri Jul 3 06:04:37 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 03 Jul 2009 06:04:44 +0200 (CEST) Received: from rv-out-0708.google.com ([209.85.198.248]:14795 "EHLO rv-out-0708.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1491892AbZGCEEh (ORCPT ); Fri, 3 Jul 2009 06:04:37 +0200 Received: by rv-out-0708.google.com with SMTP id l33so714473rvb.24 for ; Thu, 02 Jul 2009 20:58:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:subject:from:reply-to:to:cc :in-reply-to:references:content-type:organization:date:message-id :mime-version:x-mailer:content-transfer-encoding; bh=5JQrIuiPR7qOlnvHZgHSCi0/94vjc1nbFsEAUrKRhps=; b=ATBTknHqQfRt1TZH+Qhjcx3Hmv+6cSSUizR7+j9/sGNLCkk/92G39RDZjrGYypi/gX 90pQmuTO0pmDLlgdM3aRtcn/XrzWzHgsbcWOjHFxp3YHzf0kTDnlBm39XHTk1canbixP +E7VvdsfwyiSFfxRhwHkspSWNmlN6TJS6d6hc= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=subject:from:reply-to:to:cc:in-reply-to:references:content-type :organization:date:message-id:mime-version:x-mailer :content-transfer-encoding; b=tlIn+hb/BemhIl5iS1JYjLXD+2SqsbzqOClTbUjzKcX0wo92nLOjlpDly0kJ878col uKUIGuQePrh5eYdOSNQwFj+Fah4hXzborJJoO42orgGpi3xEIoPCW49A+jbV7iJVgBt9 NAr6fEXBQ384IHug0PwG9VPqo6ny+gkEBBxKo= Received: by 10.140.141.16 with SMTP id o16mr845686rvd.9.1246593519224; Thu, 02 Jul 2009 20:58:39 -0700 (PDT) Received: from ?172.16.2.101? ([222.92.8.142]) by mx.google.com with ESMTPS id k37sm14056407rvb.8.2009.07.02.20.58.32 (version=TLSv1/SSLv3 cipher=RC4-MD5); Thu, 02 Jul 2009 20:58:37 -0700 (PDT) Subject: Re: [Bug #13663] suspend to ram regression (IDE related) From: Wu Zhangjin Reply-To: wuzhangjin@gmail.com To: Bartlomiej Zolnierkiewicz Cc: Jeff Chua , Etienne Basset , David Miller , rjw@sisk.pl, linux-kernel@vger.kernel.org, kernel-testers@vger.kernel.org, Ralf Baechle , linux-mips@linux-mips.org, linux-ide@vger.kernel.org In-Reply-To: <200907021813.57322.bzolnier@gmail.com> References: <200907011829.16850.bzolnier@gmail.com> <1246499203.9660.52.camel@falcon> <200907021813.57322.bzolnier@gmail.com> Content-Type: text/plain Organization: DSLab, Lanzhou University, China Date: Fri, 03 Jul 2009 11:58:25 +0800 Message-Id: <1246593505.27828.187.camel@falcon> Mime-Version: 1.0 X-Mailer: Evolution 2.26.1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23638 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips On Thu, 2009-07-02 at 18:13 +0200, Bartlomiej Zolnierkiewicz wrote: > On Thursday 02 July 2009 03:46:43 Wu Zhangjin wrote: > > On Wed, 2009-07-01 at 18:29 +0200, Bartlomiej Zolnierkiewicz wrote: > > > On Wednesday 01 July 2009 18:21:25 Bartlomiej Zolnierkiewicz wrote: > > > > On Wednesday 01 July 2009 16:47:41 Wu Zhangjin wrote: > > > > > On Wed, 2009-07-01 at 22:31 +0800, Jeff Chua wrote: > > > > > > On Tue, Jun 30, 2009 at 12:21 AM, Jeff Chua wrote: > > > > > > > > > > > > > I just tried, and it "seems" to work. Will try a few more cycles. > > > > > > > > > > > > STD/STR survived quite a few cycles now. Patch seems to be doing the > > > > > > right thing. > > > > > > > > > > > > On Mon, Jun 29, 2009 at 11:51 PM, Etienne > > > > > > Basset wrote: > > > > > > > > > > > > > To have STR/resume work with current git, I have to : > > > > > > > > > > > > > 1) apply Bart's patch > > > > > > > > > > > > This is not yet in Linus's tree. And much needed to really fix the problem. > > > > > > > > > > > > > 2) revert this commit : a1317f714af7aed60ddc182d0122477cbe36ee9b > > > > > > > > > > > > > > > > Yes, This commit must be reverted, otherwise, STD/Hibernation will not > > > > > work either. I have tested it on two different loongson-based machines: > > > > > fuloong2e box and yeeloong2f netbook.(loongson is mips compatiable) > > > > > > > > Since it seems like Dave is taking his sweet time with doing the revert > > > > I stared at the code a bit more and I think that I finally found the bug > > > > (thanks to your debugging work for giving me the right hint!). > > > > > > > > The patch needs to take into the account a new code introduced by the recent > > > > block layer changes (commit 8f6205cd572fece673da0255d74843680f67f879): > > > > > > > > @@ -555,8 +560,11 @@ repeat: > > > > startstop = start_request(drive, rq); > > > > spin_lock_irq(&hwif->lock); > > > > > > > > - if (startstop == ide_stopped) > > > > + if (startstop == ide_stopped) { > > > > + rq = hwif->rq; > > > > + hwif->rq = NULL; > > > > goto repeat; > > > > + } > > > > } else > > > > goto plug_device; > > > > out: > > > > > > > > and not zero hwif->rq if the device is blocked. > > > > > > > > Could you try the attached patch and see if it fixes the issue? > > > > > > Here is the more complete version, also taking into the account changes > > > in ide_intr() and ide_timer_expiry(): > > > > > > > Sorry, I can not apply this patch directly, which original version did > > you use? I used the one in the master branch of linux-mips development > > git repository. > > > > commit 5a4f13fad1ab5bd08dea78fc55321e429d83cddf > > Merge: ec9c45d e18ed14 > > Author: Linus Torvalds > > Date: Mon Jun 29 20:07:43 2009 -0700 > > > > Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/ide-2.6 > > > > * git://git.kernel.org/pub/scm/linux/kernel/git/davem/ide-2.6: > > ide: memory overrun in ide_get_identity_ioctl() on big endian > > machines using ioctl HDIO_OBSOLETE_IDENTITY > > ide: fix resume for CONFIG_BLK_DEV_IDEACPI=y > > ide-cd: handle fragmented packet commands gracefully > > ide: always kill the whole request on error > > ide: fix ide_kill_rq() for special ide-{floppy,tape} driver > > requests > > > > it this too old? should i merge another git repository? > > Weird, I used linux-next but Linus' tree should also be fine > (as it matches linux-next w.r.t. ide currently). I just cloned the linux-next git repo, and tested your patch with STD/Hibernation, unfortunately, it also not work :-( here is the Call Trace: blk_delete_timer+0x0/0x20 blk_requeue_request+0x24/0xd0 ide_requeue_and_plug+0x38/0xb0 ide_intr+0x120/0x300 ---> ide_intr.... handle_IRQ_event+0x94/0x230 handle_level_irq+0x7c/0x120 mach_irq_dispatch+0xc8/0x158 ret_from_irq+0x0/0x4 cpu_idle+0x30/0x60 start_kernel+0x330/0x34c If _NOT_ apply your patch and comment this part, it works: diff --git a/drivers/ide/ide-io.c b/drivers/ide/ide-io.c index d5f3c77..a45de2b 100644 --- a/drivers/ide/ide-io.c +++ b/drivers/ide/ide-io.c @@ -468,12 +468,12 @@ void do_ide_request(struct request_queue *q) ide_hwif_t *prev_port; repeat: prev_port = hwif->host->cur_port; - +/* if (drive->dev_flags & IDE_DFLAG_BLOCKED) rq = hwif->rq; else WARN_ON_ONCE(hwif->rq); - +*/ if (drive->dev_flags & IDE_DFLAG_SLEEPING && time_after(drive->sleep, jiffies)) { ide_unlock_port(hwif); Regards, Wu Zhangjin > > Anyway since the patch was confirmed to fix the problem by > Jeff and Etienne here is the final version for Dave. > > From: Bartlomiej Zolnierkiewicz > Subject: [PATCH] ide: make resume work again > > It turns out that commit a1317f714af7aed60ddc182d0122477cbe36ee9b > ("ide: improve handling of Power Management requests") needs to take > into the account a new code added by the recent block layer changes > in commit 8f6205cd572fece673da0255d74843680f67f879 ("ide: dequeue > in-flight request") and prevent clearing of hwif->rq if the device > is blocked. > > Thanks to Etienne, Wu and Jeff for help in fixing the issue. > > Reported-and-tested-by: Jeff Chua > Reported-and-tested-by: Etienne Basset > Reported-by: Wu Zhangjin > Signed-off-by: Bartlomiej Zolnierkiewicz > --- > Added patch description, no other changes. > > drivers/ide/ide-io.c | 15 ++++++++++----- > 1 file changed, 10 insertions(+), 5 deletions(-) > > Index: b/drivers/ide/ide-io.c > =================================================================== > --- a/drivers/ide/ide-io.c > +++ b/drivers/ide/ide-io.c > @@ -532,7 +532,8 @@ repeat: > > if (startstop == ide_stopped) { > rq = hwif->rq; > - hwif->rq = NULL; > + if ((drive->dev_flags & IDE_DFLAG_BLOCKED) == 0) > + hwif->rq = NULL; > goto repeat; > } > } else > @@ -679,8 +680,10 @@ void ide_timer_expiry (unsigned long dat > spin_lock_irq(&hwif->lock); > enable_irq(hwif->irq); > if (startstop == ide_stopped && hwif->polling == 0) { > - rq_in_flight = hwif->rq; > - hwif->rq = NULL; > + if ((drive->dev_flags & IDE_DFLAG_BLOCKED) == 0) { > + rq_in_flight = hwif->rq; > + hwif->rq = NULL; > + } > ide_unlock_port(hwif); > plug_device = 1; > } > @@ -856,8 +859,10 @@ irqreturn_t ide_intr (int irq, void *dev > */ > if (startstop == ide_stopped && hwif->polling == 0) { > BUG_ON(hwif->handler); > - rq_in_flight = hwif->rq; > - hwif->rq = NULL; > + if ((drive->dev_flags & IDE_DFLAG_BLOCKED) == 0) { > + rq_in_flight = hwif->rq; > + hwif->rq = NULL; > + } > ide_unlock_port(hwif); > plug_device = 1; > } > -- > To unsubscribe from this list: send the line "unsubscribe linux-ide" in > the body of a message to majordomo@vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html From wuzhangjin@gmail.com Fri Jul 3 06:11:19 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 03 Jul 2009 06:11:27 +0200 (CEST) Received: from wa-out-1112.google.com ([209.85.146.183]:35212 "EHLO wa-out-1112.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1491882AbZGCELT (ORCPT ); Fri, 3 Jul 2009 06:11:19 +0200 Received: by wa-out-1112.google.com with SMTP id n4so395397wag.0 for ; Thu, 02 Jul 2009 21:05:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:subject:from:reply-to:to:cc :in-reply-to:references:content-type:organization:date:message-id :mime-version:x-mailer:content-transfer-encoding; bh=mAjDatM+/Kk0Y2fluusm4cNIgeFzLzJ7jgaoItnN3pA=; b=FinuFO+O2gnWIBrCsWM6UhF7Y3xjMf5fccyLv/knJfQbjqL6AY9IN1p8Kg8gT4kVBJ f0whAkdLaS/+vBCIMjsS6owkI48appVSguwCliiFBLG8WP++A8PWlCEv+K/Hjh9ypIii fdMZfpja4bXO4Tkif7Jyhx20YNA4Hzh1Ai778= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=subject:from:reply-to:to:cc:in-reply-to:references:content-type :organization:date:message-id:mime-version:x-mailer :content-transfer-encoding; b=k7FT2dyi8r1bDli+k+KdJNyENb0Jnvz+lIV0tH0JzTi37z+C131+HKVJSYRTFY5NqW qHnbhj9vv8fwgXJwXLMOCESlWbgm7gh6j3e0Xt+dT/UN7DYEMS2Z6yGk99Gd46YxZL2f N1WdBcRMf7LQIfxXb8vI9u8trDV82gikek/CE= Received: by 10.114.161.11 with SMTP id j11mr1231672wae.193.1246593923357; Thu, 02 Jul 2009 21:05:23 -0700 (PDT) Received: from ?172.16.2.101? ([222.92.8.142]) by mx.google.com with ESMTPS id l38sm5432479waf.61.2009.07.02.21.05.19 (version=TLSv1/SSLv3 cipher=RC4-MD5); Thu, 02 Jul 2009 21:05:22 -0700 (PDT) Subject: Re: [PATCH] [MIPS] Hibernation: only save pages in system ram From: Wu Zhangjin Reply-To: wuzhangjin@gmail.com To: Ralf Baechle Cc: LKML , linux-mips@linux-mips.org, Pavel Machek , "Rafael J. Wysocki" , Bartlomiej Zolnierkiewicz In-Reply-To: <1246591297.27828.165.camel@falcon> References: <1246373570-21090-1-git-send-email-wuzhangjin@gmail.com> <20090702232205.GE14804@linux-mips.org> <1246591297.27828.165.camel@falcon> Content-Type: text/plain Organization: DSLab, Lanzhou University, China Date: Fri, 03 Jul 2009 12:05:09 +0800 Message-Id: <1246593909.27828.193.camel@falcon> Mime-Version: 1.0 X-Mailer: Evolution 2.26.1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23639 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips On Fri, 2009-07-03 at 11:21 +0800, Wu Zhangjin wrote: > On Fri, 2009-07-03 at 00:22 +0100, Ralf Baechle wrote: > > On Tue, Jun 30, 2009 at 10:52:50PM +0800, Wu Zhangjin wrote: > > > > > From: Wu Zhangjin > > > > > > when using hibernation(STD) with CONFIG_FLATMEM in linux-mips-64bit, it > > > fails for the current mips-specific hibernation implementation save the > > > pages in all of the memory space(except the nosave section) and make > > > there will be not enough memory left to the STD task itself, and then > > > fail. in reality, we only need to save the pages in system rams. > > > > > > here is the reason why it fail: > > > > > > kernel/power/snapshot.c: > > > > > > static void mark_nosave_pages(struct memory_bitmap *bm) > > > { > > > ... > > > if (pfn_valid(pfn)) { > > > ... > > > } > > > } > > > > > > arch/mips/include/asm/page.h: > > > > > > ... > > > #ifdef CONFIG_FLATMEM > > > > > > #define pfn_valid(pfn) ((pfn) >= ARCH_PFN_OFFSET && (pfn) < max_mapnr) > > > > > > #elif defined(CONFIG_SPARSEMEM) > > > > > > /* pfn_valid is defined in linux/mmzone.h */ > > > ... > > > > > > we can rewrite pfn_valid(pfn) to fix this problem, but I really do not > > > want to touch such a widely-used macro, so, I used another solution: > > > > > > static struct page *saveable_page(struct zone *zone, unsigned long pfn) > > > { > > > ... > > > if ( .... pfn_is_nosave(pfn) > > > return NULL; > > > ... > > > } > > > > > > and pfn_is_nosave is implemented in arch/mips/power/cpu.c, so, hacking > > > this one is better. > > > > No - pfn_valid() is broken, so it should be fixed. Commit > > 752fbeb2e3555c0d236e992f1195fd7ce30e728d introduced the breakage. It > > seemed to assume that the valid range for PFNs doesn't start at 0 but > > some higher number but got that entirely wrong.. > > > > #define ARCH_PFN_OFFSET PFN_UP(PHYS_OFFSET) > > #define pfn_valid(pfn) ((pfn) >= ARCH_PFN_OFFSET && (pfn) < max_mapnr) > > > > works nicely when PHYS_OFFSET is 0 - as for most MIPS systems and goes > > horribly wrong otherwise. So I suggest below patch. > > Just test it with the latest master branch of linux-mips on fulong2e, > Your patch works well, thanks! > > (BTW: of course, the ide-relative bug is also there even with Bart's > patch, so, currently, I just revert this part of the ide patch: "ide: > improve handling of Power Management requests" to test your patch: > > diff --git a/drivers/ide/ide-io.c b/drivers/ide/ide-io.c > index d5f3c77..8c4608c 100644 > --- a/drivers/ide/ide-io.c > +++ b/drivers/ide/ide-io.c > @@ -468,12 +468,12 @@ void do_ide_request(struct request_queue *q) > ide_hwif_t *prev_port; > repeat: > prev_port = hwif->host->cur_port; > - > +/* > if (drive->dev_flags & IDE_DFLAG_BLOCKED) > rq = hwif->rq; > else > WARN_ON_ONCE(hwif->rq); > - > +*/ > if (drive->dev_flags & IDE_DFLAG_SLEEPING && > time_after(drive->sleep, jiffies)) { > ide_unlock_port(hwif); > > So, I will try to test Bart's patch with linux-next, I'm cloning it > currently! perhaps there is something missing in my git repo or the > linux-mips git repo? because i can not apply bart's patch neither to > git repo nor to the master branch of linux-mips git repo directly, even > if pulled linux-next and Davie's ide-2.6 in. Sorry, I have missed something in Bart's patch, Can apply it now, so please ignore the above complaint. but unfortunately, Bart's patch also not fix the problem of STD, I have reported my test result in another E-mail thread: "[Bug #13663] suspend to ram regression (IDE related)", so, please ignore this thread, thanks! Regards, Wu Zhangjin > ) > > Regards, > Wu Zhangjin > > > > > Ralf > > > > Signed-off-by: Ralf Baechle > > > > arch/mips/include/asm/page.h | 9 ++++++++- > > 1 files changed, 8 insertions(+), 1 deletions(-) > > > > diff --git a/arch/mips/include/asm/page.h b/arch/mips/include/asm/page.h > > index dc0eaa7..96a14a4 100644 > > --- a/arch/mips/include/asm/page.h > > +++ b/arch/mips/include/asm/page.h > > @@ -165,7 +165,14 @@ typedef struct { unsigned long pgprot; } pgprot_t; > > > > #ifdef CONFIG_FLATMEM > > > > -#define pfn_valid(pfn) ((pfn) >= ARCH_PFN_OFFSET && (pfn) < max_mapnr) > > +#define pfn_valid(pfn) \ > > +({ \ > > + unsigned long __pfn = (pfn); \ > > + /* avoid include hell */ \ > > + extern unsigned long min_low_pfn; \ > > + \ > > + __pfn >= min_low_pfn && __pfn < max_mapnr; \ > > +}) > > > > #elif defined(CONFIG_SPARSEMEM) > > From wuzhangjin@gmail.com Fri Jul 3 06:13:14 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 03 Jul 2009 06:13:21 +0200 (CEST) Received: from mail-px0-f188.google.com ([209.85.216.188]:43312 "EHLO mail-px0-f188.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1491882AbZGCENO (ORCPT ); Fri, 3 Jul 2009 06:13:14 +0200 Received: by pxi26 with SMTP id 26so1949413pxi.22 for ; Thu, 02 Jul 2009 21:07:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:subject:from:reply-to:to:cc :in-reply-to:references:content-type:organization:date:message-id :mime-version:x-mailer:content-transfer-encoding; bh=8qWjJ3FxRWnO1V9cydznkQje60d67PGRWfZfXzx5SP0=; b=MTU3pHu5NtDiMTnFP/DP9YUCdtQusF4rKlIDcGLCA8y2kTSfMxEzabTVDv2adTY9n9 siWGYuwE7/ODX9NftJXN3An6q+FKpzzoAHx5TtZF0oZIHuv+qXLcmABmZg61P5AmN0ID ++dHW1na6Vo/VKTPqj8JLdW7tEV4u4m7Zt5oM= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=subject:from:reply-to:to:cc:in-reply-to:references:content-type :organization:date:message-id:mime-version:x-mailer :content-transfer-encoding; b=TSmyLBbiZ0HziyPLbE0YHo5sA6rd9CwwjgpUs4rEvs1XCJmwNa5f118ee5eXt9mCcb JclwlHRYcCwjnjM7bGZybswF6F8+JmkVWiiOZlERyBmKwstvpeyRCG0t4sftSkNarXMz AzP4FQ++GAga639RXwJi1sG/Uek6CVk6i/+l0= Received: by 10.115.46.10 with SMTP id y10mr1267974waj.61.1246594032911; Thu, 02 Jul 2009 21:07:12 -0700 (PDT) Received: from ?172.16.2.101? ([222.92.8.142]) by mx.google.com with ESMTPS id v39sm5472847wah.27.2009.07.02.21.07.06 (version=TLSv1/SSLv3 cipher=RC4-MD5); Thu, 02 Jul 2009 21:07:12 -0700 (PDT) Subject: Re: [Bug #13663] suspend to ram regression (IDE related) From: Wu Zhangjin Reply-To: wuzhangjin@gmail.com To: Bartlomiej Zolnierkiewicz Cc: Jeff Chua , Etienne Basset , David Miller , rjw@sisk.pl, linux-kernel@vger.kernel.org, kernel-testers@vger.kernel.org, Ralf Baechle , linux-mips@linux-mips.org, linux-ide@vger.kernel.org In-Reply-To: <1246593505.27828.187.camel@falcon> References: <200907011829.16850.bzolnier@gmail.com> <1246499203.9660.52.camel@falcon> <200907021813.57322.bzolnier@gmail.com> <1246593505.27828.187.camel@falcon> Content-Type: text/plain Organization: DSLab, Lanzhou University, China Date: Fri, 03 Jul 2009 12:06:57 +0800 Message-Id: <1246594017.27828.195.camel@falcon> Mime-Version: 1.0 X-Mailer: Evolution 2.26.1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23640 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips On Fri, 2009-07-03 at 11:58 +0800, Wu Zhangjin wrote: > On Thu, 2009-07-02 at 18:13 +0200, Bartlomiej Zolnierkiewicz wrote: > > On Thursday 02 July 2009 03:46:43 Wu Zhangjin wrote: > > > On Wed, 2009-07-01 at 18:29 +0200, Bartlomiej Zolnierkiewicz wrote: > > > > On Wednesday 01 July 2009 18:21:25 Bartlomiej Zolnierkiewicz wrote: > > > > > On Wednesday 01 July 2009 16:47:41 Wu Zhangjin wrote: > > > > > > On Wed, 2009-07-01 at 22:31 +0800, Jeff Chua wrote: > > > > > > > On Tue, Jun 30, 2009 at 12:21 AM, Jeff Chua wrote: > > > > > > > > > > > > > > > I just tried, and it "seems" to work. Will try a few more cycles. > > > > > > > > > > > > > > STD/STR survived quite a few cycles now. Patch seems to be doing the > > > > > > > right thing. > > > > > > > > > > > > > > On Mon, Jun 29, 2009 at 11:51 PM, Etienne > > > > > > > Basset wrote: > > > > > > > > > > > > > > > To have STR/resume work with current git, I have to : > > > > > > > > > > > > > > > 1) apply Bart's patch > > > > > > > > > > > > > > This is not yet in Linus's tree. And much needed to really fix the problem. > > > > > > > > > > > > > > > 2) revert this commit : a1317f714af7aed60ddc182d0122477cbe36ee9b > > > > > > > > > > > > > > > > > > > Yes, This commit must be reverted, otherwise, STD/Hibernation will not > > > > > > work either. I have tested it on two different loongson-based machines: > > > > > > fuloong2e box and yeeloong2f netbook.(loongson is mips compatiable) > > > > > > > > > > Since it seems like Dave is taking his sweet time with doing the revert > > > > > I stared at the code a bit more and I think that I finally found the bug > > > > > (thanks to your debugging work for giving me the right hint!). > > > > > > > > > > The patch needs to take into the account a new code introduced by the recent > > > > > block layer changes (commit 8f6205cd572fece673da0255d74843680f67f879): > > > > > > > > > > @@ -555,8 +560,11 @@ repeat: > > > > > startstop = start_request(drive, rq); > > > > > spin_lock_irq(&hwif->lock); > > > > > > > > > > - if (startstop == ide_stopped) > > > > > + if (startstop == ide_stopped) { > > > > > + rq = hwif->rq; > > > > > + hwif->rq = NULL; > > > > > goto repeat; > > > > > + } > > > > > } else > > > > > goto plug_device; > > > > > out: > > > > > > > > > > and not zero hwif->rq if the device is blocked. > > > > > > > > > > Could you try the attached patch and see if it fixes the issue? > > > > > > > > Here is the more complete version, also taking into the account changes > > > > in ide_intr() and ide_timer_expiry(): > > > > > > > > > > Sorry, I can not apply this patch directly, which original version did > > > you use? I used the one in the master branch of linux-mips development > > > git repository. > > > > > > commit 5a4f13fad1ab5bd08dea78fc55321e429d83cddf > > > Merge: ec9c45d e18ed14 > > > Author: Linus Torvalds > > > Date: Mon Jun 29 20:07:43 2009 -0700 > > > > > > Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/ide-2.6 > > > > > > * git://git.kernel.org/pub/scm/linux/kernel/git/davem/ide-2.6: > > > ide: memory overrun in ide_get_identity_ioctl() on big endian > > > machines using ioctl HDIO_OBSOLETE_IDENTITY > > > ide: fix resume for CONFIG_BLK_DEV_IDEACPI=y > > > ide-cd: handle fragmented packet commands gracefully > > > ide: always kill the whole request on error > > > ide: fix ide_kill_rq() for special ide-{floppy,tape} driver > > > requests > > > > > > it this too old? should i merge another git repository? > > > > Weird, I used linux-next but Linus' tree should also be fine > > (as it matches linux-next w.r.t. ide currently). > > I just cloned the linux-next git repo, and tested your patch with > STD/Hibernation, unfortunately, it also not work :-( > > here is the Call Trace: > > blk_delete_timer+0x0/0x20 > blk_requeue_request+0x24/0xd0 > ide_requeue_and_plug+0x38/0xb0 > ide_intr+0x120/0x300 ---> ide_intr.... > handle_IRQ_event+0x94/0x230 > handle_level_irq+0x7c/0x120 > mach_irq_dispatch+0xc8/0x158 > ret_from_irq+0x0/0x4 > cpu_idle+0x30/0x60 > start_kernel+0x330/0x34c > There are two more lines after the Call Trace: Disabling lock debugging due to kernel taint Kernel panic - not syncing: Fatal exception in interrupt. > If _NOT_ apply your patch and comment this part, it works: > > diff --git a/drivers/ide/ide-io.c b/drivers/ide/ide-io.c > index d5f3c77..a45de2b 100644 > --- a/drivers/ide/ide-io.c > +++ b/drivers/ide/ide-io.c > @@ -468,12 +468,12 @@ void do_ide_request(struct request_queue *q) > ide_hwif_t *prev_port; > repeat: > prev_port = hwif->host->cur_port; > - > +/* > if (drive->dev_flags & IDE_DFLAG_BLOCKED) > rq = hwif->rq; > else > WARN_ON_ONCE(hwif->rq); > - > +*/ > if (drive->dev_flags & IDE_DFLAG_SLEEPING && > time_after(drive->sleep, jiffies)) { > ide_unlock_port(hwif); > > > Regards, > Wu Zhangjin > > > > Anyway since the patch was confirmed to fix the problem by > > Jeff and Etienne here is the final version for Dave. > > > > From: Bartlomiej Zolnierkiewicz > > Subject: [PATCH] ide: make resume work again > > > > It turns out that commit a1317f714af7aed60ddc182d0122477cbe36ee9b > > ("ide: improve handling of Power Management requests") needs to take > > into the account a new code added by the recent block layer changes > > in commit 8f6205cd572fece673da0255d74843680f67f879 ("ide: dequeue > > in-flight request") and prevent clearing of hwif->rq if the device > > is blocked. > > > > Thanks to Etienne, Wu and Jeff for help in fixing the issue. > > > > Reported-and-tested-by: Jeff Chua > > Reported-and-tested-by: Etienne Basset > > Reported-by: Wu Zhangjin > > Signed-off-by: Bartlomiej Zolnierkiewicz > > --- > > Added patch description, no other changes. > > > > drivers/ide/ide-io.c | 15 ++++++++++----- > > 1 file changed, 10 insertions(+), 5 deletions(-) > > > > Index: b/drivers/ide/ide-io.c > > =================================================================== > > --- a/drivers/ide/ide-io.c > > +++ b/drivers/ide/ide-io.c > > @@ -532,7 +532,8 @@ repeat: > > > > if (startstop == ide_stopped) { > > rq = hwif->rq; > > - hwif->rq = NULL; > > + if ((drive->dev_flags & IDE_DFLAG_BLOCKED) == 0) > > + hwif->rq = NULL; > > goto repeat; > > } > > } else > > @@ -679,8 +680,10 @@ void ide_timer_expiry (unsigned long dat > > spin_lock_irq(&hwif->lock); > > enable_irq(hwif->irq); > > if (startstop == ide_stopped && hwif->polling == 0) { > > - rq_in_flight = hwif->rq; > > - hwif->rq = NULL; > > + if ((drive->dev_flags & IDE_DFLAG_BLOCKED) == 0) { > > + rq_in_flight = hwif->rq; > > + hwif->rq = NULL; > > + } > > ide_unlock_port(hwif); > > plug_device = 1; > > } > > @@ -856,8 +859,10 @@ irqreturn_t ide_intr (int irq, void *dev > > */ > > if (startstop == ide_stopped && hwif->polling == 0) { > > BUG_ON(hwif->handler); > > - rq_in_flight = hwif->rq; > > - hwif->rq = NULL; > > + if ((drive->dev_flags & IDE_DFLAG_BLOCKED) == 0) { > > + rq_in_flight = hwif->rq; > > + hwif->rq = NULL; > > + } > > ide_unlock_port(hwif); > > plug_device = 1; > > } > > -- > > To unsubscribe from this list: send the line "unsubscribe linux-ide" in > > the body of a message to majordomo@vger.kernel.org > > More majordomo info at http://vger.kernel.org/majordomo-info.html From bzolnier@gmail.com Fri Jul 3 15:08:47 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 03 Jul 2009 15:08:55 +0200 (CEST) Received: from mail-fx0-f212.google.com ([209.85.220.212]:64170 "EHLO mail-fx0-f212.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492285AbZGCNIr (ORCPT ); Fri, 3 Jul 2009 15:08:47 +0200 Received: by fxm8 with SMTP id 8so1844880fxm.0 for ; Fri, 03 Jul 2009 06:02:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:subject:date :user-agent:cc:references:in-reply-to:mime-version:content-type :content-transfer-encoding:content-disposition:message-id; bh=WNbbOQM+BLVCVyxRpD+1/8ZlOmiUKRQZNoAao2WzXSg=; b=dAXV7zolHGUNejeV8uO25tlIob4PJSKis7xaDLFEtIlidmhfWHSU/ctdBd+TYU3z7W T7+Es9J2xnUSDNf0UZ8dYW2btGo9t6moyIAxFxoy9Yrix0z1OLjB4vLK5xosXhPjSx2Y pJSa4X52bD7gHcwfT1ijh4ion8pULZF5Ti7Qc= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:subject:date:user-agent:cc:references:in-reply-to :mime-version:content-type:content-transfer-encoding :content-disposition:message-id; b=vKUAWfwZXMQ7xJBewnDRxvfPE7Hh8Tf5UvxOhnNjOaRNqwTvwo/W7wceC3VKiICbNA a2Q0U9GC8AZzDdT1gDH6FkKC/93l0p4JS+4tn9jqkMgowXgr5EVVWsWHTNez7I4FO4B3 bn7yotTA6ELpX4jPAM+b6Zt9gU2Z/63QR9o+c= Received: by 10.103.225.11 with SMTP id c11mr776732mur.98.1246626160997; Fri, 03 Jul 2009 06:02:40 -0700 (PDT) Received: from localhost.localdomain (chello089077034197.chello.pl [89.77.34.197]) by mx.google.com with ESMTPS id 12sm17514995muq.23.2009.07.03.06.02.39 (version=TLSv1/SSLv3 cipher=RC4-MD5); Fri, 03 Jul 2009 06:02:39 -0700 (PDT) From: Bartlomiej Zolnierkiewicz To: wuzhangjin@gmail.com Subject: Re: [Bug #13663] suspend to ram regression (IDE related) Date: Fri, 3 Jul 2009 15:08:45 +0200 User-Agent: KMail/1.11.4 (Linux/2.6.31-rc1-next-20090703-03460-gb01c1b8; KDE/4.2.4; i686; ; ) Cc: Jeff Chua , Etienne Basset , David Miller , rjw@sisk.pl, linux-kernel@vger.kernel.org, kernel-testers@vger.kernel.org, Ralf Baechle , linux-mips@linux-mips.org, linux-ide@vger.kernel.org References: <200907021813.57322.bzolnier@gmail.com> <1246593505.27828.187.camel@falcon> In-Reply-To: <1246593505.27828.187.camel@falcon> MIME-Version: 1.0 Content-Type: Text/Plain; charset="iso-8859-15" Content-Transfer-Encoding: 7bit Content-Disposition: inline Message-Id: <200907031508.47891.bzolnier@gmail.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23641 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: bzolnier@gmail.com Precedence: bulk X-list: linux-mips On Friday 03 July 2009 05:58:25 Wu Zhangjin wrote: > On Thu, 2009-07-02 at 18:13 +0200, Bartlomiej Zolnierkiewicz wrote: > > On Thursday 02 July 2009 03:46:43 Wu Zhangjin wrote: > > > On Wed, 2009-07-01 at 18:29 +0200, Bartlomiej Zolnierkiewicz wrote: > > > > On Wednesday 01 July 2009 18:21:25 Bartlomiej Zolnierkiewicz wrote: > > > > > On Wednesday 01 July 2009 16:47:41 Wu Zhangjin wrote: > > > > > > On Wed, 2009-07-01 at 22:31 +0800, Jeff Chua wrote: > > > > > > > On Tue, Jun 30, 2009 at 12:21 AM, Jeff Chua wrote: > > > > > > > > > > > > > > > I just tried, and it "seems" to work. Will try a few more cycles. > > > > > > > > > > > > > > STD/STR survived quite a few cycles now. Patch seems to be doing the > > > > > > > right thing. > > > > > > > > > > > > > > On Mon, Jun 29, 2009 at 11:51 PM, Etienne > > > > > > > Basset wrote: > > > > > > > > > > > > > > > To have STR/resume work with current git, I have to : > > > > > > > > > > > > > > > 1) apply Bart's patch > > > > > > > > > > > > > > This is not yet in Linus's tree. And much needed to really fix the problem. > > > > > > > > > > > > > > > 2) revert this commit : a1317f714af7aed60ddc182d0122477cbe36ee9b > > > > > > > > > > > > > > > > > > > Yes, This commit must be reverted, otherwise, STD/Hibernation will not > > > > > > work either. I have tested it on two different loongson-based machines: > > > > > > fuloong2e box and yeeloong2f netbook.(loongson is mips compatiable) > > > > > > > > > > Since it seems like Dave is taking his sweet time with doing the revert > > > > > I stared at the code a bit more and I think that I finally found the bug > > > > > (thanks to your debugging work for giving me the right hint!). > > > > > > > > > > The patch needs to take into the account a new code introduced by the recent > > > > > block layer changes (commit 8f6205cd572fece673da0255d74843680f67f879): > > > > > > > > > > @@ -555,8 +560,11 @@ repeat: > > > > > startstop = start_request(drive, rq); > > > > > spin_lock_irq(&hwif->lock); > > > > > > > > > > - if (startstop == ide_stopped) > > > > > + if (startstop == ide_stopped) { > > > > > + rq = hwif->rq; > > > > > + hwif->rq = NULL; > > > > > goto repeat; > > > > > + } > > > > > } else > > > > > goto plug_device; > > > > > out: > > > > > > > > > > and not zero hwif->rq if the device is blocked. > > > > > > > > > > Could you try the attached patch and see if it fixes the issue? > > > > > > > > Here is the more complete version, also taking into the account changes > > > > in ide_intr() and ide_timer_expiry(): > > > > > > > > > > Sorry, I can not apply this patch directly, which original version did > > > you use? I used the one in the master branch of linux-mips development > > > git repository. > > > > > > commit 5a4f13fad1ab5bd08dea78fc55321e429d83cddf > > > Merge: ec9c45d e18ed14 > > > Author: Linus Torvalds > > > Date: Mon Jun 29 20:07:43 2009 -0700 > > > > > > Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/ide-2.6 > > > > > > * git://git.kernel.org/pub/scm/linux/kernel/git/davem/ide-2.6: > > > ide: memory overrun in ide_get_identity_ioctl() on big endian > > > machines using ioctl HDIO_OBSOLETE_IDENTITY > > > ide: fix resume for CONFIG_BLK_DEV_IDEACPI=y > > > ide-cd: handle fragmented packet commands gracefully > > > ide: always kill the whole request on error > > > ide: fix ide_kill_rq() for special ide-{floppy,tape} driver > > > requests > > > > > > it this too old? should i merge another git repository? > > > > Weird, I used linux-next but Linus' tree should also be fine > > (as it matches linux-next w.r.t. ide currently). > > I just cloned the linux-next git repo, and tested your patch with > STD/Hibernation, unfortunately, it also not work :-( > > here is the Call Trace: > > blk_delete_timer+0x0/0x20 > blk_requeue_request+0x24/0xd0 > ide_requeue_and_plug+0x38/0xb0 > ide_intr+0x120/0x300 ---> ide_intr.... > handle_IRQ_event+0x94/0x230 > handle_level_irq+0x7c/0x120 > mach_irq_dispatch+0xc8/0x158 > ret_from_irq+0x0/0x4 > cpu_idle+0x30/0x60 > start_kernel+0x330/0x34c > > If _NOT_ apply your patch and comment this part, it works: OK, I see another gotcha added by recent changes, we need to explicitly initialize rq_in_flight variables now. Revised patch below.. From: Bartlomiej Zolnierkiewicz Subject: [PATCH] ide: make resume work again (for real) It turns out that commit a1317f714af7aed60ddc182d0122477cbe36ee9b ("ide: improve handling of Power Management requests") needs to take into the account a new code added by the recent block layer changes in commit 8f6205cd572fece673da0255d74843680f67f879 ("ide: dequeue in-flight request") and prevent clearing of hwif->rq if the device is blocked. Thanks to Etienne, Wu and Jeff for help in fixing the issue. Reported-and-tested-by: Jeff Chua Reported-and-tested-by: Etienne Basset Reported-by: Wu Zhangjin Signed-off-by: Bartlomiej Zolnierkiewicz --- Added patch description, no other changes. drivers/ide/ide-io.c | 19 ++++++++++++------- 1 file changed, 12 insertions(+), 7 deletions(-) Index: b/drivers/ide/ide-io.c =================================================================== --- a/drivers/ide/ide-io.c +++ b/drivers/ide/ide-io.c @@ -532,7 +532,8 @@ repeat: if (startstop == ide_stopped) { rq = hwif->rq; - hwif->rq = NULL; + if ((drive->dev_flags & IDE_DFLAG_BLOCKED) == 0) + hwif->rq = NULL; goto repeat; } } else @@ -616,7 +617,7 @@ void ide_timer_expiry (unsigned long dat unsigned long flags; int wait = -1; int plug_device = 0; - struct request *uninitialized_var(rq_in_flight); + struct request *rq_in_flight = NULL; spin_lock_irqsave(&hwif->lock, flags); @@ -679,8 +680,10 @@ void ide_timer_expiry (unsigned long dat spin_lock_irq(&hwif->lock); enable_irq(hwif->irq); if (startstop == ide_stopped && hwif->polling == 0) { - rq_in_flight = hwif->rq; - hwif->rq = NULL; + if ((drive->dev_flags & IDE_DFLAG_BLOCKED) == 0) { + rq_in_flight = hwif->rq; + hwif->rq = NULL; + } ide_unlock_port(hwif); plug_device = 1; } @@ -775,7 +778,7 @@ irqreturn_t ide_intr (int irq, void *dev ide_startstop_t startstop; irqreturn_t irq_ret = IRQ_NONE; int plug_device = 0; - struct request *uninitialized_var(rq_in_flight); + struct request *rq_in_flight = NULL; if (host->host_flags & IDE_HFLAG_SERIALIZE) { if (hwif != host->cur_port) @@ -856,8 +859,10 @@ irqreturn_t ide_intr (int irq, void *dev */ if (startstop == ide_stopped && hwif->polling == 0) { BUG_ON(hwif->handler); - rq_in_flight = hwif->rq; - hwif->rq = NULL; + if ((drive->dev_flags & IDE_DFLAG_BLOCKED) == 0) { + rq_in_flight = hwif->rq; + hwif->rq = NULL; + } ide_unlock_port(hwif); plug_device = 1; } From wuzhangjin@gmail.com Fri Jul 3 17:38:05 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 03 Jul 2009 17:38:12 +0200 (CEST) Received: from mail-pz0-f173.google.com ([209.85.222.173]:45446 "EHLO mail-pz0-f173.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492461AbZGCPiE (ORCPT ); Fri, 3 Jul 2009 17:38:04 +0200 Received: by pzk3 with SMTP id 3so2280664pzk.22 for ; Fri, 03 Jul 2009 08:31:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:subject:from:reply-to:to:cc :in-reply-to:references:content-type:organization:date:message-id :mime-version:x-mailer:content-transfer-encoding; bh=QQ1x5vDF/dcdQbAW8QxH3eho7gvFJ/j3ZoqZAUmzov8=; b=pOQxssZ6Chc5mXRACD52jOsc62J6phIkUS/72rN40KCN+juxPNNAhzIg1DGO+FMs7p 9L0i7xjaHnHJOnJPB/vOFMTkZC8mzqQIbA8kqbk6WcDk3PLz5l4avYiAFrvXNWcaW/2k 83HvCubG7dp9s2W/wia3fo6H2cSeVLDbbMpxU= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=subject:from:reply-to:to:cc:in-reply-to:references:content-type :organization:date:message-id:mime-version:x-mailer :content-transfer-encoding; b=O8woN5XdJfuG7TqNKL8prIEeXQ+jARDQLzIaSC2+WeVfMMSe69sjllPlBYdwg6nThj MrFclc5LEBBmETMfcQtVwxP3AThKL4XTRHanSKGQSKX1jASj6tJJQR6UhzlTMsWymLxa vPPNtZdoyZVo+o2TdqBYTmQltTs3iRt6drPTo= Received: by 10.142.148.9 with SMTP id v9mr531120wfd.148.1246635115121; Fri, 03 Jul 2009 08:31:55 -0700 (PDT) Received: from ?172.16.2.101? ([222.92.8.142]) by mx.google.com with ESMTPS id 29sm11259947wfg.21.2009.07.03.08.31.50 (version=TLSv1/SSLv3 cipher=RC4-MD5); Fri, 03 Jul 2009 08:31:53 -0700 (PDT) Subject: Re: [Bug #13663] suspend to ram regression (IDE related) From: Wu Zhangjin Reply-To: wuzhangjin@gmail.com To: Bartlomiej Zolnierkiewicz Cc: Jeff Chua , Etienne Basset , David Miller , rjw@sisk.pl, linux-kernel@vger.kernel.org, kernel-testers@vger.kernel.org, Ralf Baechle , linux-mips@linux-mips.org, linux-ide@vger.kernel.org In-Reply-To: <200907031508.47891.bzolnier@gmail.com> References: <200907021813.57322.bzolnier@gmail.com> <1246593505.27828.187.camel@falcon> <200907031508.47891.bzolnier@gmail.com> Content-Type: text/plain Organization: DSLab, Lanzhou University, China Date: Fri, 03 Jul 2009 23:31:36 +0800 Message-Id: <1246635096.16890.6.camel@falcon> Mime-Version: 1.0 X-Mailer: Evolution 2.26.1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23642 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips Hi, > OK, I see another gotcha added by recent changes, we need to explicitly > initialize rq_in_flight variables now. Revised patch below.. > Sorry, STD also not work. if apply this patch, the same problem as not apply it, it stopped at: ... PM: Crete hibernation image: PM: Need to copy ... pages PM: Hibernation image created ... I think it's better to revert this commit: a1317f714af7aed60ddc182d0122477cbe36ee9b ("ide: improve handling of Power Management requests") Regards, Wu Zhangjin > From: Bartlomiej Zolnierkiewicz > Subject: [PATCH] ide: make resume work again (for real) > > It turns out that commit a1317f714af7aed60ddc182d0122477cbe36ee9b > ("ide: improve handling of Power Management requests") needs to take > into the account a new code added by the recent block layer changes > in commit 8f6205cd572fece673da0255d74843680f67f879 ("ide: dequeue > in-flight request") and prevent clearing of hwif->rq if the device > is blocked. > > Thanks to Etienne, Wu and Jeff for help in fixing the issue. > > Reported-and-tested-by: Jeff Chua > Reported-and-tested-by: Etienne Basset > Reported-by: Wu Zhangjin > Signed-off-by: Bartlomiej Zolnierkiewicz > --- > Added patch description, no other changes. > > drivers/ide/ide-io.c | 19 ++++++++++++------- > 1 file changed, 12 insertions(+), 7 deletions(-) > > Index: b/drivers/ide/ide-io.c > =================================================================== > --- a/drivers/ide/ide-io.c > +++ b/drivers/ide/ide-io.c > @@ -532,7 +532,8 @@ repeat: > > if (startstop == ide_stopped) { > rq = hwif->rq; > - hwif->rq = NULL; > + if ((drive->dev_flags & IDE_DFLAG_BLOCKED) == 0) > + hwif->rq = NULL; > goto repeat; > } > } else > @@ -616,7 +617,7 @@ void ide_timer_expiry (unsigned long dat > unsigned long flags; > int wait = -1; > int plug_device = 0; > - struct request *uninitialized_var(rq_in_flight); > + struct request *rq_in_flight = NULL; > > spin_lock_irqsave(&hwif->lock, flags); > > @@ -679,8 +680,10 @@ void ide_timer_expiry (unsigned long dat > spin_lock_irq(&hwif->lock); > enable_irq(hwif->irq); > if (startstop == ide_stopped && hwif->polling == 0) { > - rq_in_flight = hwif->rq; > - hwif->rq = NULL; > + if ((drive->dev_flags & IDE_DFLAG_BLOCKED) == 0) { > + rq_in_flight = hwif->rq; > + hwif->rq = NULL; > + } > ide_unlock_port(hwif); > plug_device = 1; > } > @@ -775,7 +778,7 @@ irqreturn_t ide_intr (int irq, void *dev > ide_startstop_t startstop; > irqreturn_t irq_ret = IRQ_NONE; > int plug_device = 0; > - struct request *uninitialized_var(rq_in_flight); > + struct request *rq_in_flight = NULL; > > if (host->host_flags & IDE_HFLAG_SERIALIZE) { > if (hwif != host->cur_port) > @@ -856,8 +859,10 @@ irqreturn_t ide_intr (int irq, void *dev > */ > if (startstop == ide_stopped && hwif->polling == 0) { > BUG_ON(hwif->handler); > - rq_in_flight = hwif->rq; > - hwif->rq = NULL; > + if ((drive->dev_flags & IDE_DFLAG_BLOCKED) == 0) { > + rq_in_flight = hwif->rq; > + hwif->rq = NULL; > + } > ide_unlock_port(hwif); > plug_device = 1; > } From akinobu.mita@gmail.com Fri Jul 3 18:41:41 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 03 Jul 2009 18:41:47 +0200 (CEST) Received: from mail-pz0-f173.google.com ([209.85.222.173]:55225 "EHLO mail-pz0-f173.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492482AbZGCQll (ORCPT ); Fri, 3 Jul 2009 18:41:41 +0200 Received: by pzk3 with SMTP id 3so2307965pzk.22 for ; Fri, 03 Jul 2009 09:35:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:date:from:to:cc:subject :message-id:mime-version:content-type:content-disposition:user-agent; bh=cVvvJOL79N88fLDAaOfTiJGKfc0J56b2N+T5gu1fUxM=; b=DwNvfO/jf79v19bLTgXQaEvsyzm4GduelJoXOxNWPgMiG6ZS2bsfrWqvUC9MCxKWRb PM4DlBp7ont/iWmUSs64rwpTsG5tSALIjGKbnNygbr21ie710CDzZ6SeI4Nd1bd+WG/H D7Uir25GwzIGW6DeKOpcGyPnu/Mtw974LR0g0= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=date:from:to:cc:subject:message-id:mime-version:content-type :content-disposition:user-agent; b=oGFBG5K1OaZ3B0RrW3MPsKsHWBYbrvCaUdzIYThKiiidsN71efuGxc1Pw/0Lki2KMr hMTtbB3ZzKR5rfI0kIO93gTZRcrU2gc8u5NGKxx0uGf8RvziONHob1HdfhVOThdqRYqC FJgJkoDwYfrMFHKm3pErHIu8XJTFbgcFwpzrE= Received: by 10.140.208.16 with SMTP id f16mr1188054rvg.263.1246638930966; Fri, 03 Jul 2009 09:35:30 -0700 (PDT) Received: from localhost.localdomain (p11179-adsao01yokonib1-acca.kanagawa.ocn.ne.jp [61.199.5.179]) by mx.google.com with ESMTPS id g22sm16879315rvb.25.2009.07.03.09.35.28 (version=SSLv3 cipher=RC4-MD5); Fri, 03 Jul 2009 09:35:29 -0700 (PDT) Date: Sat, 4 Jul 2009 01:33:09 +0900 From: Akinobu Mita To: linux-mips@linux-mips.org Cc: Ralf Baechle Subject: [PATCH] mips: drop mmap_sem in pagefault oom path Message-ID: <20090703163307.GA25268@localhost.localdomain> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-2022-jp Content-Disposition: inline User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23643 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: akinobu.mita@gmail.com Precedence: bulk X-list: linux-mips Fix the pagefault oom path which does not drop mm->mmap_sem. This was introduced by commit c7c1e3846bac1e4b8a8941f6a194812e28b0a519 (This is not compile tested) Cc: Ralf Baechle Signed-off-by: Akinobu Mita --- arch/mips/mm/fault.c | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/arch/mips/mm/fault.c b/arch/mips/mm/fault.c index 6751ce9..f956ecb 100644 --- a/arch/mips/mm/fault.c +++ b/arch/mips/mm/fault.c @@ -171,6 +171,7 @@ out_of_memory: * We ran out of memory, call the OOM killer, and return the userspace * (which will retry the fault, or kill us if we got oom-killed). */ + up_read(&mm->mmap_sem); pagefault_out_of_memory(); return; -- 1.6.0.6 From tbm@cyrius.com Sat Jul 4 23:44:21 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 04 Jul 2009 23:44:28 +0200 (CEST) Received: from sorrow.cyrius.com ([65.19.161.204]:33039 "EHLO sorrow.cyrius.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492704AbZGDVoV (ORCPT ); Sat, 4 Jul 2009 23:44:21 +0200 Received: by sorrow.cyrius.com (Postfix, from userid 10) id A1363D8D1; Sat, 4 Jul 2009 21:37:51 +0000 (UTC) Received: by deprecation.cyrius.com (Postfix, from userid 1000) id 47188151158; Sat, 4 Jul 2009 23:37:41 +0200 (CEST) Date: Sat, 4 Jul 2009 23:37:41 +0200 From: Martin Michlmayr To: Yoichi Yuasa , linux-mips@linux-mips.org Cc: dwmw2@infradead.org Subject: mtd related Cobalt build failure with current git Message-ID: <20090704213741.GA6438@deprecation.cyrius.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit User-Agent: Mutt/1.5.19 (2009-01-05) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23644 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: tbm@cyrius.com Precedence: bulk X-list: linux-mips I get the following Cobalt build failure with current git: CC arch/mips/cobalt/mtd.o cc1: warnings being treated as errors In file included from arch/mips/cobalt/mtd.c:22: include/linux/mtd/partitions.h:50: warning: ‘struct mtd_info’ declared inside parameter list include/linux/mtd/partitions.h:50: warning: its scope is only this definition or declaration, which is probably not what you want include/linux/mtd/partitions.h:51: warning: ‘struct mtd_info’ declared inside parameter list include/linux/mtd/partitions.h:61: warning: ‘struct mtd_info’ declared inside parameter list include/linux/mtd/partitions.h:67: warning: ‘struct mtd_info’ declared inside parameter list make[1]: *** [arch/mips/cobalt/mtd.o] Error 1 make: *** [arch/mips/cobalt] Error 2 Does anyone know if there's a fix for this already? -- Martin Michlmayr http://www.cyrius.com/ From wuzhangjin@gmail.com Sun Jul 5 11:18:48 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 05 Jul 2009 11:18:58 +0200 (CEST) Received: from mail-pz0-f173.google.com ([209.85.222.173]:60497 "EHLO mail-pz0-f173.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492117AbZGEJSs (ORCPT ); Sun, 5 Jul 2009 11:18:48 +0200 Received: by pzk3 with SMTP id 3so3025706pzk.22 for ; Sun, 05 Jul 2009 02:12:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:subject:from:reply-to:to:cc :content-type:organization:date:message-id:mime-version:x-mailer; bh=aULajc5RiD0Bpn3k9g4y7aRd5DDtefyvkQsF2ycnBc0=; b=A0ByJ844ELr+pFDL5XUD5hFxAH30vbafplcyAV9PeIupkoynpE52JzcQBJVBLFIS9A rv6bYo4wYIEeSEU4zJXHrWGWuZR+O4w6ke8uCuBMMHBNDXg8ZLDUu0fBWPWsbctSbVA5 t6f9GwymiX7mDvJwVocUdEdKngZlo6xZS2qcw= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=subject:from:reply-to:to:cc:content-type:organization:date :message-id:mime-version:x-mailer; b=kKSqG7mR2EWXjTs6+z81XCZj/7NPyA7K7Ej0KrRW7+4nve5Uqhad/8LGmVk58jcENQ lRltmdUJ36DCrzXMCGjzFCfOcudyNtJai8db7mFCntIT8Gpkw6jd8zPWBpShNyWUd1L8 vT8CmBgOXCgiv4tOmxV7Gr17hbVxjA9ZeJ8w8= Received: by 10.114.151.4 with SMTP id y4mr5318260wad.27.1246785128212; Sun, 05 Jul 2009 02:12:08 -0700 (PDT) Received: from ?172.16.2.101? ([222.92.8.142]) by mx.google.com with ESMTPS id n6sm9044218wag.39.2009.07.05.02.12.01 (version=TLSv1/SSLv3 cipher=RC4-MD5); Sun, 05 Jul 2009 02:12:06 -0700 (PDT) Subject: [BUG] drivers/video/sis: deadlock introduced by "fbdev: add mutex for fb_mmap locking" From: Wu Zhangjin Reply-To: wuzhangjin@gmail.com To: linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mips@linux-mips.org Cc: Krzysztof Helt , Peter Zijlstra , "Rafael J. Wysocki" , Andrew Morton , Linus Torvalds , Ralf Baechle , =?UTF-8?Q?=E6=99=8F=E5=8D=8E?= , zhangfx Content-Type: multipart/mixed; boundary="=-ijWKSaVugkZli3X1t1ni" Organization: DSLab, Lanzhou University, China Date: Sun, 05 Jul 2009 17:11:52 +0800 Message-Id: <1246785112.14240.34.camel@falcon> Mime-Version: 1.0 X-Mailer: Evolution 2.26.1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23645 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips --=-ijWKSaVugkZli3X1t1ni Content-Type: text/plain Content-Transfer-Encoding: 7bit Hi, all I just tested the sis315 driver in the latest master branch of linux-mips git repository on fuloong2f(loongson-based machine, loongson is mips comptable): Device Drivers ---> Graphics support ---> <*> Support for frame buffer devices ---> <*> SiS/XGI display support [*] SiS 315/330/340 series and XGI support The kernel stopped at(output via serial port): ... sisfb: Detected SiS301C video bridge sisfb: CRT1 DDC probing failed sisfb: Default mode is 800x600x8 (60HZ) no more output, but the Num,Caps light of keyboard works. and because sis 315 of the latest linux-2.6.30-stable works well on fuloong2f, so, I tried to check the latest commits who modified sis relative source code via "git whatchanged", at last I found this: commit 537a1bf059fa312355696fa6db80726e655e7f17 Author: Krzysztof Helt Date: Tue Jun 30 11:41:29 2009 -0700 fbdev: add mutex for fb_mmap locking Add a mutex to avoid a circular locking problem between the mm layer semaphore and fbdev ioctl mutex through the fb_mmap() call. Also, add mutex to all places where smem_start and smem_len fields change so the mutex inside the fb_mmap() is actually used. Changing of these fields before calling the framebuffer_register() are not mutexed. This is 2.6.31 material. It removes one lockdep (fb_mmap() and register_framebuffer()) but there is still another one (fb_release() and register_framebuffer()). It also cleans up handling of the smem_start and smem_len fields used by mutexed section of the fb_mmap(). Signed-off-by: Krzysztof Helt Cc: Peter Zijlstra Cc: "Rafael J. Wysocki" Cc: Signed-off-by: Andrew Morton Signed-off-by: Linus Torvalds and then, I tried to revert the modification in drivers/video/sis/sis_main.c: diff --git a/drivers/video/sis/sis_main.c b/drivers/video/sis/sis_main.c index fd33455..7072d19 100644 --- a/drivers/video/sis/sis_main.c +++ b/drivers/video/sis/sis_main.c @@ -1847,10 +1847,8 @@ sisfb_get_fix(struct fb_fix_screeninfo *fix, int con, struct fb_info *info) strcpy(fix->id, ivideo->myid); - mutex_lock(&info->mm_lock); fix->smem_start = ivideo->video_base + ivideo->video_offset; fix->smem_len = ivideo->sisfb_mem; - mutex_unlock(&info->mm_lock); fix->type = FB_TYPE_PACKED_PIXELS; fix->type_aux = 0; fix->visual = (ivideo->video_bpp == 8) ? FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR; then it works! so, I guess there is a deadlock introduced by the above commit. I attached my config file, hope it can give you more information about this bug. Regards, Wu Zhangjin --=-ijWKSaVugkZli3X1t1ni Content-Disposition: attachment; filename="sis315-deadlock.config" Content-Type: text/plain; name="sis315-deadlock.config"; charset="UTF-8" Content-Transfer-Encoding: 7bit # # Automatically generated make config: don't edit # Linux kernel version: 2.6.31-rc2 # Sun Jul 5 16:25:14 2009 # CONFIG_MIPS=y # # Machine selection # # CONFIG_MACH_ALCHEMY is not set # CONFIG_AR7 is not set # CONFIG_BASLER_EXCITE is not set # CONFIG_BCM47XX is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set # CONFIG_LASAT is not set CONFIG_MACH_LOONGSON=y # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SIM is not set # CONFIG_NEC_MARKEINS is not set # CONFIG_MACH_VR41XX is not set # CONFIG_NXP_STB220 is not set # CONFIG_NXP_STB225 is not set # CONFIG_PNX8550_JBS is not set # CONFIG_PNX8550_STB810 is not set # CONFIG_PMC_MSP is not set # CONFIG_PMC_YOSEMITE is not set # CONFIG_SGI_IP22 is not set # CONFIG_SGI_IP27 is not set # CONFIG_SGI_IP28 is not set # CONFIG_SGI_IP32 is not set # CONFIG_SIBYTE_CRHINE is not set # CONFIG_SIBYTE_CARMEL is not set # CONFIG_SIBYTE_CRHONE is not set # CONFIG_SIBYTE_RHONE is not set # CONFIG_SIBYTE_SWARM is not set # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_SENTOSA is not set # CONFIG_SIBYTE_BIGSUR is not set # CONFIG_SNI_RM is not set # CONFIG_MACH_TX39XX is not set # CONFIG_MACH_TX49XX is not set # CONFIG_MIKROTIK_RB532 is not set # CONFIG_WR_PPMC is not set # CONFIG_CAVIUM_OCTEON_SIMULATOR is not set # CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD is not set # CONFIG_ALCHEMY_GPIO_INDIRECT is not set CONFIG_ARCH_SPARSEMEM_ENABLE=y # CONFIG_LEMOTE_FULOONG2E is not set CONFIG_LEMOTE_FULOONG2F=y CONFIG_CS5536=y CONFIG_RWSEM_GENERIC_SPINLOCK=y # CONFIG_ARCH_HAS_ILOG2_U32 is not set # CONFIG_ARCH_HAS_ILOG2_U64 is not set CONFIG_ARCH_SUPPORTS_OPROFILE=y CONFIG_GENERIC_FIND_NEXT_BIT=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_GENERIC_CLOCKEVENTS=y CONFIG_GENERIC_TIME=y CONFIG_GENERIC_CMOS_UPDATE=y CONFIG_SCHED_OMIT_FRAME_POINTER=y CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y CONFIG_CEVT_R4K_LIB=y CONFIG_CEVT_R4K=y CONFIG_CSRC_R4K_LIB=y CONFIG_CSRC_R4K=y CONFIG_DMA_NONCOHERENT=y CONFIG_DMA_NEED_PCI_MAP_STATE=y CONFIG_EARLY_PRINTK=y CONFIG_SYS_HAS_EARLY_PRINTK=y CONFIG_I8259=y # CONFIG_NO_IOPORT is not set CONFIG_GENERIC_ISA_DMA=y CONFIG_GENERIC_ISA_DMA_SUPPORT_BROKEN=y # CONFIG_CPU_BIG_ENDIAN is not set CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y CONFIG_IRQ_CPU=y CONFIG_BOOT_ELF32=y CONFIG_MIPS_L1_CACHE_SHIFT=5 # # CPU selection # # CONFIG_CPU_LOONGSON2E is not set CONFIG_CPU_LOONGSON2F=y # CONFIG_CPU_MIPS32_R1 is not set # CONFIG_CPU_MIPS32_R2 is not set # CONFIG_CPU_MIPS64_R1 is not set # CONFIG_CPU_MIPS64_R2 is not set # CONFIG_CPU_R3000 is not set # CONFIG_CPU_TX39XX is not set # CONFIG_CPU_VR41XX is not set # CONFIG_CPU_R4300 is not set # CONFIG_CPU_R4X00 is not set # CONFIG_CPU_TX49XX is not set # CONFIG_CPU_R5000 is not set # CONFIG_CPU_R5432 is not set # CONFIG_CPU_R5500 is not set # CONFIG_CPU_R6000 is not set # CONFIG_CPU_NEVADA is not set # CONFIG_CPU_R8000 is not set # CONFIG_CPU_R10000 is not set # CONFIG_CPU_RM7000 is not set # CONFIG_CPU_RM9000 is not set # CONFIG_CPU_SB1 is not set # CONFIG_CPU_CAVIUM_OCTEON is not set CONFIG_CPU_LOONGSON2=y CONFIG_SYS_HAS_CPU_LOONGSON2F=y CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y # # Kernel type # # CONFIG_32BIT is not set CONFIG_64BIT=y # CONFIG_PAGE_SIZE_4KB is not set # CONFIG_PAGE_SIZE_8KB is not set CONFIG_PAGE_SIZE_16KB=y # CONFIG_PAGE_SIZE_32KB is not set # CONFIG_PAGE_SIZE_64KB is not set CONFIG_BOARD_SCACHE=y CONFIG_MIPS_MT_DISABLED=y # CONFIG_MIPS_MT_SMP is not set # CONFIG_MIPS_MT_SMTC is not set CONFIG_CPU_HAS_WB=y CONFIG_CPU_HAS_SYNC=y CONFIG_GENERIC_HARDIRQS=y CONFIG_GENERIC_IRQ_PROBE=y CONFIG_CPU_SUPPORTS_HIGHMEM=y CONFIG_SYS_SUPPORTS_HIGHMEM=y CONFIG_ARCH_FLATMEM_ENABLE=y CONFIG_ARCH_POPULATES_NODE_MAP=y CONFIG_SELECT_MEMORY_MODEL=y # CONFIG_FLATMEM_MANUAL is not set # CONFIG_DISCONTIGMEM_MANUAL is not set CONFIG_SPARSEMEM_MANUAL=y CONFIG_SPARSEMEM=y CONFIG_HAVE_MEMORY_PRESENT=y CONFIG_SPARSEMEM_STATIC=y CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 CONFIG_PHYS_ADDR_T_64BIT=y CONFIG_ZONE_DMA_FLAG=0 CONFIG_VIRT_TO_BUS=y CONFIG_HAVE_MLOCK=y CONFIG_HAVE_MLOCKED_PAGE_BIT=y CONFIG_DEFAULT_MMAP_MIN_ADDR=4096 CONFIG_TICK_ONESHOT=y CONFIG_NO_HZ=y CONFIG_HIGH_RES_TIMERS=y CONFIG_GENERIC_CLOCKEVENTS_BUILD=y # CONFIG_HZ_48 is not set # CONFIG_HZ_100 is not set # CONFIG_HZ_128 is not set CONFIG_HZ_250=y # CONFIG_HZ_256 is not set # CONFIG_HZ_1000 is not set # CONFIG_HZ_1024 is not set CONFIG_SYS_SUPPORTS_ARBIT_HZ=y CONFIG_HZ=250 # CONFIG_PREEMPT_NONE is not set CONFIG_PREEMPT_VOLUNTARY=y # CONFIG_PREEMPT is not set CONFIG_KEXEC=y # CONFIG_SECCOMP is not set CONFIG_LOCKDEP_SUPPORT=y CONFIG_STACKTRACE_SUPPORT=y CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" CONFIG_CONSTRUCTORS=y # # General setup # CONFIG_EXPERIMENTAL=y CONFIG_BROKEN_ON_SMP=y CONFIG_INIT_ENV_ARG_LIMIT=32 CONFIG_LOCALVERSION="" # CONFIG_LOCALVERSION_AUTO is not set CONFIG_SWAP=y CONFIG_SYSVIPC=y CONFIG_SYSVIPC_SYSCTL=y CONFIG_POSIX_MQUEUE=y CONFIG_POSIX_MQUEUE_SYSCTL=y CONFIG_BSD_PROCESS_ACCT=y CONFIG_BSD_PROCESS_ACCT_V3=y # CONFIG_TASKSTATS is not set CONFIG_AUDIT=y # # RCU Subsystem # CONFIG_CLASSIC_RCU=y # CONFIG_TREE_RCU is not set # CONFIG_PREEMPT_RCU is not set # CONFIG_TREE_RCU_TRACE is not set # CONFIG_PREEMPT_RCU_TRACE is not set CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=15 # CONFIG_GROUP_SCHED is not set # CONFIG_CGROUPS is not set CONFIG_SYSFS_DEPRECATED=y CONFIG_SYSFS_DEPRECATED_V2=y # CONFIG_RELAY is not set # CONFIG_NAMESPACES is not set CONFIG_BLK_DEV_INITRD=y CONFIG_INITRAMFS_SOURCE="" CONFIG_RD_GZIP=y # CONFIG_RD_BZIP2 is not set # CONFIG_RD_LZMA is not set CONFIG_CC_OPTIMIZE_FOR_SIZE=y CONFIG_SYSCTL=y CONFIG_ANON_INODES=y CONFIG_EMBEDDED=y CONFIG_SYSCTL_SYSCALL=y CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_EXTRA_PASS is not set CONFIG_HOTPLUG=y CONFIG_PRINTK=y CONFIG_BUG=y CONFIG_ELF_CORE=y CONFIG_PCSPKR_PLATFORM=y CONFIG_BASE_FULL=y CONFIG_FUTEX=y CONFIG_EPOLL=y CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y CONFIG_AIO=y # # Performance Counters # CONFIG_VM_EVENT_COUNTERS=y CONFIG_PCI_QUIRKS=y # CONFIG_STRIP_ASM_SYMS is not set CONFIG_COMPAT_BRK=y CONFIG_SLAB=y # CONFIG_SLUB is not set # CONFIG_SLOB is not set CONFIG_PROFILING=y # CONFIG_MARKERS is not set # CONFIG_OPROFILE is not set CONFIG_HAVE_OPROFILE=y CONFIG_HAVE_SYSCALL_WRAPPERS=y # # GCOV-based kernel profiling # # CONFIG_GCOV_KERNEL is not set # CONFIG_SLOW_WORK is not set # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y CONFIG_BASE_SMALL=0 CONFIG_MODULES=y # CONFIG_MODULE_FORCE_LOAD is not set CONFIG_MODULE_UNLOAD=y CONFIG_MODULE_FORCE_UNLOAD=y CONFIG_MODVERSIONS=y # CONFIG_MODULE_SRCVERSION_ALL is not set CONFIG_BLOCK=y # CONFIG_BLK_DEV_BSG is not set # CONFIG_BLK_DEV_INTEGRITY is not set CONFIG_BLOCK_COMPAT=y # # IO Schedulers # CONFIG_IOSCHED_NOOP=y CONFIG_IOSCHED_AS=y CONFIG_IOSCHED_DEADLINE=y CONFIG_IOSCHED_CFQ=y # CONFIG_DEFAULT_AS is not set # CONFIG_DEFAULT_DEADLINE is not set CONFIG_DEFAULT_CFQ=y # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="cfq" # CONFIG_PROBE_INITRD_HEADER is not set CONFIG_FREEZER=y # # Bus options (PCI, PCMCIA, EISA, ISA, TC) # CONFIG_HW_HAS_PCI=y CONFIG_PCI=y CONFIG_PCI_DOMAINS=y # CONFIG_ARCH_SUPPORTS_MSI is not set CONFIG_PCI_LEGACY=y # CONFIG_PCI_STUB is not set # CONFIG_PCI_IOV is not set CONFIG_ISA=y CONFIG_MMU=y # CONFIG_PCCARD is not set # CONFIG_HOTPLUG_PCI is not set # # Executable file formats # CONFIG_BINFMT_ELF=y # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set # CONFIG_HAVE_AOUT is not set # CONFIG_BINFMT_MISC is not set CONFIG_MIPS32_COMPAT=y CONFIG_COMPAT=y CONFIG_SYSVIPC_COMPAT=y CONFIG_MIPS32_O32=y CONFIG_MIPS32_N32=y CONFIG_BINFMT_ELF32=y # # Power management options # CONFIG_ARCH_HIBERNATION_POSSIBLE=y CONFIG_ARCH_SUSPEND_POSSIBLE=y CONFIG_PM=y # CONFIG_PM_DEBUG is not set CONFIG_PM_SLEEP=y CONFIG_SUSPEND=y CONFIG_SUSPEND_FREEZER=y # CONFIG_HIBERNATION is not set CONFIG_NET=y # # Networking options # CONFIG_PACKET=y CONFIG_PACKET_MMAP=y CONFIG_UNIX=y CONFIG_XFRM=y # CONFIG_XFRM_USER is not set # CONFIG_XFRM_SUB_POLICY is not set # CONFIG_XFRM_MIGRATE is not set # CONFIG_XFRM_STATISTICS is not set # CONFIG_NET_KEY is not set CONFIG_INET=y CONFIG_IP_MULTICAST=y CONFIG_IP_ADVANCED_ROUTER=y CONFIG_ASK_IP_FIB_HASH=y # CONFIG_IP_FIB_TRIE is not set CONFIG_IP_FIB_HASH=y CONFIG_IP_MULTIPLE_TABLES=y CONFIG_IP_ROUTE_MULTIPATH=y CONFIG_IP_ROUTE_VERBOSE=y # CONFIG_IP_PNP is not set # CONFIG_NET_IPIP is not set # CONFIG_NET_IPGRE is not set CONFIG_IP_MROUTE=y CONFIG_IP_PIMSM_V1=y CONFIG_IP_PIMSM_V2=y # CONFIG_ARPD is not set CONFIG_SYN_COOKIES=y # CONFIG_INET_AH is not set # CONFIG_INET_ESP is not set # CONFIG_INET_IPCOMP is not set # CONFIG_INET_XFRM_TUNNEL is not set CONFIG_INET_TUNNEL=m CONFIG_INET_XFRM_MODE_TRANSPORT=y CONFIG_INET_XFRM_MODE_TUNNEL=y CONFIG_INET_XFRM_MODE_BEET=y CONFIG_INET_LRO=y CONFIG_INET_DIAG=y CONFIG_INET_TCP_DIAG=y CONFIG_TCP_CONG_ADVANCED=y CONFIG_TCP_CONG_BIC=y CONFIG_TCP_CONG_CUBIC=y CONFIG_TCP_CONG_WESTWOOD=m CONFIG_TCP_CONG_HTCP=m # CONFIG_TCP_CONG_HSTCP is not set # CONFIG_TCP_CONG_HYBLA is not set # CONFIG_TCP_CONG_VEGAS is not set # CONFIG_TCP_CONG_SCALABLE is not set # CONFIG_TCP_CONG_LP is not set # CONFIG_TCP_CONG_VENO is not set # CONFIG_TCP_CONG_YEAH is not set # CONFIG_TCP_CONG_ILLINOIS is not set CONFIG_DEFAULT_BIC=y # CONFIG_DEFAULT_CUBIC is not set # CONFIG_DEFAULT_HTCP is not set # CONFIG_DEFAULT_VEGAS is not set # CONFIG_DEFAULT_WESTWOOD is not set # CONFIG_DEFAULT_RENO is not set CONFIG_DEFAULT_TCP_CONG="bic" # CONFIG_TCP_MD5SIG is not set CONFIG_IPV6=m CONFIG_IPV6_PRIVACY=y # CONFIG_IPV6_ROUTER_PREF is not set # CONFIG_IPV6_OPTIMISTIC_DAD is not set # CONFIG_INET6_AH is not set # CONFIG_INET6_ESP is not set # CONFIG_INET6_IPCOMP is not set # CONFIG_IPV6_MIP6 is not set # CONFIG_INET6_XFRM_TUNNEL is not set # CONFIG_INET6_TUNNEL is not set CONFIG_INET6_XFRM_MODE_TRANSPORT=m CONFIG_INET6_XFRM_MODE_TUNNEL=m CONFIG_INET6_XFRM_MODE_BEET=m # CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set CONFIG_IPV6_SIT=m CONFIG_IPV6_NDISC_NODETYPE=y # CONFIG_IPV6_TUNNEL is not set # CONFIG_IPV6_MULTIPLE_TABLES is not set # CONFIG_IPV6_MROUTE is not set # CONFIG_NETLABEL is not set CONFIG_NETWORK_SECMARK=y CONFIG_NETFILTER=y # CONFIG_NETFILTER_DEBUG is not set CONFIG_NETFILTER_ADVANCED=y # # Core Netfilter Configuration # # CONFIG_NETFILTER_NETLINK_QUEUE is not set # CONFIG_NETFILTER_NETLINK_LOG is not set # CONFIG_NF_CONNTRACK is not set # CONFIG_NETFILTER_XTABLES is not set # CONFIG_IP_VS is not set # # IP: Netfilter Configuration # # CONFIG_NF_DEFRAG_IPV4 is not set # CONFIG_IP_NF_QUEUE is not set # CONFIG_IP_NF_IPTABLES is not set # CONFIG_IP_NF_ARPTABLES is not set # # IPv6: Netfilter Configuration # # CONFIG_IP6_NF_QUEUE is not set # CONFIG_IP6_NF_IPTABLES is not set # CONFIG_IP_DCCP is not set # CONFIG_IP_SCTP is not set # CONFIG_TIPC is not set CONFIG_ATM=y CONFIG_ATM_CLIP=y # CONFIG_ATM_CLIP_NO_ICMP is not set # CONFIG_ATM_LANE is not set # CONFIG_ATM_BR2684 is not set # CONFIG_BRIDGE is not set # CONFIG_NET_DSA is not set # CONFIG_VLAN_8021Q is not set # CONFIG_DECNET is not set # CONFIG_LLC2 is not set # CONFIG_IPX is not set # CONFIG_ATALK is not set # CONFIG_X25 is not set # CONFIG_LAPB is not set # CONFIG_ECONET is not set # CONFIG_WAN_ROUTER is not set # CONFIG_PHONET is not set # CONFIG_IEEE802154 is not set CONFIG_NET_SCHED=y # # Queueing/Scheduling # # CONFIG_NET_SCH_CBQ is not set # CONFIG_NET_SCH_HTB is not set # CONFIG_NET_SCH_HFSC is not set # CONFIG_NET_SCH_ATM is not set # CONFIG_NET_SCH_PRIO is not set # CONFIG_NET_SCH_MULTIQ is not set # CONFIG_NET_SCH_RED is not set # CONFIG_NET_SCH_SFQ is not set # CONFIG_NET_SCH_TEQL is not set # CONFIG_NET_SCH_TBF is not set # CONFIG_NET_SCH_GRED is not set # CONFIG_NET_SCH_DSMARK is not set # CONFIG_NET_SCH_NETEM is not set # CONFIG_NET_SCH_DRR is not set # CONFIG_NET_SCH_INGRESS is not set # # Classification # CONFIG_NET_CLS=y # CONFIG_NET_CLS_BASIC is not set # CONFIG_NET_CLS_TCINDEX is not set # CONFIG_NET_CLS_ROUTE4 is not set # CONFIG_NET_CLS_FW is not set # CONFIG_NET_CLS_U32 is not set # CONFIG_NET_CLS_RSVP is not set # CONFIG_NET_CLS_RSVP6 is not set # CONFIG_NET_CLS_FLOW is not set CONFIG_NET_EMATCH=y CONFIG_NET_EMATCH_STACK=32 # CONFIG_NET_EMATCH_CMP is not set # CONFIG_NET_EMATCH_NBYTE is not set # CONFIG_NET_EMATCH_U32 is not set # CONFIG_NET_EMATCH_META is not set # CONFIG_NET_EMATCH_TEXT is not set CONFIG_NET_CLS_ACT=y # CONFIG_NET_ACT_POLICE is not set # CONFIG_NET_ACT_GACT is not set # CONFIG_NET_ACT_MIRRED is not set # CONFIG_NET_ACT_NAT is not set # CONFIG_NET_ACT_PEDIT is not set # CONFIG_NET_ACT_SIMP is not set # CONFIG_NET_ACT_SKBEDIT is not set CONFIG_NET_SCH_FIFO=y # CONFIG_DCB is not set # # Network testing # # CONFIG_NET_PKTGEN is not set CONFIG_HAMRADIO=y # # Packet Radio protocols # # CONFIG_AX25 is not set # CONFIG_CAN is not set # CONFIG_IRDA is not set # CONFIG_BT is not set CONFIG_AF_RXRPC=y # CONFIG_AF_RXRPC_DEBUG is not set # CONFIG_RXKAD is not set CONFIG_FIB_RULES=y # CONFIG_WIRELESS is not set # CONFIG_WIMAX is not set # CONFIG_RFKILL is not set # CONFIG_NET_9P is not set # # Device Drivers # # # Generic Driver Options # CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_STANDALONE=y CONFIG_PREVENT_FIRMWARE_BUILD=y CONFIG_FW_LOADER=y CONFIG_FIRMWARE_IN_KERNEL=y CONFIG_EXTRA_FIRMWARE="" # CONFIG_SYS_HYPERVISOR is not set # CONFIG_CONNECTOR is not set # CONFIG_MTD is not set # CONFIG_PARPORT is not set CONFIG_PNP=y CONFIG_PNP_DEBUG_MESSAGES=y # # Protocols # CONFIG_ISAPNP=y # CONFIG_PNPACPI is not set CONFIG_BLK_DEV=y # CONFIG_BLK_CPQ_DA is not set # CONFIG_BLK_CPQ_CISS_DA is not set # CONFIG_BLK_DEV_DAC960 is not set # CONFIG_BLK_DEV_UMEM is not set # CONFIG_BLK_DEV_COW_COMMON is not set CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_CRYPTOLOOP=y # CONFIG_BLK_DEV_NBD is not set # CONFIG_BLK_DEV_SX8 is not set # CONFIG_BLK_DEV_UB is not set CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_COUNT=16 CONFIG_BLK_DEV_RAM_SIZE=8192 # CONFIG_BLK_DEV_XIP is not set # CONFIG_CDROM_PKTCDVD is not set # CONFIG_ATA_OVER_ETH is not set # CONFIG_BLK_DEV_HD is not set CONFIG_MISC_DEVICES=y # CONFIG_PHANTOM is not set # CONFIG_SGI_IOC4 is not set # CONFIG_TIFM_CORE is not set # CONFIG_ENCLOSURE_SERVICES is not set # CONFIG_HP_ILO is not set # CONFIG_C2PORT is not set # # EEPROM support # # CONFIG_EEPROM_93CX6 is not set # CONFIG_CB710_CORE is not set CONFIG_HAVE_IDE=y CONFIG_IDE=y # # Please see Documentation/ide/ide.txt for help/info on IDE drives # CONFIG_IDE_XFER_MODE=y CONFIG_IDE_TIMINGS=y # CONFIG_BLK_DEV_IDE_SATA is not set CONFIG_IDE_GD=y CONFIG_IDE_GD_ATA=y # CONFIG_IDE_GD_ATAPI is not set # CONFIG_BLK_DEV_IDECD is not set # CONFIG_BLK_DEV_IDETAPE is not set CONFIG_IDE_TASK_IOCTL=y CONFIG_IDE_PROC_FS=y # # IDE chipset support/bugfixes # # CONFIG_IDE_GENERIC is not set # CONFIG_BLK_DEV_PLATFORM is not set # CONFIG_BLK_DEV_IDEPNP is not set CONFIG_BLK_DEV_IDEDMA_SFF=y # # PCI IDE chipsets support # CONFIG_BLK_DEV_IDEPCI=y # CONFIG_IDEPCI_PCIBUS_ORDER is not set # CONFIG_BLK_DEV_OFFBOARD is not set CONFIG_BLK_DEV_GENERIC=y # CONFIG_BLK_DEV_OPTI621 is not set CONFIG_BLK_DEV_IDEDMA_PCI=y # CONFIG_BLK_DEV_AEC62XX is not set # CONFIG_BLK_DEV_ALI15X3 is not set CONFIG_BLK_DEV_AMD74XX=y # CONFIG_BLK_DEV_CMD64X is not set # CONFIG_BLK_DEV_TRIFLEX is not set # CONFIG_BLK_DEV_CS5520 is not set # CONFIG_BLK_DEV_CS5530 is not set # CONFIG_BLK_DEV_HPT366 is not set # CONFIG_BLK_DEV_JMICRON is not set # CONFIG_BLK_DEV_SC1200 is not set # CONFIG_BLK_DEV_PIIX is not set # CONFIG_BLK_DEV_IT8172 is not set # CONFIG_BLK_DEV_IT8213 is not set # CONFIG_BLK_DEV_IT821X is not set # CONFIG_BLK_DEV_NS87415 is not set # CONFIG_BLK_DEV_PDC202XX_OLD is not set # CONFIG_BLK_DEV_PDC202XX_NEW is not set # CONFIG_BLK_DEV_SVWKS is not set # CONFIG_BLK_DEV_SIIMAGE is not set # CONFIG_BLK_DEV_SLC90E66 is not set # CONFIG_BLK_DEV_TRM290 is not set # CONFIG_BLK_DEV_VIA82CXXX is not set # CONFIG_BLK_DEV_TC86C001 is not set # # Other IDE chipsets support # # # Note: most of these also require special kernel boot parameters # # CONFIG_BLK_DEV_4DRIVES is not set # CONFIG_BLK_DEV_ALI14XX is not set # CONFIG_BLK_DEV_DTC2278 is not set # CONFIG_BLK_DEV_HT6560B is not set # CONFIG_BLK_DEV_QD65XX is not set # CONFIG_BLK_DEV_UMC8672 is not set CONFIG_BLK_DEV_IDEDMA=y # # SCSI device support # # CONFIG_RAID_ATTRS is not set CONFIG_SCSI=y CONFIG_SCSI_DMA=y # CONFIG_SCSI_TGT is not set # CONFIG_SCSI_NETLINK is not set CONFIG_SCSI_PROC_FS=y # # SCSI support type (disk, tape, CD-ROM) # CONFIG_BLK_DEV_SD=y # CONFIG_CHR_DEV_ST is not set # CONFIG_CHR_DEV_OSST is not set # CONFIG_BLK_DEV_SR is not set # CONFIG_CHR_DEV_SG is not set # CONFIG_CHR_DEV_SCH is not set CONFIG_SCSI_MULTI_LUN=y CONFIG_SCSI_CONSTANTS=y CONFIG_SCSI_LOGGING=y # CONFIG_SCSI_SCAN_ASYNC is not set CONFIG_SCSI_WAIT_SCAN=m # # SCSI Transports # # CONFIG_SCSI_SPI_ATTRS is not set # CONFIG_SCSI_FC_ATTRS is not set # CONFIG_SCSI_ISCSI_ATTRS is not set # CONFIG_SCSI_SAS_LIBSAS is not set # CONFIG_SCSI_SRP_ATTRS is not set CONFIG_SCSI_LOWLEVEL=y # CONFIG_ISCSI_TCP is not set # CONFIG_SCSI_BNX2_ISCSI is not set # CONFIG_BLK_DEV_3W_XXXX_RAID is not set # CONFIG_SCSI_3W_9XXX is not set # CONFIG_SCSI_ACARD is not set # CONFIG_SCSI_AACRAID is not set # CONFIG_SCSI_AIC7XXX is not set # CONFIG_SCSI_AIC7XXX_OLD is not set # CONFIG_SCSI_AIC79XX is not set # CONFIG_SCSI_AIC94XX is not set # CONFIG_SCSI_MVSAS is not set # CONFIG_SCSI_DPT_I2O is not set # CONFIG_SCSI_ADVANSYS is not set # CONFIG_SCSI_IN2000 is not set # CONFIG_SCSI_ARCMSR is not set # CONFIG_MEGARAID_NEWGEN is not set # CONFIG_MEGARAID_LEGACY is not set # CONFIG_MEGARAID_SAS is not set # CONFIG_SCSI_MPT2SAS is not set # CONFIG_SCSI_HPTIOP is not set # CONFIG_LIBFC is not set # CONFIG_LIBFCOE is not set # CONFIG_FCOE is not set # CONFIG_SCSI_DMX3191D is not set # CONFIG_SCSI_DTC3280 is not set # CONFIG_SCSI_FUTURE_DOMAIN is not set # CONFIG_SCSI_GENERIC_NCR5380 is not set # CONFIG_SCSI_GENERIC_NCR5380_MMIO is not set # CONFIG_SCSI_IPS is not set # CONFIG_SCSI_INITIO is not set # CONFIG_SCSI_INIA100 is not set # CONFIG_SCSI_NCR53C406A is not set # CONFIG_SCSI_STEX is not set # CONFIG_SCSI_SYM53C8XX_2 is not set # CONFIG_SCSI_PAS16 is not set # CONFIG_SCSI_QLOGIC_FAS is not set # CONFIG_SCSI_QLOGIC_1280 is not set # CONFIG_SCSI_QLA_FC is not set # CONFIG_SCSI_QLA_ISCSI is not set # CONFIG_SCSI_LPFC is not set # CONFIG_SCSI_SYM53C416 is not set # CONFIG_SCSI_DC395x is not set # CONFIG_SCSI_DC390T is not set # CONFIG_SCSI_T128 is not set # CONFIG_SCSI_DEBUG is not set # CONFIG_SCSI_SRP is not set # CONFIG_SCSI_DH is not set # CONFIG_SCSI_OSD_INITIATOR is not set # CONFIG_ATA is not set CONFIG_MD=y # CONFIG_BLK_DEV_MD is not set # CONFIG_BLK_DEV_DM is not set CONFIG_FUSION=y # CONFIG_FUSION_SPI is not set # CONFIG_FUSION_FC is not set # CONFIG_FUSION_SAS is not set CONFIG_FUSION_MAX_SGE=40 # CONFIG_FUSION_LOGGING is not set # # IEEE 1394 (FireWire) support # # # You can enable one or both FireWire driver stacks. # # # See the help texts for more information. # # CONFIG_FIREWIRE is not set # CONFIG_IEEE1394 is not set # CONFIG_I2O is not set CONFIG_NETDEVICES=y # CONFIG_IFB is not set # CONFIG_DUMMY is not set # CONFIG_BONDING is not set # CONFIG_MACVLAN is not set # CONFIG_EQUALIZER is not set # CONFIG_TUN is not set # CONFIG_VETH is not set # CONFIG_NET_SB1000 is not set # CONFIG_ARCNET is not set CONFIG_PHYLIB=y # # MII PHY device drivers # # CONFIG_MARVELL_PHY is not set # CONFIG_DAVICOM_PHY is not set # CONFIG_QSEMI_PHY is not set # CONFIG_LXT_PHY is not set # CONFIG_CICADA_PHY is not set # CONFIG_VITESSE_PHY is not set # CONFIG_SMSC_PHY is not set # CONFIG_BROADCOM_PHY is not set # CONFIG_ICPLUS_PHY is not set # CONFIG_REALTEK_PHY is not set # CONFIG_NATIONAL_PHY is not set # CONFIG_STE10XP is not set # CONFIG_LSI_ET1011C_PHY is not set # CONFIG_FIXED_PHY is not set # CONFIG_MDIO_BITBANG is not set CONFIG_NET_ETHERNET=y CONFIG_MII=y # CONFIG_AX88796 is not set # CONFIG_HAPPYMEAL is not set # CONFIG_SUNGEM is not set # CONFIG_CASSINI is not set # CONFIG_NET_VENDOR_3COM is not set # CONFIG_NET_VENDOR_SMC is not set # CONFIG_SMC91X is not set # CONFIG_DM9000 is not set # CONFIG_ETHOC is not set # CONFIG_NET_VENDOR_RACAL is not set # CONFIG_DNET is not set # CONFIG_NET_TULIP is not set # CONFIG_AT1700 is not set # CONFIG_DEPCA is not set # CONFIG_HP100 is not set # CONFIG_NET_ISA is not set # CONFIG_IBM_NEW_EMAC_ZMII is not set # CONFIG_IBM_NEW_EMAC_RGMII is not set # CONFIG_IBM_NEW_EMAC_TAH is not set # CONFIG_IBM_NEW_EMAC_EMAC4 is not set # CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set # CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set # CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set # CONFIG_NET_PCI is not set # CONFIG_B44 is not set # CONFIG_CS89x0 is not set # CONFIG_KS8842 is not set # CONFIG_ATL2 is not set CONFIG_NETDEV_1000=y # CONFIG_ACENIC is not set # CONFIG_DL2K is not set # CONFIG_E1000 is not set # CONFIG_E1000E is not set # CONFIG_IP1000 is not set # CONFIG_IGB is not set # CONFIG_IGBVF is not set # CONFIG_NS83820 is not set # CONFIG_HAMACHI is not set # CONFIG_YELLOWFIN is not set CONFIG_R8169=y # CONFIG_SIS190 is not set # CONFIG_SKGE is not set # CONFIG_SKY2 is not set # CONFIG_VIA_VELOCITY is not set # CONFIG_TIGON3 is not set # CONFIG_BNX2 is not set # CONFIG_CNIC is not set # CONFIG_QLA3XXX is not set # CONFIG_ATL1 is not set # CONFIG_ATL1E is not set # CONFIG_ATL1C is not set # CONFIG_JME is not set # CONFIG_NETDEV_10000 is not set # CONFIG_TR is not set # # Wireless LAN # # CONFIG_WLAN_PRE80211 is not set # CONFIG_WLAN_80211 is not set # # Enable WiMAX (Networking options) to see the WiMAX drivers # # # USB Network Adapters # # CONFIG_USB_CATC is not set # CONFIG_USB_KAWETH is not set # CONFIG_USB_PEGASUS is not set # CONFIG_USB_RTL8150 is not set # CONFIG_USB_USBNET is not set # CONFIG_WAN is not set # CONFIG_ATM_DRIVERS is not set # CONFIG_FDDI is not set # CONFIG_HIPPI is not set # CONFIG_PPP is not set # CONFIG_SLIP is not set # CONFIG_NET_FC is not set # CONFIG_NETCONSOLE is not set # CONFIG_NETPOLL is not set # CONFIG_NET_POLL_CONTROLLER is not set # CONFIG_ISDN is not set # CONFIG_PHONE is not set # # Input device support # CONFIG_INPUT=y # CONFIG_INPUT_FF_MEMLESS is not set # CONFIG_INPUT_POLLDEV is not set # # Userland interfaces # CONFIG_INPUT_MOUSEDEV=y CONFIG_INPUT_MOUSEDEV_PSAUX=y CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 # CONFIG_INPUT_JOYDEV is not set # CONFIG_INPUT_EVDEV is not set # CONFIG_INPUT_EVBUG is not set # # Input Device Drivers # CONFIG_INPUT_KEYBOARD=y CONFIG_KEYBOARD_ATKBD=y # CONFIG_KEYBOARD_SUNKBD is not set # CONFIG_KEYBOARD_LKKBD is not set # CONFIG_KEYBOARD_XTKBD is not set # CONFIG_KEYBOARD_NEWTON is not set # CONFIG_KEYBOARD_STOWAWAY is not set CONFIG_INPUT_MOUSE=y CONFIG_MOUSE_PS2=y CONFIG_MOUSE_PS2_ALPS=y CONFIG_MOUSE_PS2_LOGIPS2PP=y CONFIG_MOUSE_PS2_SYNAPTICS=y CONFIG_MOUSE_PS2_TRACKPOINT=y # CONFIG_MOUSE_PS2_ELANTECH is not set # CONFIG_MOUSE_PS2_TOUCHKIT is not set # CONFIG_MOUSE_SERIAL is not set # CONFIG_MOUSE_APPLETOUCH is not set # CONFIG_MOUSE_BCM5974 is not set # CONFIG_MOUSE_INPORT is not set # CONFIG_MOUSE_LOGIBM is not set # CONFIG_MOUSE_PC110PAD is not set # CONFIG_MOUSE_VSXXXAA is not set CONFIG_INPUT_JOYSTICK=y # CONFIG_JOYSTICK_ANALOG is not set # CONFIG_JOYSTICK_A3D is not set # CONFIG_JOYSTICK_ADI is not set # CONFIG_JOYSTICK_COBRA is not set # CONFIG_JOYSTICK_GF2K is not set # CONFIG_JOYSTICK_GRIP is not set # CONFIG_JOYSTICK_GRIP_MP is not set # CONFIG_JOYSTICK_GUILLEMOT is not set # CONFIG_JOYSTICK_INTERACT is not set # CONFIG_JOYSTICK_SIDEWINDER is not set # CONFIG_JOYSTICK_TMDC is not set # CONFIG_JOYSTICK_IFORCE is not set # CONFIG_JOYSTICK_WARRIOR is not set # CONFIG_JOYSTICK_MAGELLAN is not set # CONFIG_JOYSTICK_SPACEORB is not set # CONFIG_JOYSTICK_SPACEBALL is not set # CONFIG_JOYSTICK_STINGER is not set # CONFIG_JOYSTICK_TWIDJOY is not set # CONFIG_JOYSTICK_ZHENHUA is not set # CONFIG_JOYSTICK_JOYDUMP is not set # CONFIG_JOYSTICK_XPAD is not set # CONFIG_INPUT_TABLET is not set CONFIG_INPUT_TOUCHSCREEN=y # CONFIG_TOUCHSCREEN_AD7879 is not set # CONFIG_TOUCHSCREEN_FUJITSU is not set # CONFIG_TOUCHSCREEN_GUNZE is not set # CONFIG_TOUCHSCREEN_ELO is not set # CONFIG_TOUCHSCREEN_WACOM_W8001 is not set # CONFIG_TOUCHSCREEN_MTOUCH is not set # CONFIG_TOUCHSCREEN_INEXIO is not set # CONFIG_TOUCHSCREEN_MK712 is not set # CONFIG_TOUCHSCREEN_HTCPEN is not set # CONFIG_TOUCHSCREEN_PENMOUNT is not set # CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set # CONFIG_TOUCHSCREEN_TOUCHWIN is not set # CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set # CONFIG_TOUCHSCREEN_TOUCHIT213 is not set # CONFIG_TOUCHSCREEN_W90X900 is not set CONFIG_INPUT_MISC=y # CONFIG_INPUT_PCSPKR is not set # CONFIG_INPUT_ATI_REMOTE is not set # CONFIG_INPUT_ATI_REMOTE2 is not set # CONFIG_INPUT_KEYSPAN_REMOTE is not set # CONFIG_INPUT_POWERMATE is not set # CONFIG_INPUT_YEALINK is not set # CONFIG_INPUT_CM109 is not set # CONFIG_INPUT_UINPUT is not set # # Hardware I/O ports # CONFIG_SERIO=y # CONFIG_SERIO_I8042 is not set CONFIG_SERIO_SERPORT=y # CONFIG_SERIO_PCIPS2 is not set CONFIG_SERIO_LIBPS2=y # CONFIG_SERIO_RAW is not set # CONFIG_GAMEPORT is not set # # Character devices # CONFIG_VT=y CONFIG_CONSOLE_TRANSLATIONS=y CONFIG_VT_CONSOLE=y CONFIG_HW_CONSOLE=y # CONFIG_VT_HW_CONSOLE_BINDING is not set CONFIG_DEVKMEM=y CONFIG_SERIAL_NONSTANDARD=y # CONFIG_COMPUTONE is not set # CONFIG_ROCKETPORT is not set # CONFIG_CYCLADES is not set # CONFIG_DIGIEPCA is not set # CONFIG_MOXA_INTELLIO is not set # CONFIG_MOXA_SMARTIO is not set # CONFIG_ISI is not set # CONFIG_SYNCLINKMP is not set # CONFIG_SYNCLINK_GT is not set # CONFIG_N_HDLC is not set # CONFIG_RISCOM8 is not set # CONFIG_SPECIALIX is not set # CONFIG_SX is not set # CONFIG_RIO is not set # CONFIG_STALDRV is not set # CONFIG_NOZOMI is not set # # Serial drivers # CONFIG_SERIAL_8250=y CONFIG_SERIAL_8250_CONSOLE=y # CONFIG_SERIAL_8250_PCI is not set # CONFIG_SERIAL_8250_PNP is not set CONFIG_SERIAL_8250_NR_UARTS=16 CONFIG_SERIAL_8250_RUNTIME_UARTS=4 CONFIG_SERIAL_8250_EXTENDED=y CONFIG_SERIAL_8250_MANY_PORTS=y CONFIG_SERIAL_8250_FOURPORT=y # CONFIG_SERIAL_8250_ACCENT is not set # CONFIG_SERIAL_8250_BOCA is not set # CONFIG_SERIAL_8250_EXAR_ST16C554 is not set # CONFIG_SERIAL_8250_HUB6 is not set CONFIG_SERIAL_8250_SHARE_IRQ=y # CONFIG_SERIAL_8250_DETECT_IRQ is not set CONFIG_SERIAL_8250_RSA=y # # Non-8250 serial port support # CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y # CONFIG_SERIAL_JSM is not set CONFIG_UNIX98_PTYS=y CONFIG_DEVPTS_MULTIPLE_INSTANCES=y CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=16 # CONFIG_IPMI_HANDLER is not set CONFIG_HW_RANDOM=y # CONFIG_HW_RANDOM_TIMERIOMEM is not set # CONFIG_DTLK is not set # CONFIG_R3964 is not set # CONFIG_APPLICOM is not set # CONFIG_RAW_DRIVER is not set # CONFIG_TCG_TPM is not set CONFIG_DEVPORT=y # CONFIG_I2C is not set # CONFIG_SPI is not set # # PPS support # # CONFIG_PPS is not set # CONFIG_W1 is not set # CONFIG_POWER_SUPPLY is not set # CONFIG_HWMON is not set # CONFIG_THERMAL is not set # CONFIG_THERMAL_HWMON is not set CONFIG_WATCHDOG=y # CONFIG_WATCHDOG_NOWAYOUT is not set # # Watchdog Device Drivers # # CONFIG_SOFT_WATCHDOG is not set # CONFIG_ALIM7101_WDT is not set # # ISA-based Watchdog Cards # # CONFIG_PCWATCHDOG is not set # CONFIG_MIXCOMWD is not set # CONFIG_WDT is not set # # PCI-based Watchdog Cards # # CONFIG_PCIPCWATCHDOG is not set # CONFIG_WDTPCI is not set # # USB-based Watchdog Cards # # CONFIG_USBPCWATCHDOG is not set CONFIG_SSB_POSSIBLE=y # # Sonics Silicon Backplane # # CONFIG_SSB is not set # # Multifunction device drivers # # CONFIG_MFD_CORE is not set # CONFIG_MFD_SM501 is not set # CONFIG_HTC_PASIC3 is not set # CONFIG_MFD_TMIO is not set # CONFIG_REGULATOR is not set # CONFIG_MEDIA_SUPPORT is not set # # Graphics support # # CONFIG_DRM is not set # CONFIG_VGASTATE is not set # CONFIG_VIDEO_OUTPUT_CONTROL is not set CONFIG_FB=y # CONFIG_FIRMWARE_EDID is not set # CONFIG_FB_DDC is not set CONFIG_FB_BOOT_VESA_SUPPORT=y CONFIG_FB_CFB_FILLRECT=y CONFIG_FB_CFB_COPYAREA=y CONFIG_FB_CFB_IMAGEBLIT=y # CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set # CONFIG_FB_SYS_FILLRECT is not set # CONFIG_FB_SYS_COPYAREA is not set # CONFIG_FB_SYS_IMAGEBLIT is not set # CONFIG_FB_FOREIGN_ENDIAN is not set # CONFIG_FB_SYS_FOPS is not set # CONFIG_FB_SVGALIB is not set # CONFIG_FB_MACMODES is not set # CONFIG_FB_BACKLIGHT is not set # CONFIG_FB_MODE_HELPERS is not set # CONFIG_FB_TILEBLITTING is not set # # Frame buffer hardware drivers # # CONFIG_FB_CIRRUS is not set # CONFIG_FB_PM2 is not set # CONFIG_FB_CYBER2000 is not set # CONFIG_FB_ASILIANT is not set # CONFIG_FB_IMSTT is not set # CONFIG_FB_S1D13XXX is not set # CONFIG_FB_NVIDIA is not set # CONFIG_FB_RIVA is not set # CONFIG_FB_MATROX is not set # CONFIG_FB_RADEON is not set # CONFIG_FB_ATY128 is not set # CONFIG_FB_ATY is not set # CONFIG_FB_S3 is not set # CONFIG_FB_SAVAGE is not set CONFIG_FB_SIS=y # CONFIG_FB_SIS_300 is not set CONFIG_FB_SIS_315=y # CONFIG_FB_VIA is not set # CONFIG_FB_NEOMAGIC is not set # CONFIG_FB_KYRO is not set # CONFIG_FB_3DFX is not set # CONFIG_FB_VOODOO1 is not set # CONFIG_FB_VT8623 is not set # CONFIG_FB_TRIDENT is not set # CONFIG_FB_ARK is not set # CONFIG_FB_PM3 is not set # CONFIG_FB_CARMINE is not set # CONFIG_FB_VIRTUAL is not set # CONFIG_FB_METRONOME is not set # CONFIG_FB_MB862XX is not set # CONFIG_FB_BROADSHEET is not set CONFIG_BACKLIGHT_LCD_SUPPORT=y # CONFIG_LCD_CLASS_DEVICE is not set CONFIG_BACKLIGHT_CLASS_DEVICE=y CONFIG_BACKLIGHT_GENERIC=y # # Display device support # # CONFIG_DISPLAY_SUPPORT is not set # # Console display driver support # # CONFIG_VGA_CONSOLE is not set # CONFIG_MDA_CONSOLE is not set CONFIG_DUMMY_CONSOLE=y CONFIG_FRAMEBUFFER_CONSOLE=y # CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set # CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set # CONFIG_FONTS is not set CONFIG_FONT_8x8=y CONFIG_FONT_8x16=y # CONFIG_LOGO is not set # CONFIG_SOUND is not set CONFIG_HID_SUPPORT=y CONFIG_HID=y # CONFIG_HID_DEBUG is not set # CONFIG_HIDRAW is not set # # USB Input Devices # CONFIG_USB_HID=y # CONFIG_HID_PID is not set CONFIG_USB_HIDDEV=y # # Special HID drivers # # CONFIG_HID_A4TECH is not set # CONFIG_HID_APPLE is not set # CONFIG_HID_BELKIN is not set # CONFIG_HID_CHERRY is not set # CONFIG_HID_CHICONY is not set # CONFIG_HID_CYPRESS is not set # CONFIG_HID_DRAGONRISE is not set # CONFIG_HID_EZKEY is not set # CONFIG_HID_KYE is not set # CONFIG_HID_GYRATION is not set # CONFIG_HID_KENSINGTON is not set # CONFIG_HID_LOGITECH is not set # CONFIG_HID_MICROSOFT is not set # CONFIG_HID_MONTEREY is not set # CONFIG_HID_NTRIG is not set # CONFIG_HID_PANTHERLORD is not set # CONFIG_HID_PETALYNX is not set # CONFIG_HID_SAMSUNG is not set # CONFIG_HID_SONY is not set # CONFIG_HID_SUNPLUS is not set # CONFIG_HID_GREENASIA is not set # CONFIG_HID_SMARTJOYPLUS is not set # CONFIG_HID_TOPSEED is not set # CONFIG_HID_THRUSTMASTER is not set # CONFIG_HID_ZEROPLUS is not set CONFIG_USB_SUPPORT=y CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB_ARCH_HAS_OHCI=y CONFIG_USB_ARCH_HAS_EHCI=y CONFIG_USB=y # CONFIG_USB_DEBUG is not set # CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set # # Miscellaneous USB options # CONFIG_USB_DEVICEFS=y # CONFIG_USB_DEVICE_CLASS is not set # CONFIG_USB_DYNAMIC_MINORS is not set # CONFIG_USB_SUSPEND is not set # CONFIG_USB_OTG is not set # CONFIG_USB_OTG_WHITELIST is not set # CONFIG_USB_OTG_BLACKLIST_HUB is not set CONFIG_USB_MON=y # CONFIG_USB_WUSB is not set # CONFIG_USB_WUSB_CBAF is not set # # USB Host Controller Drivers # # CONFIG_USB_C67X00_HCD is not set # CONFIG_USB_XHCI_HCD is not set CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_ROOT_HUB_TT=y # CONFIG_USB_EHCI_TT_NEWSCHED is not set # CONFIG_USB_OXU210HP_HCD is not set # CONFIG_USB_ISP116X_HCD is not set # CONFIG_USB_ISP1760_HCD is not set CONFIG_USB_OHCI_HCD=y # CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set # CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set CONFIG_USB_OHCI_LITTLE_ENDIAN=y # CONFIG_USB_UHCI_HCD is not set # CONFIG_USB_SL811_HCD is not set # CONFIG_USB_R8A66597_HCD is not set # CONFIG_USB_WHCI_HCD is not set # CONFIG_USB_HWA_HCD is not set # # USB Device Class drivers # # CONFIG_USB_ACM is not set # CONFIG_USB_PRINTER is not set # CONFIG_USB_WDM is not set # CONFIG_USB_TMC is not set # # NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may # # # also be needed; see USB_STORAGE Help for more info # CONFIG_USB_STORAGE=y # CONFIG_USB_STORAGE_DEBUG is not set CONFIG_USB_STORAGE_DATAFAB=y CONFIG_USB_STORAGE_FREECOM=y CONFIG_USB_STORAGE_ISD200=y CONFIG_USB_STORAGE_USBAT=y CONFIG_USB_STORAGE_SDDR09=y CONFIG_USB_STORAGE_SDDR55=y CONFIG_USB_STORAGE_JUMPSHOT=y CONFIG_USB_STORAGE_ALAUDA=y # CONFIG_USB_STORAGE_ONETOUCH is not set # CONFIG_USB_STORAGE_KARMA is not set # CONFIG_USB_STORAGE_CYPRESS_ATACB is not set # CONFIG_USB_LIBUSUAL is not set # # USB Imaging devices # # CONFIG_USB_MDC800 is not set # CONFIG_USB_MICROTEK is not set # # USB port drivers # # CONFIG_USB_SERIAL is not set # # USB Miscellaneous drivers # # CONFIG_USB_EMI62 is not set # CONFIG_USB_EMI26 is not set # CONFIG_USB_ADUTUX is not set # CONFIG_USB_SEVSEG is not set # CONFIG_USB_RIO500 is not set # CONFIG_USB_LEGOTOWER is not set # CONFIG_USB_LCD is not set # CONFIG_USB_BERRY_CHARGE is not set # CONFIG_USB_LED is not set # CONFIG_USB_CYPRESS_CY7C63 is not set # CONFIG_USB_CYTHERM is not set # CONFIG_USB_IDMOUSE is not set # CONFIG_USB_FTDI_ELAN is not set # CONFIG_USB_APPLEDISPLAY is not set # CONFIG_USB_SISUSBVGA is not set # CONFIG_USB_LD is not set # CONFIG_USB_TRANCEVIBRATOR is not set # CONFIG_USB_IOWARRIOR is not set # CONFIG_USB_TEST is not set # CONFIG_USB_ISIGHTFW is not set # CONFIG_USB_VST is not set # CONFIG_USB_ATM is not set # CONFIG_USB_GADGET is not set # # OTG and related infrastructure # # CONFIG_NOP_USB_XCEIV is not set # CONFIG_UWB is not set # CONFIG_MMC is not set # CONFIG_MEMSTICK is not set # CONFIG_NEW_LEDS is not set # CONFIG_ACCESSIBILITY is not set # CONFIG_INFINIBAND is not set CONFIG_RTC_LIB=y CONFIG_RTC_CLASS=y CONFIG_RTC_HCTOSYS=y CONFIG_RTC_HCTOSYS_DEVICE="rtc" # CONFIG_RTC_DEBUG is not set # # RTC interfaces # CONFIG_RTC_INTF_SYSFS=y CONFIG_RTC_INTF_PROC=y CONFIG_RTC_INTF_DEV=y # CONFIG_RTC_INTF_DEV_UIE_EMUL is not set # CONFIG_RTC_DRV_TEST is not set # # SPI RTC drivers # # # Platform RTC drivers # CONFIG_RTC_DRV_CMOS=y # CONFIG_RTC_DRV_DS1286 is not set # CONFIG_RTC_DRV_DS1511 is not set # CONFIG_RTC_DRV_DS1553 is not set # CONFIG_RTC_DRV_DS1742 is not set # CONFIG_RTC_DRV_STK17TA8 is not set # CONFIG_RTC_DRV_M48T86 is not set # CONFIG_RTC_DRV_M48T35 is not set # CONFIG_RTC_DRV_M48T59 is not set # CONFIG_RTC_DRV_BQ4802 is not set # CONFIG_RTC_DRV_V3020 is not set # # on-CPU RTC drivers # # CONFIG_DMADEVICES is not set # CONFIG_AUXDISPLAY is not set # CONFIG_UIO is not set # # TI VLYNQ # # CONFIG_STAGING is not set # # File systems # CONFIG_EXT2_FS=y CONFIG_EXT2_FS_XATTR=y CONFIG_EXT2_FS_POSIX_ACL=y CONFIG_EXT2_FS_SECURITY=y # CONFIG_EXT2_FS_XIP is not set CONFIG_EXT3_FS=y # CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set CONFIG_EXT3_FS_XATTR=y CONFIG_EXT3_FS_POSIX_ACL=y CONFIG_EXT3_FS_SECURITY=y # CONFIG_EXT4_FS is not set CONFIG_JBD=y # CONFIG_JBD_DEBUG is not set CONFIG_FS_MBCACHE=y # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set CONFIG_FS_POSIX_ACL=y # CONFIG_XFS_FS is not set # CONFIG_GFS2_FS is not set # CONFIG_OCFS2_FS is not set # CONFIG_BTRFS_FS is not set CONFIG_FILE_LOCKING=y CONFIG_FSNOTIFY=y CONFIG_DNOTIFY=y CONFIG_INOTIFY=y CONFIG_INOTIFY_USER=y CONFIG_QUOTA=y # CONFIG_QUOTA_NETLINK_INTERFACE is not set CONFIG_PRINT_QUOTA_WARNING=y # CONFIG_QFMT_V1 is not set # CONFIG_QFMT_V2 is not set CONFIG_QUOTACTL=y # CONFIG_AUTOFS_FS is not set # CONFIG_AUTOFS4_FS is not set # CONFIG_FUSE_FS is not set # # Caches # # CONFIG_FSCACHE is not set # # CD-ROM/DVD Filesystems # # CONFIG_ISO9660_FS is not set # CONFIG_UDF_FS is not set # # DOS/FAT/NT Filesystems # # CONFIG_MSDOS_FS is not set # CONFIG_VFAT_FS is not set # CONFIG_NTFS_FS is not set # # Pseudo filesystems # CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_PROC_SYSCTL=y CONFIG_PROC_PAGE_MONITOR=y CONFIG_SYSFS=y CONFIG_TMPFS=y # CONFIG_TMPFS_POSIX_ACL is not set # CONFIG_HUGETLB_PAGE is not set # CONFIG_CONFIGFS_FS is not set CONFIG_MISC_FILESYSTEMS=y # CONFIG_ADFS_FS is not set # CONFIG_AFFS_FS is not set # CONFIG_ECRYPT_FS is not set # CONFIG_HFS_FS is not set # CONFIG_HFSPLUS_FS is not set # CONFIG_BEFS_FS is not set # CONFIG_BFS_FS is not set # CONFIG_EFS_FS is not set CONFIG_CRAMFS=y # CONFIG_SQUASHFS is not set # CONFIG_VXFS_FS is not set # CONFIG_MINIX_FS is not set # CONFIG_OMFS_FS is not set # CONFIG_HPFS_FS is not set # CONFIG_QNX4FS_FS is not set # CONFIG_ROMFS_FS is not set # CONFIG_SYSV_FS is not set # CONFIG_UFS_FS is not set # CONFIG_NILFS2_FS is not set CONFIG_NETWORK_FILESYSTEMS=y # CONFIG_NFS_FS is not set # CONFIG_NFSD is not set # CONFIG_SMB_FS is not set # CONFIG_CIFS is not set # CONFIG_NCP_FS is not set # CONFIG_CODA_FS is not set # CONFIG_AFS_FS is not set # # Partition Types # CONFIG_PARTITION_ADVANCED=y CONFIG_ACORN_PARTITION=y # CONFIG_ACORN_PARTITION_CUMANA is not set # CONFIG_ACORN_PARTITION_EESOX is not set CONFIG_ACORN_PARTITION_ICS=y # CONFIG_ACORN_PARTITION_ADFS is not set # CONFIG_ACORN_PARTITION_POWERTEC is not set CONFIG_ACORN_PARTITION_RISCIX=y CONFIG_OSF_PARTITION=y CONFIG_AMIGA_PARTITION=y CONFIG_ATARI_PARTITION=y CONFIG_MAC_PARTITION=y CONFIG_MSDOS_PARTITION=y CONFIG_BSD_DISKLABEL=y CONFIG_MINIX_SUBPARTITION=y CONFIG_SOLARIS_X86_PARTITION=y CONFIG_UNIXWARE_DISKLABEL=y CONFIG_LDM_PARTITION=y # CONFIG_LDM_DEBUG is not set CONFIG_SGI_PARTITION=y CONFIG_ULTRIX_PARTITION=y CONFIG_SUN_PARTITION=y CONFIG_KARMA_PARTITION=y CONFIG_EFI_PARTITION=y # CONFIG_SYSV68_PARTITION is not set CONFIG_NLS=y CONFIG_NLS_DEFAULT="iso8859-1" # CONFIG_NLS_CODEPAGE_437 is not set # CONFIG_NLS_CODEPAGE_737 is not set # CONFIG_NLS_CODEPAGE_775 is not set # CONFIG_NLS_CODEPAGE_850 is not set # CONFIG_NLS_CODEPAGE_852 is not set # CONFIG_NLS_CODEPAGE_855 is not set # CONFIG_NLS_CODEPAGE_857 is not set # CONFIG_NLS_CODEPAGE_860 is not set # CONFIG_NLS_CODEPAGE_861 is not set # CONFIG_NLS_CODEPAGE_862 is not set # CONFIG_NLS_CODEPAGE_863 is not set # CONFIG_NLS_CODEPAGE_864 is not set # CONFIG_NLS_CODEPAGE_865 is not set # CONFIG_NLS_CODEPAGE_866 is not set # CONFIG_NLS_CODEPAGE_869 is not set # CONFIG_NLS_CODEPAGE_936 is not set # CONFIG_NLS_CODEPAGE_950 is not set # CONFIG_NLS_CODEPAGE_932 is not set # CONFIG_NLS_CODEPAGE_949 is not set # CONFIG_NLS_CODEPAGE_874 is not set # CONFIG_NLS_ISO8859_8 is not set # CONFIG_NLS_CODEPAGE_1250 is not set # CONFIG_NLS_CODEPAGE_1251 is not set # CONFIG_NLS_ASCII is not set # CONFIG_NLS_ISO8859_1 is not set # CONFIG_NLS_ISO8859_2 is not set # CONFIG_NLS_ISO8859_3 is not set # CONFIG_NLS_ISO8859_4 is not set # CONFIG_NLS_ISO8859_5 is not set # CONFIG_NLS_ISO8859_6 is not set # CONFIG_NLS_ISO8859_7 is not set # CONFIG_NLS_ISO8859_9 is not set # CONFIG_NLS_ISO8859_13 is not set # CONFIG_NLS_ISO8859_14 is not set # CONFIG_NLS_ISO8859_15 is not set # CONFIG_NLS_KOI8_R is not set # CONFIG_NLS_KOI8_U is not set # CONFIG_NLS_UTF8 is not set # CONFIG_DLM is not set # # Kernel hacking # CONFIG_TRACE_IRQFLAGS_SUPPORT=y # CONFIG_PRINTK_TIME is not set CONFIG_ENABLE_WARN_DEPRECATED=y CONFIG_ENABLE_MUST_CHECK=y CONFIG_FRAME_WARN=1024 CONFIG_MAGIC_SYSRQ=y CONFIG_UNUSED_SYMBOLS=y CONFIG_DEBUG_FS=y # CONFIG_HEADERS_CHECK is not set # CONFIG_DEBUG_KERNEL is not set # CONFIG_DEBUG_MEMORY_INIT is not set # CONFIG_RCU_CPU_STALL_DETECTOR is not set CONFIG_SYSCTL_SYSCALL_CHECK=y CONFIG_TRACING_SUPPORT=y # CONFIG_FTRACE is not set # CONFIG_DYNAMIC_DEBUG is not set # CONFIG_SAMPLES is not set CONFIG_HAVE_ARCH_KGDB=y CONFIG_CMDLINE="" # # Security options # CONFIG_KEYS=y # CONFIG_KEYS_DEBUG_PROC_KEYS is not set CONFIG_SECURITY=y # CONFIG_SECURITYFS is not set CONFIG_SECURITY_NETWORK=y CONFIG_SECURITY_NETWORK_XFRM=y # CONFIG_SECURITY_PATH is not set # CONFIG_SECURITY_FILE_CAPABILITIES is not set # CONFIG_SECURITY_ROOTPLUG is not set CONFIG_SECURITY_SELINUX=y CONFIG_SECURITY_SELINUX_BOOTPARAM=y CONFIG_SECURITY_SELINUX_BOOTPARAM_VALUE=0 CONFIG_SECURITY_SELINUX_DISABLE=y CONFIG_SECURITY_SELINUX_DEVELOP=y CONFIG_SECURITY_SELINUX_AVC_STATS=y CONFIG_SECURITY_SELINUX_CHECKREQPROT_VALUE=1 # CONFIG_SECURITY_SELINUX_POLICYDB_VERSION_MAX is not set # CONFIG_SECURITY_TOMOYO is not set CONFIG_CRYPTO=y # # Crypto core or helper # # CONFIG_CRYPTO_FIPS is not set CONFIG_CRYPTO_ALGAPI=y CONFIG_CRYPTO_ALGAPI2=y CONFIG_CRYPTO_AEAD2=y CONFIG_CRYPTO_BLKCIPHER=y CONFIG_CRYPTO_BLKCIPHER2=y CONFIG_CRYPTO_HASH=y CONFIG_CRYPTO_HASH2=y CONFIG_CRYPTO_RNG2=y CONFIG_CRYPTO_PCOMP=y CONFIG_CRYPTO_MANAGER=y CONFIG_CRYPTO_MANAGER2=y # CONFIG_CRYPTO_GF128MUL is not set # CONFIG_CRYPTO_NULL is not set CONFIG_CRYPTO_WORKQUEUE=y # CONFIG_CRYPTO_CRYPTD is not set # CONFIG_CRYPTO_AUTHENC is not set # CONFIG_CRYPTO_TEST is not set # # Authenticated Encryption with Associated Data # # CONFIG_CRYPTO_CCM is not set # CONFIG_CRYPTO_GCM is not set # CONFIG_CRYPTO_SEQIV is not set # # Block modes # CONFIG_CRYPTO_CBC=y # CONFIG_CRYPTO_CTR is not set # CONFIG_CRYPTO_CTS is not set # CONFIG_CRYPTO_ECB is not set # CONFIG_CRYPTO_LRW is not set # CONFIG_CRYPTO_PCBC is not set # CONFIG_CRYPTO_XTS is not set # # Hash modes # CONFIG_CRYPTO_HMAC=y # CONFIG_CRYPTO_XCBC is not set # # Digest # # CONFIG_CRYPTO_CRC32C is not set # CONFIG_CRYPTO_MD4 is not set CONFIG_CRYPTO_MD5=y # CONFIG_CRYPTO_MICHAEL_MIC is not set # CONFIG_CRYPTO_RMD128 is not set # CONFIG_CRYPTO_RMD160 is not set # CONFIG_CRYPTO_RMD256 is not set # CONFIG_CRYPTO_RMD320 is not set # CONFIG_CRYPTO_SHA1 is not set # CONFIG_CRYPTO_SHA256 is not set # CONFIG_CRYPTO_SHA512 is not set # CONFIG_CRYPTO_TGR192 is not set # CONFIG_CRYPTO_WP512 is not set # # Ciphers # # CONFIG_CRYPTO_AES is not set # CONFIG_CRYPTO_ANUBIS is not set # CONFIG_CRYPTO_ARC4 is not set # CONFIG_CRYPTO_BLOWFISH is not set # CONFIG_CRYPTO_CAMELLIA is not set # CONFIG_CRYPTO_CAST5 is not set # CONFIG_CRYPTO_CAST6 is not set # CONFIG_CRYPTO_DES is not set # CONFIG_CRYPTO_FCRYPT is not set # CONFIG_CRYPTO_KHAZAD is not set # CONFIG_CRYPTO_SALSA20 is not set # CONFIG_CRYPTO_SEED is not set # CONFIG_CRYPTO_SERPENT is not set # CONFIG_CRYPTO_TEA is not set # CONFIG_CRYPTO_TWOFISH is not set # # Compression # # CONFIG_CRYPTO_DEFLATE is not set # CONFIG_CRYPTO_ZLIB is not set # CONFIG_CRYPTO_LZO is not set # # Random Number Generation # # CONFIG_CRYPTO_ANSI_CPRNG is not set CONFIG_CRYPTO_HW=y # CONFIG_CRYPTO_DEV_HIFN_795X is not set # CONFIG_BINARY_PRINTF is not set # # Library routines # CONFIG_BITREVERSE=y CONFIG_GENERIC_FIND_LAST_BIT=y # CONFIG_CRC_CCITT is not set # CONFIG_CRC16 is not set # CONFIG_CRC_T10DIF is not set # CONFIG_CRC_ITU_T is not set CONFIG_CRC32=y # CONFIG_CRC7 is not set # CONFIG_LIBCRC32C is not set CONFIG_AUDIT_GENERIC=y CONFIG_ZLIB_INFLATE=y CONFIG_DECOMPRESS_GZIP=y CONFIG_HAS_IOMEM=y CONFIG_HAS_IOPORT=y CONFIG_HAS_DMA=y CONFIG_NLATTR=y --=-ijWKSaVugkZli3X1t1ni-- From alex@digriz.org.uk Sun Jul 5 13:07:31 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 05 Jul 2009 13:07:38 +0200 (CEST) Received: from woodchuck.wormnet.eu ([77.75.105.223]:55592 "EHLO woodchuck.wormnet.eu" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1491772AbZGELHb (ORCPT ); Sun, 5 Jul 2009 13:07:31 +0200 Received: by woodchuck.wormnet.eu (Postfix, from userid 1000) id CAE4B35D459; Sun, 5 Jul 2009 12:00:55 +0100 (BST) Date: Sun, 5 Jul 2009 12:00:55 +0100 From: Alexander Clouter To: linux-mips@vger.kernel.org, linux-mips@linux-mips.org Cc: tanderson@mvista.com Subject: [PATCH] kernel: fix MIPS compile for !CONFIG_SMP Message-ID: <20090705110055.GO2014@woodchuck> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Organization: diGriz X-URL: http://www.digriz.org.uk/ X-JabberID: alex@digriz.org.uk User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23646 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: alex@digriz.org.uk Precedence: bulk X-list: linux-mips Commit fc03bc1715ca0ad4ccfe97aab16bcc9e7129c1a4 breaks compiling MIPS with SMP disabled. This patch fixes that. Signed-off-by: Alexander Clouter --- arch/mips/include/asm/gic.h | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/mips/include/asm/gic.h b/arch/mips/include/asm/gic.h index 10292e3..a8f5734 100644 --- a/arch/mips/include/asm/gic.h +++ b/arch/mips/include/asm/gic.h @@ -20,7 +20,7 @@ #define GIC_TRIG_EDGE 1 #define GIC_TRIG_LEVEL 0 -#if CONFIG_SMP +#ifdef CONFIG_SMP #define GIC_NUM_INTRS (24 + NR_CPUS * 2) #else #define GIC_NUM_INTRS 32 -- 1.6.3.3 From f.fainelli@gmail.com Sun Jul 5 13:16:51 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 05 Jul 2009 13:16:58 +0200 (CEST) Received: from mail-ew0-f214.google.com ([209.85.219.214]:65325 "EHLO mail-ew0-f214.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1491772AbZGELQv convert rfc822-to-8bit (ORCPT ); Sun, 5 Jul 2009 13:16:51 +0200 Received: by ewy10 with SMTP id 10so3893236ewy.0 for ; Sun, 05 Jul 2009 04:10:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:sender:from:to:subject:date :user-agent:cc:references:in-reply-to:mime-version:content-type :content-transfer-encoding:content-disposition:message-id; bh=EhmqvfeDlpNm20PykHxQTyCJgtpUG67yJm0GNCCUE7o=; b=tMX7BzlpXMrMZv3mT5AeWtbZd5UxBvOoAHSRooqZSgL83VX1xMTkRLhoCZwcg+K9ag 6LSXtdNlbPmcJt6xwHthjAYjCfesaq8NF9aeZpOUKlLSZOzHC3lfs9y07JLg6uNoFJD2 LraaBgfaSoYz6uGcakMs1jo931xuLhV6ssQu0= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:from:to:subject:date:user-agent:cc:references:in-reply-to :mime-version:content-type:content-transfer-encoding :content-disposition:message-id; b=R3i4ZjmU3eYgkuTBbjm0tTiOuDby66LObxSwDNaVjrFRKxf1PjPYbVM1B//Y8Dz/LE jfb+uQ4QoCltnGUsNUDe3NdB6jrFeAZCq4gZPO62Wjrpa7GjGUidQEWAgwtoYUsqpGLi hfm5nm6J7+ivOWDsAmVS3oULrq0U/cMkCWZ8M= Received: by 10.210.81.9 with SMTP id e9mr3393726ebb.68.1246792211285; Sun, 05 Jul 2009 04:10:11 -0700 (PDT) Received: from lenovo.mimichou.home (home.mimichou.net [82.67.132.19]) by mx.google.com with ESMTPS id 28sm8287505eye.16.2009.07.05.04.10.06 (version=TLSv1/SSLv3 cipher=RC4-MD5); Sun, 05 Jul 2009 04:10:07 -0700 (PDT) From: Florian Fainelli To: Martin Michlmayr Subject: Re: mtd related Cobalt build failure with current git Date: Sun, 5 Jul 2009 13:10:01 +0200 User-Agent: KMail/1.9.9 Cc: Yoichi Yuasa , linux-mips@linux-mips.org, dwmw2@infradead.org References: <20090704213741.GA6438@deprecation.cyrius.com> In-Reply-To: <20090704213741.GA6438@deprecation.cyrius.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8BIT Content-Disposition: inline Message-Id: <200907051310.02673.florian@openwrt.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23647 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips Hi Martin, Le Saturday 04 July 2009 23:37:41 Martin Michlmayr, vous avez écrit : > I get the following Cobalt build failure with current git: > > CC arch/mips/cobalt/mtd.o > cc1: warnings being treated as errors > In file included from arch/mips/cobalt/mtd.c:22: > include/linux/mtd/partitions.h:50: warning: ‘struct mtd_info’ declared > inside parameter list include/linux/mtd/partitions.h:50: warning: its scope > is only this definition or declaration, which is probably not what you want > include/linux/mtd/partitions.h:51: warning: ‘struct mtd_info’ declared > inside parameter list include/linux/mtd/partitions.h:61: warning: ‘struct > mtd_info’ declared inside parameter list include/linux/mtd/partitions.h:67: > warning: ‘struct mtd_info’ declared inside parameter list make[1]: *** > [arch/mips/cobalt/mtd.o] Error 1 > make: *** [arch/mips/cobalt] Error 2 > > Does anyone know if there's a fix for this already? I also had that problem and did the following fix, which still applies to the mtd-2.6 tree, master branch. -- From: Florian Fainelli Subject: [PATCH] Fix arch/mips/cobalt/mtd.c build failure This patch fixes a warning in include/linux/mtd/partitions which results in the following build failure on MIPS: CC arch/mips/cobalt/mtd.o cc1: warnings being treated as errors In file included from arch/mips/cobalt/mtd.c:22: include/linux/mtd/partitions.h:50: warning: 'struct mtd_info' declared inside parameter list include/linux/mtd/partitions.h:50: warning: its scope is only this definition or declaration, which is probably not what you want include/linux/mtd/partitions.h:51: warning: 'struct mtd_info' declared inside parameter list include/linux/mtd/partitions.h:61: warning: 'struct mtd_info' declared inside parameter list include/linux/mtd/partitions.h:67: warning: 'struct mtd_info' declared inside parameter list make[1]: *** [arch/mips/cobalt/mtd.o] Error 1 make: *** [arch/mips/cobalt] Error 2 Reported-by: Martin Michlmayr Signed-off-by: Florian Fainelli --- diff --git a/include/linux/mtd/partitions.h b/include/linux/mtd/partitions.h index af6dcb9..c8eaf44 100644 --- a/include/linux/mtd/partitions.h +++ b/include/linux/mtd/partitions.h @@ -10,7 +10,7 @@ #define MTD_PARTITIONS_H #include - +#include /* * Partition definition structure: From torvalds@linux-foundation.org Sun Jul 5 16:26:38 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 05 Jul 2009 16:26:45 +0200 (CEST) Received: from smtp1.linux-foundation.org ([140.211.169.13]:33639 "EHLO smtp1.linux-foundation.org" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492028AbZGEO0i (ORCPT ); Sun, 5 Jul 2009 16:26:38 +0200 Received: from imap1.linux-foundation.org (imap1.linux-foundation.org [140.211.169.55]) by smtp1.linux-foundation.org (8.14.2/8.13.5/Debian-3ubuntu1.1) with ESMTP id n65EJaKw026611 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Sun, 5 Jul 2009 07:19:38 -0700 Received: from localhost (localhost [127.0.0.1]) by imap1.linux-foundation.org (8.13.5.20060308/8.13.5/Debian-3ubuntu1.1) with ESMTP id n65EJXbA003368; Sun, 5 Jul 2009 07:19:33 -0700 Date: Sun, 5 Jul 2009 07:19:33 -0700 (PDT) From: Linus Torvalds X-X-Sender: torvalds@localhost.localdomain To: Wu Zhangjin cc: linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mips@linux-mips.org, Krzysztof Helt , Peter Zijlstra , "Rafael J. Wysocki" , Andrew Morton , Ralf Baechle , =?GB2312?B?6sy7qg==?= , zhangfx Subject: Re: [BUG] drivers/video/sis: deadlock introduced by "fbdev: add mutex for fb_mmap locking" In-Reply-To: <1246785112.14240.34.camel@falcon> Message-ID: References: <1246785112.14240.34.camel@falcon> User-Agent: Alpine 2.01 (LFD 1184 2008-12-16) MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII X-MIMEDefang-Filter: lf$Revision: 1.188 $ X-Scanned-By: MIMEDefang 2.63 on 140.211.169.13 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23648 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: torvalds@linux-foundation.org Precedence: bulk X-list: linux-mips On Sun, 5 Jul 2009, Wu Zhangjin wrote: > > then it works! so, I guess there is a deadlock introduced by the above > commit. Hmm. Perhaps more likely, the 'mm_lock' mutex hasn't even been initialized yet. We appear to have had that problem with matroxfb and sm501fb, and it may be more common than that. See commit f50bf2b2. That said, I do agree that the mm_lock seems to be causing more problems than it actually fixes, and maybe we should revert it. Krzysztof? Linus From lethal@linux-sh.org Sun Jul 5 16:58:56 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 05 Jul 2009 16:59:03 +0200 (CEST) Received: from 124x34x33x190.ap124.ftth.ucom.ne.jp ([124.34.33.190]:35189 "EHLO master.linux-sh.org" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492015AbZGEO64 (ORCPT ); Sun, 5 Jul 2009 16:58:56 +0200 Received: from localhost (unknown [127.0.0.1]) by master.linux-sh.org (Postfix) with ESMTP id 8F3CF63754; Sun, 5 Jul 2009 14:52:04 +0000 (UTC) X-Virus-Scanned: amavisd-new at linux-sh.org Received: from master.linux-sh.org ([127.0.0.1]) by localhost (master.linux-sh.org [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id qJ1GNXIrQL9h; Sun, 5 Jul 2009 23:52:04 +0900 (JST) Received: by master.linux-sh.org (Postfix, from userid 500) id 2612763758; Sun, 5 Jul 2009 23:52:04 +0900 (JST) Date: Sun, 5 Jul 2009 23:52:03 +0900 From: Paul Mundt To: Linus Torvalds Cc: Wu Zhangjin , linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mips@linux-mips.org, Krzysztof Helt , Peter Zijlstra , "Rafael J. Wysocki" , Andrew Morton , Ralf Baechle , ???? , zhangfx Subject: Re: [BUG] drivers/video/sis: deadlock introduced by "fbdev: add mutex for fb_mmap locking" Message-ID: <20090705145203.GA8326@linux-sh.org> Mail-Followup-To: Paul Mundt , Linus Torvalds , Wu Zhangjin , linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mips@linux-mips.org, Krzysztof Helt , Peter Zijlstra , "Rafael J. Wysocki" , Andrew Morton , Ralf Baechle , ???? , zhangfx References: <1246785112.14240.34.camel@falcon> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.13 (2006-08-11) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23649 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: lethal@linux-sh.org Precedence: bulk X-list: linux-mips On Sun, Jul 05, 2009 at 07:19:33AM -0700, Linus Torvalds wrote: > > > On Sun, 5 Jul 2009, Wu Zhangjin wrote: > > > > then it works! so, I guess there is a deadlock introduced by the above > > commit. > > Hmm. Perhaps more likely, the 'mm_lock' mutex hasn't even been initialized > yet. We appear to have had that problem with matroxfb and sm501fb, and it > may be more common than that. See commit f50bf2b2. > > That said, I do agree that the mm_lock seems to be causing more problems > than it actually fixes, and maybe we should revert it. Krzysztof? > Looking at this a bit closer, just moving the mutex initialization in to framebuffer_alloc() should basically fix most of these, at least it certainly does for sm501fb and for this sis case as well. So, here's a patch to do that. As an aside note, matroxfb is the odd one out, as it doesn't use framebuffer_alloc() directly for whatever reason. This actually raises an additional issue, in that framebuffer_alloc() is already where other mutexes are initialized, which will simply never happen on matroxfb (suggesting that at least the FB_BACKLIGHT and matroxfb combination will blow up, although perhaps that's not a valid combination). Signed-off-by: Paul Mundt --- drivers/video/fbmem.c | 1 - drivers/video/fbsysfs.c | 2 ++ 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/video/fbmem.c b/drivers/video/fbmem.c index 53ea056..27a5271 100644 --- a/drivers/video/fbmem.c +++ b/drivers/video/fbmem.c @@ -1514,7 +1514,6 @@ register_framebuffer(struct fb_info *fb_info) break; fb_info->node = i; mutex_init(&fb_info->lock); - mutex_init(&fb_info->mm_lock); fb_info->dev = device_create(fb_class, fb_info->device, MKDEV(FB_MAJOR, i), NULL, "fb%d", i); diff --git a/drivers/video/fbsysfs.c b/drivers/video/fbsysfs.c index d4a2c11..dd413ad 100644 --- a/drivers/video/fbsysfs.c +++ b/drivers/video/fbsysfs.c @@ -62,6 +62,8 @@ struct fb_info *framebuffer_alloc(size_t size, struct device *dev) mutex_init(&info->bl_curve_mutex); #endif + mutex_init(&info->mm_lock); + return info; #undef PADDING #undef BYTES_PER_LONG From krzysztof.h1@poczta.fm Sun Jul 5 17:03:02 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 05 Jul 2009 17:03:08 +0200 (CEST) Received: from smtp239.poczta.interia.pl ([217.74.64.239]:33350 "EHLO smtp239.poczta.interia.pl" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492015AbZGEPDB (ORCPT ); Sun, 5 Jul 2009 17:03:01 +0200 Received: by smtp239.poczta.interia.pl (INTERIA.PL, from userid 502) id 5D52842FEEC; Sun, 5 Jul 2009 16:56:24 +0200 (CEST) Received: from poczta.interia.pl (mi02.poczta.interia.pl [10.217.12.2]) by smtp239.poczta.interia.pl (INTERIA.PL) with ESMTP id 80B8442FF22; Sun, 5 Jul 2009 16:56:21 +0200 (CEST) Received: by poczta.interia.pl (INTERIA.PL, from userid 502) id E936B2BC510; Sun, 5 Jul 2009 16:56:20 +0200 (CEST) Received: from krzysio.net (93-181-133-4.as.kn.pl [93.181.133.4]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by www.poczta.fm (INTERIA.PL) with ESMTP id 60E082BC3CB; Sun, 5 Jul 2009 16:56:08 +0200 (CEST) Date: Sun, 5 Jul 2009 17:05:47 +0200 From: Krzysztof Helt To: Linus Torvalds Cc: Wu Zhangjin , linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mips@linux-mips.org, Krzysztof Helt , Peter Zijlstra , "Rafael J. Wysocki" , Andrew Morton , Ralf Baechle , =?UTF-8?Q?=E6=99=8F=E5=8D=8E?= , zhangfx Subject: Re: [BUG] drivers/video/sis: deadlock introduced by "fbdev: add mutex for fb_mmap locking" Message-Id: <20090705170547.c83f1cb9.krzysztof.h1@poczta.fm> In-Reply-To: References: <1246785112.14240.34.camel@falcon> X-Mailer: Sylpheed 2.4.3 (GTK+ 2.11.0; i686-pc-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-EMID: e6e2b138 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23650 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: krzysztof.h1@poczta.fm Precedence: bulk X-list: linux-mips On Sun, 5 Jul 2009 07:19:33 -0700 (PDT) Linus Torvalds wrote: > > > On Sun, 5 Jul 2009, Wu Zhangjin wrote: > > > > then it works! so, I guess there is a deadlock introduced by the above > > commit. > > Hmm. Perhaps more likely, the 'mm_lock' mutex hasn't even been initialized > yet. We appear to have had that problem with matroxfb and sm501fb, and it > may be more common than that. See commit f50bf2b2. > > That said, I do agree that the mm_lock seems to be causing more problems > than it actually fixes, and maybe we should revert it. Krzysztof? > I vote for fixing these drivers after my change. I will send a patch for the sis driver soon. I am building new kernel now. Regards, Krzysztof ---------------------------------------------------------------------- Rozwiaz krzyzowke i wygraj nagrody! Sprawdz >> http://link.interia.pl/f2232 From torvalds@linux-foundation.org Sun Jul 5 17:03:52 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 05 Jul 2009 17:03:58 +0200 (CEST) Received: from smtp1.linux-foundation.org ([140.211.169.13]:55773 "EHLO smtp1.linux-foundation.org" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S1492015AbZGEPDw (ORCPT ); Sun, 5 Jul 2009 17:03:52 +0200 Received: from imap1.linux-foundation.org (imap1.linux-foundation.org [140.211.169.55]) by smtp1.linux-foundation.org (8.14.2/8.13.5/Debian-3ubuntu1.1) with ESMTP id n65EuvXm029066 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Sun, 5 Jul 2009 07:56:58 -0700 Received: from localhost (localhost [127.0.0.1]) by imap1.linux-foundation.org (8.13.5.20060308/8.13.5/Debian-3ubuntu1.1) with ESMTP id n65EuuON013723; Sun, 5 Jul 2009 07:56:56 -0700 Date: Sun, 5 Jul 2009 07:56:56 -0700 (PDT) From: Linus Torvalds X-X-Sender: torvalds@localhost.localdomain To: Paul Mundt cc: Wu Zhangjin , linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mips@linux-mips.org, Krzysztof Helt , Peter Zijlstra , "Rafael J. Wysocki" , Andrew Morton , Ralf Baechle , ???? , zhangfx Subject: Re: [BUG] drivers/video/sis: deadlock introduced by "fbdev: add mutex for fb_mmap locking" In-Reply-To: <20090705145203.GA8326@linux-sh.org> Message-ID: References: <1246785112.14240.34.camel@falcon> <20090705145203.GA8326@linux-sh.org> User-Agent: Alpine 2.01 (LFD 1184 2008-12-16) MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII X-MIMEDefang-Filter: lf$Revision: 1.188 $ X-Scanned-By: MIMEDefang 2.63 on 140.211.169.13 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23651 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@