From ysjdxcn@gmail.com Mon Jun 1 06:41:01 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 01 Jun 2009 06:41:07 +0100 (BST) Received: from yw-out-1718.google.com ([74.125.46.154]:40815 "EHLO yw-out-1718.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20022152AbZFAFlB (ORCPT ); Mon, 1 Jun 2009 06:41:01 +0100 Received: by yw-out-1718.google.com with SMTP id 9so3415144ywk.24 for ; Sun, 31 May 2009 22:41:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:date:message-id:subject :from:to:content-type; bh=K+qRYtUu2WCrcm61BXezrXcWj8T637OWnaruQtReTwU=; b=oeL/nAnFoRwOQyTmovx9X0k2GwqeQ0l4pnx1eTr3+09kcKVna5TxCdtF5W9D4NaVlq skbI0HuFAsI+WNQi4hgNLR3oanijGSYuToLunBQDe/uz+ESIJbQoJf8ofGe1Qa4qnatv mu9NpqexTKqmqyojhm0UW/eJhxn6Jm8ei0CJ0= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:date:message-id:subject:from:to:content-type; b=FZ5u40E6jRnajnFgkrzrrouK5gLGc8bT7MeNj8kHPwAcafIJ6CXYbtFF73nMENA+vN 55qhvJx2LKT8k2+fOAp0/Y49E0yL3hb2jmhn5tKghvKrmf5Y18ES2nb0rOSOJgCRER5l oIPd2EWdgjDEZc0TMDmbgEyfoxoTaPXpoovSA= MIME-Version: 1.0 Received: by 10.90.103.13 with SMTP id a13mr4939637agc.28.1243834859912; Sun, 31 May 2009 22:40:59 -0700 (PDT) Date: Mon, 1 Jun 2009 13:40:59 +0800 Message-ID: <5ee6d7c00905312240r61b5e657oad4a9662e64dab8@mail.gmail.com> Subject: Wanna to get into this maillist From: =?GB2312?B?zLfB+g==?= To: linux-mips@linux-mips.org Content-Type: multipart/alternative; boundary=001636283694fbfe31046b42de54 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23101 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ysjdxcn@gmail.com Precedence: bulk X-list: linux-mips --001636283694fbfe31046b42de54 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit W. C. Fields - "I am free of all prejudices. I hate every one equally." --001636283694fbfe31046b42de54 Content-Type: text/html; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable

W. C. Fields =A0- "I am free = of all prejudices. I hate every one equally." --001636283694fbfe31046b42de54-- From wuzhangjin@gmail.com Mon Jun 1 08:41:43 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 01 Jun 2009 08:41:50 +0100 (BST) Received: from mail-px0-f187.google.com ([209.85.216.187]:50563 "EHLO mail-px0-f187.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20022670AbZFAHln (ORCPT ); Mon, 1 Jun 2009 08:41:43 +0100 Received: by pxi17 with SMTP id 17so6608562pxi.22 for ; Mon, 01 Jun 2009 00:41:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:subject:from:reply-to:to:cc :in-reply-to:references:content-type:organization:date:message-id :mime-version:x-mailer:content-transfer-encoding; bh=f+SfRCdJBRNm7J3BVxdcAODDjDDs+NuF0zSJmmVtxjA=; b=lzI2hakqPBgfhs31CcWy9NYARFdxjfXThvOaQUSDONbTOb9A7Kcb5TfAEePidq78z2 8L3MqKnoC4EK2uMaGkR9pRyKDTDxd/pRGmsimhDZFVU8ZWKjzcnr7BrGbPnFUV/mibUi TJOwvoxbdxMazuU4zQkj3QB12poPvapdehtFg= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=subject:from:reply-to:to:cc:in-reply-to:references:content-type :organization:date:message-id:mime-version:x-mailer :content-transfer-encoding; b=F+A1LvlnXPi/R/kUBKS1UPklQFmKFiKYiUIcEkYs3J145cu50hs4idMCmO/TizhU77 yk6ApEY8DT7ckJoQTcmqG89dBzs37XwbjuynhBFGGtEGqIh5Wc+sVi4jJLsKkjXMJNx3 pTjjIVprL1/V0FcrMqDHOuvolmFf6lnrHWk10= Received: by 10.142.204.11 with SMTP id b11mr1823347wfg.115.1243842096385; Mon, 01 Jun 2009 00:41:36 -0700 (PDT) Received: from ?192.168.2.239? ([202.201.14.140]) by mx.google.com with ESMTPS id l28sm5357539waf.54.2009.06.01.00.41.33 (version=TLSv1/SSLv3 cipher=RC4-MD5); Mon, 01 Jun 2009 00:41:35 -0700 (PDT) Subject: Re: [loongson-PATCH-v1 16/27] Add Siliconmotion 712 framebuffer driver From: Wu Zhangjin Reply-To: wuzhangjin@gmail.com To: Simon Braunschmidt Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org In-Reply-To: <4A1FE338.5010802@emlix.com> References: <4A1FE338.5010802@emlix.com> Content-Type: text/plain Organization: DSLab, Lanzhou University, China Date: Mon, 01 Jun 2009 15:41:30 +0800 Message-Id: <1243842090.5760.175.camel@falcon> Mime-Version: 1.0 X-Mailer: Evolution 2.26.1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23102 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips hi, > As i have seen lots of functionality are guarded by > #ifdef __BIG_ENDIAN > > Is there a way to setup a different mode than 1024x600 on > kernel-commandline or from userspace, e.g. with fbset? > I just removed some of #ifdef __BIG_ENDIAN ... #endif, and tuned the vesa_mode values, now, we can pass it in kernel-commandline like this: vga=1024x600x24 the latest SMI video driver patch with this modification will be sent out later, but you can get this one if you need it immediately: >From 34e4afa8b64f794e4fef0dd622ef576dbfecc851 Mon Sep 17 00:00:00 2001 From: Wu Zhangjin Date: Mon, 1 Jun 2009 15:31:26 +0800 Subject: [PATCH] enable the vga command line in SMI video driver there is no need to define a screen_info again so remove it, because it is defined in arch/mips/kernel/setup.c and not relative to big endian or little endian, and here I think its better use something like 1024x600x24 than 0x318, so replace all of the magic numbers to an understandable one. Signed-off-by: Wu Zhangjin --- drivers/video/smi/smtcfb.c | 42 ++++++++++++++++++------------------------ 1 files changed, 18 insertions(+), 24 deletions(-) diff --git a/drivers/video/smi/smtcfb.c b/drivers/video/smi/smtcfb.c index ebc6371..4fe940b 100644 --- a/drivers/video/smi/smtcfb.c +++ b/drivers/video/smi/smtcfb.c @@ -52,10 +52,6 @@ #define smdbg(format, arg...) #endif -#ifdef __BIG_ENDIAN -struct screen_info screen_info; -#endif - /* * Private structure */ @@ -96,32 +92,32 @@ struct par_info { u8 chipRevID; }; -#ifdef __BIG_ENDIAN struct vesa_mode_table { - char mode_index[6]; + char mode_index[15]; u16 lfb_width; u16 lfb_height; u16 lfb_depth; }; static struct vesa_mode_table vesa_mode[] = { - {"0x301", 640, 480, 8}, - {"0x303", 800, 600, 8}, - {"0x305", 1024, 768, 8}, - {"0x307", 1280, 1024, 8}, - - {"0x311", 640, 480, 16}, - {"0x314", 800, 600, 16}, - {"0x317", 1024, 768, 16}, - {"0x31A", 1280, 1024, 16}, - - {"0x312", 640, 480, 24}, - {"0x315", 800, 600, 24}, - {"0x318", 1024, 768, 24}, - {"0x31B", 1280, 1024, 24}, - + {"640x480x8", 640, 480, 8}, + {"800x480x8", 800, 480, 8}, + {"800x600x8", 800, 600, 8}, + {"1024x768x8", 1024, 768, 8}, + {"1280x1024x8", 1280, 1024, 8}, + + {"640x480x16", 640, 480, 16}, + {"800x480x16", 800, 480, 16}, + {"800x600x16", 800, 600, 16}, + {"1024x768x16", 1024, 768, 16}, + {"1280x1024x16", 1280, 1024, 16}, + + {"640x480x24", 640, 480, 24}, + {"800x480x24", 800, 480, 24}, + {"800x600x24", 800, 600, 24}, + {"1024x768x24", 1024, 768, 24}, + {"1280x1024x24", 1280, 1024, 24}, }; -#endif char __iomem *smtc_RegBaseAddress; /* Memory Map IO starting address */ char __iomem *smtc_VRAMBaseAddress; /* video memory starting address */ @@ -1100,7 +1096,6 @@ static int __init sm712be_setup(char *options) __setup("sm712be=", sm712be_setup); -#ifdef __BIG_ENDIAN /* * sm712vga_setup - process command line options, get vga parameter * @options: string of options @@ -1136,7 +1131,6 @@ static int __init sm712vga_setup(char *options) } __setup("vga=", sm712vga_setup); -#endif MODULE_AUTHOR("Siliconmotion "); MODULE_DESCRIPTION("Framebuffer driver for SMI Graphic Cards"); -- 1.6.0.4 with the support of this patch, the users of 7inch yeeloong and 8.9inch yeeloong can use the same kernel(not totally, the shutdown logic is a little different, a patch is also ready for it). there is only a need to add such kernel command line for 7inch yeeloong: vga=800x480x24 > What I currently do is > picking appropriate values form the table VGAMode in smtcfb.h and > hardcoding them. > > I tried 800x600x16bit@60hz, which worked also, but 1024x768x24bit@60hz > left me with a corrupted display output (distored colors, missing > regions), i did not check further wheter it also crashed. > no all of the Vesa mode is suitable to your screen, you should choose one for you, for example, only 800x480 is suitable to yeeloong 7inch screen, but the 8.9 inch yeeloong, need 1024x600. best regards, Wu Zhangjin From f.fainelli@gmail.com Mon Jun 1 12:56:45 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 01 Jun 2009 12:56:51 +0100 (BST) Received: from mail-ew0-f219.google.com ([209.85.219.219]:55949 "EHLO mail-ew0-f219.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20025117AbZFAL4p (ORCPT ); Mon, 1 Jun 2009 12:56:45 +0100 Received: by ewy19 with SMTP id 19so8025602ewy.0 for ; Mon, 01 Jun 2009 04:56:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:sender:from:to:subject:date :user-agent:mime-version:content-type:content-transfer-encoding :content-disposition:message-id; bh=gfHhlnymr3TEis5n9yXkOXlKZee1k3gN31jtxHDB+iY=; b=PgvKofoEdocUQaEfj/YgQ7roz9HgvBcrqcemivjLSVPSPeKCPzkQtRx9uUwITmpgS5 GedgOJ5lWDFxOWxtiPYuFGtS+8ZeVDV68Y+emdNam0jvEO8a+qTsbCgGHCqe8qjQ2cyB YwheAOeSQPSxJ1oAjKd5NThwdLwiHScgRPjZA= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:from:to:subject:date:user-agent:mime-version:content-type :content-transfer-encoding:content-disposition:message-id; b=mcQXpfRI1J3OEECnpVpd27mMBWn2MQ/f1FufYa5ash1o1aPAHA3Y/vjjdOl4yvb7Mv Gpsk0D1AO5lBvwqURdJXS7vpRE3/ks/b9jMtbMhDiw+JU3YuE5wqqe1jtpI44qHUZF0e yrzufH6tfQzoKvRnwLjBRHLydIJ79o6iEuo04= Received: by 10.210.35.5 with SMTP id i5mr6277716ebi.49.1243857393786; Mon, 01 Jun 2009 04:56:33 -0700 (PDT) Received: from florian.lab.openpattern.org (lab.openpattern.org [82.240.16.241]) by mx.google.com with ESMTPS id 28sm7277073eye.16.2009.06.01.04.56.31 (version=TLSv1/SSLv3 cipher=RC4-MD5); Mon, 01 Jun 2009 04:56:32 -0700 (PDT) From: Florian Fainelli To: linux-mips@linux-mips.org, Ralf Baechle , openwrt-devel@lists.openwrt.org Subject: [PATCH 0/9] Resubmission of the AR7 port Date: Mon, 1 Jun 2009 13:56:29 +0200 User-Agent: KMail/1.9.9 MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Content-Disposition: inline Message-Id: <200906011356.29943.florian@openwrt.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23103 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips Hi Ralf, This is a resubmission of the AR7 port. I have taken into account comments from the previous thread here: http://www.linux-mips.org/archives/linux-mips/2007-09/msg00005.html The following patches are splitted like this: 1 : export the sound/core/pcm_timer.c gcd implementation, also used by the AR7 clock routines 2 : add support for TI's VLYNQ bus 3 : wire in the VLYNQ bus support in drivers/ 4 : MIPS: deal with larger physical offsets 5 : serial: add support for the TI AR7 internal UART 6 : serial: workaround TI AR7 silicon bug 7 : MIPS: add TI AR7 support 8 : MIPS: add ar7_defconfig 9 : MIPS: wire in AR7 support Thanks -- Best regards, Florian Fainelli Email : florian@openwrt.org http://openwrt.org ------------------------------- From f.fainelli@gmail.com Mon Jun 1 12:57:39 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 01 Jun 2009 12:57:47 +0100 (BST) Received: from ey-out-1920.google.com ([74.125.78.147]:3487 "EHLO ey-out-1920.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20025120AbZFAL5N (ORCPT ); Mon, 1 Jun 2009 12:57:13 +0100 Received: by ey-out-1920.google.com with SMTP id 4so386372eyg.54 for ; Mon, 01 Jun 2009 04:57:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:sender:from:date:subject :mime-version:x-uid:x-length:to:content-type :content-transfer-encoding:content-disposition:message-id; bh=9jO9s7URUGIRtgsaw4G+EAosg5/XL2zy+XcCCVlhtpI=; b=xqUzi7yOA7ybpk9o9OeKMxB9PvxxgQmTO61BwXxvShUWTq5UxegNQR0ua6Q2ltkXNJ YSiAhnAxR4UnrXuOYL0GTnDtAOybJ2BgpK/lP23W3Uk4kXxCsvrbcPd+0VgNDZH4d4lP qnoFzBIZA1uFHLnezAbeozkHWlhGQmKNTouqo= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:from:date:subject:mime-version:x-uid:x-length:to :content-type:content-transfer-encoding:content-disposition :message-id; b=IDGWa0450o96NOM/9QnpH38usDfTS16RCctdMdFpPTkkzTa6sWGHIp+0UZhGmaHjSL jofYC8pNV52Mam9AD94y1CacsXM2JiQraHJZvpskc7AJo3QK0IdY9sQbhs3/yoxe7dxI j/rj3pi6c0vO7Rub6791327C66JwKAECI4xNU= Received: by 10.210.16.10 with SMTP id 10mr3939926ebp.40.1243857432048; Mon, 01 Jun 2009 04:57:12 -0700 (PDT) Received: from florian.lab.openpattern.org (lab.openpattern.org [82.240.16.241]) by mx.google.com with ESMTPS id 5sm143118eyf.48.2009.06.01.04.57.11 (version=TLSv1/SSLv3 cipher=RC4-MD5); Mon, 01 Jun 2009 04:57:11 -0700 (PDT) From: Florian Fainelli Date: Mon, 1 Jun 2009 13:57:09 +0200 Subject: [PATCH 1/9] kernel: export sound/core/pcm_timer.c gcd implementation MIME-Version: 1.0 X-UID: 173 X-Length: 2484 To: linux-kernel@vger.kernel.org, Takashi Iwai , akpm , linux-mips@linux-mips.org, Ralf Baechle , Ingo Molnar Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Content-Disposition: inline Message-Id: <200906011357.09966.florian@openwrt.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23104 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips This patch exports the gcd implementation from sound/core/pcm_timer.c into include/linux/kernel.h. AR7 uses it in its clock routines. Signed-off-by: Florian Fainelli --- diff --git a/include/linux/kernel.h b/include/linux/kernel.h index 883cd44..878a27a 100644 --- a/include/linux/kernel.h +++ b/include/linux/kernel.h @@ -147,6 +147,22 @@ extern int _cond_resched(void); (__x < 0) ? -__x : __x; \ }) +/* Greatest common divisor */ +static inline unsigned long gcd(unsigned long a, unsigned long b) +{ + unsigned long r; + if (a < b) { + r = a; + a = b; + b = r; + } + while ((r = a % b) != 0) { + a = b; + b = r; + } + return b; +} + #ifdef CONFIG_PROVE_LOCKING void might_fault(void); #else diff --git a/sound/core/pcm_timer.c b/sound/core/pcm_timer.c index ca8068b..e9dbf62 100644 --- a/sound/core/pcm_timer.c +++ b/sound/core/pcm_timer.c @@ -20,6 +20,7 @@ */ #include +#include #include #include #include @@ -28,22 +29,6 @@ * Timer functions */ -/* Greatest common divisor */ -static unsigned long gcd(unsigned long a, unsigned long b) -{ - unsigned long r; - if (a < b) { - r = a; - a = b; - b = r; - } - while ((r = a % b) != 0) { - a = b; - b = r; - } - return b; -} - void snd_pcm_timer_resolution_change(struct snd_pcm_substream *substream) { unsigned long rate, mult, fsize, l, post; From f.fainelli@gmail.com Mon Jun 1 12:59:55 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 01 Jun 2009 13:00:01 +0100 (BST) Received: from mail-ew0-f219.google.com ([209.85.219.219]:42468 "EHLO mail-ew0-f219.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20025130AbZFAL7z (ORCPT ); Mon, 1 Jun 2009 12:59:55 +0100 Received: by ewy19 with SMTP id 19so8027409ewy.0 for ; Mon, 01 Jun 2009 04:59:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:sender:from:date:subject :mime-version:x-uid:x-length:to:content-type :content-transfer-encoding:content-disposition:message-id; bh=3e1lmSTzSVnXkjpU42lXDYthx+baE/MVBgab+7ljVNA=; b=IV8uwDBYeNuTGEOhwnCqs3JRP005atQOCDenx1UuJtXgHUwa3mMVWBxo4gvygapYse XhlWf7FhGVqrPDLcHlOrE8rmgK06aEv4wfgjaLZvpcSr1DQTBRn4DbpDAZ/R4h1H1TOX 3MnyTiN9GtY3sQoYaeku/hgSGWm62NLQfz0rM= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:from:date:subject:mime-version:x-uid:x-length:to :content-type:content-transfer-encoding:content-disposition :message-id; b=XmyzMFERWmaGgm4h1ilKn9yM5wU9NUiJT7fjkx6Gmv5OBg8IsNV+UcZt7oWWYmwOaE yCrdaBfwsdKnhgmH5gGuWLJzTGWEk0/stT/KP4bdvw01nur+qbTWMXViS5fKhNAANScZ 3X9DFr6qng5VndFjJDVNyCJpar+85V8f+MPsc= Received: by 10.210.35.5 with SMTP id i5mr6286821ebi.11.1243857589183; Mon, 01 Jun 2009 04:59:49 -0700 (PDT) Received: from florian.lab.openpattern.org (lab.openpattern.org [82.240.16.241]) by mx.google.com with ESMTPS id 28sm7265148eyg.54.2009.06.01.04.59.48 (version=TLSv1/SSLv3 cipher=RC4-MD5); Mon, 01 Jun 2009 04:59:48 -0700 (PDT) From: Florian Fainelli Date: Mon, 1 Jun 2009 13:59:47 +0200 Subject: [PATCH 4/9] mips: deal with larger physical offsets MIME-Version: 1.0 X-UID: 176 X-Length: 2051 To: linux-mips@linux-mips.org, Ralf Baechle Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Content-Disposition: inline Message-Id: <200906011359.47216.florian@openwrt.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23105 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips TI AR7 has larger physical offsets than other MIPS-based systems. A long jump to the target is required instead of a short jump like on other systems. Signed-off-by: Eugene Konev Signed-off-by: Florian Fainelli --- diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index e83da17..44f7141 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -1256,9 +1256,22 @@ void *set_except_vector(int n, void *addr) exception_handlers[n] = handler; if (n == 0 && cpu_has_divec) { - *(u32 *)(ebase + 0x200) = 0x08000000 | - (0x03ffffff & (handler >> 2)); - local_flush_icache_range(ebase + 0x200, ebase + 0x204); + if ((handler ^ (ebase + 4)) & 0xfc000000) { + /* lui k0, 0x0000 */ + *(u32 *)(ebase + 0x200) = 0x3c1a0000 | (handler >> 16); + /* ori k0, 0x0000 */ + *(u32 *)(ebase + 0x204) = + 0x375a0000 | (handler & 0xffff); + /* jr k0 */ + *(u32 *)(ebase + 0x208) = 0x03400008; + /* nop */ + *(u32 *)(ebase + 0x20C) = 0x00000000; + local_flush_icache_range(ebase + 0x200, ebase + 0x210); + } else { + *(u32 *)(ebase + 0x200) = + 0x08000000 | (0x03ffffff & (handler >> 2)); + local_flush_icache_range(ebase + 0x200, ebase + 0x204); + } } return (void *)old_handler; } From f.fainelli@gmail.com Mon Jun 1 13:02:15 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 01 Jun 2009 13:02:21 +0100 (BST) Received: from mail-ew0-f219.google.com ([209.85.219.219]:34799 "EHLO mail-ew0-f219.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20025141AbZFAMCP (ORCPT ); Mon, 1 Jun 2009 13:02:15 +0100 Received: by ewy19 with SMTP id 19so8028905ewy.0 for ; Mon, 01 Jun 2009 05:02:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:sender:from:date:subject :mime-version:x-uid:x-length:to:content-type :content-transfer-encoding:content-disposition:message-id; bh=AuDNe5dDY4kQZCT0lLunMR1jOKaWMOvLWWiOQf6sXQE=; b=P9OuKiepuWorHNM9sQeozJbl5iTVSGMFdbnkpdu93IRfmu0UHaSOLDHmVjJA4++Kqg AoHZZ39uRQBssjBwg/bzBxPril5kUoeyWFct4+XHpxLooMaiPVUFzF51SiFol15+croP TGkdNkPFmGQ/jqiw9U68Sddb+gmTkSmp5xND0= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:from:date:subject:mime-version:x-uid:x-length:to :content-type:content-transfer-encoding:content-disposition :message-id; b=FLn61uALEa2EKsXT0Lm5vgjlZBD1wwWYxwqzYnviPPC7s3ZmQdzaQjWqbUVDwmDlvW QopNxTWCBuqEwAfJxk+rNFkDsffZPMSLg4sbTbgnxhQ4U58JeixYI9WI400Ayo7Xp56z +Q3Np0q/h78U7BjOc7EkgMKuPqkP9lRXu9co8= Received: by 10.210.38.5 with SMTP id l5mr3962080ebl.16.1243857728855; Mon, 01 Jun 2009 05:02:08 -0700 (PDT) Received: from florian.lab.openpattern.org (lab.openpattern.org [82.240.16.241]) by mx.google.com with ESMTPS id 28sm7275628eye.36.2009.06.01.05.02.07 (version=TLSv1/SSLv3 cipher=RC4-MD5); Mon, 01 Jun 2009 05:02:08 -0700 (PDT) From: Florian Fainelli Date: Mon, 1 Jun 2009 14:02:05 +0200 Subject: [PATCH 08/10] add TI AR7 support MIME-Version: 1.0 X-UID: 179 X-Length: 62906 To: Ralf Baechle , linux-mips@linux-mips.org, openwrt-devel@lists.openwrt.org Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Content-Disposition: inline Message-Id: <200906011402.05768.florian@openwrt.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23106 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips This patch adds support for the TI AR7 System-on-Chip. Supported versions are TNED7100, 7200 and 7300. Signed-off-by: Matteo Croce Signed-off-by: Felix Fietkau Signed-off-by: Eugene Konev Signed-off-by: Nicolas Thill Signed-off-by: Florian Fainelli --- diff --git a/arch/mips/ar7/Makefile b/arch/mips/ar7/Makefile new file mode 100644 index 0000000..7435e44 --- /dev/null +++ b/arch/mips/ar7/Makefile @@ -0,0 +1,10 @@ + +obj-y := \ + prom.o \ + setup.o \ + memory.o \ + irq.o \ + time.o \ + platform.o \ + gpio.o \ + clock.o diff --git a/arch/mips/ar7/clock.c b/arch/mips/ar7/clock.c new file mode 100644 index 0000000..3f28400 --- /dev/null +++ b/arch/mips/ar7/clock.c @@ -0,0 +1,447 @@ +/* + * Copyright (C) 2007 Felix Fietkau + * Copyright (C) 2007 Eugene Konev + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define BOOT_PLL_SOURCE_MASK 0x3 +#define CPU_PLL_SOURCE_SHIFT 16 +#define BUS_PLL_SOURCE_SHIFT 14 +#define USB_PLL_SOURCE_SHIFT 18 +#define DSP_PLL_SOURCE_SHIFT 22 +#define BOOT_PLL_SOURCE_AFE 0 +#define BOOT_PLL_SOURCE_BUS 0 +#define BOOT_PLL_SOURCE_REF 1 +#define BOOT_PLL_SOURCE_XTAL 2 +#define BOOT_PLL_SOURCE_CPU 3 +#define BOOT_PLL_BYPASS 0x00000020 +#define BOOT_PLL_ASYNC_MODE 0x02000000 +#define BOOT_PLL_2TO1_MODE 0x00008000 + +#define TNETD7200_CLOCK_ID_CPU 0 +#define TNETD7200_CLOCK_ID_DSP 1 +#define TNETD7200_CLOCK_ID_USB 2 + +#define TNETD7200_DEF_CPU_CLK 211000000 +#define TNETD7200_DEF_DSP_CLK 125000000 +#define TNETD7200_DEF_USB_CLK 48000000 + +struct tnetd7300_clock { + u32 ctrl; +#define PREDIV_MASK 0x001f0000 +#define PREDIV_SHIFT 16 +#define POSTDIV_MASK 0x0000001f + u32 unused1[3]; + u32 pll; +#define MUL_MASK 0x0000f000 +#define MUL_SHIFT 12 +#define PLL_MODE_MASK 0x00000001 +#define PLL_NDIV 0x00000800 +#define PLL_DIV 0x00000002 +#define PLL_STATUS 0x00000001 + u32 unused2[3]; +}; + +struct tnetd7300_clocks { + struct tnetd7300_clock bus; + struct tnetd7300_clock cpu; + struct tnetd7300_clock usb; + struct tnetd7300_clock dsp; +}; + +struct tnetd7200_clock { + u32 ctrl; + u32 unused1[3]; +#define DIVISOR_ENABLE_MASK 0x00008000 + u32 mul; + u32 prediv; + u32 postdiv; + u32 postdiv2; + u32 unused2[6]; + u32 cmd; + u32 status; + u32 cmden; + u32 padding[15]; +}; + +struct tnetd7200_clocks { + struct tnetd7200_clock cpu; + struct tnetd7200_clock dsp; + struct tnetd7200_clock usb; +}; + +int ar7_cpu_clock = 150000000; +EXPORT_SYMBOL(ar7_cpu_clock); +int ar7_bus_clock = 125000000; +EXPORT_SYMBOL(ar7_bus_clock); +int ar7_dsp_clock; +EXPORT_SYMBOL(ar7_dsp_clock); + +static void approximate(int base, int target, int *prediv, + int *postdiv, int *mul) +{ + int i, j, k, freq, res = target; + for (i = 1; i <= 16; i++) + for (j = 1; j <= 32; j++) + for (k = 1; k <= 32; k++) { + freq = abs(base / j * i / k - target); + if (freq < res) { + res = freq; + *mul = i; + *prediv = j; + *postdiv = k; + } + } +} + +static void calculate(int base, int target, int *prediv, int *postdiv, + int *mul) +{ + int tmp_gcd, tmp_base, tmp_freq; + + for (*prediv = 1; *prediv <= 32; (*prediv)++) { + tmp_base = base / *prediv; + tmp_gcd = gcd(target, tmp_base); + *mul = target / tmp_gcd; + *postdiv = tmp_base / tmp_gcd; + if ((*mul < 1) || (*mul >= 16)) + continue; + if ((*postdiv > 0) & (*postdiv <= 32)) + break; + } + + if (base / (*prediv) * (*mul) / (*postdiv) != target) { + approximate(base, target, prediv, postdiv, mul); + tmp_freq = base / (*prediv) * (*mul) / (*postdiv); + printk(KERN_WARNING + "Adjusted requested frequency %d to %d\n", + target, tmp_freq); + } + + printk(KERN_DEBUG "Clocks: prediv: %d, postdiv: %d, mul: %d\n", + *prediv, *postdiv, *mul); +} + +static int tnetd7300_dsp_clock(void) +{ + u32 didr1, didr2; + u8 rev = ar7_chip_rev(); + didr1 = readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x18)); + didr2 = readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x1c)); + if (didr2 & (1 << 23)) + return 0; + if ((rev >= 0x23) && (rev != 0x57)) + return 250000000; + if ((((didr2 & 0x1fff) << 10) | ((didr1 & 0xffc00000) >> 22)) + > 4208000) + return 250000000; + return 0; +} + +static int tnetd7300_get_clock(u32 shift, struct tnetd7300_clock *clock, + u32 *bootcr, u32 bus_clock) +{ + int product; + int base_clock = AR7_REF_CLOCK; + u32 ctrl = readl(&clock->ctrl); + u32 pll = readl(&clock->pll); + int prediv = ((ctrl & PREDIV_MASK) >> PREDIV_SHIFT) + 1; + int postdiv = (ctrl & POSTDIV_MASK) + 1; + int divisor = prediv * postdiv; + int mul = ((pll & MUL_MASK) >> MUL_SHIFT) + 1; + + switch ((*bootcr & (BOOT_PLL_SOURCE_MASK << shift)) >> shift) { + case BOOT_PLL_SOURCE_BUS: + base_clock = bus_clock; + break; + case BOOT_PLL_SOURCE_REF: + base_clock = AR7_REF_CLOCK; + break; + case BOOT_PLL_SOURCE_XTAL: + base_clock = AR7_XTAL_CLOCK; + break; + case BOOT_PLL_SOURCE_CPU: + base_clock = ar7_cpu_clock; + break; + } + + if (*bootcr & BOOT_PLL_BYPASS) + return base_clock / divisor; + + if ((pll & PLL_MODE_MASK) == 0) + return (base_clock >> (mul / 16 + 1)) / divisor; + + if ((pll & (PLL_NDIV | PLL_DIV)) == (PLL_NDIV | PLL_DIV)) { + product = (mul & 1) ? + (base_clock * mul) >> 1 : + (base_clock * (mul - 1)) >> 2; + return product / divisor; + } + + if (mul == 16) + return base_clock / divisor; + + return base_clock * mul / divisor; +} + +static void tnetd7300_set_clock(u32 shift, struct tnetd7300_clock *clock, + u32 *bootcr, u32 frequency) +{ + int prediv, postdiv, mul; + int base_clock = ar7_bus_clock; + + switch ((*bootcr & (BOOT_PLL_SOURCE_MASK << shift)) >> shift) { + case BOOT_PLL_SOURCE_BUS: + base_clock = ar7_bus_clock; + break; + case BOOT_PLL_SOURCE_REF: + base_clock = AR7_REF_CLOCK; + break; + case BOOT_PLL_SOURCE_XTAL: + base_clock = AR7_XTAL_CLOCK; + break; + case BOOT_PLL_SOURCE_CPU: + base_clock = ar7_cpu_clock; + break; + } + + calculate(base_clock, frequency, &prediv, &postdiv, &mul); + + writel(((prediv - 1) << PREDIV_SHIFT) | (postdiv - 1), &clock->ctrl); + mdelay(1); + writel(4, &clock->pll); + while (readl(&clock->pll) & PLL_STATUS) + ; + writel(((mul - 1) << MUL_SHIFT) | (0xff << 3) | 0x0e, &clock->pll); + mdelay(75); +} + +static void __init tnetd7300_init_clocks(void) +{ + u32 *bootcr = (u32 *)ioremap_nocache(AR7_REGS_DCL, 4); + struct tnetd7300_clocks *clocks = + (struct tnetd7300_clocks *) + ioremap_nocache(AR7_REGS_POWER + 0x20, + sizeof(struct tnetd7300_clocks)); + + ar7_bus_clock = tnetd7300_get_clock(BUS_PLL_SOURCE_SHIFT, + &clocks->bus, bootcr, AR7_AFE_CLOCK); + + if (*bootcr & BOOT_PLL_ASYNC_MODE) + ar7_cpu_clock = tnetd7300_get_clock(CPU_PLL_SOURCE_SHIFT, + &clocks->cpu, bootcr, AR7_AFE_CLOCK); + else + ar7_cpu_clock = ar7_bus_clock; +/* + tnetd7300_set_clock(USB_PLL_SOURCE_SHIFT, &clocks->usb, + bootcr, 48000000); +*/ + if (ar7_dsp_clock == 250000000) + tnetd7300_set_clock(DSP_PLL_SOURCE_SHIFT, &clocks->dsp, + bootcr, ar7_dsp_clock); + + iounmap(clocks); + iounmap(bootcr); +} + +static int tnetd7200_get_clock(int base, struct tnetd7200_clock *clock, + u32 *bootcr, u32 bus_clock) +{ + int divisor = ((readl(&clock->prediv) & 0x1f) + 1) * + ((readl(&clock->postdiv) & 0x1f) + 1); + + if (*bootcr & BOOT_PLL_BYPASS) + return base / divisor; + + return base * ((readl(&clock->mul) & 0xf) + 1) / divisor; +} + + +static void tnetd7200_set_clock(int base, struct tnetd7200_clock *clock, + int prediv, int postdiv, int postdiv2, int mul, u32 frequency) +{ + printk(KERN_INFO + "Clocks: base = %d, frequency = %u, prediv = %d, " + "postdiv = %d, postdiv2 = %d, mul = %d\n", + base, frequency, prediv, postdiv, postdiv2, mul); + + writel(0, &clock->ctrl); + writel(DIVISOR_ENABLE_MASK | ((prediv - 1) & 0x1F), &clock->prediv); + writel((mul - 1) & 0xF, &clock->mul); + + for (mul = 0; mul < 2000; mul++) + ; /* nop */ + + while (readl(&clock->status) & 0x1) + ; /* nop */ + + writel(DIVISOR_ENABLE_MASK | ((postdiv - 1) & 0x1F), &clock->postdiv); + + writel(readl(&clock->cmden) | 1, &clock->cmden); + writel(readl(&clock->cmd) | 1, &clock->cmd); + + while (readl(&clock->status) & 0x1) + ; /* nop */ + + writel(DIVISOR_ENABLE_MASK | ((postdiv2 - 1) & 0x1F), &clock->postdiv2); + + writel(readl(&clock->cmden) | 1, &clock->cmden); + writel(readl(&clock->cmd) | 1, &clock->cmd); + + while (readl(&clock->status) & 0x1) + ; /* nop */ + + writel(readl(&clock->ctrl) | 1, &clock->ctrl); +} + +static int tnetd7200_get_clock_base(int clock_id, u32 *bootcr) +{ + if (*bootcr & BOOT_PLL_ASYNC_MODE) + /* Async */ + switch (clock_id) { + case TNETD7200_CLOCK_ID_DSP: + return AR7_REF_CLOCK; + default: + return AR7_AFE_CLOCK; + } + else + /* Sync */ + if (*bootcr & BOOT_PLL_2TO1_MODE) + /* 2:1 */ + switch (clock_id) { + case TNETD7200_CLOCK_ID_DSP: + return AR7_REF_CLOCK; + default: + return AR7_AFE_CLOCK; + } + else + /* 1:1 */ + return AR7_REF_CLOCK; +} + + +static void __init tnetd7200_init_clocks(void) +{ + u32 *bootcr = (u32 *)ioremap_nocache(AR7_REGS_DCL, 4); + struct tnetd7200_clocks *clocks = + (struct tnetd7200_clocks *) + ioremap_nocache(AR7_REGS_POWER + 0x80, + sizeof(struct tnetd7200_clocks)); + int cpu_base, cpu_mul, cpu_prediv, cpu_postdiv; + int dsp_base, dsp_mul, dsp_prediv, dsp_postdiv; + int usb_base, usb_mul, usb_prediv, usb_postdiv; + + cpu_base = tnetd7200_get_clock_base(TNETD7200_CLOCK_ID_CPU, bootcr); + dsp_base = tnetd7200_get_clock_base(TNETD7200_CLOCK_ID_DSP, bootcr); + + if (*bootcr & BOOT_PLL_ASYNC_MODE) { + printk(KERN_INFO "Clocks: Async mode\n"); + + printk(KERN_INFO "Clocks: Setting DSP clock\n"); + calculate(dsp_base, TNETD7200_DEF_DSP_CLK, + &dsp_prediv, &dsp_postdiv, &dsp_mul); + ar7_bus_clock = + ((dsp_base / dsp_prediv) * dsp_mul) / dsp_postdiv; + tnetd7200_set_clock(dsp_base, &clocks->dsp, + dsp_prediv, dsp_postdiv * 2, dsp_postdiv, dsp_mul * 2, + ar7_bus_clock); + + printk(KERN_INFO "Clocks: Setting CPU clock\n"); + calculate(cpu_base, TNETD7200_DEF_CPU_CLK, &cpu_prediv, + &cpu_postdiv, &cpu_mul); + ar7_cpu_clock = + ((cpu_base / cpu_prediv) * cpu_mul) / cpu_postdiv; + tnetd7200_set_clock(cpu_base, &clocks->cpu, + cpu_prediv, cpu_postdiv, -1, cpu_mul, + ar7_cpu_clock); + + } else + if (*bootcr & BOOT_PLL_2TO1_MODE) { + printk(KERN_INFO "Clocks: Sync 2:1 mode\n"); + + printk(KERN_INFO "Clocks: Setting CPU clock\n"); + calculate(cpu_base, TNETD7200_DEF_CPU_CLK, &cpu_prediv, + &cpu_postdiv, &cpu_mul); + ar7_cpu_clock = ((cpu_base / cpu_prediv) * cpu_mul) + / cpu_postdiv; + tnetd7200_set_clock(cpu_base, &clocks->cpu, + cpu_prediv, cpu_postdiv, -1, cpu_mul, + ar7_cpu_clock); + + printk(KERN_INFO "Clocks: Setting DSP clock\n"); + calculate(dsp_base, TNETD7200_DEF_DSP_CLK, &dsp_prediv, + &dsp_postdiv, &dsp_mul); + ar7_bus_clock = ar7_cpu_clock / 2; + tnetd7200_set_clock(dsp_base, &clocks->dsp, + dsp_prediv, dsp_postdiv * 2, dsp_postdiv, + dsp_mul * 2, ar7_bus_clock); + } else { + printk(KERN_INFO "Clocks: Sync 1:1 mode\n"); + + printk(KERN_INFO "Clocks: Setting DSP clock\n"); + calculate(dsp_base, TNETD7200_DEF_DSP_CLK, &dsp_prediv, + &dsp_postdiv, &dsp_mul); + ar7_bus_clock = ((dsp_base / dsp_prediv) * dsp_mul) + / dsp_postdiv; + tnetd7200_set_clock(dsp_base, &clocks->dsp, + dsp_prediv, dsp_postdiv * 2, dsp_postdiv, + dsp_mul * 2, ar7_bus_clock); + + ar7_cpu_clock = ar7_bus_clock; + } + + printk(KERN_INFO "Clocks: Setting USB clock\n"); + usb_base = ar7_bus_clock; + calculate(usb_base, TNETD7200_DEF_USB_CLK, &usb_prediv, + &usb_postdiv, &usb_mul); + tnetd7200_set_clock(usb_base, &clocks->usb, + usb_prediv, usb_postdiv, -1, usb_mul, + TNETD7200_DEF_USB_CLK); + + #warning FIXME + ar7_dsp_clock = ar7_cpu_clock; + + iounmap(clocks); + iounmap(bootcr); +} + +void __init ar7_init_clocks(void) +{ + switch (ar7_chip_id()) { + case AR7_CHIP_7100: +#warning FIXME: Check if the new 7200 clock init works for 7100 + tnetd7200_init_clocks(); + break; + case AR7_CHIP_7200: + tnetd7200_init_clocks(); + break; + case AR7_CHIP_7300: + ar7_dsp_clock = tnetd7300_dsp_clock(); + tnetd7300_init_clocks(); + break; + default: + break; + } +} diff --git a/arch/mips/ar7/gpio.c b/arch/mips/ar7/gpio.c new file mode 100644 index 0000000..74e14a3 --- /dev/null +++ b/arch/mips/ar7/gpio.c @@ -0,0 +1,48 @@ +/* + * Copyright (C) 2007 Felix Fietkau + * Copyright (C) 2007 Eugene Konev + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include + +#include + +static const char *ar7_gpio_list[AR7_GPIO_MAX]; + +int gpio_request(unsigned gpio, const char *label) +{ + if (gpio >= AR7_GPIO_MAX) + return -EINVAL; + + if (ar7_gpio_list[gpio]) + return -EBUSY; + + if (label) + ar7_gpio_list[gpio] = label; + else + ar7_gpio_list[gpio] = "busy"; + + return 0; +} +EXPORT_SYMBOL(gpio_request); + +void gpio_free(unsigned gpio) +{ + BUG_ON(!ar7_gpio_list[gpio]); + ar7_gpio_list[gpio] = NULL; +} +EXPORT_SYMBOL(gpio_free); diff --git a/arch/mips/ar7/irq.c b/arch/mips/ar7/irq.c new file mode 100644 index 0000000..fb3756f --- /dev/null +++ b/arch/mips/ar7/irq.c @@ -0,0 +1,184 @@ +/* + * Copyright (C) 2006,2007 Felix Fietkau + * Copyright (C) 2006,2007 Eugene Konev + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include + +#include +#include +#include + +#define EXCEPT_OFFSET 0x80 +#define PACE_OFFSET 0xA0 +#define CHNLS_OFFSET 0x200 + +#define REG_OFFSET(irq, reg) ((irq) / 32 * 0x4 + reg * 0x10) +#define SEC_REG_OFFSET(reg) (EXCEPT_OFFSET + reg * 0x8) +#define SEC_SR_OFFSET (SEC_REG_OFFSET(0)) /* 0x80 */ +#define CR_OFFSET(irq) (REG_OFFSET(irq, 1)) /* 0x10 */ +#define SEC_CR_OFFSET (SEC_REG_OFFSET(1)) /* 0x88 */ +#define ESR_OFFSET(irq) (REG_OFFSET(irq, 2)) /* 0x20 */ +#define SEC_ESR_OFFSET (SEC_REG_OFFSET(2)) /* 0x90 */ +#define ECR_OFFSET(irq) (REG_OFFSET(irq, 3)) /* 0x30 */ +#define SEC_ECR_OFFSET (SEC_REG_OFFSET(3)) /* 0x98 */ +#define PIR_OFFSET (0x40) +#define MSR_OFFSET (0x44) +#define PM_OFFSET(irq) (REG_OFFSET(irq, 5)) /* 0x50 */ +#define TM_OFFSET(irq) (REG_OFFSET(irq, 6)) /* 0x60 */ + +#define REG(addr) ((u32 *)(KSEG1ADDR(AR7_REGS_IRQ) + addr)) + +#define CHNL_OFFSET(chnl) (CHNLS_OFFSET + (chnl * 4)) + +static void ar7_unmask_irq(unsigned int irq_nr); +static void ar7_mask_irq(unsigned int irq_nr); +static void ar7_ack_irq(unsigned int irq_nr); +static void ar7_unmask_sec_irq(unsigned int irq_nr); +static void ar7_mask_sec_irq(unsigned int irq_nr); +static void ar7_ack_sec_irq(unsigned int irq_nr); +static void ar7_cascade(void); +static void ar7_irq_init(int base); +static int ar7_irq_base; + +static struct irq_chip ar7_irq_type = { + .name = "AR7", + .unmask = ar7_unmask_irq, + .mask = ar7_mask_irq, + .ack = ar7_ack_irq +}; + +static struct irq_chip ar7_sec_irq_type = { + .name = "AR7", + .unmask = ar7_unmask_sec_irq, + .mask = ar7_mask_sec_irq, + .ack = ar7_ack_sec_irq, +}; + +static struct irqaction ar7_cascade_action = { + .handler = no_action, + .name = "AR7 cascade interrupt" +}; + +static void ar7_unmask_irq(unsigned int irq) +{ + writel(1 << ((irq - ar7_irq_base) % 32), + REG(ESR_OFFSET(irq - ar7_irq_base))); +} + +static void ar7_mask_irq(unsigned int irq) +{ + writel(1 << ((irq - ar7_irq_base) % 32), + REG(ECR_OFFSET(irq - ar7_irq_base))); +} + +static void ar7_ack_irq(unsigned int irq) +{ + writel(1 << ((irq - ar7_irq_base) % 32), + REG(CR_OFFSET(irq - ar7_irq_base))); +} + +static void ar7_unmask_sec_irq(unsigned int irq) +{ + writel(1 << (irq - ar7_irq_base - 40), REG(SEC_ESR_OFFSET)); +} + +static void ar7_mask_sec_irq(unsigned int irq) +{ + writel(1 << (irq - ar7_irq_base - 40), REG(SEC_ECR_OFFSET)); +} + +static void ar7_ack_sec_irq(unsigned int irq) +{ + writel(1 << (irq - ar7_irq_base - 40), REG(SEC_CR_OFFSET)); +} + +void __init arch_init_irq(void) +{ + mips_cpu_irq_init(); + ar7_irq_init(8); +} + +static void __init ar7_irq_init(int base) +{ + int i; + /* + * Disable interrupts and clear pending + */ + writel(0xffffffff, REG(ECR_OFFSET(0))); + writel(0xff, REG(ECR_OFFSET(32))); + writel(0xffffffff, REG(SEC_ECR_OFFSET)); + writel(0xffffffff, REG(CR_OFFSET(0))); + writel(0xff, REG(CR_OFFSET(32))); + writel(0xffffffff, REG(SEC_CR_OFFSET)); + + ar7_irq_base = base; + + for (i = 0; i < 40; i++) { + writel(i, REG(CHNL_OFFSET(i))); + /* Primary IRQ's */ + set_irq_chip_and_handler(base + i, &ar7_irq_type, + handle_level_irq); + /* Secondary IRQ's */ + if (i < 32) + set_irq_chip_and_handler(base + i + 40, + &ar7_sec_irq_type, + handle_level_irq); + } + + setup_irq(2, &ar7_cascade_action); + setup_irq(ar7_irq_base, &ar7_cascade_action); + set_c0_status(IE_IRQ0); +} + +static void ar7_cascade(void) +{ + u32 status; + int i, irq; + + /* Primary IRQ's */ + irq = readl(REG(PIR_OFFSET)) & 0x3f; + if (irq) { + do_IRQ(ar7_irq_base + irq); + return; + } + + /* Secondary IRQ's are cascaded through primary '0' */ + writel(1, REG(CR_OFFSET(irq))); + status = readl(REG(SEC_SR_OFFSET)); + for (i = 0; i < 32; i++) { + if (status & 1) { + do_IRQ(ar7_irq_base + i + 40); + return; + } + status >>= 1; + } + + spurious_interrupt(); +} + +asmlinkage void plat_irq_dispatch(void) +{ + unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM; + if (pending & STATUSF_IP7) /* cpu timer */ + do_IRQ(7); + else if (pending & STATUSF_IP2) /* int0 hardware line */ + ar7_cascade(); + else + spurious_interrupt(); +} diff --git a/arch/mips/ar7/memory.c b/arch/mips/ar7/memory.c new file mode 100644 index 0000000..e8522a1 --- /dev/null +++ b/arch/mips/ar7/memory.c @@ -0,0 +1,74 @@ +/* + * Based on arch/mips/mm/init.c + * Copyright (C) 1994 - 2000 Ralf Baechle + * Copyright (C) 1999, 2000 Silicon Graphics, Inc. + * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com + * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include + +static int __init memsize(void) +{ + u32 size = (64 << 20); + u32 *addr = (u32 *)KSEG1ADDR(0x14000000 + size - 4); + u32 *kernel_end = (u32 *)KSEG1ADDR(CPHYSADDR((u32)&_end)); + u32 *tmpaddr = addr; + + while (tmpaddr > kernel_end) { + *tmpaddr = (u32)tmpaddr; + size >>= 1; + tmpaddr -= size >> 2; + } + + do { + tmpaddr += size >> 2; + if (*tmpaddr != (u32)tmpaddr) + break; + size <<= 1; + } while (size < (64 << 20)); + + writel(tmpaddr, &addr); + + return size; +} + +void __init prom_meminit(void) +{ + unsigned long pages; + + pages = memsize() >> PAGE_SHIFT; + add_memory_region(PHYS_OFFSET, pages << PAGE_SHIFT, + BOOT_MEM_RAM); +} + +void __init prom_free_prom_memory(void) +{ + return; +} diff --git a/arch/mips/ar7/platform.c b/arch/mips/ar7/platform.c new file mode 100644 index 0000000..edb7fec --- /dev/null +++ b/arch/mips/ar7/platform.c @@ -0,0 +1,543 @@ +/* + * Copyright (C) 2006,2007 Felix Fietkau + * Copyright (C) 2006,2007 Eugene Konev + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +struct plat_vlynq_data { + struct plat_vlynq_ops ops; + int gpio_bit; + int reset_bit; +}; + + +static int vlynq_on(struct vlynq_device *dev) +{ + int result; + struct plat_vlynq_data *pdata = dev->dev.platform_data; + + result = gpio_request(pdata->gpio_bit, "vlynq"); + if (result) + goto out; + + ar7_device_reset(pdata->reset_bit); + + result = ar7_gpio_disable(pdata->gpio_bit); + if (result) + goto out_enabled; + + result = ar7_gpio_enable(pdata->gpio_bit); + if (result) + goto out_enabled; + + result = gpio_direction_output(pdata->gpio_bit, 0); + if (result) + goto out_gpio_enabled; + + mdelay(50); + + gpio_set_value(pdata->gpio_bit, 1); + mdelay(50); + + return 0; + +out_gpio_enabled: + ar7_gpio_disable(pdata->gpio_bit); +out_enabled: + ar7_device_disable(pdata->reset_bit); + gpio_free(pdata->gpio_bit); +out: + return result; +} + +static void vlynq_off(struct vlynq_device *dev) +{ + struct plat_vlynq_data *pdata = dev->dev.platform_data; + ar7_gpio_disable(pdata->gpio_bit); + gpio_free(pdata->gpio_bit); + ar7_device_disable(pdata->reset_bit); +} + +static struct resource physmap_flash_resource = { + .name = "mem", + .flags = IORESOURCE_MEM, + .start = 0x10000000, + .end = 0x107fffff, +}; + +static struct resource cpmac_low_res[] = { + { + .name = "regs", + .flags = IORESOURCE_MEM, + .start = AR7_REGS_MAC0, + .end = AR7_REGS_MAC0 + 0x7ff, + }, + { + .name = "irq", + .flags = IORESOURCE_IRQ, + .start = 27, + .end = 27, + }, +}; + +static struct resource cpmac_high_res[] = { + { + .name = "regs", + .flags = IORESOURCE_MEM, + .start = AR7_REGS_MAC1, + .end = AR7_REGS_MAC1 + 0x7ff, + }, + { + .name = "irq", + .flags = IORESOURCE_IRQ, + .start = 41, + .end = 41, + }, +}; + +static struct resource vlynq_low_res[] = { + { + .name = "regs", + .flags = IORESOURCE_MEM, + .start = AR7_REGS_VLYNQ0, + .end = AR7_REGS_VLYNQ0 + 0xff, + }, + { + .name = "irq", + .flags = IORESOURCE_IRQ, + .start = 29, + .end = 29, + }, + { + .name = "mem", + .flags = IORESOURCE_MEM, + .start = 0x04000000, + .end = 0x04ffffff, + }, + { + .name = "devirq", + .flags = IORESOURCE_IRQ, + .start = 80, + .end = 111, + }, +}; + +static struct resource vlynq_high_res[] = { + { + .name = "regs", + .flags = IORESOURCE_MEM, + .start = AR7_REGS_VLYNQ1, + .end = AR7_REGS_VLYNQ1 + 0xff, + }, + { + .name = "irq", + .flags = IORESOURCE_IRQ, + .start = 33, + .end = 33, + }, + { + .name = "mem", + .flags = IORESOURCE_MEM, + .start = 0x0c000000, + .end = 0x0cffffff, + }, + { + .name = "devirq", + .flags = IORESOURCE_IRQ, + .start = 112, + .end = 143, + }, +}; + +static struct resource usb_res[] = { + { + .name = "regs", + .flags = IORESOURCE_MEM, + .start = AR7_REGS_USB, + .end = AR7_REGS_USB + 0xff, + }, + { + .name = "irq", + .flags = IORESOURCE_IRQ, + .start = 32, + .end = 32, + }, + { + .name = "mem", + .flags = IORESOURCE_MEM, + .start = 0x03400000, + .end = 0x034001fff, + }, +}; + +static struct physmap_flash_data physmap_flash_data = { + .width = 2, +}; + +static struct plat_cpmac_data cpmac_low_data = { + .reset_bit = 17, + .power_bit = 20, + .phy_mask = 0x80000000, +}; + +static struct plat_cpmac_data cpmac_high_data = { + .reset_bit = 21, + .power_bit = 22, + .phy_mask = 0x7fffffff, +}; + +static struct plat_vlynq_data vlynq_low_data = { + .ops.on = vlynq_on, + .ops.off = vlynq_off, + .reset_bit = 20, + .gpio_bit = 18, +}; + +static struct plat_vlynq_data vlynq_high_data = { + .ops.on = vlynq_on, + .ops.off = vlynq_off, + .reset_bit = 16, + .gpio_bit = 19, +}; + +static struct platform_device physmap_flash = { + .id = 0, + .name = "physmap-flash", + .dev.platform_data = &physmap_flash_data, + .resource = &physmap_flash_resource, + .num_resources = 1, +}; + +static u64 cpmac_dma_mask = DMA_32BIT_MASK; +static struct platform_device cpmac_low = { + .id = 0, + .name = "cpmac", + .dev = { + .dma_mask = &cpmac_dma_mask, + .coherent_dma_mask = DMA_32BIT_MASK, + .platform_data = &cpmac_low_data, + }, + .resource = cpmac_low_res, + .num_resources = ARRAY_SIZE(cpmac_low_res), +}; + +static struct platform_device cpmac_high = { + .id = 1, + .name = "cpmac", + .dev = { + .dma_mask = &cpmac_dma_mask, + .coherent_dma_mask = DMA_32BIT_MASK, + .platform_data = &cpmac_high_data, + }, + .resource = cpmac_high_res, + .num_resources = ARRAY_SIZE(cpmac_high_res), +}; + +static struct platform_device vlynq_low = { + .id = 0, + .name = "vlynq", + .dev.platform_data = &vlynq_low_data, + .resource = vlynq_low_res, + .num_resources = ARRAY_SIZE(vlynq_low_res), +}; + +static struct platform_device vlynq_high = { + .id = 1, + .name = "vlynq", + .dev.platform_data = &vlynq_high_data, + .resource = vlynq_high_res, + .num_resources = ARRAY_SIZE(vlynq_high_res), +}; + + +/* This is proper way to define uart ports, but they are then detected + * as xscale and, obviously, don't work... + */ +#if !defined(CONFIG_SERIAL_8250) + +static struct plat_serial8250_port uart0_data = { + .mapbase = AR7_REGS_UART0, + .irq = AR7_IRQ_UART0, + .regshift = 2, + .iotype = UPIO_MEM, + .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, +}; + +static struct plat_serial8250_port uart1_data = { + .mapbase = UR8_REGS_UART1, + .irq = AR7_IRQ_UART1, + .regshift = 2, + .iotype = UPIO_MEM, + .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, +}; + +static struct plat_serial8250_port uart_data[] = { + uart0_data, + uart1_data, + { .flags = 0 } +}; + +static struct plat_serial8250_port uart_data_single[] = { + uart0_data, + { .flags = 0 } +}; + +static struct platform_device uart = { + .id = 0, + .name = "serial8250", + .dev.platform_data = uart_data_single +}; +#endif + +static struct gpio_led default_leds[] = { + { .name = "status", .gpio = 8, .active_low = 1, }, +}; + +static struct gpio_led dsl502t_leds[] = { + { .name = "status", .gpio = 9, .active_low = 1, }, + { .name = "ethernet", .gpio = 7, .active_low = 1, }, + { .name = "usb", .gpio = 12, .active_low = 1, }, +}; + +static struct gpio_led dg834g_leds[] = { + { .name = "ppp", .gpio = 6, .active_low = 1, }, + { .name = "status", .gpio = 7, .active_low = 1, }, + { .name = "adsl", .gpio = 8, .active_low = 1, }, + { .name = "wifi", .gpio = 12, .active_low = 1, }, + { + .name = "power", + .gpio = 14, + .active_low = 1, + .default_trigger = "default-on", + }, +}; + +static struct gpio_led fb_sl_leds[] = { + { .name = "1", .gpio = 7, }, + { .name = "2", .gpio = 13, .active_low = 1, }, + { .name = "3", .gpio = 10, .active_low = 1, }, + { .name = "4", .gpio = 12, .active_low = 1, }, + { .name = "5", .gpio = 9, .active_low = 1, }, +}; + +static struct gpio_led fb_fon_leds[] = { + { .name = "1", .gpio = 8, }, + { .name = "2", .gpio = 3, .active_low = 1, }, + { .name = "3", .gpio = 5, }, + { .name = "4", .gpio = 4, .active_low = 1, }, + { .name = "5", .gpio = 11, .active_low = 1, }, +}; + +static struct gpio_led_platform_data ar7_led_data; + +static struct platform_device ar7_gpio_leds = { + .name = "leds-gpio", + .id = -1, + .dev = { + .platform_data = &ar7_led_data, + } +}; + +static struct platform_device ar7_udc = { + .id = -1, + .name = "ar7_udc", + .resource = usb_res, + .num_resources = ARRAY_SIZE(usb_res), +}; + +static inline unsigned char char2hex(char h) +{ + switch (h) { + case '0': case '1': case '2': case '3': case '4': + case '5': case '6': case '7': case '8': case '9': + return h - '0'; + case 'A': case 'B': case 'C': case 'D': case 'E': case 'F': + return h - 'A' + 10; + case 'a': case 'b': case 'c': case 'd': case 'e': case 'f': + return h - 'a' + 10; + default: + return 0; + } +} + +static void cpmac_get_mac(int instance, unsigned char *dev_addr) +{ + int i; + char name[5], default_mac[] = "00:00:00:12:34:56", *mac; + + mac = NULL; + sprintf(name, "mac%c", 'a' + instance); + mac = prom_getenv(name); + if (!mac) { + sprintf(name, "mac%c", 'a'); + mac = prom_getenv(name); + } + if (!mac) + mac = default_mac; + for (i = 0; i < 6; i++) + dev_addr[i] = (char2hex(mac[i * 3]) << 4) + + char2hex(mac[i * 3 + 1]); +} + +static void __init detect_leds(void) +{ + char *prId, *usb_prod; + + /* Default LEDs */ + ar7_led_data.num_leds = ARRAY_SIZE(default_leds); + ar7_led_data.leds = default_leds; + + /* FIXME: the whole thing is unreliable */ + prId = prom_getenv("ProductID"); + usb_prod = prom_getenv("usb_prod"); + + /* If we can't get the product id from PROM, use the default LEDs */ + if (!prId) + return; + + if (strstr(prId, "Fritz_Box_FON")) { + ar7_led_data.num_leds = ARRAY_SIZE(fb_fon_leds); + ar7_led_data.leds = fb_fon_leds; + } else if (strstr(prId, "Fritz_Box_")) { + ar7_led_data.num_leds = ARRAY_SIZE(fb_sl_leds); + ar7_led_data.leds = fb_sl_leds; + } else if ((!strcmp(prId, "AR7RD") || !strcmp(prId, "AR7DB")) + && usb_prod != NULL && strstr(usb_prod, "DSL-502T")) { + ar7_led_data.num_leds = ARRAY_SIZE(dsl502t_leds); + ar7_led_data.leds = dsl502t_leds; + } else if (strstr(prId, "DG834")) { + ar7_led_data.num_leds = ARRAY_SIZE(dg834g_leds); + ar7_led_data.leds = dg834g_leds; + } +} + +static int __init ar7_register_devices(void) +{ + int res; + +#ifdef CONFIG_SERIAL_8250 + + static struct uart_port uart_port[2]; + + memset(uart_port, 0, sizeof(struct uart_port) * 2); + + uart_port[0].type = PORT_AR7; + uart_port[0].line = 0; + uart_port[0].irq = AR7_IRQ_UART0; + uart_port[0].uartclk = ar7_bus_freq() / 2; + uart_port[0].iotype = UPIO_MEM; + uart_port[0].mapbase = AR7_REGS_UART0; + uart_port[0].membase = ioremap(uart_port[0].mapbase, 256); + uart_port[0].regshift = 2; + res = early_serial_setup(&uart_port[0]); + if (res) + return res; + + + /* Only TNETD73xx have a second serial port */ + if (ar7_has_second_uart()) { + uart_port[1].type = PORT_AR7; + uart_port[1].line = 1; + uart_port[1].irq = AR7_IRQ_UART1; + uart_port[1].uartclk = ar7_bus_freq() / 2; + uart_port[1].iotype = UPIO_MEM; + uart_port[1].mapbase = UR8_REGS_UART1; + uart_port[1].membase = ioremap(uart_port[1].mapbase, 256); + uart_port[1].regshift = 2; + res = early_serial_setup(&uart_port[1]); + if (res) + return res; + } + +#else /* !CONFIG_SERIAL_8250 */ + + uart_data[0].uartclk = ar7_bus_freq() / 2; + uart_data[1].uartclk = uart_data[0].uartclk; + + /* Only TNETD73xx have a second serial port */ + if (ar7_has_second_uart()) + uart.dev.platform_data = uart_data; + + res = platform_device_register(&uart); + if (res) + return res; + +#endif /* CONFIG_SERIAL_8250 */ + + res = platform_device_register(&physmap_flash); + if (res) + return res; + + ar7_device_disable(vlynq_low_data.reset_bit); + res = platform_device_register(&vlynq_low); + if (res) + return res; + + if (ar7_has_high_vlynq()) { + ar7_device_disable(vlynq_high_data.reset_bit); + res = platform_device_register(&vlynq_high); + if (res) + return res; + } + + if (ar7_has_high_cpmac()) { + cpmac_get_mac(1, cpmac_high_data.dev_addr); + res = platform_device_register(&cpmac_high); + if (res) + return res; + } else { + cpmac_low_data.phy_mask = 0xffffffff; + } + + cpmac_get_mac(0, cpmac_low_data.dev_addr); + res = platform_device_register(&cpmac_low); + if (res) + return res; + + detect_leds(); + res = platform_device_register(&ar7_gpio_leds); + if (res) + return res; + + res = platform_device_register(&ar7_udc); + + return res; +} + + +arch_initcall(ar7_register_devices); diff --git a/arch/mips/ar7/prom.c b/arch/mips/ar7/prom.c new file mode 100644 index 0000000..ce16385 --- /dev/null +++ b/arch/mips/ar7/prom.c @@ -0,0 +1,330 @@ +/* + * Carsten Langgaard, carstenl@mips.com + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * Putting things on the screen/serial line using YAMONs facilities. + */ +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#define MAX_ENTRY 80 + +struct env_var { + char *name; + char *value; +}; + +static struct env_var adam2_env[MAX_ENTRY] = { { 0, }, }; + +char *prom_getenv(const char *name) +{ + int i; + for (i = 0; (i < MAX_ENTRY) && adam2_env[i].name; i++) + if (!strcmp(name, adam2_env[i].name)) + return adam2_env[i].value; + + return NULL; +} +EXPORT_SYMBOL(prom_getenv); + +char * __init prom_getcmdline(void) +{ + return &(arcs_cmdline[0]); +} + +static void __init ar7_init_cmdline(int argc, char *argv[]) +{ + char *cp; + int actr; + + actr = 1; /* Always ignore argv[0] */ + + cp = &(arcs_cmdline[0]); + while (actr < argc) { + strcpy(cp, argv[actr]); + cp += strlen(argv[actr]); + *cp++ = ' '; + actr++; + } + if (cp != &(arcs_cmdline[0])) { + /* get rid of trailing space */ + --cp; + *cp = '\0'; + } +} + +struct psbl_rec { + u32 psbl_size; + u32 env_base; + u32 env_size; + u32 ffs_base; + u32 ffs_size; +}; + +static __initdata char psp_env_version[] = "TIENV0.8"; + +struct psp_env_chunk { + u8 num; + u8 ctrl; + u16 csum; + u8 len; + char data[11]; +} __attribute__ ((packed)); + +struct psp_var_map_entry { + u8 num; + char *value; +}; + +static struct psp_var_map_entry psp_var_map[] = { + { 1, "cpufrequency" }, + { 2, "memsize" }, + { 3, "flashsize" }, + { 4, "modetty0" }, + { 5, "modetty1" }, + { 8, "maca" }, + { 9, "macb" }, + { 28, "sysfrequency" }, + { 38, "mipsfrequency" }, +}; + +/* + +Well-known variable (num is looked up in table above for matching variable name) +Example: cpufrequency=211968000 ++----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+--- +| 01 |CTRL|CHECKSUM | 01 | _2 | _1 | _1 | _9 | _6 | _8 | _0 | _0 | _0 | \0 | FF ++----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+--- + +Name=Value pair in a single chunk +Example: NAME=VALUE ++----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+--- +| 00 |CTRL|CHECKSUM | 01 | _N | _A | _M | _E | _0 | _V | _A | _L | _U | _E | \0 ++----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+--- + +Name=Value pair in 2 chunks (len is the number of chunks) +Example: bootloaderVersion=1.3.7.15 ++----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+--- +| 00 |CTRL|CHECKSUM | 02 | _b | _o | _o | _t | _l | _o | _a | _d | _e | _r | _V ++----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+--- +| _e | _r | _s | _i | _o | _n | \0 | _1 | _. | _3 | _. | _7 | _. | _1 | _5 | \0 ++----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+--- + +Data is padded with 0xFF + +*/ + +#define PSP_ENV_SIZE 4096 + +static char psp_env_data[PSP_ENV_SIZE] = { 0, }; + +static char * __init lookup_psp_var_map(u8 num) +{ + int i; + + for (i = 0; i < sizeof(psp_var_map); i++) + if (psp_var_map[i].num == num) + return psp_var_map[i].value; + + return NULL; +} + +static void __init add_adam2_var(char *name, char *value) +{ + int i; + for (i = 0; i < MAX_ENTRY; i++) { + if (!adam2_env[i].name) { + adam2_env[i].name = name; + adam2_env[i].value = value; + return; + } else if (!strcmp(adam2_env[i].name, name)) { + adam2_env[i].value = value; + return; + } + } +} + +static int __init parse_psp_env(void *psp_env_base) +{ + int i, n; + char *name, *value; + struct psp_env_chunk *chunks = (struct psp_env_chunk *)psp_env_data; + + memcpy_fromio(chunks, psp_env_base, PSP_ENV_SIZE); + + i = 1; + n = PSP_ENV_SIZE / sizeof(struct psp_env_chunk); + while (i < n) { + if ((chunks[i].num == 0xff) || ((i + chunks[i].len) > n)) + break; + value = chunks[i].data; + if (chunks[i].num) { + name = lookup_psp_var_map(chunks[i].num); + } else { + name = value; + value += strlen(name) + 1; + } + if (name) + add_adam2_var(name, value); + i += chunks[i].len; + } + return 0; +} + +static void __init ar7_init_env(struct env_var *env) +{ + int i; + struct psbl_rec *psbl = (struct psbl_rec *)(KSEG1ADDR(0x14000300)); + void *psp_env = (void *)KSEG1ADDR(psbl->env_base); + + if (strcmp(psp_env, psp_env_version) == 0) { + parse_psp_env(psp_env); + } else { + for (i = 0; i < MAX_ENTRY; i++, env++) + if (env->name) + add_adam2_var(env->name, env->value); + } +} + +static void __init console_config(void) +{ +#ifdef CONFIG_SERIAL_8250_CONSOLE + char console_string[40]; + int baud = 0; + char parity = '\0', bits = '\0', flow = '\0'; + char *s, *p; + + if (strstr(prom_getcmdline(), "console=")) + return; + +#ifdef CONFIG_KGDB + if (!strstr(prom_getcmdline(), "nokgdb")) { + strcat(prom_getcmdline(), " console=kgdb"); + kgdb_enabled = 1; + return; + } +#endif + + s = prom_getenv("modetty0"); + if (s) { + baud = simple_strtoul(s, &p, 10); + s = p; + if (*s == ',') + s++; + if (*s) + parity = *s++; + if (*s == ',') + s++; + if (*s) + bits = *s++; + if (*s == ',') + s++; + if (*s == 'h') + flow = 'r'; + } + + if (baud == 0) + baud = 38400; + if (parity != 'n' && parity != 'o' && parity != 'e') + parity = 'n'; + if (bits != '7' && bits != '8') + bits = '8'; + + if (flow == 'r') + sprintf(console_string, " console=ttyS0,%d%c%c%c", baud, + parity, bits, flow); + else + sprintf(console_string, " console=ttyS0,%d%c%c", baud, parity, + bits); + strcat(prom_getcmdline(), console_string); +#endif +} + +void __init prom_init(void) +{ + ar7_init_cmdline(fw_arg0, (char **)fw_arg1); + ar7_init_env((struct env_var *)fw_arg2); + console_config(); +} + +#define PORT(offset) (KSEG1ADDR(AR7_REGS_UART0 + (offset * 4))) +static inline unsigned int serial_in(int offset) +{ + return readb((void *)PORT(offset)); +} + +static inline void serial_out(int offset, int value) +{ + writeb(value, (void *)PORT(offset)); +} + +char prom_getchar(void) +{ + while (!(serial_in(UART_LSR) & UART_LSR_DR)) + ; + return serial_in(UART_RX); +} + +int prom_putchar(char c) +{ + while ((serial_in(UART_LSR) & UART_LSR_TEMT) == 0) + ; + serial_out(UART_TX, c); + return 1; +} + +/* from adm5120/prom.c */ +void prom_printf(const char *fmt, ...) +{ + va_list args; + int l; + char *p, *buf_end; + char buf[1024]; + + va_start(args, fmt); + l = vsprintf(buf, fmt, args); /* hopefully i < sizeof(buf) */ + va_end(args); + + buf_end = buf + l; + + for (p = buf; p < buf_end; p++) { + /* Crude cr/nl handling is better than none */ + if (*p == '\n') + prom_putchar('\r'); + prom_putchar(*p); + } +} + +#ifdef CONFIG_KGDB +int putDebugChar(char c) +{ + return prom_putchar(c); +} + +char getDebugChar(void) +{ + return prom_getchar(); +} +#endif diff --git a/arch/mips/ar7/setup.c b/arch/mips/ar7/setup.c new file mode 100644 index 0000000..a5bd7e6 --- /dev/null +++ b/arch/mips/ar7/setup.c @@ -0,0 +1,107 @@ +/* + * Carsten Langgaard, carstenl@mips.com + * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + */ +#include +#include +#include +#include + +#include +#include +#include +#include + +static void ar7_machine_restart(char *command); +static void ar7_machine_halt(void); +static void ar7_machine_power_off(void); + +static void ar7_machine_restart(char *command) +{ + u32 *softres_reg = (u32 *)ioremap(AR7_REGS_RESET + + AR7_RESET_SOFTWARE, 1); + writel(1, softres_reg); +} + +static void ar7_machine_halt(void) +{ + while (1) + ; +} + +static void ar7_machine_power_off(void) +{ + u32 *power_reg = (u32 *)ioremap(AR7_REGS_POWER, 1); + u32 power_state = readl(power_reg) | (3 << 30); + writel(power_state, power_reg); + ar7_machine_halt(); +} + +const char *get_system_type(void) +{ + u16 chip_id = ar7_chip_id(); + switch (chip_id) { + case AR7_CHIP_7300: + return "TI AR7 (TNETD7300)"; + case AR7_CHIP_7100: + return "TI AR7 (TNETD7100)"; + case AR7_CHIP_7200: + return "TI AR7 (TNETD7200)"; + default: + return "TI AR7 (Unknown)"; + } +} + +static int __init ar7_init_console(void) +{ + return 0; +} + +/* + * Initializes basic routines and structures pointers, memory size (as + * given by the bios and saves the command line. + */ + +extern void ar7_init_clocks(void); + +void __init plat_mem_setup(void) +{ + unsigned long io_base; + + _machine_restart = ar7_machine_restart; + _machine_halt = ar7_machine_halt; + pm_power_off = ar7_machine_power_off; + panic_timeout = 3; + + io_base = (unsigned long)ioremap(AR7_REGS_BASE, 0x10000); + if (!io_base) + panic("Can't remap IO base!\n"); + set_io_port_base(io_base); + + prom_meminit(); + ar7_init_clocks(); + + ioport_resource.start = 0; + ioport_resource.end = ~0; + iomem_resource.start = 0; + iomem_resource.end = ~0; + + printk(KERN_INFO "%s, ID: 0x%04x, Revision: 0x%02x\n", + get_system_type(), + ar7_chip_id(), ar7_chip_rev()); +} + +console_initcall(ar7_init_console); diff --git a/arch/mips/ar7/time.c b/arch/mips/ar7/time.c new file mode 100644 index 0000000..5f17489 --- /dev/null +++ b/arch/mips/ar7/time.c @@ -0,0 +1,28 @@ +/* + * Carsten Langgaard, carstenl@mips.com + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * Setting up the clock on the MIPS boards. + */ + +#include +#include +#include + +void __init plat_time_init(void) +{ + mips_hpt_frequency = ar7_cpu_freq() / 2; +} diff --git a/arch/mips/include/asm/mach-ar7/ar7.h b/arch/mips/include/asm/mach-ar7/ar7.h new file mode 100644 index 0000000..d972e09 --- /dev/null +++ b/arch/mips/include/asm/mach-ar7/ar7.h @@ -0,0 +1,170 @@ +/* + * Copyright (C) 2006,2007 Felix Fietkau + * Copyright (C) 2006,2007 Eugene Konev + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __AR7_H__ +#define __AR7_H__ + +#include +#include +#include + +#define AR7_REGS_BASE 0x08610000 + +#define AR7_REGS_MAC0 (AR7_REGS_BASE + 0x0000) +#define AR7_REGS_GPIO (AR7_REGS_BASE + 0x0900) +/* 0x08610A00 - 0x08610BFF (512 bytes, 128 bytes / clock) */ +#define AR7_REGS_POWER (AR7_REGS_BASE + 0x0a00) +#define AR7_REGS_UART0 (AR7_REGS_BASE + 0x0e00) +#define AR7_REGS_USB (AR7_REGS_BASE + 0x1200) +#define AR7_REGS_RESET (AR7_REGS_BASE + 0x1600) +#define AR7_REGS_VLYNQ0 (AR7_REGS_BASE + 0x1800) +#define AR7_REGS_DCL (AR7_REGS_BASE + 0x1a00) +#define AR7_REGS_VLYNQ1 (AR7_REGS_BASE + 0x1c00) +#define AR7_REGS_MDIO (AR7_REGS_BASE + 0x1e00) +#define AR7_REGS_IRQ (AR7_REGS_BASE + 0x2400) +#define AR7_REGS_MAC1 (AR7_REGS_BASE + 0x2800) + +#define AR7_REGS_WDT (AR7_REGS_BASE + 0x1f00) +#define UR8_REGS_WDT (AR7_REGS_BASE + 0x0b00) +#define UR8_REGS_UART1 (AR7_REGS_BASE + 0x0f00) + +#define AR7_RESET_PEREPHERIAL 0x0 +#define AR7_RESET_SOFTWARE 0x4 +#define AR7_RESET_STATUS 0x8 + +#define AR7_RESET_BIT_CPMAC_LO 17 +#define AR7_RESET_BIT_CPMAC_HI 21 +#define AR7_RESET_BIT_MDIO 22 +#define AR7_RESET_BIT_EPHY 26 + +/* GPIO control registers */ +#define AR7_GPIO_INPUT 0x0 +#define AR7_GPIO_OUTPUT 0x4 +#define AR7_GPIO_DIR 0x8 +#define AR7_GPIO_ENABLE 0xc + +#define AR7_CHIP_7100 0x18 +#define AR7_CHIP_7200 0x2b +#define AR7_CHIP_7300 0x05 + +/* Interrupts */ +#define AR7_IRQ_UART0 15 +#define AR7_IRQ_UART1 16 + +/* Clocks */ +#define AR7_AFE_CLOCK 35328000 +#define AR7_REF_CLOCK 25000000 +#define AR7_XTAL_CLOCK 24000000 + +struct plat_cpmac_data { + int reset_bit; + int power_bit; + u32 phy_mask; + char dev_addr[6]; +}; + +struct plat_dsl_data { + int reset_bit_dsl; + int reset_bit_sar; +}; + +extern int ar7_cpu_clock, ar7_bus_clock, ar7_dsp_clock; + +static inline u16 ar7_chip_id(void) +{ + return readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x14)) & 0xffff; +} + +static inline u8 ar7_chip_rev(void) +{ + return (readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x14)) >> 16) & 0xff; +} + +static inline int ar7_cpu_freq(void) +{ + return ar7_cpu_clock; +} + +static inline int ar7_bus_freq(void) +{ + return ar7_bus_clock; +} + +static inline int ar7_vbus_freq(void) +{ + return ar7_bus_clock / 2; +} +#define ar7_cpmac_freq ar7_vbus_freq + +static inline int ar7_dsp_freq(void) +{ + return ar7_dsp_clock; +} + +static inline int ar7_has_high_cpmac(void) +{ + u16 chip_id = ar7_chip_id(); + switch (chip_id) { + case AR7_CHIP_7100: + case AR7_CHIP_7200: + return 0; + default: + return 1; + } +} +#define ar7_has_high_vlynq ar7_has_high_cpmac +#define ar7_has_second_uart ar7_has_high_cpmac + +static inline void ar7_device_enable(u32 bit) +{ + void *reset_reg = + (void *)KSEG1ADDR(AR7_REGS_RESET + AR7_RESET_PEREPHERIAL); + writel(readl(reset_reg) | (1 << bit), reset_reg); + mdelay(20); +} + +static inline void ar7_device_disable(u32 bit) +{ + void *reset_reg = + (void *)KSEG1ADDR(AR7_REGS_RESET + AR7_RESET_PEREPHERIAL); + writel(readl(reset_reg) & ~(1 << bit), reset_reg); + mdelay(20); +} + +static inline void ar7_device_reset(u32 bit) +{ + ar7_device_disable(bit); + ar7_device_enable(bit); +} + +static inline void ar7_device_on(u32 bit) +{ + void *power_reg = (void *)KSEG1ADDR(AR7_REGS_POWER); + writel(readl(power_reg) | (1 << bit), power_reg); + mdelay(20); +} + +static inline void ar7_device_off(u32 bit) +{ + void *power_reg = (void *)KSEG1ADDR(AR7_REGS_POWER); + writel(readl(power_reg) & ~(1 << bit), power_reg); + mdelay(20); +} + +#endif /* __AR7_H__ */ diff --git a/arch/mips/include/asm/mach-ar7/gpio.h b/arch/mips/include/asm/mach-ar7/gpio.h new file mode 100644 index 0000000..cbe9c4f --- /dev/null +++ b/arch/mips/include/asm/mach-ar7/gpio.h @@ -0,0 +1,110 @@ +/* + * Copyright (C) 2007 Florian Fainelli + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __AR7_GPIO_H__ +#define __AR7_GPIO_H__ + +#include + +#define AR7_GPIO_MAX 32 + +extern int gpio_request(unsigned gpio, const char *label); +extern void gpio_free(unsigned gpio); + +/* Common GPIO layer */ +static inline int gpio_get_value(unsigned gpio) +{ + void __iomem *gpio_in = + (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + AR7_GPIO_INPUT); + + return readl(gpio_in) & (1 << gpio); +} + +static inline void gpio_set_value(unsigned gpio, int value) +{ + void __iomem *gpio_out = + (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + AR7_GPIO_OUTPUT); + unsigned tmp; + + tmp = readl(gpio_out) & ~(1 << gpio); + if (value) + tmp |= 1 << gpio; + writel(tmp, gpio_out); +} + +static inline int gpio_direction_input(unsigned gpio) +{ + void __iomem *gpio_dir = + (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + AR7_GPIO_DIR); + + if (gpio >= AR7_GPIO_MAX) + return -EINVAL; + + writel(readl(gpio_dir) | (1 << gpio), gpio_dir); + + return 0; +} + +static inline int gpio_direction_output(unsigned gpio, int value) +{ + void __iomem *gpio_dir = + (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + AR7_GPIO_DIR); + + if (gpio >= AR7_GPIO_MAX) + return -EINVAL; + + gpio_set_value(gpio, value); + writel(readl(gpio_dir) & ~(1 << gpio), gpio_dir); + + return 0; +} + +static inline int gpio_to_irq(unsigned gpio) +{ + return -EINVAL; +} + +static inline int irq_to_gpio(unsigned irq) +{ + return -EINVAL; +} + +/* Board specific GPIO functions */ +static inline int ar7_gpio_enable(unsigned gpio) +{ + void __iomem *gpio_en = + (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + AR7_GPIO_ENABLE); + + writel(readl(gpio_en) | (1 << gpio), gpio_en); + + return 0; +} + +static inline int ar7_gpio_disable(unsigned gpio) +{ + void __iomem *gpio_en = + (void __iomem *)KSEG1ADDR(AR7_REGS_GPIO + AR7_GPIO_ENABLE); + + writel(readl(gpio_en) & ~(1 << gpio), gpio_en); + + return 0; +} + +#include + +#endif diff --git a/arch/mips/include/asm/mach-ar7/irq.h b/arch/mips/include/asm/mach-ar7/irq.h new file mode 100644 index 0000000..39e9757 --- /dev/null +++ b/arch/mips/include/asm/mach-ar7/irq.h @@ -0,0 +1,16 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Shamelessly copied from asm-mips/mach-emma2rh/ + * Copyright (C) 2003 by Ralf Baechle + */ +#ifndef __ASM_AR7_IRQ_H +#define __ASM_AR7_IRQ_H + +#define NR_IRQS 256 + +#include_next + +#endif /* __ASM_AR7_IRQ_H */ diff --git a/arch/mips/include/asm/mach-ar7/prom.h b/arch/mips/include/asm/mach-ar7/prom.h new file mode 100644 index 0000000..55f5939 --- /dev/null +++ b/arch/mips/include/asm/mach-ar7/prom.h @@ -0,0 +1,26 @@ +/* + * Copyright (C) 2006, 2007 Florian Fainelli + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __PROM_H__ +#define __PROM_H__ + +extern char *prom_getenv(const char *name); +extern void prom_printf(const char *fmt, ...) __attribute__((format(printf, 1, 2))); +extern void prom_meminit(void); + +#endif /* __PROM_H__ */ diff --git a/arch/mips/include/asm/mach-ar7/spaces.h b/arch/mips/include/asm/mach-ar7/spaces.h new file mode 100644 index 0000000..f4d1237 --- /dev/null +++ b/arch/mips/include/asm/mach-ar7/spaces.h @@ -0,0 +1,32 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1994 - 1999, 2000, 03, 04 Ralf Baechle + * Copyright (C) 2000, 2002 Maciej W. Rozycki + * Copyright (C) 1990, 1999, 2000 Silicon Graphics, Inc. + */ +#ifndef _ASM_AR7_SPACES_H +#define _ASM_AR7_SPACES_H + +#define CAC_BASE 0x80000000 +#define IO_BASE 0xa0000000 +#define UNCAC_BASE 0xa0000000 +#define MAP_BASE 0xc0000000 + +/* + * This handles the memory map. + * We handle pages at KSEG0 for kernels with 32 bit address space. + */ +#define PAGE_OFFSET 0x94000000UL +#define PHYS_OFFSET 0x14000000UL + +/* + * Memory above this physical address will be considered highmem. + */ +#ifndef HIGHMEM_START +#define HIGHMEM_START 0x40000000UL +#endif + +#endif /* __ASM_AR7_SPACES_H */ diff --git a/arch/mips/include/asm/mach-ar7/war.h b/arch/mips/include/asm/mach-ar7/war.h new file mode 100644 index 0000000..f4862b5 --- /dev/null +++ b/arch/mips/include/asm/mach-ar7/war.h @@ -0,0 +1,25 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle + */ +#ifndef __ASM_MIPS_MACH_AR7_WAR_H +#define __ASM_MIPS_MACH_AR7_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 0 +#define MIPS_CACHE_SYNC_WAR 0 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 0 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MIPS_MACH_AR7_WAR_H */ From f.fainelli@gmail.com Mon Jun 1 13:02:48 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 01 Jun 2009 13:02:54 +0100 (BST) Received: from ey-out-1920.google.com ([74.125.78.144]:10218 "EHLO ey-out-1920.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20025142AbZFAMCs (ORCPT ); Mon, 1 Jun 2009 13:02:48 +0100 Received: by ey-out-1920.google.com with SMTP id 4so387087eyg.54 for ; Mon, 01 Jun 2009 05:02:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:sender:from:date:subject :mime-version:x-uid:x-length:to:content-type :content-transfer-encoding:content-disposition:message-id; bh=OQeWa70m0wGo0odQ5VNZ7Go8WZmhr3w8/p+KV41xKeQ=; b=YhwEr1sVqiQFaaQ6UiWjKPEwP4DE6/NPB3dkUdjS2BMqGL8387heQSxL4nL53F0uaj raO034hIDrDwz8nfloyPjq0qoXeK/k6rbnpQW59dS2m+TJo9ShTMeIxPV6nLVPrXyHtn jBB1mxeiZeOfxZHUJ+cmE1eu3n5A3xc9VvhCU= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:from:date:subject:mime-version:x-uid:x-length:to :content-type:content-transfer-encoding:content-disposition :message-id; b=rD0fm+hImGNau6i+EbbiiXanl7Q3PoLBuQanHJlWbmIeRUGDrjSyDJL9mbJeEPIsTG 22Vgc+gygtpJTvPHsZWdlLUX3DtYViksRRuGVFU5cZZ4D2Few3Wlnpl/5NtRcFYgmY0W Qb6P945zN4bcikz0uROQHL7Cl5mxt8O2qK0C0= Received: by 10.210.29.9 with SMTP id c9mr3972061ebc.29.1243857758903; Mon, 01 Jun 2009 05:02:38 -0700 (PDT) Received: from florian.lab.openpattern.org (lab.openpattern.org [82.240.16.241]) by mx.google.com with ESMTPS id 7sm78172eyb.55.2009.06.01.05.02.37 (version=TLSv1/SSLv3 cipher=RC4-MD5); Mon, 01 Jun 2009 05:02:37 -0700 (PDT) From: Florian Fainelli Date: Mon, 1 Jun 2009 14:02:35 +0200 Subject: [PATCH 8/9] add ar7_defconfig MIME-Version: 1.0 X-UID: 180 X-Length: 24876 To: linux-mips@linux-mips.org, Ralf Baechle , openwrt-devel@lists.openwrt.org Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Content-Disposition: inline Message-Id: <200906011402.36081.florian@openwrt.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23107 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips This patch adds ar7_defconfig. Signed-off-by: Florian Fainelli --- diff --git a/arch/mips/configs/ar7_defconfig b/arch/mips/configs/ar7_defconfig new file mode 100644 index 0000000..be2771b --- /dev/null +++ b/arch/mips/configs/ar7_defconfig @@ -0,0 +1,988 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.30-rc6 +# Sun May 31 22:31:15 2009 +# +CONFIG_MIPS=y + +# +# Machine selection +# +# CONFIG_MACH_ALCHEMY is not set +CONFIG_AR7=y +# CONFIG_BASLER_EXCITE is not set +# CONFIG_BCM47XX is not set +# CONFIG_MIPS_COBALT is not set +# CONFIG_MACH_DECSTATION is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_LASAT is not set +# CONFIG_LEMOTE_FULONG is not set +# CONFIG_MIPS_MALTA is not set +# CONFIG_MIPS_SIM is not set +# CONFIG_NEC_MARKEINS is not set +# CONFIG_MACH_VR41XX is not set +# CONFIG_NXP_STB220 is not set +# CONFIG_NXP_STB225 is not set +# CONFIG_PNX8550_JBS is not set +# CONFIG_PNX8550_STB810 is not set +# CONFIG_PMC_MSP is not set +# CONFIG_PMC_YOSEMITE is not set +# CONFIG_SGI_IP22 is not set +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP28 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_CRHONE is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_BIGSUR is not set +# CONFIG_SNI_RM is not set +# CONFIG_MACH_TX39XX is not set +# CONFIG_MACH_TX49XX is not set +# CONFIG_MIKROTIK_RB532 is not set +# CONFIG_WR_PPMC is not set +# CONFIG_CAVIUM_OCTEON_SIMULATOR is not set +# CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD is not set +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_ARCH_SUPPORTS_OPROFILE=y +CONFIG_GENERIC_FIND_NEXT_BIT=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CMOS_UPDATE=y +CONFIG_SCHED_OMIT_FRAME_POINTER=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +CONFIG_CEVT_R4K_LIB=y +CONFIG_CEVT_R4K=y +CONFIG_CSRC_R4K_LIB=y +CONFIG_CSRC_R4K=y +CONFIG_DMA_NONCOHERENT=y +CONFIG_DMA_NEED_PCI_MAP_STATE=y +CONFIG_EARLY_PRINTK=y +CONFIG_SYS_HAS_EARLY_PRINTK=y +# CONFIG_HOTPLUG_CPU is not set +# CONFIG_NO_IOPORT is not set +CONFIG_GENERIC_GPIO=y +# CONFIG_CPU_BIG_ENDIAN is not set +CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y +CONFIG_IRQ_CPU=y +CONFIG_NO_EXCEPT_FILL=y +CONFIG_SWAP_IO_SPACE=y +CONFIG_BOOT_ELF32=y +CONFIG_MIPS_L1_CACHE_SHIFT=5 + +# +# CPU selection +# +# CONFIG_CPU_LOONGSON2 is not set +CONFIG_CPU_MIPS32_R1=y +# CONFIG_CPU_MIPS32_R2 is not set +# CONFIG_CPU_MIPS64_R1 is not set +# CONFIG_CPU_MIPS64_R2 is not set +# CONFIG_CPU_R3000 is not set +# CONFIG_CPU_TX39XX is not set +# CONFIG_CPU_VR41XX is not set +# CONFIG_CPU_R4300 is not set +# CONFIG_CPU_R4X00 is not set +# CONFIG_CPU_TX49XX is not set +# CONFIG_CPU_R5000 is not set +# CONFIG_CPU_R5432 is not set +# CONFIG_CPU_R5500 is not set +# CONFIG_CPU_R6000 is not set +# CONFIG_CPU_NEVADA is not set +# CONFIG_CPU_R8000 is not set +# CONFIG_CPU_R10000 is not set +# CONFIG_CPU_RM7000 is not set +# CONFIG_CPU_RM9000 is not set +# CONFIG_CPU_SB1 is not set +# CONFIG_CPU_CAVIUM_OCTEON is not set +CONFIG_SYS_HAS_CPU_MIPS32_R1=y +CONFIG_CPU_MIPS32=y +CONFIG_CPU_MIPSR1=y +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_HARDWARE_WATCHPOINTS=y + +# +# Kernel type +# +CONFIG_32BIT=y +# CONFIG_64BIT is not set +CONFIG_PAGE_SIZE_4KB=y +# CONFIG_PAGE_SIZE_8KB is not set +# CONFIG_PAGE_SIZE_16KB is not set +# CONFIG_PAGE_SIZE_32KB is not set +# CONFIG_PAGE_SIZE_64KB is not set +CONFIG_CPU_HAS_PREFETCH=y +CONFIG_MIPS_MT_DISABLED=y +# CONFIG_MIPS_MT_SMP is not set +# CONFIG_MIPS_MT_SMTC is not set +CONFIG_CPU_HAS_LLSC=y +CONFIG_CPU_HAS_SYNC=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_CPU_SUPPORTS_HIGHMEM=y +CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_ARCH_POPULATES_NODE_MAP=y +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=0 +CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y +CONFIG_HAVE_MLOCK=y +CONFIG_HAVE_MLOCKED_PAGE_BIT=y +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +# CONFIG_HZ_48 is not set +# CONFIG_HZ_100 is not set +# CONFIG_HZ_128 is not set +CONFIG_HZ_250=y +# CONFIG_HZ_256 is not set +# CONFIG_HZ_1000 is not set +# CONFIG_HZ_1024 is not set +CONFIG_SYS_SUPPORTS_ARBIT_HZ=y +CONFIG_HZ=250 +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set +# CONFIG_PREEMPT is not set +CONFIG_KEXEC=y +CONFIG_SECCOMP=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="" +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_POSIX_MQUEUE=y +CONFIG_POSIX_MQUEUE_SYSCTL=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y +CONFIG_TASKSTATS=y +CONFIG_TASK_DELAY_ACCT=y +CONFIG_TASK_XACCT=y +CONFIG_TASK_IO_ACCOUNTING=y +CONFIG_AUDIT=y + +# +# RCU Subsystem +# +CONFIG_CLASSIC_RCU=y +# CONFIG_TREE_RCU is not set +# CONFIG_PREEMPT_RCU is not set +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_PREEMPT_RCU_TRACE is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=17 +CONFIG_GROUP_SCHED=y +CONFIG_FAIR_GROUP_SCHED=y +# CONFIG_RT_GROUP_SCHED is not set +# CONFIG_USER_SCHED is not set +CONFIG_CGROUP_SCHED=y +CONFIG_CGROUPS=y +# CONFIG_CGROUP_DEBUG is not set +CONFIG_CGROUP_NS=y +CONFIG_CGROUP_FREEZER=y +CONFIG_CGROUP_DEVICE=y +CONFIG_CPUSETS=y +CONFIG_PROC_PID_CPUSET=y +CONFIG_CGROUP_CPUACCT=y +# CONFIG_RESOURCE_COUNTERS is not set +# CONFIG_SYSFS_DEPRECATED_V2 is not set +CONFIG_RELAY=y +CONFIG_NAMESPACES=y +CONFIG_UTS_NS=y +CONFIG_IPC_NS=y +CONFIG_USER_NS=y +CONFIG_PID_NS=y +CONFIG_NET_NS=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_RD_GZIP=y +# CONFIG_RD_BZIP2 is not set +# CONFIG_RD_LZMA is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +CONFIG_EMBEDDED=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_EXTRA_PASS is not set +# CONFIG_STRIP_ASM_SYMS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_PCSPKR_PLATFORM=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_VM_EVENT_COUNTERS=y +# CONFIG_COMPAT_BRK is not set +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +CONFIG_PROFILING=y +CONFIG_TRACEPOINTS=y +CONFIG_MARKERS=y +CONFIG_OPROFILE=m +CONFIG_HAVE_OPROFILE=y +# CONFIG_SLOW_WORK is not set +# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +CONFIG_MODULE_FORCE_LOAD=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +CONFIG_MODVERSIONS=y +# CONFIG_MODULE_SRCVERSION_ALL is not set +CONFIG_BLOCK=y +CONFIG_LBD=y +CONFIG_BLK_DEV_BSG=y +CONFIG_BLK_DEV_INTEGRITY=y + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +# CONFIG_DEFAULT_AS is not set +# CONFIG_DEFAULT_DEADLINE is not set +CONFIG_DEFAULT_CFQ=y +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="cfq" +CONFIG_PROBE_INITRD_HEADER=y +CONFIG_FREEZER=y + +# +# Bus options (PCI, PCMCIA, EISA, ISA, TC) +# +# CONFIG_ARCH_SUPPORTS_MSI is not set +CONFIG_MMU=y +# CONFIG_PCCARD is not set + +# +# Executable file formats +# +CONFIG_BINFMT_ELF=y +CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y +# CONFIG_HAVE_AOUT is not set +CONFIG_BINFMT_MISC=m +CONFIG_TRAD_SIGNALS=y + +# +# Power management options +# +CONFIG_ARCH_SUSPEND_POSSIBLE=y +# CONFIG_PM is not set +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_PACKET_MMAP=y +CONFIG_UNIX=y +# CONFIG_NET_KEY is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_ASK_IP_FIB_HASH=y +# CONFIG_IP_FIB_TRIE is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_IP_ROUTE_MULTIPATH=y +CONFIG_IP_ROUTE_VERBOSE=y +# CONFIG_IP_PNP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +CONFIG_IP_MROUTE=y +CONFIG_IP_PIMSM_V1=y +CONFIG_IP_PIMSM_V2=y +# CONFIG_ARPD is not set +CONFIG_SYN_COOKIES=y +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +CONFIG_INET_LRO=y +# CONFIG_INET_DIAG is not set +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +# CONFIG_IPV6 is not set +CONFIG_NETWORK_SECMARK=y +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_SCTP_HMAC_NONE is not set +# CONFIG_SCTP_HMAC_SHA1 is not set +# CONFIG_SCTP_HMAC_MD5 is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_PHONET is not set +# CONFIG_NET_SCHED is not set +# CONFIG_DCB is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_NET_DROP_MONITOR is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set +CONFIG_FIB_RULES=y +# CONFIG_WIRELESS is not set +# CONFIG_WIMAX is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +# CONFIG_FIRMWARE_IN_KERNEL is not set +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_CONNECTOR is not set +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +CONFIG_MTD_CONCAT=y +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_TESTS is not set +# CONFIG_MTD_REDBOOT_PARTS is not set +# CONFIG_MTD_CMDLINE_PARTS is not set +CONFIG_MTD_AR7_PARTS=y + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_MTD_OOPS is not set + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=y +CONFIG_MTD_JEDECPROBE=y +CONFIG_MTD_GEN_PROBE=y +# CONFIG_MTD_CFI_ADV_OPTIONS is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +CONFIG_MTD_CFI_INTELEXT=y +CONFIG_MTD_CFI_AMDSTD=y +CONFIG_MTD_CFI_STAA=y +CONFIG_MTD_CFI_UTIL=y +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +CONFIG_MTD_COMPLEX_MAPPINGS=y +CONFIG_MTD_PHYSMAP=y +CONFIG_MTD_PHYSMAP_COMPAT=y +CONFIG_MTD_PHYSMAP_START=0x1fc00000 +CONFIG_MTD_PHYSMAP_LEN=0 +CONFIG_MTD_PHYSMAP_BANKWIDTH=2 +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +# CONFIG_MTD_NAND is not set +# CONFIG_MTD_ONENAND is not set + +# +# LPDDR flash memory drivers +# +CONFIG_MTD_LPDDR=m +CONFIG_MTD_QINFO_PROBE=m + +# +# UBI - Unsorted block images +# +# CONFIG_MTD_UBI is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_COW_COMMON is not set +# CONFIG_BLK_DEV_LOOP is not set +# CONFIG_BLK_DEV_NBD is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=8192 +# CONFIG_BLK_DEV_XIP is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +# CONFIG_BLK_DEV_HD is not set +# CONFIG_MISC_DEVICES is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +# CONFIG_SCSI is not set +# CONFIG_SCSI_DMA is not set +# CONFIG_SCSI_NETLINK is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +CONFIG_NETDEVICES=y +CONFIG_COMPAT_NET_DEV_OPS=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_VETH is not set +CONFIG_PHYLIB=y + +# +# MII PHY device drivers +# +# CONFIG_MARVELL_PHY is not set +# CONFIG_DAVICOM_PHY is not set +# CONFIG_QSEMI_PHY is not set +# CONFIG_LXT_PHY is not set +# CONFIG_CICADA_PHY is not set +# CONFIG_VITESSE_PHY is not set +# CONFIG_SMSC_PHY is not set +# CONFIG_BROADCOM_PHY is not set +# CONFIG_ICPLUS_PHY is not set +# CONFIG_REALTEK_PHY is not set +# CONFIG_NATIONAL_PHY is not set +# CONFIG_STE10XP is not set +# CONFIG_LSI_ET1011C_PHY is not set +# CONFIG_FIXED_PHY is not set +# CONFIG_MDIO_BITBANG is not set +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +# CONFIG_AX88796 is not set +# CONFIG_SMC91X is not set +# CONFIG_DM9000 is not set +# CONFIG_ETHOC is not set +# CONFIG_DNET is not set +# CONFIG_IBM_NEW_EMAC_ZMII is not set +# CONFIG_IBM_NEW_EMAC_RGMII is not set +# CONFIG_IBM_NEW_EMAC_TAH is not set +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set +# CONFIG_B44 is not set +CONFIG_CPMAC=y +# CONFIG_NETDEV_1000 is not set +# CONFIG_NETDEV_10000 is not set + +# +# Wireless LAN +# +# CONFIG_WLAN_PRE80211 is not set +# CONFIG_WLAN_80211 is not set + +# +# Enable WiMAX (Networking options) to see the WiMAX drivers +# +# CONFIG_WAN is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_ISDN is not set +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set + +# +# Userland interfaces +# +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +# CONFIG_INPUT_EVDEV is not set +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +CONFIG_DEVKMEM=y +CONFIG_SERIAL_NONSTANDARD=y +# CONFIG_N_HDLC is not set +# CONFIG_RISCOM8 is not set +# CONFIG_SPECIALIX is not set +# CONFIG_RIO is not set +# CONFIG_STALDRV is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_NR_UARTS=32 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +# CONFIG_SERIAL_8250_EXTENDED is not set + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_UNIX98_PTYS=y +CONFIG_DEVPTS_MULTIPLE_INSTANCES=y +# CONFIG_LEGACY_PTYS is not set +# CONFIG_IPMI_HANDLER is not set +# CONFIG_HW_RANDOM is not set +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +# CONFIG_I2C is not set +# CONFIG_SPI is not set +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +CONFIG_THERMAL_HWMON=y +CONFIG_WATCHDOG=y +# CONFIG_WATCHDOG_NOWAYOUT is not set + +# +# Watchdog Device Drivers +# +# CONFIG_SOFT_WATCHDOG is not set +CONFIG_AR7_WDT=y +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_REGULATOR is not set + +# +# Multimedia devices +# + +# +# Multimedia core support +# +# CONFIG_VIDEO_DEV is not set +# CONFIG_DVB_CORE is not set +# CONFIG_VIDEO_MEDIA is not set + +# +# Multimedia drivers +# +# CONFIG_DAB is not set + +# +# Graphics support +# +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +# CONFIG_FB is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set + +# +# Console display driver support +# +# CONFIG_VGA_CONSOLE is not set +CONFIG_DUMMY_CONSOLE=y +# CONFIG_SOUND is not set +# CONFIG_HID_SUPPORT is not set +# CONFIG_USB_SUPPORT is not set +# CONFIG_MMC is not set +# CONFIG_MEMSTICK is not set +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y + +# +# LED drivers +# +CONFIG_LEDS_GPIO=y +CONFIG_LEDS_GPIO_PLATFORM=y + +# +# LED Triggers +# +CONFIG_LEDS_TRIGGERS=y +# CONFIG_LEDS_TRIGGER_TIMER is not set +# CONFIG_LEDS_TRIGGER_HEARTBEAT is not set +# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set +CONFIG_LEDS_TRIGGER_DEFAULT_ON=y + +# +# iptables trigger is under Netfilter config (LED target) +# +# CONFIG_ACCESSIBILITY is not set +CONFIG_RTC_LIB=y +# CONFIG_RTC_CLASS is not set +# CONFIG_DMADEVICES is not set +# CONFIG_AUXDISPLAY is not set +# CONFIG_UIO is not set + +# +# TI VLYNQ +# +CONFIG_VLYNQ=y +# CONFIG_STAGING is not set + +# +# File systems +# +# CONFIG_EXT2_FS is not set +# CONFIG_EXT3_FS is not set +# CONFIG_EXT4_FS is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +CONFIG_FS_POSIX_ACL=y +# CONFIG_FILE_LOCKING is not set +# CONFIG_XFS_FS is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_BTRFS_FS is not set +# CONFIG_DNOTIFY is not set +# CONFIG_INOTIFY is not set +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set +CONFIG_GENERIC_ACL=y + +# +# Caches +# +# CONFIG_FSCACHE is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +# CONFIG_MSDOS_FS is not set +# CONFIG_VFAT_FS is not set +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_KCORE=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +# CONFIG_HUGETLB_PAGE is not set +CONFIG_CONFIGFS_FS=m +# CONFIG_MISC_FILESYSTEMS is not set +# CONFIG_NETWORK_FILESYSTEMS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y +# CONFIG_NLS is not set +# CONFIG_DLM is not set + +# +# Kernel hacking +# +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +# CONFIG_PRINTK_TIME is not set +# CONFIG_ENABLE_WARN_DEPRECATED is not set +# CONFIG_ENABLE_MUST_CHECK is not set +CONFIG_FRAME_WARN=1024 +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_UNUSED_SYMBOLS is not set +CONFIG_DEBUG_FS=y +# CONFIG_HEADERS_CHECK is not set +# CONFIG_DEBUG_KERNEL is not set +CONFIG_STACKTRACE=y +# CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +# CONFIG_SYSCTL_SYSCALL_CHECK is not set +CONFIG_NOP_TRACER=y +CONFIG_RING_BUFFER=y +CONFIG_TRACING=y +CONFIG_TRACING_SUPPORT=y + +# +# Tracers +# +# CONFIG_IRQSOFF_TRACER is not set +# CONFIG_SCHED_TRACER is not set +CONFIG_CONTEXT_SWITCH_TRACER=y +# CONFIG_EVENT_TRACER is not set +CONFIG_BOOT_TRACER=y +# CONFIG_TRACE_BRANCH_PROFILING is not set +# CONFIG_KMEMTRACE is not set +# CONFIG_WORKQUEUE_TRACER is not set +CONFIG_BLK_DEV_IO_TRACE=y +# CONFIG_FTRACE_STARTUP_TEST is not set +# CONFIG_DYNAMIC_DEBUG is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +CONFIG_CMDLINE="" + +# +# Security options +# +CONFIG_KEYS=y +# CONFIG_KEYS_DEBUG_PROC_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +# CONFIG_SECURITY_FILE_CAPABILITIES is not set +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +CONFIG_CRYPTO_FIPS=y +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD=m +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_BLKCIPHER=m +CONFIG_CRYPTO_BLKCIPHER2=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG=m +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_PCOMP=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +CONFIG_CRYPTO_GF128MUL=m +CONFIG_CRYPTO_NULL=m +CONFIG_CRYPTO_WORKQUEUE=y +# CONFIG_CRYPTO_CRYPTD is not set +CONFIG_CRYPTO_AUTHENC=m +CONFIG_CRYPTO_TEST=m + +# +# Authenticated Encryption with Associated Data +# +CONFIG_CRYPTO_CCM=m +CONFIG_CRYPTO_GCM=m +CONFIG_CRYPTO_SEQIV=m + +# +# Block modes +# +CONFIG_CRYPTO_CBC=m +CONFIG_CRYPTO_CTR=m +CONFIG_CRYPTO_CTS=m +CONFIG_CRYPTO_ECB=m +CONFIG_CRYPTO_LRW=m +CONFIG_CRYPTO_PCBC=m +CONFIG_CRYPTO_XTS=m + +# +# Hash modes +# +CONFIG_CRYPTO_HMAC=m +CONFIG_CRYPTO_XCBC=m + +# +# Digest +# +CONFIG_CRYPTO_CRC32C=m +CONFIG_CRYPTO_MD4=m +CONFIG_CRYPTO_MD5=y +CONFIG_CRYPTO_MICHAEL_MIC=m +CONFIG_CRYPTO_RMD128=m +CONFIG_CRYPTO_RMD160=m +CONFIG_CRYPTO_RMD256=m +CONFIG_CRYPTO_RMD320=m +CONFIG_CRYPTO_SHA1=m +CONFIG_CRYPTO_SHA256=m +CONFIG_CRYPTO_SHA512=m +CONFIG_CRYPTO_TGR192=m +CONFIG_CRYPTO_WP512=m + +# +# Ciphers +# +CONFIG_CRYPTO_AES=m +CONFIG_CRYPTO_ANUBIS=m +CONFIG_CRYPTO_ARC4=m +CONFIG_CRYPTO_BLOWFISH=m +CONFIG_CRYPTO_CAMELLIA=m +CONFIG_CRYPTO_CAST5=m +CONFIG_CRYPTO_CAST6=m +CONFIG_CRYPTO_DES=m +CONFIG_CRYPTO_FCRYPT=m +CONFIG_CRYPTO_KHAZAD=m +CONFIG_CRYPTO_SALSA20=m +CONFIG_CRYPTO_SEED=m +CONFIG_CRYPTO_SERPENT=m +CONFIG_CRYPTO_TEA=m +CONFIG_CRYPTO_TWOFISH=m +CONFIG_CRYPTO_TWOFISH_COMMON=m + +# +# Compression +# +CONFIG_CRYPTO_DEFLATE=m +# CONFIG_CRYPTO_ZLIB is not set +CONFIG_CRYPTO_LZO=m + +# +# Random Number Generation +# +CONFIG_CRYPTO_ANSI_CPRNG=m +CONFIG_CRYPTO_HW=y +CONFIG_BINARY_PRINTF=y + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_GENERIC_FIND_LAST_BIT=y +CONFIG_CRC_CCITT=m +CONFIG_CRC16=m +CONFIG_CRC_T10DIF=m +CONFIG_CRC_ITU_T=m +CONFIG_CRC32=y +CONFIG_CRC7=m +CONFIG_LIBCRC32C=m +CONFIG_AUDIT_GENERIC=y +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=m +CONFIG_LZO_COMPRESS=m +CONFIG_LZO_DECOMPRESS=m +CONFIG_DECOMPRESS_GZIP=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y +CONFIG_NLATTR=y From f.fainelli@gmail.com Mon Jun 1 13:03:12 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 01 Jun 2009 13:03:19 +0100 (BST) Received: from mail-ew0-f219.google.com ([209.85.219.219]:65516 "EHLO mail-ew0-f219.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20025144AbZFAMDM (ORCPT ); Mon, 1 Jun 2009 13:03:12 +0100 Received: by ewy19 with SMTP id 19so8029459ewy.0 for ; Mon, 01 Jun 2009 05:03:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:sender:from:date:subject :mime-version:x-uid:x-length:to:content-type :content-transfer-encoding:content-disposition:message-id; bh=dIYrGSN2JMBbwOtvvhOEw5tyDj3vTKCl2dZyo+AzRNA=; b=RWZhiVVhNBLq5J09NQUWTSl6BSmQO96OiTU/a5FDXORQIj3CI6etzo9ytlWhLjPE5+ W4q+vnHXeJnlXAogQId1ZUrwbmcJ1hvbBacEszZ+sQ4Dz3elA6izJm4qFLn8h8ePbnt7 aXtD1HDuUhY3M69K/f6KmTfUilWhMQQDIbgiY= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:from:date:subject:mime-version:x-uid:x-length:to :content-type:content-transfer-encoding:content-disposition :message-id; b=X809HlBvICkbzA3pJouVnAvSA87aNptpi38f0IDJmIR8X7TJJ64A1gQFD8V44K9WNr 8xAT8BQMiRKEHo7XYhpn354OYdB0CvYNY4ZglsdG7ASHQBJ7n+Jj64bBr6UmFBuA6QSO UGypWbzoCroQm73xn5VXYZn6fpxro1FSQjDug= Received: by 10.210.30.1 with SMTP id d1mr6312503ebd.50.1243857786366; Mon, 01 Jun 2009 05:03:06 -0700 (PDT) Received: from florian.lab.openpattern.org (lab.openpattern.org [82.240.16.241]) by mx.google.com with ESMTPS id 23sm85274eya.29.2009.06.01.05.03.05 (version=TLSv1/SSLv3 cipher=RC4-MD5); Mon, 01 Jun 2009 05:03:06 -0700 (PDT) From: Florian Fainelli Date: Mon, 1 Jun 2009 14:03:04 +0200 Subject: [PATCH 9/9] wire in AR7 support. MIME-Version: 1.0 X-UID: 181 X-Length: 2084 To: linux-mips@linux-mips.org, Ralf Baechle , openwrt-devel@lists.openwrt.org Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Content-Disposition: inline Message-Id: <200906011403.04327.florian@openwrt.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23108 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips This patch wires in the AR7 support in the MIPS architecture. Signed-off-by: Florian Fainelli --- diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index c4a84a6..0a75275 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -22,6 +22,22 @@ choice config MACH_ALCHEMY bool "Alchemy processor based machines" +config AR7 + bool "Texas Instruments AR7" + select BOOT_ELF32 + select DMA_NONCOHERENT + select CEVT_R4K + select CSRC_R4K + select IRQ_CPU + select NO_EXCEPT_FILL + select SWAP_IO_SPACE + select SYS_HAS_CPU_MIPS32_R1 + select SYS_HAS_EARLY_PRINTK + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_KGDB + select SYS_SUPPORTS_LITTLE_ENDIAN + select GENERIC_GPIO + config BASLER_EXCITE bool "Basler eXcite smart camera" select CEVT_R4K diff --git a/arch/mips/Makefile b/arch/mips/Makefile index c4cae9e..5e7b3b4 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -174,6 +174,13 @@ libs-$(CONFIG_SIBYTE_CFE) += arch/mips/sibyte/cfe/ # # +# Texas Instruments AR7 +# +core-$(CONFIG_AR7) += arch/mips/ar7/ +cflags-$(CONFIG_AR7) += -I$(srctree)/arch/mips/include/asm/mach-ar7 +load-$(CONFIG_AR7) += 0xffffffff94100000 + +# # Acer PICA 61, Mips Magnum 4000 and Olivetti M700. # core-$(CONFIG_MACH_JAZZ) += arch/mips/jazz/ From ralf@h5.dl5rb.org.uk Mon Jun 1 15:29:01 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 01 Jun 2009 15:29:08 +0100 (BST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:49073 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20025263AbZFAO3B (ORCPT ); Mon, 1 Jun 2009 15:29:01 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id n51ESaiB009836; Mon, 1 Jun 2009 15:28:37 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id n51ESZoJ009834; Mon, 1 Jun 2009 15:28:35 +0100 Date: Mon, 1 Jun 2009 15:28:35 +0100 From: Ralf Baechle To: Florian Fainelli Cc: linux-mips@linux-mips.org, Maxime Bizon Subject: Re: [PATCH 01/10] bcm63xx: convert to use gpiolib Message-ID: <20090601142835.GA6604@linux-mips.org> References: <200905312025.48300.florian@openwrt.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <200905312025.48300.florian@openwrt.org> User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23109 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Sun, May 31, 2009 at 08:25:47PM +0200, Florian Fainelli wrote: Folded into the existing patchset, thanks! Ralf From ralf@h5.dl5rb.org.uk Mon Jun 1 15:29:57 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 01 Jun 2009 15:30:05 +0100 (BST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:49079 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20025327AbZFAO3s (ORCPT ); Mon, 1 Jun 2009 15:29:48 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id n51ETPOe009859; Mon, 1 Jun 2009 15:29:25 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id n51ETPAW009858; Mon, 1 Jun 2009 15:29:25 +0100 Date: Mon, 1 Jun 2009 15:29:25 +0100 From: Ralf Baechle To: Florian Fainelli Cc: linux-mips@linux-mips.org, Maxime Bizon Subject: Re: [PATCH 02/10] bcm63xx: add new BCM6348-based board definitions Message-ID: <20090601142925.GB6604@linux-mips.org> References: <200905312026.19705.florian@openwrt.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <200905312026.19705.florian@openwrt.org> User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23110 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Sun, May 31, 2009 at 08:26:19PM +0200, Florian Fainelli wrote: Folded into the existing patchset after removing the bloody trailing whitespaces added by it. Thanks, Ralf From ralf@h5.dl5rb.org.uk Mon Jun 1 15:30:42 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 01 Jun 2009 15:30:49 +0100 (BST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:49087 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20025331AbZFAOam (ORCPT ); Mon, 1 Jun 2009 15:30:42 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id n51EUIkq009883; Mon, 1 Jun 2009 15:30:18 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id n51EUIvc009882; Mon, 1 Jun 2009 15:30:18 +0100 Date: Mon, 1 Jun 2009 15:30:18 +0100 From: Ralf Baechle To: Florian Fainelli Cc: linux-mips@linux-mips.org, Maxime Bizon Subject: Re: [PATCH 03/10] bcm63xx: add new BCM6358-based board definitions Message-ID: <20090601143018.GC6604@linux-mips.org> References: <200905312026.50533.florian@openwrt.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <200905312026.50533.florian@openwrt.org> User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23111 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Sun, May 31, 2009 at 08:26:50PM +0200, Florian Fainelli wrote: Also folded into the existing series. Thanks, Ralf From ralf@h5.dl5rb.org.uk Mon Jun 1 15:41:36 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 01 Jun 2009 15:41:44 +0100 (BST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:42993 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20025340AbZFAOlg (ORCPT ); Mon, 1 Jun 2009 15:41:36 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id n51EfDnd011416; Mon, 1 Jun 2009 15:41:13 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id n51EfDmN011414; Mon, 1 Jun 2009 15:41:13 +0100 Date: Mon, 1 Jun 2009 15:41:13 +0100 From: Ralf Baechle To: Florian Fainelli Cc: linux-mips@linux-mips.org, Maxime Bizon Subject: Re: [PATCH 05/10] bcm63xx: dev-enet: initialize shared_device_registered to 0 Message-ID: <20090601144113.GD6604@linux-mips.org> References: <200905312028.37498.florian@openwrt.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <200905312028.37498.florian@openwrt.org> User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23112 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Sun, May 31, 2009 at 08:28:37PM +0200, Florian Fainelli wrote: > This patch initialize the shared_device_registered > variable with 0, actually required for the check > to be working. > > Signed-off-by: Maxime Bizon > Signed-off-by: Florian Fainelli > --- > diff --git a/arch/mips/bcm63xx/dev-enet.c b/arch/mips/bcm63xx/dev-enet.c > index 51c2e5a..0298973 100644 > --- a/arch/mips/bcm63xx/dev-enet.c > +++ b/arch/mips/bcm63xx/dev-enet.c > @@ -28,7 +28,7 @@ static struct platform_device bcm63xx_enet_shared_device = { > .resource = shared_res, > }; > > -static int shared_device_registered; > +static int shared_device_registered = 0; This is bogus. The variable defaults to zero. Explicit initialization however will inflate the .data section. Dropped. Ralf From ralf@h5.dl5rb.org.uk Mon Jun 1 15:42:33 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 01 Jun 2009 15:42:42 +0100 (BST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:42999 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20025340AbZFAOmR (ORCPT ); Mon, 1 Jun 2009 15:42:17 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id n51EfsbP011437; Mon, 1 Jun 2009 15:41:54 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id n51EfsHL011436; Mon, 1 Jun 2009 15:41:54 +0100 Date: Mon, 1 Jun 2009 15:41:54 +0100 From: Ralf Baechle To: Florian Fainelli Cc: linux-mips@linux-mips.org, Maxime Bizon Subject: Re: [PATCH 06/10] bcm63xx: zero initialize mac_addr_used. Message-ID: <20090601144154.GE6604@linux-mips.org> References: <200905312029.07558.florian@openwrt.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <200905312029.07558.florian@openwrt.org> User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23113 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Sun, May 31, 2009 at 08:29:07PM +0200, Florian Fainelli wrote: > This patch initializes mac_addr_used to zero, the checks > against it later would not work properly. > > Signed-off-by: Maxime Bizon > Signed-off-by: Florian Fainelli > --- > diff --git a/arch/mips/bcm63xx/boards/board_bcm963xx.c b/arch/mips/bcm63xx/boards/board_bcm963xx.c > index 78a40e7..298804a 100644 > --- a/arch/mips/bcm63xx/boards/board_bcm963xx.c > +++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c > @@ -32,7 +32,7 @@ > #define PFX "board_bcm963xx: " > > static struct bcm963xx_nvram nvram; > -static unsigned int mac_addr_used; > +static unsigned int mac_addr_used = 0; Ditto - the variable defaults to zero. Explicit initialization however will inflate the .data section. Dropped. Ralf From ralf@h5.dl5rb.org.uk Mon Jun 1 15:46:41 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 01 Jun 2009 15:46:49 +0100 (BST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:38230 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20025334AbZFAOql (ORCPT ); Mon, 1 Jun 2009 15:46:41 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id n51EkIcL011853; Mon, 1 Jun 2009 15:46:18 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id n51EkIS1011851; Mon, 1 Jun 2009 15:46:18 +0100 Date: Mon, 1 Jun 2009 15:46:18 +0100 From: Ralf Baechle To: Florian Fainelli Cc: linux-mips@linux-mips.org, Maxime Bizon Subject: Re: [PATCH 07/10] bcm63xx: fix typo when printing CPU frequency Message-ID: <20090601144618.GF6604@linux-mips.org> References: <200905312029.50326.florian@openwrt.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <200905312029.50326.florian@openwrt.org> User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23114 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Sun, May 31, 2009 at 08:29:49PM +0200, Florian Fainelli wrote: > This patch corrects the comment about the CPU > frequency which is actually printed in Hz and not MHz. > > Signed-off-by: Florian Fainelli > --- > diff --git a/arch/mips/bcm63xx/cpu.c b/arch/mips/bcm63xx/cpu.c > index 0a403dd..410c788 100644 > --- a/arch/mips/bcm63xx/cpu.c > +++ b/arch/mips/bcm63xx/cpu.c > @@ -238,7 +238,7 @@ void __init bcm63xx_cpu_init(void) > > printk(KERN_INFO "Detected Broadcom 0x%04x CPU revision %02x\n", > bcm63xx_cpu_id, bcm63xx_cpu_rev); > - printk(KERN_INFO "CPU frequency is %u MHz\n", > + printk(KERN_INFO "CPU frequency is %u Hz\n", While technically ok I would suggest to print the number in MHz. Acuracy probably doesn't matter so even rounding to whole MHz would be ok. Want me to apply anyway? Ralf From ralf@h5.dl5rb.org.uk Mon Jun 1 15:49:38 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 01 Jun 2009 15:49:45 +0100 (BST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:38241 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20025360AbZFAOti (ORCPT ); Mon, 1 Jun 2009 15:49:38 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id n51EnFVX012282; Mon, 1 Jun 2009 15:49:15 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id n51EnFCJ012280; Mon, 1 Jun 2009 15:49:15 +0100 Date: Mon, 1 Jun 2009 15:49:15 +0100 From: Ralf Baechle To: Florian Fainelli Cc: linux-mips@linux-mips.org, Maxime Bizon Subject: Re: [PATCH 08/10] bcm63xx: update defconfig with gpiolib Message-ID: <20090601144915.GG6604@linux-mips.org> References: <200905312030.38974.florian@openwrt.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <200905312030.38974.florian@openwrt.org> User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23115 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Sun, May 31, 2009 at 08:30:38PM +0200, Florian Fainelli wrote: Folded into the existing patchset. Thanks, Ralf From f.fainelli@gmail.com Mon Jun 1 15:51:10 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 01 Jun 2009 15:51:16 +0100 (BST) Received: from mail-ew0-f219.google.com ([209.85.219.219]:35679 "EHLO mail-ew0-f219.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20025360AbZFAOvK convert rfc822-to-8bit (ORCPT ); Mon, 1 Jun 2009 15:51:10 +0100 Received: by ewy19 with SMTP id 19so8156403ewy.0 for ; Mon, 01 Jun 2009 07:51:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:sender:from:to:subject:date :user-agent:cc:references:in-reply-to:mime-version:content-type :content-transfer-encoding:content-disposition:message-id; bh=MFeAdzCKk2qaNt4TOz7p0XGtjhw0aPHCqzdnWwgHk+o=; b=ME6Iv7Pra85Pzh8kq5QXNjACiF0kOR+lANjAipK6czsXza2gvHnFYxZH1IRGbvlTTa pyYu85at+F1uBizSw7K2XAVhIGYKdcACAssV4ABuo2QKEcTYi1lAajCqqNzOkUE2NYVg grmgJwZcxyXQ75tcganxIWAIdrAW1u/eQ3h+c= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:from:to:subject:date:user-agent:cc:references:in-reply-to :mime-version:content-type:content-transfer-encoding :content-disposition:message-id; b=I6ajgHp74XwuEBss5IB1mFo1u1S/U1UZ30S1KE+Tx8bZybKtelR04JH+ayNEzxbQQC naq1LEUvY5VvqOHSBFbMOqpBrnBf62JnGJ7yqnzEv14bI3G1O0wAGxtX8Oj0p0e4zDoD INq/+k8sYlwumaBHlfwGEEc6dTVOqqkyunb9U= Received: by 10.210.16.11 with SMTP id 11mr1067375ebp.83.1243867864227; Mon, 01 Jun 2009 07:51:04 -0700 (PDT) Received: from florian.lab.openpattern.org (lab.openpattern.org [82.240.16.241]) by mx.google.com with ESMTPS id 10sm282775eyd.22.2009.06.01.07.51.03 (version=TLSv1/SSLv3 cipher=RC4-MD5); Mon, 01 Jun 2009 07:51:03 -0700 (PDT) From: Florian Fainelli To: Ralf Baechle Subject: Re: [PATCH 07/10] bcm63xx: fix typo when printing CPU frequency Date: Mon, 1 Jun 2009 16:50:58 +0200 User-Agent: KMail/1.9.9 Cc: linux-mips@linux-mips.org, Maxime Bizon References: <200905312029.50326.florian@openwrt.org> <20090601144618.GF6604@linux-mips.org> In-Reply-To: <20090601144618.GF6604@linux-mips.org> MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 8BIT Content-Disposition: inline Message-Id: <200906011650.59851.florian@openwrt.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23116 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips Le Monday 01 June 2009 16:46:18 Ralf Baechle, vous avez écrit : > On Sun, May 31, 2009 at 08:29:49PM +0200, Florian Fainelli wrote: > > This patch corrects the comment about the CPU > > frequency which is actually printed in Hz and not MHz. > > > > Signed-off-by: Florian Fainelli > > --- > > diff --git a/arch/mips/bcm63xx/cpu.c b/arch/mips/bcm63xx/cpu.c > > index 0a403dd..410c788 100644 > > --- a/arch/mips/bcm63xx/cpu.c > > +++ b/arch/mips/bcm63xx/cpu.c > > @@ -238,7 +238,7 @@ void __init bcm63xx_cpu_init(void) > > > > printk(KERN_INFO "Detected Broadcom 0x%04x CPU revision %02x\n", > > bcm63xx_cpu_id, bcm63xx_cpu_rev); > > - printk(KERN_INFO "CPU frequency is %u MHz\n", > > + printk(KERN_INFO "CPU frequency is %u Hz\n", > > While technically ok I would suggest to print the number in MHz. Acuracy > probably doesn't matter so even rounding to whole MHz would be ok. > > Want me to apply anyway? No that is a one-liner I will respin a new one which prints the frequency in Mhz directly. -- Best regards, Florian Fainelli Email : florian@openwrt.org http://openwrt.org ------------------------------- From ralf@h5.dl5rb.org.uk Mon Jun 1 15:52:05 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 01 Jun 2009 15:52:13 +0100 (BST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:49285 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20025368AbZFAOwF (ORCPT ); Mon, 1 Jun 2009 15:52:05 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id n51EpgvJ012411; Mon, 1 Jun 2009 15:51:42 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id n51Epg4h012409; Mon, 1 Jun 2009 15:51:42 +0100 Date: Mon, 1 Jun 2009 15:51:42 +0100 From: Ralf Baechle To: Florian Fainelli Cc: linux-mips@linux-mips.org, Maxime Bizon Subject: Re: [PATCH 09/10] bcm63xx: enable SSB bus support in defconfig Message-ID: <20090601145142.GH6604@linux-mips.org> References: <200905312031.06050.florian@openwrt.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <200905312031.06050.florian@openwrt.org> User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23117 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Folded into the existing series as well. Thanks, Ralf From ralf@h5.dl5rb.org.uk Mon Jun 1 15:56:15 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 01 Jun 2009 15:56:22 +0100 (BST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:49302 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20025378AbZFAO4P (ORCPT ); Mon, 1 Jun 2009 15:56:15 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id n51Etqfq012753; Mon, 1 Jun 2009 15:55:52 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id n51EtqnC012751; Mon, 1 Jun 2009 15:55:52 +0100 Date: Mon, 1 Jun 2009 15:55:52 +0100 From: Ralf Baechle To: Florian Fainelli Cc: linux-mips@linux-mips.org, Maxime Bizon Subject: Re: [PATCH 10/10] bcm63xx: compile fixes for bcm63xx_enet.c Message-ID: <20090601145552.GI6604@linux-mips.org> References: <200905312031.35241.florian@openwrt.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <200905312031.35241.florian@openwrt.org> User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23118 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Sun, May 31, 2009 at 08:31:34PM +0200, Florian Fainelli wrote: > This patch makes the ethernet driver compile again > after commit 908a7a1. netif_rx_schedule became > napi_schedule and __netif_rx_complete became > __napi_rx_complete. > > Signed-off-by: Florian Fainelli Folded into the "MIPS: BCM63XX: Add integrated ethernet mac support." patch. You should eventually run this patch by the network maintainers. It's a driver patch so I won't merge it upstream unless it's been acked by one of the network guys. Thanks, Ralf From f.fainelli@gmail.com Mon Jun 1 16:02:49 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 01 Jun 2009 16:02:55 +0100 (BST) Received: from mail-ew0-f219.google.com ([209.85.219.219]:58711 "EHLO mail-ew0-f219.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20025397AbZFAPCt (ORCPT ); Mon, 1 Jun 2009 16:02:49 +0100 Received: by ewy19 with SMTP id 19so8166561ewy.0 for ; Mon, 01 Jun 2009 08:02:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:sender:from:to:subject:date :user-agent:cc:references:in-reply-to:mime-version:content-type :content-transfer-encoding:message-id; bh=YhoxV5rbhpKfcn6DLieHyRTtod6Tj2j3dNAo79LQ+NM=; b=U5BggflPSHXrJ1g5+41GNBqARNadRTMpqSQmSfAM3jn0pqv1SKg4e2XukFbIhYA5f+ 15gP3Nk3xpHTWiPM1NzCH5FG+n5dDP/BdytIicRwIRVQDu7FGMWK/id3wNOPSahnAsv8 UUl6mQ3JYMcTlgGjLrwuX33jtSJjbdI1wx0ic= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:from:to:subject:date:user-agent:cc:references:in-reply-to :mime-version:content-type:content-transfer-encoding:message-id; b=hAAwYk5M7buJKEcble3UH2Q2RN2m1ssspO+7fLqp2H9eP1sRCpi3bZGXgkYJdhrkNe isUr8qvlFQL6xBbgZRRqT3Frkj9FfbE7iZ1xRfu1giNYN6kTOt6nyu8bFRMAoxWoF2uy 009dhI18iFIe+xYkOmSzXQAKI4ibcMqWKjK4A= Received: by 10.210.80.17 with SMTP id d17mr6498475ebb.27.1243868563256; Mon, 01 Jun 2009 08:02:43 -0700 (PDT) Received: from florian.lab.openpattern.org (lab.openpattern.org [82.240.16.241]) by mx.google.com with ESMTPS id 28sm398157eyg.14.2009.06.01.08.02.42 (version=TLSv1/SSLv3 cipher=RC4-MD5); Mon, 01 Jun 2009 08:02:42 -0700 (PDT) From: Florian Fainelli To: Ralf Baechle Subject: Re: [PATCH 10/10] bcm63xx: compile fixes for bcm63xx_enet.c Date: Mon, 1 Jun 2009 17:02:38 +0200 User-Agent: KMail/1.9.9 Cc: linux-mips@linux-mips.org, Maxime Bizon References: <200905312031.35241.florian@openwrt.org> <20090601145552.GI6604@linux-mips.org> In-Reply-To: <20090601145552.GI6604@linux-mips.org> MIME-Version: 1.0 Content-Type: multipart/signed; boundary="nextPart7950347.cy3bj5dT6T"; protocol="application/pgp-signature"; micalg=pgp-sha1 Content-Transfer-Encoding: 7bit Message-Id: <200906011702.40561.florian@openwrt.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23119 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips --nextPart7950347.cy3bj5dT6T Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Content-Disposition: inline Le Monday 01 June 2009 16:55:52 Ralf Baechle, vous avez =E9crit=A0: > On Sun, May 31, 2009 at 08:31:34PM +0200, Florian Fainelli wrote: > > This patch makes the ethernet driver compile again > > after commit 908a7a1. netif_rx_schedule became > > napi_schedule and __netif_rx_complete became > > __napi_rx_complete. > > > > Signed-off-by: Florian Fainelli > > Folded into the "MIPS: BCM63XX: Add integrated ethernet mac support." > patch. Thanks. > > You should eventually run this patch by the network maintainers. It's > a driver patch so I won't merge it upstream unless it's been acked by one > of the network guys. Actually Maxime already submitted those patches, without much answer from t= he=20 network guys so I guess they just skipped it. =2D-=20 Best regards, Florian Fainelli Email : florian@openwrt.org http://openwrt.org =2D------------------------------ --nextPart7950347.cy3bj5dT6T Content-Type: application/pgp-signature; name=signature.asc Content-Description: This is a digitally signed message part. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.9 (GNU/Linux) iEYEABECAAYFAkoj7Y4ACgkQlyvkmBGtjyZUoQCePsvQsSSEVHbgnlysyCRRz1wr JRkAnjYIDPy7lNraFl0SdjeiG6y04dKe =dAb+ -----END PGP SIGNATURE----- --nextPart7950347.cy3bj5dT6T-- From max@sakura.staff.proxad.net Mon Jun 1 18:08:26 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 01 Jun 2009 18:08:40 +0100 (WEST) Received: from sakura.staff.proxad.net ([213.228.1.107]:42534 "EHLO sakura.staff.proxad.net" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20025624AbZFARIY (ORCPT ); Mon, 1 Jun 2009 18:08:24 +0100 Received: by sakura.staff.proxad.net (Postfix, from userid 1000) id 66303112408D; Mon, 1 Jun 2009 19:08:15 +0200 (CEST) From: Maxime Bizon To: linux-mips@linux-mips.org, Ralf Baechle Cc: Florian Fainelli , Maxime Bizon Subject: [PATCH] bcm63xx: limit number of usb port to 1. Date: Mon, 1 Jun 2009 19:08:10 +0200 Message-Id: <1243876095-8987-5-git-send-email-mbizon@freebox.fr> X-Mailer: git-send-email 1.6.0.4 In-Reply-To: <1243876095-8987-1-git-send-email-mbizon@freebox.fr> References: <1243876095-8987-1-git-send-email-mbizon@freebox.fr> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23120 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mbizon@freebox.fr Precedence: bulk X-list: linux-mips This patch disables the use of more than one USB port. Hardware has two ports, but one may be shared with USB slave port. Until we have this information in the platform data, don't use the second port. Signed-off-by: Maxime Bizon --- drivers/usb/host/ohci-bcm63xx.c | 2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/drivers/usb/host/ohci-bcm63xx.c b/drivers/usb/host/ohci-bcm63xx.c index 08807d9..74f432f 100644 --- a/drivers/usb/host/ohci-bcm63xx.c +++ b/drivers/usb/host/ohci-bcm63xx.c @@ -20,6 +20,8 @@ static int __devinit ohci_bcm63xx_start(struct usb_hcd *hcd) struct ohci_hcd *ohci = hcd_to_ohci(hcd); int ret; + ohci->num_ports = 1; + ret = ohci_init(ohci); if (ret < 0) return ret; -- 1.6.0.4 From max@sakura.staff.proxad.net Mon Jun 1 18:09:00 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 01 Jun 2009 18:09:08 +0100 (WEST) Received: from sakura.staff.proxad.net ([213.228.1.107]:42528 "EHLO sakura.staff.proxad.net" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20025623AbZFARIY (ORCPT ); Mon, 1 Jun 2009 18:08:24 +0100 Received: by sakura.staff.proxad.net (Postfix, from userid 1000) id 42DFE112408B; Mon, 1 Jun 2009 19:08:15 +0200 (CEST) From: Maxime Bizon To: linux-mips@linux-mips.org, Ralf Baechle Cc: Florian Fainelli , Maxime Bizon Subject: [PATCH] bcm63xx: use napi_complete instead of __napi_complete Date: Mon, 1 Jun 2009 19:08:08 +0200 Message-Id: <1243876095-8987-3-git-send-email-mbizon@freebox.fr> X-Mailer: git-send-email 1.6.0.4 In-Reply-To: <1243876095-8987-1-git-send-email-mbizon@freebox.fr> References: <1243876095-8987-1-git-send-email-mbizon@freebox.fr> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23121 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mbizon@freebox.fr Precedence: bulk X-list: linux-mips We're not disabling IRQ, so we must call the irq safe flavour of napi_complete. Signed-off-by: Maxime Bizon --- drivers/net/bcm63xx_enet.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/drivers/net/bcm63xx_enet.c b/drivers/net/bcm63xx_enet.c index a91f909..20e08ef 100644 --- a/drivers/net/bcm63xx_enet.c +++ b/drivers/net/bcm63xx_enet.c @@ -450,7 +450,7 @@ static int bcm_enet_poll(struct napi_struct *napi, int budget) /* no more packet in rx/tx queue, remove device from poll * queue */ - __napi_complete(napi); + napi_complete(napi); /* restore rx/tx interrupt */ enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK, -- 1.6.0.4 From max@sakura.staff.proxad.net Mon Jun 1 18:09:27 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 01 Jun 2009 18:09:34 +0100 (WEST) Received: from sakura.staff.proxad.net ([213.228.1.107]:42544 "EHLO sakura.staff.proxad.net" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20025622AbZFARIa (ORCPT ); Mon, 1 Jun 2009 18:08:30 +0100 Received: by sakura.staff.proxad.net (Postfix, from userid 1000) id 6AE2F112408E; Mon, 1 Jun 2009 19:08:15 +0200 (CEST) From: Maxime Bizon To: linux-mips@linux-mips.org, Ralf Baechle Cc: Florian Fainelli , Maxime Bizon Subject: [PATCH] bcm63xx: use platform_get_irq in ohci-bcm63xx.c Date: Mon, 1 Jun 2009 19:08:11 +0200 Message-Id: <1243876095-8987-6-git-send-email-mbizon@freebox.fr> X-Mailer: git-send-email 1.6.0.4 In-Reply-To: <1243876095-8987-1-git-send-email-mbizon@freebox.fr> References: <1243876095-8987-1-git-send-email-mbizon@freebox.fr> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23122 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mbizon@freebox.fr Precedence: bulk X-list: linux-mips As requested by USB maintainer, use platform_get_irq instead of platform_get_resource. Signed-off-by: Maxime Bizon --- drivers/usb/host/ohci-bcm63xx.c | 10 +++++----- 1 files changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/usb/host/ohci-bcm63xx.c b/drivers/usb/host/ohci-bcm63xx.c index 74f432f..f0e4639 100644 --- a/drivers/usb/host/ohci-bcm63xx.c +++ b/drivers/usb/host/ohci-bcm63xx.c @@ -58,15 +58,15 @@ static const struct hc_driver ohci_bcm63xx_hc_driver = { static int __devinit ohci_hcd_bcm63xx_drv_probe(struct platform_device *pdev) { - struct resource *res_mem, *res_irq; + struct resource *res_mem; struct usb_hcd *hcd; struct ohci_hcd *ohci; u32 reg; - int ret; + int ret, irq; res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); - res_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); - if (!res_mem || !res_irq) + irq = platform_get_irq(pdev, 0); + if (!res_mem || irq < 0) return -ENODEV; if (BCMCPU_IS_6348()) { @@ -114,7 +114,7 @@ static int __devinit ohci_hcd_bcm63xx_drv_probe(struct platform_device *pdev) OHCI_QUIRK_FRAME_NO; ohci_hcd_init(ohci); - ret = usb_add_hcd(hcd, res_irq->start, IRQF_DISABLED); + ret = usb_add_hcd(hcd, irq, IRQF_DISABLED); if (ret) goto out2; -- 1.6.0.4 From max@sakura.staff.proxad.net Mon Jun 1 18:09:52 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 01 Jun 2009 18:10:01 +0100 (WEST) Received: from sakura.staff.proxad.net ([213.228.1.107]:42550 "EHLO sakura.staff.proxad.net" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20025632AbZFARIc (ORCPT ); Mon, 1 Jun 2009 18:08:32 +0100 Received: by sakura.staff.proxad.net (Postfix, from userid 1000) id 76D6D1124091; Mon, 1 Jun 2009 19:08:15 +0200 (CEST) From: Maxime Bizon To: linux-mips@linux-mips.org, Ralf Baechle Cc: Florian Fainelli , Maxime Bizon Subject: [PATCH] bcm63xx: don't set bus type in ohci-bcm63xx.c Date: Mon, 1 Jun 2009 19:08:12 +0200 Message-Id: <1243876095-8987-7-git-send-email-mbizon@freebox.fr> X-Mailer: git-send-email 1.6.0.4 In-Reply-To: <1243876095-8987-1-git-send-email-mbizon@freebox.fr> References: <1243876095-8987-1-git-send-email-mbizon@freebox.fr> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23123 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mbizon@freebox.fr Precedence: bulk X-list: linux-mips The platform code already sets the bus type, so don't do it. Signed-off-by: Maxime Bizon --- drivers/usb/host/ohci-bcm63xx.c | 1 - 1 files changed, 0 insertions(+), 1 deletions(-) diff --git a/drivers/usb/host/ohci-bcm63xx.c b/drivers/usb/host/ohci-bcm63xx.c index f0e4639..d48c8ac 100644 --- a/drivers/usb/host/ohci-bcm63xx.c +++ b/drivers/usb/host/ohci-bcm63xx.c @@ -154,7 +154,6 @@ static struct platform_driver ohci_hcd_bcm63xx_driver = { .driver = { .name = "bcm63xx_ohci", .owner = THIS_MODULE, - .bus = &platform_bus_type }, }; -- 1.6.0.4 From max@sakura.staff.proxad.net Mon Jun 1 18:10:19 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 01 Jun 2009 18:10:26 +0100 (WEST) Received: from sakura.staff.proxad.net ([213.228.1.107]:42551 "EHLO sakura.staff.proxad.net" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20025630AbZFARIc (ORCPT ); Mon, 1 Jun 2009 18:08:32 +0100 Received: by sakura.staff.proxad.net (Postfix, from userid 1000) id 79C0F1124092; Mon, 1 Jun 2009 19:08:15 +0200 (CEST) From: Maxime Bizon To: linux-mips@linux-mips.org, Ralf Baechle Cc: Florian Fainelli , Maxime Bizon Subject: [PATCH] bcm63xx: use platform_get_irq in ehci-bcm63xx.c Date: Mon, 1 Jun 2009 19:08:14 +0200 Message-Id: <1243876095-8987-9-git-send-email-mbizon@freebox.fr> X-Mailer: git-send-email 1.6.0.4 In-Reply-To: <1243876095-8987-1-git-send-email-mbizon@freebox.fr> References: <1243876095-8987-1-git-send-email-mbizon@freebox.fr> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23124 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mbizon@freebox.fr Precedence: bulk X-list: linux-mips As requested by USB maintainer, use platform_get_irq instead of platform_get_resource. Signed-off-by: Maxime Bizon --- drivers/usb/host/ehci-bcm63xx.c | 10 +++++----- 1 files changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/usb/host/ehci-bcm63xx.c b/drivers/usb/host/ehci-bcm63xx.c index 2fef571..0aba0f9 100644 --- a/drivers/usb/host/ehci-bcm63xx.c +++ b/drivers/usb/host/ehci-bcm63xx.c @@ -62,15 +62,15 @@ static const struct hc_driver ehci_bcm63xx_hc_driver = { static int __devinit ehci_hcd_bcm63xx_drv_probe(struct platform_device *pdev) { - struct resource *res_mem, *res_irq; + struct resource *res_mem; struct usb_hcd *hcd; struct ehci_hcd *ehci; u32 reg; - int ret; + int ret, irq; res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); - res_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); - if (!res_mem || !res_irq) + irq = platform_get_irq(pdev, 0);; + if (!res_mem || irq < 0) return -ENODEV; reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SWAP_REG); @@ -109,7 +109,7 @@ static int __devinit ehci_hcd_bcm63xx_drv_probe(struct platform_device *pdev) ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params); ehci->sbrn = 0x20; - ret = usb_add_hcd(hcd, res_irq->start, IRQF_DISABLED); + ret = usb_add_hcd(hcd, irq, IRQF_DISABLED); if (ret) goto out2; -- 1.6.0.4 From max@sakura.staff.proxad.net Mon Jun 1 18:10:44 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 01 Jun 2009 18:10:51 +0100 (WEST) Received: from sakura.staff.proxad.net ([213.228.1.107]:42552 "EHLO sakura.staff.proxad.net" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20025631AbZFARIc (ORCPT ); Mon, 1 Jun 2009 18:08:32 +0100 Received: by sakura.staff.proxad.net (Postfix, from userid 1000) id 7EA6D1124093; Mon, 1 Jun 2009 19:08:15 +0200 (CEST) From: Maxime Bizon To: linux-mips@linux-mips.org, Ralf Baechle Cc: Florian Fainelli , Maxime Bizon Subject: [PATCH] bcm63xx: don't set bus type in ehci-bcm63xx.c Date: Mon, 1 Jun 2009 19:08:15 +0200 Message-Id: <1243876095-8987-10-git-send-email-mbizon@freebox.fr> X-Mailer: git-send-email 1.6.0.4 In-Reply-To: <1243876095-8987-1-git-send-email-mbizon@freebox.fr> References: <1243876095-8987-1-git-send-email-mbizon@freebox.fr> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23125 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mbizon@freebox.fr Precedence: bulk X-list: linux-mips The platform code already sets the bus type, so don't do it. Signed-off-by: Maxime Bizon --- drivers/usb/host/ehci-bcm63xx.c | 1 - 1 files changed, 0 insertions(+), 1 deletions(-) diff --git a/drivers/usb/host/ehci-bcm63xx.c b/drivers/usb/host/ehci-bcm63xx.c index 0aba0f9..8a62c0a 100644 --- a/drivers/usb/host/ehci-bcm63xx.c +++ b/drivers/usb/host/ehci-bcm63xx.c @@ -145,7 +145,6 @@ static struct platform_driver ehci_hcd_bcm63xx_driver = { .driver = { .name = "bcm63xx_ehci", .owner = THIS_MODULE, - .bus = &platform_bus_type }, }; -- 1.6.0.4 From max@sakura.staff.proxad.net Mon Jun 1 18:11:08 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 01 Jun 2009 18:11:15 +0100 (WEST) Received: from sakura.staff.proxad.net ([213.228.1.107]:42543 "EHLO sakura.staff.proxad.net" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20025629AbZFARIa (ORCPT ); Mon, 1 Jun 2009 18:08:30 +0100 Received: by sakura.staff.proxad.net (Postfix, from userid 1000) id 70BE0112408F; Mon, 1 Jun 2009 19:08:15 +0200 (CEST) From: Maxime Bizon To: linux-mips@linux-mips.org, Ralf Baechle Cc: Florian Fainelli , Maxime Bizon Subject: [PATCH] bcm63xx: clarify meaning of the magical value in ohci-bcm63xx.c Date: Mon, 1 Jun 2009 19:08:13 +0200 Message-Id: <1243876095-8987-8-git-send-email-mbizon@freebox.fr> X-Mailer: git-send-email 1.6.0.4 In-Reply-To: <1243876095-8987-1-git-send-email-mbizon@freebox.fr> References: <1243876095-8987-1-git-send-email-mbizon@freebox.fr> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23126 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mbizon@freebox.fr Precedence: bulk X-list: linux-mips USB maintainer asked for clarification of the magic value used during USB init. Be clear about the source of it. Signed-off-by: Maxime Bizon --- drivers/usb/host/ohci-bcm63xx.c | 4 +++- 1 files changed, 3 insertions(+), 1 deletions(-) diff --git a/drivers/usb/host/ohci-bcm63xx.c b/drivers/usb/host/ohci-bcm63xx.c index d48c8ac..bd66d5a 100644 --- a/drivers/usb/host/ohci-bcm63xx.c +++ b/drivers/usb/host/ohci-bcm63xx.c @@ -85,7 +85,9 @@ static int __devinit ohci_hcd_bcm63xx_drv_probe(struct platform_device *pdev) reg &= ~USBH_PRIV_SWAP_OHCI_ENDN_MASK; reg |= USBH_PRIV_SWAP_OHCI_DATA_MASK; bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SWAP_REG); - /* don't ask... */ + /* the magic value comes for the original vendor BSP + * and is needed for USB to work. Datasheet does not + * help, so the magic value is used as-is. */ bcm_rset_writel(RSET_USBH_PRIV, 0x1c0020, USBH_PRIV_TEST_REG); } else return 0; -- 1.6.0.4 From max@sakura.staff.proxad.net Mon Jun 1 18:11:32 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 01 Jun 2009 18:11:40 +0100 (WEST) Received: from sakura.staff.proxad.net ([213.228.1.107]:42523 "EHLO sakura.staff.proxad.net" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20025625AbZFARIY (ORCPT ); Mon, 1 Jun 2009 18:08:24 +0100 Received: by sakura.staff.proxad.net (Postfix, from userid 1000) id 2A769112408A; Mon, 1 Jun 2009 19:08:15 +0200 (CEST) From: Maxime Bizon To: linux-mips@linux-mips.org, Ralf Baechle Cc: Florian Fainelli Subject: More updates to bcm63xx support. Date: Mon, 1 Jun 2009 19:08:06 +0200 Message-Id: <1243876095-8987-1-git-send-email-mbizon@freebox.fr> X-Mailer: git-send-email 1.6.0.4 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23127 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mbizon@freebox.fr Precedence: bulk X-list: linux-mips Hi Ralf, The following patch series (on top of Florian's latest post) are mostly trivial fixes & cleanup requested by subsystem maintainers. Patch 2 and 4 are actual bugfixes. Florian has some more patches to send to you, I will wait for them to be folded in the bcm63xx tree and then repost the whole serie. I only got feedback from USB maintainer, and addressed most of them. Davem has accidentally dropped the patch from its patchwork, so I think just resubmitting will do. Nothing from serial & pcmcia. The ethernet PHY support patch should be dropped, the only feature we get is IRQ support which after field testing seems to be buggy. Maybe later. Is it ok for you if I ask for the patches to go through your tree once they get acked ? Thanks ! From max@sakura.staff.proxad.net Mon Jun 1 18:11:57 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 01 Jun 2009 18:12:05 +0100 (WEST) Received: from sakura.staff.proxad.net ([213.228.1.107]:42530 "EHLO sakura.staff.proxad.net" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20025628AbZFARIY (ORCPT ); Mon, 1 Jun 2009 18:08:24 +0100 Received: by sakura.staff.proxad.net (Postfix, from userid 1000) id 538BD112408C; Mon, 1 Jun 2009 19:08:15 +0200 (CEST) From: Maxime Bizon To: linux-mips@linux-mips.org, Ralf Baechle Cc: Florian Fainelli , Maxime Bizon Subject: [PATCH] bcm63xx: convert bcm63xx_enet to netdev ops. Date: Mon, 1 Jun 2009 19:08:09 +0200 Message-Id: <1243876095-8987-4-git-send-email-mbizon@freebox.fr> X-Mailer: git-send-email 1.6.0.4 In-Reply-To: <1243876095-8987-1-git-send-email-mbizon@freebox.fr> References: <1243876095-8987-1-git-send-email-mbizon@freebox.fr> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23128 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mbizon@freebox.fr Precedence: bulk X-list: linux-mips This patch makes bcm63xx_enet driver use netdevice ops. Signed-off-by: Maxime Bizon --- drivers/net/bcm63xx_enet.c | 24 ++++++++++++++---------- 1 files changed, 14 insertions(+), 10 deletions(-) diff --git a/drivers/net/bcm63xx_enet.c b/drivers/net/bcm63xx_enet.c index 20e08ef..36324b3 100644 --- a/drivers/net/bcm63xx_enet.c +++ b/drivers/net/bcm63xx_enet.c @@ -1551,6 +1551,19 @@ static void bcm_enet_hw_preinit(struct bcm_enet_priv *priv) enet_writel(priv, val, ENET_MIBCTL_REG); } +static const struct net_device_ops bcm_enet_ops = { + .ndo_open = bcm_enet_open, + .ndo_stop = bcm_enet_stop, + .ndo_start_xmit = bcm_enet_start_xmit, + .ndo_get_stats = bcm_enet_get_stats, + .ndo_set_mac_address = bcm_enet_set_mac_address, + .ndo_set_multicast_list = bcm_enet_set_multicast_list, + .ndo_do_ioctl = bcm_enet_ioctl, +#ifdef CONFIG_NET_POLL_CONTROLLER + .ndo_poll_controller = bcm_enet_netpoll, +#endif +}; + /* * allocate netdevice, request register memory and register device. */ @@ -1716,17 +1729,8 @@ static int __devinit bcm_enet_probe(struct platform_device *pdev) enet_writel(priv, 0, ENET_MIB_REG(i)); /* register netdevice */ - dev->open = bcm_enet_open; - dev->stop = bcm_enet_stop; - dev->hard_start_xmit = bcm_enet_start_xmit; - dev->get_stats = bcm_enet_get_stats; - dev->set_mac_address = bcm_enet_set_mac_address; - dev->set_multicast_list = bcm_enet_set_multicast_list; + dev->netdev_ops = &bcm_enet_ops; netif_napi_add(dev, &priv->napi, bcm_enet_poll, 16); - dev->do_ioctl = bcm_enet_ioctl; -#ifdef CONFIG_NET_POLL_CONTROLLER - dev->poll_controller = bcm_enet_netpoll; -#endif SET_ETHTOOL_OPS(dev, &bcm_enet_ethtool_ops); -- 1.6.0.4 From max@sakura.staff.proxad.net Mon Jun 1 18:12:22 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 01 Jun 2009 18:12:29 +0100 (WEST) Received: from sakura.staff.proxad.net ([213.228.1.107]:42524 "EHLO sakura.staff.proxad.net" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20025627AbZFARIY (ORCPT ); Mon, 1 Jun 2009 18:08:24 +0100 Received: by sakura.staff.proxad.net (Postfix, from userid 1000) id 2C9B0112406C; Mon, 1 Jun 2009 19:08:15 +0200 (CEST) From: Maxime Bizon To: linux-mips@linux-mips.org, Ralf Baechle Cc: Florian Fainelli , Maxime Bizon Subject: [PATCH] bcm63xx: remove duplicate init fields. Date: Mon, 1 Jun 2009 19:08:07 +0200 Message-Id: <1243876095-8987-2-git-send-email-mbizon@freebox.fr> X-Mailer: git-send-email 1.6.0.4 In-Reply-To: <1243876095-8987-1-git-send-email-mbizon@freebox.fr> References: <1243876095-8987-1-git-send-email-mbizon@freebox.fr> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23129 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mbizon@freebox.fr Precedence: bulk X-list: linux-mips This patch removes duplicate init fields in resource. Signed-off-by: Maxime Bizon --- arch/mips/bcm63xx/dev-enet.c | 2 -- 1 files changed, 0 insertions(+), 2 deletions(-) diff --git a/arch/mips/bcm63xx/dev-enet.c b/arch/mips/bcm63xx/dev-enet.c index 51c2e5a..188fa66 100644 --- a/arch/mips/bcm63xx/dev-enet.c +++ b/arch/mips/bcm63xx/dev-enet.c @@ -42,12 +42,10 @@ static struct resource enet0_res[] = { }, { .start = -1, /* filled at runtime */ - .start = IRQ_ENET0_RXDMA, .flags = IORESOURCE_IRQ, }, { .start = -1, /* filled at runtime */ - .start = IRQ_ENET0_TXDMA, .flags = IORESOURCE_IRQ, }, }; -- 1.6.0.4 From max@sakura.staff.proxad.net Mon Jun 1 18:22:04 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 01 Jun 2009 18:22:12 +0100 (WEST) Received: from sakura.staff.proxad.net ([213.228.1.107]:35395 "EHLO sakura.staff.proxad.net" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20025668AbZFARWD (ORCPT ); Mon, 1 Jun 2009 18:22:03 +0100 Received: by sakura.staff.proxad.net (Postfix, from userid 1000) id 6FEDC112408D; Mon, 1 Jun 2009 19:21:58 +0200 (CEST) From: Maxime Bizon To: linux-mips@linux-mips.org, Ralf Baechle Cc: Florian Fainelli , Maxime Bizon Subject: [PATCH 04/10] bcm63xx: limit number of usb port to 1. Date: Mon, 1 Jun 2009 19:21:52 +0200 Message-Id: <1243876918-9905-5-git-send-email-mbizon@freebox.fr> X-Mailer: git-send-email 1.6.0.4 In-Reply-To: <1243876918-9905-1-git-send-email-mbizon@freebox.fr> References: <1243876918-9905-1-git-send-email-mbizon@freebox.fr> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23130 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mbizon@freebox.fr Precedence: bulk X-list: linux-mips This patch disables the use of more than one USB port. Hardware has two ports, but one may be shared with USB slave port. Until we have this information in the platform data, don't use the second port. Signed-off-by: Maxime Bizon --- drivers/usb/host/ohci-bcm63xx.c | 2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/drivers/usb/host/ohci-bcm63xx.c b/drivers/usb/host/ohci-bcm63xx.c index 08807d9..74f432f 100644 --- a/drivers/usb/host/ohci-bcm63xx.c +++ b/drivers/usb/host/ohci-bcm63xx.c @@ -20,6 +20,8 @@ static int __devinit ohci_bcm63xx_start(struct usb_hcd *hcd) struct ohci_hcd *ohci = hcd_to_ohci(hcd); int ret; + ohci->num_ports = 1; + ret = ohci_init(ohci); if (ret < 0) return ret; -- 1.6.0.4 From max@sakura.staff.proxad.net Mon Jun 1 18:22:29 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 01 Jun 2009 18:22:37 +0100 (WEST) Received: from sakura.staff.proxad.net ([213.228.1.107]:35392 "EHLO sakura.staff.proxad.net" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20025662AbZFARWD (ORCPT ); Mon, 1 Jun 2009 18:22:03 +0100 Received: by sakura.staff.proxad.net (Postfix, from userid 1000) id 6CCA5112408B; Mon, 1 Jun 2009 19:21:58 +0200 (CEST) From: Maxime Bizon To: linux-mips@linux-mips.org, Ralf Baechle Cc: Florian Fainelli , Maxime Bizon Subject: [PATCH 03/10] bcm63xx: convert bcm63xx_enet to netdev ops. Date: Mon, 1 Jun 2009 19:21:51 +0200 Message-Id: <1243876918-9905-4-git-send-email-mbizon@freebox.fr> X-Mailer: git-send-email 1.6.0.4 In-Reply-To: <1243876918-9905-1-git-send-email-mbizon@freebox.fr> References: <1243876918-9905-1-git-send-email-mbizon@freebox.fr> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23131 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mbizon@freebox.fr Precedence: bulk X-list: linux-mips This patch makes bcm63xx_enet driver use netdevice ops. Signed-off-by: Maxime Bizon --- drivers/net/bcm63xx_enet.c | 24 ++++++++++++++---------- 1 files changed, 14 insertions(+), 10 deletions(-) diff --git a/drivers/net/bcm63xx_enet.c b/drivers/net/bcm63xx_enet.c index 20e08ef..36324b3 100644 --- a/drivers/net/bcm63xx_enet.c +++ b/drivers/net/bcm63xx_enet.c @@ -1551,6 +1551,19 @@ static void bcm_enet_hw_preinit(struct bcm_enet_priv *priv) enet_writel(priv, val, ENET_MIBCTL_REG); } +static const struct net_device_ops bcm_enet_ops = { + .ndo_open = bcm_enet_open, + .ndo_stop = bcm_enet_stop, + .ndo_start_xmit = bcm_enet_start_xmit, + .ndo_get_stats = bcm_enet_get_stats, + .ndo_set_mac_address = bcm_enet_set_mac_address, + .ndo_set_multicast_list = bcm_enet_set_multicast_list, + .ndo_do_ioctl = bcm_enet_ioctl, +#ifdef CONFIG_NET_POLL_CONTROLLER + .ndo_poll_controller = bcm_enet_netpoll, +#endif +}; + /* * allocate netdevice, request register memory and register device. */ @@ -1716,17 +1729,8 @@ static int __devinit bcm_enet_probe(struct platform_device *pdev) enet_writel(priv, 0, ENET_MIB_REG(i)); /* register netdevice */ - dev->open = bcm_enet_open; - dev->stop = bcm_enet_stop; - dev->hard_start_xmit = bcm_enet_start_xmit; - dev->get_stats = bcm_enet_get_stats; - dev->set_mac_address = bcm_enet_set_mac_address; - dev->set_multicast_list = bcm_enet_set_multicast_list; + dev->netdev_ops = &bcm_enet_ops; netif_napi_add(dev, &priv->napi, bcm_enet_poll, 16); - dev->do_ioctl = bcm_enet_ioctl; -#ifdef CONFIG_NET_POLL_CONTROLLER - dev->poll_controller = bcm_enet_netpoll; -#endif SET_ETHTOOL_OPS(dev, &bcm_enet_ethtool_ops); -- 1.6.0.4 From max@sakura.staff.proxad.net Mon Jun 1 18:22:55 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 01 Jun 2009 18:23:04 +0100 (WEST) Received: from sakura.staff.proxad.net ([213.228.1.107]:35385 "EHLO sakura.staff.proxad.net" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20025664AbZFARWD (ORCPT ); Mon, 1 Jun 2009 18:22:03 +0100 Received: by sakura.staff.proxad.net (Postfix, from userid 1000) id 644E1112406C; Mon, 1 Jun 2009 19:21:58 +0200 (CEST) From: Maxime Bizon To: linux-mips@linux-mips.org, Ralf Baechle Cc: Florian Fainelli , Maxime Bizon Subject: [PATCH 01/10] bcm63xx: remove duplicate init fields. Date: Mon, 1 Jun 2009 19:21:49 +0200 Message-Id: <1243876918-9905-2-git-send-email-mbizon@freebox.fr> X-Mailer: git-send-email 1.6.0.4 In-Reply-To: <1243876918-9905-1-git-send-email-mbizon@freebox.fr> References: <1243876918-9905-1-git-send-email-mbizon@freebox.fr> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23132 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mbizon@freebox.fr Precedence: bulk X-list: linux-mips This patch removes duplicate init fields in resource. Signed-off-by: Maxime Bizon --- arch/mips/bcm63xx/dev-enet.c | 2 -- 1 files changed, 0 insertions(+), 2 deletions(-) diff --git a/arch/mips/bcm63xx/dev-enet.c b/arch/mips/bcm63xx/dev-enet.c index 51c2e5a..188fa66 100644 --- a/arch/mips/bcm63xx/dev-enet.c +++ b/arch/mips/bcm63xx/dev-enet.c @@ -42,12 +42,10 @@ static struct resource enet0_res[] = { }, { .start = -1, /* filled at runtime */ - .start = IRQ_ENET0_RXDMA, .flags = IORESOURCE_IRQ, }, { .start = -1, /* filled at runtime */ - .start = IRQ_ENET0_TXDMA, .flags = IORESOURCE_IRQ, }, }; -- 1.6.0.4 From max@sakura.staff.proxad.net Mon Jun 1 18:23:21 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 01 Jun 2009 18:23:28 +0100 (WEST) Received: from sakura.staff.proxad.net ([213.228.1.107]:35389 "EHLO sakura.staff.proxad.net" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20025660AbZFARWD (ORCPT ); Mon, 1 Jun 2009 18:22:03 +0100 Received: by sakura.staff.proxad.net (Postfix, from userid 1000) id 690A5112408C; Mon, 1 Jun 2009 19:21:58 +0200 (CEST) From: Maxime Bizon To: linux-mips@linux-mips.org, Ralf Baechle Cc: Florian Fainelli , Maxime Bizon Subject: [PATCH 02/10] bcm63xx: use napi_complete instead of __napi_complete Date: Mon, 1 Jun 2009 19:21:50 +0200 Message-Id: <1243876918-9905-3-git-send-email-mbizon@freebox.fr> X-Mailer: git-send-email 1.6.0.4 In-Reply-To: <1243876918-9905-1-git-send-email-mbizon@freebox.fr> References: <1243876918-9905-1-git-send-email-mbizon@freebox.fr> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23133 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mbizon@freebox.fr Precedence: bulk X-list: linux-mips We're not disabling IRQ, so we must call the irq safe flavour of napi_complete. Signed-off-by: Maxime Bizon --- drivers/net/bcm63xx_enet.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/drivers/net/bcm63xx_enet.c b/drivers/net/bcm63xx_enet.c index a91f909..20e08ef 100644 --- a/drivers/net/bcm63xx_enet.c +++ b/drivers/net/bcm63xx_enet.c @@ -450,7 +450,7 @@ static int bcm_enet_poll(struct napi_struct *napi, int budget) /* no more packet in rx/tx queue, remove device from poll * queue */ - __napi_complete(napi); + napi_complete(napi); /* restore rx/tx interrupt */ enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK, -- 1.6.0.4 From max@sakura.staff.proxad.net Mon Jun 1 18:23:45 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 01 Jun 2009 18:23:53 +0100 (WEST) Received: from sakura.staff.proxad.net ([213.228.1.107]:35386 "EHLO sakura.staff.proxad.net" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20025666AbZFARWD (ORCPT ); Mon, 1 Jun 2009 18:22:03 +0100 Received: by sakura.staff.proxad.net (Postfix, from userid 1000) id 61094112408A; Mon, 1 Jun 2009 19:21:58 +0200 (CEST) From: Maxime Bizon To: linux-mips@linux-mips.org, Ralf Baechle Cc: Florian Fainelli Subject: More updates to bcm63xx support (resend) Date: Mon, 1 Jun 2009 19:21:48 +0200 Message-Id: <1243876918-9905-1-git-send-email-mbizon@freebox.fr> X-Mailer: git-send-email 1.6.0.4 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23134 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mbizon@freebox.fr Precedence: bulk X-list: linux-mips [Resend, I forgot to generate an actual patch series and missed one patch doing so, sorry for the noise] Hi Ralf, The following patch series (on top of Florian's latest post) are mostly trivial fixes & cleanup requested by subsystem maintainers. Patch 2 and 4 are actual bugfixes. Florian has some more patches to send to you, I will wait for them to be folded in the bcm63xx tree and then repost the whole serie. I only got feedback from USB maintainer, and addressed most of them. Davem has accidentally dropped the patch from its patchwork, so I think just resubmitting will do. Nothing from serial & pcmcia. The ethernet PHY support patch should be dropped, the only feature we get is IRQ support which after field testing seems to be buggy. Maybe later. Is it ok for you if I ask for the patches to go through your tree once they get acked ? Thanks ! From max@sakura.staff.proxad.net Mon Jun 1 18:24:10 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 01 Jun 2009 18:24:18 +0100 (WEST) Received: from sakura.staff.proxad.net ([213.228.1.107]:35412 "EHLO sakura.staff.proxad.net" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20025670AbZFARWJ (ORCPT ); Mon, 1 Jun 2009 18:22:09 +0100 Received: by sakura.staff.proxad.net (Postfix, from userid 1000) id 82DA1112408E; Mon, 1 Jun 2009 19:21:58 +0200 (CEST) From: Maxime Bizon To: linux-mips@linux-mips.org, Ralf Baechle Cc: Florian Fainelli , Maxime Bizon Subject: [PATCH 07/10] bcm63xx: clarify meaning of the magical value in ohci-bcm63xx.c Date: Mon, 1 Jun 2009 19:21:55 +0200 Message-Id: <1243876918-9905-8-git-send-email-mbizon@freebox.fr> X-Mailer: git-send-email 1.6.0.4 In-Reply-To: <1243876918-9905-1-git-send-email-mbizon@freebox.fr> References: <1243876918-9905-1-git-send-email-mbizon@freebox.fr> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23135 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mbizon@freebox.fr Precedence: bulk X-list: linux-mips USB maintainer asked for clarification of the magic value used during USB init. Be clear about the source of it. Signed-off-by: Maxime Bizon --- drivers/usb/host/ohci-bcm63xx.c | 4 +++- 1 files changed, 3 insertions(+), 1 deletions(-) diff --git a/drivers/usb/host/ohci-bcm63xx.c b/drivers/usb/host/ohci-bcm63xx.c index d48c8ac..bd66d5a 100644 --- a/drivers/usb/host/ohci-bcm63xx.c +++ b/drivers/usb/host/ohci-bcm63xx.c @@ -85,7 +85,9 @@ static int __devinit ohci_hcd_bcm63xx_drv_probe(struct platform_device *pdev) reg &= ~USBH_PRIV_SWAP_OHCI_ENDN_MASK; reg |= USBH_PRIV_SWAP_OHCI_DATA_MASK; bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SWAP_REG); - /* don't ask... */ + /* the magic value comes for the original vendor BSP + * and is needed for USB to work. Datasheet does not + * help, so the magic value is used as-is. */ bcm_rset_writel(RSET_USBH_PRIV, 0x1c0020, USBH_PRIV_TEST_REG); } else return 0; -- 1.6.0.4 From max@sakura.staff.proxad.net Mon Jun 1 18:24:35 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 01 Jun 2009 18:24:43 +0100 (WEST) Received: from sakura.staff.proxad.net ([213.228.1.107]:35409 "EHLO sakura.staff.proxad.net" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20025672AbZFARWJ (ORCPT ); Mon, 1 Jun 2009 18:22:09 +0100 Received: by sakura.staff.proxad.net (Postfix, from userid 1000) id 8123C1124090; Mon, 1 Jun 2009 19:21:58 +0200 (CEST) From: Maxime Bizon To: linux-mips@linux-mips.org, Ralf Baechle Cc: Florian Fainelli , Maxime Bizon Subject: [PATCH 06/10] bcm63xx: don't set bus type in ohci-bcm63xx.c Date: Mon, 1 Jun 2009 19:21:54 +0200 Message-Id: <1243876918-9905-7-git-send-email-mbizon@freebox.fr> X-Mailer: git-send-email 1.6.0.4 In-Reply-To: <1243876918-9905-1-git-send-email-mbizon@freebox.fr> References: <1243876918-9905-1-git-send-email-mbizon@freebox.fr> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23136 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mbizon@freebox.fr Precedence: bulk X-list: linux-mips The platform code already sets the bus type, so don't do it. Signed-off-by: Maxime Bizon --- drivers/usb/host/ohci-bcm63xx.c | 1 - 1 files changed, 0 insertions(+), 1 deletions(-) diff --git a/drivers/usb/host/ohci-bcm63xx.c b/drivers/usb/host/ohci-bcm63xx.c index f0e4639..d48c8ac 100644 --- a/drivers/usb/host/ohci-bcm63xx.c +++ b/drivers/usb/host/ohci-bcm63xx.c @@ -154,7 +154,6 @@ static struct platform_driver ohci_hcd_bcm63xx_driver = { .driver = { .name = "bcm63xx_ohci", .owner = THIS_MODULE, - .bus = &platform_bus_type }, }; -- 1.6.0.4 From max@sakura.staff.proxad.net Mon Jun 1 18:25:00 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 01 Jun 2009 18:25:07 +0100 (WEST) Received: from sakura.staff.proxad.net ([213.228.1.107]:35411 "EHLO sakura.staff.proxad.net" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20025675AbZFARWJ (ORCPT ); Mon, 1 Jun 2009 18:22:09 +0100 Received: by sakura.staff.proxad.net (Postfix, from userid 1000) id 874981124091; Mon, 1 Jun 2009 19:21:58 +0200 (CEST) From: Maxime Bizon To: linux-mips@linux-mips.org, Ralf Baechle Cc: Florian Fainelli , Maxime Bizon Subject: [PATCH 08/10] bcm63xx: use platform_get_irq in ehci-bcm63xx.c Date: Mon, 1 Jun 2009 19:21:56 +0200 Message-Id: <1243876918-9905-9-git-send-email-mbizon@freebox.fr> X-Mailer: git-send-email 1.6.0.4 In-Reply-To: <1243876918-9905-1-git-send-email-mbizon@freebox.fr> References: <1243876918-9905-1-git-send-email-mbizon@freebox.fr> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23137 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mbizon@freebox.fr Precedence: bulk X-list: linux-mips As requested by USB maintainer, use platform_get_irq instead of platform_get_resource. Signed-off-by: Maxime Bizon --- drivers/usb/host/ehci-bcm63xx.c | 10 +++++----- 1 files changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/usb/host/ehci-bcm63xx.c b/drivers/usb/host/ehci-bcm63xx.c index 2fef571..0aba0f9 100644 --- a/drivers/usb/host/ehci-bcm63xx.c +++ b/drivers/usb/host/ehci-bcm63xx.c @@ -62,15 +62,15 @@ static const struct hc_driver ehci_bcm63xx_hc_driver = { static int __devinit ehci_hcd_bcm63xx_drv_probe(struct platform_device *pdev) { - struct resource *res_mem, *res_irq; + struct resource *res_mem; struct usb_hcd *hcd; struct ehci_hcd *ehci; u32 reg; - int ret; + int ret, irq; res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); - res_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); - if (!res_mem || !res_irq) + irq = platform_get_irq(pdev, 0);; + if (!res_mem || irq < 0) return -ENODEV; reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SWAP_REG); @@ -109,7 +109,7 @@ static int __devinit ehci_hcd_bcm63xx_drv_probe(struct platform_device *pdev) ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params); ehci->sbrn = 0x20; - ret = usb_add_hcd(hcd, res_irq->start, IRQF_DISABLED); + ret = usb_add_hcd(hcd, irq, IRQF_DISABLED); if (ret) goto out2; -- 1.6.0.4 From max@sakura.staff.proxad.net Mon Jun 1 18:25:25 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 01 Jun 2009 18:25:32 +0100 (WEST) Received: from sakura.staff.proxad.net ([213.228.1.107]:35413 "EHLO sakura.staff.proxad.net" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20025674AbZFARWJ (ORCPT ); Mon, 1 Jun 2009 18:22:09 +0100 Received: by sakura.staff.proxad.net (Postfix, from userid 1000) id 8D41C1124095; Mon, 1 Jun 2009 19:21:58 +0200 (CEST) From: Maxime Bizon To: linux-mips@linux-mips.org, Ralf Baechle Cc: Florian Fainelli , Maxime Bizon Subject: [PATCH 09/10] bcm63xx: don't set bus type in ehci-bcm63xx.c Date: Mon, 1 Jun 2009 19:21:57 +0200 Message-Id: <1243876918-9905-10-git-send-email-mbizon@freebox.fr> X-Mailer: git-send-email 1.6.0.4 In-Reply-To: <1243876918-9905-1-git-send-email-mbizon@freebox.fr> References: <1243876918-9905-1-git-send-email-mbizon@freebox.fr> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23138 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mbizon@freebox.fr Precedence: bulk X-list: linux-mips The platform code already sets the bus type, so don't do it. Signed-off-by: Maxime Bizon --- drivers/usb/host/ehci-bcm63xx.c | 1 - 1 files changed, 0 insertions(+), 1 deletions(-) diff --git a/drivers/usb/host/ehci-bcm63xx.c b/drivers/usb/host/ehci-bcm63xx.c index 0aba0f9..8a62c0a 100644 --- a/drivers/usb/host/ehci-bcm63xx.c +++ b/drivers/usb/host/ehci-bcm63xx.c @@ -145,7 +145,6 @@ static struct platform_driver ehci_hcd_bcm63xx_driver = { .driver = { .name = "bcm63xx_ehci", .owner = THIS_MODULE, - .bus = &platform_bus_type }, }; -- 1.6.0.4 From max@sakura.staff.proxad.net Mon Jun 1 18:25:49 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 01 Jun 2009 18:25:57 +0100 (WEST) Received: from sakura.staff.proxad.net ([213.228.1.107]:35414 "EHLO sakura.staff.proxad.net" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20025673AbZFARWJ (ORCPT ); Mon, 1 Jun 2009 18:22:09 +0100 Received: by sakura.staff.proxad.net (Postfix, from userid 1000) id 9023A1124092; Mon, 1 Jun 2009 19:21:58 +0200 (CEST) From: Maxime Bizon To: linux-mips@linux-mips.org, Ralf Baechle Cc: Florian Fainelli , Maxime Bizon Subject: [PATCH 10/10] bcm63xx: clarify meaning of the magical value in ehci-bcm63xx.c Date: Mon, 1 Jun 2009 19:21:58 +0200 Message-Id: <1243876918-9905-11-git-send-email-mbizon@freebox.fr> X-Mailer: git-send-email 1.6.0.4 In-Reply-To: <1243876918-9905-1-git-send-email-mbizon@freebox.fr> References: <1243876918-9905-1-git-send-email-mbizon@freebox.fr> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23139 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mbizon@freebox.fr Precedence: bulk X-list: linux-mips USB maintainer asked for clarification of the magic value used during USB init. Be clear about the source of it. Signed-off-by: Maxime Bizon --- drivers/usb/host/ehci-bcm63xx.c | 4 +++- 1 files changed, 3 insertions(+), 1 deletions(-) diff --git a/drivers/usb/host/ehci-bcm63xx.c b/drivers/usb/host/ehci-bcm63xx.c index 8a62c0a..5a03fdd 100644 --- a/drivers/usb/host/ehci-bcm63xx.c +++ b/drivers/usb/host/ehci-bcm63xx.c @@ -78,7 +78,9 @@ static int __devinit ehci_hcd_bcm63xx_drv_probe(struct platform_device *pdev) reg |= USBH_PRIV_SWAP_EHCI_ENDN_MASK; bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SWAP_REG); - /* don't ask... */ + /* the magic value comes for the original vendor BSP and is + * needed for USB to work. Datasheet does not help, so the + * magic value is used as-is. */ bcm_rset_writel(RSET_USBH_PRIV, 0x1c0020, USBH_PRIV_TEST_REG); hcd = usb_create_hcd(&ehci_bcm63xx_hc_driver, &pdev->dev, "bcm63xx"); -- 1.6.0.4 From max@sakura.staff.proxad.net Mon Jun 1 18:26:14 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 01 Jun 2009 18:26:21 +0100 (WEST) Received: from sakura.staff.proxad.net ([213.228.1.107]:35410 "EHLO sakura.staff.proxad.net" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20025671AbZFARWJ (ORCPT ); Mon, 1 Jun 2009 18:22:09 +0100 Received: by sakura.staff.proxad.net (Postfix, from userid 1000) id 77591112408F; Mon, 1 Jun 2009 19:21:58 +0200 (CEST) From: Maxime Bizon To: linux-mips@linux-mips.org, Ralf Baechle Cc: Florian Fainelli , Maxime Bizon Subject: [PATCH 05/10] bcm63xx: use platform_get_irq in ohci-bcm63xx.c Date: Mon, 1 Jun 2009 19:21:53 +0200 Message-Id: <1243876918-9905-6-git-send-email-mbizon@freebox.fr> X-Mailer: git-send-email 1.6.0.4 In-Reply-To: <1243876918-9905-1-git-send-email-mbizon@freebox.fr> References: <1243876918-9905-1-git-send-email-mbizon@freebox.fr> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23140 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mbizon@freebox.fr Precedence: bulk X-list: linux-mips As requested by USB maintainer, use platform_get_irq instead of platform_get_resource. Signed-off-by: Maxime Bizon --- drivers/usb/host/ohci-bcm63xx.c | 10 +++++----- 1 files changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/usb/host/ohci-bcm63xx.c b/drivers/usb/host/ohci-bcm63xx.c index 74f432f..f0e4639 100644 --- a/drivers/usb/host/ohci-bcm63xx.c +++ b/drivers/usb/host/ohci-bcm63xx.c @@ -58,15 +58,15 @@ static const struct hc_driver ohci_bcm63xx_hc_driver = { static int __devinit ohci_hcd_bcm63xx_drv_probe(struct platform_device *pdev) { - struct resource *res_mem, *res_irq; + struct resource *res_mem; struct usb_hcd *hcd; struct ohci_hcd *ohci; u32 reg; - int ret; + int ret, irq; res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); - res_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); - if (!res_mem || !res_irq) + irq = platform_get_irq(pdev, 0); + if (!res_mem || irq < 0) return -ENODEV; if (BCMCPU_IS_6348()) { @@ -114,7 +114,7 @@ static int __devinit ohci_hcd_bcm63xx_drv_probe(struct platform_device *pdev) OHCI_QUIRK_FRAME_NO; ohci_hcd_init(ohci); - ret = usb_add_hcd(hcd, res_irq->start, IRQF_DISABLED); + ret = usb_add_hcd(hcd, irq, IRQF_DISABLED); if (ret) goto out2; -- 1.6.0.4 From sshtylyov@ru.mvista.com Mon Jun 1 18:56:45 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 01 Jun 2009 18:56:52 +0100 (WEST) Received: from h155.mvista.com ([63.81.120.155]:56773 "EHLO imap.sh.mvista.com" rhost-flags-OK-FAIL-OK-FAIL) by ftp.linux-mips.org with ESMTP id S20025719AbZFAR4p (ORCPT ); Mon, 1 Jun 2009 18:56:45 +0100 Received: from [192.168.11.189] (unknown [10.150.0.9]) by imap.sh.mvista.com (Postfix) with ESMTP id 6C5573ECB; Mon, 1 Jun 2009 10:56:41 -0700 (PDT) Message-ID: <4A2416A4.4070902@ru.mvista.com> Date: Mon, 01 Jun 2009 21:57:56 +0400 From: Sergei Shtylyov Organization: MontaVista Software Inc. User-Agent: Mozilla/5.0 (X11; U; Linux i686; rv:1.7.2) Gecko/20040803 X-Accept-Language: ru, en-us, en-gb MIME-Version: 1.0 To: Maxime Bizon Cc: linux-mips@linux-mips.org, Ralf Baechle , Florian Fainelli Subject: Re: [PATCH 10/10] bcm63xx: clarify meaning of the magical value in ehci-bcm63xx.c References: <1243876918-9905-1-git-send-email-mbizon@freebox.fr> <1243876918-9905-11-git-send-email-mbizon@freebox.fr> In-Reply-To: <1243876918-9905-11-git-send-email-mbizon@freebox.fr> Content-Type: text/plain; charset=us-ascii; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23141 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sshtylyov@ru.mvista.com Precedence: bulk X-list: linux-mips Hello. Maxime Bizon wrote: > USB maintainer asked for clarification of the magic value used during > USB init. Be clear about the source of it. > Signed-off-by: Maxime Bizon > --- > drivers/usb/host/ehci-bcm63xx.c | 4 +++- > 1 files changed, 3 insertions(+), 1 deletions(-) > diff --git a/drivers/usb/host/ehci-bcm63xx.c b/drivers/usb/host/ehci-bcm63xx.c > index 8a62c0a..5a03fdd 100644 > --- a/drivers/usb/host/ehci-bcm63xx.c > +++ b/drivers/usb/host/ehci-bcm63xx.c > @@ -78,7 +78,9 @@ static int __devinit ehci_hcd_bcm63xx_drv_probe(struct platform_device *pdev) > reg |= USBH_PRIV_SWAP_EHCI_ENDN_MASK; > bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SWAP_REG); > > - /* don't ask... */ > + /* the magic value comes for the original vendor BSP and is > + * needed for USB to work. Datasheet does not help, so the > + * magic value is used as-is. */ > bcm_rset_writel(RSET_USBH_PRIV, 0x1c0020, USBH_PRIV_TEST_REG); > > hcd = usb_create_hcd(&ehci_bcm63xx_hc_driver, &pdev->dev, "bcm63xx"); Documentation/CodingStyle, chapter 8: The preferred style for long (multi-line) comments is: /* * This is the preferred style for multi-line * comments in the Linux kernel source code. * Please use it consistently. * * Description: A column of asterisks on the left side, * with beginning and ending almost-blank lines. */ WBR, Sergei From f.fainelli@gmail.com Mon Jun 1 19:08:02 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 01 Jun 2009 19:08:09 +0100 (WEST) Received: from mail-ew0-f219.google.com ([209.85.219.219]:39870 "EHLO mail-ew0-f219.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20023376AbZFASIC convert rfc822-to-8bit (ORCPT ); Mon, 1 Jun 2009 19:08:02 +0100 Received: by ewy19 with SMTP id 19so8321366ewy.0 for ; Mon, 01 Jun 2009 11:07:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:sender:from:to:subject:date :user-agent:cc:references:in-reply-to:mime-version:content-type :content-transfer-encoding:content-disposition:message-id; bh=IjcI12sqBxqY1TwjGQhR/SmSLkmtSuRH2NNfHziodes=; b=kIhia/p6UNccNflgwVfFgcZt88e/PuvpxZtspYKN+b4rruqz9PZPyq4uVJHEdzgRAj NL4EJGO49ic65gYDLYfAKjCXHUwjo9FCbZMJn45qqHNIO+jRHhIq4nIyF53R15LBdT48 J9328K7vgxDnC+p8B4Ptduz672INz4G3ssCtc= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:from:to:subject:date:user-agent:cc:references:in-reply-to :mime-version:content-type:content-transfer-encoding :content-disposition:message-id; b=FzO76LPIKEg4+sT300IxxUtFR+E1Pd8FUpZkBxAZs+yy2ReavEoGzxc3LJGLYdppcY 904+TI0lRzv+lxZoUTE+U3gkV1qYVXs1l/Co+y3OnwqGUdzxsVneGA1hEgfs2W/2rKFx wbjpsEfeOaKyco3eJHCep8wIeCECQ8QN02Ba8= Received: by 10.210.60.8 with SMTP id i8mr3643874eba.35.1243879676573; Mon, 01 Jun 2009 11:07:56 -0700 (PDT) Received: from florian (207.130.195-77.rev.gaoland.net [77.195.130.207]) by mx.google.com with ESMTPS id 23sm127157eya.59.2009.06.01.11.07.55 (version=TLSv1/SSLv3 cipher=RC4-MD5); Mon, 01 Jun 2009 11:07:55 -0700 (PDT) From: Florian Fainelli To: Maxime Bizon Subject: Re: [PATCH 01/10] bcm63xx: remove duplicate init fields. Date: Mon, 1 Jun 2009 20:07:53 +0200 User-Agent: KMail/1.9.9 Cc: linux-mips@linux-mips.org, Ralf Baechle References: <1243876918-9905-1-git-send-email-mbizon@freebox.fr> <1243876918-9905-2-git-send-email-mbizon@freebox.fr> In-Reply-To: <1243876918-9905-2-git-send-email-mbizon@freebox.fr> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8BIT Content-Disposition: inline Message-Id: <200906012007.53758.florian@openwrt.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23142 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips Le Monday 01 June 2009 19:21:49 Maxime Bizon, vous avez écrit : > This patch removes duplicate init fields in resource. > > Signed-off-by: Maxime Bizon Acked-by: Florian Fainelli > --- > arch/mips/bcm63xx/dev-enet.c | 2 -- > 1 files changed, 0 insertions(+), 2 deletions(-) > > diff --git a/arch/mips/bcm63xx/dev-enet.c b/arch/mips/bcm63xx/dev-enet.c > index 51c2e5a..188fa66 100644 > --- a/arch/mips/bcm63xx/dev-enet.c > +++ b/arch/mips/bcm63xx/dev-enet.c > @@ -42,12 +42,10 @@ static struct resource enet0_res[] = { > }, > { > .start = -1, /* filled at runtime */ > - .start = IRQ_ENET0_RXDMA, > .flags = IORESOURCE_IRQ, > }, > { > .start = -1, /* filled at runtime */ > - .start = IRQ_ENET0_TXDMA, > .flags = IORESOURCE_IRQ, > }, > }; From f.fainelli@gmail.com Mon Jun 1 19:09:11 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 01 Jun 2009 19:09:19 +0100 (WEST) Received: from mail-ew0-f219.google.com ([209.85.219.219]:45526 "EHLO mail-ew0-f219.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20023379AbZFASJL convert rfc822-to-8bit (ORCPT ); Mon, 1 Jun 2009 19:09:11 +0100 Received: by ewy19 with SMTP id 19so8322152ewy.0 for ; Mon, 01 Jun 2009 11:09:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:sender:from:to:subject:date :user-agent:cc:references:in-reply-to:mime-version:content-type :content-transfer-encoding:content-disposition:message-id; bh=eqSrgNkG+3/6PvNeluhcdY+QMGw+vKiLIfzcu2FV5ko=; b=M2TpWSGr6zukVX71gEQg+Iak1QlscCmUGLzIXrvxg1de1kXty0l8lBeHEeHpzwCPbs spZBIV7/ztFiK7itvKaOBxJrD/Hgh9pGa6Sz5Xt1Df4+leKENuNkxErdDcWXNgby1ZQb JjoUE3bYyEFOu7js+NdIYE8ZJWWTIYz0q55JA= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:from:to:subject:date:user-agent:cc:references:in-reply-to :mime-version:content-type:content-transfer-encoding :content-disposition:message-id; b=Bqh02IpC2C+QHVtOboapAbqpDqalawWyQjfZJTE4xHvux+AaekGnuz93ZI0VGLxpVc bfHfadwnIl3GSsM3VOG52CCXy5rM/DotTF50FWmNoTDPaIC0UAZm2eMEURpg4P4nbxJe AYwpiLV5QUFwP1XqIPJG2zhJ+QFfncad8HtlQ= Received: by 10.211.180.15 with SMTP id h15mr1200268ebp.97.1243879745761; Mon, 01 Jun 2009 11:09:05 -0700 (PDT) Received: from florian (207.130.195-77.rev.gaoland.net [77.195.130.207]) by mx.google.com with ESMTPS id 7sm7773eyg.17.2009.06.01.11.09.04 (version=TLSv1/SSLv3 cipher=RC4-MD5); Mon, 01 Jun 2009 11:09:04 -0700 (PDT) From: Florian Fainelli To: Maxime Bizon Subject: Re: [PATCH 02/10] bcm63xx: use napi_complete instead of __napi_complete Date: Mon, 1 Jun 2009 20:09:02 +0200 User-Agent: KMail/1.9.9 Cc: linux-mips@linux-mips.org, Ralf Baechle References: <1243876918-9905-1-git-send-email-mbizon@freebox.fr> <1243876918-9905-3-git-send-email-mbizon@freebox.fr> In-Reply-To: <1243876918-9905-3-git-send-email-mbizon@freebox.fr> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8BIT Content-Disposition: inline Message-Id: <200906012009.03194.florian@openwrt.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23143 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips Le Monday 01 June 2009 19:21:50 Maxime Bizon, vous avez écrit : > We're not disabling IRQ, so we must call the irq safe flavour of > napi_complete. > > Signed-off-by: Maxime Bizon Tested-by: Florian Fainelli Acked-by: Florian Fainelli > --- > drivers/net/bcm63xx_enet.c | 2 +- > 1 files changed, 1 insertions(+), 1 deletions(-) > > diff --git a/drivers/net/bcm63xx_enet.c b/drivers/net/bcm63xx_enet.c > index a91f909..20e08ef 100644 > --- a/drivers/net/bcm63xx_enet.c > +++ b/drivers/net/bcm63xx_enet.c > @@ -450,7 +450,7 @@ static int bcm_enet_poll(struct napi_struct *napi, int > budget) > > /* no more packet in rx/tx queue, remove device from poll > * queue */ > - __napi_complete(napi); > + napi_complete(napi); > > /* restore rx/tx interrupt */ > enet_dma_writel(priv, ENETDMA_IR_PKTDONE_MASK, From f.fainelli@gmail.com Mon Jun 1 19:10:17 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 01 Jun 2009 19:10:28 +0100 (WEST) Received: from mail-ew0-f219.google.com ([209.85.219.219]:41286 "EHLO mail-ew0-f219.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20023445AbZFASKR convert rfc822-to-8bit (ORCPT ); Mon, 1 Jun 2009 19:10:17 +0100 Received: by ewy19 with SMTP id 19so8322936ewy.0 for ; Mon, 01 Jun 2009 11:10:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:sender:from:to:subject:date :user-agent:cc:references:in-reply-to:mime-version:content-type :content-transfer-encoding:content-disposition:message-id; bh=DwTDCDoj8Cxpw/J3KwT3ybz+mydC2GbgvmCtDip2sfw=; b=xg656avkXYxUUjB0+tPZMRn/h8nHfyUSFNCuNuRnk/+5P0XM/4ul/Vj3dW9Xpd45Th UoXknm+3gmwRhcqXxmog3iPhjeL3sTonG+mHiVy2TJ1xO6cS/vajO3Dr9Lz0421XYHXp wwsST4ukfM5i7C0gCTXOVZNbmqzRnJVdkFK6o= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:from:to:subject:date:user-agent:cc:references:in-reply-to :mime-version:content-type:content-transfer-encoding :content-disposition:message-id; b=oMBozc66Uku/K09tto+VT9grBEs19/TqsP9R7ZGk3019zkPeDy2SLk8+llobeBXDL7 stHsvyRkxga8DK4xN8ucQiS5abqKxDUC0O0wVxy/1wfPV84KkCGgWQTpH+C4ZVd4qnaP M1cjgynyFpl1JX9rZdE9PDsMCdu8tRL6al4r4= Received: by 10.210.33.3 with SMTP id g3mr4380033ebg.27.1243879811241; Mon, 01 Jun 2009 11:10:11 -0700 (PDT) Received: from florian (207.130.195-77.rev.gaoland.net [77.195.130.207]) by mx.google.com with ESMTPS id 28sm60411eye.6.2009.06.01.11.10.10 (version=TLSv1/SSLv3 cipher=RC4-MD5); Mon, 01 Jun 2009 11:10:10 -0700 (PDT) From: Florian Fainelli To: Maxime Bizon Subject: Re: [PATCH 03/10] bcm63xx: convert bcm63xx_enet to netdev ops. Date: Mon, 1 Jun 2009 20:10:08 +0200 User-Agent: KMail/1.9.9 Cc: linux-mips@linux-mips.org, Ralf Baechle References: <1243876918-9905-1-git-send-email-mbizon@freebox.fr> <1243876918-9905-4-git-send-email-mbizon@freebox.fr> In-Reply-To: <1243876918-9905-4-git-send-email-mbizon@freebox.fr> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8BIT Content-Disposition: inline Message-Id: <200906012010.09162.florian@openwrt.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23144 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips Le Monday 01 June 2009 19:21:51 Maxime Bizon, vous avez écrit : > This patch makes bcm63xx_enet driver use netdevice ops. > > Signed-off-by: Maxime Bizon Acked-by: Florian Fainelli > --- > drivers/net/bcm63xx_enet.c | 24 ++++++++++++++---------- > 1 files changed, 14 insertions(+), 10 deletions(-) > > diff --git a/drivers/net/bcm63xx_enet.c b/drivers/net/bcm63xx_enet.c > index 20e08ef..36324b3 100644 > --- a/drivers/net/bcm63xx_enet.c > +++ b/drivers/net/bcm63xx_enet.c > @@ -1551,6 +1551,19 @@ static void bcm_enet_hw_preinit(struct bcm_enet_priv > *priv) enet_writel(priv, val, ENET_MIBCTL_REG); > } > > +static const struct net_device_ops bcm_enet_ops = { > + .ndo_open = bcm_enet_open, > + .ndo_stop = bcm_enet_stop, > + .ndo_start_xmit = bcm_enet_start_xmit, > + .ndo_get_stats = bcm_enet_get_stats, > + .ndo_set_mac_address = bcm_enet_set_mac_address, > + .ndo_set_multicast_list = bcm_enet_set_multicast_list, > + .ndo_do_ioctl = bcm_enet_ioctl, > +#ifdef CONFIG_NET_POLL_CONTROLLER > + .ndo_poll_controller = bcm_enet_netpoll, > +#endif > +}; > + > /* > * allocate netdevice, request register memory and register device. > */ > @@ -1716,17 +1729,8 @@ static int __devinit bcm_enet_probe(struct > platform_device *pdev) enet_writel(priv, 0, ENET_MIB_REG(i)); > > /* register netdevice */ > - dev->open = bcm_enet_open; > - dev->stop = bcm_enet_stop; > - dev->hard_start_xmit = bcm_enet_start_xmit; > - dev->get_stats = bcm_enet_get_stats; > - dev->set_mac_address = bcm_enet_set_mac_address; > - dev->set_multicast_list = bcm_enet_set_multicast_list; > + dev->netdev_ops = &bcm_enet_ops; > netif_napi_add(dev, &priv->napi, bcm_enet_poll, 16); > - dev->do_ioctl = bcm_enet_ioctl; > -#ifdef CONFIG_NET_POLL_CONTROLLER > - dev->poll_controller = bcm_enet_netpoll; > -#endif > > SET_ETHTOOL_OPS(dev, &bcm_enet_ethtool_ops); -- Best regards, Florian Fainelli Email : florian@openwrt.org http://openwrt.org ------------------------------- From f.fainelli@gmail.com Mon Jun 1 19:10:46 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 01 Jun 2009 19:10:53 +0100 (WEST) Received: from mail-ew0-f219.google.com ([209.85.219.219]:41286 "EHLO mail-ew0-f219.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20024925AbZFASKZ convert rfc822-to-8bit (ORCPT ); Mon, 1 Jun 2009 19:10:25 +0100 Received: by mail-ew0-f219.google.com with SMTP id 19so8322936ewy.0 for ; Mon, 01 Jun 2009 11:10:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:sender:from:to:subject:date :user-agent:cc:references:in-reply-to:mime-version:content-type :content-transfer-encoding:content-disposition:message-id; bh=AccaS+fTlj6++G5XmP1ONYqiJmjbGt6kDwo8vc9Dqmc=; b=K6XhOq0nSzPSlEnvntDnn6g5mOAKbDIJiNvQE326OdcphRC1hjKs5cqhXmwN7CwUzB H+IFRruGHzg48MBkfwM2ijkj7NpAAiOjqAChvfM8kaBRADiI3oot3WLinnaV+LK3AXSG 97ISpYSMmlTKhRfDKaTLD2hJ93uw8bl5aZ+TE= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:from:to:subject:date:user-agent:cc:references:in-reply-to :mime-version:content-type:content-transfer-encoding :content-disposition:message-id; b=rPs3O6Q//js3re5mG6izmt9KogN2YxMHScDhRPb4dPnCyyz2GcWBl6lqQRXB6bRyV5 dH9zxtVgO0Y6ApFLDlIxYqgiBAYVg0pDiAL9BGXQ/wqBhqrkqcPNZTWrH81JXTrpEL+X 3ZV6NmLg6xm1DOTpRkGD/IkxzuZvxoiMo7ZSY= Received: by 10.210.91.7 with SMTP id o7mr6709921ebb.76.1243879825010; Mon, 01 Jun 2009 11:10:25 -0700 (PDT) Received: from florian (207.130.195-77.rev.gaoland.net [77.195.130.207]) by mx.google.com with ESMTPS id 5sm15666eyh.10.2009.06.01.11.10.23 (version=TLSv1/SSLv3 cipher=RC4-MD5); Mon, 01 Jun 2009 11:10:23 -0700 (PDT) From: Florian Fainelli To: Maxime Bizon Subject: Re: [PATCH 04/10] bcm63xx: limit number of usb port to 1. Date: Mon, 1 Jun 2009 20:10:21 +0200 User-Agent: KMail/1.9.9 Cc: linux-mips@linux-mips.org, Ralf Baechle References: <1243876918-9905-1-git-send-email-mbizon@freebox.fr> <1243876918-9905-5-git-send-email-mbizon@freebox.fr> In-Reply-To: <1243876918-9905-5-git-send-email-mbizon@freebox.fr> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8BIT Content-Disposition: inline Message-Id: <200906012010.21712.florian@openwrt.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23145 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips Le Monday 01 June 2009 19:21:52 Maxime Bizon, vous avez écrit : > This patch disables the use of more than one USB port. Hardware has > two ports, but one may be shared with USB slave port. > > Until we have this information in the platform data, don't use the > second port. > > Signed-off-by: Maxime Bizon Acked-by: Florian Fainelli > --- > drivers/usb/host/ohci-bcm63xx.c | 2 ++ > 1 files changed, 2 insertions(+), 0 deletions(-) > > diff --git a/drivers/usb/host/ohci-bcm63xx.c > b/drivers/usb/host/ohci-bcm63xx.c index 08807d9..74f432f 100644 > --- a/drivers/usb/host/ohci-bcm63xx.c > +++ b/drivers/usb/host/ohci-bcm63xx.c > @@ -20,6 +20,8 @@ static int __devinit ohci_bcm63xx_start(struct usb_hcd > *hcd) struct ohci_hcd *ohci = hcd_to_ohci(hcd); > int ret; > > + ohci->num_ports = 1; > + > ret = ohci_init(ohci); > if (ret < 0) > return ret; -- Best regards, Florian Fainelli Email : florian@openwrt.org http://openwrt.org ------------------------------- From f.fainelli@gmail.com Mon Jun 1 19:11:36 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 01 Jun 2009 19:11:42 +0100 (WEST) Received: from mail-ew0-f219.google.com ([209.85.219.219]:50307 "EHLO mail-ew0-f219.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20024213AbZFASLg convert rfc822-to-8bit (ORCPT ); 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Mon, 01 Jun 2009 11:11:30 -0700 (PDT) Received: from florian (207.130.195-77.rev.gaoland.net [77.195.130.207]) by mx.google.com with ESMTPS id 7sm58557eyg.57.2009.06.01.11.11.24 (version=TLSv1/SSLv3 cipher=RC4-MD5); Mon, 01 Jun 2009 11:11:27 -0700 (PDT) From: Florian Fainelli To: Maxime Bizon Subject: Re: [PATCH 05/10] bcm63xx: use platform_get_irq in ohci-bcm63xx.c Date: Mon, 1 Jun 2009 20:11:23 +0200 User-Agent: KMail/1.9.9 Cc: linux-mips@linux-mips.org, Ralf Baechle References: <1243876918-9905-1-git-send-email-mbizon@freebox.fr> <1243876918-9905-6-git-send-email-mbizon@freebox.fr> In-Reply-To: <1243876918-9905-6-git-send-email-mbizon@freebox.fr> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8BIT Content-Disposition: inline Message-Id: <200906012011.23576.florian@openwrt.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23146 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips Le Monday 01 June 2009 19:21:53 Maxime Bizon, vous avez écrit : > As requested by USB maintainer, use platform_get_irq instead of > platform_get_resource. > > Signed-off-by: Maxime Bizon Acked-by: Florian Fainelli > --- > drivers/usb/host/ohci-bcm63xx.c | 10 +++++----- > 1 files changed, 5 insertions(+), 5 deletions(-) > > diff --git a/drivers/usb/host/ohci-bcm63xx.c > b/drivers/usb/host/ohci-bcm63xx.c index 74f432f..f0e4639 100644 > --- a/drivers/usb/host/ohci-bcm63xx.c > +++ b/drivers/usb/host/ohci-bcm63xx.c > @@ -58,15 +58,15 @@ static const struct hc_driver ohci_bcm63xx_hc_driver = > { > > static int __devinit ohci_hcd_bcm63xx_drv_probe(struct platform_device > *pdev) { > - struct resource *res_mem, *res_irq; > + struct resource *res_mem; > struct usb_hcd *hcd; > struct ohci_hcd *ohci; > u32 reg; > - int ret; > + int ret, irq; > > res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); > - res_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); > - if (!res_mem || !res_irq) > + irq = platform_get_irq(pdev, 0); > + if (!res_mem || irq < 0) > return -ENODEV; > > if (BCMCPU_IS_6348()) { > @@ -114,7 +114,7 @@ static int __devinit ohci_hcd_bcm63xx_drv_probe(struct > platform_device *pdev) OHCI_QUIRK_FRAME_NO; > ohci_hcd_init(ohci); > > - ret = usb_add_hcd(hcd, res_irq->start, IRQF_DISABLED); > + ret = usb_add_hcd(hcd, irq, IRQF_DISABLED); > if (ret) > goto out2; -- Best regards, Florian Fainelli Email : florian@openwrt.org http://openwrt.org ------------------------------- From f.fainelli@gmail.com Mon Jun 1 19:11:59 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 01 Jun 2009 19:12:06 +0100 (WEST) Received: from mail-ew0-f219.google.com ([209.85.219.219]:50307 "EHLO mail-ew0-f219.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20024908AbZFASLn convert rfc822-to-8bit (ORCPT ); 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Mon, 01 Jun 2009 11:11:42 -0700 (PDT) Received: from florian (207.130.195-77.rev.gaoland.net [77.195.130.207]) by mx.google.com with ESMTPS id 24sm325249eyx.23.2009.06.01.11.11.41 (version=TLSv1/SSLv3 cipher=RC4-MD5); Mon, 01 Jun 2009 11:11:42 -0700 (PDT) From: Florian Fainelli To: Maxime Bizon Subject: Re: [PATCH 06/10] bcm63xx: don't set bus type in ohci-bcm63xx.c Date: Mon, 1 Jun 2009 20:11:39 +0200 User-Agent: KMail/1.9.9 Cc: linux-mips@linux-mips.org, Ralf Baechle References: <1243876918-9905-1-git-send-email-mbizon@freebox.fr> <1243876918-9905-7-git-send-email-mbizon@freebox.fr> In-Reply-To: <1243876918-9905-7-git-send-email-mbizon@freebox.fr> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8BIT Content-Disposition: inline Message-Id: <200906012011.40170.florian@openwrt.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23147 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips Le Monday 01 June 2009 19:21:54 Maxime Bizon, vous avez écrit : > The platform code already sets the bus type, so don't do it. > > Signed-off-by: Maxime Bizon Acked-by: Florian Fainelli > --- > drivers/usb/host/ohci-bcm63xx.c | 1 - > 1 files changed, 0 insertions(+), 1 deletions(-) > > diff --git a/drivers/usb/host/ohci-bcm63xx.c > b/drivers/usb/host/ohci-bcm63xx.c index f0e4639..d48c8ac 100644 > --- a/drivers/usb/host/ohci-bcm63xx.c > +++ b/drivers/usb/host/ohci-bcm63xx.c > @@ -154,7 +154,6 @@ static struct platform_driver ohci_hcd_bcm63xx_driver = > { .driver = { > .name = "bcm63xx_ohci", > .owner = THIS_MODULE, > - .bus = &platform_bus_type > }, > }; -- Best regards, Florian Fainelli Email : florian@openwrt.org http://openwrt.org ------------------------------- From f.fainelli@gmail.com Mon Jun 1 19:12:23 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 01 Jun 2009 19:12:29 +0100 (WEST) Received: from ey-out-1920.google.com ([74.125.78.147]:55347 "EHLO ey-out-1920.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20024960AbZFASL6 convert rfc822-to-8bit (ORCPT ); Mon, 1 Jun 2009 19:11:58 +0100 Received: by ey-out-1920.google.com with SMTP id 4so446786eyg.54 for ; Mon, 01 Jun 2009 11:11:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:sender:from:to:subject:date :user-agent:cc:references:in-reply-to:mime-version:content-type :content-transfer-encoding:content-disposition:message-id; bh=ABTBV+PxGmew6DWQrYZiZkijTxvLHpxV3+ZbJO29VVU=; b=BbGDLFjL1PqGZ4xZy/lZbdrzKi+Kwjxx/MN3GrnRXO8clTldbLKaei/nH9U5odadsG 2dUbX4YTvruQcKelOmairl0cBWK4QbFB1llLCleH/st9ENjVyUN6cEldlKuKK/EGnXRQ A9nASw3rOBE3tDfm+8epU1g1U1IarNVhfUz88= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:from:to:subject:date:user-agent:cc:references:in-reply-to :mime-version:content-type:content-transfer-encoding :content-disposition:message-id; b=jab3sLJ9fnp6x+Jkz+6A22zfQiyJtbMmvYoNQfOx7ah/Y/YyjgJRqUlXo9nciHLCaq sGoKrxJm8BCRAEZ3wDkuQ7ACOOZlRQmBpdg7cRADMEBeMfmnHWkjAC9a6zpu2xNM6Chj 6KldX64y1QtkLtRYULClF2FEPMTYOwd5AJu04= Received: by 10.210.43.11 with SMTP id q11mr1868958ebq.86.1243879917752; Mon, 01 Jun 2009 11:11:57 -0700 (PDT) Received: from florian (207.130.195-77.rev.gaoland.net [77.195.130.207]) by mx.google.com with ESMTPS id 23sm131541eya.59.2009.06.01.11.11.53 (version=TLSv1/SSLv3 cipher=RC4-MD5); Mon, 01 Jun 2009 11:11:56 -0700 (PDT) From: Florian Fainelli To: Maxime Bizon Subject: Re: [PATCH 07/10] bcm63xx: clarify meaning of the magical value in ohci-bcm63xx.c Date: Mon, 1 Jun 2009 20:11:51 +0200 User-Agent: KMail/1.9.9 Cc: linux-mips@linux-mips.org, Ralf Baechle References: <1243876918-9905-1-git-send-email-mbizon@freebox.fr> <1243876918-9905-8-git-send-email-mbizon@freebox.fr> In-Reply-To: <1243876918-9905-8-git-send-email-mbizon@freebox.fr> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8BIT Content-Disposition: inline Message-Id: <200906012011.52421.florian@openwrt.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23148 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips Le Monday 01 June 2009 19:21:55 Maxime Bizon, vous avez écrit : > USB maintainer asked for clarification of the magic value used during > USB init. Be clear about the source of it. > > Signed-off-by: Maxime Bizon Acked-by: Florian Fainelli > --- > drivers/usb/host/ohci-bcm63xx.c | 4 +++- > 1 files changed, 3 insertions(+), 1 deletions(-) > > diff --git a/drivers/usb/host/ohci-bcm63xx.c > b/drivers/usb/host/ohci-bcm63xx.c index d48c8ac..bd66d5a 100644 > --- a/drivers/usb/host/ohci-bcm63xx.c > +++ b/drivers/usb/host/ohci-bcm63xx.c > @@ -85,7 +85,9 @@ static int __devinit ohci_hcd_bcm63xx_drv_probe(struct > platform_device *pdev) reg &= ~USBH_PRIV_SWAP_OHCI_ENDN_MASK; > reg |= USBH_PRIV_SWAP_OHCI_DATA_MASK; > bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SWAP_REG); > - /* don't ask... */ > + /* the magic value comes for the original vendor BSP > + * and is needed for USB to work. Datasheet does not > + * help, so the magic value is used as-is. */ > bcm_rset_writel(RSET_USBH_PRIV, 0x1c0020, USBH_PRIV_TEST_REG); > } else > return 0; -- Best regards, Florian Fainelli Email : florian@openwrt.org http://openwrt.org ------------------------------- From f.fainelli@gmail.com Mon Jun 1 19:12:46 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 01 Jun 2009 19:12:54 +0100 (WEST) Received: from mail-ew0-f219.google.com ([209.85.219.219]:50307 "EHLO mail-ew0-f219.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20024116AbZFASMJ convert rfc822-to-8bit (ORCPT ); Mon, 1 Jun 2009 19:12:09 +0100 Received: by mail-ew0-f219.google.com with SMTP id 19so8324030ewy.0 for ; Mon, 01 Jun 2009 11:12:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:sender:from:to:subject:date :user-agent:cc:references:in-reply-to:mime-version:content-type :content-transfer-encoding:content-disposition:message-id; bh=46aFMGEgFNOkmMlgxr3iOions2dAjUyKanwN03FfLO0=; b=HG6o9Yum+kmsGvoGg3yNZZxu2n5ce7yhOpnvGObV5R4Cpivk+pqelazMYuzrh6n2p1 Rd9vvqxX/5wmKMrWRzTW+KgizZ427xplyD444D8sZ53zjgRXpGtGmPDvDkg5d9nDFFjA eIVfNjEPPwVGCkx0FIwAESA0U6xRbggmEeOzU= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:from:to:subject:date:user-agent:cc:references:in-reply-to :mime-version:content-type:content-transfer-encoding :content-disposition:message-id; b=IZm3xZnSiG/7cNvP5aRmDtFrbKWwhv2+Ru2imzHjMko5kW+i9tuVSpgNSOmFaPWgn2 ENNJmpWlulCZxfRot86M/wKDKOxC696PRpkh+igC/qXkMs1KLKrInDQyxhG++yEW/+3U SSfg5/DKE/faVjFcahlixUV3jtQdZ3/K2bvfE= Received: by 10.210.33.15 with SMTP id g15mr6742035ebg.63.1243879929446; Mon, 01 Jun 2009 11:12:09 -0700 (PDT) Received: from florian (207.130.195-77.rev.gaoland.net [77.195.130.207]) by mx.google.com with ESMTPS id 5sm198371eyh.50.2009.06.01.11.12.07 (version=TLSv1/SSLv3 cipher=RC4-MD5); Mon, 01 Jun 2009 11:12:08 -0700 (PDT) From: Florian Fainelli To: Maxime Bizon Subject: Re: [PATCH 08/10] bcm63xx: use platform_get_irq in ehci-bcm63xx.c Date: Mon, 1 Jun 2009 20:12:05 +0200 User-Agent: KMail/1.9.9 Cc: linux-mips@linux-mips.org, Ralf Baechle References: <1243876918-9905-1-git-send-email-mbizon@freebox.fr> <1243876918-9905-9-git-send-email-mbizon@freebox.fr> In-Reply-To: <1243876918-9905-9-git-send-email-mbizon@freebox.fr> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8BIT Content-Disposition: inline Message-Id: <200906012012.06132.florian@openwrt.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23149 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips Le Monday 01 June 2009 19:21:56 Maxime Bizon, vous avez écrit : > As requested by USB maintainer, use platform_get_irq instead of > platform_get_resource. > > Signed-off-by: Maxime Bizon Acked-by: Florian Fainelli > --- > drivers/usb/host/ehci-bcm63xx.c | 10 +++++----- > 1 files changed, 5 insertions(+), 5 deletions(-) > > diff --git a/drivers/usb/host/ehci-bcm63xx.c > b/drivers/usb/host/ehci-bcm63xx.c index 2fef571..0aba0f9 100644 > --- a/drivers/usb/host/ehci-bcm63xx.c > +++ b/drivers/usb/host/ehci-bcm63xx.c > @@ -62,15 +62,15 @@ static const struct hc_driver ehci_bcm63xx_hc_driver = > { > > static int __devinit ehci_hcd_bcm63xx_drv_probe(struct platform_device > *pdev) { > - struct resource *res_mem, *res_irq; > + struct resource *res_mem; > struct usb_hcd *hcd; > struct ehci_hcd *ehci; > u32 reg; > - int ret; > + int ret, irq; > > res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); > - res_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); > - if (!res_mem || !res_irq) > + irq = platform_get_irq(pdev, 0);; > + if (!res_mem || irq < 0) > return -ENODEV; > > reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SWAP_REG); > @@ -109,7 +109,7 @@ static int __devinit ehci_hcd_bcm63xx_drv_probe(struct > platform_device *pdev) ehci->hcs_params = ehci_readl(ehci, > &ehci->caps->hcs_params); > ehci->sbrn = 0x20; > > - ret = usb_add_hcd(hcd, res_irq->start, IRQF_DISABLED); > + ret = usb_add_hcd(hcd, irq, IRQF_DISABLED); > if (ret) > goto out2; -- Best regards, Florian Fainelli Email : florian@openwrt.org http://openwrt.org ------------------------------- From f.fainelli@gmail.com Mon Jun 1 19:13:11 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 01 Jun 2009 19:13:17 +0100 (WEST) Received: from ey-out-1920.google.com ([74.125.78.144]:6982 "EHLO ey-out-1920.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20025017AbZFASMc convert rfc822-to-8bit (ORCPT ); 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Mon, 01 Jun 2009 11:12:29 -0700 (PDT) Received: from florian (207.130.195-77.rev.gaoland.net [77.195.130.207]) by mx.google.com with ESMTPS id 5sm115344eyf.48.2009.06.01.11.12.25 (version=TLSv1/SSLv3 cipher=RC4-MD5); Mon, 01 Jun 2009 11:12:27 -0700 (PDT) From: Florian Fainelli To: Maxime Bizon Subject: Re: [PATCH 09/10] bcm63xx: don't set bus type in ehci-bcm63xx.c Date: Mon, 1 Jun 2009 20:12:23 +0200 User-Agent: KMail/1.9.9 Cc: linux-mips@linux-mips.org, Ralf Baechle References: <1243876918-9905-1-git-send-email-mbizon@freebox.fr> <1243876918-9905-10-git-send-email-mbizon@freebox.fr> In-Reply-To: <1243876918-9905-10-git-send-email-mbizon@freebox.fr> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8BIT Content-Disposition: inline Message-Id: <200906012012.24267.florian@openwrt.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23150 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips Le Monday 01 June 2009 19:21:57 Maxime Bizon, vous avez écrit : > The platform code already sets the bus type, so don't do it. > > Signed-off-by: Maxime Bizon Acked-by: Florian Fainelli > --- > drivers/usb/host/ehci-bcm63xx.c | 1 - > 1 files changed, 0 insertions(+), 1 deletions(-) > > diff --git a/drivers/usb/host/ehci-bcm63xx.c > b/drivers/usb/host/ehci-bcm63xx.c index 0aba0f9..8a62c0a 100644 > --- a/drivers/usb/host/ehci-bcm63xx.c > +++ b/drivers/usb/host/ehci-bcm63xx.c > @@ -145,7 +145,6 @@ static struct platform_driver ehci_hcd_bcm63xx_driver = > { .driver = { > .name = "bcm63xx_ehci", > .owner = THIS_MODULE, > - .bus = &platform_bus_type > }, > }; -- Best regards, Florian Fainelli Email : florian@openwrt.org http://openwrt.org ------------------------------- From f.fainelli@gmail.com Mon Jun 1 19:13:34 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 01 Jun 2009 19:13:41 +0100 (WEST) Received: from mail-ew0-f219.google.com ([209.85.219.219]:62433 "EHLO mail-ew0-f219.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20025041AbZFASMv convert rfc822-to-8bit (ORCPT ); Mon, 1 Jun 2009 19:12:51 +0100 Received: by ewy19 with SMTP id 19so8324904ewy.0 for ; Mon, 01 Jun 2009 11:12:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:sender:from:to:subject:date :user-agent:cc:references:in-reply-to:mime-version:content-type :content-transfer-encoding:content-disposition:message-id; bh=4wc4uzcAxNxN4F9ULcIYFLjDTmV0aCdZwDUkwvcqYnU=; b=lqsdrKD0RKApWQF59hOPdws1NBK21/trqD3JNWBcOg7hMPUd2XpBAPI7fcID1H+vJY RY59f9urQHTjogeDmPDg7GSVIilhYcd28hntBj1bau0D0xIzeWAVqWrxQasntCqVTFtJ YmcuzRuQjjGN8Q0f0/Xt1BHln3NKL8TSuIFxs= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:from:to:subject:date:user-agent:cc:references:in-reply-to :mime-version:content-type:content-transfer-encoding :content-disposition:message-id; b=VXbIC5viDjIUjNZOgJO+xlhYWrXMMCvigBcRD35GBD/BOZK2C5IU103s0N3RISn4lY FB9Pmw/7WC2rLtDSqVrG+0qFiVOlWR4w/M+3P2of1EUmJLglIh63EGG1xqCgA66A1SG7 Liw9zue/gKso6sn8+QgQjXWbM1aPFubQuo5sQ= Received: by 10.210.71.12 with SMTP id t12mr3654603eba.68.1243879965397; Mon, 01 Jun 2009 11:12:45 -0700 (PDT) Received: from florian (207.130.195-77.rev.gaoland.net [77.195.130.207]) by mx.google.com with ESMTPS id 28sm56491eyg.44.2009.06.01.11.12.43 (version=TLSv1/SSLv3 cipher=RC4-MD5); Mon, 01 Jun 2009 11:12:44 -0700 (PDT) From: Florian Fainelli To: Maxime Bizon Subject: Re: [PATCH 10/10] bcm63xx: clarify meaning of the magical value in ehci-bcm63xx.c Date: Mon, 1 Jun 2009 20:12:41 +0200 User-Agent: KMail/1.9.9 Cc: linux-mips@linux-mips.org, Ralf Baechle References: <1243876918-9905-1-git-send-email-mbizon@freebox.fr> <1243876918-9905-11-git-send-email-mbizon@freebox.fr> In-Reply-To: <1243876918-9905-11-git-send-email-mbizon@freebox.fr> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8BIT Content-Disposition: inline Message-Id: <200906012012.42372.florian@openwrt.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23151 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips Le Monday 01 June 2009 19:21:58 Maxime Bizon, vous avez écrit : > USB maintainer asked for clarification of the magic value used during > USB init. Be clear about the source of it. > > Signed-off-by: Maxime Bizon Acked-by: Florian Fainelli > --- > drivers/usb/host/ehci-bcm63xx.c | 4 +++- > 1 files changed, 3 insertions(+), 1 deletions(-) > > diff --git a/drivers/usb/host/ehci-bcm63xx.c > b/drivers/usb/host/ehci-bcm63xx.c index 8a62c0a..5a03fdd 100644 > --- a/drivers/usb/host/ehci-bcm63xx.c > +++ b/drivers/usb/host/ehci-bcm63xx.c > @@ -78,7 +78,9 @@ static int __devinit ehci_hcd_bcm63xx_drv_probe(struct > platform_device *pdev) reg |= USBH_PRIV_SWAP_EHCI_ENDN_MASK; > bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SWAP_REG); > > - /* don't ask... */ > + /* the magic value comes for the original vendor BSP and is > + * needed for USB to work. Datasheet does not help, so the > + * magic value is used as-is. */ > bcm_rset_writel(RSET_USBH_PRIV, 0x1c0020, USBH_PRIV_TEST_REG); > > hcd = usb_create_hcd(&ehci_bcm63xx_hc_driver, &pdev->dev, "bcm63xx"); -- Best regards, Florian Fainelli Email : florian@openwrt.org http://openwrt.org ------------------------------- From f.fainelli@gmail.com Mon Jun 1 19:17:14 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 01 Jun 2009 19:17:20 +0100 (WEST) Received: from mail-ew0-f219.google.com ([209.85.219.219]:54294 "EHLO mail-ew0-f219.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20024926AbZFASRO (ORCPT ); Mon, 1 Jun 2009 19:17:14 +0100 Received: by ewy19 with SMTP id 19so8328102ewy.0 for ; Mon, 01 Jun 2009 11:17:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:sender:from:date:subject :mime-version:x-uid:x-length:to:content-type :content-transfer-encoding:content-disposition:message-id; bh=ID63Bxg0Yk7e/DX285HpTAImN6lYsUpQP4kfALEv6Fo=; b=R9fDWKIW18dBZ+Tr6OSWfBb4fymF/JEYShXqRBBaLGEWD13ERFec5rAhWeVBY5fcst HLOE8y+q+SgSUpMSqFJ5VE5mGZTHghcMar4mNn6Yq5FKbPpnewLtJ61u311CTn3K78a0 e1Am9zyMOsVO3KGthYISynRO+aQoAHMLhqK0I= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:from:date:subject:mime-version:x-uid:x-length:to :content-type:content-transfer-encoding:content-disposition :message-id; b=VArJ6dkEOYRMWKCU817kS0RmkI4uaOdzQkZGCM+1Ng6Br0Y5WuLmsaKf5cD1gcPD0F 3OPkp4B3SwfR728SWDlUYPLtSZqWb3WFpJQ9VTMidqmPb0AYWAKK6lYNboA5ol/25Wld Z2szZ2VQa3EgwMPNqi6Czfr+7Bfm+2ly7YZMg= Received: by 10.210.81.10 with SMTP id e10mr4400190ebb.39.1243880228580; Mon, 01 Jun 2009 11:17:08 -0700 (PDT) Received: from florian (207.130.195-77.rev.gaoland.net [77.195.130.207]) by mx.google.com with ESMTPS id 23sm384728eya.29.2009.06.01.11.17.06 (version=TLSv1/SSLv3 cipher=RC4-MD5); Mon, 01 Jun 2009 11:17:07 -0700 (PDT) From: Florian Fainelli Date: Mon, 1 Jun 2009 20:17:04 +0200 Subject: [PATCH 1/3] bcm63xx: fix printed CPU frequency MIME-Version: 1.0 X-UID: 193 X-Length: 1411 To: Ralf Baechle , linux-mips@linux-mips.org, Maxime Bizon Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Content-Disposition: inline Message-Id: <200906012017.05008.florian@openwrt.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23152 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips This patch fixes the CPU frequency printing which is printed in Hz and not MHz. Signed-off-by: Florian Fainelli --- diff --git a/arch/mips/bcm63xx/cpu.c b/arch/mips/bcm63xx/cpu.c index 0a403dd..9d6cfce 100644 --- a/arch/mips/bcm63xx/cpu.c +++ b/arch/mips/bcm63xx/cpu.c @@ -239,7 +239,7 @@ void __init bcm63xx_cpu_init(void) printk(KERN_INFO "Detected Broadcom 0x%04x CPU revision %02x\n", bcm63xx_cpu_id, bcm63xx_cpu_rev); printk(KERN_INFO "CPU frequency is %u MHz\n", - bcm63xx_cpu_freq); + bcm63xx_cpu_freq / 1000000); printk(KERN_INFO "%uMB of RAM installed\n", bcm63xx_memory_size >> 20); } From f.fainelli@gmail.com Mon Jun 1 19:18:23 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 01 Jun 2009 19:18:30 +0100 (WEST) Received: from ey-out-1920.google.com ([74.125.78.147]:1830 "EHLO ey-out-1920.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20024974AbZFASSX (ORCPT ); Mon, 1 Jun 2009 19:18:23 +0100 Received: by ey-out-1920.google.com with SMTP id 4so447731eyg.54 for ; Mon, 01 Jun 2009 11:18:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:sender:from:date:subject :mime-version:x-uid:x-length:to:content-type :content-transfer-encoding:content-disposition:message-id; bh=m56wAg5f+dgcT5ijhh4gbrRbAEvtw19GKvR07MrEU4k=; b=kkhR1CTGCmcCpPbS7QkwHDsPqeXdmUl9LDaM4t/apgSJFk7BT772IKx9BAGj60Qmdw vBdZBtX84ZV+izHXqjCzo9x8tuPuwUW+Kzyhv0q3Rw9QfbdYvBaLx0y2T6ZJ7HjLPgVc r4NhyFFTcahHqDfsc5egozjw8WiQ4Dt9YE9bE= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:from:date:subject:mime-version:x-uid:x-length:to :content-type:content-transfer-encoding:content-disposition :message-id; b=MIXIhn/MdxFKfD0LH+bC76te8iNa3YT0ELaW6cBkFUHhE30uAINt7CQl45htUNhWUc IdAC8Sn+Uic79se+L7yNlcuv67hc6khfkFaNfPNoWuHMFDXX7ZRuZOYmaIvqLWof4iUL 0kxFlhnHtyolmT4pm2nv8i1T1GCwRjv53en7g= Received: by 10.210.39.2 with SMTP id m2mr1474225ebm.82.1243880302954; Mon, 01 Jun 2009 11:18:22 -0700 (PDT) Received: from florian (207.130.195-77.rev.gaoland.net [77.195.130.207]) by mx.google.com with ESMTPS id 28sm62967eyg.44.2009.06.01.11.18.22 (version=TLSv1/SSLv3 cipher=RC4-MD5); Mon, 01 Jun 2009 11:18:22 -0700 (PDT) From: Florian Fainelli Date: Mon, 1 Jun 2009 20:18:20 +0200 Subject: [PATCH 3/3] bcm63xx: early registering of gpiochip MIME-Version: 1.0 X-UID: 195 X-Length: 2651 To: Ralf Baechle , linux-mips@linux-mips.org, Maxime Bizon Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Content-Disposition: inline Message-Id: <200906012018.20972.florian@openwrt.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23153 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips This patch makes the gpiochip be registered earlier in the prom code. This allows GPIO-based board detection to be made earlier. Tested-by: Maxime Bizon Signed-off-by: Florian Fainelli --- diff --git a/arch/mips/bcm63xx/gpio.c b/arch/mips/bcm63xx/gpio.c index b78d3fd..997fcaa 100644 --- a/arch/mips/bcm63xx/gpio.c +++ b/arch/mips/bcm63xx/gpio.c @@ -120,9 +120,8 @@ static struct gpio_chip bcm63xx_gpio_chip = { .ngpio = BCM63XX_GPIO_COUNT, }; -static int __init bcm63xx_gpio_init(void) +int __init bcm63xx_gpio_init(void) { printk(KERN_INFO "registering %d GPIOs\n", BCM63XX_GPIO_COUNT); return gpiochip_add(&bcm63xx_gpio_chip); } -arch_initcall(bcm63xx_gpio_init); diff --git a/arch/mips/bcm63xx/prom.c b/arch/mips/bcm63xx/prom.c index d97ceed..1e5bb15 100644 --- a/arch/mips/bcm63xx/prom.c +++ b/arch/mips/bcm63xx/prom.c @@ -13,6 +13,7 @@ #include #include #include +#include void __init prom_init(void) { @@ -40,6 +41,9 @@ void __init prom_init(void) /* do low level board init */ board_prom_init(); + + /* early register gpio */ + bcm63xx_gpio_init(); } void __init prom_free_prom_memory(void) diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h index 72cee75..8bc812f 100644 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h @@ -1,6 +1,8 @@ #ifndef BCM63XX_GPIO_H #define BCM63XX_GPIO_H +int __init bcm63xx_gpio_init(void); + /* all helpers will BUG() if gpio count is >= 37. */ #define BCM63XX_GPIO_COUNT 37 From David.Daney@caviumnetworks.com Mon Jun 1 19:19:41 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 01 Jun 2009 19:19:48 +0100 (WEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:30461 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20023445AbZFASTl (ORCPT ); Mon, 1 Jun 2009 19:19:41 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,2,2,3503) id ; Mon, 01 Jun 2009 14:13:37 -0400 Received: from dd1.caveonetworks.com ([64.169.86.201]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Mon, 1 Jun 2009 11:13:29 -0700 Message-ID: <4A241A49.1020706@caviumnetworks.com> Date: Mon, 01 Jun 2009 11:13:29 -0700 From: David Daney User-Agent: Thunderbird 2.0.0.21 (X11/20090320) MIME-Version: 1.0 To: Florian Fainelli , Ralf Baechle CC: linux-mips@linux-mips.org Subject: Re: [PATCH 4/9] mips: deal with larger physical offsets References: <200906011359.47216.florian@openwrt.org> In-Reply-To: <200906011359.47216.florian@openwrt.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 01 Jun 2009 18:13:29.0476 (UTC) FILETIME=[AA530C40:01C9E2E4] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23154 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Florian Fainelli wrote: > TI AR7 has larger physical offsets than other MIPS-based > systems. A long jump to the target is required instead of > a short jump like on other systems. > > Signed-off-by: Eugene Konev > Signed-off-by: Florian Fainelli > --- > diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c > index e83da17..44f7141 100644 > --- a/arch/mips/kernel/traps.c > +++ b/arch/mips/kernel/traps.c > @@ -1256,9 +1256,22 @@ void *set_except_vector(int n, void *addr) > > exception_handlers[n] = handler; > if (n == 0 && cpu_has_divec) { > - *(u32 *)(ebase + 0x200) = 0x08000000 | > - (0x03ffffff & (handler >> 2)); > - local_flush_icache_range(ebase + 0x200, ebase + 0x204); > + if ((handler ^ (ebase + 4)) & 0xfc000000) { > + /* lui k0, 0x0000 */ > + *(u32 *)(ebase + 0x200) = 0x3c1a0000 | (handler >> 16); > + /* ori k0, 0x0000 */ > + *(u32 *)(ebase + 0x204) = > + 0x375a0000 | (handler & 0xffff); > + /* jr k0 */ > + *(u32 *)(ebase + 0x208) = 0x03400008; > + /* nop */ > + *(u32 *)(ebase + 0x20C) = 0x00000000; > + local_flush_icache_range(ebase + 0x200, ebase + 0x210); > + } else { > + *(u32 *)(ebase + 0x200) = > + 0x08000000 | (0x03ffffff & (handler >> 2)); > + local_flush_icache_range(ebase + 0x200, ebase + 0x204); > + } > } > return (void *)old_handler; > } > I had to do a similar change for my mapped kernel patch. However in mine, I used uasm. I wonder if the extra memory occupied by uasm is too steep a penalty to pay for the ability to use it outside of __init code. If not, we should move uasm out of __init and use it instead of this manual assembly. David Daney From f.fainelli@gmail.com Mon Jun 1 19:22:29 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 01 Jun 2009 19:22:36 +0100 (WEST) Received: from mail-ew0-f219.google.com ([209.85.219.219]:49475 "EHLO mail-ew0-f219.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20023557AbZFASW3 (ORCPT ); Mon, 1 Jun 2009 19:22:29 +0100 Received: by ewy19 with SMTP id 19so8332065ewy.0 for ; Mon, 01 Jun 2009 11:22:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:sender:from:date:subject :mime-version:x-uid:x-length:to:content-type :content-transfer-encoding:content-disposition:message-id; bh=ygdtgisMu2Uhymmguzq4woplwKIJcrdb3dOJHTkJ/uc=; b=m0kFGW1ffAwxGzjIv80z8g5MjVnfC9k6ud8fc5NFcDlyACuqe6Ri2HcBx9vuLnmAaP x3i69TtiwNvrxOuBe81iBDp1gzYtPzmsRhPShgCAI8n1sH7MV4D71j3jIj2zhQkvtGQe UA57SlxJ8UEpAmBYFPA7qNwTCd4JBbR3B9j9k= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:from:date:subject:mime-version:x-uid:x-length:to :content-type:content-transfer-encoding:content-disposition :message-id; b=Xx6s4su/8QXoWM696npMxQI/LnSQpPUtVXSl/uDru5ZO9lrGwMaYXZaxKS1Ekyrc7m XnsOYHn5BYaOgimp8I+Tu8sFG3+1oNzohbKd33bWqf0COv6F0i8B3MoUBB3UohI2iH0I n2UwIzihM5zQTkaD1qOiF9hbUeazLEeaI3S2o= Received: by 10.210.29.9 with SMTP id c9mr4372192ebc.48.1243880543484; Mon, 01 Jun 2009 11:22:23 -0700 (PDT) Received: from florian (207.130.195-77.rev.gaoland.net [77.195.130.207]) by mx.google.com with ESMTPS id 7sm36386eyg.47.2009.06.01.11.22.22 (version=TLSv1/SSLv3 cipher=RC4-MD5); Mon, 01 Jun 2009 11:22:22 -0700 (PDT) From: Florian Fainelli Date: Mon, 1 Jun 2009 20:22:20 +0200 Subject: [PATCH 2/3 v2] bcm63xx: select SSB since we are using ssb_arch_set_fallback_sprom MIME-Version: 1.0 X-UID: 211 X-Length: 1386 To: Ralf Baechle , linux-mips@linux-mips.org, Maxime Bizon Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Content-Disposition: inline Message-Id: <200906012022.20804.florian@openwrt.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23155 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips This patch makes the BCM963xx boards select SSB since we unconditionnaly use ssb_arch_set_fallback_sprom. Without this linking would fail with an undefined reference. Changes from v1: - this only applies to BCM963xx boards and not 63xx as a whole Signed-off-by: Florian Fainelli --- diff --git a/arch/mips/bcm63xx/boards/Kconfig b/arch/mips/bcm63xx/boards/Kconfig index da5eeaa..c6aed33 100644 --- a/arch/mips/bcm63xx/boards/Kconfig +++ b/arch/mips/bcm63xx/boards/Kconfig @@ -5,6 +5,7 @@ choice config BOARD_BCM963XX bool "Generic Broadcom 963xx boards" + select SSB help endchoice From f.fainelli@gmail.com Mon Jun 1 19:23:44 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 01 Jun 2009 19:23:50 +0100 (WEST) Received: from mail-ew0-f219.google.com ([209.85.219.219]:33395 "EHLO mail-ew0-f219.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20023379AbZFASXo convert rfc822-to-8bit (ORCPT ); Mon, 1 Jun 2009 19:23:44 +0100 Received: by ewy19 with SMTP id 19so8333057ewy.0 for ; Mon, 01 Jun 2009 11:23:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:sender:from:to:subject:date :user-agent:cc:references:in-reply-to:mime-version:content-type :content-transfer-encoding:content-disposition:message-id; bh=SX0fM4FPl5tEMx6lKsOhOmzPDHAJ6r1ZnG7RExRA1QM=; b=XFmtLHCPRqUIQbe9+IwMZz5RwEJqOQHARZQJtoh1cbxxVJaYyTFUMq0hoh3n2Z48m2 oFb1ug58Lt/WJ2HB8qPwdpy8+mWeITdK6yofwE0P0XfJd2b2SgIt9Pvpgmjp3e8VtvBJ EDeKLJUHBLdNfz9tHngcmsyZXO5r8xSuJqJIQ= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:from:to:subject:date:user-agent:cc:references:in-reply-to :mime-version:content-type:content-transfer-encoding :content-disposition:message-id; b=VA4nnGxOl9Bnelh9KP89LGR3g9d9YMyuZ4uPnFrHmcndxaiSY0maQVX9LjBK88Pm1k 8y4b/+DMIyrHlg21alpw0CU0YnmtSQexdxqMJVPlq78iaGw8RYp44ZtBc+XBx5nTkU5A CfRxHZ3rPbOmcbh+aMh/Tm9yTe7uKwCeLyKx0= Received: by 10.210.91.17 with SMTP id o17mr6697619ebb.71.1243880618162; Mon, 01 Jun 2009 11:23:38 -0700 (PDT) Received: from florian (207.130.195-77.rev.gaoland.net [77.195.130.207]) by mx.google.com with ESMTPS id 23sm391782eya.29.2009.06.01.11.23.37 (version=TLSv1/SSLv3 cipher=RC4-MD5); Mon, 01 Jun 2009 11:23:37 -0700 (PDT) From: Florian Fainelli To: Ralf Baechle Subject: Re: [PATCH 2/3] bcm63xx: select SSB since we are using ssb_arch_set_fallback_sprom Date: Mon, 1 Jun 2009 20:23:35 +0200 User-Agent: KMail/1.9.9 Cc: linux-mips@linux-mips.org, Maxime Bizon References: <200906012017.48965.florian@openwrt.org> In-Reply-To: <200906012017.48965.florian@openwrt.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8BIT Content-Disposition: inline Message-Id: <200906012023.36068.florian@openwrt.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23156 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips Le Monday 01 June 2009 20:17:48 Florian Fainelli, vous avez écrit : > This patch makes BCM63XX select SSB since we unconditionnaly > use ssb_arch_set_fallback_sprom. Without this linking would > fail with an undefined reference. > > Signed-off-by: Florian Fainelli > --- > diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig > index 05ee268..e1f0917 100644 > --- a/arch/mips/Kconfig > +++ b/arch/mips/Kconfig > @@ -72,6 +72,7 @@ config BCM63XX > select SYS_HAS_EARLY_PRINTK > select SWAP_IO_SPACE > select ARCH_REQUIRE_GPIOLIB > + select SSB > help > Support for BCM63XX based boards Ralf, Please find an updated version below. As Maxime pointed me out, this only applies to BCM963xx boards, not BCM63xx as a whole. Thanks ! -- Best regards, Florian Fainelli Email : florian@openwrt.org http://openwrt.org ------------------------------- From f.fainelli@gmail.com Mon Jun 1 19:25:25 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 01 Jun 2009 19:25:32 +0100 (WEST) Received: from mail-ew0-f219.google.com ([209.85.219.219]:59021 "EHLO mail-ew0-f219.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20024088AbZFASZZ (ORCPT ); Mon, 1 Jun 2009 19:25:25 +0100 Received: by ewy19 with SMTP id 19so8334607ewy.0 for ; Mon, 01 Jun 2009 11:25:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:sender:from:date:subject :mime-version:x-uid:x-length:to:content-type :content-transfer-encoding:content-disposition:message-id; bh=G3jVgWeU9aOqkZ3pEG3Agj8r/eY3DEq7UHa5ahaACLM=; b=P7AgCDyupid6il6K8h70VIFpfJj/xMX+dpm/5q/FZzKoQdPB46Xjw7v2IzyN/fBmGi BKzjq9zlKQxPNsMc21dn5+tAesI9N7keo867Er4dIzN5BLl5ut0SG1xQo+aHMu3WHyJS rpRhp/z9TrI2n568dsj3X56yWZJ/i+sDEjIdE= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:from:date:subject:mime-version:x-uid:x-length:to :content-type:content-transfer-encoding:content-disposition :message-id; b=UcuRrLxWyCDfVKk3giCaP6zSmdFmHuLD0mWQyCh9Nxz7votq69+04GcBaO+0QB+pNQ vo8K9YAthtCv3SDGwQ6mphx3mlHNQ+SfVmxHDNq090SRNT7XnwSaHfjGYraglEfl/cym 61+IPD7DpqPpPEAkdKQyDEJeKGZUZMRPRZHFo= Received: by 10.210.19.7 with SMTP id 7mr2228805ebs.57.1243880270839; Mon, 01 Jun 2009 11:17:50 -0700 (PDT) Received: from florian (207.130.195-77.rev.gaoland.net [77.195.130.207]) by mx.google.com with ESMTPS id 10sm235818eyz.21.2009.06.01.11.17.50 (version=TLSv1/SSLv3 cipher=RC4-MD5); Mon, 01 Jun 2009 11:17:50 -0700 (PDT) From: Florian Fainelli Date: Mon, 1 Jun 2009 20:17:48 +0200 Subject: [PATCH 2/3] bcm63xx: select SSB since we are using ssb_arch_set_fallback_sprom MIME-Version: 1.0 X-UID: 194 X-Length: 1343 To: Ralf Baechle , linux-mips@linux-mips.org, Maxime Bizon Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Content-Disposition: inline Message-Id: <200906012017.48965.florian@openwrt.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23157 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips This patch makes BCM63XX select SSB since we unconditionnaly use ssb_arch_set_fallback_sprom. Without this linking would fail with an undefined reference. Signed-off-by: Florian Fainelli --- diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 05ee268..e1f0917 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -72,6 +72,7 @@ config BCM63XX select SYS_HAS_EARLY_PRINTK select SWAP_IO_SPACE select ARCH_REQUIRE_GPIOLIB + select SSB help Support for BCM63XX based boards From mbizon@freebox.fr Mon Jun 1 19:37:05 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 01 Jun 2009 19:37:11 +0100 (WEST) Received: from smtp5-g21.free.fr ([212.27.42.5]:50003 "EHLO smtp5-g21.free.fr" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20023378AbZFAShF (ORCPT ); Mon, 1 Jun 2009 19:37:05 +0100 Received: from smtp5-g21.free.fr (localhost [127.0.0.1]) by smtp5-g21.free.fr (Postfix) with ESMTP id 95008D4814D; Mon, 1 Jun 2009 20:36:58 +0200 (CEST) Received: from [213.228.1.107] (sakura.staff.proxad.net [213.228.1.107]) by smtp5-g21.free.fr (Postfix) with ESMTP id A1FF4D48183; Mon, 1 Jun 2009 20:36:56 +0200 (CEST) Subject: [PATCH 10/10 (v2)] bcm63xx: clarify meaning of the magical value in ehci-bcm63xx.c From: Maxime Bizon Reply-To: mbizon@freebox.fr To: Sergei Shtylyov Cc: linux-mips@linux-mips.org, Ralf Baechle , Florian Fainelli In-Reply-To: <4A2416A4.4070902@ru.mvista.com> References: <1243876918-9905-1-git-send-email-mbizon@freebox.fr> <1243876918-9905-11-git-send-email-mbizon@freebox.fr> <4A2416A4.4070902@ru.mvista.com> Content-Type: text/plain Organization: Freebox Date: Mon, 01 Jun 2009 20:36:56 +0200 Message-Id: <1243881416.7410.107.camel@sakura.staff.proxad.net> Mime-Version: 1.0 X-Mailer: Evolution 2.26.1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23158 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mbizon@freebox.fr Precedence: bulk X-list: linux-mips USB maintainer asked for clarification of the magic value used during USB init. Be clear about the source of it. Signed-off-by: Maxime Bizon --- drivers/usb/host/ehci-bcm63xx.c | 6 +++++- 1 files changed, 5 insertions(+), 1 deletions(-) diff --git a/drivers/usb/host/ehci-bcm63xx.c b/drivers/usb/host/ehci-bcm63xx.c index 8a62c0a..c2b3e7f 100644 --- a/drivers/usb/host/ehci-bcm63xx.c +++ b/drivers/usb/host/ehci-bcm63xx.c @@ -78,7 +78,11 @@ static int __devinit ehci_hcd_bcm63xx_drv_probe(struct platform_device *pdev) reg |= USBH_PRIV_SWAP_EHCI_ENDN_MASK; bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SWAP_REG); - /* don't ask... */ + /* + * The magic value comes for the original vendor BSP and is + * needed for USB to work. Datasheet does not help, so the + * magic value is used as-is. + */ bcm_rset_writel(RSET_USBH_PRIV, 0x1c0020, USBH_PRIV_TEST_REG); hcd = usb_create_hcd(&ehci_bcm63xx_hc_driver, &pdev->dev, "bcm63xx"); -- 1.6.0.4 From mbizon@freebox.fr Mon Jun 1 19:38:21 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 01 Jun 2009 19:38:28 +0100 (WEST) Received: from smtp6-g21.free.fr ([212.27.42.6]:43854 "EHLO smtp6-g21.free.fr" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20023398AbZFASiV (ORCPT ); Mon, 1 Jun 2009 19:38:21 +0100 Received: from smtp6-g21.free.fr (localhost [127.0.0.1]) by smtp6-g21.free.fr (Postfix) with ESMTP id CA3F9E0807A; Mon, 1 Jun 2009 20:38:16 +0200 (CEST) Received: from [213.228.1.107] (sakura.staff.proxad.net [213.228.1.107]) by smtp6-g21.free.fr (Postfix) with ESMTP id F243DE080FB; Mon, 1 Jun 2009 20:38:13 +0200 (CEST) Subject: [PATCH 07/10 (v2)] bcm63xx: clarify meaning of the magical value in ohci-bcm63xx.c From: Maxime Bizon Reply-To: mbizon@freebox.fr To: linux-mips@linux-mips.org Cc: Ralf Baechle , Florian Fainelli In-Reply-To: <1243876918-9905-8-git-send-email-mbizon@freebox.fr> References: <1243876918-9905-1-git-send-email-mbizon@freebox.fr> <1243876918-9905-8-git-send-email-mbizon@freebox.fr> Content-Type: text/plain Organization: Freebox Date: Mon, 01 Jun 2009 20:38:13 +0200 Message-Id: <1243881493.7410.109.camel@sakura.staff.proxad.net> Mime-Version: 1.0 X-Mailer: Evolution 2.26.1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23159 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mbizon@freebox.fr Precedence: bulk X-list: linux-mips USB maintainer asked for clarification of the magic value used during USB init. Be clear about the source of it. Signed-off-by: Maxime Bizon --- drivers/usb/host/ohci-bcm63xx.c | 6 +++++- 1 files changed, 5 insertions(+), 1 deletions(-) diff --git a/drivers/usb/host/ohci-bcm63xx.c b/drivers/usb/host/ohci-bcm63xx.c index d48c8ac..668808e 100644 --- a/drivers/usb/host/ohci-bcm63xx.c +++ b/drivers/usb/host/ohci-bcm63xx.c @@ -85,7 +85,11 @@ static int __devinit ohci_hcd_bcm63xx_drv_probe(struct platform_device *pdev) reg &= ~USBH_PRIV_SWAP_OHCI_ENDN_MASK; reg |= USBH_PRIV_SWAP_OHCI_DATA_MASK; bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SWAP_REG); - /* don't ask... */ + /* + * The magic value comes for the original vendor BSP + * and is needed for USB to work. Datasheet does not + * help, so the magic value is used as-is. + */ bcm_rset_writel(RSET_USBH_PRIV, 0x1c0020, USBH_PRIV_TEST_REG); } else return 0; -- 1.6.0.4 From mmason@upwardaccess.com Mon Jun 1 19:54:30 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 01 Jun 2009 19:54:40 +0100 (WEST) Received: from mail.upwardaccess.com ([70.89.180.121]:1252 "EHLO upwardaccess.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20022875AbZFASya convert rfc822-to-8bit (ORCPT ); Mon, 1 Jun 2009 19:54:30 +0100 Received: from [192.168.1.18] (unverified [10.61.7.126]) by upwardaccess.com (SurgeMail 3.9e) with ESMTP id 96342-1847469 for ; Mon, 01 Jun 2009 11:54:14 -0700 Subject: Re: FW: Bigsur? From: Mark Mason To: linux-mips@linux-mips.org In-Reply-To: References: Content-Type: text/plain; charset=UTF-8 Date: Mon, 01 Jun 2009 12:03:03 -0700 Message-Id: <1243882983.3841.5.camel@hawaii.site> Mime-Version: 1.0 X-Mailer: Evolution 2.22.1.1 Content-Transfer-Encoding: 8BIT X-Originating-IP: 10.61.7.126 X-Authenticated-User: mmason@upwardaccess.com Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23160 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mmason@upwardaccess.com Precedence: bulk X-list: linux-mips On Wednesday, May 20, 2009 12:16 PM, Ralf Baechle wrote: > > For many uses that will be decent but there are still a few things out > there that don't quite work the same way on NFS that they do on other > filesystems and that tends to break some software and autoconf-like > things. I'd probably give such a config a 90% score - good for most stuff. > Unfortunately, we didn't get as many of the bigsur machines out there as I would have liked before the Sibyte product was deprecated. Perhaps over time, as space is made in the labs for new projects, more of the 1250 and 1480 boards will become available. Mark From herbert@gondor.apana.org.au Tue Jun 2 04:53:19 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 02 Jun 2009 04:53:24 +0100 (WEST) Received: from rhun.apana.org.au ([64.62.148.172]:54673 "EHLO arnor.apana.org.au" rhost-flags-OK-OK-OK-FAIL) by ftp.linux-mips.org with ESMTP id S20021356AbZFBDxT (ORCPT ); Tue, 2 Jun 2009 04:53:19 +0100 Received: from gondolin.me.apana.org.au ([192.168.0.6]) by arnor.apana.org.au with esmtp (Exim 4.63 #1 (Debian)) id 1MBL3m-0001dN-2L; Tue, 02 Jun 2009 13:53:10 +1000 Received: from herbert by gondolin.me.apana.org.au with local (Exim 4.69) (envelope-from ) id 1MBL3f-000605-Du; Tue, 02 Jun 2009 13:53:03 +1000 Date: Tue, 2 Jun 2009 13:53:03 +1000 From: Herbert Xu To: Atsushi Nemoto Cc: akpm@linux-foundation.org, linux-mips@linux-mips.org, ralf@linux-mips.org, linux-kernel@vger.kernel.org, mpm@selenic.com Subject: Re: [PATCH] hwrng: Add TX4939 RNG driver Message-ID: <20090602035303.GC22831@gondor.apana.org.au> References: <1243350141-883-1-git-send-email-anemo@mba.ocn.ne.jp> <20090529162907.9cb1bba2.akpm@linux-foundation.org> <20090601.014517.169682203.anemo@mba.ocn.ne.jp> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20090601.014517.169682203.anemo@mba.ocn.ne.jp> User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23161 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: herbert@gondor.apana.org.au Precedence: bulk X-list: linux-mips On Mon, Jun 01, 2009 at 01:45:17AM +0900, Atsushi Nemoto wrote: > > >From the datasheet: > > The quality of the random numbers generated immediately after > reset can be insufficient. Therefore, do not use random > numbers obtained from the first and second generations; use > the ones from the third or subsequent generation. > > I will put this comment in the driver. OK, I think you've resolved all my concerns. Please cc me when you resubmit. Thanks! -- Visit Openswan at http://www.openswan.org/ Email: Herbert Xu ~{PmV>HI~} Home Page: http://gondor.apana.org.au/~herbert/ PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt From akpm@linux-foundation.org Tue Jun 2 05:50:45 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 02 Jun 2009 05:50:52 +0100 (WEST) Received: from smtp1.linux-foundation.org ([140.211.169.13]:35266 "EHLO smtp1.linux-foundation.org" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20021466AbZFBEup (ORCPT ); Tue, 2 Jun 2009 05:50:45 +0100 Received: from imap1.linux-foundation.org (imap1.linux-foundation.org [140.211.169.55]) by smtp1.linux-foundation.org (8.14.2/8.13.5/Debian-3ubuntu1.1) with ESMTP id n524oYtt008736 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Mon, 1 Jun 2009 21:50:35 -0700 Received: from y.localdomain (localhost [127.0.0.1]) by imap1.linux-foundation.org (8.13.5.20060308/8.13.5/Debian-3ubuntu1.1) with SMTP id n524oYqJ020206; Mon, 1 Jun 2009 21:50:34 -0700 Date: Mon, 1 Jun 2009 21:50:34 -0700 From: Andrew Morton To: Florian Fainelli Cc: linux-kernel@vger.kernel.org, Takashi Iwai , linux-mips@linux-mips.org, Ralf Baechle , Ingo Molnar Subject: Re: [PATCH 1/9] kernel: export sound/core/pcm_timer.c gcd implementation Message-Id: <20090601215034.7352ddca.akpm@linux-foundation.org> In-Reply-To: <200906011357.09966.florian@openwrt.org> References: <200906011357.09966.florian@openwrt.org> X-Mailer: Sylpheed 2.4.8 (GTK+ 2.12.5; x86_64-redhat-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-MIMEDefang-Filter: lf$Revision: 1.188 $ X-Scanned-By: MIMEDefang 2.63 on 140.211.169.13 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23162 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: akpm@linux-foundation.org Precedence: bulk X-list: linux-mips On Mon, 1 Jun 2009 13:57:09 +0200 Florian Fainelli wrote: > This patch exports the gcd implementation from > sound/core/pcm_timer.c into include/linux/kernel.h. > AR7 uses it in its clock routines. > > ... > > diff --git a/include/linux/kernel.h b/include/linux/kernel.h > index 883cd44..878a27a 100644 > --- a/include/linux/kernel.h > +++ b/include/linux/kernel.h > @@ -147,6 +147,22 @@ extern int _cond_resched(void); > (__x < 0) ? -__x : __x; \ > }) > > +/* Greatest common divisor */ > +static inline unsigned long gcd(unsigned long a, unsigned long b) > +{ > + unsigned long r; > + if (a < b) { > + r = a; > + a = b; > + b = r; > + } > + while ((r = a % b) != 0) { > + a = b; > + b = r; > + } > + return b; > +} a) the name's a bit sucky. Is there some convention for this name? b) It looks too large to be inlined. lib/gdc.c? b) there's an implementation of gcd() in net/netfilter/ipvs/ip_vs_wrr.c. I expect that this patch broke the build. From geert.uytterhoeven@gmail.com Tue Jun 2 08:15:36 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 02 Jun 2009 08:15:44 +0100 (WEST) Received: from mail-bw0-f177.google.com ([209.85.218.177]:58833 "EHLO mail-bw0-f177.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20021816AbZFBHPg convert rfc822-to-8bit (ORCPT ); Tue, 2 Jun 2009 08:15:36 +0100 Received: by bwz25 with SMTP id 25so8232606bwz.0 for ; Tue, 02 Jun 2009 00:15:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:sender:received:in-reply-to :references:date:x-google-sender-auth:message-id:subject:from:to:cc :content-type:content-transfer-encoding; bh=1fL9dsrN1EreTbxOEv2jWBhBfLcB8qCh89f/ylabOik=; b=FsEn4F4ANnRAf2oOPeAcMgJdk2YmtQBzpii7eLIwF1anJebu7V3zVu8SUoS7DliBmG 3S8rH8oN+MX4EnN24C5N6oTwylpMHqyCGrTeWEwaKCAu+6gd4JIIWe1lp93M5WNiMYuJ 5OyOGf7uxSA/1EW0mL0dOt/vRhcoVLP6vtgg0= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:sender:in-reply-to:references:date :x-google-sender-auth:message-id:subject:from:to:cc:content-type :content-transfer-encoding; b=sDCsbwn4Kph6h1apaJwAfXzH+zuAhvLhwFNxIcL6O6kPdBlX/pnWnVyV1PH2mHpvPT NFRUC9U8Zp00qE2Qgw4Fa2tzoLsElLS4XHAcXIkkFmwlUeyuZpj57aOQleplnk9Y2i6Y EPOC8GtOFq/CWr1cPdKe2YbXaNN7xtOZgEozM= MIME-Version: 1.0 Received: by 10.204.115.67 with SMTP id h3mr6488699bkq.173.1243926929922; Tue, 02 Jun 2009 00:15:29 -0700 (PDT) In-Reply-To: <20090601215034.7352ddca.akpm@linux-foundation.org> References: <200906011357.09966.florian@openwrt.org> <20090601215034.7352ddca.akpm@linux-foundation.org> Date: Tue, 2 Jun 2009 09:15:29 +0200 X-Google-Sender-Auth: 26a2fe37e5854ca9 Message-ID: <10f740e80906020015t2d63fdadmaa1fa6bc204ec33a@mail.gmail.com> Subject: Re: [PATCH 1/9] kernel: export sound/core/pcm_timer.c gcd implementation From: Geert Uytterhoeven To: Andrew Morton Cc: Florian Fainelli , linux-kernel@vger.kernel.org, Takashi Iwai , linux-mips@linux-mips.org, Ralf Baechle , Ingo Molnar Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8BIT Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23163 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: geert@linux-m68k.org Precedence: bulk X-list: linux-mips On Tue, Jun 2, 2009 at 06:50, Andrew Morton wrote: > On Mon, 1 Jun 2009 13:57:09 +0200 Florian Fainelli wrote: > >> This patch exports the gcd implementation from >> sound/core/pcm_timer.c into include/linux/kernel.h. >> AR7 uses it in its clock routines. >> >> ... >> >> diff --git a/include/linux/kernel.h b/include/linux/kernel.h >> index 883cd44..878a27a 100644 >> --- a/include/linux/kernel.h >> +++ b/include/linux/kernel.h >> @@ -147,6 +147,22 @@ extern int _cond_resched(void); >>               (__x < 0) ? -__x : __x;         \ >>       }) >> >> +/* Greatest common divisor */ >> +static inline unsigned long gcd(unsigned long a, unsigned long b) >> +{ >> +        unsigned long r; >> +        if (a < b) { >> +                r = a; >> +                a = b; >> +                b = r; >> +        } >> +        while ((r = a % b) != 0) { >> +                a = b; >> +                b = r; >> +        } >> +        return b; >> +} > > a) the name's a bit sucky.   Is there some convention for this name? Well, `gcd' is a quite common acronym, probably almost as well known as `min' and `max'... Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds From f.fainelli@gmail.com Tue Jun 2 08:19:33 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 02 Jun 2009 08:19:40 +0100 (WEST) Received: from mail-fx0-f175.google.com ([209.85.220.175]:41929 "EHLO mail-fx0-f175.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20021816AbZFBHTd (ORCPT ); Tue, 2 Jun 2009 08:19:33 +0100 Received: by fxm23 with SMTP id 23so8318038fxm.0 for ; Tue, 02 Jun 2009 00:19:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:sender:from:to:subject:date :user-agent:cc:references:in-reply-to:mime-version:content-type :content-transfer-encoding:message-id; bh=/LCqDd5Rt0h4z/FKRGfnjk/Sym7dJ9/mKrZmXxtfK7s=; b=Il6BFFc0LBR428TXHueYldB47g5IxSJvFSqkOhaZFQY2H8THVjaLBzlkHVI5x6/NxF 79ZUo+NV/Jr5LKmZglzvHtRK7uWyI3tpK5+ANEo+SPMccuB7QhFXu8zuL5J9v8xmxMmm eKeGhNh4r/sdI7T9I4XgJr0AgCq8pOmuVIqZ8= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:from:to:subject:date:user-agent:cc:references:in-reply-to :mime-version:content-type:content-transfer-encoding:message-id; b=eebZ8A/S+6Y00ce10Bf+LlJ4ALwLU/lBKCRLsMngpjgcfU69xy9qGEs3GUOzoT4F1V ryhTlnAMFNCbGyP2gVHf3ykTUCwBtH07NVqggelK6AkT+m0a7aLSdVPYiOjYJoL103BC tZ6tDKYTO9CTgMFcPOBOOeoGVMFMMDcyZoO+w= Received: by 10.204.71.68 with SMTP id g4mr6543167bkj.81.1243927167412; Tue, 02 Jun 2009 00:19:27 -0700 (PDT) Received: from florian.lab.openpattern.org (lab.openpattern.org [82.240.16.241]) by mx.google.com with ESMTPS id 13sm8236655fks.22.2009.06.02.00.19.26 (version=TLSv1/SSLv3 cipher=RC4-MD5); Tue, 02 Jun 2009 00:19:26 -0700 (PDT) From: Florian Fainelli To: Andrew Morton Subject: Re: [PATCH 1/9] kernel: export sound/core/pcm_timer.c gcd implementation Date: Tue, 2 Jun 2009 09:19:22 +0200 User-Agent: KMail/1.9.9 Cc: linux-kernel@vger.kernel.org, Takashi Iwai , linux-mips@linux-mips.org, Ralf Baechle , Ingo Molnar References: <200906011357.09966.florian@openwrt.org> <20090601215034.7352ddca.akpm@linux-foundation.org> In-Reply-To: <20090601215034.7352ddca.akpm@linux-foundation.org> MIME-Version: 1.0 Content-Type: multipart/signed; boundary="nextPart1733965.8q685CKkAD"; protocol="application/pgp-signature"; micalg=pgp-sha1 Content-Transfer-Encoding: 7bit Message-Id: <200906020919.25162.florian@openwrt.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23164 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips --nextPart1733965.8q685CKkAD Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Content-Disposition: inline Le Tuesday 02 June 2009 06:50:34 Andrew Morton, vous avez =E9crit=A0: > On Mon, 1 Jun 2009 13:57:09 +0200 Florian Fainelli = =20 wrote: > > This patch exports the gcd implementation from > > sound/core/pcm_timer.c into include/linux/kernel.h. > > AR7 uses it in its clock routines. > > > > ... > > > > diff --git a/include/linux/kernel.h b/include/linux/kernel.h > > index 883cd44..878a27a 100644 > > --- a/include/linux/kernel.h > > +++ b/include/linux/kernel.h > > @@ -147,6 +147,22 @@ extern int _cond_resched(void); > > (__x < 0) ? -__x : __x; \ > > }) > > > > +/* Greatest common divisor */ > > +static inline unsigned long gcd(unsigned long a, unsigned long b) > > +{ > > + unsigned long r; > > + if (a < b) { > > + r =3D a; > > + a =3D b; > > + b =3D r; > > + } > > + while ((r =3D a % b) !=3D 0) { > > + a =3D b; > > + b =3D r; > > + } > > + return b; > > +} > > a) the name's a bit sucky. Is there some convention for this name? We might want something better like greatest_common_divisor which is a bit= =20 more self-explanatory ? > > b) It looks too large to be inlined. lib/gdc.c? And its users select it in order not to increase the size of kernel.h, soun= ds=20 good. > > b) there's an implementation of gcd() in > net/netfilter/ipvs/ip_vs_wrr.c. I expect that this patch broke the > build. I did forget about this. That gcd implementation only treats the a > b case. What do you prefer, each user keeps its gcd implementation locally or we ma= ke=20 a lib/gcd.c for it ? Thanks =2D-=20 Best regards, Florian Fainelli Email : florian@openwrt.org http://openwrt.org =2D------------------------------ --nextPart1733965.8q685CKkAD Content-Type: application/pgp-signature; name=signature.asc Content-Description: This is a digitally signed message part. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.9 (GNU/Linux) iEYEABECAAYFAkok0nsACgkQlyvkmBGtjyYOSQCgl2miLsK5IoByk8+x64m8/F9s vNwAoKHAoFAWk6L5hN3P8c8uAdtmp3Gn =gSD5 -----END PGP SIGNATURE----- --nextPart1733965.8q685CKkAD-- From akpm@linux-foundation.org Tue Jun 2 08:27:04 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 02 Jun 2009 08:27:10 +0100 (WEST) Received: from smtp1.linux-foundation.org ([140.211.169.13]:43538 "EHLO smtp1.linux-foundation.org" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20021820AbZFBH1E (ORCPT ); Tue, 2 Jun 2009 08:27:04 +0100 Received: from imap1.linux-foundation.org (imap1.linux-foundation.org [140.211.169.55]) by smtp1.linux-foundation.org (8.14.2/8.13.5/Debian-3ubuntu1.1) with ESMTP id n527QlcZ004940 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Tue, 2 Jun 2009 00:26:48 -0700 Received: from y.localdomain (localhost [127.0.0.1]) by imap1.linux-foundation.org (8.13.5.20060308/8.13.5/Debian-3ubuntu1.1) with SMTP id n527QlTb004598; Tue, 2 Jun 2009 00:26:47 -0700 Date: Tue, 2 Jun 2009 00:26:16 -0700 From: Andrew Morton To: Florian Fainelli Cc: linux-kernel@vger.kernel.org, Takashi Iwai , linux-mips@linux-mips.org, Ralf Baechle , Ingo Molnar Subject: Re: [PATCH 1/9] kernel: export sound/core/pcm_timer.c gcd implementation Message-Id: <20090602002616.d5707d6b.akpm@linux-foundation.org> In-Reply-To: <200906020919.25162.florian@openwrt.org> References: <200906011357.09966.florian@openwrt.org> <20090601215034.7352ddca.akpm@linux-foundation.org> <200906020919.25162.florian@openwrt.org> X-Mailer: Sylpheed 2.4.8 (GTK+ 2.12.5; x86_64-redhat-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-MIMEDefang-Filter: lf$Revision: 1.188 $ X-Scanned-By: MIMEDefang 2.63 on 140.211.169.13 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23165 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: akpm@linux-foundation.org Precedence: bulk X-list: linux-mips On Tue, 2 Jun 2009 09:19:22 +0200 Florian Fainelli wrote: > Le Tuesday 02 June 2009 06:50:34 Andrew Morton, vous avez __crit__: > > On Mon, 1 Jun 2009 13:57:09 +0200 Florian Fainelli > wrote: > > > This patch exports the gcd implementation from > > > sound/core/pcm_timer.c into include/linux/kernel.h. > > > AR7 uses it in its clock routines. > > > > > > ... > > > > > > diff --git a/include/linux/kernel.h b/include/linux/kernel.h > > > index 883cd44..878a27a 100644 > > > --- a/include/linux/kernel.h > > > +++ b/include/linux/kernel.h > > > @@ -147,6 +147,22 @@ extern int _cond_resched(void); > > > (__x < 0) ? -__x : __x; \ > > > }) > > > > > > +/* Greatest common divisor */ > > > +static inline unsigned long gcd(unsigned long a, unsigned long b) > > > +{ > > > + unsigned long r; > > > + if (a < b) { > > > + r = a; > > > + a = b; > > > + b = r; > > > + } > > > + while ((r = a % b) != 0) { > > > + a = b; > > > + b = r; > > > + } > > > + return b; > > > +} > > > > a) the name's a bit sucky. Is there some convention for this name? > > We might want something better like greatest_common_divisor which is a bit > more self-explanatory ? Well, if gcd() is a commonly used name then let's use that. I don't personally recall seeing it used but that doesn't mean much. > > > > b) It looks too large to be inlined. lib/gdc.c? > > And its users select it in order not to increase the size of kernel.h, sounds > good. > > > > > b) there's an implementation of gcd() in > > net/netfilter/ipvs/ip_vs_wrr.c. I expect that this patch broke the > > build. > > I did forget about this. That gcd implementation only treats the a > b case. > > What do you prefer, each user keeps its gcd implementation locally or we make > a lib/gcd.c for it ? I think lib/gcd.c would be better. Then migrate current code over to use that. The problem with offering a generic version is types: will it work correctly and sensibly for all combinations of signed/unsigned char/short/int/long/longlong? All but the last, I expect. In which case that'll be good enough for now. From ralf@h5.dl5rb.org.uk Tue Jun 2 10:06:10 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 02 Jun 2009 10:06:17 +0100 (WEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:49628 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20021867AbZFBJGK (ORCPT ); Tue, 2 Jun 2009 10:06:10 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id n5295kwa003923; Tue, 2 Jun 2009 10:05:46 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id n5295jZ7003921; Tue, 2 Jun 2009 10:05:45 +0100 Date: Tue, 2 Jun 2009 10:05:45 +0100 From: Ralf Baechle To: Florian Fainelli Cc: linux-mips@linux-mips.org, Maxime Bizon Subject: Re: [PATCH 04/10] bcm63xx: register a fallback SPROM require for b43 to work Message-ID: <20090602090545.GA3527@linux-mips.org> References: <200905312028.02939.florian@openwrt.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <200905312028.02939.florian@openwrt.org> User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23166 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Sun, May 31, 2009 at 08:28:02PM +0200, Florian Fainelli wrote: > In order to get b43 working, we have to register a SPROM > which provides sane values to calibrate the radio, provide > GPIO settings and country code. The SSB bus is initialized > when the PCI bus is registered and expects to find the > SPROM at init time. Thus we have to move our device > registration from device_initcall to arch_initcall. The rationale > behind this comes from Broadcom not providing on-chip > EEPROM to store such settings, but relying on the main > system Flash to provide them by software means. > > Signed-off-by: Florian Fainelli Also folded into the series. Ralf From ralf@h5.dl5rb.org.uk Tue Jun 2 10:26:05 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 02 Jun 2009 10:26:13 +0100 (WEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:47169 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20021873AbZFBJ0F (ORCPT ); Tue, 2 Jun 2009 10:26:05 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id n529Pf89004716; Tue, 2 Jun 2009 10:25:41 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id n529Pfv9004714; Tue, 2 Jun 2009 10:25:41 +0100 Date: Tue, 2 Jun 2009 10:25:41 +0100 From: Ralf Baechle To: Florian Fainelli Cc: linux-mips@linux-mips.org, Maxime Bizon Subject: Re: [PATCH 10/10] bcm63xx: compile fixes for bcm63xx_enet.c Message-ID: <20090602092541.GB3527@linux-mips.org> References: <200905312031.35241.florian@openwrt.org> <20090601145552.GI6604@linux-mips.org> <200906011702.40561.florian@openwrt.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <200906011702.40561.florian@openwrt.org> User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23167 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Mon, Jun 01, 2009 at 05:02:38PM +0200, Florian Fainelli wrote: > > You should eventually run this patch by the network maintainers. It's > > a driver patch so I won't merge it upstream unless it's been acked by one > > of the network guys. > > Actually Maxime already submitted those patches, without much answer from the > network guys so I guess they just skipped it. Patches do get dropped so just resubmit until you get an ACK or NACK. Ralf From ralf@h5.dl5rb.org.uk Tue Jun 2 10:42:18 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 02 Jun 2009 10:42:25 +0100 (WEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:59304 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20021901AbZFBJmS (ORCPT ); Tue, 2 Jun 2009 10:42:18 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id n529fswo006973; Tue, 2 Jun 2009 10:41:54 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id n529fsWp006971; Tue, 2 Jun 2009 10:41:54 +0100 Date: Tue, 2 Jun 2009 10:41:54 +0100 From: Ralf Baechle To: Maxime Bizon Cc: linux-mips@linux-mips.org, Florian Fainelli Subject: Re: More updates to bcm63xx support (resend) Message-ID: <20090602094154.GC3527@linux-mips.org> References: <1243876918-9905-1-git-send-email-mbizon@freebox.fr> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1243876918-9905-1-git-send-email-mbizon@freebox.fr> User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23168 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Mon, Jun 01, 2009 at 07:21:48PM +0200, Maxime Bizon wrote: Whole series folded into the existing series. Thanks guys, Ralf From ralf@h5.dl5rb.org.uk Tue Jun 2 11:00:33 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 02 Jun 2009 11:00:41 +0100 (WEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:41721 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20021926AbZFBKAd (ORCPT ); Tue, 2 Jun 2009 11:00:33 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id n52A09vR009495; Tue, 2 Jun 2009 11:00:09 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id n52A09xh009487; Tue, 2 Jun 2009 11:00:09 +0100 Date: Tue, 2 Jun 2009 11:00:09 +0100 From: Ralf Baechle To: Florian Fainelli Cc: linux-mips@linux-mips.org, Maxime Bizon Subject: Re: [PATCH 3/3] bcm63xx: early registering of gpiochip Message-ID: <20090602100009.GD3527@linux-mips.org> References: <200906012018.20972.florian@openwrt.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <200906012018.20972.florian@openwrt.org> User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23169 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Mon, Jun 01, 2009 at 08:18:20PM +0200, Florian Fainelli wrote: > This patch makes the gpiochip be registered > earlier in the prom code. This allows GPIO-based > board detection to be made earlier. > > Tested-by: Maxime Bizon > Signed-off-by: Florian Fainelli > --- > diff --git a/arch/mips/bcm63xx/gpio.c b/arch/mips/bcm63xx/gpio.c > index b78d3fd..997fcaa 100644 > --- a/arch/mips/bcm63xx/gpio.c > +++ b/arch/mips/bcm63xx/gpio.c > @@ -120,9 +120,8 @@ static struct gpio_chip bcm63xx_gpio_chip = { > .ngpio = BCM63XX_GPIO_COUNT, > }; > > -static int __init bcm63xx_gpio_init(void) > +int __init bcm63xx_gpio_init(void) > { > printk(KERN_INFO "registering %d GPIOs\n", BCM63XX_GPIO_COUNT); > return gpiochip_add(&bcm63xx_gpio_chip); > } > -arch_initcall(bcm63xx_gpio_init); > diff --git a/arch/mips/bcm63xx/prom.c b/arch/mips/bcm63xx/prom.c > index d97ceed..1e5bb15 100644 > --- a/arch/mips/bcm63xx/prom.c > +++ b/arch/mips/bcm63xx/prom.c > @@ -13,6 +13,7 @@ > #include > #include > #include > +#include > > void __init prom_init(void) > { > @@ -40,6 +41,9 @@ void __init prom_init(void) > > /* do low level board init */ > board_prom_init(); > + > + /* early register gpio */ That word order sounds odd ... > + bcm63xx_gpio_init(); > } > > void __init prom_free_prom_memory(void) > diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h > index 72cee75..8bc812f 100644 > --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h > +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h > @@ -1,6 +1,8 @@ > #ifndef BCM63XX_GPIO_H > #define BCM63XX_GPIO_H > > +int __init bcm63xx_gpio_init(void); It is not necessary to declare a function as __init. But if you do you better include first. With this patch you'd rely on init.h having previously included which eventually when the context changes will blow up. And not last, the patch seems to reject ... Ralf From ralf@h5.dl5rb.org.uk Tue Jun 2 11:00:58 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 02 Jun 2009 11:01:05 +0100 (WEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:41728 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20021923AbZFBKAv (ORCPT ); Tue, 2 Jun 2009 11:00:51 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id n52A0R70009566; Tue, 2 Jun 2009 11:00:27 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id n52A0RWW009565; Tue, 2 Jun 2009 11:00:27 +0100 Date: Tue, 2 Jun 2009 11:00:27 +0100 From: Ralf Baechle To: Florian Fainelli Cc: linux-mips@linux-mips.org, Maxime Bizon Subject: Re: [PATCH 1/3] bcm63xx: fix printed CPU frequency Message-ID: <20090602100027.GE3527@linux-mips.org> References: <200906012017.05008.florian@openwrt.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <200906012017.05008.florian@openwrt.org> User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23170 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Mon, Jun 01, 2009 at 08:17:04PM +0200, Florian Fainelli wrote: Folded into the existing series. Ralf From ralf@h5.dl5rb.org.uk Tue Jun 2 11:01:49 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 02 Jun 2009 11:01:55 +0100 (WEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:34331 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20021923AbZFBKBt (ORCPT ); Tue, 2 Jun 2009 11:01:49 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id n52A1P3p009601; Tue, 2 Jun 2009 11:01:25 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id n52A1P92009600; Tue, 2 Jun 2009 11:01:25 +0100 Date: Tue, 2 Jun 2009 11:01:25 +0100 From: Ralf Baechle To: Florian Fainelli Cc: linux-mips@linux-mips.org, Maxime Bizon Subject: Re: [PATCH 2/3 v2] bcm63xx: select SSB since we are using ssb_arch_set_fallback_sprom Message-ID: <20090602100125.GF3527@linux-mips.org> References: <200906012022.20804.florian@openwrt.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <200906012022.20804.florian@openwrt.org> User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23171 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Mon, Jun 01, 2009 at 08:22:20PM +0200, Florian Fainelli wrote: Folded into the existing series. Thanks, Ralf From kaloz@arrakis.dune.hu Tue Jun 2 13:22:02 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 02 Jun 2009 13:22:09 +0100 (WEST) Received: from arrakis.dune.hu ([195.56.146.235]:57210 "EHLO arrakis.dune.hu" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20022014AbZFBMWC (ORCPT ); Tue, 2 Jun 2009 13:22:02 +0100 Received: from localhost (localhost [127.0.0.1]) by arrakis.dune.hu (Postfix) with ESMTP id 3997323C0108 for ; Tue, 2 Jun 2009 14:22:00 +0200 (CEST) X-Virus-Scanned: at arrakis.dune.hu Received: from arrakis.dune.hu ([127.0.0.1]) by localhost (arrakis.dune.hu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id fEvplN1rr5kx for ; Tue, 2 Jun 2009 14:22:00 +0200 (CEST) Received: by arrakis.dune.hu (Postfix, from userid 1000) id 25FC923C013F; Tue, 2 Jun 2009 14:22:00 +0200 (CEST) From: Imre Kaloz To: linux-mips@linux-mips.org Subject: [PATCH] Remove SiByte simulator option Date: Tue, 2 Jun 2009 14:22:00 +0200 Message-Id: <1243945320-4964-1-git-send-email-kaloz@openwrt.org> X-Mailer: git-send-email 1.6.0.4 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23172 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: kaloz@openwrt.org Precedence: bulk X-list: linux-mips This patch removes the SiByte simulation Kconfig option, which only modified a printk. Signed-off-by: Imre Kaloz --- arch/mips/sibyte/Kconfig | 7 ------- arch/mips/sibyte/swarm/setup.c | 4 ---- 2 files changed, 0 insertions(+), 11 deletions(-) diff --git a/arch/mips/sibyte/Kconfig b/arch/mips/sibyte/Kconfig index 366b19d..989d1a9 100644 --- a/arch/mips/sibyte/Kconfig +++ b/arch/mips/sibyte/Kconfig @@ -128,13 +128,6 @@ config SIBYTE_ENABLE_LDT_IF_PCI bool select SIBYTE_HAS_LDT if PCI -config SIMULATION - bool "Running under simulation" - depends on SIBYTE_SB1xxx_SOC - help - Build a kernel suitable for running under the GDB simulator. - Primarily adjusts the kernel's notion of time. - config SB1_CEX_ALWAYS_FATAL bool "All cache exceptions considered fatal (no recovery attempted)" depends on SIBYTE_SB1xxx_SOC diff --git a/arch/mips/sibyte/swarm/setup.c b/arch/mips/sibyte/swarm/setup.c index 080c966..cffa30a 100644 --- a/arch/mips/sibyte/swarm/setup.c +++ b/arch/mips/sibyte/swarm/setup.c @@ -137,11 +137,7 @@ void __init plat_mem_setup(void) swarm_rtc_type = RTC_M4LT81; printk("This kernel optimized for " -#ifdef CONFIG_SIMULATION - "simulation" -#else "board" -#endif " runs " #ifdef CONFIG_SIBYTE_CFE "with" -- 1.6.0.4 From kaloz@arrakis.dune.hu Tue Jun 2 13:22:26 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 02 Jun 2009 13:22:34 +0100 (WEST) Received: from arrakis.dune.hu ([195.56.146.235]:57258 "EHLO arrakis.dune.hu" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20022024AbZFBMWJ (ORCPT ); Tue, 2 Jun 2009 13:22:09 +0100 Received: from localhost (localhost [127.0.0.1]) by arrakis.dune.hu (Postfix) with ESMTP id 28FC023C0108 for ; Tue, 2 Jun 2009 14:22:09 +0200 (CEST) X-Virus-Scanned: at arrakis.dune.hu Received: from arrakis.dune.hu ([127.0.0.1]) by localhost (arrakis.dune.hu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id V6cHRFhyUNBk for ; Tue, 2 Jun 2009 14:22:06 +0200 (CEST) Received: by arrakis.dune.hu (Postfix, from userid 1000) id 55B7A23C013F; Tue, 2 Jun 2009 14:22:06 +0200 (CEST) From: Imre Kaloz To: linux-mips@linux-mips.org Subject: [PATCH] Remove standalone SiByte kernel support Date: Tue, 2 Jun 2009 14:22:06 +0200 Message-Id: <1243945326-5029-1-git-send-email-kaloz@openwrt.org> X-Mailer: git-send-email 1.6.0.4 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23173 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: kaloz@openwrt.org Precedence: bulk X-list: linux-mips CFE is the only supported and used bootloader on the SiByte boards, the standalone kernel support has been never used outside Broadcom. Remove it and make the kernel use CFE by default. Signed-off-by: Imre Kaloz --- arch/mips/Makefile | 1 - arch/mips/sibyte/Kconfig | 24 +-- arch/mips/sibyte/cfe/Makefile | 2 - arch/mips/sibyte/cfe/console.c | 79 -------- arch/mips/sibyte/cfe/setup.c | 350 --------------------------------- arch/mips/sibyte/common/Makefile | 4 +- arch/mips/sibyte/common/cfe.c | 350 +++++++++++++++++++++++++++++++++ arch/mips/sibyte/common/cfe_console.c | 79 ++++++++ arch/mips/sibyte/sb1250/Makefile | 1 - arch/mips/sibyte/sb1250/prom.c | 96 --------- arch/mips/sibyte/swarm/setup.c | 10 - 11 files changed, 434 insertions(+), 562 deletions(-) delete mode 100644 arch/mips/sibyte/cfe/Makefile delete mode 100644 arch/mips/sibyte/cfe/console.c delete mode 100644 arch/mips/sibyte/cfe/setup.c create mode 100644 arch/mips/sibyte/common/cfe.c create mode 100644 arch/mips/sibyte/common/cfe_console.c delete mode 100644 arch/mips/sibyte/sb1250/prom.c diff --git a/arch/mips/Makefile b/arch/mips/Makefile index c4cae9e..52a3509 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -167,7 +167,6 @@ libs-$(CONFIG_ARC) += arch/mips/fw/arc/ libs-$(CONFIG_CFE) += arch/mips/fw/cfe/ libs-$(CONFIG_SNIPROM) += arch/mips/fw/sni/ libs-y += arch/mips/fw/lib/ -libs-$(CONFIG_SIBYTE_CFE) += arch/mips/sibyte/cfe/ # # Board-dependent options and extra files diff --git a/arch/mips/sibyte/Kconfig b/arch/mips/sibyte/Kconfig index 989d1a9..3e639bd 100644 --- a/arch/mips/sibyte/Kconfig +++ b/arch/mips/sibyte/Kconfig @@ -75,6 +75,8 @@ config SIBYTE_SB1xxx_SOC select SWAP_IO_SPACE select SYS_SUPPORTS_32BIT_KERNEL select SYS_SUPPORTS_64BIT_KERNEL + select CFE + select SYS_HAS_EARLY_PRINTK choice prompt "SiByte SOC Stepping" @@ -136,34 +138,14 @@ config SB1_CERR_STALL bool "Stall (rather than panic) on fatal cache error" depends on SIBYTE_SB1xxx_SOC -config SIBYTE_CFE - bool "Booting from CFE" - depends on SIBYTE_SB1xxx_SOC - select CFE - select SYS_HAS_EARLY_PRINTK - help - Make use of the CFE API for enumerating available memory, - controlling secondary CPUs, and possibly console output. - config SIBYTE_CFE_CONSOLE bool "Use firmware console" - depends on SIBYTE_CFE + depends on SIBYTE_SB1xxx_SOC help Use the CFE API's console write routines during boot. Other console options (VT console, sb1250 duart console, etc.) should not be configured. -config SIBYTE_STANDALONE - bool - depends on SIBYTE_SB1xxx_SOC && !SIBYTE_CFE - select SYS_HAS_EARLY_PRINTK - default y - -config SIBYTE_STANDALONE_RAM_SIZE - int "Memory size (in megabytes)" - depends on SIBYTE_STANDALONE - default "32" - config SIBYTE_BUS_WATCHER bool "Support for Bus Watcher statistics" depends on SIBYTE_SB1xxx_SOC diff --git a/arch/mips/sibyte/cfe/Makefile b/arch/mips/sibyte/cfe/Makefile deleted file mode 100644 index 02b32e1..0000000 --- a/arch/mips/sibyte/cfe/Makefile +++ /dev/null @@ -1,2 +0,0 @@ -lib-y = setup.o -lib-$(CONFIG_SIBYTE_CFE_CONSOLE) += console.o diff --git a/arch/mips/sibyte/cfe/console.c b/arch/mips/sibyte/cfe/console.c deleted file mode 100644 index 81e3d54..0000000 --- a/arch/mips/sibyte/cfe/console.c +++ /dev/null @@ -1,79 +0,0 @@ -#include -#include -#include - -#include - -#include -#include - -extern int cfe_cons_handle; - -static void cfe_console_write(struct console *cons, const char *str, - unsigned int count) -{ - int i, last, written; - - for (i=0, last=0; i MAX_RAM_SIZE) - || (initrd_pend > MAX_RAM_SIZE))) { - panic("initrd out of addressable memory"); - } - -#endif /* INITRD */ - - for (idx = 0; cfe_enummem(idx, mem_flags, &addr, &size, &type) != CFE_ERR_NOMORE; - idx++) { - rd_flag = 0; - if (type == CFE_MI_AVAILABLE) { - /* - * See if this block contains (any portion of) the - * ramdisk - */ -#ifdef CONFIG_BLK_DEV_INITRD - if (initrd_start) { - if ((initrd_pstart > addr) && - (initrd_pstart < (addr + size))) { - add_memory_region(addr, - initrd_pstart - addr, - BOOT_MEM_RAM); - rd_flag = 1; - } - if ((initrd_pend > addr) && - (initrd_pend < (addr + size))) { - add_memory_region(initrd_pend, - (addr + size) - initrd_pend, - BOOT_MEM_RAM); - rd_flag = 1; - } - } -#endif - if (!rd_flag) { - if (addr > MAX_RAM_SIZE) - continue; - if (addr+size > MAX_RAM_SIZE) - size = MAX_RAM_SIZE - (addr+size) + 1; - /* - * memcpy/__copy_user prefetch, which - * will cause a bus error for - * KSEG/KUSEG addrs not backed by RAM. - * Hence, reserve some padding for the - * prefetch distance. - */ - if (size > 512) - size -= 512; - add_memory_region(addr, size, BOOT_MEM_RAM); - } - board_mem_region_addrs[board_mem_region_count] = addr; - board_mem_region_sizes[board_mem_region_count] = size; - board_mem_region_count++; - if (board_mem_region_count == - SIBYTE_MAX_MEM_REGIONS) { - /* - * Too many regions. Need to configure more - */ - while(1); - } - } - } -#ifdef CONFIG_BLK_DEV_INITRD - if (initrd_start) { - add_memory_region(initrd_pstart, initrd_pend - initrd_pstart, - BOOT_MEM_RESERVED); - } -#endif -} - -#ifdef CONFIG_BLK_DEV_INITRD -static int __init initrd_setup(char *str) -{ - char rdarg[64]; - int idx; - char *tmp, *endptr; - unsigned long initrd_size; - - /* Make a copy of the initrd argument so we can smash it up here */ - for (idx = 0; idx < sizeof(rdarg)-1; idx++) { - if (!str[idx] || (str[idx] == ' ')) break; - rdarg[idx] = str[idx]; - } - - rdarg[idx] = 0; - str = rdarg; - - /* - *Initrd location comes in the form "@" - * e.g. initrd=3abfd@80010000. This is set up by the loader. - */ - for (tmp = str; *tmp != '@'; tmp++) { - if (!*tmp) { - goto fail; - } - } - *tmp = 0; - tmp++; - if (!*tmp) { - goto fail; - } - initrd_size = simple_strtoul(str, &endptr, 16); - if (*endptr) { - *(tmp-1) = '@'; - goto fail; - } - *(tmp-1) = '@'; - initrd_start = simple_strtoul(tmp, &endptr, 16); - if (*endptr) { - goto fail; - } - initrd_end = initrd_start + initrd_size; - printk("Found initrd of %lx@%lx\n", initrd_size, initrd_start); - return 1; - fail: - printk("Bad initrd argument. Disabling initrd\n"); - initrd_start = 0; - initrd_end = 0; - return 1; -} - -#endif - -extern struct plat_smp_ops sb_smp_ops; -extern struct plat_smp_ops bcm1480_smp_ops; - -/* - * prom_init is called just after the cpu type is determined, from setup_arch() - */ -void __init prom_init(void) -{ - uint64_t cfe_ept, cfe_handle; - unsigned int cfe_eptseal; - int argc = fw_arg0; - char **envp = (char **) fw_arg2; - int *prom_vec = (int *) fw_arg3; - - _machine_restart = cfe_linux_restart; - _machine_halt = cfe_linux_halt; - pm_power_off = cfe_linux_halt; - - /* - * Check if a loader was used; if NOT, the 4 arguments are - * what CFE gives us (handle, 0, EPT and EPTSEAL) - */ - if (argc < 0) { - cfe_handle = (uint64_t)(long)argc; - cfe_ept = (long)envp; - cfe_eptseal = (uint32_t)(unsigned long)prom_vec; - } else { - if ((int32_t)(long)prom_vec < 0) { - /* - * Old loader; all it gives us is the handle, - * so use the "known" entrypoint and assume - * the seal. - */ - cfe_handle = (uint64_t)(long)prom_vec; - cfe_ept = (uint64_t)((int32_t)0x9fc00500); - cfe_eptseal = CFE_EPTSEAL; - } else { - /* - * Newer loaders bundle the handle/ept/eptseal - * Note: prom_vec is in the loader's useg - * which is still alive in the TLB. - */ - cfe_handle = (uint64_t)((int32_t *)prom_vec)[0]; - cfe_ept = (uint64_t)((int32_t *)prom_vec)[2]; - cfe_eptseal = (unsigned int)((uint32_t *)prom_vec)[3]; - } - } - if (cfe_eptseal != CFE_EPTSEAL) { - /* too early for panic to do any good */ - printk("CFE's entrypoint seal doesn't match. Spinning."); - while (1) ; - } - cfe_init(cfe_handle, cfe_ept); - /* - * Get the handle for (at least) prom_putchar, possibly for - * boot console - */ - cfe_cons_handle = cfe_getstdhandle(CFE_STDHANDLE_CONSOLE); - if (cfe_getenv("LINUX_CMDLINE", arcs_cmdline, CL_SIZE) < 0) { - if (argc < 0) { - /* - * It's OK for direct boot to not provide a - * command line - */ - strcpy(arcs_cmdline, "root=/dev/ram0 "); - } else { - /* The loader should have set the command line */ - /* too early for panic to do any good */ - printk("LINUX_CMDLINE not defined in cfe."); - while (1) ; - } - } - -#ifdef CONFIG_BLK_DEV_INITRD - { - char *ptr; - /* Need to find out early whether we've got an initrd. So scan - the list looking now */ - for (ptr = arcs_cmdline; *ptr; ptr++) { - while (*ptr == ' ') { - ptr++; - } - if (!strncmp(ptr, "initrd=", 7)) { - initrd_setup(ptr+7); - break; - } else { - while (*ptr && (*ptr != ' ')) { - ptr++; - } - } - } - } -#endif /* CONFIG_BLK_DEV_INITRD */ - - /* Not sure this is needed, but it's the safe way. */ - arcs_cmdline[CL_SIZE-1] = 0; - - prom_meminit(); - -#if defined(CONFIG_SIBYTE_BCM112X) || defined(CONFIG_SIBYTE_SB1250) - register_smp_ops(&sb_smp_ops); -#endif -#if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80) - register_smp_ops(&bcm1480_smp_ops); -#endif -} - -void __init prom_free_prom_memory(void) -{ - /* Not sure what I'm supposed to do here. Nothing, I think */ -} - -void prom_putchar(char c) -{ - int ret; - - while ((ret = cfe_write(cfe_cons_handle, &c, 1)) == 0) - ; -} diff --git a/arch/mips/sibyte/common/Makefile b/arch/mips/sibyte/common/Makefile index 48a91b9..4f65983 100644 --- a/arch/mips/sibyte/common/Makefile +++ b/arch/mips/sibyte/common/Makefile @@ -1,5 +1,5 @@ -obj-y := - +obj-y := cfe.o +obj-$(CONFIG_SIBYTE_CFE_CONSOLE) += cfe_console.o obj-$(CONFIG_SIBYTE_TBPROF) += sb_tbprof.o EXTRA_CFLAGS += -Werror diff --git a/arch/mips/sibyte/common/cfe.c b/arch/mips/sibyte/common/cfe.c new file mode 100644 index 0000000..3de30f7 --- /dev/null +++ b/arch/mips/sibyte/common/cfe.c @@ -0,0 +1,350 @@ +/* + * Copyright (C) 2000, 2001, 2002, 2003 Broadcom Corporation + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include +#include + +/* Max ram addressable in 32-bit segments */ +#ifdef CONFIG_64BIT +#define MAX_RAM_SIZE (~0ULL) +#else +#ifdef CONFIG_HIGHMEM +#ifdef CONFIG_64BIT_PHYS_ADDR +#define MAX_RAM_SIZE (~0ULL) +#else +#define MAX_RAM_SIZE (0xffffffffULL) +#endif +#else +#define MAX_RAM_SIZE (0x1fffffffULL) +#endif +#endif + +#define SIBYTE_MAX_MEM_REGIONS 8 +phys_t board_mem_region_addrs[SIBYTE_MAX_MEM_REGIONS]; +phys_t board_mem_region_sizes[SIBYTE_MAX_MEM_REGIONS]; +unsigned int board_mem_region_count; + +int cfe_cons_handle; + +#ifdef CONFIG_BLK_DEV_INITRD +extern unsigned long initrd_start, initrd_end; +#endif + +static void __noreturn cfe_linux_exit(void *arg) +{ + int warm = *(int *)arg; + + if (smp_processor_id()) { + static int reboot_smp; + + /* Don't repeat the process from another CPU */ + if (!reboot_smp) { + /* Get CPU 0 to do the cfe_exit */ + reboot_smp = 1; + smp_call_function(cfe_linux_exit, arg, 0); + } + } else { + printk("Passing control back to CFE...\n"); + cfe_exit(warm, 0); + printk("cfe_exit returned??\n"); + } + while (1); +} + +static void __noreturn cfe_linux_restart(char *command) +{ + static const int zero; + + cfe_linux_exit((void *)&zero); +} + +static void __noreturn cfe_linux_halt(void) +{ + static const int one = 1; + + cfe_linux_exit((void *)&one); +} + +static __init void prom_meminit(void) +{ + u64 addr, size, type; /* regardless of 64BIT_PHYS_ADDR */ + int mem_flags = 0; + unsigned int idx; + int rd_flag; +#ifdef CONFIG_BLK_DEV_INITRD + unsigned long initrd_pstart; + unsigned long initrd_pend; + + initrd_pstart = CPHYSADDR(initrd_start); + initrd_pend = CPHYSADDR(initrd_end); + if (initrd_start && + ((initrd_pstart > MAX_RAM_SIZE) + || (initrd_pend > MAX_RAM_SIZE))) { + panic("initrd out of addressable memory"); + } + +#endif /* INITRD */ + + for (idx = 0; cfe_enummem(idx, mem_flags, &addr, &size, &type) != CFE_ERR_NOMORE; + idx++) { + rd_flag = 0; + if (type == CFE_MI_AVAILABLE) { + /* + * See if this block contains (any portion of) the + * ramdisk + */ +#ifdef CONFIG_BLK_DEV_INITRD + if (initrd_start) { + if ((initrd_pstart > addr) && + (initrd_pstart < (addr + size))) { + add_memory_region(addr, + initrd_pstart - addr, + BOOT_MEM_RAM); + rd_flag = 1; + } + if ((initrd_pend > addr) && + (initrd_pend < (addr + size))) { + add_memory_region(initrd_pend, + (addr + size) - initrd_pend, + BOOT_MEM_RAM); + rd_flag = 1; + } + } +#endif + if (!rd_flag) { + if (addr > MAX_RAM_SIZE) + continue; + if (addr+size > MAX_RAM_SIZE) + size = MAX_RAM_SIZE - (addr+size) + 1; + /* + * memcpy/__copy_user prefetch, which + * will cause a bus error for + * KSEG/KUSEG addrs not backed by RAM. + * Hence, reserve some padding for the + * prefetch distance. + */ + if (size > 512) + size -= 512; + add_memory_region(addr, size, BOOT_MEM_RAM); + } + board_mem_region_addrs[board_mem_region_count] = addr; + board_mem_region_sizes[board_mem_region_count] = size; + board_mem_region_count++; + if (board_mem_region_count == + SIBYTE_MAX_MEM_REGIONS) { + /* + * Too many regions. Need to configure more + */ + while(1); + } + } + } +#ifdef CONFIG_BLK_DEV_INITRD + if (initrd_start) { + add_memory_region(initrd_pstart, initrd_pend - initrd_pstart, + BOOT_MEM_RESERVED); + } +#endif +} + +#ifdef CONFIG_BLK_DEV_INITRD +static int __init initrd_setup(char *str) +{ + char rdarg[64]; + int idx; + char *tmp, *endptr; + unsigned long initrd_size; + + /* Make a copy of the initrd argument so we can smash it up here */ + for (idx = 0; idx < sizeof(rdarg)-1; idx++) { + if (!str[idx] || (str[idx] == ' ')) break; + rdarg[idx] = str[idx]; + } + + rdarg[idx] = 0; + str = rdarg; + + /* + *Initrd location comes in the form "@" + * e.g. initrd=3abfd@80010000. This is set up by the loader. + */ + for (tmp = str; *tmp != '@'; tmp++) { + if (!*tmp) { + goto fail; + } + } + *tmp = 0; + tmp++; + if (!*tmp) { + goto fail; + } + initrd_size = simple_strtoul(str, &endptr, 16); + if (*endptr) { + *(tmp-1) = '@'; + goto fail; + } + *(tmp-1) = '@'; + initrd_start = simple_strtoul(tmp, &endptr, 16); + if (*endptr) { + goto fail; + } + initrd_end = initrd_start + initrd_size; + printk("Found initrd of %lx@%lx\n", initrd_size, initrd_start); + return 1; + fail: + printk("Bad initrd argument. Disabling initrd\n"); + initrd_start = 0; + initrd_end = 0; + return 1; +} + +#endif + +extern struct plat_smp_ops sb_smp_ops; +extern struct plat_smp_ops bcm1480_smp_ops; + +/* + * prom_init is called just after the cpu type is determined, from setup_arch() + */ +void __init prom_init(void) +{ + uint64_t cfe_ept, cfe_handle; + unsigned int cfe_eptseal; + int argc = fw_arg0; + char **envp = (char **) fw_arg2; + int *prom_vec = (int *) fw_arg3; + + _machine_restart = cfe_linux_restart; + _machine_halt = cfe_linux_halt; + pm_power_off = cfe_linux_halt; + + /* + * Check if a loader was used; if NOT, the 4 arguments are + * what CFE gives us (handle, 0, EPT and EPTSEAL) + */ + if (argc < 0) { + cfe_handle = (uint64_t)(long)argc; + cfe_ept = (long)envp; + cfe_eptseal = (uint32_t)(unsigned long)prom_vec; + } else { + if ((int32_t)(long)prom_vec < 0) { + /* + * Old loader; all it gives us is the handle, + * so use the "known" entrypoint and assume + * the seal. + */ + cfe_handle = (uint64_t)(long)prom_vec; + cfe_ept = (uint64_t)((int32_t)0x9fc00500); + cfe_eptseal = CFE_EPTSEAL; + } else { + /* + * Newer loaders bundle the handle/ept/eptseal + * Note: prom_vec is in the loader's useg + * which is still alive in the TLB. + */ + cfe_handle = (uint64_t)((int32_t *)prom_vec)[0]; + cfe_ept = (uint64_t)((int32_t *)prom_vec)[2]; + cfe_eptseal = (unsigned int)((uint32_t *)prom_vec)[3]; + } + } + if (cfe_eptseal != CFE_EPTSEAL) { + /* too early for panic to do any good */ + printk("CFE's entrypoint seal doesn't match. Spinning."); + while (1) ; + } + cfe_init(cfe_handle, cfe_ept); + /* + * Get the handle for (at least) prom_putchar, possibly for + * boot console + */ + cfe_cons_handle = cfe_getstdhandle(CFE_STDHANDLE_CONSOLE); + if (cfe_getenv("LINUX_CMDLINE", arcs_cmdline, CL_SIZE) < 0) { + if (argc < 0) { + /* + * It's OK for direct boot to not provide a + * command line + */ + strcpy(arcs_cmdline, "root=/dev/ram0 "); + } else { + /* The loader should have set the command line */ + /* too early for panic to do any good */ + printk("LINUX_CMDLINE not defined in cfe."); + while (1) ; + } + } + +#ifdef CONFIG_BLK_DEV_INITRD + { + char *ptr; + /* Need to find out early whether we've got an initrd. So scan + the list looking now */ + for (ptr = arcs_cmdline; *ptr; ptr++) { + while (*ptr == ' ') { + ptr++; + } + if (!strncmp(ptr, "initrd=", 7)) { + initrd_setup(ptr+7); + break; + } else { + while (*ptr && (*ptr != ' ')) { + ptr++; + } + } + } + } +#endif /* CONFIG_BLK_DEV_INITRD */ + + /* Not sure this is needed, but it's the safe way. */ + arcs_cmdline[CL_SIZE-1] = 0; + + prom_meminit(); + +#if defined(CONFIG_SIBYTE_BCM112X) || defined(CONFIG_SIBYTE_SB1250) + register_smp_ops(&sb_smp_ops); +#endif +#if defined(CONFIG_SIBYTE_BCM1x55) || defined(CONFIG_SIBYTE_BCM1x80) + register_smp_ops(&bcm1480_smp_ops); +#endif +} + +void __init prom_free_prom_memory(void) +{ + /* Not sure what I'm supposed to do here. Nothing, I think */ +} + +void prom_putchar(char c) +{ + int ret; + + while ((ret = cfe_write(cfe_cons_handle, &c, 1)) == 0) + ; +} diff --git a/arch/mips/sibyte/common/cfe_console.c b/arch/mips/sibyte/common/cfe_console.c new file mode 100644 index 0000000..81e3d54 --- /dev/null +++ b/arch/mips/sibyte/common/cfe_console.c @@ -0,0 +1,79 @@ +#include +#include +#include + +#include + +#include +#include + +extern int cfe_cons_handle; + +static void cfe_console_write(struct console *cons, const char *str, + unsigned int count) +{ + int i, last, written; + + for (i=0, last=0; i); Tue, 2 Jun 2009 13:22:16 +0100 Received: from localhost (localhost [127.0.0.1]) by arrakis.dune.hu (Postfix) with ESMTP id 24EB123C0143 for ; Tue, 2 Jun 2009 14:22:16 +0200 (CEST) X-Virus-Scanned: at arrakis.dune.hu Received: from arrakis.dune.hu ([127.0.0.1]) by localhost (arrakis.dune.hu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id uuof-Zsj8-4E for ; Tue, 2 Jun 2009 14:22:14 +0200 (CEST) Received: by arrakis.dune.hu (Postfix, from userid 1000) id 22CA923C013F; Tue, 2 Jun 2009 14:22:14 +0200 (CEST) From: Imre Kaloz To: linux-mips@linux-mips.org Subject: [PATCH] Honor CONFIG_CMDLINE on SiByte Date: Tue, 2 Jun 2009 14:22:14 +0200 Message-Id: <1243945334-5090-1-git-send-email-kaloz@openwrt.org> X-Mailer: git-send-email 1.6.0.4 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23174 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: kaloz@openwrt.org Precedence: bulk X-list: linux-mips The SiByte platform code doesn't honor the CONFIG_CMDLINE kernel option. This patch fixes this issue. Signed-off-by: Imre Kaloz --- arch/mips/sibyte/common/cfe.c | 4 ++++ 1 files changed, 4 insertions(+), 0 deletions(-) diff --git a/arch/mips/sibyte/common/cfe.c b/arch/mips/sibyte/common/cfe.c index 3de30f7..97e997e 100644 --- a/arch/mips/sibyte/common/cfe.c +++ b/arch/mips/sibyte/common/cfe.c @@ -293,7 +293,11 @@ void __init prom_init(void) * It's OK for direct boot to not provide a * command line */ +#ifdef CONFIG_CMDLINE + strlcpy(arcs_cmdline, CONFIG_CMDLINE, COMMAND_LINE_SIZE); +#else strcpy(arcs_cmdline, "root=/dev/ram0 "); +#endif } else { /* The loader should have set the command line */ /* too early for panic to do any good */ -- 1.6.0.4 From ralf@h5.dl5rb.org.uk Tue Jun 2 13:52:23 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 02 Jun 2009 13:52:30 +0100 (WEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:34532 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20022035AbZFBMwX (ORCPT ); Tue, 2 Jun 2009 13:52:23 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id n52Cq0pB022353; Tue, 2 Jun 2009 13:52:00 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id n52CpxUH022351; Tue, 2 Jun 2009 13:51:59 +0100 Date: Tue, 2 Jun 2009 13:51:59 +0100 From: Ralf Baechle To: Florian Fainelli Cc: linux-mips@linux-mips.org, openwrt-devel@lists.openwrt.org Subject: Re: [PATCH 08/10] add TI AR7 support Message-ID: <20090602125159.GC11488@linux-mips.org> References: <200906011402.05768.florian@openwrt.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <200906011402.05768.florian@openwrt.org> User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23175 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Mon, Jun 01, 2009 at 02:02:05PM +0200, Florian Fainelli wrote: > Subject: [PATCH 08/10] add TI AR7 support This should be 7/9 I assume? > + if (base / (*prediv) * (*mul) / (*postdiv) != target) { There should be a tax on excessive use of parenthesis ;-) > + approximate(base, target, prediv, postdiv, mul); > + tmp_freq = base / (*prediv) * (*mul) / (*postdiv); More taxes! > + > + writel(((prediv - 1) << PREDIV_SHIFT) | (postdiv - 1), &clock->ctrl); > + mdelay(1); > + writel(4, &clock->pll); > + while (readl(&clock->pll) & PLL_STATUS) > + ; > + writel(((mul - 1) << MUL_SHIFT) | (0xff << 3) | 0x0e, &clock->pll); > + mdelay(75); These calls to mdelay seem to be done very early before BogoMIPS has been calibrated? > + printk(KERN_INFO "Clocks: Setting USB clock\n"); > + usb_base = ar7_bus_clock; > + calculate(usb_base, TNETD7200_DEF_USB_CLK, &usb_prediv, > + &usb_postdiv, &usb_mul); > + tnetd7200_set_clock(usb_base, &clocks->usb, > + usb_prediv, usb_postdiv, -1, usb_mul, > + TNETD7200_DEF_USB_CLK); > + > + #warning FIXME > + ar7_dsp_clock = ar7_cpu_clock; Fix it :-) > +void __init ar7_init_clocks(void) > +{ > + switch (ar7_chip_id()) { > + case AR7_CHIP_7100: > +#warning FIXME: Check if the new 7200 clock init works for 7100 Fix it again, Toni. > diff --git a/arch/mips/ar7/memory.c b/arch/mips/ar7/memory.c > new file mode 100644 > index 0000000..e8522a1 > --- /dev/null > +++ b/arch/mips/ar7/memory.c > @@ -0,0 +1,74 @@ > +/* > + * Based on arch/mips/mm/init.c > + * Copyright (C) 1994 - 2000 Ralf Baechle > + * Copyright (C) 1999, 2000 Silicon Graphics, Inc. > + * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com > + * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. Somehow this file has no similarity to arch/mips/mm/init.c so I think somebody else should claim the (C). > --- /dev/null > +++ b/arch/mips/ar7/platform.c > @@ -0,0 +1,543 @@ > +/* > + * Copyright (C) 2006,2007 Felix Fietkau > + * Copyright (C) 2006,2007 Eugene Konev > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, write to the Free Software > + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA > + */ > + > +#include Do not include . > +static struct platform_device vlynq_high = { > + .id = 1, > + .name = "vlynq", > + .dev.platform_data = &vlynq_high_data, > + .resource = vlynq_high_res, > + .num_resources = ARRAY_SIZE(vlynq_high_res), > +}; > + > + > +/* This is proper way to define uart ports, but they are then detected > + * as xscale and, obviously, don't work... > + */ > +#if !defined(CONFIG_SERIAL_8250) Can you elaborate? > +static inline unsigned char char2hex(char h) > +{ > + switch (h) { > + case '0': case '1': case '2': case '3': case '4': > + case '5': case '6': case '7': case '8': case '9': > + return h - '0'; > + case 'A': case 'B': case 'C': case 'D': case 'E': case 'F': > + return h - 'A' + 10; > + case 'a': case 'b': case 'c': case 'd': case 'e': case 'f': > + return h - 'a' + 10; > + default: > + return 0; > + } > +} > + > +static void cpmac_get_mac(int instance, unsigned char *dev_addr) > +{ > + int i; > + char name[5], default_mac[] = "00:00:00:12:34:56", *mac; If you don't have a MAC address, either use random_ether_addr() or don't bring up the network interface at all. Multiple interfaces with the same MAC can cause chaos on a network to better avoid that. > +struct psp_env_chunk { > + u8 num; > + u8 ctrl; > + u16 csum; > + u8 len; > + char data[11]; > +} __attribute__ ((packed)); Afair historic versions of this code were totally polluted with __attribute__((packed)). Thanks for cleaning that. Btw - Linux coding style: No space between __attribute__ and ((packed)). > +#include You get a false warning from checkpatch.pl here. Which probably means either we should teach checkpatch.pl to check if is actually including or rename to something which would also help to avoid confusion. > +++ b/arch/mips/include/asm/mach-ar7/spaces.h You can cut down this header file to something like: /* Copyright blurb */ #ifndef _ASM_AR7_SPACES_H #define _ASM_AR7_SPACES_H /* * This handles the memory map. * We handle pages at KSEG0 for kernels with 32 bit address space. */ #define PAGE_OFFSET 0x94000000UL #define PHYS_OFFSET 0x14000000UL #include #endif /* __ASM_AR7_SPACES_H */ Ralf From anemo@mba.ocn.ne.jp Tue Jun 2 15:13:18 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 02 Jun 2009 15:13:25 +0100 (WEST) Received: from mba.ocn.ne.jp ([122.1.235.107]:61722 "HELO smtp.mba.ocn.ne.jp" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with SMTP id S20022066AbZFBONS (ORCPT ); Tue, 2 Jun 2009 15:13:18 +0100 Received: from localhost (p7143-ipad205funabasi.chiba.ocn.ne.jp [222.146.102.143]) by smtp.mba.ocn.ne.jp (Postfix) with ESMTP id F31F5AA7C; Tue, 2 Jun 2009 23:13:11 +0900 (JST) Date: Tue, 02 Jun 2009 23:13:11 +0900 (JST) Message-Id: <20090602.231311.106274589.anemo@mba.ocn.ne.jp> To: mpm@selenic.com Cc: linux-mips@linux-mips.org, ralf@linux-mips.org, linux-kernel@vger.kernel.org, herbert@gondor.apana.org.au Subject: Re: [PATCH] TXx9: Add TX4939 RNG support From: Atsushi Nemoto In-Reply-To: <1243791170.22069.28.camel@calx> References: <1243789289.22069.25.camel@calx> <20090601.022335.200392387.anemo@mba.ocn.ne.jp> <1243791170.22069.28.camel@calx> X-Fingerprint: 6ACA 1623 39BD 9A94 9B1A B746 CA77 FE94 2874 D52F X-Pgp-Public-Key: http://wwwkeys.pgp.net/pks/lookup?op=get&search=0x2874D52F X-Mailer: Mew version 5.2 on Emacs 22.2 / Mule 5.0 (SAKAKI) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23176 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anemo@mba.ocn.ne.jp Precedence: bulk X-list: linux-mips On Sun, 31 May 2009 12:32:50 -0500, Matt Mackall wrote: > > No, the rng driver can be used regardless of module or built-in, as > > like as other platform drivers. Any special issue for hw_rng? > > I found the source of my confusion: you've given the init function in > both files exactly the same name. So when I saw .._init at the bottom of > the second patch, I assumed it was referring to the possibly not loaded > driver's init code. OK, I see. I will rename one of them to avoid such a confusion. Thanks. --- Atsushi Nemoto From yoichi_yuasa@tripeaks.co.jp Tue Jun 2 15:15:18 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 02 Jun 2009 15:15:24 +0100 (WEST) Received: from mow301.po.2iij.net ([210.128.50.232]:34629 "EHLO mow.po.2iij.net" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20022066AbZFBOPS (ORCPT ); Tue, 2 Jun 2009 15:15:18 +0100 Received: by mow.po.2iij.net (mow301) id n52EFDqQ000453; Tue, 2 Jun 2009 23:15:13 +0900 Received: from fulvia (199.9.30.125.dy.iij4u.or.jp [125.30.9.199]) by mbox.po.2iij.net (po-mbox303) id n52EFAP9030173 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NOT); Tue, 2 Jun 2009 23:15:11 +0900 Date: Tue, 2 Jun 2009 23:15:10 +0900 From: Yoichi Yuasa To: Ralf Baechle Cc: yoichi_yuasa@tripeaks.co.jp, linux-mips Subject: [PATCH][MIPS] remove "Support for" from Cavium system type Message-Id: <20090602231510.339c24a3.yoichi_yuasa@tripeaks.co.jp> Organization: TriPeaks Corporation X-Mailer: Sylpheed 2.5.0 (GTK+ 2.12.12; i486-pc-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23177 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: yoichi_yuasa@tripeaks.co.jp Precedence: bulk X-list: linux-mips Signed-off-by: Yoichi Yuasa diff -pruN -X /home/yuasa/Memo/dontdiff linux-orig/arch/mips/Kconfig linux/arch/mips/Kconfig --- linux-orig/arch/mips/Kconfig 2009-04-16 21:22:33.885188833 +0900 +++ linux/arch/mips/Kconfig 2009-04-16 21:13:04.881168129 +0900 @@ -593,7 +593,7 @@ config WR_PPMC board, which is based on GT64120 bridge chip. config CAVIUM_OCTEON_SIMULATOR - bool "Support for the Cavium Networks Octeon Simulator" + bool "Cavium Networks Octeon Simulator" select CEVT_R4K select 64BIT_PHYS_ADDR select DMA_COHERENT @@ -607,7 +607,7 @@ config CAVIUM_OCTEON_SIMULATOR hardware. config CAVIUM_OCTEON_REFERENCE_BOARD - bool "Support for the Cavium Networks Octeon reference board" + bool "Cavium Networks Octeon reference board" select CEVT_R4K select 64BIT_PHYS_ADDR select DMA_COHERENT From yoichi_yuasa@tripeaks.co.jp Tue Jun 2 15:17:15 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 02 Jun 2009 15:17:21 +0100 (WEST) Received: from mow301.po.2iij.net ([210.128.50.232]:58787 "EHLO mow.po.2iij.net" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20022066AbZFBORP (ORCPT ); Tue, 2 Jun 2009 15:17:15 +0100 Received: by mow.po.2iij.net (mow301) id n52EHCna000941; Tue, 2 Jun 2009 23:17:12 +0900 Received: from fulvia (199.9.30.125.dy.iij4u.or.jp [125.30.9.199]) by mbox.po.2iij.net (po-mbox303) id n52EH7gQ031140 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NOT); Tue, 2 Jun 2009 23:17:08 +0900 Date: Tue, 2 Jun 2009 23:17:07 +0900 From: Yoichi Yuasa To: Ralf Baechle Cc: yoichi_yuasa@tripeaks.co.jp, linux-mips Subject: [PATCH][MIPS] PCI bus is always required for Cobalt ID Message-Id: <20090602231707.7bf24ee2.yoichi_yuasa@tripeaks.co.jp> Organization: TriPeaks Corporation X-Mailer: Sylpheed 2.5.0 (GTK+ 2.12.12; i486-pc-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23178 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: yoichi_yuasa@tripeaks.co.jp Precedence: bulk X-list: linux-mips Signed-off-by: Yoichi Yuasa diff -pruN -X /home/yuasa/Memo/dontdiff linux-orig/arch/mips/Kconfig linux/arch/mips/Kconfig --- linux-orig/arch/mips/Kconfig 2008-10-19 22:36:34.973823677 +0900 +++ linux/arch/mips/Kconfig 2008-10-19 22:33:58.440903373 +0900 @@ -72,6 +72,7 @@ config MIPS_COBALT select IRQ_CPU select IRQ_GT641XX select PCI_GT64XXX_PCI0 + select PCI select SYS_HAS_CPU_NEVADA select SYS_HAS_EARLY_PRINTK select SYS_SUPPORTS_32BIT_KERNEL From anemo@mba.ocn.ne.jp Tue Jun 2 15:54:28 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 02 Jun 2009 15:54:34 +0100 (WEST) Received: from mba.ocn.ne.jp ([122.1.235.107]:65513 "HELO smtp.mba.ocn.ne.jp" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with SMTP id S20022091AbZFBOy2 (ORCPT ); Tue, 2 Jun 2009 15:54:28 +0100 Received: from localhost.localdomain (p7143-ipad205funabasi.chiba.ocn.ne.jp [222.146.102.143]) by smtp.mba.ocn.ne.jp (Postfix) with ESMTP id 6C0BEABAD; Tue, 2 Jun 2009 23:54:23 +0900 (JST) From: Atsushi Nemoto To: linux-mips@linux-mips.org Cc: ralf@linux-mips.org, herbert@gondor.apana.org.au, mpm@selenic.com, linux-kernel@vger.kernel.org Subject: [PATCH] TXx9: Add TX4939 RNG support (v2) Date: Tue, 2 Jun 2009 23:54:22 +0900 Message-Id: <1243954462-18149-2-git-send-email-anemo@mba.ocn.ne.jp> X-Mailer: git-send-email 1.5.6.5 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23179 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anemo@mba.ocn.ne.jp Precedence: bulk X-list: linux-mips Add platform support for RNG of TX4939 SoC. Signed-off-by: Atsushi Nemoto --- Changes since v1: * Move TX4939_RNG_REG definition to tx4939.h arch/mips/include/asm/txx9/tx4939.h | 3 +++ arch/mips/txx9/generic/setup_tx4939.c | 17 +++++++++++++++++ arch/mips/txx9/rbtx4939/setup.c | 1 + 3 files changed, 21 insertions(+), 0 deletions(-) diff --git a/arch/mips/include/asm/txx9/tx4939.h b/arch/mips/include/asm/txx9/tx4939.h index 050364d..d4f342c 100644 --- a/arch/mips/include/asm/txx9/tx4939.h +++ b/arch/mips/include/asm/txx9/tx4939.h @@ -45,6 +45,8 @@ #define TX4939_RTC_REG (TX4939_REG_BASE + 0xfb00) #define TX4939_CIR_REG (TX4939_REG_BASE + 0xfc00) +#define TX4939_RNG_REG (TX4939_CRYPTO_REG + 0xb0) + struct tx4939_le_reg { __u32 r; __u32 unused; @@ -547,5 +549,6 @@ void tx4939_ndfmc_init(unsigned int hold, unsigned int spw, void tx4939_dmac_init(int memcpy_chan0, int memcpy_chan1); void tx4939_aclc_init(void); void tx4939_sramc_init(void); +void tx4939_rng_init(void); #endif /* __ASM_TXX9_TX4939_H */ diff --git a/arch/mips/txx9/generic/setup_tx4939.c b/arch/mips/txx9/generic/setup_tx4939.c index df13a89..3dc19f4 100644 --- a/arch/mips/txx9/generic/setup_tx4939.c +++ b/arch/mips/txx9/generic/setup_tx4939.c @@ -500,6 +500,23 @@ void __init tx4939_sramc_init(void) txx9_sramc_init(&tx4939_sram_resource); } +void __init tx4939_rng_init(void) +{ + static struct resource res = { + .start = TX4939_RNG_REG & 0xfffffffffULL, + .end = (TX4939_RNG_REG & 0xfffffffffULL) + 0x30 - 1, + .flags = IORESOURCE_MEM, + }; + static struct platform_device pdev = { + .name = "tx4939-rng", + .id = -1, + .num_resources = 1, + .resource = &res, + }; + + platform_device_register(&pdev); +} + static void __init tx4939_stop_unused_modules(void) { __u64 pcfg, rst = 0, ckd = 0; diff --git a/arch/mips/txx9/rbtx4939/setup.c b/arch/mips/txx9/rbtx4939/setup.c index b919696..c033ffe 100644 --- a/arch/mips/txx9/rbtx4939/setup.c +++ b/arch/mips/txx9/rbtx4939/setup.c @@ -502,6 +502,7 @@ static void __init rbtx4939_device_init(void) tx4939_aclc_init(); platform_device_register_simple("txx9aclc-generic", -1, NULL, 0); tx4939_sramc_init(); + tx4939_rng_init(); } static void __init rbtx4939_setup(void) -- 1.5.6.5 From anemo@mba.ocn.ne.jp Tue Jun 2 15:54:51 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 02 Jun 2009 15:54:58 +0100 (WEST) Received: from mba.ocn.ne.jp ([122.1.235.107]:65512 "HELO smtp.mba.ocn.ne.jp" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with SMTP id S20022084AbZFBOy2 (ORCPT ); Tue, 2 Jun 2009 15:54:28 +0100 Received: from localhost.localdomain (p7143-ipad205funabasi.chiba.ocn.ne.jp [222.146.102.143]) by smtp.mba.ocn.ne.jp (Postfix) with ESMTP id 02CDEABA9; Tue, 2 Jun 2009 23:54:23 +0900 (JST) From: Atsushi Nemoto To: linux-mips@linux-mips.org Cc: ralf@linux-mips.org, herbert@gondor.apana.org.au, mpm@selenic.com, linux-kernel@vger.kernel.org Subject: [PATCH] hwrng: Add TX4939 RNG driver (v2) Date: Tue, 2 Jun 2009 23:54:21 +0900 Message-Id: <1243954462-18149-1-git-send-email-anemo@mba.ocn.ne.jp> X-Mailer: git-send-email 1.5.6.5 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23180 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anemo@mba.ocn.ne.jp Precedence: bulk X-list: linux-mips This patch adds support for the integrated RNG of the TX4939 SoC. Signed-off-by: Atsushi Nemoto --- Changes since v1: * Wrap local_irq_enable/local_irq_disable * Add some comments * Rename tx4939_rng_init to tx4939rng_init drivers/char/hw_random/Kconfig | 13 +++ drivers/char/hw_random/Makefile | 1 + drivers/char/hw_random/tx4939-rng.c | 184 +++++++++++++++++++++++++++++++++++ 3 files changed, 198 insertions(+), 0 deletions(-) create mode 100644 drivers/char/hw_random/tx4939-rng.c diff --git a/drivers/char/hw_random/Kconfig b/drivers/char/hw_random/Kconfig index 5fab647..9d321cc 100644 --- a/drivers/char/hw_random/Kconfig +++ b/drivers/char/hw_random/Kconfig @@ -148,3 +148,16 @@ config HW_RANDOM_VIRTIO To compile this driver as a module, choose M here: the module will be called virtio-rng. If unsure, say N. + +config HW_RANDOM_TX4939 + tristate "TX4939 Random Number Generator support" + depends on HW_RANDOM && SOC_TX4939 + default HW_RANDOM + ---help--- + This driver provides kernel-side support for the Random Number + Generator hardware found on TX4939 SoC. + + To compile this driver as a module, choose M here: the + module will be called tx4939-rng. + + If unsure, say Y. diff --git a/drivers/char/hw_random/Makefile b/drivers/char/hw_random/Makefile index e81d21a..936d388 100644 --- a/drivers/char/hw_random/Makefile +++ b/drivers/char/hw_random/Makefile @@ -15,3 +15,4 @@ obj-$(CONFIG_HW_RANDOM_IXP4XX) += ixp4xx-rng.o obj-$(CONFIG_HW_RANDOM_OMAP) += omap-rng.o obj-$(CONFIG_HW_RANDOM_PASEMI) += pasemi-rng.o obj-$(CONFIG_HW_RANDOM_VIRTIO) += virtio-rng.o +obj-$(CONFIG_HW_RANDOM_TX4939) += tx4939-rng.o diff --git a/drivers/char/hw_random/tx4939-rng.c b/drivers/char/hw_random/tx4939-rng.c new file mode 100644 index 0000000..544d908 --- /dev/null +++ b/drivers/char/hw_random/tx4939-rng.c @@ -0,0 +1,184 @@ +/* + * RNG driver for TX4939 Random Number Generators (RNG) + * + * Copyright (C) 2009 Atsushi Nemoto + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#include +#include +#include +#include +#include +#include +#include + +#define TX4939_RNG_RCSR 0x00000000 +#define TX4939_RNG_ROR(n) (0x00000018 + (n) * 8) + +#define TX4939_RNG_RCSR_INTE 0x00000008 +#define TX4939_RNG_RCSR_RST 0x00000004 +#define TX4939_RNG_RCSR_FIN 0x00000002 +#define TX4939_RNG_RCSR_ST 0x00000001 + +struct tx4939_rng { + struct hwrng rng; + void __iomem *base; + u64 databuf[3]; + unsigned int data_avail; +}; + +static void rng_io_start(void) +{ +#ifndef CONFIG_64BIT + /* + * readq is reading a 64-bit register using a 64-bit load. On + * a 32-bit kernel however interrupts or any other processor + * exception would clobber the upper 32-bit of the processor + * register so interrupts need to be disabled. + */ + local_irq_disable(); +#endif +} + +static void rng_io_end(void) +{ +#ifndef CONFIG_64BIT + local_irq_enable(); +#endif +} + +static u64 read_rng(void __iomem *base, unsigned int offset) +{ + return ____raw_readq(base + offset); +} + +static void write_rng(u64 val, void __iomem *base, unsigned int offset) +{ + return ____raw_writeq(val, base + offset); +} + +static int tx4939_rng_data_present(struct hwrng *rng, int wait) +{ + struct tx4939_rng *rngdev = container_of(rng, struct tx4939_rng, rng); + int i; + + if (rngdev->data_avail) + return rngdev->data_avail; + for (i = 0; i < 20; i++) { + rng_io_start(); + if (!(read_rng(rngdev->base, TX4939_RNG_RCSR) + & TX4939_RNG_RCSR_ST)) { + rngdev->databuf[0] = + read_rng(rngdev->base, TX4939_RNG_ROR(0)); + rngdev->databuf[1] = + read_rng(rngdev->base, TX4939_RNG_ROR(1)); + rngdev->databuf[2] = + read_rng(rngdev->base, TX4939_RNG_ROR(2)); + rngdev->data_avail = + sizeof(rngdev->databuf) / sizeof(u32); + /* Start RNG */ + write_rng(TX4939_RNG_RCSR_ST, + rngdev->base, TX4939_RNG_RCSR); + wait = 0; + } + rng_io_end(); + if (!wait) + break; + /* 90 bus clock cycles by default for generation */ + ndelay(90 * 5); + } + return rngdev->data_avail; +} + +static int tx4939_rng_data_read(struct hwrng *rng, u32 *buffer) +{ + struct tx4939_rng *rngdev = container_of(rng, struct tx4939_rng, rng); + + rngdev->data_avail--; + *buffer = *((u32 *)&rngdev->databuf + rngdev->data_avail); + return sizeof(u32); +} + +static int __init tx4939_rng_probe(struct platform_device *dev) +{ + struct tx4939_rng *rngdev; + struct resource *r; + int i; + + r = platform_get_resource(dev, IORESOURCE_MEM, 0); + if (!r) + return -EBUSY; + rngdev = devm_kzalloc(&dev->dev, sizeof(*rngdev), GFP_KERNEL); + if (!rngdev) + return -ENOMEM; + if (!devm_request_mem_region(&dev->dev, r->start, resource_size(r), + dev_name(&dev->dev))) + return -EBUSY; + rngdev->base = devm_ioremap(&dev->dev, r->start, resource_size(r)); + if (!rngdev->base) + return -EBUSY; + + rngdev->rng.name = dev_name(&dev->dev); + rngdev->rng.data_present = tx4939_rng_data_present; + rngdev->rng.data_read = tx4939_rng_data_read; + + rng_io_start(); + /* Reset RNG */ + write_rng(TX4939_RNG_RCSR_RST, rngdev->base, TX4939_RNG_RCSR); + write_rng(0, rngdev->base, TX4939_RNG_RCSR); + /* Start RNG */ + write_rng(TX4939_RNG_RCSR_ST, rngdev->base, TX4939_RNG_RCSR); + rng_io_end(); + /* + * Drop first two results. From the datasheet: + * The quality of the random numbers generated immediately + * after reset can be insufficient. Therefore, do not use + * random numbers obtained from the first and second + * generations; use the ones from the third or subsequent + * generation. + */ + for (i = 0; i < 2; i++) { + rngdev->data_avail = 0; + if (!tx4939_rng_data_present(&rngdev->rng, 1)) + return -EIO; + } + + platform_set_drvdata(dev, rngdev); + return hwrng_register(&rngdev->rng); +} + +static int __exit tx4939_rng_remove(struct platform_device *dev) +{ + struct tx4939_rng *rngdev = platform_get_drvdata(dev); + + hwrng_unregister(&rngdev->rng); + platform_set_drvdata(dev, NULL); + return 0; +} + +static struct platform_driver tx4939_rng_driver = { + .driver = { + .name = "tx4939-rng", + .owner = THIS_MODULE, + }, + .remove = tx4939_rng_remove, +}; + +static int __init tx4939rng_init(void) +{ + return platform_driver_probe(&tx4939_rng_driver, tx4939_rng_probe); +} + +static void __exit tx4939rng_exit(void) +{ + platform_driver_unregister(&tx4939_rng_driver); +} + +module_init(tx4939rng_init); +module_exit(tx4939rng_exit); + +MODULE_DESCRIPTION("H/W Random Number Generator (RNG) driver for TX4939"); +MODULE_LICENSE("GPL"); -- 1.5.6.5 From wuzhangjin@gmail.com Tue Jun 2 16:32:03 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 02 Jun 2009 16:32:09 +0100 (WEST) Received: from mail-px0-f118.google.com ([209.85.216.118]:44316 "EHLO mail-px0-f118.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20022109AbZFBPcD (ORCPT ); Tue, 2 Jun 2009 16:32:03 +0100 Received: by pxi16 with SMTP id 16so283063pxi.22 for ; Tue, 02 Jun 2009 08:31:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer; bh=uLnTyx11glIoFnBOX7e73SacMfVzr3qzh9G1ScZavhE=; b=Ycr2GsUT08PQDYSlCYL6T93B2Yqqw9px4uYaofdYUyCd3mk7pyQBnzAdpeKcSDBNn3 x/V31sIbb4W0CdXLF/Jve5njUld1DIjgFQ9bkvZxPPlQotxFv5JXoY609ZT/KLbU67AY oKf7sZ98Kg4udnzqC+UuYXSAGK9v9z5+PuWug= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer; b=xzT9gbD3dhftb5Y3pD8JQE8jDzZNhHaCV5rUVJTiO7s7Q9LC15/ZCoSxiyRwJYf2GG bys7XbZBWZY8ZQo2pD2MSCRxNUOWmYL5sftR/axeLqRa0BwPP42wPuoH3Yzx2RhCS2IY Xp8lHYNMcyWl2okACuTVEyUv3W1rC48l/ZFY0= Received: by 10.114.160.17 with SMTP id i17mr6484314wae.125.1243956714197; Tue, 02 Jun 2009 08:31:54 -0700 (PDT) Received: from localhost.localdomain ([219.246.59.144]) by mx.google.com with ESMTPS id n9sm7152883wag.67.2009.06.02.08.31.49 (version=TLSv1/SSLv3 cipher=RC4-MD5); Tue, 02 Jun 2009 08:31:51 -0700 (PDT) From: wuzhangjin@gmail.com To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: Arnaud Patard , Atsushi Nemoto , yan hua , Zhang Fuxin , Pavel Machek , Wu Zhangjin , Hongbing Hu Subject: [PATCH] Hibernation Support in mips system Date: Tue, 2 Jun 2009 23:31:42 +0800 Message-Id: <1243956702-16276-1-git-send-email-wuzhangjin@gmail.com> X-Mailer: git-send-email 1.6.3.1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23181 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips From: Wu Zhangjin This is originally pulled from the to-mips branch of http://dev.lemote.com/code/linux_loongson, only a few coding style tuning under the support of script/checkpatch.pl as the feedback from Atsushi Nemoto,Yanhua and Pavel Machek, some changes have been done by Hu Hongbing(the original author of mips-specific STD) from Lemote.com. this patch apply the changes, which include: Reviewed-by: Pavel Machek Reviewed-by: yanh Reviewed-by: Arnaud Patard Reviewed-by: Atsushi Nemoto Signed-off-by: Wu Zhangjin Signed-off-by: Hongbing Hu --- arch/mips/Kconfig | 3 ++ arch/mips/Makefile | 3 ++ arch/mips/include/asm/suspend.h | 5 ++- arch/mips/kernel/asm-offsets.c | 13 +++++++ arch/mips/power/Makefile | 1 + arch/mips/power/cpu.c | 31 ++++++++++++++++++ arch/mips/power/hibernate.S | 67 +++++++++++++++++++++++++++++++++++++++ 7 files changed, 122 insertions(+), 1 deletions(-) create mode 100644 arch/mips/power/Makefile create mode 100644 arch/mips/power/cpu.c create mode 100644 arch/mips/power/hibernate.S diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index c7d1d08..4423d82 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -2128,6 +2128,9 @@ endmenu menu "Power management options" +config ARCH_HIBERNATION_POSSIBLE + def_bool y + config ARCH_SUSPEND_POSSIBLE def_bool y depends on !SMP diff --git a/arch/mips/Makefile b/arch/mips/Makefile index 6d39fdf..361a30d 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -685,6 +685,9 @@ core-y += arch/mips/kernel/ arch/mips/mm/ arch/mips/math-emu/ drivers-$(CONFIG_OPROFILE) += arch/mips/oprofile/ +# suspend and hibernation support +drivers-$(CONFIG_PM) += arch/mips/power/ + ifdef CONFIG_LASAT rom.bin rom.sw: vmlinux $(Q)$(MAKE) $(build)=arch/mips/lasat/image $@ diff --git a/arch/mips/include/asm/suspend.h b/arch/mips/include/asm/suspend.h index 2562f8f..294cdb6 100644 --- a/arch/mips/include/asm/suspend.h +++ b/arch/mips/include/asm/suspend.h @@ -1,6 +1,9 @@ #ifndef __ASM_SUSPEND_H #define __ASM_SUSPEND_H -/* Somewhen... Maybe :-) */ +static inline int arch_prepare_suspend(void) { return 0; } + +/* References to section boundaries */ +extern const void __nosave_begin, __nosave_end; #endif /* __ASM_SUSPEND_H */ diff --git a/arch/mips/kernel/asm-offsets.c b/arch/mips/kernel/asm-offsets.c index c901c22..8d006ec 100644 --- a/arch/mips/kernel/asm-offsets.c +++ b/arch/mips/kernel/asm-offsets.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include @@ -326,3 +327,15 @@ void output_octeon_cop2_state_defines(void) BLANK(); } #endif + +#ifdef CONFIG_HIBERNATION +void output_pbe_defines(void) +{ + COMMENT(" Linux struct pbe offsets. "); + OFFSET(PBE_ADDRESS, pbe, address); + OFFSET(PBE_ORIG_ADDRESS, pbe, orig_address); + OFFSET(PBE_NEXT, pbe, next); + DEFINE(PBE_SIZE, sizeof(struct pbe)); + BLANK(); +} +#endif diff --git a/arch/mips/power/Makefile b/arch/mips/power/Makefile new file mode 100644 index 0000000..73d56b8 --- /dev/null +++ b/arch/mips/power/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_HIBERNATION) += cpu.o hibernate.o diff --git a/arch/mips/power/cpu.c b/arch/mips/power/cpu.c new file mode 100644 index 0000000..5fe43e5 --- /dev/null +++ b/arch/mips/power/cpu.c @@ -0,0 +1,31 @@ +/* + * Suspend support specific for mips. + * + */ +#include +#include +#include +#include +#include +#include + +static uint32_t saved_status; +struct pt_regs saved_regs; + +void save_processor_state(void) +{ + saved_status = read_c0_status(); +} + +void restore_processor_state(void) +{ + write_c0_status(saved_status); +} + +int pfn_is_nosave(unsigned long pfn) +{ + unsigned long nosave_begin_pfn = PFN_DOWN(__pa(&__nosave_begin)); + unsigned long nosave_end_pfn = PFN_UP(__pa(&__nosave_end)); + + return (pfn >= nosave_begin_pfn) && (pfn < nosave_end_pfn); +} diff --git a/arch/mips/power/hibernate.S b/arch/mips/power/hibernate.S new file mode 100644 index 0000000..4ca9149 --- /dev/null +++ b/arch/mips/power/hibernate.S @@ -0,0 +1,67 @@ +#incldue +#include +#include +#include + + .extern __flush_cache_all +#ifdef CONFIG_SMP + .extern flush_tlb_all +#else + .extern local_flush_tlb_all +#define flush_tlb_all local_flush_tlb_all +#endif + +.text +LEAF(swsusp_arch_suspend) + PTR_LA t0, saved_regs + PTR_S ra, PT_R31(t0) + PTR_S sp, PT_R29(t0) + PTR_S fp, PT_R30(t0) + PTR_S gp, PT_R28(t0) + PTR_S s0, PT_R16(t0) + PTR_S s1, PT_R17(t0) + PTR_S s2, PT_R18(t0) + PTR_S s3, PT_R19(t0) + PTR_S s4, PT_R20(t0) + PTR_S s5, PT_R21(t0) + PTR_S s6, PT_R22(t0) + PTR_S s7, PT_R23(t0) + j swsusp_save +END(swsusp_arch_suspend) + +LEAF(swsusp_arch_resume) + PTR_L t0, restore_pblist +0: + PTR_L t1, PBE_ADDRESS(t0) /* source */ + PTR_L t2, PBE_ORIG_ADDRESS(t0) /* destination */ + PTR_ADDIU t3, t1, _PAGE_SIZE +1: + REG_L t8, (t1) + REG_S t8, (t2) + PTR_ADDIU t1, t1, SZREG + PTR_ADDIU t2, t2, SZREG + bne t1, t3, 1b + PTR_L t0, PBE_NEXT(t0) + bnez t0, 0b + /* flush caches to make sure context is in memory */ + PTR_L t0, __flush_cache_all + jalr t0 + /* flush tlb entries */ + PTR_LA t0, flush_tlb_all + jalr t0 + PTR_LA t0, saved_regs + PTR_L ra, PT_R31(t0) + PTR_L sp, PT_R29(t0) + PTR_L fp, PT_R30(t0) + PTR_L gp, PT_R28(t0) + PTR_L s0, PT_R16(t0) + PTR_L s1, PT_R17(t0) + PTR_L s2, PT_R18(t0) + PTR_L s3, PT_R19(t0) + PTR_L s4, PT_R20(t0) + PTR_L s5, PT_R21(t0) + PTR_L s6, PT_R22(t0) + PTR_L s7, PT_R23(t0) + PTR_LI v0, 0x0 + jr ra +END(swsusp_arch_resume) -- 1.6.0.4 From David.Daney@caviumnetworks.com Tue Jun 2 16:47:12 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 02 Jun 2009 16:47:18 +0100 (WEST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:58268 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20022112AbZFBPrM (ORCPT ); Tue, 2 Jun 2009 16:47:12 +0100 Received: from caexch01.caveonetworks.com (Not Verified[192.168.16.9]) by mail3.caviumnetworks.com with MailMarshal (v6,2,2,3503) id ; Tue, 02 Jun 2009 11:46:56 -0400 Received: from caexch01.caveonetworks.com ([192.168.16.9]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Tue, 2 Jun 2009 08:46:49 -0700 Received: from dd1.caveonetworks.com ([64.169.86.201]) by caexch01.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Tue, 2 Jun 2009 08:46:48 -0700 Message-ID: <4A254968.8090601@caviumnetworks.com> Date: Tue, 02 Jun 2009 08:46:48 -0700 From: David Daney User-Agent: Thunderbird 2.0.0.21 (X11/20090320) MIME-Version: 1.0 To: Yoichi Yuasa , Ralf Baechle CC: linux-mips Subject: Re: [PATCH][MIPS] remove "Support for" from Cavium system type References: <20090602231510.339c24a3.yoichi_yuasa@tripeaks.co.jp> In-Reply-To: <20090602231510.339c24a3.yoichi_yuasa@tripeaks.co.jp> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 02 Jun 2009 15:46:49.0008 (UTC) FILETIME=[573FF300:01C9E399] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23182 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Yoichi Yuasa wrote: > Signed-off-by: Yoichi Yuasa Acked-by: David Daney > > diff -pruN -X /home/yuasa/Memo/dontdiff linux-orig/arch/mips/Kconfig linux/arch/mips/Kconfig > --- linux-orig/arch/mips/Kconfig 2009-04-16 21:22:33.885188833 +0900 > +++ linux/arch/mips/Kconfig 2009-04-16 21:13:04.881168129 +0900 > @@ -593,7 +593,7 @@ config WR_PPMC > board, which is based on GT64120 bridge chip. > > config CAVIUM_OCTEON_SIMULATOR > - bool "Support for the Cavium Networks Octeon Simulator" > + bool "Cavium Networks Octeon Simulator" > select CEVT_R4K > select 64BIT_PHYS_ADDR > select DMA_COHERENT > @@ -607,7 +607,7 @@ config CAVIUM_OCTEON_SIMULATOR > hardware. > > config CAVIUM_OCTEON_REFERENCE_BOARD > - bool "Support for the Cavium Networks Octeon reference board" > + bool "Cavium Networks Octeon reference board" > select CEVT_R4K > select 64BIT_PHYS_ADDR > select DMA_COHERENT > > From wuzhangjin@gmail.com Tue Jun 2 17:15:44 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 02 Jun 2009 17:15:51 +0100 (WEST) Received: from an-out-0708.google.com ([209.85.132.244]:53292 "EHLO an-out-0708.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20022121AbZFBQPo (ORCPT ); Tue, 2 Jun 2009 17:15:44 +0100 Received: by an-out-0708.google.com with SMTP id c37so3864717anc.24 for ; Tue, 02 Jun 2009 09:15:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:in-reply-to:references :date:message-id:subject:from:to:cc:content-type :content-transfer-encoding; bh=wQyTLutCGHUPk5sLHUq9hZoYgD/iovYF5/Sm67Bjo2w=; b=j9W2Szru1b9kPxy7vLqj537Yr7k6cGHvEmmFnO0Gln029gQXgrpAQSGPmfb6OjLmPt fEH3dSZm1gfyuAm4LeISidomU7/CQwysTEmED5LWw0Mkix+MQ82770jVR5eomj17avui lQ5dQ5/KqZA37oJ63EnRA+uUUI5OcUlbGG43E= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type:content-transfer-encoding; b=rMtS4TfljHF2Hc8A8X4RWRsSxjnTpm7ecIoQAHEZcdVVOTQfzTM5CLTJgP2FJLffgQ VH/Ass61gQnXdZhPrNqbEADkYhUHbjG3/jqY0mOAl2t8J2LeChenLfoniQ9ZkJXWEmah fyRetmsxL+Jfu1VJluvWAEIy/LvBHTaPxkcys= MIME-Version: 1.0 Received: by 10.100.133.2 with SMTP id g2mr9304827and.23.1243959342461; Tue, 02 Jun 2009 09:15:42 -0700 (PDT) In-Reply-To: <4A22281B.7020908@windriver.com> References: <4A22281B.7020908@windriver.com> Date: Wed, 3 Jun 2009 00:15:42 +0800 Message-ID: Subject: Re: [PATCH v2 2/6] mips dynamic function tracer support From: wu zhangjin To: Wang Liming Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, Wu Zhangjin , Steven Rostedt , Ralf Baechle , Ingo Molnar , Andrew Morton , Frederic Weisbecker , Thomas Gleixner , Nicholas Mc Guire Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23183 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips hi, sorry, I'm so late to reply your E-mail, a little busy these days. On Sun, May 31, 2009 at 2:47 PM, Wang Liming wrote: > hi Wu, > > I have one question about dynamic ftrace support for modules on mips arch. > I have also ported a dynamic ftrace of mips before, but when I using modules > with dynamic ftrace enabled in mips, I have following error: > > # insmod ./usbcore > module usbcore: relocation overflow > insmod: cannot insert './usbcore.ko': invalid module format > # > > I have no time to test your patch, but I think your patch also has this > problem. > > Below I explain possibility of this problem in details: > > We know that on mips, kernel symbol will locate in 0x80000000~0x90000000, > and modules' symbol will locate in >0xc0000000. > > On mips, gcc will insert following assembler code before every functions: > > move at,ra > jal 0 > 10: R_MIPS_26 _mcount > > > Here "_mcount" is a kernel symbol in 0x80000000~0x90000000, for > example at 0x8027a740. > > When loading a module, kernel should relocate "jal 0" instruction to jump to > the kernel's "_mcount" address, 0x8027a740. But "jal 0" is a 26 bits offset > jump > instruction, it only can be relocated to jump to modules' symbol address > space(>0xc0000000) and it can't be relocated to jump to kernel symbol > address > space(such as 0x8027a740), because offset is 32 bits(is 0xc0000000 - > 0x80000000). We can't modify this instruction to jump to a 32 offset address > except that we modify gcc compiler to insert other assembler codes. > > So, when installing modules, the kernel will try to relocate "jal 0" > instruction > to instruction of jumping to >0xc0000000, but it finds that _mcount's > address > is 0x8027a740 and then print error indicated that it can't be reloacted. > > The following source code is the checking place: > > > ----------arch/mips/kernel/module.c:apply_r_mips_26_rel()------------------- > > static int apply_r_mips_26_rel(struct module *me, u32 *location, Elf_Addr v) > { > ... > if ((v & 0xf0000000) != (((unsigned long)location + 4) & 0xf0000000)) { > printk(KERN_ERR > "module %s: relocation overflow, v:%x, location:%x\n", > me->name, v, (unsigned long)location); > return -ENOEXEC; > } > > *location = (*location & ~0x03ffffff) | > ((*location + (v >> 2)) & 0x03ffffff); > > } > ----------arch/mips/kernel/module.c:apply_r_mips_26_rel()------------------- > > v is kernel _mcount's address, location is the address of the instrution > that should be relocated; > > To resolve this problem, we may need to do more work, either on gcc or on > the kernel. So I want to hear your test result and if you have solution, > please let me know. > yes, current version of mips-specific dynamic ftrace not support modules yet. there is similar solution implemented in PowerPC(something named trampoline), although I did not look into it, but I'm sure we can implement the mips-specific one via imitating it. and currently, I'm planning to fix it in the -v3 of mips-specific ftrace support. best wishes, Wu Zhangjin From ralf@h5.dl5rb.org.uk Tue Jun 2 18:53:11 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 02 Jun 2009 18:53:18 +0100 (WEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:45355 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20021336AbZFBRxL (ORCPT ); Tue, 2 Jun 2009 18:53:11 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id n52HqmSx004786; Tue, 2 Jun 2009 18:52:48 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id n52HqlfH004784; Tue, 2 Jun 2009 18:52:47 +0100 Date: Tue, 2 Jun 2009 18:52:47 +0100 From: Ralf Baechle To: Imre Kaloz Cc: linux-mips@linux-mips.org Subject: Re: [PATCH] Remove SiByte simulator option Message-ID: <20090602175247.GC32078@linux-mips.org> References: <1243945320-4964-1-git-send-email-kaloz@openwrt.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1243945320-4964-1-git-send-email-kaloz@openwrt.org> User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23184 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Tue, Jun 02, 2009 at 02:22:00PM +0200, Imre Kaloz wrote: > This patch removes the SiByte simulation Kconfig option, which only > modified a printk. Thanks, applied. Ralf From ralf@h5.dl5rb.org.uk Tue Jun 2 18:53:45 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 02 Jun 2009 18:53:52 +0100 (WEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:45358 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20021336AbZFBRxp (ORCPT ); Tue, 2 Jun 2009 18:53:45 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id n52HrM8X004792; Tue, 2 Jun 2009 18:53:22 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id n52HrMwd004791; Tue, 2 Jun 2009 18:53:22 +0100 Date: Tue, 2 Jun 2009 18:53:22 +0100 From: Ralf Baechle To: Imre Kaloz Cc: linux-mips@linux-mips.org Subject: Re: [PATCH] Remove standalone SiByte kernel support Message-ID: <20090602175322.GD32078@linux-mips.org> References: <1243945326-5029-1-git-send-email-kaloz@openwrt.org> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <1243945326-5029-1-git-send-email-kaloz@openwrt.org> User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23185 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Tue, Jun 02, 2009 at 02:22:06PM +0200, Imre Kaloz wrote: > CFE is the only supported and used bootloader on the SiByte boards, > the standalone kernel support has been never used outside Broadcom. > Remove it and make the kernel use CFE by default. Applied. Kösönöm! Ralf From ralf@h5.dl5rb.org.uk Tue Jun 2 18:59:50 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 02 Jun 2009 18:59:57 +0100 (WEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:45716 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20022186AbZFBR7u (ORCPT ); Tue, 2 Jun 2009 18:59:50 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id n52HxRUw005119; Tue, 2 Jun 2009 18:59:27 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id n52HxR3c005117; Tue, 2 Jun 2009 18:59:27 +0100 Date: Tue, 2 Jun 2009 18:59:27 +0100 From: Ralf Baechle To: Imre Kaloz Cc: linux-mips@linux-mips.org Subject: Re: [PATCH] Honor CONFIG_CMDLINE on SiByte Message-ID: <20090602175927.GE32078@linux-mips.org> References: <1243945334-5090-1-git-send-email-kaloz@openwrt.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1243945334-5090-1-git-send-email-kaloz@openwrt.org> User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23186 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Tue, Jun 02, 2009 at 02:22:14PM +0200, Imre Kaloz wrote: > The SiByte platform code doesn't honor the CONFIG_CMDLINE kernel > option. This patch fixes this issue. > > Signed-off-by: Imre Kaloz > --- > arch/mips/sibyte/common/cfe.c | 4 ++++ > 1 files changed, 4 insertions(+), 0 deletions(-) > > diff --git a/arch/mips/sibyte/common/cfe.c b/arch/mips/sibyte/common/cfe.c > index 3de30f7..97e997e 100644 > --- a/arch/mips/sibyte/common/cfe.c > +++ b/arch/mips/sibyte/common/cfe.c > @@ -293,7 +293,11 @@ void __init prom_init(void) > * It's OK for direct boot to not provide a > * command line > */ > +#ifdef CONFIG_CMDLINE > + strlcpy(arcs_cmdline, CONFIG_CMDLINE, COMMAND_LINE_SIZE); > +#else > strcpy(arcs_cmdline, "root=/dev/ram0 "); > +#endif I rather think the strcpy should go instead. Hardwiring an option doesn't seem a good idea. Ralf From mpm@selenic.com Tue Jun 2 21:13:56 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 02 Jun 2009 21:14:06 +0100 (WEST) Received: from waste.org ([66.93.16.53]:46555 "EHLO waste.org" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20022117AbZFBUN4 (ORCPT ); Tue, 2 Jun 2009 21:13:56 +0100 Received: from [192.168.1.100] ([10.0.0.101]) (authenticated bits=0) by waste.org (8.13.8/8.13.8/Debian-3) with ESMTP id n52KDAnN001074 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NOT); Tue, 2 Jun 2009 15:13:11 -0500 Subject: Re: [PATCH] hwrng: Add TX4939 RNG driver (v2) From: Matt Mackall To: Atsushi Nemoto Cc: linux-mips@linux-mips.org, ralf@linux-mips.org, herbert@gondor.apana.org.au, linux-kernel@vger.kernel.org In-Reply-To: <1243954462-18149-1-git-send-email-anemo@mba.ocn.ne.jp> References: <1243954462-18149-1-git-send-email-anemo@mba.ocn.ne.jp> Content-Type: text/plain Date: Tue, 02 Jun 2009 15:13:04 -0500 Message-Id: <1243973584.22069.182.camel@calx> Mime-Version: 1.0 X-Mailer: Evolution 2.26.1.1 Content-Transfer-Encoding: 7bit X-Virus-Scanned: by amavisd-new Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23187 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mpm@selenic.com Precedence: bulk X-list: linux-mips On Tue, 2009-06-02 at 23:54 +0900, Atsushi Nemoto wrote: > This patch adds support for the integrated RNG of the TX4939 SoC. > > Signed-off-by: Atsushi Nemoto Acked-by: Matt Mackall -- http://selenic.com : development and support for Mercurial and Linux From max@sakura.staff.proxad.net Wed Jun 3 00:47:42 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 03 Jun 2009 00:47:50 +0100 (WEST) Received: from sakura.staff.proxad.net ([213.228.1.107]:54287 "EHLO sakura.staff.proxad.net" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20021937AbZFBXrm (ORCPT ); Wed, 3 Jun 2009 00:47:42 +0100 Received: by sakura.staff.proxad.net (Postfix, from userid 1000) id 28A7A112406C; Wed, 3 Jun 2009 01:47:37 +0200 (CEST) From: Maxime Bizon To: linux-mips@linux-mips.org, Ralf Baechle Cc: Florian Fainelli , Maxime Bizon Subject: [PATCH 1/3] bcm63xx: don't use BUS_ID_SIZE in bcm63xx_enet. Date: Wed, 3 Jun 2009 01:47:35 +0200 Message-Id: <1243986457-27088-2-git-send-email-mbizon@freebox.fr> X-Mailer: git-send-email 1.6.0.4 In-Reply-To: <1243986457-27088-1-git-send-email-mbizon@freebox.fr> References: <1243986457-27088-1-git-send-email-mbizon@freebox.fr> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23188 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mbizon@freebox.fr Precedence: bulk X-list: linux-mips Networking recently got rid of BUS_ID_SIZE. Use MII_BUS_ID_SIZE instead in bcm63xx_enet. Signed-off-by: Maxime Bizon --- drivers/net/bcm63xx_enet.c | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/bcm63xx_enet.c b/drivers/net/bcm63xx_enet.c index 36324b3..af0114a 100644 --- a/drivers/net/bcm63xx_enet.c +++ b/drivers/net/bcm63xx_enet.c @@ -793,7 +793,7 @@ static int bcm_enet_open(struct net_device *dev) struct phy_device *phydev; int i, ret; unsigned int size; - char phy_id[BUS_ID_SIZE]; + char phy_id[MII_BUS_ID_SIZE + 3]; void *p; u32 val; @@ -802,7 +802,7 @@ static int bcm_enet_open(struct net_device *dev) if (priv->has_phy) { /* connect to PHY */ - snprintf(phy_id, BUS_ID_SIZE, PHY_ID_FMT, + snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT, priv->mac_id ? "1" : "0", priv->phy_id); phydev = phy_connect(dev, phy_id, &bcm_enet_adjust_phy_link, 0, -- 1.6.0.4 From max@sakura.staff.proxad.net Wed Jun 3 00:48:07 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 03 Jun 2009 00:48:14 +0100 (WEST) Received: from sakura.staff.proxad.net ([213.228.1.107]:54286 "EHLO sakura.staff.proxad.net" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20022103AbZFBXrm (ORCPT ); Wed, 3 Jun 2009 00:47:42 +0100 Received: by sakura.staff.proxad.net (Postfix, from userid 1000) id 17B89112408A; Wed, 3 Jun 2009 01:47:37 +0200 (CEST) From: Maxime Bizon To: linux-mips@linux-mips.org, Ralf Baechle Cc: Florian Fainelli Subject: More updates to bcm63xx Date: Wed, 3 Jun 2009 01:47:34 +0200 Message-Id: <1243986457-27088-1-git-send-email-mbizon@freebox.fr> X-Mailer: git-send-email 1.6.0.4 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23189 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mbizon@freebox.fr Precedence: bulk X-list: linux-mips Hi Ralf, Could you please fold the following patches in the bcm63xx tree ? Thanks, From max@sakura.staff.proxad.net Wed Jun 3 00:48:31 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 03 Jun 2009 00:48:39 +0100 (WEST) Received: from sakura.staff.proxad.net ([213.228.1.107]:54293 "EHLO sakura.staff.proxad.net" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20022121AbZFBXrm (ORCPT ); Wed, 3 Jun 2009 00:47:42 +0100 Received: by sakura.staff.proxad.net (Postfix, from userid 1000) id 30307112408D; Wed, 3 Jun 2009 01:47:37 +0200 (CEST) From: Maxime Bizon To: linux-mips@linux-mips.org, Ralf Baechle Cc: Florian Fainelli , Maxime Bizon Subject: [PATCH 3/3] bcm63xx: use NET_IP_ALIGN Date: Wed, 3 Jun 2009 01:47:37 +0200 Message-Id: <1243986457-27088-4-git-send-email-mbizon@freebox.fr> X-Mailer: git-send-email 1.6.0.4 In-Reply-To: <1243986457-27088-1-git-send-email-mbizon@freebox.fr> References: <1243986457-27088-1-git-send-email-mbizon@freebox.fr> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23190 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mbizon@freebox.fr Precedence: bulk X-list: linux-mips Replace hardcoded 2 with NET_IP_ALIGN. Signed-off-by: Maxime Bizon --- drivers/net/bcm63xx_enet.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/drivers/net/bcm63xx_enet.c b/drivers/net/bcm63xx_enet.c index 322ed03..660ffa2 100644 --- a/drivers/net/bcm63xx_enet.c +++ b/drivers/net/bcm63xx_enet.c @@ -320,7 +320,7 @@ static int bcm_enet_receive_queue(struct net_device *dev, int budget) if (len < copybreak) { struct sk_buff *nskb; - nskb = netdev_alloc_skb(dev, len + 2); + nskb = netdev_alloc_skb(dev, len + NET_IP_ALIGN); if (!nskb) { /* forget packet, just rearm desc */ priv->stats.rx_dropped++; -- 1.6.0.4 From max@sakura.staff.proxad.net Wed Jun 3 00:48:56 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 03 Jun 2009 00:49:04 +0100 (WEST) Received: from sakura.staff.proxad.net ([213.228.1.107]:54290 "EHLO sakura.staff.proxad.net" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20022109AbZFBXrn (ORCPT ); Wed, 3 Jun 2009 00:47:43 +0100 Received: by sakura.staff.proxad.net (Postfix, from userid 1000) id 2BA59112408B; Wed, 3 Jun 2009 01:47:37 +0200 (CEST) From: Maxime Bizon To: linux-mips@linux-mips.org, Ralf Baechle Cc: Florian Fainelli , Maxime Bizon Subject: [PATCH 2/3] bcm63xx: make it possible to change MTU on bcm63xx_enet. Date: Wed, 3 Jun 2009 01:47:36 +0200 Message-Id: <1243986457-27088-3-git-send-email-mbizon@freebox.fr> X-Mailer: git-send-email 1.6.0.4 In-Reply-To: <1243986457-27088-1-git-send-email-mbizon@freebox.fr> References: <1243986457-27088-1-git-send-email-mbizon@freebox.fr> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23191 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mbizon@freebox.fr Precedence: bulk X-list: linux-mips bcm63xx integrated ethernet mac supports receiving and sending frames bigger than 1500 bytes, this patch adds support for changing MTU. This patch also fixes the reception of 802.1q frames for default MTU which were reported as oversized. Signed-off-by: Maxime Bizon --- drivers/net/bcm63xx_enet.c | 71 +++++++++++++++++++++++++++++++++++++++----- drivers/net/bcm63xx_enet.h | 15 +++++++-- 2 files changed, 75 insertions(+), 11 deletions(-) diff --git a/drivers/net/bcm63xx_enet.c b/drivers/net/bcm63xx_enet.c index af0114a..322ed03 100644 --- a/drivers/net/bcm63xx_enet.c +++ b/drivers/net/bcm63xx_enet.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include "bcm63xx_enet.h" @@ -189,18 +190,18 @@ static int bcm_enet_refill_rx(struct net_device *dev) desc = &priv->rx_desc_cpu[desc_idx]; if (!priv->rx_skb[desc_idx]) { - skb = netdev_alloc_skb(dev, BCMENET_MAX_RX_SIZE); + skb = netdev_alloc_skb(dev, priv->rx_skb_size); if (!skb) break; priv->rx_skb[desc_idx] = skb; p = dma_map_single(&priv->pdev->dev, skb->data, - BCMENET_MAX_RX_SIZE, + priv->rx_skb_size, DMA_FROM_DEVICE); desc->address = p; } - len_stat = BCMENET_MAX_RX_SIZE << DMADESC_LENGTH_SHIFT; + len_stat = priv->rx_skb_size << DMADESC_LENGTH_SHIFT; len_stat |= DMADESC_OWNER_MASK; if (priv->rx_dirty_desc == priv->rx_ring_size - 1) { len_stat |= DMADESC_WRAP_MASK; @@ -337,7 +338,7 @@ static int bcm_enet_receive_queue(struct net_device *dev, int budget) skb = nskb; } else { dma_unmap_single(&priv->pdev->dev, desc->address, - BCMENET_MAX_RX_SIZE, DMA_FROM_DEVICE); + priv->rx_skb_size, DMA_FROM_DEVICE); priv->rx_skb[desc_idx] = NULL; } @@ -943,8 +944,8 @@ static int bcm_enet_open(struct net_device *dev) enet_dma_writel(priv, 0, ENETDMA_SRAM4_REG(priv->tx_chan)); /* set max rx/tx length */ - enet_writel(priv, BCMENET_MAX_RX_SIZE, ENET_RXMAXLEN_REG); - enet_writel(priv, BCMENET_MAX_TX_SIZE, ENET_TXMAXLEN_REG); + enet_writel(priv, priv->hw_mtu, ENET_RXMAXLEN_REG); + enet_writel(priv, priv->hw_mtu, ENET_TXMAXLEN_REG); /* set dma maximum burst len */ enet_dma_writel(priv, BCMENET_DMA_MAXBURST, @@ -1003,7 +1004,7 @@ out: continue; desc = &priv->rx_desc_cpu[i]; - dma_unmap_single(kdev, desc->address, BCMENET_MAX_RX_SIZE, + dma_unmap_single(kdev, desc->address, priv->rx_skb_size, DMA_FROM_DEVICE); kfree_skb(priv->rx_skb[i]); } @@ -1120,7 +1121,7 @@ static int bcm_enet_stop(struct net_device *dev) continue; desc = &priv->rx_desc_cpu[i]; - dma_unmap_single(kdev, desc->address, BCMENET_MAX_RX_SIZE, + dma_unmap_single(kdev, desc->address, priv->rx_skb_size, DMA_FROM_DEVICE); kfree_skb(priv->rx_skb[i]); } @@ -1510,6 +1511,55 @@ static int bcm_enet_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) } /* + * calculate actual hardware mtu + */ +static int compute_hw_mtu(struct bcm_enet_priv *priv, int mtu) +{ + int actual_mtu; + + actual_mtu = mtu; + + /* add ethernet header + vlan tag size */ + actual_mtu += VLAN_ETH_HLEN; + + if (actual_mtu < 64 || actual_mtu > BCMENET_MAX_MTU) + return -EINVAL; + + /* + * setup maximum size before we get overflow mark in + * descriptor, note that this will not prevent reception of + * big frames, they will be split into multiple buffers + * anyway + */ + priv->hw_mtu = actual_mtu; + + /* + * align rx buffer size to dma burst len, account FCS since + * it's appended + */ + priv->rx_skb_size = ALIGN(actual_mtu + ETH_FCS_LEN, + BCMENET_DMA_MAXBURST * 4); + return 0; +} + +/* + * adjust mtu, can't be called while device is running + */ +static int bcm_enet_change_mtu(struct net_device *dev, int new_mtu) +{ + int ret; + + if (netif_running(dev)) + return -EBUSY; + + ret = compute_hw_mtu(netdev_priv(dev), new_mtu); + if (ret) + return ret; + dev->mtu = new_mtu; + return 0; +} + +/* * preinit hardware to allow mii operation while device is down */ static void bcm_enet_hw_preinit(struct bcm_enet_priv *priv) @@ -1559,6 +1609,7 @@ static const struct net_device_ops bcm_enet_ops = { .ndo_set_mac_address = bcm_enet_set_mac_address, .ndo_set_multicast_list = bcm_enet_set_multicast_list, .ndo_do_ioctl = bcm_enet_ioctl, + .ndo_change_mtu = bcm_enet_change_mtu, #ifdef CONFIG_NET_POLL_CONTROLLER .ndo_poll_controller = bcm_enet_netpoll, #endif @@ -1597,6 +1648,10 @@ static int __devinit bcm_enet_probe(struct platform_device *pdev) priv = netdev_priv(dev); memset(priv, 0, sizeof(*priv)); + ret = compute_hw_mtu(priv, dev->mtu); + if (ret) + goto out; + iomem_size = res_mem->end - res_mem->start + 1; if (!request_mem_region(res_mem->start, iomem_size, "bcm63xx_enet")) { ret = -EBUSY; diff --git a/drivers/net/bcm63xx_enet.h b/drivers/net/bcm63xx_enet.h index 0da8973..bd3684d 100644 --- a/drivers/net/bcm63xx_enet.h +++ b/drivers/net/bcm63xx_enet.h @@ -23,9 +23,12 @@ * not overflow the fifo */ #define BCMENET_TX_FIFO_TRESH 32 -/* maximum rx/tx packet size */ -#define BCMENET_MAX_RX_SIZE (ETH_FRAME_LEN + 4) -#define BCMENET_MAX_TX_SIZE (ETH_FRAME_LEN + 4) +/* + * hardware maximum rx/tx packet size including FCS, max mtu is + * actually 2047, but if we set max rx size register to 2047 we won't + * get overflow information if packet size is 2048 or above + */ +#define BCMENET_MAX_MTU 2046 /* * rx/tx dma descriptor @@ -202,6 +205,9 @@ struct bcm_enet_priv { /* next dirty rx descriptor to refill */ int rx_dirty_desc; + /* size of allocated rx skbs */ + unsigned int rx_skb_size; + /* list of skb given to hw for rx */ struct sk_buff **rx_skb; @@ -289,6 +295,9 @@ struct bcm_enet_priv { /* platform device reference */ struct platform_device *pdev; + + /* maximum hardware transmit/receive size */ + unsigned int hw_mtu; }; #endif /* ! BCM63XX_ENET_H_ */ -- 1.6.0.4 From ralf@h5.dl5rb.org.uk Wed Jun 3 07:06:53 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 03 Jun 2009 07:07:01 +0100 (WEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:54849 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20022374AbZFCGGx (ORCPT ); Wed, 3 Jun 2009 07:06:53 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id n5366TGv024411; Wed, 3 Jun 2009 07:06:29 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id n5366TZM024409; Wed, 3 Jun 2009 07:06:29 +0100 Date: Wed, 3 Jun 2009 07:06:29 +0100 From: Ralf Baechle To: Maxime Bizon Cc: linux-mips@linux-mips.org, Florian Fainelli Subject: Re: More updates to bcm63xx Message-ID: <20090603060629.GA23561@linux-mips.org> References: <1243986457-27088-1-git-send-email-mbizon@freebox.fr> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1243986457-27088-1-git-send-email-mbizon@freebox.fr> User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23192 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Wed, Jun 03, 2009 at 01:47:34AM +0200, Maxime Bizon wrote: > Could you please fold the following patches in the bcm63xx tree ? Thanks, all three folded into the bcm63xx tree. Ralf From liming.wang@windriver.com Wed Jun 3 07:16:57 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 03 Jun 2009 07:17:03 +0100 (WEST) Received: from mail.windriver.com ([147.11.1.11]:43493 "EHLO mail.wrs.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20022452AbZFCGQ5 (ORCPT ); Wed, 3 Jun 2009 07:16:57 +0100 Received: from ALA-MAIL03.corp.ad.wrs.com (ala-mail03 [147.11.57.144]) by mail.wrs.com (8.13.6/8.13.6) with ESMTP id n536FXqO006142; Tue, 2 Jun 2009 23:15:33 -0700 (PDT) Received: from ala-mail06.corp.ad.wrs.com ([147.11.57.147]) by ALA-MAIL03.corp.ad.wrs.com with Microsoft SMTPSVC(6.0.3790.1830); Tue, 2 Jun 2009 23:15:32 -0700 Received: from [128.224.162.180] ([128.224.162.180]) by ala-mail06.corp.ad.wrs.com with Microsoft SMTPSVC(6.0.3790.1830); Tue, 2 Jun 2009 23:15:33 -0700 Message-ID: <4A26129E.1080008@windriver.com> Date: Wed, 03 Jun 2009 14:05:18 +0800 From: Wang Liming User-Agent: Thunderbird 2.0.0.21 (Windows/20090302) MIME-Version: 1.0 To: wu zhangjin CC: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, Wu Zhangjin , Steven Rostedt , Ralf Baechle , Ingo Molnar , Andrew Morton , Frederic Weisbecker , Thomas Gleixner , Nicholas Mc Guire Subject: Re: [PATCH v2 2/6] mips dynamic function tracer support References: <4A22281B.7020908@windriver.com> In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 03 Jun 2009 06:15:33.0455 (UTC) FILETIME=[B3D75DF0:01C9E412] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23193 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: liming.wang@windriver.com Precedence: bulk X-list: linux-mips wu zhangjin wrote: > hi, > > sorry, I'm so late to reply your E-mail, a little busy these days. >> >> } >> ----------arch/mips/kernel/module.c:apply_r_mips_26_rel()------------------- >> >> v is kernel _mcount's address, location is the address of the instrution >> that should be relocated; >> >> To resolve this problem, we may need to do more work, either on gcc or on >> the kernel. So I want to hear your test result and if you have solution, >> please let me know. >> > > yes, current version of mips-specific dynamic ftrace not support modules yet. > > there is similar solution implemented in PowerPC(something named trampoline), > although I did not look into it, but I'm sure we can implement the > mips-specific one > via imitating it. Good hit. I may have a look on Powerpc implementation. > > and currently, I'm planning to fix it in the -v3 of mips-specific > ftrace support. OK. I'm looking forward to your -v3 patches. Thanks. Liming Wang > > best wishes, > Wu Zhangjin > From ralf@h5.dl5rb.org.uk Wed Jun 3 09:58:40 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 03 Jun 2009 09:58:47 +0100 (WEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:49718 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20021325AbZFCI6k (ORCPT ); Wed, 3 Jun 2009 09:58:40 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id n538wGf0030406; Wed, 3 Jun 2009 09:58:16 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id n538wGrl030404; Wed, 3 Jun 2009 09:58:16 +0100 Date: Wed, 3 Jun 2009 09:58:16 +0100 From: Ralf Baechle To: Atsushi Nemoto Cc: linux-mips@linux-mips.org Subject: Re: [PATCH] TXx9: Add SRAMC support Message-ID: <20090603085816.GG23561@linux-mips.org> References: <1243256642-4880-1-git-send-email-anemo@mba.ocn.ne.jp> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1243256642-4880-1-git-send-email-anemo@mba.ocn.ne.jp> User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23194 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Mon, May 25, 2009 at 10:04:02PM +0900, Atsushi Nemoto wrote: > Add a sysdev to access SRAM in TXx9 SoCs via sysfs. Queued for 2.6.31. Thanks, Ralf From ralf@h5.dl5rb.org.uk Wed Jun 3 10:03:09 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 03 Jun 2009 10:03:16 +0100 (WEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:33114 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20022544AbZFCJDJ (ORCPT ); Wed, 3 Jun 2009 10:03:09 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id n5392eFn031999; Wed, 3 Jun 2009 10:02:40 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id n5392cLD031997; Wed, 3 Jun 2009 10:02:38 +0100 Date: Wed, 3 Jun 2009 10:02:38 +0100 From: Ralf Baechle To: Matt Mackall Cc: Atsushi Nemoto , linux-mips@linux-mips.org, herbert@gondor.apana.org.au, linux-kernel@vger.kernel.org Subject: Re: [PATCH] hwrng: Add TX4939 RNG driver (v2) Message-ID: <20090603090238.GH23561@linux-mips.org> References: <1243954462-18149-1-git-send-email-anemo@mba.ocn.ne.jp> <1243973584.22069.182.camel@calx> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1243973584.22069.182.camel@calx> User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23195 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Tue, Jun 02, 2009 at 03:13:04PM -0500, Matt Mackall wrote: > On Tue, 2009-06-02 at 23:54 +0900, Atsushi Nemoto wrote: > > This patch adds support for the integrated RNG of the TX4939 SoC. > > > > Signed-off-by: Atsushi Nemoto > > Acked-by: Matt Mackall Ok, I'll send this to Linus for 2.6.31 then. Thanks, Ralf From ralf@h5.dl5rb.org.uk Wed Jun 3 10:18:59 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 03 Jun 2009 10:19:08 +0100 (WEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:32779 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20021958AbZFCJS7 (ORCPT ); Wed, 3 Jun 2009 10:18:59 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id n539IZKr005350; Wed, 3 Jun 2009 10:18:36 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id n539IYVG005348; Wed, 3 Jun 2009 10:18:34 +0100 Date: Wed, 3 Jun 2009 10:18:34 +0100 From: Ralf Baechle To: Yoichi Yuasa Cc: linux-mips Subject: Re: [PATCH][MIPS] remove "Support for" from Cavium system type Message-ID: <20090603091834.GI23561@linux-mips.org> References: <20090602231510.339c24a3.yoichi_yuasa@tripeaks.co.jp> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20090602231510.339c24a3.yoichi_yuasa@tripeaks.co.jp> User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23196 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Tue, Jun 02, 2009 at 11:15:10PM +0900, Yoichi Yuasa wrote: Thanks, Yoichi-San, applied. Ralf From herbert@gondor.apana.org.au Wed Jun 3 10:26:26 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 03 Jun 2009 10:26:33 +0100 (WEST) Received: from rhun.apana.org.au ([64.62.148.172]:35159 "EHLO arnor.apana.org.au" rhost-flags-OK-OK-OK-FAIL) by ftp.linux-mips.org with ESMTP id S20022575AbZFCJ00 (ORCPT ); Wed, 3 Jun 2009 10:26:26 +0100 Received: from gondolin.me.apana.org.au ([192.168.0.6]) by arnor.apana.org.au with esmtp (Exim 4.63 #1 (Debian)) id 1MBmjg-0007Ub-PX; Wed, 03 Jun 2009 19:26:17 +1000 Received: from herbert by gondolin.me.apana.org.au with local (Exim 4.69) (envelope-from ) id 1MBmja-0002vr-Pq; Wed, 03 Jun 2009 19:26:10 +1000 Date: Wed, 3 Jun 2009 19:26:10 +1000 From: Herbert Xu To: Ralf Baechle Cc: Matt Mackall , Atsushi Nemoto , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] hwrng: Add TX4939 RNG driver (v2) Message-ID: <20090603092610.GA11258@gondor.apana.org.au> References: <1243954462-18149-1-git-send-email-anemo@mba.ocn.ne.jp> <1243973584.22069.182.camel@calx> <20090603090238.GH23561@linux-mips.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20090603090238.GH23561@linux-mips.org> User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23197 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: herbert@gondor.apana.org.au Precedence: bulk X-list: linux-mips On Wed, Jun 03, 2009 at 10:02:38AM +0100, Ralf Baechle wrote: > On Tue, Jun 02, 2009 at 03:13:04PM -0500, Matt Mackall wrote: > > > On Tue, 2009-06-02 at 23:54 +0900, Atsushi Nemoto wrote: > > > This patch adds support for the integrated RNG of the TX4939 SoC. > > > > > > Signed-off-by: Atsushi Nemoto > > > > Acked-by: Matt Mackall > > Ok, I'll send this to Linus for 2.6.31 then. Actually I've already added it to my tree since I'm looking after the hwrng drivers. Thanks, -- Visit Openswan at http://www.openswan.org/ Email: Herbert Xu ~{PmV>HI~} Home Page: http://gondor.apana.org.au/~herbert/ PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt From herbert@gondor.apana.org.au Wed Jun 3 10:29:37 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 03 Jun 2009 10:29:43 +0100 (WEST) Received: from rhun.apana.org.au ([64.62.148.172]:35172 "EHLO arnor.apana.org.au" rhost-flags-OK-OK-OK-FAIL) by ftp.linux-mips.org with ESMTP id S20022566AbZFCJ3h (ORCPT ); Wed, 3 Jun 2009 10:29:37 +0100 Received: from gondolin.me.apana.org.au ([192.168.0.6]) by arnor.apana.org.au with esmtp (Exim 4.63 #1 (Debian)) id 1MBmmn-0007XY-Co; Wed, 03 Jun 2009 19:29:29 +1000 Received: from herbert by gondolin.me.apana.org.au with local (Exim 4.69) (envelope-from ) id 1MBmml-0002xd-KX; Wed, 03 Jun 2009 19:29:27 +1000 Date: Wed, 3 Jun 2009 19:29:27 +1000 From: Herbert Xu To: Ralf Baechle Cc: Matt Mackall , Atsushi Nemoto , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] hwrng: Add TX4939 RNG driver (v2) Message-ID: <20090603092927.GA11369@gondor.apana.org.au> References: <1243954462-18149-1-git-send-email-anemo@mba.ocn.ne.jp> <1243973584.22069.182.camel@calx> <20090603090238.GH23561@linux-mips.org> <20090603092610.GA11258@gondor.apana.org.au> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20090603092610.GA11258@gondor.apana.org.au> User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23198 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: herbert@gondor.apana.org.au Precedence: bulk X-list: linux-mips On Wed, Jun 03, 2009 at 07:26:10PM +1000, Herbert Xu wrote: > On Wed, Jun 03, 2009 at 10:02:38AM +0100, Ralf Baechle wrote: > > > Ok, I'll send this to Linus for 2.6.31 then. > > Actually I've already added it to my tree since I'm looking after > the hwrng drivers. But if this causes any conflicts for you, then please let me know and I'll back it out. Cheers, -- Visit Openswan at http://www.openswan.org/ Email: Herbert Xu ~{PmV>HI~} Home Page: http://gondor.apana.org.au/~herbert/ PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt From herbert@gondor.apana.org.au Wed Jun 3 10:44:59 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 03 Jun 2009 10:45:06 +0100 (WEST) Received: from rhun.apana.org.au ([64.62.148.172]:50820 "EHLO arnor.apana.org.au" rhost-flags-OK-OK-OK-FAIL) by ftp.linux-mips.org with ESMTP id S20022000AbZFCJo7 (ORCPT ); Wed, 3 Jun 2009 10:44:59 +0100 Received: from gondolin.me.apana.org.au ([192.168.0.6]) by arnor.apana.org.au with esmtp (Exim 4.63 #1 (Debian)) id 1MBn1l-0007zJ-1D; Wed, 03 Jun 2009 19:44:57 +1000 Received: from herbert by gondolin.me.apana.org.au with local (Exim 4.69) (envelope-from ) id 1MBn1i-00031X-LR; Wed, 03 Jun 2009 19:44:54 +1000 Date: Wed, 3 Jun 2009 19:44:54 +1000 From: Herbert Xu To: Atsushi Nemoto Cc: linux-mips@linux-mips.org, ralf@linux-mips.org, mpm@selenic.com, linux-kernel@vger.kernel.org Subject: Re: [PATCH] TXx9: Add TX4939 RNG support (v2) Message-ID: <20090603094454.GB11356@gondor.apana.org.au> References: <1243954462-18149-2-git-send-email-anemo@mba.ocn.ne.jp> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1243954462-18149-2-git-send-email-anemo@mba.ocn.ne.jp> User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23199 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: herbert@gondor.apana.org.au Precedence: bulk X-list: linux-mips On Tue, Jun 02, 2009 at 11:54:22PM +0900, Atsushi Nemoto wrote: > Add platform support for RNG of TX4939 SoC. > > Signed-off-by: Atsushi Nemoto Aha, I knew I should have left Ralf take the patch, and this is the reason :) Rather than having the patches split between the two of us, I'll back out the RNG patch from my tree so both of them can go through Ralf's MIPS tree. Thanks, -- Visit Openswan at http://www.openswan.org/ Email: Herbert Xu ~{PmV>HI~} Home Page: http://gondor.apana.org.au/~herbert/ PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt From ralf@h5.dl5rb.org.uk Wed Jun 3 11:02:44 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 03 Jun 2009 11:02:51 +0100 (WEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:49452 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20022560AbZFCKCo (ORCPT ); Wed, 3 Jun 2009 11:02:44 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id n53A2GcZ013772; Wed, 3 Jun 2009 11:02:16 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id n53A2FUC013770; Wed, 3 Jun 2009 11:02:15 +0100 Date: Wed, 3 Jun 2009 11:02:15 +0100 From: Ralf Baechle To: Herbert Xu Cc: Matt Mackall , Atsushi Nemoto , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] hwrng: Add TX4939 RNG driver (v2) Message-ID: <20090603100215.GA13250@linux-mips.org> References: <1243954462-18149-1-git-send-email-anemo@mba.ocn.ne.jp> <1243973584.22069.182.camel@calx> <20090603090238.GH23561@linux-mips.org> <20090603092610.GA11258@gondor.apana.org.au> <20090603092927.GA11369@gondor.apana.org.au> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20090603092927.GA11369@gondor.apana.org.au> User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23200 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Wed, Jun 03, 2009 at 07:29:27PM +1000, Herbert Xu wrote: > On Wed, Jun 03, 2009 at 07:26:10PM +1000, Herbert Xu wrote: > > On Wed, Jun 03, 2009 at 10:02:38AM +0100, Ralf Baechle wrote: > > > > > Ok, I'll send this to Linus for 2.6.31 then. > > > > Actually I've already added it to my tree since I'm looking after > > the hwrng drivers. > > But if this causes any conflicts for you, then please let me know > and I'll back it out. Ah, I was looking at MAINTAINERS which said Mack who had acked it was handling it. There is no conflict on the drivers/char/hw_random/ part, so I'll drop that one. The platform part in arch/mips/ has to go through the MIPS tree as it depends on another patch. Ralf From ralf@h5.dl5rb.org.uk Wed Jun 3 11:04:02 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 03 Jun 2009 11:04:10 +0100 (WEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:49463 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20022560AbZFCKEC (ORCPT ); Wed, 3 Jun 2009 11:04:02 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id n53A3ZnY013806; Wed, 3 Jun 2009 11:03:35 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id n53A3ZlK013805; Wed, 3 Jun 2009 11:03:35 +0100 Date: Wed, 3 Jun 2009 11:03:35 +0100 From: Ralf Baechle To: Herbert Xu Cc: Atsushi Nemoto , linux-mips@linux-mips.org, mpm@selenic.com, linux-kernel@vger.kernel.org Subject: Re: [PATCH] TXx9: Add TX4939 RNG support (v2) Message-ID: <20090603100335.GB13250@linux-mips.org> References: <1243954462-18149-2-git-send-email-anemo@mba.ocn.ne.jp> <20090603094454.GB11356@gondor.apana.org.au> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20090603094454.GB11356@gondor.apana.org.au> User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23201 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Wed, Jun 03, 2009 at 07:44:54PM +1000, Herbert Xu wrote: > From: Herbert Xu > Date: Wed, 3 Jun 2009 19:44:54 +1000 > To: Atsushi Nemoto > Cc: linux-mips@linux-mips.org, ralf@linux-mips.org, mpm@selenic.com, > linux-kernel@vger.kernel.org > Subject: Re: [PATCH] TXx9: Add TX4939 RNG support (v2) > Content-Type: text/plain; charset=us-ascii > > On Tue, Jun 02, 2009 at 11:54:22PM +0900, Atsushi Nemoto wrote: > > Add platform support for RNG of TX4939 SoC. > > > > Signed-off-by: Atsushi Nemoto > > Aha, I knew I should have left Ralf take the patch, and this is > the reason :) > > Rather than having the patches split between the two of us, I'll > back out the RNG patch from my tree so both of them can go through > Ralf's MIPS tree. Ah, got this email just in time before actually dropping the patch as I said in the other mail so I won't drop it. Confusion`R`Us ;-) Ralf From herbert@gondor.apana.org.au Wed Jun 3 11:04:27 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 03 Jun 2009 11:04:34 +0100 (WEST) Received: from rhun.apana.org.au ([64.62.148.172]:50958 "EHLO arnor.apana.org.au" rhost-flags-OK-OK-OK-FAIL) by ftp.linux-mips.org with ESMTP id S20022575AbZFCKEU (ORCPT ); Wed, 3 Jun 2009 11:04:20 +0100 Received: from gondolin.me.apana.org.au ([192.168.0.6]) by arnor.apana.org.au with esmtp (Exim 4.63 #1 (Debian)) id 1MBnKP-0008Hx-ID; Wed, 03 Jun 2009 20:04:13 +1000 Received: from herbert by gondolin.me.apana.org.au with local (Exim 4.69) (envelope-from ) id 1MBnKL-00037l-Ux; Wed, 03 Jun 2009 20:04:10 +1000 Date: Wed, 3 Jun 2009 20:04:09 +1000 From: Herbert Xu To: Ralf Baechle Cc: Matt Mackall , Atsushi Nemoto , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] hwrng: Add TX4939 RNG driver (v2) Message-ID: <20090603100409.GA11989@gondor.apana.org.au> References: <1243954462-18149-1-git-send-email-anemo@mba.ocn.ne.jp> <1243973584.22069.182.camel@calx> <20090603090238.GH23561@linux-mips.org> <20090603092610.GA11258@gondor.apana.org.au> <20090603092927.GA11369@gondor.apana.org.au> <20090603100215.GA13250@linux-mips.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20090603100215.GA13250@linux-mips.org> User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23202 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: herbert@gondor.apana.org.au Precedence: bulk X-list: linux-mips On Wed, Jun 03, 2009 at 11:02:15AM +0100, Ralf Baechle wrote: > > There is no conflict on the drivers/char/hw_random/ part, so I'll drop > that one. The platform part in arch/mips/ has to go through the MIPS > tree as it depends on another patch. OK we can certainly do that. Thanks, -- Visit Openswan at http://www.openswan.org/ Email: Herbert Xu ~{PmV>HI~} Home Page: http://gondor.apana.org.au/~herbert/ PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt From herbert@gondor.apana.org.au Wed Jun 3 11:04:59 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 03 Jun 2009 11:05:05 +0100 (WEST) Received: from rhun.apana.org.au ([64.62.148.172]:50962 "EHLO arnor.apana.org.au" rhost-flags-OK-OK-OK-FAIL) by ftp.linux-mips.org with ESMTP id S20022583AbZFCKEt (ORCPT ); Wed, 3 Jun 2009 11:04:49 +0100 Received: from gondolin.me.apana.org.au ([192.168.0.6]) by arnor.apana.org.au with esmtp (Exim 4.63 #1 (Debian)) id 1MBnKx-0008IV-8W; Wed, 03 Jun 2009 20:04:47 +1000 Received: from herbert by gondolin.me.apana.org.au with local (Exim 4.69) (envelope-from ) id 1MBnKw-00038G-Ny; Wed, 03 Jun 2009 20:04:46 +1000 Date: Wed, 3 Jun 2009 20:04:46 +1000 From: Herbert Xu To: Ralf Baechle Cc: Atsushi Nemoto , linux-mips@linux-mips.org, mpm@selenic.com, linux-kernel@vger.kernel.org Subject: Re: [PATCH] TXx9: Add TX4939 RNG support (v2) Message-ID: <20090603100446.GB11989@gondor.apana.org.au> References: <1243954462-18149-2-git-send-email-anemo@mba.ocn.ne.jp> <20090603094454.GB11356@gondor.apana.org.au> <20090603100335.GB13250@linux-mips.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20090603100335.GB13250@linux-mips.org> User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23203 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: herbert@gondor.apana.org.au Precedence: bulk X-list: linux-mips On Wed, Jun 03, 2009 at 11:03:35AM +0100, Ralf Baechle wrote: > > Ah, got this email just in time before actually dropping the patch as I > said in the other mail so I won't drop it. > > Confusion`R`Us ;-) Heh, I should stop replying emails too quickly. Let's make this the final agreement. Cheers, -- Visit Openswan at http://www.openswan.org/ Email: Herbert Xu ~{PmV>HI~} Home Page: http://gondor.apana.org.au/~herbert/ PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt From f.fainelli@gmail.com Wed Jun 3 11:24:26 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 03 Jun 2009 11:24:34 +0100 (WEST) Received: from mail-bw0-f177.google.com ([209.85.218.177]:46057 "EHLO mail-bw0-f177.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20022592AbZFCKY0 (ORCPT ); Wed, 3 Jun 2009 11:24:26 +0100 Received: by bwz25 with SMTP id 25so8907706bwz.0 for ; Wed, 03 Jun 2009 03:24:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:sender:from:date:subject :mime-version:x-uid:x-length:to:content-type :content-transfer-encoding:content-disposition:message-id; bh=4iW2pTT8EceXT7UmGOhuzxrgoiveGPq0MDrXV/6QIwM=; b=X1KwkQDI93FoV5voeZ9nCGgSsprhNVROOzMtEMKzC4kjreg6O4XdC98dvR9LC8Hfk6 l9uwkHkbSW56d2ybQdFuq2ASbMMnT0sQMQPDqksGiyKTkm5ZZQvLeJ0TTT/0FctJ2KsQ EGkCfxVj2Yi68JzUQoRaotG2VoInb4RjAEeAM= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:from:date:subject:mime-version:x-uid:x-length:to :content-type:content-transfer-encoding:content-disposition :message-id; b=BCrDdQKEglY71Q6ezChpdHS6edAsJrvHrDuTp6SGsZORKWh7RWVGHqKdCU8GWcgpYe FYBKVaRN8GV8igBMp3+N8OkBN+831JpWmK8+AHj1Oul6o4Gb6H04u2DNP3ZYKbx9Bhib pNCNztVcmhU9m62dMwRp85xKvlA6TAz+pheqA= Received: by 10.204.59.14 with SMTP id j14mr750107bkh.39.1244024659930; Wed, 03 Jun 2009 03:24:19 -0700 (PDT) Received: from florian.lab.openpattern.org (lab.openpattern.org [82.240.16.241]) by mx.google.com with ESMTPS id 35sm9800470fkt.50.2009.06.03.03.24.19 (version=TLSv1/SSLv3 cipher=RC4-MD5); Wed, 03 Jun 2009 03:24:19 -0700 (PDT) From: Florian Fainelli Date: Wed, 3 Jun 2009 12:24:16 +0200 Subject: [PATCH] bcm63xx: register gpiochip in prom MIME-Version: 1.0 X-UID: 213 X-Length: 2676 To: Ralf Baechle , linux-mips@linux-mips.org, Maxime Bizon Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Content-Disposition: inline Message-Id: <200906031224.17368.florian@openwrt.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23204 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips This patch moves the gpiochip registration fro arch_initcall to prom. This allows GPIO-based runtime board detection to be performed earlier. Tested-by: Maxime Bizon Signed-off-by: Florian Fainelli --- diff --git a/arch/mips/bcm63xx/gpio.c b/arch/mips/bcm63xx/gpio.c index b78d3fd..997fcaa 100644 --- a/arch/mips/bcm63xx/gpio.c +++ b/arch/mips/bcm63xx/gpio.c @@ -120,9 +120,8 @@ static struct gpio_chip bcm63xx_gpio_chip = { .ngpio = BCM63XX_GPIO_COUNT, }; -static int __init bcm63xx_gpio_init(void) +int __init bcm63xx_gpio_init(void) { printk(KERN_INFO "registering %d GPIOs\n", BCM63XX_GPIO_COUNT); return gpiochip_add(&bcm63xx_gpio_chip); } -arch_initcall(bcm63xx_gpio_init); diff --git a/arch/mips/bcm63xx/prom.c b/arch/mips/bcm63xx/prom.c index d97ceed..2cac966 100644 --- a/arch/mips/bcm63xx/prom.c +++ b/arch/mips/bcm63xx/prom.c @@ -13,6 +13,7 @@ #include #include #include +#include void __init prom_init(void) { @@ -40,6 +41,9 @@ void __init prom_init(void) /* do low level board init */ board_prom_init(); + + /* register gpiochip */ + bcm63xx_gpio_init(); } void __init prom_free_prom_memory(void) diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h index 72cee75..7f5d8e8 100644 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h @@ -1,6 +1,10 @@ #ifndef BCM63XX_GPIO_H #define BCM63XX_GPIO_H +#include + +int __init bcm63xx_gpio_init(void); + /* all helpers will BUG() if gpio count is >= 37. */ #define BCM63XX_GPIO_COUNT 37 From ralf@h5.dl5rb.org.uk Wed Jun 3 11:25:54 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 03 Jun 2009 11:26:00 +0100 (WEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:35378 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20022576AbZFCKZy (ORCPT ); Wed, 3 Jun 2009 11:25:54 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id n53APTjj016177; Wed, 3 Jun 2009 11:25:29 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id n53APPIP016175; Wed, 3 Jun 2009 11:25:25 +0100 Date: Wed, 3 Jun 2009 11:25:24 +0100 From: Ralf Baechle To: Yoichi Yuasa Cc: linux-mips Subject: Re: [PATCH][MIPS] PCI bus is always required for Cobalt ID Message-ID: <20090603102523.GC13250@linux-mips.org> References: <20090602231707.7bf24ee2.yoichi_yuasa@tripeaks.co.jp> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20090602231707.7bf24ee2.yoichi_yuasa@tripeaks.co.jp> User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23205 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Tue, Jun 02, 2009 at 11:17:07PM +0900, Yoichi Yuasa wrote: Thanks, applied as well. Ralf From ralf@h5.dl5rb.org.uk Wed Jun 3 12:21:39 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 03 Jun 2009 12:21:46 +0100 (WEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:48251 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20022560AbZFCLVi (ORCPT ); Wed, 3 Jun 2009 12:21:38 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id n53BL6mA018825; Wed, 3 Jun 2009 12:21:06 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id n53BL4Jc018823; Wed, 3 Jun 2009 12:21:04 +0100 Date: Wed, 3 Jun 2009 12:21:04 +0100 From: Ralf Baechle To: wuzhangjin@gmail.com Cc: linux-mips@linux-mips.org, Arnaud Patard , Atsushi Nemoto , yan hua , Zhang Fuxin , Pavel Machek , Wu Zhangjin , Hongbing Hu Subject: Re: [PATCH] Hibernation Support in mips system Message-ID: <20090603112104.GD13250@linux-mips.org> References: <1243956702-16276-1-git-send-email-wuzhangjin@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1243956702-16276-1-git-send-email-wuzhangjin@gmail.com> User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23206 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Tue, Jun 02, 2009 at 11:31:42PM +0800, wuzhangjin@gmail.com wrote: > diff --git a/arch/mips/power/cpu.c b/arch/mips/power/cpu.c > new file mode 100644 > index 0000000..5fe43e5 > --- /dev/null > +++ b/arch/mips/power/cpu.c > @@ -0,0 +1,31 @@ > +/* > + * Suspend support specific for mips. > + * > + */ > +#include > +#include > +#include > +#include > +#include > +#include > + > +static uint32_t saved_status; > +struct pt_regs saved_regs; > + > +void save_processor_state(void) > +{ > + saved_status = read_c0_status(); > +} > + > +void restore_processor_state(void) > +{ > + write_c0_status(saved_status); > +} > + > +int pfn_is_nosave(unsigned long pfn) > +{ > + unsigned long nosave_begin_pfn = PFN_DOWN(__pa(&__nosave_begin)); > + unsigned long nosave_end_pfn = PFN_UP(__pa(&__nosave_end)); > + > + return (pfn >= nosave_begin_pfn) && (pfn < nosave_end_pfn); > +} I'm missing FPU handling here. > diff --git a/arch/mips/power/hibernate.S b/arch/mips/power/hibernate.S > new file mode 100644 > index 0000000..4ca9149 > --- /dev/null > +++ b/arch/mips/power/hibernate.S > @@ -0,0 +1,67 @@ > +#incldue > +#include > +#include > +#include > + > + .extern __flush_cache_all > +#ifdef CONFIG_SMP > + .extern flush_tlb_all > +#else > + .extern local_flush_tlb_all > +#define flush_tlb_all local_flush_tlb_all > +#endif For ease of maintenance, could you do these flushes from C code and only do the bits that absolutely must be done in assembler, in assembler? > + /* flush caches to make sure context is in memory */ > + PTR_L t0, __flush_cache_all > + jalr t0 > + /* flush tlb entries */ > + PTR_LA t0, flush_tlb_all In addition to the above said - there is no PTR_L JALR sequence needed here because this code is never compiled as a loadable module. So a jal would do the job. All in all this is looking much better than the first version! Ralf From pavel@ucw.cz Wed Jun 3 12:24:23 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 03 Jun 2009 12:24:29 +0100 (WEST) Received: from atrey.karlin.mff.cuni.cz ([195.113.26.193]:52012 "EHLO atrey.karlin.mff.cuni.cz" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20022560AbZFCLYX (ORCPT ); Wed, 3 Jun 2009 12:24:23 +0100 Received: by atrey.karlin.mff.cuni.cz (Postfix, from userid 512) id 43BA5F0131; Wed, 3 Jun 2009 13:24:21 +0200 (CEST) Date: Wed, 3 Jun 2009 13:24:15 +0200 From: Pavel Machek To: wuzhangjin@gmail.com Cc: linux-mips@linux-mips.org, ralf@linux-mips.org, Arnaud Patard , Atsushi Nemoto , yan hua , Zhang Fuxin , Wu Zhangjin , Hongbing Hu Subject: Re: [PATCH] Hibernation Support in mips system Message-ID: <20090603112414.GF5084@elf.ucw.cz> References: <1243956702-16276-1-git-send-email-wuzhangjin@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1243956702-16276-1-git-send-email-wuzhangjin@gmail.com> X-Warning: Reading this can be dangerous to your mental health. User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23207 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: pavel@ucw.cz Precedence: bulk X-list: linux-mips On Tue 2009-06-02 23:31:42, wuzhangjin@gmail.com wrote: > From: Wu Zhangjin > > This is originally pulled from the to-mips branch of > http://dev.lemote.com/code/linux_loongson, only a few coding style > tuning under the support of script/checkpatch.pl > > as the feedback from Atsushi Nemoto,Yanhua and Pavel Machek, some changes > have been done by Hu Hongbing(the original author of mips-specific STD) > from Lemote.com. this patch apply the changes, which include: > > Reviewed-by: Pavel Machek The patch looks ok, but I don't think I offered that tag before. You can add it now. > @@ -0,0 +1,31 @@ > +/* > + * Suspend support specific for mips. "Hibernation support"? Copyright, GPL, author info? > +#include > +#include > +#include > +#include > +#include > +#include > + > +static uint32_t saved_status; "u32" please. Pavel -- (english) http://www.livejournal.com/~pavelmachek (cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html From rostedt@goodmis.org Wed Jun 3 14:13:44 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 03 Jun 2009 14:13:52 +0100 (WEST) Received: from hrndva-omtalb.mail.rr.com ([71.74.56.125]:48394 "EHLO hrndva-omtalb.mail.rr.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20022726AbZFCNNn (ORCPT ); Wed, 3 Jun 2009 14:13:43 +0100 Received: from gandalf ([74.67.89.75]) by hrndva-omta02.mail.rr.com with ESMTP id <20090603124708504.NBIH11757@hrndva-omta02.mail.rr.com>; Wed, 3 Jun 2009 12:47:08 +0000 Date: Wed, 3 Jun 2009 08:47:07 -0400 (EDT) From: Steven Rostedt X-X-Sender: rostedt@gandalf.stny.rr.com To: Wang Liming cc: wu zhangjin , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, Wu Zhangjin , Ralf Baechle , Ingo Molnar , Andrew Morton , Frederic Weisbecker , Thomas Gleixner , Nicholas Mc Guire Subject: Re: [PATCH v2 2/6] mips dynamic function tracer support In-Reply-To: <4A26129E.1080008@windriver.com> Message-ID: References: <4A22281B.7020908@windriver.com> <4A26129E.1080008@windriver.com> User-Agent: Alpine 2.00 (DEB 1167 2008-08-23) MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23208 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: rostedt@goodmis.org Precedence: bulk X-list: linux-mips On Wed, 3 Jun 2009, Wang Liming wrote: > wu zhangjin wrote: > > hi, > > > > sorry, I'm so late to reply your E-mail, a little busy these days. > > > > > > } > > > > > > ----------arch/mips/kernel/module.c:apply_r_mips_26_rel()------------------- > > > > > > v is kernel _mcount's address, location is the address of the instrution > > > that should be relocated; > > > > > > To resolve this problem, we may need to do more work, either on gcc or on > > > the kernel. So I want to hear your test result and if you have solution, > > > please let me know. > > > > > > > yes, current version of mips-specific dynamic ftrace not support modules > > yet. > > > > there is similar solution implemented in PowerPC(something named > > trampoline), > > although I did not look into it, but I'm sure we can implement the > > mips-specific one > > via imitating it. > Good hit. I may have a look on Powerpc implementation. Note, PowerPC uses a trampoline from modules to kernel core. I think MIPS just calls mcount differently. That is, it does a full 32bit address call (64 bit for 64 bit archs?). Something like: lui v1, _mcount addiu v1, v1, _mcount jalr v1 addiu sp, sp, -8 Then a nop would not do. Due to preemption, we can not modify more than one line. But you could modify it to: b 1f addiu v1, v1, _mcount jalr v1 addiu sp, sp, -8 1: Clobbering v1 should not be an issue since it is already used to store _mcount. That is, we still do the addiu v1,v1,_mcount with that branch. But v1 should be ignored. -- Steve From max@sakura.staff.proxad.net Wed Jun 3 15:02:33 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 03 Jun 2009 15:02:40 +0100 (WEST) Received: from sakura.staff.proxad.net ([213.228.1.107]:55025 "EHLO sakura.staff.proxad.net" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20022859AbZFCOCd (ORCPT ); Wed, 3 Jun 2009 15:02:33 +0100 Received: by sakura.staff.proxad.net (Postfix, from userid 1000) id D9FEA1124092; Wed, 3 Jun 2009 16:02:27 +0200 (CEST) From: Maxime Bizon To: linux-mips@linux-mips.org, Ralf Baechle Cc: Florian Fainelli , Maxime Bizon Subject: [PATCH 6/8] bcm63xx: add missing null entry in bcm63xx_pcmcia pci device table. Date: Wed, 3 Jun 2009 16:02:25 +0200 Message-Id: <1244037747-27144-7-git-send-email-mbizon@freebox.fr> X-Mailer: git-send-email 1.6.0.4 In-Reply-To: <1244037747-27144-1-git-send-email-mbizon@freebox.fr> References: <1244037747-27144-1-git-send-email-mbizon@freebox.fr> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23209 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mbizon@freebox.fr Precedence: bulk X-list: linux-mips The PCI device table in bcm63xx_pcmcia lacks the final null entry. Spotted by build system when building it as module. Signed-off-by: Maxime Bizon --- drivers/pcmcia/bcm63xx_pcmcia.c | 2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/drivers/pcmcia/bcm63xx_pcmcia.c b/drivers/pcmcia/bcm63xx_pcmcia.c index 6c7f20c..48928b8 100644 --- a/drivers/pcmcia/bcm63xx_pcmcia.c +++ b/drivers/pcmcia/bcm63xx_pcmcia.c @@ -492,6 +492,8 @@ static struct pci_device_id bcm63xx_cb_table[] = { .class = PCI_CLASS_BRIDGE_CARDBUS << 8, .class_mask = ~0, }, + + { }, }; MODULE_DEVICE_TABLE(pci, bcm63xx_cb_table); -- 1.6.0.4 From max@sakura.staff.proxad.net Wed Jun 3 15:02:57 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 03 Jun 2009 15:03:05 +0100 (WEST) Received: from sakura.staff.proxad.net ([213.228.1.107]:55023 "EHLO sakura.staff.proxad.net" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20022855AbZFCOCd (ORCPT ); Wed, 3 Jun 2009 15:02:33 +0100 Received: by sakura.staff.proxad.net (Postfix, from userid 1000) id CD316112406C; Wed, 3 Jun 2009 16:02:27 +0200 (CEST) From: Maxime Bizon To: linux-mips@linux-mips.org, Ralf Baechle Cc: Florian Fainelli , Maxime Bizon Subject: [PATCH 8/8] bcm63xx: fix oops when removing bcm63xx_enet module. Date: Wed, 3 Jun 2009 16:02:27 +0200 Message-Id: <1244037747-27144-9-git-send-email-mbizon@freebox.fr> X-Mailer: git-send-email 1.6.0.4 In-Reply-To: <1244037747-27144-1-git-send-email-mbizon@freebox.fr> References: <1244037747-27144-1-git-send-email-mbizon@freebox.fr> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23210 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mbizon@freebox.fr Precedence: bulk X-list: linux-mips SET_NETDEV_DEV has to be called before registering netdevice, not after, otherwise we get unbalanced kobject get/put when unregistering. This patch also adds missing platform_set_drvdata(pdev, NULL) before freiing netdevice. Signed-off-by: Maxime Bizon --- drivers/net/bcm63xx_enet.c | 3 ++- 1 files changed, 2 insertions(+), 1 deletions(-) diff --git a/drivers/net/bcm63xx_enet.c b/drivers/net/bcm63xx_enet.c index 660ffa2..09d2709 100644 --- a/drivers/net/bcm63xx_enet.c +++ b/drivers/net/bcm63xx_enet.c @@ -1788,6 +1788,7 @@ static int __devinit bcm_enet_probe(struct platform_device *pdev) netif_napi_add(dev, &priv->napi, bcm_enet_poll, 16); SET_ETHTOOL_OPS(dev, &bcm_enet_ethtool_ops); + SET_NETDEV_DEV(dev, &pdev->dev); ret = register_netdev(dev); if (ret) @@ -1797,7 +1798,6 @@ static int __devinit bcm_enet_probe(struct platform_device *pdev) platform_set_drvdata(pdev, dev); priv->pdev = pdev; priv->net_dev = dev; - SET_NETDEV_DEV(dev, &pdev->dev); return 0; @@ -1877,6 +1877,7 @@ static int __devexit bcm_enet_remove(struct platform_device *pdev) clk_disable(priv->mac_clk); clk_put(priv->mac_clk); + platform_set_drvdata(pdev, NULL); free_netdev(dev); return 0; } -- 1.6.0.4 From max@sakura.staff.proxad.net Wed Jun 3 15:03:22 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 03 Jun 2009 15:03:30 +0100 (WEST) Received: from sakura.staff.proxad.net ([213.228.1.107]:55026 "EHLO sakura.staff.proxad.net" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20022862AbZFCOCd (ORCPT ); Wed, 3 Jun 2009 15:02:33 +0100 Received: by sakura.staff.proxad.net (Postfix, from userid 1000) id E058C1124090; Wed, 3 Jun 2009 16:02:27 +0200 (CEST) From: Maxime Bizon To: linux-mips@linux-mips.org, Ralf Baechle Cc: Florian Fainelli , Maxime Bizon Subject: [PATCH 4/8] bcm63xx: restore spinlock in gpio. Date: Wed, 3 Jun 2009 16:02:23 +0200 Message-Id: <1244037747-27144-5-git-send-email-mbizon@freebox.fr> X-Mailer: git-send-email 1.6.0.4 In-Reply-To: <1244037747-27144-1-git-send-email-mbizon@freebox.fr> References: <1244037747-27144-1-git-send-email-mbizon@freebox.fr> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23211 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mbizon@freebox.fr Precedence: bulk X-list: linux-mips gpiolib does not do any locking around chip callbacks, local_irq_save is enough for now but try to stay future-proof. Fix indentation too. Signed-off-by: Maxime Bizon --- arch/mips/bcm63xx/gpio.c | 15 ++++++++------- 1 files changed, 8 insertions(+), 7 deletions(-) diff --git a/arch/mips/bcm63xx/gpio.c b/arch/mips/bcm63xx/gpio.c index 77636aa..53e4664 100644 --- a/arch/mips/bcm63xx/gpio.c +++ b/arch/mips/bcm63xx/gpio.c @@ -18,10 +18,11 @@ #include #include +static DEFINE_SPINLOCK(bcm63xx_gpio_lock); static u32 gpio_out_low, gpio_out_high; static void bcm63xx_gpio_set(struct gpio_chip *chip, - unsigned gpio, int val) + unsigned gpio, int val) { u32 reg; u32 mask; @@ -41,13 +42,13 @@ static void bcm63xx_gpio_set(struct gpio_chip *chip, v = &gpio_out_high; } - local_irq_save(flags); + spin_lock_irqsave(&bcm63xx_gpio_lock, flags); if (val) *v |= mask; else *v &= ~mask; bcm_gpio_writel(*v, reg); - local_irq_restore(flags); + spin_unlock_irqrestore(&bcm63xx_gpio_lock, flags); } static int bcm63xx_gpio_get(struct gpio_chip *chip, unsigned gpio) @@ -70,7 +71,7 @@ static int bcm63xx_gpio_get(struct gpio_chip *chip, unsigned gpio) } static int bcm63xx_gpio_set_direction(struct gpio_chip *chip, - unsigned gpio, int dir) + unsigned gpio, int dir) { u32 reg; u32 mask; @@ -88,14 +89,14 @@ static int bcm63xx_gpio_set_direction(struct gpio_chip *chip, mask = 1 << (gpio - 32); } - local_irq_save(flags); + spin_lock_irqsave(&bcm63xx_gpio_lock, flags); tmp = bcm_gpio_readl(reg); if (dir == GPIO_DIR_IN) tmp &= ~mask; else tmp |= mask; bcm_gpio_writel(tmp, reg); - local_irq_restore(flags); + spin_unlock_irqrestore(&bcm63xx_gpio_lock, flags); return 0; } @@ -106,7 +107,7 @@ static int bcm63xx_gpio_direction_input(struct gpio_chip *chip, unsigned gpio) } static int bcm63xx_gpio_direction_output(struct gpio_chip *chip, - unsigned gpio, int value) + unsigned gpio, int value) { bcm63xx_gpio_set(chip, gpio, value); return bcm63xx_gpio_set_direction(chip, gpio, GPIO_DIR_OUT); -- 1.6.0.4 From max@sakura.staff.proxad.net Wed Jun 3 15:03:46 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 03 Jun 2009 15:03:54 +0100 (WEST) Received: from sakura.staff.proxad.net ([213.228.1.107]:55024 "EHLO sakura.staff.proxad.net" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20022860AbZFCOCd (ORCPT ); Wed, 3 Jun 2009 15:02:33 +0100 Received: by sakura.staff.proxad.net (Postfix, from userid 1000) id E6A54112408D; Wed, 3 Jun 2009 16:02:27 +0200 (CEST) From: Maxime Bizon To: linux-mips@linux-mips.org, Ralf Baechle Cc: Florian Fainelli , Maxime Bizon Subject: [PATCH 3/8] bcm63xx: fix gpio set. Date: Wed, 3 Jun 2009 16:02:22 +0200 Message-Id: <1244037747-27144-4-git-send-email-mbizon@freebox.fr> X-Mailer: git-send-email 1.6.0.4 In-Reply-To: <1244037747-27144-1-git-send-email-mbizon@freebox.fr> References: <1244037747-27144-1-git-send-email-mbizon@freebox.fr> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23212 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mbizon@freebox.fr Precedence: bulk X-list: linux-mips Previously set gpio value can not be read back from register, we're reading pin value instead. Keep cached value and always use it. Signed-off-by: Maxime Bizon --- arch/mips/bcm63xx/gpio.c | 13 ++++++++----- 1 files changed, 8 insertions(+), 5 deletions(-) diff --git a/arch/mips/bcm63xx/gpio.c b/arch/mips/bcm63xx/gpio.c index 97e3730..77636aa 100644 --- a/arch/mips/bcm63xx/gpio.c +++ b/arch/mips/bcm63xx/gpio.c @@ -18,12 +18,14 @@ #include #include +static u32 gpio_out_low, gpio_out_high; + static void bcm63xx_gpio_set(struct gpio_chip *chip, unsigned gpio, int val) { u32 reg; u32 mask; - u32 tmp; + u32 *v; unsigned long flags; if (gpio >= chip->ngpio) @@ -32,18 +34,19 @@ static void bcm63xx_gpio_set(struct gpio_chip *chip, if (gpio < 32) { reg = GPIO_DATA_LO_REG; mask = 1 << gpio; + v = &gpio_out_low; } else { reg = GPIO_DATA_HI_REG; mask = 1 << (gpio - 32); + v = &gpio_out_high; } local_irq_save(flags); - tmp = bcm_gpio_readl(reg); if (val) - tmp |= mask; + *v |= mask; else - tmp &= ~mask; - bcm_gpio_writel(tmp, reg); + *v &= ~mask; + bcm_gpio_writel(*v, reg); local_irq_restore(flags); } -- 1.6.0.4 From max@sakura.staff.proxad.net Wed Jun 3 15:04:11 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 03 Jun 2009 15:04:19 +0100 (WEST) Received: from sakura.staff.proxad.net ([213.228.1.107]:55027 "EHLO sakura.staff.proxad.net" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20022863AbZFCOCd (ORCPT ); Wed, 3 Jun 2009 15:02:33 +0100 Received: by sakura.staff.proxad.net (Postfix, from userid 1000) id 86CC0112408E; Wed, 3 Jun 2009 16:02:27 +0200 (CEST) From: Maxime Bizon To: linux-mips@linux-mips.org, Ralf Baechle Cc: Florian Fainelli Subject: More updates to bcm63xx Date: Wed, 3 Jun 2009 16:02:19 +0200 Message-Id: <1244037747-27144-1-git-send-email-mbizon@freebox.fr> X-Mailer: git-send-email 1.6.0.4 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23213 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mbizon@freebox.fr Precedence: bulk X-list: linux-mips Hi Ralf, Yet another list of cleanup and fixes for the bcm63xx tree, please fold them into the existing patches. Thanks ! From max@sakura.staff.proxad.net Wed Jun 3 15:04:36 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 03 Jun 2009 15:04:43 +0100 (WEST) Received: from sakura.staff.proxad.net ([213.228.1.107]:55032 "EHLO sakura.staff.proxad.net" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20022848AbZFCOCj (ORCPT ); Wed, 3 Jun 2009 15:02:39 +0100 Received: by sakura.staff.proxad.net (Postfix, from userid 1000) id EAED41124091; Wed, 3 Jun 2009 16:02:27 +0200 (CEST) From: Maxime Bizon To: linux-mips@linux-mips.org, Ralf Baechle Cc: Florian Fainelli , Maxime Bizon Subject: [PATCH 1/8] bcm63xx: register gpiochip in prom Date: Wed, 3 Jun 2009 16:02:20 +0200 Message-Id: <1244037747-27144-2-git-send-email-mbizon@freebox.fr> X-Mailer: git-send-email 1.6.0.4 In-Reply-To: <1244037747-27144-1-git-send-email-mbizon@freebox.fr> References: <1244037747-27144-1-git-send-email-mbizon@freebox.fr> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23214 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mbizon@freebox.fr Precedence: bulk X-list: linux-mips This patch moves the gpiochip registration fro arch_initcall to prom. This allows GPIO-based runtime board detection to be performed earlier. Original patch by Florian, changed to register gpio before calling board_prom_init callback since we may want to use gpio inside it. Signed-off-by: Florian Fainelli Signed-off-by: Maxime Bizon --- arch/mips/bcm63xx/gpio.c | 3 +-- arch/mips/bcm63xx/prom.c | 4 ++++ arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h | 4 ++++ 3 files changed, 9 insertions(+), 2 deletions(-) diff --git a/arch/mips/bcm63xx/gpio.c b/arch/mips/bcm63xx/gpio.c index b78d3fd..997fcaa 100644 --- a/arch/mips/bcm63xx/gpio.c +++ b/arch/mips/bcm63xx/gpio.c @@ -120,9 +120,8 @@ static struct gpio_chip bcm63xx_gpio_chip = { .ngpio = BCM63XX_GPIO_COUNT, }; -static int __init bcm63xx_gpio_init(void) +int __init bcm63xx_gpio_init(void) { printk(KERN_INFO "registering %d GPIOs\n", BCM63XX_GPIO_COUNT); return gpiochip_add(&bcm63xx_gpio_chip); } -arch_initcall(bcm63xx_gpio_init); diff --git a/arch/mips/bcm63xx/prom.c b/arch/mips/bcm63xx/prom.c index d97ceed..386cb9a 100644 --- a/arch/mips/bcm63xx/prom.c +++ b/arch/mips/bcm63xx/prom.c @@ -13,6 +13,7 @@ #include #include #include +#include void __init prom_init(void) { @@ -38,6 +39,9 @@ void __init prom_init(void) /* assign command line from kernel config */ strcpy(arcs_cmdline, CONFIG_CMDLINE); + /* register gpiochip */ + bcm63xx_gpio_init(); + /* do low level board init */ board_prom_init(); } diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h index 72cee75..7f5d8e8 100644 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h @@ -1,6 +1,10 @@ #ifndef BCM63XX_GPIO_H #define BCM63XX_GPIO_H +#include + +int __init bcm63xx_gpio_init(void); + /* all helpers will BUG() if gpio count is >= 37. */ #define BCM63XX_GPIO_COUNT 37 -- 1.6.0.4 From max@sakura.staff.proxad.net Wed Jun 3 15:05:00 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 03 Jun 2009 15:05:08 +0100 (WEST) Received: from sakura.staff.proxad.net ([213.228.1.107]:55035 "EHLO sakura.staff.proxad.net" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20022864AbZFCOCj (ORCPT ); Wed, 3 Jun 2009 15:02:39 +0100 Received: by sakura.staff.proxad.net (Postfix, from userid 1000) id E8243112408F; Wed, 3 Jun 2009 16:02:27 +0200 (CEST) From: Maxime Bizon To: linux-mips@linux-mips.org, Ralf Baechle Cc: Florian Fainelli , Maxime Bizon Subject: [PATCH 2/8] bcm63xx: register correct number of gpio for 6358. Date: Wed, 3 Jun 2009 16:02:21 +0200 Message-Id: <1244037747-27144-3-git-send-email-mbizon@freebox.fr> X-Mailer: git-send-email 1.6.0.4 In-Reply-To: <1244037747-27144-1-git-send-email-mbizon@freebox.fr> References: <1244037747-27144-1-git-send-email-mbizon@freebox.fr> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23215 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mbizon@freebox.fr Precedence: bulk X-list: linux-mips 6358 has 40 gpio whereas 6348 has 37, so set the maximum number of gpio at runtime. Also remove NR_BUILTIN_GPIO which does not seem to be used anymore. Signed-off-by: Maxime Bizon --- arch/mips/bcm63xx/gpio.c | 4 ++-- arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h | 12 ++++++++++-- arch/mips/include/asm/mach-bcm63xx/gpio.h | 2 -- 3 files changed, 12 insertions(+), 6 deletions(-) diff --git a/arch/mips/bcm63xx/gpio.c b/arch/mips/bcm63xx/gpio.c index 997fcaa..97e3730 100644 --- a/arch/mips/bcm63xx/gpio.c +++ b/arch/mips/bcm63xx/gpio.c @@ -117,11 +117,11 @@ static struct gpio_chip bcm63xx_gpio_chip = { .get = bcm63xx_gpio_get, .set = bcm63xx_gpio_set, .base = 0, - .ngpio = BCM63XX_GPIO_COUNT, }; int __init bcm63xx_gpio_init(void) { - printk(KERN_INFO "registering %d GPIOs\n", BCM63XX_GPIO_COUNT); + bcm63xx_gpio_chip.ngpio = bcm63xx_gpio_count(); + printk(KERN_INFO "registering %d GPIOs\n", bcm63xx_gpio_chip.ngpio); return gpiochip_add(&bcm63xx_gpio_chip); } diff --git a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h index 7f5d8e8..76a0b72 100644 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h @@ -5,8 +5,16 @@ int __init bcm63xx_gpio_init(void); -/* all helpers will BUG() if gpio count is >= 37. */ -#define BCM63XX_GPIO_COUNT 37 +static inline unsigned long bcm63xx_gpio_count(void) +{ + switch (bcm63xx_get_cpu_id()) { + case BCM6358_CPU_ID: + return 40; + case BCM6348_CPU_ID: + default: + return 37; + } +} #define GPIO_DIR_OUT 0x0 #define GPIO_DIR_IN 0x1 diff --git a/arch/mips/include/asm/mach-bcm63xx/gpio.h b/arch/mips/include/asm/mach-bcm63xx/gpio.h index 033c997..7cda8c0 100644 --- a/arch/mips/include/asm/mach-bcm63xx/gpio.h +++ b/arch/mips/include/asm/mach-bcm63xx/gpio.h @@ -3,8 +3,6 @@ #include -#define NR_BUILTIN_GPIO BCM63XX_GPIO_COUNT - #define gpio_to_irq(gpio) NULL #define gpio_get_value __gpio_get_value -- 1.6.0.4 From max@sakura.staff.proxad.net Wed Jun 3 15:05:25 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 03 Jun 2009 15:05:33 +0100 (WEST) Received: from sakura.staff.proxad.net ([213.228.1.107]:55034 "EHLO sakura.staff.proxad.net" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20022867AbZFCOCj (ORCPT ); Wed, 3 Jun 2009 15:02:39 +0100 Received: by sakura.staff.proxad.net (Postfix, from userid 1000) id E71A4112408C; Wed, 3 Jun 2009 16:02:27 +0200 (CEST) From: Maxime Bizon To: linux-mips@linux-mips.org, Ralf Baechle Cc: Florian Fainelli , Maxime Bizon Subject: [PATCH 5/8] bcm63xx: request gpio before using it in bcm63xx_pcmcia. Date: Wed, 3 Jun 2009 16:02:24 +0200 Message-Id: <1244037747-27144-6-git-send-email-mbizon@freebox.fr> X-Mailer: git-send-email 1.6.0.4 In-Reply-To: <1244037747-27144-1-git-send-email-mbizon@freebox.fr> References: <1244037747-27144-1-git-send-email-mbizon@freebox.fr> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23216 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mbizon@freebox.fr Precedence: bulk X-list: linux-mips Make sure the gpio is requested and its direction set to input before using it. Signed-off-by: Maxime Bizon --- drivers/pcmcia/bcm63xx_pcmcia.c | 15 ++++++++++++++- 1 files changed, 14 insertions(+), 1 deletions(-) diff --git a/drivers/pcmcia/bcm63xx_pcmcia.c b/drivers/pcmcia/bcm63xx_pcmcia.c index 3a0b7fc..6c7f20c 100644 --- a/drivers/pcmcia/bcm63xx_pcmcia.c +++ b/drivers/pcmcia/bcm63xx_pcmcia.c @@ -409,9 +409,18 @@ static int bcm63xx_drv_pcmcia_probe(struct platform_device *pdev) val |= 3 << PCMCIA_C2_HOLD_SHIFT; pcmcia_writel(skt, val, PCMCIA_C2_REG); + /* request and setup ready gpio */ + ret = gpio_request(skt->pd->ready_gpio, "bcm63xx_pcmcia"); + if (ret < 0) + goto err; + + ret = gpio_direction_input(skt->pd->ready_gpio); + if (ret < 0) + goto err_gpio; + ret = pcmcia_register_socket(sock); if (ret) - goto err; + goto err_gpio; /* start polling socket */ mod_timer(&skt->timer, @@ -420,6 +429,9 @@ static int bcm63xx_drv_pcmcia_probe(struct platform_device *pdev) platform_set_drvdata(pdev, skt); return 0; +err_gpio: + gpio_free(skt->pd->ready_gpio); + err: if (skt->io_base) iounmap(skt->io_base); @@ -442,6 +454,7 @@ static int bcm63xx_drv_pcmcia_remove(struct platform_device *pdev) iounmap(skt->io_base); res = skt->reg_res; release_mem_region(res->start, res->end - res->start + 1); + gpio_free(skt->pd->ready_gpio); kfree(skt); return 0; } -- 1.6.0.4 From max@sakura.staff.proxad.net Wed Jun 3 15:05:50 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 03 Jun 2009 15:05:57 +0100 (WEST) Received: from sakura.staff.proxad.net ([213.228.1.107]:55033 "EHLO sakura.staff.proxad.net" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20022866AbZFCOCj (ORCPT ); Wed, 3 Jun 2009 15:02:39 +0100 Received: by sakura.staff.proxad.net (Postfix, from userid 1000) id EA5D5112408B; Wed, 3 Jun 2009 16:02:27 +0200 (CEST) From: Maxime Bizon To: linux-mips@linux-mips.org, Ralf Baechle Cc: Florian Fainelli , Maxime Bizon Subject: [PATCH 7/8] bcm63xx: fix bcm63xx_pcmcia device removal. Date: Wed, 3 Jun 2009 16:02:26 +0200 Message-Id: <1244037747-27144-8-git-send-email-mbizon@freebox.fr> X-Mailer: git-send-email 1.6.0.4 In-Reply-To: <1244037747-27144-1-git-send-email-mbizon@freebox.fr> References: <1244037747-27144-1-git-send-email-mbizon@freebox.fr> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23217 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mbizon@freebox.fr Precedence: bulk X-list: linux-mips Add missing platform_set_drvdata(pdev, NULL) before releasing private data. Signed-off-by: Maxime Bizon --- drivers/pcmcia/bcm63xx_pcmcia.c | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/drivers/pcmcia/bcm63xx_pcmcia.c b/drivers/pcmcia/bcm63xx_pcmcia.c index 48928b8..2981aff 100644 --- a/drivers/pcmcia/bcm63xx_pcmcia.c +++ b/drivers/pcmcia/bcm63xx_pcmcia.c @@ -455,6 +455,7 @@ static int bcm63xx_drv_pcmcia_remove(struct platform_device *pdev) res = skt->reg_res; release_mem_region(res->start, res->end - res->start + 1); gpio_free(skt->pd->ready_gpio); + platform_set_drvdata(pdev, NULL); kfree(skt); return 0; } -- 1.6.0.4 From wuzhangjin@gmail.com Wed Jun 3 15:18:11 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 03 Jun 2009 15:18:17 +0100 (WEST) Received: from mail-px0-f186.google.com ([209.85.216.186]:33284 "EHLO mail-px0-f186.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20022866AbZFCOSL (ORCPT ); Wed, 3 Jun 2009 15:18:11 +0100 Received: by pxi16 with SMTP id 16so9204pxi.22 for ; Wed, 03 Jun 2009 07:18:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer; bh=V1LgB9XskjSTTyR7Hy7TZWcBxlhxfuYl4pMEHulMd4A=; b=Aa1hB/DSHqTcQ7qonhXW29qSATuf0acBcRZVUlJmIW1/pZi7d94ryBjn0e3WnEKD7c lDIdatCUWHK2vcfU8lO8FbipMJdT5L5JoOZx2deG5Z7ZwtWeSvztZHCmACXdobi727I/ GhjX8C5AR56+iTCs9sLyH9N4tydhplYusxXA8= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer; b=LekjN+KZRTNh4B5g1u4P6Id5LUTEb7aYCp+5sI5QGms4KpXO3Lrzn4C5L/EMwzLsrJ y8EM56sQNxoMugrz7jAgWPo7VrNj8ucmfAPS892uaJ3amJ7dHQEY6otRXoQPlR5aRIhK BkMPuCOT5gED8MDTrBDaRJQOvPlu4PTVR6iJY= Received: by 10.115.14.15 with SMTP id r15mr1607071wai.107.1244038680601; Wed, 03 Jun 2009 07:18:00 -0700 (PDT) Received: from localhost.localdomain ([202.201.14.140]) by mx.google.com with ESMTPS id n40sm9034457wag.65.2009.06.03.07.17.53 (version=TLSv1/SSLv3 cipher=RC4-MD5); Wed, 03 Jun 2009 07:17:59 -0700 (PDT) From: wuzhangjin@gmail.com To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: Arnaud Patard , Atsushi Nemoto , Yan Hua , Zhang Fuxin , Pavel Machek , Wu Zhangjin , Hu Hongbing Subject: [PATCH-v1] Hibernation Support in mips system Date: Wed, 3 Jun 2009 22:17:40 +0800 Message-Id: <6b7278ff10d7c4f9d819792de8742f65147c6855.1244038584.git.wuzj@lemote.com> X-Mailer: git-send-email 1.6.3.1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23218 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips From: Wu Zhangjin This is pulled from the to-mips branch of http://dev.lemote.com/code/linux_loongson, the original author is Hu Hongbing from www.lemote.com according to the feedback from Atsushi Nemoto, Arnaud Patard, Yanhua, Pavel Machek and Ralf Baechle. I removed the a0-a7,v1 registers saving/restoring, added cache/tlb flushing and fpu,dsp registers saving/restoring, and also tuned some coding style problem with the support of scripts/checkpatch.pl. Reviewed-by: Pavel Machek Reviewed-by: Yan Hua Reviewed-by: Arnaud Patard Reviewed-by: Atsushi Nemoto Signed-off-by: Wu Zhangjin Signed-off-by: Hu Hongbing --- arch/mips/Kconfig | 3 ++ arch/mips/Makefile | 3 ++ arch/mips/include/asm/suspend.h | 5 ++- arch/mips/kernel/asm-offsets.c | 13 +++++++ arch/mips/power/Makefile | 1 + arch/mips/power/cpu.c | 41 +++++++++++++++++++++++ arch/mips/power/hibernate.S | 70 +++++++++++++++++++++++++++++++++++++++ 7 files changed, 135 insertions(+), 1 deletions(-) create mode 100644 arch/mips/power/Makefile create mode 100644 arch/mips/power/cpu.c create mode 100644 arch/mips/power/hibernate.S diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index c7d1d08..4423d82 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -2128,6 +2128,9 @@ endmenu menu "Power management options" +config ARCH_HIBERNATION_POSSIBLE + def_bool y + config ARCH_SUSPEND_POSSIBLE def_bool y depends on !SMP diff --git a/arch/mips/Makefile b/arch/mips/Makefile index 6d39fdf..361a30d 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -685,6 +685,9 @@ core-y += arch/mips/kernel/ arch/mips/mm/ arch/mips/math-emu/ drivers-$(CONFIG_OPROFILE) += arch/mips/oprofile/ +# suspend and hibernation support +drivers-$(CONFIG_PM) += arch/mips/power/ + ifdef CONFIG_LASAT rom.bin rom.sw: vmlinux $(Q)$(MAKE) $(build)=arch/mips/lasat/image $@ diff --git a/arch/mips/include/asm/suspend.h b/arch/mips/include/asm/suspend.h index 2562f8f..294cdb6 100644 --- a/arch/mips/include/asm/suspend.h +++ b/arch/mips/include/asm/suspend.h @@ -1,6 +1,9 @@ #ifndef __ASM_SUSPEND_H #define __ASM_SUSPEND_H -/* Somewhen... Maybe :-) */ +static inline int arch_prepare_suspend(void) { return 0; } + +/* References to section boundaries */ +extern const void __nosave_begin, __nosave_end; #endif /* __ASM_SUSPEND_H */ diff --git a/arch/mips/kernel/asm-offsets.c b/arch/mips/kernel/asm-offsets.c index c901c22..8d006ec 100644 --- a/arch/mips/kernel/asm-offsets.c +++ b/arch/mips/kernel/asm-offsets.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include @@ -326,3 +327,15 @@ void output_octeon_cop2_state_defines(void) BLANK(); } #endif + +#ifdef CONFIG_HIBERNATION +void output_pbe_defines(void) +{ + COMMENT(" Linux struct pbe offsets. "); + OFFSET(PBE_ADDRESS, pbe, address); + OFFSET(PBE_ORIG_ADDRESS, pbe, orig_address); + OFFSET(PBE_NEXT, pbe, next); + DEFINE(PBE_SIZE, sizeof(struct pbe)); + BLANK(); +} +#endif diff --git a/arch/mips/power/Makefile b/arch/mips/power/Makefile new file mode 100644 index 0000000..73d56b8 --- /dev/null +++ b/arch/mips/power/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_HIBERNATION) += cpu.o hibernate.o diff --git a/arch/mips/power/cpu.c b/arch/mips/power/cpu.c new file mode 100644 index 0000000..30fd6b5 --- /dev/null +++ b/arch/mips/power/cpu.c @@ -0,0 +1,41 @@ +/* + * Suspend support specific for mips. + * + * Copyright (C) 2009 Lemote Inc. & Insititute of Computing Technology + * Author: Hu Hongbing + * Wu Zhangjin + */ +#include +#include +#include + +static u32 saved_status; +struct pt_regs saved_regs; + +void save_processor_state(void) +{ + saved_status = read_c0_status(); + + if (is_fpu_owner()) + save_fp(current); + if (cpu_has_dsp) + save_dsp(current); +} + +void restore_processor_state(void) +{ + write_c0_status(saved_status); + + if (is_fpu_owner()) + restore_fp(current); + if (cpu_has_dsp) + restore_dsp(current); +} + +int pfn_is_nosave(unsigned long pfn) +{ + unsigned long nosave_begin_pfn = PFN_DOWN(__pa(&__nosave_begin)); + unsigned long nosave_end_pfn = PFN_UP(__pa(&__nosave_end)); + + return (pfn >= nosave_begin_pfn) && (pfn < nosave_end_pfn); +} diff --git a/arch/mips/power/hibernate.S b/arch/mips/power/hibernate.S new file mode 100644 index 0000000..f7c78ff --- /dev/null +++ b/arch/mips/power/hibernate.S @@ -0,0 +1,70 @@ +/* + * Hibernation support specific for mips - temporary page tables + * + * Distribute under GPLv2 + * + * Copyright (C) 2009 Lemote Inc. & Insititute of Computing Technology + * Author: Hu Hongbing + * Wu Zhangjin + */ +#include +#include +#include + +.text +LEAF(swsusp_arch_suspend) + PTR_LA t0, saved_regs + PTR_S ra, PT_R31(t0) + PTR_S sp, PT_R29(t0) + PTR_S fp, PT_R30(t0) + PTR_S gp, PT_R28(t0) + PTR_S s0, PT_R16(t0) + PTR_S s1, PT_R17(t0) + PTR_S s2, PT_R18(t0) + PTR_S s3, PT_R19(t0) + PTR_S s4, PT_R20(t0) + PTR_S s5, PT_R21(t0) + PTR_S s6, PT_R22(t0) + PTR_S s7, PT_R23(t0) + j swsusp_save +END(swsusp_arch_suspend) + +LEAF(swsusp_arch_resume) + PTR_L t0, restore_pblist +0: + PTR_L t1, PBE_ADDRESS(t0) /* source */ + PTR_L t2, PBE_ORIG_ADDRESS(t0) /* destination */ + PTR_ADDIU t3, t1, _PAGE_SIZE +1: + REG_L t8, (t1) + REG_S t8, (t2) + PTR_ADDIU t1, t1, SZREG + PTR_ADDIU t2, t2, SZREG + bne t1, t3, 1b + PTR_L t0, PBE_NEXT(t0) + bnez t0, 0b + /* flush caches to make sure context is in memory */ + PTR_L t0, __flush_cache_all + jalr t0 + /* flush tlb entries */ +#ifdef CONFIG_SMP + jal flush_tlb_all +#else + jal local_flush_tlb_all +#endif + PTR_LA t0, saved_regs + PTR_L ra, PT_R31(t0) + PTR_L sp, PT_R29(t0) + PTR_L fp, PT_R30(t0) + PTR_L gp, PT_R28(t0) + PTR_L s0, PT_R16(t0) + PTR_L s1, PT_R17(t0) + PTR_L s2, PT_R18(t0) + PTR_L s3, PT_R19(t0) + PTR_L s4, PT_R20(t0) + PTR_L s5, PT_R21(t0) + PTR_L s6, PT_R22(t0) + PTR_L s7, PT_R23(t0) + PTR_LI v0, 0x0 + jr ra +END(swsusp_arch_resume) -- 1.6.0.4 From yoichi_yuasa@tripeaks.co.jp Wed Jun 3 16:16:12 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 03 Jun 2009 16:16:22 +0100 (WEST) Received: from mow300.po.2iij.net ([210.128.50.200]:38992 "EHLO mow.po.2iij.net" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20022935AbZFCPQL (ORCPT ); Wed, 3 Jun 2009 16:16:11 +0100 Received: by mow.po.2iij.net (mow300) id n53FG7fm013812; Thu, 4 Jun 2009 00:16:07 +0900 Received: from fulvia (20.8.30.125.dy.iij4u.or.jp [125.30.8.20]) by mbox.po.2iij.net (po-mbox301) id n53FG5rm016663 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NOT); Thu, 4 Jun 2009 00:16:05 +0900 Date: Thu, 4 Jun 2009 00:16:04 +0900 From: Yoichi Yuasa To: Ralf Baechle Cc: yoichi_yuasa@tripeaks.co.jp, linux-mips Subject: [PATCH][MIPS] add DMA declare coherent memory support Message-Id: <20090604001604.9ced2997.yoichi_yuasa@tripeaks.co.jp> Organization: TriPeaks Corporation X-Mailer: Sylpheed 2.5.0 (GTK+ 2.12.12; i486-pc-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23219 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: yoichi_yuasa@tripeaks.co.jp Precedence: bulk X-list: linux-mips Signed-off-by: Yoichi Yuasa diff -pruN -X /home/yuasa/Memo/dontdiff linux-orig/arch/mips/Kconfig linux/arch/mips/Kconfig --- linux-orig/arch/mips/Kconfig 2009-04-21 10:55:44.353177629 +0900 +++ linux/arch/mips/Kconfig 2009-04-21 11:01:02.801170966 +0900 @@ -3,6 +3,7 @@ config MIPS default y select HAVE_IDE select HAVE_OPROFILE + select HAVE_GENERIC_DMA_COHERENT select HAVE_ARCH_KGDB # Horrible source of confusion. Die, die, die ... select EMBEDDED diff -pruN -X /home/yuasa/Memo/dontdiff linux-orig/arch/mips/include/asm/dma-mapping.h linux/arch/mips/include/asm/dma-mapping.h --- linux-orig/arch/mips/include/asm/dma-mapping.h 2009-04-21 10:55:44.549177717 +0900 +++ linux/arch/mips/include/asm/dma-mapping.h 2009-04-21 11:19:40.077177611 +0900 @@ -3,6 +3,7 @@ #include #include +#include void *dma_alloc_noncoherent(struct device *dev, size_t size, dma_addr_t *dma_handle, gfp_t flag); @@ -73,7 +74,6 @@ extern int dma_is_consistent(struct devi extern void dma_cache_sync(struct device *dev, void *vaddr, size_t size, enum dma_data_direction direction); -#if 0 #define ARCH_HAS_DMA_DECLARE_COHERENT_MEMORY extern int dma_declare_coherent_memory(struct device *dev, dma_addr_t bus_addr, @@ -81,6 +81,5 @@ extern int dma_declare_coherent_memory(s extern void dma_release_declared_memory(struct device *dev); extern void * dma_mark_declared_memory_occupied(struct device *dev, dma_addr_t device_addr, size_t size); -#endif #endif /* _ASM_DMA_MAPPING_H */ diff -pruN -X /home/yuasa/Memo/dontdiff linux-orig/arch/mips/mm/dma-default.c linux/arch/mips/mm/dma-default.c --- linux-orig/arch/mips/mm/dma-default.c 2009-04-21 10:55:46.409177601 +0900 +++ linux/arch/mips/mm/dma-default.c 2009-04-21 11:21:17.061177557 +0900 @@ -89,6 +89,9 @@ void *dma_alloc_coherent(struct device * { void *ret; + if (dma_alloc_from_coherent(dev, size, dma_handle, &ret)) + return ret; + gfp = massage_gfp_flags(dev, gfp); ret = (void *) __get_free_pages(gfp, get_order(size)); @@ -120,8 +123,12 @@ EXPORT_SYMBOL(dma_free_noncoherent); void dma_free_coherent(struct device *dev, size_t size, void *vaddr, dma_addr_t dma_handle) { + int order = get_order(size); unsigned long addr = (unsigned long) vaddr; + if (dma_release_from_coherent(dev, order, vaddr)) + return; + plat_unmap_dma_mem(dev, dma_handle); if (!plat_device_is_coherent(dev)) From tsbogend@alpha.franken.de Wed Jun 3 16:32:34 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 03 Jun 2009 16:32:41 +0100 (WEST) Received: from elvis.franken.de ([193.175.24.41]:46586 "EHLO elvis.franken.de" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20022946AbZFCPce (ORCPT ); Wed, 3 Jun 2009 16:32:34 +0100 Received: from uucp (helo=solo.franken.de) by elvis.franken.de with local-bsmtp (Exim 3.36 #1) id 1MBsS8-00045P-00; Wed, 03 Jun 2009 17:32:32 +0200 Received: by solo.franken.de (Postfix, from userid 1000) id 265FFC34F9; Wed, 3 Jun 2009 17:31:52 +0200 (CEST) Date: Wed, 3 Jun 2009 17:31:52 +0200 From: Thomas Bogendoerfer To: Yoichi Yuasa Cc: Ralf Baechle , linux-mips Subject: Re: [PATCH][MIPS] add DMA declare coherent memory support Message-ID: <20090603153151.GA4009@alpha.franken.de> References: <20090604001604.9ced2997.yoichi_yuasa@tripeaks.co.jp> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20090604001604.9ced2997.yoichi_yuasa@tripeaks.co.jp> User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23220 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: tsbogend@alpha.franken.de Precedence: bulk X-list: linux-mips On Thu, Jun 04, 2009 at 12:16:04AM +0900, Yoichi Yuasa wrote: > > Signed-off-by: Yoichi Yuasa a little bit more description what this is all about would be quite helpful. I also see a problem as there is at least one MIPS machine (SGI IP28), which doesn't support coherent memory (at least not without playing dirty games with the memory controller, which in return makes the machine slow). Thomas. -- Crap can work. Given enough thrust pigs will fly, but it's not necessary a good idea. [ RFC1925, 2.3 ] From manuel.lauss@googlemail.com Wed Jun 3 17:18:23 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 03 Jun 2009 17:18:30 +0100 (WEST) Received: from mail-fx0-f223.google.com ([209.85.220.223]:49400 "EHLO mail-fx0-f223.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20021958AbZFCQSX (ORCPT ); Wed, 3 Jun 2009 17:18:23 +0100 Received: by fxm23 with SMTP id 23so114368fxm.0 for ; Wed, 03 Jun 2009 09:18:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer; bh=E3vPhhu+trF5Om9wV6hJgzmgn+L1lOg0SURl2EAo5AU=; b=TTS6SuaxZJfcJ+mF8lEfGvHUSVaFDfIuKeatNiISA+9KcYwEFOCr4mG64dkF8qzLyH OuPCkqfSCrQrJgdO+wroIGJj6rCgYiKcRu3kJSWW4y3cTWRkAMu7yFMjAa6bCDugQYdo 5/L4WiZG5FYeTHMjDQHuBwXKe+YbPst0fO8iY= DomainKey-Signature: a=rsa-sha1; c=nofws; d=googlemail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer; b=YTAkg2NdcOnUP8nv6meAqSdHJsCp2wkY9OIFX7uuido1OWqCUSrTEfPGAA8ntPkSyX xKKkDzyW85ItyzTTbjkgDOeq5m0RwZnvsN6sW0NsuMXw3m+kHaux1deokocJXwR9G4jN vUl+q7wH/4pNJNt4W/XNvNALWZ9s1iuDHyU3k= Received: by 10.103.182.3 with SMTP id j3mr722757mup.115.1244045897015; Wed, 03 Jun 2009 09:18:17 -0700 (PDT) Received: from localhost.localdomain (p5496DB58.dip.t-dialin.net [84.150.219.88]) by mx.google.com with ESMTPS id u26sm37723mug.22.2009.06.03.09.18.15 (version=TLSv1/SSLv3 cipher=RC4-MD5); Wed, 03 Jun 2009 09:18:16 -0700 (PDT) From: Manuel Lauss To: Linux-MIPS , Ralf Baechle Cc: Manuel Lauss Subject: [PATCH 0/5] Alchemy GPIO rewrite v6 Date: Wed, 3 Jun 2009 18:18:03 +0200 Message-Id: <1244045888-16259-1-git-send-email-manuel.lauss@gmail.com> X-Mailer: git-send-email 1.6.3.1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23221 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips Rewrite Alchemy GPIO support to be compatible with the Linux GPIO framework, both with and without gpiolib. For a list of justifications, see blurb in patch #2. Patches #3-#5 replace a few open-coded GPIO accesses in the board files with calls to the new gpio functions. Tested on DB1200 and a custom Au1200 platform. v6 - renamed gpio.[ch] to gpio-au1000.[ch], since this code only affects pre-Au1300 chips. Should make integration of Au1300 GPIO a bit easier. v5 - fix gpio1 bug in inlined gpio_get_value() v4 - GPIO2 shared interrupt management, styling. v3 - fixed thinko in alchemy_gpio2_set_value (16->32 bit) v2 - added gpio_to_irq and irq_to_gpio, some renaming. Manuel Lauss (5): Alchemy: remove unused au1000_gpio.h header Alchemy: rewrite GPIO support. Alchemy: mtx-1: use linux gpio api. Alchemy: xxs1500: use linux gpio api. Alchemy: devboards: convert to gpio calls. arch/mips/Makefile | 5 +- arch/mips/alchemy/Kconfig | 19 +- arch/mips/alchemy/common/Makefile | 11 +- arch/mips/alchemy/common/gpio-au1000.c | 130 +++++ arch/mips/alchemy/common/gpio.c | 201 ------- arch/mips/alchemy/common/reset.c | 5 +- arch/mips/alchemy/devboards/db1x00/board_setup.c | 8 +- arch/mips/alchemy/devboards/pb1000/board_setup.c | 10 +- arch/mips/alchemy/devboards/pb1100/board_setup.c | 3 +- arch/mips/alchemy/devboards/pb1500/board_setup.c | 10 +- arch/mips/alchemy/devboards/pm.c | 2 +- arch/mips/alchemy/mtx-1/board_setup.c | 24 +- arch/mips/alchemy/xxs1500/board_setup.c | 21 +- arch/mips/include/asm/mach-au1x00/au1000_gpio.h | 56 -- arch/mips/include/asm/mach-au1x00/gpio-au1000.h | 604 ++++++++++++++++++++++ arch/mips/include/asm/mach-au1x00/gpio.h | 35 +- 16 files changed, 818 insertions(+), 326 deletions(-) create mode 100644 arch/mips/alchemy/common/gpio-au1000.c delete mode 100644 arch/mips/alchemy/common/gpio.c delete mode 100644 arch/mips/include/asm/mach-au1x00/au1000_gpio.h create mode 100644 arch/mips/include/asm/mach-au1x00/gpio-au1000.h From manuel.lauss@googlemail.com Wed Jun 3 17:18:47 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 03 Jun 2009 17:18:55 +0100 (WEST) Received: from mail-fx0-f223.google.com ([209.85.220.223]:49400 "EHLO mail-fx0-f223.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20022239AbZFCQSX (ORCPT ); Wed, 3 Jun 2009 17:18:23 +0100 Received: by mail-fx0-f223.google.com with SMTP id 23so114368fxm.0 for ; Wed, 03 Jun 2009 09:18:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer:in-reply-to:references; bh=uWLEY5CJ1YSC0WXaEwNXqeiM403RaaJ762vg8OHYyOk=; b=ij5xiGurOw6tb7+C6+4XUNjM1jWlCZo8gfdEYdXFNPzdFJtHBAI1D0wquEPhc8Ju0c w+w1LtDn3GLNTmUuN7PWLRK1eE/rLRK6Y3Al219f7M4hynacpDFgmyoOMiJzUK+t3EYe n/U5n2EorLn/Cu0xvo75C/JOtJ1JX/wleRJo8= DomainKey-Signature: a=rsa-sha1; c=nofws; d=googlemail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; b=b31nAKK4Pk55kPqP8NYz0yl9tFjzQH356ta9fC4u6D+uNWIwR30A2xkjogyU2AphcX MGO5jmyx/1y52OpFUraMvxxKQFS5IGZdaHbrxyJ5drz17hk24hWyDZGybo7ReLXS9jKn EiMAiV+B5Ur2yIWn3iLBKy4uRKlg4ERaA0TZk= Received: by 10.103.160.9 with SMTP id m9mr656170muo.96.1244045902929; Wed, 03 Jun 2009 09:18:22 -0700 (PDT) Received: from localhost.localdomain (p5496DB58.dip.t-dialin.net [84.150.219.88]) by mx.google.com with ESMTPS id u26sm37723mug.22.2009.06.03.09.18.22 (version=TLSv1/SSLv3 cipher=RC4-MD5); Wed, 03 Jun 2009 09:18:22 -0700 (PDT) From: Manuel Lauss To: Linux-MIPS , Ralf Baechle Cc: Manuel Lauss Subject: [PATCH 5/5] Alchemy: devboards: convert to gpio calls. Date: Wed, 3 Jun 2009 18:18:08 +0200 Message-Id: <1244045888-16259-6-git-send-email-manuel.lauss@gmail.com> X-Mailer: git-send-email 1.6.3.1 In-Reply-To: <1244045888-16259-5-git-send-email-manuel.lauss@gmail.com> References: <1244045888-16259-1-git-send-email-manuel.lauss@gmail.com> <1244045888-16259-2-git-send-email-manuel.lauss@gmail.com> <1244045888-16259-3-git-send-email-manuel.lauss@gmail.com> <1244045888-16259-4-git-send-email-manuel.lauss@gmail.com> <1244045888-16259-5-git-send-email-manuel.lauss@gmail.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23222 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips Replace a few open-coded GPIO register accesses with gpiolib calls. Signed-off-by: Manuel Lauss --- arch/mips/alchemy/common/reset.c | 5 +++-- arch/mips/alchemy/devboards/db1x00/board_setup.c | 8 ++------ arch/mips/alchemy/devboards/pb1000/board_setup.c | 10 +++++++--- arch/mips/alchemy/devboards/pb1100/board_setup.c | 3 ++- arch/mips/alchemy/devboards/pb1500/board_setup.c | 10 ++++++---- arch/mips/alchemy/devboards/pm.c | 2 +- 6 files changed, 21 insertions(+), 17 deletions(-) diff --git a/arch/mips/alchemy/common/reset.c b/arch/mips/alchemy/common/reset.c index 0191c93..0ec33dc 100644 --- a/arch/mips/alchemy/common/reset.c +++ b/arch/mips/alchemy/common/reset.c @@ -27,8 +27,9 @@ * 675 Mass Ave, Cambridge, MA 02139, USA. */ -#include +#include +#include #include void au1000_restart(char *command) @@ -161,7 +162,7 @@ void au1000_halt(void) #else printk(KERN_NOTICE "\n** You can safely turn off the power\n"); #ifdef CONFIG_MIPS_MIRAGE - au_writel((1 << 26) | (1 << 10), GPIO2_OUTPUT); + gpio_direction_output(10, 1); #endif #ifdef CONFIG_MIPS_DB1200 au_writew(au_readw(0xB980001C) | (1 << 14), 0xB980001C); diff --git a/arch/mips/alchemy/devboards/db1x00/board_setup.c b/arch/mips/alchemy/devboards/db1x00/board_setup.c index a75ffbf..5fba562 100644 --- a/arch/mips/alchemy/devboards/db1x00/board_setup.c +++ b/arch/mips/alchemy/devboards/db1x00/board_setup.c @@ -95,11 +95,8 @@ void __init board_setup(void) bcsr->pcmcia = 0x0000; /* turn off PCMCIA power */ #ifdef CONFIG_MIPS_MIRAGE - /* Enable GPIO[31:0] inputs */ - au_writel(0, SYS_PININPUTEN); - /* GPIO[20] is output, tristate the other input primary GPIOs */ - au_writel(~(1 << 20), SYS_TRIOUTCLR); + alchemy_gpio_direction_output(20, 0); /* Set GPIO[210:208] instead of SSI_0 */ pin_func = au_readl(SYS_PINFUNC) | SYS_PF_S0; @@ -118,8 +115,7 @@ void __init board_setup(void) * Enable speaker amplifier. This should * be part of the audio driver. */ - au_writel(au_readl(GPIO2_DIR) | 0x200, GPIO2_DIR); - au_writel(0x02000200, GPIO2_OUTPUT); + alchemy_gpio_direction_output(9, 1); #endif au_sync(); diff --git a/arch/mips/alchemy/devboards/pb1000/board_setup.c b/arch/mips/alchemy/devboards/pb1000/board_setup.c index aed2fde..cd27354 100644 --- a/arch/mips/alchemy/devboards/pb1000/board_setup.c +++ b/arch/mips/alchemy/devboards/pb1000/board_setup.c @@ -24,6 +24,7 @@ */ #include +#include #include #include #include @@ -130,8 +131,11 @@ void __init board_setup(void) pin_func |= SYS_PF_USB; au_writel(pin_func, SYS_PINFUNC); - au_writel(0x2800, SYS_TRIOUTCLR); - au_writel(0x0030, SYS_OUTPUTCLR); + + alchemy_gpio_direction_input(11); + alchemy_gpio_direction_input(13); + alchemy_gpio_direction_output(4, 0); + alchemy_gpio_direction_output(5, 0); #endif /* defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) */ /* Make GPIO 15 an input (for interrupt line) */ @@ -140,7 +144,7 @@ void __init board_setup(void) pin_func |= SYS_PF_I2S; au_writel(pin_func, SYS_PINFUNC); - au_writel(0x8000, SYS_TRIOUTCLR); + alchemy_gpio_direction_input(15); static_cfg0 = au_readl(MEM_STCFG0) & ~0xc00; au_writel(static_cfg0, MEM_STCFG0); diff --git a/arch/mips/alchemy/devboards/pb1100/board_setup.c b/arch/mips/alchemy/devboards/pb1100/board_setup.c index 4df57fa..f872842 100644 --- a/arch/mips/alchemy/devboards/pb1100/board_setup.c +++ b/arch/mips/alchemy/devboards/pb1100/board_setup.c @@ -86,9 +86,10 @@ void __init board_setup(void) argptr = prom_getcmdline(); #endif + /* Set AUX clock to 12 MHz * 8 = 96 MHz */ au_writel(8, SYS_AUXPLL); - au_writel(0, SYS_PININPUTEN); + alchemy_gpio1_input_enable(); udelay(100); #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) diff --git a/arch/mips/alchemy/devboards/pb1500/board_setup.c b/arch/mips/alchemy/devboards/pb1500/board_setup.c index fed3b09..d7a5656 100644 --- a/arch/mips/alchemy/devboards/pb1500/board_setup.c +++ b/arch/mips/alchemy/devboards/pb1500/board_setup.c @@ -23,8 +23,9 @@ * 675 Mass Ave, Cambridge, MA 02139, USA. */ -#include #include +#include +#include #include #include @@ -90,11 +91,12 @@ void __init board_setup(void) au_writel(0, SYS_PINSTATERD); udelay(100); -#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) - /* GPIO201 is input for PCMCIA card detect */ /* GPIO203 is input for PCMCIA interrupt request */ - au_writel(au_readl(GPIO2_DIR) & ~((1 << 1) | (1 << 3)), GPIO2_DIR); + alchemy_gpio_direction_input(201); + alchemy_gpio_direction_input(203); + +#if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) /* Zero and disable FREQ2 */ sys_freqctrl = au_readl(SYS_FREQCTRL0); diff --git a/arch/mips/alchemy/devboards/pm.c b/arch/mips/alchemy/devboards/pm.c index d5eb9c3..5db8512 100644 --- a/arch/mips/alchemy/devboards/pm.c +++ b/arch/mips/alchemy/devboards/pm.c @@ -26,7 +26,7 @@ static unsigned long db1x_pm_last_wakesrc; static int db1x_pm_enter(suspend_state_t state) { /* enable GPIO based wakeup */ - au_writel(1, SYS_PININPUTEN); + alchemy_gpio1_input_enable(); /* clear and setup wake cause and source */ au_writel(0, SYS_WAKEMSK); -- 1.6.3.1 From manuel.lauss@googlemail.com Wed Jun 3 17:19:12 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 03 Jun 2009 17:19:18 +0100 (WEST) Received: from mail-bw0-f225.google.com ([209.85.218.225]:44539 "EHLO mail-bw0-f225.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20022326AbZFCQSZ (ORCPT ); Wed, 3 Jun 2009 17:18:25 +0100 Received: by bwz25 with SMTP id 25so113469bwz.0 for ; Wed, 03 Jun 2009 09:18:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer:in-reply-to:references; bh=hzId0WFjoSSdphtG/19V9nMKCT9iiJpdG1reZzPJ094=; b=CXMUQLlt1HkiQfqMiW3rdkJm0CpI0POFFD31zhGk6XAn+/bA1jAd6AN+4NJbSIdLnl fgjEIhscVZh4R7lcXsjXGdB7uBIDUPomQZxBwAir420VNMFMcTH5CZSObHaU7By+1c93 +qVgm6Yp8Un6bIrxCmuTcrCf/ntYnmcke8PMs= DomainKey-Signature: a=rsa-sha1; c=nofws; d=googlemail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; b=MGociG5sdwWHU973ismJ8yyKCluyJS384st/kBI9OtdLt0mLzXtBntVqKMqtmR5RsI MtvQdgdSgS/WpvBK53Wz/t5UiKdpCnjuIU2Ryj2v9DTu9w/SQO9V8ZT2sUWt1yZdFlIB wfwKJEhtJUbU6eVTBvYNyDkmXxD2SnDQz26Js= Received: by 10.103.131.13 with SMTP id i13mr755133mun.13.1244045898166; Wed, 03 Jun 2009 09:18:18 -0700 (PDT) Received: from localhost.localdomain (p5496DB58.dip.t-dialin.net [84.150.219.88]) by mx.google.com with ESMTPS id u26sm37723mug.22.2009.06.03.09.18.17 (version=TLSv1/SSLv3 cipher=RC4-MD5); Wed, 03 Jun 2009 09:18:17 -0700 (PDT) From: Manuel Lauss To: Linux-MIPS , Ralf Baechle Cc: Manuel Lauss Subject: [PATCH 1/5] Alchemy: remove unused au1000_gpio.h header Date: Wed, 3 Jun 2009 18:18:04 +0200 Message-Id: <1244045888-16259-2-git-send-email-manuel.lauss@gmail.com> X-Mailer: git-send-email 1.6.3.1 In-Reply-To: <1244045888-16259-1-git-send-email-manuel.lauss@gmail.com> References: <1244045888-16259-1-git-send-email-manuel.lauss@gmail.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23223 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips Signed-off-by: Manuel Lauss --- arch/mips/include/asm/mach-au1x00/au1000_gpio.h | 56 ----------------------- 1 files changed, 0 insertions(+), 56 deletions(-) delete mode 100644 arch/mips/include/asm/mach-au1x00/au1000_gpio.h diff --git a/arch/mips/include/asm/mach-au1x00/au1000_gpio.h b/arch/mips/include/asm/mach-au1x00/au1000_gpio.h deleted file mode 100644 index d8c96fd..0000000 --- a/arch/mips/include/asm/mach-au1x00/au1000_gpio.h +++ /dev/null @@ -1,56 +0,0 @@ -/* - * FILE NAME au1000_gpio.h - * - * BRIEF MODULE DESCRIPTION - * API to Alchemy Au1xx0 GPIO device. - * - * Author: MontaVista Software, Inc. - * Steve Longerbeam - * - * Copyright 2001, 2008 MontaVista Software Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#ifndef __AU1000_GPIO_H -#define __AU1000_GPIO_H - -#include - -#define AU1000GPIO_IOC_MAGIC 'A' - -#define AU1000GPIO_IN _IOR(AU1000GPIO_IOC_MAGIC, 0, int) -#define AU1000GPIO_SET _IOW(AU1000GPIO_IOC_MAGIC, 1, int) -#define AU1000GPIO_CLEAR _IOW(AU1000GPIO_IOC_MAGIC, 2, int) -#define AU1000GPIO_OUT _IOW(AU1000GPIO_IOC_MAGIC, 3, int) -#define AU1000GPIO_TRISTATE _IOW(AU1000GPIO_IOC_MAGIC, 4, int) -#define AU1000GPIO_AVAIL_MASK _IOR(AU1000GPIO_IOC_MAGIC, 5, int) - -#ifdef __KERNEL__ -extern u32 get_au1000_avail_gpio_mask(void); -extern int au1000gpio_tristate(u32 data); -extern int au1000gpio_in(u32 *data); -extern int au1000gpio_set(u32 data); -extern int au1000gpio_clear(u32 data); -extern int au1000gpio_out(u32 data); -#endif - -#endif -- 1.6.3.1 From manuel.lauss@googlemail.com Wed Jun 3 17:19:35 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 03 Jun 2009 17:19:42 +0100 (WEST) Received: from mail-bw0-f225.google.com ([209.85.218.225]:57234 "EHLO mail-bw0-f225.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20022336AbZFCQS0 (ORCPT ); Wed, 3 Jun 2009 17:18:26 +0100 Received: by bwz25 with SMTP id 25so113501bwz.0 for ; Wed, 03 Jun 2009 09:18:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer:in-reply-to:references; bh=68HdVqHCweH5OHusGpsypOFc+VyItaGmh2LCyMy10xc=; b=janmorfPRato0LHcRcGkNq63m/0yA764iNADxR9K6XpQq6yGrexOLKkhERek+mmoYQ B3WTYnEHzp5hPgar3eqn01l9xwDH78Ol9I/MsU1nn/4IzfZ3JGtVQCHM8WW6T03lSfYf REQ7gDd8U1RjNt600l8cvYwI99oJRFVyn+ku0= DomainKey-Signature: a=rsa-sha1; c=nofws; d=googlemail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; b=shIyO30afbA56l6IRUkaPJ8lYflBWrwJH6Npl4gmbvFmMWzWbMmfrw2N6VXnOV+izx tmur3gGXU+r7T7TKa9GPYwaz3wAZYa+pdnwrWo5VY3ekC8iMM/lU1iuxYCb0rlISLOOU 78SGJQMDIRQXCj1EEEsx2tM9So70RdVVF55bE= Received: by 10.103.226.10 with SMTP id d10mr749918mur.35.1244045900618; Wed, 03 Jun 2009 09:18:20 -0700 (PDT) Received: from localhost.localdomain (p5496DB58.dip.t-dialin.net [84.150.219.88]) by mx.google.com with ESMTPS id u26sm37723mug.22.2009.06.03.09.18.19 (version=TLSv1/SSLv3 cipher=RC4-MD5); Wed, 03 Jun 2009 09:18:20 -0700 (PDT) From: Manuel Lauss To: Linux-MIPS , Ralf Baechle Cc: Manuel Lauss Subject: [PATCH 3/5] Alchemy: mtx-1: use linux gpio api. Date: Wed, 3 Jun 2009 18:18:06 +0200 Message-Id: <1244045888-16259-4-git-send-email-manuel.lauss@gmail.com> X-Mailer: git-send-email 1.6.3.1 In-Reply-To: <1244045888-16259-3-git-send-email-manuel.lauss@gmail.com> References: <1244045888-16259-1-git-send-email-manuel.lauss@gmail.com> <1244045888-16259-2-git-send-email-manuel.lauss@gmail.com> <1244045888-16259-3-git-send-email-manuel.lauss@gmail.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23224 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips Replace a few GPIO register accesses in the board init code with calls to the gpio api. Signed-off-by: Manuel Lauss --- arch/mips/alchemy/mtx-1/board_setup.c | 24 +++++++++++++----------- 1 files changed, 13 insertions(+), 11 deletions(-) diff --git a/arch/mips/alchemy/mtx-1/board_setup.c b/arch/mips/alchemy/mtx-1/board_setup.c index 8ed1ae1..3356a0d 100644 --- a/arch/mips/alchemy/mtx-1/board_setup.c +++ b/arch/mips/alchemy/mtx-1/board_setup.c @@ -28,6 +28,7 @@ * 675 Mass Ave, Cambridge, MA 02139, USA. */ +#include #include #include @@ -55,10 +56,11 @@ void __init board_setup(void) } #endif + alchemy_gpio2_enable(); + #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) /* Enable USB power switch */ - au_writel(au_readl(GPIO2_DIR) | 0x10, GPIO2_DIR); - au_writel(0x100000, GPIO2_OUTPUT); + alchemy_gpio_direction_output(4, 0); #endif /* defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) */ #ifdef CONFIG_PCI @@ -74,14 +76,14 @@ void __init board_setup(void) /* Initialize GPIO */ au_writel(0xFFFFFFFF, SYS_TRIOUTCLR); - au_writel(0x00000001, SYS_OUTPUTCLR); /* set M66EN (PCI 66MHz) to OFF */ - au_writel(0x00000008, SYS_OUTPUTSET); /* set PCI CLKRUN# to OFF */ - au_writel(0x00000002, SYS_OUTPUTSET); /* set EXT_IO3 ON */ - au_writel(0x00000020, SYS_OUTPUTCLR); /* set eth PHY TX_ER to OFF */ + alchemy_gpio_direction_output(0, 0); /* set M66EN (PCI 66MHz) to OFF */ + alchemy_gpio_direction_output(3, 1); /* set PCI CLKRUN# to OFF */ + alchemy_gpio_direction_output(1, 1); /* set EXT_IO3 ON */ + alchemy_gpio_direction_output(5, 0); /* set eth PHY TX_ER to OFF */ /* Enable LED and set it to green */ - au_writel(au_readl(GPIO2_DIR) | 0x1800, GPIO2_DIR); - au_writel(0x18000800, GPIO2_OUTPUT); + alchemy_gpio_direction_output(211, 1); /* green on */ + alchemy_gpio_direction_output(212, 0); /* red off */ board_pci_idsel = mtx1_pci_idsel; @@ -101,10 +103,10 @@ mtx1_pci_idsel(unsigned int devsel, int assert) if (assert && devsel != 0) /* Suppress signal to Cardbus */ - au_writel(0x00000002, SYS_OUTPUTCLR); /* set EXT_IO3 OFF */ + gpio_set_value(1, 0); /* set EXT_IO3 OFF */ else - au_writel(0x00000002, SYS_OUTPUTSET); /* set EXT_IO3 ON */ + gpio_set_value(1, 1); /* set EXT_IO3 ON */ + au_sync_udelay(1); return 1; } - -- 1.6.3.1 From manuel.lauss@googlemail.com Wed Jun 3 17:19:59 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 03 Jun 2009 17:20:07 +0100 (WEST) Received: from mail-fx0-f223.google.com ([209.85.220.223]:57831 "EHLO mail-fx0-f223.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20022339AbZFCQS0 (ORCPT ); Wed, 3 Jun 2009 17:18:26 +0100 Received: by fxm23 with SMTP id 23so114397fxm.0 for ; Wed, 03 Jun 2009 09:18:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer:in-reply-to:references; bh=b3kB7Yn0HfhkyUgfxqj1HL6vyviO5FB0QueBoEZte94=; b=Tc7a1T5pkRtzvl8/mtxE0OaDOJt4xvN0JFkebd0HyPoqvqaLH3K+X3/Oh4MRks4oal CEBl/o0sh6a/aXl9GKSBAHX2PtDmrdNHEcR2VQIEwIlOQ20pHp5pIRCwp4xqDMPRA9Pg EhmemWrp+h8r5CCS1qZGINF9sT3AzJ2PGImCM= DomainKey-Signature: a=rsa-sha1; c=nofws; d=googlemail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; b=JFJi8CQf+by2rMIjc3PeabmRaQ9C9CqapkVNWBl/6IqQ6Ddn1SUDEuKZhtBVXGJBCO CW0xhROQc8e/2s+icYYZzYkCEQoCkjewwKXRAWkn/2Xyb855wTmgQ27vWzAwpmKNEgbm ipwTlfjf1GtRSIkmpdX3M6c0khMlU/aYLIcoo= Received: by 10.103.231.16 with SMTP id i16mr762531mur.7.1244045899693; Wed, 03 Jun 2009 09:18:19 -0700 (PDT) Received: from localhost.localdomain (p5496DB58.dip.t-dialin.net [84.150.219.88]) by mx.google.com with ESMTPS id u26sm37723mug.22.2009.06.03.09.18.18 (version=TLSv1/SSLv3 cipher=RC4-MD5); Wed, 03 Jun 2009 09:18:19 -0700 (PDT) From: Manuel Lauss To: Linux-MIPS , Ralf Baechle Cc: Manuel Lauss Subject: [PATCH 2/5] Alchemy: rewrite GPIO support. Date: Wed, 3 Jun 2009 18:18:05 +0200 Message-Id: <1244045888-16259-3-git-send-email-manuel.lauss@gmail.com> X-Mailer: git-send-email 1.6.3.1 In-Reply-To: <1244045888-16259-2-git-send-email-manuel.lauss@gmail.com> References: <1244045888-16259-1-git-send-email-manuel.lauss@gmail.com> <1244045888-16259-2-git-send-email-manuel.lauss@gmail.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23225 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips The current in-kernel Alchemy GPIO support is far too inflexible for all my use cases. To address this, the following changes are made: * create generic functions which deal with manipulating the on-chip GPIO1/2 blocks. Such functions are universally useful. * Macros for GPIO2 shared interrupt management and block control. * support for both built-in CONFIG_GPIOLIB and fast, inlined GPIO macros. If CONFIG_GPIOLIB is not enabled, provide linux gpio framework compatibility by directly inlining the GPIO1/2 functions. GPIO access is limited to on-chip ones and they can be accessed as documented in the datasheets (GPIO0-31 and 200-215). If CONFIG_GPIOLIB is selected, two (2) gpio_chip-s, one for GPIO1 and one for GPIO2, are registered. GPIOs can still be accessed by using the numberspace established in the databooks. However this is not yet flexible enough for my uses: My Alchemy systems have a documented "external" gpio interface (fixed, different numberspace) and can support a variety of baseboards, some of which are equipped with I2C gpio expanders. I want to be able to provide the default 16 GPIOs of the CPU board numbered as 0..15 and also support gpio expanders, if present, starting as gpio16. To achieve this, a new Kconfig symbol for Alchemy is introduced, CONFIG_ALCHEMY_GPIO_INDIRECT, which boards can enable to signal that they don't want the Alchemy numberspace exposed to the outside world, but instead want to provide their own. Boards are now respon- sible for providing the linux gpio interface glue code (either in a custom gpio.h header (in board include directory) or with gpio_chips). To make the board-specific inlined gpio functions work, the MIPS Makefile must be changed so that the mach-au1x00/gpio.h header is included _after_ the board headers, by moving the inclusion of the mach-au1x00/ to the end of the header list. see arch/mips/include/asm/mach-au1x00/gpio.h for more info. Acked-by: Florian Fainelli Signed-off-by: Manuel Lauss --- arch/mips/Makefile | 5 +- arch/mips/alchemy/Kconfig | 19 +- arch/mips/alchemy/common/Makefile | 11 +- arch/mips/alchemy/common/gpio-au1000.c | 130 +++++ arch/mips/alchemy/common/gpio.c | 201 -------- arch/mips/include/asm/mach-au1x00/gpio-au1000.h | 604 +++++++++++++++++++++++ arch/mips/include/asm/mach-au1x00/gpio.h | 35 +-- 7 files changed, 772 insertions(+), 233 deletions(-) create mode 100644 arch/mips/alchemy/common/gpio-au1000.c delete mode 100644 arch/mips/alchemy/common/gpio.c create mode 100644 arch/mips/include/asm/mach-au1x00/gpio-au1000.h diff --git a/arch/mips/Makefile b/arch/mips/Makefile index c4cae9e..c7ddef1 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -184,7 +184,6 @@ load-$(CONFIG_MACH_JAZZ) += 0xffffffff80080000 # Common Alchemy Au1x00 stuff # core-$(CONFIG_SOC_AU1X00) += arch/mips/alchemy/common/ -cflags-$(CONFIG_SOC_AU1X00) += -I$(srctree)/arch/mips/include/asm/mach-au1x00 # # AMD Alchemy Pb1000 eval board @@ -282,6 +281,10 @@ load-$(CONFIG_MIPS_MTX1) += 0xffffffff80100000 libs-$(CONFIG_MIPS_XXS1500) += arch/mips/alchemy/xxs1500/ load-$(CONFIG_MIPS_XXS1500) += 0xffffffff80100000 +# must be last for Alchemy systems for GPIO to work properly +cflags-$(CONFIG_SOC_AU1X00) += -I$(srctree)/arch/mips/include/asm/mach-au1x00 + + # # Cobalt Server # diff --git a/arch/mips/alchemy/Kconfig b/arch/mips/alchemy/Kconfig index 8128aeb..00b498e 100644 --- a/arch/mips/alchemy/Kconfig +++ b/arch/mips/alchemy/Kconfig @@ -1,3 +1,14 @@ +# au1000-style gpio +config ALCHEMY_GPIO_AU1000 + bool + +# select this in your board config if you don't want to use the gpio +# namespace as documented in the manuals. In this case however you need +# to create the necessary gpio_* functions in your board code/headers! +# see arch/mips/include/asm/mach-au1x00/gpio.h for more information. +config ALCHEMY_GPIO_INDIRECT + def_bool n + choice prompt "Machine type" depends on MACH_ALCHEMY @@ -108,22 +119,27 @@ endchoice config SOC_AU1000 bool select SOC_AU1X00 + select ALCHEMY_GPIO_AU1000 config SOC_AU1100 bool select SOC_AU1X00 + select ALCHEMY_GPIO_AU1000 config SOC_AU1500 bool select SOC_AU1X00 + select ALCHEMY_GPIO_AU1000 config SOC_AU1550 bool select SOC_AU1X00 + select ALCHEMY_GPIO_AU1000 config SOC_AU1200 bool select SOC_AU1X00 + select ALCHEMY_GPIO_AU1000 config SOC_AU1X00 bool @@ -134,4 +150,5 @@ config SOC_AU1X00 select SYS_HAS_CPU_MIPS32_R1 select SYS_SUPPORTS_32BIT_KERNEL select SYS_SUPPORTS_APM_EMULATION - select ARCH_REQUIRE_GPIOLIB + select GENERIC_GPIO + select ARCH_WANT_OPTIONAL_GPIOLIB diff --git a/arch/mips/alchemy/common/Makefile b/arch/mips/alchemy/common/Makefile index d50d476..36895c4 100644 --- a/arch/mips/alchemy/common/Makefile +++ b/arch/mips/alchemy/common/Makefile @@ -7,7 +7,16 @@ obj-y += prom.o irq.o puts.o time.o reset.o \ clocks.o platform.o power.o setup.o \ - sleeper.o dma.o dbdma.o gpio.o + sleeper.o dma.o dbdma.o + +ifeq (CONFIG_ALCHEMY_GPIO_INDIRECT,) +ifeq (CONFIG_ALCHEMY_GPIO_AU1000,y) + +# Build default gpiolib for au1000-style gpio +obj-y += gpio-au1000.o + +endif +endif obj-$(CONFIG_PCI) += pci.o diff --git a/arch/mips/alchemy/common/gpio-au1000.c b/arch/mips/alchemy/common/gpio-au1000.c new file mode 100644 index 0000000..3e7212e --- /dev/null +++ b/arch/mips/alchemy/common/gpio-au1000.c @@ -0,0 +1,130 @@ +/* + * Copyright (C) 2007-2009, OpenWrt.org, Florian Fainelli + * GPIO support for Au1000, Au1500, Au1100, Au1550 and Au12x0. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + * Notes : + * au1000 SoC have only one GPIO block : GPIO1 + * Au1100, Au15x0, Au12x0 have a second one : GPIO2 + */ + +#include +#include +#include +#include +#include + +#include +#include + +#if !defined(CONFIG_SOC_AU1000) +static int gpio2_get(struct gpio_chip *chip, unsigned offset) +{ + return alchemy_gpio2_get_value(offset + ALCHEMY_GPIO2_BASE); +} + +static void gpio2_set(struct gpio_chip *chip, unsigned offset, int value) +{ + alchemy_gpio2_set_value(offset + ALCHEMY_GPIO2_BASE, value); +} + +static int gpio2_direction_input(struct gpio_chip *chip, unsigned offset) +{ + return alchemy_gpio2_direction_input(offset + ALCHEMY_GPIO2_BASE); +} + +static int gpio2_direction_output(struct gpio_chip *chip, unsigned offset, + int value) +{ + return alchemy_gpio2_direction_output(offset + ALCHEMY_GPIO2_BASE, + value); +} + +static int gpio2_to_irq(struct gpio_chip *chip, unsigned offset) +{ + return alchemy_gpio2_to_irq(offset + ALCHEMY_GPIO2_BASE); +} +#endif /* !defined(CONFIG_SOC_AU1000) */ + +static int gpio1_get(struct gpio_chip *chip, unsigned offset) +{ + return alchemy_gpio1_get_value(offset + ALCHEMY_GPIO1_BASE); +} + +static void gpio1_set(struct gpio_chip *chip, + unsigned offset, int value) +{ + alchemy_gpio1_set_value(offset + ALCHEMY_GPIO1_BASE, value); +} + +static int gpio1_direction_input(struct gpio_chip *chip, unsigned offset) +{ + return alchemy_gpio1_direction_input(offset + ALCHEMY_GPIO1_BASE); +} + +static int gpio1_direction_output(struct gpio_chip *chip, + unsigned offset, int value) +{ + return alchemy_gpio1_direction_output(offset + ALCHEMY_GPIO1_BASE, + value); +} + +static int gpio1_to_irq(struct gpio_chip *chip, unsigned offset) +{ + return alchemy_gpio1_to_irq(offset + ALCHEMY_GPIO1_BASE); +} + +struct gpio_chip alchemy_gpio_chip[] = { + [0] = { + .label = "alchemy-gpio1", + .direction_input = gpio1_direction_input, + .direction_output = gpio1_direction_output, + .get = gpio1_get, + .set = gpio1_set, + .to_irq = gpio1_to_irq, + .base = ALCHEMY_GPIO1_BASE, + .ngpio = ALCHEMY_GPIO1_NUM, + }, +#if !defined(CONFIG_SOC_AU1000) + [1] = { + .label = "alchemy-gpio2", + .direction_input = gpio2_direction_input, + .direction_output = gpio2_direction_output, + .get = gpio2_get, + .set = gpio2_set, + .to_irq = gpio2_to_irq, + .base = ALCHEMY_GPIO2_BASE, + .ngpio = ALCHEMY_GPIO2_NUM, + }, +#endif +}; + +static int __init alchemy_gpio_init(void) +{ + gpiochip_add(&alchemy_gpio_chip[0]); +#if !defined(CONFIG_SOC_AU1000) + gpiochip_add(&alchemy_gpio_chip[1]); +#endif + + return 0; +} +arch_initcall(alchemy_gpio_init); diff --git a/arch/mips/alchemy/common/gpio.c b/arch/mips/alchemy/common/gpio.c deleted file mode 100644 index 91a9c44..0000000 --- a/arch/mips/alchemy/common/gpio.c +++ /dev/null @@ -1,201 +0,0 @@ -/* - * Copyright (C) 2007-2009, OpenWrt.org, Florian Fainelli - * Architecture specific GPIO support - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - * - * Notes : - * au1000 SoC have only one GPIO line : GPIO1 - * others have a second one : GPIO2 - */ - -#include -#include -#include -#include -#include - -#include -#include - -struct au1000_gpio_chip { - struct gpio_chip chip; - void __iomem *regbase; -}; - -#if !defined(CONFIG_SOC_AU1000) -static int au1000_gpio2_get(struct gpio_chip *chip, unsigned offset) -{ - u32 mask = 1 << offset; - struct au1000_gpio_chip *gpch; - - gpch = container_of(chip, struct au1000_gpio_chip, chip); - return readl(gpch->regbase + AU1000_GPIO2_ST) & mask; -} - -static void au1000_gpio2_set(struct gpio_chip *chip, - unsigned offset, int value) -{ - u32 mask = ((GPIO2_OUT_EN_MASK << offset) | (!!value << offset)); - struct au1000_gpio_chip *gpch; - unsigned long flags; - - gpch = container_of(chip, struct au1000_gpio_chip, chip); - - local_irq_save(flags); - writel(mask, gpch->regbase + AU1000_GPIO2_OUT); - local_irq_restore(flags); -} - -static int au1000_gpio2_direction_input(struct gpio_chip *chip, unsigned offset) -{ - u32 mask = 1 << offset; - u32 tmp; - struct au1000_gpio_chip *gpch; - unsigned long flags; - - gpch = container_of(chip, struct au1000_gpio_chip, chip); - - local_irq_save(flags); - tmp = readl(gpch->regbase + AU1000_GPIO2_DIR); - tmp &= ~mask; - writel(tmp, gpch->regbase + AU1000_GPIO2_DIR); - local_irq_restore(flags); - - return 0; -} - -static int au1000_gpio2_direction_output(struct gpio_chip *chip, - unsigned offset, int value) -{ - u32 mask = 1 << offset; - u32 out_mask = ((GPIO2_OUT_EN_MASK << offset) | (!!value << offset)); - u32 tmp; - struct au1000_gpio_chip *gpch; - unsigned long flags; - - gpch = container_of(chip, struct au1000_gpio_chip, chip); - - local_irq_save(flags); - tmp = readl(gpch->regbase + AU1000_GPIO2_DIR); - tmp |= mask; - writel(tmp, gpch->regbase + AU1000_GPIO2_DIR); - writel(out_mask, gpch->regbase + AU1000_GPIO2_OUT); - local_irq_restore(flags); - - return 0; -} -#endif /* !defined(CONFIG_SOC_AU1000) */ - -static int au1000_gpio1_get(struct gpio_chip *chip, unsigned offset) -{ - u32 mask = 1 << offset; - struct au1000_gpio_chip *gpch; - - gpch = container_of(chip, struct au1000_gpio_chip, chip); - return readl(gpch->regbase + AU1000_GPIO1_ST) & mask; -} - -static void au1000_gpio1_set(struct gpio_chip *chip, - unsigned offset, int value) -{ - u32 mask = 1 << offset; - u32 reg_offset; - struct au1000_gpio_chip *gpch; - unsigned long flags; - - gpch = container_of(chip, struct au1000_gpio_chip, chip); - - if (value) - reg_offset = AU1000_GPIO1_OUT; - else - reg_offset = AU1000_GPIO1_CLR; - - local_irq_save(flags); - writel(mask, gpch->regbase + reg_offset); - local_irq_restore(flags); -} - -static int au1000_gpio1_direction_input(struct gpio_chip *chip, unsigned offset) -{ - u32 mask = 1 << offset; - struct au1000_gpio_chip *gpch; - - gpch = container_of(chip, struct au1000_gpio_chip, chip); - writel(mask, gpch->regbase + AU1000_GPIO1_ST); - - return 0; -} - -static int au1000_gpio1_direction_output(struct gpio_chip *chip, - unsigned offset, int value) -{ - u32 mask = 1 << offset; - struct au1000_gpio_chip *gpch; - - gpch = container_of(chip, struct au1000_gpio_chip, chip); - - writel(mask, gpch->regbase + AU1000_GPIO1_TRI_OUT); - au1000_gpio1_set(chip, offset, value); - - return 0; -} - -struct au1000_gpio_chip au1000_gpio_chip[] = { - [0] = { - .regbase = (void __iomem *)SYS_BASE, - .chip = { - .label = "au1000-gpio1", - .direction_input = au1000_gpio1_direction_input, - .direction_output = au1000_gpio1_direction_output, - .get = au1000_gpio1_get, - .set = au1000_gpio1_set, - .base = 0, - .ngpio = 32, - }, - }, -#if !defined(CONFIG_SOC_AU1000) - [1] = { - .regbase = (void __iomem *)GPIO2_BASE, - .chip = { - .label = "au1000-gpio2", - .direction_input = au1000_gpio2_direction_input, - .direction_output = au1000_gpio2_direction_output, - .get = au1000_gpio2_get, - .set = au1000_gpio2_set, - .base = AU1XXX_GPIO_BASE, - .ngpio = 32, - }, - }, -#endif -}; - -static int __init au1000_gpio_init(void) -{ - gpiochip_add(&au1000_gpio_chip[0].chip); -#if !defined(CONFIG_SOC_AU1000) - gpiochip_add(&au1000_gpio_chip[1].chip); -#endif - - return 0; -} -arch_initcall(au1000_gpio_init); - diff --git a/arch/mips/include/asm/mach-au1x00/gpio-au1000.h b/arch/mips/include/asm/mach-au1x00/gpio-au1000.h new file mode 100644 index 0000000..127d4ed --- /dev/null +++ b/arch/mips/include/asm/mach-au1x00/gpio-au1000.h @@ -0,0 +1,604 @@ +/* + * GPIO functions for Au1000, Au1500, Au1100, Au1550, Au1200 + * + * Copyright (c) 2009 Manuel Lauss. + * + * Licensed under the terms outlined in the file COPYING. + */ + +#ifndef _ALCHEMY_GPIO_AU1000_H_ +#define _ALCHEMY_GPIO_AU1000_H_ + +#include + +/* The default GPIO numberspace as documented in the Alchemy manuals. + * GPIO0-31 from GPIO1 block, GPIO200-215 from GPIO2 block. + */ +#define ALCHEMY_GPIO1_BASE 0 +#define ALCHEMY_GPIO2_BASE 200 + +#define ALCHEMY_GPIO1_NUM 32 +#define ALCHEMY_GPIO2_NUM 16 +#define ALCHEMY_GPIO1_MAX (ALCHEMY_GPIO1_BASE + ALCHEMY_GPIO1_NUM - 1) +#define ALCHEMY_GPIO2_MAX (ALCHEMY_GPIO2_BASE + ALCHEMY_GPIO2_NUM - 1) + +#define MAKE_IRQ(intc, off) (AU1000_INTC##intc##_INT_BASE + (off)) + + +static inline int au1000_gpio1_to_irq(int gpio) +{ + return MAKE_IRQ(1, gpio - ALCHEMY_GPIO1_BASE); +} + +static inline int au1000_gpio2_to_irq(int gpio) +{ + return -ENXIO; +} + +#ifdef CONFIG_SOC_AU1000 +static inline int au1000_irq_to_gpio(int irq) +{ + if ((irq >= AU1000_GPIO_0) && (irq <= AU1000_GPIO_31)) + return ALCHEMY_GPIO1_BASE + (irq - AU1000_GPIO_0) + 0; + + return -ENXIO; +} +#endif + +static inline int au1500_gpio1_to_irq(int gpio) +{ + gpio -= ALCHEMY_GPIO1_BASE; + + switch (gpio) { + case 0 ... 15: + case 20: + case 23 ... 28: return MAKE_IRQ(1, gpio); + } + + return -ENXIO; +} + +static inline int au1500_gpio2_to_irq(int gpio) +{ + gpio -= ALCHEMY_GPIO2_BASE; + + switch (gpio) { + case 0 ... 3: return MAKE_IRQ(1, 16 + gpio - 0); + case 4 ... 5: return MAKE_IRQ(1, 21 + gpio - 4); + case 6 ... 7: return MAKE_IRQ(1, 29 + gpio - 6); + } + + return -ENXIO; +} + +#ifdef CONFIG_SOC_AU1500 +static inline int au1500_irq_to_gpio(int irq) +{ + switch (irq) { + case AU1000_GPIO_0 ... AU1000_GPIO_15: + case AU1500_GPIO_20: + case AU1500_GPIO_23 ... AU1500_GPIO_28: + return ALCHEMY_GPIO1_BASE + (irq - AU1000_GPIO_0) + 0; + case AU1500_GPIO_200 ... AU1500_GPIO_203: + return ALCHEMY_GPIO2_BASE + (irq - AU1500_GPIO_200) + 0; + case AU1500_GPIO_204 ... AU1500_GPIO_205: + return ALCHEMY_GPIO2_BASE + (irq - AU1500_GPIO_204) + 4; + case AU1500_GPIO_206 ... AU1500_GPIO_207: + return ALCHEMY_GPIO2_BASE + (irq - AU1500_GPIO_206) + 6; + case AU1500_GPIO_208_215: + return ALCHEMY_GPIO2_BASE + 8; + } + + return -ENXIO; +} +#endif + +static inline int au1100_gpio1_to_irq(int gpio) +{ + return MAKE_IRQ(1, gpio - ALCHEMY_GPIO1_BASE); +} + +static inline int au1100_gpio2_to_irq(int gpio) +{ + gpio -= ALCHEMY_GPIO2_BASE; + + if ((gpio >= 8) && (gpio <= 15)) + return MAKE_IRQ(0, 29); /* shared GPIO208_215 */ +} + +#ifdef CONFIG_SOC_AU1100 +static inline int au1100_irq_to_gpio(int irq) +{ + switch (irq) { + case AU1000_GPIO_0 ... AU1000_GPIO_31: + return ALCHEMY_GPIO1_BASE + (irq - AU1000_GPIO_0) + 0; + case AU1100_GPIO_208_215: + return ALCHEMY_GPIO2_BASE + 8; + } + + return -ENXIO; +} +#endif + +static inline int au1550_gpio1_to_irq(int gpio) +{ + gpio -= ALCHEMY_GPIO1_BASE; + + switch (gpio) { + case 0 ... 15: + case 20 ... 28: return MAKE_IRQ(1, gpio); + case 16 ... 17: return MAKE_IRQ(1, 18 + gpio - 16); + } + + return -ENXIO; +} + +static inline int au1550_gpio2_to_irq(int gpio) +{ + gpio -= ALCHEMY_GPIO2_BASE; + + switch (gpio) { + case 0: return MAKE_IRQ(1, 16); + case 1 ... 5: return MAKE_IRQ(1, 17); /* shared GPIO201_205 */ + case 6 ... 7: return MAKE_IRQ(1, 29 + gpio - 6); + case 8 ... 15: return MAKE_IRQ(1, 31); /* shared GPIO208_215 */ + } + + return -ENXIO; +} + +#ifdef CONFIG_SOC_AU1550 +static inline int au1550_irq_to_gpio(int irq) +{ + switch (irq) { + case AU1000_GPIO_0 ... AU1000_GPIO_15: + return ALCHEMY_GPIO1_BASE + (irq - AU1000_GPIO_0) + 0; + case AU1550_GPIO_200: + case AU1500_GPIO_201_205: + return ALCHEMY_GPIO2_BASE + (irq - AU1550_GPIO_200) + 0; + case AU1500_GPIO_16 ... AU1500_GPIO_28: + return ALCHEMY_GPIO1_BASE + (irq - AU1500_GPIO_16) + 16; + case AU1500_GPIO_206 ... AU1500_GPIO_208_218: + return ALCHEMY_GPIO2_BASE + (irq - AU1500_GPIO_206) + 6; + } + + return -ENXIO; +} +#endif + +static inline int au1200_gpio1_to_irq(int gpio) +{ + return MAKE_IRQ(1, gpio - ALCHEMY_GPIO1_BASE); +} + +static inline int au1200_gpio2_to_irq(int gpio) +{ + gpio -= ALCHEMY_GPIO2_BASE; + + switch (gpio) { + case 0 ... 2: return MAKE_IRQ(0, 5 + gpio - 0); + case 3: return MAKE_IRQ(0, 22); + case 4 ... 7: return MAKE_IRQ(0, 24 + gpio - 4); + case 8 ... 15: return MAKE_IRQ(0, 28); /* shared GPIO208_215 */ + } + + return -ENXIO; +} + +#ifdef CONFIG_SOC_AU1200 +static inline int au1200_irq_to_gpio(int irq) +{ + switch (irq) { + case AU1000_GPIO_0 ... AU1000_GPIO_31: + return ALCHEMY_GPIO1_BASE + (irq - AU1000_GPIO_0) + 0; + case AU1200_GPIO_200 ... AU1200_GPIO_202: + return ALCHEMY_GPIO2_BASE + (irq - AU1200_GPIO_200) + 0; + case AU1200_GPIO_203: + return ALCHEMY_GPIO2_BASE + 3; + case AU1200_GPIO_204 ... AU1200_GPIO_208_215: + return ALCHEMY_GPIO2_BASE + (irq - AU1200_GPIO_204) + 4; + } + + return -ENXIO; +} +#endif + +/* + * GPIO1 block macros for common linux gpio functions. + */ +static inline void alchemy_gpio1_set_value(int gpio, int v) +{ + unsigned long mask = 1 << (gpio - ALCHEMY_GPIO1_BASE); + unsigned long r = v ? SYS_OUTPUTSET : SYS_OUTPUTCLR; + au_writel(mask, r); + au_sync(); +} + +static inline int alchemy_gpio1_get_value(int gpio) +{ + unsigned long mask = 1 << (gpio - ALCHEMY_GPIO1_BASE); + return au_readl(SYS_PINSTATERD) & mask; +} + +static inline int alchemy_gpio1_direction_input(int gpio) +{ + unsigned long mask = 1 << (gpio - ALCHEMY_GPIO1_BASE); + au_writel(mask, SYS_TRIOUTCLR); + au_sync(); + return 0; +} + +static inline int alchemy_gpio1_direction_output(int gpio, int v) +{ + /* hardware switches to "output" mode when one of the two + * "set_value" registers is accessed. + */ + alchemy_gpio1_set_value(gpio, v); + return 0; +} + +static inline int alchemy_gpio1_is_valid(int gpio) +{ + return ((gpio >= ALCHEMY_GPIO1_BASE) && (gpio <= ALCHEMY_GPIO1_MAX)); +} + +static inline int alchemy_gpio1_to_irq(int gpio) +{ +#if defined(CONFIG_SOC_AU1000) + return au1000_gpio1_to_irq(gpio); +#elif defined(CONFIG_SOC_AU1100) + return au1100_gpio1_to_irq(gpio); +#elif defined(CONFIG_SOC_AU1500) + return au1500_gpio1_to_irq(gpio); +#elif defined(CONFIG_SOC_AU1550) + return au1550_gpio1_to_irq(gpio); +#elif defined(CONFIG_SOC_AU1200) + return au1200_gpio1_to_irq(gpio); +#else + return -ENXIO; +#endif +} + +/* + * GPIO2 block macros for common linux GPIO functions. The 'gpio' + * parameter must be in range of ALCHEMY_GPIO2_BASE..ALCHEMY_GPIO2_MAX. + */ +static inline void __alchemy_gpio2_mod_dir(int gpio, int to_out) +{ + unsigned long mask = 1 << (gpio - ALCHEMY_GPIO2_BASE); + unsigned long d = au_readl(GPIO2_DIR); + if (to_out) + d |= mask; + else + d &= ~mask; + au_writel(d, GPIO2_DIR); + au_sync(); +} + +static inline void alchemy_gpio2_set_value(int gpio, int v) +{ + unsigned long mask; + mask = ((v) ? 0x00010001 : 0x00010000) << (gpio - ALCHEMY_GPIO2_BASE); + au_writel(mask, GPIO2_OUTPUT); + au_sync(); +} + +static inline int alchemy_gpio2_get_value(int gpio) +{ + return au_readl(GPIO2_PINSTATE) & (1 << (gpio - ALCHEMY_GPIO2_BASE)); +} + +static inline int alchemy_gpio2_direction_input(int gpio) +{ + unsigned long flags; + local_irq_save(flags); + __alchemy_gpio2_mod_dir(gpio, 0); + local_irq_restore(flags); + return 0; +} + +static inline int alchemy_gpio2_direction_output(int gpio, int v) +{ + unsigned long flags; + alchemy_gpio2_set_value(gpio, v); + local_irq_save(flags); + __alchemy_gpio2_mod_dir(gpio, 1); + local_irq_restore(flags); + return 0; +} + +static inline int alchemy_gpio2_is_valid(int gpio) +{ + return ((gpio >= ALCHEMY_GPIO2_BASE) && (gpio <= ALCHEMY_GPIO2_MAX)); +} + +static inline int alchemy_gpio2_to_irq(int gpio) +{ +#if defined(CONFIG_SOC_AU1000) + return au1000_gpio2_to_irq(gpio); +#elif defined(CONFIG_SOC_AU1100) + return au1100_gpio2_to_irq(gpio); +#elif defined(CONFIG_SOC_AU1500) + return au1500_gpio2_to_irq(gpio); +#elif defined(CONFIG_SOC_AU1550) + return au1550_gpio2_to_irq(gpio); +#elif defined(CONFIG_SOC_AU1200) + return au1200_gpio2_to_irq(gpio); +#else + return -ENXIO; +#endif +} + +/**********************************************************************/ + +/* On Au1000, Au1500 and Au1100 GPIOs won't work as inputs before + * SYS_PININPUTEN is written to at least once. On Au1550/Au1200 this + * register enables use of GPIOs as wake source. + */ +static inline void alchemy_gpio1_input_enable(void) +{ + au_writel(0, SYS_PININPUTEN); /* the write op is key */ + au_sync(); +} + +/* GPIO2 shared interrupts and control */ + +static inline void __alchemy_gpio2_mod_int(int gpio2, int en) +{ + unsigned long r = au_readl(GPIO2_INTENABLE); + if (en) + r |= 1 << gpio2; + else + r &= ~(1 << gpio2); + au_writel(r, GPIO2_INTENABLE); + au_sync(); +} + +/** + * alchemy_gpio2_enable_int - Enable a GPIO2 pins' shared irq contribution. + * @gpio2: The GPIO2 pin to activate (200...215). + * + * GPIO208-215 have one shared interrupt line to the INTC. They are + * and'ed with a per-pin enable bit and finally or'ed together to form + * a single irq request (useful for active-high sources). + * With this function, a pins' individual contribution to the int request + * can be enabled. As with all other GPIO-based interrupts, the INTC + * must be programmed to accept the GPIO208_215 interrupt as well. + * + * NOTE: Calling this macro is only necessary for GPIO208-215; all other + * GPIO2-based interrupts have their own request to the INTC. Please + * consult your Alchemy databook for more information! + * + * NOTE: On the Au1550, GPIOs 201-205 also have a shared interrupt request + * line to the INTC, GPIO201_205. This function can be used for those + * as well. + * + * NOTE: 'gpio2' parameter must be in range of the GPIO2 numberspace + * (200-215 by default). No sanity checks are made, + */ +static inline void alchemy_gpio2_enable_int(int gpio2) +{ + unsigned long flags; + + gpio2 -= ALCHEMY_GPIO2_BASE; + +#if defined(CONFIG_SOC_AU1100) || defined(CONFIG_SOC_AU1500) + /* Au1100/Au1500 have GPIO208-215 enable bits at 0..7 */ + gpio2 -= 8; +#endif + local_irq_save(flags); + __alchemy_gpio2_mod_int(gpio2, 1); + local_irq_restore(flags); +} + +/** + * alchemy_gpio2_disable_int - Disable a GPIO2 pins' shared irq contribution. + * @gpio2: The GPIO2 pin to activate (200...215). + * + * see function alchemy_gpio2_enable_int() for more information. + */ +static inline void alchemy_gpio2_disable_int(int gpio2) +{ + unsigned long flags; + + gpio2 -= ALCHEMY_GPIO2_BASE; + +#if defined(CONFIG_SOC_AU1100) || defined(CONFIG_SOC_AU1500) + /* Au1100/Au1500 have GPIO208-215 enable bits at 0..7 */ + gpio2 -= 8; +#endif + local_irq_save(flags); + __alchemy_gpio2_mod_int(gpio2, 0); + local_irq_restore(flags); +} + +/** + * alchemy_gpio2_enable - Activate GPIO2 block. + * + * The GPIO2 block must be enabled excplicitly to work. On systems + * where this isn't done by the bootloader, this macro can be used. + */ +static inline void alchemy_gpio2_enable(void) +{ + au_writel(3, GPIO2_ENABLE); /* reset, clock enabled */ + au_sync(); + au_writel(1, GPIO2_ENABLE); /* clock enabled */ + au_sync(); +} + +/** + * alchemy_gpio2_disable - disable GPIO2 block. + * + * Disable and put GPIO2 block in low-power mode. + */ +static inline void alchemy_gpio2_disable(void) +{ + au_writel(2, GPIO2_ENABLE); /* reset, clock disabled */ + au_sync(); +} + +/**********************************************************************/ + +/* wrappers for on-chip gpios; can be used before gpio chips have been + * registered with gpiolib. + */ +static inline int alchemy_gpio_direction_input(int gpio) +{ + return (gpio >= ALCHEMY_GPIO2_BASE) ? + alchemy_gpio2_direction_input(gpio) : + alchemy_gpio1_direction_input(gpio); +} + +static inline int alchemy_gpio_direction_output(int gpio, int v) +{ + return (gpio >= ALCHEMY_GPIO2_BASE) ? + alchemy_gpio2_direction_output(gpio, v) : + alchemy_gpio1_direction_output(gpio, v); +} + +static inline int alchemy_gpio_get_value(int gpio) +{ + return (gpio >= ALCHEMY_GPIO2_BASE) ? + alchemy_gpio2_get_value(gpio) : + alchemy_gpio1_get_value(gpio); +} + +static inline void alchemy_gpio_set_value(int gpio, int v) +{ + if (gpio >= ALCHEMY_GPIO2_BASE) + alchemy_gpio2_set_value(gpio, v); + else + alchemy_gpio1_set_value(gpio, v); +} + +static inline int alchemy_gpio_is_valid(int gpio) +{ + return (gpio >= ALCHEMY_GPIO2_BASE) ? + alchemy_gpio2_is_valid(gpio) : + alchemy_gpio1_is_valid(gpio); +} + +static inline int alchemy_gpio_cansleep(int gpio) +{ + return 0; /* Alchemy never gets tired */ +} + +static inline int alchemy_gpio_to_irq(int gpio) +{ + return (gpio >= ALCHEMY_GPIO2_BASE) ? + alchemy_gpio2_to_irq(gpio) : + alchemy_gpio1_to_irq(gpio); +} + +static inline int alchemy_irq_to_gpio(int irq) +{ +#if defined(CONFIG_SOC_AU1000) + return au1000_irq_to_gpio(irq); +#elif defined(CONFIG_SOC_AU1100) + return au1100_irq_to_gpio(irq); +#elif defined(CONFIG_SOC_AU1500) + return au1500_irq_to_gpio(irq); +#elif defined(CONFIG_SOC_AU1550) + return au1550_irq_to_gpio(irq); +#elif defined(CONFIG_SOC_AU1200) + return au1200_irq_to_gpio(irq); +#else + return -ENXIO; +#endif +} + +/**********************************************************************/ + +/* Linux gpio framework integration. + * + * 4 use cases of Au1000-Au1200 GPIOS: + *(1) GPIOLIB=y, ALCHEMY_GPIO_INDIRECT=y: + * Board must register gpiochips. + *(2) GPIOLIB=y, ALCHEMY_GPIO_INDIRECT=n: + * 2 (1 for Au1000) gpio_chips are registered. + * + *(3) GPIOLIB=n, ALCHEMY_GPIO_INDIRECT=y: + * the boards' gpio.h must provide the linux gpio wrapper functions, + * + *(4) GPIOLIB=n, ALCHEMY_GPIO_INDIRECT=n: + * inlinable gpio functions are provided which enable access to the + * Au1000 gpios only by using the numbers straight out of the data- + * sheets. + + * Cases 1 and 3 are intended for boards which want to provide their own + * GPIO namespace and -operations (i.e. for example you have 8 GPIOs + * which are in part provided by spare Au1000 GPIO pins and in part by + * an external FPGA but you still want them to be accssible in linux + * as gpio0-7. The board can of course use the alchemy_gpioX_* functions + * as required). + */ + +#ifndef CONFIG_GPIOLIB + + +#ifndef CONFIG_ALCHEMY_GPIO_INDIRECT /* case (4) */ + +static inline int gpio_direction_input(int gpio) +{ + return alchemy_gpio_direction_input(gpio); +} + +static inline int gpio_direction_output(int gpio, int v) +{ + return alchemy_gpio_direction_output(gpio, v); +} + +static inline int gpio_get_value(int gpio) +{ + return alchemy_gpio_get_value(gpio); +} + +static inline void gpio_set_value(int gpio, int v) +{ + alchemy_gpio_set_value(gpio, v); +} + +static inline int gpio_is_valid(int gpio) +{ + return alchemy_gpio_is_valid(gpio); +} + +static inline int gpio_cansleep(int gpio) +{ + return alchemy_gpio_cansleep(gpio); +} + +static inline int gpio_to_irq(int gpio) +{ + return alchemy_gpio_to_irq(gpio); +} + +static inline int irq_to_gpio(int irq) +{ + return alchemy_irq_to_gpio(irq); +} + +#endif /* !CONFIG_ALCHEMY_GPIO_INDIRECT */ + + +#else /* CONFIG GPIOLIB */ + + + /* using gpiolib to provide up to 2 gpio_chips for on-chip gpios */ +#ifndef CONFIG_ALCHEMY_GPIO_INDIRECT /* case (2) */ + +/* get everything through gpiolib */ +#define gpio_to_irq __gpio_to_irq +#define gpio_get_value __gpio_get_value +#define gpio_set_value __gpio_set_value +#define gpio_cansleep __gpio_cansleep +#define irq_to_gpio alchemy_irq_to_gpio + +#include + +#endif /* !CONFIG_ALCHEMY_GPIO_INDIRECT */ + + +#endif /* !CONFIG_GPIOLIB */ + +#endif /* _ALCHEMY_GPIO_AU1000_H_ */ diff --git a/arch/mips/include/asm/mach-au1x00/gpio.h b/arch/mips/include/asm/mach-au1x00/gpio.h index 34d9b72..f9b7d41 100644 --- a/arch/mips/include/asm/mach-au1x00/gpio.h +++ b/arch/mips/include/asm/mach-au1x00/gpio.h @@ -1,33 +1,10 @@ -#ifndef _AU1XXX_GPIO_H_ -#define _AU1XXX_GPIO_H_ +#ifndef _ALCHEMY_GPIO_H_ +#define _ALCHEMY_GPIO_H_ -#include +#if defined(CONFIG_ALCHEMY_GPIO_AU1000) -#define AU1XXX_GPIO_BASE 200 +#include -/* GPIO bank 1 offsets */ -#define AU1000_GPIO1_TRI_OUT 0x0100 -#define AU1000_GPIO1_OUT 0x0108 -#define AU1000_GPIO1_ST 0x0110 -#define AU1000_GPIO1_CLR 0x010C +#endif -/* GPIO bank 2 offsets */ -#define AU1000_GPIO2_DIR 0x00 -#define AU1000_GPIO2_RSVD 0x04 -#define AU1000_GPIO2_OUT 0x08 -#define AU1000_GPIO2_ST 0x0C -#define AU1000_GPIO2_INT 0x10 -#define AU1000_GPIO2_EN 0x14 - -#define GPIO2_OUT_EN_MASK 0x00010000 - -#define gpio_to_irq(gpio) NULL - -#define gpio_get_value __gpio_get_value -#define gpio_set_value __gpio_set_value - -#define gpio_cansleep __gpio_cansleep - -#include - -#endif /* _AU1XXX_GPIO_H_ */ +#endif /* _ALCHEMY_GPIO_H_ */ -- 1.6.3.1 From manuel.lauss@googlemail.com Wed Jun 3 17:20:24 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 03 Jun 2009 17:20:31 +0100 (WEST) Received: from mail-fx0-f223.google.com ([209.85.220.223]:35959 "EHLO mail-fx0-f223.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20022343AbZFCQS1 (ORCPT ); Wed, 3 Jun 2009 17:18:27 +0100 Received: by fxm23 with SMTP id 23so114418fxm.0 for ; Wed, 03 Jun 2009 09:18:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer:in-reply-to:references; bh=GMbZlBqYnsxeIszQj9UKwbkVVg8r3DbgUHb0Zdh3VEo=; b=VoXBaMf8gm4HY2U+c+vjzEP++BPHCPlCzH8w+IJxAC+TLKKI5/vMk30jCy2qT8GiNs Ag0v3T7EREFYauzTnoSyrH5MCtXe/83Pxu6Tl16+0CRS0kTxpea8mjJt2NMqfuicssjQ CoOUpyBodADmDm2LaRel85EoInkD90e/P9e+o= DomainKey-Signature: a=rsa-sha1; c=nofws; d=googlemail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; b=Wd+4FfKXaJEH76Aai8ynmTNJQDi53hOozkdNvuWazRAq7GLvbck6bFmdB2ONeTnzCl iCqrM0ACR9iqH+CnfafHcKGjulBU+VEz5IE3OiFAm+a/05+dYi0DO/YBdLS+lL4eM9Or DsS2vIlxVkmSb8uFWr8kqUVHDZNTfU9FOTeCQ= Received: by 10.103.246.1 with SMTP id y1mr733856mur.72.1244045901965; Wed, 03 Jun 2009 09:18:21 -0700 (PDT) Received: from localhost.localdomain (p5496DB58.dip.t-dialin.net [84.150.219.88]) by mx.google.com with ESMTPS id u26sm37723mug.22.2009.06.03.09.18.20 (version=TLSv1/SSLv3 cipher=RC4-MD5); Wed, 03 Jun 2009 09:18:21 -0700 (PDT) From: Manuel Lauss To: Linux-MIPS , Ralf Baechle Cc: Manuel Lauss Subject: [PATCH 4/5] Alchemy: xxs1500: use linux gpio api. Date: Wed, 3 Jun 2009 18:18:07 +0200 Message-Id: <1244045888-16259-5-git-send-email-manuel.lauss@gmail.com> X-Mailer: git-send-email 1.6.3.1 In-Reply-To: <1244045888-16259-4-git-send-email-manuel.lauss@gmail.com> References: <1244045888-16259-1-git-send-email-manuel.lauss@gmail.com> <1244045888-16259-2-git-send-email-manuel.lauss@gmail.com> <1244045888-16259-3-git-send-email-manuel.lauss@gmail.com> <1244045888-16259-4-git-send-email-manuel.lauss@gmail.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23226 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips Replace a few GPIO register accesses in the board init code with calls to the gpio api. Signed-off-by: Manuel Lauss --- arch/mips/alchemy/xxs1500/board_setup.c | 21 ++++++++++++--------- 1 files changed, 12 insertions(+), 9 deletions(-) diff --git a/arch/mips/alchemy/xxs1500/board_setup.c b/arch/mips/alchemy/xxs1500/board_setup.c index a2634fa..4de2d48 100644 --- a/arch/mips/alchemy/xxs1500/board_setup.c +++ b/arch/mips/alchemy/xxs1500/board_setup.c @@ -23,6 +23,7 @@ * 675 Mass Ave, Cambridge, MA 02139, USA. */ +#include #include #include @@ -50,6 +51,9 @@ void __init board_setup(void) } #endif + alchemy_gpio1_input_enable(); + alchemy_gpio2_enable(); + /* Set multiple use pins (UART3/GPIO) to UART (it's used as UART too) */ pin_func = au_readl(SYS_PINFUNC) & ~SYS_PF_UR3; pin_func |= SYS_PF_UR3; @@ -65,20 +69,19 @@ void __init board_setup(void) au_writel(0x01, UART3_ADDR + UART_MCR); /* UART_MCR_DTR is 0x01??? */ #ifdef CONFIG_PCMCIA_XXS1500 - /* Setup PCMCIA signals */ - au_writel(0, SYS_PININPUTEN); - /* GPIO 0, 1, and 4 are inputs */ - au_writel(1 | (1 << 1) | (1 << 4), SYS_TRIOUTCLR); + alchemy_gpio_direction_input(0); + alchemy_gpio_direction_input(1); + alchemy_gpio_direction_input(4); - /* Enable GPIO2 if not already enabled */ - au_writel(1, GPIO2_ENABLE); /* GPIO2 208/9/10/11 are inputs */ - au_writel((1 << 8) | (1 << 9) | (1 << 10) | (1 << 11), GPIO2_DIR); + alchemy_gpio_direction_input(208); + alchemy_gpio_direction_input(209); + alchemy_gpio_direction_input(210); + alchemy_gpio_direction_input(211); /* Turn off power */ - au_writel((au_readl(GPIO2_PINSTATE) & ~(1 << 14)) | (1 << 30), - GPIO2_OUTPUT); + alchemy_gpio_direction_output(214, 0); #endif #ifdef CONFIG_PCI -- 1.6.3.1 From manuel.lauss@googlemail.com Wed Jun 3 18:03:02 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 03 Jun 2009 18:03:10 +0100 (WEST) Received: from mail-bw0-f225.google.com ([209.85.218.225]:65035 "EHLO mail-bw0-f225.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20022326AbZFCRDC (ORCPT ); Wed, 3 Jun 2009 18:03:02 +0100 Received: by bwz25 with SMTP id 25so145388bwz.0 for ; Wed, 03 Jun 2009 10:02:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer; bh=6rNNWFTMwMnQmeItQ5MsgWw8f62GThNccNmZKFwilag=; b=QsF60/xZNv3KTnTx/Ms4CChZAlSyd6xPtgKNJl30YQzvE8Nqa4vuL34Yp8FVkLYpYQ hUyShyNbmfPRhubcB4EA7bhAQOFgtpzBUwNn4pO36LJId04wFV6QRQLaTMu9rzbTZI1y F3/ekody7j0xpnYQZHLitrOZriQlGl1Up6PKI= DomainKey-Signature: a=rsa-sha1; c=nofws; d=googlemail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer; b=FFhOMsQsqymTcJ6GPJtUxX4Zo5EnYduJCY5V7MXf1MT3yek21RFWmRHB+IoZyF13+q c84LX6PaIwgf3lUPKMOhIGvIkolDYrGx4WL9rzmfA+dQNY3ySoZk6/6VH4lf82f7BX1O 7TlP+pj+NXS5U4DyFGt9sRdVNi57hoOVdYKYI= Received: by 10.204.53.143 with SMTP id m15mr1057883bkg.119.1244048576697; Wed, 03 Jun 2009 10:02:56 -0700 (PDT) Received: from localhost.localdomain (p5496DB58.dip.t-dialin.net [84.150.219.88]) by mx.google.com with ESMTPS id 18sm2452543fks.10.2009.06.03.10.02.54 (version=TLSv1/SSLv3 cipher=RC4-MD5); Wed, 03 Jun 2009 10:02:56 -0700 (PDT) From: Manuel Lauss To: Linux-MIPS , Ralf Baechle Cc: Manuel Lauss Subject: [PATCH 0/5] Alchemy: core and platform updates Date: Wed, 3 Jun 2009 19:02:43 +0200 Message-Id: <1244048568-18006-1-git-send-email-manuel.lauss@gmail.com> X-Mailer: git-send-email 1.6.3.1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23227 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips Minor updates to the Alchemy core code to get rid of a hack in the irq dispatcher and the global variable "allow_au1k_wait". The bulk of this series is in patches #3 to #5, which introduce new DB1200 platform code, a new PCMCIA socket driver for almost all Alchemy demoboards and finally the elimination of the alchemy-flash MTD map driver in favor of physmap_flash platform devices. As always, run-tested on the DB1200 only. Manuel Lauss (5): Alchemy: prioritize timer and usb irqs Alchemy: get rid of allow_au1k_wait Alchemy: extended DB1200 board support. Alchemy: new PCMCIA socket driver for devboards. Alchemy: convert to physmap flash arch/mips/alchemy/common/irq.c | 275 ++-- arch/mips/alchemy/common/platform.c | 6 - arch/mips/alchemy/common/reset.c | 3 - arch/mips/alchemy/common/setup.c | 3 +- arch/mips/alchemy/common/time.c | 14 +- arch/mips/alchemy/devboards/Makefile | 2 +- arch/mips/alchemy/devboards/db1200/Makefile | 1 + arch/mips/alchemy/devboards/db1200/platform.c | 667 +++++++++ arch/mips/alchemy/devboards/db1200/setup.c | 181 +++ arch/mips/alchemy/devboards/db1x00/Makefile | 3 +- arch/mips/alchemy/devboards/db1x00/platform.c | 243 ++++ arch/mips/alchemy/devboards/pb1000/Makefile | 3 +- arch/mips/alchemy/devboards/pb1000/platform.c | 84 ++ arch/mips/alchemy/devboards/pb1100/Makefile | 3 +- arch/mips/alchemy/devboards/pb1100/platform.c | 134 ++ arch/mips/alchemy/devboards/pb1200/board_setup.c | 5 - arch/mips/alchemy/devboards/pb1200/irqmap.c | 19 +- arch/mips/alchemy/devboards/pb1200/platform.c | 167 +++- arch/mips/alchemy/devboards/pb1500/Makefile | 3 +- arch/mips/alchemy/devboards/pb1500/platform.c | 134 ++ arch/mips/alchemy/devboards/pb1550/Makefile | 3 +- arch/mips/alchemy/devboards/pb1550/board_setup.c | 3 + arch/mips/alchemy/devboards/pb1550/platform.c | 181 +++ arch/mips/configs/db1200_defconfig | 1629 +++++++++++++--------- arch/mips/include/asm/mach-au1x00/au1000.h | 14 + arch/mips/include/asm/mach-db1x00/db1200.h | 38 +- arch/mips/include/asm/mach-db1x00/db1x00.h | 8 - arch/mips/include/asm/mach-pb1x00/pb1100.h | 7 - arch/mips/include/asm/mach-pb1x00/pb1200.h | 14 - arch/mips/include/asm/mach-pb1x00/pb1500.h | 7 - arch/mips/include/asm/mach-pb1x00/pb1550.h | 7 - arch/mips/kernel/cpu-probe.c | 10 +- drivers/mtd/maps/Kconfig | 6 - drivers/mtd/maps/Makefile | 1 - drivers/mtd/maps/alchemy-flash.c | 166 --- drivers/pcmcia/Kconfig | 17 +- drivers/pcmcia/Makefile | 9 +- drivers/pcmcia/au1000_db1x00.c | 305 ---- drivers/pcmcia/db1xxx_ss.c | 700 ++++++++++ sound/soc/au1x/Kconfig | 10 +- sound/soc/au1x/Makefile | 4 +- sound/soc/au1x/db1200.c | 189 +++ sound/soc/au1x/sample-ac97.c | 144 -- 43 files changed, 3875 insertions(+), 1547 deletions(-) create mode 100644 arch/mips/alchemy/devboards/db1200/Makefile create mode 100644 arch/mips/alchemy/devboards/db1200/platform.c create mode 100644 arch/mips/alchemy/devboards/db1200/setup.c create mode 100644 arch/mips/alchemy/devboards/db1x00/platform.c create mode 100644 arch/mips/alchemy/devboards/pb1000/platform.c create mode 100644 arch/mips/alchemy/devboards/pb1100/platform.c create mode 100644 arch/mips/alchemy/devboards/pb1500/platform.c create mode 100644 arch/mips/alchemy/devboards/pb1550/platform.c delete mode 100644 drivers/mtd/maps/alchemy-flash.c delete mode 100644 drivers/pcmcia/au1000_db1x00.c create mode 100644 drivers/pcmcia/db1xxx_ss.c create mode 100644 sound/soc/au1x/db1200.c delete mode 100644 sound/soc/au1x/sample-ac97.c From manuel.lauss@googlemail.com Wed Jun 3 18:03:27 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 03 Jun 2009 18:03:35 +0100 (WEST) Received: from mail-fx0-f223.google.com ([209.85.220.223]:47045 "EHLO mail-fx0-f223.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20022344AbZFCRDE (ORCPT ); Wed, 3 Jun 2009 18:03:04 +0100 Received: by fxm23 with SMTP id 23so146835fxm.0 for ; Wed, 03 Jun 2009 10:02:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer:in-reply-to:references; bh=CkILRoHYcmfxcGfKc17FtDZ8TttG9Mvlh0STjurRUdI=; b=Ux5stKRlTmXCnhtXlDolAmlZgsosV4Mlq6KXPu9KI5DxXNXWEAEU+OSsuEVtmT4Z7P 0gxFDqrjTsNQ0hJEPpFjMRvL4O+oShJcnGAB5so6bhQFLlynvPGSUD9cy5W3Gz1dp9Il i4SO18RCS/1Q3YLzfVOvY2vG91X7CsPUwfbB0= DomainKey-Signature: a=rsa-sha1; c=nofws; d=googlemail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; b=jByAPM9ixqmQrZHQfzVRJ48kQdBF00vcbfX/cYwv+iweoquTqIPCQV+zafKWzUgRO0 /zjjndcQ7ceJ/mpYnA4Tj4KPx8SqpOX6J/6J+vmOsX4PIvwqVoCbvVJV7XzOlqALuki4 HtFTHlML84GLps7/tQFaxxbkKCBvaboZHpKuA= Received: by 10.204.100.71 with SMTP id x7mr1059531bkn.130.1244048577896; Wed, 03 Jun 2009 10:02:57 -0700 (PDT) Received: from localhost.localdomain (p5496DB58.dip.t-dialin.net [84.150.219.88]) by mx.google.com with ESMTPS id 18sm2452543fks.10.2009.06.03.10.02.56 (version=TLSv1/SSLv3 cipher=RC4-MD5); Wed, 03 Jun 2009 10:02:57 -0700 (PDT) From: Manuel Lauss To: Linux-MIPS , Ralf Baechle Cc: Manuel Lauss Subject: [PATCH 1/5] Alchemy: prioritize timer and usb irqs Date: Wed, 3 Jun 2009 19:02:44 +0200 Message-Id: <1244048568-18006-2-git-send-email-manuel.lauss@gmail.com> X-Mailer: git-send-email 1.6.3.1 In-Reply-To: <1244048568-18006-1-git-send-email-manuel.lauss@gmail.com> References: <1244048568-18006-1-git-send-email-manuel.lauss@gmail.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23228 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips MIPS IRQ0-3 are already processed in order; to assure that the system timer and usb-device (if it exists) irqs are processed with highest priority, assign the RTCMATCH2 and USB device irq to request0 of IC0 (=IRQ0) and all other IC0 sources to request1 (=IRQ1). This makes the USB-device priority hack unnecessary (in theory at least, I have no hardware to actually test this on). Signed-off-by: Manuel Lauss --- arch/mips/alchemy/common/irq.c | 275 +++++++++++++++++++--------------------- 1 files changed, 133 insertions(+), 142 deletions(-) diff --git a/arch/mips/alchemy/common/irq.c b/arch/mips/alchemy/common/irq.c index c88c821..6882de3 100644 --- a/arch/mips/alchemy/common/irq.c +++ b/arch/mips/alchemy/common/irq.c @@ -39,164 +39,168 @@ static int au1x_ic_settype(unsigned int irq, unsigned int flow_type); -/* per-processor fixed function irqs */ +/* per-processor fixed function irqs. + * Note on request assignments: to ensure timer (rtcmatch2) and usb + * device interrupts are processed with highest priority, they are + * exclusively assigned to request 0 and all others to request 1. + */ struct au1xxx_irqmap au1xxx_ic0_map[] __initdata = { #if defined(CONFIG_SOC_AU1000) - { AU1000_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1000_UART1_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1000_UART2_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1000_UART3_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1000_SSI0_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1000_SSI1_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1000_DMA_INT_BASE, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1000_DMA_INT_BASE+1, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1000_DMA_INT_BASE+2, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1000_DMA_INT_BASE+3, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1000_DMA_INT_BASE+4, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1000_DMA_INT_BASE+5, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1000_DMA_INT_BASE+6, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1000_DMA_INT_BASE+7, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1000_TOY_INT, IRQ_TYPE_EDGE_RISING, 0 }, - { AU1000_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 }, - { AU1000_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 }, + { AU1000_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 1 }, + { AU1000_UART1_INT, IRQ_TYPE_LEVEL_HIGH, 1 }, + { AU1000_UART2_INT, IRQ_TYPE_LEVEL_HIGH, 1 }, + { AU1000_UART3_INT, IRQ_TYPE_LEVEL_HIGH, 1 }, + { AU1000_SSI0_INT, IRQ_TYPE_LEVEL_HIGH, 1 }, + { AU1000_SSI1_INT, IRQ_TYPE_LEVEL_HIGH, 1 }, + { AU1000_DMA_INT_BASE, IRQ_TYPE_LEVEL_HIGH, 1 }, + { AU1000_DMA_INT_BASE+1, IRQ_TYPE_LEVEL_HIGH, 1 }, + { AU1000_DMA_INT_BASE+2, IRQ_TYPE_LEVEL_HIGH, 1 }, + { AU1000_DMA_INT_BASE+3, IRQ_TYPE_LEVEL_HIGH, 1 }, + { AU1000_DMA_INT_BASE+4, IRQ_TYPE_LEVEL_HIGH, 1 }, + { AU1000_DMA_INT_BASE+5, IRQ_TYPE_LEVEL_HIGH, 1 }, + { AU1000_DMA_INT_BASE+6, IRQ_TYPE_LEVEL_HIGH, 1 }, + { AU1000_DMA_INT_BASE+7, IRQ_TYPE_LEVEL_HIGH, 1 }, + { AU1000_TOY_INT, IRQ_TYPE_EDGE_RISING, 1 }, + { AU1000_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 1 }, + { AU1000_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 1 }, { AU1000_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1 }, - { AU1000_RTC_INT, IRQ_TYPE_EDGE_RISING, 0 }, - { AU1000_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 }, - { AU1000_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 }, + { AU1000_RTC_INT, IRQ_TYPE_EDGE_RISING, 1 }, + { AU1000_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 1 }, + { AU1000_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 1 }, { AU1000_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0 }, - { AU1000_IRDA_TX_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1000_IRDA_RX_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, + { AU1000_IRDA_TX_INT, IRQ_TYPE_LEVEL_HIGH, 1 }, + { AU1000_IRDA_RX_INT, IRQ_TYPE_LEVEL_HIGH, 1 }, { AU1000_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1000_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 0 }, - { AU1000_USB_HOST_INT, IRQ_TYPE_LEVEL_LOW, 0 }, - { AU1000_ACSYNC_INT, IRQ_TYPE_EDGE_RISING, 0 }, - { AU1000_MAC0_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1000_MAC1_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1000_AC97C_INT, IRQ_TYPE_EDGE_RISING, 0 }, + { AU1000_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 1 }, + { AU1000_USB_HOST_INT, IRQ_TYPE_LEVEL_LOW, 1 }, + { AU1000_ACSYNC_INT, IRQ_TYPE_EDGE_RISING, 1 }, + { AU1000_MAC0_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 1 }, + { AU1000_MAC1_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 1 }, + { AU1000_AC97C_INT, IRQ_TYPE_EDGE_RISING, 1 }, #elif defined(CONFIG_SOC_AU1500) - { AU1500_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1000_PCI_INTA, IRQ_TYPE_LEVEL_LOW, 0 }, - { AU1000_PCI_INTB, IRQ_TYPE_LEVEL_LOW, 0 }, - { AU1500_UART3_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1000_PCI_INTC, IRQ_TYPE_LEVEL_LOW, 0 }, - { AU1000_PCI_INTD, IRQ_TYPE_LEVEL_LOW, 0 }, - { AU1000_DMA_INT_BASE, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1000_DMA_INT_BASE+1, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1000_DMA_INT_BASE+2, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1000_DMA_INT_BASE+3, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1000_DMA_INT_BASE+4, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1000_DMA_INT_BASE+5, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1000_DMA_INT_BASE+6, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1000_DMA_INT_BASE+7, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1000_TOY_INT, IRQ_TYPE_EDGE_RISING, 0 }, - { AU1000_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 }, - { AU1000_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 }, + { AU1500_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 1 }, + { AU1000_PCI_INTA, IRQ_TYPE_LEVEL_LOW, 1 }, + { AU1000_PCI_INTB, IRQ_TYPE_LEVEL_LOW, 1 }, + { AU1500_UART3_INT, IRQ_TYPE_LEVEL_HIGH, 1 }, + { AU1000_PCI_INTC, IRQ_TYPE_LEVEL_LOW, 1 }, + { AU1000_PCI_INTD, IRQ_TYPE_LEVEL_LOW, 1 }, + { AU1000_DMA_INT_BASE, IRQ_TYPE_LEVEL_HIGH, 1 }, + { AU1000_DMA_INT_BASE+1, IRQ_TYPE_LEVEL_HIGH, 1 }, + { AU1000_DMA_INT_BASE+2, IRQ_TYPE_LEVEL_HIGH, 1 }, + { AU1000_DMA_INT_BASE+3, IRQ_TYPE_LEVEL_HIGH, 1 }, + { AU1000_DMA_INT_BASE+4, IRQ_TYPE_LEVEL_HIGH, 1 }, + { AU1000_DMA_INT_BASE+5, IRQ_TYPE_LEVEL_HIGH, 1 }, + { AU1000_DMA_INT_BASE+6, IRQ_TYPE_LEVEL_HIGH, 1 }, + { AU1000_DMA_INT_BASE+7, IRQ_TYPE_LEVEL_HIGH, 1 }, + { AU1000_TOY_INT, IRQ_TYPE_EDGE_RISING, 1 }, + { AU1000_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 1 }, + { AU1000_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 1 }, { AU1000_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1 }, - { AU1000_RTC_INT, IRQ_TYPE_EDGE_RISING, 0 }, - { AU1000_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 }, - { AU1000_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 }, + { AU1000_RTC_INT, IRQ_TYPE_EDGE_RISING, 1 }, + { AU1000_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 1 }, + { AU1000_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 1 }, { AU1000_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0 }, { AU1000_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1000_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 0 }, - { AU1000_USB_HOST_INT, IRQ_TYPE_LEVEL_LOW, 0 }, - { AU1000_ACSYNC_INT, IRQ_TYPE_EDGE_RISING, 0 }, - { AU1500_MAC0_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1500_MAC1_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1000_AC97C_INT, IRQ_TYPE_EDGE_RISING, 0 }, + { AU1000_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 1 }, + { AU1000_USB_HOST_INT, IRQ_TYPE_LEVEL_LOW, 1 }, + { AU1000_ACSYNC_INT, IRQ_TYPE_EDGE_RISING, 1 }, + { AU1500_MAC0_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 1 }, + { AU1500_MAC1_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 1 }, + { AU1000_AC97C_INT, IRQ_TYPE_EDGE_RISING, 1 }, #elif defined(CONFIG_SOC_AU1100) - { AU1100_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1100_UART1_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1100_SD_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1100_UART3_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1000_SSI0_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1000_SSI1_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1000_DMA_INT_BASE, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1000_DMA_INT_BASE+1, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1000_DMA_INT_BASE+2, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1000_DMA_INT_BASE+3, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1000_DMA_INT_BASE+4, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1000_DMA_INT_BASE+5, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1000_DMA_INT_BASE+6, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1000_DMA_INT_BASE+7, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1000_TOY_INT, IRQ_TYPE_EDGE_RISING, 0 }, - { AU1000_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 }, - { AU1000_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 }, + { AU1100_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 1 }, + { AU1100_UART1_INT, IRQ_TYPE_LEVEL_HIGH, 1 }, + { AU1100_SD_INT, IRQ_TYPE_LEVEL_HIGH, 1 }, + { AU1100_UART3_INT, IRQ_TYPE_LEVEL_HIGH, 1 }, + { AU1000_SSI0_INT, IRQ_TYPE_LEVEL_HIGH, 1 }, + { AU1000_SSI1_INT, IRQ_TYPE_LEVEL_HIGH, 1 }, + { AU1000_DMA_INT_BASE, IRQ_TYPE_LEVEL_HIGH, 1 }, + { AU1000_DMA_INT_BASE+1, IRQ_TYPE_LEVEL_HIGH, 1 }, + { AU1000_DMA_INT_BASE+2, IRQ_TYPE_LEVEL_HIGH, 1 }, + { AU1000_DMA_INT_BASE+3, IRQ_TYPE_LEVEL_HIGH, 1 }, + { AU1000_DMA_INT_BASE+4, IRQ_TYPE_LEVEL_HIGH, 1 }, + { AU1000_DMA_INT_BASE+5, IRQ_TYPE_LEVEL_HIGH, 1 }, + { AU1000_DMA_INT_BASE+6, IRQ_TYPE_LEVEL_HIGH, 1 }, + { AU1000_DMA_INT_BASE+7, IRQ_TYPE_LEVEL_HIGH, 1 }, + { AU1000_TOY_INT, IRQ_TYPE_EDGE_RISING, 1 }, + { AU1000_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 1 }, + { AU1000_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 1 }, { AU1000_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1 }, - { AU1000_RTC_INT, IRQ_TYPE_EDGE_RISING, 0 }, - { AU1000_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 }, - { AU1000_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 }, + { AU1000_RTC_INT, IRQ_TYPE_EDGE_RISING, 1 }, + { AU1000_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 1 }, + { AU1000_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 1 }, { AU1000_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0 }, - { AU1000_IRDA_TX_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1000_IRDA_RX_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, + { AU1000_IRDA_TX_INT, IRQ_TYPE_LEVEL_HIGH, 1 }, + { AU1000_IRDA_RX_INT, IRQ_TYPE_LEVEL_HIGH, 1 }, { AU1000_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1000_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 0 }, - { AU1000_USB_HOST_INT, IRQ_TYPE_LEVEL_LOW, 0 }, - { AU1000_ACSYNC_INT, IRQ_TYPE_EDGE_RISING, 0 }, - { AU1100_MAC0_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1100_LCD_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1000_AC97C_INT, IRQ_TYPE_EDGE_RISING, 0 }, + { AU1000_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 1 }, + { AU1000_USB_HOST_INT, IRQ_TYPE_LEVEL_LOW, 1 }, + { AU1000_ACSYNC_INT, IRQ_TYPE_EDGE_RISING, 1 }, + { AU1100_MAC0_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 1 }, + { AU1100_LCD_INT, IRQ_TYPE_LEVEL_HIGH, 1 }, + { AU1000_AC97C_INT, IRQ_TYPE_EDGE_RISING, 1 }, #elif defined(CONFIG_SOC_AU1550) - { AU1550_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1550_PCI_INTA, IRQ_TYPE_LEVEL_LOW, 0 }, - { AU1550_PCI_INTB, IRQ_TYPE_LEVEL_LOW, 0 }, - { AU1550_DDMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1550_CRYPTO_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1550_PCI_INTC, IRQ_TYPE_LEVEL_LOW, 0 }, - { AU1550_PCI_INTD, IRQ_TYPE_LEVEL_LOW, 0 }, - { AU1550_PCI_RST_INT, IRQ_TYPE_LEVEL_LOW, 0 }, - { AU1550_UART1_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1550_UART3_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1550_PSC0_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1550_PSC1_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1550_PSC2_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1550_PSC3_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1000_TOY_INT, IRQ_TYPE_EDGE_RISING, 0 }, - { AU1000_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 }, - { AU1000_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 }, + { AU1550_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 1 }, + { AU1550_PCI_INTA, IRQ_TYPE_LEVEL_LOW, 1 }, + { AU1550_PCI_INTB, IRQ_TYPE_LEVEL_LOW, 1 }, + { AU1550_DDMA_INT, IRQ_TYPE_LEVEL_HIGH, 1 }, + { AU1550_CRYPTO_INT, IRQ_TYPE_LEVEL_HIGH, 1 }, + { AU1550_PCI_INTC, IRQ_TYPE_LEVEL_LOW, 1 }, + { AU1550_PCI_INTD, IRQ_TYPE_LEVEL_LOW, 1 }, + { AU1550_PCI_RST_INT, IRQ_TYPE_LEVEL_LOW, 1 }, + { AU1550_UART1_INT, IRQ_TYPE_LEVEL_HIGH, 1 }, + { AU1550_UART3_INT, IRQ_TYPE_LEVEL_HIGH, 1 }, + { AU1550_PSC0_INT, IRQ_TYPE_LEVEL_HIGH, 1 }, + { AU1550_PSC1_INT, IRQ_TYPE_LEVEL_HIGH, 1 }, + { AU1550_PSC2_INT, IRQ_TYPE_LEVEL_HIGH, 1 }, + { AU1550_PSC3_INT, IRQ_TYPE_LEVEL_HIGH, 1 }, + { AU1000_TOY_INT, IRQ_TYPE_EDGE_RISING, 1 }, + { AU1000_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 1 }, + { AU1000_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 1 }, { AU1000_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1 }, - { AU1000_RTC_INT, IRQ_TYPE_EDGE_RISING, 0 }, - { AU1000_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 }, - { AU1000_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 }, + { AU1000_RTC_INT, IRQ_TYPE_EDGE_RISING, 1 }, + { AU1000_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 1 }, + { AU1000_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 1 }, { AU1000_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0 }, - { AU1550_NAND_INT, IRQ_TYPE_EDGE_RISING, 0 }, + { AU1550_NAND_INT, IRQ_TYPE_EDGE_RISING, 1 }, { AU1550_USB_DEV_REQ_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1550_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 0 }, - { AU1550_USB_HOST_INT, IRQ_TYPE_LEVEL_LOW, 0 }, - { AU1550_MAC0_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1550_MAC1_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, + { AU1550_USB_DEV_SUS_INT, IRQ_TYPE_EDGE_RISING, 1 }, + { AU1550_USB_HOST_INT, IRQ_TYPE_LEVEL_LOW, 1 }, + { AU1550_MAC0_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 1 }, + { AU1550_MAC1_DMA_INT, IRQ_TYPE_LEVEL_HIGH, 1 }, #elif defined(CONFIG_SOC_AU1200) - { AU1200_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1200_SWT_INT, IRQ_TYPE_EDGE_RISING, 0 }, - { AU1200_SD_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1200_DDMA_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1200_MAE_BE_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1200_UART1_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1200_MAE_FE_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1200_PSC0_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1200_PSC1_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1200_AES_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1200_CAMERA_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1000_TOY_INT, IRQ_TYPE_EDGE_RISING, 0 }, - { AU1000_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 }, - { AU1000_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 }, + { AU1200_UART0_INT, IRQ_TYPE_LEVEL_HIGH, 1 }, + { AU1200_SWT_INT, IRQ_TYPE_EDGE_RISING, 1 }, + { AU1200_SD_INT, IRQ_TYPE_LEVEL_HIGH, 1 }, + { AU1200_DDMA_INT, IRQ_TYPE_LEVEL_HIGH, 1 }, + { AU1200_MAE_BE_INT, IRQ_TYPE_LEVEL_HIGH, 1 }, + { AU1200_UART1_INT, IRQ_TYPE_LEVEL_HIGH, 1 }, + { AU1200_MAE_FE_INT, IRQ_TYPE_LEVEL_HIGH, 1 }, + { AU1200_PSC0_INT, IRQ_TYPE_LEVEL_HIGH, 1 }, + { AU1200_PSC1_INT, IRQ_TYPE_LEVEL_HIGH, 1 }, + { AU1200_AES_INT, IRQ_TYPE_LEVEL_HIGH, 1 }, + { AU1200_CAMERA_INT, IRQ_TYPE_LEVEL_HIGH, 1 }, + { AU1000_TOY_INT, IRQ_TYPE_EDGE_RISING, 1 }, + { AU1000_TOY_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 1 }, + { AU1000_TOY_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 1 }, { AU1000_TOY_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 1 }, - { AU1000_RTC_INT, IRQ_TYPE_EDGE_RISING, 0 }, - { AU1000_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 0 }, - { AU1000_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 0 }, + { AU1000_RTC_INT, IRQ_TYPE_EDGE_RISING, 1 }, + { AU1000_RTC_MATCH0_INT, IRQ_TYPE_EDGE_RISING, 1 }, + { AU1000_RTC_MATCH1_INT, IRQ_TYPE_EDGE_RISING, 1 }, { AU1000_RTC_MATCH2_INT, IRQ_TYPE_EDGE_RISING, 0 }, - { AU1200_NAND_INT, IRQ_TYPE_EDGE_RISING, 0 }, + { AU1200_NAND_INT, IRQ_TYPE_EDGE_RISING, 1 }, { AU1200_USB_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1200_LCD_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, - { AU1200_MAE_BOTH_INT, IRQ_TYPE_LEVEL_HIGH, 0 }, + { AU1200_LCD_INT, IRQ_TYPE_LEVEL_HIGH, 1 }, + { AU1200_MAE_BOTH_INT, IRQ_TYPE_LEVEL_HIGH, 1 }, #else #error "Error: Unknown Alchemy SOC" @@ -486,7 +490,7 @@ static int au1x_ic_settype(unsigned int irq, unsigned int flow_type) asmlinkage void plat_irq_dispatch(void) { unsigned int pending = read_c0_status() & read_c0_cause(); - unsigned long s, off, bit; + unsigned long s, off; if (pending & CAUSEF_IP7) { do_IRQ(MIPS_CPU_IRQ_BASE + 7); @@ -506,25 +510,12 @@ asmlinkage void plat_irq_dispatch(void) } else goto spurious; - bit = 0; s = au_readl(s); if (unlikely(!s)) { spurious: spurious_interrupt(); return; } -#ifdef AU1000_USB_DEV_REQ_INT - /* - * Because of the tight timing of SETUP token to reply - * transactions, the USB devices-side packet complete - * interrupt needs the highest priority. - */ - bit = 1 << (AU1000_USB_DEV_REQ_INT - AU1000_INTC0_INT_BASE); - if ((pending & CAUSEF_IP2) && (s & bit)) { - do_IRQ(AU1000_USB_DEV_REQ_INT); - return; - } -#endif do_IRQ(__ffs(s) + off); } -- 1.6.3.1 From manuel.lauss@googlemail.com Wed Jun 3 18:03:52 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 03 Jun 2009 18:03:59 +0100 (WEST) Received: from mail-bw0-f225.google.com ([209.85.218.225]:65035 "EHLO mail-bw0-f225.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20022386AbZFCRDE (ORCPT ); Wed, 3 Jun 2009 18:03:04 +0100 Received: by mail-bw0-f225.google.com with SMTP id 25so145388bwz.0 for ; Wed, 03 Jun 2009 10:03:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer:in-reply-to:references; bh=5kbb87JWF/nVFsSnLBP3JQnuQvclrrVNphf15HuNpMc=; b=JCOwYzz4HI9tOFJFxTP1XBCTM6Bl7df0Ma72p3elUt3r18JoSNNZW62V+D//Dlb0pa nMuMnP5NT3NKgyCK/PuxL1rYufdPe8RB3GT7rmfk5BOA2WkLKW81VJ1mxzRuXlpCjlKv ssn12lMfNGU9NWyaU3c3eh90x1KIvSQj6IbJA= DomainKey-Signature: a=rsa-sha1; c=nofws; d=googlemail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; b=D8UqkwkX675Oqtr8gaxuxc/3rkjVn1UQLeUCor9DCMBLbHQ3edAG5oqQZvF3CpiJHl 2kHB/QvhcJToiBntUnknl2HrKcLovvij3N4Lxxp1tW69/wHgWMCzyQdTo7NXXECW8y4+ FQSPj3PRtzkHfGveO3x3kGnb/x0BgUPnH74iI= Received: by 10.204.54.65 with SMTP id p1mr1052488bkg.195.1244048583959; Wed, 03 Jun 2009 10:03:03 -0700 (PDT) Received: from localhost.localdomain (p5496DB58.dip.t-dialin.net [84.150.219.88]) by mx.google.com with ESMTPS id 18sm2452543fks.10.2009.06.03.10.03.01 (version=TLSv1/SSLv3 cipher=RC4-MD5); Wed, 03 Jun 2009 10:03:03 -0700 (PDT) From: Manuel Lauss To: Linux-MIPS , Ralf Baechle Cc: Manuel Lauss Subject: [PATCH 4/5] Alchemy: new PCMCIA socket driver for devboards. Date: Wed, 3 Jun 2009 19:02:47 +0200 Message-Id: <1244048568-18006-5-git-send-email-manuel.lauss@gmail.com> X-Mailer: git-send-email 1.6.3.1 In-Reply-To: <1244048568-18006-4-git-send-email-manuel.lauss@gmail.com> References: <1244048568-18006-1-git-send-email-manuel.lauss@gmail.com> <1244048568-18006-2-git-send-email-manuel.lauss@gmail.com> <1244048568-18006-3-git-send-email-manuel.lauss@gmail.com> <1244048568-18006-4-git-send-email-manuel.lauss@gmail.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23229 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips New PCMCIA socket driver for all Db/Pb1xxx boards (except Pb1000) Notable features: - it builds for all supported boards. - support for carddetect and statuschange (disabled) IRQs. - pcmcia socket mem/io/attr areas and irqs passed through platform resource information. - doesn't freeze system during card insertion/ejection like the old one. Also add platform device registration for all boards supported by this driver. Run-tested on Db1200; however since all of these boards have an identical PCMCIA setup (at least eletrically; some differ in IRQs used) I'm fairly confident that it works on them too. Signed-off-by: Manuel Lauss --- arch/mips/alchemy/common/platform.c | 6 - arch/mips/alchemy/common/setup.c | 3 +- arch/mips/alchemy/devboards/db1200/platform.c | 113 ++++ arch/mips/alchemy/devboards/db1x00/Makefile | 3 +- arch/mips/alchemy/devboards/db1x00/platform.c | 166 +++++ arch/mips/alchemy/devboards/pb1100/Makefile | 3 +- arch/mips/alchemy/devboards/pb1100/platform.c | 83 +++ arch/mips/alchemy/devboards/pb1200/platform.c | 113 ++++- arch/mips/alchemy/devboards/pb1500/Makefile | 3 +- arch/mips/alchemy/devboards/pb1500/platform.c | 83 +++ arch/mips/alchemy/devboards/pb1550/Makefile | 3 +- arch/mips/alchemy/devboards/pb1550/board_setup.c | 3 + arch/mips/alchemy/devboards/pb1550/platform.c | 130 ++++ arch/mips/include/asm/mach-au1x00/au1000.h | 14 + arch/mips/include/asm/mach-db1x00/db1200.h | 15 - arch/mips/include/asm/mach-db1x00/db1x00.h | 8 - arch/mips/include/asm/mach-pb1x00/pb1100.h | 7 - arch/mips/include/asm/mach-pb1x00/pb1200.h | 14 - arch/mips/include/asm/mach-pb1x00/pb1500.h | 7 - arch/mips/include/asm/mach-pb1x00/pb1550.h | 7 - drivers/pcmcia/Kconfig | 17 +- drivers/pcmcia/Makefile | 9 +- drivers/pcmcia/au1000_db1x00.c | 305 ---------- drivers/pcmcia/db1xxx_ss.c | 700 ++++++++++++++++++++++ 24 files changed, 1429 insertions(+), 386 deletions(-) create mode 100644 arch/mips/alchemy/devboards/db1x00/platform.c create mode 100644 arch/mips/alchemy/devboards/pb1100/platform.c create mode 100644 arch/mips/alchemy/devboards/pb1500/platform.c create mode 100644 arch/mips/alchemy/devboards/pb1550/platform.c delete mode 100644 drivers/pcmcia/au1000_db1x00.c create mode 100644 drivers/pcmcia/db1xxx_ss.c diff --git a/arch/mips/alchemy/common/platform.c b/arch/mips/alchemy/common/platform.c index 117f99f..2b76a57 100644 --- a/arch/mips/alchemy/common/platform.c +++ b/arch/mips/alchemy/common/platform.c @@ -308,11 +308,6 @@ static struct platform_device au1200_mmc1_device = { #endif /* #ifndef CONFIG_MIPS_DB1200 */ #endif /* #ifdef CONFIG_SOC_AU1200 */ -static struct platform_device au1x00_pcmcia_device = { - .name = "au1x00-pcmcia", - .id = 0, -}; - /* All Alchemy demoboards with I2C have this #define in their headers */ #ifdef SMBUS_PSC_BASE static struct resource pbdb_smbus_resources[] = { @@ -334,7 +329,6 @@ static struct platform_device pbdb_smbus_device = { static struct platform_device *au1xxx_platform_devices[] __initdata = { &au1xx0_uart_device, &au1xxx_usb_ohci_device, - &au1x00_pcmcia_device, #ifdef CONFIG_FB_AU1100 &au1100_lcd_device, #endif diff --git a/arch/mips/alchemy/common/setup.c b/arch/mips/alchemy/common/setup.c index 3f036b3..e8d27f6 100644 --- a/arch/mips/alchemy/common/setup.c +++ b/arch/mips/alchemy/common/setup.c @@ -103,7 +103,8 @@ phys_t __fixup_bigphys_addr(phys_t phys_addr, phys_t size) * The pseudo address we use is 0xF400 0000. Any address over * 0xF400 0000 is a PCMCIA pseudo address. */ - if ((phys_addr >= 0xF4000000) && (phys_addr < 0xFFFFFFFF)) + if ((phys_addr >= PCMCIA_ATTR_PSEUDO_PHYS) && + (phys_addr < PCMCIA_PSEUDO_END)) return (phys_t)(phys_addr << 4); /* default nop */ diff --git a/arch/mips/alchemy/devboards/db1200/platform.c b/arch/mips/alchemy/devboards/db1200/platform.c index b3142e0..fb63026 100644 --- a/arch/mips/alchemy/devboards/db1200/platform.c +++ b/arch/mips/alchemy/devboards/db1200/platform.c @@ -352,6 +352,117 @@ struct au1xmmc_platform_data au1xmmc_platdata[] = { /**********************************************************************/ +static struct resource db1200_pcmcia0_res[] = { + { + .name = "pseudo-attr", + .flags = IORESOURCE_MEM, + .start = PCMCIA_ATTR_PSEUDO_PHYS, + .end = PCMCIA_ATTR_PSEUDO_PHYS + 0x00040000 - 1, + }, + { + .name = "pseudo-mem", + .flags = IORESOURCE_MEM, + .start = PCMCIA_MEM_PSEUDO_PHYS, + .end = PCMCIA_MEM_PSEUDO_PHYS + 0x00040000 - 1, + }, + { + .name = "pseudo-io", + .flags = IORESOURCE_MEM, + .start = PCMCIA_IO_PSEUDO_PHYS, + .end = PCMCIA_IO_PSEUDO_PHYS + 0x0001000 - 1, + }, + { + .name = "card", + .flags = IORESOURCE_IRQ, + .start = DB1200_PC0_INT, + .end = DB1200_PC0_INT, + }, +#if 0 /* more trouble than it's worth */ + { + .name = "stschg", + .flags = IORESOURCE_IRQ, + .start = DB1200_PC0_STSCHG_INT, + .end = DB1200_PC0_STSCHG_INT, + }, +#endif + { + .name = "insert", + .flags = IORESOURCE_IRQ, + .start = DB1200_PC0_INSERT_INT, + .end = DB1200_PC0_INSERT_INT, + }, + { + .name = "eject", + .flags = IORESOURCE_IRQ, + .start = DB1200_PC0_EJECT_INT, + .end = DB1200_PC0_EJECT_INT, + }, +}; + +static struct platform_device db1200_pcmcia0_dev = { + .name = "pb1200_pcmcia", + .id = 0, + .num_resources = ARRAY_SIZE(db1200_pcmcia0_res), + .resource = db1200_pcmcia0_res, +}; + +/* mem/io resources of 2nd socket at offset 0x00400000 from 1st */ +static struct resource db1200_pcmcia1_res[] = { + { + .name = "pseudo-attr", + .flags = IORESOURCE_MEM, + .start = PCMCIA_ATTR_PSEUDO_PHYS + 0x00400000, + .end = PCMCIA_ATTR_PSEUDO_PHYS + 0x00440000 - 1, + }, + { + .name = "pseudo-mem", + .flags = IORESOURCE_MEM, + .start = PCMCIA_MEM_PSEUDO_PHYS + 0x00400000, + .end = PCMCIA_MEM_PSEUDO_PHYS + 0x00440000 - 1, + }, + { + .name = "pseudo-io", + .flags = IORESOURCE_MEM, + .start = PCMCIA_IO_PSEUDO_PHYS + 0x00400000, + .end = PCMCIA_IO_PSEUDO_PHYS + 0x00401000 - 1, + }, + { + .name = "card", + .flags = IORESOURCE_IRQ, + .start = DB1200_PC1_INT, + .end = DB1200_PC1_INT, + }, +#if 0 /* more trouble than it's worth */ + { + .name = "stschg", + .flags = IORESOURCE_IRQ, + .start = DB1200_PC1_STSCHG_INT, + .end = DB1200_PC1_STSCHG_INT, + }, +#endif + { + .name = "insert", + .flags = IORESOURCE_IRQ, + .start = DB1200_PC1_INSERT_INT, + .end = DB1200_PC1_INSERT_INT, + }, + { + .name = "eject", + .flags = IORESOURCE_IRQ, + .start = DB1200_PC1_EJECT_INT, + .end = DB1200_PC1_EJECT_INT, + }, +}; + +static struct platform_device db1200_pcmcia1_dev = { + .name = "pb1200_pcmcia", + .id = 1, + .num_resources = ARRAY_SIZE(db1200_pcmcia1_res), + .resource = db1200_pcmcia1_res, +}; + +/**********************************************************************/ + static struct resource psc0_res[] = { [0] = { .start = CPHYSADDR(PSC0_BASE_ADDR), @@ -416,6 +527,8 @@ static struct platform_device *db1200_devs[] __initdata = { &smc91x_dev, &rtc_dev, &nand_dev, + &db1200_pcmcia0_dev, + &db1200_pcmcia1_dev, }; static int __init db1200_dev_init(void) diff --git a/arch/mips/alchemy/devboards/db1x00/Makefile b/arch/mips/alchemy/devboards/db1x00/Makefile index 432241a..5024d16 100644 --- a/arch/mips/alchemy/devboards/db1x00/Makefile +++ b/arch/mips/alchemy/devboards/db1x00/Makefile @@ -5,4 +5,5 @@ # Makefile for the Alchemy Semiconductor DBAu1xx0 boards. # -obj-y := board_setup.o irqmap.o +obj-y := board_setup.o irqmap.o platform.o + diff --git a/arch/mips/alchemy/devboards/db1x00/platform.c b/arch/mips/alchemy/devboards/db1x00/platform.c new file mode 100644 index 0000000..1b50b1a --- /dev/null +++ b/arch/mips/alchemy/devboards/db1x00/platform.c @@ -0,0 +1,166 @@ +/* + * DBAu1xxx board platform device registration + * + * Copyright (C) 2009 Manuel Lauss + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include + +#include + +#if defined(CONFIG_MIPS_DB1000) || defined(CONFIG_MIPS_DB1100) || \ + defined(CONFIG_MIPS_DB1500) || defined(CONFIG_MIPS_DB1550) +#define DB1XXX_HAS_PCMCIA +#endif + +/* DB1xxx PCMCIA interrupt sources: + * CD0/1 GPIO0/3 + * STSCHG0/1 GPIO1/4 + * CARD0/1 GPIO2/5 + * Db1550: 0/1, 21/22, 3/5 + */ +#ifndef CONFIG_MIPS_DB1550 +/* Db1000, Db1100, Db1500 */ +#define DB1XXX_PCMCIA_DRVNAME "db1xxx_pcmcia" +#define DB1XXX_PCMCIA_CD0 AU1000_GPIO_0 +#define DB1XXX_PCMCIA_STSCHG0 AU1000_GPIO_1 +#define DB1XXX_PCMCIA_CARD0 AU1000_GPIO_2 +#define DB1XXX_PCMCIA_CD1 AU1000_GPIO_3 +#define DB1XXX_PCMCIA_STSCHG1 AU1000_GPIO_4 +#define DB1XXX_PCMCIA_CARD1 AU1000_GPIO_5 +#else +#define DB1XXX_PCMCIA_DRVNAME "pb1550_pcmcia" +#define DB1XXX_PCMCIA_CD0 AU1000_GPIO_0 +#define DB1XXX_PCMCIA_STSCHG0 AU1500_GPIO_21 +#define DB1XXX_PCMCIA_CARD0 AU1000_GPIO_3 +#define DB1XXX_PCMCIA_CD1 AU1000_GPIO_1 +#define DB1XXX_PCMCIA_STSCHG1 AU1500_GPIO_22 +#define DB1XXX_PCMCIA_CARD1 AU1000_GPIO_5 +#endif + +#ifdef DB1XXX_HAS_PCMCIA +static struct resource db1xxx_pcmcia0_res[] = { + { + .name = "pseudo-attr", + .flags = IORESOURCE_MEM, + .start = PCMCIA_ATTR_PSEUDO_PHYS, + .end = PCMCIA_ATTR_PSEUDO_PHYS + 0x00040000 - 1, + }, + { + .name = "pseudo-mem", + .flags = IORESOURCE_MEM, + .start = PCMCIA_MEM_PSEUDO_PHYS, + .end = PCMCIA_MEM_PSEUDO_PHYS + 0x00040000 - 1, + }, + { + .name = "pseudo-io", + .flags = IORESOURCE_MEM, + .start = PCMCIA_IO_PSEUDO_PHYS, + .end = PCMCIA_IO_PSEUDO_PHYS + 0x0001000 - 1, + }, + { + .name = "insert", + .flags = IORESOURCE_IRQ, + .start = DB1XXX_PCMCIA_CD0, + .end = DB1XXX_PCMCIA_CD0, + }, +#if 0 /* more trouble than it's worth */ + { + .name = "stschg", + .flags = IORESOURCE_IRQ, + .start = DB1XXX_PCMCIA_STSCHG0, + .end = DB1XXX_PCMCIA_STSCHG0, + }, +#endif + { + .name = "card", + .flags = IORESOURCE_IRQ, + .start = DB1XXX_PCMCIA_CARD0, + .end = DB1XXX_PCMCIA_CARD0, + }, +}; + +static struct platform_device db1xxx_pcmcia0_dev = { + .name = DB1XXX_PCMCIA_DRVNAME, + .id = 0, + .num_resources = ARRAY_SIZE(db1xxx_pcmcia0_res), + .resource = db1xxx_pcmcia0_res, +}; + +/* mem/io resources of 2nd socket at offset 0x00400000 from 1st */ +static struct resource db1xxx_pcmcia1_res[] = { + { + .name = "pseudo-attr", + .flags = IORESOURCE_MEM, + .start = PCMCIA_ATTR_PSEUDO_PHYS + 0x00400000, + .end = PCMCIA_ATTR_PSEUDO_PHYS + 0x00440000 - 1, + }, + { + .name = "pseudo-mem", + .flags = IORESOURCE_MEM, + .start = PCMCIA_MEM_PSEUDO_PHYS + 0x00400000, + .end = PCMCIA_MEM_PSEUDO_PHYS + 0x00440000 - 1, + }, + { + .name = "pseudo-io", + .flags = IORESOURCE_MEM, + .start = PCMCIA_IO_PSEUDO_PHYS + 0x00400000, + .end = PCMCIA_IO_PSEUDO_PHYS + 0x00401000 - 1, + }, + { + .name = "insert", + .flags = IORESOURCE_IRQ, + .start = DB1XXX_PCMCIA_CD1, + .end = DB1XXX_PCMCIA_CD1, + }, +#if 0 /* more trouble than it's worth */ + { + .name = "stschg", + .flags = IORESOURCE_IRQ, + .start = DB1XXX_PCMCIA_STSCHG1, + .end = DB1XXX_PCMCIA_STSCHG1, + }, +#endif + { + .name = "card", + .flags = IORESOURCE_IRQ, + .start = DB1XXX_PCMCIA_CARD1, + .end = DB1XXX_PCMCIA_CARD1, + }, +}; + +static struct platform_device db1xxx_pcmcia1_dev = { + .name = DB1XXX_PCMCIA_DRVNAME, + .id = 1, + .num_resources = ARRAY_SIZE(db1xxx_pcmcia1_res), + .resource = db1xxx_pcmcia1_res, +}; +#endif + +static struct platform_device *db1xxx_devs[] __initdata = { +#ifdef DB1XXX_HAS_PCMCIA + &db1xxx_pcmcia0_dev, + &db1xxx_pcmcia1_dev, +#endif +}; + +static int __init db1xxx_dev_init(void) +{ + return platform_add_devices(db1xxx_devs, ARRAY_SIZE(db1xxx_devs)); +} +device_initcall(db1xxx_dev_init); diff --git a/arch/mips/alchemy/devboards/pb1100/Makefile b/arch/mips/alchemy/devboards/pb1100/Makefile index c586dd7..60cf5b9 100644 --- a/arch/mips/alchemy/devboards/pb1100/Makefile +++ b/arch/mips/alchemy/devboards/pb1100/Makefile @@ -5,4 +5,5 @@ # Makefile for the Alchemy Semiconductor Pb1100 board. # -obj-y := board_setup.o +obj-y := board_setup.o platform.o + diff --git a/arch/mips/alchemy/devboards/pb1100/platform.c b/arch/mips/alchemy/devboards/pb1100/platform.c new file mode 100644 index 0000000..fb52b4b --- /dev/null +++ b/arch/mips/alchemy/devboards/pb1100/platform.c @@ -0,0 +1,83 @@ +/* + * Pb1100 board platform device registration + * + * Copyright (C) 2009 Manuel Lauss + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include + +#include + +/* PCMCIA. single socket, identical to Pb1500 */ +static struct resource pb1100_pcmcia_res[] = { + { + .name = "pseudo-attr", + .flags = IORESOURCE_MEM, + .start = PCMCIA_ATTR_PSEUDO_PHYS, + .end = PCMCIA_ATTR_PSEUDO_PHYS + 0x00040000 - 1, + }, + { + .name = "pseudo-mem", + .flags = IORESOURCE_MEM, + .start = PCMCIA_MEM_PSEUDO_PHYS, + .end = PCMCIA_MEM_PSEUDO_PHYS + 0x00040000 - 1, + }, + { + .name = "pseudo-io", + .flags = IORESOURCE_MEM, + .start = PCMCIA_IO_PSEUDO_PHYS, + .end = PCMCIA_IO_PSEUDO_PHYS + 0x0001000 - 1, + }, + { + .name = "insert", + .flags = IORESOURCE_IRQ, + .start = AU1000_GPIO_9, + .end = AU1000_GPIO_9, + }, +#if 0 /* more trouble than it's worth */ + { + .name = "stschg", + .flags = IORESOURCE_IRQ, + .start = AU1000_GPIO_10, + .end = AU1000_GPIO_10, + }, +#endif + { + .name = "card", + .flags = IORESOURCE_IRQ, + .start = AU1000_GPIO_11, + .end = AU1000_GPIO_11, + }, +}; + +static struct platform_device pb1100_pcmcia_dev = { + .name = "pb1100_pcmcia", + .id = 0, + .num_resources = ARRAY_SIZE(pb1100_pcmcia_res), + .resource = pb1100_pcmcia_res, +}; + +static struct platform_device *pb1100_devs[] __initdata = { + &pb1100_pcmcia_dev, +}; + +static int __init pb1100_dev_init(void) +{ + return platform_add_devices(pb1100_devs, ARRAY_SIZE(pb1100_devs)); +} +device_initcall(pb1100_dev_init); diff --git a/arch/mips/alchemy/devboards/pb1200/platform.c b/arch/mips/alchemy/devboards/pb1200/platform.c index 4d6edd8..c49fb10 100644 --- a/arch/mips/alchemy/devboards/pb1200/platform.c +++ b/arch/mips/alchemy/devboards/pb1200/platform.c @@ -158,9 +158,120 @@ static struct platform_device smc91c111_device = { .resource = smc91c111_resources }; +static struct resource pb1200_pcmcia0_res[] = { + { + .name = "pseudo-attr", + .flags = IORESOURCE_MEM, + .start = PCMCIA_ATTR_PSEUDO_PHYS, + .end = PCMCIA_ATTR_PSEUDO_PHYS + 0x00040000 - 1, + }, + { + .name = "pseudo-mem", + .flags = IORESOURCE_MEM, + .start = PCMCIA_MEM_PSEUDO_PHYS, + .end = PCMCIA_MEM_PSEUDO_PHYS + 0x00040000 - 1, + }, + { + .name = "pseudo-io", + .flags = IORESOURCE_MEM, + .start = PCMCIA_IO_PSEUDO_PHYS, + .end = PCMCIA_IO_PSEUDO_PHYS + 0x0001000 - 1, + }, + { + .name = "card", + .flags = IORESOURCE_IRQ, + .start = PB1200_PC0_INT, + .end = PB1200_PC0_INT, + }, +#if 0 /* more trouble than what it's worth */ + { + .name = "stschg", + .flags = IORESOURCE_IRQ, + .start = PB1200_PC0_STSCHG_INT, + .end = PB1200_PC0_STSCHG_INT, + }, +#endif + { + .name = "insert", + .flags = IORESOURCE_IRQ, + .start = PB1200_PC0_INSERT_INT, + .end = PB1200_PC0_INSERT_INT, + }, + { + .name = "eject", + .flags = IORESOURCE_IRQ, + .start = PB1200_PC0_EJECT_INT, + .end = PB1200_PC0_EJECT_INT, + }, +}; + +static struct platform_device pb1200_pcmcia0_dev = { + .name = "pb1200_pcmcia", + .id = 0, + .num_resources = ARRAY_SIZE(pb1200_pcmcia0_res), + .resource = pb1200_pcmcia0_res, +}; + +/* mem/io resources of 2nd socket at offset 0x00800000 from 1st */ +static struct resource pb1200_pcmcia1_res[] = { + { + .name = "pseudo-attr", + .flags = IORESOURCE_MEM, + .start = PCMCIA_ATTR_PSEUDO_PHYS + 0x00800000, + .end = PCMCIA_ATTR_PSEUDO_PHYS + 0x00840000 - 1, + }, + { + .name = "pseudo-mem", + .flags = IORESOURCE_MEM, + .start = PCMCIA_MEM_PSEUDO_PHYS + 0x00800000, + .end = PCMCIA_MEM_PSEUDO_PHYS + 0x00840000 - 1, + }, + { + .name = "pseudo-io", + .flags = IORESOURCE_MEM, + .start = PCMCIA_IO_PSEUDO_PHYS + 0x00800000, + .end = PCMCIA_IO_PSEUDO_PHYS + 0x00801000 - 1, + }, + { + .name = "card", + .flags = IORESOURCE_IRQ, + .start = PB1200_PC1_INT, + .end = PB1200_PC1_INT, + }, +#if 0 /* too much trouble than what it's worth */ + { + .name = "stschg", + .flags = IORESOURCE_IRQ, + .start = PB1200_PC1_STSCHG_INT, + .end = PB1200_PC1_STSCHG_INT, + }, +#endif + { + .name = "insert", + .flags = IORESOURCE_IRQ, + .start = PB1200_PC1_INSERT_INT, + .end = PB1200_PC1_INSERT_INT, + }, + { + .name = "eject", + .flags = IORESOURCE_IRQ, + .start = PB1200_PC1_EJECT_INT, + .end = PB1200_PC1_EJECT_INT, + }, +}; + +static struct platform_device pb1200_pcmcia1_dev = { + .name = "pb1200_pcmcia", + .id = 1, + .num_resources = ARRAY_SIZE(pb1200_pcmcia1_res), + .resource = pb1200_pcmcia1_res, +}; + static struct platform_device *board_platform_devices[] __initdata = { &ide_device, - &smc91c111_device + &smc91c111_device, + &pb1200_pcmcia0_dev, + &pb1200_pcmcia1_dev }; static int __init board_register_devices(void) diff --git a/arch/mips/alchemy/devboards/pb1500/Makefile b/arch/mips/alchemy/devboards/pb1500/Makefile index 173b419..c29545d 100644 --- a/arch/mips/alchemy/devboards/pb1500/Makefile +++ b/arch/mips/alchemy/devboards/pb1500/Makefile @@ -5,4 +5,5 @@ # Makefile for the Alchemy Semiconductor Pb1500 board. # -obj-y := board_setup.o +obj-y := board_setup.o platform.o + diff --git a/arch/mips/alchemy/devboards/pb1500/platform.c b/arch/mips/alchemy/devboards/pb1500/platform.c new file mode 100644 index 0000000..36a4034 --- /dev/null +++ b/arch/mips/alchemy/devboards/pb1500/platform.c @@ -0,0 +1,83 @@ +/* + * Pb1500 board platform device registration + * + * Copyright (C) 2009 Manuel Lauss + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include + +#include + +/* PCMCIA: single socket, identical to PB1100 */ +static struct resource pb1500_pcmcia_res[] = { + { + .name = "pseudo-attr", + .flags = IORESOURCE_MEM, + .start = PCMCIA_ATTR_PSEUDO_PHYS, + .end = PCMCIA_ATTR_PSEUDO_PHYS + 0x00040000 - 1, + }, + { + .name = "pseudo-mem", + .flags = IORESOURCE_MEM, + .start = PCMCIA_MEM_PSEUDO_PHYS, + .end = PCMCIA_MEM_PSEUDO_PHYS + 0x00040000 - 1, + }, + { + .name = "pseudo-io", + .flags = IORESOURCE_MEM, + .start = PCMCIA_IO_PSEUDO_PHYS, + .end = PCMCIA_IO_PSEUDO_PHYS + 0x0001000 - 1, + }, + { + .name = "insert", + .flags = IORESOURCE_IRQ, + .start = AU1000_GPIO_9, + .end = AU1000_GPIO_9, + }, +#if 0 /* more trouble than it's worth */ + { + .name = "stschg", + .flags = IORESOURCE_IRQ, + .start = AU1000_GPIO_10, + .end = AU1000_GPIO_10, + }, +#endif + { + .name = "card", + .flags = IORESOURCE_IRQ, + .start = AU1000_GPIO_11, + .end = AU1000_GPIO_11, + }, +}; + +static struct platform_device pb1500_pcmcia_dev = { + .name = "pb1100_pcmcia", + .id = 0, + .num_resources = ARRAY_SIZE(pb1500_pcmcia_res), + .resource = pb1500_pcmcia_res, +}; + +static struct platform_device *pb1500_devs[] __initdata = { + &pb1500_pcmcia_dev, +}; + +static int __init pb1500_dev_init(void) +{ + return platform_add_devices(pb1500_devs, ARRAY_SIZE(pb1500_devs)); +} +device_initcall(pb1500_dev_init); diff --git a/arch/mips/alchemy/devboards/pb1550/Makefile b/arch/mips/alchemy/devboards/pb1550/Makefile index cff95bc..86b410b 100644 --- a/arch/mips/alchemy/devboards/pb1550/Makefile +++ b/arch/mips/alchemy/devboards/pb1550/Makefile @@ -5,4 +5,5 @@ # Makefile for the Alchemy Semiconductor Pb1550 board. # -obj-y := board_setup.o +obj-y := board_setup.o platform.o + diff --git a/arch/mips/alchemy/devboards/pb1550/board_setup.c b/arch/mips/alchemy/devboards/pb1550/board_setup.c index b6e9e7d..56d33df 100644 --- a/arch/mips/alchemy/devboards/pb1550/board_setup.c +++ b/arch/mips/alchemy/devboards/pb1550/board_setup.c @@ -32,6 +32,7 @@ #include #include +#include #include @@ -76,6 +77,8 @@ void __init board_setup(void) } #endif + alchemy_gpio2_enable(); + /* * Enable PSC1 SYNC for AC'97. Normaly done in audio driver, * but it is board specific code, so put it here. diff --git a/arch/mips/alchemy/devboards/pb1550/platform.c b/arch/mips/alchemy/devboards/pb1550/platform.c new file mode 100644 index 0000000..11c91b5 --- /dev/null +++ b/arch/mips/alchemy/devboards/pb1550/platform.c @@ -0,0 +1,130 @@ +/* + * Pb1550 board platform device registration + * + * Copyright (C) 2009 Manuel Lauss + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include + +#include +#include + +/* Pb1550, like all others, also has statuschange irqs; however they're + * wired up on one of the Au1550's shared GPIO201_205 line, which also + * services the PCMCIA card interrupts. So we ignore statuschange and + * use the GPIO201_205 exclusively for card interrupts, since a) pcmcia + * drivers are used to shared irqs and b) statuschange isn't really use- + * ful anyway. + */ +static struct resource pb1550_pcmcia0_res[] = { + { + .name = "pseudo-attr", + .flags = IORESOURCE_MEM, + .start = PCMCIA_ATTR_PSEUDO_PHYS, + .end = PCMCIA_ATTR_PSEUDO_PHYS + 0x00040000 - 1, + }, + { + .name = "pseudo-mem", + .flags = IORESOURCE_MEM, + .start = PCMCIA_MEM_PSEUDO_PHYS, + .end = PCMCIA_MEM_PSEUDO_PHYS + 0x00040000 - 1, + }, + { + .name = "pseudo-io", + .flags = IORESOURCE_MEM, + .start = PCMCIA_IO_PSEUDO_PHYS, + .end = PCMCIA_IO_PSEUDO_PHYS + 0x0001000 - 1, + }, + { + .name = "insert", + .flags = IORESOURCE_IRQ, + .start = AU1000_GPIO_0, + .end = AU1000_GPIO_0, + }, + { /* is GPIO_201, but this one shares an IRQ with 201-205 */ + .name = "card", + .flags = IORESOURCE_IRQ, + .start = AU1500_GPIO_201_205, + .end = AU1500_GPIO_201_205, + }, +}; + +static struct platform_device pb1550_pcmcia0_dev = { + .name = "pb1550_pcmcia", + .id = 0, + .num_resources = ARRAY_SIZE(pb1550_pcmcia0_res), + .resource = pb1550_pcmcia0_res, +}; + +/* mem/io resources of 2nd socket at offset 0x00800000 from 1st */ +static struct resource pb1550_pcmcia1_res[] = { + { + .name = "pseudo-attr", + .flags = IORESOURCE_MEM, + .start = PCMCIA_ATTR_PSEUDO_PHYS + 0x00800000, + .end = PCMCIA_ATTR_PSEUDO_PHYS + 0x00840000 - 1, + }, + { + .name = "pseudo-mem", + .flags = IORESOURCE_MEM, + .start = PCMCIA_MEM_PSEUDO_PHYS + 0x00800000, + .end = PCMCIA_MEM_PSEUDO_PHYS + 0x00840000 - 1, + }, + { + .name = "pseudo-io", + .flags = IORESOURCE_MEM, + .start = PCMCIA_IO_PSEUDO_PHYS + 0x00800000, + .end = PCMCIA_IO_PSEUDO_PHYS + 0x00801000 - 1, + }, + { + .name = "insert", + .flags = IORESOURCE_IRQ, + .start = AU1000_GPIO_1, + .end = AU1000_GPIO_1, + }, + { /* is GPIO_202, but this one shares an IRQ with 201-205 */ + .name = "card", + .flags = IORESOURCE_IRQ, + .start = AU1500_GPIO_201_205, + .end = AU1500_GPIO_201_205, + }, +}; + +static struct platform_device pb1550_pcmcia1_dev = { + .name = "pb1550_pcmcia", + .id = 1, + .num_resources = ARRAY_SIZE(pb1550_pcmcia1_res), + .resource = pb1550_pcmcia1_res, +}; + +static struct platform_device *board_platform_devices[] __initdata = { + &pb1550_pcmcia0_dev, + &pb1550_pcmcia1_dev +}; + +static int __init board_register_devices(void) +{ + /* activate PCMCIA card interrupts */ + alchemy_gpio2_enable_int(201); + alchemy_gpio2_enable_int(202); + + return platform_add_devices(board_platform_devices, + ARRAY_SIZE(board_platform_devices)); +} +arch_initcall(board_register_devices); diff --git a/arch/mips/include/asm/mach-au1x00/au1000.h b/arch/mips/include/asm/mach-au1x00/au1000.h index 854e95f..df04e91 100644 --- a/arch/mips/include/asm/mach-au1x00/au1000.h +++ b/arch/mips/include/asm/mach-au1x00/au1000.h @@ -1739,6 +1739,20 @@ enum soc_au1200_ints { #endif +/* + * All Au1xx0 SOCs have a PCMCIA controller. + * We setup our 32-bit pseudo addresses to be equal to the + * 36-bit addr >> 4, to make it easier to check the address + * and fix it. + * The PCMCIA socket 0 physical attribute address is 0xF 4000 0000. + * The pseudo address we use is 0xF400 0000. Any address over + * 0xF400 0000 is a PCMCIA pseudo address. + */ +#define PCMCIA_IO_PSEUDO_PHYS (PCMCIA_IO_PHYS_ADDR >> 4) +#define PCMCIA_ATTR_PSEUDO_PHYS (PCMCIA_ATTR_PHYS_ADDR >> 4) +#define PCMCIA_MEM_PSEUDO_PHYS (PCMCIA_MEM_PHYS_ADDR >> 4) +#define PCMCIA_PSEUDO_END (0xffffffff) + #ifndef _LANGUAGE_ASSEMBLY typedef volatile struct { /* 0x0000 */ u32 toytrim; diff --git a/arch/mips/include/asm/mach-db1x00/db1200.h b/arch/mips/include/asm/mach-db1x00/db1200.h index 2a54103..acb7042 100644 --- a/arch/mips/include/asm/mach-db1x00/db1200.h +++ b/arch/mips/include/asm/mach-db1x00/db1200.h @@ -190,21 +190,6 @@ enum external_pb1200_ints { DB1200_INT_END = DB1200_INT_BEGIN + 15, }; - -/* - * DBAu1200 specific PCMCIA defines for drivers/pcmcia/au1000_db1x00.c - */ -#define PCMCIA_MAX_SOCK 1 -#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1) - -/* VPP/VCC */ -#define SET_VCC_VPP(VCC, VPP, SLOT) \ - ((((VCC) << 2) | ((VPP) << 0)) << ((SLOT) * 8)) - -#define BOARD_PC0_INT DB1200_PC0_INT -#define BOARD_PC1_INT DB1200_PC1_INT -#define BOARD_CARD_INSERTED(SOCKET) bcsr->sig_status & (1 << (8 + (2 * SOCKET))) - /* NAND chip select */ #define NAND_CS 1 diff --git a/arch/mips/include/asm/mach-db1x00/db1x00.h b/arch/mips/include/asm/mach-db1x00/db1x00.h index 1a515b8..d654434 100644 --- a/arch/mips/include/asm/mach-db1x00/db1x00.h +++ b/arch/mips/include/asm/mach-db1x00/db1x00.h @@ -137,14 +137,6 @@ typedef volatile struct #define BCSR_SWRESET_RESET 0x0080 -/* PCMCIA DBAu1x00 specific defines */ -#define PCMCIA_MAX_SOCK 1 -#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1) - -/* VPP/VCC */ -#define SET_VCC_VPP(VCC, VPP, SLOT)\ - ((((VCC) << 2) | ((VPP) << 0)) << ((SLOT) * 8)) - /* * NAND defines * diff --git a/arch/mips/include/asm/mach-pb1x00/pb1100.h b/arch/mips/include/asm/mach-pb1x00/pb1100.h index b1a60f1..2621f65 100644 --- a/arch/mips/include/asm/mach-pb1x00/pb1100.h +++ b/arch/mips/include/asm/mach-pb1x00/pb1100.h @@ -75,11 +75,4 @@ */ #define PB1100_HEX_LED 0xAE000018 -/* PCMCIA Pb1100 specific defines */ -#define PCMCIA_MAX_SOCK 0 -#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1) - -/* VPP/VCC */ -#define SET_VCC_VPP(VCC, VPP) (((VCC) << 2) | ((VPP) << 0)) - #endif /* __ASM_PB1100_H */ diff --git a/arch/mips/include/asm/mach-pb1x00/pb1200.h b/arch/mips/include/asm/mach-pb1x00/pb1200.h index c8618df..fa1c295 100644 --- a/arch/mips/include/asm/mach-pb1x00/pb1200.h +++ b/arch/mips/include/asm/mach-pb1x00/pb1200.h @@ -239,20 +239,6 @@ enum external_pb1200_ints { PB1200_INT_END = PB1200_INT_BEGIN + 15 }; -/* - * Pb1200 specific PCMCIA defines for drivers/pcmcia/au1000_db1x00.c - */ -#define PCMCIA_MAX_SOCK 1 -#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1) - -/* VPP/VCC */ -#define SET_VCC_VPP(VCC, VPP, SLOT) \ - ((((VCC) << 2) | ((VPP) << 0)) << ((SLOT) * 8)) - -#define BOARD_PC0_INT PB1200_PC0_INT -#define BOARD_PC1_INT PB1200_PC1_INT -#define BOARD_CARD_INSERTED(SOCKET) bcsr->sig_status & (1 << (8 + (2 * SOCKET))) - /* NAND chip select */ #define NAND_CS 1 diff --git a/arch/mips/include/asm/mach-pb1x00/pb1500.h b/arch/mips/include/asm/mach-pb1x00/pb1500.h index da51a2e..66b770a 100644 --- a/arch/mips/include/asm/mach-pb1x00/pb1500.h +++ b/arch/mips/include/asm/mach-pb1x00/pb1500.h @@ -39,11 +39,4 @@ #define PB1500_HEX_LED 0xAF000004 #define PB1500_HEX_LED_BLANK 0xAF000008 -/* PCMCIA Pb1500 specific defines */ -#define PCMCIA_MAX_SOCK 0 -#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1) - -/* VPP/VCC */ -#define SET_VCC_VPP(VCC, VPP) (((VCC) << 2) | ((VPP) << 0)) - #endif /* __ASM_PB1500_H */ diff --git a/arch/mips/include/asm/mach-pb1x00/pb1550.h b/arch/mips/include/asm/mach-pb1x00/pb1550.h index 6704a11..c437d9b 100644 --- a/arch/mips/include/asm/mach-pb1x00/pb1550.h +++ b/arch/mips/include/asm/mach-pb1x00/pb1550.h @@ -129,13 +129,6 @@ static BCSR * const bcsr = (BCSR *)BCSR_PHYS_ADDR; #define BCSR_SYSTEM_POWEROFF 0x4000 #define BCSR_SYSTEM_RESET 0x8000 -#define PCMCIA_MAX_SOCK 1 -#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1) - -/* VPP/VCC */ -#define SET_VCC_VPP(VCC, VPP, SLOT) \ - ((((VCC) << 2) | ((VPP) << 0)) << ((SLOT) * 8)) - #if defined(CONFIG_MTD_PB1550_BOOT) && defined(CONFIG_MTD_PB1550_USER) #define PB1550_BOTH_BANKS #elif defined(CONFIG_MTD_PB1550_BOOT) && !defined(CONFIG_MTD_PB1550_USER) diff --git a/drivers/pcmcia/Kconfig b/drivers/pcmcia/Kconfig index 2764735..c94ba1e 100644 --- a/drivers/pcmcia/Kconfig +++ b/drivers/pcmcia/Kconfig @@ -82,7 +82,7 @@ config PCMCIA_IOCTL If unsure, say Y. config CARDBUS - bool "32-bit CardBus support" + bool "32-bit CardBus support" depends on PCI default y ---help--- @@ -105,8 +105,8 @@ config YENTA select PCCARD_NONSTATIC ---help--- This option enables support for CardBus host bridges. Virtually - all modern PCMCIA bridges are CardBus compatible. A "bridge" is - the hardware inside your computer that PCMCIA cards are plugged + all modern PCMCIA bridges are CardBus compatible. A "bridge" is + the hardware inside your computer that PCMCIA cards are plugged into. To compile this driver as modules, choose M here: the @@ -192,6 +192,17 @@ config PCMCIA_AU1X00 tristate "Au1x00 pcmcia support" depends on SOC_AU1X00 && PCMCIA +config PCMCIA_ALCHEMY_DEVBOARD + tristate "Alchemy Db/Pb1xxx PCMCIA socket services" + depends on SOC_AU1X00 && PCMCIA + select 64BIT_PHYS_ADDR + help + Enable this driver of you want PCMCIA support on your Alchemy + Db1000, Db/Pb1100, Db/Pb1500, Db/Pb1550, Db/Pb1200 board. + NOT suitable for the PB1000! + + This driver is also available as a module called db1xxx_ss.ko + config PCMCIA_SA1100 tristate "SA1100 support" depends on ARM && ARCH_SA1100 && PCMCIA diff --git a/drivers/pcmcia/Makefile b/drivers/pcmcia/Makefile index bbac463..3c52108 100644 --- a/drivers/pcmcia/Makefile +++ b/drivers/pcmcia/Makefile @@ -33,20 +33,13 @@ obj-$(CONFIG_OMAP_CF) += omap_cf.o obj-$(CONFIG_BFIN_CFPCMCIA) += bfin_cf_pcmcia.o obj-$(CONFIG_AT91_CF) += at91_cf.o obj-$(CONFIG_ELECTRA_CF) += electra_cf.o +obj-$(CONFIG_PCMCIA_ALCHEMY_DEVBOARD) += db1xxx_ss.o sa11xx_core-y += soc_common.o sa11xx_base.o pxa2xx_core-y += soc_common.o pxa2xx_base.o au1x00_ss-y += au1000_generic.o au1x00_ss-$(CONFIG_MIPS_PB1000) += au1000_pb1x00.o -au1x00_ss-$(CONFIG_MIPS_PB1100) += au1000_pb1x00.o -au1x00_ss-$(CONFIG_MIPS_PB1200) += au1000_db1x00.o -au1x00_ss-$(CONFIG_MIPS_PB1500) += au1000_pb1x00.o -au1x00_ss-$(CONFIG_MIPS_DB1000) += au1000_db1x00.o -au1x00_ss-$(CONFIG_MIPS_DB1100) += au1000_db1x00.o -au1x00_ss-$(CONFIG_MIPS_DB1200) += au1000_db1x00.o -au1x00_ss-$(CONFIG_MIPS_DB1500) += au1000_db1x00.o -au1x00_ss-$(CONFIG_MIPS_DB1550) += au1000_db1x00.o au1x00_ss-$(CONFIG_MIPS_XXS1500) += au1000_xxs1500.o sa1111_cs-y += sa1111_generic.o diff --git a/drivers/pcmcia/au1000_db1x00.c b/drivers/pcmcia/au1000_db1x00.c deleted file mode 100644 index c78d77f..0000000 --- a/drivers/pcmcia/au1000_db1x00.c +++ /dev/null @@ -1,305 +0,0 @@ -/* - * - * Alchemy Semi Db1x00 boards specific pcmcia routines. - * - * Copyright 2002 MontaVista Software Inc. - * Author: MontaVista Software, Inc. - * ppopov@mvista.com or source@mvista.com - * - * Copyright 2004 Pete Popov, updated the driver to 2.6. - * Followed the sa11xx API and largely copied many of the hardware - * independent functions. - * - * ######################################################################## - * - * This program is free software; you can distribute it and/or modify it - * under the terms of the GNU General Public License (Version 2) as - * published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License - * for more details. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. - * - * ######################################################################## - * - * - */ - -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#if defined(CONFIG_MIPS_DB1200) - #include -#elif defined(CONFIG_MIPS_PB1200) - #include -#else - #include - static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR; -#endif - -#include "au1000_generic.h" - -#if 0 -#define debug(x,args...) printk(KERN_DEBUG "%s: " x, __func__ , ##args) -#else -#define debug(x,args...) -#endif - - -struct au1000_pcmcia_socket au1000_pcmcia_socket[PCMCIA_NUM_SOCKS]; -extern int au1x00_pcmcia_socket_probe(struct device *, struct pcmcia_low_level *, int, int); - -static int db1x00_pcmcia_hw_init(struct au1000_pcmcia_socket *skt) -{ -#ifdef CONFIG_MIPS_DB1550 - skt->irq = skt->nr ? AU1000_GPIO_5 : AU1000_GPIO_3; -#elif defined(CONFIG_MIPS_DB1200) || defined(CONFIG_MIPS_PB1200) - skt->irq = skt->nr ? BOARD_PC1_INT : BOARD_PC0_INT; -#else - skt->irq = skt->nr ? AU1000_GPIO_5 : AU1000_GPIO_2; -#endif - return 0; -} - -static void db1x00_pcmcia_shutdown(struct au1000_pcmcia_socket *skt) -{ - bcsr->pcmcia = 0; /* turn off power */ - au_sync_delay(2); -} - -static void -db1x00_pcmcia_socket_state(struct au1000_pcmcia_socket *skt, struct pcmcia_state *state) -{ - u32 inserted; - unsigned char vs; - - state->ready = 0; - state->vs_Xv = 0; - state->vs_3v = 0; - state->detect = 0; - - switch (skt->nr) { - case 0: - vs = bcsr->status & 0x3; -#if defined(CONFIG_MIPS_DB1200) || defined(CONFIG_MIPS_PB1200) - inserted = BOARD_CARD_INSERTED(0); -#else - inserted = !(bcsr->status & (1<<4)); -#endif - break; - case 1: - vs = (bcsr->status & 0xC)>>2; -#if defined(CONFIG_MIPS_DB1200) || defined(CONFIG_MIPS_PB1200) - inserted = BOARD_CARD_INSERTED(1); -#else - inserted = !(bcsr->status & (1<<5)); -#endif - break; - default:/* should never happen */ - return; - } - - if (inserted) - debug("db1x00 socket %d: inserted %d, vs %d pcmcia %x\n", - skt->nr, inserted, vs, bcsr->pcmcia); - - if (inserted) { - switch (vs) { - case 0: - case 2: - state->vs_3v=1; - break; - case 3: /* 5V */ - break; - default: - /* return without setting 'detect' */ - printk(KERN_ERR "db1x00 bad VS (%d)\n", - vs); - } - state->detect = 1; - state->ready = 1; - } - else { - /* if the card was previously inserted and then ejected, - * we should turn off power to it - */ - if ((skt->nr == 0) && (bcsr->pcmcia & BCSR_PCMCIA_PC0RST)) { - bcsr->pcmcia &= ~(BCSR_PCMCIA_PC0RST | - BCSR_PCMCIA_PC0DRVEN | - BCSR_PCMCIA_PC0VPP | - BCSR_PCMCIA_PC0VCC); - au_sync_delay(10); - } - else if ((skt->nr == 1) && bcsr->pcmcia & BCSR_PCMCIA_PC1RST) { - bcsr->pcmcia &= ~(BCSR_PCMCIA_PC1RST | - BCSR_PCMCIA_PC1DRVEN | - BCSR_PCMCIA_PC1VPP | - BCSR_PCMCIA_PC1VCC); - au_sync_delay(10); - } - } - - state->bvd1=1; - state->bvd2=1; - state->wrprot=0; -} - -static int -db1x00_pcmcia_configure_socket(struct au1000_pcmcia_socket *skt, struct socket_state_t *state) -{ - u16 pwr; - int sock = skt->nr; - - debug("config_skt %d Vcc %dV Vpp %dV, reset %d\n", - sock, state->Vcc, state->Vpp, - state->flags & SS_RESET); - - /* pcmcia reg was set to zero at init time. Be careful when - * initializing a socket not to wipe out the settings of the - * other socket. - */ - pwr = bcsr->pcmcia; - pwr &= ~(0xf << sock*8); /* clear voltage settings */ - - state->Vpp = 0; - switch(state->Vcc){ - case 0: /* Vcc 0 */ - pwr |= SET_VCC_VPP(0,0,sock); - break; - case 50: /* Vcc 5V */ - switch(state->Vpp) { - case 0: - pwr |= SET_VCC_VPP(2,0,sock); - break; - case 50: - pwr |= SET_VCC_VPP(2,1,sock); - break; - case 12: - pwr |= SET_VCC_VPP(2,2,sock); - break; - case 33: - default: - pwr |= SET_VCC_VPP(0,0,sock); - printk("%s: bad Vcc/Vpp (%d:%d)\n", - __func__, - state->Vcc, - state->Vpp); - break; - } - break; - case 33: /* Vcc 3.3V */ - switch(state->Vpp) { - case 0: - pwr |= SET_VCC_VPP(1,0,sock); - break; - case 12: - pwr |= SET_VCC_VPP(1,2,sock); - break; - case 33: - pwr |= SET_VCC_VPP(1,1,sock); - break; - case 50: - default: - pwr |= SET_VCC_VPP(0,0,sock); - printk("%s: bad Vcc/Vpp (%d:%d)\n", - __func__, - state->Vcc, - state->Vpp); - break; - } - break; - default: /* what's this ? */ - pwr |= SET_VCC_VPP(0,0,sock); - printk(KERN_ERR "%s: bad Vcc %d\n", - __func__, state->Vcc); - break; - } - - bcsr->pcmcia = pwr; - au_sync_delay(300); - - if (sock == 0) { - if (!(state->flags & SS_RESET)) { - pwr |= BCSR_PCMCIA_PC0DRVEN; - bcsr->pcmcia = pwr; - au_sync_delay(300); - pwr |= BCSR_PCMCIA_PC0RST; - bcsr->pcmcia = pwr; - au_sync_delay(100); - } - else { - pwr &= ~(BCSR_PCMCIA_PC0RST | BCSR_PCMCIA_PC0DRVEN); - bcsr->pcmcia = pwr; - au_sync_delay(100); - } - } - else { - if (!(state->flags & SS_RESET)) { - pwr |= BCSR_PCMCIA_PC1DRVEN; - bcsr->pcmcia = pwr; - au_sync_delay(300); - pwr |= BCSR_PCMCIA_PC1RST; - bcsr->pcmcia = pwr; - au_sync_delay(100); - } - else { - pwr &= ~(BCSR_PCMCIA_PC1RST | BCSR_PCMCIA_PC1DRVEN); - bcsr->pcmcia = pwr; - au_sync_delay(100); - } - } - return 0; -} - -/* - * Enable card status IRQs on (re-)initialisation. This can - * be called at initialisation, power management event, or - * pcmcia event. - */ -void db1x00_socket_init(struct au1000_pcmcia_socket *skt) -{ - /* nothing to do for now */ -} - -/* - * Disable card status IRQs and PCMCIA bus on suspend. - */ -void db1x00_socket_suspend(struct au1000_pcmcia_socket *skt) -{ - /* nothing to do for now */ -} - -struct pcmcia_low_level db1x00_pcmcia_ops = { - .owner = THIS_MODULE, - - .hw_init = db1x00_pcmcia_hw_init, - .hw_shutdown = db1x00_pcmcia_shutdown, - - .socket_state = db1x00_pcmcia_socket_state, - .configure_socket = db1x00_pcmcia_configure_socket, - - .socket_init = db1x00_socket_init, - .socket_suspend = db1x00_socket_suspend -}; - -int au1x_board_init(struct device *dev) -{ - int ret = -ENODEV; - bcsr->pcmcia = 0; /* turn off power, if it's not already off */ - au_sync_delay(2); - ret = au1x00_pcmcia_socket_probe(dev, &db1x00_pcmcia_ops, 0, 2); - return ret; -} diff --git a/drivers/pcmcia/db1xxx_ss.c b/drivers/pcmcia/db1xxx_ss.c new file mode 100644 index 0000000..7e9c674 --- /dev/null +++ b/drivers/pcmcia/db1xxx_ss.c @@ -0,0 +1,700 @@ +/* + * PCMCIA socket code for the Alchemy Db1xxx/Pb1xxx boards. + * + * Copyright (c) 2009 Manuel Lauss + * + */ + +/* This is a fairly generic PCMCIA socket driver suitable for the + * following Alchemy Development boards: + * Db1000, Db/Pb1500, Db/Pb1100, Db/Pb1550, Db/Pb1200. + * + * The PB1000 is rather ... special... and not yet supported. + * + * The Db1000 is taken as a reference: Per-socket card, carddetect and + * statuschange IRQs connected to GPIOs, control and status register + * bits arranged in per-socket groups. All boards listed here use this + * layout, including bit positions and meanings, but with these + * differences: + * + * - Pb1100/Pb1500: single socket only; voltage key bits VS are + * at STATUS[5:4] (instead of STATUS[1:0]). + * - Au1550-based: control regs are at different base address. + * - Au1200-based: control regs are at different base address, + * additional card-eject irqs, irqs not gpios! + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include +#include +#include + +#include "cs_internal.h" + +#define MEM_MAP_SIZE 0x400000 +#define IO_MAP_SIZE 0x1000 + +struct db1x_pcmcia_sock { + struct pcmcia_socket socket; + int nr; /* socket number */ + void *virt_io; + + /* the "pseudo" addresses of the PCMCIA space. */ + unsigned long phys_io; + unsigned long phys_attr; + unsigned long phys_mem; + + /* previous flags for set_socket() */ + unsigned int old_flags; + + /* interrupt sources. Real linux irq numbers, NOT the GPIO pins! */ + int insert_irq; /* default carddetect irq */ + int stschg_irq; /* card-status-change irq */ + int card_irq; /* card irq */ + int eject_irq; /* db1200/pb1200 have these */ + +#define BOARD_TYPE_DEFAULT 0 /* most Db1x boards */ +#define BOARD_TYPE_DB1200 1 /* IRQs aren't gpios */ +#define BOARD_TYPE_PB1100 2 /* VS bits slightly different */ + int board_type; + + unsigned long bcsr_base; +}; + +#define to_db1x_socket(x) container_of(x, struct db1x_pcmcia_sock, socket) + +/* + * card in socket for DB1200/PB1200: Check CPLD SigStatus register; + * bits 10/12 are 1 if a card is in the socket (0/1) + */ +static int db1200_card_inserted(struct db1x_pcmcia_sock *sock) +{ + unsigned short sigstat; + + sigstat = au_readw(sock->bcsr_base + 0x30); + return sigstat & 1 << (8 + 2 * sock->nr); +} + +/* + * Check the carddetect-gpio: if it's low, then there's a card. + */ +static int db1000_card_inserted(struct db1x_pcmcia_sock *sock) +{ + return !gpio_get_value(irq_to_gpio(sock->insert_irq)); +} + +static int db1x_card_inserted(struct db1x_pcmcia_sock *sock) +{ + switch (sock->board_type) { + case BOARD_TYPE_DB1200: + return db1200_card_inserted(sock); + default: + return db1000_card_inserted(sock); + } +} + +/* STSCHG tends to bounce heavily when cards are inserted/ejected. + * To avoid this, the interrupt is normally disabled and only enabled + * after reset to a card has been de-asserted. + */ +static inline void set_stschg(struct db1x_pcmcia_sock *sock, int en) +{ + if (sock->stschg_irq != -1) { + if (en) + enable_irq(sock->stschg_irq); + else + disable_irq(sock->stschg_irq); + } +} + +static irqreturn_t db1200_pcmcia_cdirq(int irq, void *data) +{ + struct db1x_pcmcia_sock *sock = data; + + /* IRQs stay asserted as long as card is present. Stop the one + * triggering and enable the other. + */ + if (irq == sock->insert_irq) { + disable_irq_nosync(sock->insert_irq); + enable_irq(sock->eject_irq); + } else { + disable_irq_nosync(sock->eject_irq); + enable_irq(sock->insert_irq); + } + + pcmcia_parse_events(&sock->socket, SS_DETECT); + + return IRQ_HANDLED; +} + +static irqreturn_t db1000_pcmcia_cdirq(int irq, void *data) +{ + struct db1x_pcmcia_sock *sock = data; + + pcmcia_parse_events(&sock->socket, SS_DETECT); + + return IRQ_HANDLED; +} + +static irqreturn_t db1000_pcmcia_stschgirq(int irq, void *data) +{ + struct db1x_pcmcia_sock *sock = data; + + pcmcia_parse_events(&sock->socket, SS_STSCHG); + + return IRQ_HANDLED; +} + +static int db1x_pcmcia_setup_irqs(struct db1x_pcmcia_sock *sock) +{ + int ret; + unsigned long flags; + + if (sock->stschg_irq != -1) { + ret = request_irq(sock->stschg_irq, db1000_pcmcia_stschgirq, + 0, "pcmcia_stschg", sock); + if (ret) + return ret; + } + + /* Db/Pb1200 have separate per-socket insertion and ejection + * interrupts. The manual says they're supposed to be edge, but + * they show level behaviour. So kill all interrupts until both + * have been registered since one will always be triggering and + * hang the system. + */ + if (sock->board_type == BOARD_TYPE_DB1200) { + raw_local_irq_save(flags); + + ret = request_irq(sock->insert_irq, db1200_pcmcia_cdirq, + 0, "pcmcia_insert", sock); + if (ret) + goto out1; + + ret = request_irq(sock->eject_irq, db1200_pcmcia_cdirq, + 0, "pcmcia_eject", sock); + if (ret) { + free_irq(sock->insert_irq, sock); + raw_local_irq_restore(flags); + goto out1; + } + + /* disable the currently active one */ + if (db1200_card_inserted(sock)) + disable_irq_nosync(sock->insert_irq); + else + disable_irq_nosync(sock->eject_irq); + + raw_local_irq_restore(flags); + + } else { + /* all previous Db1x00 boards use a GPIO to show card + * detection status: neat for both-edge irq type. + */ + set_irq_type(sock->insert_irq, IRQ_TYPE_EDGE_BOTH); + ret = request_irq(sock->insert_irq, db1000_pcmcia_cdirq, + 0, "pcmcia_carddetect", sock); + + if (ret) + goto out1; + } + + return 0; /* all done */ + +out1: + if (sock->stschg_irq != -1) + free_irq(sock->stschg_irq, sock); + + return ret; +} + +static void db1x_pcmcia_free_irqs(struct db1x_pcmcia_sock *sock) +{ + if (sock->stschg_irq != -1) + free_irq(sock->stschg_irq, sock); + + free_irq(sock->insert_irq, sock); + if (sock->eject_irq != -1) + free_irq(sock->eject_irq, sock); +} + +/* + * configure a PCMCIA socket on the Db1x00 series of boards (and + * compatibles). + * + * 2 external registers are involved: + * pcmcia_status (offset 0x04): bits [0:1/2:3]: read card voltage id + * pcmcia_control(offset 0x10): + * bits[0:1] set vcc for card + * bits[2:3] set vpp for card + * bit 4: enable data buffers + * bit 7: reset# for card + * add 8 for second socket. + */ +static int db1x_pcmcia_configure(struct pcmcia_socket *skt, + struct socket_state_t *state) +{ + struct db1x_pcmcia_sock *sock = to_db1x_socket(skt); + unsigned short cr; + unsigned int changed; + int v, p, ret; + + /* + * card voltage setup + */ + cr = au_readw(sock->bcsr_base + 0x10); + cr &= ~(0xf << (sock->nr * 8)); /* clear voltage settings */ + v = p = ret = 0; + + switch (state->Vcc) { + case 50: ++v; + case 33: ++v; + case 0: break; + default: + printk(KERN_INFO "pcmcia%d unsupported Vcc %d\n", + sock->nr, state->Vcc); + } + + switch (state->Vpp) { + case 12: ++p; + case 33: + case 50: ++p; + case 0: break; + default: + printk(KERN_INFO "pcmcia%d unsupported Vpp %d\n", + sock->nr, state->Vpp); + } + + /* sanity check: Vpp must be 0, 12, or Vcc */ + if (((state->Vcc == 33) && (state->Vpp == 50)) || + ((state->Vcc == 50) && (state->Vpp == 33))) { + printk(KERN_INFO "pcmcia%d bad Vcc/Vpp combo (%d %d)\n", + sock->nr, state->Vcc, state->Vpp); + v = p = 0; + ret = -EINVAL; + } + + /* create new voltage code */ + cr |= ((v << 2) | p) << (sock->nr * 8); + + changed = state->flags ^ sock->old_flags; + + if (changed & SS_RESET) { + if (state->flags & SS_RESET) { + set_stschg(sock, 0); + /* assert reset, disable io buffers */ + cr &= ~(1 << (7 + (sock->nr * 8))); + cr &= ~(1 << (4 + (sock->nr * 8))); + } else { + /* de-assert reset, enable io buffers */ + cr |= 1 << (7 + (sock->nr * 8)); + cr |= 1 << (4 + (sock->nr * 8)); + } + } + + au_writew(cr, sock->bcsr_base + 0x10); + au_sync(); + + sock->old_flags = state->flags; + + /* reset was taken away: give card time to initialize properly */ + if ((changed & SS_RESET) && !(state->flags & SS_RESET)) { + msleep(500); + set_stschg(sock, 1); + } + + return ret; +} + +/* VCC bits at [3:2]/[11:10] */ +#define GET_VCC(cr, socknr) \ + ((((cr) >> 2) >> ((socknr) * 8)) & 3) + +/* VS bits at [0:1]/[3:2] */ +#define GET_VS(sr, socknr) \ + (((sr) >> (2 * (socknr))) & 3) + +/* reset bits at [7]/[15] */ +#define GET_RESET(cr, socknr) \ + ((cr) & (1 << (7 + (8 * (socknr))))) + +static int db1x_pcmcia_get_status(struct pcmcia_socket *skt, + unsigned int *value) +{ + struct db1x_pcmcia_sock *sock = to_db1x_socket(skt); + unsigned short cr, sr; + unsigned int status; + + status = db1x_card_inserted(sock) ? SS_DETECT : 0; + + cr = au_readw(sock->bcsr_base + 0x10); + sr = au_readw(sock->bcsr_base + 0x04); + + + /* PB1100/PB1500: voltage key bits are at [5:4] */ + if (sock->board_type == BOARD_TYPE_PB1100) + sr >>= 4; + + /* determine card type */ + switch (GET_VS(sr, sock->nr)) { + case 0: + case 2: + status |= SS_3VCARD; /* 3V card */ + case 3: + break; /* 5V card: set nothing */ + default: + status |= SS_XVCARD; /* treated as unsupported in core */ + } + + /* if Vcc is not zero, we have applied power to a card */ + status |= GET_VCC(cr, sock->nr) ? SS_POWERON : 0; + + /* reset de-asserted? then we're ready */ + status |= (GET_RESET(cr, sock->nr)) ? SS_READY : SS_RESET; + + *value = status; + + return 0; +} + +static int db1x_pcmcia_sock_init(struct pcmcia_socket *skt) +{ + return 0; +} + +static int db1x_pcmcia_sock_suspend(struct pcmcia_socket *skt) +{ + return 0; +} + +static int au1x00_pcmcia_set_io_map(struct pcmcia_socket *skt, + struct pccard_io_map *map) +{ + struct db1x_pcmcia_sock *sock = to_db1x_socket(skt); + + map->start = (u32)sock->virt_io; + map->stop = map->start + IO_MAP_SIZE; + + return 0; +} + +static int au1x00_pcmcia_set_mem_map(struct pcmcia_socket *skt, + struct pccard_mem_map *map) +{ + struct db1x_pcmcia_sock *sock = to_db1x_socket(skt); + + if (map->flags & MAP_ATTRIB) + map->static_start = sock->phys_attr + map->card_start; + else + map->static_start = sock->phys_mem + map->card_start; + + return 0; +} + +static struct pccard_operations db1x_pcmcia_operations = { + .init = db1x_pcmcia_sock_init, + .suspend = db1x_pcmcia_sock_suspend, + .get_status = db1x_pcmcia_get_status, + .set_socket = db1x_pcmcia_configure, + .set_io_map = au1x00_pcmcia_set_io_map, + .set_mem_map = au1x00_pcmcia_set_mem_map, +}; + +static int __devinit common_pcmcia_probe(struct platform_device *pdev, + int board_type, + unsigned long bcsr_base) +{ + struct db1x_pcmcia_sock *sock; + struct resource *r; + phys_t physio; + int ret; + + sock = kzalloc(sizeof(struct db1x_pcmcia_sock), GFP_KERNEL); + if (!sock) + return -ENOMEM; + + sock->nr = pdev->id; + sock->bcsr_base = bcsr_base; + sock->board_type = board_type; + + /* + * gather resources necessary and optional nice-to-haved to + * operate a socket. + * This includes IRQs for Carddetection/ejection, the card + * itself and optional status change detection. + * Also, the memory areas covered by a socket. For these + * we require the 32bit "pseudo" addresses (see the au1000.h + * header for more information). + */ + + /* card: irq assigned to the card itself. */ + r = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "card"); + sock->card_irq = r ? r->start : 0; + + /* insert: irq which triggers on card insertion/ejection */ + r = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "insert"); + sock->insert_irq = r ? r->start : -1; + + /* stschg: irq which trigger on card status change (optional) */ + r = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "stschg"); + sock->stschg_irq = r ? r->start : -1; + + /* eject: irq which triggers on ejection (DB1200/PB1200 only) */ + r = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "eject"); + sock->eject_irq = r ? r->start : -1; + + ret = -ENODEV; + + /* + * pseudo-attr: The 32bit address of the PCMCIA attribute space + * for this socket (usually the 36bit address shifted 4 to the + * right). + */ + r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pseudo-attr"); + if (!r) { + printk(KERN_ERR "pcmcia%d has no 'pseudo-attr' resource!\n", + sock->nr); + goto out0; + } + sock->phys_attr = r->start; + + /* + * pseudo-mem: The 32bit address of the PCMCIA memory space for + * this socket (usually the 36bit address shifted 4 to the right) + */ + r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pseudo-mem"); + if (!r) { + printk(KERN_ERR "pcmcia%d has no 'pseudo-mem' resource!\n", + sock->nr); + goto out0; + } + sock->phys_mem = r->start; + + /* + * pseudo-io: The 32bit address of the PCMCIA IO space for this + * socket (usually the 36bit address shifted 4 to the right). + */ + r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pseudo-io"); + if (!r) { + printk(KERN_ERR "pcmcia%d has no 'pseudo-io' resource!\n", + sock->nr); + goto out0; + } + sock->phys_io = r->start; + + + /* for io must remap the full 36bit address (for reference see + * alchemy/common/setup.c::__fixup_bigphys_addr) + */ + physio = ((phys_t)sock->phys_io) << 4; + + /* + * PCMCIA client drivers use the inb/outb macros to access + * the IO registers. Since mips_io_port_base is added + * to the access address of the mips implementation of + * inb/outb, we need to subtract it here because we want + * to access the I/O or MEM address directly, without + * going through this "mips_io_port_base" mechanism. + */ + sock->virt_io = (void *)(ioremap(physio, IO_MAP_SIZE) - + mips_io_port_base); + + if (!sock->virt_io) { + printk(KERN_ERR "pcmcia%d: cannot remap IO area\n", + sock->nr); + ret = -ENOMEM; + goto out0; + } + + sock->socket.ops = &db1x_pcmcia_operations; + sock->socket.owner = THIS_MODULE; + sock->socket.pci_irq = sock->card_irq; + sock->socket.features = SS_CAP_STATIC_MAP | SS_CAP_PCCARD; + sock->socket.map_size = MEM_MAP_SIZE; + sock->socket.io_offset = (unsigned long)sock->virt_io; + sock->socket.dev.parent = &pdev->dev; + sock->socket.resource_ops = &pccard_static_ops; + + platform_set_drvdata(pdev, sock); + + ret = db1x_pcmcia_setup_irqs(sock); + if (ret) { + printk(KERN_ERR "pcmcia%d cannot setup interrupts\n", + sock->nr); + goto out1; + } + + set_stschg(sock, 0); + + ret = pcmcia_register_socket(&sock->socket); + if (ret) { + printk(KERN_ERR "pcmcia%d failed to register\n", sock->nr); + goto out2; + } + + printk(KERN_INFO "Alchemy Db/Pb1xxx pcmcia%d @ io/attr/mem %08lx" + "(%p) %08lx %08lx card/insert/stschg/eject irqs @ %d " + "%d %d %d\n", sock->nr, sock->phys_io, sock->virt_io, + sock->phys_attr, sock->phys_mem, sock->card_irq, + sock->insert_irq, sock->stschg_irq, sock->eject_irq); + + return 0; + +out2: + db1x_pcmcia_free_irqs(sock); +out1: + iounmap((void *)(sock->virt_io + (u32)mips_io_port_base)); +out0: + kfree(sock); + return ret; +} + +/* Db1000, Db1500, Db1100 */ +static int __devinit db1000_pcmcia_socket_probe(struct platform_device *pdev) +{ + return common_pcmcia_probe(pdev, BOARD_TYPE_DEFAULT, 0xAE000000); +} + +/* Db1550/Pb1550: like the Db1000, only different bscr_base */ +static int __devinit pb1550_pcmcia_socket_probe(struct platform_device *pdev) +{ + return common_pcmcia_probe(pdev, BOARD_TYPE_DEFAULT, 0xAF000000); +} + +/* Pb1200/Db1200 */ +static int __devinit pb1200_pcmcia_socket_probe(struct platform_device *pdev) +{ + return common_pcmcia_probe(pdev, BOARD_TYPE_DB1200, 0xB9800000); +} + +/* Pb1100/Pb1500 */ +static int __devinit pb1100_pcmcia_socket_probe(struct platform_device *pdev) +{ + return common_pcmcia_probe(pdev, BOARD_TYPE_PB1100, 0xAE000000); +} + +static int __devexit db1x_pcmcia_socket_remove(struct platform_device *pdev) +{ + struct db1x_pcmcia_sock *sock = platform_get_drvdata(pdev); + + pcmcia_unregister_socket(&sock->socket); + db1x_pcmcia_free_irqs(sock); + iounmap((void *)(sock->virt_io + (u32)mips_io_port_base)); + kfree(sock); + + return 0; +} + +static int db1x_pcmcia_suspend(struct platform_device *pdev, + pm_message_t state) +{ + return pcmcia_socket_dev_suspend(&pdev->dev, state); +} + +static int db1x_pcmcia_resume(struct platform_device *pdev) +{ + return pcmcia_socket_dev_resume(&pdev->dev); +} + +static struct platform_driver db1x_pcmcia_socket_driver = { + .driver = { + .name = "db1x00_pcmcia", + .owner = THIS_MODULE, + }, + .probe = db1000_pcmcia_socket_probe, + .remove = __devexit_p(db1x_pcmcia_socket_remove), + .suspend = db1x_pcmcia_suspend, + .resume = db1x_pcmcia_resume, +}; + +static struct platform_driver pb1200_pcmcia_socket_driver = { + .driver = { + .name = "pb1200_pcmcia", + .owner = THIS_MODULE, + }, + .probe = pb1200_pcmcia_socket_probe, + .remove = __devexit_p(db1x_pcmcia_socket_remove), + .suspend = db1x_pcmcia_suspend, + .resume = db1x_pcmcia_resume, +}; + +static struct platform_driver pb1100_pcmcia_socket_driver = { + .driver = { + .name = "pb1100_pcmcia", + .owner = THIS_MODULE, + }, + .probe = pb1100_pcmcia_socket_probe, + .remove = __devexit_p(db1x_pcmcia_socket_remove), + .suspend = db1x_pcmcia_suspend, + .resume = db1x_pcmcia_resume, +}; + +static struct platform_driver pb1550_pcmcia_socket_driver = { + .driver = { + .name = "pb1550_pcmcia", + .owner = THIS_MODULE, + }, + .probe = pb1550_pcmcia_socket_probe, + .remove = __devexit_p(db1x_pcmcia_socket_remove), + .suspend = db1x_pcmcia_suspend, + .resume = db1x_pcmcia_resume, +}; + +int __init db1x_pcmcia_socket_load(void) +{ + int ret; + + ret = platform_driver_register(&db1x_pcmcia_socket_driver); + if (ret) + return ret; + + ret = platform_driver_register(&pb1200_pcmcia_socket_driver); + if (ret) { + platform_driver_unregister(&db1x_pcmcia_socket_driver); + return ret; + } + ret = platform_driver_register(&pb1100_pcmcia_socket_driver); + if (ret) { + platform_driver_unregister(&pb1200_pcmcia_socket_driver); + platform_driver_unregister(&db1x_pcmcia_socket_driver); + return ret; + } + ret = platform_driver_register(&pb1550_pcmcia_socket_driver); + if (ret) { + platform_driver_unregister(&pb1100_pcmcia_socket_driver); + platform_driver_unregister(&pb1200_pcmcia_socket_driver); + platform_driver_unregister(&db1x_pcmcia_socket_driver); + return ret; + } + + return ret; +} + +void __exit db1x_pcmcia_socket_unload(void) +{ + platform_driver_unregister(&db1x_pcmcia_socket_driver); + platform_driver_unregister(&pb1200_pcmcia_socket_driver); + platform_driver_unregister(&pb1100_pcmcia_socket_driver); + platform_driver_unregister(&pb1550_pcmcia_socket_driver); +} + +module_init(db1x_pcmcia_socket_load); +module_exit(db1x_pcmcia_socket_unload); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("PCMCIA Socket Services for Alchemy Db1x00 boards\n"); +MODULE_AUTHOR("Manuel Lauss"); -- 1.6.3.1 From manuel.lauss@googlemail.com Wed Jun 3 18:04:16 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 03 Jun 2009 18:04:23 +0100 (WEST) Received: from mail-bw0-f225.google.com ([209.85.218.225]:54891 "EHLO mail-bw0-f225.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20022411AbZFCRDF (ORCPT ); Wed, 3 Jun 2009 18:03:05 +0100 Received: by bwz25 with SMTP id 25so145420bwz.0 for ; Wed, 03 Jun 2009 10:02:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer:in-reply-to:references; bh=jEwyiyWr733dMBcCUvFqr99XZNSj02w2fbxgn6jSYPM=; b=NRDQhfXkSdxS39Wx0FlNBuJnAf52sVoFedv5wSu1e4EXesThLkuYVwmyU/FjuOlF/7 517XBN0nrymUr027i5p2R3CNjToP3pjhk4t8uss3Sd1MHMGheZMQgmJJOQYVhB7PxYHD NvjuRJrM5isSmVxmF3Fog2hp97l+5L2rpCMAA= DomainKey-Signature: a=rsa-sha1; c=nofws; d=googlemail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; b=n8mm/XA7BKymd9y8MLuG9tMcu9cEiD/xQlUL6jTJ/HxvevI1vB/bDCATZIqU+gqiC4 dyTx1t4X8iUwJW2Xfezjboov2lmrqkG0uELE3kb1LPBBT+isEeltmJqQR5yquUTEYnba lDyseebFrbptDLhFnAEBd7EL0ldGNS34sJmTk= Received: by 10.204.55.199 with SMTP id v7mr1069074bkg.141.1244048578844; Wed, 03 Jun 2009 10:02:58 -0700 (PDT) Received: from localhost.localdomain (p5496DB58.dip.t-dialin.net [84.150.219.88]) by mx.google.com with ESMTPS id 18sm2452543fks.10.2009.06.03.10.02.57 (version=TLSv1/SSLv3 cipher=RC4-MD5); Wed, 03 Jun 2009 10:02:58 -0700 (PDT) From: Manuel Lauss To: Linux-MIPS , Ralf Baechle Cc: Manuel Lauss Subject: [PATCH 2/5] Alchemy: get rid of allow_au1k_wait Date: Wed, 3 Jun 2009 19:02:45 +0200 Message-Id: <1244048568-18006-3-git-send-email-manuel.lauss@gmail.com> X-Mailer: git-send-email 1.6.3.1 In-Reply-To: <1244048568-18006-2-git-send-email-manuel.lauss@gmail.com> References: <1244048568-18006-1-git-send-email-manuel.lauss@gmail.com> <1244048568-18006-2-git-send-email-manuel.lauss@gmail.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23230 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips Eliminate the 'allow_au1k_wait' variable. MIPS kernel installs the Alchemy-specific wait code before timer initialization; if the C0 timer must be used for timekeeping the wait function is set to NULL which means no wait implementation is available. This also corrects the 'wait instruction available' output in cpuinfo. Run-tested on DB1200. Signed-off-by: Manuel Lauss --- arch/mips/alchemy/common/time.c | 14 ++++++++------ arch/mips/kernel/cpu-probe.c | 10 +++------- 2 files changed, 11 insertions(+), 13 deletions(-) diff --git a/arch/mips/alchemy/common/time.c b/arch/mips/alchemy/common/time.c index 33fbae7..9fc0d44 100644 --- a/arch/mips/alchemy/common/time.c +++ b/arch/mips/alchemy/common/time.c @@ -36,14 +36,13 @@ #include #include +#include #include #include /* 32kHz clock enabled and detected */ #define CNTR_OK (SYS_CNTRL_E0 | SYS_CNTRL_32S) -extern int allow_au1k_wait; /* default off for CP0 Counter */ - static cycle_t au1x_counter1_read(struct clocksource *cs) { return au_readl(SYS_RTCREAD); @@ -153,13 +152,16 @@ void __init plat_time_init(void) printk(KERN_INFO "Alchemy clocksource installed\n"); - /* can now use 'wait' */ - allow_au1k_wait = 1; return; cntr_err: - /* counters unusable, use C0 counter */ + /* MIPS kernel assigns 'au1k_wait' to 'cpu_wait' before this + * function is called. Because the Alchemy counters are unusable + * the C0 timekeeping code is installed and use of the 'wait' + * instruction must be prohibited, which is done most easily by + * assigning NULL to cpu_wait. + */ + cpu_wait = NULL; r4k_clockevent_init(); init_r4k_clocksource(); - allow_au1k_wait = 0; } diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index b13b8eb..262ea9c 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -91,15 +91,11 @@ static void rm7k_wait_irqoff(void) } /* The Au1xxx wait is available only if using 32khz counter or - * external timer source, but specifically not CP0 Counter. */ -int allow_au1k_wait; - + * external timer source, but specifically not CP0 Counter. + * alchemy/common/time.c may override cpu_wait! + */ static void au1k_wait(void) { - if (!allow_au1k_wait) - return; - - /* using the wait instruction makes CP0 counter unusable */ __asm__(" .set mips3 \n" " cache 0x14, 0(%0) \n" " cache 0x14, 32(%0) \n" -- 1.6.3.1 From manuel.lauss@googlemail.com Wed Jun 3 18:04:40 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 03 Jun 2009 18:04:47 +0100 (WEST) Received: from mail-bw0-f225.google.com ([209.85.218.225]:65035 "EHLO mail-bw0-f225.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20022404AbZFCRDG (ORCPT ); Wed, 3 Jun 2009 18:03:06 +0100 Received: by mail-bw0-f225.google.com with SMTP id 25so145388bwz.0 for ; Wed, 03 Jun 2009 10:03:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer:in-reply-to:references; bh=/tUJ4iR/EHNSaLWZjBpDeGsnBf/WoLIDxTfHggVS//0=; b=P7doxnLsZY56APjAsqv12f+x+BsBQGrSe5YZ8O1Ckg2y3LBOODcP95iRc3XEy4+FOs ES10oXFUDEB1p9Dp9mQZnGx064RHHCr05Zp33UWR/E8XCmNvp9KEqBhSqKpjuyv7bduP x2xBMQ4oISxXj3Dow0Fx88RfMGVCrHIMG9Feg= DomainKey-Signature: a=rsa-sha1; c=nofws; d=googlemail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; b=Tt+wjMFvYhbMuQYdeDqn0/+oBqyh9hiAFeVdaxhciZHP/CwAqTBwAGDndHd2Uc3TwQ FsJ3vXfjhLVcoN73ewKGzgQ5QsqIVQYRHGj0FfahKThbDdflZqqWbhaOr4GtF3DxAl3t CIrAUXXosnmQtPCXr2SIL6DGxXwGem9rgRgUU= Received: by 10.204.31.78 with SMTP id x14mr1118065bkc.3.1244048585351; Wed, 03 Jun 2009 10:03:05 -0700 (PDT) Received: from localhost.localdomain (p5496DB58.dip.t-dialin.net [84.150.219.88]) by mx.google.com with ESMTPS id 18sm2452543fks.10.2009.06.03.10.03.04 (version=TLSv1/SSLv3 cipher=RC4-MD5); Wed, 03 Jun 2009 10:03:04 -0700 (PDT) From: Manuel Lauss To: Linux-MIPS , Ralf Baechle Cc: Manuel Lauss Subject: [PATCH 5/5] Alchemy: convert to physmap flash Date: Wed, 3 Jun 2009 19:02:48 +0200 Message-Id: <1244048568-18006-6-git-send-email-manuel.lauss@gmail.com> X-Mailer: git-send-email 1.6.3.1 In-Reply-To: <1244048568-18006-5-git-send-email-manuel.lauss@gmail.com> References: <1244048568-18006-1-git-send-email-manuel.lauss@gmail.com> <1244048568-18006-2-git-send-email-manuel.lauss@gmail.com> <1244048568-18006-3-git-send-email-manuel.lauss@gmail.com> <1244048568-18006-4-git-send-email-manuel.lauss@gmail.com> <1244048568-18006-5-git-send-email-manuel.lauss@gmail.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23231 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips Add physmap-flash support to all Alchemy devboards and get rid of the alchemy-flash.c MTD map driver. Signed-off-by: Manuel Lauss --- arch/mips/alchemy/devboards/db1200/platform.c | 49 +++++++ arch/mips/alchemy/devboards/db1x00/platform.c | 77 ++++++++++++ arch/mips/alchemy/devboards/pb1000/Makefile | 3 +- arch/mips/alchemy/devboards/pb1000/platform.c | 84 +++++++++++++ arch/mips/alchemy/devboards/pb1100/platform.c | 51 ++++++++ arch/mips/alchemy/devboards/pb1200/platform.c | 50 ++++++++ arch/mips/alchemy/devboards/pb1500/platform.c | 51 ++++++++ arch/mips/alchemy/devboards/pb1550/platform.c | 51 ++++++++ drivers/mtd/maps/Kconfig | 6 - drivers/mtd/maps/Makefile | 1 - drivers/mtd/maps/alchemy-flash.c | 166 ------------------------- 11 files changed, 415 insertions(+), 174 deletions(-) create mode 100644 arch/mips/alchemy/devboards/pb1000/platform.c delete mode 100644 drivers/mtd/maps/alchemy-flash.c diff --git a/arch/mips/alchemy/devboards/db1200/platform.c b/arch/mips/alchemy/devboards/db1200/platform.c index fb63026..1da114e 100644 --- a/arch/mips/alchemy/devboards/db1200/platform.c +++ b/arch/mips/alchemy/devboards/db1200/platform.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include #include @@ -39,6 +40,10 @@ #include #include +/* NOR flash */ +#define BOARD_FLASH_SIZE 0x04000000 /* 64MB */ +#define BOARD_FLASH_WIDTH 2 /* 16-bits */ + static struct mtd_partition db1200_spiflash_parts[] = { { .name = "DB1200 SPI flash", @@ -169,6 +174,49 @@ static struct platform_device nand_dev = { } }; +static struct mtd_partition db1200_nor_partitions[] = { + { + .name = "User FS", + .size = BOARD_FLASH_SIZE - 0x00400000, + .offset = 0x0000000, + }, + { + .name = "YAMON", + .size = 0x0100000, + .offset = MTDPART_OFS_APPEND, + .mask_flags = MTD_WRITEABLE, + }, + { + .name = "raw kernel", + .size = (0x300000 - 0x40000), /* last 256KB is yamon env */ + .offset = MTDPART_OFS_APPEND, + } +}; + +static struct physmap_flash_data db1200_nor_data = { + .width = BOARD_FLASH_WIDTH, + .nr_parts = ARRAY_SIZE(db1200_nor_partitions), + .parts = &db1200_nor_partitions[0], +}; + +static struct resource db1200_nor_res[] = { + [0] = { + .start = 0x20000000 - BOARD_FLASH_SIZE, + .end = 0x1fffffff, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device db1200_nor_dev = { + .name = "physmap-flash", + .id = -1, + .dev = { + .platform_data = &db1200_nor_data, + }, + .resource = db1200_nor_res, + .num_resources = ARRAY_SIZE(db1200_nor_res), +}; + /**********************************************************************/ static struct smc91x_platdata smc_data = { @@ -526,6 +574,7 @@ static struct platform_device *db1200_devs[] __initdata = { &ide_dev, &smc91x_dev, &rtc_dev, + &db1200_nor_dev, &nand_dev, &db1200_pcmcia0_dev, &db1200_pcmcia1_dev, diff --git a/arch/mips/alchemy/devboards/db1x00/platform.c b/arch/mips/alchemy/devboards/db1x00/platform.c index 1b50b1a..e7e4243 100644 --- a/arch/mips/alchemy/devboards/db1x00/platform.c +++ b/arch/mips/alchemy/devboards/db1x00/platform.c @@ -20,6 +20,9 @@ #include #include +#include +#include +#include #include @@ -152,7 +155,81 @@ static struct platform_device db1xxx_pcmcia1_dev = { }; #endif +#ifdef CONFIG_MIPS_BOSPORUS +#define BOARD_FLASH_SIZE 0x01000000 /* 16MB */ +#define BOARD_FLASH_WIDTH 2 /* 16-bits */ +#endif + +#ifdef CONFIG_MIPS_MIRAGE +#define BOARD_FLASH_SIZE 0x04000000 /* 64MB */ +#define BOARD_FLASH_WIDTH 4 /* 32-bits */ +#endif + +#ifdef CONFIG_MIPS_DB1000 +#define BOARD_FLASH_SIZE 0x02000000 /* 32MB */ +#define BOARD_FLASH_WIDTH 4 /* 32-bits */ +#endif + +#ifdef CONFIG_MIPS_DB1500 +#define BOARD_FLASH_SIZE 0x02000000 /* 32MB */ +#define BOARD_FLASH_WIDTH 4 /* 32-bits */ +#endif + +#ifdef CONFIG_MIPS_DB1100 +#define BOARD_FLASH_SIZE 0x02000000 /* 32MB */ +#define BOARD_FLASH_WIDTH 4 /* 32-bits */ +#endif + +#ifdef CONFIG_MIPS_DB1550 +#define BOARD_FLASH_SIZE 0x08000000 /* 128MB */ +#define BOARD_FLASH_WIDTH 4 /* 32-bits */ +#endif + +static struct mtd_partition db1xxx_nor_partitions[] = { + { + .name = "User FS", + .size = BOARD_FLASH_SIZE - 0x00400000, + .offset = 0x0000000, + }, + { + .name = "YAMON", + .size = 0x0100000, + .offset = MTDPART_OFS_APPEND, + .mask_flags = MTD_WRITEABLE, + }, + { + .name = "raw kernel", + .size = (0x300000 - 0x40000), /* last 256KB is yamon env */ + .offset = MTDPART_OFS_APPEND, + } +}; + +static struct physmap_flash_data db1xxx_nor_data = { + .width = BOARD_FLASH_WIDTH, + .nr_parts = ARRAY_SIZE(db1xxx_nor_partitions), + .parts = &db1xxx_nor_partitions[0], +}; + +static struct resource db1xxx_nor_res[] = { + [0] = { + .start = 0x20000000 - BOARD_FLASH_SIZE, + .end = 0x1fffffff, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device db1xxx_nor_dev = { + .name = "physmap-flash", + .id = -1, + .dev = { + .platform_data = &db1xxx_nor_data, + }, + .resource = db1xxx_nor_res, + .num_resources = ARRAY_SIZE(db1xxx_nor_res), +}; + static struct platform_device *db1xxx_devs[] __initdata = { + &db1xxx_nor_dev, #ifdef DB1XXX_HAS_PCMCIA &db1xxx_pcmcia0_dev, &db1xxx_pcmcia1_dev, diff --git a/arch/mips/alchemy/devboards/pb1000/Makefile b/arch/mips/alchemy/devboards/pb1000/Makefile index 97c6615..ff838be 100644 --- a/arch/mips/alchemy/devboards/pb1000/Makefile +++ b/arch/mips/alchemy/devboards/pb1000/Makefile @@ -5,4 +5,5 @@ # Makefile for the Alchemy Semiconductor Pb1000 board. # -obj-y := board_setup.o +obj-y := board_setup.o platform.o + diff --git a/arch/mips/alchemy/devboards/pb1000/platform.c b/arch/mips/alchemy/devboards/pb1000/platform.c new file mode 100644 index 0000000..949982d --- /dev/null +++ b/arch/mips/alchemy/devboards/pb1000/platform.c @@ -0,0 +1,84 @@ +/* + * Pb1000 board platform device registration + * + * Copyright (C) 2009 Manuel Lauss + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include + +#include +#include + +#define PB1000_FLASH_SIZE 0x00800000 /* 8MB */ +#define PB1000_FLASH_WIDTH 4 /* 32-bits */ + +static struct mtd_partition pb1000_nor_partitions[] = { + { + .name = "User FS", + .size = PB1000_FLASH_SIZE - 0x00400000, + .offset = 0x0000000, + }, + { + .name = "YAMON", + .size = 0x0100000, + .offset = MTDPART_OFS_APPEND, + .mask_flags = MTD_WRITEABLE, + }, + { + .name = "raw kernel", + .size = (0x300000 - 0x40000), /* last 256KB is yamon env */ + .offset = MTDPART_OFS_APPEND, + } +}; + +static struct physmap_flash_data pb1000_nor_data = { + .width = PB1000_FLASH_WIDTH, + .nr_parts = ARRAY_SIZE(pb1000_nor_partitions), + .parts = &pb1000_nor_partitions[0], +}; + +static struct resource pb1000_nor_res[] = { + [0] = { + .start = 0x20000000 - PB1000_FLASH_SIZE, + .end = 0x1fffffff, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device pb1000_nor_dev = { + .name = "physmap-flash", + .id = -1, + .dev = { + .platform_data = &pb1000_nor_data, + }, + .resource = pb1000_nor_res, + .num_resources = ARRAY_SIZE(pb1000_nor_res), +}; + +static struct platform_device *pb1000_devs[] __initdata = { + &pb1000_nor_dev, +}; + +static int __init pb1000_dev_init(void) +{ + return platform_add_devices(pb1000_devs, ARRAY_SIZE(pb1000_devs)); +} +device_initcall(pb1000_dev_init); diff --git a/arch/mips/alchemy/devboards/pb1100/platform.c b/arch/mips/alchemy/devboards/pb1100/platform.c index fb52b4b..c5787fa 100644 --- a/arch/mips/alchemy/devboards/pb1100/platform.c +++ b/arch/mips/alchemy/devboards/pb1100/platform.c @@ -20,6 +20,9 @@ #include #include +#include +#include +#include #include @@ -72,7 +75,55 @@ static struct platform_device pb1100_pcmcia_dev = { .resource = pb1100_pcmcia_res, }; + +#define PB1100_FLASH_SIZE 0x04000000 /* 64MB */ +#define PB1100_FLASH_WIDTH 4 /* 32-bits */ + +static struct mtd_partition pb1100_nor_partitions[] = { + { + .name = "User FS", + .size = PB1100_FLASH_SIZE - 0x00400000, + .offset = 0x0000000, + }, + { + .name = "YAMON", + .size = 0x0100000, + .offset = MTDPART_OFS_APPEND, + .mask_flags = MTD_WRITEABLE, + }, + { + .name = "raw kernel", + .size = (0x300000 - 0x40000), /* last 256KB is yamon env */ + .offset = MTDPART_OFS_APPEND, + } +}; + +static struct physmap_flash_data pb1100_nor_data = { + .width = PB1100_FLASH_WIDTH, + .nr_parts = ARRAY_SIZE(pb1100_nor_partitions), + .parts = &pb1100_nor_partitions[0], +}; + +static struct resource pb1100_nor_res[] = { + [0] = { + .start = 0x20000000 - PB1100_FLASH_SIZE, + .end = 0x1fffffff, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device pb1100_nor_dev = { + .name = "physmap-flash", + .id = -1, + .dev = { + .platform_data = &pb1100_nor_data, + }, + .resource = pb1100_nor_res, + .num_resources = ARRAY_SIZE(pb1100_nor_res), +}; + static struct platform_device *pb1100_devs[] __initdata = { + &pb1100_nor_dev, &pb1100_pcmcia_dev, }; diff --git a/arch/mips/alchemy/devboards/pb1200/platform.c b/arch/mips/alchemy/devboards/pb1200/platform.c index c49fb10..c33b2fc 100644 --- a/arch/mips/alchemy/devboards/pb1200/platform.c +++ b/arch/mips/alchemy/devboards/pb1200/platform.c @@ -21,12 +21,18 @@ #include #include #include +#include +#include +#include #include #include #include #include +#define BOARD_FLASH_SIZE 0x08000000 /* 128MB */ +#define BOARD_FLASH_WIDTH 2 /* 16-bits */ + static int mmc_activity; static void pb1200mmc0_set_power(void *mmc_host, int state) @@ -267,9 +273,53 @@ static struct platform_device pb1200_pcmcia1_dev = { .resource = pb1200_pcmcia1_res, }; +static struct mtd_partition pb1200_nor_partitions[] = { + { + .name = "User FS", + .size = BOARD_FLASH_SIZE - 0x00400000, + .offset = 0x0000000, + }, + { + .name = "YAMON", + .size = 0x0100000, + .offset = MTDPART_OFS_APPEND, + .mask_flags = MTD_WRITEABLE, + }, + { + .name = "raw kernel", + .size = (0x300000 - 0x40000), /* last 256KB is yamon env */ + .offset = MTDPART_OFS_APPEND, + } +}; + +static struct physmap_flash_data pb1200_nor_data = { + .width = BOARD_FLASH_WIDTH, + .nr_parts = ARRAY_SIZE(pb1200_nor_partitions), + .parts = &pb1200_nor_partitions[0], +}; + +static struct resource pb1200_nor_res[] = { + [0] = { + .start = 0x20000000 - BOARD_FLASH_SIZE, + .end = 0x1fffffff, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device pb1200_nor_dev = { + .name = "physmap-flash", + .id = -1, + .dev = { + .platform_data = &pb1200_nor_data, + }, + .resource = pb1200_nor_res, + .num_resources = ARRAY_SIZE(pb1200_nor_res), +}; + static struct platform_device *board_platform_devices[] __initdata = { &ide_device, &smc91c111_device, + &pb1200_nor_dev, &pb1200_pcmcia0_dev, &pb1200_pcmcia1_dev }; diff --git a/arch/mips/alchemy/devboards/pb1500/platform.c b/arch/mips/alchemy/devboards/pb1500/platform.c index 36a4034..90c26b7 100644 --- a/arch/mips/alchemy/devboards/pb1500/platform.c +++ b/arch/mips/alchemy/devboards/pb1500/platform.c @@ -19,10 +19,17 @@ */ #include +#include +#include +#include #include #include +#define PB1500_FLASH_SIZE 0x04000000 /* 64MB */ +#define PB1500_FLASH_WIDTH 4 /* 32-bits */ + + /* PCMCIA: single socket, identical to PB1100 */ static struct resource pb1500_pcmcia_res[] = { { @@ -72,7 +79,51 @@ static struct platform_device pb1500_pcmcia_dev = { .resource = pb1500_pcmcia_res, }; +static struct mtd_partition pb1500_nor_partitions[] = { + { + .name = "User FS", + .size = PB1500_FLASH_SIZE - 0x00400000, + .offset = 0x0000000, + }, + { + .name = "YAMON", + .size = 0x0100000, + .offset = MTDPART_OFS_APPEND, + .mask_flags = MTD_WRITEABLE, + }, + { + .name = "raw kernel", + .size = (0x300000 - 0x40000), /* last 256KB is yamon env */ + .offset = MTDPART_OFS_APPEND, + } +}; + +static struct physmap_flash_data pb1500_nor_data = { + .width = PB1500_FLASH_WIDTH, + .nr_parts = ARRAY_SIZE(pb1500_nor_partitions), + .parts = &pb1500_nor_partitions[0], +}; + +static struct resource pb1500_nor_res[] = { + [0] = { + .start = 0x20000000 - PB1500_FLASH_SIZE, + .end = 0x1fffffff, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device pb1500_nor_dev = { + .name = "physmap-flash", + .id = -1, + .dev = { + .platform_data = &pb1500_nor_data, + }, + .resource = pb1500_nor_res, + .num_resources = ARRAY_SIZE(pb1500_nor_res), +}; + static struct platform_device *pb1500_devs[] __initdata = { + &pb1500_nor_dev, &pb1500_pcmcia_dev, }; diff --git a/arch/mips/alchemy/devboards/pb1550/platform.c b/arch/mips/alchemy/devboards/pb1550/platform.c index 11c91b5..9a4627c 100644 --- a/arch/mips/alchemy/devboards/pb1550/platform.c +++ b/arch/mips/alchemy/devboards/pb1550/platform.c @@ -20,11 +20,18 @@ #include #include +#include +#include +#include #include #include #include +#define PB1550_FLASH_SIZE 0x08000000 /* 128MB */ +#define PB1550_FLASH_WIDTH 4 /* 32-bits */ + + /* Pb1550, like all others, also has statuschange irqs; however they're * wired up on one of the Au1550's shared GPIO201_205 line, which also * services the PCMCIA card interrupts. So we ignore statuschange and @@ -113,7 +120,51 @@ static struct platform_device pb1550_pcmcia1_dev = { .resource = pb1550_pcmcia1_res, }; +static struct mtd_partition pb1550_nor_partitions[] = { + { + .name = "User FS", + .size = PB1550_FLASH_SIZE - 0x00400000, + .offset = 0x0000000, + }, + { + .name = "YAMON", + .size = 0x0100000, + .offset = MTDPART_OFS_APPEND, + .mask_flags = MTD_WRITEABLE, + }, + { + .name = "raw kernel", + .size = (0x300000 - 0x40000), /* last 256KB is yamon env */ + .offset = MTDPART_OFS_APPEND, + } +}; + +static struct physmap_flash_data pb1550_nor_data = { + .width = PB1550_FLASH_WIDTH, + .nr_parts = ARRAY_SIZE(pb1550_nor_partitions), + .parts = &pb1550_nor_partitions[0], +}; + +static struct resource pb1550_nor_res[] = { + [0] = { + .start = 0x20000000 - PB1550_FLASH_SIZE, + .end = 0x1fffffff, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device pb1550_nor_dev = { + .name = "physmap-flash", + .id = -1, + .dev = { + .platform_data = &pb1550_nor_data, + }, + .resource = pb1550_nor_res, + .num_resources = ARRAY_SIZE(pb1550_nor_res), +}; + static struct platform_device *board_platform_devices[] __initdata = { + &pb1550_nor_dev, &pb1550_pcmcia0_dev, &pb1550_pcmcia1_dev }; diff --git a/drivers/mtd/maps/Kconfig b/drivers/mtd/maps/Kconfig index 82923bd..118cab4 100644 --- a/drivers/mtd/maps/Kconfig +++ b/drivers/mtd/maps/Kconfig @@ -262,12 +262,6 @@ config MTD_NETtel help Support for flash chips on NETtel/SecureEdge/SnapGear boards. -config MTD_ALCHEMY - tristate "AMD Alchemy Pb1xxx/Db1xxx/RDK MTD support" - depends on SOC_AU1X00 && MTD_PARTITIONS && MTD_CFI - help - Flash memory access on AMD Alchemy Pb/Db/RDK Reference Boards - config MTD_DILNETPC tristate "CFI Flash device mapped on DIL/Net PC" depends on X86 && MTD_CONCAT && MTD_PARTITIONS && MTD_CFI_INTELEXT diff --git a/drivers/mtd/maps/Makefile b/drivers/mtd/maps/Makefile index 2dbc1be..2c846c9 100644 --- a/drivers/mtd/maps/Makefile +++ b/drivers/mtd/maps/Makefile @@ -41,7 +41,6 @@ obj-$(CONFIG_MTD_SCx200_DOCFLASH)+= scx200_docflash.o obj-$(CONFIG_MTD_DBOX2) += dbox2-flash.o obj-$(CONFIG_MTD_SOLUTIONENGINE)+= solutionengine.o obj-$(CONFIG_MTD_PCI) += pci.o -obj-$(CONFIG_MTD_ALCHEMY) += alchemy-flash.o obj-$(CONFIG_MTD_AUTCPU12) += autcpu12-nvram.o obj-$(CONFIG_MTD_EDB7312) += edb7312.o obj-$(CONFIG_MTD_IMPA7) += impa7.o diff --git a/drivers/mtd/maps/alchemy-flash.c b/drivers/mtd/maps/alchemy-flash.c deleted file mode 100644 index 845ad4f..0000000 --- a/drivers/mtd/maps/alchemy-flash.c +++ /dev/null @@ -1,166 +0,0 @@ -/* - * Flash memory access on AMD Alchemy evaluation boards - * - * (C) 2003, 2004 Pete Popov - */ - -#include -#include -#include -#include - -#include -#include -#include - -#include - -#ifdef CONFIG_MIPS_PB1000 -#define BOARD_MAP_NAME "Pb1000 Flash" -#define BOARD_FLASH_SIZE 0x00800000 /* 8MB */ -#define BOARD_FLASH_WIDTH 4 /* 32-bits */ -#endif - -#ifdef CONFIG_MIPS_PB1500 -#define BOARD_MAP_NAME "Pb1500 Flash" -#define BOARD_FLASH_SIZE 0x04000000 /* 64MB */ -#define BOARD_FLASH_WIDTH 4 /* 32-bits */ -#endif - -#ifdef CONFIG_MIPS_PB1100 -#define BOARD_MAP_NAME "Pb1100 Flash" -#define BOARD_FLASH_SIZE 0x04000000 /* 64MB */ -#define BOARD_FLASH_WIDTH 4 /* 32-bits */ -#endif - -#ifdef CONFIG_MIPS_PB1550 -#define BOARD_MAP_NAME "Pb1550 Flash" -#define BOARD_FLASH_SIZE 0x08000000 /* 128MB */ -#define BOARD_FLASH_WIDTH 4 /* 32-bits */ -#endif - -#ifdef CONFIG_MIPS_PB1200 -#define BOARD_MAP_NAME "Pb1200 Flash" -#define BOARD_FLASH_SIZE 0x08000000 /* 128MB */ -#define BOARD_FLASH_WIDTH 2 /* 16-bits */ -#endif - -#ifdef CONFIG_MIPS_DB1000 -#define BOARD_MAP_NAME "Db1000 Flash" -#define BOARD_FLASH_SIZE 0x02000000 /* 32MB */ -#define BOARD_FLASH_WIDTH 4 /* 32-bits */ -#endif - -#ifdef CONFIG_MIPS_DB1500 -#define BOARD_MAP_NAME "Db1500 Flash" -#define BOARD_FLASH_SIZE 0x02000000 /* 32MB */ -#define BOARD_FLASH_WIDTH 4 /* 32-bits */ -#endif - -#ifdef CONFIG_MIPS_DB1100 -#define BOARD_MAP_NAME "Db1100 Flash" -#define BOARD_FLASH_SIZE 0x02000000 /* 32MB */ -#define BOARD_FLASH_WIDTH 4 /* 32-bits */ -#endif - -#ifdef CONFIG_MIPS_DB1550 -#define BOARD_MAP_NAME "Db1550 Flash" -#define BOARD_FLASH_SIZE 0x08000000 /* 128MB */ -#define BOARD_FLASH_WIDTH 4 /* 32-bits */ -#endif - -#ifdef CONFIG_MIPS_DB1200 -#define BOARD_MAP_NAME "Db1200 Flash" -#define BOARD_FLASH_SIZE 0x04000000 /* 64MB */ -#define BOARD_FLASH_WIDTH 2 /* 16-bits */ -#endif - -#ifdef CONFIG_MIPS_BOSPORUS -#define BOARD_MAP_NAME "Bosporus Flash" -#define BOARD_FLASH_SIZE 0x01000000 /* 16MB */ -#define BOARD_FLASH_WIDTH 2 /* 16-bits */ -#endif - -#ifdef CONFIG_MIPS_MIRAGE -#define BOARD_MAP_NAME "Mirage Flash" -#define BOARD_FLASH_SIZE 0x04000000 /* 64MB */ -#define BOARD_FLASH_WIDTH 4 /* 32-bits */ -#define USE_LOCAL_ACCESSORS /* why? */ -#endif - -static struct map_info alchemy_map = { - .name = BOARD_MAP_NAME, -}; - -static struct mtd_partition alchemy_partitions[] = { - { - .name = "User FS", - .size = BOARD_FLASH_SIZE - 0x00400000, - .offset = 0x0000000 - },{ - .name = "YAMON", - .size = 0x0100000, - .offset = MTDPART_OFS_APPEND, - .mask_flags = MTD_WRITEABLE - },{ - .name = "raw kernel", - .size = (0x300000 - 0x40000), /* last 256KB is yamon env */ - .offset = MTDPART_OFS_APPEND, - } -}; - -static struct mtd_info *mymtd; - -static int __init alchemy_mtd_init(void) -{ - struct mtd_partition *parts; - int nb_parts = 0; - unsigned long window_addr; - unsigned long window_size; - - /* Default flash buswidth */ - alchemy_map.bankwidth = BOARD_FLASH_WIDTH; - - window_addr = 0x20000000 - BOARD_FLASH_SIZE; - window_size = BOARD_FLASH_SIZE; - - /* - * Static partition definition selection - */ - parts = alchemy_partitions; - nb_parts = ARRAY_SIZE(alchemy_partitions); - alchemy_map.size = window_size; - - /* - * Now let's probe for the actual flash. Do it here since - * specific machine settings might have been set above. - */ - printk(KERN_NOTICE BOARD_MAP_NAME ": probing %d-bit flash bus\n", - alchemy_map.bankwidth*8); - alchemy_map.virt = ioremap(window_addr, window_size); - mymtd = do_map_probe("cfi_probe", &alchemy_map); - if (!mymtd) { - iounmap(alchemy_map.virt); - return -ENXIO; - } - mymtd->owner = THIS_MODULE; - - add_mtd_partitions(mymtd, parts, nb_parts); - return 0; -} - -static void __exit alchemy_mtd_cleanup(void) -{ - if (mymtd) { - del_mtd_partitions(mymtd); - map_destroy(mymtd); - iounmap(alchemy_map.virt); - } -} - -module_init(alchemy_mtd_init); -module_exit(alchemy_mtd_cleanup); - -MODULE_AUTHOR("Embedded Alley Solutions, Inc"); -MODULE_DESCRIPTION(BOARD_MAP_NAME " MTD driver"); -MODULE_LICENSE("GPL"); -- 1.6.3.1 From manuel.lauss@googlemail.com Wed Jun 3 18:05:04 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 03 Jun 2009 18:05:12 +0100 (WEST) Received: from mail-bw0-f225.google.com ([209.85.218.225]:56059 "EHLO mail-bw0-f225.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20022417AbZFCRDI (ORCPT ); Wed, 3 Jun 2009 18:03:08 +0100 Received: by bwz25 with SMTP id 25so145444bwz.0 for ; Wed, 03 Jun 2009 10:03:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer:in-reply-to:references; bh=cTfxWDJTpmdotc49If9x1+O9TlD/zOA/YYYSw+fqpPM=; b=wYg90osvTHdXRPrTKex8Sk1YSitJKFfdoxR5Q3qeoRKsvzF3yiki7YcJ2kwP0PABRF BbHwpZNlWhX+9a1+J31Ei0JCDhgwZYWe9DFtgU6zck5e92Mc8NOsWlIL4hD6yUyNqv7r fZOEi+Q2LF2XxF2z9Y2cHPcY7wb9rMG17V9as= DomainKey-Signature: a=rsa-sha1; c=nofws; d=googlemail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; b=e9VpXt7Lzs4bcKtCvbNhdTHOGZ/lw0yF9iRo579fT0v59/PuKIaiO4VbjWL50vIDgF XOjbGOWAsiNYEOWVkIc3XOYj1+vqirH8/l/+/kwbR9bmb1uxHwBhrK36MaLymEJkOKjB QSrkbPnQwHDzh9GqjRoGgbzdmmE6RTnOwYsAk= Received: by 10.204.121.131 with SMTP id h3mr1067696bkr.172.1244048581713; Wed, 03 Jun 2009 10:03:01 -0700 (PDT) Received: from localhost.localdomain (p5496DB58.dip.t-dialin.net [84.150.219.88]) by mx.google.com with ESMTPS id 18sm2452543fks.10.2009.06.03.10.02.58 (version=TLSv1/SSLv3 cipher=RC4-MD5); Wed, 03 Jun 2009 10:03:00 -0700 (PDT) From: Manuel Lauss To: Linux-MIPS , Ralf Baechle Cc: Manuel Lauss Subject: [PATCH 3/5] Alchemy: extended DB1200 board support. Date: Wed, 3 Jun 2009 19:02:46 +0200 Message-Id: <1244048568-18006-4-git-send-email-manuel.lauss@gmail.com> X-Mailer: git-send-email 1.6.3.1 In-Reply-To: <1244048568-18006-3-git-send-email-manuel.lauss@gmail.com> References: <1244048568-18006-1-git-send-email-manuel.lauss@gmail.com> <1244048568-18006-2-git-send-email-manuel.lauss@gmail.com> <1244048568-18006-3-git-send-email-manuel.lauss@gmail.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23232 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: manuel.lauss@googlemail.com Precedence: bulk X-list: linux-mips Create own directory for DB1200 code and update it with new features. - SPI support - tmp121 temperature sensor - SPI flash on DB1200 (untested, mine doesn't have this chip) - I2C support - NE1619 sensor - AT24 eeprom - Audio AC97 and I2S (I2S requires I2C) - I2C/SPI and AC97/I2S can be selected at boot time via switches S6.8 and S6.7 - Carddetect IRQs for SD cards. - gen_nand based NAND support. - hexleds count sleep/wake transitions - defconfig update Signed-off-by: Manuel Lauss --- arch/mips/alchemy/common/reset.c | 3 - arch/mips/alchemy/devboards/Makefile | 2 +- arch/mips/alchemy/devboards/db1200/Makefile | 1 + arch/mips/alchemy/devboards/db1200/platform.c | 505 +++++++ arch/mips/alchemy/devboards/db1200/setup.c | 181 +++ arch/mips/alchemy/devboards/pb1200/board_setup.c | 5 - arch/mips/alchemy/devboards/pb1200/irqmap.c | 19 +- arch/mips/alchemy/devboards/pb1200/platform.c | 4 - arch/mips/configs/db1200_defconfig | 1629 +++++++++++++--------- arch/mips/include/asm/mach-db1x00/db1200.h | 23 +- sound/soc/au1x/Kconfig | 10 +- sound/soc/au1x/Makefile | 4 +- sound/soc/au1x/db1200.c | 189 +++ sound/soc/au1x/sample-ac97.c | 144 -- 14 files changed, 1887 insertions(+), 832 deletions(-) create mode 100644 arch/mips/alchemy/devboards/db1200/Makefile create mode 100644 arch/mips/alchemy/devboards/db1200/platform.c create mode 100644 arch/mips/alchemy/devboards/db1200/setup.c create mode 100644 sound/soc/au1x/db1200.c delete mode 100644 sound/soc/au1x/sample-ac97.c diff --git a/arch/mips/alchemy/common/reset.c b/arch/mips/alchemy/common/reset.c index 0ec33dc..e985068 100644 --- a/arch/mips/alchemy/common/reset.c +++ b/arch/mips/alchemy/common/reset.c @@ -164,9 +164,6 @@ void au1000_halt(void) #ifdef CONFIG_MIPS_MIRAGE gpio_direction_output(10, 1); #endif -#ifdef CONFIG_MIPS_DB1200 - au_writew(au_readw(0xB980001C) | (1 << 14), 0xB980001C); -#endif #ifdef CONFIG_PM au_sleep(); diff --git a/arch/mips/alchemy/devboards/Makefile b/arch/mips/alchemy/devboards/Makefile index 730f9f2..ed2bd04 100644 --- a/arch/mips/alchemy/devboards/Makefile +++ b/arch/mips/alchemy/devboards/Makefile @@ -11,7 +11,7 @@ obj-$(CONFIG_MIPS_PB1500) += pb1500/ obj-$(CONFIG_MIPS_PB1550) += pb1550/ obj-$(CONFIG_MIPS_DB1000) += db1x00/ obj-$(CONFIG_MIPS_DB1100) += db1x00/ -obj-$(CONFIG_MIPS_DB1200) += pb1200/ +obj-$(CONFIG_MIPS_DB1200) += db1200/ obj-$(CONFIG_MIPS_DB1500) += db1x00/ obj-$(CONFIG_MIPS_DB1550) += db1x00/ obj-$(CONFIG_MIPS_BOSPORUS) += db1x00/ diff --git a/arch/mips/alchemy/devboards/db1200/Makefile b/arch/mips/alchemy/devboards/db1200/Makefile new file mode 100644 index 0000000..17840a5 --- /dev/null +++ b/arch/mips/alchemy/devboards/db1200/Makefile @@ -0,0 +1 @@ +obj-y += setup.o platform.o diff --git a/arch/mips/alchemy/devboards/db1200/platform.c b/arch/mips/alchemy/devboards/db1200/platform.c new file mode 100644 index 0000000..b3142e0 --- /dev/null +++ b/arch/mips/alchemy/devboards/db1200/platform.c @@ -0,0 +1,505 @@ +/* + * DBAu1200 board platform device registration + * + * Copyright (C) 2008-2009 Manuel Lauss + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +static struct mtd_partition db1200_spiflash_parts[] = { + { + .name = "DB1200 SPI flash", + .offset = 0, + .size = MTDPART_SIZ_FULL, + }, +}; + +static struct flash_platform_data db1200_spiflash_data = { + .name = "s25fl001", + .parts = db1200_spiflash_parts, + .nr_parts = ARRAY_SIZE(db1200_spiflash_parts), + .type = "m25p10", +}; + +static struct spi_board_info db1200_spi_devs[] __initdata = { + { + /* TI TMP121AIDBVR temp sensor */ + .modalias = "tmp121", + .max_speed_hz = 2000000, + .bus_num = 0, + .chip_select = 0, + .mode = 0, + }, + { + /* Spansion S25FL001D0FMA SPI flash */ + .modalias = "m25p80", + .max_speed_hz = 50000000, + .bus_num = 0, + .chip_select = 1, + .mode = 0, + .platform_data = &db1200_spiflash_data, + }, +}; + +static struct i2c_board_info db1200_i2c_devs[] __initdata = { + { + /* AT24C04-10 I2C eeprom */ + I2C_BOARD_INFO("24c04", 0x52), + }, + { + /* Philips NE1619 temp/voltage sensor (adm1025 drv) */ + I2C_BOARD_INFO("ne1619", 0x2d), + }, + { + /* I2S audio codec WM8731 */ + I2C_BOARD_INFO("wm8731", 0x1b), + }, +}; + +/**********************************************************************/ + +static void au1200_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, + unsigned int ctrl) +{ + struct nand_chip *this = mtd->priv; + unsigned long ioaddr = (unsigned long)this->IO_ADDR_W; + + ioaddr &= 0xffffff00; + + if (ctrl & NAND_CLE) { + ioaddr += MEM_STNAND_CMD; + } else if (ctrl & NAND_ALE) { + ioaddr += MEM_STNAND_ADDR; + } else { + /* assume we want to r/w real data by default */ + ioaddr += MEM_STNAND_DATA; + } + this->IO_ADDR_R = this->IO_ADDR_W = (void __iomem *)ioaddr; + if (cmd != NAND_CMD_NONE) { + au_writeb(cmd, ioaddr); + au_sync(); + } +} + +static int au1200_nand_device_ready(struct mtd_info *mtd) +{ + return au_readl(MEM_STSTAT) & 1; +} + +static const char *db1200_part_probes[] = { "cmdlinepart", NULL }; + +static struct mtd_partition db1200_nand_parts[] = { + { + .name = "NAND FS 0", + .offset = 0, + .size = 8 * 1024 * 1024, + }, + { + .name = "NAND FS 1", + .offset = MTDPART_OFS_APPEND, + .size = MTDPART_SIZ_FULL + }, +}; + +struct platform_nand_data db1200_nand_platdata = { + .chip = { + .nr_chips = 1, + .chip_offset = 0, + .nr_partitions = ARRAY_SIZE(db1200_nand_parts), + .partitions = db1200_nand_parts, + .chip_delay = 20, + .part_probe_types = db1200_part_probes, + }, + .ctrl = { + .hwcontrol = 0, + .dev_ready = au1200_nand_device_ready, + .select_chip = 0, + .cmd_ctrl = au1200_nand_cmd_ctrl, + }, +}; + +static struct resource db1200_nand_res[] = { + [0] = { + .start = 0x20000000, + .end = 0x200000ff, + .flags = IORESOURCE_MEM, + }, +}; + +static struct platform_device nand_dev = { + .name = "gen_nand", + .num_resources = ARRAY_SIZE(db1200_nand_res), + .resource = db1200_nand_res, + .id = -1, + .dev = { + .platform_data = &db1200_nand_platdata, + } +}; + +/**********************************************************************/ + +static struct smc91x_platdata smc_data = { + .flags = SMC91X_NOWAIT | SMC91X_USE_16BIT, + .leda = RPC_LED_100_10, + .ledb = RPC_LED_TX_RX, +}; + +static struct resource smc91x_res[] = { + [0] = { + .start = SMC91C111_PHYS_ADDR, + .end = SMC91C111_PHYS_ADDR + 0xf, + .flags = IORESOURCE_MEM + }, + [1] = { + .start = SMC91C111_INT, + .end = SMC91C111_INT, + .flags = IORESOURCE_IRQ + }, +}; + +static struct platform_device smc91x_dev = { + .dev = { + .platform_data = &smc_data, + }, + .name = "smc91x", + .id = -1, + .num_resources = ARRAY_SIZE(smc91x_res), + .resource = smc91x_res +}; + +/**********************************************************************/ + +static struct resource ide_resources[] = { + [0] = { + .start = IDE_PHYS_ADDR, + .end = IDE_PHYS_ADDR + IDE_PHYS_LEN - 1, + .flags = IORESOURCE_MEM + }, + [1] = { + .start = IDE_INT, + .end = IDE_INT, + .flags = IORESOURCE_IRQ + } +}; + +static u64 ide_dmamask = DMA_32BIT_MASK; + +static struct platform_device ide_dev = { + .name = "au1200-ide", + .id = 0, + .dev = { + .dma_mask = &ide_dmamask, + .coherent_dma_mask = DMA_32BIT_MASK, + }, + .num_resources = ARRAY_SIZE(ide_resources), + .resource = ide_resources +}; + +/**********************************************************************/ + +static struct platform_device rtc_dev = { + .name = "rtc-au1xxx", + .id = -1, +}; + +/**********************************************************************/ + +/* SD Carddetect irqs. Although the manual says they're supposed to be + * edge, they stay asserted as long as the card is inserted/removed, + * regardless of how many times the bit gets acked. So depending on + * which IRQ has triggered, one gets masked and the other unmasked. + */ +static irqreturn_t db1200_mmc_cd(int irq, void *ptr) +{ + void(*mmc_cd)(struct mmc_host *, unsigned long); + + if (irq == DB1200_SD0_INSERT_INT) { + disable_irq_nosync(DB1200_SD0_INSERT_INT); + enable_irq(DB1200_SD0_EJECT_INT); + } else { + disable_irq_nosync(DB1200_SD0_EJECT_INT); + enable_irq(DB1200_SD0_INSERT_INT); + } + + /* account for modular mmc_core, to avoid link errors */ + mmc_cd = symbol_get(mmc_detect_change); + if (mmc_cd) { + mmc_cd(ptr, msecs_to_jiffies(500)); + symbol_put(mmc_detect_change); + } + return IRQ_HANDLED; +} + +static int db1200_mmc_cd_setup(void *mmc_host, int en) +{ + unsigned long flags; + int ret; + + /* kill irqs until both handlers have been registered, since one + * will always trigger immediately and leave nasty warnings in + * the kernel log. + */ + raw_local_irq_save(flags); + if (en) { + ret = request_irq(DB1200_SD0_INSERT_INT, db1200_mmc_cd, + IRQF_DISABLED, "sd_insert", mmc_host); + if (ret) + goto out; + + ret = request_irq(DB1200_SD0_EJECT_INT, db1200_mmc_cd, + IRQF_DISABLED, "sd_eject", mmc_host); + if (ret) { + free_irq(DB1200_SD0_INSERT_INT, mmc_host); + goto out; + } + + /* disable the one which is currently triggering; + * the MMC layer will detect the card anyway. + */ + if (bcsr->sig_status & BCSR_INT_SD0INSERT) + disable_irq_nosync(DB1200_SD0_INSERT_INT); + else + disable_irq_nosync(DB1200_SD0_EJECT_INT); + + } else { + free_irq(DB1200_SD0_INSERT_INT, mmc_host); + free_irq(DB1200_SD0_EJECT_INT, mmc_host); + } + ret = 0; +out: + raw_local_irq_restore(flags); + return ret; +} + +static void db1200_mmc_set_power(void *mmc_host, int state) +{ + if (state) + bcsr->board |= BCSR_BOARD_SD0PWR; + else + bcsr->board &= ~BCSR_BOARD_SD0PWR; + + au_sync(); + if (state) + msleep(400); /* give card time to initialize */ +} + +static int db1200_mmc_card_readonly(void *mmc_host) +{ + return (bcsr->status & BCSR_STATUS_SD0WP) ? 1 : 0; +} + +static int db1200_mmc_card_inserted(void *mmc_host) +{ + return (bcsr->sig_status & BCSR_INT_SD0INSERT) ? 1 : 0; +} + +static void db1200_mmcled_set(struct led_classdev *led, + enum led_brightness brightness) +{ + if (brightness != LED_OFF) + bcsr->disk_leds &= ~(1 << 8); + else + bcsr->disk_leds |= (1 << 8); +} + +static struct led_classdev db1200_mmc_led = { + .brightness_set = db1200_mmcled_set, +}; + +/* needed by arch/mips/alchemy/common/platform.c */ +struct au1xmmc_platform_data au1xmmc_platdata[] = { + [0] = { + .cd_setup = db1200_mmc_cd_setup, + .set_power = db1200_mmc_set_power, + .card_inserted = db1200_mmc_card_inserted, + .card_readonly = db1200_mmc_card_readonly, + .led = &db1200_mmc_led, + }, +}; + +/**********************************************************************/ + +static struct resource psc0_res[] = { + [0] = { + .start = CPHYSADDR(PSC0_BASE_ADDR), + .end = CPHYSADDR(PSC0_BASE_ADDR) + 0x000fffff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AU1200_PSC0_INT, + .end = AU1200_PSC0_INT, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = DSCR_CMD0_PSC0_TX, + .end = DSCR_CMD0_PSC0_TX, + .flags = IORESOURCE_DMA, + }, + [3] = { + .start = DSCR_CMD0_PSC0_RX, + .end = DSCR_CMD0_PSC0_RX, + .flags = IORESOURCE_DMA, + }, +}; + +static struct platform_device i2c_dev = { + .name = "au1xpsc_smbus", + .id = 0, /* bus number */ + .num_resources = ARRAY_SIZE(psc0_res), + .resource = psc0_res, +}; + +static void db1200_spi_cs_en(struct au1550_spi_info *spi, int cs, int pol) +{ + if (cs) + bcsr->resets |= BCSR_RESETS_SPISEL; + else + bcsr->resets &= ~BCSR_RESETS_SPISEL; +} + +static struct au1550_spi_info db1200_spi_platdata = { + .mainclk_hz = 50000000, /* PSC0 clock */ + .num_chipselect = 2, + .activate_cs = db1200_spi_cs_en, +}; + +static u64 spi_dmamask = DMA_32BIT_MASK; + +static struct platform_device spi_dev = { + .dev = { + .dma_mask = &spi_dmamask, + .coherent_dma_mask = DMA_32BIT_MASK, + .platform_data = &db1200_spi_platdata, + }, + .name = "au1550-spi", + .id = 0, /* bus number */ + .num_resources = ARRAY_SIZE(psc0_res), + .resource = psc0_res, +}; + +static struct platform_device *db1200_devs[] __initdata = { + NULL, /* PSC0, selected by S6.8 */ + &ide_dev, + &smc91x_dev, + &rtc_dev, + &nand_dev, +}; + +static int __init db1200_dev_init(void) +{ + unsigned long pfc; + + i2c_register_board_info(0, db1200_i2c_devs, + ARRAY_SIZE(db1200_i2c_devs)); + spi_register_board_info(db1200_spi_devs, + ARRAY_SIZE(db1200_i2c_devs)); + + /* SWITCHES: S6.8 I2C/SPI selector (OFF=I2C ON=SPI) + * S6.7 AC97/I2S selector (OFF=AC97 ON=I2S) + */ + + /* NOTE: GPIO215 controls OTG VBUS supply. In SPI mode however + * this pin is claimed by PSC0 (unused though, but pinmux doesn't + * allow to free it without crippling the SPI interface). + * As a result, in SPI mode, OTG simply won't work (PSC0 uses + * it as an input pin which is pulled high on the boards). + */ + pfc = au_readl(SYS_PINFUNC) & ~SYS_PINFUNC_P0A; + + /* switch off OTG VBUS supply */ +#ifdef CONFIG_GPIOLIB + gpio_request(215, "otg-vbus"); +#endif + gpio_direction_output(215, 1); + + printk(KERN_INFO "DB1200 device configuration:\n"); + + if (bcsr->switches & BCSR_SWITCHES_DIP_8) { + db1200_devs[0] = &i2c_dev; + bcsr->resets &= ~BCSR_RESETS_PSC0MUX; + + pfc |= (2 << 17); /* GPIO2 block owns GPIO215 */ + + printk(KERN_INFO " S6.8 OFF: PSC0 mode I2C\n"); + printk(KERN_INFO " OTG port VBUS supply available!\n"); + } else { + db1200_devs[0] = &spi_dev; + bcsr->resets |= BCSR_RESETS_PSC0MUX; + + pfc |= (1 << 17); /* PSC0 owns GPIO215 */ + + printk(KERN_INFO " S6.8 ON : PSC0 mode SPI\n"); + printk(KERN_INFO " OTG port VBUS supply disabled\n"); + } + au_writel(pfc, SYS_PINFUNC); + au_sync(); + + /* audio is handled in sound/soc/au1x/db1200.c; + * however we need I2C to talk to I2S codec. + */ + if ((bcsr->switches & 3) == BCSR_SWITCHES_DIP_8) { + bcsr->resets |= BCSR_RESETS_PSC1MUX; + printk(KERN_INFO " S6.7 ON : PSC1 mode I2S\n"); + } else { + bcsr->resets &= ~BCSR_RESETS_PSC1MUX; + printk(KERN_INFO " S6.7 OFF: PSC1 mode AC97\n"); + } + + return platform_add_devices(db1200_devs, ARRAY_SIZE(db1200_devs)); +} +device_initcall(db1200_dev_init); + +/* au1200fb calls these */ +int board_au1200fb_panel(void) +{ + return ((bcsr->switches) >> 8) & 0xf; /* rotary switch */ +} + +int board_au1200fb_panel_init(void) +{ + /* Apply power */ + bcsr->board |= BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD | + BCSR_BOARD_LCDBL; + return 0; +} + +int board_au1200fb_panel_shutdown(void) +{ + /* Remove power */ + bcsr->board &= ~(BCSR_BOARD_LCDVEE | BCSR_BOARD_LCDVDD | + BCSR_BOARD_LCDBL); + return 0; +} diff --git a/arch/mips/alchemy/devboards/db1200/setup.c b/arch/mips/alchemy/devboards/db1200/setup.c new file mode 100644 index 0000000..422b703 --- /dev/null +++ b/arch/mips/alchemy/devboards/db1200/setup.c @@ -0,0 +1,181 @@ +/* + * Alchemy/AMD/RMI DB1200 board setup. + * + * Licensed under the terms outlined in the file COPYING in the root of + * this source archive. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +static void db1200_irq_cascade(unsigned int irq, struct irq_desc *desc) +{ + unsigned short bisr = bcsr->int_status; + + while (bisr) { + generic_handle_irq(DB1200_INT_BEGIN + __ffs(bisr)); + bisr &= bisr - 1; + } +} + +/* both the enable (intset) and mask (inset_mask) bits must be modified, + * otherwise the CPLD triggers tons of spurious interrupts. + */ +static void db1200_mask_irq(unsigned int irq_nr) +{ + bcsr->intclr_mask = 1 << (irq_nr - DB1200_INT_BEGIN); + bcsr->intclr = 1 << (irq_nr - DB1200_INT_BEGIN); + au_sync(); +} + +static void db1200_maskack_irq(unsigned int irq_nr) +{ + bcsr->intclr_mask = 1 << (irq_nr - DB1200_INT_BEGIN); + bcsr->intclr = 1 << (irq_nr - DB1200_INT_BEGIN); + bcsr->int_status = 1 << (irq_nr - DB1200_INT_BEGIN); /* ack */ + au_sync(); +} + +static void db1200_unmask_irq(unsigned int irq_nr) +{ + bcsr->intset = 1 << (irq_nr - DB1200_INT_BEGIN); + bcsr->intset_mask = 1 << (irq_nr - DB1200_INT_BEGIN); + au_sync(); +} + +static struct irq_chip db1200_cpld_irq = { + .name = "DB1200-CPLD", + .mask = db1200_mask_irq, + .mask_ack = db1200_maskack_irq, + .unmask = db1200_unmask_irq, +}; + +void __init board_init_irq(void) +{ + unsigned int i; + + /* mask & disable & ack all */ + bcsr->intclr_mask = 0xffff; + bcsr->intclr = 0xffff; + bcsr->int_status = 0xffff; + au_sync(); + + for (i = DB1200_INT_BEGIN; i <= DB1200_INT_END; i++) + set_irq_chip_and_handler_name(i, &db1200_cpld_irq, + handle_level_irq, "level"); + + /* GPIO7 is low-level triggered CPLD cascade */ + set_irq_type(AU1000_GPIO_7, IRQF_TRIGGER_LOW); + set_irq_chained_handler(AU1000_GPIO_7, db1200_irq_cascade); +} + +const char *get_system_type(void) +{ + return "Alchemy Db1200"; +} + +static void board_power_off(void) +{ + bcsr->resets = 0; + bcsr->system = BCSR_SYSTEM_POWEROFF | BCSR_SYSTEM_RESET; +} + +void board_reset(void) +{ + bcsr->resets = 0; + bcsr->system = 0; +} + +void __init board_setup(void) +{ + u32 freq0, clksrc, div; + u32 pfc; + + printk(KERN_INFO "Alchemy/AMD/RMI DB1200 Board, CPLD Rev %d" + " Board-ID %d Daughtercard ID %d\n", + (bcsr->whoami >> 4) & 0xf, (bcsr->whoami >> 8) & 0xf, + bcsr->whoami & 0xf); + + /* SMBus/SPI on PSC0, Audio on PSC1 */ + pfc = au_readl(SYS_PINFUNC); + pfc &= ~(SYS_PINFUNC_P0A | SYS_PINFUNC_P0B); + pfc &= ~(SYS_PINFUNC_P1A | SYS_PINFUNC_P1B | SYS_PINFUNC_FS3); + pfc |= SYS_PINFUNC_P1C; /* SPI is configured later */ + au_writel(pfc, SYS_PINFUNC); + au_sync(); + + /* Clock configurations: PSC0: ~50MHz via Clkgen0, derived from + * CPU clock; all other clock generators off/unused. + */ + div = (get_au1x00_speed() + 25000000) / 50000000; + if (div & 1) + div++; + div = ((div >> 1) - 1) & 0xff; + + freq0 = div << SYS_FC_FRDIV0_BIT; + au_writel(freq0, SYS_FREQCTRL0); + au_sync(); + freq0 |= SYS_FC_FE0; /* enable F0 */ + au_writel(freq0, SYS_FREQCTRL0); + au_sync(); + + /* psc0_intclk comes 1:1 from F0 */ + clksrc = SYS_CS_MUX_FQ0 << SYS_CS_ME0_BIT; + au_writel(clksrc, SYS_CLKSRC); + au_sync(); + + pm_power_off = board_power_off; + _machine_halt = board_power_off; + _machine_restart = (void(*)(char *))board_reset; +} + +/* use the hexleds to count the number of times the cpu has entered + * wait, the dots to indicate whether the CPU is currently idle or + * active (dots off = sleeping, dots on = working) for cases where + * the number doesn't change for a long(er) period of time. + */ +static void db1200_wait(void) +{ + __asm__(" .set push \n" + " .set mips3 \n" + " .set noreorder \n" + " cache 0x14, 0(%0) \n" + " cache 0x14, 32(%0) \n" + " cache 0x14, 64(%0) \n" + /* dots off: we're about to call wait */ + " lui $26, 0xb980 \n" + " ori $27, $0, 3 \n" + " sb $27, 0x18($26) \n" + " sync \n" + " nop \n" + " wait \n" + " nop \n" + " nop \n" + " nop \n" + " nop \n" + " nop \n" + /* dots on: there's work to do, increment cntr */ + " lui $26, 0xb980 \n" + " sb $0, 0x18($26) \n" + " lui $26, 0xb9c0 \n" + " lb $27, 0($26) \n" + " addiu $27, $27, 1 \n" + " sb $27, 0($26) \n" + " sync \n" + " .set pop \n" + : : "r" (db1200_wait)); +} + +static int __init db1200_wait_init(void) +{ + if (cpu_wait) + cpu_wait = db1200_wait; + return 0; +} +arch_initcall(db1200_wait_init); diff --git a/arch/mips/alchemy/devboards/pb1200/board_setup.c b/arch/mips/alchemy/devboards/pb1200/board_setup.c index 94e6b7e..2829f45 100644 --- a/arch/mips/alchemy/devboards/pb1200/board_setup.c +++ b/arch/mips/alchemy/devboards/pb1200/board_setup.c @@ -123,12 +123,7 @@ void __init board_setup(void) #endif au_sync(); -#ifdef CONFIG_MIPS_PB1200 printk(KERN_INFO "AMD Alchemy Pb1200 Board\n"); -#endif -#ifdef CONFIG_MIPS_DB1200 - printk(KERN_INFO "AMD Alchemy Db1200 Board\n"); -#endif } int board_au1200fb_panel(void) diff --git a/arch/mips/alchemy/devboards/pb1200/irqmap.c b/arch/mips/alchemy/devboards/pb1200/irqmap.c index fe47498..453e18b 100644 --- a/arch/mips/alchemy/devboards/pb1200/irqmap.c +++ b/arch/mips/alchemy/devboards/pb1200/irqmap.c @@ -27,16 +27,7 @@ #include #include - -#ifdef CONFIG_MIPS_PB1200 #include -#endif - -#ifdef CONFIG_MIPS_DB1200 -#include -#define PB1200_INT_BEGIN DB1200_INT_BEGIN -#define PB1200_INT_END DB1200_INT_END -#endif struct au1xxx_irqmap __initdata au1xxx_irq_map[] = { /* This is external interrupt cascade */ @@ -82,12 +73,7 @@ static void pb1200_unmask_irq(unsigned int irq_nr) } static struct irq_chip pb1200_cpld_irq_type = { -#ifdef CONFIG_MIPS_PB1200 - .name = "Pb1200 Ext", -#endif -#ifdef CONFIG_MIPS_DB1200 - .name = "Db1200 Ext", -#endif + .name = "Pb1200 Ext", .mask = pb1200_mask_irq, .mask_ack = pb1200_maskack_irq, .unmask = pb1200_unmask_irq, @@ -99,7 +85,6 @@ void __init board_init_irq(void) au1xxx_setup_irqmap(au1xxx_irq_map, ARRAY_SIZE(au1xxx_irq_map)); -#ifdef CONFIG_MIPS_PB1200 /* We have a problem with CPLD rev 3. */ if (((bcsr->whoami & BCSR_WHOAMI_CPLD) >> 4) <= 3) { printk(KERN_ERR "WARNING!!!\n"); @@ -119,7 +104,7 @@ void __init board_init_irq(void) printk(KERN_ERR "WARNING!!!\n"); panic("Game over. Your score is 0."); } -#endif + /* mask & disable & ack all */ bcsr->intclr_mask = 0xffff; bcsr->intclr = 0xffff; diff --git a/arch/mips/alchemy/devboards/pb1200/platform.c b/arch/mips/alchemy/devboards/pb1200/platform.c index b93dff4..4d6edd8 100644 --- a/arch/mips/alchemy/devboards/pb1200/platform.c +++ b/arch/mips/alchemy/devboards/pb1200/platform.c @@ -65,7 +65,6 @@ static struct led_classdev pb1200mmc_led = { .brightness_set = pb1200_mmcled_set, }; -#ifndef CONFIG_MIPS_DB1200 static void pb1200mmc1_set_power(void *mmc_host, int state) { if (state) @@ -85,7 +84,6 @@ static int pb1200mmc1_card_inserted(void *mmc_host) { return (bcsr->sig_status & BCSR_INT_SD1INSERT) ? 1 : 0; } -#endif const struct au1xmmc_platform_data au1xmmc_platdata[2] = { [0] = { @@ -95,7 +93,6 @@ const struct au1xmmc_platform_data au1xmmc_platdata[2] = { .cd_setup = NULL, /* use poll-timer in driver */ .led = &pb1200mmc_led, }, -#ifndef CONFIG_MIPS_DB1200 [1] = { .set_power = pb1200mmc1_set_power, .card_inserted = pb1200mmc1_card_inserted, @@ -103,7 +100,6 @@ const struct au1xmmc_platform_data au1xmmc_platdata[2] = { .cd_setup = NULL, /* use poll-timer in driver */ .led = &pb1200mmc_led, }, -#endif }; static struct resource ide_resources[] = { diff --git a/arch/mips/configs/db1200_defconfig b/arch/mips/configs/db1200_defconfig index ab17973..c883812 100644 --- a/arch/mips/configs/db1200_defconfig +++ b/arch/mips/configs/db1200_defconfig @@ -1,79 +1,97 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.20 -# Tue Feb 20 21:47:25 2007 +# Linux kernel version: 2.6.30-rc6 +# Fri May 22 20:39:58 2009 # CONFIG_MIPS=y # # Machine selection # -CONFIG_ZONE_DMA=y CONFIG_MACH_ALCHEMY=y -# CONFIG_MIPS_MTX1 is not set -# CONFIG_MIPS_BOSPORUS is not set -# CONFIG_MIPS_PB1000 is not set -# CONFIG_MIPS_PB1100 is not set -# CONFIG_MIPS_PB1500 is not set -# CONFIG_MIPS_PB1550 is not set -# CONFIG_MIPS_PB1200 is not set -# CONFIG_MIPS_DB1000 is not set -# CONFIG_MIPS_DB1100 is not set -# CONFIG_MIPS_DB1500 is not set -# CONFIG_MIPS_DB1550 is not set -CONFIG_MIPS_DB1200=y -# CONFIG_MIPS_MIRAGE is not set # CONFIG_BASLER_EXCITE is not set +# CONFIG_BCM47XX is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set +# CONFIG_LASAT is not set +# CONFIG_LEMOTE_FULONG is not set # CONFIG_MIPS_MALTA is not set -# CONFIG_WR_PPMC is not set # CONFIG_MIPS_SIM is not set -# CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_MIPS_XXS1500 is not set +# CONFIG_NEC_MARKEINS is not set +# CONFIG_MACH_VR41XX is not set +# CONFIG_NXP_STB220 is not set +# CONFIG_NXP_STB225 is not set # CONFIG_PNX8550_JBS is not set # CONFIG_PNX8550_STB810 is not set -# CONFIG_MACH_VR41XX is not set +# CONFIG_PMC_MSP is not set # CONFIG_PMC_YOSEMITE is not set -# CONFIG_MARKEINS is not set # CONFIG_SGI_IP22 is not set # CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP28 is not set # CONFIG_SGI_IP32 is not set -# CONFIG_SIBYTE_BIGSUR is not set -# CONFIG_SIBYTE_SWARM is not set -# CONFIG_SIBYTE_SENTOSA is not set -# CONFIG_SIBYTE_RHONE is not set -# CONFIG_SIBYTE_CARMEL is not set -# CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CARMEL is not set # CONFIG_SIBYTE_CRHONE is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_BIGSUR is not set # CONFIG_SNI_RM is not set -# CONFIG_TOSHIBA_JMR3927 is not set -# CONFIG_TOSHIBA_RBTX4927 is not set -# CONFIG_TOSHIBA_RBTX4938 is not set +# CONFIG_MACH_TX39XX is not set +# CONFIG_MACH_TX49XX is not set +# CONFIG_MIKROTIK_RB532 is not set +# CONFIG_WR_PPMC is not set +# CONFIG_CAVIUM_OCTEON_SIMULATOR is not set +# CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD is not set +# CONFIG_ALCHEMY_GPIO_INDIRECT is not set +# CONFIG_MIPS_MTX1 is not set +# CONFIG_MIPS_BOSPORUS is not set +# CONFIG_MIPS_DB1000 is not set +# CONFIG_MIPS_DB1100 is not set +CONFIG_MIPS_DB1200=y +# CONFIG_MIPS_DB1500 is not set +# CONFIG_MIPS_DB1550 is not set +# CONFIG_MIPS_MIRAGE is not set +# CONFIG_MIPS_PB1000 is not set +# CONFIG_MIPS_PB1100 is not set +# CONFIG_MIPS_PB1200 is not set +# CONFIG_MIPS_PB1500 is not set +# CONFIG_MIPS_PB1550 is not set +# CONFIG_MIPS_XXS1500 is not set +CONFIG_SOC_AU1200=y +CONFIG_SOC_AU1X00=y CONFIG_RWSEM_GENERIC_SPINLOCK=y # CONFIG_ARCH_HAS_ILOG2_U32 is not set # CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_ARCH_SUPPORTS_OPROFILE=y CONFIG_GENERIC_FIND_NEXT_BIT=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_CLOCKEVENTS=y CONFIG_GENERIC_TIME=y -CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y -# CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ is not set +CONFIG_GENERIC_CMOS_UPDATE=y +CONFIG_SCHED_OMIT_FRAME_POINTER=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +CONFIG_CEVT_R4K_LIB=y +CONFIG_CSRC_R4K_LIB=y CONFIG_DMA_COHERENT=y +# CONFIG_HOTPLUG_CPU is not set CONFIG_MIPS_DISABLE_OBSOLETE_IDE=y +# CONFIG_NO_IOPORT is not set +CONFIG_GENERIC_GPIO=y # CONFIG_CPU_BIG_ENDIAN is not set CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_SYS_SUPPORTS_APM_EMULATION=y CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y -CONFIG_SOC_AU1200=y -CONFIG_SOC_AU1X00=y +CONFIG_IRQ_CPU=y CONFIG_MIPS_L1_CACHE_SHIFT=5 # # CPU selection # +# CONFIG_CPU_LOONGSON2 is not set CONFIG_CPU_MIPS32_R1=y # CONFIG_CPU_MIPS32_R2 is not set # CONFIG_CPU_MIPS64_R1 is not set @@ -86,6 +104,7 @@ CONFIG_CPU_MIPS32_R1=y # CONFIG_CPU_TX49XX is not set # CONFIG_CPU_R5000 is not set # CONFIG_CPU_R5432 is not set +# CONFIG_CPU_R5500 is not set # CONFIG_CPU_R6000 is not set # CONFIG_CPU_NEVADA is not set # CONFIG_CPU_R8000 is not set @@ -93,11 +112,13 @@ CONFIG_CPU_MIPS32_R1=y # CONFIG_CPU_RM7000 is not set # CONFIG_CPU_RM9000 is not set # CONFIG_CPU_SB1 is not set +# CONFIG_CPU_CAVIUM_OCTEON is not set CONFIG_SYS_HAS_CPU_MIPS32_R1=y CONFIG_CPU_MIPS32=y CONFIG_CPU_MIPSR1=y CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_HARDWARE_WATCHPOINTS=y # # Kernel type @@ -107,12 +128,12 @@ CONFIG_32BIT=y CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_8KB is not set # CONFIG_PAGE_SIZE_16KB is not set +# CONFIG_PAGE_SIZE_32KB is not set # CONFIG_PAGE_SIZE_64KB is not set CONFIG_CPU_HAS_PREFETCH=y CONFIG_MIPS_MT_DISABLED=y # CONFIG_MIPS_MT_SMP is not set # CONFIG_MIPS_MT_SMTC is not set -# CONFIG_MIPS_VPE_LOADER is not set CONFIG_64BIT_PHYS_ADDR=y CONFIG_CPU_HAS_LLSC=y CONFIG_CPU_HAS_SYNC=y @@ -120,168 +141,188 @@ CONFIG_GENERIC_HARDIRQS=y CONFIG_GENERIC_IRQ_PROBE=y CONFIG_CPU_SUPPORTS_HIGHMEM=y CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_ARCH_POPULATES_NODE_MAP=y CONFIG_SELECT_MEMORY_MODEL=y CONFIG_FLATMEM_MANUAL=y # CONFIG_DISCONTIGMEM_MANUAL is not set # CONFIG_SPARSEMEM_MANUAL is not set CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_SPARSEMEM_STATIC is not set +CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 -# CONFIG_RESOURCES_64BIT is not set -CONFIG_ZONE_DMA_FLAG=1 +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=0 +CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y +CONFIG_HAVE_MLOCK=y +CONFIG_HAVE_MLOCKED_PAGE_BIT=y +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y # CONFIG_HZ_48 is not set -# CONFIG_HZ_100 is not set +CONFIG_HZ_100=y # CONFIG_HZ_128 is not set # CONFIG_HZ_250 is not set # CONFIG_HZ_256 is not set -CONFIG_HZ_1000=y +# CONFIG_HZ_1000 is not set # CONFIG_HZ_1024 is not set CONFIG_SYS_SUPPORTS_ARBIT_HZ=y -CONFIG_HZ=1000 +CONFIG_HZ=100 CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set # CONFIG_KEXEC is not set +# CONFIG_SECCOMP is not set CONFIG_LOCKDEP_SUPPORT=y CONFIG_STACKTRACE_SUPPORT=y CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" # -# Code maturity level options +# General setup # CONFIG_EXPERIMENTAL=y CONFIG_BROKEN_ON_SMP=y CONFIG_INIT_ENV_ARG_LIMIT=32 - -# -# General setup -# -CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION="-db1200" CONFIG_LOCALVERSION_AUTO=y CONFIG_SWAP=y CONFIG_SYSVIPC=y -# CONFIG_IPC_NS is not set CONFIG_SYSVIPC_SYSCTL=y -# CONFIG_POSIX_MQUEUE is not set +CONFIG_POSIX_MQUEUE=y +CONFIG_POSIX_MQUEUE_SYSCTL=y # CONFIG_BSD_PROCESS_ACCT is not set # CONFIG_TASKSTATS is not set -# CONFIG_UTS_NS is not set # CONFIG_AUDIT is not set -CONFIG_IKCONFIG=y -CONFIG_IKCONFIG_PROC=y -CONFIG_SYSFS_DEPRECATED=y + +# +# RCU Subsystem +# +CONFIG_CLASSIC_RCU=y +# CONFIG_TREE_RCU is not set +# CONFIG_PREEMPT_RCU is not set +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_PREEMPT_RCU_TRACE is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=18 +# CONFIG_GROUP_SCHED is not set +# CONFIG_CGROUPS is not set +# CONFIG_SYSFS_DEPRECATED_V2 is not set # CONFIG_RELAY is not set -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +# CONFIG_NAMESPACES is not set +# CONFIG_BLK_DEV_INITRD is not set +CONFIG_CC_OPTIMIZE_FOR_SIZE=y CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y CONFIG_EMBEDDED=y -CONFIG_SYSCTL_SYSCALL=y +# CONFIG_SYSCTL_SYSCALL is not set CONFIG_KALLSYMS=y +CONFIG_KALLSYMS_ALL=y # CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_STRIP_ASM_SYMS=y CONFIG_HOTPLUG=y CONFIG_PRINTK=y CONFIG_BUG=y CONFIG_ELF_CORE=y +# CONFIG_PCSPKR_PLATFORM is not set CONFIG_BASE_FULL=y CONFIG_FUTEX=y CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y CONFIG_SHMEM=y -CONFIG_SLAB=y -CONFIG_VM_EVENT_COUNTERS=y +CONFIG_AIO=y +# CONFIG_VM_EVENT_COUNTERS is not set +# CONFIG_SLUB_DEBUG is not set +# CONFIG_COMPAT_BRK is not set +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +# CONFIG_MARKERS is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_SLOW_WORK is not set +# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set CONFIG_RT_MUTEXES=y -# CONFIG_TINY_SHMEM is not set CONFIG_BASE_SMALL=0 -# CONFIG_SLOB is not set - -# -# Loadable module support -# CONFIG_MODULES=y +CONFIG_MODULE_FORCE_LOAD=y CONFIG_MODULE_UNLOAD=y -# CONFIG_MODULE_FORCE_UNLOAD is not set -CONFIG_MODVERSIONS=y -CONFIG_MODULE_SRCVERSION_ALL=y -CONFIG_KMOD=y - -# -# Block layer -# +CONFIG_MODULE_FORCE_UNLOAD=y +# CONFIG_MODVERSIONS is not set +# CONFIG_MODULE_SRCVERSION_ALL is not set CONFIG_BLOCK=y # CONFIG_LBD is not set -# CONFIG_BLK_DEV_IO_TRACE is not set -# CONFIG_LSF is not set +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set # # IO Schedulers # CONFIG_IOSCHED_NOOP=y -CONFIG_IOSCHED_AS=y +# CONFIG_IOSCHED_AS is not set CONFIG_IOSCHED_DEADLINE=y -CONFIG_IOSCHED_CFQ=y -CONFIG_DEFAULT_AS=y -# CONFIG_DEFAULT_DEADLINE is not set +# CONFIG_IOSCHED_CFQ is not set +# CONFIG_DEFAULT_AS is not set +CONFIG_DEFAULT_DEADLINE=y # CONFIG_DEFAULT_CFQ is not set # CONFIG_DEFAULT_NOOP is not set -CONFIG_DEFAULT_IOSCHED="anticipatory" +CONFIG_DEFAULT_IOSCHED="deadline" +CONFIG_FREEZER=y # # Bus options (PCI, PCMCIA, EISA, ISA, TC) # +# CONFIG_ARCH_SUPPORTS_MSI is not set CONFIG_MMU=y - -# -# PCCARD (PCMCIA/CardBus) support -# -CONFIG_PCCARD=m +CONFIG_PCCARD=y # CONFIG_PCMCIA_DEBUG is not set -CONFIG_PCMCIA=m +CONFIG_PCMCIA=y CONFIG_PCMCIA_LOAD_CIS=y -CONFIG_PCMCIA_IOCTL=y +# CONFIG_PCMCIA_IOCTL is not set # # PC-card bridges # -CONFIG_PCMCIA_AU1X00=m - -# -# PCI Hotplug Support -# +# CONFIG_PCMCIA_AU1X00 is not set # # Executable file formats # CONFIG_BINFMT_ELF=y -# CONFIG_BINFMT_MISC is not set +CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y +# CONFIG_HAVE_AOUT is not set +CONFIG_BINFMT_MISC=y CONFIG_TRAD_SIGNALS=y # # Power management options # -# CONFIG_PM is not set - -# -# Networking -# +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_PM=y +# CONFIG_PM_DEBUG is not set +CONFIG_PM_SLEEP=y +CONFIG_SUSPEND=y +CONFIG_SUSPEND_FREEZER=y +# CONFIG_APM_EMULATION is not set CONFIG_NET=y # # Networking options # -# CONFIG_NETDEBUG is not set CONFIG_PACKET=y -# CONFIG_PACKET_MMAP is not set +CONFIG_PACKET_MMAP=y CONFIG_UNIX=y -CONFIG_XFRM=y -CONFIG_XFRM_USER=m -# CONFIG_XFRM_SUB_POLICY is not set -CONFIG_XFRM_MIGRATE=y -CONFIG_NET_KEY=y -CONFIG_NET_KEY_MIGRATE=y +# CONFIG_NET_KEY is not set CONFIG_INET=y CONFIG_IP_MULTICAST=y # CONFIG_IP_ADVANCED_ROUTER is not set CONFIG_IP_FIB_HASH=y -# CONFIG_IP_PNP is not set +CONFIG_IP_PNP=y +# CONFIG_IP_PNP_DHCP is not set +# CONFIG_IP_PNP_BOOTP is not set +# CONFIG_IP_PNP_RARP is not set # CONFIG_NET_IPIP is not set # CONFIG_NET_IPGRE is not set # CONFIG_IP_MROUTE is not set @@ -292,107 +333,24 @@ CONFIG_IP_FIB_HASH=y # CONFIG_INET_IPCOMP is not set # CONFIG_INET_XFRM_TUNNEL is not set # CONFIG_INET_TUNNEL is not set -CONFIG_INET_XFRM_MODE_TRANSPORT=m -CONFIG_INET_XFRM_MODE_TUNNEL=m -CONFIG_INET_XFRM_MODE_BEET=m -CONFIG_INET_DIAG=y -CONFIG_INET_TCP_DIAG=y +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +CONFIG_INET_LRO=y +# CONFIG_INET_DIAG is not set # CONFIG_TCP_CONG_ADVANCED is not set CONFIG_TCP_CONG_CUBIC=y CONFIG_DEFAULT_TCP_CONG="cubic" -CONFIG_TCP_MD5SIG=y - -# -# IP: Virtual Server Configuration -# -# CONFIG_IP_VS is not set +# CONFIG_TCP_MD5SIG is not set # CONFIG_IPV6 is not set -# CONFIG_INET6_XFRM_TUNNEL is not set -# CONFIG_INET6_TUNNEL is not set -CONFIG_NETWORK_SECMARK=y -CONFIG_NETFILTER=y -# CONFIG_NETFILTER_DEBUG is not set - -# -# Core Netfilter Configuration -# -# CONFIG_NETFILTER_NETLINK is not set -CONFIG_NF_CONNTRACK_ENABLED=m -CONFIG_NF_CONNTRACK_SUPPORT=y -# CONFIG_IP_NF_CONNTRACK_SUPPORT is not set -CONFIG_NF_CONNTRACK=m -CONFIG_NF_CT_ACCT=y -CONFIG_NF_CONNTRACK_MARK=y -CONFIG_NF_CONNTRACK_SECMARK=y -CONFIG_NF_CONNTRACK_EVENTS=y -CONFIG_NF_CT_PROTO_GRE=m -CONFIG_NF_CT_PROTO_SCTP=m -CONFIG_NF_CONNTRACK_AMANDA=m -CONFIG_NF_CONNTRACK_FTP=m -CONFIG_NF_CONNTRACK_H323=m -CONFIG_NF_CONNTRACK_IRC=m -# CONFIG_NF_CONNTRACK_NETBIOS_NS is not set -CONFIG_NF_CONNTRACK_PPTP=m -CONFIG_NF_CONNTRACK_SANE=m -CONFIG_NF_CONNTRACK_SIP=m -CONFIG_NF_CONNTRACK_TFTP=m -CONFIG_NETFILTER_XTABLES=m -CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m -CONFIG_NETFILTER_XT_TARGET_MARK=m -CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m -CONFIG_NETFILTER_XT_TARGET_NFLOG=m -CONFIG_NETFILTER_XT_TARGET_SECMARK=m -CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=m -CONFIG_NETFILTER_XT_TARGET_TCPMSS=m -CONFIG_NETFILTER_XT_MATCH_COMMENT=m -CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m -CONFIG_NETFILTER_XT_MATCH_CONNMARK=m -CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m -CONFIG_NETFILTER_XT_MATCH_DCCP=m -CONFIG_NETFILTER_XT_MATCH_DSCP=m -CONFIG_NETFILTER_XT_MATCH_ESP=m -CONFIG_NETFILTER_XT_MATCH_HELPER=m -CONFIG_NETFILTER_XT_MATCH_LENGTH=m -CONFIG_NETFILTER_XT_MATCH_LIMIT=m -CONFIG_NETFILTER_XT_MATCH_MAC=m -CONFIG_NETFILTER_XT_MATCH_MARK=m -CONFIG_NETFILTER_XT_MATCH_POLICY=m -CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m -CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m -CONFIG_NETFILTER_XT_MATCH_QUOTA=m -CONFIG_NETFILTER_XT_MATCH_REALM=m -CONFIG_NETFILTER_XT_MATCH_SCTP=m -CONFIG_NETFILTER_XT_MATCH_STATE=m -CONFIG_NETFILTER_XT_MATCH_STATISTIC=m -CONFIG_NETFILTER_XT_MATCH_STRING=m -CONFIG_NETFILTER_XT_MATCH_TCPMSS=m -CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m - -# -# IP: Netfilter Configuration -# -CONFIG_NF_CONNTRACK_IPV4=m -CONFIG_NF_CONNTRACK_PROC_COMPAT=y -# CONFIG_IP_NF_QUEUE is not set -# CONFIG_IP_NF_IPTABLES is not set -# CONFIG_IP_NF_ARPTABLES is not set - -# -# DCCP Configuration (EXPERIMENTAL) -# +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETFILTER is not set # CONFIG_IP_DCCP is not set - -# -# SCTP Configuration (EXPERIMENTAL) -# # CONFIG_IP_SCTP is not set - -# -# TIPC Configuration (EXPERIMENTAL) -# # CONFIG_TIPC is not set # CONFIG_ATM is not set # CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set # CONFIG_VLAN_8021Q is not set # CONFIG_DECNET is not set # CONFIG_LLC2 is not set @@ -402,21 +360,23 @@ CONFIG_NF_CONNTRACK_PROC_COMPAT=y # CONFIG_LAPB is not set # CONFIG_ECONET is not set # CONFIG_WAN_ROUTER is not set - -# -# QoS and/or fair queueing -# +# CONFIG_PHONET is not set # CONFIG_NET_SCHED is not set -CONFIG_NET_CLS_ROUTE=y +# CONFIG_DCB is not set # # Network testing # # CONFIG_NET_PKTGEN is not set # CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set # CONFIG_IRDA is not set # CONFIG_BT is not set -# CONFIG_IEEE80211 is not set +# CONFIG_AF_RXRPC is not set +# CONFIG_WIRELESS is not set +# CONFIG_WIMAX is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set # # Device Drivers @@ -425,25 +385,24 @@ CONFIG_NET_CLS_ROUTE=y # # Generic Driver Options # +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_STANDALONE=y CONFIG_PREVENT_FIRMWARE_BUILD=y CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set # CONFIG_SYS_HYPERVISOR is not set - -# -# Connector - unified userspace <-> kernelspace linker -# # CONFIG_CONNECTOR is not set - -# -# Memory Technology Devices (MTD) -# CONFIG_MTD=y # CONFIG_MTD_DEBUG is not set -# CONFIG_MTD_CONCAT is not set +CONFIG_MTD_CONCAT=y CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_TESTS is not set # CONFIG_MTD_REDBOOT_PARTS is not set # CONFIG_MTD_CMDLINE_PARTS is not set +# CONFIG_MTD_AR7_PARTS is not set # # User Modules And Translation Layers @@ -456,6 +415,7 @@ CONFIG_MTD_BLOCK=y # CONFIG_INFTL is not set # CONFIG_RFD_FTL is not set # CONFIG_SSFDC is not set +# CONFIG_MTD_OOPS is not set # # RAM/ROM/Flash chip drivers @@ -481,19 +441,22 @@ CONFIG_MTD_CFI_UTIL=y # CONFIG_MTD_RAM is not set # CONFIG_MTD_ROM is not set # CONFIG_MTD_ABSENT is not set -# CONFIG_MTD_OBSOLETE_CHIPS is not set # # Mapping drivers for chip access # # CONFIG_MTD_COMPLEX_MAPPINGS is not set -# CONFIG_MTD_PHYSMAP is not set -CONFIG_MTD_ALCHEMY=y +CONFIG_MTD_PHYSMAP=y +# CONFIG_MTD_PHYSMAP_COMPAT is not set +# CONFIG_MTD_ALCHEMY is not set # CONFIG_MTD_PLATRAM is not set # # Self-contained MTD device drivers # +# CONFIG_MTD_DATAFLASH is not set +CONFIG_MTD_M25P80=y +CONFIG_M25PXX_USE_FAST_READ=y # CONFIG_MTD_SLRAM is not set # CONFIG_MTD_PHRAM is not set # CONFIG_MTD_MTDRAM is not set @@ -505,224 +468,139 @@ CONFIG_MTD_ALCHEMY=y # CONFIG_MTD_DOC2000 is not set # CONFIG_MTD_DOC2001 is not set # CONFIG_MTD_DOC2001PLUS is not set - -# -# NAND Flash Device Drivers -# CONFIG_MTD_NAND=y # CONFIG_MTD_NAND_VERIFY_WRITE is not set # CONFIG_MTD_NAND_ECC_SMC is not set +# CONFIG_MTD_NAND_MUSEUM_IDS is not set CONFIG_MTD_NAND_IDS=y # CONFIG_MTD_NAND_AU1550 is not set # CONFIG_MTD_NAND_DISKONCHIP is not set # CONFIG_MTD_NAND_NANDSIM is not set - -# -# OneNAND Flash Device Drivers -# +CONFIG_MTD_NAND_PLATFORM=y +# CONFIG_MTD_ALAUDA is not set # CONFIG_MTD_ONENAND is not set # -# Parallel port support +# LPDDR flash memory drivers # -# CONFIG_PARPORT is not set +# CONFIG_MTD_LPDDR is not set # -# Plug and Play support -# -# CONFIG_PNPACPI is not set - +# UBI - Unsorted block images # -# Block devices -# -# CONFIG_BLK_DEV_COW_COMMON is not set -CONFIG_BLK_DEV_LOOP=y -# CONFIG_BLK_DEV_CRYPTOLOOP is not set -# CONFIG_BLK_DEV_NBD is not set -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_COUNT=16 -CONFIG_BLK_DEV_RAM_SIZE=4096 -CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024 -# CONFIG_BLK_DEV_INITRD is not set -# CONFIG_CDROM_PKTCDVD is not set -# CONFIG_ATA_OVER_ETH is not set +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_WL_THRESHOLD=4096 +CONFIG_MTD_UBI_BEB_RESERVE=1 +# CONFIG_MTD_UBI_GLUEBI is not set # -# Misc devices -# - -# -# ATA/ATAPI/MFM/RLL support +# UBI debugging options # +# CONFIG_MTD_UBI_DEBUG is not set +# CONFIG_PARPORT is not set +# CONFIG_BLK_DEV is not set +# CONFIG_MISC_DEVICES is not set +CONFIG_HAVE_IDE=y CONFIG_IDE=y -CONFIG_IDE_MAX_HWIFS=4 -CONFIG_BLK_DEV_IDE=y # -# Please see Documentation/ide.txt for help/info on IDE drives +# Please see Documentation/ide/ide.txt for help/info on IDE drives # +CONFIG_IDE_XFER_MODE=y +CONFIG_IDE_ATAPI=y # CONFIG_BLK_DEV_IDE_SATA is not set -CONFIG_BLK_DEV_IDEDISK=y -CONFIG_IDEDISK_MULTI_MODE=y -CONFIG_BLK_DEV_IDECS=m -# CONFIG_BLK_DEV_IDECD is not set +CONFIG_IDE_GD=y +CONFIG_IDE_GD_ATA=y +# CONFIG_IDE_GD_ATAPI is not set +CONFIG_BLK_DEV_IDECS=y +CONFIG_BLK_DEV_IDECD=y +CONFIG_BLK_DEV_IDECD_VERBOSE_ERRORS=y # CONFIG_BLK_DEV_IDETAPE is not set -# CONFIG_BLK_DEV_IDEFLOPPY is not set -# CONFIG_BLK_DEV_IDESCSI is not set -# CONFIG_IDE_TASK_IOCTL is not set +CONFIG_IDE_TASK_IOCTL=y +# CONFIG_IDE_PROC_FS is not set # # IDE chipset support/bugfixes # -CONFIG_IDE_GENERIC=y +# CONFIG_IDE_GENERIC is not set +# CONFIG_BLK_DEV_PLATFORM is not set CONFIG_BLK_DEV_IDE_AU1XXX=y CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA=y # CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA is not set -CONFIG_BLK_DEV_IDE_AU1XXX_SEQTS_PER_RQ=128 -# CONFIG_IDE_ARM is not set # CONFIG_BLK_DEV_IDEDMA is not set -# CONFIG_IDEDMA_AUTO is not set -# CONFIG_BLK_DEV_HD is not set # # SCSI device support # # CONFIG_RAID_ATTRS is not set -CONFIG_SCSI=y -CONFIG_SCSI_TGT=m +# CONFIG_SCSI is not set +# CONFIG_SCSI_DMA is not set # CONFIG_SCSI_NETLINK is not set -CONFIG_SCSI_PROC_FS=y - -# -# SCSI support type (disk, tape, CD-ROM) -# -CONFIG_BLK_DEV_SD=y -# CONFIG_CHR_DEV_ST is not set -# CONFIG_CHR_DEV_OSST is not set -CONFIG_BLK_DEV_SR=y -# CONFIG_BLK_DEV_SR_VENDOR is not set -CONFIG_CHR_DEV_SG=y -# CONFIG_CHR_DEV_SCH is not set - -# -# Some SCSI devices (e.g. CD jukebox) support multiple LUNs -# -CONFIG_SCSI_MULTI_LUN=y -# CONFIG_SCSI_CONSTANTS is not set -# CONFIG_SCSI_LOGGING is not set -CONFIG_SCSI_SCAN_ASYNC=y - -# -# SCSI Transports -# -# CONFIG_SCSI_SPI_ATTRS is not set -# CONFIG_SCSI_FC_ATTRS is not set -# CONFIG_SCSI_ISCSI_ATTRS is not set -# CONFIG_SCSI_SAS_ATTRS is not set -# CONFIG_SCSI_SAS_LIBSAS is not set - -# -# SCSI low-level drivers -# -# CONFIG_ISCSI_TCP is not set -# CONFIG_SCSI_DEBUG is not set - -# -# PCMCIA SCSI adapter support -# -# CONFIG_PCMCIA_AHA152X is not set -# CONFIG_PCMCIA_FDOMAIN is not set -# CONFIG_PCMCIA_NINJA_SCSI is not set -# CONFIG_PCMCIA_QLOGIC is not set -# CONFIG_PCMCIA_SYM53C500 is not set - -# -# Serial ATA (prod) and Parallel ATA (experimental) drivers -# # CONFIG_ATA is not set - -# -# Multi-device support (RAID and LVM) -# # CONFIG_MD is not set - -# -# Fusion MPT device support -# -# CONFIG_FUSION is not set - -# -# IEEE 1394 (FireWire) support -# - -# -# I2O device support -# - -# -# Network device support -# CONFIG_NETDEVICES=y +CONFIG_COMPAT_NET_DEV_OPS=y # CONFIG_DUMMY is not set # CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set # CONFIG_EQUALIZER is not set # CONFIG_TUN is not set - -# -# PHY device support -# +# CONFIG_VETH is not set # CONFIG_PHYLIB is not set - -# -# Ethernet (10 or 100Mbit) -# CONFIG_NET_ETHERNET=y -CONFIG_MII=m +CONFIG_MII=y +# CONFIG_AX88796 is not set # CONFIG_MIPS_AU1X00_ENET is not set -# CONFIG_SMC91X is not set +CONFIG_SMC91X=y # CONFIG_DM9000 is not set - -# -# Ethernet (1000 Mbit) -# - -# -# Ethernet (10000 Mbit) -# - -# -# Token Ring devices -# - -# -# Wireless LAN (non-hamradio) -# -# CONFIG_NET_RADIO is not set - -# -# PCMCIA network device support -# -# CONFIG_NET_PCMCIA is not set - -# -# Wan interfaces -# +# CONFIG_ENC28J60 is not set +# CONFIG_ETHOC is not set +# CONFIG_DNET is not set +# CONFIG_IBM_NEW_EMAC_ZMII is not set +# CONFIG_IBM_NEW_EMAC_RGMII is not set +# CONFIG_IBM_NEW_EMAC_TAH is not set +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set +# CONFIG_B44 is not set +# CONFIG_NETDEV_1000 is not set +# CONFIG_NETDEV_10000 is not set + +# +# Wireless LAN +# +# CONFIG_WLAN_PRE80211 is not set +# CONFIG_WLAN_80211 is not set + +# +# Enable WiMAX (Networking options) to see the WiMAX drivers +# + +# +# USB Network Adapters +# +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_USBNET is not set +CONFIG_NET_PCMCIA=y +CONFIG_PCMCIA_3C589=y +# CONFIG_PCMCIA_3C574 is not set +# CONFIG_PCMCIA_FMVJ18X is not set +# CONFIG_PCMCIA_PCNET is not set +# CONFIG_PCMCIA_NMCLAN is not set +# CONFIG_PCMCIA_SMC91C92 is not set +# CONFIG_PCMCIA_XIRC2PS is not set +# CONFIG_PCMCIA_AXNET is not set # CONFIG_WAN is not set # CONFIG_PPP is not set # CONFIG_SLIP is not set -# CONFIG_SHAPER is not set # CONFIG_NETCONSOLE is not set # CONFIG_NETPOLL is not set # CONFIG_NET_POLL_CONTROLLER is not set - -# -# ISDN subsystem -# # CONFIG_ISDN is not set - -# -# Telephony Support -# # CONFIG_PHONE is not set # @@ -730,16 +608,13 @@ CONFIG_MII=m # CONFIG_INPUT=y # CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set # # Userland interfaces # -CONFIG_INPUT_MOUSEDEV=y -CONFIG_INPUT_MOUSEDEV_PSAUX=y -CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 -CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_MOUSEDEV is not set # CONFIG_INPUT_JOYDEV is not set -# CONFIG_INPUT_TSDEV is not set CONFIG_INPUT_EVDEV=y # CONFIG_INPUT_EVBUG is not set @@ -749,28 +624,34 @@ CONFIG_INPUT_EVDEV=y # CONFIG_INPUT_KEYBOARD is not set # CONFIG_INPUT_MOUSE is not set # CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set # CONFIG_INPUT_TOUCHSCREEN is not set -# CONFIG_INPUT_MISC is not set +CONFIG_INPUT_MISC=y +# CONFIG_INPUT_ATI_REMOTE is not set +# CONFIG_INPUT_ATI_REMOTE2 is not set +# CONFIG_INPUT_KEYSPAN_REMOTE is not set +# CONFIG_INPUT_POWERMATE is not set +# CONFIG_INPUT_YEALINK is not set +# CONFIG_INPUT_CM109 is not set +CONFIG_INPUT_UINPUT=y +# CONFIG_INPUT_GPIO_ROTARY_ENCODER is not set # # Hardware I/O ports # -CONFIG_SERIO=y -# CONFIG_SERIO_I8042 is not set -CONFIG_SERIO_SERPORT=y -# CONFIG_SERIO_LIBPS2 is not set -CONFIG_SERIO_RAW=y +# CONFIG_SERIO is not set # CONFIG_GAMEPORT is not set # # Character devices # CONFIG_VT=y +# CONFIG_CONSOLE_TRANSLATIONS is not set CONFIG_VT_CONSOLE=y CONFIG_HW_CONSOLE=y -CONFIG_VT_HW_CONSOLE_BINDING=y +# CONFIG_VT_HW_CONSOLE_BINDING is not set +CONFIG_DEVKMEM=y # CONFIG_SERIAL_NONSTANDARD is not set -# CONFIG_AU1X00_GPIO is not set # # Serial drivers @@ -778,33 +659,22 @@ CONFIG_VT_HW_CONSOLE_BINDING=y CONFIG_SERIAL_8250=y CONFIG_SERIAL_8250_CONSOLE=y # CONFIG_SERIAL_8250_CS is not set -CONFIG_SERIAL_8250_NR_UARTS=4 -CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +CONFIG_SERIAL_8250_NR_UARTS=2 +CONFIG_SERIAL_8250_RUNTIME_UARTS=2 # CONFIG_SERIAL_8250_EXTENDED is not set CONFIG_SERIAL_8250_AU1X00=y # # Non-8250 serial port support # +# CONFIG_SERIAL_MAX3100 is not set CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y CONFIG_UNIX98_PTYS=y -CONFIG_LEGACY_PTYS=y -CONFIG_LEGACY_PTY_COUNT=256 - -# -# IPMI -# +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set +# CONFIG_LEGACY_PTYS is not set # CONFIG_IPMI_HANDLER is not set - -# -# Watchdog Cards -# -# CONFIG_WATCHDOG is not set # CONFIG_HW_RANDOM is not set -# CONFIG_RTC is not set -# CONFIG_GEN_RTC is not set -# CONFIG_DTLK is not set # CONFIG_R3964 is not set # @@ -813,223 +683,596 @@ CONFIG_LEGACY_PTY_COUNT=256 # CONFIG_SYNCLINK_CS is not set # CONFIG_CARDMAN_4000 is not set # CONFIG_CARDMAN_4040 is not set +# CONFIG_IPWIRELESS is not set # CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_CHARDEV=y +# CONFIG_I2C_HELPER_AUTO is not set # -# TPM devices +# I2C Algorithms # -# CONFIG_TCG_TPM is not set +# CONFIG_I2C_ALGOBIT is not set +# CONFIG_I2C_ALGOPCF is not set +# CONFIG_I2C_ALGOPCA is not set # -# I2C support +# I2C Hardware Bus support # -# CONFIG_I2C is not set # -# SPI support +# I2C system bus drivers (mostly embedded / system-on-chip) # -# CONFIG_SPI is not set -# CONFIG_SPI_MASTER is not set +CONFIG_I2C_AU1550=y +# CONFIG_I2C_GPIO is not set +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_SIMTEC is not set # -# Dallas's 1-wire bus +# External I2C/SMBus adapter drivers # +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_TAOS_EVM is not set +# CONFIG_I2C_TINY_USB is not set + +# +# Other I2C/SMBus bus drivers +# +# CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_STUB is not set + +# +# Miscellaneous I2C Chip support +# +# CONFIG_DS1682 is not set +# CONFIG_SENSORS_PCF8574 is not set +# CONFIG_PCF8575 is not set +# CONFIG_SENSORS_PCA9539 is not set +# CONFIG_SENSORS_MAX6875 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# CONFIG_I2C_DEBUG_CHIP is not set +CONFIG_SPI=y +# CONFIG_SPI_DEBUG is not set +CONFIG_SPI_MASTER=y + +# +# SPI Master Controller Drivers +# +CONFIG_SPI_AU1550=y +CONFIG_SPI_BITBANG=y +# CONFIG_SPI_GPIO is not set + +# +# SPI Protocol Masters +# +# CONFIG_SPI_SPIDEV is not set +# CONFIG_SPI_TLE62X0 is not set +CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y +CONFIG_GPIOLIB=y +# CONFIG_DEBUG_GPIO is not set +CONFIG_GPIO_SYSFS=y + +# +# Memory mapped GPIO expanders: +# + +# +# I2C GPIO expanders: +# +# CONFIG_GPIO_MAX732X is not set +# CONFIG_GPIO_PCA953X is not set +# CONFIG_GPIO_PCF857X is not set + +# +# PCI GPIO expanders: +# + +# +# SPI GPIO expanders: +# +# CONFIG_GPIO_MAX7301 is not set +# CONFIG_GPIO_MCP23S08 is not set # CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +CONFIG_HWMON=y +CONFIG_HWMON_VID=y +# CONFIG_SENSORS_AD7414 is not set +# CONFIG_SENSORS_AD7418 is not set +# CONFIG_SENSORS_ADCXX is not set +# CONFIG_SENSORS_ADM1021 is not set +CONFIG_SENSORS_ADM1025=y +# CONFIG_SENSORS_ADM1026 is not set +# CONFIG_SENSORS_ADM1029 is not set +# CONFIG_SENSORS_ADM1031 is not set +# CONFIG_SENSORS_ADM9240 is not set +# CONFIG_SENSORS_ADT7462 is not set +# CONFIG_SENSORS_ADT7470 is not set +# CONFIG_SENSORS_ADT7473 is not set +# CONFIG_SENSORS_ADT7475 is not set +# CONFIG_SENSORS_ATXP1 is not set +# CONFIG_SENSORS_DS1621 is not set +# CONFIG_SENSORS_F71805F is not set +# CONFIG_SENSORS_F71882FG is not set +# CONFIG_SENSORS_F75375S is not set +# CONFIG_SENSORS_G760A is not set +# CONFIG_SENSORS_GL518SM is not set +# CONFIG_SENSORS_GL520SM is not set +# CONFIG_SENSORS_IT87 is not set +# CONFIG_SENSORS_LM63 is not set +CONFIG_SENSORS_LM70=y +# CONFIG_SENSORS_LM75 is not set +# CONFIG_SENSORS_LM77 is not set +# CONFIG_SENSORS_LM78 is not set +# CONFIG_SENSORS_LM80 is not set +# CONFIG_SENSORS_LM83 is not set +# CONFIG_SENSORS_LM85 is not set +# CONFIG_SENSORS_LM87 is not set +# CONFIG_SENSORS_LM90 is not set +# CONFIG_SENSORS_LM92 is not set +# CONFIG_SENSORS_LM93 is not set +# CONFIG_SENSORS_LTC4215 is not set +# CONFIG_SENSORS_LTC4245 is not set +# CONFIG_SENSORS_LM95241 is not set +# CONFIG_SENSORS_MAX1111 is not set +# CONFIG_SENSORS_MAX1619 is not set +# CONFIG_SENSORS_MAX6650 is not set +# CONFIG_SENSORS_PC87360 is not set +# CONFIG_SENSORS_PC87427 is not set +# CONFIG_SENSORS_PCF8591 is not set +# CONFIG_SENSORS_SHT15 is not set +# CONFIG_SENSORS_DME1737 is not set +# CONFIG_SENSORS_SMSC47M1 is not set +# CONFIG_SENSORS_SMSC47M192 is not set +# CONFIG_SENSORS_SMSC47B397 is not set +# CONFIG_SENSORS_ADS7828 is not set +# CONFIG_SENSORS_THMC50 is not set +# CONFIG_SENSORS_VT1211 is not set +# CONFIG_SENSORS_W83781D is not set +# CONFIG_SENSORS_W83791D is not set +# CONFIG_SENSORS_W83792D is not set +# CONFIG_SENSORS_W83793 is not set +# CONFIG_SENSORS_W83L785TS is not set +# CONFIG_SENSORS_W83L786NG is not set +# CONFIG_SENSORS_W83627HF is not set +# CONFIG_SENSORS_W83627EHF is not set +# CONFIG_SENSORS_LIS3_SPI is not set +# CONFIG_HWMON_DEBUG_CHIP is not set +# CONFIG_THERMAL is not set +# CONFIG_THERMAL_HWMON is not set +# CONFIG_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set # -# Hardware Monitoring support +# Multifunction device drivers # -# CONFIG_HWMON is not set -# CONFIG_HWMON_VID is not set +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_UCB1400_CORE is not set +# CONFIG_TPS65010 is not set +# CONFIG_TWL4030_CORE is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_MFD_PCF50633 is not set +# CONFIG_REGULATOR is not set # # Multimedia devices # + +# +# Multimedia core support +# # CONFIG_VIDEO_DEV is not set +# CONFIG_DVB_CORE is not set +# CONFIG_VIDEO_MEDIA is not set # -# Digital Video Broadcasting Devices +# Multimedia drivers # -# CONFIG_DVB is not set +# CONFIG_DAB is not set # # Graphics support # -# CONFIG_FIRMWARE_EDID is not set +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set CONFIG_FB=y -CONFIG_FB_CFB_FILLRECT=y -CONFIG_FB_CFB_COPYAREA=y -CONFIG_FB_CFB_IMAGEBLIT=y +# CONFIG_FIRMWARE_EDID is not set +# CONFIG_FB_DDC is not set +# CONFIG_FB_BOOT_VESA_SUPPORT is not set +# CONFIG_FB_CFB_FILLRECT is not set +# CONFIG_FB_CFB_COPYAREA is not set +# CONFIG_FB_CFB_IMAGEBLIT is not set +# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set +CONFIG_FB_SYS_FILLRECT=y +CONFIG_FB_SYS_COPYAREA=y +CONFIG_FB_SYS_IMAGEBLIT=y +# CONFIG_FB_FOREIGN_ENDIAN is not set +CONFIG_FB_SYS_FOPS=y # CONFIG_FB_SVGALIB is not set # CONFIG_FB_MACMODES is not set # CONFIG_FB_BACKLIGHT is not set # CONFIG_FB_MODE_HELPERS is not set # CONFIG_FB_TILEBLITTING is not set + +# +# Frame buffer hardware drivers +# # CONFIG_FB_S1D13XXX is not set CONFIG_FB_AU1200=y # CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_METRONOME is not set +# CONFIG_FB_MB862XX is not set +# CONFIG_FB_BROADSHEET is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set # # Console display driver support # -CONFIG_VGA_CONSOLE=y -# CONFIG_VGACON_SOFT_SCROLLBACK is not set +# CONFIG_VGA_CONSOLE is not set CONFIG_DUMMY_CONSOLE=y -# CONFIG_FRAMEBUFFER_CONSOLE is not set +CONFIG_FRAMEBUFFER_CONSOLE=y +# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set +# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set +CONFIG_FONTS=y +# CONFIG_FONT_8x8 is not set +CONFIG_FONT_8x16=y +# CONFIG_FONT_6x11 is not set +# CONFIG_FONT_7x14 is not set +# CONFIG_FONT_PEARL_8x8 is not set +# CONFIG_FONT_ACORN_8x8 is not set +# CONFIG_FONT_MINI_4x6 is not set +# CONFIG_FONT_SUN8x16 is not set +# CONFIG_FONT_SUN12x22 is not set +# CONFIG_FONT_10x18 is not set +# CONFIG_LOGO is not set +CONFIG_SOUND=y +# CONFIG_SOUND_OSS_CORE is not set +CONFIG_SND=y +CONFIG_SND_TIMER=y +CONFIG_SND_PCM=y +CONFIG_SND_JACK=y +# CONFIG_SND_SEQUENCER is not set +# CONFIG_SND_MIXER_OSS is not set +# CONFIG_SND_PCM_OSS is not set +CONFIG_SND_HRTIMER=y +CONFIG_SND_DYNAMIC_MINORS=y +# CONFIG_SND_SUPPORT_OLD_API is not set +CONFIG_SND_VERBOSE_PROCFS=y +CONFIG_SND_VERBOSE_PRINTK=y +# CONFIG_SND_DEBUG is not set +CONFIG_SND_VMASTER=y +CONFIG_SND_AC97_CODEC=y +# CONFIG_SND_DRIVERS is not set +# CONFIG_SND_SPI is not set +# CONFIG_SND_MIPS is not set +# CONFIG_SND_USB is not set +# CONFIG_SND_PCMCIA is not set +CONFIG_SND_SOC=y +CONFIG_SND_SOC_AC97_BUS=y +CONFIG_SND_SOC_AU1XPSC=y +CONFIG_SND_SOC_AU1XPSC_I2S=y +CONFIG_SND_SOC_AU1XPSC_AC97=y +CONFIG_SND_SOC_DB1200=y +CONFIG_SND_SOC_I2C_AND_SPI=y +# CONFIG_SND_SOC_ALL_CODECS is not set +CONFIG_SND_SOC_AC97_CODEC=y +CONFIG_SND_SOC_WM8731=y +# CONFIG_SOUND_PRIME is not set +CONFIG_AC97_BUS=y +CONFIG_HID_SUPPORT=y +CONFIG_HID=y +# CONFIG_HID_DEBUG is not set +CONFIG_HIDRAW=y + +# +# USB Input Devices +# +CONFIG_USB_HID=y +# CONFIG_HID_PID is not set +CONFIG_USB_HIDDEV=y + +# +# Special HID drivers +# +# CONFIG_HID_A4TECH is not set +# CONFIG_HID_APPLE is not set +# CONFIG_HID_BELKIN is not set +# CONFIG_HID_CHERRY is not set +# CONFIG_HID_CHICONY is not set +# CONFIG_HID_CYPRESS is not set +# CONFIG_DRAGONRISE_FF is not set +# CONFIG_HID_EZKEY is not set +# CONFIG_HID_KYE is not set +# CONFIG_HID_GYRATION is not set +# CONFIG_HID_KENSINGTON is not set +# CONFIG_HID_LOGITECH is not set +# CONFIG_HID_MICROSOFT is not set +# CONFIG_HID_MONTEREY is not set +# CONFIG_HID_NTRIG is not set +# CONFIG_HID_PANTHERLORD is not set +# CONFIG_HID_PETALYNX is not set +# CONFIG_HID_SAMSUNG is not set +# CONFIG_HID_SONY is not set +# CONFIG_HID_SUNPLUS is not set +# CONFIG_GREENASIA_FF is not set +# CONFIG_HID_TOPSEED is not set +# CONFIG_THRUSTMASTER_FF is not set +# CONFIG_ZEROPLUS_FF is not set +CONFIG_USB_SUPPORT=y +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y +CONFIG_USB_ARCH_HAS_EHCI=y +CONFIG_USB=y +# CONFIG_USB_DEBUG is not set +# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set # -# Logo configuration +# Miscellaneous USB options # -CONFIG_LOGO=y -CONFIG_LOGO_LINUX_MONO=y -CONFIG_LOGO_LINUX_VGA16=y -CONFIG_LOGO_LINUX_CLUT224=y -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set +CONFIG_USB_DEVICEFS=y +# CONFIG_USB_DEVICE_CLASS is not set +CONFIG_USB_DYNAMIC_MINORS=y +# CONFIG_USB_SUSPEND is not set +# CONFIG_USB_OTG is not set +# CONFIG_USB_OTG_WHITELIST is not set +# CONFIG_USB_OTG_BLACKLIST_HUB is not set +# CONFIG_USB_MON is not set +# CONFIG_USB_WUSB is not set +# CONFIG_USB_WUSB_CBAF is not set # -# Sound +# USB Host Controller Drivers # -# CONFIG_SOUND is not set +# CONFIG_USB_C67X00_HCD is not set +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y +CONFIG_USB_EHCI_TT_NEWSCHED=y +# CONFIG_USB_OXU210HP_HCD is not set +CONFIG_USB_EHCI_NO_IO_WATCHDOG=y +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_ISP1760_HCD is not set +CONFIG_USB_OHCI_HCD=y +# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set +# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_HWA_HCD is not set # -# HID Devices +# USB Device Class drivers # -CONFIG_HID=y -# CONFIG_HID_DEBUG is not set +# CONFIG_USB_ACM is not set +# CONFIG_USB_PRINTER is not set +# CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set # -# USB support +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may # -CONFIG_USB_ARCH_HAS_HCD=y -CONFIG_USB_ARCH_HAS_OHCI=y -CONFIG_USB_ARCH_HAS_EHCI=y -# CONFIG_USB is not set # -# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' +# also be needed; see USB_STORAGE Help for more info # +# CONFIG_USB_LIBUSUAL is not set # -# USB Gadget Support +# USB Imaging devices # -CONFIG_USB_GADGET=m -# CONFIG_USB_GADGET_DEBUG_FILES is not set -# CONFIG_USB_GADGET_NET2280 is not set -# CONFIG_USB_GADGET_PXA2XX is not set -# CONFIG_USB_GADGET_GOKU is not set -# CONFIG_USB_GADGET_LH7A40X is not set -# CONFIG_USB_GADGET_OMAP is not set -# CONFIG_USB_GADGET_AT91 is not set -# CONFIG_USB_GADGET_DUMMY_HCD is not set -# CONFIG_USB_GADGET_DUALSPEED is not set +# CONFIG_USB_MDC800 is not set # -# MMC/SD Card support +# USB port drivers # -CONFIG_MMC=y -# CONFIG_MMC_DEBUG is not set -CONFIG_MMC_BLOCK=y -CONFIG_MMC_AU1X=y +# CONFIG_USB_SERIAL is not set # -# LED devices +# USB Miscellaneous drivers # -# CONFIG_NEW_LEDS is not set +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_BERRY_CHARGE is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_SISUSBVGA is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_TEST is not set +# CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_VST is not set +# CONFIG_USB_GADGET is not set # -# LED drivers +# OTG and related infrastructure # +# CONFIG_USB_GPIO_VBUS is not set +# CONFIG_NOP_USB_XCEIV is not set +CONFIG_MMC=y +# CONFIG_MMC_DEBUG is not set +# CONFIG_MMC_UNSAFE_RESUME is not set # -# LED Triggers +# MMC/SD/SDIO Card Drivers # +CONFIG_MMC_BLOCK=y +# CONFIG_MMC_BLOCK_BOUNCE is not set +CONFIG_SDIO_UART=y +# CONFIG_MMC_TEST is not set + +# +# MMC/SD/SDIO Host Controller Drivers +# +# CONFIG_MMC_SDHCI is not set +CONFIG_MMC_AU1X=y +# CONFIG_MMC_SPI is not set +# CONFIG_MEMSTICK is not set +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y # -# InfiniBand support +# LED drivers # +# CONFIG_LEDS_PCA9532 is not set +# CONFIG_LEDS_GPIO is not set +# CONFIG_LEDS_LP5521 is not set +# CONFIG_LEDS_PCA955X is not set +# CONFIG_LEDS_DAC124S085 is not set +# CONFIG_LEDS_BD2802 is not set # -# EDAC - error detection and reporting (RAS) (EXPERIMENTAL) +# LED Triggers # +CONFIG_LEDS_TRIGGERS=y +# CONFIG_LEDS_TRIGGER_TIMER is not set +# CONFIG_LEDS_TRIGGER_IDE_DISK is not set +# CONFIG_LEDS_TRIGGER_HEARTBEAT is not set +# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set +# CONFIG_LEDS_TRIGGER_GPIO is not set +# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set # -# Real Time Clock +# iptables trigger is under Netfilter config (LED target) # -# CONFIG_RTC_CLASS is not set +# CONFIG_ACCESSIBILITY is not set +CONFIG_RTC_LIB=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_HCTOSYS=y +CONFIG_RTC_HCTOSYS_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set # -# DMA Engine support +# RTC interfaces # -# CONFIG_DMA_ENGINE is not set +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +# CONFIG_RTC_DRV_TEST is not set # -# DMA Clients +# I2C RTC drivers # +# CONFIG_RTC_DRV_DS1307 is not set +# CONFIG_RTC_DRV_DS1374 is not set +# CONFIG_RTC_DRV_DS1672 is not set +# CONFIG_RTC_DRV_MAX6900 is not set +# CONFIG_RTC_DRV_RS5C372 is not set +# CONFIG_RTC_DRV_ISL1208 is not set +# CONFIG_RTC_DRV_X1205 is not set +# CONFIG_RTC_DRV_PCF8563 is not set +# CONFIG_RTC_DRV_PCF8583 is not set +# CONFIG_RTC_DRV_M41T80 is not set +# CONFIG_RTC_DRV_S35390A is not set +# CONFIG_RTC_DRV_FM3130 is not set +# CONFIG_RTC_DRV_RX8581 is not set # -# DMA Devices +# SPI RTC drivers # +# CONFIG_RTC_DRV_M41T94 is not set +# CONFIG_RTC_DRV_DS1305 is not set +# CONFIG_RTC_DRV_DS1390 is not set +# CONFIG_RTC_DRV_MAX6902 is not set +# CONFIG_RTC_DRV_R9701 is not set +# CONFIG_RTC_DRV_RS5C348 is not set +# CONFIG_RTC_DRV_DS3234 is not set # -# Auxiliary Display support +# Platform RTC drivers # +# CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_DS1286 is not set +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_BQ4802 is not set +# CONFIG_RTC_DRV_V3020 is not set # -# Virtualization +# on-CPU RTC drivers # +CONFIG_RTC_DRV_AU1XXX=y +# CONFIG_DMADEVICES is not set +# CONFIG_AUXDISPLAY is not set +# CONFIG_UIO is not set +# CONFIG_STAGING is not set # # File systems # CONFIG_EXT2_FS=y -CONFIG_EXT2_FS_XATTR=y -CONFIG_EXT2_FS_POSIX_ACL=y -# CONFIG_EXT2_FS_SECURITY is not set +# CONFIG_EXT2_FS_XATTR is not set # CONFIG_EXT2_FS_XIP is not set -CONFIG_EXT3_FS=y -CONFIG_EXT3_FS_XATTR=y -CONFIG_EXT3_FS_POSIX_ACL=y -CONFIG_EXT3_FS_SECURITY=y -# CONFIG_EXT4DEV_FS is not set -CONFIG_JBD=y -# CONFIG_JBD_DEBUG is not set -CONFIG_FS_MBCACHE=y +# CONFIG_EXT3_FS is not set +# CONFIG_EXT4_FS is not set # CONFIG_REISERFS_FS is not set -CONFIG_JFS_FS=y -# CONFIG_JFS_POSIX_ACL is not set -# CONFIG_JFS_SECURITY is not set -# CONFIG_JFS_DEBUG is not set -# CONFIG_JFS_STATISTICS is not set +# CONFIG_JFS_FS is not set CONFIG_FS_POSIX_ACL=y +CONFIG_FILE_LOCKING=y # CONFIG_XFS_FS is not set -# CONFIG_GFS2_FS is not set # CONFIG_OCFS2_FS is not set -# CONFIG_MINIX_FS is not set -# CONFIG_ROMFS_FS is not set +# CONFIG_BTRFS_FS is not set +CONFIG_DNOTIFY=y CONFIG_INOTIFY=y CONFIG_INOTIFY_USER=y # CONFIG_QUOTA is not set -CONFIG_DNOTIFY=y # CONFIG_AUTOFS_FS is not set # CONFIG_AUTOFS4_FS is not set # CONFIG_FUSE_FS is not set -CONFIG_GENERIC_ACL=y + +# +# Caches +# +# CONFIG_FSCACHE is not set # # CD-ROM/DVD Filesystems # -CONFIG_ISO9660_FS=m +CONFIG_ISO9660_FS=y CONFIG_JOLIET=y CONFIG_ZISOFS=y -CONFIG_UDF_FS=m +CONFIG_UDF_FS=y CONFIG_UDF_NLS=y # # DOS/FAT/NT Filesystems # -CONFIG_FAT_FS=m -CONFIG_MSDOS_FS=m -CONFIG_VFAT_FS=m +CONFIG_FAT_FS=y +# CONFIG_MSDOS_FS is not set +CONFIG_VFAT_FS=y CONFIG_FAT_DEFAULT_CODEPAGE=437 CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" # CONFIG_NTFS_FS is not set @@ -1040,16 +1283,13 @@ CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_PROC_SYSCTL=y +# CONFIG_PROC_PAGE_MONITOR is not set CONFIG_SYSFS=y CONFIG_TMPFS=y -CONFIG_TMPFS_POSIX_ACL=y +# CONFIG_TMPFS_POSIX_ACL is not set # CONFIG_HUGETLB_PAGE is not set -CONFIG_RAMFS=y -CONFIG_CONFIGFS_FS=m - -# -# Miscellaneous filesystems -# +# CONFIG_CONFIGFS_FS is not set +CONFIG_MISC_FILESYSTEMS=y # CONFIG_ADFS_FS is not set # CONFIG_AFFS_FS is not set # CONFIG_ECRYPT_FS is not set @@ -1061,119 +1301,190 @@ CONFIG_CONFIGFS_FS=m CONFIG_JFFS2_FS=y CONFIG_JFFS2_FS_DEBUG=0 CONFIG_JFFS2_FS_WRITEBUFFER=y -# CONFIG_JFFS2_SUMMARY is not set +# CONFIG_JFFS2_FS_WBUF_VERIFY is not set +CONFIG_JFFS2_SUMMARY=y # CONFIG_JFFS2_FS_XATTR is not set -# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set +CONFIG_JFFS2_COMPRESSION_OPTIONS=y CONFIG_JFFS2_ZLIB=y +CONFIG_JFFS2_LZO=y CONFIG_JFFS2_RTIME=y -# CONFIG_JFFS2_RUBIN is not set -CONFIG_CRAMFS=m +CONFIG_JFFS2_RUBIN=y +# CONFIG_JFFS2_CMODE_NONE is not set +CONFIG_JFFS2_CMODE_PRIORITY=y +# CONFIG_JFFS2_CMODE_SIZE is not set +# CONFIG_JFFS2_CMODE_FAVOURLZO is not set +CONFIG_UBIFS_FS=y +# CONFIG_UBIFS_FS_XATTR is not set +CONFIG_UBIFS_FS_ADVANCED_COMPR=y +CONFIG_UBIFS_FS_LZO=y +CONFIG_UBIFS_FS_ZLIB=y +# CONFIG_UBIFS_FS_DEBUG is not set +# CONFIG_CRAMFS is not set +CONFIG_SQUASHFS=y +# CONFIG_SQUASHFS_EMBEDDED is not set +CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3 # CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set # CONFIG_HPFS_FS is not set # CONFIG_QNX4FS_FS is not set +# CONFIG_ROMFS_FS is not set # CONFIG_SYSV_FS is not set # CONFIG_UFS_FS is not set - -# -# Network File Systems -# +# CONFIG_NILFS2_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y CONFIG_NFS_FS=y CONFIG_NFS_V3=y # CONFIG_NFS_V3_ACL is not set -# CONFIG_NFS_V4 is not set -# CONFIG_NFS_DIRECTIO is not set -# CONFIG_NFSD is not set +CONFIG_NFS_V4=y +CONFIG_ROOT_NFS=y +CONFIG_NFSD=y +CONFIG_NFSD_V3=y +# CONFIG_NFSD_V3_ACL is not set +CONFIG_NFSD_V4=y CONFIG_LOCKD=y CONFIG_LOCKD_V4=y +CONFIG_EXPORTFS=y CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y -# CONFIG_RPCSEC_GSS_KRB5 is not set -# CONFIG_RPCSEC_GSS_SPKM3 is not set -CONFIG_SMB_FS=y -# CONFIG_SMB_NLS_DEFAULT is not set +CONFIG_SUNRPC_GSS=y +CONFIG_RPCSEC_GSS_KRB5=y +CONFIG_RPCSEC_GSS_SPKM3=y +# CONFIG_SMB_FS is not set # CONFIG_CIFS is not set # CONFIG_NCP_FS is not set # CONFIG_CODA_FS is not set # CONFIG_AFS_FS is not set -# CONFIG_9P_FS is not set # # Partition Types # -# CONFIG_PARTITION_ADVANCED is not set +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +# CONFIG_OSF_PARTITION is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_ATARI_PARTITION is not set +# CONFIG_MAC_PARTITION is not set CONFIG_MSDOS_PARTITION=y - -# -# Native Language Support -# +# CONFIG_BSD_DISKLABEL is not set +# CONFIG_MINIX_SUBPARTITION is not set +# CONFIG_SOLARIS_X86_PARTITION is not set +# CONFIG_UNIXWARE_DISKLABEL is not set +CONFIG_LDM_PARTITION=y +# CONFIG_LDM_DEBUG is not set +CONFIG_SGI_PARTITION=y +CONFIG_ULTRIX_PARTITION=y +CONFIG_SUN_PARTITION=y +CONFIG_KARMA_PARTITION=y +CONFIG_EFI_PARTITION=y +# CONFIG_SYSV68_PARTITION is not set CONFIG_NLS=y CONFIG_NLS_DEFAULT="iso8859-1" -CONFIG_NLS_CODEPAGE_437=m -CONFIG_NLS_CODEPAGE_737=m -CONFIG_NLS_CODEPAGE_775=m -CONFIG_NLS_CODEPAGE_850=m -CONFIG_NLS_CODEPAGE_852=m -CONFIG_NLS_CODEPAGE_855=m -CONFIG_NLS_CODEPAGE_857=m -CONFIG_NLS_CODEPAGE_860=m -CONFIG_NLS_CODEPAGE_861=m -CONFIG_NLS_CODEPAGE_862=m -CONFIG_NLS_CODEPAGE_863=m -CONFIG_NLS_CODEPAGE_864=m -CONFIG_NLS_CODEPAGE_865=m -CONFIG_NLS_CODEPAGE_866=m -CONFIG_NLS_CODEPAGE_869=m -CONFIG_NLS_CODEPAGE_936=m -CONFIG_NLS_CODEPAGE_950=m -CONFIG_NLS_CODEPAGE_932=m -CONFIG_NLS_CODEPAGE_949=m -CONFIG_NLS_CODEPAGE_874=m -CONFIG_NLS_ISO8859_8=m -CONFIG_NLS_CODEPAGE_1250=m -CONFIG_NLS_CODEPAGE_1251=m -CONFIG_NLS_ASCII=m -CONFIG_NLS_ISO8859_1=m -CONFIG_NLS_ISO8859_2=m -CONFIG_NLS_ISO8859_3=m -CONFIG_NLS_ISO8859_4=m -CONFIG_NLS_ISO8859_5=m -CONFIG_NLS_ISO8859_6=m -CONFIG_NLS_ISO8859_7=m -CONFIG_NLS_ISO8859_9=m -CONFIG_NLS_ISO8859_13=m -CONFIG_NLS_ISO8859_14=m -CONFIG_NLS_ISO8859_15=m -CONFIG_NLS_KOI8_R=m -CONFIG_NLS_KOI8_U=m -CONFIG_NLS_UTF8=m - -# -# Distributed Lock Manager -# -CONFIG_DLM=m -CONFIG_DLM_TCP=y -# CONFIG_DLM_SCTP is not set -# CONFIG_DLM_DEBUG is not set - -# -# Profiling support -# -# CONFIG_PROFILING is not set +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +CONFIG_NLS_CODEPAGE_850=y +CONFIG_NLS_CODEPAGE_852=y +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=y +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +CONFIG_NLS_ISO8859_15=y +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +CONFIG_NLS_UTF8=y +# CONFIG_DLM is not set # # Kernel hacking # CONFIG_TRACE_IRQFLAGS_SUPPORT=y # CONFIG_PRINTK_TIME is not set -CONFIG_ENABLE_MUST_CHECK=y -# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_ENABLE_WARN_DEPRECATED is not set +# CONFIG_ENABLE_MUST_CHECK is not set +CONFIG_FRAME_WARN=1024 +CONFIG_MAGIC_SYSRQ=y # CONFIG_UNUSED_SYMBOLS is not set # CONFIG_DEBUG_FS is not set # CONFIG_HEADERS_CHECK is not set -# CONFIG_DEBUG_KERNEL is not set -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_CROSSCOMPILE=y -CONFIG_CMDLINE="mem=48M" +CONFIG_DEBUG_KERNEL=y +# CONFIG_IRQ_DEBUG is not set +# CONFIG_DEBUG_SHIRQ is not set +# CONFIG_DETECT_SOFTLOCKUP is not set +# CONFIG_DETECT_HUNG_TASK is not set +# CONFIG_SCHED_DEBUG is not set +# CONFIG_SCHEDSTATS is not set +# CONFIG_TIMER_STATS is not set +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_RT_MUTEX_TESTER is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_PROVE_LOCKING is not set +# CONFIG_LOCK_STAT is not set +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_DEBUG_KOBJECT is not set +CONFIG_DEBUG_INFO=y +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_WRITECOUNT is not set +# CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_DEBUG_LIST is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_BOOT_PRINTK_DELAY is not set +# CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +# CONFIG_FAULT_INJECTION is not set +# CONFIG_PAGE_POISONING is not set +CONFIG_TRACING_SUPPORT=y + +# +# Tracers +# +# CONFIG_IRQSOFF_TRACER is not set +# CONFIG_SCHED_TRACER is not set +# CONFIG_CONTEXT_SWITCH_TRACER is not set +# CONFIG_EVENT_TRACER is not set +# CONFIG_BOOT_TRACER is not set +# CONFIG_TRACE_BRANCH_PROFILING is not set +# CONFIG_KMEMTRACE is not set +# CONFIG_WORKQUEUE_TRACER is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_KGDB is not set +CONFIG_CMDLINE="console=ttyS0,115200 video=au1200fb:panel:bs fastboot" +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_RUNTIME_DEBUG is not set # # Security options @@ -1181,67 +1492,123 @@ CONFIG_CMDLINE="mem=48M" CONFIG_KEYS=y CONFIG_KEYS_DEBUG_PROC_KEYS=y # CONFIG_SECURITY is not set +CONFIG_SECURITYFS=y +CONFIG_SECURITY_FILE_CAPABILITIES=y +CONFIG_CRYPTO=y # -# Cryptographic options +# Crypto core or helper # -CONFIG_CRYPTO=y +# CONFIG_CRYPTO_FIPS is not set CONFIG_CRYPTO_ALGAPI=y -CONFIG_CRYPTO_BLKCIPHER=m -CONFIG_CRYPTO_HASH=m -CONFIG_CRYPTO_MANAGER=m -CONFIG_CRYPTO_HMAC=m -CONFIG_CRYPTO_XCBC=m -CONFIG_CRYPTO_NULL=m -CONFIG_CRYPTO_MD4=m -CONFIG_CRYPTO_MD5=y -CONFIG_CRYPTO_SHA1=m -CONFIG_CRYPTO_SHA256=m -CONFIG_CRYPTO_SHA512=m -CONFIG_CRYPTO_WP512=m -CONFIG_CRYPTO_TGR192=m -CONFIG_CRYPTO_GF128MUL=m -CONFIG_CRYPTO_ECB=m -CONFIG_CRYPTO_CBC=m -CONFIG_CRYPTO_PCBC=m -CONFIG_CRYPTO_LRW=m -CONFIG_CRYPTO_DES=m -CONFIG_CRYPTO_FCRYPT=m -CONFIG_CRYPTO_BLOWFISH=m -CONFIG_CRYPTO_TWOFISH=m -CONFIG_CRYPTO_TWOFISH_COMMON=m -CONFIG_CRYPTO_SERPENT=m -CONFIG_CRYPTO_AES=m -CONFIG_CRYPTO_CAST5=m -CONFIG_CRYPTO_CAST6=m -CONFIG_CRYPTO_TEA=m -CONFIG_CRYPTO_ARC4=m -CONFIG_CRYPTO_KHAZAD=m -CONFIG_CRYPTO_ANUBIS=m -CONFIG_CRYPTO_DEFLATE=m -CONFIG_CRYPTO_MICHAEL_MIC=m -CONFIG_CRYPTO_CRC32C=m -CONFIG_CRYPTO_CAMELLIA=m +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_BLKCIPHER2=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_PCOMP=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +# CONFIG_CRYPTO_GF128MUL is not set +# CONFIG_CRYPTO_NULL is not set +CONFIG_CRYPTO_WORKQUEUE=y +# CONFIG_CRYPTO_CRYPTD is not set +# CONFIG_CRYPTO_AUTHENC is not set # CONFIG_CRYPTO_TEST is not set # -# Hardware crypto devices +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_SEQIV is not set + +# +# Block modes +# +CONFIG_CRYPTO_CBC=y +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +CONFIG_CRYPTO_ECB=y +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# +# CONFIG_CRYPTO_HMAC is not set +# CONFIG_CRYPTO_XCBC is not set + +# +# Digest +# +# CONFIG_CRYPTO_CRC32C is not set +# CONFIG_CRYPTO_MD4 is not set +CONFIG_CRYPTO_MD5=y +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +# CONFIG_CRYPTO_SHA1 is not set +# CONFIG_CRYPTO_SHA256 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +CONFIG_CRYPTO_AES=y +# CONFIG_CRYPTO_ANUBIS is not set +CONFIG_CRYPTO_ARC4=y +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +CONFIG_CRYPTO_CAST5=y +# CONFIG_CRYPTO_CAST6 is not set +CONFIG_CRYPTO_DES=y +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TWOFISH is not set + +# +# Compression +# +CONFIG_CRYPTO_DEFLATE=y +# CONFIG_CRYPTO_ZLIB is not set +CONFIG_CRYPTO_LZO=y + +# +# Random Number Generation # +# CONFIG_CRYPTO_ANSI_CPRNG is not set +# CONFIG_CRYPTO_HW is not set +# CONFIG_BINARY_PRINTF is not set # # Library routines # CONFIG_BITREVERSE=y -CONFIG_CRC_CCITT=y -# CONFIG_CRC16 is not set +CONFIG_GENERIC_FIND_LAST_BIT=y +# CONFIG_CRC_CCITT is not set +CONFIG_CRC16=y +# CONFIG_CRC_T10DIF is not set +CONFIG_CRC_ITU_T=y CONFIG_CRC32=y -CONFIG_LIBCRC32C=y +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set CONFIG_ZLIB_INFLATE=y CONFIG_ZLIB_DEFLATE=y -CONFIG_TEXTSEARCH=y -CONFIG_TEXTSEARCH_KMP=m -CONFIG_TEXTSEARCH_BM=m -CONFIG_TEXTSEARCH_FSM=m -CONFIG_PLIST=y +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y CONFIG_HAS_IOMEM=y CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y +CONFIG_NLATTR=y diff --git a/arch/mips/include/asm/mach-db1x00/db1200.h b/arch/mips/include/asm/mach-db1x00/db1200.h index 27f2610..2a54103 100644 --- a/arch/mips/include/asm/mach-db1x00/db1200.h +++ b/arch/mips/include/asm/mach-db1x00/db1200.h @@ -25,25 +25,6 @@ #define __ASM_DB1200_H #include -#include - -#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX -#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX -#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC1_TX -#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC1_RX - -/* - * SPI and SMB are muxed on the DBAu1200 board. - * Refer to board documentation. - */ -#define SPI_PSC_BASE PSC0_BASE_ADDR -#define SMBUS_PSC_BASE PSC0_BASE_ADDR -/* - * AC'97 and I2S are muxed on the DBAu1200 board. - * Refer to board documentation. - */ -#define AC97_PSC_BASE PSC1_BASE_ADDR -#define I2S_PSC_BASE PSC1_BASE_ADDR #define BCSR_KSEG1_ADDR 0xB9800000 @@ -123,8 +104,8 @@ static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR; #define BCSR_RESETS_TV 0x0010 /* Not resets but in the same register */ #define BCSR_RESETS_PWMR1MUX 0x0800 -#define BCSR_RESETS_PCS0MUX 0x1000 -#define BCSR_RESETS_PCS1MUX 0x2000 +#define BCSR_RESETS_PSC0MUX 0x1000 +#define BCSR_RESETS_PSC1MUX 0x2000 #define BCSR_RESETS_SPISEL 0x4000 #define BCSR_PCMCIA_PC0VPP 0x0003 diff --git a/sound/soc/au1x/Kconfig b/sound/soc/au1x/Kconfig index 410a893..4b67140 100644 --- a/sound/soc/au1x/Kconfig +++ b/sound/soc/au1x/Kconfig @@ -22,11 +22,13 @@ config SND_SOC_AU1XPSC_AC97 ## ## Boards ## -config SND_SOC_SAMPLE_PSC_AC97 - tristate "Sample Au12x0/Au1550 PSC AC97 sound machine" +config SND_SOC_DB1200 + tristate "DB1200 AC97+I2S audio support" depends on SND_SOC_AU1XPSC select SND_SOC_AU1XPSC_AC97 select SND_SOC_AC97_CODEC + select SND_SOC_AU1XPSC_I2S + select SND_SOC_WM8731 help - This is a sample AC97 sound machine for use in Au12x0/Au1550 - based systems which have audio on PSC1 (e.g. Db1200 demoboard). + Select this option to enable audio (AC97 or I2S) on the + Alchemy/AMD/RMI DB1200 demoboard. diff --git a/sound/soc/au1x/Makefile b/sound/soc/au1x/Makefile index 6c6950b..1687307 100644 --- a/sound/soc/au1x/Makefile +++ b/sound/soc/au1x/Makefile @@ -8,6 +8,6 @@ obj-$(CONFIG_SND_SOC_AU1XPSC_I2S) += snd-soc-au1xpsc-i2s.o obj-$(CONFIG_SND_SOC_AU1XPSC_AC97) += snd-soc-au1xpsc-ac97.o # Boards -snd-soc-sample-ac97-objs := sample-ac97.o +snd-soc-db1200-objs := db1200.o -obj-$(CONFIG_SND_SOC_SAMPLE_PSC_AC97) += snd-soc-sample-ac97.o +obj-$(CONFIG_SND_SOC_DB1200) += snd-soc-db1200.o diff --git a/sound/soc/au1x/db1200.c b/sound/soc/au1x/db1200.c new file mode 100644 index 0000000..a2cb02c --- /dev/null +++ b/sound/soc/au1x/db1200.c @@ -0,0 +1,189 @@ +/* + * DB1200 ASoC audio support code. + * + * (c) 2008 Manuel Lauss + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* it sucks that the ASoC headers are not under include/ */ +#include "../codecs/ac97.h" +#include "../codecs/wm8731.h" +#include "psc.h" + +/*------------------------- AC97 PART ---------------------------*/ + +static int db1200_ac97_init(struct snd_soc_codec *codec) +{ + snd_soc_dapm_sync(codec); + return 0; +} + +static struct snd_soc_dai_link db1200_ac97_dai = { + .name = "AC97", + .stream_name = "AC97 HiFi", + .cpu_dai = &au1xpsc_ac97_dai, + .codec_dai = &ac97_dai, + .init = db1200_ac97_init, +}; + +static struct snd_soc_card db1200_ac97_machine = { + .name = "DB1200 AC97 Audio", + .dai_link = &db1200_ac97_dai, + .num_links = 1, + .platform = &au1xpsc_soc_platform, +}; + +static struct snd_soc_device db1200_ac97_devdata = { + .card = &db1200_ac97_machine, + .codec_dev = &soc_codec_dev_ac97, +}; + +/*------------------------- I2S PART ---------------------------*/ + +static int db1200_i2s_startup(struct snd_pcm_substream *substream) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_dai *codec_dai = rtd->dai->codec_dai; + struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai; + int ret; + + /* WM8731 has its own 12MHz crystal */ + snd_soc_dai_set_sysclk(codec_dai, WM8731_SYSCLK, + 12000000, SND_SOC_CLOCK_IN); + + /* codec is bitclock and lrclk master */ + ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_LEFT_J | + SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBM_CFM); + if (ret < 0) + goto out; + + ret = snd_soc_dai_set_fmt(cpu_dai, SND_SOC_DAIFMT_LEFT_J | + SND_SOC_DAIFMT_NB_NF | SND_SOC_DAIFMT_CBM_CFM); + if (ret < 0) + goto out; + + ret = 0; +out: + return ret; +} + +static struct snd_soc_ops db1200_i2s_wm8731_ops = { + .startup = db1200_i2s_startup, +}; + +static int db1200_i2s_init(struct snd_soc_codec *codec) +{ + snd_soc_dapm_sync(codec); + return 0; +} + +static struct snd_soc_dai_link db1200_i2s_dai = { + .name = "WM8731", + .stream_name = "WM8731 PCM", + .cpu_dai = &au1xpsc_i2s_dai, + .codec_dai = &wm8731_dai, + .init = db1200_i2s_init, + .ops = &db1200_i2s_wm8731_ops, +}; + +static struct snd_soc_card db1200_i2s_machine = { + .name = "DB1200 I2S Audio", + .dai_link = &db1200_i2s_dai, + .num_links = 1, + .platform = &au1xpsc_soc_platform, +}; + +static struct snd_soc_device db1200_i2s_devdata = { + .card = &db1200_i2s_machine, + .codec_dev = &soc_codec_dev_wm8731, +}; + +/*------------------------- COMMON PART ---------------------------*/ + +static struct resource psc1_res[] = { + [0] = { + .start = CPHYSADDR(PSC1_BASE_ADDR), + .end = CPHYSADDR(PSC1_BASE_ADDR) + 0x000fffff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AU1200_PSC1_INT, + .end = AU1200_PSC1_INT, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = DSCR_CMD0_PSC1_TX, + .end = DSCR_CMD0_PSC1_TX, + .flags = IORESOURCE_DMA, + }, + [3] = { + .start = DSCR_CMD0_PSC1_RX, + .end = DSCR_CMD0_PSC1_RX, + .flags = IORESOURCE_DMA, + }, +}; + +static struct platform_device *db1200_asoc_dev; + +static int __init db1200_audio_load(void) +{ + int ret; + + /* DB1200: PSC clock is supplied externally */ + au_writel(PSC_SEL_CLK_SERCLK, PSC1_BASE_ADDR + PSC_SEL_OFFSET); + au_sync(); + + ret = -ENOMEM; + db1200_asoc_dev = platform_device_alloc("soc-audio", -1); + if (!db1200_asoc_dev) + goto out; + + db1200_asoc_dev->resource = + kmemdup(psc1_res, sizeof(struct resource) * + ARRAY_SIZE(psc1_res), GFP_KERNEL); + db1200_asoc_dev->num_resources = ARRAY_SIZE(psc1_res); + db1200_asoc_dev->id = 1; + + /* DB1200 board setup set PSC1MUX to preferred audio device */ + if (bcsr->resets & BCSR_RESETS_PSC1MUX) + platform_set_drvdata(db1200_asoc_dev, &db1200_i2s_devdata); + else + platform_set_drvdata(db1200_asoc_dev, &db1200_ac97_devdata); + + db1200_ac97_devdata.dev = &db1200_asoc_dev->dev; + db1200_i2s_devdata.dev = &db1200_asoc_dev->dev; + ret = platform_device_add(db1200_asoc_dev); + + if (ret) { + platform_device_put(db1200_asoc_dev); + db1200_asoc_dev = NULL; + } +out: + return ret; +} + +static void __exit db1200_audio_unload(void) +{ + platform_device_unregister(db1200_asoc_dev); +} + +module_init(db1200_audio_load); +module_exit(db1200_audio_unload); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("DB1200 ASoC audio support"); +MODULE_AUTHOR("Manuel Lauss"); diff --git a/sound/soc/au1x/sample-ac97.c b/sound/soc/au1x/sample-ac97.c deleted file mode 100644 index 27683eb..0000000 --- a/sound/soc/au1x/sample-ac97.c +++ /dev/null @@ -1,144 +0,0 @@ -/* - * Sample Au12x0/Au1550 PSC AC97 sound machine. - * - * Copyright (c) 2007-2008 Manuel Lauss - * - * This program is free software; you can redistribute it and/or modify - * it under the terms outlined in the file COPYING at the root of this - * source archive. - * - * This is a very generic AC97 sound machine driver for boards which - * have (AC97) audio at PSC1 (e.g. DB1200 demoboards). - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "../codecs/ac97.h" -#include "psc.h" - -static int au1xpsc_sample_ac97_init(struct snd_soc_codec *codec) -{ - snd_soc_dapm_sync(codec); - return 0; -} - -static struct snd_soc_dai_link au1xpsc_sample_ac97_dai = { - .name = "AC97", - .stream_name = "AC97 HiFi", - .cpu_dai = &au1xpsc_ac97_dai, /* see psc-ac97.c */ - .codec_dai = &ac97_dai, /* see codecs/ac97.c */ - .init = au1xpsc_sample_ac97_init, - .ops = NULL, -}; - -static struct snd_soc_card au1xpsc_sample_ac97_machine = { - .name = "Au1xxx PSC AC97 Audio", - .dai_link = &au1xpsc_sample_ac97_dai, - .num_links = 1, -}; - -static struct snd_soc_device au1xpsc_sample_ac97_devdata = { - .card = &au1xpsc_sample_ac97_machine, - .platform = &au1xpsc_soc_platform, /* see dbdma2.c */ - .codec_dev = &soc_codec_dev_ac97, -}; - -static struct resource au1xpsc_psc1_res[] = { - [0] = { - .start = CPHYSADDR(PSC1_BASE_ADDR), - .end = CPHYSADDR(PSC1_BASE_ADDR) + 0x000fffff, - .flags = IORESOURCE_MEM, - }, - [1] = { -#ifdef CONFIG_SOC_AU1200 - .start = AU1200_PSC1_INT, - .end = AU1200_PSC1_INT, -#elif defined(CONFIG_SOC_AU1550) - .start = AU1550_PSC1_INT, - .end = AU1550_PSC1_INT, -#endif - .flags = IORESOURCE_IRQ, - }, - [2] = { - .start = DSCR_CMD0_PSC1_TX, - .end = DSCR_CMD0_PSC1_TX, - .flags = IORESOURCE_DMA, - }, - [3] = { - .start = DSCR_CMD0_PSC1_RX, - .end = DSCR_CMD0_PSC1_RX, - .flags = IORESOURCE_DMA, - }, -}; - -static struct platform_device *au1xpsc_sample_ac97_dev; - -static int __init au1xpsc_sample_ac97_load(void) -{ - int ret; - -#ifdef CONFIG_SOC_AU1200 - unsigned long io; - - /* modify sys_pinfunc for AC97 on PSC1 */ - io = au_readl(SYS_PINFUNC); - io |= SYS_PINFUNC_P1C; - io &= ~(SYS_PINFUNC_P1A | SYS_PINFUNC_P1B); - au_writel(io, SYS_PINFUNC); - au_sync(); -#endif - - ret = -ENOMEM; - - /* setup PSC clock source for AC97 part: external clock provided - * by codec. The psc-ac97.c driver depends on this setting! - */ - au_writel(PSC_SEL_CLK_SERCLK, PSC1_BASE_ADDR + PSC_SEL_OFFSET); - au_sync(); - - au1xpsc_sample_ac97_dev = platform_device_alloc("soc-audio", -1); - if (!au1xpsc_sample_ac97_dev) - goto out; - - au1xpsc_sample_ac97_dev->resource = - kmemdup(au1xpsc_psc1_res, sizeof(struct resource) * - ARRAY_SIZE(au1xpsc_psc1_res), GFP_KERNEL); - au1xpsc_sample_ac97_dev->num_resources = ARRAY_SIZE(au1xpsc_psc1_res); - au1xpsc_sample_ac97_dev->id = 1; - - platform_set_drvdata(au1xpsc_sample_ac97_dev, - &au1xpsc_sample_ac97_devdata); - au1xpsc_sample_ac97_devdata.dev = &au1xpsc_sample_ac97_dev->dev; - ret = platform_device_add(au1xpsc_sample_ac97_dev); - - if (ret) { - platform_device_put(au1xpsc_sample_ac97_dev); - au1xpsc_sample_ac97_dev = NULL; - } - -out: - return ret; -} - -static void __exit au1xpsc_sample_ac97_exit(void) -{ - platform_device_unregister(au1xpsc_sample_ac97_dev); -} - -module_init(au1xpsc_sample_ac97_load); -module_exit(au1xpsc_sample_ac97_exit); - -MODULE_LICENSE("GPL"); -MODULE_DESCRIPTION("Au1xxx PSC sample AC97 machine"); -MODULE_AUTHOR("Manuel Lauss "); -- 1.6.3.1 From mpm@selenic.com Wed Jun 3 19:50:28 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 03 Jun 2009 19:50:36 +0100 (WEST) Received: from waste.org ([66.93.16.53]:48051 "EHLO waste.org" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20021952AbZFCSu2 (ORCPT ); Wed, 3 Jun 2009 19:50:28 +0100 Received: from [192.168.1.100] ([10.0.0.101]) (authenticated bits=0) by waste.org (8.13.8/8.13.8/Debian-3) with ESMTP id n53Inq36016400 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NOT); Wed, 3 Jun 2009 13:49:54 -0500 Subject: Re: [PATCH] hwrng: Add TX4939 RNG driver (v2) From: Matt Mackall To: Ralf Baechle Cc: Herbert Xu , Atsushi Nemoto , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org In-Reply-To: <20090603100215.GA13250@linux-mips.org> References: <1243954462-18149-1-git-send-email-anemo@mba.ocn.ne.jp> <1243973584.22069.182.camel@calx> <20090603090238.GH23561@linux-mips.org> <20090603092610.GA11258@gondor.apana.org.au> <20090603092927.GA11369@gondor.apana.org.au> <20090603100215.GA13250@linux-mips.org> Content-Type: text/plain Date: Wed, 03 Jun 2009 13:49:46 -0500 Message-Id: <1244054986.22069.200.camel@calx> Mime-Version: 1.0 X-Mailer: Evolution 2.26.1.1 Content-Transfer-Encoding: 7bit X-Virus-Scanned: by amavisd-new Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23233 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mpm@selenic.com Precedence: bulk X-list: linux-mips On Wed, 2009-06-03 at 11:02 +0100, Ralf Baechle wrote: > On Wed, Jun 03, 2009 at 07:29:27PM +1000, Herbert Xu wrote: > > > On Wed, Jun 03, 2009 at 07:26:10PM +1000, Herbert Xu wrote: > > > On Wed, Jun 03, 2009 at 10:02:38AM +0100, Ralf Baechle wrote: > > > > > > > Ok, I'll send this to Linus for 2.6.31 then. > > > > > > Actually I've already added it to my tree since I'm looking after > > > the hwrng drivers. > > > > But if this causes any conflicts for you, then please let me know > > and I'll back it out. > > Ah, I was looking at MAINTAINERS which said Mack who had acked it was > handling it. I'm the maintainer of record for random.c, which is different. Not long ago, I sent in a patch to add myself to the HWRNG piece because people were regularly sending me things to review and it was marked as orphan. So, Herbert: we should probably resolve this confusion in MAINTAINERS. We should add one or both of our names to HWRNG and, if necessary, add a comment to RANDOM pointing to HWRNG. I have an eventual goal to make random.c sample the hwrngs without a trip through userspace, so this may get even more confusing. -- http://selenic.com : development and support for Mercurial and Linux From greg@kroah.com Thu Jun 4 01:01:36 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 04 Jun 2009 01:01:42 +0100 (WEST) Received: from kroah.org ([198.145.64.141]:46785 "EHLO coco.kroah.org" rhost-flags-OK-FAIL-OK-FAIL) by ftp.linux-mips.org with ESMTP id S20021561AbZFDABg (ORCPT ); Thu, 4 Jun 2009 01:01:36 +0100 Received: from localhost (c-76-105-230-205.hsd1.or.comcast.net [76.105.230.205]) (using TLSv1 with cipher DHE-RSA-AES128-SHA (128/128 bits)) (No client certificate requested) by coco.kroah.org (Postfix) with ESMTPSA id D2D8448FA4; Wed, 3 Jun 2009 17:01:13 -0700 (PDT) Date: Wed, 3 Jun 2009 16:54:28 -0700 From: Greg KH To: David Daney Cc: gregkh@suse.de, Ralf Baechle , linux-mips Subject: Re: [PATCH 0/7] Staging: Octeon-ethernet driver. Message-ID: <20090603235428.GB19375@kroah.com> References: <4A00DA84.5040101@caviumnetworks.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <4A00DA84.5040101@caviumnetworks.com> User-Agent: Mutt/1.5.19 (2009-01-05) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23234 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: greg@kroah.com Precedence: bulk X-list: linux-mips On Tue, May 05, 2009 at 05:32:04PM -0700, David Daney wrote: > This patch set introduces the octeon-ethernet driver into the > drivers/staging tree. The Octeon is a mips64r2 base multi-core SOC > family. > > The first five patches are small tweaks to the existing octeon support > that are required by the ethernet driver. I would expect them to be > merged via Ralf's linux-mips.org tree. > > The last two are the driver, and would probably be merged via the > drivers/staging tree. However since they depend on the first five, > they probably shouldn't be merged until those five are merged. Ok, as Ralf doesn't seem to have responded to my previous query, I'll just merge the last driver, and mark it CONFIG_BROKEN which you can turn off when the infrastructure portions go in. Sound reasonable? thanks, greg k-h From f.fainelli@gmail.com Thu Jun 4 08:49:58 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 04 Jun 2009 08:50:04 +0100 (WEST) Received: from fg-out-1718.google.com ([72.14.220.153]:2221 "EHLO fg-out-1718.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20022351AbZFDHt6 convert rfc822-to-8bit (ORCPT ); Thu, 4 Jun 2009 08:49:58 +0100 Received: by fg-out-1718.google.com with SMTP id 22so212551fge.9 for ; Thu, 04 Jun 2009 00:49:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:sender:from:to:subject:date :user-agent:cc:references:in-reply-to:mime-version:content-type :content-transfer-encoding:content-disposition:message-id; bh=T9GRYk3HS1OUnG+AhAAbyoK3MZ/MAuRVxUmXWlg2b78=; b=eaODcN+QvbX/TXfWvki9x4Daj3yVHEEbDcrKh3xpE+9YtytD5K7+K5kGpsB2f08PQs ajDo+lCmtmK88bMNE22g+T3ixe/I5B2+K6ScSvEeFoEk4kWQ1g7OQYx24hqBAFRe3Kla Vm/z7qTaqmM6g0MwB5GqazsYJB+/y2NxNvLzs= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:from:to:subject:date:user-agent:cc:references:in-reply-to :mime-version:content-type:content-transfer-encoding :content-disposition:message-id; b=fnoy2JTzYfn0xuJyqO1dDgWj2ACqxRYQBfDd70rmhhHuUHWG5e6v6xiGBEvN3R/l+n xAjdT3XUY5qkInId6FfaD9hfpuB3vPfQOpNuS5RMssm+coURMg/BnJRd2t9Hd8m5Du9U oKRtNidgi9m/HH0mO44ymuiAdjMbq6MxkkVZY= Received: by 10.86.96.1 with SMTP id t1mr2097121fgb.68.1244101797557; Thu, 04 Jun 2009 00:49:57 -0700 (PDT) Received: from florian.lab.openpattern.org (lab.openpattern.org [82.240.16.241]) by mx.google.com with ESMTPS id e11sm1136653fga.16.2009.06.04.00.49.54 (version=TLSv1/SSLv3 cipher=RC4-MD5); Thu, 04 Jun 2009 00:49:54 -0700 (PDT) From: Florian Fainelli To: Greg KH , David Miller Subject: Re: [PATCH 0/7] Staging: Octeon-ethernet driver. Date: Thu, 4 Jun 2009 09:49:52 +0200 User-Agent: KMail/1.9.9 Cc: David Daney , gregkh@suse.de, Ralf Baechle , linux-mips References: <4A00DA84.5040101@caviumnetworks.com> <20090603235428.GB19375@kroah.com> In-Reply-To: <20090603235428.GB19375@kroah.com> MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 8BIT Content-Disposition: inline Message-Id: <200906040949.53167.florian@openwrt.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23235 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips Le Thursday 04 June 2009 01:54:28 Greg KH, vous avez écrit : > On Tue, May 05, 2009 at 05:32:04PM -0700, David Daney wrote: > > This patch set introduces the octeon-ethernet driver into the > > drivers/staging tree. The Octeon is a mips64r2 base multi-core SOC > > family. > > > > The first five patches are small tweaks to the existing octeon support > > that are required by the ethernet driver. I would expect them to be > > merged via Ralf's linux-mips.org tree. > > > > The last two are the driver, and would probably be merged via the > > drivers/staging tree. However since they depend on the first five, > > they probably shouldn't be merged until those five are merged. > > Ok, as Ralf doesn't seem to have responded to my previous query, I'll > just merge the last driver, and mark it CONFIG_BROKEN which you can turn > off when the infrastructure portions go in. > > Sound reasonable? Cannot we get this driver merged via David Miller's tree instead ? It has been rock solid here and does not seem too ugly for a net-next-2.6 inclusion imho. -- Best regards, Florian Fainelli Email : florian@openwrt.org http://openwrt.org ------------------------------- From f.fainelli@gmail.com Thu Jun 4 10:22:23 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 04 Jun 2009 10:22:29 +0100 (WEST) Received: from mail-fx0-f223.google.com ([209.85.220.223]:50658 "EHLO mail-fx0-f223.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20022409AbZFDJWX convert rfc822-to-8bit (ORCPT ); Thu, 4 Jun 2009 10:22:23 +0100 Received: by fxm23 with SMTP id 23so601995fxm.0 for ; Thu, 04 Jun 2009 02:22:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:sender:from:to:subject:date :user-agent:cc:references:in-reply-to:mime-version:content-type :content-transfer-encoding:content-disposition:message-id; bh=3H04p7mDv0jeDPAGi1Pr5xsMitOHVPUuLZcAI4ldC3M=; b=K9Eh5gYNfIag+ZmQS8DGqyICTHT5M9/Q+tyBrj/P15P2tRS1C/ABjp8Lwt2sXdRk9O uAPuznzgql0xE74eyOs7Q7XCTk4K1zB4RuOuKSyRdHMQy3fJm6zR6rl2dltKykiDSWJ1 Ht/OiJL8uoYA7XD69SuaqZdbUkXKYhuwaci5I= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:from:to:subject:date:user-agent:cc:references:in-reply-to :mime-version:content-type:content-transfer-encoding :content-disposition:message-id; b=fAPaGCsDBJNf0lpdMkB2KKOz+1e/wkyy7cp+efIiKa8H5ct0JwF1jGlEGKW+K54A3j 1m7ItD/vLgFHo6wAn8JwXnT/1aaBHfolyzTtOvVZueKiYkdL8HXUfUcaB+SQPJC6N7Xo fM4ayt/76WDddLGzprMjhTgIGA38YqQ/sG5+8= Received: by 10.103.52.13 with SMTP id e13mr1198706muk.52.1244107336823; Thu, 04 Jun 2009 02:22:16 -0700 (PDT) Received: from florian.lab.openpattern.org (lab.openpattern.org [82.240.16.241]) by mx.google.com with ESMTPS id n7sm3973377mue.58.2009.06.04.02.22.15 (version=TLSv1/SSLv3 cipher=RC4-MD5); Thu, 04 Jun 2009 02:22:16 -0700 (PDT) From: Florian Fainelli To: Ralf Baechle Subject: Re: [PATCH 08/10] add TI AR7 support Date: Thu, 4 Jun 2009 11:22:13 +0200 User-Agent: KMail/1.9.9 Cc: linux-mips@linux-mips.org, openwrt-devel@lists.openwrt.org References: <200906011402.05768.florian@openwrt.org> <20090602125159.GC11488@linux-mips.org> In-Reply-To: <20090602125159.GC11488@linux-mips.org> MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 8BIT Content-Disposition: inline Message-Id: <200906041122.14063.florian@openwrt.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23236 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips Hallo Ralf, Le Tuesday 02 June 2009 14:51:59 Ralf Baechle, vous avez écrit : [snip] > > + > > + writel(((prediv - 1) << PREDIV_SHIFT) | (postdiv - 1), &clock->ctrl); > > + mdelay(1); > > + writel(4, &clock->pll); > > + while (readl(&clock->pll) & PLL_STATUS) > > + ; > > + writel(((mul - 1) << MUL_SHIFT) | (0xff << 3) | 0x0e, &clock->pll); > > + mdelay(75); > > These calls to mdelay seem to be done very early before BogoMIPS has been > calibrated? Yes, is there a prefered way than using mdelay here ? > > > Can you elaborate? I do not think there has been AR7 devices having non-8250 compatible UARTs out there thus this code is simply useful. What is meant by the comment is that the UART will be reported by Linux as ttyS0 .... is a Xscale. But this should not happen since there are only 8250 UARTs. > If you don't have a MAC address, either use random_ether_addr() or don't > bring up the network interface at all. Multiple interfaces with the same > MAC can cause chaos on a network to better avoid that. Thanks for spotting this. > > > +struct psp_env_chunk { > > + u8 num; > > + u8 ctrl; > > + u16 csum; > > + u8 len; > > + char data[11]; > > +} __attribute__ ((packed)); > > Afair historic versions of this code were totally polluted with > __attribute__((packed)). Thanks for cleaning that. > > Btw - Linux coding style: No space between __attribute__ and ((packed)). > > > +#include > > You get a false warning from checkpatch.pl here. Which probably means > either we should teach checkpatch.pl to check if is > actually including or rename to something > which would also help to avoid confusion. is not including so renaming sounds like a good solution. > > > +++ b/arch/mips/include/asm/mach-ar7/spaces.h > > You can cut down this header file to something like: > > /* Copyright blurb */ > #ifndef _ASM_AR7_SPACES_H > #define _ASM_AR7_SPACES_H > > /* > * This handles the memory map. > * We handle pages at KSEG0 for kernels with 32 bit address space. > */ > #define PAGE_OFFSET 0x94000000UL > #define PHYS_OFFSET 0x14000000UL > > #include Fixed, thanks ! -- Best regards, Florian Fainelli Email : florian@openwrt.org http://openwrt.org ------------------------------- From f.fainelli@gmail.com Thu Jun 4 10:26:11 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 04 Jun 2009 10:26:18 +0100 (WEST) Received: from mail-fx0-f223.google.com ([209.85.220.223]:51911 "EHLO mail-fx0-f223.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20022399AbZFDJ0L convert rfc822-to-8bit (ORCPT ); Thu, 4 Jun 2009 10:26:11 +0100 Received: by fxm23 with SMTP id 23so604503fxm.0 for ; Thu, 04 Jun 2009 02:26:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:sender:from:to:subject:date :user-agent:cc:references:in-reply-to:mime-version:content-type :content-transfer-encoding:content-disposition:message-id; bh=MFfUKYm5edvcUJ/yiH3WWV3tLwZPRvl6ENvsQiGvf6Y=; b=QmhmjmUmUy6eMvkN2717ugPb45jPq0Jf9ozNNuYzteVlHoiGxfJQcAmN8YEEK3Cg3f zQQ+5YsVniT4PpzB6dSPZijPacEhDWGkthSXhA3bkTzqq6Pkn4lw6nycNjqTFqxM7RAS W6QuY6ViXKLi5nT/1oVCJ0dnxwrB3QkrG7+xE= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:from:to:subject:date:user-agent:cc:references:in-reply-to :mime-version:content-type:content-transfer-encoding :content-disposition:message-id; b=r8RwTxLz1dgljiKWMesEXW8d/mUJ5XsNFKc8BJshk4HhXx/oXwjPSsLya4MPlKsN8x Xd2JV20IxoyAi/LTNqOzxhLlm1YqrLmzbNiKm+4WEkhAI/otyfYk+FAANK/9USP4DJRs yC3sTVwlSaZQZ0z+ES2d2CocdvX/Z0wwGWTBo= Received: by 10.103.172.9 with SMTP id z9mr1191723muo.58.1244107565779; Thu, 04 Jun 2009 02:26:05 -0700 (PDT) Received: from florian.lab.openpattern.org (lab.openpattern.org [82.240.16.241]) by mx.google.com with ESMTPS id 12sm3151521muq.53.2009.06.04.02.26.04 (version=TLSv1/SSLv3 cipher=RC4-MD5); Thu, 04 Jun 2009 02:26:04 -0700 (PDT) From: Florian Fainelli To: Manuel Lauss Subject: Re: [PATCH 0/5] Alchemy GPIO rewrite v6 Date: Thu, 4 Jun 2009 11:26:02 +0200 User-Agent: KMail/1.9.9 Cc: Linux-MIPS , Ralf Baechle , Manuel Lauss References: <1244045888-16259-1-git-send-email-manuel.lauss@gmail.com> In-Reply-To: <1244045888-16259-1-git-send-email-manuel.lauss@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8BIT Content-Disposition: inline Message-Id: <200906041126.02982.florian@openwrt.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23237 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips Hi Manuel, Le Wednesday 03 June 2009 18:18:03 Manuel Lauss, vous avez écrit : > Rewrite Alchemy GPIO support to be compatible with the Linux > GPIO framework, both with and without gpiolib. For a list of > justifications, see blurb in patch #2. > Patches #3-#5 replace a few open-coded GPIO accesses in the board > files with calls to the new gpio functions. > > Tested on DB1200 and a custom Au1200 platform. > > v6 - renamed gpio.[ch] to gpio-au1000.[ch], since this code only affects > pre-Au1300 chips. Should make integration of Au1300 GPIO a bit > easier. > v5 - fix gpio1 bug in inlined gpio_get_value() > v4 - GPIO2 shared interrupt management, styling. > v3 - fixed thinko in alchemy_gpio2_set_value (16->32 bit) > v2 - added gpio_to_irq and irq_to_gpio, some renaming. Thanks for this work ! For the whole serie you got my Acked-by: Florian Fainelli . Thanks ! > > Manuel Lauss (5): > Alchemy: remove unused au1000_gpio.h header > Alchemy: rewrite GPIO support. > Alchemy: mtx-1: use linux gpio api. > Alchemy: xxs1500: use linux gpio api. > Alchemy: devboards: convert to gpio calls. > > arch/mips/Makefile | 5 +- > arch/mips/alchemy/Kconfig | 19 +- > arch/mips/alchemy/common/Makefile | 11 +- > arch/mips/alchemy/common/gpio-au1000.c | 130 +++++ > arch/mips/alchemy/common/gpio.c | 201 ------- > arch/mips/alchemy/common/reset.c | 5 +- > arch/mips/alchemy/devboards/db1x00/board_setup.c | 8 +- > arch/mips/alchemy/devboards/pb1000/board_setup.c | 10 +- > arch/mips/alchemy/devboards/pb1100/board_setup.c | 3 +- > arch/mips/alchemy/devboards/pb1500/board_setup.c | 10 +- > arch/mips/alchemy/devboards/pm.c | 2 +- > arch/mips/alchemy/mtx-1/board_setup.c | 24 +- > arch/mips/alchemy/xxs1500/board_setup.c | 21 +- > arch/mips/include/asm/mach-au1x00/au1000_gpio.h | 56 -- > arch/mips/include/asm/mach-au1x00/gpio-au1000.h | 604 > ++++++++++++++++++++++ arch/mips/include/asm/mach-au1x00/gpio.h | > 35 +- > 16 files changed, 818 insertions(+), 326 deletions(-) > create mode 100644 arch/mips/alchemy/common/gpio-au1000.c > delete mode 100644 arch/mips/alchemy/common/gpio.c > delete mode 100644 arch/mips/include/asm/mach-au1x00/au1000_gpio.h > create mode 100644 arch/mips/include/asm/mach-au1x00/gpio-au1000.h -- Best regards, Florian Fainelli Email : florian@openwrt.org http://openwrt.org ------------------------------- From wuzhangjin@gmail.com Thu Jun 4 12:22:21 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 04 Jun 2009 12:22:29 +0100 (WEST) Received: from wa-out-1112.google.com ([209.85.146.179]:38642 "EHLO wa-out-1112.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20022501AbZFDLWV (ORCPT ); Thu, 4 Jun 2009 12:22:21 +0100 Received: by wa-out-1112.google.com with SMTP id n4so131048wag.0 for ; Thu, 04 Jun 2009 04:22:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:subject:from:reply-to:to:cc :in-reply-to:references:content-type:organization:date:message-id :mime-version:x-mailer:content-transfer-encoding; bh=UcshC3rICgxdT9spBiDk+uuyhsPEbloiy6NbT/IhYO8=; b=ai4kLTzqioSPiEz9kXRcYl3/2fdknA4JtwSt5CHVNeCk5Ok5l8/wznhTFZpyUiSs/c ExXBiSpFX5uXEnykPv4eN5hDBKDG4Wv5eITQd4ZlwtwZxY0hIFYC60g8hCRbmBU4AmV6 NI100uyCnDR+tkvlqJZydW1W2n7r3YdHgABfU= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=subject:from:reply-to:to:cc:in-reply-to:references:content-type :organization:date:message-id:mime-version:x-mailer :content-transfer-encoding; b=MDZQi+g/RrK2pXA8Q6Hx+qBk1Og7EOvWgR8dUFDGC/t9JDyDHL9rezioLsaargo+M/ m8Pjz3CtZf8AUk20/ztuRAoRwh55I2DSQ/Zrtjm8evWRg9j0PFacLdWnY+XVnuq5ioh2 BpqDLTOOQAHVKr0SNNmguAJDBUU4HtZ//Acos= Received: by 10.114.208.12 with SMTP id f12mr2239547wag.226.1244114539122; Thu, 04 Jun 2009 04:22:19 -0700 (PDT) Received: from ?192.168.2.239? ([202.201.14.140]) by mx.google.com with ESMTPS id l30sm2339331waf.35.2009.06.04.04.22.14 (version=TLSv1/SSLv3 cipher=RC4-MD5); Thu, 04 Jun 2009 04:22:18 -0700 (PDT) Subject: Re: [PATCH v2 2/6] mips dynamic function tracer support From: Wu Zhangjin Reply-To: wuzhangjin@gmail.com To: Steven Rostedt Cc: Wang Liming , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, Ralf Baechle , Ingo Molnar , Andrew Morton , Frederic Weisbecker , Thomas Gleixner , Nicholas Mc Guire In-Reply-To: References: <4A22281B.7020908@windriver.com> <4A26129E.1080008@windriver.com> Content-Type: text/plain Organization: DSLab, Lanzhou University, China Date: Thu, 04 Jun 2009 19:20:34 +0800 Message-Id: <1244114434.31146.48.camel@falcon> Mime-Version: 1.0 X-Mailer: Evolution 2.26.1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23238 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips hi, Steven > Note, PowerPC uses a trampoline from modules to kernel core. I think MIPS > just calls mcount differently. That is, it does a full 32bit address call > (64 bit for 64 bit archs?). Something like: > > lui v1, _mcount > addiu v1, v1, _mcount > jalr v1 > addiu sp, sp, -8 > > Then a nop would not do. Due to preemption, we can not modify more than > one line. But you could modify it to: > > b 1f > addiu v1, v1, _mcount > jalr v1 > addiu sp, sp, -8 > 1: > > Clobbering v1 should not be an issue since it is already used to store > _mcount. That is, we still do the addiu v1,v1,_mcount with that branch. > But v1 should be ignored. > sorry, I'm not clear what you said above, could you give more explanation on it, thanks! I think "jal _mcount" itself will not work in static and dynamic ftrace. something like what you described above should be used instead. perhaps a PATCH can be sent to gcc or we use some tricks in kernel. if we not use the method of modifying the kernel code in run time(avoid preemption?), can we link something as following to the modules: _mcount_trampoline: PTR_LA t0, _mcount jalr t0 and then we replace the original "jal _mcount" in every module to "jal _mcount_trampoline" with a perl script. this solution maybe work for static ftrace. does it? but in dynamic ftrace, when ftrace is enabled and set_filter_function is set, the place of filtered function will be substituted to "jal ftrace_caller", this will not work since ftrace_caller is a function like _mcount, which will not reached in modules. so, this ftrace_caller should be substituted to something like this: ftrace_caller_trampoline: PTR_LA t0, ftrace_caller jalr t0 and ftrace_caller_trampoline should be linked to modules too. or we substituted it to the above _mcount_trampoline, but change "PTR_LA t0, _mcount" to "PTR_LA t0, ftrace_caller". does this work? thanks! Wu Zhangjin From pavel@ucw.cz Thu Jun 4 13:05:57 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 04 Jun 2009 13:06:04 +0100 (WEST) Received: from atrey.karlin.mff.cuni.cz ([195.113.26.193]:60437 "EHLO atrey.karlin.mff.cuni.cz" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20022521AbZFDMF5 (ORCPT ); Thu, 4 Jun 2009 13:05:57 +0100 Received: by atrey.karlin.mff.cuni.cz (Postfix, from userid 512) id 70CC5F0210; Thu, 4 Jun 2009 14:05:55 +0200 (CEST) Date: Thu, 4 Jun 2009 14:05:49 +0200 From: Pavel Machek To: wuzhangjin@gmail.com Cc: linux-mips@linux-mips.org, ralf@linux-mips.org, Arnaud Patard , Atsushi Nemoto , Yan Hua , Zhang Fuxin , Wu Zhangjin , Hu Hongbing Subject: Re: [PATCH-v1] Hibernation Support in mips system Message-ID: <20090604120549.GD22897@elf.ucw.cz> References: <6b7278ff10d7c4f9d819792de8742f65147c6855.1244038584.git.wuzj@lemote.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <6b7278ff10d7c4f9d819792de8742f65147c6855.1244038584.git.wuzj@lemote.com> X-Warning: Reading this can be dangerous to your mental health. User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23239 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: pavel@ucw.cz Precedence: bulk X-list: linux-mips Hi! > @@ -0,0 +1,41 @@ > +/* > + * Suspend support specific for mips. > + * > + * Copyright (C) 2009 Lemote Inc. & Insititute of Computing Technology > + * Author: Hu Hongbing > + * Wu Zhangjin > + */ I guess GPL notice there would be nice... -- (english) http://www.livejournal.com/~pavelmachek (cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html From wuzhangjin@gmail.com Thu Jun 4 13:22:52 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 04 Jun 2009 13:22:58 +0100 (WEST) Received: from mail-pz0-f202.google.com ([209.85.222.202]:38089 "EHLO mail-pz0-f202.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20022539AbZFDMWw (ORCPT ); Thu, 4 Jun 2009 13:22:52 +0100 Received: by pzk40 with SMTP id 40so720987pzk.22 for ; Thu, 04 Jun 2009 05:22:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:subject:from:reply-to:to:cc :in-reply-to:references:content-type:organization:date:message-id :mime-version:x-mailer:content-transfer-encoding; bh=523EWA0viAsZK0AzIKbpvhbO0vJgWnkt6YQYcTsA5As=; b=t0nTRq3LrazpRKZS7uK1qyae/ctJAAiK0Pbo2gcadh5WnxwpzYPv5TfPJDfjEDHT8C u1n4G29CuxENwGbol1GULd/bAUXwzgwJf+ISQiMSqPEXJhi3lukQv3t6bCXQ8s7Qgerp 2Slc+qdVUZuYSvl+HsgkgLze2TqXsTd/iO/VQ= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=subject:from:reply-to:to:cc:in-reply-to:references:content-type :organization:date:message-id:mime-version:x-mailer :content-transfer-encoding; b=IWkAH1Phw50Xn9c889/PJYqKfnmZJLO9tUta68KuF8m5+7ch4wa3rDBWYM6vSlsrtQ LWmEQ4rlg+Q534WcA14DOub0+MvV25GA3JDXTBrTMuCzwDJ89RVoaBaE60ytN15f1vLq hDS0xsgv8FFdliwDPpRLLQ7uIfxufrMJ9urlA= Received: by 10.115.60.2 with SMTP id n2mr3386056wak.36.1244118165421; Thu, 04 Jun 2009 05:22:45 -0700 (PDT) Received: from ?192.168.2.239? ([202.201.14.140]) by mx.google.com with ESMTPS id l27sm10862576waf.20.2009.06.04.05.22.41 (version=TLSv1/SSLv3 cipher=RC4-MD5); Thu, 04 Jun 2009 05:22:44 -0700 (PDT) Subject: Re: [PATCH-v1] Hibernation Support in mips system From: Wu Zhangjin Reply-To: wuzhangjin@gmail.com To: Pavel Machek Cc: linux-mips@linux-mips.org, ralf@linux-mips.org, Arnaud Patard , Atsushi Nemoto , Yan Hua , Zhang Fuxin , Hu Hongbing In-Reply-To: <20090604120549.GD22897@elf.ucw.cz> References: <6b7278ff10d7c4f9d819792de8742f65147c6855.1244038584.git.wuzj@lemote.com> <20090604120549.GD22897@elf.ucw.cz> Content-Type: text/plain Organization: DSLab, Lanzhou University, China Date: Thu, 04 Jun 2009 20:22:31 +0800 Message-Id: <1244118151.32116.0.camel@falcon> Mime-Version: 1.0 X-Mailer: Evolution 2.26.1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23240 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips On Thu, 2009-06-04 at 14:05 +0200, Pavel Machek wrote: > Hi! > > > @@ -0,0 +1,41 @@ > > +/* > > + * Suspend support specific for mips. > > + * > > + * Copyright (C) 2009 Lemote Inc. & Insititute of Computing Technology > > + * Author: Hu Hongbing > > + * Wu Zhangjin > > + */ > > I guess GPL notice there would be nice... > sorry, forget it, will add later :-) thanks! Wu Zhangjin From wuzhangjin@gmail.com Thu Jun 4 13:27:31 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 04 Jun 2009 13:27:37 +0100 (WEST) Received: from mail-px0-f186.google.com ([209.85.216.186]:37803 "EHLO mail-px0-f186.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20022547AbZFDM1b (ORCPT ); Thu, 4 Jun 2009 13:27:31 +0100 Received: by pxi16 with SMTP id 16so732871pxi.22 for ; Thu, 04 Jun 2009 05:27:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer; bh=LiQ+r2nxtJGb3fQtTcDiBhqq3bo0UrPSEiO7cudGgF8=; b=BYwV6m1kATZgfwmYwKeQkX0IXxEHn1sruNozYgw7i6ErZrwIXJJ/1BTckIzZ2Js4/s eebwYh3B6Rf5J5/LtssakwtSo21XMQbsBDP0C4Rz5x7VL00eeRTI61gEe0DOabzJFhfM 3URXclboJ4Q2wjvHWi3I810K7qidPIj/mAf/A= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer; b=bFzVcFU9y61Ub6+Asx6k1v/iI0SEPxk252/saT9Sj/TVaiiLZLNDeGGx5E81CC8tZK uH2PdlAtA2fCBaP8naj4PaihZY/LM+v11akm/QGTXmcpjVP3H+mSU66sF+/wnid0n3dL C93PY15e2glu7OwN3SLio0PKRJ1eruQO/S4VM= Received: by 10.115.106.14 with SMTP id i14mr3431192wam.77.1244118443880; Thu, 04 Jun 2009 05:27:23 -0700 (PDT) Received: from localhost.localdomain ([202.201.14.140]) by mx.google.com with ESMTPS id n33sm3170041wag.32.2009.06.04.05.27.19 (version=TLSv1/SSLv3 cipher=RC4-MD5); Thu, 04 Jun 2009 05:27:23 -0700 (PDT) From: wuzhangjin@gmail.com To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: Arnaud Patard , Atsushi Nemoto , Yan Hua , Zhang Fuxin , Pavel Machek , Wu Zhangjin , Hu Hongbing Subject: [PATCH-v2] Hibernation Support in mips system Date: Thu, 4 Jun 2009 20:27:10 +0800 Message-Id: <9c9bc070f3c272c41254304537e9dec398245b94.1244118419.git.wuzj@lemote.com> X-Mailer: git-send-email 1.6.3.1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23241 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips From: Wu Zhangjin This is pulled from the to-mips branch of http://dev.lemote.com/code/linux_loongson, the original author is Hu Hongbing from www.lemote.com according to the feedback from Atsushi Nemoto, Arnaud Patard, Yanhua, Pavel Machek and Ralf Baechle. I removed the a0-a7,v1 registers saving/restoring, added cache/tlb flushing and fpu,dsp registers saving/restoring, and also tuned some coding style problem with the support of scripts/checkpatch.pl and added GPL notice. Reviewed-by: Pavel Machek Reviewed-by: Yan Hua Reviewed-by: Arnaud Patard Reviewed-by: Atsushi Nemoto Signed-off-by: Wu Zhangjin Signed-off-by: Hu Hongbing --- arch/mips/Kconfig | 3 ++ arch/mips/Makefile | 3 ++ arch/mips/include/asm/suspend.h | 5 ++- arch/mips/kernel/asm-offsets.c | 13 +++++++ arch/mips/power/Makefile | 1 + arch/mips/power/cpu.c | 43 ++++++++++++++++++++++++ arch/mips/power/hibernate.S | 70 +++++++++++++++++++++++++++++++++++++++ 7 files changed, 137 insertions(+), 1 deletions(-) create mode 100644 arch/mips/power/Makefile create mode 100644 arch/mips/power/cpu.c create mode 100644 arch/mips/power/hibernate.S diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index c7d1d08..4423d82 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -2128,6 +2128,9 @@ endmenu menu "Power management options" +config ARCH_HIBERNATION_POSSIBLE + def_bool y + config ARCH_SUSPEND_POSSIBLE def_bool y depends on !SMP diff --git a/arch/mips/Makefile b/arch/mips/Makefile index 6d39fdf..361a30d 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -685,6 +685,9 @@ core-y += arch/mips/kernel/ arch/mips/mm/ arch/mips/math-emu/ drivers-$(CONFIG_OPROFILE) += arch/mips/oprofile/ +# suspend and hibernation support +drivers-$(CONFIG_PM) += arch/mips/power/ + ifdef CONFIG_LASAT rom.bin rom.sw: vmlinux $(Q)$(MAKE) $(build)=arch/mips/lasat/image $@ diff --git a/arch/mips/include/asm/suspend.h b/arch/mips/include/asm/suspend.h index 2562f8f..294cdb6 100644 --- a/arch/mips/include/asm/suspend.h +++ b/arch/mips/include/asm/suspend.h @@ -1,6 +1,9 @@ #ifndef __ASM_SUSPEND_H #define __ASM_SUSPEND_H -/* Somewhen... Maybe :-) */ +static inline int arch_prepare_suspend(void) { return 0; } + +/* References to section boundaries */ +extern const void __nosave_begin, __nosave_end; #endif /* __ASM_SUSPEND_H */ diff --git a/arch/mips/kernel/asm-offsets.c b/arch/mips/kernel/asm-offsets.c index c901c22..8d006ec 100644 --- a/arch/mips/kernel/asm-offsets.c +++ b/arch/mips/kernel/asm-offsets.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include @@ -326,3 +327,15 @@ void output_octeon_cop2_state_defines(void) BLANK(); } #endif + +#ifdef CONFIG_HIBERNATION +void output_pbe_defines(void) +{ + COMMENT(" Linux struct pbe offsets. "); + OFFSET(PBE_ADDRESS, pbe, address); + OFFSET(PBE_ORIG_ADDRESS, pbe, orig_address); + OFFSET(PBE_NEXT, pbe, next); + DEFINE(PBE_SIZE, sizeof(struct pbe)); + BLANK(); +} +#endif diff --git a/arch/mips/power/Makefile b/arch/mips/power/Makefile new file mode 100644 index 0000000..73d56b8 --- /dev/null +++ b/arch/mips/power/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_HIBERNATION) += cpu.o hibernate.o diff --git a/arch/mips/power/cpu.c b/arch/mips/power/cpu.c new file mode 100644 index 0000000..505c1b2 --- /dev/null +++ b/arch/mips/power/cpu.c @@ -0,0 +1,43 @@ +/* + * Suspend support specific for mips. + * + * Distribute under GPLv2 + * + * Copyright (C) 2009 Lemote Inc. & Insititute of Computing Technology + * Author: Hu Hongbing + * Wu Zhangjin + */ +#include +#include +#include + +static u32 saved_status; +struct pt_regs saved_regs; + +void save_processor_state(void) +{ + saved_status = read_c0_status(); + + if (is_fpu_owner()) + save_fp(current); + if (cpu_has_dsp) + save_dsp(current); +} + +void restore_processor_state(void) +{ + write_c0_status(saved_status); + + if (is_fpu_owner()) + restore_fp(current); + if (cpu_has_dsp) + restore_dsp(current); +} + +int pfn_is_nosave(unsigned long pfn) +{ + unsigned long nosave_begin_pfn = PFN_DOWN(__pa(&__nosave_begin)); + unsigned long nosave_end_pfn = PFN_UP(__pa(&__nosave_end)); + + return (pfn >= nosave_begin_pfn) && (pfn < nosave_end_pfn); +} diff --git a/arch/mips/power/hibernate.S b/arch/mips/power/hibernate.S new file mode 100644 index 0000000..f7c78ff --- /dev/null +++ b/arch/mips/power/hibernate.S @@ -0,0 +1,70 @@ +/* + * Hibernation support specific for mips - temporary page tables + * + * Distribute under GPLv2 + * + * Copyright (C) 2009 Lemote Inc. & Insititute of Computing Technology + * Author: Hu Hongbing + * Wu Zhangjin + */ +#include +#include +#include + +.text +LEAF(swsusp_arch_suspend) + PTR_LA t0, saved_regs + PTR_S ra, PT_R31(t0) + PTR_S sp, PT_R29(t0) + PTR_S fp, PT_R30(t0) + PTR_S gp, PT_R28(t0) + PTR_S s0, PT_R16(t0) + PTR_S s1, PT_R17(t0) + PTR_S s2, PT_R18(t0) + PTR_S s3, PT_R19(t0) + PTR_S s4, PT_R20(t0) + PTR_S s5, PT_R21(t0) + PTR_S s6, PT_R22(t0) + PTR_S s7, PT_R23(t0) + j swsusp_save +END(swsusp_arch_suspend) + +LEAF(swsusp_arch_resume) + PTR_L t0, restore_pblist +0: + PTR_L t1, PBE_ADDRESS(t0) /* source */ + PTR_L t2, PBE_ORIG_ADDRESS(t0) /* destination */ + PTR_ADDIU t3, t1, _PAGE_SIZE +1: + REG_L t8, (t1) + REG_S t8, (t2) + PTR_ADDIU t1, t1, SZREG + PTR_ADDIU t2, t2, SZREG + bne t1, t3, 1b + PTR_L t0, PBE_NEXT(t0) + bnez t0, 0b + /* flush caches to make sure context is in memory */ + PTR_L t0, __flush_cache_all + jalr t0 + /* flush tlb entries */ +#ifdef CONFIG_SMP + jal flush_tlb_all +#else + jal local_flush_tlb_all +#endif + PTR_LA t0, saved_regs + PTR_L ra, PT_R31(t0) + PTR_L sp, PT_R29(t0) + PTR_L fp, PT_R30(t0) + PTR_L gp, PT_R28(t0) + PTR_L s0, PT_R16(t0) + PTR_L s1, PT_R17(t0) + PTR_L s2, PT_R18(t0) + PTR_L s3, PT_R19(t0) + PTR_L s4, PT_R20(t0) + PTR_L s5, PT_R21(t0) + PTR_L s6, PT_R22(t0) + PTR_L s7, PT_R23(t0) + PTR_LI v0, 0x0 + jr ra +END(swsusp_arch_resume) -- 1.6.0.4 From jaswinder@kernel.org Thu Jun 4 13:41:49 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 04 Jun 2009 13:41:56 +0100 (WEST) Received: from hera.kernel.org ([140.211.167.34]:58660 "EHLO hera.kernel.org" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20022565AbZFDMlt (ORCPT ); Thu, 4 Jun 2009 13:41:49 +0100 Received: from [192.168.1.220] (triband-del-59.180.95.155.bol.net.in [59.180.95.155] (may be forged)) (authenticated bits=0) by hera.kernel.org (8.14.2/8.13.8) with ESMTP id n54Cf0bc012138 (version=TLSv1/SSLv3 cipher=DHE-RSA-CAMELLIA256-SHA bits=256 verify=NO); Thu, 4 Jun 2009 12:41:03 GMT Subject: [PATCH 4/6] headers_check fix: mips, ioctl.h From: Jaswinder Singh Rajput To: Sam Ravnborg Cc: Ingo Molnar , Andrew Morton , LKML , Ralf Baechle , linux-mips , Michael Abbott In-Reply-To: <1244118714.5172.33.camel@ht.satnam> References: <1244118232.5172.26.camel@ht.satnam> <1244118476.5172.29.camel@ht.satnam> <1244118599.5172.31.camel@ht.satnam> <1244118714.5172.33.camel@ht.satnam> Content-Type: text/plain Date: Thu, 04 Jun 2009 18:05:49 +0530 Message-Id: <1244118949.5172.37.camel@ht.satnam> Mime-Version: 1.0 X-Mailer: Evolution 2.24.5 (2.24.5-1.fc10) Content-Transfer-Encoding: 7bit X-Virus-Scanned: ClamAV 0.93.3/9419/Thu Jun 4 02:47:46 2009 on hera.kernel.org X-Virus-Status: Clean Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23242 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jaswinder@kernel.org Precedence: bulk X-list: linux-mips Make ioctl.h compatible with asm-generic/ioctl.h and userspace fix the following 'make headers_check' warning: usr/include/asm-mips/ioctl.h:64: extern's make no sense in userspace Signed-off-by: Jaswinder Singh Rajput --- arch/mips/include/asm/ioctl.h | 4 ++++ 1 files changed, 4 insertions(+), 0 deletions(-) diff --git a/arch/mips/include/asm/ioctl.h b/arch/mips/include/asm/ioctl.h index 85067e2..9161634 100644 --- a/arch/mips/include/asm/ioctl.h +++ b/arch/mips/include/asm/ioctl.h @@ -60,12 +60,16 @@ ((nr) << _IOC_NRSHIFT) | \ ((size) << _IOC_SIZESHIFT)) +#ifdef __KERNEL__ /* provoke compile error for invalid uses of size argument */ extern unsigned int __invalid_size_argument_for_IOC; #define _IOC_TYPECHECK(t) \ ((sizeof(t) == sizeof(t[1]) && \ sizeof(t) < (1 << _IOC_SIZEBITS)) ? \ sizeof(t) : __invalid_size_argument_for_IOC) +#else +#define _IOC_TYPECHECK(t) (sizeof(t)) +#endif /* used to create numbers */ #define _IO(type, nr) _IOC(_IOC_NONE, (type), (nr), 0) -- 1.6.0.6 From ralf@h5.dl5rb.org.uk Thu Jun 4 13:53:32 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 04 Jun 2009 13:53:39 +0100 (WEST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:38642 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20022564AbZFDMxc (ORCPT ); Thu, 4 Jun 2009 13:53:32 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id n54CkfDP021159; Thu, 4 Jun 2009 13:46:41 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id n54CkVGV021157; Thu, 4 Jun 2009 13:46:31 +0100 Date: Thu, 4 Jun 2009 13:46:31 +0100 From: Ralf Baechle To: Jaswinder Singh Rajput Cc: Sam Ravnborg , Ingo Molnar , Andrew Morton , LKML , linux-mips , Michael Abbott Subject: Re: [PATCH 4/6] headers_check fix: mips, ioctl.h Message-ID: <20090604124631.GB19459@linux-mips.org> References: <1244118232.5172.26.camel@ht.satnam> <1244118476.5172.29.camel@ht.satnam> <1244118599.5172.31.camel@ht.satnam> <1244118714.5172.33.camel@ht.satnam> <1244118949.5172.37.camel@ht.satnam> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1244118949.5172.37.camel@ht.satnam> User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23243 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Thu, Jun 04, 2009 at 06:05:49PM +0530, Jaswinder Singh Rajput wrote: > Make ioctl.h compatible with asm-generic/ioctl.h and userspace > > fix the following 'make headers_check' warning: > > usr/include/asm-mips/ioctl.h:64: extern's make no sense in userspace > > Signed-off-by: Jaswinder Singh Rajput Thanks, applied. Ralf From wuzhangjin@gmail.com Thu Jun 4 13:58:53 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 04 Jun 2009 13:59:03 +0100 (WEST) Received: from mail-pz0-f202.google.com ([209.85.222.202]:47096 "EHLO mail-pz0-f202.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20022564AbZFDM6x (ORCPT ); Thu, 4 Jun 2009 13:58:53 +0100 Received: by pzk40 with SMTP id 40so735169pzk.22 for ; Thu, 04 Jun 2009 05:58:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer; bh=HrmCw4cN4+o10+KoetQWE4wpUiZre/7T0Ft7hpgNF9k=; b=PhPR0963D6gTRmM/77QquRWI/aac9uF2FjgCiMLpbzIdPFY8B4g/MWJLpYVCUvt0dq TtN2ejJlT4wWdLc0Clk4BipIvng2HgO0svRubjPliKA6oR40RwvtcNfVohCC3L2tTlbV oEgmBA93Y9Z/oSqqLMluAGyPh2pq+FVMYvfQ4= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer; b=j/SuDw0xk7sLOjn8axWPQqPZZ1wTBIGFXiUqpR/elYT4vHLHmkhzfWVaIW8qEK8Szc zY6hBjbDGtgDNEjGIZP2vWcx6EWwkxUJ3iO41F3IQVa9opbAqAoW2Lird6KG3C9KqOHb 6hvP+hH/GlmZsZhXIw4qOBCjlEP89W+dMr8A0= Received: by 10.114.134.1 with SMTP id h1mr2359837wad.63.1244120326315; Thu, 04 Jun 2009 05:58:46 -0700 (PDT) Received: from localhost.localdomain ([202.201.14.140]) by mx.google.com with ESMTPS id k37sm2596453waf.42.2009.06.04.05.58.41 (version=TLSv1/SSLv3 cipher=RC4-MD5); Thu, 04 Jun 2009 05:58:45 -0700 (PDT) From: wuzhangjin@gmail.com To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: Wu Zhangjin , Yan Hua , Philippe Vachon , Zhang Le , Zhang Fuxin , loongson-dev , Liu Junliang , Erwan Lerale Subject: [loongson-PATCH-v3 00/25] loongson-based machines support Date: Thu, 4 Jun 2009 20:58:15 +0800 Message-Id: X-Mailer: git-send-email 1.6.3.1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23244 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips From: Wu Zhangjin This patch series introduces support for loongson-based machines, including source code tuning for old fuloong-2e support, and the whole new support for fuloong-2f and yeeloong-2f. these three different machines are all made by Lemote (http://www.lemote.com). This -v3 patch series incorporates feedback I received on -v2 of these series, the changes include: * update it the latest linux-mips development git repo: git://dev.lemote.com/rt4ls.git linux-loongson-dev-to-ralf * add vmlinux.32 in .gitignore * split environment argument handling out of cmdline.c * split "Hibernation support in mips system" out of this patch series, and submmit it individually. * Simon Braunschmidt helped to test the SMI driver in a non-mips machine, works well. and according to his feedback, I enabled the vga command line argument to config the suitable screen resolution ratio dynamically. * enable halt command for yeeloong-7inch laptop * add a machtype command line argument to share the same kernel image file between yeeloong-7inch and yeeloong-8.9inch Wu Zhangjin (25): add vmlinux.32 in .gitignore fix-warning: incompatible argument type of pci_fixup_irqs fix-warning: incompatible argument type of virt_to_phys change the naming methods remove reference to bonito64.h divide the files to the smallest logic unit replace tons of magic numbers by understandable symbols clean up the early printk support for fuloong(2e) enable Real Time Clock Support for fuloong(2e) split the loongson-specific part out split env out of cmdline.c add basic loongson-2f support add basic fuloong(2f) support enable serial port support of loongson-based machines add basic yeeloong(2f) laptop support enable halt command for yeeloong-7inch laptop add a machtype kernel command line argument Add Siliconmotion 712 framebuffer driver define Loongson2F arch specific phys prot access Loongson2 specific OProfile driver flush posted write to irq CS5536 MFGPT as system clock source support Loongson2F cpufreq support add gcc 4.4 support for MIPS and loongson add default kernel config file for loongson-based machines .gitignore | 1 + Documentation/kernel-parameters.txt | 4 + arch/mips/Kconfig | 87 +- arch/mips/Makefile | 18 +- arch/mips/configs/fulong_defconfig | 1912 -------------- arch/mips/configs/fuloong2e_defconfig | 1977 +++++++++++++++ arch/mips/configs/fuloong2f_defconfig | 2630 +++++++++++++++++++ arch/mips/configs/yeeloong2f-7inch_defconfig | 1720 +++++++++++++ arch/mips/configs/yeeloong2f_defconfig | 2641 ++++++++++++++++++++ arch/mips/include/asm/compiler.h | 10 + arch/mips/include/asm/delay.h | 58 +- .../asm/mach-lemote/cpu-feature-overrides.h | 59 - arch/mips/include/asm/mach-lemote/dma-coherence.h | 66 - arch/mips/include/asm/mach-lemote/mc146818rtc.h | 36 - arch/mips/include/asm/mach-lemote/pci.h | 30 - arch/mips/include/asm/mach-lemote/war.h | 25 - arch/mips/include/asm/mach-loongson/clock.h | 64 + arch/mips/include/asm/mach-loongson/cmdline.h | 9 + .../asm/mach-loongson/cpu-feature-overrides.h | 59 + .../mips/include/asm/mach-loongson/cs5536/cs5536.h | 382 +++ .../asm/mach-loongson/cs5536/cs5536_mfgpt.h | 26 + .../include/asm/mach-loongson/cs5536/cs5536_pci.h | 174 ++ .../include/asm/mach-loongson/cs5536/cs5536_vsm.h | 59 + .../mips/include/asm/mach-loongson/dma-coherence.h | 70 + arch/mips/include/asm/mach-loongson/loongson.h | 319 +++ arch/mips/include/asm/mach-loongson/machine.h | 75 + arch/mips/include/asm/mach-loongson/machtype.h | 32 + arch/mips/include/asm/mach-loongson/mc146818rtc.h | 36 + arch/mips/include/asm/mach-loongson/mem.h | 31 + arch/mips/include/asm/mach-loongson/pci.h | 59 + arch/mips/include/asm/mach-loongson/war.h | 25 + arch/mips/include/asm/mips-boards/bonito64.h | 5 - arch/mips/include/asm/page.h | 5 +- arch/mips/include/asm/pci.h | 2 +- arch/mips/include/asm/pgtable.h | 13 + arch/mips/include/asm/txx9/generic.h | 2 +- arch/mips/include/asm/txx9/jmr3927.h | 2 +- arch/mips/include/asm/txx9/rbtx4927.h | 2 +- arch/mips/include/asm/txx9/rbtx4938.h | 2 +- arch/mips/include/asm/txx9/tx4938.h | 2 +- arch/mips/include/asm/txx9/tx4939.h | 4 +- arch/mips/kernel/Makefile | 1 + arch/mips/kernel/i8259.c | 2 + arch/mips/kernel/loongson2f_freq.c | 216 ++ arch/mips/lemote/lm2e/Makefile | 7 - arch/mips/lemote/lm2e/bonito-irq.c | 74 - arch/mips/lemote/lm2e/dbg_io.c | 146 -- arch/mips/lemote/lm2e/irq.c | 143 -- arch/mips/lemote/lm2e/mem.c | 23 - arch/mips/lemote/lm2e/pci.c | 97 - arch/mips/lemote/lm2e/prom.c | 97 - arch/mips/lemote/lm2e/reset.c | 41 - arch/mips/lemote/lm2e/setup.c | 111 - arch/mips/loongson/Kconfig | 135 + arch/mips/loongson/Makefile | 23 + arch/mips/loongson/common/Makefile | 37 + arch/mips/loongson/common/bonito-irq.c | 78 + arch/mips/loongson/common/clock.c | 166 ++ arch/mips/loongson/common/cmdline.c | 59 + arch/mips/loongson/common/cs5536/Makefile | 25 + arch/mips/loongson/common/cs5536/cs5536_acc.c | 156 ++ arch/mips/loongson/common/cs5536/cs5536_ehci.c | 166 ++ arch/mips/loongson/common/cs5536/cs5536_flash.c | 452 ++++ arch/mips/loongson/common/cs5536/cs5536_ide.c | 194 ++ arch/mips/loongson/common/cs5536/cs5536_isa.c | 376 +++ arch/mips/loongson/common/cs5536/cs5536_mfgpt.c | 257 ++ arch/mips/loongson/common/cs5536/cs5536_ohci.c | 168 ++ arch/mips/loongson/common/cs5536/cs5536_otg.c | 138 + arch/mips/loongson/common/cs5536/cs5536_pci.c | 126 + arch/mips/loongson/common/cs5536/cs5536_udc.c | 143 ++ arch/mips/loongson/common/early_printk.c | 28 + arch/mips/loongson/common/env.c | 59 + arch/mips/loongson/common/init.c | 54 + arch/mips/loongson/common/irq.c | 132 + arch/mips/loongson/common/machtype.c | 58 + arch/mips/loongson/common/mem.c | 116 + arch/mips/loongson/common/pci.c | 109 + arch/mips/loongson/common/reset.c | 38 + arch/mips/loongson/common/rtc.c | 54 + arch/mips/loongson/common/serial.c | 66 + arch/mips/loongson/common/setup.c | 74 + arch/mips/loongson/common/time.c | 34 + arch/mips/loongson/fuloong-2e/Makefile | 7 + arch/mips/loongson/fuloong-2e/irq.c | 58 + arch/mips/loongson/fuloong-2e/reset.c | 26 + arch/mips/loongson/fuloong-2f/Makefile | 5 + arch/mips/loongson/fuloong-2f/irq.c | 53 + arch/mips/loongson/fuloong-2f/reset.c | 65 + arch/mips/loongson/yeeloong-2f/Makefile | 5 + arch/mips/loongson/yeeloong-2f/init.c | 82 + arch/mips/loongson/yeeloong-2f/irq.c | 53 + arch/mips/loongson/yeeloong-2f/reset.c | 90 + arch/mips/oprofile/Makefile | 1 + arch/mips/oprofile/common.c | 5 + arch/mips/oprofile/op_model_loongson2.c | 186 ++ arch/mips/pci/Makefile | 4 +- arch/mips/pci/fixup-au1000.c | 2 +- arch/mips/pci/fixup-capcella.c | 2 +- arch/mips/pci/fixup-cobalt.c | 2 +- arch/mips/pci/fixup-emma2rh.c | 2 +- arch/mips/pci/fixup-excite.c | 2 +- arch/mips/pci/fixup-fuloong2e.c | 243 ++ arch/mips/pci/fixup-ip32.c | 2 +- arch/mips/pci/fixup-jmr3927.c | 2 +- arch/mips/pci/fixup-lemote2f.c | 171 ++ arch/mips/pci/fixup-lm2e.c | 242 -- arch/mips/pci/fixup-malta.c | 2 +- arch/mips/pci/fixup-mpc30x.c | 2 +- arch/mips/pci/fixup-pmcmsp.c | 2 +- arch/mips/pci/fixup-pnx8550.c | 2 +- arch/mips/pci/fixup-rbtx4927.c | 2 +- arch/mips/pci/fixup-rbtx4938.c | 2 +- arch/mips/pci/fixup-rc32434.c | 2 +- arch/mips/pci/fixup-sni.c | 2 +- arch/mips/pci/fixup-tb0219.c | 2 +- arch/mips/pci/fixup-tb0226.c | 2 +- arch/mips/pci/fixup-tb0287.c | 2 +- arch/mips/pci/fixup-wrppmc.c | 2 +- arch/mips/pci/fixup-yosemite.c | 2 +- arch/mips/pci/ops-bonito64.c | 19 +- arch/mips/pci/ops-loongson2.c | 213 ++ arch/mips/pci/pci-bcm1480.c | 2 +- arch/mips/pci/pci-bcm47xx.c | 2 +- arch/mips/pci/pci-ip27.c | 2 +- arch/mips/pci/pci-lasat.c | 2 +- arch/mips/pci/pci-sb1250.c | 2 +- arch/mips/pci/pci-tx4938.c | 2 +- arch/mips/pci/pci-tx4939.c | 4 +- arch/mips/txx9/generic/pci.c | 2 +- drivers/rtc/rtc-cmos.c | 8 +- drivers/video/Kconfig | 23 + drivers/video/Makefile | 1 + drivers/video/smi/Makefile | 8 + drivers/video/smi/smtc2d.c | 979 ++++++++ drivers/video/smi/smtc2d.h | 530 ++++ drivers/video/smi/smtcfb.c | 1138 +++++++++ drivers/video/smi/smtcfb.h | 793 ++++++ 137 files changed, 19054 insertions(+), 3224 deletions(-) delete mode 100644 arch/mips/configs/fulong_defconfig create mode 100644 arch/mips/configs/fuloong2e_defconfig create mode 100644 arch/mips/configs/fuloong2f_defconfig create mode 100644 arch/mips/configs/yeeloong2f-7inch_defconfig create mode 100644 arch/mips/configs/yeeloong2f_defconfig delete mode 100644 arch/mips/include/asm/mach-lemote/cpu-feature-overrides.h delete mode 100644 arch/mips/include/asm/mach-lemote/dma-coherence.h delete mode 100644 arch/mips/include/asm/mach-lemote/mc146818rtc.h delete mode 100644 arch/mips/include/asm/mach-lemote/pci.h delete mode 100644 arch/mips/include/asm/mach-lemote/war.h create mode 100644 arch/mips/include/asm/mach-loongson/clock.h create mode 100644 arch/mips/include/asm/mach-loongson/cmdline.h create mode 100644 arch/mips/include/asm/mach-loongson/cpu-feature-overrides.h create mode 100644 arch/mips/include/asm/mach-loongson/cs5536/cs5536.h create mode 100644 arch/mips/include/asm/mach-loongson/cs5536/cs5536_mfgpt.h create mode 100644 arch/mips/include/asm/mach-loongson/cs5536/cs5536_pci.h create mode 100644 arch/mips/include/asm/mach-loongson/cs5536/cs5536_vsm.h create mode 100644 arch/mips/include/asm/mach-loongson/dma-coherence.h create mode 100644 arch/mips/include/asm/mach-loongson/loongson.h create mode 100644 arch/mips/include/asm/mach-loongson/machine.h create mode 100644 arch/mips/include/asm/mach-loongson/machtype.h create mode 100644 arch/mips/include/asm/mach-loongson/mc146818rtc.h create mode 100644 arch/mips/include/asm/mach-loongson/mem.h create mode 100644 arch/mips/include/asm/mach-loongson/pci.h create mode 100644 arch/mips/include/asm/mach-loongson/war.h create mode 100644 arch/mips/kernel/loongson2f_freq.c delete mode 100644 arch/mips/lemote/lm2e/Makefile delete mode 100644 arch/mips/lemote/lm2e/bonito-irq.c delete mode 100644 arch/mips/lemote/lm2e/dbg_io.c delete mode 100644 arch/mips/lemote/lm2e/irq.c delete mode 100644 arch/mips/lemote/lm2e/mem.c delete mode 100644 arch/mips/lemote/lm2e/pci.c delete mode 100644 arch/mips/lemote/lm2e/prom.c delete mode 100644 arch/mips/lemote/lm2e/reset.c delete mode 100644 arch/mips/lemote/lm2e/setup.c create mode 100644 arch/mips/loongson/Kconfig create mode 100644 arch/mips/loongson/Makefile create mode 100644 arch/mips/loongson/common/Makefile create mode 100644 arch/mips/loongson/common/bonito-irq.c create mode 100644 arch/mips/loongson/common/clock.c create mode 100644 arch/mips/loongson/common/cmdline.c create mode 100644 arch/mips/loongson/common/cs5536/Makefile create mode 100644 arch/mips/loongson/common/cs5536/cs5536_acc.c create mode 100644 arch/mips/loongson/common/cs5536/cs5536_ehci.c create mode 100644 arch/mips/loongson/common/cs5536/cs5536_flash.c create mode 100644 arch/mips/loongson/common/cs5536/cs5536_ide.c create mode 100644 arch/mips/loongson/common/cs5536/cs5536_isa.c create mode 100644 arch/mips/loongson/common/cs5536/cs5536_mfgpt.c create mode 100644 arch/mips/loongson/common/cs5536/cs5536_ohci.c create mode 100644 arch/mips/loongson/common/cs5536/cs5536_otg.c create mode 100644 arch/mips/loongson/common/cs5536/cs5536_pci.c create mode 100644 arch/mips/loongson/common/cs5536/cs5536_udc.c create mode 100644 arch/mips/loongson/common/early_printk.c create mode 100644 arch/mips/loongson/common/env.c create mode 100644 arch/mips/loongson/common/init.c create mode 100644 arch/mips/loongson/common/irq.c create mode 100644 arch/mips/loongson/common/machtype.c create mode 100644 arch/mips/loongson/common/mem.c create mode 100644 arch/mips/loongson/common/pci.c create mode 100644 arch/mips/loongson/common/reset.c create mode 100644 arch/mips/loongson/common/rtc.c create mode 100644 arch/mips/loongson/common/serial.c create mode 100644 arch/mips/loongson/common/setup.c create mode 100644 arch/mips/loongson/common/time.c create mode 100644 arch/mips/loongson/fuloong-2e/Makefile create mode 100644 arch/mips/loongson/fuloong-2e/irq.c create mode 100644 arch/mips/loongson/fuloong-2e/reset.c create mode 100644 arch/mips/loongson/fuloong-2f/Makefile create mode 100644 arch/mips/loongson/fuloong-2f/irq.c create mode 100644 arch/mips/loongson/fuloong-2f/reset.c create mode 100644 arch/mips/loongson/yeeloong-2f/Makefile create mode 100644 arch/mips/loongson/yeeloong-2f/init.c create mode 100644 arch/mips/loongson/yeeloong-2f/irq.c create mode 100644 arch/mips/loongson/yeeloong-2f/reset.c create mode 100644 arch/mips/oprofile/op_model_loongson2.c create mode 100644 arch/mips/pci/fixup-fuloong2e.c create mode 100644 arch/mips/pci/fixup-lemote2f.c delete mode 100644 arch/mips/pci/fixup-lm2e.c create mode 100644 arch/mips/pci/ops-loongson2.c create mode 100644 drivers/video/smi/Makefile create mode 100644 drivers/video/smi/smtc2d.c create mode 100644 drivers/video/smi/smtc2d.h create mode 100644 drivers/video/smi/smtcfb.c create mode 100644 drivers/video/smi/smtcfb.h From wuzhangjin@gmail.com Thu Jun 4 14:00:05 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 04 Jun 2009 14:00:11 +0100 (WEST) Received: from mail-pz0-f202.google.com ([209.85.222.202]:41739 "EHLO mail-pz0-f202.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20022564AbZFDNAE (ORCPT ); Thu, 4 Jun 2009 14:00:04 +0100 Received: by pzk40 with SMTP id 40so735719pzk.22 for ; Thu, 04 Jun 2009 05:59:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer:in-reply-to:references; bh=u+nsltYDdnjfVtXQla0aXV0FlWOpEWy6ZNdPEoKIHu8=; b=sL36pUegjyla43qnQT5SYApxI2fvXfWtAME5edpbAYTGN/lF6mUQvLVCrZEHG7Sem4 YBg4G8mrht919Thz9ct/I7tY8q8PExz2vwVADLzFRVSdTp3kFSALOwjbhUrArz4n7Xqa 8lrvPJOVR8WqEfKSae6s4T1h4gZJuQye9rLrI= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; b=T81wV7JjxHGNOKELO/LSIfYpntK/nA6jdrFHigF5Xl//CYG8dIRB5L/odaaVPeTcq2 HEprnDWyLrwwCuQmA7bRMhKqh5Vqkwp2iAUSTGiiPtZl3VHKrNp3B+kap0iuhlHUpZJ+ jZC8CSzPclcigDFqpYIumFT4lkZ8xYzI0uJ0Q= Received: by 10.114.67.17 with SMTP id p17mr2466266waa.163.1244120397266; Thu, 04 Jun 2009 05:59:57 -0700 (PDT) Received: from localhost.localdomain ([202.201.14.140]) by mx.google.com with ESMTPS id l38sm10940983waf.3.2009.06.04.05.59.52 (version=TLSv1/SSLv3 cipher=RC4-MD5); Thu, 04 Jun 2009 05:59:56 -0700 (PDT) From: wuzhangjin@gmail.com To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: Wu Zhangjin , Yan Hua , Philippe Vachon , Zhang Le , Zhang Fuxin , loongson-dev , Liu Junliang , Erwan Lerale Subject: [loongson-PATCH-v3 01/25] add vmlinux.32 in .gitignore Date: Thu, 4 Jun 2009 20:59:44 +0800 Message-Id: X-Mailer: git-send-email 1.6.3.1 In-Reply-To: References: Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23245 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips From: Wu Zhangjin Signed-off-by: Wu Zhangjin --- .gitignore | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/.gitignore b/.gitignore index 51bd99d..8ceeffb 100644 --- a/.gitignore +++ b/.gitignore @@ -32,6 +32,7 @@ tags TAGS vmlinux +vmlinux.32 System.map Module.markers Module.symvers -- 1.6.0.4 From wuzhangjin@gmail.com Thu Jun 4 14:00:30 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 04 Jun 2009 14:00:37 +0100 (WEST) Received: from mail-pz0-f202.google.com ([209.85.222.202]:41739 "EHLO mail-pz0-f202.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20022574AbZFDNAR (ORCPT ); Thu, 4 Jun 2009 14:00:17 +0100 Received: by mail-pz0-f202.google.com with SMTP id 40so735719pzk.22 for ; Thu, 04 Jun 2009 06:00:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer:in-reply-to:references:mime-version :content-type:content-transfer-encoding; bh=ZJwrRb8S/y+Zc02i8yW6T8PKOr2idXTX/2vGMdzfG0k=; b=pMB4ZagOuXeEfEw1hK+VEMx4fOvsekc4EFrNEYEROeD4pF04Fnr9QwNY/0vZXVSGl1 EwjSX5mHPUJlQQgA7KyWxq/kxbIfjIBXkJRXcuwbGpVditFcwfqigEin9qcnQXoQxF6T Ba/uDhNnuCZh9gVNMdSIBzh3l//DNO05w1Iac= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :mime-version:content-type:content-transfer-encoding; b=YffHOTgmNncJaiB2w5jJz7VPrE0lrWGsxfyLcd7ISPJaiEiunFOJePWWhmtjYtwsHO 2902F3q/d8laskImn6mwotG4ehgWM6oH0OaidyEyArjmXC2Na5iG/2aTszQhyrmNCmet /jGfCpr73D79nekF0s1BugVhGycqx5J9aWy+8= Received: by 10.114.185.12 with SMTP id i12mr2506120waf.178.1244120415052; Thu, 04 Jun 2009 06:00:15 -0700 (PDT) Received: from localhost.localdomain ([202.201.14.140]) by mx.google.com with ESMTPS id l27sm10687982waf.55.2009.06.04.06.00.08 (version=TLSv1/SSLv3 cipher=RC4-MD5); Thu, 04 Jun 2009 06:00:13 -0700 (PDT) From: wuzhangjin@gmail.com To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: Wu Zhangjin , Yan Hua , Philippe Vachon , Zhang Le , Zhang Fuxin , loongson-dev , Liu Junliang , Erwan Lerale , Wu Zhangjin Subject: [loongson-PATCH-v3 02/25] fix-warning: incompatible argument type of pci_fixup_irqs Date: Thu, 4 Jun 2009 21:00:01 +0800 Message-Id: X-Mailer: git-send-email 1.6.3.1 In-Reply-To: References: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23246 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips From: Wu Zhangjin arch/mips/pci/pci.c:160: warning: passing argument 2 of ‘pci_fixup_irqs’ from incompatible pointer type include/linux/pci.h: void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *), int (*)(struct pci_dev *, u8, u8)); arch/mips/pci/pci.c:160: pci_fixup_irqs(pci_common_swizzle, pcibios_map_irq); arch/mips/include/asm/pci.h: extern int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin); arch/mips/pci/fixup-malta.c int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) Reviewed-by: David Daney Signed-off-by: Wu Zhangjin --- arch/mips/include/asm/pci.h | 2 +- arch/mips/include/asm/txx9/generic.h | 2 +- arch/mips/include/asm/txx9/jmr3927.h | 2 +- arch/mips/include/asm/txx9/rbtx4927.h | 2 +- arch/mips/include/asm/txx9/rbtx4938.h | 2 +- arch/mips/include/asm/txx9/tx4938.h | 2 +- arch/mips/include/asm/txx9/tx4939.h | 4 ++-- arch/mips/pci/fixup-au1000.c | 2 +- arch/mips/pci/fixup-capcella.c | 2 +- arch/mips/pci/fixup-cobalt.c | 2 +- arch/mips/pci/fixup-emma2rh.c | 2 +- arch/mips/pci/fixup-excite.c | 2 +- arch/mips/pci/fixup-ip32.c | 2 +- arch/mips/pci/fixup-jmr3927.c | 2 +- arch/mips/pci/fixup-lm2e.c | 2 +- arch/mips/pci/fixup-malta.c | 2 +- arch/mips/pci/fixup-mpc30x.c | 2 +- arch/mips/pci/fixup-pmcmsp.c | 2 +- arch/mips/pci/fixup-pnx8550.c | 2 +- arch/mips/pci/fixup-rbtx4927.c | 2 +- arch/mips/pci/fixup-rbtx4938.c | 2 +- arch/mips/pci/fixup-rc32434.c | 2 +- arch/mips/pci/fixup-sni.c | 2 +- arch/mips/pci/fixup-tb0219.c | 2 +- arch/mips/pci/fixup-tb0226.c | 2 +- arch/mips/pci/fixup-tb0287.c | 2 +- arch/mips/pci/fixup-wrppmc.c | 2 +- arch/mips/pci/fixup-yosemite.c | 2 +- arch/mips/pci/pci-bcm1480.c | 2 +- arch/mips/pci/pci-bcm47xx.c | 2 +- arch/mips/pci/pci-ip27.c | 2 +- arch/mips/pci/pci-lasat.c | 2 +- arch/mips/pci/pci-sb1250.c | 2 +- arch/mips/pci/pci-tx4938.c | 2 +- arch/mips/pci/pci-tx4939.c | 4 ++-- arch/mips/txx9/generic/pci.c | 2 +- 36 files changed, 38 insertions(+), 38 deletions(-) diff --git a/arch/mips/include/asm/pci.h b/arch/mips/include/asm/pci.h index 053e463..42b895b 100644 --- a/arch/mips/include/asm/pci.h +++ b/arch/mips/include/asm/pci.h @@ -56,7 +56,7 @@ extern void register_pci_controller(struct pci_controller *hose); /* * board supplied pci irq fixup routine */ -extern int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin); +extern int pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin); /* Can be used to override the logic in pci_scan_bus for skipping diff --git a/arch/mips/include/asm/txx9/generic.h b/arch/mips/include/asm/txx9/generic.h index 9cde009..166da5a 100644 --- a/arch/mips/include/asm/txx9/generic.h +++ b/arch/mips/include/asm/txx9/generic.h @@ -37,7 +37,7 @@ struct txx9_board_vec { void (*arch_init)(void); void (*device_init)(void); #ifdef CONFIG_PCI - int (*pci_map_irq)(const struct pci_dev *dev, u8 slot, u8 pin); + int (*pci_map_irq)(struct pci_dev *dev, u8 slot, u8 pin); #endif }; extern struct txx9_board_vec *txx9_board_vec; diff --git a/arch/mips/include/asm/txx9/jmr3927.h b/arch/mips/include/asm/txx9/jmr3927.h index a409c44..8f37def 100644 --- a/arch/mips/include/asm/txx9/jmr3927.h +++ b/arch/mips/include/asm/txx9/jmr3927.h @@ -175,6 +175,6 @@ void jmr3927_prom_init(void); void jmr3927_irq_setup(void); struct pci_dev; -int jmr3927_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin); +int jmr3927_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin); #endif /* __ASM_TXX9_JMR3927_H */ diff --git a/arch/mips/include/asm/txx9/rbtx4927.h b/arch/mips/include/asm/txx9/rbtx4927.h index b2adab3..0168a87 100644 --- a/arch/mips/include/asm/txx9/rbtx4927.h +++ b/arch/mips/include/asm/txx9/rbtx4927.h @@ -87,6 +87,6 @@ void rbtx4927_prom_init(void); void rbtx4927_irq_setup(void); struct pci_dev; -int rbtx4927_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin); +int rbtx4927_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin); #endif /* __ASM_TXX9_RBTX4927_H */ diff --git a/arch/mips/include/asm/txx9/rbtx4938.h b/arch/mips/include/asm/txx9/rbtx4938.h index 9f0441a..705435b 100644 --- a/arch/mips/include/asm/txx9/rbtx4938.h +++ b/arch/mips/include/asm/txx9/rbtx4938.h @@ -140,6 +140,6 @@ void rbtx4938_prom_init(void); void rbtx4938_irq_setup(void); struct pci_dev; -int rbtx4938_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin); +int rbtx4938_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin); #endif /* __ASM_TXX9_RBTX4938_H */ diff --git a/arch/mips/include/asm/txx9/tx4938.h b/arch/mips/include/asm/txx9/tx4938.h index cd8bc20..e104c95 100644 --- a/arch/mips/include/asm/txx9/tx4938.h +++ b/arch/mips/include/asm/txx9/tx4938.h @@ -287,7 +287,7 @@ int tx4938_report_pciclk(void); void tx4938_report_pci1clk(void); int tx4938_pciclk66_setup(void); struct pci_dev; -int tx4938_pcic1_map_irq(const struct pci_dev *dev, u8 slot); +int tx4938_pcic1_map_irq(struct pci_dev *dev, u8 slot); void tx4938_setup_pcierr_irq(void); void tx4938_irq_init(void); void tx4938_mtd_init(int ch); diff --git a/arch/mips/include/asm/txx9/tx4939.h b/arch/mips/include/asm/txx9/tx4939.h index f02c50b..b7af10e 100644 --- a/arch/mips/include/asm/txx9/tx4939.h +++ b/arch/mips/include/asm/txx9/tx4939.h @@ -534,8 +534,8 @@ void tx4939_ethaddr_init(unsigned char *addr0, unsigned char *addr1); int tx4939_report_pciclk(void); void tx4939_report_pci1clk(void); struct pci_dev; -int tx4939_pcic1_map_irq(const struct pci_dev *dev, u8 slot); -int tx4939_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin); +int tx4939_pcic1_map_irq(struct pci_dev *dev, u8 slot); +int tx4939_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin); void tx4939_setup_pcierr_irq(void); void tx4939_irq_init(void); int tx4939_irq(void); diff --git a/arch/mips/pci/fixup-au1000.c b/arch/mips/pci/fixup-au1000.c index e2ddfc4..15b8ecc 100644 --- a/arch/mips/pci/fixup-au1000.c +++ b/arch/mips/pci/fixup-au1000.c @@ -31,7 +31,7 @@ extern char irq_tab_alchemy[][5]; -int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) +int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) { return irq_tab_alchemy[slot][pin]; } diff --git a/arch/mips/pci/fixup-capcella.c b/arch/mips/pci/fixup-capcella.c index 1416bca..1e53075 100644 --- a/arch/mips/pci/fixup-capcella.c +++ b/arch/mips/pci/fixup-capcella.c @@ -38,7 +38,7 @@ static char irq_tab_capcella[][5] __initdata = { [14] = { -1, INTA, INTB, INTC, INTD } }; -int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) +int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) { return irq_tab_capcella[slot][pin]; } diff --git a/arch/mips/pci/fixup-cobalt.c b/arch/mips/pci/fixup-cobalt.c index 9553b14..63d1af3 100644 --- a/arch/mips/pci/fixup-cobalt.c +++ b/arch/mips/pci/fixup-cobalt.c @@ -175,7 +175,7 @@ static char irq_tab_raq2[] __initdata = { [COBALT_PCICONF_ETH1] = ETH1_IRQ }; -int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) +int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) { if (cobalt_board_id <= COBALT_BRD_ID_QUBE1) return irq_tab_qube1[slot]; diff --git a/arch/mips/pci/fixup-emma2rh.c b/arch/mips/pci/fixup-emma2rh.c index fba5aad..04c28f3 100644 --- a/arch/mips/pci/fixup-emma2rh.c +++ b/arch/mips/pci/fixup-emma2rh.c @@ -88,7 +88,7 @@ static void __devinit emma2rh_pci_host_fixup(struct pci_dev *dev) DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_EMMA2RH, emma2rh_pci_host_fixup); -int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) +int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) { return irq_map[slot][pin]; } diff --git a/arch/mips/pci/fixup-excite.c b/arch/mips/pci/fixup-excite.c index cd64d9f..1da696d 100644 --- a/arch/mips/pci/fixup-excite.c +++ b/arch/mips/pci/fixup-excite.c @@ -21,7 +21,7 @@ #include #include -int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) +int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) { if (pin == 0) return -1; diff --git a/arch/mips/pci/fixup-ip32.c b/arch/mips/pci/fixup-ip32.c index 190fffd..3e66b0a 100644 --- a/arch/mips/pci/fixup-ip32.c +++ b/arch/mips/pci/fixup-ip32.c @@ -39,7 +39,7 @@ static char irq_tab_mace[][5] __initdata = { * irqs. I suppose a device without a pin A will thank us for doing it * right if there exists such a broken piece of crap. */ -int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) +int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) { return irq_tab_mace[slot][pin]; } diff --git a/arch/mips/pci/fixup-jmr3927.c b/arch/mips/pci/fixup-jmr3927.c index 0f10695..e6ff40e 100644 --- a/arch/mips/pci/fixup-jmr3927.c +++ b/arch/mips/pci/fixup-jmr3927.c @@ -31,7 +31,7 @@ #include #include -int __init jmr3927_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) +int __init jmr3927_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) { unsigned char irq = pin; diff --git a/arch/mips/pci/fixup-lm2e.c b/arch/mips/pci/fixup-lm2e.c index e18ae4f..08de000 100644 --- a/arch/mips/pci/fixup-lm2e.c +++ b/arch/mips/pci/fixup-lm2e.c @@ -36,7 +36,7 @@ /* South bridge slot number is set by the pci probe process */ static u8 sb_slot = 5; -int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) +int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) { int irq = 0; diff --git a/arch/mips/pci/fixup-malta.c b/arch/mips/pci/fixup-malta.c index 0f48498..bf2c41d 100644 --- a/arch/mips/pci/fixup-malta.c +++ b/arch/mips/pci/fixup-malta.c @@ -36,7 +36,7 @@ static char irq_tab[][5] __initdata = { {0, PCID, PCIA, PCIB, PCIC } /* 21: PCI Slot 4 */ }; -int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) +int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) { int virq; virq = irq_tab[slot][pin]; diff --git a/arch/mips/pci/fixup-mpc30x.c b/arch/mips/pci/fixup-mpc30x.c index 5911596..3c9ae41 100644 --- a/arch/mips/pci/fixup-mpc30x.c +++ b/arch/mips/pci/fixup-mpc30x.c @@ -34,7 +34,7 @@ static const int irq_tab_mpc30x[] __initdata = { [29] = MQ200_IRQ, }; -int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) +int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) { if (slot == 30) return internal_func_irqs[PCI_FUNC(dev->devfn)]; diff --git a/arch/mips/pci/fixup-pmcmsp.c b/arch/mips/pci/fixup-pmcmsp.c index 65735b1..0026121 100644 --- a/arch/mips/pci/fixup-pmcmsp.c +++ b/arch/mips/pci/fixup-pmcmsp.c @@ -202,7 +202,7 @@ int pcibios_plat_dev_init(struct pci_dev *dev) * RETURNS: IRQ number * ****************************************************************************/ -int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) +int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) { #if !defined(CONFIG_PMC_MSP7120_GW) && !defined(CONFIG_PMC_MSP7120_EVAL) printk(KERN_WARNING "PCI: unknown board, no PCI IRQs assigned.\n"); diff --git a/arch/mips/pci/fixup-pnx8550.c b/arch/mips/pci/fixup-pnx8550.c index 96857ac..50546da 100644 --- a/arch/mips/pci/fixup-pnx8550.c +++ b/arch/mips/pci/fixup-pnx8550.c @@ -45,7 +45,7 @@ void __init pcibios_fixup(void) /* nothing to do here */ } -int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) +int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) { return pnx8550_irq_tab[slot][pin]; } diff --git a/arch/mips/pci/fixup-rbtx4927.c b/arch/mips/pci/fixup-rbtx4927.c index 321db26..3f1df0e 100644 --- a/arch/mips/pci/fixup-rbtx4927.c +++ b/arch/mips/pci/fixup-rbtx4927.c @@ -36,7 +36,7 @@ #include #include -int __init rbtx4927_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) +int __init rbtx4927_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) { unsigned char irq = pin; diff --git a/arch/mips/pci/fixup-rbtx4938.c b/arch/mips/pci/fixup-rbtx4938.c index a80579a..a5e0a41 100644 --- a/arch/mips/pci/fixup-rbtx4938.c +++ b/arch/mips/pci/fixup-rbtx4938.c @@ -13,7 +13,7 @@ #include #include -int __init rbtx4938_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) +int __init rbtx4938_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) { int irq = tx4938_pcic1_map_irq(dev, slot); diff --git a/arch/mips/pci/fixup-rc32434.c b/arch/mips/pci/fixup-rc32434.c index 3d86823..68f8537 100644 --- a/arch/mips/pci/fixup-rc32434.c +++ b/arch/mips/pci/fixup-rc32434.c @@ -37,7 +37,7 @@ static int __devinitdata irq_map[2][12] = { {0, 0, 1, 3, 0, 2, 1, 3, 0, 2, 1, 3} }; -int __devinit pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) +int __devinit pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) { int irq = 0; diff --git a/arch/mips/pci/fixup-sni.c b/arch/mips/pci/fixup-sni.c index 5c8a79b..4ce73be 100644 --- a/arch/mips/pci/fixup-sni.c +++ b/arch/mips/pci/fixup-sni.c @@ -130,7 +130,7 @@ static inline int is_rm300_revd(void) return (csmsr & 0xa0) == 0x20; } -int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) +int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) { switch (sni_brd_type) { case SNI_BRD_PCI_TOWER_CPLUS: diff --git a/arch/mips/pci/fixup-tb0219.c b/arch/mips/pci/fixup-tb0219.c index ed87733..0f8d31b 100644 --- a/arch/mips/pci/fixup-tb0219.c +++ b/arch/mips/pci/fixup-tb0219.c @@ -23,7 +23,7 @@ #include -int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) +int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) { int irq = -1; diff --git a/arch/mips/pci/fixup-tb0226.c b/arch/mips/pci/fixup-tb0226.c index e3eedf4..c9e7cb4 100644 --- a/arch/mips/pci/fixup-tb0226.c +++ b/arch/mips/pci/fixup-tb0226.c @@ -23,7 +23,7 @@ #include #include -int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) +int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) { int irq = -1; diff --git a/arch/mips/pci/fixup-tb0287.c b/arch/mips/pci/fixup-tb0287.c index 267ab3d..fbe6bcb 100644 --- a/arch/mips/pci/fixup-tb0287.c +++ b/arch/mips/pci/fixup-tb0287.c @@ -22,7 +22,7 @@ #include -int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) +int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) { unsigned char bus; int irq = -1; diff --git a/arch/mips/pci/fixup-wrppmc.c b/arch/mips/pci/fixup-wrppmc.c index 3d27754..3357c13 100644 --- a/arch/mips/pci/fixup-wrppmc.c +++ b/arch/mips/pci/fixup-wrppmc.c @@ -25,7 +25,7 @@ static char pci_irq_tab[PCI_SLOT_MAXNR][5] __initdata = { [6] = {0, WRPPMC_PCI_INTA_IRQ, 0, 0, 0}, }; -int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) +int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) { return pci_irq_tab[slot][pin]; } diff --git a/arch/mips/pci/fixup-yosemite.c b/arch/mips/pci/fixup-yosemite.c index fdafb13..81d77a5 100644 --- a/arch/mips/pci/fixup-yosemite.c +++ b/arch/mips/pci/fixup-yosemite.c @@ -26,7 +26,7 @@ #include #include -int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) +int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) { if (pin == 0) return -1; diff --git a/arch/mips/pci/pci-bcm1480.c b/arch/mips/pci/pci-bcm1480.c index a9060c7..41e691a 100644 --- a/arch/mips/pci/pci-bcm1480.c +++ b/arch/mips/pci/pci-bcm1480.c @@ -74,7 +74,7 @@ static inline void WRITECFG32(u32 addr, u32 data) *(u32 *)(cfg_space + (addr & ~3)) = data; } -int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) +int pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) { if (pin == 0) return -1; diff --git a/arch/mips/pci/pci-bcm47xx.c b/arch/mips/pci/pci-bcm47xx.c index bea9b6c..1f3721d 100644 --- a/arch/mips/pci/pci-bcm47xx.c +++ b/arch/mips/pci/pci-bcm47xx.c @@ -26,7 +26,7 @@ #include #include -int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) +int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) { return 0; } diff --git a/arch/mips/pci/pci-ip27.c b/arch/mips/pci/pci-ip27.c index dda6f20..a2a5b5d 100644 --- a/arch/mips/pci/pci-ip27.c +++ b/arch/mips/pci/pci-ip27.c @@ -141,7 +141,7 @@ int __cpuinit bridge_probe(nasid_t nasid, int widget_id, int masterwid) * A given PCI device, in general, should be able to intr any of the cpus * on any one of the hubs connected to its xbow. */ -int __devinit pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) +int __devinit pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) { return 0; } diff --git a/arch/mips/pci/pci-lasat.c b/arch/mips/pci/pci-lasat.c index a98e543..149d503 100644 --- a/arch/mips/pci/pci-lasat.c +++ b/arch/mips/pci/pci-lasat.c @@ -61,7 +61,7 @@ arch_initcall(lasat_pci_setup); #define LASAT_IRQ_PCIC (LASAT_IRQ_BASE + 7) #define LASAT_IRQ_PCID (LASAT_IRQ_BASE + 8) -int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) +int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) { switch (slot) { case 1: diff --git a/arch/mips/pci/pci-sb1250.c b/arch/mips/pci/pci-sb1250.c index bf63959..bd26d4a 100644 --- a/arch/mips/pci/pci-sb1250.c +++ b/arch/mips/pci/pci-sb1250.c @@ -84,7 +84,7 @@ static inline void WRITECFG32(u32 addr, u32 data) *(u32 *) (cfg_space + (addr & ~3)) = data; } -int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) +int pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) { return dev->irq; } diff --git a/arch/mips/pci/pci-tx4938.c b/arch/mips/pci/pci-tx4938.c index 1ea257b..0a2467d 100644 --- a/arch/mips/pci/pci-tx4938.c +++ b/arch/mips/pci/pci-tx4938.c @@ -114,7 +114,7 @@ int __init tx4938_pciclk66_setup(void) return pciclk; } -int __init tx4938_pcic1_map_irq(const struct pci_dev *dev, u8 slot) +int __init tx4938_pcic1_map_irq(struct pci_dev *dev, u8 slot) { if (get_tx4927_pcicptr(dev->bus->sysdata) == tx4938_pcic1ptr) { switch (slot) { diff --git a/arch/mips/pci/pci-tx4939.c b/arch/mips/pci/pci-tx4939.c index 5fecf1c..b39f9a5 100644 --- a/arch/mips/pci/pci-tx4939.c +++ b/arch/mips/pci/pci-tx4939.c @@ -50,7 +50,7 @@ void __init tx4939_report_pci1clk(void) ((pciclk + 50000) / 100000) % 10); } -int __init tx4939_pcic1_map_irq(const struct pci_dev *dev, u8 slot) +int __init tx4939_pcic1_map_irq(struct pci_dev *dev, u8 slot) { if (get_tx4927_pcicptr(dev->bus->sysdata) == tx4939_pcic1ptr) { switch (slot) { @@ -70,7 +70,7 @@ int __init tx4939_pcic1_map_irq(const struct pci_dev *dev, u8 slot) return -1; } -int __init tx4939_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) +int __init tx4939_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin) { int irq = tx4939_pcic1_map_irq(dev, slot); diff --git a/arch/mips/txx9/generic/pci.c b/arch/mips/txx9/generic/pci.c index 7b637a7..27104f7 100644 --- a/arch/mips/txx9/generic/pci.c +++ b/arch/mips/txx9/generic/pci.c @@ -382,7 +382,7 @@ int pcibios_plat_dev_init(struct pci_dev *dev) return 0; } -int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) +int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) { return txx9_board_vec->pci_map_irq(dev, slot, pin); } -- 1.6.0.4 From wuzhangjin@gmail.com Thu Jun 4 14:00:55 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 04 Jun 2009 14:01:02 +0100 (WEST) Received: from mail-pz0-f202.google.com ([209.85.222.202]:41739 "EHLO mail-pz0-f202.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20022564AbZFDNAe (ORCPT ); Thu, 4 Jun 2009 14:00:34 +0100 Received: by mail-pz0-f202.google.com with SMTP id 40so735719pzk.22 for ; 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Thu, 04 Jun 2009 06:00:31 -0700 (PDT) From: wuzhangjin@gmail.com To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: Wu Zhangjin , Yan Hua , Philippe Vachon , Zhang Le , Zhang Fuxin , loongson-dev , Liu Junliang , Erwan Lerale , Wu Zhangjin Subject: [loongson-PATCH-v3 03/25] fix-warning: incompatible argument type of virt_to_phys Date: Thu, 4 Jun 2009 21:00:19 +0800 Message-Id: X-Mailer: git-send-email 1.6.3.1 In-Reply-To: References: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23247 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips From: Wu Zhangjin mm/page_alloc.c:1760: warning: passing argument 1 of ‘virt_to_phys’ makes pointer from integer without a cast mm/page_alloc.c:1760 ... unsigned long addr; ... split_page(virt_to_page(addr), order); arch/mips/include/asm/page.h #define virt_to_page(kaddr) pfn_to_page(PFN_DOWN(virt_to_phys(kaddr))) #define virt_addr_valid(kaddr) pfn_valid(PFN_DOWN(virt_to_phys(kaddr))) arch/mips/include/asm/io.h static inline unsigned long virt_to_phys(volatile const void *address) Signed-off-by: Wu Zhangjin --- arch/mips/include/asm/page.h | 5 +++-- 1 files changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/mips/include/asm/page.h b/arch/mips/include/asm/page.h index 9f946e4..d148e87 100644 --- a/arch/mips/include/asm/page.h +++ b/arch/mips/include/asm/page.h @@ -179,8 +179,9 @@ typedef struct { unsigned long pgprot; } pgprot_t; #endif -#define virt_to_page(kaddr) pfn_to_page(PFN_DOWN(virt_to_phys(kaddr))) -#define virt_addr_valid(kaddr) pfn_valid(PFN_DOWN(virt_to_phys(kaddr))) +#define virt_to_page(kaddr) \ + pfn_to_page(PFN_DOWN(virt_to_phys((void *)kaddr))) +#define virt_addr_valid(kaddr) pfn_valid(PFN_DOWN(virt_to_phys((void *)kaddr))) #define VM_DATA_DEFAULT_FLAGS (VM_READ | VM_WRITE | VM_EXEC | \ VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC) -- 1.6.0.4 From wuzhangjin@gmail.com Thu Jun 4 14:04:32 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 04 Jun 2009 14:04:39 +0100 (WEST) Received: from mail-pz0-f202.google.com ([209.85.222.202]:62921 "EHLO mail-pz0-f202.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20022589AbZFDNEc (ORCPT ); Thu, 4 Jun 2009 14:04:32 +0100 Received: by pzk40 with SMTP id 40so737962pzk.22 for ; Thu, 04 Jun 2009 06:04:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer:in-reply-to:references; bh=5LJy2u/B9XZZatTdOC+nd4ombWxEbIz63Ze4jV1wZpg=; b=p1uDqxQI/8YjQLLBf8QpZp90War1hrnWMXlfum4K4WyVFMoj4bisrcP7UMC3lcaI4N XcDAUYr639lSdmqjwlDshBxLfrLedH3FgKe8VG/M4ovqg/YHIcsT/OZkM8n8TKKgCuQn UN6udz3VbmFoVbsbJyoy9u0N3SXHx3rbEUtqQ= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; b=Z2Wg1QfC3ZFbl/M/YIStfzH7SrWlIsnJlvpyar1vxSiLfuLXfntLIhlbLNBo2axTt0 K1DIZfG11d1qBW5HLIozr9of+ugBVJVE5k1fWQnsa5qqJxmN/1PVDx87XGKB3FrpeVsg PUhJjingd8dvDZNf2IufTmu8XpOnKElrFfVJU= Received: by 10.114.182.15 with SMTP id e15mr3407642waf.148.1244120665005; Thu, 04 Jun 2009 06:04:25 -0700 (PDT) Received: from localhost.localdomain ([202.201.14.140]) by mx.google.com with ESMTPS id l38sm11181358waf.38.2009.06.04.06.04.18 (version=TLSv1/SSLv3 cipher=RC4-MD5); Thu, 04 Jun 2009 06:04:24 -0700 (PDT) From: wuzhangjin@gmail.com To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: Wu Zhangjin , Yan Hua , Philippe Vachon , Zhang Le , Zhang Fuxin , loongson-dev , Liu Junliang , Erwan Lerale , Arnaud Patard , Wu Zhangjin Subject: [loongson-PATCH-v3 05/25] remove reference to bonito64.h Date: Thu, 4 Jun 2009 21:04:11 +0800 Message-Id: <5223517b96e55194c2e7ed14a7377dfe8dcd15bb.1244120575.git.wuzj@lemote.com> X-Mailer: git-send-email 1.6.3.1 In-Reply-To: References: Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23248 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips From: Wu Zhangjin in loongson2e, there is an internal bonito64 compatiable north bridge, but in loongson2f and the later loongson revisions, this will change a lot, so, remove reference from bonito64.h and create a new loongson.h is better. Signed-off-by: Wu Zhangjin --- arch/mips/include/asm/mach-loongson/loongson.h | 194 +++++++++++++++++++++++- arch/mips/include/asm/mach-loongson/pci.h | 2 +- arch/mips/include/asm/mips-boards/bonito64.h | 5 - arch/mips/loongson/fuloong-2e/bonito-irq.c | 10 +- arch/mips/loongson/fuloong-2e/irq.c | 23 ++-- arch/mips/loongson/fuloong-2e/pci.c | 15 +- arch/mips/pci/Makefile | 2 +- arch/mips/pci/fixup-fuloong2e.c | 5 +- arch/mips/pci/ops-bonito64.c | 7 - arch/mips/pci/ops-fuloong2e.c | 160 +++++++++++++++++++ 10 files changed, 382 insertions(+), 41 deletions(-) create mode 100644 arch/mips/pci/ops-fuloong2e.c diff --git a/arch/mips/include/asm/mach-loongson/loongson.h b/arch/mips/include/asm/mach-loongson/loongson.h index 18ebef1..26308b5 100644 --- a/arch/mips/include/asm/mach-loongson/loongson.h +++ b/arch/mips/include/asm/mach-loongson/loongson.h @@ -1,7 +1,19 @@ /* - * loongson-specific header file + * Copyright (c) 2009 Philippe Vachon + * + * Copyright (C) 2009 Lemote, Inc. & Institute of Computing Technology + * Author: Wu Zhangjin + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * */ +#ifndef __LOONGSON_H +#define __LOONGSON_H + /* loongson internal northbridge initialization */ extern void bonito_irq_init(void); @@ -12,3 +24,183 @@ extern unsigned long memsize, highmemsize; /* loongson-based machines specific reboot setup */ extern void loongson_reboot_setup(void); +#define LOONGSON_REG(x) \ + (*(u32 *)((char *)CKSEG1ADDR(LOONGSON_REG_BASE) + (x))) +#define LOONGSON_IRQ_BASE 32 + +#define LOONGSON_FLASH_BASE 0x1c000000 +#define LOONGSON_FLASH_SIZE 0x02000000 /* 32M */ +#define LOONGSON_FLASH_TOP (LOONGSON_FLASH_BASE+LOONGSON_FLASH_SIZE-1) + +#define LOONGSON_LIO0_BASE 0x1e000000 +#define LOONGSON_LIO0_SIZE 0x01C00000 /* 28M */ +#define LOONGSON_LIO0_TOP (LOONGSON_LIO0_BASE+LOONGSON_LIO0_SIZE-1) + +#define LOONGSON_BOOT_BASE 0x1fc00000 +#define LOONGSON_BOOT_SIZE 0x00100000 /* 1M */ +#define LOONGSON_BOOT_TOP (LOONGSON_BOOT_BASE+LOONGSON_BOOT_SIZE-1) +#define LOONGSON_REG_BASE 0x1fe00000 +#define LOONGSON_REG_SIZE 0x00100000 /* 256Bytes + 256Bytes + ??? */ +#define LOONGSON_REG_TOP (LOONGSON_REG_BASE+LOONGSON_REG_SIZE-1) + +#define LOONGSON_LIO1_BASE 0x1ff00000 +#define LOONGSON_LIO1_SIZE 0x00100000 /* 1M */ +#define LOONGSON_LIO1_TOP (LOONGSON_LIO1_BASE+LOONGSON_LIO1_SIZE-1) + +#define LOONGSON_PCILO0_BASE 0x10000000 +#define LOONGSON_PCILO1_BASE 0x14000000 +#define LOONGSON_PCILO2_BASE 0x18000000 +#define LOONGSON_PCILO_BASE LOONGSON_PCILO0_BASE +#define LOONGSON_PCILO_SIZE 0x0c000000 /* 64M * 3 */ +#define LOONGSON_PCILO_TOP (LOONGSON_PCILO0_BASE+LOONGSON_PCILO_SIZE-1) + +#define LOONGSON_PCICFG_BASE 0x1fe80000 +#define LOONGSON_PCICFG_SIZE 0x00000800 /* 2K */ +#define LOONGSON_PCICFG_TOP (LOONGSON_PCICFG_BASE+LOONGSON_PCICFG_SIZE-1) +#define LOONGSON_PCIIO_BASE 0x1fd00000 +#define LOONGSON_PCIIO_SIZE 0x00100000 /* 1M */ +#define LOONGSON_PCIIO_TOP (LOONGSON_PCIIO_BASE+LOONGSON_PCIIO_SIZE-1) + +/* Loongson Register Bases */ + +#define LOONGSON_PCICONFIGBASE 0x00 +#define LOONGSON_REGBASE 0x100 + +/* PCI Configuration Registers */ + +#define LOONGSON_PCI_REG(x) LOONGSON_REG(LOONGSON_PCICONFIGBASE + (x)) +#define LOONGSON_PCIDID LOONGSON_PCI_REG(0x00) +#define LOONGSON_PCICMD LOONGSON_PCI_REG(0x04) +#define LOONGSON_PCICLASS LOONGSON_PCI_REG(0x08) +#define LOONGSON_PCILTIMER LOONGSON_PCI_REG(0x0c) +#define LOONGSON_PCIBASE0 LOONGSON_PCI_REG(0x10) +#define LOONGSON_PCIBASE1 LOONGSON_PCI_REG(0x14) +#define LOONGSON_PCIBASE2 LOONGSON_PCI_REG(0x18) +#define LOONGSON_PCIBASE3 LOONGSON_PCI_REG(0x1c) +#define LOONGSON_PCIBASE4 LOONGSON_PCI_REG(0x20) +#define LOONGSON_PCIEXPRBASE LOONGSON_PCI_REG(0x30) +#define LOONGSON_PCIINT LOONGSON_PCI_REG(0x3c) + +#define LOONGSON_PCI_ISR4C LOONGSON_PCI_REG(0x4c) + +#define LOONGSON_PCICMD_PERR_CLR 0x80000000 +#define LOONGSON_PCICMD_SERR_CLR 0x40000000 +#define LOONGSON_PCICMD_MABORT_CLR 0x20000000 +#define LOONGSON_PCICMD_MTABORT_CLR 0x10000000 +#define LOONGSON_PCICMD_TABORT_CLR 0x08000000 +#define LOONGSON_PCICMD_MPERR_CLR 0x01000000 +#define LOONGSON_PCICMD_PERRRESPEN 0x00000040 +#define LOONGSON_PCICMD_ASTEPEN 0x00000080 +#define LOONGSON_PCICMD_SERREN 0x00000100 +#define LOONGSON_PCILTIMER_BUSLATENCY 0x0000ff00 +#define LOONGSON_PCILTIMER_BUSLATENCY_SHIFT 8 + +/* Loongson h/w Configuration */ + +#define LOONGSON_GENCFG_OFFSET 0x4 +#define LOONGSON_GENCFG LOONGSON_REG(LOONGSON_REGBASE + LOONGSON_GENCFG_OFFSET) + +#define LOONGSON_GENCFG_DEBUGMODE 0x00000001 +#define LOONGSON_GENCFG_SNOOPEN 0x00000002 +#define LOONGSON_GENCFG_CPUSELFRESET 0x00000004 + +#define LOONGSON_GENCFG_FORCE_IRQA 0x00000008 +#define LOONGSON_GENCFG_IRQA_ISOUT 0x00000010 +#define LOONGSON_GENCFG_IRQA_FROM_INT1 0x00000020 +#define LOONGSON_GENCFG_BYTESWAP 0x00000040 + +#define LOONGSON_GENCFG_UNCACHED 0x00000080 +#define LOONGSON_GENCFG_PREFETCHEN 0x00000100 +#define LOONGSON_GENCFG_WBEHINDEN 0x00000200 +#define LOONGSON_GENCFG_CACHEALG 0x00000c00 +#define LOONGSON_GENCFG_CACHEALG_SHIFT 10 +#define LOONGSON_GENCFG_PCIQUEUE 0x00001000 +#define LOONGSON_GENCFG_CACHESTOP 0x00002000 +#define LOONGSON_GENCFG_MSTRBYTESWAP 0x00004000 +#define LOONGSON_GENCFG_BUSERREN 0x00008000 +#define LOONGSON_GENCFG_NORETRYTIMEOUT 0x00010000 +#define LOONGSON_GENCFG_SHORTCOPYTIMEOUT 0x00020000 + +/* PCI address map control */ + +#define LOONGSON_PCIMAP LOONGSON_REG(LOONGSON_REGBASE + 0x10) +#define LOONGSON_PCIMEMBASECFG LOONGSON_REG(LOONGSON_REGBASE + 0x14) +#define LOONGSON_PCIMAP_CFG LOONGSON_REG(LOONGSON_REGBASE + 0x18) + +/* GPIO Regs - r/w */ + +#define LOONGSON_GPIODATA LOONGSON_REG(LOONGSON_REGBASE + 0x1c) +#define LOONGSON_GPIOIE LOONGSON_REG(LOONGSON_REGBASE + 0x20) + +/* ICU Configuration Regs - r/w */ + +#define LOONGSON_INTEDGE LOONGSON_REG(LOONGSON_REGBASE + 0x24) +#define LOONGSON_INTSTEER LOONGSON_REG(LOONGSON_REGBASE + 0x28) +#define LOONGSON_INTPOL LOONGSON_REG(LOONGSON_REGBASE + 0x2c) + +/* ICU Enable Regs - IntEn & IntISR are r/o. */ + +#define LOONGSON_INTENSET LOONGSON_REG(LOONGSON_REGBASE + 0x30) +#define LOONGSON_INTENCLR LOONGSON_REG(LOONGSON_REGBASE + 0x34) +#define LOONGSON_INTEN LOONGSON_REG(LOONGSON_REGBASE + 0x38) +#define LOONGSON_INTISR LOONGSON_REG(LOONGSON_REGBASE + 0x3c) + +/* ICU */ +#define LOONGSON_ICU_MBOXES 0x0000000f +#define LOONGSON_ICU_MBOXES_SHIFT 0 +#define LOONGSON_ICU_DMARDY 0x00000010 +#define LOONGSON_ICU_DMAEMPTY 0x00000020 +#define LOONGSON_ICU_COPYRDY 0x00000040 +#define LOONGSON_ICU_COPYEMPTY 0x00000080 +#define LOONGSON_ICU_COPYERR 0x00000100 +#define LOONGSON_ICU_PCIIRQ 0x00000200 +#define LOONGSON_ICU_MASTERERR 0x00000400 +#define LOONGSON_ICU_SYSTEMERR 0x00000800 +#define LOONGSON_ICU_DRAMPERR 0x00001000 +#define LOONGSON_ICU_RETRYERR 0x00002000 +#define LOONGSON_ICU_GPIOS 0x01ff0000 +#define LOONGSON_ICU_GPIOS_SHIFT 16 +#define LOONGSON_ICU_GPINS 0x7e000000 +#define LOONGSON_ICU_GPINS_SHIFT 25 +#define LOONGSON_ICU_MBOX(N) (1<<(LOONGSON_ICU_MBOXES_SHIFT+(N))) +#define LOONGSON_ICU_GPIO(N) (1<<(LOONGSON_ICU_GPIOS_SHIFT+(N))) +#define LOONGSON_ICU_GPIN(N) (1<<(LOONGSON_ICU_GPINS_SHIFT+(N))) + +/* PCI prefetch window base & mask */ + +#define LOONGSON_MEM_WIN_BASE_L LOONGSON_REG(LOONGSON_REGBASE + 0x40) +#define LOONGSON_MEM_WIN_BASE_H LOONGSON_REG(LOONGSON_REGBASE + 0x44) +#define LOONGSON_MEM_WIN_MASK_L LOONGSON_REG(LOONGSON_REGBASE + 0x48) +#define LOONGSON_MEM_WIN_MASK_H LOONGSON_REG(LOONGSON_REGBASE + 0x4c) + +/* PCI_Hit*_Sel_* */ + +#define LOONGSON_PCI_HIT0_SEL_L LOONGSON_REG(LOONGSON_REGBASE + 0x50) +#define LOONGSON_PCI_HIT0_SEL_H LOONGSON_REG(LOONGSON_REGBASE + 0x54) +#define LOONGSON_PCI_HIT1_SEL_L LOONGSON_REG(LOONGSON_REGBASE + 0x58) +#define LOONGSON_PCI_HIT1_SEL_H LOONGSON_REG(LOONGSON_REGBASE + 0x5c) +#define LOONGSON_PCI_HIT2_SEL_L LOONGSON_REG(LOONGSON_REGBASE + 0x60) +#define LOONGSON_PCI_HIT2_SEL_H LOONGSON_REG(LOONGSON_REGBASE + 0x64) + +/* PXArb Config & Status */ + +#define LOONGSON_PXARB_CFG LOONGSON_REG(LOONGSON_REGBASE + 0x68) +#define LOONGSON_PXARB_STATUS LOONGSON_REG(LOONGSON_REGBASE + 0x6c) + +/* Chip Config */ +#define LOONGSON_CHIPCFG0 LOONGSON_REG(LOONGSON_REGBASE + 0x80) + +/* pcimap */ + +#define LOONGSON_PCIMAP_PCIMAP_LO0 0x0000003f +#define LOONGSON_PCIMAP_PCIMAP_LO0_SHIFT 0 +#define LOONGSON_PCIMAP_PCIMAP_LO1 0x00000fc0 +#define LOONGSON_PCIMAP_PCIMAP_LO1_SHIFT 6 +#define LOONGSON_PCIMAP_PCIMAP_LO2 0x0003f000 +#define LOONGSON_PCIMAP_PCIMAP_LO2_SHIFT 12 +#define LOONGSON_PCIMAP_PCIMAP_2 0x00040000 +#define LOONGSON_PCIMAP_WIN(WIN, ADDR) \ + ((((ADDR)>>26) & LOONGSON_PCIMAP_PCIMAP_LO0) << ((WIN)*6)) + +#endif /* __LOONGSON_H */ + diff --git a/arch/mips/include/asm/mach-loongson/pci.h b/arch/mips/include/asm/mach-loongson/pci.h index e685096..9a351be 100644 --- a/arch/mips/include/asm/mach-loongson/pci.h +++ b/arch/mips/include/asm/mach-loongson/pci.h @@ -22,7 +22,7 @@ #ifndef _LOONGSON_PCI_H_ #define _LOONGSON_PCI_H_ -extern struct pci_ops bonito64_pci_ops; +extern struct pci_ops loongson_pci_ops; #define LOONGSON2E_PCI_MEM_START 0x14000000UL #define LOONGSON2E_PCI_MEM_END 0x1fffffffUL diff --git a/arch/mips/include/asm/mips-boards/bonito64.h b/arch/mips/include/asm/mips-boards/bonito64.h index a576ce0..d14e2ad 100644 --- a/arch/mips/include/asm/mips-boards/bonito64.h +++ b/arch/mips/include/asm/mips-boards/bonito64.h @@ -26,11 +26,6 @@ /* offsets from base register */ #define BONITO(x) (x) -#elif defined(CONFIG_LEMOTE_FULOONG2E) - -#define BONITO(x) (*(volatile u32 *)((char *)CKSEG1ADDR(BONITO_REG_BASE) + (x))) -#define BONITO_IRQ_BASE 32 - #else /* diff --git a/arch/mips/loongson/fuloong-2e/bonito-irq.c b/arch/mips/loongson/fuloong-2e/bonito-irq.c index 5adf373..91b9c08 100644 --- a/arch/mips/loongson/fuloong-2e/bonito-irq.c +++ b/arch/mips/loongson/fuloong-2e/bonito-irq.c @@ -34,18 +34,18 @@ #include #include -#include +#include static inline void bonito_irq_enable(unsigned int irq) { - BONITO_INTENSET = (1 << (irq - BONITO_IRQ_BASE)); + LOONGSON_INTENSET = (1 << (irq - LOONGSON_IRQ_BASE)); mmiowb(); } static inline void bonito_irq_disable(unsigned int irq) { - BONITO_INTENCLR = (1 << (irq - BONITO_IRQ_BASE)); + LOONGSON_INTENCLR = (1 << (irq - LOONGSON_IRQ_BASE)); mmiowb(); } @@ -66,8 +66,8 @@ void bonito_irq_init(void) { u32 i; - for (i = BONITO_IRQ_BASE; i < BONITO_IRQ_BASE + 32; i++) + for (i = LOONGSON_IRQ_BASE; i < LOONGSON_IRQ_BASE + 32; i++) set_irq_chip_and_handler(i, &bonito_irq_type, handle_level_irq); - setup_irq(BONITO_IRQ_BASE + 10, &dma_timeout_irqaction); + setup_irq(LOONGSON_IRQ_BASE + 10, &dma_timeout_irqaction); } diff --git a/arch/mips/loongson/fuloong-2e/irq.c b/arch/mips/loongson/fuloong-2e/irq.c index 1b0d491..20030c0 100644 --- a/arch/mips/loongson/fuloong-2e/irq.c +++ b/arch/mips/loongson/fuloong-2e/irq.c @@ -32,7 +32,6 @@ #include #include #include -#include #include @@ -45,21 +44,21 @@ static void bonito_irqdispatch(void) int i; /* workaround the IO dma problem: let cpu looping to allow DMA finish */ - int_status = BONITO_INTISR; + int_status = LOONGSON_INTISR; if (int_status & (1 << 10)) { while (int_status & (1 << 10)) { udelay(1); - int_status = BONITO_INTISR; + int_status = LOONGSON_INTISR; } } /* Get pending sources, masked by current enables */ - int_status = BONITO_INTISR & BONITO_INTEN; + int_status = LOONGSON_INTISR & LOONGSON_INTEN; if (int_status != 0) { i = __ffs(int_status); int_status &= ~(1 << i); - do_IRQ(BONITO_IRQ_BASE + i); + do_IRQ(LOONGSON_IRQ_BASE + i); } } @@ -103,15 +102,15 @@ void __init arch_init_irq(void) local_irq_disable(); /* most bonito irq should be level triggered */ - BONITO_INTEDGE = BONITO_ICU_SYSTEMERR | BONITO_ICU_MASTERERR | - BONITO_ICU_RETRYERR | BONITO_ICU_MBOXES; - BONITO_INTSTEER = 0; + LOONGSON_INTEDGE = LOONGSON_ICU_SYSTEMERR | LOONGSON_ICU_MASTERERR | + LOONGSON_ICU_RETRYERR | LOONGSON_ICU_MBOXES; + LOONGSON_INTSTEER = 0; /* * Mask out all interrupt by writing "1" to all bit position in * the interrupt reset reg. */ - BONITO_INTENCLR = ~0; + LOONGSON_INTENCLR = ~0; /* init all controller * 0-15 ------> i8259 interrupt @@ -125,10 +124,10 @@ void __init arch_init_irq(void) bonito_irq_init(); /* - printk("GPIODATA=%x, GPIOIE=%x\n", BONITO_GPIODATA, BONITO_GPIOIE); + printk("GPIODATA=%x, GPIOIE=%x\n", LOONGSON_GPIODATA, LOONGSON_GPIOIE); printk("INTEN=%x, INTSET=%x, INTCLR=%x, INTISR=%x\n", - BONITO_INTEN, BONITO_INTENSET, - BONITO_INTENCLR, BONITO_INTISR); + LOONGSON_INTEN, LOONGSON_INTENSET, + LOONGSON_INTENCLR, LOONGSON_INTISR); */ /* bonito irq at IP2 */ diff --git a/arch/mips/loongson/fuloong-2e/pci.c b/arch/mips/loongson/fuloong-2e/pci.c index 4c4bc07..1d81110 100644 --- a/arch/mips/loongson/fuloong-2e/pci.c +++ b/arch/mips/loongson/fuloong-2e/pci.c @@ -29,7 +29,8 @@ #include #include #include -#include + +#include #include static struct resource loongson2e_pci_mem_resource = { @@ -47,7 +48,7 @@ static struct resource loongson2e_pci_io_resource = { }; static struct pci_controller loongson2e_pci_controller = { - .pci_ops = &bonito64_pci_ops, + .pci_ops = &loongson_pci_ops, .io_resource = &loongson2e_pci_io_resource, .mem_resource = &loongson2e_pci_mem_resource, .mem_offset = 0x00000000UL, @@ -64,17 +65,17 @@ static void __init ict_pcimap(void) * pcimap: bit18,pcimap_2; bit[17-12],lo2;bit[11-6],lo1;bit[5-0],lo0 */ /* 1,00 0110 ,0001 01,00 0000 */ - BONITO_PCIMAP = 0x46140; + LOONGSON_PCIMAP = 0x46140; /* 1, 00 0010, 0000,01, 00 0000 */ - /* BONITO_PCIMAP = 0x42040; */ + /* LOONGSON_PCIMAP = 0x42040; */ /* * PCI to local mapping: [2G,2G+256M] -> [0,256M] */ - BONITO_PCIBASE0 = 0x80000000; - BONITO_PCIBASE1 = 0x00800000; - BONITO_PCIBASE2 = 0x90000000; + LOONGSON_PCIBASE0 = 0x80000000; + LOONGSON_PCIBASE1 = 0x00800000; + LOONGSON_PCIBASE2 = 0x90000000; } diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile index 1c66fc0..a0cc238 100644 --- a/arch/mips/pci/Makefile +++ b/arch/mips/pci/Makefile @@ -26,7 +26,7 @@ obj-$(CONFIG_MIPS_COBALT) += fixup-cobalt.o obj-$(CONFIG_SOC_AU1500) += fixup-au1000.o ops-au1000.o obj-$(CONFIG_SOC_AU1550) += fixup-au1000.o ops-au1000.o obj-$(CONFIG_SOC_PNX8550) += fixup-pnx8550.o ops-pnx8550.o -obj-$(CONFIG_LEMOTE_FULOONG2E) += fixup-fuloong2e.o ops-bonito64.o +obj-$(CONFIG_LEMOTE_FULOONG2E) += fixup-fuloong2e.o ops-fuloong2e.o obj-$(CONFIG_MIPS_MALTA) += fixup-malta.o obj-$(CONFIG_PMC_MSP7120_GW) += fixup-pmcmsp.o ops-pmcmsp.o obj-$(CONFIG_PMC_MSP7120_EVAL) += fixup-pmcmsp.o ops-pmcmsp.o diff --git a/arch/mips/pci/fixup-fuloong2e.c b/arch/mips/pci/fixup-fuloong2e.c index bd26008..0e3c5de 100644 --- a/arch/mips/pci/fixup-fuloong2e.c +++ b/arch/mips/pci/fixup-fuloong2e.c @@ -31,7 +31,8 @@ */ #include #include -#include + +#include /* South bridge slot number is set by the pci probe process */ static u8 sb_slot = 5; @@ -53,7 +54,7 @@ int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin) break; } } else { - irq = BONITO_IRQ_BASE + 25 + pin; + irq = LOONGSON_IRQ_BASE + 25 + pin; } return irq; diff --git a/arch/mips/pci/ops-bonito64.c b/arch/mips/pci/ops-bonito64.c index e3b091d..39de8cb 100644 --- a/arch/mips/pci/ops-bonito64.c +++ b/arch/mips/pci/ops-bonito64.c @@ -29,14 +29,9 @@ #define PCI_ACCESS_READ 0 #define PCI_ACCESS_WRITE 1 -#ifdef CONFIG_LEMOTE_FULOONG2E -#define CFG_SPACE_REG(offset) (void *)CKSEG1ADDR(BONITO_PCICFG_BASE | (offset)) -#define ID_SEL_BEGIN 11 -#else #define CFG_SPACE_REG(offset) \ (void *)CKSEG1ADDR(_pcictrl_bonito_pcicfg + (offset)) #define ID_SEL_BEGIN 10 -#endif #define MAX_DEV_NUM (31 - ID_SEL_BEGIN) @@ -78,11 +73,9 @@ static int bonito64_pcibios_config_access(unsigned char access_type, addrp = CFG_SPACE_REG(addr & 0xffff); if (access_type == PCI_ACCESS_WRITE) { writel(cpu_to_le32(*data), addrp); -#ifndef CONFIG_LEMOTE_FULOONG2E /* Wait till done */ while (BONITO_PCIMSTAT & 0xF) ; -#endif } else { *data = le32_to_cpu(readl(addrp)); } diff --git a/arch/mips/pci/ops-fuloong2e.c b/arch/mips/pci/ops-fuloong2e.c new file mode 100644 index 0000000..6bb7919 --- /dev/null +++ b/arch/mips/pci/ops-fuloong2e.c @@ -0,0 +1,160 @@ +/* + * Copyright (C) 1999, 2000, 2004 MIPS Technologies, Inc. + * All rights reserved. + * Authors: Carsten Langgaard + * Maciej W. Rozycki + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * MIPS boards specific PCI support. + */ +#include +#include +#include +#include + +#include + +#define PCI_ACCESS_READ 0 +#define PCI_ACCESS_WRITE 1 + +#define CFG_SPACE_REG(offset) \ + (void *)CKSEG1ADDR(LOONGSON_PCICFG_BASE | (offset)) +#define ID_SEL_BEGIN 11 +#define MAX_DEV_NUM (31 - ID_SEL_BEGIN) + + +static int loongson_pcibios_config_access(unsigned char access_type, + struct pci_bus *bus, + unsigned int devfn, int where, + u32 *data) +{ + u32 busnum = bus->number; + u32 addr, type; + u32 dummy; + void *addrp; + int device = PCI_SLOT(devfn); + int function = PCI_FUNC(devfn); + int reg = where & ~3; + + if (busnum == 0) { + /* Type 0 configuration for onboard PCI bus */ + if (device > MAX_DEV_NUM) + return -1; + + addr = (1 << (device + ID_SEL_BEGIN)) | (function << 8) | reg; + type = 0; + } else { + /* Type 1 configuration for offboard PCI bus */ + addr = (busnum << 16) | (device << 11) | (function << 8) | reg; + type = 0x10000; + } + + /* Clear aborts */ + LOONGSON_PCICMD |= LOONGSON_PCICMD_MABORT_CLR | \ + LOONGSON_PCICMD_MTABORT_CLR; + + LOONGSON_PCIMAP_CFG = (addr >> 16) | type; + + /* Flush Bonito register block */ + dummy = LOONGSON_PCIMAP_CFG; + mmiowb(); + + addrp = CFG_SPACE_REG(addr & 0xffff); + if (access_type == PCI_ACCESS_WRITE) + writel(cpu_to_le32(*data), addrp); + else + *data = le32_to_cpu(readl(addrp)); + + /* Detect Master/Target abort */ + if (LOONGSON_PCICMD & (LOONGSON_PCICMD_MABORT_CLR | + LOONGSON_PCICMD_MTABORT_CLR)) { + /* Error occurred */ + + /* Clear bits */ + LOONGSON_PCICMD |= (LOONGSON_PCICMD_MABORT_CLR | + LOONGSON_PCICMD_MTABORT_CLR); + + return -1; + } + + return 0; + +} + + +/* + * We can't address 8 and 16 bit words directly. Instead we have to + * read/write a 32bit word and mask/modify the data we actually want. + */ +static int loongson_pcibios_read(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 *val) +{ + u32 data = 0; + + if ((size == 2) && (where & 1)) + return PCIBIOS_BAD_REGISTER_NUMBER; + else if ((size == 4) && (where & 3)) + return PCIBIOS_BAD_REGISTER_NUMBER; + + if (loongson_pcibios_config_access(PCI_ACCESS_READ, bus, devfn, where, + &data)) + return -1; + + if (size == 1) + *val = (data >> ((where & 3) << 3)) & 0xff; + else if (size == 2) + *val = (data >> ((where & 3) << 3)) & 0xffff; + else + *val = data; + + return PCIBIOS_SUCCESSFUL; +} + +static int loongson_pcibios_write(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 val) +{ + u32 data = 0; + + if ((size == 2) && (where & 1)) + return PCIBIOS_BAD_REGISTER_NUMBER; + else if ((size == 4) && (where & 3)) + return PCIBIOS_BAD_REGISTER_NUMBER; + + if (size == 4) + data = val; + else { + if (loongson_pcibios_config_access(PCI_ACCESS_READ, bus, devfn, + where, &data)) + return -1; + + if (size == 1) + data = (data & ~(0xff << ((where & 3) << 3))) | + (val << ((where & 3) << 3)); + else if (size == 2) + data = (data & ~(0xffff << ((where & 3) << 3))) | + (val << ((where & 3) << 3)); + } + + if (loongson_pcibios_config_access(PCI_ACCESS_WRITE, bus, devfn, where, + &data)) + return -1; + + return PCIBIOS_SUCCESSFUL; +} + +struct pci_ops loongson_pci_ops = { + .read = loongson_pcibios_read, + .write = loongson_pcibios_write +}; -- 1.6.0.4 From wuzhangjin@gmail.com Thu Jun 4 14:04:56 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 04 Jun 2009 14:05:03 +0100 (WEST) Received: from mail-px0-f186.google.com ([209.85.216.186]:64292 "EHLO mail-px0-f186.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20022595AbZFDNEv (ORCPT ); Thu, 4 Jun 2009 14:04:51 +0100 Received: by pxi16 with SMTP id 16so748644pxi.22 for ; Thu, 04 Jun 2009 06:04:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer:in-reply-to:references; bh=NUmfv/P1yo5mjj19fqD5cPPDQYQH9YHJ3YgbOdiBcRE=; b=mi91SXjzlf7rH4OX7mKExwFtG66BjIqORi8Smfi3QaZrZM+Mt8fKcpZL/2E7FH1aiQ nbKwvYaALG6fYkSttaH3VGMoyHii8tNgyFmSuNYTyeZnGom1mdVNMi1KdETMGJ0g0kxG YRzgq8mlgqK7/Itp6OAFuccTSaLVbixs5yRfg= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; b=ggy82HbmJanvCsmAhiI/RPjXSF7ViIuw526w2yIQB3AU4ni/1y936gwFmB779+QTFK NTBdH51X4IBpGKsbEmyPrVHiYwxCFYue4NoQYOGCt3/6ndeUkpuWxGpwKvuCA0+eu+75 5f38VzmR+IQO2p5xwbHVx51SpRtjlzubnoSLY= Received: by 10.115.94.1 with SMTP id w1mr3491147wal.177.1244120683581; Thu, 04 Jun 2009 06:04:43 -0700 (PDT) Received: from localhost.localdomain ([202.201.14.140]) by mx.google.com with ESMTPS id j34sm10975219waf.29.2009.06.04.06.04.37 (version=TLSv1/SSLv3 cipher=RC4-MD5); Thu, 04 Jun 2009 06:04:42 -0700 (PDT) From: wuzhangjin@gmail.com To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: Wu Zhangjin , Yan Hua , Philippe Vachon , Zhang Le , Zhang Fuxin , loongson-dev , Liu Junliang , Erwan Lerale , Arnaud Patard , Wu Zhangjin Subject: [loongson-PATCH-v3 06/25] divide the files to the smallest logic unit Date: Thu, 4 Jun 2009 21:04:29 +0800 Message-Id: <8a17b160bdf7ebf7a959cabbde59530b068190f4.1244120575.git.wuzj@lemote.com> X-Mailer: git-send-email 1.6.3.1 In-Reply-To: References: Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23249 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips From: Wu Zhangjin to enhance the maintainability and scalability of the source code, there is a need to divide the files to the smallest logic function unit. at the same time, the header files references are cleaned up, and some loongson2e* names are changed to loongson* for future source code sharing between loongson-2e and loongson-2f Signed-off-by: Wu Zhangjin --- arch/mips/include/asm/mach-loongson/loongson.h | 4 + arch/mips/include/asm/mach-loongson/pci.h | 7 +- arch/mips/loongson/fuloong-2e/Makefile | 3 +- arch/mips/loongson/fuloong-2e/bonito-irq.c | 7 +-- arch/mips/loongson/fuloong-2e/cmdline.c | 77 ++++++++++++++++++ arch/mips/loongson/fuloong-2e/init.c | 40 +++++++++ arch/mips/loongson/fuloong-2e/irq.c | 5 +- arch/mips/loongson/fuloong-2e/mem.c | 18 ++++- arch/mips/loongson/fuloong-2e/misc.c | 13 +++ arch/mips/loongson/fuloong-2e/pci.c | 30 +++---- arch/mips/loongson/fuloong-2e/prom.c | 90 --------------------- arch/mips/loongson/fuloong-2e/setup.c | 103 ++++++++---------------- arch/mips/loongson/fuloong-2e/time.c | 27 ++++++ 13 files changed, 230 insertions(+), 194 deletions(-) create mode 100644 arch/mips/loongson/fuloong-2e/cmdline.c create mode 100644 arch/mips/loongson/fuloong-2e/init.c create mode 100644 arch/mips/loongson/fuloong-2e/misc.c delete mode 100644 arch/mips/loongson/fuloong-2e/prom.c create mode 100644 arch/mips/loongson/fuloong-2e/time.c diff --git a/arch/mips/include/asm/mach-loongson/loongson.h b/arch/mips/include/asm/mach-loongson/loongson.h index 26308b5..bce85a8 100644 --- a/arch/mips/include/asm/mach-loongson/loongson.h +++ b/arch/mips/include/asm/mach-loongson/loongson.h @@ -24,6 +24,10 @@ extern unsigned long memsize, highmemsize; /* loongson-based machines specific reboot setup */ extern void loongson_reboot_setup(void); +/* loongson-specific command line and memory initialization */ +extern void __init prom_init_memory(void); +extern void __init prom_init_cmdline(void); + #define LOONGSON_REG(x) \ (*(u32 *)((char *)CKSEG1ADDR(LOONGSON_REG_BASE) + (x))) #define LOONGSON_IRQ_BASE 32 diff --git a/arch/mips/include/asm/mach-loongson/pci.h b/arch/mips/include/asm/mach-loongson/pci.h index 9a351be..8f02486 100644 --- a/arch/mips/include/asm/mach-loongson/pci.h +++ b/arch/mips/include/asm/mach-loongson/pci.h @@ -24,9 +24,8 @@ extern struct pci_ops loongson_pci_ops; -#define LOONGSON2E_PCI_MEM_START 0x14000000UL -#define LOONGSON2E_PCI_MEM_END 0x1fffffffUL -#define LOONGSON2E_PCI_IO_START 0x00004000UL -#define LOONGSON2E_IO_PORT_BASE 0x1fd00000UL +#define LOONGSON_PCI_MEM_START 0x14000000UL +#define LOONGSON_PCI_MEM_END 0x1fffffffUL +#define LOONGSON_PCI_IO_START 0x00004000UL #endif /* !_LOONGSON_PCI_H_ */ diff --git a/arch/mips/loongson/fuloong-2e/Makefile b/arch/mips/loongson/fuloong-2e/Makefile index d34671d..796e729 100644 --- a/arch/mips/loongson/fuloong-2e/Makefile +++ b/arch/mips/loongson/fuloong-2e/Makefile @@ -2,6 +2,7 @@ # Makefile for Lemote Fulong mini-PC board. # -obj-y += setup.o prom.o reset.o irq.o pci.o bonito-irq.o dbg_io.o mem.o +obj-y += setup.o init.o cmdline.o time.o reset.o irq.o \ + pci.o bonito-irq.o dbg_io.o mem.o misc.o EXTRA_CFLAGS += -Werror diff --git a/arch/mips/loongson/fuloong-2e/bonito-irq.c b/arch/mips/loongson/fuloong-2e/bonito-irq.c index 91b9c08..8a32651 100644 --- a/arch/mips/loongson/fuloong-2e/bonito-irq.c +++ b/arch/mips/loongson/fuloong-2e/bonito-irq.c @@ -27,16 +27,11 @@ * 675 Mass Ave, Cambridge, MA 02139, USA. * */ -#include -#include -#include -#include + #include -#include #include - static inline void bonito_irq_enable(unsigned int irq) { LOONGSON_INTENSET = (1 << (irq - LOONGSON_IRQ_BASE)); diff --git a/arch/mips/loongson/fuloong-2e/cmdline.c b/arch/mips/loongson/fuloong-2e/cmdline.c new file mode 100644 index 0000000..01e30db --- /dev/null +++ b/arch/mips/loongson/fuloong-2e/cmdline.c @@ -0,0 +1,77 @@ +/* + * Based on Ocelot Linux port, which is + * Copyright 2001 MontaVista Software Inc. + * Author: jsun@mvista.com or jsun@junsun.net + * + * Copyright 2003 ICT CAS + * Author: Michael Guo + * + * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology + * Author: Fuxin Zhang, zhangfx@lemote.com + * + * Copyright (C) 2009 Lemote Inc. & Insititute of Computing Technology + * Author: Wu Zhangjin, wuzj@lemote.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include + +#include + +unsigned long bus_clock, cpu_clock_freq; +unsigned long memsize, highmemsize; + +int prom_argc; +/* pmon passes arguments in 32bit pointers */ +int *_prom_argv, *_prom_envp; + +#define parse_even_earlier(res, option, p) \ +do { \ + if (strncmp(option, (char *)p, strlen(option)) == 0) \ + strict_strtol((char *)p + strlen(option"="), \ + 10, &res); \ +} while (0) + +void __init prom_init_cmdline(void) +{ + int i; + long l; + prom_argc = fw_arg0; + _prom_argv = (int *)fw_arg1; + _prom_envp = (int *)fw_arg2; + + /* arg[0] is "g", the rest is boot parameters */ + arcs_cmdline[0] = '\0'; + for (i = 1; i < prom_argc; i++) { + l = (long)_prom_argv[i]; + if (strlen(arcs_cmdline) + strlen(((char *)l) + 1) + >= sizeof(arcs_cmdline)) + break; + strcat(arcs_cmdline, ((char *)l)); + strcat(arcs_cmdline, " "); + } + + if ((strstr(arcs_cmdline, "console=")) == NULL) + strcat(arcs_cmdline, " console=ttyS0,115200"); + if ((strstr(arcs_cmdline, "root=")) == NULL) + strcat(arcs_cmdline, " root=/dev/hda1"); + + l = (long)*_prom_envp; + while (l != 0) { + parse_even_earlier(bus_clock, "busclock", l); + parse_even_earlier(cpu_clock_freq, "cpuclock", l); + parse_even_earlier(memsize, "memsize", l); + parse_even_earlier(highmemsize, "highmemsize", l); + _prom_envp++; + l = (long)*_prom_envp; + } + if (memsize == 0) + memsize = 256; + + pr_info("busclock=%ld, cpuclock=%ld, memsize=%ld, highmemsize=%ld\n", + bus_clock, cpu_clock_freq, memsize, highmemsize); +} diff --git a/arch/mips/loongson/fuloong-2e/init.c b/arch/mips/loongson/fuloong-2e/init.c new file mode 100644 index 0000000..76e6fda --- /dev/null +++ b/arch/mips/loongson/fuloong-2e/init.c @@ -0,0 +1,40 @@ +/* + * Based on Ocelot Linux port, which is + * Copyright 2001 MontaVista Software Inc. + * Author: jsun@mvista.com or jsun@junsun.net + * + * Copyright 2003 ICT CAS + * Author: Michael Guo + * + * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology + * Author: Fuxin Zhang, zhangfx@lemote.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include + +#include +#include + +#include + +void __init prom_init(void) +{ + /* init mach type, does we need to init it?? */ + mips_machtype = PRID_IMP_LOONGSON2; + + /* init several base address */ + set_io_port_base((unsigned long) + ioremap(LOONGSON_PCIIO_BASE, LOONGSON_PCIIO_SIZE)); + + prom_init_cmdline(); + prom_init_memory(); +} + +void __init prom_free_prom_memory(void) +{ +} diff --git a/arch/mips/loongson/fuloong-2e/irq.c b/arch/mips/loongson/fuloong-2e/irq.c index 20030c0..d4db5e1 100644 --- a/arch/mips/loongson/fuloong-2e/irq.c +++ b/arch/mips/loongson/fuloong-2e/irq.c @@ -23,15 +23,12 @@ * 675 Mass Ave, Cambridge, MA 02139, USA. * */ + #include -#include -#include #include -#include #include #include -#include #include diff --git a/arch/mips/loongson/fuloong-2e/mem.c b/arch/mips/loongson/fuloong-2e/mem.c index 16cd215..2a0f4e6 100644 --- a/arch/mips/loongson/fuloong-2e/mem.c +++ b/arch/mips/loongson/fuloong-2e/mem.c @@ -4,9 +4,25 @@ * Free Software Foundation; either version 2 of the License, or (at your * option) any later version. */ + #include -#include #include +#include + +#include + +#include + +void __init prom_init_memory(void) +{ + add_memory_region(0x0, (memsize << 20), BOOT_MEM_RAM); +#ifdef CONFIG_64BIT + if (highmemsize > 0) { + add_memory_region(0x20000000, + highmemsize << 20, BOOT_MEM_RAM); + } +#endif /* CONFIG_64BIT */ +} /* override of arch/mips/mm/cache.c: __uncached_access */ int __uncached_access(struct file *file, unsigned long addr) diff --git a/arch/mips/loongson/fuloong-2e/misc.c b/arch/mips/loongson/fuloong-2e/misc.c new file mode 100644 index 0000000..d9532ca --- /dev/null +++ b/arch/mips/loongson/fuloong-2e/misc.c @@ -0,0 +1,13 @@ +/* Copyright (C) 2009 Lemote Inc. & Insititute of Computing Technology + * Author: Wu Zhangjin, wuzj@lemote.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +const char *get_system_type(void) +{ + return "fuloong-2e"; +} diff --git a/arch/mips/loongson/fuloong-2e/pci.c b/arch/mips/loongson/fuloong-2e/pci.c index 1d81110..cfc09a1 100644 --- a/arch/mips/loongson/fuloong-2e/pci.c +++ b/arch/mips/loongson/fuloong-2e/pci.c @@ -25,32 +25,29 @@ * 675 Mass Ave, Cambridge, MA 02139, USA. * */ -#include #include -#include -#include #include #include -static struct resource loongson2e_pci_mem_resource = { - .name = "LOONGSON2E PCI MEM", - .start = LOONGSON2E_PCI_MEM_START, - .end = LOONGSON2E_PCI_MEM_END, +static struct resource loongson_pci_mem_resource = { + .name = "LOONGSON PCI MEM", + .start = LOONGSON_PCI_MEM_START, + .end = LOONGSON_PCI_MEM_END, .flags = IORESOURCE_MEM, }; -static struct resource loongson2e_pci_io_resource = { - .name = "LOONGSON2E PCI IO MEM", - .start = LOONGSON2E_PCI_IO_START, +static struct resource loongson_pci_io_resource = { + .name = "LOONGSON PCI IO MEM", + .start = LOONGSON_PCI_IO_START, .end = IO_SPACE_LIMIT, .flags = IORESOURCE_IO, }; -static struct pci_controller loongson2e_pci_controller = { +static struct pci_controller loongson_pci_controller = { .pci_ops = &loongson_pci_ops, - .io_resource = &loongson2e_pci_io_resource, - .mem_resource = &loongson2e_pci_mem_resource, + .io_resource = &loongson_pci_io_resource, + .mem_resource = &loongson_pci_mem_resource, .mem_offset = 0x00000000UL, .io_offset = 0x00000000UL, }; @@ -83,12 +80,9 @@ static int __init pcibios_init(void) { ict_pcimap(); - loongson2e_pci_controller.io_map_base = - (unsigned long) ioremap(LOONGSON2E_IO_PORT_BASE, - loongson2e_pci_io_resource.end - - loongson2e_pci_io_resource.start + 1); + loongson_pci_controller.io_map_base = mips_io_port_base; - register_pci_controller(&loongson2e_pci_controller); + register_pci_controller(&loongson_pci_controller); return 0; } diff --git a/arch/mips/loongson/fuloong-2e/prom.c b/arch/mips/loongson/fuloong-2e/prom.c deleted file mode 100644 index 95081f4..0000000 --- a/arch/mips/loongson/fuloong-2e/prom.c +++ /dev/null @@ -1,90 +0,0 @@ -/* - * Based on Ocelot Linux port, which is - * Copyright 2001 MontaVista Software Inc. - * Author: jsun@mvista.com or jsun@junsun.net - * - * Copyright 2003 ICT CAS - * Author: Michael Guo - * - * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology - * Author: Fuxin Zhang, zhangfx@lemote.com - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ -#include -#include -#include - -#include - -static int argc; -/* pmon passes arguments in 32bit pointers */ -static int *arg; -static int *env; - -const char *get_system_type(void) -{ - return "lemote-fulong"; -} - -void __init prom_init_cmdline(void) -{ - int i; - long l; - - /* arg[0] is "g", the rest is boot parameters */ - arcs_cmdline[0] = '\0'; - for (i = 1; i < argc; i++) { - l = (long)arg[i]; - if (strlen(arcs_cmdline) + strlen(((char *)l) + 1) - >= sizeof(arcs_cmdline)) - break; - strcat(arcs_cmdline, ((char *)l)); - strcat(arcs_cmdline, " "); - } -} - -#define parse_even_earlier(res, option, p) \ -do { \ - if (strncmp(option, (char *)p, strlen(option)) == 0) \ - strict_strtol((char *)p + strlen(option"="), \ - 10, &res); \ -} while (0) - - -void __init prom_init(void) -{ - long l; - argc = fw_arg0; - arg = (int *)fw_arg1; - env = (int *)fw_arg2; - - prom_init_cmdline(); - - if ((strstr(arcs_cmdline, "console=")) == NULL) - strcat(arcs_cmdline, " console=ttyS0,115200"); - if ((strstr(arcs_cmdline, "root=")) == NULL) - strcat(arcs_cmdline, " root=/dev/hda1"); - - l = (long)*env; - while (l != 0) { - parse_even_earlier(bus_clock, "busclock", l); - parse_even_earlier(cpu_clock_freq, "cpuclock", l); - parse_even_earlier(memsize, "memsize", l); - parse_even_earlier(highmemsize, "highmemsize", l); - env++; - l = (long)*env; - } - if (memsize == 0) - memsize = 256; - - pr_info("busclock=%ld, cpuclock=%ld, memsize=%ld, highmemsize=%ld\n", - bus_clock, cpu_clock_freq, memsize, highmemsize); -} - -void __init prom_free_prom_memory(void) -{ -} diff --git a/arch/mips/loongson/fuloong-2e/setup.c b/arch/mips/loongson/fuloong-2e/setup.c index ae226a4..770d7b5 100644 --- a/arch/mips/loongson/fuloong-2e/setup.c +++ b/arch/mips/loongson/fuloong-2e/setup.c @@ -1,108 +1,71 @@ /* - * BRIEF MODULE DESCRIPTION - * setup.c - board dependent boot routines + * board dependent setup routines * * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology * Author: Fuxin Zhang, zhangfx@lemote.com * + * Copyright (C) 2009 Lemote Inc. & Insititute of Computing Technology + * Author: Wu Zhangjin, wuzj@lemote.com + * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the * Free Software Foundation; either version 2 of the License, or (at your * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - * */ -#include -#include -#include -#include -#include +#include + #include -#include #include -#include - -#ifdef CONFIG_VT -#include -#include -#endif -unsigned long cpu_clock_freq, bus_clock; -unsigned long memsize, highmemsize; - -void __init plat_time_init(void) -{ - /* setup mips r4k timer */ - mips_hpt_frequency = cpu_clock_freq / 2; -} - -unsigned long read_persistent_clock(void) -{ - return mc146818_get_cmos_time(); -} - -void (*__wbflush)(void); +void (*__wbflush) (void); EXPORT_SYMBOL(__wbflush); -static void wbflush_loongson2e(void) +static void loongson_wbflush(void) { asm(".set\tpush\n\t" ".set\tnoreorder\n\t" ".set mips3\n\t" - "sync\n\t" - "nop\n\t" - ".set\tpop\n\t" - ".set mips0\n\t"); + "sync\n\t" "nop\n\t" ".set\tpop\n\t" ".set mips0\n\t"); } -void __init plat_mem_setup(void) +void __init loongson_wbflush_setup(void) { - set_io_port_base((unsigned long)ioremap(LOONGSON2E_IO_PORT_BASE, - IO_SPACE_LIMIT - LOONGSON2E_PCI_IO_START + 1)); - loongson_reboot_setup(); - - __wbflush = wbflush_loongson2e; - - add_memory_region(0x0, (memsize << 20), BOOT_MEM_RAM); -#ifdef CONFIG_64BIT - if (highmemsize > 0) - add_memory_region(0x20000000, highmemsize << 20, BOOT_MEM_RAM); -#endif + __wbflush = loongson_wbflush; +} -#ifdef CONFIG_VT -#if defined(CONFIG_VGA_CONSOLE) - conswitchp = &vga_con; +#if defined(CONFIG_VT) && defined(CONFIG_VGA_CONSOLE) +#include +void __init loongson_screeninfo_setup(void) +{ screen_info = (struct screen_info) { - 0, 25, /* orig-x, orig-y */ + 0, /* orig-x */ + 25, /* orig-y */ 0, /* unused */ 0, /* orig-video-page */ 0, /* orig-video-mode */ 80, /* orig-video-cols */ - 0, 0, 0, /* ega_ax, ega_bx, ega_cx */ + 0, /* ega_ax */ + 0, /* ega_bx */ + 0, /* ega_cx */ 25, /* orig-video-lines */ VIDEO_TYPE_VGAC, /* orig-video-isVGA */ 16 /* orig-video-points */ }; -#elif defined(CONFIG_DUMMY_CONSOLE) - conswitchp = &dummy_con; -#endif +} +#else +void __init loongson_screeninfo_setup(void) +{ +} #endif +void __init plat_mem_setup(void) +{ + loongson_reboot_setup(); + + loongson_wbflush_setup(); + + loongson_screeninfo_setup(); } diff --git a/arch/mips/loongson/fuloong-2e/time.c b/arch/mips/loongson/fuloong-2e/time.c new file mode 100644 index 0000000..231f0c2 --- /dev/null +++ b/arch/mips/loongson/fuloong-2e/time.c @@ -0,0 +1,27 @@ +/* + * board dependent boot routines + * + * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology + * Author: Fuxin Zhang, zhangfx@lemote.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include +#include + +#include + +unsigned long read_persistent_clock(void) +{ + return mc146818_get_cmos_time(); +} + +void __init plat_time_init(void) +{ + /* setup mips r4k timer */ + mips_hpt_frequency = cpu_clock_freq / 2; +} -- 1.6.0.4 From wuzhangjin@gmail.com Thu Jun 4 14:05:20 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 04 Jun 2009 14:05:27 +0100 (WEST) Received: from mail-pz0-f202.google.com ([209.85.222.202]:51894 "EHLO mail-pz0-f202.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20022601AbZFDNFL (ORCPT ); Thu, 4 Jun 2009 14:05:11 +0100 Received: by pzk40 with SMTP id 40so738268pzk.22 for ; Thu, 04 Jun 2009 06:05:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer:in-reply-to:references; bh=quMDu3344c2fhPaDGTCIknHILRYldZzHovkdr/zRW0c=; b=s5pCUWs/m5yQHEXz9Nvnfkbn334VCqILy/FPEtmihT7+37OhlRrJvF2508JUBVgQ9n nR9TPTQB/nFOLxjHBWxn56p7dx5j8Zzxp5nHn+45N/VXg6TrwMY0dAeD0J0GYCmvti9P hCS40DaEy9Rfa2HbGPl3jzQViE2AaincSvn4Q= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; b=S+4/PTA8VWtnF69fasfh7ywoO2banWdobdIPVV5waAMZeai7p00sv8dLoxpaFqoDc/ F0AuCsXRXp0kut5U1mqZE/F0iW/Jcie+rI7uGpkE7794UK6gaRVK8UQFWaOMJuaOq4Al ty464Jcl+qXyBL9sKMTTyjSYOQyIvi60oDfJ4= Received: by 10.114.59.9 with SMTP id h9mr2624299waa.211.1244120703949; Thu, 04 Jun 2009 06:05:03 -0700 (PDT) Received: from localhost.localdomain ([202.201.14.140]) by mx.google.com with ESMTPS id n40sm11153191wag.30.2009.06.04.06.04.57 (version=TLSv1/SSLv3 cipher=RC4-MD5); Thu, 04 Jun 2009 06:05:02 -0700 (PDT) From: wuzhangjin@gmail.com To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: Wu Zhangjin , Yan Hua , Philippe Vachon , Zhang Le , Zhang Fuxin , loongson-dev , Liu Junliang , Erwan Lerale , Arnaud Patard , Wu Zhangjin Subject: [loongson-PATCH-v3 07/25] replace tons of magic numbers by understandable symbols Date: Thu, 4 Jun 2009 21:04:49 +0800 Message-Id: <5d793c4a2e351954a09522b12c3d2d36b7120cf2.1244120575.git.wuzj@lemote.com> X-Mailer: git-send-email 1.6.3.1 In-Reply-To: References: Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23250 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips From: Wu Zhangjin tons of magic numbers are replaced by understandable symbols, and two new header files are added to support this substitution. Reviewd-by: Arnaud Patard Signed-off-by: Wu Zhangjin --- arch/mips/include/asm/mach-loongson/loongson.h | 3 ++ arch/mips/include/asm/mach-loongson/machine.h | 27 ++++++++++++++++++ arch/mips/include/asm/mach-loongson/mem.h | 8 +++++ arch/mips/loongson/fuloong-2e/bonito-irq.c | 3 +- arch/mips/loongson/fuloong-2e/dbg_io.c | 12 +++---- arch/mips/loongson/fuloong-2e/irq.c | 7 ++-- arch/mips/loongson/fuloong-2e/mem.c | 9 +++-- arch/mips/loongson/fuloong-2e/misc.c | 4 ++- arch/mips/loongson/fuloong-2e/pci.c | 36 ++++++++++++++++-------- arch/mips/loongson/fuloong-2e/reset.c | 19 +++++++----- arch/mips/loongson/fuloong-2e/setup.c | 5 ++- 11 files changed, 96 insertions(+), 37 deletions(-) create mode 100644 arch/mips/include/asm/mach-loongson/machine.h create mode 100644 arch/mips/include/asm/mach-loongson/mem.h diff --git a/arch/mips/include/asm/mach-loongson/loongson.h b/arch/mips/include/asm/mach-loongson/loongson.h index bce85a8..5ad629e 100644 --- a/arch/mips/include/asm/mach-loongson/loongson.h +++ b/arch/mips/include/asm/mach-loongson/loongson.h @@ -14,6 +14,9 @@ #ifndef __LOONGSON_H #define __LOONGSON_H +#include +#include + /* loongson internal northbridge initialization */ extern void bonito_irq_init(void); diff --git a/arch/mips/include/asm/mach-loongson/machine.h b/arch/mips/include/asm/mach-loongson/machine.h new file mode 100644 index 0000000..651a35d --- /dev/null +++ b/arch/mips/include/asm/mach-loongson/machine.h @@ -0,0 +1,27 @@ +/* + * board-specific header file + * + * Copyright (c) 2009 Wu Zhangjin + * + * This program is free software; you can redistribute it + * and/or modify it under the terms of the GNU General + * Public License as published by the Free Software + * Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#ifndef __MACHINE_H +#define __MACHINE_H + +#define MACH_NAME "lemote-fuloong(2e)" + +#define LOONGSON_UART_BASE (LOONGSON_PCIIO_BASE + 0x3f8) + +#define LOONGSON_NORTH_BRIDGE_IRQ (MIPS_CPU_IRQ_BASE + 2) +#define LOONGSON_UART_IRQ (MIPS_CPU_IRQ_BASE + 4) +#define LOONGSON_SOUTH_BRIDGE_IRQ (MIPS_CPU_IRQ_BASE + 5) +#define LOONGSON_TIMER_IRQ (MIPS_CPU_IRQ_BASE + 7) +#define LOONGSON_DMATIMEOUT_IRQ (LOONGSON_IRQ_BASE + 10) + + +#endif /* ! __MACHINE_H */ diff --git a/arch/mips/include/asm/mach-loongson/mem.h b/arch/mips/include/asm/mach-loongson/mem.h new file mode 100644 index 0000000..ad01dc2 --- /dev/null +++ b/arch/mips/include/asm/mach-loongson/mem.h @@ -0,0 +1,8 @@ +#ifndef __MEM_H +#define __MEM_H + +#define LOONGSON_HIGHMEM_START 0x20000000 +#define LOONGSON_MMIO_MEM_START 0x10000000 +#define LOONGSON_MMIO_MEM_END 0x20000000 + +#endif /* !__MEM_H */ diff --git a/arch/mips/loongson/fuloong-2e/bonito-irq.c b/arch/mips/loongson/fuloong-2e/bonito-irq.c index 8a32651..1f43447 100644 --- a/arch/mips/loongson/fuloong-2e/bonito-irq.c +++ b/arch/mips/loongson/fuloong-2e/bonito-irq.c @@ -31,6 +31,7 @@ #include #include +#include static inline void bonito_irq_enable(unsigned int irq) { @@ -64,5 +65,5 @@ void bonito_irq_init(void) for (i = LOONGSON_IRQ_BASE; i < LOONGSON_IRQ_BASE + 32; i++) set_irq_chip_and_handler(i, &bonito_irq_type, handle_level_irq); - setup_irq(LOONGSON_IRQ_BASE + 10, &dma_timeout_irqaction); + setup_irq(LOONGSON_DMATIMEOUT_IRQ, &dma_timeout_irqaction); } diff --git a/arch/mips/loongson/fuloong-2e/dbg_io.c b/arch/mips/loongson/fuloong-2e/dbg_io.c index 84f8320..1ace08f 100644 --- a/arch/mips/loongson/fuloong-2e/dbg_io.c +++ b/arch/mips/loongson/fuloong-2e/dbg_io.c @@ -28,12 +28,13 @@ * */ -#include -#include #include #include +#include +#include + #define UART16550_BAUD_2400 2400 #define UART16550_BAUD_4800 4800 #define UART16550_BAUD_9600 9600 @@ -59,11 +60,8 @@ /* ----------------------------------------------------- */ /* === CONFIG === */ -#ifdef CONFIG_64BIT -#define BASE (0xffffffffbfd003f8) -#else -#define BASE (0xbfd003f8) -#endif + +#define BASE ioremap_nocache(LOONGSON_UART_BASE, 8) #define MAX_BAUD BASE_BAUD /* === END OF CONFIG === */ diff --git a/arch/mips/loongson/fuloong-2e/irq.c b/arch/mips/loongson/fuloong-2e/irq.c index d4db5e1..7bf9e18 100644 --- a/arch/mips/loongson/fuloong-2e/irq.c +++ b/arch/mips/loongson/fuloong-2e/irq.c @@ -31,6 +31,7 @@ #include #include +#include /* * the first level int-handler will jump here if it is a bonito irq @@ -75,7 +76,7 @@ asmlinkage void plat_irq_dispatch(void) unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM; if (pending & CAUSEF_IP7) - do_IRQ(MIPS_CPU_IRQ_BASE + 7); + do_IRQ(LOONGSON_TIMER_IRQ); else if (pending & CAUSEF_IP5) i8259_irqdispatch(); else if (pending & CAUSEF_IP2) @@ -128,8 +129,8 @@ void __init arch_init_irq(void) */ /* bonito irq at IP2 */ - setup_irq(MIPS_CPU_IRQ_BASE + 2, &cascade_irqaction); + setup_irq(LOONGSON_NORTH_BRIDGE_IRQ, &cascade_irqaction); /* 8259 irq at IP5 */ - setup_irq(MIPS_CPU_IRQ_BASE + 5, &cascade_irqaction); + setup_irq(LOONGSON_SOUTH_BRIDGE_IRQ, &cascade_irqaction); } diff --git a/arch/mips/loongson/fuloong-2e/mem.c b/arch/mips/loongson/fuloong-2e/mem.c index 2a0f4e6..7f6ee37 100644 --- a/arch/mips/loongson/fuloong-2e/mem.c +++ b/arch/mips/loongson/fuloong-2e/mem.c @@ -7,18 +7,18 @@ #include #include -#include #include #include +#include void __init prom_init_memory(void) { add_memory_region(0x0, (memsize << 20), BOOT_MEM_RAM); #ifdef CONFIG_64BIT if (highmemsize > 0) { - add_memory_region(0x20000000, + add_memory_region(LOONGSON_HIGHMEM_START, highmemsize << 20, BOOT_MEM_RAM); } #endif /* CONFIG_64BIT */ @@ -34,6 +34,7 @@ int __uncached_access(struct file *file, unsigned long addr) * On the Lemote Loongson 2e system, the peripheral registers * reside between 0x1000:0000 and 0x2000:0000. */ - return addr >= __pa(high_memory) || - ((addr >= 0x10000000) && (addr < 0x20000000)); + return addr >= __pa(high_memory) || \ + ((addr >= LOONGSON_MMIO_MEM_START) && \ + (addr < LOONGSON_MMIO_MEM_END)); } diff --git a/arch/mips/loongson/fuloong-2e/misc.c b/arch/mips/loongson/fuloong-2e/misc.c index d9532ca..1b8044c 100644 --- a/arch/mips/loongson/fuloong-2e/misc.c +++ b/arch/mips/loongson/fuloong-2e/misc.c @@ -7,7 +7,9 @@ * option) any later version. */ +#include + const char *get_system_type(void) { - return "fuloong-2e"; + return MACH_NAME; } diff --git a/arch/mips/loongson/fuloong-2e/pci.c b/arch/mips/loongson/fuloong-2e/pci.c index cfc09a1..89bc1af 100644 --- a/arch/mips/loongson/fuloong-2e/pci.c +++ b/arch/mips/loongson/fuloong-2e/pci.c @@ -55,25 +55,37 @@ static struct pci_controller loongson_pci_controller = { static void __init ict_pcimap(void) { /* - * local to PCI mapping: [256M,512M] -> [256M,512M]; differ from PMON + * local to PCI mapping for CPU accessing PCI space * * CPU address space [256M,448M] is window for accessing pci space - * we set pcimap_lo[0,1,2] to map it to pci space [256M,448M] - * pcimap: bit18,pcimap_2; bit[17-12],lo2;bit[11-6],lo1;bit[5-0],lo0 + * we set pcimap_lo[0,1,2] to map it to pci space[0M, 64M], [320M,448M] + * + * pcimap: PCI_MAP2 PCI_Mem_Lo2 PCI_Mem_Lo1 PCI_Mem_Lo0 + * [<2G] [384M,448M] [320M,384M] [0M,64M] */ - /* 1,00 0110 ,0001 01,00 0000 */ - LOONGSON_PCIMAP = 0x46140; - - /* 1, 00 0010, 0000,01, 00 0000 */ - /* LOONGSON_PCIMAP = 0x42040; */ + LOONGSON_PCIMAP = LOONGSON_PCIMAP_PCIMAP_2 | + LOONGSON_PCIMAP_WIN(2, 0x18000000) | + LOONGSON_PCIMAP_WIN(1, 0x14000000) | + LOONGSON_PCIMAP_WIN(0, 0); /* - * PCI to local mapping: [2G,2G+256M] -> [0,256M] + * PCI-DMA to local mapping: [2G,2G+256M] -> [0M,256M] */ - LOONGSON_PCIBASE0 = 0x80000000; - LOONGSON_PCIBASE1 = 0x00800000; - LOONGSON_PCIBASE2 = 0x90000000; + LOONGSON_PCIBASE0 = 0x80000000ul; /* base: 2G -> mmap: 0M */ + /* size: 256M, burst transmission, pre-fetch enable, 64bit */ + LOONGSON_PCI_HIT0_SEL_L = 0xc000000cul; + LOONGSON_PCI_HIT0_SEL_H = 0xfffffffful; + LOONGSON_PCI_HIT1_SEL_L = 0x00000006ul; /* set this BAR as invalid */ + LOONGSON_PCI_HIT1_SEL_H = 0x00000000ul; + LOONGSON_PCI_HIT2_SEL_L = 0x00000006ul; /* set this BAR as invalid */ + LOONGSON_PCI_HIT2_SEL_H = 0x00000000ul; + + /* avoid deadlock of PCI reading/writing lock operation */ + LOONGSON_PCI_ISR4C = 0xd2000001ul; + /* can not change gnt to break pci transfer when device's gnt not + deassert for some broken device */ + LOONGSON_PXARB_CFG = 0x00fe0105ul; } static int __init pcibios_init(void) diff --git a/arch/mips/loongson/fuloong-2e/reset.c b/arch/mips/loongson/fuloong-2e/reset.c index 769a2ce..87244a1 100644 --- a/arch/mips/loongson/fuloong-2e/reset.c +++ b/arch/mips/loongson/fuloong-2e/reset.c @@ -6,21 +6,24 @@ * * Copyright (C) 2007 Lemote, Inc. & Institute of Computing Technology * Author: Fuxin Zhang, zhangfx@lemote.com + * + * Copyright (c) 2009 Philippe Vachon + * + * Copyright (c) 2009 Lemote, Inc. & Institute of Computing Technology + * Author: Wu Zhangjin, wuzj@lemote.com */ #include #include +#include static void loongson_restart(char *command) { -#ifdef CONFIG_32BIT - *(unsigned long *)0xbfe00104 &= ~(1 << 2); - *(unsigned long *)0xbfe00104 |= (1 << 2); -#else - *(unsigned long *)0xffffffffbfe00104 &= ~(1 << 2); - *(unsigned long *)0xffffffffbfe00104 |= (1 << 2); -#endif - __asm__ __volatile__("jr\t%0" : : "r"(0xbfc00000)); + LOONGSON_GENCFG &= ~LOONGSON_GENCFG_CPUSELFRESET; + LOONGSON_GENCFG |= LOONGSON_GENCFG_CPUSELFRESET; + + /* reboot via jumping to 0xbfc00000 */ + ((void (*)(void))ioremap_nocache(LOONGSON_BOOT_BASE, 4)) (); } static void loongson_halt(void) diff --git a/arch/mips/loongson/fuloong-2e/setup.c b/arch/mips/loongson/fuloong-2e/setup.c index 770d7b5..4fcbe48 100644 --- a/arch/mips/loongson/fuloong-2e/setup.c +++ b/arch/mips/loongson/fuloong-2e/setup.c @@ -27,7 +27,10 @@ static void loongson_wbflush(void) asm(".set\tpush\n\t" ".set\tnoreorder\n\t" ".set mips3\n\t" - "sync\n\t" "nop\n\t" ".set\tpop\n\t" ".set mips0\n\t"); + "sync\n\t" + "nop\n\t" + ".set\tpop\n\t" + ".set mips0\n\t"); } void __init loongson_wbflush_setup(void) -- 1.6.0.4 From wuzhangjin@gmail.com Thu Jun 4 14:05:44 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 04 Jun 2009 14:05:51 +0100 (WEST) Received: from mail-px0-f186.google.com ([209.85.216.186]:63048 "EHLO mail-px0-f186.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20022605AbZFDNFa (ORCPT ); Thu, 4 Jun 2009 14:05:30 +0100 Received: by pxi16 with SMTP id 16so748978pxi.22 for ; Thu, 04 Jun 2009 06:05:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer:in-reply-to:references; bh=HVDzJfTZ0I1EvoOSLEO/q2yqMsri0zxkisWu82bAa6M=; b=bbr8fChd+rHwiVsCLUUdzBHLOoOShYDnl1haS2ofkMKI98aGPuOf+r6QTS/HFACwZS EaRw/2tb9GlJcj5aUNI1+pjkLGA0MLulOSQnvqZI+3fIqOtRQ18NwulQCduKlDbXtgms BJl96XILanhk7qaZg8hcu9kg5u8ygRwYCWKIc= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; b=nNsG4t0Zz8PD03k/gzfwDBwB/gZTxJIKMUZasg8IBO1iJgk/s2wLn1jnkCV+SI3DFb Wd0VdH3c/VYSFJvpU0OUXuK7Lv85pdIlN3NFtA2AB2tKcRTOHJjl/iwQr5LInMRk0lPz 2+7Wy508m+kX3AVf/5N6eh/uqFr+gLL1GnOvA= Received: by 10.114.136.16 with SMTP id j16mr3426184wad.209.1244120723338; Thu, 04 Jun 2009 06:05:23 -0700 (PDT) Received: from localhost.localdomain ([202.201.14.140]) by mx.google.com with ESMTPS id m6sm11115389wag.14.2009.06.04.06.05.17 (version=TLSv1/SSLv3 cipher=RC4-MD5); Thu, 04 Jun 2009 06:05:22 -0700 (PDT) From: wuzhangjin@gmail.com To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: Wu Zhangjin , Yan Hua , Philippe Vachon , Zhang Le , Zhang Fuxin , loongson-dev , Liu Junliang , Erwan Lerale , Arnaud Patard , Wu Zhangjin Subject: [loongson-PATCH-v3 08/25] clean up the early printk support for fuloong(2e) Date: Thu, 4 Jun 2009 21:05:09 +0800 Message-Id: <09d017e0bb7ba768fb21efbbc577a37f272e6506.1244120575.git.wuzj@lemote.com> X-Mailer: git-send-email 1.6.3.1 In-Reply-To: References: Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23251 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips From: Wu Zhangjin this is originally from the lm2e-fixes branch of Philippe's git://git.linux-cisco.org/linux-mips.git Signed-off-by: Wu Zhangjin --- arch/mips/loongson/fuloong-2e/Makefile | 7 +- arch/mips/loongson/fuloong-2e/dbg_io.c | 151 -------------------------- arch/mips/loongson/fuloong-2e/early_printk.c | 28 +++++ 3 files changed, 34 insertions(+), 152 deletions(-) delete mode 100644 arch/mips/loongson/fuloong-2e/dbg_io.c create mode 100644 arch/mips/loongson/fuloong-2e/early_printk.c diff --git a/arch/mips/loongson/fuloong-2e/Makefile b/arch/mips/loongson/fuloong-2e/Makefile index 796e729..035e04c 100644 --- a/arch/mips/loongson/fuloong-2e/Makefile +++ b/arch/mips/loongson/fuloong-2e/Makefile @@ -3,6 +3,11 @@ # obj-y += setup.o init.o cmdline.o time.o reset.o irq.o \ - pci.o bonito-irq.o dbg_io.o mem.o misc.o + pci.o bonito-irq.o mem.o misc.o + +# +# Early printk support +# +obj-$(CONFIG_EARLY_PRINTK) += early_printk.o EXTRA_CFLAGS += -Werror diff --git a/arch/mips/loongson/fuloong-2e/dbg_io.c b/arch/mips/loongson/fuloong-2e/dbg_io.c deleted file mode 100644 index 1ace08f..0000000 --- a/arch/mips/loongson/fuloong-2e/dbg_io.c +++ /dev/null @@ -1,151 +0,0 @@ -/* - * Copyright 2001 MontaVista Software Inc. - * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net - * Copyright (C) 2000, 2001 Ralf Baechle (ralf@gnu.org) - * - * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology - * Author: Fuxin Zhang, zhangfx@lemote.com - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - * - */ - -#include - -#include - -#include -#include - -#define UART16550_BAUD_2400 2400 -#define UART16550_BAUD_4800 4800 -#define UART16550_BAUD_9600 9600 -#define UART16550_BAUD_19200 19200 -#define UART16550_BAUD_38400 38400 -#define UART16550_BAUD_57600 57600 -#define UART16550_BAUD_115200 115200 - -#define UART16550_PARITY_NONE 0 -#define UART16550_PARITY_ODD 0x08 -#define UART16550_PARITY_EVEN 0x18 -#define UART16550_PARITY_MARK 0x28 -#define UART16550_PARITY_SPACE 0x38 - -#define UART16550_DATA_5BIT 0x0 -#define UART16550_DATA_6BIT 0x1 -#define UART16550_DATA_7BIT 0x2 -#define UART16550_DATA_8BIT 0x3 - -#define UART16550_STOP_1BIT 0x0 -#define UART16550_STOP_2BIT 0x4 - -/* ----------------------------------------------------- */ - -/* === CONFIG === */ - -#define BASE ioremap_nocache(LOONGSON_UART_BASE, 8) - -#define MAX_BAUD BASE_BAUD -/* === END OF CONFIG === */ - -#define REG_OFFSET 1 - -/* register offset */ -#define OFS_RCV_BUFFER 0 -#define OFS_TRANS_HOLD 0 -#define OFS_SEND_BUFFER 0 -#define OFS_INTR_ENABLE (1*REG_OFFSET) -#define OFS_INTR_ID (2*REG_OFFSET) -#define OFS_DATA_FORMAT (3*REG_OFFSET) -#define OFS_LINE_CONTROL (3*REG_OFFSET) -#define OFS_MODEM_CONTROL (4*REG_OFFSET) -#define OFS_RS232_OUTPUT (4*REG_OFFSET) -#define OFS_LINE_STATUS (5*REG_OFFSET) -#define OFS_MODEM_STATUS (6*REG_OFFSET) -#define OFS_RS232_INPUT (6*REG_OFFSET) -#define OFS_SCRATCH_PAD (7*REG_OFFSET) - -#define OFS_DIVISOR_LSB (0*REG_OFFSET) -#define OFS_DIVISOR_MSB (1*REG_OFFSET) - -/* memory-mapped read/write of the port */ -#define UART16550_READ(y) readb((char *)BASE + (y)) -#define UART16550_WRITE(y, z) writeb(z, (char *)BASE + (y)) - -void debugInit(u32 baud, u8 data, u8 parity, u8 stop) -{ - u32 divisor; - - /* disable interrupts */ - UART16550_WRITE(OFS_INTR_ENABLE, 0); - - /* set up buad rate */ - /* set DIAB bit */ - UART16550_WRITE(OFS_LINE_CONTROL, 0x80); - - /* set divisor */ - divisor = MAX_BAUD / baud; - UART16550_WRITE(OFS_DIVISOR_LSB, divisor & 0xff); - UART16550_WRITE(OFS_DIVISOR_MSB, (divisor & 0xff00) >> 8); - - /* clear DIAB bit */ - UART16550_WRITE(OFS_LINE_CONTROL, 0x0); - - /* set data format */ - UART16550_WRITE(OFS_DATA_FORMAT, data | parity | stop); -} - -static int remoteDebugInitialized; - -u8 getDebugChar(void) -{ - if (!remoteDebugInitialized) { - remoteDebugInitialized = 1; - debugInit(UART16550_BAUD_115200, - UART16550_DATA_8BIT, - UART16550_PARITY_NONE, UART16550_STOP_1BIT); - } - - while ((UART16550_READ(OFS_LINE_STATUS) & 0x1) == 0) - ; - return UART16550_READ(OFS_RCV_BUFFER); -} - -int putDebugChar(u8 byte) -{ - if (!remoteDebugInitialized) { - remoteDebugInitialized = 1; - /* - debugInit(UART16550_BAUD_115200, - UART16550_DATA_8BIT, - UART16550_PARITY_NONE, UART16550_STOP_1BIT); */ - } - - while ((UART16550_READ(OFS_LINE_STATUS) & 0x20) == 0) - ; - UART16550_WRITE(OFS_SEND_BUFFER, byte); - return 1; -} - -void prom_putchar(char c) -{ - putDebugChar(c); -} diff --git a/arch/mips/loongson/fuloong-2e/early_printk.c b/arch/mips/loongson/fuloong-2e/early_printk.c new file mode 100644 index 0000000..9f4b881 --- /dev/null +++ b/arch/mips/loongson/fuloong-2e/early_printk.c @@ -0,0 +1,28 @@ +/* early printk support + * + * Copyright (c) 2009 Philippe Vachon + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include +#include + +#include +#include + +void prom_putchar(char c) +{ + int timeout; + phys_addr_t uart_base = + (phys_addr_t) ioremap_nocache(LOONGSON_UART_BASE, 8); + char reg = readb((u8 *) (uart_base + UART_LSR)) & UART_LSR_THRE; + + for (timeout = 1024; reg == 0 && timeout > 0; timeout--) + reg = readb((u8 *) (uart_base + UART_LSR)) & UART_LSR_THRE; + + writeb(c, (u8 *) (uart_base + UART_TX)); +} -- 1.6.0.4 From wuzhangjin@gmail.com Thu Jun 4 14:06:17 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 04 Jun 2009 14:06:23 +0100 (WEST) Received: from mail-px0-f186.google.com ([209.85.216.186]:63048 "EHLO mail-px0-f186.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20022611AbZFDNFn (ORCPT ); Thu, 4 Jun 2009 14:05:43 +0100 Received: by mail-px0-f186.google.com with SMTP id 16so748978pxi.22 for ; Thu, 04 Jun 2009 06:05:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer:in-reply-to:references; bh=w8CcwpuRdezyOhMtc030IpNyb/hSUy2JaEq2t5fvSPM=; b=eKXWDutL9b+r7Fu8/+6fee4pXem4daKjjUmxu+gsWaJn7BosqeyrNA+cFCbDORd74S jLvfBOZ57+btKEtd3KxAsLS09xxjt1DDsHl/tns62ALwOxgPuZXAlcpFqx1rtntmrJ1k tazqu9csv3/TcOJJmmZEKgFdOTZGCNvkd2zkA= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; b=V/qQGk0oH/dhVZjSueaBgo8n67sFLMZ1JjRyzRUGhCg+LIWF6rye5N1ExJbPyYZNW1 EuDhBAwLGQIzjula4gYhVXkHty0VUNrYPXs3e8/NuWgjoJga0ySb+emMkZ/qml3B6Spu Xo5SaKLqFjmC/H0eAnm+sTYplWnTACm+wPk/U= Received: by 10.115.60.1 with SMTP id n1mr3425924wak.113.1244120742204; Thu, 04 Jun 2009 06:05:42 -0700 (PDT) Received: from localhost.localdomain ([202.201.14.140]) by mx.google.com with ESMTPS id n6sm11061901wag.39.2009.06.04.06.05.36 (version=TLSv1/SSLv3 cipher=RC4-MD5); Thu, 04 Jun 2009 06:05:40 -0700 (PDT) From: wuzhangjin@gmail.com To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: Wu Zhangjin , Yan Hua , Philippe Vachon , Zhang Le , Zhang Fuxin , loongson-dev , Liu Junliang , Erwan Lerale , Arnaud Patard , Wu Zhangjin Subject: [loongson-PATCH-v3 09/25] enable Real Time Clock Support for fuloong(2e) Date: Thu, 4 Jun 2009 21:05:29 +0800 Message-Id: <5783988b6878698ddddb007950e53d34fa3ef565.1244120575.git.wuzj@lemote.com> X-Mailer: git-send-email 1.6.3.1 In-Reply-To: References: Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23252 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips From: Wu Zhangjin by default, RTC_LIB is selected by MIPS, but if RTC_LIB is enabled, Enhanced Real Time Clock Support(RTC) will be disabled, so, to enable it, not select RTC_LIB in LEMOTE_FULOONG2E will fix this problem. RTC support is needed by some tools like hwclock, if you want hwclock work well, these two jobs need to do: kernel configuration: Device Drivers ---> Character devices ---> <*> Enhanced Real Time Clock Support (legacy PC RTC driver) user-space configuration: $ mknod /dev/rtc c 10 135 and there is another RTC support in linux, whose kernel option is RTC_CLASS, it should be fixed for fuloong(2e) via enabling the binary mode in driver/rtc/rtc-cmos.c and register the RTC device resource in a machine specific rtc.c to make hwclock work with it normally, please do: kernel configuration: Device Drivers ---> <*> Real Time Clock ---> <*> PC-style 'CMOS' user-space configuration: $ mknod /dev/rtc0 c 254 0 /dev/rtc0 is the default RTC device file. Signed-off-by: Wu Zhangjin --- arch/mips/Kconfig | 2 +- arch/mips/loongson/fuloong-2e/Makefile | 7 ++++ arch/mips/loongson/fuloong-2e/rtc.c | 55 ++++++++++++++++++++++++++++++++ drivers/rtc/rtc-cmos.c | 8 ++-- 4 files changed, 67 insertions(+), 5 deletions(-) create mode 100644 arch/mips/loongson/fuloong-2e/rtc.c diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 7897861..4a7e61f 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -6,7 +6,7 @@ config MIPS select HAVE_ARCH_KGDB # Horrible source of confusion. Die, die, die ... select EMBEDDED - select RTC_LIB + select RTC_LIB if !LEMOTE_FULOONG2E mainmenu "Linux/MIPS Kernel Configuration" diff --git a/arch/mips/loongson/fuloong-2e/Makefile b/arch/mips/loongson/fuloong-2e/Makefile index 035e04c..76904da 100644 --- a/arch/mips/loongson/fuloong-2e/Makefile +++ b/arch/mips/loongson/fuloong-2e/Makefile @@ -10,4 +10,11 @@ obj-y += setup.o init.o cmdline.o time.o reset.o irq.o \ # obj-$(CONFIG_EARLY_PRINTK) += early_printk.o +# +# Enable RTC Class support +# +# please enable CONFIG_RTC_DRV_CMOS +# +obj-$(CONFIG_RTC_DRV_CMOS) += rtc.o + EXTRA_CFLAGS += -Werror diff --git a/arch/mips/loongson/fuloong-2e/rtc.c b/arch/mips/loongson/fuloong-2e/rtc.c new file mode 100644 index 0000000..469ada8 --- /dev/null +++ b/arch/mips/loongson/fuloong-2e/rtc.c @@ -0,0 +1,55 @@ +/* + * Registration of Cobalt RTC platform device. + * + * Copyright (C) 2007 Yoichi Yuasa + * Copyright (C) 2009 Wu Zhangjin + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include +#include +#include +#include + +static struct resource rtc_cmos_resource[] = { + { + .start = RTC_PORT(0), + .end = RTC_PORT(1), + .flags = IORESOURCE_IO, + }, + { + .start = RTC_IRQ, + .end = RTC_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device rtc_cmos_device = { + .name = "rtc_cmos", + .id = -1, + .num_resources = ARRAY_SIZE(rtc_cmos_resource), + .resource = rtc_cmos_resource +}; + +static __init int rtc_cmos_init(void) +{ + platform_device_register(&rtc_cmos_device); + + return 0; +} + +device_initcall(rtc_cmos_init); diff --git a/drivers/rtc/rtc-cmos.c b/drivers/rtc/rtc-cmos.c index 23e10b6..6f32ac5 100644 --- a/drivers/rtc/rtc-cmos.c +++ b/drivers/rtc/rtc-cmos.c @@ -691,7 +691,8 @@ cmos_do_probe(struct device *dev, struct resource *ports, int rtc_irq) */ #if defined(CONFIG_ATARI) address_space = 64; -#elif defined(__i386__) || defined(__x86_64__) || defined(__arm__) || defined(__sparc__) +#elif defined(__i386__) || defined(__x86_64__) || defined(__arm__) \ + || defined(__sparc__) || defined(__mips__) address_space = 128; #else #warning Assuming 128 bytes of RTC+NVRAM address space, not 64 bytes. @@ -756,9 +757,8 @@ cmos_do_probe(struct device *dev, struct resource *ports, int rtc_irq) /* FIXME teach the alarm code how to handle binary mode; * doesn't know 12-hour mode either. */ - if (is_valid_irq(rtc_irq) && - (!(rtc_control & RTC_24H) || (rtc_control & (RTC_DM_BINARY)))) { - dev_dbg(dev, "only 24-hr BCD mode supported\n"); + if (is_valid_irq(rtc_irq) && !(rtc_control & RTC_24H)) { + dev_dbg(dev, "only 24-hr supported\n"); retval = -ENXIO; goto cleanup1; } -- 1.6.0.4 From wuzhangjin@gmail.com Thu Jun 4 14:06:40 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 04 Jun 2009 14:06:47 +0100 (WEST) Received: from wa-out-1112.google.com ([209.85.146.178]:37218 "EHLO wa-out-1112.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20022601AbZFDNGG (ORCPT ); Thu, 4 Jun 2009 14:06:06 +0100 Received: by wa-out-1112.google.com with SMTP id n4so139210wag.0 for ; Thu, 04 Jun 2009 06:06:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer:in-reply-to:references; bh=aSyV5nnA5Gm3IDPtQOaGre2OdNsiKHPJvQVzrMfrifg=; b=pGzlEk8/sv5poElT6RxII+K2rg3X1IU0FQmLLqXhfOc8R4kY4WW6DnP85+2AltGDs3 vAMMCjCCIGy3AsY1hS/UA4Vssnf+9mNxCwbUJ8aS/tW1Z/7jJBthMr2tvLCyERVDvB5O IchybVFM0HZsFh9j1eeyDSlCPnDysJvnrkGJE= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; b=ZrCNVkTO8wa0nzlNVtzqiVO1hkSAQGjiz/DGH1++kaUexO1UA7bS2aEbAJRya23gMn bhqqvEbJ6TGr+IjUCBs3mVPnULO0lDb1ISKlcDehNKUksZInjXmWh/AIEU/kDjqs3RFw BAO9DTyklNl05qLUjcjKeihAcEOvEKyEtcAfs= Received: by 10.115.54.7 with SMTP id g7mr1626329wak.147.1244120763031; Thu, 04 Jun 2009 06:06:03 -0700 (PDT) Received: from localhost.localdomain ([202.201.14.140]) by mx.google.com with ESMTPS id m34sm10989704waf.56.2009.06.04.06.05.56 (version=TLSv1/SSLv3 cipher=RC4-MD5); Thu, 04 Jun 2009 06:06:01 -0700 (PDT) From: wuzhangjin@gmail.com To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: Wu Zhangjin , Yan Hua , Philippe Vachon , Zhang Le , Zhang Fuxin , loongson-dev , Liu Junliang , Erwan Lerale , Arnaud Patard , Wu Zhangjin Subject: [loongson-PATCH-v3 10/25] split the loongson-specific part out Date: Thu, 4 Jun 2009 21:05:48 +0800 Message-Id: X-Mailer: git-send-email 1.6.3.1 In-Reply-To: References: Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23253 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips From: Wu Zhangjin for sharing lots of loongson-specific source code among loongson-based machines, there is a need to split the loongson-specific part out to a common/ directory. and the machine-specific files are put in the machine-name/ directory. Signed-off-by: Wu Zhangjin --- arch/mips/Kconfig | 52 +++++------- arch/mips/Makefile | 5 +- arch/mips/include/asm/mach-loongson/loongson.h | 14 +++- arch/mips/loongson/Kconfig | 31 +++++++ arch/mips/loongson/Makefile | 11 +++ arch/mips/loongson/common/Makefile | 20 +++++ arch/mips/loongson/common/bonito-irq.c | 69 +++++++++++++++ arch/mips/loongson/common/cmdline.c | 80 +++++++++++++++++ arch/mips/loongson/common/early_printk.c | 28 ++++++ arch/mips/loongson/common/init.c | 40 +++++++++ arch/mips/loongson/common/irq.c | 109 ++++++++++++++++++++++++ arch/mips/loongson/common/mem.c | 40 +++++++++ arch/mips/loongson/common/misc.c | 15 +++ arch/mips/loongson/common/pci.c | 101 ++++++++++++++++++++++ arch/mips/loongson/common/reset.c | 38 ++++++++ arch/mips/loongson/common/rtc.c | 54 ++++++++++++ arch/mips/loongson/common/setup.c | 74 ++++++++++++++++ arch/mips/loongson/common/time.c | 27 ++++++ arch/mips/loongson/fuloong-2e/Makefile | 17 +--- arch/mips/loongson/fuloong-2e/bonito-irq.c | 69 --------------- arch/mips/loongson/fuloong-2e/cmdline.c | 77 ----------------- arch/mips/loongson/fuloong-2e/early_printk.c | 28 ------ arch/mips/loongson/fuloong-2e/init.c | 40 --------- arch/mips/loongson/fuloong-2e/irq.c | 88 +------------------ arch/mips/loongson/fuloong-2e/mem.c | 40 --------- arch/mips/loongson/fuloong-2e/misc.c | 15 --- arch/mips/loongson/fuloong-2e/pci.c | 102 ---------------------- arch/mips/loongson/fuloong-2e/reset.c | 36 +++------ arch/mips/loongson/fuloong-2e/rtc.c | 55 ------------ arch/mips/loongson/fuloong-2e/setup.c | 74 ---------------- arch/mips/loongson/fuloong-2e/time.c | 27 ------ 31 files changed, 791 insertions(+), 685 deletions(-) create mode 100644 arch/mips/loongson/Kconfig create mode 100644 arch/mips/loongson/Makefile create mode 100644 arch/mips/loongson/common/Makefile create mode 100644 arch/mips/loongson/common/bonito-irq.c create mode 100644 arch/mips/loongson/common/cmdline.c create mode 100644 arch/mips/loongson/common/early_printk.c create mode 100644 arch/mips/loongson/common/init.c create mode 100644 arch/mips/loongson/common/irq.c create mode 100644 arch/mips/loongson/common/mem.c create mode 100644 arch/mips/loongson/common/misc.c create mode 100644 arch/mips/loongson/common/pci.c create mode 100644 arch/mips/loongson/common/reset.c create mode 100644 arch/mips/loongson/common/rtc.c create mode 100644 arch/mips/loongson/common/setup.c create mode 100644 arch/mips/loongson/common/time.c delete mode 100644 arch/mips/loongson/fuloong-2e/bonito-irq.c delete mode 100644 arch/mips/loongson/fuloong-2e/cmdline.c delete mode 100644 arch/mips/loongson/fuloong-2e/early_printk.c delete mode 100644 arch/mips/loongson/fuloong-2e/init.c delete mode 100644 arch/mips/loongson/fuloong-2e/mem.c delete mode 100644 arch/mips/loongson/fuloong-2e/misc.c delete mode 100644 arch/mips/loongson/fuloong-2e/pci.c delete mode 100644 arch/mips/loongson/fuloong-2e/rtc.c delete mode 100644 arch/mips/loongson/fuloong-2e/setup.c delete mode 100644 arch/mips/loongson/fuloong-2e/time.c diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 4a7e61f..33a3bc6 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -6,7 +6,7 @@ config MIPS select HAVE_ARCH_KGDB # Horrible source of confusion. Die, die, die ... select EMBEDDED - select RTC_LIB if !LEMOTE_FULOONG2E + select RTC_LIB if !LOONGSON_SYSTEMS mainmenu "Linux/MIPS Kernel Configuration" @@ -153,30 +153,15 @@ config LASAT select SYS_SUPPORTS_64BIT_KERNEL if BROKEN select SYS_SUPPORTS_LITTLE_ENDIAN -config LEMOTE_FULOONG2E - bool "Lemote Fuloong(2e) mini-PC" - select ARCH_SPARSEMEM_ENABLE - select CEVT_R4K - select CSRC_R4K - select SYS_HAS_CPU_LOONGSON2 - select DMA_NONCOHERENT - select BOOT_ELF32 - select BOARD_SCACHE - select HAVE_STD_PC_SERIAL_PORT - select HW_HAS_PCI - select I8259 - select ISA - select IRQ_CPU - select SYS_SUPPORTS_32BIT_KERNEL - select SYS_SUPPORTS_64BIT_KERNEL - select SYS_SUPPORTS_LITTLE_ENDIAN - select SYS_SUPPORTS_HIGHMEM - select SYS_HAS_EARLY_PRINTK - select GENERIC_ISA_DMA_SUPPORT_BROKEN - select CPU_HAS_WB +config LOONGSON_SYSTEMS + bool "Loongson Based Machines" help - Lemote Fulong mini-PC board based on the Chinese Loongson-2E CPU and - an FPGA northbridge + This enables the support of Loongson based machines. + + Loongson is a family of general-purpose MIPS-compatible CPUs. + developed at Institute of Computing Technology (ICT), + Chinese Academy of Sciences (CAS) in the People's Republic + of China. The chief architect is Professor Weiwu Hu. config MIPS_MALTA bool "MIPS Malta board" @@ -642,6 +627,7 @@ source "arch/mips/sibyte/Kconfig" source "arch/mips/txx9/Kconfig" source "arch/mips/vr41xx/Kconfig" source "arch/mips/cavium-octeon/Kconfig" +source "arch/mips/loongson/Kconfig" endmenu @@ -1004,12 +990,10 @@ choice prompt "CPU type" default CPU_R4X00 -config CPU_LOONGSON2 - bool "Loongson 2" - depends on SYS_HAS_CPU_LOONGSON2 - select CPU_SUPPORTS_32BIT_KERNEL - select CPU_SUPPORTS_64BIT_KERNEL - select CPU_SUPPORTS_HIGHMEM +config CPU_LOONGSON2E + bool "Loongson 2E" + depends on SYS_HAS_CPU_LOONGSON2E + select CPU_LOONGSON2 help The Loongson 2E processor implements the MIPS III instruction set with many extensions. @@ -1252,7 +1236,13 @@ config CPU_CAVIUM_OCTEON endchoice -config SYS_HAS_CPU_LOONGSON2 +config CPU_LOONGSON2 + bool + select CPU_SUPPORTS_32BIT_KERNEL + select CPU_SUPPORTS_64BIT_KERNEL + select CPU_SUPPORTS_HIGHMEM + +config SYS_HAS_CPU_LOONGSON2E bool config SYS_HAS_CPU_MIPS32_R1 diff --git a/arch/mips/Makefile b/arch/mips/Makefile index 55181a4..6801baa 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -307,9 +307,10 @@ load-$(CONFIG_WR_PPMC) += 0xffffffff80100000 # # lemote fulong mini-PC board # -core-$(CONFIG_LEMOTE_FULOONG2E) +=arch/mips/loongson/fuloong-2e/ +core-$(CONFIG_LOONGSON_SYSTEMS) +=arch/mips/loongson/ +cflags-$(CONFIG_LOONGSON_SYSTEMS) += -I$(srctree)/arch/mips/include/asm/mach-loongson \ + -mno-branch-likely load-$(CONFIG_LEMOTE_FULOONG2E) +=0xffffffff80100000 -cflags-$(CONFIG_LEMOTE_FULOONG2E) += -I$(srctree)/arch/mips/include/asm/mach-loongson # # MIPS Malta board diff --git a/arch/mips/include/asm/mach-loongson/loongson.h b/arch/mips/include/asm/mach-loongson/loongson.h index 5ad629e..656511e 100644 --- a/arch/mips/include/asm/mach-loongson/loongson.h +++ b/arch/mips/include/asm/mach-loongson/loongson.h @@ -20,7 +20,7 @@ /* loongson internal northbridge initialization */ extern void bonito_irq_init(void); -/* command line */ +/* command line arguments */ extern unsigned long bus_clock, cpu_clock_freq; extern unsigned long memsize, highmemsize; @@ -31,6 +31,18 @@ extern void loongson_reboot_setup(void); extern void __init prom_init_memory(void); extern void __init prom_init_cmdline(void); +/* irq operation functions */ +extern void bonito_irqdispatch(void); +extern void i8259_irqdispatch(void); +extern void __init bonito_irq_init(void); +extern void __init set_irq_trigger_mode(void); +extern int mach_i8259_irq(void); +extern void mach_irq_dispatch(unsigned int pending); + +/* machine-specific reboot/halt operation */ +extern void mach_prepare_reboot(void); +extern void mach_prepare_shutdown(void); + #define LOONGSON_REG(x) \ (*(u32 *)((char *)CKSEG1ADDR(LOONGSON_REG_BASE) + (x))) #define LOONGSON_IRQ_BASE 32 diff --git a/arch/mips/loongson/Kconfig b/arch/mips/loongson/Kconfig new file mode 100644 index 0000000..5874bf6 --- /dev/null +++ b/arch/mips/loongson/Kconfig @@ -0,0 +1,31 @@ +choice + prompt "Machine Type" + depends on LOONGSON_SYSTEMS + +config LEMOTE_FULOONG2E + bool "Lemote Fuloong(2e) mini-PC" + select ARCH_SPARSEMEM_ENABLE + select CEVT_R4K + select CSRC_R4K + select SYS_HAS_CPU_LOONGSON2E + select DMA_NONCOHERENT + select BOOT_ELF32 + select BOARD_SCACHE + select HAVE_STD_PC_SERIAL_PORT + select HW_HAS_PCI + select I8259 + select ISA + select IRQ_CPU + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_64BIT_KERNEL + select SYS_SUPPORTS_LITTLE_ENDIAN + select SYS_SUPPORTS_HIGHMEM + select SYS_HAS_EARLY_PRINTK + select GENERIC_HARDIRQS_NO__DO_IRQ + select GENERIC_ISA_DMA_SUPPORT_BROKEN + select CPU_HAS_WB + help + Lemote Fulong mini-PC board based on the Chinese Loongson-2E CPU and + an FPGA northbridge + +endchoice diff --git a/arch/mips/loongson/Makefile b/arch/mips/loongson/Makefile new file mode 100644 index 0000000..cc9f1c8 --- /dev/null +++ b/arch/mips/loongson/Makefile @@ -0,0 +1,11 @@ +# +# Common code for all Loongson based systems +# + +obj-$(CONFIG_LOONGSON_SYSTEMS) += common/ + +# +# Lemote Fuloong mini-PC (Loongson 2E-based) +# + +obj-$(CONFIG_LEMOTE_FULOONG2E) += fuloong-2e/ diff --git a/arch/mips/loongson/common/Makefile b/arch/mips/loongson/common/Makefile new file mode 100644 index 0000000..79b2736 --- /dev/null +++ b/arch/mips/loongson/common/Makefile @@ -0,0 +1,20 @@ +# +# Makefile for loongson based machines. +# + +obj-y += setup.o init.o cmdline.o time.o reset.o irq.o \ + pci.o bonito-irq.o mem.o misc.o + +# +# Early printk support +# +obj-$(CONFIG_EARLY_PRINTK) += early_printk.o + +# +# Enable RTC Class support +# +# please enable CONFIG_RTC_DRV_CMOS +# +obj-$(CONFIG_RTC_DRV_CMOS) += rtc.o + +EXTRA_CFLAGS += -Werror diff --git a/arch/mips/loongson/common/bonito-irq.c b/arch/mips/loongson/common/bonito-irq.c new file mode 100644 index 0000000..1f43447 --- /dev/null +++ b/arch/mips/loongson/common/bonito-irq.c @@ -0,0 +1,69 @@ +/* + * Copyright 2001 MontaVista Software Inc. + * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net + * Copyright (C) 2000, 2001 Ralf Baechle (ralf@gnu.org) + * + * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology + * Author: Fuxin Zhang, zhangfx@lemote.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ + +#include + +#include +#include + +static inline void bonito_irq_enable(unsigned int irq) +{ + LOONGSON_INTENSET = (1 << (irq - LOONGSON_IRQ_BASE)); + mmiowb(); +} + +static inline void bonito_irq_disable(unsigned int irq) +{ + LOONGSON_INTENCLR = (1 << (irq - LOONGSON_IRQ_BASE)); + mmiowb(); +} + +static struct irq_chip bonito_irq_type = { + .name = "bonito_irq", + .ack = bonito_irq_disable, + .mask = bonito_irq_disable, + .mask_ack = bonito_irq_disable, + .unmask = bonito_irq_enable, +}; + +static struct irqaction dma_timeout_irqaction = { + .handler = no_action, + .name = "dma_timeout", +}; + +void bonito_irq_init(void) +{ + u32 i; + + for (i = LOONGSON_IRQ_BASE; i < LOONGSON_IRQ_BASE + 32; i++) + set_irq_chip_and_handler(i, &bonito_irq_type, handle_level_irq); + + setup_irq(LOONGSON_DMATIMEOUT_IRQ, &dma_timeout_irqaction); +} diff --git a/arch/mips/loongson/common/cmdline.c b/arch/mips/loongson/common/cmdline.c new file mode 100644 index 0000000..6f603ac --- /dev/null +++ b/arch/mips/loongson/common/cmdline.c @@ -0,0 +1,80 @@ +/* + * Based on Ocelot Linux port, which is + * Copyright 2001 MontaVista Software Inc. + * Author: jsun@mvista.com or jsun@junsun.net + * + * Copyright 2003 ICT CAS + * Author: Michael Guo + * + * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology + * Author: Fuxin Zhang, zhangfx@lemote.com + * + * Copyright (C) 2009 Lemote Inc. & Insititute of Computing Technology + * Author: Wu Zhangjin, wuzj@lemote.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include + +#include + +unsigned long bus_clock, cpu_clock_freq; +unsigned long memsize, highmemsize; + +int prom_argc; +/* pmon passes arguments in 32bit pointers */ +int *_prom_argv, *_prom_envp; + +#define parse_even_earlier(res, option, p) \ +do { \ + if (strncmp(option, (char *)p, strlen(option)) == 0) \ + strict_strtol((char *)p + strlen(option"="), \ + 10, &res); \ +} while (0) + +void __init prom_init_cmdline(void) +{ + int i; + long l; + prom_argc = fw_arg0; + _prom_argv = (int *)fw_arg1; + _prom_envp = (int *)fw_arg2; + + /* arg[0] is "g", the rest is boot parameters */ + arcs_cmdline[0] = '\0'; + for (i = 1; i < prom_argc; i++) { + l = (long)_prom_argv[i]; + if (strlen(arcs_cmdline) + strlen(((char *)l) + 1) + >= sizeof(arcs_cmdline)) + break; + strcat(arcs_cmdline, ((char *)l)); + strcat(arcs_cmdline, " "); + } + + /* handle console, root, busclock, cpuclock, memsize, highmemsize + arguments */ + + if ((strstr(arcs_cmdline, "console=")) == NULL) + strcat(arcs_cmdline, " console=ttyS0,115200"); + if ((strstr(arcs_cmdline, "root=")) == NULL) + strcat(arcs_cmdline, " root=/dev/hda1"); + + l = (long)*_prom_envp; + while (l != 0) { + parse_even_earlier(bus_clock, "busclock", l); + parse_even_earlier(cpu_clock_freq, "cpuclock", l); + parse_even_earlier(memsize, "memsize", l); + parse_even_earlier(highmemsize, "highmemsize", l); + _prom_envp++; + l = (long)*_prom_envp; + } + if (memsize == 0) + memsize = 256; + + pr_info("busclock=%ld, cpuclock=%ld, memsize=%ld, highmemsize=%ld\n", + bus_clock, cpu_clock_freq, memsize, highmemsize); +} diff --git a/arch/mips/loongson/common/early_printk.c b/arch/mips/loongson/common/early_printk.c new file mode 100644 index 0000000..9f4b881 --- /dev/null +++ b/arch/mips/loongson/common/early_printk.c @@ -0,0 +1,28 @@ +/* early printk support + * + * Copyright (c) 2009 Philippe Vachon + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include +#include + +#include +#include + +void prom_putchar(char c) +{ + int timeout; + phys_addr_t uart_base = + (phys_addr_t) ioremap_nocache(LOONGSON_UART_BASE, 8); + char reg = readb((u8 *) (uart_base + UART_LSR)) & UART_LSR_THRE; + + for (timeout = 1024; reg == 0 && timeout > 0; timeout--) + reg = readb((u8 *) (uart_base + UART_LSR)) & UART_LSR_THRE; + + writeb(c, (u8 *) (uart_base + UART_TX)); +} diff --git a/arch/mips/loongson/common/init.c b/arch/mips/loongson/common/init.c new file mode 100644 index 0000000..76e6fda --- /dev/null +++ b/arch/mips/loongson/common/init.c @@ -0,0 +1,40 @@ +/* + * Based on Ocelot Linux port, which is + * Copyright 2001 MontaVista Software Inc. + * Author: jsun@mvista.com or jsun@junsun.net + * + * Copyright 2003 ICT CAS + * Author: Michael Guo + * + * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology + * Author: Fuxin Zhang, zhangfx@lemote.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include + +#include +#include + +#include + +void __init prom_init(void) +{ + /* init mach type, does we need to init it?? */ + mips_machtype = PRID_IMP_LOONGSON2; + + /* init several base address */ + set_io_port_base((unsigned long) + ioremap(LOONGSON_PCIIO_BASE, LOONGSON_PCIIO_SIZE)); + + prom_init_cmdline(); + prom_init_memory(); +} + +void __init prom_free_prom_memory(void) +{ +} diff --git a/arch/mips/loongson/common/irq.c b/arch/mips/loongson/common/irq.c new file mode 100644 index 0000000..5834f35 --- /dev/null +++ b/arch/mips/loongson/common/irq.c @@ -0,0 +1,109 @@ +/* + * Copyright 2001 MontaVista Software Inc. + * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net + * Copyright (C) 2000, 2001 Ralf Baechle (ralf@gnu.org) + * + * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology + * Author: Fuxin Zhang, zhangfx@lemote.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include +#include + +#include +#include + +#include +#include + +/* + * the first level int-handler will jump here if it is a loongson irq + */ +void bonito_irqdispatch(void) +{ + u32 int_status; + int i; + + /* workaround the IO dma problem: let cpu looping to allow DMA finish */ + int_status = LOONGSON_INTISR; + while (int_status & (1 << 10)) { + udelay(1); + int_status = LOONGSON_INTISR; + } + + /* Get pending sources, masked by current enables */ + int_status = LOONGSON_INTISR & LOONGSON_INTEN; + + if (int_status != 0) { + i = __ffs(int_status); + int_status &= ~(1 << i); + do_IRQ(LOONGSON_IRQ_BASE + i); + } +} + +void i8259_irqdispatch(void) +{ + int irq; + + irq = mach_i8259_irq(); + if (irq < 0) + spurious_interrupt(); + else + do_IRQ(irq); +} + +asmlinkage void plat_irq_dispatch(void) +{ + unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM; + + mach_irq_dispatch(pending); +} + + +static struct irqaction cascade_irqaction = { + .handler = no_action, + .name = "cascade", +}; + +void __init arch_init_irq(void) +{ + /* + * Clear all of the interrupts while we change the able around a bit. + * int-handler is not on bootstrap + */ + clear_c0_status(ST0_IM | ST0_BEV); + local_irq_disable(); + + /* setting irq trigger mode */ + set_irq_trigger_mode(); + + /* no steer */ + LOONGSON_INTSTEER = 0; + + /* + * Mask out all interrupt by writing "1" to all bit position in + * the interrupt reset reg. + */ + LOONGSON_INTENCLR = ~0; + + /* init all controller + * 0-15 ------> i8259 interrupt + * 16-23 ------> mips cpu interrupt + * 32-63 ------> bonito irq + */ + + /* Sets the first-level interrupt dispatcher. */ + mips_cpu_irq_init(); + init_i8259_irqs(); + bonito_irq_init(); + + /* setup north bridge irq (bonito) */ + setup_irq(LOONGSON_NORTH_BRIDGE_IRQ, &cascade_irqaction); + /* setup source bridge irq (i8259) */ + setup_irq(LOONGSON_SOUTH_BRIDGE_IRQ, &cascade_irqaction); +} diff --git a/arch/mips/loongson/common/mem.c b/arch/mips/loongson/common/mem.c new file mode 100644 index 0000000..17a7278 --- /dev/null +++ b/arch/mips/loongson/common/mem.c @@ -0,0 +1,40 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include +#include + +#include + +#include +#include + +void __init prom_init_memory(void) +{ + add_memory_region(0x0, (memsize << 20), BOOT_MEM_RAM); +#ifdef CONFIG_64BIT + if (highmemsize > 0) { + add_memory_region(LOONGSON_HIGHMEM_START, + highmemsize << 20, BOOT_MEM_RAM); + } +#endif /* CONFIG_64BIT */ +} + +/* override of arch/mips/mm/cache.c: __uncached_access */ +int __uncached_access(struct file *file, unsigned long addr) +{ + if (file->f_flags & O_SYNC) + return 1; + + /* + * On the Lemote Loongson 2e system, the peripheral registers + * reside between 0x1000:0000 and 0x2000:0000. + */ + return addr >= __pa(high_memory) || + ((addr >= LOONGSON_MMIO_MEM_START) && \ + (addr < LOONGSON_MMIO_MEM_END)); +} diff --git a/arch/mips/loongson/common/misc.c b/arch/mips/loongson/common/misc.c new file mode 100644 index 0000000..1b8044c --- /dev/null +++ b/arch/mips/loongson/common/misc.c @@ -0,0 +1,15 @@ +/* Copyright (C) 2009 Lemote Inc. & Insititute of Computing Technology + * Author: Wu Zhangjin, wuzj@lemote.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include + +const char *get_system_type(void) +{ + return MACH_NAME; +} diff --git a/arch/mips/loongson/common/pci.c b/arch/mips/loongson/common/pci.c new file mode 100644 index 0000000..e97c845 --- /dev/null +++ b/arch/mips/loongson/common/pci.c @@ -0,0 +1,101 @@ +/* + * Copyright (C) 2007 Lemote, Inc. & Institute of Computing Technology + * Author: Fuxin Zhang, zhangfx@lemote.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + */ + +#include + +#include +#include + +static struct resource loongson_pci_mem_resource = { + .name = "LOONGSON PCI MEM", + .start = LOONGSON_PCI_MEM_START, + .end = LOONGSON_PCI_MEM_END, + .flags = IORESOURCE_MEM, +}; + +static struct resource loongson_pci_io_resource = { + .name = "LOONGSON PCI IO MEM", + .start = LOONGSON_PCI_IO_START, + .end = IO_SPACE_LIMIT, + .flags = IORESOURCE_IO, +}; + +static struct pci_controller loongson_pci_controller = { + .pci_ops = &loongson_pci_ops, + .io_resource = &loongson_pci_io_resource, + .mem_resource = &loongson_pci_mem_resource, + .mem_offset = 0x00000000UL, + .io_offset = 0x00000000UL, +}; + +static void __init ict_pcimap(void) +{ + /* + * local to PCI mapping for CPU accessing PCI space + * + * CPU address space [256M,448M] is window for accessing pci space + * we set pcimap_lo[0,1,2] to map it to pci space[0M,64M], [320M,448M] + * + * pcimap: PCI_MAP2 PCI_Mem_Lo2 PCI_Mem_Lo1 PCI_Mem_Lo0 + * [<2G] [384M,448M] [320M,384M] [0M,64M] + */ + LOONGSON_PCIMAP = LOONGSON_PCIMAP_PCIMAP_2 | + LOONGSON_PCIMAP_WIN(2, 0x18000000) | + LOONGSON_PCIMAP_WIN(1, 0x14000000) | + LOONGSON_PCIMAP_WIN(0, 0); + + /* + * PCI-DMA to local mapping: [2G,2G+256M] -> [0M,256M] + */ + LOONGSON_PCIBASE0 = 0x80000000ul; /* base: 2G -> mmap: 0M */ + /* size: 256M, burst transmission, pre-fetch enable, 64bit */ + LOONGSON_PCI_HIT0_SEL_L = 0xc000000cul; + LOONGSON_PCI_HIT0_SEL_H = 0xfffffffful; + LOONGSON_PCI_HIT1_SEL_L = 0x00000006ul; /* set this BAR as invalid */ + LOONGSON_PCI_HIT1_SEL_H = 0x00000000ul; + LOONGSON_PCI_HIT2_SEL_L = 0x00000006ul; /* set this BAR as invalid */ + LOONGSON_PCI_HIT2_SEL_H = 0x00000000ul; + + /* avoid deadlock of PCI reading/writing lock operation */ + LOONGSON_PCI_ISR4C = 0xd2000001ul; + + /* can not change gnt to break pci transfer when device's gnt not + deassert for some broken device */ + LOONGSON_PXARB_CFG = 0x00fe0105ul; +} + +static int __init pcibios_init(void) +{ + ict_pcimap(); + + loongson_pci_controller.io_map_base = mips_io_port_base; + + register_pci_controller(&loongson_pci_controller); + + return 0; +} + +arch_initcall(pcibios_init); diff --git a/arch/mips/loongson/common/reset.c b/arch/mips/loongson/common/reset.c new file mode 100644 index 0000000..c3431fb --- /dev/null +++ b/arch/mips/loongson/common/reset.c @@ -0,0 +1,38 @@ +/* + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * Copyright (C) 2007 Lemote, Inc. & Institute of Computing Technology + * Author: Fuxin Zhang, zhangfx@lemote.com + */ + +#include + +#include + +#include + +static void loongson_restart(char *command) +{ + /* perform board-specific pre-reboot operations */ + mach_prepare_reboot(); + + /* reboot via jumping to 0xbfc00000 */ + ((void (*)(void))ioremap_nocache(LOONGSON_BOOT_BASE, 4)) (); +} + +static void loongson_halt(void) +{ + mach_prepare_shutdown(); + while (1) + ; +} + +void __init loongson_reboot_setup(void) +{ + _machine_restart = loongson_restart; + _machine_halt = loongson_halt; + pm_power_off = loongson_halt; +} diff --git a/arch/mips/loongson/common/rtc.c b/arch/mips/loongson/common/rtc.c new file mode 100644 index 0000000..1eb39b4 --- /dev/null +++ b/arch/mips/loongson/common/rtc.c @@ -0,0 +1,54 @@ +/* + * Registration of Cobalt RTC platform device. + * + * Copyright (C) 2007 Yoichi Yuasa + * Copyright (C) 2009 Wu Zhangjin + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include +#include +#include + +static struct resource rtc_cmos_resource[] = { + { + .start = RTC_PORT(0), + .end = RTC_PORT(1), + .flags = IORESOURCE_IO, + }, + { + .start = RTC_IRQ, + .end = RTC_IRQ, + .flags = IORESOURCE_IRQ, + }, +}; + +static struct platform_device rtc_cmos_device = { + .name = "rtc_cmos", + .id = -1, + .num_resources = ARRAY_SIZE(rtc_cmos_resource), + .resource = rtc_cmos_resource +}; + +static __init int rtc_cmos_init(void) +{ + platform_device_register(&rtc_cmos_device); + + return 0; +} + +device_initcall(rtc_cmos_init); diff --git a/arch/mips/loongson/common/setup.c b/arch/mips/loongson/common/setup.c new file mode 100644 index 0000000..4fcbe48 --- /dev/null +++ b/arch/mips/loongson/common/setup.c @@ -0,0 +1,74 @@ +/* + * board dependent setup routines + * + * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology + * Author: Fuxin Zhang, zhangfx@lemote.com + * + * Copyright (C) 2009 Lemote Inc. & Insititute of Computing Technology + * Author: Wu Zhangjin, wuzj@lemote.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include + +#include + +#include + +void (*__wbflush) (void); +EXPORT_SYMBOL(__wbflush); + +static void loongson_wbflush(void) +{ + asm(".set\tpush\n\t" + ".set\tnoreorder\n\t" + ".set mips3\n\t" + "sync\n\t" + "nop\n\t" + ".set\tpop\n\t" + ".set mips0\n\t"); +} + +void __init loongson_wbflush_setup(void) +{ + __wbflush = loongson_wbflush; +} + +#if defined(CONFIG_VT) && defined(CONFIG_VGA_CONSOLE) +#include + +void __init loongson_screeninfo_setup(void) +{ + screen_info = (struct screen_info) { + 0, /* orig-x */ + 25, /* orig-y */ + 0, /* unused */ + 0, /* orig-video-page */ + 0, /* orig-video-mode */ + 80, /* orig-video-cols */ + 0, /* ega_ax */ + 0, /* ega_bx */ + 0, /* ega_cx */ + 25, /* orig-video-lines */ + VIDEO_TYPE_VGAC, /* orig-video-isVGA */ + 16 /* orig-video-points */ + }; +} +#else +void __init loongson_screeninfo_setup(void) +{ +} +#endif + +void __init plat_mem_setup(void) +{ + loongson_reboot_setup(); + + loongson_wbflush_setup(); + + loongson_screeninfo_setup(); +} diff --git a/arch/mips/loongson/common/time.c b/arch/mips/loongson/common/time.c new file mode 100644 index 0000000..231f0c2 --- /dev/null +++ b/arch/mips/loongson/common/time.c @@ -0,0 +1,27 @@ +/* + * board dependent boot routines + * + * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology + * Author: Fuxin Zhang, zhangfx@lemote.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include +#include + +#include + +unsigned long read_persistent_clock(void) +{ + return mc146818_get_cmos_time(); +} + +void __init plat_time_init(void) +{ + /* setup mips r4k timer */ + mips_hpt_frequency = cpu_clock_freq / 2; +} diff --git a/arch/mips/loongson/fuloong-2e/Makefile b/arch/mips/loongson/fuloong-2e/Makefile index 76904da..1ee57a1 100644 --- a/arch/mips/loongson/fuloong-2e/Makefile +++ b/arch/mips/loongson/fuloong-2e/Makefile @@ -1,20 +1,7 @@ # -# Makefile for Lemote Fulong mini-PC board. +# Makefile for fuloong-2e # -obj-y += setup.o init.o cmdline.o time.o reset.o irq.o \ - pci.o bonito-irq.o mem.o misc.o - -# -# Early printk support -# -obj-$(CONFIG_EARLY_PRINTK) += early_printk.o - -# -# Enable RTC Class support -# -# please enable CONFIG_RTC_DRV_CMOS -# -obj-$(CONFIG_RTC_DRV_CMOS) += rtc.o +obj-y += irq.o reset.o EXTRA_CFLAGS += -Werror diff --git a/arch/mips/loongson/fuloong-2e/bonito-irq.c b/arch/mips/loongson/fuloong-2e/bonito-irq.c deleted file mode 100644 index 1f43447..0000000 --- a/arch/mips/loongson/fuloong-2e/bonito-irq.c +++ /dev/null @@ -1,69 +0,0 @@ -/* - * Copyright 2001 MontaVista Software Inc. - * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net - * Copyright (C) 2000, 2001 Ralf Baechle (ralf@gnu.org) - * - * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology - * Author: Fuxin Zhang, zhangfx@lemote.com - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - * - */ - -#include - -#include -#include - -static inline void bonito_irq_enable(unsigned int irq) -{ - LOONGSON_INTENSET = (1 << (irq - LOONGSON_IRQ_BASE)); - mmiowb(); -} - -static inline void bonito_irq_disable(unsigned int irq) -{ - LOONGSON_INTENCLR = (1 << (irq - LOONGSON_IRQ_BASE)); - mmiowb(); -} - -static struct irq_chip bonito_irq_type = { - .name = "bonito_irq", - .ack = bonito_irq_disable, - .mask = bonito_irq_disable, - .mask_ack = bonito_irq_disable, - .unmask = bonito_irq_enable, -}; - -static struct irqaction dma_timeout_irqaction = { - .handler = no_action, - .name = "dma_timeout", -}; - -void bonito_irq_init(void) -{ - u32 i; - - for (i = LOONGSON_IRQ_BASE; i < LOONGSON_IRQ_BASE + 32; i++) - set_irq_chip_and_handler(i, &bonito_irq_type, handle_level_irq); - - setup_irq(LOONGSON_DMATIMEOUT_IRQ, &dma_timeout_irqaction); -} diff --git a/arch/mips/loongson/fuloong-2e/cmdline.c b/arch/mips/loongson/fuloong-2e/cmdline.c deleted file mode 100644 index 01e30db..0000000 --- a/arch/mips/loongson/fuloong-2e/cmdline.c +++ /dev/null @@ -1,77 +0,0 @@ -/* - * Based on Ocelot Linux port, which is - * Copyright 2001 MontaVista Software Inc. - * Author: jsun@mvista.com or jsun@junsun.net - * - * Copyright 2003 ICT CAS - * Author: Michael Guo - * - * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology - * Author: Fuxin Zhang, zhangfx@lemote.com - * - * Copyright (C) 2009 Lemote Inc. & Insititute of Computing Technology - * Author: Wu Zhangjin, wuzj@lemote.com - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#include - -#include - -unsigned long bus_clock, cpu_clock_freq; -unsigned long memsize, highmemsize; - -int prom_argc; -/* pmon passes arguments in 32bit pointers */ -int *_prom_argv, *_prom_envp; - -#define parse_even_earlier(res, option, p) \ -do { \ - if (strncmp(option, (char *)p, strlen(option)) == 0) \ - strict_strtol((char *)p + strlen(option"="), \ - 10, &res); \ -} while (0) - -void __init prom_init_cmdline(void) -{ - int i; - long l; - prom_argc = fw_arg0; - _prom_argv = (int *)fw_arg1; - _prom_envp = (int *)fw_arg2; - - /* arg[0] is "g", the rest is boot parameters */ - arcs_cmdline[0] = '\0'; - for (i = 1; i < prom_argc; i++) { - l = (long)_prom_argv[i]; - if (strlen(arcs_cmdline) + strlen(((char *)l) + 1) - >= sizeof(arcs_cmdline)) - break; - strcat(arcs_cmdline, ((char *)l)); - strcat(arcs_cmdline, " "); - } - - if ((strstr(arcs_cmdline, "console=")) == NULL) - strcat(arcs_cmdline, " console=ttyS0,115200"); - if ((strstr(arcs_cmdline, "root=")) == NULL) - strcat(arcs_cmdline, " root=/dev/hda1"); - - l = (long)*_prom_envp; - while (l != 0) { - parse_even_earlier(bus_clock, "busclock", l); - parse_even_earlier(cpu_clock_freq, "cpuclock", l); - parse_even_earlier(memsize, "memsize", l); - parse_even_earlier(highmemsize, "highmemsize", l); - _prom_envp++; - l = (long)*_prom_envp; - } - if (memsize == 0) - memsize = 256; - - pr_info("busclock=%ld, cpuclock=%ld, memsize=%ld, highmemsize=%ld\n", - bus_clock, cpu_clock_freq, memsize, highmemsize); -} diff --git a/arch/mips/loongson/fuloong-2e/early_printk.c b/arch/mips/loongson/fuloong-2e/early_printk.c deleted file mode 100644 index 9f4b881..0000000 --- a/arch/mips/loongson/fuloong-2e/early_printk.c +++ /dev/null @@ -1,28 +0,0 @@ -/* early printk support - * - * Copyright (c) 2009 Philippe Vachon - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#include -#include - -#include -#include - -void prom_putchar(char c) -{ - int timeout; - phys_addr_t uart_base = - (phys_addr_t) ioremap_nocache(LOONGSON_UART_BASE, 8); - char reg = readb((u8 *) (uart_base + UART_LSR)) & UART_LSR_THRE; - - for (timeout = 1024; reg == 0 && timeout > 0; timeout--) - reg = readb((u8 *) (uart_base + UART_LSR)) & UART_LSR_THRE; - - writeb(c, (u8 *) (uart_base + UART_TX)); -} diff --git a/arch/mips/loongson/fuloong-2e/init.c b/arch/mips/loongson/fuloong-2e/init.c deleted file mode 100644 index 76e6fda..0000000 --- a/arch/mips/loongson/fuloong-2e/init.c +++ /dev/null @@ -1,40 +0,0 @@ -/* - * Based on Ocelot Linux port, which is - * Copyright 2001 MontaVista Software Inc. - * Author: jsun@mvista.com or jsun@junsun.net - * - * Copyright 2003 ICT CAS - * Author: Michael Guo - * - * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology - * Author: Fuxin Zhang, zhangfx@lemote.com - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#include - -#include -#include - -#include - -void __init prom_init(void) -{ - /* init mach type, does we need to init it?? */ - mips_machtype = PRID_IMP_LOONGSON2; - - /* init several base address */ - set_io_port_base((unsigned long) - ioremap(LOONGSON_PCIIO_BASE, LOONGSON_PCIIO_SIZE)); - - prom_init_cmdline(); - prom_init_memory(); -} - -void __init prom_free_prom_memory(void) -{ -} diff --git a/arch/mips/loongson/fuloong-2e/irq.c b/arch/mips/loongson/fuloong-2e/irq.c index 7bf9e18..9057709 100644 --- a/arch/mips/loongson/fuloong-2e/irq.c +++ b/arch/mips/loongson/fuloong-2e/irq.c @@ -24,57 +24,20 @@ * */ -#include #include -#include #include #include #include -/* - * the first level int-handler will jump here if it is a bonito irq - */ -static void bonito_irqdispatch(void) -{ - u32 int_status; - int i; - - /* workaround the IO dma problem: let cpu looping to allow DMA finish */ - int_status = LOONGSON_INTISR; - if (int_status & (1 << 10)) { - while (int_status & (1 << 10)) { - udelay(1); - int_status = LOONGSON_INTISR; - } - } - - /* Get pending sources, masked by current enables */ - int_status = LOONGSON_INTISR & LOONGSON_INTEN; - - if (int_status != 0) { - i = __ffs(int_status); - int_status &= ~(1 << i); - do_IRQ(LOONGSON_IRQ_BASE + i); - } -} - -static void i8259_irqdispatch(void) +int mach_i8259_irq(void) { - int irq; - - irq = i8259_irq(); - if (irq >= 0) - do_IRQ(irq); - else - spurious_interrupt(); + return i8259_irq(); } -asmlinkage void plat_irq_dispatch(void) +void mach_irq_dispatch(unsigned int pending) { - unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM; - if (pending & CAUSEF_IP7) do_IRQ(LOONGSON_TIMER_IRQ); else if (pending & CAUSEF_IP5) @@ -85,52 +48,9 @@ asmlinkage void plat_irq_dispatch(void) spurious_interrupt(); } -static struct irqaction cascade_irqaction = { - .handler = no_action, - .name = "cascade", -}; - -void __init arch_init_irq(void) +void __init set_irq_trigger_mode(void) { - /* - * Clear all of the interrupts while we change the able around a bit. - * int-handler is not on bootstrap - */ - clear_c0_status(ST0_IM | ST0_BEV); - local_irq_disable(); - /* most bonito irq should be level triggered */ LOONGSON_INTEDGE = LOONGSON_ICU_SYSTEMERR | LOONGSON_ICU_MASTERERR | LOONGSON_ICU_RETRYERR | LOONGSON_ICU_MBOXES; - LOONGSON_INTSTEER = 0; - - /* - * Mask out all interrupt by writing "1" to all bit position in - * the interrupt reset reg. - */ - LOONGSON_INTENCLR = ~0; - - /* init all controller - * 0-15 ------> i8259 interrupt - * 16-23 ------> mips cpu interrupt - * 32-63 ------> bonito irq - */ - - /* Sets the first-level interrupt dispatcher. */ - mips_cpu_irq_init(); - init_i8259_irqs(); - bonito_irq_init(); - - /* - printk("GPIODATA=%x, GPIOIE=%x\n", LOONGSON_GPIODATA, LOONGSON_GPIOIE); - printk("INTEN=%x, INTSET=%x, INTCLR=%x, INTISR=%x\n", - LOONGSON_INTEN, LOONGSON_INTENSET, - LOONGSON_INTENCLR, LOONGSON_INTISR); - */ - - /* bonito irq at IP2 */ - setup_irq(LOONGSON_NORTH_BRIDGE_IRQ, &cascade_irqaction); - /* 8259 irq at IP5 */ - setup_irq(LOONGSON_SOUTH_BRIDGE_IRQ, &cascade_irqaction); - } diff --git a/arch/mips/loongson/fuloong-2e/mem.c b/arch/mips/loongson/fuloong-2e/mem.c deleted file mode 100644 index 7f6ee37..0000000 --- a/arch/mips/loongson/fuloong-2e/mem.c +++ /dev/null @@ -1,40 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#include -#include - -#include - -#include -#include - -void __init prom_init_memory(void) -{ - add_memory_region(0x0, (memsize << 20), BOOT_MEM_RAM); -#ifdef CONFIG_64BIT - if (highmemsize > 0) { - add_memory_region(LOONGSON_HIGHMEM_START, - highmemsize << 20, BOOT_MEM_RAM); - } -#endif /* CONFIG_64BIT */ -} - -/* override of arch/mips/mm/cache.c: __uncached_access */ -int __uncached_access(struct file *file, unsigned long addr) -{ - if (file->f_flags & O_SYNC) - return 1; - - /* - * On the Lemote Loongson 2e system, the peripheral registers - * reside between 0x1000:0000 and 0x2000:0000. - */ - return addr >= __pa(high_memory) || \ - ((addr >= LOONGSON_MMIO_MEM_START) && \ - (addr < LOONGSON_MMIO_MEM_END)); -} diff --git a/arch/mips/loongson/fuloong-2e/misc.c b/arch/mips/loongson/fuloong-2e/misc.c deleted file mode 100644 index 1b8044c..0000000 --- a/arch/mips/loongson/fuloong-2e/misc.c +++ /dev/null @@ -1,15 +0,0 @@ -/* Copyright (C) 2009 Lemote Inc. & Insititute of Computing Technology - * Author: Wu Zhangjin, wuzj@lemote.com - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#include - -const char *get_system_type(void) -{ - return MACH_NAME; -} diff --git a/arch/mips/loongson/fuloong-2e/pci.c b/arch/mips/loongson/fuloong-2e/pci.c deleted file mode 100644 index 89bc1af..0000000 --- a/arch/mips/loongson/fuloong-2e/pci.c +++ /dev/null @@ -1,102 +0,0 @@ -/* - * pci.c - * - * Copyright (C) 2007 Lemote, Inc. & Institute of Computing Technology - * Author: Fuxin Zhang, zhangfx@lemote.com - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - * - */ -#include - -#include -#include - -static struct resource loongson_pci_mem_resource = { - .name = "LOONGSON PCI MEM", - .start = LOONGSON_PCI_MEM_START, - .end = LOONGSON_PCI_MEM_END, - .flags = IORESOURCE_MEM, -}; - -static struct resource loongson_pci_io_resource = { - .name = "LOONGSON PCI IO MEM", - .start = LOONGSON_PCI_IO_START, - .end = IO_SPACE_LIMIT, - .flags = IORESOURCE_IO, -}; - -static struct pci_controller loongson_pci_controller = { - .pci_ops = &loongson_pci_ops, - .io_resource = &loongson_pci_io_resource, - .mem_resource = &loongson_pci_mem_resource, - .mem_offset = 0x00000000UL, - .io_offset = 0x00000000UL, -}; - -static void __init ict_pcimap(void) -{ - /* - * local to PCI mapping for CPU accessing PCI space - * - * CPU address space [256M,448M] is window for accessing pci space - * we set pcimap_lo[0,1,2] to map it to pci space[0M, 64M], [320M,448M] - * - * pcimap: PCI_MAP2 PCI_Mem_Lo2 PCI_Mem_Lo1 PCI_Mem_Lo0 - * [<2G] [384M,448M] [320M,384M] [0M,64M] - */ - LOONGSON_PCIMAP = LOONGSON_PCIMAP_PCIMAP_2 | - LOONGSON_PCIMAP_WIN(2, 0x18000000) | - LOONGSON_PCIMAP_WIN(1, 0x14000000) | - LOONGSON_PCIMAP_WIN(0, 0); - - /* - * PCI-DMA to local mapping: [2G,2G+256M] -> [0M,256M] - */ - LOONGSON_PCIBASE0 = 0x80000000ul; /* base: 2G -> mmap: 0M */ - /* size: 256M, burst transmission, pre-fetch enable, 64bit */ - LOONGSON_PCI_HIT0_SEL_L = 0xc000000cul; - LOONGSON_PCI_HIT0_SEL_H = 0xfffffffful; - LOONGSON_PCI_HIT1_SEL_L = 0x00000006ul; /* set this BAR as invalid */ - LOONGSON_PCI_HIT1_SEL_H = 0x00000000ul; - LOONGSON_PCI_HIT2_SEL_L = 0x00000006ul; /* set this BAR as invalid */ - LOONGSON_PCI_HIT2_SEL_H = 0x00000000ul; - - /* avoid deadlock of PCI reading/writing lock operation */ - LOONGSON_PCI_ISR4C = 0xd2000001ul; - - /* can not change gnt to break pci transfer when device's gnt not - deassert for some broken device */ - LOONGSON_PXARB_CFG = 0x00fe0105ul; -} - -static int __init pcibios_init(void) -{ - ict_pcimap(); - - loongson_pci_controller.io_map_base = mips_io_port_base; - - register_pci_controller(&loongson_pci_controller); - - return 0; -} - -arch_initcall(pcibios_init); diff --git a/arch/mips/loongson/fuloong-2e/reset.c b/arch/mips/loongson/fuloong-2e/reset.c index 87244a1..4ad0923 100644 --- a/arch/mips/loongson/fuloong-2e/reset.c +++ b/arch/mips/loongson/fuloong-2e/reset.c @@ -1,40 +1,26 @@ -/* +/* Board-specific reboot/shutdown routines + * Copyright (c) 2009 Philippe Vachon + * + * Copyright (C) 2009 Lemote Inc. & Insititute of Computing Technology + * Author: Wu Zhangjin, wuzj@lemote.com + * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the * Free Software Foundation; either version 2 of the License, or (at your * option) any later version. - * - * Copyright (C) 2007 Lemote, Inc. & Institute of Computing Technology - * Author: Fuxin Zhang, zhangfx@lemote.com - * - * Copyright (c) 2009 Philippe Vachon - * - * Copyright (c) 2009 Lemote, Inc. & Institute of Computing Technology - * Author: Wu Zhangjin, wuzj@lemote.com */ -#include -#include +#include +#include + #include -static void loongson_restart(char *command) +void mach_prepare_reboot(void) { LOONGSON_GENCFG &= ~LOONGSON_GENCFG_CPUSELFRESET; LOONGSON_GENCFG |= LOONGSON_GENCFG_CPUSELFRESET; - - /* reboot via jumping to 0xbfc00000 */ - ((void (*)(void))ioremap_nocache(LOONGSON_BOOT_BASE, 4)) (); -} - -static void loongson_halt(void) -{ - while (1) - ; } -void loongson_reboot_setup(void) +void mach_prepare_shutdown(void) { - _machine_restart = loongson_restart; - _machine_halt = loongson_halt; - pm_power_off = loongson_halt; } diff --git a/arch/mips/loongson/fuloong-2e/rtc.c b/arch/mips/loongson/fuloong-2e/rtc.c deleted file mode 100644 index 469ada8..0000000 --- a/arch/mips/loongson/fuloong-2e/rtc.c +++ /dev/null @@ -1,55 +0,0 @@ -/* - * Registration of Cobalt RTC platform device. - * - * Copyright (C) 2007 Yoichi Yuasa - * Copyright (C) 2009 Wu Zhangjin - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, - * MA 02110-1301 USA - */ - -#include -#include -#include -#include - -static struct resource rtc_cmos_resource[] = { - { - .start = RTC_PORT(0), - .end = RTC_PORT(1), - .flags = IORESOURCE_IO, - }, - { - .start = RTC_IRQ, - .end = RTC_IRQ, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device rtc_cmos_device = { - .name = "rtc_cmos", - .id = -1, - .num_resources = ARRAY_SIZE(rtc_cmos_resource), - .resource = rtc_cmos_resource -}; - -static __init int rtc_cmos_init(void) -{ - platform_device_register(&rtc_cmos_device); - - return 0; -} - -device_initcall(rtc_cmos_init); diff --git a/arch/mips/loongson/fuloong-2e/setup.c b/arch/mips/loongson/fuloong-2e/setup.c deleted file mode 100644 index 4fcbe48..0000000 --- a/arch/mips/loongson/fuloong-2e/setup.c +++ /dev/null @@ -1,74 +0,0 @@ -/* - * board dependent setup routines - * - * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology - * Author: Fuxin Zhang, zhangfx@lemote.com - * - * Copyright (C) 2009 Lemote Inc. & Insititute of Computing Technology - * Author: Wu Zhangjin, wuzj@lemote.com - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#include - -#include - -#include - -void (*__wbflush) (void); -EXPORT_SYMBOL(__wbflush); - -static void loongson_wbflush(void) -{ - asm(".set\tpush\n\t" - ".set\tnoreorder\n\t" - ".set mips3\n\t" - "sync\n\t" - "nop\n\t" - ".set\tpop\n\t" - ".set mips0\n\t"); -} - -void __init loongson_wbflush_setup(void) -{ - __wbflush = loongson_wbflush; -} - -#if defined(CONFIG_VT) && defined(CONFIG_VGA_CONSOLE) -#include - -void __init loongson_screeninfo_setup(void) -{ - screen_info = (struct screen_info) { - 0, /* orig-x */ - 25, /* orig-y */ - 0, /* unused */ - 0, /* orig-video-page */ - 0, /* orig-video-mode */ - 80, /* orig-video-cols */ - 0, /* ega_ax */ - 0, /* ega_bx */ - 0, /* ega_cx */ - 25, /* orig-video-lines */ - VIDEO_TYPE_VGAC, /* orig-video-isVGA */ - 16 /* orig-video-points */ - }; -} -#else -void __init loongson_screeninfo_setup(void) -{ -} -#endif - -void __init plat_mem_setup(void) -{ - loongson_reboot_setup(); - - loongson_wbflush_setup(); - - loongson_screeninfo_setup(); -} diff --git a/arch/mips/loongson/fuloong-2e/time.c b/arch/mips/loongson/fuloong-2e/time.c deleted file mode 100644 index 231f0c2..0000000 --- a/arch/mips/loongson/fuloong-2e/time.c +++ /dev/null @@ -1,27 +0,0 @@ -/* - * board dependent boot routines - * - * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology - * Author: Fuxin Zhang, zhangfx@lemote.com - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - */ - -#include -#include - -#include - -unsigned long read_persistent_clock(void) -{ - return mc146818_get_cmos_time(); -} - -void __init plat_time_init(void) -{ - /* setup mips r4k timer */ - mips_hpt_frequency = cpu_clock_freq / 2; -} -- 1.6.0.4 From wuzhangjin@gmail.com Thu Jun 4 14:07:04 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 04 Jun 2009 14:07:12 +0100 (WEST) Received: from mail-pz0-f202.google.com ([209.85.222.202]:46485 "EHLO mail-pz0-f202.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20022605AbZFDNG1 (ORCPT ); Thu, 4 Jun 2009 14:06:27 +0100 Received: by pzk40 with SMTP id 40so738925pzk.22 for ; Thu, 04 Jun 2009 06:06:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer:in-reply-to:references; bh=kpSrz5Jx632rPehNciYORq8bDiK7qKAQvOSUaqzR7s0=; b=AZuP9wMYTNGhq29GjGpRKBu3ZrLKVY0g4xKhjUdqPYxl4UhxeDw6iqMkPmJiglPAjl Q6AvYP5Eg0uGK+GkhGfLVtwUK4gEYfHRknKeQjH8RT2Z7DpCWN6woKwqOJr5kIdPLf5V /ObjMcfpJeMfLhNy1zYKLpfbZt86npUZeTZPE= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; b=L49PkCNsJ2q9u1XtoIXgVPUxb67G03vzcNmSpej3MpKXbwSr96C9B/SLmwRI7GvJDB 3NFdg4bKNllPclm8ePD1r01kAgbXRHYGglRuqofeIZ8Zadn8HPZkvxARYXEHXyv8e2aD V63rSYtTbzfm16nn8D+XXu4n6XBJPkte1KozM= Received: by 10.115.74.1 with SMTP id b1mr2393014wal.168.1244120780727; Thu, 04 Jun 2009 06:06:20 -0700 (PDT) Received: from localhost.localdomain ([202.201.14.140]) by mx.google.com with ESMTPS id n33sm3228701wag.32.2009.06.04.06.06.15 (version=TLSv1/SSLv3 cipher=RC4-MD5); Thu, 04 Jun 2009 06:06:20 -0700 (PDT) From: wuzhangjin@gmail.com To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: Wu Zhangjin , Yan Hua , Philippe Vachon , Zhang Le , Zhang Fuxin , loongson-dev , Liu Junliang , Erwan Lerale , Arnaud Patard Subject: [loongson-PATCH-v3 11/25] split env out of cmdline.c Date: Thu, 4 Jun 2009 21:06:08 +0800 Message-Id: X-Mailer: git-send-email 1.6.3.1 In-Reply-To: References: Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23254 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips From: Wu Zhangjin add a new init function: prom_init_env() to split environment arguments initialization out of cmdline.c, the environment arguments are passed from bootloader, currently is PMON. Signed-off-by: Wu Zhangjin --- arch/mips/include/asm/mach-loongson/loongson.h | 5 +- arch/mips/loongson/common/Makefile | 2 +- arch/mips/loongson/common/cmdline.c | 36 ++------------ arch/mips/loongson/common/env.c | 59 ++++++++++++++++++++++++ arch/mips/loongson/common/init.c | 1 + 5 files changed, 69 insertions(+), 34 deletions(-) create mode 100644 arch/mips/loongson/common/env.c diff --git a/arch/mips/include/asm/mach-loongson/loongson.h b/arch/mips/include/asm/mach-loongson/loongson.h index 656511e..ca591ed 100644 --- a/arch/mips/include/asm/mach-loongson/loongson.h +++ b/arch/mips/include/asm/mach-loongson/loongson.h @@ -20,16 +20,17 @@ /* loongson internal northbridge initialization */ extern void bonito_irq_init(void); -/* command line arguments */ +/* environment arguments from bootloader */ extern unsigned long bus_clock, cpu_clock_freq; extern unsigned long memsize, highmemsize; /* loongson-based machines specific reboot setup */ extern void loongson_reboot_setup(void); -/* loongson-specific command line and memory initialization */ +/* loongson-specific command line, env and memory initialization */ extern void __init prom_init_memory(void); extern void __init prom_init_cmdline(void); +extern void __init prom_init_env(void); /* irq operation functions */ extern void bonito_irqdispatch(void); diff --git a/arch/mips/loongson/common/Makefile b/arch/mips/loongson/common/Makefile index 79b2736..030a0a0 100644 --- a/arch/mips/loongson/common/Makefile +++ b/arch/mips/loongson/common/Makefile @@ -2,7 +2,7 @@ # Makefile for loongson based machines. # -obj-y += setup.o init.o cmdline.o time.o reset.o irq.o \ +obj-y += setup.o init.o cmdline.o env.o time.o reset.o irq.o \ pci.o bonito-irq.o mem.o misc.o # diff --git a/arch/mips/loongson/common/cmdline.c b/arch/mips/loongson/common/cmdline.c index 6f603ac..12bb606 100644 --- a/arch/mips/loongson/common/cmdline.c +++ b/arch/mips/loongson/common/cmdline.c @@ -18,31 +18,23 @@ * option) any later version. */ -#include - #include -unsigned long bus_clock, cpu_clock_freq; -unsigned long memsize, highmemsize; +#include +#include int prom_argc; /* pmon passes arguments in 32bit pointers */ -int *_prom_argv, *_prom_envp; - -#define parse_even_earlier(res, option, p) \ -do { \ - if (strncmp(option, (char *)p, strlen(option)) == 0) \ - strict_strtol((char *)p + strlen(option"="), \ - 10, &res); \ -} while (0) +int *_prom_argv; void __init prom_init_cmdline(void) { int i; long l; + + /* firmware arguments are initialized in head.S */ prom_argc = fw_arg0; _prom_argv = (int *)fw_arg1; - _prom_envp = (int *)fw_arg2; /* arg[0] is "g", the rest is boot parameters */ arcs_cmdline[0] = '\0'; @@ -55,26 +47,8 @@ void __init prom_init_cmdline(void) strcat(arcs_cmdline, " "); } - /* handle console, root, busclock, cpuclock, memsize, highmemsize - arguments */ - if ((strstr(arcs_cmdline, "console=")) == NULL) strcat(arcs_cmdline, " console=ttyS0,115200"); if ((strstr(arcs_cmdline, "root=")) == NULL) strcat(arcs_cmdline, " root=/dev/hda1"); - - l = (long)*_prom_envp; - while (l != 0) { - parse_even_earlier(bus_clock, "busclock", l); - parse_even_earlier(cpu_clock_freq, "cpuclock", l); - parse_even_earlier(memsize, "memsize", l); - parse_even_earlier(highmemsize, "highmemsize", l); - _prom_envp++; - l = (long)*_prom_envp; - } - if (memsize == 0) - memsize = 256; - - pr_info("busclock=%ld, cpuclock=%ld, memsize=%ld, highmemsize=%ld\n", - bus_clock, cpu_clock_freq, memsize, highmemsize); } diff --git a/arch/mips/loongson/common/env.c b/arch/mips/loongson/common/env.c new file mode 100644 index 0000000..1a02428 --- /dev/null +++ b/arch/mips/loongson/common/env.c @@ -0,0 +1,59 @@ +/* + * Based on Ocelot Linux port, which is + * Copyright 2001 MontaVista Software Inc. + * Author: jsun@mvista.com or jsun@junsun.net + * + * Copyright 2003 ICT CAS + * Author: Michael Guo + * + * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology + * Author: Fuxin Zhang, zhangfx@lemote.com + * + * Copyright (C) 2009 Lemote Inc. & Insititute of Computing Technology + * Author: Wu Zhangjin, wuzj@lemote.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include + +#include + +unsigned long bus_clock, cpu_clock_freq; +unsigned long memsize, highmemsize; + +/* pmon passes arguments in 32bit pointers */ +int *_prom_envp; + +#define parse_even_earlier(res, option, p) \ +do { \ + if (strncmp(option, (char *)p, strlen(option)) == 0) \ + strict_strtol((char *)p + strlen(option"="), \ + 10, &res); \ +} while (0) + +void __init prom_init_env(void) +{ + long l; + + /* firmware arguments are initialized in head.S */ + _prom_envp = (int *)fw_arg2; + + l = (long)*_prom_envp; + while (l != 0) { + parse_even_earlier(bus_clock, "busclock", l); + parse_even_earlier(cpu_clock_freq, "cpuclock", l); + parse_even_earlier(memsize, "memsize", l); + parse_even_earlier(highmemsize, "highmemsize", l); + _prom_envp++; + l = (long)*_prom_envp; + } + if (memsize == 0) + memsize = 256; + + pr_info("busclock=%ld, cpuclock=%ld, memsize=%ld, highmemsize=%ld\n", + bus_clock, cpu_clock_freq, memsize, highmemsize); +} diff --git a/arch/mips/loongson/common/init.c b/arch/mips/loongson/common/init.c index 76e6fda..1c5a0e6 100644 --- a/arch/mips/loongson/common/init.c +++ b/arch/mips/loongson/common/init.c @@ -32,6 +32,7 @@ void __init prom_init(void) ioremap(LOONGSON_PCIIO_BASE, LOONGSON_PCIIO_SIZE)); prom_init_cmdline(); + prom_init_env(); prom_init_memory(); } -- 1.6.0.4 From wuzhangjin@gmail.com Thu Jun 4 14:07:29 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 04 Jun 2009 14:07:35 +0100 (WEST) Received: from wa-out-1112.google.com ([209.85.146.177]:45309 "EHLO wa-out-1112.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20022608AbZFDNGm (ORCPT ); Thu, 4 Jun 2009 14:06:42 +0100 Received: by wa-out-1112.google.com with SMTP id n4so139262wag.0 for ; Thu, 04 Jun 2009 06:06:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer:in-reply-to:references; bh=5DK0uPwmbQOtlyhJsQbK4TJs+HF7ziM4YaG4AeNAr1s=; b=JiosiWDxWM3A3CQLqMDK/SIbGLlOxbAzm23OEYVHlN/a7v258YEJAmyOZAB8JB9SZM 1krUoI6orA1DKd+k6+vlBlDxdlaU4MKu1SKIiPJkrBM7PAcmOppazrEC6X/tGcPC+8aB rKqX8QKWsfnt60PGqEt+mMQb8hA/8t0nwJ5lw= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; b=AwrjZ8zp0LEtUlKkEjsoMg1g7aw9mLANoFa5EK3mFO9DyuaLyv/+U5rKLSv5WHhoK7 /c+V3ioHKjCeaove0vvgCJjaaDb6TqJcr5I+MgGMoquAnAvzxbsytn15GQWoiFOkZgUY HPa8+GcTsy+fEKrK8EHL3iltkvh8wWovOf43Q= Received: by 10.114.201.2 with SMTP id y2mr2359284waf.184.1244120799667; Thu, 04 Jun 2009 06:06:39 -0700 (PDT) Received: from localhost.localdomain ([202.201.14.140]) by mx.google.com with ESMTPS id f20sm11038017waf.17.2009.06.04.06.06.32 (version=TLSv1/SSLv3 cipher=RC4-MD5); Thu, 04 Jun 2009 06:06:38 -0700 (PDT) From: wuzhangjin@gmail.com To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: Wu Zhangjin , Yan Hua , Philippe Vachon , Zhang Le , Zhang Fuxin , loongson-dev , Liu Junliang , Erwan Lerale , Arnaud Patard , Wu Zhangjin Subject: [loongson-PATCH-v3 12/25] add basic loongson-2f support Date: Thu, 4 Jun 2009 21:06:24 +0800 Message-Id: <86b9e1d6c2842104610df5fab45c733a0b917558.1244120575.git.wuzj@lemote.com> X-Mailer: git-send-email 1.6.3.1 In-Reply-To: References: Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23255 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips From: Wu Zhangjin Loongson2F has built-in DDR2 and PCIX controller. The PCIX controller have a similar programming interface with FPGA northbridge used in Loongson2E. so, the main difference between loongson-2e and loongson-2f is: loongson-2f has an extra address windows configuration module, which can be used to map CPU address space to DDR or PCI address space, or map the PCI-DMA address space to DDR or LIO address space. herein, the module and the operations are abstracted to loongson.h. NOTE: this module is only available in 64bit kernel. Signed-off-by: Wu Zhangjin --- arch/mips/Kconfig | 18 +++++ .../mips/include/asm/mach-loongson/dma-coherence.h | 4 + arch/mips/include/asm/mach-loongson/loongson.h | 79 +++++++++++++++++++- arch/mips/include/asm/mach-loongson/mem.h | 23 ++++++ arch/mips/include/asm/mach-loongson/pci.h | 30 +++++++- arch/mips/loongson/common/init.c | 17 ++++ arch/mips/loongson/common/mem.c | 21 ++++- arch/mips/loongson/common/pci.c | 14 +++- 8 files changed, 197 insertions(+), 9 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 33a3bc6..74efb43 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -998,6 +998,21 @@ config CPU_LOONGSON2E The Loongson 2E processor implements the MIPS III instruction set with many extensions. + It has an internal FPGA northbridge, which is compatiable to + bonito64. + +config CPU_LOONGSON2F + bool "Loongson 2F" + depends on SYS_HAS_CPU_LOONGSON2F + select CPU_LOONGSON2 + help + The Loongson 2F processor implements the MIPS III instruction set + with many extensions. + + Loongson2F have built-in DDR2 and PCIX controller. The PCIX controller + have a similar programming interface with FPGA northbridge used in + Loongson2E. + config CPU_MIPS32_R1 bool "MIPS32 Release 1" depends on SYS_HAS_CPU_MIPS32_R1 @@ -1245,6 +1260,9 @@ config CPU_LOONGSON2 config SYS_HAS_CPU_LOONGSON2E bool +config SYS_HAS_CPU_LOONGSON2F + bool + config SYS_HAS_CPU_MIPS32_R1 bool diff --git a/arch/mips/include/asm/mach-loongson/dma-coherence.h b/arch/mips/include/asm/mach-loongson/dma-coherence.h index f27d0f8..6ba8279 100644 --- a/arch/mips/include/asm/mach-loongson/dma-coherence.h +++ b/arch/mips/include/asm/mach-loongson/dma-coherence.h @@ -27,7 +27,11 @@ static inline dma_addr_t plat_map_dma_mem_page(struct device *dev, static inline unsigned long plat_dma_addr_to_phys(dma_addr_t dma_addr) { +#if defined(CONFIG_CPU_LOONGSON2F) & defined(CONFIG_64BIT) + return (dma_addr > 0x8fffffff) ? dma_addr : (dma_addr & 0x0fffffff); +#else return dma_addr & 0x7fffffff; +#endif } static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr) diff --git a/arch/mips/include/asm/mach-loongson/loongson.h b/arch/mips/include/asm/mach-loongson/loongson.h index ca591ed..b5e3d95 100644 --- a/arch/mips/include/asm/mach-loongson/loongson.h +++ b/arch/mips/include/asm/mach-loongson/loongson.h @@ -222,5 +222,82 @@ extern void mach_prepare_shutdown(void); #define LOONGSON_PCIMAP_WIN(WIN, ADDR) \ ((((ADDR)>>26) & LOONGSON_PCIMAP_PCIMAP_LO0) << ((WIN)*6)) -#endif /* __LOONGSON_H */ +/* + * address windows configuration module + * + * loongson2e do not have this module + */ +#if defined(CONFIG_CPU_LOONGSON2F) && defined(CONFIG_64BIT) + +/* address window config module base address */ +#define LOONGSON_ADDRWINCFG_BASE 0x3ff00000ul +#define LOONGSON_ADDRWINCFG_SIZE 0x180 + +extern unsigned long _loongson_addrwincfg_base; +#define LOONGSON_ADDRWINCFG(offset) \ + (*(u64 *)(_loongson_addrwincfg_base + (offset))) + +#define CPU_WIN0_BASE LOONGSON_ADDRWINCFG(0x00) +#define CPU_WIN1_BASE LOONGSON_ADDRWINCFG(0x08) +#define CPU_WIN2_BASE LOONGSON_ADDRWINCFG(0x10) +#define CPU_WIN3_BASE LOONGSON_ADDRWINCFG(0x18) + +#define CPU_WIN0_MASK LOONGSON_ADDRWINCFG(0x20) +#define CPU_WIN1_MASK LOONGSON_ADDRWINCFG(0x28) +#define CPU_WIN2_MASK LOONGSON_ADDRWINCFG(0x30) +#define CPU_WIN3_MASK LOONGSON_ADDRWINCFG(0x38) + +#define CPU_WIN0_MMAP LOONGSON_ADDRWINCFG(0x40) +#define CPU_WIN1_MMAP LOONGSON_ADDRWINCFG(0x48) +#define CPU_WIN2_MMAP LOONGSON_ADDRWINCFG(0x50) +#define CPU_WIN3_MMAP LOONGSON_ADDRWINCFG(0x58) + +#define PCIDMA_WIN0_BASE LOONGSON_ADDRWINCFG(0x60) +#define PCIDMA_WIN1_BASE LOONGSON_ADDRWINCFG(0x68) +#define PCIDMA_WIN2_BASE LOONGSON_ADDRWINCFG(0x70) +#define PCIDMA_WIN3_BASE LOONGSON_ADDRWINCFG(0x78) + +#define PCIDMA_WIN0_MASK LOONGSON_ADDRWINCFG(0x80) +#define PCIDMA_WIN1_MASK LOONGSON_ADDRWINCFG(0x88) +#define PCIDMA_WIN2_MASK LOONGSON_ADDRWINCFG(0x90) +#define PCIDMA_WIN3_MASK LOONGSON_ADDRWINCFG(0x98) + +#define PCIDMA_WIN0_MMAP LOONGSON_ADDRWINCFG(0xa0) +#define PCIDMA_WIN1_MMAP LOONGSON_ADDRWINCFG(0xa8) +#define PCIDMA_WIN2_MMAP LOONGSON_ADDRWINCFG(0xb0) +#define PCIDMA_WIN3_MMAP LOONGSON_ADDRWINCFG(0xb8) + +#define ADDRWIN_WIN0 0 +#define ADDRWIN_WIN1 1 +#define ADDRWIN_WIN2 2 +#define ADDRWIN_WIN3 3 + +#define ADDRWIN_MAP_DST_DDR 0 +#define ADDRWIN_MAP_DST_PCI 1 +#define ADDRWIN_MAP_DST_LIO 1 + +/* + * s: CPU, PCIDMA + * d: DDR, PCI, LIO + * win: 0, 1, 2, 3 + * src: map source + * dst: map destination + * size: ~mask + 1 + */ +#define LOONGSON_ADDRWIN_CFG(s, d, w, src, dst, size) do {\ + s##_WIN##w##_BASE = (src); \ + s##_WIN##w##_MMAP = (src) | ADDRWIN_MAP_DST_##d; \ + s##_WIN##w##_MASK = ~(size-1); \ +} while (0); + +#define LOONGSON_ADDRWIN_CPUTOPCI(win, src, dst, size) \ + LOONGSON_ADDRWIN_CFG(CPU, PCI, win, src, dst, size) +#define LOONGSON_ADDRWIN_CPUTODDR(win, src, dst, size) \ + LOONGSON_ADDRWIN_CFG(CPU, DDR, win, src, dst, size) +#define LOONGSON_ADDRWIN_PCITODDR(win, src, dst, size) \ + LOONGSON_ADDRWIN_CFG(PCIDMA, DDR, win, src, dst, size) + +#endif /* ! CONFIG_CPU_LOONGSON2F && CONFIG_64BIT */ + +#endif /* __LOONGSON_H */ diff --git a/arch/mips/include/asm/mach-loongson/mem.h b/arch/mips/include/asm/mach-loongson/mem.h index ad01dc2..fb53be0 100644 --- a/arch/mips/include/asm/mach-loongson/mem.h +++ b/arch/mips/include/asm/mach-loongson/mem.h @@ -1,8 +1,31 @@ #ifndef __MEM_H #define __MEM_H +/* + * high memory space + * + * in loongson2e, starts from 512M + * in loongson2f, starts from 2G + 256M + */ +#ifdef CONFIG_CPU_LOONGSON2E #define LOONGSON_HIGHMEM_START 0x20000000 +#else +#define LOONGSON_HIGHMEM_START 0x90000000 +#endif + +/* + * the peripheral registers(MMIO): + * + * On the Lemote Loongson 2e system, reside between 0x1000:0000 and 0x2000:0000. + * On the Lemote Loongson 2f system, reside between 0x1000:0000 and 0x8000:0000. + */ + #define LOONGSON_MMIO_MEM_START 0x10000000 + +#ifdef CONFIG_CPU_LOONGSON2E #define LOONGSON_MMIO_MEM_END 0x20000000 +#else +#define LOONGSON_MMIO_MEM_END 0x80000000 +#endif #endif /* !__MEM_H */ diff --git a/arch/mips/include/asm/mach-loongson/pci.h b/arch/mips/include/asm/mach-loongson/pci.h index 8f02486..cdec41c 100644 --- a/arch/mips/include/asm/mach-loongson/pci.h +++ b/arch/mips/include/asm/mach-loongson/pci.h @@ -1,5 +1,6 @@ /* * Copyright (c) 2008 Zhang Le + * Copyright (c) 2009 Wu Zhangjin * * This program is free software; you can redistribute it * and/or modify it under the terms of the GNU General @@ -24,8 +25,35 @@ extern struct pci_ops loongson_pci_ops; +/* this is an offset from mips_io_port_base */ +#define LOONGSON_PCI_IO_START 0x00004000UL + +#if defined(CONFIG_CPU_LOONGSON2F) && defined(CONFIG_64BIT) + +/* + * we use address window2 to map cpu address space to pci space + * window2: cpu [1G, 2G] -> pci [1G, 2G] + * why not use window 0 & 1? because they are used by cpu when booting. + * window0: cpu [0, 256M] -> ddr [0, 256M] + * window1: cpu [256M, 512M] -> pci [256M, 512M] + */ + +/* the smallest LOONGSON_CPU_MEM_SRC can be 512M */ +#define LOONGSON_CPU_MEM_SRC 0x40000000ul /* 1G */ +#define LOONGSON_PCI_MEM_DST LOONGSON_CPU_MEM_SRC + +#define LOONGSON_PCI_MEM_START LOONGSON_PCI_MEM_DST +#define LOONGSON_PCI_MEM_END (0x80000000ul-1) /* 2G */ + +#define MMAP_CPUTOPCI_SIZE (LOONGSON_PCI_MEM_END - \ + LOONGSON_PCI_MEM_START + 1) + +#else /* loongson2f/32bit & loongson2e */ + #define LOONGSON_PCI_MEM_START 0x14000000UL #define LOONGSON_PCI_MEM_END 0x1fffffffUL -#define LOONGSON_PCI_IO_START 0x00004000UL + +#endif /* !(defined(CONFIG_CPU_LOONGSON2F) && defined(CONFIG_64BIT))*/ + #endif /* !_LOONGSON_PCI_H_ */ diff --git a/arch/mips/loongson/common/init.c b/arch/mips/loongson/common/init.c index 1c5a0e6..cbb33de 100644 --- a/arch/mips/loongson/common/init.c +++ b/arch/mips/loongson/common/init.c @@ -22,6 +22,17 @@ #include +#if defined(CONFIG_CPU_LOONGSON2F) && defined(CONFIG_64BIT) +unsigned long _loongson_addrwincfg_base; + +/* Loongson CPU address windows config space base address */ +static inline void set_loongson_addrwincfg_base(unsigned long base) +{ + *(unsigned long *)&_loongson_addrwincfg_base = base; + barrier(); +} +#endif + void __init prom_init(void) { /* init mach type, does we need to init it?? */ @@ -31,6 +42,12 @@ void __init prom_init(void) set_io_port_base((unsigned long) ioremap(LOONGSON_PCIIO_BASE, LOONGSON_PCIIO_SIZE)); +#if defined(CONFIG_CPU_LOONGSON2F) && defined(CONFIG_64BIT) + set_loongson_addrwincfg_base((unsigned long) + ioremap(LOONGSON_ADDRWINCFG_BASE, + LOONGSON_ADDRWINCFG_SIZE)); +#endif + prom_init_cmdline(); prom_init_env(); prom_init_memory(); diff --git a/arch/mips/loongson/common/mem.c b/arch/mips/loongson/common/mem.c index 17a7278..9e0b6e0 100644 --- a/arch/mips/loongson/common/mem.c +++ b/arch/mips/loongson/common/mem.c @@ -17,6 +17,23 @@ void __init prom_init_memory(void) { add_memory_region(0x0, (memsize << 20), BOOT_MEM_RAM); #ifdef CONFIG_64BIT +#ifdef CONFIG_CPU_LOONGSON2F + { + int bit; + + bit = fls(memsize + highmemsize); + if (bit != ffs(memsize + highmemsize)) + bit += 20; + else + bit = bit + 20 - 1; + + /* set cpu window3 to map CPU to DDR: 2G -> 2G */ + LOONGSON_ADDRWIN_CPUTODDR(ADDRWIN_WIN3, 0x80000000ul, + 0x80000000ul, (1 << bit)); + mmiowb(); + } +#endif /* CONFIG_CPU_LOONGSON2F */ + if (highmemsize > 0) { add_memory_region(LOONGSON_HIGHMEM_START, highmemsize << 20, BOOT_MEM_RAM); @@ -30,10 +47,6 @@ int __uncached_access(struct file *file, unsigned long addr) if (file->f_flags & O_SYNC) return 1; - /* - * On the Lemote Loongson 2e system, the peripheral registers - * reside between 0x1000:0000 and 0x2000:0000. - */ return addr >= __pa(high_memory) || ((addr >= LOONGSON_MMIO_MEM_START) && \ (addr < LOONGSON_MMIO_MEM_END)); diff --git a/arch/mips/loongson/common/pci.c b/arch/mips/loongson/common/pci.c index e97c845..e8291c3 100644 --- a/arch/mips/loongson/common/pci.c +++ b/arch/mips/loongson/common/pci.c @@ -30,15 +30,15 @@ #include static struct resource loongson_pci_mem_resource = { - .name = "LOONGSON PCI MEM", + .name = "pci memory space", .start = LOONGSON_PCI_MEM_START, .end = LOONGSON_PCI_MEM_END, .flags = IORESOURCE_MEM, }; static struct resource loongson_pci_io_resource = { - .name = "LOONGSON PCI IO MEM", - .start = LOONGSON_PCI_IO_START, + .name = "pci io space", + .start = LOONGSON_PCI_IO_START, /* reserve regacy I/O space */ .end = IO_SPACE_LIMIT, .flags = IORESOURCE_IO, }; @@ -85,6 +85,14 @@ static void __init ict_pcimap(void) /* can not change gnt to break pci transfer when device's gnt not deassert for some broken device */ LOONGSON_PXARB_CFG = 0x00fe0105ul; + +#if defined(CONFIG_CPU_LOONGSON2F) && defined(CONFIG_64BIT) + /* + * set cpu addr window2 to map CPU address space to PCI address space + */ + LOONGSON_ADDRWIN_CPUTOPCI(ADDRWIN_WIN2, LOONGSON_CPU_MEM_SRC, + LOONGSON_PCI_MEM_DST, MMAP_CPUTOPCI_SIZE); +#endif } static int __init pcibios_init(void) -- 1.6.0.4 From wuzhangjin@gmail.com Thu Jun 4 14:07:52 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 04 Jun 2009 14:08:01 +0100 (WEST) Received: from mail-px0-f186.google.com ([209.85.216.186]:34980 "EHLO mail-px0-f186.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20022601AbZFDNHJ (ORCPT ); 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Thu, 04 Jun 2009 06:06:57 -0700 (PDT) From: wuzhangjin@gmail.com To: linux-mips@linux-mips.org, ralf@linux-mips.org Cc: Wu Zhangjin , Yan Hua , Philippe Vachon , Zhang Le , Zhang Fuxin , loongson-dev , Liu Junliang , Erwan Lerale , Arnaud Patard , Wu Zhangjin Subject: [loongson-PATCH-v3 13/25] add basic fuloong(2f) support Date: Thu, 4 Jun 2009 21:06:44 +0800 Message-Id: X-Mailer: git-send-email 1.6.3.1 In-Reply-To: References: Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 23256 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wuzhangjin@gmail.com Precedence: bulk X-list: linux-mips From: Wu Zhangjin fuloong(2e) has an VIA686B south bridge, but fuloong(2f) has an AMD CS5536 south bridge. so, we need to add basic cs5536 south bridge support here. there are several modules provided by cs5536, currently, only these modules are used in fuloong(2f) mini PC: ide, acc(audio), ohci, isa, and ehci. and these modules are general modules, which means should be compiled in kernel by default, besides, there are several selective modules: flash(nor and nand), otg, udc. the otg and udc modules are used in the NAS machine made by Lemote(the source code support will be added later, only a few differ from fuloong2f mini PC). since the PCI operations are similiar between fuloong(2e) and fuloong(2f),yeeloong(2f) and even similiar to gdium, herein, I just rename ops-fuloong2e.c to ops-loongsgon2.c to share most of the source code. PS: the originl cs5536 support for fuloong2f is from the to-mips branch of git://dev.lemote.com/linux_loongson.git, tons of source code have been cleaned up. the most important change is using the linux-internal pci_regs.h(include/linux/pci_regs.h) instead of the original pcireg.h and dividing the huge cs5536_vsm.c to several small files, one file one cs5536 module. at the same time, tons of souce code are tuned to be understandable and some trashy souce code are removed away which will archieve a higher performance. and also, the header files, cs5536.h and cs5536_pci.h are cleaned up a lot. Signed-off-by: Wu Zhangjin Signed-off-by: Yan Hua --- arch/mips/Makefile | 1 + .../mips/include/asm/mach-loongson/cs5536/cs5536.h | 382 +++++++++++++++++ .../include/asm/mach-loongson/cs5536/cs5536_pci.h | 174 ++++++++ .../include/asm/mach-loongson/cs5536/cs5536_vsm.h | 59 +++ arch/mips/include/asm/mach-loongson/loongson.h | 2 +- arch/mips/include/asm/mach-loongson/machine.h | 30 ++ arch/mips/loongson/Kconfig | 44 ++ arch/mips/loongson/Makefile | 6 + arch/mips/loongson/common/Makefile | 6 + arch/mips/loongson/common/bonito-irq.c | 5 + arch/mips/loongson/common/cs5536/Makefile | 20 + arch/mips/loongson/common/cs5536/cs5536_acc.c | 156 +++++++ arch/mips/loongson/common/cs5536/cs5536_ehci.c | 166 +++++++ arch/mips/loongson/common/cs5536/cs5536_flash.c | 452 ++++++++++++++++++++ arch/mips/loongson/common/cs5536/cs5536_ide.c | 194 +++++++++ arch/mips/loongson/common/cs5536/cs5536_isa.c | 376 ++++++++++++++++ arch/mips/loongson/common/cs5536/cs5536_ohci.c | 168 ++++++++ arch/mips/loongson/common/cs5536/cs5536_otg.c | 138 ++++++ arch/mips/loongson/common/cs5536/cs5536_pci.c | 126 ++++++ arch/mips/loongson/common/cs5536/cs5536_udc.c | 143 ++++++ arch/mips/loongson/fuloong-2f/Makefile | 5 + arch/mips/loongson/fuloong-2f/irq.c | 53 +++ arch/mips/loongson/fuloong-2f/reset.c | 65 +++ arch/mips/pci/Makefile | 3 +- arch/mips/pci/fixup-fuloong2f.c | 171 ++++++++ arch/mips/pci/ops-fuloong2e.c | 160 ------- arch/mips/pci/ops-loongson2.c | 213 +++++++++ 27 files changed, 3156 insertions(+), 162 deletions(-) create mode 100644 arch/mips/include/asm/mach-loongson/cs5536/cs5536.h create mode 100644 arch/mips/include/asm/mach-loongson/cs5536/cs5536_pci.h create mode 100644 arch/mips/include/asm/mach-loongson/cs5536/cs5536_vsm.h create mode 100644 arch/mips/loongson/common/cs5536/Makefile create mode 100644 arch/mips/loongson/common/cs5536/cs5536_acc.c create mode 100644 arch/mips/loongson/common/cs5536/cs5536_ehci.c create mode 100644 arch/mips/loongson/common/cs5536/cs5536_flash.c create mode 100644 arch/mips/loongson/common/cs5536/cs5536_ide.c create mode 100644 arch/mips/loongson/common/cs5536/cs5536_isa.c create mode 100644 arch/mips/loongson/common/cs5536/cs5536_ohci.c create mode 100644 arch/mips/loongson/common/cs5536/cs5536_otg.c create mode 100644 arch/mips/loongson/common/cs5536/cs5536_pci.c create mode 100644 arch/mips/loongson/common/cs5536/cs5536_udc.c create mode 100644 arch/mips/loongson/fuloong-2f/Makefile create mode 100644 arch/mips/loongson/fuloong-2f/irq.c create mode 100644 arch/mips/loongson/fuloong-2f/reset.c create mode 100644 arch/mips/pci/fixup-fuloong2f.c delete mode 100644 arch/mips/pci/ops-fuloong2e.c create mode 100644 arch/mips/pci/ops-loongson2.c diff --git a/arch/mips/Makefile b/arch/mips/Makefile index 6801baa..74f23ad 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -311,6 +311,7 @@ core-$(CONFIG_LOONGSON_SYSTEMS) +=arch/mips/loongson/ cflags-$(CONFIG_LOONGSON_SYSTEMS) += -I$(srctree)/arch/mips/include/asm/mach-loongson \ -mno-branch-likely load-$(CONFIG_LEMOTE_FULOONG2E) +=0xffffffff80100000 +load-$(CONFIG_LEMOTE_FULOONG2F) +=0xffffffff80200000 # # MIPS Malta board diff --git a/arch/mips/include/asm/mach-loongson/cs5536/cs5536.h b/arch/mips/include/asm/mach-loongson/cs5536/cs5536.h new file mode 100644 index 0000000..a9bbe1d --- /dev/null +++ b/arch/mips/include/asm/mach-loongson/cs5536/cs5536.h @@ -0,0 +1,382 @@ +/* + * The header file of cs5536 sourth bridge. + * + * Copyright (C) 2007 Lemote, Inc. & Institute of Computing Technology + * Author : jlliu + */ + +#ifndef _CS5536_H +#define _CS5536_H + +#include + +extern void _rdmsr(u32 msr, u32 *hi, u32 *lo); +extern void _wrmsr(u32 msr, u32 hi, u32 lo); + +/* + * MSR module base + */ +#define CS5536_SB_MSR_BASE (0x00000000) +#define CS5536_GLIU_MSR_BASE (0x10000000) +#define CS5536_ILLEGAL_MSR_BASE (0x20000000) +#define CS5536_USB_MSR_BASE (0x40000000) +#define CS5536_IDE_MSR_BASE (0x60000000) +#define CS5536_DIVIL_MSR_BASE (0x80000000) +#define CS5536_ACC_MSR_BASE (0xa0000000) +#define CS5536_UNUSED_MSR_BASE (0xc0000000) +#define CS5536_GLCP_MSR_BASE (0xe0000000) + +#define SB_MSR_REG(offset) (CS5536_SB_MSR_BASE | (offset)) +#define GLIU_MSR_REG(offset) (CS5536_GLIU_MSR_BASE | (offset)) +#define ILLEGAL_MSR_REG(offset) (CS5536_ILLEGAL_MSR_BASE | (offset)) +#define USB_MSR_REG(offset) (CS5536_USB_MSR_BASE | (offset)) +#define IDE_MSR_REG(offset) (CS5536_IDE_MSR_BASE | (offset)) +#define DIVIL_MSR_REG(offset) (CS5536_DIVIL_MSR_BASE | (offset)) +#define ACC_MSR_REG(offset) (CS5536_ACC_MSR_BASE | (offset)) +#define UNUSED_MSR_REG(offset) (CS5536_UNUSED_MSR_BASE | (offset)) +#define GLCP_MSR_REG(offset) (CS5536_GLCP_MSR_BASE | (offset)) + +/* + * BAR SPACE OF VIRTUAL PCI : + * range for pci probe use, length is the actual size. + */ +/* IO space for all DIVIL modules */ +#define CS5536_IRQ_RANGE 0xffffffe0 /* USERD FOR PCI PROBE */ +#define CS5536_IRQ_LENGTH 0x20 /* THE REGS ACTUAL LENGTH */ +#define CS5536_SMB_RANGE 0xfffffff8 +#define CS5536_SMB_LENGTH 0x08 +#define CS5536_GPIO_RANGE 0xffffff00 +#define CS5536_GPIO_LENGTH 0x100 +#define CS5536_MFGPT_RANGE 0xffffffc0 +#define CS5536_MFGPT_LENGTH 0x40 +#define CS5536_ACPI_RANGE 0xffffffe0 +#define CS5536_ACPI_LENGTH 0x20 +#define CS5536_PMS_RANGE 0xffffff80 +#define CS5536_PMS_LENGTH 0x80 +/* MEM space for 4KB nand flash; IO space for 16B nor flash. */ +#ifdef CS5536_NOR_FLASH +#define CS5536_FLSH_LENGTH 0x10 +#define CS5536_FLSH_RANGE 0xfffffff0 +#else +#define CS5536_FLSH_RANGE 0xfffff000 +#define CS5536_FLSH_LENGTH 0x1000 +#endif +/* IO space for IDE */ +#define CS5536_IDE_RANGE 0xfffffff0 +#define CS5536_IDE_LENGTH 0x10 +/* IO space for ACC */ +#define CS5536_ACC_RANGE 0xffffff80 +#define CS5536_ACC_LENGTH 0x80 +/* MEM space for ALL USB modules */ +#define CS5536_OHCI_RANGE 0xfffff000 +#define CS5536_OHCI_LENGTH 0x1000 +#define CS5536_EHCI_RANGE 0xfffff000 +#define CS5536_EHCI_LENGTH 0x1000 +#define CS5536_UDC_RANGE 0xffffe000 +#define CS5536_UDC_LENGTH 0x2000 +#define CS5536_OTG_RANGE 0xfffff000 +#define CS5536_OTG_LENGTH 0x1000 + +/* + * PCI MSR ACCESS + */ +#define PCI_MSR_CTRL 0xF0 +#define PCI_MSR_ADDR 0xF4 +#define PCI_MSR_DATA_LO 0xF8 +#define PCI_MSR_DATA_HI 0xFC + +/**************** MSR *****************************/ + +/* + * GLIU STANDARD MSR + */ +#define GLIU_CAP 0x00 +#define GLIU_CONFIG 0x01 +#define GLIU_SMI 0x02 +#define GLIU_ERROR 0x03 +#define GLIU_PM 0x04 +#define GLIU_DIAG 0x05 + +/* + * GLIU SPEC. MSR + */ +#define GLIU_P2D_BM0 0x20 +#define GLIU_P2D_BM1 0x21 +#define GLIU_P2D_BM2 0x22 +#define GLIU_P2D_BMK0 0x23 +#define GLIU_P2D_BMK1 0x24 +#define GLIU_P2D_BM3 0x25 +#define GLIU_P2D_BM4 0x26 +#define GLIU_COH 0x80 +#define GLIU_PAE 0x81 +#define GLIU_ARB 0x82 +#define GLIU_ASMI 0x83 +#define GLIU_AERR 0x84 +#define GLIU_DEBUG 0x85 +#define GLIU_PHY_CAP 0x86 +#define GLIU_NOUT_RESP 0x87 +#define GLIU_NOUT_WDATA 0x88 +#define GLIU_WHOAMI 0x8B +#define GLIU_SLV_DIS 0x8C +#define GLIU_IOD_BM0 0xE0 +#define GLIU_IOD_BM1 0xE1 +#define GLIU_IOD_BM2 0xE2 +#define GLIU_IOD_BM3 0xE3 +#define GLIU_IOD_BM4 0xE4 +#define GLIU_IOD_BM5 0xE5 +#define GLIU_IOD_BM6 0xE6 +#define GLIU_IOD_BM7 0xE7 +#define GLIU_IOD_BM8 0xE8 +#define GLIU_IOD_BM9 0xE9 +#define GLIU_IOD_SC0 0xEA +#define GLIU_IOD_SC1 0xEB +#define GLIU_IOD_SC2 0xEC +#define GLIU_IOD_SC3 0xED +#define GLIU_IOD_SC4 0xEE +#define GLIU_IOD_SC5 0xEF +#define GLIU_IOD_SC6 0xF0 +#define GLIU_IOD_SC7 0xF1 + +/* + * SB STANDARD + */ +#define SB_CAP 0x00 +#define SB_CONFIG 0x01 +#define SB_SMI 0x02 +#define SB_ERROR 0x03 +#define SB_MAR_ERR_EN 0x00000001 +#define SB_TAR_ERR_EN 0x00000002 +#define SB_RSVD_BIT1 0x00000004 +#define SB_EXCEP_ERR_EN 0x00000008 +#define SB_SYSE_ERR_EN 0x00000010 +#define SB_PARE_ERR_EN 0x00000020 +#define SB_TAS_ERR_EN 0x00000040 +#define SB_MAR_ERR_FLAG 0x00010000 +#define SB_TAR_ERR_FLAG 0x00020000 +#define SB_RSVD_BIT2 0x00040000 +#define SB_EXCEP_ERR_FLAG 0x00080000 +#define SB_SYSE_ERR_FLAG 0x00100000 +#define SB_PARE_ERR_FLAG 0x00200000 +#define SB_TAS_ERR_FLAG 0x00400000 +#define SB_PM 0x04 +#define SB_DIAG 0x05 + +/* + * SB SPEC. + */ +#define SB_CTRL 0x10 +#define SB_R0 0x20 +#define SB_R1 0x21 +#define SB_R2 0x22 +#define SB_R3 0x23 +#define SB_R4 0x24 +#define SB_R5 0x25 +#define SB_R6 0x26 +#define SB_R7 0x27 +#define SB_R8 0x28 +#define SB_R9 0x29 +#define SB_R10 0x2A +#define SB_R11 0x2B +#define SB_R12 0x2C +#define SB_R13 0x2D +#define SB_R14 0x2E +#define SB_R15 0x2F + +/* + * GLCP STANDARD + */ +#define GLCP_CAP 0x00 +#define GLCP_CONFIG 0x01 +#define GLCP_SMI 0x02 +#define GLCP_ERROR 0x03 +#define GLCP_PM 0x04 +#define GLCP_DIAG 0x05 + +/* + * GLCP SPEC. + */ +#define GLCP_CLK_DIS_DELAY 0x08 +#define GLCP_PM_CLK_DISABLE 0x09 +#define GLCP_GLB_PM 0x0B +#define GLCP_DBG_OUT 0x0C +#define GLCP_RSVD1 0x0D +#define GLCP_SOFT_COM 0x0E +#define SOFT_BAR_SMB_FLAG 0x00000001 +#define SOFT_BAR_GPIO_FLAG 0x00000002 +#define SOFT_BAR_MFGPT_FLAG 0x00000004 +#define SOFT_BAR_IRQ_FLAG 0x00000008 +#define SOFT_BAR_PMS_FLAG 0x00000010 +#define SOFT_BAR_ACPI_FLAG 0x00000020 +#define SOFT_BAR_FLSH0_FLAG 0x00000040 +#define SOFT_BAR_FLSH1_FLAG 0x00000080 +#define SOFT_BAR_FLSH2_FLAG 0x00000100 +#define SOFT_BAR_FLSH3_FLAG 0x00000200 +#define SOFT_BAR_IDE_FLAG 0x00000400 +#define SOFT_BAR_ACC_FLAG 0x00000800 +#define SOFT_BAR_OHCI_FLAG 0x00001000 +#define SOFT_BAR_EHCI_FLAG 0x00002000 +#define SOFT_BAR_UDC_FLAG 0x00004000 +#define SOFT_BAR_OTG_FLAG 0x00008000 +#define GLCP_RSVD2 0x0F +#define GLCP_CLK_OFF 0x10 +#define GLCP_CLK_ACTIVE 0x11 +#define GLCP_CLK_DISABLE 0x12 +#define GLCP_CLK4ACK 0x13 +#define GLCP_SYS_RST 0x14 +#define GLCP_RSVD3 0x15 +#define GLCP_DBG_CLK_CTRL 0x16 +#define GLCP_CHIP_REV_ID 0x17 + +/* + * DIVIL STANDARD + */ +#define DIVIL_CAP 0x00 +#define DIVIL_CONFIG 0x01 +#define DIVIL_SMI 0x02 +#define DIVIL_ERROR 0x03 +#define DIVIL_PM 0x04 +#define DIVIL_DIAG 0x05 + +/* + * DIVIL SPEC. + */ +#define DIVIL_LBAR_IRQ 0x08 +#define DIVIL_LBAR_KEL 0x09 +#define DIVIL_LBAR_SMB 0x0B +#define DIVIL_LBAR_GPIO 0x0C +#define DIVIL_LBAR_MFGPT 0x0D +#define DIVIL_LBAR_ACPI 0x0E +#define DIVIL_LBAR_PMS 0x0F +#define DIVIL_LBAR_FLSH0 0x10 +#define DIVIL_LBAR_FLSH1 0x11 +#define DIVIL_LBAR_FLSH2 0x12 +#define DIVIL_LBAR_FLSH3 0x13 +#define DIVIL_LEG_IO 0x14 +#define DIVIL_BALL_OPTS 0x15 +#define DIVIL_SOFT_IRQ 0x16 +#define DIVIL_SOFT_RESET 0x17 +/* NOR FLASH */ +#define NORF_CTRL 0x18 +#define NORF_T01 0x19 +#define NORF_T23 0x1A +/* NAND FLASH */ +#define NANDF_DATA 0x1B +#define NANDF_CTRL 0x1C +#define NANDF_RSVD 0x1D +/* KEL Keyboard Emulation Logic */ +#define KEL_CTRL 0x1F +/* PIC */ +#define PIC_YSEL_LOW 0x20 +#define PIC_YSEL_LOW_USB_SHIFT 8 +#define PIC_YSEL_LOW_ACC_SHIFT 16 +#define PIC_YSEL_LOW_FLASH_SHIFT 24 +#define PIC_YSEL_HIGH 0x21 +#define PIC_ZSEL_LOW 0x22 +#define PIC_ZSEL_HIGH 0x23 +#define PIC_IRQM_PRIM 0x24 +#define PIC_IRQM_LPC 0x25 +#define PIC_XIRR_STS_LOW 0x26 +#define PIC_XIRR_STS_HIGH 0x27 +#define PCI_SHDW 0x34 +/* MFGPT */ +#define MFGPT_IRQ 0x28 +#define MFGPT_NR 0x29 +#define MFGPT_RSVD 0x2A +#define MFGPT_SETUP 0x2B +/* FLOPPY */ +#define FLPY_3F2_SHDW 0x30 +#define FLPY_3F7_SHDW 0x31 +#define FLPY_372_SHDW 0x32 +#define FLPY_377_SHDW 0x33 +/* PIT */ +#define PIT_SHDW 0x36 +#define PIT_CNTRL 0x37 +/* UART */ +#define UART1_MOD 0x38 +#define UART1_DONG 0x39 +#define UART1_CONF 0x3A +#define UART1_RSVD 0x3B +#define UART2_MOD 0x3C +#define UART2_DONG 0x3D +#define UART2_CONF 0x3E +#define UART2_RSVD 0x3F +/* DMA */ +#define DIVIL_AC_DMA 0x1E +#define DMA_MAP 0x40 +#define DMA_SHDW_CH0 0x41 +#define DMA_SHDW_CH1 0x42 +#define DMA_SHDW_CH2 0x43 +#define DMA_SHDW_CH3 0x44 +#define DMA_SHDW_CH4 0x45 +#define DMA_SHDW_CH5 0x46 +#define DMA_SHDW_CH6 0x47 +#define DMA_SHDW_CH7 0x48 +#define DMA_MSK_SHDW 0x49 +/* LPC */ +#define LPC_EADDR 0x4C +#define LPC_ESTAT 0x4D +#define LPC_SIRQ 0x4E +#define LPC_RSVD 0x4F +/* PMC */ +#define PMC_LTMR 0x50 +#define PMC_RSVD 0x51 +/* RTC */ +#define RTC_RAM_LOCK 0x54 +#define RTC_DOMA_OFFSET 0x55 +#define RTC_MONA_OFFSET 0x56 +#define RTC_CEN_OFFSET 0x57 + +/* + * IDE STANDARD + */ +#define IDE_CAP 0x00 +#define IDE_CONFIG 0x01 +#define IDE_SMI 0x02 +#define IDE_ERROR 0x03 +#define IDE_PM 0x04 +#define IDE_DIAG 0x05 + +/* + * IDE SPEC. + */ +#define IDE_IO_BAR 0x08 +#define IDE_CFG 0x10 +#define IDE_DTC 0x12 +#define IDE_CAST 0x13 +#define IDE_ETC 0x14 +#define IDE_INTERNAL_PM 0x15 + +/* + * ACC STANDARD + */ +#define ACC_CAP 0x00 +#define ACC_CONFIG 0x01 +#define ACC_SMI 0x02 +#define ACC_ERROR 0x03 +#define ACC_PM 0x04 +#define ACC_DIAG 0x05 + +/* + * USB STANDARD + */ +#define USB_CAP 0x00 +#define USB_CONFIG 0x01 +#define USB_SMI 0x02 +#define USB_ERROR 0x03 +#define USB_PM 0x04 +#define USB_DIAG 0x05 + +/* + * USB SPEC. + */ +#define USB_OHCI 0x08 +#define USB_EHCI 0x09 +#define USB_UDC 0x0A +#define USB_OTG 0x0B + +/****************** NATIVE ***************************/ +/* GPIO : I/O SPACE; REG : 32BITS */ +#define GPIOL_OUT_VAL 0x00 +#define GPIOL_OUT_EN 0x04 + +#endif /* _CS5536_H */ diff --git a/arch/mips/include/asm/mach-loongson/cs5536/cs5536_pci.h b/arch/mips/include/asm/mach-loongson/cs5536/cs5536_pci.h new file mode 100644 index 0000000..34d37ed --- /dev/null +++ b/arch/mips/include/asm/mach-loongson/cs5536/cs5536_pci.h @@ -0,0 +1,174 @@ +/* + * the definition file of cs5536 Virtual Support Module(VSM). + * pci configuration space can be accessed through the VSM, so + * there is no need of the MSR read/write now, except the spec. + * MSR registers which are not implemented yet. + * + * Copyright (C) 2007 Lemote Inc. & Insititute of Computing Technology + * Author : jlliu, liujl@lemote.com + */ + +#ifndef _CS5536_PCI_H +#define _CS5536_PCI_H + +#include +#include + +extern void cs5536_pci_conf_write4(int function, int reg, u32 value); +extern u32 cs5536_pci_conf_read4(int function, int reg); + +#define CS5536_FLASH_INTR 6 +#define CS5536_ACC_INTR 9 +#define CS5536_IDE_INTR 14 +#define CS5536_USB_INTR 11 +#define CS5536_UART1_INTR 4 +#define CS5536_UART2_INTR 3 + +/************** PCI BUS DEVICE FUNCTION ***************/ + +/* + * PCI bus device function + */ +#define PCI_BUS_CS5536 0 +#define PCI_IDSEL_CS5536 14 + +/********** STANDARD PCI-2.2 EXPANSION ****************/ + +/* + * PCI configuration space + * we have to virtualize the PCI configure space head, so we should + * define the necessary IDs and some others. + */ + +/* CONFIG of PCI VENDOR ID*/ +#define CFG_PCI_VENDOR_ID(mod_dev_id, sys_vendor_id) \ + (((mod_dev_id) << 16) | (sys_vendor_id)) + +/* VENDOR ID */ +#define CS5536_VENDOR_ID 0x1022 + +/* DEVICE ID */ +#define CS5536_ISA_DEVICE_ID 0x2090 +#define CS5536_FLASH_DEVICE_ID 0x2091 +#define CS5536_IDE_DEVICE_ID 0x209a +#define CS5536_ACC_DEVICE_ID 0x2093 +#define CS5536_OHCI_DEVICE_ID 0x2094 +#define CS5536_EHCI_DEVICE_ID 0x2095 +#define CS5536_UDC_DEVICE_ID 0x2096 +#define CS5536_OTG_DEVICE_ID 0x2097 + +/* CLASS CODE : CLASS SUB-CLASS INTERFACE */ +#define CS5536_ISA_CLASS_CODE 0x060100 +#define CS5536_FLASH_CLASS_CODE 0x050100 +#define CS5536_IDE_CLASS_CODE 0x010180 +#define CS5536_ACC_CLASS_CODE 0x040100 +#define CS5536_OHCI_CLASS_CODE 0x0C0310 +#define CS5536_EHCI_CLASS_CODE 0x0C0320 +#define CS5536_UDC_CLASS_CODE 0x0C03FE +#define CS5536_OTG_CLASS_CODE 0x0C0380 + +/* BHLC : BIST HEADER-TYPE LATENCY-TIMER CACHE-LINE-SIZE */ + +#define CFG_PCI_CACHE_LINE_SIZE(header_type, latency_timer) \ + ((PCI_NONE_BIST << 24) | ((header_type) << 16) \ + | ((latency_timer) << 8) | PCI_NORMAL_CACHE_LINE_SIZE); + +#define PCI_NONE_BIST 0x00 /* RO not implemented yet. */ +#define PCI_BRIDGE_HEADER_TYPE 0x80 /* RO */ +#define PCI_NORMAL_HEADER_TYPE 0x00 +#define PCI_NORMAL_LATENCY_TIMER 0x00 +#define PCI_NORMAL_CACHE_LINE_SIZE 0x08 /* RW */ + +/* BAR */ +#define PCI_BAR0_REG 0x10 +#define PCI_BAR1_REG 0x14 +#define PCI_BAR2_REG 0x18 +#define PCI_BAR3_REG 0x1c +#define PCI_BAR4_REG 0x20 +#define PCI_BAR5_REG 0x24 +#define PCI_BAR_COUNT 6 +#define PCI_BAR_RANGE_MASK 0xFFFFFFFF + +/* CARDBUS CIS POINTER */ +#define PCI_CARDBUS_CIS_POINTER 0x00000000 + +/* SUBSYSTEM VENDOR ID */ +#define CS5536_SUB_VENDOR_ID CS5536_VENDOR_ID + +/* SUBSYSTEM ID */ +#define CS5536_ISA_SUB_ID CS5536_ISA_DEVICE_ID +#define CS5536_FLASH_SUB_ID CS5536_FLASH_DEVICE_ID +#define CS5536_IDE_SUB_ID CS5536_IDE_DEVICE_ID +#define CS5536_ACC_SUB_ID CS5536_ACC_DEVICE_ID +#define CS5536_OHCI_SUB_ID CS5536_OHCI_DEVICE_ID +#define CS5536_EHCI_SUB_ID CS5536_EHCI_DEVICE_ID +#define CS5536_UDC_SUB_ID CS5536_UDC_DEVICE_ID +#define CS5536_OTG_SUB_ID CS5536_OTG_DEVICE_ID + +/* EXPANSION ROM BAR */ +#define PCI_EXPANSION_ROM_BAR 0x00000000 + +/* CAPABILITIES POINTER */ +#define PCI_CAPLIST_POINTER 0x00000000 +#define PCI_CAPLIST_USB_POINTER 0x40 +/* INTERRUPT */ + +#define CFG_PCI_INTERRUPT_LINE(pin, mod_intr) \ + ((PCI_MAX_LATENCY << 24) | (PCI_MIN_GRANT << 16) | \ + ((pin) << 8) | (mod_intr)) + +#define PCI_MAX_LATENCY 0x40 +#define PCI_MIN_GRANT 0x00 +#define PCI_DEFAULT_PIN 0x01 + +/*********** EXPANSION PCI REG ************************/ + +/* + * ISA EXPANSION + */ +#define PCI_UART1_INT_REG 0x50 +#define PCI_UART2_INT_REG 0x54 +#define PCI_ISA_FIXUP_REG 0x58 + +/* + * FLASH EXPANSION + */ +#define PCI_FLASH_INT_REG 0x50 +#define PCI_NOR_FLASH_CTRL_REG 0x40 +#define PCI_NOR_FLASH_T01_REG 0x44 +#define PCI_NOR_FLASH_T23_REG 0x48 +#define PCI_NAND_FLASH_TDATA_REG 0x60 +#define PCI_NAND_FLASH_TCTRL_REG 0x64 +#define PCI_NAND_FLASH_RSVD_REG 0x68 +#define PCI_FLASH_SELECT_REG 0x70 + +/* + * IDE EXPANSION + */ +#define PCI_IDE_CFG_REG 0x40 +#define CS5536_IDE_FLASH_SIGNATURE 0xDEADBEEF +#define PCI_IDE_DTC_REG 0x48 +#define PCI_IDE_CAST_REG 0x4C +#define PCI_IDE_ETC_REG 0x50 +#define PCI_IDE_PM_REG 0x54 +#define PCI_IDE_INT_REG 0x60 + +/* + * ACC EXPANSION + */ +#define PCI_ACC_INT_REG 0x50 + +/* + * OHCI EXPANSION : INTTERUPT IS IMPLEMENTED BY THE OHCI + */ +#define PCI_OHCI_PM_REG 0x40 +#define PCI_OHCI_INT_REG 0x50 + +/* + * EHCI EXPANSION + */ +#define PCI_EHCI_LEGSMIEN_REG 0x50 +#define PCI_EHCI_LEGSMISTS_REG 0x54 +#define PCI_EHCI_FLADJ_REG 0x60 + +#endif /* _CS5536_PCI_H_ */ diff --git a/arch/mips/include/asm/mach-loongson/cs5536/cs5536_vsm.h b/arch/mips/include/asm/mach-loongson/cs5536/cs5536_vsm.h new file mode 100644 index 0000000..41e7136 --- /dev/null +++ b/arch/mips/include/asm/mach-loongson/cs5536/cs5536_vsm.h @@ -0,0 +1,59 @@ +/* + * the Virtual Support Module(VSM) read/write interfaces + * + * Copyright (C) 2009 Lemote, Inc. & Institute of Computing Technology + * Author: Wu Zhangjin + */ + +#ifndef _CS5536_VSM_H +#define _CS5536_VSM_H + +#include + +#define DECLARE_CS5536_MODULE(name) \ +extern void pci_##name##_write_reg(int reg, u32 value); \ +extern u32 pci_##name##_read_reg(int reg); + +#define DEFINE_CS5536_MODULE(name) \ +void pci_##name##_write_reg(int reg, u32 value)\ +{ \ + return; \ +} \ +u32 pci_##name##_read_reg(int reg) \ +{ \ + return 0xffffffff; \ +} \ + +/* core modules of cs5536 */ + +/* ide module */ +DECLARE_CS5536_MODULE(ide) +/* acc module */ +DECLARE_CS5536_MODULE(acc) +/* ohci module */ +DECLARE_CS5536_MODULE(ohci) +/* isa module */ +DECLARE_CS5536_MODULE(isa) +/* ehci module */ +DECLARE_CS5536_MODULE(ehci) + +/* selective modules of cs5536 */ +/* flash(nor or nand flash) module */ +#ifdef CONFIG_CS5536_FLASH + DECLARE_CS5536_MODULE(flash) +#else + DEFINE_CS5536_MODULE(flash) +#endif +/* otg module */ +#ifdef CONFIG_CS5536_OTG + DECLARE_CS5536_MODULE(otg) +#else + DEFINE_CS5536_MODULE(otg) +#endif +/* udc module */ +#ifdef CONFIG_CS5536_UDC + DECLARE_CS5536_MODULE(udc) +#else + DEFINE_CS5536_MODULE(udc) +#endif +#endif /* _CS5536_VSM_H */ diff --git a/arch/mips/include/asm/mach-loongson/loongson.h b/arch/mips/include/asm/mach-loongson/loongson.h index b5e3d95..cd6668b 100644 --- a/arch/mips/include/asm/mach-loongson/loongson.h +++ b/arch/mips/include/asm/mach-loongson/loongson.h @@ -288,7 +288,7 @@ extern unsigned long _loongson_addrwincfg_base; s##_WIN##w##_BASE = (src); \ s##_WIN##w##_MMAP = (src) | ADDRWIN_MAP_DST_##d; \ s##_WIN##w##_MASK = ~(size-1); \ -} while (0); +} while (0) #define LOONGSON_ADDRWIN_CPUTOPCI(win, src, dst, size) \ LOONGSON_ADDRWIN_CFG(CPU, PCI, win, src, dst, size) diff --git a/arch/mips/include/asm/mach-loongson/machine.h b/arch/mips/include/asm/mach-loongson/machine.h index 651a35d..da6b6d6 100644 --- a/arch/mips/include/asm/mach-loongson/machine.h +++ b/arch/mips/include/asm/mach-loongson/machine.h @@ -13,6 +13,8 @@ #ifndef __MACHINE_H #define __MACHINE_H +#ifdef CONFIG_LEMOTE_FULOONG2E + #define MACH_NAME "lemote-fuloong(2e)" #define LOONGSON_UART_BASE (LOONGSON_PCIIO_BASE + 0x3f8) @@ -23,5 +25,33 @@ #define LOONGSON_TIMER_IRQ (MIPS_CPU_IRQ_BASE + 7) #define LOONGSON_DMATIMEOUT_IRQ (LOONGSON_IRQ_BASE + 10) +#else /* CONFIG_LEMOTE_FULOONG2F */ + +#define MACH_NAME "lemote-fuloong(2f)" + +#define LOONGSON_UART_BASE (LOONGSON_PCIIO_BASE + 0x2f8) + +#define LOONGSON_TIMER_IRQ (MIPS_CPU_IRQ_BASE + 7) /* cpu timer */ +#define LOONGSON_PERFCNT_IRQ (MIPS_CPU_IRQ_BASE + 6) /* cpu perf counter */ +#define LOONGSON_NORTH_BRIDGE_IRQ (MIPS_CPU_IRQ_BASE + 6) /* bonito */ +#define LOONGSON_UART_IRQ (MIPS_CPU_IRQ_BASE + 3) /* cpu serial port */ +#define LOONGSON_SOUTH_BRIDGE_IRQ (MIPS_CPU_IRQ_BASE + 2) /* i8259 */ + +#define LOONGSON_INT_BIT_GPIO1 (1 << 1) +#define LOONGSON_INT_BIT_GPIO2 (1 << 2) +#define LOONGSON_INT_BIT_GPIO3 (1 << 3) +#define LOONGSON_INT_BIT_PCI_INTA (1 << 4) +#define LOONGSON_INT_BIT_PCI_INTB (1 << 5) +#define LOONGSON_INT_BIT_PCI_INTC (1 << 6) +#define LOONGSON_INT_BIT_PCI_INTD (1 << 7) +#define LOONGSON_INT_BIT_PCI_PERR (1 << 8) +#define LOONGSON_INT_BIT_PCI_SERR (1 << 9) +#define LOONGSON_INT_BIT_DDR (1 << 10) +#define LOONGSON_INT_BIT_INT0 (1 << 11) +#define LOONGSON_INT_BIT_INT1 (1 << 12) +#define LOONGSON_INT_BIT_INT2 (1 << 13) +#define LOONGSON_INT_BIT_INT3 (1 << 14) + +#endif #endif /* ! __MACHINE_H */ diff --git a/arch/mips/loongson/Kconfig b/arch/mips/loongson/Kconfig index 5874bf6..2bfda6e 100644 --- a/arch/mips/loongson/Kconfig +++ b/arch/mips/loongson/Kconfig @@ -28,4 +28,48 @@ config LEMOTE_FULOONG2E Lemote Fulong mini-PC board based on the Chinese Loongson-2E CPU and an FPGA northbridge +config LEMOTE_FULOONG2F + bool "Lemote Fuloong(2f) mini-PC" + select ARCH_SPARSEMEM_ENABLE + select CEVT_R4K + select CSRC_R4K + select SYS_HAS_CPU_LOONGSON2F + select DMA_NONCOHERENT + select BOOT_ELF32 + select BOARD_SCACHE + select HW_HAS_PCI + select I8259 + select ISA + select IRQ_CPU + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_64BIT_KERNEL + select SYS_SUPPORTS_LITTLE_ENDIAN + select SYS_SUPPORTS_HIGHMEM + select SYS_HAS_EARLY_PRINTK + select GENERIC_HARDIRQS_NO__DO_IRQ + select GENERIC_ISA_DMA_SUPPORT_BROKEN + select CPU_HAS_WB + select CS5536 + help + Lemote Fulong mini-PC board based on the Chinese Loongson-2F CPU + endchoice + +config CS5536 + bool + +config CS5536_FLASH + bool + depends on CS5536 + +config CS5536_NOR_FLASH + bool + depends on CS5536_FLASH + +config CS5536_OTG + bool + depends on CS5536 + +config CS5536_UDC + bool + depends on CS5536 diff --git a/arch/mips/loongson/Makefile b/arch/mips/loongson/Makefile index cc9f1c8..e9b8a81 100644 --- a/arch/mips/loongson/Makefile +++ b/arch/mips/loongson/Makefile @@ -9,3 +9,9 @@ obj-$(CONFIG_LOONGSON_SYSTEMS) += common/ # obj-$(CONFIG_LEMOTE_FULOONG2E) += fuloong-2e/ + +# +# Lemote Fuloong mini-PC (Loongson 2F-based) +# + +obj-$(CONFIG_LEMOTE_FULOONG2F) += fuloong-2f/ diff --git a/arch/mips/loongson/common/Makefile b/arch/mips/loongson/common/Makefile index 030a0a0..d55499e 100644 --- a/arch/mips/loongson/common/Makefile +++ b/arch/mips/loongson/common/Makefile @@ -17,4 +17,10 @@ obj-$(CONFIG_EARLY_PRINTK) += early_printk.o # obj-$(CONFIG_RTC_DRV_CMOS) += rtc.o +# +# Enable CS5536 Virtual Support Module(VSM) for virtulize the PCI configure +# space +# +obj-$(CONFIG_CS5536) += cs5536/ + EXTRA_CFLAGS += -Werror diff --git a/arch/mips/loongson/common/bonito-irq.c b/arch/mips/loongson/common/bonito-irq.c index 1f43447..940c1f0 100644 --- a/arch/mips/loongson/common/bonito-irq.c +++ b/arch/mips/loongson/common/bonito-irq.c @@ -53,10 +53,13 @@ static struct irq_chip bonito_irq_type = { .unmask = bonito_irq_enable, }; +/* there is no need to handle dma timeout in loongson-2f based machines */ +#ifdef CONFIG_CPU_LOONGSON2E static struct irqaction dma_timeout_irqaction = { .handler = no_action, .name = "dma_timeout", }; +#endif void bonito_irq_init(void) { @@ -65,5 +68,7 @@ void bonito_irq_init(void) for (i = LOONGSON_IRQ_BASE; i < LOONGSON_IRQ_BASE + 32; i++) set_irq_chip_and_handler(i, &bonito_irq_type, handle_level_irq); +#ifdef CONFIG_CPU_LOONGSON2E setup_irq(LOONGSON_DMATIMEOUT_IRQ, &dma_timeout_irqaction); +#endif } diff --git a/arch/mips/loongson/common/cs5536/Makefile b/arch/mips/loongson/common/cs5536/Makefile new file mode 100644 index 0000000..09bc177 --- /dev/null +++ b/arch/mips/loongson/common/cs5536/Makefile @@ -0,0 +1,20 @@ +# +# Makefile for CS5536 support. +# + +# +# core modules +# +obj-$(CONFIG_CS5536) += cs5536_pci.o cs5536_ide.o cs5536_acc.o cs5536_ohci.o \ + cs5536_isa.o cs5536_ehci.o +# +# selective modules +# +# add a CS5536_[MODULE] to your board in arch/mips/loongson/Kconfig +# +obj-$(CONFIG_CS5536_FLASH) += cs5536_flash.o +obj-$(CONFIG_CS5536_NOR_FLASH) += cs5536_flash.o +obj-$(CONFIG_CS5536_OTG) += cs5536_otg.o +obj-$(CONFIG_CS5536_UDC) += cs5536_udc.o + +EXTRA_CFLAGS += -Werror diff --git a/arch/mips/loongson/common/cs5536/cs5536_acc.c b/arch/mips/loongson/common/cs5536/cs5536_acc.c new file mode 100644 index 0000000..7212b08 --- /dev/null +++ b/arch/mips/loongson/common/cs5536/cs5536_acc.c @@ -0,0 +1,156 @@ +/* + * the ACC Virtual Support Module of AMD CS5536 + * + * Copyright (C) 2007 Lemote, Inc. & Institute of Computing Technology + * Author : jlliu, liujl@lemote.com + * + * Copyright (C) 2009 Lemote, Inc. & Institute of Computing Technology + * Author: Wu Zhangjin, wuzj@lemote.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include +#include + +/* + * acc_write: acc write transfering + */ + +void pci_acc_write_reg(int reg, u32 value) +{ + u32 hi = 0, lo = value; + + switch (reg) { + case PCI_COMMAND: + _rdmsr(GLIU_MSR_REG(GLIU_PAE), &hi, &lo); + if (value & PCI_COMMAND_MASTER) + lo |= (0x03 << 8); + else + lo &= ~(0x03 << 8); + _wrmsr(GLIU_MSR_REG(GLIU_PAE), hi, lo); + break; + case PCI_STATUS: + if (value & PCI_STATUS_PARITY) { + _rdmsr(SB_MSR_REG(SB_ERROR), &hi, &lo); + if (lo & SB_PARE_ERR_FLAG) { + lo = (lo & 0x0000ffff) | SB_PARE_ERR_FLAG; + _wrmsr(SB_MSR_REG(SB_ERROR), hi, lo); + } + } + break; + case PCI_BAR