From tabbott@MIT.EDU Fri May 1 00:54:00 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 01 May 2009 00:54:06 +0100 (BST) Received: from BISCAYNE-ONE-STATION.MIT.EDU ([18.7.7.80]:60448 "EHLO biscayne-one-station.mit.edu" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20026838AbZD3XyA (ORCPT ); Fri, 1 May 2009 00:54:00 +0100 Received: from outgoing.mit.edu (OUTGOING-AUTH.MIT.EDU [18.7.22.103]) by biscayne-one-station.mit.edu (8.13.6/8.9.2) with ESMTP id n3UNrWHT016874; Thu, 30 Apr 2009 19:53:33 -0400 (EDT) Received: from localhost (c-67-186-133-195.hsd1.ma.comcast.net [67.186.133.195]) (authenticated bits=0) (User authenticated as tabbott@ATHENA.MIT.EDU) by outgoing.mit.edu (8.13.6/8.12.4) with ESMTP id n3UNrVn7011398; Thu, 30 Apr 2009 19:53:32 -0400 (EDT) From: Tim Abbott To: Sam Ravnborg Cc: Linux kernel mailing list , Anders Kaseorg , Waseem Daher , Denys Vlasenko , Jeff Arnold , Ralf Baechle , linux-mips@linux-mips.org, Tim Abbott Subject: [PATCH 1/4] mips: use NOSAVE_DATA macro for .data.nosave section. Date: Thu, 30 Apr 2009 19:53:27 -0400 Message-Id: <1241135610-9012-2-git-send-email-tabbott@mit.edu> X-Mailer: git-send-email 1.6.2.1 In-Reply-To: <1241135610-9012-1-git-send-email-tabbott@mit.edu> References: <1241135610-9012-1-git-send-email-tabbott@mit.edu> X-Scanned-By: MIMEDefang 2.42 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22577 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: tabbott@MIT.EDU Precedence: bulk X-list: linux-mips This has the consequence of replacing the alignment of _PAGE_SIZE with an alignment of PAGE_SIZE. I believe these have the same value. .data.nosave should not need a separate output section; this change moves it into the .data section. Signed-off-by: Tim Abbott Cc: Ralf Baechle Cc: linux-mips@linux-mips.org --- arch/mips/kernel/vmlinux.lds.S | 10 +--------- 1 files changed, 1 insertions(+), 9 deletions(-) diff --git a/arch/mips/kernel/vmlinux.lds.S b/arch/mips/kernel/vmlinux.lds.S index 58738c8..2a6a995 100644 --- a/arch/mips/kernel/vmlinux.lds.S +++ b/arch/mips/kernel/vmlinux.lds.S @@ -78,7 +78,7 @@ SECTIONS */ . = ALIGN(_PAGE_SIZE); *(.data.init_task) - + NOSAVE_DATA DATA_DATA CONSTRUCTORS } @@ -96,14 +96,6 @@ SECTIONS *(.sdata) } - . = ALIGN(_PAGE_SIZE); - .data_nosave : { - __nosave_begin = .; - *(.data.nosave) - } - . = ALIGN(_PAGE_SIZE); - __nosave_end = .; - . = ALIGN(1 << CONFIG_MIPS_L1_CACHE_SHIFT); .data.cacheline_aligned : { *(.data.cacheline_aligned) -- 1.6.2.1 From tabbott@MIT.EDU Fri May 1 00:54:23 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 01 May 2009 00:54:30 +0100 (BST) Received: from BISCAYNE-ONE-STATION.MIT.EDU ([18.7.7.80]:60511 "EHLO biscayne-one-station.mit.edu" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20026843AbZD3XyR (ORCPT ); Fri, 1 May 2009 00:54:17 +0100 Received: from outgoing.mit.edu (OUTGOING-AUTH.MIT.EDU [18.7.22.103]) by biscayne-one-station.mit.edu (8.13.6/8.9.2) with ESMTP id n3UNrZUP016920; Thu, 30 Apr 2009 19:53:36 -0400 (EDT) Received: from localhost (c-67-186-133-195.hsd1.ma.comcast.net [67.186.133.195]) (authenticated bits=0) (User authenticated as tabbott@ATHENA.MIT.EDU) by outgoing.mit.edu (8.13.6/8.12.4) with ESMTP id n3UNrY3i011410; Thu, 30 Apr 2009 19:53:35 -0400 (EDT) From: Tim Abbott To: Sam Ravnborg Cc: Linux kernel mailing list , Anders Kaseorg , Waseem Daher , Denys Vlasenko , Jeff Arnold , Ralf Baechle , linux-mips@linux-mips.org, Tim Abbott Subject: [PATCH 4/4] mips: use .text, not .text.start, for lasat boot loader. Date: Thu, 30 Apr 2009 19:53:30 -0400 Message-Id: <1241135610-9012-5-git-send-email-tabbott@mit.edu> X-Mailer: git-send-email 1.6.2.1 In-Reply-To: <1241135610-9012-4-git-send-email-tabbott@mit.edu> References: <1241135610-9012-1-git-send-email-tabbott@mit.edu> <1241135610-9012-2-git-send-email-tabbott@mit.edu> <1241135610-9012-3-git-send-email-tabbott@mit.edu> <1241135610-9012-4-git-send-email-tabbott@mit.edu> X-Scanned-By: MIMEDefang 2.42 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22578 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: tabbott@MIT.EDU Precedence: bulk X-list: linux-mips There doesn't seem to be a reason to use a special section here, so just use the normal .text. Signed-off-by: Tim Abbott Cc: Ralf Baechle Cc: linux-mips@linux-mips.org --- arch/mips/lasat/image/head.S | 2 +- arch/mips/lasat/image/romscript.normal | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/mips/lasat/image/head.S b/arch/mips/lasat/image/head.S index efb95f2..c699363 100644 --- a/arch/mips/lasat/image/head.S +++ b/arch/mips/lasat/image/head.S @@ -1,7 +1,7 @@ #include .text - .section .text.start, "ax" + .section .text, "ax" .set noreorder .set mips3 diff --git a/arch/mips/lasat/image/romscript.normal b/arch/mips/lasat/image/romscript.normal index 988f8ad..f470353 100644 --- a/arch/mips/lasat/image/romscript.normal +++ b/arch/mips/lasat/image/romscript.normal @@ -4,7 +4,7 @@ SECTIONS { .text : { - *(.text.start) + *(.text) } /* Data in ROM */ -- 1.6.2.1 From tabbott@MIT.EDU Fri May 1 00:56:33 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 01 May 2009 00:56:39 +0100 (BST) Received: from BISCAYNE-ONE-STATION.MIT.EDU ([18.7.7.80]:60935 "EHLO biscayne-one-station.mit.edu" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20026850AbZD3X4d (ORCPT ); Fri, 1 May 2009 00:56:33 +0100 Received: from outgoing.mit.edu (OUTGOING-AUTH.MIT.EDU [18.7.22.103]) by biscayne-one-station.mit.edu (8.13.6/8.9.2) with ESMTP id n3UNrYHV016911; Thu, 30 Apr 2009 19:53:35 -0400 (EDT) Received: from localhost (c-67-186-133-195.hsd1.ma.comcast.net [67.186.133.195]) (authenticated bits=0) (User authenticated as tabbott@ATHENA.MIT.EDU) by outgoing.mit.edu (8.13.6/8.12.4) with ESMTP id n3UNrXp2011404; Thu, 30 Apr 2009 19:53:34 -0400 (EDT) From: Tim Abbott To: Sam Ravnborg Cc: Linux kernel mailing list , Anders Kaseorg , Waseem Daher , Denys Vlasenko , Jeff Arnold , Ralf Baechle , linux-mips@linux-mips.org, Tim Abbott Subject: [PATCH 3/4] mips: use new macros for .data.init_task. Date: Thu, 30 Apr 2009 19:53:29 -0400 Message-Id: <1241135610-9012-4-git-send-email-tabbott@mit.edu> X-Mailer: git-send-email 1.6.2.1 In-Reply-To: <1241135610-9012-3-git-send-email-tabbott@mit.edu> References: <1241135610-9012-1-git-send-email-tabbott@mit.edu> <1241135610-9012-2-git-send-email-tabbott@mit.edu> <1241135610-9012-3-git-send-email-tabbott@mit.edu> X-Scanned-By: MIMEDefang 2.42 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22579 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: tabbott@MIT.EDU Precedence: bulk X-list: linux-mips Signed-off-by: Tim Abbott Cc: Ralf Baechle Cc: linux-mips@linux-mips.org --- arch/mips/kernel/init_task.c | 5 ++--- arch/mips/kernel/vmlinux.lds.S | 3 +-- 2 files changed, 3 insertions(+), 5 deletions(-) diff --git a/arch/mips/kernel/init_task.c b/arch/mips/kernel/init_task.c index 149cd91..30051b4 100644 --- a/arch/mips/kernel/init_task.c +++ b/arch/mips/kernel/init_task.c @@ -25,9 +25,8 @@ EXPORT_SYMBOL(init_mm); * * The things we do for performance.. */ -union thread_union init_thread_union - __attribute__((__section__(".data.init_task"), - __aligned__(THREAD_SIZE))) = +union thread_union init_thread_union __init_task_data + __attribute__((__aligned__(THREAD_SIZE))) = { INIT_THREAD_INFO(init_task) }; /* diff --git a/arch/mips/kernel/vmlinux.lds.S b/arch/mips/kernel/vmlinux.lds.S index ba459cb..85085e3 100644 --- a/arch/mips/kernel/vmlinux.lds.S +++ b/arch/mips/kernel/vmlinux.lds.S @@ -76,8 +76,7 @@ SECTIONS * of ‘init_thread_union’ is greater than maximum * object file alignment. Using 32768 */ - . = ALIGN(_PAGE_SIZE); - *(.data.init_task) + INIT_TASK_DATA(_PAGE_SIZE) NOSAVE_DATA CACHELINE_ALIGNED_DATA(1 << CONFIG_MIPS_L1_CACHE_SHIFT) DATA_DATA -- 1.6.2.1 From tabbott@MIT.EDU Fri May 1 00:59:34 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 01 May 2009 00:59:40 +0100 (BST) Received: from BISCAYNE-ONE-STATION.MIT.EDU ([18.7.7.80]:61118 "EHLO biscayne-one-station.mit.edu" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20026857AbZD3X7e (ORCPT ); Fri, 1 May 2009 00:59:34 +0100 Received: from outgoing.mit.edu (OUTGOING-AUTH.MIT.EDU [18.7.22.103]) by biscayne-one-station.mit.edu (8.13.6/8.9.2) with ESMTP id n3UNrX7m016907; Thu, 30 Apr 2009 19:53:34 -0400 (EDT) Received: from localhost (c-67-186-133-195.hsd1.ma.comcast.net [67.186.133.195]) (authenticated bits=0) (User authenticated as tabbott@ATHENA.MIT.EDU) by outgoing.mit.edu (8.13.6/8.12.4) with ESMTP id n3UNrW7u011401; Thu, 30 Apr 2009 19:53:33 -0400 (EDT) From: Tim Abbott To: Sam Ravnborg Cc: Linux kernel mailing list , Anders Kaseorg , Waseem Daher , Denys Vlasenko , Jeff Arnold , Ralf Baechle , linux-mips@linux-mips.org, Tim Abbott Subject: [PATCH 2/4] mips: use new macro for .data.cacheline_aligned section. Date: Thu, 30 Apr 2009 19:53:28 -0400 Message-Id: <1241135610-9012-3-git-send-email-tabbott@mit.edu> X-Mailer: git-send-email 1.6.2.1 In-Reply-To: <1241135610-9012-2-git-send-email-tabbott@mit.edu> References: <1241135610-9012-1-git-send-email-tabbott@mit.edu> <1241135610-9012-2-git-send-email-tabbott@mit.edu> X-Scanned-By: MIMEDefang 2.42 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22580 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: tabbott@MIT.EDU Precedence: bulk X-list: linux-mips .data.cacheline_aligned should not need a separate output section; this change moves it into the .data section. Signed-off-by: Tim Abbott Cc: Ralf Baechle Cc: linux-mips@linux-mips.org --- arch/mips/kernel/vmlinux.lds.S | 6 +----- 1 files changed, 1 insertions(+), 5 deletions(-) diff --git a/arch/mips/kernel/vmlinux.lds.S b/arch/mips/kernel/vmlinux.lds.S index 2a6a995..ba459cb 100644 --- a/arch/mips/kernel/vmlinux.lds.S +++ b/arch/mips/kernel/vmlinux.lds.S @@ -79,6 +79,7 @@ SECTIONS . = ALIGN(_PAGE_SIZE); *(.data.init_task) NOSAVE_DATA + CACHELINE_ALIGNED_DATA(1 << CONFIG_MIPS_L1_CACHE_SHIFT) DATA_DATA CONSTRUCTORS } @@ -95,11 +96,6 @@ SECTIONS .sdata : { *(.sdata) } - - . = ALIGN(1 << CONFIG_MIPS_L1_CACHE_SHIFT); - .data.cacheline_aligned : { - *(.data.cacheline_aligned) - } _edata = .; /* End of data section */ /* will be freed after init */ -- 1.6.2.1 From tabbott@MIT.EDU Fri May 1 00:59:57 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 01 May 2009 01:00:03 +0100 (BST) Received: from BISCAYNE-ONE-STATION.MIT.EDU ([18.7.7.80]:61118 "EHLO biscayne-one-station.mit.edu" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S28573947AbZD3X7g (ORCPT ); Fri, 1 May 2009 00:59:36 +0100 Received: from outgoing.mit.edu (OUTGOING-AUTH.MIT.EDU [18.7.22.103]) by biscayne-one-station.mit.edu (8.13.6/8.9.2) with ESMTP id n3UNrV8C016871; Thu, 30 Apr 2009 19:53:32 -0400 (EDT) Received: from localhost (c-67-186-133-195.hsd1.ma.comcast.net [67.186.133.195]) (authenticated bits=0) (User authenticated as tabbott@ATHENA.MIT.EDU) by outgoing.mit.edu (8.13.6/8.12.4) with ESMTP id n3UNrUUe011393; Thu, 30 Apr 2009 19:53:30 -0400 (EDT) From: Tim Abbott To: Sam Ravnborg Cc: Linux kernel mailing list , Anders Kaseorg , Waseem Daher , Denys Vlasenko , Jeff Arnold , Ralf Baechle , linux-mips@linux-mips.org, Tim Abbott Subject: [PATCH 0/4] section name cleanup for mips Date: Thu, 30 Apr 2009 19:53:26 -0400 Message-Id: <1241135610-9012-1-git-send-email-tabbott@mit.edu> X-Mailer: git-send-email 1.6.2.1 X-Scanned-By: MIMEDefang 2.42 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22581 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: tabbott@MIT.EDU Precedence: bulk X-list: linux-mips This patch series cleans up the section names on the mips architecture. It requires the architecture-independent macro definitions from this patch series: The long-term goal here is to add support for building the kernel with -ffunction-sections -fdata-sections. This requires renaming all the magic section names in the kernel of the form .text.foo, .data.foo, .bss.foo, and .rodata.foo to not have collisions with sections generated for code like: static int nosave = 0; /* -fdata-sections places in .data.nosave */ static void head(); /* -ffunction-sections places in .text.head */ Note that these patches have not been boot-tested (aside from testing the analogous changes on x86), since I don't have access to the appropriate hardware. -Tim Abbott Tim Abbott (4): mips: use NOSAVE_DATA macro for .data.nosave section. mips: use new macro for .data.cacheline_aligned section. mips: use new macros for .data.init_task. mips: use .text, not .text.start, for lasat boot loader. arch/mips/kernel/init_task.c | 5 ++--- arch/mips/kernel/vmlinux.lds.S | 19 +++---------------- arch/mips/lasat/image/head.S | 2 +- arch/mips/lasat/image/romscript.normal | 2 +- 4 files changed, 7 insertions(+), 21 deletions(-) From aurelien@aurel32.net Fri May 1 08:57:36 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 01 May 2009 08:57:42 +0100 (BST) Received: from hall.aurel32.net ([88.191.82.174]:47254 "EHLO hall.aurel32.net" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20027027AbZEAH5g (ORCPT ); Fri, 1 May 2009 08:57:36 +0100 Received: from aurel32 by hall.aurel32.net with local (Exim 4.69) (envelope-from ) id 1Lzncg-0005bC-M2; Fri, 01 May 2009 09:57:30 +0200 Date: Fri, 1 May 2009 09:57:30 +0200 From: Aurelien Jarno To: luk@debian.org, linux-mips@linux-mips.org Subject: Re: kernel for a Broadcom Swarm board Message-ID: <20090501075730.GC16244@hall.aurel32.net> References: <49FA27FA.3070408@debian.org> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-15 Content-Disposition: inline In-Reply-To: <49FA27FA.3070408@debian.org> X-Mailer: Mutt 1.5.18 (2008-05-17) User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22582 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: aurelien@aurel32.net Precedence: bulk X-list: linux-mips On Fri, May 01, 2009 at 12:36:42AM +0200, Luk Claes wrote: > Hi > > > | [ 0.000000] Broadcom SiByte BCM1250 B2 @ 800 MHz (SB1 rev 2) > > | [ 0.000000] Board type: SiByte BCM91250A (SWARM) > > | [ 0.000000] This kernel optimized for board runs with CFE > > | [ 0.000000] Determined physical RAM map: > > | [ 0.000000] memory: 000000000fe47e00 @ 0000000000000000 (usable) > > | [ 0.000000] Initrd not found or empty - disabling initrd > > | [ 0.000000] Zone PFN ranges: > > | [ 0.000000] DMA32 0x00000000 -> 0x00100000 > > | [ 0.000000] Normal 0x00100000 -> 0x00100000 > > | [ 0.000000] Movable zone start PFN for each node > > | [ 0.000000] early_node_map[1] active PFN ranges > > | [ 0.000000] 0: 0x00000000 -> 0x0000fe47 > > | [ 0.000000] Detected 1 available secondary CPU(s) > > | [ 0.000000] Built 1 zonelists in Zone order, mobility grouping > on. Total > > pages: 64205 > > | [ 0.000000] Kernel command line: root=/dev/hdc1 console=duart0 > > | [ 0.000000] Primary instruction cache 32kB, VIVT, 4-way, linesize > 32 bytes. > > | [ 0.000000] Primary data cache 32kB, 4-way, PIPT, no aliases, > linesize 32 > > bytes > > | [ 0.000000] PID hash table entries: 1024 (order: 10, 8192 bytes) > > > > And then it hangs... > > The zeros look like there are no timing interrupts happening. It's a > pity we don't have hardware to test which kernel version introduced the > bug (for instance with git-bisect and reboots). > I think the zeros are normal here, on other machines, the values actually start to change just after this line. -- Aurelien Jarno GPG: 1024D/F1BCDB73 aurelien@aurel32.net http://www.aurel32.net From sam@ravnborg.org Fri May 1 10:03:01 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 01 May 2009 10:03:08 +0100 (BST) Received: from pfepa.post.tele.dk ([195.41.46.235]:49144 "EHLO pfepa.post.tele.dk" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20027053AbZEAJDB (ORCPT ); Fri, 1 May 2009 10:03:01 +0100 Received: from ravnborg.org (x1-6-00-1e-2a-84-ae-3e.k225.webspeed.dk [80.163.61.94]) by pfepa.post.tele.dk (Postfix) with ESMTP id F248FA5005B; Fri, 1 May 2009 11:02:45 +0200 (CEST) Received: by ravnborg.org (Postfix, from userid 500) id 35671580D0; Fri, 1 May 2009 11:04:56 +0200 (CEST) Date: Fri, 1 May 2009 11:04:56 +0200 From: Sam Ravnborg To: Tim Abbott Cc: Linux kernel mailing list , Anders Kaseorg , Waseem Daher , Denys Vlasenko , Jeff Arnold , Benjamin Herrenschmidt , Bryan Wu , Chris Zankel , Cyrill Gorcunov , David Howells , "David S. Miller" , dev-etrax@axis.com, Geert Uytterhoeven , Greg Ungerer , Haavard Skinnemoen , Heiko Carstens , Helge Deller , Hirokazu Takata , "H. Peter Anvin" , Ingo Molnar , Jeff Dike , Jesper Nilsson , Kyle McMartin , Linus Torvalds , linux-alpha@vger.kernel.org, linux-ia64@vger.kernel.org, linux-m68k@vger.kernel.org, linux-mips@linux-mips.org, linux-parisc@vger.kernel.org, linuxppc-dev@ozlabs.org, linux-s390@vger.kernel.org, linux-sh@vger.kernel.org, Martin Schwidefsky , Michal Simek , microblaze-uclinux@itee.uq.edu.au, Mikael Starvik , Paul Mackerras , Paul Mundt , Ralf Baechle , Richard Henderson , Roman Zippel , Russell King , sparclinux@vger.kernel.org, Thomas Gleixner , Tony Luck , uclinux-dist-devel@blackfin.uclinux.org, user-mode-linux-devel@lists.sourceforge.net, Yoshinori Sato Subject: Re: [PATCH v2 0/6] macros for section name cleanup Message-ID: <20090501090455.GA18326@uranus.ravnborg.org> References: <1241121253-32341-1-git-send-email-tabbott@mit.edu> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1241121253-32341-1-git-send-email-tabbott@mit.edu> User-Agent: Mutt/1.4.2.1i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22583 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sam@ravnborg.org Precedence: bulk X-list: linux-mips On Thu, Apr 30, 2009 at 03:54:07PM -0400, Tim Abbott wrote: > (this patch series differs from v1 only in the CC list; some of the > architecture lists I sent the previous one to are moderated against > non-members; all replies should go to this version). > > Here are the architecture-independent macro definitions needed for > to clean up the kernel's section names. The overall diffstat from > this section name cleanup project is: > > 96 files changed, 261 insertions(+), 503 deletions(-) > > The decrease results from removing a lot of redundancy in the linker > scripts. > > The long-term goal here is to add support for building the kernel with > -ffunction-sections -fdata-sections. This requires renaming all the > magic section names in the kernel of the form .text.foo, .data.foo, > .bss.foo, and .rodata.foo to not have collisions with sections > generated for code like: > > static int nosave = 0; /* -fdata-sections places in .data.nosave */ > static void head(); /* -ffunction-sections places in .text.head */ > > Sam Ravnborg proposed that rather than just renaming all the sections > outright, we should start by first getting more control over the > section names used in the kernel so that we can later rename sections > without touching too many files. These patch series implement that > cleanup. Later, there will be another patch series to actually rename > the sections. > > I'm hoping we can get just these macro definitions into 2.6.30 so that > the arch maintainers don't have to grab the macro definitions for > their trees while reviewing the patches for 2.6.31. > > Shortly, I'm going to send one patch series for each of the > architectures updating those architectures to use these new macros > (and otherwise cleaning up section names on those architectures). Hi Tim. We agreed to get the common stuff and one architecture done before proceeding with the rest. Please stick to that plan so we avoid patch-bombing lkml + maintainers. When we have this ready it will be a simple one-patch-per-arch to cover the rest. I will comment on your common patches for now. Sam From sam@ravnborg.org Fri May 1 10:16:45 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 01 May 2009 10:16:52 +0100 (BST) Received: from pfepa.post.tele.dk ([195.41.46.235]:55489 "EHLO pfepa.post.tele.dk" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20027071AbZEAJQp (ORCPT ); Fri, 1 May 2009 10:16:45 +0100 Received: from ravnborg.org (x1-6-00-1e-2a-84-ae-3e.k225.webspeed.dk [80.163.61.94]) by pfepa.post.tele.dk (Postfix) with ESMTP id 3888FA50039; Fri, 1 May 2009 11:16:37 +0200 (CEST) Received: by ravnborg.org (Postfix, from userid 500) id 91906580D0; Fri, 1 May 2009 11:18:48 +0200 (CEST) Date: Fri, 1 May 2009 11:18:48 +0200 From: Sam Ravnborg To: Tim Abbott Cc: Linux kernel mailing list , Anders Kaseorg , Waseem Daher , Denys Vlasenko , Jeff Arnold , Benjamin Herrenschmidt , Bryan Wu , Chris Zankel , Cyrill Gorcunov , David Howells , "David S. Miller" , dev-etrax@axis.com, Geert Uytterhoeven , Greg Ungerer , Haavard Skinnemoen , Heiko Carstens , Helge Deller , Hirokazu Takata , "H. Peter Anvin" , Ingo Molnar , Jeff Dike , Jesper Nilsson , Kyle McMartin , Linus Torvalds , linux-alpha@vger.kernel.org, linux-ia64@vger.kernel.org, linux-m68k@vger.kernel.org, linux-mips@linux-mips.org, linux-parisc@vger.kernel.org, linuxppc-dev@ozlabs.org, linux-s390@vger.kernel.org, linux-sh@vger.kernel.org, Martin Schwidefsky , Michal Simek , microblaze-uclinux@itee.uq.edu.au, Mikael Starvik , Paul Mackerras , Paul Mundt , Ralf Baechle , Richard Henderson , Roman Zippel , Russell King , sparclinux@vger.kernel.org, Thomas Gleixner , Tony Luck , uclinux-dist-devel@blackfin.uclinux.org, user-mode-linux-devel@lists.sourceforge.net, Yoshinori Sato Subject: Re: [PATCH v2 1/6] Add new macros for page-aligned data and bss sections. Message-ID: <20090501091848.GB18326@uranus.ravnborg.org> References: <1241121253-32341-1-git-send-email-tabbott@mit.edu> <1241121253-32341-2-git-send-email-tabbott@mit.edu> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1241121253-32341-2-git-send-email-tabbott@mit.edu> User-Agent: Mutt/1.4.2.1i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22584 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sam@ravnborg.org Precedence: bulk X-list: linux-mips On Thu, Apr 30, 2009 at 03:54:08PM -0400, Tim Abbott wrote: > This patch is preparation for replacing most uses of > ".bss.page_aligned" and ".data.page_aligned" in the kernel with > macros, so that the section name can later be changed without having > to touch a lot of the kernel. > > The long-term goal here is to be able to change the kernel's magic > section names to those that are compatible with -ffunction-sections > -fdata-sections. This requires renaming all magic sections with names > of the form ".data.foo". > > Signed-off-by: Tim Abbott > Cc: Sam Ravnborg > Acked-by: David Howells > --- > include/asm-generic/vmlinux.lds.h | 8 ++++++++ > include/linux/linkage.h | 9 +++++++++ > 2 files changed, 17 insertions(+), 0 deletions(-) > > diff --git a/include/asm-generic/vmlinux.lds.h b/include/asm-generic/vmlinux.lds.h > index 89853bc..3d88c87 100644 > --- a/include/asm-generic/vmlinux.lds.h > +++ b/include/asm-generic/vmlinux.lds.h > @@ -116,6 +116,14 @@ > FTRACE_EVENTS() \ > TRACE_SYSCALLS() > > +#define PAGE_ALIGNED_DATA \ > + . = ALIGN(PAGE_SIZE); \ > + *(.data.page_aligned) > + > +#define PAGE_ALIGNED_BSS \ > + . = ALIGN(PAGE_SIZE); \ > + *(.bss.page_aligned) > + > #define RO_DATA(align) \ > . = ALIGN((align)); \ > .rodata : AT(ADDR(.rodata) - LOAD_OFFSET) { \ > diff --git a/include/linux/linkage.h b/include/linux/linkage.h > index fee9e59..af051fc 100644 > --- a/include/linux/linkage.h > +++ b/include/linux/linkage.h > @@ -22,6 +22,15 @@ > #define __page_aligned_bss __section(.bss.page_aligned) __aligned(PAGE_SIZE) > > /* > + * For assembly routines. > + * > + * Note when using these that you must specify the appropriate > + * alignment directives yourself > + */ > +#define __PAGE_ALIGNED_DATA .section ".data.page_aligned", "aw", @progbits > +#define __PAGE_ALIGNED_BSS .section ".bss.page_aligned", "aw", @nobits The above will work on most architectures but fails (silently?) on arm. arm uses %{progbits,nobits} where all other uses @{nobits,progbits}. I know we do not use page_aligned in arm assembler code for now, but if we do then it should work. It is my understanding that the linker will automatically assume nobits for section names starting with .bss and likewise progbits for section names starting with .data - so we can leave them out? Sam From sam@ravnborg.org Fri May 1 10:19:10 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 01 May 2009 10:19:17 +0100 (BST) Received: from pfepb.post.tele.dk ([195.41.46.236]:34575 "EHLO pfepb.post.tele.dk" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20025248AbZEAJTK (ORCPT ); Fri, 1 May 2009 10:19:10 +0100 Received: from ravnborg.org (x1-6-00-1e-2a-84-ae-3e.k225.webspeed.dk [80.163.61.94]) by pfepb.post.tele.dk (Postfix) with ESMTP id 12570F8404B; Fri, 1 May 2009 11:19:03 +0200 (CEST) Received: by ravnborg.org (Postfix, from userid 500) id 804EA580D0; Fri, 1 May 2009 11:21:14 +0200 (CEST) Date: Fri, 1 May 2009 11:21:14 +0200 From: Sam Ravnborg To: Tim Abbott Cc: Linux kernel mailing list , Anders Kaseorg , Waseem Daher , Denys Vlasenko , Jeff Arnold , Benjamin Herrenschmidt , Bryan Wu , Chris Zankel , Cyrill Gorcunov , David Howells , "David S. Miller" , dev-etrax@axis.com, Geert Uytterhoeven , Greg Ungerer , Haavard Skinnemoen , Heiko Carstens , Helge Deller , Hirokazu Takata , "H. Peter Anvin" , Ingo Molnar , Jeff Dike , Jesper Nilsson , Kyle McMartin , Linus Torvalds , linux-alpha@vger.kernel.org, linux-ia64@vger.kernel.org, linux-m68k@vger.kernel.org, linux-mips@linux-mips.org, linux-parisc@vger.kernel.org, linuxppc-dev@ozlabs.org, linux-s390@vger.kernel.org, linux-sh@vger.kernel.org, Martin Schwidefsky , Michal Simek , microblaze-uclinux@itee.uq.edu.au, Mikael Starvik , Paul Mackerras , Paul Mundt , Ralf Baechle , Richard Henderson , Roman Zippel , Russell King , sparclinux@vger.kernel.org, Thomas Gleixner , Tony Luck , uclinux-dist-devel@blackfin.uclinux.org, user-mode-linux-devel@lists.sourceforge.net, Yoshinori Sato Subject: Re: [PATCH v2 2/6] Add new NOSAVE_DATA linker script macro. Message-ID: <20090501092114.GC18326@uranus.ravnborg.org> References: <1241121253-32341-1-git-send-email-tabbott@mit.edu> <1241121253-32341-2-git-send-email-tabbott@mit.edu> <1241121253-32341-3-git-send-email-tabbott@mit.edu> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1241121253-32341-3-git-send-email-tabbott@mit.edu> User-Agent: Mutt/1.4.2.1i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22585 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sam@ravnborg.org Precedence: bulk X-list: linux-mips On Thu, Apr 30, 2009 at 03:54:09PM -0400, Tim Abbott wrote: > This patch is preparation for replacing most ".data.nosave" in the > kernel with macros, so that the section name can later be changed > without having to touch a lot of the kernel. > > The long-term goal here is to be able to change the kernel's magic > section names to those that are compatible with -ffunction-sections > -fdata-sections. This requires renaming all magic sections with names > of the form ".data.foo". > > Signed-off-by: Tim Abbott > Cc: Sam Ravnborg > --- > include/asm-generic/vmlinux.lds.h | 7 +++++++ > 1 files changed, 7 insertions(+), 0 deletions(-) > > diff --git a/include/asm-generic/vmlinux.lds.h b/include/asm-generic/vmlinux.lds.h > index 3d88c87..f5ebd2b 100644 > --- a/include/asm-generic/vmlinux.lds.h > +++ b/include/asm-generic/vmlinux.lds.h > @@ -124,6 +124,13 @@ > . = ALIGN(PAGE_SIZE); \ > *(.bss.page_aligned) > > +#define NOSAVE_DATA \ > + . = ALIGN(PAGE_SIZE); \ > + __nosave_begin = .; \ > + *(.data.nosave) \ > + . = ALIGN(PAGE_SIZE); \ > + __nosave_end = .; > + You need to use: VMLINUX_SYMBOL(__nosave_begin) = .; Otherwise architectures such as m68k wil break as they add a leading underscore. See other symbols that is defined inside vmlinux.lds.h Sam From sam@ravnborg.org Fri May 1 10:42:04 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 01 May 2009 10:42:10 +0100 (BST) Received: from pfepa.post.tele.dk ([195.41.46.235]:39850 "EHLO pfepa.post.tele.dk" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20027118AbZEAJmE (ORCPT ); Fri, 1 May 2009 10:42:04 +0100 Received: from ravnborg.org (x1-6-00-1e-2a-84-ae-3e.k225.webspeed.dk [80.163.61.94]) by pfepa.post.tele.dk (Postfix) with ESMTP id CF77FA50033; Fri, 1 May 2009 11:41:56 +0200 (CEST) Received: by ravnborg.org (Postfix, from userid 500) id 3993E580D0; Fri, 1 May 2009 11:44:07 +0200 (CEST) Date: Fri, 1 May 2009 11:44:07 +0200 From: Sam Ravnborg To: Tim Abbott , Christoph Lameter Cc: Anders Kaseorg , Waseem Daher , Denys Vlasenko , Jeff Arnold , Benjamin Herrenschmidt , Bryan Wu , Chris Zankel , Cyrill Gorcunov , David Howells , "David S. Miller" , dev-etrax@axis.com, Geert Uytterhoeven , Greg Ungerer , Haavard Skinnemoen , Heiko Carstens , Helge Deller , Hirokazu Takata , "H. Peter Anvin" , Ingo Molnar , Jeff Dike , Jesper Nilsson , Kyle McMartin , Linus Torvalds , linux-alpha@vger.kernel.org, linux-am33-list@redhat.com, linux-arm-kernel@lists.arm.linux.org.uk, linux-ia64@vger.kernel.org, linux-m32r@ml.linux-m32r.org, linux-m68k@vger.kernel.org, linux-mips@linux-mips.org, linux-parisc@vger.kernel.org, linuxppc-dev@ozlabs.org, linux-s390@vger.kernel.org, linux-sh@vger.kernel.org, Martin Schwidefsky , Michal Simek , microblaze-uclinux@itee.uq.edu.au, Mikael Starvik , Paul Mackerras , Paul Mundt , Ralf Baechle , Richard Henderson , Roman Zippel , Russell King , sparclinux@vger.kernel.org, Thomas Gleixner , Tony Luck , uclinux-dist-devel@blackfin.uclinux.org, user-mode-linux-devel@lists.sourceforge.net, Yoshinori Sato Subject: Re: [PATCH 6/6] Add support for __read_mostly to linux/cache.h Message-ID: <20090501094407.GD18326@uranus.ravnborg.org> References: <1241119956-31453-1-git-send-email-tabbott@mit.edu> <1241119956-31453-2-git-send-email-tabbott@mit.edu> <1241119956-31453-3-git-send-email-tabbott@mit.edu> <1241119956-31453-4-git-send-email-tabbott@mit.edu> <1241119956-31453-5-git-send-email-tabbott@mit.edu> <1241119956-31453-6-git-send-email-tabbott@mit.edu> <1241119956-31453-7-git-send-email-tabbott@mit.edu> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1241119956-31453-7-git-send-email-tabbott@mit.edu> User-Agent: Mutt/1.4.2.1i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22586 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sam@ravnborg.org Precedence: bulk X-list: linux-mips On Thu, Apr 30, 2009 at 03:32:36PM -0400, Tim Abbott wrote: > Signed-off-by: Tim Abbott > --- > include/linux/cache.h | 6 ++++++ > 1 files changed, 6 insertions(+), 0 deletions(-) > > diff --git a/include/linux/cache.h b/include/linux/cache.h > index 97e2488..99d8a6f 100644 > --- a/include/linux/cache.h > +++ b/include/linux/cache.h > @@ -13,7 +13,13 @@ > #endif > > #ifndef __read_mostly > +#ifdef CONFIG_HAVE_READ_MOSTLY_DATA > +#define __read_mostly __attribute__((__section__(".data.read_mostly"))) > +#define __READ_MOSTLY .section ".data.read_mostly", "aw" > +#else > #define __read_mostly > +#define __READ_MOSTLY > +#endif /* CONFIG_HAVE_READ_MOSTLY_DATA */ > #endif Are there any specific reason why we do not support read_mostly on all architectures? read_mostly is about grouping rarely written data together so what is needed is to introduce this section in the remaining archtectures. Christoph - git log says you did the inital implmentation. Do you agree? Sam From ralf@h5.dl5rb.org.uk Fri May 1 14:47:32 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 01 May 2009 14:47:35 +0100 (BST) Received: from localhost.localdomain ([127.0.0.1]:45688 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-FAIL) by ftp.linux-mips.org with ESMTP id S20027498AbZEANrc (ORCPT ); Fri, 1 May 2009 14:47:32 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id n41DlRkI021663; Fri, 1 May 2009 15:47:29 +0200 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id n41DlLfa021660; Fri, 1 May 2009 15:47:21 +0200 Date: Fri, 1 May 2009 15:47:21 +0200 From: Ralf Baechle To: Florian Fainelli Cc: linux-mips@linux-mips.org, David Daney Subject: Re: [PATCH] flash_setup should only be built when CONFIG_MTD is enabled Message-ID: <20090501134720.GA15672@linux-mips.org> References: <200904301748.52718.florian@openwrt.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <200904301748.52718.florian@openwrt.org> User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22587 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Thu, Apr 30, 2009 at 05:48:51PM +0200, Florian Fainelli wrote: > Building flash_setup while CONFIG_MTD is not enabled does work, but > results in the following oops while booting: > > Bootbus flash: Setting flash for 32MB flash at 0x1dc00000 > Kernel bug detected[#1]: > Cpu 0 > $ 0 : 0000000000000000 0000000000000010 000000000000003d 0000000000000002 > $ 4 : 0000000000000001 0000000000000000 ffffffffffffffff 0000000000000d52 > $ 8 : 0000000000000d52 000000000000003e 000000000000000a 0000000000000d17 > $12 : 0000000000000031 ffffffff81105e2c 00000000f34c39b5 0000000017da5c01 > $16 : ffffffff813ab588 ffffffff8138b514 0000000000000001 ffffffff814d2390 > $20 : 0000000000000010 0000000000000010 0000000000000000 0000000000000000 > $24 : 000000000931a549 ffffffff8110e68c > $28 : a800000007828000 a80000000782bf00 0000000000000000 ffffffff8138b594 > Hi : 0000000000000191 > Lo : 36978d4fdf254137 > epc : ffffffff8138b594 0xffffffff8138b594 > Not tainted > ra : ffffffff8138b594 0xffffffff8138b594 > Status: 10008ce3 KX SX UX KERNEL EXL IE > Cause : 00800024 > PrId : 000d0601 (Cavium Octeon) > Modules linked in: > Process swapper (pid: 1, threadinfo=a800000007828000, task=a800000007825540, tls=0000000000000000) > Stack : ffffffff813ab580 ffffffff8110d918 0000000007885780 ffffffff81385080 > ffffffff81385080 ffffffff8116ca10 3135310000000000 0000000000000000 > 0000000000000098 ffffffff81360000 ffffffff81350000 ffffffff813ab588 > ffffffff813ab5d0 ffffffff81350000 ffffffff814d2390 ffffffff813862e8 > 000000000000ffff 0000000000000000 0000000000000000 0000000000000000 > 0000000000000000 0000000000000000 0000000000000000 0000000000000000 > 0000000000000000 ffffffff81114f38 0000000000000000 0000000000000000 > 0000000000000000 0000000000000000 0000000000000000 0000000000000000 > Call Trace:[] 0xffffffff8110d918 > [] 0xffffffff8116ca10 > [] 0xffffffff813862e8 > [] 0xffffffff81114f38 > > This patch makes flash_setup be compiled only when CONFIG_MTD > which solves issue, the MTD driver then fails to register but this is > less critical. I think your code blows up if !CONFIG_MTD_COMPLEX_MAPPINGS and !CONFIG_MTD_MAP_BANK_WIDTH_1 in which case simple_map_init is defined as: #define simple_map_init(map) BUG_ON(!map_bankwidth_supported((map)->bankwidth)) bankwidth is 1, so: static inline int map_bankwidth_supported(int w) { switch (w) { #ifdef CONFIG_MTD_MAP_BANK_WIDTH_1 case 1: #endif return 1; [...] default: return 0; } } Ralf From ralf@h5.dl5rb.org.uk Fri May 1 14:54:47 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 01 May 2009 14:54:49 +0100 (BST) Received: from localhost.localdomain ([127.0.0.1]:48420 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-FAIL) by ftp.linux-mips.org with ESMTP id S20027512AbZEANyr (ORCPT ); Fri, 1 May 2009 14:54:47 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id n41Dsiw4021881; Fri, 1 May 2009 15:54:44 +0200 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id n41Dsh3m021878; Fri, 1 May 2009 15:54:43 +0200 Date: Fri, 1 May 2009 15:54:43 +0200 From: Ralf Baechle To: Aurelien Jarno Cc: luk@debian.org, linux-mips@linux-mips.org Subject: Re: kernel for a Broadcom Swarm board Message-ID: <20090501135443.GB15672@linux-mips.org> References: <49FA27FA.3070408@debian.org> <20090501075730.GC16244@hall.aurel32.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20090501075730.GC16244@hall.aurel32.net> User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22588 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Fri, May 01, 2009 at 09:57:30AM +0200, Aurelien Jarno wrote: > > > | [ 0.000000] PID hash table entries: 1024 (order: 10, 8192 bytes) > > > > > > And then it hangs... > > > > The zeros look like there are no timing interrupts happening. It's a > > pity we don't have hardware to test which kernel version introduced the > > bug (for instance with git-bisect and reboots). > > > > I think the zeros are normal here, on other machines, the values > actually start to change just after this line. They are completly normal and I'd be happy if people disable CONFIG_PRINTK_TIME for readability when posting kernel messages. Ralf From tabbott@MIT.EDU Fri May 1 15:01:07 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 01 May 2009 15:01:13 +0100 (BST) Received: from BISCAYNE-ONE-STATION.MIT.EDU ([18.7.7.80]:37425 "EHLO biscayne-one-station.mit.edu" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20027528AbZEAOBH (ORCPT ); Fri, 1 May 2009 15:01:07 +0100 Received: from outgoing.mit.edu (OUTGOING-AUTH.MIT.EDU [18.7.22.103]) by biscayne-one-station.mit.edu (8.13.6/8.9.2) with ESMTP id n41Dsh2v003169; Fri, 1 May 2009 09:54:43 -0400 (EDT) Received: from localhost (VINEGAR-POT.MIT.EDU [18.181.0.51]) (authenticated bits=0) (User authenticated as tabbott@ATHENA.MIT.EDU) by outgoing.mit.edu (8.13.6/8.12.4) with ESMTP id n41DsY94028568; Fri, 1 May 2009 09:54:35 -0400 (EDT) Date: Fri, 1 May 2009 09:54:34 -0400 (EDT) From: Tim Abbott To: Sam Ravnborg cc: Linux kernel mailing list , Anders Kaseorg , Waseem Daher , Denys Vlasenko , Jeff Arnold , Benjamin Herrenschmidt , Bryan Wu , Chris Zankel , Cyrill Gorcunov , David Howells , "David S. Miller" , dev-etrax@axis.com, Geert Uytterhoeven , Greg Ungerer , Haavard Skinnemoen , Heiko Carstens , Helge Deller , Hirokazu Takata , "H. Peter Anvin" , Ingo Molnar , Jeff Dike , Jesper Nilsson , Kyle McMartin , Linus Torvalds , linux-alpha@vger.kernel.org, linux-ia64@vger.kernel.org, linux-m68k@vger.kernel.org, linux-mips@linux-mips.org, linux-parisc@vger.kernel.org, linuxppc-dev@ozlabs.org, linux-s390@vger.kernel.org, linux-sh@vger.kernel.org, Martin Schwidefsky , Michal Simek , microblaze-uclinux@itee.uq.edu.au, Mikael Starvik , Paul Mackerras , Paul Mundt , Ralf Baechle , Richard Henderson , Roman Zippel , Russell King , sparclinux@vger.kernel.org, Thomas Gleixner , Tony Luck , uclinux-dist-devel@blackfin.uclinux.org, user-mode-linux-devel@lists.sourceforge.net, Yoshinori Sato Subject: Re: [PATCH v2 1/6] Add new macros for page-aligned data and bss sections. In-Reply-To: <20090501091848.GB18326@uranus.ravnborg.org> Message-ID: References: <1241121253-32341-1-git-send-email-tabbott@mit.edu> <1241121253-32341-2-git-send-email-tabbott@mit.edu> <20090501091848.GB18326@uranus.ravnborg.org> User-Agent: Alpine 1.10 (DEB 962 2008-03-14) MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII X-Scanned-By: MIMEDefang 2.42 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22589 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: tabbott@MIT.EDU Precedence: bulk X-list: linux-mips On Fri, 1 May 2009, Sam Ravnborg wrote: > On Thu, Apr 30, 2009 at 03:54:08PM -0400, Tim Abbott wrote: > > +#define __PAGE_ALIGNED_DATA .section ".data.page_aligned", "aw", @progbits > > +#define __PAGE_ALIGNED_BSS .section ".bss.page_aligned", "aw", @nobits > > It is my understanding that the linker will automatically > assume nobits for section names starting with .bss and likewise > progbits for section names starting with .data - so we can leave them out? I believe that is correct. -Tim Abbott From sam@ravnborg.org Fri May 1 15:19:06 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 01 May 2009 15:19:12 +0100 (BST) Received: from pfepb.post.tele.dk ([195.41.46.236]:51679 "EHLO pfepb.post.tele.dk" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20027554AbZEAOTG (ORCPT ); Fri, 1 May 2009 15:19:06 +0100 Received: from ravnborg.org (x1-6-00-1e-2a-84-ae-3e.k225.webspeed.dk [80.163.61.94]) by pfepb.post.tele.dk (Postfix) with ESMTP id 32470F84029; Fri, 1 May 2009 16:19:00 +0200 (CEST) Received: by ravnborg.org (Postfix, from userid 500) id 00E09580D0; Fri, 1 May 2009 16:21:10 +0200 (CEST) Date: Fri, 1 May 2009 16:21:10 +0200 From: Sam Ravnborg To: Tim Abbott Cc: Linux kernel mailing list , Anders Kaseorg , Waseem Daher , Denys Vlasenko , Jeff Arnold , Benjamin Herrenschmidt , Bryan Wu , Chris Zankel , Cyrill Gorcunov , David Howells , "David S. Miller" , dev-etrax@axis.com, Geert Uytterhoeven , Greg Ungerer , Haavard Skinnemoen , Heiko Carstens , Helge Deller , Hirokazu Takata , "H. Peter Anvin" , Ingo Molnar , Jeff Dike , Jesper Nilsson , Kyle McMartin , Linus Torvalds , linux-alpha@vger.kernel.org, linux-ia64@vger.kernel.org, linux-m68k@vger.kernel.org, linux-mips@linux-mips.org, linux-parisc@vger.kernel.org, linuxppc-dev@ozlabs.org, linux-s390@vger.kernel.org, linux-sh@vger.kernel.org, Martin Schwidefsky , Michal Simek , microblaze-uclinux@itee.uq.edu.au, Mikael Starvik , Paul Mackerras , Paul Mundt , Ralf Baechle , Richard Henderson , Roman Zippel , Russell King , sparclinux@vger.kernel.org, Thomas Gleixner , Tony Luck , uclinux-dist-devel@blackfin.uclinux.org, user-mode-linux-devel@lists.sourceforge.net, Yoshinori Sato Subject: Re: [PATCH v2 0/6] macros for section name cleanup Message-ID: <20090501142110.GA25236@uranus.ravnborg.org> References: <1241121253-32341-1-git-send-email-tabbott@mit.edu> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1241121253-32341-1-git-send-email-tabbott@mit.edu> User-Agent: Mutt/1.4.2.1i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22590 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sam@ravnborg.org Precedence: bulk X-list: linux-mips On Thu, Apr 30, 2009 at 03:54:07PM -0400, Tim Abbott wrote: > (this patch series differs from v1 only in the CC list; some of the > architecture lists I sent the previous one to are moderated against > non-members; all replies should go to this version). > > Here are the architecture-independent macro definitions needed for > to clean up the kernel's section names. The overall diffstat from > this section name cleanup project is: > > 96 files changed, 261 insertions(+), 503 deletions(-) > > The decrease results from removing a lot of redundancy in the linker > scripts. > > The long-term goal here is to add support for building the kernel with > -ffunction-sections -fdata-sections. This requires renaming all the > magic section names in the kernel of the form .text.foo, .data.foo, > .bss.foo, and .rodata.foo to not have collisions with sections > generated for code like: > > static int nosave = 0; /* -fdata-sections places in .data.nosave */ > static void head(); /* -ffunction-sections places in .text.head */ > > Sam Ravnborg proposed that rather than just renaming all the sections > outright, we should start by first getting more control over the > section names used in the kernel so that we can later rename sections > without touching too many files. These patch series implement that > cleanup. Later, there will be another patch series to actually rename > the sections. > > I'm hoping we can get just these macro definitions into 2.6.30 so that > the arch maintainers don't have to grab the macro definitions for > their trees while reviewing the patches for 2.6.31. > > Shortly, I'm going to send one patch series for each of the > architectures updating those architectures to use these new macros > (and otherwise cleaning up section names on those architectures). > > -Tim Abbott > > Tim Abbott (6): > Add new macros for page-aligned data and bss sections. > Add new NOSAVE_DATA linker script macro. > Add new CACHELINE_ALIGNED_DATA linker script macro. > Add new INIT_TASK_DATA() linker script macro. > Add new READ_MOSTLY_DATA(align) linker script macro. I am about to apply this part of your patches. I am doing some additional modifications and will most likely apply them as one patch. Will post to linux-arch for review when it is ready. Sam From jfraser@broadcom.com Fri May 1 16:17:16 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 01 May 2009 16:17:23 +0100 (BST) Received: from mms1.broadcom.com ([216.31.210.17]:2681 "EHLO mms1.broadcom.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S28574141AbZEAPRQ (ORCPT ); Fri, 1 May 2009 16:17:16 +0100 Received: from [10.9.200.131] by mms1.broadcom.com with ESMTP (Broadcom SMTP Relay (Email Firewall v6.3.2)); Fri, 01 May 2009 08:16:55 -0700 X-Server-Uuid: 02CED230-5797-4B57-9875-D5D2FEE4708A Received: from mail-irva-13.broadcom.com (10.11.16.103) by IRVEXCHHUB01.corp.ad.broadcom.com (10.9.200.131) with Microsoft SMTP Server id 8.1.358.0; Fri, 1 May 2009 08:16:55 -0700 Received: from [10.28.6.13] (lab-mhtb-013.ne.broadcom.com [10.28.6.13]) by mail-irva-13.broadcom.com (Postfix) with ESMTP id CB6AB74D03; Fri, 1 May 2009 08:16:54 -0700 (PDT) Subject: Re: kernel for a Broadcom Swarm board From: "Jon Fraser" Reply-to: jfraser@broadcom.com To: "luk@debian.org" , "linux-mips@linux-mips.org" cc: jfraser@broadcom.com In-Reply-To: <49FA27FA.3070408@debian.org> References: <49FA27FA.3070408@debian.org> Organization: Broadcom Date: Fri, 1 May 2009 11:16:53 -0400 Message-ID: <1241191013.15448.218.camel@chaos.ne.broadcom.com> MIME-Version: 1.0 X-Mailer: Evolution 2.12.3 (2.12.3-5.fc8) X-WSS-ID: 65E5CDED3BW7901537-01-01 Content-Type: text/plain Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22591 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jfraser@broadcom.com Precedence: bulk X-list: linux-mips On Thu, 2009-04-30 at 15:36 -0700, Luk Claes wrote: > Hi > > > | [ 0.000000] Broadcom SiByte BCM1250 B2 @ 800 MHz (SB1 rev 2) > > | [ 0.000000] Board type: SiByte BCM91250A (SWARM) > > | [ 0.000000] This kernel optimized for board runs with CFE > > | [ 0.000000] Determined physical RAM map: > > | [ 0.000000] memory: 000000000fe47e00 @ 0000000000000000 (usable) > > | [ 0.000000] Initrd not found or empty - disabling initrd > > | [ 0.000000] Zone PFN ranges: > > | [ 0.000000] DMA32 0x00000000 -> 0x00100000 > > | [ 0.000000] Normal 0x00100000 -> 0x00100000 > > | [ 0.000000] Movable zone start PFN for each node > > | [ 0.000000] early_node_map[1] active PFN ranges > > | [ 0.000000] 0: 0x00000000 -> 0x0000fe47 > > | [ 0.000000] Detected 1 available secondary CPU(s) > > | [ 0.000000] Built 1 zonelists in Zone order, mobility grouping > on. Total > > pages: 64205 > > | [ 0.000000] Kernel command line: root=/dev/hdc1 console=duart0 > > | [ 0.000000] Primary instruction cache 32kB, VIVT, 4-way, > linesize 32 bytes. > > | [ 0.000000] Primary data cache 32kB, 4-way, PIPT, no aliases, > linesize 32 > > bytes > > | [ 0.000000] PID hash table entries: 1024 (order: 10, 8192 bytes) > > > > And then it hangs... > > The zeros look like there are no timing interrupts happening. It's a > pity we don't have hardware to test which kernel version introduced the > bug (for instance with git-bisect and reboots). > > Cheers > > Luk > Try turning off SMP. I have a 1480 (big sur) board. I just tried 2.6.28.9. This is 32 bit, little endian mode. With SMP turned on, it hung in the same place. With SMP turned off, it booted fine. Jon Fraser Broadcom > From cl@linux.com Fri May 1 16:33:00 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 01 May 2009 16:33:07 +0100 (BST) Received: from smtp.ultrahosting.com ([74.213.174.254]:50826 "EHLO smtp.ultrahosting.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S28574169AbZEAPdA (ORCPT ); Fri, 1 May 2009 16:33:00 +0100 Received: from localhost (smtp.ultrahosting.com [127.0.0.1]) by smtp.ultrahosting.com (Postfix) with ESMTP id AAAE282C2F8; Fri, 1 May 2009 11:44:23 -0400 (EDT) X-Virus-Scanned: amavisd-new at ultrahosting.com Received: from smtp.ultrahosting.com ([74.213.174.254]) by localhost (smtp.ultrahosting.com [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id MItjYErjRLqR; Fri, 1 May 2009 11:44:23 -0400 (EDT) Received: from qirst.com (unknown [74.213.171.31]) by smtp.ultrahosting.com (Postfix) with ESMTP id 7F54982C51E; Fri, 1 May 2009 11:43:57 -0400 (EDT) Received: from cl (helo=localhost) by qirst.com with local-esmtp (Exim 4.69) (envelope-from ) id 1LztA2-0003YL-MS; Fri, 01 May 2009 09:52:18 -0400 Date: Fri, 1 May 2009 09:52:18 -0400 (EDT) From: Christoph Lameter X-X-Sender: cl@qirst.com To: Sam Ravnborg cc: Tim Abbott , Anders Kaseorg , Waseem Daher , Denys Vlasenko , Jeff Arnold , Benjamin Herrenschmidt , Bryan Wu , Chris Zankel , Cyrill Gorcunov , David Howells , "David S. Miller" , dev-etrax@axis.com, Geert Uytterhoeven , Greg Ungerer , Haavard Skinnemoen , Heiko Carstens , Helge Deller , Hirokazu Takata , "H. Peter Anvin" , Ingo Molnar , Jeff Dike , Jesper Nilsson , Kyle McMartin , Linus Torvalds , linux-alpha@vger.kernel.org, linux-am33-list@redhat.com, linux-arm-kernel@lists.arm.linux.org.uk, linux-ia64@vger.kernel.org, linux-m32r@ml.linux-m32r.org, linux-m68k@vger.kernel.org, linux-mips@linux-mips.org, linux-parisc@vger.kernel.org, linuxppc-dev@ozlabs.org, linux-s390@vger.kernel.org, linux-sh@vger.kernel.org, Martin Schwidefsky , Michal Simek , microblaze-uclinux@itee.uq.edu.au, Mikael Starvik , Paul Mackerras , Paul Mundt , Ralf Baechle , Richard Henderson , Roman Zippel , Russell King , sparclinux@vger.kernel.org, Thomas Gleixner , Tony Luck , uclinux-dist-devel@blackfin.uclinux.org, user-mode-linux-devel@lists.sourceforge.net, Yoshinori Sato Subject: Re: [PATCH 6/6] Add support for __read_mostly to linux/cache.h In-Reply-To: <20090501094407.GD18326@uranus.ravnborg.org> Message-ID: References: <1241119956-31453-1-git-send-email-tabbott@mit.edu> <1241119956-31453-2-git-send-email-tabbott@mit.edu> <1241119956-31453-3-git-send-email-tabbott@mit.edu> <1241119956-31453-4-git-send-email-tabbott@mit.edu> <1241119956-31453-5-git-send-email-tabbott@mit.edu> <1241119956-31453-6-git-send-email-tabbott@mit.edu> <1241119956-31453-7-git-send-email-tabbott@mit.edu> <20090501094407.GD18326@uranus.ravnborg.org> User-Agent: Alpine 1.10 (DEB 962 2008-03-14) MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22592 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: cl@linux.com Precedence: bulk X-list: linux-mips On Fri, 1 May 2009, Sam Ravnborg wrote: > Are there any specific reason why we do not support read_mostly on all > architectures? Not that I know of. > read_mostly is about grouping rarely written data together > so what is needed is to introduce this section in the remaining > archtectures. > > Christoph - git log says you did the inital implmentation. > Do you agree? Yes. There is some concern that __read_mostly is needlessly applied to numerous variables that are not used in hot code paths. This may make __read_mostly ineffective and actually increase the cache footprint of a function since global variables are no longer in the same cacheline. If such a function is called and the caches are cold then two cacheline fetches have to be done instead of one. From hpa@zytor.com Fri May 1 18:01:35 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 01 May 2009 18:01:41 +0100 (BST) Received: from terminus.zytor.com ([198.137.202.10]:59971 "EHLO terminus.zytor.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20027061AbZEARBf (ORCPT ); Fri, 1 May 2009 18:01:35 +0100 Received: from mail.hos.anvin.org (c-98-210-181-100.hsd1.ca.comcast.net [98.210.181.100]) (authenticated bits=0) by terminus.zytor.com (8.14.3/8.14.1) with ESMTP id n41GXTOq020302 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Fri, 1 May 2009 09:33:29 -0700 Received: from tazenda.hos.anvin.org (tazenda.hos.anvin.org [172.27.0.16]) by mail.hos.anvin.org (8.14.2/8.13.8) with ESMTP id n41GXS9r009009; Fri, 1 May 2009 09:33:28 -0700 Received: from tazenda.hos.anvin.org (localhost.localdomain [127.0.0.1]) by tazenda.hos.anvin.org (8.14.3/8.13.6) with ESMTP id n41GXD72013573; Fri, 1 May 2009 09:33:13 -0700 Message-ID: <49FB2449.1010301@zytor.com> Date: Fri, 01 May 2009 09:33:13 -0700 From: "H. Peter Anvin" User-Agent: Thunderbird 2.0.0.14 (X11/20080501) MIME-Version: 1.0 To: Tim Abbott CC: Sam Ravnborg , Linux kernel mailing list , Anders Kaseorg , Waseem Daher , Denys Vlasenko , Jeff Arnold , Benjamin Herrenschmidt , Bryan Wu , Chris Zankel , Cyrill Gorcunov , David Howells , "David S. Miller" , dev-etrax@axis.com, Geert Uytterhoeven , Greg Ungerer , Haavard Skinnemoen , Heiko Carstens , Helge Deller , Hirokazu Takata , Ingo Molnar , Jeff Dike , Jesper Nilsson , Kyle McMartin , Linus Torvalds , linux-alpha@vger.kernel.org, linux-ia64@vger.kernel.org, linux-m68k@vger.kernel.org, linux-mips@linux-mips.org, linux-parisc@vger.kernel.org, linuxppc-dev@ozlabs.org, linux-s390@vger.kernel.org, linux-sh@vger.kernel.org, Martin Schwidefsky , Michal Simek , microblaze-uclinux@itee.uq.edu.au, Mikael Starvik , Paul Mackerras , Paul Mundt , Ralf Baechle , Richard Henderson , Roman Zippel , Russell King , sparclinux@vger.kernel.org, Thomas Gleixner , Tony Luck , uclinux-dist-devel@blackfin.uclinux.org, user-mode-linux-devel@lists.sourceforge.net, Yoshinori Sato Subject: Re: [PATCH v2 1/6] Add new macros for page-aligned data and bss sections. References: <1241121253-32341-1-git-send-email-tabbott@mit.edu> <1241121253-32341-2-git-send-email-tabbott@mit.edu> <20090501091848.GB18326@uranus.ravnborg.org> In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Virus-Scanned: ClamAV 0.94.2/9309/Thu Apr 30 20:55:03 2009 on terminus.zytor.com X-Virus-Status: Clean Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22593 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hpa@zytor.com Precedence: bulk X-list: linux-mips Tim Abbott wrote: > On Fri, 1 May 2009, Sam Ravnborg wrote: > >> On Thu, Apr 30, 2009 at 03:54:08PM -0400, Tim Abbott wrote: >>> +#define __PAGE_ALIGNED_DATA .section ".data.page_aligned", "aw", @progbits >>> +#define __PAGE_ALIGNED_BSS .section ".bss.page_aligned", "aw", @nobits >> It is my understanding that the linker will automatically >> assume nobits for section names starting with .bss and likewise >> progbits for section names starting with .data - so we can leave them out? > > I believe that is correct. > ... but that doesn't mean it's the right thing to do. It's better to be fully explicit when macroizing this kind of stuff. This is part of why macroizing it is good: it means we end up with *one* place that determines this stuff, not some magic heuristics in the linker. -hpa -- H. Peter Anvin, Intel Open Source Technology Center I work for Intel. I don't speak on their behalf. From sam@ravnborg.org Fri May 1 18:15:14 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 01 May 2009 18:15:21 +0100 (BST) Received: from pfepb.post.tele.dk ([195.41.46.236]:56469 "EHLO pfepb.post.tele.dk" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20027138AbZEARPO (ORCPT ); Fri, 1 May 2009 18:15:14 +0100 Received: from ravnborg.org (x1-6-00-1e-2a-84-ae-3e.k225.webspeed.dk [80.163.61.94]) by pfepb.post.tele.dk (Postfix) with ESMTP id 1166AF8404F; Fri, 1 May 2009 19:15:06 +0200 (CEST) Received: by ravnborg.org (Postfix, from userid 500) id 4C36F580D0; Fri, 1 May 2009 19:17:17 +0200 (CEST) Date: Fri, 1 May 2009 19:17:17 +0200 From: Sam Ravnborg To: "H. Peter Anvin" Cc: Tim Abbott , Linux kernel mailing list , Anders Kaseorg , Waseem Daher , Denys Vlasenko , Jeff Arnold , Benjamin Herrenschmidt , Bryan Wu , Chris Zankel , Cyrill Gorcunov , David Howells , "David S. Miller" , dev-etrax@axis.com, Geert Uytterhoeven , Greg Ungerer , Haavard Skinnemoen , Heiko Carstens , Helge Deller , Hirokazu Takata , Ingo Molnar , Jeff Dike , Jesper Nilsson , Kyle McMartin , Linus Torvalds , linux-alpha@vger.kernel.org, linux-ia64@vger.kernel.org, linux-m68k@vger.kernel.org, linux-mips@linux-mips.org, linux-parisc@vger.kernel.org, linuxppc-dev@ozlabs.org, linux-s390@vger.kernel.org, linux-sh@vger.kernel.org, Martin Schwidefsky , Michal Simek , microblaze-uclinux@itee.uq.edu.au, Mikael Starvik , Paul Mackerras , Paul Mundt , Ralf Baechle , Richard Henderson , Roman Zippel , Russell King , sparclinux@vger.kernel.org, Thomas Gleixner , Tony Luck , uclinux-dist-devel@blackfin.uclinux.org, user-mode-linux-devel@lists.sourceforge.net, Yoshinori Sato Subject: Re: [PATCH v2 1/6] Add new macros for page-aligned data and bss sections. Message-ID: <20090501171717.GA26401@uranus.ravnborg.org> References: <1241121253-32341-1-git-send-email-tabbott@mit.edu> <1241121253-32341-2-git-send-email-tabbott@mit.edu> <20090501091848.GB18326@uranus.ravnborg.org> <49FB2449.1010301@zytor.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <49FB2449.1010301@zytor.com> User-Agent: Mutt/1.4.2.1i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22594 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sam@ravnborg.org Precedence: bulk X-list: linux-mips On Fri, May 01, 2009 at 09:33:13AM -0700, H. Peter Anvin wrote: > Tim Abbott wrote: > > On Fri, 1 May 2009, Sam Ravnborg wrote: > > > >> On Thu, Apr 30, 2009 at 03:54:08PM -0400, Tim Abbott wrote: > >>> +#define __PAGE_ALIGNED_DATA .section ".data.page_aligned", "aw", @progbits > >>> +#define __PAGE_ALIGNED_BSS .section ".bss.page_aligned", "aw", @nobits > >> It is my understanding that the linker will automatically > >> assume nobits for section names starting with .bss and likewise > >> progbits for section names starting with .data - so we can leave them out? > > > > I believe that is correct. > > > > ... but that doesn't mean it's the right thing to do. > > It's better to be fully explicit when macroizing this kind of stuff. > This is part of why macroizing it is good: it means we end up with *one* > place that determines this stuff, not some magic heuristics in the linker. Do you know if we can use % in place of @? I could see that gas supports both - at least in trunk in cvs. Sam From hpa@zytor.com Fri May 1 18:29:51 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 01 May 2009 18:29:58 +0100 (BST) Received: from terminus.zytor.com ([198.137.202.10]:43449 "EHLO terminus.zytor.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20027183AbZEAR3v (ORCPT ); Fri, 1 May 2009 18:29:51 +0100 Received: from mail.hos.anvin.org (c-98-210-181-100.hsd1.ca.comcast.net [98.210.181.100]) (authenticated bits=0) by terminus.zytor.com (8.14.3/8.14.1) with ESMTP id n41HIPSU028658 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Fri, 1 May 2009 10:18:25 -0700 Received: from tazenda.hos.anvin.org (tazenda.hos.anvin.org [172.27.0.16]) by mail.hos.anvin.org (8.14.2/8.13.8) with ESMTP id n41HIOqU009097; Fri, 1 May 2009 10:18:24 -0700 Received: from tazenda.hos.anvin.org (localhost.localdomain [127.0.0.1]) by tazenda.hos.anvin.org (8.14.3/8.13.6) with ESMTP id n41HIK58014054; Fri, 1 May 2009 10:18:22 -0700 Message-ID: <49FB2EDC.9050300@zytor.com> Date: Fri, 01 May 2009 10:18:20 -0700 From: "H. Peter Anvin" User-Agent: Thunderbird 2.0.0.14 (X11/20080501) MIME-Version: 1.0 To: Sam Ravnborg CC: Tim Abbott , Linux kernel mailing list , Anders Kaseorg , Waseem Daher , Denys Vlasenko , Jeff Arnold , Benjamin Herrenschmidt , Bryan Wu , Chris Zankel , Cyrill Gorcunov , David Howells , "David S. Miller" , dev-etrax@axis.com, Geert Uytterhoeven , Greg Ungerer , Haavard Skinnemoen , Heiko Carstens , Helge Deller , Hirokazu Takata , Ingo Molnar , Jeff Dike , Jesper Nilsson , Kyle McMartin , Linus Torvalds , linux-alpha@vger.kernel.org, linux-ia64@vger.kernel.org, linux-m68k@vger.kernel.org, linux-mips@linux-mips.org, linux-parisc@vger.kernel.org, linuxppc-dev@ozlabs.org, linux-s390@vger.kernel.org, linux-sh@vger.kernel.org, Martin Schwidefsky , Michal Simek , microblaze-uclinux@itee.uq.edu.au, Mikael Starvik , Paul Mackerras , Paul Mundt , Ralf Baechle , Richard Henderson , Roman Zippel , Russell King , sparclinux@vger.kernel.org, Thomas Gleixner , Tony Luck , uclinux-dist-devel@blackfin.uclinux.org, user-mode-linux-devel@lists.sourceforge.net, Yoshinori Sato Subject: Re: [PATCH v2 1/6] Add new macros for page-aligned data and bss sections. References: <1241121253-32341-1-git-send-email-tabbott@mit.edu> <1241121253-32341-2-git-send-email-tabbott@mit.edu> <20090501091848.GB18326@uranus.ravnborg.org> <49FB2449.1010301@zytor.com> <20090501171717.GA26401@uranus.ravnborg.org> In-Reply-To: <20090501171717.GA26401@uranus.ravnborg.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Virus-Scanned: ClamAV 0.94.2/9309/Thu Apr 30 20:55:03 2009 on terminus.zytor.com X-Virus-Status: Clean Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22595 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hpa@zytor.com Precedence: bulk X-list: linux-mips Sam Ravnborg wrote: > On Fri, May 01, 2009 at 09:33:13AM -0700, H. Peter Anvin wrote: >> Tim Abbott wrote: >>> On Fri, 1 May 2009, Sam Ravnborg wrote: >>> >>>> On Thu, Apr 30, 2009 at 03:54:08PM -0400, Tim Abbott wrote: >>>>> +#define __PAGE_ALIGNED_DATA .section ".data.page_aligned", "aw", @progbits >>>>> +#define __PAGE_ALIGNED_BSS .section ".bss.page_aligned", "aw", @nobits >>>> It is my understanding that the linker will automatically >>>> assume nobits for section names starting with .bss and likewise >>>> progbits for section names starting with .data - so we can leave them out? >>> I believe that is correct. >>> >> ... but that doesn't mean it's the right thing to do. >> >> It's better to be fully explicit when macroizing this kind of stuff. >> This is part of why macroizing it is good: it means we end up with *one* >> place that determines this stuff, not some magic heuristics in the linker. > > Do you know if we can use % in place of @? > I could see that gas supports both - at least in trunk in cvs. > I think it might depend on the architecture(!)... but it would definitely have to be an issue with testing a bunch of different versions. What's wrong with @? -hpa -- H. Peter Anvin, Intel Open Source Technology Center I work for Intel. I don't speak on their behalf. From sam@ravnborg.org Fri May 1 18:42:51 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 01 May 2009 18:42:58 +0100 (BST) Received: from pfepb.post.tele.dk ([195.41.46.236]:46599 "EHLO pfepb.post.tele.dk" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20027248AbZEARmv (ORCPT ); Fri, 1 May 2009 18:42:51 +0100 Received: from ravnborg.org (x1-6-00-1e-2a-84-ae-3e.k225.webspeed.dk [80.163.61.94]) by pfepb.post.tele.dk (Postfix) with ESMTP id DAE74F8404D; Fri, 1 May 2009 19:42:47 +0200 (CEST) Received: by ravnborg.org (Postfix, from userid 500) id 09233580D0; Fri, 1 May 2009 19:44:58 +0200 (CEST) Date: Fri, 1 May 2009 19:44:57 +0200 From: Sam Ravnborg To: "H. Peter Anvin" Cc: Tim Abbott , Linux kernel mailing list , Anders Kaseorg , Waseem Daher , Denys Vlasenko , Jeff Arnold , Benjamin Herrenschmidt , Bryan Wu , Chris Zankel , Cyrill Gorcunov , David Howells , "David S. Miller" , dev-etrax@axis.com, Geert Uytterhoeven , Greg Ungerer , Haavard Skinnemoen , Heiko Carstens , Helge Deller , Hirokazu Takata , Ingo Molnar , Jeff Dike , Jesper Nilsson , Kyle McMartin , Linus Torvalds , linux-alpha@vger.kernel.org, linux-ia64@vger.kernel.org, linux-m68k@vger.kernel.org, linux-mips@linux-mips.org, linux-parisc@vger.kernel.org, linuxppc-dev@ozlabs.org, linux-s390@vger.kernel.org, linux-sh@vger.kernel.org, Martin Schwidefsky , Michal Simek , microblaze-uclinux@itee.uq.edu.au, Mikael Starvik , Paul Mackerras , Paul Mundt , Ralf Baechle , Richard Henderson , Roman Zippel , Russell King , sparclinux@vger.kernel.org, Thomas Gleixner , Tony Luck , uclinux-dist-devel@blackfin.uclinux.org, user-mode-linux-devel@lists.sourceforge.net, Yoshinori Sato Subject: Re: [PATCH v2 1/6] Add new macros for page-aligned data and bss sections. Message-ID: <20090501174457.GA26559@uranus.ravnborg.org> References: <1241121253-32341-1-git-send-email-tabbott@mit.edu> <1241121253-32341-2-git-send-email-tabbott@mit.edu> <20090501091848.GB18326@uranus.ravnborg.org> <49FB2449.1010301@zytor.com> <20090501171717.GA26401@uranus.ravnborg.org> <49FB2EDC.9050300@zytor.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <49FB2EDC.9050300@zytor.com> User-Agent: Mutt/1.4.2.1i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22596 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sam@ravnborg.org Precedence: bulk X-list: linux-mips On Fri, May 01, 2009 at 10:18:20AM -0700, H. Peter Anvin wrote: > Sam Ravnborg wrote: > > On Fri, May 01, 2009 at 09:33:13AM -0700, H. Peter Anvin wrote: > >> Tim Abbott wrote: > >>> On Fri, 1 May 2009, Sam Ravnborg wrote: > >>> > >>>> On Thu, Apr 30, 2009 at 03:54:08PM -0400, Tim Abbott wrote: > >>>>> +#define __PAGE_ALIGNED_DATA .section ".data.page_aligned", "aw", @progbits > >>>>> +#define __PAGE_ALIGNED_BSS .section ".bss.page_aligned", "aw", @nobits > >>>> It is my understanding that the linker will automatically > >>>> assume nobits for section names starting with .bss and likewise > >>>> progbits for section names starting with .data - so we can leave them out? > >>> I believe that is correct. > >>> > >> ... but that doesn't mean it's the right thing to do. > >> > >> It's better to be fully explicit when macroizing this kind of stuff. > >> This is part of why macroizing it is good: it means we end up with *one* > >> place that determines this stuff, not some magic heuristics in the linker. > > > > Do you know if we can use % in place of @? > > I could see that gas supports both - at least in trunk in cvs. > > > > I think it might depend on the architecture(!)... but it would > definitely have to be an issue with testing a bunch of different versions. > > What's wrong with @? arm does not support it :-( I recall it denote a comment in arm assembler. I could do some magic to detect the ARM case but I'm reluctant to do so. I could also ignore the arm issue for now as it is not used by arm, but that strikes me as the wrong approach. Sam From hpa@zytor.com Fri May 1 18:58:31 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 01 May 2009 18:58:37 +0100 (BST) Received: from terminus.zytor.com ([198.137.202.10]:33462 "EHLO terminus.zytor.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20021519AbZEAR6b (ORCPT ); Fri, 1 May 2009 18:58:31 +0100 Received: from mail.hos.anvin.org (c-98-210-181-100.hsd1.ca.comcast.net [98.210.181.100]) (authenticated bits=0) by terminus.zytor.com (8.14.3/8.14.1) with ESMTP id n41Hlt0g001022 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Fri, 1 May 2009 10:47:55 -0700 Received: from tazenda.hos.anvin.org (tazenda.hos.anvin.org [172.27.0.16]) by mail.hos.anvin.org (8.14.2/8.13.8) with ESMTP id n41Hlt87009137; Fri, 1 May 2009 10:47:55 -0700 Received: from tazenda.hos.anvin.org (localhost.localdomain [127.0.0.1]) by tazenda.hos.anvin.org (8.14.3/8.13.6) with ESMTP id n41HlmKI014417; Fri, 1 May 2009 10:47:49 -0700 Message-ID: <49FB35C4.6060107@zytor.com> Date: Fri, 01 May 2009 10:47:48 -0700 From: "H. Peter Anvin" User-Agent: Thunderbird 2.0.0.14 (X11/20080501) MIME-Version: 1.0 To: Sam Ravnborg CC: Tim Abbott , Linux kernel mailing list , Anders Kaseorg , Waseem Daher , Denys Vlasenko , Jeff Arnold , Benjamin Herrenschmidt , Bryan Wu , Chris Zankel , Cyrill Gorcunov , David Howells , "David S. Miller" , dev-etrax@axis.com, Geert Uytterhoeven , Greg Ungerer , Haavard Skinnemoen , Heiko Carstens , Helge Deller , Hirokazu Takata , Ingo Molnar , Jeff Dike , Jesper Nilsson , Kyle McMartin , Linus Torvalds , linux-alpha@vger.kernel.org, linux-ia64@vger.kernel.org, linux-m68k@vger.kernel.org, linux-mips@linux-mips.org, linux-parisc@vger.kernel.org, linuxppc-dev@ozlabs.org, linux-s390@vger.kernel.org, linux-sh@vger.kernel.org, Martin Schwidefsky , Michal Simek , microblaze-uclinux@itee.uq.edu.au, Mikael Starvik , Paul Mackerras , Paul Mundt , Ralf Baechle , Richard Henderson , Roman Zippel , Russell King , sparclinux@vger.kernel.org, Thomas Gleixner , Tony Luck , uclinux-dist-devel@blackfin.uclinux.org, user-mode-linux-devel@lists.sourceforge.net, Yoshinori Sato Subject: Re: [PATCH v2 1/6] Add new macros for page-aligned data and bss sections. References: <1241121253-32341-1-git-send-email-tabbott@mit.edu> <1241121253-32341-2-git-send-email-tabbott@mit.edu> <20090501091848.GB18326@uranus.ravnborg.org> <49FB2449.1010301@zytor.com> <20090501171717.GA26401@uranus.ravnborg.org> <49FB2EDC.9050300@zytor.com> <20090501174457.GA26559@uranus.ravnborg.org> In-Reply-To: <20090501174457.GA26559@uranus.ravnborg.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Virus-Scanned: ClamAV 0.94.2/9309/Thu Apr 30 20:55:03 2009 on terminus.zytor.com X-Virus-Status: Clean Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22597 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: hpa@zytor.com Precedence: bulk X-list: linux-mips Sam Ravnborg wrote: >> >> What's wrong with @? > arm does not support it :-( > I recall it denote a comment in arm assembler. > > I could do some magic to detect the ARM case but I'm reluctant to do so. > I could also ignore the arm issue for now as it is not used by arm, > but that strikes me as the wrong approach. > If we really have to use different tokens, I would say: #ifdef __ARM__ # define _PROGBITS %progbits /* or whatever */ # define _NOBITS %nobits #else # define _PROGBITS @progbits # define _NOBITS @nobits #endif Otherwise we probably need to ask the binutils people... -hpa -- H. Peter Anvin, Intel Open Source Technology Center I work for Intel. I don't speak on their behalf. From edgar.iglesias@gmail.com Fri May 1 22:47:28 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 01 May 2009 22:47:35 +0100 (BST) Received: from mail-bw0-f177.google.com ([209.85.218.177]:56394 "EHLO mail-bw0-f177.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20027867AbZEAVr2 (ORCPT ); Fri, 1 May 2009 22:47:28 +0100 Received: by bwz25 with SMTP id 25so2655882bwz.0 for ; Fri, 01 May 2009 14:47:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:received:date:from:to:cc :subject:message-id:references:mime-version:content-type :content-disposition:in-reply-to:user-agent; bh=mng4vw6dm21qh7/q+QJctc3NV+qYTC1IRY7MqV61E1U=; b=yBhjkmWl83f7r+hD4ofFb3pGwHcUU/Rw8QFdmScKLpm4U4JnEiUC5QRpAZ3DO9iTsY FeIat+TiehhbxDJdQJ/8GsRMR3f2fqLUqaiOC9A9PFgCUVLOSDXxqzx5Q0AC7FdRgDIB y4ZRBrHTKPsXMwEjTCbPD7S/yEmR3zDWjPae0= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=date:from:to:cc:subject:message-id:references:mime-version :content-type:content-disposition:in-reply-to:user-agent; b=IaXKigzjNJmm/l6CdDsX1aytbuDHM/BA52TPzXQC4HWXmLGDqD0NdT3qPNgDO2WtBB 5HdwBiXncwZy/foVhIUgYzpMhY7wzdZJpgHaJ4RMi6/A6aletBE/QnK2BcYr1Ogfl0Ks uGE64q2Ltz1wdIGipZExqsVIovu0Sq0yUNf4o= Received: by 10.204.53.143 with SMTP id m15mr2983774bkg.119.1241214438233; Fri, 01 May 2009 14:47:18 -0700 (PDT) Received: from edgar.iglesias@gmail.com (c83-249-210-227.bredband.comhem.se [83.249.210.227]) by mx.google.com with ESMTPS id g28sm5040063fkg.5.2009.05.01.14.47.13 (version=TLSv1/SSLv3 cipher=RC4-MD5); Fri, 01 May 2009 14:47:17 -0700 (PDT) Received: by edgar.iglesias@gmail.com (sSMTP sendmail emulation); Fri, 01 May 2009 23:47:13 +0200 Date: Fri, 1 May 2009 23:47:13 +0200 From: "Edgar E. Iglesias" To: Christoph Lameter Cc: Sam Ravnborg , Tim Abbott , Anders Kaseorg , Waseem Daher , Denys Vlasenko , Jeff Arnold , Benjamin Herrenschmidt , Bryan Wu , Chris Zankel , Cyrill Gorcunov , David Howells , "David S. Miller" , dev-etrax@axis.com, Geert Uytterhoeven , Greg Ungerer , Haavard Skinnemoen , Heiko Carstens , Helge Deller , Hirokazu Takata , "H. Peter Anvin" , Ingo Molnar , Jeff Dike , Jesper Nilsson , Kyle McMartin , Linus Torvalds , linux-alpha@vger.kernel.org, linux-am33-list@redhat.com, linux-arm-kernel@lists.arm.linux.org.uk, linux-ia64@vger.kernel.org, linux-m32r@ml.linux-m32r.org, linux-m68k@vger.kernel.org, linux-mips@linux-mips.org, linux-parisc@vger.kernel.org, linuxppc-dev@ozlabs.org, linux-s390@vger.kernel.org, linux-sh@vger.kernel.org, Martin Schwidefsky , Michal Simek , microblaze-uclinux@itee.uq.edu.au, Mikael Starvik , Paul Mackerras , Paul Mundt , Ralf Baechle , Richard Henderson , Roman Zippel , Russell King , sparclinux@vger.kernel.org, Thomas Gleixner , Tony Luck , uclinux-dist-devel@blackfin.uclinux.org, user-mode-linux-devel@lists.sourceforge.net, Yoshinori Sato Subject: Re: [microblaze-uclinux] Re: [PATCH 6/6] Add support for __read_mostly to linux/cache.h Message-ID: <20090501214713.GB12724@laped.iglesias.mooo.com> References: <1241119956-31453-1-git-send-email-tabbott@mit.edu> <1241119956-31453-2-git-send-email-tabbott@mit.edu> <1241119956-31453-3-git-send-email-tabbott@mit.edu> <1241119956-31453-4-git-send-email-tabbott@mit.edu> <1241119956-31453-5-git-send-email-tabbott@mit.edu> <1241119956-31453-6-git-send-email-tabbott@mit.edu> <1241119956-31453-7-git-send-email-tabbott@mit.edu> <20090501094407.GD18326@uranus.ravnborg.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.16 (2007-06-09) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22598 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: edgar.iglesias@gmail.com Precedence: bulk X-list: linux-mips On Fri, May 01, 2009 at 09:52:18AM -0400, Christoph Lameter wrote: > On Fri, 1 May 2009, Sam Ravnborg wrote: > > > Are there any specific reason why we do not support read_mostly on all > > architectures? > > Not that I know of. > > > read_mostly is about grouping rarely written data together > > so what is needed is to introduce this section in the remaining > > archtectures. > > > > Christoph - git log says you did the inital implmentation. > > Do you agree? > > Yes. > > There is some concern that __read_mostly is needlessly applied to > numerous variables that are not used in hot code paths. This may make > __read_mostly ineffective and actually increase the cache footprint of a > function since global variables are no longer in the same cacheline. If > such a function is called and the caches are cold then two cacheline > fetches have to be done instead of one. FWIW I think that's a valid concern. Also, I think one can question the value of __read_mostly for write-through caches, given the mentioned concern it probably makes things worse for those. IMO there should be a way to turn it off for arch's that know it's no good for them. Cheers From whitebox@nefkom.net Sat May 2 00:02:35 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 02 May 2009 00:02:42 +0100 (BST) Received: from mail-out.m-online.net ([212.18.0.9]:35618 "EHLO mail-out.m-online.net" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S28574086AbZEAXCf (ORCPT ); Sat, 2 May 2009 00:02:35 +0100 Received: from mail01.m-online.net (mail.m-online.net [192.168.3.149]) by mail-out.m-online.net (Postfix) with ESMTP id 241241C15368; Sat, 2 May 2009 01:02:15 +0200 (CEST) Received: from localhost (dynscan2.mnet-online.de [192.168.1.215]) by mail.m-online.net (Postfix) with ESMTP id 8B89E90197; Sat, 2 May 2009 01:02:15 +0200 (CEST) X-Virus-Scanned: amavisd-new at mnet-online.de Received: from mail.mnet-online.de ([192.168.3.149]) by localhost (dynscan2.mnet-online.de [192.168.1.215]) (amavisd-new, port 10024) with ESMTP id J5MY1fAE9fML; Sat, 2 May 2009 01:02:13 +0200 (CEST) Received: from igel.home (DSL01.83.171.176.91.ip-pool.NEFkom.net [83.171.176.91]) by mail.mnet-online.de (Postfix) with ESMTP; Sat, 2 May 2009 01:02:13 +0200 (CEST) Received: by igel.home (Postfix, from userid 501) id E9F0B10DA5D; Sat, 2 May 2009 01:02:12 +0200 (CEST) From: Andreas Schwab To: "H. Peter Anvin" Cc: Sam Ravnborg , linux-mips@linux-mips.org, linux-m68k@vger.kernel.org, linux-ia64@vger.kernel.org, linux-sh@vger.kernel.org, Denys Vlasenko , Tim Abbott , Heiko Carstens , linuxppc-dev@ozlabs.org, Paul Mackerras , Greg Ungerer , sparclinux@vger.kernel.org, Thomas Gleixner , linux-s390@vger.kernel.org, Jesper Nilsson , Yoshinori Sato , Helge Deller , Ingo Molnar , Geert Uytterhoeven , Russell King , user-mode-linux-devel@lists.sourceforge.net, microblaze-uclinux@itee.uq.edu.au, Jeff Dike , Jeff Arnold , dev-etrax@axis.com, Mikael Starvik , Cyrill Gorcunov , Michal Simek , Waseem Daher , Richard Henderson , Chris Zankel , Bryan Wu , Tony Luck , linux-parisc@vger.kernel.org, Haavard Skinnemoen , Hirokazu Takata , Linux kernel mailing list , Ralf Baechle , Anders Kaseorg , Kyle McMartin , Paul Mundt , linux-alpha@vger.kernel.org, Martin Schwidefsky , uclinux-dist-devel@blackfin.uclinux.org, Linus Torvalds , "David S. Miller" Subject: Re: [PATCH v2 1/6] Add new macros for page-aligned data and bss sections. References: <1241121253-32341-1-git-send-email-tabbott@mit.edu> <1241121253-32341-2-git-send-email-tabbott@mit.edu> <20090501091848.GB18326@uranus.ravnborg.org> <49FB2449.1010301@zytor.com> <20090501171717.GA26401@uranus.ravnborg.org> <49FB2EDC.9050300@zytor.com> <20090501174457.GA26559@uranus.ravnborg.org> <49FB35C4.6060107@zytor.com> X-Yow: I'm MENTALLY here.. but PHYSICALLY I'm purchasing NAUGAHYDE furniture in the' SUBURBS of PHOENIX!! Date: Sat, 02 May 2009 01:02:12 +0200 In-Reply-To: <49FB35C4.6060107@zytor.com> (H. Peter Anvin's message of "Fri, 01 May 2009 10:47:48 -0700") Message-ID: User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/23.0.93 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22599 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: schwab@linux-m68k.org Precedence: bulk X-list: linux-mips "H. Peter Anvin" writes: > Sam Ravnborg wrote: >>> >>> What's wrong with @? >> arm does not support it :-( >> I recall it denote a comment in arm assembler. >> >> I could do some magic to detect the ARM case but I'm reluctant to do so. >> I could also ignore the arm issue for now as it is not used by arm, >> but that strikes me as the wrong approach. >> > > If we really have to use different tokens, I would say: > > #ifdef __ARM__ > # define _PROGBITS %progbits /* or whatever */ > # define _NOBITS %nobits > #else > # define _PROGBITS @progbits > # define _NOBITS @nobits > #endif GAS has always supported both '@' and '%', so '%' can be used everywhere. Andreas. -- Andreas Schwab, schwab@linux-m68k.org GPG Key fingerprint = 58CA 54C7 6D53 942B 1756 01D3 44D5 214B 8276 4ED5 "And now for something completely different." From tsbogend@alpha.franken.de Sat May 2 12:01:02 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 02 May 2009 12:01:10 +0100 (BST) Received: from elvis.franken.de ([193.175.24.41]:56050 "EHLO elvis.franken.de" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20024943AbZEBLBC (ORCPT ); Sat, 2 May 2009 12:01:02 +0100 Received: from uucp (helo=solo.franken.de) by elvis.franken.de with local-bsmtp (Exim 3.36 #1) id 1M0Cxo-0004VQ-00; Sat, 02 May 2009 13:01:00 +0200 Received: by solo.franken.de (Postfix, from userid 1000) id 8B62AC2D1B; Sat, 2 May 2009 13:00:55 +0200 (CEST) From: Thomas Bogendoerfer Subject: [PATCH] MIPS: check for R5k XKPHYS bug To: linux-mips@linux-mips.org cc: ralf@linux-mips.org Message-Id: <20090502110055.8B62AC2D1B@solo.franken.de> Date: Sat, 2 May 2009 13:00:55 +0200 (CEST) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22600 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: tsbogend@alpha.franken.de Precedence: bulk X-list: linux-mips R5k CPUs have a bug, where ll access to XKPHYS addresses don't work. Check for this bug and enable workaround, if possible. Signed-off-by: Thomas Bogendoerfer --- arch/mips/kernel/cpu-bugs64.c | 36 ++++++++++++++++++++++++++++++++++++ 1 files changed, 36 insertions(+), 0 deletions(-) diff --git a/arch/mips/kernel/cpu-bugs64.c b/arch/mips/kernel/cpu-bugs64.c index 02b7713..8e55649 100644 --- a/arch/mips/kernel/cpu-bugs64.c +++ b/arch/mips/kernel/cpu-bugs64.c @@ -26,6 +26,8 @@ static char r4kwar[] __initdata = "Enable CPU_R4000_WORKAROUNDS to rectify."; static char daddiwar[] __initdata = "Enable CPU_DADDI_WORKAROUNDS to rectify."; +static char xkphysllwar[] __initdata = + "CPU has ll xkphys bug."; static inline void align_mod(const int align, const int mod) { @@ -307,10 +309,44 @@ static inline void check_daddiu(void) panic(bug64hit, !DADDI_WAR ? daddiwar : nowar); } +static u32 ll(u32 *p) +{ + u32 ret; + + asm volatile( + "ll %0, %1\n\t" + : "=&r" (ret) + : "m" (*p)); + + return ret; +} + +void __init check_ll_xkphys(void) +{ + static u32 val; + u32 *p = (u32 *)PHYS_TO_XKPHYS(K_CALG_NONCOHERENT, + CPHYSADDR((unsigned long)&val)); + + printk("Checking for the ll/lld xkphys bug... "); + memset(p, 0xff, sizeof(val)); + if (ll(p) != 0xffffffff) { + printk("yes, enabling workaround... "); + cpu_data[0].options &= ~MIPS_CPU_LLSC; + if (cpu_has_llsc != (cpu_data[0].options & MIPS_CPU_LLSC)) { + printk("failed.\n"); + panic(bug64hit, xkphysllwar); + } + printk("ok.\n"); + } else + printk("no.\n"); +} + + void __init check_bugs64_early(void) { check_mult_sh(); check_daddiu(); + check_ll_xkphys(); } void __init check_bugs64(void) From mcdonald.shane@gmail.com Sat May 2 16:40:12 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 02 May 2009 16:40:19 +0100 (BST) Received: from yx-out-1718.google.com ([74.125.44.155]:41154 "EHLO yx-out-1718.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20022625AbZEBPkM (ORCPT ); Sat, 2 May 2009 16:40:12 +0100 Received: by yx-out-1718.google.com with SMTP id 4so1734054yxp.24 for ; Sat, 02 May 2009 08:40:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:received:to:subject:cc :message-id:from:date; bh=kaP37j5AyYVyHCsKIjAFkhqvRQESyZaTJtNK+w2M92c=; b=YAZJIvyQKYer3ESN+IHRbolJVS8+FR0x/rXN3PUpt242/DHOwEk01WWybWJzd/l0aH E35EAIW9bqPkFVVpIlDwK+uNppX2qM9VNrgG3T8Y7PhYlmxFBSc4Fk+MjNPDv8bzrqkk aaDBESuIGqT/UNd/ycr8d1pTc6DzRiK2WnKeI= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=to:subject:cc:message-id:from:date; b=Whka8IURIbT/BNtNX0L07dtFN3DVmci0kVD6TCKZKCxkhCP4UTYdm3p30b7NmUEYQl ftUFmmzH1ms1n+9Cv48pj21IA7LMLOQbzG0wnvMG15JmdalA3MzS8AXmlgiqzh6lVGqO 9PiftEA7uOxFTnINI6T7/tOsMp41LYLKaPEB4= Received: by 10.100.141.10 with SMTP id o10mr8359941and.152.1241278809972; Sat, 02 May 2009 08:40:09 -0700 (PDT) Received: from localhost (207-47-250-185.sktn.hsdb.sasknet.sk.ca [207.47.250.185]) by mx.google.com with ESMTPS id d21sm6798849and.8.2009.05.02.08.40.08 (version=TLSv1/SSLv3 cipher=RC4-MD5); Sat, 02 May 2009 08:40:09 -0700 (PDT) Received: from shane by localhost with local (Exim 4.63) (envelope-from ) id 1M0HJu-0007HN-7j; Sat, 02 May 2009 09:40:06 -0600 To: linux-mtd@lists.infradead.org Subject: [PATCH] MTD: Remove pmcmsp-ramroot.c Cc: linux-mips@linux-mips.org, ralf@linux-mips.org, hch@lst.de, dwmw2@infradead.org, linux-kernel@vger.kernel.org Message-Id: From: Shane McDonald Date: Sat, 02 May 2009 09:40:06 -0600 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22601 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mcdonald.shane@gmail.com Precedence: bulk X-list: linux-mips The RAMROOT function was a successful but non-portable attempt to append the root filesystem to the end of the kernel image. The preferred and portable solution is to use an initramfs instead. The only user of this function was the msp71xx configuration in the MIPS architecture; as the use of the RAMROOT has been removed from that configuration, there are no more users, so this code can be removed. Signed-off-by: Shane McDonald --- drivers/mtd/maps/Kconfig | 9 --- drivers/mtd/maps/Makefile | 1 - drivers/mtd/maps/pmcmsp-ramroot.c | 104 ------------------------------------- 3 files changed, 0 insertions(+), 114 deletions(-) delete mode 100644 drivers/mtd/maps/pmcmsp-ramroot.c diff --git a/drivers/mtd/maps/Kconfig b/drivers/mtd/maps/Kconfig index 82923bd..2807833 100644 --- a/drivers/mtd/maps/Kconfig +++ b/drivers/mtd/maps/Kconfig @@ -105,15 +105,6 @@ config MSP_FLASH_MAP_LIMIT default "0x02000000" depends on MSP_FLASH_MAP_LIMIT_32M -config MTD_PMC_MSP_RAMROOT - tristate "Embedded RAM block device for root on PMC-Sierra MSP" - depends on PMC_MSP_EMBEDDED_ROOTFS && \ - (MTD_BLOCK || MTD_BLOCK_RO) && \ - MTD_RAM - help - This provides support for the embedded root file system - on PMC MSP devices. This memory is mapped as a MTD block device. - config MTD_SUN_UFLASH tristate "Sun Microsystems userflash support" depends on SPARC && MTD_CFI && PCI diff --git a/drivers/mtd/maps/Makefile b/drivers/mtd/maps/Makefile index 2dbc1be..8bae7f9 100644 --- a/drivers/mtd/maps/Makefile +++ b/drivers/mtd/maps/Makefile @@ -25,7 +25,6 @@ obj-$(CONFIG_MTD_OCTAGON) += octagon-5066.o obj-$(CONFIG_MTD_PHYSMAP) += physmap.o obj-$(CONFIG_MTD_PHYSMAP_OF) += physmap_of.o obj-$(CONFIG_MTD_PMC_MSP_EVM) += pmcmsp-flash.o -obj-$(CONFIG_MTD_PMC_MSP_RAMROOT)+= pmcmsp-ramroot.o obj-$(CONFIG_MTD_PCMCIA) += pcmciamtd.o obj-$(CONFIG_MTD_RPXLITE) += rpxlite.o obj-$(CONFIG_MTD_TQM8XXL) += tqm8xxl.o diff --git a/drivers/mtd/maps/pmcmsp-ramroot.c b/drivers/mtd/maps/pmcmsp-ramroot.c deleted file mode 100644 index 30de5c0..0000000 --- a/drivers/mtd/maps/pmcmsp-ramroot.c +++ /dev/null @@ -1,104 +0,0 @@ -/* - * Mapping of the rootfs in a physical region of memory - * - * Copyright (C) 2005-2007 PMC-Sierra Inc. - * Author: Andrew Hughes, Andrew_Hughes@pmc-sierra.com - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include - -#include - -static struct mtd_info *rr_mtd; - -struct map_info rr_map = { - .name = "ramroot", - .bankwidth = 4, -}; - -static int __init init_rrmap(void) -{ - void *ramroot_start; - unsigned long ramroot_size; - - /* Check for supported rootfs types */ - if (get_ramroot(&ramroot_start, &ramroot_size)) { - rr_map.phys = CPHYSADDR(ramroot_start); - rr_map.size = ramroot_size; - - printk(KERN_NOTICE - "PMC embedded root device: 0x%08lx @ 0x%08lx\n", - rr_map.size, (unsigned long)rr_map.phys); - } else { - printk(KERN_ERR - "init_rrmap: no supported embedded rootfs detected!\n"); - return -ENXIO; - } - - /* Map rootfs to I/O space for block device driver */ - rr_map.virt = ioremap(rr_map.phys, rr_map.size); - if (!rr_map.virt) { - printk(KERN_ERR "Failed to ioremap\n"); - return -EIO; - } - - simple_map_init(&rr_map); - - rr_mtd = do_map_probe("map_ram", &rr_map); - if (rr_mtd) { - rr_mtd->owner = THIS_MODULE; - - add_mtd_device(rr_mtd); - - return 0; - } - - iounmap(rr_map.virt); - return -ENXIO; -} - -static void __exit cleanup_rrmap(void) -{ - del_mtd_device(rr_mtd); - map_destroy(rr_mtd); - - iounmap(rr_map.virt); - rr_map.virt = NULL; -} - -MODULE_AUTHOR("PMC-Sierra, Inc"); -MODULE_DESCRIPTION("MTD map driver for embedded PMC-Sierra MSP filesystem"); -MODULE_LICENSE("GPL"); - -module_init(init_rrmap); -module_exit(cleanup_rrmap); -- 1.6.2.4 From geert.uytterhoeven@gmail.com Sun May 3 09:19:57 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 03 May 2009 09:20:04 +0100 (BST) Received: from ey-out-1920.google.com ([74.125.78.146]:19235 "EHLO ey-out-1920.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20023941AbZECIT5 (ORCPT ); Sun, 3 May 2009 09:19:57 +0100 Received: by ey-out-1920.google.com with SMTP id 13so703524eye.54 for ; Sun, 03 May 2009 01:19:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:sender:received:in-reply-to :references:date:x-google-sender-auth:message-id:subject:from:to:cc :content-type:content-transfer-encoding; bh=VEHYLE1/JNSkUoibEt/tDpFHXIP1sBdkJ6L/OYF1g4g=; b=rBLtnxJvev6MuUuBM8VV8/2DLozlhruxPQWZ7c1qYYif+pnj9paIEUPlx3ElhDFDE9 6w2nK9qka4WzGAUAvOwBCI0I/yiQlNJjRIMkFJg+c8jxia759loH3uCpbt98olSwn6TX +KBeVueXzk3/oy2G6C7Bm3aDou0fOhBd2UsG0= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:sender:in-reply-to:references:date :x-google-sender-auth:message-id:subject:from:to:cc:content-type :content-transfer-encoding; b=IU79kxy8AuXZpNbiCn15k5V3NtC+pgUcjkClaPGl6dXhg9A/2N6LJk9KGzA9wq6l0k w/97Ba/zxjZsQmKdg+l9ezdMab6r3fnIrHAk9qBrqwRF24k1AnnQdrzss7/G9cHmaPLi gQpciHBCriqJYOhv+fhKH6TynGUKJ+cv9VvhM= MIME-Version: 1.0 Received: by 10.210.17.2 with SMTP id 2mr4719938ebq.85.1241338796043; Sun, 03 May 2009 01:19:56 -0700 (PDT) In-Reply-To: <200904302141.53025.florian@openwrt.org> References: <200904302141.53025.florian@openwrt.org> Date: Sun, 3 May 2009 10:19:56 +0200 X-Google-Sender-Auth: 3d1e795dfca5b56d Message-ID: <10f740e80905030119u6f196b6bqe63003d502f9f731@mail.gmail.com> Subject: Re: initramfs breakage with 64-bits kernels? From: Geert Uytterhoeven To: Florian Fainelli Cc: linux-mips@linux-mips.org Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22602 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: geert@linux-m68k.org Precedence: bulk X-list: linux-mips On Thu, Apr 30, 2009 at 21:41, Florian Fainelli wrote: > I have been trying to get a 2.6.29 64-bits kernel for Cavium Octeon to work > with a 32-bits userland in an initramfs. While booting, the kernel does not > find the initramfs due to the check against initrd_start in populate_rootfs > (init/initramfs.c) failing. You mean the test for initrd_start being non-zero? Is your initramfs really at address zero? Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds From kevink@paralogos.com Sun May 3 10:24:41 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 03 May 2009 10:24:47 +0100 (BST) Received: from gateway05.websitewelcome.com ([67.18.15.4]:46469 "HELO gateway05.websitewelcome.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with SMTP id S20024084AbZECJYl (ORCPT ); Sun, 3 May 2009 10:24:41 +0100 Received: (qmail 26216 invoked from network); 3 May 2009 09:26:28 -0000 Received: from gator750.hostgator.com (174.132.194.2) by gateway05.websitewelcome.com with SMTP; 3 May 2009 09:26:28 -0000 Received: from [217.109.65.213] (port=2140 helo=[127.0.0.1]) by gator750.hostgator.com with esmtpa (Exim 4.69) (envelope-from ) id 1M0Xw3-0002qS-V6; Sun, 03 May 2009 04:24:36 -0500 Message-ID: <49FD62D5.5000803@paralogos.com> Date: Sun, 03 May 2009 11:24:37 +0200 From: "Kevin D. Kissell" User-Agent: Thunderbird 2.0.0.21 (Windows/20090302) MIME-Version: 1.0 To: Geert Uytterhoeven CC: Florian Fainelli , linux-mips@linux-mips.org Subject: Re: initramfs breakage with 64-bits kernels? References: <200904302141.53025.florian@openwrt.org> <10f740e80905030119u6f196b6bqe63003d502f9f731@mail.gmail.com> In-Reply-To: <10f740e80905030119u6f196b6bqe63003d502f9f731@mail.gmail.com> Content-Type: multipart/alternative; boundary="------------080101070409010603030905" X-AntiAbuse: This header was added to track abuse, please include it with any abuse report X-AntiAbuse: Primary Hostname - gator750.hostgator.com X-AntiAbuse: Original Domain - linux-mips.org X-AntiAbuse: Originator/Caller UID/GID - [47 12] / [47 12] X-AntiAbuse: Sender Address Domain - paralogos.com Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22603 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: kevink@paralogos.com Precedence: bulk X-list: linux-mips This is a multi-part message in MIME format. --------------080101070409010603030905 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Geert Uytterhoeven wrote: > On Thu, Apr 30, 2009 at 21:41, Florian Fainelli wrote: > >> I have been trying to get a 2.6.29 64-bits kernel for Cavium Octeon to work >> with a 32-bits userland in an initramfs. While booting, the kernel does not >> find the initramfs due to the check against initrd_start in populate_rootfs >> (init/initramfs.c) failing. >> > > You mean the test for initrd_start being non-zero? Is your initramfs really at > address zero? I'm not set up to verify this, but I have a nagging suspicion that a big-endian 64-bit kernel build could store an initrd_start address with 32 or fewer significant bits (i.e. it starts in the first 4GB) as a 64-bit pointer, but that the code in initramfs.c is testing the value as a 32-bit scalar type. I don't know about lmo but in kernel.org 2.6.29, it's declared in include/linux/initrd.h as an extern unsigned long, not a void *. Little endian builds wouldn't see such a problem. Regards, Kevin K. --------------080101070409010603030905 Content-Type: text/html; charset=UTF-8 Content-Transfer-Encoding: 8bit Geert Uytterhoeven wrote: 
On Thu, Apr 30, 2009 at 21:41, Florian Fainelli <florian@openwrt.org> wrote:
  
I have been trying to get a 2.6.29 64-bits kernel for Cavium Octeon to work
with a 32-bits userland in an initramfs. While booting, the kernel does not
find the initramfs due to the check against initrd_start in populate_rootfs
(init/initramfs.c) failing.
    

You mean the test for initrd_start being non-zero? Is your initramfs really at
address zero?
I'm not set up to verify this, but I have a nagging suspicion that a big-endian 64-bit kernel build could store an initrd_start address with 32 or fewer significant bits (i.e. it starts in the first 4GB) as a 64-bit pointer, but that the code in initramfs.c is testing the value as a 32-bit scalar type.  I don't know about lmo but in kernel.org 2.6.29, it's declared in include/linux/initrd.h as an extern unsigned long, not a void *.  Little endian builds wouldn't see such a problem.

          Regards,

          Kevin K.
--------------080101070409010603030905-- From kevink@paralogos.com Sun May 3 10:42:48 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 03 May 2009 10:42:54 +0100 (BST) Received: from gateway05.websitewelcome.com ([64.5.52.8]:56353 "HELO gateway05.websitewelcome.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with SMTP id S20024100AbZECJms (ORCPT ); Sun, 3 May 2009 10:42:48 +0100 Received: (qmail 18296 invoked from network); 3 May 2009 09:44:36 -0000 Received: from gator750.hostgator.com (174.132.194.2) by gateway05.websitewelcome.com with SMTP; 3 May 2009 09:44:36 -0000 Received: from [217.109.65.213] (port=2204 helo=[127.0.0.1]) by gator750.hostgator.com with esmtpa (Exim 4.69) (envelope-from ) id 1M0YDc-0006kw-RQ; Sun, 03 May 2009 04:42:45 -0500 Message-ID: <49FD6716.9080309@paralogos.com> Date: Sun, 03 May 2009 11:42:46 +0200 From: "Kevin D. Kissell" User-Agent: Thunderbird 2.0.0.21 (Windows/20090302) MIME-Version: 1.0 To: Geert Uytterhoeven CC: Florian Fainelli , linux-mips@linux-mips.org Subject: Re: initramfs breakage with 64-bits kernels? References: <200904302141.53025.florian@openwrt.org> <10f740e80905030119u6f196b6bqe63003d502f9f731@mail.gmail.com> <49FD62D5.5000803@paralogos.com> In-Reply-To: <49FD62D5.5000803@paralogos.com> Content-Type: multipart/alternative; boundary="------------060909060201010000060503" X-AntiAbuse: This header was added to track abuse, please include it with any abuse report X-AntiAbuse: Primary Hostname - gator750.hostgator.com X-AntiAbuse: Original Domain - linux-mips.org X-AntiAbuse: Originator/Caller UID/GID - [47 12] / [47 12] X-AntiAbuse: Sender Address Domain - paralogos.com Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22604 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: kevink@paralogos.com Precedence: bulk X-list: linux-mips This is a multi-part message in MIME format. --------------060909060201010000060503 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Kevin D. Kissell wrote: > Geert Uytterhoeven wrote: >> You mean the test for initrd_start being non-zero? Is your initramfs >> really at address zero? > I'm not set up to verify this, but I have a nagging suspicion that a > big-endian 64-bit kernel build could store an initrd_start address > with 32 or fewer significant bits (i.e. it starts in the first 4GB) as > a 64-bit pointer, but that the code in initramfs.c is testing the > value as a 32-bit scalar type. I don't know about lmo but in > kernel.org 2.6.29, it's declared in include/linux/initrd.h as an > extern unsigned long, not a void *. And yes, I know that MIPS64 builds *should* have data type equivalence for longs and pointers, but this behavior just smells like a data typing mismatch problem, at some level. Kevin K. --------------060909060201010000060503 Content-Type: text/html; charset=UTF-8 Content-Transfer-Encoding: 8bit Kevin D. Kissell wrote:
Geert Uytterhoeven wrote:
You mean the test for initrd_start being non-zero? Is your initramfs really at address zero?
I'm not set up to verify this, but I have a nagging suspicion that a big-endian 64-bit kernel build could store an initrd_start address with 32 or fewer significant bits (i.e. it starts in the first 4GB) as a 64-bit pointer, but that the code in initramfs.c is testing the value as a 32-bit scalar type.  I don't know about lmo but in kernel.org 2.6.29, it's declared in include/linux/initrd.h as an extern unsigned long, not a void *.
And yes, I know that MIPS64 builds *should* have data type equivalence for longs and pointers, but this behavior just smells like a data typing mismatch problem, at some level.

          Kevin K.
--------------060909060201010000060503-- From mano@roarinelk.homelinux.net Mon May 4 09:28:23 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 04 May 2009 09:28:30 +0100 (BST) Received: from fnoeppeil48.netpark.at ([217.175.205.176]:40865 "EHLO roarinelk.homelinux.net" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20021938AbZEDI2X (ORCPT ); Mon, 4 May 2009 09:28:23 +0100 Received: (qmail 25513 invoked by uid 1000); 4 May 2009 10:28:16 +0200 Date: Mon, 4 May 2009 10:28:16 +0200 From: Manuel Lauss To: Sam Ravnborg Cc: Anders Kaseorg , LKML , Linux-MIPS Subject: Re: Lots of unexpected non-allocatable section warnings Message-ID: <20090504082816.GA25378@roarinelk.homelinux.net> References: <20090503110517.6d09bca2@hyperion.delvare> <20090503103010.GA27978@uranus.ravnborg.org> <20090503124848.276b437f@hyperion.delvare> <20090503180332.GA31820@uranus.ravnborg.org> <20090503202939.GA1237@uranus.ravnborg.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20090503202939.GA1237@uranus.ravnborg.org> User-Agent: Mutt/1.5.16 (2007-06-09) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22605 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mano@roarinelk.homelinux.net Precedence: bulk X-list: linux-mips Hi Sam, On Sun, May 03, 2009 at 10:29:39PM +0200, Sam Ravnborg wrote: > This is due to the SUSE specific section as you expected. > We ignore sections named ".comment" but not ".comment" sections > with something appended to the name. On a related note, I see tons of the following warnings cross-building for MIPS: WARNING: init/mounts.o (.mdebug.abi32): unexpected non-allocatable section. Did you forget to use "ax"/"aw" in a .S file? Note that for example contains section definitions for use in .S files. WARNING: init/mounts.o (.pdr): unexpected non-allocatable section. Did you forget to use "ax"/"aw" in a .S file? Note that for example contains section definitions for use in .S files. I added ".pdr" and ".mdebug*" to the whitelist; the resulting kernels still work. (gcc-4.3.3, binutils-2.19.1) Thanks! Manuel Lauss From sam@ravnborg.org Mon May 4 10:47:28 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 04 May 2009 10:47:34 +0100 (BST) Received: from pfepa.post.tele.dk ([195.41.46.235]:38228 "EHLO pfepa.post.tele.dk" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20022025AbZEDJr2 (ORCPT ); Mon, 4 May 2009 10:47:28 +0100 Received: from ravnborg.org (x1-6-00-1e-2a-84-ae-3e.k225.webspeed.dk [80.163.61.94]) by pfepa.post.tele.dk (Postfix) with ESMTP id 99CF7A5008C; Mon, 4 May 2009 11:47:17 +0200 (CEST) Received: by ravnborg.org (Postfix, from userid 500) id 66656580D0; Mon, 4 May 2009 11:49:28 +0200 (CEST) Date: Mon, 4 May 2009 11:49:28 +0200 From: Sam Ravnborg To: Manuel Lauss Cc: Anders Kaseorg , LKML , Linux-MIPS Subject: Re: Lots of unexpected non-allocatable section warnings Message-ID: <20090504094928.GA6157@uranus.ravnborg.org> References: <20090503110517.6d09bca2@hyperion.delvare> <20090503103010.GA27978@uranus.ravnborg.org> <20090503124848.276b437f@hyperion.delvare> <20090503180332.GA31820@uranus.ravnborg.org> <20090503202939.GA1237@uranus.ravnborg.org> <20090504082816.GA25378@roarinelk.homelinux.net> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20090504082816.GA25378@roarinelk.homelinux.net> User-Agent: Mutt/1.4.2.1i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22606 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sam@ravnborg.org Precedence: bulk X-list: linux-mips On Mon, May 04, 2009 at 10:28:16AM +0200, Manuel Lauss wrote: > Hi Sam, > > On Sun, May 03, 2009 at 10:29:39PM +0200, Sam Ravnborg wrote: > > This is due to the SUSE specific section as you expected. > > We ignore sections named ".comment" but not ".comment" sections > > with something appended to the name. > > > On a related note, I see tons of the following warnings cross-building for > MIPS: > > WARNING: init/mounts.o (.mdebug.abi32): unexpected non-allocatable section. > Did you forget to use "ax"/"aw" in a .S file? > Note that for example contains > section definitions for use in .S files. > > WARNING: init/mounts.o (.pdr): unexpected non-allocatable section. > Did you forget to use "ax"/"aw" in a .S file? > Note that for example contains > section definitions for use in .S files. > > > I added ".pdr" and ".mdebug*" to the whitelist; the resulting kernels still > work. (gcc-4.3.3, binutils-2.19.1) Hi Manuel - thanks for reporting! Is your mips target little or big endian? If it is a big-endian target (which I expect) then the right fix is the patch posted by Anders. In other words - what happens if you back out your change and apply the appended patch. Sam From 23938116e57f8597f3cead5e1f79a51ebbbe3dd6 Mon Sep 17 00:00:00 2001 From: Anders Kaseorg Date: Sun, 3 May 2009 22:02:55 +0200 Subject: [PATCH 1/2] kbuild, modpost: fix unexpected non-allocatable section when cross compiling The missing TO_NATIVE(sechdrs[i].sh_flags) was causing many unexpected non-allocatable section warnings when cross-compiling for an architecture with a different endianness. Fix endianness of all the fields in the ELF header and section headers, not just some of them so we are not hit by this anohter time. Signed-off-by: Anders Kaseorg Reported-by: Sean MacLennan Signed-off-by: Sam Ravnborg --- scripts/mod/modpost.c | 35 +++++++++++++++++++++++------------ 1 files changed, 23 insertions(+), 12 deletions(-) diff --git a/scripts/mod/modpost.c b/scripts/mod/modpost.c index 936b6f8..a5c17db 100644 --- a/scripts/mod/modpost.c +++ b/scripts/mod/modpost.c @@ -384,11 +384,19 @@ static int parse_elf(struct elf_info *info, const char *filename) return 0; } /* Fix endianness in ELF header */ - hdr->e_shoff = TO_NATIVE(hdr->e_shoff); - hdr->e_shstrndx = TO_NATIVE(hdr->e_shstrndx); - hdr->e_shnum = TO_NATIVE(hdr->e_shnum); - hdr->e_machine = TO_NATIVE(hdr->e_machine); - hdr->e_type = TO_NATIVE(hdr->e_type); + hdr->e_type = TO_NATIVE(hdr->e_type); + hdr->e_machine = TO_NATIVE(hdr->e_machine); + hdr->e_version = TO_NATIVE(hdr->e_version); + hdr->e_entry = TO_NATIVE(hdr->e_entry); + hdr->e_phoff = TO_NATIVE(hdr->e_phoff); + hdr->e_shoff = TO_NATIVE(hdr->e_shoff); + hdr->e_flags = TO_NATIVE(hdr->e_flags); + hdr->e_ehsize = TO_NATIVE(hdr->e_ehsize); + hdr->e_phentsize = TO_NATIVE(hdr->e_phentsize); + hdr->e_phnum = TO_NATIVE(hdr->e_phnum); + hdr->e_shentsize = TO_NATIVE(hdr->e_shentsize); + hdr->e_shnum = TO_NATIVE(hdr->e_shnum); + hdr->e_shstrndx = TO_NATIVE(hdr->e_shstrndx); sechdrs = (void *)hdr + hdr->e_shoff; info->sechdrs = sechdrs; @@ -402,13 +410,16 @@ static int parse_elf(struct elf_info *info, const char *filename) /* Fix endianness in section headers */ for (i = 0; i < hdr->e_shnum; i++) { - sechdrs[i].sh_type = TO_NATIVE(sechdrs[i].sh_type); - sechdrs[i].sh_offset = TO_NATIVE(sechdrs[i].sh_offset); - sechdrs[i].sh_size = TO_NATIVE(sechdrs[i].sh_size); - sechdrs[i].sh_link = TO_NATIVE(sechdrs[i].sh_link); - sechdrs[i].sh_name = TO_NATIVE(sechdrs[i].sh_name); - sechdrs[i].sh_info = TO_NATIVE(sechdrs[i].sh_info); - sechdrs[i].sh_addr = TO_NATIVE(sechdrs[i].sh_addr); + sechdrs[i].sh_name = TO_NATIVE(sechdrs[i].sh_name); + sechdrs[i].sh_type = TO_NATIVE(sechdrs[i].sh_type); + sechdrs[i].sh_flags = TO_NATIVE(sechdrs[i].sh_flags); + sechdrs[i].sh_addr = TO_NATIVE(sechdrs[i].sh_addr); + sechdrs[i].sh_offset = TO_NATIVE(sechdrs[i].sh_offset); + sechdrs[i].sh_size = TO_NATIVE(sechdrs[i].sh_size); + sechdrs[i].sh_link = TO_NATIVE(sechdrs[i].sh_link); + sechdrs[i].sh_info = TO_NATIVE(sechdrs[i].sh_info); + sechdrs[i].sh_addralign = TO_NATIVE(sechdrs[i].sh_addralign); + sechdrs[i].sh_entsize = TO_NATIVE(sechdrs[i].sh_entsize); } /* Find symbol table. */ for (i = 1; i < hdr->e_shnum; i++) { -- 1.6.3.rc3.40.g75b44 From mano@roarinelk.homelinux.net Mon May 4 11:05:43 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 04 May 2009 11:05:50 +0100 (BST) Received: from fnoeppeil48.netpark.at ([217.175.205.176]:41674 "EHLO roarinelk.homelinux.net" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20022035AbZEDKFn (ORCPT ); Mon, 4 May 2009 11:05:43 +0100 Received: (qmail 26180 invoked by uid 1000); 4 May 2009 12:05:42 +0200 Date: Mon, 4 May 2009 12:05:42 +0200 From: Manuel Lauss To: Sam Ravnborg Cc: Anders Kaseorg , LKML , Linux-MIPS Subject: Re: Lots of unexpected non-allocatable section warnings Message-ID: <20090504100542.GA26150@roarinelk.homelinux.net> References: <20090503110517.6d09bca2@hyperion.delvare> <20090503103010.GA27978@uranus.ravnborg.org> <20090503124848.276b437f@hyperion.delvare> <20090503180332.GA31820@uranus.ravnborg.org> <20090503202939.GA1237@uranus.ravnborg.org> <20090504082816.GA25378@roarinelk.homelinux.net> <20090504094928.GA6157@uranus.ravnborg.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20090504094928.GA6157@uranus.ravnborg.org> User-Agent: Mutt/1.5.16 (2007-06-09) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22608 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mano@roarinelk.homelinux.net Precedence: bulk X-list: linux-mips Content-Length: 1683 Lines: 48 Hi Sam, On Mon, May 04, 2009 at 11:49:28AM +0200, Sam Ravnborg wrote: > On Mon, May 04, 2009 at 10:28:16AM +0200, Manuel Lauss wrote: > > Hi Sam, > > > > On Sun, May 03, 2009 at 10:29:39PM +0200, Sam Ravnborg wrote: > > > This is due to the SUSE specific section as you expected. > > > We ignore sections named ".comment" but not ".comment" sections > > > with something appended to the name. > > > > > > On a related note, I see tons of the following warnings cross-building for > > MIPS: > > > > WARNING: init/mounts.o (.mdebug.abi32): unexpected non-allocatable section. > > Did you forget to use "ax"/"aw" in a .S file? > > Note that for example contains > > section definitions for use in .S files. > > > > WARNING: init/mounts.o (.pdr): unexpected non-allocatable section. > > Did you forget to use "ax"/"aw" in a .S file? > > Note that for example contains > > section definitions for use in .S files. > > > > > > I added ".pdr" and ".mdebug*" to the whitelist; the resulting kernels still > > work. (gcc-4.3.3, binutils-2.19.1) > > Hi Manuel - thanks for reporting! > > Is your mips target little or big endian? > If it is a big-endian target (which I expect) then the right fix > is the patch posted by Anders. No, it's little-endian. Cross-compiling on x86_64 to mipsel. > In other words - what happens if you back out your change > and apply the appended patch. no change. (Did you attach the wrong patch? It does indentation fixes and adds a few more entries) Thanks! Manuel Lauss From jfraser@broadcom.com Mon May 4 15:50:03 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 04 May 2009 15:50:10 +0100 (BST) Received: from mms2.broadcom.com ([216.31.210.18]:3895 "EHLO mms2.broadcom.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20022537AbZEDOuD (ORCPT ); Mon, 4 May 2009 15:50:03 +0100 Received: from [10.9.200.131] by mms2.broadcom.com with ESMTP (Broadcom SMTP Relay (Email Firewall v6.3.2)); Mon, 04 May 2009 07:49:48 -0700 X-Server-Uuid: D3C04415-6FA8-4F2C-93C1-920E106A2031 Received: from mail-irva-13.broadcom.com (10.11.16.103) by IRVEXCHHUB01.corp.ad.broadcom.com (10.9.200.131) with Microsoft SMTP Server id 8.1.358.0; Mon, 4 May 2009 07:49:48 -0700 Received: from [10.28.6.13] (lab-mhtb-013.ne.broadcom.com [10.28.6.13]) by mail-irva-13.broadcom.com (Postfix) with ESMTP id 9F5EB74D04; Mon, 4 May 2009 07:49:47 -0700 (PDT) Subject: Re: HIGHMEM fix for r24k From: "Jon Fraser" Reply-to: jfraser@broadcom.com To: "Ralf Baechle" cc: jfraser@broadcom.com, "linux-mips@linux-mips.org" In-Reply-To: <20090425092446.GA9845@linux-mips.org> References: <1240525424.15448.33.camel@chaos.ne.broadcom.com> <20090424154349.GB3614@linux-mips.org> <1240589632.15448.38.camel@chaos.ne.broadcom.com> <20090425092446.GA9845@linux-mips.org> Organization: Broadcom Date: Mon, 4 May 2009 10:49:46 -0400 Message-ID: <1241448586.15448.249.camel@chaos.ne.broadcom.com> MIME-Version: 1.0 X-Mailer: Evolution 2.12.3 (2.12.3-5.fc8) X-WSS-ID: 65E1DF063BO10324328-01-01 Content-Type: text/plain Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22609 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jfraser@broadcom.com Precedence: bulk X-list: linux-mips Content-Length: 5653 Lines: 194 Hi Ralf, Just wanted to acknowledge your email. I've been playing catch up for the last week after spending a large amount of unscheduled time finding the root cause of this bug. I should be able to get to applying this patch this week. Were these against HOT or 2.6.29? Jon On Sat, 2009-04-25 at 02:24 -0700, Ralf Baechle wrote: > On Fri, Apr 24, 2009 at 12:13:52PM -0400, Jon Fraser wrote: > > > That's why I haven't proposed a fix yet. But there are other people > > dealing with the same HIGHMEM issues and I wanted them to know about the > > problem. > > Can you test below fix? Thanks, > > Ralf > > Signed-off-by: Ralf Baechle > > arch/mips/include/asm/fixmap.h | 3 +++ > arch/mips/include/asm/highmem.h | 6 ++++-- > arch/mips/mm/highmem.c | 25 +++++++++++++++++++------ > arch/mips/mm/init.c | 26 -------------------------- > 4 files changed, 26 insertions(+), 34 deletions(-) > > diff --git a/arch/mips/include/asm/fixmap.h b/arch/mips/include/asm/fixmap.h > index 9cc8522..0f5caa1 100644 > --- a/arch/mips/include/asm/fixmap.h > +++ b/arch/mips/include/asm/fixmap.h > @@ -108,6 +108,9 @@ static inline unsigned long virt_to_fix(const unsigned long vaddr) > return __virt_to_fix(vaddr); > } > > +#define kmap_get_fixmap_pte(vaddr) \ > + pte_offset_kernel(pmd_offset(pud_offset(pgd_offset_k(vaddr), (vaddr)), (vaddr)), (vaddr)) > + > /* > * Called from pgtable_init() > */ > diff --git a/arch/mips/include/asm/highmem.h b/arch/mips/include/asm/highmem.h > index 4374ab2..25adfb0 100644 > --- a/arch/mips/include/asm/highmem.h > +++ b/arch/mips/include/asm/highmem.h > @@ -30,8 +30,6 @@ > /* declarations for highmem.c */ > extern unsigned long highstart_pfn, highend_pfn; > > -extern pte_t *kmap_pte; > -extern pgprot_t kmap_prot; > extern pte_t *pkmap_page_table; > > /* > @@ -62,6 +60,10 @@ extern struct page *__kmap_atomic_to_page(void *ptr); > > #define flush_cache_kmaps() flush_cache_all() > > +extern void kmap_init(void); > + > +#define kmap_prot PAGE_KERNEL > + > #endif /* __KERNEL__ */ > > #endif /* _ASM_HIGHMEM_H */ > diff --git a/arch/mips/mm/highmem.c b/arch/mips/mm/highmem.c > index 4481656..2b1309b 100644 > --- a/arch/mips/mm/highmem.c > +++ b/arch/mips/mm/highmem.c > @@ -1,7 +1,12 @@ > #include > #include > +#include > #include > > +static pte_t *kmap_pte; > + > +unsigned long highstart_pfn, highend_pfn; > + > void *__kmap(struct page *page) > { > void *addr; > @@ -14,6 +19,7 @@ void *__kmap(struct page *page) > > return addr; > } > +EXPORT_SYMBOL(__kmap); > > void __kunmap(struct page *page) > { > @@ -22,6 +28,7 @@ void __kunmap(struct page *page) > return; > kunmap_high(page); > } > +EXPORT_SYMBOL(__kunmap); > > /* > * kmap_atomic/kunmap_atomic is significantly faster than kmap/kunmap because > @@ -48,11 +55,12 @@ void *__kmap_atomic(struct page *page, enum km_type type) > #ifdef CONFIG_DEBUG_HIGHMEM > BUG_ON(!pte_none(*(kmap_pte - idx))); > #endif > - set_pte(kmap_pte-idx, mk_pte(page, kmap_prot)); > + set_pte(kmap_pte-idx, mk_pte(page, PAGE_KERNEL)); > local_flush_tlb_one((unsigned long)vaddr); > > return (void*) vaddr; > } > +EXPORT_SYMBOL(__kmap_atomic); > > void __kunmap_atomic(void *kvaddr, enum km_type type) > { > @@ -77,6 +85,7 @@ void __kunmap_atomic(void *kvaddr, enum km_type type) > > pagefault_enable(); > } > +EXPORT_SYMBOL(__kunmap_atomic); > > /* > * This is the same as kmap_atomic() but can map memory that doesn't > @@ -92,7 +101,7 @@ void *kmap_atomic_pfn(unsigned long pfn, enum km_type type) > debug_kmap_atomic(type); > idx = type + KM_TYPE_NR*smp_processor_id(); > vaddr = __fix_to_virt(FIX_KMAP_BEGIN + idx); > - set_pte(kmap_pte-idx, pfn_pte(pfn, kmap_prot)); > + set_pte(kmap_pte-idx, pfn_pte(pfn, PAGE_KERNEL)); > flush_tlb_one(vaddr); > > return (void*) vaddr; > @@ -111,7 +120,11 @@ struct page *__kmap_atomic_to_page(void *ptr) > return pte_page(*pte); > } > > -EXPORT_SYMBOL(__kmap); > -EXPORT_SYMBOL(__kunmap); > -EXPORT_SYMBOL(__kmap_atomic); > -EXPORT_SYMBOL(__kunmap_atomic); > +void __init kmap_init(void) > +{ > + unsigned long kmap_vstart; > + > + /* cache the first kmap pte */ > + kmap_vstart = __fix_to_virt(FIX_KMAP_BEGIN); > + kmap_pte = kmap_get_fixmap_pte(kmap_vstart); > +} > diff --git a/arch/mips/mm/init.c b/arch/mips/mm/init.c > index d934894..c551129 100644 > --- a/arch/mips/mm/init.c > +++ b/arch/mips/mm/init.c > @@ -104,14 +104,6 @@ unsigned long setup_zero_pages(void) > return 1UL << order; > } > > -/* > - * These are almost like kmap_atomic / kunmap_atmic except they take an > - * additional address argument as the hint. > - */ > - > -#define kmap_get_fixmap_pte(vaddr) \ > - pte_offset_kernel(pmd_offset(pud_offset(pgd_offset_k(vaddr), (vaddr)), (vaddr)), (vaddr)) > - > #ifdef CONFIG_MIPS_MT_SMTC > static pte_t *kmap_coherent_pte; > static void __init kmap_coherent_init(void) > @@ -264,24 +256,6 @@ void copy_from_user_page(struct vm_area_struct *vma, > } > } > > -#ifdef CONFIG_HIGHMEM > -unsigned long highstart_pfn, highend_pfn; > - > -pte_t *kmap_pte; > -pgprot_t kmap_prot; > - > -static void __init kmap_init(void) > -{ > - unsigned long kmap_vstart; > - > - /* cache the first kmap pte */ > - kmap_vstart = __fix_to_virt(FIX_KMAP_BEGIN); > - kmap_pte = kmap_get_fixmap_pte(kmap_vstart); > - > - kmap_prot = PAGE_KERNEL; > -} > -#endif /* CONFIG_HIGHMEM */ > - > void __init fixrange_init(unsigned long start, unsigned long end, > pgd_t *pgd_base) > { > From David.Daney@caviumnetworks.com Mon May 4 16:24:57 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 04 May 2009 16:25:03 +0100 (BST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:4327 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20022631AbZEDPY5 (ORCPT ); Mon, 4 May 2009 16:24:57 +0100 Received: from exch4.caveonetworks.com (Not Verified[192.168.16.23]) by mail3.caviumnetworks.com with MailMarshal (v6,2,2,3503) id ; Mon, 04 May 2009 11:24:26 -0400 Received: from exch4.caveonetworks.com ([192.168.16.23]) by exch4.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Mon, 4 May 2009 08:24:28 -0700 Received: from dd1.caveonetworks.com ([64.169.86.201]) by exch4.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Mon, 4 May 2009 08:24:28 -0700 Message-ID: <49FF08AC.3030901@caviumnetworks.com> Date: Mon, 04 May 2009 08:24:28 -0700 From: David Daney User-Agent: Thunderbird 2.0.0.21 (X11/20090320) MIME-Version: 1.0 To: Sam Ravnborg CC: Manuel Lauss , Anders Kaseorg , LKML , Linux-MIPS Subject: Re: Lots of unexpected non-allocatable section warnings References: <20090503110517.6d09bca2@hyperion.delvare> <20090503103010.GA27978@uranus.ravnborg.org> <20090503124848.276b437f@hyperion.delvare> <20090503180332.GA31820@uranus.ravnborg.org> <20090503202939.GA1237@uranus.ravnborg.org> <20090504082816.GA25378@roarinelk.homelinux.net> <20090504094928.GA6157@uranus.ravnborg.org> In-Reply-To: <20090504094928.GA6157@uranus.ravnborg.org> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 04 May 2009 15:24:28.0438 (UTC) FILETIME=[6A3A7360:01C9CCCC] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22610 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Content-Length: 3497 Lines: 81 Sam Ravnborg wrote: > From: Anders Kaseorg > Date: Sun, 3 May 2009 22:02:55 +0200 > Subject: [PATCH 1/2] kbuild, modpost: fix unexpected non-allocatable section when cross compiling > > The missing TO_NATIVE(sechdrs[i].sh_flags) was causing many > unexpected non-allocatable section warnings when cross-compiling > for an architecture with a different endianness. > > Fix endianness of all the fields in the ELF header and > section headers, not just some of them so we are not > hit by this anohter time. > > Signed-off-by: Anders Kaseorg > Reported-by: Sean MacLennan > Signed-off-by: Sam Ravnborg Acked-by: David Daney This is essentially what I did in my local tree to fix the problems. > --- > scripts/mod/modpost.c | 35 +++++++++++++++++++++++------------ > 1 files changed, 23 insertions(+), 12 deletions(-) > > diff --git a/scripts/mod/modpost.c b/scripts/mod/modpost.c > index 936b6f8..a5c17db 100644 > --- a/scripts/mod/modpost.c > +++ b/scripts/mod/modpost.c > @@ -384,11 +384,19 @@ static int parse_elf(struct elf_info *info, const char *filename) > return 0; > } > /* Fix endianness in ELF header */ > - hdr->e_shoff = TO_NATIVE(hdr->e_shoff); > - hdr->e_shstrndx = TO_NATIVE(hdr->e_shstrndx); > - hdr->e_shnum = TO_NATIVE(hdr->e_shnum); > - hdr->e_machine = TO_NATIVE(hdr->e_machine); > - hdr->e_type = TO_NATIVE(hdr->e_type); > + hdr->e_type = TO_NATIVE(hdr->e_type); > + hdr->e_machine = TO_NATIVE(hdr->e_machine); > + hdr->e_version = TO_NATIVE(hdr->e_version); > + hdr->e_entry = TO_NATIVE(hdr->e_entry); > + hdr->e_phoff = TO_NATIVE(hdr->e_phoff); > + hdr->e_shoff = TO_NATIVE(hdr->e_shoff); > + hdr->e_flags = TO_NATIVE(hdr->e_flags); > + hdr->e_ehsize = TO_NATIVE(hdr->e_ehsize); > + hdr->e_phentsize = TO_NATIVE(hdr->e_phentsize); > + hdr->e_phnum = TO_NATIVE(hdr->e_phnum); > + hdr->e_shentsize = TO_NATIVE(hdr->e_shentsize); > + hdr->e_shnum = TO_NATIVE(hdr->e_shnum); > + hdr->e_shstrndx = TO_NATIVE(hdr->e_shstrndx); > sechdrs = (void *)hdr + hdr->e_shoff; > info->sechdrs = sechdrs; > > @@ -402,13 +410,16 @@ static int parse_elf(struct elf_info *info, const char *filename) > > /* Fix endianness in section headers */ > for (i = 0; i < hdr->e_shnum; i++) { > - sechdrs[i].sh_type = TO_NATIVE(sechdrs[i].sh_type); > - sechdrs[i].sh_offset = TO_NATIVE(sechdrs[i].sh_offset); > - sechdrs[i].sh_size = TO_NATIVE(sechdrs[i].sh_size); > - sechdrs[i].sh_link = TO_NATIVE(sechdrs[i].sh_link); > - sechdrs[i].sh_name = TO_NATIVE(sechdrs[i].sh_name); > - sechdrs[i].sh_info = TO_NATIVE(sechdrs[i].sh_info); > - sechdrs[i].sh_addr = TO_NATIVE(sechdrs[i].sh_addr); > + sechdrs[i].sh_name = TO_NATIVE(sechdrs[i].sh_name); > + sechdrs[i].sh_type = TO_NATIVE(sechdrs[i].sh_type); > + sechdrs[i].sh_flags = TO_NATIVE(sechdrs[i].sh_flags); > + sechdrs[i].sh_addr = TO_NATIVE(sechdrs[i].sh_addr); > + sechdrs[i].sh_offset = TO_NATIVE(sechdrs[i].sh_offset); > + sechdrs[i].sh_size = TO_NATIVE(sechdrs[i].sh_size); > + sechdrs[i].sh_link = TO_NATIVE(sechdrs[i].sh_link); > + sechdrs[i].sh_info = TO_NATIVE(sechdrs[i].sh_info); > + sechdrs[i].sh_addralign = TO_NATIVE(sechdrs[i].sh_addralign); > + sechdrs[i].sh_entsize = TO_NATIVE(sechdrs[i].sh_entsize); > } > /* Find symbol table. */ > for (i = 1; i < hdr->e_shnum; i++) { From David.Daney@caviumnetworks.com Mon May 4 16:26:11 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 04 May 2009 16:26:18 +0100 (BST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:4599 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20022640AbZEDP0L (ORCPT ); Mon, 4 May 2009 16:26:11 +0100 Received: from exch4.caveonetworks.com (Not Verified[192.168.16.23]) by mail3.caviumnetworks.com with MailMarshal (v6,2,2,3503) id ; Mon, 04 May 2009 11:26:00 -0400 Received: from exch4.caveonetworks.com ([192.168.16.23]) by exch4.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Mon, 4 May 2009 08:26:02 -0700 Received: from dd1.caveonetworks.com ([64.169.86.201]) by exch4.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Mon, 4 May 2009 08:26:02 -0700 Message-ID: <49FF090A.3030505@caviumnetworks.com> Date: Mon, 04 May 2009 08:26:02 -0700 From: David Daney User-Agent: Thunderbird 2.0.0.21 (X11/20090320) MIME-Version: 1.0 To: Manuel Lauss CC: Sam Ravnborg , Anders Kaseorg , LKML , Linux-MIPS Subject: Re: Lots of unexpected non-allocatable section warnings References: <20090503110517.6d09bca2@hyperion.delvare> <20090503103010.GA27978@uranus.ravnborg.org> <20090503124848.276b437f@hyperion.delvare> <20090503180332.GA31820@uranus.ravnborg.org> <20090503202939.GA1237@uranus.ravnborg.org> <20090504082816.GA25378@roarinelk.homelinux.net> In-Reply-To: <20090504082816.GA25378@roarinelk.homelinux.net> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 04 May 2009 15:26:02.0781 (UTC) FILETIME=[A2760CD0:01C9CCCC] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22611 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Content-Length: 1129 Lines: 30 Manuel Lauss wrote: > Hi Sam, > > On Sun, May 03, 2009 at 10:29:39PM +0200, Sam Ravnborg wrote: >> This is due to the SUSE specific section as you expected. >> We ignore sections named ".comment" but not ".comment" sections >> with something appended to the name. > > > On a related note, I see tons of the following warnings cross-building for > MIPS: > > WARNING: init/mounts.o (.mdebug.abi32): unexpected non-allocatable section. > Did you forget to use "ax"/"aw" in a .S file? > Note that for example contains > section definitions for use in .S files. > > WARNING: init/mounts.o (.pdr): unexpected non-allocatable section. > Did you forget to use "ax"/"aw" in a .S file? > Note that for example contains > section definitions for use in .S files. > > > I added ".pdr" and ".mdebug*" to the whitelist; the resulting kernels still > work. (gcc-4.3.3, binutils-2.19.1) > I too think they are needed. Are you going to prepare a patch? David Daney From geert.uytterhoeven@gmail.com Mon May 4 17:45:15 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 04 May 2009 17:45:22 +0100 (BST) Received: from mail-ew0-f174.google.com ([209.85.219.174]:35097 "EHLO mail-ew0-f174.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20022905AbZEDQpP (ORCPT ); Mon, 4 May 2009 17:45:15 +0100 Received: by ewy22 with SMTP id 22so4129625ewy.0 for ; Mon, 04 May 2009 09:45:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:sender:received:date :x-google-sender-auth:message-id:subject:from:to:content-type :content-transfer-encoding; bh=/+wG92suaR8HSBUo/B3voLxMhGGqHF1aFFLoK6gZhxQ=; b=T/+IYSFdwgTEUJMGOLjjfWCkin3GrV5Zfr0vO3KNUXNKzCx+xDirTzo8ujTsL5W/ed WTrJcIQGmy+g0EUi2NMp92Ukx4AynIYOsQ87JZ3aZhtT8KFE2sM6l6vmpTnIsLzDFjqF fNLyKraIKtxskJU2AxUKJYRS0jJqqvoG2+Pek= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:sender:date:x-google-sender-auth:message-id:subject :from:to:content-type:content-transfer-encoding; b=Y0xrWIF2CP7GCPk7ecGal18uY9JrYe6UngLl5oWdKqORPEx0tmGEmnJbnrKo4mIbqn GrcHEY2APmiaqOLa3TMMsQSuoPZ9ElOQiSwZmhC4eqnQun6BW9Dz9JQjB/VySXMSDgGX TTpvxTUAKyeWjwVtszT+3E7wM9r43HsaJdGoE= MIME-Version: 1.0 Received: by 10.210.120.17 with SMTP id s17mr6362151ebc.99.1241455509657; Mon, 04 May 2009 09:45:09 -0700 (PDT) Date: Mon, 4 May 2009 18:45:09 +0200 X-Google-Sender-Auth: 050649cddb96c7b7 Message-ID: <10f740e80905040945i186e995ap1ecb43c2ad3e2458@mail.gmail.com> Subject: rbtx4927 and sound? From: Geert Uytterhoeven To: linux-mips@linux-mips.org Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22612 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: geert@linux-m68k.org Precedence: bulk X-list: linux-mips Content-Length: 447 Lines: 15 Did anyone ever try to get sound working on the Toshiba RBTX4927? It seems the AD1881A codec is connected to PIO2-4 of the TMPR4927 SoC. Thx! Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds From dvomlehn@cisco.com Mon May 4 18:23:46 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 04 May 2009 18:23:53 +0100 (BST) Received: from sj-iport-6.cisco.com ([171.71.176.117]:59134 "EHLO sj-iport-6.cisco.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20022995AbZEDRXq convert rfc822-to-8bit (ORCPT ); Mon, 4 May 2009 18:23:46 +0100 X-IronPort-AV: E=Sophos;i="4.40,292,1238976000"; d="scan'208";a="298015101" Received: from sj-dkim-3.cisco.com ([171.71.179.195]) by sj-iport-6.cisco.com with ESMTP; 04 May 2009 17:23:26 +0000 Received: from sj-core-5.cisco.com (sj-core-5.cisco.com [171.71.177.238]) by sj-dkim-3.cisco.com (8.12.11/8.12.11) with ESMTP id n44HNQUc006745; Mon, 4 May 2009 10:23:26 -0700 Received: from xbh-rtp-201.amer.cisco.com (xbh-rtp-201.cisco.com [64.102.31.12]) by sj-core-5.cisco.com (8.13.8/8.13.8) with ESMTP id n44HNLKi007988; Mon, 4 May 2009 17:23:26 GMT Received: from xmb-rtp-218.amer.cisco.com ([64.102.31.117]) by xbh-rtp-201.amer.cisco.com with Microsoft SMTPSVC(6.0.3790.1830); Mon, 4 May 2009 13:23:25 -0400 X-MimeOLE: Produced By Microsoft Exchange V6.5 Content-class: urn:content-classes:message MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT Subject: RE: HIGHMEM fix for r24k Date: Mon, 4 May 2009 13:23:24 -0400 Message-ID: In-Reply-To: <1241448586.15448.249.camel@chaos.ne.broadcom.com> X-MS-Has-Attach: X-MS-TNEF-Correlator: Thread-Topic: HIGHMEM fix for r24k thread-index: AcnMx7HU36/RKYELQCGLHXEBk+s16QAFR0Dw References: <1240525424.15448.33.camel@chaos.ne.broadcom.com> <20090424154349.GB3614@linux-mips.org> <1240589632.15448.38.camel@chaos.ne.broadcom.com> <20090425092446.GA9845@linux-mips.org> <1241448586.15448.249.camel@chaos.ne.broadcom.com> From: "David VomLehn (dvomlehn)" To: , "Ralf Baechle" Cc: X-OriginalArrivalTime: 04 May 2009 17:23:25.0822 (UTC) FILETIME=[0870D1E0:01C9CCDD] DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; l=6972; t=1241457806; x=1242321806; c=relaxed/simple; s=sjdkim3002; h=Content-Type:From:Subject:Content-Transfer-Encoding:MIME-Version; d=cisco.com; i=dvomlehn@cisco.com; z=From:=20=22David=20VomLehn=20(dvomlehn)=22=20 |Subject:=20RE=3A=20HIGHMEM=20fix=20for=20r24k |Sender:=20; bh=N/nP6Z0C+9ih/IWlNaWhzfUeCtZzJsyMNzGETiHoF3s=; b=ejMcOrr6771+eRbEXkTPtQeHTvmc+9JFv2eRK56p633AwNJ+BQ+Q/dS4eA TKhYNLS0xIQLXgWNDcJCRLjSkDME8pKDMSgCS5MK/M2lmu46bEsgD8cRJVTR iK9J83bqSV; Authentication-Results: sj-dkim-3; header.From=dvomlehn@cisco.com; dkim=pass ( sig from cisco.com/sjdkim3002 verified; ); Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22613 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dvomlehn@cisco.com Precedence: bulk X-list: linux-mips Content-Length: 6615 Lines: 229 I applied it against the head of tree, but it didn't work. I've been too tied up with other things, though, so I haven't been able to dig into it. It is entirely possible that there is nothing wrong with the patch. > -----Original Message----- > From: linux-mips-bounce@linux-mips.org > [mailto:linux-mips-bounce@linux-mips.org] On Behalf Of Jon Fraser > Sent: Monday, May 04, 2009 7:50 AM > To: Ralf Baechle > Cc: jfraser@broadcom.com; linux-mips@linux-mips.org > Subject: Re: HIGHMEM fix for r24k > > Hi Ralf, > > Just wanted to acknowledge your email. I've been > playing catch > up for the last week after spending a large amount of unscheduled time > finding the root cause of this bug. I should be able to get > to applying > this patch this week. Were these against HOT or 2.6.29? > > Jon > > > On Sat, 2009-04-25 at 02:24 -0700, Ralf Baechle wrote: > > On Fri, Apr 24, 2009 at 12:13:52PM -0400, Jon Fraser wrote: > > > > > That's why I haven't proposed a fix yet. But there are > other people > > > dealing with the same HIGHMEM issues and I wanted them to > know about the > > > problem. > > > > Can you test below fix? Thanks, > > > > Ralf > > > > Signed-off-by: Ralf Baechle > > > > arch/mips/include/asm/fixmap.h | 3 +++ > > arch/mips/include/asm/highmem.h | 6 ++++-- > > arch/mips/mm/highmem.c | 25 +++++++++++++++++++------ > > arch/mips/mm/init.c | 26 -------------------------- > > 4 files changed, 26 insertions(+), 34 deletions(-) > > > > diff --git a/arch/mips/include/asm/fixmap.h > b/arch/mips/include/asm/fixmap.h > > index 9cc8522..0f5caa1 100644 > > --- a/arch/mips/include/asm/fixmap.h > > +++ b/arch/mips/include/asm/fixmap.h > > @@ -108,6 +108,9 @@ static inline unsigned long > virt_to_fix(const unsigned long vaddr) > > return __virt_to_fix(vaddr); > > } > > > > +#define kmap_get_fixmap_pte(vaddr) > \ > > + > pte_offset_kernel(pmd_offset(pud_offset(pgd_offset_k(vaddr), > (vaddr)), (vaddr)), (vaddr)) > > + > > /* > > * Called from pgtable_init() > > */ > > diff --git a/arch/mips/include/asm/highmem.h > b/arch/mips/include/asm/highmem.h > > index 4374ab2..25adfb0 100644 > > --- a/arch/mips/include/asm/highmem.h > > +++ b/arch/mips/include/asm/highmem.h > > @@ -30,8 +30,6 @@ > > /* declarations for highmem.c */ > > extern unsigned long highstart_pfn, highend_pfn; > > > > -extern pte_t *kmap_pte; > > -extern pgprot_t kmap_prot; > > extern pte_t *pkmap_page_table; > > > > /* > > @@ -62,6 +60,10 @@ extern struct page > *__kmap_atomic_to_page(void *ptr); > > > > #define flush_cache_kmaps() flush_cache_all() > > > > +extern void kmap_init(void); > > + > > +#define kmap_prot PAGE_KERNEL > > + > > #endif /* __KERNEL__ */ > > > > #endif /* _ASM_HIGHMEM_H */ > > diff --git a/arch/mips/mm/highmem.c b/arch/mips/mm/highmem.c > > index 4481656..2b1309b 100644 > > --- a/arch/mips/mm/highmem.c > > +++ b/arch/mips/mm/highmem.c > > @@ -1,7 +1,12 @@ > > #include > > #include > > +#include > > #include > > > > +static pte_t *kmap_pte; > > + > > +unsigned long highstart_pfn, highend_pfn; > > + > > void *__kmap(struct page *page) > > { > > void *addr; > > @@ -14,6 +19,7 @@ void *__kmap(struct page *page) > > > > return addr; > > } > > +EXPORT_SYMBOL(__kmap); > > > > void __kunmap(struct page *page) > > { > > @@ -22,6 +28,7 @@ void __kunmap(struct page *page) > > return; > > kunmap_high(page); > > } > > +EXPORT_SYMBOL(__kunmap); > > > > /* > > * kmap_atomic/kunmap_atomic is significantly faster than > kmap/kunmap because > > @@ -48,11 +55,12 @@ void *__kmap_atomic(struct page *page, > enum km_type type) > > #ifdef CONFIG_DEBUG_HIGHMEM > > BUG_ON(!pte_none(*(kmap_pte - idx))); > > #endif > > - set_pte(kmap_pte-idx, mk_pte(page, kmap_prot)); > > + set_pte(kmap_pte-idx, mk_pte(page, PAGE_KERNEL)); > > local_flush_tlb_one((unsigned long)vaddr); > > > > return (void*) vaddr; > > } > > +EXPORT_SYMBOL(__kmap_atomic); > > > > void __kunmap_atomic(void *kvaddr, enum km_type type) > > { > > @@ -77,6 +85,7 @@ void __kunmap_atomic(void *kvaddr, enum > km_type type) > > > > pagefault_enable(); > > } > > +EXPORT_SYMBOL(__kunmap_atomic); > > > > /* > > * This is the same as kmap_atomic() but can map memory > that doesn't > > @@ -92,7 +101,7 @@ void *kmap_atomic_pfn(unsigned long pfn, > enum km_type type) > > debug_kmap_atomic(type); > > idx = type + KM_TYPE_NR*smp_processor_id(); > > vaddr = __fix_to_virt(FIX_KMAP_BEGIN + idx); > > - set_pte(kmap_pte-idx, pfn_pte(pfn, kmap_prot)); > > + set_pte(kmap_pte-idx, pfn_pte(pfn, PAGE_KERNEL)); > > flush_tlb_one(vaddr); > > > > return (void*) vaddr; > > @@ -111,7 +120,11 @@ struct page *__kmap_atomic_to_page(void *ptr) > > return pte_page(*pte); > > } > > > > -EXPORT_SYMBOL(__kmap); > > -EXPORT_SYMBOL(__kunmap); > > -EXPORT_SYMBOL(__kmap_atomic); > > -EXPORT_SYMBOL(__kunmap_atomic); > > +void __init kmap_init(void) > > +{ > > + unsigned long kmap_vstart; > > + > > + /* cache the first kmap pte */ > > + kmap_vstart = __fix_to_virt(FIX_KMAP_BEGIN); > > + kmap_pte = kmap_get_fixmap_pte(kmap_vstart); > > +} > > diff --git a/arch/mips/mm/init.c b/arch/mips/mm/init.c > > index d934894..c551129 100644 > > --- a/arch/mips/mm/init.c > > +++ b/arch/mips/mm/init.c > > @@ -104,14 +104,6 @@ unsigned long setup_zero_pages(void) > > return 1UL << order; > > } > > > > -/* > > - * These are almost like kmap_atomic / kunmap_atmic except > they take an > > - * additional address argument as the hint. > > - */ > > - > > -#define kmap_get_fixmap_pte(vaddr) > \ > > - > pte_offset_kernel(pmd_offset(pud_offset(pgd_offset_k(vaddr), > (vaddr)), (vaddr)), (vaddr)) > > - > > #ifdef CONFIG_MIPS_MT_SMTC > > static pte_t *kmap_coherent_pte; > > static void __init kmap_coherent_init(void) > > @@ -264,24 +256,6 @@ void copy_from_user_page(struct > vm_area_struct *vma, > > } > > } > > > > -#ifdef CONFIG_HIGHMEM > > -unsigned long highstart_pfn, highend_pfn; > > - > > -pte_t *kmap_pte; > > -pgprot_t kmap_prot; > > - > > -static void __init kmap_init(void) > > -{ > > - unsigned long kmap_vstart; > > - > > - /* cache the first kmap pte */ > > - kmap_vstart = __fix_to_virt(FIX_KMAP_BEGIN); > > - kmap_pte = kmap_get_fixmap_pte(kmap_vstart); > > - > > - kmap_prot = PAGE_KERNEL; > > -} > > -#endif /* CONFIG_HIGHMEM */ > > - > > void __init fixrange_init(unsigned long start, unsigned long end, > > pgd_t *pgd_base) > > { > > > > > > From greg@kroah.com Mon May 4 21:05:11 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 04 May 2009 21:05:18 +0100 (BST) Received: from kroah.org ([198.145.64.141]:37335 "EHLO coco.kroah.org" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20023350AbZEDUFL (ORCPT ); Mon, 4 May 2009 21:05:11 +0100 Received: from localhost (c-76-105-230-205.hsd1.or.comcast.net [76.105.230.205]) (using TLSv1 with cipher DHE-RSA-AES128-SHA (128/128 bits)) (No client certificate requested) by coco.kroah.org (Postfix) with ESMTPSA id 1472448FB3; Mon, 4 May 2009 13:05:08 -0700 (PDT) Date: Mon, 4 May 2009 13:01:17 -0700 From: Greg Kroah-Hartman To: Ralf Baechle Cc: linux-mips@linux-mips.org, Greg KH Subject: [PATCH] mips: remove driver_data direct access of struct device Message-ID: <20090504200117.GA22829@kroah.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline User-Agent: Mutt/1.5.19 (2009-01-05) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22614 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: gregkh@suse.de Precedence: bulk X-list: linux-mips Content-Length: 896 Lines: 26 From: Greg Kroah-Hartman In the near future, the driver core is going to not allow direct access to the driver_data pointer in struct device. Instead, the functions dev_get_drvdata() and dev_set_drvdata() should be used. These functions have been around since the beginning, so are backwards compatible with all older kernel versions. Cc: linux-mips@linux-mips.org Cc: Ralf Baechle Signed-off-by: Greg Kroah-Hartman --- arch/mips/sni/eisa.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) --- a/arch/mips/sni/eisa.c +++ b/arch/mips/sni/eisa.c @@ -38,7 +38,7 @@ int __init sni_eisa_root_init(void) if (!r) return r; - eisa_root_dev.dev.driver_data = &eisa_bus_root; + dev_set_drvdata(&eisa_root_dev.dev, &eisa_bus_root); if (eisa_root_register(&eisa_bus_root)) { /* A real bridge may have been registered before From tsbogend@alpha.franken.de Mon May 4 22:54:33 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 04 May 2009 22:54:40 +0100 (BST) Received: from elvis.franken.de ([193.175.24.41]:53597 "EHLO elvis.franken.de" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20023514AbZEDVyd (ORCPT ); Mon, 4 May 2009 22:54:33 +0100 Received: from uucp (helo=solo.franken.de) by elvis.franken.de with local-bsmtp (Exim 3.36 #1) id 1M167M-0005fm-02; Mon, 04 May 2009 23:54:32 +0200 Received: by solo.franken.de (Postfix, from userid 1000) id 77D33C2C47; Mon, 4 May 2009 23:54:22 +0200 (CEST) Date: Mon, 4 May 2009 23:54:22 +0200 To: Jon Fraser Cc: "linux-mips@linux-mips.org" Subject: Re: linux-mips on big_sur (broadcom 1480) Message-ID: <20090504215422.GB16886@alpha.franken.de> References: <1239227598.14558.39.camel@chaos.ne.broadcom.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1239227598.14558.39.camel@chaos.ne.broadcom.com> User-Agent: Mutt/1.5.13 (2006-08-11) From: tsbogend@alpha.franken.de (Thomas Bogendoerfer) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22616 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: tsbogend@alpha.franken.de Precedence: bulk X-list: linux-mips Content-Length: 489 Lines: 13 On Wed, Apr 08, 2009 at 05:53:18PM -0400, Jon Fraser wrote: > Can anybody confirm the running any of the sibyte processors on any of > the latest kernels? I've sent a fix a couple of seconds ago, which fixes SMP for BCM1480 and SB1250 systems. I could only test on a BigSur, but the breakage for SB1250 systems is the same. Thomas. -- Crap can work. Given enough thrust pigs will fly, but it's not necessary a good idea. [ RFC1925, 2.3 ] From tsbogend@alpha.franken.de Mon May 4 22:54:57 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 04 May 2009 22:55:05 +0100 (BST) Received: from elvis.franken.de ([193.175.24.41]:53596 "EHLO elvis.franken.de" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20023500AbZEDVyd (ORCPT ); Mon, 4 May 2009 22:54:33 +0100 Received: from uucp (helo=solo.franken.de) by elvis.franken.de with local-bsmtp (Exim 3.36 #1) id 1M167M-0005fm-00; Mon, 04 May 2009 23:54:32 +0200 Received: by solo.franken.de (Postfix, from userid 1000) id 461B2E31C1; Mon, 4 May 2009 23:51:55 +0200 (CEST) From: Thomas Bogendoerfer Subject: [PATCH] SIBYTE: fix locking in set_irq_affinity To: linux-mips@linux-mips.org cc: ralf@linux-mips.org Message-Id: <20090504215155.461B2E31C1@solo.franken.de> Date: Mon, 4 May 2009 23:51:54 +0200 (CEST) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22617 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: tsbogend@alpha.franken.de Precedence: bulk X-list: linux-mips Content-Length: 2731 Lines: 74 Locking of irq_desc is now done in irq_set_affinity; Don't lock it again in chip specific set_affinity function. Signed-off-by: Thomas Bogendoerfer --- arch/mips/sibyte/bcm1480/irq.c | 7 ++----- arch/mips/sibyte/sb1250/irq.c | 7 ++----- 2 files changed, 4 insertions(+), 10 deletions(-) diff --git a/arch/mips/sibyte/bcm1480/irq.c b/arch/mips/sibyte/bcm1480/irq.c index 352352b..c147c4b 100644 --- a/arch/mips/sibyte/bcm1480/irq.c +++ b/arch/mips/sibyte/bcm1480/irq.c @@ -113,7 +113,6 @@ static void bcm1480_set_affinity(unsigned int irq, const struct cpumask *mask) { int i = 0, old_cpu, cpu, int_on, k; u64 cur_ints; - struct irq_desc *desc = irq_desc + irq; unsigned long flags; unsigned int irq_dirty; @@ -127,8 +126,7 @@ static void bcm1480_set_affinity(unsigned int irq, const struct cpumask *mask) cpu = cpu_logical_map(i); /* Protect against other affinity changers and IMR manipulation */ - spin_lock_irqsave(&desc->lock, flags); - spin_lock(&bcm1480_imr_lock); + spin_lock_irqsave(&bcm1480_imr_lock, flags); /* Swizzle each CPU's IMR (but leave the IP selection alone) */ old_cpu = bcm1480_irq_owner[irq]; @@ -153,8 +151,7 @@ static void bcm1480_set_affinity(unsigned int irq, const struct cpumask *mask) ____raw_writeq(cur_ints, IOADDR(A_BCM1480_IMR_MAPPER(cpu) + R_BCM1480_IMR_INTERRUPT_MASK_H + (k*BCM1480_IMR_HL_SPACING))); } } - spin_unlock(&bcm1480_imr_lock); - spin_unlock_irqrestore(&desc->lock, flags); + spin_unlock_irqrestore(&bcm1480_imr_lock, flags); } #endif diff --git a/arch/mips/sibyte/sb1250/irq.c b/arch/mips/sibyte/sb1250/irq.c index c08ff58..38cb998 100644 --- a/arch/mips/sibyte/sb1250/irq.c +++ b/arch/mips/sibyte/sb1250/irq.c @@ -107,7 +107,6 @@ static void sb1250_set_affinity(unsigned int irq, const struct cpumask *mask) { int i = 0, old_cpu, cpu, int_on; u64 cur_ints; - struct irq_desc *desc = irq_desc + irq; unsigned long flags; i = cpumask_first(mask); @@ -121,8 +120,7 @@ static void sb1250_set_affinity(unsigned int irq, const struct cpumask *mask) cpu = cpu_logical_map(i); /* Protect against other affinity changers and IMR manipulation */ - spin_lock_irqsave(&desc->lock, flags); - spin_lock(&sb1250_imr_lock); + spin_lock_irqsave(&sb1250_imr_lock, flags); /* Swizzle each CPU's IMR (but leave the IP selection alone) */ old_cpu = sb1250_irq_owner[irq]; @@ -144,8 +142,7 @@ static void sb1250_set_affinity(unsigned int irq, const struct cpumask *mask) ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) + R_IMR_INTERRUPT_MASK)); } - spin_unlock(&sb1250_imr_lock); - spin_unlock_irqrestore(&desc->lock, flags); + spin_unlock_irqrestore(&sb1250_imr_lock, flags); } #endif From dvomlehn@cisco.com Mon May 4 23:55:21 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 04 May 2009 23:55:28 +0100 (BST) Received: from sj-iport-2.cisco.com ([171.71.176.71]:12958 "EHLO sj-iport-2.cisco.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20023529AbZEDWzV (ORCPT ); Mon, 4 May 2009 23:55:21 +0100 X-IronPort-AV: E=Sophos;i="4.40,293,1238976000"; d="scan'208";a="161761723" Received: from sj-dkim-1.cisco.com ([171.71.179.21]) by sj-iport-2.cisco.com with ESMTP; 04 May 2009 22:55:14 +0000 Received: from sj-core-1.cisco.com (sj-core-1.cisco.com [171.71.177.237]) by sj-dkim-1.cisco.com (8.12.11/8.12.11) with ESMTP id n44MtExo007122; Mon, 4 May 2009 15:55:14 -0700 Received: from cuplxvomd02.corp.sa.net ([64.101.20.155]) by sj-core-1.cisco.com (8.13.8/8.13.8) with ESMTP id n44MtECt028576; Mon, 4 May 2009 22:55:14 GMT Date: Mon, 4 May 2009 15:55:14 -0700 From: David VomLehn To: linux-mips@linux-mips.org Cc: ralf@linux-mips.org Subject: [PATCH 0/3] mips:powertv: Introduction to new Cisco Powertv platform, v2 Message-ID: <20090504225514.GA22180@cuplxvomd02.corp.sa.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline User-Agent: Mutt/1.5.18 (2008-05-17) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; l=821; t=1241477714; x=1242341714; c=relaxed/simple; s=sjdkim1004; h=Content-Type:From:Subject:Content-Transfer-Encoding:MIME-Version; d=cisco.com; i=dvomlehn@cisco.com; z=From:=20David=20VomLehn=20 |Subject:=20[PATCH=200/3]=20mips=3Apowertv=3A=20Introductio n=20to=20new=20Cisco=20Powertv=0A=09platform,=20v2 |Sender:=20; bh=efU4IbRwGKdcEs1fLuqdJnM/+sBaMVvlPKPiU81GNqA=; b=VuOvCJSJbAtB4hch4NkM04TUm7z2oNp/3cTmX2BDgdzTx4AyjtTD8K3qAW GduRe+ma/2EnjwpLQ74bhribIatIE7Efq6xNTSsukMiCiUMShMYWCeLnB07m n1U6g4zoCb3C7EDf82W+N/i2KecuT8AB/IyxIaJTsmJQ8uweJfrZY=; Authentication-Results: sj-dkim-1; header.From=dvomlehn@cisco.com; dkim=pass ( sig from cisco.com/sjdkim1004 verified; ); Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22618 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dvomlehn@cisco.com Precedence: bulk X-list: linux-mips Content-Length: 804 Lines: 24 The following series of patches adds the Cisco Powertv cable settop box to the MIPS tree. The following patches are included: powertv-intro.patch This file powertv-base.patch Base kernel files powertv-config-cmdline-size.patch Allow configurable command line buffer size powertv-integrate.patch Integrate the Powertv platform with other MIPS-based platforms This code has been out of the tree *way* too long and, though it has no checkpatch errors, it a few checkpatch warnings and other non-standard things in it. Still, you have to start sometime, so this is where things are today. History v2 Dropped DMA fixes and PowerTV-specific USB code. They are required for the PowerTV platform, but will be posted separately. v1 Original version Signed-off-by: David VomLehn --- From dvomlehn@cisco.com Mon May 4 23:56:28 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 04 May 2009 23:56:45 +0100 (BST) Received: from sj-iport-1.cisco.com ([171.71.176.70]:55050 "EHLO sj-iport-1.cisco.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20023529AbZEDW42 (ORCPT ); Mon, 4 May 2009 23:56:28 +0100 X-IronPort-AV: E=Sophos;i="4.40,293,1238976000"; d="scan'208";a="180713028" Received: from sj-dkim-3.cisco.com ([171.71.179.195]) by sj-iport-1.cisco.com with ESMTP; 04 May 2009 22:56:17 +0000 Received: from sj-core-2.cisco.com (sj-core-2.cisco.com [171.71.177.254]) by sj-dkim-3.cisco.com (8.12.11/8.12.11) with ESMTP id n44MuG48020569; Mon, 4 May 2009 15:56:16 -0700 Received: from cuplxvomd02.corp.sa.net ([64.101.20.155]) by sj-core-2.cisco.com (8.13.8/8.13.8) with ESMTP id n44MuGdL014043; Mon, 4 May 2009 22:56:16 GMT Date: Mon, 4 May 2009 15:56:16 -0700 From: David VomLehn To: linux-mips@linux-mips.org Cc: ralf@linux-mips.org Subject: [PATCH 1/3] mips:powertv: Base files for Cisco Powertv platform (resend) Message-ID: <20090504225616.GA22321@cuplxvomd02.corp.sa.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline User-Agent: Mutt/1.5.18 (2008-05-17) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; l=270104; t=1241477777; x=1242341777; c=relaxed/simple; s=sjdkim3002; h=Content-Type:From:Subject:Content-Transfer-Encoding:MIME-Version; d=cisco.com; i=dvomlehn@cisco.com; z=From:=20David=20VomLehn=20 |Subject:=20[PATCH=201/3]=20mips=3Apowertv=3A=20Base=20file s=20for=20Cisco=20Powertv=20platform=0A=09(resend) |Sender:=20; bh=zdnVT0CjGUx6Igui7a1cPeGcIzUuGcw8ISJlILfLG/g=; b=f0IcxqciPsnS4t9jEBcR5Ior9Iu5+cNNDgG8Px85p2CIpMlb1dIqHeQRyQ Wxo3nOCibu2xpP7dsTpP4L0PQT0YTfNdM9GsAxUMKgxyt8z91w//PnJd4zs2 B/TOnQ9YqN; Authentication-Results: sj-dkim-3; header.From=dvomlehn@cisco.com; dkim=pass ( sig from cisco.com/sjdkim3002 verified; ); Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22619 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dvomlehn@cisco.com Precedence: bulk X-list: linux-mips Content-Length: 261454 Lines: 8650 Adds the C and header source files for the Cisco PowerTV platform. History v2 Check clocksource function to correspond to changed prototype. v1 First release Signed-off-by: David VomLehn --- arch/mips/include/asm/mach-powertv/asic.h | 124 + arch/mips/include/asm/mach-powertv/asic_regs.h | 136 + arch/mips/include/asm/mach-powertv/dma-coherence.h | 123 + arch/mips/include/asm/mach-powertv/interrupts.h | 234 ++ arch/mips/include/asm/mach-powertv/war.h | 27 + arch/mips/powertv/Kconfig | 17 + arch/mips/powertv/Makefile | 37 + arch/mips/powertv/asic/Kconfig | 24 + arch/mips/powertv/asic/Makefile | 24 + arch/mips/powertv/asic/asic_devices.c | 2902 +++++++++++++++++++ arch/mips/powertv/asic/asic_int.c | 146 + arch/mips/powertv/asic/irq_asic.c | 115 + arch/mips/powertv/cevt-powertv.c | 247 ++ arch/mips/powertv/cmdline.c | 51 + arch/mips/powertv/csrc-powertv.c | 84 + arch/mips/powertv/init.c | 127 + arch/mips/powertv/init.h | 10 + arch/mips/powertv/memory.c | 183 ++ arch/mips/powertv/pci/Makefile | 26 + arch/mips/powertv/pci/fixup-powertv.c | 14 + arch/mips/powertv/pci/pci.c | 35 + arch/mips/powertv/pci/pciemod.c | 2921 ++++++++++++++++++++ arch/mips/powertv/pci/pcieregs.h | 333 +++ arch/mips/powertv/pci/powertv-pci.h | 12 + arch/mips/powertv/powertv-clock.h | 10 + arch/mips/powertv/powertv_setup.c | 351 +++ arch/mips/powertv/reset.c | 69 + arch/mips/powertv/reset.h | 8 + arch/mips/powertv/time.c | 47 + 29 files changed, 8437 insertions(+), 0 deletions(-) diff --git a/arch/mips/include/asm/mach-powertv/asic.h b/arch/mips/include/asm/mach-powertv/asic.h new file mode 100644 index 0000000..4240e4e --- /dev/null +++ b/arch/mips/include/asm/mach-powertv/asic.h @@ -0,0 +1,124 @@ +#ifndef _ASM_ASIC_H +#define _ASM_ASIC_H + +#include + +#define DVR_CAPABLE (1<<0) +#define PCIE_CAPABLE (1<<1) +#define FFS_CAPABLE (1<<2) +#define DISPLAY_CAPABLE (1<<3) + +/* Platform Family types + * For compitability, the new value must be added in the end */ +enum tFamilyType { + FAMILY_8500, + FAMILY_8500RNG, + FAMILY_4500, + FAMILY_1500, + FAMILY_8600, + FAMILY_4600, + FAMILY_4600VZA, + FAMILY_8600VZB, + FAMILY_1500VZE, + FAMILY_1500VZF, + FAMILIES +}; + +extern void powertv_platform_init(void); +extern void platform_alloc_bootmem(void); +extern enum tAsicType platform_get_asic(void); +extern enum tFamilyType platform_get_family(void); +extern int platform_supports_dvr(void); +extern int platform_supports_ffs(void); +extern int platform_supports_pcie(void); +extern int platform_supports_display(void); +extern void configure_platform(void); +extern void platform_configure_usb_ehci(void); +extern void platform_unconfigure_usb_ehci(void); +extern void platform_configure_usb_ohci(void); +extern void platform_unconfigure_usb_ohci(void); + +/* + * The bus addresses are different than the physical addresses that + * the processor sees by an offset. This offset varies by ASIC + * version. Define a variable to hold the offset and some macros to + * make the conversion simpler. */ +extern unsigned long gPhysToBusOffset; + +#ifdef CONFIG_HIGHMEM +/* + * TODO: We will use the hard code for conversion between physical and + * bus until the bootloader releases their device tree to us. + */ +#define phys_to_bus(x) (((x) < 0x20000000) ? ((x) + gPhysToBusOffset) : (x)) +#define bus_to_phys(x) (((x) < 0x60000000) ? ((x) - gPhysToBusOffset) : (x)) +#else +#define phys_to_bus(x) ((x) + gPhysToBusOffset) +#define bus_to_phys(x) ((x) - gPhysToBusOffset) +#endif + +/* + * Determine whether the address we are given is for an ASIC device + * Params: addr Address to check + * Returns: Zero if the address is not for ASIC devices, non-zero + * if it is. + */ +static inline int asic_is_device_addr(phys_t addr) +{ + return !((phys_t)addr & (phys_t) ~0x1fffffffULL); +} + +/* + * Determine whether the address we are given is external RAM mappable + * into KSEG1. + * Params: addr Address to check + * Returns: Zero if the address is not for external RAM and + */ +static inline int asic_is_lowmem_ram_addr(phys_t addr) +{ + /* + * The RAM always starts at the following address in the processor's + * physical address space + */ + static const phys_t phys_ram_base = 0x10000000; + phys_t bus_ram_base; + + bus_ram_base = gPhysToBusOffset + phys_ram_base; + + return addr >= bus_ram_base && + addr < (bus_ram_base + 256 * 1024 * 1024); +} + +/* Platform Resources */ +#define ASIC_RESOURCE_GET_EXISTS 1 +extern struct resource *asic_resource_get(const char *name); +extern void platform_release_memory(void *baddr, int size); + +/* Reboot Cause */ +extern void set_reboot_cause(char code, unsigned int data, unsigned int data2); +extern void set_locked_reboot_cause(char code, unsigned int data, + unsigned int data2); + +enum eSys_RebootType { + kSys_UnknownReboot = 0x00, /* Unknown reboot cause */ + kSys_DavicChange = 0x01, /* Reboot due to change in DAVIC + * mode */ + kSys_UserReboot = 0x02, /* Reboot initiated by user */ + kSys_SystemReboot = 0x03, /* Reboot initiated by OS */ + kSys_TrapReboot = 0x04, /* Reboot due to a CPU trap */ + kSys_SilentReboot = 0x05, /* Silent reboot */ + kSys_BootLdrReboot = 0x06, /* Bootloader reboot */ + kSys_PowerUpReboot = 0x07, /* Power on bootup. Older + * drivers may report as + * userReboot. */ + kSys_CodeChange = 0x08, /* Reboot to take code change. + * Older drivers may report as + * userReboot. */ + kSys_HardwareReset = 0x09, /* HW Watchdog or front-panel + * reset button reset. Older + * drivers may report as + * userReboot. */ + kSys_WatchdogInterrupt = 0x0A /* Pre-watchdog interrupt */ +}; + +#endif /* _ASM_ASIC_H */ diff --git a/arch/mips/include/asm/mach-powertv/asic_regs.h b/arch/mips/include/asm/mach-powertv/asic_regs.h new file mode 100644 index 0000000..8bdbec2 --- /dev/null +++ b/arch/mips/include/asm/mach-powertv/asic_regs.h @@ -0,0 +1,136 @@ + +#ifndef __ASIC_H_ +#define __ASIC_H_ +#include + +/* ASIC types */ +enum tAsicType { + ASIC_UNKNOWN, + ASIC_ZEUS, + ASIC_CALLIOPE, + ASIC_CRONUS, + ASIC_CRONUSLITE, + ASICS +}; + +/* hardcoded values read from Chip Version registers */ +#define CRONUS_10 0x0B4C1C20 +#define CRONUS_11 0x0B4C1C21 +#define CRONUSLITE_10 0x0B4C1C40 + +#define NAND_FLASH_BASE 0x03000000 +#define ZEUS_IO_BASE 0x09000000 +#define CALLIOPE_IO_BASE 0x08000000 +#define CRONUS_IO_BASE 0x09000000 +#define ASIC_IO_SIZE 0x01000000 + +/* ASIC register enumeration */ +struct tRegisterMap { /* ==ZEUS== ==CALLIOPE== */ + int EIC_SLOW0_STRT_ADD; + int EIC_CFG_BITS; + int EIC_READY_STATUS; /* 0x00004c 0x80004c */ + + int CHIPVER3; /* 0x280800 0xA00800 */ + int CHIPVER2; /* 0x280804 0xA00804 */ + int CHIPVER1; /* 0x280808 0xA00808 */ + int CHIPVER0; /* 0x28080c 0xA0080c */ + + int UART1_INTSTAT; /* 0x281800 0xA01800 */ + int UART1_INTEN; /* 0x281804 0xA01804 */ + int UART1_CONFIG1; /* 0x281808 0xA01808 */ + int UART1_CONFIG2; /* 0x28180C 0xA0180C */ + int UART1_DIVISORHI; /* 0x281810 0xA01810 */ + int UART1_DIVISORLO; /* 0x281814 0xA01814 */ + int UART1_DATA; /* 0x281818 0xA01818 */ + int UART1_STATUS; /* 0x28181C 0xA0181C */ + + int Int_Stat_3; /* 0x282800 0xA02800 */ + int Int_Stat_2; /* 0x282804 0xA02804 */ + int Int_Stat_1; /* 0x282808 0xA02808 */ + int Int_Stat_0; /* 0x28280c 0xA0280c */ + int Int_Config; /* 0x282810 0xA02810 */ + int Int_Int_Scan; /* 0x282818 0xA02818 */ + int Ien_Int_3; /* 0x282830 0xA02830 */ + int Ien_Int_2; /* 0x282834 0xA02834 */ + int Ien_Int_1; /* 0x282838 0xA02838 */ + int Ien_Int_0; /* 0x28283c 0xA0283c */ + int Int_Level_3_3; /* 0x282880 0xA02880 */ + int Int_Level_3_2; /* 0x282884 0xA02884 */ + int Int_Level_3_1; /* 0x282888 0xA02888 */ + int Int_Level_3_0; /* 0x28288c 0xA0288c */ + int Int_Level_2_3; /* 0x282890 0xA02890 */ + int Int_Level_2_2; /* 0x282894 0xA02894 */ + int Int_Level_2_1; /* 0x282898 0xA02898 */ + int Int_Level_2_0; /* 0x28289c 0xA0289c */ + int Int_Level_1_3; /* 0x2828a0 0xA028a0 */ + int Int_Level_1_2; /* 0x2828a4 0xA028a4 */ + int Int_Level_1_1; /* 0x2828a8 0xA028a8 */ + int Int_Level_1_0; /* 0x2828ac 0xA028ac */ + int Int_Level_0_3; /* 0x2828b0 0xA028b0 */ + int Int_Level_0_2; /* 0x2828b4 0xA028b4 */ + int Int_Level_0_1; /* 0x2828b8 0xA028b8 */ + int Int_Level_0_0; /* 0x2828bc 0xA028bc */ + int Int_Docsis_En; /* 0x2828F4 0xA028F4 */ + + int MIPS_PLL_SETUP; /* 0x1a0000 0x980000 */ + int USB_FS; /* 0x1a0018 0x980030 */ + int Test_Bus; /* 0x1a0238 0x9800CC */ + int USB2_OHCI_IntMask; /* 0x1e000c 0x9A000c */ + int USB2_Strap; /* 0x1e0014 0x9A0014 */ + int EHCI_HCAPBASE; /* 0x1FFE00 0x9BFE00 */ + int OHCI_HcRevision; /* 0x1FFC00 0x9BFC00 */ + int BCM1_BS_LMI_STEER; /* 0x2C0008 0x9E0004 */ + int USB2_Control; /* 0x2c01a0 0x9E0054 */ + int USB2_STBUS_OBC; /* 0x1FFF00 0x9BFF00 */ + int USB2_STBUS_MESS_SIZE; /* 0x1FFF04 0x9BFF04 */ + int USB2_STBUS_CHUNK_SIZE; /* 0x1FFF08 0x9BFF08 */ + + int PCIe_Regs; /* 0x200000 0x000000 */ + int Free_Running_Ctr_Hi; /* 0x282C10 0xA02C10 */ + int Free_Running_Ctr_Lo; /* 0x282C14 0xA02C14 */ + int GPIO_DOUT; /* 0x282c20 0xA02c20 */ + int GPIO_DIN; /* 0x282c24 0xA02c24 */ + int GPIO_DIR; /* 0x282c2c 0xA02c2c */ + int Watchdog; /* 0x282c30 0xA02c30 */ + int Front_Panel; /* 0x283800 0x000000 */ + + int REGISTER_MAPS; +}; + +extern enum tAsicType gAsic; +extern const struct tRegisterMap *gRegisterMap; +extern unsigned long gAsicPhyBase; /* Physical address of ASIC */ +extern unsigned long pAsicBase; /* Virtual address of ASIC */ + +/* + * Macros to interface to registers through their ioremapped address + * asic_reg_offset Returns the offset of a given register from the start + * of the ASIC address space + * asic_reg_phys_addr Returns the physical address of the given register + * asic_reg_addr Returns the iomapped virtual address of the given + * register. + */ +#define asic_reg_offset(x) (gRegisterMap->x) +#define asic_reg_phys_addr(x) (gAsicPhyBase + asic_reg_offset(x)) +#define asic_reg_addr(x) ((unsigned int *) (pAsicBase + asic_reg_offset(x))) + +/* + * The asic_reg macro is gone. It should be replaced by either asic_read or + * asic_write, as appropriate. + */ + +#define asic_read(x) _asic_read(asic_reg_addr(x)) +#define asic_write(v, x) _asic_write(v, asic_reg_addr(x)) + +static inline unsigned int _asic_read(unsigned int *addr) +{ + return readl(addr); +} + +static inline void _asic_write(unsigned int value, unsigned int *addr) +{ + writel(value, addr); +} + +extern void asic_irq_init(void); +#endif diff --git a/arch/mips/include/asm/mach-powertv/dma-coherence.h b/arch/mips/include/asm/mach-powertv/dma-coherence.h new file mode 100644 index 0000000..b39f945 --- /dev/null +++ b/arch/mips/include/asm/mach-powertv/dma-coherence.h @@ -0,0 +1,123 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Version from mach-generic modified to support PowerTV port + * + * Copyright (C) 2006 Ralf Baechle + * + */ +#ifndef __ASM_MACH_GENERIC_DMA_COHERENCE_H +#define __ASM_MACH_GENERIC_DMA_COHERENCE_H + +#include +#include +#include + +struct device; + + +static inline bool is_kseg2(void *addr) +{ + return (unsigned long)addr >= KSEG2; +} + +static inline unsigned long virt_to_phys_from_pte(void *addr) +{ + pgd_t *pgd; + pud_t *pud; + pmd_t *pmd; + pte_t *ptep, pte; + + unsigned long virt_addr = (unsigned long)addr; + unsigned long phys_addr = 0UL; + + /* get the page global directory. */ + pgd = pgd_offset_k(virt_addr); + + if (!pgd_none(*pgd)) { + /* get the page upper directory */ + pud = pud_offset(pgd, virt_addr); + if (!pud_none(*pud)) { + /* get the page middle directory */ + pmd = pmd_offset(pud, virt_addr); + if (!pmd_none(*pmd)) { + /* get a pointer to the page table entry */ + ptep = pte_offset(pmd, virt_addr); + pte = *ptep; + /* check for a valid page */ + if (pte_present(pte)) { + /* get the physical address the page is + * refering to */ + phys_addr = (unsigned long) + page_to_phys(pte_page(pte)); + /* add the offset within the page */ + phys_addr |= (virt_addr & ~PAGE_MASK); + } + } + } + } + + return phys_addr; +} + +static inline dma_addr_t plat_map_dma_mem(struct device *dev, void *addr, + size_t size) +{ + if (is_kseg2(addr)) + return phys_to_bus(virt_to_phys_from_pte(addr)); + else + return phys_to_bus(virt_to_phys(addr)); +} + +static inline dma_addr_t plat_map_dma_mem_page(struct device *dev, + struct page *page) +{ + return phys_to_bus(page_to_phys(page)); +} + +static inline unsigned long plat_dma_addr_to_phys(dma_addr_t dma_addr) +{ + return bus_to_phys(dma_addr); +} + +static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr) +{ +} + +static inline int plat_dma_supported(struct device *dev, u64 mask) +{ + /* + * we fall back to GFP_DMA when the mask isn't all 1s, + * so we can't guarantee allocations that must be + * within a tighter range than GFP_DMA.. + */ + if (mask < DMA_BIT_MASK(24)) + return 0; + + return 1; +} + +static inline void plat_extra_sync_for_device(struct device *dev) +{ + return; +} + +static inline int plat_dma_mapping_error(struct device *dev, + dma_addr_t dma_addr) +{ + return 0; +} + +static inline int plat_device_is_coherent(struct device *dev) +{ +#ifdef CONFIG_DMA_COHERENT + return 1; +#endif +#ifdef CONFIG_DMA_NONCOHERENT + return 0; +#endif +} + +#endif /* __ASM_MACH_GENERIC_DMA_COHERENCE_H */ diff --git a/arch/mips/include/asm/mach-powertv/interrupts.h b/arch/mips/include/asm/mach-powertv/interrupts.h new file mode 100644 index 0000000..c37df64 --- /dev/null +++ b/arch/mips/include/asm/mach-powertv/interrupts.h @@ -0,0 +1,234 @@ +#ifndef _INTERRUPTS_H_ +#define _INTERRUPTS_H_ + + +/************************************************************* + * \brief Defines for all of the interrupt lines + *************************************************************/ + +#define kIBase 0 + +/*------------- Register: Int_Stat_3 */ +/* 126 unused (bit 31) */ +#define kIrq_ASC2Video (kIBase+126) /* ASC 2 Video Interrupt */ +#define kIrq_ASC1Video (kIBase+125) /* ASC 1 Video Interrupt */ +#define kIrq_COMMS_BlockWd (kIBase+124) /* ASC 1 Video Interrupt */ +#define kIrq_FDMA_Mailbox (kIBase+123) /* FDMA Mailbox Output */ +#define kIrq_FDMA_GP (kIBase+122) /* FDMA GP Output */ +#define kIrq_MipsPIC (kIBase+121) /* MIPS Performance Counter + * Interrupt */ +#define kIrq_MipsTimer (kIBase+120) /* MIPS Timer Interrupt */ +#define kIrq_Memory_Protect (kIBase+119) /* Memory Protection Interrupt + * -- Ored by glue logic inside + * SPARC ILC (see + * INT_MEM_PROT_STAT, below, + * for individual interrupts) + */ +/* 118 unused (bit 22) */ +#define kIrq_SBAG (kIBase+117) /* SBAG Interrupt -- Ored by + * glue logic inside SPARC ILC + * (see INT_SBAG_STAT, below, + * for individual interrupts) */ +#define kIrq_QamB_FEC (kIBase+116) /* QAM B FEC Interrupt */ +#define kIrq_QamA_FEC (kIBase+115) /* QAM A FEC Interrupt */ +/* 114 unused (bit 18) */ +#define kIrq_Mailbox (kIBase+113) /* Mailbox Debug Interrupt -- + * Ored by glue logic inside + * SPARC ILC (see + * INT_MAILBOX_STAT, below, for + * individual interrupts) */ +#define kIrq_FuseStat1 (kIBase+112) /* Fuse Status 1 */ +#define kIrq_FuseStat2 (kIBase+111) /* Fuse Status 2 */ +#define kIrq_FuseStat3 (kIBase+110) /* Blitter Interrupt / Fuse + * Status 3 */ +#define kIrq_Blitter (kIBase+110) /* Blitter Interrupt / Fuse + * Status 3 */ +#define kIrq_AVC1_PP0 (kIBase+109) /* AVC Decoder #1 PP0 + * Interrupt */ +#define kIrq_AVC1_PP1 (kIBase+108) /* AVC Decoder #1 PP1 + * Interrupt */ +#define kIrq_AVC1_MBE (kIBase+107) /* AVC Decoder #1 MBE + * Interrupt */ +#define kIrq_AVC2_PP0 (kIBase+106) /* AVC Decoder #2 PP0 + * Interrupt */ +#define kIrq_AVC2_PP1 (kIBase+105) /* AVC Decoder #2 PP1 + * Interrupt */ +#define kIrq_AVC2_MBE (kIBase+104) /* AVC Decoder #2 MBE + * Interrupt */ +#define kIrq_ZbugSpi (kIBase+103) /* Zbug SPI Slave Interrupt */ +#define kIrq_QAM_MOD2 (kIBase+102) /* QAM Modulator 2 DMA + * Interrupt */ +#define kIrq_IrRx (kIBase+101) /* IR RX 2 Interrupt */ +#define kIrq_AudDsp2 (kIBase+100) /* Audio DSP #2 Interrupt */ +#define kIrq_AudDsp1 (kIBase+99) /* Audio DSP #1 Interrupt */ +#define kIrq_Docsis (kIBase+98) /* DOCSIS Debug Interrupt */ +#define kIrq_SdDVP1 (kIBase+97) /* SD DVP #1 Interrupt */ +#define kIrq_SdDVP2 (kIBase+96) /* SD DVP #2 Interrupt */ +/*------------- Register: Int_Stat_2 */ +#define kIrq_HdDVP (kIBase+95) /* HD DVP Interrupt */ +#define kIrq_PreWatchdog (kIBase+94) /* Watchdog Pre-Interrupt */ +#define kIrq_Timer2 (kIBase+93) /* Programmable Timer + * Interrupt 2 */ +#define kIrq_1394 (kIBase+92) /* 1394 Firewire Interrupt */ +#define kIrq_USBOHCI (kIBase+91) /* USB 2.0 OHCI Interrupt */ +#define kIrq_USBEHCI (kIBase+90) /* USB 2.0 EHCI Interrupt */ +#define kIrq_PCIExp (kIBase+89) /* PCI Express 0 Interrupt */ +#define kIrq_PCIExp0 (kIBase+89) /* PCI Express 0 Interrupt */ +#define kIrq_AFE1 (kIBase+88) /* AFE 1 Interrupt */ +#define kIrq_SATA (kIBase+87) /* SATA 1 Interrupt */ +#define kIrq_SATA1 (kIBase+87) /* SATA 1 Interrupt */ +#define kIrq_DTCP (kIBase+86) /* DTCP Interrupt */ +#define kIrq_PCIExp1 (kIBase+85) /* PCI Express 1 Interrupt */ +/* 84 unused (bit 20) */ +/* 83 unused (bit 19) */ +/* 82 unused (bit 18) */ +#define kIrq_SATA2 (kIBase+81) /* SATA2 Interrupt */ +#define kIrq_Uart2 (kIBase+80) /* UART2 Interrupt */ +#define kIrq_LegacyUSB (kIBase+79) /* Legacy USB Host ISR (1.1 + * Host module) */ +#define kIrq_POD (kIBase+78) /* POD Interrupt */ +#define kIrq_SlaveUSB (kIBase+77) /* Slave USB */ +#define kIrq_Denc1 (kIBase+76) /* DENC #1 VTG Interrupt */ +#define kIrq_VbiVTG (kIBase+75) /* VBI VTG Interrupt */ +#define kIrq_AFE2 (kIBase+74) /* AFE 2 Interrupt */ +#define kIrq_Denc2 (kIBase+73) /* DENC #2 VTG Interrupt */ +#define kIrq_ASC2 (kIBase+72) /* ASC #2 Interrupt */ +#define kIrq_ASC1 (kIBase+71) /* ASC #1 Interrupt */ +#define kIrq_ModDMA (kIBase+70) /* Modulator DMA Interrupt */ +#define kIrq_ByteEng1 (kIBase+69) /* Byte Engine Interrupt [1] */ +#define kIrq_ByteEng0 (kIBase+68) /* Byte Engine Interrupt [0] */ +/* 67 unused (bit 03) */ +/* 66 unused (bit 02) */ +/* 65 unused (bit 01) */ +/* 64 unused (bit 00) */ +/*------------- Register: Int_Stat_1 */ +/* 63 unused (bit 31) */ +/* 62 unused (bit 30) */ +/* 61 unused (bit 29) */ +/* 60 unused (bit 28) */ +/* 59 unused (bit 27) */ +/* 58 unused (bit 26) */ +/* 57 unused (bit 25) */ +/* 56 unused (bit 24) */ +#define kIrq_BufDMA_Mem2Mem (kIBase+55) /* BufDMA Memory to Memory + * Interrupt */ +#define kIrq_BufDMA_USBTransmit (kIBase+54) /* BufDMA USB Transmit + * Interrupt */ +#define kIrq_BufDMA_QPSKPODTransmit (kIBase+53) /* BufDMA QPSK/POD Tramsit + * Interrupt */ +#define kIrq_BufDMA_TransmitError (kIBase+52) /* BufDMA Transmit Error + * Interrupt */ +#define kIrq_BufDMA_USBRecv (kIBase+51) /* BufDMA USB Receive + * Interrupt */ +#define kIrq_BufDMA_QPSKPODRecv (kIBase+50) /* BufDMA QPSK/POD Receive + * Interrupt */ +#define kIrq_BufDMA_RecvError (kIBase+49) /* BufDMA Receive Error + * Interrupt */ +#define kIrq_QAMDMA_TransmitPlay (kIBase+48) /* QAMDMA Transmit/Play + * Interrupt */ +#define kIrq_QAMDMA_TransmitError (kIBase+47) /* QAMDMA Transmit Error + * Interrupt */ +#define kIrq_QAMDMA_Recv2High (kIBase+46) /* QAMDMA Receive 2 High + * (Chans 63-32) */ +#define kIrq_QAMDMA_Recv2Low (kIBase+45) /* QAMDMA Receive 2 Low + * (Chans 31-0) */ +#define kIrq_QAMDMA_Recv1High (kIBase+44) /* QAMDMA Receive 1 High + * (Chans 63-32) */ +#define kIrq_QAMDMA_Recv1Low (kIBase+43) /* QAMDMA Receive 1 Low + * (Chans 31-0) */ +#define kIrq_QAMDMA_RecvError (kIBase+42) /* QAMDMA Receive Error + * Interrupt */ +#define kIrq_MPEGSplice (kIBase+41) /* MPEG Splice Interrupt */ +#define kIrq_DeinterlaceRdy (kIBase+40) /* Deinterlacer Frame Ready + * Interrupt */ +#define kIrq_ExtIn0 (kIBase+39) /* External Interrupt irq_in0 */ +#define kIrq_Gpio3 (kIBase+38) /* GP I/O IRQ 3 - From GP I/O + * Module */ +#define kIrq_Gpio2 (kIBase+37) /* GP I/O IRQ 2 - From GP I/O + * Module (ABE_intN) */ +#define kIrq_PCRCmplt1 (kIBase+36) /* PCR Capture Complete or + * Discontinuity 1 */ +#define kIrq_PCRCmplt2 (kIBase+35) /* PCR Capture Complete or + * Discontinuity 2 */ +#define kIrq_ParsePEIErr (kIBase+34) /* PID Parser Error Detect + * (PEI) */ +#define kIrq_ParseContErr (kIBase+33) /* PID Parser continuity error + * detect */ +#define kIrq_DS1Framer (kIBase+32) /* DS1 Framer Interrupt */ +/*------------- Register: Int_Stat_0 */ +#define kIrq_Gpio1 (kIBase+31) /* GP I/O IRQ 1 - From GP I/O + * Module */ +#define kIrq_Gpio0 (kIBase+30) /* GP I/O IRQ 0 - From GP I/O + * Module */ +#define kIrq_QpskOutAloha (kIBase+29) /* QPSK Output Slotted Aloha + * (chan 3) Transmission + * Completed OK */ +#define kIrq_QpskOutTdma (kIBase+28) /* QPSK Output TDMA (chan 2) + * Transmission Completed OK */ +#define kIrq_QpskOutReserve (kIBase+27) /* QPSK Output Reservation + * (chan 1) Transmission + * Completed OK */ +#define kIrq_QpskOutAlohaErr (kIBase+26) /* QPSK Output Slotted Aloha + * (chan 3)Transmission + * completed with Errors. */ +#define kIrq_QpskOutTdmaErr (kIBase+25) /* QPSK Output TDMA (chan 2) + * Transmission completed with + * Errors. */ +#define kIrq_QpskOutRsrvErr (kIBase+24) /* QPSK Output Reservation + * (chan 1) Transmission + * completed with Errors */ +#define kIrq_AlohaFail (kIBase+23) /* Unsuccessful Resend of Aloha + * for N times. Aloha retry + * timeout for channel 3. */ +#define kIrq_Timer1 (kIBase+22) /* Programmable Timer + * Interrupt */ +#define kIrq_Keyboard (kIBase+21) /* Keyboard Module Interrupt */ +#define kIrq_I2c (kIBase+20) /* I2C Module Interrupt */ +#define kIrq_Spi (kIBase+19) /* SPI Module Interrupt */ +#define kIrq_IRBlaster (kIBase+18) /* IR Blaster Interrupt */ +#define kIrq_SpliceDetect (kIBase+17) /* PID Key Change Interrupt or + * Splice Detect Interrupt */ +#define kIrq_SeMicro (kIBase+16) /* Secure Micro I/F Module + * Interrupt */ +#define kIrq_Uart1 (kIBase+15) /* UART Interrupt */ +#define kIrq_IRrecv (kIBase+14) /* IR Receiver Interrupt */ +#define kIrq_HostInt1 (kIBase+13) /* Host-to-Host Interrupt 1 */ +#define kIrq_HostInt0 (kIBase+12) /* Host-to-Host Interrupt 0 */ +#define kIrq_QpskHECErr (kIBase+11) /* QPSK HEC Error Interrupt */ +#define kIrq_QpskCRCErr (kIBase+10) /* QPSK AAL-5 CRC Error + * Interrupt */ +/* 9 unused (bit 09) */ +/* 8 unused (bit 08) */ +#define kIrq_PSICRCErr (kIBase+7) /* QAM PSI CRC Error + * Interrupt */ +#define kIrq_PSILengthErr (kIBase+6) /* QAM PSI Length Error + * Interrupt */ +#define kIrq_ESFForward (kIBase+5) /* ESF Interrupt Mark From + * Forward Path Reference - + * every 3ms when forward Mbits + * and forward slot control + * bytes are updated. */ +#define kIrq_ESFReverse (kIBase+4) /* ESF Interrupt Mark from + * Reverse Path Reference - + * delayed from forward mark by + * the ranging delay plus a + * fixed amount. When reverse + * Mbits and reverse slot + * control bytes are updated. + * Occurs every 3ms for 3.0M and + * 1.554 M upstream rates and + * every 6 ms for 256K upstream + * rate. */ +#define kIrq_AlohaTimeout (kIBase+3) /* Slotted-Aloha timeout on + * Channel 1. */ +#define kIrq_Reservation (kIBase+2) /* Partial (or Incremental) + * Reservation Message Completed + * or Slotted aloha verify for + * channel 1. */ +#define kIrq_Aloha3 (kIBase+1) /* Slotted-Aloha Message Verify + * Interrupt or Reservation + * increment completed for + * channel 3. */ +#define kIrq_MpegD (kIBase+0) /* MPEG Decoder Interrupt */ +#endif /* _INTERRUPTS_H_ */ + diff --git a/arch/mips/include/asm/mach-powertv/war.h b/arch/mips/include/asm/mach-powertv/war.h new file mode 100644 index 0000000..2f4a155 --- /dev/null +++ b/arch/mips/include/asm/mach-powertv/war.h @@ -0,0 +1,27 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * This version for the PowerTV platform copied from the Malta version. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle + */ +#ifndef __ASM_MIPS_MACH_MIPS_WAR_H +#define __ASM_MIPS_MACH_MIPS_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 1 +#define MIPS_CACHE_SYNC_WAR 1 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 1 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MIPS_MACH_MIPS_WAR_H */ diff --git a/arch/mips/powertv/Kconfig b/arch/mips/powertv/Kconfig new file mode 100644 index 0000000..ada1732 --- /dev/null +++ b/arch/mips/powertv/Kconfig @@ -0,0 +1,17 @@ +source "arch/mips/powertv/asic/Kconfig" + +config BOOTLOADER_DRIVER + bool "PowerTV Bootloader Driver Support" + default n + depends on POWERTV + help + Use this option if you want to load bootloader driver. + +config BOOTLOADER_FAMILY + string "POWERTV Bootloader Family string" + default "85" + depends on POWERTV && !BOOTLOADER_DRIVER + help + This value should be specified when the bootloader driver is disabled + and must be exactly two characters long. + diff --git a/arch/mips/powertv/Makefile b/arch/mips/powertv/Makefile new file mode 100644 index 0000000..87886e0 --- /dev/null +++ b/arch/mips/powertv/Makefile @@ -0,0 +1,37 @@ +# +# Carsten Langgaard, carstenl@mips.com +# Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. +# +# Carsten Langgaard, carstenl@mips.com +# Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. +# +# This program is free software; you can distribute it and/or modify it +# under the terms of the GNU General Public License (Version 2) as +# published by the Free Software Foundation. +# +# This program is distributed in the hope it will be useful, but WITHOUT +# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License +# for more details. +# +# You should have received a copy of the GNU General Public License along +# with this program; if not, write to the Free Software Foundation, Inc., +# 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. +# +# Makefile for the MIPS Malta specific kernel interface routines +# under Linux. +# + +obj-y := + +obj-$(CONFIG_POWERTV) += cmdline.o \ + init.o \ + memory.o \ + reset.o \ + time.o \ + powertv_setup.o \ + asic/ \ + pci/ + +obj-$(CONFIG_CEVT_POWERTV) += cevt-powertv.o +obj-$(CONFIG_CSRC_POWERTV) += csrc-powertv.o diff --git a/arch/mips/powertv/asic/Kconfig b/arch/mips/powertv/asic/Kconfig new file mode 100644 index 0000000..48b85ea --- /dev/null +++ b/arch/mips/powertv/asic/Kconfig @@ -0,0 +1,24 @@ +config MIN_RUNTIME_RESOURCES + bool "Support for minimum runtime resources" + depends on POWERTV + help + Enables support for minimizing the number of (SA asic) runtime + resources that are preallocated by the kernel. + +config MIN_RUNTIME_DOCSIS + bool "Support for minimum DOCSIS resource" + depends on MIN_RUNTIME_RESOURCES + help + Enables support for the preallocated DOCSIS resource. + +config MIN_RUNTIME_PMEM + bool "Support for minimum PMEM resource" + depends on MIN_RUNTIME_RESOURCES + help + Enables support for the preallocated Memory resource. + +config MIN_RUNTIME_TFTP + bool "Support for minimum TFTP resource" + depends on MIN_RUNTIME_RESOURCES + help + Enables support for the preallocated TFTP resource. diff --git a/arch/mips/powertv/asic/Makefile b/arch/mips/powertv/asic/Makefile new file mode 100644 index 0000000..52d4336 --- /dev/null +++ b/arch/mips/powertv/asic/Makefile @@ -0,0 +1,24 @@ +# ***************************************************************************** +# Make file for PowerTV Asic related files +# +# Copyright (C) 2009 Scientific-Atlanta, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# +# ***************************************************************************** + +obj-y := + +obj-$(CONFIG_POWERTV) += irq_asic.o asic_devices.o asic_int.o diff --git a/arch/mips/powertv/asic/asic_devices.c b/arch/mips/powertv/asic/asic_devices.c new file mode 100644 index 0000000..2e67979 --- /dev/null +++ b/arch/mips/powertv/asic/asic_devices.c @@ -0,0 +1,2902 @@ +/**************************************************************************** + * ASIC Device List Intialization + * + * Copyright (C) 2005-2009 Scientific-Atlanta, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + ***************************************************************************** + * + * File Name: asic_devices.c + * + * See Also: + * + * Project: SA explorer settops + * + * Compiler: + * + * Author: Ken Eppinett + * David Schleef + * + * Description: Defines the platform resources for the SA settop. + * + * NOTE: The bootloader allocates persistent memory at an address which is + * 16 MiB below the end of the highest address in KSEG0. All fixed + * address memory reservations must avoid this region. + * + ***************************************************************************** + * History: + * Rev Level Date Name ECN# Description + *---------------------------------------------------------------------------- + * 1.0 Eppinett initial version + ****************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#ifdef CONFIG_BOOTLOADER_DRIVER +#include +#endif + +/****************************************************************************** + * Forward Prototypes + *****************************************************************************/ +static void pmem_setup_resource(void); + +/****************************************************************************** + * Global Variables + *****************************************************************************/ +enum tAsicType gAsic; + +unsigned int gPlatformFeatures; +unsigned int gPlatformFamily; +const struct tRegisterMap *gRegisterMap; +EXPORT_SYMBOL(gRegisterMap); /* Exported for testing */ +unsigned long gAsicPhyBase; +unsigned long pAsicBase; +EXPORT_SYMBOL(pAsicBase); /* Exported for testing */ +struct resource *gpResources; +static bool usb_configured; + +/* + * Don't recommend to use it directly, it is usually used by kernel internally. + * Portable code should be using interfaces such as ioremp, dma_map_single, etc. + */ +unsigned long gPhysToBusOffset; +EXPORT_SYMBOL(gPhysToBusOffset); + +static const struct tRegisterMap zeus_register_map = { + .EIC_SLOW0_STRT_ADD = 0x000000, + .EIC_CFG_BITS = 0x000038, + .EIC_READY_STATUS = 0x00004c, + + .CHIPVER3 = 0x280800, + .CHIPVER2 = 0x280804, + .CHIPVER1 = 0x280808, + .CHIPVER0 = 0x28080c, + + /* The registers of IRBlaster */ + .UART1_INTSTAT = 0x281800, + .UART1_INTEN = 0x281804, + .UART1_CONFIG1 = 0x281808, + .UART1_CONFIG2 = 0x28180C, + .UART1_DIVISORHI = 0x281810, + .UART1_DIVISORLO = 0x281814, + .UART1_DATA = 0x281818, + .UART1_STATUS = 0x28181C, + + .Int_Stat_3 = 0x282800, + .Int_Stat_2 = 0x282804, + .Int_Stat_1 = 0x282808, + .Int_Stat_0 = 0x28280c, + .Int_Config = 0x282810, + .Int_Int_Scan = 0x282818, + .Ien_Int_3 = 0x282830, + .Ien_Int_2 = 0x282834, + .Ien_Int_1 = 0x282838, + .Ien_Int_0 = 0x28283c, + .Int_Level_3_3 = 0x282880, + .Int_Level_3_2 = 0x282884, + .Int_Level_3_1 = 0x282888, + .Int_Level_3_0 = 0x28288c, + .Int_Level_2_3 = 0x282890, + .Int_Level_2_2 = 0x282894, + .Int_Level_2_1 = 0x282898, + .Int_Level_2_0 = 0x28289c, + .Int_Level_1_3 = 0x2828a0, + .Int_Level_1_2 = 0x2828a4, + .Int_Level_1_1 = 0x2828a8, + .Int_Level_1_0 = 0x2828ac, + .Int_Level_0_3 = 0x2828b0, + .Int_Level_0_2 = 0x2828b4, + .Int_Level_0_1 = 0x2828b8, + .Int_Level_0_0 = 0x2828bc, + .Int_Docsis_En = 0x2828F4, + + .MIPS_PLL_SETUP = 0x1a0000, + .USB_FS = 0x1a0018, + .Test_Bus = 0x1a0238, + .USB2_OHCI_IntMask = 0x1e000c, + .USB2_Strap = 0x1e0014, + .EHCI_HCAPBASE = 0x1FFE00, + .OHCI_HcRevision = 0x1FFC00, + .BCM1_BS_LMI_STEER = 0x2C0008, + .USB2_Control = 0x2c01a0, + .USB2_STBUS_OBC = 0x1FFF00, + .USB2_STBUS_MESS_SIZE = 0x1FFF04, + .USB2_STBUS_CHUNK_SIZE = 0x1FFF08, + + .PCIe_Regs = 0x200000, + .Free_Running_Ctr_Hi = 0x282C10, + .Free_Running_Ctr_Lo = 0x282C14, + .GPIO_DOUT = 0x282c20, + .GPIO_DIN = 0x282c24, + .GPIO_DIR = 0x282c2C, + .Watchdog = 0x282c30, + .Front_Panel = 0x283800, +}; + +static const struct tRegisterMap calliope_register_map = { + .EIC_SLOW0_STRT_ADD = 0x800000, + .EIC_CFG_BITS = 0x800038, + .EIC_READY_STATUS = 0x80004c, + + .CHIPVER3 = 0xA00800, + .CHIPVER2 = 0xA00804, + .CHIPVER1 = 0xA00808, + .CHIPVER0 = 0xA0080c, + + /* The registers of IRBlaster */ + .UART1_INTSTAT = 0xA01800, + .UART1_INTEN = 0xA01804, + .UART1_CONFIG1 = 0xA01808, + .UART1_CONFIG2 = 0xA0180C, + .UART1_DIVISORHI = 0xA01810, + .UART1_DIVISORLO = 0xA01814, + .UART1_DATA = 0xA01818, + .UART1_STATUS = 0xA0181C, + + .Int_Stat_3 = 0xA02800, + .Int_Stat_2 = 0xA02804, + .Int_Stat_1 = 0xA02808, + .Int_Stat_0 = 0xA0280c, + .Int_Config = 0xA02810, + .Int_Int_Scan = 0xA02818, + .Ien_Int_3 = 0xA02830, + .Ien_Int_2 = 0xA02834, + .Ien_Int_1 = 0xA02838, + .Ien_Int_0 = 0xA0283c, + .Int_Level_3_3 = 0xA02880, + .Int_Level_3_2 = 0xA02884, + .Int_Level_3_1 = 0xA02888, + .Int_Level_3_0 = 0xA0288c, + .Int_Level_2_3 = 0xA02890, + .Int_Level_2_2 = 0xA02894, + .Int_Level_2_1 = 0xA02898, + .Int_Level_2_0 = 0xA0289c, + .Int_Level_1_3 = 0xA028a0, + .Int_Level_1_2 = 0xA028a4, + .Int_Level_1_1 = 0xA028a8, + .Int_Level_1_0 = 0xA028ac, + .Int_Level_0_3 = 0xA028b0, + .Int_Level_0_2 = 0xA028b4, + .Int_Level_0_1 = 0xA028b8, + .Int_Level_0_0 = 0xA028bc, + .Int_Docsis_En = 0xA028F4, + + .MIPS_PLL_SETUP = 0x980000, + .USB_FS = 0x980030, /* -default 72800028- */ + .Test_Bus = 0x9800CC, + .USB2_OHCI_IntMask = 0x9A000c, + .USB2_Strap = 0x9A0014, + .EHCI_HCAPBASE = 0x9BFE00, + .OHCI_HcRevision = 0x9BFC00, + .BCM1_BS_LMI_STEER = 0x9E0004, + .USB2_Control = 0x9E0054, + .USB2_STBUS_OBC = 0x9BFF00, + .USB2_STBUS_MESS_SIZE = 0x9BFF04, + .USB2_STBUS_CHUNK_SIZE = 0x9BFF08, + + .PCIe_Regs = 0x000000, /* -doesn't exist- */ + .Free_Running_Ctr_Hi = 0xA02C10, + .Free_Running_Ctr_Lo = 0xA02C14, + .GPIO_DOUT = 0xA02c20, + .GPIO_DIN = 0xA02c24, + .GPIO_DIR = 0xA02c2C, + .Watchdog = 0xA02c30, + .Front_Panel = 0x000000, /* -not used- */ +}; + +static const struct tRegisterMap cronus_register_map = { + .EIC_SLOW0_STRT_ADD = 0x000000, + .EIC_CFG_BITS = 0x000038, + .EIC_READY_STATUS = 0x00004C, + + .CHIPVER3 = 0x2A0800, + .CHIPVER2 = 0x2A0804, + .CHIPVER1 = 0x2A0808, + .CHIPVER0 = 0x2A080C, + + /* The registers of IRBlaster */ + .UART1_INTSTAT = 0x2A1800, + .UART1_INTEN = 0x2A1804, + .UART1_CONFIG1 = 0x2A1808, + .UART1_CONFIG2 = 0x2A180C, + .UART1_DIVISORHI = 0x2A1810, + .UART1_DIVISORLO = 0x2A1814, + .UART1_DATA = 0x2A1818, + .UART1_STATUS = 0x2A181C, + + .Int_Stat_3 = 0x2A2800, + .Int_Stat_2 = 0x2A2804, + .Int_Stat_1 = 0x2A2808, + .Int_Stat_0 = 0x2A280C, + .Int_Config = 0x2A2810, + .Int_Int_Scan = 0x2A2818, + .Ien_Int_3 = 0x2A2830, + .Ien_Int_2 = 0x2A2834, + .Ien_Int_1 = 0x2A2838, + .Ien_Int_0 = 0x2A283C, + .Int_Level_3_3 = 0x2A2880, + .Int_Level_3_2 = 0x2A2884, + .Int_Level_3_1 = 0x2A2888, + .Int_Level_3_0 = 0x2A288C, + .Int_Level_2_3 = 0x2A2890, + .Int_Level_2_2 = 0x2A2894, + .Int_Level_2_1 = 0x2A2898, + .Int_Level_2_0 = 0x2A289C, + .Int_Level_1_3 = 0x2A28A0, + .Int_Level_1_2 = 0x2A28A4, + .Int_Level_1_1 = 0x2A28A8, + .Int_Level_1_0 = 0x2A28AC, + .Int_Level_0_3 = 0x2A28B0, + .Int_Level_0_2 = 0x2A28B4, + .Int_Level_0_1 = 0x2A28B8, + .Int_Level_0_0 = 0x2A28BC, + .Int_Docsis_En = 0x2A28F4, + + .MIPS_PLL_SETUP = 0x1C0000, + .USB_FS = 0x1C0018, + .Test_Bus = 0x1C00CC, + .USB2_OHCI_IntMask = 0x20000C, + .USB2_Strap = 0x200014, + .EHCI_HCAPBASE = 0x21FE00, + .OHCI_HcRevision = 0x1E0000, + .BCM1_BS_LMI_STEER = 0x2E0008, + .USB2_Control = 0x2E004C, + .USB2_STBUS_OBC = 0x21FF00, + .USB2_STBUS_MESS_SIZE = 0x21FF04, + .USB2_STBUS_CHUNK_SIZE = 0x21FF08, + + .PCIe_Regs = 0x220000, + .Free_Running_Ctr_Hi = 0x2A2C10, + .Free_Running_Ctr_Lo = 0x2A2C14, + .GPIO_DOUT = 0x2A2C20, + .GPIO_DIN = 0x2A2C24, + .GPIO_DIR = 0x2A2C2C, + .Watchdog = 0x2A2C30, + .Front_Panel = 0x2A3800, +}; + +/****************************************************************************** + * DVR_CAPABLE RESOURCES + *****************************************************************************/ +struct resource dvr_zeus_resources[] = +{ + /********************************************************************** + * + * VIDEO1 / LX1 + * + *********************************************************************/ + { + .name = "ST231aImage", /* Delta-Mu 1 image and ram */ + .start = 0x20000000, + .end = 0x201FFFFF, /* 2MiB */ + .flags = IORESOURCE_IO, + }, + { + .name = "ST231aMonitor", /* 8KiB block ST231a monitor */ + .start = 0x20200000, + .end = 0x20201FFF, + .flags = IORESOURCE_IO, + }, + { + .name = "MediaMemory1", + .start = 0x20202000, + .end = 0x21FFFFFF, /*~29.9MiB (32MiB - (2MiB + 8KiB)) */ + .flags = IORESOURCE_IO, + }, + /********************************************************************** + * + * VIDEO2 / LX2 + * + *********************************************************************/ + { + .name = "ST231bImage", /* Delta-Mu 2 image and ram */ + .start = 0x30000000, + .end = 0x301FFFFF, /* 2MiB */ + .flags = IORESOURCE_IO, + }, + { + .name = "ST231bMonitor", /* 8KiB block ST231b monitor */ + .start = 0x30200000, + .end = 0x30201FFF, + .flags = IORESOURCE_IO, + }, + { + .name = "MediaMemory2", + .start = 0x30202000, + .end = 0x31FFFFFF, /*~29.9MiB (32MiB - (2MiB + 8KiB)) */ + .flags = IORESOURCE_IO, + }, + /********************************************************************** + * + * Sysaudio Driver + * + * This driver requires: + * + * Arbitrary Based Buffers: + * DSP_Image_Buff - DSP code and data images (1MB) + * ADSC_CPU_PCM_Buff - ADSC CPU PCM buffer (40KB) + * ADSC_AUX_Buff - ADSC AUX buffer (16KB) + * ADSC_Main_Buff - ADSC Main buffer (16KB) + * + *********************************************************************/ + { + .name = "DSP_Image_Buff", + .start = 0x00000000, + .end = 0x000FFFFF, + .flags = IORESOURCE_MEM, + }, + { + .name = "ADSC_CPU_PCM_Buff", + .start = 0x00000000, + .end = 0x00009FFF, + .flags = IORESOURCE_MEM, + }, + { + .name = "ADSC_AUX_Buff", + .start = 0x00000000, + .end = 0x00003FFF, + .flags = IORESOURCE_MEM, + }, + { + .name = "ADSC_Main_Buff", + .start = 0x00000000, + .end = 0x00003FFF, + .flags = IORESOURCE_MEM, + }, + /********************************************************************** + * + * STAVEM driver/STAPI + * + * This driver requires: + * + * Arbitrary Based Buffers: + * This memory area is used for allocating buffers for Video decoding + * purposes. Allocation/De-allocation within this buffer is managed + * by the STAVMEM driver of the STAPI. They could be Decimated + * Picture Buffers, Intermediate Buffers, as deemed necessary for + * video decoding purposes, for any video decoders on Zeus. + * + *********************************************************************/ + { + .name = "AVMEMPartition0", + .start = 0x00000000, + .end = 0x00c00000 - 1, /* 12 MB total */ + .flags = IORESOURCE_MEM, + }, + /********************************************************************** + * + * DOCSIS Subsystem + * + * This driver requires: + * + * Arbitrary Based Buffers: + * Docsis - + * + *********************************************************************/ + { + .name = "Docsis", + .start = 0x40100000, + .end = 0x407fffff, + .flags = IORESOURCE_MEM, + }, + /********************************************************************** + * + * GHW HAL Driver + * + * This driver requires: + * + * Arbitrary Based Buffers: + * GraphicsHeap - PowerTV Graphics Heap + * + *********************************************************************/ + { + .name = "GraphicsHeap", + .start = 0x46900000, + .end = 0x47700000 - 1, /* 14 MB total */ + .flags = IORESOURCE_MEM, + }, + /********************************************************************** + * + * multi com buffer area + * + * This driver requires: + * + * Arbitrary Based Buffers: + * Docsis - + * + *********************************************************************/ + { + .name = "MulticomSHM", + .start = 0x47900000, + .end = 0x47920000 - 1, + .flags = IORESOURCE_MEM, + }, + /********************************************************************** + * + * DMA Ring buffer + * + * This driver requires: + * + * Arbitrary Based Buffers: + * Docsis - + * + *********************************************************************/ + { + .name = "BMM_Buffer", + .start = 0x00000000, + .end = 0x00280000 - 1, + .flags = IORESOURCE_MEM, + }, + /********************************************************************** + * + * Display bins buffer for unit0 + * + * This driver requires: + * + * Arbitrary Based Buffers: + * Display Bins for unit0 + * + *********************************************************************/ + { + .name = "DisplayBins0", + .start = 0x00000000, + .end = 0x00000FFF, /* 4 KB total */ + .flags = IORESOURCE_MEM, + }, + /********************************************************************** + * + * Display bins buffer + * + * This driver requires: + * + * Arbitrary Based Buffers: + * Display Bins for unit1 + * + *********************************************************************/ + { + .name = "DisplayBins1", + .start = 0x00000000, + .end = 0x00000FFF, /* 4 KB total */ + .flags = IORESOURCE_MEM, + }, + /********************************************************************** + * + * ITFS + * + * This driver requires: + * + * Arbitrary Based Buffers: + * Docsis - + * + *********************************************************************/ + { + .name = "ITFS", + .start = 0x00000000, + /* 815,104 bytes each for 2 ITFS partitions. */ + .end = 0x0018DFFF, + .flags = IORESOURCE_MEM, + }, + /********************************************************************** + * + * AVFS + * + * This driver requires: + * + * Arbitrary Based Buffers: + * Docsis - + * + *********************************************************************/ + { + .name = "AvfsDmaMem", + .start = 0x00000000, + /* (945K * 8) = (128K * 3) 5 playbacks / 3 server */ + .end = 0x007c2000 - 1, + .flags = IORESOURCE_MEM, + }, + { + .name = "AvfsFileSys", + .start = 0x00000000, + .end = 0x00001000 - 1, /* 4K */ + .flags = IORESOURCE_MEM, + }, + /********************************************************************** + * + * PMEM + * + * This driver requires: + * + * Arbitrary Based Buffers: + * Persistent memory for diagnostics. + * + *********************************************************************/ + { + .name = "DiagPersistentMemory", + .start = 0x00000000, + .end = 0x10000 - 1, + .flags = IORESOURCE_MEM, + }, + /********************************************************************** + * + * Smartcard + * + * This driver requires: + * + * Arbitrary Based Buffers: + * Read and write buffers for Internal/External cards + * + *********************************************************************/ + { + .name = "SmartCardInfo", + .start = 0x00000000, + .end = 0x2800 - 1, + .flags = IORESOURCE_MEM, + }, + /********************************************************************** + * Add other resources here + */ + /* + * End of Resource marker + * + *********************************************************************/ + { + .flags = 0, + }, +}; + +/****************************************************************************** + * NON_DVR_CAPABLE ZEUS RESOURCES + *****************************************************************************/ +struct resource non_dvr_zeus_resources[] = +{ + /********************************************************************** + * VIDEO1 / LX1 + *********************************************************************/ + { + .name = "ST231aImage", /* Delta-Mu 1 image and ram */ + .start = 0x20000000, + .end = 0x201FFFFF, /* 2MiB */ + .flags = IORESOURCE_IO, + }, + { + .name = "ST231aMonitor", /* 8KiB block ST231a monitor */ + .start = 0x20200000, + .end = 0x20201FFF, + .flags = IORESOURCE_IO, + }, + { + .name = "MediaMemory1", + .start = 0x20202000, + .end = 0x21FFFFFF, /*~29.9MiB (32MiB - (2MiB + 8KiB)) */ + .flags = IORESOURCE_IO, + }, + /********************************************************************** + * Sysaudio Driver + *********************************************************************/ + { + .name = "DSP_Image_Buff", + .start = 0x00000000, + .end = 0x000FFFFF, + .flags = IORESOURCE_MEM, + }, + { + .name = "ADSC_CPU_PCM_Buff", + .start = 0x00000000, + .end = 0x00009FFF, + .flags = IORESOURCE_MEM, + }, + { + .name = "ADSC_AUX_Buff", + .start = 0x00000000, + .end = 0x00003FFF, + .flags = IORESOURCE_MEM, + }, + { + .name = "ADSC_Main_Buff", + .start = 0x00000000, + .end = 0x00003FFF, + .flags = IORESOURCE_MEM, + }, + /********************************************************************** + * STAVEM driver/STAPI + *********************************************************************/ + { + .name = "AVMEMPartition0", + .start = 0x00000000, + .end = 0x00600000 - 1, /* 6 MB total */ + .flags = IORESOURCE_MEM, + }, + /********************************************************************** + * DOCSIS Subsystem + *********************************************************************/ + { + .name = "Docsis", + .start = 0x40100000, + .end = 0x407fffff, + .flags = IORESOURCE_MEM, + }, + /********************************************************************** + * GHW HAL Driver + *********************************************************************/ + { + .name = "GraphicsHeap", + .start = 0x46900000, + .end = 0x47700000 - 1, /* 14 MB total */ + .flags = IORESOURCE_MEM, + }, + /********************************************************************** + * multi com buffer area + *********************************************************************/ + { + .name = "MulticomSHM", + .start = 0x47900000, + .end = 0x47920000 - 1, + .flags = IORESOURCE_MEM, + }, + /********************************************************************** + * DMA Ring buffer + *********************************************************************/ + { + .name = "BMM_Buffer", + .start = 0x00000000, + .end = 0x00280000 - 1, + .flags = IORESOURCE_MEM, + }, + /********************************************************************** + * Display bins buffer for unit0 + *********************************************************************/ + { + .name = "DisplayBins0", + .start = 0x00000000, + .end = 0x00000FFF, /* 4 KB total */ + .flags = IORESOURCE_MEM, + }, + /********************************************************************** + * + * AVFS: player HAL memory + * + * + *********************************************************************/ + { + .name = "AvfsDmaMem", + .start = 0x00000000, + .end = 0x002c4c00 - 1, /* 945K * 3 for playback */ + .flags = IORESOURCE_MEM, + }, + /********************************************************************** + * PMEM + *********************************************************************/ + { + .name = "DiagPersistentMemory", + .start = 0x00000000, + .end = 0x10000 - 1, + .flags = IORESOURCE_MEM, + }, + /********************************************************************** + * Smartcard + *********************************************************************/ + { + .name = "SmartCardInfo", + .start = 0x00000000, + .end = 0x2800 - 1, + .flags = IORESOURCE_MEM, + }, + /********************************************************************** + * NAND Flash + *********************************************************************/ + { + .name = "NandFlash", + .start = NAND_FLASH_BASE, + .end = NAND_FLASH_BASE + 0x400 - 1, + .flags = IORESOURCE_IO, + }, + /********************************************************************** + * Add other resources here + * + * End of Resource marker + *********************************************************************/ + { + .flags = 0, + }, +}; + +/****************************************************************************** + * NON_DVR_CAPABLE CALLIOPE RESOURCES + *****************************************************************************/ +struct resource non_dvr_calliope_resources[] = +{ + /********************************************************************** + * VIDEO / LX1 + *********************************************************************/ + { + .name = "ST231aImage", /* Delta-Mu 1 image and ram */ + .start = 0x24000000, + .end = 0x24200000 - 1, /*2MiB */ + .flags = IORESOURCE_MEM, + }, + { + .name = "ST231aMonitor", /*8KiB block ST231a monitor */ + .start = 0x24200000, + .end = 0x24202000 - 1, + .flags = IORESOURCE_MEM, + }, + { + .name = "MediaMemory1", + .start = 0x24202000, + .end = 0x26700000 - 1, /*~36.9MiB (32MiB - (2MiB + 8KiB)) */ + .flags = IORESOURCE_MEM, + }, + /********************************************************************** + * Sysaudio Driver + *********************************************************************/ + { + .name = "DSP_Image_Buff", + .start = 0x00000000, + .end = 0x000FFFFF, + .flags = IORESOURCE_MEM, + }, + { + .name = "ADSC_CPU_PCM_Buff", + .start = 0x00000000, + .end = 0x00009FFF, + .flags = IORESOURCE_MEM, + }, + { + .name = "ADSC_AUX_Buff", + .start = 0x00000000, + .end = 0x00003FFF, + .flags = IORESOURCE_MEM, + }, + { + .name = "ADSC_Main_Buff", + .start = 0x00000000, + .end = 0x00003FFF, + .flags = IORESOURCE_MEM, + }, + /********************************************************************** + * STAVEM driver/STAPI + *********************************************************************/ + { + .name = "AVMEMPartition0", + .start = 0x00000000, + .end = 0x00600000 - 1, /* 6 MB total */ + .flags = IORESOURCE_MEM, + }, + /********************************************************************** + * DOCSIS Subsystem + *********************************************************************/ + { + .name = "Docsis", + .start = 0x22000000, + .end = 0x22700000 - 1, + .flags = IORESOURCE_MEM, + }, + /********************************************************************** + * GHW HAL Driver + *********************************************************************/ + { + .name = "GraphicsHeap", + .start = 0x22700000, + .end = 0x23500000 - 1, /* 14 MB total */ + .flags = IORESOURCE_MEM, + }, + /********************************************************************** + * multi com buffer area + *********************************************************************/ + { + .name = "MulticomSHM", + .start = 0x23700000, + .end = 0x23720000 - 1, + .flags = IORESOURCE_MEM, + }, + /********************************************************************** + * DMA Ring buffer (don't need recording buffers) + *********************************************************************/ + { + .name = "BMM_Buffer", + .start = 0x00000000, + .end = 0x000AA000 - 1, + .flags = IORESOURCE_MEM, + }, + /********************************************************************** + * Display bins buffer for unit0 + *********************************************************************/ + { + .name = "DisplayBins0", + .start = 0x00000000, + .end = 0x00000FFF, /* 4 KB total */ + .flags = IORESOURCE_MEM, + }, + /********************************************************************** + * + * AVFS: player HAL memory + * + * + *********************************************************************/ + { + .name = "AvfsDmaMem", + .start = 0x00000000, + .end = 0x002c4c00 - 1, /* 945K * 3 for playback */ + .flags = IORESOURCE_MEM, + }, + /********************************************************************** + * PMEM + *********************************************************************/ + { + .name = "DiagPersistentMemory", + .start = 0x00000000, + .end = 0x10000 - 1, + .flags = IORESOURCE_MEM, + }, + /********************************************************************** + * Smartcard + *********************************************************************/ + { + .name = "SmartCardInfo", + .start = 0x00000000, + .end = 0x2800 - 1, + .flags = IORESOURCE_MEM, + }, + /********************************************************************** + * NAND Flash + *********************************************************************/ + { + .name = "NandFlash", + .start = NAND_FLASH_BASE, + .end = NAND_FLASH_BASE + 0x400 - 1, + .flags = IORESOURCE_IO, + }, + /********************************************************************** + * Synopsys GMAC Memory Region + *********************************************************************/ + { + .name = "GMAC", + .start = 0x00000000, + .end = 0x00010000 - 1, + .flags = IORESOURCE_MEM, + }, + /********************************************************************** + * Add other resources here + * + */ + /* + * End of Resource marker + *********************************************************************/ + { + .flags = 0, + }, +}; + +struct resource non_dvr_vz_calliope_resources[] = +{ + /********************************************************************** + * VIDEO / LX1 + *********************************************************************/ + { + .name = "ST231aImage", /* Delta-Mu 1 image and ram */ + .start = 0x24000000, + .end = 0x24200000 - 1, /*2 Meg */ + .flags = IORESOURCE_MEM, + }, + { + .name = "ST231aMonitor", /* 8k block ST231a monitor */ + .start = 0x24200000, + .end = 0x24202000 - 1, + .flags = IORESOURCE_MEM, + }, + { + .name = "MediaMemory1", + .start = 0x22202000, + .end = 0x22C20B85 - 1, /* 10.12 Meg */ + .flags = IORESOURCE_MEM, + }, + /********************************************************************** + * Sysaudio Driver + *********************************************************************/ + { + .name = "DSP_Image_Buff", + .start = 0x00000000, + .end = 0x000FFFFF, + .flags = IORESOURCE_MEM, + }, + { + .name = "ADSC_CPU_PCM_Buff", + .start = 0x00000000, + .end = 0x00009FFF, + .flags = IORESOURCE_MEM, + }, + { + .name = "ADSC_AUX_Buff", + .start = 0x00000000, + .end = 0x00003FFF, + .flags = IORESOURCE_MEM, + }, + { + .name = "ADSC_Main_Buff", + .start = 0x00000000, + .end = 0x00003FFF, + .flags = IORESOURCE_MEM, + }, + /********************************************************************** + * STAVEM driver/STAPI + *********************************************************************/ + { + .name = "AVMEMPartition0", + .start = 0x20300000, + .end = 0x20620000-1, /*3.125 MB total */ + .flags = IORESOURCE_MEM, + }, + /********************************************************************** + * GHW HAL Driver + *********************************************************************/ + { + .name = "GraphicsHeap", + .start = 0x20100000, + .end = 0x20300000 - 1, + .flags = IORESOURCE_MEM, + }, + /********************************************************************** + * multi com buffer area + *********************************************************************/ + { + .name = "MulticomSHM", + .start = 0x23900000, + .end = 0x23920000 - 1, + .flags = IORESOURCE_MEM, + }, + /********************************************************************** + * DMA Ring buffer + *********************************************************************/ + { + .name = "BMM_Buffer", + .start = 0x00000000, + .end = 0x000AA000 - 1, + .flags = IORESOURCE_MEM, + }, + /********************************************************************** + * Display bins buffer for unit0 + *********************************************************************/ + { + .name = "DisplayBins0", + .start = 0x00000000, + .end = 0x00000FFF, + .flags = IORESOURCE_MEM, + }, + /********************************************************************** + * PMEM + *********************************************************************/ + { + .name = "DiagPersistentMemory", + .start = 0x00000000, + .end = 0x10000 - 1, + .flags = IORESOURCE_MEM, + }, + /********************************************************************** + * Smartcard + *********************************************************************/ + { + .name = "SmartCardInfo", + .start = 0x00000000, + .end = 0x2800 - 1, + .flags = IORESOURCE_MEM, + }, + /********************************************************************** + * NAND Flash + *********************************************************************/ + { + .name = "NandFlash", + .start = NAND_FLASH_BASE, + .end = NAND_FLASH_BASE+0x400 - 1, + .flags = IORESOURCE_IO, + }, + /********************************************************************** + * Synopsys GMAC Memory Region + *********************************************************************/ + { + .name = "GMAC", + .start = 0x00000000, + .end = 0x00010000 - 1, + .flags = IORESOURCE_MEM, + }, + /********************************************************************** + * Add other resources here + */ + /* + * End of Resource marker + *********************************************************************/ + { + .flags = 0, + }, +}; + + +/* + * NOTES: + * + * There are two things to be done on CRONUS platforms when we try to reserve + * the space of HIGHMEM for a specific device. + * + * 1. "IORESOURCE_MEM" flag can't be used anymore, it should be changed to + * "IORESOURCE_IO". + * + * 2. For the kernel with HIGHMEM support, we have to do some work in the + * memory configuration (in memory.c) since we don't make any actual + * reservation which has "IORESOURCE_IO" flag through bootmem allocator. + * + * TODO: Find a solution to make it working easily. + */ + +static struct resource non_dvr_vze_calliope_resources[] __initdata = +{ + /********************************************************************** + * VIDEO / LX1 + *********************************************************************/ + { + .name = "ST231aImage", /* Delta-Mu 1 image and ram */ + .start = 0x22000000, + .end = 0x22200000 - 1, /*2 Meg */ + .flags = IORESOURCE_MEM, + }, + { + .name = "ST231aMonitor", /* 8k block ST231a monitor */ + .start = 0x22200000, + .end = 0x22202000 - 1, + .flags = IORESOURCE_MEM, + }, + { + .name = "MediaMemory1", + .start = 0x22202000, + .end = 0x22C20B85 - 1, /* 10.12 Meg */ + .flags = IORESOURCE_MEM, + }, + /********************************************************************** + * Sysaudio Driver + *********************************************************************/ + { + .name = "DSP_Image_Buff", + .start = 0x00000000, + .end = 0x000FFFFF, + .flags = IORESOURCE_MEM, + }, + { + .name = "ADSC_CPU_PCM_Buff", + .start = 0x00000000, + .end = 0x00009FFF, + .flags = IORESOURCE_MEM, + }, + { + .name = "ADSC_AUX_Buff", + .start = 0x00000000, + .end = 0x00003FFF, + .flags = IORESOURCE_MEM, + }, + { + .name = "ADSC_Main_Buff", + .start = 0x00000000, + .end = 0x00003FFF, + .flags = IORESOURCE_MEM, + }, + /********************************************************************** + * STAVEM driver/STAPI + *********************************************************************/ + { + .name = "AVMEMPartition0", + .start = 0x20396000, + .end = 0x206B6000 - 1, /* 3.125 MB total */ + .flags = IORESOURCE_MEM, + }, + /********************************************************************** + * GHW HAL Driver + *********************************************************************/ + { + .name = "GraphicsHeap", + .start = 0x20100000, + .end = 0x20396000 - 1, + .flags = IORESOURCE_MEM, + }, + /********************************************************************** + * multi com buffer area + *********************************************************************/ + { + .name = "MulticomSHM", + .start = 0x206B6000, + .end = 0x206D6000 - 1, + .flags = IORESOURCE_MEM, + }, + /********************************************************************** + * DMA Ring buffer + *********************************************************************/ + { + .name = "BMM_Buffer", + .start = 0x00000000, + .end = 0x000AA000 - 1, + .flags = IORESOURCE_MEM, + }, + /********************************************************************** + * Display bins buffer for unit0 + *********************************************************************/ + { + .name = "DisplayBins0", + .start = 0x00000000, + .end = 0x00000FFF, + .flags = IORESOURCE_MEM, + }, + /********************************************************************** + * PMEM + *********************************************************************/ + { + .name = "DiagPersistentMemory", + .start = 0x00000000, + .end = 0x10000 - 1, + .flags = IORESOURCE_MEM, + }, + /********************************************************************** + * Smartcard + *********************************************************************/ + { + .name = "SmartCardInfo", + .start = 0x00000000, + .end = 0x2800 - 1, + .flags = IORESOURCE_MEM, + }, + /********************************************************************** + * NAND Flash + *********************************************************************/ + { + .name = "NandFlash", + .start = NAND_FLASH_BASE, + .end = NAND_FLASH_BASE+0x400 - 1, + .flags = IORESOURCE_MEM, + }, + /********************************************************************** + * Synopsys GMAC Memory Region + *********************************************************************/ + { + .name = "GMAC", + .start = 0x00000000, + .end = 0x00010000 - 1, + .flags = IORESOURCE_MEM, + }, + /********************************************************************** + * Add other resources here + */ + /* + * End of Resource marker + *********************************************************************/ + { + .flags = 0, + }, +}; + +static struct resource non_dvr_vzf_calliope_resources[] __initdata = +{ + /********************************************************************** + * VIDEO / LX1 + *********************************************************************/ + { + .name = "ST231aImage", /*Delta-Mu 1 image and ram */ + .start = 0x24000000, + .end = 0x24200000 - 1, /*2MiB */ + .flags = IORESOURCE_MEM, + }, + { + .name = "ST231aMonitor", /*8KiB block ST231a monitor */ + .start = 0x24200000, + .end = 0x24202000 - 1, + .flags = IORESOURCE_MEM, + }, + { + .name = "MediaMemory1", + .start = 0x24202000, + /* ~19.4 (21.5MiB - (2MiB + 8KiB)) */ + .end = 0x25580000 - 1, + .flags = IORESOURCE_MEM, + }, + /********************************************************************** + * Sysaudio Driver + *********************************************************************/ + { + .name = "DSP_Image_Buff", + .start = 0x00000000, + .end = 0x000FFFFF, + .flags = IORESOURCE_MEM, + }, + { + .name = "ADSC_CPU_PCM_Buff", + .start = 0x00000000, + .end = 0x00009FFF, + .flags = IORESOURCE_MEM, + }, + { + .name = "ADSC_AUX_Buff", + .start = 0x00000000, + .end = 0x00003FFF, + .flags = IORESOURCE_MEM, + }, + { + .name = "ADSC_Main_Buff", + .start = 0x00000000, + .end = 0x00003FFF, + .flags = IORESOURCE_MEM, + }, + /********************************************************************** + * STAVEM driver/STAPI + *********************************************************************/ + { + .name = "AVMEMPartition0", + .start = 0x00000000, + .end = 0x00480000 - 1, /* 4.5 MB total */ + .flags = IORESOURCE_MEM, + }, + /********************************************************************** + * GHW HAL Driver + *********************************************************************/ + { + .name = "GraphicsHeap", + .start = 0x22700000, + .end = 0x23500000 - 1, /* 14 MB total */ + .flags = IORESOURCE_MEM, + }, + /********************************************************************** + * multi com buffer area + *********************************************************************/ + { + .name = "MulticomSHM", + .start = 0x23700000, + .end = 0x23720000 - 1, + .flags = IORESOURCE_MEM, + }, + /********************************************************************** + * DMA Ring buffer (don't need recording buffers) + *********************************************************************/ + { + .name = "BMM_Buffer", + .start = 0x00000000, + .end = 0x000AA000 - 1, + .flags = IORESOURCE_MEM, + }, + /********************************************************************** + * Display bins buffer for unit0 + *********************************************************************/ + { + .name = "DisplayBins0", + .start = 0x00000000, + .end = 0x00000FFF, /* 4 KB total */ + .flags = IORESOURCE_MEM, + }, + /********************************************************************** + * Display bins buffer for unit1 + *********************************************************************/ + { + .name = "DisplayBins1", + .start = 0x00000000, + .end = 0x00000FFF, /* 4 KB total */ + .flags = IORESOURCE_MEM, + }, + /********************************************************************** + * + * AVFS: player HAL memory + * + * + *********************************************************************/ + { + .name = "AvfsDmaMem", + .start = 0x00000000, + .end = 0x002c4c00 - 1, /* 945K * 3 for playback */ + .flags = IORESOURCE_MEM, + }, + /********************************************************************** + * PMEM + *********************************************************************/ + { + .name = "DiagPersistentMemory", + .start = 0x00000000, + .end = 0x10000 - 1, + .flags = IORESOURCE_MEM, + }, + /********************************************************************** + * Smartcard + *********************************************************************/ + { + .name = "SmartCardInfo", + .start = 0x00000000, + .end = 0x2800 - 1, + .flags = IORESOURCE_MEM, + }, + /********************************************************************** + * NAND Flash + *********************************************************************/ + { + .name = "NandFlash", + .start = NAND_FLASH_BASE, + .end = NAND_FLASH_BASE + 0x400 - 1, + .flags = IORESOURCE_MEM, + }, + /********************************************************************** + * Synopsys GMAC Memory Region + *********************************************************************/ + { + .name = "GMAC", + .start = 0x00000000, + .end = 0x00010000 - 1, + .flags = IORESOURCE_MEM, + }, + /********************************************************************** + * Add other resources here + */ + /********************************************************************* + * End of Resource marker + *********************************************************************/ + { + .flags = 0, + }, +}; + +/****************************************************************************** + * DVR_CAPABLE CRONUS RESOURCES + *****************************************************************************/ +struct resource dvr_cronus_resources[] = +{ + /********************************************************************** + * + * VIDEO1 / LX1 + * + *********************************************************************/ + { + .name = "ST231aImage", /* Delta-Mu 1 image and ram */ + .start = 0x24000000, + .end = 0x241FFFFF, /* 2MiB */ + .flags = IORESOURCE_MEM, + }, + { + .name = "ST231aMonitor", /* 8KiB block ST231a monitor */ + .start = 0x24200000, + .end = 0x24201FFF, + .flags = IORESOURCE_MEM, + }, + { + .name = "MediaMemory1", + .start = 0x24202000, + .end = 0x25FFFFFF, /*~29.9MiB (32MiB - (2MiB + 8KiB)) */ + .flags = IORESOURCE_MEM, + }, + /********************************************************************** + * + * VIDEO2 / LX2 + * + *********************************************************************/ + { + .name = "ST231bImage", /* Delta-Mu 2 image and ram */ + .start = 0x60000000, + .end = 0x601FFFFF, /* 2MiB */ + .flags = IORESOURCE_IO, + }, + { + .name = "ST231bMonitor", /* 8KiB block ST231b monitor */ + .start = 0x60200000, + .end = 0x60201FFF, + .flags = IORESOURCE_IO, + }, + { + .name = "MediaMemory2", + .start = 0x60202000, + .end = 0x61FFFFFF, /*~29.9MiB (32MiB - (2MiB + 8KiB)) */ + .flags = IORESOURCE_IO, + }, + /********************************************************************** + * + * Sysaudio Driver + * + * This driver requires: + * + * Arbitrary Based Buffers: + * DSP_Image_Buff - DSP code and data images (1MB) + * ADSC_CPU_PCM_Buff - ADSC CPU PCM buffer (40KB) + * ADSC_AUX_Buff - ADSC AUX buffer (16KB) + * ADSC_Main_Buff - ADSC Main buffer (16KB) + * + *********************************************************************/ + { + .name = "DSP_Image_Buff", + .start = 0x00000000, + .end = 0x000FFFFF, + .flags = IORESOURCE_MEM, + }, + { + .name = "ADSC_CPU_PCM_Buff", + .start = 0x00000000, + .end = 0x00009FFF, + .flags = IORESOURCE_MEM, + }, + { + .name = "ADSC_AUX_Buff", + .start = 0x00000000, + .end = 0x00003FFF, + .flags = IORESOURCE_MEM, + }, + { + .name = "ADSC_Main_Buff", + .start = 0x00000000, + .end = 0x00003FFF, + .flags = IORESOURCE_MEM, + }, + /********************************************************************** + * + * STAVEM driver/STAPI + * + * This driver requires: + * + * Arbitrary Based Buffers: + * This memory area is used for allocating buffers for Video decoding + * purposes. Allocation/De-allocation within this buffer is managed + * by the STAVMEM driver of the STAPI. They could be Decimated + * Picture Buffers, Intermediate Buffers, as deemed necessary for + * video decoding purposes, for any video decoders on Zeus. + * + *********************************************************************/ + { + .name = "AVMEMPartition0", + .start = 0x63580000, + .end = 0x64180000 - 1, /* 12 MB total */ + .flags = IORESOURCE_IO, + }, + /********************************************************************** + * + * DOCSIS Subsystem + * + * This driver requires: + * + * Arbitrary Based Buffers: + * Docsis - + * + *********************************************************************/ + { + .name = "Docsis", + .start = 0x62000000, + .end = 0x62700000 - 1, /* 7 MB total */ + .flags = IORESOURCE_IO, + }, + /********************************************************************** + * + * GHW HAL Driver + * + * This driver requires: + * + * Arbitrary Based Buffers: + * GraphicsHeap - PowerTV Graphics Heap + * + *********************************************************************/ + { + .name = "GraphicsHeap", + .start = 0x62700000, + .end = 0x63500000 - 1, /* 14 MB total */ + .flags = IORESOURCE_IO, + }, + /********************************************************************** + * + * multi com buffer area + * + * This driver requires: + * + * Arbitrary Based Buffers: + * Docsis - + * + *********************************************************************/ + { + .name = "MulticomSHM", + .start = 0x26000000, + .end = 0x26020000 - 1, + .flags = IORESOURCE_MEM, + }, + /********************************************************************** + * + * DMA Ring buffer + * + * This driver requires: + * + * Arbitrary Based Buffers: + * Docsis - + * + *********************************************************************/ + { + .name = "BMM_Buffer", + .start = 0x00000000, + .end = 0x00280000 - 1, + .flags = IORESOURCE_MEM, + }, + /********************************************************************** + * + * Display bins buffer for unit0 + * + * This driver requires: + * + * Arbitrary Based Buffers: + * Display Bins for unit0 + * + *********************************************************************/ + { + .name = "DisplayBins0", + .start = 0x00000000, + .end = 0x00000FFF, /* 4 KB total */ + .flags = IORESOURCE_MEM, + }, + /********************************************************************** + * + * Display bins buffer + * + * This driver requires: + * + * Arbitrary Based Buffers: + * Display Bins for unit1 + * + *********************************************************************/ + { + .name = "DisplayBins1", + .start = 0x64AD4000, + .end = 0x64AD5000 - 1, /* 4 KB total */ + .flags = IORESOURCE_IO, + }, + /********************************************************************** + * + * ITFS + * + * This driver requires: + * + * Arbitrary Based Buffers: + * Docsis - + * + *********************************************************************/ + { + .name = "ITFS", + .start = 0x64180000, + /* 815,104 bytes each for 2 ITFS partitions. */ + .end = 0x6430DFFF, + .flags = IORESOURCE_IO, + }, + /********************************************************************** + * + * AVFS + * + * This driver requires: + * + * Arbitrary Based Buffers: + * Docsis - + * + *********************************************************************/ + { + .name = "AvfsDmaMem", + .start = 0x6430E000, + /* (945K * 8) = (128K *3) 5 playbacks / 3 server */ + .end = 0x64AD0000 - 1, + .flags = IORESOURCE_IO, + }, + { + .name = "AvfsFileSys", + .start = 0x64AD0000, + .end = 0x64AD1000 - 1, /* 4K */ + .flags = IORESOURCE_IO, + }, + /********************************************************************** + * + * PMEM + * + * This driver requires: + * + * Arbitrary Based Buffers: + * Persistent memory for diagnostics. + * + *********************************************************************/ + { + .name = "DiagPersistentMemory", + .start = 0x00000000, + .end = 0x10000 - 1, + .flags = IORESOURCE_MEM, + }, + /********************************************************************** + * + * Smartcard + * + * This driver requires: + * + * Arbitrary Based Buffers: + * Read and write buffers for Internal/External cards + * + *********************************************************************/ + { + .name = "SmartCardInfo", + .start = 0x64AD1000, + .end = 0x64AD3800 - 1, + .flags = IORESOURCE_IO, + }, + /********************************************************************** + * + * KAVNET + * NP Reset Vector - must be of the form xxCxxxxx + * NP Image - must be video bank 1 + * NP IPC - must be video bank 2 + *********************************************************************/ + { + .name = "NP_Reset_Vector", + .start = 0x27c00000, + .end = 0x27c01000 - 1, + .flags = IORESOURCE_MEM, + }, + { + .name = "NP_Image", + .start = 0x27020000, + .end = 0x27060000 - 1, + .flags = IORESOURCE_MEM, + }, + { + .name = "NP_IPC", + .start = 0x63500000, + .end = 0x63580000 - 1, + .flags = IORESOURCE_IO, + }, + /********************************************************************** + * Add other resources here + */ + /* + * End of Resource marker + * + *********************************************************************/ + { + .flags = 0, + }, +}; + +/****************************************************************************** + * NON_DVR_CAPABLE CRONUSLITE RESOURCES + *****************************************************************************/ +struct resource non_dvr_cronuslite_resources[] = +{ + /********************************************************************** + * + * VIDEO2 / LX2 + * + *********************************************************************/ + { + .name = "ST231aImage", /* Delta-Mu 2 image and ram */ + .start = 0x60000000, + .end = 0x601FFFFF, /* 2MiB */ + .flags = IORESOURCE_IO, + }, + { + .name = "ST231aMonitor", /* 8KiB block ST231b monitor */ + .start = 0x60200000, + .end = 0x60201FFF, + .flags = IORESOURCE_IO, + }, + { + .name = "MediaMemory1", + .start = 0x60202000, + .end = 0x61FFFFFF, /*~29.9MiB (32MiB - (2MiB + 8KiB)) */ + .flags = IORESOURCE_IO, + }, + /********************************************************************** + * + * Sysaudio Driver + * + * This driver requires: + * + * Arbitrary Based Buffers: + * DSP_Image_Buff - DSP code and data images (1MB) + * ADSC_CPU_PCM_Buff - ADSC CPU PCM buffer (40KB) + * ADSC_AUX_Buff - ADSC AUX buffer (16KB) + * ADSC_Main_Buff - ADSC Main buffer (16KB) + * + *********************************************************************/ + { + .name = "DSP_Image_Buff", + .start = 0x00000000, + .end = 0x000FFFFF, + .flags = IORESOURCE_MEM, + }, + { + .name = "ADSC_CPU_PCM_Buff", + .start = 0x00000000, + .end = 0x00009FFF, + .flags = IORESOURCE_MEM, + }, + { + .name = "ADSC_AUX_Buff", + .start = 0x00000000, + .end = 0x00003FFF, + .flags = IORESOURCE_MEM, + }, + { + .name = "ADSC_Main_Buff", + .start = 0x00000000, + .end = 0x00003FFF, + .flags = IORESOURCE_MEM, + }, + /********************************************************************** + * + * STAVEM driver/STAPI + * + * This driver requires: + * + * Arbitrary Based Buffers: + * This memory area is used for allocating buffers for Video decoding + * purposes. Allocation/De-allocation within this buffer is managed + * by the STAVMEM driver of the STAPI. They could be Decimated + * Picture Buffers, Intermediate Buffers, as deemed necessary for + * video decoding purposes, for any video decoders on Zeus. + * + *********************************************************************/ + { + .name = "AVMEMPartition0", + .start = 0x63580000, + .end = 0x63B80000 - 1, /* 6 MB total */ + .flags = IORESOURCE_IO, + }, + /********************************************************************** + * + * DOCSIS Subsystem + * + * This driver requires: + * + * Arbitrary Based Buffers: + * Docsis - + * + *********************************************************************/ + { + .name = "Docsis", + .start = 0x62000000, + .end = 0x62700000 - 1, /* 7 MB total */ + .flags = IORESOURCE_IO, + }, + /********************************************************************** + * + * GHW HAL Driver + * + * This driver requires: + * + * Arbitrary Based Buffers: + * GraphicsHeap - PowerTV Graphics Heap + * + *********************************************************************/ + { + .name = "GraphicsHeap", + .start = 0x62700000, + .end = 0x63500000 - 1, /* 14 MB total */ + .flags = IORESOURCE_IO, + }, + /********************************************************************** + * + * multi com buffer area + * + * This driver requires: + * + * Arbitrary Based Buffers: + * Docsis - + * + *********************************************************************/ + { + .name = "MulticomSHM", + .start = 0x26000000, + .end = 0x26020000 - 1, + .flags = IORESOURCE_MEM, + }, + /********************************************************************** + * + * DMA Ring buffer + * + * This driver requires: + * + * Arbitrary Based Buffers: + * Docsis - + * + *********************************************************************/ + { + .name = "BMM_Buffer", + .start = 0x00000000, + .end = 0x000AA000 - 1, + .flags = IORESOURCE_MEM, + }, + /********************************************************************** + * + * Display bins buffer for unit0 + * + * This driver requires: + * + * Arbitrary Based Buffers: + * Display Bins for unit0 + * + *********************************************************************/ + { + .name = "DisplayBins0", + .start = 0x00000000, + .end = 0x00000FFF, /* 4 KB total */ + .flags = IORESOURCE_MEM, + }, + /********************************************************************** + * + * Display bins buffer + * + * This driver requires: + * + * Arbitrary Based Buffers: + * Display Bins for unit1 + * + *********************************************************************/ + { + .name = "DisplayBins1", + .start = 0x63B83000, + .end = 0x63B84000 - 1, /* 4 KB total */ + .flags = IORESOURCE_IO, + }, + /********************************************************************** + * + * AVFS: player HAL memory + * + * + *********************************************************************/ + { + .name = "AvfsDmaMem", + .start = 0x63B84000, + .end = 0x63E48C00 - 1, /* 945K * 3 for playback */ + .flags = IORESOURCE_IO, + }, + /********************************************************************** + * + * PMEM + * + * This driver requires: + * + * Arbitrary Based Buffers: + * Persistent memory for diagnostics. + * + *********************************************************************/ + { + .name = "DiagPersistentMemory", + .start = 0x00000000, + .end = 0x10000 - 1, + .flags = IORESOURCE_MEM, + }, + /********************************************************************** + * + * Smartcard + * + * This driver requires: + * + * Arbitrary Based Buffers: + * Read and write buffers for Internal/External cards + * + *********************************************************************/ + { + .name = "SmartCardInfo", + .start = 0x63B80000, + .end = 0x63B82800 - 1, + .flags = IORESOURCE_IO, + }, + /********************************************************************** + * + * KAVNET + * NP Reset Vector - must be of the form xxCxxxxx + * NP Image - must be video bank 1 + * NP IPC - must be video bank 2 + *********************************************************************/ + { + .name = "NP_Reset_Vector", + .start = 0x27c00000, + .end = 0x27c01000 - 1, + .flags = IORESOURCE_MEM, + }, + { + .name = "NP_Image", + .start = 0x27020000, + .end = 0x27060000 - 1, + .flags = IORESOURCE_MEM, + }, + { + .name = "NP_IPC", + .start = 0x63500000, + .end = 0x63580000 - 1, + .flags = IORESOURCE_IO, + }, + /********************************************************************** + * NAND Flash + *********************************************************************/ + { + .name = "NandFlash", + .start = NAND_FLASH_BASE, + .end = NAND_FLASH_BASE + 0x400 - 1, + .flags = IORESOURCE_IO, + }, + /********************************************************************** + * Add other resources here + */ + /* + * End of Resource marker + * + *********************************************************************/ + { + .flags = 0, + }, +}; + +/****************************************************************************** + * NON_DVR_CAPABLE CRONUS RESOURCES + *****************************************************************************/ +struct resource non_dvr_cronus_resources[] = +{ + /********************************************************************** + * + * VIDEO1 / LX1 + * + *********************************************************************/ + { + .name = "ST231aImage", /* Delta-Mu 1 image and ram */ + .start = 0x24000000, + .end = 0x241FFFFF, /* 2MiB */ + .flags = IORESOURCE_MEM, + }, + { + .name = "ST231aMonitor", /* 8KiB block ST231a monitor */ + .start = 0x24200000, + .end = 0x24201FFF, + .flags = IORESOURCE_MEM, + }, + { + .name = "MediaMemory1", + .start = 0x24202000, + .end = 0x25FFFFFF, /*~29.9MiB (32MiB - (2MiB + 8KiB)) */ + .flags = IORESOURCE_MEM, + }, + /********************************************************************** + * + * VIDEO2 / LX2 + * + *********************************************************************/ + { + .name = "ST231bImage", /* Delta-Mu 2 image and ram */ + .start = 0x60000000, + .end = 0x601FFFFF, /* 2MiB */ + .flags = IORESOURCE_IO, + }, + { + .name = "ST231bMonitor", /* 8KiB block ST231b monitor */ + .start = 0x60200000, + .end = 0x60201FFF, + .flags = IORESOURCE_IO, + }, + { + .name = "MediaMemory2", + .start = 0x60202000, + .end = 0x61FFFFFF, /*~29.9MiB (32MiB - (2MiB + 8KiB)) */ + .flags = IORESOURCE_IO, + }, + /********************************************************************** + * + * Sysaudio Driver + * + * This driver requires: + * + * Arbitrary Based Buffers: + * DSP_Image_Buff - DSP code and data images (1MB) + * ADSC_CPU_PCM_Buff - ADSC CPU PCM buffer (40KB) + * ADSC_AUX_Buff - ADSC AUX buffer (16KB) + * ADSC_Main_Buff - ADSC Main buffer (16KB) + * + *********************************************************************/ + { + .name = "DSP_Image_Buff", + .start = 0x00000000, + .end = 0x000FFFFF, + .flags = IORESOURCE_MEM, + }, + { + .name = "ADSC_CPU_PCM_Buff", + .start = 0x00000000, + .end = 0x00009FFF, + .flags = IORESOURCE_MEM, + }, + { + .name = "ADSC_AUX_Buff", + .start = 0x00000000, + .end = 0x00003FFF, + .flags = IORESOURCE_MEM, + }, + { + .name = "ADSC_Main_Buff", + .start = 0x00000000, + .end = 0x00003FFF, + .flags = IORESOURCE_MEM, + }, + /********************************************************************** + * + * STAVEM driver/STAPI + * + * This driver requires: + * + * Arbitrary Based Buffers: + * This memory area is used for allocating buffers for Video decoding + * purposes. Allocation/De-allocation within this buffer is managed + * by the STAVMEM driver of the STAPI. They could be Decimated + * Picture Buffers, Intermediate Buffers, as deemed necessary for + * video decoding purposes, for any video decoders on Zeus. + * + *********************************************************************/ + { + .name = "AVMEMPartition0", + .start = 0x63580000, + .end = 0x64180000 - 1, /* 12 MB total */ + .flags = IORESOURCE_IO, + }, + /********************************************************************** + * + * DOCSIS Subsystem + * + * This driver requires: + * + * Arbitrary Based Buffers: + * Docsis - + * + *********************************************************************/ + { + .name = "Docsis", + .start = 0x62000000, + .end = 0x62700000 - 1, /* 7 MB total */ + .flags = IORESOURCE_IO, + }, + /********************************************************************** + * + * GHW HAL Driver + * + * This driver requires: + * + * Arbitrary Based Buffers: + * GraphicsHeap - PowerTV Graphics Heap + * + *********************************************************************/ + { + .name = "GraphicsHeap", + .start = 0x62700000, + .end = 0x63500000 - 1, /* 14 MB total */ + .flags = IORESOURCE_IO, + }, + /********************************************************************** + * + * multi com buffer area + * + * This driver requires: + * + * Arbitrary Based Buffers: + * Docsis - + * + *********************************************************************/ + { + .name = "MulticomSHM", + .start = 0x26000000, + .end = 0x26020000 - 1, + .flags = IORESOURCE_MEM, + }, + /********************************************************************** + * + * DMA Ring buffer + * + * This driver requires: + * + * Arbitrary Based Buffers: + * Docsis - + * + *********************************************************************/ + { + .name = "BMM_Buffer", + .start = 0x00000000, + .end = 0x000AA000 - 1, + .flags = IORESOURCE_MEM, + }, + /********************************************************************** + * + * Display bins buffer for unit0 + * + * This driver requires: + * + * Arbitrary Based Buffers: + * Display Bins for unit0 + * + *********************************************************************/ + { + .name = "DisplayBins0", + .start = 0x00000000, + .end = 0x00000FFF, /* 4 KB total */ + .flags = IORESOURCE_MEM, + }, + /********************************************************************** + * + * Display bins buffer + * + * This driver requires: + * + * Arbitrary Based Buffers: + * Display Bins for unit1 + * + *********************************************************************/ + { + .name = "DisplayBins1", + .start = 0x64AD4000, + .end = 0x64AD5000 - 1, /* 4 KB total */ + .flags = IORESOURCE_IO, + }, + /********************************************************************** + * + * AVFS: player HAL memory + * + * + *********************************************************************/ + { + .name = "AvfsDmaMem", + .start = 0x6430E000, + .end = 0x645D2C00 - 1, /* 945K * 3 for playback */ + .flags = IORESOURCE_IO, + }, + /********************************************************************** + * + * PMEM + * + * This driver requires: + * + * Arbitrary Based Buffers: + * Persistent memory for diagnostics. + * + *********************************************************************/ + { + .name = "DiagPersistentMemory", + .start = 0x00000000, + .end = 0x10000 - 1, + .flags = IORESOURCE_MEM, + }, + /********************************************************************** + * + * Smartcard + * + * This driver requires: + * + * Arbitrary Based Buffers: + * Read and write buffers for Internal/External cards + * + *********************************************************************/ + { + .name = "SmartCardInfo", + .start = 0x64AD1000, + .end = 0x64AD3800 - 1, + .flags = IORESOURCE_IO, + }, + /********************************************************************** + * + * KAVNET + * NP Reset Vector - must be of the form xxCxxxxx + * NP Image - must be video bank 1 + * NP IPC - must be video bank 2 + *********************************************************************/ + { + .name = "NP_Reset_Vector", + .start = 0x27c00000, + .end = 0x27c01000 - 1, + .flags = IORESOURCE_MEM, + }, + { + .name = "NP_Image", + .start = 0x27020000, + .end = 0x27060000 - 1, + .flags = IORESOURCE_MEM, + }, + { + .name = "NP_IPC", + .start = 0x63500000, + .end = 0x63580000 - 1, + .flags = IORESOURCE_IO, + }, + /********************************************************************** + * Add other resources here + */ + /* + * End of Resource marker + * + *********************************************************************/ + { + .flags = 0, + }, +}; + +/* + * + * IO Resource Definition + * + */ + +struct resource asic_resource = { + .name = "ASIC Resource", + .start = 0, + .end = ASIC_IO_SIZE, + .flags = IORESOURCE_MEM, +}; + +/* + * + * USB Host Resource Definition + * + */ + +static struct resource ehci_resources[] = { + { + .parent = &asic_resource, + .start = 0, + .end = 0xff, + .flags = IORESOURCE_MEM, + }, + { + .start = kIrq_USBEHCI, + .end = kIrq_USBEHCI, + .flags = IORESOURCE_IRQ, + }, +}; + +static u64 ehci_dmamask = 0xffffffffULL; + +static struct platform_device ehci_device = { + .name = "powertv-ehci", + .id = 0, + .num_resources = 2, + .resource = ehci_resources, + .dev = { + .dma_mask = &ehci_dmamask, + .coherent_dma_mask = 0xffffffff, + }, +}; + +static struct resource ohci_resources[] = { + { + .parent = &asic_resource, + .start = 0, + .end = 0xff, + .flags = IORESOURCE_MEM, + }, + { + .start = kIrq_USBOHCI, + .end = kIrq_USBOHCI, + .flags = IORESOURCE_IRQ, + }, +}; + +static u64 ohci_dmamask = 0xffffffffULL; + +static struct platform_device ohci_device = { + .name = "powertv-ohci", + .id = 0, + .num_resources = 2, + .resource = ohci_resources, + .dev = { + .dma_mask = &ohci_dmamask, + .coherent_dma_mask = 0xffffffff, + }, +}; + +static struct platform_device *platform_devices[] = { + &ehci_device, + &ohci_device, +}; + +/* + * + * Platform Configuration and Device Initialization + * + */ +static void __init fs_update(int pe, int md, int sdiv, int disable_div_by_3) +{ + int en_prg, byp, pwr, nsb, val; + int sout; + + sout = 1; + en_prg = 1; + byp = 0; + nsb = 1; + pwr = 1; + + val = ((sdiv << 29) | (md << 24) | (pe<<8) | (sout<<3) | (byp<<2) | + (nsb<<1) | (disable_div_by_3<<5)); + + asic_write(val, USB_FS); + asic_write(val | (en_prg<<4), USB_FS); + asic_write(val | (en_prg<<4) | pwr, USB_FS); +} + +/* + * \brief platform_get_family() determine major platform family type. + * + * \param none + * + * \return family type; -1 if none + * + */ +enum tFamilyType platform_get_family(void) +{ +#define BOOTLDRFAMILY(byte1, byte0) (((byte1) << 8) | (byte0)) + + unsigned short bootldrFamily; + static enum tFamilyType family = -1; + static int firstTime = 1; + + if (firstTime) { + firstTime = 0; + +#ifdef CONFIG_BOOTLOADER_DRIVER + bootldrFamily = (unsigned short) kbldr_GetSWFamily(); +#else +#if defined(CONFIG_BOOTLOADER_FAMILY) + bootldrFamily = (unsigned short) BOOTLDRFAMILY( + CONFIG_BOOTLOADER_FAMILY[0], + CONFIG_BOOTLOADER_FAMILY[1]); +#else +#error "Unknown Bootloader Family" +#endif +#endif + + pr_info("Bootloader Family = 0x%04X\n", bootldrFamily); + + switch (bootldrFamily) { + case BOOTLDRFAMILY('R', '1'): + family = FAMILY_1500; + break; + case BOOTLDRFAMILY('4', '4'): + family = FAMILY_4500; + break; + case BOOTLDRFAMILY('4', '6'): + family = FAMILY_4600; + break; + case BOOTLDRFAMILY('A', '1'): + family = FAMILY_4600VZA; + break; + case BOOTLDRFAMILY('8', '5'): + family = FAMILY_8500; + break; + case BOOTLDRFAMILY('R', '2'): + family = FAMILY_8500RNG; + break; + case BOOTLDRFAMILY('8', '6'): + family = FAMILY_8600; + break; + case BOOTLDRFAMILY('B', '1'): + family = FAMILY_8600VZB; + break; + case BOOTLDRFAMILY('E', '1'): + family = FAMILY_1500VZE; + break; + case BOOTLDRFAMILY('F', '1'): + family = FAMILY_1500VZF; + break; + default: + family = -1; + } + } + + return family; + +#undef BOOTLDRFAMILY +} +EXPORT_SYMBOL(platform_get_family); + +/* + * \brief platform_get_asic() determine the ASIC type. + * + * \param none + * + * \return ASIC type; ASIC_UNKNOWN if none + * + */ +enum tAsicType platform_get_asic(void) +{ + return gAsic; +} +EXPORT_SYMBOL(platform_get_asic); + +/* + * \brief platform_configure_usb() usb configuration based on platform type. + * + * \param int divide_by_3 divide clock setting by 3 + * + * \return none + * + */ +static void platform_configure_usb(void) +{ + int divide_by_3; + + if (usb_configured) + return; + + switch (gAsic) { + case ASIC_ZEUS: + case ASIC_CRONUS: + case ASIC_CRONUSLITE: + divide_by_3 = 0; + break; + + case ASIC_CALLIOPE: + divide_by_3 = 1; + break; + + default: + pr_err("Unknown ASIC type: %d\n", gAsic); + divide_by_3 = 0; + break; + } + + /* Set up PLL for USB */ + fs_update(0x0000, 0x11, 0x02, divide_by_3); + /* turn on USB power */ + asic_write(0, USB2_Strap); + /* Enable all OHCI interrupts */ + asic_write(0x00000803, USB2_Control); + /* USB2_STBUS_OBC store32/load32 */ + asic_write(3, USB2_STBUS_OBC); + /* USB2_STBUS_MESS_SIZE 2 packets */ + asic_write(1, USB2_STBUS_MESS_SIZE); + /* USB2_STBUS_CHUNK_SIZE 2 packets */ + asic_write(1, USB2_STBUS_CHUNK_SIZE); + + usb_configured = true; +} + +/* + * Set up the USB EHCI interface + */ +void platform_configure_usb_ehci() +{ platform_configure_usb(); +} + +/* + * Set up the USB OHCI interface + */ +void platform_configure_usb_ohci() +{ platform_configure_usb(); +} + +/* + * Shut the USB EHCI interface down--currently a NOP + */ +void platform_unconfigure_usb_ehci() +{ +} + +/* + * Shut the USB OHCI interface down--currently a NOP + */ +void platform_unconfigure_usb_ohci() +{ +} + +/* + * \brief configure_platform() configuration based on platform type. + * + * \param none + * + * \return none + * + */ +void __init configure_platform(void) +{ + gPlatformFamily = platform_get_family(); + + switch (gPlatformFamily) { + case FAMILY_1500: + case FAMILY_1500VZE: + case FAMILY_1500VZF: + gPlatformFeatures = FFS_CAPABLE; + gAsic = ASIC_CALLIOPE; + gAsicPhyBase = CALLIOPE_IO_BASE; + gRegisterMap = &calliope_register_map; + pAsicBase = (unsigned long)ioremap_nocache(gAsicPhyBase, + ASIC_IO_SIZE); + + if (gPlatformFamily == FAMILY_1500VZE) { + gpResources = non_dvr_vze_calliope_resources; + pr_info("Platform: 1500/Vz Class E - " + "CALLIOPE, NON_DVR_CAPABLE\n"); + } else if (gPlatformFamily == FAMILY_1500VZF) { + gpResources = non_dvr_vzf_calliope_resources; + pr_info("Platform: 1500/Vz Class F - " + "CALLIOPE, NON_DVR_CAPABLE\n"); + } else { + gpResources = non_dvr_calliope_resources; + pr_info("Platform: 1500/RNG100 - CALLIOPE, " + "NON_DVR_CAPABLE\n"); + } + break; + + case FAMILY_4500: + gPlatformFeatures = FFS_CAPABLE | PCIE_CAPABLE | + DISPLAY_CAPABLE; + gAsic = ASIC_ZEUS; + gAsicPhyBase = ZEUS_IO_BASE; + gRegisterMap = &zeus_register_map; + pAsicBase = (unsigned long)ioremap_nocache(gAsicPhyBase, + ASIC_IO_SIZE); + gpResources = non_dvr_zeus_resources; + + pr_info("Platform: 4500 - ZEUS, NON_DVR_CAPABLE\n"); + break; + + case FAMILY_4600: + { + unsigned int chipversion = 0; + + /* The settop has PCIE but it isn't used, so don't advertise + * it*/ + gPlatformFeatures = FFS_CAPABLE | DISPLAY_CAPABLE; + gAsicPhyBase = CRONUS_IO_BASE; /* same as Cronus */ + gRegisterMap = &cronus_register_map; /* same as Cronus */ + pAsicBase = (unsigned long)ioremap_nocache(gAsicPhyBase, + ASIC_IO_SIZE); + gpResources = non_dvr_cronuslite_resources; + + /* ASIC version will determine if this is a real CronusLite or + * Castrati(Cronus) */ + chipversion = asic_read(CHIPVER3) << 24; + chipversion |= asic_read(CHIPVER2) << 16; + chipversion |= asic_read(CHIPVER1) << 8; + chipversion |= asic_read(CHIPVER0); + + if ((chipversion == CRONUS_10) || (chipversion == CRONUS_11)) + gAsic = ASIC_CRONUS; + else + gAsic = ASIC_CRONUSLITE; + + pr_info("Platform: 4600 - %s, NON_DVR_CAPABLE, " + "chipversion=0x%08X\n", + (gAsic == ASIC_CRONUS) ? "CRONUS" : "CRONUS LITE", + chipversion); + break; + } + case FAMILY_4600VZA: + gPlatformFeatures = FFS_CAPABLE | DISPLAY_CAPABLE; + gAsic = ASIC_CRONUS; + gAsicPhyBase = CRONUS_IO_BASE; + gRegisterMap = &cronus_register_map; + pAsicBase = (unsigned long)ioremap_nocache(gAsicPhyBase, + ASIC_IO_SIZE); + gpResources = non_dvr_cronus_resources; + + pr_info("Platform: Vz Class A - CRONUS, NON_DVR_CAPABLE\n"); + break; + + case FAMILY_8500: + case FAMILY_8500RNG: + gPlatformFeatures = DVR_CAPABLE | PCIE_CAPABLE | + DISPLAY_CAPABLE; + gAsic = ASIC_ZEUS; + gAsicPhyBase = ZEUS_IO_BASE; + gRegisterMap = &zeus_register_map; + pAsicBase = (unsigned long)ioremap_nocache(gAsicPhyBase, + ASIC_IO_SIZE); + gpResources = dvr_zeus_resources; + break; + + case FAMILY_8600: + case FAMILY_8600VZB: + gPlatformFeatures = DVR_CAPABLE | PCIE_CAPABLE | + DISPLAY_CAPABLE; + gAsic = ASIC_CRONUS; + gAsicPhyBase = CRONUS_IO_BASE; + gRegisterMap = &cronus_register_map; + pAsicBase = (unsigned long)ioremap_nocache(gAsicPhyBase, + ASIC_IO_SIZE); + gpResources = dvr_cronus_resources; + + pr_info("Platform: 8600/Vz Class B - CRONUS, " + "DVR_CAPABLE\n"); + break; + + default: + gPlatformFeatures = 0; + gAsic = ASIC_UNKNOWN; + gAsicPhyBase = 0; + gRegisterMap = NULL; + gpResources = NULL; + + pr_crit("Platform: UNKNOWN PLATFORM\n"); + break; + } + + platform_configure_usb(); + + switch (gAsic) { + case ASIC_ZEUS: + gPhysToBusOffset = 0x30000000; + break; + case ASIC_CALLIOPE: + gPhysToBusOffset = 0x10000000; + break; + case ASIC_CRONUSLITE: + /* Fall through */ + case ASIC_CRONUS: + /* + * TODO: We suppose 0x10000000 aliases into 0x20000000- + * 0x2XXXXXXX. If 0x10000000 aliases into 0x60000000- + * 0x6XXXXXXX, the offset should be 0x50000000, not 0x10000000. + */ + gPhysToBusOffset = 0x10000000; + break; + default: + gPhysToBusOffset = 0x00000000; + break; + } +} + +/* + * \brief platform_devices_init() sets up USB device resourse. + * + * \param none + * + * \return none + * + */ +static int __init platform_devices_init(void) +{ + pr_crit("%s: ----- Initializing USB resources -----\n", __func__); + + asic_resource.start = gAsicPhyBase; + asic_resource.end += asic_resource.start; + + ehci_resources[0].start = asic_reg_phys_addr(EHCI_HCAPBASE); + ehci_resources[0].end += ehci_resources[0].start; + + ohci_resources[0].start = asic_reg_phys_addr(OHCI_HcRevision); + ohci_resources[0].end += ohci_resources[0].start; + + set_io_port_base(0); + + platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); + + return 0; +} + +arch_initcall(platform_devices_init); + +/* + * + * BOOTMEM ALLOCATION + * + */ +/* + * Allocates/reserves the Platform memory resources early in the boot process. + * This ignores any resources that are designated IORESOURCE_IO + */ +void __init platform_alloc_bootmem(void) +{ + int i; + int total = 0; + + /* Get persistent memory data from command line before allocating + * resources. This need to happen before normal command line parsing + * has been done */ + pmem_setup_resource(); + + /* Loop through looking for resources that want a particular address */ + for (i = 0; gpResources[i].flags != 0; i++) { + int size = gpResources[i].end - gpResources[i].start + 1; + if ((gpResources[i].start != 0) && + ((gpResources[i].flags & IORESOURCE_MEM) != 0)) { + reserve_bootmem(bus_to_phys(gpResources[i].start), + size, 0); + total += gpResources[i].end - gpResources[i].start + 1; + pr_info("reserve resource %s at %08x (%u bytes)\n", + gpResources[i].name, gpResources[i].start, + gpResources[i].end - gpResources[i].start + 1); + } + } + + /* Loop through assigning addresses for those that are left */ + for (i = 0; gpResources[i].flags != 0; i++) { + int size = gpResources[i].end - gpResources[i].start + 1; + if ((gpResources[i].start == 0) && + ((gpResources[i].flags & IORESOURCE_MEM) != 0)) { + void *mem = alloc_bootmem_pages(size); + + if (mem == NULL) + pr_err("Unable to allocate bootmem pages " + "for %s\n", gpResources[i].name); + + else { + gpResources[i].start = + phys_to_bus(virt_to_phys(mem)); + gpResources[i].end = + gpResources[i].start + size - 1; + total += size; + pr_info("allocate resource %s at %08x " + "(%u bytes)\n", + gpResources[i].name, + gpResources[i].start, size); + } + } + } + + pr_info("Total Platform driver memory allocation: 0x%08x\n", total); + + /* indicate resources that are platform I/O related */ + for (i = 0; gpResources[i].flags != 0; i++) { + if ((gpResources[i].start != 0) && + ((gpResources[i].flags & IORESOURCE_IO) != 0)) { + pr_info("reserved platform resource %s at %08x\n", + gpResources[i].name, gpResources[i].start); + } + } +} + +/* + * + * PERSISTENT MEMORY (PMEM) CONFIGURATION + * + */ +static unsigned long pmemaddr __initdata; + +static int __init early_param_pmemaddr(char *p) +{ + pmemaddr = (unsigned long)simple_strtoul(p, NULL, 0); + return 0; +} +early_param("pmemaddr", early_param_pmemaddr); + +static long pmemlen __initdata; + +static int __init early_param_pmemlen(char *p) +{ +/* TODO: we can use this code when and if the bootloader ever changes this */ +#if 0 + pmemlen = (unsigned long)simple_strtoul(p, NULL, 0); +#else + pmemlen = 0x20000; +#endif + return 0; +} +early_param("pmemlen", early_param_pmemlen); + +/* + * Set up persistent memory. If we were given values, we patch the array of + * resources. Otherwise, persistent memory may be allocated anywhere at all. + */ +static void __init pmem_setup_resource(void) +{ + struct resource *resource; + resource = asic_resource_get("DiagPersistentMemory"); + + if (resource && pmemaddr && pmemlen) { + /* The address provided by bootloader is in kseg0. Convert to + * a bus address. */ + resource->start = phys_to_bus(pmemaddr - 0x80000000); + resource->end = resource->start + pmemlen - 1; + + pr_info("persistent memory: start=0x%x end=0x%x\n", + resource->start, resource->end); + } +} + +/* + * + * RESOURCE ACCESS FUNCTIONS + * + */ + +/* + * \brief asic_resource_get() retreives parameters used for allocating + * a platform resource. + * + * \param name - string to match resource + * + * \return resource ptr + * + * CANNOT BE NAMED platform_resource_get is this function name is already + * declared + */ +struct resource *asic_resource_get(const char *name) +{ + int i; + + for (i = 0; gpResources[i].flags != 0; i++) { + if (strcmp(gpResources[i].name, name) == 0) + return &gpResources[i]; + } + + return NULL; +} +EXPORT_SYMBOL(asic_resource_get); + +/* + * \brief platform_release_memory() . + * + * \param ptr - pointer to resource + * \param size - size of resource + * + * \return resource ptr + * + */ +void platform_release_memory(void *ptr, int size) +{ + unsigned long addr; + unsigned long end; + + addr = ((unsigned long)ptr + (PAGE_SIZE - 1)) & PAGE_MASK; + end = ((unsigned long)ptr + size) & PAGE_MASK; + + for (; addr < end; addr += PAGE_SIZE) { + ClearPageReserved(virt_to_page(__va(addr))); + init_page_count(virt_to_page(__va(addr))); + free_page((unsigned long)__va(addr)); + } +} +EXPORT_SYMBOL(platform_release_memory); + +/* + * + * FEATURE AVAILABILITY FUNCTIONS + * + */ +int platform_supports_dvr(void) +{ + return (gPlatformFeatures & DVR_CAPABLE) != 0; +} + +int platform_supports_ffs(void) +{ + return (gPlatformFeatures & FFS_CAPABLE) != 0; +} + +int platform_supports_pcie(void) +{ + return (gPlatformFeatures & PCIE_CAPABLE) != 0; +} + +int platform_supports_display(void) +{ + return (gPlatformFeatures & DISPLAY_CAPABLE) != 0; +} diff --git a/arch/mips/powertv/asic/asic_int.c b/arch/mips/powertv/asic/asic_int.c new file mode 100644 index 0000000..94b6ca9 --- /dev/null +++ b/arch/mips/powertv/asic/asic_int.c @@ -0,0 +1,146 @@ +/* + * Carsten Langgaard, carstenl@mips.com + * Copyright (C) 2000, 2001, 2004 MIPS Technologies, Inc. + * Copyright (C) 2001 Ralf Baechle + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * Routines for generic manipulation of the interrupts found on the MIPS + * Malta board. + * The interrupt controller is located in the South Bridge a PIIX4 device + * with two internal 82C95 interrupt controllers. + */ +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include + +static DEFINE_SPINLOCK(mips_irq_lock); + +static inline int get_int(void) +{ + unsigned long flags; + int irq; + + spin_lock_irqsave(&mips_irq_lock, flags); + + irq = (asic_read(Int_Int_Scan) >> 4) - 1; + + if (irq == 0 || irq >= NR_IRQS) + irq = -1; + + spin_unlock_irqrestore(&mips_irq_lock, flags); + + return irq; +} + +static void asic_irqdispatch(void) +{ + int irq; + + irq = get_int(); + if (irq < 0) + return; /* interrupt has already been cleared */ + + do_IRQ(irq); +} + +static inline int clz(unsigned long x) +{ + __asm__( + " .set push \n" + " .set mips32 \n" + " clz %0, %1 \n" + " .set pop \n" + : "=r" (x) + : "r" (x)); + + return x; +} + +/* + * Version of ffs that only looks at bits 12..15. + */ +static inline unsigned int irq_ffs(unsigned int pending) +{ +#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) + return -clz(pending) + 31 - CAUSEB_IP; +#else + unsigned int a0 = 7; + unsigned int t0; + + t0 = pending & 0xf000; + t0 = t0 < 1; + t0 = t0 << 2; + a0 = a0 - t0; + pending = pending << t0; + + t0 = pending & 0xc000; + t0 = t0 < 1; + t0 = t0 << 1; + a0 = a0 - t0; + pending = pending << t0; + + t0 = pending & 0x8000; + t0 = t0 < 1; + a0 = a0 - t0; + + return a0; +#endif +} + +/* + * TODO: check how it works under EIC mode. + */ +asmlinkage void plat_irq_dispatch(void) +{ + unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM; + int irq; + + irq = irq_ffs(pending); + + if (irq == CAUSEF_IP3) + asic_irqdispatch(); + else if (irq >= 0) + do_IRQ(irq); + else + spurious_interrupt(); +} + +void __init arch_init_irq(void) +{ + int i; + + asic_irq_init(); + + /* + * Initialize interrupt exception vectors. + */ + if (cpu_has_veic || cpu_has_vint) { + int nvec = cpu_has_veic ? 64 : 8; + for (i = 0; i < nvec; i++) + set_vi_handler(i, asic_irqdispatch); + } +} diff --git a/arch/mips/powertv/asic/irq_asic.c b/arch/mips/powertv/asic/irq_asic.c new file mode 100644 index 0000000..693abab --- /dev/null +++ b/arch/mips/powertv/asic/irq_asic.c @@ -0,0 +1,115 @@ +/* + * Copyright (C) 2005 Scientific Atlanta + * + * Modified from arch/mips/kernel/irq-rm7000.c: + * Copyright (C) 2003 Ralf Baechle + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ +#include +#include +#include + +#include +#include +#include + +#include + +static inline void unmask_asic_irq(unsigned int irq) +{ + unsigned long enable_bit; + + enable_bit = (1 << (irq & 0x1f)); + + switch (irq >> 5) { + case 0: + asic_write(asic_read(Ien_Int_0) | enable_bit, Ien_Int_0); + break; + case 1: + asic_write(asic_read(Ien_Int_1) | enable_bit, Ien_Int_1); + break; + case 2: + asic_write(asic_read(Ien_Int_2) | enable_bit, Ien_Int_2); + break; + case 3: + asic_write(asic_read(Ien_Int_3) | enable_bit, Ien_Int_3); + break; + default: + BUG(); + } +} + +static inline void mask_asic_irq(unsigned int irq) +{ + unsigned long disable_mask; + + disable_mask = ~(1 << (irq & 0x1f)); + + switch (irq >> 5) { + case 0: + asic_write(asic_read(Ien_Int_0) & disable_mask, Ien_Int_0); + break; + case 1: + asic_write(asic_read(Ien_Int_1) & disable_mask, Ien_Int_1); + break; + case 2: + asic_write(asic_read(Ien_Int_2) & disable_mask, Ien_Int_2); + break; + case 3: + asic_write(asic_read(Ien_Int_3) & disable_mask, Ien_Int_3); + break; + default: + BUG(); + } +} + +static struct irq_chip asic_irq_chip = { + .name = "ASIC Level", + .ack = mask_asic_irq, + .mask = mask_asic_irq, + .mask_ack = mask_asic_irq, + .unmask = unmask_asic_irq, + .eoi = unmask_asic_irq, +}; + +void __init asic_irq_init(void) +{ + int i; + + /* set priority to 0 */ + write_c0_status(read_c0_status() & ~(0x0000fc00)); + + asic_write(0, Ien_Int_0); + asic_write(0, Ien_Int_1); + asic_write(0, Ien_Int_2); + asic_write(0, Ien_Int_3); + + asic_write(0x0fffffff, Int_Level_3_3); + asic_write(0xffffffff, Int_Level_3_2); + asic_write(0xffffffff, Int_Level_3_1); + asic_write(0xffffffff, Int_Level_3_0); + asic_write(0xffffffff, Int_Level_2_3); + asic_write(0xffffffff, Int_Level_2_2); + asic_write(0xffffffff, Int_Level_2_1); + asic_write(0xffffffff, Int_Level_2_0); + asic_write(0xffffffff, Int_Level_1_3); + asic_write(0xffffffff, Int_Level_1_2); + asic_write(0xffffffff, Int_Level_1_1); + asic_write(0xffffffff, Int_Level_1_0); + asic_write(0xffffffff, Int_Level_0_3); + asic_write(0xffffffff, Int_Level_0_2); + asic_write(0xffffffff, Int_Level_0_1); + asic_write(0xffffffff, Int_Level_0_0); + + asic_write(0xf, Int_Int_Scan); + + /* + * Initialize interrupt handlers. + */ + for (i = 0; i < NR_IRQS; i++) + set_irq_chip_and_handler(i, &asic_irq_chip, handle_level_irq); +} diff --git a/arch/mips/powertv/cevt-powertv.c b/arch/mips/powertv/cevt-powertv.c new file mode 100644 index 0000000..cecbf40 --- /dev/null +++ b/arch/mips/powertv/cevt-powertv.c @@ -0,0 +1,247 @@ +/* + * Copyright (C) 2008 Scientific-Atlanta, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + */ +/* + * The file comes from kernel/cevt-r4k.c + */ +#include +#include +#include +#include + +#include +#include /* Not included in linux/time.h */ + +#include +#include "powertv-clock.h" + +static int mips_next_event(unsigned long delta, + struct clock_event_device *evt) +{ + unsigned int cnt; + int res; + +#ifdef CONFIG_MIPS_MT_SMTC + { + unsigned long flags, vpflags; + local_irq_save(flags); + vpflags = dvpe(); +#endif + cnt = read_c0_count(); + cnt += delta; + write_c0_compare(cnt); + res = ((int)(read_c0_count() - cnt) > 0) ? -ETIME : 0; +#ifdef CONFIG_MIPS_MT_SMTC + evpe(vpflags); + local_irq_restore(flags); + } +#endif + return res; +} + +static void mips_set_mode(enum clock_event_mode mode, + struct clock_event_device *evt) +{ + /* Nothing to do ... */ +} + +static DEFINE_PER_CPU(struct clock_event_device, mips_clockevent_device); +static int cp0_timer_irq_installed; + +/* + * Timer ack for an R4k-compatible timer of a known frequency. + */ +static void c0_timer_ack(void) +{ + write_c0_compare(read_c0_compare()); +} + +#ifndef CONFIG_SEPARATE_PCI_TI +/* + * Possibly handle a performance counter interrupt. + * Return true if the timer interrupt should not be checked + */ +static inline int handle_perf_irq(int r2) +{ + /* + * The performance counter overflow interrupt may be shared with the + * timer interrupt (cp0_perfcount_irq < 0). If it is and a + * performance counter has overflowed (perf_irq() == IRQ_HANDLED) + * and we can't reliably determine if a counter interrupt has also + * happened (!r2) then don't check for a timer interrupt. + */ + return (cp0_perfcount_irq < 0) && + perf_irq() == IRQ_HANDLED && + !r2; +} +#endif + +static irqreturn_t c0_compare_interrupt(int irq, void *dev_id) +{ + const int r2 = cpu_has_mips_r2; + struct clock_event_device *cd; + int cpu = smp_processor_id(); + +#ifndef CONFIG_SEPARATE_PCI_TI + /* + * Suckage alert: + * Before R2 of the architecture there was no way to see if a + * performance counter interrupt was pending, so we have to run + * the performance counter interrupt handler anyway. + */ + if (handle_perf_irq(r2)) + return IRQ_HANDLED; +#endif + + /* + * The same applies to performance counter interrupts. But with the + * above we now know that the reason we got here must be a timer + * interrupt. Being the paranoiacs we are we check anyway. + */ + if (!r2 || (read_c0_cause() & (1 << 30))) { + c0_timer_ack(); +#ifdef CONFIG_MIPS_MT_SMTC + if (cpu_data[cpu].vpe_id) + return IRQ_HANDLED; + cpu = 0; +#endif + cd = &per_cpu(mips_clockevent_device, cpu); + cd->event_handler(cd); + } + + return IRQ_HANDLED; +} + +static struct irqaction c0_compare_irqaction = { + .handler = c0_compare_interrupt, +#ifdef CONFIG_MIPS_MT_SMTC + .flags = IRQF_DISABLED, +#else + .flags = IRQF_DISABLED | IRQF_PERCPU, +#endif + .name = "timer", +}; + +#ifdef CONFIG_MIPS_MT_SMTC +DEFINE_PER_CPU(struct clock_event_device, smtc_dummy_clockevent_device); + +static void smtc_set_mode(enum clock_event_mode mode, + struct clock_event_device *evt) +{ +} + +static void mips_broadcast(cpumask_t mask) +{ + unsigned int cpu; + + for_each_cpu_mask(cpu, mask) + smtc_send_ipi(cpu, SMTC_CLOCK_TICK, 0); +} + +static void setup_smtc_dummy_clockevent_device(void) +{ + unsigned int cpu = smp_processor_id(); + struct clock_event_device *cd; + + cd = &per_cpu(smtc_dummy_clockevent_device, cpu); + + cd->name = "SMTC"; + cd->features = CLOCK_EVT_FEAT_DUMMY; + + /* Calculate the min / max delta */ + cd->mult = 0; + cd->shift = 0; + cd->max_delta_ns = 0; + cd->min_delta_ns = 0; + + cd->rating = 200; + cd->irq = 17; + cd->cpumask = cpumask_of_cpu(cpu); + + cd->set_mode = smtc_set_mode; + + cd->broadcast = mips_broadcast; + + clockevents_register_device(cd); +} +#endif + +static void mips_event_handler(struct clock_event_device *dev) +{ +} + +int __cpuinit powertv_clockevent_init(void) +{ + uint64_t mips_freq = mips_hpt_frequency; + unsigned int cpu = smp_processor_id(); + struct clock_event_device *cd; + unsigned int irq; + + if (!cpu_has_counter || !mips_hpt_frequency) + return -ENXIO; + +#ifdef CONFIG_MIPS_MT_SMTC + setup_smtc_dummy_clockevent_device(); + + /* + * On SMTC we only register VPE0's compare interrupt as clockevent + * device. + */ + if (cpu) + return 0; +#endif + + irq = kIrq_MipsTimer; + + cd = &per_cpu(mips_clockevent_device, cpu); + + cd->name = "MIPS"; + cd->features = CLOCK_EVT_FEAT_ONESHOT; + + /* Calculate the min / max delta */ + cd->mult = div_sc((unsigned long) mips_freq, NSEC_PER_SEC, 32); + cd->shift = 32; + cd->max_delta_ns = clockevent_delta2ns(0x7fffffff, cd); + cd->min_delta_ns = clockevent_delta2ns(0x300, cd); + + cd->rating = 300; + cd->irq = irq; +#ifdef CONFIG_MIPS_MT_SMTC + cd->cpumask = CPU_MASK_ALL; +#else + cd->cpumask = get_cpu_mask(cpu); +#endif + cd->set_next_event = mips_next_event; + cd->set_mode = mips_set_mode; + cd->event_handler = mips_event_handler; + + clockevents_register_device(cd); + + if (cp0_timer_irq_installed) + return 0; + + cp0_timer_irq_installed = 1; + +#ifdef CONFIG_MIPS_MT_SMTC +#define CPUCTR_IMASKBIT (0x100 << cp0_compare_irq) + setup_irq_smtc(irq, &c0_compare_irqaction, CPUCTR_IMASKBIT); +#else + setup_irq(irq, &c0_compare_irqaction); +#endif + + return 0; +} diff --git a/arch/mips/powertv/cmdline.c b/arch/mips/powertv/cmdline.c new file mode 100644 index 0000000..ee570a1 --- /dev/null +++ b/arch/mips/powertv/cmdline.c @@ -0,0 +1,51 @@ +/* + * Carsten Langgaard, carstenl@mips.com + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * Kernel command line creation using the prom monitor (YAMON) argc/argv. + */ +#include +#include + +#include + +#include "init.h" + +/* + * YAMON (32-bit PROM) pass arguments and environment as 32-bit pointer. + * This macro take care of sign extension. + */ +#define prom_argv(index) ((char *)(long)_prom_argv[(index)]) + +char * __init prom_getcmdline(void) +{ + return &(arcs_cmdline[0]); +} + +void __init prom_init_cmdline(void) +{ + int len; + + if (prom_argc != 1) + return; + + len = strlen(arcs_cmdline); + + arcs_cmdline[len] = ' '; + + strlcpy(arcs_cmdline + len + 1, (char *)_prom_argv, + COMMAND_LINE_SIZE - len - 1); +} diff --git a/arch/mips/powertv/csrc-powertv.c b/arch/mips/powertv/csrc-powertv.c new file mode 100644 index 0000000..c032660 --- /dev/null +++ b/arch/mips/powertv/csrc-powertv.c @@ -0,0 +1,84 @@ +/* + * Copyright (C) 2008 Scientific-Atlanta, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + */ +/* + * The file comes from kernel/csrc-r4k.c + */ +#include +#include + +#include /* Not included in linux/time.h */ + +#include +#include "powertv-clock.h" + +/* MIPS PLL Register Definitions */ +#define PLL_GET_M(x) (((x) >> 8) & 0x000000FF) +#define PLL_GET_N(x) (((x) >> 16) & 0x000000FF) +#define PLL_GET_P(x) (((x) >> 24) & 0x00000007) + +/* + * returns: Clock frequency in kHz + */ +unsigned int __init mips_get_pll_freq(void) +{ + unsigned int pll_reg, m, n, p; + unsigned int fin = 54000; /* Base frequency in kHz */ + unsigned int fout; + + /* Read PLL register setting */ + pll_reg = asic_read(MIPS_PLL_SETUP); + m = PLL_GET_M(pll_reg); + n = PLL_GET_N(pll_reg); + p = PLL_GET_P(pll_reg); + pr_info("MIPS PLL Register:0x%x M=%d N=%d P=%d\n", pll_reg, m, n, p); + + /* Calculate clock frequency = (2 * N * 54MHz) / (M * (2**P)) */ + fout = ((2 * n * fin) / (m * (0x01 << p))); + + pr_info("MIPS Clock Freq=%d kHz\n", fout); + + return fout; +} + +static cycle_t c0_hpt_read(struct clocksource *cs) +{ + return read_c0_count(); +} + +static struct clocksource clocksource_mips = { + .name = "powertv-counter", + .read = c0_hpt_read, + .mask = CLOCKSOURCE_MASK(32), + .flags = CLOCK_SOURCE_IS_CONTINUOUS, +}; + +void __init powertv_clocksource_init(void) +{ + unsigned int pll_freq = mips_get_pll_freq(); + + pr_info("CPU frequency %d.%02d MHz\n", pll_freq / 1000, + (pll_freq % 1000) * 100 / 1000); + + mips_hpt_frequency = pll_freq / 2 * 1000; + + clocksource_mips.rating = 200 + mips_hpt_frequency / 10000000; + + clocksource_set_clock(&clocksource_mips, mips_hpt_frequency); + + clocksource_register(&clocksource_mips); +} diff --git a/arch/mips/powertv/init.c b/arch/mips/powertv/init.c new file mode 100644 index 0000000..6d7b229 --- /dev/null +++ b/arch/mips/powertv/init.c @@ -0,0 +1,127 @@ +/* + * Copyright (C) 1999, 2000, 2004, 2005 MIPS Technologies, Inc. + * All rights reserved. + * Authors: Carsten Langgaard + * Maciej W. Rozycki + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * PROM library initialisation code. + */ +#include +#include +#include + +#include +#include +#include +#include +#include + +#include +#include +#include + +#include "init.h" + +int prom_argc; +int *_prom_argv, *_prom_envp; +unsigned long _prom_memsize; + +/* + * YAMON (32-bit PROM) pass arguments and environment as 32-bit pointer. + * This macro take care of sign extension, if running in 64-bit mode. + */ +#define prom_envp(index) ((char *)(long)_prom_envp[(index)]) + +char *prom_getenv(char *envname) +{ + char *result = NULL; + + if (_prom_envp != NULL) { + /* + * Return a pointer to the given environment variable. + * In 64-bit mode: we're using 64-bit pointers, but all pointers + * in the PROM structures are only 32-bit, so we need some + * workarounds, if we are running in 64-bit mode. + */ + int i, index = 0; + + i = strlen(envname); + + while (prom_envp(index)) { + if (strncmp(envname, prom_envp(index), i) == 0) { + result = prom_envp(index + 1); + break; + } + index += 2; + } + } + + return result; +} + +/* TODO: Verify on linux-mips mailing list that the following two */ +/* functions are correct */ +/* TODO: Copy NMI and EJTAG exception vectors to memory from the */ +/* BootROM exception vectors. Flush their cache entries. test it. */ + +static void __init mips_nmi_setup(void) +{ + void *base; +#if defined(CONFIG_CPU_MIPS32_R1) + base = cpu_has_veic ? + (void *)(CAC_BASE + 0xa80) : + (void *)(CAC_BASE + 0x380); +#elif defined(CONFIG_CPU_MIPS32_R2) + base = (void *)0xbfc00000; +#else +#error NMI exception handler address not defined +#endif +} + +static void __init mips_ejtag_setup(void) +{ + void *base; + +#if defined(CONFIG_CPU_MIPS32_R1) + base = cpu_has_veic ? + (void *)(CAC_BASE + 0xa00) : + (void *)(CAC_BASE + 0x300); +#elif defined(CONFIG_CPU_MIPS32_R2) + base = (void *)0xbfc00480; +#else +#error EJTAG exception handler address not defined +#endif +} + +void __init prom_init(void) +{ + prom_argc = fw_arg0; + _prom_argv = (int *) fw_arg1; + _prom_envp = (int *) fw_arg2; + _prom_memsize = (unsigned long) fw_arg3; + + board_nmi_handler_setup = mips_nmi_setup; + board_ejtag_handler_setup = mips_ejtag_setup; + + pr_info("\nLINUX started...\n"); + prom_init_cmdline(); + configure_platform(); + prom_meminit(); + +#ifndef CONFIG_BOOTLOADER_DRIVER + pr_info("\nBootloader driver isn't loaded...\n"); +#endif +} diff --git a/arch/mips/powertv/init.h b/arch/mips/powertv/init.h new file mode 100644 index 0000000..763472e --- /dev/null +++ b/arch/mips/powertv/init.h @@ -0,0 +1,10 @@ +/* + * Definitions from powertv init.c file + */ + +#ifndef _POWERTV_INIT_H +#define _POWERTV_INIT_H +extern int prom_argc; +extern int *_prom_argv; +extern unsigned long _prom_memsize; +#endif diff --git a/arch/mips/powertv/memory.c b/arch/mips/powertv/memory.c new file mode 100644 index 0000000..a57972f --- /dev/null +++ b/arch/mips/powertv/memory.c @@ -0,0 +1,183 @@ +/* + * Carsten Langgaard, carstenl@mips.com + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * PROM library functions for acquiring/using memory descriptors given to + * us from the YAMON. + */ +#include +#include +#include +#include +#include + +#include +#include +#include + +#include + +#include "init.h" + +/* Memory constants */ +#define KIBIBYTE(n) ((n) * 1024) /* Number of kibibytes */ +#define MEBIBYTE(n) ((n) * KIBIBYTE(1024)) /* Number of mebibytes */ +#define DEFAULT_MEMSIZE MEBIBYTE(256) /* If no memsize provided */ +#define LOW_MEM_MAX MEBIBYTE(252) /* Max usable low mem */ +#define RES_BOOTLDR_MEMSIZE MEBIBYTE(1) /* Memory reserved for bldr */ +#define BOOT_MEM_SIZE KIBIBYTE(256) /* Memory reserved for bldr */ +#define PHYS_MEM_START 0x10000000 /* Start of physical memory */ + +unsigned long ptv_memsize; + +void __init prom_meminit(void) +{ + char *memsize_str; + unsigned long memsize = 0; + unsigned int physend; + char cmdline[CL_SIZE], *ptr; + int low_mem; + int high_mem; + + /* Check the command line first for a memsize directive */ + strcpy(cmdline, arcs_cmdline); + ptr = strstr(cmdline, "memsize="); + if (ptr && (ptr != cmdline) && (*(ptr - 1) != ' ')) + ptr = strstr(ptr, " memsize="); + + if (ptr) { + memsize = memparse(ptr + 8, &ptr); + } else { + /* otherwise look in the environment */ + memsize_str = prom_getenv("memsize"); + + if (memsize_str != NULL) { + pr_info("prom memsize = %s\n", memsize_str); + memsize = simple_strtol(memsize_str, NULL, 0); + } + + if (memsize == 0) { + if (_prom_memsize != 0) { + memsize = _prom_memsize; + pr_info("_prom_memsize = 0x%lx\n", memsize); + /* add in memory that the bootloader doesn't + * report */ + memsize += BOOT_MEM_SIZE; + } else { + memsize = DEFAULT_MEMSIZE; + pr_info("Memsize not passed by bootloader, " + "defaulting to 0x%lx\n", memsize); + } + } + } + + /* Store memsize for diagnostic purposes */ + ptv_memsize = memsize; + + physend = PFN_ALIGN(&_end) - 0x80000000; + if (memsize > LOW_MEM_MAX) { + low_mem = LOW_MEM_MAX; + high_mem = memsize - low_mem; + } else { + low_mem = memsize; + high_mem = 0; + } + +/* + * TODO: We will use the hard code for memory configuration until + * the bootloader releases their device tree to us. + */ + /* + * Add the memory reserved for use by the bootloader to the + * memory map. + */ + add_memory_region(PHYS_MEM_START, RES_BOOTLDR_MEMSIZE, + BOOT_MEM_RESERVED); +#ifdef CONFIG_HIGHMEM_256_128 + /* + * Add memory in low for general use by the kernel and its friends + * (like drivers, applications, etc). + */ + add_memory_region(PHYS_MEM_START + RES_BOOTLDR_MEMSIZE, + LOW_MEM_MAX - RES_BOOTLDR_MEMSIZE, BOOT_MEM_RAM); + /* + * Add the memory reserved for reset vector. + */ + add_memory_region(0x1fc00000, MEBIBYTE(4), BOOT_MEM_RESERVED); + /* + * Add the memory reserved. + */ + add_memory_region(0x20000000, MEBIBYTE(1024 + 75), BOOT_MEM_RESERVED); + /* + * Add memory in high for general use by the kernel and its friends + * (like drivers, applications, etc). + * + * 75MB is reserved for devices which are using the memory in high. + */ + add_memory_region(0x60000000 + MEBIBYTE(75), MEBIBYTE(128 - 75), + BOOT_MEM_RAM); +#elif defined CONFIG_HIGHMEM_128_128 + /* + * Add memory in low for general use by the kernel and its friends + * (like drivers, applications, etc). + */ + add_memory_region(PHYS_MEM_START + RES_BOOTLDR_MEMSIZE, + MEBIBYTE(128) - RES_BOOTLDR_MEMSIZE, BOOT_MEM_RAM); + /* + * Add the memory reserved. + */ + add_memory_region(PHYS_MEM_START + MEBIBYTE(128), + MEBIBYTE(128 + 1024 + 75), BOOT_MEM_RESERVED); + /* + * Add memory in high for general use by the kernel and its friends + * (like drivers, applications, etc). + * + * 75MB is reserved for devices which are using the memory in high. + */ + add_memory_region(0x60000000 + MEBIBYTE(75), MEBIBYTE(128 - 75), + BOOT_MEM_RAM); +#else + /* Add low memory regions for either: + * - no-highmemory configuration case -OR- + * - highmemory "HIGHMEM_LOWBANK_ONLY" case + */ + /* + * Add memory for general use by the kernel and its friends + * (like drivers, applications, etc). + */ + add_memory_region(PHYS_MEM_START + RES_BOOTLDR_MEMSIZE, + low_mem - RES_BOOTLDR_MEMSIZE, BOOT_MEM_RAM); + /* + * Add the memory reserved for reset vector. + */ + add_memory_region(0x1fc00000, MEBIBYTE(4), BOOT_MEM_RESERVED); +#endif +} + +void __init prom_free_prom_memory(void) +{ + unsigned long addr; + int i; + + for (i = 0; i < boot_mem_map.nr_map; i++) { + if (boot_mem_map.map[i].type != BOOT_MEM_ROM_DATA) + continue; + + addr = boot_mem_map.map[i].addr; + free_init_pages("prom memory", + addr, addr + boot_mem_map.map[i].size); + } +} diff --git a/arch/mips/powertv/pci/Makefile b/arch/mips/powertv/pci/Makefile new file mode 100644 index 0000000..7bf9f8c --- /dev/null +++ b/arch/mips/powertv/pci/Makefile @@ -0,0 +1,26 @@ +# ***************************************************************************** +# Make file for PowerTV PCI driver +# +# Copyright (C) 2009 Scientific-Atlanta, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# +# ***************************************************************************** + +obj-y := + +obj-$(CONFIG_PCI) += pci.o fixup-powertv.o pciemod.o + + diff --git a/arch/mips/powertv/pci/fixup-powertv.c b/arch/mips/powertv/pci/fixup-powertv.c new file mode 100644 index 0000000..a75a9ab --- /dev/null +++ b/arch/mips/powertv/pci/fixup-powertv.c @@ -0,0 +1,14 @@ +#include +#include +#include "powertv-pci.h" + +int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) +{ + return asic_pcie_map_irq(dev, slot, pin); +} + +/* Do platform specific device initialization at pci_enable_device() time */ +int pcibios_plat_dev_init(struct pci_dev *dev) +{ + return 0; +} diff --git a/arch/mips/powertv/pci/pci.c b/arch/mips/powertv/pci/pci.c new file mode 100644 index 0000000..3358b5f --- /dev/null +++ b/arch/mips/powertv/pci/pci.c @@ -0,0 +1,35 @@ +/* + * Copyright (C) 1999, 2000, 2004, 2005 MIPS Technologies, Inc. + * All rights reserved. + * Authors: Carsten Langgaard + * Maciej W. Rozycki + * + * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org) + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * MIPS boards specific PCI support. + */ +#include +#include +#include +#include + +#include +#include "powertv-pci.h" + +void __init mips_pcibios_init(void) +{ + asic_pcie_init(); +} diff --git a/arch/mips/powertv/pci/pciemod.c b/arch/mips/powertv/pci/pciemod.c new file mode 100644 index 0000000..f152fc5 --- /dev/null +++ b/arch/mips/powertv/pci/pciemod.c @@ -0,0 +1,2921 @@ +/* ----------------------------------------------------------------------------- + * PCIE Module + * + * Copyright (C) 2000-2009 Scientific-Atlanta, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + * ----------------------------------------------------------------------------- + * + * File Name: pciemod.c + * + * Project: NGP + * + * Compiler: gnu C (gcc) + * + * Author(s): Tom Haman + * + * Description: Routines implementing kernel PCIE Module. + * + * Documents: PCIE Software Design Document + * + * NOTES: + * + * ----------------------------------------------------------------------------- + * History: + * Rev Level Date Name ECN# Description + * ----------------------------------------------------------------------------- + * 1.00 03/27/06 Tom Haman --- Initial version for NGP (Zeus) + * ----------------------------------------------------------------------------- + */ + + +/*platform and compile/usage definitions */ +#define DEBUG 1 +#define LOADABLE 0 + +#ifndef SA8KG5 +#define SA8KG5 1 +#endif + +#ifndef qDebug +#define qDebug DEBUG +#endif + + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* SA includes */ +#include +#include +#include + +#include "pcieregs.h" + + + +/****************************************************************************** + ****************************************************************************** + * these items would normally be in SA driver include files but since we are + * in the low level Kernel, they are defined here + ****************************************************************************** + ****************************************************************************** + * FROM "SAKernel.h" + */ +enum { + SA_OFF, + SA_FATAL, + SA_SEVERE, + SA_INFO, + SA_NOISE +} eSa_LogLevels; + +#define SA_LOG_TO_PRINT 1 + +#if ((defined(DEBUG) && DEBUG) || (defined(qDebug) && qDebug)) +#define SAPRINT(level, destflags, fmt...) do { \ + if ((level <= LogLevel) && ((destflags) & SA_LOG_TO_PRINT)) \ + printk(fmt); \ + } while (0) +#else +#define SAPRINT(level, destflags, fmt...) do {} while (0) +#endif + +MODULE_AUTHOR("Tom Haman"); +MODULE_DESCRIPTION("PCIE Module"); +MODULE_LICENSE("GPL"); + +/* File ID info (DO NOT EDIT) */ +const char PCIE_ident[] = "SA-Drv-Ident %name: %, %version: %, " + "%instance: %, %date_created: %, %created_by: %"; + +/******************************************************************************* + ******************************************************************************* + * LOADABLE Elements + ******************************************************************************* + ******************************************************************************/ +#if LOADABLE +/*Module Parameters */ +module_param(LogLevel, int, S_IRUGO); +MODULE_PARM_DESC(LogLevel, "Module debug log level"); +#endif /*LOADABLE */ + +/******************************************************************************* + ******************************************************************************* + * KERNEL Elements + ******************************************************************************* + ******************************************************************************/ +/*---------- Defines ------------ */ +#define pcieModule_Name "pcie" + +/*---------- Variables ------------ */ +static struct proc_dir_entry *PCIE_pProc; /* proc directory entry */ +static int LogLevel = SA_INFO; +static struct tPCIERegs *PCIE_RegsPtr; +static int PCIE_irqrequest_pcie; +static u32 PCIE_initialized; +static u32 *timerptr; +static spinlock_t PCIE_lock; + +/*---------- Non Private Module Prototypes ------------ */ +static int __init pcie_Init(void); +static void __exit pcie_Finalize(void); +static int asic_pcie_read_config(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 *val); +static int asic_pcie_write_config(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 val); + +/*---------- Private Module Prototypes ------------ */ +static irqreturn_t asic_pcie_process_interrupt(int irq, void *dev_id); +static u32 pcie_rc_cfg_read32(u32 type, u32 busnum, u32 devnum, u32 func_num, + u32 reg_num, u32 *dataptr); +static u32 pcie_rc_cfg_write32(u32 type, u32 busnum, u32 devnum, u32 func_num, + u32 reg_num, u32 *dataptr); +static void pcie_DumpRegs(void); +static int pcie_dumpcapability(int busnumber, int dev, int fn, int ptr); +static int pcie_dumpextendedcapability(int busnumber, int dev, int fn, int ptr); +static void pcie_delay(u32 ms); +static int pcie_reset_ethernet(void) ; +static void pcie_uSecDelay(u32 us); + +/*proc */ +static int pcie_WriteProc(struct file *pfile, const char __user *pbuff, + unsigned long bytecnt, void *data); +static int pcie_ReadProc(char *page, char **start, off_t off, int pageSize, + int *eof, void *data); + +/*interrupt */ +static u32 intdata[4]; +static int intcountslow[32], intcountshigh[32]; + +/*---------- Structures ----------- */ +static struct pci_ops asic_pci_ops = { + .read = asic_pcie_read_config, + .write = asic_pcie_write_config +}; + +static struct resource asic_mem_resource = { + .name = "ZEUS PCI MEM", + .flags = IORESOURCE_MEM, + .start = 0x08000000UL, + .end = 0x083FFFFFUL, + +}; + +static struct resource asic_io_resource = { + .name = "ASIC PCI I/O", + .start = 0x08400000UL, + .end = 0x087FFFFFUL, + .flags = IORESOURCE_IO, +}; + +struct pci_controller asic_controller = { + .pci_ops = &asic_pci_ops, + .io_resource = &asic_io_resource, + .mem_resource = &asic_mem_resource, + .io_offset = 0x00000000UL, + .mem_offset = 0x00000000UL +}; + + +/* VFD-SPI registers */ +struct tFPanel_regs { + u32 rSVFDControl; /* control register */ + u32 rSVFDStart; /* start register */ + u32 rSVFDFifo; /* Fifo register */ + u32 rSVFDKeyData; /* key data register */ + u32 rSVFDManReadData; /* manual read data register */ + u32 rSVFDReadCmd; /* read command register */ + u32 rSVFDStatus; /* status register */ + u32 rSVFDIntStat; /* interrupt status register */ + u32 rSVFDIntEnable; /* interrupt enable register */ +}; + +/*---------- Constants ------------ */ + +/*---------- Externals ------------ */ + +/*---------- Temporary Fixes ------------ */ +static inline u8 fix_readb(u8 *addr) +{ + u32 temp = (u32)addr ^ 3; + u8 *ptr; + ptr = (u8 *)temp; + return readb(ptr); +} +static inline u16 fix_readw(u16 *addr) +{ + u32 temp = (u32)addr ^ 2; + u16 *ptr; + ptr = (u16 *)temp; + return readw(ptr); +} +static inline u32 fix_readl(u32 *addr) +{ + return readl(addr); +} + +static inline void fix_writeb(u8 val, u8 *addr) +{ + u32 temp = (u32)addr ^ 3; + u8 *ptr; + ptr = (u8 *)temp; + writeb(val, ptr); +} +static inline void fix_writew(u16 val, u16 *addr) +{ + u32 temp = (u32)addr ^ 2; + u16 *ptr; + ptr = (u16 *)temp; + writew(val, ptr); +} +static inline void fix_writel(u32 val, u32 *addr) +{ + writel(val, addr); +} + +/* Convenience functions for performing logical operations on device + * registers */ +static void writel_or(u32 v, u32 *addr) +{ + writel(readl(addr) | v, addr); +} + +static void writel_and(u32 v, u32 *addr) +{ + writel(readl(addr) & v, addr); +} + + +#ifdef PCIE_PLL_FIX + + static struct tTBRegs *TB_RegsPtr; + static unsigned int scr_data_in[kSCR_DEPTH]; + + +/******************************************************************************* + * asic_pcie_reset + * + * If the box is a Zeus 1.0 box and the PHY layer's PLL has not acheived lock, + * then load the PLL with the correct value and then reset it. There is no way + * to reset the PHY layer by a conventional register command. Therefore, this + * backdoor method using the testbus to control the jtag port has been used. + * PCIe PHY layer to be reset after new PLL value has been loaded. + * + * + ******************************************************************************/ +void asic_shift_clk(void) +{ + /* clock low */ + writel_and(0xFFFFFFFD, &TB_RegsPtr->TEST_BUS_GPIO); + pcie_uSecDelay(20); + /* clock high */ + writel_or(0x2, &TB_RegsPtr->TEST_BUS_GPIO); + pcie_uSecDelay(20); +} + + +void asic_shift_in(void) +{ + int i; + + writel_or(0x30, &TB_RegsPtr->TEST_BUS_GPIO); /* Set SCR_OPCODE to a 3 */ + for (i = kSCR_DEPTH-1; i >= 0; i--) { + if (scr_data_in[i]) + /* Set SCR_IN high */ + writel_or(0x4, &TB_RegsPtr->TEST_BUS_GPIO); + else + /* Set SCR_IN lo */ + writel_and(0xFFFFFFFB, &TB_RegsPtr->TEST_BUS_GPIO); + asic_shift_clk(); + } + /* Set SCR_OPCODE to 2'b10 */ + writel_and(0xFFFFFFEF, &TB_RegsPtr->TEST_BUS_GPIO); + asic_shift_clk(); + /* Set SCR_OPCODE to zero */ + writel_and(0xFFFFFFCF, &TB_RegsPtr->TEST_BUS_GPIO); +} + +void asic_phy_reset(void) +{ + int i; + + /* Enable OEs */ + writel_or(0x17 | 0x107F00, &TB_RegsPtr->TEST_BUS_GPIO_CTL); + /* Set lower bits to zero */ + writel_and(0xFFFFF80, &TB_RegsPtr->TEST_BUS_GPIO); + /* Set mode bit */ + writel_or(0x8, &TB_RegsPtr->TEST_BUS_GPIO); + + for (i = kSCR_DEPTH-1; i >= 0; i--) + scr_data_in[i] = 0; + + scr_data_in[kSCR_DEPTH-93] = 1; + scr_data_in[kSCR_DEPTH-94] = 1; + + asic_shift_in(); + + /* Clear mode bit */ + writel_and(0xFFFFFFF7, &TB_RegsPtr->TEST_BUS_GPIO); + +} + +void asic_write_jtag(unsigned int tms, unsigned int tdi) +{ + /* drive bit 13 low (clk) */ + writel_and(0xFFFFDFFF, &TB_RegsPtr->TEST_BUS_GPIO); + + if (tms) /* set tms */ + writel_or(0x2, &TB_RegsPtr->TEST_BUS_GPIO); + else /* clear tms */ + writel_and(0xFFFFFFFD, &TB_RegsPtr->TEST_BUS_GPIO); + + if (tdi) /* set tdi */ + writel_or(0x4, &TB_RegsPtr->TEST_BUS_GPIO); + else /* clear tdi */ + writel_and(0xFFFFFFFB, &TB_RegsPtr->TEST_BUS_GPIO); + + pcie_uSecDelay(20); + /* drive bit 13 high (clk) */ + writel_or(0x00002000, &TB_RegsPtr->TEST_BUS_GPIO); + pcie_uSecDelay(20); +} + + +void asic_setup_jtag(unsigned int value) + +{ + int i; + + writel(0x17 | 0x300600, &TB_RegsPtr->TEST_BUS_GPIO_CTL); + + /*Select Controller 0 */ + /* drive bit 12, 13, 1, 2 low */ + writel_and(0xFFFFCFF9, &TB_RegsPtr->TEST_BUS_GPIO); + pcie_uSecDelay(20); + writel_or(0x00000004, &TB_RegsPtr->TEST_BUS_GPIO); /* tdI = 1 */ + pcie_uSecDelay(20); + writel_or(0x00002000, &TB_RegsPtr->TEST_BUS_GPIO); /* CLK = 1 */ + pcie_uSecDelay(20); + writel_and(0xFFFFDFFF, &TB_RegsPtr->TEST_BUS_GPIO); /* CLK = 0 */ + pcie_uSecDelay(20); + writel_or(0x00001000, &TB_RegsPtr->TEST_BUS_GPIO); /* trstn = 1 */ + writel_and(0xFFFFFFFB, &TB_RegsPtr->TEST_BUS_GPIO); /* tdi = 0 */ + pcie_uSecDelay(20); + writel_or(0x00002000, &TB_RegsPtr->TEST_BUS_GPIO); /* CLK = 1 */ + pcie_uSecDelay(20); + writel_and(0xFFFFDFFF, &TB_RegsPtr->TEST_BUS_GPIO); /* CLK = 0 */ + + asic_write_jtag(1, 0); + asic_write_jtag(1, 0); + asic_write_jtag(1, 0); + asic_write_jtag(0, 0); + asic_write_jtag(1, 0); + asic_write_jtag(1, 0); + asic_write_jtag(0, 0); + asic_write_jtag(0, 0); + asic_write_jtag(0, 0); + asic_write_jtag(0, 0); + asic_write_jtag(0, 0); + asic_write_jtag(0, 1); + asic_write_jtag(1, 0); + asic_write_jtag(1, 0); + asic_write_jtag(0, 0); + asic_write_jtag(1, 0); + asic_write_jtag(0, 0); + asic_write_jtag(0, 0); + + for (i = 0; i < 28 ; i++) + asic_write_jtag(0, 0); + + asic_write_jtag(0, value); + for (i = 0; i < 75 ; i++) + asic_write_jtag(0, 0); + + asic_write_jtag(1, 0); + asic_write_jtag(1, 0); + asic_write_jtag(0, 0); +} + +void asic_pcie_reset(void) +{ + asic_setup_jtag(1); + asic_phy_reset(); + asic_setup_jtag(0); +} + +#endif + + +/******************************************************************************* + ******************************************************************************* + * PCIE General Interface + ******************************************************************************* + ******************************************************************************* + ******************************************************************************* + * asic_pcie_init + * + * This API is called at power up and therefore must be exposed to other + * modules. + * + * Parameters - None + * + * Return Value - 0 or error + * + * Description: + * asic_pcie_init initializes the ASIC' PCI Express registers, obtains an IRQ + * from the Linux Kernel and registers the controller with the PCI System + * Software. + ******************************************************************************/ +int asic_pcie_init(void) +{ + unsigned int timeout_count; + int i; + + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, + "%s:%s:asic_pcie_init called.\n", pcieModule_Name, + __func__); + + if (!platform_supports_pcie()) + return -1; + + /*init spinlock */ + spin_lock_init(&PCIE_lock); + + /*map ASIC LS timer register */ + timerptr = (u32 *) (asic_reg_addr(Free_Running_Ctr_Lo)); + if (timerptr == 0) { + SAPRINT(SA_SEVERE, SA_LOG_TO_PRINT, + "%s:%s: failed to get timer register mapping\n", + pcieModule_Name, __func__); + return -1; + } + + /*map the registers */ + PCIE_RegsPtr = (struct tPCIERegs *)(asic_reg_addr(PCIe_Regs)); + + if (PCIE_RegsPtr == 0) { + SAPRINT(SA_SEVERE, SA_LOG_TO_PRINT, + "%s:%s: failed to get register mapping\n", + pcieModule_Name, __func__); + return -1; + } + + /*--------------- Hw initialization begins here ------------------- */ + /*reset ethernet chip */ + if (pcie_reset_ethernet() == -1) { + SAPRINT(SA_SEVERE, SA_LOG_TO_PRINT, + "%s:%s: failed to reset ethernet chip\n", + pcieModule_Name, __func__); + return -1; + } + +#ifdef PCIE_PLL_FIX + /* if PCIE_PLL_FIX is defined, then apply workaround to allow + * PCIe PHY layer to be reset after new PLL value has been loaded. + * subsequent versions of Zeus will have proper PLL default value + * set so that this will not be necessary. */ + + TB_RegsPtr = (struct tTBRegs *)(asic_reg_addr(Test_Bus)); + + if (TB_RegsPtr == 0) { + SAPRINT(SA_SEVERE, SA_LOG_TO_PRINT, + "%s:%s: failed to get TESTBUS register mapping\n", + pcieModule_Name, __func__); + return -1; + } + + { + int asicVersion; + + /* read CHIPVER0 Zeus register */ + asicVersion = (int)asic_read(CHIPVER0); + + /* if Zeus 1.0 */ + if (asicVersion == 0x11) { + /* if PLL is not locked, then apply workaround */ + if ((readl(&PCIE_RegsPtr->PCIX_PHY_READ_BACK) & + kPCIX_PHY_READ_BACK_Ready) == 0) { + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, + "%s:%s:Applying PCIe PHY PLL " + "workaround\n", pcieModule_Name, + __func__); + + /* load correct PHY PLL value */ + writel(0x19232300, + &PCIE_RegsPtr->PCIX_PHY_CONT_DATA1); + + /* reset PHY layer */ + pcie_delay(10); + asic_pcie_reset(); + } + } + } +#endif + + + /* Check PLL Lock */ + timeout_count = 0; + while ((readl(&PCIE_RegsPtr->PCIX_PHY_READ_BACK) & + kPCIX_PHY_READ_BACK_PllLock) == 0) { + timeout_count += 1; + if (timeout_count == 1000) + break; + pcie_delay(1); + } + + if (readl(&PCIE_RegsPtr->PCIX_PHY_READ_BACK) & + kPCIX_PHY_READ_BACK_PllLock) + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "%s:%s: PLL lock.\n", + pcieModule_Name, __func__); + else { + SAPRINT(SA_SEVERE, SA_LOG_TO_PRINT, + "%s:%s: PLL NOT LOCKED.\n", pcieModule_Name, + __func__); + PCIE_RegsPtr = 0; + return -1; + } + + /* Check PHY Ready */ + timeout_count = 0; + while ((readl(&PCIE_RegsPtr->PCIX_PHY_READ_BACK) + & kPCIX_PHY_READ_BACK_Ready) + == 0) { + timeout_count += 1; + if (timeout_count == 1000) + break; + pcie_delay(1); + } + + + if (readl(&PCIE_RegsPtr->PCIX_PHY_READ_BACK) & + kPCIX_PHY_READ_BACK_Ready) + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, + "%s:%s: PHY ready.\n", pcieModule_Name, __func__); + else { + SAPRINT(SA_SEVERE, SA_LOG_TO_PRINT, "%s:%s: PHY not ready.\n", + pcieModule_Name, __func__); + PCIE_RegsPtr = 0; + return -1; + } + + /* set port link control. Set link to be x1. (Zeus undocumented + * register) */ + writel_and(0x0000FFFF, &PCIE_RegsPtr->PCIX_CFG_SPACE_FUNC0[452]); + writel_or(0x00010000, &PCIE_RegsPtr->PCIX_CFG_SPACE_FUNC0[452]); + + /*All is well with the PHY, Set the control register */ + writel(kPCIX_CTL1_PCIE_FUNC0 | kPCIX_CTL1_PCIE_ROOT_COMPLEX | + kPCIX_CTL1_PCIE_SEL_CLOCK, &PCIE_RegsPtr->PCIX_CTL1); + + writel_or(kPCIX_CTL1_PCIE_LTSSM, &PCIE_RegsPtr->PCIX_CTL1); + pcie_delay(100); + + /* verify data link layer up */ + timeout_count = 0; + while ((readl(&PCIE_RegsPtr->PCIX_RDLH_LINK) & + kPCIX_RDLH_LINK_RdlhUp) == 0) { + timeout_count += 1; + if (timeout_count == 1000) + break; + pcie_delay(1); + } + + + if (readl(&PCIE_RegsPtr->PCIX_RDLH_LINK) & kPCIX_RDLH_LINK_RdlhUp) + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, + "%s:%s: Data Link Layer up.\n", pcieModule_Name, + __func__); + else { + SAPRINT(SA_SEVERE, SA_LOG_TO_PRINT, + "%s:%s: Data Link Layer not available.\n", + pcieModule_Name, __func__); + PCIE_RegsPtr = 0; + return -1; + } + + /* Going to map target space, map 8M, Zeus spec says we have 16 meg but + * can only get to 8M because of register limitations + * (limit to 8MB because HW only carries 23 bits) + * Memory Space from 0x08000000 - 0x083FFFFF */ + writel(0x00000000, &PCIE_RegsPtr->PCIX_T3TARG_BASE0); + /* 4 MB at PCIe add 0x08000000, Zeus add = 0x08000000 */ + writel(0x08000000 | 0x16, &PCIE_RegsPtr->PCIX_T3TARG_WIN0); + + /* I/O Space from 0x08400000 - 0x087FFFFF (ORed bit 23 is I/O enable */ + writel(0x00400000 | 0x00800000, &PCIE_RegsPtr->PCIX_T3TARG_BASE1); + /* 4 MB at PCIe add 0x08400000, Zeus add = 0x08400000 */ + writel(0x08400000 | 0x16, &PCIE_RegsPtr->PCIX_T3TARG_WIN1); + + /* T3 init config */ + writel(0x00000000, &PCIE_RegsPtr->PCIX_ACC_BAR0[4]); /* Reset BAR 0 */ + writel(0x00000000, &PCIE_RegsPtr->PCIX_ACC_BAR0[5]); /* Reset BAR 1 */ + + /* BAR0 - Zeus space at 0x00000000 in PCIe space */ + writel(0x40000000, &PCIE_RegsPtr->PCIX_CFG_SPACE_FUNC0[4]); + /* BAR1 - Unused */ + writel(0x0, &PCIE_RegsPtr->PCIX_CFG_SPACE_FUNC0[5]); + /* Mem Limit/Mem Base (0x00000000 - 0x00000000) */ + writel(0x00000000, &PCIE_RegsPtr->PCIX_CFG_SPACE_FUNC0[8]); + /* Bus Master/Memory Enable */ + writel_or(0x6, &PCIE_RegsPtr->PCIX_CFG_SPACE_FUNC0[1]); + + /* map all of memory for PCIE */ + /*0x00000000 - 0x7FFFFFFFF) */ + writel(0x00000000 | 31, &PCIE_RegsPtr->PCIX_FUNC0_USERBAR0); + + + SAPRINT(SA_NOISE, SA_LOG_TO_PRINT, + "%s:%s: PCIE Bus num %d, device num = %d\n.\n", + pcieModule_Name, __func__, PCIE_RegsPtr->PCIX_CFG_PBUS_NUM, + PCIE_RegsPtr->PCIX_CFG_PBUS_DEVNUM); + + + writel(0, &PCIE_RegsPtr->PCIX_CLIENT0_TLPTC); + writel(1, &PCIE_RegsPtr->PCIX_CLIENT0_TLPATTR); + writel(0, &PCIE_RegsPtr->PCIX_CLIENT0_TLPFUN); + + /*clear the interrupt counters */ + for (i = 0; i < 32; i++) { + intcountslow[i] = 0; + intcountshigh[i] = 0; + } + + /*unmask the interrupts that we care about (overall interrupt enable + * will be set when IRQ requested) */ + writel(~(kPCIX_IntLow_cfg_sys_err_rc0 | + kPCIX_IntLow_radm_cpl_timeout | + kPCIX_IntLow_cfg_aer_rc_err_int0 | + kPCIX_IntLow_radm_inta_asserted | + kPCIX_IntLow_radm_intb_asserted | + kPCIX_IntLow_radm_intc_asserted | + kPCIX_IntLow_radm_intd_asserted | + kPCIX_IntLow_radm_correctable_err | + kPCIX_IntLow_radm_nonfatal_err | + kPCIX_IntLow_radm_pm_pme | + kPCIX_IntLow_radm_cpl_dllp_abort | + kPCIX_IntLow_radm_cpl_tlp_abort | + kPCIX_IntLow_radm_cpl_ecrc_err | + kPCIX_IntLow_radm_fatal_err), + &PCIE_RegsPtr->PCIX_MASKRISE_LOW); + + writel(~(kPCIX_IntHigh_radm_inta_deasserted | + kPCIX_IntHigh_radm_intb_deasserted | + kPCIX_IntHigh_radm_intc_deasserted | + kPCIX_IntHigh_radm_pm_to_ack | + kPCIX_IntHigh_radm_cpl_error_int | + kPCIX_IntHigh_radm_intd_deasserted), + &PCIE_RegsPtr->PCIX_MASKRISE_HIGH); + + /*register controller */ +#if !LOADABLE + register_pci_controller(&asic_controller); +#endif /*!LOADABLE */ + + PCIE_initialized = 1; + return 0; +} +EXPORT_SYMBOL(asic_pcie_init); + + + + +/******************************************************************************* + * asic_pcie_read_config + * + * This API is called to read PCI Express Configuration Space registers. It is + * exposed to the PCI System Software. + * + * Parameters: + * *bus - pointer to pci_bus structure + * devfn - device function number + * where - configuration space register number + * size - byte, word, or doubleword + * *val - pointer to memory where read data is to be stored + * + * Return Value: + * returns: PCIBIOS_SUCCESSFUL if successful otherwise + * PCIBIOS_BAD_REGISTER_NUMBER or -1 + * + * Description: + * asic_pcie_read_config is called to read PCI Express Space Configuration + * registers. Configuration reads may be for byte, word or double word accesses. + * + * + ******************************************************************************/ +int asic_pcie_read_config(struct pci_bus *bus, unsigned int devfn, int where, + int size, u32 *val) +{ + u32 data = 0; + u32 rtn = 0; + unsigned long flags = 0; + int offset = where & 3; + u32 type; + + SAPRINT(SA_NOISE, SA_LOG_TO_PRINT, + "%s:%s:asic_pcie_read_config called (%x, %x, %x, %x).\n", + pcieModule_Name, __func__, bus->number, devfn, where, size); + + if (PCIE_initialized == 0) + return -1; + + /*error checks */ + if ((size == 2) && (where & 1)) + return PCIBIOS_BAD_REGISTER_NUMBER; + else if ((size == 4) && (where & 3)) + return PCIBIOS_BAD_REGISTER_NUMBER; + + spin_lock_irqsave(&PCIE_lock, flags); + + if (bus->number == 255) { + /*root complex, only one device and function in root complex */ + if (devfn == 0) + /*read the 32 bits directly */ + data = readl(&PCIE_RegsPtr-> + PCIX_CFG_SPACE_FUNC0[where >> 2]); + else + data = 0xFFFFFFFF; + } else { + /* For now only one bus, and one device on that bus and one + * function on that device (0, 0, 0). If we can ever get the + * ethernet chip to not respond to everything we can lose this + * check */ + if ((bus->number == 0) && (devfn == 0)) { + /*not root complex, type 0 or 1 msg */ + if (bus->number == 0) + type = kPCIE_RC_CFG_SETUP1_TYPE0; + else + type = kPCIE_RC_CFG_SETUP1_TYPE1; + + /*read 32 bits of data */ + rtn = pcie_rc_cfg_read32(type, bus->number, + PCI_SLOT(devfn), PCI_FUNC(devfn), where & ~0x3, + &data); + } else + data = 0xFFFFFFFF; + } + + /*check for error */ + if (rtn == -1) { + spin_unlock_irqrestore(&PCIE_lock, flags); + return PCIBIOS_SET_FAILED; + } + + /*right justify the data */ + switch (size) { + case 1: + if (offset == 3) + *val = (data >> 24) & 0xFF; + if (offset == 2) + *val = (data >> 16) & 0xFF; + if (offset == 1) + *val = (data >> 8) & 0xFF; + if (offset == 0) + *val = data & 0xFF; + break; + + case 2: + if (offset == 2) + *val = (data >> 16) & 0xFFFF; + if (offset == 0) + *val = data & 0xFFFF; + break; + + case 4: + *val = data; + break; + } + + + spin_unlock_irqrestore(&PCIE_lock, flags); + + SAPRINT(SA_NOISE, SA_LOG_TO_PRINT, + "%s:%s: READ PCI data %8x from bus %8x device %8x function " + "%8x register %8x size %d\n", pcieModule_Name, __func__, + *val, bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), where, + size); + + + return PCIBIOS_SUCCESSFUL; +} + + + + +/******************************************************************************* + * asic_pcie_write_config + * + * Parameters: + * *bus - pointer to pci_bus structure + * devfn - device function number + * where - configuration space register number + * size - byte, word, or doubleword + * val - data to be written + * + * Return Value: + * returns: PCIBIOS_SUCCESSFUL if successful otherwise + * PCIBIOS_BAD_REGISTER_NUMBER or -1 + * + * Description: + * asic_pcie_write_config is called to write PCI Express Configuration Space + * registers. Configuration writes may be for byte, word or double word + * accesses. + ******************************************************************************/ +int asic_pcie_write_config(struct pci_bus *bus, unsigned int devfn, int where, + int size, u32 val) +{ + u32 data = 0; + u32 rtn = 0; + unsigned long flags = 0; + int offset = where & 3; + u32 type; + + SAPRINT(SA_NOISE, SA_LOG_TO_PRINT, + "%s:%s:asic_pcie_write_config called (%x, %x, %x, %x, %x).\n", + pcieModule_Name, __func__, bus->number, devfn, where, size, + val); + + if (PCIE_initialized == 0) + return -1; + + /*error checks */ + if ((size == 2) && (where & 1)) + return PCIBIOS_BAD_REGISTER_NUMBER; + else if ((size == 4) && (where & 3)) + return PCIBIOS_BAD_REGISTER_NUMBER; + + spin_lock_irqsave(&PCIE_lock, flags); + + if (bus->number == 255) { + /* root complex, only one device and function in root complex */ + if (devfn != 0) { + spin_unlock_irqrestore(&PCIE_lock, flags); + return PCIBIOS_SET_FAILED; + } + + /*read the register first */ + data = readl(&PCIE_RegsPtr->PCIX_CFG_SPACE_FUNC0[where >> 2]); + + /*clear old value or in the new one */ + switch (size) { + case 1: + val = val & 0xFF; + if (offset == 3) + data = (data & 0x00FFFFFF) | (val << 24); + if (offset == 2) + data = (data & 0xFF00FFFF) | (val << 16); + if (offset == 1) + data = (data & 0xFFFF00FF) | (val << 8); + if (offset == 0) + data = (data & 0xFFFFFF00) | val ; + break; + + case 2: + val = val & 0xFFFF; + if (offset == 2) + data = (data & 0x0000FFFF) | (val << 16); + if (offset == 0) + data = (data & 0xFFFF0000) | val ; + break; + + case 4: + data = val; + break; + } + + /*write the new 32 bits */ + writel(data, &PCIE_RegsPtr->PCIX_CFG_SPACE_FUNC0[where >> 2]); + } else { + /*not root complex, type 0 or 1 msg */ + if (bus->number == 0) + type = kPCIE_RC_CFG_SETUP1_TYPE0; + else + type = kPCIE_RC_CFG_SETUP1_TYPE1; + + + /*read the register first */ + rtn = pcie_rc_cfg_read32(type, bus->number, PCI_SLOT(devfn), + PCI_FUNC(devfn), where & ~0x3, &data); + + /*check for error */ + if (rtn == -1) { + spin_unlock_irqrestore(&PCIE_lock, flags); + return PCIBIOS_SET_FAILED; + } + + /*clear old value or in the new one */ + switch (size) { + case 1: + val = val & 0xFF; + if (offset == 3) + data = (data & 0x00FFFFFF) | (val << 24); + if (offset == 2) + data = (data & 0xFF00FFFF) | (val << 16); + if (offset == 1) + data = (data & 0xFFFF00FF) | (val << 8); + if (offset == 0) + data = (data & 0xFFFFFF00) | val ; + break; + + case 2: + val = val & 0xFFFF; + if (offset == 2) + data = (data & 0x0000FFFF) | (val << 16); + if (offset == 0) + data = (data & 0xFFFF0000) | val ; + break; + + case 4: + data = val; + break; + } + + /*write the new 32 bits */ + pcie_rc_cfg_write32(type, bus->number, PCI_SLOT(devfn), + PCI_FUNC(devfn), where & ~0x3, &data); + } + + spin_unlock_irqrestore(&PCIE_lock, flags); + SAPRINT(SA_NOISE, SA_LOG_TO_PRINT, + "%s:%s: WROTE PCI data %8x to bus %8x device %8x function " + "%8x register %8x size %d\n", pcieModule_Name, __func__, + val, bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), where, + size); + + return PCIBIOS_SUCCESSFUL; +} + + + + +/******************************************************************************* + * asic_pcie_process_interrupt + * + * Parameters: + * Irq - interrupt number + * tbd - pointer to controller specific data (specifics tbd) + * pointer to register contents prior to interrupt + * + * Return Value: + * returns: IRQ_HANDLED or IRQ_NONE + * + * Description: + * asic_pcie_process_interrupt is called to process PCI Express interrupts. + * + ******************************************************************************/ +static irqreturn_t asic_pcie_process_interrupt(int irq, void *dev_id) +{ + int i; + u32 bit; + + if (PCIE_initialized == 0) + return IRQ_NONE; + + /*disable all pcie interrupts */ + writel_and(~kPCIX_CTL1_PCI_ENAB_INTS, &PCIE_RegsPtr->PCIX_CTL1); + + /*save the system data */ + intdata[0] = (u32)irq; + intdata[1] = (u32)dev_id; + + /*save interrupts pending */ + intdata[2] = readl(&PCIE_RegsPtr->PCIX_RISING_EVENT_LOW); + intdata[3] = readl(&PCIE_RegsPtr->PCIX_RISING_EVENT_HIGH); + + /*clear the pending interrupts (pulse high then low) */ + writel(intdata[2], &PCIE_RegsPtr->PCIX_CLRRISE_LOW); + writel(0, &PCIE_RegsPtr->PCIX_CLRRISE_LOW); + writel(intdata[3], &PCIE_RegsPtr->PCIX_CLRRISE_HIGH); + writel(0, &PCIE_RegsPtr->PCIX_CLRRISE_HIGH); + + /*adjust interrupt counters */ + bit = 0x01; + for (i = 0; i < 32; i++) { + if (intdata[2] & bit) + intcountslow[i]++; + if (intdata[3] & bit) + intcountshigh[i]++; + bit = bit << 1; + } + + /*enable all pcie interrupts */ + writel_or(kPCIX_CTL1_PCI_ENAB_INTS, &PCIE_RegsPtr->PCIX_CTL1); + + + return IRQ_HANDLED; +} + + + +/******************************************************************************* + * asic_pcie_map_irq + * + * Parameters: + * *dev - pointer to a pci_dev structure (not used) + * slot - slot number (not used) + * pin - pin number (not used) + * + * Return Value: + * Returns: IRQ number (always the PCI Express IRQ number) + * + * Description: + * asic_pcie_map_irq will return the IRQ number of the PCI Express interrupt. + * + ******************************************************************************/ +int asic_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) +{ + SAPRINT(SA_NOISE, SA_LOG_TO_PRINT, + "%s:%s:asic_pcie_map_irq called(%x, %x, %x).\n", + pcieModule_Name, __func__, (u32)dev, slot, pin); + + return kIrq_PCIExp; +} +EXPORT_SYMBOL(asic_pcie_map_irq); + + + +/******************************************************************************* + * pcie_rc_cfg_read32 + * + * Read 32 bit value from non RC config space + * + * Parameters: + * type - type 0 or 1 header + * busnum - bus number + * devnum - device number + * func_num - function number + * reg_num - register number + * *dataptr - pointer to where data value should be stored + * + * Return Value: 0 success -1 error + * + ******************************************************************************/ +u32 pcie_rc_cfg_read32(u32 type, u32 busnum, u32 devnum, u32 func_num, + u32 reg_num, u32 *dataptr) +{ + + unsigned int temp; + unsigned int stat; + u32 rtn = 0; + + SAPRINT(SA_NOISE, SA_LOG_TO_PRINT, + "%s:%s:pcie_rc_cfg_read32 called (%x, %x, %x, %x, %x, %x).\n", + pcieModule_Name, __func__, type, busnum, devnum, func_num, + reg_num, *dataptr); + + /*enter RC mode */ + writel_and(~kPCIX_CTL1_PCIE_TLP_ENABLE, &PCIE_RegsPtr->PCIX_CTL1); + writel(1, &PCIE_RegsPtr->PCIE_RC_CFG_MODE); + + /*setup for read */ + temp = (reg_num) | (func_num<<16) | (devnum<<19) | (busnum<<24); + writel(temp, &PCIE_RegsPtr->PCIE_RC_CFG_SETUP2); + writel(kPCIE_RC_CFG_SETUP1_CFG_ENAB_ALL_BYTES | (type<<2) | + kPCIE_RC_CFG_SETUP1_CFG_READ, + &PCIE_RegsPtr->PCIE_RC_CFG_SETUP1); + + /*read and wait for completion */ + stat = readl(&PCIE_RegsPtr->PCIE_RC_CFG_STAT); + while ((stat & 6) == 0) + stat = readl(&PCIE_RegsPtr->PCIE_RC_CFG_STAT); + + /*successful? */ + if (stat & 4) { + SAPRINT(SA_SEVERE, SA_LOG_TO_PRINT, + "%s:%s:pcie_rc_cfg_read32 timeout.\n", + pcieModule_Name, __func__); + rtn = -1; + } + + *dataptr = readl(&PCIE_RegsPtr->PCIE_RC_CFG_CPL_DATA); + + /* leave RC config mode */ + writel(0, &PCIE_RegsPtr->PCIE_RC_CFG_MODE); + writel_or(kPCIX_CTL1_PCIE_TLP_ENABLE, &PCIE_RegsPtr->PCIX_CTL1); + + SAPRINT(SA_NOISE, SA_LOG_TO_PRINT, + "%s:%s:pcie_rc_cfg_read32 read %x.\n", pcieModule_Name, + __func__, *dataptr); + return rtn; +} + + + + +/******************************************************************************* + * pcie_rc_cfg_write32 + * + * Write 32 bit value from non RC config space + * + * Parameters: + * type - type 0 or 1 header + * busnum - bus number + * devnum - device number + * func_num - function number + * reg_num - register number (word based!) + * *dataptr - pointer to where data value should be stored + + * Return Value: 0 success -1 error + * + ******************************************************************************/ +u32 pcie_rc_cfg_write32(u32 type, u32 busnum, u32 devnum, u32 func_num, + u32 reg_num, u32 *dataptr) +{ + + unsigned int temp; + u32 rtn = 0; + + SAPRINT(SA_NOISE, SA_LOG_TO_PRINT, + "%s:%s:pcie_rc_cfg_write32 called (%x, %x, %x, %x, %x, %x).\n", + pcieModule_Name, __func__, type, busnum, devnum, func_num, + reg_num, *dataptr); + + /*enter RC mode */ + writel_and(~kPCIX_CTL1_PCIE_TLP_ENABLE, &PCIE_RegsPtr->PCIX_CTL1); + writel(1, &PCIE_RegsPtr->PCIE_RC_CFG_MODE); + + /*setup for write */ + temp = (reg_num) | (func_num<<16) | (devnum<<19) | (busnum<<24); + writel(temp, &PCIE_RegsPtr->PCIE_RC_CFG_SETUP2); + writel(*dataptr, &PCIE_RegsPtr->PCIE_RC_CFG_WRITE_DATA); + + /*write the data */ + writel(kPCIE_RC_CFG_SETUP1_CFG_ENAB_ALL_BYTES | (type<<2) | + kPCIE_RC_CFG_SETUP1_CFG_WRITE, + &PCIE_RegsPtr->PCIE_RC_CFG_SETUP1); + + /* leave RC config mode */ + writel(0, &PCIE_RegsPtr->PCIE_RC_CFG_MODE); + writel_or(kPCIX_CTL1_PCIE_TLP_ENABLE, &PCIE_RegsPtr->PCIX_CTL1); + + return rtn; +} + + + + +/******************************************************************************* + * pcie_uSecDelay + * + * delay number of us passed + * + * Parameters: + * us - number of microseconds + * + * Return Value: none + * + ******************************************************************************/ +static void pcie_uSecDelay(u32 us) +{ + u32 start, stop, adder; + + /*check for no delay */ + if (us == 0) + return; + + /*read timer and calculate end time */ + start = *timerptr; + stop = start + (us * 3); /* rounded down from 3.375 */ + adder = 0; + + /*check for wrap */ + if (stop < start) { + stop += 0x7FFFFFFF; + adder = 0x7FFFFFFF; + } + +loop: + if (stop > (*timerptr + adder)) + goto loop; +} + + + + +/******************************************************************************* + * pcie_delay + * + * delay number of ms passed + * + * Parameters: + * ms - number of milliseconds + * + * Return Value: none + * + ******************************************************************************/ +static void pcie_delay(u32 ms) +{ + u32 start, stop, adder; + + /*check for no delay */ + if (ms == 0) + return; + + /*read timer and calculate end time */ + start = *timerptr; + stop = start + (ms * 3375); + adder = 0; + + /*check for wrap */ + if (stop < start) { + stop += 0x7FFFFFFF; + adder = 0x7FFFFFFF; + } + +loop: + if (stop > (*timerptr + adder)) + goto loop; +} + + + + +/******************************************************************************* + * pcie_reset_ethernet + * + * reset ethernet chip + * + * Parameters: none + * + * Return Value: -1 error, otherwise 0 + * + ******************************************************************************/ +static int pcie_reset_ethernet(void) +{ + /* virtual pointer to register region */ + struct tFPanel_regs *pFPanelRegs; + + /*Map VFD registers for ethernet reset line */ + pFPanelRegs = (struct tFPanel_regs *)(asic_reg_addr(Front_Panel)); + if (pFPanelRegs == 0) { + SAPRINT(SA_SEVERE, SA_LOG_TO_PRINT, + "%s:%s: failed to remap reset register\n", + pcieModule_Name, __func__); + return -1; + } + + writel(0x45, &pFPanelRegs->rSVFDFifo); + writel(0x107, &pFPanelRegs->rSVFDFifo); + writel(0x1, &pFPanelRegs->rSVFDStart); + + pcie_delay(140); + + writel(0x45, &pFPanelRegs->rSVFDFifo); + writel(0x10F, &pFPanelRegs->rSVFDFifo); + writel(0x1, &pFPanelRegs->rSVFDStart); + + return 0; +} + + + + +/******************************************************************************* + ******************************************************************************* + * DEBUG/INFORMATION Elements + ******************************************************************************* + ******************************************************************************* + ******************************************************************************* + * pcie_Init + * + * API Type - Kernel public + * + * Parameters - None + * + * Return Value - 0 or error + * + * Description: + * This is expected to be called from the Linux kernel during module + * installation. It has no functionality except to init the global semaphore + * + ******************************************************************************/ +static int __init pcie_Init(void) +{ +#if LOADABLE + int status = 0; + + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "%s:%s:pcie_Init called.\n", + pcieModule_Name, __func__); + + if (!platform_supports_pcie()) + return -1; + + /*init asic PCIE */ + status = asic_pcie_init(); + if (status != 0) { + SAPRINT(SA_SEVERE, SA_LOG_TO_PRINT, + "%s:%s:pcie_Init failed.\n", pcieModule_Name, + __func__); + return -EADDRINUSE; + } +#else + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "%s:%s:pcie_Init called.\n", + pcieModule_Name, __func__); + + if (!platform_supports_pcie()) + return -1; + +#endif /*LOADABLE */ + + + if (PCIE_initialized == 0) + return -1; + + + /*request the IRQ and enable interrupts if successful */ + PCIE_irqrequest_pcie = + request_irq(kIrq_PCIExp, asic_pcie_process_interrupt, + IRQF_SHARED, "PCIE Interrupt", (void *)PCIE_RegsPtr); + + if (PCIE_irqrequest_pcie != 0) + SAPRINT(SA_SEVERE, SA_LOG_TO_PRINT, + "%s:%s: failed to get IRQ (%x)\n", pcieModule_Name, + __func__, PCIE_irqrequest_pcie); + else { + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "%s:%s: Got IRQ (%x)\n", + pcieModule_Name, __func__, PCIE_irqrequest_pcie); + + /*enable interrupts */ + writel_or(kPCIX_CTL1_PCI_ENAB_INTS, &PCIE_RegsPtr->PCIX_CTL1); + } + + + + + /*Proc stuff */ + PCIE_pProc = create_proc_entry(pcieModule_Name, S_IRUGO | S_IWUGO, + NULL); + + if (PCIE_pProc != NULL) { + PCIE_pProc->read_proc = pcie_ReadProc; + PCIE_pProc->write_proc = pcie_WriteProc; + } else + SAPRINT(SA_SEVERE, SA_LOG_TO_PRINT, "%s:%s: proc not created\n", + pcieModule_Name, __func__); + + return 0; +} +module_init(pcie_Init); + + +/******************************************************************************* + * pcie_Finalize + * + * API Type - Kernel public. + * + * Parameters - None + * + * Return Value - None + * + * Description: + * This is expected to be called from the Linux kernel when the module is + * unloaded. It has no functionality. + * + ******************************************************************************/ +static void __exit pcie_Finalize(void) +{ + + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "%s:%s:pcie_Finalize called.\n", + pcieModule_Name, __func__); + + /*free IRQ */ + if (PCIE_irqrequest_pcie == 0) + free_irq(kIrq_PCIExp, 0); + + /*remove proc entry */ + if (PCIE_pProc != NULL) + remove_proc_entry(pcieModule_Name, NULL); +} +module_exit(pcie_Finalize); + + + + +/******************************************************************************* + * pcie_WriteProc + * + * pfile - pointer to the return buffer + * pbuff - not used + * bytecnt - not used + * pdata - length of the return buffer + * + * bytes filled in the return buffer + * + ******************************************************************************/ +static int pcie_WriteProc(struct file *pfile, const char __user *pbuff, + unsigned long bytecnt, void *data) +{ + u8 buffer[65]; + int cnt; + u32 addr; + u32 *ioaddr; + int i, stat, index; + struct pci_bus pseudobus; + int busnumber, dev, fn, where, size, val; + int rtn; + int saveloglevel; + int rval, wval; + u8 byte; + u8 *byteptr; + u16 word; + u16 *wordptr; + u32 dword; + u32 *dwordptr; + u32 savemem; + u32 led; + struct tFPanel_regs *pFPanelRegs; + + SAPRINT(SA_NOISE, SA_LOG_TO_PRINT, "%s: pcie WriteProc \n", + pcieModule_Name); + + /* get the buffer count, but limit it to 64 chars */ + cnt = (bytecnt < 64) ? bytecnt : 64; + + memset(buffer, 0, 65); + + /* get the users buffer */ + stat = copy_from_user(buffer, pbuff, cnt); + if (stat < 0) + return stat; + + pr_info("STRING= %s \n", buffer); + + /* if its the log level command then change the level */ + if (!strncmp(buffer, "LogLevel=", 8)) { + sscanf(buffer, "LogLevel=%d", &LogLevel); + + SAPRINT(SA_NOISE, SA_LOG_TO_PRINT, + "%s: Noise log \n", pcieModule_Name); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "%s: Info log \n", + pcieModule_Name); + SAPRINT(SA_SEVERE, SA_LOG_TO_PRINT, "%s: Severe log \n", + pcieModule_Name); + SAPRINT(SA_FATAL, SA_LOG_TO_PRINT, "%s: Fatal log \n", + pcieModule_Name); + + return cnt; + } + + /*set VFD ledn (ethernet reset is led4 (bit 3) */ + if (!strncmp(buffer, "Z=", 2)) { + sscanf(buffer, "Z=%x", &led); + pFPanelRegs = (struct tFPanel_regs *) + (asic_reg_addr(Front_Panel)); + writel(0x45, &pFPanelRegs->rSVFDFifo); + writel(0x100 | led, &pFPanelRegs->rSVFDFifo); + writel(0x1, &pFPanelRegs->rSVFDStart); + pr_info("set Led to %x\n", led); + return cnt; + } + + /*reset ethernet */ + if (!strncmp(buffer, "z=", 2)) { + pcie_reset_ethernet(); + return cnt; + } + + /*read register */ + if (!strncmp(buffer, "R=", 2)) { + ioaddr = (u32 *)PCIE_RegsPtr; + sscanf(buffer, "R=%x", &index); + pr_info("Data at PCIe[%x]= %x\n", index, ioaddr[index]); + return cnt; + } + + /*write register */ + if (!strncmp(buffer, "W=", 2)) { + ioaddr = (u32 *)PCIE_RegsPtr; + sscanf(buffer, "W=%x %x", &index, &val); + pr_info("Writing data at PCIe[%x] to %x\n", index, val); + ioaddr[index] = val; + return cnt; + } + + /*dump specific range of registers */ + if (!strncmp(buffer, "D=", 2)) { + ioaddr = (u32 *)PCIE_RegsPtr; + saveloglevel = LogLevel; + LogLevel = SA_OFF; + sscanf(buffer, "D=%x %x", &index, &val); + for (i = 0; i < val; i++) { + pr_info("Data at PCIe[%x] %x\n", index, + ioaddr[index]); + index++; + } + LogLevel = saveloglevel; + return cnt; + } + + /*dump all registers */ + if (!strncmp(buffer, "d=", 2)) { + pcie_DumpRegs(); + return cnt; + } + + /*interrupt counters */ + if (!strncmp(buffer, "N=", 2)) { + for (i = 0; i < 32; i++) { + if (intcountslow[i] != 0) + pr_info("Interrupt count low %d is %x\n", i, + intcountslow[i]); + } + for (i = 0; i < 32; i++) { + if (intcountshigh[i] != 0) + pr_info("Interrupt count high %d is %x\n", i, + intcountshigh[i]); + } + return cnt; + } + + /*read config word */ + if (!strncmp(buffer, "I=", 2)) { + sscanf(buffer, "I=%d %d %d %x %d", &busnumber, &dev, &fn, + &where, &size); + pseudobus.number = busnumber; + rtn = asic_pcie_read_config(&pseudobus, PCI_DEVFN(dev, fn), + where, size, &val); + if (rtn == PCIBIOS_SUCCESSFUL) + pr_info("Data at bus %d device %d function %d register " + "%x (size %d) was %x\n", busnumber, dev, fn, + where, size, (u32)val); + else + pr_err("asic_pcie_read_config failed (%d).\n", rtn); + return cnt; + } + + /*write config word */ + if (!strncmp(buffer, "O=", 2)) { + sscanf(buffer, "O=%d %d %d %x %d %x", &busnumber, &dev, &fn, + &where, &size, &val); + pseudobus.number = busnumber; + rtn = asic_pcie_write_config(&pseudobus, PCI_DEVFN(dev, fn), + where, size, val); + if (rtn == PCIBIOS_SUCCESSFUL) + pr_info("Data written to bus %d device %d function %d " + "register %x (size %d) was %x\n", busnumber, + dev, fn, where, size, (u32)val); + else + pr_err("asic_pcie_write_config failed (%d).\n", rtn); + return cnt; + } + + /*enumerate bus */ + if (!strncmp(buffer, "E=", 2)) { + saveloglevel = LogLevel; + LogLevel = SA_OFF; + sscanf(buffer, "E=%d", &busnumber); + pseudobus.number = busnumber; + for (dev = 0; dev < 32; dev++) { + rtn = asic_pcie_read_config(&pseudobus, + PCI_DEVFN(dev, 0), 0, 4, &val); + if (rtn == PCIBIOS_SUCCESSFUL) + pr_info("Data at bus %d device %d function 0 " + "register 0 (size 4) was %x\n", + busnumber, dev, (u32)val); + else + pr_err("asic_pcie_read_config failed (%d).\n", + rtn); + } + LogLevel = saveloglevel; + return cnt; + } + + /*dump Config area */ + if (!strncmp(buffer, "C=", 2)) { + saveloglevel = LogLevel; + LogLevel = SA_OFF; + sscanf(buffer, "C=%d %d %d", &busnumber, &dev, &fn); + pseudobus.number = busnumber; + where = 0; + pr_info("\n"); + for (where = 0; where < 4096; where = where+4) { + if ((where & 0x1F) == 0x00) + pr_info("\n%08x ", where); + rtn = asic_pcie_read_config(&pseudobus, + PCI_DEVFN(dev, fn), where, 4, &val); + if (rtn == PCIBIOS_SUCCESSFUL) + pr_info(" %08x", (u32)val); + else + pr_info(" xxxxxxxx"); + } + pr_info("\n"); + LogLevel = saveloglevel; + return cnt; + } + + /*dump Config area */ + if (!strncmp(buffer, "S=", 2)) { + int ptr; + + saveloglevel = LogLevel; + LogLevel = SA_OFF; + sscanf(buffer, "S=%d %d %d", &busnumber, &dev, &fn); + pseudobus.number = busnumber; + pr_info("Header:\n"); + for (where = 0; where < 64; where = where+4) { + if ((where & 0x1F) == 0x00) + pr_info("\n%08x ", where); + rtn = asic_pcie_read_config(&pseudobus, + PCI_DEVFN(dev, fn), where, 4, &val); + if (rtn == PCIBIOS_SUCCESSFUL) + pr_info(" %08x", (u32)val); + else + pr_info(" xxxxxxxx"); + } + + /*follow the capabilities */ + rtn = asic_pcie_read_config(&pseudobus, PCI_DEVFN(dev, fn), + 0x34, 1, &ptr); + if (rtn != PCIBIOS_SUCCESSFUL) { + LogLevel = saveloglevel; + return cnt; + } + + if (ptr != 0) { + while ((ptr != 0x100) && ((ptr & 0x03) == 0)) + ptr = pcie_dumpcapability(busnumber, dev, fn, + ptr); + + /*follow the extended capabilities */ + ptr = 0x100; + while ((ptr != 0x1000) && ((ptr & 0x03) == 0)) + ptr = pcie_dumpextendedcapability(busnumber, + dev, fn, ptr); + } + + pr_info("\n"); + LogLevel = saveloglevel; + return cnt; + } + + /*Root Complex R/W test */ + if (!strncmp(buffer, "T=", 2)) { + pr_info("Root Complex R/W test\n"); + pseudobus.number = 255; + + /*save old value */ + rtn = asic_pcie_read_config(&pseudobus, 0, 0x20, 4, &val); + if (rtn != PCIBIOS_SUCCESSFUL) { + pr_err("Setup failed\n"); + return cnt; + } + + /* bytewise test */ + wval = 0x10; + rtn = asic_pcie_write_config(&pseudobus, 0, 0x20, 1, wval); + if (rtn != PCIBIOS_SUCCESSFUL) { + pr_err("Write failed\n"); + return cnt; + } + rtn = asic_pcie_read_config(&pseudobus, 0, 0x20, 1, &rval); + if (rtn != PCIBIOS_SUCCESSFUL) { + pr_err("Read failed\n"); + return cnt; + } + if (wval != rval) { + pr_info("Test failed (%x, %x)\n", wval, rval); + return cnt; + } + + wval = 0x32; + rtn = asic_pcie_write_config(&pseudobus, 0, 0x21, 1, wval); + if (rtn != PCIBIOS_SUCCESSFUL) { + pr_err("Write failed\n"); + return cnt; + } + rtn = asic_pcie_read_config(&pseudobus, 0, 0x21, 1, &rval); + if (rtn != PCIBIOS_SUCCESSFUL) { + pr_err("Read failed\n"); + return cnt; + } + if (wval != rval) { + pr_err("Test failed (%x, %x)\n", wval, rval); + return cnt; + } + + wval = 0x40; + rtn = asic_pcie_write_config(&pseudobus, 0, 0x22, 1, wval); + if (rtn != PCIBIOS_SUCCESSFUL) { + pr_err("Write failed\n"); + return cnt; + } + rtn = asic_pcie_read_config(&pseudobus, 0, 0x22, 1, + &rval); + if (rtn != PCIBIOS_SUCCESSFUL) { + pr_err("Read failed\n"); + return cnt; + } + if (wval != rval) { + pr_err("Test failed (%x, %x)\n", wval, rval); + return cnt; + } + + wval = 0x65; + rtn = asic_pcie_write_config(&pseudobus, 0, 0x23, 1, wval); + if (rtn != PCIBIOS_SUCCESSFUL) { + pr_err("Write failed\n"); + return cnt; + } + rtn = asic_pcie_read_config(&pseudobus, 0, 0x23, 1, &rval); + if (rtn != PCIBIOS_SUCCESSFUL) { + pr_err("Read failed\n"); + return cnt; + } + if (wval != rval) { + pr_err("Test failed (%x, %x)\n", wval, rval); + return cnt; + } + + + /* 16 bit test */ + wval = 0x9870; + rtn = asic_pcie_write_config(&pseudobus, 0, 0x20, 2, wval); + if (rtn != PCIBIOS_SUCCESSFUL) { + pr_err("Write failed\n"); + return cnt; + } + rtn = asic_pcie_read_config(&pseudobus, 0, 0x20, 2, + &rval); + if (rtn != PCIBIOS_SUCCESSFUL) { + pr_err("Read failed\n"); + return cnt; + } + if (wval != rval) { + pr_err("Test failed (%x, %x)\n", wval, rval); + return cnt; + } + + wval = 0xCBA0; + rtn = asic_pcie_write_config(&pseudobus, 0, 0x22, 2, wval); + if (rtn != PCIBIOS_SUCCESSFUL) { + pr_err("Write failed\n"); + return cnt; + } + rtn = asic_pcie_read_config(&pseudobus, 0, 0x22, 2, &rval); + if (rtn != PCIBIOS_SUCCESSFUL) { + pr_err("Read failed\n"); + return cnt; + } + if (wval != rval) { + pr_err("Test failed (%x, %x)\n", wval, rval); + return cnt; + } + + /* 32 bit test */ + wval = 0x77605540; + rtn = asic_pcie_write_config(&pseudobus, 0, 0x20, 4, wval); + if (rtn != PCIBIOS_SUCCESSFUL) { + pr_err("Write failed\n"); + return cnt; + } + rtn = asic_pcie_read_config(&pseudobus, 0, 0x20, 4, &rval); + if (rtn != PCIBIOS_SUCCESSFUL) { + pr_err("Read failed\n"); + return cnt; + } + if (wval != rval) { + pr_err("Test failed (%x, %x)\n", wval, rval); + return cnt; + } + + + /*restore original value */ + rtn = asic_pcie_write_config(&pseudobus, 0, 0x20, 4, + val); + if (rtn != PCIBIOS_SUCCESSFUL) { + pr_err("Restore failed\n"); + return cnt; + } + + + pr_info("Test passed\n"); + + return cnt; + } + + /*Endpoint R/W test */ + if (!strncmp(buffer, "t=", 2)) { + pr_info("Endpoint R/W test\n"); + + pseudobus.number = 0; + + /*save old value */ + rtn = asic_pcie_read_config(&pseudobus, 0, 0x14, 4, &val); + if (rtn != PCIBIOS_SUCCESSFUL) { + pr_err("Setup failed\n"); + return cnt; + } + + + /* bytewise test */ + wval = 0x10; + rtn = asic_pcie_write_config(&pseudobus, 0, 0x14, 1, wval); + if (rtn != PCIBIOS_SUCCESSFUL) { + pr_err("Write failed\n"); + return cnt; + } + rtn = asic_pcie_read_config(&pseudobus, 0, 0x14, 1, &rval); + if (rtn != PCIBIOS_SUCCESSFUL) { + pr_err("Read failed\n"); + return cnt; + } + if (wval != rval) { + pr_err("Test failed (%x, %x)\n", wval, rval); + return cnt; + } + + wval = 0x32; + rtn = asic_pcie_write_config(&pseudobus, 0, 0x15, 1, wval); + if (rtn != PCIBIOS_SUCCESSFUL) { + pr_err("Write failed\n"); + return cnt; + } + rtn = asic_pcie_read_config(&pseudobus, 0, 0x15, 1, &rval); + if (rtn != PCIBIOS_SUCCESSFUL) { + pr_err("Read failed\n"); + return cnt; + } + if (wval != rval) { + pr_err("Test failed (%x, %x)\n", wval, rval); + return cnt; + } + + wval = 0x40; + rtn = asic_pcie_write_config(&pseudobus, 0, 0x16, 1, wval); + if (rtn != PCIBIOS_SUCCESSFUL) { + pr_err("Write failed\n"); + return cnt; + } + rtn = asic_pcie_read_config(&pseudobus, 0, 0x16, 1, &rval); + if (rtn != PCIBIOS_SUCCESSFUL) { + pr_err("Read failed\n"); + return cnt; + } + if (wval != rval) { + pr_err("Test failed (%x, %x)\n", wval, rval); + return cnt; + } + + wval = 0x65; + rtn = asic_pcie_write_config(&pseudobus, 0, 0x17, 1, wval); + if (rtn != PCIBIOS_SUCCESSFUL) { + pr_err("Write failed\n"); + return cnt; + } + rtn = asic_pcie_read_config(&pseudobus, 0, 0x17, 1, &rval); + if (rtn != PCIBIOS_SUCCESSFUL) { + pr_err("Read failed\n"); + return cnt; + } + if (wval != rval) { + pr_err("Test failed (%x, %x)\n", wval, rval); + return cnt; + } + + + + /* 16 bit test */ + wval = 0x9870; + rtn = asic_pcie_write_config(&pseudobus, 0, 0x14, 2, wval); + if (rtn != PCIBIOS_SUCCESSFUL) { + pr_err("Write failed\n"); + return cnt; + } + rtn = asic_pcie_read_config(&pseudobus, 0, 0x14, 2, &rval); + if (rtn != PCIBIOS_SUCCESSFUL) { + pr_err("Read failed\n"); + return cnt; + } + if (wval != rval) { + pr_err("Test failed (%x, %x)\n", wval, rval); + return cnt; + } + + wval = 0xCBA0; + rtn = asic_pcie_write_config(&pseudobus, 0, 0x16, 2, wval); + if (rtn != PCIBIOS_SUCCESSFUL) { + pr_err("Write failed\n"); + return cnt; + } + rtn = asic_pcie_read_config(&pseudobus, 0, 0x16, 2, &rval); + if (rtn != PCIBIOS_SUCCESSFUL) { + pr_err("Read failed\n"); + return cnt; + } + if (wval != rval) { + pr_err("Test failed (%x, %x)\n", wval, rval); + return cnt; + } + + + + /* 32 bit test */ + wval = 0x77605540; + rtn = asic_pcie_write_config(&pseudobus, 0, 0x14, 4, wval); + if (rtn != PCIBIOS_SUCCESSFUL) { + pr_err("Write failed\n"); + return cnt; + } + rtn = asic_pcie_read_config(&pseudobus, 0, 0x14, 4, &rval); + if (rtn != PCIBIOS_SUCCESSFUL) { + pr_err("Read failed\n"); + return cnt; + } + if (wval != rval) { + pr_err("Test failed (%x, %x)\n", wval, rval); + return cnt; + } + + + /*restore original value */ + rtn = asic_pcie_write_config(&pseudobus, 0, 0x20, 4, val); + if (rtn != PCIBIOS_SUCCESSFUL) { + pr_err("Restore failed\n"); + return cnt; + } + + + pr_info("Test passed\n"); + + return cnt; + } + + + /*Byte Order Memory Mapped Register test */ + if (!strncmp(buffer, "M=", 2)) { + pr_info("Byte Order Memory Mapped Register test\n"); + + byteptr = (u8 *)ioremap_nocache(0x8000000, 1024); + wordptr = (u16 *)byteptr; + dwordptr = (u32 *)byteptr; + + if (byteptr == 0) { + pr_err("Test failed. Unable to remap memory\n"); + return cnt; + } + + /*TEST1 */ + /*read memory mapped register as byte, word, and dword */ + byte = fix_readb(byteptr+0x11B); + word = fix_readw(wordptr+0x08D); + dword = fix_readl(dwordptr+0x046); + + if ((byte != 0xB7) || ((word & 0xFF00) != 0xB700) || + ((dword & 0xFF000000) != 0xB7000000)) { + iounmap(byteptr); + pr_err("Test failed. byte= %x word= %x dword= %x\n", + byte, word, dword); + return cnt; + } + + + /*TEST2 */ + /*seve original contents */ + savemem = fix_readl(dwordptr + 0x3); + + + /*write as a long */ + fix_writel(0x11223344, dwordptr + 0x03); + + /*read as bytes */ + byte = fix_readb(byteptr + 0x0C); + if (byte != 0x44) { + pr_err("Test Failed. Byte 0x11 (%x)\n", byte); + iounmap(byteptr); + fix_writel(savemem, dwordptr + 0x03); + return cnt; + } + byte = fix_readb(byteptr + 0x0D); + if (byte != 0x33) { + pr_err("Test Failed. Byte 0x22 (%x)\n", byte); + iounmap(byteptr); + fix_writel(savemem, dwordptr + 0x03); + return cnt; + } + byte = fix_readb(byteptr + 0x0E); + if (byte != 0x22) { + pr_err("Test Failed. Byte 0x33 (%x)\n", byte); + iounmap(byteptr); + fix_writel(savemem, dwordptr + 0x03); + return cnt; + } + byte = fix_readb(byteptr + 0x0F); + if (byte != 0x11) { + pr_err("Test Failed. Byte 0x44 (%x)\n", byte); + iounmap(byteptr); + fix_writel(savemem, dwordptr + 0x03); + return cnt; + } + + /*read as words */ + word = fix_readw(wordptr + 0x06); + if (word != 0x3344) { + pr_err("Test Failed. Word 0x1122 (%x)\n", word); + iounmap(byteptr); + fix_writel(savemem, dwordptr + 0x03); + return cnt; + } + word = fix_readw(wordptr + 0x07); + if (word != 0x1122) { + pr_err("Test Failed. Word 0x3344 (%x)\n", word); + iounmap(byteptr); + fix_writel(savemem, dwordptr + 0x03); + return cnt; + } + + /*read as a long */ + dword = fix_readl(dwordptr + 0x03); + if (dword != 0x11223344) { + pr_err("Test Failed. Dword 0x11223344 (%x)\n", dword); + iounmap(byteptr); + fix_writel(savemem, dwordptr + 0x03); + return cnt; + } + + + /*write as two words */ + fix_writew(0x8899, wordptr + 0x06); + fix_writew(0x6677, wordptr + 0x07); + + /*read as bytes */ + byte = fix_readb(byteptr + 0x0C); + if (byte != 0x99) { + pr_err("Test Failed. Byte 0x88 (%x)\n", byte); + iounmap(byteptr); + fix_writel(savemem, dwordptr + 0x03); + return cnt; + } + byte = fix_readb(byteptr + 0x0D); + if (byte != 0x88) { + pr_err("Test Failed. Byte 0x99 (%x)\n", byte); + iounmap(byteptr); + fix_writel(savemem, dwordptr + 0x03); + return cnt; + } + byte = fix_readb(byteptr + 0x0E); + if (byte != 0x77) { + pr_err("Test Failed. Byte 0x66 (%x)\n", byte); + iounmap(byteptr); + fix_writel(savemem, dwordptr + 0x03); + return cnt; + } + byte = fix_readb(byteptr + 0x0F); + if (byte != 0x66) { + pr_err("Test Failed. Byte 0x77 (%x)\n", byte); + iounmap(byteptr); + fix_writel(savemem, dwordptr + 0x03); + return cnt; + } + + /*read as words */ + word = fix_readw(wordptr + 0x06); + if (word != 0x8899) { + pr_err("Test Failed. Word 0x8899 (%x)\n", word); + iounmap(byteptr); + fix_writel(savemem, dwordptr + 0x03); + return cnt; + } + word = fix_readw(wordptr + 0x07); + if (word != 0x6677) { + pr_err("Test Failed. Word 0x6677 (%x)\n", word); + iounmap(byteptr); + fix_writel(savemem, dwordptr + 0x03); + return cnt; + } + + /*read as a long */ + dword = fix_readl(dwordptr + 0x03); + if (dword != 0x66778899) { + pr_err("Test Failed. Dword 0x88996677 (%x)\n", dword); + iounmap(byteptr); + fix_writel(savemem, dwordptr + 0x03); + return cnt; + } + + + /*write as four bytes */ + fix_writeb(0xFF, byteptr + 0x0C); + fix_writeb(0xEE, byteptr + 0x0D); + fix_writeb(0xDD, byteptr + 0x0E); + fix_writeb(0xCC, byteptr + 0x0F); + + /*read as bytes */ + byte = fix_readb(byteptr + 0x0C); + if (byte != 0xFF) { + pr_err("Test Failed. Byte 0xFF (%x)\n", byte); + iounmap(byteptr); + fix_writel(savemem, dwordptr + 0x03); + return cnt; + } + byte = fix_readb(byteptr + 0x0D); + if (byte != 0xEE) { + pr_err("Test Failed. Byte 0xEE (%x)\n", byte); + iounmap(byteptr); + fix_writel(savemem, dwordptr + 0x03); + return cnt; + } + byte = fix_readb(byteptr + 0x0E); + if (byte != 0xDD) { + pr_err("Test Failed. Byte 0xDD (%x)\n", byte); + iounmap(byteptr); + fix_writel(savemem, dwordptr + 0x03); + return cnt; + } + byte = fix_readb(byteptr + 0x0F); + if (byte != 0xCC) { + pr_err("Test Failed. Byte 0xCC (%x)\n", byte); + iounmap(byteptr); + fix_writel(savemem, dwordptr + 0x03); + return cnt; + } + + /*read as words */ + word = fix_readw(wordptr + 0x06); + if (word != 0xEEFF) { + pr_err("Test Failed. Word 0xFFEE (%x)\n", word); + iounmap(byteptr); + fix_writel(savemem, dwordptr + 0x03); + return cnt; + } + word = fix_readw(wordptr + 0x07); + if (word != 0xCCDD) { + pr_err("Test Failed. Word 0xDDCC (%x)\n", word); + iounmap(byteptr); + fix_writel(savemem, dwordptr + 0x03); + return cnt; + } + + /*read as a long */ + dword = fix_readl(dwordptr + 0x03); + if (dword != 0xCCDDEEFF) { + pr_err("Test Failed. Dword 0xCCDDEEFF (%x)\n", dword); + iounmap(byteptr); + fix_writel(savemem, dwordptr + 0x03); + return cnt; + } + + + /*restore test location */ + fix_writel(savemem, dwordptr + 0x03); + + + iounmap(byteptr); + + pr_info("Test passed\n"); + + return cnt; + } + + /*Memory Mapped Register dump */ + if (!strncmp(buffer, "H=", 2)) { + dwordptr = (u32 *)ioremap_nocache(0x8000000, 16384); + if (dwordptr == 0) { + pr_err("Failed. Unable to remap memory\n"); + return cnt; + } + + sscanf(buffer, "H=%x %x", &addr, &val); + addr = (addr + (u32)dwordptr) & 0xFFFFFFE0; + val |= 0xF; + pr_info("dump %x words of memory from %x\n", val, addr); + + for (i = 0; i < val; i++) { + if ((addr & 0x1F) == 0x00) + pr_info("\n%08x ", addr); + dword = fix_readl((u32 *)addr); + pr_info(" %08x", (u32)dword); + addr += 4; + } + pr_info("\n"); + + iounmap(dwordptr); + return cnt; + } + + + return cnt; +} + + + + +/******************************************************************************* + * pcie_ReadProc is called to dump HW registers + * + * page - not used + * start - not used + * off - not used + * count - not used + * eof - not used + * data - not used + * + * return - 0 or error if not enabled + * + * + ******************************************************************************/ +static int pcie_ReadProc(char *page, char **start, off_t off, int pageSize, + int *eof, void *data) +{ + SAPRINT(SA_NOISE, SA_LOG_TO_PRINT, "%s: pcie ReadProc \n", + pcieModule_Name); + + return 0; +} + + + + +/******************************************************************************* + * pcie_dumpcapability is called to dump a PCI capability structure + * + * bus - bus number + * dev - device number + * fun - function number + * ptr - pointer to beginning of device structure + * + * return - 0 or pointer to next capability structure + * + * + ******************************************************************************/ +int pcie_dumpcapability(int busnumber, int dev, int fn, int ptr) +{ + struct pci_bus pseudobus; + int id, nextptr; + int rtn, val, where; + int dumpptr; + + pseudobus.number = busnumber; + + /*read id */ + rtn = asic_pcie_read_config(&pseudobus, PCI_DEVFN(dev, fn), ptr, 1, + &id); + if (rtn != PCIBIOS_SUCCESSFUL) + return 0; + + /*read nextptr */ + rtn = asic_pcie_read_config(&pseudobus, PCI_DEVFN(dev, fn), ptr+1, 1, + &nextptr); + if (rtn != PCIBIOS_SUCCESSFUL) + return 0; + if (nextptr == 0) + nextptr = 0x100; + + pr_info("\nID= %x", id); + + dumpptr = ptr & 0xFFFFFFF0; + if (ptr != dumpptr) { + pr_info("\n%08x ", dumpptr); + for (where = dumpptr; where < ptr; where = where+4) + pr_info(" xxxxxxxx"); + } + + for (where = ptr; where < nextptr; where = where+4) { + if ((where & 0xF) == 0x00) + pr_info("\n%08x ", where); + rtn = asic_pcie_read_config(&pseudobus, PCI_DEVFN(dev, fn), + where, 4, &val); + if (rtn == PCIBIOS_SUCCESSFUL) + pr_info(" %08x", (u32)val); + else + pr_info(" xxxxxxxx"); + } + return nextptr; +} + + + + +/******************************************************************************* + * pcie_dumpextendedcapability is called to dump an extended PCI capability structure + * + * bus - bus number + * dev - device number + * fun - function number + * ptr - pointer to beginning of device structure + * + * return - 0 or pointer to next capability structure + * + * + ******************************************************************************/ +int pcie_dumpextendedcapability(int busnumber, int dev, int fn, int ptr) +{ + struct pci_bus pseudobus; + int id, nextptr; + int rtn, val, where; + + pseudobus.number = busnumber; + + /*read id */ + rtn = asic_pcie_read_config(&pseudobus, PCI_DEVFN(dev, fn), ptr, 2, + &id); + if (rtn != PCIBIOS_SUCCESSFUL) + return 0; + + /*read nextptr */ + rtn = asic_pcie_read_config(&pseudobus, PCI_DEVFN(dev, fn), ptr+2, 2, + &nextptr); + if (rtn != PCIBIOS_SUCCESSFUL) + return 0; + nextptr = nextptr >> 4; + if (nextptr == 0) + nextptr = 0x1000; + + pr_info("\nExID= %x", id); + + for (where = ptr; where < nextptr; where = where+4) { + if ((where & 0xF) == 0x00) + pr_info("\n%08x ", where); + rtn = asic_pcie_read_config(&pseudobus, PCI_DEVFN(dev, fn), + where, 4, &val); + if (rtn == PCIBIOS_SUCCESSFUL) + pr_info(" %08x", (u32)val); + else + pr_info(" xxxxxxxx"); + } + return nextptr; +} + + + + +/******************************************************************************* + * pcie_DumpRegs + * + * API Type - pcie private + * + * Parameters - none + * + * Return Value - none + * + * Description: + * Dups all registers + * + ******************************************************************************/ +void pcie_DumpRegs() +{ +int i; + + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "%s: pcie_DumpRegs \n", + pcieModule_Name); + + for (i = 0; i < 1024; i++) + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_CFG_SPACE_FUNC0[i], + readl(&PCIE_RegsPtr->PCIX_CFG_SPACE_FUNC0[i])); + for (i = 0; i < 1024; i++) + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_CFG_SPACE_FUNC1[i], + readl(&PCIE_RegsPtr->PCIX_CFG_SPACE_FUNC1[i])); + for (i = 0; i < 1024; i++) + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_CFG_SPACE_FUNC2[i], + readl(&PCIE_RegsPtr->PCIX_CFG_SPACE_FUNC2[i])); + for (i = 0; i < 1024; i++) + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_CFG_SPACE_FUNC3[i], + readl(&PCIE_RegsPtr->PCIX_CFG_SPACE_FUNC3[i])); + for (i = 0; i < 1024; i++) + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_ACC_BAR0[i], + readl(&PCIE_RegsPtr->PCIX_ACC_BAR0[i])); + for (i = 0; i < 1024; i++) + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_ACC_BAR1[i], + readl(&PCIE_RegsPtr->PCIX_ACC_BAR1[i])); + for (i = 0; i < 1024; i++) + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_ACC_BAR2[i], + readl(&PCIE_RegsPtr->PCIX_ACC_BAR2[i])); + for (i = 0; i < 1024; i++) + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_ACC_BAR3[i], + readl(&PCIE_RegsPtr->PCIX_ACC_BAR3[i])); + + + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_CTL1, + readl(&PCIE_RegsPtr->PCIX_CTL1)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_TRGT0_EN, + readl(&PCIE_RegsPtr->PCIX_TRGT0_EN)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_CLIENT0_ADDR_ALIGN_EN, + readl(&PCIE_RegsPtr->PCIX_CLIENT0_ADDR_ALIGN_EN)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_CLIENT0_TLPREQID, + readl(&PCIE_RegsPtr->PCIX_CLIENT0_TLPREQID)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_CLIENT0_TLP_ADEOT, + readl(&PCIE_RegsPtr->PCIX_CLIENT0_TLP_ADEOT)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_CLIENT0_TLPTC, + readl(&PCIE_RegsPtr->PCIX_CLIENT0_TLPTC)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_CLIENT0_TLPEP, + readl(&PCIE_RegsPtr->PCIX_CLIENT0_TLPEP)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_CLIENT0_TLPATTR, + readl(&PCIE_RegsPtr->PCIX_CLIENT0_TLPATTR)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_CLIENT0_TLPFUN, + readl(&PCIE_RegsPtr->PCIX_CLIENT0_TLPFUN)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_CLIENT1_ADDR_ALIGN_EN, + readl(&PCIE_RegsPtr->PCIX_CLIENT1_ADDR_ALIGN_EN)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_APP_UNLOCK, + readl(&PCIE_RegsPtr->PCIX_APP_UNLOCK)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_CLIENT1_TLP_BADEOT, + readl(&PCIE_RegsPtr->PCIX_CLIENT1_TLP_BADEOT)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_APPREQ, + readl(&PCIE_RegsPtr->PCIX_APPREQ)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_CLIENT1_TLPEP, + readl(&PCIE_RegsPtr->PCIX_CLIENT1_TLPEP)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_MEMRD_LOCKEN, + readl(&PCIE_RegsPtr->PCIX_MEMRD_LOCKEN)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_SYSCMD, + readl(&PCIE_RegsPtr->PCIX_SYSCMD)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_PHYCFG, + readl(&PCIE_RegsPtr->PCIX_PHYCFG)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_OUTBAND_PWRUP, + readl(&PCIE_RegsPtr->PCIX_OUTBAND_PWRUP)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_SYSINT, + readl(&PCIE_RegsPtr->PCIX_SYSINT)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_SYSATTEN, + readl(&PCIE_RegsPtr->PCIX_SYSATTEN)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_CLEAR_RST, + readl(&PCIE_RegsPtr->PCIX_CLEAR_RST)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_SOFT_RST, + readl(&PCIE_RegsPtr->PCIX_SOFT_RST)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_MASKRISE_LOW, + readl(&PCIE_RegsPtr->PCIX_MASKRISE_LOW)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_MASKRISE_HIGH, + readl(&PCIE_RegsPtr->PCIX_MASKRISE_HIGH)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_CLRRISE_LOW, + readl(&PCIE_RegsPtr->PCIX_CLRRISE_LOW)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_CLRRISE_HIGH, + readl(&PCIE_RegsPtr->PCIX_CLRRISE_HIGH)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_MSKFALL, + readl(&PCIE_RegsPtr->PCIX_MSKFALL)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_CLRFALL, + readl(&PCIE_RegsPtr->PCIX_CLRFALL)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_MSKLEV, + readl(&PCIE_RegsPtr->PCIX_MSKLEV)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_CLRLEV, + readl(&PCIE_RegsPtr->PCIX_CLRLEV)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_ABORT, + readl(&PCIE_RegsPtr->PCIX_ABORT)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_APPINIT, + readl(&PCIE_RegsPtr->PCIX_APPINIT)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_FUNC0_USERBAR0, + readl(&PCIE_RegsPtr->PCIX_FUNC0_USERBAR0)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_FUNC0_USERBAR2, + readl(&PCIE_RegsPtr->PCIX_FUNC0_USERBAR2)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_FUNC0_USERBAR4, + readl(&PCIE_RegsPtr->PCIX_FUNC0_USERBAR4)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_FUNC0_USEREXP, + readl(&PCIE_RegsPtr->PCIX_FUNC0_USEREXP)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_FUNC1_USERBAR0, + readl(&PCIE_RegsPtr->PCIX_FUNC1_USERBAR0)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_FUNC1_USERBAR2, + readl(&PCIE_RegsPtr->PCIX_FUNC1_USERBAR2)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_FUNC1_USERBAR4, + readl(&PCIE_RegsPtr->PCIX_FUNC1_USERBAR4)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_FUNC1_USEREXP, + readl(&PCIE_RegsPtr->PCIX_FUNC1_USEREXP)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_FUNC2_USERBAR0, + readl(&PCIE_RegsPtr->PCIX_FUNC2_USERBAR0)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_FUNC2_USERBAR2, + readl(&PCIE_RegsPtr->PCIX_FUNC2_USERBAR2)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_FUNC2_USERBAR4, + readl(&PCIE_RegsPtr->PCIX_FUNC2_USERBAR4)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_FUNC2_USEREXP, + readl(&PCIE_RegsPtr->PCIX_FUNC2_USEREXP)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_FUNC3_USERBAR0, + readl(&PCIE_RegsPtr->PCIX_FUNC3_USERBAR0)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_FUNC3_USERBAR2, + readl(&PCIE_RegsPtr->PCIX_FUNC3_USERBAR2)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_FUNC3_USERBAR4, + readl(&PCIE_RegsPtr->PCIX_FUNC3_USERBAR4)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_FUNC3_USEREXP, + readl(&PCIE_RegsPtr->PCIX_FUNC3_USEREXP)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_T3TARG_BASE0, + readl(&PCIE_RegsPtr->PCIX_T3TARG_BASE0)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_T3TARG_BASE1, + readl(&PCIE_RegsPtr->PCIX_T3TARG_BASE1)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_T3TARG_BASE2, + readl(&PCIE_RegsPtr->PCIX_T3TARG_BASE2)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_T3TARG_BASE3, + readl(&PCIE_RegsPtr->PCIX_T3TARG_BASE3)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_T3TARG_WIN0, + readl(&PCIE_RegsPtr->PCIX_T3TARG_WIN0)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_T3TARG_WIN1, + readl(&PCIE_RegsPtr->PCIX_T3TARG_WIN1)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_T3TARG_WIN2, + readl(&PCIE_RegsPtr->PCIX_T3TARG_WIN2)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_T3TARG_WIN3, + readl(&PCIE_RegsPtr->PCIX_T3TARG_WIN3)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIE_RC_CFG_MODE, + readl(&PCIE_RegsPtr->PCIE_RC_CFG_MODE)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIE_RC_CFG_SETUP1, + readl(&PCIE_RegsPtr->PCIE_RC_CFG_SETUP1)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIE_RC_CFG_SETUP2, + readl(&PCIE_RegsPtr->PCIE_RC_CFG_SETUP2)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIE_RC_CFG_WRITE_DATA, + readl(&PCIE_RegsPtr->PCIE_RC_CFG_WRITE_DATA)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIE_RC_CFG_STAT, + readl(&PCIE_RegsPtr->PCIE_RC_CFG_STAT)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIE_RC_CFG_CPL_DATA, + readl(&PCIE_RegsPtr->PCIE_RC_CFG_CPL_DATA)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIE_RC_CFG_CPLID, + readl(&PCIE_RegsPtr->PCIE_RC_CFG_CPLID)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_RISING_EVENT_LOW, + readl(&PCIE_RegsPtr->PCIX_RISING_EVENT_LOW)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_RISING_EVENT_HIGH, + readl(&PCIE_RegsPtr->PCIX_RISING_EVENT_HIGH)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_FALLING_EVENT, + readl(&PCIE_RegsPtr->PCIX_FALLING_EVENT)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_LEVEL_EVENT, + readl(&PCIE_RegsPtr->PCIX_LEVEL_EVENT)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_PHY_CONT_DATA1, + readl(&PCIE_RegsPtr->PCIX_PHY_CONT_DATA1)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_PHY_CONT_DATA2, + readl(&PCIE_RegsPtr->PCIX_PHY_CONT_DATA2)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_PHY_READ_BACK, + readl(&PCIE_RegsPtr->PCIX_PHY_READ_BACK)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_APPS_PM, + readl(&PCIE_RegsPtr->PCIX_APPS_PM)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_INT_EN, + readl(&PCIE_RegsPtr->PCIX_INT_EN)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_MASKRISE_LOW2, + readl(&PCIE_RegsPtr->PCIX_MASKRISE_LOW2)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_MASKRISE_HIGH2, + readl(&PCIE_RegsPtr->PCIX_MASKRISE_HIGH2)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_CLRRISE_LOW2, + readl(&PCIE_RegsPtr->PCIX_CLRRISE_LOW2)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_CLRRISE_HIGH2, + readl(&PCIE_RegsPtr->PCIX_CLRRISE_HIGH2)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_MSKFALL2, + readl(&PCIE_RegsPtr->PCIX_MSKFALL2)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_CLRFALL2, + readl(&PCIE_RegsPtr->PCIX_CLRFALL2)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_MSKLEV2, + readl(&PCIE_RegsPtr->PCIX_MSKLEV2)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_CLRLEV2, + readl(&PCIE_RegsPtr->PCIX_CLRLEV2)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_RISING_EVENT_LOW2, + readl(&PCIE_RegsPtr->PCIX_RISING_EVENT_LOW2)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_RISING_EVENT_HIGH2, + readl(&PCIE_RegsPtr->PCIX_RISING_EVENT_HIGH2)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_FALLING_EVENT2, + readl(&PCIE_RegsPtr->PCIX_FALLING_EVENT2)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_LEVEL_EVENT2, + readl(&PCIE_RegsPtr->PCIX_LEVEL_EVENT2)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_CFG_PBUS_NUM, + readl(&PCIE_RegsPtr->PCIX_CFG_PBUS_NUM)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_CFG_PBUS_DEVNUM, + readl(&PCIE_RegsPtr->PCIX_CFG_PBUS_DEVNUM)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_PMSTAT, + readl(&PCIE_RegsPtr->PCIX_PMSTAT)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_RADM, + readl(&PCIE_RegsPtr->PCIX_RADM)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_MSI_EN1, + readl(&PCIE_RegsPtr->PCIX_MSI_EN1)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_MSIADDR1_LOW, + readl(&PCIE_RegsPtr->PCIX_MSIADDR1_LOW)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_MSIADDR1_HIGH, + readl(&PCIE_RegsPtr->PCIX_MSIADDR1_HIGH)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_MSIDATA1, + readl(&PCIE_RegsPtr->PCIX_MSIDATA1)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_MSI_EN2, + readl(&PCIE_RegsPtr->PCIX_MSI_EN2)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_MSIADDR2_LOW, + readl(&PCIE_RegsPtr->PCIX_MSIADDR2_LOW)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_MSIADDR2_HIGH, + readl(&PCIE_RegsPtr->PCIX_MSIADDR2_HIGH)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_MSIDATA2, + readl(&PCIE_RegsPtr->PCIX_MSIDATA2)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_TESTBUS, + readl(&PCIE_RegsPtr->PCIX_TESTBUS)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_MSIX_ADDR_LOW, + readl(&PCIE_RegsPtr->PCIX_MSIX_ADDR_LOW)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_MSIX_ADDR_HIGH, + readl(&PCIE_RegsPtr->PCIX_MSIX_ADDR_HIGH)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_MSIXDATA, + readl(&PCIE_RegsPtr->PCIX_MSIXDATA)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_MSIX_EN, + readl(&PCIE_RegsPtr->PCIX_MSIX_EN)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_AER_INT_MSGNUM, + readl(&PCIE_RegsPtr->PCIX_AER_INT_MSGNUM)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_CAP_INT_MSTNUM, + readl(&PCIE_RegsPtr->PCIX_CAP_INT_MSTNUM)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_EMLCONT, + readl(&PCIE_RegsPtr->PCIX_EMLCONT)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_CFG_PHY_CONT0, + readl(&PCIE_RegsPtr->PCIX_CFG_PHY_CONT0)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_CFG_BAR0_START_0, + readl(&PCIE_RegsPtr->PCIX_CFG_BAR0_START_0)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_CFG_BAR0_START_1, + readl(&PCIE_RegsPtr->PCIX_CFG_BAR0_START_1)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_CFG_BAR0_START_2, + readl(&PCIE_RegsPtr->PCIX_CFG_BAR0_START_2)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_CFG_BAR0_START_3, + readl(&PCIE_RegsPtr->PCIX_CFG_BAR0_START_3)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_CFG_BAR0_START_4, + readl(&PCIE_RegsPtr->PCIX_CFG_BAR0_START_4)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_CFG_BAR0_START_5, + readl(&PCIE_RegsPtr->PCIX_CFG_BAR0_START_5)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_CFG_BAR0_START_6, + readl(&PCIE_RegsPtr->PCIX_CFG_BAR0_START_6)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_CFG_BAR0_START_7, + readl(&PCIE_RegsPtr->PCIX_CFG_BAR0_START_7)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_CFG_BAR0_LIMIT_0, + readl(&PCIE_RegsPtr->PCIX_CFG_BAR0_LIMIT_0)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_CFG_BAR0_LIMIT_2, + readl(&PCIE_RegsPtr->PCIX_CFG_BAR0_LIMIT_2)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_CFG_BAR0_LIMIT_3, + readl(&PCIE_RegsPtr->PCIX_CFG_BAR0_LIMIT_3)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_CFG_BAR0_LIMIT_4, + readl(&PCIE_RegsPtr->PCIX_CFG_BAR0_LIMIT_4)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_CFG_BAR0_LIMIT_5, + readl(&PCIE_RegsPtr->PCIX_CFG_BAR0_LIMIT_5)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_CFG_BAR0_LIMIT_6, + readl(&PCIE_RegsPtr->PCIX_CFG_BAR0_LIMIT_6)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_CFG_BAR0_LIMIT_7, + readl(&PCIE_RegsPtr->PCIX_CFG_BAR0_LIMIT_7)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_CFG_BAR1_START_0, + readl(&PCIE_RegsPtr->PCIX_CFG_BAR1_START_0)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_CFG_BAR1_START_1, + readl(&PCIE_RegsPtr->PCIX_CFG_BAR1_START_1)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_CFG_BAR1_START_2, + readl(&PCIE_RegsPtr->PCIX_CFG_BAR1_START_2)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_CFG_BAR1_START_3, + readl(&PCIE_RegsPtr->PCIX_CFG_BAR1_START_3)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_CFG_BAR1_START_4, + readl(&PCIE_RegsPtr->PCIX_CFG_BAR1_START_4)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_CFG_BAR1_START_5, + readl(&PCIE_RegsPtr->PCIX_CFG_BAR1_START_5)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_CFG_BAR1_START_6, + readl(&PCIE_RegsPtr->PCIX_CFG_BAR1_START_6)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_CFG_BAR1_START_7, + readl(&PCIE_RegsPtr->PCIX_CFG_BAR1_START_7)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_CFG_BAR1_LIMIT_0, + readl(&PCIE_RegsPtr->PCIX_CFG_BAR1_LIMIT_0)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_CFG_BAR1_LIMIT_1, + readl(&PCIE_RegsPtr->PCIX_CFG_BAR1_LIMIT_1)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_CFG_BAR1_LIMIT_2, + readl(&PCIE_RegsPtr->PCIX_CFG_BAR1_LIMIT_2)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_CFG_BAR1_LIMIT_3, + readl(&PCIE_RegsPtr->PCIX_CFG_BAR1_LIMIT_3)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_CFG_BAR1_LIMIT_4, + readl(&PCIE_RegsPtr->PCIX_CFG_BAR1_LIMIT_4)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_CFG_BAR1_LIMIT_5, + readl(&PCIE_RegsPtr->PCIX_CFG_BAR1_LIMIT_5)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_CFG_BAR1_LIMIT_6, + readl(&PCIE_RegsPtr->PCIX_CFG_BAR1_LIMIT_6)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_CFG_BAR1_LIMIT_7, + readl(&PCIE_RegsPtr->PCIX_CFG_BAR1_LIMIT_7)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_CFG_EXP_ROM_START_0, + readl(&PCIE_RegsPtr->PCIX_CFG_EXP_ROM_START_0)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_CFG_EXP_ROM_START_1, + readl(&PCIE_RegsPtr->PCIX_CFG_EXP_ROM_START_1)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_CFG_EXP_ROM_START_2, + readl(&PCIE_RegsPtr->PCIX_CFG_EXP_ROM_START_2)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_CFG_EXP_ROM_START_3, + readl(&PCIE_RegsPtr->PCIX_CFG_EXP_ROM_START_3)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_CFG_EXP_ROM_LIMIT_0, + readl(&PCIE_RegsPtr->PCIX_CFG_EXP_ROM_LIMIT_0)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_CFG_EXP_ROM_LIMIT_1, + readl(&PCIE_RegsPtr->PCIX_CFG_EXP_ROM_LIMIT_1)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_CFG_EXP_ROM_LIMIT_2, + readl(&PCIE_RegsPtr->PCIX_CFG_EXP_ROM_LIMIT_2)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_CFG_EXP_ROM_LIMIT_3, + readl(&PCIE_RegsPtr->PCIX_CFG_EXP_ROM_LIMIT_3)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_XLMH_STATE, + readl(&PCIE_RegsPtr->PCIX_XLMH_STATE)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_RDLH_LINK, + readl(&PCIE_RegsPtr->PCIX_RDLH_LINK)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_CFG_BUS_MSTR, + readl(&PCIE_RegsPtr->PCIX_CFG_BUS_MSTR)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_CFG_MEM, + readl(&PCIE_RegsPtr->PCIX_CFG_MEM)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_CFG_MSI, + readl(&PCIE_RegsPtr->PCIX_CFG_MSI)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_CFG_MAX, + readl(&PCIE_RegsPtr->PCIX_CFG_MAX)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_PM_CURST, + readl(&PCIE_RegsPtr->PCIX_PM_CURST)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_RADM_MSGCTL, + readl(&PCIE_RegsPtr->PCIX_RADM_MSGCTL)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_RADM_MSGPAY, + readl(&PCIE_RegsPtr->PCIX_RADM_MSGPAY)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_RADM_PWR, + readl(&PCIE_RegsPtr->PCIX_RADM_PWR)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_RADM_CORR, + readl(&PCIE_RegsPtr->PCIX_RADM_CORR)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_RTLH_UPD, + readl(&PCIE_RegsPtr->PCIX_RTLH_UPD)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_RTLD_DATA, + readl(&PCIE_RegsPtr->PCIX_RTLD_DATA)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_CXPL_DEBUGLO, + readl(&PCIE_RegsPtr->PCIX_CXPL_DEBUGLO)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_CXPL_DEBUGHI, + readl(&PCIE_RegsPtr->PCIX_CXPL_DEBUGHI)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_RADM_CPL_0, + readl(&PCIE_RegsPtr->PCIX_RADM_CPL_0)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_RADM_CPL_1, + readl(&PCIE_RegsPtr->PCIX_RADM_CPL_1)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_RADM_CPL_2, + readl(&PCIE_RegsPtr->PCIX_RADM_CPL_2)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_RADM_CPL_3, + readl(&PCIE_RegsPtr->PCIX_RADM_CPL_3)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_CFG_RCB, + readl(&PCIE_RegsPtr->PCIX_CFG_RCB)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_VEN_MSG_STAT1, + readl(&PCIE_RegsPtr->PCIX_VEN_MSG_STAT1)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_VEN_MSG_DATALO, + readl(&PCIE_RegsPtr->PCIX_VEN_MSG_DATALO)); + SAPRINT(SA_INFO, SA_LOG_TO_PRINT, "register at %8x = %8x\n", + (u32)&PCIE_RegsPtr->PCIX_VEN_MSG_DATAHI, + readl(&PCIE_RegsPtr->PCIX_VEN_MSG_DATAHI)); +} + diff --git a/arch/mips/powertv/pci/pcieregs.h b/arch/mips/powertv/pci/pcieregs.h new file mode 100644 index 0000000..3200256 --- /dev/null +++ b/arch/mips/powertv/pci/pcieregs.h @@ -0,0 +1,333 @@ +/* ---------------------------------------------------------------------------- + * PCIE Module + * + * Copyright (C) 2000-2009 Scientific-Atlanta, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + * ---------------------------------------------------------------------------- + * + * File Name: pcieregs.h + * + * Project: NGP + * + * Compiler: gnu C (gcc) + * + * Author(s): Tom Haman + * + * Description: This header file defines the registers for the PCIE + * section of the Zeus Asic. + * + * Documents: PCIE Software Design Document + * + * NOTES: + * + * ---------------------------------------------------------------------------- + * History: + * Rev Level Date Name ECN# Description + * ---------------------------------------------------------------------------- + * 1.00 02/15/06 Tom Haman --- Initial version for NGP (Zeus) + * ---------------------------------------------------------------------------- + */ + +#ifndef _PCIE_REGS_H_ +#define _PCIE_REGS_H_ + +#define PCIE_PLL_FIX +#ifdef PCIE_PLL_FIX +/* if PCIE_PLL_FIX is defined, then apply workaround to allow + * PCIe PHY layer to be reset after new PLL value has been loaded. + * subsequent versions of Zeus will have proper PLL default value + * set so that this will not be necessary. */ + +/* TESTBUS Registers */ +#define kSCR_DEPTH 640 + +struct tTBRegs { + u32 TEST_BUS_GPIO_CTL; /* 091A0238 */ + u32 TEST_BUS_GPIO; /* 091A023C */ +}; +#endif + +/* PCIE Registers, Offsets and Bit Definitions */ +struct tPCIERegs { + u32 PCIX_CFG_SPACE_FUNC0[1024]; /*09200000 thru 09200FFF */ + u32 PCIX_CFG_SPACE_FUNC1[1024]; /*09201000 thru 09201FFF */ + u32 PCIX_CFG_SPACE_FUNC2[1024]; /*09202000 thru 09202FFF */ + u32 PCIX_CFG_SPACE_FUNC3[1024]; /*09203000 thru 09203FFF */ + + u32 filler1[4096]; /*09204000 thru 09207FFF */ + + u32 PCIX_ACC_BAR0[1024]; /*09208000 thru 09208FFF */ + u32 PCIX_ACC_BAR1[1024]; /*09209000 thru 09209FFF */ + u32 PCIX_ACC_BAR2[1024]; /*0920A000 thru 0920AFFF */ + u32 PCIX_ACC_BAR3[1024]; /*0920B000 thru 0920BFFF */ + + u32 filler2[4096]; /*0920C000 thru 0920FFFF */ + + u32 PCIX_CTL1; /*09210000 */ + u32 PCIX_TRGT0_EN; /*09210004 */ + u32 PCIX_CLIENT0_ADDR_ALIGN_EN; /*09210008 */ + u32 PCIX_CLIENT0_TLPREQID; /*0921000C */ + u32 PCIX_CLIENT0_TLP_ADEOT; /*09210010 */ + u32 PCIX_CLIENT0_TLPTC; /*09210014 */ + u32 PCIX_CLIENT0_TLPEP; /*09210018 */ + u32 PCIX_CLIENT0_TLPATTR; /*0921001C */ + u32 PCIX_CLIENT0_TLPFUN; /*09210020 */ + u32 PCIX_CLIENT1_ADDR_ALIGN_EN; /*09210024 */ + u32 PCIX_APP_UNLOCK; /*09210028 */ + u32 PCIX_CLIENT1_TLP_BADEOT; /*0921002C */ + u32 PCIX_APPREQ; /*09210030 */ + u32 PCIX_CLIENT1_TLPEP; /*09210034 */ + u32 PCIX_MEMRD_LOCKEN; /*09210038 */ + u32 PCIX_SYSCMD; /*0921003C */ + u32 PCIX_PHYCFG; /*09210040 */ + u32 PCIX_OUTBAND_PWRUP; /*09210044 */ + u32 PCIX_SYSINT; /*09210048 */ + u32 PCIX_SYSATTEN; /*0921004C */ + u32 PCIX_CLEAR_RST; /*09210050 */ + u32 PCIX_SOFT_RST; /*09210054 */ + u32 PCIX_MASKRISE_LOW; /*09210058 */ + u32 PCIX_MASKRISE_HIGH; /*0921005C */ + u32 PCIX_CLRRISE_LOW; /*09210060 */ + u32 PCIX_CLRRISE_HIGH; /*09210064 */ + u32 PCIX_MSKFALL; /*09210068 */ + u32 PCIX_CLRFALL; /*0921006C */ + u32 PCIX_MSKLEV; /*09210070 */ + u32 PCIX_CLRLEV; /*09210074 */ + u32 PCIX_ABORT; /*09210078 */ + u32 PCIX_APPINIT; /*0921007C */ + u32 PCIX_FUNC0_USERBAR0; /*09210080 */ + u32 PCIX_FUNC0_USERBAR2; /*09210084 */ + u32 PCIX_FUNC0_USERBAR4; /*09210088 */ + u32 PCIX_FUNC0_USEREXP; /*0921008C */ + u32 PCIX_FUNC1_USERBAR0; /*09210090 */ + u32 PCIX_FUNC1_USERBAR2; /*09210094 */ + u32 PCIX_FUNC1_USERBAR4; /*09210098 */ + u32 PCIX_FUNC1_USEREXP; /*0921009C */ + u32 PCIX_FUNC2_USERBAR0; /*092100A0 */ + u32 PCIX_FUNC2_USERBAR2; /*092100A4 */ + u32 PCIX_FUNC2_USERBAR4; /*092100A8 */ + u32 PCIX_FUNC2_USEREXP; /*092100AC */ + u32 PCIX_FUNC3_USERBAR0; /*092100B0 */ + u32 PCIX_FUNC3_USERBAR2; /*092100B4 */ + u32 PCIX_FUNC3_USERBAR4; /*092100B8 */ + u32 PCIX_FUNC3_USEREXP; /*092100BC */ + u32 PCIX_T3TARG_BASE0; /*092100C0 */ + u32 PCIX_T3TARG_BASE1; /*092100C4 */ + u32 PCIX_T3TARG_BASE2; /*092100C8 */ + u32 PCIX_T3TARG_BASE3; /*092100CC */ + u32 PCIX_T3TARG_WIN0; /*092100D0 */ + u32 PCIX_T3TARG_WIN1; /*092100D4 */ + u32 PCIX_T3TARG_WIN2; /*092100D8 */ + u32 PCIX_T3TARG_WIN3; /*092100DC */ + u32 filler3[8]; /*092100E0 thru 092100FF */ + u32 PCIE_RC_CFG_MODE; /*09210100 */ + u32 PCIE_RC_CFG_SETUP1; /*09210104 */ + u32 PCIE_RC_CFG_SETUP2; /*09210108 */ + u32 PCIE_RC_CFG_WRITE_DATA; /*0921010C */ + u32 PCIE_RC_CFG_STAT; /*09210110 */ + u32 PCIE_RC_CFG_CPL_DATA; /*09210114 */ + u32 PCIE_RC_CFG_CPLID; /*09210118 */ + u32 filler4; /*0921011C */ + u32 PCIX_RISING_EVENT_LOW; /*09210120 */ + u32 PCIX_RISING_EVENT_HIGH; /*09210124 */ + u32 PCIX_FALLING_EVENT; /*09210128 */ + u32 PCIX_LEVEL_EVENT; /*0921012C */ + u32 PCIX_PHY_CONT_DATA1; /*09210130 */ + u32 PCIX_PHY_CONT_DATA2; /*09210134 */ + u32 PCIX_PHY_READ_BACK; /*09210138 */ + u32 PCIX_APPS_PM; /*0921013C */ + u32 PCIX_INT_EN; /*09210140 */ + u32 PCIX_MASKRISE_LOW2; /*09210144 */ + u32 PCIX_MASKRISE_HIGH2; /*09210148 */ + u32 PCIX_CLRRISE_LOW2; /*0921014C */ + u32 PCIX_CLRRISE_HIGH2; /*09210150 */ + u32 PCIX_MSKFALL2; /*09210154 */ + u32 PCIX_CLRFALL2; /*09210158 */ + u32 PCIX_MSKLEV2; /*0921015C */ + u32 PCIX_CLRLEV2; /*09210160 */ + u32 PCIX_RISING_EVENT_LOW2; /*09210164 */ + u32 PCIX_RISING_EVENT_HIGH2; /*09210168 */ + u32 PCIX_FALLING_EVENT2; /*0921016C */ + u32 PCIX_LEVEL_EVENT2; /*09210170 */ + u32 PCIX_CFG_PBUS_NUM; /*09210174 */ + u32 PCIX_CFG_PBUS_DEVNUM; /*09210178 */ + u32 PCIX_PMSTAT; /*0921017C */ + u32 PCIX_RADM; /*09210180 */ + u32 PCIX_MSI_EN1; /*09210184 */ + u32 PCIX_MSIADDR1_LOW; /*09210188 */ + u32 PCIX_MSIADDR1_HIGH; /*0921018C */ + u32 PCIX_MSIDATA1; /*09210190 */ + u32 PCIX_MSI_EN2; /*09210194 */ + u32 PCIX_MSIADDR2_LOW; /*09210198 */ + u32 PCIX_MSIADDR2_HIGH; /*0921019C */ + u32 PCIX_MSIDATA2; /*092101A0 */ + u32 PCIX_TESTBUS; /*092101A4 */ + u32 PCIX_MSIX_ADDR_LOW; /*092101A8 */ + u32 PCIX_MSIX_ADDR_HIGH; /*092101AC */ + u32 PCIX_MSIXDATA; /*092101B0 */ + u32 PCIX_MSIX_EN; /*092101B4 */ + u32 PCIX_AER_INT_MSGNUM; /*092101B8 */ + u32 PCIX_CAP_INT_MSTNUM; /*092101BC */ + u32 PCIX_EMLCONT; /*092101C0 */ + u32 filler5[143]; /*092101C4 thru 092103FF */ + u32 PCIX_CFG_PHY_CONT0; /*09210400 */ + u32 filler6[3]; /*09210404 thru 0921040F */ + u32 PCIX_CFG_BAR0_START_0; /*09210410 */ + u32 PCIX_CFG_BAR0_START_1; /*09210414 */ + u32 PCIX_CFG_BAR0_START_2; /*09210418 */ + u32 PCIX_CFG_BAR0_START_3; /*0921041C */ + u32 PCIX_CFG_BAR0_START_4; /*09210420 */ + u32 PCIX_CFG_BAR0_START_5; /*09210424 */ + u32 PCIX_CFG_BAR0_START_6; /*09210428 */ + u32 PCIX_CFG_BAR0_START_7; /*0921042C */ + u32 PCIX_CFG_BAR0_LIMIT_0; /*09210430 */ + u32 filler7; /*09210434 */ + u32 PCIX_CFG_BAR0_LIMIT_2; /*09210438 */ + u32 PCIX_CFG_BAR0_LIMIT_3; /*0921043C */ + u32 PCIX_CFG_BAR0_LIMIT_4; /*09210440 */ + u32 PCIX_CFG_BAR0_LIMIT_5; /*09210444 */ + u32 PCIX_CFG_BAR0_LIMIT_6; /*09210448 */ + u32 PCIX_CFG_BAR0_LIMIT_7; /*0921044C */ + u32 PCIX_CFG_BAR1_START_0; /*09210450 */ + u32 PCIX_CFG_BAR1_START_1; /*09210454 */ + u32 PCIX_CFG_BAR1_START_2; /*09210458 */ + u32 PCIX_CFG_BAR1_START_3; /*0921045C */ + u32 PCIX_CFG_BAR1_START_4; /*09210460 */ + u32 PCIX_CFG_BAR1_START_5; /*09210464 */ + u32 PCIX_CFG_BAR1_START_6; /*09210468 */ + u32 PCIX_CFG_BAR1_START_7; /*0921046C */ + u32 PCIX_CFG_BAR1_LIMIT_0; /*09210470 */ + u32 PCIX_CFG_BAR1_LIMIT_1; /*09210474 */ + u32 PCIX_CFG_BAR1_LIMIT_2; /*09210478 */ + u32 PCIX_CFG_BAR1_LIMIT_3; /*0921047C */ + u32 PCIX_CFG_BAR1_LIMIT_4; /*09210480 */ + u32 PCIX_CFG_BAR1_LIMIT_5; /*09210484 */ + u32 PCIX_CFG_BAR1_LIMIT_6; /*09210488 */ + u32 PCIX_CFG_BAR1_LIMIT_7; /*0921048C */ + u32 PCIX_CFG_EXP_ROM_START_0; /*09210490 */ + u32 PCIX_CFG_EXP_ROM_START_1; /*09210494 */ + u32 PCIX_CFG_EXP_ROM_START_2; /*09210498 */ + u32 PCIX_CFG_EXP_ROM_START_3; /*0921049C */ + u32 PCIX_CFG_EXP_ROM_LIMIT_0; /*092104A0 */ + u32 PCIX_CFG_EXP_ROM_LIMIT_1; /*092104A4 */ + u32 PCIX_CFG_EXP_ROM_LIMIT_2; /*092104A8 */ + u32 PCIX_CFG_EXP_ROM_LIMIT_3; /*092104AC */ + u32 PCIX_XLMH_STATE; /*092104B0 */ + u32 PCIX_RDLH_LINK; /*092104B4 */ + u32 PCIX_CFG_BUS_MSTR; /*092104B8 */ + u32 PCIX_CFG_MEM; /*092104BC */ + u32 PCIX_CFG_MSI; /*092104C0 */ + u32 PCIX_CFG_MAX; /*092104C4 */ + u32 filler8; /*092104C8 */ + u32 PCIX_PM_CURST; /*092104CC */ + u32 PCIX_RADM_MSGCTL; /*092104D0 */ + u32 PCIX_RADM_MSGPAY; /*092104D4 */ + u32 PCIX_RADM_PWR; /*092104D8 */ + u32 filler9[2]; /*092104DC thru 092104E0 */ + u32 PCIX_RADM_CORR; /*092104E4 */ + u32 PCIX_RTLH_UPD; /*092104E8 */ + u32 PCIX_RTLD_DATA; /*092104EC */ + u32 PCIX_CXPL_DEBUGLO; /*092104F0 */ + u32 PCIX_CXPL_DEBUGHI; /*092104F4 */ + u32 PCIX_RADM_CPL_0; /*092104F8 */ + u32 PCIX_RADM_CPL_1; /*092104FC */ + u32 PCIX_RADM_CPL_2; /*09210500 */ + u32 PCIX_RADM_CPL_3; /*09210504 */ + u32 PCIX_CFG_RCB; /*09210508 */ + u32 filler10[7872]; /*0921050C thru 09218000 */ + u32 PCIX_VEN_MSG_STAT1; /*0921800C */ + u32 PCIX_VEN_MSG_DATALO; /*09218010 */ + u32 PCIX_VEN_MSG_DATAHI; /*09218014 */ +}; + +/*PCIX_PHY_READ_BACK bits */ +#define kPCIX_PHY_READ_BACK_PllLock 0x01 +#define kPCIX_PHY_READ_BACK_Ready 0x02 + +/*PCIX_CTL1 bits */ +#define kPCIX_CTL1_PCIE_TLP_ENABLE 0x0002 +#define kPCIX_CTL1_PCIE_FUNC0 0x0040 +#define kPCIX_CTL1_PCIE_ROOT_COMPLEX 0x0010 +#define kPCIX_CTL1_PCIE_SEL_CLOCK 0x1000 +#define kPCIX_CTL1_PCIE_LTSSM 0x0400 +#define kPCIX_CTL1_PCI_ENAB_INTS 0x0800 + +/*PCIX_RDLH_LINK bits */ +#define kPCIX_RDLH_LINK_RdlhUp 0x01 + +/*PCIE_RC_CFG_SETUP1 */ +#define kPCIE_RC_CFG_SETUP1_CFG_ENAB_ALL_BYTES 0x78 +#define kPCIE_RC_CFG_SETUP1_CFG_READ 0x01 +#define kPCIE_RC_CFG_SETUP1_CFG_WRITE 0x03 +#define kPCIE_RC_CFG_SETUP1_TYPE0 0x00 +#define kPCIE_RC_CFG_SETUP1_TYPE1 0x01 + +/*Interrupt bits */ +#define kPCIX_IntLow_cfg_sys_err_rc3 0x80000000 +#define kPCIX_IntLow_cfg_sys_err_rc2 0x40000000 +#define kPCIX_IntLow_cfg_sys_err_rc1 0x20000000 +#define kPCIX_IntLow_cfg_sys_err_rc0 0x10000000 +#define kPCIX_IntLow_radm_cpl_hv 0x08000000 +#define kPCIX_IntLow_radm_cpl_dllp_abort 0x04000000 +#define kPCIX_IntLow_radm_cpl_tlp_abort 0x02000000 +#define kPCIX_IntLow_radm_cpl_ecrc_err 0x01000000 +#define kPCIX_IntLow_radm_cpl_eot 0x00800000 +#define kPCIX_IntLow_radm_cpl_last 0x00400000 +#define kPCIX_IntLow_radm_cpl_timeout 0x00200000 +#define kPCIX_IntLow_radm_trgt1_hv 0x00100000 +#define kPCIX_IntLow_radm_trgt1_eot 0x00080000 +#define kPCIX_IntLow_training_rst_n 0x00040000 +#define kPCIX_IntLow_rtlh_rfc_upd 0x00020000 +#define kPCIX_IntLow_pm_xtlh_block_tlp 0x00010000 +#define kPCIX_IntLow_cfg_aer_rc_err_int3 0x00008000 +#define kPCIX_IntLow_cfg_aer_rc_err_int2 0x00004000 +#define kPCIX_IntLow_cfg_aer_rc_err_int1 0x00002000 +#define kPCIX_IntLow_cfg_aer_rc_err_int0 0x00001000 +#define kPCIX_IntLow_rdlh_link_up 0x00000800 +#define kPCIX_IntLow_radm_vendor_msg 0x00000400 +#define kPCIX_IntLow_radm_msg_unlock 0x00000200 +#define kPCIX_IntLow_radm_inta_asserted 0x00000100 +#define kPCIX_IntLow_radm_intb_asserted 0x00000080 +#define kPCIX_IntLow_radm_intc_asserted 0x00000040 +#define kPCIX_IntLow_radm_intd_asserted 0x00000020 +#define kPCIX_IntLow_radm_correctable_err 0x00000010 +#define kPCIX_IntLow_radm_nonfatal_err 0x00000008 +#define kPCIX_IntLow_radm_fatal_err 0x00000004 +#define kPCIX_IntLow_radm_att_button_pressed 0x00000002 +#define kPCIX_IntLow_radm_pm_pme 0x00000001 + +#define kPCIX_IntHigh_radm_pm_to_ack 0x00020000 +#define kPCIX_IntHigh_xmlh_link_up 0x00010000 +#define kPCIX_IntHigh_wake_n 0x00008000 +#define kPCIX_IntHigh_cfg_bus_master_en3 0x00004000 +#define kPCIX_IntHigh_cfg_bus_master_en2 0x00002000 +#define kPCIX_IntHigh_cfg_bus_master_en1 0x00001000 +#define kPCIX_IntHigh_cfg_bus_master_en0 0x00000800 +#define kPCIX_IntHigh_radm_inta_deasserted 0x00000400 +#define kPCIX_IntHigh_radm_intb_deasserted 0x00000200 +#define kPCIX_IntHigh_radm_intc_deasserted 0x00000100 +#define kPCIX_IntHigh_radm_intd_deasserted 0x00000080 +#define kPCIX_IntHigh_radm_att_ind_on 0x00000040 +#define kPCIX_IntHigh_radm_att_ind_blink 0x00000020 +#define kPCIX_IntHigh_radm_att_ind_off 0x00000010 +#define kPCIX_IntHigh_radm_pwr_ind_on 0x00000008 +#define kPCIX_IntHigh_radm_pwr_ind_blink 0x00000004 +#define kPCIX_IntHigh_radm_pwr_ind_off 0x00000002 +#define kPCIX_IntHigh_radm_cpl_error_int 0x00000001 + +#endif /* _PCIE_REGS_H_ */ + diff --git a/arch/mips/powertv/pci/powertv-pci.h b/arch/mips/powertv/pci/powertv-pci.h new file mode 100644 index 0000000..98c087e --- /dev/null +++ b/arch/mips/powertv/pci/powertv-pci.h @@ -0,0 +1,12 @@ +/* + * Local definitions for the powertv PCI code + */ + +#ifndef _POWERTV_PCI_H_ +#define _POWERTV_PCI_H_ +extern int asic_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin); +extern int asic_pcie_init(void); +extern int asic_pcie_init(void); + +extern int LogLevel; +#endif diff --git a/arch/mips/powertv/powertv-clock.h b/arch/mips/powertv/powertv-clock.h new file mode 100644 index 0000000..6f8c17b --- /dev/null +++ b/arch/mips/powertv/powertv-clock.h @@ -0,0 +1,10 @@ +/* + * Definitions for clocks + */ + +#ifndef _POWERTV_CLOCK_H +#define _POWERTV_CLOCK_H +extern int powertv_clockevent_init(void); +extern void powertv_clocksource_init(void); +extern unsigned int mips_get_pll_freq(void); +#endif diff --git a/arch/mips/powertv/powertv_setup.c b/arch/mips/powertv/powertv_setup.c new file mode 100644 index 0000000..f19f36f --- /dev/null +++ b/arch/mips/powertv/powertv_setup.c @@ -0,0 +1,351 @@ +/* + * Carsten Langgaard, carstenl@mips.com + * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved. + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "reset.h" + +#define VAL(n) STR(n) + +/* + * Macros for loading addresses and storing registers: + * PTR_LA Load the address into a register + * LONG_S Store the full width of the given register. + * LONG_L Load the full width of the given register + * PTR_ADDIU Add a constant value to a register used as a pointer + * REG_SIZE Number of 8-bit bytes in a full width register + */ +#ifdef CONFIG_64BIT +#warning TODO: 64-bit code needs to be verified +#define PTR_LA "dla " +#define LONG_S "sd " +#define LONG_L "ld " +#define PTR_ADDIU "daddiu " +#define REG_SIZE "8" /* In bytes */ +#endif + +#ifdef CONFIG_32BIT +#define PTR_LA "la " +#define LONG_S "sw " +#define LONG_L "lw " +#define PTR_ADDIU "addiu " +#define REG_SIZE "4" /* In bytes */ +#endif + +static struct pt_regs die_regs; +static bool have_die_regs; + +static void register_panic_notifier(void); +static int panic_handler(struct notifier_block *notifier_block, + unsigned long event, void *cause_string); + +const char *get_system_type(void) +{ + return "PowerTV"; +} + +void __init plat_mem_setup(void) +{ + panic_on_oops = 1; + register_panic_notifier(); + + mips_pcibios_init(); + mips_reboot_setup(); +} + +/* + * Install a panic notifier for platform-specific diagnostics + */ +static void register_panic_notifier() +{ + static struct notifier_block panic_notifier = { + .notifier_call = panic_handler, + .next = NULL, + .priority = INT_MAX + }; + atomic_notifier_chain_register(&panic_notifier_list, &panic_notifier); +} + +static int panic_handler (struct notifier_block *notifier_block, + unsigned long event, void *cause_string) +{ + struct pt_regs my_regs; + + /* Save all of the registers */ + { + unsigned long at, v0, v1; /* Must be on the stack */ + + /* Start by saving $at and v0 on the stack. We use $at + * ourselves, but it looks like the compiler may use v0 or v1 + * to load the address of the pt_regs structure. We'll come + * back later to store the registers in the pt_regs + * structure. */ + __asm__ __volatile__ ( + ".set noat\n" + LONG_S "$at, %[at]\n" + LONG_S "$2, %[v0]\n" + LONG_S "$3, %[v1]\n" + : + [at] "=m" (at), + [v0] "=m" (v0), + [v1] "=m" (v1) + : + : "at" + ); + + __asm__ __volatile__ ( + ".set noat\n" + "move $at, %[pt_regs]\n" + + /* Argument registers */ + LONG_S "$4, " VAL(PT_R4) "($at)\n" + LONG_S "$5, " VAL(PT_R5) "($at)\n" + LONG_S "$6, " VAL(PT_R6) "($at)\n" + LONG_S "$7, " VAL(PT_R7) "($at)\n" + + /* Temporary regs */ + LONG_S "$8, " VAL(PT_R8) "($at)\n" + LONG_S "$9, " VAL(PT_R9) "($at)\n" + LONG_S "$10, " VAL(PT_R10) "($at)\n" + LONG_S "$11, " VAL(PT_R11) "($at)\n" + LONG_S "$12, " VAL(PT_R12) "($at)\n" + LONG_S "$13, " VAL(PT_R13) "($at)\n" + LONG_S "$14, " VAL(PT_R14) "($at)\n" + LONG_S "$15, " VAL(PT_R15) "($at)\n" + + /* "Saved" registers */ + LONG_S "$16, " VAL(PT_R16) "($at)\n" + LONG_S "$17, " VAL(PT_R17) "($at)\n" + LONG_S "$18, " VAL(PT_R18) "($at)\n" + LONG_S "$19, " VAL(PT_R19) "($at)\n" + LONG_S "$20, " VAL(PT_R20) "($at)\n" + LONG_S "$21, " VAL(PT_R21) "($at)\n" + LONG_S "$22, " VAL(PT_R22) "($at)\n" + LONG_S "$23, " VAL(PT_R23) "($at)\n" + + /* Add'l temp regs */ + LONG_S "$24, " VAL(PT_R24) "($at)\n" + LONG_S "$25, " VAL(PT_R25) "($at)\n" + + /* Kernel temp regs */ + LONG_S "$26, " VAL(PT_R26) "($at)\n" + LONG_S "$27, " VAL(PT_R27) "($at)\n" + + /* Global pointer, stack pointer, frame pointer and + * return address */ + LONG_S "$gp, " VAL(PT_R28) "($at)\n" + LONG_S "$sp, " VAL(PT_R29) "($at)\n" + LONG_S "$fp, " VAL(PT_R30) "($at)\n" + LONG_S "$ra, " VAL(PT_R31) "($at)\n" + + /* Now we can get the $at and v0 registers back and + * store them */ + LONG_L "$8, %[at]\n" + LONG_S "$8, " VAL(PT_R1) "($at)\n" + LONG_L "$8, %[v0]\n" + LONG_S "$8, " VAL(PT_R2) "($at)\n" + LONG_L "$8, %[v1]\n" + LONG_S "$8, " VAL(PT_R3) "($at)\n" + : + : + [at] "m" (at), + [v0] "m" (v0), + [v1] "m" (v1), + [pt_regs] "r" (&my_regs) + : "at", "t0" + ); + + /* Set the current EPC value to be the current location in this + * function */ + __asm__ __volatile__ ( + ".set noat\n" + "1:\n" + PTR_LA "$at, 1b\n" + LONG_S "$at, %[cp0_epc]\n" + : + [cp0_epc] "=m" (my_regs.cp0_epc) + : + : "at" + ); + + my_regs.cp0_cause = read_c0_cause(); + my_regs.cp0_status = read_c0_status(); + } + +#ifdef CONFIG_DIAGNOSTICS + failure_report((char *) cause_string, + have_die_regs ? &die_regs : &my_regs); + have_die_regs = false; +#else + pr_crit("I'm feeling a bit sleepy. hmmmmm... perhaps a nap would... " + "zzzz... \n"); +#endif + + return NOTIFY_DONE; +} + +/** + * Platform-specific handling of oops + * @str: Pointer to the oops string + * @regs: Pointer to the oops registers + * All we do here is to save the registers for subsequent printing through + * the panic notifier. + */ +void platform_die(const char *str, const struct pt_regs *regs) +{ + /* If we already have saved registers, don't overwrite them as they + * they apply to the initial fault */ + + if (!have_die_regs) { + have_die_regs = true; + die_regs = *regs; + } +} + +/* Information about the RF MAC address, if one was supplied on the + * command line. */ +static bool have_rfmac; +static u8 rfmac[ETH_ALEN]; + +static int rfmac_param(char *p) +{ + u8 *q; + bool is_high_nibble; + int c; + + /* Skip a leading "0x", if present */ + if (*p == '0' && *(p+1) == 'x') + p += 2; + + q = rfmac; + is_high_nibble = true; + + for (c = (unsigned char) *p++; + isxdigit(c) && q - rfmac < ETH_ALEN; + c = (unsigned char) *p++) { + int nibble; + + nibble = (isdigit(c) ? (c - '0') : + (isupper(c) ? c - 'A' + 10 : c - 'a' + 10)); + + if (is_high_nibble) + *q = nibble << 4; + else + *q++ |= nibble; + + is_high_nibble = !is_high_nibble; + } + + /* If we parsed all the way to the end of the parameter value and + * parsed all ETH_ALEN bytes, we have a usable RF MAC address */ + have_rfmac = (c == '\0' && q - rfmac == ETH_ALEN); + + return 0; +} + +early_param("rfmac", rfmac_param); + +/* + * Generate an Ethernet MAC address that has a good chance of being unique. + * @addr: Pointer to six-byte array containing the Ethernet address + * Generates an Ethernet MAC address that is highly likely to be unique for + * this particular system on a network with other systems of the same type. + * + * The problem we are solving is that, when random_ether_addr() is used to + * generate MAC addresses at startup, there isn't much entropy for the random + * number generator to use and the addresses it produces are fairly likely to + * be the same as those of other identical systems on the same local network. + * This is true even for relatively small numbers of systems (for the reason + * why, see the Wikipedia entry for "Birthday problem" at: + * http://en.wikipedia.org/wiki/Birthday_problem + * + * The good news is that we already have a MAC address known to be unique, the + * RF MAC address. The bad news is that this address is already in use on the + * RF interface. Worse, the obvious trick, taking the RF MAC address and + * turning on the locally managed bit, has already been used for other devices. + * Still, this does give us something to work with. + * + * The approach we take is: + * 1. If we can't get the RF MAC Address, just call random_ether_addr. + * 2. Use the 24-bit NIC-specific bits of the RF MAC address as the last 24 + * bits of the new address. This is very likely to be unique, except for + * the current box. + * 3. To avoid using addresses already on the current box, we set the top + * six bits of the address with a value different from any currently + * registered Scientific Atlanta organizationally unique identifyer + * (OUI). This avoids duplication with any addresses on the system that + * were generated from valid Scientific Atlanta-registered address by + * simply flipping the locally managed bit. + * 4. We aren't generating a multicast address, so we leave the multicast + * bit off. Since we aren't using a registered address, we have to set + * the locally managed bit. + * 5. We then randomly generate the remaining 16-bits. This does two + * things: + * a. It allows us to call this function for more than one device + * in this system + * b. It ensures that things will probably still work even if + * some device on the device network has a locally managed + * address that matches the top six bits from step 2. + */ +void platform_random_ether_addr(u8 addr[ETH_ALEN]) +{ +#define NUM_RANDOM_BYTES 2 +#define NON_SCIATL_OUI_BITS 0xc0u +#define MAC_ADDR_LOCALLY_MANAGED (1 << 1) + + if (!have_rfmac) { + pr_warning("rfmac not available on command line; " + "generating random MAC address\n"); + random_ether_addr(addr); + } + + else { + int i; + + /* Set the first byte to something that won't match a Scientific + * Atlanta OUI, is locally managed, and isn't a multicast + * address */ + addr[0] = NON_SCIATL_OUI_BITS | MAC_ADDR_LOCALLY_MANAGED; + + /* Get some bytes of random address information */ + get_random_bytes(&addr[1], NUM_RANDOM_BYTES); + + /* Copy over the NIC-specific bits of the RF MAC address */ + for (i = 1 + NUM_RANDOM_BYTES; i < ETH_ALEN; i++) + addr[i] = rfmac[i]; + } +#undef NON_RANDOM_BYTES +#undef NON_SCIATL_OUI_BITS +#undef MAC_ADDR_LOCALLY_MANAGED +} diff --git a/arch/mips/powertv/reset.c b/arch/mips/powertv/reset.c new file mode 100644 index 0000000..9756090 --- /dev/null +++ b/arch/mips/powertv/reset.c @@ -0,0 +1,69 @@ +/* + * Carsten Langgaard, carstenl@mips.com + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. + * + * ######################################################################## + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * ######################################################################## + * + */ +#include + +#include +#include /* Not included by linux/reboot.h */ + +#ifdef CONFIG_BOOTLOADER_DRIVER +#include +#endif + +#include +#include "reset.h" + +static void mips_machine_restart(char *command); +static void mips_machine_halt(void); + +static void mips_machine_restart(char *command) +{ +#ifdef CONFIG_BOOTLOADER_DRIVER + /* + * Call the bootloader's reset function to ensure + * that persistent data is flushed before hard reset + */ + kbldr_SetCauseAndReset(); +#else + writel(0x1, asic_reg_addr(Watchdog)); +#endif +} + +static void mips_machine_halt(void) +{ +#ifdef CONFIG_BOOTLOADER_DRIVER + /* + * Call the bootloader's reset function to ensure + * that persistent data is flushed before hard reset + */ + kbldr_SetCauseAndReset(); +#else + writel(0x1, asic_reg_addr(Watchdog)); +#endif +} + +void mips_reboot_setup(void) +{ + _machine_restart = mips_machine_restart; + _machine_halt = mips_machine_halt; + pm_power_off = mips_machine_halt; +} diff --git a/arch/mips/powertv/reset.h b/arch/mips/powertv/reset.h new file mode 100644 index 0000000..79211ce --- /dev/null +++ b/arch/mips/powertv/reset.h @@ -0,0 +1,8 @@ +/* + * Definitions from powertv reset.c file + */ + +#ifndef _POWERTV_RESET_H +#define _POWERTV_RESET_H +extern void mips_reboot_setup(void); +#endif diff --git a/arch/mips/powertv/time.c b/arch/mips/powertv/time.c new file mode 100644 index 0000000..b5806e5 --- /dev/null +++ b/arch/mips/powertv/time.c @@ -0,0 +1,47 @@ +/* + * Carsten Langgaard, carstenl@mips.com + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. + * + * This program is free software; you can distribute it and/or modify it + * under the terms of the GNU General Public License (Version 2) as + * published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License + * for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. + * + * Setting up the clock on the MIPS boards. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "powertv-clock.h" + +void __init plat_time_init(void) +{ + powertv_clocksource_init(); + powertv_clockevent_init(); +} From dvomlehn@cisco.com Mon May 4 23:57:29 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 04 May 2009 23:57:35 +0100 (BST) Received: from sj-iport-1.cisco.com ([171.71.176.70]:2633 "EHLO sj-iport-1.cisco.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20023529AbZEDW53 (ORCPT ); Mon, 4 May 2009 23:57:29 +0100 X-IronPort-AV: E=Sophos;i="4.40,293,1238976000"; d="scan'208";a="180713250" Received: from sj-dkim-1.cisco.com ([171.71.179.21]) by sj-iport-1.cisco.com with ESMTP; 04 May 2009 22:57:19 +0000 Received: from sj-core-1.cisco.com (sj-core-1.cisco.com [171.71.177.237]) by sj-dkim-1.cisco.com (8.12.11/8.12.11) with ESMTP id n44MvImh009583; Mon, 4 May 2009 15:57:18 -0700 Received: from cuplxvomd02.corp.sa.net ([64.101.20.155]) by sj-core-1.cisco.com (8.13.8/8.13.8) with ESMTP id n44MvIFv000039; Mon, 4 May 2009 22:57:18 GMT Date: Mon, 4 May 2009 15:57:19 -0700 From: David VomLehn To: linux-mips@linux-mips.org Cc: ralf@linux-mips.org Subject: [PATCH 2/3] mips:powertv: Make kernel command line size configurable (resend) Message-ID: <20090504225719.GA22417@cuplxvomd02.corp.sa.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline User-Agent: Mutt/1.5.18 (2008-05-17) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; l=1381; t=1241477839; x=1242341839; c=relaxed/simple; s=sjdkim1004; h=Content-Type:From:Subject:Content-Transfer-Encoding:MIME-Version; d=cisco.com; i=dvomlehn@cisco.com; z=From:=20David=20VomLehn=20 |Subject:=20[PATCH=202/3]=20mips=3Apowertv=3A=20Make=20kern el=20command=20line=20size=0A=09configurable=20(resend) |Sender:=20; bh=QChCafKFKQZR0MXfTBpj7rhqJBTpk+ar6Cou0Tf900A=; b=JE3748NyVpfuSNTDJOKAq7oHAEWGsJ7cbkgfNxaqEPzE5Dc2SuP28hrPrj ucAWDFKrP9zuz0ETXKHACsTv90e4TgLeCf03bEQpPf2lMtZvB0L+25C0QrFB FBgwPhv88YpSK5AibtegJ1rc1W3qVCXr22IxQ7k3zKMRVZlXjmLWA=; Authentication-Results: sj-dkim-1; header.From=dvomlehn@cisco.com; dkim=pass ( sig from cisco.com/sjdkim1004 verified; ); Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22620 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dvomlehn@cisco.com Precedence: bulk X-list: linux-mips Content-Length: 1339 Lines: 42 Most platforms can get by perfectly well with the default command line size, but some platforms need more. This patch allows the command line size to be configured for those platforms that need it. The default remains 256 characters. Signed-off-by: David VomLehn --- arch/mips/Kconfig | 7 +++++++ arch/mips/include/asm/setup.h | 2 +- 2 files changed, 8 insertions(+), 1 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 998e5db..99f7b6d 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -780,6 +780,13 @@ config EARLY_PRINTK config SYS_HAS_EARLY_PRINTK bool +config COMMAND_LINE_SIZE + int "Maximum size of command line passed to kernel from bootloader" + default 256 + help + Most systems work well with the default value, but some bootloaders pass more + information on the command line than others. A smaller value is good here. + config HOTPLUG_CPU bool default n diff --git a/arch/mips/include/asm/setup.h b/arch/mips/include/asm/setup.h index e600ced..132e397 100644 --- a/arch/mips/include/asm/setup.h +++ b/arch/mips/include/asm/setup.h @@ -1,7 +1,7 @@ #ifndef _MIPS_SETUP_H #define _MIPS_SETUP_H -#define COMMAND_LINE_SIZE 256 +#define COMMAND_LINE_SIZE CONFIG_COMMAND_LINE_SIZE #ifdef __KERNEL__ extern void setup_early_printk(void); From dvomlehn@cisco.com Mon May 4 23:58:41 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 04 May 2009 23:58:47 +0100 (BST) Received: from sj-iport-6.cisco.com ([171.71.176.117]:18805 "EHLO sj-iport-6.cisco.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20023554AbZEDW6l (ORCPT ); Mon, 4 May 2009 23:58:41 +0100 X-IronPort-AV: E=Sophos;i="4.40,293,1238976000"; d="scan'208";a="298211346" Received: from sj-dkim-3.cisco.com ([171.71.179.195]) by sj-iport-6.cisco.com with ESMTP; 04 May 2009 22:58:21 +0000 Received: from sj-core-1.cisco.com (sj-core-1.cisco.com [171.71.177.237]) by sj-dkim-3.cisco.com (8.12.11/8.12.11) with ESMTP id n44MwLMU022986; Mon, 4 May 2009 15:58:21 -0700 Received: from cuplxvomd02.corp.sa.net ([64.101.20.155]) by sj-core-1.cisco.com (8.13.8/8.13.8) with ESMTP id n44MwL6Q000732; Mon, 4 May 2009 22:58:21 GMT Date: Mon, 4 May 2009 15:58:21 -0700 From: David VomLehn To: linux-mips@linux-mips.org Cc: ralf@linux-mips.org Subject: [PATCH 3/3] mips:powertv: Integrate Cisco Powertv platform into MIPS architecture (resend) Message-ID: <20090504225821.GA22833@cuplxvomd02.corp.sa.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline User-Agent: Mutt/1.5.18 (2008-05-17) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; l=43872; t=1241477901; x=1242341901; c=relaxed/simple; s=sjdkim3002; h=Content-Type:From:Subject:Content-Transfer-Encoding:MIME-Version; d=cisco.com; i=dvomlehn@cisco.com; z=From:=20David=20VomLehn=20 |Subject:=20[PATCH=203/3]=20mips=3Apowertv=3A=20Integrate=2 0Cisco=20Powertv=20platform=20into=0A=09MIPS=20architecture= 20(resend) |Sender:=20; bh=P4DHOLUSb/jPGk4mRLEJabEMNhNC856TmUN+pC/vCFI=; b=U+A+YJdVQ6dPTM+LusGg4v+eTL6dSDbjtJQ5tADB2OFWNJDP0jzkL5jroB Brhneg0nZ+mHyhZ+zE6BKcAjMomiQb6+oN8GV2pnNZSSn7NskX+pTks3isr+ C6/HqiZ9ny; Authentication-Results: sj-dkim-3; header.From=dvomlehn@cisco.com; dkim=pass ( sig from cisco.com/sjdkim3002 verified; ); Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22621 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dvomlehn@cisco.com Precedence: bulk X-list: linux-mips Content-Length: 42291 Lines: 1581 Adds the Cisco PowerTV platform to the configuration and Make files so that we can build a kernel for it. Signed-off-by: David VomLehn --- arch/mips/Kconfig | 30 + arch/mips/Makefile | 8 + arch/mips/configs/powertv_defconfig | 1484 +++++++++++++++++++++++++++++++++++ 3 files changed, 1522 insertions(+), 0 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 99f7b6d..b23ec4c 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -311,6 +311,23 @@ config PMC_YOSEMITE Yosemite is an evaluation board for the RM9000x2 processor manufactured by PMC-Sierra. +config POWERTV + bool "Support for Cisco PowerTV Platform" + select BOOT_ELF32 + select CEVT_POWERTV + select CSRC_POWERTV + select DMA_NONCOHERENT + select HW_HAS_PCI + select SYS_HAS_CPU_MIPS32_R2 + select SYS_SUPPORTS_32BIT_KERNEL + select SYS_SUPPORTS_BIG_ENDIAN + select CPU_MIPSR2_IRQ_VI + select CPU_MIPSR2_IRQ_EI + select USB_OHCI_LITTLE_ENDIAN + select SYS_SUPPORTS_HIGHMEM + help + This enables support for the Cisco PowerTV Platform. + config SGI_IP22 bool "SGI IP22 (Indy/Indigo2)" select ARC @@ -637,6 +654,7 @@ source "arch/mips/basler/excite/Kconfig" source "arch/mips/jazz/Kconfig" source "arch/mips/lasat/Kconfig" source "arch/mips/pmc-sierra/Kconfig" +source "arch/mips/powertv/Kconfig" source "arch/mips/sgi-ip27/Kconfig" source "arch/mips/sibyte/Kconfig" source "arch/mips/txx9/Kconfig" @@ -723,6 +741,12 @@ config CEVT_R4K select CEVT_R4K_LIB bool +# +# The flag for POWERTV clock source. +# +config CEVT_POWERTV + bool + config CEVT_SB1250 bool @@ -742,6 +766,12 @@ config CSRC_R4K select CSRC_R4K_LIB bool +# +# The flag for POWERTV clock event. +# +config CSRC_POWERTV + bool + config CSRC_SB1250 bool diff --git a/arch/mips/Makefile b/arch/mips/Makefile index 8d544c7..6a5e31b 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -426,6 +426,14 @@ core-$(CONFIG_NEC_MARKEINS) += arch/mips/emma/markeins/ load-$(CONFIG_NEC_MARKEINS) += 0xffffffff88100000 # +# Cisco PowerTV Platform +# +core-$(CONFIG_POWERTV) += arch/mips/powertv/ +#cflags-$(CONFIG_POWERTV) += -I$(srctree)/arch/mips/include/asm/mach-mips +cflags-$(CONFIG_POWERTV) += -I$(srctree)/arch/mips/include/asm/mach-powertv +load-$(CONFIG_POWERTV) += 0xffffffff90800000 + +# # SGI IP22 (Indy/Indigo2) # # Set the load address to >= 0xffffffff88069000 if you want to leave space for diff --git a/arch/mips/configs/powertv_defconfig b/arch/mips/configs/powertv_defconfig new file mode 100644 index 0000000..7311e63 --- /dev/null +++ b/arch/mips/configs/powertv_defconfig @@ -0,0 +1,1484 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.30-rc2 +# Thu Apr 16 11:29:44 2009 +# +CONFIG_MIPS=y + +# +# Machine selection +# +# CONFIG_MACH_ALCHEMY is not set +# CONFIG_BASLER_EXCITE is not set +# CONFIG_BCM47XX is not set +# CONFIG_MIPS_COBALT is not set +# CONFIG_MACH_DECSTATION is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_LASAT is not set +# CONFIG_LEMOTE_FULONG is not set +# CONFIG_MIPS_MALTA is not set +# CONFIG_MIPS_SIM is not set +# CONFIG_NEC_MARKEINS is not set +# CONFIG_MACH_VR41XX is not set +# CONFIG_NXP_STB220 is not set +# CONFIG_NXP_STB225 is not set +# CONFIG_PNX8550_JBS is not set +# CONFIG_PNX8550_STB810 is not set +# CONFIG_PMC_MSP is not set +# CONFIG_PMC_YOSEMITE is not set +CONFIG_POWERTV=y +# CONFIG_SGI_IP22 is not set +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP28 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_CRHONE is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_BIGSUR is not set +# CONFIG_SNI_RM is not set +# CONFIG_MACH_TX39XX is not set +# CONFIG_MACH_TX49XX is not set +# CONFIG_MIKROTIK_RB532 is not set +# CONFIG_WR_PPMC is not set +# CONFIG_CAVIUM_OCTEON_SIMULATOR is not set +# CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD is not set +# CONFIG_MIN_RUNTIME_RESOURCES is not set +# CONFIG_BOOTLOADER_DRIVER is not set +CONFIG_BOOTLOADER_FAMILY="R2" +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_ARCH_SUPPORTS_OPROFILE=y +CONFIG_GENERIC_FIND_NEXT_BIT=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CMOS_UPDATE=y +CONFIG_SCHED_OMIT_FRAME_POINTER=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +CONFIG_CEVT_POWERTV=y +CONFIG_CSRC_POWERTV=y +CONFIG_DMA_NONCOHERENT=y +CONFIG_DMA_NEED_PCI_MAP_STATE=y +CONFIG_COMMAND_LINE_SIZE=4096 +# CONFIG_HOTPLUG_CPU is not set +# CONFIG_NO_IOPORT is not set +CONFIG_CPU_BIG_ENDIAN=y +# CONFIG_CPU_LITTLE_ENDIAN is not set +CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y +CONFIG_BOOT_ELF32=y +CONFIG_MIPS_L1_CACHE_SHIFT=5 + +# +# CPU selection +# +# CONFIG_CPU_LOONGSON2 is not set +# CONFIG_CPU_MIPS32_R1 is not set +CONFIG_CPU_MIPS32_R2=y +# CONFIG_CPU_MIPS64_R1 is not set +# CONFIG_CPU_MIPS64_R2 is not set +# CONFIG_CPU_R3000 is not set +# CONFIG_CPU_TX39XX is not set +# CONFIG_CPU_VR41XX is not set +# CONFIG_CPU_R4300 is not set +# CONFIG_CPU_R4X00 is not set +# CONFIG_CPU_TX49XX is not set +# CONFIG_CPU_R5000 is not set +# CONFIG_CPU_R5432 is not set +# CONFIG_CPU_R5500 is not set +# CONFIG_CPU_R6000 is not set +# CONFIG_CPU_NEVADA is not set +# CONFIG_CPU_R8000 is not set +# CONFIG_CPU_R10000 is not set +# CONFIG_CPU_RM7000 is not set +# CONFIG_CPU_RM9000 is not set +# CONFIG_CPU_SB1 is not set +# CONFIG_CPU_CAVIUM_OCTEON is not set +CONFIG_SYS_HAS_CPU_MIPS32_R2=y +CONFIG_CPU_MIPS32=y +CONFIG_CPU_MIPSR2=y +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_HARDWARE_WATCHPOINTS=y + +# +# Kernel type +# +CONFIG_32BIT=y +# CONFIG_64BIT is not set +CONFIG_PAGE_SIZE_4KB=y +# CONFIG_PAGE_SIZE_8KB is not set +# CONFIG_PAGE_SIZE_16KB is not set +# CONFIG_PAGE_SIZE_64KB is not set +CONFIG_CPU_HAS_PREFETCH=y +CONFIG_MIPS_MT_DISABLED=y +# CONFIG_MIPS_MT_SMP is not set +# CONFIG_MIPS_MT_SMTC is not set +CONFIG_CPU_HAS_LLSC=y +CONFIG_CPU_MIPSR2_IRQ_VI=y +CONFIG_CPU_MIPSR2_IRQ_EI=y +CONFIG_CPU_HAS_SYNC=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_IRQ_PROBE=y +# CONFIG_HIGHMEM is not set +CONFIG_CPU_SUPPORTS_HIGHMEM=y +CONFIG_SYS_SUPPORTS_HIGHMEM=y +CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_ARCH_POPULATES_NODE_MAP=y +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=0 +CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y +CONFIG_HAVE_MLOCK=y +CONFIG_HAVE_MLOCKED_PAGE_BIT=y +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +# CONFIG_HZ_48 is not set +# CONFIG_HZ_100 is not set +# CONFIG_HZ_128 is not set +# CONFIG_HZ_250 is not set +# CONFIG_HZ_256 is not set +CONFIG_HZ_1000=y +# CONFIG_HZ_1024 is not set +CONFIG_SYS_SUPPORTS_ARBIT_HZ=y +CONFIG_HZ=1000 +# CONFIG_PREEMPT_NONE is not set +# CONFIG_PREEMPT_VOLUNTARY is not set +CONFIG_PREEMPT=y +# CONFIG_KEXEC is not set +# CONFIG_SECCOMP is not set +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_LOCK_KERNEL=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +# CONFIG_SWAP is not set +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_AUDIT is not set + +# +# RCU Subsystem +# +CONFIG_CLASSIC_RCU=y +# CONFIG_TREE_RCU is not set +# CONFIG_PREEMPT_RCU is not set +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_PREEMPT_RCU_TRACE is not set +# CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=16 +CONFIG_GROUP_SCHED=y +CONFIG_FAIR_GROUP_SCHED=y +# CONFIG_RT_GROUP_SCHED is not set +CONFIG_USER_SCHED=y +# CONFIG_CGROUP_SCHED is not set +# CONFIG_CGROUPS is not set +# CONFIG_SYSFS_DEPRECATED_V2 is not set +CONFIG_RELAY=y +# CONFIG_NAMESPACES is not set +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +# CONFIG_RD_GZIP is not set +# CONFIG_RD_BZIP2 is not set +# CONFIG_RD_LZMA is not set +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_SYSCTL=y +CONFIG_ANON_INODES=y +CONFIG_EMBEDDED=y +# CONFIG_SYSCTL_SYSCALL is not set +CONFIG_KALLSYMS=y +CONFIG_KALLSYMS_ALL=y +# CONFIG_KALLSYMS_EXTRA_PASS is not set +# CONFIG_STRIP_ASM_SYMS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_PRINTK_CONSOLE_WAIT=500 +CONFIG_BUG=y +CONFIG_ELF_CORE=y +# CONFIG_PCSPKR_PLATFORM is not set +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +# CONFIG_EPOLL is not set +# CONFIG_SIGNALFD is not set +CONFIG_TIMERFD=y +# CONFIG_EVENTFD is not set +CONFIG_SHMEM=y +CONFIG_AIO=y +# CONFIG_VM_EVENT_COUNTERS is not set +CONFIG_PCI_QUIRKS=y +# CONFIG_SLUB_DEBUG is not set +CONFIG_COMPAT_BRK=y +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +# CONFIG_MARKERS is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_SLOW_WORK is not set +# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +CONFIG_MODVERSIONS=y +CONFIG_MODULE_SRCVERSION_ALL=y +CONFIG_BLOCK=y +# CONFIG_LBD is not set +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +# CONFIG_IOSCHED_AS is not set +# CONFIG_IOSCHED_DEADLINE is not set +# CONFIG_IOSCHED_CFQ is not set +# CONFIG_DEFAULT_AS is not set +# CONFIG_DEFAULT_DEADLINE is not set +# CONFIG_DEFAULT_CFQ is not set +CONFIG_DEFAULT_NOOP=y +CONFIG_DEFAULT_IOSCHED="noop" +# CONFIG_PROBE_INITRD_HEADER is not set +# CONFIG_FREEZER is not set + +# +# Bus options (PCI, PCMCIA, EISA, ISA, TC) +# +CONFIG_HW_HAS_PCI=y +CONFIG_PCI=y +CONFIG_PCI_DOMAINS=y +# CONFIG_ARCH_SUPPORTS_MSI is not set +# CONFIG_PCI_LEGACY is not set +# CONFIG_PCI_DEBUG is not set +# CONFIG_PCI_STUB is not set +# CONFIG_PCI_IOV is not set +CONFIG_MMU=y +# CONFIG_PCCARD is not set +# CONFIG_HOTPLUG_PCI is not set + +# +# Executable file formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set +# CONFIG_BINFMT_MISC is not set +CONFIG_TRAD_SIGNALS=y + +# +# Power management options +# +CONFIG_ARCH_SUSPEND_POSSIBLE=y +# CONFIG_PM is not set +CONFIG_NET=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_PACKET_MMAP=y +CONFIG_UNIX=y +CONFIG_XFRM=y +# CONFIG_XFRM_USER is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set +CONFIG_XFRM_IPCOMP=y +# CONFIG_NET_KEY is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +CONFIG_ASK_IP_FIB_HASH=y +# CONFIG_IP_FIB_TRIE is not set +CONFIG_IP_FIB_HASH=y +# CONFIG_IP_MULTIPLE_TABLES is not set +# CONFIG_IP_ROUTE_MULTIPATH is not set +# CONFIG_IP_ROUTE_VERBOSE is not set +CONFIG_IP_PNP=y +# CONFIG_IP_PNP_DHCP is not set +# CONFIG_IP_PNP_BOOTP is not set +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_IP_MROUTE is not set +# CONFIG_ARPD is not set +CONFIG_SYN_COOKIES=y +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET_XFRM_MODE_TUNNEL is not set +# CONFIG_INET_XFRM_MODE_BEET is not set +# CONFIG_INET_LRO is not set +# CONFIG_INET_DIAG is not set +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +# CONFIG_TCP_MD5SIG is not set +CONFIG_IPV6=y +CONFIG_IPV6_PRIVACY=y +# CONFIG_IPV6_ROUTER_PREF is not set +# CONFIG_IPV6_OPTIMISTIC_DAD is not set +CONFIG_INET6_AH=y +CONFIG_INET6_ESP=y +CONFIG_INET6_IPCOMP=y +# CONFIG_IPV6_MIP6 is not set +CONFIG_INET6_XFRM_TUNNEL=y +CONFIG_INET6_TUNNEL=y +# CONFIG_INET6_XFRM_MODE_TRANSPORT is not set +# CONFIG_INET6_XFRM_MODE_TUNNEL is not set +# CONFIG_INET6_XFRM_MODE_BEET is not set +# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set +# CONFIG_IPV6_SIT is not set +CONFIG_IPV6_TUNNEL=y +# CONFIG_IPV6_MULTIPLE_TABLES is not set +# CONFIG_IPV6_MROUTE is not set +# CONFIG_NETWORK_SECMARK is not set +CONFIG_NETFILTER=y +# CONFIG_NETFILTER_DEBUG is not set +CONFIG_NETFILTER_ADVANCED=y +# CONFIG_BRIDGE_NETFILTER is not set + +# +# Core Netfilter Configuration +# +# CONFIG_NETFILTER_NETLINK_QUEUE is not set +# CONFIG_NETFILTER_NETLINK_LOG is not set +# CONFIG_NF_CONNTRACK is not set +CONFIG_NETFILTER_XTABLES=y +# CONFIG_NETFILTER_XT_TARGET_CLASSIFY is not set +# CONFIG_NETFILTER_XT_TARGET_MARK is not set +# CONFIG_NETFILTER_XT_TARGET_NFLOG is not set +# CONFIG_NETFILTER_XT_TARGET_NFQUEUE is not set +# CONFIG_NETFILTER_XT_TARGET_RATEEST is not set +# CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set +# CONFIG_NETFILTER_XT_MATCH_COMMENT is not set +# CONFIG_NETFILTER_XT_MATCH_DCCP is not set +# CONFIG_NETFILTER_XT_MATCH_DSCP is not set +# CONFIG_NETFILTER_XT_MATCH_ESP is not set +# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set +# CONFIG_NETFILTER_XT_MATCH_HL is not set +# CONFIG_NETFILTER_XT_MATCH_IPRANGE is not set +# CONFIG_NETFILTER_XT_MATCH_LENGTH is not set +# CONFIG_NETFILTER_XT_MATCH_LIMIT is not set +# CONFIG_NETFILTER_XT_MATCH_MAC is not set +# CONFIG_NETFILTER_XT_MATCH_MARK is not set +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y +# CONFIG_NETFILTER_XT_MATCH_OWNER is not set +# CONFIG_NETFILTER_XT_MATCH_POLICY is not set +# CONFIG_NETFILTER_XT_MATCH_PKTTYPE is not set +# CONFIG_NETFILTER_XT_MATCH_QUOTA is not set +# CONFIG_NETFILTER_XT_MATCH_RATEEST is not set +# CONFIG_NETFILTER_XT_MATCH_REALM is not set +# CONFIG_NETFILTER_XT_MATCH_RECENT is not set +# CONFIG_NETFILTER_XT_MATCH_SCTP is not set +# CONFIG_NETFILTER_XT_MATCH_STATISTIC is not set +# CONFIG_NETFILTER_XT_MATCH_STRING is not set +# CONFIG_NETFILTER_XT_MATCH_TCPMSS is not set +# CONFIG_NETFILTER_XT_MATCH_TIME is not set +# CONFIG_NETFILTER_XT_MATCH_U32 is not set +# CONFIG_IP_VS is not set + +# +# IP: Netfilter Configuration +# +# CONFIG_NF_DEFRAG_IPV4 is not set +# CONFIG_IP_NF_QUEUE is not set +CONFIG_IP_NF_IPTABLES=y +# CONFIG_IP_NF_MATCH_ADDRTYPE is not set +# CONFIG_IP_NF_MATCH_AH is not set +# CONFIG_IP_NF_MATCH_ECN is not set +# CONFIG_IP_NF_MATCH_TTL is not set +CONFIG_IP_NF_FILTER=y +# CONFIG_IP_NF_TARGET_REJECT is not set +# CONFIG_IP_NF_TARGET_LOG is not set +# CONFIG_IP_NF_TARGET_ULOG is not set +# CONFIG_IP_NF_MANGLE is not set +# CONFIG_IP_NF_TARGET_TTL is not set +# CONFIG_IP_NF_RAW is not set +CONFIG_IP_NF_ARPTABLES=y +CONFIG_IP_NF_ARPFILTER=y +# CONFIG_IP_NF_ARP_MANGLE is not set + +# +# IPv6: Netfilter Configuration +# +# CONFIG_IP6_NF_QUEUE is not set +CONFIG_IP6_NF_IPTABLES=y +# CONFIG_IP6_NF_MATCH_AH is not set +# CONFIG_IP6_NF_MATCH_EUI64 is not set +# CONFIG_IP6_NF_MATCH_FRAG is not set +# CONFIG_IP6_NF_MATCH_OPTS is not set +# CONFIG_IP6_NF_MATCH_HL is not set +# CONFIG_IP6_NF_MATCH_IPV6HEADER is not set +# CONFIG_IP6_NF_MATCH_MH is not set +# CONFIG_IP6_NF_MATCH_RT is not set +# CONFIG_IP6_NF_TARGET_HL is not set +# CONFIG_IP6_NF_TARGET_LOG is not set +CONFIG_IP6_NF_FILTER=y +# CONFIG_IP6_NF_TARGET_REJECT is not set +# CONFIG_IP6_NF_MANGLE is not set +# CONFIG_IP6_NF_RAW is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +CONFIG_STP=y +CONFIG_BRIDGE=y +# CONFIG_NET_DSA is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +CONFIG_LLC=y +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_PHONET is not set +CONFIG_NET_SCHED=y + +# +# Queueing/Scheduling +# +# CONFIG_NET_SCH_CBQ is not set +# CONFIG_NET_SCH_HTB is not set +# CONFIG_NET_SCH_HFSC is not set +# CONFIG_NET_SCH_PRIO is not set +# CONFIG_NET_SCH_MULTIQ is not set +# CONFIG_NET_SCH_RED is not set +# CONFIG_NET_SCH_SFQ is not set +# CONFIG_NET_SCH_TEQL is not set +CONFIG_NET_SCH_TBF=y +# CONFIG_NET_SCH_GRED is not set +# CONFIG_NET_SCH_DSMARK is not set +# CONFIG_NET_SCH_NETEM is not set +# CONFIG_NET_SCH_DRR is not set + +# +# Classification +# +# CONFIG_NET_CLS_BASIC is not set +# CONFIG_NET_CLS_TCINDEX is not set +# CONFIG_NET_CLS_ROUTE4 is not set +# CONFIG_NET_CLS_FW is not set +# CONFIG_NET_CLS_U32 is not set +# CONFIG_NET_CLS_RSVP is not set +# CONFIG_NET_CLS_RSVP6 is not set +# CONFIG_NET_CLS_FLOW is not set +# CONFIG_NET_EMATCH is not set +# CONFIG_NET_CLS_ACT is not set +CONFIG_NET_SCH_FIFO=y +# CONFIG_DCB is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set +# CONFIG_WIRELESS is not set +# CONFIG_WIMAX is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_CONNECTOR is not set +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_CONCAT is not set +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_TESTS is not set +# CONFIG_MTD_REDBOOT_PARTS is not set +CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_AR7_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +CONFIG_MTD_BLKDEVS=y +CONFIG_MTD_BLOCK=y +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_MTD_OOPS is not set + +# +# RAM/ROM/Flash chip drivers +# +# CONFIG_MTD_CFI is not set +# CONFIG_MTD_JEDECPROBE is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +# CONFIG_MTD_INTEL_VR_NOR is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_PMC551 is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +CONFIG_MTD_NAND=y +# CONFIG_MTD_NAND_VERIFY_WRITE is not set +# CONFIG_MTD_NAND_ECC_SMC is not set +# CONFIG_MTD_NAND_MUSEUM_IDS is not set +CONFIG_MTD_NAND_IDS=y +# CONFIG_MTD_NAND_DISKONCHIP is not set +# CONFIG_MTD_NAND_CAFE is not set +# CONFIG_MTD_NAND_NANDSIM is not set +# CONFIG_MTD_NAND_PLATFORM is not set +# CONFIG_MTD_ALAUDA is not set +# CONFIG_MTD_ONENAND is not set + +# +# LPDDR flash memory drivers +# +# CONFIG_MTD_LPDDR is not set + +# +# UBI - Unsorted block images +# +# CONFIG_MTD_UBI is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_CPQ_DA is not set +# CONFIG_BLK_CPQ_CISS_DA is not set +# CONFIG_BLK_DEV_DAC960 is not set +# CONFIG_BLK_DEV_UMEM is not set +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=y +# CONFIG_BLK_DEV_CRYPTOLOOP is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_SX8 is not set +# CONFIG_BLK_DEV_UB is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=32768 +# CONFIG_BLK_DEV_XIP is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +# CONFIG_BLK_DEV_HD is not set +# CONFIG_MISC_DEVICES is not set +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +# CONFIG_SCSI_TGT is not set +# CONFIG_SCSI_NETLINK is not set +# CONFIG_SCSI_PROC_FS is not set + +# +# SCSI support type (disk, tape, CD-ROM) +# +# CONFIG_BLK_DEV_SD is not set +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +# CONFIG_BLK_DEV_SR is not set +# CONFIG_CHR_DEV_SG is not set +# CONFIG_CHR_DEV_SCH is not set + +# +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs +# +# CONFIG_SCSI_MULTI_LUN is not set +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set +CONFIG_SCSI_WAIT_SCAN=m + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +# CONFIG_SCSI_LOWLEVEL is not set +# CONFIG_SCSI_DH is not set +# CONFIG_SCSI_OSD_INITIATOR is not set +CONFIG_ATA=y +# CONFIG_ATA_NONSTANDARD is not set +CONFIG_SATA_PMP=y +# CONFIG_SATA_AHCI is not set +# CONFIG_SATA_SIL24 is not set +CONFIG_ATA_SFF=y +# CONFIG_SATA_SVW is not set +# CONFIG_ATA_PIIX is not set +# CONFIG_SATA_MV is not set +# CONFIG_SATA_NV is not set +# CONFIG_PDC_ADMA is not set +# CONFIG_SATA_QSTOR is not set +# CONFIG_SATA_PROMISE is not set +# CONFIG_SATA_SX4 is not set +# CONFIG_SATA_SIL is not set +# CONFIG_SATA_SIS is not set +# CONFIG_SATA_ULI is not set +# CONFIG_SATA_VIA is not set +# CONFIG_SATA_VITESSE is not set +# CONFIG_SATA_INIC162X is not set +# CONFIG_PATA_ALI is not set +# CONFIG_PATA_AMD is not set +# CONFIG_PATA_ARTOP is not set +# CONFIG_PATA_ATIIXP is not set +# CONFIG_PATA_CMD640_PCI is not set +# CONFIG_PATA_CMD64X is not set +# CONFIG_PATA_CS5520 is not set +# CONFIG_PATA_CS5530 is not set +# CONFIG_PATA_CYPRESS is not set +# CONFIG_PATA_EFAR is not set +# CONFIG_ATA_GENERIC is not set +# CONFIG_PATA_HPT366 is not set +# CONFIG_PATA_HPT37X is not set +# CONFIG_PATA_HPT3X2N is not set +# CONFIG_PATA_HPT3X3 is not set +# CONFIG_PATA_IT821X is not set +# CONFIG_PATA_IT8213 is not set +# CONFIG_PATA_JMICRON is not set +# CONFIG_PATA_TRIFLEX is not set +# CONFIG_PATA_MARVELL is not set +# CONFIG_PATA_MPIIX is not set +# CONFIG_PATA_OLDPIIX is not set +# CONFIG_PATA_NETCELL is not set +# CONFIG_PATA_NINJA32 is not set +# CONFIG_PATA_NS87410 is not set +# CONFIG_PATA_NS87415 is not set +# CONFIG_PATA_OPTI is not set +# CONFIG_PATA_OPTIDMA is not set +# CONFIG_PATA_PDC_OLD is not set +# CONFIG_PATA_RADISYS is not set +# CONFIG_PATA_RZ1000 is not set +# CONFIG_PATA_SC1200 is not set +# CONFIG_PATA_SERVERWORKS is not set +# CONFIG_PATA_PDC2027X is not set +# CONFIG_PATA_SIL680 is not set +# CONFIG_PATA_SIS is not set +# CONFIG_PATA_VIA is not set +# CONFIG_PATA_WINBOND is not set +# CONFIG_PATA_PLATFORM is not set +# CONFIG_PATA_SCH is not set +# CONFIG_MD is not set +# CONFIG_FUSION is not set + +# +# IEEE 1394 (FireWire) support +# + +# +# Enable only one of the two stacks, unless you know what you are doing +# +# CONFIG_FIREWIRE is not set +# CONFIG_IEEE1394 is not set +# CONFIG_I2O is not set +CONFIG_NETDEVICES=y +CONFIG_COMPAT_NET_DEV_OPS=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_VETH is not set +# CONFIG_ARCNET is not set +# CONFIG_PHYLIB is not set +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +# CONFIG_AX88796 is not set +# CONFIG_HAPPYMEAL is not set +# CONFIG_SUNGEM is not set +# CONFIG_CASSINI is not set +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_SMC91X is not set +# CONFIG_DM9000 is not set +# CONFIG_ETHOC is not set +# CONFIG_DNET is not set +# CONFIG_NET_TULIP is not set +# CONFIG_HP100 is not set +# CONFIG_IBM_NEW_EMAC_ZMII is not set +# CONFIG_IBM_NEW_EMAC_RGMII is not set +# CONFIG_IBM_NEW_EMAC_TAH is not set +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set +# CONFIG_NET_PCI is not set +# CONFIG_B44 is not set +# CONFIG_ATL2 is not set +CONFIG_NETDEV_1000=y +# CONFIG_ACENIC is not set +# CONFIG_DL2K is not set +# CONFIG_E1000 is not set +# CONFIG_E1000E is not set +# CONFIG_IP1000 is not set +# CONFIG_IGB is not set +# CONFIG_IGBVF is not set +# CONFIG_NS83820 is not set +# CONFIG_HAMACHI is not set +# CONFIG_YELLOWFIN is not set +# CONFIG_R8169 is not set +# CONFIG_SIS190 is not set +# CONFIG_SKGE is not set +# CONFIG_SKY2 is not set +# CONFIG_VIA_VELOCITY is not set +# CONFIG_TIGON3 is not set +# CONFIG_BNX2 is not set +# CONFIG_QLA3XXX is not set +# CONFIG_ATL1 is not set +# CONFIG_ATL1E is not set +# CONFIG_ATL1C is not set +# CONFIG_JME is not set +CONFIG_NETDEV_10000=y +# CONFIG_CHELSIO_T1 is not set +CONFIG_CHELSIO_T3_DEPENDS=y +# CONFIG_CHELSIO_T3 is not set +# CONFIG_ENIC is not set +# CONFIG_IXGBE is not set +# CONFIG_IXGB is not set +# CONFIG_S2IO is not set +# CONFIG_VXGE is not set +# CONFIG_MYRI10GE is not set +# CONFIG_NETXEN_NIC is not set +# CONFIG_NIU is not set +# CONFIG_MLX4_EN is not set +# CONFIG_MLX4_CORE is not set +# CONFIG_TEHUTI is not set +# CONFIG_BNX2X is not set +# CONFIG_QLGE is not set +# CONFIG_SFC is not set +# CONFIG_BE2NET is not set +# CONFIG_TR is not set + +# +# Wireless LAN +# +# CONFIG_WLAN_PRE80211 is not set +# CONFIG_WLAN_80211 is not set + +# +# Enable WiMAX (Networking options) to see the WiMAX drivers +# + +# +# USB Network Adapters +# +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +CONFIG_USB_RTL8150=y +# CONFIG_USB_USBNET is not set +# CONFIG_WAN is not set +# CONFIG_FDDI is not set +# CONFIG_HIPPI is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_NET_FC is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_ISDN is not set +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set + +# +# Userland interfaces +# +# CONFIG_INPUT_MOUSEDEV is not set +# CONFIG_INPUT_JOYDEV is not set +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +# CONFIG_INPUT_KEYBOARD is not set +# CONFIG_INPUT_MOUSE is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +# CONFIG_SERIO is not set +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +# CONFIG_VT is not set +# CONFIG_DEVKMEM is not set +# CONFIG_SERIAL_NONSTANDARD is not set +# CONFIG_NOZOMI is not set + +# +# Serial drivers +# +# CONFIG_SERIAL_8250 is not set + +# +# Non-8250 serial port support +# +# CONFIG_SERIAL_JSM is not set +CONFIG_UNIX98_PTYS=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set +# CONFIG_LEGACY_PTYS is not set +# CONFIG_IPMI_HANDLER is not set +# CONFIG_HW_RANDOM is not set +# CONFIG_R3964 is not set +# CONFIG_APPLICOM is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +CONFIG_DEVPORT=y +# CONFIG_I2C is not set +# CONFIG_SPI is not set +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +# CONFIG_THERMAL_HWMON is not set +# CONFIG_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_REGULATOR is not set + +# +# Multimedia devices +# + +# +# Multimedia core support +# +# CONFIG_VIDEO_DEV is not set +# CONFIG_DVB_CORE is not set +# CONFIG_VIDEO_MEDIA is not set + +# +# Multimedia drivers +# +# CONFIG_DAB is not set + +# +# Graphics support +# +# CONFIG_DRM is not set +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +# CONFIG_FB is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set +# CONFIG_SOUND is not set +CONFIG_HID_SUPPORT=y +CONFIG_HID=y +# CONFIG_HID_DEBUG is not set +# CONFIG_HIDRAW is not set + +# +# USB Input Devices +# +CONFIG_USB_HID=y +# CONFIG_HID_PID is not set +CONFIG_USB_HIDDEV=y + +# +# Special HID drivers +# +# CONFIG_HID_A4TECH is not set +# CONFIG_HID_APPLE is not set +# CONFIG_HID_BELKIN is not set +# CONFIG_HID_CHERRY is not set +# CONFIG_HID_CHICONY is not set +# CONFIG_HID_CYPRESS is not set +# CONFIG_DRAGONRISE_FF is not set +# CONFIG_HID_EZKEY is not set +# CONFIG_HID_KYE is not set +# CONFIG_HID_GYRATION is not set +# CONFIG_HID_KENSINGTON is not set +# CONFIG_HID_LOGITECH is not set +# CONFIG_HID_MICROSOFT is not set +# CONFIG_HID_MONTEREY is not set +# CONFIG_HID_NTRIG is not set +# CONFIG_HID_PANTHERLORD is not set +# CONFIG_HID_PETALYNX is not set +# CONFIG_HID_SAMSUNG is not set +# CONFIG_HID_SONY is not set +# CONFIG_HID_SUNPLUS is not set +# CONFIG_GREENASIA_FF is not set +# CONFIG_HID_TOPSEED is not set +# CONFIG_THRUSTMASTER_FF is not set +# CONFIG_ZEROPLUS_FF is not set +CONFIG_USB_SUPPORT=y +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y +CONFIG_USB_ARCH_HAS_EHCI=y +CONFIG_USB=y +CONFIG_USB_DEBUG=y +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y + +# +# Miscellaneous USB options +# +CONFIG_USB_DEVICEFS=y +# CONFIG_USB_DEVICE_CLASS is not set +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_OTG is not set +# CONFIG_USB_OTG_WHITELIST is not set +# CONFIG_USB_OTG_BLACKLIST_HUB is not set +# CONFIG_USB_MON is not set +# CONFIG_USB_WUSB is not set +# CONFIG_USB_WUSB_CBAF is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_C67X00_HCD is not set +CONFIG_USB_EHCI_HCD=y +# CONFIG_USB_EHCI_ROOT_HUB_TT is not set +# CONFIG_USB_EHCI_TT_NEWSCHED is not set +# CONFIG_USB_OXU210HP_HCD is not set +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_ISP1760_HCD is not set +CONFIG_USB_OHCI_HCD=y +# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set +# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +# CONFIG_USB_UHCI_HCD is not set +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_WHCI_HCD is not set +# CONFIG_USB_HWA_HCD is not set + +# +# USB Device Class drivers +# +# CONFIG_USB_ACM is not set +# CONFIG_USB_PRINTER is not set +# CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may +# + +# +# also be needed; see USB_STORAGE Help for more info +# +# CONFIG_USB_STORAGE is not set +# CONFIG_USB_LIBUSUAL is not set + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set + +# +# USB port drivers +# +CONFIG_USB_SERIAL=y +CONFIG_USB_SERIAL_CONSOLE=y +# CONFIG_USB_EZUSB is not set +# CONFIG_USB_SERIAL_GENERIC is not set +# CONFIG_USB_SERIAL_AIRCABLE is not set +# CONFIG_USB_SERIAL_ARK3116 is not set +# CONFIG_USB_SERIAL_BELKIN is not set +# CONFIG_USB_SERIAL_CH341 is not set +# CONFIG_USB_SERIAL_WHITEHEAT is not set +# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set +CONFIG_USB_SERIAL_CP210X=y +# CONFIG_USB_SERIAL_CYPRESS_M8 is not set +# CONFIG_USB_SERIAL_EMPEG is not set +# CONFIG_USB_SERIAL_FTDI_SIO is not set +# CONFIG_USB_SERIAL_FUNSOFT is not set +# CONFIG_USB_SERIAL_VISOR is not set +# CONFIG_USB_SERIAL_IPAQ is not set +# CONFIG_USB_SERIAL_IR is not set +# CONFIG_USB_SERIAL_EDGEPORT is not set +# CONFIG_USB_SERIAL_EDGEPORT_TI is not set +# CONFIG_USB_SERIAL_GARMIN is not set +# CONFIG_USB_SERIAL_IPW is not set +# CONFIG_USB_SERIAL_IUU is not set +# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set +# CONFIG_USB_SERIAL_KEYSPAN is not set +# CONFIG_USB_SERIAL_KLSI is not set +# CONFIG_USB_SERIAL_KOBIL_SCT is not set +# CONFIG_USB_SERIAL_MCT_U232 is not set +# CONFIG_USB_SERIAL_MOS7720 is not set +# CONFIG_USB_SERIAL_MOS7840 is not set +# CONFIG_USB_SERIAL_MOTOROLA is not set +# CONFIG_USB_SERIAL_NAVMAN is not set +# CONFIG_USB_SERIAL_PL2303 is not set +# CONFIG_USB_SERIAL_OTI6858 is not set +# CONFIG_USB_SERIAL_QUALCOMM is not set +# CONFIG_USB_SERIAL_SPCP8X5 is not set +# CONFIG_USB_SERIAL_HP4X is not set +# CONFIG_USB_SERIAL_SAFE is not set +# CONFIG_USB_SERIAL_SIEMENS_MPI is not set +# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set +# CONFIG_USB_SERIAL_SYMBOL is not set +# CONFIG_USB_SERIAL_TI is not set +# CONFIG_USB_SERIAL_CYBERJACK is not set +# CONFIG_USB_SERIAL_XIRCOM is not set +# CONFIG_USB_SERIAL_OPTION is not set +# CONFIG_USB_SERIAL_OMNINET is not set +# CONFIG_USB_SERIAL_OPTICON is not set +# CONFIG_USB_SERIAL_DEBUG is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_BERRY_CHARGE is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_SISUSBVGA is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_TEST is not set +# CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_VST is not set +# CONFIG_USB_GADGET is not set + +# +# OTG and related infrastructure +# +# CONFIG_NOP_USB_XCEIV is not set +# CONFIG_UWB is not set +# CONFIG_MMC is not set +# CONFIG_MEMSTICK is not set +# CONFIG_NEW_LEDS is not set +# CONFIG_ACCESSIBILITY is not set +# CONFIG_INFINIBAND is not set +CONFIG_RTC_LIB=y +# CONFIG_RTC_CLASS is not set +# CONFIG_DMADEVICES is not set +# CONFIG_AUXDISPLAY is not set +# CONFIG_UIO is not set +# CONFIG_STAGING is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +# CONFIG_EXT2_FS_XATTR is not set +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=y +# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set +# CONFIG_EXT3_FS_XATTR is not set +# CONFIG_EXT4_FS is not set +CONFIG_JBD=y +# CONFIG_JBD_DEBUG is not set +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +# CONFIG_FS_POSIX_ACL is not set +CONFIG_FILE_LOCKING=y +# CONFIG_XFS_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_BTRFS_FS is not set +# CONFIG_DNOTIFY is not set +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +CONFIG_FUSE_FS=y + +# +# Caches +# +# CONFIG_FSCACHE is not set + +# +# CD-ROM/DVD Filesystems +# +# CONFIG_ISO9660_FS is not set +# CONFIG_UDF_FS is not set + +# +# DOS/FAT/NT Filesystems +# +# CONFIG_MSDOS_FS is not set +# CONFIG_VFAT_FS is not set +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_KCORE=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +# CONFIG_TMPFS_POSIX_ACL is not set +# CONFIG_HUGETLB_PAGE is not set +# CONFIG_CONFIGFS_FS is not set +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_FS_DEBUG=0 +CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_FS_WBUF_VERIFY is not set +# CONFIG_JFFS2_SUMMARY is not set +# CONFIG_JFFS2_FS_XATTR is not set +# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set +CONFIG_JFFS2_ZLIB=y +# CONFIG_JFFS2_LZO is not set +CONFIG_JFFS2_RTIME=y +# CONFIG_JFFS2_RUBIN is not set +CONFIG_CRAMFS=y +# CONFIG_SQUASHFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +# CONFIG_NILFS2_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set +CONFIG_ROOT_NFS=y +# CONFIG_NFSD is not set +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_RPCSEC_GSS_KRB5 is not set +# CONFIG_RPCSEC_GSS_SPKM3 is not set +# CONFIG_SMB_FS is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y +# CONFIG_NLS is not set +# CONFIG_DLM is not set + +# +# Kernel hacking +# +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_PRINTK_TIME=y +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +# CONFIG_MAGIC_SYSRQ is not set +# CONFIG_UNUSED_SYMBOLS is not set +CONFIG_DEBUG_FS=y +# CONFIG_HEADERS_CHECK is not set +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_SHIRQ is not set +CONFIG_DETECT_SOFTLOCKUP=y +# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set +CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 +CONFIG_DETECT_HUNG_TASK=y +# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set +CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 +# CONFIG_SCHED_DEBUG is not set +# CONFIG_SCHEDSTATS is not set +# CONFIG_TIMER_STATS is not set +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_DEBUG_PREEMPT is not set +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_RT_MUTEX_TESTER is not set +# CONFIG_DEBUG_SPINLOCK is not set +# CONFIG_DEBUG_MUTEXES is not set +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_PROVE_LOCKING is not set +# CONFIG_LOCK_STAT is not set +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_DEBUG_KOBJECT is not set +CONFIG_DEBUG_INFO=y +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_WRITECOUNT is not set +# CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_DEBUG_LIST is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_BOOT_PRINTK_DELAY is not set +# CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +# CONFIG_FAULT_INJECTION is not set +# CONFIG_PAGE_POISONING is not set +CONFIG_TRACING_SUPPORT=y + +# +# Tracers +# +# CONFIG_IRQSOFF_TRACER is not set +# CONFIG_PREEMPT_TRACER is not set +# CONFIG_SCHED_TRACER is not set +# CONFIG_CONTEXT_SWITCH_TRACER is not set +# CONFIG_EVENT_TRACER is not set +# CONFIG_BOOT_TRACER is not set +# CONFIG_TRACE_BRANCH_PROFILING is not set +# CONFIG_KMEMTRACE is not set +# CONFIG_WORKQUEUE_TRACER is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_DYNAMIC_DEBUG is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_KGDB is not set +CONFIG_CMDLINE="rw dhash_entries=1024 ihash_entries=1024 ip=10.0.1.3:10.0.1.1:10.0.1.1:255.255.255.0:zeus:eth0: root=/dev/nfs nfsroot=/nfsroot/cramfs,wsize=512,rsize=512,tcp nokgdb console=ttyUSB0,115200 memsize=252M" +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_RUNTIME_DEBUG is not set + +# +# Security options +# +# CONFIG_KEYS is not set +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +# CONFIG_SECURITY_FILE_CAPABILITIES is not set +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +# CONFIG_CRYPTO_FIPS is not set +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD=y +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_BLKCIPHER2=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_PCOMP=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +# CONFIG_CRYPTO_GF128MUL is not set +# CONFIG_CRYPTO_NULL is not set +CONFIG_CRYPTO_WORKQUEUE=y +# CONFIG_CRYPTO_CRYPTD is not set +CONFIG_CRYPTO_AUTHENC=y +# CONFIG_CRYPTO_TEST is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_SEQIV is not set + +# +# Block modes +# +CONFIG_CRYPTO_CBC=y +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +# CONFIG_CRYPTO_ECB is not set +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# +CONFIG_CRYPTO_HMAC=y +# CONFIG_CRYPTO_XCBC is not set + +# +# Digest +# +# CONFIG_CRYPTO_CRC32C is not set +# CONFIG_CRYPTO_MD4 is not set +CONFIG_CRYPTO_MD5=y +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +CONFIG_CRYPTO_SHA1=y +# CONFIG_CRYPTO_SHA256 is not set +# CONFIG_CRYPTO_SHA512 is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set + +# +# Ciphers +# +# CONFIG_CRYPTO_AES is not set +# CONFIG_CRYPTO_ANUBIS is not set +# CONFIG_CRYPTO_ARC4 is not set +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST6 is not set +CONFIG_CRYPTO_DES=y +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TWOFISH is not set + +# +# Compression +# +CONFIG_CRYPTO_DEFLATE=y +# CONFIG_CRYPTO_ZLIB is not set +# CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set +# CONFIG_CRYPTO_HW is not set +# CONFIG_BINARY_PRINTF is not set + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_GENERIC_FIND_LAST_BIT=y +# CONFIG_CRC_CCITT is not set +# CONFIG_CRC16 is not set +# CONFIG_CRC_T10DIF is not set +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +# CONFIG_LIBCRC32C is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y +CONFIG_NLATTR=y From David.Daney@caviumnetworks.com Tue May 5 01:52:26 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 05 May 2009 01:52:32 +0100 (BST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:8221 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20023636AbZEEAw0 (ORCPT ); Tue, 5 May 2009 01:52:26 +0100 Received: from exch4.caveonetworks.com (Not Verified[192.168.16.23]) by mail3.caviumnetworks.com with MailMarshal (v6,2,2,3503) id ; Mon, 04 May 2009 20:52:04 -0400 Received: from exch4.caveonetworks.com ([192.168.16.23]) by exch4.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Mon, 4 May 2009 17:51:56 -0700 Received: from dd1.caveonetworks.com ([64.169.86.201]) by exch4.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Mon, 4 May 2009 17:51:56 -0700 Message-ID: <49FF8DAC.8090701@caviumnetworks.com> Date: Mon, 04 May 2009 17:51:56 -0700 From: David Daney User-Agent: Thunderbird 2.0.0.21 (X11/20090320) MIME-Version: 1.0 To: David VomLehn CC: linux-mips@linux-mips.org, ralf@linux-mips.org Subject: Re: [PATCH 3/3] mips:powertv: Integrate Cisco Powertv platform into MIPS architecture (resend) References: <20090504225821.GA22833@cuplxvomd02.corp.sa.net> In-Reply-To: <20090504225821.GA22833@cuplxvomd02.corp.sa.net> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 05 May 2009 00:51:56.0780 (UTC) FILETIME=[B09F22C0:01C9CD1B] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22622 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Content-Length: 1064 Lines: 45 David VomLehn wrote: > Adds the Cisco PowerTV platform to the configuration and Make files so > that we can build a kernel for it. > > Signed-off-by: David VomLehn > --- > arch/mips/Kconfig | 30 + > arch/mips/Makefile | 8 + > arch/mips/configs/powertv_defconfig | 1484 +++++++++++++++++++++++++++++++++++ > 3 files changed, 1522 insertions(+), 0 deletions(-) > > diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig > index 99f7b6d..b23ec4c 100644 > --- a/arch/mips/Kconfig > +++ b/arch/mips/Kconfig [...] > > +# > +# The flag for POWERTV clock source. > +# > +config CEVT_POWERTV > + bool > + > config CEVT_SB1250 > bool > > @@ -742,6 +766,12 @@ config CSRC_R4K > select CSRC_R4K_LIB > bool > > +# > +# The flag for POWERTV clock event. > +# > +config CSRC_POWERTV > + bool > + > config CSRC_SB1250 > bool > Could/should CEVT_POWERTV and CSRC_POWERTV be either eliminated or moved to your processor specific directory? That is where the corresponding code lives. David Daney From info@goahelpline.com Tue May 5 03:11:50 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 05 May 2009 03:11:55 +0100 (BST) Received: from rv-out-0708.google.com ([209.85.198.240]:5175 "EHLO rv-out-0708.google.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20023692AbZEECLu (ORCPT ); Tue, 5 May 2009 03:11:50 +0100 Received: by rv-out-0708.google.com with SMTP id b17so1662320rvf.0 for ; Mon, 04 May 2009 19:11:47 -0700 (PDT) Received: by 10.114.111.1 with SMTP id j1mr4789210wac.153.1241489506900; Mon, 04 May 2009 19:11:46 -0700 (PDT) Received: from khushiraj ([121.245.178.110]) by mx.google.com with ESMTPS id m29sm29967284poh.11.2009.05.04.19.11.08 (version=SSLv3 cipher=RC4-MD5); Mon, 04 May 2009 19:11:46 -0700 (PDT) Message-ID: <02e101c9cd26$d5de5960$9b01a8c0@khushiraj> From: "Jokes of the Day - GHL" To: Subject: Fw: Increase brain power, 27 Health Tips & Womens Health & Thyroid Date: Tue, 5 May 2009 07:35:00 +0530 MIME-Version: 1.0 Content-Type: multipart/alternative; boundary="----=_NextPart_000_0226_01C9CD53.FF0706C0" X-Priority: 3 X-MSMail-Priority: Normal X-Mailer: Microsoft Outlook Express 6.00.2900.2180 X-MimeOLE: Produced By Microsoft MimeOLE V6.00.2900.2180 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22623 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: info@goahelpline.com Precedence: bulk X-list: linux-mips Content-Length: 7588 Lines: 208 This is a multi-part message in MIME format. ------=_NextPart_000_0226_01C9CD53.FF0706C0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Increase your Brain Power Read More : http://dhristi.co.in/increase_brain_power.html =20 =20 Womens Health Guide Read More : http://dhristi.co.in/womenshealth.html =20 =20 Breast Care & Guide Read More : http://dhristi.co.in/breast_cancer.html =20 27 Health Tips !!! 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------=_NextPart_000_0226_01C9CD53.FF0706C0-- From anemo@mba.ocn.ne.jp Tue May 5 17:11:41 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 05 May 2009 17:11:47 +0100 (BST) Received: from mba.ocn.ne.jp ([122.1.235.107]:61002 "HELO smtp.mba.ocn.ne.jp" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with SMTP id S20022385AbZEEQLl (ORCPT ); Tue, 5 May 2009 17:11:41 +0100 Received: from localhost (p8102-ipad210funabasi.chiba.ocn.ne.jp [58.88.127.102]) by smtp.mba.ocn.ne.jp (Postfix) with ESMTP id 5E826AAB7; Wed, 6 May 2009 01:11:35 +0900 (JST) Date: Wed, 06 May 2009 01:11:24 +0900 (JST) Message-Id: <20090506.011124.260797104.anemo@mba.ocn.ne.jp> To: geert@linux-m68k.org Cc: linux-mips@linux-mips.org Subject: Re: rbtx4927 and sound? From: Atsushi Nemoto In-Reply-To: <10f740e80905040945i186e995ap1ecb43c2ad3e2458@mail.gmail.com> References: <10f740e80905040945i186e995ap1ecb43c2ad3e2458@mail.gmail.com> X-Fingerprint: 6ACA 1623 39BD 9A94 9B1A B746 CA77 FE94 2874 D52F X-Pgp-Public-Key: http://wwwkeys.pgp.net/pks/lookup?op=get&search=0x2874D52F X-Mailer: Mew version 5.2 on Emacs 22.2 / Mule 5.0 (SAKAKI) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22624 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anemo@mba.ocn.ne.jp Precedence: bulk X-list: linux-mips Content-Length: 606 Lines: 14 On Mon, 4 May 2009 18:45:09 +0200, Geert Uytterhoeven wrote: > Did anyone ever try to get sound working on the Toshiba RBTX4927? > It seems the AD1881A codec is connected to PIO2-4 of the TMPR4927 SoC. I'm writing a ASoC driver for TXx9 ACLC based on (non-ASoC) driver in RBTX49xx patch from CELF Patch Archive [1]. I can send it if you want to try, though it is still under debugging. This driver depends on DMAC driver in linux-mips queue tree [2]. [1] http://tree.celinuxforum.org/CelfPubWiki/PatchArchive [2] http://www.linux-mips.org/git?p=linux-queue.git --- Atsushi Nemoto From David.Daney@caviumnetworks.com Tue May 5 17:47:45 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 05 May 2009 17:47:52 +0100 (BST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:11464 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20022612AbZEEQrp (ORCPT ); Tue, 5 May 2009 17:47:45 +0100 Received: from exch4.caveonetworks.com (Not Verified[192.168.16.23]) by mail3.caviumnetworks.com with MailMarshal (v6,2,2,3503) id ; Tue, 05 May 2009 12:45:03 -0400 Received: from exch4.caveonetworks.com ([192.168.16.23]) by exch4.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Tue, 5 May 2009 09:44:06 -0700 Received: from dd1.caveonetworks.com ([64.169.86.201]) by exch4.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Tue, 5 May 2009 09:44:06 -0700 Message-ID: <4A006CD5.8080401@caviumnetworks.com> Date: Tue, 05 May 2009 09:44:05 -0700 From: David Daney User-Agent: Thunderbird 2.0.0.21 (X11/20090320) MIME-Version: 1.0 To: David VomLehn CC: linux-mips@linux-mips.org, ralf@linux-mips.org Subject: Re: [PATCH 1/3] mips:powertv: Base files for Cisco Powertv platform (resend) References: <20090504225616.GA22321@cuplxvomd02.corp.sa.net> In-Reply-To: <20090504225616.GA22321@cuplxvomd02.corp.sa.net> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 05 May 2009 16:44:06.0270 (UTC) FILETIME=[B47381E0:01C9CDA0] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22625 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Content-Length: 3741 Lines: 126 David VomLehn wrote: > diff --git a/arch/mips/powertv/cevt-powertv.c b/arch/mips/powertv/cevt-powertv.c [...] > +static int mips_next_event(unsigned long delta, > + struct clock_event_device *evt) > +{ > + unsigned int cnt; > + int res; > + > +#ifdef CONFIG_MIPS_MT_SMTC > + { > + unsigned long flags, vpflags; > + local_irq_save(flags); > + vpflags = dvpe(); > +#endif > + cnt = read_c0_count(); > + cnt += delta; > + write_c0_compare(cnt); > + res = ((int)(read_c0_count() - cnt) > 0) ? -ETIME : 0; > +#ifdef CONFIG_MIPS_MT_SMTC > + evpe(vpflags); > + local_irq_restore(flags); > + } > +#endif > + return res; Does this cpu have MIPS_MT? If not you could remove the #ifdef (actually you could remove it in any case). [...] > diff --git a/arch/mips/powertv/csrc-powertv.c b/arch/mips/powertv/csrc-powertv.c > new file mode 100644 > index 0000000..c032660 > --- /dev/null > +++ b/arch/mips/powertv/csrc-powertv.c > @@ -0,0 +1,84 @@ > +/* > + * Copyright (C) 2008 Scientific-Atlanta, Inc. > + * > + * This program is free software; you can redistribute it and/or > + * modify it under the terms of the GNU General Public License > + * as published by the Free Software Foundation; either version 2 > + * of the License, or (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, write to the Free Software > + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. > + */ > +/* > + * The file comes from kernel/csrc-r4k.c > + */ Could you just use kernel/csrc-r4k.c, and move your mips_get_pll_freq() to a different file (init.c or time.c)? > +#include > +#include > + > +#include /* Not included in linux/time.h */ > + > +#include > +#include "powertv-clock.h" > + > +/* MIPS PLL Register Definitions */ > +#define PLL_GET_M(x) (((x) >> 8) & 0x000000FF) > +#define PLL_GET_N(x) (((x) >> 16) & 0x000000FF) > +#define PLL_GET_P(x) (((x) >> 24) & 0x00000007) > + > +/* > + * returns: Clock frequency in kHz > + */ > +unsigned int __init mips_get_pll_freq(void) > +{ > + unsigned int pll_reg, m, n, p; > + unsigned int fin = 54000; /* Base frequency in kHz */ > + unsigned int fout; > + > + /* Read PLL register setting */ > + pll_reg = asic_read(MIPS_PLL_SETUP); > + m = PLL_GET_M(pll_reg); > + n = PLL_GET_N(pll_reg); > + p = PLL_GET_P(pll_reg); > + pr_info("MIPS PLL Register:0x%x M=%d N=%d P=%d\n", pll_reg, m, n, p); > + > + /* Calculate clock frequency = (2 * N * 54MHz) / (M * (2**P)) */ > + fout = ((2 * n * fin) / (m * (0x01 << p))); > + > + pr_info("MIPS Clock Freq=%d kHz\n", fout); > + > + return fout; > +} > + > +static cycle_t c0_hpt_read(struct clocksource *cs) > +{ > + return read_c0_count(); > +} > + > +static struct clocksource clocksource_mips = { > + .name = "powertv-counter", > + .read = c0_hpt_read, > + .mask = CLOCKSOURCE_MASK(32), > + .flags = CLOCK_SOURCE_IS_CONTINUOUS, > +}; > + > +void __init powertv_clocksource_init(void) > +{ > + unsigned int pll_freq = mips_get_pll_freq(); > + > + pr_info("CPU frequency %d.%02d MHz\n", pll_freq / 1000, > + (pll_freq % 1000) * 100 / 1000); > + > + mips_hpt_frequency = pll_freq / 2 * 1000; > + > + clocksource_mips.rating = 200 + mips_hpt_frequency / 10000000; > + > + clocksource_set_clock(&clocksource_mips, mips_hpt_frequency); > + > + clocksource_register(&clocksource_mips); > +} From David.Daney@caviumnetworks.com Tue May 5 20:51:24 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 05 May 2009 20:51:30 +0100 (BST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:29386 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20023658AbZEETvY (ORCPT ); Tue, 5 May 2009 20:51:24 +0100 Received: from exch4.caveonetworks.com (Not Verified[192.168.16.23]) by mail3.caviumnetworks.com with MailMarshal (v6,2,2,3503) id ; Tue, 05 May 2009 15:50:38 -0400 Received: from exch4.caveonetworks.com ([192.168.16.23]) by exch4.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Tue, 5 May 2009 12:49:51 -0700 Received: from dd1.caveonetworks.com ([64.169.86.201]) by exch4.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Tue, 5 May 2009 12:49:51 -0700 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.2/8.14.2) with ESMTP id n45Jnmve000688; Tue, 5 May 2009 12:49:49 -0700 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.2/8.14.2/Submit) id n45JnlnU000686; Tue, 5 May 2009 12:49:47 -0700 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org, florian@openwrt.org Cc: David Daney Subject: [PATCH] MIPS: Use force_sig when handling address errors. Date: Tue, 5 May 2009 12:49:47 -0700 Message-Id: <1241552987-662-1-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.6.0.6 X-OriginalArrivalTime: 05 May 2009 19:49:51.0409 (UTC) FILETIME=[A778C210:01C9CDBA] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22626 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Content-Length: 1234 Lines: 45 When init is started it is SIGNAL_UNKILLABLE. If it were to get an address error, we would try to send it SIGBUS, but it would be ignored and the faulting instruction restarted. This results in an endless loop. We need to use force_sig() instead so it will actually die and give us some useful information. Reported-by: Florian Fainelli Signed-off-by: David Daney --- arch/mips/kernel/unaligned.c | 6 +++--- 1 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/mips/kernel/unaligned.c b/arch/mips/kernel/unaligned.c index bf4c4a9..67bd626 100644 --- a/arch/mips/kernel/unaligned.c +++ b/arch/mips/kernel/unaligned.c @@ -482,19 +482,19 @@ fault: return; die_if_kernel("Unhandled kernel unaligned access", regs); - send_sig(SIGSEGV, current, 1); + force_sig(SIGSEGV, current); return; sigbus: die_if_kernel("Unhandled kernel unaligned access", regs); - send_sig(SIGBUS, current, 1); + force_sig(SIGBUS, current); return; sigill: die_if_kernel("Unhandled kernel unaligned access or invalid instruction", regs); - send_sig(SIGILL, current, 1); + force_sig(SIGILL, current); } asmlinkage void do_ade(struct pt_regs *regs) -- 1.6.0.6 From ralf@h5.dl5rb.org.uk Tue May 5 21:32:38 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 05 May 2009 21:32:45 +0100 (BST) Received: from h5.dl5rb.org.uk ([81.2.74.5]:52289 "EHLO h5.dl5rb.org.uk" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20023987AbZEEUci (ORCPT ); Tue, 5 May 2009 21:32:38 +0100 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id n45KWXv1025465; Tue, 5 May 2009 21:32:33 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id n45KWW48025463; Tue, 5 May 2009 21:32:32 +0100 Date: Tue, 5 May 2009 21:32:32 +0100 From: Ralf Baechle To: David Daney Cc: linux-mips@linux-mips.org, florian@openwrt.org Subject: Re: [PATCH] MIPS: Use force_sig when handling address errors. Message-ID: <20090505203231.GA25433@linux-mips.org> References: <1241552987-662-1-git-send-email-ddaney@caviumnetworks.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1241552987-662-1-git-send-email-ddaney@caviumnetworks.com> User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22627 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Content-Length: 533 Lines: 17 On Tue, May 05, 2009 at 12:49:47PM -0700, David Daney wrote: > When init is started it is SIGNAL_UNKILLABLE. If it were to get an > address error, we would try to send it SIGBUS, but it would be ignored > and the faulting instruction restarted. This results in an endless > loop. > > We need to use force_sig() instead so it will actually die and give us > some useful information. > > Reported-by: Florian Fainelli > > Signed-off-by: David Daney Thanks! Will apply. Ralf From David.Daney@caviumnetworks.com Wed May 6 01:32:49 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 06 May 2009 01:32:54 +0100 (BST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:15113 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20023714AbZEFAct (ORCPT ); Wed, 6 May 2009 01:32:49 +0100 Received: from exch4.caveonetworks.com (Not Verified[192.168.16.23]) by mail3.caviumnetworks.com with MailMarshal (v6,2,2,3503) id ; Tue, 05 May 2009 20:32:13 -0400 Received: from exch4.caveonetworks.com ([192.168.16.23]) by exch4.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Tue, 5 May 2009 17:32:04 -0700 Received: from dd1.caveonetworks.com ([64.169.86.201]) by exch4.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Tue, 5 May 2009 17:32:04 -0700 Message-ID: <4A00DA84.5040101@caviumnetworks.com> Date: Tue, 05 May 2009 17:32:04 -0700 From: David Daney User-Agent: Thunderbird 2.0.0.21 (X11/20090320) MIME-Version: 1.0 To: gregkh@suse.de, Ralf Baechle CC: linux-mips Subject: [PATCH 0/7] Staging: Octeon-ethernet driver. Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 06 May 2009 00:32:04.0176 (UTC) FILETIME=[142FF500:01C9CDE2] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22628 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Content-Length: 10558 Lines: 181 This patch set introduces the octeon-ethernet driver into the drivers/staging tree. The Octeon is a mips64r2 base multi-core SOC family. The first five patches are small tweaks to the existing octeon support that are required by the ethernet driver. I would expect them to be merged via Ralf's linux-mips.org tree. The last two are the driver, and would probably be merged via the drivers/staging tree. However since they depend on the first five, they probably shouldn't be merged until those five are merged. I will reply with the seven patches. David Daney (7): MIPS: Add named alloc functions to OCTEON boot monitor memory allocator. MIPS: Export cvmx_sysinfo_get needed by octeon-ethernet driver. MIPS: Cavium-Octeon: Add more board type constants. MIPS: Cavium-Octeon: Add more chip specific feature tests. MIPS: Export erratum function needed by octeon-ethernet driver. [Staging] Add octeon-ethernet driver files. [Staging] Hookup octeon-ethernet driver. arch/mips/cavium-octeon/executive/cvmx-bootmem.c | 104 + .../cavium-octeon/executive/cvmx-helper-errata.c | 3 + arch/mips/cavium-octeon/executive/cvmx-sysinfo.c | 2 + arch/mips/include/asm/octeon/cvmx-bootinfo.h | 13 + arch/mips/include/asm/octeon/cvmx-bootmem.h | 85 + arch/mips/include/asm/octeon/octeon-feature.h | 27 + drivers/staging/Kconfig | 2 + drivers/staging/Makefile | 1 + drivers/staging/octeon/Kconfig | 12 + drivers/staging/octeon/Makefile | 30 + drivers/staging/octeon/cvmx-address.h | 274 +++ drivers/staging/octeon/cvmx-asxx-defs.h | 475 ++++ drivers/staging/octeon/cvmx-cmd-queue.c | 306 +++ drivers/staging/octeon/cvmx-cmd-queue.h | 617 +++++ drivers/staging/octeon/cvmx-config.h | 169 ++ drivers/staging/octeon/cvmx-dbg-defs.h | 72 + drivers/staging/octeon/cvmx-fau.h | 597 +++++ drivers/staging/octeon/cvmx-fpa-defs.h | 403 ++++ drivers/staging/octeon/cvmx-fpa.c | 183 ++ drivers/staging/octeon/cvmx-fpa.h | 299 +++ drivers/staging/octeon/cvmx-gmxx-defs.h | 2529 ++++++++++++++++++++ drivers/staging/octeon/cvmx-helper-board.c | 706 ++++++ drivers/staging/octeon/cvmx-helper-board.h | 180 ++ drivers/staging/octeon/cvmx-helper-fpa.c | 243 ++ drivers/staging/octeon/cvmx-helper-fpa.h | 64 + drivers/staging/octeon/cvmx-helper-loop.c | 85 + drivers/staging/octeon/cvmx-helper-loop.h | 59 + drivers/staging/octeon/cvmx-helper-npi.c | 113 + drivers/staging/octeon/cvmx-helper-npi.h | 60 + drivers/staging/octeon/cvmx-helper-rgmii.c | 525 ++++ drivers/staging/octeon/cvmx-helper-rgmii.h | 110 + drivers/staging/octeon/cvmx-helper-sgmii.c | 550 +++++ drivers/staging/octeon/cvmx-helper-sgmii.h | 104 + drivers/staging/octeon/cvmx-helper-spi.c | 195 ++ drivers/staging/octeon/cvmx-helper-spi.h | 84 + drivers/staging/octeon/cvmx-helper-util.c | 433 ++++ drivers/staging/octeon/cvmx-helper-util.h | 215 ++ drivers/staging/octeon/cvmx-helper-xaui.c | 348 +++ drivers/staging/octeon/cvmx-helper-xaui.h | 103 + drivers/staging/octeon/cvmx-helper.c | 1058 ++++++++ drivers/staging/octeon/cvmx-helper.h | 227 ++ drivers/staging/octeon/cvmx-interrupt-decodes.c | 371 +++ drivers/staging/octeon/cvmx-interrupt-rsl.c | 140 ++ drivers/staging/octeon/cvmx-ipd.h | 338 +++ drivers/staging/octeon/cvmx-mdio.h | 506 ++++ drivers/staging/octeon/cvmx-packet.h | 65 + drivers/staging/octeon/cvmx-pcsx-defs.h | 370 +++ drivers/staging/octeon/cvmx-pcsxx-defs.h | 316 +++ drivers/staging/octeon/cvmx-pip-defs.h | 1267 ++++++++++ drivers/staging/octeon/cvmx-pip.h | 524 ++++ drivers/staging/octeon/cvmx-pko-defs.h | 1133 +++++++++ drivers/staging/octeon/cvmx-pko.c | 506 ++++ drivers/staging/octeon/cvmx-pko.h | 610 +++++ drivers/staging/octeon/cvmx-pow.h | 1982 +++++++++++++++ drivers/staging/octeon/cvmx-scratch.h | 139 ++ drivers/staging/octeon/cvmx-smix-defs.h | 178 ++ drivers/staging/octeon/cvmx-spi.c | 667 ++++++ drivers/staging/octeon/cvmx-spi.h | 269 +++ drivers/staging/octeon/cvmx-spxx-defs.h | 347 +++ drivers/staging/octeon/cvmx-srxx-defs.h | 126 + drivers/staging/octeon/cvmx-stxx-defs.h | 292 +++ drivers/staging/octeon/cvmx-wqe.h | 397 +++ drivers/staging/octeon/ethernet-common.c | 328 +++ drivers/staging/octeon/ethernet-common.h | 29 + drivers/staging/octeon/ethernet-defines.h | 134 + drivers/staging/octeon/ethernet-mdio.c | 231 ++ drivers/staging/octeon/ethernet-mdio.h | 46 + drivers/staging/octeon/ethernet-mem.c | 198 ++ drivers/staging/octeon/ethernet-mem.h | 29 + drivers/staging/octeon/ethernet-proc.c | 256 ++ drivers/staging/octeon/ethernet-proc.h | 29 + drivers/staging/octeon/ethernet-rgmii.c | 397 +++ drivers/staging/octeon/ethernet-rx.c | 505 ++++ drivers/staging/octeon/ethernet-rx.h | 33 + drivers/staging/octeon/ethernet-sgmii.c | 129 + drivers/staging/octeon/ethernet-spi.c | 323 +++ drivers/staging/octeon/ethernet-tx.c | 634 +++++ drivers/staging/octeon/ethernet-tx.h | 32 + drivers/staging/octeon/ethernet-util.h | 81 + drivers/staging/octeon/ethernet-xaui.c | 127 + drivers/staging/octeon/ethernet.c | 507 ++++ drivers/staging/octeon/octeon-ethernet.h | 127 + 82 files changed, 26383 insertions(+), 0 deletions(-) create mode 100644 drivers/staging/octeon/Kconfig create mode 100644 drivers/staging/octeon/Makefile create mode 100644 drivers/staging/octeon/cvmx-address.h create mode 100644 drivers/staging/octeon/cvmx-asxx-defs.h create mode 100644 drivers/staging/octeon/cvmx-cmd-queue.c create mode 100644 drivers/staging/octeon/cvmx-cmd-queue.h create mode 100644 drivers/staging/octeon/cvmx-config.h create mode 100644 drivers/staging/octeon/cvmx-dbg-defs.h create mode 100644 drivers/staging/octeon/cvmx-fau.h create mode 100644 drivers/staging/octeon/cvmx-fpa-defs.h create mode 100644 drivers/staging/octeon/cvmx-fpa.c create mode 100644 drivers/staging/octeon/cvmx-fpa.h create mode 100644 drivers/staging/octeon/cvmx-gmxx-defs.h create mode 100644 drivers/staging/octeon/cvmx-helper-board.c create mode 100644 drivers/staging/octeon/cvmx-helper-board.h create mode 100644 drivers/staging/octeon/cvmx-helper-fpa.c create mode 100644 drivers/staging/octeon/cvmx-helper-fpa.h create mode 100644 drivers/staging/octeon/cvmx-helper-loop.c create mode 100644 drivers/staging/octeon/cvmx-helper-loop.h create mode 100644 drivers/staging/octeon/cvmx-helper-npi.c create mode 100644 drivers/staging/octeon/cvmx-helper-npi.h create mode 100644 drivers/staging/octeon/cvmx-helper-rgmii.c create mode 100644 drivers/staging/octeon/cvmx-helper-rgmii.h create mode 100644 drivers/staging/octeon/cvmx-helper-sgmii.c create mode 100644 drivers/staging/octeon/cvmx-helper-sgmii.h create mode 100644 drivers/staging/octeon/cvmx-helper-spi.c create mode 100644 drivers/staging/octeon/cvmx-helper-spi.h create mode 100644 drivers/staging/octeon/cvmx-helper-util.c create mode 100644 drivers/staging/octeon/cvmx-helper-util.h create mode 100644 drivers/staging/octeon/cvmx-helper-xaui.c create mode 100644 drivers/staging/octeon/cvmx-helper-xaui.h create mode 100644 drivers/staging/octeon/cvmx-helper.c create mode 100644 drivers/staging/octeon/cvmx-helper.h create mode 100644 drivers/staging/octeon/cvmx-interrupt-decodes.c create mode 100644 drivers/staging/octeon/cvmx-interrupt-rsl.c create mode 100644 drivers/staging/octeon/cvmx-ipd.h create mode 100644 drivers/staging/octeon/cvmx-mdio.h create mode 100644 drivers/staging/octeon/cvmx-packet.h create mode 100644 drivers/staging/octeon/cvmx-pcsx-defs.h create mode 100644 drivers/staging/octeon/cvmx-pcsxx-defs.h create mode 100644 drivers/staging/octeon/cvmx-pip-defs.h create mode 100644 drivers/staging/octeon/cvmx-pip.h create mode 100644 drivers/staging/octeon/cvmx-pko-defs.h create mode 100644 drivers/staging/octeon/cvmx-pko.c create mode 100644 drivers/staging/octeon/cvmx-pko.h create mode 100644 drivers/staging/octeon/cvmx-pow.h create mode 100644 drivers/staging/octeon/cvmx-scratch.h create mode 100644 drivers/staging/octeon/cvmx-smix-defs.h create mode 100644 drivers/staging/octeon/cvmx-spi.c create mode 100644 drivers/staging/octeon/cvmx-spi.h create mode 100644 drivers/staging/octeon/cvmx-spxx-defs.h create mode 100644 drivers/staging/octeon/cvmx-srxx-defs.h create mode 100644 drivers/staging/octeon/cvmx-stxx-defs.h create mode 100644 drivers/staging/octeon/cvmx-wqe.h create mode 100644 drivers/staging/octeon/ethernet-common.c create mode 100644 drivers/staging/octeon/ethernet-common.h create mode 100644 drivers/staging/octeon/ethernet-defines.h create mode 100644 drivers/staging/octeon/ethernet-mdio.c create mode 100644 drivers/staging/octeon/ethernet-mdio.h create mode 100644 drivers/staging/octeon/ethernet-mem.c create mode 100644 drivers/staging/octeon/ethernet-mem.h create mode 100644 drivers/staging/octeon/ethernet-proc.c create mode 100644 drivers/staging/octeon/ethernet-proc.h create mode 100644 drivers/staging/octeon/ethernet-rgmii.c create mode 100644 drivers/staging/octeon/ethernet-rx.c create mode 100644 drivers/staging/octeon/ethernet-rx.h create mode 100644 drivers/staging/octeon/ethernet-sgmii.c create mode 100644 drivers/staging/octeon/ethernet-spi.c create mode 100644 drivers/staging/octeon/ethernet-tx.c create mode 100644 drivers/staging/octeon/ethernet-tx.h create mode 100644 drivers/staging/octeon/ethernet-util.h create mode 100644 drivers/staging/octeon/ethernet-xaui.c create mode 100644 drivers/staging/octeon/ethernet.c create mode 100644 drivers/staging/octeon/octeon-ethernet.h From David.Daney@caviumnetworks.com Wed May 6 01:36:27 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 06 May 2009 01:36:33 +0100 (BST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:16892 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20021296AbZEFAg1 (ORCPT ); Wed, 6 May 2009 01:36:27 +0100 Received: from exch4.caveonetworks.com (Not Verified[192.168.16.23]) by mail3.caviumnetworks.com with MailMarshal (v6,2,2,3503) id ; Tue, 05 May 2009 20:36:16 -0400 Received: from exch4.caveonetworks.com ([192.168.16.23]) by exch4.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Tue, 5 May 2009 17:35:29 -0700 Received: from dd1.caveonetworks.com ([64.169.86.201]) by exch4.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Tue, 5 May 2009 17:35:28 -0700 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.2/8.14.2) with ESMTP id n460ZO9q022755; Tue, 5 May 2009 17:35:24 -0700 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.2/8.14.2/Submit) id n460ZMKe022753; Tue, 5 May 2009 17:35:22 -0700 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org, gregkh@suse.de Cc: David Daney Subject: [PATCH 1/7] MIPS: Add named alloc functions to OCTEON boot monitor memory allocator. Date: Tue, 5 May 2009 17:35:16 -0700 Message-Id: <1241570122-22728-1-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.6.0.6 In-Reply-To: <4A00DA84.5040101@caviumnetworks.com> References: <4A00DA84.5040101@caviumnetworks.com> X-OriginalArrivalTime: 06 May 2009 00:35:28.0909 (UTC) FILETIME=[8E37BBD0:01C9CDE2] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22629 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Content-Length: 8876 Lines: 247 The various Octeon ethernet drivers use these new functions. Signed-off-by: David Daney --- arch/mips/cavium-octeon/executive/cvmx-bootmem.c | 104 ++++++++++++++++++++++ arch/mips/include/asm/octeon/cvmx-bootmem.h | 85 ++++++++++++++++++ 2 files changed, 189 insertions(+), 0 deletions(-) diff --git a/arch/mips/cavium-octeon/executive/cvmx-bootmem.c b/arch/mips/cavium-octeon/executive/cvmx-bootmem.c index 4f5a08b..25666da 100644 --- a/arch/mips/cavium-octeon/executive/cvmx-bootmem.c +++ b/arch/mips/cavium-octeon/executive/cvmx-bootmem.c @@ -31,6 +31,7 @@ */ #include +#include #include #include @@ -97,6 +98,33 @@ void *cvmx_bootmem_alloc(uint64_t size, uint64_t alignment) return cvmx_bootmem_alloc_range(size, alignment, 0, 0); } +void *cvmx_bootmem_alloc_named_range(uint64_t size, uint64_t min_addr, + uint64_t max_addr, uint64_t align, + char *name) +{ + int64_t addr; + + addr = cvmx_bootmem_phy_named_block_alloc(size, min_addr, max_addr, + align, name, 0); + if (addr >= 0) + return cvmx_phys_to_ptr(addr); + else + return NULL; +} + +void *cvmx_bootmem_alloc_named_address(uint64_t size, uint64_t address, + char *name) +{ + return cvmx_bootmem_alloc_named_range(size, address, address + size, + 0, name); +} + +void *cvmx_bootmem_alloc_named(uint64_t size, uint64_t alignment, char *name) +{ + return cvmx_bootmem_alloc_named_range(size, 0, 0, alignment, name); +} +EXPORT_SYMBOL(cvmx_bootmem_alloc_named); + int cvmx_bootmem_free_named(char *name) { return cvmx_bootmem_phy_named_block_free(name, 0); @@ -106,6 +134,7 @@ struct cvmx_bootmem_named_block_desc *cvmx_bootmem_find_named_block(char *name) { return cvmx_bootmem_phy_named_block_find(name, 0); } +EXPORT_SYMBOL(cvmx_bootmem_find_named_block); void cvmx_bootmem_lock(void) { @@ -584,3 +613,78 @@ int cvmx_bootmem_phy_named_block_free(char *name, uint32_t flags) cvmx_bootmem_unlock(); return named_block_ptr != NULL; /* 0 on failure, 1 on success */ } + +int64_t cvmx_bootmem_phy_named_block_alloc(uint64_t size, uint64_t min_addr, + uint64_t max_addr, + uint64_t alignment, + char *name, + uint32_t flags) +{ + int64_t addr_allocated; + struct cvmx_bootmem_named_block_desc *named_block_desc_ptr; + +#ifdef DEBUG + cvmx_dprintf("cvmx_bootmem_phy_named_block_alloc: size: 0x%llx, min: " + "0x%llx, max: 0x%llx, align: 0x%llx, name: %s\n", + (unsigned long long)size, + (unsigned long long)min_addr, + (unsigned long long)max_addr, + (unsigned long long)alignment, + name); +#endif + if (cvmx_bootmem_desc->major_version != 3) { + cvmx_dprintf("ERROR: Incompatible bootmem descriptor version: " + "%d.%d at addr: %p\n", + (int)cvmx_bootmem_desc->major_version, + (int)cvmx_bootmem_desc->minor_version, + cvmx_bootmem_desc); + return -1; + } + + /* + * Take lock here, as name lookup/block alloc/name add need to + * be atomic. + */ + if (!(flags & CVMX_BOOTMEM_FLAG_NO_LOCKING)) + cvmx_spinlock_lock((cvmx_spinlock_t *)&(cvmx_bootmem_desc->lock)); + + /* Get pointer to first available named block descriptor */ + named_block_desc_ptr = + cvmx_bootmem_phy_named_block_find(NULL, + flags | CVMX_BOOTMEM_FLAG_NO_LOCKING); + + /* + * Check to see if name already in use, return error if name + * not available or no more room for blocks. + */ + if (cvmx_bootmem_phy_named_block_find(name, + flags | CVMX_BOOTMEM_FLAG_NO_LOCKING) || !named_block_desc_ptr) { + if (!(flags & CVMX_BOOTMEM_FLAG_NO_LOCKING)) + cvmx_spinlock_unlock((cvmx_spinlock_t *)&(cvmx_bootmem_desc->lock)); + return -1; + } + + + /* + * Round size up to mult of minimum alignment bytes We need + * the actual size allocated to allow for blocks to be + * coallesced when they are freed. The alloc routine does the + * same rounding up on all allocations. + */ + size = __ALIGN_MASK(size, (CVMX_BOOTMEM_ALIGNMENT_SIZE - 1)); + + addr_allocated = cvmx_bootmem_phy_alloc(size, min_addr, max_addr, + alignment, + flags | CVMX_BOOTMEM_FLAG_NO_LOCKING); + if (addr_allocated >= 0) { + named_block_desc_ptr->base_addr = addr_allocated; + named_block_desc_ptr->size = size; + strncpy(named_block_desc_ptr->name, name, + cvmx_bootmem_desc->named_block_name_len); + named_block_desc_ptr->name[cvmx_bootmem_desc->named_block_name_len - 1] = 0; + } + + if (!(flags & CVMX_BOOTMEM_FLAG_NO_LOCKING)) + cvmx_spinlock_unlock((cvmx_spinlock_t *)&(cvmx_bootmem_desc->lock)); + return addr_allocated; +} diff --git a/arch/mips/include/asm/octeon/cvmx-bootmem.h b/arch/mips/include/asm/octeon/cvmx-bootmem.h index 1cbe4b5..8e708bd 100644 --- a/arch/mips/include/asm/octeon/cvmx-bootmem.h +++ b/arch/mips/include/asm/octeon/cvmx-bootmem.h @@ -183,6 +183,64 @@ extern void *cvmx_bootmem_alloc_range(uint64_t size, uint64_t alignment, * Returns 0 on failure, * !0 on success */ + + +/** + * Allocate a block of memory from the free list that was passed + * to the application by the bootloader, and assign it a name in the + * global named block table. (part of the cvmx_bootmem_descriptor_t structure) + * Named blocks can later be freed. + * + * @size: Size in bytes of block to allocate + * @alignment: Alignment required - must be power of 2 + * @name: name of block - must be less than CVMX_BOOTMEM_NAME_LEN bytes + * + * Returns a pointer to block of memory, NULL on error + */ +extern void *cvmx_bootmem_alloc_named(uint64_t size, uint64_t alignment, + char *name); + + + +/** + * Allocate a block of memory from the free list that was passed + * to the application by the bootloader, and assign it a name in the + * global named block table. (part of the cvmx_bootmem_descriptor_t structure) + * Named blocks can later be freed. + * + * @size: Size in bytes of block to allocate + * @address: Physical address to allocate memory at. If this + * memory is not available, the allocation fails. + * @name: name of block - must be less than CVMX_BOOTMEM_NAME_LEN + * bytes + * + * Returns a pointer to block of memory, NULL on error + */ +extern void *cvmx_bootmem_alloc_named_address(uint64_t size, uint64_t address, + char *name); + + + +/** + * Allocate a block of memory from a specific range of the free list + * that was passed to the application by the bootloader, and assign it + * a name in the global named block table. (part of the + * cvmx_bootmem_descriptor_t structure) Named blocks can later be + * freed. If request cannot be satisfied within the address range + * specified, NULL is returned + * + * @size: Size in bytes of block to allocate + * @min_addr: minimum address of range + * @max_addr: maximum address of range + * @align: Alignment of memory to be allocated. (must be a power of 2) + * @name: name of block - must be less than CVMX_BOOTMEM_NAME_LEN bytes + * + * Returns a pointer to block of memory, NULL on error + */ +extern void *cvmx_bootmem_alloc_named_range(uint64_t size, uint64_t min_addr, + uint64_t max_addr, uint64_t align, + char *name); + extern int cvmx_bootmem_free_named(char *name); /** @@ -224,6 +282,33 @@ int64_t cvmx_bootmem_phy_alloc(uint64_t req_size, uint64_t address_min, uint32_t flags); /** + * Allocates a named block of physical memory from the free list, at + * (optional) requested address and alignment. + * + * @param size size of region to allocate. All requests are rounded + * up to be a multiple CVMX_BOOTMEM_ALIGNMENT_SIZE + * bytes size + * @param min_addr Minimum address that block can occupy. + * @param max_addr Specifies the maximum address_min (inclusive) that + * the allocation can use. + * @param alignment Requested alignment of the block. If this + * alignment cannot be met, the allocation fails. + * This must be a power of 2. (Note: Alignment of + * CVMX_BOOTMEM_ALIGNMENT_SIZE bytes is required, and + * internally enforced. Requested alignments of less + * than CVMX_BOOTMEM_ALIGNMENT_SIZE are set to + * CVMX_BOOTMEM_ALIGNMENT_SIZE.) + * @param name name to assign to named block + * @param flags Flags to control options for the allocation. + * + * @return physical address of block allocated, or -1 on failure + */ +int64_t cvmx_bootmem_phy_named_block_alloc(uint64_t size, uint64_t min_addr, + uint64_t max_addr, + uint64_t alignment, + char *name, uint32_t flags); + +/** * Finds a named memory block by name. * Also used for finding an unused entry in the named block table. * -- 1.6.0.6 From David.Daney@caviumnetworks.com Wed May 6 01:36:50 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 06 May 2009 01:36:57 +0100 (BST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:16891 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20021310AbZEFAg1 (ORCPT ); Wed, 6 May 2009 01:36:27 +0100 Received: from exch4.caveonetworks.com (Not Verified[192.168.16.23]) by mail3.caviumnetworks.com with MailMarshal (v6,2,2,3503) id ; Tue, 05 May 2009 20:36:16 -0400 Received: from exch4.caveonetworks.com ([192.168.16.23]) by exch4.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Tue, 5 May 2009 17:35:29 -0700 Received: from dd1.caveonetworks.com ([64.169.86.201]) by exch4.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Tue, 5 May 2009 17:35:28 -0700 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.2/8.14.2) with ESMTP id n460ZPrQ022767; Tue, 5 May 2009 17:35:25 -0700 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.2/8.14.2/Submit) id n460ZPEr022766; Tue, 5 May 2009 17:35:25 -0700 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org, gregkh@suse.de Cc: David Daney Subject: [PATCH 4/7] MIPS: Cavium-Octeon: Add more chip specific feature tests. Date: Tue, 5 May 2009 17:35:19 -0700 Message-Id: <1241570122-22728-4-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.6.0.6 In-Reply-To: <4A00DA84.5040101@caviumnetworks.com> References: <4A00DA84.5040101@caviumnetworks.com> X-OriginalArrivalTime: 06 May 2009 00:35:28.0909 (UTC) FILETIME=[8E37BBD0:01C9CDE2] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22630 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Content-Length: 1923 Lines: 56 The octeon-ethernet driver needs to check for additional chip specific features, we add them to the octeon_has_feature() framework. Signed-off-by: David Daney --- arch/mips/include/asm/octeon/octeon-feature.h | 27 +++++++++++++++++++++++++ 1 files changed, 27 insertions(+), 0 deletions(-) diff --git a/arch/mips/include/asm/octeon/octeon-feature.h b/arch/mips/include/asm/octeon/octeon-feature.h index 04fac68..ef24a7b 100644 --- a/arch/mips/include/asm/octeon/octeon-feature.h +++ b/arch/mips/include/asm/octeon/octeon-feature.h @@ -57,6 +57,13 @@ enum octeon_feature { OCTEON_FEATURE_RAID, /* Octeon has a builtin USB */ OCTEON_FEATURE_USB, + /* Octeon IPD can run without using work queue entries */ + OCTEON_FEATURE_NO_WPTR, + /* Octeon has DFA state machines */ + OCTEON_FEATURE_DFA, + /* Octeon MDIO block supports clause 45 transactions for 10 + * Gig support */ + OCTEON_FEATURE_MDIO_CLAUSE_45, }; static inline int cvmx_fuse_read(int fuse); @@ -112,6 +119,26 @@ static inline int octeon_has_feature(enum octeon_feature feature) case OCTEON_FEATURE_USB: return !(OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)); + case OCTEON_FEATURE_NO_WPTR: + return (OCTEON_IS_MODEL(OCTEON_CN56XX) + || OCTEON_IS_MODEL(OCTEON_CN52XX)) + && !OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X) + && !OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X); + case OCTEON_FEATURE_DFA: + if (!OCTEON_IS_MODEL(OCTEON_CN38XX) + && !OCTEON_IS_MODEL(OCTEON_CN31XX) + && !OCTEON_IS_MODEL(OCTEON_CN58XX)) + return 0; + else if (OCTEON_IS_MODEL(OCTEON_CN3020)) + return 0; + else if (OCTEON_IS_MODEL(OCTEON_CN38XX_PASS1)) + return 1; + else + return !cvmx_fuse_read(120); + case OCTEON_FEATURE_MDIO_CLAUSE_45: + return !(OCTEON_IS_MODEL(OCTEON_CN3XXX) + || OCTEON_IS_MODEL(OCTEON_CN58XX) + || OCTEON_IS_MODEL(OCTEON_CN50XX)); } return 0; } -- 1.6.0.6 From David.Daney@caviumnetworks.com Wed May 6 01:37:14 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 06 May 2009 01:37:21 +0100 (BST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:16893 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20021329AbZEFAg1 (ORCPT ); Wed, 6 May 2009 01:36:27 +0100 Received: from exch4.caveonetworks.com (Not Verified[192.168.16.23]) by mail3.caviumnetworks.com with MailMarshal (v6,2,2,3503) id ; Tue, 05 May 2009 20:36:16 -0400 Received: from exch4.caveonetworks.com ([192.168.16.23]) by exch4.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Tue, 5 May 2009 17:35:31 -0700 Received: from dd1.caveonetworks.com ([64.169.86.201]) by exch4.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Tue, 5 May 2009 17:35:31 -0700 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.2/8.14.2) with ESMTP id n460ZQ6q022779; Tue, 5 May 2009 17:35:26 -0700 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.2/8.14.2/Submit) id n460ZQW2022778; Tue, 5 May 2009 17:35:26 -0700 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org, gregkh@suse.de Cc: David Daney Subject: [PATCH 7/7] [Staging] Hookup octeon-ethernet driver. Date: Tue, 5 May 2009 17:35:22 -0700 Message-Id: <1241570122-22728-7-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.6.0.6 In-Reply-To: <4A00DA84.5040101@caviumnetworks.com> References: <4A00DA84.5040101@caviumnetworks.com> X-OriginalArrivalTime: 06 May 2009 00:35:31.0237 (UTC) FILETIME=[8F9AF550:01C9CDE2] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22631 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Content-Length: 1040 Lines: 33 The previous patch adds the driver files for octeon-ethernet. Here we hook them up into the main kernel build system. Signed-off-by: David Daney --- drivers/staging/Kconfig | 2 ++ drivers/staging/Makefile | 1 + 2 files changed, 3 insertions(+), 0 deletions(-) diff --git a/drivers/staging/Kconfig b/drivers/staging/Kconfig index 0dcf9ca..6c2ca23 100644 --- a/drivers/staging/Kconfig +++ b/drivers/staging/Kconfig @@ -115,5 +115,7 @@ source "drivers/staging/line6/Kconfig" source "drivers/staging/serqt_usb/Kconfig" +source "drivers/staging/octeon/Kconfig" + endif # !STAGING_EXCLUDE_BUILD endif # STAGING diff --git a/drivers/staging/Makefile b/drivers/staging/Makefile index 47dfd5b..6da9c74 100644 --- a/drivers/staging/Makefile +++ b/drivers/staging/Makefile @@ -40,3 +40,4 @@ obj-$(CONFIG_PLAN9AUTH) += p9auth/ obj-$(CONFIG_HECI) += heci/ obj-$(CONFIG_LINE6_USB) += line6/ obj-$(CONFIG_USB_SERIAL_QUATECH_ESU100) += serqt_usb/ +obj-$(CONFIG_OCTEON_ETHERNET) += octeon/ -- 1.6.0.6 From David.Daney@caviumnetworks.com Wed May 6 01:37:38 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 06 May 2009 01:37:45 +0100 (BST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:16970 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20021374AbZEFAge (ORCPT ); Wed, 6 May 2009 01:36:34 +0100 Received: from exch4.caveonetworks.com (Not Verified[192.168.16.23]) by mail3.caviumnetworks.com with MailMarshal (v6,2,2,3503) id ; Tue, 05 May 2009 20:36:16 -0400 Received: from exch4.caveonetworks.com ([192.168.16.23]) by exch4.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Tue, 5 May 2009 17:35:29 -0700 Received: from dd1.caveonetworks.com ([64.169.86.201]) by exch4.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Tue, 5 May 2009 17:35:28 -0700 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.2/8.14.2) with ESMTP id n460ZOGn022759; Tue, 5 May 2009 17:35:24 -0700 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.2/8.14.2/Submit) id n460ZOnr022758; Tue, 5 May 2009 17:35:24 -0700 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org, gregkh@suse.de Cc: David Daney Subject: [PATCH 2/7] MIPS: Export cvmx_sysinfo_get needed by octeon-ethernet driver. Date: Tue, 5 May 2009 17:35:17 -0700 Message-Id: <1241570122-22728-2-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.6.0.6 In-Reply-To: <4A00DA84.5040101@caviumnetworks.com> References: <4A00DA84.5040101@caviumnetworks.com> X-OriginalArrivalTime: 06 May 2009 00:35:28.0893 (UTC) FILETIME=[8E354AD0:01C9CDE2] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22632 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Content-Length: 859 Lines: 28 Signed-off-by: David Daney --- arch/mips/cavium-octeon/executive/cvmx-sysinfo.c | 2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/arch/mips/cavium-octeon/executive/cvmx-sysinfo.c b/arch/mips/cavium-octeon/executive/cvmx-sysinfo.c index 4812370..e583889 100644 --- a/arch/mips/cavium-octeon/executive/cvmx-sysinfo.c +++ b/arch/mips/cavium-octeon/executive/cvmx-sysinfo.c @@ -29,6 +29,7 @@ * This module provides system/board/application information obtained * by the bootloader. */ +#include #include #include @@ -69,6 +70,7 @@ struct cvmx_sysinfo *cvmx_sysinfo_get(void) { return &(state.sysinfo); } +EXPORT_SYMBOL(cvmx_sysinfo_get); /** * This function is used in non-simple executive environments (such as -- 1.6.0.6 From David.Daney@caviumnetworks.com Wed May 6 01:38:02 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 06 May 2009 01:38:09 +0100 (BST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:16979 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20021485AbZEFAgf (ORCPT ); Wed, 6 May 2009 01:36:35 +0100 Received: from exch4.caveonetworks.com (Not Verified[192.168.16.23]) by mail3.caviumnetworks.com with MailMarshal (v6,2,2,3503) id ; Tue, 05 May 2009 20:36:16 -0400 Received: from exch4.caveonetworks.com ([192.168.16.23]) by exch4.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Tue, 5 May 2009 17:35:29 -0700 Received: from dd1.caveonetworks.com ([64.169.86.201]) by exch4.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Tue, 5 May 2009 17:35:28 -0700 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.2/8.14.2) with ESMTP id n460ZPLf022771; Tue, 5 May 2009 17:35:25 -0700 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.2/8.14.2/Submit) id n460ZP7o022770; Tue, 5 May 2009 17:35:25 -0700 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org, gregkh@suse.de Cc: David Daney Subject: [PATCH 5/7] MIPS: Export erratum function needed by octeon-ethernet driver. Date: Tue, 5 May 2009 17:35:20 -0700 Message-Id: <1241570122-22728-5-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.6.0.6 In-Reply-To: <4A00DA84.5040101@caviumnetworks.com> References: <4A00DA84.5040101@caviumnetworks.com> X-OriginalArrivalTime: 06 May 2009 00:35:28.0893 (UTC) FILETIME=[8E354AD0:01C9CDE2] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22633 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Content-Length: 811 Lines: 26 Signed-off-by: David Daney --- .../cavium-octeon/executive/cvmx-helper-errata.c | 3 +++ 1 files changed, 3 insertions(+), 0 deletions(-) diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper-errata.c b/arch/mips/cavium-octeon/executive/cvmx-helper-errata.c index 8fb8205..868659e 100644 --- a/arch/mips/cavium-octeon/executive/cvmx-helper-errata.c +++ b/arch/mips/cavium-octeon/executive/cvmx-helper-errata.c @@ -33,6 +33,8 @@ * these functions directly. * */ +#include + #include #include @@ -68,3 +70,4 @@ void __cvmx_helper_errata_qlm_disable_2nd_order_cdr(int qlm) } cvmx_helper_qlm_jtag_update(qlm); } +EXPORT_SYMBOL(__cvmx_helper_errata_qlm_disable_2nd_order_cdr); -- 1.6.0.6 From David.Daney@caviumnetworks.com Wed May 6 01:38:26 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 06 May 2009 01:38:33 +0100 (BST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:16977 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20021551AbZEFAgf (ORCPT ); Wed, 6 May 2009 01:36:35 +0100 Received: from exch4.caveonetworks.com (Not Verified[192.168.16.23]) by mail3.caviumnetworks.com with MailMarshal (v6,2,2,3503) id ; Tue, 05 May 2009 20:36:16 -0400 Received: from exch4.caveonetworks.com ([192.168.16.23]) by exch4.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Tue, 5 May 2009 17:35:29 -0700 Received: from dd1.caveonetworks.com ([64.169.86.201]) by exch4.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Tue, 5 May 2009 17:35:28 -0700 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.2/8.14.2) with ESMTP id n460ZPdH022763; Tue, 5 May 2009 17:35:25 -0700 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.2/8.14.2/Submit) id n460ZPLD022762; Tue, 5 May 2009 17:35:25 -0700 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org, gregkh@suse.de Cc: David Daney Subject: [PATCH 3/7] MIPS: Cavium-Octeon: Add more board type constants. Date: Tue, 5 May 2009 17:35:18 -0700 Message-Id: <1241570122-22728-3-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.6.0.6 In-Reply-To: <4A00DA84.5040101@caviumnetworks.com> References: <4A00DA84.5040101@caviumnetworks.com> X-OriginalArrivalTime: 06 May 2009 00:35:28.0893 (UTC) FILETIME=[8E354AD0:01C9CDE2] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22634 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Content-Length: 1558 Lines: 42 The bootloader now uses additional board type constants. The octeon-ethernet driver needs some of the new values. Signed-off-by: David Daney --- arch/mips/include/asm/octeon/cvmx-bootinfo.h | 13 +++++++++++++ 1 files changed, 13 insertions(+), 0 deletions(-) diff --git a/arch/mips/include/asm/octeon/cvmx-bootinfo.h b/arch/mips/include/asm/octeon/cvmx-bootinfo.h index 692989a..f3c23a4 100644 --- a/arch/mips/include/asm/octeon/cvmx-bootinfo.h +++ b/arch/mips/include/asm/octeon/cvmx-bootinfo.h @@ -157,6 +157,13 @@ enum cvmx_board_types_enum { CVMX_BOARD_TYPE_NIC_XLE_4G = 21, CVMX_BOARD_TYPE_EBT5600 = 22, CVMX_BOARD_TYPE_EBH5201 = 23, + CVMX_BOARD_TYPE_EBT5200 = 24, + CVMX_BOARD_TYPE_CB5600 = 25, + CVMX_BOARD_TYPE_CB5601 = 26, + CVMX_BOARD_TYPE_CB5200 = 27, + /* Special 'generic' board type, supports many boards */ + CVMX_BOARD_TYPE_GENERIC = 28, + CVMX_BOARD_TYPE_EBH5610 = 29, CVMX_BOARD_TYPE_MAX, /* @@ -228,6 +235,12 @@ static inline const char *cvmx_board_type_to_string(enum ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_NIC_XLE_4G) ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBT5600) ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBH5201) + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBT5200) + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CB5600) + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CB5601) + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_CB5200) + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_GENERIC) + ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_EBH5610) ENUM_BRD_TYPE_CASE(CVMX_BOARD_TYPE_MAX) /* Customer boards listed here */ -- 1.6.0.6 From David.Daney@caviumnetworks.com Wed May 6 01:38:50 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 06 May 2009 01:39:15 +0100 (BST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:17251 "EHLO mail3.caviumnetworks.com" rhost-flags-OK-OK-OK-OK) by ftp.linux-mips.org with ESMTP id S20021601AbZEFAhe (ORCPT ); Wed, 6 May 2009 01:37:34 +0100 Received: from exch4.caveonetworks.com (Not Verified[192.168.16.23]) by mail3.caviumnetworks.com with MailMarshal (v6,2,2,3503) id ; Tue, 05 May 2009 20:36:16 -0400 Received: from exch4.caveonetworks.com ([192.168.16.23]) by exch4.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Tue, 5 May 2009 17:35:29 -0700 Received: from dd1.caveonetworks.com ([64.169.86.201]) by exch4.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Tue, 5 May 2009 17:35:28 -0700 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.2/8.14.2) with ESMTP id n460ZQVG022775; Tue, 5 May 2009 17:35:26 -0700 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.2/8.14.2/Submit) id n460ZQM6022774; Tue, 5 May 2009 17:35:26 -0700 From: David Daney To: linux-mips@linux-mips.org, ralf@linux-mips.org, gregkh@suse.de Cc: David Daney Subject: [PATCH 6/7] [Staging] Add octeon-ethernet driver files. Date: Tue, 5 May 2009 17:35:21 -0700 Message-Id: <1241570122-22728-6-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.6.0.6 In-Reply-To: <4A00DA84.5040101@caviumnetworks.com> References: <4A00DA84.5040101@caviumnetworks.com> X-OriginalArrivalTime: 06 May 2009 00:35:28.0893 (UTC) FILETIME=[8E354AD0:01C9CDE2] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22635 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Content-Length: 852342 Lines: 26758 The octeon-ethernet driver supports the sgmii, rgmii, spi, and xaui ports present on the Cavium OCTEON family of SOCs. These SOCs are multi-core mips64 processors with existing support over in arch/mips. The driver files can be categorized into three basic groups: 1) Register definitions, these are named cvmx-*-defs.h 2) Main driver code, these have names that don't start cvmx-. 3) Interface specific functions and other utility code, names starting with cvmx- Signed-off-by: David Daney --- drivers/staging/octeon/Kconfig | 12 + drivers/staging/octeon/Makefile | 30 + drivers/staging/octeon/cvmx-address.h | 274 +++ drivers/staging/octeon/cvmx-asxx-defs.h | 475 +++++ drivers/staging/octeon/cvmx-cmd-queue.c | 306 +++ drivers/staging/octeon/cvmx-cmd-queue.h | 617 ++++++ drivers/staging/octeon/cvmx-config.h | 169 ++ drivers/staging/octeon/cvmx-dbg-defs.h | 72 + drivers/staging/octeon/cvmx-fau.h | 597 ++++++ drivers/staging/octeon/cvmx-fpa-defs.h | 403 ++++ drivers/staging/octeon/cvmx-fpa.c | 183 ++ drivers/staging/octeon/cvmx-fpa.h | 299 +++ drivers/staging/octeon/cvmx-gmxx-defs.h | 2529 +++++++++++++++++++++++ drivers/staging/octeon/cvmx-helper-board.c | 706 +++++++ drivers/staging/octeon/cvmx-helper-board.h | 180 ++ drivers/staging/octeon/cvmx-helper-fpa.c | 243 +++ drivers/staging/octeon/cvmx-helper-fpa.h | 64 + drivers/staging/octeon/cvmx-helper-loop.c | 85 + drivers/staging/octeon/cvmx-helper-loop.h | 59 + drivers/staging/octeon/cvmx-helper-npi.c | 113 + drivers/staging/octeon/cvmx-helper-npi.h | 60 + drivers/staging/octeon/cvmx-helper-rgmii.c | 525 +++++ drivers/staging/octeon/cvmx-helper-rgmii.h | 110 + drivers/staging/octeon/cvmx-helper-sgmii.c | 550 +++++ drivers/staging/octeon/cvmx-helper-sgmii.h | 104 + drivers/staging/octeon/cvmx-helper-spi.c | 195 ++ drivers/staging/octeon/cvmx-helper-spi.h | 84 + drivers/staging/octeon/cvmx-helper-util.c | 433 ++++ drivers/staging/octeon/cvmx-helper-util.h | 215 ++ drivers/staging/octeon/cvmx-helper-xaui.c | 348 ++++ drivers/staging/octeon/cvmx-helper-xaui.h | 103 + drivers/staging/octeon/cvmx-helper.c | 1058 ++++++++++ drivers/staging/octeon/cvmx-helper.h | 227 ++ drivers/staging/octeon/cvmx-interrupt-decodes.c | 371 ++++ drivers/staging/octeon/cvmx-interrupt-rsl.c | 140 ++ drivers/staging/octeon/cvmx-ipd.h | 338 +++ drivers/staging/octeon/cvmx-mdio.h | 506 +++++ drivers/staging/octeon/cvmx-packet.h | 65 + drivers/staging/octeon/cvmx-pcsx-defs.h | 370 ++++ drivers/staging/octeon/cvmx-pcsxx-defs.h | 316 +++ drivers/staging/octeon/cvmx-pip-defs.h | 1267 ++++++++++++ drivers/staging/octeon/cvmx-pip.h | 524 +++++ drivers/staging/octeon/cvmx-pko-defs.h | 1133 ++++++++++ drivers/staging/octeon/cvmx-pko.c | 506 +++++ drivers/staging/octeon/cvmx-pko.h | 610 ++++++ drivers/staging/octeon/cvmx-pow.h | 1982 ++++++++++++++++++ drivers/staging/octeon/cvmx-scratch.h | 139 ++ drivers/staging/octeon/cvmx-smix-defs.h | 178 ++ drivers/staging/octeon/cvmx-spi.c | 667 ++++++ drivers/staging/octeon/cvmx-spi.h | 269 +++ drivers/staging/octeon/cvmx-spxx-defs.h | 347 ++++ drivers/staging/octeon/cvmx-srxx-defs.h | 126 ++ drivers/staging/octeon/cvmx-stxx-defs.h | 292 +++ drivers/staging/octeon/cvmx-wqe.h | 397 ++++ drivers/staging/octeon/ethernet-common.c | 328 +++ drivers/staging/octeon/ethernet-common.h | 29 + drivers/staging/octeon/ethernet-defines.h | 134 ++ drivers/staging/octeon/ethernet-mdio.c | 231 +++ drivers/staging/octeon/ethernet-mdio.h | 46 + drivers/staging/octeon/ethernet-mem.c | 198 ++ drivers/staging/octeon/ethernet-mem.h | 29 + drivers/staging/octeon/ethernet-proc.c | 256 +++ drivers/staging/octeon/ethernet-proc.h | 29 + drivers/staging/octeon/ethernet-rgmii.c | 397 ++++ drivers/staging/octeon/ethernet-rx.c | 505 +++++ drivers/staging/octeon/ethernet-rx.h | 33 + drivers/staging/octeon/ethernet-sgmii.c | 129 ++ drivers/staging/octeon/ethernet-spi.c | 323 +++ drivers/staging/octeon/ethernet-tx.c | 634 ++++++ drivers/staging/octeon/ethernet-tx.h | 32 + drivers/staging/octeon/ethernet-util.h | 81 + drivers/staging/octeon/ethernet-xaui.c | 127 ++ drivers/staging/octeon/ethernet.c | 507 +++++ drivers/staging/octeon/octeon-ethernet.h | 127 ++ 74 files changed, 26146 insertions(+), 0 deletions(-) create mode 100644 drivers/staging/octeon/Kconfig create mode 100644 drivers/staging/octeon/Makefile create mode 100644 drivers/staging/octeon/cvmx-address.h create mode 100644 drivers/staging/octeon/cvmx-asxx-defs.h create mode 100644 drivers/staging/octeon/cvmx-cmd-queue.c create mode 100644 drivers/staging/octeon/cvmx-cmd-queue.h create mode 100644 drivers/staging/octeon/cvmx-config.h create mode 100644 drivers/staging/octeon/cvmx-dbg-defs.h create mode 100644 drivers/staging/octeon/cvmx-fau.h create mode 100644 drivers/staging/octeon/cvmx-fpa-defs.h create mode 100644 drivers/staging/octeon/cvmx-fpa.c create mode 100644 drivers/staging/octeon/cvmx-fpa.h create mode 100644 drivers/staging/octeon/cvmx-gmxx-defs.h create mode 100644 drivers/staging/octeon/cvmx-helper-board.c create mode 100644 drivers/staging/octeon/cvmx-helper-board.h create mode 100644 drivers/staging/octeon/cvmx-helper-fpa.c create mode 100644 drivers/staging/octeon/cvmx-helper-fpa.h create mode 100644 drivers/staging/octeon/cvmx-helper-loop.c create mode 100644 drivers/staging/octeon/cvmx-helper-loop.h create mode 100644 drivers/staging/octeon/cvmx-helper-npi.c create mode 100644 drivers/staging/octeon/cvmx-helper-npi.h create mode 100644 drivers/staging/octeon/cvmx-helper-rgmii.c create mode 100644 drivers/staging/octeon/cvmx-helper-rgmii.h create mode 100644 drivers/staging/octeon/cvmx-helper-sgmii.c create mode 100644 drivers/staging/octeon/cvmx-helper-sgmii.h create mode 100644 drivers/staging/octeon/cvmx-helper-spi.c create mode 100644 drivers/staging/octeon/cvmx-helper-spi.h create mode 100644 drivers/staging/octeon/cvmx-helper-util.c create mode 100644 drivers/staging/octeon/cvmx-helper-util.h create mode 100644 drivers/staging/octeon/cvmx-helper-xaui.c create mode 100644 drivers/staging/octeon/cvmx-helper-xaui.h create mode 100644 drivers/staging/octeon/cvmx-helper.c create mode 100644 drivers/staging/octeon/cvmx-helper.h create mode 100644 drivers/staging/octeon/cvmx-interrupt-decodes.c create mode 100644 drivers/staging/octeon/cvmx-interrupt-rsl.c create mode 100644 drivers/staging/octeon/cvmx-ipd.h create mode 100644 drivers/staging/octeon/cvmx-mdio.h create mode 100644 drivers/staging/octeon/cvmx-packet.h create mode 100644 drivers/staging/octeon/cvmx-pcsx-defs.h create mode 100644 drivers/staging/octeon/cvmx-pcsxx-defs.h create mode 100644 drivers/staging/octeon/cvmx-pip-defs.h create mode 100644 drivers/staging/octeon/cvmx-pip.h create mode 100644 drivers/staging/octeon/cvmx-pko-defs.h create mode 100644 drivers/staging/octeon/cvmx-pko.c create mode 100644 drivers/staging/octeon/cvmx-pko.h create mode 100644 drivers/staging/octeon/cvmx-pow.h create mode 100644 drivers/staging/octeon/cvmx-scratch.h create mode 100644 drivers/staging/octeon/cvmx-smix-defs.h create mode 100644 drivers/staging/octeon/cvmx-spi.c create mode 100644 drivers/staging/octeon/cvmx-spi.h create mode 100644 drivers/staging/octeon/cvmx-spxx-defs.h create mode 100644 drivers/staging/octeon/cvmx-srxx-defs.h create mode 100644 drivers/staging/octeon/cvmx-stxx-defs.h create mode 100644 drivers/staging/octeon/cvmx-wqe.h create mode 100644 drivers/staging/octeon/ethernet-common.c create mode 100644 drivers/staging/octeon/ethernet-common.h create mode 100644 drivers/staging/octeon/ethernet-defines.h create mode 100644 drivers/staging/octeon/ethernet-mdio.c create mode 100644 drivers/staging/octeon/ethernet-mdio.h create mode 100644 drivers/staging/octeon/ethernet-mem.c create mode 100644 drivers/staging/octeon/ethernet-mem.h create mode 100644 drivers/staging/octeon/ethernet-proc.c create mode 100644 drivers/staging/octeon/ethernet-proc.h create mode 100644 drivers/staging/octeon/ethernet-rgmii.c create mode 100644 drivers/staging/octeon/ethernet-rx.c create mode 100644 drivers/staging/octeon/ethernet-rx.h create mode 100644 drivers/staging/octeon/ethernet-sgmii.c create mode 100644 drivers/staging/octeon/ethernet-spi.c create mode 100644 drivers/staging/octeon/ethernet-tx.c create mode 100644 drivers/staging/octeon/ethernet-tx.h create mode 100644 drivers/staging/octeon/ethernet-util.h create mode 100644 drivers/staging/octeon/ethernet-xaui.c create mode 100644 drivers/staging/octeon/ethernet.c create mode 100644 drivers/staging/octeon/octeon-ethernet.h diff --git a/drivers/staging/octeon/Kconfig b/drivers/staging/octeon/Kconfig new file mode 100644 index 0000000..536e238 --- /dev/null +++ b/drivers/staging/octeon/Kconfig @@ -0,0 +1,12 @@ +config OCTEON_ETHERNET + tristate "Cavium Networks Octeon Ethernet support" + depends on CPU_CAVIUM_OCTEON + select MII + help + This driver supports the builtin ethernet ports on Cavium + Networks' products in the Octeon family. This driver supports the + CN3XXX and CN5XXX Octeon processors. + + To compile this driver as a module, choose M here. The module + will be called octeon-ethernet. + diff --git a/drivers/staging/octeon/Makefile b/drivers/staging/octeon/Makefile new file mode 100644 index 0000000..3c839e3 --- /dev/null +++ b/drivers/staging/octeon/Makefile @@ -0,0 +1,30 @@ +# This file is subject to the terms and conditions of the GNU General Public +# License. See the file "COPYING" in the main directory of this archive +# for more details. +# +# Copyright (C) 2005-2009 Cavium Networks +# + +# +# Makefile for Cavium OCTEON on-board ethernet driver +# + +obj-${CONFIG_OCTEON_ETHERNET} := octeon-ethernet.o + +octeon-ethernet-objs := ethernet.o +octeon-ethernet-objs += ethernet-common.o +octeon-ethernet-objs += ethernet-mdio.o +octeon-ethernet-objs += ethernet-mem.o +octeon-ethernet-objs += ethernet-proc.o +octeon-ethernet-objs += ethernet-rgmii.o +octeon-ethernet-objs += ethernet-rx.o +octeon-ethernet-objs += ethernet-sgmii.o +octeon-ethernet-objs += ethernet-spi.o +octeon-ethernet-objs += ethernet-tx.o +octeon-ethernet-objs += ethernet-xaui.o +octeon-ethernet-objs += cvmx-pko.o cvmx-spi.o cvmx-cmd-queue.o \ + cvmx-helper-board.o cvmx-helper.o cvmx-helper-xaui.o \ + cvmx-helper-rgmii.o cvmx-helper-sgmii.o cvmx-helper-npi.o \ + cvmx-helper-loop.o cvmx-helper-spi.o cvmx-helper-util.o \ + cvmx-interrupt-decodes.o cvmx-interrupt-rsl.o + diff --git a/drivers/staging/octeon/cvmx-address.h b/drivers/staging/octeon/cvmx-address.h new file mode 100644 index 0000000..3c74d82 --- /dev/null +++ b/drivers/staging/octeon/cvmx-address.h @@ -0,0 +1,274 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2009 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * along with this file; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +/** + * Typedefs and defines for working with Octeon physical addresses. + * + */ +#ifndef __CVMX_ADDRESS_H__ +#define __CVMX_ADDRESS_H__ + +#if 0 +typedef enum { + CVMX_MIPS_SPACE_XKSEG = 3LL, + CVMX_MIPS_SPACE_XKPHYS = 2LL, + CVMX_MIPS_SPACE_XSSEG = 1LL, + CVMX_MIPS_SPACE_XUSEG = 0LL +} cvmx_mips_space_t; +#endif + +typedef enum { + CVMX_MIPS_XKSEG_SPACE_KSEG0 = 0LL, + CVMX_MIPS_XKSEG_SPACE_KSEG1 = 1LL, + CVMX_MIPS_XKSEG_SPACE_SSEG = 2LL, + CVMX_MIPS_XKSEG_SPACE_KSEG3 = 3LL +} cvmx_mips_xkseg_space_t; + +/* decodes <14:13> of a kseg3 window address */ +typedef enum { + CVMX_ADD_WIN_SCR = 0L, + /* see cvmx_add_win_dma_dec_t for further decode */ + CVMX_ADD_WIN_DMA = 1L, + CVMX_ADD_WIN_UNUSED = 2L, + CVMX_ADD_WIN_UNUSED2 = 3L +} cvmx_add_win_dec_t; + +/* decode within DMA space */ +typedef enum { + /* + * Add store data to the write buffer entry, allocating it if + * necessary. + */ + CVMX_ADD_WIN_DMA_ADD = 0L, + /* send out the write buffer entry to DRAM */ + CVMX_ADD_WIN_DMA_SENDMEM = 1L, + /* store data must be normal DRAM memory space address in this case */ + /* send out the write buffer entry as an IOBDMA command */ + CVMX_ADD_WIN_DMA_SENDDMA = 2L, + /* see CVMX_ADD_WIN_DMA_SEND_DEC for data contents */ + /* send out the write buffer entry as an IO write */ + CVMX_ADD_WIN_DMA_SENDIO = 3L, + /* store data must be normal IO space address in this case */ + /* send out a single-tick command on the NCB bus */ + CVMX_ADD_WIN_DMA_SENDSINGLE = 4L, + /* no write buffer data needed/used */ +} cvmx_add_win_dma_dec_t; + +/* + * Physical Address Decode + * + * Octeon-I HW never interprets this X (<39:36> reserved + * for future expansion), software should set to 0. + * + * - 0x0 XXX0 0000 0000 to DRAM Cached + * - 0x0 XXX0 0FFF FFFF + * + * - 0x0 XXX0 1000 0000 to Boot Bus Uncached (Converted to 0x1 00X0 1000 0000 + * - 0x0 XXX0 1FFF FFFF + EJTAG to 0x1 00X0 1FFF FFFF) + * + * - 0x0 XXX0 2000 0000 to DRAM Cached + * - 0x0 XXXF FFFF FFFF + * + * - 0x1 00X0 0000 0000 to Boot Bus Uncached + * - 0x1 00XF FFFF FFFF + * + * - 0x1 01X0 0000 0000 to Other NCB Uncached + * - 0x1 FFXF FFFF FFFF devices + * + * Decode of all Octeon addresses + */ +typedef union { + + uint64_t u64; + /* mapped or unmapped virtual address */ + struct { + uint64_t R:2; + uint64_t offset:62; + } sva; + + /* mapped USEG virtual addresses (typically) */ + struct { + uint64_t zeroes:33; + uint64_t offset:31; + } suseg; + + /* mapped or unmapped virtual address */ + struct { + uint64_t ones:33; + uint64_t sp:2; + uint64_t offset:29; + } sxkseg; + + /* + * physical address accessed through xkphys unmapped virtual + * address. + */ + struct { + uint64_t R:2; /* CVMX_MIPS_SPACE_XKPHYS in this case */ + uint64_t cca:3; /* ignored by octeon */ + uint64_t mbz:10; + uint64_t pa:49; /* physical address */ + } sxkphys; + + /* physical address */ + struct { + uint64_t mbz:15; + /* if set, the address is uncached and resides on MCB bus */ + uint64_t is_io:1; + /* + * the hardware ignores this field when is_io==0, else + * device ID. + */ + uint64_t did:8; + /* the hardware ignores <39:36> in Octeon I */ + uint64_t unaddr:4; + uint64_t offset:36; + } sphys; + + /* physical mem address */ + struct { + /* techically, <47:40> are dont-cares */ + uint64_t zeroes:24; + /* the hardware ignores <39:36> in Octeon I */ + uint64_t unaddr:4; + uint64_t offset:36; + } smem; + + /* physical IO address */ + struct { + uint64_t mem_region:2; + uint64_t mbz:13; + /* 1 in this case */ + uint64_t is_io:1; + /* + * The hardware ignores this field when is_io==0, else + * device ID. + */ + uint64_t did:8; + /* the hardware ignores <39:36> in Octeon I */ + uint64_t unaddr:4; + uint64_t offset:36; + } sio; + + /* + * Scratchpad virtual address - accessed through a window at + * the end of kseg3 + */ + struct { + uint64_t ones:49; + /* CVMX_ADD_WIN_SCR (0) in this case */ + cvmx_add_win_dec_t csrdec:2; + uint64_t addr:13; + } sscr; + + /* there should only be stores to IOBDMA space, no loads */ + /* + * IOBDMA virtual address - accessed through a window at the + * end of kseg3 + */ + struct { + uint64_t ones:49; + uint64_t csrdec:2; /* CVMX_ADD_WIN_DMA (1) in this case */ + uint64_t unused2:3; + uint64_t type:3; + uint64_t addr:7; + } sdma; + + struct { + uint64_t didspace:24; + uint64_t unused:40; + } sfilldidspace; + +} cvmx_addr_t; + +/* These macros for used by 32 bit applications */ + +#define CVMX_MIPS32_SPACE_KSEG0 1l +#define CVMX_ADD_SEG32(segment, add) \ + (((int32_t)segment << 31) | (int32_t)(add)) + +/* + * Currently all IOs are performed using XKPHYS addressing. Linux uses + * the CvmMemCtl register to enable XKPHYS addressing to IO space from + * user mode. Future OSes may need to change the upper bits of IO + * addresses. The following define controls the upper two bits for all + * IO addresses generated by the simple executive library. + */ +#define CVMX_IO_SEG CVMX_MIPS_SPACE_XKPHYS + +/* These macros simplify the process of creating common IO addresses */ +#define CVMX_ADD_SEG(segment, add) ((((uint64_t)segment) << 62) | (add)) +#ifndef CVMX_ADD_IO_SEG +#define CVMX_ADD_IO_SEG(add) CVMX_ADD_SEG(CVMX_IO_SEG, (add)) +#endif +#define CVMX_ADDR_DIDSPACE(did) (((CVMX_IO_SEG) << 22) | ((1ULL) << 8) | (did)) +#define CVMX_ADDR_DID(did) (CVMX_ADDR_DIDSPACE(did) << 40) +#define CVMX_FULL_DID(did, subdid) (((did) << 3) | (subdid)) + + /* from include/ncb_rsl_id.v */ +#define CVMX_OCT_DID_MIS 0ULL /* misc stuff */ +#define CVMX_OCT_DID_GMX0 1ULL +#define CVMX_OCT_DID_GMX1 2ULL +#define CVMX_OCT_DID_PCI 3ULL +#define CVMX_OCT_DID_KEY 4ULL +#define CVMX_OCT_DID_FPA 5ULL +#define CVMX_OCT_DID_DFA 6ULL +#define CVMX_OCT_DID_ZIP 7ULL +#define CVMX_OCT_DID_RNG 8ULL +#define CVMX_OCT_DID_IPD 9ULL +#define CVMX_OCT_DID_PKT 10ULL +#define CVMX_OCT_DID_TIM 11ULL +#define CVMX_OCT_DID_TAG 12ULL + /* the rest are not on the IO bus */ +#define CVMX_OCT_DID_L2C 16ULL +#define CVMX_OCT_DID_LMC 17ULL +#define CVMX_OCT_DID_SPX0 18ULL +#define CVMX_OCT_DID_SPX1 19ULL +#define CVMX_OCT_DID_PIP 20ULL +#define CVMX_OCT_DID_ASX0 22ULL +#define CVMX_OCT_DID_ASX1 23ULL +#define CVMX_OCT_DID_IOB 30ULL + +#define CVMX_OCT_DID_PKT_SEND CVMX_FULL_DID(CVMX_OCT_DID_PKT, 2ULL) +#define CVMX_OCT_DID_TAG_SWTAG CVMX_FULL_DID(CVMX_OCT_DID_TAG, 0ULL) +#define CVMX_OCT_DID_TAG_TAG1 CVMX_FULL_DID(CVMX_OCT_DID_TAG, 1ULL) +#define CVMX_OCT_DID_TAG_TAG2 CVMX_FULL_DID(CVMX_OCT_DID_TAG, 2ULL) +#define CVMX_OCT_DID_TAG_TAG3 CVMX_FULL_DID(CVMX_OCT_DID_TAG, 3ULL) +#define CVMX_OCT_DID_TAG_NULL_RD CVMX_FULL_DID(CVMX_OCT_DID_TAG, 4ULL) +#define CVMX_OCT_DID_TAG_CSR CVMX_FULL_DID(CVMX_OCT_DID_TAG, 7ULL) +#define CVMX_OCT_DID_FAU_FAI CVMX_FULL_DID(CVMX_OCT_DID_IOB, 0ULL) +#define CVMX_OCT_DID_TIM_CSR CVMX_FULL_DID(CVMX_OCT_DID_TIM, 0ULL) +#define CVMX_OCT_DID_KEY_RW CVMX_FULL_DID(CVMX_OCT_DID_KEY, 0ULL) +#define CVMX_OCT_DID_PCI_6 CVMX_FULL_DID(CVMX_OCT_DID_PCI, 6ULL) +#define CVMX_OCT_DID_MIS_BOO CVMX_FULL_DID(CVMX_OCT_DID_MIS, 0ULL) +#define CVMX_OCT_DID_PCI_RML CVMX_FULL_DID(CVMX_OCT_DID_PCI, 0ULL) +#define CVMX_OCT_DID_IPD_CSR CVMX_FULL_DID(CVMX_OCT_DID_IPD, 7ULL) +#define CVMX_OCT_DID_DFA_CSR CVMX_FULL_DID(CVMX_OCT_DID_DFA, 7ULL) +#define CVMX_OCT_DID_MIS_CSR CVMX_FULL_DID(CVMX_OCT_DID_MIS, 7ULL) +#define CVMX_OCT_DID_ZIP_CSR CVMX_FULL_DID(CVMX_OCT_DID_ZIP, 0ULL) + +#endif /* __CVMX_ADDRESS_H__ */ diff --git a/drivers/staging/octeon/cvmx-asxx-defs.h b/drivers/staging/octeon/cvmx-asxx-defs.h new file mode 100644 index 0000000..91415a8 --- /dev/null +++ b/drivers/staging/octeon/cvmx-asxx-defs.h @@ -0,0 +1,475 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * along with this file; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +#ifndef __CVMX_ASXX_DEFS_H__ +#define __CVMX_ASXX_DEFS_H__ + +#define CVMX_ASXX_GMII_RX_CLK_SET(block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0000180ull + (((block_id) & 0) * 0x8000000ull)) +#define CVMX_ASXX_GMII_RX_DAT_SET(block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0000188ull + (((block_id) & 0) * 0x8000000ull)) +#define CVMX_ASXX_INT_EN(block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0000018ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_ASXX_INT_REG(block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0000010ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_ASXX_MII_RX_DAT_SET(block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0000190ull + (((block_id) & 0) * 0x8000000ull)) +#define CVMX_ASXX_PRT_LOOP(block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0000040ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_ASXX_RLD_BYPASS(block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0000248ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_ASXX_RLD_BYPASS_SETTING(block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0000250ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_ASXX_RLD_COMP(block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0000220ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_ASXX_RLD_DATA_DRV(block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0000218ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_ASXX_RLD_FCRAM_MODE(block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0000210ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_ASXX_RLD_NCTL_STRONG(block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0000230ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_ASXX_RLD_NCTL_WEAK(block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0000240ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_ASXX_RLD_PCTL_STRONG(block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0000228ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_ASXX_RLD_PCTL_WEAK(block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0000238ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_ASXX_RLD_SETTING(block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0000258ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_ASXX_RX_CLK_SETX(offset, block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0000020ull + (((offset) & 3) * 8) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_ASXX_RX_PRT_EN(block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0000000ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_ASXX_RX_WOL(block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0000100ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_ASXX_RX_WOL_MSK(block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0000108ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_ASXX_RX_WOL_POWOK(block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0000118ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_ASXX_RX_WOL_SIG(block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0000110ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_ASXX_TX_CLK_SETX(offset, block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0000048ull + (((offset) & 3) * 8) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_ASXX_TX_COMP_BYP(block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0000068ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_ASXX_TX_HI_WATERX(offset, block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0000080ull + (((offset) & 3) * 8) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_ASXX_TX_PRT_EN(block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0000008ull + (((block_id) & 1) * 0x8000000ull)) + +union cvmx_asxx_gmii_rx_clk_set { + uint64_t u64; + struct cvmx_asxx_gmii_rx_clk_set_s { + uint64_t reserved_5_63:59; + uint64_t setting:5; + } s; + struct cvmx_asxx_gmii_rx_clk_set_s cn30xx; + struct cvmx_asxx_gmii_rx_clk_set_s cn31xx; + struct cvmx_asxx_gmii_rx_clk_set_s cn50xx; +}; + +union cvmx_asxx_gmii_rx_dat_set { + uint64_t u64; + struct cvmx_asxx_gmii_rx_dat_set_s { + uint64_t reserved_5_63:59; + uint64_t setting:5; + } s; + struct cvmx_asxx_gmii_rx_dat_set_s cn30xx; + struct cvmx_asxx_gmii_rx_dat_set_s cn31xx; + struct cvmx_asxx_gmii_rx_dat_set_s cn50xx; +}; + +union cvmx_asxx_int_en { + uint64_t u64; + struct cvmx_asxx_int_en_s { + uint64_t reserved_12_63:52; + uint64_t txpsh:4; + uint64_t txpop:4; + uint64_t ovrflw:4; + } s; + struct cvmx_asxx_int_en_cn30xx { + uint64_t reserved_11_63:53; + uint64_t txpsh:3; + uint64_t reserved_7_7:1; + uint64_t txpop:3; + uint64_t reserved_3_3:1; + uint64_t ovrflw:3; + } cn30xx; + struct cvmx_asxx_int_en_cn30xx cn31xx; + struct cvmx_asxx_int_en_s cn38xx; + struct cvmx_asxx_int_en_s cn38xxp2; + struct cvmx_asxx_int_en_cn30xx cn50xx; + struct cvmx_asxx_int_en_s cn58xx; + struct cvmx_asxx_int_en_s cn58xxp1; +}; + +union cvmx_asxx_int_reg { + uint64_t u64; + struct cvmx_asxx_int_reg_s { + uint64_t reserved_12_63:52; + uint64_t txpsh:4; + uint64_t txpop:4; + uint64_t ovrflw:4; + } s; + struct cvmx_asxx_int_reg_cn30xx { + uint64_t reserved_11_63:53; + uint64_t txpsh:3; + uint64_t reserved_7_7:1; + uint64_t txpop:3; + uint64_t reserved_3_3:1; + uint64_t ovrflw:3; + } cn30xx; + struct cvmx_asxx_int_reg_cn30xx cn31xx; + struct cvmx_asxx_int_reg_s cn38xx; + struct cvmx_asxx_int_reg_s cn38xxp2; + struct cvmx_asxx_int_reg_cn30xx cn50xx; + struct cvmx_asxx_int_reg_s cn58xx; + struct cvmx_asxx_int_reg_s cn58xxp1; +}; + +union cvmx_asxx_mii_rx_dat_set { + uint64_t u64; + struct cvmx_asxx_mii_rx_dat_set_s { + uint64_t reserved_5_63:59; + uint64_t setting:5; + } s; + struct cvmx_asxx_mii_rx_dat_set_s cn30xx; + struct cvmx_asxx_mii_rx_dat_set_s cn50xx; +}; + +union cvmx_asxx_prt_loop { + uint64_t u64; + struct cvmx_asxx_prt_loop_s { + uint64_t reserved_8_63:56; + uint64_t ext_loop:4; + uint64_t int_loop:4; + } s; + struct cvmx_asxx_prt_loop_cn30xx { + uint64_t reserved_7_63:57; + uint64_t ext_loop:3; + uint64_t reserved_3_3:1; + uint64_t int_loop:3; + } cn30xx; + struct cvmx_asxx_prt_loop_cn30xx cn31xx; + struct cvmx_asxx_prt_loop_s cn38xx; + struct cvmx_asxx_prt_loop_s cn38xxp2; + struct cvmx_asxx_prt_loop_cn30xx cn50xx; + struct cvmx_asxx_prt_loop_s cn58xx; + struct cvmx_asxx_prt_loop_s cn58xxp1; +}; + +union cvmx_asxx_rld_bypass { + uint64_t u64; + struct cvmx_asxx_rld_bypass_s { + uint64_t reserved_1_63:63; + uint64_t bypass:1; + } s; + struct cvmx_asxx_rld_bypass_s cn38xx; + struct cvmx_asxx_rld_bypass_s cn38xxp2; + struct cvmx_asxx_rld_bypass_s cn58xx; + struct cvmx_asxx_rld_bypass_s cn58xxp1; +}; + +union cvmx_asxx_rld_bypass_setting { + uint64_t u64; + struct cvmx_asxx_rld_bypass_setting_s { + uint64_t reserved_5_63:59; + uint64_t setting:5; + } s; + struct cvmx_asxx_rld_bypass_setting_s cn38xx; + struct cvmx_asxx_rld_bypass_setting_s cn38xxp2; + struct cvmx_asxx_rld_bypass_setting_s cn58xx; + struct cvmx_asxx_rld_bypass_setting_s cn58xxp1; +}; + +union cvmx_asxx_rld_comp { + uint64_t u64; + struct cvmx_asxx_rld_comp_s { + uint64_t reserved_9_63:55; + uint64_t pctl:5; + uint64_t nctl:4; + } s; + struct cvmx_asxx_rld_comp_cn38xx { + uint64_t reserved_8_63:56; + uint64_t pctl:4; + uint64_t nctl:4; + } cn38xx; + struct cvmx_asxx_rld_comp_cn38xx cn38xxp2; + struct cvmx_asxx_rld_comp_s cn58xx; + struct cvmx_asxx_rld_comp_s cn58xxp1; +}; + +union cvmx_asxx_rld_data_drv { + uint64_t u64; + struct cvmx_asxx_rld_data_drv_s { + uint64_t reserved_8_63:56; + uint64_t pctl:4; + uint64_t nctl:4; + } s; + struct cvmx_asxx_rld_data_drv_s cn38xx; + struct cvmx_asxx_rld_data_drv_s cn38xxp2; + struct cvmx_asxx_rld_data_drv_s cn58xx; + struct cvmx_asxx_rld_data_drv_s cn58xxp1; +}; + +union cvmx_asxx_rld_fcram_mode { + uint64_t u64; + struct cvmx_asxx_rld_fcram_mode_s { + uint64_t reserved_1_63:63; + uint64_t mode:1; + } s; + struct cvmx_asxx_rld_fcram_mode_s cn38xx; + struct cvmx_asxx_rld_fcram_mode_s cn38xxp2; +}; + +union cvmx_asxx_rld_nctl_strong { + uint64_t u64; + struct cvmx_asxx_rld_nctl_strong_s { + uint64_t reserved_5_63:59; + uint64_t nctl:5; + } s; + struct cvmx_asxx_rld_nctl_strong_s cn38xx; + struct cvmx_asxx_rld_nctl_strong_s cn38xxp2; + struct cvmx_asxx_rld_nctl_strong_s cn58xx; + struct cvmx_asxx_rld_nctl_strong_s cn58xxp1; +}; + +union cvmx_asxx_rld_nctl_weak { + uint64_t u64; + struct cvmx_asxx_rld_nctl_weak_s { + uint64_t reserved_5_63:59; + uint64_t nctl:5; + } s; + struct cvmx_asxx_rld_nctl_weak_s cn38xx; + struct cvmx_asxx_rld_nctl_weak_s cn38xxp2; + struct cvmx_asxx_rld_nctl_weak_s cn58xx; + struct cvmx_asxx_rld_nctl_weak_s cn58xxp1; +}; + +union cvmx_asxx_rld_pctl_strong { + uint64_t u64; + struct cvmx_asxx_rld_pctl_strong_s { + uint64_t reserved_5_63:59; + uint64_t pctl:5; + } s; + struct cvmx_asxx_rld_pctl_strong_s cn38xx; + struct cvmx_asxx_rld_pctl_strong_s cn38xxp2; + struct cvmx_asxx_rld_pctl_strong_s cn58xx; + struct cvmx_asxx_rld_pctl_strong_s cn58xxp1; +}; + +union cvmx_asxx_rld_pctl_weak { + uint64_t u64; + struct cvmx_asxx_rld_pctl_weak_s { + uint64_t reserved_5_63:59; + uint64_t pctl:5; + } s; + struct cvmx_asxx_rld_pctl_weak_s cn38xx; + struct cvmx_asxx_rld_pctl_weak_s cn38xxp2; + struct cvmx_asxx_rld_pctl_weak_s cn58xx; + struct cvmx_asxx_rld_pctl_weak_s cn58xxp1; +}; + +union cvmx_asxx_rld_setting { + uint64_t u64; + struct cvmx_asxx_rld_setting_s { + uint64_t reserved_13_63:51; + uint64_t dfaset:5; + uint64_t dfalag:1; + uint64_t dfalead:1; + uint64_t dfalock:1; + uint64_t setting:5; + } s; + struct cvmx_asxx_rld_setting_cn38xx { + uint64_t reserved_5_63:59; + uint64_t setting:5; + } cn38xx; + struct cvmx_asxx_rld_setting_cn38xx cn38xxp2; + struct cvmx_asxx_rld_setting_s cn58xx; + struct cvmx_asxx_rld_setting_s cn58xxp1; +}; + +union cvmx_asxx_rx_clk_setx { + uint64_t u64; + struct cvmx_asxx_rx_clk_setx_s { + uint64_t reserved_5_63:59; + uint64_t setting:5; + } s; + struct cvmx_asxx_rx_clk_setx_s cn30xx; + struct cvmx_asxx_rx_clk_setx_s cn31xx; + struct cvmx_asxx_rx_clk_setx_s cn38xx; + struct cvmx_asxx_rx_clk_setx_s cn38xxp2; + struct cvmx_asxx_rx_clk_setx_s cn50xx; + struct cvmx_asxx_rx_clk_setx_s cn58xx; + struct cvmx_asxx_rx_clk_setx_s cn58xxp1; +}; + +union cvmx_asxx_rx_prt_en { + uint64_t u64; + struct cvmx_asxx_rx_prt_en_s { + uint64_t reserved_4_63:60; + uint64_t prt_en:4; + } s; + struct cvmx_asxx_rx_prt_en_cn30xx { + uint64_t reserved_3_63:61; + uint64_t prt_en:3; + } cn30xx; + struct cvmx_asxx_rx_prt_en_cn30xx cn31xx; + struct cvmx_asxx_rx_prt_en_s cn38xx; + struct cvmx_asxx_rx_prt_en_s cn38xxp2; + struct cvmx_asxx_rx_prt_en_cn30xx cn50xx; + struct cvmx_asxx_rx_prt_en_s cn58xx; + struct cvmx_asxx_rx_prt_en_s cn58xxp1; +}; + +union cvmx_asxx_rx_wol { + uint64_t u64; + struct cvmx_asxx_rx_wol_s { + uint64_t reserved_2_63:62; + uint64_t status:1; + uint64_t enable:1; + } s; + struct cvmx_asxx_rx_wol_s cn38xx; + struct cvmx_asxx_rx_wol_s cn38xxp2; +}; + +union cvmx_asxx_rx_wol_msk { + uint64_t u64; + struct cvmx_asxx_rx_wol_msk_s { + uint64_t msk:64; + } s; + struct cvmx_asxx_rx_wol_msk_s cn38xx; + struct cvmx_asxx_rx_wol_msk_s cn38xxp2; +}; + +union cvmx_asxx_rx_wol_powok { + uint64_t u64; + struct cvmx_asxx_rx_wol_powok_s { + uint64_t reserved_1_63:63; + uint64_t powerok:1; + } s; + struct cvmx_asxx_rx_wol_powok_s cn38xx; + struct cvmx_asxx_rx_wol_powok_s cn38xxp2; +}; + +union cvmx_asxx_rx_wol_sig { + uint64_t u64; + struct cvmx_asxx_rx_wol_sig_s { + uint64_t reserved_32_63:32; + uint64_t sig:32; + } s; + struct cvmx_asxx_rx_wol_sig_s cn38xx; + struct cvmx_asxx_rx_wol_sig_s cn38xxp2; +}; + +union cvmx_asxx_tx_clk_setx { + uint64_t u64; + struct cvmx_asxx_tx_clk_setx_s { + uint64_t reserved_5_63:59; + uint64_t setting:5; + } s; + struct cvmx_asxx_tx_clk_setx_s cn30xx; + struct cvmx_asxx_tx_clk_setx_s cn31xx; + struct cvmx_asxx_tx_clk_setx_s cn38xx; + struct cvmx_asxx_tx_clk_setx_s cn38xxp2; + struct cvmx_asxx_tx_clk_setx_s cn50xx; + struct cvmx_asxx_tx_clk_setx_s cn58xx; + struct cvmx_asxx_tx_clk_setx_s cn58xxp1; +}; + +union cvmx_asxx_tx_comp_byp { + uint64_t u64; + struct cvmx_asxx_tx_comp_byp_s { + uint64_t reserved_0_63:64; + } s; + struct cvmx_asxx_tx_comp_byp_cn30xx { + uint64_t reserved_9_63:55; + uint64_t bypass:1; + uint64_t pctl:4; + uint64_t nctl:4; + } cn30xx; + struct cvmx_asxx_tx_comp_byp_cn30xx cn31xx; + struct cvmx_asxx_tx_comp_byp_cn38xx { + uint64_t reserved_8_63:56; + uint64_t pctl:4; + uint64_t nctl:4; + } cn38xx; + struct cvmx_asxx_tx_comp_byp_cn38xx cn38xxp2; + struct cvmx_asxx_tx_comp_byp_cn50xx { + uint64_t reserved_17_63:47; + uint64_t bypass:1; + uint64_t reserved_13_15:3; + uint64_t pctl:5; + uint64_t reserved_5_7:3; + uint64_t nctl:5; + } cn50xx; + struct cvmx_asxx_tx_comp_byp_cn58xx { + uint64_t reserved_13_63:51; + uint64_t pctl:5; + uint64_t reserved_5_7:3; + uint64_t nctl:5; + } cn58xx; + struct cvmx_asxx_tx_comp_byp_cn58xx cn58xxp1; +}; + +union cvmx_asxx_tx_hi_waterx { + uint64_t u64; + struct cvmx_asxx_tx_hi_waterx_s { + uint64_t reserved_4_63:60; + uint64_t mark:4; + } s; + struct cvmx_asxx_tx_hi_waterx_cn30xx { + uint64_t reserved_3_63:61; + uint64_t mark:3; + } cn30xx; + struct cvmx_asxx_tx_hi_waterx_cn30xx cn31xx; + struct cvmx_asxx_tx_hi_waterx_s cn38xx; + struct cvmx_asxx_tx_hi_waterx_s cn38xxp2; + struct cvmx_asxx_tx_hi_waterx_cn30xx cn50xx; + struct cvmx_asxx_tx_hi_waterx_s cn58xx; + struct cvmx_asxx_tx_hi_waterx_s cn58xxp1; +}; + +union cvmx_asxx_tx_prt_en { + uint64_t u64; + struct cvmx_asxx_tx_prt_en_s { + uint64_t reserved_4_63:60; + uint64_t prt_en:4; + } s; + struct cvmx_asxx_tx_prt_en_cn30xx { + uint64_t reserved_3_63:61; + uint64_t prt_en:3; + } cn30xx; + struct cvmx_asxx_tx_prt_en_cn30xx cn31xx; + struct cvmx_asxx_tx_prt_en_s cn38xx; + struct cvmx_asxx_tx_prt_en_s cn38xxp2; + struct cvmx_asxx_tx_prt_en_cn30xx cn50xx; + struct cvmx_asxx_tx_prt_en_s cn58xx; + struct cvmx_asxx_tx_prt_en_s cn58xxp1; +}; + +#endif diff --git a/drivers/staging/octeon/cvmx-cmd-queue.c b/drivers/staging/octeon/cvmx-cmd-queue.c new file mode 100644 index 0000000..976227b --- /dev/null +++ b/drivers/staging/octeon/cvmx-cmd-queue.c @@ -0,0 +1,306 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * along with this file; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +/* + * Support functions for managing command queues used for + * various hardware blocks. + */ + +#include + +#include + +#include "cvmx-config.h" +#include "cvmx-fpa.h" +#include "cvmx-cmd-queue.h" + +#include +#include +#include "cvmx-pko-defs.h" + +/** + * This application uses this pointer to access the global queue + * state. It points to a bootmem named block. + */ +__cvmx_cmd_queue_all_state_t *__cvmx_cmd_queue_state_ptr; + +/** + * Initialize the Global queue state pointer. + * + * Returns CVMX_CMD_QUEUE_SUCCESS or a failure code + */ +static cvmx_cmd_queue_result_t __cvmx_cmd_queue_init_state_ptr(void) +{ + char *alloc_name = "cvmx_cmd_queues"; +#if defined(CONFIG_CAVIUM_RESERVE32) && CONFIG_CAVIUM_RESERVE32 + extern uint64_t octeon_reserve32_memory; +#endif + + if (likely(__cvmx_cmd_queue_state_ptr)) + return CVMX_CMD_QUEUE_SUCCESS; + +#if defined(CONFIG_CAVIUM_RESERVE32) && CONFIG_CAVIUM_RESERVE32 + if (octeon_reserve32_memory) + __cvmx_cmd_queue_state_ptr = + cvmx_bootmem_alloc_named_range(sizeof(*__cvmx_cmd_queue_state_ptr), + octeon_reserve32_memory, + octeon_reserve32_memory + + (CONFIG_CAVIUM_RESERVE32 << + 20) - 1, 128, alloc_name); + else +#endif + __cvmx_cmd_queue_state_ptr = + cvmx_bootmem_alloc_named(sizeof(*__cvmx_cmd_queue_state_ptr), + 128, + alloc_name); + if (__cvmx_cmd_queue_state_ptr) + memset(__cvmx_cmd_queue_state_ptr, 0, + sizeof(*__cvmx_cmd_queue_state_ptr)); + else { + struct cvmx_bootmem_named_block_desc *block_desc = + cvmx_bootmem_find_named_block(alloc_name); + if (block_desc) + __cvmx_cmd_queue_state_ptr = + cvmx_phys_to_ptr(block_desc->base_addr); + else { + cvmx_dprintf + ("ERROR: cvmx_cmd_queue_initialize: Unable to get named block %s.\n", + alloc_name); + return CVMX_CMD_QUEUE_NO_MEMORY; + } + } + return CVMX_CMD_QUEUE_SUCCESS; +} + +/** + * Initialize a command queue for use. The initial FPA buffer is + * allocated and the hardware unit is configured to point to the + * new command queue. + * + * @queue_id: Hardware command queue to initialize. + * @max_depth: Maximum outstanding commands that can be queued. + * @fpa_pool: FPA pool the command queues should come from. + * @pool_size: Size of each buffer in the FPA pool (bytes) + * + * Returns CVMX_CMD_QUEUE_SUCCESS or a failure code + */ +cvmx_cmd_queue_result_t cvmx_cmd_queue_initialize(cvmx_cmd_queue_id_t queue_id, + int max_depth, int fpa_pool, + int pool_size) +{ + __cvmx_cmd_queue_state_t *qstate; + cvmx_cmd_queue_result_t result = __cvmx_cmd_queue_init_state_ptr(); + if (result != CVMX_CMD_QUEUE_SUCCESS) + return result; + + qstate = __cvmx_cmd_queue_get_state(queue_id); + if (qstate == NULL) + return CVMX_CMD_QUEUE_INVALID_PARAM; + + /* + * We artificially limit max_depth to 1<<20 words. It is an + * arbitrary limit. + */ + if (CVMX_CMD_QUEUE_ENABLE_MAX_DEPTH) { + if ((max_depth < 0) || (max_depth > 1 << 20)) + return CVMX_CMD_QUEUE_INVALID_PARAM; + } else if (max_depth != 0) + return CVMX_CMD_QUEUE_INVALID_PARAM; + + if ((fpa_pool < 0) || (fpa_pool > 7)) + return CVMX_CMD_QUEUE_INVALID_PARAM; + if ((pool_size < 128) || (pool_size > 65536)) + return CVMX_CMD_QUEUE_INVALID_PARAM; + + /* See if someone else has already initialized the queue */ + if (qstate->base_ptr_div128) { + if (max_depth != (int)qstate->max_depth) { + cvmx_dprintf("ERROR: cvmx_cmd_queue_initialize: " + "Queue already initalized with different " + "max_depth (%d).\n", + (int)qstate->max_depth); + return CVMX_CMD_QUEUE_INVALID_PARAM; + } + if (fpa_pool != qstate->fpa_pool) { + cvmx_dprintf("ERROR: cvmx_cmd_queue_initialize: " + "Queue already initalized with different " + "FPA pool (%u).\n", + qstate->fpa_pool); + return CVMX_CMD_QUEUE_INVALID_PARAM; + } + if ((pool_size >> 3) - 1 != qstate->pool_size_m1) { + cvmx_dprintf("ERROR: cvmx_cmd_queue_initialize: " + "Queue already initalized with different " + "FPA pool size (%u).\n", + (qstate->pool_size_m1 + 1) << 3); + return CVMX_CMD_QUEUE_INVALID_PARAM; + } + CVMX_SYNCWS; + return CVMX_CMD_QUEUE_ALREADY_SETUP; + } else { + union cvmx_fpa_ctl_status status; + void *buffer; + + status.u64 = cvmx_read_csr(CVMX_FPA_CTL_STATUS); + if (!status.s.enb) { + cvmx_dprintf("ERROR: cvmx_cmd_queue_initialize: " + "FPA is not enabled.\n"); + return CVMX_CMD_QUEUE_NO_MEMORY; + } + buffer = cvmx_fpa_alloc(fpa_pool); + if (buffer == NULL) { + cvmx_dprintf("ERROR: cvmx_cmd_queue_initialize: " + "Unable to allocate initial buffer.\n"); + return CVMX_CMD_QUEUE_NO_MEMORY; + } + + memset(qstate, 0, sizeof(*qstate)); + qstate->max_depth = max_depth; + qstate->fpa_pool = fpa_pool; + qstate->pool_size_m1 = (pool_size >> 3) - 1; + qstate->base_ptr_div128 = cvmx_ptr_to_phys(buffer) / 128; + /* + * We zeroed the now serving field so we need to also + * zero the ticket. + */ + __cvmx_cmd_queue_state_ptr-> + ticket[__cvmx_cmd_queue_get_index(queue_id)] = 0; + CVMX_SYNCWS; + return CVMX_CMD_QUEUE_SUCCESS; + } +} + +/** + * Shutdown a queue a free it's command buffers to the FPA. The + * hardware connected to the queue must be stopped before this + * function is called. + * + * @queue_id: Queue to shutdown + * + * Returns CVMX_CMD_QUEUE_SUCCESS or a failure code + */ +cvmx_cmd_queue_result_t cvmx_cmd_queue_shutdown(cvmx_cmd_queue_id_t queue_id) +{ + __cvmx_cmd_queue_state_t *qptr = __cvmx_cmd_queue_get_state(queue_id); + if (qptr == NULL) { + cvmx_dprintf("ERROR: cvmx_cmd_queue_shutdown: Unable to " + "get queue information.\n"); + return CVMX_CMD_QUEUE_INVALID_PARAM; + } + + if (cvmx_cmd_queue_length(queue_id) > 0) { + cvmx_dprintf("ERROR: cvmx_cmd_queue_shutdown: Queue still " + "has data in it.\n"); + return CVMX_CMD_QUEUE_FULL; + } + + __cvmx_cmd_queue_lock(queue_id, qptr); + if (qptr->base_ptr_div128) { + cvmx_fpa_free(cvmx_phys_to_ptr + ((uint64_t) qptr->base_ptr_div128 << 7), + qptr->fpa_pool, 0); + qptr->base_ptr_div128 = 0; + } + __cvmx_cmd_queue_unlock(qptr); + + return CVMX_CMD_QUEUE_SUCCESS; +} + +/** + * Return the number of command words pending in the queue. This + * function may be relatively slow for some hardware units. + * + * @queue_id: Hardware command queue to query + * + * Returns Number of outstanding commands + */ +int cvmx_cmd_queue_length(cvmx_cmd_queue_id_t queue_id) +{ + if (CVMX_ENABLE_PARAMETER_CHECKING) { + if (__cvmx_cmd_queue_get_state(queue_id) == NULL) + return CVMX_CMD_QUEUE_INVALID_PARAM; + } + + /* + * The cast is here so gcc with check that all values in the + * cvmx_cmd_queue_id_t enumeration are here. + */ + switch ((cvmx_cmd_queue_id_t) (queue_id & 0xff0000)) { + case CVMX_CMD_QUEUE_PKO_BASE: + /* + * FIXME: Need atomic lock on + * CVMX_PKO_REG_READ_IDX. Right now we are normally + * called with the queue lock, so that is a SLIGHT + * amount of protection. + */ + cvmx_write_csr(CVMX_PKO_REG_READ_IDX, queue_id & 0xffff); + if (OCTEON_IS_MODEL(OCTEON_CN3XXX)) { + union cvmx_pko_mem_debug9 debug9; + debug9.u64 = cvmx_read_csr(CVMX_PKO_MEM_DEBUG9); + return debug9.cn38xx.doorbell; + } else { + union cvmx_pko_mem_debug8 debug8; + debug8.u64 = cvmx_read_csr(CVMX_PKO_MEM_DEBUG8); + return debug8.cn58xx.doorbell; + } + case CVMX_CMD_QUEUE_ZIP: + case CVMX_CMD_QUEUE_DFA: + case CVMX_CMD_QUEUE_RAID: + /* FIXME: Implement other lengths */ + return 0; + case CVMX_CMD_QUEUE_DMA_BASE: + { + union cvmx_npei_dmax_counts dmax_counts; + dmax_counts.u64 = + cvmx_read_csr(CVMX_PEXP_NPEI_DMAX_COUNTS + (queue_id & 0x7)); + return dmax_counts.s.dbell; + } + case CVMX_CMD_QUEUE_END: + return CVMX_CMD_QUEUE_INVALID_PARAM; + } + return CVMX_CMD_QUEUE_INVALID_PARAM; +} + +/** + * Return the command buffer to be written to. The purpose of this + * function is to allow CVMX routine access t othe low level buffer + * for initial hardware setup. User applications should not call this + * function directly. + * + * @queue_id: Command queue to query + * + * Returns Command buffer or NULL on failure + */ +void *cvmx_cmd_queue_buffer(cvmx_cmd_queue_id_t queue_id) +{ + __cvmx_cmd_queue_state_t *qptr = __cvmx_cmd_queue_get_state(queue_id); + if (qptr && qptr->base_ptr_div128) + return cvmx_phys_to_ptr((uint64_t) qptr->base_ptr_div128 << 7); + else + return NULL; +} diff --git a/drivers/staging/octeon/cvmx-cmd-queue.h b/drivers/staging/octeon/cvmx-cmd-queue.h new file mode 100644 index 0000000..f0cb20f --- /dev/null +++ b/drivers/staging/octeon/cvmx-cmd-queue.h @@ -0,0 +1,617 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * along with this file; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +/* + * + * Support functions for managing command queues used for + * various hardware blocks. + * + * The common command queue infrastructure abstracts out the + * software necessary for adding to Octeon's chained queue + * structures. These structures are used for commands to the + * PKO, ZIP, DFA, RAID, and DMA engine blocks. Although each + * hardware unit takes commands and CSRs of different types, + * they all use basic linked command buffers to store the + * pending request. In general, users of the CVMX API don't + * call cvmx-cmd-queue functions directly. Instead the hardware + * unit specific wrapper should be used. The wrappers perform + * unit specific validation and CSR writes to submit the + * commands. + * + * Even though most software will never directly interact with + * cvmx-cmd-queue, knowledge of its internal working can help + * in diagnosing performance problems and help with debugging. + * + * Command queue pointers are stored in a global named block + * called "cvmx_cmd_queues". Except for the PKO queues, each + * hardware queue is stored in its own cache line to reduce SMP + * contention on spin locks. The PKO queues are stored such that + * every 16th queue is next to each other in memory. This scheme + * allows for queues being in separate cache lines when there + * are low number of queues per port. With 16 queues per port, + * the first queue for each port is in the same cache area. The + * second queues for each port are in another area, etc. This + * allows software to implement very efficient lockless PKO with + * 16 queues per port using a minimum of cache lines per core. + * All queues for a given core will be isolated in the same + * cache area. + * + * In addition to the memory pointer layout, cvmx-cmd-queue + * provides an optimized fair ll/sc locking mechanism for the + * queues. The lock uses a "ticket / now serving" model to + * maintain fair order on contended locks. In addition, it uses + * predicted locking time to limit cache contention. When a core + * know it must wait in line for a lock, it spins on the + * internal cycle counter to completely eliminate any causes of + * bus traffic. + * + */ + +#ifndef __CVMX_CMD_QUEUE_H__ +#define __CVMX_CMD_QUEUE_H__ + +#include + +#include "cvmx-fpa.h" +/** + * By default we disable the max depth support. Most programs + * don't use it and it slows down the command queue processing + * significantly. + */ +#ifndef CVMX_CMD_QUEUE_ENABLE_MAX_DEPTH +#define CVMX_CMD_QUEUE_ENABLE_MAX_DEPTH 0 +#endif + +/** + * Enumeration representing all hardware blocks that use command + * queues. Each hardware block has up to 65536 sub identifiers for + * multiple command queues. Not all chips support all hardware + * units. + */ +typedef enum { + CVMX_CMD_QUEUE_PKO_BASE = 0x00000, + +#define CVMX_CMD_QUEUE_PKO(queue) \ + ((cvmx_cmd_queue_id_t)(CVMX_CMD_QUEUE_PKO_BASE + (0xffff&(queue)))) + + CVMX_CMD_QUEUE_ZIP = 0x10000, + CVMX_CMD_QUEUE_DFA = 0x20000, + CVMX_CMD_QUEUE_RAID = 0x30000, + CVMX_CMD_QUEUE_DMA_BASE = 0x40000, + +#define CVMX_CMD_QUEUE_DMA(queue) \ + ((cvmx_cmd_queue_id_t)(CVMX_CMD_QUEUE_DMA_BASE + (0xffff&(queue)))) + + CVMX_CMD_QUEUE_END = 0x50000, +} cvmx_cmd_queue_id_t; + +/** + * Command write operations can fail if the comamnd queue needs + * a new buffer and the associated FPA pool is empty. It can also + * fail if the number of queued command words reaches the maximum + * set at initialization. + */ +typedef enum { + CVMX_CMD_QUEUE_SUCCESS = 0, + CVMX_CMD_QUEUE_NO_MEMORY = -1, + CVMX_CMD_QUEUE_FULL = -2, + CVMX_CMD_QUEUE_INVALID_PARAM = -3, + CVMX_CMD_QUEUE_ALREADY_SETUP = -4, +} cvmx_cmd_queue_result_t; + +typedef struct { + /* You have lock when this is your ticket */ + uint8_t now_serving; + uint64_t unused1:24; + /* Maximum outstanding command words */ + uint32_t max_depth; + /* FPA pool buffers come from */ + uint64_t fpa_pool:3; + /* Top of command buffer pointer shifted 7 */ + uint64_t base_ptr_div128:29; + uint64_t unused2:6; + /* FPA buffer size in 64bit words minus 1 */ + uint64_t pool_size_m1:13; + /* Number of comamnds already used in buffer */ + uint64_t index:13; +} __cvmx_cmd_queue_state_t; + +/** + * This structure contains the global state of all comamnd queues. + * It is stored in a bootmem named block and shared by all + * applications running on Octeon. Tickets are stored in a differnet + * cahce line that queue information to reduce the contention on the + * ll/sc used to get a ticket. If this is not the case, the update + * of queue state causes the ll/sc to fail quite often. + */ +typedef struct { + uint64_t ticket[(CVMX_CMD_QUEUE_END >> 16) * 256]; + __cvmx_cmd_queue_state_t state[(CVMX_CMD_QUEUE_END >> 16) * 256]; +} __cvmx_cmd_queue_all_state_t; + +/** + * Initialize a command queue for use. The initial FPA buffer is + * allocated and the hardware unit is configured to point to the + * new command queue. + * + * @queue_id: Hardware command queue to initialize. + * @max_depth: Maximum outstanding commands that can be queued. + * @fpa_pool: FPA pool the command queues should come from. + * @pool_size: Size of each buffer in the FPA pool (bytes) + * + * Returns CVMX_CMD_QUEUE_SUCCESS or a failure code + */ +cvmx_cmd_queue_result_t cvmx_cmd_queue_initialize(cvmx_cmd_queue_id_t queue_id, + int max_depth, int fpa_pool, + int pool_size); + +/** + * Shutdown a queue a free it's command buffers to the FPA. The + * hardware connected to the queue must be stopped before this + * function is called. + * + * @queue_id: Queue to shutdown + * + * Returns CVMX_CMD_QUEUE_SUCCESS or a failure code + */ +cvmx_cmd_queue_result_t cvmx_cmd_queue_shutdown(cvmx_cmd_queue_id_t queue_id); + +/** + * Return the number of command words pending in the queue. This + * function may be relatively slow for some hardware units. + * + * @queue_id: Hardware command queue to query + * + * Returns Number of outstanding commands + */ +int cvmx_cmd_queue_length(cvmx_cmd_queue_id_t queue_id); + +/** + * Return the command buffer to be written to. The purpose of this + * function is to allow CVMX routine access t othe low level buffer + * for initial hardware setup. User applications should not call this + * function directly. + * + * @queue_id: Command queue to query + * + * Returns Command buffer or NULL on failure + */ +void *cvmx_cmd_queue_buffer(cvmx_cmd_queue_id_t queue_id); + +/** + * Get the index into the state arrays for the supplied queue id. + * + * @queue_id: Queue ID to get an index for + * + * Returns Index into the state arrays + */ +static inline int __cvmx_cmd_queue_get_index(cvmx_cmd_queue_id_t queue_id) +{ + /* + * Warning: This code currently only works with devices that + * have 256 queues or less. Devices with more than 16 queues + * are layed out in memory to allow cores quick access to + * every 16th queue. This reduces cache thrashing when you are + * running 16 queues per port to support lockless operation. + */ + int unit = queue_id >> 16; + int q = (queue_id >> 4) & 0xf; + int core = queue_id & 0xf; + return unit * 256 + core * 16 + q; +} + +/** + * Lock the supplied queue so nobody else is updating it at the same + * time as us. + * + * @queue_id: Queue ID to lock + * @qptr: Pointer to the queue's global state + */ +static inline void __cvmx_cmd_queue_lock(cvmx_cmd_queue_id_t queue_id, + __cvmx_cmd_queue_state_t *qptr) +{ + extern __cvmx_cmd_queue_all_state_t + *__cvmx_cmd_queue_state_ptr; + int tmp; + int my_ticket; + prefetch(qptr); + asm volatile ( + ".set push\n" + ".set noreorder\n" + "1:\n" + /* Atomic add one to ticket_ptr */ + "ll %[my_ticket], %[ticket_ptr]\n" + /* and store the original value */ + "li %[ticket], 1\n" + /* in my_ticket */ + "baddu %[ticket], %[my_ticket]\n" + "sc %[ticket], %[ticket_ptr]\n" + "beqz %[ticket], 1b\n" + " nop\n" + /* Load the current now_serving ticket */ + "lbu %[ticket], %[now_serving]\n" + "2:\n" + /* Jump out if now_serving == my_ticket */ + "beq %[ticket], %[my_ticket], 4f\n" + /* Find out how many tickets are in front of me */ + " subu %[ticket], %[my_ticket], %[ticket]\n" + /* Use tickets in front of me minus one to delay */ + "subu %[ticket], 1\n" + /* Delay will be ((tickets in front)-1)*32 loops */ + "cins %[ticket], %[ticket], 5, 7\n" + "3:\n" + /* Loop here until our ticket might be up */ + "bnez %[ticket], 3b\n" + " subu %[ticket], 1\n" + /* Jump back up to check out ticket again */ + "b 2b\n" + /* Load the current now_serving ticket */ + " lbu %[ticket], %[now_serving]\n" + "4:\n" + ".set pop\n" : + [ticket_ptr] "=m"(__cvmx_cmd_queue_state_ptr->ticket[__cvmx_cmd_queue_get_index(queue_id)]), + [now_serving] "=m"(qptr->now_serving), [ticket] "=r"(tmp), + [my_ticket] "=r"(my_ticket) + ); +} + +/** + * Unlock the queue, flushing all writes. + * + * @qptr: Queue to unlock + */ +static inline void __cvmx_cmd_queue_unlock(__cvmx_cmd_queue_state_t *qptr) +{ + qptr->now_serving++; + CVMX_SYNCWS; +} + +/** + * Get the queue state structure for the given queue id + * + * @queue_id: Queue id to get + * + * Returns Queue structure or NULL on failure + */ +static inline __cvmx_cmd_queue_state_t + *__cvmx_cmd_queue_get_state(cvmx_cmd_queue_id_t queue_id) +{ + extern __cvmx_cmd_queue_all_state_t + *__cvmx_cmd_queue_state_ptr; + return &__cvmx_cmd_queue_state_ptr-> + state[__cvmx_cmd_queue_get_index(queue_id)]; +} + +/** + * Write an arbitrary number of command words to a command queue. + * This is a generic function; the fixed number of comamnd word + * functions yield higher performance. + * + * @queue_id: Hardware command queue to write to + * @use_locking: + * Use internal locking to ensure exclusive access for queue + * updates. If you don't use this locking you must ensure + * exclusivity some other way. Locking is strongly recommended. + * @cmd_count: Number of command words to write + * @cmds: Array of comamnds to write + * + * Returns CVMX_CMD_QUEUE_SUCCESS or a failure code + */ +static inline cvmx_cmd_queue_result_t cvmx_cmd_queue_write(cvmx_cmd_queue_id_t + queue_id, + int use_locking, + int cmd_count, + uint64_t *cmds) +{ + __cvmx_cmd_queue_state_t *qptr = __cvmx_cmd_queue_get_state(queue_id); + + /* Make sure nobody else is updating the same queue */ + if (likely(use_locking)) + __cvmx_cmd_queue_lock(queue_id, qptr); + + /* + * If a max queue length was specified then make sure we don't + * exceed it. If any part of the command would be below the + * limit we allow it. + */ + if (CVMX_CMD_QUEUE_ENABLE_MAX_DEPTH && unlikely(qptr->max_depth)) { + if (unlikely + (cvmx_cmd_queue_length(queue_id) > (int)qptr->max_depth)) { + if (likely(use_locking)) + __cvmx_cmd_queue_unlock(qptr); + return CVMX_CMD_QUEUE_FULL; + } + } + + /* + * Normally there is plenty of room in the current buffer for + * the command. + */ + if (likely(qptr->index + cmd_count < qptr->pool_size_m1)) { + uint64_t *ptr = + (uint64_t *) cvmx_phys_to_ptr((uint64_t) qptr-> + base_ptr_div128 << 7); + ptr += qptr->index; + qptr->index += cmd_count; + while (cmd_count--) + *ptr++ = *cmds++; + } else { + uint64_t *ptr; + int count; + /* + * We need a new comamnd buffer. Fail if there isn't + * one available. + */ + uint64_t *new_buffer = + (uint64_t *) cvmx_fpa_alloc(qptr->fpa_pool); + if (unlikely(new_buffer == NULL)) { + if (likely(use_locking)) + __cvmx_cmd_queue_unlock(qptr); + return CVMX_CMD_QUEUE_NO_MEMORY; + } + ptr = + (uint64_t *) cvmx_phys_to_ptr((uint64_t) qptr-> + base_ptr_div128 << 7); + /* + * Figure out how many command words will fit in this + * buffer. One location will be needed for the next + * buffer pointer. + */ + count = qptr->pool_size_m1 - qptr->index; + ptr += qptr->index; + cmd_count -= count; + while (count--) + *ptr++ = *cmds++; + *ptr = cvmx_ptr_to_phys(new_buffer); + /* + * The current buffer is full and has a link to the + * next buffer. Time to write the rest of the commands + * into the new buffer. + */ + qptr->base_ptr_div128 = *ptr >> 7; + qptr->index = cmd_count; + ptr = new_buffer; + while (cmd_count--) + *ptr++ = *cmds++; + } + + /* All updates are complete. Release the lock and return */ + if (likely(use_locking)) + __cvmx_cmd_queue_unlock(qptr); + return CVMX_CMD_QUEUE_SUCCESS; +} + +/** + * Simple function to write two command words to a command + * queue. + * + * @queue_id: Hardware command queue to write to + * @use_locking: + * Use internal locking to ensure exclusive access for queue + * updates. If you don't use this locking you must ensure + * exclusivity some other way. Locking is strongly recommended. + * @cmd1: Command + * @cmd2: Command + * + * Returns CVMX_CMD_QUEUE_SUCCESS or a failure code + */ +static inline cvmx_cmd_queue_result_t cvmx_cmd_queue_write2(cvmx_cmd_queue_id_t + queue_id, + int use_locking, + uint64_t cmd1, + uint64_t cmd2) +{ + __cvmx_cmd_queue_state_t *qptr = __cvmx_cmd_queue_get_state(queue_id); + + /* Make sure nobody else is updating the same queue */ + if (likely(use_locking)) + __cvmx_cmd_queue_lock(queue_id, qptr); + + /* + * If a max queue length was specified then make sure we don't + * exceed it. If any part of the command would be below the + * limit we allow it. + */ + if (CVMX_CMD_QUEUE_ENABLE_MAX_DEPTH && unlikely(qptr->max_depth)) { + if (unlikely + (cvmx_cmd_queue_length(queue_id) > (int)qptr->max_depth)) { + if (likely(use_locking)) + __cvmx_cmd_queue_unlock(qptr); + return CVMX_CMD_QUEUE_FULL; + } + } + + /* + * Normally there is plenty of room in the current buffer for + * the command. + */ + if (likely(qptr->index + 2 < qptr->pool_size_m1)) { + uint64_t *ptr = + (uint64_t *) cvmx_phys_to_ptr((uint64_t) qptr-> + base_ptr_div128 << 7); + ptr += qptr->index; + qptr->index += 2; + ptr[0] = cmd1; + ptr[1] = cmd2; + } else { + uint64_t *ptr; + /* + * Figure out how many command words will fit in this + * buffer. One location will be needed for the next + * buffer pointer. + */ + int count = qptr->pool_size_m1 - qptr->index; + /* + * We need a new comamnd buffer. Fail if there isn't + * one available. + */ + uint64_t *new_buffer = + (uint64_t *) cvmx_fpa_alloc(qptr->fpa_pool); + if (unlikely(new_buffer == NULL)) { + if (likely(use_locking)) + __cvmx_cmd_queue_unlock(qptr); + return CVMX_CMD_QUEUE_NO_MEMORY; + } + count--; + ptr = + (uint64_t *) cvmx_phys_to_ptr((uint64_t) qptr-> + base_ptr_div128 << 7); + ptr += qptr->index; + *ptr++ = cmd1; + if (likely(count)) + *ptr++ = cmd2; + *ptr = cvmx_ptr_to_phys(new_buffer); + /* + * The current buffer is full and has a link to the + * next buffer. Time to write the rest of the commands + * into the new buffer. + */ + qptr->base_ptr_div128 = *ptr >> 7; + qptr->index = 0; + if (unlikely(count == 0)) { + qptr->index = 1; + new_buffer[0] = cmd2; + } + } + + /* All updates are complete. Release the lock and return */ + if (likely(use_locking)) + __cvmx_cmd_queue_unlock(qptr); + return CVMX_CMD_QUEUE_SUCCESS; +} + +/** + * Simple function to write three command words to a command + * queue. + * + * @queue_id: Hardware command queue to write to + * @use_locking: + * Use internal locking to ensure exclusive access for queue + * updates. If you don't use this locking you must ensure + * exclusivity some other way. Locking is strongly recommended. + * @cmd1: Command + * @cmd2: Command + * @cmd3: Command + * + * Returns CVMX_CMD_QUEUE_SUCCESS or a failure code + */ +static inline cvmx_cmd_queue_result_t cvmx_cmd_queue_write3(cvmx_cmd_queue_id_t + queue_id, + int use_locking, + uint64_t cmd1, + uint64_t cmd2, + uint64_t cmd3) +{ + __cvmx_cmd_queue_state_t *qptr = __cvmx_cmd_queue_get_state(queue_id); + + /* Make sure nobody else is updating the same queue */ + if (likely(use_locking)) + __cvmx_cmd_queue_lock(queue_id, qptr); + + /* + * If a max queue length was specified then make sure we don't + * exceed it. If any part of the command would be below the + * limit we allow it. + */ + if (CVMX_CMD_QUEUE_ENABLE_MAX_DEPTH && unlikely(qptr->max_depth)) { + if (unlikely + (cvmx_cmd_queue_length(queue_id) > (int)qptr->max_depth)) { + if (likely(use_locking)) + __cvmx_cmd_queue_unlock(qptr); + return CVMX_CMD_QUEUE_FULL; + } + } + + /* + * Normally there is plenty of room in the current buffer for + * the command. + */ + if (likely(qptr->index + 3 < qptr->pool_size_m1)) { + uint64_t *ptr = + (uint64_t *) cvmx_phys_to_ptr((uint64_t) qptr-> + base_ptr_div128 << 7); + ptr += qptr->index; + qptr->index += 3; + ptr[0] = cmd1; + ptr[1] = cmd2; + ptr[2] = cmd3; + } else { + uint64_t *ptr; + /* + * Figure out how many command words will fit in this + * buffer. One location will be needed for the next + * buffer pointer + */ + int count = qptr->pool_size_m1 - qptr->index; + /* + * We need a new comamnd buffer. Fail if there isn't + * one available + */ + uint64_t *new_buffer = + (uint64_t *) cvmx_fpa_alloc(qptr->fpa_pool); + if (unlikely(new_buffer == NULL)) { + if (likely(use_locking)) + __cvmx_cmd_queue_unlock(qptr); + return CVMX_CMD_QUEUE_NO_MEMORY; + } + count--; + ptr = + (uint64_t *) cvmx_phys_to_ptr((uint64_t) qptr-> + base_ptr_div128 << 7); + ptr += qptr->index; + *ptr++ = cmd1; + if (count) { + *ptr++ = cmd2; + if (count > 1) + *ptr++ = cmd3; + } + *ptr = cvmx_ptr_to_phys(new_buffer); + /* + * The current buffer is full and has a link to the + * next buffer. Time to write the rest of the commands + * into the new buffer. + */ + qptr->base_ptr_div128 = *ptr >> 7; + qptr->index = 0; + ptr = new_buffer; + if (count == 0) { + *ptr++ = cmd2; + qptr->index++; + } + if (count < 2) { + *ptr++ = cmd3; + qptr->index++; + } + } + + /* All updates are complete. Release the lock and return */ + if (likely(use_locking)) + __cvmx_cmd_queue_unlock(qptr); + return CVMX_CMD_QUEUE_SUCCESS; +} + +#endif /* __CVMX_CMD_QUEUE_H__ */ diff --git a/drivers/staging/octeon/cvmx-config.h b/drivers/staging/octeon/cvmx-config.h new file mode 100644 index 0000000..078a520 --- /dev/null +++ b/drivers/staging/octeon/cvmx-config.h @@ -0,0 +1,169 @@ +#ifndef __CVMX_CONFIG_H__ +#define __CVMX_CONFIG_H__ + +/************************* Config Specific Defines ************************/ +#define CVMX_LLM_NUM_PORTS 1 +#define CVMX_NULL_POINTER_PROTECT 1 +#define CVMX_ENABLE_DEBUG_PRINTS 1 +/* PKO queues per port for interface 0 (ports 0-15) */ +#define CVMX_PKO_QUEUES_PER_PORT_INTERFACE0 1 +/* PKO queues per port for interface 1 (ports 16-31) */ +#define CVMX_PKO_QUEUES_PER_PORT_INTERFACE1 1 +/* Limit on the number of PKO ports enabled for interface 0 */ +#define CVMX_PKO_MAX_PORTS_INTERFACE0 CVMX_HELPER_PKO_MAX_PORTS_INTERFACE0 +/* Limit on the number of PKO ports enabled for interface 1 */ +#define CVMX_PKO_MAX_PORTS_INTERFACE1 CVMX_HELPER_PKO_MAX_PORTS_INTERFACE1 +/* PKO queues per port for PCI (ports 32-35) */ +#define CVMX_PKO_QUEUES_PER_PORT_PCI 1 +/* PKO queues per port for Loop devices (ports 36-39) */ +#define CVMX_PKO_QUEUES_PER_PORT_LOOP 1 + +/************************* FPA allocation *********************************/ +/* Pool sizes in bytes, must be multiple of a cache line */ +#define CVMX_FPA_POOL_0_SIZE (16 * CVMX_CACHE_LINE_SIZE) +#define CVMX_FPA_POOL_1_SIZE (1 * CVMX_CACHE_LINE_SIZE) +#define CVMX_FPA_POOL_2_SIZE (8 * CVMX_CACHE_LINE_SIZE) +#define CVMX_FPA_POOL_3_SIZE (0 * CVMX_CACHE_LINE_SIZE) +#define CVMX_FPA_POOL_4_SIZE (0 * CVMX_CACHE_LINE_SIZE) +#define CVMX_FPA_POOL_5_SIZE (0 * CVMX_CACHE_LINE_SIZE) +#define CVMX_FPA_POOL_6_SIZE (0 * CVMX_CACHE_LINE_SIZE) +#define CVMX_FPA_POOL_7_SIZE (0 * CVMX_CACHE_LINE_SIZE) + +/* Pools in use */ +/* Packet buffers */ +#define CVMX_FPA_PACKET_POOL (0) +#define CVMX_FPA_PACKET_POOL_SIZE CVMX_FPA_POOL_0_SIZE +/* Work queue entrys */ +#define CVMX_FPA_WQE_POOL (1) +#define CVMX_FPA_WQE_POOL_SIZE CVMX_FPA_POOL_1_SIZE +/* PKO queue command buffers */ +#define CVMX_FPA_OUTPUT_BUFFER_POOL (2) +#define CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE CVMX_FPA_POOL_2_SIZE + +/************************* FAU allocation ********************************/ +/* The fetch and add registers are allocated here. They are arranged + * in order of descending size so that all alignment constraints are + * automatically met. The enums are linked so that the following enum + * continues allocating where the previous one left off, so the + * numbering within each enum always starts with zero. The macros + * take care of the address increment size, so the values entered + * always increase by 1. FAU registers are accessed with byte + * addresses. + */ + +#define CVMX_FAU_REG_64_ADDR(x) ((x << 3) + CVMX_FAU_REG_64_START) +typedef enum { + CVMX_FAU_REG_64_START = 0, + CVMX_FAU_REG_64_END = CVMX_FAU_REG_64_ADDR(0), +} cvmx_fau_reg_64_t; + +#define CVMX_FAU_REG_32_ADDR(x) ((x << 2) + CVMX_FAU_REG_32_START) +typedef enum { + CVMX_FAU_REG_32_START = CVMX_FAU_REG_64_END, + CVMX_FAU_REG_32_END = CVMX_FAU_REG_32_ADDR(0), +} cvmx_fau_reg_32_t; + +#define CVMX_FAU_REG_16_ADDR(x) ((x << 1) + CVMX_FAU_REG_16_START) +typedef enum { + CVMX_FAU_REG_16_START = CVMX_FAU_REG_32_END, + CVMX_FAU_REG_16_END = CVMX_FAU_REG_16_ADDR(0), +} cvmx_fau_reg_16_t; + +#define CVMX_FAU_REG_8_ADDR(x) ((x) + CVMX_FAU_REG_8_START) +typedef enum { + CVMX_FAU_REG_8_START = CVMX_FAU_REG_16_END, + CVMX_FAU_REG_8_END = CVMX_FAU_REG_8_ADDR(0), +} cvmx_fau_reg_8_t; + +/* + * The name CVMX_FAU_REG_AVAIL_BASE is provided to indicate the first + * available FAU address that is not allocated in cvmx-config.h. This + * is 64 bit aligned. + */ +#define CVMX_FAU_REG_AVAIL_BASE ((CVMX_FAU_REG_8_END + 0x7) & (~0x7ULL)) +#define CVMX_FAU_REG_END (2048) + +/********************** scratch memory allocation *************************/ +/* Scratchpad memory allocation. Note that these are byte memory + * addresses. Some uses of scratchpad (IOBDMA for example) require + * the use of 8-byte aligned addresses, so proper alignment needs to + * be taken into account. + */ +/* Generic scratch iobdma area */ +#define CVMX_SCR_SCRATCH (0) +/* First location available after cvmx-config.h allocated region. */ +#define CVMX_SCR_REG_AVAIL_BASE (8) + +/* + * CVMX_HELPER_FIRST_MBUFF_SKIP is the number of bytes to reserve + * before the beginning of the packet. If necessary, override the + * default here. See the IPD section of the hardware manual for MBUFF + * SKIP details. + */ +#define CVMX_HELPER_FIRST_MBUFF_SKIP 184 + +/* + * CVMX_HELPER_NOT_FIRST_MBUFF_SKIP is the number of bytes to reserve + * in each chained packet element. If necessary, override the default + * here. + */ +#define CVMX_HELPER_NOT_FIRST_MBUFF_SKIP 0 + +/* + * CVMX_HELPER_ENABLE_BACK_PRESSURE controls whether back pressure is + * enabled for all input ports. This controls if IPD sends + * backpressure to all ports if Octeon's FPA pools don't have enough + * packet or work queue entries. Even when this is off, it is still + * possible to get backpressure from individual hardware ports. When + * configuring backpressure, also check + * CVMX_HELPER_DISABLE_*_BACKPRESSURE below. If necessary, override + * the default here. + */ +#define CVMX_HELPER_ENABLE_BACK_PRESSURE 1 + +/* + * CVMX_HELPER_ENABLE_IPD controls if the IPD is enabled in the helper + * function. Once it is enabled the hardware starts accepting + * packets. You might want to skip the IPD enable if configuration + * changes are need from the default helper setup. If necessary, + * override the default here. + */ +#define CVMX_HELPER_ENABLE_IPD 0 + +/* + * CVMX_HELPER_INPUT_TAG_TYPE selects the type of tag that the IPD assigns + * to incoming packets. + */ +#define CVMX_HELPER_INPUT_TAG_TYPE CVMX_POW_TAG_TYPE_ORDERED + +#define CVMX_ENABLE_PARAMETER_CHECKING 0 + +/* + * The following select which fields are used by the PIP to generate + * the tag on INPUT + * 0: don't include + * 1: include + */ +#define CVMX_HELPER_INPUT_TAG_IPV6_SRC_IP 0 +#define CVMX_HELPER_INPUT_TAG_IPV6_DST_IP 0 +#define CVMX_HELPER_INPUT_TAG_IPV6_SRC_PORT 0 +#define CVMX_HELPER_INPUT_TAG_IPV6_DST_PORT 0 +#define CVMX_HELPER_INPUT_TAG_IPV6_NEXT_HEADER 0 +#define CVMX_HELPER_INPUT_TAG_IPV4_SRC_IP 0 +#define CVMX_HELPER_INPUT_TAG_IPV4_DST_IP 0 +#define CVMX_HELPER_INPUT_TAG_IPV4_SRC_PORT 0 +#define CVMX_HELPER_INPUT_TAG_IPV4_DST_PORT 0 +#define CVMX_HELPER_INPUT_TAG_IPV4_PROTOCOL 0 +#define CVMX_HELPER_INPUT_TAG_INPUT_PORT 1 + +/* Select skip mode for input ports */ +#define CVMX_HELPER_INPUT_PORT_SKIP_MODE CVMX_PIP_PORT_CFG_MODE_SKIPL2 + +/* + * Force backpressure to be disabled. This overrides all other + * backpressure configuration. + */ +#define CVMX_HELPER_DISABLE_RGMII_BACKPRESSURE 0 + +#endif /* __CVMX_CONFIG_H__ */ + diff --git a/drivers/staging/octeon/cvmx-dbg-defs.h b/drivers/staging/octeon/cvmx-dbg-defs.h new file mode 100644 index 0000000..abbf42d --- /dev/null +++ b/drivers/staging/octeon/cvmx-dbg-defs.h @@ -0,0 +1,72 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * along with this file; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +#ifndef __CVMX_DBG_DEFS_H__ +#define __CVMX_DBG_DEFS_H__ + +#define CVMX_DBG_DATA \ + CVMX_ADD_IO_SEG(0x00011F00000001E8ull) + +union cvmx_dbg_data { + uint64_t u64; + struct cvmx_dbg_data_s { + uint64_t reserved_23_63:41; + uint64_t c_mul:5; + uint64_t dsel_ext:1; + uint64_t data:17; + } s; + struct cvmx_dbg_data_cn30xx { + uint64_t reserved_31_63:33; + uint64_t pll_mul:3; + uint64_t reserved_23_27:5; + uint64_t c_mul:5; + uint64_t dsel_ext:1; + uint64_t data:17; + } cn30xx; + struct cvmx_dbg_data_cn30xx cn31xx; + struct cvmx_dbg_data_cn38xx { + uint64_t reserved_29_63:35; + uint64_t d_mul:4; + uint64_t dclk_mul2:1; + uint64_t cclk_div2:1; + uint64_t c_mul:5; + uint64_t dsel_ext:1; + uint64_t data:17; + } cn38xx; + struct cvmx_dbg_data_cn38xx cn38xxp2; + struct cvmx_dbg_data_cn30xx cn50xx; + struct cvmx_dbg_data_cn58xx { + uint64_t reserved_29_63:35; + uint64_t rem:6; + uint64_t c_mul:5; + uint64_t dsel_ext:1; + uint64_t data:17; + } cn58xx; + struct cvmx_dbg_data_cn58xx cn58xxp1; +}; + +#endif diff --git a/drivers/staging/octeon/cvmx-fau.h b/drivers/staging/octeon/cvmx-fau.h new file mode 100644 index 0000000..29bdce6 --- /dev/null +++ b/drivers/staging/octeon/cvmx-fau.h @@ -0,0 +1,597 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * along with this file; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +/* + * Interface to the hardware Fetch and Add Unit. + */ + +#ifndef __CVMX_FAU_H__ +#define __CVMX_FAU_H__ + +/* + * Octeon Fetch and Add Unit (FAU) + */ + +#define CVMX_FAU_LOAD_IO_ADDRESS cvmx_build_io_address(0x1e, 0) +#define CVMX_FAU_BITS_SCRADDR 63, 56 +#define CVMX_FAU_BITS_LEN 55, 48 +#define CVMX_FAU_BITS_INEVAL 35, 14 +#define CVMX_FAU_BITS_TAGWAIT 13, 13 +#define CVMX_FAU_BITS_NOADD 13, 13 +#define CVMX_FAU_BITS_SIZE 12, 11 +#define CVMX_FAU_BITS_REGISTER 10, 0 + +typedef enum { + CVMX_FAU_OP_SIZE_8 = 0, + CVMX_FAU_OP_SIZE_16 = 1, + CVMX_FAU_OP_SIZE_32 = 2, + CVMX_FAU_OP_SIZE_64 = 3 +} cvmx_fau_op_size_t; + +/** + * Tagwait return definition. If a timeout occurs, the error + * bit will be set. Otherwise the value of the register before + * the update will be returned. + */ +typedef struct { + uint64_t error:1; + int64_t value:63; +} cvmx_fau_tagwait64_t; + +/** + * Tagwait return definition. If a timeout occurs, the error + * bit will be set. Otherwise the value of the register before + * the update will be returned. + */ +typedef struct { + uint64_t error:1; + int32_t value:31; +} cvmx_fau_tagwait32_t; + +/** + * Tagwait return definition. If a timeout occurs, the error + * bit will be set. Otherwise the value of the register before + * the update will be returned. + */ +typedef struct { + uint64_t error:1; + int16_t value:15; +} cvmx_fau_tagwait16_t; + +/** + * Tagwait return definition. If a timeout occurs, the error + * bit will be set. Otherwise the value of the register before + * the update will be returned. + */ +typedef struct { + uint64_t error:1; + int8_t value:7; +} cvmx_fau_tagwait8_t; + +/** + * Asynchronous tagwait return definition. If a timeout occurs, + * the error bit will be set. Otherwise the value of the + * register before the update will be returned. + */ +typedef union { + uint64_t u64; + struct { + uint64_t invalid:1; + uint64_t data:63; /* unpredictable if invalid is set */ + } s; +} cvmx_fau_async_tagwait_result_t; + +/** + * Builds a store I/O address for writing to the FAU + * + * @noadd: 0 = Store value is atomically added to the current value + * 1 = Store value is atomically written over the current value + * @reg: FAU atomic register to access. 0 <= reg < 2048. + * - Step by 2 for 16 bit access. + * - Step by 4 for 32 bit access. + * - Step by 8 for 64 bit access. + * Returns Address to store for atomic update + */ +static inline uint64_t __cvmx_fau_store_address(uint64_t noadd, uint64_t reg) +{ + return CVMX_ADD_IO_SEG(CVMX_FAU_LOAD_IO_ADDRESS) | + cvmx_build_bits(CVMX_FAU_BITS_NOADD, noadd) | + cvmx_build_bits(CVMX_FAU_BITS_REGISTER, reg); +} + +/** + * Builds a I/O address for accessing the FAU + * + * @tagwait: Should the atomic add wait for the current tag switch + * operation to complete. + * - 0 = Don't wait + * - 1 = Wait for tag switch to complete + * @reg: FAU atomic register to access. 0 <= reg < 2048. + * - Step by 2 for 16 bit access. + * - Step by 4 for 32 bit access. + * - Step by 8 for 64 bit access. + * @value: Signed value to add. + * Note: When performing 32 and 64 bit access, only the low + * 22 bits are available. + * Returns Address to read from for atomic update + */ +static inline uint64_t __cvmx_fau_atomic_address(uint64_t tagwait, uint64_t reg, + int64_t value) +{ + return CVMX_ADD_IO_SEG(CVMX_FAU_LOAD_IO_ADDRESS) | + cvmx_build_bits(CVMX_FAU_BITS_INEVAL, value) | + cvmx_build_bits(CVMX_FAU_BITS_TAGWAIT, tagwait) | + cvmx_build_bits(CVMX_FAU_BITS_REGISTER, reg); +} + +/** + * Perform an atomic 64 bit add + * + * @reg: FAU atomic register to access. 0 <= reg < 2048. + * - Step by 8 for 64 bit access. + * @value: Signed value to add. + * Note: Only the low 22 bits are available. + * Returns Value of the register before the update + */ +static inline int64_t cvmx_fau_fetch_and_add64(cvmx_fau_reg_64_t reg, + int64_t value) +{ + return cvmx_read64_int64(__cvmx_fau_atomic_address(0, reg, value)); +} + +/** + * Perform an atomic 32 bit add + * + * @reg: FAU atomic register to access. 0 <= reg < 2048. + * - Step by 4 for 32 bit access. + * @value: Signed value to add. + * Note: Only the low 22 bits are available. + * Returns Value of the register before the update + */ +static inline int32_t cvmx_fau_fetch_and_add32(cvmx_fau_reg_32_t reg, + int32_t value) +{ + return cvmx_read64_int32(__cvmx_fau_atomic_address(0, reg, value)); +} + +/** + * Perform an atomic 16 bit add + * + * @reg: FAU atomic register to access. 0 <= reg < 2048. + * - Step by 2 for 16 bit access. + * @value: Signed value to add. + * Returns Value of the register before the update + */ +static inline int16_t cvmx_fau_fetch_and_add16(cvmx_fau_reg_16_t reg, + int16_t value) +{ + return cvmx_read64_int16(__cvmx_fau_atomic_address(0, reg, value)); +} + +/** + * Perform an atomic 8 bit add + * + * @reg: FAU atomic register to access. 0 <= reg < 2048. + * @value: Signed value to add. + * Returns Value of the register before the update + */ +static inline int8_t cvmx_fau_fetch_and_add8(cvmx_fau_reg_8_t reg, int8_t value) +{ + return cvmx_read64_int8(__cvmx_fau_atomic_address(0, reg, value)); +} + +/** + * Perform an atomic 64 bit add after the current tag switch + * completes + * + * @reg: FAU atomic register to access. 0 <= reg < 2048. + * - Step by 8 for 64 bit access. + * @value: Signed value to add. + * Note: Only the low 22 bits are available. + * Returns If a timeout occurs, the error bit will be set. Otherwise + * the value of the register before the update will be + * returned + */ +static inline cvmx_fau_tagwait64_t +cvmx_fau_tagwait_fetch_and_add64(cvmx_fau_reg_64_t reg, int64_t value) +{ + union { + uint64_t i64; + cvmx_fau_tagwait64_t t; + } result; + result.i64 = + cvmx_read64_int64(__cvmx_fau_atomic_address(1, reg, value)); + return result.t; +} + +/** + * Perform an atomic 32 bit add after the current tag switch + * completes + * + * @reg: FAU atomic register to access. 0 <= reg < 2048. + * - Step by 4 for 32 bit access. + * @value: Signed value to add. + * Note: Only the low 22 bits are available. + * Returns If a timeout occurs, the error bit will be set. Otherwise + * the value of the register before the update will be + * returned + */ +static inline cvmx_fau_tagwait32_t +cvmx_fau_tagwait_fetch_and_add32(cvmx_fau_reg_32_t reg, int32_t value) +{ + union { + uint64_t i32; + cvmx_fau_tagwait32_t t; + } result; + result.i32 = + cvmx_read64_int32(__cvmx_fau_atomic_address(1, reg, value)); + return result.t; +} + +/** + * Perform an atomic 16 bit add after the current tag switch + * completes + * + * @reg: FAU atomic register to access. 0 <= reg < 2048. + * - Step by 2 for 16 bit access. + * @value: Signed value to add. + * Returns If a timeout occurs, the error bit will be set. Otherwise + * the value of the register before the update will be + * returned + */ +static inline cvmx_fau_tagwait16_t +cvmx_fau_tagwait_fetch_and_add16(cvmx_fau_reg_16_t reg, int16_t value) +{ + union { + uint64_t i16; + cvmx_fau_tagwait16_t t; + } result; + result.i16 = + cvmx_read64_int16(__cvmx_fau_atomic_address(1, reg, value)); + return result.t; +} + +/** + * Perform an atomic 8 bit add after the current tag switch + * completes + * + * @reg: FAU atomic register to access. 0 <= reg < 2048. + * @value: Signed value to add. + * Returns If a timeout occurs, the error bit will be set. Otherwise + * the value of the register before the update will be + * returned + */ +static inline cvmx_fau_tagwait8_t +cvmx_fau_tagwait_fetch_and_add8(cvmx_fau_reg_8_t reg, int8_t value) +{ + union { + uint64_t i8; + cvmx_fau_tagwait8_t t; + } result; + result.i8 = cvmx_read64_int8(__cvmx_fau_atomic_address(1, reg, value)); + return result.t; +} + +/** + * Builds I/O data for async operations + * + * @scraddr: Scratch pad byte addres to write to. Must be 8 byte aligned + * @value: Signed value to add. + * Note: When performing 32 and 64 bit access, only the low + * 22 bits are available. + * @tagwait: Should the atomic add wait for the current tag switch + * operation to complete. + * - 0 = Don't wait + * - 1 = Wait for tag switch to complete + * @size: The size of the operation: + * - CVMX_FAU_OP_SIZE_8 (0) = 8 bits + * - CVMX_FAU_OP_SIZE_16 (1) = 16 bits + * - CVMX_FAU_OP_SIZE_32 (2) = 32 bits + * - CVMX_FAU_OP_SIZE_64 (3) = 64 bits + * @reg: FAU atomic register to access. 0 <= reg < 2048. + * - Step by 2 for 16 bit access. + * - Step by 4 for 32 bit access. + * - Step by 8 for 64 bit access. + * Returns Data to write using cvmx_send_single + */ +static inline uint64_t __cvmx_fau_iobdma_data(uint64_t scraddr, int64_t value, + uint64_t tagwait, + cvmx_fau_op_size_t size, + uint64_t reg) +{ + return CVMX_FAU_LOAD_IO_ADDRESS | + cvmx_build_bits(CVMX_FAU_BITS_SCRADDR, scraddr >> 3) | + cvmx_build_bits(CVMX_FAU_BITS_LEN, 1) | + cvmx_build_bits(CVMX_FAU_BITS_INEVAL, value) | + cvmx_build_bits(CVMX_FAU_BITS_TAGWAIT, tagwait) | + cvmx_build_bits(CVMX_FAU_BITS_SIZE, size) | + cvmx_build_bits(CVMX_FAU_BITS_REGISTER, reg); +} + +/** + * Perform an async atomic 64 bit add. The old value is + * placed in the scratch memory at byte address scraddr. + * + * @scraddr: Scratch memory byte address to put response in. + * Must be 8 byte aligned. + * @reg: FAU atomic register to access. 0 <= reg < 2048. + * - Step by 8 for 64 bit access. + * @value: Signed value to add. + * Note: Only the low 22 bits are available. + * Returns Placed in the scratch pad register + */ +static inline void cvmx_fau_async_fetch_and_add64(uint64_t scraddr, + cvmx_fau_reg_64_t reg, + int64_t value) +{ + cvmx_send_single(__cvmx_fau_iobdma_data + (scraddr, value, 0, CVMX_FAU_OP_SIZE_64, reg)); +} + +/** + * Perform an async atomic 32 bit add. The old value is + * placed in the scratch memory at byte address scraddr. + * + * @scraddr: Scratch memory byte address to put response in. + * Must be 8 byte aligned. + * @reg: FAU atomic register to access. 0 <= reg < 2048. + * - Step by 4 for 32 bit access. + * @value: Signed value to add. + * Note: Only the low 22 bits are available. + * Returns Placed in the scratch pad register + */ +static inline void cvmx_fau_async_fetch_and_add32(uint64_t scraddr, + cvmx_fau_reg_32_t reg, + int32_t value) +{ + cvmx_send_single(__cvmx_fau_iobdma_data + (scraddr, value, 0, CVMX_FAU_OP_SIZE_32, reg)); +} + +/** + * Perform an async atomic 16 bit add. The old value is + * placed in the scratch memory at byte address scraddr. + * + * @scraddr: Scratch memory byte address to put response in. + * Must be 8 byte aligned. + * @reg: FAU atomic register to access. 0 <= reg < 2048. + * - Step by 2 for 16 bit access. + * @value: Signed value to add. + * Returns Placed in the scratch pad register + */ +static inline void cvmx_fau_async_fetch_and_add16(uint64_t scraddr, + cvmx_fau_reg_16_t reg, + int16_t value) +{ + cvmx_send_single(__cvmx_fau_iobdma_data + (scraddr, value, 0, CVMX_FAU_OP_SIZE_16, reg)); +} + +/** + * Perform an async atomic 8 bit add. The old value is + * placed in the scratch memory at byte address scraddr. + * + * @scraddr: Scratch memory byte address to put response in. + * Must be 8 byte aligned. + * @reg: FAU atomic register to access. 0 <= reg < 2048. + * @value: Signed value to add. + * Returns Placed in the scratch pad register + */ +static inline void cvmx_fau_async_fetch_and_add8(uint64_t scraddr, + cvmx_fau_reg_8_t reg, + int8_t value) +{ + cvmx_send_single(__cvmx_fau_iobdma_data + (scraddr, value, 0, CVMX_FAU_OP_SIZE_8, reg)); +} + +/** + * Perform an async atomic 64 bit add after the current tag + * switch completes. + * + * @scraddr: Scratch memory byte address to put response in. Must be + * 8 byte aligned. If a timeout occurs, the error bit (63) + * will be set. Otherwise the value of the register before + * the update will be returned + * + * @reg: FAU atomic register to access. 0 <= reg < 2048. + * - Step by 8 for 64 bit access. + * @value: Signed value to add. + * Note: Only the low 22 bits are available. + * Returns Placed in the scratch pad register + */ +static inline void cvmx_fau_async_tagwait_fetch_and_add64(uint64_t scraddr, + cvmx_fau_reg_64_t reg, + int64_t value) +{ + cvmx_send_single(__cvmx_fau_iobdma_data + (scraddr, value, 1, CVMX_FAU_OP_SIZE_64, reg)); +} + +/** + * Perform an async atomic 32 bit add after the current tag + * switch completes. + * + * @scraddr: Scratch memory byte address to put response in. Must be + * 8 byte aligned. If a timeout occurs, the error bit (63) + * will be set. Otherwise the value of the register before + * the update will be returned + * + * @reg: FAU atomic register to access. 0 <= reg < 2048. + * - Step by 4 for 32 bit access. + * @value: Signed value to add. + * Note: Only the low 22 bits are available. + * Returns Placed in the scratch pad register + */ +static inline void cvmx_fau_async_tagwait_fetch_and_add32(uint64_t scraddr, + cvmx_fau_reg_32_t reg, + int32_t value) +{ + cvmx_send_single(__cvmx_fau_iobdma_data + (scraddr, value, 1, CVMX_FAU_OP_SIZE_32, reg)); +} + +/** + * Perform an async atomic 16 bit add after the current tag + * switch completes. + * + * @scraddr: Scratch memory byte address to put response in. Must be + * 8 byte aligned. If a timeout occurs, the error bit (63) + * will be set. Otherwise the value of the register before + * the update will be returned + * + * @reg: FAU atomic register to access. 0 <= reg < 2048. + * - Step by 2 for 16 bit access. + * @value: Signed value to add. + * + * Returns Placed in the scratch pad register + */ +static inline void cvmx_fau_async_tagwait_fetch_and_add16(uint64_t scraddr, + cvmx_fau_reg_16_t reg, + int16_t value) +{ + cvmx_send_single(__cvmx_fau_iobdma_data + (scraddr, value, 1, CVMX_FAU_OP_SIZE_16, reg)); +} + +/** + * Perform an async atomic 8 bit add after the current tag + * switch completes. + * + * @scraddr: Scratch memory byte address to put response in. Must be + * 8 byte aligned. If a timeout occurs, the error bit (63) + * will be set. Otherwise the value of the register before + * the update will be returned + * + * @reg: FAU atomic register to access. 0 <= reg < 2048. + * @value: Signed value to add. + * + * Returns Placed in the scratch pad register + */ +static inline void cvmx_fau_async_tagwait_fetch_and_add8(uint64_t scraddr, + cvmx_fau_reg_8_t reg, + int8_t value) +{ + cvmx_send_single(__cvmx_fau_iobdma_data + (scraddr, value, 1, CVMX_FAU_OP_SIZE_8, reg)); +} + +/** + * Perform an atomic 64 bit add + * + * @reg: FAU atomic register to access. 0 <= reg < 2048. + * - Step by 8 for 64 bit access. + * @value: Signed value to add. + */ +static inline void cvmx_fau_atomic_add64(cvmx_fau_reg_64_t reg, int64_t value) +{ + cvmx_write64_int64(__cvmx_fau_store_address(0, reg), value); +} + +/** + * Perform an atomic 32 bit add + * + * @reg: FAU atomic register to access. 0 <= reg < 2048. + * - Step by 4 for 32 bit access. + * @value: Signed value to add. + */ +static inline void cvmx_fau_atomic_add32(cvmx_fau_reg_32_t reg, int32_t value) +{ + cvmx_write64_int32(__cvmx_fau_store_address(0, reg), value); +} + +/** + * Perform an atomic 16 bit add + * + * @reg: FAU atomic register to access. 0 <= reg < 2048. + * - Step by 2 for 16 bit access. + * @value: Signed value to add. + */ +static inline void cvmx_fau_atomic_add16(cvmx_fau_reg_16_t reg, int16_t value) +{ + cvmx_write64_int16(__cvmx_fau_store_address(0, reg), value); +} + +/** + * Perform an atomic 8 bit add + * + * @reg: FAU atomic register to access. 0 <= reg < 2048. + * @value: Signed value to add. + */ +static inline void cvmx_fau_atomic_add8(cvmx_fau_reg_8_t reg, int8_t value) +{ + cvmx_write64_int8(__cvmx_fau_store_address(0, reg), value); +} + +/** + * Perform an atomic 64 bit write + * + * @reg: FAU atomic register to access. 0 <= reg < 2048. + * - Step by 8 for 64 bit access. + * @value: Signed value to write. + */ +static inline void cvmx_fau_atomic_write64(cvmx_fau_reg_64_t reg, int64_t value) +{ + cvmx_write64_int64(__cvmx_fau_store_address(1, reg), value); +} + +/** + * Perform an atomic 32 bit write + * + * @reg: FAU atomic register to access. 0 <= reg < 2048. + * - Step by 4 for 32 bit access. + * @value: Signed value to write. + */ +static inline void cvmx_fau_atomic_write32(cvmx_fau_reg_32_t reg, int32_t value) +{ + cvmx_write64_int32(__cvmx_fau_store_address(1, reg), value); +} + +/** + * Perform an atomic 16 bit write + * + * @reg: FAU atomic register to access. 0 <= reg < 2048. + * - Step by 2 for 16 bit access. + * @value: Signed value to write. + */ +static inline void cvmx_fau_atomic_write16(cvmx_fau_reg_16_t reg, int16_t value) +{ + cvmx_write64_int16(__cvmx_fau_store_address(1, reg), value); +} + +/** + * Perform an atomic 8 bit write + * + * @reg: FAU atomic register to access. 0 <= reg < 2048. + * @value: Signed value to write. + */ +static inline void cvmx_fau_atomic_write8(cvmx_fau_reg_8_t reg, int8_t value) +{ + cvmx_write64_int8(__cvmx_fau_store_address(1, reg), value); +} + +#endif /* __CVMX_FAU_H__ */ diff --git a/drivers/staging/octeon/cvmx-fpa-defs.h b/drivers/staging/octeon/cvmx-fpa-defs.h new file mode 100644 index 0000000..bf5546b --- /dev/null +++ b/drivers/staging/octeon/cvmx-fpa-defs.h @@ -0,0 +1,403 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * along with this file; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +#ifndef __CVMX_FPA_DEFS_H__ +#define __CVMX_FPA_DEFS_H__ + +#define CVMX_FPA_BIST_STATUS \ + CVMX_ADD_IO_SEG(0x00011800280000E8ull) +#define CVMX_FPA_CTL_STATUS \ + CVMX_ADD_IO_SEG(0x0001180028000050ull) +#define CVMX_FPA_FPF0_MARKS \ + CVMX_ADD_IO_SEG(0x0001180028000000ull) +#define CVMX_FPA_FPF0_SIZE \ + CVMX_ADD_IO_SEG(0x0001180028000058ull) +#define CVMX_FPA_FPF1_MARKS \ + CVMX_ADD_IO_SEG(0x0001180028000008ull) +#define CVMX_FPA_FPF2_MARKS \ + CVMX_ADD_IO_SEG(0x0001180028000010ull) +#define CVMX_FPA_FPF3_MARKS \ + CVMX_ADD_IO_SEG(0x0001180028000018ull) +#define CVMX_FPA_FPF4_MARKS \ + CVMX_ADD_IO_SEG(0x0001180028000020ull) +#define CVMX_FPA_FPF5_MARKS \ + CVMX_ADD_IO_SEG(0x0001180028000028ull) +#define CVMX_FPA_FPF6_MARKS \ + CVMX_ADD_IO_SEG(0x0001180028000030ull) +#define CVMX_FPA_FPF7_MARKS \ + CVMX_ADD_IO_SEG(0x0001180028000038ull) +#define CVMX_FPA_FPFX_MARKS(offset) \ + CVMX_ADD_IO_SEG(0x0001180028000008ull + (((offset) & 7) * 8) - 8 * 1) +#define CVMX_FPA_FPFX_SIZE(offset) \ + CVMX_ADD_IO_SEG(0x0001180028000060ull + (((offset) & 7) * 8) - 8 * 1) +#define CVMX_FPA_INT_ENB \ + CVMX_ADD_IO_SEG(0x0001180028000048ull) +#define CVMX_FPA_INT_SUM \ + CVMX_ADD_IO_SEG(0x0001180028000040ull) +#define CVMX_FPA_QUE0_PAGE_INDEX \ + CVMX_ADD_IO_SEG(0x00011800280000F0ull) +#define CVMX_FPA_QUE1_PAGE_INDEX \ + CVMX_ADD_IO_SEG(0x00011800280000F8ull) +#define CVMX_FPA_QUE2_PAGE_INDEX \ + CVMX_ADD_IO_SEG(0x0001180028000100ull) +#define CVMX_FPA_QUE3_PAGE_INDEX \ + CVMX_ADD_IO_SEG(0x0001180028000108ull) +#define CVMX_FPA_QUE4_PAGE_INDEX \ + CVMX_ADD_IO_SEG(0x0001180028000110ull) +#define CVMX_FPA_QUE5_PAGE_INDEX \ + CVMX_ADD_IO_SEG(0x0001180028000118ull) +#define CVMX_FPA_QUE6_PAGE_INDEX \ + CVMX_ADD_IO_SEG(0x0001180028000120ull) +#define CVMX_FPA_QUE7_PAGE_INDEX \ + CVMX_ADD_IO_SEG(0x0001180028000128ull) +#define CVMX_FPA_QUEX_AVAILABLE(offset) \ + CVMX_ADD_IO_SEG(0x0001180028000098ull + (((offset) & 7) * 8)) +#define CVMX_FPA_QUEX_PAGE_INDEX(offset) \ + CVMX_ADD_IO_SEG(0x00011800280000F0ull + (((offset) & 7) * 8)) +#define CVMX_FPA_QUE_ACT \ + CVMX_ADD_IO_SEG(0x0001180028000138ull) +#define CVMX_FPA_QUE_EXP \ + CVMX_ADD_IO_SEG(0x0001180028000130ull) +#define CVMX_FPA_WART_CTL \ + CVMX_ADD_IO_SEG(0x00011800280000D8ull) +#define CVMX_FPA_WART_STATUS \ + CVMX_ADD_IO_SEG(0x00011800280000E0ull) + +union cvmx_fpa_bist_status { + uint64_t u64; + struct cvmx_fpa_bist_status_s { + uint64_t reserved_5_63:59; + uint64_t frd:1; + uint64_t fpf0:1; + uint64_t fpf1:1; + uint64_t ffr:1; + uint64_t fdr:1; + } s; + struct cvmx_fpa_bist_status_s cn30xx; + struct cvmx_fpa_bist_status_s cn31xx; + struct cvmx_fpa_bist_status_s cn38xx; + struct cvmx_fpa_bist_status_s cn38xxp2; + struct cvmx_fpa_bist_status_s cn50xx; + struct cvmx_fpa_bist_status_s cn52xx; + struct cvmx_fpa_bist_status_s cn52xxp1; + struct cvmx_fpa_bist_status_s cn56xx; + struct cvmx_fpa_bist_status_s cn56xxp1; + struct cvmx_fpa_bist_status_s cn58xx; + struct cvmx_fpa_bist_status_s cn58xxp1; +}; + +union cvmx_fpa_ctl_status { + uint64_t u64; + struct cvmx_fpa_ctl_status_s { + uint64_t reserved_18_63:46; + uint64_t reset:1; + uint64_t use_ldt:1; + uint64_t use_stt:1; + uint64_t enb:1; + uint64_t mem1_err:7; + uint64_t mem0_err:7; + } s; + struct cvmx_fpa_ctl_status_s cn30xx; + struct cvmx_fpa_ctl_status_s cn31xx; + struct cvmx_fpa_ctl_status_s cn38xx; + struct cvmx_fpa_ctl_status_s cn38xxp2; + struct cvmx_fpa_ctl_status_s cn50xx; + struct cvmx_fpa_ctl_status_s cn52xx; + struct cvmx_fpa_ctl_status_s cn52xxp1; + struct cvmx_fpa_ctl_status_s cn56xx; + struct cvmx_fpa_ctl_status_s cn56xxp1; + struct cvmx_fpa_ctl_status_s cn58xx; + struct cvmx_fpa_ctl_status_s cn58xxp1; +}; + +union cvmx_fpa_fpfx_marks { + uint64_t u64; + struct cvmx_fpa_fpfx_marks_s { + uint64_t reserved_22_63:42; + uint64_t fpf_wr:11; + uint64_t fpf_rd:11; + } s; + struct cvmx_fpa_fpfx_marks_s cn38xx; + struct cvmx_fpa_fpfx_marks_s cn38xxp2; + struct cvmx_fpa_fpfx_marks_s cn56xx; + struct cvmx_fpa_fpfx_marks_s cn56xxp1; + struct cvmx_fpa_fpfx_marks_s cn58xx; + struct cvmx_fpa_fpfx_marks_s cn58xxp1; +}; + +union cvmx_fpa_fpfx_size { + uint64_t u64; + struct cvmx_fpa_fpfx_size_s { + uint64_t reserved_11_63:53; + uint64_t fpf_siz:11; + } s; + struct cvmx_fpa_fpfx_size_s cn38xx; + struct cvmx_fpa_fpfx_size_s cn38xxp2; + struct cvmx_fpa_fpfx_size_s cn56xx; + struct cvmx_fpa_fpfx_size_s cn56xxp1; + struct cvmx_fpa_fpfx_size_s cn58xx; + struct cvmx_fpa_fpfx_size_s cn58xxp1; +}; + +union cvmx_fpa_fpf0_marks { + uint64_t u64; + struct cvmx_fpa_fpf0_marks_s { + uint64_t reserved_24_63:40; + uint64_t fpf_wr:12; + uint64_t fpf_rd:12; + } s; + struct cvmx_fpa_fpf0_marks_s cn38xx; + struct cvmx_fpa_fpf0_marks_s cn38xxp2; + struct cvmx_fpa_fpf0_marks_s cn56xx; + struct cvmx_fpa_fpf0_marks_s cn56xxp1; + struct cvmx_fpa_fpf0_marks_s cn58xx; + struct cvmx_fpa_fpf0_marks_s cn58xxp1; +}; + +union cvmx_fpa_fpf0_size { + uint64_t u64; + struct cvmx_fpa_fpf0_size_s { + uint64_t reserved_12_63:52; + uint64_t fpf_siz:12; + } s; + struct cvmx_fpa_fpf0_size_s cn38xx; + struct cvmx_fpa_fpf0_size_s cn38xxp2; + struct cvmx_fpa_fpf0_size_s cn56xx; + struct cvmx_fpa_fpf0_size_s cn56xxp1; + struct cvmx_fpa_fpf0_size_s cn58xx; + struct cvmx_fpa_fpf0_size_s cn58xxp1; +}; + +union cvmx_fpa_int_enb { + uint64_t u64; + struct cvmx_fpa_int_enb_s { + uint64_t reserved_28_63:36; + uint64_t q7_perr:1; + uint64_t q7_coff:1; + uint64_t q7_und:1; + uint64_t q6_perr:1; + uint64_t q6_coff:1; + uint64_t q6_und:1; + uint64_t q5_perr:1; + uint64_t q5_coff:1; + uint64_t q5_und:1; + uint64_t q4_perr:1; + uint64_t q4_coff:1; + uint64_t q4_und:1; + uint64_t q3_perr:1; + uint64_t q3_coff:1; + uint64_t q3_und:1; + uint64_t q2_perr:1; + uint64_t q2_coff:1; + uint64_t q2_und:1; + uint64_t q1_perr:1; + uint64_t q1_coff:1; + uint64_t q1_und:1; + uint64_t q0_perr:1; + uint64_t q0_coff:1; + uint64_t q0_und:1; + uint64_t fed1_dbe:1; + uint64_t fed1_sbe:1; + uint64_t fed0_dbe:1; + uint64_t fed0_sbe:1; + } s; + struct cvmx_fpa_int_enb_s cn30xx; + struct cvmx_fpa_int_enb_s cn31xx; + struct cvmx_fpa_int_enb_s cn38xx; + struct cvmx_fpa_int_enb_s cn38xxp2; + struct cvmx_fpa_int_enb_s cn50xx; + struct cvmx_fpa_int_enb_s cn52xx; + struct cvmx_fpa_int_enb_s cn52xxp1; + struct cvmx_fpa_int_enb_s cn56xx; + struct cvmx_fpa_int_enb_s cn56xxp1; + struct cvmx_fpa_int_enb_s cn58xx; + struct cvmx_fpa_int_enb_s cn58xxp1; +}; + +union cvmx_fpa_int_sum { + uint64_t u64; + struct cvmx_fpa_int_sum_s { + uint64_t reserved_28_63:36; + uint64_t q7_perr:1; + uint64_t q7_coff:1; + uint64_t q7_und:1; + uint64_t q6_perr:1; + uint64_t q6_coff:1; + uint64_t q6_und:1; + uint64_t q5_perr:1; + uint64_t q5_coff:1; + uint64_t q5_und:1; + uint64_t q4_perr:1; + uint64_t q4_coff:1; + uint64_t q4_und:1; + uint64_t q3_perr:1; + uint64_t q3_coff:1; + uint64_t q3_und:1; + uint64_t q2_perr:1; + uint64_t q2_coff:1; + uint64_t q2_und:1; + uint64_t q1_perr:1; + uint64_t q1_coff:1; + uint64_t q1_und:1; + uint64_t q0_perr:1; + uint64_t q0_coff:1; + uint64_t q0_und:1; + uint64_t fed1_dbe:1; + uint64_t fed1_sbe:1; + uint64_t fed0_dbe:1; + uint64_t fed0_sbe:1; + } s; + struct cvmx_fpa_int_sum_s cn30xx; + struct cvmx_fpa_int_sum_s cn31xx; + struct cvmx_fpa_int_sum_s cn38xx; + struct cvmx_fpa_int_sum_s cn38xxp2; + struct cvmx_fpa_int_sum_s cn50xx; + struct cvmx_fpa_int_sum_s cn52xx; + struct cvmx_fpa_int_sum_s cn52xxp1; + struct cvmx_fpa_int_sum_s cn56xx; + struct cvmx_fpa_int_sum_s cn56xxp1; + struct cvmx_fpa_int_sum_s cn58xx; + struct cvmx_fpa_int_sum_s cn58xxp1; +}; + +union cvmx_fpa_quex_available { + uint64_t u64; + struct cvmx_fpa_quex_available_s { + uint64_t reserved_29_63:35; + uint64_t que_siz:29; + } s; + struct cvmx_fpa_quex_available_s cn30xx; + struct cvmx_fpa_quex_available_s cn31xx; + struct cvmx_fpa_quex_available_s cn38xx; + struct cvmx_fpa_quex_available_s cn38xxp2; + struct cvmx_fpa_quex_available_s cn50xx; + struct cvmx_fpa_quex_available_s cn52xx; + struct cvmx_fpa_quex_available_s cn52xxp1; + struct cvmx_fpa_quex_available_s cn56xx; + struct cvmx_fpa_quex_available_s cn56xxp1; + struct cvmx_fpa_quex_available_s cn58xx; + struct cvmx_fpa_quex_available_s cn58xxp1; +}; + +union cvmx_fpa_quex_page_index { + uint64_t u64; + struct cvmx_fpa_quex_page_index_s { + uint64_t reserved_25_63:39; + uint64_t pg_num:25; + } s; + struct cvmx_fpa_quex_page_index_s cn30xx; + struct cvmx_fpa_quex_page_index_s cn31xx; + struct cvmx_fpa_quex_page_index_s cn38xx; + struct cvmx_fpa_quex_page_index_s cn38xxp2; + struct cvmx_fpa_quex_page_index_s cn50xx; + struct cvmx_fpa_quex_page_index_s cn52xx; + struct cvmx_fpa_quex_page_index_s cn52xxp1; + struct cvmx_fpa_quex_page_index_s cn56xx; + struct cvmx_fpa_quex_page_index_s cn56xxp1; + struct cvmx_fpa_quex_page_index_s cn58xx; + struct cvmx_fpa_quex_page_index_s cn58xxp1; +}; + +union cvmx_fpa_que_act { + uint64_t u64; + struct cvmx_fpa_que_act_s { + uint64_t reserved_29_63:35; + uint64_t act_que:3; + uint64_t act_indx:26; + } s; + struct cvmx_fpa_que_act_s cn30xx; + struct cvmx_fpa_que_act_s cn31xx; + struct cvmx_fpa_que_act_s cn38xx; + struct cvmx_fpa_que_act_s cn38xxp2; + struct cvmx_fpa_que_act_s cn50xx; + struct cvmx_fpa_que_act_s cn52xx; + struct cvmx_fpa_que_act_s cn52xxp1; + struct cvmx_fpa_que_act_s cn56xx; + struct cvmx_fpa_que_act_s cn56xxp1; + struct cvmx_fpa_que_act_s cn58xx; + struct cvmx_fpa_que_act_s cn58xxp1; +}; + +union cvmx_fpa_que_exp { + uint64_t u64; + struct cvmx_fpa_que_exp_s { + uint64_t reserved_29_63:35; + uint64_t exp_que:3; + uint64_t exp_indx:26; + } s; + struct cvmx_fpa_que_exp_s cn30xx; + struct cvmx_fpa_que_exp_s cn31xx; + struct cvmx_fpa_que_exp_s cn38xx; + struct cvmx_fpa_que_exp_s cn38xxp2; + struct cvmx_fpa_que_exp_s cn50xx; + struct cvmx_fpa_que_exp_s cn52xx; + struct cvmx_fpa_que_exp_s cn52xxp1; + struct cvmx_fpa_que_exp_s cn56xx; + struct cvmx_fpa_que_exp_s cn56xxp1; + struct cvmx_fpa_que_exp_s cn58xx; + struct cvmx_fpa_que_exp_s cn58xxp1; +}; + +union cvmx_fpa_wart_ctl { + uint64_t u64; + struct cvmx_fpa_wart_ctl_s { + uint64_t reserved_16_63:48; + uint64_t ctl:16; + } s; + struct cvmx_fpa_wart_ctl_s cn30xx; + struct cvmx_fpa_wart_ctl_s cn31xx; + struct cvmx_fpa_wart_ctl_s cn38xx; + struct cvmx_fpa_wart_ctl_s cn38xxp2; + struct cvmx_fpa_wart_ctl_s cn50xx; + struct cvmx_fpa_wart_ctl_s cn52xx; + struct cvmx_fpa_wart_ctl_s cn52xxp1; + struct cvmx_fpa_wart_ctl_s cn56xx; + struct cvmx_fpa_wart_ctl_s cn56xxp1; + struct cvmx_fpa_wart_ctl_s cn58xx; + struct cvmx_fpa_wart_ctl_s cn58xxp1; +}; + +union cvmx_fpa_wart_status { + uint64_t u64; + struct cvmx_fpa_wart_status_s { + uint64_t reserved_32_63:32; + uint64_t status:32; + } s; + struct cvmx_fpa_wart_status_s cn30xx; + struct cvmx_fpa_wart_status_s cn31xx; + struct cvmx_fpa_wart_status_s cn38xx; + struct cvmx_fpa_wart_status_s cn38xxp2; + struct cvmx_fpa_wart_status_s cn50xx; + struct cvmx_fpa_wart_status_s cn52xx; + struct cvmx_fpa_wart_status_s cn52xxp1; + struct cvmx_fpa_wart_status_s cn56xx; + struct cvmx_fpa_wart_status_s cn56xxp1; + struct cvmx_fpa_wart_status_s cn58xx; + struct cvmx_fpa_wart_status_s cn58xxp1; +}; + +#endif diff --git a/drivers/staging/octeon/cvmx-fpa.c b/drivers/staging/octeon/cvmx-fpa.c new file mode 100644 index 0000000..55d9147 --- /dev/null +++ b/drivers/staging/octeon/cvmx-fpa.c @@ -0,0 +1,183 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * along with this file; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +/** + * @file + * + * Support library for the hardware Free Pool Allocator. + * + * + */ + +#include "cvmx-config.h" +#include "cvmx.h" +#include "cvmx-fpa.h" +#include "cvmx-ipd.h" + +/** + * Current state of all the pools. Use access functions + * instead of using it directly. + */ +CVMX_SHARED cvmx_fpa_pool_info_t cvmx_fpa_pool_info[CVMX_FPA_NUM_POOLS]; + +/** + * Setup a FPA pool to control a new block of memory. The + * buffer pointer must be a physical address. + * + * @pool: Pool to initialize + * 0 <= pool < 8 + * @name: Constant character string to name this pool. + * String is not copied. + * @buffer: Pointer to the block of memory to use. This must be + * accessable by all processors and external hardware. + * @block_size: Size for each block controlled by the FPA + * @num_blocks: Number of blocks + * + * Returns 0 on Success, + * -1 on failure + */ +int cvmx_fpa_setup_pool(uint64_t pool, const char *name, void *buffer, + uint64_t block_size, uint64_t num_blocks) +{ + char *ptr; + if (!buffer) { + cvmx_dprintf + ("ERROR: cvmx_fpa_setup_pool: NULL buffer pointer!\n"); + return -1; + } + if (pool >= CVMX_FPA_NUM_POOLS) { + cvmx_dprintf("ERROR: cvmx_fpa_setup_pool: Illegal pool!\n"); + return -1; + } + + if (block_size < CVMX_FPA_MIN_BLOCK_SIZE) { + cvmx_dprintf + ("ERROR: cvmx_fpa_setup_pool: Block size too small.\n"); + return -1; + } + + if (((unsigned long)buffer & (CVMX_FPA_ALIGNMENT - 1)) != 0) { + cvmx_dprintf + ("ERROR: cvmx_fpa_setup_pool: Buffer not aligned properly.\n"); + return -1; + } + + cvmx_fpa_pool_info[pool].name = name; + cvmx_fpa_pool_info[pool].size = block_size; + cvmx_fpa_pool_info[pool].starting_element_count = num_blocks; + cvmx_fpa_pool_info[pool].base = buffer; + + ptr = (char *)buffer; + while (num_blocks--) { + cvmx_fpa_free(ptr, pool, 0); + ptr += block_size; + } + return 0; +} + +/** + * Shutdown a Memory pool and validate that it had all of + * the buffers originally placed in it. + * + * @pool: Pool to shutdown + * Returns Zero on success + * - Positive is count of missing buffers + * - Negative is too many buffers or corrupted pointers + */ +uint64_t cvmx_fpa_shutdown_pool(uint64_t pool) +{ + uint64_t errors = 0; + uint64_t count = 0; + uint64_t base = cvmx_ptr_to_phys(cvmx_fpa_pool_info[pool].base); + uint64_t finish = + base + + cvmx_fpa_pool_info[pool].size * + cvmx_fpa_pool_info[pool].starting_element_count; + void *ptr; + uint64_t address; + + count = 0; + do { + ptr = cvmx_fpa_alloc(pool); + if (ptr) + address = cvmx_ptr_to_phys(ptr); + else + address = 0; + if (address) { + if ((address >= base) && (address < finish) && + (((address - + base) % cvmx_fpa_pool_info[pool].size) == 0)) { + count++; + } else { + cvmx_dprintf + ("ERROR: cvmx_fpa_shutdown_pool: Illegal address 0x%llx in pool %s(%d)\n", + (unsigned long long)address, + cvmx_fpa_pool_info[pool].name, (int)pool); + errors++; + } + } + } while (address); + +#ifdef CVMX_ENABLE_PKO_FUNCTIONS + if (pool == 0) + cvmx_ipd_free_ptr(); +#endif + + if (errors) { + cvmx_dprintf + ("ERROR: cvmx_fpa_shutdown_pool: Pool %s(%d) started at 0x%llx, ended at 0x%llx, with a step of 0x%llx\n", + cvmx_fpa_pool_info[pool].name, (int)pool, + (unsigned long long)base, (unsigned long long)finish, + (unsigned long long)cvmx_fpa_pool_info[pool].size); + return -errors; + } else + return 0; +} + +uint64_t cvmx_fpa_get_block_size(uint64_t pool) +{ + switch (pool) { + case 0: + return CVMX_FPA_POOL_0_SIZE; + case 1: + return CVMX_FPA_POOL_1_SIZE; + case 2: + return CVMX_FPA_POOL_2_SIZE; + case 3: + return CVMX_FPA_POOL_3_SIZE; + case 4: + return CVMX_FPA_POOL_4_SIZE; + case 5: + return CVMX_FPA_POOL_5_SIZE; + case 6: + return CVMX_FPA_POOL_6_SIZE; + case 7: + return CVMX_FPA_POOL_7_SIZE; + default: + return 0; + } +} diff --git a/drivers/staging/octeon/cvmx-fpa.h b/drivers/staging/octeon/cvmx-fpa.h new file mode 100644 index 0000000..1d7788f --- /dev/null +++ b/drivers/staging/octeon/cvmx-fpa.h @@ -0,0 +1,299 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * along with this file; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +/** + * @file + * + * Interface to the hardware Free Pool Allocator. + * + * + */ + +#ifndef __CVMX_FPA_H__ +#define __CVMX_FPA_H__ + +#include "cvmx-address.h" +#include "cvmx-fpa-defs.h" + +#define CVMX_FPA_NUM_POOLS 8 +#define CVMX_FPA_MIN_BLOCK_SIZE 128 +#define CVMX_FPA_ALIGNMENT 128 + +/** + * Structure describing the data format used for stores to the FPA. + */ +typedef union { + uint64_t u64; + struct { + /* + * the (64-bit word) location in scratchpad to write + * to (if len != 0) + */ + uint64_t scraddr:8; + /* the number of words in the response (0 => no response) */ + uint64_t len:8; + /* the ID of the device on the non-coherent bus */ + uint64_t did:8; + /* + * the address that will appear in the first tick on + * the NCB bus. + */ + uint64_t addr:40; + } s; +} cvmx_fpa_iobdma_data_t; + +/** + * Structure describing the current state of a FPA pool. + */ +typedef struct { + /* Name it was created under */ + const char *name; + /* Size of each block */ + uint64_t size; + /* The base memory address of whole block */ + void *base; + /* The number of elements in the pool at creation */ + uint64_t starting_element_count; +} cvmx_fpa_pool_info_t; + +/** + * Current state of all the pools. Use access functions + * instead of using it directly. + */ +extern cvmx_fpa_pool_info_t cvmx_fpa_pool_info[CVMX_FPA_NUM_POOLS]; + +/* CSR typedefs have been moved to cvmx-csr-*.h */ + +/** + * Return the name of the pool + * + * @pool: Pool to get the name of + * Returns The name + */ +static inline const char *cvmx_fpa_get_name(uint64_t pool) +{ + return cvmx_fpa_pool_info[pool].name; +} + +/** + * Return the base of the pool + * + * @pool: Pool to get the base of + * Returns The base + */ +static inline void *cvmx_fpa_get_base(uint64_t pool) +{ + return cvmx_fpa_pool_info[pool].base; +} + +/** + * Check if a pointer belongs to an FPA pool. Return non-zero + * if the supplied pointer is inside the memory controlled by + * an FPA pool. + * + * @pool: Pool to check + * @ptr: Pointer to check + * Returns Non-zero if pointer is in the pool. Zero if not + */ +static inline int cvmx_fpa_is_member(uint64_t pool, void *ptr) +{ + return ((ptr >= cvmx_fpa_pool_info[pool].base) && + ((char *)ptr < + ((char *)(cvmx_fpa_pool_info[pool].base)) + + cvmx_fpa_pool_info[pool].size * + cvmx_fpa_pool_info[pool].starting_element_count)); +} + +/** + * Enable the FPA for use. Must be performed after any CSR + * configuration but before any other FPA functions. + */ +static inline void cvmx_fpa_enable(void) +{ + union cvmx_fpa_ctl_status status; + + status.u64 = cvmx_read_csr(CVMX_FPA_CTL_STATUS); + if (status.s.enb) { + cvmx_dprintf + ("Warning: Enabling FPA when FPA already enabled.\n"); + } + + /* + * Do runtime check as we allow pass1 compiled code to run on + * pass2 chips. + */ + if (cvmx_octeon_is_pass1()) { + union cvmx_fpa_fpfx_marks marks; + int i; + for (i = 1; i < 8; i++) { + marks.u64 = + cvmx_read_csr(CVMX_FPA_FPF1_MARKS + (i - 1) * 8ull); + marks.s.fpf_wr = 0xe0; + cvmx_write_csr(CVMX_FPA_FPF1_MARKS + (i - 1) * 8ull, + marks.u64); + } + + /* Enforce a 10 cycle delay between config and enable */ + cvmx_wait(10); + } + + /* FIXME: CVMX_FPA_CTL_STATUS read is unmodelled */ + status.u64 = 0; + status.s.enb = 1; + cvmx_write_csr(CVMX_FPA_CTL_STATUS, status.u64); +} + +/** + * Get a new block from the FPA + * + * @pool: Pool to get the block from + * Returns Pointer to the block or NULL on failure + */ +static inline void *cvmx_fpa_alloc(uint64_t pool) +{ + uint64_t address = + cvmx_read_csr(CVMX_ADDR_DID(CVMX_FULL_DID(CVMX_OCT_DID_FPA, pool))); + if (address) + return cvmx_phys_to_ptr(address); + else + return NULL; +} + +/** + * Asynchronously get a new block from the FPA + * + * @scr_addr: Local scratch address to put response in. This is a byte address, + * but must be 8 byte aligned. + * @pool: Pool to get the block from + */ +static inline void cvmx_fpa_async_alloc(uint64_t scr_addr, uint64_t pool) +{ + cvmx_fpa_iobdma_data_t data; + + /* + * Hardware only uses 64 bit alligned locations, so convert + * from byte address to 64-bit index + */ + data.s.scraddr = scr_addr >> 3; + data.s.len = 1; + data.s.did = CVMX_FULL_DID(CVMX_OCT_DID_FPA, pool); + data.s.addr = 0; + cvmx_send_single(data.u64); +} + +/** + * Free a block allocated with a FPA pool. Does NOT provide memory + * ordering in cases where the memory block was modified by the core. + * + * @ptr: Block to free + * @pool: Pool to put it in + * @num_cache_lines: + * Cache lines to invalidate + */ +static inline void cvmx_fpa_free_nosync(void *ptr, uint64_t pool, + uint64_t num_cache_lines) +{ + cvmx_addr_t newptr; + newptr.u64 = cvmx_ptr_to_phys(ptr); + newptr.sfilldidspace.didspace = + CVMX_ADDR_DIDSPACE(CVMX_FULL_DID(CVMX_OCT_DID_FPA, pool)); + /* Prevent GCC from reordering around free */ + barrier(); + /* value written is number of cache lines not written back */ + cvmx_write_io(newptr.u64, num_cache_lines); +} + +/** + * Free a block allocated with a FPA pool. Provides required memory + * ordering in cases where memory block was modified by core. + * + * @ptr: Block to free + * @pool: Pool to put it in + * @num_cache_lines: + * Cache lines to invalidate + */ +static inline void cvmx_fpa_free(void *ptr, uint64_t pool, + uint64_t num_cache_lines) +{ + cvmx_addr_t newptr; + newptr.u64 = cvmx_ptr_to_phys(ptr); + newptr.sfilldidspace.didspace = + CVMX_ADDR_DIDSPACE(CVMX_FULL_DID(CVMX_OCT_DID_FPA, pool)); + /* + * Make sure that any previous writes to memory go out before + * we free this buffer. This also serves as a barrier to + * prevent GCC from reordering operations to after the + * free. + */ + CVMX_SYNCWS; + /* value written is number of cache lines not written back */ + cvmx_write_io(newptr.u64, num_cache_lines); +} + +/** + * Setup a FPA pool to control a new block of memory. + * This can only be called once per pool. Make sure proper + * locking enforces this. + * + * @pool: Pool to initialize + * 0 <= pool < 8 + * @name: Constant character string to name this pool. + * String is not copied. + * @buffer: Pointer to the block of memory to use. This must be + * accessable by all processors and external hardware. + * @block_size: Size for each block controlled by the FPA + * @num_blocks: Number of blocks + * + * Returns 0 on Success, + * -1 on failure + */ +extern int cvmx_fpa_setup_pool(uint64_t pool, const char *name, void *buffer, + uint64_t block_size, uint64_t num_blocks); + +/** + * Shutdown a Memory pool and validate that it had all of + * the buffers originally placed in it. This should only be + * called by one processor after all hardware has finished + * using the pool. + * + * @pool: Pool to shutdown + * Returns Zero on success + * - Positive is count of missing buffers + * - Negative is too many buffers or corrupted pointers + */ +extern uint64_t cvmx_fpa_shutdown_pool(uint64_t pool); + +/** + * Get the size of blocks controlled by the pool + * This is resolved to a constant at compile time. + * + * @pool: Pool to access + * Returns Size of the block in bytes + */ +uint64_t cvmx_fpa_get_block_size(uint64_t pool); + +#endif /* __CVM_FPA_H__ */ diff --git a/drivers/staging/octeon/cvmx-gmxx-defs.h b/drivers/staging/octeon/cvmx-gmxx-defs.h new file mode 100644 index 0000000..946a43a --- /dev/null +++ b/drivers/staging/octeon/cvmx-gmxx-defs.h @@ -0,0 +1,2529 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * along with this file; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +#ifndef __CVMX_GMXX_DEFS_H__ +#define __CVMX_GMXX_DEFS_H__ + +#define CVMX_GMXX_BAD_REG(block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000518ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_BIST(block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000400ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_CLK_EN(block_id) \ + CVMX_ADD_IO_SEG(0x00011800080007F0ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_HG2_CONTROL(block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000550ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_INF_MODE(block_id) \ + CVMX_ADD_IO_SEG(0x00011800080007F8ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_NXA_ADR(block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000510ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_PRTX_CBFC_CTL(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000580ull + (((offset) & 0) * 8) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_PRTX_CFG(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000010ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_RXX_ADR_CAM0(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000180ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_RXX_ADR_CAM1(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000188ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_RXX_ADR_CAM2(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000190ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_RXX_ADR_CAM3(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000198ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_RXX_ADR_CAM4(offset, block_id) \ + CVMX_ADD_IO_SEG(0x00011800080001A0ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_RXX_ADR_CAM5(offset, block_id) \ + CVMX_ADD_IO_SEG(0x00011800080001A8ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_RXX_ADR_CAM_EN(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000108ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_RXX_ADR_CTL(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000100ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_RXX_DECISION(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000040ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_RXX_FRM_CHK(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000020ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_RXX_FRM_CTL(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000018ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_RXX_FRM_MAX(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000030ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_RXX_FRM_MIN(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000028ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_RXX_IFG(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000058ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_RXX_INT_EN(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000008ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_RXX_INT_REG(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000000ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_RXX_JABBER(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000038ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_RXX_PAUSE_DROP_TIME(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000068ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_RXX_RX_INBND(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000060ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_RXX_STATS_CTL(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000050ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_RXX_STATS_OCTS(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000088ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_RXX_STATS_OCTS_CTL(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000098ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_RXX_STATS_OCTS_DMAC(offset, block_id) \ + CVMX_ADD_IO_SEG(0x00011800080000A8ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_RXX_STATS_OCTS_DRP(offset, block_id) \ + CVMX_ADD_IO_SEG(0x00011800080000B8ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_RXX_STATS_PKTS(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000080ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_RXX_STATS_PKTS_BAD(offset, block_id) \ + CVMX_ADD_IO_SEG(0x00011800080000C0ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_RXX_STATS_PKTS_CTL(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000090ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_RXX_STATS_PKTS_DMAC(offset, block_id) \ + CVMX_ADD_IO_SEG(0x00011800080000A0ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_RXX_STATS_PKTS_DRP(offset, block_id) \ + CVMX_ADD_IO_SEG(0x00011800080000B0ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_RXX_UDD_SKP(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000048ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_RX_BP_DROPX(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000420ull + (((offset) & 3) * 8) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_RX_BP_OFFX(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000460ull + (((offset) & 3) * 8) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_RX_BP_ONX(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000440ull + (((offset) & 3) * 8) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_RX_HG2_STATUS(block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000548ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_RX_PASS_EN(block_id) \ + CVMX_ADD_IO_SEG(0x00011800080005F8ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_RX_PASS_MAPX(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000600ull + (((offset) & 15) * 8) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_RX_PRTS(block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000410ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_RX_PRT_INFO(block_id) \ + CVMX_ADD_IO_SEG(0x00011800080004E8ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_RX_TX_STATUS(block_id) \ + CVMX_ADD_IO_SEG(0x00011800080007E8ull + (((block_id) & 0) * 0x8000000ull)) +#define CVMX_GMXX_RX_XAUI_BAD_COL(block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000538ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_RX_XAUI_CTL(block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000530ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_SMACX(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000230ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_STAT_BP(block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000520ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TXX_APPEND(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000218ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TXX_BURST(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000228ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TXX_CBFC_XOFF(offset, block_id) \ + CVMX_ADD_IO_SEG(0x00011800080005A0ull + (((offset) & 0) * 8) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TXX_CBFC_XON(offset, block_id) \ + CVMX_ADD_IO_SEG(0x00011800080005C0ull + (((offset) & 0) * 8) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TXX_CLK(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000208ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TXX_CTL(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000270ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TXX_MIN_PKT(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000240ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TXX_PAUSE_PKT_INTERVAL(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000248ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TXX_PAUSE_PKT_TIME(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000238ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TXX_PAUSE_TOGO(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000258ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TXX_PAUSE_ZERO(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000260ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TXX_SGMII_CTL(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000300ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TXX_SLOT(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000220ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TXX_SOFT_PAUSE(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000250ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TXX_STAT0(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000280ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TXX_STAT1(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000288ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TXX_STAT2(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000290ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TXX_STAT3(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000298ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TXX_STAT4(offset, block_id) \ + CVMX_ADD_IO_SEG(0x00011800080002A0ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TXX_STAT5(offset, block_id) \ + CVMX_ADD_IO_SEG(0x00011800080002A8ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TXX_STAT6(offset, block_id) \ + CVMX_ADD_IO_SEG(0x00011800080002B0ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TXX_STAT7(offset, block_id) \ + CVMX_ADD_IO_SEG(0x00011800080002B8ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TXX_STAT8(offset, block_id) \ + CVMX_ADD_IO_SEG(0x00011800080002C0ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TXX_STAT9(offset, block_id) \ + CVMX_ADD_IO_SEG(0x00011800080002C8ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TXX_STATS_CTL(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000268ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TXX_THRESH(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000210ull + (((offset) & 3) * 2048) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TX_BP(block_id) \ + CVMX_ADD_IO_SEG(0x00011800080004D0ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TX_CLK_MSKX(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000780ull + (((offset) & 1) * 8) + (((block_id) & 0) * 0x0ull)) +#define CVMX_GMXX_TX_COL_ATTEMPT(block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000498ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TX_CORRUPT(block_id) \ + CVMX_ADD_IO_SEG(0x00011800080004D8ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TX_HG2_REG1(block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000558ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TX_HG2_REG2(block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000560ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TX_IFG(block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000488ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TX_INT_EN(block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000508ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TX_INT_REG(block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000500ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TX_JAM(block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000490ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TX_LFSR(block_id) \ + CVMX_ADD_IO_SEG(0x00011800080004F8ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TX_OVR_BP(block_id) \ + CVMX_ADD_IO_SEG(0x00011800080004C8ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TX_PAUSE_PKT_DMAC(block_id) \ + CVMX_ADD_IO_SEG(0x00011800080004A0ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TX_PAUSE_PKT_TYPE(block_id) \ + CVMX_ADD_IO_SEG(0x00011800080004A8ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TX_PRTS(block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000480ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TX_SPI_CTL(block_id) \ + CVMX_ADD_IO_SEG(0x00011800080004C0ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TX_SPI_DRAIN(block_id) \ + CVMX_ADD_IO_SEG(0x00011800080004E0ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TX_SPI_MAX(block_id) \ + CVMX_ADD_IO_SEG(0x00011800080004B0ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TX_SPI_ROUNDX(offset, block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000680ull + (((offset) & 31) * 8) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TX_SPI_THRESH(block_id) \ + CVMX_ADD_IO_SEG(0x00011800080004B8ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_TX_XAUI_CTL(block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000528ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_GMXX_XAUI_EXT_LOOPBACK(block_id) \ + CVMX_ADD_IO_SEG(0x0001180008000540ull + (((block_id) & 1) * 0x8000000ull)) + +union cvmx_gmxx_bad_reg { + uint64_t u64; + struct cvmx_gmxx_bad_reg_s { + uint64_t reserved_31_63:33; + uint64_t inb_nxa:4; + uint64_t statovr:1; + uint64_t loststat:4; + uint64_t reserved_18_21:4; + uint64_t out_ovr:16; + uint64_t ncb_ovr:1; + uint64_t out_col:1; + } s; + struct cvmx_gmxx_bad_reg_cn30xx { + uint64_t reserved_31_63:33; + uint64_t inb_nxa:4; + uint64_t statovr:1; + uint64_t reserved_25_25:1; + uint64_t loststat:3; + uint64_t reserved_5_21:17; + uint64_t out_ovr:3; + uint64_t reserved_0_1:2; + } cn30xx; + struct cvmx_gmxx_bad_reg_cn30xx cn31xx; + struct cvmx_gmxx_bad_reg_s cn38xx; + struct cvmx_gmxx_bad_reg_s cn38xxp2; + struct cvmx_gmxx_bad_reg_cn30xx cn50xx; + struct cvmx_gmxx_bad_reg_cn52xx { + uint64_t reserved_31_63:33; + uint64_t inb_nxa:4; + uint64_t statovr:1; + uint64_t loststat:4; + uint64_t reserved_6_21:16; + uint64_t out_ovr:4; + uint64_t reserved_0_1:2; + } cn52xx; + struct cvmx_gmxx_bad_reg_cn52xx cn52xxp1; + struct cvmx_gmxx_bad_reg_cn52xx cn56xx; + struct cvmx_gmxx_bad_reg_cn52xx cn56xxp1; + struct cvmx_gmxx_bad_reg_s cn58xx; + struct cvmx_gmxx_bad_reg_s cn58xxp1; +}; + +union cvmx_gmxx_bist { + uint64_t u64; + struct cvmx_gmxx_bist_s { + uint64_t reserved_17_63:47; + uint64_t status:17; + } s; + struct cvmx_gmxx_bist_cn30xx { + uint64_t reserved_10_63:54; + uint64_t status:10; + } cn30xx; + struct cvmx_gmxx_bist_cn30xx cn31xx; + struct cvmx_gmxx_bist_cn30xx cn38xx; + struct cvmx_gmxx_bist_cn30xx cn38xxp2; + struct cvmx_gmxx_bist_cn50xx { + uint64_t reserved_12_63:52; + uint64_t status:12; + } cn50xx; + struct cvmx_gmxx_bist_cn52xx { + uint64_t reserved_16_63:48; + uint64_t status:16; + } cn52xx; + struct cvmx_gmxx_bist_cn52xx cn52xxp1; + struct cvmx_gmxx_bist_cn52xx cn56xx; + struct cvmx_gmxx_bist_cn52xx cn56xxp1; + struct cvmx_gmxx_bist_s cn58xx; + struct cvmx_gmxx_bist_s cn58xxp1; +}; + +union cvmx_gmxx_clk_en { + uint64_t u64; + struct cvmx_gmxx_clk_en_s { + uint64_t reserved_1_63:63; + uint64_t clk_en:1; + } s; + struct cvmx_gmxx_clk_en_s cn52xx; + struct cvmx_gmxx_clk_en_s cn52xxp1; + struct cvmx_gmxx_clk_en_s cn56xx; + struct cvmx_gmxx_clk_en_s cn56xxp1; +}; + +union cvmx_gmxx_hg2_control { + uint64_t u64; + struct cvmx_gmxx_hg2_control_s { + uint64_t reserved_19_63:45; + uint64_t hg2tx_en:1; + uint64_t hg2rx_en:1; + uint64_t phys_en:1; + uint64_t logl_en:16; + } s; + struct cvmx_gmxx_hg2_control_s cn52xx; + struct cvmx_gmxx_hg2_control_s cn52xxp1; + struct cvmx_gmxx_hg2_control_s cn56xx; +}; + +union cvmx_gmxx_inf_mode { + uint64_t u64; + struct cvmx_gmxx_inf_mode_s { + uint64_t reserved_10_63:54; + uint64_t speed:2; + uint64_t reserved_6_7:2; + uint64_t mode:2; + uint64_t reserved_3_3:1; + uint64_t p0mii:1; + uint64_t en:1; + uint64_t type:1; + } s; + struct cvmx_gmxx_inf_mode_cn30xx { + uint64_t reserved_3_63:61; + uint64_t p0mii:1; + uint64_t en:1; + uint64_t type:1; + } cn30xx; + struct cvmx_gmxx_inf_mode_cn31xx { + uint64_t reserved_2_63:62; + uint64_t en:1; + uint64_t type:1; + } cn31xx; + struct cvmx_gmxx_inf_mode_cn31xx cn38xx; + struct cvmx_gmxx_inf_mode_cn31xx cn38xxp2; + struct cvmx_gmxx_inf_mode_cn30xx cn50xx; + struct cvmx_gmxx_inf_mode_cn52xx { + uint64_t reserved_10_63:54; + uint64_t speed:2; + uint64_t reserved_6_7:2; + uint64_t mode:2; + uint64_t reserved_2_3:2; + uint64_t en:1; + uint64_t type:1; + } cn52xx; + struct cvmx_gmxx_inf_mode_cn52xx cn52xxp1; + struct cvmx_gmxx_inf_mode_cn52xx cn56xx; + struct cvmx_gmxx_inf_mode_cn52xx cn56xxp1; + struct cvmx_gmxx_inf_mode_cn31xx cn58xx; + struct cvmx_gmxx_inf_mode_cn31xx cn58xxp1; +}; + +union cvmx_gmxx_nxa_adr { + uint64_t u64; + struct cvmx_gmxx_nxa_adr_s { + uint64_t reserved_6_63:58; + uint64_t prt:6; + } s; + struct cvmx_gmxx_nxa_adr_s cn30xx; + struct cvmx_gmxx_nxa_adr_s cn31xx; + struct cvmx_gmxx_nxa_adr_s cn38xx; + struct cvmx_gmxx_nxa_adr_s cn38xxp2; + struct cvmx_gmxx_nxa_adr_s cn50xx; + struct cvmx_gmxx_nxa_adr_s cn52xx; + struct cvmx_gmxx_nxa_adr_s cn52xxp1; + struct cvmx_gmxx_nxa_adr_s cn56xx; + struct cvmx_gmxx_nxa_adr_s cn56xxp1; + struct cvmx_gmxx_nxa_adr_s cn58xx; + struct cvmx_gmxx_nxa_adr_s cn58xxp1; +}; + +union cvmx_gmxx_prtx_cbfc_ctl { + uint64_t u64; + struct cvmx_gmxx_prtx_cbfc_ctl_s { + uint64_t phys_en:16; + uint64_t logl_en:16; + uint64_t phys_bp:16; + uint64_t reserved_4_15:12; + uint64_t bck_en:1; + uint64_t drp_en:1; + uint64_t tx_en:1; + uint64_t rx_en:1; + } s; + struct cvmx_gmxx_prtx_cbfc_ctl_s cn52xx; + struct cvmx_gmxx_prtx_cbfc_ctl_s cn56xx; +}; + +union cvmx_gmxx_prtx_cfg { + uint64_t u64; + struct cvmx_gmxx_prtx_cfg_s { + uint64_t reserved_14_63:50; + uint64_t tx_idle:1; + uint64_t rx_idle:1; + uint64_t reserved_9_11:3; + uint64_t speed_msb:1; + uint64_t reserved_4_7:4; + uint64_t slottime:1; + uint64_t duplex:1; + uint64_t speed:1; + uint64_t en:1; + } s; + struct cvmx_gmxx_prtx_cfg_cn30xx { + uint64_t reserved_4_63:60; + uint64_t slottime:1; + uint64_t duplex:1; + uint64_t speed:1; + uint64_t en:1; + } cn30xx; + struct cvmx_gmxx_prtx_cfg_cn30xx cn31xx; + struct cvmx_gmxx_prtx_cfg_cn30xx cn38xx; + struct cvmx_gmxx_prtx_cfg_cn30xx cn38xxp2; + struct cvmx_gmxx_prtx_cfg_cn30xx cn50xx; + struct cvmx_gmxx_prtx_cfg_s cn52xx; + struct cvmx_gmxx_prtx_cfg_s cn52xxp1; + struct cvmx_gmxx_prtx_cfg_s cn56xx; + struct cvmx_gmxx_prtx_cfg_s cn56xxp1; + struct cvmx_gmxx_prtx_cfg_cn30xx cn58xx; + struct cvmx_gmxx_prtx_cfg_cn30xx cn58xxp1; +}; + +union cvmx_gmxx_rxx_adr_cam0 { + uint64_t u64; + struct cvmx_gmxx_rxx_adr_cam0_s { + uint64_t adr:64; + } s; + struct cvmx_gmxx_rxx_adr_cam0_s cn30xx; + struct cvmx_gmxx_rxx_adr_cam0_s cn31xx; + struct cvmx_gmxx_rxx_adr_cam0_s cn38xx; + struct cvmx_gmxx_rxx_adr_cam0_s cn38xxp2; + struct cvmx_gmxx_rxx_adr_cam0_s cn50xx; + struct cvmx_gmxx_rxx_adr_cam0_s cn52xx; + struct cvmx_gmxx_rxx_adr_cam0_s cn52xxp1; + struct cvmx_gmxx_rxx_adr_cam0_s cn56xx; + struct cvmx_gmxx_rxx_adr_cam0_s cn56xxp1; + struct cvmx_gmxx_rxx_adr_cam0_s cn58xx; + struct cvmx_gmxx_rxx_adr_cam0_s cn58xxp1; +}; + +union cvmx_gmxx_rxx_adr_cam1 { + uint64_t u64; + struct cvmx_gmxx_rxx_adr_cam1_s { + uint64_t adr:64; + } s; + struct cvmx_gmxx_rxx_adr_cam1_s cn30xx; + struct cvmx_gmxx_rxx_adr_cam1_s cn31xx; + struct cvmx_gmxx_rxx_adr_cam1_s cn38xx; + struct cvmx_gmxx_rxx_adr_cam1_s cn38xxp2; + struct cvmx_gmxx_rxx_adr_cam1_s cn50xx; + struct cvmx_gmxx_rxx_adr_cam1_s cn52xx; + struct cvmx_gmxx_rxx_adr_cam1_s cn52xxp1; + struct cvmx_gmxx_rxx_adr_cam1_s cn56xx; + struct cvmx_gmxx_rxx_adr_cam1_s cn56xxp1; + struct cvmx_gmxx_rxx_adr_cam1_s cn58xx; + struct cvmx_gmxx_rxx_adr_cam1_s cn58xxp1; +}; + +union cvmx_gmxx_rxx_adr_cam2 { + uint64_t u64; + struct cvmx_gmxx_rxx_adr_cam2_s { + uint64_t adr:64; + } s; + struct cvmx_gmxx_rxx_adr_cam2_s cn30xx; + struct cvmx_gmxx_rxx_adr_cam2_s cn31xx; + struct cvmx_gmxx_rxx_adr_cam2_s cn38xx; + struct cvmx_gmxx_rxx_adr_cam2_s cn38xxp2; + struct cvmx_gmxx_rxx_adr_cam2_s cn50xx; + struct cvmx_gmxx_rxx_adr_cam2_s cn52xx; + struct cvmx_gmxx_rxx_adr_cam2_s cn52xxp1; + struct cvmx_gmxx_rxx_adr_cam2_s cn56xx; + struct cvmx_gmxx_rxx_adr_cam2_s cn56xxp1; + struct cvmx_gmxx_rxx_adr_cam2_s cn58xx; + struct cvmx_gmxx_rxx_adr_cam2_s cn58xxp1; +}; + +union cvmx_gmxx_rxx_adr_cam3 { + uint64_t u64; + struct cvmx_gmxx_rxx_adr_cam3_s { + uint64_t adr:64; + } s; + struct cvmx_gmxx_rxx_adr_cam3_s cn30xx; + struct cvmx_gmxx_rxx_adr_cam3_s cn31xx; + struct cvmx_gmxx_rxx_adr_cam3_s cn38xx; + struct cvmx_gmxx_rxx_adr_cam3_s cn38xxp2; + struct cvmx_gmxx_rxx_adr_cam3_s cn50xx; + struct cvmx_gmxx_rxx_adr_cam3_s cn52xx; + struct cvmx_gmxx_rxx_adr_cam3_s cn52xxp1; + struct cvmx_gmxx_rxx_adr_cam3_s cn56xx; + struct cvmx_gmxx_rxx_adr_cam3_s cn56xxp1; + struct cvmx_gmxx_rxx_adr_cam3_s cn58xx; + struct cvmx_gmxx_rxx_adr_cam3_s cn58xxp1; +}; + +union cvmx_gmxx_rxx_adr_cam4 { + uint64_t u64; + struct cvmx_gmxx_rxx_adr_cam4_s { + uint64_t adr:64; + } s; + struct cvmx_gmxx_rxx_adr_cam4_s cn30xx; + struct cvmx_gmxx_rxx_adr_cam4_s cn31xx; + struct cvmx_gmxx_rxx_adr_cam4_s cn38xx; + struct cvmx_gmxx_rxx_adr_cam4_s cn38xxp2; + struct cvmx_gmxx_rxx_adr_cam4_s cn50xx; + struct cvmx_gmxx_rxx_adr_cam4_s cn52xx; + struct cvmx_gmxx_rxx_adr_cam4_s cn52xxp1; + struct cvmx_gmxx_rxx_adr_cam4_s cn56xx; + struct cvmx_gmxx_rxx_adr_cam4_s cn56xxp1; + struct cvmx_gmxx_rxx_adr_cam4_s cn58xx; + struct cvmx_gmxx_rxx_adr_cam4_s cn58xxp1; +}; + +union cvmx_gmxx_rxx_adr_cam5 { + uint64_t u64; + struct cvmx_gmxx_rxx_adr_cam5_s { + uint64_t adr:64; + } s; + struct cvmx_gmxx_rxx_adr_cam5_s cn30xx; + struct cvmx_gmxx_rxx_adr_cam5_s cn31xx; + struct cvmx_gmxx_rxx_adr_cam5_s cn38xx; + struct cvmx_gmxx_rxx_adr_cam5_s cn38xxp2; + struct cvmx_gmxx_rxx_adr_cam5_s cn50xx; + struct cvmx_gmxx_rxx_adr_cam5_s cn52xx; + struct cvmx_gmxx_rxx_adr_cam5_s cn52xxp1; + struct cvmx_gmxx_rxx_adr_cam5_s cn56xx; + struct cvmx_gmxx_rxx_adr_cam5_s cn56xxp1; + struct cvmx_gmxx_rxx_adr_cam5_s cn58xx; + struct cvmx_gmxx_rxx_adr_cam5_s cn58xxp1; +}; + +union cvmx_gmxx_rxx_adr_cam_en { + uint64_t u64; + struct cvmx_gmxx_rxx_adr_cam_en_s { + uint64_t reserved_8_63:56; + uint64_t en:8; + } s; + struct cvmx_gmxx_rxx_adr_cam_en_s cn30xx; + struct cvmx_gmxx_rxx_adr_cam_en_s cn31xx; + struct cvmx_gmxx_rxx_adr_cam_en_s cn38xx; + struct cvmx_gmxx_rxx_adr_cam_en_s cn38xxp2; + struct cvmx_gmxx_rxx_adr_cam_en_s cn50xx; + struct cvmx_gmxx_rxx_adr_cam_en_s cn52xx; + struct cvmx_gmxx_rxx_adr_cam_en_s cn52xxp1; + struct cvmx_gmxx_rxx_adr_cam_en_s cn56xx; + struct cvmx_gmxx_rxx_adr_cam_en_s cn56xxp1; + struct cvmx_gmxx_rxx_adr_cam_en_s cn58xx; + struct cvmx_gmxx_rxx_adr_cam_en_s cn58xxp1; +}; + +union cvmx_gmxx_rxx_adr_ctl { + uint64_t u64; + struct cvmx_gmxx_rxx_adr_ctl_s { + uint64_t reserved_4_63:60; + uint64_t cam_mode:1; + uint64_t mcst:2; + uint64_t bcst:1; + } s; + struct cvmx_gmxx_rxx_adr_ctl_s cn30xx; + struct cvmx_gmxx_rxx_adr_ctl_s cn31xx; + struct cvmx_gmxx_rxx_adr_ctl_s cn38xx; + struct cvmx_gmxx_rxx_adr_ctl_s cn38xxp2; + struct cvmx_gmxx_rxx_adr_ctl_s cn50xx; + struct cvmx_gmxx_rxx_adr_ctl_s cn52xx; + struct cvmx_gmxx_rxx_adr_ctl_s cn52xxp1; + struct cvmx_gmxx_rxx_adr_ctl_s cn56xx; + struct cvmx_gmxx_rxx_adr_ctl_s cn56xxp1; + struct cvmx_gmxx_rxx_adr_ctl_s cn58xx; + struct cvmx_gmxx_rxx_adr_ctl_s cn58xxp1; +}; + +union cvmx_gmxx_rxx_decision { + uint64_t u64; + struct cvmx_gmxx_rxx_decision_s { + uint64_t reserved_5_63:59; + uint64_t cnt:5; + } s; + struct cvmx_gmxx_rxx_decision_s cn30xx; + struct cvmx_gmxx_rxx_decision_s cn31xx; + struct cvmx_gmxx_rxx_decision_s cn38xx; + struct cvmx_gmxx_rxx_decision_s cn38xxp2; + struct cvmx_gmxx_rxx_decision_s cn50xx; + struct cvmx_gmxx_rxx_decision_s cn52xx; + struct cvmx_gmxx_rxx_decision_s cn52xxp1; + struct cvmx_gmxx_rxx_decision_s cn56xx; + struct cvmx_gmxx_rxx_decision_s cn56xxp1; + struct cvmx_gmxx_rxx_decision_s cn58xx; + struct cvmx_gmxx_rxx_decision_s cn58xxp1; +}; + +union cvmx_gmxx_rxx_frm_chk { + uint64_t u64; + struct cvmx_gmxx_rxx_frm_chk_s { + uint64_t reserved_10_63:54; + uint64_t niberr:1; + uint64_t skperr:1; + uint64_t rcverr:1; + uint64_t lenerr:1; + uint64_t alnerr:1; + uint64_t fcserr:1; + uint64_t jabber:1; + uint64_t maxerr:1; + uint64_t carext:1; + uint64_t minerr:1; + } s; + struct cvmx_gmxx_rxx_frm_chk_s cn30xx; + struct cvmx_gmxx_rxx_frm_chk_s cn31xx; + struct cvmx_gmxx_rxx_frm_chk_s cn38xx; + struct cvmx_gmxx_rxx_frm_chk_s cn38xxp2; + struct cvmx_gmxx_rxx_frm_chk_cn50xx { + uint64_t reserved_10_63:54; + uint64_t niberr:1; + uint64_t skperr:1; + uint64_t rcverr:1; + uint64_t reserved_6_6:1; + uint64_t alnerr:1; + uint64_t fcserr:1; + uint64_t jabber:1; + uint64_t reserved_2_2:1; + uint64_t carext:1; + uint64_t reserved_0_0:1; + } cn50xx; + struct cvmx_gmxx_rxx_frm_chk_cn52xx { + uint64_t reserved_9_63:55; + uint64_t skperr:1; + uint64_t rcverr:1; + uint64_t reserved_5_6:2; + uint64_t fcserr:1; + uint64_t jabber:1; + uint64_t reserved_2_2:1; + uint64_t carext:1; + uint64_t reserved_0_0:1; + } cn52xx; + struct cvmx_gmxx_rxx_frm_chk_cn52xx cn52xxp1; + struct cvmx_gmxx_rxx_frm_chk_cn52xx cn56xx; + struct cvmx_gmxx_rxx_frm_chk_cn52xx cn56xxp1; + struct cvmx_gmxx_rxx_frm_chk_s cn58xx; + struct cvmx_gmxx_rxx_frm_chk_s cn58xxp1; +}; + +union cvmx_gmxx_rxx_frm_ctl { + uint64_t u64; + struct cvmx_gmxx_rxx_frm_ctl_s { + uint64_t reserved_11_63:53; + uint64_t null_dis:1; + uint64_t pre_align:1; + uint64_t pad_len:1; + uint64_t vlan_len:1; + uint64_t pre_free:1; + uint64_t ctl_smac:1; + uint64_t ctl_mcst:1; + uint64_t ctl_bck:1; + uint64_t ctl_drp:1; + uint64_t pre_strp:1; + uint64_t pre_chk:1; + } s; + struct cvmx_gmxx_rxx_frm_ctl_cn30xx { + uint64_t reserved_9_63:55; + uint64_t pad_len:1; + uint64_t vlan_len:1; + uint64_t pre_free:1; + uint64_t ctl_smac:1; + uint64_t ctl_mcst:1; + uint64_t ctl_bck:1; + uint64_t ctl_drp:1; + uint64_t pre_strp:1; + uint64_t pre_chk:1; + } cn30xx; + struct cvmx_gmxx_rxx_frm_ctl_cn31xx { + uint64_t reserved_8_63:56; + uint64_t vlan_len:1; + uint64_t pre_free:1; + uint64_t ctl_smac:1; + uint64_t ctl_mcst:1; + uint64_t ctl_bck:1; + uint64_t ctl_drp:1; + uint64_t pre_strp:1; + uint64_t pre_chk:1; + } cn31xx; + struct cvmx_gmxx_rxx_frm_ctl_cn30xx cn38xx; + struct cvmx_gmxx_rxx_frm_ctl_cn31xx cn38xxp2; + struct cvmx_gmxx_rxx_frm_ctl_cn50xx { + uint64_t reserved_11_63:53; + uint64_t null_dis:1; + uint64_t pre_align:1; + uint64_t reserved_7_8:2; + uint64_t pre_free:1; + uint64_t ctl_smac:1; + uint64_t ctl_mcst:1; + uint64_t ctl_bck:1; + uint64_t ctl_drp:1; + uint64_t pre_strp:1; + uint64_t pre_chk:1; + } cn50xx; + struct cvmx_gmxx_rxx_frm_ctl_cn50xx cn52xx; + struct cvmx_gmxx_rxx_frm_ctl_cn50xx cn52xxp1; + struct cvmx_gmxx_rxx_frm_ctl_cn50xx cn56xx; + struct cvmx_gmxx_rxx_frm_ctl_cn56xxp1 { + uint64_t reserved_10_63:54; + uint64_t pre_align:1; + uint64_t reserved_7_8:2; + uint64_t pre_free:1; + uint64_t ctl_smac:1; + uint64_t ctl_mcst:1; + uint64_t ctl_bck:1; + uint64_t ctl_drp:1; + uint64_t pre_strp:1; + uint64_t pre_chk:1; + } cn56xxp1; + struct cvmx_gmxx_rxx_frm_ctl_s cn58xx; + struct cvmx_gmxx_rxx_frm_ctl_cn30xx cn58xxp1; +}; + +union cvmx_gmxx_rxx_frm_max { + uint64_t u64; + struct cvmx_gmxx_rxx_frm_max_s { + uint64_t reserved_16_63:48; + uint64_t len:16; + } s; + struct cvmx_gmxx_rxx_frm_max_s cn30xx; + struct cvmx_gmxx_rxx_frm_max_s cn31xx; + struct cvmx_gmxx_rxx_frm_max_s cn38xx; + struct cvmx_gmxx_rxx_frm_max_s cn38xxp2; + struct cvmx_gmxx_rxx_frm_max_s cn58xx; + struct cvmx_gmxx_rxx_frm_max_s cn58xxp1; +}; + +union cvmx_gmxx_rxx_frm_min { + uint64_t u64; + struct cvmx_gmxx_rxx_frm_min_s { + uint64_t reserved_16_63:48; + uint64_t len:16; + } s; + struct cvmx_gmxx_rxx_frm_min_s cn30xx; + struct cvmx_gmxx_rxx_frm_min_s cn31xx; + struct cvmx_gmxx_rxx_frm_min_s cn38xx; + struct cvmx_gmxx_rxx_frm_min_s cn38xxp2; + struct cvmx_gmxx_rxx_frm_min_s cn58xx; + struct cvmx_gmxx_rxx_frm_min_s cn58xxp1; +}; + +union cvmx_gmxx_rxx_ifg { + uint64_t u64; + struct cvmx_gmxx_rxx_ifg_s { + uint64_t reserved_4_63:60; + uint64_t ifg:4; + } s; + struct cvmx_gmxx_rxx_ifg_s cn30xx; + struct cvmx_gmxx_rxx_ifg_s cn31xx; + struct cvmx_gmxx_rxx_ifg_s cn38xx; + struct cvmx_gmxx_rxx_ifg_s cn38xxp2; + struct cvmx_gmxx_rxx_ifg_s cn50xx; + struct cvmx_gmxx_rxx_ifg_s cn52xx; + struct cvmx_gmxx_rxx_ifg_s cn52xxp1; + struct cvmx_gmxx_rxx_ifg_s cn56xx; + struct cvmx_gmxx_rxx_ifg_s cn56xxp1; + struct cvmx_gmxx_rxx_ifg_s cn58xx; + struct cvmx_gmxx_rxx_ifg_s cn58xxp1; +}; + +union cvmx_gmxx_rxx_int_en { + uint64_t u64; + struct cvmx_gmxx_rxx_int_en_s { + uint64_t reserved_29_63:35; + uint64_t hg2cc:1; + uint64_t hg2fld:1; + uint64_t undat:1; + uint64_t uneop:1; + uint64_t unsop:1; + uint64_t bad_term:1; + uint64_t bad_seq:1; + uint64_t rem_fault:1; + uint64_t loc_fault:1; + uint64_t pause_drp:1; + uint64_t phy_dupx:1; + uint64_t phy_spd:1; + uint64_t phy_link:1; + uint64_t ifgerr:1; + uint64_t coldet:1; + uint64_t falerr:1; + uint64_t rsverr:1; + uint64_t pcterr:1; + uint64_t ovrerr:1; + uint64_t niberr:1; + uint64_t skperr:1; + uint64_t rcverr:1; + uint64_t lenerr:1; + uint64_t alnerr:1; + uint64_t fcserr:1; + uint64_t jabber:1; + uint64_t maxerr:1; + uint64_t carext:1; + uint64_t minerr:1; + } s; + struct cvmx_gmxx_rxx_int_en_cn30xx { + uint64_t reserved_19_63:45; + uint64_t phy_dupx:1; + uint64_t phy_spd:1; + uint64_t phy_link:1; + uint64_t ifgerr:1; + uint64_t coldet:1; + uint64_t falerr:1; + uint64_t rsverr:1; + uint64_t pcterr:1; + uint64_t ovrerr:1; + uint64_t niberr:1; + uint64_t skperr:1; + uint64_t rcverr:1; + uint64_t lenerr:1; + uint64_t alnerr:1; + uint64_t fcserr:1; + uint64_t jabber:1; + uint64_t maxerr:1; + uint64_t carext:1; + uint64_t minerr:1; + } cn30xx; + struct cvmx_gmxx_rxx_int_en_cn30xx cn31xx; + struct cvmx_gmxx_rxx_int_en_cn30xx cn38xx; + struct cvmx_gmxx_rxx_int_en_cn30xx cn38xxp2; + struct cvmx_gmxx_rxx_int_en_cn50xx { + uint64_t reserved_20_63:44; + uint64_t pause_drp:1; + uint64_t phy_dupx:1; + uint64_t phy_spd:1; + uint64_t phy_link:1; + uint64_t ifgerr:1; + uint64_t coldet:1; + uint64_t falerr:1; + uint64_t rsverr:1; + uint64_t pcterr:1; + uint64_t ovrerr:1; + uint64_t niberr:1; + uint64_t skperr:1; + uint64_t rcverr:1; + uint64_t reserved_6_6:1; + uint64_t alnerr:1; + uint64_t fcserr:1; + uint64_t jabber:1; + uint64_t reserved_2_2:1; + uint64_t carext:1; + uint64_t reserved_0_0:1; + } cn50xx; + struct cvmx_gmxx_rxx_int_en_cn52xx { + uint64_t reserved_29_63:35; + uint64_t hg2cc:1; + uint64_t hg2fld:1; + uint64_t undat:1; + uint64_t uneop:1; + uint64_t unsop:1; + uint64_t bad_term:1; + uint64_t bad_seq:1; + uint64_t rem_fault:1; + uint64_t loc_fault:1; + uint64_t pause_drp:1; + uint64_t reserved_16_18:3; + uint64_t ifgerr:1; + uint64_t coldet:1; + uint64_t falerr:1; + uint64_t rsverr:1; + uint64_t pcterr:1; + uint64_t ovrerr:1; + uint64_t reserved_9_9:1; + uint64_t skperr:1; + uint64_t rcverr:1; + uint64_t reserved_5_6:2; + uint64_t fcserr:1; + uint64_t jabber:1; + uint64_t reserved_2_2:1; + uint64_t carext:1; + uint64_t reserved_0_0:1; + } cn52xx; + struct cvmx_gmxx_rxx_int_en_cn52xx cn52xxp1; + struct cvmx_gmxx_rxx_int_en_cn52xx cn56xx; + struct cvmx_gmxx_rxx_int_en_cn56xxp1 { + uint64_t reserved_27_63:37; + uint64_t undat:1; + uint64_t uneop:1; + uint64_t unsop:1; + uint64_t bad_term:1; + uint64_t bad_seq:1; + uint64_t rem_fault:1; + uint64_t loc_fault:1; + uint64_t pause_drp:1; + uint64_t reserved_16_18:3; + uint64_t ifgerr:1; + uint64_t coldet:1; + uint64_t falerr:1; + uint64_t rsverr:1; + uint64_t pcterr:1; + uint64_t ovrerr:1; + uint64_t reserved_9_9:1; + uint64_t skperr:1; + uint64_t rcverr:1; + uint64_t reserved_5_6:2; + uint64_t fcserr:1; + uint64_t jabber:1; + uint64_t reserved_2_2:1; + uint64_t carext:1; + uint64_t reserved_0_0:1; + } cn56xxp1; + struct cvmx_gmxx_rxx_int_en_cn58xx { + uint64_t reserved_20_63:44; + uint64_t pause_drp:1; + uint64_t phy_dupx:1; + uint64_t phy_spd:1; + uint64_t phy_link:1; + uint64_t ifgerr:1; + uint64_t coldet:1; + uint64_t falerr:1; + uint64_t rsverr:1; + uint64_t pcterr:1; + uint64_t ovrerr:1; + uint64_t niberr:1; + uint64_t skperr:1; + uint64_t rcverr:1; + uint64_t lenerr:1; + uint64_t alnerr:1; + uint64_t fcserr:1; + uint64_t jabber:1; + uint64_t maxerr:1; + uint64_t carext:1; + uint64_t minerr:1; + } cn58xx; + struct cvmx_gmxx_rxx_int_en_cn58xx cn58xxp1; +}; + +union cvmx_gmxx_rxx_int_reg { + uint64_t u64; + struct cvmx_gmxx_rxx_int_reg_s { + uint64_t reserved_29_63:35; + uint64_t hg2cc:1; + uint64_t hg2fld:1; + uint64_t undat:1; + uint64_t uneop:1; + uint64_t unsop:1; + uint64_t bad_term:1; + uint64_t bad_seq:1; + uint64_t rem_fault:1; + uint64_t loc_fault:1; + uint64_t pause_drp:1; + uint64_t phy_dupx:1; + uint64_t phy_spd:1; + uint64_t phy_link:1; + uint64_t ifgerr:1; + uint64_t coldet:1; + uint64_t falerr:1; + uint64_t rsverr:1; + uint64_t pcterr:1; + uint64_t ovrerr:1; + uint64_t niberr:1; + uint64_t skperr:1; + uint64_t rcverr:1; + uint64_t lenerr:1; + uint64_t alnerr:1; + uint64_t fcserr:1; + uint64_t jabber:1; + uint64_t maxerr:1; + uint64_t carext:1; + uint64_t minerr:1; + } s; + struct cvmx_gmxx_rxx_int_reg_cn30xx { + uint64_t reserved_19_63:45; + uint64_t phy_dupx:1; + uint64_t phy_spd:1; + uint64_t phy_link:1; + uint64_t ifgerr:1; + uint64_t coldet:1; + uint64_t falerr:1; + uint64_t rsverr:1; + uint64_t pcterr:1; + uint64_t ovrerr:1; + uint64_t niberr:1; + uint64_t skperr:1; + uint64_t rcverr:1; + uint64_t lenerr:1; + uint64_t alnerr:1; + uint64_t fcserr:1; + uint64_t jabber:1; + uint64_t maxerr:1; + uint64_t carext:1; + uint64_t minerr:1; + } cn30xx; + struct cvmx_gmxx_rxx_int_reg_cn30xx cn31xx; + struct cvmx_gmxx_rxx_int_reg_cn30xx cn38xx; + struct cvmx_gmxx_rxx_int_reg_cn30xx cn38xxp2; + struct cvmx_gmxx_rxx_int_reg_cn50xx { + uint64_t reserved_20_63:44; + uint64_t pause_drp:1; + uint64_t phy_dupx:1; + uint64_t phy_spd:1; + uint64_t phy_link:1; + uint64_t ifgerr:1; + uint64_t coldet:1; + uint64_t falerr:1; + uint64_t rsverr:1; + uint64_t pcterr:1; + uint64_t ovrerr:1; + uint64_t niberr:1; + uint64_t skperr:1; + uint64_t rcverr:1; + uint64_t reserved_6_6:1; + uint64_t alnerr:1; + uint64_t fcserr:1; + uint64_t jabber:1; + uint64_t reserved_2_2:1; + uint64_t carext:1; + uint64_t reserved_0_0:1; + } cn50xx; + struct cvmx_gmxx_rxx_int_reg_cn52xx { + uint64_t reserved_29_63:35; + uint64_t hg2cc:1; + uint64_t hg2fld:1; + uint64_t undat:1; + uint64_t uneop:1; + uint64_t unsop:1; + uint64_t bad_term:1; + uint64_t bad_seq:1; + uint64_t rem_fault:1; + uint64_t loc_fault:1; + uint64_t pause_drp:1; + uint64_t reserved_16_18:3; + uint64_t ifgerr:1; + uint64_t coldet:1; + uint64_t falerr:1; + uint64_t rsverr:1; + uint64_t pcterr:1; + uint64_t ovrerr:1; + uint64_t reserved_9_9:1; + uint64_t skperr:1; + uint64_t rcverr:1; + uint64_t reserved_5_6:2; + uint64_t fcserr:1; + uint64_t jabber:1; + uint64_t reserved_2_2:1; + uint64_t carext:1; + uint64_t reserved_0_0:1; + } cn52xx; + struct cvmx_gmxx_rxx_int_reg_cn52xx cn52xxp1; + struct cvmx_gmxx_rxx_int_reg_cn52xx cn56xx; + struct cvmx_gmxx_rxx_int_reg_cn56xxp1 { + uint64_t reserved_27_63:37; + uint64_t undat:1; + uint64_t uneop:1; + uint64_t unsop:1; + uint64_t bad_term:1; + uint64_t bad_seq:1; + uint64_t rem_fault:1; + uint64_t loc_fault:1; + uint64_t pause_drp:1; + uint64_t reserved_16_18:3; + uint64_t ifgerr:1; + uint64_t coldet:1; + uint64_t falerr:1; + uint64_t rsverr:1; + uint64_t pcterr:1; + uint64_t ovrerr:1; + uint64_t reserved_9_9:1; + uint64_t skperr:1; + uint64_t rcverr:1; + uint64_t reserved_5_6:2; + uint64_t fcserr:1; + uint64_t jabber:1; + uint64_t reserved_2_2:1; + uint64_t carext:1; + uint64_t reserved_0_0:1; + } cn56xxp1; + struct cvmx_gmxx_rxx_int_reg_cn58xx { + uint64_t reserved_20_63:44; + uint64_t pause_drp:1; + uint64_t phy_dupx:1; + uint64_t phy_spd:1; + uint64_t phy_link:1; + uint64_t ifgerr:1; + uint64_t coldet:1; + uint64_t falerr:1; + uint64_t rsverr:1; + uint64_t pcterr:1; + uint64_t ovrerr:1; + uint64_t niberr:1; + uint64_t skperr:1; + uint64_t rcverr:1; + uint64_t lenerr:1; + uint64_t alnerr:1; + uint64_t fcserr:1; + uint64_t jabber:1; + uint64_t maxerr:1; + uint64_t carext:1; + uint64_t minerr:1; + } cn58xx; + struct cvmx_gmxx_rxx_int_reg_cn58xx cn58xxp1; +}; + +union cvmx_gmxx_rxx_jabber { + uint64_t u64; + struct cvmx_gmxx_rxx_jabber_s { + uint64_t reserved_16_63:48; + uint64_t cnt:16; + } s; + struct cvmx_gmxx_rxx_jabber_s cn30xx; + struct cvmx_gmxx_rxx_jabber_s cn31xx; + struct cvmx_gmxx_rxx_jabber_s cn38xx; + struct cvmx_gmxx_rxx_jabber_s cn38xxp2; + struct cvmx_gmxx_rxx_jabber_s cn50xx; + struct cvmx_gmxx_rxx_jabber_s cn52xx; + struct cvmx_gmxx_rxx_jabber_s cn52xxp1; + struct cvmx_gmxx_rxx_jabber_s cn56xx; + struct cvmx_gmxx_rxx_jabber_s cn56xxp1; + struct cvmx_gmxx_rxx_jabber_s cn58xx; + struct cvmx_gmxx_rxx_jabber_s cn58xxp1; +}; + +union cvmx_gmxx_rxx_pause_drop_time { + uint64_t u64; + struct cvmx_gmxx_rxx_pause_drop_time_s { + uint64_t reserved_16_63:48; + uint64_t status:16; + } s; + struct cvmx_gmxx_rxx_pause_drop_time_s cn50xx; + struct cvmx_gmxx_rxx_pause_drop_time_s cn52xx; + struct cvmx_gmxx_rxx_pause_drop_time_s cn52xxp1; + struct cvmx_gmxx_rxx_pause_drop_time_s cn56xx; + struct cvmx_gmxx_rxx_pause_drop_time_s cn56xxp1; + struct cvmx_gmxx_rxx_pause_drop_time_s cn58xx; + struct cvmx_gmxx_rxx_pause_drop_time_s cn58xxp1; +}; + +union cvmx_gmxx_rxx_rx_inbnd { + uint64_t u64; + struct cvmx_gmxx_rxx_rx_inbnd_s { + uint64_t reserved_4_63:60; + uint64_t duplex:1; + uint64_t speed:2; + uint64_t status:1; + } s; + struct cvmx_gmxx_rxx_rx_inbnd_s cn30xx; + struct cvmx_gmxx_rxx_rx_inbnd_s cn31xx; + struct cvmx_gmxx_rxx_rx_inbnd_s cn38xx; + struct cvmx_gmxx_rxx_rx_inbnd_s cn38xxp2; + struct cvmx_gmxx_rxx_rx_inbnd_s cn50xx; + struct cvmx_gmxx_rxx_rx_inbnd_s cn58xx; + struct cvmx_gmxx_rxx_rx_inbnd_s cn58xxp1; +}; + +union cvmx_gmxx_rxx_stats_ctl { + uint64_t u64; + struct cvmx_gmxx_rxx_stats_ctl_s { + uint64_t reserved_1_63:63; + uint64_t rd_clr:1; + } s; + struct cvmx_gmxx_rxx_stats_ctl_s cn30xx; + struct cvmx_gmxx_rxx_stats_ctl_s cn31xx; + struct cvmx_gmxx_rxx_stats_ctl_s cn38xx; + struct cvmx_gmxx_rxx_stats_ctl_s cn38xxp2; + struct cvmx_gmxx_rxx_stats_ctl_s cn50xx; + struct cvmx_gmxx_rxx_stats_ctl_s cn52xx; + struct cvmx_gmxx_rxx_stats_ctl_s cn52xxp1; + struct cvmx_gmxx_rxx_stats_ctl_s cn56xx; + struct cvmx_gmxx_rxx_stats_ctl_s cn56xxp1; + struct cvmx_gmxx_rxx_stats_ctl_s cn58xx; + struct cvmx_gmxx_rxx_stats_ctl_s cn58xxp1; +}; + +union cvmx_gmxx_rxx_stats_octs { + uint64_t u64; + struct cvmx_gmxx_rxx_stats_octs_s { + uint64_t reserved_48_63:16; + uint64_t cnt:48; + } s; + struct cvmx_gmxx_rxx_stats_octs_s cn30xx; + struct cvmx_gmxx_rxx_stats_octs_s cn31xx; + struct cvmx_gmxx_rxx_stats_octs_s cn38xx; + struct cvmx_gmxx_rxx_stats_octs_s cn38xxp2; + struct cvmx_gmxx_rxx_stats_octs_s cn50xx; + struct cvmx_gmxx_rxx_stats_octs_s cn52xx; + struct cvmx_gmxx_rxx_stats_octs_s cn52xxp1; + struct cvmx_gmxx_rxx_stats_octs_s cn56xx; + struct cvmx_gmxx_rxx_stats_octs_s cn56xxp1; + struct cvmx_gmxx_rxx_stats_octs_s cn58xx; + struct cvmx_gmxx_rxx_stats_octs_s cn58xxp1; +}; + +union cvmx_gmxx_rxx_stats_octs_ctl { + uint64_t u64; + struct cvmx_gmxx_rxx_stats_octs_ctl_s { + uint64_t reserved_48_63:16; + uint64_t cnt:48; + } s; + struct cvmx_gmxx_rxx_stats_octs_ctl_s cn30xx; + struct cvmx_gmxx_rxx_stats_octs_ctl_s cn31xx; + struct cvmx_gmxx_rxx_stats_octs_ctl_s cn38xx; + struct cvmx_gmxx_rxx_stats_octs_ctl_s cn38xxp2; + struct cvmx_gmxx_rxx_stats_octs_ctl_s cn50xx; + struct cvmx_gmxx_rxx_stats_octs_ctl_s cn52xx; + struct cvmx_gmxx_rxx_stats_octs_ctl_s cn52xxp1; + struct cvmx_gmxx_rxx_stats_octs_ctl_s cn56xx; + struct cvmx_gmxx_rxx_stats_octs_ctl_s cn56xxp1; + struct cvmx_gmxx_rxx_stats_octs_ctl_s cn58xx; + struct cvmx_gmxx_rxx_stats_octs_ctl_s cn58xxp1; +}; + +union cvmx_gmxx_rxx_stats_octs_dmac { + uint64_t u64; + struct cvmx_gmxx_rxx_stats_octs_dmac_s { + uint64_t reserved_48_63:16; + uint64_t cnt:48; + } s; + struct cvmx_gmxx_rxx_stats_octs_dmac_s cn30xx; + struct cvmx_gmxx_rxx_stats_octs_dmac_s cn31xx; + struct cvmx_gmxx_rxx_stats_octs_dmac_s cn38xx; + struct cvmx_gmxx_rxx_stats_octs_dmac_s cn38xxp2; + struct cvmx_gmxx_rxx_stats_octs_dmac_s cn50xx; + struct cvmx_gmxx_rxx_stats_octs_dmac_s cn52xx; + struct cvmx_gmxx_rxx_stats_octs_dmac_s cn52xxp1; + struct cvmx_gmxx_rxx_stats_octs_dmac_s cn56xx; + struct cvmx_gmxx_rxx_stats_octs_dmac_s cn56xxp1; + struct cvmx_gmxx_rxx_stats_octs_dmac_s cn58xx; + struct cvmx_gmxx_rxx_stats_octs_dmac_s cn58xxp1; +}; + +union cvmx_gmxx_rxx_stats_octs_drp { + uint64_t u64; + struct cvmx_gmxx_rxx_stats_octs_drp_s { + uint64_t reserved_48_63:16; + uint64_t cnt:48; + } s; + struct cvmx_gmxx_rxx_stats_octs_drp_s cn30xx; + struct cvmx_gmxx_rxx_stats_octs_drp_s cn31xx; + struct cvmx_gmxx_rxx_stats_octs_drp_s cn38xx; + struct cvmx_gmxx_rxx_stats_octs_drp_s cn38xxp2; + struct cvmx_gmxx_rxx_stats_octs_drp_s cn50xx; + struct cvmx_gmxx_rxx_stats_octs_drp_s cn52xx; + struct cvmx_gmxx_rxx_stats_octs_drp_s cn52xxp1; + struct cvmx_gmxx_rxx_stats_octs_drp_s cn56xx; + struct cvmx_gmxx_rxx_stats_octs_drp_s cn56xxp1; + struct cvmx_gmxx_rxx_stats_octs_drp_s cn58xx; + struct cvmx_gmxx_rxx_stats_octs_drp_s cn58xxp1; +}; + +union cvmx_gmxx_rxx_stats_pkts { + uint64_t u64; + struct cvmx_gmxx_rxx_stats_pkts_s { + uint64_t reserved_32_63:32; + uint64_t cnt:32; + } s; + struct cvmx_gmxx_rxx_stats_pkts_s cn30xx; + struct cvmx_gmxx_rxx_stats_pkts_s cn31xx; + struct cvmx_gmxx_rxx_stats_pkts_s cn38xx; + struct cvmx_gmxx_rxx_stats_pkts_s cn38xxp2; + struct cvmx_gmxx_rxx_stats_pkts_s cn50xx; + struct cvmx_gmxx_rxx_stats_pkts_s cn52xx; + struct cvmx_gmxx_rxx_stats_pkts_s cn52xxp1; + struct cvmx_gmxx_rxx_stats_pkts_s cn56xx; + struct cvmx_gmxx_rxx_stats_pkts_s cn56xxp1; + struct cvmx_gmxx_rxx_stats_pkts_s cn58xx; + struct cvmx_gmxx_rxx_stats_pkts_s cn58xxp1; +}; + +union cvmx_gmxx_rxx_stats_pkts_bad { + uint64_t u64; + struct cvmx_gmxx_rxx_stats_pkts_bad_s { + uint64_t reserved_32_63:32; + uint64_t cnt:32; + } s; + struct cvmx_gmxx_rxx_stats_pkts_bad_s cn30xx; + struct cvmx_gmxx_rxx_stats_pkts_bad_s cn31xx; + struct cvmx_gmxx_rxx_stats_pkts_bad_s cn38xx; + struct cvmx_gmxx_rxx_stats_pkts_bad_s cn38xxp2; + struct cvmx_gmxx_rxx_stats_pkts_bad_s cn50xx; + struct cvmx_gmxx_rxx_stats_pkts_bad_s cn52xx; + struct cvmx_gmxx_rxx_stats_pkts_bad_s cn52xxp1; + struct cvmx_gmxx_rxx_stats_pkts_bad_s cn56xx; + struct cvmx_gmxx_rxx_stats_pkts_bad_s cn56xxp1; + struct cvmx_gmxx_rxx_stats_pkts_bad_s cn58xx; + struct cvmx_gmxx_rxx_stats_pkts_bad_s cn58xxp1; +}; + +union cvmx_gmxx_rxx_stats_pkts_ctl { + uint64_t u64; + struct cvmx_gmxx_rxx_stats_pkts_ctl_s { + uint64_t reserved_32_63:32; + uint64_t cnt:32; + } s; + struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn30xx; + struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn31xx; + struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn38xx; + struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn38xxp2; + struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn50xx; + struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn52xx; + struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn52xxp1; + struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn56xx; + struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn56xxp1; + struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn58xx; + struct cvmx_gmxx_rxx_stats_pkts_ctl_s cn58xxp1; +}; + +union cvmx_gmxx_rxx_stats_pkts_dmac { + uint64_t u64; + struct cvmx_gmxx_rxx_stats_pkts_dmac_s { + uint64_t reserved_32_63:32; + uint64_t cnt:32; + } s; + struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn30xx; + struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn31xx; + struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn38xx; + struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn38xxp2; + struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn50xx; + struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn52xx; + struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn52xxp1; + struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn56xx; + struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn56xxp1; + struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn58xx; + struct cvmx_gmxx_rxx_stats_pkts_dmac_s cn58xxp1; +}; + +union cvmx_gmxx_rxx_stats_pkts_drp { + uint64_t u64; + struct cvmx_gmxx_rxx_stats_pkts_drp_s { + uint64_t reserved_32_63:32; + uint64_t cnt:32; + } s; + struct cvmx_gmxx_rxx_stats_pkts_drp_s cn30xx; + struct cvmx_gmxx_rxx_stats_pkts_drp_s cn31xx; + struct cvmx_gmxx_rxx_stats_pkts_drp_s cn38xx; + struct cvmx_gmxx_rxx_stats_pkts_drp_s cn38xxp2; + struct cvmx_gmxx_rxx_stats_pkts_drp_s cn50xx; + struct cvmx_gmxx_rxx_stats_pkts_drp_s cn52xx; + struct cvmx_gmxx_rxx_stats_pkts_drp_s cn52xxp1; + struct cvmx_gmxx_rxx_stats_pkts_drp_s cn56xx; + struct cvmx_gmxx_rxx_stats_pkts_drp_s cn56xxp1; + struct cvmx_gmxx_rxx_stats_pkts_drp_s cn58xx; + struct cvmx_gmxx_rxx_stats_pkts_drp_s cn58xxp1; +}; + +union cvmx_gmxx_rxx_udd_skp { + uint64_t u64; + struct cvmx_gmxx_rxx_udd_skp_s { + uint64_t reserved_9_63:55; + uint64_t fcssel:1; + uint64_t reserved_7_7:1; + uint64_t len:7; + } s; + struct cvmx_gmxx_rxx_udd_skp_s cn30xx; + struct cvmx_gmxx_rxx_udd_skp_s cn31xx; + struct cvmx_gmxx_rxx_udd_skp_s cn38xx; + struct cvmx_gmxx_rxx_udd_skp_s cn38xxp2; + struct cvmx_gmxx_rxx_udd_skp_s cn50xx; + struct cvmx_gmxx_rxx_udd_skp_s cn52xx; + struct cvmx_gmxx_rxx_udd_skp_s cn52xxp1; + struct cvmx_gmxx_rxx_udd_skp_s cn56xx; + struct cvmx_gmxx_rxx_udd_skp_s cn56xxp1; + struct cvmx_gmxx_rxx_udd_skp_s cn58xx; + struct cvmx_gmxx_rxx_udd_skp_s cn58xxp1; +}; + +union cvmx_gmxx_rx_bp_dropx { + uint64_t u64; + struct cvmx_gmxx_rx_bp_dropx_s { + uint64_t reserved_6_63:58; + uint64_t mark:6; + } s; + struct cvmx_gmxx_rx_bp_dropx_s cn30xx; + struct cvmx_gmxx_rx_bp_dropx_s cn31xx; + struct cvmx_gmxx_rx_bp_dropx_s cn38xx; + struct cvmx_gmxx_rx_bp_dropx_s cn38xxp2; + struct cvmx_gmxx_rx_bp_dropx_s cn50xx; + struct cvmx_gmxx_rx_bp_dropx_s cn52xx; + struct cvmx_gmxx_rx_bp_dropx_s cn52xxp1; + struct cvmx_gmxx_rx_bp_dropx_s cn56xx; + struct cvmx_gmxx_rx_bp_dropx_s cn56xxp1; + struct cvmx_gmxx_rx_bp_dropx_s cn58xx; + struct cvmx_gmxx_rx_bp_dropx_s cn58xxp1; +}; + +union cvmx_gmxx_rx_bp_offx { + uint64_t u64; + struct cvmx_gmxx_rx_bp_offx_s { + uint64_t reserved_6_63:58; + uint64_t mark:6; + } s; + struct cvmx_gmxx_rx_bp_offx_s cn30xx; + struct cvmx_gmxx_rx_bp_offx_s cn31xx; + struct cvmx_gmxx_rx_bp_offx_s cn38xx; + struct cvmx_gmxx_rx_bp_offx_s cn38xxp2; + struct cvmx_gmxx_rx_bp_offx_s cn50xx; + struct cvmx_gmxx_rx_bp_offx_s cn52xx; + struct cvmx_gmxx_rx_bp_offx_s cn52xxp1; + struct cvmx_gmxx_rx_bp_offx_s cn56xx; + struct cvmx_gmxx_rx_bp_offx_s cn56xxp1; + struct cvmx_gmxx_rx_bp_offx_s cn58xx; + struct cvmx_gmxx_rx_bp_offx_s cn58xxp1; +}; + +union cvmx_gmxx_rx_bp_onx { + uint64_t u64; + struct cvmx_gmxx_rx_bp_onx_s { + uint64_t reserved_9_63:55; + uint64_t mark:9; + } s; + struct cvmx_gmxx_rx_bp_onx_s cn30xx; + struct cvmx_gmxx_rx_bp_onx_s cn31xx; + struct cvmx_gmxx_rx_bp_onx_s cn38xx; + struct cvmx_gmxx_rx_bp_onx_s cn38xxp2; + struct cvmx_gmxx_rx_bp_onx_s cn50xx; + struct cvmx_gmxx_rx_bp_onx_s cn52xx; + struct cvmx_gmxx_rx_bp_onx_s cn52xxp1; + struct cvmx_gmxx_rx_bp_onx_s cn56xx; + struct cvmx_gmxx_rx_bp_onx_s cn56xxp1; + struct cvmx_gmxx_rx_bp_onx_s cn58xx; + struct cvmx_gmxx_rx_bp_onx_s cn58xxp1; +}; + +union cvmx_gmxx_rx_hg2_status { + uint64_t u64; + struct cvmx_gmxx_rx_hg2_status_s { + uint64_t reserved_48_63:16; + uint64_t phtim2go:16; + uint64_t xof:16; + uint64_t lgtim2go:16; + } s; + struct cvmx_gmxx_rx_hg2_status_s cn52xx; + struct cvmx_gmxx_rx_hg2_status_s cn52xxp1; + struct cvmx_gmxx_rx_hg2_status_s cn56xx; +}; + +union cvmx_gmxx_rx_pass_en { + uint64_t u64; + struct cvmx_gmxx_rx_pass_en_s { + uint64_t reserved_16_63:48; + uint64_t en:16; + } s; + struct cvmx_gmxx_rx_pass_en_s cn38xx; + struct cvmx_gmxx_rx_pass_en_s cn38xxp2; + struct cvmx_gmxx_rx_pass_en_s cn58xx; + struct cvmx_gmxx_rx_pass_en_s cn58xxp1; +}; + +union cvmx_gmxx_rx_pass_mapx { + uint64_t u64; + struct cvmx_gmxx_rx_pass_mapx_s { + uint64_t reserved_4_63:60; + uint64_t dprt:4; + } s; + struct cvmx_gmxx_rx_pass_mapx_s cn38xx; + struct cvmx_gmxx_rx_pass_mapx_s cn38xxp2; + struct cvmx_gmxx_rx_pass_mapx_s cn58xx; + struct cvmx_gmxx_rx_pass_mapx_s cn58xxp1; +}; + +union cvmx_gmxx_rx_prt_info { + uint64_t u64; + struct cvmx_gmxx_rx_prt_info_s { + uint64_t reserved_32_63:32; + uint64_t drop:16; + uint64_t commit:16; + } s; + struct cvmx_gmxx_rx_prt_info_cn30xx { + uint64_t reserved_19_63:45; + uint64_t drop:3; + uint64_t reserved_3_15:13; + uint64_t commit:3; + } cn30xx; + struct cvmx_gmxx_rx_prt_info_cn30xx cn31xx; + struct cvmx_gmxx_rx_prt_info_s cn38xx; + struct cvmx_gmxx_rx_prt_info_cn30xx cn50xx; + struct cvmx_gmxx_rx_prt_info_cn52xx { + uint64_t reserved_20_63:44; + uint64_t drop:4; + uint64_t reserved_4_15:12; + uint64_t commit:4; + } cn52xx; + struct cvmx_gmxx_rx_prt_info_cn52xx cn52xxp1; + struct cvmx_gmxx_rx_prt_info_cn52xx cn56xx; + struct cvmx_gmxx_rx_prt_info_cn52xx cn56xxp1; + struct cvmx_gmxx_rx_prt_info_s cn58xx; + struct cvmx_gmxx_rx_prt_info_s cn58xxp1; +}; + +union cvmx_gmxx_rx_prts { + uint64_t u64; + struct cvmx_gmxx_rx_prts_s { + uint64_t reserved_3_63:61; + uint64_t prts:3; + } s; + struct cvmx_gmxx_rx_prts_s cn30xx; + struct cvmx_gmxx_rx_prts_s cn31xx; + struct cvmx_gmxx_rx_prts_s cn38xx; + struct cvmx_gmxx_rx_prts_s cn38xxp2; + struct cvmx_gmxx_rx_prts_s cn50xx; + struct cvmx_gmxx_rx_prts_s cn52xx; + struct cvmx_gmxx_rx_prts_s cn52xxp1; + struct cvmx_gmxx_rx_prts_s cn56xx; + struct cvmx_gmxx_rx_prts_s cn56xxp1; + struct cvmx_gmxx_rx_prts_s cn58xx; + struct cvmx_gmxx_rx_prts_s cn58xxp1; +}; + +union cvmx_gmxx_rx_tx_status { + uint64_t u64; + struct cvmx_gmxx_rx_tx_status_s { + uint64_t reserved_7_63:57; + uint64_t tx:3; + uint64_t reserved_3_3:1; + uint64_t rx:3; + } s; + struct cvmx_gmxx_rx_tx_status_s cn30xx; + struct cvmx_gmxx_rx_tx_status_s cn31xx; + struct cvmx_gmxx_rx_tx_status_s cn50xx; +}; + +union cvmx_gmxx_rx_xaui_bad_col { + uint64_t u64; + struct cvmx_gmxx_rx_xaui_bad_col_s { + uint64_t reserved_40_63:24; + uint64_t val:1; + uint64_t state:3; + uint64_t lane_rxc:4; + uint64_t lane_rxd:32; + } s; + struct cvmx_gmxx_rx_xaui_bad_col_s cn52xx; + struct cvmx_gmxx_rx_xaui_bad_col_s cn52xxp1; + struct cvmx_gmxx_rx_xaui_bad_col_s cn56xx; + struct cvmx_gmxx_rx_xaui_bad_col_s cn56xxp1; +}; + +union cvmx_gmxx_rx_xaui_ctl { + uint64_t u64; + struct cvmx_gmxx_rx_xaui_ctl_s { + uint64_t reserved_2_63:62; + uint64_t status:2; + } s; + struct cvmx_gmxx_rx_xaui_ctl_s cn52xx; + struct cvmx_gmxx_rx_xaui_ctl_s cn52xxp1; + struct cvmx_gmxx_rx_xaui_ctl_s cn56xx; + struct cvmx_gmxx_rx_xaui_ctl_s cn56xxp1; +}; + +union cvmx_gmxx_smacx { + uint64_t u64; + struct cvmx_gmxx_smacx_s { + uint64_t reserved_48_63:16; + uint64_t smac:48; + } s; + struct cvmx_gmxx_smacx_s cn30xx; + struct cvmx_gmxx_smacx_s cn31xx; + struct cvmx_gmxx_smacx_s cn38xx; + struct cvmx_gmxx_smacx_s cn38xxp2; + struct cvmx_gmxx_smacx_s cn50xx; + struct cvmx_gmxx_smacx_s cn52xx; + struct cvmx_gmxx_smacx_s cn52xxp1; + struct cvmx_gmxx_smacx_s cn56xx; + struct cvmx_gmxx_smacx_s cn56xxp1; + struct cvmx_gmxx_smacx_s cn58xx; + struct cvmx_gmxx_smacx_s cn58xxp1; +}; + +union cvmx_gmxx_stat_bp { + uint64_t u64; + struct cvmx_gmxx_stat_bp_s { + uint64_t reserved_17_63:47; + uint64_t bp:1; + uint64_t cnt:16; + } s; + struct cvmx_gmxx_stat_bp_s cn30xx; + struct cvmx_gmxx_stat_bp_s cn31xx; + struct cvmx_gmxx_stat_bp_s cn38xx; + struct cvmx_gmxx_stat_bp_s cn38xxp2; + struct cvmx_gmxx_stat_bp_s cn50xx; + struct cvmx_gmxx_stat_bp_s cn52xx; + struct cvmx_gmxx_stat_bp_s cn52xxp1; + struct cvmx_gmxx_stat_bp_s cn56xx; + struct cvmx_gmxx_stat_bp_s cn56xxp1; + struct cvmx_gmxx_stat_bp_s cn58xx; + struct cvmx_gmxx_stat_bp_s cn58xxp1; +}; + +union cvmx_gmxx_txx_append { + uint64_t u64; + struct cvmx_gmxx_txx_append_s { + uint64_t reserved_4_63:60; + uint64_t force_fcs:1; + uint64_t fcs:1; + uint64_t pad:1; + uint64_t preamble:1; + } s; + struct cvmx_gmxx_txx_append_s cn30xx; + struct cvmx_gmxx_txx_append_s cn31xx; + struct cvmx_gmxx_txx_append_s cn38xx; + struct cvmx_gmxx_txx_append_s cn38xxp2; + struct cvmx_gmxx_txx_append_s cn50xx; + struct cvmx_gmxx_txx_append_s cn52xx; + struct cvmx_gmxx_txx_append_s cn52xxp1; + struct cvmx_gmxx_txx_append_s cn56xx; + struct cvmx_gmxx_txx_append_s cn56xxp1; + struct cvmx_gmxx_txx_append_s cn58xx; + struct cvmx_gmxx_txx_append_s cn58xxp1; +}; + +union cvmx_gmxx_txx_burst { + uint64_t u64; + struct cvmx_gmxx_txx_burst_s { + uint64_t reserved_16_63:48; + uint64_t burst:16; + } s; + struct cvmx_gmxx_txx_burst_s cn30xx; + struct cvmx_gmxx_txx_burst_s cn31xx; + struct cvmx_gmxx_txx_burst_s cn38xx; + struct cvmx_gmxx_txx_burst_s cn38xxp2; + struct cvmx_gmxx_txx_burst_s cn50xx; + struct cvmx_gmxx_txx_burst_s cn52xx; + struct cvmx_gmxx_txx_burst_s cn52xxp1; + struct cvmx_gmxx_txx_burst_s cn56xx; + struct cvmx_gmxx_txx_burst_s cn56xxp1; + struct cvmx_gmxx_txx_burst_s cn58xx; + struct cvmx_gmxx_txx_burst_s cn58xxp1; +}; + +union cvmx_gmxx_txx_cbfc_xoff { + uint64_t u64; + struct cvmx_gmxx_txx_cbfc_xoff_s { + uint64_t reserved_16_63:48; + uint64_t xoff:16; + } s; + struct cvmx_gmxx_txx_cbfc_xoff_s cn52xx; + struct cvmx_gmxx_txx_cbfc_xoff_s cn56xx; +}; + +union cvmx_gmxx_txx_cbfc_xon { + uint64_t u64; + struct cvmx_gmxx_txx_cbfc_xon_s { + uint64_t reserved_16_63:48; + uint64_t xon:16; + } s; + struct cvmx_gmxx_txx_cbfc_xon_s cn52xx; + struct cvmx_gmxx_txx_cbfc_xon_s cn56xx; +}; + +union cvmx_gmxx_txx_clk { + uint64_t u64; + struct cvmx_gmxx_txx_clk_s { + uint64_t reserved_6_63:58; + uint64_t clk_cnt:6; + } s; + struct cvmx_gmxx_txx_clk_s cn30xx; + struct cvmx_gmxx_txx_clk_s cn31xx; + struct cvmx_gmxx_txx_clk_s cn38xx; + struct cvmx_gmxx_txx_clk_s cn38xxp2; + struct cvmx_gmxx_txx_clk_s cn50xx; + struct cvmx_gmxx_txx_clk_s cn58xx; + struct cvmx_gmxx_txx_clk_s cn58xxp1; +}; + +union cvmx_gmxx_txx_ctl { + uint64_t u64; + struct cvmx_gmxx_txx_ctl_s { + uint64_t reserved_2_63:62; + uint64_t xsdef_en:1; + uint64_t xscol_en:1; + } s; + struct cvmx_gmxx_txx_ctl_s cn30xx; + struct cvmx_gmxx_txx_ctl_s cn31xx; + struct cvmx_gmxx_txx_ctl_s cn38xx; + struct cvmx_gmxx_txx_ctl_s cn38xxp2; + struct cvmx_gmxx_txx_ctl_s cn50xx; + struct cvmx_gmxx_txx_ctl_s cn52xx; + struct cvmx_gmxx_txx_ctl_s cn52xxp1; + struct cvmx_gmxx_txx_ctl_s cn56xx; + struct cvmx_gmxx_txx_ctl_s cn56xxp1; + struct cvmx_gmxx_txx_ctl_s cn58xx; + struct cvmx_gmxx_txx_ctl_s cn58xxp1; +}; + +union cvmx_gmxx_txx_min_pkt { + uint64_t u64; + struct cvmx_gmxx_txx_min_pkt_s { + uint64_t reserved_8_63:56; + uint64_t min_size:8; + } s; + struct cvmx_gmxx_txx_min_pkt_s cn30xx; + struct cvmx_gmxx_txx_min_pkt_s cn31xx; + struct cvmx_gmxx_txx_min_pkt_s cn38xx; + struct cvmx_gmxx_txx_min_pkt_s cn38xxp2; + struct cvmx_gmxx_txx_min_pkt_s cn50xx; + struct cvmx_gmxx_txx_min_pkt_s cn52xx; + struct cvmx_gmxx_txx_min_pkt_s cn52xxp1; + struct cvmx_gmxx_txx_min_pkt_s cn56xx; + struct cvmx_gmxx_txx_min_pkt_s cn56xxp1; + struct cvmx_gmxx_txx_min_pkt_s cn58xx; + struct cvmx_gmxx_txx_min_pkt_s cn58xxp1; +}; + +union cvmx_gmxx_txx_pause_pkt_interval { + uint64_t u64; + struct cvmx_gmxx_txx_pause_pkt_interval_s { + uint64_t reserved_16_63:48; + uint64_t interval:16; + } s; + struct cvmx_gmxx_txx_pause_pkt_interval_s cn30xx; + struct cvmx_gmxx_txx_pause_pkt_interval_s cn31xx; + struct cvmx_gmxx_txx_pause_pkt_interval_s cn38xx; + struct cvmx_gmxx_txx_pause_pkt_interval_s cn38xxp2; + struct cvmx_gmxx_txx_pause_pkt_interval_s cn50xx; + struct cvmx_gmxx_txx_pause_pkt_interval_s cn52xx; + struct cvmx_gmxx_txx_pause_pkt_interval_s cn52xxp1; + struct cvmx_gmxx_txx_pause_pkt_interval_s cn56xx; + struct cvmx_gmxx_txx_pause_pkt_interval_s cn56xxp1; + struct cvmx_gmxx_txx_pause_pkt_interval_s cn58xx; + struct cvmx_gmxx_txx_pause_pkt_interval_s cn58xxp1; +}; + +union cvmx_gmxx_txx_pause_pkt_time { + uint64_t u64; + struct cvmx_gmxx_txx_pause_pkt_time_s { + uint64_t reserved_16_63:48; + uint64_t time:16; + } s; + struct cvmx_gmxx_txx_pause_pkt_time_s cn30xx; + struct cvmx_gmxx_txx_pause_pkt_time_s cn31xx; + struct cvmx_gmxx_txx_pause_pkt_time_s cn38xx; + struct cvmx_gmxx_txx_pause_pkt_time_s cn38xxp2; + struct cvmx_gmxx_txx_pause_pkt_time_s cn50xx; + struct cvmx_gmxx_txx_pause_pkt_time_s cn52xx; + struct cvmx_gmxx_txx_pause_pkt_time_s cn52xxp1; + struct cvmx_gmxx_txx_pause_pkt_time_s cn56xx; + struct cvmx_gmxx_txx_pause_pkt_time_s cn56xxp1; + struct cvmx_gmxx_txx_pause_pkt_time_s cn58xx; + struct cvmx_gmxx_txx_pause_pkt_time_s cn58xxp1; +}; + +union cvmx_gmxx_txx_pause_togo { + uint64_t u64; + struct cvmx_gmxx_txx_pause_togo_s { + uint64_t reserved_32_63:32; + uint64_t msg_time:16; + uint64_t time:16; + } s; + struct cvmx_gmxx_txx_pause_togo_cn30xx { + uint64_t reserved_16_63:48; + uint64_t time:16; + } cn30xx; + struct cvmx_gmxx_txx_pause_togo_cn30xx cn31xx; + struct cvmx_gmxx_txx_pause_togo_cn30xx cn38xx; + struct cvmx_gmxx_txx_pause_togo_cn30xx cn38xxp2; + struct cvmx_gmxx_txx_pause_togo_cn30xx cn50xx; + struct cvmx_gmxx_txx_pause_togo_s cn52xx; + struct cvmx_gmxx_txx_pause_togo_s cn52xxp1; + struct cvmx_gmxx_txx_pause_togo_s cn56xx; + struct cvmx_gmxx_txx_pause_togo_cn30xx cn56xxp1; + struct cvmx_gmxx_txx_pause_togo_cn30xx cn58xx; + struct cvmx_gmxx_txx_pause_togo_cn30xx cn58xxp1; +}; + +union cvmx_gmxx_txx_pause_zero { + uint64_t u64; + struct cvmx_gmxx_txx_pause_zero_s { + uint64_t reserved_1_63:63; + uint64_t send:1; + } s; + struct cvmx_gmxx_txx_pause_zero_s cn30xx; + struct cvmx_gmxx_txx_pause_zero_s cn31xx; + struct cvmx_gmxx_txx_pause_zero_s cn38xx; + struct cvmx_gmxx_txx_pause_zero_s cn38xxp2; + struct cvmx_gmxx_txx_pause_zero_s cn50xx; + struct cvmx_gmxx_txx_pause_zero_s cn52xx; + struct cvmx_gmxx_txx_pause_zero_s cn52xxp1; + struct cvmx_gmxx_txx_pause_zero_s cn56xx; + struct cvmx_gmxx_txx_pause_zero_s cn56xxp1; + struct cvmx_gmxx_txx_pause_zero_s cn58xx; + struct cvmx_gmxx_txx_pause_zero_s cn58xxp1; +}; + +union cvmx_gmxx_txx_sgmii_ctl { + uint64_t u64; + struct cvmx_gmxx_txx_sgmii_ctl_s { + uint64_t reserved_1_63:63; + uint64_t align:1; + } s; + struct cvmx_gmxx_txx_sgmii_ctl_s cn52xx; + struct cvmx_gmxx_txx_sgmii_ctl_s cn52xxp1; + struct cvmx_gmxx_txx_sgmii_ctl_s cn56xx; + struct cvmx_gmxx_txx_sgmii_ctl_s cn56xxp1; +}; + +union cvmx_gmxx_txx_slot { + uint64_t u64; + struct cvmx_gmxx_txx_slot_s { + uint64_t reserved_10_63:54; + uint64_t slot:10; + } s; + struct cvmx_gmxx_txx_slot_s cn30xx; + struct cvmx_gmxx_txx_slot_s cn31xx; + struct cvmx_gmxx_txx_slot_s cn38xx; + struct cvmx_gmxx_txx_slot_s cn38xxp2; + struct cvmx_gmxx_txx_slot_s cn50xx; + struct cvmx_gmxx_txx_slot_s cn52xx; + struct cvmx_gmxx_txx_slot_s cn52xxp1; + struct cvmx_gmxx_txx_slot_s cn56xx; + struct cvmx_gmxx_txx_slot_s cn56xxp1; + struct cvmx_gmxx_txx_slot_s cn58xx; + struct cvmx_gmxx_txx_slot_s cn58xxp1; +}; + +union cvmx_gmxx_txx_soft_pause { + uint64_t u64; + struct cvmx_gmxx_txx_soft_pause_s { + uint64_t reserved_16_63:48; + uint64_t time:16; + } s; + struct cvmx_gmxx_txx_soft_pause_s cn30xx; + struct cvmx_gmxx_txx_soft_pause_s cn31xx; + struct cvmx_gmxx_txx_soft_pause_s cn38xx; + struct cvmx_gmxx_txx_soft_pause_s cn38xxp2; + struct cvmx_gmxx_txx_soft_pause_s cn50xx; + struct cvmx_gmxx_txx_soft_pause_s cn52xx; + struct cvmx_gmxx_txx_soft_pause_s cn52xxp1; + struct cvmx_gmxx_txx_soft_pause_s cn56xx; + struct cvmx_gmxx_txx_soft_pause_s cn56xxp1; + struct cvmx_gmxx_txx_soft_pause_s cn58xx; + struct cvmx_gmxx_txx_soft_pause_s cn58xxp1; +}; + +union cvmx_gmxx_txx_stat0 { + uint64_t u64; + struct cvmx_gmxx_txx_stat0_s { + uint64_t xsdef:32; + uint64_t xscol:32; + } s; + struct cvmx_gmxx_txx_stat0_s cn30xx; + struct cvmx_gmxx_txx_stat0_s cn31xx; + struct cvmx_gmxx_txx_stat0_s cn38xx; + struct cvmx_gmxx_txx_stat0_s cn38xxp2; + struct cvmx_gmxx_txx_stat0_s cn50xx; + struct cvmx_gmxx_txx_stat0_s cn52xx; + struct cvmx_gmxx_txx_stat0_s cn52xxp1; + struct cvmx_gmxx_txx_stat0_s cn56xx; + struct cvmx_gmxx_txx_stat0_s cn56xxp1; + struct cvmx_gmxx_txx_stat0_s cn58xx; + struct cvmx_gmxx_txx_stat0_s cn58xxp1; +}; + +union cvmx_gmxx_txx_stat1 { + uint64_t u64; + struct cvmx_gmxx_txx_stat1_s { + uint64_t scol:32; + uint64_t mcol:32; + } s; + struct cvmx_gmxx_txx_stat1_s cn30xx; + struct cvmx_gmxx_txx_stat1_s cn31xx; + struct cvmx_gmxx_txx_stat1_s cn38xx; + struct cvmx_gmxx_txx_stat1_s cn38xxp2; + struct cvmx_gmxx_txx_stat1_s cn50xx; + struct cvmx_gmxx_txx_stat1_s cn52xx; + struct cvmx_gmxx_txx_stat1_s cn52xxp1; + struct cvmx_gmxx_txx_stat1_s cn56xx; + struct cvmx_gmxx_txx_stat1_s cn56xxp1; + struct cvmx_gmxx_txx_stat1_s cn58xx; + struct cvmx_gmxx_txx_stat1_s cn58xxp1; +}; + +union cvmx_gmxx_txx_stat2 { + uint64_t u64; + struct cvmx_gmxx_txx_stat2_s { + uint64_t reserved_48_63:16; + uint64_t octs:48; + } s; + struct cvmx_gmxx_txx_stat2_s cn30xx; + struct cvmx_gmxx_txx_stat2_s cn31xx; + struct cvmx_gmxx_txx_stat2_s cn38xx; + struct cvmx_gmxx_txx_stat2_s cn38xxp2; + struct cvmx_gmxx_txx_stat2_s cn50xx; + struct cvmx_gmxx_txx_stat2_s cn52xx; + struct cvmx_gmxx_txx_stat2_s cn52xxp1; + struct cvmx_gmxx_txx_stat2_s cn56xx; + struct cvmx_gmxx_txx_stat2_s cn56xxp1; + struct cvmx_gmxx_txx_stat2_s cn58xx; + struct cvmx_gmxx_txx_stat2_s cn58xxp1; +}; + +union cvmx_gmxx_txx_stat3 { + uint64_t u64; + struct cvmx_gmxx_txx_stat3_s { + uint64_t reserved_32_63:32; + uint64_t pkts:32; + } s; + struct cvmx_gmxx_txx_stat3_s cn30xx; + struct cvmx_gmxx_txx_stat3_s cn31xx; + struct cvmx_gmxx_txx_stat3_s cn38xx; + struct cvmx_gmxx_txx_stat3_s cn38xxp2; + struct cvmx_gmxx_txx_stat3_s cn50xx; + struct cvmx_gmxx_txx_stat3_s cn52xx; + struct cvmx_gmxx_txx_stat3_s cn52xxp1; + struct cvmx_gmxx_txx_stat3_s cn56xx; + struct cvmx_gmxx_txx_stat3_s cn56xxp1; + struct cvmx_gmxx_txx_stat3_s cn58xx; + struct cvmx_gmxx_txx_stat3_s cn58xxp1; +}; + +union cvmx_gmxx_txx_stat4 { + uint64_t u64; + struct cvmx_gmxx_txx_stat4_s { + uint64_t hist1:32; + uint64_t hist0:32; + } s; + struct cvmx_gmxx_txx_stat4_s cn30xx; + struct cvmx_gmxx_txx_stat4_s cn31xx; + struct cvmx_gmxx_txx_stat4_s cn38xx; + struct cvmx_gmxx_txx_stat4_s cn38xxp2; + struct cvmx_gmxx_txx_stat4_s cn50xx; + struct cvmx_gmxx_txx_stat4_s cn52xx; + struct cvmx_gmxx_txx_stat4_s cn52xxp1; + struct cvmx_gmxx_txx_stat4_s cn56xx; + struct cvmx_gmxx_txx_stat4_s cn56xxp1; + struct cvmx_gmxx_txx_stat4_s cn58xx; + struct cvmx_gmxx_txx_stat4_s cn58xxp1; +}; + +union cvmx_gmxx_txx_stat5 { + uint64_t u64; + struct cvmx_gmxx_txx_stat5_s { + uint64_t hist3:32; + uint64_t hist2:32; + } s; + struct cvmx_gmxx_txx_stat5_s cn30xx; + struct cvmx_gmxx_txx_stat5_s cn31xx; + struct cvmx_gmxx_txx_stat5_s cn38xx; + struct cvmx_gmxx_txx_stat5_s cn38xxp2; + struct cvmx_gmxx_txx_stat5_s cn50xx; + struct cvmx_gmxx_txx_stat5_s cn52xx; + struct cvmx_gmxx_txx_stat5_s cn52xxp1; + struct cvmx_gmxx_txx_stat5_s cn56xx; + struct cvmx_gmxx_txx_stat5_s cn56xxp1; + struct cvmx_gmxx_txx_stat5_s cn58xx; + struct cvmx_gmxx_txx_stat5_s cn58xxp1; +}; + +union cvmx_gmxx_txx_stat6 { + uint64_t u64; + struct cvmx_gmxx_txx_stat6_s { + uint64_t hist5:32; + uint64_t hist4:32; + } s; + struct cvmx_gmxx_txx_stat6_s cn30xx; + struct cvmx_gmxx_txx_stat6_s cn31xx; + struct cvmx_gmxx_txx_stat6_s cn38xx; + struct cvmx_gmxx_txx_stat6_s cn38xxp2; + struct cvmx_gmxx_txx_stat6_s cn50xx; + struct cvmx_gmxx_txx_stat6_s cn52xx; + struct cvmx_gmxx_txx_stat6_s cn52xxp1; + struct cvmx_gmxx_txx_stat6_s cn56xx; + struct cvmx_gmxx_txx_stat6_s cn56xxp1; + struct cvmx_gmxx_txx_stat6_s cn58xx; + struct cvmx_gmxx_txx_stat6_s cn58xxp1; +}; + +union cvmx_gmxx_txx_stat7 { + uint64_t u64; + struct cvmx_gmxx_txx_stat7_s { + uint64_t hist7:32; + uint64_t hist6:32; + } s; + struct cvmx_gmxx_txx_stat7_s cn30xx; + struct cvmx_gmxx_txx_stat7_s cn31xx; + struct cvmx_gmxx_txx_stat7_s cn38xx; + struct cvmx_gmxx_txx_stat7_s cn38xxp2; + struct cvmx_gmxx_txx_stat7_s cn50xx; + struct cvmx_gmxx_txx_stat7_s cn52xx; + struct cvmx_gmxx_txx_stat7_s cn52xxp1; + struct cvmx_gmxx_txx_stat7_s cn56xx; + struct cvmx_gmxx_txx_stat7_s cn56xxp1; + struct cvmx_gmxx_txx_stat7_s cn58xx; + struct cvmx_gmxx_txx_stat7_s cn58xxp1; +}; + +union cvmx_gmxx_txx_stat8 { + uint64_t u64; + struct cvmx_gmxx_txx_stat8_s { + uint64_t mcst:32; + uint64_t bcst:32; + } s; + struct cvmx_gmxx_txx_stat8_s cn30xx; + struct cvmx_gmxx_txx_stat8_s cn31xx; + struct cvmx_gmxx_txx_stat8_s cn38xx; + struct cvmx_gmxx_txx_stat8_s cn38xxp2; + struct cvmx_gmxx_txx_stat8_s cn50xx; + struct cvmx_gmxx_txx_stat8_s cn52xx; + struct cvmx_gmxx_txx_stat8_s cn52xxp1; + struct cvmx_gmxx_txx_stat8_s cn56xx; + struct cvmx_gmxx_txx_stat8_s cn56xxp1; + struct cvmx_gmxx_txx_stat8_s cn58xx; + struct cvmx_gmxx_txx_stat8_s cn58xxp1; +}; + +union cvmx_gmxx_txx_stat9 { + uint64_t u64; + struct cvmx_gmxx_txx_stat9_s { + uint64_t undflw:32; + uint64_t ctl:32; + } s; + struct cvmx_gmxx_txx_stat9_s cn30xx; + struct cvmx_gmxx_txx_stat9_s cn31xx; + struct cvmx_gmxx_txx_stat9_s cn38xx; + struct cvmx_gmxx_txx_stat9_s cn38xxp2; + struct cvmx_gmxx_txx_stat9_s cn50xx; + struct cvmx_gmxx_txx_stat9_s cn52xx; + struct cvmx_gmxx_txx_stat9_s cn52xxp1; + struct cvmx_gmxx_txx_stat9_s cn56xx; + struct cvmx_gmxx_txx_stat9_s cn56xxp1; + struct cvmx_gmxx_txx_stat9_s cn58xx; + struct cvmx_gmxx_txx_stat9_s cn58xxp1; +}; + +union cvmx_gmxx_txx_stats_ctl { + uint64_t u64; + struct cvmx_gmxx_txx_stats_ctl_s { + uint64_t reserved_1_63:63; + uint64_t rd_clr:1; + } s; + struct cvmx_gmxx_txx_stats_ctl_s cn30xx; + struct cvmx_gmxx_txx_stats_ctl_s cn31xx; + struct cvmx_gmxx_txx_stats_ctl_s cn38xx; + struct cvmx_gmxx_txx_stats_ctl_s cn38xxp2; + struct cvmx_gmxx_txx_stats_ctl_s cn50xx; + struct cvmx_gmxx_txx_stats_ctl_s cn52xx; + struct cvmx_gmxx_txx_stats_ctl_s cn52xxp1; + struct cvmx_gmxx_txx_stats_ctl_s cn56xx; + struct cvmx_gmxx_txx_stats_ctl_s cn56xxp1; + struct cvmx_gmxx_txx_stats_ctl_s cn58xx; + struct cvmx_gmxx_txx_stats_ctl_s cn58xxp1; +}; + +union cvmx_gmxx_txx_thresh { + uint64_t u64; + struct cvmx_gmxx_txx_thresh_s { + uint64_t reserved_9_63:55; + uint64_t cnt:9; + } s; + struct cvmx_gmxx_txx_thresh_cn30xx { + uint64_t reserved_7_63:57; + uint64_t cnt:7; + } cn30xx; + struct cvmx_gmxx_txx_thresh_cn30xx cn31xx; + struct cvmx_gmxx_txx_thresh_s cn38xx; + struct cvmx_gmxx_txx_thresh_s cn38xxp2; + struct cvmx_gmxx_txx_thresh_cn30xx cn50xx; + struct cvmx_gmxx_txx_thresh_s cn52xx; + struct cvmx_gmxx_txx_thresh_s cn52xxp1; + struct cvmx_gmxx_txx_thresh_s cn56xx; + struct cvmx_gmxx_txx_thresh_s cn56xxp1; + struct cvmx_gmxx_txx_thresh_s cn58xx; + struct cvmx_gmxx_txx_thresh_s cn58xxp1; +}; + +union cvmx_gmxx_tx_bp { + uint64_t u64; + struct cvmx_gmxx_tx_bp_s { + uint64_t reserved_4_63:60; + uint64_t bp:4; + } s; + struct cvmx_gmxx_tx_bp_cn30xx { + uint64_t reserved_3_63:61; + uint64_t bp:3; + } cn30xx; + struct cvmx_gmxx_tx_bp_cn30xx cn31xx; + struct cvmx_gmxx_tx_bp_s cn38xx; + struct cvmx_gmxx_tx_bp_s cn38xxp2; + struct cvmx_gmxx_tx_bp_cn30xx cn50xx; + struct cvmx_gmxx_tx_bp_s cn52xx; + struct cvmx_gmxx_tx_bp_s cn52xxp1; + struct cvmx_gmxx_tx_bp_s cn56xx; + struct cvmx_gmxx_tx_bp_s cn56xxp1; + struct cvmx_gmxx_tx_bp_s cn58xx; + struct cvmx_gmxx_tx_bp_s cn58xxp1; +}; + +union cvmx_gmxx_tx_clk_mskx { + uint64_t u64; + struct cvmx_gmxx_tx_clk_mskx_s { + uint64_t reserved_1_63:63; + uint64_t msk:1; + } s; + struct cvmx_gmxx_tx_clk_mskx_s cn30xx; + struct cvmx_gmxx_tx_clk_mskx_s cn50xx; +}; + +union cvmx_gmxx_tx_col_attempt { + uint64_t u64; + struct cvmx_gmxx_tx_col_attempt_s { + uint64_t reserved_5_63:59; + uint64_t limit:5; + } s; + struct cvmx_gmxx_tx_col_attempt_s cn30xx; + struct cvmx_gmxx_tx_col_attempt_s cn31xx; + struct cvmx_gmxx_tx_col_attempt_s cn38xx; + struct cvmx_gmxx_tx_col_attempt_s cn38xxp2; + struct cvmx_gmxx_tx_col_attempt_s cn50xx; + struct cvmx_gmxx_tx_col_attempt_s cn52xx; + struct cvmx_gmxx_tx_col_attempt_s cn52xxp1; + struct cvmx_gmxx_tx_col_attempt_s cn56xx; + struct cvmx_gmxx_tx_col_attempt_s cn56xxp1; + struct cvmx_gmxx_tx_col_attempt_s cn58xx; + struct cvmx_gmxx_tx_col_attempt_s cn58xxp1; +}; + +union cvmx_gmxx_tx_corrupt { + uint64_t u64; + struct cvmx_gmxx_tx_corrupt_s { + uint64_t reserved_4_63:60; + uint64_t corrupt:4; + } s; + struct cvmx_gmxx_tx_corrupt_cn30xx { + uint64_t reserved_3_63:61; + uint64_t corrupt:3; + } cn30xx; + struct cvmx_gmxx_tx_corrupt_cn30xx cn31xx; + struct cvmx_gmxx_tx_corrupt_s cn38xx; + struct cvmx_gmxx_tx_corrupt_s cn38xxp2; + struct cvmx_gmxx_tx_corrupt_cn30xx cn50xx; + struct cvmx_gmxx_tx_corrupt_s cn52xx; + struct cvmx_gmxx_tx_corrupt_s cn52xxp1; + struct cvmx_gmxx_tx_corrupt_s cn56xx; + struct cvmx_gmxx_tx_corrupt_s cn56xxp1; + struct cvmx_gmxx_tx_corrupt_s cn58xx; + struct cvmx_gmxx_tx_corrupt_s cn58xxp1; +}; + +union cvmx_gmxx_tx_hg2_reg1 { + uint64_t u64; + struct cvmx_gmxx_tx_hg2_reg1_s { + uint64_t reserved_16_63:48; + uint64_t tx_xof:16; + } s; + struct cvmx_gmxx_tx_hg2_reg1_s cn52xx; + struct cvmx_gmxx_tx_hg2_reg1_s cn52xxp1; + struct cvmx_gmxx_tx_hg2_reg1_s cn56xx; +}; + +union cvmx_gmxx_tx_hg2_reg2 { + uint64_t u64; + struct cvmx_gmxx_tx_hg2_reg2_s { + uint64_t reserved_16_63:48; + uint64_t tx_xon:16; + } s; + struct cvmx_gmxx_tx_hg2_reg2_s cn52xx; + struct cvmx_gmxx_tx_hg2_reg2_s cn52xxp1; + struct cvmx_gmxx_tx_hg2_reg2_s cn56xx; +}; + +union cvmx_gmxx_tx_ifg { + uint64_t u64; + struct cvmx_gmxx_tx_ifg_s { + uint64_t reserved_8_63:56; + uint64_t ifg2:4; + uint64_t ifg1:4; + } s; + struct cvmx_gmxx_tx_ifg_s cn30xx; + struct cvmx_gmxx_tx_ifg_s cn31xx; + struct cvmx_gmxx_tx_ifg_s cn38xx; + struct cvmx_gmxx_tx_ifg_s cn38xxp2; + struct cvmx_gmxx_tx_ifg_s cn50xx; + struct cvmx_gmxx_tx_ifg_s cn52xx; + struct cvmx_gmxx_tx_ifg_s cn52xxp1; + struct cvmx_gmxx_tx_ifg_s cn56xx; + struct cvmx_gmxx_tx_ifg_s cn56xxp1; + struct cvmx_gmxx_tx_ifg_s cn58xx; + struct cvmx_gmxx_tx_ifg_s cn58xxp1; +}; + +union cvmx_gmxx_tx_int_en { + uint64_t u64; + struct cvmx_gmxx_tx_int_en_s { + uint64_t reserved_20_63:44; + uint64_t late_col:4; + uint64_t xsdef:4; + uint64_t xscol:4; + uint64_t reserved_6_7:2; + uint64_t undflw:4; + uint64_t ncb_nxa:1; + uint64_t pko_nxa:1; + } s; + struct cvmx_gmxx_tx_int_en_cn30xx { + uint64_t reserved_19_63:45; + uint64_t late_col:3; + uint64_t reserved_15_15:1; + uint64_t xsdef:3; + uint64_t reserved_11_11:1; + uint64_t xscol:3; + uint64_t reserved_5_7:3; + uint64_t undflw:3; + uint64_t reserved_1_1:1; + uint64_t pko_nxa:1; + } cn30xx; + struct cvmx_gmxx_tx_int_en_cn31xx { + uint64_t reserved_15_63:49; + uint64_t xsdef:3; + uint64_t reserved_11_11:1; + uint64_t xscol:3; + uint64_t reserved_5_7:3; + uint64_t undflw:3; + uint64_t reserved_1_1:1; + uint64_t pko_nxa:1; + } cn31xx; + struct cvmx_gmxx_tx_int_en_s cn38xx; + struct cvmx_gmxx_tx_int_en_cn38xxp2 { + uint64_t reserved_16_63:48; + uint64_t xsdef:4; + uint64_t xscol:4; + uint64_t reserved_6_7:2; + uint64_t undflw:4; + uint64_t ncb_nxa:1; + uint64_t pko_nxa:1; + } cn38xxp2; + struct cvmx_gmxx_tx_int_en_cn30xx cn50xx; + struct cvmx_gmxx_tx_int_en_cn52xx { + uint64_t reserved_20_63:44; + uint64_t late_col:4; + uint64_t xsdef:4; + uint64_t xscol:4; + uint64_t reserved_6_7:2; + uint64_t undflw:4; + uint64_t reserved_1_1:1; + uint64_t pko_nxa:1; + } cn52xx; + struct cvmx_gmxx_tx_int_en_cn52xx cn52xxp1; + struct cvmx_gmxx_tx_int_en_cn52xx cn56xx; + struct cvmx_gmxx_tx_int_en_cn52xx cn56xxp1; + struct cvmx_gmxx_tx_int_en_s cn58xx; + struct cvmx_gmxx_tx_int_en_s cn58xxp1; +}; + +union cvmx_gmxx_tx_int_reg { + uint64_t u64; + struct cvmx_gmxx_tx_int_reg_s { + uint64_t reserved_20_63:44; + uint64_t late_col:4; + uint64_t xsdef:4; + uint64_t xscol:4; + uint64_t reserved_6_7:2; + uint64_t undflw:4; + uint64_t ncb_nxa:1; + uint64_t pko_nxa:1; + } s; + struct cvmx_gmxx_tx_int_reg_cn30xx { + uint64_t reserved_19_63:45; + uint64_t late_col:3; + uint64_t reserved_15_15:1; + uint64_t xsdef:3; + uint64_t reserved_11_11:1; + uint64_t xscol:3; + uint64_t reserved_5_7:3; + uint64_t undflw:3; + uint64_t reserved_1_1:1; + uint64_t pko_nxa:1; + } cn30xx; + struct cvmx_gmxx_tx_int_reg_cn31xx { + uint64_t reserved_15_63:49; + uint64_t xsdef:3; + uint64_t reserved_11_11:1; + uint64_t xscol:3; + uint64_t reserved_5_7:3; + uint64_t undflw:3; + uint64_t reserved_1_1:1; + uint64_t pko_nxa:1; + } cn31xx; + struct cvmx_gmxx_tx_int_reg_s cn38xx; + struct cvmx_gmxx_tx_int_reg_cn38xxp2 { + uint64_t reserved_16_63:48; + uint64_t xsdef:4; + uint64_t xscol:4; + uint64_t reserved_6_7:2; + uint64_t undflw:4; + uint64_t ncb_nxa:1; + uint64_t pko_nxa:1; + } cn38xxp2; + struct cvmx_gmxx_tx_int_reg_cn30xx cn50xx; + struct cvmx_gmxx_tx_int_reg_cn52xx { + uint64_t reserved_20_63:44; + uint64_t late_col:4; + uint64_t xsdef:4; + uint64_t xscol:4; + uint64_t reserved_6_7:2; + uint64_t undflw:4; + uint64_t reserved_1_1:1; + uint64_t pko_nxa:1; + } cn52xx; + struct cvmx_gmxx_tx_int_reg_cn52xx cn52xxp1; + struct cvmx_gmxx_tx_int_reg_cn52xx cn56xx; + struct cvmx_gmxx_tx_int_reg_cn52xx cn56xxp1; + struct cvmx_gmxx_tx_int_reg_s cn58xx; + struct cvmx_gmxx_tx_int_reg_s cn58xxp1; +}; + +union cvmx_gmxx_tx_jam { + uint64_t u64; + struct cvmx_gmxx_tx_jam_s { + uint64_t reserved_8_63:56; + uint64_t jam:8; + } s; + struct cvmx_gmxx_tx_jam_s cn30xx; + struct cvmx_gmxx_tx_jam_s cn31xx; + struct cvmx_gmxx_tx_jam_s cn38xx; + struct cvmx_gmxx_tx_jam_s cn38xxp2; + struct cvmx_gmxx_tx_jam_s cn50xx; + struct cvmx_gmxx_tx_jam_s cn52xx; + struct cvmx_gmxx_tx_jam_s cn52xxp1; + struct cvmx_gmxx_tx_jam_s cn56xx; + struct cvmx_gmxx_tx_jam_s cn56xxp1; + struct cvmx_gmxx_tx_jam_s cn58xx; + struct cvmx_gmxx_tx_jam_s cn58xxp1; +}; + +union cvmx_gmxx_tx_lfsr { + uint64_t u64; + struct cvmx_gmxx_tx_lfsr_s { + uint64_t reserved_16_63:48; + uint64_t lfsr:16; + } s; + struct cvmx_gmxx_tx_lfsr_s cn30xx; + struct cvmx_gmxx_tx_lfsr_s cn31xx; + struct cvmx_gmxx_tx_lfsr_s cn38xx; + struct cvmx_gmxx_tx_lfsr_s cn38xxp2; + struct cvmx_gmxx_tx_lfsr_s cn50xx; + struct cvmx_gmxx_tx_lfsr_s cn52xx; + struct cvmx_gmxx_tx_lfsr_s cn52xxp1; + struct cvmx_gmxx_tx_lfsr_s cn56xx; + struct cvmx_gmxx_tx_lfsr_s cn56xxp1; + struct cvmx_gmxx_tx_lfsr_s cn58xx; + struct cvmx_gmxx_tx_lfsr_s cn58xxp1; +}; + +union cvmx_gmxx_tx_ovr_bp { + uint64_t u64; + struct cvmx_gmxx_tx_ovr_bp_s { + uint64_t reserved_48_63:16; + uint64_t tx_prt_bp:16; + uint64_t reserved_12_31:20; + uint64_t en:4; + uint64_t bp:4; + uint64_t ign_full:4; + } s; + struct cvmx_gmxx_tx_ovr_bp_cn30xx { + uint64_t reserved_11_63:53; + uint64_t en:3; + uint64_t reserved_7_7:1; + uint64_t bp:3; + uint64_t reserved_3_3:1; + uint64_t ign_full:3; + } cn30xx; + struct cvmx_gmxx_tx_ovr_bp_cn30xx cn31xx; + struct cvmx_gmxx_tx_ovr_bp_cn38xx { + uint64_t reserved_12_63:52; + uint64_t en:4; + uint64_t bp:4; + uint64_t ign_full:4; + } cn38xx; + struct cvmx_gmxx_tx_ovr_bp_cn38xx cn38xxp2; + struct cvmx_gmxx_tx_ovr_bp_cn30xx cn50xx; + struct cvmx_gmxx_tx_ovr_bp_s cn52xx; + struct cvmx_gmxx_tx_ovr_bp_s cn52xxp1; + struct cvmx_gmxx_tx_ovr_bp_s cn56xx; + struct cvmx_gmxx_tx_ovr_bp_s cn56xxp1; + struct cvmx_gmxx_tx_ovr_bp_cn38xx cn58xx; + struct cvmx_gmxx_tx_ovr_bp_cn38xx cn58xxp1; +}; + +union cvmx_gmxx_tx_pause_pkt_dmac { + uint64_t u64; + struct cvmx_gmxx_tx_pause_pkt_dmac_s { + uint64_t reserved_48_63:16; + uint64_t dmac:48; + } s; + struct cvmx_gmxx_tx_pause_pkt_dmac_s cn30xx; + struct cvmx_gmxx_tx_pause_pkt_dmac_s cn31xx; + struct cvmx_gmxx_tx_pause_pkt_dmac_s cn38xx; + struct cvmx_gmxx_tx_pause_pkt_dmac_s cn38xxp2; + struct cvmx_gmxx_tx_pause_pkt_dmac_s cn50xx; + struct cvmx_gmxx_tx_pause_pkt_dmac_s cn52xx; + struct cvmx_gmxx_tx_pause_pkt_dmac_s cn52xxp1; + struct cvmx_gmxx_tx_pause_pkt_dmac_s cn56xx; + struct cvmx_gmxx_tx_pause_pkt_dmac_s cn56xxp1; + struct cvmx_gmxx_tx_pause_pkt_dmac_s cn58xx; + struct cvmx_gmxx_tx_pause_pkt_dmac_s cn58xxp1; +}; + +union cvmx_gmxx_tx_pause_pkt_type { + uint64_t u64; + struct cvmx_gmxx_tx_pause_pkt_type_s { + uint64_t reserved_16_63:48; + uint64_t type:16; + } s; + struct cvmx_gmxx_tx_pause_pkt_type_s cn30xx; + struct cvmx_gmxx_tx_pause_pkt_type_s cn31xx; + struct cvmx_gmxx_tx_pause_pkt_type_s cn38xx; + struct cvmx_gmxx_tx_pause_pkt_type_s cn38xxp2; + struct cvmx_gmxx_tx_pause_pkt_type_s cn50xx; + struct cvmx_gmxx_tx_pause_pkt_type_s cn52xx; + struct cvmx_gmxx_tx_pause_pkt_type_s cn52xxp1; + struct cvmx_gmxx_tx_pause_pkt_type_s cn56xx; + struct cvmx_gmxx_tx_pause_pkt_type_s cn56xxp1; + struct cvmx_gmxx_tx_pause_pkt_type_s cn58xx; + struct cvmx_gmxx_tx_pause_pkt_type_s cn58xxp1; +}; + +union cvmx_gmxx_tx_prts { + uint64_t u64; + struct cvmx_gmxx_tx_prts_s { + uint64_t reserved_5_63:59; + uint64_t prts:5; + } s; + struct cvmx_gmxx_tx_prts_s cn30xx; + struct cvmx_gmxx_tx_prts_s cn31xx; + struct cvmx_gmxx_tx_prts_s cn38xx; + struct cvmx_gmxx_tx_prts_s cn38xxp2; + struct cvmx_gmxx_tx_prts_s cn50xx; + struct cvmx_gmxx_tx_prts_s cn52xx; + struct cvmx_gmxx_tx_prts_s cn52xxp1; + struct cvmx_gmxx_tx_prts_s cn56xx; + struct cvmx_gmxx_tx_prts_s cn56xxp1; + struct cvmx_gmxx_tx_prts_s cn58xx; + struct cvmx_gmxx_tx_prts_s cn58xxp1; +}; + +union cvmx_gmxx_tx_spi_ctl { + uint64_t u64; + struct cvmx_gmxx_tx_spi_ctl_s { + uint64_t reserved_2_63:62; + uint64_t tpa_clr:1; + uint64_t cont_pkt:1; + } s; + struct cvmx_gmxx_tx_spi_ctl_s cn38xx; + struct cvmx_gmxx_tx_spi_ctl_s cn38xxp2; + struct cvmx_gmxx_tx_spi_ctl_s cn58xx; + struct cvmx_gmxx_tx_spi_ctl_s cn58xxp1; +}; + +union cvmx_gmxx_tx_spi_drain { + uint64_t u64; + struct cvmx_gmxx_tx_spi_drain_s { + uint64_t reserved_16_63:48; + uint64_t drain:16; + } s; + struct cvmx_gmxx_tx_spi_drain_s cn38xx; + struct cvmx_gmxx_tx_spi_drain_s cn58xx; + struct cvmx_gmxx_tx_spi_drain_s cn58xxp1; +}; + +union cvmx_gmxx_tx_spi_max { + uint64_t u64; + struct cvmx_gmxx_tx_spi_max_s { + uint64_t reserved_23_63:41; + uint64_t slice:7; + uint64_t max2:8; + uint64_t max1:8; + } s; + struct cvmx_gmxx_tx_spi_max_cn38xx { + uint64_t reserved_16_63:48; + uint64_t max2:8; + uint64_t max1:8; + } cn38xx; + struct cvmx_gmxx_tx_spi_max_cn38xx cn38xxp2; + struct cvmx_gmxx_tx_spi_max_s cn58xx; + struct cvmx_gmxx_tx_spi_max_s cn58xxp1; +}; + +union cvmx_gmxx_tx_spi_roundx { + uint64_t u64; + struct cvmx_gmxx_tx_spi_roundx_s { + uint64_t reserved_16_63:48; + uint64_t round:16; + } s; + struct cvmx_gmxx_tx_spi_roundx_s cn58xx; + struct cvmx_gmxx_tx_spi_roundx_s cn58xxp1; +}; + +union cvmx_gmxx_tx_spi_thresh { + uint64_t u64; + struct cvmx_gmxx_tx_spi_thresh_s { + uint64_t reserved_6_63:58; + uint64_t thresh:6; + } s; + struct cvmx_gmxx_tx_spi_thresh_s cn38xx; + struct cvmx_gmxx_tx_spi_thresh_s cn38xxp2; + struct cvmx_gmxx_tx_spi_thresh_s cn58xx; + struct cvmx_gmxx_tx_spi_thresh_s cn58xxp1; +}; + +union cvmx_gmxx_tx_xaui_ctl { + uint64_t u64; + struct cvmx_gmxx_tx_xaui_ctl_s { + uint64_t reserved_11_63:53; + uint64_t hg_pause_hgi:2; + uint64_t hg_en:1; + uint64_t reserved_7_7:1; + uint64_t ls_byp:1; + uint64_t ls:2; + uint64_t reserved_2_3:2; + uint64_t uni_en:1; + uint64_t dic_en:1; + } s; + struct cvmx_gmxx_tx_xaui_ctl_s cn52xx; + struct cvmx_gmxx_tx_xaui_ctl_s cn52xxp1; + struct cvmx_gmxx_tx_xaui_ctl_s cn56xx; + struct cvmx_gmxx_tx_xaui_ctl_s cn56xxp1; +}; + +union cvmx_gmxx_xaui_ext_loopback { + uint64_t u64; + struct cvmx_gmxx_xaui_ext_loopback_s { + uint64_t reserved_5_63:59; + uint64_t en:1; + uint64_t thresh:4; + } s; + struct cvmx_gmxx_xaui_ext_loopback_s cn52xx; + struct cvmx_gmxx_xaui_ext_loopback_s cn52xxp1; + struct cvmx_gmxx_xaui_ext_loopback_s cn56xx; + struct cvmx_gmxx_xaui_ext_loopback_s cn56xxp1; +}; + +#endif diff --git a/drivers/staging/octeon/cvmx-helper-board.c b/drivers/staging/octeon/cvmx-helper-board.c new file mode 100644 index 0000000..3085e38 --- /dev/null +++ b/drivers/staging/octeon/cvmx-helper-board.c @@ -0,0 +1,706 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * along with this file; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +/* + * + * Helper functions to abstract board specific data about + * network ports from the rest of the cvmx-helper files. + */ + +#include +#include + +#include "cvmx-config.h" + +#include "cvmx-mdio.h" + +#include "cvmx-helper.h" +#include "cvmx-helper-util.h" +#include "cvmx-helper-board.h" + +#include "cvmx-gmxx-defs.h" +#include "cvmx-asxx-defs.h" + +/** + * cvmx_override_board_link_get(int ipd_port) is a function + * pointer. It is meant to allow customization of the process of + * talking to a PHY to determine link speed. It is called every + * time a PHY must be polled for link status. Users should set + * this pointer to a function before calling any cvmx-helper + * operations. + */ +cvmx_helper_link_info_t(*cvmx_override_board_link_get) (int ipd_port) = + NULL; + +/** + * Return the MII PHY address associated with the given IPD + * port. A result of -1 means there isn't a MII capable PHY + * connected to this port. On chips supporting multiple MII + * busses the bus number is encoded in bits <15:8>. + * + * This function must be modified for every new Octeon board. + * Internally it uses switch statements based on the cvmx_sysinfo + * data to determine board types and revisions. It replies on the + * fact that every Octeon board receives a unique board type + * enumeration from the bootloader. + * + * @ipd_port: Octeon IPD port to get the MII address for. + * + * Returns MII PHY address and bus number or -1. + */ +int cvmx_helper_board_get_mii_address(int ipd_port) +{ + switch (cvmx_sysinfo_get()->board_type) { + case CVMX_BOARD_TYPE_SIM: + /* Simulator doesn't have MII */ + return -1; + case CVMX_BOARD_TYPE_EBT3000: + case CVMX_BOARD_TYPE_EBT5800: + case CVMX_BOARD_TYPE_THUNDER: + case CVMX_BOARD_TYPE_NICPRO2: + /* Interface 0 is SPI4, interface 1 is RGMII */ + if ((ipd_port >= 16) && (ipd_port < 20)) + return ipd_port - 16; + else + return -1; + case CVMX_BOARD_TYPE_KODAMA: + case CVMX_BOARD_TYPE_EBH3100: + case CVMX_BOARD_TYPE_HIKARI: + case CVMX_BOARD_TYPE_CN3010_EVB_HS5: + case CVMX_BOARD_TYPE_CN3005_EVB_HS5: + case CVMX_BOARD_TYPE_CN3020_EVB_HS5: + /* + * Port 0 is WAN connected to a PHY, Port 1 is GMII + * connected to a switch + */ + if (ipd_port == 0) + return 4; + else if (ipd_port == 1) + return 9; + else + return -1; + case CVMX_BOARD_TYPE_NAC38: + /* Board has 8 RGMII ports PHYs are 0-7 */ + if ((ipd_port >= 0) && (ipd_port < 4)) + return ipd_port; + else if ((ipd_port >= 16) && (ipd_port < 20)) + return ipd_port - 16 + 4; + else + return -1; + case CVMX_BOARD_TYPE_EBH3000: + /* Board has dual SPI4 and no PHYs */ + return -1; + case CVMX_BOARD_TYPE_EBH5200: + case CVMX_BOARD_TYPE_EBH5201: + case CVMX_BOARD_TYPE_EBT5200: + /* + * Board has 4 SGMII ports. The PHYs start right after the MII + * ports MII0 = 0, MII1 = 1, SGMII = 2-5. + */ + if ((ipd_port >= 0) && (ipd_port < 4)) + return ipd_port + 2; + else + return -1; + case CVMX_BOARD_TYPE_EBH5600: + case CVMX_BOARD_TYPE_EBH5601: + case CVMX_BOARD_TYPE_EBH5610: + /* + * Board has 8 SGMII ports. 4 connect out, two connect + * to a switch, and 2 loop to each other + */ + if ((ipd_port >= 0) && (ipd_port < 4)) + return ipd_port + 1; + else + return -1; + case CVMX_BOARD_TYPE_CUST_NB5: + if (ipd_port == 2) + return 4; + else + return -1; + case CVMX_BOARD_TYPE_NIC_XLE_4G: + /* Board has 4 SGMII ports. connected QLM3(interface 1) */ + if ((ipd_port >= 16) && (ipd_port < 20)) + return ipd_port - 16 + 1; + else + return -1; + case CVMX_BOARD_TYPE_BBGW_REF: + /* + * No PHYs are connected to Octeon, everything is + * through switch. + */ + return -1; + } + + /* Some unknown board. Somebody forgot to update this function... */ + cvmx_dprintf + ("cvmx_helper_board_get_mii_address: Unknown board type %d\n", + cvmx_sysinfo_get()->board_type); + return -1; +} + +/** + * This function is the board specific method of determining an + * ethernet ports link speed. Most Octeon boards have Marvell PHYs + * and are handled by the fall through case. This function must be + * updated for boards that don't have the normal Marvell PHYs. + * + * This function must be modified for every new Octeon board. + * Internally it uses switch statements based on the cvmx_sysinfo + * data to determine board types and revisions. It relies on the + * fact that every Octeon board receives a unique board type + * enumeration from the bootloader. + * + * @ipd_port: IPD input port associated with the port we want to get link + * status for. + * + * Returns The ports link status. If the link isn't fully resolved, this must + * return zero. + */ +cvmx_helper_link_info_t __cvmx_helper_board_link_get(int ipd_port) +{ + cvmx_helper_link_info_t result; + int phy_addr; + int is_broadcom_phy = 0; + + /* Give the user a chance to override the processing of this function */ + if (cvmx_override_board_link_get) + return cvmx_override_board_link_get(ipd_port); + + /* Unless we fix it later, all links are defaulted to down */ + result.u64 = 0; + + /* + * This switch statement should handle all ports that either don't use + * Marvell PHYS, or don't support in-band status. + */ + switch (cvmx_sysinfo_get()->board_type) { + case CVMX_BOARD_TYPE_SIM: + /* The simulator gives you a simulated 1Gbps full duplex link */ + result.s.link_up = 1; + result.s.full_duplex = 1; + result.s.speed = 1000; + return result; + case CVMX_BOARD_TYPE_EBH3100: + case CVMX_BOARD_TYPE_CN3010_EVB_HS5: + case CVMX_BOARD_TYPE_CN3005_EVB_HS5: + case CVMX_BOARD_TYPE_CN3020_EVB_HS5: + /* Port 1 on these boards is always Gigabit */ + if (ipd_port == 1) { + result.s.link_up = 1; + result.s.full_duplex = 1; + result.s.speed = 1000; + return result; + } + /* Fall through to the generic code below */ + break; + case CVMX_BOARD_TYPE_CUST_NB5: + /* Port 1 on these boards is always Gigabit */ + if (ipd_port == 1) { + result.s.link_up = 1; + result.s.full_duplex = 1; + result.s.speed = 1000; + return result; + } else /* The other port uses a broadcom PHY */ + is_broadcom_phy = 1; + break; + case CVMX_BOARD_TYPE_BBGW_REF: + /* Port 1 on these boards is always Gigabit */ + if (ipd_port == 2) { + /* Port 2 is not hooked up */ + result.u64 = 0; + return result; + } else { + /* Ports 0 and 1 connect to the switch */ + result.s.link_up = 1; + result.s.full_duplex = 1; + result.s.speed = 1000; + return result; + } + break; + } + + phy_addr = cvmx_helper_board_get_mii_address(ipd_port); + if (phy_addr != -1) { + if (is_broadcom_phy) { + /* + * Below we are going to read SMI/MDIO + * register 0x19 which works on Broadcom + * parts + */ + int phy_status = + cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, + 0x19); + switch ((phy_status >> 8) & 0x7) { + case 0: + result.u64 = 0; + break; + case 1: + result.s.link_up = 1; + result.s.full_duplex = 0; + result.s.speed = 10; + break; + case 2: + result.s.link_up = 1; + result.s.full_duplex = 1; + result.s.speed = 10; + break; + case 3: + result.s.link_up = 1; + result.s.full_duplex = 0; + result.s.speed = 100; + break; + case 4: + result.s.link_up = 1; + result.s.full_duplex = 1; + result.s.speed = 100; + break; + case 5: + result.s.link_up = 1; + result.s.full_duplex = 1; + result.s.speed = 100; + break; + case 6: + result.s.link_up = 1; + result.s.full_duplex = 0; + result.s.speed = 1000; + break; + case 7: + result.s.link_up = 1; + result.s.full_duplex = 1; + result.s.speed = 1000; + break; + } + } else { + /* + * This code assumes we are using a Marvell + * Gigabit PHY. All the speed information can + * be read from register 17 in one + * go. Somebody using a different PHY will + * need to handle it above in the board + * specific area. + */ + int phy_status = + cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, 17); + + /* + * If the resolve bit 11 isn't set, see if + * autoneg is turned off (bit 12, reg 0). The + * resolve bit doesn't get set properly when + * autoneg is off, so force it. + */ + if ((phy_status & (1 << 11)) == 0) { + int auto_status = + cvmx_mdio_read(phy_addr >> 8, + phy_addr & 0xff, 0); + if ((auto_status & (1 << 12)) == 0) + phy_status |= 1 << 11; + } + + /* + * Only return a link if the PHY has finished + * auto negotiation and set the resolved bit + * (bit 11) + */ + if (phy_status & (1 << 11)) { + result.s.link_up = 1; + result.s.full_duplex = ((phy_status >> 13) & 1); + switch ((phy_status >> 14) & 3) { + case 0: /* 10 Mbps */ + result.s.speed = 10; + break; + case 1: /* 100 Mbps */ + result.s.speed = 100; + break; + case 2: /* 1 Gbps */ + result.s.speed = 1000; + break; + case 3: /* Illegal */ + result.u64 = 0; + break; + } + } + } + } else if (OCTEON_IS_MODEL(OCTEON_CN3XXX) + || OCTEON_IS_MODEL(OCTEON_CN58XX) + || OCTEON_IS_MODEL(OCTEON_CN50XX)) { + /* + * We don't have a PHY address, so attempt to use + * in-band status. It is really important that boards + * not supporting in-band status never get + * here. Reading broken in-band status tends to do bad + * things + */ + union cvmx_gmxx_rxx_rx_inbnd inband_status; + int interface = cvmx_helper_get_interface_num(ipd_port); + int index = cvmx_helper_get_interface_index_num(ipd_port); + inband_status.u64 = + cvmx_read_csr(CVMX_GMXX_RXX_RX_INBND(index, interface)); + + result.s.link_up = inband_status.s.status; + result.s.full_duplex = inband_status.s.duplex; + switch (inband_status.s.speed) { + case 0: /* 10 Mbps */ + result.s.speed = 10; + break; + case 1: /* 100 Mbps */ + result.s.speed = 100; + break; + case 2: /* 1 Gbps */ + result.s.speed = 1000; + break; + case 3: /* Illegal */ + result.u64 = 0; + break; + } + } else { + /* + * We don't have a PHY address and we don't have + * in-band status. There is no way to determine the + * link speed. Return down assuming this port isn't + * wired + */ + result.u64 = 0; + } + + /* If link is down, return all fields as zero. */ + if (!result.s.link_up) + result.u64 = 0; + + return result; +} + +/** + * This function as a board specific method of changing the PHY + * speed, duplex, and auto-negotiation. This programs the PHY and + * not Octeon. This can be used to force Octeon's links to + * specific settings. + * + * @phy_addr: The address of the PHY to program + * @enable_autoneg: + * Non zero if you want to enable auto-negotiation. + * @link_info: Link speed to program. If the speed is zero and auto-negotiation + * is enabled, all possible negotiation speeds are advertised. + * + * Returns Zero on success, negative on failure + */ +int cvmx_helper_board_link_set_phy(int phy_addr, + cvmx_helper_board_set_phy_link_flags_types_t + link_flags, + cvmx_helper_link_info_t link_info) +{ + + /* Set the flow control settings based on link_flags */ + if ((link_flags & set_phy_link_flags_flow_control_mask) != + set_phy_link_flags_flow_control_dont_touch) { + cvmx_mdio_phy_reg_autoneg_adver_t reg_autoneg_adver; + reg_autoneg_adver.u16 = + cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, + CVMX_MDIO_PHY_REG_AUTONEG_ADVER); + reg_autoneg_adver.s.asymmetric_pause = + (link_flags & set_phy_link_flags_flow_control_mask) == + set_phy_link_flags_flow_control_enable; + reg_autoneg_adver.s.pause = + (link_flags & set_phy_link_flags_flow_control_mask) == + set_phy_link_flags_flow_control_enable; + cvmx_mdio_write(phy_addr >> 8, phy_addr & 0xff, + CVMX_MDIO_PHY_REG_AUTONEG_ADVER, + reg_autoneg_adver.u16); + } + + /* If speed isn't set and autoneg is on advertise all supported modes */ + if ((link_flags & set_phy_link_flags_autoneg) + && (link_info.s.speed == 0)) { + cvmx_mdio_phy_reg_control_t reg_control; + cvmx_mdio_phy_reg_status_t reg_status; + cvmx_mdio_phy_reg_autoneg_adver_t reg_autoneg_adver; + cvmx_mdio_phy_reg_extended_status_t reg_extended_status; + cvmx_mdio_phy_reg_control_1000_t reg_control_1000; + + reg_status.u16 = + cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, + CVMX_MDIO_PHY_REG_STATUS); + reg_autoneg_adver.u16 = + cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, + CVMX_MDIO_PHY_REG_AUTONEG_ADVER); + reg_autoneg_adver.s.advert_100base_t4 = + reg_status.s.capable_100base_t4; + reg_autoneg_adver.s.advert_10base_tx_full = + reg_status.s.capable_10_full; + reg_autoneg_adver.s.advert_10base_tx_half = + reg_status.s.capable_10_half; + reg_autoneg_adver.s.advert_100base_tx_full = + reg_status.s.capable_100base_x_full; + reg_autoneg_adver.s.advert_100base_tx_half = + reg_status.s.capable_100base_x_half; + cvmx_mdio_write(phy_addr >> 8, phy_addr & 0xff, + CVMX_MDIO_PHY_REG_AUTONEG_ADVER, + reg_autoneg_adver.u16); + if (reg_status.s.capable_extended_status) { + reg_extended_status.u16 = + cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, + CVMX_MDIO_PHY_REG_EXTENDED_STATUS); + reg_control_1000.u16 = + cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, + CVMX_MDIO_PHY_REG_CONTROL_1000); + reg_control_1000.s.advert_1000base_t_full = + reg_extended_status.s.capable_1000base_t_full; + reg_control_1000.s.advert_1000base_t_half = + reg_extended_status.s.capable_1000base_t_half; + cvmx_mdio_write(phy_addr >> 8, phy_addr & 0xff, + CVMX_MDIO_PHY_REG_CONTROL_1000, + reg_control_1000.u16); + } + reg_control.u16 = + cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, + CVMX_MDIO_PHY_REG_CONTROL); + reg_control.s.autoneg_enable = 1; + reg_control.s.restart_autoneg = 1; + cvmx_mdio_write(phy_addr >> 8, phy_addr & 0xff, + CVMX_MDIO_PHY_REG_CONTROL, reg_control.u16); + } else if ((link_flags & set_phy_link_flags_autoneg)) { + cvmx_mdio_phy_reg_control_t reg_control; + cvmx_mdio_phy_reg_status_t reg_status; + cvmx_mdio_phy_reg_autoneg_adver_t reg_autoneg_adver; + cvmx_mdio_phy_reg_extended_status_t reg_extended_status; + cvmx_mdio_phy_reg_control_1000_t reg_control_1000; + + reg_status.u16 = + cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, + CVMX_MDIO_PHY_REG_STATUS); + reg_autoneg_adver.u16 = + cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, + CVMX_MDIO_PHY_REG_AUTONEG_ADVER); + reg_autoneg_adver.s.advert_100base_t4 = 0; + reg_autoneg_adver.s.advert_10base_tx_full = 0; + reg_autoneg_adver.s.advert_10base_tx_half = 0; + reg_autoneg_adver.s.advert_100base_tx_full = 0; + reg_autoneg_adver.s.advert_100base_tx_half = 0; + if (reg_status.s.capable_extended_status) { + reg_extended_status.u16 = + cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, + CVMX_MDIO_PHY_REG_EXTENDED_STATUS); + reg_control_1000.u16 = + cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, + CVMX_MDIO_PHY_REG_CONTROL_1000); + reg_control_1000.s.advert_1000base_t_full = 0; + reg_control_1000.s.advert_1000base_t_half = 0; + } + switch (link_info.s.speed) { + case 10: + reg_autoneg_adver.s.advert_10base_tx_full = + link_info.s.full_duplex; + reg_autoneg_adver.s.advert_10base_tx_half = + !link_info.s.full_duplex; + break; + case 100: + reg_autoneg_adver.s.advert_100base_tx_full = + link_info.s.full_duplex; + reg_autoneg_adver.s.advert_100base_tx_half = + !link_info.s.full_duplex; + break; + case 1000: + reg_control_1000.s.advert_1000base_t_full = + link_info.s.full_duplex; + reg_control_1000.s.advert_1000base_t_half = + !link_info.s.full_duplex; + break; + } + cvmx_mdio_write(phy_addr >> 8, phy_addr & 0xff, + CVMX_MDIO_PHY_REG_AUTONEG_ADVER, + reg_autoneg_adver.u16); + if (reg_status.s.capable_extended_status) + cvmx_mdio_write(phy_addr >> 8, phy_addr & 0xff, + CVMX_MDIO_PHY_REG_CONTROL_1000, + reg_control_1000.u16); + reg_control.u16 = + cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, + CVMX_MDIO_PHY_REG_CONTROL); + reg_control.s.autoneg_enable = 1; + reg_control.s.restart_autoneg = 1; + cvmx_mdio_write(phy_addr >> 8, phy_addr & 0xff, + CVMX_MDIO_PHY_REG_CONTROL, reg_control.u16); + } else { + cvmx_mdio_phy_reg_control_t reg_control; + reg_control.u16 = + cvmx_mdio_read(phy_addr >> 8, phy_addr & 0xff, + CVMX_MDIO_PHY_REG_CONTROL); + reg_control.s.autoneg_enable = 0; + reg_control.s.restart_autoneg = 1; + reg_control.s.duplex = link_info.s.full_duplex; + if (link_info.s.speed == 1000) { + reg_control.s.speed_msb = 1; + reg_control.s.speed_lsb = 0; + } else if (link_info.s.speed == 100) { + reg_control.s.speed_msb = 0; + reg_control.s.speed_lsb = 1; + } else if (link_info.s.speed == 10) { + reg_control.s.speed_msb = 0; + reg_control.s.speed_lsb = 0; + } + cvmx_mdio_write(phy_addr >> 8, phy_addr & 0xff, + CVMX_MDIO_PHY_REG_CONTROL, reg_control.u16); + } + return 0; +} + +/** + * This function is called by cvmx_helper_interface_probe() after it + * determines the number of ports Octeon can support on a specific + * interface. This function is the per board location to override + * this value. It is called with the number of ports Octeon might + * support and should return the number of actual ports on the + * board. + * + * This function must be modifed for every new Octeon board. + * Internally it uses switch statements based on the cvmx_sysinfo + * data to determine board types and revisions. It relys on the + * fact that every Octeon board receives a unique board type + * enumeration from the bootloader. + * + * @interface: Interface to probe + * @supported_ports: + * Number of ports Octeon supports. + * + * Returns Number of ports the actual board supports. Many times this will + * simple be "support_ports". + */ +int __cvmx_helper_board_interface_probe(int interface, int supported_ports) +{ + switch (cvmx_sysinfo_get()->board_type) { + case CVMX_BOARD_TYPE_CN3005_EVB_HS5: + if (interface == 0) + return 2; + break; + case CVMX_BOARD_TYPE_BBGW_REF: + if (interface == 0) + return 2; + break; + case CVMX_BOARD_TYPE_NIC_XLE_4G: + if (interface == 0) + return 0; + break; + /* The 2nd interface on the EBH5600 is connected to the Marvel switch, + which we don't support. Disable ports connected to it */ + case CVMX_BOARD_TYPE_EBH5600: + if (interface == 1) + return 0; + break; + } + return supported_ports; +} + +/** + * Enable packet input/output from the hardware. This function is + * called after by cvmx_helper_packet_hardware_enable() to + * perform board specific initialization. For most boards + * nothing is needed. + * + * @interface: Interface to enable + * + * Returns Zero on success, negative on failure + */ +int __cvmx_helper_board_hardware_enable(int interface) +{ + if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_CN3005_EVB_HS5) { + if (interface == 0) { + /* Different config for switch port */ + cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX(1, interface), 0); + cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX(1, interface), 0); + /* + * Boards with gigabit WAN ports need a + * different setting that is compatible with + * 100 Mbit settings + */ + cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX(0, interface), + 0xc); + cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX(0, interface), + 0xc); + } + } else if (cvmx_sysinfo_get()->board_type == + CVMX_BOARD_TYPE_CN3010_EVB_HS5) { + /* + * Broadcom PHYs require differnet ASX + * clocks. Unfortunately many boards don't define a + * new board Id and simply mangle the + * CN3010_EVB_HS5 + */ + if (interface == 0) { + /* + * Some boards use a hacked up bootloader that + * identifies them as CN3010_EVB_HS5 + * evaluation boards. This leads to all kinds + * of configuration problems. Detect one + * case, and print warning, while trying to do + * the right thing. + */ + int phy_addr = cvmx_helper_board_get_mii_address(0); + if (phy_addr != -1) { + int phy_identifier = + cvmx_mdio_read(phy_addr >> 8, + phy_addr & 0xff, 0x2); + /* Is it a Broadcom PHY? */ + if (phy_identifier == 0x0143) { + cvmx_dprintf("\n"); + cvmx_dprintf("ERROR:\n"); + cvmx_dprintf + ("ERROR: Board type is CVMX_BOARD_TYPE_CN3010_EVB_HS5, but Broadcom PHY found.\n"); + cvmx_dprintf + ("ERROR: The board type is mis-configured, and software malfunctions are likely.\n"); + cvmx_dprintf + ("ERROR: All boards require a unique board type to identify them.\n"); + cvmx_dprintf("ERROR:\n"); + cvmx_dprintf("\n"); + cvmx_wait(1000000000); + cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX + (0, interface), 5); + cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX + (0, interface), 5); + } + } + } + } + return 0; +} + +cvmx_helper_board_usb_clock_types_t __cvmx_helper_board_usb_get_clock_type(void) +{ + switch (cvmx_sysinfo_get()->board_type) { + case CVMX_BOARD_TYPE_BBGW_REF: + return USB_CLOCK_TYPE_CRYSTAL_12; + } + return USB_CLOCK_TYPE_REF_48; +} + +int __cvmx_helper_board_usb_get_num_ports(int supported_ports) +{ + switch (cvmx_sysinfo_get()->board_type) { + case CVMX_BOARD_TYPE_NIC_XLE_4G: + return 0; + } + + return supported_ports; +} diff --git a/drivers/staging/octeon/cvmx-helper-board.h b/drivers/staging/octeon/cvmx-helper-board.h new file mode 100644 index 0000000..dc20b01 --- /dev/null +++ b/drivers/staging/octeon/cvmx-helper-board.h @@ -0,0 +1,180 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * along with this file; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +/** + * + * Helper functions to abstract board specific data about + * network ports from the rest of the cvmx-helper files. + * + */ +#ifndef __CVMX_HELPER_BOARD_H__ +#define __CVMX_HELPER_BOARD_H__ + +#include "cvmx-helper.h" + +typedef enum { + USB_CLOCK_TYPE_REF_12, + USB_CLOCK_TYPE_REF_24, + USB_CLOCK_TYPE_REF_48, + USB_CLOCK_TYPE_CRYSTAL_12, +} cvmx_helper_board_usb_clock_types_t; + +typedef enum { + set_phy_link_flags_autoneg = 0x1, + set_phy_link_flags_flow_control_dont_touch = 0x0 << 1, + set_phy_link_flags_flow_control_enable = 0x1 << 1, + set_phy_link_flags_flow_control_disable = 0x2 << 1, + set_phy_link_flags_flow_control_mask = 0x3 << 1, /* Mask for 2 bit wide flow control field */ +} cvmx_helper_board_set_phy_link_flags_types_t; + +/** + * cvmx_override_board_link_get(int ipd_port) is a function + * pointer. It is meant to allow customization of the process of + * talking to a PHY to determine link speed. It is called every + * time a PHY must be polled for link status. Users should set + * this pointer to a function before calling any cvmx-helper + * operations. + */ +extern cvmx_helper_link_info_t(*cvmx_override_board_link_get) (int ipd_port); + +/** + * Return the MII PHY address associated with the given IPD + * port. A result of -1 means there isn't a MII capable PHY + * connected to this port. On chips supporting multiple MII + * busses the bus number is encoded in bits <15:8>. + * + * This function must be modifed for every new Octeon board. + * Internally it uses switch statements based on the cvmx_sysinfo + * data to determine board types and revisions. It relys on the + * fact that every Octeon board receives a unique board type + * enumeration from the bootloader. + * + * @ipd_port: Octeon IPD port to get the MII address for. + * + * Returns MII PHY address and bus number or -1. + */ +extern int cvmx_helper_board_get_mii_address(int ipd_port); + +/** + * This function as a board specific method of changing the PHY + * speed, duplex, and autonegotiation. This programs the PHY and + * not Octeon. This can be used to force Octeon's links to + * specific settings. + * + * @phy_addr: The address of the PHY to program + * @link_flags: + * Flags to control autonegotiation. Bit 0 is autonegotiation + * enable/disable to maintain backware compatability. + * @link_info: Link speed to program. If the speed is zero and autonegotiation + * is enabled, all possible negotiation speeds are advertised. + * + * Returns Zero on success, negative on failure + */ +int cvmx_helper_board_link_set_phy(int phy_addr, + cvmx_helper_board_set_phy_link_flags_types_t + link_flags, + cvmx_helper_link_info_t link_info); + +/** + * This function is the board specific method of determining an + * ethernet ports link speed. Most Octeon boards have Marvell PHYs + * and are handled by the fall through case. This function must be + * updated for boards that don't have the normal Marvell PHYs. + * + * This function must be modifed for every new Octeon board. + * Internally it uses switch statements based on the cvmx_sysinfo + * data to determine board types and revisions. It relys on the + * fact that every Octeon board receives a unique board type + * enumeration from the bootloader. + * + * @ipd_port: IPD input port associated with the port we want to get link + * status for. + * + * Returns The ports link status. If the link isn't fully resolved, this must + * return zero. + */ +extern cvmx_helper_link_info_t __cvmx_helper_board_link_get(int ipd_port); + +/** + * This function is called by cvmx_helper_interface_probe() after it + * determines the number of ports Octeon can support on a specific + * interface. This function is the per board location to override + * this value. It is called with the number of ports Octeon might + * support and should return the number of actual ports on the + * board. + * + * This function must be modifed for every new Octeon board. + * Internally it uses switch statements based on the cvmx_sysinfo + * data to determine board types and revisions. It relys on the + * fact that every Octeon board receives a unique board type + * enumeration from the bootloader. + * + * @interface: Interface to probe + * @supported_ports: + * Number of ports Octeon supports. + * + * Returns Number of ports the actual board supports. Many times this will + * simple be "support_ports". + */ +extern int __cvmx_helper_board_interface_probe(int interface, + int supported_ports); + +/** + * Enable packet input/output from the hardware. This function is + * called after by cvmx_helper_packet_hardware_enable() to + * perform board specific initialization. For most boards + * nothing is needed. + * + * @interface: Interface to enable + * + * Returns Zero on success, negative on failure + */ +extern int __cvmx_helper_board_hardware_enable(int interface); + +/** + * Gets the clock type used for the USB block based on board type. + * Used by the USB code for auto configuration of clock type. + * + * Returns USB clock type enumeration + */ +cvmx_helper_board_usb_clock_types_t +__cvmx_helper_board_usb_get_clock_type(void); + +/** + * Adjusts the number of available USB ports on Octeon based on board + * specifics. + * + * @supported_ports: expected number of ports based on chip type; + * + * + * Returns number of available usb ports, based on board specifics. + * Return value is supported_ports if function does not + * override. + */ +int __cvmx_helper_board_usb_get_num_ports(int supported_ports); + +#endif /* __CVMX_HELPER_BOARD_H__ */ diff --git a/drivers/staging/octeon/cvmx-helper-fpa.c b/drivers/staging/octeon/cvmx-helper-fpa.c new file mode 100644 index 0000000..c239e5f --- /dev/null +++ b/drivers/staging/octeon/cvmx-helper-fpa.c @@ -0,0 +1,243 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * along with this file; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +/** + * @file + * + * Helper functions for FPA setup. + * + */ +#include "executive-config.h" +#include "cvmx-config.h" +#include "cvmx.h" +#include "cvmx-bootmem.h" +#include "cvmx-fpa.h" +#include "cvmx-helper-fpa.h" + +/** + * Allocate memory for and initialize a single FPA pool. + * + * @pool: Pool to initialize + * @buffer_size: Size of buffers to allocate in bytes + * @buffers: Number of buffers to put in the pool. Zero is allowed + * @name: String name of the pool for debugging purposes + * Returns Zero on success, non-zero on failure + */ +static int __cvmx_helper_initialize_fpa_pool(int pool, uint64_t buffer_size, + uint64_t buffers, const char *name) +{ + uint64_t current_num; + void *memory; + uint64_t align = CVMX_CACHE_LINE_SIZE; + + /* + * Align the allocation so that power of 2 size buffers are + * naturally aligned. + */ + while (align < buffer_size) + align = align << 1; + + if (buffers == 0) + return 0; + + current_num = cvmx_read_csr(CVMX_FPA_QUEX_AVAILABLE(pool)); + if (current_num) { + cvmx_dprintf("Fpa pool %d(%s) already has %llu buffers. " + "Skipping setup.\n", + pool, name, (unsigned long long)current_num); + return 0; + } + + memory = cvmx_bootmem_alloc(buffer_size * buffers, align); + if (memory == NULL) { + cvmx_dprintf("Out of memory initializing fpa pool %d(%s).\n", + pool, name); + return -1; + } + cvmx_fpa_setup_pool(pool, name, memory, buffer_size, buffers); + return 0; +} + +/** + * Allocate memory and initialize the FPA pools using memory + * from cvmx-bootmem. Specifying zero for the number of + * buffers will cause that FPA pool to not be setup. This is + * useful if you aren't using some of the hardware and want + * to save memory. Use cvmx_helper_initialize_fpa instead of + * this function directly. + * + * @pip_pool: Should always be CVMX_FPA_PACKET_POOL + * @pip_size: Should always be CVMX_FPA_PACKET_POOL_SIZE + * @pip_buffers: + * Number of packet buffers. + * @wqe_pool: Should always be CVMX_FPA_WQE_POOL + * @wqe_size: Should always be CVMX_FPA_WQE_POOL_SIZE + * @wqe_entries: + * Number of work queue entries + * @pko_pool: Should always be CVMX_FPA_OUTPUT_BUFFER_POOL + * @pko_size: Should always be CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE + * @pko_buffers: + * PKO Command buffers. You should at minimum have two per + * each PKO queue. + * @tim_pool: Should always be CVMX_FPA_TIMER_POOL + * @tim_size: Should always be CVMX_FPA_TIMER_POOL_SIZE + * @tim_buffers: + * TIM ring buffer command queues. At least two per timer bucket + * is recommened. + * @dfa_pool: Should always be CVMX_FPA_DFA_POOL + * @dfa_size: Should always be CVMX_FPA_DFA_POOL_SIZE + * @dfa_buffers: + * DFA command buffer. A relatively small (32 for example) + * number should work. + * Returns Zero on success, non-zero if out of memory + */ +static int __cvmx_helper_initialize_fpa(int pip_pool, int pip_size, + int pip_buffers, int wqe_pool, + int wqe_size, int wqe_entries, + int pko_pool, int pko_size, + int pko_buffers, int tim_pool, + int tim_size, int tim_buffers, + int dfa_pool, int dfa_size, + int dfa_buffers) +{ + int status; + + cvmx_fpa_enable(); + + if ((pip_buffers > 0) && (pip_buffers <= 64)) + cvmx_dprintf + ("Warning: %d packet buffers may not be enough for hardware" + " prefetch. 65 or more is recommended.\n", pip_buffers); + + if (pip_pool >= 0) { + status = + __cvmx_helper_initialize_fpa_pool(pip_pool, pip_size, + pip_buffers, + "Packet Buffers"); + if (status) + return status; + } + + if (wqe_pool >= 0) { + status = + __cvmx_helper_initialize_fpa_pool(wqe_pool, wqe_size, + wqe_entries, + "Work Queue Entries"); + if (status) + return status; + } + + if (pko_pool >= 0) { + status = + __cvmx_helper_initialize_fpa_pool(pko_pool, pko_size, + pko_buffers, + "PKO Command Buffers"); + if (status) + return status; + } + + if (tim_pool >= 0) { + status = + __cvmx_helper_initialize_fpa_pool(tim_pool, tim_size, + tim_buffers, + "TIM Command Buffers"); + if (status) + return status; + } + + if (dfa_pool >= 0) { + status = + __cvmx_helper_initialize_fpa_pool(dfa_pool, dfa_size, + dfa_buffers, + "DFA Command Buffers"); + if (status) + return status; + } + + return 0; +} + +/** + * Allocate memory and initialize the FPA pools using memory + * from cvmx-bootmem. Sizes of each element in the pools is + * controlled by the cvmx-config.h header file. Specifying + * zero for any parameter will cause that FPA pool to not be + * setup. This is useful if you aren't using some of the + * hardware and want to save memory. + * + * @packet_buffers: + * Number of packet buffers to allocate + * @work_queue_entries: + * Number of work queue entries + * @pko_buffers: + * PKO Command buffers. You should at minimum have two per + * each PKO queue. + * @tim_buffers: + * TIM ring buffer command queues. At least two per timer bucket + * is recommened. + * @dfa_buffers: + * DFA command buffer. A relatively small (32 for example) + * number should work. + * Returns Zero on success, non-zero if out of memory + */ +int cvmx_helper_initialize_fpa(int packet_buffers, int work_queue_entries, + int pko_buffers, int tim_buffers, + int dfa_buffers) +{ +#ifndef CVMX_FPA_PACKET_POOL +#define CVMX_FPA_PACKET_POOL -1 +#define CVMX_FPA_PACKET_POOL_SIZE 0 +#endif +#ifndef CVMX_FPA_WQE_POOL +#define CVMX_FPA_WQE_POOL -1 +#define CVMX_FPA_WQE_POOL_SIZE 0 +#endif +#ifndef CVMX_FPA_OUTPUT_BUFFER_POOL +#define CVMX_FPA_OUTPUT_BUFFER_POOL -1 +#define CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE 0 +#endif +#ifndef CVMX_FPA_TIMER_POOL +#define CVMX_FPA_TIMER_POOL -1 +#define CVMX_FPA_TIMER_POOL_SIZE 0 +#endif +#ifndef CVMX_FPA_DFA_POOL +#define CVMX_FPA_DFA_POOL -1 +#define CVMX_FPA_DFA_POOL_SIZE 0 +#endif + return __cvmx_helper_initialize_fpa(CVMX_FPA_PACKET_POOL, + CVMX_FPA_PACKET_POOL_SIZE, + packet_buffers, CVMX_FPA_WQE_POOL, + CVMX_FPA_WQE_POOL_SIZE, + work_queue_entries, + CVMX_FPA_OUTPUT_BUFFER_POOL, + CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE, + pko_buffers, CVMX_FPA_TIMER_POOL, + CVMX_FPA_TIMER_POOL_SIZE, + tim_buffers, CVMX_FPA_DFA_POOL, + CVMX_FPA_DFA_POOL_SIZE, + dfa_buffers); +} diff --git a/drivers/staging/octeon/cvmx-helper-fpa.h b/drivers/staging/octeon/cvmx-helper-fpa.h new file mode 100644 index 0000000..5ff8c93 --- /dev/null +++ b/drivers/staging/octeon/cvmx-helper-fpa.h @@ -0,0 +1,64 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * along with this file; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +/** + * @file + * + * Helper functions for FPA setup. + * + */ +#ifndef __CVMX_HELPER_H_FPA__ +#define __CVMX_HELPER_H_FPA__ + +/** + * Allocate memory and initialize the FPA pools using memory + * from cvmx-bootmem. Sizes of each element in the pools is + * controlled by the cvmx-config.h header file. Specifying + * zero for any parameter will cause that FPA pool to not be + * setup. This is useful if you aren't using some of the + * hardware and want to save memory. + * + * @packet_buffers: + * Number of packet buffers to allocate + * @work_queue_entries: + * Number of work queue entries + * @pko_buffers: + * PKO Command buffers. You should at minimum have two per + * each PKO queue. + * @tim_buffers: + * TIM ring buffer command queues. At least two per timer bucket + * is recommened. + * @dfa_buffers: + * DFA command buffer. A relatively small (32 for example) + * number should work. + * Returns Zero on success, non-zero if out of memory + */ +extern int cvmx_helper_initialize_fpa(int packet_buffers, + int work_queue_entries, int pko_buffers, + int tim_buffers, int dfa_buffers); + +#endif /* __CVMX_HELPER_H__ */ diff --git a/drivers/staging/octeon/cvmx-helper-loop.c b/drivers/staging/octeon/cvmx-helper-loop.c new file mode 100644 index 0000000..55a571a --- /dev/null +++ b/drivers/staging/octeon/cvmx-helper-loop.c @@ -0,0 +1,85 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * along with this file; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +/* + * Functions for LOOP initialization, configuration, + * and monitoring. + */ +#include + +#include "cvmx-config.h" + +#include "cvmx-helper.h" +#include "cvmx-pip-defs.h" + +/** + * Probe a LOOP interface and determine the number of ports + * connected to it. The LOOP interface should still be down + * after this call. + * + * @interface: Interface to probe + * + * Returns Number of ports on the interface. Zero to disable. + */ +int __cvmx_helper_loop_probe(int interface) +{ + union cvmx_ipd_sub_port_fcs ipd_sub_port_fcs; + int num_ports = 4; + int port; + + /* We need to disable length checking so packet < 64 bytes and jumbo + frames don't get errors */ + for (port = 0; port < num_ports; port++) { + union cvmx_pip_prt_cfgx port_cfg; + int ipd_port = cvmx_helper_get_ipd_port(interface, port); + port_cfg.u64 = cvmx_read_csr(CVMX_PIP_PRT_CFGX(ipd_port)); + port_cfg.s.maxerr_en = 0; + port_cfg.s.minerr_en = 0; + cvmx_write_csr(CVMX_PIP_PRT_CFGX(ipd_port), port_cfg.u64); + } + + /* Disable FCS stripping for loopback ports */ + ipd_sub_port_fcs.u64 = cvmx_read_csr(CVMX_IPD_SUB_PORT_FCS); + ipd_sub_port_fcs.s.port_bit2 = 0; + cvmx_write_csr(CVMX_IPD_SUB_PORT_FCS, ipd_sub_port_fcs.u64); + return num_ports; +} + +/** + * Bringup and enable a LOOP interface. After this call packet + * I/O should be fully functional. This is called with IPD + * enabled but PKO disabled. + * + * @interface: Interface to bring up + * + * Returns Zero on success, negative on failure + */ +int __cvmx_helper_loop_enable(int interface) +{ + /* Do nothing. */ + return 0; +} diff --git a/drivers/staging/octeon/cvmx-helper-loop.h b/drivers/staging/octeon/cvmx-helper-loop.h new file mode 100644 index 0000000..e646a6c --- /dev/null +++ b/drivers/staging/octeon/cvmx-helper-loop.h @@ -0,0 +1,59 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as published by + * the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, + * but AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or NONINFRINGEMENT. + * See the GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this file; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +/** + * @file + * + * Functions for LOOP initialization, configuration, + * and monitoring. + * + */ +#ifndef __CVMX_HELPER_LOOP_H__ +#define __CVMX_HELPER_LOOP_H__ + +/** + * Probe a LOOP interface and determine the number of ports + * connected to it. The LOOP interface should still be down after + * this call. + * + * @interface: Interface to probe + * + * Returns Number of ports on the interface. Zero to disable. + */ +extern int __cvmx_helper_loop_probe(int interface); + +/** + * Bringup and enable a LOOP interface. After this call packet + * I/O should be fully functional. This is called with IPD + * enabled but PKO disabled. + * + * @interface: Interface to bring up + * + * Returns Zero on success, negative on failure + */ +extern int __cvmx_helper_loop_enable(int interface); + +#endif diff --git a/drivers/staging/octeon/cvmx-helper-npi.c b/drivers/staging/octeon/cvmx-helper-npi.c new file mode 100644 index 0000000..7388a1e --- /dev/null +++ b/drivers/staging/octeon/cvmx-helper-npi.c @@ -0,0 +1,113 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * along with this file; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +/* + * Functions for NPI initialization, configuration, + * and monitoring. + */ +#include + +#include "cvmx-config.h" + +#include "cvmx-helper.h" + +#include "cvmx-pip-defs.h" + +/** + * Probe a NPI interface and determine the number of ports + * connected to it. The NPI interface should still be down + * after this call. + * + * @interface: Interface to probe + * + * Returns Number of ports on the interface. Zero to disable. + */ +int __cvmx_helper_npi_probe(int interface) +{ +#if CVMX_PKO_QUEUES_PER_PORT_PCI > 0 + if (OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)) + return 4; + else if (OCTEON_IS_MODEL(OCTEON_CN56XX) + && !OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X)) + /* The packet engines didn't exist before pass 2 */ + return 4; + else if (OCTEON_IS_MODEL(OCTEON_CN52XX) + && !OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X)) + /* The packet engines didn't exist before pass 2 */ + return 4; +#if 0 + /* + * Technically CN30XX, CN31XX, and CN50XX contain packet + * engines, but nobody ever uses them. Since this is the case, + * we disable them here. + */ + else if (OCTEON_IS_MODEL(OCTEON_CN31XX) + || OCTEON_IS_MODEL(OCTEON_CN50XX)) + return 2; + else if (OCTEON_IS_MODEL(OCTEON_CN30XX)) + return 1; +#endif +#endif + return 0; +} + +/** + * Bringup and enable a NPI interface. After this call packet + * I/O should be fully functional. This is called with IPD + * enabled but PKO disabled. + * + * @interface: Interface to bring up + * + * Returns Zero on success, negative on failure + */ +int __cvmx_helper_npi_enable(int interface) +{ + /* + * On CN50XX, CN52XX, and CN56XX we need to disable length + * checking so packet < 64 bytes and jumbo frames don't get + * errors. + */ + if (!OCTEON_IS_MODEL(OCTEON_CN3XXX) && + !OCTEON_IS_MODEL(OCTEON_CN58XX)) { + int num_ports = cvmx_helper_ports_on_interface(interface); + int port; + for (port = 0; port < num_ports; port++) { + union cvmx_pip_prt_cfgx port_cfg; + int ipd_port = + cvmx_helper_get_ipd_port(interface, port); + port_cfg.u64 = + cvmx_read_csr(CVMX_PIP_PRT_CFGX(ipd_port)); + port_cfg.s.maxerr_en = 0; + port_cfg.s.minerr_en = 0; + cvmx_write_csr(CVMX_PIP_PRT_CFGX(ipd_port), + port_cfg.u64); + } + } + + /* Enables are controlled by the remote host, so nothing to do here */ + return 0; +} diff --git a/drivers/staging/octeon/cvmx-helper-npi.h b/drivers/staging/octeon/cvmx-helper-npi.h new file mode 100644 index 0000000..908e7b0 --- /dev/null +++ b/drivers/staging/octeon/cvmx-helper-npi.h @@ -0,0 +1,60 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * along with this file; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +/** + * @file + * + * Functions for NPI initialization, configuration, + * and monitoring. + * + */ +#ifndef __CVMX_HELPER_NPI_H__ +#define __CVMX_HELPER_NPI_H__ + +/** + * Probe a NPI interface and determine the number of ports + * connected to it. The NPI interface should still be down after + * this call. + * + * @interface: Interface to probe + * + * Returns Number of ports on the interface. Zero to disable. + */ +extern int __cvmx_helper_npi_probe(int interface); + +/** + * Bringup and enable a NPI interface. After this call packet + * I/O should be fully functional. This is called with IPD + * enabled but PKO disabled. + * + * @interface: Interface to bring up + * + * Returns Zero on success, negative on failure + */ +extern int __cvmx_helper_npi_enable(int interface); + +#endif diff --git a/drivers/staging/octeon/cvmx-helper-rgmii.c b/drivers/staging/octeon/cvmx-helper-rgmii.c new file mode 100644 index 0000000..aa2d5d7 --- /dev/null +++ b/drivers/staging/octeon/cvmx-helper-rgmii.c @@ -0,0 +1,525 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * along with this file; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +/* + * Functions for RGMII/GMII/MII initialization, configuration, + * and monitoring. + */ +#include + +#include "cvmx-config.h" + + +#include "cvmx-mdio.h" +#include "cvmx-pko.h" +#include "cvmx-helper.h" +#include "cvmx-helper-board.h" + +#include +#include "cvmx-gmxx-defs.h" +#include "cvmx-asxx-defs.h" +#include "cvmx-dbg-defs.h" + +void __cvmx_interrupt_gmxx_enable(int interface); +void __cvmx_interrupt_asxx_enable(int block); + +/** + * Probe RGMII ports and determine the number present + * + * @interface: Interface to probe + * + * Returns Number of RGMII/GMII/MII ports (0-4). + */ +int __cvmx_helper_rgmii_probe(int interface) +{ + int num_ports = 0; + union cvmx_gmxx_inf_mode mode; + mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface)); + + if (mode.s.type) { + if (OCTEON_IS_MODEL(OCTEON_CN38XX) + || OCTEON_IS_MODEL(OCTEON_CN58XX)) { + cvmx_dprintf("ERROR: RGMII initialize called in " + "SPI interface\n"); + } else if (OCTEON_IS_MODEL(OCTEON_CN31XX) + || OCTEON_IS_MODEL(OCTEON_CN30XX) + || OCTEON_IS_MODEL(OCTEON_CN50XX)) { + /* + * On these chips "type" says we're in + * GMII/MII mode. This limits us to 2 ports + */ + num_ports = 2; + } else { + cvmx_dprintf("ERROR: Unsupported Octeon model in %s\n", + __func__); + } + } else { + if (OCTEON_IS_MODEL(OCTEON_CN38XX) + || OCTEON_IS_MODEL(OCTEON_CN58XX)) { + num_ports = 4; + } else if (OCTEON_IS_MODEL(OCTEON_CN31XX) + || OCTEON_IS_MODEL(OCTEON_CN30XX) + || OCTEON_IS_MODEL(OCTEON_CN50XX)) { + num_ports = 3; + } else { + cvmx_dprintf("ERROR: Unsupported Octeon model in %s\n", + __func__); + } + } + return num_ports; +} + +/** + * Put an RGMII interface in loopback mode. Internal packets sent + * out will be received back again on the same port. Externally + * received packets will echo back out. + * + * @port: IPD port number to loop. + */ +void cvmx_helper_rgmii_internal_loopback(int port) +{ + int interface = (port >> 4) & 1; + int index = port & 0xf; + uint64_t tmp; + + union cvmx_gmxx_prtx_cfg gmx_cfg; + gmx_cfg.u64 = 0; + gmx_cfg.s.duplex = 1; + gmx_cfg.s.slottime = 1; + gmx_cfg.s.speed = 1; + cvmx_write_csr(CVMX_GMXX_TXX_CLK(index, interface), 1); + cvmx_write_csr(CVMX_GMXX_TXX_SLOT(index, interface), 0x200); + cvmx_write_csr(CVMX_GMXX_TXX_BURST(index, interface), 0x2000); + cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmx_cfg.u64); + tmp = cvmx_read_csr(CVMX_ASXX_PRT_LOOP(interface)); + cvmx_write_csr(CVMX_ASXX_PRT_LOOP(interface), (1 << index) | tmp); + tmp = cvmx_read_csr(CVMX_ASXX_TX_PRT_EN(interface)); + cvmx_write_csr(CVMX_ASXX_TX_PRT_EN(interface), (1 << index) | tmp); + tmp = cvmx_read_csr(CVMX_ASXX_RX_PRT_EN(interface)); + cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(interface), (1 << index) | tmp); + gmx_cfg.s.en = 1; + cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmx_cfg.u64); +} + +/** + * Workaround ASX setup errata with CN38XX pass1 + * + * @interface: Interface to setup + * @port: Port to setup (0..3) + * @cpu_clock_hz: + * Chip frequency in Hertz + * + * Returns Zero on success, negative on failure + */ +static int __cvmx_helper_errata_asx_pass1(int interface, int port, + int cpu_clock_hz) +{ + /* Set hi water mark as per errata GMX-4 */ + if (cpu_clock_hz >= 325000000 && cpu_clock_hz < 375000000) + cvmx_write_csr(CVMX_ASXX_TX_HI_WATERX(port, interface), 12); + else if (cpu_clock_hz >= 375000000 && cpu_clock_hz < 437000000) + cvmx_write_csr(CVMX_ASXX_TX_HI_WATERX(port, interface), 11); + else if (cpu_clock_hz >= 437000000 && cpu_clock_hz < 550000000) + cvmx_write_csr(CVMX_ASXX_TX_HI_WATERX(port, interface), 10); + else if (cpu_clock_hz >= 550000000 && cpu_clock_hz < 687000000) + cvmx_write_csr(CVMX_ASXX_TX_HI_WATERX(port, interface), 9); + else + cvmx_dprintf("Illegal clock frequency (%d). " + "CVMX_ASXX_TX_HI_WATERX not set\n", cpu_clock_hz); + return 0; +} + +/** + * Configure all of the ASX, GMX, and PKO regsiters required + * to get RGMII to function on the supplied interface. + * + * @interface: PKO Interface to configure (0 or 1) + * + * Returns Zero on success + */ +int __cvmx_helper_rgmii_enable(int interface) +{ + int num_ports = cvmx_helper_ports_on_interface(interface); + int port; + struct cvmx_sysinfo *sys_info_ptr = cvmx_sysinfo_get(); + union cvmx_gmxx_inf_mode mode; + union cvmx_asxx_tx_prt_en asx_tx; + union cvmx_asxx_rx_prt_en asx_rx; + + mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface)); + + if (mode.s.en == 0) + return -1; + if ((OCTEON_IS_MODEL(OCTEON_CN38XX) || + OCTEON_IS_MODEL(OCTEON_CN58XX)) && mode.s.type == 1) + /* Ignore SPI interfaces */ + return -1; + + /* Configure the ASX registers needed to use the RGMII ports */ + asx_tx.u64 = 0; + asx_tx.s.prt_en = cvmx_build_mask(num_ports); + cvmx_write_csr(CVMX_ASXX_TX_PRT_EN(interface), asx_tx.u64); + + asx_rx.u64 = 0; + asx_rx.s.prt_en = cvmx_build_mask(num_ports); + cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(interface), asx_rx.u64); + + /* Configure the GMX registers needed to use the RGMII ports */ + for (port = 0; port < num_ports; port++) { + /* Setting of CVMX_GMXX_TXX_THRESH has been moved to + __cvmx_helper_setup_gmx() */ + + if (cvmx_octeon_is_pass1()) + __cvmx_helper_errata_asx_pass1(interface, port, + sys_info_ptr-> + cpu_clock_hz); + else { + /* + * Configure more flexible RGMII preamble + * checking. Pass 1 doesn't support this + * feature. + */ + union cvmx_gmxx_rxx_frm_ctl frm_ctl; + frm_ctl.u64 = + cvmx_read_csr(CVMX_GMXX_RXX_FRM_CTL + (port, interface)); + /* New field, so must be compile time */ + frm_ctl.s.pre_free = 1; + cvmx_write_csr(CVMX_GMXX_RXX_FRM_CTL(port, interface), + frm_ctl.u64); + } + + /* + * Each pause frame transmitted will ask for about 10M + * bit times before resume. If buffer space comes + * available before that time has expired, an XON + * pause frame (0 time) will be transmitted to restart + * the flow. + */ + cvmx_write_csr(CVMX_GMXX_TXX_PAUSE_PKT_TIME(port, interface), + 20000); + cvmx_write_csr(CVMX_GMXX_TXX_PAUSE_PKT_INTERVAL + (port, interface), 19000); + + if (OCTEON_IS_MODEL(OCTEON_CN50XX)) { + cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX(port, interface), + 16); + cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX(port, interface), + 16); + } else { + cvmx_write_csr(CVMX_ASXX_TX_CLK_SETX(port, interface), + 24); + cvmx_write_csr(CVMX_ASXX_RX_CLK_SETX(port, interface), + 24); + } + } + + __cvmx_helper_setup_gmx(interface, num_ports); + + /* enable the ports now */ + for (port = 0; port < num_ports; port++) { + union cvmx_gmxx_prtx_cfg gmx_cfg; + cvmx_helper_link_autoconf(cvmx_helper_get_ipd_port + (interface, port)); + gmx_cfg.u64 = + cvmx_read_csr(CVMX_GMXX_PRTX_CFG(port, interface)); + gmx_cfg.s.en = 1; + cvmx_write_csr(CVMX_GMXX_PRTX_CFG(port, interface), + gmx_cfg.u64); + } + __cvmx_interrupt_asxx_enable(interface); + __cvmx_interrupt_gmxx_enable(interface); + + return 0; +} + +/** + * Return the link state of an IPD/PKO port as returned by + * auto negotiation. The result of this function may not match + * Octeon's link config if auto negotiation has changed since + * the last call to cvmx_helper_link_set(). + * + * @ipd_port: IPD/PKO port to query + * + * Returns Link state + */ +cvmx_helper_link_info_t __cvmx_helper_rgmii_link_get(int ipd_port) +{ + int interface = cvmx_helper_get_interface_num(ipd_port); + int index = cvmx_helper_get_interface_index_num(ipd_port); + union cvmx_asxx_prt_loop asxx_prt_loop; + + asxx_prt_loop.u64 = cvmx_read_csr(CVMX_ASXX_PRT_LOOP(interface)); + if (asxx_prt_loop.s.int_loop & (1 << index)) { + /* Force 1Gbps full duplex on internal loopback */ + cvmx_helper_link_info_t result; + result.u64 = 0; + result.s.full_duplex = 1; + result.s.link_up = 1; + result.s.speed = 1000; + return result; + } else + return __cvmx_helper_board_link_get(ipd_port); +} + +/** + * Configure an IPD/PKO port for the specified link state. This + * function does not influence auto negotiation at the PHY level. + * The passed link state must always match the link state returned + * by cvmx_helper_link_get(). It is normally best to use + * cvmx_helper_link_autoconf() instead. + * + * @ipd_port: IPD/PKO port to configure + * @link_info: The new link state + * + * Returns Zero on success, negative on failure + */ +int __cvmx_helper_rgmii_link_set(int ipd_port, + cvmx_helper_link_info_t link_info) +{ + int result = 0; + int interface = cvmx_helper_get_interface_num(ipd_port); + int index = cvmx_helper_get_interface_index_num(ipd_port); + union cvmx_gmxx_prtx_cfg original_gmx_cfg; + union cvmx_gmxx_prtx_cfg new_gmx_cfg; + union cvmx_pko_mem_queue_qos pko_mem_queue_qos; + union cvmx_pko_mem_queue_qos pko_mem_queue_qos_save[16]; + union cvmx_gmxx_tx_ovr_bp gmx_tx_ovr_bp; + union cvmx_gmxx_tx_ovr_bp gmx_tx_ovr_bp_save; + int i; + + /* Ignore speed sets in the simulator */ + if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_SIM) + return 0; + + /* Read the current settings so we know the current enable state */ + original_gmx_cfg.u64 = + cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface)); + new_gmx_cfg = original_gmx_cfg; + + /* Disable the lowest level RX */ + cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(interface), + cvmx_read_csr(CVMX_ASXX_RX_PRT_EN(interface)) & + ~(1 << index)); + + /* Disable all queues so that TX should become idle */ + for (i = 0; i < cvmx_pko_get_num_queues(ipd_port); i++) { + int queue = cvmx_pko_get_base_queue(ipd_port) + i; + cvmx_write_csr(CVMX_PKO_REG_READ_IDX, queue); + pko_mem_queue_qos.u64 = cvmx_read_csr(CVMX_PKO_MEM_QUEUE_QOS); + pko_mem_queue_qos.s.pid = ipd_port; + pko_mem_queue_qos.s.qid = queue; + pko_mem_queue_qos_save[i] = pko_mem_queue_qos; + pko_mem_queue_qos.s.qos_mask = 0; + cvmx_write_csr(CVMX_PKO_MEM_QUEUE_QOS, pko_mem_queue_qos.u64); + } + + /* Disable backpressure */ + gmx_tx_ovr_bp.u64 = cvmx_read_csr(CVMX_GMXX_TX_OVR_BP(interface)); + gmx_tx_ovr_bp_save = gmx_tx_ovr_bp; + gmx_tx_ovr_bp.s.bp &= ~(1 << index); + gmx_tx_ovr_bp.s.en |= 1 << index; + cvmx_write_csr(CVMX_GMXX_TX_OVR_BP(interface), gmx_tx_ovr_bp.u64); + cvmx_read_csr(CVMX_GMXX_TX_OVR_BP(interface)); + + /* + * Poll the GMX state machine waiting for it to become + * idle. Preferably we should only change speed when it is + * idle. If it doesn't become idle we will still do the speed + * change, but there is a slight chance that GMX will + * lockup. + */ + cvmx_write_csr(CVMX_NPI_DBG_SELECT, + interface * 0x800 + index * 0x100 + 0x880); + CVMX_WAIT_FOR_FIELD64(CVMX_DBG_DATA, union cvmx_dbg_data, data & 7, + ==, 0, 10000); + CVMX_WAIT_FOR_FIELD64(CVMX_DBG_DATA, union cvmx_dbg_data, data & 0xf, + ==, 0, 10000); + + /* Disable the port before we make any changes */ + new_gmx_cfg.s.en = 0; + cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), new_gmx_cfg.u64); + cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface)); + + /* Set full/half duplex */ + if (cvmx_octeon_is_pass1()) + /* Half duplex is broken for 38XX Pass 1 */ + new_gmx_cfg.s.duplex = 1; + else if (!link_info.s.link_up) + /* Force full duplex on down links */ + new_gmx_cfg.s.duplex = 1; + else + new_gmx_cfg.s.duplex = link_info.s.full_duplex; + + /* Set the link speed. Anything unknown is set to 1Gbps */ + if (link_info.s.speed == 10) { + new_gmx_cfg.s.slottime = 0; + new_gmx_cfg.s.speed = 0; + } else if (link_info.s.speed == 100) { + new_gmx_cfg.s.slottime = 0; + new_gmx_cfg.s.speed = 0; + } else { + new_gmx_cfg.s.slottime = 1; + new_gmx_cfg.s.speed = 1; + } + + /* Adjust the clocks */ + if (link_info.s.speed == 10) { + cvmx_write_csr(CVMX_GMXX_TXX_CLK(index, interface), 50); + cvmx_write_csr(CVMX_GMXX_TXX_SLOT(index, interface), 0x40); + cvmx_write_csr(CVMX_GMXX_TXX_BURST(index, interface), 0); + } else if (link_info.s.speed == 100) { + cvmx_write_csr(CVMX_GMXX_TXX_CLK(index, interface), 5); + cvmx_write_csr(CVMX_GMXX_TXX_SLOT(index, interface), 0x40); + cvmx_write_csr(CVMX_GMXX_TXX_BURST(index, interface), 0); + } else { + cvmx_write_csr(CVMX_GMXX_TXX_CLK(index, interface), 1); + cvmx_write_csr(CVMX_GMXX_TXX_SLOT(index, interface), 0x200); + cvmx_write_csr(CVMX_GMXX_TXX_BURST(index, interface), 0x2000); + } + + if (OCTEON_IS_MODEL(OCTEON_CN30XX) || OCTEON_IS_MODEL(OCTEON_CN50XX)) { + if ((link_info.s.speed == 10) || (link_info.s.speed == 100)) { + union cvmx_gmxx_inf_mode mode; + mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface)); + + /* + * Port .en .type .p0mii Configuration + * ---- --- ----- ------ ----------------------------------------- + * X 0 X X All links are disabled. + * 0 1 X 0 Port 0 is RGMII + * 0 1 X 1 Port 0 is MII + * 1 1 0 X Ports 1 and 2 are configured as RGMII ports. + * 1 1 1 X Port 1: GMII/MII; Port 2: disabled. GMII or + * MII port is selected by GMX_PRT1_CFG[SPEED]. + */ + + /* In MII mode, CLK_CNT = 1. */ + if (((index == 0) && (mode.s.p0mii == 1)) + || ((index != 0) && (mode.s.type == 1))) { + cvmx_write_csr(CVMX_GMXX_TXX_CLK + (index, interface), 1); + } + } + } + + /* Do a read to make sure all setup stuff is complete */ + cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface)); + + /* Save the new GMX setting without enabling the port */ + cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), new_gmx_cfg.u64); + + /* Enable the lowest level RX */ + cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(interface), + cvmx_read_csr(CVMX_ASXX_RX_PRT_EN(interface)) | (1 << + index)); + + /* Re-enable the TX path */ + for (i = 0; i < cvmx_pko_get_num_queues(ipd_port); i++) { + int queue = cvmx_pko_get_base_queue(ipd_port) + i; + cvmx_write_csr(CVMX_PKO_REG_READ_IDX, queue); + cvmx_write_csr(CVMX_PKO_MEM_QUEUE_QOS, + pko_mem_queue_qos_save[i].u64); + } + + /* Restore backpressure */ + cvmx_write_csr(CVMX_GMXX_TX_OVR_BP(interface), gmx_tx_ovr_bp_save.u64); + + /* Restore the GMX enable state. Port config is complete */ + new_gmx_cfg.s.en = original_gmx_cfg.s.en; + cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), new_gmx_cfg.u64); + + return result; +} + +/** + * Configure a port for internal and/or external loopback. Internal loopback + * causes packets sent by the port to be received by Octeon. External loopback + * causes packets received from the wire to sent out again. + * + * @ipd_port: IPD/PKO port to loopback. + * @enable_internal: + * Non zero if you want internal loopback + * @enable_external: + * Non zero if you want external loopback + * + * Returns Zero on success, negative on failure. + */ +int __cvmx_helper_rgmii_configure_loopback(int ipd_port, int enable_internal, + int enable_external) +{ + int interface = cvmx_helper_get_interface_num(ipd_port); + int index = cvmx_helper_get_interface_index_num(ipd_port); + int original_enable; + union cvmx_gmxx_prtx_cfg gmx_cfg; + union cvmx_asxx_prt_loop asxx_prt_loop; + + /* Read the current enable state and save it */ + gmx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface)); + original_enable = gmx_cfg.s.en; + /* Force port to be disabled */ + gmx_cfg.s.en = 0; + if (enable_internal) { + /* Force speed if we're doing internal loopback */ + gmx_cfg.s.duplex = 1; + gmx_cfg.s.slottime = 1; + gmx_cfg.s.speed = 1; + cvmx_write_csr(CVMX_GMXX_TXX_CLK(index, interface), 1); + cvmx_write_csr(CVMX_GMXX_TXX_SLOT(index, interface), 0x200); + cvmx_write_csr(CVMX_GMXX_TXX_BURST(index, interface), 0x2000); + } + cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmx_cfg.u64); + + /* Set the loopback bits */ + asxx_prt_loop.u64 = cvmx_read_csr(CVMX_ASXX_PRT_LOOP(interface)); + if (enable_internal) + asxx_prt_loop.s.int_loop |= 1 << index; + else + asxx_prt_loop.s.int_loop &= ~(1 << index); + if (enable_external) + asxx_prt_loop.s.ext_loop |= 1 << index; + else + asxx_prt_loop.s.ext_loop &= ~(1 << index); + cvmx_write_csr(CVMX_ASXX_PRT_LOOP(interface), asxx_prt_loop.u64); + + /* Force enables in internal loopback */ + if (enable_internal) { + uint64_t tmp; + tmp = cvmx_read_csr(CVMX_ASXX_TX_PRT_EN(interface)); + cvmx_write_csr(CVMX_ASXX_TX_PRT_EN(interface), + (1 << index) | tmp); + tmp = cvmx_read_csr(CVMX_ASXX_RX_PRT_EN(interface)); + cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(interface), + (1 << index) | tmp); + original_enable = 1; + } + + /* Restore the enable state */ + gmx_cfg.s.en = original_enable; + cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmx_cfg.u64); + return 0; +} diff --git a/drivers/staging/octeon/cvmx-helper-rgmii.h b/drivers/staging/octeon/cvmx-helper-rgmii.h new file mode 100644 index 0000000..ea26526 --- /dev/null +++ b/drivers/staging/octeon/cvmx-helper-rgmii.h @@ -0,0 +1,110 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * along with this file; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +/** + * @file + * + * Functions for RGMII/GMII/MII initialization, configuration, + * and monitoring. + * + */ +#ifndef __CVMX_HELPER_RGMII_H__ +#define __CVMX_HELPER_RGMII_H__ + +/** + * Probe RGMII ports and determine the number present + * + * @interface: Interface to probe + * + * Returns Number of RGMII/GMII/MII ports (0-4). + */ +extern int __cvmx_helper_rgmii_probe(int interface); + +/** + * Put an RGMII interface in loopback mode. Internal packets sent + * out will be received back again on the same port. Externally + * received packets will echo back out. + * + * @port: IPD port number to loop. + */ +extern void cvmx_helper_rgmii_internal_loopback(int port); + +/** + * Configure all of the ASX, GMX, and PKO regsiters required + * to get RGMII to function on the supplied interface. + * + * @interface: PKO Interface to configure (0 or 1) + * + * Returns Zero on success + */ +extern int __cvmx_helper_rgmii_enable(int interface); + +/** + * Return the link state of an IPD/PKO port as returned by + * auto negotiation. The result of this function may not match + * Octeon's link config if auto negotiation has changed since + * the last call to cvmx_helper_link_set(). + * + * @ipd_port: IPD/PKO port to query + * + * Returns Link state + */ +extern cvmx_helper_link_info_t __cvmx_helper_rgmii_link_get(int ipd_port); + +/** + * Configure an IPD/PKO port for the specified link state. This + * function does not influence auto negotiation at the PHY level. + * The passed link state must always match the link state returned + * by cvmx_helper_link_get(). It is normally best to use + * cvmx_helper_link_autoconf() instead. + * + * @ipd_port: IPD/PKO port to configure + * @link_info: The new link state + * + * Returns Zero on success, negative on failure + */ +extern int __cvmx_helper_rgmii_link_set(int ipd_port, + cvmx_helper_link_info_t link_info); + +/** + * Configure a port for internal and/or external loopback. Internal loopback + * causes packets sent by the port to be received by Octeon. External loopback + * causes packets received from the wire to sent out again. + * + * @ipd_port: IPD/PKO port to loopback. + * @enable_internal: + * Non zero if you want internal loopback + * @enable_external: + * Non zero if you want external loopback + * + * Returns Zero on success, negative on failure. + */ +extern int __cvmx_helper_rgmii_configure_loopback(int ipd_port, + int enable_internal, + int enable_external); + +#endif diff --git a/drivers/staging/octeon/cvmx-helper-sgmii.c b/drivers/staging/octeon/cvmx-helper-sgmii.c new file mode 100644 index 0000000..6214e3b --- /dev/null +++ b/drivers/staging/octeon/cvmx-helper-sgmii.c @@ -0,0 +1,550 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * along with this file; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +/* + * Functions for SGMII initialization, configuration, + * and monitoring. + */ + +#include + +#include "cvmx-config.h" + +#include "cvmx-mdio.h" +#include "cvmx-helper.h" +#include "cvmx-helper-board.h" + +#include "cvmx-gmxx-defs.h" +#include "cvmx-pcsx-defs.h" + +void __cvmx_interrupt_gmxx_enable(int interface); +void __cvmx_interrupt_pcsx_intx_en_reg_enable(int index, int block); +void __cvmx_interrupt_pcsxx_int_en_reg_enable(int index); + +/** + * Perform initialization required only once for an SGMII port. + * + * @interface: Interface to init + * @index: Index of prot on the interface + * + * Returns Zero on success, negative on failure + */ +static int __cvmx_helper_sgmii_hardware_init_one_time(int interface, int index) +{ + const uint64_t clock_mhz = cvmx_sysinfo_get()->cpu_clock_hz / 1000000; + union cvmx_pcsx_miscx_ctl_reg pcs_misc_ctl_reg; + union cvmx_pcsx_linkx_timer_count_reg pcsx_linkx_timer_count_reg; + union cvmx_gmxx_prtx_cfg gmxx_prtx_cfg; + + /* Disable GMX */ + gmxx_prtx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface)); + gmxx_prtx_cfg.s.en = 0; + cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmxx_prtx_cfg.u64); + + /* + * Write PCS*_LINK*_TIMER_COUNT_REG[COUNT] with the + * appropriate value. 1000BASE-X specifies a 10ms + * interval. SGMII specifies a 1.6ms interval. + */ + pcs_misc_ctl_reg.u64 = + cvmx_read_csr(CVMX_PCSX_MISCX_CTL_REG(index, interface)); + pcsx_linkx_timer_count_reg.u64 = + cvmx_read_csr(CVMX_PCSX_LINKX_TIMER_COUNT_REG(index, interface)); + if (pcs_misc_ctl_reg.s.mode) { + /* 1000BASE-X */ + pcsx_linkx_timer_count_reg.s.count = + (10000ull * clock_mhz) >> 10; + } else { + /* SGMII */ + pcsx_linkx_timer_count_reg.s.count = + (1600ull * clock_mhz) >> 10; + } + cvmx_write_csr(CVMX_PCSX_LINKX_TIMER_COUNT_REG(index, interface), + pcsx_linkx_timer_count_reg.u64); + + /* + * Write the advertisement register to be used as the + * tx_Config_Reg of the autonegotiation. In + * 1000BASE-X mode, tx_Config_Reg is PCS*_AN*_ADV_REG. + * In SGMII PHY mode, tx_Config_Reg is + * PCS*_SGM*_AN_ADV_REG. In SGMII MAC mode, + * tx_Config_Reg is the fixed value 0x4001, so this + * step can be skipped. + */ + if (pcs_misc_ctl_reg.s.mode) { + /* 1000BASE-X */ + union cvmx_pcsx_anx_adv_reg pcsx_anx_adv_reg; + pcsx_anx_adv_reg.u64 = + cvmx_read_csr(CVMX_PCSX_ANX_ADV_REG(index, interface)); + pcsx_anx_adv_reg.s.rem_flt = 0; + pcsx_anx_adv_reg.s.pause = 3; + pcsx_anx_adv_reg.s.hfd = 1; + pcsx_anx_adv_reg.s.fd = 1; + cvmx_write_csr(CVMX_PCSX_ANX_ADV_REG(index, interface), + pcsx_anx_adv_reg.u64); + } else { + union cvmx_pcsx_miscx_ctl_reg pcsx_miscx_ctl_reg; + pcsx_miscx_ctl_reg.u64 = + cvmx_read_csr(CVMX_PCSX_MISCX_CTL_REG(index, interface)); + if (pcsx_miscx_ctl_reg.s.mac_phy) { + /* PHY Mode */ + union cvmx_pcsx_sgmx_an_adv_reg pcsx_sgmx_an_adv_reg; + pcsx_sgmx_an_adv_reg.u64 = + cvmx_read_csr(CVMX_PCSX_SGMX_AN_ADV_REG + (index, interface)); + pcsx_sgmx_an_adv_reg.s.link = 1; + pcsx_sgmx_an_adv_reg.s.dup = 1; + pcsx_sgmx_an_adv_reg.s.speed = 2; + cvmx_write_csr(CVMX_PCSX_SGMX_AN_ADV_REG + (index, interface), + pcsx_sgmx_an_adv_reg.u64); + } else { + /* MAC Mode - Nothing to do */ + } + } + return 0; +} + +/** + * Initialize the SERTES link for the first time or after a loss + * of link. + * + * @interface: Interface to init + * @index: Index of prot on the interface + * + * Returns Zero on success, negative on failure + */ +static int __cvmx_helper_sgmii_hardware_init_link(int interface, int index) +{ + union cvmx_pcsx_mrx_control_reg control_reg; + + /* + * Take PCS through a reset sequence. + * PCS*_MR*_CONTROL_REG[PWR_DN] should be cleared to zero. + * Write PCS*_MR*_CONTROL_REG[RESET]=1 (while not changing the + * value of the other PCS*_MR*_CONTROL_REG bits). Read + * PCS*_MR*_CONTROL_REG[RESET] until it changes value to + * zero. + */ + control_reg.u64 = + cvmx_read_csr(CVMX_PCSX_MRX_CONTROL_REG(index, interface)); + if (cvmx_sysinfo_get()->board_type != CVMX_BOARD_TYPE_SIM) { + control_reg.s.reset = 1; + cvmx_write_csr(CVMX_PCSX_MRX_CONTROL_REG(index, interface), + control_reg.u64); + if (CVMX_WAIT_FOR_FIELD64 + (CVMX_PCSX_MRX_CONTROL_REG(index, interface), + union cvmx_pcsx_mrx_control_reg, reset, ==, 0, 10000)) { + cvmx_dprintf("SGMII%d: Timeout waiting for port %d " + "to finish reset\n", + interface, index); + return -1; + } + } + + /* + * Write PCS*_MR*_CONTROL_REG[RST_AN]=1 to ensure a fresh + * sgmii negotiation starts. + */ + control_reg.s.rst_an = 1; + control_reg.s.an_en = 1; + control_reg.s.pwr_dn = 0; + cvmx_write_csr(CVMX_PCSX_MRX_CONTROL_REG(index, interface), + control_reg.u64); + + /* + * Wait for PCS*_MR*_STATUS_REG[AN_CPT] to be set, indicating + * that sgmii autonegotiation is complete. In MAC mode this + * isn't an ethernet link, but a link between Octeon and the + * PHY. + */ + if ((cvmx_sysinfo_get()->board_type != CVMX_BOARD_TYPE_SIM) && + CVMX_WAIT_FOR_FIELD64(CVMX_PCSX_MRX_STATUS_REG(index, interface), + union cvmx_pcsx_mrx_status_reg, an_cpt, ==, 1, + 10000)) { + /* cvmx_dprintf("SGMII%d: Port %d link timeout\n", interface, index); */ + return -1; + } + return 0; +} + +/** + * Configure an SGMII link to the specified speed after the SERTES + * link is up. + * + * @interface: Interface to init + * @index: Index of prot on the interface + * @link_info: Link state to configure + * + * Returns Zero on success, negative on failure + */ +static int __cvmx_helper_sgmii_hardware_init_link_speed(int interface, + int index, + cvmx_helper_link_info_t + link_info) +{ + int is_enabled; + union cvmx_gmxx_prtx_cfg gmxx_prtx_cfg; + union cvmx_pcsx_miscx_ctl_reg pcsx_miscx_ctl_reg; + + /* Disable GMX before we make any changes. Remember the enable state */ + gmxx_prtx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface)); + is_enabled = gmxx_prtx_cfg.s.en; + gmxx_prtx_cfg.s.en = 0; + cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmxx_prtx_cfg.u64); + + /* Wait for GMX to be idle */ + if (CVMX_WAIT_FOR_FIELD64 + (CVMX_GMXX_PRTX_CFG(index, interface), union cvmx_gmxx_prtx_cfg, + rx_idle, ==, 1, 10000) + || CVMX_WAIT_FOR_FIELD64(CVMX_GMXX_PRTX_CFG(index, interface), + union cvmx_gmxx_prtx_cfg, tx_idle, ==, 1, + 10000)) { + cvmx_dprintf + ("SGMII%d: Timeout waiting for port %d to be idle\n", + interface, index); + return -1; + } + + /* Read GMX CFG again to make sure the disable completed */ + gmxx_prtx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface)); + + /* + * Get the misc control for PCS. We will need to set the + * duplication amount. + */ + pcsx_miscx_ctl_reg.u64 = + cvmx_read_csr(CVMX_PCSX_MISCX_CTL_REG(index, interface)); + + /* + * Use GMXENO to force the link down if the status we get says + * it should be down. + */ + pcsx_miscx_ctl_reg.s.gmxeno = !link_info.s.link_up; + + /* Only change the duplex setting if the link is up */ + if (link_info.s.link_up) + gmxx_prtx_cfg.s.duplex = link_info.s.full_duplex; + + /* Do speed based setting for GMX */ + switch (link_info.s.speed) { + case 10: + gmxx_prtx_cfg.s.speed = 0; + gmxx_prtx_cfg.s.speed_msb = 1; + gmxx_prtx_cfg.s.slottime = 0; + /* Setting from GMX-603 */ + pcsx_miscx_ctl_reg.s.samp_pt = 25; + cvmx_write_csr(CVMX_GMXX_TXX_SLOT(index, interface), 64); + cvmx_write_csr(CVMX_GMXX_TXX_BURST(index, interface), 0); + break; + case 100: + gmxx_prtx_cfg.s.speed = 0; + gmxx_prtx_cfg.s.speed_msb = 0; + gmxx_prtx_cfg.s.slottime = 0; + pcsx_miscx_ctl_reg.s.samp_pt = 0x5; + cvmx_write_csr(CVMX_GMXX_TXX_SLOT(index, interface), 64); + cvmx_write_csr(CVMX_GMXX_TXX_BURST(index, interface), 0); + break; + case 1000: + gmxx_prtx_cfg.s.speed = 1; + gmxx_prtx_cfg.s.speed_msb = 0; + gmxx_prtx_cfg.s.slottime = 1; + pcsx_miscx_ctl_reg.s.samp_pt = 1; + cvmx_write_csr(CVMX_GMXX_TXX_SLOT(index, interface), 512); + cvmx_write_csr(CVMX_GMXX_TXX_BURST(index, interface), 8192); + break; + default: + break; + } + + /* Write the new misc control for PCS */ + cvmx_write_csr(CVMX_PCSX_MISCX_CTL_REG(index, interface), + pcsx_miscx_ctl_reg.u64); + + /* Write the new GMX settings with the port still disabled */ + cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmxx_prtx_cfg.u64); + + /* Read GMX CFG again to make sure the config completed */ + gmxx_prtx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface)); + + /* Restore the enabled / disabled state */ + gmxx_prtx_cfg.s.en = is_enabled; + cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), gmxx_prtx_cfg.u64); + + return 0; +} + +/** + * Bring up the SGMII interface to be ready for packet I/O but + * leave I/O disabled using the GMX override. This function + * follows the bringup documented in 10.6.3 of the manual. + * + * @interface: Interface to bringup + * @num_ports: Number of ports on the interface + * + * Returns Zero on success, negative on failure + */ +static int __cvmx_helper_sgmii_hardware_init(int interface, int num_ports) +{ + int index; + + __cvmx_helper_setup_gmx(interface, num_ports); + + for (index = 0; index < num_ports; index++) { + int ipd_port = cvmx_helper_get_ipd_port(interface, index); + __cvmx_helper_sgmii_hardware_init_one_time(interface, index); + __cvmx_helper_sgmii_link_set(ipd_port, + __cvmx_helper_sgmii_link_get + (ipd_port)); + + } + + return 0; +} + +/** + * Probe a SGMII interface and determine the number of ports + * connected to it. The SGMII interface should still be down after + * this call. + * + * @interface: Interface to probe + * + * Returns Number of ports on the interface. Zero to disable. + */ +int __cvmx_helper_sgmii_probe(int interface) +{ + union cvmx_gmxx_inf_mode mode; + + /* + * Due to errata GMX-700 on CN56XXp1.x and CN52XXp1.x, the + * interface needs to be enabled before IPD otherwise per port + * backpressure may not work properly + */ + mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface)); + mode.s.en = 1; + cvmx_write_csr(CVMX_GMXX_INF_MODE(interface), mode.u64); + return 4; +} + +/** + * Bringup and enable a SGMII interface. After this call packet + * I/O should be fully functional. This is called with IPD + * enabled but PKO disabled. + * + * @interface: Interface to bring up + * + * Returns Zero on success, negative on failure + */ +int __cvmx_helper_sgmii_enable(int interface) +{ + int num_ports = cvmx_helper_ports_on_interface(interface); + int index; + + __cvmx_helper_sgmii_hardware_init(interface, num_ports); + + for (index = 0; index < num_ports; index++) { + union cvmx_gmxx_prtx_cfg gmxx_prtx_cfg; + gmxx_prtx_cfg.u64 = + cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface)); + gmxx_prtx_cfg.s.en = 1; + cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), + gmxx_prtx_cfg.u64); + __cvmx_interrupt_pcsx_intx_en_reg_enable(index, interface); + } + __cvmx_interrupt_pcsxx_int_en_reg_enable(interface); + __cvmx_interrupt_gmxx_enable(interface); + return 0; +} + +/** + * Return the link state of an IPD/PKO port as returned by + * auto negotiation. The result of this function may not match + * Octeon's link config if auto negotiation has changed since + * the last call to cvmx_helper_link_set(). + * + * @ipd_port: IPD/PKO port to query + * + * Returns Link state + */ +cvmx_helper_link_info_t __cvmx_helper_sgmii_link_get(int ipd_port) +{ + cvmx_helper_link_info_t result; + union cvmx_pcsx_miscx_ctl_reg pcs_misc_ctl_reg; + int interface = cvmx_helper_get_interface_num(ipd_port); + int index = cvmx_helper_get_interface_index_num(ipd_port); + union cvmx_pcsx_mrx_control_reg pcsx_mrx_control_reg; + + result.u64 = 0; + + if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_SIM) { + /* The simulator gives you a simulated 1Gbps full duplex link */ + result.s.link_up = 1; + result.s.full_duplex = 1; + result.s.speed = 1000; + return result; + } + + pcsx_mrx_control_reg.u64 = + cvmx_read_csr(CVMX_PCSX_MRX_CONTROL_REG(index, interface)); + if (pcsx_mrx_control_reg.s.loopbck1) { + /* Force 1Gbps full duplex link for internal loopback */ + result.s.link_up = 1; + result.s.full_duplex = 1; + result.s.speed = 1000; + return result; + } + + pcs_misc_ctl_reg.u64 = + cvmx_read_csr(CVMX_PCSX_MISCX_CTL_REG(index, interface)); + if (pcs_misc_ctl_reg.s.mode) { + /* 1000BASE-X */ + /* FIXME */ + } else { + union cvmx_pcsx_miscx_ctl_reg pcsx_miscx_ctl_reg; + pcsx_miscx_ctl_reg.u64 = + cvmx_read_csr(CVMX_PCSX_MISCX_CTL_REG(index, interface)); + if (pcsx_miscx_ctl_reg.s.mac_phy) { + /* PHY Mode */ + union cvmx_pcsx_mrx_status_reg pcsx_mrx_status_reg; + union cvmx_pcsx_anx_results_reg pcsx_anx_results_reg; + + /* + * Don't bother continuing if the SERTES low + * level link is down + */ + pcsx_mrx_status_reg.u64 = + cvmx_read_csr(CVMX_PCSX_MRX_STATUS_REG + (index, interface)); + if (pcsx_mrx_status_reg.s.lnk_st == 0) { + if (__cvmx_helper_sgmii_hardware_init_link + (interface, index) != 0) + return result; + } + + /* Read the autoneg results */ + pcsx_anx_results_reg.u64 = + cvmx_read_csr(CVMX_PCSX_ANX_RESULTS_REG + (index, interface)); + if (pcsx_anx_results_reg.s.an_cpt) { + /* + * Auto negotiation is complete. Set + * status accordingly. + */ + result.s.full_duplex = + pcsx_anx_results_reg.s.dup; + result.s.link_up = + pcsx_anx_results_reg.s.link_ok; + switch (pcsx_anx_results_reg.s.spd) { + case 0: + result.s.speed = 10; + break; + case 1: + result.s.speed = 100; + break; + case 2: + result.s.speed = 1000; + break; + default: + result.s.speed = 0; + result.s.link_up = 0; + break; + } + } else { + /* + * Auto negotiation isn't + * complete. Return link down. + */ + result.s.speed = 0; + result.s.link_up = 0; + } + } else { /* MAC Mode */ + + result = __cvmx_helper_board_link_get(ipd_port); + } + } + return result; +} + +/** + * Configure an IPD/PKO port for the specified link state. This + * function does not influence auto negotiation at the PHY level. + * The passed link state must always match the link state returned + * by cvmx_helper_link_get(). It is normally best to use + * cvmx_helper_link_autoconf() instead. + * + * @ipd_port: IPD/PKO port to configure + * @link_info: The new link state + * + * Returns Zero on success, negative on failure + */ +int __cvmx_helper_sgmii_link_set(int ipd_port, + cvmx_helper_link_info_t link_info) +{ + int interface = cvmx_helper_get_interface_num(ipd_port); + int index = cvmx_helper_get_interface_index_num(ipd_port); + __cvmx_helper_sgmii_hardware_init_link(interface, index); + return __cvmx_helper_sgmii_hardware_init_link_speed(interface, index, + link_info); +} + +/** + * Configure a port for internal and/or external loopback. Internal + * loopback causes packets sent by the port to be received by + * Octeon. External loopback causes packets received from the wire to + * sent out again. + * + * @ipd_port: IPD/PKO port to loopback. + * @enable_internal: + * Non zero if you want internal loopback + * @enable_external: + * Non zero if you want external loopback + * + * Returns Zero on success, negative on failure. + */ +int __cvmx_helper_sgmii_configure_loopback(int ipd_port, int enable_internal, + int enable_external) +{ + int interface = cvmx_helper_get_interface_num(ipd_port); + int index = cvmx_helper_get_interface_index_num(ipd_port); + union cvmx_pcsx_mrx_control_reg pcsx_mrx_control_reg; + union cvmx_pcsx_miscx_ctl_reg pcsx_miscx_ctl_reg; + + pcsx_mrx_control_reg.u64 = + cvmx_read_csr(CVMX_PCSX_MRX_CONTROL_REG(index, interface)); + pcsx_mrx_control_reg.s.loopbck1 = enable_internal; + cvmx_write_csr(CVMX_PCSX_MRX_CONTROL_REG(index, interface), + pcsx_mrx_control_reg.u64); + + pcsx_miscx_ctl_reg.u64 = + cvmx_read_csr(CVMX_PCSX_MISCX_CTL_REG(index, interface)); + pcsx_miscx_ctl_reg.s.loopbck2 = enable_external; + cvmx_write_csr(CVMX_PCSX_MISCX_CTL_REG(index, interface), + pcsx_miscx_ctl_reg.u64); + + __cvmx_helper_sgmii_hardware_init_link(interface, index); + return 0; +} diff --git a/drivers/staging/octeon/cvmx-helper-sgmii.h b/drivers/staging/octeon/cvmx-helper-sgmii.h new file mode 100644 index 0000000..19b48d6 --- /dev/null +++ b/drivers/staging/octeon/cvmx-helper-sgmii.h @@ -0,0 +1,104 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * along with this file; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +/** + * @file + * + * Functions for SGMII initialization, configuration, + * and monitoring. + * + */ +#ifndef __CVMX_HELPER_SGMII_H__ +#define __CVMX_HELPER_SGMII_H__ + +/** + * Probe a SGMII interface and determine the number of ports + * connected to it. The SGMII interface should still be down after + * this call. + * + * @interface: Interface to probe + * + * Returns Number of ports on the interface. Zero to disable. + */ +extern int __cvmx_helper_sgmii_probe(int interface); + +/** + * Bringup and enable a SGMII interface. After this call packet + * I/O should be fully functional. This is called with IPD + * enabled but PKO disabled. + * + * @interface: Interface to bring up + * + * Returns Zero on success, negative on failure + */ +extern int __cvmx_helper_sgmii_enable(int interface); + +/** + * Return the link state of an IPD/PKO port as returned by + * auto negotiation. The result of this function may not match + * Octeon's link config if auto negotiation has changed since + * the last call to cvmx_helper_link_set(). + * + * @ipd_port: IPD/PKO port to query + * + * Returns Link state + */ +extern cvmx_helper_link_info_t __cvmx_helper_sgmii_link_get(int ipd_port); + +/** + * Configure an IPD/PKO port for the specified link state. This + * function does not influence auto negotiation at the PHY level. + * The passed link state must always match the link state returned + * by cvmx_helper_link_get(). It is normally best to use + * cvmx_helper_link_autoconf() instead. + * + * @ipd_port: IPD/PKO port to configure + * @link_info: The new link state + * + * Returns Zero on success, negative on failure + */ +extern int __cvmx_helper_sgmii_link_set(int ipd_port, + cvmx_helper_link_info_t link_info); + +/** + * Configure a port for internal and/or external loopback. Internal loopback + * causes packets sent by the port to be received by Octeon. External loopback + * causes packets received from the wire to sent out again. + * + * @ipd_port: IPD/PKO port to loopback. + * @enable_internal: + * Non zero if you want internal loopback + * @enable_external: + * Non zero if you want external loopback + * + * Returns Zero on success, negative on failure. + */ +extern int __cvmx_helper_sgmii_configure_loopback(int ipd_port, + int enable_internal, + int enable_external); + +#endif diff --git a/drivers/staging/octeon/cvmx-helper-spi.c b/drivers/staging/octeon/cvmx-helper-spi.c new file mode 100644 index 0000000..8ba6c83 --- /dev/null +++ b/drivers/staging/octeon/cvmx-helper-spi.c @@ -0,0 +1,195 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * along with this file; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +void __cvmx_interrupt_gmxx_enable(int interface); +void __cvmx_interrupt_spxx_int_msk_enable(int index); +void __cvmx_interrupt_stxx_int_msk_enable(int index); + +/* + * Functions for SPI initialization, configuration, + * and monitoring. + */ +#include + +#include "cvmx-config.h" +#include "cvmx-spi.h" +#include "cvmx-helper.h" + +#include "cvmx-pip-defs.h" +#include "cvmx-pko-defs.h" + +/* + * CVMX_HELPER_SPI_TIMEOUT is used to determine how long the SPI + * initialization routines wait for SPI training. You can override the + * value using executive-config.h if necessary. + */ +#ifndef CVMX_HELPER_SPI_TIMEOUT +#define CVMX_HELPER_SPI_TIMEOUT 10 +#endif + +/** + * Probe a SPI interface and determine the number of ports + * connected to it. The SPI interface should still be down after + * this call. + * + * @interface: Interface to probe + * + * Returns Number of ports on the interface. Zero to disable. + */ +int __cvmx_helper_spi_probe(int interface) +{ + int num_ports = 0; + + if ((cvmx_sysinfo_get()->board_type != CVMX_BOARD_TYPE_SIM) && + cvmx_spi4000_is_present(interface)) { + num_ports = 10; + } else { + union cvmx_pko_reg_crc_enable enable; + num_ports = 16; + /* + * Unlike the SPI4000, most SPI devices don't + * automatically put on the L2 CRC. For everything + * except for the SPI4000 have PKO append the L2 CRC + * to the packet. + */ + enable.u64 = cvmx_read_csr(CVMX_PKO_REG_CRC_ENABLE); + enable.s.enable |= 0xffff << (interface * 16); + cvmx_write_csr(CVMX_PKO_REG_CRC_ENABLE, enable.u64); + } + __cvmx_helper_setup_gmx(interface, num_ports); + return num_ports; +} + +/** + * Bringup and enable a SPI interface. After this call packet I/O + * should be fully functional. This is called with IPD enabled but + * PKO disabled. + * + * @interface: Interface to bring up + * + * Returns Zero on success, negative on failure + */ +int __cvmx_helper_spi_enable(int interface) +{ + /* + * Normally the ethernet L2 CRC is checked and stripped in the + * GMX block. When you are using SPI, this isn' the case and + * IPD needs to check the L2 CRC. + */ + int num_ports = cvmx_helper_ports_on_interface(interface); + int ipd_port; + for (ipd_port = interface * 16; ipd_port < interface * 16 + num_ports; + ipd_port++) { + union cvmx_pip_prt_cfgx port_config; + port_config.u64 = cvmx_read_csr(CVMX_PIP_PRT_CFGX(ipd_port)); + port_config.s.crc_en = 1; + cvmx_write_csr(CVMX_PIP_PRT_CFGX(ipd_port), port_config.u64); + } + + if (cvmx_sysinfo_get()->board_type != CVMX_BOARD_TYPE_SIM) { + cvmx_spi_start_interface(interface, CVMX_SPI_MODE_DUPLEX, + CVMX_HELPER_SPI_TIMEOUT, num_ports); + if (cvmx_spi4000_is_present(interface)) + cvmx_spi4000_initialize(interface); + } + __cvmx_interrupt_spxx_int_msk_enable(interface); + __cvmx_interrupt_stxx_int_msk_enable(interface); + __cvmx_interrupt_gmxx_enable(interface); + return 0; +} + +/** + * Return the link state of an IPD/PKO port as returned by + * auto negotiation. The result of this function may not match + * Octeon's link config if auto negotiation has changed since + * the last call to cvmx_helper_link_set(). + * + * @ipd_port: IPD/PKO port to query + * + * Returns Link state + */ +cvmx_helper_link_info_t __cvmx_helper_spi_link_get(int ipd_port) +{ + cvmx_helper_link_info_t result; + int interface = cvmx_helper_get_interface_num(ipd_port); + int index = cvmx_helper_get_interface_index_num(ipd_port); + result.u64 = 0; + + if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_SIM) { + /* The simulator gives you a simulated full duplex link */ + result.s.link_up = 1; + result.s.full_duplex = 1; + result.s.speed = 10000; + } else if (cvmx_spi4000_is_present(interface)) { + union cvmx_gmxx_rxx_rx_inbnd inband = + cvmx_spi4000_check_speed(interface, index); + result.s.link_up = inband.s.status; + result.s.full_duplex = inband.s.duplex; + switch (inband.s.speed) { + case 0: /* 10 Mbps */ + result.s.speed = 10; + break; + case 1: /* 100 Mbps */ + result.s.speed = 100; + break; + case 2: /* 1 Gbps */ + result.s.speed = 1000; + break; + case 3: /* Illegal */ + result.s.speed = 0; + result.s.link_up = 0; + break; + } + } else { + /* For generic SPI we can't determine the link, just return some + sane results */ + result.s.link_up = 1; + result.s.full_duplex = 1; + result.s.speed = 10000; + } + return result; +} + +/** + * Configure an IPD/PKO port for the specified link state. This + * function does not influence auto negotiation at the PHY level. + * The passed link state must always match the link state returned + * by cvmx_helper_link_get(). It is normally best to use + * cvmx_helper_link_autoconf() instead. + * + * @ipd_port: IPD/PKO port to configure + * @link_info: The new link state + * + * Returns Zero on success, negative on failure + */ +int __cvmx_helper_spi_link_set(int ipd_port, cvmx_helper_link_info_t link_info) +{ + /* Nothing to do. If we have a SPI4000 then the setup was already performed + by cvmx_spi4000_check_speed(). If not then there isn't any link + info */ + return 0; +} diff --git a/drivers/staging/octeon/cvmx-helper-spi.h b/drivers/staging/octeon/cvmx-helper-spi.h new file mode 100644 index 0000000..69bac03 --- /dev/null +++ b/drivers/staging/octeon/cvmx-helper-spi.h @@ -0,0 +1,84 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * along with this file; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +/* + * Functions for SPI initialization, configuration, + * and monitoring. + */ +#ifndef __CVMX_HELPER_SPI_H__ +#define __CVMX_HELPER_SPI_H__ + +/** + * Probe a SPI interface and determine the number of ports + * connected to it. The SPI interface should still be down after + * this call. + * + * @interface: Interface to probe + * + * Returns Number of ports on the interface. Zero to disable. + */ +extern int __cvmx_helper_spi_probe(int interface); + +/** + * Bringup and enable a SPI interface. After this call packet I/O + * should be fully functional. This is called with IPD enabled but + * PKO disabled. + * + * @interface: Interface to bring up + * + * Returns Zero on success, negative on failure + */ +extern int __cvmx_helper_spi_enable(int interface); + +/** + * Return the link state of an IPD/PKO port as returned by + * auto negotiation. The result of this function may not match + * Octeon's link config if auto negotiation has changed since + * the last call to cvmx_helper_link_set(). + * + * @ipd_port: IPD/PKO port to query + * + * Returns Link state + */ +extern cvmx_helper_link_info_t __cvmx_helper_spi_link_get(int ipd_port); + +/** + * Configure an IPD/PKO port for the specified link state. This + * function does not influence auto negotiation at the PHY level. + * The passed link state must always match the link state returned + * by cvmx_helper_link_get(). It is normally best to use + * cvmx_helper_link_autoconf() instead. + * + * @ipd_port: IPD/PKO port to configure + * @link_info: The new link state + * + * Returns Zero on success, negative on failure + */ +extern int __cvmx_helper_spi_link_set(int ipd_port, + cvmx_helper_link_info_t link_info); + +#endif diff --git a/drivers/staging/octeon/cvmx-helper-util.c b/drivers/staging/octeon/cvmx-helper-util.c new file mode 100644 index 0000000..41ef8a4 --- /dev/null +++ b/drivers/staging/octeon/cvmx-helper-util.c @@ -0,0 +1,433 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * along with this file; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +/* + * Small helper utilities. + */ +#include + +#include + +#include "cvmx-config.h" + +#include "cvmx-fpa.h" +#include "cvmx-pip.h" +#include "cvmx-pko.h" +#include "cvmx-ipd.h" +#include "cvmx-spi.h" + +#include "cvmx-helper.h" +#include "cvmx-helper-util.h" + +#include + +/** + * Convert a interface mode into a human readable string + * + * @mode: Mode to convert + * + * Returns String + */ +const char *cvmx_helper_interface_mode_to_string(cvmx_helper_interface_mode_t + mode) +{ + switch (mode) { + case CVMX_HELPER_INTERFACE_MODE_DISABLED: + return "DISABLED"; + case CVMX_HELPER_INTERFACE_MODE_RGMII: + return "RGMII"; + case CVMX_HELPER_INTERFACE_MODE_GMII: + return "GMII"; + case CVMX_HELPER_INTERFACE_MODE_SPI: + return "SPI"; + case CVMX_HELPER_INTERFACE_MODE_PCIE: + return "PCIE"; + case CVMX_HELPER_INTERFACE_MODE_XAUI: + return "XAUI"; + case CVMX_HELPER_INTERFACE_MODE_SGMII: + return "SGMII"; + case CVMX_HELPER_INTERFACE_MODE_PICMG: + return "PICMG"; + case CVMX_HELPER_INTERFACE_MODE_NPI: + return "NPI"; + case CVMX_HELPER_INTERFACE_MODE_LOOP: + return "LOOP"; + } + return "UNKNOWN"; +} + +/** + * Debug routine to dump the packet structure to the console + * + * @work: Work queue entry containing the packet to dump + * Returns + */ +int cvmx_helper_dump_packet(cvmx_wqe_t *work) +{ + uint64_t count; + uint64_t remaining_bytes; + union cvmx_buf_ptr buffer_ptr; + uint64_t start_of_buffer; + uint8_t *data_address; + uint8_t *end_of_data; + + cvmx_dprintf("Packet Length: %u\n", work->len); + cvmx_dprintf(" Input Port: %u\n", work->ipprt); + cvmx_dprintf(" QoS: %u\n", work->qos); + cvmx_dprintf(" Buffers: %u\n", work->word2.s.bufs); + + if (work->word2.s.bufs == 0) { + union cvmx_ipd_wqe_fpa_queue wqe_pool; + wqe_pool.u64 = cvmx_read_csr(CVMX_IPD_WQE_FPA_QUEUE); + buffer_ptr.u64 = 0; + buffer_ptr.s.pool = wqe_pool.s.wqe_pool; + buffer_ptr.s.size = 128; + buffer_ptr.s.addr = cvmx_ptr_to_phys(work->packet_data); + if (likely(!work->word2.s.not_IP)) { + union cvmx_pip_ip_offset pip_ip_offset; + pip_ip_offset.u64 = cvmx_read_csr(CVMX_PIP_IP_OFFSET); + buffer_ptr.s.addr += + (pip_ip_offset.s.offset << 3) - + work->word2.s.ip_offset; + buffer_ptr.s.addr += (work->word2.s.is_v6 ^ 1) << 2; + } else { + /* + * WARNING: This code assumes that the packet + * is not RAW. If it was, we would use + * PIP_GBL_CFG[RAW_SHF] instead of + * PIP_GBL_CFG[NIP_SHF]. + */ + union cvmx_pip_gbl_cfg pip_gbl_cfg; + pip_gbl_cfg.u64 = cvmx_read_csr(CVMX_PIP_GBL_CFG); + buffer_ptr.s.addr += pip_gbl_cfg.s.nip_shf; + } + } else + buffer_ptr = work->packet_ptr; + remaining_bytes = work->len; + + while (remaining_bytes) { + start_of_buffer = + ((buffer_ptr.s.addr >> 7) - buffer_ptr.s.back) << 7; + cvmx_dprintf(" Buffer Start:%llx\n", + (unsigned long long)start_of_buffer); + cvmx_dprintf(" Buffer I : %u\n", buffer_ptr.s.i); + cvmx_dprintf(" Buffer Back: %u\n", buffer_ptr.s.back); + cvmx_dprintf(" Buffer Pool: %u\n", buffer_ptr.s.pool); + cvmx_dprintf(" Buffer Data: %llx\n", + (unsigned long long)buffer_ptr.s.addr); + cvmx_dprintf(" Buffer Size: %u\n", buffer_ptr.s.size); + + cvmx_dprintf("\t\t"); + data_address = (uint8_t *) cvmx_phys_to_ptr(buffer_ptr.s.addr); + end_of_data = data_address + buffer_ptr.s.size; + count = 0; + while (data_address < end_of_data) { + if (remaining_bytes == 0) + break; + else + remaining_bytes--; + cvmx_dprintf("%02x", (unsigned int)*data_address); + data_address++; + if (remaining_bytes && (count == 7)) { + cvmx_dprintf("\n\t\t"); + count = 0; + } else + count++; + } + cvmx_dprintf("\n"); + + if (remaining_bytes) + buffer_ptr = *(union cvmx_buf_ptr *) + cvmx_phys_to_ptr(buffer_ptr.s.addr - 8); + } + return 0; +} + +/** + * Setup Random Early Drop on a specific input queue + * + * @queue: Input queue to setup RED on (0-7) + * @pass_thresh: + * Packets will begin slowly dropping when there are less than + * this many packet buffers free in FPA 0. + * @drop_thresh: + * All incomming packets will be dropped when there are less + * than this many free packet buffers in FPA 0. + * Returns Zero on success. Negative on failure + */ +int cvmx_helper_setup_red_queue(int queue, int pass_thresh, int drop_thresh) +{ + union cvmx_ipd_qosx_red_marks red_marks; + union cvmx_ipd_red_quex_param red_param; + + /* Set RED to begin dropping packets when there are pass_thresh buffers + left. It will linearly drop more packets until reaching drop_thresh + buffers */ + red_marks.u64 = 0; + red_marks.s.drop = drop_thresh; + red_marks.s.pass = pass_thresh; + cvmx_write_csr(CVMX_IPD_QOSX_RED_MARKS(queue), red_marks.u64); + + /* Use the actual queue 0 counter, not the average */ + red_param.u64 = 0; + red_param.s.prb_con = + (255ul << 24) / (red_marks.s.pass - red_marks.s.drop); + red_param.s.avg_con = 1; + red_param.s.new_con = 255; + red_param.s.use_pcnt = 1; + cvmx_write_csr(CVMX_IPD_RED_QUEX_PARAM(queue), red_param.u64); + return 0; +} + +/** + * Setup Random Early Drop to automatically begin dropping packets. + * + * @pass_thresh: + * Packets will begin slowly dropping when there are less than + * this many packet buffers free in FPA 0. + * @drop_thresh: + * All incomming packets will be dropped when there are less + * than this many free packet buffers in FPA 0. + * Returns Zero on success. Negative on failure + */ +int cvmx_helper_setup_red(int pass_thresh, int drop_thresh) +{ + union cvmx_ipd_portx_bp_page_cnt page_cnt; + union cvmx_ipd_bp_prt_red_end ipd_bp_prt_red_end; + union cvmx_ipd_red_port_enable red_port_enable; + int queue; + int interface; + int port; + + /* Disable backpressure based on queued buffers. It needs SW support */ + page_cnt.u64 = 0; + page_cnt.s.bp_enb = 0; + page_cnt.s.page_cnt = 100; + for (interface = 0; interface < 2; interface++) { + for (port = cvmx_helper_get_first_ipd_port(interface); + port < cvmx_helper_get_last_ipd_port(interface); port++) + cvmx_write_csr(CVMX_IPD_PORTX_BP_PAGE_CNT(port), + page_cnt.u64); + } + + for (queue = 0; queue < 8; queue++) + cvmx_helper_setup_red_queue(queue, pass_thresh, drop_thresh); + + /* Shutoff the dropping based on the per port page count. SW isn't + decrementing it right now */ + ipd_bp_prt_red_end.u64 = 0; + ipd_bp_prt_red_end.s.prt_enb = 0; + cvmx_write_csr(CVMX_IPD_BP_PRT_RED_END, ipd_bp_prt_red_end.u64); + + red_port_enable.u64 = 0; + red_port_enable.s.prt_enb = 0xfffffffffull; + red_port_enable.s.avg_dly = 10000; + red_port_enable.s.prb_dly = 10000; + cvmx_write_csr(CVMX_IPD_RED_PORT_ENABLE, red_port_enable.u64); + + return 0; +} + +/** + * Setup the common GMX settings that determine the number of + * ports. These setting apply to almost all configurations of all + * chips. + * + * @interface: Interface to configure + * @num_ports: Number of ports on the interface + * + * Returns Zero on success, negative on failure + */ +int __cvmx_helper_setup_gmx(int interface, int num_ports) +{ + union cvmx_gmxx_tx_prts gmx_tx_prts; + union cvmx_gmxx_rx_prts gmx_rx_prts; + union cvmx_pko_reg_gmx_port_mode pko_mode; + union cvmx_gmxx_txx_thresh gmx_tx_thresh; + int index; + + /* Tell GMX the number of TX ports on this interface */ + gmx_tx_prts.u64 = cvmx_read_csr(CVMX_GMXX_TX_PRTS(interface)); + gmx_tx_prts.s.prts = num_ports; + cvmx_write_csr(CVMX_GMXX_TX_PRTS(interface), gmx_tx_prts.u64); + + /* Tell GMX the number of RX ports on this interface. This only + ** applies to *GMII and XAUI ports */ + if (cvmx_helper_interface_get_mode(interface) == + CVMX_HELPER_INTERFACE_MODE_RGMII + || cvmx_helper_interface_get_mode(interface) == + CVMX_HELPER_INTERFACE_MODE_SGMII + || cvmx_helper_interface_get_mode(interface) == + CVMX_HELPER_INTERFACE_MODE_GMII + || cvmx_helper_interface_get_mode(interface) == + CVMX_HELPER_INTERFACE_MODE_XAUI) { + if (num_ports > 4) { + cvmx_dprintf("__cvmx_helper_setup_gmx: Illegal " + "num_ports\n"); + return -1; + } + + gmx_rx_prts.u64 = cvmx_read_csr(CVMX_GMXX_RX_PRTS(interface)); + gmx_rx_prts.s.prts = num_ports; + cvmx_write_csr(CVMX_GMXX_RX_PRTS(interface), gmx_rx_prts.u64); + } + + /* Skip setting CVMX_PKO_REG_GMX_PORT_MODE on 30XX, 31XX, and 50XX */ + if (!OCTEON_IS_MODEL(OCTEON_CN30XX) && !OCTEON_IS_MODEL(OCTEON_CN31XX) + && !OCTEON_IS_MODEL(OCTEON_CN50XX)) { + /* Tell PKO the number of ports on this interface */ + pko_mode.u64 = cvmx_read_csr(CVMX_PKO_REG_GMX_PORT_MODE); + if (interface == 0) { + if (num_ports == 1) + pko_mode.s.mode0 = 4; + else if (num_ports == 2) + pko_mode.s.mode0 = 3; + else if (num_ports <= 4) + pko_mode.s.mode0 = 2; + else if (num_ports <= 8) + pko_mode.s.mode0 = 1; + else + pko_mode.s.mode0 = 0; + } else { + if (num_ports == 1) + pko_mode.s.mode1 = 4; + else if (num_ports == 2) + pko_mode.s.mode1 = 3; + else if (num_ports <= 4) + pko_mode.s.mode1 = 2; + else if (num_ports <= 8) + pko_mode.s.mode1 = 1; + else + pko_mode.s.mode1 = 0; + } + cvmx_write_csr(CVMX_PKO_REG_GMX_PORT_MODE, pko_mode.u64); + } + + /* + * Set GMX to buffer as much data as possible before starting + * transmit. This reduces the chances that we have a TX under + * run due to memory contention. Any packet that fits entirely + * in the GMX FIFO can never have an under run regardless of + * memory load. + */ + gmx_tx_thresh.u64 = cvmx_read_csr(CVMX_GMXX_TXX_THRESH(0, interface)); + if (OCTEON_IS_MODEL(OCTEON_CN30XX) || OCTEON_IS_MODEL(OCTEON_CN31XX) + || OCTEON_IS_MODEL(OCTEON_CN50XX)) { + /* These chips have a fixed max threshold of 0x40 */ + gmx_tx_thresh.s.cnt = 0x40; + } else { + /* Choose the max value for the number of ports */ + if (num_ports <= 1) + gmx_tx_thresh.s.cnt = 0x100 / 1; + else if (num_ports == 2) + gmx_tx_thresh.s.cnt = 0x100 / 2; + else + gmx_tx_thresh.s.cnt = 0x100 / 4; + } + /* + * SPI and XAUI can have lots of ports but the GMX hardware + * only ever has a max of 4. + */ + if (num_ports > 4) + num_ports = 4; + for (index = 0; index < num_ports; index++) + cvmx_write_csr(CVMX_GMXX_TXX_THRESH(index, interface), + gmx_tx_thresh.u64); + + return 0; +} + +/** + * Returns the IPD/PKO port number for a port on teh given + * interface. + * + * @interface: Interface to use + * @port: Port on the interface + * + * Returns IPD/PKO port number + */ +int cvmx_helper_get_ipd_port(int interface, int port) +{ + switch (interface) { + case 0: + return port; + case 1: + return port + 16; + case 2: + return port + 32; + case 3: + return port + 36; + } + return -1; +} + +/** + * Returns the interface number for an IPD/PKO port number. + * + * @ipd_port: IPD/PKO port number + * + * Returns Interface number + */ +int cvmx_helper_get_interface_num(int ipd_port) +{ + if (ipd_port < 16) + return 0; + else if (ipd_port < 32) + return 1; + else if (ipd_port < 36) + return 2; + else if (ipd_port < 40) + return 3; + else + cvmx_dprintf("cvmx_helper_get_interface_num: Illegal IPD " + "port number\n"); + + return -1; +} + +/** + * Returns the interface index number for an IPD/PKO port + * number. + * + * @ipd_port: IPD/PKO port number + * + * Returns Interface index number + */ +int cvmx_helper_get_interface_index_num(int ipd_port) +{ + if (ipd_port < 32) + return ipd_port & 15; + else if (ipd_port < 36) + return ipd_port & 3; + else if (ipd_port < 40) + return ipd_port & 3; + else + cvmx_dprintf("cvmx_helper_get_interface_index_num: " + "Illegal IPD port number\n"); + + return -1; +} diff --git a/drivers/staging/octeon/cvmx-helper-util.h b/drivers/staging/octeon/cvmx-helper-util.h new file mode 100644 index 0000000..6a6e52f --- /dev/null +++ b/drivers/staging/octeon/cvmx-helper-util.h @@ -0,0 +1,215 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * along with this file; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +/* + * + * Small helper utilities. + * + */ + +#ifndef __CVMX_HELPER_UTIL_H__ +#define __CVMX_HELPER_UTIL_H__ + +/** + * Convert a interface mode into a human readable string + * + * @mode: Mode to convert + * + * Returns String + */ +extern const char + *cvmx_helper_interface_mode_to_string(cvmx_helper_interface_mode_t mode); + +/** + * Debug routine to dump the packet structure to the console + * + * @work: Work queue entry containing the packet to dump + * Returns + */ +extern int cvmx_helper_dump_packet(cvmx_wqe_t *work); + +/** + * Setup Random Early Drop on a specific input queue + * + * @queue: Input queue to setup RED on (0-7) + * @pass_thresh: + * Packets will begin slowly dropping when there are less than + * this many packet buffers free in FPA 0. + * @drop_thresh: + * All incomming packets will be dropped when there are less + * than this many free packet buffers in FPA 0. + * Returns Zero on success. Negative on failure + */ +extern int cvmx_helper_setup_red_queue(int queue, int pass_thresh, + int drop_thresh); + +/** + * Setup Random Early Drop to automatically begin dropping packets. + * + * @pass_thresh: + * Packets will begin slowly dropping when there are less than + * this many packet buffers free in FPA 0. + * @drop_thresh: + * All incomming packets will be dropped when there are less + * than this many free packet buffers in FPA 0. + * Returns Zero on success. Negative on failure + */ +extern int cvmx_helper_setup_red(int pass_thresh, int drop_thresh); + +/** + * Get the version of the CVMX libraries. + * + * Returns Version string. Note this buffer is allocated statically + * and will be shared by all callers. + */ +extern const char *cvmx_helper_get_version(void); + +/** + * Setup the common GMX settings that determine the number of + * ports. These setting apply to almost all configurations of all + * chips. + * + * @interface: Interface to configure + * @num_ports: Number of ports on the interface + * + * Returns Zero on success, negative on failure + */ +extern int __cvmx_helper_setup_gmx(int interface, int num_ports); + +/** + * Returns the IPD/PKO port number for a port on the given + * interface. + * + * @interface: Interface to use + * @port: Port on the interface + * + * Returns IPD/PKO port number + */ +extern int cvmx_helper_get_ipd_port(int interface, int port); + +/** + * Returns the IPD/PKO port number for the first port on the given + * interface. + * + * @interface: Interface to use + * + * Returns IPD/PKO port number + */ +static inline int cvmx_helper_get_first_ipd_port(int interface) +{ + return cvmx_helper_get_ipd_port(interface, 0); +} + +/** + * Returns the IPD/PKO port number for the last port on the given + * interface. + * + * @interface: Interface to use + * + * Returns IPD/PKO port number + */ +static inline int cvmx_helper_get_last_ipd_port(int interface) +{ + extern int cvmx_helper_ports_on_interface(int interface); + + return cvmx_helper_get_first_ipd_port(interface) + + cvmx_helper_ports_on_interface(interface) - 1; +} + +/** + * Free the packet buffers contained in a work queue entry. + * The work queue entry is not freed. + * + * @work: Work queue entry with packet to free + */ +static inline void cvmx_helper_free_packet_data(cvmx_wqe_t *work) +{ + uint64_t number_buffers; + union cvmx_buf_ptr buffer_ptr; + union cvmx_buf_ptr next_buffer_ptr; + uint64_t start_of_buffer; + + number_buffers = work->word2.s.bufs; + if (number_buffers == 0) + return; + buffer_ptr = work->packet_ptr; + + /* + * Since the number of buffers is not zero, we know this is + * not a dynamic short packet. We need to check if it is a + * packet received with IPD_CTL_STATUS[NO_WPTR]. If this is + * true, we need to free all buffers except for the first + * one. The caller doesn't expect their WQE pointer to be + * freed + */ + start_of_buffer = ((buffer_ptr.s.addr >> 7) - buffer_ptr.s.back) << 7; + if (cvmx_ptr_to_phys(work) == start_of_buffer) { + next_buffer_ptr = + *(union cvmx_buf_ptr *) cvmx_phys_to_ptr(buffer_ptr.s.addr - 8); + buffer_ptr = next_buffer_ptr; + number_buffers--; + } + + while (number_buffers--) { + /* + * Remember the back pointer is in cache lines, not + * 64bit words + */ + start_of_buffer = + ((buffer_ptr.s.addr >> 7) - buffer_ptr.s.back) << 7; + /* + * Read pointer to next buffer before we free the + * current buffer. + */ + next_buffer_ptr = + *(union cvmx_buf_ptr *) cvmx_phys_to_ptr(buffer_ptr.s.addr - 8); + cvmx_fpa_free(cvmx_phys_to_ptr(start_of_buffer), + buffer_ptr.s.pool, 0); + buffer_ptr = next_buffer_ptr; + } +} + +/** + * Returns the interface number for an IPD/PKO port number. + * + * @ipd_port: IPD/PKO port number + * + * Returns Interface number + */ +extern int cvmx_helper_get_interface_num(int ipd_port); + +/** + * Returns the interface index number for an IPD/PKO port + * number. + * + * @ipd_port: IPD/PKO port number + * + * Returns Interface index number + */ +extern int cvmx_helper_get_interface_index_num(int ipd_port); + +#endif /* __CVMX_HELPER_H__ */ diff --git a/drivers/staging/octeon/cvmx-helper-xaui.c b/drivers/staging/octeon/cvmx-helper-xaui.c new file mode 100644 index 0000000..a11e676 --- /dev/null +++ b/drivers/staging/octeon/cvmx-helper-xaui.c @@ -0,0 +1,348 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * along with this file; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +/* + * Functions for XAUI initialization, configuration, + * and monitoring. + * + */ + +#include + +#include "cvmx-config.h" + +#include "cvmx-helper.h" + +#include "cvmx-pko-defs.h" +#include "cvmx-gmxx-defs.h" +#include "cvmx-pcsxx-defs.h" + +void __cvmx_interrupt_gmxx_enable(int interface); +void __cvmx_interrupt_pcsx_intx_en_reg_enable(int index, int block); +void __cvmx_interrupt_pcsxx_int_en_reg_enable(int index); +/** + * Probe a XAUI interface and determine the number of ports + * connected to it. The XAUI interface should still be down + * after this call. + * + * @interface: Interface to probe + * + * Returns Number of ports on the interface. Zero to disable. + */ +int __cvmx_helper_xaui_probe(int interface) +{ + int i; + union cvmx_gmxx_hg2_control gmx_hg2_control; + union cvmx_gmxx_inf_mode mode; + + /* + * Due to errata GMX-700 on CN56XXp1.x and CN52XXp1.x, the + * interface needs to be enabled before IPD otherwise per port + * backpressure may not work properly. + */ + mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface)); + mode.s.en = 1; + cvmx_write_csr(CVMX_GMXX_INF_MODE(interface), mode.u64); + + __cvmx_helper_setup_gmx(interface, 1); + + /* + * Setup PKO to support 16 ports for HiGig2 virtual + * ports. We're pointing all of the PKO packet ports for this + * interface to the XAUI. This allows us to use HiGig2 + * backpressure per port. + */ + for (i = 0; i < 16; i++) { + union cvmx_pko_mem_port_ptrs pko_mem_port_ptrs; + pko_mem_port_ptrs.u64 = 0; + /* + * We set each PKO port to have equal priority in a + * round robin fashion. + */ + pko_mem_port_ptrs.s.static_p = 0; + pko_mem_port_ptrs.s.qos_mask = 0xff; + /* All PKO ports map to the same XAUI hardware port */ + pko_mem_port_ptrs.s.eid = interface * 4; + pko_mem_port_ptrs.s.pid = interface * 16 + i; + cvmx_write_csr(CVMX_PKO_MEM_PORT_PTRS, pko_mem_port_ptrs.u64); + } + + /* If HiGig2 is enabled return 16 ports, otherwise return 1 port */ + gmx_hg2_control.u64 = cvmx_read_csr(CVMX_GMXX_HG2_CONTROL(interface)); + if (gmx_hg2_control.s.hg2tx_en) + return 16; + else + return 1; +} + +/** + * Bringup and enable a XAUI interface. After this call packet + * I/O should be fully functional. This is called with IPD + * enabled but PKO disabled. + * + * @interface: Interface to bring up + * + * Returns Zero on success, negative on failure + */ +int __cvmx_helper_xaui_enable(int interface) +{ + union cvmx_gmxx_prtx_cfg gmx_cfg; + union cvmx_pcsxx_control1_reg xauiCtl; + union cvmx_pcsxx_misc_ctl_reg xauiMiscCtl; + union cvmx_gmxx_tx_xaui_ctl gmxXauiTxCtl; + union cvmx_gmxx_rxx_int_en gmx_rx_int_en; + union cvmx_gmxx_tx_int_en gmx_tx_int_en; + union cvmx_pcsxx_int_en_reg pcsx_int_en_reg; + + /* (1) Interface has already been enabled. */ + + /* (2) Disable GMX. */ + xauiMiscCtl.u64 = cvmx_read_csr(CVMX_PCSXX_MISC_CTL_REG(interface)); + xauiMiscCtl.s.gmxeno = 1; + cvmx_write_csr(CVMX_PCSXX_MISC_CTL_REG(interface), xauiMiscCtl.u64); + + /* (3) Disable GMX and PCSX interrupts. */ + gmx_rx_int_en.u64 = cvmx_read_csr(CVMX_GMXX_RXX_INT_EN(0, interface)); + cvmx_write_csr(CVMX_GMXX_RXX_INT_EN(0, interface), 0x0); + gmx_tx_int_en.u64 = cvmx_read_csr(CVMX_GMXX_TX_INT_EN(interface)); + cvmx_write_csr(CVMX_GMXX_TX_INT_EN(interface), 0x0); + pcsx_int_en_reg.u64 = cvmx_read_csr(CVMX_PCSXX_INT_EN_REG(interface)); + cvmx_write_csr(CVMX_PCSXX_INT_EN_REG(interface), 0x0); + + /* (4) Bring up the PCSX and GMX reconciliation layer. */ + /* (4)a Set polarity and lane swapping. */ + /* (4)b */ + gmxXauiTxCtl.u64 = cvmx_read_csr(CVMX_GMXX_TX_XAUI_CTL(interface)); + /* Enable better IFG packing and improves performance */ + gmxXauiTxCtl.s.dic_en = 1; + gmxXauiTxCtl.s.uni_en = 0; + cvmx_write_csr(CVMX_GMXX_TX_XAUI_CTL(interface), gmxXauiTxCtl.u64); + + /* (4)c Aply reset sequence */ + xauiCtl.u64 = cvmx_read_csr(CVMX_PCSXX_CONTROL1_REG(interface)); + xauiCtl.s.lo_pwr = 0; + xauiCtl.s.reset = 1; + cvmx_write_csr(CVMX_PCSXX_CONTROL1_REG(interface), xauiCtl.u64); + + /* Wait for PCS to come out of reset */ + if (CVMX_WAIT_FOR_FIELD64 + (CVMX_PCSXX_CONTROL1_REG(interface), union cvmx_pcsxx_control1_reg, + reset, ==, 0, 10000)) + return -1; + /* Wait for PCS to be aligned */ + if (CVMX_WAIT_FOR_FIELD64 + (CVMX_PCSXX_10GBX_STATUS_REG(interface), + union cvmx_pcsxx_10gbx_status_reg, alignd, ==, 1, 10000)) + return -1; + /* Wait for RX to be ready */ + if (CVMX_WAIT_FOR_FIELD64 + (CVMX_GMXX_RX_XAUI_CTL(interface), union cvmx_gmxx_rx_xaui_ctl, + status, ==, 0, 10000)) + return -1; + + /* (6) Configure GMX */ + gmx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(0, interface)); + gmx_cfg.s.en = 0; + cvmx_write_csr(CVMX_GMXX_PRTX_CFG(0, interface), gmx_cfg.u64); + + /* Wait for GMX RX to be idle */ + if (CVMX_WAIT_FOR_FIELD64 + (CVMX_GMXX_PRTX_CFG(0, interface), union cvmx_gmxx_prtx_cfg, + rx_idle, ==, 1, 10000)) + return -1; + /* Wait for GMX TX to be idle */ + if (CVMX_WAIT_FOR_FIELD64 + (CVMX_GMXX_PRTX_CFG(0, interface), union cvmx_gmxx_prtx_cfg, + tx_idle, ==, 1, 10000)) + return -1; + + /* GMX configure */ + gmx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(0, interface)); + gmx_cfg.s.speed = 1; + gmx_cfg.s.speed_msb = 0; + gmx_cfg.s.slottime = 1; + cvmx_write_csr(CVMX_GMXX_TX_PRTS(interface), 1); + cvmx_write_csr(CVMX_GMXX_TXX_SLOT(0, interface), 512); + cvmx_write_csr(CVMX_GMXX_TXX_BURST(0, interface), 8192); + cvmx_write_csr(CVMX_GMXX_PRTX_CFG(0, interface), gmx_cfg.u64); + + /* (7) Clear out any error state */ + cvmx_write_csr(CVMX_GMXX_RXX_INT_REG(0, interface), + cvmx_read_csr(CVMX_GMXX_RXX_INT_REG(0, interface))); + cvmx_write_csr(CVMX_GMXX_TX_INT_REG(interface), + cvmx_read_csr(CVMX_GMXX_TX_INT_REG(interface))); + cvmx_write_csr(CVMX_PCSXX_INT_REG(interface), + cvmx_read_csr(CVMX_PCSXX_INT_REG(interface))); + + /* Wait for receive link */ + if (CVMX_WAIT_FOR_FIELD64 + (CVMX_PCSXX_STATUS1_REG(interface), union cvmx_pcsxx_status1_reg, + rcv_lnk, ==, 1, 10000)) + return -1; + if (CVMX_WAIT_FOR_FIELD64 + (CVMX_PCSXX_STATUS2_REG(interface), union cvmx_pcsxx_status2_reg, + xmtflt, ==, 0, 10000)) + return -1; + if (CVMX_WAIT_FOR_FIELD64 + (CVMX_PCSXX_STATUS2_REG(interface), union cvmx_pcsxx_status2_reg, + rcvflt, ==, 0, 10000)) + return -1; + + cvmx_write_csr(CVMX_GMXX_RXX_INT_EN(0, interface), gmx_rx_int_en.u64); + cvmx_write_csr(CVMX_GMXX_TX_INT_EN(interface), gmx_tx_int_en.u64); + cvmx_write_csr(CVMX_PCSXX_INT_EN_REG(interface), pcsx_int_en_reg.u64); + + cvmx_helper_link_autoconf(cvmx_helper_get_ipd_port(interface, 0)); + + /* (8) Enable packet reception */ + xauiMiscCtl.s.gmxeno = 0; + cvmx_write_csr(CVMX_PCSXX_MISC_CTL_REG(interface), xauiMiscCtl.u64); + + gmx_cfg.u64 = cvmx_read_csr(CVMX_GMXX_PRTX_CFG(0, interface)); + gmx_cfg.s.en = 1; + cvmx_write_csr(CVMX_GMXX_PRTX_CFG(0, interface), gmx_cfg.u64); + + __cvmx_interrupt_pcsx_intx_en_reg_enable(0, interface); + __cvmx_interrupt_pcsx_intx_en_reg_enable(1, interface); + __cvmx_interrupt_pcsx_intx_en_reg_enable(2, interface); + __cvmx_interrupt_pcsx_intx_en_reg_enable(3, interface); + __cvmx_interrupt_pcsxx_int_en_reg_enable(interface); + __cvmx_interrupt_gmxx_enable(interface); + + return 0; +} + +/** + * Return the link state of an IPD/PKO port as returned by + * auto negotiation. The result of this function may not match + * Octeon's link config if auto negotiation has changed since + * the last call to cvmx_helper_link_set(). + * + * @ipd_port: IPD/PKO port to query + * + * Returns Link state + */ +cvmx_helper_link_info_t __cvmx_helper_xaui_link_get(int ipd_port) +{ + int interface = cvmx_helper_get_interface_num(ipd_port); + union cvmx_gmxx_tx_xaui_ctl gmxx_tx_xaui_ctl; + union cvmx_gmxx_rx_xaui_ctl gmxx_rx_xaui_ctl; + union cvmx_pcsxx_status1_reg pcsxx_status1_reg; + cvmx_helper_link_info_t result; + + gmxx_tx_xaui_ctl.u64 = cvmx_read_csr(CVMX_GMXX_TX_XAUI_CTL(interface)); + gmxx_rx_xaui_ctl.u64 = cvmx_read_csr(CVMX_GMXX_RX_XAUI_CTL(interface)); + pcsxx_status1_reg.u64 = + cvmx_read_csr(CVMX_PCSXX_STATUS1_REG(interface)); + result.u64 = 0; + + /* Only return a link if both RX and TX are happy */ + if ((gmxx_tx_xaui_ctl.s.ls == 0) && (gmxx_rx_xaui_ctl.s.status == 0) && + (pcsxx_status1_reg.s.rcv_lnk == 1)) { + result.s.link_up = 1; + result.s.full_duplex = 1; + result.s.speed = 10000; + } else { + /* Disable GMX and PCSX interrupts. */ + cvmx_write_csr(CVMX_GMXX_RXX_INT_EN(0, interface), 0x0); + cvmx_write_csr(CVMX_GMXX_TX_INT_EN(interface), 0x0); + cvmx_write_csr(CVMX_PCSXX_INT_EN_REG(interface), 0x0); + } + return result; +} + +/** + * Configure an IPD/PKO port for the specified link state. This + * function does not influence auto negotiation at the PHY level. + * The passed link state must always match the link state returned + * by cvmx_helper_link_get(). It is normally best to use + * cvmx_helper_link_autoconf() instead. + * + * @ipd_port: IPD/PKO port to configure + * @link_info: The new link state + * + * Returns Zero on success, negative on failure + */ +int __cvmx_helper_xaui_link_set(int ipd_port, cvmx_helper_link_info_t link_info) +{ + int interface = cvmx_helper_get_interface_num(ipd_port); + union cvmx_gmxx_tx_xaui_ctl gmxx_tx_xaui_ctl; + union cvmx_gmxx_rx_xaui_ctl gmxx_rx_xaui_ctl; + + gmxx_tx_xaui_ctl.u64 = cvmx_read_csr(CVMX_GMXX_TX_XAUI_CTL(interface)); + gmxx_rx_xaui_ctl.u64 = cvmx_read_csr(CVMX_GMXX_RX_XAUI_CTL(interface)); + + /* If the link shouldn't be up, then just return */ + if (!link_info.s.link_up) + return 0; + + /* Do nothing if both RX and TX are happy */ + if ((gmxx_tx_xaui_ctl.s.ls == 0) && (gmxx_rx_xaui_ctl.s.status == 0)) + return 0; + + /* Bring the link up */ + return __cvmx_helper_xaui_enable(interface); +} + +/** + * Configure a port for internal and/or external loopback. Internal loopback + * causes packets sent by the port to be received by Octeon. External loopback + * causes packets received from the wire to sent out again. + * + * @ipd_port: IPD/PKO port to loopback. + * @enable_internal: + * Non zero if you want internal loopback + * @enable_external: + * Non zero if you want external loopback + * + * Returns Zero on success, negative on failure. + */ +extern int __cvmx_helper_xaui_configure_loopback(int ipd_port, + int enable_internal, + int enable_external) +{ + int interface = cvmx_helper_get_interface_num(ipd_port); + union cvmx_pcsxx_control1_reg pcsxx_control1_reg; + union cvmx_gmxx_xaui_ext_loopback gmxx_xaui_ext_loopback; + + /* Set the internal loop */ + pcsxx_control1_reg.u64 = + cvmx_read_csr(CVMX_PCSXX_CONTROL1_REG(interface)); + pcsxx_control1_reg.s.loopbck1 = enable_internal; + cvmx_write_csr(CVMX_PCSXX_CONTROL1_REG(interface), + pcsxx_control1_reg.u64); + + /* Set the external loop */ + gmxx_xaui_ext_loopback.u64 = + cvmx_read_csr(CVMX_GMXX_XAUI_EXT_LOOPBACK(interface)); + gmxx_xaui_ext_loopback.s.en = enable_external; + cvmx_write_csr(CVMX_GMXX_XAUI_EXT_LOOPBACK(interface), + gmxx_xaui_ext_loopback.u64); + + /* Take the link through a reset */ + return __cvmx_helper_xaui_enable(interface); +} diff --git a/drivers/staging/octeon/cvmx-helper-xaui.h b/drivers/staging/octeon/cvmx-helper-xaui.h new file mode 100644 index 0000000..4b4db2f --- /dev/null +++ b/drivers/staging/octeon/cvmx-helper-xaui.h @@ -0,0 +1,103 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * along with this file; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +/** + * @file + * + * Functions for XAUI initialization, configuration, + * and monitoring. + * + */ +#ifndef __CVMX_HELPER_XAUI_H__ +#define __CVMX_HELPER_XAUI_H__ + +/** + * Probe a XAUI interface and determine the number of ports + * connected to it. The XAUI interface should still be down + * after this call. + * + * @interface: Interface to probe + * + * Returns Number of ports on the interface. Zero to disable. + */ +extern int __cvmx_helper_xaui_probe(int interface); + +/** + * Bringup and enable a XAUI interface. After this call packet + * I/O should be fully functional. This is called with IPD + * enabled but PKO disabled. + * + * @interface: Interface to bring up + * + * Returns Zero on success, negative on failure + */ +extern int __cvmx_helper_xaui_enable(int interface); + +/** + * Return the link state of an IPD/PKO port as returned by + * auto negotiation. The result of this function may not match + * Octeon's link config if auto negotiation has changed since + * the last call to cvmx_helper_link_set(). + * + * @ipd_port: IPD/PKO port to query + * + * Returns Link state + */ +extern cvmx_helper_link_info_t __cvmx_helper_xaui_link_get(int ipd_port); + +/** + * Configure an IPD/PKO port for the specified link state. This + * function does not influence auto negotiation at the PHY level. + * The passed link state must always match the link state returned + * by cvmx_helper_link_get(). It is normally best to use + * cvmx_helper_link_autoconf() instead. + * + * @ipd_port: IPD/PKO port to configure + * @link_info: The new link state + * + * Returns Zero on success, negative on failure + */ +extern int __cvmx_helper_xaui_link_set(int ipd_port, + cvmx_helper_link_info_t link_info); + +/** + * Configure a port for internal and/or external loopback. Internal loopback + * causes packets sent by the port to be received by Octeon. External loopback + * causes packets received from the wire to sent out again. + * + * @ipd_port: IPD/PKO port to loopback. + * @enable_internal: + * Non zero if you want internal loopback + * @enable_external: + * Non zero if you want external loopback + * + * Returns Zero on success, negative on failure. + */ +extern int __cvmx_helper_xaui_configure_loopback(int ipd_port, + int enable_internal, + int enable_external); +#endif diff --git a/drivers/staging/octeon/cvmx-helper.c b/drivers/staging/octeon/cvmx-helper.c new file mode 100644 index 0000000..5915066 --- /dev/null +++ b/drivers/staging/octeon/cvmx-helper.c @@ -0,0 +1,1058 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * along with this file; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +/* + * + * Helper functions for common, but complicated tasks. + * + */ +#include + +#include "cvmx-config.h" + +#include "cvmx-fpa.h" +#include "cvmx-pip.h" +#include "cvmx-pko.h" +#include "cvmx-ipd.h" +#include "cvmx-spi.h" +#include "cvmx-helper.h" +#include "cvmx-helper-board.h" + +#include "cvmx-pip-defs.h" +#include "cvmx-smix-defs.h" +#include "cvmx-asxx-defs.h" + +/** + * cvmx_override_pko_queue_priority(int ipd_port, uint64_t + * priorities[16]) is a function pointer. It is meant to allow + * customization of the PKO queue priorities based on the port + * number. Users should set this pointer to a function before + * calling any cvmx-helper operations. + */ +void (*cvmx_override_pko_queue_priority) (int pko_port, + uint64_t priorities[16]); + +/** + * cvmx_override_ipd_port_setup(int ipd_port) is a function + * pointer. It is meant to allow customization of the IPD port + * setup before packet input/output comes online. It is called + * after cvmx-helper does the default IPD configuration, but + * before IPD is enabled. Users should set this pointer to a + * function before calling any cvmx-helper operations. + */ +void (*cvmx_override_ipd_port_setup) (int ipd_port); + +/* Port count per interface */ +static int interface_port_count[4] = { 0, 0, 0, 0 }; + +/* Port last configured link info index by IPD/PKO port */ +static cvmx_helper_link_info_t + port_link_info[CVMX_PIP_NUM_INPUT_PORTS]; + +/** + * Return the number of interfaces the chip has. Each interface + * may have multiple ports. Most chips support two interfaces, + * but the CNX0XX and CNX1XX are exceptions. These only support + * one interface. + * + * Returns Number of interfaces on chip + */ +int cvmx_helper_get_number_of_interfaces(void) +{ + if (OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN52XX)) + return 4; + else + return 3; +} + +/** + * Return the number of ports on an interface. Depending on the + * chip and configuration, this can be 1-16. A value of 0 + * specifies that the interface doesn't exist or isn't usable. + * + * @interface: Interface to get the port count for + * + * Returns Number of ports on interface. Can be Zero. + */ +int cvmx_helper_ports_on_interface(int interface) +{ + return interface_port_count[interface]; +} + +/** + * Get the operating mode of an interface. Depending on the Octeon + * chip and configuration, this function returns an enumeration + * of the type of packet I/O supported by an interface. + * + * @interface: Interface to probe + * + * Returns Mode of the interface. Unknown or unsupported interfaces return + * DISABLED. + */ +cvmx_helper_interface_mode_t cvmx_helper_interface_get_mode(int interface) +{ + union cvmx_gmxx_inf_mode mode; + if (interface == 2) + return CVMX_HELPER_INTERFACE_MODE_NPI; + + if (interface == 3) { + if (OCTEON_IS_MODEL(OCTEON_CN56XX) + || OCTEON_IS_MODEL(OCTEON_CN52XX)) + return CVMX_HELPER_INTERFACE_MODE_LOOP; + else + return CVMX_HELPER_INTERFACE_MODE_DISABLED; + } + + if (interface == 0 + && cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_CN3005_EVB_HS5 + && cvmx_sysinfo_get()->board_rev_major == 1) { + /* + * Lie about interface type of CN3005 board. This + * board has a switch on port 1 like the other + * evaluation boards, but it is connected over RGMII + * instead of GMII. Report GMII mode so that the + * speed is forced to 1 Gbit full duplex. Other than + * some initial configuration (which does not use the + * output of this function) there is no difference in + * setup between GMII and RGMII modes. + */ + return CVMX_HELPER_INTERFACE_MODE_GMII; + } + + /* Interface 1 is always disabled on CN31XX and CN30XX */ + if ((interface == 1) + && (OCTEON_IS_MODEL(OCTEON_CN31XX) || OCTEON_IS_MODEL(OCTEON_CN30XX) + || OCTEON_IS_MODEL(OCTEON_CN50XX) + || OCTEON_IS_MODEL(OCTEON_CN52XX))) + return CVMX_HELPER_INTERFACE_MODE_DISABLED; + + mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface)); + + if (OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN52XX)) { + switch (mode.cn56xx.mode) { + case 0: + return CVMX_HELPER_INTERFACE_MODE_DISABLED; + case 1: + return CVMX_HELPER_INTERFACE_MODE_XAUI; + case 2: + return CVMX_HELPER_INTERFACE_MODE_SGMII; + case 3: + return CVMX_HELPER_INTERFACE_MODE_PICMG; + default: + return CVMX_HELPER_INTERFACE_MODE_DISABLED; + } + } else { + if (!mode.s.en) + return CVMX_HELPER_INTERFACE_MODE_DISABLED; + + if (mode.s.type) { + if (OCTEON_IS_MODEL(OCTEON_CN38XX) + || OCTEON_IS_MODEL(OCTEON_CN58XX)) + return CVMX_HELPER_INTERFACE_MODE_SPI; + else + return CVMX_HELPER_INTERFACE_MODE_GMII; + } else + return CVMX_HELPER_INTERFACE_MODE_RGMII; + } +} + +/** + * Configure the IPD/PIP tagging and QoS options for a specific + * port. This function determines the POW work queue entry + * contents for a port. The setup performed here is controlled by + * the defines in executive-config.h. + * + * @ipd_port: Port to configure. This follows the IPD numbering, not the + * per interface numbering + * + * Returns Zero on success, negative on failure + */ +static int __cvmx_helper_port_setup_ipd(int ipd_port) +{ + union cvmx_pip_prt_cfgx port_config; + union cvmx_pip_prt_tagx tag_config; + + port_config.u64 = cvmx_read_csr(CVMX_PIP_PRT_CFGX(ipd_port)); + tag_config.u64 = cvmx_read_csr(CVMX_PIP_PRT_TAGX(ipd_port)); + + /* Have each port go to a different POW queue */ + port_config.s.qos = ipd_port & 0x7; + + /* Process the headers and place the IP header in the work queue */ + port_config.s.mode = CVMX_HELPER_INPUT_PORT_SKIP_MODE; + + tag_config.s.ip6_src_flag = CVMX_HELPER_INPUT_TAG_IPV6_SRC_IP; + tag_config.s.ip6_dst_flag = CVMX_HELPER_INPUT_TAG_IPV6_DST_IP; + tag_config.s.ip6_sprt_flag = CVMX_HELPER_INPUT_TAG_IPV6_SRC_PORT; + tag_config.s.ip6_dprt_flag = CVMX_HELPER_INPUT_TAG_IPV6_DST_PORT; + tag_config.s.ip6_nxth_flag = CVMX_HELPER_INPUT_TAG_IPV6_NEXT_HEADER; + tag_config.s.ip4_src_flag = CVMX_HELPER_INPUT_TAG_IPV4_SRC_IP; + tag_config.s.ip4_dst_flag = CVMX_HELPER_INPUT_TAG_IPV4_DST_IP; + tag_config.s.ip4_sprt_flag = CVMX_HELPER_INPUT_TAG_IPV4_SRC_PORT; + tag_config.s.ip4_dprt_flag = CVMX_HELPER_INPUT_TAG_IPV4_DST_PORT; + tag_config.s.ip4_pctl_flag = CVMX_HELPER_INPUT_TAG_IPV4_PROTOCOL; + tag_config.s.inc_prt_flag = CVMX_HELPER_INPUT_TAG_INPUT_PORT; + tag_config.s.tcp6_tag_type = CVMX_HELPER_INPUT_TAG_TYPE; + tag_config.s.tcp4_tag_type = CVMX_HELPER_INPUT_TAG_TYPE; + tag_config.s.ip6_tag_type = CVMX_HELPER_INPUT_TAG_TYPE; + tag_config.s.ip4_tag_type = CVMX_HELPER_INPUT_TAG_TYPE; + tag_config.s.non_tag_type = CVMX_HELPER_INPUT_TAG_TYPE; + /* Put all packets in group 0. Other groups can be used by the app */ + tag_config.s.grp = 0; + + cvmx_pip_config_port(ipd_port, port_config, tag_config); + + /* Give the user a chance to override our setting for each port */ + if (cvmx_override_ipd_port_setup) + cvmx_override_ipd_port_setup(ipd_port); + + return 0; +} + +/** + * This function probes an interface to determine the actual + * number of hardware ports connected to it. It doesn't setup the + * ports or enable them. The main goal here is to set the global + * interface_port_count[interface] correctly. Hardware setup of the + * ports will be performed later. + * + * @interface: Interface to probe + * + * Returns Zero on success, negative on failure + */ +int cvmx_helper_interface_probe(int interface) +{ + /* At this stage in the game we don't want packets to be moving yet. + The following probe calls should perform hardware setup + needed to determine port counts. Receive must still be disabled */ + switch (cvmx_helper_interface_get_mode(interface)) { + /* These types don't support ports to IPD/PKO */ + case CVMX_HELPER_INTERFACE_MODE_DISABLED: + case CVMX_HELPER_INTERFACE_MODE_PCIE: + interface_port_count[interface] = 0; + break; + /* XAUI is a single high speed port */ + case CVMX_HELPER_INTERFACE_MODE_XAUI: + interface_port_count[interface] = + __cvmx_helper_xaui_probe(interface); + break; + /* + * RGMII/GMII/MII are all treated about the same. Most + * functions refer to these ports as RGMII. + */ + case CVMX_HELPER_INTERFACE_MODE_RGMII: + case CVMX_HELPER_INTERFACE_MODE_GMII: + interface_port_count[interface] = + __cvmx_helper_rgmii_probe(interface); + break; + /* + * SPI4 can have 1-16 ports depending on the device at + * the other end. + */ + case CVMX_HELPER_INTERFACE_MODE_SPI: + interface_port_count[interface] = + __cvmx_helper_spi_probe(interface); + break; + /* + * SGMII can have 1-4 ports depending on how many are + * hooked up. + */ + case CVMX_HELPER_INTERFACE_MODE_SGMII: + case CVMX_HELPER_INTERFACE_MODE_PICMG: + interface_port_count[interface] = + __cvmx_helper_sgmii_probe(interface); + break; + /* PCI target Network Packet Interface */ + case CVMX_HELPER_INTERFACE_MODE_NPI: + interface_port_count[interface] = + __cvmx_helper_npi_probe(interface); + break; + /* + * Special loopback only ports. These are not the same + * as other ports in loopback mode. + */ + case CVMX_HELPER_INTERFACE_MODE_LOOP: + interface_port_count[interface] = + __cvmx_helper_loop_probe(interface); + break; + } + + interface_port_count[interface] = + __cvmx_helper_board_interface_probe(interface, + interface_port_count + [interface]); + + /* Make sure all global variables propagate to other cores */ + CVMX_SYNCWS; + + return 0; +} + +/** + * Setup the IPD/PIP for the ports on an interface. Packet + * classification and tagging are set for every port on the + * interface. The number of ports on the interface must already + * have been probed. + * + * @interface: Interface to setup IPD/PIP for + * + * Returns Zero on success, negative on failure + */ +static int __cvmx_helper_interface_setup_ipd(int interface) +{ + int ipd_port = cvmx_helper_get_ipd_port(interface, 0); + int num_ports = interface_port_count[interface]; + + while (num_ports--) { + __cvmx_helper_port_setup_ipd(ipd_port); + ipd_port++; + } + return 0; +} + +/** + * Setup global setting for IPD/PIP not related to a specific + * interface or port. This must be called before IPD is enabled. + * + * Returns Zero on success, negative on failure. + */ +static int __cvmx_helper_global_setup_ipd(void) +{ + /* Setup the global packet input options */ + cvmx_ipd_config(CVMX_FPA_PACKET_POOL_SIZE / 8, + CVMX_HELPER_FIRST_MBUFF_SKIP / 8, + CVMX_HELPER_NOT_FIRST_MBUFF_SKIP / 8, + /* The +8 is to account for the next ptr */ + (CVMX_HELPER_FIRST_MBUFF_SKIP + 8) / 128, + /* The +8 is to account for the next ptr */ + (CVMX_HELPER_NOT_FIRST_MBUFF_SKIP + 8) / 128, + CVMX_FPA_WQE_POOL, + CVMX_IPD_OPC_MODE_STT, + CVMX_HELPER_ENABLE_BACK_PRESSURE); + return 0; +} + +/** + * Setup the PKO for the ports on an interface. The number of + * queues per port and the priority of each PKO output queue + * is set here. PKO must be disabled when this function is called. + * + * @interface: Interface to setup PKO for + * + * Returns Zero on success, negative on failure + */ +static int __cvmx_helper_interface_setup_pko(int interface) +{ + /* + * Each packet output queue has an associated priority. The + * higher the priority, the more often it can send a packet. A + * priority of 8 means it can send in all 8 rounds of + * contention. We're going to make each queue one less than + * the last. The vector of priorities has been extended to + * support CN5xxx CPUs, where up to 16 queues can be + * associated to a port. To keep backward compatibility we + * don't change the initial 8 priorities and replicate them in + * the second half. With per-core PKO queues (PKO lockless + * operation) all queues have the same priority. + */ + uint64_t priorities[16] = + { 8, 7, 6, 5, 4, 3, 2, 1, 8, 7, 6, 5, 4, 3, 2, 1 }; + + /* + * Setup the IPD/PIP and PKO for the ports discovered + * above. Here packet classification, tagging and output + * priorities are set. + */ + int ipd_port = cvmx_helper_get_ipd_port(interface, 0); + int num_ports = interface_port_count[interface]; + while (num_ports--) { + /* + * Give the user a chance to override the per queue + * priorities. + */ + if (cvmx_override_pko_queue_priority) + cvmx_override_pko_queue_priority(ipd_port, priorities); + + cvmx_pko_config_port(ipd_port, + cvmx_pko_get_base_queue_per_core(ipd_port, + 0), + cvmx_pko_get_num_queues(ipd_port), + priorities); + ipd_port++; + } + return 0; +} + +/** + * Setup global setting for PKO not related to a specific + * interface or port. This must be called before PKO is enabled. + * + * Returns Zero on success, negative on failure. + */ +static int __cvmx_helper_global_setup_pko(void) +{ + /* + * Disable tagwait FAU timeout. This needs to be done before + * anyone might start packet output using tags. + */ + union cvmx_iob_fau_timeout fau_to; + fau_to.u64 = 0; + fau_to.s.tout_val = 0xfff; + fau_to.s.tout_enb = 0; + cvmx_write_csr(CVMX_IOB_FAU_TIMEOUT, fau_to.u64); + return 0; +} + +/** + * Setup global backpressure setting. + * + * Returns Zero on success, negative on failure + */ +static int __cvmx_helper_global_setup_backpressure(void) +{ +#if CVMX_HELPER_DISABLE_RGMII_BACKPRESSURE + /* Disable backpressure if configured to do so */ + /* Disable backpressure (pause frame) generation */ + int num_interfaces = cvmx_helper_get_number_of_interfaces(); + int interface; + for (interface = 0; interface < num_interfaces; interface++) { + switch (cvmx_helper_interface_get_mode(interface)) { + case CVMX_HELPER_INTERFACE_MODE_DISABLED: + case CVMX_HELPER_INTERFACE_MODE_PCIE: + case CVMX_HELPER_INTERFACE_MODE_NPI: + case CVMX_HELPER_INTERFACE_MODE_LOOP: + case CVMX_HELPER_INTERFACE_MODE_XAUI: + break; + case CVMX_HELPER_INTERFACE_MODE_RGMII: + case CVMX_HELPER_INTERFACE_MODE_GMII: + case CVMX_HELPER_INTERFACE_MODE_SPI: + case CVMX_HELPER_INTERFACE_MODE_SGMII: + case CVMX_HELPER_INTERFACE_MODE_PICMG: + cvmx_gmx_set_backpressure_override(interface, 0xf); + break; + } + } +#endif + + return 0; +} + +/** + * Enable packet input/output from the hardware. This function is + * called after all internal setup is complete and IPD is enabled. + * After this function completes, packets will be accepted from the + * hardware ports. PKO should still be disabled to make sure packets + * aren't sent out partially setup hardware. + * + * @interface: Interface to enable + * + * Returns Zero on success, negative on failure + */ +static int __cvmx_helper_packet_hardware_enable(int interface) +{ + int result = 0; + switch (cvmx_helper_interface_get_mode(interface)) { + /* These types don't support ports to IPD/PKO */ + case CVMX_HELPER_INTERFACE_MODE_DISABLED: + case CVMX_HELPER_INTERFACE_MODE_PCIE: + /* Nothing to do */ + break; + /* XAUI is a single high speed port */ + case CVMX_HELPER_INTERFACE_MODE_XAUI: + result = __cvmx_helper_xaui_enable(interface); + break; + /* + * RGMII/GMII/MII are all treated about the same. Most + * functions refer to these ports as RGMII + */ + case CVMX_HELPER_INTERFACE_MODE_RGMII: + case CVMX_HELPER_INTERFACE_MODE_GMII: + result = __cvmx_helper_rgmii_enable(interface); + break; + /* + * SPI4 can have 1-16 ports depending on the device at + * the other end + */ + case CVMX_HELPER_INTERFACE_MODE_SPI: + result = __cvmx_helper_spi_enable(interface); + break; + /* + * SGMII can have 1-4 ports depending on how many are + * hooked up + */ + case CVMX_HELPER_INTERFACE_MODE_SGMII: + case CVMX_HELPER_INTERFACE_MODE_PICMG: + result = __cvmx_helper_sgmii_enable(interface); + break; + /* PCI target Network Packet Interface */ + case CVMX_HELPER_INTERFACE_MODE_NPI: + result = __cvmx_helper_npi_enable(interface); + break; + /* + * Special loopback only ports. These are not the same + * as other ports in loopback mode + */ + case CVMX_HELPER_INTERFACE_MODE_LOOP: + result = __cvmx_helper_loop_enable(interface); + break; + } + result |= __cvmx_helper_board_hardware_enable(interface); + return result; +} + +/** + * Function to adjust internal IPD pointer alignments + * + * Returns 0 on success + * !0 on failure + */ +int __cvmx_helper_errata_fix_ipd_ptr_alignment(void) +{ +#define FIX_IPD_FIRST_BUFF_PAYLOAD_BYTES \ + (CVMX_FPA_PACKET_POOL_SIZE-8-CVMX_HELPER_FIRST_MBUFF_SKIP) +#define FIX_IPD_NON_FIRST_BUFF_PAYLOAD_BYTES \ + (CVMX_FPA_PACKET_POOL_SIZE-8-CVMX_HELPER_NOT_FIRST_MBUFF_SKIP) +#define FIX_IPD_OUTPORT 0 + /* Ports 0-15 are interface 0, 16-31 are interface 1 */ +#define INTERFACE(port) (port >> 4) +#define INDEX(port) (port & 0xf) + uint64_t *p64; + cvmx_pko_command_word0_t pko_command; + union cvmx_buf_ptr g_buffer, pkt_buffer; + cvmx_wqe_t *work; + int size, num_segs = 0, wqe_pcnt, pkt_pcnt; + union cvmx_gmxx_prtx_cfg gmx_cfg; + int retry_cnt; + int retry_loop_cnt; + int mtu; + int i; + cvmx_helper_link_info_t link_info; + + /* Save values for restore at end */ + uint64_t prtx_cfg = + cvmx_read_csr(CVMX_GMXX_PRTX_CFG + (INDEX(FIX_IPD_OUTPORT), INTERFACE(FIX_IPD_OUTPORT))); + uint64_t tx_ptr_en = + cvmx_read_csr(CVMX_ASXX_TX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT))); + uint64_t rx_ptr_en = + cvmx_read_csr(CVMX_ASXX_RX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT))); + uint64_t rxx_jabber = + cvmx_read_csr(CVMX_GMXX_RXX_JABBER + (INDEX(FIX_IPD_OUTPORT), INTERFACE(FIX_IPD_OUTPORT))); + uint64_t frame_max = + cvmx_read_csr(CVMX_GMXX_RXX_FRM_MAX + (INDEX(FIX_IPD_OUTPORT), INTERFACE(FIX_IPD_OUTPORT))); + + /* Configure port to gig FDX as required for loopback mode */ + cvmx_helper_rgmii_internal_loopback(FIX_IPD_OUTPORT); + + /* + * Disable reception on all ports so if traffic is present it + * will not interfere. + */ + cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT)), 0); + + cvmx_wait(100000000ull); + + for (retry_loop_cnt = 0; retry_loop_cnt < 10; retry_loop_cnt++) { + retry_cnt = 100000; + wqe_pcnt = cvmx_read_csr(CVMX_IPD_PTR_COUNT); + pkt_pcnt = (wqe_pcnt >> 7) & 0x7f; + wqe_pcnt &= 0x7f; + + num_segs = (2 + pkt_pcnt - wqe_pcnt) & 3; + + if (num_segs == 0) + goto fix_ipd_exit; + + num_segs += 1; + + size = + FIX_IPD_FIRST_BUFF_PAYLOAD_BYTES + + ((num_segs - 1) * FIX_IPD_NON_FIRST_BUFF_PAYLOAD_BYTES) - + (FIX_IPD_NON_FIRST_BUFF_PAYLOAD_BYTES / 2); + + cvmx_write_csr(CVMX_ASXX_PRT_LOOP(INTERFACE(FIX_IPD_OUTPORT)), + 1 << INDEX(FIX_IPD_OUTPORT)); + CVMX_SYNC; + + g_buffer.u64 = 0; + g_buffer.s.addr = + cvmx_ptr_to_phys(cvmx_fpa_alloc(CVMX_FPA_WQE_POOL)); + if (g_buffer.s.addr == 0) { + cvmx_dprintf("WARNING: FIX_IPD_PTR_ALIGNMENT " + "buffer allocation failure.\n"); + goto fix_ipd_exit; + } + + g_buffer.s.pool = CVMX_FPA_WQE_POOL; + g_buffer.s.size = num_segs; + + pkt_buffer.u64 = 0; + pkt_buffer.s.addr = + cvmx_ptr_to_phys(cvmx_fpa_alloc(CVMX_FPA_PACKET_POOL)); + if (pkt_buffer.s.addr == 0) { + cvmx_dprintf("WARNING: FIX_IPD_PTR_ALIGNMENT " + "buffer allocation failure.\n"); + goto fix_ipd_exit; + } + pkt_buffer.s.i = 1; + pkt_buffer.s.pool = CVMX_FPA_PACKET_POOL; + pkt_buffer.s.size = FIX_IPD_FIRST_BUFF_PAYLOAD_BYTES; + + p64 = (uint64_t *) cvmx_phys_to_ptr(pkt_buffer.s.addr); + p64[0] = 0xffffffffffff0000ull; + p64[1] = 0x08004510ull; + p64[2] = ((uint64_t) (size - 14) << 48) | 0x5ae740004000ull; + p64[3] = 0x3a5fc0a81073c0a8ull; + + for (i = 0; i < num_segs; i++) { + if (i > 0) + pkt_buffer.s.size = + FIX_IPD_NON_FIRST_BUFF_PAYLOAD_BYTES; + + if (i == (num_segs - 1)) + pkt_buffer.s.i = 0; + + *(uint64_t *) cvmx_phys_to_ptr(g_buffer.s.addr + + 8 * i) = pkt_buffer.u64; + } + + /* Build the PKO command */ + pko_command.u64 = 0; + pko_command.s.segs = num_segs; + pko_command.s.total_bytes = size; + pko_command.s.dontfree = 0; + pko_command.s.gather = 1; + + gmx_cfg.u64 = + cvmx_read_csr(CVMX_GMXX_PRTX_CFG + (INDEX(FIX_IPD_OUTPORT), + INTERFACE(FIX_IPD_OUTPORT))); + gmx_cfg.s.en = 1; + cvmx_write_csr(CVMX_GMXX_PRTX_CFG + (INDEX(FIX_IPD_OUTPORT), + INTERFACE(FIX_IPD_OUTPORT)), gmx_cfg.u64); + cvmx_write_csr(CVMX_ASXX_TX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT)), + 1 << INDEX(FIX_IPD_OUTPORT)); + cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT)), + 1 << INDEX(FIX_IPD_OUTPORT)); + + mtu = + cvmx_read_csr(CVMX_GMXX_RXX_JABBER + (INDEX(FIX_IPD_OUTPORT), + INTERFACE(FIX_IPD_OUTPORT))); + cvmx_write_csr(CVMX_GMXX_RXX_JABBER + (INDEX(FIX_IPD_OUTPORT), + INTERFACE(FIX_IPD_OUTPORT)), 65392 - 14 - 4); + cvmx_write_csr(CVMX_GMXX_RXX_FRM_MAX + (INDEX(FIX_IPD_OUTPORT), + INTERFACE(FIX_IPD_OUTPORT)), 65392 - 14 - 4); + + cvmx_pko_send_packet_prepare(FIX_IPD_OUTPORT, + cvmx_pko_get_base_queue + (FIX_IPD_OUTPORT), + CVMX_PKO_LOCK_CMD_QUEUE); + cvmx_pko_send_packet_finish(FIX_IPD_OUTPORT, + cvmx_pko_get_base_queue + (FIX_IPD_OUTPORT), pko_command, + g_buffer, CVMX_PKO_LOCK_CMD_QUEUE); + + CVMX_SYNC; + + do { + work = cvmx_pow_work_request_sync(CVMX_POW_WAIT); + retry_cnt--; + } while ((work == NULL) && (retry_cnt > 0)); + + if (!retry_cnt) + cvmx_dprintf("WARNING: FIX_IPD_PTR_ALIGNMENT " + "get_work() timeout occured.\n"); + + /* Free packet */ + if (work) + cvmx_helper_free_packet_data(work); + } + +fix_ipd_exit: + + /* Return CSR configs to saved values */ + cvmx_write_csr(CVMX_GMXX_PRTX_CFG + (INDEX(FIX_IPD_OUTPORT), INTERFACE(FIX_IPD_OUTPORT)), + prtx_cfg); + cvmx_write_csr(CVMX_ASXX_TX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT)), + tx_ptr_en); + cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT)), + rx_ptr_en); + cvmx_write_csr(CVMX_GMXX_RXX_JABBER + (INDEX(FIX_IPD_OUTPORT), INTERFACE(FIX_IPD_OUTPORT)), + rxx_jabber); + cvmx_write_csr(CVMX_GMXX_RXX_FRM_MAX + (INDEX(FIX_IPD_OUTPORT), INTERFACE(FIX_IPD_OUTPORT)), + frame_max); + cvmx_write_csr(CVMX_ASXX_PRT_LOOP(INTERFACE(FIX_IPD_OUTPORT)), 0); + /* Set link to down so autonegotiation will set it up again */ + link_info.u64 = 0; + cvmx_helper_link_set(FIX_IPD_OUTPORT, link_info); + + /* + * Bring the link back up as autonegotiation is not done in + * user applications. + */ + cvmx_helper_link_autoconf(FIX_IPD_OUTPORT); + + CVMX_SYNC; + if (num_segs) + cvmx_dprintf("WARNING: FIX_IPD_PTR_ALIGNMENT failed.\n"); + + return !!num_segs; + +} + +/** + * Called after all internal packet IO paths are setup. This + * function enables IPD/PIP and begins packet input and output. + * + * Returns Zero on success, negative on failure + */ +int cvmx_helper_ipd_and_packet_input_enable(void) +{ + int num_interfaces; + int interface; + + /* Enable IPD */ + cvmx_ipd_enable(); + + /* + * Time to enable hardware ports packet input and output. Note + * that at this point IPD/PIP must be fully functional and PKO + * must be disabled + */ + num_interfaces = cvmx_helper_get_number_of_interfaces(); + for (interface = 0; interface < num_interfaces; interface++) { + if (cvmx_helper_ports_on_interface(interface) > 0) + __cvmx_helper_packet_hardware_enable(interface); + } + + /* Finally enable PKO now that the entire path is up and running */ + cvmx_pko_enable(); + + if ((OCTEON_IS_MODEL(OCTEON_CN31XX_PASS1) + || OCTEON_IS_MODEL(OCTEON_CN30XX_PASS1)) + && (cvmx_sysinfo_get()->board_type != CVMX_BOARD_TYPE_SIM)) + __cvmx_helper_errata_fix_ipd_ptr_alignment(); + return 0; +} + +/** + * Initialize the PIP, IPD, and PKO hardware to support + * simple priority based queues for the ethernet ports. Each + * port is configured with a number of priority queues based + * on CVMX_PKO_QUEUES_PER_PORT_* where each queue is lower + * priority than the previous. + * + * Returns Zero on success, non-zero on failure + */ +int cvmx_helper_initialize_packet_io_global(void) +{ + int result = 0; + int interface; + union cvmx_l2c_cfg l2c_cfg; + union cvmx_smix_en smix_en; + const int num_interfaces = cvmx_helper_get_number_of_interfaces(); + + /* + * CN52XX pass 1: Due to a bug in 2nd order CDR, it needs to + * be disabled. + */ + if (OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_0)) + __cvmx_helper_errata_qlm_disable_2nd_order_cdr(1); + + /* + * Tell L2 to give the IOB statically higher priority compared + * to the cores. This avoids conditions where IO blocks might + * be starved under very high L2 loads. + */ + l2c_cfg.u64 = cvmx_read_csr(CVMX_L2C_CFG); + l2c_cfg.s.lrf_arb_mode = 0; + l2c_cfg.s.rfb_arb_mode = 0; + cvmx_write_csr(CVMX_L2C_CFG, l2c_cfg.u64); + + /* Make sure SMI/MDIO is enabled so we can query PHYs */ + smix_en.u64 = cvmx_read_csr(CVMX_SMIX_EN(0)); + if (!smix_en.s.en) { + smix_en.s.en = 1; + cvmx_write_csr(CVMX_SMIX_EN(0), smix_en.u64); + } + + /* Newer chips actually have two SMI/MDIO interfaces */ + if (!OCTEON_IS_MODEL(OCTEON_CN3XXX) && + !OCTEON_IS_MODEL(OCTEON_CN58XX) && + !OCTEON_IS_MODEL(OCTEON_CN50XX)) { + smix_en.u64 = cvmx_read_csr(CVMX_SMIX_EN(1)); + if (!smix_en.s.en) { + smix_en.s.en = 1; + cvmx_write_csr(CVMX_SMIX_EN(1), smix_en.u64); + } + } + + cvmx_pko_initialize_global(); + for (interface = 0; interface < num_interfaces; interface++) { + result |= cvmx_helper_interface_probe(interface); + if (cvmx_helper_ports_on_interface(interface) > 0) + cvmx_dprintf("Interface %d has %d ports (%s)\n", + interface, + cvmx_helper_ports_on_interface(interface), + cvmx_helper_interface_mode_to_string + (cvmx_helper_interface_get_mode + (interface))); + result |= __cvmx_helper_interface_setup_ipd(interface); + result |= __cvmx_helper_interface_setup_pko(interface); + } + + result |= __cvmx_helper_global_setup_ipd(); + result |= __cvmx_helper_global_setup_pko(); + + /* Enable any flow control and backpressure */ + result |= __cvmx_helper_global_setup_backpressure(); + +#if CVMX_HELPER_ENABLE_IPD + result |= cvmx_helper_ipd_and_packet_input_enable(); +#endif + return result; +} + +/** + * Does core local initialization for packet io + * + * Returns Zero on success, non-zero on failure + */ +int cvmx_helper_initialize_packet_io_local(void) +{ + return cvmx_pko_initialize_local(); +} + +/** + * Auto configure an IPD/PKO port link state and speed. This + * function basically does the equivalent of: + * cvmx_helper_link_set(ipd_port, cvmx_helper_link_get(ipd_port)); + * + * @ipd_port: IPD/PKO port to auto configure + * + * Returns Link state after configure + */ +cvmx_helper_link_info_t cvmx_helper_link_autoconf(int ipd_port) +{ + cvmx_helper_link_info_t link_info; + int interface = cvmx_helper_get_interface_num(ipd_port); + int index = cvmx_helper_get_interface_index_num(ipd_port); + + if (index >= cvmx_helper_ports_on_interface(interface)) { + link_info.u64 = 0; + return link_info; + } + + link_info = cvmx_helper_link_get(ipd_port); + if (link_info.u64 == port_link_info[ipd_port].u64) + return link_info; + + /* If we fail to set the link speed, port_link_info will not change */ + cvmx_helper_link_set(ipd_port, link_info); + + /* + * port_link_info should be the current value, which will be + * different than expect if cvmx_helper_link_set() failed. + */ + return port_link_info[ipd_port]; +} + +/** + * Return the link state of an IPD/PKO port as returned by + * auto negotiation. The result of this function may not match + * Octeon's link config if auto negotiation has changed since + * the last call to cvmx_helper_link_set(). + * + * @ipd_port: IPD/PKO port to query + * + * Returns Link state + */ +cvmx_helper_link_info_t cvmx_helper_link_get(int ipd_port) +{ + cvmx_helper_link_info_t result; + int interface = cvmx_helper_get_interface_num(ipd_port); + int index = cvmx_helper_get_interface_index_num(ipd_port); + + /* The default result will be a down link unless the code below + changes it */ + result.u64 = 0; + + if (index >= cvmx_helper_ports_on_interface(interface)) + return result; + + switch (cvmx_helper_interface_get_mode(interface)) { + case CVMX_HELPER_INTERFACE_MODE_DISABLED: + case CVMX_HELPER_INTERFACE_MODE_PCIE: + /* Network links are not supported */ + break; + case CVMX_HELPER_INTERFACE_MODE_XAUI: + result = __cvmx_helper_xaui_link_get(ipd_port); + break; + case CVMX_HELPER_INTERFACE_MODE_GMII: + if (index == 0) + result = __cvmx_helper_rgmii_link_get(ipd_port); + else { + result.s.full_duplex = 1; + result.s.link_up = 1; + result.s.speed = 1000; + } + break; + case CVMX_HELPER_INTERFACE_MODE_RGMII: + result = __cvmx_helper_rgmii_link_get(ipd_port); + break; + case CVMX_HELPER_INTERFACE_MODE_SPI: + result = __cvmx_helper_spi_link_get(ipd_port); + break; + case CVMX_HELPER_INTERFACE_MODE_SGMII: + case CVMX_HELPER_INTERFACE_MODE_PICMG: + result = __cvmx_helper_sgmii_link_get(ipd_port); + break; + case CVMX_HELPER_INTERFACE_MODE_NPI: + case CVMX_HELPER_INTERFACE_MODE_LOOP: + /* Network links are not supported */ + break; + } + return result; +} + +/** + * Configure an IPD/PKO port for the specified link state. This + * function does not influence auto negotiation at the PHY level. + * The passed link state must always match the link state returned + * by cvmx_helper_link_get(). It is normally best to use + * cvmx_helper_link_autoconf() instead. + * + * @ipd_port: IPD/PKO port to configure + * @link_info: The new link state + * + * Returns Zero on success, negative on failure + */ +int cvmx_helper_link_set(int ipd_port, cvmx_helper_link_info_t link_info) +{ + int result = -1; + int interface = cvmx_helper_get_interface_num(ipd_port); + int index = cvmx_helper_get_interface_index_num(ipd_port); + + if (index >= cvmx_helper_ports_on_interface(interface)) + return -1; + + switch (cvmx_helper_interface_get_mode(interface)) { + case CVMX_HELPER_INTERFACE_MODE_DISABLED: + case CVMX_HELPER_INTERFACE_MODE_PCIE: + break; + case CVMX_HELPER_INTERFACE_MODE_XAUI: + result = __cvmx_helper_xaui_link_set(ipd_port, link_info); + break; + /* + * RGMII/GMII/MII are all treated about the same. Most + * functions refer to these ports as RGMII. + */ + case CVMX_HELPER_INTERFACE_MODE_RGMII: + case CVMX_HELPER_INTERFACE_MODE_GMII: + result = __cvmx_helper_rgmii_link_set(ipd_port, link_info); + break; + case CVMX_HELPER_INTERFACE_MODE_SPI: + result = __cvmx_helper_spi_link_set(ipd_port, link_info); + break; + case CVMX_HELPER_INTERFACE_MODE_SGMII: + case CVMX_HELPER_INTERFACE_MODE_PICMG: + result = __cvmx_helper_sgmii_link_set(ipd_port, link_info); + break; + case CVMX_HELPER_INTERFACE_MODE_NPI: + case CVMX_HELPER_INTERFACE_MODE_LOOP: + break; + } + /* Set the port_link_info here so that the link status is updated + no matter how cvmx_helper_link_set is called. We don't change + the value if link_set failed */ + if (result == 0) + port_link_info[ipd_port].u64 = link_info.u64; + return result; +} + +/** + * Configure a port for internal and/or external loopback. Internal loopback + * causes packets sent by the port to be received by Octeon. External loopback + * causes packets received from the wire to sent out again. + * + * @ipd_port: IPD/PKO port to loopback. + * @enable_internal: + * Non zero if you want internal loopback + * @enable_external: + * Non zero if you want external loopback + * + * Returns Zero on success, negative on failure. + */ +int cvmx_helper_configure_loopback(int ipd_port, int enable_internal, + int enable_external) +{ + int result = -1; + int interface = cvmx_helper_get_interface_num(ipd_port); + int index = cvmx_helper_get_interface_index_num(ipd_port); + + if (index >= cvmx_helper_ports_on_interface(interface)) + return -1; + + switch (cvmx_helper_interface_get_mode(interface)) { + case CVMX_HELPER_INTERFACE_MODE_DISABLED: + case CVMX_HELPER_INTERFACE_MODE_PCIE: + case CVMX_HELPER_INTERFACE_MODE_SPI: + case CVMX_HELPER_INTERFACE_MODE_NPI: + case CVMX_HELPER_INTERFACE_MODE_LOOP: + break; + case CVMX_HELPER_INTERFACE_MODE_XAUI: + result = + __cvmx_helper_xaui_configure_loopback(ipd_port, + enable_internal, + enable_external); + break; + case CVMX_HELPER_INTERFACE_MODE_RGMII: + case CVMX_HELPER_INTERFACE_MODE_GMII: + result = + __cvmx_helper_rgmii_configure_loopback(ipd_port, + enable_internal, + enable_external); + break; + case CVMX_HELPER_INTERFACE_MODE_SGMII: + case CVMX_HELPER_INTERFACE_MODE_PICMG: + result = + __cvmx_helper_sgmii_configure_loopback(ipd_port, + enable_internal, + enable_external); + break; + } + return result; +} diff --git a/drivers/staging/octeon/cvmx-helper.h b/drivers/staging/octeon/cvmx-helper.h new file mode 100644 index 0000000..51916f3 --- /dev/null +++ b/drivers/staging/octeon/cvmx-helper.h @@ -0,0 +1,227 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * along with this file; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +/* + * + * Helper functions for common, but complicated tasks. + * + */ + +#ifndef __CVMX_HELPER_H__ +#define __CVMX_HELPER_H__ + +#include "cvmx-config.h" +#include "cvmx-fpa.h" +#include "cvmx-wqe.h" + +typedef enum { + CVMX_HELPER_INTERFACE_MODE_DISABLED, + CVMX_HELPER_INTERFACE_MODE_RGMII, + CVMX_HELPER_INTERFACE_MODE_GMII, + CVMX_HELPER_INTERFACE_MODE_SPI, + CVMX_HELPER_INTERFACE_MODE_PCIE, + CVMX_HELPER_INTERFACE_MODE_XAUI, + CVMX_HELPER_INTERFACE_MODE_SGMII, + CVMX_HELPER_INTERFACE_MODE_PICMG, + CVMX_HELPER_INTERFACE_MODE_NPI, + CVMX_HELPER_INTERFACE_MODE_LOOP, +} cvmx_helper_interface_mode_t; + +typedef union { + uint64_t u64; + struct { + uint64_t reserved_20_63:44; + uint64_t link_up:1; /**< Is the physical link up? */ + uint64_t full_duplex:1; /**< 1 if the link is full duplex */ + uint64_t speed:18; /**< Speed of the link in Mbps */ + } s; +} cvmx_helper_link_info_t; + +#include "cvmx-helper-fpa.h" + +#include +#include "cvmx-helper-loop.h" +#include "cvmx-helper-npi.h" +#include "cvmx-helper-rgmii.h" +#include "cvmx-helper-sgmii.h" +#include "cvmx-helper-spi.h" +#include "cvmx-helper-util.h" +#include "cvmx-helper-xaui.h" + +/** + * cvmx_override_pko_queue_priority(int ipd_port, uint64_t + * priorities[16]) is a function pointer. It is meant to allow + * customization of the PKO queue priorities based on the port + * number. Users should set this pointer to a function before + * calling any cvmx-helper operations. + */ +extern void (*cvmx_override_pko_queue_priority) (int pko_port, + uint64_t priorities[16]); + +/** + * cvmx_override_ipd_port_setup(int ipd_port) is a function + * pointer. It is meant to allow customization of the IPD port + * setup before packet input/output comes online. It is called + * after cvmx-helper does the default IPD configuration, but + * before IPD is enabled. Users should set this pointer to a + * function before calling any cvmx-helper operations. + */ +extern void (*cvmx_override_ipd_port_setup) (int ipd_port); + +/** + * This function enables the IPD and also enables the packet interfaces. + * The packet interfaces (RGMII and SPI) must be enabled after the + * IPD. This should be called by the user program after any additional + * IPD configuration changes are made if CVMX_HELPER_ENABLE_IPD + * is not set in the executive-config.h file. + * + * Returns 0 on success + * -1 on failure + */ +extern int cvmx_helper_ipd_and_packet_input_enable(void); + +/** + * Initialize the PIP, IPD, and PKO hardware to support + * simple priority based queues for the ethernet ports. Each + * port is configured with a number of priority queues based + * on CVMX_PKO_QUEUES_PER_PORT_* where each queue is lower + * priority than the previous. + * + * Returns Zero on success, non-zero on failure + */ +extern int cvmx_helper_initialize_packet_io_global(void); + +/** + * Does core local initialization for packet io + * + * Returns Zero on success, non-zero on failure + */ +extern int cvmx_helper_initialize_packet_io_local(void); + +/** + * Returns the number of ports on the given interface. + * The interface must be initialized before the port count + * can be returned. + * + * @interface: Which interface to return port count for. + * + * Returns Port count for interface + * -1 for uninitialized interface + */ +extern int cvmx_helper_ports_on_interface(int interface); + +/** + * Return the number of interfaces the chip has. Each interface + * may have multiple ports. Most chips support two interfaces, + * but the CNX0XX and CNX1XX are exceptions. These only support + * one interface. + * + * Returns Number of interfaces on chip + */ +extern int cvmx_helper_get_number_of_interfaces(void); + +/** + * Get the operating mode of an interface. Depending on the Octeon + * chip and configuration, this function returns an enumeration + * of the type of packet I/O supported by an interface. + * + * @interface: Interface to probe + * + * Returns Mode of the interface. Unknown or unsupported interfaces return + * DISABLED. + */ +extern cvmx_helper_interface_mode_t cvmx_helper_interface_get_mode(int + interface); + +/** + * Auto configure an IPD/PKO port link state and speed. This + * function basically does the equivalent of: + * cvmx_helper_link_set(ipd_port, cvmx_helper_link_get(ipd_port)); + * + * @ipd_port: IPD/PKO port to auto configure + * + * Returns Link state after configure + */ +extern cvmx_helper_link_info_t cvmx_helper_link_autoconf(int ipd_port); + +/** + * Return the link state of an IPD/PKO port as returned by + * auto negotiation. The result of this function may not match + * Octeon's link config if auto negotiation has changed since + * the last call to cvmx_helper_link_set(). + * + * @ipd_port: IPD/PKO port to query + * + * Returns Link state + */ +extern cvmx_helper_link_info_t cvmx_helper_link_get(int ipd_port); + +/** + * Configure an IPD/PKO port for the specified link state. This + * function does not influence auto negotiation at the PHY level. + * The passed link state must always match the link state returned + * by cvmx_helper_link_get(). It is normally best to use + * cvmx_helper_link_autoconf() instead. + * + * @ipd_port: IPD/PKO port to configure + * @link_info: The new link state + * + * Returns Zero on success, negative on failure + */ +extern int cvmx_helper_link_set(int ipd_port, + cvmx_helper_link_info_t link_info); + +/** + * This function probes an interface to determine the actual + * number of hardware ports connected to it. It doesn't setup the + * ports or enable them. The main goal here is to set the global + * interface_port_count[interface] correctly. Hardware setup of the + * ports will be performed later. + * + * @interface: Interface to probe + * + * Returns Zero on success, negative on failure + */ +extern int cvmx_helper_interface_probe(int interface); + +/** + * Configure a port for internal and/or external loopback. Internal loopback + * causes packets sent by the port to be received by Octeon. External loopback + * causes packets received from the wire to sent out again. + * + * @ipd_port: IPD/PKO port to loopback. + * @enable_internal: + * Non zero if you want internal loopback + * @enable_external: + * Non zero if you want external loopback + * + * Returns Zero on success, negative on failure. + */ +extern int cvmx_helper_configure_loopback(int ipd_port, int enable_internal, + int enable_external); + +#endif /* __CVMX_HELPER_H__ */ diff --git a/drivers/staging/octeon/cvmx-interrupt-decodes.c b/drivers/staging/octeon/cvmx-interrupt-decodes.c new file mode 100644 index 0000000..a3337e3 --- /dev/null +++ b/drivers/staging/octeon/cvmx-interrupt-decodes.c @@ -0,0 +1,371 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2009 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * along with this file; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +/* + * + * Automatically generated functions useful for enabling + * and decoding RSL_INT_BLOCKS interrupts. + * + */ + +#include + +#include "cvmx-gmxx-defs.h" +#include "cvmx-pcsx-defs.h" +#include "cvmx-pcsxx-defs.h" +#include "cvmx-spxx-defs.h" +#include "cvmx-stxx-defs.h" + +#ifndef PRINT_ERROR +#define PRINT_ERROR(format, ...) +#endif + + +/** + * __cvmx_interrupt_gmxx_rxx_int_en_enable enables all interrupt bits in cvmx_gmxx_rxx_int_en_t + */ +void __cvmx_interrupt_gmxx_rxx_int_en_enable(int index, int block) +{ + union cvmx_gmxx_rxx_int_en gmx_rx_int_en; + cvmx_write_csr(CVMX_GMXX_RXX_INT_REG(index, block), + cvmx_read_csr(CVMX_GMXX_RXX_INT_REG(index, block))); + gmx_rx_int_en.u64 = 0; + if (OCTEON_IS_MODEL(OCTEON_CN56XX)) { + /* Skipping gmx_rx_int_en.s.reserved_29_63 */ + gmx_rx_int_en.s.hg2cc = 1; + gmx_rx_int_en.s.hg2fld = 1; + gmx_rx_int_en.s.undat = 1; + gmx_rx_int_en.s.uneop = 1; + gmx_rx_int_en.s.unsop = 1; + gmx_rx_int_en.s.bad_term = 1; + gmx_rx_int_en.s.bad_seq = 1; + gmx_rx_int_en.s.rem_fault = 1; + gmx_rx_int_en.s.loc_fault = 1; + gmx_rx_int_en.s.pause_drp = 1; + /* Skipping gmx_rx_int_en.s.reserved_16_18 */ + /*gmx_rx_int_en.s.ifgerr = 1; */ + /*gmx_rx_int_en.s.coldet = 1; // Collsion detect */ + /*gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime */ + /*gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes */ + /*gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol */ + gmx_rx_int_en.s.ovrerr = 1; + /* Skipping gmx_rx_int_en.s.reserved_9_9 */ + gmx_rx_int_en.s.skperr = 1; + gmx_rx_int_en.s.rcverr = 1; + /* Skipping gmx_rx_int_en.s.reserved_5_6 */ + /*gmx_rx_int_en.s.fcserr = 1; // FCS errors are handled when we get work */ + gmx_rx_int_en.s.jabber = 1; + /* Skipping gmx_rx_int_en.s.reserved_2_2 */ + gmx_rx_int_en.s.carext = 1; + /* Skipping gmx_rx_int_en.s.reserved_0_0 */ + } + if (OCTEON_IS_MODEL(OCTEON_CN30XX)) { + /* Skipping gmx_rx_int_en.s.reserved_19_63 */ + /*gmx_rx_int_en.s.phy_dupx = 1; */ + /*gmx_rx_int_en.s.phy_spd = 1; */ + /*gmx_rx_int_en.s.phy_link = 1; */ + /*gmx_rx_int_en.s.ifgerr = 1; */ + /*gmx_rx_int_en.s.coldet = 1; // Collsion detect */ + /*gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime */ + /*gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes */ + /*gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol */ + gmx_rx_int_en.s.ovrerr = 1; + gmx_rx_int_en.s.niberr = 1; + gmx_rx_int_en.s.skperr = 1; + gmx_rx_int_en.s.rcverr = 1; + /*gmx_rx_int_en.s.lenerr = 1; // Length errors are handled when we get work */ + gmx_rx_int_en.s.alnerr = 1; + /*gmx_rx_int_en.s.fcserr = 1; // FCS errors are handled when we get work */ + gmx_rx_int_en.s.jabber = 1; + gmx_rx_int_en.s.maxerr = 1; + gmx_rx_int_en.s.carext = 1; + gmx_rx_int_en.s.minerr = 1; + } + if (OCTEON_IS_MODEL(OCTEON_CN50XX)) { + /* Skipping gmx_rx_int_en.s.reserved_20_63 */ + gmx_rx_int_en.s.pause_drp = 1; + /*gmx_rx_int_en.s.phy_dupx = 1; */ + /*gmx_rx_int_en.s.phy_spd = 1; */ + /*gmx_rx_int_en.s.phy_link = 1; */ + /*gmx_rx_int_en.s.ifgerr = 1; */ + /*gmx_rx_int_en.s.coldet = 1; // Collsion detect */ + /*gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime */ + /*gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes */ + /*gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol */ + gmx_rx_int_en.s.ovrerr = 1; + gmx_rx_int_en.s.niberr = 1; + gmx_rx_int_en.s.skperr = 1; + gmx_rx_int_en.s.rcverr = 1; + /* Skipping gmx_rx_int_en.s.reserved_6_6 */ + gmx_rx_int_en.s.alnerr = 1; + /*gmx_rx_int_en.s.fcserr = 1; // FCS errors are handled when we get work */ + gmx_rx_int_en.s.jabber = 1; + /* Skipping gmx_rx_int_en.s.reserved_2_2 */ + gmx_rx_int_en.s.carext = 1; + /* Skipping gmx_rx_int_en.s.reserved_0_0 */ + } + if (OCTEON_IS_MODEL(OCTEON_CN38XX)) { + /* Skipping gmx_rx_int_en.s.reserved_19_63 */ + /*gmx_rx_int_en.s.phy_dupx = 1; */ + /*gmx_rx_int_en.s.phy_spd = 1; */ + /*gmx_rx_int_en.s.phy_link = 1; */ + /*gmx_rx_int_en.s.ifgerr = 1; */ + /*gmx_rx_int_en.s.coldet = 1; // Collsion detect */ + /*gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime */ + /*gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes */ + /*gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol */ + gmx_rx_int_en.s.ovrerr = 1; + gmx_rx_int_en.s.niberr = 1; + gmx_rx_int_en.s.skperr = 1; + gmx_rx_int_en.s.rcverr = 1; + /*gmx_rx_int_en.s.lenerr = 1; // Length errors are handled when we get work */ + gmx_rx_int_en.s.alnerr = 1; + /*gmx_rx_int_en.s.fcserr = 1; // FCS errors are handled when we get work */ + gmx_rx_int_en.s.jabber = 1; + gmx_rx_int_en.s.maxerr = 1; + gmx_rx_int_en.s.carext = 1; + gmx_rx_int_en.s.minerr = 1; + } + if (OCTEON_IS_MODEL(OCTEON_CN31XX)) { + /* Skipping gmx_rx_int_en.s.reserved_19_63 */ + /*gmx_rx_int_en.s.phy_dupx = 1; */ + /*gmx_rx_int_en.s.phy_spd = 1; */ + /*gmx_rx_int_en.s.phy_link = 1; */ + /*gmx_rx_int_en.s.ifgerr = 1; */ + /*gmx_rx_int_en.s.coldet = 1; // Collsion detect */ + /*gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime */ + /*gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes */ + /*gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol */ + gmx_rx_int_en.s.ovrerr = 1; + gmx_rx_int_en.s.niberr = 1; + gmx_rx_int_en.s.skperr = 1; + gmx_rx_int_en.s.rcverr = 1; + /*gmx_rx_int_en.s.lenerr = 1; // Length errors are handled when we get work */ + gmx_rx_int_en.s.alnerr = 1; + /*gmx_rx_int_en.s.fcserr = 1; // FCS errors are handled when we get work */ + gmx_rx_int_en.s.jabber = 1; + gmx_rx_int_en.s.maxerr = 1; + gmx_rx_int_en.s.carext = 1; + gmx_rx_int_en.s.minerr = 1; + } + if (OCTEON_IS_MODEL(OCTEON_CN58XX)) { + /* Skipping gmx_rx_int_en.s.reserved_20_63 */ + gmx_rx_int_en.s.pause_drp = 1; + /*gmx_rx_int_en.s.phy_dupx = 1; */ + /*gmx_rx_int_en.s.phy_spd = 1; */ + /*gmx_rx_int_en.s.phy_link = 1; */ + /*gmx_rx_int_en.s.ifgerr = 1; */ + /*gmx_rx_int_en.s.coldet = 1; // Collsion detect */ + /*gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime */ + /*gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes */ + /*gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol */ + gmx_rx_int_en.s.ovrerr = 1; + gmx_rx_int_en.s.niberr = 1; + gmx_rx_int_en.s.skperr = 1; + gmx_rx_int_en.s.rcverr = 1; + /*gmx_rx_int_en.s.lenerr = 1; // Length errors are handled when we get work */ + gmx_rx_int_en.s.alnerr = 1; + /*gmx_rx_int_en.s.fcserr = 1; // FCS errors are handled when we get work */ + gmx_rx_int_en.s.jabber = 1; + gmx_rx_int_en.s.maxerr = 1; + gmx_rx_int_en.s.carext = 1; + gmx_rx_int_en.s.minerr = 1; + } + if (OCTEON_IS_MODEL(OCTEON_CN52XX)) { + /* Skipping gmx_rx_int_en.s.reserved_29_63 */ + gmx_rx_int_en.s.hg2cc = 1; + gmx_rx_int_en.s.hg2fld = 1; + gmx_rx_int_en.s.undat = 1; + gmx_rx_int_en.s.uneop = 1; + gmx_rx_int_en.s.unsop = 1; + gmx_rx_int_en.s.bad_term = 1; + gmx_rx_int_en.s.bad_seq = 0; + gmx_rx_int_en.s.rem_fault = 1; + gmx_rx_int_en.s.loc_fault = 0; + gmx_rx_int_en.s.pause_drp = 1; + /* Skipping gmx_rx_int_en.s.reserved_16_18 */ + /*gmx_rx_int_en.s.ifgerr = 1; */ + /*gmx_rx_int_en.s.coldet = 1; // Collsion detect */ + /*gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime */ + /*gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes */ + /*gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol */ + gmx_rx_int_en.s.ovrerr = 1; + /* Skipping gmx_rx_int_en.s.reserved_9_9 */ + gmx_rx_int_en.s.skperr = 1; + gmx_rx_int_en.s.rcverr = 1; + /* Skipping gmx_rx_int_en.s.reserved_5_6 */ + /*gmx_rx_int_en.s.fcserr = 1; // FCS errors are handled when we get work */ + gmx_rx_int_en.s.jabber = 1; + /* Skipping gmx_rx_int_en.s.reserved_2_2 */ + gmx_rx_int_en.s.carext = 1; + /* Skipping gmx_rx_int_en.s.reserved_0_0 */ + } + cvmx_write_csr(CVMX_GMXX_RXX_INT_EN(index, block), gmx_rx_int_en.u64); +} +/** + * __cvmx_interrupt_pcsx_intx_en_reg_enable enables all interrupt bits in cvmx_pcsx_intx_en_reg_t + */ +void __cvmx_interrupt_pcsx_intx_en_reg_enable(int index, int block) +{ + union cvmx_pcsx_intx_en_reg pcs_int_en_reg; + cvmx_write_csr(CVMX_PCSX_INTX_REG(index, block), + cvmx_read_csr(CVMX_PCSX_INTX_REG(index, block))); + pcs_int_en_reg.u64 = 0; + if (OCTEON_IS_MODEL(OCTEON_CN56XX)) { + /* Skipping pcs_int_en_reg.s.reserved_12_63 */ + /*pcs_int_en_reg.s.dup = 1; // This happens during normal operation */ + pcs_int_en_reg.s.sync_bad_en = 1; + pcs_int_en_reg.s.an_bad_en = 1; + pcs_int_en_reg.s.rxlock_en = 1; + pcs_int_en_reg.s.rxbad_en = 1; + /*pcs_int_en_reg.s.rxerr_en = 1; // This happens during normal operation */ + pcs_int_en_reg.s.txbad_en = 1; + pcs_int_en_reg.s.txfifo_en = 1; + pcs_int_en_reg.s.txfifu_en = 1; + pcs_int_en_reg.s.an_err_en = 1; + /*pcs_int_en_reg.s.xmit_en = 1; // This happens during normal operation */ + /*pcs_int_en_reg.s.lnkspd_en = 1; // This happens during normal operation */ + } + if (OCTEON_IS_MODEL(OCTEON_CN52XX)) { + /* Skipping pcs_int_en_reg.s.reserved_12_63 */ + /*pcs_int_en_reg.s.dup = 1; // This happens during normal operation */ + pcs_int_en_reg.s.sync_bad_en = 1; + pcs_int_en_reg.s.an_bad_en = 1; + pcs_int_en_reg.s.rxlock_en = 1; + pcs_int_en_reg.s.rxbad_en = 1; + /*pcs_int_en_reg.s.rxerr_en = 1; // This happens during normal operation */ + pcs_int_en_reg.s.txbad_en = 1; + pcs_int_en_reg.s.txfifo_en = 1; + pcs_int_en_reg.s.txfifu_en = 1; + pcs_int_en_reg.s.an_err_en = 1; + /*pcs_int_en_reg.s.xmit_en = 1; // This happens during normal operation */ + /*pcs_int_en_reg.s.lnkspd_en = 1; // This happens during normal operation */ + } + cvmx_write_csr(CVMX_PCSX_INTX_EN_REG(index, block), pcs_int_en_reg.u64); +} +/** + * __cvmx_interrupt_pcsxx_int_en_reg_enable enables all interrupt bits in cvmx_pcsxx_int_en_reg_t + */ +void __cvmx_interrupt_pcsxx_int_en_reg_enable(int index) +{ + union cvmx_pcsxx_int_en_reg pcsx_int_en_reg; + cvmx_write_csr(CVMX_PCSXX_INT_REG(index), + cvmx_read_csr(CVMX_PCSXX_INT_REG(index))); + pcsx_int_en_reg.u64 = 0; + if (OCTEON_IS_MODEL(OCTEON_CN56XX)) { + /* Skipping pcsx_int_en_reg.s.reserved_6_63 */ + pcsx_int_en_reg.s.algnlos_en = 1; + pcsx_int_en_reg.s.synlos_en = 1; + pcsx_int_en_reg.s.bitlckls_en = 1; + pcsx_int_en_reg.s.rxsynbad_en = 1; + pcsx_int_en_reg.s.rxbad_en = 1; + pcsx_int_en_reg.s.txflt_en = 1; + } + if (OCTEON_IS_MODEL(OCTEON_CN52XX)) { + /* Skipping pcsx_int_en_reg.s.reserved_6_63 */ + pcsx_int_en_reg.s.algnlos_en = 1; + pcsx_int_en_reg.s.synlos_en = 1; + pcsx_int_en_reg.s.bitlckls_en = 0; /* Happens if XAUI module is not installed */ + pcsx_int_en_reg.s.rxsynbad_en = 1; + pcsx_int_en_reg.s.rxbad_en = 1; + pcsx_int_en_reg.s.txflt_en = 1; + } + cvmx_write_csr(CVMX_PCSXX_INT_EN_REG(index), pcsx_int_en_reg.u64); +} + +/** + * __cvmx_interrupt_spxx_int_msk_enable enables all interrupt bits in cvmx_spxx_int_msk_t + */ +void __cvmx_interrupt_spxx_int_msk_enable(int index) +{ + union cvmx_spxx_int_msk spx_int_msk; + cvmx_write_csr(CVMX_SPXX_INT_REG(index), + cvmx_read_csr(CVMX_SPXX_INT_REG(index))); + spx_int_msk.u64 = 0; + if (OCTEON_IS_MODEL(OCTEON_CN38XX)) { + /* Skipping spx_int_msk.s.reserved_12_63 */ + spx_int_msk.s.calerr = 1; + spx_int_msk.s.syncerr = 1; + spx_int_msk.s.diperr = 1; + spx_int_msk.s.tpaovr = 1; + spx_int_msk.s.rsverr = 1; + spx_int_msk.s.drwnng = 1; + spx_int_msk.s.clserr = 1; + spx_int_msk.s.spiovr = 1; + /* Skipping spx_int_msk.s.reserved_2_3 */ + spx_int_msk.s.abnorm = 1; + spx_int_msk.s.prtnxa = 1; + } + if (OCTEON_IS_MODEL(OCTEON_CN58XX)) { + /* Skipping spx_int_msk.s.reserved_12_63 */ + spx_int_msk.s.calerr = 1; + spx_int_msk.s.syncerr = 1; + spx_int_msk.s.diperr = 1; + spx_int_msk.s.tpaovr = 1; + spx_int_msk.s.rsverr = 1; + spx_int_msk.s.drwnng = 1; + spx_int_msk.s.clserr = 1; + spx_int_msk.s.spiovr = 1; + /* Skipping spx_int_msk.s.reserved_2_3 */ + spx_int_msk.s.abnorm = 1; + spx_int_msk.s.prtnxa = 1; + } + cvmx_write_csr(CVMX_SPXX_INT_MSK(index), spx_int_msk.u64); +} +/** + * __cvmx_interrupt_stxx_int_msk_enable enables all interrupt bits in cvmx_stxx_int_msk_t + */ +void __cvmx_interrupt_stxx_int_msk_enable(int index) +{ + union cvmx_stxx_int_msk stx_int_msk; + cvmx_write_csr(CVMX_STXX_INT_REG(index), + cvmx_read_csr(CVMX_STXX_INT_REG(index))); + stx_int_msk.u64 = 0; + if (OCTEON_IS_MODEL(OCTEON_CN38XX)) { + /* Skipping stx_int_msk.s.reserved_8_63 */ + stx_int_msk.s.frmerr = 1; + stx_int_msk.s.unxfrm = 1; + stx_int_msk.s.nosync = 1; + stx_int_msk.s.diperr = 1; + stx_int_msk.s.datovr = 1; + stx_int_msk.s.ovrbst = 1; + stx_int_msk.s.calpar1 = 1; + stx_int_msk.s.calpar0 = 1; + } + if (OCTEON_IS_MODEL(OCTEON_CN58XX)) { + /* Skipping stx_int_msk.s.reserved_8_63 */ + stx_int_msk.s.frmerr = 1; + stx_int_msk.s.unxfrm = 1; + stx_int_msk.s.nosync = 1; + stx_int_msk.s.diperr = 1; + stx_int_msk.s.datovr = 1; + stx_int_msk.s.ovrbst = 1; + stx_int_msk.s.calpar1 = 1; + stx_int_msk.s.calpar0 = 1; + } + cvmx_write_csr(CVMX_STXX_INT_MSK(index), stx_int_msk.u64); +} diff --git a/drivers/staging/octeon/cvmx-interrupt-rsl.c b/drivers/staging/octeon/cvmx-interrupt-rsl.c new file mode 100644 index 0000000..df50048 --- /dev/null +++ b/drivers/staging/octeon/cvmx-interrupt-rsl.c @@ -0,0 +1,140 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * along with this file; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +/* + * Utility functions to decode Octeon's RSL_INT_BLOCKS + * interrupts into error messages. + */ + +#include + +#include "cvmx-asxx-defs.h" +#include "cvmx-gmxx-defs.h" + +#ifndef PRINT_ERROR +#define PRINT_ERROR(format, ...) +#endif + +void __cvmx_interrupt_gmxx_rxx_int_en_enable(int index, int block); + +/** + * Enable ASX error interrupts that exist on CN3XXX, CN50XX, and + * CN58XX. + * + * @block: Interface to enable 0-1 + */ +void __cvmx_interrupt_asxx_enable(int block) +{ + int mask; + union cvmx_asxx_int_en csr; + /* + * CN38XX and CN58XX have two interfaces with 4 ports per + * interface. All other chips have a max of 3 ports on + * interface 0 + */ + if (OCTEON_IS_MODEL(OCTEON_CN38XX) || OCTEON_IS_MODEL(OCTEON_CN58XX)) + mask = 0xf; /* Set enables for 4 ports */ + else + mask = 0x7; /* Set enables for 3 ports */ + + /* Enable interface interrupts */ + csr.u64 = cvmx_read_csr(CVMX_ASXX_INT_EN(block)); + csr.s.txpsh = mask; + csr.s.txpop = mask; + csr.s.ovrflw = mask; + cvmx_write_csr(CVMX_ASXX_INT_EN(block), csr.u64); +} +/** + * Enable GMX error reporting for the supplied interface + * + * @interface: Interface to enable + */ +void __cvmx_interrupt_gmxx_enable(int interface) +{ + union cvmx_gmxx_inf_mode mode; + union cvmx_gmxx_tx_int_en gmx_tx_int_en; + int num_ports; + int index; + + mode.u64 = cvmx_read_csr(CVMX_GMXX_INF_MODE(interface)); + + if (OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN52XX)) { + if (mode.s.en) { + switch (mode.cn56xx.mode) { + case 1: /* XAUI */ + num_ports = 1; + break; + case 2: /* SGMII */ + case 3: /* PICMG */ + num_ports = 4; + break; + default: /* Disabled */ + num_ports = 0; + break; + } + } else + num_ports = 0; + } else { + if (mode.s.en) { + if (OCTEON_IS_MODEL(OCTEON_CN38XX) + || OCTEON_IS_MODEL(OCTEON_CN58XX)) { + /* + * SPI on CN38XX and CN58XX report all + * errors through port 0. RGMII needs + * to check all 4 ports + */ + if (mode.s.type) + num_ports = 1; + else + num_ports = 4; + } else { + /* + * CN30XX, CN31XX, and CN50XX have two + * or three ports. GMII and MII has 2, + * RGMII has three + */ + if (mode.s.type) + num_ports = 2; + else + num_ports = 3; + } + } else + num_ports = 0; + } + + gmx_tx_int_en.u64 = 0; + if (num_ports) { + if (OCTEON_IS_MODEL(OCTEON_CN38XX) + || OCTEON_IS_MODEL(OCTEON_CN58XX)) + gmx_tx_int_en.s.ncb_nxa = 1; + gmx_tx_int_en.s.pko_nxa = 1; + } + gmx_tx_int_en.s.undflw = (1 << num_ports) - 1; + cvmx_write_csr(CVMX_GMXX_TX_INT_EN(interface), gmx_tx_int_en.u64); + for (index = 0; index < num_ports; index++) + __cvmx_interrupt_gmxx_rxx_int_en_enable(index, interface); +} diff --git a/drivers/staging/octeon/cvmx-ipd.h b/drivers/staging/octeon/cvmx-ipd.h new file mode 100644 index 0000000..115a552 --- /dev/null +++ b/drivers/staging/octeon/cvmx-ipd.h @@ -0,0 +1,338 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * along with this file; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +/** + * + * Interface to the hardware Input Packet Data unit. + */ + +#ifndef __CVMX_IPD_H__ +#define __CVMX_IPD_H__ + +#include + +#include + +enum cvmx_ipd_mode { + CVMX_IPD_OPC_MODE_STT = 0LL, /* All blocks DRAM, not cached in L2 */ + CVMX_IPD_OPC_MODE_STF = 1LL, /* All bloccks into L2 */ + CVMX_IPD_OPC_MODE_STF1_STT = 2LL, /* 1st block L2, rest DRAM */ + CVMX_IPD_OPC_MODE_STF2_STT = 3LL /* 1st, 2nd blocks L2, rest DRAM */ +}; + +#ifndef CVMX_ENABLE_LEN_M8_FIX +#define CVMX_ENABLE_LEN_M8_FIX 0 +#endif + +/* CSR typedefs have been moved to cvmx-csr-*.h */ +typedef union cvmx_ipd_1st_mbuff_skip cvmx_ipd_mbuff_first_skip_t; +typedef union cvmx_ipd_1st_next_ptr_back cvmx_ipd_first_next_ptr_back_t; + +typedef cvmx_ipd_mbuff_first_skip_t cvmx_ipd_mbuff_not_first_skip_t; +typedef cvmx_ipd_first_next_ptr_back_t cvmx_ipd_second_next_ptr_back_t; + +/** + * Configure IPD + * + * @mbuff_size: Packets buffer size in 8 byte words + * @first_mbuff_skip: + * Number of 8 byte words to skip in the first buffer + * @not_first_mbuff_skip: + * Number of 8 byte words to skip in each following buffer + * @first_back: Must be same as first_mbuff_skip / 128 + * @second_back: + * Must be same as not_first_mbuff_skip / 128 + * @wqe_fpa_pool: + * FPA pool to get work entries from + * @cache_mode: + * @back_pres_enable_flag: + * Enable or disable port back pressure + */ +static inline void cvmx_ipd_config(uint64_t mbuff_size, + uint64_t first_mbuff_skip, + uint64_t not_first_mbuff_skip, + uint64_t first_back, + uint64_t second_back, + uint64_t wqe_fpa_pool, + enum cvmx_ipd_mode cache_mode, + uint64_t back_pres_enable_flag) +{ + cvmx_ipd_mbuff_first_skip_t first_skip; + cvmx_ipd_mbuff_not_first_skip_t not_first_skip; + union cvmx_ipd_packet_mbuff_size size; + cvmx_ipd_first_next_ptr_back_t first_back_struct; + cvmx_ipd_second_next_ptr_back_t second_back_struct; + union cvmx_ipd_wqe_fpa_queue wqe_pool; + union cvmx_ipd_ctl_status ipd_ctl_reg; + + first_skip.u64 = 0; + first_skip.s.skip_sz = first_mbuff_skip; + cvmx_write_csr(CVMX_IPD_1ST_MBUFF_SKIP, first_skip.u64); + + not_first_skip.u64 = 0; + not_first_skip.s.skip_sz = not_first_mbuff_skip; + cvmx_write_csr(CVMX_IPD_NOT_1ST_MBUFF_SKIP, not_first_skip.u64); + + size.u64 = 0; + size.s.mb_size = mbuff_size; + cvmx_write_csr(CVMX_IPD_PACKET_MBUFF_SIZE, size.u64); + + first_back_struct.u64 = 0; + first_back_struct.s.back = first_back; + cvmx_write_csr(CVMX_IPD_1st_NEXT_PTR_BACK, first_back_struct.u64); + + second_back_struct.u64 = 0; + second_back_struct.s.back = second_back; + cvmx_write_csr(CVMX_IPD_2nd_NEXT_PTR_BACK, second_back_struct.u64); + + wqe_pool.u64 = 0; + wqe_pool.s.wqe_pool = wqe_fpa_pool; + cvmx_write_csr(CVMX_IPD_WQE_FPA_QUEUE, wqe_pool.u64); + + ipd_ctl_reg.u64 = cvmx_read_csr(CVMX_IPD_CTL_STATUS); + ipd_ctl_reg.s.opc_mode = cache_mode; + ipd_ctl_reg.s.pbp_en = back_pres_enable_flag; + cvmx_write_csr(CVMX_IPD_CTL_STATUS, ipd_ctl_reg.u64); + + /* Note: the example RED code that used to be here has been moved to + cvmx_helper_setup_red */ +} + +/** + * Enable IPD + */ +static inline void cvmx_ipd_enable(void) +{ + union cvmx_ipd_ctl_status ipd_reg; + ipd_reg.u64 = cvmx_read_csr(CVMX_IPD_CTL_STATUS); + if (ipd_reg.s.ipd_en) { + cvmx_dprintf + ("Warning: Enabling IPD when IPD already enabled.\n"); + } + ipd_reg.s.ipd_en = 1; +#if CVMX_ENABLE_LEN_M8_FIX + if (!OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2)) + ipd_reg.s.len_m8 = TRUE; +#endif + cvmx_write_csr(CVMX_IPD_CTL_STATUS, ipd_reg.u64); +} + +/** + * Disable IPD + */ +static inline void cvmx_ipd_disable(void) +{ + union cvmx_ipd_ctl_status ipd_reg; + ipd_reg.u64 = cvmx_read_csr(CVMX_IPD_CTL_STATUS); + ipd_reg.s.ipd_en = 0; + cvmx_write_csr(CVMX_IPD_CTL_STATUS, ipd_reg.u64); +} + +/** + * Supportive function for cvmx_fpa_shutdown_pool. + */ +static inline void cvmx_ipd_free_ptr(void) +{ + /* Only CN38XXp{1,2} cannot read pointer out of the IPD */ + if (!OCTEON_IS_MODEL(OCTEON_CN38XX_PASS1) + && !OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2)) { + int no_wptr = 0; + union cvmx_ipd_ptr_count ipd_ptr_count; + ipd_ptr_count.u64 = cvmx_read_csr(CVMX_IPD_PTR_COUNT); + + /* Handle Work Queue Entry in cn56xx and cn52xx */ + if (octeon_has_feature(OCTEON_FEATURE_NO_WPTR)) { + union cvmx_ipd_ctl_status ipd_ctl_status; + ipd_ctl_status.u64 = cvmx_read_csr(CVMX_IPD_CTL_STATUS); + if (ipd_ctl_status.s.no_wptr) + no_wptr = 1; + } + + /* Free the prefetched WQE */ + if (ipd_ptr_count.s.wqev_cnt) { + union cvmx_ipd_wqe_ptr_valid ipd_wqe_ptr_valid; + ipd_wqe_ptr_valid.u64 = + cvmx_read_csr(CVMX_IPD_WQE_PTR_VALID); + if (no_wptr) + cvmx_fpa_free(cvmx_phys_to_ptr + ((uint64_t) ipd_wqe_ptr_valid.s. + ptr << 7), CVMX_FPA_PACKET_POOL, + 0); + else + cvmx_fpa_free(cvmx_phys_to_ptr + ((uint64_t) ipd_wqe_ptr_valid.s. + ptr << 7), CVMX_FPA_WQE_POOL, 0); + } + + /* Free all WQE in the fifo */ + if (ipd_ptr_count.s.wqe_pcnt) { + int i; + union cvmx_ipd_pwp_ptr_fifo_ctl ipd_pwp_ptr_fifo_ctl; + ipd_pwp_ptr_fifo_ctl.u64 = + cvmx_read_csr(CVMX_IPD_PWP_PTR_FIFO_CTL); + for (i = 0; i < ipd_ptr_count.s.wqe_pcnt; i++) { + ipd_pwp_ptr_fifo_ctl.s.cena = 0; + ipd_pwp_ptr_fifo_ctl.s.raddr = + ipd_pwp_ptr_fifo_ctl.s.max_cnts + + (ipd_pwp_ptr_fifo_ctl.s.wraddr + + i) % ipd_pwp_ptr_fifo_ctl.s.max_cnts; + cvmx_write_csr(CVMX_IPD_PWP_PTR_FIFO_CTL, + ipd_pwp_ptr_fifo_ctl.u64); + ipd_pwp_ptr_fifo_ctl.u64 = + cvmx_read_csr(CVMX_IPD_PWP_PTR_FIFO_CTL); + if (no_wptr) + cvmx_fpa_free(cvmx_phys_to_ptr + ((uint64_t) + ipd_pwp_ptr_fifo_ctl.s. + ptr << 7), + CVMX_FPA_PACKET_POOL, 0); + else + cvmx_fpa_free(cvmx_phys_to_ptr + ((uint64_t) + ipd_pwp_ptr_fifo_ctl.s. + ptr << 7), + CVMX_FPA_WQE_POOL, 0); + } + ipd_pwp_ptr_fifo_ctl.s.cena = 1; + cvmx_write_csr(CVMX_IPD_PWP_PTR_FIFO_CTL, + ipd_pwp_ptr_fifo_ctl.u64); + } + + /* Free the prefetched packet */ + if (ipd_ptr_count.s.pktv_cnt) { + union cvmx_ipd_pkt_ptr_valid ipd_pkt_ptr_valid; + ipd_pkt_ptr_valid.u64 = + cvmx_read_csr(CVMX_IPD_PKT_PTR_VALID); + cvmx_fpa_free(cvmx_phys_to_ptr + (ipd_pkt_ptr_valid.s.ptr << 7), + CVMX_FPA_PACKET_POOL, 0); + } + + /* Free the per port prefetched packets */ + if (1) { + int i; + union cvmx_ipd_prc_port_ptr_fifo_ctl + ipd_prc_port_ptr_fifo_ctl; + ipd_prc_port_ptr_fifo_ctl.u64 = + cvmx_read_csr(CVMX_IPD_PRC_PORT_PTR_FIFO_CTL); + + for (i = 0; i < ipd_prc_port_ptr_fifo_ctl.s.max_pkt; + i++) { + ipd_prc_port_ptr_fifo_ctl.s.cena = 0; + ipd_prc_port_ptr_fifo_ctl.s.raddr = + i % ipd_prc_port_ptr_fifo_ctl.s.max_pkt; + cvmx_write_csr(CVMX_IPD_PRC_PORT_PTR_FIFO_CTL, + ipd_prc_port_ptr_fifo_ctl.u64); + ipd_prc_port_ptr_fifo_ctl.u64 = + cvmx_read_csr + (CVMX_IPD_PRC_PORT_PTR_FIFO_CTL); + cvmx_fpa_free(cvmx_phys_to_ptr + ((uint64_t) + ipd_prc_port_ptr_fifo_ctl.s. + ptr << 7), CVMX_FPA_PACKET_POOL, + 0); + } + ipd_prc_port_ptr_fifo_ctl.s.cena = 1; + cvmx_write_csr(CVMX_IPD_PRC_PORT_PTR_FIFO_CTL, + ipd_prc_port_ptr_fifo_ctl.u64); + } + + /* Free all packets in the holding fifo */ + if (ipd_ptr_count.s.pfif_cnt) { + int i; + union cvmx_ipd_prc_hold_ptr_fifo_ctl + ipd_prc_hold_ptr_fifo_ctl; + + ipd_prc_hold_ptr_fifo_ctl.u64 = + cvmx_read_csr(CVMX_IPD_PRC_HOLD_PTR_FIFO_CTL); + + for (i = 0; i < ipd_ptr_count.s.pfif_cnt; i++) { + ipd_prc_hold_ptr_fifo_ctl.s.cena = 0; + ipd_prc_hold_ptr_fifo_ctl.s.raddr = + (ipd_prc_hold_ptr_fifo_ctl.s.praddr + + i) % ipd_prc_hold_ptr_fifo_ctl.s.max_pkt; + cvmx_write_csr(CVMX_IPD_PRC_HOLD_PTR_FIFO_CTL, + ipd_prc_hold_ptr_fifo_ctl.u64); + ipd_prc_hold_ptr_fifo_ctl.u64 = + cvmx_read_csr + (CVMX_IPD_PRC_HOLD_PTR_FIFO_CTL); + cvmx_fpa_free(cvmx_phys_to_ptr + ((uint64_t) + ipd_prc_hold_ptr_fifo_ctl.s. + ptr << 7), CVMX_FPA_PACKET_POOL, + 0); + } + ipd_prc_hold_ptr_fifo_ctl.s.cena = 1; + cvmx_write_csr(CVMX_IPD_PRC_HOLD_PTR_FIFO_CTL, + ipd_prc_hold_ptr_fifo_ctl.u64); + } + + /* Free all packets in the fifo */ + if (ipd_ptr_count.s.pkt_pcnt) { + int i; + union cvmx_ipd_pwp_ptr_fifo_ctl ipd_pwp_ptr_fifo_ctl; + ipd_pwp_ptr_fifo_ctl.u64 = + cvmx_read_csr(CVMX_IPD_PWP_PTR_FIFO_CTL); + + for (i = 0; i < ipd_ptr_count.s.pkt_pcnt; i++) { + ipd_pwp_ptr_fifo_ctl.s.cena = 0; + ipd_pwp_ptr_fifo_ctl.s.raddr = + (ipd_pwp_ptr_fifo_ctl.s.praddr + + i) % ipd_pwp_ptr_fifo_ctl.s.max_cnts; + cvmx_write_csr(CVMX_IPD_PWP_PTR_FIFO_CTL, + ipd_pwp_ptr_fifo_ctl.u64); + ipd_pwp_ptr_fifo_ctl.u64 = + cvmx_read_csr(CVMX_IPD_PWP_PTR_FIFO_CTL); + cvmx_fpa_free(cvmx_phys_to_ptr + ((uint64_t) ipd_pwp_ptr_fifo_ctl. + s.ptr << 7), + CVMX_FPA_PACKET_POOL, 0); + } + ipd_pwp_ptr_fifo_ctl.s.cena = 1; + cvmx_write_csr(CVMX_IPD_PWP_PTR_FIFO_CTL, + ipd_pwp_ptr_fifo_ctl.u64); + } + + /* Reset the IPD to get all buffers out of it */ + { + union cvmx_ipd_ctl_status ipd_ctl_status; + ipd_ctl_status.u64 = cvmx_read_csr(CVMX_IPD_CTL_STATUS); + ipd_ctl_status.s.reset = 1; + cvmx_write_csr(CVMX_IPD_CTL_STATUS, ipd_ctl_status.u64); + } + + /* Reset the PIP */ + { + union cvmx_pip_sft_rst pip_sft_rst; + pip_sft_rst.u64 = cvmx_read_csr(CVMX_PIP_SFT_RST); + pip_sft_rst.s.rst = 1; + cvmx_write_csr(CVMX_PIP_SFT_RST, pip_sft_rst.u64); + } + } +} + +#endif /* __CVMX_IPD_H__ */ diff --git a/drivers/staging/octeon/cvmx-mdio.h b/drivers/staging/octeon/cvmx-mdio.h new file mode 100644 index 0000000..c987a75 --- /dev/null +++ b/drivers/staging/octeon/cvmx-mdio.h @@ -0,0 +1,506 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * along with this file; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +/* + * + * Interface to the SMI/MDIO hardware, including support for both IEEE 802.3 + * clause 22 and clause 45 operations. + * + */ + +#ifndef __CVMX_MIO_H__ +#define __CVMX_MIO_H__ + +#include "cvmx-smix-defs.h" + +/** + * PHY register 0 from the 802.3 spec + */ +#define CVMX_MDIO_PHY_REG_CONTROL 0 +typedef union { + uint16_t u16; + struct { + uint16_t reset:1; + uint16_t loopback:1; + uint16_t speed_lsb:1; + uint16_t autoneg_enable:1; + uint16_t power_down:1; + uint16_t isolate:1; + uint16_t restart_autoneg:1; + uint16_t duplex:1; + uint16_t collision_test:1; + uint16_t speed_msb:1; + uint16_t unidirectional_enable:1; + uint16_t reserved_0_4:5; + } s; +} cvmx_mdio_phy_reg_control_t; + +/** + * PHY register 1 from the 802.3 spec + */ +#define CVMX_MDIO_PHY_REG_STATUS 1 +typedef union { + uint16_t u16; + struct { + uint16_t capable_100base_t4:1; + uint16_t capable_100base_x_full:1; + uint16_t capable_100base_x_half:1; + uint16_t capable_10_full:1; + uint16_t capable_10_half:1; + uint16_t capable_100base_t2_full:1; + uint16_t capable_100base_t2_half:1; + uint16_t capable_extended_status:1; + uint16_t capable_unidirectional:1; + uint16_t capable_mf_preamble_suppression:1; + uint16_t autoneg_complete:1; + uint16_t remote_fault:1; + uint16_t capable_autoneg:1; + uint16_t link_status:1; + uint16_t jabber_detect:1; + uint16_t capable_extended_registers:1; + + } s; +} cvmx_mdio_phy_reg_status_t; + +/** + * PHY register 2 from the 802.3 spec + */ +#define CVMX_MDIO_PHY_REG_ID1 2 +typedef union { + uint16_t u16; + struct { + uint16_t oui_bits_3_18; + } s; +} cvmx_mdio_phy_reg_id1_t; + +/** + * PHY register 3 from the 802.3 spec + */ +#define CVMX_MDIO_PHY_REG_ID2 3 +typedef union { + uint16_t u16; + struct { + uint16_t oui_bits_19_24:6; + uint16_t model:6; + uint16_t revision:4; + } s; +} cvmx_mdio_phy_reg_id2_t; + +/** + * PHY register 4 from the 802.3 spec + */ +#define CVMX_MDIO_PHY_REG_AUTONEG_ADVER 4 +typedef union { + uint16_t u16; + struct { + uint16_t next_page:1; + uint16_t reserved_14:1; + uint16_t remote_fault:1; + uint16_t reserved_12:1; + uint16_t asymmetric_pause:1; + uint16_t pause:1; + uint16_t advert_100base_t4:1; + uint16_t advert_100base_tx_full:1; + uint16_t advert_100base_tx_half:1; + uint16_t advert_10base_tx_full:1; + uint16_t advert_10base_tx_half:1; + uint16_t selector:5; + } s; +} cvmx_mdio_phy_reg_autoneg_adver_t; + +/** + * PHY register 5 from the 802.3 spec + */ +#define CVMX_MDIO_PHY_REG_LINK_PARTNER_ABILITY 5 +typedef union { + uint16_t u16; + struct { + uint16_t next_page:1; + uint16_t ack:1; + uint16_t remote_fault:1; + uint16_t reserved_12:1; + uint16_t asymmetric_pause:1; + uint16_t pause:1; + uint16_t advert_100base_t4:1; + uint16_t advert_100base_tx_full:1; + uint16_t advert_100base_tx_half:1; + uint16_t advert_10base_tx_full:1; + uint16_t advert_10base_tx_half:1; + uint16_t selector:5; + } s; +} cvmx_mdio_phy_reg_link_partner_ability_t; + +/** + * PHY register 6 from the 802.3 spec + */ +#define CVMX_MDIO_PHY_REG_AUTONEG_EXPANSION 6 +typedef union { + uint16_t u16; + struct { + uint16_t reserved_5_15:11; + uint16_t parallel_detection_fault:1; + uint16_t link_partner_next_page_capable:1; + uint16_t local_next_page_capable:1; + uint16_t page_received:1; + uint16_t link_partner_autoneg_capable:1; + + } s; +} cvmx_mdio_phy_reg_autoneg_expansion_t; + +/** + * PHY register 9 from the 802.3 spec + */ +#define CVMX_MDIO_PHY_REG_CONTROL_1000 9 +typedef union { + uint16_t u16; + struct { + uint16_t test_mode:3; + uint16_t manual_master_slave:1; + uint16_t master:1; + uint16_t port_type:1; + uint16_t advert_1000base_t_full:1; + uint16_t advert_1000base_t_half:1; + uint16_t reserved_0_7:8; + } s; +} cvmx_mdio_phy_reg_control_1000_t; + +/** + * PHY register 10 from the 802.3 spec + */ +#define CVMX_MDIO_PHY_REG_STATUS_1000 10 +typedef union { + uint16_t u16; + struct { + uint16_t master_slave_fault:1; + uint16_t is_master:1; + uint16_t local_receiver_ok:1; + uint16_t remote_receiver_ok:1; + uint16_t remote_capable_1000base_t_full:1; + uint16_t remote_capable_1000base_t_half:1; + uint16_t reserved_8_9:2; + uint16_t idle_error_count:8; + } s; +} cvmx_mdio_phy_reg_status_1000_t; + +/** + * PHY register 15 from the 802.3 spec + */ +#define CVMX_MDIO_PHY_REG_EXTENDED_STATUS 15 +typedef union { + uint16_t u16; + struct { + uint16_t capable_1000base_x_full:1; + uint16_t capable_1000base_x_half:1; + uint16_t capable_1000base_t_full:1; + uint16_t capable_1000base_t_half:1; + uint16_t reserved_0_11:12; + } s; +} cvmx_mdio_phy_reg_extended_status_t; + +/** + * PHY register 13 from the 802.3 spec + */ +#define CVMX_MDIO_PHY_REG_MMD_CONTROL 13 +typedef union { + uint16_t u16; + struct { + uint16_t function:2; + uint16_t reserved_5_13:9; + uint16_t devad:5; + } s; +} cvmx_mdio_phy_reg_mmd_control_t; + +/** + * PHY register 14 from the 802.3 spec + */ +#define CVMX_MDIO_PHY_REG_MMD_ADDRESS_DATA 14 +typedef union { + uint16_t u16; + struct { + uint16_t address_data:16; + } s; +} cvmx_mdio_phy_reg_mmd_address_data_t; + +/* Operating request encodings. */ +#define MDIO_CLAUSE_22_WRITE 0 +#define MDIO_CLAUSE_22_READ 1 + +#define MDIO_CLAUSE_45_ADDRESS 0 +#define MDIO_CLAUSE_45_WRITE 1 +#define MDIO_CLAUSE_45_READ_INC 2 +#define MDIO_CLAUSE_45_READ 3 + +/* MMD identifiers, mostly for accessing devices withing XENPAK modules. */ +#define CVMX_MMD_DEVICE_PMA_PMD 1 +#define CVMX_MMD_DEVICE_WIS 2 +#define CVMX_MMD_DEVICE_PCS 3 +#define CVMX_MMD_DEVICE_PHY_XS 4 +#define CVMX_MMD_DEVICE_DTS_XS 5 +#define CVMX_MMD_DEVICE_TC 6 +#define CVMX_MMD_DEVICE_CL22_EXT 29 +#define CVMX_MMD_DEVICE_VENDOR_1 30 +#define CVMX_MMD_DEVICE_VENDOR_2 31 + +/* Helper function to put MDIO interface into clause 45 mode */ +static inline void __cvmx_mdio_set_clause45_mode(int bus_id) +{ + union cvmx_smix_clk smi_clk; + /* Put bus into clause 45 mode */ + smi_clk.u64 = cvmx_read_csr(CVMX_SMIX_CLK(bus_id)); + smi_clk.s.mode = 1; + smi_clk.s.preamble = 1; + cvmx_write_csr(CVMX_SMIX_CLK(bus_id), smi_clk.u64); +} + +/* Helper function to put MDIO interface into clause 22 mode */ +static inline void __cvmx_mdio_set_clause22_mode(int bus_id) +{ + union cvmx_smix_clk smi_clk; + /* Put bus into clause 22 mode */ + smi_clk.u64 = cvmx_read_csr(CVMX_SMIX_CLK(bus_id)); + smi_clk.s.mode = 0; + cvmx_write_csr(CVMX_SMIX_CLK(bus_id), smi_clk.u64); +} + +/** + * Perform an MII read. This function is used to read PHY + * registers controlling auto negotiation. + * + * @bus_id: MDIO bus number. Zero on most chips, but some chips (ex CN56XX) + * support multiple busses. + * @phy_id: The MII phy id + * @location: Register location to read + * + * Returns Result from the read or -1 on failure + */ +static inline int cvmx_mdio_read(int bus_id, int phy_id, int location) +{ + union cvmx_smix_cmd smi_cmd; + union cvmx_smix_rd_dat smi_rd; + int timeout = 1000; + + if (octeon_has_feature(OCTEON_FEATURE_MDIO_CLAUSE_45)) + __cvmx_mdio_set_clause22_mode(bus_id); + + smi_cmd.u64 = 0; + smi_cmd.s.phy_op = MDIO_CLAUSE_22_READ; + smi_cmd.s.phy_adr = phy_id; + smi_cmd.s.reg_adr = location; + cvmx_write_csr(CVMX_SMIX_CMD(bus_id), smi_cmd.u64); + + do { + cvmx_wait(1000); + smi_rd.u64 = cvmx_read_csr(CVMX_SMIX_RD_DAT(bus_id)); + } while (smi_rd.s.pending && timeout--); + + if (smi_rd.s.val) + return smi_rd.s.dat; + else + return -1; +} + +/** + * Perform an MII write. This function is used to write PHY + * registers controlling auto negotiation. + * + * @bus_id: MDIO bus number. Zero on most chips, but some chips (ex CN56XX) + * support multiple busses. + * @phy_id: The MII phy id + * @location: Register location to write + * @val: Value to write + * + * Returns -1 on error + * 0 on success + */ +static inline int cvmx_mdio_write(int bus_id, int phy_id, int location, int val) +{ + union cvmx_smix_cmd smi_cmd; + union cvmx_smix_wr_dat smi_wr; + int timeout = 1000; + + if (octeon_has_feature(OCTEON_FEATURE_MDIO_CLAUSE_45)) + __cvmx_mdio_set_clause22_mode(bus_id); + + smi_wr.u64 = 0; + smi_wr.s.dat = val; + cvmx_write_csr(CVMX_SMIX_WR_DAT(bus_id), smi_wr.u64); + + smi_cmd.u64 = 0; + smi_cmd.s.phy_op = MDIO_CLAUSE_22_WRITE; + smi_cmd.s.phy_adr = phy_id; + smi_cmd.s.reg_adr = location; + cvmx_write_csr(CVMX_SMIX_CMD(bus_id), smi_cmd.u64); + + do { + cvmx_wait(1000); + smi_wr.u64 = cvmx_read_csr(CVMX_SMIX_WR_DAT(bus_id)); + } while (smi_wr.s.pending && --timeout); + if (timeout <= 0) + return -1; + + return 0; +} + +/** + * Perform an IEEE 802.3 clause 45 MII read. This function is used to + * read PHY registers controlling auto negotiation. + * + * @bus_id: MDIO bus number. Zero on most chips, but some chips (ex CN56XX) + * support multiple busses. + * @phy_id: The MII phy id + * @device: MDIO Managable Device (MMD) id + * @location: Register location to read + * + * Returns Result from the read or -1 on failure + */ + +static inline int cvmx_mdio_45_read(int bus_id, int phy_id, int device, + int location) +{ + union cvmx_smix_cmd smi_cmd; + union cvmx_smix_rd_dat smi_rd; + union cvmx_smix_wr_dat smi_wr; + int timeout = 1000; + + if (!octeon_has_feature(OCTEON_FEATURE_MDIO_CLAUSE_45)) + return -1; + + __cvmx_mdio_set_clause45_mode(bus_id); + + smi_wr.u64 = 0; + smi_wr.s.dat = location; + cvmx_write_csr(CVMX_SMIX_WR_DAT(bus_id), smi_wr.u64); + + smi_cmd.u64 = 0; + smi_cmd.s.phy_op = MDIO_CLAUSE_45_ADDRESS; + smi_cmd.s.phy_adr = phy_id; + smi_cmd.s.reg_adr = device; + cvmx_write_csr(CVMX_SMIX_CMD(bus_id), smi_cmd.u64); + + do { + cvmx_wait(1000); + smi_wr.u64 = cvmx_read_csr(CVMX_SMIX_WR_DAT(bus_id)); + } while (smi_wr.s.pending && --timeout); + if (timeout <= 0) { + cvmx_dprintf("cvmx_mdio_45_read: bus_id %d phy_id %2d " + "device %2d register %2d TIME OUT(address)\n", + bus_id, phy_id, device, location); + return -1; + } + + smi_cmd.u64 = 0; + smi_cmd.s.phy_op = MDIO_CLAUSE_45_READ; + smi_cmd.s.phy_adr = phy_id; + smi_cmd.s.reg_adr = device; + cvmx_write_csr(CVMX_SMIX_CMD(bus_id), smi_cmd.u64); + + do { + cvmx_wait(1000); + smi_rd.u64 = cvmx_read_csr(CVMX_SMIX_RD_DAT(bus_id)); + } while (smi_rd.s.pending && timeout--); + + if (timeout <= 0) { + cvmx_dprintf("cvmx_mdio_45_read: bus_id %d phy_id %2d " + "device %2d register %2d TIME OUT(data)\n", + bus_id, phy_id, device, location); + return -1; + } + + if (smi_rd.s.val) + return smi_rd.s.dat; + else { + cvmx_dprintf("cvmx_mdio_45_read: bus_id %d phy_id %2d " + "device %2d register %2d INVALID READ\n", + bus_id, phy_id, device, location); + return -1; + } +} + +/** + * Perform an IEEE 802.3 clause 45 MII write. This function is used to + * write PHY registers controlling auto negotiation. + * + * @bus_id: MDIO bus number. Zero on most chips, but some chips (ex CN56XX) + * support multiple busses. + * @phy_id: The MII phy id + * @device: MDIO Managable Device (MMD) id + * @location: Register location to write + * @val: Value to write + * + * Returns -1 on error + * 0 on success + */ +static inline int cvmx_mdio_45_write(int bus_id, int phy_id, int device, + int location, int val) +{ + union cvmx_smix_cmd smi_cmd; + union cvmx_smix_wr_dat smi_wr; + int timeout = 1000; + + if (!octeon_has_feature(OCTEON_FEATURE_MDIO_CLAUSE_45)) + return -1; + + __cvmx_mdio_set_clause45_mode(bus_id); + + smi_wr.u64 = 0; + smi_wr.s.dat = location; + cvmx_write_csr(CVMX_SMIX_WR_DAT(bus_id), smi_wr.u64); + + smi_cmd.u64 = 0; + smi_cmd.s.phy_op = MDIO_CLAUSE_45_ADDRESS; + smi_cmd.s.phy_adr = phy_id; + smi_cmd.s.reg_adr = device; + cvmx_write_csr(CVMX_SMIX_CMD(bus_id), smi_cmd.u64); + + do { + cvmx_wait(1000); + smi_wr.u64 = cvmx_read_csr(CVMX_SMIX_WR_DAT(bus_id)); + } while (smi_wr.s.pending && --timeout); + if (timeout <= 0) + return -1; + + smi_wr.u64 = 0; + smi_wr.s.dat = val; + cvmx_write_csr(CVMX_SMIX_WR_DAT(bus_id), smi_wr.u64); + + smi_cmd.u64 = 0; + smi_cmd.s.phy_op = MDIO_CLAUSE_45_WRITE; + smi_cmd.s.phy_adr = phy_id; + smi_cmd.s.reg_adr = device; + cvmx_write_csr(CVMX_SMIX_CMD(bus_id), smi_cmd.u64); + + do { + cvmx_wait(1000); + smi_wr.u64 = cvmx_read_csr(CVMX_SMIX_WR_DAT(bus_id)); + } while (smi_wr.s.pending && --timeout); + if (timeout <= 0) + return -1; + + return 0; +} + +#endif diff --git a/drivers/staging/octeon/cvmx-packet.h b/drivers/staging/octeon/cvmx-packet.h new file mode 100644 index 0000000..62ffe78 --- /dev/null +++ b/drivers/staging/octeon/cvmx-packet.h @@ -0,0 +1,65 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * along with this file; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +/** + * + * Packet buffer defines. + */ + +#ifndef __CVMX_PACKET_H__ +#define __CVMX_PACKET_H__ + +/** + * This structure defines a buffer pointer on Octeon + */ +union cvmx_buf_ptr { + void *ptr; + uint64_t u64; + struct { + /* + * if set, invert the "free" pick of the overall + * packet. HW always sets this bit to 0 on inbound + * packet + */ + uint64_t i:1; + /* + * Indicates the amount to back up to get to the + * buffer start in cache lines. In most cases this is + * less than one complete cache line, so the value is + * zero. + */ + uint64_t back:4; + /* The pool that the buffer came from / goes to */ + uint64_t pool:3; + /* The size of the segment pointed to by addr (in bytes) */ + uint64_t size:16; + /* Pointer to the first byte of the data, NOT buffer */ + uint64_t addr:40; + } s; +}; + +#endif /* __CVMX_PACKET_H__ */ diff --git a/drivers/staging/octeon/cvmx-pcsx-defs.h b/drivers/staging/octeon/cvmx-pcsx-defs.h new file mode 100644 index 0000000..d45952d --- /dev/null +++ b/drivers/staging/octeon/cvmx-pcsx-defs.h @@ -0,0 +1,370 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * along with this file; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +#ifndef __CVMX_PCSX_DEFS_H__ +#define __CVMX_PCSX_DEFS_H__ + +#define CVMX_PCSX_ANX_ADV_REG(offset, block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0001010ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_PCSX_ANX_EXT_ST_REG(offset, block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0001028ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_PCSX_ANX_LP_ABIL_REG(offset, block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0001018ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_PCSX_ANX_RESULTS_REG(offset, block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0001020ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_PCSX_INTX_EN_REG(offset, block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0001088ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_PCSX_INTX_REG(offset, block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0001080ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_PCSX_LINKX_TIMER_COUNT_REG(offset, block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0001040ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_PCSX_LOG_ANLX_REG(offset, block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0001090ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_PCSX_MISCX_CTL_REG(offset, block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0001078ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_PCSX_MRX_CONTROL_REG(offset, block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0001000ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_PCSX_MRX_STATUS_REG(offset, block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0001008ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_PCSX_RXX_STATES_REG(offset, block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0001058ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_PCSX_RXX_SYNC_REG(offset, block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0001050ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_PCSX_SGMX_AN_ADV_REG(offset, block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0001068ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_PCSX_SGMX_LP_ADV_REG(offset, block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0001070ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_PCSX_TXX_STATES_REG(offset, block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0001060ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_PCSX_TX_RXX_POLARITY_REG(offset, block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0001048ull + (((offset) & 3) * 1024) + (((block_id) & 1) * 0x8000000ull)) + +union cvmx_pcsx_anx_adv_reg { + uint64_t u64; + struct cvmx_pcsx_anx_adv_reg_s { + uint64_t reserved_16_63:48; + uint64_t np:1; + uint64_t reserved_14_14:1; + uint64_t rem_flt:2; + uint64_t reserved_9_11:3; + uint64_t pause:2; + uint64_t hfd:1; + uint64_t fd:1; + uint64_t reserved_0_4:5; + } s; + struct cvmx_pcsx_anx_adv_reg_s cn52xx; + struct cvmx_pcsx_anx_adv_reg_s cn52xxp1; + struct cvmx_pcsx_anx_adv_reg_s cn56xx; + struct cvmx_pcsx_anx_adv_reg_s cn56xxp1; +}; + +union cvmx_pcsx_anx_ext_st_reg { + uint64_t u64; + struct cvmx_pcsx_anx_ext_st_reg_s { + uint64_t reserved_16_63:48; + uint64_t thou_xfd:1; + uint64_t thou_xhd:1; + uint64_t thou_tfd:1; + uint64_t thou_thd:1; + uint64_t reserved_0_11:12; + } s; + struct cvmx_pcsx_anx_ext_st_reg_s cn52xx; + struct cvmx_pcsx_anx_ext_st_reg_s cn52xxp1; + struct cvmx_pcsx_anx_ext_st_reg_s cn56xx; + struct cvmx_pcsx_anx_ext_st_reg_s cn56xxp1; +}; + +union cvmx_pcsx_anx_lp_abil_reg { + uint64_t u64; + struct cvmx_pcsx_anx_lp_abil_reg_s { + uint64_t reserved_16_63:48; + uint64_t np:1; + uint64_t ack:1; + uint64_t rem_flt:2; + uint64_t reserved_9_11:3; + uint64_t pause:2; + uint64_t hfd:1; + uint64_t fd:1; + uint64_t reserved_0_4:5; + } s; + struct cvmx_pcsx_anx_lp_abil_reg_s cn52xx; + struct cvmx_pcsx_anx_lp_abil_reg_s cn52xxp1; + struct cvmx_pcsx_anx_lp_abil_reg_s cn56xx; + struct cvmx_pcsx_anx_lp_abil_reg_s cn56xxp1; +}; + +union cvmx_pcsx_anx_results_reg { + uint64_t u64; + struct cvmx_pcsx_anx_results_reg_s { + uint64_t reserved_7_63:57; + uint64_t pause:2; + uint64_t spd:2; + uint64_t an_cpt:1; + uint64_t dup:1; + uint64_t link_ok:1; + } s; + struct cvmx_pcsx_anx_results_reg_s cn52xx; + struct cvmx_pcsx_anx_results_reg_s cn52xxp1; + struct cvmx_pcsx_anx_results_reg_s cn56xx; + struct cvmx_pcsx_anx_results_reg_s cn56xxp1; +}; + +union cvmx_pcsx_intx_en_reg { + uint64_t u64; + struct cvmx_pcsx_intx_en_reg_s { + uint64_t reserved_12_63:52; + uint64_t dup:1; + uint64_t sync_bad_en:1; + uint64_t an_bad_en:1; + uint64_t rxlock_en:1; + uint64_t rxbad_en:1; + uint64_t rxerr_en:1; + uint64_t txbad_en:1; + uint64_t txfifo_en:1; + uint64_t txfifu_en:1; + uint64_t an_err_en:1; + uint64_t xmit_en:1; + uint64_t lnkspd_en:1; + } s; + struct cvmx_pcsx_intx_en_reg_s cn52xx; + struct cvmx_pcsx_intx_en_reg_s cn52xxp1; + struct cvmx_pcsx_intx_en_reg_s cn56xx; + struct cvmx_pcsx_intx_en_reg_s cn56xxp1; +}; + +union cvmx_pcsx_intx_reg { + uint64_t u64; + struct cvmx_pcsx_intx_reg_s { + uint64_t reserved_12_63:52; + uint64_t dup:1; + uint64_t sync_bad:1; + uint64_t an_bad:1; + uint64_t rxlock:1; + uint64_t rxbad:1; + uint64_t rxerr:1; + uint64_t txbad:1; + uint64_t txfifo:1; + uint64_t txfifu:1; + uint64_t an_err:1; + uint64_t xmit:1; + uint64_t lnkspd:1; + } s; + struct cvmx_pcsx_intx_reg_s cn52xx; + struct cvmx_pcsx_intx_reg_s cn52xxp1; + struct cvmx_pcsx_intx_reg_s cn56xx; + struct cvmx_pcsx_intx_reg_s cn56xxp1; +}; + +union cvmx_pcsx_linkx_timer_count_reg { + uint64_t u64; + struct cvmx_pcsx_linkx_timer_count_reg_s { + uint64_t reserved_16_63:48; + uint64_t count:16; + } s; + struct cvmx_pcsx_linkx_timer_count_reg_s cn52xx; + struct cvmx_pcsx_linkx_timer_count_reg_s cn52xxp1; + struct cvmx_pcsx_linkx_timer_count_reg_s cn56xx; + struct cvmx_pcsx_linkx_timer_count_reg_s cn56xxp1; +}; + +union cvmx_pcsx_log_anlx_reg { + uint64_t u64; + struct cvmx_pcsx_log_anlx_reg_s { + uint64_t reserved_4_63:60; + uint64_t lafifovfl:1; + uint64_t la_en:1; + uint64_t pkt_sz:2; + } s; + struct cvmx_pcsx_log_anlx_reg_s cn52xx; + struct cvmx_pcsx_log_anlx_reg_s cn52xxp1; + struct cvmx_pcsx_log_anlx_reg_s cn56xx; + struct cvmx_pcsx_log_anlx_reg_s cn56xxp1; +}; + +union cvmx_pcsx_miscx_ctl_reg { + uint64_t u64; + struct cvmx_pcsx_miscx_ctl_reg_s { + uint64_t reserved_13_63:51; + uint64_t sgmii:1; + uint64_t gmxeno:1; + uint64_t loopbck2:1; + uint64_t mac_phy:1; + uint64_t mode:1; + uint64_t an_ovrd:1; + uint64_t samp_pt:7; + } s; + struct cvmx_pcsx_miscx_ctl_reg_s cn52xx; + struct cvmx_pcsx_miscx_ctl_reg_s cn52xxp1; + struct cvmx_pcsx_miscx_ctl_reg_s cn56xx; + struct cvmx_pcsx_miscx_ctl_reg_s cn56xxp1; +}; + +union cvmx_pcsx_mrx_control_reg { + uint64_t u64; + struct cvmx_pcsx_mrx_control_reg_s { + uint64_t reserved_16_63:48; + uint64_t reset:1; + uint64_t loopbck1:1; + uint64_t spdlsb:1; + uint64_t an_en:1; + uint64_t pwr_dn:1; + uint64_t reserved_10_10:1; + uint64_t rst_an:1; + uint64_t dup:1; + uint64_t coltst:1; + uint64_t spdmsb:1; + uint64_t uni:1; + uint64_t reserved_0_4:5; + } s; + struct cvmx_pcsx_mrx_control_reg_s cn52xx; + struct cvmx_pcsx_mrx_control_reg_s cn52xxp1; + struct cvmx_pcsx_mrx_control_reg_s cn56xx; + struct cvmx_pcsx_mrx_control_reg_s cn56xxp1; +}; + +union cvmx_pcsx_mrx_status_reg { + uint64_t u64; + struct cvmx_pcsx_mrx_status_reg_s { + uint64_t reserved_16_63:48; + uint64_t hun_t4:1; + uint64_t hun_xfd:1; + uint64_t hun_xhd:1; + uint64_t ten_fd:1; + uint64_t ten_hd:1; + uint64_t hun_t2fd:1; + uint64_t hun_t2hd:1; + uint64_t ext_st:1; + uint64_t reserved_7_7:1; + uint64_t prb_sup:1; + uint64_t an_cpt:1; + uint64_t rm_flt:1; + uint64_t an_abil:1; + uint64_t lnk_st:1; + uint64_t reserved_1_1:1; + uint64_t extnd:1; + } s; + struct cvmx_pcsx_mrx_status_reg_s cn52xx; + struct cvmx_pcsx_mrx_status_reg_s cn52xxp1; + struct cvmx_pcsx_mrx_status_reg_s cn56xx; + struct cvmx_pcsx_mrx_status_reg_s cn56xxp1; +}; + +union cvmx_pcsx_rxx_states_reg { + uint64_t u64; + struct cvmx_pcsx_rxx_states_reg_s { + uint64_t reserved_16_63:48; + uint64_t rx_bad:1; + uint64_t rx_st:5; + uint64_t sync_bad:1; + uint64_t sync:4; + uint64_t an_bad:1; + uint64_t an_st:4; + } s; + struct cvmx_pcsx_rxx_states_reg_s cn52xx; + struct cvmx_pcsx_rxx_states_reg_s cn52xxp1; + struct cvmx_pcsx_rxx_states_reg_s cn56xx; + struct cvmx_pcsx_rxx_states_reg_s cn56xxp1; +}; + +union cvmx_pcsx_rxx_sync_reg { + uint64_t u64; + struct cvmx_pcsx_rxx_sync_reg_s { + uint64_t reserved_2_63:62; + uint64_t sync:1; + uint64_t bit_lock:1; + } s; + struct cvmx_pcsx_rxx_sync_reg_s cn52xx; + struct cvmx_pcsx_rxx_sync_reg_s cn52xxp1; + struct cvmx_pcsx_rxx_sync_reg_s cn56xx; + struct cvmx_pcsx_rxx_sync_reg_s cn56xxp1; +}; + +union cvmx_pcsx_sgmx_an_adv_reg { + uint64_t u64; + struct cvmx_pcsx_sgmx_an_adv_reg_s { + uint64_t reserved_16_63:48; + uint64_t link:1; + uint64_t ack:1; + uint64_t reserved_13_13:1; + uint64_t dup:1; + uint64_t speed:2; + uint64_t reserved_1_9:9; + uint64_t one:1; + } s; + struct cvmx_pcsx_sgmx_an_adv_reg_s cn52xx; + struct cvmx_pcsx_sgmx_an_adv_reg_s cn52xxp1; + struct cvmx_pcsx_sgmx_an_adv_reg_s cn56xx; + struct cvmx_pcsx_sgmx_an_adv_reg_s cn56xxp1; +}; + +union cvmx_pcsx_sgmx_lp_adv_reg { + uint64_t u64; + struct cvmx_pcsx_sgmx_lp_adv_reg_s { + uint64_t reserved_16_63:48; + uint64_t link:1; + uint64_t reserved_13_14:2; + uint64_t dup:1; + uint64_t speed:2; + uint64_t reserved_1_9:9; + uint64_t one:1; + } s; + struct cvmx_pcsx_sgmx_lp_adv_reg_s cn52xx; + struct cvmx_pcsx_sgmx_lp_adv_reg_s cn52xxp1; + struct cvmx_pcsx_sgmx_lp_adv_reg_s cn56xx; + struct cvmx_pcsx_sgmx_lp_adv_reg_s cn56xxp1; +}; + +union cvmx_pcsx_txx_states_reg { + uint64_t u64; + struct cvmx_pcsx_txx_states_reg_s { + uint64_t reserved_7_63:57; + uint64_t xmit:2; + uint64_t tx_bad:1; + uint64_t ord_st:4; + } s; + struct cvmx_pcsx_txx_states_reg_s cn52xx; + struct cvmx_pcsx_txx_states_reg_s cn52xxp1; + struct cvmx_pcsx_txx_states_reg_s cn56xx; + struct cvmx_pcsx_txx_states_reg_s cn56xxp1; +}; + +union cvmx_pcsx_tx_rxx_polarity_reg { + uint64_t u64; + struct cvmx_pcsx_tx_rxx_polarity_reg_s { + uint64_t reserved_4_63:60; + uint64_t rxovrd:1; + uint64_t autorxpl:1; + uint64_t rxplrt:1; + uint64_t txplrt:1; + } s; + struct cvmx_pcsx_tx_rxx_polarity_reg_s cn52xx; + struct cvmx_pcsx_tx_rxx_polarity_reg_s cn52xxp1; + struct cvmx_pcsx_tx_rxx_polarity_reg_s cn56xx; + struct cvmx_pcsx_tx_rxx_polarity_reg_s cn56xxp1; +}; + +#endif diff --git a/drivers/staging/octeon/cvmx-pcsxx-defs.h b/drivers/staging/octeon/cvmx-pcsxx-defs.h new file mode 100644 index 0000000..55d120f --- /dev/null +++ b/drivers/staging/octeon/cvmx-pcsxx-defs.h @@ -0,0 +1,316 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * along with this file; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +#ifndef __CVMX_PCSXX_DEFS_H__ +#define __CVMX_PCSXX_DEFS_H__ + +#define CVMX_PCSXX_10GBX_STATUS_REG(block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0000828ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_PCSXX_BIST_STATUS_REG(block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0000870ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_PCSXX_BIT_LOCK_STATUS_REG(block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0000850ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_PCSXX_CONTROL1_REG(block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0000800ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_PCSXX_CONTROL2_REG(block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0000818ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_PCSXX_INT_EN_REG(block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0000860ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_PCSXX_INT_REG(block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0000858ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_PCSXX_LOG_ANL_REG(block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0000868ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_PCSXX_MISC_CTL_REG(block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0000848ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_PCSXX_RX_SYNC_STATES_REG(block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0000838ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_PCSXX_SPD_ABIL_REG(block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0000810ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_PCSXX_STATUS1_REG(block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0000808ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_PCSXX_STATUS2_REG(block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0000820ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_PCSXX_TX_RX_POLARITY_REG(block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0000840ull + (((block_id) & 1) * 0x8000000ull)) +#define CVMX_PCSXX_TX_RX_STATES_REG(block_id) \ + CVMX_ADD_IO_SEG(0x00011800B0000830ull + (((block_id) & 1) * 0x8000000ull)) + +union cvmx_pcsxx_10gbx_status_reg { + uint64_t u64; + struct cvmx_pcsxx_10gbx_status_reg_s { + uint64_t reserved_13_63:51; + uint64_t alignd:1; + uint64_t pattst:1; + uint64_t reserved_4_10:7; + uint64_t l3sync:1; + uint64_t l2sync:1; + uint64_t l1sync:1; + uint64_t l0sync:1; + } s; + struct cvmx_pcsxx_10gbx_status_reg_s cn52xx; + struct cvmx_pcsxx_10gbx_status_reg_s cn52xxp1; + struct cvmx_pcsxx_10gbx_status_reg_s cn56xx; + struct cvmx_pcsxx_10gbx_status_reg_s cn56xxp1; +}; + +union cvmx_pcsxx_bist_status_reg { + uint64_t u64; + struct cvmx_pcsxx_bist_status_reg_s { + uint64_t reserved_1_63:63; + uint64_t bist_status:1; + } s; + struct cvmx_pcsxx_bist_status_reg_s cn52xx; + struct cvmx_pcsxx_bist_status_reg_s cn52xxp1; + struct cvmx_pcsxx_bist_status_reg_s cn56xx; + struct cvmx_pcsxx_bist_status_reg_s cn56xxp1; +}; + +union cvmx_pcsxx_bit_lock_status_reg { + uint64_t u64; + struct cvmx_pcsxx_bit_lock_status_reg_s { + uint64_t reserved_4_63:60; + uint64_t bitlck3:1; + uint64_t bitlck2:1; + uint64_t bitlck1:1; + uint64_t bitlck0:1; + } s; + struct cvmx_pcsxx_bit_lock_status_reg_s cn52xx; + struct cvmx_pcsxx_bit_lock_status_reg_s cn52xxp1; + struct cvmx_pcsxx_bit_lock_status_reg_s cn56xx; + struct cvmx_pcsxx_bit_lock_status_reg_s cn56xxp1; +}; + +union cvmx_pcsxx_control1_reg { + uint64_t u64; + struct cvmx_pcsxx_control1_reg_s { + uint64_t reserved_16_63:48; + uint64_t reset:1; + uint64_t loopbck1:1; + uint64_t spdsel1:1; + uint64_t reserved_12_12:1; + uint64_t lo_pwr:1; + uint64_t reserved_7_10:4; + uint64_t spdsel0:1; + uint64_t spd:4; + uint64_t reserved_0_1:2; + } s; + struct cvmx_pcsxx_control1_reg_s cn52xx; + struct cvmx_pcsxx_control1_reg_s cn52xxp1; + struct cvmx_pcsxx_control1_reg_s cn56xx; + struct cvmx_pcsxx_control1_reg_s cn56xxp1; +}; + +union cvmx_pcsxx_control2_reg { + uint64_t u64; + struct cvmx_pcsxx_control2_reg_s { + uint64_t reserved_2_63:62; + uint64_t type:2; + } s; + struct cvmx_pcsxx_control2_reg_s cn52xx; + struct cvmx_pcsxx_control2_reg_s cn52xxp1; + struct cvmx_pcsxx_control2_reg_s cn56xx; + struct cvmx_pcsxx_control2_reg_s cn56xxp1; +}; + +union cvmx_pcsxx_int_en_reg { + uint64_t u64; + struct cvmx_pcsxx_int_en_reg_s { + uint64_t reserved_6_63:58; + uint64_t algnlos_en:1; + uint64_t synlos_en:1; + uint64_t bitlckls_en:1; + uint64_t rxsynbad_en:1; + uint64_t rxbad_en:1; + uint64_t txflt_en:1; + } s; + struct cvmx_pcsxx_int_en_reg_s cn52xx; + struct cvmx_pcsxx_int_en_reg_s cn52xxp1; + struct cvmx_pcsxx_int_en_reg_s cn56xx; + struct cvmx_pcsxx_int_en_reg_s cn56xxp1; +}; + +union cvmx_pcsxx_int_reg { + uint64_t u64; + struct cvmx_pcsxx_int_reg_s { + uint64_t reserved_6_63:58; + uint64_t algnlos:1; + uint64_t synlos:1; + uint64_t bitlckls:1; + uint64_t rxsynbad:1; + uint64_t rxbad:1; + uint64_t txflt:1; + } s; + struct cvmx_pcsxx_int_reg_s cn52xx; + struct cvmx_pcsxx_int_reg_s cn52xxp1; + struct cvmx_pcsxx_int_reg_s cn56xx; + struct cvmx_pcsxx_int_reg_s cn56xxp1; +}; + +union cvmx_pcsxx_log_anl_reg { + uint64_t u64; + struct cvmx_pcsxx_log_anl_reg_s { + uint64_t reserved_7_63:57; + uint64_t enc_mode:1; + uint64_t drop_ln:2; + uint64_t lafifovfl:1; + uint64_t la_en:1; + uint64_t pkt_sz:2; + } s; + struct cvmx_pcsxx_log_anl_reg_s cn52xx; + struct cvmx_pcsxx_log_anl_reg_s cn52xxp1; + struct cvmx_pcsxx_log_anl_reg_s cn56xx; + struct cvmx_pcsxx_log_anl_reg_s cn56xxp1; +}; + +union cvmx_pcsxx_misc_ctl_reg { + uint64_t u64; + struct cvmx_pcsxx_misc_ctl_reg_s { + uint64_t reserved_4_63:60; + uint64_t tx_swap:1; + uint64_t rx_swap:1; + uint64_t xaui:1; + uint64_t gmxeno:1; + } s; + struct cvmx_pcsxx_misc_ctl_reg_s cn52xx; + struct cvmx_pcsxx_misc_ctl_reg_s cn52xxp1; + struct cvmx_pcsxx_misc_ctl_reg_s cn56xx; + struct cvmx_pcsxx_misc_ctl_reg_s cn56xxp1; +}; + +union cvmx_pcsxx_rx_sync_states_reg { + uint64_t u64; + struct cvmx_pcsxx_rx_sync_states_reg_s { + uint64_t reserved_16_63:48; + uint64_t sync3st:4; + uint64_t sync2st:4; + uint64_t sync1st:4; + uint64_t sync0st:4; + } s; + struct cvmx_pcsxx_rx_sync_states_reg_s cn52xx; + struct cvmx_pcsxx_rx_sync_states_reg_s cn52xxp1; + struct cvmx_pcsxx_rx_sync_states_reg_s cn56xx; + struct cvmx_pcsxx_rx_sync_states_reg_s cn56xxp1; +}; + +union cvmx_pcsxx_spd_abil_reg { + uint64_t u64; + struct cvmx_pcsxx_spd_abil_reg_s { + uint64_t reserved_2_63:62; + uint64_t tenpasst:1; + uint64_t tengb:1; + } s; + struct cvmx_pcsxx_spd_abil_reg_s cn52xx; + struct cvmx_pcsxx_spd_abil_reg_s cn52xxp1; + struct cvmx_pcsxx_spd_abil_reg_s cn56xx; + struct cvmx_pcsxx_spd_abil_reg_s cn56xxp1; +}; + +union cvmx_pcsxx_status1_reg { + uint64_t u64; + struct cvmx_pcsxx_status1_reg_s { + uint64_t reserved_8_63:56; + uint64_t flt:1; + uint64_t reserved_3_6:4; + uint64_t rcv_lnk:1; + uint64_t lpable:1; + uint64_t reserved_0_0:1; + } s; + struct cvmx_pcsxx_status1_reg_s cn52xx; + struct cvmx_pcsxx_status1_reg_s cn52xxp1; + struct cvmx_pcsxx_status1_reg_s cn56xx; + struct cvmx_pcsxx_status1_reg_s cn56xxp1; +}; + +union cvmx_pcsxx_status2_reg { + uint64_t u64; + struct cvmx_pcsxx_status2_reg_s { + uint64_t reserved_16_63:48; + uint64_t dev:2; + uint64_t reserved_12_13:2; + uint64_t xmtflt:1; + uint64_t rcvflt:1; + uint64_t reserved_3_9:7; + uint64_t tengb_w:1; + uint64_t tengb_x:1; + uint64_t tengb_r:1; + } s; + struct cvmx_pcsxx_status2_reg_s cn52xx; + struct cvmx_pcsxx_status2_reg_s cn52xxp1; + struct cvmx_pcsxx_status2_reg_s cn56xx; + struct cvmx_pcsxx_status2_reg_s cn56xxp1; +}; + +union cvmx_pcsxx_tx_rx_polarity_reg { + uint64_t u64; + struct cvmx_pcsxx_tx_rx_polarity_reg_s { + uint64_t reserved_10_63:54; + uint64_t xor_rxplrt:4; + uint64_t xor_txplrt:4; + uint64_t rxplrt:1; + uint64_t txplrt:1; + } s; + struct cvmx_pcsxx_tx_rx_polarity_reg_s cn52xx; + struct cvmx_pcsxx_tx_rx_polarity_reg_cn52xxp1 { + uint64_t reserved_2_63:62; + uint64_t rxplrt:1; + uint64_t txplrt:1; + } cn52xxp1; + struct cvmx_pcsxx_tx_rx_polarity_reg_s cn56xx; + struct cvmx_pcsxx_tx_rx_polarity_reg_cn52xxp1 cn56xxp1; +}; + +union cvmx_pcsxx_tx_rx_states_reg { + uint64_t u64; + struct cvmx_pcsxx_tx_rx_states_reg_s { + uint64_t reserved_14_63:50; + uint64_t term_err:1; + uint64_t syn3bad:1; + uint64_t syn2bad:1; + uint64_t syn1bad:1; + uint64_t syn0bad:1; + uint64_t rxbad:1; + uint64_t algn_st:3; + uint64_t rx_st:2; + uint64_t tx_st:3; + } s; + struct cvmx_pcsxx_tx_rx_states_reg_s cn52xx; + struct cvmx_pcsxx_tx_rx_states_reg_cn52xxp1 { + uint64_t reserved_13_63:51; + uint64_t syn3bad:1; + uint64_t syn2bad:1; + uint64_t syn1bad:1; + uint64_t syn0bad:1; + uint64_t rxbad:1; + uint64_t algn_st:3; + uint64_t rx_st:2; + uint64_t tx_st:3; + } cn52xxp1; + struct cvmx_pcsxx_tx_rx_states_reg_s cn56xx; + struct cvmx_pcsxx_tx_rx_states_reg_cn52xxp1 cn56xxp1; +}; + +#endif diff --git a/drivers/staging/octeon/cvmx-pip-defs.h b/drivers/staging/octeon/cvmx-pip-defs.h new file mode 100644 index 0000000..5a36910 --- /dev/null +++ b/drivers/staging/octeon/cvmx-pip-defs.h @@ -0,0 +1,1267 @@ +/***********************license start*************** + * Author: Cavium Networks + * + * Contact: support@caviumnetworks.com + * This file is part of the OCTEON SDK + * + * Copyright (c) 2003-2008 Cavium Networks + * + * This file is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License, Version 2, as + * published by the Free Software Foundation. + * + * This file is distributed in the hope that it will be useful, but + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or + * NONINFRINGEMENT. See the GNU General Public License for more + * details. + * + * You should have received a copy of the GNU General Public License + * along with this file; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * or visit http://www.gnu.org/licenses/. + * + * This file may also be available under a different license from Cavium. + * Contact Cavium Networks for more information + ***********************license end**************************************/ + +#ifndef __CVMX_PIP_DEFS_H__ +#define __CVMX_PIP_DEFS_H__ + +/* + * Enumeration representing the amount of packet processing + * and validation performed by the input hardware. + */ +enum cvmx_pip_port_parse_mode { + /* + * Packet input doesn't perform any processing of the input + * packet. + */ + CVMX_PIP_PORT_CFG_MODE_NONE = 0ull, + /* + * Full packet processing is performed with pointer starting + * at the L2 (ethernet MAC) header. + */ + CVMX_PIP_PORT_CFG_MODE_SKIPL2 = 1ull, + /* + * Input packets are assumed to be IP. Results from non IP + * packets is undefined. Pointers reference the beginning of + * the IP header. + */ + CVMX_PIP_PORT_CFG_MODE_SKIPIP = 2ull +}; + +#define CVMX_PIP_BCK_PRS \ + CVMX_ADD_IO_SEG(0x00011800A0000038ull) +#define CVMX_PIP_BIST_STATUS \ + CVMX_ADD_IO_SEG(0x00011800A0000000ull) +#define CVMX_PIP_CRC_CTLX(offset) \ + CVMX_ADD_IO_SEG(0x00011800A0000040ull + (((offset) & 1) * 8)) +#define CVMX_PIP_CRC_IVX(offset) \ + CVMX_ADD_IO_SEG(0x00011800A0000050ull + (((offset) & 1) * 8)) +#define CVMX_PIP_DEC_IPSECX(offset) \ + CVMX_ADD_IO_SEG(0x00011800A0000080ull + (((offset) & 3) * 8)) +#define CVMX_PIP_DSA_SRC_GRP \ + CVMX_ADD_IO_SEG(0x00011800A0000190ull) +#define CVMX_PIP_DSA_VID_GRP \ + CVMX_ADD_IO_SEG(0x00011800A0000198ull) +#define CVMX_PIP_FRM_LEN_CHKX(offset) \ + CVMX_ADD_IO_SEG(0x00011800A0000180ull + (((offset) & 1) * 8)) +#define CVMX_PIP_GBL_CFG \ + CVMX_ADD_IO_SEG(0x00011800A0000028ull) +#define CVMX_PIP_GBL_CTL \ + CVMX_ADD_IO_SEG(0x00011800A0000020ull) +#define CVMX_PIP_HG_PRI_QOS \ + CVMX_ADD_IO_SEG(0x00011800A00001A0ull) +#define CVMX_PIP_INT_EN \ + CVMX_ADD_IO_SEG(0x00011800A0000010ull) +#define CVMX_PIP_INT_REG \ + CVMX_ADD_IO_SEG(0x00011800A0000008ull) +#define CVMX_PIP_IP_OFFSET \ + CVMX_ADD_IO_SEG(0x00011800A0000060ull) +#define CVMX_PIP_PRT_CFGX(offset) \ + CVMX_ADD_IO_SEG(0x00011800A0000200ull + (((offset) & 63) * 8)) +#define CVMX_PIP_PRT_TAGX(offset) \ + CVMX_ADD_IO_SEG(0x00011800A0000400ull + (((offset) & 63) * 8)) +#define CVMX_PIP_QOS_DIFFX(offset) \ + CVMX_ADD_IO_SEG(0x00011800A0000600ull + (((offset) & 63) * 8)) +#define CVMX_PIP_QOS_VLANX(offset) \ + CVMX_ADD_IO_SEG(0x00011800A00000C0ull + (((offset) & 7) * 8)) +#define CVMX_PIP_QOS_WATCHX(offset) \ + CVMX_ADD_IO_SEG(0x00011800A0000100ull + (((offset) & 7) * 8)) +#define CVMX_PIP_RAW_WORD \ + CVMX_ADD_IO_SEG(0x00011800A00000B0ull) +#define CVMX_PIP_SFT_RST \ + CVMX_ADD_IO_SEG(0x00011800A0000030ull) +#define CVMX_PIP_STAT0_PRTX(offset) \ + CVMX_ADD_IO_SEG(0x00011800A0000800ull + (((offset) & 63) * 80)) +#define CVMX_PIP_STAT1_PRTX(offset) \ + CVMX_ADD_IO_SEG(0x00011800A0000808ull + (((offset) & 63) * 80)) +#define CVMX_PIP_STAT2_PRTX(offset) \ + CVMX_ADD_IO_SEG(0x00011800A0000810ull + (((offset) & 63) * 80)) +#define CVMX_PIP_STAT3_PRTX(offset) \ + CVMX_ADD_IO_SEG(0x00011800A0000818ull + (((offset) & 63) * 80)) +#define CVMX_PIP_STAT4_PRTX(offset) \ + CVMX_ADD_IO_SEG(0x00011800A0000820ull + (((offset) & 63) * 80)) +#define CVMX_PIP_STAT5_PRTX(offset) \ + CVMX_ADD_IO_SEG(0x00011800A0000828ull + (((offset) & 63) * 80)) +#define CVMX_PIP_STAT6_PRTX(offset) \ + CVMX_ADD_IO_SEG(0x00011800A0000830ull + (((offset) & 63) * 80)) +#define CVMX_PIP_STAT7_PRTX(offset) \ + CVMX_ADD_IO_SEG(0x00011800A0000838ull + (((offset) & 63) * 80)) +#define CVMX_PIP_STAT8_PRTX(offset) \ + CVMX_ADD_IO_SEG(0x00011800A0000840ull + (((offset) & 63) * 80)) +#define CVMX_PIP_STAT9_PRTX(offset) \ + CVMX_ADD_IO_SEG(0x00011800A0000848ull + (((offset) & 63) * 80)) +#define CVMX_PIP_STAT_CTL \ + CVMX_ADD_IO_SEG(0x00011800A0000018ull) +#define CVMX_PIP_STAT_INB_ERRSX(offset) \ + CVMX_ADD_IO_SEG(0x00011800A0001A10ull + (((offset) & 63) * 32)) +#define CVMX_PIP_STAT_INB_OCTSX(offset) \ + CVMX_ADD_IO_SEG(0x00011800A0001A08ull + (((offset) & 63) * 32)) +#define CVMX_PIP_STAT_INB_PKTSX(offset) \ + CVMX_ADD_IO_SEG(0x00011800A0001A00ull + (((offset) & 63) * 32)) +#define CVMX_PIP_TAG_INCX(offset) \ + CVMX_ADD_IO_SEG(0x00011800A0001800ull + (((offset) & 63) * 8)) +#define CVMX_PIP_TAG_MASK \ + CVMX_ADD_IO_SEG(0x00011800A0000070ull) +#define CVMX_PIP_TAG_SECRET \ + CVMX_ADD_IO_SEG(0x00011800A0000068ull) +#define CVMX_PIP_TODO_ENTRY \ + CVMX_ADD_IO_SEG(0x00011800A0000078ull) + +union cvmx_pip_bck_prs { + uint64_t u64; + struct cvmx_pip_bck_prs_s { + uint64_t bckprs:1; + uint64_t reserved_13_62:50; + uint64_t hiwater:5; + uint64_t reserved_5_7:3; + uint64_t lowater:5; + } s; + struct cvmx_pip_bck_prs_s cn38xx; + struct cvmx_pip_bck_prs_s cn38xxp2; + struct cvmx_pip_bck_prs_s cn56xx; + struct cvmx_pip_bck_prs_s cn56xxp1; + struct cvmx_pip_bck_prs_s cn58xx; + struct cvmx_pip_bck_prs_s cn58xxp1; +}; + +union cvmx_pip_bist_status { + uint64_t u64; + struct cvmx_pip_bist_status_s { + uint64_t reserved_18_63:46; + uint64_t bist:18; + } s; + struct cvmx_pip_bist_status_s cn30xx; + struct cvmx_pip_bist_status_s cn31xx; + struct cvmx_pip_bist_status_s cn38xx; + struct cvmx_pip_bist_status_s cn38xxp2; + struct cvmx_pip_bist_status_cn50xx { + uint64_t reserved_17_63:47; + uint64_t bist:17; + } cn50xx; + struct cvmx_pip_bist_status_s cn52xx; + struct cvmx_pip_bist_status_s cn52xxp1; + struct cvmx_pip_bist_status_s cn56xx; + struct cvmx_pip_bist_status_s cn56xxp1; + struct cvmx_pip_bist_status_s cn58xx; + struct cvmx_pip_bist_status_s cn58xxp1; +}; + +union cvmx_pip_crc_ctlx { + uint64_t u64; + struct cvmx_pip_crc_ctlx_s { + uint64_t reserved_2_63:62; + uint64_t invres:1; + uint64_t reflect:1; + } s; + struct cvmx_pip_crc_ctlx_s cn38xx; + struct cvmx_pip_crc_ctlx_s cn38xxp2; + struct cvmx_pip_crc_ctlx_s cn58xx; + struct cvmx_pip_crc_ctlx_s cn58xxp1; +}; + +union cvmx_pip_crc_ivx { + uint64_t u64; + struct cvmx_pip_crc_ivx_s { + uint64_t reserved_32_63:32; + uint64_t iv:32; + } s; + struct cvmx_pip_crc_ivx_s cn38xx; + struct cvmx_pip_crc_ivx_s cn38xxp2; + struct cvmx_pip_crc_ivx_s cn58xx; + struct cvmx_pip_crc_ivx_s cn58xxp1; +}; + +union cvmx_pip_dec_ipsecx { + uint64_t u64; + struct cvmx_pip_dec_ipsecx_s { + uint64_t reserved_18_63:46; + uint64_t tcp:1; + uint64_t udp:1; + uint64_t dprt:16; + } s; + struct cvmx_pip_dec_ipsecx_s cn30xx; + struct cvmx_pip_dec_ipsecx_s cn31xx; + struct cvmx_pip_dec_ipsecx_s cn38xx; + struct cvmx_pip_dec_ipsecx_s cn38xxp2; + struct cvmx_pip_dec_ipsecx_s cn50xx; + struct cvmx_pip_dec_ipsecx_s cn52xx; + struct cvmx_pip_dec_ipsecx_s cn52xxp1; + struct cvmx_pip_dec_ipsecx_s cn56xx; + struct cvmx_pip_dec_ipsecx_s cn56xxp1; + struct cvmx_pip_dec_ipsecx_s cn58xx; + struct cvmx_pip_dec_ipsecx_s cn58xxp1; +}; + +union cvmx_pip_dsa_src_grp { + uint64_t u64; + struct cvmx_pip_dsa_src_grp_s { + uint64_t map15:4; + uint64_t map14:4; + uint64_t map13:4; + uint64_t map12:4; + uint64_t map11:4; + uint64_t map10:4; + uint64_t map9:4; + uint64_t map8:4; + uint64_t map7:4; + uint64_t map6:4; + uint64_t map5:4; + uint64_t map4:4; + uint64_t map3:4; + uint64_t map2:4; + uint64_t map1:4; + uint64_t map0:4; + } s; + struct cvmx_pip_dsa_src_grp_s cn52xx; + struct cvmx_pip_dsa_src_grp_s cn52xxp1; + struct cvmx_pip_dsa_src_grp_s cn56xx; +}; + +union cvmx_pip_dsa_vid_grp { + uint64_t u64; + struct cvmx_pip_dsa_vid_grp_s { + uint64_t map15:4; + uint64_t map14:4; + uint64_t map13:4; + uint64_t map12:4; + uint64_t map11:4; + uint64_t map10:4; + uint64_t map9:4; + uint64_t map8:4; + uint64_t map7:4; + uint64_t map6:4; + uint64_t map5:4; + uint64_t map4:4; + uint64_t map3:4; + uint64_t map2:4; + uint64_t map1:4; + uint64_t map0:4; + } s; + struct cvmx_pip_dsa_vid_grp_s cn52xx; + struct cvmx_pip_dsa_vid_grp_s cn52xxp1; + struct cvmx_pip_dsa_vid_grp_s cn56xx; +}; + +union cvmx_pip_frm_len_chkx { + uint64_t u64; + struct cvmx_pip_frm_len_chkx_s { + uint64_t reserved_32_63:32; + uint64_t maxlen:16; + uint64_t minlen:16; + } s; + struct cvmx_pip_frm_len_chkx_s cn50xx; + struct cvmx_pip_frm_len_chkx_s cn52xx; + struct cvmx_pip_frm_len_chkx_s cn52xxp1; + struct cvmx_pip_frm_len_chkx_s cn56xx; + struct cvmx_pip_frm_len_chkx_s cn56xxp1; +}; + +union cvmx_pip_gbl_cfg { + uint64_t u64; + struct cvmx_pip_gbl_cfg_s { + uint64_t reserved_19_63:45; + uint64_t tag_syn:1; + uint64_t ip6_udp:1; + uint64_t max_l2:1; + uint64_t reserved_11_15:5; + uint64_t raw_shf:3; + uint64_t reserved_3_7:5; + uint64_t nip_shf:3; + } s; + struct cvmx_pip_gbl_cfg_s cn30xx; + struct cvmx_pip_gbl_cfg_s cn31xx; + struct cvmx_pip_gbl_cfg_s cn38xx; + struct cvmx_pip_gbl_cfg_s cn38xxp2; + struct cvmx_pip_gbl_cfg_s cn50xx; + struct cvmx_pip_gbl_cfg_s cn52xx; + struct cvmx_pip_gbl_cfg_s cn52xxp1; + struct cvmx_pip_gbl_cfg_s cn56xx; + struct cvmx_pip_gbl_cfg_s cn56xxp1; + struct cvmx_pip_gbl_cfg_s cn58xx; + struct cvmx_pip_gbl_cfg_s cn58xxp1; +}; + +union cvmx_pip_gbl_ctl { + uint64_t u64; + struct cvmx_pip_gbl_ctl_s { + uint64_t reserved_27_63:37; + uint64_t dsa_grp_tvid:1; + uint64_t dsa_grp_scmd:1; + uint64_t dsa_grp_sid:1; + uint64_t reserved_21_23:3; + uint64_t ring_en:1; + uint64_t reserved_17_19:3; + uint64_t ignrs:1; + uint64_t vs_wqe:1; + uint64_t vs_qos:1; + uint64_t l2_mal:1; + uint64_t tcp_flag:1; + uint64_t l4_len:1; + uint64_t l4_chk:1; + uint64_t l4_prt:1; + uint64_t l4_mal:1; + uint64_t reserved_6_7:2; + uint64_t ip6_eext:2; + uint64_t ip4_opts:1; + uint64_t ip_hop:1; + uint64_t ip_mal:1; + uint64_t ip_chk:1; + } s; + struct cvmx_pip_gbl_ctl_cn30xx { + uint64_t reserved_17_63:47; + uint64_t ignrs:1; + uint64_t vs_wqe:1; + uint64_t vs_qos:1; + uint64_t l2_mal:1; + uint64_t tcp_flag:1; + uint64_t l4_len:1; + uint64_t l4_chk:1; + uint64_t l4_prt:1; + uint64_t l4_mal:1; + uint64_t reserved_6_7:2; + uint64_t ip6_eext:2; + uint64_t ip4_opts:1; + uint64_t ip_hop:1; + uint64_t ip_mal:1; + uint64_t ip_chk:1; + } cn30xx; + struct cvmx_pip_gbl_ctl_cn30xx cn31xx; + struct cvmx_pip_gbl_ctl_cn30xx cn38xx; + struct cvmx_pip_gbl_ctl_cn30xx cn38xxp2; + struct cvmx_pip_gbl_ctl_cn30xx cn50xx; + struct cvmx_pip_gbl_ctl_s cn52xx; + struct cvmx_pip_gbl_ctl_s cn52xxp1; + struct cvmx_pip_gbl_ctl_s cn56xx; + struct cvmx_pip_gbl_ctl_cn56xxp1 { + uint64_t reserved_21_63:43; + uint64_t ring_en:1; + uint64_t reserved_17_19:3; + uint64_t ignrs:1; + uint64_t vs_wqe:1; + uint64_t vs_qos:1; + uint64_t l2_mal:1; + uint64_t tcp_flag:1; + uint64_t l4_len:1; + uint64_t l4_chk:1; + uint64_t l4_prt:1; + uint64_t l4_mal:1; + uint64_t reserved_6_7:2; + uint64_t ip6_eext:2; + uint64_t ip4_opts:1; + uint64_t ip_hop:1; + uint64_t ip_mal:1; + uint64_t ip_chk:1; + } cn56xxp1; + struct cvmx_pip_gbl_ctl_cn30xx cn58xx; + struct cvmx_pip_gbl_ctl_cn30xx cn58xxp1; +}; + +union cvmx_pip_hg_pri_qos { + uint64_t u64; + struct cvmx_pip_hg_pri_qos_s { + uint64_t reserved_11_63:53; + uint64_t qos:3; + uint64_t reserved_6_7:2; + uint64_t pri:6; + } s; + struct cvmx_pip_hg_pri_qos_s cn52xx; + struct cvmx_pip_hg_pri_qos_s cn52xxp1; + struct cvmx_pip_hg_pri_qos_s cn56xx; +}; + +union cvmx_pip_int_en { + uint64_t u64; + struct cvmx_pip_int_en_s { + uint64_t reserved_13_63:51; + uint64_t punyerr:1; + uint64_t lenerr:1; + uint64_t maxerr:1; + uint64_t minerr:1; + uint64_t beperr:1; + uint64_t feperr:1; + uint64_t todoovr:1; + uint64_t skprunt:1; + uint64_t badtag:1; + uint64_t prtnxa:1; + uint64_t bckprs:1; + uint64_t crcerr:1; + uint64_t pktdrp:1; + } s; + struct cvmx_pip_int_en_cn30xx { + uint64_t reserved_9_63:55; + uint64_t beperr:1; + uint64_t feperr:1; + uint64_t todoovr:1; + uint64_t skprunt:1; + uint64_t badtag:1; + uint64_t prtnxa:1; + uint64_t bckprs:1; + uint64_t crcerr:1; + uint64_t pktdrp:1; + } cn30xx; + struct cvmx_pip_int_en_cn30xx cn31xx; + struct cvmx_pip_int_en_cn30xx cn38xx; + struct cvmx_pip_int_en_cn30xx cn38xxp2; + struct cvmx_pip_int_en_cn50xx { + uint64_t reserved_12_63:52; + uint64_t lenerr:1; + uint64_t maxerr:1; + uint64_t minerr:1; + uint64_t beperr:1; + uint64_t feperr:1; + uint64_t todoovr:1; + uint64_t skprunt:1; + uint64_t badtag:1; + uint64_t prtnxa:1; + uint64_t bckprs:1; + uint64_t reserved_1_1:1; + uint64_t pktdrp:1; + } cn50xx; + struct cvmx_pip_int_en_cn52xx { + uint64_t reserved_13_63:51; + uint64_t punyerr:1; + uint64_t lenerr:1; + uint64_t maxerr:1; + uint64_t minerr:1; + uint64_t beperr:1; + uint64_t feperr:1; + uint64_t todoovr:1; + uint64_t skprunt:1; + uint64_t badtag:1; + uint64_t prtnxa:1; + uint64_t bckprs:1; + uint64_t reserved_1_1:1; + uint64_t pktdrp:1; + } cn52xx; + struct cvmx_pip_int_en_cn52xx cn52xxp1; + struct cvmx_pip_int_en_s cn56xx; + struct cvmx_pip_int_en_cn56xxp1 { + uint64_t reserved_12_63:52; + uint64_t lenerr:1; + uint64_t maxerr:1; + uint64_t minerr:1; + uint64_t beperr:1; + uint64_t feperr:1; + uint64_t todoovr:1; + uint64_t skprunt:1; + uint64_t badtag:1; + uint64_t prtnxa:1; + uint64_t bckprs:1; + uint64_t crcerr:1; + uint64_t pktdrp:1; + } cn56xxp1; + struct cvmx_pip_int_en_cn58xx { + uint64_t reserved_13_63:51; + uint64_t punyerr:1; + uint64_t reserved_9_11:3; + uint64_t beperr:1; + uint64_t feperr:1; + uint64_t todoovr:1; + uint64_t skprunt:1; + uint64_t badtag:1; + uint64_t prtnxa:1; + uint64_t bckprs:1; + uint64_t crcerr:1; + uint64_t pktdrp:1; + } cn58xx; + struct cvmx_pip_int_en_cn30xx cn58xxp1; +}; + +union cvmx_pip_int_reg { + uint64_t u64; + struct cvmx_pip_int_reg_s { + uint64_t reserved_13_63:51; + uint64_t punyerr:1; + uint64_t lenerr:1; + uint64_t maxerr:1; + uint64_t minerr:1; + uint64_t beperr:1; + uint64_t feperr:1; + uint64_t todoovr:1; + uint64_t skprunt:1; + uint64_t badtag:1; + uint64_t prtnxa:1; + uint64_t bckprs:1; + uint64_t crcerr:1; + uint64_t pktdrp:1; + } s; + struct cvmx_pip_int_reg_cn30xx { + uint64_t reserved_9_63:55; + uint64_t beperr:1; + uint64_t feperr:1; + uint64_t todoovr:1; + uint64_t skprunt:1; + uint64_t badtag:1; + uint64_t prtnxa:1; + uint64_t bckprs:1; + uint64_t crcerr:1; + uint64_t pktdrp:1; + } cn30xx; + struct cvmx_pip_int_reg_cn30xx cn31xx; + struct cvmx_pip_int_reg_cn30xx cn38xx; + struct cvmx_pip_int_reg_cn30xx cn38xxp2; + struct cvmx_pip_int_reg_cn50xx { + uint64_t reserved_12_63:52; + uint64_t lenerr:1; + uint64_t maxerr:1; + uint64_t minerr:1; + uint64_t beperr:1; + uint64_t feperr:1; + uint64_t todoovr:1; + uint64_t skprunt:1; + uint64_t badtag:1; + uint64_t prtnxa:1; + uint64_t bckprs:1; + uint64_t reserved_1_1:1; + uint64_t pktdrp:1; + } cn50xx; + struct cvmx_pip_int_reg_cn52xx { + uint64_t reserved_13_63:51; + uint64_t punyerr:1; + uint64_t lenerr:1; + uint64_t maxerr:1; + uint64_t minerr:1; + uint64_t beperr:1; + uint64_t feperr:1; + uint64_t todoovr:1; + uint64_t skprunt:1; + uint64_t badtag:1; + uint64_t prtnxa:1; + uint64_t bckprs:1; + uint64_t reserved_1_1:1; + uint64_t pktdrp:1; + } cn52xx; + struct cvmx_pip_int_reg_cn52xx cn52xxp1; + struct cvmx_pip_int_reg_s cn56xx; + struct cvmx_pip_int_reg_cn56xxp1 { + uint64_t reserved_12_63:52; + uint64_t lenerr:1; + uint64_t maxerr:1; + uint64_t minerr:1; + uint64_t beperr:1; + uint64_t feperr:1; + uint64_t todoovr:1; + uint64_t skprunt:1; + uint64_t badtag:1; + uint64_t prtnxa:1; + uint64_t bckprs:1; + uint64_t crcerr:1; + uint64_t pktdrp:1; + } cn56xxp1; + struct cvmx_pip_int_reg_cn58xx { + uint64_t reserved_13_63:51; + uint64_t punyerr:1; + uint64_t reserved_9_11:3; + uint64_t beperr:1; + uint64_t feperr:1; + uint64_t todoovr:1; + uint64_t skprunt:1; + uint64_t badtag:1; + uint64_t prtnxa:1; + uint64_t bckprs:1; + uint64_t crcerr:1; + uint64_t pktdrp:1; + } cn58xx; + struct cvmx_pip_int_reg_cn30xx cn58xxp1; +}; + +union cvmx_pip_ip_offset { + uint64_t u64; + struct cvmx_pip_ip_offset_s { + uint64_t reserved_3_63:61; + uint64_t offset:3; + } s; + struct cvmx_pip_ip_offset_s cn30xx; + struct cvmx_pip_ip_offset_s cn31xx; + struct cvmx_pip_ip_offset_s cn38xx; + struct cvmx_pip_ip_offset_s cn38xxp2; + struct cvmx_pip_ip_offset_s cn50xx; + struct cvmx_pip_ip_offset_s cn52xx; + struct cvmx_pip_ip_offset_s cn52xxp1; + struct cvmx_pip_ip_offset_s cn56xx; + struct cvmx_pip_ip_offset_s cn56xxp1; + struct cvmx_pip_ip_offset_s cn58xx; + struct cvmx_pip_ip_offset_s cn58xxp1; +}; + +union cvmx_pip_prt_cfgx { + uint64_t u64; + struct cvmx_pip_prt_cfgx_s { + uint64_t reserved_53_63:11; + uint64_t pad_len:1; + uint64_t vlan_len:1; + uint64_t lenerr_en:1; + uint64_t maxerr_en:1; + uint64_t minerr_en:1; + uint64_t grp_wat_47:4; + uint64_t qos_wat_47:4; + uint64_t reserved_37_39:3; + uint64_t rawdrp:1; + uint64_t tag_inc:2; + uint64_t dyn_rs:1; + uint64_t inst_hdr:1; + uint64_t grp_wat:4; + uint64_t hg_qos:1; + uint64_t qos:3; + uint64_t qos_wat:4; + uint64_t qos_vsel:1; + uint64_t qos_vod:1; + uint64_t qos_diff:1; + uint64_t qos_vlan:1; + uint64_t reserved_13_15:3; + uint64_t crc_en:1; + uint64_t higig_en:1; + uint64_t dsa_en:1; + uint64_t mode:2; + uint64_t reserved_7_7:1; + uint64_t skip:7; + } s; + struct cvmx_pip_prt_cfgx_cn30xx { + uint64_t reserved_37_63:27; + uint64_t rawdrp:1; + uint64_t tag_inc:2; + uint64_t dyn_rs:1; + uint64_t inst_hdr:1; + uint64_t grp_wat:4; + uint64_t reserved_27_27:1; + uint64_t qos:3; + uint64_t qos_wat:4; + uint64_t reserved_18_19:2; + uint64_t qos_diff:1; + uint64_t qos_vlan:1; + uint64_t reserved_10_15:6; + uint64_t mode:2; + uint64_t reserved_7_7:1; + uint64_t skip:7; + } cn30xx; + struct cvmx_pip_prt_cfgx_cn30xx cn31xx; + struct cvmx_pip_prt_cfgx_cn38xx { + uint64_t reserved_37_63:27; + uint64_t rawdrp:1; + uint64_t tag_inc:2; + uint64_t dyn_rs:1; + uint64_t inst_hdr:1; + uint64_t grp_wat:4; + uint64_t reserved_27_27:1; + uint64_t qos:3; + uint64_t qos_wat:4; + uint64_t reserved_18_19:2; + uint64_t qos_diff:1; + uint64_t qos_vlan:1; + uint64_t reserved_13_15:3; + uint64_t crc_en:1; + uint64_t reserved_10_11:2; + uint64_t mode:2; + uint64_t reserved_7_7:1; + uint64_t skip:7; + } cn38xx; + struct cvmx_pip_prt_cfgx_cn38xx cn38xxp2; + struct cvmx_pip_prt_cfgx_cn50xx { + uint64_t reserved_53_63:11; + uint64_t pad_len:1; + uint64_t vlan_len:1; + uint64_t lenerr_en:1; + uint64_t maxerr_en:1; + uint64_t minerr_en:1; + uint64_t grp_wat_47:4; + uint64_t qos_wat_47:4; + uint64_t reserved_37_39:3; + uint64_t rawdrp:1; + uint64_t tag_inc:2; + uint64_t dyn_rs:1; + uint64_t inst_hdr:1; + uint64_t grp_wat:4; + uint64_t reserved_27_27:1; + uint64_t qos:3; + uint64_t qos_wat:4; + uint64_t reserved_19_19:1; + uint64_t qos_vod:1; + uint64_t qos_diff:1; + uint64_t qos_vlan:1; + uint64_t reserved_13_15:3; + uint64_t crc_en:1; + uint64_t reserved_10_11:2; + uint64_t mode:2; + uint64_t reserved_7_7:1; + uint64_t skip:7; + } cn50xx; + struct cvmx_pip_prt_cfgx_s cn52xx; + struct cvmx_pip_prt_cfgx_s cn52xxp1; + struct cvmx_pip_prt_cfgx_s cn56xx; + struct cvmx_pip_prt_cfgx_cn50xx cn56xxp1; + struct cvmx_pip_prt_cfgx_cn58xx { + uint64_t reserved_37_63:27; + uint64_t rawdrp:1; + uint64_t tag_inc:2; + uint64_t dyn_rs:1; + uint64_t inst_hdr:1; + uint64_t grp_wat:4; + uint64_t reserved_27_27:1; + uint64_t qos:3; + uint64_t qos_wat:4; + uint64_t reserved_19_19:1; + uint64_t qos_vod:1; + uint64_t qos_diff:1; + uint64_t qos_vlan:1; + uint64_t reserved_13_15:3; + uint64_t crc_en:1; + uint64_t reserved_10_11:2; + uint64_t mode:2; + uint64_t reserved_7_7:1; + uint64_t skip:7; + } cn58xx; + struct cvmx_pip_prt_cfgx_cn58xx cn58xxp1; +}; + +union cvmx_pip_prt_tagx { + uint64_t u64; + struct cvmx_pip_prt_tagx_s { + uint64_t reserved_40_63:24; + uint64_t grptagbase:4; + uint64_t grptagmask:4; + uint64_t grptag:1; + uint64_t grptag_mskip:1; + uint64_t tag_mode:2; + uint64_t inc_vs:2; + uint64_t inc_vlan:1; + uint64_t inc_prt_flag:1; + uint64_t ip6_dprt_flag:1; + uint64_t ip4_dprt_flag:1; + uint64_t ip6_sprt_flag:1; + uint64_t ip4_sprt_flag:1; + uint64_t ip6_nxth_flag:1; + uint64_t ip4_pctl_flag:1; + uint64_t ip6_dst_flag:1; + uint64_t ip4_dst_flag:1; + uint64_t ip6_src_flag:1; + uint64_t ip4_src_flag:1; + uint64_t tcp6_tag_type:2; + uint64_t tcp4_tag_type:2; + uint64_t ip6_tag_type:2; + uint64_t ip4_tag_type:2; + uint64_t non_tag_type:2; + uint64_t grp:4; + } s; + struct cvmx_pip_prt_tagx_cn30xx { + uint64_t reserved_40_63:24; + uint64_t grptagbase:4; + uint64_t grptagmask:4; + uint64_t grptag:1; + uint64_t reserved_30_30:1; + uint64_t tag_mode:2; + uint64_t inc_vs:2; + uint64_t inc_vlan:1; + uint64_t inc_prt_flag:1; + uint64_t ip6_dprt_flag:1; + uint64_t ip4_dprt_flag:1; + uint64_t ip6_sprt_flag:1; + uint64_t ip4_sprt_flag:1; + uint64_t ip6_nxth_flag:1; + uint64_t ip4_pctl_flag:1; + uint64_t ip6_dst_flag:1; + uint64_t ip4_dst_flag:1; + uint64_t ip6_src_flag:1; + uint64_t ip4_src_flag:1; + uint64_t tcp6_tag_type:2; + uint64_t tcp4_tag_type:2; + uint64_t ip6_tag_type:2; + uint64_t ip4_tag_type:2; + uint64_t non_tag_type:2; + uint64_t grp:4; + } cn30xx; + struct cvmx_pip_prt_tagx_cn30xx cn31xx; + struct cvmx_pip_prt_tagx_cn30xx cn38xx; + struct cvmx_pip_prt_tagx_cn30xx cn38xxp2; + struct cvmx_pip_prt_tagx_s cn50xx; + struct cvmx_pip_prt_tagx_s cn52xx; + struct cvmx_pip_prt_tagx_s cn52xxp1; + struct cvmx_pip_prt_tagx_s cn56xx; + struct cvmx_pip_prt_tagx_s cn56xxp1; + struct cvmx_pip_prt_tagx_cn30xx cn58xx; + struct cvmx_pip_prt_tagx_cn30xx cn58xxp1; +}; + +union cvmx_pip_qos_diffx { + uint64_t u64; + struct cvmx_pip_qos_diffx_s { + uint64_t reserved_3_63:61; + uint64_t qos:3; + } s; + struct cvmx_pip_qos_diffx_s cn30xx; + struct cvmx_pip_qos_diffx_s cn31xx; + struct cvmx_pip_qos_diffx_s cn38xx; + struct cvmx_pip_qos_diffx_s cn38xxp2; + struct cvmx_pip_qos_diffx_s cn50xx; + struct cvmx_pip_qos_diffx_s cn52xx; + struct cvmx_pip_qos_diffx_s cn52xxp1; + struct cvmx_pip_qos_diffx_s cn56xx; + struct cvmx_pip_qos_diffx_s cn56xxp1; + struct cvmx_pip_qos_diffx_s cn58xx; + struct cvmx_pip_qos_diffx_s cn58xxp1; +}; + +union cvmx_pip_qos_vlanx { + uint64_t u64; + struct cvmx_pip_qos_vlanx_s { + uint64_t reserved_7_63:57; + uint64_t qos1:3; + uint64_t reserved_3_3:1; + uint64_t qos:3; + } s; + struct cvmx_pip_qos_vlanx_cn30xx { + uint64_t reserved_3_63:61; + uint64_t qos:3; + } cn30xx; + struct cvmx_pip_qos_vlanx_cn30xx cn31xx; + struct cvmx_pip_qos_vlanx_cn30xx cn38xx; + struct cvmx_pip_qos_vlanx_cn30xx cn38xxp2; + struct cvmx_pip_qos_vlanx_cn30xx cn50xx; + struct cvmx_pip_qos_vlanx_s cn52xx; + struct cvmx_pip_qos_vlanx_s cn52xxp1; + struct cvmx_pip_qos_vlanx_s cn56xx; + struct cvmx_pip_qos_vlanx_cn30xx cn56xxp1; + struct cvmx_pip_qos_vlanx_cn30xx cn58xx; + struct cvmx_pip_qos_vlanx_cn30xx cn58xxp1; +}; + +union cvmx_pip_qos_watchx { + uint64_t u64; + struct cvmx_pip_qos_watchx_s { + uint64_t reserved_48_63:16; + uint64_t mask:16; + uint64_t reserved_28_31:4; + uint64_t grp:4; + uint64_t reserved_23_23:1; + uint64_t qos:3; + uint64_t reserved_19_19:1; + uint64_t match_type:3; + uint64_t match_value:16; + } s; + struct cvmx_pip_qos_watchx_cn30xx { + uint64_t reserved_48_63:16; + uint64_t mask:16; + uint64_t reserved_28_31:4; + uint64_t grp:4; + uint64_t reserved_23_23:1; + uint64_t qos:3; + uint64_t reserved_18_19:2; + uint64_t match_type:2; + uint64_t match_value:16; + } cn30xx; + struct cvmx_pip_qos_watchx_cn30xx cn31xx; + struct cvmx_pip_qos_watchx_cn30xx cn38xx; + struct cvmx_pip_qos_watchx_cn30xx cn38xxp2; + struct cvmx_pip_qos_watchx_s cn50xx; + struct cvmx_pip_qos_watchx_s cn52xx; + struct cvmx_pip_qos_watchx_s cn52xxp1; + struct cvmx_pip_qos_watchx_s cn56xx; + struct cvmx_pip_qos_watchx_s cn56xxp1; + struct cvmx_pip_qos_watchx_cn30xx cn58xx; + struct cvmx_pip_qos_watchx_cn30xx cn58xxp1; +}; + +union cvmx_pip_raw_word { + uint64_t u64; + struct cvmx_pip_raw_word_s { + uint64_t reserved_56_63:8; + uint64_t word:56; + } s; + struct cvmx_pip_raw_word_s cn30xx; + struct cvmx_pip_raw_word_s cn31xx; + struct cvmx_pip_raw_word_s cn38xx; + struct cvmx_pip_raw_word_s cn38xxp2; + struct cvmx_pip_raw_word_s cn50xx; + struct cvmx_pip_raw_word_s cn52xx; + struct cvmx_pip_raw_word_s cn52xxp1; + struct cvmx_pip_raw_word_s cn56xx; + struct cvmx_pip_raw_word_s cn56xxp1; + struct cvmx_pip_raw_word_s cn58xx; + struct cvmx_pip_raw_word_s cn58xxp1; +}; + +union cvmx_pip_sft_rst { + uint64_t u64; + struct cvmx_pip_sft_rst_s { + uint64_t reserved_1_63:63; + uint64_t rst:1; + } s; + struct cvmx_pip_sft_rst_s cn30xx; + struct cvmx_pip_sft_rst_s cn31xx; + struct cvmx_pip_sft_rst_s cn38xx; + struct cvmx_pip_sft_rst_s cn50xx; + struct cvmx_pip_sft_rst_s cn52xx; + struct cvmx_pip_sft_rst_s cn52xxp1; + struct cvmx_pip_sft_rst_s cn56xx; + struct cvmx_pip_sft_rst_s cn56xxp1; + struct cvmx_pip_sft_rst_s cn58xx; + struct cvmx_pip_sft_rst_s cn58xxp1; +}; + +union cvmx_pip_stat0_prtx { + uint64_t u64; + struct cvmx_pip_stat0_prtx_s { + uint64_t drp_pkts:32; + uint64_t drp_octs:32; + } s; + struct cvmx_pip_stat0_prtx_s cn30xx; + struct cvmx_pip_stat0_prtx_s cn31xx; + struct cvmx_pip_stat0_prtx_s cn38xx; + struct cvmx_pip_stat0_prtx_s cn38xxp2; + struct cvmx_pip_stat0_prtx_s cn50xx; + struct cvmx_pip_stat0_prtx_s cn52xx; + struct cvmx_pip_stat0_prtx_s cn52xxp1; + struct cvmx_pip_stat0_prtx_s cn56xx; + struct cvmx_pip_stat0_prtx_s cn56xxp1; + struct cvmx_pip_stat0_prtx_s cn58xx; + struct cvmx_pip_stat0_prtx_s cn58xxp1; +}; + +union cvmx_pip_stat1_prtx { + uint64_t u64; + struct cvmx_pip_stat1_prtx_s { + uint64_t reserved_48_63:16; + uint64_t octs:48; + } s; + struct cvmx_pip_stat1_prtx_s cn30xx; + struct cvmx_pip_stat1_prtx_s cn31xx; + struct cvmx_pip_stat1_prtx_s cn38xx; + struct cvmx_pip_stat1_prtx_s cn38xxp2; + struct cvmx_pip_stat1_prtx_s cn50xx; + struct cvmx_pip_stat1_prtx_s cn52xx; + struct cvmx_pip_stat1_prtx_s cn52xxp1; + struct cvmx_pip_stat1_prtx_s cn56xx; + struct cvmx_pip_stat1_prtx_s cn56xxp1; + struct cvmx_pip_stat1_prtx_s cn58xx; + struct cvmx_pip_stat1_prtx_s cn58xxp1; +}; + +union cvmx_pip_stat2_prtx { + uint64_t u64; + struct cvmx_pip_stat2_prtx_s { + uint64_t pkts:32; + uint64_t raw:32; + } s; + struct cvmx_pip_stat2_prtx_s cn30xx; + struct cvmx_pip_stat2_prtx_s cn31xx; + struct cvmx_pip_stat2_prtx_s cn38xx; + struct cvmx_pip_stat2_prtx_s cn38xxp2; + struct cvmx_pip_stat2_prtx_s cn50xx; + struct cvmx_pip_stat2_prtx_s cn52xx; + struct cvmx_pip_stat2_prtx_s cn52xxp1; + struct cvmx_pip_stat2_prtx_s cn56xx; + struct cvmx_pip_stat2_prtx_s cn56xxp1; + struct cvmx_pip_stat2_prtx_s cn58xx; + struct cvmx_pip_stat2_prtx_s cn58xxp1; +}; + +union cvmx_pip_stat3_prtx { + uint64_t u64; + struct cvmx_pip_stat3_prtx_s { + uint64_t bcst:32; + uint64_t mcst:32; + } s; + struct cvmx_pip_stat3_prtx_s cn30xx; + struct cvmx_pip_stat3_prtx_s cn31xx; + struct cvmx_pip_stat3_prtx_s cn38xx; + struct cvmx_pip_stat3_prtx_s cn38xxp2; + struct cvmx_pip_stat3_prtx_s cn50xx; + struct cvmx_pip_stat3_prtx_s cn52xx; + struct cvmx_pip_stat3_prtx_s cn52xxp1; + struct cvmx_pip_stat3_prtx_s cn56xx; + struct cvmx_pip_stat3_prtx_s cn56xxp1; + struct cvmx_pip_stat3_prtx_s cn58xx; + struct cvmx_pip_stat3_prtx_s cn58xxp1; +}; + +union cvmx_pip_stat4_prtx { + uint64_t u64; + struct cvmx_pip_stat4_prtx_s { + uint64_t h65to127:32; + uint64_t h64:32; + } s; + struct cvmx_pip_stat4_prtx_s cn30xx; + struct cvmx_pip_stat4_prtx_s cn31xx; + struct cvmx_pip_stat4_prtx_s cn38xx; + struct cvmx_pip_stat4_prtx_s cn38xxp2; + struct cvmx_pip_stat4_prtx_s cn50xx; + struct cvmx_pip_stat4_prtx_s cn52xx; + struct cvmx_pip_stat4_prtx_s cn52xxp1; + struct cvmx_pip_stat4_prtx_s cn56xx; + struct cvmx_pip_stat4_prtx_s cn56xxp1; + struct cvmx_pip_stat4_prtx_s cn58xx; + struct cvmx_pip_stat4_prtx_s cn58xxp1; +}; + +union cvmx_pip_stat5_prtx { + uint64_t u64; + struct cvmx_pip_stat5_prtx_s { + uint64_t h256to511:32; + uint64_t h128to255:32; + } s; + struct cvmx_pip_stat5_prtx_s cn30xx; + struct cvmx_pip_stat5_prtx_s cn31xx; + struct cvmx_pip_stat5_prtx_s cn38xx; + struct cvmx_pip_stat5_prtx_s cn38xxp2; + struct cvmx_pip_stat5_prtx_s cn50xx; + struct cvmx_pip_stat5_prtx_s cn52xx; + struct cvmx_pip_stat5_prtx_s cn52xxp1; + struct cvmx_pip_stat5_prtx_s cn56xx; + struct cvmx_pip_stat5_prtx_s cn56xxp1; + struct cvmx_pip_stat5_prtx_s cn58xx; + struct cvmx_pip_stat5_prtx_s cn58xxp1; +}; + +union cvmx_pip_stat6_prtx { + uint64_t u64; + struct cvmx_pip_stat6_prtx_s { + uint64_t h1024to1518:32; + uint64_t h512to1023:32; + } s; + struct cvmx_pip_stat6_prtx_s cn30xx; + struct cvmx_pip_stat6_prtx_s cn31xx; + struct cvmx_pip_stat6_prtx_s cn38xx; + struct cvmx_pip_stat6_prtx_s cn38xxp2; + struct cvmx_pip_stat6_prtx_s cn50xx; + struct cvmx_pip_stat6_prtx_s cn52xx; + struct cvmx_pip_stat6_prtx_s cn52xxp1; + struct cvmx_pip_stat6_prtx_s cn56xx; + struct cvmx_pip_stat6_prtx_s cn56xxp1; + struct cvmx_pip_stat6_prtx_s cn58xx; + struct cvmx_pip_stat6_prtx_s cn58xxp1; +}; + +union cvmx_pip_stat7_prtx { + uint64_t u64; + struct cvmx_pip_stat7_prtx_s { + uint64_t fcs:32; + uint64_t h1519:32; + } s; + struct cvmx_pip_stat7_prtx_s cn30xx; + struct cvmx_pip_stat7_prtx_s cn31xx; + struct cvmx_pip_stat7_prtx_s cn38xx; + struct cvmx_pip_stat7_prtx_s cn38xxp2; + struct cvmx_pip_stat7_prtx_s cn50xx; + struct cvmx_pip_stat7_prtx_s cn52xx; + struct cvmx_pip_stat7_prtx_s cn52xxp1; + struct cvmx_pip_stat7_prtx_s cn56xx; + struct cvmx_pip_stat7_prtx_s cn56xxp1; + struct cvmx_pip_stat7_prtx_s cn58xx; + struct cvmx_pip_stat7_prtx_s cn58xxp1; +}; + +union cvmx_pip_stat8_prtx { + uint64_t u64; + struct cvmx_pip_stat8_prtx_s { + uint64_t frag:32; + uint64_t undersz:32; + } s; + struct cvmx_pip_stat8_prtx_s cn30xx; + struct cvmx_pip_stat8_prtx_s cn31xx; + struct cvmx_pip_stat8_prtx_s cn38xx; + struct cvmx_pip_stat8_prtx_s cn38xxp2; + struct cvmx_pip_stat8_prtx_s cn50xx; + struct cvmx_pip_stat8_prtx_s cn52xx; + struct cvmx_pip_stat8_prtx_s cn52xxp1; + struct cvmx_pip_stat8_prtx_s cn56xx; + struct cvmx_pip_stat8_prtx_s cn56xxp1; + struct cvmx_pip_stat8_prtx_s cn58xx; + struct cvmx_pip_stat8_prtx_s cn58xxp1; +}; + +un