From macro@codesourcery.com Sun Mar 1 00:12:43 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 01 Mar 2009 00:12:46 +0000 (GMT) Received: from mail.codesourcery.com ([65.74.133.4]:44168 "EHLO mail.codesourcery.com") by ftp.linux-mips.org with ESMTP id S20809047AbZCAAMn (ORCPT ); Sun, 1 Mar 2009 00:12:43 +0000 Received: (qmail 15788 invoked from network); 1 Mar 2009 00:12:37 -0000 Received: from unknown (HELO pl.orcam.me.uk) (macro@127.0.0.2) by mail.codesourcery.com with ESMTPA; 1 Mar 2009 00:12:37 -0000 Date: Sun, 1 Mar 2009 00:12:25 +0000 (GMT) From: "Maciej W. Rozycki" To: Ralf Baechle , linux-mips@linux-mips.org cc: libc-ports@sourceware.org, "Maciej W. Rozycki" Subject: [PATCH, RFC] MIPS: Implement the getcontext API Message-ID: User-Agent: Alpine 1.10 (DEB 962 2008-03-14) MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21991 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: macro@codesourcery.com Precedence: bulk X-list: linux-mips Hello, Here is code to implement the getcontext API for MIPS. This glibc patch is sent to the linux-mips mailing list, because it makes use of an internal syscall which has not been designated as a part of the public ABI. I am writing to request this syscall to become fixed as a part of the ABI or to seek for an alternative. See below for the rationale. The code should speak for itself. ;) There are two points to note though. The requirement to be able to call setcontext() or swapcontext() on a context obtained from a signal handler has the implication of the need to use the sigreturn(2) syscall (RT signal syscalls are actually used throughout to cover the full set of signals and I have chosen to use them unconditionally as any remotely modern Linux will have supported them). There are two reasons for doing this. First, the full set of registers has to be restored in this case as signals can arrive at random points (OTOH, contexts saved by getcontext(), swapcontext() or created with makecontext() only need to restore call-saved or argument registers as appropriate) and on MIPS it cannot be done in the userland. This is because at least one register is required to perform the final jump to restore the PC and the register cannot be restored in the jump's delay slot because the ABI does not reserve a red zone on the stack below the SP (and space above the SP cannot be used for obvious reasons). Second, only the kernel may restore the DSP registers without a lot of hassle, i.e. fiddling with the SIGILL signal in case the ASE is not implemented. Given the first reason above this is largely irrelevant, but even if a way was found to restore otherwise the full user state without a need to go through sigreturn(2), this problem would still remain. Given the above the implementation was written such that for contexts obtained from a signal handler sigreturn(2) is used and for all the other ones siprocmask(2) is used to restore the signal mask and appropriate registers are restored within setcontext() itself. Again, this has to be done this way, because a full context required for sigreturn(2) cannot be easily reconstructed by user code. There are two potential issues with the use of sigreturn(2) however. First, a stack frame of a specific layout has to be created. The frame is roughly described by the structure introduced in kernel_rt_sigframe.h (the structure is only used to calculate offsets in ucontext_i.sym). The description has to be rough, because the exact layout of the structure depends on the cache line size specified in the kernel configuration. This is not much of the concern for setcontext(), because the variable part is beyond the area the function accesses. The kernel only checks whether the whole span of the structure is accessible from sigreturn(2), so all that setcontext() has to do is to reserve enough space on the stack. The maximum line size currently supported (which is 128 bytes) is used, anticipating it will not ever grow. The complication of the matter may sound alerting and rightfully so as sigreturn(2) currently is not the part of an official ABI. It is normally only invoked from a signal return trampoline created by the kernel itself. There is apparently some knowledge of the layout of the signal stack frame in GDB already though and the way the layout of the signal stack frame evolved shows binary compatibility was a concern here in the past. Also there is other data included in the frame beside the context. It is currently not used by sigreturn(2) though. The other issue is setcontext(), etc. have to mark contexts created by themselves somehow so as to differentiate them from ones obtained from a signal handler. I have chosen to reuse the slot for the $zero register, which is normally... zero. ;) As the register is always zero, so will be a context passed to a signal handler. The functions make use of this observation and store one instead. Then setcontext() examines the contents of the slot and selects between sigreturn(2) (if zero) and manual restoration (if one). The danger here is contents of a context are meant not to be really interpreted by user software and may potentially change in the future. The conclusion is what I am requesting is to get the structure of the stack frame used by sigreturn(2) fixed in its current form and make sure the syscall only ever uses data from the ucontext_t structure within. A new syscall would have to be introduced if the kernel required a change in the way sigreturn(2) behaves in the future. For the purpose of glibc the structure of the stack frame is defined in the kernel_rt_sigframe.h header provided with the patch. Furthermore I am requesting that the kernel recognises the special meaning of the value of one stored in the slot designated for the $zero register and never places such a value itself there. A few other Linux ports already use sigreturn(2) as the underlying mechanism for their setcontext() implementation one way or another so such a use of the syscall for the MIPS port would follow an already established practice. 2009-03-01 Maciej W. Rozycki * sysdeps/unix/sysv/linux/mips/getcontext.S: New file. * sysdeps/unix/sysv/linux/mips/makecontext.S: New file. * sysdeps/unix/sysv/linux/mips/setcontext.S: New file. * sysdeps/unix/sysv/linux/mips/swapcontext.S: New file. * sysdeps/unix/sysv/linux/mips/sys/ucontext.h (mcontext_t): Update comment. * sysdeps/unix/sysv/linux/mips/kernel_rt_sigframe.h: New file. * sysdeps/unix/sysv/linux/mips/ucontext_i.sym: New file. * sysdeps/unix/sysv/linux/mips/Makefile (gen-as-const-headers): Add ucontext_i.sym. The changes themselves were tested with an almost current head of glibc (recent changes to introduce psiginfo broke compilation), specifically a snapshot from Feb 3rd, and the current head of glibc-ports. Testing was done by running the glibc testsuite for the n64, n32 and o32 ABIs in the little-endian configuration. All the included getcontext tests passed as did two new ones I prepared myself to cover cases not already tested. I will submit the new test cases separately. A separate patch to provide cooked FP register names is required to build this code for the new ABIs. I will send it shortly. Maciej glibc-ports-2.9.90-20090226-mips-ucontext-14.patch diff -up --recursive --new-file glibc-ports-2.9.90-20090226.macro/sysdeps/unix/sysv/linux/mips/Makefile glibc-ports-2.9.90-20090226/sysdeps/unix/sysv/linux/mips/Makefile --- glibc-ports-2.9.90-20090226.macro/sysdeps/unix/sysv/linux/mips/Makefile 2009-01-27 15:32:55.000000000 +0000 +++ glibc-ports-2.9.90-20090226/sysdeps/unix/sysv/linux/mips/Makefile 2009-02-26 18:58:49.000000000 +0000 @@ -135,3 +135,7 @@ sysdep_routines += dl-static sysdep-rtld-routines += dl-static endif endif + +ifeq ($(subdir),stdlib) +gen-as-const-headers += ucontext_i.sym +endif diff -up --recursive --new-file glibc-ports-2.9.90-20090226.macro/sysdeps/unix/sysv/linux/mips/getcontext.S glibc-ports-2.9.90-20090226/sysdeps/unix/sysv/linux/mips/getcontext.S --- glibc-ports-2.9.90-20090226.macro/sysdeps/unix/sysv/linux/mips/getcontext.S 1970-01-01 00:00:00.000000000 +0000 +++ glibc-ports-2.9.90-20090226/sysdeps/unix/sysv/linux/mips/getcontext.S 2009-02-26 19:00:33.000000000 +0000 @@ -0,0 +1,149 @@ +/* Save current context. + Copyright (C) 2009 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Maciej W. Rozycki . + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, write to the Free + Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA + 02110-1301, USA. */ + +#include +#include +#include +#include + +#include "ucontext_i.h" + +/* int getcontext (ucontext_t *ucp) */ + + .text +LOCALSZ = 0 +MASK = 0x00000000 +#ifdef __PIC__ +LOCALSZ = 1 /* save gp */ +# if _MIPS_SIM != _ABIO32 +MASK = 0x10000000 +# endif +#endif +FRAMESZ = ((LOCALSZ * SZREG) + ALSZ) & ALMASK +GPOFF = FRAMESZ - (1 * SZREG) + +NESTED (__getcontext, FRAMESZ, ra) + .mask MASK, 0 + .fmask 0x00000000, 0 + +#ifdef __PIC__ + SETUP_GP + + move a2, sp +# define _SP a2 + +# if _MIPS_SIM != _ABIO32 + move a3, gp +# define _GP a3 +# endif + + PTR_ADDIU sp, -FRAMESZ + SETUP_GP64 (GPOFF, __getcontext) + SAVE_GP (GPOFF) + +#else /* ! __PIC__ */ +# define _SP sp +# define _GP gp + +#endif /* ! __PIC__ */ + +#ifdef PROF + .set noat + move AT, ra + jal _mcount + .set at +#endif + + /* Store a magic flag. */ + li v1, 1 + REG_S v1, (0 * SZREG + MCONTEXT_GREGS)(a0) /* zero */ + + REG_S s0, (16 * SZREG + MCONTEXT_GREGS)(a0) + REG_S s1, (17 * SZREG + MCONTEXT_GREGS)(a0) + REG_S s2, (18 * SZREG + MCONTEXT_GREGS)(a0) + REG_S s3, (19 * SZREG + MCONTEXT_GREGS)(a0) + REG_S s4, (20 * SZREG + MCONTEXT_GREGS)(a0) + REG_S s5, (21 * SZREG + MCONTEXT_GREGS)(a0) + REG_S s6, (22 * SZREG + MCONTEXT_GREGS)(a0) + REG_S s7, (23 * SZREG + MCONTEXT_GREGS)(a0) +#if ! defined (__PIC__) || _MIPS_SIM != _ABIO32 + REG_S _GP, (28 * SZREG + MCONTEXT_GREGS)(a0) +#endif + REG_S _SP, (29 * SZREG + MCONTEXT_GREGS)(a0) + REG_S fp, (30 * SZREG + MCONTEXT_GREGS)(a0) + REG_S ra, (31 * SZREG + MCONTEXT_GREGS)(a0) + REG_S ra, MCONTEXT_PC(a0) + +#ifdef __mips_hard_float +# if _MIPS_SIM == _ABI64 + s.d fs0, (24 * SZREG + MCONTEXT_FPREGS)(a0) + s.d fs1, (25 * SZREG + MCONTEXT_FPREGS)(a0) + s.d fs2, (26 * SZREG + MCONTEXT_FPREGS)(a0) + s.d fs3, (27 * SZREG + MCONTEXT_FPREGS)(a0) + s.d fs4, (28 * SZREG + MCONTEXT_FPREGS)(a0) + s.d fs5, (29 * SZREG + MCONTEXT_FPREGS)(a0) + s.d fs6, (30 * SZREG + MCONTEXT_FPREGS)(a0) + s.d fs7, (31 * SZREG + MCONTEXT_FPREGS)(a0) + +# else /* _MIPS_SIM != _ABI64 */ + s.d fs0, (20 * SZREG + MCONTEXT_FPREGS)(a0) + s.d fs1, (22 * SZREG + MCONTEXT_FPREGS)(a0) + s.d fs2, (24 * SZREG + MCONTEXT_FPREGS)(a0) + s.d fs3, (26 * SZREG + MCONTEXT_FPREGS)(a0) + s.d fs4, (28 * SZREG + MCONTEXT_FPREGS)(a0) + s.d fs5, (30 * SZREG + MCONTEXT_FPREGS)(a0) + +# endif /* _MIPS_SIM != _ABI64 */ + + cfc1 v1, fcr31 + sw v1, MCONTEXT_FPC_CSR(a0) +#endif /* __mips_hard_float */ + +/* rt_sigprocmask (SIG_BLOCK, NULL, &ucp->uc_sigmask, _NSIG8) */ + li a3, _NSIG8 + PTR_ADDU a2, a0, UCONTEXT_SIGMASK + move a1, zero + li a0, SIG_BLOCK + + li v0, SYS_ify (rt_sigprocmask) + syscall + bnez a3, 99f + +#ifdef __PIC__ + RESTORE_GP64 + PTR_ADDIU sp, FRAMESZ +#endif + move v0, zero + jr ra + +99: +#ifdef __PIC__ + PTR_LA t9, JUMPTARGET (__syscall_error) + RESTORE_GP64 + PTR_ADDIU sp, FRAMESZ + jr t9 + +#else /* ! __PIC__ */ + + j JUMPTARGET (__syscall_error) +#endif /* ! __PIC__ */ +PSEUDO_END (__getcontext) + +weak_alias (__getcontext, getcontext) diff -up --recursive --new-file glibc-ports-2.9.90-20090226.macro/sysdeps/unix/sysv/linux/mips/kernel_rt_sigframe.h glibc-ports-2.9.90-20090226/sysdeps/unix/sysv/linux/mips/kernel_rt_sigframe.h --- glibc-ports-2.9.90-20090226.macro/sysdeps/unix/sysv/linux/mips/kernel_rt_sigframe.h 1970-01-01 00:00:00.000000000 +0000 +++ glibc-ports-2.9.90-20090226/sysdeps/unix/sysv/linux/mips/kernel_rt_sigframe.h 2009-02-26 00:00:00.000000000 +0000 @@ -0,0 +1,10 @@ +/* Linux kernel RT signal frame. */ +typedef struct kernel_rt_sigframe + { + uint32_t rs_ass[4]; + uint32_t rs_code[2]; + struct siginfo rs_info; + struct ucontext rs_uc; + uint32_t rs_altcode[8] __attribute__ ((__aligned__ (1 << 7))); + } +kernel_rt_sigframe_t; diff -up --recursive --new-file glibc-ports-2.9.90-20090226.macro/sysdeps/unix/sysv/linux/mips/makecontext.S glibc-ports-2.9.90-20090226/sysdeps/unix/sysv/linux/mips/makecontext.S --- glibc-ports-2.9.90-20090226.macro/sysdeps/unix/sysv/linux/mips/makecontext.S 1970-01-01 00:00:00.000000000 +0000 +++ glibc-ports-2.9.90-20090226/sysdeps/unix/sysv/linux/mips/makecontext.S 2009-02-26 00:00:00.000000000 +0000 @@ -0,0 +1,189 @@ +/* Modify saved context. + Copyright (C) 2009 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Maciej W. Rozycki . + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, write to the Free + Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA + 02110-1301, USA. */ + +#include +#include +#include +#include + +#include "ucontext_i.h" + +/* int makecontext (ucontext_t *ucp, (void *func) (), int argc, ...) */ + + .text +LOCALSZ = 0 +ARGSZ = 0 +MASK = 0x00000000 +#ifdef __PIC__ +LOCALSZ = 1 /* save gp */ +#endif +#if _MIPS_SIM != _ABIO32 +ARGSZ = 5 /* save a3-a7 */ +# ifdef __PIC__ +MASK = 0x10000000 +# endif +#endif +FRAMESZ = (((ARGSZ + LOCALSZ) * SZREG) + ALSZ) & ALMASK +GPOFF = FRAMESZ - ((ARGSZ + 1) * SZREG) +#if _MIPS_SIM != _ABIO32 +A3OFF = FRAMESZ - (5 * SZREG) /* callee-allocated */ +A4OFF = FRAMESZ - (4 * SZREG) +A5OFF = FRAMESZ - (3 * SZREG) +A6OFF = FRAMESZ - (2 * SZREG) +A7OFF = FRAMESZ - (1 * SZREG) +NARGREGS = 8 +#else +A3OFF = FRAMESZ + (3 * SZREG) /* caller-allocated */ +NARGREGS = 4 +#endif + +NESTED (__makecontext, FRAMESZ, ra) + .mask MASK, -(ARGSZ * SZREG) + .fmask 0x00000000, 0 + +98: +#ifdef __PIC__ + SETUP_GP +#endif + + PTR_ADDIU sp, -FRAMESZ + +#ifdef __PIC__ + SETUP_GP64 (GPOFF, __makecontext) + SAVE_GP (GPOFF) +#endif + +#ifdef PROF + .set noat + move AT, ra + jal _mcount + .set at +#endif + + /* Store args to be passed. */ + REG_S a3, A3OFF(sp) +#if _MIPS_SIM != _ABIO32 + REG_S a4, A4OFF(sp) + REG_S a5, A5OFF(sp) + REG_S a6, A6OFF(sp) + REG_S a7, A7OFF(sp) +#endif + + /* Store a magic flag. */ + li v1, 1 + REG_S v1, (0 * SZREG + MCONTEXT_GREGS)(a0) /* zero */ + + /* Set up the stack. */ + PTR_L t0, STACK_SP(a0) + PTR_L t2, STACK_SIZE(a0) + PTR_ADDIU t1, sp, A3OFF + PTR_ADDU t0, t2 + and t0, ALMASK + blez a2, 2f /* no arguments */ + + /* Store register arguments. */ + PTR_ADDIU t2, a0, MCONTEXT_GREGS + 4 * SZREG + move t3, zero +0: + addiu t3, 1 + REG_L v1, (t1) + PTR_ADDIU t1, SZREG + REG_S v1, (t2) + PTR_ADDIU t2, SZREG + bgeu t3, a2, 2f /* all done */ + bltu t3, NARGREGS, 0b /* next */ + + /* Make room for stack arguments. */ + PTR_SUBU t2, a2, t3 + PTR_SLL t2, 3 + PTR_SUBU t0, t2 + and t0, ALMASK + + /* Store stack arguments. */ + move t2, t0 +1: + addiu t3, 1 + REG_L v1, (t1) + PTR_ADDIU t1, SZREG + REG_S v1, (t2) + PTR_ADDIU t2, SZREG + bltu t3, a2, 1b /* next */ + +2: +#if _MIPS_SIM == _ABIO32 + /* Make room for a0-a3 storage. */ + PTR_ADDIU t0, -(NARGSAVE * SZREG) +#endif + PTR_L v1, UCONTEXT_LINK(a0) +#ifdef __PIC__ + PTR_ADDIU t9, 99f - 98b +#else + PTR_LA t9, 99f +#endif + REG_S t0, (29 * SZREG + MCONTEXT_GREGS)(a0) /* sp */ + REG_S v1, (16 * SZREG + MCONTEXT_GREGS)(a0) /* s0 */ +#ifdef __PIC__ + REG_S gp, (17 * SZREG + MCONTEXT_GREGS)(a0) /* s1 */ +#endif + REG_S t9, (31 * SZREG + MCONTEXT_GREGS)(a0) /* ra */ + REG_S a1, MCONTEXT_PC(a0) + +#ifdef __PIC__ + RESTORE_GP64 + PTR_ADDIU sp, FRAMESZ +#endif + jr ra + +99: +#ifdef __PIC__ + move gp, s1 +#endif + move a0, zero + beqz s0, 0f + + /* setcontext (ucp) */ + move a0, s0 +#ifdef __PIC__ + PTR_LA t9, JUMPTARGET (__setcontext) + jalr t9 +# if _MIPS_SIM == _ABIO32 + move gp, s1 +# endif +#else + jal JUMPTARGET (__setcontext) +#endif + move a0, v0 + +0: + /* exit (a0) */ +#ifdef __PIC__ + PTR_LA t9, HIDDEN_JUMPTARGET (exit) + jalr t9 +#else + jal HIDDEN_JUMPTARGET (exit) +#endif + + /* You don't exist, you won't feel anything. */ +1: + lb zero, (zero) + b 1b +PSEUDO_END (__makecontext) + +weak_alias (__makecontext, makecontext) diff -up --recursive --new-file glibc-ports-2.9.90-20090226.macro/sysdeps/unix/sysv/linux/mips/setcontext.S glibc-ports-2.9.90-20090226/sysdeps/unix/sysv/linux/mips/setcontext.S --- glibc-ports-2.9.90-20090226.macro/sysdeps/unix/sysv/linux/mips/setcontext.S 1970-01-01 00:00:00.000000000 +0000 +++ glibc-ports-2.9.90-20090226/sysdeps/unix/sysv/linux/mips/setcontext.S 2009-02-28 13:43:46.000000000 +0000 @@ -0,0 +1,192 @@ +/* Set current context. + Copyright (C) 2009 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Maciej W. Rozycki . + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, write to the Free + Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA + 02110-1301, USA. */ + +#include +#include +#include +#include + +#include "ucontext_i.h" + +/* int setcontext (const ucontext_t *ucp) */ + + .text +LOCALSZ = 0 +ARGSZ = 0 +MASK = 0x00000000 +#ifdef __PIC__ +LOCALSZ = 1 /* save gp */ +#endif +#if _MIPS_SIM != _ABIO32 +ARGSZ = 1 /* save a0 */ +# ifdef __PIC__ +MASK = 0x10000000 +# endif +#endif +FRAMESZ = (((ARGSZ + LOCALSZ) * SZREG) + ALSZ) & ALMASK +GPOFF = FRAMESZ - ((ARGSZ + 1) * SZREG) +#if _MIPS_SIM != _ABIO32 +A0OFF = FRAMESZ - (1 * SZREG) /* callee-allocated */ +#else +A0OFF = FRAMESZ + (0 * SZREG) /* caller-allocated */ +#endif + +NESTED (__setcontext, FRAMESZ, ra) + .mask MASK, -(ARGSZ * SZREG) + .fmask 0x00000000, 0 + +#ifdef __PIC__ + SETUP_GP +#endif + + PTR_ADDIU sp, -FRAMESZ + +#ifdef __PIC__ + SETUP_GP64 (GPOFF, __setcontext) + SAVE_GP (GPOFF) +#endif + +#ifdef PROF + .set noat + move AT, ra + jal _mcount + .set at +#endif + + /* Check for the magic flag. */ + li v0, 1 + REG_L v1, (0 * SZREG + MCONTEXT_GREGS)(a0) /* zero */ + bne v0, v1, 98f + + REG_S a0, A0OFF(sp) + +/* rt_sigprocmask (SIG_SETMASK, &ucp->uc_sigmask, NULL, _NSIG8) */ + li a3, _NSIG8 + move a2, zero + PTR_ADDU a1, a0, UCONTEXT_SIGMASK + li a0, SIG_SETMASK + + li v0, SYS_ify (rt_sigprocmask) + syscall + bnez a3, 99f + + REG_L v0, A0OFF(sp) + +#ifdef __mips_hard_float +# if _MIPS_SIM == _ABI64 + l.d fs0, (24 * SZREG + MCONTEXT_FPREGS)(v0) + l.d fs1, (25 * SZREG + MCONTEXT_FPREGS)(v0) + l.d fs2, (26 * SZREG + MCONTEXT_FPREGS)(v0) + l.d fs3, (27 * SZREG + MCONTEXT_FPREGS)(v0) + l.d fs4, (28 * SZREG + MCONTEXT_FPREGS)(v0) + l.d fs5, (29 * SZREG + MCONTEXT_FPREGS)(v0) + l.d fs6, (30 * SZREG + MCONTEXT_FPREGS)(v0) + l.d fs7, (31 * SZREG + MCONTEXT_FPREGS)(v0) + +# else /* _MIPS_SIM != _ABI64 */ + l.d fs0, (20 * SZREG + MCONTEXT_FPREGS)(v0) + l.d fs1, (22 * SZREG + MCONTEXT_FPREGS)(v0) + l.d fs2, (24 * SZREG + MCONTEXT_FPREGS)(v0) + l.d fs3, (26 * SZREG + MCONTEXT_FPREGS)(v0) + l.d fs4, (28 * SZREG + MCONTEXT_FPREGS)(v0) + l.d fs5, (30 * SZREG + MCONTEXT_FPREGS)(v0) + +# endif /* _MIPS_SIM != _ABI64 */ + + lw v1, MCONTEXT_FPC_CSR(v0) + ctc1 v1, fcr31 +#endif /* __mips_hard_float */ + + /* Note the contents of argument registers will be random + unless makecontext() has been called. */ + REG_L a0, (4 * SZREG + MCONTEXT_GREGS)(v0) + REG_L a1, (5 * SZREG + MCONTEXT_GREGS)(v0) + REG_L a2, (6 * SZREG + MCONTEXT_GREGS)(v0) + REG_L a3, (7 * SZREG + MCONTEXT_GREGS)(v0) +#if _MIPS_SIM != _ABIO32 + REG_L a4, (8 * SZREG + MCONTEXT_GREGS)(v0) + REG_L a5, (9 * SZREG + MCONTEXT_GREGS)(v0) + REG_L a6, (10 * SZREG + MCONTEXT_GREGS)(v0) + REG_L a7, (11 * SZREG + MCONTEXT_GREGS)(v0) +#endif + + REG_L s0, (16 * SZREG + MCONTEXT_GREGS)(v0) + REG_L s1, (17 * SZREG + MCONTEXT_GREGS)(v0) + REG_L s2, (18 * SZREG + MCONTEXT_GREGS)(v0) + REG_L s3, (19 * SZREG + MCONTEXT_GREGS)(v0) + REG_L s4, (20 * SZREG + MCONTEXT_GREGS)(v0) + REG_L s5, (21 * SZREG + MCONTEXT_GREGS)(v0) + REG_L s6, (22 * SZREG + MCONTEXT_GREGS)(v0) + REG_L s7, (23 * SZREG + MCONTEXT_GREGS)(v0) +#if ! defined (__PIC__) || _MIPS_SIM != _ABIO32 + REG_L gp, (28 * SZREG + MCONTEXT_GREGS)(v0) +#endif + REG_L sp, (29 * SZREG + MCONTEXT_GREGS)(v0) + REG_L fp, (30 * SZREG + MCONTEXT_GREGS)(v0) + REG_L ra, (31 * SZREG + MCONTEXT_GREGS)(v0) + REG_L t9, MCONTEXT_PC(v0) + + move v0, zero + jr t9 + +98: + /* This is a context obtained from a signal handler. + Perform a full restore by pushing the context + passed onto a simulated signal frame on the stack + and call the signal return syscall as if a signal + handler exited normally. */ + PTR_ADDIU sp, -((RT_SIGFRAME_SIZE + ALSZ) & ALMASK) + + /* Only ucontext is referred to from rt_sigreturn, + copy it. */ + PTR_ADDIU t1, sp, RT_SIGFRAME_UCONTEXT + li t3, ((UCONTEXT_SIZE + SZREG - 1) / SZREG) - 1 +0: + REG_L t2, (a0) + PTR_ADDIU a0, SZREG + REG_S t2, (t1) + PTR_ADDIU t1, SZREG + .set noreorder + bgtz t3, 0b + addiu t3, -1 + .set reorder + +/* rt_sigreturn () -- no arguments, sp points to struct rt_sigframe. */ + li v0, SYS_ify (rt_sigreturn) + syscall + + /* Restore the stack and fall through to the error + path. Successful rt_sigreturn never returns to + its calling place. */ + PTR_ADDIU sp, ((RT_SIGFRAME_SIZE + ALSZ) & ALMASK) +99: +#ifdef __PIC__ + PTR_LA t9, JUMPTARGET (__syscall_error) + RESTORE_GP64 + PTR_ADDIU sp, FRAMESZ + jr t9 + +#else /* ! __PIC__ */ + + j JUMPTARGET (__syscall_error) +#endif /* ! __PIC__ */ +PSEUDO_END (__setcontext) + +weak_alias (__setcontext, setcontext) diff -up --recursive --new-file glibc-ports-2.9.90-20090226.macro/sysdeps/unix/sysv/linux/mips/swapcontext.S glibc-ports-2.9.90-20090226/sysdeps/unix/sysv/linux/mips/swapcontext.S --- glibc-ports-2.9.90-20090226.macro/sysdeps/unix/sysv/linux/mips/swapcontext.S 1970-01-01 00:00:00.000000000 +0000 +++ glibc-ports-2.9.90-20090226/sysdeps/unix/sysv/linux/mips/swapcontext.S 2009-02-26 19:00:07.000000000 +0000 @@ -0,0 +1,212 @@ +/* Save and set current context. + Copyright (C) 2009 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Maciej W. Rozycki . + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, write to the Free + Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA + 02110-1301, USA. */ + +#include +#include +#include +#include + +#include "ucontext_i.h" + +/* int swapcontext (ucontext_t *oucp, const ucontext_t *ucp) */ + + .text +LOCALSZ = 0 +ARGSZ = 0 +MASK = 0x00000000 +#ifdef __PIC__ +LOCALSZ = 1 /* save gp */ +#endif +#if _MIPS_SIM != _ABIO32 +ARGSZ = 1 /* save a1 */ +# ifdef __PIC__ +MASK = 0x10000000 +# endif +#endif +FRAMESZ = (((ARGSZ + LOCALSZ) * SZREG) + ALSZ) & ALMASK +GPOFF = FRAMESZ - ((ARGSZ + 1) * SZREG) +#if _MIPS_SIM != _ABIO32 +A1OFF = FRAMESZ - (1 * SZREG) /* callee-allocated */ +#else +A1OFF = FRAMESZ + (1 * SZREG) /* caller-allocated */ +#endif + +NESTED (__swapcontext, FRAMESZ, ra) + .mask MASK, -(ARGSZ * SZREG) + .fmask 0x00000000, 0 + +#ifdef __PIC__ + SETUP_GP + + move a2, sp +# define _SP a2 + +# if _MIPS_SIM != _ABIO32 + move a3, gp +# define _GP a3 +# endif + + PTR_ADDIU sp, -FRAMESZ + SETUP_GP64 (GPOFF, __swapcontext) + SAVE_GP (GPOFF) + +#else /* ! __PIC__ */ +# define _SP sp +# define _GP gp + +#endif /* ! __PIC__ */ + +#ifdef PROF + .set noat + move AT, ra + jal _mcount + .set at +#endif + + /* Store a magic flag. */ + li v1, 1 + REG_S v1, (0 * SZREG + MCONTEXT_GREGS)(a0) /* zero */ + + REG_S s0, (16 * SZREG + MCONTEXT_GREGS)(a0) + REG_S s1, (17 * SZREG + MCONTEXT_GREGS)(a0) + REG_S s2, (18 * SZREG + MCONTEXT_GREGS)(a0) + REG_S s3, (19 * SZREG + MCONTEXT_GREGS)(a0) + REG_S s4, (20 * SZREG + MCONTEXT_GREGS)(a0) + REG_S s5, (21 * SZREG + MCONTEXT_GREGS)(a0) + REG_S s6, (22 * SZREG + MCONTEXT_GREGS)(a0) + REG_S s7, (23 * SZREG + MCONTEXT_GREGS)(a0) +#if ! defined (__PIC__) || _MIPS_SIM != _ABIO32 + REG_S _GP, (28 * SZREG + MCONTEXT_GREGS)(a0) +#endif + REG_S _SP, (29 * SZREG + MCONTEXT_GREGS)(a0) + REG_S fp, (30 * SZREG + MCONTEXT_GREGS)(a0) + REG_S ra, (31 * SZREG + MCONTEXT_GREGS)(a0) + REG_S ra, MCONTEXT_PC(a0) + +#ifdef __mips_hard_float +# if _MIPS_SIM == _ABI64 + s.d fs0, (24 * SZREG + MCONTEXT_FPREGS)(a0) + s.d fs1, (25 * SZREG + MCONTEXT_FPREGS)(a0) + s.d fs2, (26 * SZREG + MCONTEXT_FPREGS)(a0) + s.d fs3, (27 * SZREG + MCONTEXT_FPREGS)(a0) + s.d fs4, (28 * SZREG + MCONTEXT_FPREGS)(a0) + s.d fs5, (29 * SZREG + MCONTEXT_FPREGS)(a0) + s.d fs6, (30 * SZREG + MCONTEXT_FPREGS)(a0) + s.d fs7, (31 * SZREG + MCONTEXT_FPREGS)(a0) + +# else /* _MIPS_SIM != _ABI64 */ + s.d fs0, (20 * SZREG + MCONTEXT_FPREGS)(a0) + s.d fs1, (22 * SZREG + MCONTEXT_FPREGS)(a0) + s.d fs2, (24 * SZREG + MCONTEXT_FPREGS)(a0) + s.d fs3, (26 * SZREG + MCONTEXT_FPREGS)(a0) + s.d fs4, (28 * SZREG + MCONTEXT_FPREGS)(a0) + s.d fs5, (30 * SZREG + MCONTEXT_FPREGS)(a0) + +# endif /* _MIPS_SIM != _ABI64 */ + + cfc1 v1, fcr31 + sw v1, MCONTEXT_FPC_CSR(a0) +#endif /* __mips_hard_float */ + + REG_S a1, A1OFF(sp) + +/* rt_sigprocmask (SIG_SETMASK, &ucp->uc_sigmask, &oucp->uc_sigmask, _NSIG8) */ + li a3, _NSIG8 + PTR_ADDU a2, a0, UCONTEXT_SIGMASK + PTR_ADDU a1, a1, UCONTEXT_SIGMASK + li a0, SIG_SETMASK + + li v0, SYS_ify (rt_sigprocmask) + syscall + bnez a3, 99f + + REG_L v0, A1OFF(sp) + +#ifdef __mips_hard_float +# if _MIPS_SIM == _ABI64 + l.d fs0, (24 * SZREG + MCONTEXT_FPREGS)(v0) + l.d fs1, (25 * SZREG + MCONTEXT_FPREGS)(v0) + l.d fs2, (26 * SZREG + MCONTEXT_FPREGS)(v0) + l.d fs3, (27 * SZREG + MCONTEXT_FPREGS)(v0) + l.d fs4, (28 * SZREG + MCONTEXT_FPREGS)(v0) + l.d fs5, (29 * SZREG + MCONTEXT_FPREGS)(v0) + l.d fs6, (30 * SZREG + MCONTEXT_FPREGS)(v0) + l.d fs7, (31 * SZREG + MCONTEXT_FPREGS)(v0) + +# else /* _MIPS_SIM != _ABI64 */ + l.d fs0, (20 * SZREG + MCONTEXT_FPREGS)(v0) + l.d fs1, (22 * SZREG + MCONTEXT_FPREGS)(v0) + l.d fs2, (24 * SZREG + MCONTEXT_FPREGS)(v0) + l.d fs3, (26 * SZREG + MCONTEXT_FPREGS)(v0) + l.d fs4, (28 * SZREG + MCONTEXT_FPREGS)(v0) + l.d fs5, (30 * SZREG + MCONTEXT_FPREGS)(v0) + +# endif /* _MIPS_SIM != _ABI64 */ + + lw v1, MCONTEXT_FPC_CSR(v0) + ctc1 v1, fcr31 +#endif /* __mips_hard_float */ + + /* Note the contents of argument registers will be random + unless makecontext() has been called. */ + REG_L a0, (4 * SZREG + MCONTEXT_GREGS)(v0) + REG_L a1, (5 * SZREG + MCONTEXT_GREGS)(v0) + REG_L a2, (6 * SZREG + MCONTEXT_GREGS)(v0) + REG_L a3, (7 * SZREG + MCONTEXT_GREGS)(v0) +#if _MIPS_SIM != _ABIO32 + REG_L a4, (8 * SZREG + MCONTEXT_GREGS)(v0) + REG_L a5, (9 * SZREG + MCONTEXT_GREGS)(v0) + REG_L a6, (10 * SZREG + MCONTEXT_GREGS)(v0) + REG_L a7, (11 * SZREG + MCONTEXT_GREGS)(v0) +#endif + + REG_L s0, (16 * SZREG + MCONTEXT_GREGS)(v0) + REG_L s1, (17 * SZREG + MCONTEXT_GREGS)(v0) + REG_L s2, (18 * SZREG + MCONTEXT_GREGS)(v0) + REG_L s3, (19 * SZREG + MCONTEXT_GREGS)(v0) + REG_L s4, (20 * SZREG + MCONTEXT_GREGS)(v0) + REG_L s5, (21 * SZREG + MCONTEXT_GREGS)(v0) + REG_L s6, (22 * SZREG + MCONTEXT_GREGS)(v0) + REG_L s7, (23 * SZREG + MCONTEXT_GREGS)(v0) +#if ! defined (__PIC__) || _MIPS_SIM != _ABIO32 + REG_L gp, (28 * SZREG + MCONTEXT_GREGS)(v0) +#endif + REG_L sp, (29 * SZREG + MCONTEXT_GREGS)(v0) + REG_L fp, (30 * SZREG + MCONTEXT_GREGS)(v0) + REG_L ra, (31 * SZREG + MCONTEXT_GREGS)(v0) + REG_L t9, MCONTEXT_PC(v0) + + move v0, zero + jr t9 + +99: +#ifdef __PIC__ + PTR_LA t9, JUMPTARGET (__syscall_error) + RESTORE_GP64 + PTR_ADDIU sp, FRAMESZ + jr t9 + +#else /* ! __PIC__ */ + + j JUMPTARGET (__syscall_error) +#endif /* ! __PIC__ */ +PSEUDO_END (__swapcontext) + +weak_alias (__swapcontext, swapcontext) diff -up --recursive --new-file glibc-ports-2.9.90-20090226.macro/sysdeps/unix/sysv/linux/mips/sys/ucontext.h glibc-ports-2.9.90-20090226/sysdeps/unix/sysv/linux/mips/sys/ucontext.h --- glibc-ports-2.9.90-20090226.macro/sysdeps/unix/sysv/linux/mips/sys/ucontext.h 2006-05-10 18:57:03.000000000 +0000 +++ glibc-ports-2.9.90-20090226/sysdeps/unix/sysv/linux/mips/sys/ucontext.h 2009-02-26 18:58:49.000000000 +0000 @@ -56,12 +56,9 @@ typedef struct fpregset { #if _MIPS_SIM == _ABIO32 /* Earlier versions of glibc for mips had an entirely different definition of mcontext_t, that didn't even resemble the - corresponding kernel data structure. Since all legitimate uses of - ucontext_t in glibc mustn't have accessed anything beyond - uc_mcontext and, even then, taking a pointer to it, casting it to - sigcontext_t, and accessing it as such, which is what it has always - been, this can still be rectified. Fortunately, makecontext, - [gs]etcontext et all have never been implemented. */ + corresponding kernel data structure. Fortunately, makecontext, + [gs]etcontext et all were not implemented back then, so this can + still be rectified. */ typedef struct { unsigned int regmask; diff -up --recursive --new-file glibc-ports-2.9.90-20090226.macro/sysdeps/unix/sysv/linux/mips/ucontext_i.sym glibc-ports-2.9.90-20090226/sysdeps/unix/sysv/linux/mips/ucontext_i.sym --- glibc-ports-2.9.90-20090226.macro/sysdeps/unix/sysv/linux/mips/ucontext_i.sym 1970-01-01 00:00:00.000000000 +0000 +++ glibc-ports-2.9.90-20090226/sysdeps/unix/sysv/linux/mips/ucontext_i.sym 2009-02-26 00:00:00.000000000 +0000 @@ -0,0 +1,52 @@ +#include +#include +#include +#include + +#include + +-- Constants used by the rt_sigprocmask call. + +SIG_BLOCK +SIG_SETMASK + +_NSIG8 (_NSIG / 8) + +-- Offsets of the fields in the kernel rt_sigframe_t structure. +#define rt_sigframe(member) offsetof (kernel_rt_sigframe_t, member) + +RT_SIGFRAME_UCONTEXT rt_sigframe (rs_uc) + +RT_SIGFRAME_SIZE sizeof (kernel_rt_sigframe_t) + +-- Offsets of the fields in the ucontext_t structure. +#define ucontext(member) offsetof (ucontext_t, member) +#define stack(member) ucontext (uc_stack.member) +#define mcontext(member) ucontext (uc_mcontext.member) + +UCONTEXT_FLAGS ucontext (uc_flags) +UCONTEXT_LINK ucontext (uc_link) +UCONTEXT_STACK ucontext (uc_stack) +UCONTEXT_MCONTEXT ucontext (uc_mcontext) +UCONTEXT_SIGMASK ucontext (uc_sigmask) + +STACK_SP stack (ss_sp) +STACK_SIZE stack (ss_size) +STACK_FLAGS stack (ss_flags) + +MCONTEXT_GREGS mcontext (gregs) +MCONTEXT_FPREGS mcontext (fpregs) +MCONTEXT_MDHI mcontext (mdhi) +MCONTEXT_HI1 mcontext (hi1) +MCONTEXT_HI2 mcontext (hi2) +MCONTEXT_HI3 mcontext (hi3) +MCONTEXT_MDLO mcontext (mdlo) +MCONTEXT_LO1 mcontext (lo1) +MCONTEXT_LO2 mcontext (lo2) +MCONTEXT_LO3 mcontext (lo3) +MCONTEXT_PC mcontext (pc) +MCONTEXT_FPC_CSR mcontext (fpc_csr) +MCONTEXT_USED_MATH mcontext (used_math) +MCONTEXT_DSP mcontext (dsp) + +UCONTEXT_SIZE sizeof (ucontext_t) From macro@codesourcery.com Sun Mar 1 00:19:56 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 01 Mar 2009 00:19:58 +0000 (GMT) Received: from mail.codesourcery.com ([65.74.133.4]:19179 "EHLO mail.codesourcery.com") by ftp.linux-mips.org with ESMTP id S20809045AbZCAAT4 (ORCPT ); Sun, 1 Mar 2009 00:19:56 +0000 Received: (qmail 18996 invoked from network); 1 Mar 2009 00:19:53 -0000 Received: from unknown (HELO pl.orcam.me.uk) (macro@127.0.0.2) by mail.codesourcery.com with ESMTPA; 1 Mar 2009 00:19:53 -0000 Date: Sun, 1 Mar 2009 00:19:36 +0000 (GMT) From: "Maciej W. Rozycki" To: libc-ports@sourceware.org cc: linux-mips@linux-mips.org, "Maciej W. Rozycki" Subject: [PATCH] MIPS: Cooked FP register for new ABIs Message-ID: User-Agent: Alpine 1.10 (DEB 962 2008-03-14) MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21992 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: macro@codesourcery.com Precedence: bulk X-list: linux-mips Hello, Here is a change to to provide correct cooked FP register names for the MIPS n64 and n32 ABIs according to "MIPSpro Assembly Language Programmer's Guide" (Silicon Graphic's document number 007-2418-004). 2009-03-01 Maciej W. Rozycki * sysdeps/mips/sys/fpregdef.h: Update for new ABIs. Please apply. Maciej glibc-ports-2.9.90-20090226-mips-fpregdef-15.patch diff -up --recursive --new-file glibc-ports-2.9.90-20090226.macro/sysdeps/mips/sys/fpregdef.h glibc-ports-2.9.90-20090226/sysdeps/mips/sys/fpregdef.h --- glibc-ports-2.9.90-20090226.macro/sysdeps/mips/sys/fpregdef.h 2001-07-06 04:56:01.000000000 +0000 +++ glibc-ports-2.9.90-20090226/sysdeps/mips/sys/fpregdef.h 2009-03-01 00:10:53.000000000 +0000 @@ -1,4 +1,4 @@ -/* Copyright (C) 1991, 92, 94, 95, 96, 97, 98 Free Software Foundation, Inc. +/* Copyright (C) 1991,92,94,95,96,97,98,2009 Free Software Foundation, Inc. This file is part of the GNU C Library. The GNU C Library is free software; you can redistribute it and/or @@ -19,19 +19,52 @@ #ifndef _SYS_FPREGDEF_H #define _SYS_FPREGDEF_H -/* - * These definitions only cover the R3000-ish 16/32 register model. - * But we're trying to be R3000 friendly anyway ... - */ -#define fv0 $f0 /* return value */ -#define fv0f $f1 +#include + +/* Commonalities first, individualities next... */ + +#define fv0 $f0 /* return value */ #define fv1 $f2 + +#if _MIPS_SIM == _ABIO32 || _MIPS_SIM == _ABIN32 +#define fs0 $f20 /* callee saved */ +#define fs1 $f22 +#define fs2 $f24 +#define fs3 $f26 +#define fs4 $f28 +#define fs5 $f30 +#endif /* _MIPS_SIM == _ABIO32 || _MIPS_SIM == _ABIN32 */ + +#if _MIPS_SIM == _ABI64 || _MIPS_SIM == _ABIN32 +#define fa0 $f12 /* argument registers */ +#define fa1 $f13 +#define fa2 $f14 +#define fa3 $f15 +#define fa4 $f16 +#define fa5 $f17 +#define fa6 $f18 +#define fa7 $f19 + +#define ft0 $f4 /* caller saved */ +#define ft1 $f5 +#define ft2 $f6 +#define ft3 $f7 +#define ft4 $f8 +#define ft5 $f9 +#define ft6 $f10 +#define ft7 $f11 +#endif /* _MIPS_SIM == _ABI64 || _MIPS_SIM == _ABIN32 */ + +#if _MIPS_SIM == _ABIO32 +#define fv0f $f1 /* return value, high part */ #define fv1f $f3 -#define fa0 $f12 /* argument registers */ + +#define fa0 $f12 /* argument registers */ #define fa0f $f13 #define fa1 $f14 #define fa1f $f15 -#define ft0 $f4 /* caller saved */ + +#define ft0 $f4 /* caller saved */ #define ft0f $f5 #define ft1 $f6 #define ft1f $f7 @@ -43,19 +76,44 @@ #define ft4f $f17 #define ft5 $f18 #define ft5f $f19 -#define fs0 $f20 /* callee saved */ -#define fs0f $f21 -#define fs1 $f22 + +#define fs0f $f21 /* callee saved, high part */ #define fs1f $f23 -#define fs2 $f24 #define fs2f $f25 -#define fs3 $f26 #define fs3f $f27 -#define fs4 $f28 #define fs4f $f29 -#define fs5 $f30 #define fs5f $f31 +#endif /* _MIPS_SIM == _ABIO32 */ + +#if _MIPS_SIM == _ABI64 +#define ft8 $f20 /* caller saved */ +#define ft9 $f21 +#define ft10 $f22 +#define ft11 $f23 +#define ft12 $f1 +#define ft13 $f3 + +#define fs0 $f24 /* callee saved */ +#define fs1 $f25 +#define fs2 $f26 +#define fs3 $f27 +#define fs4 $f28 +#define fs5 $f29 +#define fs6 $f30 +#define fs7 $f31 +#endif /* _MIPS_SIM == _ABI64 */ + +#if _MIPS_SIM == _ABIN32 +#define ft8 $f21 /* caller saved */ +#define ft9 $f23 +#define ft10 $f25 +#define ft11 $f27 +#define ft12 $f29 +#define ft13 $f31 +#define ft14 $f1 +#define ft15 $f3 +#endif /* _MIPS_SIM == _ABIN32 */ -#define fcr31 $31 /* FPU status register */ +#define fcr31 $31 /* FPU status register */ #endif /* sys/fpregdef.h */ From roland@redhat.com Mon Mar 2 01:44:52 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 02 Mar 2009 01:44:54 +0000 (GMT) Received: from mx1.redhat.com ([66.187.233.31]:64708 "EHLO mx1.redhat.com") by ftp.linux-mips.org with ESMTP id S21103416AbZCBBow (ORCPT ); Mon, 2 Mar 2009 01:44:52 +0000 Received: from int-mx1.corp.redhat.com (int-mx1.corp.redhat.com [172.16.52.254]) by mx1.redhat.com (8.13.8/8.13.8) with ESMTP id n221iSZa010435; Sun, 1 Mar 2009 20:44:28 -0500 Received: from gateway.sf.frob.com (vpn-13-15.rdu.redhat.com [10.11.13.15]) by int-mx1.corp.redhat.com (8.13.1/8.13.1) with ESMTP id n221iRTj003095; Sun, 1 Mar 2009 20:44:29 -0500 Received: from magilla.sf.frob.com (magilla.sf.frob.com [198.49.250.228]) by gateway.sf.frob.com (Postfix) with ESMTP id B1AE5357B; Sun, 1 Mar 2009 17:44:23 -0800 (PST) Received: by magilla.sf.frob.com (Postfix, from userid 5281) id 22A6FFC3C6; Sun, 1 Mar 2009 17:44:23 -0800 (PST) MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit From: Roland McGrath To: Linus Torvalds X-Fcc: ~/Mail/linus Cc: Andrew Morton , x86@kernel.org, linux-kernel@vger.kernel.org, stable@kernel.org, linux-mips@linux-mips.org, sparclinux@vger.kernel.org, linuxppc-dev@ozlabs.org Subject: Re: [PATCH 2/2] x86-64: seccomp: fix 32/64 syscall hole In-Reply-To: Linus Torvalds's message of Saturday, 28 February 2009 09:23:36 -0800 X-Fcc: ~/Mail/linus References: <20090228030226.C0D34FC3DA@magilla.sf.frob.com> <20090228030413.5B915FC3DA@magilla.sf.frob.com> <20090228072554.CFEA6FC3DA@magilla.sf.frob.com> X-Antipastobozoticataclysm: When George Bush projectile vomits antipasto on the Japanese. Message-Id: <20090302014423.22A6FFC3C6@magilla.sf.frob.com> Date: Sun, 1 Mar 2009 17:44:23 -0800 (PST) X-Scanned-By: MIMEDefang 2.58 on 172.16.52.254 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21993 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: roland@redhat.com Precedence: bulk X-list: linux-mips > And I guess the seccomp interaction means that this is potentially a > 2.6.29 thing. Not that I know whether anybody actually _uses_ seccomp. It > does seem to be enabled in at least Fedora kernels, but it might not be > used anywhere. I have no idea who uses it. I just assume that anyone who is using it might be expecting it to be reliable for security purposes as advertised. Thanks, Roland From shinya.kuribayashi@necel.com Tue Mar 3 09:05:16 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 03 Mar 2009 09:05:19 +0000 (GMT) Received: from TYO202.gate.nec.co.jp ([202.32.8.206]:30336 "EHLO tyo202.gate.nec.co.jp") by ftp.linux-mips.org with ESMTP id S19202101AbZCCJFQ (ORCPT ); Tue, 3 Mar 2009 09:05:16 +0000 Received: from relay31.aps.necel.com ([10.29.19.54]) by tyo202.gate.nec.co.jp (8.13.8/8.13.4) with ESMTP id n2395BWZ004166 for ; Tue, 3 Mar 2009 18:05:11 +0900 (JST) Received: from realmbox21.aps.necel.com ([10.29.19.32] [10.29.19.32]) by relay31.aps.necel.com with ESMTP; Tue, 3 Mar 2009 18:05:11 +0900 Received: from [10.114.181.78] ([10.114.181.78] [10.114.181.78]) by mbox02.aps.necel.com with ESMTP; Tue, 3 Mar 2009 18:05:11 +0900 Message-Id: <49ACF2EF.3080903@necel.com> Date: Tue, 03 Mar 2009 18:05:51 +0900 From: Shinya Kuribayashi User-Agent: Thunderbird 2.0.0.19 (Windows/20081209) MIME-Version: 1.0 To: linux-mips@linux-mips.org Subject: [PATCH] MIPS: NEC VR5500 processor support fixup Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21994 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: shinya.kuribayashi@necel.com Precedence: bulk X-list: linux-mips Current VR5500 processor support lacks of some functions which are expected to be configured/syhthesized on arch initialization. Here're some VR5500A spec notes: * all execution hazards are handled in hardware. * Once VR5500A stops the operation of the pipeline by WAIT instruction, it could return from the standby mode only when either a reset, NMI request, or all enabled interrupts is/are detected. In other words, if interrupts are disabled by Status.IE=0, it keeps in standby mode even when interrupts are internally asserted. Notes on WAIT: The operation of the processor is undefined if WAIT insn is in the branch delay slot. The operation is also undefined if WAIT insn is executed when Status.EXL and Status.ERL are set to 1. * VR5500A core only implements the Load prefetch. With these changes, it boots fine. Signed-off-by: Shinya Kuribayashi --- Hi, I have several EMMA2RH markeins patches in my local branch, but before anything else, here's a VR5500 support patch. Please review. I'm afraid that I might put CPU_R5500 enum in incorrect position. If it doesn't suit for you, please let me know. Shinya arch/mips/include/asm/hazards.h | 3 ++- arch/mips/include/asm/prefetch.h | 2 +- arch/mips/kernel/cpu-probe.c | 1 + arch/mips/mm/page.c | 3 ++- arch/mips/mm/tlbex.c | 1 + 5 files changed, 7 insertions(+), 3 deletions(-) diff --git a/arch/mips/include/asm/hazards.h b/arch/mips/include/asm/hazards.h index 43baed1..134e1fc 100644 --- a/arch/mips/include/asm/hazards.h +++ b/arch/mips/include/asm/hazards.h @@ -138,7 +138,8 @@ do { \ __instruction_hazard(); \ } while (0) -#elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_CAVIUM_OCTEON) +#elif defined(CONFIG_CPU_R10000) || defined(CONFIG_CPU_CAVIUM_OCTEON) || \ + defined(CONFIG_CPU_R5500) /* * R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer. diff --git a/arch/mips/include/asm/prefetch.h b/arch/mips/include/asm/prefetch.h index 1785083..b5b2103 100644 --- a/arch/mips/include/asm/prefetch.h +++ b/arch/mips/include/asm/prefetch.h @@ -26,7 +26,7 @@ * Pref_WriteBackInvalidate is a nop and Pref_PrepareForStore is broken in * current versions due to erratum G105. * - * VR7701 only implements the Load prefetch. + * VR5500 (including VR5701 and VR7701) only implements the Load prefetch. * * Finally MIPS32 and MIPS64 implement all of the following hints. */ diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index a7162a4..1bdbcad 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -149,6 +149,7 @@ void __init check_wait(void) case CPU_R4650: case CPU_R4700: case CPU_R5000: + case CPU_R5500: case CPU_NEVADA: case CPU_4KC: case CPU_4KEC: diff --git a/arch/mips/mm/page.c b/arch/mips/mm/page.c index 1417c64..48060c6 100644 --- a/arch/mips/mm/page.c +++ b/arch/mips/mm/page.c @@ -172,8 +172,9 @@ static void __cpuinit set_prefetch_parameters(void) */ cache_line_size = cpu_dcache_line_size(); switch (current_cpu_type()) { + case CPU_R5500: case CPU_TX49XX: - /* TX49 supports only Pref_Load */ + /* These processors only support the Pref_Load. */ pref_bias_copy_load = 256; break; diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index 4294203..f335cf6 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -318,6 +318,7 @@ static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l, case CPU_BCM4710: case CPU_LOONGSON2: case CPU_CAVIUM_OCTEON: + case CPU_R5500: if (m4kc_tlbp_war()) uasm_i_nop(p); tlbw(p); From robert.richter@amd.com Tue Mar 3 11:08:39 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 03 Mar 2009 11:08:42 +0000 (GMT) Received: from tx2ehsobe005.messaging.microsoft.com ([65.55.88.15]:19800 "EHLO TX2EHSOBE009.bigfish.com") by ftp.linux-mips.org with ESMTP id S19202471AbZCCLIj (ORCPT ); Tue, 3 Mar 2009 11:08:39 +0000 Received: from mail234-tx2-R.bigfish.com (10.9.14.248) by TX2EHSOBE009.bigfish.com (10.9.40.29) with Microsoft SMTP Server id 8.1.340.0; Tue, 3 Mar 2009 11:08:33 +0000 Received: from mail234-tx2 (localhost.localdomain [127.0.0.1]) by mail234-tx2-R.bigfish.com (Postfix) with ESMTP id 878F134685F4; Tue, 3 Mar 2009 11:08:32 +0000 (UTC) X-BigFish: VPS-77(zz709fM1432R62a3L98dR936eQ4015M1805M936fK8d0R655O13ddRzzzzz32i6bh61h) X-FB-SS: 5, Received: by mail234-tx2 (MessageSwitch) id 1236078486301073_16714; Tue, 3 Mar 2009 11:08:06 +0000 (UCT) Received: from svlb1extmailp02.amd.com (unknown [139.95.251.11]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail234-tx2.bigfish.com (Postfix) with ESMTP id A95A64F10055; Tue, 3 Mar 2009 11:08:05 +0000 (UTC) Received: from svlb1twp01.amd.com ([139.95.250.34]) by svlb1extmailp02.amd.com (Switch-3.2.7/Switch-3.2.7) with ESMTP id n23B7sGs029832; Tue, 3 Mar 2009 03:07:57 -0800 X-WSS-ID: 0KFXG98-03-9BX-01 Received: from SSVLEXBH2.amd.com (ssvlexbh2.amd.com [139.95.53.183]) by svlb1twp01.amd.com (Tumbleweed MailGate 3.5.1) with ESMTP id 26903884941; Tue, 3 Mar 2009 03:07:56 -0800 (PST) Received: from ssvlexmb2.amd.com ([139.95.53.7]) by SSVLEXBH2.amd.com with Microsoft SMTPSVC(6.0.3790.3959); Tue, 3 Mar 2009 03:07:59 -0800 Received: from SF36EXMB1.amd.com ([172.19.4.24]) by ssvlexmb2.amd.com with Microsoft SMTPSVC(6.0.3790.3959); Tue, 3 Mar 2009 03:07:59 -0800 Received: from seurexmb1.amd.com ([165.204.82.130]) by SF36EXMB1.amd.com with Microsoft SMTPSVC(6.0.3790.3959); Tue, 3 Mar 2009 12:07:56 +0100 Received: from erda.amd.com ([165.204.85.17]) by seurexmb1.amd.com with Microsoft SMTPSVC(6.0.3790.3959); Tue, 3 Mar 2009 12:07:56 +0100 Received: by erda.amd.com (Postfix, from userid 35569) id 19B32800D; Tue, 3 Mar 2009 12:07:56 +0100 (CET) Date: Tue, 3 Mar 2009 12:07:56 +0100 From: Robert Richter To: Mark Asselstine , Ralf Baechle CC: linux-mips@linux-mips.org, oprofile-list@lists.sf.net Subject: Re: [PATCH V2] oprofile: VR5500 performance counter driver Message-ID: <20090303110755.GD10085@erda.amd.com> References: <20090225165953.GF25042@erda.amd.com> <1235681374-19952-1-git-send-email-mark.asselstine@windriver.com> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <1235681374-19952-1-git-send-email-mark.asselstine@windriver.com> User-Agent: Mutt/1.5.16 (2007-06-09) X-OriginalArrivalTime: 03 Mar 2009 11:07:56.0182 (UTC) FILETIME=[4E1E1360:01C99BF0] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21995 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: robert.richter@amd.com Precedence: bulk X-list: linux-mips On 26.02.09 15:49:34, Mark Asselstine wrote: > This is inspired by op_model_mipsxx.c with some modification > in regards to register layout and overflow handling. This has > been tested on a NEC VR5500 board and shown to produce sane > results. > > Signed-off-by: Mark Asselstine > --- > > I have left this as a new file as there is enough differences > to make combining it combersome. If pushed I would possibly > change my mind but I am not convinced yet. The userspace > events are seen as mips/vr5500 so if there is a desire to > have everything be r5500 some userspace changes would need > to be made. > > arch/mips/oprofile/Makefile | 1 + > arch/mips/oprofile/common.c | 5 + > arch/mips/oprofile/op_model_r5500.c | 161 +++++++++++++++++++++++++++++++++++ Mark, the Kconfig option for CONFIG_CPU_R5500 is still missing otherwise the patch itself looks fine. Ralf, do you agree on introducing a separate file for this cpu model? Please ack. Thanks, -Robert > 3 files changed, 167 insertions(+), 0 deletions(-) > create mode 100644 arch/mips/oprofile/op_model_r5500.c > > diff --git a/arch/mips/oprofile/Makefile b/arch/mips/oprofile/Makefile > index bf3be6f..586e64e 100644 > --- a/arch/mips/oprofile/Makefile > +++ b/arch/mips/oprofile/Makefile > @@ -14,4 +14,5 @@ oprofile-$(CONFIG_CPU_MIPS32) += op_model_mipsxx.o > oprofile-$(CONFIG_CPU_MIPS64) += op_model_mipsxx.o > oprofile-$(CONFIG_CPU_R10000) += op_model_mipsxx.o > oprofile-$(CONFIG_CPU_SB1) += op_model_mipsxx.o > +oprofile-$(CONFIG_CPU_R5500) += op_model_r5500.o > oprofile-$(CONFIG_CPU_RM9000) += op_model_rm9000.o > diff --git a/arch/mips/oprofile/common.c b/arch/mips/oprofile/common.c > index 3bf3354..26780c7 100644 > --- a/arch/mips/oprofile/common.c > +++ b/arch/mips/oprofile/common.c > @@ -16,6 +16,7 @@ > > extern struct op_mips_model op_model_mipsxx_ops __attribute__((weak)); > extern struct op_mips_model op_model_rm9000_ops __attribute__((weak)); > +extern struct op_mips_model op_model_r5500_ops __attribute__((weak)); > > static struct op_mips_model *model; > > @@ -93,6 +94,10 @@ int __init oprofile_arch_init(struct oprofile_operations *ops) > case CPU_RM9000: > lmodel = &op_model_rm9000_ops; > break; > + > + case CPU_R5500: > + lmodel = &op_model_r5500_ops; > + break; > }; > > if (!lmodel) > diff --git a/arch/mips/oprofile/op_model_r5500.c b/arch/mips/oprofile/op_model_r5500.c > new file mode 100644 > index 0000000..9b0d20f > --- /dev/null > +++ b/arch/mips/oprofile/op_model_r5500.c > @@ -0,0 +1,161 @@ > +/* > + * This file is subject to the terms and conditions of the GNU General Public > + * License. See the file "COPYING" in the main directory of this archive > + * for more details. > + * > + * Copyright (c) 2009 Wind River Systems, Inc. > + * > + * Derived from op_model_mipsxx.c Copyright Ralf Baechle, MIPS Technologies Inc > + */ > +#include > +#include > +#include > + > +#include "op_impl.h" > + > +#define M_PERFCTL_EXL (1UL << 0) > +#define M_PERFCTL_KERNEL (1UL << 1) > +#define M_PERFCTL_SUPERVISOR (1UL << 2) > +#define M_PERFCTL_USER (1UL << 3) > +#define M_PERFCTL_INTERRUPT_ENABLE (1UL << 4) > +#define M_PERFCTL_INTERRUPT (1UL << 5) > +#define M_PERFCTL_EVENT(event) (((event) & 0xf) << 6) > +#define M_PERFCTL_COUNT_ENABLE (1UL << 10) > + > +#define NUM_COUNTERS 2 > + > +static int (*save_perf_irq) (void); > + > +struct op_mips_model op_model_r5500_ops; > + > +static struct r5500_register_config { > + unsigned int control[NUM_COUNTERS]; > + unsigned int counter[NUM_COUNTERS]; > +} reg; > + > +/* Compute all of the registers in preparation for enabling profiling. */ > +static void r5500_reg_setup(struct op_counter_config *ctr) > +{ > + int i; > + unsigned int counters = NUM_COUNTERS; > + > + /* Compute the performance counter control word. */ > + for (i = 0; i < counters; i++) { > + reg.control[i] = 0; > + reg.counter[i] = 0; > + > + if (!ctr[i].enabled) > + continue; > + > + reg.control[i] = M_PERFCTL_EVENT(ctr[i].event) | > + M_PERFCTL_INTERRUPT_ENABLE | M_PERFCTL_COUNT_ENABLE; > + if (ctr[i].kernel) > + reg.control[i] |= M_PERFCTL_KERNEL; > + if (ctr[i].user) > + reg.control[i] |= M_PERFCTL_USER; > + if (ctr[i].exl) > + reg.control[i] |= M_PERFCTL_EXL; > + > + reg.counter[i] = 0xffffffff - ctr[i].count + 1; > + } > +} > + > +/* Program all of the registers in preparation for enabling profiling. */ > +static void r5500_cpu_setup(void *args) > +{ > + write_c0_perfctrl1(0); > + write_c0_perfcntr1(reg.counter[1]); > + > + write_c0_perfctrl0(0); > + write_c0_perfcntr0(reg.counter[0]); > +} > + > +/* Start all counters on current CPU */ > +static void r5500_cpu_start(void *args) > +{ > + write_c0_perfctrl1(reg.control[1]); > + write_c0_perfctrl0(reg.control[0]); > +} > + > +/* Stop all counters on current CPU */ > +static void r5500_cpu_stop(void *args) > +{ > + write_c0_perfctrl1(0); > + write_c0_perfctrl0(0); > +} > + > +static int r5500_perfcount_handler(void) > +{ > + unsigned int control; > + unsigned int counter; > + int handled = IRQ_NONE; > + > + control = read_c0_perfctrl0(); > + counter = read_c0_perfcntr0(); > + if ((control & M_PERFCTL_INTERRUPT_ENABLE) && > + (control & M_PERFCTL_INTERRUPT)) { > + oprofile_add_sample(get_irq_regs(), 0); > + write_c0_perfcntr0(reg.counter[0]); > + write_c0_perfctrl0(control & ~M_PERFCTL_INTERRUPT); > + handled = IRQ_HANDLED; > + } > + > + control = read_c0_perfctrl1(); > + counter = read_c0_perfcntr1(); > + if ((control & M_PERFCTL_INTERRUPT_ENABLE) && > + (control & M_PERFCTL_INTERRUPT)) { > + oprofile_add_sample(get_irq_regs(), 1); > + write_c0_perfcntr1(reg.counter[1]); > + write_c0_perfctrl1(control & ~M_PERFCTL_INTERRUPT); > + handled = IRQ_HANDLED; > + } > + > + return handled; > +} > + > +static void reset_counters(void *arg) > +{ > + write_c0_perfctrl1(0); > + write_c0_perfcntr1(0); > + > + write_c0_perfctrl0(0); > + write_c0_perfcntr0(0); > +} > + > +static int __init r5500_init(void) > +{ > + on_each_cpu(reset_counters, NULL, 1); > + > + switch (current_cpu_type()) { > + case CPU_R5500: > + op_model_r5500_ops.cpu_type = "mips/vr5500"; > + break; > + > + default: > + printk(KERN_ERR "Profiling unsupported for this CPU\n"); > + > + return -ENODEV; > + } > + > + save_perf_irq = perf_irq; > + perf_irq = r5500_perfcount_handler; > + > + return 0; > +} > + > +static void r5500_exit(void) > +{ > + on_each_cpu(reset_counters, NULL, 1); > + > + perf_irq = save_perf_irq; > +} > + > +struct op_mips_model op_model_r5500_ops = { > + .reg_setup = r5500_reg_setup, > + .cpu_setup = r5500_cpu_setup, > + .init = r5500_init, > + .exit = r5500_exit, > + .cpu_start = r5500_cpu_start, > + .cpu_stop = r5500_cpu_stop, > + .num_counters = NUM_COUNTERS, > +}; > -- > 1.6.0.3 > > > ------------------------------------------------------------------------------ > Open Source Business Conference (OSBC), March 24-25, 2009, San Francisco, CA > -OSBC tackles the biggest issue in open source: Open Sourcing the Enterprise > -Strategies to boost innovation and cut costs with open source participation > -Receive a $600 discount off the registration fee with the source code: SFAD > http://p.sf.net/sfu/XcvMzF8H > _______________________________________________ > oprofile-list mailing list > oprofile-list@lists.sourceforge.net > https://lists.sourceforge.net/lists/listinfo/oprofile-list > -- Advanced Micro Devices, Inc. Operating System Research Center email: robert.richter@amd.com From David.Daney@caviumnetworks.com Tue Mar 3 16:59:51 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 03 Mar 2009 16:59:55 +0000 (GMT) Received: from mail3.caviumnetworks.com ([12.108.191.235]:50187 "EHLO mail3.caviumnetworks.com") by ftp.linux-mips.org with ESMTP id S21299811AbZCCQ7v (ORCPT ); Tue, 3 Mar 2009 16:59:51 +0000 Received: from exch4.caveonetworks.com (Not Verified[192.168.16.23]) by mail3.caviumnetworks.com with MailMarshal (v6,2,2,3503) id ; Tue, 03 Mar 2009 11:57:30 -0500 Received: from exch4.caveonetworks.com ([192.168.16.23]) by exch4.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Tue, 3 Mar 2009 08:56:25 -0800 Received: from dd1.caveonetworks.com ([64.169.86.201]) by exch4.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Tue, 3 Mar 2009 08:56:25 -0800 Message-ID: <49AD6139.60209@caviumnetworks.com> Date: Tue, 03 Mar 2009 08:56:25 -0800 From: David Daney User-Agent: Thunderbird 2.0.0.19 (X11/20090105) MIME-Version: 1.0 To: "Maciej W. Rozycki" CC: Ralf Baechle , linux-mips@linux-mips.org, libc-ports@sourceware.org, "Maciej W. Rozycki" Subject: Re: [PATCH, RFC] MIPS: Implement the getcontext API References: In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 03 Mar 2009 16:56:25.0772 (UTC) FILETIME=[FD344EC0:01C99C20] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21996 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Maciej W. Rozycki wrote: > Hello, > > Here is code to implement the getcontext API for MIPS. [...] > > The conclusion is what I am requesting is to get the structure of the > stack frame used by sigreturn(2) fixed in its current form and make sure > the syscall only ever uses data from the ucontext_t structure within. A > new syscall would have to be introduced if the kernel required a change in > the way sigreturn(2) behaves in the future. For the purpose of glibc the > structure of the stack frame is defined in the kernel_rt_sigframe.h header > provided with the patch. > Note the libgcc currently makes the assumption that the layout of the stack for signal handlers is fixed. The DWARF2 unwinder needs this information to be able to unwind through signal frames (see gcc/config/mips/linux-unwind.h), so it is already a de facto part of the ABI. When (and if) we move the sigreturn trampoline to a vdso we should be able to maintain the ABI. > Furthermore I am requesting that the kernel recognises the special > meaning of the value of one stored in the slot designated for the $zero > register and never places such a value itself there. Seems reasonable to me as currently a zero is unconditionally stored there. David Daney From blf.ireland@gmail.com Wed Mar 4 08:20:02 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 04 Mar 2009 08:20:07 +0000 (GMT) Received: from mail-bw0-f161.google.com ([209.85.218.161]:11931 "EHLO mail-bw0-f161.google.com") by ftp.linux-mips.org with ESMTP id S20808057AbZCDIUC convert rfc822-to-8bit (ORCPT ); Wed, 4 Mar 2009 08:20:02 +0000 Received: by bwz5 with SMTP id 5so3321613bwz.0 for ; Wed, 04 Mar 2009 00:19:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:sender:from:reply-to:to :subject:date:user-agent:cc:references:in-reply-to:mime-version :content-type:content-transfer-encoding:content-disposition :message-id; bh=lGXEOxqlUvUhIyniZDhZLqw8iFSzkmVqTBczFaoGz9Y=; b=hjZ34u3lS+mRXWTNJEKD+dIpEqBev8IYYwx6gra1BXaI+FEWRPCP8AU2Ej1qHiT7QS fPZt9UKndYK0k0YZra91p2o6pmStOA30oJLnHOTcysemvPJc5derOlEaE08QkKxJTzPe VRw+jnz5wPwr3DaOc3FWgFB0Z+JC8ak/CNXdE= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:from:reply-to:to:subject:date:user-agent:cc:references :in-reply-to:mime-version:content-type:content-transfer-encoding :content-disposition:message-id; b=yAK5Rqcdjes/4TP4oSbYG9+An2+eyxvmNYTtTwBfxiPwWnV1zhCxGWi41CeB5vGb2g Z5wbDdPmQBBsRf1+1FxmhKeGWb8FmlIHzfHooIhUhLJB7tmO7V/u1bEcUE8XxyKDfhvi KcYa0sNg5qQAl92/B98q+MykzvpcNn6QvgFZk= Received: by 10.181.49.3 with SMTP id b3mr2883689bkk.21.1236154795855; Wed, 04 Mar 2009 00:19:55 -0800 (PST) Received: from innova-card.com (1-61.252-81.static-ip.oleane.fr [81.252.61.1]) by mx.google.com with ESMTPS id 17sm14268659bwz.81.2009.03.04.00.19.53 (version=TLSv1/SSLv3 cipher=RC4-MD5); Wed, 04 Mar 2009 00:19:54 -0800 (PST) From: Brian Foster Reply-To: Brian Foster To: David Daney Subject: Re: [PATCH, RFC] MIPS: Implement the getcontext API Date: Wed, 4 Mar 2009 09:19:28 +0100 User-Agent: KMail/1.10.4 (Linux/2.6.27-11-generic; KDE/4.1.4; x86_64; ; ) Cc: "Maciej W. Rozycki" , Ralf Baechle , linux-mips@linux-mips.org, libc-ports@sourceware.org, "Maciej W. Rozycki" References: <49AD6139.60209@caviumnetworks.com> In-Reply-To: <49AD6139.60209@caviumnetworks.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8BIT Content-Disposition: inline Message-Id: <200903040919.29294.brian.foster@innova-card.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21997 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: brian.foster@innova-card.com Precedence: bulk X-list: linux-mips On Tuesday 03 March 2009 17:56:25 David Daney wrote: >[ ... ] > When (and if) we move the sigreturn trampoline to a vdso we should be > able to maintain the ABI. it's more a matter of “when” rather than “if”. there is still an intention here to use XI (we have SmartMIPS), which requires not using the signal (or FP) trampoline on the stack. moving the signal trampoline to a vdso (which is(? was?) called, maybe misleadingly, ‘vsyscall’, on other architectures) is the obvious solution to that part of the puzzle. and yes, it is possible to maintain the ABI; the signal trampoline is still also put on the stack, and modulo XI, would work if used — the trampoline-on-stack is simply not used if there is a vdso with the signal trampoline. cheers! -blf- -- “How many surrealists does it take to | Brian Foster change a lightbulb? Three. One calms | somewhere in south of France the warthog, and two fill the bathtub | Stop E$$o (ExxonMobil)! with brightly-coloured machine tools.” | http://www.stopesso.com From drow@false.org Wed Mar 4 12:17:39 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 04 Mar 2009 12:17:41 +0000 (GMT) Received: from NaN.false.org ([208.75.86.248]:25220 "EHLO nan.false.org") by ftp.linux-mips.org with ESMTP id S21365165AbZCDMRi (ORCPT ); Wed, 4 Mar 2009 12:17:38 +0000 Received: from nan.false.org (localhost [127.0.0.1]) by nan.false.org (Postfix) with ESMTP id 48BEF10A30; Wed, 4 Mar 2009 12:17:36 +0000 (GMT) Received: from caradoc.them.org (209.195.188.212.nauticom.net [209.195.188.212]) by nan.false.org (Postfix) with ESMTP id 986BF104DE; Wed, 4 Mar 2009 12:17:35 +0000 (GMT) Received: from drow by caradoc.them.org with local (Exim 4.69) (envelope-from ) id 1Leq2W-0007TG-W4; Wed, 04 Mar 2009 07:17:33 -0500 Date: Wed, 4 Mar 2009 07:17:32 -0500 From: Daniel Jacobowitz To: Brian Foster Cc: David Daney , "Maciej W. Rozycki" , Ralf Baechle , linux-mips@linux-mips.org, libc-ports@sourceware.org, "Maciej W. Rozycki" Subject: Re: [PATCH, RFC] MIPS: Implement the getcontext API Message-ID: <20090304121732.GA28381@caradoc.them.org> References: <49AD6139.60209@caviumnetworks.com> <200903040919.29294.brian.foster@innova-card.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <200903040919.29294.brian.foster@innova-card.com> User-Agent: Mutt/1.5.17 (2008-05-11) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21998 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dan@debian.org Precedence: bulk X-list: linux-mips On Wed, Mar 04, 2009 at 09:19:28AM +0100, Brian Foster wrote: > moving the signal trampoline to a vdso (which > is(? was?) called, maybe misleadingly, ‘vsyscall’, > on other architectures) is the obvious solution to > that part of the puzzle. and yes, it is possible > to maintain the ABI; the signal trampoline is still > also put on the stack, and modulo XI, would work if > used — the trampoline-on-stack is simply not used > if there is a vdso with the signal trampoline. That won't quite retain the ABI: you need to make sure everyone locates it by using the stack pointer instead of the return pc. Fortunately, GCC uses the return PC only for instruction matching today. I have a vague memory it used to use the stack pointer but this was more reliable. They don't necessarily have to go into the vdso; other architectures have moved them off the stack directly to glibc. -- Daniel Jacobowitz CodeSourcery From anemo@mba.ocn.ne.jp Wed Mar 4 14:45:52 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 04 Mar 2009 14:45:56 +0000 (GMT) Received: from mba.ocn.ne.jp ([122.1.235.107]:24567 "HELO smtp.mba.ocn.ne.jp") by ftp.linux-mips.org with SMTP id S21365443AbZCDOpw (ORCPT ); Wed, 4 Mar 2009 14:45:52 +0000 Received: from localhost.localdomain (p2109-ipad305funabasi.chiba.ocn.ne.jp [123.217.164.109]) by smtp.mba.ocn.ne.jp (Postfix) with ESMTP id 57693AB56; Wed, 4 Mar 2009 23:45:44 +0900 (JST) From: Atsushi Nemoto To: linux-mips@linux-mips.org Cc: ralf@linux-mips.org Subject: [PATCH] TXx9: update defconfigs Date: Wed, 4 Mar 2009 23:45:44 +0900 Message-Id: <1236177944-24243-1-git-send-email-anemo@mba.ocn.ne.jp> X-Mailer: git-send-email 1.5.6.3 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21999 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anemo@mba.ocn.ne.jp Precedence: bulk X-list: linux-mips Enable following features: * MTD (PHYSMAP) * LED (LEDS_GPIO) * RBTX4939 * 7SEGLED * IDE (IDE_TX4938, IDE_TX4939) * SMC91X * RTC_DRV_TX4939 Signed-off-by: Atsushi Nemoto --- arch/mips/configs/jmr3927_defconfig | 265 ++++++++++++++++++++-------- arch/mips/configs/rbtx49xx_defconfig | 319 +++++++++++++++++++++++++++------- 2 files changed, 447 insertions(+), 137 deletions(-) diff --git a/arch/mips/configs/jmr3927_defconfig b/arch/mips/configs/jmr3927_defconfig index 9d5bd2a..5380f1f 100644 --- a/arch/mips/configs/jmr3927_defconfig +++ b/arch/mips/configs/jmr3927_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.26-rc9 -# Fri Jul 11 23:01:36 2008 +# Linux kernel version: 2.6.29-rc7 +# Wed Mar 4 23:07:16 2009 # CONFIG_MIPS=y @@ -18,8 +18,10 @@ CONFIG_MIPS=y # CONFIG_LEMOTE_FULONG is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SIM is not set -# CONFIG_MARKEINS is not set +# CONFIG_MACH_EMMA is not set # CONFIG_MACH_VR41XX is not set +# CONFIG_NXP_STB220 is not set +# CONFIG_NXP_STB225 is not set # CONFIG_PNX8550_JBS is not set # CONFIG_PNX8550_STB810 is not set # CONFIG_PMC_MSP is not set @@ -39,7 +41,11 @@ CONFIG_MIPS=y # CONFIG_SNI_RM is not set CONFIG_MACH_TX39XX=y # CONFIG_MACH_TX49XX is not set +# CONFIG_MIKROTIK_RB532 is not set # CONFIG_WR_PPMC is not set +# CONFIG_CAVIUM_OCTEON_SIMULATOR is not set +# CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD is not set +CONFIG_MACH_TXX9=y CONFIG_TOSHIBA_JMR3927=y CONFIG_SOC_TX3927=y # CONFIG_TOSHIBA_FPCIB0 is not set @@ -54,12 +60,14 @@ CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_GENERIC_CLOCKEVENTS=y CONFIG_GENERIC_TIME=y CONFIG_GENERIC_CMOS_UPDATE=y -CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y +CONFIG_SCHED_OMIT_FRAME_POINTER=y CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y CONFIG_CEVT_TXX9=y CONFIG_GPIO_TXX9=y CONFIG_DMA_NONCOHERENT=y CONFIG_DMA_NEED_PCI_MAP_STATE=y +CONFIG_EARLY_PRINTK=y +CONFIG_SYS_HAS_EARLY_PRINTK=y # CONFIG_HOTPLUG_CPU is not set # CONFIG_NO_IOPORT is not set CONFIG_GENERIC_GPIO=y @@ -87,6 +95,7 @@ CONFIG_CPU_TX39XX=y # CONFIG_CPU_TX49XX is not set # CONFIG_CPU_R5000 is not set # CONFIG_CPU_R5432 is not set +# CONFIG_CPU_R5500 is not set # CONFIG_CPU_R6000 is not set # CONFIG_CPU_NEVADA is not set # CONFIG_CPU_R8000 is not set @@ -94,6 +103,7 @@ CONFIG_CPU_TX39XX=y # CONFIG_CPU_RM7000 is not set # CONFIG_CPU_RM9000 is not set # CONFIG_CPU_SB1 is not set +# CONFIG_CPU_CAVIUM_OCTEON is not set CONFIG_SYS_HAS_CPU_TX39XX=y CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y @@ -117,14 +127,12 @@ CONFIG_ARCH_FLATMEM_ENABLE=y CONFIG_ARCH_POPULATES_NODE_MAP=y CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_SPARSEMEM_STATIC is not set -# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 -# CONFIG_RESOURCES_64BIT is not set +# CONFIG_PHYS_ADDR_T_64BIT is not set CONFIG_ZONE_DMA_FLAG=0 CONFIG_VIRT_TO_BUS=y -# CONFIG_TICK_ONESHOT is not set +CONFIG_UNEVICTABLE_LRU=y # CONFIG_NO_HZ is not set # CONFIG_HIGH_RES_TIMERS is not set CONFIG_GENERIC_CLOCKEVENTS_BUILD=y @@ -159,6 +167,15 @@ CONFIG_SYSVIPC_SYSCTL=y # CONFIG_BSD_PROCESS_ACCT is not set # CONFIG_TASKSTATS is not set # CONFIG_AUDIT is not set + +# +# RCU Subsystem +# +CONFIG_CLASSIC_RCU=y +# CONFIG_TREE_RCU is not set +# CONFIG_PREEMPT_RCU is not set +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_PREEMPT_RCU_TRACE is not set # CONFIG_IKCONFIG is not set CONFIG_LOG_BUF_SHIFT=14 # CONFIG_CGROUPS is not set @@ -171,7 +188,6 @@ CONFIG_CC_OPTIMIZE_FOR_SIZE=y CONFIG_SYSCTL=y CONFIG_EMBEDDED=y CONFIG_SYSCTL_SYSCALL=y -CONFIG_SYSCTL_SYSCALL_CHECK=y CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_EXTRA_PASS is not set # CONFIG_HOTPLUG is not set @@ -188,26 +204,23 @@ CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y +CONFIG_AIO=y CONFIG_VM_EVENT_COUNTERS=y +CONFIG_PCI_QUIRKS=y CONFIG_SLAB=y # CONFIG_SLUB is not set # CONFIG_SLOB is not set # CONFIG_PROFILING is not set -# CONFIG_MARKERS is not set CONFIG_HAVE_OPROFILE=y -# CONFIG_HAVE_KPROBES is not set -# CONFIG_HAVE_KRETPROBES is not set -# CONFIG_HAVE_DMA_ATTRS is not set -CONFIG_PROC_PAGE_MONITOR=y +# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y -# CONFIG_TINY_SHMEM is not set CONFIG_BASE_SMALL=0 # CONFIG_MODULES is not set CONFIG_BLOCK=y # CONFIG_LBD is not set # CONFIG_BLK_DEV_IO_TRACE is not set -# CONFIG_LSF is not set +# CONFIG_BLK_DEV_INTEGRITY is not set # # IO Schedulers @@ -221,7 +234,7 @@ CONFIG_IOSCHED_CFQ=y CONFIG_DEFAULT_CFQ=y # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="cfq" -CONFIG_CLASSIC_RCU=y +# CONFIG_FREEZER is not set # # Bus options (PCI, PCMCIA, EISA, ISA, TC) @@ -231,12 +244,15 @@ CONFIG_PCI=y CONFIG_PCI_DOMAINS=y # CONFIG_ARCH_SUPPORTS_MSI is not set CONFIG_PCI_LEGACY=y +# CONFIG_PCI_STUB is not set CONFIG_MMU=y # # Executable file formats # CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set # CONFIG_BINFMT_MISC is not set CONFIG_TRAD_SIGNALS=y @@ -245,15 +261,12 @@ CONFIG_TRAD_SIGNALS=y # CONFIG_ARCH_SUSPEND_POSSIBLE=y # CONFIG_PM is not set - -# -# Networking -# CONFIG_NET=y # # Networking options # +CONFIG_COMPAT_NET_DEV_OPS=y CONFIG_PACKET=y # CONFIG_PACKET_MMAP is not set CONFIG_UNIX=y @@ -293,6 +306,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_IPX is not set # CONFIG_ATALK is not set # CONFIG_NET_SCHED is not set +# CONFIG_DCB is not set # # Network testing @@ -302,14 +316,9 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_CAN is not set # CONFIG_IRDA is not set # CONFIG_BT is not set - -# -# Wireless -# -# CONFIG_CFG80211 is not set -# CONFIG_WIRELESS_EXT is not set -# CONFIG_MAC80211 is not set -# CONFIG_IEEE80211 is not set +# CONFIG_PHONET is not set +# CONFIG_WIRELESS is not set +# CONFIG_WIMAX is not set # CONFIG_RFKILL is not set # @@ -323,7 +332,89 @@ CONFIG_STANDALONE=y CONFIG_PREVENT_FIRMWARE_BUILD=y # CONFIG_SYS_HYPERVISOR is not set # CONFIG_CONNECTOR is not set -# CONFIG_MTD is not set +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_CONCAT is not set +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_REDBOOT_PARTS is not set +CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_AR7_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +# CONFIG_MTD_BLKDEVS is not set +# CONFIG_MTD_BLOCK is not set +# CONFIG_MTD_BLOCK_RO is not set +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_MTD_OOPS is not set + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=y +CONFIG_MTD_JEDECPROBE=y +CONFIG_MTD_GEN_PROBE=y +# CONFIG_MTD_CFI_ADV_OPTIONS is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_CFI_INTELEXT is not set +CONFIG_MTD_CFI_AMDSTD=y +# CONFIG_MTD_CFI_STAA is not set +CONFIG_MTD_CFI_UTIL=y +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +CONFIG_MTD_PHYSMAP=y +# CONFIG_MTD_PHYSMAP_COMPAT is not set +# CONFIG_MTD_INTEL_VR_NOR is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_PMC551 is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +# CONFIG_MTD_NAND is not set +# CONFIG_MTD_ONENAND is not set + +# +# LPDDR flash memory drivers +# +# CONFIG_MTD_LPDDR is not set + +# +# UBI - Unsorted block images +# +# CONFIG_MTD_UBI is not set # CONFIG_PARPORT is not set CONFIG_BLK_DEV=y # CONFIG_BLK_CPQ_DA is not set @@ -336,6 +427,7 @@ CONFIG_BLK_DEV=y # CONFIG_BLK_DEV_RAM is not set # CONFIG_CDROM_PKTCDVD is not set # CONFIG_ATA_OVER_ETH is not set +# CONFIG_BLK_DEV_HD is not set # CONFIG_MISC_DEVICES is not set CONFIG_HAVE_IDE=y # CONFIG_IDE is not set @@ -361,7 +453,6 @@ CONFIG_HAVE_IDE=y # CONFIG_IEEE1394 is not set # CONFIG_I2O is not set CONFIG_NETDEVICES=y -# CONFIG_NETDEVICES_MULTIQUEUE is not set # CONFIG_DUMMY is not set # CONFIG_BONDING is not set # CONFIG_EQUALIZER is not set @@ -383,6 +474,9 @@ CONFIG_PHYLIB=y # CONFIG_BROADCOM_PHY is not set # CONFIG_ICPLUS_PHY is not set # CONFIG_REALTEK_PHY is not set +# CONFIG_NATIONAL_PHY is not set +# CONFIG_STE10XP is not set +# CONFIG_LSI_ET1011C_PHY is not set # CONFIG_FIXED_PHY is not set # CONFIG_MDIO_BITBANG is not set CONFIG_NET_ETHERNET=y @@ -392,6 +486,7 @@ CONFIG_NET_ETHERNET=y # CONFIG_SUNGEM is not set # CONFIG_CASSINI is not set # CONFIG_NET_VENDOR_3COM is not set +# CONFIG_SMC91X is not set # CONFIG_DM9000 is not set # CONFIG_NET_TULIP is not set # CONFIG_HP100 is not set @@ -399,6 +494,9 @@ CONFIG_NET_ETHERNET=y # CONFIG_IBM_NEW_EMAC_RGMII is not set # CONFIG_IBM_NEW_EMAC_TAH is not set # CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set CONFIG_NET_PCI=y # CONFIG_PCNET32 is not set # CONFIG_AMD8111_ETH is not set @@ -406,7 +504,6 @@ CONFIG_NET_PCI=y # CONFIG_B44 is not set # CONFIG_FORCEDETH is not set CONFIG_TC35815=y -# CONFIG_EEPRO100 is not set # CONFIG_E100 is not set # CONFIG_FEALNX is not set # CONFIG_NATSEMI is not set @@ -415,9 +512,11 @@ CONFIG_TC35815=y # CONFIG_R6040 is not set # CONFIG_SIS900 is not set # CONFIG_EPIC100 is not set +# CONFIG_SMSC9420 is not set # CONFIG_SUNDANCE is not set # CONFIG_TLAN is not set # CONFIG_VIA_RHINE is not set +# CONFIG_ATL2 is not set # CONFIG_NETDEV_1000 is not set # CONFIG_NETDEV_10000 is not set # CONFIG_TR is not set @@ -428,6 +527,10 @@ CONFIG_TC35815=y # CONFIG_WLAN_PRE80211 is not set # CONFIG_WLAN_80211 is not set # CONFIG_IWLWIFI_LEDS is not set + +# +# Enable WiMAX (Networking options) to see the WiMAX drivers +# # CONFIG_WAN is not set # CONFIG_FDDI is not set # CONFIG_PPP is not set @@ -440,27 +543,7 @@ CONFIG_TC35815=y # # Input device support # -CONFIG_INPUT=y -# CONFIG_INPUT_FF_MEMLESS is not set -# CONFIG_INPUT_POLLDEV is not set - -# -# Userland interfaces -# -# CONFIG_INPUT_MOUSEDEV is not set -# CONFIG_INPUT_JOYDEV is not set -# CONFIG_INPUT_EVDEV is not set -# CONFIG_INPUT_EVBUG is not set - -# -# Input Device Drivers -# -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -# CONFIG_INPUT_JOYSTICK is not set -# CONFIG_INPUT_TABLET is not set -# CONFIG_INPUT_TOUCHSCREEN is not set -# CONFIG_INPUT_MISC is not set +# CONFIG_INPUT is not set # # Hardware I/O ports @@ -517,10 +600,11 @@ CONFIG_LEGACY_PTY_COUNT=256 CONFIG_DEVPORT=y # CONFIG_I2C is not set # CONFIG_SPI is not set -CONFIG_HAVE_GPIO_LIB=y +CONFIG_ARCH_REQUIRE_GPIOLIB=y +CONFIG_GPIOLIB=y # -# GPIO Support +# Memory mapped GPIO expanders: # # @@ -528,6 +612,11 @@ CONFIG_HAVE_GPIO_LIB=y # # +# PCI GPIO expanders: +# +# CONFIG_GPIO_BT8XX is not set + +# # SPI GPIO expanders: # # CONFIG_W1 is not set @@ -542,6 +631,7 @@ CONFIG_WATCHDOG=y # Watchdog Device Drivers # # CONFIG_SOFT_WATCHDOG is not set +# CONFIG_ALIM7101_WDT is not set CONFIG_TXX9_WDT=y # @@ -549,18 +639,21 @@ CONFIG_TXX9_WDT=y # # CONFIG_PCIPCWATCHDOG is not set # CONFIG_WDTPCI is not set +CONFIG_SSB_POSSIBLE=y # # Sonics Silicon Backplane # -CONFIG_SSB_POSSIBLE=y # CONFIG_SSB is not set # # Multifunction device drivers # +# CONFIG_MFD_CORE is not set # CONFIG_MFD_SM501 is not set # CONFIG_HTC_PASIC3 is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_REGULATOR is not set # # Multimedia devices @@ -591,16 +684,26 @@ CONFIG_SSB_POSSIBLE=y # Display device support # # CONFIG_DISPLAY_SUPPORT is not set - -# -# Sound -# # CONFIG_SOUND is not set -# CONFIG_HID_SUPPORT is not set # CONFIG_USB_SUPPORT is not set # CONFIG_MMC is not set # CONFIG_MEMSTICK is not set -# CONFIG_NEW_LEDS is not set +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y + +# +# LED drivers +# +CONFIG_LEDS_GPIO=y + +# +# LED Triggers +# +CONFIG_LEDS_TRIGGERS=y +# CONFIG_LEDS_TRIGGER_TIMER is not set +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set +# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set # CONFIG_ACCESSIBILITY is not set # CONFIG_INFINIBAND is not set CONFIG_RTC_LIB=y @@ -626,27 +729,34 @@ CONFIG_RTC_INTF_DEV=y # Platform RTC drivers # # CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_DS1286 is not set # CONFIG_RTC_DRV_DS1511 is not set # CONFIG_RTC_DRV_DS1553 is not set CONFIG_RTC_DRV_DS1742=y # CONFIG_RTC_DRV_STK17TA8 is not set # CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set # CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_BQ4802 is not set # CONFIG_RTC_DRV_V3020 is not set # # on-CPU RTC drivers # +# CONFIG_DMADEVICES is not set # CONFIG_UIO is not set +# CONFIG_STAGING is not set # # File systems # # CONFIG_EXT2_FS is not set # CONFIG_EXT3_FS is not set +# CONFIG_EXT4_FS is not set # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set # CONFIG_FS_POSIX_ACL is not set +CONFIG_FILE_LOCKING=y # CONFIG_XFS_FS is not set # CONFIG_OCFS2_FS is not set CONFIG_DNOTIFY=y @@ -676,28 +786,17 @@ CONFIG_INOTIFY_USER=y CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y CONFIG_SYSFS=y # CONFIG_TMPFS is not set # CONFIG_HUGETLB_PAGE is not set # CONFIG_CONFIGFS_FS is not set - -# -# Miscellaneous filesystems -# -# CONFIG_HFSPLUS_FS is not set -# CONFIG_CRAMFS is not set -# CONFIG_VXFS_FS is not set -# CONFIG_MINIX_FS is not set -# CONFIG_HPFS_FS is not set -# CONFIG_QNX4FS_FS is not set -# CONFIG_ROMFS_FS is not set -# CONFIG_SYSV_FS is not set -# CONFIG_UFS_FS is not set +# CONFIG_MISC_FILESYSTEMS is not set CONFIG_NETWORK_FILESYSTEMS=y CONFIG_NFS_FS=y # CONFIG_NFS_V3 is not set -# CONFIG_NFSD is not set CONFIG_ROOT_NFS=y +# CONFIG_NFSD is not set CONFIG_LOCKD=y CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y @@ -726,7 +825,16 @@ CONFIG_FRAME_WARN=1024 # CONFIG_DEBUG_FS is not set # CONFIG_HEADERS_CHECK is not set # CONFIG_DEBUG_KERNEL is not set +# CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +CONFIG_SYSCTL_SYSCALL_CHECK=y + +# +# Tracers +# +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set # CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y CONFIG_CMDLINE="" # @@ -734,15 +842,18 @@ CONFIG_CMDLINE="" # # CONFIG_KEYS is not set # CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +# CONFIG_SECURITY_FILE_CAPABILITIES is not set # CONFIG_CRYPTO is not set # # Library routines # CONFIG_BITREVERSE=y -# CONFIG_GENERIC_FIND_FIRST_BIT is not set +CONFIG_GENERIC_FIND_LAST_BIT=y # CONFIG_CRC_CCITT is not set # CONFIG_CRC16 is not set +# CONFIG_CRC_T10DIF is not set # CONFIG_CRC_ITU_T is not set CONFIG_CRC32=y # CONFIG_CRC7 is not set diff --git a/arch/mips/configs/rbtx49xx_defconfig b/arch/mips/configs/rbtx49xx_defconfig index 83d5c58..1efe977 100644 --- a/arch/mips/configs/rbtx49xx_defconfig +++ b/arch/mips/configs/rbtx49xx_defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.26-rc9 -# Fri Jul 11 23:03:21 2008 +# Linux kernel version: 2.6.29-rc7 +# Wed Mar 4 23:08:06 2009 # CONFIG_MIPS=y @@ -18,8 +18,10 @@ CONFIG_MIPS=y # CONFIG_LEMOTE_FULONG is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SIM is not set -# CONFIG_MARKEINS is not set +# CONFIG_MACH_EMMA is not set # CONFIG_MACH_VR41XX is not set +# CONFIG_NXP_STB220 is not set +# CONFIG_NXP_STB225 is not set # CONFIG_PNX8550_JBS is not set # CONFIG_PNX8550_STB810 is not set # CONFIG_PMC_MSP is not set @@ -39,20 +41,28 @@ CONFIG_MIPS=y # CONFIG_SNI_RM is not set # CONFIG_MACH_TX39XX is not set CONFIG_MACH_TX49XX=y +# CONFIG_MIKROTIK_RB532 is not set # CONFIG_WR_PPMC is not set +# CONFIG_CAVIUM_OCTEON_SIMULATOR is not set +# CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD is not set +CONFIG_MACH_TXX9=y CONFIG_TOSHIBA_RBTX4927=y CONFIG_TOSHIBA_RBTX4938=y +CONFIG_TOSHIBA_RBTX4939=y CONFIG_SOC_TX4927=y CONFIG_SOC_TX4938=y +CONFIG_SOC_TX4939=y +CONFIG_TXX9_7SEGLED=y # CONFIG_TOSHIBA_FPCIB0 is not set CONFIG_PICMG_PCI_BACKPLANE_DEFAULT=y # # Multiplex Pin Select # -CONFIG_TOSHIBA_RBTX4938_MPLEX_PIO58_61=y +# CONFIG_TOSHIBA_RBTX4938_MPLEX_PIO58_61 is not set # CONFIG_TOSHIBA_RBTX4938_MPLEX_NAND is not set # CONFIG_TOSHIBA_RBTX4938_MPLEX_ATA is not set +CONFIG_TOSHIBA_RBTX4938_MPLEX_KEEP=y CONFIG_PCI_TX4927=y CONFIG_RWSEM_GENERIC_SPINLOCK=y # CONFIG_ARCH_HAS_ILOG2_U32 is not set @@ -64,14 +74,18 @@ CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_GENERIC_CLOCKEVENTS=y CONFIG_GENERIC_TIME=y CONFIG_GENERIC_CMOS_UPDATE=y -CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y +CONFIG_SCHED_OMIT_FRAME_POINTER=y CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +CONFIG_CEVT_R4K_LIB=y CONFIG_CEVT_R4K=y CONFIG_CEVT_TXX9=y +CONFIG_CSRC_R4K_LIB=y CONFIG_CSRC_R4K=y CONFIG_GPIO_TXX9=y CONFIG_DMA_NONCOHERENT=y CONFIG_DMA_NEED_PCI_MAP_STATE=y +CONFIG_EARLY_PRINTK=y +CONFIG_SYS_HAS_EARLY_PRINTK=y # CONFIG_HOTPLUG_CPU is not set # CONFIG_NO_IOPORT is not set CONFIG_GENERIC_GPIO=y @@ -100,6 +114,7 @@ CONFIG_MIPS_L1_CACHE_SHIFT=5 CONFIG_CPU_TX49XX=y # CONFIG_CPU_R5000 is not set # CONFIG_CPU_R5432 is not set +# CONFIG_CPU_R5500 is not set # CONFIG_CPU_R6000 is not set # CONFIG_CPU_NEVADA is not set # CONFIG_CPU_R8000 is not set @@ -107,6 +122,7 @@ CONFIG_CPU_TX49XX=y # CONFIG_CPU_RM7000 is not set # CONFIG_CPU_RM9000 is not set # CONFIG_CPU_SB1 is not set +# CONFIG_CPU_CAVIUM_OCTEON is not set CONFIG_SYS_HAS_CPU_TX49XX=y CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y @@ -134,13 +150,12 @@ CONFIG_ARCH_FLATMEM_ENABLE=y CONFIG_ARCH_POPULATES_NODE_MAP=y CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y -# CONFIG_SPARSEMEM_STATIC is not set -# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 -# CONFIG_RESOURCES_64BIT is not set +# CONFIG_PHYS_ADDR_T_64BIT is not set CONFIG_ZONE_DMA_FLAG=0 CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y CONFIG_TICK_ONESHOT=y CONFIG_NO_HZ=y CONFIG_HIGH_RES_TIMERS=y @@ -176,6 +191,15 @@ CONFIG_SYSVIPC_SYSCTL=y # CONFIG_BSD_PROCESS_ACCT is not set # CONFIG_TASKSTATS is not set # CONFIG_AUDIT is not set + +# +# RCU Subsystem +# +CONFIG_CLASSIC_RCU=y +# CONFIG_TREE_RCU is not set +# CONFIG_PREEMPT_RCU is not set +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_PREEMPT_RCU_TRACE is not set CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=14 @@ -190,7 +214,6 @@ CONFIG_CC_OPTIMIZE_FOR_SIZE=y CONFIG_SYSCTL=y CONFIG_EMBEDDED=y CONFIG_SYSCTL_SYSCALL=y -CONFIG_SYSCTL_SYSCALL_CHECK=y CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_EXTRA_PASS is not set # CONFIG_HOTPLUG is not set @@ -207,30 +230,26 @@ CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y +CONFIG_AIO=y CONFIG_VM_EVENT_COUNTERS=y +CONFIG_PCI_QUIRKS=y CONFIG_SLAB=y # CONFIG_SLUB is not set # CONFIG_SLOB is not set # CONFIG_PROFILING is not set -# CONFIG_MARKERS is not set CONFIG_HAVE_OPROFILE=y -# CONFIG_HAVE_KPROBES is not set -# CONFIG_HAVE_KRETPROBES is not set -# CONFIG_HAVE_DMA_ATTRS is not set -CONFIG_PROC_PAGE_MONITOR=y +# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set CONFIG_SLABINFO=y -# CONFIG_TINY_SHMEM is not set CONFIG_BASE_SMALL=0 CONFIG_MODULES=y # CONFIG_MODULE_FORCE_LOAD is not set -# CONFIG_MODULE_UNLOAD is not set +CONFIG_MODULE_UNLOAD=y # CONFIG_MODVERSIONS is not set # CONFIG_MODULE_SRCVERSION_ALL is not set -CONFIG_KMOD=y CONFIG_BLOCK=y # CONFIG_LBD is not set # CONFIG_BLK_DEV_IO_TRACE is not set -# CONFIG_LSF is not set +# CONFIG_BLK_DEV_INTEGRITY is not set # # IO Schedulers @@ -244,7 +263,8 @@ CONFIG_DEFAULT_AS=y # CONFIG_DEFAULT_CFQ is not set # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="anticipatory" -CONFIG_CLASSIC_RCU=y +# CONFIG_PROBE_INITRD_HEADER is not set +# CONFIG_FREEZER is not set # # Bus options (PCI, PCMCIA, EISA, ISA, TC) @@ -254,12 +274,15 @@ CONFIG_PCI=y CONFIG_PCI_DOMAINS=y # CONFIG_ARCH_SUPPORTS_MSI is not set # CONFIG_PCI_LEGACY is not set +# CONFIG_PCI_STUB is not set CONFIG_MMU=y # # Executable file formats # CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set # CONFIG_BINFMT_MISC is not set CONFIG_TRAD_SIGNALS=y @@ -268,15 +291,12 @@ CONFIG_TRAD_SIGNALS=y # CONFIG_ARCH_SUSPEND_POSSIBLE=y # CONFIG_PM is not set - -# -# Networking -# CONFIG_NET=y # # Networking options # +CONFIG_COMPAT_NET_DEV_OPS=y CONFIG_PACKET=y # CONFIG_PACKET_MMAP is not set CONFIG_UNIX=y @@ -318,6 +338,7 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_IPX is not set # CONFIG_ATALK is not set # CONFIG_NET_SCHED is not set +# CONFIG_DCB is not set # # Network testing @@ -327,14 +348,9 @@ CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_CAN is not set # CONFIG_IRDA is not set # CONFIG_BT is not set - -# -# Wireless -# -# CONFIG_CFG80211 is not set -# CONFIG_WIRELESS_EXT is not set -# CONFIG_MAC80211 is not set -# CONFIG_IEEE80211 is not set +# CONFIG_PHONET is not set +# CONFIG_WIRELESS is not set +# CONFIG_WIMAX is not set # CONFIG_RFKILL is not set # @@ -348,7 +364,90 @@ CONFIG_STANDALONE=y CONFIG_PREVENT_FIRMWARE_BUILD=y # CONFIG_SYS_HYPERVISOR is not set # CONFIG_CONNECTOR is not set -# CONFIG_MTD is not set +CONFIG_MTD=y +# CONFIG_MTD_DEBUG is not set +# CONFIG_MTD_CONCAT is not set +CONFIG_MTD_PARTITIONS=y +# CONFIG_MTD_TESTS is not set +# CONFIG_MTD_REDBOOT_PARTS is not set +CONFIG_MTD_CMDLINE_PARTS=y +# CONFIG_MTD_AR7_PARTS is not set + +# +# User Modules And Translation Layers +# +CONFIG_MTD_CHAR=y +# CONFIG_MTD_BLKDEVS is not set +# CONFIG_MTD_BLOCK is not set +# CONFIG_MTD_BLOCK_RO is not set +# CONFIG_FTL is not set +# CONFIG_NFTL is not set +# CONFIG_INFTL is not set +# CONFIG_RFD_FTL is not set +# CONFIG_SSFDC is not set +# CONFIG_MTD_OOPS is not set + +# +# RAM/ROM/Flash chip drivers +# +CONFIG_MTD_CFI=y +CONFIG_MTD_JEDECPROBE=y +CONFIG_MTD_GEN_PROBE=y +# CONFIG_MTD_CFI_ADV_OPTIONS is not set +CONFIG_MTD_MAP_BANK_WIDTH_1=y +CONFIG_MTD_MAP_BANK_WIDTH_2=y +CONFIG_MTD_MAP_BANK_WIDTH_4=y +# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set +# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set +CONFIG_MTD_CFI_I1=y +CONFIG_MTD_CFI_I2=y +# CONFIG_MTD_CFI_I4 is not set +# CONFIG_MTD_CFI_I8 is not set +# CONFIG_MTD_CFI_INTELEXT is not set +CONFIG_MTD_CFI_AMDSTD=y +# CONFIG_MTD_CFI_STAA is not set +CONFIG_MTD_CFI_UTIL=y +# CONFIG_MTD_RAM is not set +# CONFIG_MTD_ROM is not set +# CONFIG_MTD_ABSENT is not set + +# +# Mapping drivers for chip access +# +# CONFIG_MTD_COMPLEX_MAPPINGS is not set +CONFIG_MTD_PHYSMAP=y +# CONFIG_MTD_PHYSMAP_COMPAT is not set +# CONFIG_MTD_INTEL_VR_NOR is not set +# CONFIG_MTD_PLATRAM is not set + +# +# Self-contained MTD device drivers +# +# CONFIG_MTD_PMC551 is not set +# CONFIG_MTD_SLRAM is not set +# CONFIG_MTD_PHRAM is not set +# CONFIG_MTD_MTDRAM is not set +# CONFIG_MTD_BLOCK2MTD is not set + +# +# Disk-On-Chip Device Drivers +# +# CONFIG_MTD_DOC2000 is not set +# CONFIG_MTD_DOC2001 is not set +# CONFIG_MTD_DOC2001PLUS is not set +# CONFIG_MTD_NAND is not set +# CONFIG_MTD_ONENAND is not set + +# +# LPDDR flash memory drivers +# +# CONFIG_MTD_LPDDR is not set + +# +# UBI - Unsorted block images +# +# CONFIG_MTD_UBI is not set # CONFIG_PARPORT is not set CONFIG_BLK_DEV=y # CONFIG_BLK_CPQ_DA is not set @@ -365,9 +464,60 @@ CONFIG_BLK_DEV_RAM_SIZE=8192 # CONFIG_BLK_DEV_XIP is not set # CONFIG_CDROM_PKTCDVD is not set # CONFIG_ATA_OVER_ETH is not set +# CONFIG_BLK_DEV_HD is not set # CONFIG_MISC_DEVICES is not set CONFIG_HAVE_IDE=y -# CONFIG_IDE is not set +CONFIG_IDE=y + +# +# Please see Documentation/ide/ide.txt for help/info on IDE drives +# +CONFIG_IDE_TIMINGS=y +# CONFIG_BLK_DEV_IDE_SATA is not set +CONFIG_IDE_GD=y +CONFIG_IDE_GD_ATA=y +# CONFIG_IDE_GD_ATAPI is not set +# CONFIG_BLK_DEV_IDECD is not set +# CONFIG_BLK_DEV_IDETAPE is not set +# CONFIG_IDE_TASK_IOCTL is not set +CONFIG_IDE_PROC_FS=y + +# +# IDE chipset support/bugfixes +# +# CONFIG_IDE_GENERIC is not set +# CONFIG_BLK_DEV_PLATFORM is not set +CONFIG_BLK_DEV_IDEDMA_SFF=y + +# +# PCI IDE chipsets support +# +# CONFIG_BLK_DEV_GENERIC is not set +# CONFIG_BLK_DEV_AEC62XX is not set +# CONFIG_BLK_DEV_ALI15X3 is not set +# CONFIG_BLK_DEV_AMD74XX is not set +# CONFIG_BLK_DEV_CMD64X is not set +# CONFIG_BLK_DEV_TRIFLEX is not set +# CONFIG_BLK_DEV_CS5530 is not set +# CONFIG_BLK_DEV_HPT366 is not set +# CONFIG_BLK_DEV_JMICRON is not set +# CONFIG_BLK_DEV_SC1200 is not set +# CONFIG_BLK_DEV_PIIX is not set +# CONFIG_BLK_DEV_IT8172 is not set +# CONFIG_BLK_DEV_IT8213 is not set +# CONFIG_BLK_DEV_IT821X is not set +# CONFIG_BLK_DEV_NS87415 is not set +# CONFIG_BLK_DEV_PDC202XX_OLD is not set +# CONFIG_BLK_DEV_PDC202XX_NEW is not set +# CONFIG_BLK_DEV_SVWKS is not set +# CONFIG_BLK_DEV_SIIMAGE is not set +# CONFIG_BLK_DEV_SLC90E66 is not set +# CONFIG_BLK_DEV_TRM290 is not set +# CONFIG_BLK_DEV_VIA82CXXX is not set +# CONFIG_BLK_DEV_TC86C001 is not set +CONFIG_BLK_DEV_IDE_TX4938=y +CONFIG_BLK_DEV_IDE_TX4939=y +CONFIG_BLK_DEV_IDEDMA=y # # SCSI device support @@ -390,7 +540,6 @@ CONFIG_HAVE_IDE=y # CONFIG_IEEE1394 is not set # CONFIG_I2O is not set CONFIG_NETDEVICES=y -# CONFIG_NETDEVICES_MULTIQUEUE is not set # CONFIG_DUMMY is not set # CONFIG_BONDING is not set # CONFIG_EQUALIZER is not set @@ -412,15 +561,19 @@ CONFIG_PHYLIB=y # CONFIG_BROADCOM_PHY is not set # CONFIG_ICPLUS_PHY is not set # CONFIG_REALTEK_PHY is not set +# CONFIG_NATIONAL_PHY is not set +# CONFIG_STE10XP is not set +# CONFIG_LSI_ET1011C_PHY is not set # CONFIG_FIXED_PHY is not set # CONFIG_MDIO_BITBANG is not set CONFIG_NET_ETHERNET=y -# CONFIG_MII is not set +CONFIG_MII=y # CONFIG_AX88796 is not set # CONFIG_HAPPYMEAL is not set # CONFIG_SUNGEM is not set # CONFIG_CASSINI is not set # CONFIG_NET_VENDOR_3COM is not set +CONFIG_SMC91X=y # CONFIG_DM9000 is not set # CONFIG_NET_TULIP is not set # CONFIG_HP100 is not set @@ -429,6 +582,9 @@ CONFIG_NE2000=y # CONFIG_IBM_NEW_EMAC_RGMII is not set # CONFIG_IBM_NEW_EMAC_TAH is not set # CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set CONFIG_NET_PCI=y # CONFIG_PCNET32 is not set # CONFIG_AMD8111_ETH is not set @@ -436,7 +592,6 @@ CONFIG_NET_PCI=y # CONFIG_B44 is not set # CONFIG_FORCEDETH is not set CONFIG_TC35815=y -# CONFIG_EEPRO100 is not set # CONFIG_E100 is not set # CONFIG_FEALNX is not set # CONFIG_NATSEMI is not set @@ -445,9 +600,11 @@ CONFIG_TC35815=y # CONFIG_R6040 is not set # CONFIG_SIS900 is not set # CONFIG_EPIC100 is not set +# CONFIG_SMSC9420 is not set # CONFIG_SUNDANCE is not set # CONFIG_TLAN is not set # CONFIG_VIA_RHINE is not set +# CONFIG_ATL2 is not set # CONFIG_NETDEV_1000 is not set # CONFIG_NETDEV_10000 is not set # CONFIG_TR is not set @@ -458,6 +615,10 @@ CONFIG_TC35815=y # CONFIG_WLAN_PRE80211 is not set # CONFIG_WLAN_80211 is not set # CONFIG_IWLWIFI_LEDS is not set + +# +# Enable WiMAX (Networking options) to see the WiMAX drivers +# # CONFIG_WAN is not set # CONFIG_FDDI is not set # CONFIG_PPP is not set @@ -502,6 +663,7 @@ CONFIG_SERIAL_TXX9_CONSOLE=y CONFIG_SERIAL_TXX9_STDSERIAL=y # CONFIG_SERIAL_JSM is not set CONFIG_UNIX98_PTYS=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=256 # CONFIG_IPMI_HANDLER is not set @@ -517,17 +679,19 @@ CONFIG_SPI_MASTER=y # # SPI Master Controller Drivers # +# CONFIG_SPI_BITBANG is not set +# CONFIG_SPI_GPIO is not set CONFIG_SPI_TXX9=y # # SPI Protocol Masters # -CONFIG_EEPROM_AT25=y # CONFIG_SPI_TLE62X0 is not set -CONFIG_HAVE_GPIO_LIB=y +CONFIG_ARCH_REQUIRE_GPIOLIB=y +CONFIG_GPIOLIB=y # -# GPIO Support +# Memory mapped GPIO expanders: # # @@ -535,8 +699,14 @@ CONFIG_HAVE_GPIO_LIB=y # # +# PCI GPIO expanders: +# +# CONFIG_GPIO_BT8XX is not set + +# # SPI GPIO expanders: # +# CONFIG_GPIO_MAX7301 is not set # CONFIG_GPIO_MCP23S08 is not set # CONFIG_W1 is not set # CONFIG_POWER_SUPPLY is not set @@ -550,6 +720,7 @@ CONFIG_WATCHDOG=y # Watchdog Device Drivers # # CONFIG_SOFT_WATCHDOG is not set +# CONFIG_ALIM7101_WDT is not set CONFIG_TXX9_WDT=m # @@ -557,18 +728,21 @@ CONFIG_TXX9_WDT=m # # CONFIG_PCIPCWATCHDOG is not set # CONFIG_WDTPCI is not set +CONFIG_SSB_POSSIBLE=y # # Sonics Silicon Backplane # -CONFIG_SSB_POSSIBLE=y # CONFIG_SSB is not set # # Multifunction device drivers # +# CONFIG_MFD_CORE is not set # CONFIG_MFD_SM501 is not set # CONFIG_HTC_PASIC3 is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_REGULATOR is not set # # Multimedia devices @@ -599,15 +773,27 @@ CONFIG_SSB_POSSIBLE=y # Display device support # # CONFIG_DISPLAY_SUPPORT is not set - -# -# Sound -# # CONFIG_SOUND is not set # CONFIG_USB_SUPPORT is not set # CONFIG_MMC is not set # CONFIG_MEMSTICK is not set -# CONFIG_NEW_LEDS is not set +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y + +# +# LED drivers +# +CONFIG_LEDS_GPIO=y + +# +# LED Triggers +# +CONFIG_LEDS_TRIGGERS=y +# CONFIG_LEDS_TRIGGER_TIMER is not set +CONFIG_LEDS_TRIGGER_IDE_DISK=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set +# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set # CONFIG_ACCESSIBILITY is not set # CONFIG_INFINIBAND is not set CONFIG_RTC_LIB=y @@ -628,35 +814,47 @@ CONFIG_RTC_INTF_DEV_UIE_EMUL=y # # SPI RTC drivers # +# CONFIG_RTC_DRV_M41T94 is not set +# CONFIG_RTC_DRV_DS1305 is not set +# CONFIG_RTC_DRV_DS1390 is not set # CONFIG_RTC_DRV_MAX6902 is not set # CONFIG_RTC_DRV_R9701 is not set CONFIG_RTC_DRV_RS5C348=y +# CONFIG_RTC_DRV_DS3234 is not set # # Platform RTC drivers # # CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_DS1286 is not set # CONFIG_RTC_DRV_DS1511 is not set # CONFIG_RTC_DRV_DS1553 is not set CONFIG_RTC_DRV_DS1742=y # CONFIG_RTC_DRV_STK17TA8 is not set # CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set # CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_BQ4802 is not set # CONFIG_RTC_DRV_V3020 is not set # # on-CPU RTC drivers # +CONFIG_RTC_DRV_TX4939=y +# CONFIG_DMADEVICES is not set # CONFIG_UIO is not set +# CONFIG_STAGING is not set # # File systems # # CONFIG_EXT2_FS is not set # CONFIG_EXT3_FS is not set +# CONFIG_EXT4_FS is not set # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set CONFIG_FS_POSIX_ACL=y +CONFIG_FILE_LOCKING=y # CONFIG_XFS_FS is not set # CONFIG_OCFS2_FS is not set # CONFIG_DNOTIFY is not set @@ -687,30 +885,19 @@ CONFIG_GENERIC_ACL=y CONFIG_PROC_FS=y # CONFIG_PROC_KCORE is not set CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y CONFIG_SYSFS=y CONFIG_TMPFS=y CONFIG_TMPFS_POSIX_ACL=y # CONFIG_HUGETLB_PAGE is not set # CONFIG_CONFIGFS_FS is not set - -# -# Miscellaneous filesystems -# -# CONFIG_HFSPLUS_FS is not set -# CONFIG_CRAMFS is not set -# CONFIG_VXFS_FS is not set -# CONFIG_MINIX_FS is not set -# CONFIG_HPFS_FS is not set -# CONFIG_QNX4FS_FS is not set -# CONFIG_ROMFS_FS is not set -# CONFIG_SYSV_FS is not set -# CONFIG_UFS_FS is not set +# CONFIG_MISC_FILESYSTEMS is not set CONFIG_NETWORK_FILESYSTEMS=y CONFIG_NFS_FS=y CONFIG_NFS_V3=y # CONFIG_NFS_V3_ACL is not set -# CONFIG_NFSD is not set CONFIG_ROOT_NFS=y +# CONFIG_NFSD is not set CONFIG_LOCKD=y CONFIG_LOCKD_V4=y CONFIG_NFS_COMMON=y @@ -740,7 +927,16 @@ CONFIG_FRAME_WARN=1024 CONFIG_DEBUG_FS=y # CONFIG_HEADERS_CHECK is not set # CONFIG_DEBUG_KERNEL is not set +# CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +CONFIG_SYSCTL_SYSCALL_CHECK=y + +# +# Tracers +# +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set # CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y CONFIG_CMDLINE="" # @@ -748,15 +944,18 @@ CONFIG_CMDLINE="" # # CONFIG_KEYS is not set # CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +# CONFIG_SECURITY_FILE_CAPABILITIES is not set # CONFIG_CRYPTO is not set # # Library routines # CONFIG_BITREVERSE=y -# CONFIG_GENERIC_FIND_FIRST_BIT is not set +CONFIG_GENERIC_FIND_LAST_BIT=y # CONFIG_CRC_CCITT is not set # CONFIG_CRC16 is not set +# CONFIG_CRC_T10DIF is not set # CONFIG_CRC_ITU_T is not set CONFIG_CRC32=y # CONFIG_CRC7 is not set -- 1.5.6.3 From ralf@h5.dl5rb.org.uk Wed Mar 4 15:44:35 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 04 Mar 2009 15:44:37 +0000 (GMT) Received: from localhost.localdomain ([127.0.0.1]:7066 "EHLO h5.dl5rb.org.uk") by ftp.linux-mips.org with ESMTP id S21365601AbZCDPof (ORCPT ); Wed, 4 Mar 2009 15:44:35 +0000 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id n24FiQlo019538; Wed, 4 Mar 2009 15:44:26 GMT Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id n24FiIYL019535; Wed, 4 Mar 2009 15:44:18 GMT Date: Wed, 4 Mar 2009 15:44:18 +0000 From: Ralf Baechle To: Brian Foster Cc: David Daney , "Maciej W. Rozycki" , linux-mips@linux-mips.org, libc-ports@sourceware.org, "Maciej W. Rozycki" Subject: Re: [PATCH, RFC] MIPS: Implement the getcontext API Message-ID: <20090304154418.GA13464@linux-mips.org> References: <49AD6139.60209@caviumnetworks.com> <200903040919.29294.brian.foster@innova-card.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <200903040919.29294.brian.foster@innova-card.com> User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22000 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Wed, Mar 04, 2009 at 09:19:28AM +0100, Brian Foster wrote: > On Tuesday 03 March 2009 17:56:25 David Daney wrote: > >[ ... ] > > When (and if) we move the sigreturn trampoline to a vdso we should be > > able to maintain the ABI. > > it's more a matter of “when” rather than “if”. > there is still an intention here to use XI (we > have SmartMIPS), which requires not using the > signal (or FP) trampoline on the stack. > > moving the signal trampoline to a vdso (which > is(? was?) called, maybe misleadingly, ‘vsyscall’, > on other architectures) is the obvious solution to > that part of the puzzle. and yes, it is possible > to maintain the ABI; the signal trampoline is still > also put on the stack, and modulo XI, would work if > used — the trampoline-on-stack is simply not used > if there is a vdso with the signal trampoline. We generally want to get rid of stack trampolines. Trampolines require cacheflushing which especially on SMP systems can be a rather expensive operation. Ralf From David.Daney@caviumnetworks.com Wed Mar 4 16:38:45 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 04 Mar 2009 16:38:48 +0000 (GMT) Received: from mail3.caviumnetworks.com ([12.108.191.235]:53911 "EHLO mail3.caviumnetworks.com") by ftp.linux-mips.org with ESMTP id S21365663AbZCDQip (ORCPT ); Wed, 4 Mar 2009 16:38:45 +0000 Received: from exch4.caveonetworks.com (Not Verified[192.168.16.23]) by mail3.caviumnetworks.com with MailMarshal (v6,2,2,3503) id ; Wed, 04 Mar 2009 11:37:20 -0500 Received: from exch4.caveonetworks.com ([192.168.16.23]) by exch4.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Wed, 4 Mar 2009 08:36:45 -0800 Received: from dd1.caveonetworks.com ([64.169.86.201]) by exch4.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Wed, 4 Mar 2009 08:36:45 -0800 Message-ID: <49AEAE1D.5030205@caviumnetworks.com> Date: Wed, 04 Mar 2009 08:36:45 -0800 From: David Daney User-Agent: Thunderbird 2.0.0.19 (X11/20090105) MIME-Version: 1.0 To: Daniel Jacobowitz CC: Brian Foster , "Maciej W. Rozycki" , Ralf Baechle , linux-mips@linux-mips.org, libc-ports@sourceware.org, "Maciej W. Rozycki" Subject: Re: [PATCH, RFC] MIPS: Implement the getcontext API References: <49AD6139.60209@caviumnetworks.com> <200903040919.29294.brian.foster@innova-card.com> <20090304121732.GA28381@caradoc.them.org> In-Reply-To: <20090304121732.GA28381@caradoc.them.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-OriginalArrivalTime: 04 Mar 2009 16:36:45.0367 (UTC) FILETIME=[680A8C70:01C99CE7] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22001 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Daniel Jacobowitz wrote: > On Wed, Mar 04, 2009 at 09:19:28AM +0100, Brian Foster wrote: >> moving the signal trampoline to a vdso (which >> is(? was?) called, maybe misleadingly, ‘vsyscall’, >> on other architectures) is the obvious solution to >> that part of the puzzle. and yes, it is possible >> to maintain the ABI; the signal trampoline is still >> also put on the stack, and modulo XI, would work if >> used — the trampoline-on-stack is simply not used >> if there is a vdso with the signal trampoline. > > That won't quite retain the ABI: you need to make sure everyone > locates it by using the stack pointer instead of the return pc. > Fortunately, GCC uses the return PC only for instruction matching > today. I have a vague memory it used to use the stack pointer but > this was more reliable. That is correct. Due to various errata the trampoline cannot always be at a fixed offset to the signal context bits. So we had to use the return PC as you indicate. David Daney From Mark.Asselstine@windriver.com Wed Mar 4 17:53:16 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 04 Mar 2009 17:53:19 +0000 (GMT) Received: from mail.windriver.com ([147.11.1.11]:51653 "EHLO mail.wrs.com") by ftp.linux-mips.org with ESMTP id S21365662AbZCDRxQ (ORCPT ); Wed, 4 Mar 2009 17:53:16 +0000 Received: from ALA-MAIL03.corp.ad.wrs.com (ala-mail03 [147.11.57.144]) by mail.wrs.com (8.13.6/8.13.6) with ESMTP id n24Hr5IP023894; Wed, 4 Mar 2009 09:53:06 -0800 (PST) Received: from ala-mail06.corp.ad.wrs.com ([147.11.57.147]) by ALA-MAIL03.corp.ad.wrs.com with Microsoft SMTPSVC(6.0.3790.1830); Wed, 4 Mar 2009 09:53:04 -0800 Received: from yow-masselst-d1.localnet ([128.224.146.23]) by ala-mail06.corp.ad.wrs.com with Microsoft SMTPSVC(6.0.3790.1830); Wed, 4 Mar 2009 09:53:04 -0800 From: "M. Asselstine" Organization: Wind River Systems Inc. To: Robert Richter Subject: Re: [PATCH V2] oprofile: VR5500 performance counter driver Date: Wed, 4 Mar 2009 12:53:03 -0500 User-Agent: KMail/1.11.0 (Linux/2.6.27-9-generic; KDE/4.2.0; x86_64; ; ) Cc: Ralf Baechle , linux-mips@linux-mips.org, oprofile-list@lists.sf.net References: <20090225165953.GF25042@erda.amd.com> <1235681374-19952-1-git-send-email-mark.asselstine@windriver.com> <20090303110755.GD10085@erda.amd.com> In-Reply-To: <20090303110755.GD10085@erda.amd.com> MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit Content-Disposition: inline Message-Id: <200903041253.03682.Mark.Asselstine@windriver.com> X-OriginalArrivalTime: 04 Mar 2009 17:53:04.0648 (UTC) FILETIME=[11816080:01C99CF2] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22002 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: Mark.Asselstine@windriver.com Precedence: bulk X-list: linux-mips On Tuesday 03 March 2009, Robert Richter wrote: > On 26.02.09 15:49:34, Mark Asselstine wrote: > > This is inspired by op_model_mipsxx.c with some modification > > in regards to register layout and overflow handling. This has > > been tested on a NEC VR5500 board and shown to produce sane > > results. > > > > Signed-off-by: Mark Asselstine > > --- > > > > I have left this as a new file as there is enough differences > > to make combining it combersome. If pushed I would possibly > > change my mind but I am not convinced yet. The userspace > > events are seen as mips/vr5500 so if there is a desire to > > have everything be r5500 some userspace changes would need > > to be made. > > > > arch/mips/oprofile/Makefile | 1 + > > arch/mips/oprofile/common.c | 5 + > > arch/mips/oprofile/op_model_r5500.c | 161 > > +++++++++++++++++++++++++++++++++++ > > Mark, > > the Kconfig option for CONFIG_CPU_R5500 is still missing otherwise the > patch itself looks fine. > Hmmm, what tree are you looking at? I see it in Linus' tree as well as Ralf's .29 RCs and master. Mark > Ralf, > > do you agree on introducing a separate file for this cpu model? > Please ack. > > Thanks, > > -Robert > > > 3 files changed, 167 insertions(+), 0 deletions(-) > > create mode 100644 arch/mips/oprofile/op_model_r5500.c > > > > diff --git a/arch/mips/oprofile/Makefile b/arch/mips/oprofile/Makefile > > index bf3be6f..586e64e 100644 > > --- a/arch/mips/oprofile/Makefile > > +++ b/arch/mips/oprofile/Makefile > > @@ -14,4 +14,5 @@ oprofile-$(CONFIG_CPU_MIPS32) += op_model_mipsxx.o > > oprofile-$(CONFIG_CPU_MIPS64) += op_model_mipsxx.o > > oprofile-$(CONFIG_CPU_R10000) += op_model_mipsxx.o > > oprofile-$(CONFIG_CPU_SB1) += op_model_mipsxx.o > > +oprofile-$(CONFIG_CPU_R5500) += op_model_r5500.o > > oprofile-$(CONFIG_CPU_RM9000) += op_model_rm9000.o > > diff --git a/arch/mips/oprofile/common.c b/arch/mips/oprofile/common.c > > index 3bf3354..26780c7 100644 > > --- a/arch/mips/oprofile/common.c > > +++ b/arch/mips/oprofile/common.c > > @@ -16,6 +16,7 @@ > > > > extern struct op_mips_model op_model_mipsxx_ops __attribute__((weak)); > > extern struct op_mips_model op_model_rm9000_ops __attribute__((weak)); > > +extern struct op_mips_model op_model_r5500_ops __attribute__((weak)); > > > > static struct op_mips_model *model; > > > > @@ -93,6 +94,10 @@ int __init oprofile_arch_init(struct > > oprofile_operations *ops) case CPU_RM9000: > > lmodel = &op_model_rm9000_ops; > > break; > > + > > + case CPU_R5500: > > + lmodel = &op_model_r5500_ops; > > + break; > > }; > > > > if (!lmodel) > > diff --git a/arch/mips/oprofile/op_model_r5500.c > > b/arch/mips/oprofile/op_model_r5500.c new file mode 100644 > > index 0000000..9b0d20f > > --- /dev/null > > +++ b/arch/mips/oprofile/op_model_r5500.c > > @@ -0,0 +1,161 @@ > > +/* > > + * This file is subject to the terms and conditions of the GNU General > > Public + * License. See the file "COPYING" in the main directory of this > > archive + * for more details. > > + * > > + * Copyright (c) 2009 Wind River Systems, Inc. > > + * > > + * Derived from op_model_mipsxx.c Copyright Ralf Baechle, MIPS > > Technologies Inc + */ > > +#include > > +#include > > +#include > > + > > +#include "op_impl.h" > > + > > +#define M_PERFCTL_EXL (1UL << 0) > > +#define M_PERFCTL_KERNEL (1UL << 1) > > +#define M_PERFCTL_SUPERVISOR (1UL << 2) > > +#define M_PERFCTL_USER (1UL << 3) > > +#define M_PERFCTL_INTERRUPT_ENABLE (1UL << 4) > > +#define M_PERFCTL_INTERRUPT (1UL << 5) > > +#define M_PERFCTL_EVENT(event) (((event) & 0xf) << 6) > > +#define M_PERFCTL_COUNT_ENABLE (1UL << 10) > > + > > +#define NUM_COUNTERS 2 > > + > > +static int (*save_perf_irq) (void); > > + > > +struct op_mips_model op_model_r5500_ops; > > + > > +static struct r5500_register_config { > > + unsigned int control[NUM_COUNTERS]; > > + unsigned int counter[NUM_COUNTERS]; > > +} reg; > > + > > +/* Compute all of the registers in preparation for enabling profiling. > > */ +static void r5500_reg_setup(struct op_counter_config *ctr) > > +{ > > + int i; > > + unsigned int counters = NUM_COUNTERS; > > + > > + /* Compute the performance counter control word. */ > > + for (i = 0; i < counters; i++) { > > + reg.control[i] = 0; > > + reg.counter[i] = 0; > > + > > + if (!ctr[i].enabled) > > + continue; > > + > > + reg.control[i] = M_PERFCTL_EVENT(ctr[i].event) | > > + M_PERFCTL_INTERRUPT_ENABLE | M_PERFCTL_COUNT_ENABLE; > > + if (ctr[i].kernel) > > + reg.control[i] |= M_PERFCTL_KERNEL; > > + if (ctr[i].user) > > + reg.control[i] |= M_PERFCTL_USER; > > + if (ctr[i].exl) > > + reg.control[i] |= M_PERFCTL_EXL; > > + > > + reg.counter[i] = 0xffffffff - ctr[i].count + 1; > > + } > > +} > > + > > +/* Program all of the registers in preparation for enabling profiling. > > */ +static void r5500_cpu_setup(void *args) > > +{ > > + write_c0_perfctrl1(0); > > + write_c0_perfcntr1(reg.counter[1]); > > + > > + write_c0_perfctrl0(0); > > + write_c0_perfcntr0(reg.counter[0]); > > +} > > + > > +/* Start all counters on current CPU */ > > +static void r5500_cpu_start(void *args) > > +{ > > + write_c0_perfctrl1(reg.control[1]); > > + write_c0_perfctrl0(reg.control[0]); > > +} > > + > > +/* Stop all counters on current CPU */ > > +static void r5500_cpu_stop(void *args) > > +{ > > + write_c0_perfctrl1(0); > > + write_c0_perfctrl0(0); > > +} > > + > > +static int r5500_perfcount_handler(void) > > +{ > > + unsigned int control; > > + unsigned int counter; > > + int handled = IRQ_NONE; > > + > > + control = read_c0_perfctrl0(); > > + counter = read_c0_perfcntr0(); > > + if ((control & M_PERFCTL_INTERRUPT_ENABLE) && > > + (control & M_PERFCTL_INTERRUPT)) { > > + oprofile_add_sample(get_irq_regs(), 0); > > + write_c0_perfcntr0(reg.counter[0]); > > + write_c0_perfctrl0(control & ~M_PERFCTL_INTERRUPT); > > + handled = IRQ_HANDLED; > > + } > > + > > + control = read_c0_perfctrl1(); > > + counter = read_c0_perfcntr1(); > > + if ((control & M_PERFCTL_INTERRUPT_ENABLE) && > > + (control & M_PERFCTL_INTERRUPT)) { > > + oprofile_add_sample(get_irq_regs(), 1); > > + write_c0_perfcntr1(reg.counter[1]); > > + write_c0_perfctrl1(control & ~M_PERFCTL_INTERRUPT); > > + handled = IRQ_HANDLED; > > + } > > + > > + return handled; > > +} > > + > > +static void reset_counters(void *arg) > > +{ > > + write_c0_perfctrl1(0); > > + write_c0_perfcntr1(0); > > + > > + write_c0_perfctrl0(0); > > + write_c0_perfcntr0(0); > > +} > > + > > +static int __init r5500_init(void) > > +{ > > + on_each_cpu(reset_counters, NULL, 1); > > + > > + switch (current_cpu_type()) { > > + case CPU_R5500: > > + op_model_r5500_ops.cpu_type = "mips/vr5500"; > > + break; > > + > > + default: > > + printk(KERN_ERR "Profiling unsupported for this CPU\n"); > > + > > + return -ENODEV; > > + } > > + > > + save_perf_irq = perf_irq; > > + perf_irq = r5500_perfcount_handler; > > + > > + return 0; > > +} > > + > > +static void r5500_exit(void) > > +{ > > + on_each_cpu(reset_counters, NULL, 1); > > + > > + perf_irq = save_perf_irq; > > +} > > + > > +struct op_mips_model op_model_r5500_ops = { > > + .reg_setup = r5500_reg_setup, > > + .cpu_setup = r5500_cpu_setup, > > + .init = r5500_init, > > + .exit = r5500_exit, > > + .cpu_start = r5500_cpu_start, > > + .cpu_stop = r5500_cpu_stop, > > + .num_counters = NUM_COUNTERS, > > +}; > > -- > > 1.6.0.3 > > > > > > ------------------------------------------------------------------------- > >----- Open Source Business Conference (OSBC), March 24-25, 2009, San > > Francisco, CA -OSBC tackles the biggest issue in open source: Open > > Sourcing the Enterprise -Strategies to boost innovation and cut costs > > with open source participation -Receive a $600 discount off the > > registration fee with the source code: SFAD http://p.sf.net/sfu/XcvMzF8H > > _______________________________________________ > > oprofile-list mailing list > > oprofile-list@lists.sourceforge.net > > https://lists.sourceforge.net/lists/listinfo/oprofile-list From robert.richter@amd.com Wed Mar 4 21:50:46 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 04 Mar 2009 21:50:49 +0000 (GMT) Received: from va3ehsobe001.messaging.microsoft.com ([216.32.180.11]:40412 "EHLO VA3EHSOBE001.bigfish.com") by ftp.linux-mips.org with ESMTP id S21365705AbZCDVuq (ORCPT ); Wed, 4 Mar 2009 21:50:46 +0000 Received: from mail211-va3-R.bigfish.com (10.7.14.252) by VA3EHSOBE001.bigfish.com (10.7.40.21) with Microsoft SMTP Server id 8.1.340.0; Wed, 4 Mar 2009 21:50:40 +0000 Received: from mail211-va3 (localhost.localdomain [127.0.0.1]) by mail211-va3-R.bigfish.com (Postfix) with ESMTP id 213DA11F81FD; Wed, 4 Mar 2009 21:50:40 +0000 (UTC) X-BigFish: VPS-47(zz1432R62a3L98dR936eQ1805M179dRzzzzz32i6bh61h) Received: by mail211-va3 (MessageSwitch) id 1236203438642915_25220; Wed, 4 Mar 2009 21:50:38 +0000 (UCT) Received: from ausb3extmailp01.amd.com (unknown [163.181.251.8]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail211-va3.bigfish.com (Postfix) with ESMTP id 83A7570057; Wed, 4 Mar 2009 21:50:38 +0000 (UTC) Received: from ausb3twp02.amd.com ([163.181.250.38]) by ausb3extmailp01.amd.com (Switch-3.2.7/Switch-3.2.7) with ESMTP id n24LoUFe022070; Wed, 4 Mar 2009 15:50:33 -0600 X-WSS-ID: 0KG04NW-02-D1A-01 Received: from sausexbh1.amd.com (sausexbh1.amd.com [163.181.22.101]) by ausb3twp02.amd.com (Tumbleweed MailGate 3.5.1) with ESMTP id 26D0F16A063B; Wed, 4 Mar 2009 15:50:20 -0600 (CST) Received: from sausexmb2.amd.com ([163.181.3.157]) by sausexbh1.amd.com with Microsoft SMTPSVC(6.0.3790.3959); Wed, 4 Mar 2009 15:50:32 -0600 Received: from SDRSEXMB1.amd.com ([172.20.3.116]) by sausexmb2.amd.com with Microsoft SMTPSVC(6.0.3790.3959); Wed, 4 Mar 2009 15:50:32 -0600 Received: from seurexmb1.amd.com ([165.204.82.130]) by SDRSEXMB1.amd.com with Microsoft SMTPSVC(6.0.3790.3959); Wed, 4 Mar 2009 22:50:30 +0100 Received: from erda.amd.com ([165.204.85.17]) by seurexmb1.amd.com with Microsoft SMTPSVC(6.0.3790.3959); Wed, 4 Mar 2009 22:50:29 +0100 Received: by erda.amd.com (Postfix, from userid 35569) id BC97D800E; Wed, 4 Mar 2009 22:50:29 +0100 (CET) Date: Wed, 4 Mar 2009 22:50:29 +0100 From: Robert Richter To: "M. Asselstine" CC: Ralf Baechle , linux-mips@linux-mips.org, oprofile-list@lists.sf.net Subject: Re: [PATCH V2] oprofile: VR5500 performance counter driver Message-ID: <20090304215029.GT10085@erda.amd.com> References: <20090225165953.GF25042@erda.amd.com> <1235681374-19952-1-git-send-email-mark.asselstine@windriver.com> <20090303110755.GD10085@erda.amd.com> <200903041253.03682.Mark.Asselstine@windriver.com> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <200903041253.03682.Mark.Asselstine@windriver.com> User-Agent: Mutt/1.5.16 (2007-06-09) X-OriginalArrivalTime: 04 Mar 2009 21:50:29.0864 (UTC) FILETIME=[3C50D680:01C99D13] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22003 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: robert.richter@amd.com Precedence: bulk X-list: linux-mips On 04.03.09 12:53:03, M. Asselstine wrote: > > the Kconfig option for CONFIG_CPU_R5500 is still missing otherwise the > > patch itself looks fine. > > > > Hmmm, what tree are you looking at? I see it in Linus' tree as well as Ralf's > .29 RCs and master. Ahh, sorry. Was accidentally greping for CPU_VR5500. It is already upstream. Thanks Mark, -Robert -- Advanced Micro Devices, Inc. Operating System Research Center email: robert.richter@amd.com From dvomlehn@cisco.com Wed Mar 4 22:25:44 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 04 Mar 2009 22:25:46 +0000 (GMT) Received: from sj-iport-3.cisco.com ([171.71.176.72]:41373 "EHLO sj-iport-3.cisco.com") by ftp.linux-mips.org with ESMTP id S21365695AbZCDWZo convert rfc822-to-8bit (ORCPT ); Wed, 4 Mar 2009 22:25:44 +0000 X-IronPort-AV: E=Sophos;i="4.38,303,1233532800"; d="scan'208";a="139494868" Received: from sj-dkim-4.cisco.com ([171.71.179.196]) by sj-iport-3.cisco.com with ESMTP; 04 Mar 2009 22:25:37 +0000 Received: from sj-core-2.cisco.com (sj-core-2.cisco.com [171.71.177.254]) by sj-dkim-4.cisco.com (8.12.11/8.12.11) with ESMTP id n24MPbT9025135; Wed, 4 Mar 2009 14:25:37 -0800 Received: from xbh-rtp-201.amer.cisco.com (xbh-rtp-201.cisco.com [64.102.31.12]) by sj-core-2.cisco.com (8.13.8/8.13.8) with ESMTP id n24MPaj8022064; Wed, 4 Mar 2009 22:25:36 GMT Received: from xmb-rtp-218.amer.cisco.com ([64.102.31.117]) by xbh-rtp-201.amer.cisco.com with Microsoft SMTPSVC(6.0.3790.1830); Wed, 4 Mar 2009 17:25:36 -0500 X-MimeOLE: Produced By Microsoft Exchange V6.5 Content-class: urn:content-classes:message MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT Subject: RE: [PATCH, RFC] MIPS: Implement the getcontext API Date: Wed, 4 Mar 2009 17:25:35 -0500 Message-ID: In-Reply-To: <20090304154418.GA13464@linux-mips.org> X-MS-Has-Attach: X-MS-TNEF-Correlator: Thread-Topic: [PATCH, RFC] MIPS: Implement the getcontext API Thread-Index: Acmc4ESDyhWudsJMRte5BEcO+1iu2QAN0gVQ References: <49AD6139.60209@caviumnetworks.com> <200903040919.29294.brian.foster@innova-card.com> <20090304154418.GA13464@linux-mips.org> From: "David VomLehn (dvomlehn)" To: "Ralf Baechle" , "Brian Foster" Cc: "David Daney" , "Maciej W. Rozycki" , , , "Maciej W. Rozycki" X-OriginalArrivalTime: 04 Mar 2009 22:25:36.0599 (UTC) FILETIME=[24071670:01C99D18] DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; l=1814; t=1236205537; x=1237069537; c=relaxed/simple; s=sjdkim4002; h=Content-Type:From:Subject:Content-Transfer-Encoding:MIME-Version; d=cisco.com; i=dvomlehn@cisco.com; z=From:=20=22David=20VomLehn=20(dvomlehn)=22=20 |Subject:=20RE=3A=20[PATCH,=20RFC]=20MIPS=3A=20Implement=20 the=20getcontext=20API |Sender:=20; bh=Jb5HcdrPhHVfpf0WY4tayloauviO7DYGwAEnQShfgmU=; b=twC9FsnRhuMmYebOc1LzoYNJDtfWMih2SqlyOATQ8e2LOYIaRGZeXUVvFX ulwe08MT9XRkhYmzbL22N/t3Qxm0mnR4ay+wD9bYnzWlweDXxZ6xEnKmf/iG AlXDJIZi+z; Authentication-Results: sj-dkim-4; header.From=dvomlehn@cisco.com; dkim=pass ( sig from cisco.com/sjdkim4002 verified; ); Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22004 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dvomlehn@cisco.com Precedence: bulk X-list: linux-mips > -----Original Message----- > From: linux-mips-bounce@linux-mips.org > [mailto:linux-mips-bounce@linux-mips.org] On Behalf Of Ralf Baechle > Sent: Wednesday, March 04, 2009 7:44 AM > To: Brian Foster > Cc: David Daney; Maciej W. Rozycki; > linux-mips@linux-mips.org; libc-ports@sourceware.org; Maciej > W. Rozycki > Subject: Re: [PATCH, RFC] MIPS: Implement the getcontext API > > On Wed, Mar 04, 2009 at 09:19:28AM +0100, Brian Foster wrote: > > > On Tuesday 03 March 2009 17:56:25 David Daney wrote: > > >[ ... ] > > > When (and if) we move the sigreturn trampoline to a vdso > we should be > > > able to maintain the ABI. > > > > it's more a matter of "when" rather than "if". > > there is still an intention here to use XI (we > > have SmartMIPS), which requires not using the > > signal (or FP) trampoline on the stack. > > > > moving the signal trampoline to a vdso (which > > is(? was?) called, maybe misleadingly, 'vsyscall', > > on other architectures) is the obvious solution to > > that part of the puzzle. and yes, it is possible > > to maintain the ABI; the signal trampoline is still > > also put on the stack, and modulo XI, would work if > > used - the trampoline-on-stack is simply not used > > if there is a vdso with the signal trampoline. > > We generally want to get rid of stack trampolines. > Trampolines require > cacheflushing which especially on SMP systems can be a rather > expensive > operation. If I understand this correctly, using a vdso would allow a stack without execute permission on those processors that differentiate between read and execute permission. This defeats attaches that use buffer overrun to write code to be executed onto the stack, a nice thing for more secure systems. From David.Daney@caviumnetworks.com Wed Mar 4 22:36:25 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 04 Mar 2009 22:36:29 +0000 (GMT) Received: from mail3.caviumnetworks.com ([12.108.191.235]:44054 "EHLO mail3.caviumnetworks.com") by ftp.linux-mips.org with ESMTP id S21365751AbZCDWgZ (ORCPT ); Wed, 4 Mar 2009 22:36:25 +0000 Received: from exch4.caveonetworks.com (Not Verified[192.168.16.23]) by mail3.caviumnetworks.com with MailMarshal (v6,2,2,3503) id ; Wed, 04 Mar 2009 17:34:56 -0500 Received: from exch4.caveonetworks.com ([192.168.16.23]) by exch4.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Wed, 4 Mar 2009 14:34:17 -0800 Received: from dd1.caveonetworks.com ([64.169.86.201]) by exch4.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Wed, 4 Mar 2009 14:34:16 -0800 Message-ID: <49AF01E8.80705@caviumnetworks.com> Date: Wed, 04 Mar 2009 14:34:16 -0800 From: David Daney User-Agent: Thunderbird 2.0.0.19 (X11/20090105) MIME-Version: 1.0 To: "David VomLehn (dvomlehn)" CC: Ralf Baechle , Brian Foster , "Maciej W. Rozycki" , linux-mips@linux-mips.org, libc-ports@sourceware.org, "Maciej W. Rozycki" Subject: Re: [PATCH, RFC] MIPS: Implement the getcontext API References: <49AD6139.60209@caviumnetworks.com> <200903040919.29294.brian.foster@innova-card.com> <20090304154418.GA13464@linux-mips.org> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 04 Mar 2009 22:34:16.0907 (UTC) FILETIME=[5A27C9B0:01C99D19] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22005 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips David VomLehn (dvomlehn) wrote: >> -----Original Message----- >> From: linux-mips-bounce@linux-mips.org >> [mailto:linux-mips-bounce@linux-mips.org] On Behalf Of Ralf Baechle >> Sent: Wednesday, March 04, 2009 7:44 AM >> To: Brian Foster >> Cc: David Daney; Maciej W. Rozycki; >> linux-mips@linux-mips.org; libc-ports@sourceware.org; Maciej >> W. Rozycki >> Subject: Re: [PATCH, RFC] MIPS: Implement the getcontext API >> >> On Wed, Mar 04, 2009 at 09:19:28AM +0100, Brian Foster wrote: >> >>> On Tuesday 03 March 2009 17:56:25 David Daney wrote: >>>> [ ... ] >>>> When (and if) we move the sigreturn trampoline to a vdso >> we should be >>>> able to maintain the ABI. >>> it's more a matter of "when" rather than "if". >>> there is still an intention here to use XI (we >>> have SmartMIPS), which requires not using the >>> signal (or FP) trampoline on the stack. >>> >>> moving the signal trampoline to a vdso (which >>> is(? was?) called, maybe misleadingly, 'vsyscall', >>> on other architectures) is the obvious solution to >>> that part of the puzzle. and yes, it is possible >>> to maintain the ABI; the signal trampoline is still >>> also put on the stack, and modulo XI, would work if >>> used - the trampoline-on-stack is simply not used >>> if there is a vdso with the signal trampoline. >> We generally want to get rid of stack trampolines. >> Trampolines require >> cacheflushing which especially on SMP systems can be a rather >> expensive >> operation. > > If I understand this correctly, using a vdso would allow a stack without > execute permission on those processors that differentiate between read > and execute permission. This defeats attaches that use buffer overrun to > write code to be executed onto the stack, a nice thing for more secure > systems. > With one caveat, software other than the Linux kernel depends on an executable stack (GCC's nested functions for example). All users of the executable stack would have to modified before you could universally make the switch. That said, we do have RI/XI working well in our kernel (for non-stack memory), so it is something we are interested in pursuing. David Daney From blf.ireland@gmail.com Thu Mar 5 07:59:11 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 05 Mar 2009 07:59:17 +0000 (GMT) Received: from mail-bw0-f161.google.com ([209.85.218.161]:48346 "EHLO mail-bw0-f161.google.com") by ftp.linux-mips.org with ESMTP id S20808810AbZCEH7I convert rfc822-to-8bit (ORCPT ); Thu, 5 Mar 2009 07:59:08 +0000 Received: by bwz5 with SMTP id 5so3781463bwz.0 for ; Wed, 04 Mar 2009 23:59:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:sender:from:reply-to:to :subject:date:user-agent:cc:references:in-reply-to:mime-version :content-type:content-transfer-encoding:content-disposition :message-id; bh=VQAygljJbtVx3hMfoU/6vYDpSB57WJsQ+3kO+QPHR54=; b=ZL/u/fwcdTcyuaHxh8S5cNB9VmW+PyglOw1w+OaKiTZbqvJL3Q6+esgNhIY28ZCizS AkWmuC7M6Ov0aZXXlOugYs5+ftaMTiQigc5rv6emVg3rKbirERkPh/XFKmBANw4+iyG6 k34k9wfmJU+AiK2f+3oEqdc6B78RmkPRinnKI= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:from:reply-to:to:subject:date:user-agent:cc:references :in-reply-to:mime-version:content-type:content-transfer-encoding :content-disposition:message-id; b=e9yMpXTX1ncDllyfVCbJsHx1Kb1vThDt/LLbuJhbswWWLWrZH+1sbFau3toem+u+zd fqrLvANRQcogpnD2InJ9aC2sk9kBcP2sdKneRTjNjmneL2X3zi5bzWsUDLUm90VkfJM3 F9mWIJKfBri+44U9IVQEZT1QQQHvWwpCDNeCM= Received: by 10.180.245.20 with SMTP id s20mr275234bkh.184.1236239942778; Wed, 04 Mar 2009 23:59:02 -0800 (PST) Received: from innova-card.com (1-61.252-81.static-ip.oleane.fr [81.252.61.1]) by mx.google.com with ESMTPS id 10sm4081054bwz.24.2009.03.04.23.58.59 (version=TLSv1/SSLv3 cipher=RC4-MD5); Wed, 04 Mar 2009 23:59:01 -0800 (PST) From: Brian Foster Reply-To: Brian Foster To: David Daney Subject: MIPS RI/XI & trampolines [was:- [PATCH, RFC] MIPS: Implement the getcontext API ] Date: Thu, 5 Mar 2009 08:58:31 +0100 User-Agent: KMail/1.10.4 (Linux/2.6.27-11-generic; KDE/4.1.4; x86_64; ; ) Cc: "David VomLehn (dvomlehn)" , Ralf Baechle , "Maciej W. Rozycki" , linux-mips@linux-mips.org, libc-ports@sourceware.org, "Maciej W. Rozycki" References: <49AF01E8.80705@caviumnetworks.com> In-Reply-To: <49AF01E8.80705@caviumnetworks.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8BIT Content-Disposition: inline Message-Id: <200903050858.32232.brian.foster@innova-card.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22006 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: brian.foster@innova-card.com Precedence: bulk X-list: linux-mips On Wednesday 04 March 2009 23:34:16 David Daney wrote: > David VomLehn (dvomlehn) wrote: > >> -----Original Message----- > >> Sent: Wednesday, March 04, 2009 7:44 AM > >> From: [...] On Behalf Of Ralf Baechle > >> > >> On Wed, Mar 04, 2009 at 09:19:28AM +0100, Brian Foster wrote: > >>> On Tuesday 03 March 2009 17:56:25 David Daney wrote: > >>>>[ ... ] > >>>> When (and if) we move the sigreturn trampoline to a vdso we should be > >>>> able to maintain the ABI. > >>> it's more a matter of "when" rather than "if". > >>> there is still an intention here to use XI (we > >>> have SmartMIPS), which requires not using the > >>> signal (or FP) trampoline on the stack. > >>>[ ... ] > >> We generally want to get rid of stack trampolines. > >> Trampolines require cacheflushing which especially > >> on SMP systems can be a rather expensive operation. > > > > If I understand this correctly, using a vdso would allow a stack without > > execute permission on those processors that differentiate between read > > and execute permission. This defeats attaches that use buffer overrun to > > write code to be executed onto the stack, a nice thing for more secure > > systems. correct, albeit there are at least two caveats; one is, as David points out, (pointer-to) GCC nested functions; the other is the MIPS FP trampoline. > With one caveat, software other than the Linux kernel depends on an > executable stack (GCC's nested functions for example). All users of the > executable stack would have to modified before you could universally > make the switch. > > That said, we do have RI/XI working well in our kernel (for non-stack > memory), so it is something we are interested in pursuing. David, I am Very Interested in this. we also want RI/XI, at least for for userland (and, very importantly, including the stack), but haven't yet time to deal with the issue. (our platform is the 4KSd, which has SmartMIPS (and thus has RI/XI)). is what you have at linux-mips.org someplace? cheers! -blf- -- “How many surrealists does it take to | Brian Foster change a lightbulb? Three. One calms | somewhere in south of France the warthog, and two fill the bathtub | Stop E$$o (ExxonMobil)! with brightly-coloured machine tools.” | http://www.stopesso.com From macro@codesourcery.com Thu Mar 5 15:35:01 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 05 Mar 2009 15:35:03 +0000 (GMT) Received: from mail.codesourcery.com ([65.74.133.4]:399 "EHLO mail.codesourcery.com") by ftp.linux-mips.org with ESMTP id S20808979AbZCEPfA (ORCPT ); Thu, 5 Mar 2009 15:35:00 +0000 Received: (qmail 31753 invoked from network); 5 Mar 2009 15:34:57 -0000 Received: from unknown (HELO pl.orcam.me.uk) (macro@127.0.0.2) by mail.codesourcery.com with ESMTPA; 5 Mar 2009 15:34:57 -0000 Date: Thu, 5 Mar 2009 15:34:45 +0000 (GMT) From: "Maciej W. Rozycki" To: David Daney cc: Ralf Baechle , linux-mips@linux-mips.org, libc-ports@sourceware.org, "Maciej W. Rozycki" Subject: Re: [PATCH, RFC] MIPS: Implement the getcontext API In-Reply-To: <49AD6139.60209@caviumnetworks.com> Message-ID: References: <49AD6139.60209@caviumnetworks.com> User-Agent: Alpine 1.10 (DEB 962 2008-03-14) MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22007 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: macro@codesourcery.com Precedence: bulk X-list: linux-mips On Tue, 3 Mar 2009, David Daney wrote: > Note the libgcc currently makes the assumption that the layout of the stack > for signal handlers is fixed. The DWARF2 unwinder needs this information to > be able to unwind through signal frames (see gcc/config/mips/linux-unwind.h), > so it is already a de facto part of the ABI. I do hope it was agreed upon at some point. I certainly cannot recall a discussion at the linux-mips list, but I did not always follow it closely enough either, so I may have missed the discussion. The interface is meant to be internal to Linux, so the usual rule of volatility apply. The structure is not defined in a header even. > > Furthermore I am requesting that the kernel recognises the special meaning > > of the value of one stored in the slot designated for the $zero register and > > never places such a value itself there. > > Seems reasonable to me as currently a zero is unconditionally stored there. It is, but is should be architected, not assumed. Also contexts built with the *context() functions are meant to be usable by them only -- software will still be able to assume the value in the slot when constructed by the kernel. Maciej From David.Daney@caviumnetworks.com Thu Mar 5 16:59:27 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 05 Mar 2009 16:59:31 +0000 (GMT) Received: from smtp2.caviumnetworks.com ([209.113.159.134]:44807 "EHLO smtp2.caviumnetworks.com") by ftp.linux-mips.org with ESMTP id S21366218AbZCEQ71 (ORCPT ); Thu, 5 Mar 2009 16:59:27 +0000 Received: from exch4.caveonetworks.com (Not Verified[192.168.16.23]) by smtp2.caviumnetworks.com with MailMarshal (v6,2,2,3503) id ; Thu, 05 Mar 2009 11:58:47 -0500 Received: from exch4.caveonetworks.com ([192.168.16.23]) by exch4.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Thu, 5 Mar 2009 08:58:18 -0800 Received: from dd1.caveonetworks.com ([64.169.86.201]) by exch4.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Thu, 5 Mar 2009 08:58:18 -0800 Message-ID: <49B004AA.8050006@caviumnetworks.com> Date: Thu, 05 Mar 2009 08:58:18 -0800 From: David Daney User-Agent: Thunderbird 2.0.0.19 (X11/20090105) MIME-Version: 1.0 To: "Maciej W. Rozycki" CC: Ralf Baechle , linux-mips@linux-mips.org, libc-ports@sourceware.org, "Maciej W. Rozycki" , Richard Sandiford Subject: Re: [PATCH, RFC] MIPS: Implement the getcontext API References: <49AD6139.60209@caviumnetworks.com> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 05 Mar 2009 16:58:18.0505 (UTC) FILETIME=[95397F90:01C99DB3] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22008 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Adding Richard S. as he may be interested... Maciej W. Rozycki wrote: > On Tue, 3 Mar 2009, David Daney wrote: > >> Note the libgcc currently makes the assumption that the layout of the stack >> for signal handlers is fixed. The DWARF2 unwinder needs this information to >> be able to unwind through signal frames (see gcc/config/mips/linux-unwind.h), >> so it is already a de facto part of the ABI. > > I do hope it was agreed upon at some point. As with many things, there was no formal agreement. > I certainly cannot recall a > discussion at the linux-mips list, but I did not always follow it closely > enough either, so I may have missed the discussion. http://www.linux-mips.org/cgi-bin/mesg.cgi?a=linux-mips&i=473957B6.3030202%40avtrex.com http://www.linux-mips.org/cgi-bin/mesg.cgi?a=linux-mips&i=4739CCD6.2080306%40avtrex.com > The interface is > meant to be internal to Linux, so the usual rule of volatility apply. The > structure is not defined in a header even. > Certainly it started out that way, but if the kernel doesn't supply DWARF2 unwind tables for its signal trampolines (which it currently does not), then I think using the structures is the only way for user-space applications to unwind through signal trampolines. I was pointing this out not as any type of objection to your plan, but as further support for formalizing the interfaces. >>> Furthermore I am requesting that the kernel recognises the special meaning >>> of the value of one stored in the slot designated for the $zero register and >>> never places such a value itself there. >> Seems reasonable to me as currently a zero is unconditionally stored there. > > It is, but is should be architected, not assumed. Also contexts built > with the *context() functions are meant to be usable by them only -- > software will still be able to assume the value in the slot when > constructed by the kernel. > Agreed. Thanks for working on this, David Daney From David.Daney@caviumnetworks.com Thu Mar 5 17:03:06 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 05 Mar 2009 17:03:09 +0000 (GMT) Received: from mail3.caviumnetworks.com ([12.108.191.235]:9107 "EHLO mail3.caviumnetworks.com") by ftp.linux-mips.org with ESMTP id S21366218AbZCERDG (ORCPT ); Thu, 5 Mar 2009 17:03:06 +0000 Received: from exch4.caveonetworks.com (Not Verified[192.168.16.23]) by mail3.caviumnetworks.com with MailMarshal (v6,2,2,3503) id ; Thu, 05 Mar 2009 12:01:42 -0500 Received: from exch4.caveonetworks.com ([192.168.16.23]) by exch4.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Thu, 5 Mar 2009 09:01:04 -0800 Received: from dd1.caveonetworks.com ([64.169.86.201]) by exch4.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Thu, 5 Mar 2009 09:01:04 -0800 Message-ID: <49B00550.5050303@caviumnetworks.com> Date: Thu, 05 Mar 2009 09:01:04 -0800 From: David Daney User-Agent: Thunderbird 2.0.0.19 (X11/20090105) MIME-Version: 1.0 To: Brian Foster CC: "David VomLehn (dvomlehn)" , Ralf Baechle , "Maciej W. Rozycki" , linux-mips@linux-mips.org, libc-ports@sourceware.org, "Maciej W. Rozycki" Subject: Re: MIPS RI/XI & trampolines [was:- [PATCH, RFC] MIPS: Implement the getcontext API ] References: <49AF01E8.80705@caviumnetworks.com> <200903050858.32232.brian.foster@innova-card.com> In-Reply-To: <200903050858.32232.brian.foster@innova-card.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 05 Mar 2009 17:01:04.0207 (UTC) FILETIME=[F7FD9DF0:01C99DB3] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22009 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Brian Foster wrote: > On Wednesday 04 March 2009 23:34:16 David Daney wrote: [...] >> That said, we do have RI/XI working well in our kernel (for non-stack >> memory), so it is something we are interested in pursuing. > > David, > > I am Very Interested in this. we also want RI/XI, > at least for for userland (and, very importantly, > including the stack), but haven't yet time to deal > with the issue. (our platform is the 4KSd, which > has SmartMIPS (and thus has RI/XI)). > > is what you have at linux-mips.org someplace? > Not at this time, I will see if we can get it merged for 2.6.30... David Daney From dvomlehn@cisco.com Thu Mar 5 18:23:45 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 05 Mar 2009 18:23:49 +0000 (GMT) Received: from sj-iport-1.cisco.com ([171.71.176.70]:64519 "EHLO sj-iport-1.cisco.com") by ftp.linux-mips.org with ESMTP id S21366256AbZCESXp convert rfc822-to-8bit (ORCPT ); Thu, 5 Mar 2009 18:23:45 +0000 X-IronPort-AV: E=Sophos;i="4.38,308,1233532800"; d="scan'208";a="151416825" Received: from sj-dkim-2.cisco.com ([171.71.179.186]) by sj-iport-1.cisco.com with ESMTP; 05 Mar 2009 18:23:35 +0000 Received: from sj-core-5.cisco.com (sj-core-5.cisco.com [171.71.177.238]) by sj-dkim-2.cisco.com (8.12.11/8.12.11) with ESMTP id n25INZ3w021876; Thu, 5 Mar 2009 10:23:35 -0800 Received: from xbh-rtp-201.amer.cisco.com (xbh-rtp-201.cisco.com [64.102.31.12]) by sj-core-5.cisco.com (8.13.8/8.13.8) with ESMTP id n25INPBR003744; Thu, 5 Mar 2009 18:23:35 GMT Received: from xmb-rtp-218.amer.cisco.com ([64.102.31.117]) by xbh-rtp-201.amer.cisco.com with Microsoft SMTPSVC(6.0.3790.1830); Thu, 5 Mar 2009 13:23:32 -0500 X-MimeOLE: Produced By Microsoft Exchange V6.5 Content-class: urn:content-classes:message MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT Subject: RE: [PATCH, RFC] MIPS: Implement the getcontext API Date: Thu, 5 Mar 2009 13:23:31 -0500 Message-ID: In-Reply-To: <49B004AA.8050006@caviumnetworks.com> X-MS-Has-Attach: X-MS-TNEF-Correlator: Thread-Topic: [PATCH, RFC] MIPS: Implement the getcontext API Thread-Index: Acmds9qK4urogWtGSdKC7Amxa4hzaQACwSEw References: <49AD6139.60209@caviumnetworks.com> <49B004AA.8050006@caviumnetworks.com> From: "David VomLehn (dvomlehn)" To: "David Daney" , "Maciej W. Rozycki" Cc: "Ralf Baechle" , , , "Maciej W. Rozycki" , "Richard Sandiford" X-OriginalArrivalTime: 05 Mar 2009 18:23:32.0808 (UTC) FILETIME=[7D963480:01C99DBF] DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; l=1321; t=1236277415; x=1237141415; c=relaxed/simple; s=sjdkim2002; h=Content-Type:From:Subject:Content-Transfer-Encoding:MIME-Version; d=cisco.com; i=dvomlehn@cisco.com; z=From:=20=22David=20VomLehn=20(dvomlehn)=22=20 |Subject:=20RE=3A=20[PATCH,=20RFC]=20MIPS=3A=20Implement=20 the=20getcontext=20API |Sender:=20; bh=l5AIuFnITfSmQxyIpC/Jpt1DHipPwNOu4ok08B1NLcY=; b=oY/rLoVg/rTy8kE0LSKiKW98eC5OtzvgSLnvVsYq8qMjLeggESqUQbGkU4 3mHj9rY9KZaXIJW5GgC2YU5Q7aB+YsZGr5hDWz4KCTpdi10JzhIZH6OBqrRP yIu6ch12tb; Authentication-Results: sj-dkim-2; header.From=dvomlehn@cisco.com; dkim=pass ( sig from cisco.com/sjdkim2002 verified; ); Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22010 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dvomlehn@cisco.com Precedence: bulk X-list: linux-mips > -----Original Message----- > From: linux-mips-bounce@linux-mips.org > [mailto:linux-mips-bounce@linux-mips.org] On Behalf Of David Daney > Sent: Thursday, March 05, 2009 8:58 AM > To: Maciej W. Rozycki > Cc: Ralf Baechle; linux-mips@linux-mips.org; > libc-ports@sourceware.org; Maciej W. Rozycki; Richard Sandiford > Subject: Re: [PATCH, RFC] MIPS: Implement the getcontext API > > Adding Richard S. as he may be interested... > > Maciej W. Rozycki wrote: > > On Tue, 3 Mar 2009, David Daney wrote: > > > >> Note the libgcc currently makes the assumption that the > layout of the stack > >> for signal handlers is fixed. The DWARF2 unwinder needs > this information to > >> be able to unwind through signal frames (see > gcc/config/mips/linux-unwind.h), > >> so it is already a de facto part of the ABI. > > > > I do hope it was agreed upon at some point. > > As with many things, there was no formal agreement. To the best of my knowledge, there is no formal ABI for MIPS Linux, period. The closest we have is the MIPS psABI, which documented the o32 ABI as it stood ten years ago. What we have now does not conform to that document in some subtle, but non-trivial, ways. If I'm wrong, I'd love to know where I could find documentation. David VomLehn From s.boutayeb@free.fr Thu Mar 5 19:43:44 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 05 Mar 2009 19:43:46 +0000 (GMT) Received: from wmproxy1-g27.free.fr ([212.27.42.91]:8629 "EHLO wmproxy1-g27.free.fr") by ftp.linux-mips.org with ESMTP id S21366270AbZCETno (ORCPT ); Thu, 5 Mar 2009 19:43:44 +0000 Received: from wmproxy1-g27.free.fr (localhost [127.0.0.1]) by wmproxy1-g27.free.fr (Postfix) with ESMTP id AC6BB630C5; Thu, 5 Mar 2009 20:43:40 +0100 (CET) Received: from UNKNOWN (imp8-g19.priv.proxad.net [172.20.243.138]) by wmproxy1-g27.free.fr (Postfix) with ESMTP id 736746306D; Thu, 5 Mar 2009 20:43:38 +0100 (CET) Received: by UNKNOWN (Postfix, from userid 0) id 7291C3696AA8A; Thu, 5 Mar 2009 20:43:38 +0100 (CET) Received: from ([83.154.79.221]) by imp.free.fr (IMP) with HTTP for ; Thu, 05 Mar 2009 20:43:38 +0100 Message-ID: <1236282218.49b02b6a6c724@imp.free.fr> Date: Thu, 05 Mar 2009 20:43:38 +0100 From: s.boutayeb@free.fr To: gnewsense-dev@nongnu.org Cc: dclark@gnu.org, rms@gnu.org, debian-mips@lists.debian.org, linux-mips@linux-mips.org Subject: gns mips-l: what next? MIME-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit User-Agent: Internet Messaging Program (IMP) 3.2.8 X-Originating-IP: 83.154.79.221 X-Virus-Scanned: ClamAV using ClamSMTP Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22011 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: s.boutayeb@free.fr Precedence: bulk X-list: linux-mips Hi, The "gNewSense mips-l" project ( http://wiki.gnewsense.org/Projects/GNewSenseToMIPS ) is on a good way, thanks to the support of the gNewSense team, of the FSF, of Lemote Tech, and of various contributors around the world. So far, we have a gNewSense-compliant Debian installer allowing the execution of netboot installation procedure from an usb stick and fine-tuned for the lemote hardware. The installation and the upgrade uses the archive set by the FSF at http://archive.gnewsense.org/gnewsense-mipsel-l/. The Lemote hardware ("yeeloong 8089" laptop and "Fuloong 6003" mini box) boot from the bsd licensed PMON200 boot loader. The netboot install procedure has be proven successful on the "Yeeloong 8089" laptop and remains to be tested on the "Fuloong 6003" mini box. We have now a nice full-free laptop with beautiful arts designed by the gNewSense-arts-team, a working gnome desktop environment. Many things need to be polished: for example the apm (the battery of the laptops show a 0% gauge), the webcam is not yet working), but we have full networking capabilities (both wired and wireless), a functional xorg server (thanks to the siliconmotion driver from lemote's dev), etc. In the same time, Lemote Tech's team has setup a netboot installation procedure http://dev.lemote.com/drupal/node/58 and has provided valuable advice, hardware resources, code, etc. to the gNewSenseToMips project. This was a big help for us all. Now, how could we move forward? Maybe: - improving - testing - documenting - upgrading - promoting - upstreaming - etc. That is, many things, but not too much, considering the realistic perspective that more talents decide to contribute to the gNewSense project. You are wellcome! Thank you for your comments and for your support! Cheers Samy From ralf@h5.dl5rb.org.uk Thu Mar 5 21:37:12 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 05 Mar 2009 21:37:16 +0000 (GMT) Received: from localhost.localdomain ([127.0.0.1]:28367 "EHLO h5.dl5rb.org.uk") by ftp.linux-mips.org with ESMTP id S20808998AbZCEVhM (ORCPT ); Thu, 5 Mar 2009 21:37:12 +0000 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id n25LaxP7023892; Thu, 5 Mar 2009 22:36:59 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id n25Lars9023882; Thu, 5 Mar 2009 22:36:53 +0100 Date: Thu, 5 Mar 2009 22:36:53 +0100 From: Ralf Baechle To: "David VomLehn (dvomlehn)" Cc: David Daney , "Maciej W. Rozycki" , linux-mips@linux-mips.org, libc-ports@sourceware.org, "Maciej W. Rozycki" , Richard Sandiford Subject: Re: [PATCH, RFC] MIPS: Implement the getcontext API Message-ID: <20090305213653.GB12355@linux-mips.org> References: <49AD6139.60209@caviumnetworks.com> <49B004AA.8050006@caviumnetworks.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22012 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Thu, Mar 05, 2009 at 01:23:31PM -0500, David VomLehn (dvomlehn) wrote: > > > I do hope it was agreed upon at some point. > > > > As with many things, there was no formal agreement. > > To the best of my knowledge, there is no formal ABI for MIPS Linux, > period. The closest we have is the MIPS psABI, which documented the o32 > ABI as it stood ten years ago. What we have now does not conform to that > document in some subtle, but non-trivial, ways. If I'm wrong, I'd love > to know where I could find documentation. This is correct. The documentation situation is a bit chaotic. ELF was specified by System V ABI and later by the Tool Interface Standard. There is a MIPS psABI to cover the MIPS specifics of the Sys V ABI. SGI did some enhancements and came up with their own ELF variant which is incompatible with ABI ELF in subtle ways. In addition SGI came up with the over-engineered NABI (New ABI) variants for N32 and N64 which are partially documented in antique postscript files floating around on the net and partially in some IRIX specs on techpubs.sgi.com. Add the stillborn EABI and NUBI variants. Add various Linux and GNU specific enhancements and deviations from the previously mentioned documents for example for TLS. Frequently the documentation really is just in the code, a mailing list archive or in the back of somebody's brain ... Somebody could probably earn a medal by writing a single consolidated and readable piece of documentation. Ralf From roland@redhat.com Thu Mar 5 21:42:27 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 05 Mar 2009 21:42:31 +0000 (GMT) Received: from mx1.redhat.com ([66.187.233.31]:3977 "EHLO mx1.redhat.com") by ftp.linux-mips.org with ESMTP id S21366146AbZCEVm1 (ORCPT ); Thu, 5 Mar 2009 21:42:27 +0000 Received: from int-mx1.corp.redhat.com (int-mx1.corp.redhat.com [172.16.52.254]) by mx1.redhat.com (8.13.8/8.13.8) with ESMTP id n25Le59D020448; Thu, 5 Mar 2009 16:40:05 -0500 Received: from gateway.sf.frob.com (vpn-14-9.rdu.redhat.com [10.11.14.9]) by int-mx1.corp.redhat.com (8.13.1/8.13.1) with ESMTP id n25LdvTX022651; Thu, 5 Mar 2009 16:40:06 -0500 Received: from magilla.sf.frob.com (magilla.sf.frob.com [198.49.250.228]) by gateway.sf.frob.com (Postfix) with ESMTP id 5012A357B; Thu, 5 Mar 2009 13:39:51 -0800 (PST) Received: by magilla.sf.frob.com (Postfix, from userid 5281) id DC443FC3BF; Thu, 5 Mar 2009 13:39:50 -0800 (PST) MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit From: Roland McGrath To: Ralf Baechle Cc: "David VomLehn (dvomlehn)" , David Daney , "Maciej W. Rozycki" , linux-mips@linux-mips.org, libc-ports@sourceware.org, "Maciej W. Rozycki" , Richard Sandiford Subject: Re: [PATCH, RFC] MIPS: Implement the getcontext API In-Reply-To: Ralf Baechle's message of Thursday, 5 March 2009 22:36:53 +0100 <20090305213653.GB12355@linux-mips.org> References: <49AD6139.60209@caviumnetworks.com> <49B004AA.8050006@caviumnetworks.com> <20090305213653.GB12355@linux-mips.org> X-Zippy-Says: Is this BOISE?? Message-Id: <20090305213950.DC443FC3BF@magilla.sf.frob.com> Date: Thu, 5 Mar 2009 13:39:50 -0800 (PST) X-Scanned-By: MIMEDefang 2.58 on 172.16.52.254 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22013 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: roland@redhat.com Precedence: bulk X-list: linux-mips > Somebody could probably earn a medal by writing a single consolidated > and readable piece of documentation. generic-abi@googlegroups.com is a place nowadays to find people likely to be interested in collaborating on better ELF-related documentation. From joseph@codesourcery.com Thu Mar 5 21:53:27 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 05 Mar 2009 21:53:30 +0000 (GMT) Received: from mail.codesourcery.com ([65.74.133.4]:36538 "EHLO mail.codesourcery.com") by ftp.linux-mips.org with ESMTP id S21366316AbZCEVxW (ORCPT ); Thu, 5 Mar 2009 21:53:22 +0000 Received: (qmail 10224 invoked from network); 5 Mar 2009 21:53:19 -0000 Received: from unknown (HELO digraph.polyomino.org.uk) (joseph@127.0.0.2) by mail.codesourcery.com with ESMTPA; 5 Mar 2009 21:53:19 -0000 Received: from jsm28 (helo=localhost) by digraph.polyomino.org.uk with local-esmtp (Exim 4.69) (envelope-from ) id 1LfLVG-0003aR-MS; Thu, 05 Mar 2009 21:53:18 +0000 Date: Thu, 5 Mar 2009 21:53:18 +0000 (UTC) From: "Joseph S. Myers" X-X-Sender: jsm28@digraph.polyomino.org.uk To: Ralf Baechle cc: "David VomLehn (dvomlehn)" , David Daney , "Maciej W. Rozycki" , linux-mips@linux-mips.org, libc-ports@sourceware.org, "Maciej W. Rozycki" , Richard Sandiford Subject: Re: [PATCH, RFC] MIPS: Implement the getcontext API In-Reply-To: <20090305213653.GB12355@linux-mips.org> Message-ID: References: <49AD6139.60209@caviumnetworks.com> <49B004AA.8050006@caviumnetworks.com> <20090305213653.GB12355@linux-mips.org> MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22014 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: joseph@codesourcery.com Precedence: bulk X-list: linux-mips On Thu, 5 Mar 2009, Ralf Baechle wrote: > stillborn EABI and NUBI variants. Add various Linux and GNU specific > enhancements and deviations from the previously mentioned documents for > example for TLS. Frequently the documentation really is just in the code, > a mailing list archive or in the back of somebody's brain ... (Although it took a while for the documentation to catch up with the implementation and changes made in the course of patch review, as far as I know is now an accurate description of TLS for MIPS.) > Somebody could probably earn a medal by writing a single consolidated > and readable piece of documentation. Anyone seriously wishing to produce a complete and current and copyright-clean description of what the MIPS ABIs now are might wish to note that a similar project for (32-bit) Power Architecture has been going on since late 2006 and we still haven't quite got to the point of releasing a public review draft. There is a lot of work involved. -- Joseph S. Myers joseph@codesourcery.com From dvomlehn@cisco.com Thu Mar 5 22:08:29 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 05 Mar 2009 22:08:32 +0000 (GMT) Received: from sj-iport-1.cisco.com ([171.71.176.70]:7782 "EHLO sj-iport-1.cisco.com") by ftp.linux-mips.org with ESMTP id S20808936AbZCEWI3 convert rfc822-to-8bit (ORCPT ); Thu, 5 Mar 2009 22:08:29 +0000 X-IronPort-AV: E=Sophos;i="4.38,309,1233532800"; d="scan'208";a="151553296" Received: from rtp-dkim-1.cisco.com ([64.102.121.158]) by sj-iport-1.cisco.com with ESMTP; 05 Mar 2009 22:08:21 +0000 Received: from rtp-core-1.cisco.com (rtp-core-1.cisco.com [64.102.124.12]) by rtp-dkim-1.cisco.com (8.12.11/8.12.11) with ESMTP id n25M8J3D005004; Thu, 5 Mar 2009 17:08:19 -0500 Received: from xbh-rtp-201.amer.cisco.com (xbh-rtp-201.cisco.com [64.102.31.12]) by rtp-core-1.cisco.com (8.13.8/8.13.8) with ESMTP id n25M8JnX016173; Thu, 5 Mar 2009 22:08:19 GMT Received: from xmb-rtp-218.amer.cisco.com ([64.102.31.117]) by xbh-rtp-201.amer.cisco.com with Microsoft SMTPSVC(6.0.3790.1830); Thu, 5 Mar 2009 17:08:19 -0500 X-MimeOLE: Produced By Microsoft Exchange V6.5 Content-class: urn:content-classes:message MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT Subject: RE: [PATCH, RFC] MIPS: Implement the getcontext API Date: Thu, 5 Mar 2009 17:08:18 -0500 Message-ID: In-Reply-To: X-MS-Has-Attach: X-MS-TNEF-Correlator: Thread-Topic: [PATCH, RFC] MIPS: Implement the getcontext API Thread-Index: Acmd3Nkuz4Q900bBQfa7KqWkCfRlNAAAWe2w References: <49AD6139.60209@caviumnetworks.com> <49B004AA.8050006@caviumnetworks.com> <20090305213653.GB12355@linux-mips.org> From: "David VomLehn (dvomlehn)" To: "Joseph Myers" , "Ralf Baechle" Cc: "David Daney" , "Maciej W. Rozycki" , , , "Maciej W. Rozycki" , "Richard Sandiford" X-OriginalArrivalTime: 05 Mar 2009 22:08:19.0261 (UTC) FILETIME=[E4239ED0:01C99DDE] DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; l=1880; t=1236290899; x=1237154899; c=relaxed/simple; s=rtpdkim1001; h=Content-Type:From:Subject:Content-Transfer-Encoding:MIME-Version; d=cisco.com; i=dvomlehn@cisco.com; z=From:=20=22David=20VomLehn=20(dvomlehn)=22=20 |Subject:=20RE=3A=20[PATCH,=20RFC]=20MIPS=3A=20Implement=20 the=20getcontext=20API |Sender:=20 |To:=20=22Joseph=20Myers=22=20,=0A =20=20=20=20=20=20=20=20=22Ralf=20Baechle=22=20; bh=vKwgj+ZUuHHGblUz09Hyc+6ZekVPHss3LRmLtMGe4dk=; b=nenzj3N3T8pwglFHjCQ0D0MwHthZoPL0rjljCO+bzmqZGmHvyPv3606oeh AqDkKsRHzwWuVLlotkJgZWa70bb6PddsvRjFydV+2tu6hU4PJ93d4MDsDrt+ 5osxkm5Iq1; Authentication-Results: rtp-dkim-1; header.From=dvomlehn@cisco.com; dkim=pass ( sig from cisco.com/rtpdkim1001 verified; ); Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22015 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dvomlehn@cisco.com Precedence: bulk X-list: linux-mips > -----Original Message----- > From: Joseph Myers [mailto:joseph@codesourcery.com] > Sent: Thursday, March 05, 2009 1:53 PM > To: Ralf Baechle > Cc: David VomLehn (dvomlehn); David Daney; Maciej W. Rozycki; > linux-mips@linux-mips.org; libc-ports@sourceware.org; Maciej > W. Rozycki; Richard Sandiford > Subject: Re: [PATCH, RFC] MIPS: Implement the getcontext API > > On Thu, 5 Mar 2009, Ralf Baechle wrote: > > > stillborn EABI and NUBI variants. Add various Linux and > GNU specific > > enhancements and deviations from the previously mentioned > documents for > > example for TLS. Frequently the documentation really is > just in the code, > > a mailing list archive or in the back of somebody's brain ... > > (Although it took a while for the documentation to catch up with the > implementation and changes made in the course of patch > review, as far as I > know is now an accurate > description > of TLS for MIPS.) > > > Somebody could probably earn a medal by writing a single > consolidated > > and readable piece of documentation. > > Anyone seriously wishing to produce a complete and current and > copyright-clean description of what the MIPS ABIs now are > might wish to > note that a similar project for (32-bit) Power Architecture > has been going > on since late 2006 and we still haven't quite got to the point of > releasing a public review draft. There is a lot of work involved. I spent two years as Chair of the MIPS ABI Group Technical Committee working on the MIPS psABI and I can attest to how much work it is. Still, if there were enough of people involved from the kernel, compiler/library, and appropriate utility communities willing to try to pull things together, I could see spending time on it. From khickey@rmicorp.com Fri Mar 6 16:20:15 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 06 Mar 2009 16:20:18 +0000 (GMT) Received: from mx1.rmicorp.com ([63.111.213.197]:35445 "EHLO mx1.rmicorp.com") by ftp.linux-mips.org with ESMTP id S20808195AbZCFQUP (ORCPT ); Fri, 6 Mar 2009 16:20:15 +0000 Received: from sark.razamicroelectronics.com ([10.8.0.254]) by mx1.rmicorp.com with Microsoft SMTPSVC(6.0.3790.3959); Fri, 6 Mar 2009 08:20:09 -0800 Received: from localhost.localdomain (unknown [10.8.0.23]) by sark.razamicroelectronics.com (Postfix) with ESMTP id BF26E6E1D04; Fri, 6 Mar 2009 09:42:10 -0600 (CST) From: Kevin Hickey To: ralf@linux-mips.org, linux-mips@linux-mips.org Subject: Alchemy: Support for RMI Alchemy Au1300 and DBAu1300 Date: Fri, 6 Mar 2009 10:19:59 -0600 Message-Id: <1236356409-32357-1-git-send-email-khickey@rmicorp.com> X-Mailer: git-send-email 1.5.4.3 In-Reply-To: <> References: <> X-OriginalArrivalTime: 06 Mar 2009 16:20:09.0278 (UTC) FILETIME=[6B26EDE0:01C99E77] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22016 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: khickey@rmicorp.com Precedence: bulk X-list: linux-mips This patch series introduces support for the RMI Alchemy Au1300 series of SOCs and the DBAu1300 (or DB1300) development board. With this set the basic CPU and board are supported, as well as a few of the system peripherals. USB, LCD, UART, MMC/SD and ethernet drivers are included. Other drivers are currently in development and will be released in a later patch set. All included code has been tested and verified working on a DB1300 board. Though some of the new code added here could be useful for other boards (the DB1200 in particular), I did my best to limit this patch set to additions only. It should not disturb any other boards. To verify this I built and tested the updated directory for an on a DB1200 board. A future patch set may include some integration of this new code into the DB1200 configuration. arch/mips/Kconfig | 1 + arch/mips/Makefile | 6 + arch/mips/alchemy/Kconfig | 22 + arch/mips/alchemy/common/Makefile | 4 +- arch/mips/alchemy/common/au13xx_res.c | 104 + arch/mips/alchemy/common/dbdma.c | 46 +- arch/mips/alchemy/common/gpio_int.c | 268 + arch/mips/alchemy/common/irq.c | 3 + arch/mips/alchemy/common/platform.c | 76 +- arch/mips/alchemy/common/time.c | 16 + arch/mips/alchemy/devboards/Makefile | 6 + arch/mips/alchemy/devboards/cascade_irq.c | 142 + arch/mips/alchemy/devboards/db1300/Makefile | 6 + arch/mips/alchemy/devboards/db1300/board_setup.c | 123 + arch/mips/alchemy/devboards/db1300/mmc.c | 154 + arch/mips/alchemy/devboards/leds.c | 58 + arch/mips/configs/db1300_defconfig | 1216 ++++ arch/mips/include/asm/cpu.h | 10 +- arch/mips/include/asm/mach-au1x00/au1000.h | 49 + arch/mips/include/asm/mach-au1x00/au13xx.h | 207 + arch/mips/include/asm/mach-au1x00/au1xxx.h | 3 + arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h | 33 + arch/mips/include/asm/mach-au1x00/dev_boards.h | 44 + arch/mips/include/asm/mach-au1x00/gpio_int.h | 239 + arch/mips/include/asm/mach-au1x00/irq.h | 34 + arch/mips/include/asm/mips-boards/db1300.h | 120 + arch/mips/kernel/cpu-probe.c | 20 + arch/mips/mm/c-r4k.c | 1 + arch/mips/mm/tlbex.c | 1 + drivers/mmc/host/Kconfig | 2 +- drivers/mmc/host/au1xmmc.c | 18 +- drivers/net/Kconfig | 6 + drivers/net/Makefile | 3 + drivers/net/smsc9210/Makefile | 9 + drivers/net/smsc9210/ioctl_118.h | 298 + drivers/net/smsc9210/platform_alchemy.c | 88 + drivers/net/smsc9210/platform_alchemy.h | 117 + drivers/net/smsc9210/smsc9210.h | 23 + drivers/net/smsc9210/smsc9210_main.c | 7189 ++++++++++++++++++++++ drivers/usb/Kconfig | 1 + drivers/usb/host/ehci-au13xx.c | 213 + drivers/usb/host/ehci-hcd.c | 5 + drivers/video/Kconfig | 2 +- 43 files changed, 10969 insertions(+), 17 deletions(-) From khickey@rmicorp.com Fri Mar 6 16:20:35 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 06 Mar 2009 16:20:39 +0000 (GMT) Received: from mx1.rmicorp.com ([63.111.213.197]:35445 "EHLO mx1.rmicorp.com") by ftp.linux-mips.org with ESMTP id S20808213AbZCFQUQ (ORCPT ); Fri, 6 Mar 2009 16:20:16 +0000 Received: from sark.razamicroelectronics.com ([10.8.0.254]) by mx1.rmicorp.com with Microsoft SMTPSVC(6.0.3790.3959); Fri, 6 Mar 2009 08:20:09 -0800 Received: from localhost.localdomain (unknown [10.8.0.23]) by sark.razamicroelectronics.com (Postfix) with ESMTP id C78F0EE76A7; Fri, 6 Mar 2009 09:42:10 -0600 (CST) From: Kevin Hickey To: ralf@linux-mips.org, linux-mips@linux-mips.org Cc: Kevin Hickey Subject: [PATCH 03/10] Alchemy: Au1300/DB1300 UART support Date: Fri, 6 Mar 2009 10:20:02 -0600 Message-Id: <7afc5c84989c4bc0f94181397369f284f2bb6924.1236354153.git.khickey@rmicorp.com> X-Mailer: git-send-email 1.5.4.3 In-Reply-To: <0b447f7e26be90a9179bdf89ca2cfd1f34c5d16e.1236354153.git.khickey@rmicorp.com> References: <> <1236356409-32357-1-git-send-email-khickey@rmicorp.com> <788248524efc28ba2608ed79bfb7080ee476b12d.1236354153.git.khickey@rmicorp.com> <0b447f7e26be90a9179bdf89ca2cfd1f34c5d16e.1236354153.git.khickey@rmicorp.com> In-Reply-To: <788248524efc28ba2608ed79bfb7080ee476b12d.1236354153.git.khickey@rmicorp.com> References: <788248524efc28ba2608ed79bfb7080ee476b12d.1236354153.git.khickey@rmicorp.com> X-OriginalArrivalTime: 06 Mar 2009 16:20:09.0418 (UTC) FILETIME=[6B3C4AA0:01C99E77] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22017 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: khickey@rmicorp.com Precedence: bulk X-list: linux-mips Adds support for the UART on the Au1300 SOC and the DB1300 board. This includes enabling EARLY_PRINTK for Alchemy. Signed-off-by: Kevin Hickey --- arch/mips/Kconfig | 1 + arch/mips/alchemy/common/platform.c | 5 +++++ arch/mips/include/asm/mach-au1x00/au1000.h | 5 +++++ 3 files changed, 11 insertions(+), 0 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index e61465a..b030770 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -21,6 +21,7 @@ choice config MACH_ALCHEMY bool "Alchemy processor based machines" + select SYS_HAS_EARLY_PRINTK config BASLER_EXCITE bool "Basler eXcite smart camera" diff --git a/arch/mips/alchemy/common/platform.c b/arch/mips/alchemy/common/platform.c index fd096d1..d53d3a0 100644 --- a/arch/mips/alchemy/common/platform.c +++ b/arch/mips/alchemy/common/platform.c @@ -52,6 +52,11 @@ static struct plat_serial8250_port au1x00_uart_data[] = { #elif defined(CONFIG_SOC_AU1200) PORT(UART0_ADDR, AU1200_UART0_INT), PORT(UART1_ADDR, AU1200_UART1_INT), +#elif defined(CONFIG_SOC_AU13XX) + PORT(UART2_ADDR, AU1300_IRQ_UART2 + GPINT_LINUX_IRQ_OFFSET), + PORT(UART0_ADDR, AU1300_IRQ_UART0 + GPINT_LINUX_IRQ_OFFSET), + PORT(UART1_ADDR, AU1300_IRQ_UART1 + GPINT_LINUX_IRQ_OFFSET), + PORT(UART3_ADDR, AU1300_IRQ_UART3 + GPINT_LINUX_IRQ_OFFSET), #endif #endif /* CONFIG_SERIAL_8250_AU1X00 */ { }, diff --git a/arch/mips/include/asm/mach-au1x00/au1000.h b/arch/mips/include/asm/mach-au1x00/au1000.h index ddebb84..debf896 100644 --- a/arch/mips/include/asm/mach-au1x00/au1000.h +++ b/arch/mips/include/asm/mach-au1x00/au1000.h @@ -1276,7 +1276,12 @@ enum soc_au1200_ints { #define MAC_RX_BUFF3_ADDR 0x34 /* UARTS 0-3 */ +#ifdef CONFIG_SOC_AU13XX +#define UART_BASE UART2_ADDR +#else #define UART_BASE UART0_ADDR +#endif + #ifdef CONFIG_SOC_AU1200 #define UART_DEBUG_BASE UART1_ADDR #else -- 1.5.4.3 From khickey@rmicorp.com Fri Mar 6 16:20:58 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 06 Mar 2009 16:21:02 +0000 (GMT) Received: from mx1.rmicorp.com ([63.111.213.197]:35445 "EHLO mx1.rmicorp.com") by ftp.linux-mips.org with ESMTP id S20808295AbZCFQUR (ORCPT ); Fri, 6 Mar 2009 16:20:17 +0000 Received: from sark.razamicroelectronics.com ([10.8.0.254]) by mx1.rmicorp.com with Microsoft SMTPSVC(6.0.3790.3959); Fri, 6 Mar 2009 08:20:09 -0800 Received: from localhost.localdomain (unknown [10.8.0.23]) by sark.razamicroelectronics.com (Postfix) with ESMTP id C9BC0EE76A9; Fri, 6 Mar 2009 09:42:10 -0600 (CST) From: Kevin Hickey To: ralf@linux-mips.org, linux-mips@linux-mips.org Cc: Kevin Hickey Subject: [PATCH 04/10] Alchemy: Au1300/DB1300 peripheral resource declarations Date: Fri, 6 Mar 2009 10:20:03 -0600 Message-Id: <0946334bbaf9883076889fe060a362b72d31e6f4.1236354153.git.khickey@rmicorp.com> X-Mailer: git-send-email 1.5.4.3 In-Reply-To: <7afc5c84989c4bc0f94181397369f284f2bb6924.1236354153.git.khickey@rmicorp.com> References: <> <1236356409-32357-1-git-send-email-khickey@rmicorp.com> <788248524efc28ba2608ed79bfb7080ee476b12d.1236354153.git.khickey@rmicorp.com> <0b447f7e26be90a9179bdf89ca2cfd1f34c5d16e.1236354153.git.khickey@rmicorp.com> <7afc5c84989c4bc0f94181397369f284f2bb6924.1236354153.git.khickey@rmicorp.com> In-Reply-To: <788248524efc28ba2608ed79bfb7080ee476b12d.1236354153.git.khickey@rmicorp.com> References: <788248524efc28ba2608ed79bfb7080ee476b12d.1236354153.git.khickey@rmicorp.com> X-OriginalArrivalTime: 06 Mar 2009 16:20:09.0434 (UTC) FILETIME=[6B3EBBA0:01C99E77] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22018 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: khickey@rmicorp.com Precedence: bulk X-list: linux-mips This adds some declarations for peripheral resouces for the first few supported peripherals. This includes USB, LCD, IDE and MMC. Signed-off-by: Kevin Hickey --- arch/mips/alchemy/common/au13xx_res.c | 104 ++++++++++++++++++++++ arch/mips/alchemy/common/dbdma.c | 46 +++++++++- arch/mips/alchemy/common/platform.c | 69 ++++++++++++++- arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h | 33 +++++++ 4 files changed, 250 insertions(+), 2 deletions(-) create mode 100644 arch/mips/alchemy/common/au13xx_res.c diff --git a/arch/mips/alchemy/common/au13xx_res.c b/arch/mips/alchemy/common/au13xx_res.c new file mode 100644 index 0000000..206c2f8 --- /dev/null +++ b/arch/mips/alchemy/common/au13xx_res.c @@ -0,0 +1,104 @@ +/* + * Copyright 2003-2008 RMI Corporation. All rights reserved. + * Author: Kevin Hickey + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED BY RMI Corporation 'AS IS' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL RMI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include +#include + +#include + +#ifdef CONFIG_SOC_AU13XX +/* + * USB Resources for Au13xx + */ +static struct resource au13xx_usb_ehci_resources[] = { + [0] = { + .start = USB_EHCI_BASE, + .end = USB_EHCI_BASE + USB_EHCI_LEN - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AU1300_IRQ_USB + GPINT_LINUX_IRQ_OFFSET, + .end = AU1300_IRQ_USB + GPINT_LINUX_IRQ_OFFSET, + .flags = IORESOURCE_IRQ, + }, +}; + +static u64 ehci_dmamask = DMA_32BIT_MASK; + +static struct platform_device au13xx_usb_ehci_device = { + .name = "au13xx-ehci", + .id = 0, + .dev = { + .dma_mask = &ehci_dmamask, + .coherent_dma_mask = DMA_32BIT_MASK, + }, + .num_resources = ARRAY_SIZE(au13xx_usb_ehci_resources), + .resource = au13xx_usb_ehci_resources, +}; + +/* OHCI (USB full speed host controller) */ +static struct resource au13xx_usb_ohci_resources[] = { + [0] = { + .start = USB_OHCI_BASE, + .end = USB_OHCI_BASE + USB_OHCI_LEN - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AU1300_IRQ_USB + GPINT_LINUX_IRQ_OFFSET, + .end = AU1300_IRQ_USB + GPINT_LINUX_IRQ_OFFSET, + .flags = IORESOURCE_IRQ, + }, +}; + +/* The dmamask must be set for OHCI to work */ +static u64 ohci_dmamask = DMA_32BIT_MASK; + +static struct platform_device au13xx_usb_ohci_device = { + .name = "au1xxx-ohci", + .id = 0, + .dev = { + .dma_mask = &ohci_dmamask, + .coherent_dma_mask = DMA_32BIT_MASK, + }, + .num_resources = ARRAY_SIZE(au13xx_usb_ohci_resources), + .resource = au13xx_usb_ohci_resources, +}; + + +static struct platform_device *au13xx_platform_devices[] __initdata = { + &au13xx_usb_ehci_device, + &au13xx_usb_ohci_device, +}; + +static int __init au13xx_add_devices(void) +{ + return platform_add_devices(au13xx_platform_devices, + ARRAY_SIZE(au13xx_platform_devices)); +} + +arch_initcall(au13xx_add_devices); + +#endif /* CONFIG_SOC_AU13XX */ diff --git a/arch/mips/alchemy/common/dbdma.c b/arch/mips/alchemy/common/dbdma.c index 3ab6d80..7fda56b 100644 --- a/arch/mips/alchemy/common/dbdma.c +++ b/arch/mips/alchemy/common/dbdma.c @@ -38,7 +38,8 @@ #include #include -#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) +#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) || \ + defined(CONFIG_SOC_AU13XX) /* * The Descriptor Based DMA supports up to 16 channels. @@ -150,6 +151,47 @@ static dbdev_tab_t dbdev_tab[] = { #endif /* CONFIG_SOC_AU1200 */ +#ifdef CONFIG_SOC_AU13XX + { DSCR_CMD0_UART0_TX, DEV_FLAGS_OUT, 0, 8, 0x10100004, 0, 0 }, + { DSCR_CMD0_UART0_RX, DEV_FLAGS_IN, 0, 8, 0x10100000, 0, 0 }, + { DSCR_CMD0_UART1_TX, DEV_FLAGS_OUT, 0, 8, 0x01011004, 0, 0 }, + { DSCR_CMD0_UART1_RX, DEV_FLAGS_IN, 0, 8, 0x10101000, 0, 0 }, + { DSCR_CMD0_UART2_TX, DEV_FLAGS_OUT, 0, 8, 0x01012004, 0, 0 }, + { DSCR_CMD0_UART2_RX, DEV_FLAGS_IN, 0, 8, 0x10102000, 0, 0 }, + { DSCR_CMD0_UART3_TX, DEV_FLAGS_OUT, 0, 8, 0x01013004, 0, 0 }, + { DSCR_CMD0_UART3_RX, DEV_FLAGS_IN, 0, 8, 0x10103000, 0, 0 }, + + { DSCR_CMD0_SDMS_TX0, DEV_FLAGS_OUT, 4, 8, 0x10600000, 0, 0 }, + { DSCR_CMD0_SDMS_RX0, DEV_FLAGS_IN, 4, 8, 0x10600004, 0, 0 }, + { DSCR_CMD0_SDMS_TX1, DEV_FLAGS_OUT, 8, 8, 0x10601000, 0, 0 }, + { DSCR_CMD0_SDMS_RX1, DEV_FLAGS_IN, 8, 8, 0x10601004, 0, 0 }, + + { DSCR_CMD0_AES_RX, DEV_FLAGS_IN , 4, 32, 0x10300008, 0, 0 }, + { DSCR_CMD0_AES_TX, DEV_FLAGS_OUT, 4, 32, 0x10300004, 0, 0 }, + + { DSCR_CMD0_PSC0_TX, DEV_FLAGS_OUT, 0, 16, 0x10a0001c, 0, 0 }, + { DSCR_CMD0_PSC0_RX, DEV_FLAGS_IN, 0, 16, 0x10a0001c, 0, 0 }, + { DSCR_CMD0_PSC1_TX, DEV_FLAGS_OUT, 0, 16, 0x10a0101c, 0, 0 }, + { DSCR_CMD0_PSC1_RX, DEV_FLAGS_IN, 0, 16, 0x10a0101c, 0, 0 }, + { DSCR_CMD0_PSC2_TX, DEV_FLAGS_OUT, 0, 16, 0x10a0201c, 0, 0 }, + { DSCR_CMD0_PSC2_RX, DEV_FLAGS_IN, 0, 16, 0x10a0201c, 0, 0 }, + { DSCR_CMD0_PSC3_TX, DEV_FLAGS_OUT, 0, 16, 0x10a0301c, 0, 0 }, + { DSCR_CMD0_PSC3_RX, DEV_FLAGS_IN, 0, 16, 0x10a0301c, 0, 0 }, + + { DSCR_CMD0_LCD, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, + { DSCR_CMD0_NAND_FLASH, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 }, + + { DSCR_CMD0_SDMS_TX2, DEV_FLAGS_OUT, 4, 8, 0x10602000, 0, 0 }, + { DSCR_CMD0_SDMS_RX2, DEV_FLAGS_IN, 4, 8, 0x10602004, 0, 0 }, + + { DSCR_CMD0_CIM_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, + + { DSCR_CMD0_UDMA, DEV_FLAGS_ANYUSE, 0, 32, 0x14001810, 0, 0 }, + + { DSCR_CMD0_DMA_REQ0, 0, 0, 0, 0x00000000, 0, 0 }, + { DSCR_CMD0_DMA_REQ1, 0, 0, 0, 0x00000000, 0, 0 }, +#endif /* CONFIG_SOC_AU13XX */ + { DSCR_CMD0_THROTTLE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, { DSCR_CMD0_ALWAYS, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, @@ -881,6 +923,8 @@ static void au1xxx_dbdma_init(void) irq_nr = AU1550_DDMA_INT; #elif defined(CONFIG_SOC_AU1200) irq_nr = AU1200_DDMA_INT; +#elif defined(CONFIG_SOC_AU13XX) + irq_nr = AU1300_IRQ_DDMA + GPINT_LINUX_IRQ_OFFSET; #else #error Unknown Au1x00 SOC #endif diff --git a/arch/mips/alchemy/common/platform.c b/arch/mips/alchemy/common/platform.c index d53d3a0..d1b370d 100644 --- a/arch/mips/alchemy/common/platform.c +++ b/arch/mips/alchemy/common/platform.c @@ -338,14 +338,81 @@ static struct platform_device pbdb_smbus_device = { }; #endif +#ifdef CONFIG_SOC_AU13XX +static struct resource au1200_lcd_resources[] = { + [0] = { + .start = LCD_PHYS_ADDR, + .end = LCD_PHYS_ADDR + 0x800 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AU1300_IRQ_LCD + 8, + .end = AU1300_IRQ_LCD + 8, + .flags = IORESOURCE_IRQ, + } +}; + +static u64 au1200_lcd_dmamask = DMA_32BIT_MASK; + +static struct platform_device au1200_lcd_device = { + .name = "au1200-lcd", + .id = 0, + .dev = { + .dma_mask = &au1200_lcd_dmamask, + .coherent_dma_mask = DMA_32BIT_MASK, + }, + .num_resources = ARRAY_SIZE(au1200_lcd_resources), + .resource = au1200_lcd_resources, +}; + +extern struct platform_device au13xx_mmc0_device; +extern struct platform_device au13xx_mmc1_device; + + +extern struct au1xmmc_platform_data au1xmmc_platdata[2]; +static struct resource ide_resources[] = { + [0] = { + .start = IDE_PHYS_ADDR, + .end = IDE_PHYS_ADDR + IDE_PHYS_LEN - 1, + .flags = IORESOURCE_MEM + }, + [1] = { + .start = IDE_INT, + .end = IDE_INT, + .flags = IORESOURCE_IRQ + } +}; + +static u64 ide_dmamask = DMA_32BIT_MASK; + +static struct platform_device ide_device = { + .name = "au1200-ide", + .id = 0, + .dev = { + .dma_mask = &ide_dmamask, + .coherent_dma_mask = DMA_32BIT_MASK, + }, + .num_resources = ARRAY_SIZE(ide_resources), + .resource = ide_resources +}; + +#endif + + static struct platform_device *au1xxx_platform_devices[] __initdata = { &au1xx0_uart_device, - &au1xxx_usb_ohci_device, +#ifdef CONFIG_SOC_AU13XX + &au1200_lcd_device, + &ide_device, + //&au13xx_mmc0_device, + &au13xx_mmc1_device, +#endif &au1x00_pcmcia_device, #ifdef CONFIG_FB_AU1100 &au1100_lcd_device, #endif #ifdef CONFIG_SOC_AU1200 + &au1xxx_usb_ohci_device, &au1xxx_usb_ehci_device, &au1xxx_usb_gdt_device, &au1xxx_usb_otg_device, diff --git a/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h b/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h index 06f68f4..1c36b9f 100644 --- a/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h +++ b/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h @@ -195,6 +195,39 @@ typedef volatile struct au1xxx_ddma_desc { #define DSCR_CMD0_CIM_SYNC 26 #endif /* CONFIG_SOC_AU1200 */ +#ifdef CONFIG_SOC_AU13XX +#define DSCR_CMD0_UART0_TX 0 +#define DSCR_CMD0_UART0_RX 1 +#define DSCR_CMD0_UART1_TX 2 +#define DSCR_CMD0_UART1_RX 3 +#define DSCR_CMD0_UART2_TX 4 +#define DSCR_CMD0_UART2_RX 5 +#define DSCR_CMD0_UART3_TX 6 +#define DSCR_CMD0_UART3_RX 7 +#define DSCR_CMD0_SDMS_TX0 8 +#define DSCR_CMD0_SDMS_RX0 9 +#define DSCR_CMD0_SDMS_TX1 10 +#define DSCR_CMD0_SDMS_RX1 11 +#define DSCR_CMD0_AES_TX 12 +#define DSCR_CMD0_AES_RX 13 +#define DSCR_CMD0_PSC0_TX 14 +#define DSCR_CMD0_PSC0_RX 15 +#define DSCR_CMD0_PSC1_TX 16 +#define DSCR_CMD0_PSC1_RX 17 +#define DSCR_CMD0_PSC2_TX 18 +#define DSCR_CMD0_PSC2_RX 19 +#define DSCR_CMD0_PSC3_TX 20 +#define DSCR_CMD0_PSC3_RX 21 +#define DSCR_CMD0_LCD 22 +#define DSCR_CMD0_NAND_FLASH 23 +#define DSCR_CMD0_SDMS_TX2 24 +#define DSCR_CMD0_SDMS_RX2 25 +#define DSCR_CMD0_CIM_SYNC 26 +#define DSCR_CMD0_UDMA 27 +#define DSCR_CMD0_DMA_REQ0 28 +#define DSCR_CMD0_DMA_REQ1 29 +#endif /* CONFIG_SOC_AU13XX */ + #define DSCR_CMD0_THROTTLE 30 #define DSCR_CMD0_ALWAYS 31 #define DSCR_NDEV_IDS 32 -- 1.5.4.3 From khickey@rmicorp.com Fri Mar 6 16:21:19 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 06 Mar 2009 16:21:24 +0000 (GMT) Received: from mx1.rmicorp.com ([63.111.213.197]:35445 "EHLO mx1.rmicorp.com") by ftp.linux-mips.org with ESMTP id S21366478AbZCFQUS (ORCPT ); Fri, 6 Mar 2009 16:20:18 +0000 Received: from sark.razamicroelectronics.com ([10.8.0.254]) by mx1.rmicorp.com with Microsoft SMTPSVC(6.0.3790.3959); Fri, 6 Mar 2009 08:20:09 -0800 Received: from localhost.localdomain (unknown [10.8.0.23]) by sark.razamicroelectronics.com (Postfix) with ESMTP id C1765EE7685; Fri, 6 Mar 2009 09:42:10 -0600 (CST) From: Kevin Hickey To: ralf@linux-mips.org, linux-mips@linux-mips.org Cc: Kevin Hickey Subject: [PATCH 01/10] Initial Au1300 and DBAu1300 support Date: Fri, 6 Mar 2009 10:20:00 -0600 Message-Id: <788248524efc28ba2608ed79bfb7080ee476b12d.1236354153.git.khickey@rmicorp.com> X-Mailer: git-send-email 1.5.4.3 In-Reply-To: <1236356409-32357-1-git-send-email-khickey@rmicorp.com> References: <> <1236356409-32357-1-git-send-email-khickey@rmicorp.com> X-OriginalArrivalTime: 06 Mar 2009 16:20:09.0293 (UTC) FILETIME=[6B2937D0:01C99E77] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22019 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: khickey@rmicorp.com Precedence: bulk X-list: linux-mips This patch introduces the new RMI Alchemy Au1300 series SOC to the kernel, as well as its first development board, the DBAu1300 (or DB1300). This patch is just the basic CPU identification and some resouce constants. Also included are some new Alchemy IO functions and macros, named to match with the current kernel standard. They include au_iowrite32, au_ioread32, etc. These are used heavily in the Au1300/DB1300 code so they need to be included here. Signed-off-by: Kevin Hickey --- arch/mips/Makefile | 6 + arch/mips/alchemy/Kconfig | 18 ++ arch/mips/alchemy/common/platform.c | 2 + arch/mips/alchemy/devboards/Makefile | 1 + arch/mips/alchemy/devboards/db1300/Makefile | 6 + arch/mips/alchemy/devboards/db1300/board_setup.c | 123 +++++++++++++ arch/mips/include/asm/cpu.h | 10 +- arch/mips/include/asm/mach-au1x00/au1000.h | 44 +++++ arch/mips/include/asm/mach-au1x00/au13xx.h | 207 ++++++++++++++++++++++ arch/mips/include/asm/mach-au1x00/au1xxx.h | 3 + arch/mips/include/asm/mach-au1x00/dev_boards.h | 44 +++++ arch/mips/include/asm/mips-boards/db1300.h | 120 +++++++++++++ arch/mips/kernel/cpu-probe.c | 20 ++ arch/mips/mm/c-r4k.c | 1 + arch/mips/mm/tlbex.c | 1 + 15 files changed, 603 insertions(+), 3 deletions(-) create mode 100644 arch/mips/alchemy/devboards/db1300/Makefile create mode 100644 arch/mips/alchemy/devboards/db1300/board_setup.c create mode 100644 arch/mips/include/asm/mach-au1x00/au13xx.h create mode 100644 arch/mips/include/asm/mach-au1x00/dev_boards.h create mode 100644 arch/mips/include/asm/mips-boards/db1300.h diff --git a/arch/mips/Makefile b/arch/mips/Makefile index 21b00e9..15e1577 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -255,6 +255,12 @@ core-$(CONFIG_MIPS_DB1200) += arch/mips/alchemy/devboards/ cflags-$(CONFIG_MIPS_DB1200) += -I$(srctree)/arch/mips/include/asm/mach-db1x00 load-$(CONFIG_MIPS_DB1200) += 0xffffffff80100000 +# RMI Alchemy DBAu1300 development board +# +core-$(CONFIG_MIPS_DB1300) += arch/mips/alchemy/devboards/ +cflags-$(CONFIG_MIPS_DB1300) += -I$(srctree)/arch/mips/include/asm/mach-db1x00 +load-$(CONFIG_MIPS_DB1300) += 0xffffffff80100000 + # # AMD Alchemy Bosporus eval board # diff --git a/arch/mips/alchemy/Kconfig b/arch/mips/alchemy/Kconfig index 7f8ef13..7198a88 100644 --- a/arch/mips/alchemy/Kconfig +++ b/arch/mips/alchemy/Kconfig @@ -53,6 +53,12 @@ config MIPS_DB1550 select MIPS_DISABLE_OBSOLETE_IDE select SYS_SUPPORTS_LITTLE_ENDIAN +config MIPS_DB1300 + bool "Alchemy DBAu1300 Development Board" + select SOC_AU13XX + select DMA_COHERENT + select SYS_SUPPORTS_LITTLE_ENDIAN + config MIPS_MIRAGE bool "Alchemy Mirage board" select DMA_NONCOHERENT @@ -124,6 +130,12 @@ config SOC_AU1550 config SOC_AU1200 bool select SOC_AU1X00 + select AU_INT_CNTLR + +config SOC_AU13XX + bool + select SOC_AU1X00 + select AU_GPIO_INT_CNTLR config SOC_AU1X00 bool @@ -135,3 +147,9 @@ config SOC_AU1X00 select SYS_SUPPORTS_32BIT_KERNEL select SYS_SUPPORTS_APM_EMULATION select GENERIC_HARDIRQS_NO__DO_IRQ + +config AU_INT_CNTLR + bool + +config AU_GPIO_INT_CNTLR + bool diff --git a/arch/mips/alchemy/common/platform.c b/arch/mips/alchemy/common/platform.c index 5c76c64..fd096d1 100644 --- a/arch/mips/alchemy/common/platform.c +++ b/arch/mips/alchemy/common/platform.c @@ -65,6 +65,7 @@ static struct platform_device au1xx0_uart_device = { }, }; +#ifndef CONFIG_SOC_AU13XX /* OHCI (USB full speed host controller) */ static struct resource au1xxx_usb_ohci_resources[] = { [0] = { @@ -92,6 +93,7 @@ static struct platform_device au1xxx_usb_ohci_device = { .num_resources = ARRAY_SIZE(au1xxx_usb_ohci_resources), .resource = au1xxx_usb_ohci_resources, }; +#endif /*** AU1100 LCD controller ***/ diff --git a/arch/mips/alchemy/devboards/Makefile b/arch/mips/alchemy/devboards/Makefile index 730f9f2..0d2d224 100644 --- a/arch/mips/alchemy/devboards/Makefile +++ b/arch/mips/alchemy/devboards/Makefile @@ -12,6 +12,7 @@ obj-$(CONFIG_MIPS_PB1550) += pb1550/ obj-$(CONFIG_MIPS_DB1000) += db1x00/ obj-$(CONFIG_MIPS_DB1100) += db1x00/ obj-$(CONFIG_MIPS_DB1200) += pb1200/ +obj-$(CONFIG_MIPS_DB1300) += db1300/ obj-$(CONFIG_MIPS_DB1500) += db1x00/ obj-$(CONFIG_MIPS_DB1550) += db1x00/ obj-$(CONFIG_MIPS_BOSPORUS) += db1x00/ diff --git a/arch/mips/alchemy/devboards/db1300/Makefile b/arch/mips/alchemy/devboards/db1300/Makefile new file mode 100644 index 0000000..edaff49 --- /dev/null +++ b/arch/mips/alchemy/devboards/db1300/Makefile @@ -0,0 +1,6 @@ +# +# Copyright 2008 RMI Corporation. All rights reserved. +# Author: Kevin Hickey +# + +obj-y := board_setup.o mmc.o diff --git a/arch/mips/alchemy/devboards/db1300/board_setup.c b/arch/mips/alchemy/devboards/db1300/board_setup.c new file mode 100644 index 0000000..118b15c --- /dev/null +++ b/arch/mips/alchemy/devboards/db1300/board_setup.c @@ -0,0 +1,123 @@ +/* + * Copyright 2003-2008 RMI Corporation. All rights reserved. + * Author: Kevin Hickey + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED BY RMI Corporation 'AS IS' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL RMI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include /* for printk */ + +#include +#include +#include + +#define DB1300_SYSTEM_TYPE_STRING "RMI DBAu1300 Development Board" + +volatile struct bcsr_regs *const bcsr = + (struct bcsr_regs *)(DB1300_BCSR_REGS_PHYS_ADDR + KSEG1_OFFSET); + +void __init board_setup(void) +{ + char *argptr = NULL; + + printk(KERN_INFO DB1300_SYSTEM_TYPE_STRING "\n"); + + /* + * Add some text to the command line to point the au1200fb driver to + * the board switch. + */ + argptr = prom_getcmdline(); + strcat(argptr, "console=ttyS0,115200 video=au1200fb:panel:bs"); + + /* + * Enable VBUS to the USB Host port + */ + AU_SET_BITS_16(BCSR_RESETS_USB_HOST, &bcsr->resets); +} + +void board_reset(void) +{ + /* KH: TODO - write board_reset() */ +} + +const char *get_system_type(void) +{ + return DB1300_SYSTEM_TYPE_STRING; +} + +#if 0 +void __init prom_init(void) +{ + unsigned char *memsize_str; + unsigned long memsize; + + prom_argc = (int)fw_arg0; + prom_argv = (char **)fw_arg1; + prom_envp = (char **)fw_arg2; + + prom_init_cmdline(); + memsize_str = prom_getenv("memsize"); + /* KH: TODO - Change back to 128 MB when the second DDR channel is working. */ + if (!memsize_str) + memsize = 0x04000000; + else + strict_strtol(memsize_str, 0, &memsize); + add_memory_region(0, memsize, BOOT_MEM_RAM); +} +#endif + +/* + * Called by plat_irq_dispatch to do board-specific things (i.e. display the + * interrupt on a hex output). This should *not* be used for board-specific + * interrupt handling; for that register a new interrupt handler as a device + * driver would do. + */ +void board_irq_dispatch(unsigned int irq) +{ + db_set_hex((u8)irq); +} + +/* + * Board specific functions for the Au1200 Framebuffer driver + */ + +int board_au1200fb_panel(void) +{ + u16 switches = (au_ioread16(&db_bcsr->switches) & 0x0f00 ) >> 8; + + printk("Returning LCD switch setting %d\n", switches); + return switches; +} + +int board_au1200fb_panel_init(void) +{ + /* Apply power */ + AU_SET_BITS_16(0x7, &db_bcsr->board); + return 0; +} + +int board_au1200fb_panel_shutdown(void) +{ + /* Remove power */ + AU_CLEAR_BITS_16(0x7, &db_bcsr->board); + return 0; +} diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h index c018727..e3528a7 100644 --- a/arch/mips/include/asm/cpu.h +++ b/arch/mips/include/asm/cpu.h @@ -33,9 +33,9 @@ #define PRID_COMP_TOSHIBA 0x070000 #define PRID_COMP_LSI 0x080000 #define PRID_COMP_LEXRA 0x0b0000 +#define PRID_COMP_RMI 0x0c0000 #define PRID_COMP_CAVIUM 0x0d0000 - /* * Assigned values for the product ID register. In order to detect a * certain CPU type exactly eventually additional registers may need to @@ -115,9 +115,13 @@ #define PRID_IMP_BCM3302 0x9000 /* - * These are the PRID's for when 23:16 == PRID_COMP_CAVIUM + * These are the PRID's for when 23:16 == PRID_COMP_RMI */ +#define PRID_IMP_AU13XX 0x8000 +/* + * These are the PRID's for when 23:16 == PRID_COMP_CAVIUM + */ #define PRID_IMP_CAVIUM_CN38XX 0x0000 #define PRID_IMP_CAVIUM_CN31XX 0x0100 #define PRID_IMP_CAVIUM_CN30XX 0x0200 @@ -210,7 +214,7 @@ enum cpu_type_enum { */ CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K, CPU_AU1000, CPU_AU1100, CPU_AU1200, CPU_AU1210, CPU_AU1250, CPU_AU1500, - CPU_AU1550, CPU_PR4450, CPU_BCM3302, CPU_BCM4710, + CPU_AU1550, CPU_AU13XX, CPU_PR4450, CPU_BCM3302, CPU_BCM4710, /* * MIPS64 class processors diff --git a/arch/mips/include/asm/mach-au1x00/au1000.h b/arch/mips/include/asm/mach-au1x00/au1000.h index 62f91f5..ddebb84 100644 --- a/arch/mips/include/asm/mach-au1x00/au1000.h +++ b/arch/mips/include/asm/mach-au1x00/au1000.h @@ -6,6 +6,9 @@ * Copyright 2000-2001, 2006-2008 MontaVista Software Inc. * Author: MontaVista Software, Inc. * + * Copyright 2008 RMI Corporation + * Author: Kevin Hickey + * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the * Free Software Foundation; either version 2 of the License, or (at your @@ -43,6 +46,8 @@ #include #include +#include + /* cpu pipeline flush */ void static inline au_sync(void) { @@ -91,6 +96,10 @@ static inline u32 au_readl(unsigned long reg) return *(volatile u32 *)reg; } +void static inline au_iowrite16(u16 val, volatile u16 *reg) +{ + *reg = val; +} /* Early Au1000 have a write-only SYS_CPUPLL register. */ static inline int au1xxx_cpu_has_pll_wo(void) { @@ -103,6 +112,11 @@ static inline int au1xxx_cpu_has_pll_wo(void) return 0; } +static inline u16 au_ioread16(volatile u16 *reg) +{ + return *reg; +} + /* does CPU need CONFIG[OD] set to fix tons of errata? */ static inline int au1xxx_cpu_needs_config_od(void) { @@ -130,6 +144,36 @@ static inline int au1xxx_cpu_needs_config_od(void) return 0; } +void static inline au_iowrite32(u32 val, volatile u32 *reg) +{ + *reg = val; +} + +static inline u32 au_ioread32(volatile u32 *reg) +{ + return *reg; +} + +#define AU_SET_BITS_16(mask, reg) \ +do { \ + au_iowrite16((au_ioread16(reg) | mask ), reg); \ +} while(0) + +#define AU_CLEAR_BITS_16(mask, reg) \ +do { \ + au_iowrite16((au_ioread16(reg) & ~mask ), reg); \ +} while(0) + +#define AU_SET_BITS_32(mask, reg) \ +do { \ + au_iowrite32((au_ioread32(reg) | mask), reg); \ +} while(0) + +#define AU_CLEAR_BITS_32(mask, reg) \ +do { \ + au_iowrite32((au_ioread32(reg) & ~mask), reg); \ +} while(0) + /* arch/mips/au1000/common/clocks.c */ extern void set_au1x00_speed(unsigned int new_freq); extern unsigned int get_au1x00_speed(void); diff --git a/arch/mips/include/asm/mach-au1x00/au13xx.h b/arch/mips/include/asm/mach-au1x00/au13xx.h new file mode 100644 index 0000000..e868176 --- /dev/null +++ b/arch/mips/include/asm/mach-au1x00/au13xx.h @@ -0,0 +1,207 @@ +/* + * Copyright 2008 RMI Corporation + * Author: Kevin Hickey + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef _AU13XX_H +#define _AU13XX_H + +#ifdef CONFIG_SOC_AU13XX + +#define NR_INTS 255 + +#define UART0_ADDR 0xB0100000 +#define UART1_ADDR 0xB0101000 +#define UART2_ADDR 0xB0102000 +#define UART3_ADDR 0xB0103000 + +#define KSEG1_OFFSET 0xA0000000 +#define GPIO_INT_CTRLR_BASE 0x10200000 +/* + * Linux uses IRQ 0-7 for the 8 causes. That means that all of our channel + * bits need to be offset by 8 either when passed to do_IRQ or when received + * through the irq_chip calls + * + * KH: TODO - This is duplicated from gpio_int.h Is that the right thing to do? + */ +#define GPINT_LINUX_IRQ_OFFSET 8 + +#define AU1300_IRQ_UART1 17 +#define AU1300_IRQ_UART2 25 +#define AU1300_IRQ_UART3 27 +#define AU1300_IRQ_SD1 32 +#define AU1300_IRQ_SD2 38 +#define AU1300_IRQ_PSC0 48 +#define AU1300_IRQ_PSC1 52 +#define AU1300_IRQ_PSC2 56 +#define AU1300_IRQ_PSC3 60 +#define AU1300_IRQ_NAND 62 +#define AU1300_IRQ_DDMA 75 +#define AU1300_IRQ_GPU 78 +#define AU1300_IRQ_MPU 77 +#define AU1300_IRQ_MMU 76 +#define AU1300_IRQ_UDMA 79 +#define AU1300_IRQ_TOY_TICK 80 +#define AU1300_IRQ_TOYMATCH_0 81 +#define AU1300_IRQ_TOYMATCH_1 82 +#define AU1300_IRQ_TOYMATCH_2 83 +#define AU1300_IRQ_RTC_TICK 84 +#define AU1300_IRQ_RTCMATCH_0 85 +#define AU1300_IRQ_RTCMATCH_1 86 +#define AU1300_IRQ_RTCMATCH_2 87 +#define AU1300_IRQ_UART0 88 +#define AU1300_IRQ_SD0 89 +#define AU1300_IRQ_USB 90 +#define AU1300_IRQ_LCD 91 +#define AU1300_IRQ_BSA 94 +#define AU1300_IRQ_MPE 93 +#define AU1300_IRQ_ITE 92 +#define AU1300_IRQ_AES 95 +#define AU1300_IRQ_CIM 96 + +#define LCD_PHYS_ADDR 0x15000000 + +#define AU1200_LCD_INT (GPINT_LINUX_IRQ_OFFSET + AU1300_IRQ_LCD) +#define AU1000_RTC_MATCH2_INT (GPINT_LINUX_IRQ_OFFSET + AU1300_IRQ_RTCMATCH_2) + +#define SD0_PHYS_ADDR 0x10600000 +#define SD1_PHYS_ADDR 0x10601000 + + +#define USB_BASE_PHYS_ADDR 0x14021000 +#define USB_EHCI_BASE 0x14020000 +#define USB_EHCI_LEN 0x400 +#define USB_OHCI_BASE 0x14020800 +#define USB_OHCI_LEN 0x400 +#define USB_UOC_BASE 0x14022000 +#define USB_UOC_LEN 0x20 +#define USB_UDC_BASE 0x14022000 +#define USB_UDC_LEN 0x2000 + +#if !defined(ASSEMBLER) +typedef volatile struct +{ + // setup registers + u32 dwc_ctrl1; //0x0000 + u32 dwc_ctrl2; //0x0004 + u32 reserved0[2]; //0x08 - 0x0C + + u32 vbus_timer; //0x0010 + u32 sbus_ctrl; //0x0014 + u32 msr_err; //0x0018 + u32 dwc_ctrl3; //0x001C + + u32 dwc_ctrl4; //0x0020 + u32 reserved1; //0x0024 + u32 otg_status; //0x0028 + u32 dwc_ctrl5; //0x002C + + u32 dwc_ctrl6; //0x0030 + u32 dwc_ctrl7; //0x0034 + + u32 reserved2[(0xC0-0x38)/4]; // 0x0038 -- 0x00C0 + + u32 phy_status; //0x00C0 + u32 intr_status; //0x00C4 + u32 intr_enable; //0x00C8 + +} AU13XX_USB; +#endif // ASSEMBLER + +#define USB_DWC_CTRL1_OTGD (1<<2) +#define USB_DWC_CTRL1_HSTRS (1<<1) +#define USB_DWC_CTRL1_DCRS (1<<0) + +#define USB_DWC_CTRL2_HTBSE1 (1<<11) +#define USB_DWC_CTRL2_HTBSE0 (1<<10) +#define USB_DWC_CTRL2_LTBSE1 (1<<9) +#define USB_DWC_CTRL2_LTBSE0 (1<<8) +#define USB_DWC_CTRL2_LPBKE1 (1<<5) +#define USB_DWC_CTRL2_LPBKE0 (1<<4) +#define USB_DWC_CTRL2_VBUSD (1<<3) +#define USB_DWC_CTRL2_PH1RS (1<<2) +#define USB_DWC_CTRL2_PHY0RS (1<<1) +#define USB_DWC_CTRL2_PHYRS (1<<0) + +#define USB_VBUS_TIMER(n) (n) + +#define USB_SBUS_CTRL_SBCA (1<<2) +#define USB_SBUS_CTRL_HWSZ (1<<1) +#define USB_SBUS_CTRL_BSZ (1<<0) + +#define USB_MSR_ERR_ILLBM (1<<18) +#define USB_MSR_ERR_ILLBRST (1<<17) +#define USB_MSR_ERR_UADDRSTS (1<<16) +#define USB_MSR_ERR_BMMSK (1<<2) +#define USB_MSR_ERR_BRSTMSK (1<<1) +#define USB_MSR_ERR_UADMK (1<<0) + +#define USB_DWC_CTRL3_VATEST_EN (1<<20) +#define USB_DWC_CTRL3_OHC1_CLKEN (1<<19) +#define USB_DWC_CTRL3_OHC0_CLKEN (1<<18) +#define USB_DWC_CTRL3_EHC_CLKEN (1<<17) +#define USB_DWC_CTRL3_OTG_CLKEN (1<<16) +#define USB_DWC_CTRL3_OHCI_SUSP (1<<3) +#define USB_DWC_CTRL3_VBUS_VALID_PORT1 (1<<2) +#define USB_DWC_CTRL3_VBUS_VALID_PORT0 (1<<1) +#define USB_DWC_CTRL3_VBUS_VALID_SEL (1<<0) + +#define USB_DWC_CTRL4_USB_MODE (1<<16) +#define USB_DWC_CTRL4_AHB_CLKDIV(n) ((n&0xF)<<0) + +#define USB_OTG_STATUS_IDPULLUP (1<<8) +#define USB_OTG_STATUS_IDDIG (1<<7) +#define USB_OTG_STATUS_DISCHRGVBUS (1<<6) +#define USB_OTG_STATUS_CHRGVBUS (1<<5) +#define USB_OTG_STATUS_DRVVBUS (1<<4) +#define USB_OTG_STATUS_SESSIONEND (1<<3) +#define USB_OTG_STATUS_VBUSVALID (1<<2) +#define USB_OTG_STATUS_BVALID (1<<1) +#define USB_OTG_STATUS_AVALID (1<<0) + +#define USB_DWC_CTRL5_REFCLK_DIV(n) ((n&3)<<18) +#define USB_DWC_CTRL5_REFCLK_EN(n) ((n&3)<<16) +#define USB_DWC_CTRL5_SIDDQ (1<<1) +#define USB_DWC_CTRL5_COMMONONN (1<<0) + +#define USB_DWC_CTRL6_DMPULLDOWN_PORT1 (1<<3) +#define USB_DWC_CTRL6_DPPULLDOWN_PORT1 (1<<2) +#define USB_DWC_CTRL6_DMPULLDOWN_PORT2 (1<<1) +#define USB_DWC_CTRL6_DPPULLDOWN_PORT2 (1<<0) + +#define USB_DWC_CTRL7_OHC_STARTCLK (1<<0) + +#define USB_PHY_STATUS_VBUS (1<<0) + +// Bit defines used for status and enable registers +#define USB_INTR_S2A (1<<6) +#define USB_INTR_FORCE (1<<5) +#define USB_INTR_PHY (1<<4) +#define USB_INTR_DEVICE (1<<3) +#define USB_INTR_EHCI (1<<2) +#define USB_INTR_OHCI1 (1<<1) +#define USB_INTR_OHCI0 (1<<0) + + +#endif /* CONFIG_SOC_AU13XX */ +#endif /* _AU13XX_H */ diff --git a/arch/mips/include/asm/mach-au1x00/au1xxx.h b/arch/mips/include/asm/mach-au1x00/au1xxx.h index 1b36550..9a6d9f1 100644 --- a/arch/mips/include/asm/mach-au1x00/au1xxx.h +++ b/arch/mips/include/asm/mach-au1x00/au1xxx.h @@ -38,6 +38,9 @@ #elif defined(CONFIG_MIPS_DB1200) #include +#elif defined(CONFIG_MIPS_DB1300) +#include + #endif #endif /* _AU1XXX_H_ */ diff --git a/arch/mips/include/asm/mach-au1x00/dev_boards.h b/arch/mips/include/asm/mach-au1x00/dev_boards.h new file mode 100644 index 0000000..27bca17 --- /dev/null +++ b/arch/mips/include/asm/mach-au1x00/dev_boards.h @@ -0,0 +1,44 @@ +/* + * Copyright 2003-2008 RMI Corporation. All rights reserved. + * Author: Kevin Hickey + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED BY RMI Corporation 'AS IS' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL RMI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef _AU_DEV_BOARDS_H +#define _AU_DEV_BOARDS_H + +#ifdef CONFIG_MIPS_DB1300 +#include +#endif + +#ifdef CONFIG_MIPS_DB1200 +#include +#endif + +void db_set_hex(u8 val); + +/* + * 2 dots use 2 bits + */ +void db_set_hex_dots(u8 val); + +#endif /* _AU_DEV_BOARDS_H */ diff --git a/arch/mips/include/asm/mips-boards/db1300.h b/arch/mips/include/asm/mips-boards/db1300.h new file mode 100644 index 0000000..5d7ce9d --- /dev/null +++ b/arch/mips/include/asm/mips-boards/db1300.h @@ -0,0 +1,120 @@ +/* + * Copyright 2003-2008 RMI Corporation. All rights reserved. + * Author: Kevin Hickey + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED BY RMI Corporation 'AS IS' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL RMI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#ifndef ASM_DB1300_H +#define ASM_DB1300_H +#ifdef CONFIG_MIPS_DB1300 +#include /* For KSEG1_OFFSET */ + +struct db1300_hex_regs { + u16 hex; /* Write 8-bit value here */ + u16 reserved; + u16 blank; /* Write 11b to blank */ +}; + + +#define DB1300_HEX_REGS_PHYS_ADDR 0x19C00000 + +/* For alchemy/dev_boards/leds.c */ +typedef struct db1300_hex_regs hex_regs; +#define HEX_REGS_KSEG1_ADDR DB1300_HEX_REGS_PHYS_ADDR + KSEG1_OFFSET + +struct bcsr_regs { + /*00*/ u16 whoami; + u16 reserved0; + /*04*/ u16 status; + u16 reserved1; + /*08*/ u16 switches; + u16 reserved2; + /*0C*/ u16 resets; + u16 reserved3; + + /*10*/ u16 pcmcia; + u16 reserved4; + /*14*/ u16 board; + u16 reserved5; + /*18*/ u16 disk_leds; + u16 reserved6; + /*1C*/ u16 system; + u16 reserved7; + + /*20*/ u16 intclr; + u16 reserved8; + /*24*/ u16 intset; + u16 reserved9; + /*28*/ u16 intclr_mask; + u16 reserved10; + /*2C*/ u16 intset_mask; + u16 reserved11; + + /*30*/ u16 sig_status; + u16 reserved12; + /*34*/ u16 int_status; + u16 reserved13; + /*38*/ u16 reserved14; + u16 reserved15; + /*3C*/ u16 reserved16; + u16 reserved17; +}; + +#define DB1300_BCSR_REGS_PHYS_ADDR 0x19800000 +#define BCSR_REGS_KSEG1_ADDR (KSEG1_OFFSET + DB1300_BCSR_REGS_PHYS_ADDR) + +static volatile struct bcsr_regs *const db_bcsr = + (struct bcsr_regs *)(DB1300_BCSR_REGS_PHYS_ADDR + KSEG1_OFFSET); + +#define BCSR_STATUS_SD1_WP (1<<10) +#define BCSR_INT_SD1_INSERT (1<<12) + +#define BCSR_RESETS_USB_OTG 0x4000 +#define BCSR_RESETS_USB_HOST 0x8000 + +#define CASCADE_IRQ_MIN 129 + +enum db1300_cascade_irqs { + DB1300_IDE_IRQ = CASCADE_IRQ_MIN, + DB1300_ETHERNET_IRQ, + DB1300_AC97_IRQ, + DB1300_AC97_PEN_IRQ, +}; + +#define CASCADE_IRQ_MAX DB1300_AC97_PEN_IRQ + +#define CASCADE_IRQ (5 + GPINT_LINUX_IRQ_OFFSET) +#define CASCADE_IRQ_TYPE_STRING "DB1300 Cascade" + +/* + * Defines for au1xxx-ide + * See the CPLD/BCSR datasheet for details + */ +#define IDE_PHYS_ADDR 0x18800000 +#define IDE_REG_SHIFT 5 +#define IDE_INT DB1300_IDE_IRQ +#define IDE_DDMA_REQ DSCR_CMD0_DMA_REQ1 +#define IDE_RQSIZE 128 +#define IDE_PHYS_LEN (16 << IDE_REG_SHIFT) + + +#endif /* CONFIG_MIPS_DB1300 */ +#endif /* ASM_DB1300_H */ diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index a7162a4..03e0ae7 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -189,6 +189,7 @@ void __init check_wait(void) case CPU_AU1200: case CPU_AU1210: case CPU_AU1250: + case CPU_AU13XX: cpu_wait = au1k_wait; break; case CPU_20KC: @@ -819,6 +820,20 @@ static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu) } } +static inline void cpu_probe_rmi(struct cpuinfo_mips *c, unsigned int cpu) +{ + decode_configs(c); + switch(c->processor_id & 0xff00) { + case PRID_IMP_AU13XX: + c->cputype = CPU_AU13XX; + __cpu_name[cpu] = "Au13xx"; + break; + default: + panic("Unknown RMI Core!\n"); + break; + } +} + static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu) { decode_configs(c); @@ -936,6 +951,11 @@ __cpuinit void cpu_probe(void) case PRID_COMP_CAVIUM: cpu_probe_cavium(c, cpu); break; + case PRID_COMP_RMI: + cpu_probe_rmi(c, cpu); + break; + default: + c->cputype = CPU_UNKNOWN; } BUG_ON(!__cpu_name[cpu]); diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index c43f4b2..2b4736a 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -1033,6 +1033,7 @@ static void __cpuinit probe_pcache(void) case CPU_AU1200: case CPU_AU1210: case CPU_AU1250: + case CPU_AU13XX: c->icache.flags |= MIPS_CACHE_IC_F_DC; break; } diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index 4294203..ee5e2de 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -299,6 +299,7 @@ static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l, case CPU_AU1200: case CPU_AU1210: case CPU_AU1250: + case CPU_AU13XX: case CPU_PR4450: uasm_i_nop(p); tlbw(p); -- 1.5.4.3 From khickey@rmicorp.com Fri Mar 6 16:21:41 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 06 Mar 2009 16:21:46 +0000 (GMT) Received: from mx1.rmicorp.com ([63.111.213.197]:35445 "EHLO mx1.rmicorp.com") by ftp.linux-mips.org with ESMTP id S21366484AbZCFQUT (ORCPT ); Fri, 6 Mar 2009 16:20:19 +0000 Received: from sark.razamicroelectronics.com ([10.8.0.254]) by mx1.rmicorp.com with Microsoft SMTPSVC(6.0.3790.3959); Fri, 6 Mar 2009 08:20:09 -0800 Received: from localhost.localdomain (unknown [10.8.0.23]) by sark.razamicroelectronics.com (Postfix) with ESMTP id C4D62EE76A5; Fri, 6 Mar 2009 09:42:10 -0600 (CST) From: Kevin Hickey To: ralf@linux-mips.org, linux-mips@linux-mips.org Cc: Kevin Hickey Subject: [PATCH 02/10] Alchemy: Au1300 new interrupt controller Date: Fri, 6 Mar 2009 10:20:01 -0600 Message-Id: <0b447f7e26be90a9179bdf89ca2cfd1f34c5d16e.1236354153.git.khickey@rmicorp.com> X-Mailer: git-send-email 1.5.4.3 In-Reply-To: <788248524efc28ba2608ed79bfb7080ee476b12d.1236354153.git.khickey@rmicorp.com> References: <> <1236356409-32357-1-git-send-email-khickey@rmicorp.com> <788248524efc28ba2608ed79bfb7080ee476b12d.1236354153.git.khickey@rmicorp.com> In-Reply-To: <788248524efc28ba2608ed79bfb7080ee476b12d.1236354153.git.khickey@rmicorp.com> References: <788248524efc28ba2608ed79bfb7080ee476b12d.1236354153.git.khickey@rmicorp.com> X-OriginalArrivalTime: 06 Mar 2009 16:20:09.0372 (UTC) FILETIME=[6B3545C0:01C99E77] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22020 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: khickey@rmicorp.com Precedence: bulk X-list: linux-mips The Au1300 has a new interrupt controller (relative to the rest of the Alchemy line). The differences were great enough to justify adding a whole new module. Included in this patch is the new interrupt controller, a new implementation of the cascade interrupt controller on the DB1300 board and some code to drive LEDs on the DB1300 that is used by the interrupt controller. A small change was made to the existing interrupt controller; it is "ifdef'd out" for Au1300. Since the cascade interrupt controller is virtually indentical (with the exception of some constants) between the DB1300 and DB1200, a future optimization may be to use the same code for both boards. Signed-off-by: Kevin Hickey --- arch/mips/alchemy/Kconfig | 4 + arch/mips/alchemy/common/Makefile | 4 +- arch/mips/alchemy/common/gpio_int.c | 268 ++++++++++++++++++++++++++ arch/mips/alchemy/common/irq.c | 3 + arch/mips/alchemy/devboards/Makefile | 5 + arch/mips/alchemy/devboards/cascade_irq.c | 142 ++++++++++++++ arch/mips/alchemy/devboards/leds.c | 58 ++++++ arch/mips/include/asm/mach-au1x00/gpio_int.h | 239 +++++++++++++++++++++++ arch/mips/include/asm/mach-au1x00/irq.h | 34 ++++ 9 files changed, 756 insertions(+), 1 deletions(-) create mode 100644 arch/mips/alchemy/common/gpio_int.c create mode 100644 arch/mips/alchemy/devboards/cascade_irq.c create mode 100644 arch/mips/alchemy/devboards/leds.c create mode 100644 arch/mips/include/asm/mach-au1x00/gpio_int.h create mode 100644 arch/mips/include/asm/mach-au1x00/irq.h diff --git a/arch/mips/alchemy/Kconfig b/arch/mips/alchemy/Kconfig index 7198a88..2e189c2 100644 --- a/arch/mips/alchemy/Kconfig +++ b/arch/mips/alchemy/Kconfig @@ -114,18 +114,22 @@ endchoice config SOC_AU1000 bool select SOC_AU1X00 + select AU_INT_CNTLR config SOC_AU1100 bool select SOC_AU1X00 + select AU_INT_CNTLR config SOC_AU1500 bool select SOC_AU1X00 + select AU_INT_CNTLR config SOC_AU1550 bool select SOC_AU1X00 + select AU_INT_CNTLR config SOC_AU1200 bool diff --git a/arch/mips/alchemy/common/Makefile b/arch/mips/alchemy/common/Makefile index d50d476..85ffa2e 100644 --- a/arch/mips/alchemy/common/Makefile +++ b/arch/mips/alchemy/common/Makefile @@ -7,7 +7,9 @@ obj-y += prom.o irq.o puts.o time.o reset.o \ clocks.o platform.o power.o setup.o \ - sleeper.o dma.o dbdma.o gpio.o + sleeper.o dma.o dbdma.o gpio.o gpio_int.o + +obj-$(CONFIG_SOC_AU13XX) += au13xx_res.o obj-$(CONFIG_PCI) += pci.o diff --git a/arch/mips/alchemy/common/gpio_int.c b/arch/mips/alchemy/common/gpio_int.c new file mode 100644 index 0000000..c09b793 --- /dev/null +++ b/arch/mips/alchemy/common/gpio_int.c @@ -0,0 +1,268 @@ +/* + * Copyright 2008 RMI Corporation + * Author: Kevin Hickey + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifdef CONFIG_AU_GPIO_INT_CNTLR + +#include +#include +#include /* For functions called by do_IRQ */ +#include + +#include +#include + +#include + +volatile struct gpio_int_regs *const gpio_int = + (struct gpio_int_regs *)(GPIO_INT_CTRLR_BASE + KSEG1_OFFSET); + +static struct gpio_int_cfg __initdata basic_irqs[]; + +#ifdef CONFIG_SOC_AU13XX +static struct gpio_int_cfg __initdata basic_irqs[] = { + { AU1300_IRQ_DDMA, 1, LEVEL_HIGH, HW_INT_1, DEV_CTRL }, + + { AU1300_IRQ_RTC_TICK, 1, RISING, HW_INT_1, DEV_CTRL }, + { AU1300_IRQ_TOY_TICK, 1, RISING, HW_INT_1, DEV_CTRL }, + + { AU1300_IRQ_LCD, 1, LEVEL_HIGH, HW_INT_1, DEV_CTRL }, + + { AU1300_IRQ_UART1, 1, LEVEL_HIGH, HW_INT_1, DEV_CTRL }, + { AU1300_IRQ_UART1, 1, LEVEL_HIGH, HW_INT_1, DEV_CTRL }, + { AU1300_IRQ_UART2, 1, LEVEL_HIGH, HW_INT_1, DEV_CTRL }, + { AU1300_IRQ_UART3, 1, LEVEL_HIGH, HW_INT_1, DEV_CTRL }, + + { AU1300_IRQ_SD1, 1, LEVEL_HIGH, HW_INT_1, DEV_CTRL }, + { AU1300_IRQ_SD2, 1, LEVEL_HIGH, HW_INT_1, DEV_CTRL }, + + { AU1300_IRQ_USB, 1, LEVEL_HIGH, HW_INT_1, DEV_CTRL }, + + { AU1300_IRQ_BSA, 1, LEVEL_HIGH, HW_INT_1, DEV_CTRL }, + { AU1300_IRQ_MPE, 1, RISING, HW_INT_1, DEV_CTRL }, + { AU1300_IRQ_ITE, 1, LEVEL_HIGH, HW_INT_1, DEV_CTRL }, + + { AU1300_IRQ_RTCMATCH_1, 1, RISING, HW_INT_1, DEV_CTRL }, + { AU1300_IRQ_RTCMATCH_1, 1, RISING, HW_INT_1, DEV_CTRL }, + { AU1300_IRQ_RTCMATCH_2, 0, RISING, HW_INT_0, DEV_CTRL }, + + { AU1300_IRQ_TOYMATCH_1, 1, RISING, HW_INT_1, DEV_CTRL }, + { AU1300_IRQ_TOYMATCH_1, 1, RISING, HW_INT_1, DEV_CTRL }, + { AU1300_IRQ_TOYMATCH_2, 1, RISING, HW_INT_1, DEV_CTRL }, + + + // KH: TODO - Move this to the board file. + { 5, 0, LEVEL_HIGH, HW_INT_0, GPIO_IN }, +}; + +/* + * KH: TODO - Consider moving to board specific location... + */ +static struct gpio_int_cfg __initdata basic_gpios[] = { + { 32, 0, DISABLED, HW_INT_0, DEV_CTRL }, + { 33, 0, DISABLED, HW_INT_0, DEV_CTRL }, + { 34, 0, DISABLED, HW_INT_0, DEV_CTRL }, + { 35, 0, DISABLED, HW_INT_0, DEV_CTRL }, + { 36, 0, DISABLED, HW_INT_0, DEV_CTRL }, + { 37, 0, DISABLED, HW_INT_0, DEV_CTRL }, +}; +#endif + +int __initdata nr_basic_irqs = ARRAY_SIZE(basic_irqs); + +/* + **************************************************************************** + * Functions and delcaration for irq_chip + **************************************************************************** + */ +void gpio_int_ack(unsigned int irq) +{ + u32 intr = irq - GPINT_LINUX_IRQ_OFFSET; + u32 bank = GPINT_BANK_FROM_INT(intr); + u32 bit = GPINT_BIT_FROM_INT(bank, intr); + + au_iowrite32(bit, &gpio_int->int_pend[bank]); +} + +void gpio_int_mask(unsigned int irq) +{ + u32 intr = irq - GPINT_LINUX_IRQ_OFFSET; + u32 bank = GPINT_BANK_FROM_INT(intr); + u32 bit = GPINT_BIT_FROM_INT(bank, intr); + + au_iowrite32(bit, &gpio_int->int_maskclr[bank]); +} + +void gpio_int_unmask(unsigned int irq) +{ + u32 intr = irq - GPINT_LINUX_IRQ_OFFSET; + u32 bank = GPINT_BANK_FROM_INT(intr); + u32 bit = GPINT_BIT_FROM_INT(bank, intr); + + au_iowrite32(bit, &gpio_int->int_mask[bank]); +} + +void gpio_int_mask_ack(unsigned int irq) +{ + u32 intr = irq - GPINT_LINUX_IRQ_OFFSET; + u32 bank = GPINT_BANK_FROM_INT(intr); + u32 bit = GPINT_BIT_FROM_INT(bank, intr); + + au_iowrite32(bit, &gpio_int->int_maskclr[bank]); + au_iowrite32(bit, &gpio_int->int_pend[bank]); +} + +static struct irq_chip gpio_int_irq_type = { + .name = "Au GPIO/INT", + .ack = gpio_int_ack, + .mask = gpio_int_mask, + .unmask = gpio_int_unmask, + .mask_ack = gpio_int_mask_ack +}; +/*****************************************************************************/ + +void set_pin_cfg(const struct gpio_int_cfg *cfg) +{ + u32 tmp; + tmp = GPINT_PINCTL_N(cfg->pinctl); + tmp |= GPINT_INTLINE_N(cfg->intline); + tmp |= GPINT_INTCFG_N(cfg->intcfg); + tmp |= cfg->intwake ? GPINT_INTWAKE_ENABLE : 0; + au_iowrite32(tmp, &gpio_int->gp_int[cfg->number]); +} + +void set_gpio(u8 gpio, u8 value) +{ + u32 bank = GPINT_BANK_FROM_GPIO(gpio); + u32 bit = GPINT_BIT_FROM_GPIO(bank, gpio); + + if (value == 0) + au_iowrite32(1 << bit, &gpio_int->pin_valclr[bank]); + else + au_iowrite32(1 << bit, &gpio_int->pin_val[bank]); +} + +u8 get_gpio(u8 gpio) +{ + u32 bank = GPINT_BANK_FROM_GPIO(gpio); + u32 bit = GPINT_BIT_FROM_GPIO(bank, gpio); + u32 tmp; + + tmp = au_ioread32(&gpio_int->pin_val[bank]); + return tmp >> bit; +} + + +void __init arch_init_irq(void) +{ + int i; + + /* + * Initialize the basic MIPS interrupt components. + */ + mips_cpu_irq_init(); + + for (i = 0; i < GPINT_NUM_BANKS; ++i) + gpio_int->int_maskclr[i] = ~0UL; + + + for (i = 0; i < ARRAY_SIZE(basic_gpios); ++i) { + set_pin_cfg(&basic_gpios[i]); + } + + for (i = 0; i < nr_basic_irqs; ++i) { + printk("Initializing IRQ %d\n", basic_irqs[i].number); + set_pin_cfg(&basic_irqs[i]); + if (basic_irqs[i].intcfg == LEVEL_LOW) + set_irq_chip_and_handler_name( + basic_irqs[i].number + GPINT_LINUX_IRQ_OFFSET, + &gpio_int_irq_type, + handle_level_irq, + "lowlevel"); + else if (basic_irqs[i].intcfg == LEVEL_HIGH) + set_irq_chip_and_handler_name( + basic_irqs[i].number + GPINT_LINUX_IRQ_OFFSET, + &gpio_int_irq_type, + handle_level_irq, + "highlevel"); + else if (basic_irqs[i].intcfg == FALLING) + set_irq_chip_and_handler_name( + basic_irqs[i].number + GPINT_LINUX_IRQ_OFFSET, + &gpio_int_irq_type, + handle_edge_irq, + "fallingedge"); + else if (basic_irqs[i].intcfg == RISING) + set_irq_chip_and_handler_name( + basic_irqs[i].number + GPINT_LINUX_IRQ_OFFSET, + &gpio_int_irq_type, + handle_edge_irq, + "risingedge"); + else if (basic_irqs[i].intcfg == ANY_CHANGE) + set_irq_chip_and_handler_name( + basic_irqs[i].number + GPINT_LINUX_IRQ_OFFSET, + &gpio_int_irq_type, + handle_edge_irq, + "bothedge"); + else + set_irq_chip( + basic_irqs[i].number + GPINT_LINUX_IRQ_OFFSET, + &gpio_int_irq_type); + } + + set_c0_status(IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4); + + board_init_irq(); +} + +asmlinkage void plat_irq_dispatch(void) +{ + unsigned int intr; + u32 bank; + u32 reg_msk; + unsigned int pending = read_c0_status() & read_c0_cause(); + /* + * C0 timer tick + */ + if (pending & CAUSEF_IP7) + do_IRQ(MIPS_CPU_IRQ_BASE + 7); + else if (pending & (CAUSEF_IP2 | CAUSEF_IP3)) { + intr = au_ioread32(&gpio_int->pri_enc); + bank = GPINT_BANK_FROM_INT(intr); + reg_msk = GPINT_BIT_FROM_INT(bank, intr); + + if (intr != 127) { + if (pending & CAUSEF_IP3) + board_irq_dispatch(intr); + + do_IRQ(GPINT_LINUX_IRQ_OFFSET + intr); + } + } else { + printk(KERN_WARNING + "ALCHEMY GPIO_INT: Unexpected cause was set. %08x\n", + pending); + } + +} + +#endif diff --git a/arch/mips/alchemy/common/irq.c b/arch/mips/alchemy/common/irq.c index c88c821..f8742dd 100644 --- a/arch/mips/alchemy/common/irq.c +++ b/arch/mips/alchemy/common/irq.c @@ -24,6 +24,7 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 675 Mass Ave, Cambridge, MA 02139, USA. */ +#ifdef CONFIG_AU_INT_CNTLR #include #include @@ -609,3 +610,5 @@ void __init arch_init_irq(void) set_c0_status(IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3); } + +#endif diff --git a/arch/mips/alchemy/devboards/Makefile b/arch/mips/alchemy/devboards/Makefile index 0d2d224..8cce4d0 100644 --- a/arch/mips/alchemy/devboards/Makefile +++ b/arch/mips/alchemy/devboards/Makefile @@ -17,3 +17,8 @@ obj-$(CONFIG_MIPS_DB1500) += db1x00/ obj-$(CONFIG_MIPS_DB1550) += db1x00/ obj-$(CONFIG_MIPS_BOSPORUS) += db1x00/ obj-$(CONFIG_MIPS_MIRAGE) += db1x00/ + +# These two files are used only by DB1300 today but will be used by DB1200 and +# possibly others in the future. +obj-$(CONFIG_MIPS_DB1300) += cascade_irq.o +obj-$(CONFIG_MIPS_DB1300) += leds.o diff --git a/arch/mips/alchemy/devboards/cascade_irq.c b/arch/mips/alchemy/devboards/cascade_irq.c new file mode 100644 index 0000000..6d0a965 --- /dev/null +++ b/arch/mips/alchemy/devboards/cascade_irq.c @@ -0,0 +1,142 @@ +/* + * Copyright 2003-2008 RMI Corporation. All rights reserved. + * Author: Kevin Hickey + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED BY RMI Corporation 'AS IS' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL RMI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include +#include +#include +#include +#include + +#include + +/* + * The following must be declared/defined in an included file: + * - volatile struct bcsr_regs (declared) + * (which much include fields int_status, intset_mask, intclr_mask, intset, + * and intclr) + * - volatile struct bcsr_regs *const bcsr (defined) + * - CASCADE_IRQ_MIN + * - CASCADE_IRQ_MAX + * - CASCADE_IRQ_TYPE_STRING + * - CASCADE_IRQ (System IRQ to which the cascade is connected) + */ + +void __init board_init_irq(void); + +irqreturn_t cascade_handler(int irq, void *dev_id) +{ + u16 int_status = au_ioread16(&db_bcsr->int_status); + int irq_in_service; + + au_iowrite16(int_status, &db_bcsr->int_status); + for ( ; int_status; int_status &= int_status - 1) { + irq_in_service = CASCADE_IRQ_MIN + __ffs(int_status); + db_set_hex((u8)(irq_in_service)); + do_IRQ(irq_in_service); + } + + return IRQ_RETVAL(1); +} + +DEFINE_MUTEX(cascade_use_count_mutex); +static int cascade_use_count = 0; + +static void cascade_mask(unsigned int irq) +{ + au_iowrite16(1 << (irq - CASCADE_IRQ_MIN), &db_bcsr->intclr_mask); +} + +static void cascade_unmask(unsigned int irq) +{ + au_iowrite16(1 << (irq - CASCADE_IRQ_MIN), &db_bcsr->intset_mask); +} + +static void cascade_enable(unsigned int irq) +{ + au_iowrite16(1 << (irq - CASCADE_IRQ_MIN), &db_bcsr->intset); + cascade_unmask(irq); +} + +static void cascade_disable(unsigned int irq) +{ + au_iowrite16(1 << (irq - CASCADE_IRQ_MIN), &db_bcsr->intclr); + cascade_mask(irq); +} + + +static unsigned int cascade_startup(unsigned int irq) +{ + int retval = 0; + + mutex_lock(&cascade_use_count_mutex); + ++cascade_use_count; + if (cascade_use_count == 1) + retval = request_irq(CASCADE_IRQ, + &cascade_handler, 0, "Cascade", + &cascade_handler); + mutex_unlock(&cascade_use_count_mutex); + + cascade_enable(irq); + cascade_unmask(irq); + + return retval; +} + +static void cascade_shutdown(unsigned int irq) +{ + cascade_mask(irq); + cascade_disable(irq); + + mutex_lock(&cascade_use_count_mutex); + --cascade_use_count; + if (cascade_use_count == 0) + free_irq(CASCADE_IRQ, &cascade_handler); + mutex_unlock(&cascade_use_count_mutex); +} + +static struct irq_chip cascade_irq_type = { + .name = CASCADE_IRQ_TYPE_STRING, + .startup = cascade_startup, + .shutdown = cascade_shutdown, + .mask = cascade_mask, + .enable = cascade_enable, + .disable = cascade_disable, + .unmask = cascade_unmask, + .mask_ack = cascade_mask +}; + +void __init board_init_irq(void) +{ + int irq; + + for (irq = CASCADE_IRQ_MIN; + irq < CASCADE_IRQ_MAX; ++irq ) { + printk("Initializing IRQ %d\n", irq); + set_irq_chip_and_handler(irq, &cascade_irq_type, + handle_level_irq); + cascade_disable(irq); + } +} diff --git a/arch/mips/alchemy/devboards/leds.c b/arch/mips/alchemy/devboards/leds.c new file mode 100644 index 0000000..75be345 --- /dev/null +++ b/arch/mips/alchemy/devboards/leds.c @@ -0,0 +1,58 @@ +/* + * Copyright 2003-2008 RMI Corporation. All rights reserved. + * Author: Kevin Hickey + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED BY RMI Corporation 'AS IS' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL RMI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include + +/* + * Requires the following to be defined in the board-specifc .h file: + * - HEX_REGS_KSEG1_ADDR + * - struct hex_regs with members: + * - hex (set the hex value) + * - BCSR_REGS_KSEG1_ADDR + * - struct bcsr_regs + */ + +static volatile hex_regs *const hex = (hex_regs *)(HEX_REGS_KSEG1_ADDR); + +/* + * Takes a u8 because though the register is 16 bits, only 8 appear + */ +void db_set_hex(u8 val) +{ + au_iowrite16((u16)val, &hex->hex); +} + +/* + * 2 dots use the least significant 2 bits + * Setting a bit lights the LED (opposite of the register) + */ +void db_set_hex_dots(u8 val) +{ + u16 leds = au_ioread16(&db_bcsr->disk_leds); + leds |= 0x3; + leds &= (~(val & 0x3)); + au_iowrite16(leds, &db_bcsr->disk_leds); +} diff --git a/arch/mips/include/asm/mach-au1x00/gpio_int.h b/arch/mips/include/asm/mach-au1x00/gpio_int.h new file mode 100644 index 0000000..85df296 --- /dev/null +++ b/arch/mips/include/asm/mach-au1x00/gpio_int.h @@ -0,0 +1,239 @@ +/* + * Copyright 2008 RMI Corporation + * Author: Kevin Hickey + * + * Defines and macros for the GPIO and Interrupt controller for Alchemy, + * introduced in the Au13xx series. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#ifndef _GPIO_INT_H +#define _GPIO_INT_H + +#include + +/* + * There are a total 128 'channels' defined by the Au13xx databook. However, + * this requires 4 sperate 32bit registers for programming. Each register is + * called a 'bank' for ease of use. + */ +#define GPINT_BANK0 0 +#define GPINT_BANK1 1 +#define GPINT_BANK2 2 +#define GPINT_BANK3 3 + +#define GPINT_NUM_BANKS 4 /* 0-3 */ +#define GPINT_MAX_BANK (GPINT_BANK3) + +#define GPINT_GPIO_PER_BANK 32 +#define GPINT_INTS_PER_BANK GPINT_GPIO_PER_BANK + +/* Total number of interrupts our architecture allows */ +#define GPINT_MAX_INTS (GPINT_NUM_BANKS*GPINT_INTS_PER_BANK) + +/* Current maximum supported GPIO/INTERRUPTs */ +#define GPINT_NUM_GPIO GPINT_MAX_INTS +#define GPINT_NUM_INTERRUPTS GPINT_MAX_INTS + +/* Starting GPIO/INTERRUPT for each bank */ +#define GPINT_BANK0_START 0 +#define GPINT_BANK1_START 32 +#define GPINT_BANK2_START 64 +#define GPINT_BANK3_START 96 + +/* divide by 32 to get bank */ +#define GPINT_BANK_FROM_GPIO(n) (n>>5) +#define GPINT_BANK_FROM_INT(n) GPINT_BANK_FROM_GPIO(n) +/* multiply by 32 to get base */ +#define GPINT_BIT_FROM_GPIO(b, n) (1<<(n-(b<<5))) +#define GPINT_BIT_FROM_INT(b, n) GPINT_BIT_FROM_GPIO(b, n) + +struct gpio_int_regs { + /* R/W1S */ + /* u32 pin_val0; 0x00 */ + /* u32 pin_val1; 0x04 */ + /* u32 pin_val2; 0x08 */ + /* u32 pin_val3; 0x0C */ + u32 pin_val[GPINT_NUM_BANKS]; + + /* W1C */ + /* u32 pin_valclr0 0x10 */ + /* u32 pin_valclr1; 0x14 */ + /* u32 pin_valclr2; 0x18 */ + /* u32 pin_valclr3; 0x1C */ + u32 pin_valclr[GPINT_NUM_BANKS]; + + /* R/W1C */ + /* u32 int_pend0; 0x20 */ + /* u32 int_pend1; 0x24 */ + /* u32 int_pend2; 0x28 */ + /* u32 int_pend3; 0x2c */ + u32 int_pend[GPINT_NUM_BANKS]; + + u32 pri_enc; /* 0x30 */ + u32 _resvd0[3]; /* 0x34-0x3c */ + + /* R/W1S */ + /* u32 int_mask0; 0x40 */ + /* u32 int_mask1; 0x44 */ + /* u32 int_mask2; 0x48 */ + /* u32 int_mask3; 0x4c */ + u32 int_mask[GPINT_NUM_BANKS]; + + /* W1C */ + /* u32 int_maskclr0; 0x50 */ + /* u32 int_maskclr1; 0x54 */ + /* u32 int_maskclr2; 0x58 */ + /* u32 int_maskclr3; 0x5C */ + u32 int_maskclr[GPINT_NUM_BANKS]; + + /* R/W */ + u32 dma_sel; /* 0x60 */ + u32 _resvd1[(0x80-0x64)/4]; /* 0x64-0x7C */ + + /* W */ + /* u32 dev_sel0; 0x80 */ + /* u32 dev_sel1; 0x84 */ + /* u32 dev_sel2; 0x88 */ + /* u32 dev_sel3; 0x8C */ + u32 dev_sel[GPINT_NUM_BANKS]; + + /* W */ + /* u32 dev_selclr0; 0x90 */ + /* u32 dev_selclr1; 0x94 */ + /* u32 dev_selclr2; 0x98 */ + /* u32 dev_selclr3; 0x9C */ + u32 dev_selclr[GPINT_NUM_BANKS]; + + /* R */ + /* u32 reset_val0; 0xA0 */ + /* u32 reset_val1; 0xA4 */ + /* u32 reset_val2; 0xA8 */ + /* u32 reset_val3; 0xAC */ + u32 reset_val[GPINT_NUM_BANKS]; + + /* 0xB0 - 0xFFC */ + u32 _resvd2[(0x1000-0xB0)/4]; + + /* R/W -- when interrupt mask is clear */ + /* R -- when interrupt mask is set */ + /* u32 gp_int0; 0x1000 */ + /* u32 gp_int1; 0x1004 */ + /* u32 gp_int2; 0x1008 */ + /* u32 gp_int2; 0x100C */ + /* u32 gp_intN; 0x1000 + (N*4) */ + u32 gp_int[GPINT_MAX_INTS]; +}; + +extern volatile struct gpio_int_regs *const gpio_int; + +#define GPINT_DMASEL_DMA0 (0) +#define GPINT_DMASEL_DMA0_N(n) (((n)&0xFF)< + * + * Defines and macros for the GPIO and Interrupt controller for Alchemy, + * introduced in the Au13xx series. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#ifndef _MACH_AU1X00_INT_H +#define _MACH_AU1X00_INT_H + +#define NR_IRQS 255 +#define MIPS_CPU_IRQ_BASE 0 + +#endif /* _MACH_AU1X00_INT_H */ -- 1.5.4.3 From khickey@rmicorp.com Fri Mar 6 16:22:04 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 06 Mar 2009 16:22:06 +0000 (GMT) Received: from mx1.rmicorp.com ([63.111.213.197]:35445 "EHLO mx1.rmicorp.com") by ftp.linux-mips.org with ESMTP id S21366486AbZCFQUU (ORCPT ); Fri, 6 Mar 2009 16:20:20 +0000 Received: from sark.razamicroelectronics.com ([10.8.0.254]) by mx1.rmicorp.com with Microsoft SMTPSVC(6.0.3790.3959); Fri, 6 Mar 2009 08:20:09 -0800 Received: from localhost.localdomain (unknown [10.8.0.23]) by sark.razamicroelectronics.com (Postfix) with ESMTP id 15921EE76AD; Fri, 6 Mar 2009 09:42:11 -0600 (CST) From: Kevin Hickey To: ralf@linux-mips.org, linux-mips@linux-mips.org Cc: Kevin Hickey Subject: [PATCH 08/10] Alchemy: DB1300 blink leds on timer tick Date: Fri, 6 Mar 2009 10:20:07 -0600 Message-Id: X-Mailer: git-send-email 1.5.4.3 In-Reply-To: References: <> <1236356409-32357-1-git-send-email-khickey@rmicorp.com> <788248524efc28ba2608ed79bfb7080ee476b12d.1236354153.git.khickey@rmicorp.com> <0b447f7e26be90a9179bdf89ca2cfd1f34c5d16e.1236354153.git.khickey@rmicorp.com> <7afc5c84989c4bc0f94181397369f284f2bb6924.1236354153.git.khickey@rmicorp.com> <0946334bbaf9883076889fe060a362b72d31e6f4.1236354153.git.khickey@rmicorp.com> <394c116b9fa5bd1865ac21d11185f09e07bd2ab5.1236354153.git.khickey@rmicorp.com> <7e632686ab9b29a94eefeb2e5dca8b091a956b95.1236354153.git.khickey@rmicorp.com> In-Reply-To: <788248524efc28ba2608ed79bfb7080ee476b12d.1236354153.git.khickey@rmicorp.com> References: <788248524efc28ba2608ed79bfb7080ee476b12d.1236354153.git.khickey@rmicorp.com> X-OriginalArrivalTime: 06 Mar 2009 16:20:10.0043 (UTC) FILETIME=[6B9BA8B0:01C99E77] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22021 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: khickey@rmicorp.com Precedence: bulk X-list: linux-mips Blinks the dots on the hex display on the DB1300 board every 1000 timer ticks. This can help tell the difference between a soft and hard hung board. Signed-off-by: Kevin Hickey --- arch/mips/alchemy/common/time.c | 16 ++++++++++++++++ 1 files changed, 16 insertions(+), 0 deletions(-) diff --git a/arch/mips/alchemy/common/time.c b/arch/mips/alchemy/common/time.c index f58d4ff..2b2f6bf 100644 --- a/arch/mips/alchemy/common/time.c +++ b/arch/mips/alchemy/common/time.c @@ -39,6 +39,10 @@ #include #include +#ifdef CONFIG_MIPS_DB1300 +#include +#endif + /* 32kHz clock enabled and detected */ #define CNTR_OK (SYS_CNTRL_E0 | SYS_CNTRL_32S) @@ -60,6 +64,11 @@ static struct clocksource au1x_counter1_clocksource = { static int au1x_rtcmatch2_set_next_event(unsigned long delta, struct clock_event_device *cd) { +#ifdef CONFIG_MIPS_DB1300 + static u8 dots = 1; + static u32 delayer = 0; +#endif + delta += au_readl(SYS_RTCREAD); /* wait for register access */ while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M21) @@ -67,6 +76,13 @@ static int au1x_rtcmatch2_set_next_event(unsigned long delta, au_writel(delta, SYS_RTCMATCH2); au_sync(); +#ifdef CONFIG_MIPS_DB1300 + if (++delayer % 1000 == 0) { + db_set_hex_dots(dots++); + dots %= 4; + } +#endif + return 0; } -- 1.5.4.3 From khickey@rmicorp.com Fri Mar 6 16:22:23 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 06 Mar 2009 16:22:27 +0000 (GMT) Received: from mx1.rmicorp.com ([63.111.213.197]:35445 "EHLO mx1.rmicorp.com") by ftp.linux-mips.org with ESMTP id S21366481AbZCFQUU (ORCPT ); Fri, 6 Mar 2009 16:20:20 +0000 Received: from sark.razamicroelectronics.com ([10.8.0.254]) by mx1.rmicorp.com with Microsoft SMTPSVC(6.0.3790.3959); Fri, 6 Mar 2009 08:20:09 -0800 Received: from localhost.localdomain (unknown [10.8.0.23]) by sark.razamicroelectronics.com (Postfix) with ESMTP id D70F6EE76AB; Fri, 6 Mar 2009 09:42:10 -0600 (CST) From: Kevin Hickey To: ralf@linux-mips.org, linux-mips@linux-mips.org Cc: Kevin Hickey Subject: [PATCH 06/10] Alchemy: Au1300 USB support Date: Fri, 6 Mar 2009 10:20:05 -0600 Message-Id: <7e632686ab9b29a94eefeb2e5dca8b091a956b95.1236354153.git.khickey@rmicorp.com> X-Mailer: git-send-email 1.5.4.3 In-Reply-To: <394c116b9fa5bd1865ac21d11185f09e07bd2ab5.1236354153.git.khickey@rmicorp.com> References: <> <1236356409-32357-1-git-send-email-khickey@rmicorp.com> <788248524efc28ba2608ed79bfb7080ee476b12d.1236354153.git.khickey@rmicorp.com> <0b447f7e26be90a9179bdf89ca2cfd1f34c5d16e.1236354153.git.khickey@rmicorp.com> <7afc5c84989c4bc0f94181397369f284f2bb6924.1236354153.git.khickey@rmicorp.com> <0946334bbaf9883076889fe060a362b72d31e6f4.1236354153.git.khickey@rmicorp.com> <394c116b9fa5bd1865ac21d11185f09e07bd2ab5.1236354153.git.khickey@rmicorp.com> In-Reply-To: <788248524efc28ba2608ed79bfb7080ee476b12d.1236354153.git.khickey@rmicorp.com> References: <788248524efc28ba2608ed79bfb7080ee476b12d.1236354153.git.khickey@rmicorp.com> X-OriginalArrivalTime: 06 Mar 2009 16:20:09.0887 (UTC) FILETIME=[6B83DAF0:01C99E77] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22022 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: khickey@rmicorp.com Precedence: bulk X-list: linux-mips Adds support for USB 2.0 on the Au1300 SOC. Signed-off-by: Kevin Hickey --- drivers/usb/Kconfig | 1 + drivers/usb/host/ehci-au13xx.c | 213 ++++++++++++++++++++++++++++++++++++++++ drivers/usb/host/ehci-hcd.c | 5 + 3 files changed, 219 insertions(+), 0 deletions(-) create mode 100644 drivers/usb/host/ehci-au13xx.c diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig index 83babb0..a50d053 100644 --- a/drivers/usb/Kconfig +++ b/drivers/usb/Kconfig @@ -55,6 +55,7 @@ config USB_ARCH_HAS_EHCI boolean default y if PPC_83xx default y if SOC_AU1200 + default y if SOC_AU13XX default y if ARCH_IXP4XX default PCI diff --git a/drivers/usb/host/ehci-au13xx.c b/drivers/usb/host/ehci-au13xx.c new file mode 100644 index 0000000..fe03667 --- /dev/null +++ b/drivers/usb/host/ehci-au13xx.c @@ -0,0 +1,213 @@ +/* + * Copyright 2008 RMI Corporation + * Author: Kevin Hickey + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + * Based on ehci-au1xxx.c. + */ + +#include +#include + + +extern int usb_disabled(void); + +static void au13xx_start_ehc(void) +{ + AU13XX_USB* au13xx_usb = (AU13XX_USB*)(KSEG1 | USB_BASE_PHYS_ADDR); + /* + * Enable clocks. + */ + AU_SET_BITS_32(USB_DWC_CTRL3_EHC_CLKEN, &au13xx_usb->dwc_ctrl3); + + /* + * Take the host controller block out of reset + */ + AU_SET_BITS_32(USB_DWC_CTRL1_HSTRS, &au13xx_usb->dwc_ctrl1); + + /* + * Enable all of the PHYs + */ + AU_SET_BITS_32(USB_DWC_CTRL2_PHYRS | USB_DWC_CTRL2_PHY0RS | USB_DWC_CTRL2_PH1RS, + &au13xx_usb->dwc_ctrl2); + + /* + * Enable interrupts + */ + AU_SET_BITS_32(USB_INTR_EHCI, &au13xx_usb->intr_enable); + + /* + * This bit enables coherent DMA. + */ + AU_SET_BITS_32(USB_SBUS_CTRL_SBCA, &au13xx_usb->sbus_ctrl); + asm("sync"); +} + +static void au13xx_stop_ehc(void) +{ + AU13XX_USB* au13xx_usb = (AU13XX_USB*)(KSEG1 | USB_BASE_PHYS_ADDR); + /* + * Disable the EHCI interrupt + */ + AU_CLEAR_BITS_32(USB_INTR_EHCI, &au13xx_usb->intr_enable); + + /* + * Disable the clock to the EHCI block + */ + AU_CLEAR_BITS_32(USB_DWC_CTRL3_EHC_CLKEN, &au13xx_usb->dwc_ctrl3); + + /* + * Note: we're not disabling the PHY here because the OHCI and EHCI + * drivers share a PHY and the OHCI driver may still be active. + */ +} + +static const struct hc_driver ehci_au13xx_hc_driver = { + .description = hcd_name, + .product_desc = "Au13xx EHCI", + .hcd_priv_size = sizeof(struct ehci_hcd), + + /* + * generic hardware linkage + */ + .irq = ehci_irq, + .flags = HCD_MEMORY | HCD_USB2, + + /* + * basic lifecycle operations + */ + .reset = ehci_init, + .start = ehci_run, + .stop = ehci_stop, + .shutdown = ehci_shutdown, + + /* + * managing i/o requests and associated device resources + */ + .urb_enqueue = ehci_urb_enqueue, + .urb_dequeue = ehci_urb_dequeue, + .endpoint_disable = ehci_endpoint_disable, + + /* + * scheduling support + */ + .get_frame_number = ehci_get_frame, + + /* + * root hub support + */ + .hub_status_data = ehci_hub_status_data, + .hub_control = ehci_hub_control, + .bus_suspend = ehci_bus_suspend, + .bus_resume = ehci_bus_resume, + .relinquish_port = ehci_relinquish_port, + .port_handed_over = ehci_port_handed_over, +}; + +static int ehci_hcd_au13xx_drv_probe(struct platform_device *pdev) +{ + struct usb_hcd *hcd; + struct ehci_hcd *ehci; + int ret; + + if (usb_disabled()) + return -ENODEV; + + if (pdev->resource[1].flags != IORESOURCE_IRQ) { + pr_debug("resource[1] is not IORESOURCE_IRQ"); + return -ENOMEM; + } + hcd = usb_create_hcd(&ehci_au13xx_hc_driver, &pdev->dev, + dev_name(&pdev->dev)); + + if (!hcd) + return -ENOMEM; + + hcd->rsrc_start = pdev->resource[0].start; + hcd->rsrc_len = pdev->resource[0].end - pdev->resource[0].start + 1; + + if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, hcd_name)) { + pr_debug("request_mem_region failed"); + ret = -EBUSY; + goto err1; + } + + hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len); + if (!hcd->regs) { + pr_debug("ioremap failed"); + ret = -ENOMEM; + goto err2; + } + + au13xx_start_ehc(); + + ehci = hcd_to_ehci(hcd); + ehci->caps = hcd->regs; + ehci->regs = hcd->regs + HC_LENGTH(readl(&ehci->caps->hc_capbase)); + printk("ehci->regs = %p\n", ehci->regs); + + /* cache this readonly data; minimize chip reads */ + ehci->hcs_params = readl(&ehci->caps->hcs_params); + + ret = usb_add_hcd(hcd, pdev->resource[1].start, + IRQF_DISABLED | IRQF_SHARED); + if (ret == 0) { + platform_set_drvdata(pdev, hcd); + return ret; + } + + au13xx_stop_ehc(); + iounmap(hcd->regs); +err2: + release_mem_region(hcd->rsrc_start, hcd->rsrc_len); +err1: + usb_put_hcd(hcd); + return ret; +} + +static int ehci_hcd_au13xx_drv_remove(struct platform_device *pdev) +{ + struct usb_hcd *hcd = platform_get_drvdata(pdev); + + usb_remove_hcd(hcd); + iounmap(hcd->regs); + release_mem_region(hcd->rsrc_start, hcd->rsrc_len); + usb_put_hcd(hcd); + au13xx_stop_ehc(); + platform_set_drvdata(pdev, NULL); + + return 0; +} + +static struct platform_driver ehci_hcd_au13xx_driver = { + .probe = ehci_hcd_au13xx_drv_probe, + .remove = ehci_hcd_au13xx_drv_remove, + .shutdown = usb_hcd_platform_shutdown, + .suspend = NULL, + .resume = NULL, + .driver = { + .name = "au13xx-ehci", + .owner = THIS_MODULE, + } +}; + +MODULE_ALIAS("platform:au13xx-ehci"); diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c index e551bb3..1e4ca7e 100644 --- a/drivers/usb/host/ehci-hcd.c +++ b/drivers/usb/host/ehci-hcd.c @@ -1016,6 +1016,11 @@ MODULE_LICENSE ("GPL"); #define PLATFORM_DRIVER ehci_hcd_au1xxx_driver #endif +#ifdef CONFIG_SOC_AU13XX +#include "ehci-au13xx.c" +#define PLATFORM_DRIVER ehci_hcd_au13xx_driver +#endif + #ifdef CONFIG_PPC_PS3 #include "ehci-ps3.c" #define PS3_SYSTEM_BUS_DRIVER ps3_ehci_driver -- 1.5.4.3 From khickey@rmicorp.com Fri Mar 6 16:22:45 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 06 Mar 2009 16:22:49 +0000 (GMT) Received: from mx1.rmicorp.com ([63.111.213.197]:35445 "EHLO mx1.rmicorp.com") by ftp.linux-mips.org with ESMTP id S21366487AbZCFQUV (ORCPT ); Fri, 6 Mar 2009 16:20:21 +0000 Received: from sark.razamicroelectronics.com ([10.8.0.254]) by mx1.rmicorp.com with Microsoft SMTPSVC(6.0.3790.3959); Fri, 6 Mar 2009 08:20:09 -0800 Received: from localhost.localdomain (unknown [10.8.0.23]) by sark.razamicroelectronics.com (Postfix) with ESMTP id D573CEE76AA; Fri, 6 Mar 2009 09:42:10 -0600 (CST) From: Kevin Hickey To: ralf@linux-mips.org, linux-mips@linux-mips.org Cc: Kevin Hickey Subject: [PATCH 05/10] Alchemy: Au1300/DB1300 MMC support Date: Fri, 6 Mar 2009 10:20:04 -0600 Message-Id: <394c116b9fa5bd1865ac21d11185f09e07bd2ab5.1236354153.git.khickey@rmicorp.com> X-Mailer: git-send-email 1.5.4.3 In-Reply-To: <0946334bbaf9883076889fe060a362b72d31e6f4.1236354153.git.khickey@rmicorp.com> References: <> <1236356409-32357-1-git-send-email-khickey@rmicorp.com> <788248524efc28ba2608ed79bfb7080ee476b12d.1236354153.git.khickey@rmicorp.com> <0b447f7e26be90a9179bdf89ca2cfd1f34c5d16e.1236354153.git.khickey@rmicorp.com> <7afc5c84989c4bc0f94181397369f284f2bb6924.1236354153.git.khickey@rmicorp.com> <0946334bbaf9883076889fe060a362b72d31e6f4.1236354153.git.khickey@rmicorp.com> In-Reply-To: <788248524efc28ba2608ed79bfb7080ee476b12d.1236354153.git.khickey@rmicorp.com> References: <788248524efc28ba2608ed79bfb7080ee476b12d.1236354153.git.khickey@rmicorp.com> X-OriginalArrivalTime: 06 Mar 2009 16:20:09.0903 (UTC) FILETIME=[6B864BF0:01C99E77] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22023 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: khickey@rmicorp.com Precedence: bulk X-list: linux-mips Supports the MMC/SD controller on Au1300 and the single slot on the DB1300 board. Signed-off-by: Kevin Hickey --- arch/mips/alchemy/devboards/db1300/mmc.c | 154 ++++++++++++++++++++++++++++++ drivers/mmc/host/Kconfig | 2 +- drivers/mmc/host/au1xmmc.c | 18 ++-- 3 files changed, 164 insertions(+), 10 deletions(-) create mode 100644 arch/mips/alchemy/devboards/db1300/mmc.c diff --git a/arch/mips/alchemy/devboards/db1300/mmc.c b/arch/mips/alchemy/devboards/db1300/mmc.c new file mode 100644 index 0000000..821658c --- /dev/null +++ b/arch/mips/alchemy/devboards/db1300/mmc.c @@ -0,0 +1,154 @@ +/* + * Copyright 2003-2008 RMI Corporation. All rights reserved. + * Author: Kevin Hickey + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED BY RMI Corporation 'AS IS' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL RMI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include +#include +#include +#include +#include + +static volatile struct bcsr_regs *const bcsr = + (struct bcsr_regs *)(DB1300_BCSR_REGS_PHYS_ADDR + KSEG1_OFFSET); + +static int mmc_activity; +static u64 au1xxx_mmc_dmamask = DMA_32BIT_MASK; + + +static void db1300_mmcled_set(struct led_classdev *led, + enum led_brightness brightness) +{ + if (brightness != LED_OFF) { + if (++mmc_activity == 1) + bcsr->disk_leds &= ~(1 << 8); + } else { + if (--mmc_activity == 0) + bcsr->disk_leds |= (1 << 8); + } +} + +static struct led_classdev db1300mmc_led = { + .brightness_set = db1300_mmcled_set, +}; + + +static int db1300mmc1_card_readonly(void *mmc_host) +{ + return (bcsr->status & BCSR_STATUS_SD1_WP) ? 1 : 0; +} + +static int db1300mmc1_card_inserted(void *mmc_host) +{ + int retval; + retval = (bcsr->sig_status & BCSR_INT_SD1_INSERT) ? 1 : 0; + return retval; +} + +struct au1xmmc_platform_data au1xmmc_platdata[2] = { + [0] = { + .set_power = NULL, + .card_inserted = NULL, + .card_readonly = NULL, + .cd_setup = NULL, /* use poll-timer in driver */ + .led = &db1300mmc_led, + }, + [1] = { + .set_power = NULL, + .card_inserted = db1300mmc1_card_inserted, + .card_readonly = db1300mmc1_card_readonly, + .cd_setup = NULL, /* use poll-timer in driver */ + .led = &db1300mmc_led, + }, +}; + +static struct resource au13xx_mmc0_resources[] = { + [0] = { + .start = SD0_PHYS_ADDR, + .end = SD0_PHYS_ADDR + 0x7ffff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AU1300_IRQ_SD0 + GPINT_LINUX_IRQ_OFFSET, + .end = AU1300_IRQ_SD0 + GPINT_LINUX_IRQ_OFFSET, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = DSCR_CMD0_SDMS_TX0, + .end = DSCR_CMD0_SDMS_TX0, + .flags = IORESOURCE_DMA, + }, + [3] = { + .start = DSCR_CMD0_SDMS_RX0, + .end = DSCR_CMD0_SDMS_RX0, + .flags = IORESOURCE_DMA, + } +}; + +struct platform_device au13xx_mmc0_device = { + .name = "au1xxx-mmc", + .id = 0, + .dev = { + .dma_mask = &au1xxx_mmc_dmamask, + .coherent_dma_mask = DMA_32BIT_MASK, + .platform_data = &au1xmmc_platdata[0], + }, + .num_resources = ARRAY_SIZE(au13xx_mmc0_resources), + .resource = au13xx_mmc0_resources, +}; + +static struct resource au13xx_mmc1_resources[] = { + [0] = { + .start = SD1_PHYS_ADDR, + .end = SD1_PHYS_ADDR + 0x7ffff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AU1300_IRQ_SD1 + GPINT_LINUX_IRQ_OFFSET, + .end = AU1300_IRQ_SD1 + GPINT_LINUX_IRQ_OFFSET, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = DSCR_CMD0_SDMS_TX1, + .end = DSCR_CMD0_SDMS_TX1, + .flags = IORESOURCE_DMA, + }, + [3] = { + .start = DSCR_CMD0_SDMS_RX1, + .end = DSCR_CMD0_SDMS_RX1, + .flags = IORESOURCE_DMA, + } +}; + +struct platform_device au13xx_mmc1_device = { + .name = "au1xxx-mmc", + .id = 1, + .dev = { + .dma_mask = &au1xxx_mmc_dmamask, + .coherent_dma_mask = DMA_32BIT_MASK, + .platform_data = &au1xmmc_platdata[1], + }, + .num_resources = ARRAY_SIZE(au13xx_mmc1_resources), + .resource = au13xx_mmc1_resources, +}; diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig index 99d4b28..a37bfee 100644 --- a/drivers/mmc/host/Kconfig +++ b/drivers/mmc/host/Kconfig @@ -99,7 +99,7 @@ config MMC_WBSD config MMC_AU1X tristate "Alchemy AU1XX0 MMC Card Interface support" - depends on SOC_AU1200 + depends on (SOC_AU1200 || SOC_AU13XX) help This selects the AMD Alchemy(R) Multimedia card interface. If you have a Alchemy platform with a MMC slot, say Y or M here. diff --git a/drivers/mmc/host/au1xmmc.c b/drivers/mmc/host/au1xmmc.c index d3f5561..a3b8ac7 100644 --- a/drivers/mmc/host/au1xmmc.c +++ b/drivers/mmc/host/au1xmmc.c @@ -353,7 +353,7 @@ static void au1xmmc_data_complete(struct au1xmmc_host *host, u32 status) if (!data->error) { if (host->flags & HOST_F_DMA) { -#ifdef CONFIG_SOC_AU1200 /* DBDMA */ +#if defined(CONFIG_SOC_AU1200) || defined(CONFIG_SOC_AU13XX) /* DBDMA */ u32 chan = DMA_CHANNEL(host); chan_tab_t *c = *((chan_tab_t **)chan); @@ -570,7 +570,7 @@ static void au1xmmc_cmd_complete(struct au1xmmc_host *host, u32 status) host->status = HOST_S_DATA; if (host->flags & HOST_F_DMA) { -#ifdef CONFIG_SOC_AU1200 /* DBDMA */ +#if defined(CONFIG_SOC_AU1200) || defined(CONFIG_SOC_AU13XX) /* DBDMA */ u32 channel = DMA_CHANNEL(host); /* Start the DMA as soon as the buffer gets something in it */ @@ -633,7 +633,7 @@ static int au1xmmc_prepare_data(struct au1xmmc_host *host, au_writel(data->blksz - 1, HOST_BLKSIZE(host)); if (host->flags & HOST_F_DMA) { -#ifdef CONFIG_SOC_AU1200 /* DBDMA */ +#if defined(CONFIG_SOC_AU1200) || defined(CONFIG_SOC_AU13XX) /* DBDMA */ int i; u32 channel = DMA_CHANNEL(host); @@ -837,7 +837,7 @@ static irqreturn_t au1xmmc_irq(int irq, void *dev_id) return IRQ_HANDLED; } -#ifdef CONFIG_SOC_AU1200 +#if defined(CONFIG_SOC_AU1200) || defined(CONFIG_SOC_AU13XX) /* 8bit memory DMA device */ static dbdev_tab_t au1xmmc_mem_dbdev = { .dev_id = DSCR_CMD0_ALWAYS, @@ -1023,7 +1023,7 @@ static int __devinit au1xmmc_probe(struct platform_device *pdev) tasklet_init(&host->finish_task, au1xmmc_tasklet_finish, (unsigned long)host); -#ifdef CONFIG_SOC_AU1200 +#if defined(CONFIG_SOC_AU1200) || defined(CONFIG_SOC_AU13XX) ret = au1xmmc_dbdma_init(host); if (ret) printk(KERN_INFO DRIVER_NAME ": DBDMA init failed; using PIO\n"); @@ -1068,7 +1068,7 @@ out5: au_writel(0, HOST_CONFIG2(host)); au_sync(); -#ifdef CONFIG_SOC_AU1200 +#if defined(CONFIG_SOC_AU1200) || defined(CONFIG_SOC_AU13XX) au1xmmc_dbdma_shutdown(host); #endif @@ -1115,7 +1115,7 @@ static int __devexit au1xmmc_remove(struct platform_device *pdev) tasklet_kill(&host->data_task); tasklet_kill(&host->finish_task); -#ifdef CONFIG_SOC_AU1200 +#if defined(CONFIG_SOC_AU1200) || defined(CONFIG_SOC_AU13XX) au1xmmc_dbdma_shutdown(host); #endif au1xmmc_set_power(host, 0); @@ -1176,7 +1176,7 @@ static struct platform_driver au1xmmc_driver = { static int __init au1xmmc_init(void) { -#ifdef CONFIG_SOC_AU1200 +#if defined(CONFIG_SOC_AU1200) || defined(CONFIG_SOC_AU13XX) /* DSCR_CMD0_ALWAYS has a stride of 32 bits, we need a stride * of 8 bits. And since devices are shared, we need to create * our own to avoid freaking out other devices. @@ -1190,7 +1190,7 @@ static int __init au1xmmc_init(void) static void __exit au1xmmc_exit(void) { -#ifdef CONFIG_SOC_AU1200 +#if defined(CONFIG_SOC_AU1200) || defined(CONFIG_SOC_AU13XX) if (memid) au1xxx_ddma_del_device(memid); #endif -- 1.5.4.3 From khickey@rmicorp.com Fri Mar 6 16:23:07 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 06 Mar 2009 16:23:10 +0000 (GMT) Received: from mx1.rmicorp.com ([63.111.213.197]:35445 "EHLO mx1.rmicorp.com") by ftp.linux-mips.org with ESMTP id S21366489AbZCFQUW (ORCPT ); Fri, 6 Mar 2009 16:20:22 +0000 Received: from sark.razamicroelectronics.com ([10.8.0.254]) by mx1.rmicorp.com with Microsoft SMTPSVC(6.0.3790.3959); Fri, 6 Mar 2009 08:20:10 -0800 Received: from localhost.localdomain (unknown [10.8.0.23]) by sark.razamicroelectronics.com (Postfix) with ESMTP id 18D99EE76AE; Fri, 6 Mar 2009 09:42:11 -0600 (CST) From: Kevin Hickey To: ralf@linux-mips.org, linux-mips@linux-mips.org Cc: Kevin Hickey Subject: [PATCH 09/10] Alchemy: Au1300: Add LCD framebuffer support Date: Fri, 6 Mar 2009 10:20:08 -0600 Message-Id: <02861156af87464c26e9cb564bef047fd83e054f.1236354153.git.khickey@rmicorp.com> X-Mailer: git-send-email 1.5.4.3 In-Reply-To: References: <> <1236356409-32357-1-git-send-email-khickey@rmicorp.com> <788248524efc28ba2608ed79bfb7080ee476b12d.1236354153.git.khickey@rmicorp.com> <0b447f7e26be90a9179bdf89ca2cfd1f34c5d16e.1236354153.git.khickey@rmicorp.com> <7afc5c84989c4bc0f94181397369f284f2bb6924.1236354153.git.khickey@rmicorp.com> <0946334bbaf9883076889fe060a362b72d31e6f4.1236354153.git.khickey@rmicorp.com> <394c116b9fa5bd1865ac21d11185f09e07bd2ab5.1236354153.git.khickey@rmicorp.com> <7e632686ab9b29a94eefeb2e5dca8b091a956b95.1236354153.git.khickey@rmicorp.com> In-Reply-To: <788248524efc28ba2608ed79bfb7080ee476b12d.1236354153.git.khickey@rmicorp.com> References: <788248524efc28ba2608ed79bfb7080ee476b12d.1236354153.git.khickey@rmicorp.com> X-OriginalArrivalTime: 06 Mar 2009 16:20:10.0247 (UTC) FILETIME=[6BBAC970:01C99E77] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22024 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: khickey@rmicorp.com Precedence: bulk X-list: linux-mips Signed-off-by: Kevin Hickey --- drivers/video/Kconfig | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index fb19803..9f571df 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -1713,7 +1713,7 @@ config FB_AU1100 config FB_AU1200 bool "Au1200 LCD Driver" - depends on (FB = y) && MIPS && SOC_AU1200 + depends on (FB = y) && MIPS && (SOC_AU1200 || SOC_AU13XX) select FB_CFB_FILLRECT select FB_CFB_COPYAREA select FB_CFB_IMAGEBLIT -- 1.5.4.3 From khickey@rmicorp.com Fri Mar 6 16:23:28 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 06 Mar 2009 16:23:32 +0000 (GMT) Received: from mx1.rmicorp.com ([63.111.213.197]:35445 "EHLO mx1.rmicorp.com") by ftp.linux-mips.org with ESMTP id S20808191AbZCFQUX (ORCPT ); Fri, 6 Mar 2009 16:20:23 +0000 Received: from sark.razamicroelectronics.com ([10.8.0.254]) by mx1.rmicorp.com with Microsoft SMTPSVC(6.0.3790.3959); Fri, 6 Mar 2009 08:20:10 -0800 Received: from localhost.localdomain (unknown [10.8.0.23]) by sark.razamicroelectronics.com (Postfix) with ESMTP id 1B77AEE76AF; Fri, 6 Mar 2009 09:42:11 -0600 (CST) From: Kevin Hickey To: ralf@linux-mips.org, linux-mips@linux-mips.org Cc: Kevin Hickey Subject: [PATCH 10/10] Alchemy: DB1300 defconfig Date: Fri, 6 Mar 2009 10:20:09 -0600 Message-Id: <3c6723e0be27cc089df85c3cf5d6cf280970ec9a.1236354153.git.khickey@rmicorp.com> X-Mailer: git-send-email 1.5.4.3 In-Reply-To: <02861156af87464c26e9cb564bef047fd83e054f.1236354153.git.khickey@rmicorp.com> References: <> <1236356409-32357-1-git-send-email-khickey@rmicorp.com> <788248524efc28ba2608ed79bfb7080ee476b12d.1236354153.git.khickey@rmicorp.com> <0b447f7e26be90a9179bdf89ca2cfd1f34c5d16e.1236354153.git.khickey@rmicorp.com> <7afc5c84989c4bc0f94181397369f284f2bb6924.1236354153.git.khickey@rmicorp.com> <0946334bbaf9883076889fe060a362b72d31e6f4.1236354153.git.khickey@rmicorp.com> <394c116b9fa5bd1865ac21d11185f09e07bd2ab5.1236354153.git.khickey@rmicorp.com> <7e632686ab9b29a94eefeb2e5dca8b091a956b95.1236354153.git.khickey@rmicorp.com> <02861156af87464c26e9cb564bef047fd83e054f.1236354153.git.khickey@rmicorp.com> In-Reply-To: <788248524efc28ba2608ed79bfb7080ee476b12d.1236354153.git.khickey@rmicorp.com> References: <788248524efc28ba2608ed79bfb7080ee476b12d.1236354153.git.khickey@rmicorp.com> X-OriginalArrivalTime: 06 Mar 2009 16:20:10.0262 (UTC) FILETIME=[6BBD1360:01C99E77] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22025 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: khickey@rmicorp.com Precedence: bulk X-list: linux-mips This configuration enables and compiles in all currently supported features. Anything not included in this configuration is either untested, unsupported or known broken. Signed-off-by: Kevin Hickey --- arch/mips/configs/db1300_defconfig | 1216 ++++++++++++++++++++++++++++++++++++ 1 files changed, 1216 insertions(+), 0 deletions(-) create mode 100644 arch/mips/configs/db1300_defconfig diff --git a/arch/mips/configs/db1300_defconfig b/arch/mips/configs/db1300_defconfig new file mode 100644 index 0000000..1861212 --- /dev/null +++ b/arch/mips/configs/db1300_defconfig @@ -0,0 +1,1216 @@ +# +# Automatically generated make config: don't edit +# Linux kernel version: 2.6.29-rc7 +# Thu Mar 5 16:58:03 2009 +# +CONFIG_MIPS=y + +# +# Machine selection +# +CONFIG_MACH_ALCHEMY=y +# CONFIG_BASLER_EXCITE is not set +# CONFIG_BCM47XX is not set +# CONFIG_MIPS_COBALT is not set +# CONFIG_MACH_DECSTATION is not set +# CONFIG_MACH_JAZZ is not set +# CONFIG_LASAT is not set +# CONFIG_LEMOTE_FULONG is not set +# CONFIG_MIPS_MALTA is not set +# CONFIG_MIPS_SIM is not set +# CONFIG_MACH_EMMA is not set +# CONFIG_MACH_VR41XX is not set +# CONFIG_NXP_STB220 is not set +# CONFIG_NXP_STB225 is not set +# CONFIG_PNX8550_JBS is not set +# CONFIG_PNX8550_STB810 is not set +# CONFIG_PMC_MSP is not set +# CONFIG_PMC_YOSEMITE is not set +# CONFIG_SGI_IP22 is not set +# CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP28 is not set +# CONFIG_SGI_IP32 is not set +# CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CARMEL is not set +# CONFIG_SIBYTE_CRHONE is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_BIGSUR is not set +# CONFIG_SNI_RM is not set +# CONFIG_MACH_TX39XX is not set +# CONFIG_MACH_TX49XX is not set +# CONFIG_MIKROTIK_RB532 is not set +# CONFIG_WR_PPMC is not set +# CONFIG_CAVIUM_OCTEON_SIMULATOR is not set +# CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD is not set +# CONFIG_MIPS_MTX1 is not set +# CONFIG_MIPS_BOSPORUS is not set +# CONFIG_MIPS_DB1000 is not set +# CONFIG_MIPS_DB1100 is not set +# CONFIG_MIPS_DB1200 is not set +# CONFIG_MIPS_DB1500 is not set +# CONFIG_MIPS_DB1550 is not set +CONFIG_MIPS_DB1300=y +# CONFIG_MIPS_MIRAGE is not set +# CONFIG_MIPS_PB1000 is not set +# CONFIG_MIPS_PB1100 is not set +# CONFIG_MIPS_PB1200 is not set +# CONFIG_MIPS_PB1500 is not set +# CONFIG_MIPS_PB1550 is not set +# CONFIG_MIPS_XXS1500 is not set +CONFIG_SOC_AU13XX=y +CONFIG_SOC_AU1X00=y +CONFIG_AU_GPIO_INT_CNTLR=y +CONFIG_RWSEM_GENERIC_SPINLOCK=y +# CONFIG_ARCH_HAS_ILOG2_U32 is not set +# CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_ARCH_SUPPORTS_OPROFILE=y +CONFIG_GENERIC_FIND_NEXT_BIT=y +CONFIG_GENERIC_HWEIGHT=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CMOS_UPDATE=y +CONFIG_SCHED_OMIT_FRAME_POINTER=y +CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ=y +CONFIG_CEVT_R4K_LIB=y +CONFIG_CSRC_R4K_LIB=y +CONFIG_DMA_COHERENT=y +CONFIG_EARLY_PRINTK=y +CONFIG_SYS_HAS_EARLY_PRINTK=y +# CONFIG_HOTPLUG_CPU is not set +# CONFIG_NO_IOPORT is not set +# CONFIG_CPU_BIG_ENDIAN is not set +CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y +CONFIG_IRQ_CPU=y +CONFIG_MIPS_L1_CACHE_SHIFT=5 + +# +# CPU selection +# +# CONFIG_CPU_LOONGSON2 is not set +CONFIG_CPU_MIPS32_R1=y +# CONFIG_CPU_MIPS32_R2 is not set +# CONFIG_CPU_MIPS64_R1 is not set +# CONFIG_CPU_MIPS64_R2 is not set +# CONFIG_CPU_R3000 is not set +# CONFIG_CPU_TX39XX is not set +# CONFIG_CPU_VR41XX is not set +# CONFIG_CPU_R4300 is not set +# CONFIG_CPU_R4X00 is not set +# CONFIG_CPU_TX49XX is not set +# CONFIG_CPU_R5000 is not set +# CONFIG_CPU_R5432 is not set +# CONFIG_CPU_R5500 is not set +# CONFIG_CPU_R6000 is not set +# CONFIG_CPU_NEVADA is not set +# CONFIG_CPU_R8000 is not set +# CONFIG_CPU_R10000 is not set +# CONFIG_CPU_RM7000 is not set +# CONFIG_CPU_RM9000 is not set +# CONFIG_CPU_SB1 is not set +# CONFIG_CPU_CAVIUM_OCTEON is not set +CONFIG_SYS_HAS_CPU_MIPS32_R1=y +CONFIG_CPU_MIPS32=y +CONFIG_CPU_MIPSR1=y +CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y +CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y +CONFIG_HARDWARE_WATCHPOINTS=y + +# +# Kernel type +# +CONFIG_32BIT=y +# CONFIG_64BIT is not set +CONFIG_PAGE_SIZE_4KB=y +# CONFIG_PAGE_SIZE_8KB is not set +# CONFIG_PAGE_SIZE_16KB is not set +# CONFIG_PAGE_SIZE_64KB is not set +CONFIG_CPU_HAS_PREFETCH=y +CONFIG_MIPS_MT_DISABLED=y +# CONFIG_MIPS_MT_SMP is not set +# CONFIG_MIPS_MT_SMTC is not set +CONFIG_64BIT_PHYS_ADDR=y +CONFIG_CPU_HAS_LLSC=y +CONFIG_CPU_HAS_SYNC=y +CONFIG_GENERIC_HARDIRQS=y +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_CPU_SUPPORTS_HIGHMEM=y +CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_ARCH_POPULATES_NODE_MAP=y +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_FLATMEM_MANUAL=y +# CONFIG_DISCONTIGMEM_MANUAL is not set +# CONFIG_SPARSEMEM_MANUAL is not set +CONFIG_FLATMEM=y +CONFIG_FLAT_NODE_MEM_MAP=y +CONFIG_PAGEFLAGS_EXTENDED=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +# CONFIG_PHYS_ADDR_T_64BIT is not set +CONFIG_ZONE_DMA_FLAG=0 +CONFIG_VIRT_TO_BUS=y +CONFIG_UNEVICTABLE_LRU=y +# CONFIG_NO_HZ is not set +# CONFIG_HIGH_RES_TIMERS is not set +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y +# CONFIG_HZ_48 is not set +# CONFIG_HZ_100 is not set +# CONFIG_HZ_128 is not set +# CONFIG_HZ_250 is not set +# CONFIG_HZ_256 is not set +CONFIG_HZ_1000=y +# CONFIG_HZ_1024 is not set +CONFIG_SYS_SUPPORTS_ARBIT_HZ=y +CONFIG_HZ=1000 +CONFIG_PREEMPT_NONE=y +# CONFIG_PREEMPT_VOLUNTARY is not set +# CONFIG_PREEMPT is not set +# CONFIG_KEXEC is not set +CONFIG_SECCOMP=y +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" + +# +# General setup +# +CONFIG_EXPERIMENTAL=y +CONFIG_BROKEN_ON_SMP=y +CONFIG_INIT_ENV_ARG_LIMIT=32 +CONFIG_LOCALVERSION="" +CONFIG_LOCALVERSION_AUTO=y +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +# CONFIG_POSIX_MQUEUE is not set +# CONFIG_BSD_PROCESS_ACCT is not set +# CONFIG_TASKSTATS is not set +# CONFIG_AUDIT is not set + +# +# RCU Subsystem +# +CONFIG_CLASSIC_RCU=y +# CONFIG_TREE_RCU is not set +# CONFIG_PREEMPT_RCU is not set +# CONFIG_TREE_RCU_TRACE is not set +# CONFIG_PREEMPT_RCU_TRACE is not set +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_GROUP_SCHED is not set +# CONFIG_CGROUPS is not set +# CONFIG_SYSFS_DEPRECATED_V2 is not set +# CONFIG_RELAY is not set +# CONFIG_NAMESPACES is not set +# CONFIG_BLK_DEV_INITRD is not set +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_SYSCTL=y +CONFIG_EMBEDDED=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_KALLSYMS=y +# CONFIG_KALLSYMS_ALL is not set +# CONFIG_KALLSYMS_EXTRA_PASS is not set +CONFIG_HOTPLUG=y +CONFIG_PRINTK=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_PCSPKR_PLATFORM=y +CONFIG_COMPAT_BRK=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_ANON_INODES=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set +CONFIG_SLABINFO=y +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +CONFIG_MODVERSIONS=y +CONFIG_MODULE_SRCVERSION_ALL=y +CONFIG_BLOCK=y +# CONFIG_LBD is not set +# CONFIG_BLK_DEV_IO_TRACE is not set +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set + +# +# IO Schedulers +# +CONFIG_IOSCHED_NOOP=y +CONFIG_IOSCHED_AS=y +CONFIG_IOSCHED_DEADLINE=y +CONFIG_IOSCHED_CFQ=y +CONFIG_DEFAULT_AS=y +# CONFIG_DEFAULT_DEADLINE is not set +# CONFIG_DEFAULT_CFQ is not set +# CONFIG_DEFAULT_NOOP is not set +CONFIG_DEFAULT_IOSCHED="anticipatory" +# CONFIG_FREEZER is not set + +# +# Bus options (PCI, PCMCIA, EISA, ISA, TC) +# +# CONFIG_ARCH_SUPPORTS_MSI is not set +CONFIG_MMU=y +# CONFIG_PCCARD is not set + +# +# Executable file formats +# +CONFIG_BINFMT_ELF=y +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_HAVE_AOUT is not set +# CONFIG_BINFMT_MISC is not set +CONFIG_TRAD_SIGNALS=y + +# +# Power management options +# +CONFIG_ARCH_SUSPEND_POSSIBLE=y +# CONFIG_PM is not set +CONFIG_NET=y + +# +# Networking options +# +CONFIG_COMPAT_NET_DEV_OPS=y +CONFIG_PACKET=y +# CONFIG_PACKET_MMAP is not set +CONFIG_UNIX=y +CONFIG_XFRM=y +CONFIG_XFRM_USER=m +# CONFIG_XFRM_SUB_POLICY is not set +CONFIG_XFRM_MIGRATE=y +# CONFIG_XFRM_STATISTICS is not set +CONFIG_NET_KEY=y +CONFIG_NET_KEY_MIGRATE=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +# CONFIG_IP_ADVANCED_ROUTER is not set +CONFIG_IP_FIB_HASH=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +# CONFIG_IP_PNP_RARP is not set +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE is not set +# CONFIG_IP_MROUTE is not set +# CONFIG_ARPD is not set +# CONFIG_SYN_COOKIES is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +# CONFIG_INET_XFRM_TUNNEL is not set +# CONFIG_INET_TUNNEL is not set +CONFIG_INET_XFRM_MODE_TRANSPORT=y +CONFIG_INET_XFRM_MODE_TUNNEL=y +CONFIG_INET_XFRM_MODE_BEET=y +# CONFIG_INET_LRO is not set +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_TCP_CONG_ADVANCED is not set +CONFIG_TCP_CONG_CUBIC=y +CONFIG_DEFAULT_TCP_CONG="cubic" +CONFIG_TCP_MD5SIG=y +# CONFIG_IPV6 is not set +# CONFIG_NETWORK_SECMARK is not set +# CONFIG_NETFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_SCTP_HMAC_NONE is not set +# CONFIG_SCTP_HMAC_SHA1 is not set +# CONFIG_SCTP_HMAC_MD5 is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_BRIDGE is not set +# CONFIG_NET_DSA is not set +# CONFIG_VLAN_8021Q is not set +# CONFIG_DECNET is not set +# CONFIG_LLC2 is not set +# CONFIG_IPX is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_ECONET is not set +# CONFIG_WAN_ROUTER is not set +# CONFIG_NET_SCHED is not set +# CONFIG_DCB is not set + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set +# CONFIG_IRDA is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set +# CONFIG_PHONET is not set +# CONFIG_WIRELESS is not set +# CONFIG_WIMAX is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set + +# +# Device Drivers +# + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_STANDALONE=y +CONFIG_PREVENT_FIRMWARE_BUILD=y +CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_SYS_HYPERVISOR is not set +# CONFIG_CONNECTOR is not set +# CONFIG_MTD is not set +# CONFIG_PARPORT is not set +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_COW_COMMON is not set +CONFIG_BLK_DEV_LOOP=y +# CONFIG_BLK_DEV_CRYPTOLOOP is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_UB is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=4096 +# CONFIG_BLK_DEV_XIP is not set +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +# CONFIG_BLK_DEV_HD is not set +# CONFIG_MISC_DEVICES is not set +CONFIG_HAVE_IDE=y +CONFIG_IDE=y + +# +# Please see Documentation/ide/ide.txt for help/info on IDE drives +# +# CONFIG_BLK_DEV_IDE_SATA is not set +# CONFIG_IDE_GD is not set +# CONFIG_BLK_DEV_IDECD is not set +# CONFIG_BLK_DEV_IDETAPE is not set +# CONFIG_IDE_TASK_IOCTL is not set +# CONFIG_IDE_PROC_FS is not set + +# +# IDE chipset support/bugfixes +# +# CONFIG_IDE_GENERIC is not set +# CONFIG_BLK_DEV_PLATFORM is not set +# CONFIG_BLK_DEV_IDEDMA is not set + +# +# SCSI device support +# +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +CONFIG_SCSI_TGT=m +# CONFIG_SCSI_NETLINK is not set +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +# CONFIG_CHR_DEV_OSST is not set +CONFIG_BLK_DEV_SR=y +# CONFIG_BLK_DEV_SR_VENDOR is not set +CONFIG_CHR_DEV_SG=y +# CONFIG_CHR_DEV_SCH is not set + +# +# Some SCSI devices (e.g. CD jukebox) support multiple LUNs +# +CONFIG_SCSI_MULTI_LUN=y +# CONFIG_SCSI_CONSTANTS is not set +# CONFIG_SCSI_LOGGING is not set +CONFIG_SCSI_SCAN_ASYNC=y +CONFIG_SCSI_WAIT_SCAN=m + +# +# SCSI Transports +# +# CONFIG_SCSI_SPI_ATTRS is not set +# CONFIG_SCSI_FC_ATTRS is not set +# CONFIG_SCSI_ISCSI_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +CONFIG_SCSI_LOWLEVEL=y +# CONFIG_ISCSI_TCP is not set +# CONFIG_LIBFC is not set +# CONFIG_SCSI_DEBUG is not set +# CONFIG_SCSI_DH is not set +# CONFIG_ATA is not set +# CONFIG_MD is not set +CONFIG_NETDEVICES=y +# CONFIG_DUMMY is not set +# CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set +# CONFIG_EQUALIZER is not set +# CONFIG_TUN is not set +# CONFIG_VETH is not set +# CONFIG_PHYLIB is not set +CONFIG_NET_ETHERNET=y +CONFIG_MII=y +# CONFIG_AX88796 is not set +# CONFIG_MIPS_AU1X00_ENET is not set +# CONFIG_SMC91X is not set +CONFIG_SMSC9210=y +# CONFIG_DM9000 is not set +# CONFIG_IBM_NEW_EMAC_ZMII is not set +# CONFIG_IBM_NEW_EMAC_RGMII is not set +# CONFIG_IBM_NEW_EMAC_TAH is not set +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set +# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set +# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set +# CONFIG_B44 is not set +# CONFIG_NETDEV_1000 is not set +# CONFIG_NETDEV_10000 is not set + +# +# Wireless LAN +# +# CONFIG_WLAN_PRE80211 is not set +# CONFIG_WLAN_80211 is not set +# CONFIG_IWLWIFI_LEDS is not set + +# +# Enable WiMAX (Networking options) to see the WiMAX drivers +# + +# +# USB Network Adapters +# +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +# CONFIG_USB_USBNET is not set +# CONFIG_WAN is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +# CONFIG_NETCONSOLE is not set +# CONFIG_NETPOLL is not set +# CONFIG_NET_POLL_CONTROLLER is not set +# CONFIG_ISDN is not set +# CONFIG_PHONE is not set + +# +# Input device support +# +CONFIG_INPUT=y +# CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +CONFIG_INPUT_MOUSEDEV_PSAUX=y +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +CONFIG_KEYBOARD_ATKBD=y +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_LKKBD is not set +# CONFIG_KEYBOARD_XTKBD is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +CONFIG_INPUT_MOUSE=y +CONFIG_MOUSE_PS2=y +CONFIG_MOUSE_PS2_ALPS=y +CONFIG_MOUSE_PS2_LOGIPS2PP=y +CONFIG_MOUSE_PS2_SYNAPTICS=y +CONFIG_MOUSE_PS2_TRACKPOINT=y +# CONFIG_MOUSE_PS2_ELANTECH is not set +# CONFIG_MOUSE_PS2_TOUCHKIT is not set +# CONFIG_MOUSE_SERIAL is not set +# CONFIG_MOUSE_APPLETOUCH is not set +# CONFIG_MOUSE_BCM5974 is not set +# CONFIG_MOUSE_VSXXXAA is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +# CONFIG_SERIO_I8042 is not set +CONFIG_SERIO_SERPORT=y +CONFIG_SERIO_LIBPS2=y +CONFIG_SERIO_RAW=y +# CONFIG_GAMEPORT is not set + +# +# Character devices +# +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_HW_CONSOLE=y +CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_DEVKMEM=y +# CONFIG_SERIAL_NONSTANDARD is not set + +# +# Serial drivers +# +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_NR_UARTS=4 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +# CONFIG_SERIAL_8250_EXTENDED is not set +CONFIG_SERIAL_8250_AU1X00=y + +# +# Non-8250 serial port support +# +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_UNIX98_PTYS=y +# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set +CONFIG_LEGACY_PTYS=y +CONFIG_LEGACY_PTY_COUNT=256 +# CONFIG_IPMI_HANDLER is not set +# CONFIG_HW_RANDOM is not set +# CONFIG_R3964 is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_TCG_TPM is not set +# CONFIG_I2C is not set +# CONFIG_SPI is not set +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +# CONFIG_THERMAL_HWMON is not set +# CONFIG_WATCHDOG is not set +CONFIG_SSB_POSSIBLE=y + +# +# Sonics Silicon Backplane +# +# CONFIG_SSB is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_MFD_TMIO is not set +# CONFIG_REGULATOR is not set + +# +# Multimedia devices +# + +# +# Multimedia core support +# +# CONFIG_VIDEO_DEV is not set +# CONFIG_DVB_CORE is not set +# CONFIG_VIDEO_MEDIA is not set + +# +# Multimedia drivers +# +# CONFIG_DAB is not set + +# +# Graphics support +# +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set +CONFIG_FB=y +# CONFIG_FIRMWARE_EDID is not set +# CONFIG_FB_DDC is not set +# CONFIG_FB_BOOT_VESA_SUPPORT is not set +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y +# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set +# CONFIG_FB_SYS_FILLRECT is not set +# CONFIG_FB_SYS_COPYAREA is not set +# CONFIG_FB_SYS_IMAGEBLIT is not set +# CONFIG_FB_FOREIGN_ENDIAN is not set +# CONFIG_FB_SYS_FOPS is not set +# CONFIG_FB_SVGALIB is not set +# CONFIG_FB_MACMODES is not set +# CONFIG_FB_BACKLIGHT is not set +# CONFIG_FB_MODE_HELPERS is not set +# CONFIG_FB_TILEBLITTING is not set + +# +# Frame buffer hardware drivers +# +# CONFIG_FB_S1D13XXX is not set +CONFIG_FB_AU1200=y +# CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_METRONOME is not set +# CONFIG_FB_MB862XX is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set + +# +# Console display driver support +# +CONFIG_VGA_CONSOLE=y +# CONFIG_VGACON_SOFT_SCROLLBACK is not set +CONFIG_DUMMY_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE=y +# CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY is not set +# CONFIG_FRAMEBUFFER_CONSOLE_ROTATION is not set +# CONFIG_FONTS is not set +CONFIG_FONT_8x8=y +CONFIG_FONT_8x16=y +CONFIG_LOGO=y +CONFIG_LOGO_LINUX_MONO=y +CONFIG_LOGO_LINUX_VGA16=y +CONFIG_LOGO_LINUX_CLUT224=y +# CONFIG_SOUND is not set +CONFIG_HID_SUPPORT=y +CONFIG_HID=y +# CONFIG_HID_DEBUG is not set +# CONFIG_HIDRAW is not set + +# +# USB Input Devices +# +CONFIG_USB_HID=y +# CONFIG_HID_PID is not set +# CONFIG_USB_HIDDEV is not set + +# +# Special HID drivers +# +CONFIG_HID_COMPAT=y +# CONFIG_HID_A4TECH is not set +# CONFIG_HID_APPLE is not set +# CONFIG_HID_BELKIN is not set +# CONFIG_HID_CHERRY is not set +# CONFIG_HID_CHICONY is not set +# CONFIG_HID_CYPRESS is not set +# CONFIG_HID_EZKEY is not set +# CONFIG_HID_GYRATION is not set +# CONFIG_HID_LOGITECH is not set +# CONFIG_HID_MICROSOFT is not set +# CONFIG_HID_MONTEREY is not set +# CONFIG_HID_NTRIG is not set +# CONFIG_HID_PANTHERLORD is not set +# CONFIG_HID_PETALYNX is not set +# CONFIG_HID_SAMSUNG is not set +# CONFIG_HID_SONY is not set +# CONFIG_HID_SUNPLUS is not set +# CONFIG_GREENASIA_FF is not set +# CONFIG_HID_TOPSEED is not set +# CONFIG_THRUSTMASTER_FF is not set +# CONFIG_ZEROPLUS_FF is not set +CONFIG_USB_SUPPORT=y +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB_ARCH_HAS_OHCI=y +CONFIG_USB_ARCH_HAS_EHCI=y +CONFIG_USB=y +# CONFIG_USB_DEBUG is not set +# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set + +# +# Miscellaneous USB options +# +CONFIG_USB_DEVICEFS=y +CONFIG_USB_DEVICE_CLASS=y +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_OTG is not set +# CONFIG_USB_OTG_WHITELIST is not set +# CONFIG_USB_OTG_BLACKLIST_HUB is not set +CONFIG_USB_MON=y +# CONFIG_USB_WUSB is not set +# CONFIG_USB_WUSB_CBAF is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_C67X00_HCD is not set +CONFIG_USB_EHCI_HCD=y +# CONFIG_USB_EHCI_ROOT_HUB_TT is not set +# CONFIG_USB_EHCI_TT_NEWSCHED is not set +# CONFIG_USB_OXU210HP_HCD is not set +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_OHCI_HCD is not set +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_HWA_HCD is not set + +# +# USB Device Class drivers +# +# CONFIG_USB_ACM is not set +# CONFIG_USB_PRINTER is not set +# CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed; +# + +# +# see USB_STORAGE Help for more information +# +CONFIG_USB_STORAGE=y +# CONFIG_USB_STORAGE_DEBUG is not set +# CONFIG_USB_STORAGE_DATAFAB is not set +# CONFIG_USB_STORAGE_FREECOM is not set +# CONFIG_USB_STORAGE_ISD200 is not set +# CONFIG_USB_STORAGE_USBAT is not set +# CONFIG_USB_STORAGE_SDDR09 is not set +# CONFIG_USB_STORAGE_SDDR55 is not set +# CONFIG_USB_STORAGE_JUMPSHOT is not set +# CONFIG_USB_STORAGE_ALAUDA is not set +# CONFIG_USB_STORAGE_ONETOUCH is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set +# CONFIG_USB_LIBUSUAL is not set + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set + +# +# USB port drivers +# +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_BERRY_CHARGE is not set +# CONFIG_USB_LED is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_PHIDGET is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_SISUSBVGA is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_TEST is not set +# CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_VST is not set +# CONFIG_USB_GADGET is not set + +# +# OTG and related infrastructure +# +CONFIG_MMC=y +# CONFIG_MMC_DEBUG is not set +# CONFIG_MMC_UNSAFE_RESUME is not set + +# +# MMC/SD/SDIO Card Drivers +# +CONFIG_MMC_BLOCK=y +CONFIG_MMC_BLOCK_BOUNCE=y +# CONFIG_SDIO_UART is not set +# CONFIG_MMC_TEST is not set + +# +# MMC/SD/SDIO Host Controller Drivers +# +# CONFIG_MMC_SDHCI is not set +CONFIG_MMC_AU1X=y +# CONFIG_MEMSTICK is not set +# CONFIG_NEW_LEDS is not set +# CONFIG_ACCESSIBILITY is not set +CONFIG_RTC_LIB=y +# CONFIG_RTC_CLASS is not set +# CONFIG_DMADEVICES is not set +# CONFIG_UIO is not set +# CONFIG_STAGING is not set + +# +# File systems +# +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +CONFIG_EXT2_FS_POSIX_ACL=y +# CONFIG_EXT2_FS_SECURITY is not set +# CONFIG_EXT2_FS_XIP is not set +CONFIG_EXT3_FS=y +CONFIG_EXT3_FS_XATTR=y +CONFIG_EXT3_FS_POSIX_ACL=y +CONFIG_EXT3_FS_SECURITY=y +# CONFIG_EXT4_FS is not set +CONFIG_JBD=y +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +CONFIG_JFS_FS=y +# CONFIG_JFS_POSIX_ACL is not set +# CONFIG_JFS_SECURITY is not set +# CONFIG_JFS_DEBUG is not set +# CONFIG_JFS_STATISTICS is not set +CONFIG_FS_POSIX_ACL=y +CONFIG_FILE_LOCKING=y +# CONFIG_XFS_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_BTRFS_FS is not set +CONFIG_DNOTIFY=y +CONFIG_INOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_QUOTA is not set +# CONFIG_AUTOFS_FS is not set +# CONFIG_AUTOFS4_FS is not set +# CONFIG_FUSE_FS is not set +CONFIG_GENERIC_ACL=y + +# +# CD-ROM/DVD Filesystems +# +CONFIG_ISO9660_FS=m +CONFIG_JOLIET=y +CONFIG_ZISOFS=y +CONFIG_UDF_FS=m +CONFIG_UDF_NLS=y + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_NTFS_FS is not set + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_KCORE=y +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +# CONFIG_HUGETLB_PAGE is not set +CONFIG_CONFIGFS_FS=m +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_ECRYPT_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +CONFIG_CRAMFS=m +# CONFIG_SQUASHFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_ROMFS_FS is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3=y +# CONFIG_NFS_V3_ACL is not set +# CONFIG_NFS_V4 is not set +CONFIG_ROOT_NFS=y +# CONFIG_NFSD is not set +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +# CONFIG_SUNRPC_REGISTER_V4 is not set +# CONFIG_RPCSEC_GSS_KRB5 is not set +# CONFIG_RPCSEC_GSS_SPKM3 is not set +CONFIG_SMB_FS=y +# CONFIG_SMB_NLS_DEFAULT is not set +# CONFIG_CIFS is not set +# CONFIG_NCP_FS is not set +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set + +# +# Partition Types +# +# CONFIG_PARTITION_ADVANCED is not set +CONFIG_MSDOS_PARTITION=y +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="iso8859-1" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=y +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +CONFIG_NLS_UTF8=y +# CONFIG_DLM is not set + +# +# Kernel hacking +# +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +# CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_WARN_DEPRECATED=y +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 +CONFIG_MAGIC_SYSRQ=y +# CONFIG_UNUSED_SYMBOLS is not set +# CONFIG_DEBUG_FS is not set +# CONFIG_HEADERS_CHECK is not set +CONFIG_DEBUG_KERNEL=y +# CONFIG_DEBUG_SHIRQ is not set +CONFIG_DETECT_SOFTLOCKUP=y +# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set +CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 +# CONFIG_SCHED_DEBUG is not set +# CONFIG_SCHEDSTATS is not set +# CONFIG_TIMER_STATS is not set +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_DEBUG_SLAB is not set +# CONFIG_DEBUG_RT_MUTEXES is not set +# CONFIG_RT_MUTEX_TESTER is not set +# CONFIG_DEBUG_SPINLOCK is not set +CONFIG_DEBUG_MUTEXES=y +# CONFIG_DEBUG_LOCK_ALLOC is not set +# CONFIG_PROVE_LOCKING is not set +# CONFIG_LOCK_STAT is not set +# CONFIG_DEBUG_SPINLOCK_SLEEP is not set +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_DEBUG_KOBJECT is not set +CONFIG_DEBUG_INFO=y +# CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_WRITECOUNT is not set +# CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_DEBUG_LIST is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_BOOT_PRINTK_DELAY is not set +# CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_CPU_STALL_DETECTOR is not set +# CONFIG_BACKTRACE_SELF_TEST is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +# CONFIG_FAULT_INJECTION is not set +# CONFIG_SYSCTL_SYSCALL_CHECK is not set + +# +# Tracers +# +# CONFIG_IRQSOFF_TRACER is not set +# CONFIG_SCHED_TRACER is not set +# CONFIG_CONTEXT_SWITCH_TRACER is not set +# CONFIG_BOOT_TRACER is not set +# CONFIG_TRACE_BRANCH_PROFILING is not set +# CONFIG_DYNAMIC_PRINTK_DEBUG is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +# CONFIG_KGDB is not set +CONFIG_CMDLINE="" +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_RUNTIME_DEBUG is not set + +# +# Security options +# +CONFIG_KEYS=y +CONFIG_KEYS_DEBUG_PROC_KEYS=y +# CONFIG_SECURITY is not set +# CONFIG_SECURITYFS is not set +# CONFIG_SECURITY_FILE_CAPABILITIES is not set +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +# CONFIG_CRYPTO_FIPS is not set +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_BLKCIPHER=m +CONFIG_CRYPTO_BLKCIPHER2=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_MANAGER=m +CONFIG_CRYPTO_MANAGER2=y +CONFIG_CRYPTO_GF128MUL=m +CONFIG_CRYPTO_NULL=m +# CONFIG_CRYPTO_CRYPTD is not set +# CONFIG_CRYPTO_AUTHENC is not set +# CONFIG_CRYPTO_TEST is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_SEQIV is not set + +# +# Block modes +# +CONFIG_CRYPTO_CBC=m +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +CONFIG_CRYPTO_ECB=m +CONFIG_CRYPTO_LRW=m +CONFIG_CRYPTO_PCBC=m +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# +CONFIG_CRYPTO_HMAC=m +CONFIG_CRYPTO_XCBC=m + +# +# Digest +# +CONFIG_CRYPTO_CRC32C=y +CONFIG_CRYPTO_MD4=m +CONFIG_CRYPTO_MD5=y +CONFIG_CRYPTO_MICHAEL_MIC=m +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +CONFIG_CRYPTO_SHA1=m +CONFIG_CRYPTO_SHA256=m +CONFIG_CRYPTO_SHA512=m +CONFIG_CRYPTO_TGR192=m +CONFIG_CRYPTO_WP512=m + +# +# Ciphers +# +CONFIG_CRYPTO_AES=m +CONFIG_CRYPTO_ANUBIS=m +CONFIG_CRYPTO_ARC4=m +CONFIG_CRYPTO_BLOWFISH=m +CONFIG_CRYPTO_CAMELLIA=m +CONFIG_CRYPTO_CAST5=m +CONFIG_CRYPTO_CAST6=m +CONFIG_CRYPTO_DES=m +CONFIG_CRYPTO_FCRYPT=m +CONFIG_CRYPTO_KHAZAD=m +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +CONFIG_CRYPTO_SERPENT=m +CONFIG_CRYPTO_TEA=m +CONFIG_CRYPTO_TWOFISH=m +CONFIG_CRYPTO_TWOFISH_COMMON=m + +# +# Compression +# +CONFIG_CRYPTO_DEFLATE=m +# CONFIG_CRYPTO_LZO is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set +CONFIG_CRYPTO_HW=y + +# +# Library routines +# +CONFIG_BITREVERSE=y +CONFIG_GENERIC_FIND_LAST_BIT=y +CONFIG_CRC_CCITT=y +# CONFIG_CRC16 is not set +# CONFIG_CRC_T10DIF is not set +CONFIG_CRC_ITU_T=m +CONFIG_CRC32=y +# CONFIG_CRC7 is not set +CONFIG_LIBCRC32C=y +CONFIG_ZLIB_INFLATE=m +CONFIG_ZLIB_DEFLATE=m +CONFIG_PLIST=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y -- 1.5.4.3 From khickey@rmicorp.com Fri Mar 6 16:23:50 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 06 Mar 2009 16:24:01 +0000 (GMT) Received: from mx1.rmicorp.com ([63.111.213.197]:35445 "EHLO mx1.rmicorp.com") by ftp.linux-mips.org with ESMTP id S21366492AbZCFQUZ (ORCPT ); Fri, 6 Mar 2009 16:20:25 +0000 Received: from sark.razamicroelectronics.com ([10.8.0.254]) by mx1.rmicorp.com with Microsoft SMTPSVC(6.0.3790.3959); Fri, 6 Mar 2009 08:20:09 -0800 Received: from localhost.localdomain (unknown [10.8.0.23]) by sark.razamicroelectronics.com (Postfix) with ESMTP id DA26FEE76AC; Fri, 6 Mar 2009 09:42:10 -0600 (CST) From: Kevin Hickey To: ralf@linux-mips.org, linux-mips@linux-mips.org Cc: Kevin Hickey Subject: [PATCH 07/10] Alchemy: SMSC 9210 Ethernet support Date: Fri, 6 Mar 2009 10:20:06 -0600 Message-Id: X-Mailer: git-send-email 1.5.4.3 In-Reply-To: <7e632686ab9b29a94eefeb2e5dca8b091a956b95.1236354153.git.khickey@rmicorp.com> References: <> <1236356409-32357-1-git-send-email-khickey@rmicorp.com> <788248524efc28ba2608ed79bfb7080ee476b12d.1236354153.git.khickey@rmicorp.com> <0b447f7e26be90a9179bdf89ca2cfd1f34c5d16e.1236354153.git.khickey@rmicorp.com> <7afc5c84989c4bc0f94181397369f284f2bb6924.1236354153.git.khickey@rmicorp.com> <0946334bbaf9883076889fe060a362b72d31e6f4.1236354153.git.khickey@rmicorp.com> <394c116b9fa5bd1865ac21d11185f09e07bd2ab5.1236354153.git.khickey@rmicorp.com> <7e632686ab9b29a94eefeb2e5dca8b091a956b95.1236354153.git.khickey@rmicorp.com> In-Reply-To: <788248524efc28ba2608ed79bfb7080ee476b12d.1236354153.git.khickey@rmicorp.com> References: <788248524efc28ba2608ed79bfb7080ee476b12d.1236354153.git.khickey@rmicorp.com> X-OriginalArrivalTime: 06 Mar 2009 16:20:10.0028 (UTC) FILETIME=[6B995EC0:01C99E77] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22026 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: khickey@rmicorp.com Precedence: bulk X-list: linux-mips This patch adds support for the SMSC 9210 Ethernet chip, specialized for Alchemy platforms (including the DB1300). The ethernet driver code was provided by SMSC; the platform shim by RMI. Signed-off-by: Kevin Hickey --- drivers/net/Kconfig | 6 + drivers/net/Makefile | 3 + drivers/net/smsc9210/Makefile | 9 + drivers/net/smsc9210/ioctl_118.h | 298 ++ drivers/net/smsc9210/platform_alchemy.c | 88 + drivers/net/smsc9210/platform_alchemy.h | 117 + drivers/net/smsc9210/smsc9210.h | 23 + drivers/net/smsc9210/smsc9210_main.c | 7189 +++++++++++++++++++++++++++++++ 8 files changed, 7733 insertions(+), 0 deletions(-) create mode 100644 drivers/net/smsc9210/Makefile create mode 100644 drivers/net/smsc9210/ioctl_118.h create mode 100644 drivers/net/smsc9210/platform_alchemy.c create mode 100644 drivers/net/smsc9210/platform_alchemy.h create mode 100644 drivers/net/smsc9210/smsc9210.h create mode 100644 drivers/net/smsc9210/smsc9210_main.c diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 8b13c5d..791735e 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -907,6 +907,12 @@ config SMC91X inserted in and removed from the running kernel whenever you want). The module will be called smc91x. If you want to compile it as a module, say M here and read . + +config SMSC9210 + tristate "SMSC 9210 support" + depends on SOC_AU1X00 + help + TODO config NET_NETX tristate "NetX Ethernet support" diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 3c627d0..7c4052f 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -222,6 +222,9 @@ obj-$(CONFIG_IBMVETH) += ibmveth.o obj-$(CONFIG_S2IO) += s2io.o obj-$(CONFIG_MYRI10GE) += myri10ge/ obj-$(CONFIG_SMC91X) += smc91x.o + +obj-$(CONFIG_SMSC9210) += smsc9210/ + obj-$(CONFIG_SMC911X) += smc911x.o obj-$(CONFIG_SMSC911X) += smsc911x.o obj-$(CONFIG_BFIN_MAC) += bfin_mac.o diff --git a/drivers/net/smsc9210/Makefile b/drivers/net/smsc9210/Makefile new file mode 100644 index 0000000..76a1217 --- /dev/null +++ b/drivers/net/smsc9210/Makefile @@ -0,0 +1,9 @@ +# +# Copyright 2008 RMI Corporation. All rights reserved. +# Author: Kevin Hickey +# + +obj-$(CONFIG_SMSC9210) += smsc9210.o + +smsc9210-objs := smsc9210_main.o platform_alchemy.o + diff --git a/drivers/net/smsc9210/ioctl_118.h b/drivers/net/smsc9210/ioctl_118.h new file mode 100644 index 0000000..07187d7 --- /dev/null +++ b/drivers/net/smsc9210/ioctl_118.h @@ -0,0 +1,298 @@ +/*************************************************************************** + + * + + * Copyright (C) 2004-2005 SMSC + + * + + * This program is free software; you can redistribute it and/or + + * modify it under the terms of the GNU General Public License + + * as published by the Free Software Foundation; either version 2 + + * of the License, or (at your option) any later version. + + * + + * This program is distributed in the hope that it will be useful, + + * but WITHOUT ANY WARRANTY; without even the implied warranty of + + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + + * GNU General Public License for more details. + + * + + * You should have received a copy of the GNU General Public License + + * along with this program; if not, write to the Free Software + + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + + * + + *************************************************************************** + + * File: ioctl_118.h + + */ + + + +#ifndef IOCTL_118_H + +#define IOCTL_118_H + + + +#define DRIVER_VERSION (0x00000155UL) + + + +#define SMSC9118_DRIVER_SIGNATURE (0x82745BACUL+DRIVER_VERSION) + +#define SMSC9118_APP_SIGNATURE (0x987BEF28UL+DRIVER_VERSION) + + + +#define SMSC9118_IOCTL (SIOCDEVPRIVATE + 0xB) + + + +#define COMMAND_BASE (0x974FB832UL) + + + +#define COMMAND_GET_SIGNATURE (COMMAND_BASE+0) + + + +#define COMMAND_LAN_GET_REG (COMMAND_BASE+1) + +#define COMMAND_LAN_SET_REG (COMMAND_BASE+2) + + + +#define COMMAND_MAC_GET_REG (COMMAND_BASE+3) + +#define COMMAND_MAC_SET_REG (COMMAND_BASE+4) + + + +#define COMMAND_PHY_GET_REG (COMMAND_BASE+5) + +#define COMMAND_PHY_SET_REG (COMMAND_BASE+6) + + + +#define COMMAND_DUMP_LAN_REGS (COMMAND_BASE+7) + +#define LAN_REG_ID_REV (0) + +#define LAN_REG_INT_CFG (1) + +#define LAN_REG_INT_STS (2) + +#define LAN_REG_INT_EN (3) + +#define LAN_REG_BYTE_TEST (4) + +#define LAN_REG_FIFO_INT (5) + +#define LAN_REG_RX_CFG (6) + +#define LAN_REG_TX_CFG (7) + +#define LAN_REG_HW_CFG (8) + +#define LAN_REG_RX_DP_CTRL (9) + +#define LAN_REG_RX_FIFO_INF (10) + +#define LAN_REG_TX_FIFO_INF (11) + +#define LAN_REG_PMT_CTRL (12) + +#define LAN_REG_GPIO_CFG (13) + +#define LAN_REG_GPT_CFG (14) + +#define LAN_REG_GPT_CNT (15) + +#define LAN_REG_FPGA_REV (16) + +#define LAN_REG_WORD_SWAP (17) + +#define LAN_REG_FREE_RUN (18) + +#define LAN_REG_RX_DROP (19) + +#define LAN_REG_MAC_CSR_CMD (21) + +#define LAN_REG_MAC_CSR_DATA (22) + +#define LAN_REG_AFC_CFG (23) + +#define LAN_REG_E2P_CMD (24) + +#define LAN_REG_E2P_DATA (25) + + + +#define COMMAND_DUMP_MAC_REGS (COMMAND_BASE+8) + +#define MAC_REG_MAC_CR (0) + +#define MAC_REG_ADDRH (1) + +#define MAC_REG_ADDRL (2) + +#define MAC_REG_HASHH (3) + +#define MAC_REG_HASHL (4) + +#define MAC_REG_MII_ACC (5) + +#define MAC_REG_MII_DATA (6) + +#define MAC_REG_FLOW (7) + +#define MAC_REG_VLAN1 (8) + +#define MAC_REG_VLAN2 (9) + +#define MAC_REG_WUFF (10) + +#define MAC_REG_WUCSR (11) + + + +#define COMMAND_DUMP_PHY_REGS (COMMAND_BASE+9) + +#define PHY_REG_0 (0) + +#define PHY_REG_1 (1) + +#define PHY_REG_2 (2) + +#define PHY_REG_3 (3) + +#define PHY_REG_4 (4) + +#define PHY_REG_5 (5) + +#define PHY_REG_6 (6) + +#define PHY_REG_16 (7) + +#define PHY_REG_17 (8) + +#define PHY_REG_18 (9) + +#define PHY_REG_20 (10) + +#define PHY_REG_21 (11) + +#define PHY_REG_22 (12) + +#define PHY_REG_23 (13) + +#define PHY_REG_27 (14) + +#define PHY_REG_28 (15) + +#define PHY_REG_29 (16) + +#define PHY_REG_30 (17) + +#define PHY_REG_31 (18) + + + +#define COMMAND_DUMP_EEPROM (COMMAND_BASE+10) + + + +#define COMMAND_GET_MAC_ADDRESS (COMMAND_BASE+11) + +#define COMMAND_SET_MAC_ADDRESS (COMMAND_BASE+12) + +#define COMMAND_LOAD_MAC_ADDRESS (COMMAND_BASE+13) + +#define COMMAND_SAVE_MAC_ADDRESS (COMMAND_BASE+14) + +#define COMMAND_SET_DEBUG_MODE (COMMAND_BASE+15) + + + +#define COMMAND_SET_POWER_MODE (COMMAND_BASE+16) + +#define COMMAND_GET_POWER_MODE (COMMAND_BASE+17) + + + +#define COMMAND_SET_LINK_MODE (COMMAND_BASE+18) + +#define COMMAND_GET_LINK_MODE (COMMAND_BASE+19) + +#define COMMAND_GET_CONFIGURATION (COMMAND_BASE+20) + +#define COMMAND_DUMP_TEMP (COMMAND_BASE+21) + +#define COMMAND_READ_BYTE (COMMAND_BASE+22) + +#define COMMAND_READ_WORD (COMMAND_BASE+23) + +#define COMMAND_READ_DWORD (COMMAND_BASE+24) + +#define COMMAND_WRITE_BYTE (COMMAND_BASE+25) + +#define COMMAND_WRITE_WORD (COMMAND_BASE+26) + +#define COMMAND_WRITE_DWORD (COMMAND_BASE+27) + +#define COMMAND_CHECK_LINK (COMMAND_BASE+28) + + + +//the following codes are intended for cmd9118 only + +// they are not intended to have any use in the driver + +#define COMMAND_RUN_SERVER (COMMAND_BASE+29) + +#define COMMAND_RUN_TUNER (COMMAND_BASE+30) + + + +#define COMMAND_GET_FLOW_PARAMS (COMMAND_BASE+31) + +#define COMMAND_SET_FLOW_PARAMS (COMMAND_BASE+32) + +#define COMMAND_SET_AMDIX_STS (COMMAND_BASE+33) + +#define COMMAND_GET_AMDIX_STS (COMMAND_BASE+34) + +typedef struct _SMSC9118_IOCTL_DATA { + + unsigned long dwSignature; + + unsigned long dwCommand; + + unsigned long Data[0x60]; + + char Strng1[30]; + + char Strng2[10]; + +} SMSC9118_IOCTL_DATA, *PSMSC9118_IOCTL_DATA; + + + +#endif + + + diff --git a/drivers/net/smsc9210/platform_alchemy.c b/drivers/net/smsc9210/platform_alchemy.c new file mode 100644 index 0000000..1da19a6 --- /dev/null +++ b/drivers/net/smsc9210/platform_alchemy.c @@ -0,0 +1,88 @@ +/* + * Copyright 2003-2008 RMI Corporation. All rights reserved. + * Author: Kevin Hickey + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED BY RMI Corporation 'AS IS' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL RMI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include "platform_alchemy.h" + +u32 Platform_Initialize(PPLATFORM_DATA pd, u32 lan_base, u32 bus_width) +{ + return BASE_ADDRESS; +} + + +/* + * Ignores the passed in irq in favor of the one we know to be correct... + */ +bool Platform_RequestIRQ(PPLATFORM_DATA pd, + u32 irq, + irqreturn_t (*pIsr)(int irq,void *dev_id), + void* dev_id ) +{ + int retval = request_irq(PLATFORM_IRQ, pIsr, 0, "SMSC 9210 Ethernet", dev_id); + pd->irq_dev_id = dev_id; + + return retval == 0 ? true : false; +} + +void Platform_FreeIRQ(PPLATFORM_DATA pd) +{ + free_irq(PLATFORM_IRQ, pd->irq_dev_id); +} + +void Platform_WriteFifo(u32 lan_base, u32 *buf, u32 count) +{ + int i; + for(i = 0; i < count; ++i) + { + au_iowrite32(*buf, (u32*)(lan_base+0x20)); + ++buf; + } +} + +void Platform_ReadFifo(u32 lan_base, u32 *buf, u32 count) +{ + int i; + for(i = 0; i < count; ++i) + { + *buf = au_ioread32((u32*)lan_base); + ++buf; + } + +} + +void Platform_GetFlowControlParameters(PPLATFORM_DATA pd, PFLOW_CONTROL_PARAMETERS fcp, bool useDma) +{ + /* + * Borrowed from xscale_linux.c in the 16-bit PIO 8210 section + */ + memset(fcp,0,sizeof(FLOW_CONTROL_PARAMETERS)); + fcp->BurstPeriod=100; + fcp->IntDeas=0; + fcp->MaxThroughput=0x74378UL; + fcp->MaxPacketCount=0x13AUL; + fcp->PacketCost=0x02UL; + fcp->BurstPeriod=0x76UL; + fcp->IntDeas=0x18UL; +} diff --git a/drivers/net/smsc9210/platform_alchemy.h b/drivers/net/smsc9210/platform_alchemy.h new file mode 100644 index 0000000..17f42e3 --- /dev/null +++ b/drivers/net/smsc9210/platform_alchemy.h @@ -0,0 +1,117 @@ +/* + * Copyright 2003-2008 RMI Corporation. All rights reserved. + * Author: Kevin Hickey + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED BY RMI Corporation 'AS IS' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL RMI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef PLATFORM_ALCHEMY_H +#define PLATFORM_ALCHEMY_H + +#include +#include + +#if defined(CONFIG_MIPS_DB1200) +#include +#define PLATFORM_IRQ DB1200_DC_INT +#elif defined(CONFIG_MIPS_HMP10) +#include +#define PLATFORM_IRQ HMP10_ETH_IRQ +#elif defined(CONFIG_MIPS_DB1300) +#include +#define PLATFORM_IRQ DB1300_ETHERNET_IRQ +#endif + +#include "smsc9210.h" +/* + * Make the IRQ a push-pull; on DB1300 there is no pull up so open-drain will + * always be low. + */ +#define PLATFORM_IRQ_POL 0 +#define PLATFORM_IRQ_TYPE 1 +#define PLATFORM_CACHE_LINE_BYTES 0 +#define PLATFORM_RX_DMA TRANSFER_PIO +#define PLATFORM_TX_DMA TRANSFER_PIO +#define PLATFORM_DMA_THRESHOLD 0 +#define PLATFORM_NAME "Alchemy" + +#ifdef CONFIG_MIPS_DB1200 +#define BASE_ADDRESS 0xBA000000 +#else +#define BASE_ADDRESS 0xB9000000 +#endif + +typedef struct { + void *irq_dev_id; +} PLATFORM_DATA, *PPLATFORM_DATA; + +u32 Platform_Initialize(PPLATFORM_DATA pd, u32 lan_base, u32 bus_width); + +static void Platform_CleanUp(PPLATFORM_DATA pd) { } +static u32 Platform_CurrentIRQ(PPLATFORM_DATA pd) +{ + return PLATFORM_IRQ; +} + +static inline void Platform_SetRegDW(u32 lan_base, u32 offset, u32 val) +{ + au_writel(val, (lan_base + offset)); +} + +static inline u32 Platform_GetRegDW(u32 lan_base, u32 offset) +{ + return au_readl(lan_base + offset); +} + +bool Platform_RequestIRQ(PPLATFORM_DATA pd, + u32 irq, + irqreturn_t (*pIsr)(int irq, void *dev_id), + void* dev_id ); + +void Platform_FreeIRQ(PPLATFORM_DATA pd); +void Platform_GetFlowControlParameters(PPLATFORM_DATA pd, PFLOW_CONTROL_PARAMETERS fcp, bool useDma); +void Platform_WriteFifo(u32 lan_base, u32 *buf, u32 count); +void Platform_ReadFifo(u32 lan_base, u32 *buf, u32 count); + +/* * We're not supporting DMA at this time, so degenerate all functions to return + * errors. + */ +static inline bool Platform_IsValidDmaChannel(u32 chan) { return false; } +static inline bool Platform_DmaInitialize(PPLATFORM_DATA pd, u32 chan) { return false; } +static inline bool Platform_DmaDisable(PPLATFORM_DATA pd, u32 chan) { return false; } +static inline void Platform_CacheInvalidate(PPLATFORM_DATA pd, const void *const sa, + const u32 len) { } +static inline void Platform_CachePurge(PPLATFORM_DATA pd, const void *const sa, + const u32 len) { } +static inline u32 Platform_RequestDmaChannel(PPLATFORM_DATA pd) { return TRANSFER_PIO; } +static inline void Platform_ReleaseDmaChannel(PPLATFORM_DATA pd, u32 chan) { } +static inline bool Platform_DmaStartXfer(PPLATFORM_DATA pd, const DMA_XFER * const pDmaXfer) +{ + return false; +} +static inline u32 Platform_DmaGetDwCnt(PPLATFORM_DATA platformData, const u32 dwDmaCh) +{ + return 0; +} +static inline void Platform_DmaComplete(PPLATFORM_DATA platformData, const u32 dwDmaCh) { } + + +#endif /* PLATFORM_ALCHEMY_H */ diff --git a/drivers/net/smsc9210/smsc9210.h b/drivers/net/smsc9210/smsc9210.h new file mode 100644 index 0000000..903b156 --- /dev/null +++ b/drivers/net/smsc9210/smsc9210.h @@ -0,0 +1,23 @@ +#ifndef SMSC9210_H +#define SMSC9210_H + +#define TRANSFER_PIO (256UL) + +typedef struct _DMA_XFER +{ + u32 dwLanReg; + u32 *pdwBuf; + u32 dwDmaCh; + u32 dwDwCnt; + bool fMemWr; +} DMA_XFER; + +typedef struct _FLOW_CONTROL_PARAMETERS +{ + u32 MaxThroughput; + u32 MaxPacketCount; + u32 PacketCost; + u32 BurstPeriod; + u32 IntDeas; +} FLOW_CONTROL_PARAMETERS, *PFLOW_CONTROL_PARAMETERS; +#endif /* SMSC9210_H */ diff --git a/drivers/net/smsc9210/smsc9210_main.c b/drivers/net/smsc9210/smsc9210_main.c new file mode 100644 index 0000000..15fbf7f --- /dev/null +++ b/drivers/net/smsc9210/smsc9210_main.c @@ -0,0 +1,7189 @@ +/*************************************************************************** + * + * Copyright (C) 2004-2005 SMSC + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. + * + *************************************************************************** + * File: smsc9118.c + * see readme.txt for programmers guide + */ + + +//#define UseScatterGather +//#define UseTxCsum +//#define UseRxCsum + +#define USE_DEBUG + +#ifndef __KERNEL__ +# define __KERNEL__ +#endif + +#ifdef USING_LINT +#include "lint.h" +#else //not USING_LINT +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include "smsc9210.h" + +#endif //not USING_LINT + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)) +typedef void irqreturn_t; +#define IRQ_NONE +#define IRQ_HANDLED +#define IRQ_RETVAL(x) +#else +#define LINUX_2_6_OR_NEWER +#endif + +#ifdef USE_DEBUG +static u32 debug_mode=0x7UL; +#else +static u32 debug_mode=0x0UL; +#endif + +#ifdef USE_DEBUG +//select debug modes +#define USE_WARNING +#define USE_TRACE +#define USE_ASSERT +#endif //USE_DEBUG + +#define USE_LED1_WORK_AROUND // 10/100 LED link-state inversion +#define USE_PHY_WORK_AROUND // output polarity inversion + +typedef long TIME_SPAN; +#define MAX_TIME_SPAN ((TIME_SPAN)(0x7FFFFFFFUL)) +typedef unsigned short WORD; +typedef unsigned char BYTE; +//typedef unsigned char bool; +#define true ((bool)1) +#define false ((bool)0) + +//unsigned char testbuff[1600]={0}; +//u32 * p= NULL; + + +#define HIBYTE(word) ((BYTE)(((WORD)(word))>>8)) +#define LOBYTE(word) ((BYTE)(((WORD)(word))&0x00FFU)) +#define HIWORD(dWord) ((WORD)(((u32)(dWord))>>16)) +#define LOWORD(dWord) ((WORD)(((u32)(dWord))&0x0000FFFFUL)) + +#define TRANSFER_PIO (256UL) +#define TRANSFER_REQUEST_DMA (255UL) +//these are values that can be assigned to +//PLATFORM_RX_DMA +//PLATFORM_TX_DMA +// in addition to any specific dma channel + +/******************************************************* + * Macro: SMSC_TRACE + * Description: + * This macro is used like printf. + * It can be used anywhere you want to display information + * For any release version it should not be left in + * performance sensitive Tx and Rx code paths. + * To use this macro define USE_TRACE and set bit 0 of debug_mode + *******************************************************/ +#ifdef USING_LINT +extern void SMSC_TRACE(const char * a, ...); +#else //not USING_LINT +#ifdef USE_TRACE +#ifndef USE_WARNING +#define USE_WARNING +#endif +# define SMSC_TRACE(msg,args...) \ + if(debug_mode&0x01UL) { \ + printk("SMSC: " msg "\n", ## args); \ + } +#else +# define SMSC_TRACE(msg,args...) +#endif +#endif //not USING_LINT + +/******************************************************* + * Macro: SMSC_WARNING + * Description: + * This macro is used like printf. + * It can be used anywhere you want to display warning information + * For any release version it should not be left in + * performance sensitive Tx and Rx code paths. + * To use this macro define USE_TRACE or + * USE_WARNING and set bit 1 of debug_mode + *******************************************************/ + + +#ifdef USING_LINT +extern void SMSC_WARNING(const char * a, ...); +#else //not USING_LINT +#ifdef USE_WARNING +#ifndef USE_ASSERT +#define USE_ASSERT +#endif +# define SMSC_WARNING(msg, args...) \ + if(debug_mode&0x02UL) { \ + printk("SMSC_WARNING: " msg "\n",## args); \ + } +#else +# define SMSC_WARNING(msg, args...) +#endif +#endif //not USING_LINT + + +/******************************************************* + * Macro: SMSC_ASSERT + * Description: + * This macro is used to test assumptions made when coding. + * It can be used anywhere, but is intended only for situations + * where a failure is fatal. + * If code execution where allowed to continue it is assumed that + * only further unrecoverable errors would occur and so this macro + * includes an infinite loop to prevent further corruption. + * Assertions are only intended for use during developement to + * insure consistency of logic through out the driver. + * A driver should not be released if assertion failures are + * still occuring. + * To use this macro define USE_TRACE or USE_WARNING or + * USE_ASSERT + *******************************************************/ +#ifdef USING_LINT +extern void SMSC_ASSERT(bool condition); +#else //not USING_LINT +#ifdef USE_ASSERT +# define SMSC_ASSERT(condition) \ + if(!(condition)) { \ + printk("SMSC_ASSERTION_FAILURE: File=" __FILE__ ", Line=%d\n",__LINE__); \ + while(1); \ + } +#else +# define SMSC_ASSERT(condition) +#endif +#endif //not USING_LINT + +//Below are the register offsets and bit definitions +// of the Lan9118 memory space +#define RX_DATA_FIFO (0x00UL) +#define TX_DATA_FIFO (0x20UL) +#define TX_CMD_A_INT_ON_COMP_ (0x80000000UL) +#define TX_CMD_A_INT_BUF_END_ALGN_ (0x03000000UL) +#define TX_CMD_A_INT_4_BYTE_ALGN_ (0x00000000UL) +#define TX_CMD_A_INT_16_BYTE_ALGN_ (0x01000000UL) +#define TX_CMD_A_INT_32_BYTE_ALGN_ (0x02000000UL) +#define TX_CMD_A_INT_DATA_OFFSET_ (0x001F0000UL) +#define TX_CMD_A_INT_FIRST_SEG_ (0x00002000UL) +#define TX_CMD_A_INT_LAST_SEG_ (0x00001000UL) +#define TX_CMD_A_BUF_SIZE_ (0x000007FFUL) +#define TX_CMD_B_PKT_TAG_ (0xFFFF0000UL) +#define TX_CMD_B_CSUM_ENABLE (0x00004000UL) +#define TX_CMD_B_ADD_CRC_DISABLE_ (0x00002000UL) +#define TX_CMD_B_DISABLE_PADDING_ (0x00001000UL) +#define TX_CMD_B_PKT_BYTE_LENGTH_ (0x000007FFUL) + +#define RX_STATUS_FIFO (0x40UL) +#define RX_STS_ES_ (0x00008000UL) +#define RX_STS_MCAST_ (0x00000400UL) +#define RX_STATUS_FIFO_PEEK (0x44UL) +#define TX_STATUS_FIFO (0x48UL) +#define TX_STATUS_FIFO_PEEK (0x4CUL) +#define ID_REV (0x50UL) +#define ID_REV_CHIP_ID_ (0xFFFF0000UL) // RO +#define ID_REV_REV_ID_ (0x0000FFFFUL) // RO + +#define INT_CFG (0x54UL) +#define INT_CFG_INT_DEAS_ (0xFF000000UL) // R/W +#define INT_CFG_IRQ_INT_ (0x00001000UL) // RO +#define INT_CFG_IRQ_EN_ (0x00000100UL) // R/W +#define INT_CFG_IRQ_POL_ (0x00000010UL) // R/W Not Affected by SW Reset +#define INT_CFG_IRQ_TYPE_ (0x00000001UL) // R/W Not Affected by SW Reset + +#define INT_STS (0x58UL) +#define INT_STS_SW_INT_ (0x80000000UL) // R/WC +#define INT_STS_TXSTOP_INT_ (0x02000000UL) // R/WC +#define INT_STS_RXSTOP_INT_ (0x01000000UL) // R/WC +#define INT_STS_RXDFH_INT_ (0x00800000UL) // R/WC +#define INT_STS_RXDF_INT_ (0x00400000UL) // R/WC +#define INT_STS_TX_IOC_ (0x00200000UL) // R/WC +#define INT_STS_RXD_INT_ (0x00100000UL) // R/WC +#define INT_STS_GPT_INT_ (0x00080000UL) // R/WC +#define INT_STS_PHY_INT_ (0x00040000UL) // RO +#define INT_STS_PME_INT_ (0x00020000UL) // R/WC +#define INT_STS_TXSO_ (0x00010000UL) // R/WC +#define INT_STS_RWT_ (0x00008000UL) // R/WC +#define INT_STS_RXE_ (0x00004000UL) // R/WC +#define INT_STS_TXE_ (0x00002000UL) // R/WC +#define INT_STS_ERX_ (0x00001000UL) // R/WC +#define INT_STS_TDFU_ (0x00000800UL) // R/WC +#define INT_STS_TDFO_ (0x00000400UL) // R/WC +#define INT_STS_TDFA_ (0x00000200UL) // R/WC +#define INT_STS_TSFF_ (0x00000100UL) // R/WC +#define INT_STS_TSFL_ (0x00000080UL) // R/WC +#define INT_STS_RDFO_ (0x00000040UL) // R/WC +#define INT_STS_RDFL_ (0x00000020UL) // R/WC +#define INT_STS_RSFF_ (0x00000010UL) // R/WC +#define INT_STS_RSFL_ (0x00000008UL) // R/WC +#define INT_STS_GPIO2_INT_ (0x00000004UL) // R/WC +#define INT_STS_GPIO1_INT_ (0x00000002UL) // R/WC +#define INT_STS_GPIO0_INT_ (0x00000001UL) // R/WC + +#define INT_EN (0x5CUL) +#define INT_EN_SW_INT_EN_ (0x80000000UL) // R/W +#define INT_EN_TXSTOP_INT_EN_ (0x02000000UL) // R/W +#define INT_EN_RXSTOP_INT_EN_ (0x01000000UL) // R/W +#define INT_EN_RXDFH_INT_EN_ (0x00800000UL) // R/W +#define INT_EN_RXDF_INT_EN_ (0x00400000UL) // R/W +#define INT_EN_TIOC_INT_EN_ (0x00200000UL) // R/W +#define INT_EN_RXD_INT_EN_ (0x00100000UL) // R/W +#define INT_EN_GPT_INT_EN_ (0x00080000UL) // R/W +#define INT_EN_PHY_INT_EN_ (0x00040000UL) // R/W +#define INT_EN_PME_INT_EN_ (0x00020000UL) // R/W +#define INT_EN_TXSO_EN_ (0x00010000UL) // R/W +#define INT_EN_RWT_EN_ (0x00008000UL) // R/W +#define INT_EN_RXE_EN_ (0x00004000UL) // R/W +#define INT_EN_TXE_EN_ (0x00002000UL) // R/W +#define INT_EN_ERX_EN_ (0x00001000UL) // R/W +#define INT_EN_TDFU_EN_ (0x00000800UL) // R/W +#define INT_EN_TDFO_EN_ (0x00000400UL) // R/W +#define INT_EN_TDFA_EN_ (0x00000200UL) // R/W +#define INT_EN_TSFF_EN_ (0x00000100UL) // R/W +#define INT_EN_TSFL_EN_ (0x00000080UL) // R/W +#define INT_EN_RDFO_EN_ (0x00000040UL) // R/W +#define INT_EN_RDFL_EN_ (0x00000020UL) // R/W +#define INT_EN_RSFF_EN_ (0x00000010UL) // R/W +#define INT_EN_RSFL_EN_ (0x00000008UL) // R/W +#define INT_EN_GPIO2_INT_ (0x00000004UL) // R/W +#define INT_EN_GPIO1_INT_ (0x00000002UL) // R/W +#define INT_EN_GPIO0_INT_ (0x00000001UL) // R/W + +#define BYTE_TEST (0x64UL) +#define FIFO_INT (0x68UL) +#define FIFO_INT_TX_AVAIL_LEVEL_ (0xFF000000UL) // R/W +#define FIFO_INT_TX_STS_LEVEL_ (0x00FF0000UL) // R/W +#define FIFO_INT_RX_AVAIL_LEVEL_ (0x0000FF00UL) // R/W +#define FIFO_INT_RX_STS_LEVEL_ (0x000000FFUL) // R/W + +#define RX_CFG (0x6CUL) +#define RX_CFG_RX_END_ALGN_ (0xC0000000UL) // R/W +#define RX_CFG_RX_END_ALGN4_ (0x00000000UL) // R/W +#define RX_CFG_RX_END_ALGN16_ (0x40000000UL) // R/W +#define RX_CFG_RX_END_ALGN32_ (0x80000000UL) // R/W +#define RX_CFG_RX_DMA_CNT_ (0x0FFF0000UL) // R/W +#define RX_CFG_RX_DUMP_ (0x00008000UL) // R/W +#define RX_CFG_RXDOFF_ (0x00001F00UL) // R/W +#define RX_CFG_RXDOFF_2_ (0x00000200UL) //Rx data offset is 2 +#define RX_CFG_RXDOFF_18_ (0x00001200UL) //Rx data offset is 0x12 +#define RX_CFG_RXBAD_ (0x00000001UL) // R/W + +#define TX_CFG (0x70UL) +#define TX_CFG_TX_DMA_LVL_ (0xE0000000UL) // R/W +#define TX_CFG_TX_DMA_CNT_ (0x0FFF0000UL) // R/W Self Clearing +#define TX_CFG_TXS_DUMP_ (0x00008000UL) // Self Clearing +#define TX_CFG_TXD_DUMP_ (0x00004000UL) // Self Clearing +#define TX_CFG_TXSAO_ (0x00000004UL) // R/W +#define TX_CFG_TX_ON_ (0x00000002UL) // R/W +#define TX_CFG_STOP_TX_ (0x00000001UL) // Self Clearing + +#define HW_CFG (0x74UL) +#define HW_CFG_AMDIX_EN_STRAP_STS_ (0x01000000UL) +#define HW_CFG_TTM_ (0x00200000UL) // R/W +#define HW_CFG_SF_ (0x00100000UL) // R/W +#define HW_CFG_TX_FIF_SZ_ (0x000F0000UL) // R/W +#define HW_CFG_TR_ (0x00003000UL) // R/W +#define HW_CFG_PHY_CLK_SEL_ (0x00000060UL) // R/W +#define HW_CFG_PHY_CLK_SEL_INT_PHY_ (0x00000000UL) // R/W +#define HW_CFG_PHY_CLK_SEL_EXT_PHY_ (0x00000020UL) // R/W +#define HW_CFG_PHY_CLK_SEL_CLK_DIS_ (0x00000040UL) // R/W +#define HW_CFG_SMI_SEL_ (0x00000010UL) // R/W +#define HW_CFG_EXT_PHY_DET_ (0x00000008UL) // RO +#define HW_CFG_EXT_PHY_EN_ (0x00000004UL) // R/W +#define HW_CFG_32_16_BIT_MODE_ (0x00000004UL) // RO +#define HW_CFG_SRST_TO_ (0x00000002UL) // RO +#define HW_CFG_SRST_ (0x00000001UL) // Self Clearing + +#define RX_DP_CTRL (0x78UL) +#define RX_DP_CTRL_RX_FFWD_ (0x00000FFFUL) // R/W +#define RX_DP_CTRL_FFWD_BUSY_ (0x80000000UL) // RO + +#define RX_FIFO_INF (0x7CUL) +#define RX_FIFO_INF_RXSUSED_ (0x00FF0000UL) // RO +#define RX_FIFO_INF_RXDUSED_ (0x0000FFFFUL) // RO + +#define TX_FIFO_INF (0x80UL) +#define TX_FIFO_INF_TSUSED_ (0x00FF0000UL) // RO +#define TX_FIFO_INF_TSFREE_ (0x00FF0000UL) // RO +#define TX_FIFO_INF_TDFREE_ (0x0000FFFFUL) // RO + +#define PMT_CTRL (0x84UL) +#define PMT_CTRL_PM_MODE_ (0x00018000UL) // Self Clearing +#define PMT_CTRL_PHY_RST_ (0x00000400UL) // Self Clearing +#define PMT_CTRL_WOL_EN_ (0x00000200UL) // R/W +#define PMT_CTRL_ED_EN_ (0x00000100UL) // R/W +#define PMT_CTRL_PME_TYPE_ (0x00000040UL) // R/W Not Affected by SW Reset +#define PMT_CTRL_WUPS_ (0x00000030UL) // R/WC +#define PMT_CTRL_WUPS_NOWAKE_ (0x00000000UL) // R/WC +#define PMT_CTRL_WUPS_ED_ (0x00000010UL) // R/WC +#define PMT_CTRL_WUPS_WOL_ (0x00000020UL) // R/WC +#define PMT_CTRL_WUPS_MULTI_ (0x00000030UL) // R/WC +#define PMT_CTRL_PME_IND_ (0x00000008UL) // R/W +#define PMT_CTRL_PME_POL_ (0x00000004UL) // R/W +#define PMT_CTRL_PME_EN_ (0x00000002UL) // R/W Not Affected by SW Reset +#define PMT_CTRL_READY_ (0x00000001UL) // RO + +#define GPIO_CFG (0x88UL) +#define GPIO_CFG_LED3_EN_ (0x40000000UL) // R/W +#define GPIO_CFG_LED2_EN_ (0x20000000UL) // R/W +#define GPIO_CFG_LED1_EN_ (0x10000000UL) // R/W +#define GPIO_CFG_GPIO2_INT_POL_ (0x04000000UL) // R/W +#define GPIO_CFG_GPIO1_INT_POL_ (0x02000000UL) // R/W +#define GPIO_CFG_GPIO0_INT_POL_ (0x01000000UL) // R/W +#define GPIO_CFG_EEPR_EN_ (0x00E00000UL) // R/W +#define GPIO_CFG_GPIOBUF2_ (0x00040000UL) // R/W +#define GPIO_CFG_GPIOBUF1_ (0x00020000UL) // R/W +#define GPIO_CFG_GPIOBUF0_ (0x00010000UL) // R/W +#define GPIO_CFG_GPIODIR2_ (0x00000400UL) // R/W +#define GPIO_CFG_GPIODIR1_ (0x00000200UL) // R/W +#define GPIO_CFG_GPIODIR0_ (0x00000100UL) // R/W +#define GPIO_CFG_GPIOD4_ (0x00000020UL) // R/W +#define GPIO_CFG_GPIOD3_ (0x00000010UL) // R/W +#define GPIO_CFG_GPIOD2_ (0x00000004UL) // R/W +#define GPIO_CFG_GPIOD1_ (0x00000002UL) // R/W +#define GPIO_CFG_GPIOD0_ (0x00000001UL) // R/W + +#define GPT_CFG (0x8CUL) +#define GPT_CFG_TIMER_EN_ (0x20000000UL) // R/W +#define GPT_CFG_GPT_LOAD_ (0x0000FFFFUL) // R/W + +#define GPT_CNT (0x90UL) +#define GPT_CNT_GPT_CNT_ (0x0000FFFFUL) // RO + +#define FPGA_REV (0x94UL) +#define FPGA_REV_FPGA_REV_ (0x0000FFFFUL) // RO + +#define WORD_SWAP (0x98UL) +#define FREE_RUN (0x9CUL) +#define RX_DROP (0xA0UL) +#define MAC_CSR_CMD (0xA4UL) +#define MAC_CSR_CMD_CSR_BUSY_ (0x80000000UL) // Self Clearing +#define MAC_CSR_CMD_R_NOT_W_ (0x40000000UL) // R/W +#define MAC_CSR_CMD_CSR_ADDR_ (0x000000FFUL) // R/W + +#define MAC_CSR_DATA (0xA8UL) +#define AFC_CFG (0xACUL) +#define AFC_CFG_AFC_HI_ (0x00FF0000UL) // R/W +#define AFC_CFG_AFC_LO_ (0x0000FF00UL) // R/W +#define AFC_CFG_BACK_DUR_ (0x000000F0UL) // R/W +#define AFC_CFG_FCMULT_ (0x00000008UL) // R/W +#define AFC_CFG_FCBRD_ (0x00000004UL) // R/W +#define AFC_CFG_FCADD_ (0x00000002UL) // R/W +#define AFC_CFG_FCANY_ (0x00000001UL) // R/W + +#define E2P_CMD (0xB0UL) +#define E2P_CMD_EPC_BUSY_ (0x80000000UL) // Self Clearing +#define E2P_CMD_EPC_CMD_ (0x70000000UL) // R/W +#define E2P_CMD_EPC_CMD_READ_ (0x00000000UL) // R/W +#define E2P_CMD_EPC_CMD_EWDS_ (0x10000000UL) // R/W +#define E2P_CMD_EPC_CMD_EWEN_ (0x20000000UL) // R/W +#define E2P_CMD_EPC_CMD_WRITE_ (0x30000000UL) // R/W +#define E2P_CMD_EPC_CMD_WRAL_ (0x40000000UL) // R/W +#define E2P_CMD_EPC_CMD_ERASE_ (0x50000000UL) // R/W +#define E2P_CMD_EPC_CMD_ERAL_ (0x60000000UL) // R/W +#define E2P_CMD_EPC_CMD_RELOAD_ (0x70000000UL) // R/W +#define E2P_CMD_EPC_TIMEOUT_ (0x00000200UL) // R +#define E2P_CMD_MAC_ADDR_LOADED_ (0x00000100UL) // RO +#define E2P_CMD_EPC_ADDR_ (0x000000FFUL) // R/W + +#define E2P_DATA (0xB4UL) +#define E2P_DATA_EEPROM_DATA_ (0x000000FFUL) // R/W +//end of lan register offsets and bit definitions + +#define LAN_REGISTER_EXTENT (0x00002000UL) + +//The following describes the synchronization policies used in this driver. +//Register Name Policy +//RX_DATA_FIFO Only used by the Rx Thread, Rx_ProcessPackets +//TX_DATA_FIFO Only used by the Tx Thread, Tx_SendSkb +//RX_STATUS_FIFO Only used by the Rx Thread, Rx_ProcessPackets +//RX_STATUS_FIFO_PEEK Not used. +//TX_STATUS_FIFO Used in Tx_CompleteTx in Tx_UpdateTxCounters. +// protected by TxCounterLock +//TX_STATUS_FIFO_PEEK Not used. +//ID_REV Read only +//INT_CFG Set in Lan_Initialize, +// protected by IntEnableLock +//INT_STS Sharable, +//INT_EN Initialized at startup, +// Used in Rx_ProcessPackets +// otherwise protected by IntEnableLock +//BYTE_TEST Read Only +//FIFO_INT Initialized at startup, +// During run time only accessed by +// Tx_HandleInterrupt, and Tx_SendSkb and done in a safe manner +//RX_CFG Used during initialization +// During runtime only used by Rx Thread +//TX_CFG Only used during initialization +//HW_CFG Only used during initialization +//RX_DP_CTRL Only used in Rx Thread, in Rx_FastForward +//RX_FIFO_INF Read Only, Only used in Rx Thread, in Rx_PopRxStatus +//TX_FIFO_INF Read Only, Only used in Tx Thread, in Tx_GetTxStatusCount, Tx_SendSkb, Tx_CompleteTx +//PMT_CTRL Not Used +//GPIO_CFG used during initialization, in Lan_Initialize +// used for debugging +// used during EEPROM access. +// safe enough to not require a lock +//GPT_CFG protected by GpTimerLock +//GPT_CNT Not Used +//WORD_SWAP Not Used +//FREE_RUN Read only +//RX_DROP Used in Rx Interrupt Handler, +// and get_stats. +// safe enough to not require a lock. +//MAC_CSR_CMD Protected by MacPhyLock +//MAC_CSR_DATA Protected by MacPhyLock +// Because the two previous MAC_CSR_ registers are protected +// All MAC, and PHY registers are protected as well. +//AFC_CFG Used during initialization, in Lan_Initialize +// During run time, used in timer call back, in Phy_UpdateLinkMode +//E2P_CMD Used during initialization, in Lan_Initialize +// Used in EEPROM functions +//E2P_DATA Used in EEPROM functions + +#include "platform_alchemy.h" + +#define Lan_GetRegDW(dwOffset) \ + Platform_GetRegDW(privateData->dwLanBase,dwOffset) + +#define Lan_SetRegDW(dwOffset,dwVal) \ + Platform_SetRegDW(privateData->dwLanBase,dwOffset,dwVal) + +#define Lan_ClrBitsDW(dwOffset,dwBits) \ + Platform_SetRegDW(privateData->dwLanBase, \ + dwOffset,Platform_GetRegDW(privateData->dwLanBase, \ + dwOffset)&(~dwBits)) + +#define Lan_SetBitsDW(dwOffset,dwBits) \ + Platform_SetRegDW(privateData->dwLanBase, \ + dwOffset,Platform_GetRegDW(privateData->dwLanBase, \ + dwOffset)|dwBits); + +#define LINK_OFF (0x00UL) +#define LINK_SPEED_10HD (0x01UL) +#define LINK_SPEED_10FD (0x02UL) +#define LINK_SPEED_100HD (0x04UL) +#define LINK_SPEED_100FD (0x08UL) +#define LINK_SYMMETRIC_PAUSE (0x10UL) +#define LINK_ASYMMETRIC_PAUSE (0x20UL) +#define LINK_AUTO_NEGOTIATE (0x40UL) + +typedef unsigned long VL_KEY; +typedef struct _VERIFIABLE_LOCK { + spinlock_t Lock; + VL_KEY KeyCode; +} VERIFIABLE_LOCK, * PVERIFIABLE_LOCK; + +void Vl_InitLock(PVERIFIABLE_LOCK pVl); +bool Vl_CheckLock(PVERIFIABLE_LOCK pVl,VL_KEY keyCode); +VL_KEY Vl_WaitForLock(PVERIFIABLE_LOCK pVl,unsigned long *pdwIntFlags); +void Vl_ReleaseLock(PVERIFIABLE_LOCK pVl,VL_KEY keyCode,unsigned long *pdwIntFlags); + +typedef struct _PRIVATE_DATA { + u32 dwLanBase; + u32 dwIdRev; + u32 dwFpgaRev; + struct net_device *dev; + u32 dwGeneration;//used to decide which workarounds apply + bool UseScatterGather; + bool UseTxCsum; + bool UseRxCsum; + + + spinlock_t IntEnableLock; + bool LanInitialized; + VERIFIABLE_LOCK MacPhyLock; + bool ExtPhy; // + + u32 dwTxDmaCh; + bool TxDmaChReserved; + DMA_XFER TxDmaXfer; + u32 dwTxDmaThreshold; + u32 dwTxQueueDisableMask; + struct sk_buff *TxSkb; + spinlock_t TxSkbLock; + spinlock_t TxQueueLock; + spinlock_t TxCounterLock; + bool TxInitialized; + + + + // BYTE bCoalesceBuf[1600]; + + + + // struct sk_buff *TxSkbPending; + + + u32 dwRxDmaCh; + struct sk_buff *RxSkb; + bool RxDmaChReserved; + u32 dwRxDmaThreshold; + bool RxCongested; + u32 dwRxOffCount; + bool RxOverrun; + u32 RxOverrunCount; + u32 RxStatusDWReadCount; + u32 RxDataDWReadCount; + u32 RxPacketReadCount; + u32 RxFastForwardCount; + u32 RxPioReadCount; + u32 RxDmaReadCount; + u32 RxCongestedCount; + u32 RxDumpCount; + u32 LastReasonForReleasingCPU; + u32 LastRxStatus1; + u32 LastRxStatus2; + u32 LastRxStatus3; + u32 LastIntStatus1; + u32 LastIntStatus2; + u32 LastIntStatus3; + u32 RxUnloadProgress; + u32 RxUnloadPacketProgress; + u32 RxMaxDataFifoSize; + // bool RxVLanPkt; + + //NAPI + int RxWorkLimit; + int RxPacketsReceived; + // bool RxDone; + + + u32 RxFlowCurrentThroughput; + u32 RxFlowCurrentPacketCount; + u32 RxFlowCurrentWorkLoad; + bool MeasuringRxThroughput; + u32 RxFlowMeasuredMaxThroughput; + u32 RxFlowMeasuredMaxPacketCount; + + //RX_FLOW_ACTIVATION specifies the percentage that RxFlowCurrentWorkLoad must exceed + // RxFlowMaxWorkLoad in order to activate flow control +#define RX_FLOW_ACTIVATION (4UL) + + //RX_FLOW_DEACTIVATION specifies the percentage that RxFlowCurrentWorkLoad must reduce + // from RxFlowMaxWorkLoad in order to deactivate flow control +#define RX_FLOW_DEACTIVATION (25UL) + u32 RxFlowMaxWorkLoad; + + FLOW_CONTROL_PARAMETERS RxFlowParameters; + + u32 RxFlowBurstWorkLoad; + u32 RxFlowBurstMaxWorkLoad; + bool RxFlowControlActive; + bool RxFlowBurstActive; + u32 RxInterrupts; + +#define GPT_SCHEDULE_DEPTH (3) + void *GptFunction[GPT_SCHEDULE_DEPTH]; + u32 GptCallTime[GPT_SCHEDULE_DEPTH]; + u32 Gpt_scheduled_slot_index; + spinlock_t GpTimerLock; + + bool Running; + struct net_device_stats stats; + + u32 dwPhyAddress; + u32 dwPhyId; +#ifdef USE_LED1_WORK_AROUND + u32 NotUsingExtPhy; +#endif + BYTE bPhyModel; + BYTE bPhyRev; + u32 dwLinkSpeed; + u32 dwLinkSettings; + u32 dwRemoteFaultCount; + struct timer_list LinkPollingTimer; + bool StopLinkPolling; + WORD wLastADV; + WORD wLastADVatRestart; +#ifdef USE_PHY_WORK_AROUND +#define MIN_PACKET_SIZE (64) + u32 dwTxStartMargen; + BYTE LoopBackTxPacket[MIN_PACKET_SIZE]; + u32 dwTxEndMargen; + u32 dwRxStartMargen; + BYTE LoopBackRxPacket[MIN_PACKET_SIZE]; + u32 dwRxEndMargen; + u32 dwResetCount; +#endif + + bool SoftwareInterruptSignal; + + PLATFORM_DATA PlatformData; + +#define SMSC_IF_NAME_SIZE (10) + char ifName[SMSC_IF_NAME_SIZE]; + + /* for Rx Multicast work around */ + volatile u32 HashLo; + volatile u32 HashHi; + volatile bool MulticastUpdatePending; + volatile u32 set_bits_mask; + volatile u32 clear_bits_mask; + +} PRIVATE_DATA, *PPRIVATE_DATA; + + +/* + **************************************************************************** + **************************************************************************** + * MAC Control and Status Register (Indirect Address) + * Offset (through the MAC_CSR CMD and DATA port) + **************************************************************************** + **************************************************************************** + * + */ +#define MAC_CR (0x01UL) // R/W + +/* MAC_CR - MAC Control Register */ +#define MAC_CR_RXALL_ (0x80000000UL) +#define MAC_CR_HBDIS_ (0x10000000UL) +#define MAC_CR_RCVOWN_ (0x00800000UL) +#define MAC_CR_LOOPBK_ (0x00200000UL) +#define MAC_CR_FDPX_ (0x00100000UL) +#define MAC_CR_MCPAS_ (0x00080000UL) +#define MAC_CR_PRMS_ (0x00040000UL) +#define MAC_CR_INVFILT_ (0x00020000UL) +#define MAC_CR_PASSBAD_ (0x00010000UL) +#define MAC_CR_HFILT_ (0x00008000UL) +#define MAC_CR_HPFILT_ (0x00002000UL) +#define MAC_CR_LCOLL_ (0x00001000UL) +#define MAC_CR_BCAST_ (0x00000800UL) +#define MAC_CR_DISRTY_ (0x00000400UL) +#define MAC_CR_PADSTR_ (0x00000100UL) +#define MAC_CR_BOLMT_MASK_ (0x000000C0UL) +#define MAC_CR_DFCHK_ (0x00000020UL) +#define MAC_CR_TXEN_ (0x00000008UL) +#define MAC_CR_RXEN_ (0x00000004UL) + +#define ADDRH (0x02UL) // R/W mask 0x0000FFFFUL +#define ADDRL (0x03UL) // R/W mask 0xFFFFFFFFUL +#define HASHH (0x04UL) // R/W +#define HASHL (0x05UL) // R/W + +#define MII_ACC (0x06UL) // R/W +#define MII_ACC_PHY_ADDR_ (0x0000F800UL) +#define MII_ACC_MIIRINDA_ (0x000007C0UL) +#define MII_ACC_MII_WRITE_ (0x00000002UL) +#define MII_ACC_MII_BUSY_ (0x00000001UL) + +#define MII_DATA (0x07UL) // R/W mask 0x0000FFFFUL + +#define FLOW (0x08UL) // R/W +#define FLOW_FCPT_ (0xFFFF0000UL) +#define FLOW_FCPASS_ (0x00000004UL) +#define FLOW_FCEN_ (0x00000002UL) +#define FLOW_FCBSY_ (0x00000001UL) + +#define VLAN1 (0x09UL) // R/W mask 0x0000FFFFUL +#define VLAN2 (0x0AUL) // R/W mask 0x0000FFFFUL + +#define WUFF (0x0BUL) // WO + +#define WUCSR (0x0CUL) // R/W +#define WUCSR_GUE_ (0x00000200UL) +#define WUCSR_WUFR_ (0x00000040UL) +#define WUCSR_MPR_ (0x00000020UL) +#define WUCSR_WAKE_EN_ (0x00000004UL) +#define WUCSR_MPEN_ (0x00000002UL) + +#define COE_CR 0xDUL +#define TX_COE_EN 0x00010000UL +#define RX_COE_MODE 0x00000002UL +#define RX_COE_EN 0x00000001UL + + +bool Mac_Initialize(PPRIVATE_DATA privateData); +static bool MacNotBusy(PPRIVATE_DATA privateData,VL_KEY keyCode); +u32 Mac_GetRegDW(PPRIVATE_DATA privateData,u32 dwRegOffset,VL_KEY keyCode); +void Mac_SetRegDW(PPRIVATE_DATA privateData,u32 dwRegOffset,u32 dwVal,VL_KEY keyCode); + +/* + **************************************************************************** + * Chip Specific MII Defines + **************************************************************************** + * + * Phy register offsets and bit definitions + * + */ +#define LAN9118_PHY_ID (0x00C0001C) + +#define PHY_BCR ((u32)0U) +#define PHY_BCR_RESET_ ((WORD)0x8000U) +#define PHY_BCR_LOOPBACK_ ((WORD)0x4000U) +#define PHY_BCR_SPEED_SELECT_ ((WORD)0x2000U) +#define PHY_BCR_AUTO_NEG_ENABLE_ ((WORD)0x1000U) +#define PHY_BCR_RESTART_AUTO_NEG_ ((WORD)0x0200U) +#define PHY_BCR_DUPLEX_MODE_ ((WORD)0x0100U) + +#define PHY_BSR ((u32)1U) +#define PHY_BSR_LINK_STATUS_ ((WORD)0x0004U) +#define PHY_BSR_REMOTE_FAULT_ ((WORD)0x0010U) +#define PHY_BSR_AUTO_NEG_COMP_ ((WORD)0x0020U) + +#define PHY_ID_1 ((u32)2U) +#define PHY_ID_2 ((u32)3U) + +#define PHY_ANEG_ADV ((u32)4U) +#define PHY_ANEG_ADV_PAUSE_ ((WORD)0x0C00) +#define PHY_ANEG_ADV_ASYMP_ ((WORD)0x0800) +#define PHY_ANEG_ADV_SYMP_ ((WORD)0x0400) +#define PHY_ANEG_ADV_10H_ ((WORD)0x20) +#define PHY_ANEG_ADV_10F_ ((WORD)0x40) +#define PHY_ANEG_ADV_100H_ ((WORD)0x80) +#define PHY_ANEG_ADV_100F_ ((WORD)0x100) +#define PHY_ANEG_ADV_SPEED_ ((WORD)0x1E0) + +#define PHY_ANEG_LPA ((u32)5U) +#define PHY_ANEG_LPA_ASYMP_ ((WORD)0x0800) +#define PHY_ANEG_LPA_SYMP_ ((WORD)0x0400) +#define PHY_ANEG_LPA_100FDX_ ((WORD)0x0100) +#define PHY_ANEG_LPA_100HDX_ ((WORD)0x0080) +#define PHY_ANEG_LPA_10FDX_ ((WORD)0x0040) +#define PHY_ANEG_LPA_10HDX_ ((WORD)0x0020) + +#define PHY_MODE_CTRL_STS ((u32)17) // Mode Control/Status Register +#define MODE_CTRL_STS_FASTRIP_ ((WORD)0x4000U) +#define MODE_CTRL_STS_EDPWRDOWN_ ((WORD)0x2000U) +#define MODE_CTRL_STS_LOWSQEN_ ((WORD)0x0800U) +#define MODE_CTRL_STS_MDPREBP_ ((WORD)0x0400U) +#define MODE_CTRL_STS_FARLOOPBACK_ ((WORD)0x0200U) +#define MODE_CTRL_STS_FASTEST_ ((WORD)0x0100U) +#define MODE_CTRL_STS_REFCLKEN_ ((WORD)0x0010U) +#define MODE_CTRL_STS_PHYADBP_ ((WORD)0x0008U) +#define MODE_CTRL_STS_FORCE_G_LINK_ ((WORD)0x0004U) +#define MODE_CTRL_STS_ENERGYON_ ((WORD)0x0002U) + +#define SPECIAL_CTRL_STS ((u32)27) +#define SPECIAL_CTRL_STS_OVRRD_AMDIX_ ((WORD)0x8000U) +#define SPECIAL_CTRL_STS_AMDIX_ENABLE_ ((WORD)0x4000U) +#define SPECIAL_CTRL_STS_AMDIX_STATE_ ((WORD)0x2000U) + +#define PHY_INT_SRC ((u32)29) +#define PHY_INT_SRC_ENERGY_ON_ ((WORD)0x0080U) +#define PHY_INT_SRC_ANEG_COMP_ ((WORD)0x0040U) +#define PHY_INT_SRC_REMOTE_FAULT_ ((WORD)0x0020U) +#define PHY_INT_SRC_LINK_DOWN_ ((WORD)0x0010U) + +#define PHY_INT_MASK ((u32)30) +#define PHY_INT_MASK_ENERGY_ON_ ((WORD)0x0080U) +#define PHY_INT_MASK_ANEG_COMP_ ((WORD)0x0040U) +#define PHY_INT_MASK_REMOTE_FAULT_ ((WORD)0x0020U) +#define PHY_INT_MASK_LINK_DOWN_ ((WORD)0x0010U) + +#define PHY_SPECIAL ((u32)31) +#define PHY_SPECIAL_SPD_ ((WORD)0x001CU) +#define PHY_SPECIAL_SPD_10HALF_ ((WORD)0x0004U) +#define PHY_SPECIAL_SPD_10FULL_ ((WORD)0x0014U) +#define PHY_SPECIAL_SPD_100HALF_ ((WORD)0x0008U) +#define PHY_SPECIAL_SPD_100FULL_ ((WORD)0x0018U) + +#define AMDIX_DISABLE_STRAIGHT ((WORD)0x0U) +#define AMDIX_DISABLE_CROSSOVER ((WORD)0x01U) +#define AMDIX_ENABLE ((WORD)0x02U) + +bool Phy_Initialize( + PPRIVATE_DATA privateData, + u32 dwPhyAddress, + u32 dwLinkMode); +void Phy_SetLink(PPRIVATE_DATA privateData, + u32 dwLinkRequest); +WORD Phy_GetRegW( + PPRIVATE_DATA privateData, + u32 dwRegIndex, + VL_KEY keyCode); +void Phy_SetRegW( + PPRIVATE_DATA privateData, + u32 dwRegIndex, + WORD wVal, + VL_KEY keyCode); +void Phy_UpdateLinkMode( + PPRIVATE_DATA privateData); +void Phy_GetLinkMode( + PPRIVATE_DATA privateData, + VL_KEY keyCode); +void Phy_CheckLink(unsigned long ptr); +void Phy_SetAutoMdixSts(PPRIVATE_DATA privateData, + WORD wAutoMdixSts); +void Phy_GetAutoMdixSts(PPRIVATE_DATA privateData); + + + + + +TIME_SPAN Gpt_FreeRunCompare(u32 time1,u32 time2); +void Gpt_ScheduleInterrupt(PPRIVATE_DATA privateData,TIME_SPAN timeSpan); +void Gpt_CancelInterrupt(PPRIVATE_DATA privateData); +void Gpt_CancelCallBack( + PPRIVATE_DATA privateData, + void (*callBackFunction)(PPRIVATE_DATA privateData)); +void Gpt_ScheduleCallBack( + PPRIVATE_DATA privateData, + void (*callBackFunction)(PPRIVATE_DATA privateData), + u32 callBackTime);//100uS units relative to now +bool Gpt_HandleInterrupt( + PPRIVATE_DATA privateData,u32 dwIntSts); +void GptCB_RxCompleteMulticast(PPRIVATE_DATA privateData); +void GptCB_RestartBurst(PPRIVATE_DATA privateData); +void GptCB_MeasureRxThroughput(PPRIVATE_DATA privateData); + +void Tx_Initialize( + PPRIVATE_DATA privateData, + u32 dwTxDmaCh, + u32 dwTxDmaThreshold); +void Tx_SendSkb( + PPRIVATE_DATA privateData, + struct sk_buff *skb); +bool Tx_HandleInterrupt( + PPRIVATE_DATA privateData,u32 dwIntSts); + +void Tx_StopQueue( + PPRIVATE_DATA privateData,u32 dwSource); +void Tx_WakeQueue( + PPRIVATE_DATA privateData,u32 dwSource); + +static u32 Tx_GetTxStatusCount( + PPRIVATE_DATA privateData); +static u32 Tx_CompleteTx( + PPRIVATE_DATA privateData); +void Tx_UpdateTxCounters( + PPRIVATE_DATA privateData); + +void Tx_CompleteDma( + PPRIVATE_DATA privateData); + +void CalculateTxChecksumOffset( + struct sk_buff *skb, + int *csum_start_offset); + +void rkdump(unsigned char *p, unsigned short len); + +void Rx_Initialize( + PPRIVATE_DATA privateData, + u32 dwRxDmaCh, + u32 dwDmaThreshold); + +void Rx_CompleteMulticastUpdate (PPRIVATE_DATA privateData); +static void Rx_HandleOverrun(PPRIVATE_DATA privateData); +static void Rx_HandOffSkb( + PPRIVATE_DATA privateData, + struct sk_buff *skb); +static u32 Rx_PopRxStatus( + PPRIVATE_DATA privateData); +void Rx_CountErrors(PPRIVATE_DATA privateData,u32 dwRxStatus); +void Rx_FastForward(PPRIVATE_DATA privateData,u32 dwDwordCount); +void Rx_ProcessPackets(PPRIVATE_DATA privateData); +void Rx_BeginMulticastUpdate (PPRIVATE_DATA privateData); + +unsigned long Rx_TaskletParameter=0; + +void Rx_ProcessPacketsTasklet(unsigned long data); +DECLARE_TASKLET(Rx_Tasklet,Rx_ProcessPacketsTasklet,0); + +#ifdef LINUX_2_6_OR_NEWER +int Smsc9118_rx_poll(struct net_device *dev,int * budget); +#endif + +bool RxStop_HandleInterrupt( + PPRIVATE_DATA privateData, + u32 dwIntSts); +bool Rx_HandleInterrupt( + PPRIVATE_DATA privateData, + u32 dwIntSts); +static u32 Rx_Hash(BYTE addr[6]); + +void Rx_SetMulticastList( + struct net_device *dev); +void Rx_ReceiverOff( + PPRIVATE_DATA privateData); +void Rx_ReceiverOn( + PPRIVATE_DATA privateData, VL_KEY callerKeyCode); + + +void Eeprom_EnableAccess(PPRIVATE_DATA privateData); +void Eeprom_DisableAccess(PPRIVATE_DATA privateData); + +bool Eeprom_IsMacAddressLoaded(PPRIVATE_DATA privateData); +bool Eeprom_IsBusy(PPRIVATE_DATA privateData); +bool Eeprom_Timeout(PPRIVATE_DATA privateData); + +bool Eeprom_ReadLocation( + PPRIVATE_DATA privateData,BYTE address, BYTE * data); +bool Eeprom_EnableEraseAndWrite( + PPRIVATE_DATA privateData); +bool Eeprom_DisableEraseAndWrite( + PPRIVATE_DATA privateData); +bool Eeprom_WriteLocation( + PPRIVATE_DATA privateData,BYTE address,BYTE data); +bool Eeprom_EraseAll( + PPRIVATE_DATA privateData); +bool Eeprom_Reload( + PPRIVATE_DATA privateData); + +bool Eeprom_SaveMacAddress( + PPRIVATE_DATA privateData, + u32 dwHi16,u32 dwLo32); + + +#define OLD_REGISTERS(privData) (((privData->dwIdRev)==0x01180000UL)&& \ + ((privData->dwFpgaRev)>=0x01)&& \ + ((privData->dwFpgaRev)<=0x25)) + +extern volatile u32 g_GpioSetting; +#define GP_0 (0x01UL) +#define GP_1 (0x02UL) +#define GP_2 (0x04UL) +#define GP_3 (0x08UL) +#define GP_4 (0x10UL) +#define GP_OFF (0x00UL) +#define GP_ISR GP_OFF +#define GP_RX GP_OFF +#define GP_TX GP_OFF +#define GP_BEGIN_MULTICAST_UPDATE GP_OFF +#define GP_COMPLETE_MULTICAST_UPDATE GP_OFF + +#define SET_GPIO(gpioBit) \ + if(debug_mode&0x04UL) { \ + g_GpioSetting|=gpioBit; \ + Lan_SetRegDW(GPIO_CFG,g_GpioSetting); \ + } + +#define CLEAR_GPIO(gpioBit) \ + if(debug_mode&0x04UL) { \ + g_GpioSetting&=(~gpioBit); \ + Lan_SetRegDW(GPIO_CFG,g_GpioSetting); \ + } + +#define PULSE_GPIO(gpioBit,count) \ + if(debug_mode&0x04UL) { \ + u32 pulseNum=0; \ + /*make first pulse longer */ \ + SET_GPIO(gpioBit); \ + while(pulseNum init_module()"); + SMSC_TRACE("Compiled: %s, %s",__DATE__,__TIME__); + SMSC_TRACE("Platform: %s",PLATFORM_NAME); + SMSC_TRACE("Driver Parameters"); + + if(lan_base==0UL) { + SMSC_TRACE(" lan_base = 0x%08X, driver will decide",lan_base); + } else { + SMSC_TRACE(" lan_base = 0x%08X",lan_base); + } + if((bus_width==16UL)||(bus_width==32UL)) { + SMSC_TRACE(" bus_width = %d",bus_width); + } else { + SMSC_TRACE(" bus_width = %d, driver will autodetect",bus_width); + } + if(link_mode>0x7FUL) { + SMSC_WARNING(" link_mode = %d, Unknown",link_mode); + link_mode=0x7FUL; + SMSC_WARNING(" resetting link_mode to %d, 100FD,100HD,10FD,10HD,ASYMP,SYMP,ANEG",link_mode); + } else if(link_mode==0UL) { + SMSC_TRACE(" link_mode = %d, LINK_OFF",link_mode); + } else { + SMSC_TRACE(" link_mode = 0x%X, %s,%s,%s,%s,%s,%s,%s", + link_mode, + (link_mode&LINK_SPEED_10HD)?"10HD":"", + (link_mode&LINK_SPEED_10FD)?"10FD":"", + (link_mode&LINK_SPEED_100HD)?"100HD":"", + (link_mode&LINK_SPEED_100FD)?"100FD":"", + (link_mode&LINK_ASYMMETRIC_PAUSE)?"ASYMP":"", + (link_mode&LINK_SYMMETRIC_PAUSE)?"SYMP":"", + (link_mode&LINK_AUTO_NEGOTIATE)?"ANEG":""); + } + SMSC_TRACE( " irq = %d",irq); + if(int_deas!=0xFFFFFFFFUL) { + if(int_deas>0xFFUL) { + SMSC_WARNING(" int_deas = %d, too high",int_deas); + int_deas=0xFFFFFFFFUL; + SMSC_WARNING(" resetting int_deas to %d",int_deas); + } + } + if(int_deas==0xFFFFFFFFUL) { + SMSC_TRACE( " int_deas = 0x%08X, use platform default",int_deas); + } else { + SMSC_TRACE( " int_deas = %d, %duS",int_deas,(unsigned int)(10UL*int_deas)); + } + if(irq_pol) { + SMSC_TRACE(" irq_pol = %d, IRQ output is active high",irq_pol); + } else { + SMSC_TRACE(" irq_pol = %d, IRQ output is active low",irq_pol); + } + if(irq_type) { + SMSC_TRACE(" irq_type = %d, IRQ output is Push-Pull driver",irq_type); + } else { + SMSC_TRACE(" irq_type = %d, IRQ output is Open-Drain buffer",irq_type); + } + if(rx_dma0x000E0000UL) { + SMSC_WARNING("tx_fif_sz = 0x%08X is too high",tx_fif_sz); + tx_fif_sz=0x000E0000UL; + SMSC_WARNING(" resetting tx_fif_sz to 0x%08X",tx_fif_sz); + } + if(tx_fif_sz<0x00020000UL) { + SMSC_WARNING("tx_fif_sz = 0x%08X is too low",tx_fif_sz); + tx_fif_sz=0x00020000UL; + SMSC_WARNING(" resetting tx_fif_sz to 0x%08X",tx_fif_sz); + } + SMSC_TRACE( " tx_fif_sz = 0x%08X",tx_fif_sz); + if(afc_cfg==0xFFFFFFFFUL) { + SMSC_TRACE(" afc_cfg = 0x%08X, driver will decide",afc_cfg); + } else { + if(afc_cfg&0xFF000000UL) { + SMSC_WARNING("afc_cfg = 0x%08X is invalid",afc_cfg); + afc_cfg&=0xFFFFFFFFUL; + SMSC_WARNING(" resetting to afc_cfg = 0x%08X, driver will decide",afc_cfg); + } else { + SMSC_TRACE( + " afc_cfg = 0x%08X",afc_cfg); + } + } + if(rx_mode==PROCESSING_MODE_TASKLET) { + SMSC_TRACE(" rx_mode = 0x%08X, Tasklets enabled",rx_mode); + } else if(rx_mode==PROCESSING_MODE_NAPI) { +#ifndef LINUX_2_6_OR_NEWER + SMSC_WARNING(" rx_mode = 0x%08X requires Linux 2.6 or newer", rx_mode); + rx_mode=PROCESSING_MODE_TASKLET; + SMSC_WARNING(" resetting to rx_mode = 0x%08X, Tasklets enabled", rx_mode); +#else + SMSC_TRACE(" rx_mode = 0x%08X, NAPI enabled",rx_mode); +#endif + } else { + SMSC_TRACE(" rx_mode = 0, use ISR"); + } + + if(phy_addr==0xFFFFFFFFUL) { + SMSC_TRACE(" phy_addr = 0xFFFFFFFF, Use internal phy"); + } else if(phy_addr<=31UL) { + SMSC_TRACE(" phy_addr = 0x%08X, use this address for external phy",phy_addr); + } else { + SMSC_TRACE(" phy_addr = 0x%08X, auto detect external phy",phy_addr); + } + if(max_throughput) { + SMSC_TRACE(" max_throughput = 0x%08X, Use platform default",max_throughput); + } else { + SMSC_TRACE(" max_throughput = 0x%08X",max_throughput); + } + if(max_packet_count) { + SMSC_TRACE(" max_packet_count = 0x%08X, Use platform default",max_packet_count); + } else { + SMSC_TRACE(" max_packet_count = 0x%08X",max_packet_count); + } + if(packet_cost) { + SMSC_TRACE(" packet_cost = 0x%08X, Use platform default",packet_cost); + } else { + SMSC_TRACE(" packet_cost = 0x%08X",packet_cost); + } + if(burst_period) { + SMSC_TRACE(" burst_period = 0x%08X, Use platform default",burst_period); + } else { + SMSC_TRACE(" burst_period = 0x%08X",burst_period); + } + if(max_work_load) { + SMSC_TRACE(" max_work_load = 0x%08X, Use platform default",max_work_load); + } else { + SMSC_TRACE(" max_work_load = 0x%08X",max_work_load); + } + + SMSC9118 = alloc_netdev_mq(0, "eth%d", Smsc9118_init, 1); + SMSC_TRACE(" alloc_netdev complete. SMSC9118 = 0x%08X\n", (u32)SMSC9118); + result=register_netdev(SMSC9118); + if(result) { + SMSC_WARNING("error %i registering device",result); + } else { + device_present=1; + SMSC_TRACE(" Interface Name = \"%s\"",SMSC9118->name); + } + result=result;//make lint happy + SMSC_TRACE("<-- init_module()"); + return device_present ? 0 : -ENODEV; +} + +void Smsc9118_cleanup_module(void) +{ + SMSC_TRACE("--> cleanup_module()"); + if(SMSC9118->ml_priv!=NULL) { + PPRIVATE_DATA privateData=(PPRIVATE_DATA)SMSC9118->ml_priv; + PPLATFORM_DATA platformData=(PPLATFORM_DATA)&(privateData->PlatformData); + Platform_CleanUp(platformData); + kfree(SMSC9118->ml_priv); + SMSC9118->ml_priv=NULL; + } + unregister_netdev(SMSC9118); + SMSC_TRACE("<-- cleanup_module()"); +} + +void Smsc9118_init(struct net_device *dev) +{ + u32 dwLanBase=0UL; + u32 dwIdRev=0UL; + u32 dwFpgaRev=0UL; + // WORD SpecialCtrlSts=0U; + PPRIVATE_DATA privateData=NULL; + PPLATFORM_DATA platformData=NULL; + bool platformInitialized=false; + int result=-ENODEV; + + int i; + bool acquired_mem_region=false; + bool acquired_isr=false; + + SMSC_TRACE("-->Smsc9118_init(dev=0x%08X)",(u32)dev); + + if(dev==NULL) { + SMSC_WARNING("Smsc9118_init(dev==NULL)"); + result=-EFAULT; + goto DONE; + } + + if(dev->ml_priv!=NULL) { + SMSC_WARNING("dev->ml_priv!=NULL, going to overwrite pointer"); + } + dev->ml_priv=kmalloc(sizeof(PRIVATE_DATA),GFP_KERNEL); + if(dev->ml_priv==NULL) { + SMSC_WARNING("Unable to allocate PRIVATE_DATA"); + result=-ENOMEM; + goto DONE; + } + memset(dev->ml_priv,0,sizeof(PRIVATE_DATA)); + privateData=(PPRIVATE_DATA)(dev->ml_priv); + platformData=&(privateData->PlatformData); + + dwLanBase=Platform_Initialize( + platformData, + lan_base,bus_width); + + if(dwLanBase==0UL) { + SMSC_WARNING("dwLanBase==0x00000000"); + result=-ENODEV; + goto DONE; + } + platformInitialized=true; + SMSC_TRACE("dwLanBase=0x%08X",dwLanBase); + + if(check_mem_region(dwLanBase,LAN_REGISTER_EXTENT)!=0) { + SMSC_WARNING(" Memory Region specified (0x%08X to 0x%08X) is not available.", + dwLanBase,(u32)(dwLanBase+LAN_REGISTER_EXTENT-1UL)); + result=-ENOMEM; + goto DONE; + } + + privateData->dwLanBase=dwLanBase; + dwIdRev=Lan_GetRegDW(ID_REV); + if(HIWORD(dwIdRev)==LOWORD(dwIdRev)) { + //this may mean the chip is set for 32 bit + // while the bus is reading as 16 bit +UNKNOWN_CHIP: + SMSC_WARNING(" LAN9118 Family NOT Identified, dwIdRev==0x%08X",dwIdRev); + result=-ENODEV; + goto DONE; + } + switch(dwIdRev&0xFFFF0000UL) { + + case 0x93120000UL: + if (Scatter_gather | tx_Csum | rx_Csum) + SMSC_TRACE("This chip doesn't support checksum offload!!! Will use nonchecksum offload by default"); + privateData->UseScatterGather=false; + privateData->UseTxCsum=false; + privateData->UseRxCsum=false; + + switch(dwIdRev&0x0000FFFFUL) { + case 1UL: + SMSC_TRACE(" Hydra identified, dwIdRev==0x%08X",dwIdRev); + privateData->dwGeneration=3; + break; + default: + SMSC_TRACE(" Hydra identified (NEW), dwIdRev==0x%08X",dwIdRev); + privateData->dwGeneration=3; + break; + };break; + + + case 0x01180000UL: + if (Scatter_gather | tx_Csum | rx_Csum) + SMSC_TRACE("This chip doesn't support checksum offload!!! Will use nonchecksum offload by default"); + privateData->UseScatterGather=false; + privateData->UseTxCsum=false; + privateData->UseRxCsum=false; + + switch(dwIdRev&0x0000FFFFUL) { + case 0UL: + SMSC_TRACE(" LAN9118 Beacon identified, dwIdRev==0x%08X",dwIdRev); + privateData->dwGeneration=0; + break; + case 1UL: + SMSC_TRACE(" LAN9118 Concord A0 identified, dwIdRev==0x%08X",dwIdRev); + privateData->dwGeneration=1; + break; + case 2UL: + SMSC_TRACE(" LAN9118 Concord A1 identified, dwIdRev==0x%08X",dwIdRev); + privateData->dwGeneration=2; + break; + default: + SMSC_TRACE(" LAN9118 Concord A1 identified (NEW), dwIdRev==0x%08X",dwIdRev); + privateData->dwGeneration=2; + break; + };break; + + case 0x01170000UL: + if (Scatter_gather | tx_Csum | rx_Csum) + SMSC_TRACE("This chip doesn't support checksum offload!!! Will use nonchecksum offload by default"); + privateData->UseScatterGather=false; + privateData->UseTxCsum=false; + privateData->UseRxCsum=false; + + switch(dwIdRev&0x0000FFFFUL) { + case 0UL: + SMSC_TRACE(" LAN9117 Beacon identified, dwIdRev==0x%08X",dwIdRev); + privateData->dwGeneration=0; + break; + case 1UL: + SMSC_TRACE(" LAN9117 Concord A0 identified, dwIdRev==0x%08X",dwIdRev); + privateData->dwGeneration=1; + break; + case 2UL: + SMSC_TRACE(" LAN9117 Concord A1 identified, dwIdRev==0x%08X",dwIdRev); + privateData->dwGeneration=2; + break; + default: + SMSC_TRACE(" LAN9117 Concord A1 identified (NEW), dwIdRev==0x%08X",dwIdRev); + privateData->dwGeneration=2; + break; + };break; + + case 0x01160000UL: + if (Scatter_gather | tx_Csum | rx_Csum) + SMSC_TRACE("This chip doesn't support checksum offload!!! Will use nonchecksum offload by default"); + privateData->UseScatterGather=false; + privateData->UseTxCsum=false; + privateData->UseRxCsum=false; + + switch(dwIdRev&0x0000FFFFUL) { + case 0UL: + goto UNKNOWN_CHIP; + case 1UL: + SMSC_TRACE(" LAN9116 Concord A0 identified, dwIdRev==0x%08X",dwIdRev); + privateData->dwGeneration=1; + break; + case 2UL: + SMSC_TRACE(" LAN9116 Concord A1 identified, dwIdRev==0x%08X",dwIdRev); + privateData->dwGeneration=2; + break; + default: + SMSC_TRACE(" LAN9116 Concord A1 identified (NEW), dwIdRev==0x%08X",dwIdRev); + privateData->dwGeneration=2; + break; + };break; + + case 0x01150000UL: + if (Scatter_gather | tx_Csum | rx_Csum) + SMSC_TRACE("This chip doesn't support checksum offload!!! Will use nonchecksum offload by default"); + privateData->UseScatterGather=false; + privateData->UseTxCsum=false; + privateData->UseRxCsum=false; + + switch(dwIdRev&0x0000FFFFUL) { + case 0UL: + goto UNKNOWN_CHIP; + case 1UL: + SMSC_TRACE(" LAN9115 Concord A0 identified, dwIdRev==0x%08X",dwIdRev); + privateData->dwGeneration=1; + break; + case 2UL: + SMSC_TRACE(" LAN9115 Concord A1 identified, dwIdRev==0x%08X",dwIdRev); + privateData->dwGeneration=2; + break; + default: + SMSC_TRACE(" LAN9115 Concord A1 identified (NEW), dwIdRev==0x%08X",dwIdRev); + privateData->dwGeneration=2; + break; + };break; + + case 0x118A0000UL: + if (Scatter_gather | tx_Csum | rx_Csum) + SMSC_TRACE("This chip doesn't support checksum offload!!! Will use nonchecksum offload by default"); + privateData->UseScatterGather=false; + privateData->UseTxCsum=false; + privateData->UseRxCsum=false; + + switch(dwIdRev&0x0000FFFFUL) { + case 0UL: + SMSC_TRACE(" LAN9218 Boylston identified, dwIdRev==0x%08X",dwIdRev); + privateData->dwGeneration=3; + break; + default: + SMSC_TRACE(" LAN9218 Boylston identified (NEW), dwIdRev==0x%08X",dwIdRev); + privateData->dwGeneration=3; + break; + };break; + + case 0x117A0000UL: + if (Scatter_gather | tx_Csum | rx_Csum) + SMSC_TRACE("This chip doesn't support checksum offload!!! Will use nonchecksum offload by default"); + privateData->UseScatterGather=false; + privateData->UseTxCsum=false; + privateData->UseRxCsum=false; + + switch(dwIdRev&0x0000FFFFUL) { + case 0UL: + SMSC_TRACE(" LAN9217 Boylston identified, dwIdRev==0x%08X",dwIdRev); + privateData->dwGeneration=3; + break; + default: + SMSC_TRACE(" LAN9217 Boylston identified (NEW), dwIdRev==0x%08X",dwIdRev); + privateData->dwGeneration=3; + break; + };break; + + case 0x116A0000UL: + if (Scatter_gather | tx_Csum | rx_Csum) + SMSC_TRACE("This chip doesn't support checksum offload!!! Will use nonchecksum offload by default"); + privateData->UseScatterGather=false; + privateData->UseTxCsum=false; + privateData->UseRxCsum=false; + + switch(dwIdRev&0x0000FFFFUL) { + case 0UL: + SMSC_TRACE(" LAN9216 Boylston identified, dwIdRev==0x%08X",dwIdRev); + privateData->dwGeneration=3; + break; + default: + SMSC_TRACE(" LAN9216 Boylston identified (NEW), dwIdRev==0x%08X",dwIdRev); + privateData->dwGeneration=3; + break; + };break; + + case 0x115A0000UL: + if (Scatter_gather | tx_Csum | rx_Csum) + SMSC_TRACE("This chip doesn't support checksum offload!!! Will use nonchecksum offload by default"); + privateData->UseScatterGather=false; + privateData->UseTxCsum=false; + privateData->UseRxCsum=false; + + switch(dwIdRev&0x0000FFFFUL) { + case 0UL: + SMSC_TRACE(" LAN9215 Boylston identified, dwIdRev==0x%08X",dwIdRev); + privateData->dwGeneration=3; + break; + default: + SMSC_TRACE(" LAN9215 Boylston identified (NEW), dwIdRev==0x%08X",dwIdRev); + privateData->dwGeneration=3; + break; + };break; + + + case 0x92100000UL: + privateData->UseScatterGather=Scatter_gather; + privateData->UseTxCsum=tx_Csum; + privateData->UseRxCsum=rx_Csum; + if (Scatter_gather) + SMSC_TRACE(" Tx Scatter-Gather"); + if (tx_Csum) + SMSC_TRACE(" Tx HW Checksum"); + if (rx_Csum) + SMSC_TRACE(" Rx HW Checksum"); + + switch(dwIdRev&0x0000FFFFUL) { + case 0UL: + SMSC_TRACE(" LAN9210 Boylston Lite identified, dwIdRev==0x%08X",dwIdRev); + privateData->dwGeneration=4; + break; + + default: + SMSC_TRACE(" LAN9210 Boylston Lite identified (NEW), dwIdRev==0x%08X",dwIdRev); + privateData->dwGeneration=4; + break; + };break; + + case 0x92110000UL: + privateData->UseScatterGather=Scatter_gather; + privateData->UseTxCsum=tx_Csum; + privateData->UseRxCsum=rx_Csum; + if (Scatter_gather) + SMSC_TRACE(" Tx Scatter-Gather"); + if (tx_Csum) + SMSC_TRACE(" Tx HW Checksum"); + if (rx_Csum) + SMSC_TRACE(" Rx HW Checksum"); + + switch(dwIdRev&0x0000FFFFUL) { + case 0UL: + SMSC_TRACE(" LAN9211 Boylston Lite identified, dwIdRev==0x%08X",dwIdRev); + privateData->dwGeneration=4; + break; + + default: + SMSC_TRACE(" LAN9211 Boylston Lite identified (NEW), dwIdRev==0x%08X",dwIdRev); + privateData->dwGeneration=4; + break; + };break; + + case 0x215A0000UL: + privateData->UseScatterGather=Scatter_gather; + privateData->UseTxCsum=tx_Csum; + privateData->UseRxCsum=rx_Csum; + if (Scatter_gather) + SMSC_TRACE(" Tx Scatter-Gather"); + if (tx_Csum) + SMSC_TRACE(" Tx HW Checksum"); + if (rx_Csum) + SMSC_TRACE(" Rx HW Checksum"); + + switch(dwIdRev&0x0000FFFFUL) { + case 0UL: + SMSC_TRACE(" LAN9215A Boylston Auto identified, dwIdRev==0x%08X",dwIdRev); + privateData->dwGeneration=4; + break; + + default: + SMSC_TRACE(" LAN9215A Boylston Auto identified (NEW), dwIdRev==0x%08X",dwIdRev); + privateData->dwGeneration=4; + break; + };break; + + case 0x216A0000UL: + privateData->UseScatterGather=Scatter_gather; + privateData->UseTxCsum=tx_Csum; + privateData->UseRxCsum=rx_Csum; + if (Scatter_gather) + SMSC_TRACE(" Tx Scatter-Gather"); + if (tx_Csum) + SMSC_TRACE(" Tx HW Checksum"); + if (rx_Csum) + SMSC_TRACE(" Rx HW Checksum"); + + switch(dwIdRev&0x0000FFFFUL) { + case 0UL: + SMSC_TRACE(" LAN9216A Boylston Auto identified, dwIdRev==0x%08X",dwIdRev); + privateData->dwGeneration=4; + break; + + default: + SMSC_TRACE(" LAN9216A Boylston Auto identified (NEW), dwIdRev==0x%08X",dwIdRev); + privateData->dwGeneration=4; + break; + };break; + + case 0x217A0000UL: + privateData->UseScatterGather=Scatter_gather; + privateData->UseTxCsum=tx_Csum; + privateData->UseRxCsum=rx_Csum; + if (Scatter_gather) + SMSC_TRACE(" Tx Scatter-Gather"); + if (tx_Csum) + SMSC_TRACE(" Tx HW Checksum"); + if (rx_Csum) + SMSC_TRACE(" Rx HW Checksum"); + + switch(dwIdRev&0x0000FFFFUL) { + case 0UL: + SMSC_TRACE(" LAN9217A Boylston Auto identified, dwIdRev==0x%08X",dwIdRev); + privateData->dwGeneration=4; + break; + + default: + SMSC_TRACE(" LAN9217A Boylston Auto identified (NEW), dwIdRev==0x%08X",dwIdRev); + privateData->dwGeneration=4; + break; + };break; + + + case 0x218A0000UL: + privateData->UseScatterGather=Scatter_gather; + privateData->UseTxCsum=tx_Csum; + privateData->UseRxCsum=rx_Csum; + if (Scatter_gather) + SMSC_TRACE(" Tx Scatter-Gather"); + if (tx_Csum) + SMSC_TRACE(" Tx HW Checksum"); + if (rx_Csum) + SMSC_TRACE(" Rx HW Checksum"); + + switch(dwIdRev&0x0000FFFFUL) { + case 0UL: + SMSC_TRACE(" LAN9218A Boylston Auto identified, dwIdRev==0x%08X",dwIdRev); + privateData->dwGeneration=4; + break; + + default: + SMSC_TRACE(" LAN9218A Boylston Auto identified (NEW), dwIdRev==0x%08X",dwIdRev); + privateData->dwGeneration=4; + break; + };break; + + default: + //This is used for the new unkonw chip before we formally add them in the driver + if (id_reg==dwIdRev) { + if (Csum_Support) { + privateData->UseScatterGather=Scatter_gather; + privateData->UseTxCsum=tx_Csum; + privateData->UseRxCsum=rx_Csum; + } else { + SMSC_TRACE("This chip doesn't support checksum offload!!! Will use nonchecksum offload by default"); + privateData->UseScatterGather=false; + privateData->UseTxCsum=false; + privateData->UseRxCsum=false; + } + + SMSC_TRACE(" New Chip identified, dwIdRev==0x%08X",dwIdRev); + privateData->dwGeneration=5; + + } else { + + SMSC_WARNING("unknow chip, dwIdRev==0x%08X",dwIdRev); + + }; break; + + + } + + //printk("dwGeneration = %d\n", privateData->dwGeneration); + + dwFpgaRev=Lan_GetRegDW(FPGA_REV); + SMSC_TRACE(" FPGA_REV == 0x%08X",dwFpgaRev); + + + ether_setup(dev); + dev->open= Smsc9118_open; + dev->stop= Smsc9118_stop; + dev->hard_start_xmit= Smsc9118_hard_start_xmit; + dev->get_stats= Smsc9118_get_stats; + dev->do_ioctl= Smsc9118_do_ioctl; + dev->set_multicast_list=Smsc9118_set_multicast_list; + dev->flags|=IFF_MULTICAST; +#ifdef LINUX_2_6_OR_NEWER + /* + if (rx_mode==PROCESSING_MODE_NAPI) { + dev->poll=Smsc9118_rx_poll; + dev->weight=napi_weight; + } + */ +#endif + if(privateData->UseScatterGather) { + + if(privateData->UseTxCsum) + dev->features = (NETIF_F_HW_CSUM | NETIF_F_SG | NETIF_F_FRAGLIST); + else + dev->features = (NETIF_F_SG | NETIF_F_FRAGLIST); // Kernel will turn off SG in this case. + } + + else { + + if(privateData->UseTxCsum) + dev->features = (NETIF_F_HW_CSUM); + else + dev->features = 0; + } + + if(dev==NULL) { + SMSC_WARNING("Smsc9118_open(dev==NULL)"); + result=-EFAULT; + goto DONE; + } + privateData=(PPRIVATE_DATA)(dev->ml_priv); + if(privateData==NULL) { + SMSC_WARNING("Smsc9118_open(privateData==NULL)"); + result=-EFAULT; + goto DONE; + } + platformData=&(privateData->PlatformData); + + for (i = 0; i < GPT_SCHEDULE_DEPTH; i++) { + privateData->GptFunction [i] = NULL; + } + privateData->Gpt_scheduled_slot_index = GPT_SCHEDULE_DEPTH; + + //get memory region + if(check_mem_region(privateData->dwLanBase,LAN_REGISTER_EXTENT)!=0) + { + SMSC_WARNING("Device memory is already in use."); + result=-ENOMEM; + goto DONE; + } + request_mem_region(privateData->dwLanBase,LAN_REGISTER_EXTENT,"SMSC_LAN9118"); + acquired_mem_region=true; + + //initialize the LAN9118 + { + u32 dwIntCfg=0; + if(irq_pol) { + dwIntCfg|=INT_CFG_IRQ_POL_; + } + if(irq_type) { + dwIntCfg|=INT_CFG_IRQ_TYPE_; + } + if(!Lan_Initialize(privateData,dwIntCfg,tx_fif_sz,afc_cfg)) + { + SMSC_WARNING("Failed Lan_Initialize"); + result=-ENODEV; + goto DONE; + } + } + + if(!Platform_RequestIRQ(platformData,irq,Smsc9118_ISR,privateData)) { + result=-ENODEV; + goto DONE; + } + acquired_isr=true; + + //must now test the IRQ connection to the ISR + SMSC_TRACE("Testing ISR using IRQ %d",Platform_CurrentIRQ(platformData)); + { + u32 dwTimeOut=1000000; + Lan_SignalSoftwareInterrupt(privateData); + SMSC_TRACE("privateData=%08X", (u32)privateData); + do { + udelay(10); + dwTimeOut--; + } while((dwTimeOut)&&(!(privateData->SoftwareInterruptSignal))); + if(!(privateData->SoftwareInterruptSignal)) { + SMSC_WARNING("ISR failed signaling test"); + result=-ENODEV; + goto DONE; + } + } + SMSC_TRACE("ISR passed test using IRQ %d",Platform_CurrentIRQ(platformData)); + + if(!Mac_Initialize(privateData)) { + SMSC_WARNING("Failed Mac_Initialize"); + result=-ENODEV; + goto DONE; + } + {//get mac address + u32 dwHigh16=0; + u32 dwLow32=0; + unsigned long dwIntFlags=0; + VL_KEY keyCode=Vl_WaitForLock(&(privateData->MacPhyLock),&dwIntFlags); + if(mac_addr_hi16==0xFFFFFFFF) { + dwHigh16=Mac_GetRegDW(privateData,ADDRH,keyCode); + dwLow32=Mac_GetRegDW(privateData,ADDRL,keyCode); + if((dwHigh16==0x0000FFFFUL)&&(dwLow32==0xFFFFFFFF)) + { + dwHigh16=0x00000070UL; + dwLow32=0x110F8000UL; + Mac_SetRegDW(privateData,ADDRH,dwHigh16,keyCode); + Mac_SetRegDW(privateData,ADDRL,dwLow32,keyCode); + SMSC_TRACE("Mac Address is set by default to 0x%04X%08X", + dwHigh16,dwLow32); + } else { + SMSC_TRACE("Mac Address is read from LAN9118 as 0x%04X%08X", + dwHigh16,dwLow32); + } + } else { + //SMSC_ASSERT((mac_addr_hi16&0xFFFF8000UL)==0); + dwHigh16=mac_addr_hi16; + dwLow32=mac_addr_lo32; + Mac_SetRegDW(privateData,ADDRH,dwHigh16,keyCode); + Mac_SetRegDW(privateData,ADDRL,dwLow32,keyCode); + SMSC_TRACE("Mac Address is set by parameter to 0x%04X%08X", + dwHigh16,dwLow32); + } + Vl_ReleaseLock(&(privateData->MacPhyLock),keyCode,&dwIntFlags); + dev->dev_addr[0]=LOBYTE(LOWORD(dwLow32)); + dev->dev_addr[1]=HIBYTE(LOWORD(dwLow32)); + dev->dev_addr[2]=LOBYTE(HIWORD(dwLow32)); + dev->dev_addr[3]=HIBYTE(HIWORD(dwLow32)); + dev->dev_addr[4]=LOBYTE(LOWORD(dwHigh16)); + dev->dev_addr[5]=HIBYTE(LOWORD(dwHigh16)); + } + + privateData->dwIdRev=dwIdRev; + privateData->dwFpgaRev=dwFpgaRev&(0x000000FFUL); + privateData->dev=dev; + + sprintf(privateData->ifName,"%s","eth1"); + SMSC_TRACE("privateData->ifName = %s\n", privateData->ifName); + result=0; + +DONE: + if(result!=0) { + if(dev!=NULL) { + if(dev->ml_priv!=NULL) { + if(platformInitialized) { + Platform_CleanUp(platformData); + } + kfree(dev->ml_priv); + dev->ml_priv=NULL; + } + } + } + SMSC_TRACE("<--Smsc9118_init(), result=%d",result); +} + +int Smsc9118_open(struct net_device *dev) +{ + int result=-ENODEV; + PPRIVATE_DATA privateData=NULL; + PPLATFORM_DATA platformData=NULL; + bool acquired_mem_region=false; + bool acquired_isr=false; + SMSC_TRACE("-->Smsc9118_open(dev=0x%08X)",(u32)dev); + if(dev==NULL) { + SMSC_WARNING("Smsc9118_open(dev==NULL)"); + result=-EFAULT; + goto DONE; + } + privateData=(PPRIVATE_DATA)(dev->ml_priv); + if(privateData==NULL) { + SMSC_WARNING("Smsc9118_open(privateData==NULL)"); + result=-EFAULT; + goto DONE; + } + platformData=&(privateData->PlatformData); + + privateData->MulticastUpdatePending = false; +#ifdef USE_PHY_WORK_AROUND + netif_carrier_off(dev); + if(!Phy_Initialize( + privateData, + phy_addr, + link_mode)) + { + SMSC_WARNING("Failed to initialize Phy"); + result=-ENODEV; + goto DONE; + } +#endif + + { + u32 dwRxDmaCh=rx_dma; + u32 dwTxDmaCh=tx_dma; + privateData->RxDmaChReserved=false; + + + if(rx_dma==TRANSFER_REQUEST_DMA) { + dwRxDmaCh=Platform_RequestDmaChannel(&(privateData->PlatformData)); + SMSC_ASSERT(dwRxDmaCh!=TRANSFER_REQUEST_DMA); + if(dwRxDmaChRxDmaChReserved=true; + } + } + privateData->TxDmaChReserved=false; + if(tx_dma==TRANSFER_REQUEST_DMA) { + dwTxDmaCh=Platform_RequestDmaChannel(&(privateData->PlatformData)); + SMSC_ASSERT(dwTxDmaCh!=TRANSFER_REQUEST_DMA); + if(dwTxDmaChTxDmaChReserved=true; + } + } + Tx_Initialize(privateData,dwTxDmaCh,dma_threshold); + Rx_Initialize(privateData,dwRxDmaCh,dma_threshold); + + } + +#ifndef LINUX_2_6_OR_NEWER + MOD_INC_USE_COUNT; +#endif + privateData->Running=true; + netif_start_queue(dev); + Tx_StopQueue(privateData,0x01UL); + + + spin_lock_init(&(privateData->GpTimerLock)); + Lan_EnableInterrupt(privateData,INT_EN_GPT_INT_EN_); + +#ifndef USE_PHY_WORK_AROUND + netif_carrier_off(dev); + if(!Phy_Initialize( + privateData, + phy_addr, + link_mode)) + { + SMSC_WARNING("Failed to initialize Phy"); + result=-ENODEV; + goto DONE; + } +#endif + + result=0; + +DONE: + if(result!=0) { +#ifndef LINUX_2_6_OR_NEWER + MOD_DEC_USE_COUNT; +#endif + if(privateData!=NULL) { + if(privateData->TxDmaChReserved) { + Platform_ReleaseDmaChannel(platformData, + privateData->dwTxDmaCh); + privateData->TxDmaChReserved=false; + } + if(privateData->RxDmaChReserved) { + Platform_ReleaseDmaChannel(platformData, + privateData->dwRxDmaCh); + privateData->RxDmaChReserved=false; + } + if(acquired_isr) { + Platform_FreeIRQ(platformData); + } + if(acquired_mem_region) { + release_mem_region( + privateData->dwLanBase, + LAN_REGISTER_EXTENT); + } + } + } + SMSC_TRACE("<--Smsc9118_open, result=%d",result); + return result; +} + +int Smsc9118_stop(struct net_device *dev) +{ + int result=0; + PPRIVATE_DATA privateData=NULL; + SMSC_TRACE("-->Smsc9118_stop(dev=0x%08X)",(u32)dev); + if(dev==NULL) { + SMSC_WARNING("Smsc9118_stop(dev==NULL)"); + result=-EFAULT; + goto DONE; + } + privateData=(PPRIVATE_DATA)(dev->ml_priv); + if(privateData==NULL) { + SMSC_WARNING("Smsc9118_stop(privateData==NULL)"); + result=-EFAULT; + goto DONE; + } + + privateData->StopLinkPolling=true; + del_timer_sync(&(privateData->LinkPollingTimer)); + + Lan_DisableInterrupt(privateData,INT_EN_GPT_INT_EN_); + + Tx_UpdateTxCounters(privateData); + privateData->Running=false; + Lan_DisableIRQ(privateData); + + Tx_CompleteDma(privateData); + + Tx_StopQueue(privateData,0x01UL); + +#ifndef LINUX_2_6_OR_NEWER + MOD_DEC_USE_COUNT; +#endif + + if(privateData->TxDmaChReserved) { + Platform_ReleaseDmaChannel( + &(privateData->PlatformData), + privateData->dwTxDmaCh); + privateData->TxDmaChReserved=false; + } + if(privateData->RxDmaChReserved) { + Platform_ReleaseDmaChannel( + &(privateData->PlatformData), + privateData->dwRxDmaCh); + privateData->RxDmaChReserved=false; + } + + Platform_FreeIRQ(&(privateData->PlatformData)); + release_mem_region(privateData->dwLanBase,LAN_REGISTER_EXTENT); + + { + const u32 dwLanBase=privateData->dwLanBase; + const u32 dwIdRev=privateData->dwIdRev; + const u32 dwFpgaRev=privateData->dwFpgaRev; + struct net_device * const tempDev=privateData->dev; + char ifName[SMSC_IF_NAME_SIZE]; + PLATFORM_DATA platformDataBackup; + memcpy(ifName,privateData->ifName,SMSC_IF_NAME_SIZE); + memcpy(&platformDataBackup,&(privateData->PlatformData),sizeof(PLATFORM_DATA)); + + memset(privateData,0,sizeof(PRIVATE_DATA)); + + privateData->dwLanBase=dwLanBase; + privateData->dwIdRev=dwIdRev; + privateData->dwFpgaRev=dwFpgaRev; + privateData->dev=tempDev; + memcpy(privateData->ifName,ifName,SMSC_IF_NAME_SIZE); + memcpy(&(privateData->PlatformData),&platformDataBackup,sizeof(PLATFORM_DATA)); + } + +DONE: + SMSC_TRACE("<--Smsc9118_stop, result=%d",result); + return result; +} + +int Smsc9118_hard_start_xmit( + struct sk_buff *skb, struct net_device * const dev) +{ + int result=0; + PPRIVATE_DATA privateData=NULL; + //SMSC_TRACE("-->Smsc9118_hard_start_xmit(skb=0x%08X,dev=0x%08X)",(u32)skb,(u32)dev); + if(skb==NULL) { + SMSC_WARNING("Smsc9118_hard_start_xmit(skb==NULL)"); + result=-EFAULT; + goto DONE; + } + if(dev==NULL) { + SMSC_WARNING("Smsc9118_hard_start_xmit(dev==NULL)"); + result=-EFAULT; + goto DONE; + } + if(dev->ml_priv==NULL) { + SMSC_WARNING("Smsc9118_hard_start_xmit(dev->ml_priv==NULL)"); + result=-EFAULT; + goto DONE; + } + privateData=(PPRIVATE_DATA)(dev->ml_priv); + // SET_GPIO(GP_TX); + + Tx_SendSkb(privateData,skb); + + // CLEAR_GPIO(GP_TX); +DONE: + //SMSC_TRACE("<--Smsc9118_hard_start_xmit, result=%d",result); + return result; +} + +struct net_device_stats * Smsc9118_get_stats(struct net_device * const dev) +{ + PPRIVATE_DATA privateData=NULL; + if(dev==NULL) { + SMSC_WARNING("Smsc9118_get_stats(dev==NULL)"); + return NULL; + } + if(dev->ml_priv==NULL) { + // SMSC_WARNING("Smsc9118_get_stats(dev->ml_priv==NULL)"); + return NULL; + } + + privateData=(PPRIVATE_DATA)(dev->ml_priv); + if(privateData->Running) { + privateData->stats.rx_dropped+=Lan_GetRegDW(RX_DROP); + Tx_UpdateTxCounters(privateData); + } + return &(privateData->stats); +} + +void Smsc9118_set_multicast_list(struct net_device *dev) +{ + SMSC_ASSERT(dev!=NULL); + Rx_SetMulticastList(dev); +} + + +int Smsc9118_do_ioctl( + struct net_device *dev, + struct ifreq *ifr, + int cmd) +{ + int result=0; + PPRIVATE_DATA privateData=NULL; + void *userAddr=NULL; + + // bool success=false; + + SMSC_TRACE("-->Smsc9118_do_ioctl"); + SMSC_TRACE("cmd=%d,SIOCGMIIPHY=%d,SIOCDEVPRIVATE=%d", + cmd,SIOCGMIIPHY,SIOCDEVPRIVATE); + + + if(dev==NULL) { + SMSC_WARNING("dev==NULL"); + result=-EFAULT; + goto DONE; + } + if(dev->ml_priv==NULL) { + SMSC_WARNING("dev->ml_priv==NULL"); + result=-EFAULT; + goto DONE; + } + privateData=((PPRIVATE_DATA)dev->ml_priv); + if(ifr==NULL) { + SMSC_WARNING("ifr==NULL"); + result=-EFAULT; + goto DONE; + } + userAddr=ifr->ifr_data; + + + if(privateData->LanInitialized) { + // standard MII IOC's + struct mii_ioctl_data * const data= + (struct mii_ioctl_data *) & ifr->ifr_data; + switch(cmd) { + case SIOCGMIIPHY: + + case SIOCDEVPRIVATE: + data->phy_id=1; + SMSC_TRACE("SIOCGMIIPHY: phy_id set to 0x%04X",data->phy_id); + break; + case SIOCGMIIREG: + case SIOCDEVPRIVATE+1: + { + unsigned long dwIntFlags=0; + VL_KEY keyCode=Vl_WaitForLock(&(privateData->MacPhyLock),&dwIntFlags); + data->val_out=Phy_GetRegW( + privateData,data->reg_num,keyCode); + Vl_ReleaseLock(&(privateData->MacPhyLock),keyCode,&dwIntFlags); + } + SMSC_TRACE("SIOCGMIIREG: phy_id=0x%04X, reg_num=0x%04X, val_out set to 0x%04X", + data->phy_id,data->reg_num,data->val_out); + break; + case SIOCSMIIREG: + case SIOCDEVPRIVATE+2: + SMSC_TRACE("SIOCSMIIREG: phy_id=0x%04X, reg_num=0x%04X, val_in=0x%04X", + data->phy_id,data->reg_num,data->val_in); + { + unsigned long dwIntFlags=0; + VL_KEY keyCode=Vl_WaitForLock(&(privateData->MacPhyLock),&dwIntFlags); + Phy_SetRegW( + privateData,data->reg_num,((WORD)(data->val_in)),keyCode); + Vl_ReleaseLock(&(privateData->MacPhyLock),keyCode,&dwIntFlags); + } + break; + + case SIOCETHTOOL: + result=Smsc9118_ethtool_ioctl(privateData,userAddr); + break; + case SMSC9118_IOCTL: + result=Smsc9118_private_ioctl(privateData,userAddr); + break; + + default: + result=-EOPNOTSUPP; + break;//make lint happy + } + } + +DONE: + + return result; +} + + + +int Smsc9118_private_ioctl(PPRIVATE_DATA privateData,void *useraddr) +{ + + + bool success=false; + int result=-EFAULT; + SMSC9118_IOCTL_DATA ioctlData; + + if(useraddr==NULL) { + SMSC_WARNING("useraddr==NULL"); + result=-EFAULT; + goto DONE; + } + + if(copy_from_user(&ioctlData,useraddr,sizeof(ioctlData))) { + SMSC_WARNING("copy_from_user failed"); + result=-EFAULT; + goto DONE; + } + + if(ioctlData.dwSignature!=SMSC9118_APP_SIGNATURE) { + SMSC_WARNING("invalid application signature"); + result=-EFAULT; + goto DONE; + } + + switch(ioctlData.dwCommand) { + case COMMAND_GET_SIGNATURE: + success=true; + break; + case COMMAND_GET_FLOW_PARAMS: + ioctlData.Data[0]=privateData->RxFlowMeasuredMaxThroughput; + ioctlData.Data[1]=privateData->RxFlowMeasuredMaxPacketCount; + ioctlData.Data[2]=privateData->RxFlowParameters.MaxThroughput; + ioctlData.Data[3]=privateData->RxFlowParameters.MaxPacketCount; + ioctlData.Data[4]=privateData->RxFlowParameters.PacketCost; + ioctlData.Data[5]=privateData->RxFlowParameters.BurstPeriod; + ioctlData.Data[6]=privateData->RxFlowMaxWorkLoad; + ioctlData.Data[7]=Lan_GetRegDW(INT_CFG)>>24; + privateData->RxFlowMeasuredMaxThroughput=0; + privateData->RxFlowMeasuredMaxPacketCount=0; + success=true; + break; + case COMMAND_SET_FLOW_PARAMS: + if(!(privateData->RxFlowControlActive)) { + privateData->RxFlowParameters.MaxThroughput=ioctlData.Data[2]; + privateData->RxFlowParameters.MaxPacketCount=ioctlData.Data[3]; + privateData->RxFlowParameters.PacketCost=ioctlData.Data[4]; + privateData->RxFlowParameters.BurstPeriod=ioctlData.Data[5]; + if(ioctlData.Data[6]==0xFFFFFFFFUL) { + privateData->RxFlowMaxWorkLoad= + privateData->RxFlowParameters.MaxThroughput+ + (privateData->RxFlowParameters.MaxPacketCount* + privateData->RxFlowParameters.PacketCost); + } else { + privateData->RxFlowMaxWorkLoad=ioctlData.Data[6]; + } + Lan_SetIntDeas(privateData,ioctlData.Data[7]); + privateData->RxFlowBurstMaxWorkLoad= + (privateData->RxFlowMaxWorkLoad* + privateData->RxFlowParameters.BurstPeriod)/1000; + success=true; + };break; + case COMMAND_GET_CONFIGURATION: + ioctlData.Data[0]=DRIVER_VERSION; + ioctlData.Data[1]=lan_base; + ioctlData.Data[2]=bus_width; + ioctlData.Data[3]=link_mode; + ioctlData.Data[4]=irq; + ioctlData.Data[5]=int_deas; + ioctlData.Data[6]=irq_pol; + ioctlData.Data[7]=irq_type; + ioctlData.Data[8]=rx_dma; + ioctlData.Data[9]=tx_dma; + ioctlData.Data[10]=dma_threshold; + ioctlData.Data[11]=mac_addr_hi16; + ioctlData.Data[12]=mac_addr_lo32; + ioctlData.Data[13]=debug_mode; + ioctlData.Data[14]=tx_fif_sz; + ioctlData.Data[15]=afc_cfg; + ioctlData.Data[16]=rx_mode; + ioctlData.Data[17]=max_throughput; + ioctlData.Data[18]=max_packet_count; + ioctlData.Data[19]=packet_cost; + ioctlData.Data[20]=burst_period; + ioctlData.Data[21]=max_work_load; + ioctlData.Data[22]=privateData->dwIdRev; + ioctlData.Data[23]=privateData->dwFpgaRev; + ioctlData.Data[24]=1; + ioctlData.Data[25]=privateData->dwPhyId; + ioctlData.Data[26]=privateData->bPhyModel; + ioctlData.Data[27]=privateData->bPhyRev; + ioctlData.Data[28]=privateData->dwLinkSpeed; + ioctlData.Data[29]=privateData->RxFlowMeasuredMaxThroughput; + ioctlData.Data[30]=privateData->RxFlowMeasuredMaxPacketCount; + ioctlData.Data[31]=privateData->RxFlowParameters.MaxThroughput; + ioctlData.Data[32]=privateData->RxFlowParameters.MaxPacketCount; + ioctlData.Data[33]=privateData->RxFlowParameters.PacketCost; + ioctlData.Data[34]=privateData->RxFlowParameters.BurstPeriod; + ioctlData.Data[35]=privateData->RxFlowMaxWorkLoad; + sprintf(ioctlData.Strng1,"%s, %s",__DATE__,__TIME__); + sprintf(ioctlData.Strng2,"%s",privateData->ifName); + privateData->RxFlowMeasuredMaxThroughput=0; + privateData->RxFlowMeasuredMaxPacketCount=0; + success=true; + break; + case COMMAND_LAN_GET_REG: + if((ioctlData.Data[0]dwLanBase+ + ioctlData.Data[0]))); + success=true; + } else { + SMSC_WARNING("Reading LAN9118 Mem Map Failed"); + goto MEM_MAP_ACCESS_FAILED; + } + break; + case COMMAND_LAN_SET_REG: + if((ioctlData.Data[0]dwLanBase+ + ioctlData.Data[0])))=ioctlData.Data[1]; + success=true; + } else { + SMSC_WARNING("Reading LAN9118 Mem Map Failed"); +MEM_MAP_ACCESS_FAILED: + SMSC_WARNING(" Invalid offset == 0x%08X",(u32)(ioctlData.Data[0])); + if(ioctlData.Data[0]>=LAN_REGISTER_EXTENT) { + SMSC_WARNING(" Out of range"); + } + if(ioctlData.Data[0]&0x3UL) { + SMSC_WARNING(" Not u32 aligned"); + } + } + break; + case COMMAND_MAC_GET_REG: + if((ioctlData.Data[0]<=0xC)&&(privateData->LanInitialized)) { + unsigned long dwIntFlags=0; + VL_KEY keyCode=Vl_WaitForLock(&(privateData->MacPhyLock),&dwIntFlags); + ioctlData.Data[1]= + Mac_GetRegDW(privateData,ioctlData.Data[0],keyCode); + Vl_ReleaseLock(&(privateData->MacPhyLock),keyCode,&dwIntFlags); + success=true; + } else { + SMSC_WARNING("Reading Mac Register Failed"); + goto MAC_ACCESS_FAILURE; + } + break; + case COMMAND_MAC_SET_REG: + if((ioctlData.Data[0]<=0xC)&&(privateData->LanInitialized)) { + unsigned long dwIntFlags=0; + VL_KEY keyCode=Vl_WaitForLock(&(privateData->MacPhyLock),&dwIntFlags); + Mac_SetRegDW( + privateData, + ioctlData.Data[0], + ioctlData.Data[1], + keyCode); + Vl_ReleaseLock(&(privateData->MacPhyLock),keyCode,&dwIntFlags); + success=true; + } else { + SMSC_WARNING("Writing Mac Register Failed"); +MAC_ACCESS_FAILURE: + if(!(privateData->LanInitialized)) { + + SMSC_WARNING(" LAN Not Initialized,"); + SMSC_WARNING(" Use ifconfig to bring interface UP"); + } + if(!(ioctlData.Data[0]<=0xC)) { + SMSC_WARNING(" Invalid index == 0x%08X",(u32)(ioctlData.Data[0])); + } + } + break; + case COMMAND_PHY_GET_REG: + if((ioctlData.Data[0]<32)&&(privateData->LanInitialized)) { + unsigned long dwIntFlags=0; + VL_KEY keyCode=Vl_WaitForLock(&(privateData->MacPhyLock),&dwIntFlags); + ioctlData.Data[1]=((u32) + Phy_GetRegW(privateData,ioctlData.Data[0],keyCode)); + Vl_ReleaseLock(&(privateData->MacPhyLock),keyCode,&dwIntFlags); + success=true; + } else { + SMSC_WARNING("Reading Phy Register Failed"); + goto PHY_ACCESS_FAILURE; + } + break; + case COMMAND_PHY_SET_REG: + if((ioctlData.Data[0]<32)&&(privateData->LanInitialized)) { + unsigned long dwIntFlags=0; + VL_KEY keyCode=Vl_WaitForLock(&(privateData->MacPhyLock),&dwIntFlags); + Phy_SetRegW( + privateData, + ioctlData.Data[0], + ((WORD)(ioctlData.Data[1])), + keyCode); + Vl_ReleaseLock(&(privateData->MacPhyLock),keyCode,&dwIntFlags); + success=true; + } else { + SMSC_WARNING("Writing Phy Register Failed"); +PHY_ACCESS_FAILURE: + if(!(privateData->LanInitialized)) { + SMSC_WARNING(" Lan Not Initialized,"); + SMSC_WARNING(" Use ifconfig to bring interface UP"); + } + if(!(ioctlData.Data[0]<32)) { + SMSC_WARNING(" Invalid index == 0x%d",(u32)(ioctlData.Data[0])); + } + } + break; + // case COMMAND_DUMP_TEMP: + // { + // u32 c=0; + // for(c=0;c<0x40;c++) + // ioctlData.Data[c]=privateData->temp[c]; + // } + // success=true; + // break; + case COMMAND_DUMP_LAN_REGS: + ioctlData.Data[LAN_REG_ID_REV]=Lan_GetRegDW(ID_REV); + ioctlData.Data[LAN_REG_INT_CFG]=Lan_GetRegDW(INT_CFG); + ioctlData.Data[LAN_REG_INT_STS]=Lan_GetRegDW(INT_STS); + ioctlData.Data[LAN_REG_INT_EN]=Lan_GetRegDW(INT_EN); + ioctlData.Data[LAN_REG_BYTE_TEST]=Lan_GetRegDW(BYTE_TEST); + ioctlData.Data[LAN_REG_FIFO_INT]=Lan_GetRegDW(FIFO_INT); + ioctlData.Data[LAN_REG_RX_CFG]=Lan_GetRegDW(RX_CFG); + ioctlData.Data[LAN_REG_TX_CFG]=Lan_GetRegDW(TX_CFG); + ioctlData.Data[LAN_REG_HW_CFG]=Lan_GetRegDW(HW_CFG); + ioctlData.Data[LAN_REG_RX_DP_CTRL]=Lan_GetRegDW(RX_DP_CTRL); + ioctlData.Data[LAN_REG_RX_FIFO_INF]=Lan_GetRegDW(RX_FIFO_INF); + ioctlData.Data[LAN_REG_TX_FIFO_INF]=Lan_GetRegDW(TX_FIFO_INF); + ioctlData.Data[LAN_REG_PMT_CTRL]=Lan_GetRegDW(PMT_CTRL); + ioctlData.Data[LAN_REG_GPIO_CFG]=Lan_GetRegDW(GPIO_CFG); + ioctlData.Data[LAN_REG_GPT_CFG]=Lan_GetRegDW(GPT_CFG); + ioctlData.Data[LAN_REG_GPT_CNT]=Lan_GetRegDW(GPT_CNT); + ioctlData.Data[LAN_REG_FPGA_REV]=Lan_GetRegDW(FPGA_REV); + ioctlData.Data[LAN_REG_WORD_SWAP]=Lan_GetRegDW(WORD_SWAP); + ioctlData.Data[LAN_REG_FREE_RUN]=Lan_GetRegDW(FREE_RUN); + ioctlData.Data[LAN_REG_RX_DROP]=Lan_GetRegDW(RX_DROP); + if(privateData->LanInitialized) { + unsigned long dwIntFlags=0; + VL_KEY keyCode=Vl_WaitForLock(&(privateData->MacPhyLock),&dwIntFlags); + ioctlData.Data[LAN_REG_MAC_CSR_CMD]=Lan_GetRegDW(MAC_CSR_CMD); + ioctlData.Data[LAN_REG_MAC_CSR_DATA]=Lan_GetRegDW(MAC_CSR_DATA); + Vl_ReleaseLock(&(privateData->MacPhyLock),keyCode,&dwIntFlags); + } else { + ioctlData.Data[LAN_REG_MAC_CSR_CMD]=Lan_GetRegDW(MAC_CSR_CMD); + ioctlData.Data[LAN_REG_MAC_CSR_DATA]=Lan_GetRegDW(MAC_CSR_DATA); + } + ioctlData.Data[LAN_REG_AFC_CFG]=Lan_GetRegDW(AFC_CFG); + ioctlData.Data[LAN_REG_E2P_CMD]=Lan_GetRegDW(E2P_CMD); + ioctlData.Data[LAN_REG_E2P_DATA]=Lan_GetRegDW(E2P_DATA); + success=true; + break; + case COMMAND_DUMP_MAC_REGS: + if(privateData->LanInitialized) { + unsigned long dwIntFlags=0; + VL_KEY keyCode=Vl_WaitForLock(&(privateData->MacPhyLock),&dwIntFlags); + ioctlData.Data[MAC_REG_MAC_CR]=Mac_GetRegDW(privateData,MAC_CR,keyCode); + ioctlData.Data[MAC_REG_ADDRH]=Mac_GetRegDW(privateData,ADDRH,keyCode); + ioctlData.Data[MAC_REG_ADDRL]=Mac_GetRegDW(privateData,ADDRL,keyCode); + ioctlData.Data[MAC_REG_HASHH]=Mac_GetRegDW(privateData,HASHH,keyCode); + ioctlData.Data[MAC_REG_HASHL]=Mac_GetRegDW(privateData,HASHL,keyCode); + ioctlData.Data[MAC_REG_MII_ACC]=Mac_GetRegDW(privateData,MII_ACC,keyCode); + ioctlData.Data[MAC_REG_MII_DATA]=Mac_GetRegDW(privateData,MII_DATA,keyCode); + ioctlData.Data[MAC_REG_FLOW]=Mac_GetRegDW(privateData,FLOW,keyCode); + ioctlData.Data[MAC_REG_VLAN1]=Mac_GetRegDW(privateData,VLAN1,keyCode); + ioctlData.Data[MAC_REG_VLAN2]=Mac_GetRegDW(privateData,VLAN2,keyCode); + ioctlData.Data[MAC_REG_WUFF]=Mac_GetRegDW(privateData,WUFF,keyCode); + ioctlData.Data[MAC_REG_WUCSR]=Mac_GetRegDW(privateData,WUCSR,keyCode); + Vl_ReleaseLock(&(privateData->MacPhyLock),keyCode,&dwIntFlags); + success=true; + } else { + SMSC_WARNING("Mac Not Initialized,"); + SMSC_WARNING(" Use ifconfig to bring interface UP"); + } + break; + case COMMAND_DUMP_PHY_REGS: + if(privateData->LanInitialized) { + unsigned long dwIntFlags=0; + VL_KEY keyCode=Vl_WaitForLock(&(privateData->MacPhyLock),&dwIntFlags); + ioctlData.Data[PHY_REG_0]=Phy_GetRegW(privateData,0,keyCode); + ioctlData.Data[PHY_REG_1]=Phy_GetRegW(privateData,1,keyCode); + ioctlData.Data[PHY_REG_2]=Phy_GetRegW(privateData,2,keyCode); + ioctlData.Data[PHY_REG_3]=Phy_GetRegW(privateData,3,keyCode); + ioctlData.Data[PHY_REG_4]=Phy_GetRegW(privateData,4,keyCode); + ioctlData.Data[PHY_REG_5]=Phy_GetRegW(privateData,5,keyCode); + ioctlData.Data[PHY_REG_6]=Phy_GetRegW(privateData,6,keyCode); + ioctlData.Data[PHY_REG_16]=Phy_GetRegW(privateData,16,keyCode); + ioctlData.Data[PHY_REG_17]=Phy_GetRegW(privateData,17,keyCode); + ioctlData.Data[PHY_REG_18]=Phy_GetRegW(privateData,18,keyCode); + ioctlData.Data[PHY_REG_20]=Phy_GetRegW(privateData,20,keyCode); + ioctlData.Data[PHY_REG_21]=Phy_GetRegW(privateData,21,keyCode); + ioctlData.Data[PHY_REG_22]=Phy_GetRegW(privateData,22,keyCode); + ioctlData.Data[PHY_REG_23]=Phy_GetRegW(privateData,23,keyCode); + ioctlData.Data[PHY_REG_27]=Phy_GetRegW(privateData,27,keyCode); + ioctlData.Data[PHY_REG_28]=Phy_GetRegW(privateData,28,keyCode); + ioctlData.Data[PHY_REG_29]=Phy_GetRegW(privateData,29,keyCode); + ioctlData.Data[PHY_REG_30]=Phy_GetRegW(privateData,30,keyCode); + ioctlData.Data[PHY_REG_31]=Phy_GetRegW(privateData,31,keyCode); + Vl_ReleaseLock(&(privateData->MacPhyLock),keyCode,&dwIntFlags); + success=true; + } else { + SMSC_WARNING("Phy Not Initialized,"); + SMSC_WARNING(" Use ifconfig to bring interface UP"); + } + break; + case COMMAND_DUMP_EEPROM: + { + BYTE data=0; + BYTE index=0; + Eeprom_EnableAccess(privateData); + success=true; + for(index=0;index<8;index++) { + if(Eeprom_ReadLocation(privateData,index,&data)) { + ioctlData.Data[index]=(u32)data; + } else { + success=false; + break; + } + } + Eeprom_DisableAccess(privateData); + };break; + case COMMAND_GET_MAC_ADDRESS: + if(privateData->LanInitialized) { + unsigned long dwIntFlags=0; + VL_KEY keyCode=Vl_WaitForLock(&(privateData->MacPhyLock),&dwIntFlags); + ioctlData.Data[0]=Mac_GetRegDW(privateData,ADDRH,keyCode); + ioctlData.Data[1]=Mac_GetRegDW(privateData,ADDRL,keyCode); + Vl_ReleaseLock(&(privateData->MacPhyLock),keyCode,&dwIntFlags); + success=true; + } else { + SMSC_WARNING("Lan Not Initialized,"); + SMSC_WARNING(" Use ifconfig to bring interface UP"); + } + break; + + case COMMAND_SET_MAC_ADDRESS: + if(privateData->LanInitialized) + { + u32 dwLow32=ioctlData.Data[1]; + u32 dwHigh16=ioctlData.Data[0]; + unsigned long dwIntFlags=0; + VL_KEY keyCode=Vl_WaitForLock(&(privateData->MacPhyLock),&dwIntFlags); + Mac_SetRegDW(privateData,ADDRH,dwHigh16,keyCode); + Mac_SetRegDW(privateData,ADDRL,dwLow32,keyCode); + Vl_ReleaseLock(&(privateData->MacPhyLock),keyCode,&dwIntFlags); + success=true; + } else { + SMSC_WARNING("Lan Not Initialized,"); + SMSC_WARNING(" Use ifconfig to bring interface UP"); + };break; + case COMMAND_LOAD_MAC_ADDRESS: + if(privateData->LanInitialized) { + Eeprom_EnableAccess(privateData); + if(Eeprom_Reload(privateData)) { + if(Eeprom_IsMacAddressLoaded(privateData)) { + unsigned long dwIntFlags=0; + VL_KEY keyCode=Vl_WaitForLock(&(privateData->MacPhyLock),&dwIntFlags); + ioctlData.Data[0]=Mac_GetRegDW(privateData,ADDRH,keyCode); + ioctlData.Data[1]=Mac_GetRegDW(privateData,ADDRL,keyCode); + Vl_ReleaseLock(&(privateData->MacPhyLock),keyCode,&dwIntFlags); + success=true; + } else { + SMSC_WARNING("Failed to Load Mac Address(1)"); + } + } else { + SMSC_WARNING("Failed to Load Mac Address(2)"); + } + Eeprom_DisableAccess(privateData); + } else { + SMSC_WARNING("Lan Not Initialized,"); + SMSC_WARNING(" Use ifconfig to bring interface UP"); + };break; + case COMMAND_SAVE_MAC_ADDRESS: + if(privateData->LanInitialized) { + if(Eeprom_SaveMacAddress(privateData, + ioctlData.Data[0],ioctlData.Data[1])) { + success=true; + } + } else { + SMSC_WARNING("Lan Not Initialized,"); + SMSC_WARNING(" Use ifconfig to bring interface UP"); + };break; + case COMMAND_SET_DEBUG_MODE: + debug_mode=ioctlData.Data[0]; + if(debug_mode&0x04UL) { + if(OLD_REGISTERS(privateData)) + { + g_GpioSetting=0x00270700UL; + } else { + g_GpioSetting=0x00670700UL; + } + Lan_SetRegDW(GPIO_CFG,g_GpioSetting); + } else { + Lan_SetRegDW(GPIO_CFG,0x70070000); + } + success=true; + break; + case COMMAND_SET_LINK_MODE: + link_mode=(ioctlData.Data[0]&0x7FUL); + if(privateData->LanInitialized) { + Phy_SetLink(privateData,link_mode); + } + success=true; + break; + case COMMAND_GET_LINK_MODE: + ioctlData.Data[0]=link_mode; + success=true; + break; + case COMMAND_CHECK_LINK: + Phy_UpdateLinkMode(privateData); + success=true; + break; + case COMMAND_READ_BYTE: + ioctlData.Data[1]=(*((volatile BYTE *)(ioctlData.Data[0]))); + success=true; + break; + case COMMAND_READ_WORD: + ioctlData.Data[1]=(*((volatile WORD *)(ioctlData.Data[0]))); + success=true; + break; + case COMMAND_READ_DWORD: + ioctlData.Data[1]=(*((volatile u32 *)(ioctlData.Data[0]))); + success=true; + break; + case COMMAND_WRITE_BYTE: + (*((volatile BYTE *)(ioctlData.Data[0])))= + ((BYTE)(ioctlData.Data[1])); + success=true; + break; + case COMMAND_WRITE_WORD: + (*((volatile WORD *)(ioctlData.Data[0])))= + ((WORD)(ioctlData.Data[1])); + success=true; + break; + case COMMAND_WRITE_DWORD: + (*((volatile u32 *)(ioctlData.Data[0])))= + ((u32)(ioctlData.Data[1])); + success=true; + break; + case COMMAND_SET_AMDIX_STS: + AutoMdix=(ioctlData.Data[0]); + if(privateData->LanInitialized) { + Phy_SetAutoMdixSts(privateData,AutoMdix); + } + success=true; + break; + case COMMAND_GET_AMDIX_STS: + ioctlData.Data[0]=AutoMdix; + if(privateData->LanInitialized) { + Phy_GetAutoMdixSts(privateData); + } + success=true; + break; + + default:return -EOPNOTSUPP; + } + +DONE: + if(success) { + ioctlData.dwSignature=SMSC9118_DRIVER_SIGNATURE; + if(copy_to_user(useraddr, &ioctlData, sizeof(ioctlData))) { + SMSC_WARNING("copy_to_user failed"); + result=-EFAULT; + } + result=0; + } + // SMSC_TRACE("<--Smsc9118_do_ioctl"); + return result; + +} + + + +int Smsc9118_ethtool_ioctl(PPRIVATE_DATA privateData, void * userAddr) +{ + int result=-EFAULT; + u32 ethcmd=0; + if(copy_from_user(ðcmd,userAddr,sizeof(ethcmd))) + { + result=-EFAULT; + goto DONE; + } + switch(ethcmd) { + case ETHTOOL_GSET:// Get settings. + // SMSC_TRACE("ETHTOOL_GSET"); + { + struct ethtool_cmd settings={ETHTOOL_GSET}; + settings.supported= + SUPPORTED_10baseT_Half | + SUPPORTED_10baseT_Full | + SUPPORTED_100baseT_Half | + SUPPORTED_100baseT_Full | + SUPPORTED_Autoneg | + SUPPORTED_MII; + settings.advertising=ADVERTISED_MII; + if(privateData->dwLinkSettings & LINK_SPEED_10HD) + settings.advertising|=ADVERTISED_10baseT_Half; + if(privateData->dwLinkSettings & LINK_SPEED_10FD) + settings.advertising|=ADVERTISED_10baseT_Full; + if(privateData->dwLinkSettings & LINK_SPEED_100HD) + settings.advertising|=ADVERTISED_100baseT_Half; + if(privateData->dwLinkSettings & LINK_SPEED_100FD) + settings.advertising|=ADVERTISED_100baseT_Full; + if(privateData->dwLinkSettings & LINK_AUTO_NEGOTIATE) { + settings.advertising|=ADVERTISED_Autoneg; + settings.autoneg=AUTONEG_ENABLE; + } else settings.autoneg=AUTONEG_DISABLE; + if(privateData->dwLinkSpeed & (LINK_SPEED_100HD|LINK_SPEED_100FD)) + settings.speed=SPEED_100; + else settings.speed=SPEED_10; + if(privateData->dwLinkSpeed & (LINK_SPEED_10FD|LINK_SPEED_100FD)) + settings.duplex=DUPLEX_FULL; + else settings.duplex=DUPLEX_HALF; + settings.port=PORT_MII; + settings.phy_address=(u8)privateData->dwPhyAddress; + settings.transceiver=XCVR_INTERNAL; + settings.maxtxpkt=0; + settings.maxrxpkt=0; + if(copy_to_user(userAddr,&settings,sizeof(settings))) { + result=-EFAULT; + } else { + result=0; + } + } + break; + case ETHTOOL_SSET:// Set settings. + // SMSC_TRACE("ETHTOOL_SSET"); + { + struct ethtool_cmd settings; + u16 speed=0; + u8 duplex=0; + u8 autoneg=0; + if(copy_from_user(&settings,userAddr,sizeof(settings))) { + result=-EFAULT; + goto DONE; + } + if(privateData->dwLinkSettings&LINK_AUTO_NEGOTIATE) { + autoneg=AUTONEG_ENABLE; + } else { + autoneg=AUTONEG_DISABLE; + } + if(privateData->dwLinkSpeed&(LINK_SPEED_100HD|LINK_SPEED_100FD)) + { + speed=SPEED_100; + } else { + speed=SPEED_10; + } + if(privateData->dwLinkSpeed&(LINK_SPEED_10FD|LINK_SPEED_100FD)) + { + duplex=DUPLEX_FULL; + } else { + duplex=DUPLEX_HALF; + } + if((settings.speed!=100)&&(settings.speed!=10)) { + result=-EOPNOTSUPP; + goto DONE; + } + if((settings.duplex!=DUPLEX_FULL)&&(settings.duplex!=DUPLEX_HALF)) { + result=-EOPNOTSUPP; + goto DONE; + } + if((settings.autoneg!=AUTONEG_ENABLE)&&(settings.autoneg!=AUTONEG_DISABLE)) { + result=-EOPNOTSUPP; + goto DONE; + } + if((settings.autoneg!=autoneg)|| + (settings.speed!=speed)|| + (settings.duplex!=duplex)) + { + unsigned long dwIntFlags=0; + VL_KEY keyCode=Vl_WaitForLock(&(privateData->MacPhyLock),&dwIntFlags); + if(settings.autoneg==AUTONEG_ENABLE) { + + + + WORD wAdvertisement=Phy_GetRegW(privateData,PHY_ANEG_ADV,keyCode); + wAdvertisement&=(~PHY_ANEG_ADV_SPEED_); + if(settings.speed==SPEED_100) { + if(settings.duplex==DUPLEX_FULL) { + wAdvertisement|=PHY_ANEG_ADV_100F_; + } else { + wAdvertisement|=PHY_ANEG_ADV_100H_; + } + } else { + if(settings.duplex==DUPLEX_FULL) { + wAdvertisement|=PHY_ANEG_ADV_10F_; + } else { + wAdvertisement|=PHY_ANEG_ADV_10H_; + } + } + + + + Phy_SetRegW(privateData,PHY_ANEG_ADV,wAdvertisement,keyCode); + Phy_SetRegW(privateData,PHY_BCR, + (PHY_BCR_AUTO_NEG_ENABLE_|PHY_BCR_RESTART_AUTO_NEG_),keyCode); + + + } else { + WORD wBcr=Phy_GetRegW(privateData,PHY_BCR,keyCode); + if(settings.speed==SPEED_100) { + wBcr|=PHY_BCR_SPEED_SELECT_; + } else { + wBcr&=(~PHY_BCR_SPEED_SELECT_); + } + if(settings.duplex==DUPLEX_FULL) { + wBcr|=PHY_BCR_DUPLEX_MODE_; + } else { + wBcr&=(~PHY_BCR_DUPLEX_MODE_); + } + Phy_SetRegW(privateData,PHY_BCR,wBcr,keyCode); + } + Vl_ReleaseLock(&(privateData->MacPhyLock),keyCode,&dwIntFlags); + + } + result=0; + } + break; + case ETHTOOL_GDRVINFO:// Get driver info. + // SMSC_TRACE("ETHTOOL_GDRVINFO"); + { + struct ethtool_drvinfo info = {ETHTOOL_GDRVINFO}; + strcpy(info.driver,"Smsc9131_eth"); + memset(&info.version,0,sizeof(info.version)); + memset(&info.fw_version,0,sizeof(info.fw_version)); + sprintf(info.fw_version,"%u",(privateData->dwIdRev)&0xFFFF); + memset(&info.bus_info,0,sizeof(info.bus_info)); + memset(&info.reserved1,0,sizeof(info.reserved1)); + memset(&info.reserved2,0,sizeof(info.reserved2)); +#ifdef LINUX_2_6_OR_NEWER + info.n_stats=0; + info.testinfo_len=0; +#endif + info.eedump_len=0; + info.regdump_len=0; + if(copy_to_user(userAddr,&info,sizeof(info))) { + result=-EFAULT; + } else { + result=0; + } + } + break; + case ETHTOOL_GREGS:// Get NIC registers. + // SMSC_TRACE("ETHTOOL_GREGS"); + result=-EOPNOTSUPP; + break; + /* + case ETHTOOL_GWOL:// Get wake-on-lan options. + SMSC_TRACE("ETHTOOL_GWOL"); + { + struct ethtool_wolinfo wol_info={ETHTOOL_GWOL}; + //wol_info.supported=true; + wol_info.supported=(WAKE_PHY | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST | WAKE_ARP | WAKE_MAGIC); + wol_info.wolopts= privateData->WolWakeupOpts; + memset(&wol_info.sopass,0,sizeof(wol_info.sopass)); + if(copy_to_user(userAddr,&wol_info,sizeof(wol_info))) { + result=-EFAULT; + } else { + result=0; + } + } + break; + case ETHTOOL_SWOL:// Set wake-on-lan options. + SMSC_TRACE("ETHTOOL_SWOL"); + { + unsigned long dwIntFlags=0; + struct ethtool_wolinfo wol_info; + if(copy_from_user(&wol_info,userAddr,sizeof(wol_info))) + { + result=-EFAULT; + } else { + SMSC_TRACE(DBG_IOCTL,"WOL OPTS = 0x%x", wol_info.wolopts); + spin_lock_irqsave(&(privateData->PhyLock),dwIntFlags); + privateData->WolWakeupOpts = wol_info.wolopts; + spin_unlock_irqrestore(&(privateData->PhyLock),dwIntFlags); + result=0; + } + } + break; + */ + case ETHTOOL_GMSGLVL:// Get driver message level + // SMSC_TRACE("ETHTOOL_GMSGLVL"); + { + struct ethtool_value msgLevel={ETHTOOL_GMSGLVL}; + msgLevel.data=debug_mode; + if(copy_to_user(userAddr, &msgLevel,sizeof(msgLevel))) { + result=-EFAULT; + } else { + result=0; + } + } + break; + case ETHTOOL_SMSGLVL:// Set driver msg level. + // SMSC_TRACE("ETHTOOL_SMSGLVL"); + { + struct ethtool_value msgLevel; + if(copy_from_user(&msgLevel,userAddr,sizeof(msgLevel))) + { + result=-EFAULT; + } else { + debug_mode=msgLevel.data; + result=0; + } + } + break; + case ETHTOOL_NWAY_RST:// Restart autonegotiation. + // SMSC_TRACE("ETHTOOL_NWAY_RST"); + { + unsigned long dwIntFlags=0; + VL_KEY keyCode=Vl_WaitForLock(&(privateData->MacPhyLock),&dwIntFlags); + Phy_SetRegW(privateData,PHY_BCR, + (PHY_BCR_AUTO_NEG_ENABLE_|PHY_BCR_RESTART_AUTO_NEG_),keyCode); + Vl_ReleaseLock(&(privateData->MacPhyLock),keyCode,&dwIntFlags); + result=0; + } + break; + case ETHTOOL_GLINK:// Get link status (ethtool_value) + // SMSC_TRACE("ETHTOOL_GLINK"); + { + struct ethtool_value linkStatus={ETHTOOL_GLINK}; + if(privateData->dwLinkSpeed!=LINK_OFF) { + linkStatus.data=1; + } else { + linkStatus.data=0; + } + if(copy_to_user(userAddr,&linkStatus,sizeof(linkStatus))) + { + result=-EFAULT; + } else { + result=0; + } + } + break; + case ETHTOOL_GEEPROM:// Get EEPROM data + // SMSC_TRACE("ETHTOOL_GEEPROM"); + result=-EOPNOTSUPP; + break; + case ETHTOOL_SEEPROM:// Set EEPROM data. + // SMSC_TRACE("ETHTOOL_SEEPROM"); + result=-EOPNOTSUPP; + break; + +#ifdef LINUX_2_6_OR_NEWER + + case ETHTOOL_GCOALESCE:// Get coalesce config + // SMSC_TRACE("ETHTOOL_GCOALESCE"); + result=-EOPNOTSUPP; + break; + case ETHTOOL_SCOALESCE:// Set coalesce config. + // SMSC_TRACE("ETHTOOL_SCOALESCE"); + result=-EOPNOTSUPP; + break; + case ETHTOOL_GRINGPARAM:// Get ring parameters + // SMSC_TRACE("ETHTOOL_GRINGPARAM"); + result=-EOPNOTSUPP; + break; + case ETHTOOL_SRINGPARAM:// Set ring parameters. + // SMSC_TRACE("ETHTOOL_SRINGPARAM"); + result=-EOPNOTSUPP; + break; + case ETHTOOL_GPAUSEPARAM:// Get pause parameters + // SMSC_TRACE("ETHTOOL_GPAUSEPARAM"); + result=-EOPNOTSUPP; + break; + case ETHTOOL_SPAUSEPARAM:// Set pause parameters. + // SMSC_TRACE("ETHTOOL_SPAUSEPARAM"); + result=-EOPNOTSUPP; + break; + case ETHTOOL_GRXCSUM:// Get RX hw csum enable (ethtool_value) + // SMSC_TRACE("ETHTOOL_GRXCSUM"); + { + struct ethtool_value rxCsum={ETHTOOL_GRXCSUM}; + rxCsum.data=0; + if(copy_to_user(userAddr,&rxCsum,sizeof(rxCsum))) { + result=-EFAULT; + } else { + result=0; + } + } + break; + case ETHTOOL_SRXCSUM:// Set RX hw csum enable (ethtool_value) + // SMSC_TRACE("ETHTOOL_SRXCSUM"); + result=-EOPNOTSUPP; + break; + case ETHTOOL_GTXCSUM:// Get TX hw csum enable (ethtool_value) + // SMSC_TRACE("ETHTOOL_GTXCSUM"); + { + struct ethtool_value txCsum={ETHTOOL_GTXCSUM}; + txCsum.data=0; + if(copy_to_user(userAddr,&txCsum,sizeof(txCsum))) { + result=-EFAULT; + } else { + result=0; + } + } + break; + case ETHTOOL_STXCSUM:// Set TX hw csum enable (ethtool_value) + // SMSC_TRACE("ETHTOOL_STXCSUM"); + result=-EOPNOTSUPP; + break; + case ETHTOOL_GSG:// Get scatter-gather enable (ethtool_value) + // SMSC_TRACE("ETHTOOL_GSG"); + { + struct ethtool_value sg={ETHTOOL_GSG}; + sg.data=0; + if(copy_to_user(userAddr,&sg,sizeof(sg))) { + result=-EFAULT; + } else { + result=0; + } + } + break; + case ETHTOOL_SSG:// Set scatter-gather enable (ethtool_value). + // SMSC_TRACE("ETHTOOL_SSG"); + result=-EOPNOTSUPP; + break; + case ETHTOOL_TEST:// execute NIC self-test. + // SMSC_TRACE("ETHTOOL_TEST"); + result=-EOPNOTSUPP; + break; + case ETHTOOL_GSTRINGS:// get specified string set + // SMSC_TRACE("ETHTOOL_GSTRINGS"); + result=-EOPNOTSUPP; + break; + case ETHTOOL_PHYS_ID:// identify the NIC + // SMSC_TRACE("ETHTOOL_PHYS_ID"); + result=-EOPNOTSUPP; + break; + case ETHTOOL_GSTATS:// get NIC-specific statistics + // SMSC_TRACE("ETHTOOL_GSTATS"); + result=-EOPNOTSUPP; + break; + + case ETHTOOL_GTSO:// Get TSO enable (ethtool_value) + // SMSC_TRACE("ETHTOOL_GTSO"); + { + struct ethtool_value tso={ETHTOOL_GTSO}; + tso.data=0; + if(copy_to_user(userAddr,&tso,sizeof(tso))) { + result=-EFAULT; + } else { + result=0; + } + } + break; + case ETHTOOL_STSO:// Set TSO enable (ethtool_value) + // SMSC_TRACE("ETHTOOL_STS0"); + result=-EOPNOTSUPP; + break; +#endif + default: + // SMSC_WARNING("unknown ethcmd=0x%08X",ethcmd); + result=-EOPNOTSUPP; + break; + } +DONE: + return result; +} + + +//returns time1-time2; +TIME_SPAN Gpt_FreeRunCompare(u32 time1,u32 time2) +{ + return ((TIME_SPAN)(time1-time2)); +} +void Gpt_ScheduleInterrupt(PPRIVATE_DATA privateData,TIME_SPAN timeSpan) +{ + u32 timerValue=0; + if(timeSpan<0) timeSpan=0; + timerValue=(u32)timeSpan; + if((timerValue%2500)>=1250) { + timerValue=(timerValue/2500)+1; + } else { + timerValue=(timerValue/2500); + } + if(timerValue>0x0000FFFFUL) { + timerValue=0x0000FFFF; + } + Lan_SetRegDW(GPT_CFG,(timerValue|GPT_CFG_TIMER_EN_)); + Lan_SetRegDW(INT_STS,INT_STS_GPT_INT_); +} + +void Gpt_CancelInterrupt(PPRIVATE_DATA privateData) +{ + Lan_SetRegDW(GPT_CFG,0UL); + Lan_SetRegDW(INT_STS,INT_STS_GPT_INT_); +} + +void Gpt_ScheduleCallBack( + PPRIVATE_DATA privateData, + void (*callBackFunction)(PPRIVATE_DATA privateData), + u32 callBackTime) +{ + u32 slot_index=GPT_SCHEDULE_DEPTH; + bool result=false; + if((callBackFunction!=NULL)&&(callBackTime!=0)) { + unsigned long dwIntFlags=0; + SMSC_ASSERT(privateData!=NULL); + spin_lock_irqsave(&privateData->GpTimerLock,dwIntFlags); + { + u32 index=0; + u32 currentTime=Lan_GetRegDW(FREE_RUN); + TIME_SPAN nextCallTime=MAX_TIME_SPAN; + TIME_SPAN timeSpan=MAX_TIME_SPAN; + bool rescheduleRequired=false; + for(index=0;indexGptFunction[index]==NULL) { + if(!result) { + result=true; + //lint -save + //lint -e611 //suspicious cast + privateData->GptFunction[index]=(void *)callBackFunction; + //lint -restore_ + privateData->GptCallTime[index]=currentTime+(2500*callBackTime); + timeSpan=Gpt_FreeRunCompare(privateData->GptCallTime[index],currentTime); + if(nextCallTime>timeSpan) { + nextCallTime=timeSpan; + rescheduleRequired=true; + slot_index = index; + } + } + } else { + timeSpan=Gpt_FreeRunCompare(privateData->GptCallTime[index],currentTime); + if(nextCallTime>=timeSpan) { + nextCallTime=timeSpan; + rescheduleRequired=false; + } + } + } + if(rescheduleRequired) { + privateData->Gpt_scheduled_slot_index = slot_index; + Gpt_ScheduleInterrupt(privateData,nextCallTime); + } + } + spin_unlock_irqrestore(&(privateData->GpTimerLock),dwIntFlags); + } + if(!result) { + SMSC_WARNING("Gpt_ScheduleCallBack: Failed"); + } +} + +void Gpt_CancelCallBack( + PPRIVATE_DATA privateData, + void (*callBackFunction)(PPRIVATE_DATA privateData)) +{ + bool result=false; + if(callBackFunction!=NULL) { + unsigned long dwIntFlags=0; + SMSC_ASSERT(privateData!=NULL); + spin_lock_irqsave(&(privateData->GpTimerLock),dwIntFlags); + { + u32 index=0; + u32 currentTime=Lan_GetRegDW(FREE_RUN); + TIME_SPAN nextCallTime=MAX_TIME_SPAN; + TIME_SPAN timeSpan=MAX_TIME_SPAN; + bool rescheduleRequired=false; + for(index=0;indexGptFunction[index]==callBackFunction) { + result=true; + //lint -save + //lint -e611 //suspicious cast + privateData->GptFunction[index]=(void *)NULL; + // cancelled time will not need a + // re-scheduled + + // re-scheduled is done at other + // non-null slots + } + else if(privateData->GptFunction[index]!=NULL) { + timeSpan=Gpt_FreeRunCompare(privateData->GptCallTime[index],currentTime); + // if this scheduled time is earlier + // than current scheduled time + // AND not a duplicated one + if(nextCallTime>=timeSpan && privateData->Gpt_scheduled_slot_index != index) { + nextCallTime=timeSpan; + rescheduleRequired=true; + privateData->Gpt_scheduled_slot_index = index; + } + } + } + if(rescheduleRequired) { + Gpt_ScheduleInterrupt(privateData,nextCallTime); + } + else if (privateData->Gpt_scheduled_slot_index==GPT_SCHEDULE_DEPTH) { + Gpt_CancelInterrupt(privateData); + } + } + spin_unlock_irqrestore(&(privateData->GpTimerLock),dwIntFlags); + } + if(!result) { + SMSC_WARNING("Gpt_CancelCallBack: Failed"); + } +} + +bool Gpt_HandleInterrupt( + PPRIVATE_DATA privateData,u32 dwIntSts) +{ + SMSC_ASSERT(privateData!=NULL); + if(dwIntSts&INT_STS_GPT_INT_) + { + unsigned long dwIntFlags=0; + Lan_SetRegDW(INT_STS,INT_STS_GPT_INT_); + spin_lock_irqsave(&(privateData->GpTimerLock),dwIntFlags); + { + u32 index=0; + u32 currentTime=Lan_GetRegDW(FREE_RUN); + TIME_SPAN timeSpan=MAX_TIME_SPAN; + TIME_SPAN nextCallTime=MAX_TIME_SPAN; + bool rescheduleRequired=false; + for(index=0;indexGptFunction[index]!=NULL) { + timeSpan=Gpt_FreeRunCompare(privateData->GptCallTime[index],currentTime); + if(timeSpan<1250) { + void (*callBackFunction)(PPRIVATE_DATA privateData); + callBackFunction=privateData->GptFunction[index]; + privateData->GptFunction[index]=NULL; + spin_unlock_irqrestore(&(privateData->GpTimerLock),dwIntFlags); + privateData->Gpt_scheduled_slot_index = GPT_SCHEDULE_DEPTH; + callBackFunction(privateData); + spin_lock_irqsave(&(privateData->GpTimerLock),dwIntFlags); + } + } + } + for(index=0;indexGptFunction[index]!=NULL) { + rescheduleRequired=true; + timeSpan=Gpt_FreeRunCompare(privateData->GptCallTime[index],currentTime); + if(nextCallTime>timeSpan) { + nextCallTime=timeSpan; + privateData->Gpt_scheduled_slot_index = index; + } + } + } + if(rescheduleRequired) { + Gpt_ScheduleInterrupt(privateData,nextCallTime); + } + } + spin_unlock_irqrestore(&(privateData->GpTimerLock),dwIntFlags); + return true; + } + return false; +} + +void GptCB_RxCompleteMulticast(PPRIVATE_DATA privateData) +{ + Rx_CompleteMulticastUpdate (privateData); +} + +void GptCB_RestartBurst(PPRIVATE_DATA privateData) +{ + if(privateData->RxFlowControlActive) { + privateData->RxFlowBurstActive=true; + if(privateData->RxFlowBurstWorkLoad>privateData->RxFlowBurstMaxWorkLoad) { + privateData->RxFlowBurstWorkLoad-=privateData->RxFlowBurstMaxWorkLoad; + } else { + privateData->RxFlowBurstWorkLoad=0; + } + Gpt_ScheduleCallBack(privateData,GptCB_RestartBurst, + privateData->RxFlowParameters.BurstPeriod); + } + Lan_EnableInterrupt(privateData,privateData->RxInterrupts); +} + +void GptCB_MeasureRxThroughput(PPRIVATE_DATA privateData) +{ + if(privateData->RxFlowMeasuredMaxThroughputRxFlowCurrentThroughput) { + privateData->RxFlowMeasuredMaxThroughput=privateData->RxFlowCurrentThroughput; + } + if(privateData->RxFlowMeasuredMaxPacketCountRxFlowCurrentPacketCount) { + privateData->RxFlowMeasuredMaxPacketCount=privateData->RxFlowCurrentPacketCount; + } + if(privateData->RxFlowCurrentThroughput!=0) { + if(privateData->RxFlowMaxWorkLoad!=0) { + if(!(privateData->RxFlowControlActive)) { + u32 activationLevel= + (privateData->RxFlowMaxWorkLoad*(100+RX_FLOW_ACTIVATION))/100; + if(privateData->RxFlowCurrentWorkLoad>=activationLevel) { + privateData->RxFlowControlActive=true; + privateData->RxFlowBurstActive=true; + privateData->RxFlowBurstWorkLoad=0; + Gpt_ScheduleCallBack(privateData,GptCB_RestartBurst, + privateData->RxFlowParameters.BurstPeriod); + //SET_GPIO(GP_TX); + } + } else { + u32 deactivationLevel= + (privateData->RxFlowMaxWorkLoad*(100-RX_FLOW_DEACTIVATION))/100; + if(privateData->RxFlowCurrentWorkLoad<=deactivationLevel) { + privateData->RxFlowControlActive=false; + //CLEAR_GPIO(GP_TX); + } + } + } + privateData->RxFlowCurrentThroughput=0; + privateData->RxFlowCurrentPacketCount=0; + privateData->RxFlowCurrentWorkLoad=0; + Gpt_ScheduleCallBack(privateData,GptCB_MeasureRxThroughput,1000); + } else { + if(privateData->RxFlowMaxWorkLoad!=0) { + if(privateData->RxFlowControlActive) { + privateData->RxFlowControlActive=false; + //CLEAR_GPIO(GP_TX); + } + } + privateData->MeasuringRxThroughput=false; + } +} + +irqreturn_t Smsc9118_ISR(int Irq, void *dev_id) +{ + u32 dwIntCfg=0; + u32 dwIntSts=0; + u32 dwIntEn=0; + u32 dwIntBits=0; + PPRIVATE_DATA privateData=(PPRIVATE_DATA)dev_id; + bool serviced=false; + + Irq=Irq;//make lint happy + + if(privateData==NULL) { + SMSC_WARNING("Smsc9118_ISR(privateData==NULL)"); + goto DONE; + } + if(privateData->dwLanBase==0) { + SMSC_WARNING("Smsc9118_ISR(dwLanBase==0)"); + goto DONE; + } + SET_GPIO(GP_ISR); + dwIntCfg=Lan_GetRegDW(INT_CFG); + if((dwIntCfg&0x00001100)!=0x00001100) { + SMSC_TRACE("In ISR, not my interrupt, dwIntCfg=0x%08X", + dwIntCfg); + goto ALMOST_DONE; + } + + { + /* + * KH: Neither is true for 9210 + u32 reservedBits; + if(OLD_REGISTERS(privateData)) { + reservedBits=0x00FFEEEEUL; + } else { + reservedBits=0x00FFCEEEUL; + } + */ + /* + reservedBits = 0x00FF8EEEUL; + if(dwIntCfg&reservedBits) { + SMSC_WARNING("In ISR, reserved bits are high.\n"); + SMSC_TRACE("(reserved=0x%08X int=0x%08X)\n", reservedBits, dwIntCfg); + //this could mean surprise removal + goto ALMOST_DONE; + } + */ + } + + dwIntSts=Lan_GetRegDW(INT_STS); + dwIntEn=Lan_GetRegDW(INT_EN); + dwIntBits=dwIntSts&dwIntEn; + //SMSC_TRACE("dwIntBits= 0x%x8l \n", dwIntBits); + privateData->LastIntStatus3=privateData->LastIntStatus2; + privateData->LastIntStatus2=privateData->LastIntStatus1; + privateData->LastIntStatus1=dwIntBits; + if(Lan_HandleSoftwareInterrupt(privateData,dwIntBits)) { + serviced=true; + } + if(Gpt_HandleInterrupt(privateData,dwIntBits)) { + serviced=true; + } + if(Tx_HandleInterrupt(privateData,dwIntBits)) { + serviced=true; + } + + if(RxStop_HandleInterrupt(privateData,dwIntBits)) { + serviced=true; + } + + + if(Rx_HandleInterrupt(privateData,dwIntBits)) { + serviced=true; + } + + if(!serviced) { + SMSC_WARNING("unserviced interrupt dwIntCfg=0x%08X,dwIntSts=0x%08X,dwIntEn=0x%08X,dwIntBits=0x%08X", + dwIntCfg,dwIntSts,dwIntEn,dwIntBits); + } + +ALMOST_DONE: + CLEAR_GPIO(GP_ISR); +DONE: + return IRQ_RETVAL(serviced); +} + +#ifdef USE_PHY_WORK_AROUND +bool Phy_Reset(PPRIVATE_DATA privateData,VL_KEY keyCode) +{ + bool result=false; + WORD wTemp=0; + u32 dwLoopCount=100000; + SMSC_TRACE("Performing PHY BCR Reset"); + Phy_SetRegW(privateData,PHY_BCR,PHY_BCR_RESET_,keyCode); + do { + udelay(10); + wTemp=Phy_GetRegW(privateData,PHY_BCR,keyCode); + dwLoopCount--; + } while((dwLoopCount>0)&&(wTemp&PHY_BCR_RESET_)); + if(wTemp&PHY_BCR_RESET_) { + SMSC_WARNING("Phy Reset failed to complete."); + goto DONE; + } + //extra delay required because the phy may not be completed with its reset + // when PHY_BCR_RESET_ is cleared. + // They say 256 uS is enough delay but I'm using 500 here to be safe + udelay(500); + result=true; +DONE: + return result; +} + +u32 Phy_LBT_GetTxStatus(PPRIVATE_DATA privateData) +{ + u32 result=Lan_GetRegDW(TX_FIFO_INF); + if(OLD_REGISTERS(privateData)) { + result&=TX_FIFO_INF_TSFREE_; + if(result!=0x00800000UL) { + result=Lan_GetRegDW(TX_STATUS_FIFO); + } else { + result=0; + } + } else { + result&=TX_FIFO_INF_TSUSED_; + if(result!=0x00000000UL) { + result=Lan_GetRegDW(TX_STATUS_FIFO); + } else { + result=0; + } + } + return result; +} + +u32 Phy_LBT_GetRxStatus(PPRIVATE_DATA privateData) +{ + u32 result=Lan_GetRegDW(RX_FIFO_INF); + if(result&0x00FF0000UL) { + //Rx status is available, read it + result=Lan_GetRegDW(RX_STATUS_FIFO); + } else { + result=0; + } + return result; +} + +bool Phy_TransmitTestPacket(PPRIVATE_DATA privateData) +{ + bool result=false; + u32 dwLoopCount=0; + u32 dwTxCmdA=0; + u32 dwTxCmdB=0; + u32 dwStatus=0; + + //write Tx Packet to 118 + dwTxCmdA= + ((((u32)(privateData->LoopBackTxPacket))&0x03UL)<<16) | //u32 alignment adjustment + TX_CMD_A_INT_FIRST_SEG_ | TX_CMD_A_INT_LAST_SEG_ | + ((u32)(MIN_PACKET_SIZE)); + dwTxCmdB= + (((u32)(MIN_PACKET_SIZE))<<16) | + ((u32)(MIN_PACKET_SIZE)); + Lan_SetRegDW(TX_DATA_FIFO,dwTxCmdA); + Lan_SetRegDW(TX_DATA_FIFO,dwTxCmdB); + Platform_WriteFifo( + privateData->dwLanBase, + (u32 *)(((u32)(privateData->LoopBackTxPacket))&0xFFFFFFFCUL), + (((u32)(MIN_PACKET_SIZE))+3+ + (((u32)(privateData->LoopBackTxPacket))&0x03UL))>>2); + + //wait till transmit is done + dwLoopCount=60; + while((dwLoopCount>0)&&((dwStatus=Phy_LBT_GetTxStatus(privateData))==0)) { + udelay(5); + dwLoopCount--; + } + if(dwStatus==0) { + SMSC_WARNING("Failed to Transmit during Packet Test"); + goto DONE; + } + if(dwStatus&0x00008000UL) { + SMSC_WARNING("Transmit encountered errors during Packet Test"); + goto DONE; + } +DONE: + return result; +} + +bool Phy_CheckLoopBackPacket(PPRIVATE_DATA privateData) + +{ + bool result=false; + u32 tryCount=0; + u32 dwLoopCount=0; + for(tryCount=0;tryCount<10;tryCount++) + { + u32 dwTxCmdA=0; + u32 dwTxCmdB=0; + u32 dwStatus=0; + u32 dwPacketLength=0; + + //zero-out Rx Packet memory + memset(privateData->LoopBackRxPacket,0,MIN_PACKET_SIZE); + + //write Tx Packet to 118 + dwTxCmdA= + ((((u32)(privateData->LoopBackTxPacket))&0x03UL)<<16) | //u32 alignment adjustment + TX_CMD_A_INT_FIRST_SEG_ | TX_CMD_A_INT_LAST_SEG_ | + ((u32)(MIN_PACKET_SIZE)); + dwTxCmdB= + (((u32)(MIN_PACKET_SIZE))<<16) | + ((u32)(MIN_PACKET_SIZE)); + Lan_SetRegDW(TX_DATA_FIFO,dwTxCmdA); + Lan_SetRegDW(TX_DATA_FIFO,dwTxCmdB); + Platform_WriteFifo( + privateData->dwLanBase, + (u32 *)(((u32)(privateData->LoopBackTxPacket))&0xFFFFFFFCUL), + (((u32)(MIN_PACKET_SIZE))+3+ + (((u32)(privateData->LoopBackTxPacket))&0x03UL))>>2); + + //wait till transmit is done + dwLoopCount=60; + while((dwLoopCount>0)&&((dwStatus=Phy_LBT_GetTxStatus(privateData))==0)) { + udelay(5); + dwLoopCount--; + } + if(dwStatus==0) { + SMSC_WARNING("Failed to Transmit during Loop Back Test"); + continue; + } + if(dwStatus&0x00008000UL) { + SMSC_WARNING("Transmit encountered errors during Loop Back Test"); + continue; + } + + //wait till receive is done + dwLoopCount=60; + while((dwLoopCount>0)&&((dwStatus=Phy_LBT_GetRxStatus(privateData))==0)) + { + udelay(5); + dwLoopCount--; + } + if(dwStatus==0) { + SMSC_WARNING("Failed to Receive during Loop Back Test"); + continue; + } + if(dwStatus&RX_STS_ES_) + { + SMSC_WARNING("Receive encountered errors during Loop Back Test"); + continue; + } + + dwPacketLength=((dwStatus&0x3FFF0000UL)>>16); + + Platform_ReadFifo( + privateData->dwLanBase, + ((u32 *)(privateData->LoopBackRxPacket)), + (dwPacketLength+3+(((u32)(privateData->LoopBackRxPacket))&0x03UL))>>2); + + if(dwPacketLength!=(MIN_PACKET_SIZE+4)) { + SMSC_WARNING("Unexpected packet size during loop back test, size=%d, will retry",dwPacketLength); + } else { + u32 byteIndex=0; + bool foundMissMatch=false; + for(byteIndex=0;byteIndexLoopBackTxPacket[byteIndex]!=privateData->LoopBackRxPacket[byteIndex]) + { + foundMissMatch=true; + break; + } + } + if(!foundMissMatch) { + SMSC_TRACE("Successfully Verified Loop Back Packet"); + result=true; + goto DONE; + } else { + SMSC_WARNING("Data miss match during loop back test, will retry."); + } + } + } +DONE: + return result; +} + +bool Phy_LoopBackTest(PPRIVATE_DATA privateData) +{ + bool result=false; + u32 byteIndex=0; + u32 tryCount=0; + // u32 failed=0; + //Initialize Tx Packet + for(byteIndex=0;byteIndex<6;byteIndex++) { + //use broadcast destination address + privateData->LoopBackTxPacket[byteIndex]=(BYTE)0xFF; + } + for(byteIndex=6;byteIndex<12;byteIndex++) { + //use incrementing source address + privateData->LoopBackTxPacket[byteIndex]=(BYTE)byteIndex; + } + //Set length type field + privateData->LoopBackTxPacket[12]=0x00; + privateData->LoopBackTxPacket[13]=0x00; + for(byteIndex=14;byteIndexLoopBackTxPacket[byteIndex]=(BYTE)byteIndex; + } + //TRY_AGAIN: + { + u32 dwRegVal=Lan_GetRegDW(HW_CFG); + dwRegVal&=(HW_CFG_TX_FIF_SZ_|0x00000FFFUL); + dwRegVal|=HW_CFG_SF_; + Lan_SetRegDW(HW_CFG,dwRegVal); + } + Lan_SetRegDW(TX_CFG,TX_CFG_TX_ON_); + + Lan_SetRegDW(RX_CFG,(((u32)(privateData->LoopBackRxPacket))&0x03)<<8); + + { + + unsigned long dwIntFlags=0; + VL_KEY keyCode=Vl_WaitForLock(&(privateData->MacPhyLock),&dwIntFlags); + //Set Phy to 10/FD, no ANEG, + Phy_SetRegW(privateData,PHY_BCR,0x0100,keyCode); + + //enable MAC Tx/Rx, FD + Mac_SetRegDW(privateData,MAC_CR,MAC_CR_FDPX_|MAC_CR_TXEN_|MAC_CR_RXEN_,keyCode); + + // Phy_TransmitTestPacket(privateData); + + //set Phy to loopback mode + Phy_SetRegW(privateData,PHY_BCR,0x4100,keyCode); + + for(tryCount=0;tryCount<10;tryCount++) { + if(Phy_CheckLoopBackPacket(privateData)) + { + result=true; + goto DONE; + } + privateData->dwResetCount++; + //disable MAC rx + Mac_SetRegDW(privateData,MAC_CR,0UL,keyCode); + Phy_Reset(privateData,keyCode); + + //Set Phy to 10/FD, no ANEG, and Loopbackmode + Phy_SetRegW(privateData,PHY_BCR,0x4100,keyCode); + + //enable MAC Tx/Rx, FD + Mac_SetRegDW(privateData,MAC_CR,MAC_CR_FDPX_|MAC_CR_TXEN_|MAC_CR_RXEN_,keyCode); + } + // if(failed<2) { + // if(tryCount>=10) { + // u32 timeOut=10000; + // Lan_ShowRegs(privateData); + // SMSC_TRACE("Performing full reset"); + // privateData->Lan9118->HW_CFG=HW_CFG_SRST_; + // while((timeOut>0)&&(privateData->Lan9118->HW_CFG&HW_CFG_SRST_)) { + // udelay(1); + // timeOut--; + // } + // failed++; + // goto TRY_AGAIN; + // } + // } +DONE: + //disable MAC + Mac_SetRegDW(privateData,MAC_CR,0UL,keyCode); + //Cancel Phy loopback mode + Phy_SetRegW(privateData,PHY_BCR,0U,keyCode); + Vl_ReleaseLock(&(privateData->MacPhyLock),keyCode,&dwIntFlags); + } + + Lan_SetRegDW(TX_CFG,0UL); + Lan_SetRegDW(RX_CFG,0UL); + + return result; +} + +#endif //USE_PHY_WORK_AROUND +void Phy_SetLink(PPRIVATE_DATA privateData, + u32 dwLinkRequest) +{ + unsigned long dwIntFlags=0; + VL_KEY keyCode=Vl_WaitForLock(&(privateData->MacPhyLock),&dwIntFlags); + if(dwLinkRequest&LINK_AUTO_NEGOTIATE) { + WORD wTemp; + wTemp=Phy_GetRegW(privateData, + PHY_ANEG_ADV,keyCode); + wTemp&=~PHY_ANEG_ADV_PAUSE_; + if(dwLinkRequest&LINK_ASYMMETRIC_PAUSE) { + wTemp|=PHY_ANEG_ADV_ASYMP_; + } + if(dwLinkRequest&LINK_SYMMETRIC_PAUSE) { + wTemp|=PHY_ANEG_ADV_SYMP_; + } + wTemp&=~PHY_ANEG_ADV_SPEED_; + if(dwLinkRequest&LINK_SPEED_10HD) { + wTemp|=PHY_ANEG_ADV_10H_; + } + if(dwLinkRequest&LINK_SPEED_10FD) { + wTemp|=PHY_ANEG_ADV_10F_; + } + if(dwLinkRequest&LINK_SPEED_100HD) { + wTemp|=PHY_ANEG_ADV_100H_; + } + if(dwLinkRequest&LINK_SPEED_100FD) { + wTemp|=PHY_ANEG_ADV_100F_; + } + Phy_SetRegW(privateData,PHY_ANEG_ADV,wTemp,keyCode); + + // begin to establish link + privateData->dwRemoteFaultCount=0; + Phy_SetRegW(privateData, + PHY_BCR, + PHY_BCR_AUTO_NEG_ENABLE_| + PHY_BCR_RESTART_AUTO_NEG_, + keyCode); + } else { + WORD wTemp=0; + if(dwLinkRequest&(LINK_SPEED_100FD)) { + dwLinkRequest=LINK_SPEED_100FD; + } else if(dwLinkRequest&(LINK_SPEED_100HD)) { + dwLinkRequest=LINK_SPEED_100HD; + } else if(dwLinkRequest&(LINK_SPEED_10FD)) { + dwLinkRequest=LINK_SPEED_10FD; + } else if(dwLinkRequest&(LINK_SPEED_10HD)) { + dwLinkRequest=LINK_SPEED_10HD; + } + if(dwLinkRequest&(LINK_SPEED_10FD|LINK_SPEED_100FD)) { + wTemp|=PHY_BCR_DUPLEX_MODE_; + } + if(dwLinkRequest&(LINK_SPEED_100HD|LINK_SPEED_100FD)) { + wTemp|=PHY_BCR_SPEED_SELECT_; + } + Phy_SetRegW(privateData,PHY_BCR,wTemp,keyCode); + } + Vl_ReleaseLock(&(privateData->MacPhyLock),keyCode,&dwIntFlags); +} + +void Phy_SetAutoMdixSts(PPRIVATE_DATA privateData, + WORD wAutoMdixSts) +{ + WORD SpecialCtrlSts=0U; + + if (((privateData->dwGeneration)>2) && (!(privateData->ExtPhy))) + { + if (wAutoMdixSts > 2) + { + unsigned long dwIntFlags=0; + VL_KEY keyCode=Vl_WaitForLock(&(privateData->MacPhyLock),&dwIntFlags); + SpecialCtrlSts=Phy_GetRegW(privateData, SPECIAL_CTRL_STS,keyCode); + SpecialCtrlSts = (SpecialCtrlSts&0x1FFF); + Phy_SetRegW(privateData, SPECIAL_CTRL_STS,SpecialCtrlSts,keyCode); + Vl_ReleaseLock(&(privateData->MacPhyLock),keyCode,&dwIntFlags); + + if (Lan_GetRegDW(HW_CFG) & HW_CFG_AMDIX_EN_STRAP_STS_) { + SMSC_TRACE("Auto-MDIX Enable by default!!!"); + } + else { + SMSC_TRACE("Auto-MDIX Disable by default!!!"); + } + } + else + { + + unsigned long dwIntFlags=0; + VL_KEY keyCode=Vl_WaitForLock(&(privateData->MacPhyLock),&dwIntFlags); + SpecialCtrlSts=Phy_GetRegW(privateData, SPECIAL_CTRL_STS,keyCode); + SpecialCtrlSts = (((wAutoMdixSts+4) << 13) | (SpecialCtrlSts&0x1FFF)); + Phy_SetRegW(privateData, SPECIAL_CTRL_STS,SpecialCtrlSts,keyCode); + Vl_ReleaseLock(&(privateData->MacPhyLock),keyCode,&dwIntFlags); + + if (wAutoMdixSts & AMDIX_ENABLE) { + SMSC_TRACE("Override Strap, Enable Auto-MDIX "); + } else if (wAutoMdixSts & AMDIX_DISABLE_CROSSOVER) { + SMSC_TRACE("Override Strap, Disable Auto-MDIX, CrossOver Cable"); + } else { + SMSC_TRACE("Override Strap, Disable Auto-MDIX, Straight Cable"); + } + + } + } + + else { + SMSC_TRACE("This chip or PHY doesn't support HP AMDIX!!!"); + } + +} + +void Phy_GetAutoMdixSts(PPRIVATE_DATA privateData) +{ + + + WORD SpecialCtrlSts=0U; + unsigned long dwIntFlags=0; + + if (((privateData->dwGeneration)>2) && (!(privateData->ExtPhy))) + { + VL_KEY keyCode=Vl_WaitForLock(&(privateData->MacPhyLock),&dwIntFlags); + SpecialCtrlSts=Phy_GetRegW(privateData, SPECIAL_CTRL_STS,keyCode); + Vl_ReleaseLock(&(privateData->MacPhyLock),keyCode,&dwIntFlags); + + if (SpecialCtrlSts & SPECIAL_CTRL_STS_OVRRD_AMDIX_) { + + if (SpecialCtrlSts & SPECIAL_CTRL_STS_AMDIX_ENABLE_) { + SMSC_TRACE("AutoMdix Status: Override Strap, Enable Auto Mdix"); + } + else if (SpecialCtrlSts & SPECIAL_CTRL_STS_AMDIX_STATE_) { + + SMSC_TRACE("AutoMdix Status: Override Strap, Disable Auto Mdix, CrossOver Cable"); + + } else { + + SMSC_TRACE("AutoMdix Status: Override Strap, Disable Auto Mdix, Straight Cable"); + } + + } + else { + if (Lan_GetRegDW(HW_CFG) & HW_CFG_AMDIX_EN_STRAP_STS_) { + SMSC_TRACE("AutoMdix Status: Enable by default!!!"); + } + else { + SMSC_TRACE("AutoMdix Status: Disable by default!!!"); + } + } + + } + else { + SMSC_TRACE("This chip or PHY doesn't support HP AMDIX!!!"); + } + +} + + +bool Phy_Initialize( + PPRIVATE_DATA privateData, + u32 dwPhyAddr, + u32 dwLinkRequest) +{ + bool result=false; + u32 dwTemp=0; + WORD wTemp=0; + u32 dwLoopCount=0; + // WORD SpecialCtrlSts=0U; + + SMSC_TRACE("-->Phy_Initialize"); + SMSC_ASSERT(privateData!=NULL); + SMSC_ASSERT(privateData->dwLanBase!=0); + SMSC_ASSERT(dwLinkRequest<=0x7FUL); + privateData->ExtPhy=false; + + if(dwPhyAddr!=0xFFFFFFFFUL) { + switch(privateData->dwIdRev&0xFFFF0000) { + case 0x117A0000UL: + case 0x115A0000UL: + goto EXTERNAL_PHY_SUPPORTED; + case 0x01170000UL: + case 0x01150000UL: + if(privateData->dwIdRev&0x0000FFFF) { + u32 dwHwCfg=0; +EXTERNAL_PHY_SUPPORTED: + dwHwCfg=Lan_GetRegDW(HW_CFG); + if(dwHwCfg&HW_CFG_EXT_PHY_DET_) { + //External phy is requested, supported, and detected + //Attempt to switch + //NOTE: Assuming Rx and Tx are stopped + // because Phy_Initialize is called before + // Rx_Initialize and Tx_Initialize + WORD wPhyId1=0; + WORD wPhyId2=0; + + //Disable phy clocks to the mac + dwHwCfg&= (~HW_CFG_PHY_CLK_SEL_); + dwHwCfg|= HW_CFG_PHY_CLK_SEL_CLK_DIS_; + Lan_SetRegDW(HW_CFG,dwHwCfg); + udelay(10);//wait for clocks to acutally stop + + dwHwCfg|=HW_CFG_EXT_PHY_EN_; + Lan_SetRegDW(HW_CFG,dwHwCfg); + + dwHwCfg&= (~HW_CFG_PHY_CLK_SEL_); + dwHwCfg|= HW_CFG_PHY_CLK_SEL_EXT_PHY_; + Lan_SetRegDW(HW_CFG,dwHwCfg); + udelay(10);//wait for clocks to actually start + + dwHwCfg|=HW_CFG_SMI_SEL_; + Lan_SetRegDW(HW_CFG,dwHwCfg); + + { + unsigned long dwIntFlags=0; + VL_KEY keyCode=Vl_WaitForLock(&(privateData->MacPhyLock),&dwIntFlags); + if(dwPhyAddr<=31) { + //only check the phy address specified + privateData->dwPhyAddress=dwPhyAddr; + wPhyId1=Phy_GetRegW(privateData,PHY_ID_1,keyCode); + wPhyId2=Phy_GetRegW(privateData,PHY_ID_2,keyCode); + } else { + //auto detect phy + u32 address=0; + for(address=0;address<=31;address++) { + privateData->dwPhyAddress=address; + wPhyId1=Phy_GetRegW(privateData,PHY_ID_1,keyCode); + wPhyId2=Phy_GetRegW(privateData,PHY_ID_2,keyCode); + if((wPhyId1!=0xFFFFU)||(wPhyId2!=0xFFFFU)) { + SMSC_TRACE("Detected Phy at address = 0x%02X = %d", + address,address); + break; + } + } + if(address>=32) { + SMSC_WARNING("Failed to auto detect external phy"); + } + } + Vl_ReleaseLock(&(privateData->MacPhyLock),keyCode,&dwIntFlags); + } + if((wPhyId1==0xFFFFU)&&(wPhyId2==0xFFFFU)) { + SMSC_WARNING("External Phy is not accessable"); + SMSC_WARNING(" using internal phy instead"); + //revert back to interal phy settings. + + //Disable phy clocks to the mac + dwHwCfg&= (~HW_CFG_PHY_CLK_SEL_); + dwHwCfg|= HW_CFG_PHY_CLK_SEL_CLK_DIS_; + Lan_SetRegDW(HW_CFG,dwHwCfg); + udelay(10);//wait for clocks to actually stop + + dwHwCfg&=(~HW_CFG_EXT_PHY_EN_); + Lan_SetRegDW(HW_CFG,dwHwCfg); + + dwHwCfg&= (~HW_CFG_PHY_CLK_SEL_); + dwHwCfg|= HW_CFG_PHY_CLK_SEL_INT_PHY_; + Lan_SetRegDW(HW_CFG,dwHwCfg); + udelay(10);//wait for clocks to actually start + + dwHwCfg&=(~HW_CFG_SMI_SEL_); + Lan_SetRegDW(HW_CFG,dwHwCfg); + goto USE_INTERNAL_PHY; + } else { + SMSC_TRACE("Successfully switched to external phy"); + privateData->ExtPhy=true; +#ifdef USE_LED1_WORK_AROUND + privateData->NotUsingExtPhy=0; +#endif + } + } else { + SMSC_WARNING("No External Phy Detected"); + SMSC_WARNING(" using internal phy instead"); + goto USE_INTERNAL_PHY; + } + } else { + SMSC_WARNING("External Phy is not supported"); + SMSC_WARNING(" using internal phy instead"); + goto USE_INTERNAL_PHY; + };break; + default: + SMSC_WARNING("External Phy is not supported"); + SMSC_WARNING(" using internal phy instead"); + goto USE_INTERNAL_PHY; + } + } else { +USE_INTERNAL_PHY: + + privateData->dwPhyAddress=1; + privateData->ExtPhy=false; +#ifdef USE_LED1_WORK_AROUND + if(privateData->dwGeneration<=2) { + privateData->NotUsingExtPhy=1; + } else { + //Generation 3 or higher has the LED problem fixed + // to disable the workaround pretend the phy is external + privateData->NotUsingExtPhy=0; + } +#endif + + Phy_SetAutoMdixSts(privateData,AutoMdix); + } + + { + unsigned long dwIntFlags=0; + VL_KEY keyCode=Vl_WaitForLock(&(privateData->MacPhyLock),&dwIntFlags); + dwTemp=Phy_GetRegW(privateData,PHY_ID_2,keyCode); + privateData->bPhyRev=((BYTE)(dwTemp&(0x0FUL))); + privateData->bPhyModel=((BYTE)((dwTemp>>4)&(0x3FUL))); + privateData->dwPhyId=((dwTemp&(0xFC00UL))<<8); + dwTemp=Phy_GetRegW(privateData,PHY_ID_1,keyCode); + privateData->dwPhyId|=((dwTemp&(0x0000FFFFUL))<<2); + + SMSC_TRACE("dwPhyId==0x%08X,bPhyModel==0x%02X,bPhyRev==0x%02X", + privateData->dwPhyId, + privateData->bPhyModel, + privateData->bPhyRev); + + privateData->dwLinkSpeed=LINK_OFF; + privateData->dwLinkSettings=LINK_OFF; + //reset the PHY + Phy_SetRegW(privateData,PHY_BCR,PHY_BCR_RESET_,keyCode); + dwLoopCount=100000; + do { + + udelay(10); + wTemp=Phy_GetRegW(privateData,PHY_BCR,keyCode); + dwLoopCount--; + } while((dwLoopCount>0) && (wTemp&PHY_BCR_RESET_)); + Vl_ReleaseLock(&(privateData->MacPhyLock),keyCode,&dwIntFlags); + } + + if(wTemp&PHY_BCR_RESET_) { + SMSC_WARNING("PHY reset failed to complete."); + goto DONE; + } + +#ifdef USE_PHY_WORK_AROUND + if(privateData->dwGeneration<=2) { + // printk("phy_LoopBackTest\n"); + if(!Phy_LoopBackTest(privateData)) { + SMSC_WARNING("Failed Loop back test"); + goto DONE; + } else { + SMSC_TRACE("Passed Loop Back Test"); + } + } +#endif + + Phy_SetLink(privateData,dwLinkRequest); + + init_timer(&(privateData->LinkPollingTimer)); + privateData->LinkPollingTimer.function=Phy_CheckLink; + privateData->LinkPollingTimer.data=(unsigned long)privateData; + privateData->LinkPollingTimer.expires=jiffies+HZ; + add_timer(&(privateData->LinkPollingTimer)); + + result=true; +DONE: + SMSC_TRACE("<--Phy_Initialize, result=%s",result?"true":"false"); + return result; +} + +WORD Phy_GetRegW( + PPRIVATE_DATA privateData, + u32 dwRegIndex, + VL_KEY keyCode) +{ + u32 dwAddr=0; + int i=0; + WORD result=0xFFFFU; + + SMSC_ASSERT(privateData!=NULL); + SMSC_ASSERT(privateData->LanInitialized==true); + SMSC_ASSERT(Vl_CheckLock(&(privateData->MacPhyLock),keyCode)); + + // confirm MII not busy + if ((Mac_GetRegDW(privateData, MII_ACC,keyCode) & MII_ACC_MII_BUSY_) != 0UL) + { + SMSC_WARNING("MII is busy in Phy_GetRegW???"); + result=0; + goto DONE; + } + + // set the address, index & direction (read from PHY) + dwAddr = ((privateData->dwPhyAddress&0x1FUL)<<11) | ((dwRegIndex & 0x1FUL)<<6); + Mac_SetRegDW(privateData, MII_ACC, dwAddr,keyCode); + + // wait for read to complete w/ timeout + for(i=0;i<100;i++) { + // see if MII is finished yet + if ((Mac_GetRegDW(privateData, MII_ACC,keyCode) & MII_ACC_MII_BUSY_) == 0UL) + { + // get the read data from the MAC & return i + result=((WORD)Mac_GetRegDW(privateData, MII_DATA,keyCode)); + goto DONE; + } + } + SMSC_WARNING("timeout waiting for MII write to finish"); + +DONE: + return result; +} + +void Phy_SetRegW( + PPRIVATE_DATA privateData, + u32 dwRegIndex,WORD wVal, + VL_KEY keyCode) +{ + u32 dwAddr=0; + int i=0; + + SMSC_ASSERT(privateData!=NULL); + SMSC_ASSERT(privateData->LanInitialized==true); + + SMSC_ASSERT(Vl_CheckLock(&(privateData->MacPhyLock),keyCode)); + + if(dwRegIndex==0) { + if((wVal&0x1200)==0x1200) { + privateData->wLastADVatRestart=privateData->wLastADV; + } + } + if(dwRegIndex==4) { + privateData->wLastADV=wVal; + } + + // confirm MII not busy + if ((Mac_GetRegDW(privateData, MII_ACC,keyCode) & MII_ACC_MII_BUSY_) != 0UL) + { + SMSC_WARNING("MII is busy in Phy_SetRegW???"); + goto DONE; + } + + // put the data to write in the MAC + Mac_SetRegDW(privateData, MII_DATA, (u32)wVal,keyCode); + + // set the address, index & direction (write to PHY) + dwAddr = ((privateData->dwPhyAddress&0x1FUL)<<11) | ((dwRegIndex & 0x1FUL)<<6) | MII_ACC_MII_WRITE_; + Mac_SetRegDW(privateData, MII_ACC, dwAddr,keyCode); + + // wait for write to complete w/ timeout + for(i=0;i<100;i++) { + // see if MII is finished yet + if ((Mac_GetRegDW(privateData, MII_ACC,keyCode) & MII_ACC_MII_BUSY_) == 0UL) + { + goto DONE; + } + } + SMSC_WARNING("timeout waiting for MII write to finish"); +DONE: + return; +} + +void Phy_UpdateLinkMode(PPRIVATE_DATA privateData) +{ + u32 dwOldLinkSpeed=privateData->dwLinkSpeed; + unsigned long dwIntFlags=0; + VL_KEY keyCode=Vl_WaitForLock(&(privateData->MacPhyLock),&dwIntFlags); + + Phy_GetLinkMode(privateData,keyCode); + + if(dwOldLinkSpeed!=(privateData->dwLinkSpeed)) { + if(privateData->dwLinkSpeed!=LINK_OFF) { + u32 dwRegVal=0; + switch(privateData->dwLinkSpeed) { + case LINK_SPEED_10HD: + SMSC_TRACE("Link is now UP at 10Mbps HD"); + break; + case LINK_SPEED_10FD: + SMSC_TRACE("Link is now UP at 10Mbps FD"); + break; + case LINK_SPEED_100HD: + SMSC_TRACE("Link is now UP at 100Mbps HD"); + break; + case LINK_SPEED_100FD: + SMSC_TRACE("Link is now UP at 100Mbps FD"); + break; + default: + SMSC_WARNING("Link is now UP at Unknown Link Speed, dwLinkSpeed=0x%08X", + privateData->dwLinkSpeed); + break; + } + + dwRegVal=Mac_GetRegDW(privateData,MAC_CR,keyCode); + dwRegVal&=~(MAC_CR_FDPX_|MAC_CR_RCVOWN_); + switch(privateData->dwLinkSpeed) { + case LINK_SPEED_10HD: + case LINK_SPEED_100HD: + dwRegVal|=MAC_CR_RCVOWN_; + break; + case LINK_SPEED_10FD: + case LINK_SPEED_100FD: + dwRegVal|=MAC_CR_FDPX_; + break; + default:break;//make lint happy + } + + Mac_SetRegDW(privateData, + MAC_CR,dwRegVal,keyCode); + + if(privateData->dwLinkSettings&LINK_AUTO_NEGOTIATE) { + WORD linkPartner=0; + WORD localLink=0; + localLink=Phy_GetRegW(privateData,4,keyCode); + linkPartner=Phy_GetRegW(privateData,5,keyCode); + switch(privateData->dwLinkSpeed) { + case LINK_SPEED_10FD: + case LINK_SPEED_100FD: + if(((localLink&linkPartner)&((WORD)0x0400U)) != ((WORD)0U)) { + //Enable PAUSE receive and transmit + Mac_SetRegDW(privateData,FLOW,0xFFFF0002UL,keyCode); + Lan_SetBitsDW(AFC_CFG,(afc_cfg&0x0000000FUL)); + } else if(((localLink&((WORD)0x0C00U))==((WORD)0x0C00U)) && + ((linkPartner&((WORD)0x0C00U))==((WORD)0x0800U))) + { + //Enable PAUSE receive, disable PAUSE transmit + Mac_SetRegDW(privateData,FLOW,0xFFFF0002UL,keyCode); + Lan_ClrBitsDW(AFC_CFG,0x0000000FUL); + } else { + //Disable PAUSE receive and transmit + Mac_SetRegDW(privateData,FLOW,0UL,keyCode); + Lan_ClrBitsDW(AFC_CFG,0x0000000FUL); + };break; + case LINK_SPEED_10HD: + case LINK_SPEED_100HD: + Mac_SetRegDW(privateData,FLOW,0UL,keyCode); + Lan_SetBitsDW(AFC_CFG,0x0000000FUL); + break; + default:break;//make lint happy + } + SMSC_TRACE("LAN9118: %s,%s,%s,%s,%s,%s", + (localLink&PHY_ANEG_ADV_ASYMP_)?"ASYMP":" ", + (localLink&PHY_ANEG_ADV_SYMP_)?"SYMP ":" ", + (localLink&PHY_ANEG_ADV_100F_)?"100FD":" ", + (localLink&PHY_ANEG_ADV_100H_)?"100HD":" ", + (localLink&PHY_ANEG_ADV_10F_)?"10FD ":" ", + (localLink&PHY_ANEG_ADV_10H_)?"10HD ":" "); + + SMSC_TRACE("Partner: %s,%s,%s,%s,%s,%s", + (linkPartner&PHY_ANEG_LPA_ASYMP_)?"ASYMP":" ", + (linkPartner&PHY_ANEG_LPA_SYMP_)?"SYMP ":" ", + (linkPartner&PHY_ANEG_LPA_100FDX_)?"100FD":" ", + (linkPartner&PHY_ANEG_LPA_100HDX_)?"100HD":" ", + (linkPartner&PHY_ANEG_LPA_10FDX_)?"10FD ":" ", + (linkPartner&PHY_ANEG_LPA_10HDX_)?"10HD ":" "); + } else { + switch(privateData->dwLinkSpeed) { + case LINK_SPEED_10HD: + case LINK_SPEED_100HD: + Mac_SetRegDW(privateData,FLOW,0x0UL,keyCode); + Lan_SetBitsDW(AFC_CFG,0x0000000FUL); + break; + default: + Mac_SetRegDW(privateData,FLOW,0x0UL,keyCode); + Lan_ClrBitsDW(AFC_CFG,0x0000000FUL); + break; + } + } + netif_carrier_on(privateData->dev); + Tx_WakeQueue(privateData,0x01); +#ifdef USE_LED1_WORK_AROUND + if ((g_GpioSettingOriginal & GPIO_CFG_LED1_EN_) && + privateData->NotUsingExtPhy) + { + // Restore orginal GPIO configuration + g_GpioSetting = g_GpioSettingOriginal; + Lan_SetRegDW(GPIO_CFG,g_GpioSetting); + } +#endif // USE_LED1_WORK_AROUND + } else { + SMSC_TRACE("Link is now DOWN"); + Tx_StopQueue(privateData,0x01); + netif_carrier_off(privateData->dev); + Mac_SetRegDW(privateData,FLOW,0UL,keyCode); + Lan_ClrBitsDW(AFC_CFG,0x0000000FUL); +#ifdef USE_LED1_WORK_AROUND + // Check global setting that LED1 usage is 10/100 indicator + // g_GpioSetting = Lan_GetRegDW(GPIO_CFG); + if ((g_GpioSetting & GPIO_CFG_LED1_EN_) && + privateData->NotUsingExtPhy) + { + //Force 10/100 LED off, after saving orginal GPIO configuration + g_GpioSettingOriginal = g_GpioSetting; + + g_GpioSetting &= ~GPIO_CFG_LED1_EN_; + g_GpioSetting |= + (GPIO_CFG_GPIOBUF0_|GPIO_CFG_GPIODIR0_|GPIO_CFG_GPIOD0_); + Lan_SetRegDW(GPIO_CFG,g_GpioSetting); + } +#endif // USE_LED1_WORK_AROUND + } + } + Vl_ReleaseLock(&(privateData->MacPhyLock),keyCode,&dwIntFlags); +} + +void Phy_CheckLink(unsigned long ptr) +{ + PPRIVATE_DATA privateData=(PPRIVATE_DATA)ptr; + if(privateData==NULL) { + SMSC_WARNING("Phy_CheckLink(ptr==0)"); + return; + } + + //must call this twice + Phy_UpdateLinkMode(privateData); + Phy_UpdateLinkMode(privateData); + + if(!(privateData->StopLinkPolling)) { + privateData->LinkPollingTimer.expires=jiffies+HZ; + add_timer(&(privateData->LinkPollingTimer)); + } +} + +void Phy_GetLinkMode( + PPRIVATE_DATA privateData, + VL_KEY keyCode) +{ + u32 result=LINK_OFF; + WORD wRegVal=0; + WORD wRegBSR=Phy_GetRegW( + privateData, + PHY_BSR,keyCode); + privateData->dwLinkSettings=LINK_OFF; + if(wRegBSR&PHY_BSR_LINK_STATUS_) { + wRegVal=Phy_GetRegW( + privateData, + PHY_BCR,keyCode); + if(wRegVal&PHY_BCR_AUTO_NEG_ENABLE_) { + u32 linkSettings=LINK_AUTO_NEGOTIATE; + WORD wRegADV=privateData->wLastADVatRestart; + // Phy_GetRegW( + // privateData, + // PHY_ANEG_ADV,keyCode); + WORD wRegLPA=Phy_GetRegW( + privateData, + PHY_ANEG_LPA,keyCode); + if(wRegADV&PHY_ANEG_ADV_ASYMP_) { + linkSettings|=LINK_ASYMMETRIC_PAUSE; + } + if(wRegADV&PHY_ANEG_ADV_SYMP_) { + linkSettings|=LINK_SYMMETRIC_PAUSE; + } + if(wRegADV&PHY_ANEG_LPA_100FDX_) { + linkSettings|=LINK_SPEED_100FD; + } + if(wRegADV&PHY_ANEG_LPA_100HDX_) { + linkSettings|=LINK_SPEED_100HD; + } + if(wRegADV&PHY_ANEG_LPA_10FDX_) { + linkSettings|=LINK_SPEED_10FD; + } + if(wRegADV&PHY_ANEG_LPA_10HDX_) { + linkSettings|=LINK_SPEED_10HD; + } + privateData->dwLinkSettings=linkSettings; + wRegLPA&=wRegADV; + if(wRegLPA&PHY_ANEG_LPA_100FDX_) { + result=LINK_SPEED_100FD; + } else if(wRegLPA&PHY_ANEG_LPA_100HDX_) { + result=LINK_SPEED_100HD; + } else if(wRegLPA&PHY_ANEG_LPA_10FDX_) { + result=LINK_SPEED_10FD; + } else if(wRegLPA&PHY_ANEG_LPA_10HDX_) { + result=LINK_SPEED_10HD; + } + } else { + if(wRegVal&PHY_BCR_SPEED_SELECT_) { + if(wRegVal&PHY_BCR_DUPLEX_MODE_) { + privateData->dwLinkSettings=result=LINK_SPEED_100FD; + } else { + privateData->dwLinkSettings=result=LINK_SPEED_100HD; + } + } else { + if(wRegVal&PHY_BCR_DUPLEX_MODE_) { + privateData->dwLinkSettings=result=LINK_SPEED_10FD; + } else { + privateData->dwLinkSettings=result=LINK_SPEED_10HD; + } + } + } + } + privateData->dwLinkSpeed=result; +} + +extern int smsc_prom_get_ethernet_mac_addr(char *addr); + +bool Mac_Initialize(PPRIVATE_DATA privateData) +{ + unsigned char ea[6]; + int result; + u32 dwHigh16, dwLow32; + unsigned long dwIntFlags = 0; + VL_KEY keyCode=Vl_WaitForLock(&(privateData->MacPhyLock),&dwIntFlags); + + SMSC_ASSERT(privateData!=NULL); +#ifdef CONFIG_MIPS_HMP10 + result = smsc_prom_get_ethernet_mac_addr(ea); +#else + result = prom_get_ethernet_addr(ea); +#endif + + if (result == 0) { + SMSC_TRACE("Got ethernet addr %2.2X:%2.2X:%2.2X:%2.2X:%2.2X:%2.2X from prom\n", + ea[0], ea[1], ea[2], ea[3], ea[4], ea[5] ); + dwHigh16 = (ea[5] << 8) | ea[4]; + Mac_SetRegDW(privateData, ADDRH, dwHigh16, keyCode); + dwLow32 = (ea[3] << 24) | (ea[2] << 16) | (ea[1] << 8) | ea[0]; + Mac_SetRegDW(privateData, ADDRL, dwLow32, keyCode); + } else { + SMSC_TRACE("Failed to get ethernet addr from prom\n"); + return result; + } + + return true; +} + +static bool MacNotBusy(PPRIVATE_DATA privateData, VL_KEY keyCode) +{ + int i=0; + SMSC_ASSERT(Vl_CheckLock(&(privateData->MacPhyLock),keyCode)); + // wait for MAC not busy, w/ timeout + for(i=0;i<40;i++) + { + if((Lan_GetRegDW(MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY_)==(0UL)) { + return true; + } + } + SMSC_WARNING("timeout waiting for MAC not BUSY. MAC_CSR_CMD = 0x%08X", + Lan_GetRegDW(MAC_CSR_CMD)); + return false; +} + +u32 Mac_GetRegDW(PPRIVATE_DATA privateData,u32 dwRegOffset,VL_KEY keyCode) +{ + u32 result=0xFFFFFFFFUL; + u32 dwTemp=0; + SMSC_ASSERT(privateData!=NULL); + SMSC_ASSERT(privateData->LanInitialized==true); + SMSC_ASSERT(Vl_CheckLock(&(privateData->MacPhyLock),keyCode)); + SMSC_ASSERT(privateData->dwLanBase!=0); + + // wait until not busy + if (Lan_GetRegDW(MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY_) + { + SMSC_WARNING("Mac_GetRegDW() failed, MAC already busy at entry"); + goto DONE; + } + + // send the MAC Cmd w/ offset + Lan_SetRegDW(MAC_CSR_CMD, + ((dwRegOffset & 0x000000FFUL) | + MAC_CSR_CMD_CSR_BUSY_ | MAC_CSR_CMD_R_NOT_W_)); + dwTemp=Lan_GetRegDW(BYTE_TEST);//to flush previous write + dwTemp=dwTemp; + + // wait for the read to happen, w/ timeout + if (!MacNotBusy(privateData,keyCode)) + { + SMSC_WARNING("Mac_GetRegDW() failed, waiting for MAC not busy after read"); + goto DONE; + } else { + // finally, return the read data + result=Lan_GetRegDW(MAC_CSR_DATA); + } +DONE: + return result; +} + +void Mac_SetRegDW(PPRIVATE_DATA privateData,u32 dwRegOffset,u32 dwVal,VL_KEY keyCode) +{ + u32 dwTemp=0; + SMSC_ASSERT(privateData!=NULL); + SMSC_ASSERT(privateData->LanInitialized==true); + SMSC_ASSERT(Vl_CheckLock(&(privateData->MacPhyLock),keyCode)); + SMSC_ASSERT(privateData->dwLanBase!=0); + + if (Lan_GetRegDW(MAC_CSR_CMD) & MAC_CSR_CMD_CSR_BUSY_) + { + SMSC_WARNING("Mac_SetRegDW() failed, MAC already busy at entry"); + goto DONE; + } + + // send the data to write + Lan_SetRegDW(MAC_CSR_DATA,dwVal); + + // do the actual write + Lan_SetRegDW(MAC_CSR_CMD,((dwRegOffset & 0x000000FFUL) | MAC_CSR_CMD_CSR_BUSY_)); + dwTemp=Lan_GetRegDW(BYTE_TEST);//force flush of previous write + dwTemp=dwTemp; + + // wait for the write to complete, w/ timeout + if (!MacNotBusy(privateData,keyCode)) + { + SMSC_WARNING("Mac_SetRegDW() failed, waiting for MAC not busy after write"); + } +DONE: + return; +} + +#define TX_FIFO_LOW_THRESHOLD (1600) +//#define Tx_Max_Fragments (86) //every fragment needs 6 bytes overhead. 1514+2(alignment)+6*86=2032 < 2036 + +void Tx_Initialize( + PPRIVATE_DATA privateData, + u32 dwTxDmaCh, + u32 dwDmaThreshold) +{ + u32 dwRegVal=0; + SMSC_ASSERT(privateData!=NULL); + SMSC_ASSERT(privateData->dwLanBase!=0); + + dwRegVal=Lan_GetRegDW(HW_CFG); + dwRegVal&=(HW_CFG_TX_FIF_SZ_|0x00000FFFUL); + dwRegVal|=HW_CFG_SF_; + Lan_SetRegDW(HW_CFG,dwRegVal); + + + if(privateData->UseTxCsum) + + //Set TX COE + { + unsigned long dwIntFlags=0; + VL_KEY keyCode=Vl_WaitForLock(&(privateData->MacPhyLock),&dwIntFlags); + u32 dwCoeCr=Mac_GetRegDW(privateData,COE_CR,keyCode); + dwCoeCr|=(TX_COE_EN); + Mac_SetRegDW(privateData,COE_CR,dwCoeCr,keyCode); + //printk("COE_CR = 0x%08x\n", Mac_GetRegDW(privateData,COE_CR,keyCode)); + Vl_ReleaseLock(&(privateData->MacPhyLock),keyCode,&dwIntFlags); + + } + + + + Lan_SetTDFL(privateData,0xFF); + Lan_EnableInterrupt(privateData,INT_EN_TDFA_EN_); + + privateData->dwTxDmaThreshold=dwDmaThreshold; + privateData->dwTxDmaCh=dwTxDmaCh; + if(dwTxDmaCh>=TRANSFER_PIO) { + SMSC_TRACE("Tx will use PIO"); + } else { + SMSC_TRACE("Tx will use DMA channel %d",dwTxDmaCh); + SMSC_ASSERT(Platform_IsValidDmaChannel(dwTxDmaCh)); + if(!Platform_DmaInitialize( + &(privateData->PlatformData), + dwTxDmaCh)) + { + SMSC_WARNING("Failed Platform_DmaInitialize, dwTxDmaCh=%u",dwTxDmaCh); + } + privateData->TxDmaXfer.dwLanReg=privateData->dwLanBase+TX_DATA_FIFO; + privateData->TxDmaXfer.pdwBuf=NULL;//this will be reset per dma request + privateData->TxDmaXfer.dwDmaCh=privateData->dwTxDmaCh; + privateData->TxDmaXfer.dwDwCnt=0;//this will be reset per dma request + privateData->TxDmaXfer.fMemWr=false; + } + + { + unsigned long dwIntFlags=0; + VL_KEY keyCode=Vl_WaitForLock(&(privateData->MacPhyLock),&dwIntFlags); + u32 dwMacCr=Mac_GetRegDW(privateData,MAC_CR,keyCode); + dwMacCr|=(MAC_CR_TXEN_|MAC_CR_HBDIS_); + Mac_SetRegDW(privateData,MAC_CR,dwMacCr,keyCode); + Lan_SetRegDW(TX_CFG,TX_CFG_TX_ON_); + Vl_ReleaseLock(&(privateData->MacPhyLock),keyCode,&dwIntFlags); + } + + privateData->TxSkb=NULL; + spin_lock_init(&(privateData->TxSkbLock)); + privateData->dwTxQueueDisableMask=0; + spin_lock_init(&(privateData->TxQueueLock)); + spin_lock_init(&(privateData->TxCounterLock)); + privateData->TxInitialized=true; + +} + +bool Tx_HandleInterrupt( + PPRIVATE_DATA privateData,u32 dwIntSts) +{ + SMSC_ASSERT(privateData!=NULL); + if(dwIntSts&INT_STS_TDFA_) + { + Lan_SetTDFL(privateData,0xFF); + Lan_SetRegDW(INT_STS,INT_STS_TDFA_); + Tx_WakeQueue(privateData,0x02UL); + return true; + } + return false; +} + +void Tx_StopQueue( + PPRIVATE_DATA privateData,u32 dwSource) +{ + unsigned long intFlags=0; + SMSC_ASSERT(privateData!=NULL); + SMSC_ASSERT(privateData->dev!=NULL); + SMSC_ASSERT(privateData->TxInitialized); + spin_lock_irqsave(&(privateData->TxQueueLock),intFlags); + if(privateData->dwTxQueueDisableMask==0) { + netif_stop_queue(privateData->dev); + } + privateData->dwTxQueueDisableMask|=dwSource; + spin_unlock_irqrestore(&(privateData->TxQueueLock),intFlags); +} + +void Tx_WakeQueue( + PPRIVATE_DATA privateData,u32 dwSource) +{ + unsigned long intFlags=0; + SMSC_ASSERT(privateData!=NULL); + SMSC_ASSERT(privateData->dev!=NULL); + SMSC_ASSERT(privateData->TxInitialized); + spin_lock_irqsave(&(privateData->TxQueueLock),intFlags); + privateData->dwTxQueueDisableMask&=(~dwSource); + if(privateData->dwTxQueueDisableMask==0) { + netif_wake_queue(privateData->dev); + } + spin_unlock_irqrestore(&(privateData->TxQueueLock),intFlags); +} + +static u32 Tx_GetTxStatusCount( + PPRIVATE_DATA privateData) +{ + u32 result=0; + SMSC_ASSERT(privateData!=NULL); + SMSC_ASSERT(privateData->dwLanBase!=0); + result=Lan_GetRegDW(TX_FIFO_INF); + if(OLD_REGISTERS(privateData)) { + result&=TX_FIFO_INF_TSFREE_; + result>>=16; + if(result>0x80) { + SMSC_WARNING("TX_FIFO_INF_TSFREE_>0x80"); + result=0x80; + } + result=0x80-result; + } else { + result&=TX_FIFO_INF_TSUSED_; + result>>=16; + } + return result; +} + + + +void Tx_SendSkb( + PPRIVATE_DATA privateData, + struct sk_buff *skb) +{ + u32 dwFreeSpace=0; + unsigned int i=0, TxFrag=0, skbFragCnt = skb_shinfo(skb)->nr_frags + 1; + + //if (skbFragCnt>1) + // printk("skbFrsgCnt = (%d)\n", skbFragCnt); + + // if (privateData->UseTxCsum) { + int Chsum_start_offset=0; + u32 dwTxCsumPreamble=0; + // } + + SMSC_ASSERT(privateData!=NULL); + SMSC_ASSERT(privateData->dwLanBase!=0); + + if(privateData->UseTxCsum){ + + if(skb->ip_summed == CHECKSUM_PARTIAL) + { + //printk("ip summed!\n"); + TxFrag = skbFragCnt + 1; + } + else + { + TxFrag = skbFragCnt; + } + } + else { + TxFrag = skbFragCnt; + } + TxFrag = skbFragCnt; + + + if (privateData->UseTxCsum) { + + if (skb->ip_summed == CHECKSUM_PARTIAL) + { + CalculateTxChecksumOffset( + skb, + &Chsum_start_offset); + + + dwTxCsumPreamble=(((WORD) (Chsum_start_offset + skb->csum)) << 16) | ((WORD) Chsum_start_offset); + + + } + } + + //printk("Tx skb->len = 0x%08x\n", (u32) skb->len); + + + + if(privateData->dwTxDmaCh>=TRANSFER_PIO) + { + //Use PIO only + + //printk("Tx using pio only\n"); + + u32 dwTxCmdA=0; + u32 dwTxCmdB=0; + + + dwFreeSpace=Lan_GetRegDW(TX_FIFO_INF); + dwFreeSpace&=TX_FIFO_INF_TDFREE_; + if(dwFreeSpaceUseTxCsum) { + if(skb->ip_summed == CHECKSUM_PARTIAL) + { + + + dwTxCmdA=TX_CMD_A_INT_FIRST_SEG_ |((u32)sizeof(u32)) ; + + dwTxCmdB= + (((u32)(skb->len+4))<<16) | TX_CMD_B_CSUM_ENABLE | + (((u32)(skb->len+4)&0x7FFUL)); + + + + Lan_SetRegDW(TX_DATA_FIFO,dwTxCmdA); + Lan_SetRegDW(TX_DATA_FIFO,dwTxCmdB); + Lan_SetRegDW(TX_DATA_FIFO,dwTxCsumPreamble); + + + } + } + + if (skbFragCnt == 1){ + + if(skb->ip_summed == CHECKSUM_PARTIAL){ + + dwTxCmdA =((((u32)(skb->data))&0x03UL)<<16) | + TX_CMD_A_INT_LAST_SEG_|((u32)(skb->len)); + dwTxCmdB= + (((u32)(skb->len+4))<<16) | + (((u32)(skb->len+4)&0x7FFUL)); + + + + } + else{ + dwTxCmdA = + ((((u32)(skb->data))&0x03UL)<<16) | TX_CMD_A_INT_FIRST_SEG_ | + TX_CMD_A_INT_LAST_SEG_|((u32)(skb->len)); + + dwTxCmdB= + (((u32)(skb->len))<<16) | + (((u32)(skb->len)&0x7FFUL)); + + } + + //printk("dwTxCmdA = 0x%08x\n", (u32) dwTxCmdA); + //printk("dwTxCmdB = 0x%08x\n", (u32) dwTxCmdB); + + Lan_SetRegDW(TX_DATA_FIFO,dwTxCmdA); + Lan_SetRegDW(TX_DATA_FIFO,dwTxCmdB); + + + // rkdump(skb->data, skb->len); + Platform_WriteFifo( + privateData->dwLanBase, + (u32 *)(((u32)(skb->data))&0xFFFFFFFCUL), + (((u32)(skb->len))+3+ + (((u32)(skb->data))&0x03UL))>>2); + + //printk("Tx skb->len2 = 0x%08x\n", (u32) skb->len); + dwFreeSpace-=(skb->len+32); + dev_kfree_skb(skb); + + } + + else { + + if(skb->ip_summed == CHECKSUM_PARTIAL){ + dwTxCmdA = + ((((u32)(skb->data))&0x03UL)<<16) | //u32 alignment adjustment + ((u32)((skb->len)-(skb->data_len))); + dwTxCmdB= + (((u32)(skb->len+4))<<16) | + (((u32)(skb->len+4)&0x7FFUL)); + + } + else{ + dwTxCmdA = + ((((u32)(skb->data))&0x03UL)<<16) |TX_CMD_A_INT_FIRST_SEG_ | + ((u32)((skb->len)-(skb->data_len))); + dwTxCmdB= + (((u32)(skb->len))<<16) | + (((u32)(skb->len)&0x7FFUL)); + + } + //printk("first frag. \n"); + //rkdump(skb->data, ((skb->len)-(skb->data_len))); + + Lan_SetRegDW(TX_DATA_FIFO,dwTxCmdA); + Lan_SetRegDW(TX_DATA_FIFO,dwTxCmdB); + + + Platform_WriteFifo( + privateData->dwLanBase, + (u32 *)(((u32)(skb->data))&0xFFFFFFFCUL), + (((u32)((skb->len)-(skb->data_len)))+3+ + (((u32)(skb->data))&0x03UL))>>2); + // dwFreeSpace-=((skb->len-skb->data_len)+32); + + + for(i=1;ifrags[i - 1]; + void *frag_addr = page_address(frag->page) + frag->page_offset; + + + dwTxCmdA= + ((((u32)(frag_addr))&0x03UL)<<16) | //u32 alignment adjustment + ((u32)(frag->size)); + + + if (i==(skbFragCnt-1)){ + dwTxCmdA |= TX_CMD_A_INT_LAST_SEG_ ; + } + + if(skb->ip_summed == CHECKSUM_PARTIAL) { + dwTxCmdB= + (((u32)(skb->len+4))<<16) | + (((u32)(skb->len+4)&0x7FFUL)); + } + else { + dwTxCmdB= + (((u32)(skb->len))<<16) | + (((u32)(skb->len)&0x7FFUL)); + } + + Lan_SetRegDW(TX_DATA_FIFO,dwTxCmdA); + Lan_SetRegDW(TX_DATA_FIFO,dwTxCmdB); + //printk("i= %d\n", i); + //rkdump(frag_addr, frag->size); + + Platform_WriteFifo( + privateData->dwLanBase, + (u32 *)(((u32)(frag_addr))&0xFFFFFFFCUL), + (((u32)(frag->size))+3+ + (((u32)(frag_addr))&0x03UL))>>2); + // dwFreeSpace-=(frag->size+8); + + } + + dwFreeSpace-=skb->len+12*TxFrag+16; + dev_kfree_skb(skb); + } + + } + + + else + { + //Use DMA and PIO + + //printk("Tx using dma!!\n"); + + u32 dwDmaCh=privateData->dwTxDmaCh; + PPLATFORM_DATA platformData=&(privateData->PlatformData); + SMSC_ASSERT(TX_FIFO_LOW_THRESHOLD>(skb->len+32)); + + if(((skb->len)>=(privateData->dwTxDmaThreshold)) && (skbFragCnt == 1)) + { + + //printk("Tx using dma!!\n"); + // if(privateData->UseTxCsum) { + u32 dwTxCmdA1=0; + u32 dwTxCmdB1=0; + // } + u32 dwTxCmdA=0; + u32 dwTxCmdB=0; + + + if(privateData->UseTxCsum) { + if(skb->ip_summed == CHECKSUM_PARTIAL) + + { + + + dwTxCmdA1= + TX_CMD_A_INT_FIRST_SEG_ | + ((u32)sizeof(u32));//buffer length + + dwTxCmdB1= + (((u32)(skb->len+4))<<16) |TX_CMD_B_CSUM_ENABLE | + (((u32)(skb->len+4)&0x7FFUL)); + + + } + } + + if (skbFragCnt == 1){ + + dwTxCmdA = +#if (PLATFORM_CACHE_LINE_BYTES == 16) + (0x01UL<<24)|//16 byte end alignment +#endif +#if (PLATFORM_CACHE_LINE_BYTES == 32) + (0x02UL<<24)|//32 byte end alignment +#endif + ((((u32)(skb->data))&(PLATFORM_CACHE_LINE_BYTES-1))<<16) |//16 Byte start alignment + TX_CMD_A_INT_LAST_SEG_ | + ((u32)(skb->len));//buffer length + + if(skb->ip_summed != CHECKSUM_PARTIAL) + dwTxCmdA |= TX_CMD_A_INT_FIRST_SEG_; + + if (skb->ip_summed == CHECKSUM_PARTIAL){ + dwTxCmdB= + (((u32)(skb->len+4))<<16) | + (((u32)(skb->len+4)&0x7FFUL)); + } + else{ + dwTxCmdB= + (((u32)(skb->len))<<16) | + ((u32)(skb->len)); + } + + + + privateData->TxDmaXfer.pdwBuf= + (u32 *)(((u32)(skb->data))& + (~(PLATFORM_CACHE_LINE_BYTES-1))); + privateData->TxDmaXfer.dwDwCnt= + ((((u32)(skb->len))+ + (PLATFORM_CACHE_LINE_BYTES-1)+ + (((u32)(skb->data))& + (PLATFORM_CACHE_LINE_BYTES-1)))& + (~(PLATFORM_CACHE_LINE_BYTES-1)))>>2; + Platform_CachePurge( + platformData, + privateData->TxDmaXfer.pdwBuf, + (privateData->TxDmaXfer.dwDwCnt)<<2); + + spin_lock(&(privateData->TxSkbLock)); + { + if(privateData->TxSkb) + Platform_DmaComplete(platformData,dwDmaCh); + + dwFreeSpace=Lan_GetRegDW(TX_FIFO_INF); + dwFreeSpace&=TX_FIFO_INF_TDFREE_; + if(dwFreeSpaceUseTxCsum) { + if(skb->ip_summed == CHECKSUM_PARTIAL) + + { + + Lan_SetRegDW(TX_DATA_FIFO,dwTxCmdA1); + Lan_SetRegDW(TX_DATA_FIFO,dwTxCmdB1); + Lan_SetRegDW(TX_DATA_FIFO,dwTxCsumPreamble); + } + } + + Lan_SetRegDW(TX_DATA_FIFO,dwTxCmdA); + Lan_SetRegDW(TX_DATA_FIFO,dwTxCmdB); + if(!Platform_DmaStartXfer(platformData,&(privateData->TxDmaXfer))) + { + SMSC_WARNING("Failed Platform_DmaStartXfer"); + } + + dwFreeSpace-=(skb->len+32); + if(privateData->TxSkb) + dev_kfree_skb(privateData->TxSkb); + + privateData->TxSkb=skb; + } + spin_unlock(&(privateData->TxSkbLock)); + + } + + + + } + + else + { + + + //Use PIO + + //printk("skb->len (%d)\n", skb->len); + //printk("Tx using pio\n"); + + u32 dwTxCmdA=0; + u32 dwTxCmdB=0; + + + spin_lock(&(privateData->TxSkbLock)); + if(privateData->TxSkb) { + Platform_DmaComplete(platformData,dwDmaCh); + dev_kfree_skb(privateData->TxSkb); + privateData->TxSkb=NULL; + } + spin_unlock(&(privateData->TxSkbLock)); + + + dwFreeSpace=Lan_GetRegDW(TX_FIFO_INF); + dwFreeSpace&=TX_FIFO_INF_TDFREE_; + if(dwFreeSpaceUseTxCsum) { + + if(skb->ip_summed == CHECKSUM_PARTIAL) + { + + dwTxCmdA=TX_CMD_A_INT_FIRST_SEG_ |((u32)sizeof(u32)) ; + + + dwTxCmdB= + (((u32)(skb->len+4))<<16) |TX_CMD_B_CSUM_ENABLE | + (((u32)(skb->len+4)&0x7FFUL)); + + + //printk("dwTxCmdA = 0x%08x\n", (u32) dwTxCmdA); + //printk("dwTxCmdB = 0x%08x\n", (u32) dwTxCmdB); + //printk("dwTxCsumPreamble = 0x%08x\n", (u32) dwTxCsumPreamble); + + Lan_SetRegDW(TX_DATA_FIFO,dwTxCmdA); + Lan_SetRegDW(TX_DATA_FIFO,dwTxCmdB); + Lan_SetRegDW(TX_DATA_FIFO,dwTxCsumPreamble); + + } + + } + + if (skbFragCnt == 1){ + + if(skb->ip_summed == CHECKSUM_PARTIAL){ + dwTxCmdA = + ((((u32)(skb->data))&0x03UL)<<16) | //u32 alignment adjustment + TX_CMD_A_INT_LAST_SEG_|((u32)(skb->len)); + dwTxCmdB= + (((u32)(skb->len+4))<<16) | + (((u32)(skb->len+4)&0x7FFUL)); + + } + else{ + dwTxCmdA = + ((((u32)(skb->data))&0x03UL)<<16) | TX_CMD_A_INT_FIRST_SEG_ | + TX_CMD_A_INT_LAST_SEG_|((u32)(skb->len)); + dwTxCmdB= + (((u32)(skb->len))<<16) | + ((u32)(skb->len)); + + } + + + Lan_SetRegDW(TX_DATA_FIFO,dwTxCmdA); + Lan_SetRegDW(TX_DATA_FIFO,dwTxCmdB); + + Platform_WriteFifo( + privateData->dwLanBase, + (u32 *)(((u32)(skb->data))&0xFFFFFFFCUL), + (((u32)(skb->len))+3+ + (((u32)(skb->data))&0x03UL))>>2); + dwFreeSpace-=(skb->len+32); + dev_kfree_skb(skb); + } + + else { + + if(skb->ip_summed == CHECKSUM_PARTIAL){ + dwTxCmdA = + ((((u32)(skb->data))&0x03UL)<<16) | //u32 alignment adjustment + ((u32)((skb->len)-(skb->data_len))); + + dwTxCmdB= + (((u32)(skb->len+4))<<16) | + (((u32)(skb->len+4)&0x7FFUL)); + } + else{ + dwTxCmdA = + ((((u32)(skb->data))&0x03UL)<<16) |TX_CMD_A_INT_FIRST_SEG_ | //u32 alignment adjustment + ((u32)((skb->len)-(skb->data_len))); + + dwTxCmdB= + (((u32)(skb->len))<<16) | + (((u32)(skb->len)&0x7FFUL)); + + } + + //printk("first frag. \n"); + //rkdump(skb->data, ((skb->len)-(skb->data_len))); + + Lan_SetRegDW(TX_DATA_FIFO,dwTxCmdA); + Lan_SetRegDW(TX_DATA_FIFO,dwTxCmdB); + + Platform_WriteFifo( + privateData->dwLanBase, + (u32 *)(((u32)(skb->data))&0xFFFFFFFCUL), + (((u32)((skb->len)-(skb->data_len)))+3+ + (((u32)(skb->data))&0x03UL))>>2); + // dwFreeSpace-=((skb->len-skb->data_len)+32); + + + for(i=1;ifrags[i - 1]; + void *frag_addr = page_address(frag->page) + frag->page_offset; + + + dwTxCmdA= + ((((u32)(frag_addr))&0x03UL)<<16) | //u32 alignment adjustment + ((u32)(frag->size)); + + + if (i==(skbFragCnt-1)){ + dwTxCmdA |= TX_CMD_A_INT_LAST_SEG_ ; + } + + if (skb->ip_summed == CHECKSUM_PARTIAL){ + dwTxCmdB= + (((u32)(skb->len+4))<<16) | + (((u32)(skb->len+4)&0x7FFUL)); + } + else{ + dwTxCmdB= + (((u32)(skb->len))<<16) | + ((u32)(skb->len)); + } + + //printk("i= %d\n", i); + //rkdump(frag_addr, frag->size); + + + Lan_SetRegDW(TX_DATA_FIFO,dwTxCmdA); + Lan_SetRegDW(TX_DATA_FIFO,dwTxCmdB); + + Platform_WriteFifo( + privateData->dwLanBase, + (u32 *)(((u32)(frag_addr))&0xFFFFFFFCUL), + (((u32)(frag->size))+3+ + (((u32)(frag_addr))&0x03UL))>>2); + // dwFreeSpace-=(frag->size+8); + + } + + dwFreeSpace-=skb->len+12*TxFrag+16; + dev_kfree_skb(skb); + + } + + } + + } + + //printk("finish.\n"); + + + if(Tx_GetTxStatusCount(privateData)>=30) + { + Tx_UpdateTxCounters(privateData); + } + + if(dwFreeSpacedwLanBase!=0); + SMSC_ASSERT(privateData->TxInitialized==true); + result=Lan_GetRegDW(TX_FIFO_INF); + if(OLD_REGISTERS(privateData)) { + result&=TX_FIFO_INF_TSFREE_; + if(result!=0x00800000UL) { + result=Lan_GetRegDW(TX_STATUS_FIFO); + } else { + result=0; + } + } else { + result&=TX_FIFO_INF_TSUSED_; + if(result!=0x00000000UL) { + result=Lan_GetRegDW(TX_STATUS_FIFO); + } else { + result=0; + } + } + return result; +} + +void Tx_UpdateTxCounters( + PPRIVATE_DATA privateData) +{ + + u32 dwTxStatus=0; + SMSC_ASSERT(privateData!=NULL); + spin_lock(&(privateData->TxCounterLock)); + while((dwTxStatus=Tx_CompleteTx(privateData))!=0) + { + if(dwTxStatus&0x80000000UL) { + SMSC_WARNING("Packet tag reserved bit is high"); + privateData->stats.tx_errors++; + } else if(dwTxStatus&0x00007080UL) { + SMSC_WARNING("Tx Status reserved bits are high"); + privateData->stats.tx_errors++; + } else { + if(dwTxStatus&0x00008000UL) { + privateData->stats.tx_errors++; + } else { + privateData->stats.tx_packets++; + privateData->stats.tx_bytes+=(dwTxStatus>>16); + } + if(dwTxStatus&0x00000100UL) { + privateData->stats.collisions+=16; + privateData->stats.tx_aborted_errors+=1; + } else { + privateData->stats.collisions+= + ((dwTxStatus>>3)&0xFUL); + } + if(dwTxStatus&0x00000800UL) { + privateData->stats.tx_carrier_errors+=1; + } + if(dwTxStatus&0x00000200UL) { + privateData->stats.collisions++; + privateData->stats.tx_aborted_errors++; + } + } + } + spin_unlock(&(privateData->TxCounterLock)); +} + +void Tx_CompleteDma( + PPRIVATE_DATA privateData) +{ + SMSC_ASSERT(privateData!=NULL); + + spin_lock(&(privateData->TxSkbLock)); + if(privateData->TxSkb) { + Platform_DmaComplete( + &(privateData->PlatformData), + privateData->dwTxDmaCh); + dev_kfree_skb(privateData->TxSkb); + privateData->TxSkb=NULL; + } + spin_unlock(&(privateData->TxSkbLock)); +} + + +void CalculateTxChecksumOffset( + struct sk_buff *skb, + int *csum_start_offset + ) +{ + unsigned int skbFragCnt; + + skbFragCnt = skb_shinfo(skb)->nr_frags + 1; + *csum_start_offset = skb->csum_offset; +} + + + + +void rkdump(unsigned char *p, unsigned short len) +{ + int i; + + for(i=0; idwRxDmaCh=dwRxDmaCh; + if(dwRxDmaCh>=TRANSFER_PIO) { + SMSC_TRACE("Rx will use PIO"); + Platform_GetFlowControlParameters( + &(privateData->PlatformData), + &(privateData->RxFlowParameters), + false); + } else { + SMSC_TRACE("Rx will use DMA Channel %d",dwRxDmaCh); + SMSC_ASSERT(Platform_IsValidDmaChannel(dwRxDmaCh)); + if(!Platform_DmaInitialize( + &(privateData->PlatformData), + dwRxDmaCh)) + { + SMSC_WARNING("Failed Platform_DmaInitialize, dwRxDmaCh=%u",dwRxDmaCh); + } + Platform_GetFlowControlParameters( + &(privateData->PlatformData), + &(privateData->RxFlowParameters), + true); + } + if(max_throughput!=0xFFFFFFFFUL) { + privateData->RxFlowParameters.MaxThroughput=max_throughput; + } + if(max_packet_count!=0xFFFFFFFFUL) { + privateData->RxFlowParameters.MaxPacketCount=max_packet_count; + } + if(packet_cost!=0xFFFFFFFFUL) { + privateData->RxFlowParameters.PacketCost=packet_cost; + } + if(burst_period!=0xFFFFFFFFUL) { + privateData->RxFlowParameters.BurstPeriod=burst_period; + } + if(privateData->RxFlowParameters.BurstPeriod==0) { + SMSC_WARNING("burst_period of 0 is not allowed"); + SMSC_WARNING(" resetting burst_period to 100"); + privateData->RxFlowParameters.BurstPeriod=100; + } + if(max_work_load!=0xFFFFFFFFUL) { + privateData->RxFlowMaxWorkLoad=max_work_load; + } else { + privateData->RxFlowMaxWorkLoad= + privateData->RxFlowParameters.MaxThroughput+ + (privateData->RxFlowParameters.MaxPacketCount* + privateData->RxFlowParameters.PacketCost); + } + privateData->RxFlowBurstMaxWorkLoad= + (privateData->RxFlowMaxWorkLoad* + privateData->RxFlowParameters.BurstPeriod)/1000; + if(int_deas!=0xFFFFFFFFUL) { + Lan_SetIntDeas(privateData,int_deas); + } else { + Lan_SetIntDeas(privateData,privateData->RxFlowParameters.IntDeas); + } + + + //Set RX COE + { + unsigned long dwIntFlags=0; + VL_KEY keyCode=Vl_WaitForLock(&(privateData->MacPhyLock),&dwIntFlags); + Mac_SetRegDW(privateData,VLAN1,ETH_P_8021Q,keyCode); + Vl_ReleaseLock(&(privateData->MacPhyLock),keyCode,&dwIntFlags); + // privateData->RxVLanPkt=true; + + } + + + if (privateData->UseRxCsum) { + + { + unsigned long dwIntFlags=0; + VL_KEY keyCode=Vl_WaitForLock(&(privateData->MacPhyLock),&dwIntFlags); + u32 dwCoeCr=Mac_GetRegDW(privateData,COE_CR,keyCode); + dwCoeCr|=(RX_COE_EN | RX_COE_MODE); + Mac_SetRegDW(privateData,COE_CR,dwCoeCr,keyCode); + //printk("COE_CR2 = 0x%08x\n", Mac_GetRegDW(privateData,COE_CR,keyCode)); + Vl_ReleaseLock(&(privateData->MacPhyLock),keyCode,&dwIntFlags); + + } + + + } + + + + //initially the receiver is off + // a following link up detection will turn the receiver on + privateData->dwRxOffCount=1; + Lan_SetRegDW(RX_CFG,RX_CFG_RXDOFF_2_); + Rx_ReceiverOn(privateData, 0); + + privateData->dwRxDmaThreshold=dwDmaThreshold; + Lan_SetRDFL(privateData,0x01); + Lan_SetRSFL(privateData,0x00); + privateData->RxInterrupts=INT_EN_RSFL_EN_; + privateData->RxInterrupts|=INT_EN_RXE_EN_; + if(privateData->dwGeneration==0) { + privateData->RxInterrupts|=INT_EN_RDFL_EN_; + } else { + privateData->RxInterrupts|=INT_EN_RDFO_EN_; + } + privateData->RxInterrupts|=INT_EN_RXDFH_INT_EN_; + Lan_EnableInterrupt(privateData,privateData->RxInterrupts); + +} + +static void Rx_HandleOverrun(PPRIVATE_DATA privateData) +{ + if(privateData->dwGeneration==0) { + if(privateData->RxOverrun==false) { + Rx_ReceiverOff(privateData); + privateData->RxUnloadProgress= + (((((privateData->LastRxStatus1)&0x3FFF0000UL)>>16)+2+3)&0xFFFFFFFCUL); + if(privateData->dwRxDmaChRxUnloadProgress+= + (((((privateData->LastRxStatus2)&0x3FFF0000UL)>>16)+2+3)&0xFFFFFFFCUL); + } + privateData->RxUnloadPacketProgress=0; + privateData->RxOverrun=true; + privateData->RxOverrunCount++; + } + } else { + privateData->RxOverrunCount++; + } +} + +static void Rx_HandOffSkb( + PPRIVATE_DATA privateData, + struct sk_buff *skb) +{ + int result=0; + + skb->dev=privateData->dev; + skb->protocol= eth_type_trans(skb,privateData->dev); + + // #ifdef UseRxCsum + // WORD wHwCsum = 0; + // #endif + + //printk(" Handoff skb->len = 0x%08x\n",(u32) skb->len); + if (privateData->UseRxCsum) { + + WORD wHwCsum = *(WORD *)(skb->tail +4); + skb->csum = wHwCsum; + //printk(" HW csum = 0x%04x\n", skb->csum); + + } + + + if (privateData->UseRxCsum) + + skb->ip_summed = CHECKSUM_PARTIAL; + + else + skb->ip_summed = CHECKSUM_NONE; +#ifdef LINUX_2_6_OR_NEWER + if(rx_mode==PROCESSING_MODE_NAPI) { + result=netif_receive_skb(skb); + privateData->RxWorkLimit--; + privateData->RxPacketsReceived++; + if(privateData->RxWorkLimit<=0) { + privateData->RxCongested=true; + } + + } else { + result=netif_rx(skb);//hand off the Received packet to higher layer + } +#else + result=netif_rx(skb); +#endif + + // result=netif_rx(skb); + + switch(result) + { + case NET_RX_SUCCESS: + break; + case NET_RX_CN_LOW: + case NET_RX_CN_MOD: + case NET_RX_CN_HIGH: + case NET_RX_DROP: + privateData->RxCongested=true; + privateData->RxCongestedCount++; + break; + default: + privateData->RxCongested=true; + privateData->RxCongestedCount++; + SMSC_WARNING("Unknown return value from netif_rx, result=%d",result); + break; + } +} + +void Rx_CompleteMulticastUpdate (PPRIVATE_DATA privateData) +{ + u32 local_MACCR; + VL_KEY keyCode=0; + unsigned long dwIntFlags=0; + + keyCode=Vl_WaitForLock(&(privateData->MacPhyLock),&dwIntFlags); + if (privateData->MulticastUpdatePending) { + SET_GPIO(GP_COMPLETE_MULTICAST_UPDATE); + Mac_SetRegDW(privateData,HASHH,privateData->HashHi,keyCode); + Mac_SetRegDW(privateData,HASHL,privateData->HashLo,keyCode); + local_MACCR = Mac_GetRegDW(privateData,MAC_CR,keyCode); + local_MACCR |= privateData->set_bits_mask; + local_MACCR &= ~(privateData->clear_bits_mask); + Mac_SetRegDW(privateData,MAC_CR,local_MACCR,keyCode); + Rx_ReceiverOn(privateData, keyCode); + privateData->MulticastUpdatePending = false; + CLEAR_GPIO(GP_COMPLETE_MULTICAST_UPDATE); + } + Vl_ReleaseLock(&(privateData->MacPhyLock),keyCode,&dwIntFlags); +} + +void Rx_BeginMulticastUpdate (PPRIVATE_DATA privateData) +{ + u32 startTime, currentTime; + u32 timeout; + unsigned long flags; + + SET_GPIO(GP_BEGIN_MULTICAST_UPDATE); + + //NOTE: we can't rely on privateData->dwLinkSpeed because + // it updates only once per second and may be out dated. + + local_irq_save(flags); + Rx_ReceiverOff(privateData); + if(privateData->dwGeneration>0) { + //since this is concord or later there is no + // overrun processing that might turn off the receiver. + // there for we can rely on RxStop Int. + + //if the speed is 100Mb then lets poll rx stop to get the + // quickest response. + timeout = 200UL; + while ((timeout)&&(!(Lan_GetRegDW(INT_STS)&(INT_STS_RXSTOP_INT_)))) { + // wait 1 uSec + startTime=Lan_GetRegDW(FREE_RUN); + while (1) { + currentTime=Lan_GetRegDW(FREE_RUN); + if (currentTime-startTime >= 25UL) + break; + } + timeout--; + } + if(timeout==0) { + //this is probably a 10Mb link, therefore prepare + // interrupt for update later. + Lan_EnableInterrupt(privateData,INT_EN_RXSTOP_INT_EN_); + + // if this is a 10Mbps half duplex connection + // then Rx stop is only 99.6% reliable + // Therefor we must schedule Gpt callback as + // back up + + // using 18*(100uS) because we already waited 200uS + Gpt_ScheduleCallBack(privateData,GptCB_RxCompleteMulticast, 18UL); + } else { + //Rx is stopped + Lan_SetRegDW(INT_STS,INT_STS_RXSTOP_INT_);//clear interrupt signal + Rx_CompleteMulticastUpdate(privateData); + } + } else { + // for generation 0 we can't rely on Rx stop because + // the receiver may have already been stopped due to + // overflow processing + + // for the same reason we can't just wait 200uS and + // check stopped status there for we must rely on GP timer + // and we must assume a worse case of 10Mb speed + + Gpt_ScheduleCallBack(privateData,GptCB_RxCompleteMulticast, 20UL); + } + local_irq_restore (flags); + CLEAR_GPIO(GP_BEGIN_MULTICAST_UPDATE); +} + +static u32 Rx_PopRxStatus( + PPRIVATE_DATA privateData) +{ + u32 result=Lan_GetRegDW(RX_FIFO_INF); + if((privateData->RxCongested==false)|| + ((privateData->RxCongested==true)&&((result&0x00FF0000UL)==0UL))) + { + if(result&0x00FF0000UL) { + u32 dwIntSts=Lan_GetRegDW(INT_STS); + if(privateData->dwGeneration==0) { + if(dwIntSts&INT_STS_RDFL_) { + Lan_SetRegDW(INT_STS,INT_STS_RDFL_); + Rx_HandleOverrun(privateData); + } + } else { + if(dwIntSts&INT_STS_RDFO_) { + Lan_SetRegDW(INT_STS,INT_STS_RDFO_); + Rx_HandleOverrun(privateData); + } + } + if((privateData->RxFlowControlActive==false)|| + ((privateData->RxFlowControlActive==true)&& + (privateData->RxFlowBurstActive==true))) + { + //Rx status is available, read it + result=Lan_GetRegDW(RX_STATUS_FIFO); + privateData->RxStatusDWReadCount++; + privateData->LastRxStatus3= + privateData->LastRxStatus2; + privateData->LastRxStatus2= + privateData->LastRxStatus1; + privateData->LastRxStatus1=result; + + if(privateData->RxOverrun) { + u32 dwPacketLength=((result&0x3FFF0000UL)>>16); + u32 dwByteCount=((dwPacketLength+2+3)&0xFFFFFFFCUL); + if((privateData->RxUnloadProgress+dwByteCount)>= + ((privateData->RxMaxDataFifoSize)-16)) + { + //This is the packet that crosses the corruption point + // so just ignore it and complete the overrun processing. + result=0; + goto FINISH_OVERRUN_PROCESSING; + } + privateData->RxUnloadProgress+=dwByteCount; + privateData->RxUnloadPacketProgress++; + } + + privateData->RxFlowCurrentThroughput+= + ((((result&0x3FFF0000UL)>>16)-4UL)); + privateData->RxFlowCurrentPacketCount++; + privateData->RxFlowCurrentWorkLoad+= + ((((result&0x3FFF0000UL)>>16)-4UL)+privateData->RxFlowParameters.PacketCost); + if(privateData->RxFlowControlActive) { + privateData->RxFlowBurstWorkLoad+= + ((((result&0x3FFF0000UL)>>16)-4UL)+privateData->RxFlowParameters.PacketCost); + if(privateData->RxFlowBurstWorkLoad>= + privateData->RxFlowBurstMaxWorkLoad) + { + privateData->RxFlowBurstActive=false; + Lan_DisableInterrupt(privateData,privateData->RxInterrupts); + } + } + } else { + result=0; + } + } + else + { + if(privateData->RxOverrun) { + u32 timeOut; + u32 temp; +FINISH_OVERRUN_PROCESSING: + temp=0; + { + timeOut=2000; + while((timeOut>0)&&(!(Lan_GetRegDW(INT_STS)&(INT_STS_RXSTOP_INT_)))) { + udelay(1); + timeOut--; + } + if(timeOut==0) { + // privateData->RxStopTimeOutCount++; + // PULSE_GPIO(GP_TX,1); + SMSC_WARNING("Timed out waiting for Rx to Stop\n"); + } + Lan_SetRegDW(INT_STS,INT_STS_RXSTOP_INT_); + } + + if(privateData->dwRxDmaChRxSkb) { + Platform_DmaComplete( + &(privateData->PlatformData), + privateData->dwRxDmaCh); + + Rx_HandOffSkb(privateData,privateData->RxSkb); + privateData->RxSkb=NULL; + } + } + + temp=Lan_GetRegDW(RX_CFG); + Lan_SetRegDW(RX_CFG,(temp&0x3FFFFFFFUL)); + timeOut=10000000; + Lan_SetBitsDW(RX_CFG,RX_CFG_RX_DUMP_); + while((timeOut>0)&&(Lan_GetRegDW(RX_CFG)&(RX_CFG_RX_DUMP_))) { + udelay(1); + timeOut--; + } + if(timeOut==0) { + SMSC_WARNING("Timed out waiting for Rx Dump to complete\n"); + } + Lan_SetRegDW(RX_CFG,temp); + + privateData->RxDumpCount++; + Lan_SetRegDW(INT_STS,INT_STS_RDFL_); + Rx_ReceiverOn(privateData, 0); + privateData->RxOverrun=false; + } + result=0; + privateData->LastReasonForReleasingCPU=1;//Status FIFO Empty + } + } else { + //disable and reenable the INT_EN + // This will allow the deassertion interval to begin + u32 temp=Lan_GetRegDW(INT_EN); + Lan_SetRegDW(INT_EN,0); + Lan_SetRegDW(INT_EN,temp); + result=0; + privateData->LastReasonForReleasingCPU=2;//High Congestion + } + return result; +} + +void Rx_CountErrors(PPRIVATE_DATA privateData,u32 dwRxStatus) +{ + bool crcError=false; + if(dwRxStatus&0x00008000UL) { + privateData->stats.rx_errors++; + if(dwRxStatus&0x00000002UL) { + privateData->stats.rx_crc_errors++; + crcError=true; + } + } + if(!crcError) { + if((dwRxStatus&0x00001020UL)==0x00001020UL) { + //Frame type indicates length, and length error is set + privateData->stats.rx_length_errors++; + } + if(dwRxStatus&RX_STS_MCAST_) { + privateData->stats.multicast++; + } + } +} + +void Rx_FastForward(PPRIVATE_DATA privateData,u32 dwDwordCount) +{ + privateData->RxFastForwardCount++; + if((dwDwordCount>=4) + && ( + (((privateData->dwIdRev&0x0000FFFFUL)==0x00000000UL) + && (privateData->dwFpgaRev>=0x36)) + || + ((privateData->dwIdRev&0x0000FFFFUL)!=0UL) + ) + ) + { + u32 dwTimeOut=500; + Lan_SetRegDW(RX_DP_CTRL,(dwDwordCount|RX_DP_CTRL_FFWD_BUSY_)); + while((dwTimeOut)&&(Lan_GetRegDW(RX_DP_CTRL)& + RX_DP_CTRL_FFWD_BUSY_)) + { + udelay(1); + dwTimeOut--; + } + if(dwTimeOut==0) { + + SMSC_WARNING("timed out waiting for RX FFWD to finish, RX_DP_CTRL=0x%08X", + Lan_GetRegDW(RX_DP_CTRL)); + } + } else { + while(dwDwordCount) { + u32 dwTemp=Lan_GetRegDW(RX_DATA_FIFO); + dwTemp=dwTemp; + dwDwordCount--; + } + } +} + +//Rx_ReceiverOff, and Rx_ReceiverOn use a reference counter +// because they are used in both the Rx code and the link management count +void Rx_ReceiverOff(PPRIVATE_DATA privateData) +{ + unsigned long dwIntFlags=0; + VL_KEY keyCode=Vl_WaitForLock(&(privateData->MacPhyLock),&dwIntFlags); + if(privateData->dwRxOffCount==0) { + u32 dwMacCr=Mac_GetRegDW(privateData,MAC_CR,keyCode); + if(!(dwMacCr&MAC_CR_RXEN_)) { + SMSC_WARNING("Rx_ReceiverOff: Receiver is already Off"); + } + dwMacCr&=(~MAC_CR_RXEN_); + Mac_SetRegDW(privateData,MAC_CR,dwMacCr,keyCode); + //CLEAR_GPIO(GP_RX); + } + privateData->dwRxOffCount++; + Vl_ReleaseLock(&(privateData->MacPhyLock),keyCode,&dwIntFlags); +} + +//Rx_ReceiverOff, and Rx_ReceiverOn use a reference counter +// because they are used in both the Rx code and the link management count +void Rx_ReceiverOn(PPRIVATE_DATA privateData, VL_KEY callerKeyCode) +{ + unsigned long dwIntFlags=0; + VL_KEY keyCode=0; + + if (callerKeyCode == 0) { + keyCode=Vl_WaitForLock(&(privateData->MacPhyLock),&dwIntFlags); + } + else { + SMSC_ASSERT(Vl_CheckLock(&(privateData->MacPhyLock),callerKeyCode)); + keyCode = callerKeyCode; + } + if(privateData->dwRxOffCount>0) { + privateData->dwRxOffCount--; + if(privateData->dwRxOffCount==0) { + u32 dwMacCr=Mac_GetRegDW(privateData,MAC_CR,keyCode); + if(dwMacCr&MAC_CR_RXEN_) { + SMSC_WARNING("Rx_ReceiverOn: Receiver is already on"); + } + dwMacCr|=MAC_CR_RXEN_; + Mac_SetRegDW(privateData,MAC_CR,dwMacCr,keyCode); + //SET_GPIO(GP_RX); + } + } else { + SMSC_ASSERT(false); + } + if (callerKeyCode == 0) { + Vl_ReleaseLock(&(privateData->MacPhyLock),keyCode,&dwIntFlags); + } +} + +void Rx_ProcessPackets(PPRIVATE_DATA privateData) +{ + u32 dwRxStatus=0; + PPLATFORM_DATA platformData=NULL; + + /* +#ifdef UseRxCsum +WORD wHwCsum = 0; +#endif +*/ + + // SET_GPIO(GP_RX); + + privateData->RxCongested=false; + platformData=&(privateData->PlatformData); + if(privateData->dwRxDmaCh>=TRANSFER_PIO) { + //Use PIO only + + //WARNING: the two LSBs of RXDOFF cannot be changed with the receiver running , + // however we are here re-writing the same value it already had, so it's ok" + Lan_SetRegDW(RX_CFG,RX_CFG_RXDOFF_2_); + while((dwRxStatus=Rx_PopRxStatus(privateData))!=0) + { + u32 dwPacketLength=((dwRxStatus&0x3FFF0000UL)>>16); + + //printk("dwPacketLength = 0x%08x\n", (u32) dwPacketLength); + //printk("dwRxStatus = 0x%08x\n", (u32) dwRxStatus); + + Rx_CountErrors(privateData,dwRxStatus); + + + if((dwRxStatus&RX_STS_ES_)==0) + //||(((dwRxStatus&0x00001080)==0x00001080)&&(privateData->RxVLanPkt==true))) + { + struct sk_buff *skb=NULL; + skb=dev_alloc_skb(dwPacketLength+2); + if(skb!=NULL) { + skb->data=skb->head; + skb->tail=skb->head; + skb_reserve(skb,2); // align IP on 16B boundary + + if (privateData->UseRxCsum) + { + skb_put(skb,dwPacketLength-2UL-4UL); + } + else + { + skb_put(skb,dwPacketLength-4UL); + } + + + //update counters + privateData->stats.rx_packets++; + + + if (privateData->UseRxCsum) + { + privateData->stats.rx_bytes+=(dwPacketLength-4-2); + + } + else + { + privateData->stats.rx_bytes+=(dwPacketLength-4); + } + + + privateData->RxPacketReadCount++; + privateData->RxPioReadCount++; + privateData->RxDataDWReadCount+= + (dwPacketLength+2+3)>>2; + + + + Platform_ReadFifo( + privateData->dwLanBase, + ((u32 *)(skb->head)), + (dwPacketLength+2+3)>>2); + + + //printk("Rx skb->len = 0x%08x\n", (u32) skb->len); + + Rx_HandOffSkb(privateData,skb); + continue; + } else { + SMSC_WARNING("Unable to allocate sk_buff for RX Packet, in PIO path"); + privateData->stats.rx_dropped++; + } + } + //if we get here then the packet is to be read + // out of the fifo and discarded + //printk("fast forward\n"); + dwPacketLength+=(2+3); + dwPacketLength>>=2; + Rx_FastForward(privateData,dwPacketLength); + } + } + else { + + //Use DMA and PIO + u32 dwDmaCh=privateData->dwRxDmaCh; + //struct sk_buff *dmaSkb=NULL;//use privateData->RxDmaSkb + DMA_XFER dmaXfer; + dmaXfer.dwLanReg=privateData->dwLanBase+RX_DATA_FIFO; + dmaXfer.pdwBuf=NULL;// this will be reset per dma request + dmaXfer.dwDmaCh=dwDmaCh; + dmaXfer.dwDwCnt=0;// this will be reset per dma request + dmaXfer.fMemWr=true; + while((dwRxStatus=Rx_PopRxStatus(privateData))!=0) + { + u32 dwPacketLength; +RUN_AGAIN: + Rx_CountErrors(privateData,dwRxStatus); + dwPacketLength=((dwRxStatus&0x3FFF0000UL)>>16); + + + if((dwRxStatus&RX_STS_ES_)==0) + { + struct sk_buff *skb=dev_alloc_skb(dwPacketLength+2*PLATFORM_CACHE_LINE_BYTES); + if(skb!=NULL) + { + skb->data=skb->head; + skb->tail=skb->head; + + //align IP on cache line boundary + privateData->stats.rx_packets++; + privateData->stats.rx_bytes+=(dwPacketLength-4UL); + if(dwPacketLength>=privateData->dwRxDmaThreshold) + { + //use DMA + //printk("Rx using DMA\n"); + u32 dwDwordCount; + skb_reserve(skb,PLATFORM_CACHE_LINE_BYTES-14); + + if (privateData->UseRxCsum) + { + skb_put(skb,dwPacketLength-2UL-4UL); + } + else + { + skb_put(skb,dwPacketLength-4UL); + } + + + + // skb_put(skb,dwPacketLength-4UL); + dwDwordCount=((dwPacketLength+ + (PLATFORM_CACHE_LINE_BYTES-14)+ + PLATFORM_CACHE_LINE_BYTES-1)& + (~(PLATFORM_CACHE_LINE_BYTES-1)))>>2; + Platform_CacheInvalidate( + platformData, + skb->head,dwDwordCount<<2); + dmaXfer.pdwBuf=(u32 *)(skb->head); + dmaXfer.dwDwCnt=dwDwordCount; + privateData->RxDataDWReadCount+=dwDwordCount; + privateData->RxPacketReadCount++; + privateData->RxDmaReadCount++; + if(privateData->RxSkb) + Platform_DmaComplete(platformData,dwDmaCh); + + //set end alignment and offset + switch(PLATFORM_CACHE_LINE_BYTES) + { + //case 4: Lan_SetRegDW(RX_CFG,0x00000200UL);break; + //WARNING: the two LSBs of RXDOFF cannot be changed with the receiver running , + // however we are here re-writing the same value it already had, so it's ok" + case 16:Lan_SetRegDW(RX_CFG, RX_CFG_RX_END_ALGN16_ |RX_CFG_RXDOFF_2_ );break; + case 32:Lan_SetRegDW(RX_CFG, RX_CFG_RX_END_ALGN32_ |RX_CFG_RXDOFF_18_);break; + default:SMSC_ASSERT(false); + } + if(!Platform_DmaStartXfer(platformData,&dmaXfer)) { + SMSC_WARNING("Failed Platform_DmaStartXfer"); + } + + + + + if(privateData->RxSkb) { + + Rx_HandOffSkb(privateData,privateData->RxSkb); + } + privateData->RxSkb=skb; + } + else + { + //use PIO + + // printk("Rx using PIO\n"); + if(privateData->RxSkb) { + Platform_DmaComplete(platformData,dwDmaCh); + Rx_HandOffSkb(privateData,privateData->RxSkb); + } + + privateData->RxSkb=skb; + + skb_reserve(skb,2); + + if (privateData->UseRxCsum) + { + skb_put(skb,dwPacketLength-2UL-4UL); + } + else + { + skb_put(skb,dwPacketLength-4UL); + } + + + + // skb_put(skb,dwPacketLength-4UL); + //set end alignment and offset + //WARNING: the two LSBs of RXDOFF cannot be changed with the receiver running , + // however we are here re-writing the same value it already had, so it's ok" + Lan_SetRegDW(RX_CFG, RX_CFG_RXDOFF_2_);//4 byte end alignment + privateData->RxPacketReadCount++; + privateData->RxPioReadCount++; + privateData->RxDataDWReadCount+= + ((dwPacketLength+2+3)>>2); + Platform_ReadFifo( + privateData->dwLanBase, + ((u32 *)(skb->head)), + (dwPacketLength+2+3)>>2); + + + + } + continue; + } + else + { + SMSC_WARNING("Unable to allocate sk_buff for RX Packet, in DMA path"); + privateData->stats.rx_dropped++; + } + } + //if we get here then the packet is to be read + // out of the fifo and discarded + if(privateData->RxSkb) Platform_DmaComplete(platformData,dwDmaCh); + //delay returning the dmaSkb to OS till later + dwPacketLength+=(2+3); + dwPacketLength>>=2; + //WARNING: the two LSBs of RXDOFF cannot be changed with the receiver running , + // however we are here re-writing the same value it already had, so it's ok" + Lan_SetRegDW(RX_CFG,RX_CFG_RXDOFF_2_);//4 byte end alignment + Rx_FastForward(privateData,dwPacketLength); + } + if(privateData->RxSkb) { + //while waiting for dma to complete, + // check if another packet arrives + u32 dwTimeOut=1000000; + while((Platform_DmaGetDwCnt(platformData,dwDmaCh))&& + (dwTimeOut)) + { + if((dwRxStatus=Rx_PopRxStatus(privateData))!=0) { + goto RUN_AGAIN; + } + udelay(1); + dwTimeOut--; + } + if(dwTimeOut==0) { + SMSC_WARNING("Timed out while waiting for final Dma to complete"); + } + if((dwRxStatus=Rx_PopRxStatus(privateData))!=0) { + goto RUN_AGAIN; + } + + + Rx_HandOffSkb(privateData,privateData->RxSkb); + privateData->RxSkb=NULL; + + //check one last time for another packet. + if((dwRxStatus=Rx_PopRxStatus(privateData))!=0) { + goto RUN_AGAIN; + } + } + } + Lan_SetRegDW(INT_STS,INT_STS_RSFL_); + // CLEAR_GPIO(GP_RX); +} + +void Rx_ProcessPacketsTasklet(unsigned long data) +{ + PPRIVATE_DATA privateData=(PPRIVATE_DATA)Rx_TaskletParameter; + data=data;//make lint happy + if(privateData==NULL) { + SMSC_WARNING("Rx_ProcessPacketsTasklet(privateData==NULL)"); + return; + } + Rx_ProcessPackets(privateData); + Lan_EnableIRQ(privateData); +} + +#ifdef LINUX_2_6_OR_NEWER +/* +int Smsc9118_rx_poll(struct net_device *dev,int * budget) +{ + int result=0; + int limit=0; + + PPRIVATE_DATA privateData=NULL; + SMSC_ASSERT(dev!=NULL); + SMSC_ASSERT(budget!=NULL); + privateData=((PPRIVATE_DATA)(dev->ml_priv)); + SMSC_ASSERT(privateData!=NULL); + + privateData->RxWorkLimit=dev->quota; + if((privateData->RxWorkLimit)>(*budget)) { + privateData->RxWorkLimit=(*budget); + } + + limit=privateData->RxWorkLimit; + + privateData->RxPacketsReceived=0; + // privateData->RxDone=false; + Rx_ProcessPackets(privateData); + + dev->quota-=privateData->RxPacketsReceived; + (*budget)-=privateData->RxPacketsReceived; + + if(privateData->RxPacketsReceived < limit) { + netif_rx_complete(dev); + Lan_EnableIRQ(privateData); + } else { + result=1; + } + + return result; +} +*/ +#endif + + + + + +bool Rx_HandleInterrupt( + PPRIVATE_DATA privateData, + u32 dwIntSts) +{ + bool result=false; + SMSC_ASSERT(privateData!=NULL); + + privateData->LastReasonForReleasingCPU=0; + + if(dwIntSts&INT_STS_RXE_) { + SMSC_TRACE("Rx_HandleInterrupt: RXE signalled"); + privateData->stats.rx_errors++; + Lan_SetRegDW(INT_STS,INT_STS_RXE_); + result=true; + } + + if(dwIntSts&INT_STS_RXDFH_INT_) { + privateData->stats.rx_dropped+=Lan_GetRegDW(RX_DROP); + Lan_SetRegDW(INT_STS,INT_STS_RXDFH_INT_); + result=true; + } + + if(privateData->dwGeneration==0) { + if(dwIntSts&(INT_STS_RDFL_)) { + Lan_SetRegDW(INT_STS,INT_STS_RDFL_); + Rx_HandleOverrun(privateData); + result=true; + } + } else { + if(dwIntSts&(INT_STS_RDFO_)) { + Lan_SetRegDW(INT_STS,INT_STS_RDFO_); + Rx_HandleOverrun(privateData); + result=true; + } + } + + if((!(dwIntSts&INT_STS_RSFL_))&&(privateData->RxOverrun==false)) { + return result; + } + result=true; + + if(privateData->MeasuringRxThroughput==false) { + privateData->MeasuringRxThroughput=true; + Gpt_ScheduleCallBack(privateData,GptCB_MeasureRxThroughput,1000); + privateData->RxFlowCurrentThroughput=0; + privateData->RxFlowCurrentPacketCount=0; + privateData->RxFlowCurrentWorkLoad=0; + } + + +#ifdef LINUX_2_6_OR_NEWER + if(rx_mode==PROCESSING_MODE_TASKLET) { + Lan_DisableIRQ(privateData); + Rx_TaskletParameter=(unsigned long)privateData; + tasklet_schedule(&Rx_Tasklet); + }else if (rx_mode==PROCESSING_MODE_NAPI) { + /* + Lan_DisableIRQ(privateData); + netif_rx_schedule(privateData->dev); + */ + }else { + Rx_ProcessPackets(privateData); + } +#else + if(rx_mode==PROCESSING_MODE_TASKLET) { + Lan_DisableIRQ(privateData); + Rx_TaskletParameter=(unsigned long)privateData; + tasklet_schedule(&Rx_Tasklet); + }else { + Rx_ProcessPackets(privateData); + } +#endif + + return result; +} + +bool RxStop_HandleInterrupt( + PPRIVATE_DATA privateData, + u32 dwIntSts) +{ + bool result=false; + SMSC_ASSERT(privateData!=NULL); + + if(dwIntSts&INT_STS_RXSTOP_INT_) { + result=true; + Gpt_CancelCallBack (privateData, GptCB_RxCompleteMulticast); + Rx_CompleteMulticastUpdate (privateData); + Lan_SetRegDW(INT_STS,INT_STS_RXSTOP_INT_); + Lan_DisableInterrupt(privateData,INT_EN_RXSTOP_INT_EN_); + } + return result; +} + +//returns hash bit number for given MAC address +//example: +// 01 00 5E 00 00 01 -> returns bit number 31 +static u32 Rx_Hash(BYTE addr[6]) +{ + int i; + u32 crc=0xFFFFFFFFUL; + u32 poly=0xEDB88320UL; + u32 result=0; + for(i=0;i<6;i++) + { + int bit; + u32 data=((u32)addr[i]); + for(bit=0;bit<8;bit++) + { + u32 p = (crc^((u32)data))&1UL; + crc >>= 1; + if(p!=0) crc ^= poly; + data >>=1; + } + } + result=((crc&0x01UL)<<5)| + ((crc&0x02UL)<<3)| + ((crc&0x04UL)<<1)| + ((crc&0x08UL)>>1)| + ((crc&0x10UL)>>3)| + ((crc&0x20UL)>>5); + return result; +} + +void Rx_SetMulticastList( + struct net_device *dev) +{ + PPRIVATE_DATA privateData=NULL; + VL_KEY keyCode=0; + unsigned long dwIntFlags=0; + SMSC_ASSERT(dev!=NULL); + + privateData=((PPRIVATE_DATA)(dev->ml_priv)); + SMSC_ASSERT(privateData!=NULL); + keyCode=Vl_WaitForLock(&(privateData->MacPhyLock),&dwIntFlags); + + if(dev->flags & IFF_PROMISC) { + // SMSC_TRACE("Promiscuous Mode Enabled"); + privateData->set_bits_mask = MAC_CR_PRMS_; + privateData->clear_bits_mask = (MAC_CR_MCPAS_ | MAC_CR_HPFILT_); + + privateData->HashHi = 0UL; + privateData->HashLo = 0UL; + goto PREPARE; + } + + if(dev->flags & IFF_ALLMULTI) { + // SMSC_TRACE("Receive all Multicast Enabled"); + privateData->set_bits_mask = MAC_CR_MCPAS_; + privateData->clear_bits_mask = (MAC_CR_PRMS_ | MAC_CR_HPFILT_); + + privateData->HashHi = 0UL; + privateData->HashLo = 0UL; + goto PREPARE; + } + + + if(dev->mc_count>0) { + u32 dwHashH=0; + u32 dwHashL=0; + u32 dwCount=0; + struct dev_mc_list *mc_list=dev->mc_list; + + privateData->set_bits_mask = MAC_CR_HPFILT_; + privateData->clear_bits_mask = (MAC_CR_PRMS_ | MAC_CR_MCPAS_); + + while(mc_list!=NULL) { + dwCount++; + if((mc_list->dmi_addrlen)==6) { + u32 dwMask=0x01UL; + u32 dwBitNum=Rx_Hash(mc_list->dmi_addr); + // SMSC_TRACE("Multicast: enable dwBitNum=%d,addr=%02X %02X %02X %02X %02X %02X", + // dwBitNum, + // ((BYTE *)(mc_list->dmi_addr))[0], + // ((BYTE *)(mc_list->dmi_addr))[1], + // ((BYTE *)(mc_list->dmi_addr))[2], + // ((BYTE *)(mc_list->dmi_addr))[3], + // ((BYTE *)(mc_list->dmi_addr))[4], + // ((BYTE *)(mc_list->dmi_addr))[5]); + dwMask<<=(dwBitNum&0x1FUL); + if(dwBitNum&0x20UL) { + dwHashH|=dwMask; + } else { + dwHashL|=dwMask; + } + } else { + SMSC_WARNING("dmi_addrlen!=6"); + } + mc_list=mc_list->next; + } + if(dwCount!=((u32)(dev->mc_count))) { + SMSC_WARNING("dwCount!=dev->mc_count"); + } + // SMSC_TRACE("Multicast: HASHH=0x%08X,HASHL=0x%08X",dwHashH,dwHashL); + privateData->HashHi = dwHashH; + privateData->HashLo = dwHashL; + } + else + { + privateData->set_bits_mask = 0L; + privateData->clear_bits_mask = (MAC_CR_PRMS_ | MAC_CR_MCPAS_ | MAC_CR_HPFILT_); + + // SMSC_TRACE("Receive own packets only."); + privateData->HashHi = 0UL; + privateData->HashLo = 0UL; + } + +PREPARE: + if(privateData->dwGeneration<=1) { + if (privateData->MulticastUpdatePending == false) { + privateData->MulticastUpdatePending = true; + // prepare to signal software interrupt + Lan_SignalSoftwareInterrupt(privateData); + } + else { + // Rx_CompleteMulticastUpdate has not yet been called + // therefore these latest settings will be used instead + } + } else { + u32 local_MACCR; + Mac_SetRegDW(privateData,HASHH,privateData->HashHi,keyCode); + Mac_SetRegDW(privateData,HASHL,privateData->HashLo,keyCode); + local_MACCR = Mac_GetRegDW(privateData,MAC_CR,keyCode); + local_MACCR |= privateData->set_bits_mask; + local_MACCR &= ~(privateData->clear_bits_mask); + Mac_SetRegDW(privateData,MAC_CR,local_MACCR,keyCode); + } + Vl_ReleaseLock(&(privateData->MacPhyLock),keyCode,&dwIntFlags); + return; +} + +void Eeprom_EnableAccess(PPRIVATE_DATA privateData) +{ + SMSC_ASSERT(privateData!=NULL); + if(debug_mode&0x04UL) { + Lan_SetRegDW(GPIO_CFG,(g_GpioSetting&0xFF0FFFFFUL)); + } else { + Lan_ClrBitsDW(GPIO_CFG,0x00F00000UL); + } + udelay(100); +} + +void Eeprom_DisableAccess(PPRIVATE_DATA privateData) +{ + SMSC_ASSERT(privateData!=NULL); + if(debug_mode&0x04UL) { + Lan_SetRegDW(GPIO_CFG,g_GpioSetting); + } +} + +bool Eeprom_IsMacAddressLoaded(PPRIVATE_DATA privateData) +{ + SMSC_ASSERT(privateData!=NULL); + return (Lan_GetRegDW(E2P_CMD)& + E2P_CMD_MAC_ADDR_LOADED_)?true:false; +} + +bool Eeprom_IsBusy(PPRIVATE_DATA privateData) +{ + SMSC_ASSERT(privateData!=NULL); + return (Lan_GetRegDW(E2P_CMD)& + E2P_CMD_EPC_BUSY_)?true:false; +} + +bool Eeprom_Timeout(PPRIVATE_DATA privateData) +{ + SMSC_ASSERT(privateData!=NULL); + return (Lan_GetRegDW(E2P_CMD)& + E2P_CMD_EPC_TIMEOUT_)?true:false; +} + +bool Eeprom_ReadLocation( + PPRIVATE_DATA privateData, + BYTE address, BYTE * data) +{ + u32 timeout=100000; + u32 temp=0; + SMSC_ASSERT(privateData!=NULL); + SMSC_ASSERT(data!=NULL); + if((temp=Lan_GetRegDW(E2P_CMD))&E2P_CMD_EPC_BUSY_) { + SMSC_WARNING("Eeprom_ReadLocation: Busy at start, E2P_CMD=0x%08X",temp); + return false; + } + Lan_SetRegDW(E2P_CMD, + (E2P_CMD_EPC_BUSY_|E2P_CMD_EPC_CMD_READ_|((u32)address))); + while((timeout>0)&& + (Lan_GetRegDW(E2P_CMD)&E2P_CMD_EPC_BUSY_)) + { + udelay(10); + timeout--; + } + if(timeout==0) { + return false; + } + (*data)=(BYTE)(Lan_GetRegDW(E2P_DATA)); + return true; +} + +bool Eeprom_EnableEraseAndWrite( + PPRIVATE_DATA privateData) +{ + u32 timeout=100000; + SMSC_ASSERT(privateData!=NULL); + if(Lan_GetRegDW(E2P_CMD)&E2P_CMD_EPC_BUSY_) { + SMSC_WARNING("Eeprom_EnableEraseAndWrite: Busy at start"); + return false; + } + Lan_SetRegDW(E2P_CMD, + (E2P_CMD_EPC_BUSY_|E2P_CMD_EPC_CMD_EWEN_)); + + while((timeout>0)&& + (Lan_GetRegDW(E2P_CMD)&E2P_CMD_EPC_BUSY_)) + { + udelay(10); + timeout--; + } + if(timeout==0) { + return false; + } + return true; +} + +bool Eeprom_DisableEraseAndWrite( + PPRIVATE_DATA privateData) +{ + u32 timeout=100000; + SMSC_ASSERT(privateData!=NULL); + if(Lan_GetRegDW(E2P_CMD)&E2P_CMD_EPC_BUSY_) { + SMSC_WARNING("Eeprom_DisableEraseAndWrite: Busy at start"); + return false; + } + Lan_SetRegDW(E2P_CMD, + (E2P_CMD_EPC_BUSY_|E2P_CMD_EPC_CMD_EWDS_)); + + while((timeout>0)&& + (Lan_GetRegDW(E2P_CMD)&E2P_CMD_EPC_BUSY_)) + { + udelay(10); + timeout--; + } + if(timeout==0) { + return false; + } + return true; +} + +bool Eeprom_WriteLocation( + PPRIVATE_DATA privateData,BYTE address,BYTE data) +{ + u32 timeout=100000; + SMSC_ASSERT(privateData!=NULL); + if(Lan_GetRegDW(E2P_CMD)&E2P_CMD_EPC_BUSY_) { + SMSC_WARNING("Eeprom_WriteLocation: Busy at start"); + return false; + } + Lan_SetRegDW(E2P_DATA,((u32)data)); + Lan_SetRegDW(E2P_CMD, + (E2P_CMD_EPC_BUSY_|E2P_CMD_EPC_CMD_WRITE_|((u32)address))); + + while((timeout>0)&& + (Lan_GetRegDW(E2P_CMD)&E2P_CMD_EPC_BUSY_)) + { + udelay(10); + timeout--; + } + if(timeout==0) { + return false; + } + return true; +} + +bool Eeprom_EraseAll( + PPRIVATE_DATA privateData) +{ + u32 timeout=100000; + SMSC_ASSERT(privateData!=NULL); + if(Lan_GetRegDW(E2P_CMD)&E2P_CMD_EPC_BUSY_) { + SMSC_WARNING("Eeprom_EraseAll: Busy at start"); + return false; + } + Lan_SetRegDW(E2P_CMD, + (E2P_CMD_EPC_BUSY_|E2P_CMD_EPC_CMD_ERAL_)); + + while((timeout>0)&& + (Lan_GetRegDW(E2P_CMD)&E2P_CMD_EPC_BUSY_)) + { + udelay(10); + timeout--; + } + if(timeout==0) { + return false; + } + return true; +} + +bool Eeprom_Reload( + PPRIVATE_DATA privateData) +{ + u32 timeout=100000; + SMSC_ASSERT(privateData!=NULL); + if(Lan_GetRegDW(E2P_CMD)&E2P_CMD_EPC_BUSY_) { + SMSC_WARNING("Eeprom_Reload: Busy at start"); + return false; + } + Lan_SetRegDW(E2P_CMD, + (E2P_CMD_EPC_BUSY_|E2P_CMD_EPC_CMD_RELOAD_)); + + while((timeout>0)&& + (Lan_GetRegDW(E2P_CMD)&E2P_CMD_EPC_BUSY_)) + { + udelay(10); + timeout--; + } + if(timeout==0) { + return false; + } + return true; +} + +bool Eeprom_SaveMacAddress( + PPRIVATE_DATA privateData, + u32 dwHi16,u32 dwLo32) +{ + bool result=false; + SMSC_ASSERT(privateData!=NULL); + Eeprom_EnableAccess(privateData); + if(!Eeprom_EnableEraseAndWrite(privateData)) goto DONE; + if(!Eeprom_EraseAll(privateData)) goto DONE; + if(privateData->dwGeneration==0) { + if(!Eeprom_EnableEraseAndWrite(privateData)) goto DONE; + if(!Eeprom_WriteLocation(privateData,0,0xA5)) goto DONE; + if(!Eeprom_EnableEraseAndWrite(privateData)) goto DONE; + if(!Eeprom_WriteLocation(privateData,1,LOBYTE(LOWORD(dwLo32)))) goto DONE; + if(!Eeprom_EnableEraseAndWrite(privateData)) goto DONE; + if(!Eeprom_WriteLocation(privateData,2,HIBYTE(LOWORD(dwLo32)))) goto DONE; + if(!Eeprom_EnableEraseAndWrite(privateData)) goto DONE; + if(!Eeprom_WriteLocation(privateData,3,LOBYTE(HIWORD(dwLo32)))) goto DONE; + if(!Eeprom_EnableEraseAndWrite(privateData)) goto DONE; + if(!Eeprom_WriteLocation(privateData,4,HIBYTE(HIWORD(dwLo32)))) goto DONE; + if(!Eeprom_EnableEraseAndWrite(privateData)) goto DONE; + if(!Eeprom_WriteLocation(privateData,5,LOBYTE(LOWORD(dwHi16)))) goto DONE; + if(!Eeprom_EnableEraseAndWrite(privateData)) goto DONE; + if(!Eeprom_WriteLocation(privateData,6,HIBYTE(LOWORD(dwHi16)))) goto DONE; + } else { + if(!Eeprom_WriteLocation(privateData,0,0xA5)) goto DONE; + if(!Eeprom_WriteLocation(privateData,1,LOBYTE(LOWORD(dwLo32)))) goto DONE; + if(!Eeprom_WriteLocation(privateData,2,HIBYTE(LOWORD(dwLo32)))) goto DONE; + if(!Eeprom_WriteLocation(privateData,3,LOBYTE(HIWORD(dwLo32)))) goto DONE; + if(!Eeprom_WriteLocation(privateData,4,HIBYTE(HIWORD(dwLo32)))) goto DONE; + if(!Eeprom_WriteLocation(privateData,5,LOBYTE(LOWORD(dwHi16)))) goto DONE; + if(!Eeprom_WriteLocation(privateData,6,HIBYTE(LOWORD(dwHi16)))) goto DONE; + } + if(!Eeprom_DisableEraseAndWrite(privateData)) goto DONE; + + if(!Eeprom_Reload(privateData)) goto DONE; + if(!Eeprom_IsMacAddressLoaded(privateData)) goto DONE; + { + unsigned long dwIntFlags=0; + VL_KEY keyCode=Vl_WaitForLock(&(privateData->MacPhyLock),&dwIntFlags); + if(dwHi16!=Mac_GetRegDW(privateData,ADDRH,keyCode)) goto DONE; + if(dwLo32!=Mac_GetRegDW(privateData,ADDRL,keyCode)) goto DONE; + Vl_ReleaseLock(&(privateData->MacPhyLock),keyCode,&dwIntFlags); + } + result=true; +DONE: + Eeprom_DisableAccess(privateData); + return result; +} + +volatile u32 g_GpioSetting=0x00000000UL; +#ifdef USE_LED1_WORK_AROUND +volatile u32 g_GpioSettingOriginal=0x00000000UL; +#endif + +bool Lan_Initialize( + PPRIVATE_DATA privateData, + u32 dwIntCfg, + u32 dwTxFifSz, + u32 dwAfcCfg) +{ + bool result=false; + u32 dwTimeOut=0; + u32 dwTemp=0; + u32 dwResetCount=3; + + SMSC_TRACE("-->Lan_Initialize(dwIntCfg=0x%08X)",dwIntCfg); + SMSC_ASSERT(privateData!=NULL); + + //Reset the LAN9118 + if(privateData->dwGeneration>0) { + dwResetCount=1; + } + while(dwResetCount>0) { + Lan_SetRegDW(HW_CFG,HW_CFG_SRST_); + dwTimeOut=1000000; + do { + udelay(10); + dwTemp=Lan_GetRegDW(HW_CFG); + dwTimeOut--; + } while((dwTimeOut>0)&&(dwTemp&HW_CFG_SRST_)); + if(dwTemp&HW_CFG_SRST_) { + SMSC_WARNING(" Failed to complete reset."); + goto DONE; + } + dwResetCount--; + } + + SMSC_ASSERT(dwTxFifSz>=0x00020000UL); + SMSC_ASSERT(dwTxFifSz<=0x000E0000UL); + SMSC_ASSERT((dwTxFifSz&(~HW_CFG_TX_FIF_SZ_))==0); + Lan_SetRegDW(HW_CFG,dwTxFifSz); + privateData->RxMaxDataFifoSize=0; + switch(dwTxFifSz>>16) { + case 2:privateData->RxMaxDataFifoSize=13440;break; + case 3:privateData->RxMaxDataFifoSize=12480;break; + case 4:privateData->RxMaxDataFifoSize=11520;break; + case 5:privateData->RxMaxDataFifoSize=10560;break; + case 6:privateData->RxMaxDataFifoSize=9600;break; + case 7:privateData->RxMaxDataFifoSize=8640;break; + case 8:privateData->RxMaxDataFifoSize=7680;break; + case 9:privateData->RxMaxDataFifoSize=6720;break; + case 10:privateData->RxMaxDataFifoSize=5760;break; + case 11:privateData->RxMaxDataFifoSize=4800;break; + case 12:privateData->RxMaxDataFifoSize=3840;break; + case 13:privateData->RxMaxDataFifoSize=2880;break; + case 14:privateData->RxMaxDataFifoSize=1920;break; + default:SMSC_ASSERT(false);break; + } + + if(dwAfcCfg==0xFFFFFFFF) { + switch(dwTxFifSz) { + + //AFC_HI is about ((Rx Data Fifo Size)*2/3)/64 + //AFC_LO is AFC_HI/2 + //BACK_DUR is about 5uS*(AFC_LO) rounded down + case 0x00020000UL://13440 Rx Data Fifo Size + dwAfcCfg=0x008C46AF;break; + case 0x00030000UL://12480 Rx Data Fifo Size + dwAfcCfg=0x0082419F;break; + case 0x00040000UL://11520 Rx Data Fifo Size + + dwAfcCfg=0x00783C9F;break; + case 0x00050000UL://10560 Rx Data Fifo Size + // dwAfcCfg=0x006E378F;break; + dwAfcCfg=0x006E374F;break; + case 0x00060000UL:// 9600 Rx Data Fifo Size + dwAfcCfg=0x0064328F;break; + case 0x00070000UL:// 8640 Rx Data Fifo Size + dwAfcCfg=0x005A2D7F;break; + case 0x00080000UL:// 7680 Rx Data Fifo Size + dwAfcCfg=0x0050287F;break; + case 0x00090000UL:// 6720 Rx Data Fifo Size + dwAfcCfg=0x0046236F;break; + case 0x000A0000UL:// 5760 Rx Data Fifo Size + dwAfcCfg=0x003C1E6F;break; + case 0x000B0000UL:// 4800 Rx Data Fifo Size + dwAfcCfg=0x0032195F;break; + + //AFC_HI is ~1520 bytes less than RX Data Fifo Size + //AFC_LO is AFC_HI/2 + //BACK_DUR is about 5uS*(AFC_LO) rounded down + case 0x000C0000UL:// 3840 Rx Data Fifo Size + dwAfcCfg=0x0024124F;break; + case 0x000D0000UL:// 2880 Rx Data Fifo Size + dwAfcCfg=0x0015073F;break; + case 0x000E0000UL:// 1920 Rx Data Fifo Size + dwAfcCfg=0x0006032F;break; + default:SMSC_ASSERT(false);break; + } + } + Lan_SetRegDW(AFC_CFG,(dwAfcCfg&0xFFFFFFF0UL)); + + //make sure EEPROM has finished loading before setting GPIO_CFG + dwTimeOut=1000; + while((dwTimeOut>0)&&(Lan_GetRegDW(E2P_CMD)&E2P_CMD_EPC_BUSY_)) { + udelay(5); + dwTimeOut--; + } + if(dwTimeOut==0) { + SMSC_WARNING("Lan_Initialize: Timed out waiting for EEPROM busy bit to clear\n"); + } + + if(debug_mode&0x04UL) { + if(OLD_REGISTERS(privateData)) + { + g_GpioSetting=0x00270700UL; + } else { + g_GpioSetting=0x00670700UL; + } + } else { + g_GpioSetting = 0x70070000UL; + } + Lan_SetRegDW(GPIO_CFG,g_GpioSetting); + + //initialize interrupts + Lan_SetRegDW(INT_EN,0); + Lan_SetRegDW(INT_STS,0xFFFFFFFFUL); + dwIntCfg|=INT_CFG_IRQ_EN_; + Lan_SetRegDW(INT_CFG,dwIntCfg); + + Vl_InitLock(&(privateData->MacPhyLock)); + spin_lock_init(&(privateData->IntEnableLock)); + privateData->LanInitialized=true; + + result=true; + +DONE: + SMSC_TRACE("<--Lan_Initialize"); + return result; +} + +void Lan_EnableInterrupt(PPRIVATE_DATA privateData,u32 dwIntEnMask) +{ + unsigned long dwIntFlags=0; + SMSC_ASSERT(privateData!=NULL); + SMSC_ASSERT(privateData->LanInitialized==true); + spin_lock_irqsave(&(privateData->IntEnableLock),dwIntFlags); + Lan_SetBitsDW(INT_EN,dwIntEnMask); + spin_unlock_irqrestore(&(privateData->IntEnableLock),dwIntFlags); +} + +void Lan_DisableInterrupt(PPRIVATE_DATA privateData,u32 dwIntEnMask) +{ + unsigned long dwIntFlags=0; + SMSC_ASSERT(privateData!=NULL); + SMSC_ASSERT(privateData->LanInitialized==true); + spin_lock_irqsave(&(privateData->IntEnableLock),dwIntFlags); + Lan_ClrBitsDW(INT_EN,dwIntEnMask); + spin_unlock_irqrestore(&(privateData->IntEnableLock),dwIntFlags); +} + +//Spin locks for the following functions have been commented out +// because at this time they are not necessary. +//These function are +// Lan_SetTDFL +// Lan_SetTSFL +// Lan_SetRDFL +// Lan_SetRSFL +//Both the Rx and Tx side of the driver use the FIFO_INT, +// but the Rx side only touches is during initialization, +// so it is sufficient that Tx side simple preserve the Rx setting + +void Lan_SetTDFL(PPRIVATE_DATA privateData,BYTE level) { + // unsigned long dwIntFlags=0; + SMSC_ASSERT(privateData!=NULL); + SMSC_ASSERT(privateData->LanInitialized==true); + // spin_lock_irqsave(&(privateData->IntEnableLock),dwIntFlags); + { + u32 temp=Lan_GetRegDW(FIFO_INT); + temp&=0x00FFFFFFUL; + temp|=((u32)level)<<24; + Lan_SetRegDW(FIFO_INT,temp); + } + // spin_unlock_irqrestore(&(privateData->IntEnableLock),dwIntFlags); +} + +void Lan_SetTSFL(PPRIVATE_DATA privateData,BYTE level) { + // unsigned long dwIntFlags=0; + SMSC_ASSERT(privateData!=NULL); + SMSC_ASSERT(privateData->LanInitialized==true); + // spin_lock_irqsave(&(privateData->IntEnableLock),dwIntFlags); + { + u32 temp=Lan_GetRegDW(FIFO_INT); + temp&=0xFF00FFFFUL; + temp|=((u32)level)<<16; + Lan_SetRegDW(FIFO_INT,temp); + } + // spin_unlock_irqrestore(&(privateData->IntEnableLock),dwIntFlags); +} + +void Lan_SetRDFL(PPRIVATE_DATA privateData,BYTE level) { + // unsigned long dwIntFlags=0; + SMSC_ASSERT(privateData!=NULL); + SMSC_ASSERT(privateData->LanInitialized==true); + // spin_lock_irqsave(&(privateData->IntEnableLock),dwIntFlags); + { + u32 temp=Lan_GetRegDW(FIFO_INT); + temp&=0xFFFF00FFUL; + temp|=((u32)level)<<8; + Lan_SetRegDW(FIFO_INT,temp); + } + // spin_unlock_irqrestore(&(privateData->IntEnableLock),dwIntFlags); +} + +void Lan_SetRSFL(PPRIVATE_DATA privateData,BYTE level) { + // unsigned long dwIntFlags=0; + SMSC_ASSERT(privateData!=NULL); + SMSC_ASSERT(privateData->LanInitialized==true); + // spin_lock_irqsave(&(privateData->IntEnableLock),dwIntFlags); + { + u32 temp=Lan_GetRegDW(FIFO_INT); + temp&=0xFFFFFF00UL; + temp|=((u32)level); + Lan_SetRegDW(FIFO_INT,temp); + } + // spin_unlock_irqrestore(&(privateData->IntEnableLock),dwIntFlags); +} + +void Lan_EnableIRQ(PPRIVATE_DATA privateData) +{ + unsigned long dwIntFlags=0; + spin_lock_irqsave(&(privateData->IntEnableLock),dwIntFlags); + { + Lan_SetBitsDW(INT_CFG,INT_CFG_IRQ_EN_); + } + spin_unlock_irqrestore(&(privateData->IntEnableLock),dwIntFlags); +} + +void Lan_DisableIRQ(PPRIVATE_DATA privateData) +{ + unsigned long dwIntFlags=0; + spin_lock_irqsave(&(privateData->IntEnableLock),dwIntFlags); + { + Lan_ClrBitsDW(INT_CFG,INT_CFG_IRQ_EN_); + } + spin_unlock_irqrestore(&(privateData->IntEnableLock),dwIntFlags); +} + +void Lan_SetIntDeas(PPRIVATE_DATA privateData, u32 dwIntDeas) +{ + unsigned long dwIntFlags=0; + spin_lock_irqsave(&(privateData->IntEnableLock),dwIntFlags); + { + Lan_ClrBitsDW(INT_CFG,INT_CFG_INT_DEAS_); + Lan_SetBitsDW(INT_CFG,(dwIntDeas<<24)); + } + spin_unlock_irqrestore(&(privateData->IntEnableLock),dwIntFlags); +} + +void Lan_SignalSoftwareInterrupt(PPRIVATE_DATA privateData) +{ + SMSC_ASSERT(privateData!=NULL); + SMSC_ASSERT(privateData->dwLanBase!=0); + privateData->SoftwareInterruptSignal=false; + Lan_EnableInterrupt(privateData,INT_EN_SW_INT_EN_); +} + +bool Lan_HandleSoftwareInterrupt( + PPRIVATE_DATA privateData, + u32 dwIntSts) +{ + if(dwIntSts&INT_STS_SW_INT_) { + SMSC_TRACE("Got SW Interrupt (privateData=%08X)", (u32)privateData); + SMSC_ASSERT(privateData!=NULL); + Lan_DisableInterrupt(privateData,INT_EN_SW_INT_EN_); + Lan_SetRegDW(INT_STS,INT_STS_SW_INT_); + privateData->SoftwareInterruptSignal=true; + if (privateData->MulticastUpdatePending) { + Rx_BeginMulticastUpdate (privateData); + } + return true; + } + return false; +} + +typedef struct _SHOW_REG +{ + char szName[20]; + u32 dwOffset; +} SHOW_REG; +/* +FUNCTION: Lan_ShowRegs +This function is used to display the registers. +Except the phy. +*/ +void Lan_ShowRegs(PPRIVATE_DATA privateData) +{ + // Make these const struct's static to keep them off the stack. + // Otherwise, gcc will try to use _memcpy() to initialize them, + // which will *NOT* work in our RunTime environment. + static const SHOW_REG sysCsr[] = { + { "ID_REV", 0x50UL }, + { "INT_CFG", 0x54UL }, + { "INT_STS", 0x58UL }, + { "INT_EN", 0x5CUL }, + { "DMA_CFG", 0x60UL }, + { "BYTE_TEST", 0x64UL }, + { "FIFO_INT", 0x68UL }, + { "RX_CFG", 0x6CUL }, + { "TX_CFG", 0x70UL }, + { "HW_CFG", 0x74UL }, + { "RX_DP_CTRL", 0x78UL }, + { "RX_FIFO_INF", 0x7CUL }, + { "TX_FIFO_INF", 0x80UL }, + { "PMT_CTRL", 0x84UL }, + { "GPIO_CFG", 0x88UL }, + { "GPT_CFG", 0x8CUL }, + { "GPT_CNT", 0x90UL }, + { "FPGA_REV", 0x94UL }, + { "WORD_SWAP", 0x98UL }, + { "FREE_RUN", 0x9CUL }, + { "RX_DROP", 0xA0UL }, + { "MAC_CSR_CMD", 0xA4UL }, + { "MAC_CSR_DATA", 0xA8UL }, + { "AFC_CFG", 0xACUL }, + { "E2P_CMD", 0xB0UL }, + { "E2P_DATA", 0xB4UL }, + { "TEST_REG_A", 0xC0UL }}; + + static const SHOW_REG macCsr[] = { + { "MAC_CR", MAC_CR }, + { "ADDRH", ADDRH }, + { "ADDRL", ADDRL }, + { "HASHH", HASHH }, + { "HASHL", HASHL }, + { "MII_ACC", MII_ACC }, + { "MII_DATA", MII_DATA }, + { "FLOW", FLOW }, + { "VLAN1", VLAN1 }, + { "VLAN2", VLAN2 }, + { "WUFF", WUFF }, + { "WUCSR", WUCSR }}; + + int i, iNumSysRegs, iNumMacRegs; + u32 dwOldMacCmdReg, dwOldMacDataReg; + + iNumSysRegs = (int)(sizeof(sysCsr) / sizeof(SHOW_REG)); + iNumMacRegs = (int)(sizeof(macCsr) / sizeof(SHOW_REG)); + + // preserve MAC cmd/data reg's + dwOldMacCmdReg = Lan_GetRegDW(MAC_CSR_CMD); + dwOldMacDataReg = Lan_GetRegDW(MAC_CSR_DATA); + + SMSC_TRACE(""); + SMSC_TRACE(" LAN91C118 CSR's"); + SMSC_TRACE(" SYS CSR's MAC CSR's"); + + { + unsigned long dwIntFlags=0; + VL_KEY keyCode=Vl_WaitForLock(&(privateData->MacPhyLock),&dwIntFlags); + for (i=0; idwLanBase+sysCsr[i].dwOffset)), + macCsr[i].szName, + macCsr[i].dwOffset, + Mac_GetRegDW(privateData,macCsr[i].dwOffset,keyCode)); + + // restore original mac cmd/data reg's after each usage + Lan_SetRegDW(MAC_CSR_CMD,dwOldMacCmdReg); + Lan_SetRegDW(MAC_CSR_DATA,dwOldMacDataReg); + } + Vl_ReleaseLock(&(privateData->MacPhyLock),keyCode,&dwIntFlags); + } + for (i=iNumMacRegs; idwLanBase+sysCsr[i].dwOffset))); + } +} + +void Vl_InitLock(PVERIFIABLE_LOCK pVl) +{ + SMSC_ASSERT(pVl!=NULL); + spin_lock_init(&(pVl->Lock)); + pVl->KeyCode=0; +} + +bool Vl_CheckLock(PVERIFIABLE_LOCK pVl,VL_KEY keyCode) +{ + bool result=false; + SMSC_ASSERT(pVl!=NULL); + if(keyCode==pVl->KeyCode) + result=true; + return result; +} + +VL_KEY Vl_WaitForLock(PVERIFIABLE_LOCK pVl,unsigned long *pdwIntFlags) +{ + VL_KEY result=0; + SMSC_ASSERT(pVl!=NULL); + spin_lock_irqsave( + &(pVl->Lock), + (*pdwIntFlags)); + pVl->KeyCode++; + if(pVl->KeyCode>0x80000000UL) { + pVl->KeyCode=1; + } + result=pVl->KeyCode; + return result; +} + +void Vl_ReleaseLock(PVERIFIABLE_LOCK pVl,VL_KEY keyCode,unsigned long *pdwIntFlags) +{ + SMSC_ASSERT(pVl!=NULL); + SMSC_ASSERT(pVl->KeyCode==keyCode); + spin_unlock_irqrestore(&(pVl->Lock),(*pdwIntFlags)); +} + +#ifndef USING_LINT +module_init(Smsc9118_init_module); +module_exit(Smsc9118_cleanup_module); +#endif -- 1.5.4.3 From nils.faerber@kernelconcepts.de Fri Mar 6 16:36:29 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 06 Mar 2009 16:36:32 +0000 (GMT) Received: from mail.kernelconcepts.de ([212.60.202.196]:30121 "EHLO mail.kernelconcepts.de") by ftp.linux-mips.org with ESMTP id S21366485AbZCFQg3 (ORCPT ); Fri, 6 Mar 2009 16:36:29 +0000 Received: from [192.168.2.28] by mail.kernelconcepts.de with esmtpsa (TLS-1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.63) (envelope-from ) id 1LfdHU-0008H3-Rg for linux-mips@linux-mips.org; Fri, 06 Mar 2009 17:52:16 +0100 Message-ID: <49B1510B.8020606@kernelconcepts.de> Date: Fri, 06 Mar 2009 17:36:27 +0100 From: Nils Faerber Organization: kernel concepts GbR User-Agent: Thunderbird 2.0.0.19 (X11/20090105) MIME-Version: 1.0 To: linux-mips@linux-mips.org Subject: Ingenic JZ4730 - illegal instruction X-Enigmail-Version: 0.95.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22027 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: nils.faerber@kernelconcepts.de Precedence: bulk X-list: linux-mips Hello! I am rather playing than really working on a Ingenic JZ4730 based device. The JZ4730 is a MIPS32 SOC included in many types of devices, like media players and thelike but also in small power efficient subnotebooks (this is the device I am trying to support based on the Ingebic Linux kernel patch). The current kernel patch from Ingenic http://www.ingenic.cn/eng/productServ/App/JZ4730/pfCustomPage.aspx or ftp://ftp.ingenic.cn/3sw/01linux/02kernel/linux-2.6.24/linux-2.6.24.3-jz-20090218.patch.gz for the patch (I used an even older patch to start my board support but they basically only added newer CPU types in later patches). The support for my board is almost in place but I see from time to time failing applications with "illegal instruction" faults. Most shell applications work pretty fine, especially more complex GUI applications seem to fail, like a webbrowser or such. I also tested this with different GCC and glibc version which makes me pretty sure that I am seeing a kernel problem here rather than a userspace problem. I am pretty clueless how to debug this. Apropos debig as another hint: Some application work if I start them in GDB but fail outside. Any hint how to start debugging this would be greatly appreciated! And a fix would be like a dream ;) Many thanks! Cheers nils faerber -- kernel concepts GbR Tel: +49-271-771091-12 Sieghuetter Hauptweg 48 Fax: +49-271-771091-19 D-57072 Siegen Mob: +49-176-21024535 http://www.kernelconcepts.de From m.jancar@satca.net Fri Mar 6 16:55:14 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 06 Mar 2009 16:55:16 +0000 (GMT) Received: from skerikoff.satca.net ([81.90.243.194]:14528 "EHLO smtp.satca.net") by ftp.linux-mips.org with ESMTP id S20808199AbZCFQzO (ORCPT ); Fri, 6 Mar 2009 16:55:14 +0000 Received: from localhost (unknown [127.0.0.1]) by smtp.satca.net (Postfix) with ESMTP id 1EEAE158A73 for ; Fri, 6 Mar 2009 16:55:01 +0000 (UTC) X-Virus-Scanned: amavisd-new at satca.net Received: from smtp.satca.net ([127.0.0.1]) by localhost (skerikoff.satca.net [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id uIf6pehBW+FI for ; Fri, 6 Mar 2009 17:54:58 +0100 (CET) Received: from [192.168.51.254] (unknown [192.168.51.254]) by smtp.satca.net (Postfix) with ESMTP id 35A831589EF for ; Fri, 6 Mar 2009 16:54:58 +0000 (UTC) Message-ID: <49B1556E.3030903@satca.net> Date: Fri, 06 Mar 2009 17:55:10 +0100 From: Marian Jancar User-Agent: Thunderbird 2.0.0.12 (X11/20071114) MIME-Version: 1.0 To: linux-mips@linux-mips.org Subject: gcc: mips32 vs mips3 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22028 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: m.jancar@satca.net Precedence: bulk X-list: linux-mips Hi, which option is supposed to compile faster code, -mips3 or -mips32? Marian From mano@roarinelk.homelinux.net Sat Mar 7 09:35:31 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 07 Mar 2009 09:35:34 +0000 (GMT) Received: from fnoeppeil36.netpark.at ([217.175.205.164]:43739 "EHLO roarinelk.homelinux.net") by ftp.linux-mips.org with ESMTP id S21366511AbZCGJfb (ORCPT ); Sat, 7 Mar 2009 09:35:31 +0000 Received: (qmail 20058 invoked from network); 7 Mar 2009 10:35:30 +0100 Received: from scarran.roarinelk.net (192.168.0.242) by fnoeppeil36.netpark.at with SMTP; 7 Mar 2009 10:35:30 +0100 Date: Sat, 7 Mar 2009 10:35:29 +0100 From: Manuel Lauss To: Kevin Hickey Cc: ralf@linux-mips.org, linux-mips@linux-mips.org, Kevin Hickey Subject: Re: [PATCH 07/10] Alchemy: SMSC 9210 Ethernet support Message-ID: <20090307103529.23c36da0@scarran.roarinelk.net> In-Reply-To: References: <1236356409-32357-1-git-send-email-khickey@rmicorp.com> <788248524efc28ba2608ed79bfb7080ee476b12d.1236354153.git.khickey@rmicorp.com> <0b447f7e26be90a9179bdf89ca2cfd1f34c5d16e.1236354153.git.khickey@rmicorp.com> <7afc5c84989c4bc0f94181397369f284f2bb6924.1236354153.git.khickey@rmicorp.com> <0946334bbaf9883076889fe060a362b72d31e6f4.1236354153.git.khickey@rmicorp.com> <394c116b9fa5bd1865ac21d11185f09e07bd2ab5.1236354153.git.khickey@rmicorp.com> <7e632686ab9b29a94eefeb2e5dca8b091a956b95.1236354153.git.khickey@rmicorp.com> Organization: Private X-Mailer: Claws Mail 3.7.0 (GTK+ 2.14.7; i686-pc-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22029 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mano@roarinelk.homelinux.net Precedence: bulk X-list: linux-mips On Fri, 6 Mar 2009 10:20:06 -0600 Kevin Hickey wrote: > This patch adds support for the SMSC 9210 Ethernet chip, specialized for > Alchemy platforms (including the DB1300). The ethernet driver code was > provided by SMSC; the platform shim by RMI. > > Signed-off-by: Kevin Hickey > --- > drivers/net/Kconfig | 6 + > drivers/net/Makefile | 3 + > drivers/net/smsc9210/Makefile | 9 + > drivers/net/smsc9210/ioctl_118.h | 298 ++ > drivers/net/smsc9210/platform_alchemy.c | 88 + > drivers/net/smsc9210/platform_alchemy.h | 117 + > drivers/net/smsc9210/smsc9210.h | 23 + > drivers/net/smsc9210/smsc9210_main.c | 7189 +++++++++++++++++++++++++++++++ What's wrong with the in-kernel smsc911x.c driver? It can handle the 9210 just fine (we use it on an ARM board). Best regards, Manuel Lauss From mano@roarinelk.homelinux.net Sat Mar 7 09:37:32 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 07 Mar 2009 09:37:36 +0000 (GMT) Received: from fnoeppeil36.netpark.at ([217.175.205.164]:55176 "EHLO roarinelk.homelinux.net") by ftp.linux-mips.org with ESMTP id S21366536AbZCGJhc (ORCPT ); Sat, 7 Mar 2009 09:37:32 +0000 Received: (qmail 20076 invoked from network); 7 Mar 2009 10:37:31 +0100 Received: from scarran.roarinelk.net (192.168.0.242) by fnoeppeil36.netpark.at with SMTP; 7 Mar 2009 10:37:31 +0100 Date: Sat, 7 Mar 2009 10:37:31 +0100 From: Manuel Lauss To: Kevin Hickey Cc: ralf@linux-mips.org, linux-mips@linux-mips.org, Kevin Hickey Subject: Re: [PATCH 08/10] Alchemy: DB1300 blink leds on timer tick Message-ID: <20090307103731.4660e57f@scarran.roarinelk.net> In-Reply-To: References: <1236356409-32357-1-git-send-email-khickey@rmicorp.com> <788248524efc28ba2608ed79bfb7080ee476b12d.1236354153.git.khickey@rmicorp.com> <0b447f7e26be90a9179bdf89ca2cfd1f34c5d16e.1236354153.git.khickey@rmicorp.com> <7afc5c84989c4bc0f94181397369f284f2bb6924.1236354153.git.khickey@rmicorp.com> <0946334bbaf9883076889fe060a362b72d31e6f4.1236354153.git.khickey@rmicorp.com> <394c116b9fa5bd1865ac21d11185f09e07bd2ab5.1236354153.git.khickey@rmicorp.com> <7e632686ab9b29a94eefeb2e5dca8b091a956b95.1236354153.git.khickey@rmicorp.com> Organization: Private X-Mailer: Claws Mail 3.7.0 (GTK+ 2.14.7; i686-pc-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22030 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mano@roarinelk.homelinux.net Precedence: bulk X-list: linux-mips On Fri, 6 Mar 2009 10:20:07 -0600 Kevin Hickey wrote: > Blinks the dots on the hex display on the DB1300 board every 1000 timer ticks. > This can help tell the difference between a soft and hard hung board. > > Signed-off-by: Kevin Hickey > --- > arch/mips/alchemy/common/time.c | 16 ++++++++++++++++ > 1 files changed, 16 insertions(+), 0 deletions(-) > > diff --git a/arch/mips/alchemy/common/time.c b/arch/mips/alchemy/common/time.c > index f58d4ff..2b2f6bf 100644 > --- a/arch/mips/alchemy/common/time.c > +++ b/arch/mips/alchemy/common/time.c > @@ -39,6 +39,10 @@ > #include > #include > > +#ifdef CONFIG_MIPS_DB1300 > +#include > +#endif > + > /* 32kHz clock enabled and detected */ > #define CNTR_OK (SYS_CNTRL_E0 | SYS_CNTRL_32S) > > @@ -60,6 +64,11 @@ static struct clocksource au1x_counter1_clocksource = { > static int au1x_rtcmatch2_set_next_event(unsigned long delta, > struct clock_event_device *cd) > { > +#ifdef CONFIG_MIPS_DB1300 > + static u8 dots = 1; > + static u32 delayer = 0; > +#endif > + > delta += au_readl(SYS_RTCREAD); > /* wait for register access */ > while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M21) > @@ -67,6 +76,13 @@ static int au1x_rtcmatch2_set_next_event(unsigned long delta, > au_writel(delta, SYS_RTCMATCH2); > au_sync(); > > +#ifdef CONFIG_MIPS_DB1300 > + if (++delayer % 1000 == 0) { > + db_set_hex_dots(dots++); > + dots %= 4; > + } > +#endif > + > return 0; > } > Please don't do that. I'd still like to get all devboard hackery out of code in common/ (at least for mainline kernels; what you do to the RMI-sources I don't care about). (btw, I made something similar for the DB1200 a while ago: http://mlau.at/files/au1xxx-updates/4040-Alchemy-DB1200-cpu-idle-counter.patch ) Best regards, Manuel Lauss From mano@roarinelk.homelinux.net Sat Mar 7 09:49:34 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 07 Mar 2009 09:49:37 +0000 (GMT) Received: from fnoeppeil36.netpark.at ([217.175.205.164]:22991 "EHLO roarinelk.homelinux.net") by ftp.linux-mips.org with ESMTP id S21103232AbZCGJte (ORCPT ); Sat, 7 Mar 2009 09:49:34 +0000 Received: (qmail 20144 invoked from network); 7 Mar 2009 10:49:33 +0100 Received: from scarran.roarinelk.net (192.168.0.242) by fnoeppeil36.netpark.at with SMTP; 7 Mar 2009 10:49:33 +0100 Date: Sat, 7 Mar 2009 10:49:32 +0100 From: Manuel Lauss To: Kevin Hickey Cc: ralf@linux-mips.org, linux-mips@linux-mips.org, Kevin Hickey Subject: Re: [PATCH 02/10] Alchemy: Au1300 new interrupt controller Message-ID: <20090307104932.49408650@scarran.roarinelk.net> In-Reply-To: <0b447f7e26be90a9179bdf89ca2cfd1f34c5d16e.1236354153.git.khickey@rmicorp.com> References: <1236356409-32357-1-git-send-email-khickey@rmicorp.com> <788248524efc28ba2608ed79bfb7080ee476b12d.1236354153.git.khickey@rmicorp.com> <0b447f7e26be90a9179bdf89ca2cfd1f34c5d16e.1236354153.git.khickey@rmicorp.com> Organization: Private X-Mailer: Claws Mail 3.7.0 (GTK+ 2.14.7; i686-pc-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22031 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mano@roarinelk.homelinux.net Precedence: bulk X-list: linux-mips On Fri, 6 Mar 2009 10:20:01 -0600 Kevin Hickey wrote: > The Au1300 has a new interrupt controller (relative to the rest of the Alchemy > line). The differences were great enough to justify adding a whole new module. > Included in this patch is the new interrupt controller, a new implementation of > the cascade interrupt controller on the DB1300 board and some code to drive > LEDs on the DB1300 that is used by the interrupt controller. > > A small change was made to the existing interrupt controller; it is "ifdef'd > out" for Au1300. > > Since the cascade interrupt controller is virtually indentical (with the > exception of some constants) between the DB1300 and DB1200, a future > optimization may be to use the same code for both boards. > diff --git a/arch/mips/alchemy/common/Makefile b/arch/mips/alchemy/common/Makefile > index d50d476..85ffa2e 100644 > --- a/arch/mips/alchemy/common/Makefile > +++ b/arch/mips/alchemy/common/Makefile > @@ -7,7 +7,9 @@ > > obj-y += prom.o irq.o puts.o time.o reset.o \ > clocks.o platform.o power.o setup.o \ > - sleeper.o dma.o dbdma.o gpio.o > + sleeper.o dma.o dbdma.o gpio.o gpio_int.o > + > +obj-$(CONFIG_SOC_AU13XX) += au13xx_res.o belongs to another patch in the series? > diff --git a/arch/mips/alchemy/common/gpio_int.c b/arch/mips/alchemy/common/gpio_int.c > new file mode 100644 > index 0000000..c09b793 > --- /dev/null > +++ b/arch/mips/alchemy/common/gpio_int.c > @@ -0,0 +1,268 @@ > +/* > + * Copyright 2008 RMI Corporation > + * Author: Kevin Hickey > + * > + * This program is free software; you can redistribute it and/or modify it > + * under the terms of the GNU General Public License as published by the > + * Free Software Foundation; either version 2 of the License, or (at your > + * option) any later version. > + * > + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED > + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF > + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN > + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, > + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT > + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF > + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON > + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT > + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF > + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. > + * > + * You should have received a copy of the GNU General Public License along > + * with this program; if not, write to the Free Software Foundation, Inc., > + * 675 Mass Ave, Cambridge, MA 02139, USA. > + */ > + > +#ifdef CONFIG_AU_GPIO_INT_CNTLR > + > +#include > +#include > +#include /* For functions called by do_IRQ */ > +#include > + > +#include > +#include > + > +#include Please try to keep common/ free of anything not related to the chip itself. > +asmlinkage void plat_irq_dispatch(void) > +{ > + unsigned int intr; > + u32 bank; > + u32 reg_msk; > + unsigned int pending = read_c0_status() & read_c0_cause(); > + /* > + * C0 timer tick > + */ > + if (pending & CAUSEF_IP7) > + do_IRQ(MIPS_CPU_IRQ_BASE + 7); > + else if (pending & (CAUSEF_IP2 | CAUSEF_IP3)) { > + intr = au_ioread32(&gpio_int->pri_enc); > + bank = GPINT_BANK_FROM_INT(intr); > + reg_msk = GPINT_BIT_FROM_INT(bank, intr); > + > + if (intr != 127) { > + if (pending & CAUSEF_IP3) > + board_irq_dispatch(intr); What is this supposed to do? (missed debug code?) > + > + do_IRQ(GPINT_LINUX_IRQ_OFFSET + intr); > + } > + } else { > + printk(KERN_WARNING > + "ALCHEMY GPIO_INT: Unexpected cause was set. %08x\n", > + pending); > + } should probably call spurious_interrupt() here. > + > +} > + > +#endif > diff --git a/arch/mips/alchemy/common/irq.c b/arch/mips/alchemy/common/irq.c > index c88c821..f8742dd 100644 > --- a/arch/mips/alchemy/common/irq.c > +++ b/arch/mips/alchemy/common/irq.c > @@ -24,6 +24,7 @@ > * with this program; if not, write to the Free Software Foundation, Inc., > * 675 Mass Ave, Cambridge, MA 02139, USA. > */ > +#ifdef CONFIG_AU_INT_CNTLR > > #include > #include > @@ -609,3 +610,5 @@ void __init arch_init_irq(void) > > set_c0_status(IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3); > } > + > +#endif Why not make compilation of the original irq.c file dependent on AU_INT_CNTRL? (i.e. change the Makefile to obj-$(CONFIG_AU_INT_CNTRL) += irq.o for non-au1300 parts). (FWIW, I'm working on getting rid of the explicit CPU-type config options and instead do runtime detection and configuration of dma/dbdma/irq/ and so on). Best regards, Manuel Lauss From sshtylyov@ru.mvista.com Sat Mar 7 10:01:29 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 07 Mar 2009 10:01:32 +0000 (GMT) Received: from h155.mvista.com ([63.81.120.155]:44500 "EHLO imap.sh.mvista.com") by ftp.linux-mips.org with ESMTP id S21103082AbZCGKB3 (ORCPT ); Sat, 7 Mar 2009 10:01:29 +0000 Received: from [127.0.0.1] (unknown [10.150.0.9]) by imap.sh.mvista.com (Postfix) with ESMTP id 444DB3EC9; Sat, 7 Mar 2009 02:01:25 -0800 (PST) Message-ID: <49B245F1.2090200@ru.mvista.com> Date: Sat, 07 Mar 2009 13:01:21 +0300 From: Sergei Shtylyov User-Agent: Thunderbird 2.0.0.19 (Windows/20081209) MIME-Version: 1.0 To: Kevin Hickey Cc: ralf@linux-mips.org, linux-mips@linux-mips.org Subject: Re: [PATCH 06/10] Alchemy: Au1300 USB support References: <> <1236356409-32357-1-git-send-email-khickey@rmicorp.com> <788248524efc28ba2608ed79bfb7080ee476b12d.1236354153.git.khickey@rmicorp.com> <0b447f7e26be90a9179bdf89ca2cfd1f34c5d16e.1236354153.git.khickey@rmicorp.com> <7afc5c84989c4bc0f94181397369f284f2bb6924.1236354153.git.khickey@rmicorp.com> <0946334bbaf9883076889fe060a362b72d31e6f4.1236354153.git.khickey@rmicorp.com> <394c116b9fa5bd1865ac21d11185f09e07bd2ab5.1236354153.git.khickey@rmicorp.com> <7e632686ab9b29a94eefeb2e5dca8b091a956b95.1236354153.git.khickey@rmicorp.com> In-Reply-To: <7e632686ab9b29a94eefeb2e5dca8b091a956b95.1236354153.git.khickey@rmicorp.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22032 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sshtylyov@ru.mvista.com Precedence: bulk X-list: linux-mips Hello. Kevin Hickey wrote: > Adds support for USB 2.0 on the Au1300 SOC. > > Signed-off-by: Kevin Hickey > [...] > diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig > index 83babb0..a50d053 100644 > --- a/drivers/usb/Kconfig > +++ b/drivers/usb/Kconfig > @@ -55,6 +55,7 @@ config USB_ARCH_HAS_EHCI > boolean > default y if PPC_83xx > default y if SOC_AU1200 > + default y if SOC_AU13XX > Why not: default y if SOC_AU1200 || SOC_AU13XX > diff --git a/drivers/usb/host/ehci-au13xx.c b/drivers/usb/host/ehci-au13xx.c > new file mode 100644 > index 0000000..fe03667 > --- /dev/null > +++ b/drivers/usb/host/ehci-au13xx.c > @@ -0,0 +1,213 @@ > +/* > + * Copyright 2008 RMI Corporation > + * Author: Kevin Hickey > + * > + * This program is free software; you can redistribute it and/or modify it > + * under the terms of the GNU General Public License as published by the > + * Free Software Foundation; either version 2 of the License, or (at your > + * option) any later version. > + * > + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED > + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF > + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN > + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, > + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT > + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF > + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON > + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT > + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF > + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. > + * > + * You should have received a copy of the GNU General Public License along > + * with this program; if not, write to the Free Software Foundation, Inc., > + * 675 Mass Ave, Cambridge, MA 02139, USA. > + * > + * Based on ehci-au1xxx.c. > + */ > + > +#include > +#include > + > + > +extern int usb_disabled(void); > + > +static void au13xx_start_ehc(void) > +{ > + AU13XX_USB* au13xx_usb = (AU13XX_USB*)(KSEG1 | USB_BASE_PHYS_ADDR); > Your coding style is not acceptable -- run your patched thru scruipts/checkpatch.pl please. > + /* > + * Enable clocks. > + */ > + AU_SET_BITS_32(USB_DWC_CTRL3_EHC_CLKEN, &au13xx_usb->dwc_ctrl3); > + > + /* > + * Take the host controller block out of reset > + */ > + AU_SET_BITS_32(USB_DWC_CTRL1_HSTRS, &au13xx_usb->dwc_ctrl1); > + > + /* > + * Enable all of the PHYs > + */ > + AU_SET_BITS_32(USB_DWC_CTRL2_PHYRS | USB_DWC_CTRL2_PHY0RS | USB_DWC_CTRL2_PH1RS, > + &au13xx_usb->dwc_ctrl2); > + > + /* > + * Enable interrupts > + */ > + AU_SET_BITS_32(USB_INTR_EHCI, &au13xx_usb->intr_enable); > + > + /* > + * This bit enables coherent DMA. > + */ > + AU_SET_BITS_32(USB_SBUS_CTRL_SBCA, &au13xx_usb->sbus_ctrl); > + asm("sync"); > Don't we have au_sync()? > +static int ehci_hcd_au13xx_drv_probe(struct platform_device *pdev) > +{ > [...] > + au13xx_start_ehc(); > + > + ehci = hcd_to_ehci(hcd); > + ehci->caps = hcd->regs; > + ehci->regs = hcd->regs + HC_LENGTH(readl(&ehci->caps->hc_capbase)); > + printk("ehci->regs = %p\n", ehci->regs); > printk() should have KERN_* facility. > +static struct platform_driver ehci_hcd_au13xx_driver = { > + .probe = ehci_hcd_au13xx_drv_probe, > + .remove = ehci_hcd_au13xx_drv_remove, > + .shutdown = usb_hcd_platform_shutdown, > + .suspend = NULL, > + .resume = NULL, > No dire need to explicitly initializer these two... WBR, Sergei From khickey@rmicorp.com Sat Mar 7 19:05:05 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 07 Mar 2009 19:05:07 +0000 (GMT) Received: from mx1.rmicorp.com ([63.111.213.197]:33036 "EHLO mx1.rmicorp.com") by ftp.linux-mips.org with ESMTP id S21366784AbZCGTFF (ORCPT ); Sat, 7 Mar 2009 19:05:05 +0000 Received: from 10.8.0.23 ([10.8.0.23]) by hq-ex-mb01.razamicroelectronics.com ([10.1.1.40]) via Exchange Front-End Server webmail.razamicroelectronics.com ([10.1.1.41]) with Microsoft Exchange Server HTTP-DAV ; Sat, 7 Mar 2009 19:04:57 +0000 Received: from kh-d820 by webmail.razamicroelectronics.com; 07 Mar 2009 13:04:58 -0600 Subject: Re: [PATCH 08/10] Alchemy: DB1300 blink leds on timer tick From: Kevin Hickey To: Manuel Lauss Cc: ralf@linux-mips.org, linux-mips@linux-mips.org In-Reply-To: <20090307103731.4660e57f@scarran.roarinelk.net> References: <1236356409-32357-1-git-send-email-khickey@rmicorp.com> <788248524efc28ba2608ed79bfb7080ee476b12d.1236354153.git.khickey@rmicorp.com> <0b447f7e26be90a9179bdf89ca2cfd1f34c5d16e.1236354153.git.khickey@rmicorp.com> <7afc5c84989c4bc0f94181397369f284f2bb6924.1236354153.git.khickey@rmicorp.com> <0946334bbaf9883076889fe060a362b72d31e6f4.1236354153.git.khickey@rmicorp.com> <394c116b9fa5bd1865ac21d11185f09e07bd2ab5.1236354153.git.khickey@rmicorp.com> <7e632686ab9b29a94eefeb2e5dca8b091a956b95.1236354153.git.khickey@rmicorp.com> <20090307103731.4660e57f@scarran.roarinelk.net> Content-Type: text/plain Content-Transfer-Encoding: 7bit Date: Sat, 07 Mar 2009 13:04:57 -0600 Message-Id: <1236452697.9848.1.camel@kh-d820> Mime-Version: 1.0 X-Mailer: Evolution 2.22.3.1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22033 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: khickey@rmicorp.com Precedence: bulk X-list: linux-mips On Sat, 2009-03-07 at 10:37 +0100, Manuel Lauss wrote: > On Fri, 6 Mar 2009 10:20:07 -0600 > Kevin Hickey wrote: > > > Blinks the dots on the hex display on the DB1300 board every 1000 timer ticks. > > This can help tell the difference between a soft and hard hung board. > Please don't do that. I'd still like to get all devboard hackery out > of code in common/ (at least for mainline kernels; what you do to the > RMI-sources I don't care about). Can you suggest an alternative? Or are you saying that this functionality does not belong in the mainline kernel at all? -- Kevin Hickey Alchemy Solutions RMI Corporation khickey@rmicorp.com P: 512.691.8044 From khickey@rmicorp.com Sat Mar 7 19:06:22 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 07 Mar 2009 19:06:24 +0000 (GMT) Received: from mx1.rmicorp.com ([63.111.213.197]:51468 "EHLO mx1.rmicorp.com") by ftp.linux-mips.org with ESMTP id S21366793AbZCGTGW (ORCPT ); Sat, 7 Mar 2009 19:06:22 +0000 Received: from 10.8.0.23 ([10.8.0.23]) by hq-ex-mb01.razamicroelectronics.com ([10.1.1.40]) via Exchange Front-End Server webmail.razamicroelectronics.com ([10.1.1.41]) with Microsoft Exchange Server HTTP-DAV ; Sat, 7 Mar 2009 19:06:15 +0000 Received: from kh-d820 by webmail.razamicroelectronics.com; 07 Mar 2009 13:06:15 -0600 Subject: Re: [PATCH 07/10] Alchemy: SMSC 9210 Ethernet support From: Kevin Hickey To: Manuel Lauss Cc: ralf@linux-mips.org, linux-mips@linux-mips.org In-Reply-To: <20090307103529.23c36da0@scarran.roarinelk.net> References: <1236356409-32357-1-git-send-email-khickey@rmicorp.com> <788248524efc28ba2608ed79bfb7080ee476b12d.1236354153.git.khickey@rmicorp.com> <0b447f7e26be90a9179bdf89ca2cfd1f34c5d16e.1236354153.git.khickey@rmicorp.com> <7afc5c84989c4bc0f94181397369f284f2bb6924.1236354153.git.khickey@rmicorp.com> <0946334bbaf9883076889fe060a362b72d31e6f4.1236354153.git.khickey@rmicorp.com> <394c116b9fa5bd1865ac21d11185f09e07bd2ab5.1236354153.git.khickey@rmicorp.com> <7e632686ab9b29a94eefeb2e5dca8b091a956b95.1236354153.git.khickey@rmicorp.com> <20090307103529.23c36da0@scarran.roarinelk.net> Content-Type: text/plain Content-Transfer-Encoding: 7bit Date: Sat, 07 Mar 2009 13:06:05 -0600 Message-Id: <1236452765.9848.3.camel@kh-d820> Mime-Version: 1.0 X-Mailer: Evolution 2.22.3.1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22034 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: khickey@rmicorp.com Precedence: bulk X-list: linux-mips On Sat, 2009-03-07 at 10:35 +0100, Manuel Lauss wrote: > On Fri, 6 Mar 2009 10:20:06 -0600 > Kevin Hickey wrote: > > > This patch adds support for the SMSC 9210 Ethernet chip, specialized for > > Alchemy platforms (including the DB1300). The ethernet driver code was > > provided by SMSC; the platform shim by RMI. > What's wrong with the in-kernel smsc911x.c driver? It can handle the > 9210 just fine (we use it on an ARM board). I was unaware that smsc911x.c could handle 9210. I'll try it out sometime and if it works then we can drop this one. =Kevin -- Kevin Hickey Alchemy Solutions RMI Corporation khickey@rmicorp.com P: 512.691.8044 From khickey@rmicorp.com Sat Mar 7 19:11:35 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 07 Mar 2009 19:11:37 +0000 (GMT) Received: from mx1.rmicorp.com ([63.111.213.197]:61197 "EHLO mx1.rmicorp.com") by ftp.linux-mips.org with ESMTP id S21366931AbZCGTLf (ORCPT ); Sat, 7 Mar 2009 19:11:35 +0000 Received: from 10.8.0.23 ([10.8.0.23]) by hq-ex-mb01.razamicroelectronics.com ([10.1.1.40]) via Exchange Front-End Server webmail.razamicroelectronics.com ([10.1.1.41]) with Microsoft Exchange Server HTTP-DAV ; Sat, 7 Mar 2009 19:11:28 +0000 Received: from kh-d820 by webmail.razamicroelectronics.com; 07 Mar 2009 13:11:28 -0600 Subject: Re: [PATCH 06/10] Alchemy: Au1300 USB support From: Kevin Hickey To: Sergei Shtylyov Cc: ralf@linux-mips.org, linux-mips@linux-mips.org In-Reply-To: <49B245F1.2090200@ru.mvista.com> References: <> <1236356409-32357-1-git-send-email-khickey@rmicorp.com> <788248524efc28ba2608ed79bfb7080ee476b12d.1236354153.git.khickey@rmicorp.com> <0b447f7e26be90a9179bdf89ca2cfd1f34c5d16e.1236354153.git.khickey@rmicorp.com> <7afc5c84989c4bc0f94181397369f284f2bb6924.1236354153.git.khickey@rmicorp.com> <0946334bbaf9883076889fe060a362b72d31e6f4.1236354153.git.khickey@rmicorp.com> <394c116b9fa5bd1865ac21d11185f09e07bd2ab5.1236354153.git.khickey@rmicorp.com> <7e632686ab9b29a94eefeb2e5dca8b091a956b95.1236354153.git.khickey@rmicorp.com> <49B245F1.2090200@ru.mvista.com> Content-Type: text/plain Content-Transfer-Encoding: 7bit Date: Sat, 07 Mar 2009 13:11:28 -0600 Message-Id: <1236453088.9848.7.camel@kh-d820> Mime-Version: 1.0 X-Mailer: Evolution 2.22.3.1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22035 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: khickey@rmicorp.com Precedence: bulk X-list: linux-mips On Sat, 2009-03-07 at 13:01 +0300, Sergei Shtylyov wrote: > Hello. > > Kevin Hickey wrote: > > > Adds support for USB 2.0 on the Au1300 SOC. > > > > Signed-off-by: Kevin Hickey > > > [...] > > diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig > > index 83babb0..a50d053 100644 > > --- a/drivers/usb/Kconfig > > +++ b/drivers/usb/Kconfig > > @@ -55,6 +55,7 @@ config USB_ARCH_HAS_EHCI > > boolean > > default y if PPC_83xx > > default y if SOC_AU1200 > > + default y if SOC_AU13XX > > > > Why not: > > default y if SOC_AU1200 || SOC_AU13XX > I was just following the pattern... there were already two other explicit "default y if" lines. > > > diff --git a/drivers/usb/host/ehci-au13xx.c b/drivers/usb/host/ehci-au13xx.c > > new file mode 100644 > > index 0000000..fe03667 > > --- /dev/null > > +++ b/drivers/usb/host/ehci-au13xx.c > > @@ -0,0 +1,213 @@ > > +/* > > + * Copyright 2008 RMI Corporation > > + * Author: Kevin Hickey > > + * > > + * This program is free software; you can redistribute it and/or modify it > > + * under the terms of the GNU General Public License as published by the > > + * Free Software Foundation; either version 2 of the License, or (at your > > + * option) any later version. > > + * > > + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED > > + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF > > + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN > > + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, > > + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT > > + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF > > + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON > > + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT > > + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF > > + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. > > + * > > + * You should have received a copy of the GNU General Public License along > > + * with this program; if not, write to the Free Software Foundation, Inc., > > + * 675 Mass Ave, Cambridge, MA 02139, USA. > > + * > > + * Based on ehci-au1xxx.c. > > + */ > > + > > +#include > > +#include > > + > > + > > +extern int usb_disabled(void); > > + > > +static void au13xx_start_ehc(void) > > +{ > > + AU13XX_USB* au13xx_usb = (AU13XX_USB*)(KSEG1 | USB_BASE_PHYS_ADDR); > > > > Your coding style is not acceptable -- run your patched thru > scruipts/checkpatch.pl please. Sorry about that. > > > + /* > > + * Enable clocks. > > + */ > > + AU_SET_BITS_32(USB_DWC_CTRL3_EHC_CLKEN, &au13xx_usb->dwc_ctrl3); > > + > > + /* > > + * Take the host controller block out of reset > > + */ > > + AU_SET_BITS_32(USB_DWC_CTRL1_HSTRS, &au13xx_usb->dwc_ctrl1); > > + > > + /* > > + * Enable all of the PHYs > > + */ > > + AU_SET_BITS_32(USB_DWC_CTRL2_PHYRS | USB_DWC_CTRL2_PHY0RS | USB_DWC_CTRL2_PH1RS, > > + &au13xx_usb->dwc_ctrl2); > > + > > + /* > > + * Enable interrupts > > + */ > > + AU_SET_BITS_32(USB_INTR_EHCI, &au13xx_usb->intr_enable); > > + > > + /* > > + * This bit enables coherent DMA. > > + */ > > + AU_SET_BITS_32(USB_SBUS_CTRL_SBCA, &au13xx_usb->sbus_ctrl); > > + asm("sync"); > > > > Don't we have au_sync()? Yes, and I should have used it here :) > > > +static int ehci_hcd_au13xx_drv_probe(struct platform_device *pdev) > > +{ > > > [...] > > + au13xx_start_ehc(); > > + > > + ehci = hcd_to_ehci(hcd); > > + ehci->caps = hcd->regs; > > + ehci->regs = hcd->regs + HC_LENGTH(readl(&ehci->caps->hc_capbase)); > > + printk("ehci->regs = %p\n", ehci->regs); > > > > printk() should have KERN_* facility. Agreed. In fact this is probably just leftover bringup/debug code that should be eliminated. > > > +static struct platform_driver ehci_hcd_au13xx_driver = { > > + .probe = ehci_hcd_au13xx_drv_probe, > > + .remove = ehci_hcd_au13xx_drv_remove, > > + .shutdown = usb_hcd_platform_shutdown, > > + .suspend = NULL, > > + .resume = NULL, > > > > No dire need to explicitly initializer these two... Copy-paste laziness strikes again... > > WBR, Sergei > > -- Kevin Hickey Alchemy Solutions RMI Corporation khickey@rmicorp.com P: 512.691.8044 From khickey@rmicorp.com Sat Mar 7 19:20:15 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 07 Mar 2009 19:20:17 +0000 (GMT) Received: from mx1.rmicorp.com ([63.111.213.197]:62735 "EHLO mx1.rmicorp.com") by ftp.linux-mips.org with ESMTP id S21366932AbZCGTUP (ORCPT ); Sat, 7 Mar 2009 19:20:15 +0000 Received: from 10.8.0.23 ([10.8.0.23]) by hq-ex-mb01.razamicroelectronics.com ([10.1.1.40]) via Exchange Front-End Server webmail.razamicroelectronics.com ([10.1.1.41]) with Microsoft Exchange Server HTTP-DAV ; Sat, 7 Mar 2009 19:20:08 +0000 Received: from kh-d820 by webmail.razamicroelectronics.com; 07 Mar 2009 13:20:08 -0600 Subject: Re: [PATCH 02/10] Alchemy: Au1300 new interrupt controller From: Kevin Hickey To: Manuel Lauss Cc: ralf@linux-mips.org, linux-mips@linux-mips.org In-Reply-To: <20090307104932.49408650@scarran.roarinelk.net> References: <1236356409-32357-1-git-send-email-khickey@rmicorp.com> <788248524efc28ba2608ed79bfb7080ee476b12d.1236354153.git.khickey@rmicorp.com> <0b447f7e26be90a9179bdf89ca2cfd1f34c5d16e.1236354153.git.khickey@rmicorp.com> <20090307104932.49408650@scarran.roarinelk.net> Content-Type: text/plain Content-Transfer-Encoding: 7bit Date: Sat, 07 Mar 2009 13:20:08 -0600 Message-Id: <1236453608.9848.16.camel@kh-d820> Mime-Version: 1.0 X-Mailer: Evolution 2.22.3.1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22036 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: khickey@rmicorp.com Precedence: bulk X-list: linux-mips On Sat, 2009-03-07 at 10:49 +0100, Manuel Lauss wrote: > On Fri, 6 Mar 2009 10:20:01 -0600 > Kevin Hickey wrote: > > > The Au1300 has a new interrupt controller (relative to the rest of the Alchemy > > line). The differences were great enough to justify adding a whole new module. > > Included in this patch is the new interrupt controller, a new implementation of > > the cascade interrupt controller on the DB1300 board and some code to drive > > LEDs on the DB1300 that is used by the interrupt controller. > > > > A small change was made to the existing interrupt controller; it is "ifdef'd > > out" for Au1300. > > > > Since the cascade interrupt controller is virtually indentical (with the > > exception of some constants) between the DB1300 and DB1200, a future > > optimization may be to use the same code for both boards. > > > diff --git a/arch/mips/alchemy/common/Makefile b/arch/mips/alchemy/common/Makefile > > index d50d476..85ffa2e 100644 > > --- a/arch/mips/alchemy/common/Makefile > > +++ b/arch/mips/alchemy/common/Makefile > > @@ -7,7 +7,9 @@ > > > > obj-y += prom.o irq.o puts.o time.o reset.o \ > > clocks.o platform.o power.o setup.o \ > > - sleeper.o dma.o dbdma.o gpio.o > > + sleeper.o dma.o dbdma.o gpio.o gpio_int.o > > + > > +obj-$(CONFIG_SOC_AU13XX) += au13xx_res.o > > belongs to another patch in the series? Yes, but git-add wouldn't let me split the hunk so I just left it... figured the series would be taken as a whole anyway. > > > > diff --git a/arch/mips/alchemy/common/gpio_int.c b/arch/mips/alchemy/common/gpio_int.c > > new file mode 100644 > > index 0000000..c09b793 > > --- /dev/null > > +++ b/arch/mips/alchemy/common/gpio_int.c > > @@ -0,0 +1,268 @@ > > +/* > > + * Copyright 2008 RMI Corporation > > + * Author: Kevin Hickey > > + * > > + * This program is free software; you can redistribute it and/or modify it > > + * under the terms of the GNU General Public License as published by the > > + * Free Software Foundation; either version 2 of the License, or (at your > > + * option) any later version. > > + * > > + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED > > + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF > > + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN > > + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, > > + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT > > + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF > > + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON > > + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT > > + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF > > + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. > > + * > > + * You should have received a copy of the GNU General Public License along > > + * with this program; if not, write to the Free Software Foundation, Inc., > > + * 675 Mass Ave, Cambridge, MA 02139, USA. > > + */ > > + > > +#ifdef CONFIG_AU_GPIO_INT_CNTLR > > + > > +#include > > +#include > > +#include /* For functions called by do_IRQ */ > > +#include > > + > > +#include > > +#include > > + > > +#include > > Please try to keep common/ free of anything not related to the chip > itself. > I have board_irq_dispatch() in there. I should move that to some other non-dev-board specific include. > > > > +asmlinkage void plat_irq_dispatch(void) > > +{ > > + unsigned int intr; > > + u32 bank; > > + u32 reg_msk; > > + unsigned int pending = read_c0_status() & read_c0_cause(); > > + /* > > + * C0 timer tick > > + */ > > + if (pending & CAUSEF_IP7) > > + do_IRQ(MIPS_CPU_IRQ_BASE + 7); > > + else if (pending & (CAUSEF_IP2 | CAUSEF_IP3)) { > > + intr = au_ioread32(&gpio_int->pri_enc); > > + bank = GPINT_BANK_FROM_INT(intr); > > + reg_msk = GPINT_BIT_FROM_INT(bank, intr); > > + > > + if (intr != 127) { > > + if (pending & CAUSEF_IP3) > > + board_irq_dispatch(intr); > > What is this supposed to do? (missed debug code?) board_irq_dispatch (which as I said above should be in a non-devboard include) is used to display the IRQ number on the hex LEDs on the DB1300 board. I tried to keep it generic so that other boards could do what they want or leave it unimplemented and have it optimized out. The CAUSEF_IP3 part is there to not display the timer tick (since it pretty much floods out the other IRQ displays). I should really do that segregation in the board_irq_dispatch call; I was pretty focused on my board when I wrote this code. > > > + > > + do_IRQ(GPINT_LINUX_IRQ_OFFSET + intr); > > + } > > + } else { > > + printk(KERN_WARNING > > + "ALCHEMY GPIO_INT: Unexpected cause was set. %08x\n", > > + pending); > > + } > > should probably call spurious_interrupt() here. Agreed. > > > > + > > +} > > + > > +#endif > > diff --git a/arch/mips/alchemy/common/irq.c b/arch/mips/alchemy/common/irq.c > > index c88c821..f8742dd 100644 > > --- a/arch/mips/alchemy/common/irq.c > > +++ b/arch/mips/alchemy/common/irq.c > > @@ -24,6 +24,7 @@ > > * with this program; if not, write to the Free Software Foundation, Inc., > > * 675 Mass Ave, Cambridge, MA 02139, USA. > > */ > > +#ifdef CONFIG_AU_INT_CNTLR > > > > #include > > #include > > @@ -609,3 +610,5 @@ void __init arch_init_irq(void) > > > > set_c0_status(IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3); > > } > > + > > +#endif > > Why not make compilation of the original irq.c file dependent on > AU_INT_CNTRL? (i.e. change the Makefile to > obj-$(CONFIG_AU_INT_CNTRL) += irq.o > for non-au1300 parts). Good idea. I'm still getting used to some of the build system options so they're not always instinct. > > (FWIW, I'm working on getting rid of the explicit CPU-type config > options and instead do runtime detection and configuration of > dma/dbdma/irq/ and so on). Why? Won't that just lead to a larger kernel binary since it will have all of the tables in it? I would prefer to only compile in the data that I need. Unless I'm missing what you're doing... > > > Best regards, > Manuel Lauss -- Kevin Hickey Alchemy Solutions RMI Corporation khickey@rmicorp.com P: 512.691.8044 From mano@roarinelk.homelinux.net Sun Mar 8 08:37:33 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 08 Mar 2009 08:37:35 +0000 (GMT) Received: from fnoeppeil36.netpark.at ([217.175.205.164]:23512 "EHLO roarinelk.homelinux.net") by ftp.linux-mips.org with ESMTP id S20808857AbZCHIhd (ORCPT ); Sun, 8 Mar 2009 08:37:33 +0000 Received: (qmail 27627 invoked from network); 8 Mar 2009 09:37:31 +0100 Received: from scarran.roarinelk.net (192.168.0.242) by fnoeppeil36.netpark.at with SMTP; 8 Mar 2009 09:37:31 +0100 Date: Sun, 8 Mar 2009 09:37:31 +0100 From: Manuel Lauss To: Kevin Hickey Cc: ralf@linux-mips.org, linux-mips@linux-mips.org Subject: Re: [PATCH 08/10] Alchemy: DB1300 blink leds on timer tick Message-ID: <20090308093731.1e7a9067@scarran.roarinelk.net> In-Reply-To: <1236452697.9848.1.camel@kh-d820> References: <1236356409-32357-1-git-send-email-khickey@rmicorp.com> <788248524efc28ba2608ed79bfb7080ee476b12d.1236354153.git.khickey@rmicorp.com> <0b447f7e26be90a9179bdf89ca2cfd1f34c5d16e.1236354153.git.khickey@rmicorp.com> <7afc5c84989c4bc0f94181397369f284f2bb6924.1236354153.git.khickey@rmicorp.com> <0946334bbaf9883076889fe060a362b72d31e6f4.1236354153.git.khickey@rmicorp.com> <394c116b9fa5bd1865ac21d11185f09e07bd2ab5.1236354153.git.khickey@rmicorp.com> <7e632686ab9b29a94eefeb2e5dca8b091a956b95.1236354153.git.khickey@rmicorp.com> <20090307103731.4660e57f@scarran.roarinelk.net> <1236452697.9848.1.camel@kh-d820> Organization: Private X-Mailer: Claws Mail 3.7.0 (GTK+ 2.14.7; i686-pc-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22037 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mano@roarinelk.homelinux.net Precedence: bulk X-list: linux-mips On Sat, 07 Mar 2009 13:04:57 -0600 Kevin Hickey wrote: > On Sat, 2009-03-07 at 10:37 +0100, Manuel Lauss wrote: > > On Fri, 6 Mar 2009 10:20:07 -0600 > > Kevin Hickey wrote: > > > > > Blinks the dots on the hex display on the DB1300 board every 1000 timer ticks. > > > This can help tell the difference between a soft and hard hung board. > > > Please don't do that. I'd still like to get all devboard hackery out > > of code in common/ (at least for mainline kernels; what you do to the > > RMI-sources I don't care about). > > Can you suggest an alternative? Or are you saying that this > functionality does not belong in the mainline kernel at all? > How about this? No ifdefery, and every board can implement its own board_timer_set callback to blink some leds. (Note, I still don't feel this is "right", but ultimately it's not up you anyway). diff --git a/arch/mips/alchemy/common/time.c b/arch/mips/alchemy/common/time.c index f58d4ff..ac448c2 100644 --- a/arch/mips/alchemy/common/time.c +++ b/arch/mips/alchemy/common/time.c @@ -44,6 +44,8 @@ extern int allow_au1k_wait; /* default off for CP0 Counter */ +void (*board_timer_set)(void) = NULL; + static cycle_t au1x_counter1_read(void) { return au_readl(SYS_RTCREAD); @@ -67,6 +69,9 @@ static int au1x_rtcmatch2_set_next_event(unsigned long delta, au_writel(delta, SYS_RTCMATCH2); au_sync(); + if (board_timer_set) + board_timer_set(); + return 0; } From mano@roarinelk.homelinux.net Sun Mar 8 08:49:14 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 08 Mar 2009 08:49:17 +0000 (GMT) Received: from fnoeppeil36.netpark.at ([217.175.205.164]:40077 "EHLO roarinelk.homelinux.net") by ftp.linux-mips.org with ESMTP id S20807986AbZCHItN (ORCPT ); Sun, 8 Mar 2009 08:49:13 +0000 Received: (qmail 27698 invoked from network); 8 Mar 2009 09:49:12 +0100 Received: from scarran.roarinelk.net (192.168.0.242) by fnoeppeil36.netpark.at with SMTP; 8 Mar 2009 09:49:12 +0100 Date: Sun, 8 Mar 2009 09:49:12 +0100 From: Manuel Lauss To: Kevin Hickey Cc: ralf@linux-mips.org, linux-mips@linux-mips.org Subject: Re: [PATCH 02/10] Alchemy: Au1300 new interrupt controller Message-ID: <20090308094912.426c9533@scarran.roarinelk.net> In-Reply-To: <1236453608.9848.16.camel@kh-d820> References: <1236356409-32357-1-git-send-email-khickey@rmicorp.com> <788248524efc28ba2608ed79bfb7080ee476b12d.1236354153.git.khickey@rmicorp.com> <0b447f7e26be90a9179bdf89ca2cfd1f34c5d16e.1236354153.git.khickey@rmicorp.com> <20090307104932.49408650@scarran.roarinelk.net> <1236453608.9848.16.camel@kh-d820> Organization: Private X-Mailer: Claws Mail 3.7.0 (GTK+ 2.14.7; i686-pc-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22038 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mano@roarinelk.homelinux.net Precedence: bulk X-list: linux-mips On Sat, 07 Mar 2009 13:20:08 -0600 Kevin Hickey wrote: > > > +asmlinkage void plat_irq_dispatch(void) > > > +{ > > > + unsigned int intr; > > > + u32 bank; > > > + u32 reg_msk; > > > + unsigned int pending = read_c0_status() & read_c0_cause(); > > > + /* > > > + * C0 timer tick > > > + */ > > > + if (pending & CAUSEF_IP7) > > > + do_IRQ(MIPS_CPU_IRQ_BASE + 7); > > > + else if (pending & (CAUSEF_IP2 | CAUSEF_IP3)) { > > > + intr = au_ioread32(&gpio_int->pri_enc); > > > + bank = GPINT_BANK_FROM_INT(intr); > > > + reg_msk = GPINT_BIT_FROM_INT(bank, intr); > > > + > > > + if (intr != 127) { > > > + if (pending & CAUSEF_IP3) > > > + board_irq_dispatch(intr); > > > > What is this supposed to do? (missed debug code?) > board_irq_dispatch (which as I said above should be in a non-devboard > include) is used to display the IRQ number on the hex LEDs on the DB1300 > board. I tried to keep it generic so that other boards could do what > they want or leave it unimplemented and have it optimized out. The > CAUSEF_IP3 part is there to not display the timer tick (since it pretty > much floods out the other IRQ displays). I should really do that > segregation in the board_irq_dispatch call; I was pretty focused on my > board when I wrote this code. Oh okay. I was wondering about the IP3. We should probably make a list of all (possible) hooks available into the alchemy core code (and give them nice prefixed names ;-) ) > > (FWIW, I'm working on getting rid of the explicit CPU-type config > > options and instead do runtime detection and configuration of > > dma/dbdma/irq/ and so on). > > Why? Won't that just lead to a larger kernel binary since it will have > all of the tables in it? I would prefer to only compile in the data > that I need. Unless I'm missing what you're doing... All Alchemy chips are more or less identical. Some have different sd/ddr controller, some have different dma, and some lack peripherals others do have; most periperhals have identical mmio addresses across chip types. Interestingly even the devboard designers assigned a unique 4bit value to each board type; with a bit of work you could in theory build one kernel binary which runs on all of them. That's what I'm aiming at. Best regards, Manuel Lauss From mano@roarinelk.homelinux.net Sun Mar 8 08:54:21 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 08 Mar 2009 08:54:24 +0000 (GMT) Received: from fnoeppeil36.netpark.at ([217.175.205.164]:64671 "EHLO roarinelk.homelinux.net") by ftp.linux-mips.org with ESMTP id S21102887AbZCHIyV (ORCPT ); Sun, 8 Mar 2009 08:54:21 +0000 Received: (qmail 27732 invoked from network); 8 Mar 2009 09:54:20 +0100 Received: from scarran.roarinelk.net (192.168.0.242) by fnoeppeil36.netpark.at with SMTP; 8 Mar 2009 09:54:20 +0100 Date: Sun, 8 Mar 2009 09:54:20 +0100 From: Manuel Lauss To: Manuel Lauss Cc: Kevin Hickey , ralf@linux-mips.org, linux-mips@linux-mips.org Subject: Re: [PATCH 08/10] Alchemy: DB1300 blink leds on timer tick Message-ID: <20090308095420.220ebd3f@scarran.roarinelk.net> In-Reply-To: <20090308093731.1e7a9067@scarran.roarinelk.net> References: <1236356409-32357-1-git-send-email-khickey@rmicorp.com> <788248524efc28ba2608ed79bfb7080ee476b12d.1236354153.git.khickey@rmicorp.com> <0b447f7e26be90a9179bdf89ca2cfd1f34c5d16e.1236354153.git.khickey@rmicorp.com> <7afc5c84989c4bc0f94181397369f284f2bb6924.1236354153.git.khickey@rmicorp.com> <0946334bbaf9883076889fe060a362b72d31e6f4.1236354153.git.khickey@rmicorp.com> <394c116b9fa5bd1865ac21d11185f09e07bd2ab5.1236354153.git.khickey@rmicorp.com> <7e632686ab9b29a94eefeb2e5dca8b091a956b95.1236354153.git.khickey@rmicorp.com> <20090307103731.4660e57f@scarran.roarinelk.net> <1236452697.9848.1.camel@kh-d820> <20090308093731.1e7a9067@scarran.roarinelk.net> Organization: Private X-Mailer: Claws Mail 3.7.0 (GTK+ 2.14.7; i686-pc-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22039 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mano@roarinelk.homelinux.net Precedence: bulk X-list: linux-mips > board_timer_set callback to blink some leds. (Note, I still don't feel > this is "right", but ultimately it's not up you anyway). should read "but ultimately it's up to you anyway" From nietzsche@lysator.liu.se Sun Mar 8 14:53:55 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 08 Mar 2009 14:53:59 +0000 (GMT) Received: from mail.lysator.liu.se ([130.236.254.3]:7101 "EHLO mail.lysator.liu.se") by ftp.linux-mips.org with ESMTP id S20808646AbZCHOxz (ORCPT ); Sun, 8 Mar 2009 14:53:55 +0000 Received: from mail.lysator.liu.se (localhost [127.0.0.1]) by mail.lysator.liu.se (Postfix) with ESMTP id B701940055; Sun, 8 Mar 2009 15:53:46 +0100 (CET) Received: from [192.168.10.105] (c-30bde555.035-105-73746f38.cust.bredbandsbolaget.se [85.229.189.48]) (using TLSv1 with cipher AES128-SHA (128/128 bits)) (No client certificate requested) by mail.lysator.liu.se (Postfix) with ESMTP id 990244004F; Sun, 8 Mar 2009 15:53:46 +0100 (CET) Cc: linux-mips@linux-mips.org Message-Id: From: Markus Gothe To: Nils Faerber In-Reply-To: <49B1510B.8020606@kernelconcepts.de> Content-Type: multipart/signed; protocol="application/pgp-signature"; micalg=pgp-sha1; boundary="Apple-Mail-3-518791976" Content-Transfer-Encoding: 7bit Mime-Version: 1.0 (Apple Message framework v930.3) Subject: Re: Ingenic JZ4730 - illegal instruction Date: Sun, 8 Mar 2009 15:53:49 +0100 References: <49B1510B.8020606@kernelconcepts.de> X-Pgp-Agent: GPGMail 1.2.0 (v56) X-Mailer: Apple Mail (2.930.3) X-Virus-Scanned: ClamAV using ClamSMTP Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22040 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: nietzsche@lysator.liu.se Precedence: bulk X-list: linux-mips This is an OpenPGP/MIME signed message (RFC 2440 and 3156) --Apple-Mail-3-518791976 Content-Type: text/plain; charset=US-ASCII; format=flowed; delsp=yes Content-Transfer-Encoding: 7bit Well, the Xburst-arch seems to be pretty fucked up beyond all repair. //Markus On 6 Mar 2009, at 17:36, Nils Faerber wrote: > Hello! > I am rather playing than really working on a Ingenic JZ4730 based > device. The JZ4730 is a MIPS32 SOC included in many types of devices, > like media players and thelike but also in small power efficient > subnotebooks (this is the device I am trying to support based on the > Ingebic Linux kernel patch). > > The current kernel patch from Ingenic > > http://www.ingenic.cn/eng/productServ/App/JZ4730/pfCustomPage.aspx > or > ftp://ftp.ingenic.cn/3sw/01linux/02kernel/linux-2.6.24/linux-2.6.24.3-jz-20090218.patch.gz > > for the patch (I used an even older patch to start my board support > but > they basically only added newer CPU types in later patches). > > The support for my board is almost in place but I see from time to > time > failing applications with "illegal instruction" faults. Most shell > applications work pretty fine, especially more complex GUI > applications > seem to fail, like a webbrowser or such. > I also tested this with different GCC and glibc version which makes me > pretty sure that I am seeing a kernel problem here rather than a > userspace problem. > > I am pretty clueless how to debug this. Apropos debig as another hint: > Some application work if I start them in GDB but fail outside. > > Any hint how to start debugging this would be greatly appreciated! > And a > fix would be like a dream ;) > > Many thanks! > > Cheers > nils faerber > > -- > kernel concepts GbR Tel: +49-271-771091-12 > Sieghuetter Hauptweg 48 Fax: +49-271-771091-19 > D-57072 Siegen Mob: +49-176-21024535 > http://www.kernelconcepts.de > --Apple-Mail-3-518791976 content-type: application/pgp-signature; x-mac-type=70674453; name=PGP.sig content-description: This is a digitally signed message part content-disposition: inline; filename=PGP.sig content-transfer-encoding: 7bit -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.8 (Darwin) iEYEARECAAYFAkmz2/0ACgkQ6I0XmJx2NrwsGgCffg2xSRrF2Efmtt53fBsrG51+ NQ4AnjDzkdqiqqL7OwFJUYAMH6We6mOh =z60D -----END PGP SIGNATURE----- --Apple-Mail-3-518791976-- From ard@kwaak.net Sun Mar 8 16:03:39 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 08 Mar 2009 16:03:42 +0000 (GMT) Received: from gw-cistron.kwaak.net ([62.216.22.210]:21176 "EHLO mail.kwaak.net") by ftp.linux-mips.org with ESMTP id S21103620AbZCHQDj (ORCPT ); Sun, 8 Mar 2009 16:03:39 +0000 Received: from shell2.kwaak.net ([2001:7b8:32d::6]:60117) by mail.kwaak.net with esmtp (Exim 4.50) id 1LgLTM-0006gl-GK for linux-mips@linux-mips.org; Sun, 08 Mar 2009 17:03:28 +0100 Received: from ard by shell2.kwaak.net with local (Exim 4.69) (envelope-from ) id 1LgLTM-0005O1-4f for linux-mips@linux-mips.org; Sun, 08 Mar 2009 17:03:28 +0100 Date: Sun, 8 Mar 2009 17:03:28 +0100 From: ard To: linux-mips@linux-mips.org Subject: Re: Ingenic JZ4730 - illegal instruction Message-ID: <20090308160328.GC9943@kwaak.net> References: <49B1510B.8020606@kernelconcepts.de> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.17+20080114 (2008-01-14) X-kwaak-MailScanner: Found to be clean X-kwaak-MailScanner-SpamCheck: not spam, SpamAssassin (score=-5.899, required 5, autolearn=not spam, ALL_TRUSTED -3.30, BAYES_00 -2.60) X-MailScanner-From: ard@kwaak.net Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22041 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ard+lm@kwaak.net Precedence: bulk X-list: linux-mips Hello, On Sun, Mar 08, 2009 at 03:53:49PM +0100, Markus Gothe wrote: > Well, the Xburst-arch seems to be pretty fucked up beyond all repair. Hmmm, that doesn't sound promising. But do you have references for that? Maybe google has some more info than since I first started searching. Anyway: for now it happily runs debian, and for what I can see, the kernel patches have no real changes except for extra drivers and extra board and powermanagement drivers. So if you have hints in which way the xburst deviates from "standard" mips, it could help us a lot. In the mean time I am going to subscribe to the ingenic forum ( http://www.ingenic.cn/eng/forum/vvFrmDefault.aspx ) that contains more characters that I can't read than characters that I can read :-(. Regards, Ard -- .signature not found From Xiaotian.Feng@windriver.com Mon Mar 9 01:42:00 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 09 Mar 2009 01:42:03 +0000 (GMT) Received: from mail.windriver.com ([147.11.1.11]:39113 "EHLO mail.wrs.com") by ftp.linux-mips.org with ESMTP id S20808720AbZCIBmA (ORCPT ); Mon, 9 Mar 2009 01:42:00 +0000 Received: from ALA-MAIL03.corp.ad.wrs.com (ala-mail03 [147.11.57.144]) by mail.wrs.com (8.13.6/8.13.6) with ESMTP id n291fqBR003540; Sun, 8 Mar 2009 18:41:52 -0700 (PDT) Received: from ala-mail06.corp.ad.wrs.com ([147.11.57.147]) by ALA-MAIL03.corp.ad.wrs.com with Microsoft SMTPSVC(6.0.3790.1830); Sun, 8 Mar 2009 18:41:52 -0700 Received: from localhost.localdomain ([128.224.158.187]) by ala-mail06.corp.ad.wrs.com with Microsoft SMTPSVC(6.0.3790.1830); Sun, 8 Mar 2009 18:41:51 -0700 From: Xiaotian Feng To: ralf@linux-mips.org, linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Subject: [PATCH V1] mips: fix mips syscall wrapper sys_32_ipc bug Date: Mon, 9 Mar 2009 09:45:12 +0800 Message-Id: <1236563112-24287-1-git-send-email-Xiaotian.Feng@windriver.com> X-Mailer: git-send-email 1.5.5.1 X-OriginalArrivalTime: 09 Mar 2009 01:41:51.0997 (UTC) FILETIME=[385D3AD0:01C9A058] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22042 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: Xiaotian.Feng@windriver.com Precedence: bulk X-list: linux-mips There's a typo in mips syscall wrapper sys_32_ipc. If CONFIG_SYSVIPC is not set, it will cause mips linux compile error. Signed-off-by: Xiaotian Feng --- arch/mips/kernel/linux32.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/mips/kernel/linux32.c b/arch/mips/kernel/linux32.c index 2f8452b..1a86f84 100644 --- a/arch/mips/kernel/linux32.c +++ b/arch/mips/kernel/linux32.c @@ -235,7 +235,7 @@ SYSCALL_DEFINE6(32_ipc, u32, call, long, first, long, second, long, third, #else SYSCALL_DEFINE6(32_ipc, u32, call, int, first, int, second, int, third, - u32, ptr, u32 fifth) + u32, ptr, u32, fifth) { return -ENOSYS; } -- 1.5.5.1 From kevink@paralogos.com Mon Mar 9 08:39:29 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 09 Mar 2009 08:39:34 +0000 (GMT) Received: from aux-209-217-49-36.oklahoma.net ([209.217.49.36]:23814 "EHLO proteus.paralogos.com") by ftp.linux-mips.org with ESMTP id S20808106AbZCIIj3 (ORCPT ); Mon, 9 Mar 2009 08:39:29 +0000 Received: from [192.168.236.58] ([217.109.65.213]) by proteus.paralogos.com (8.9.3/8.9.3) with ESMTP id IAA31811; Sun, 8 Mar 2009 08:17:21 -0600 Message-ID: <49B4D5BC.5020203@paralogos.com> Date: Mon, 09 Mar 2009 03:39:24 -0500 From: "Kevin D. Kissell" User-Agent: Thunderbird 2.0.0.19 (Windows/20081209) MIME-Version: 1.0 To: Nils Faerber CC: linux-mips@linux-mips.org Subject: Re: Ingenic JZ4730 - illegal instruction References: <49B1510B.8020606@kernelconcepts.de> In-Reply-To: <49B1510B.8020606@kernelconcepts.de> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22043 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: kevink@paralogos.com Precedence: bulk X-list: linux-mips The only thing that you've mentioned below that really makes me think that you're looking at a kernel bug is the comment about things not failing under GDB. But if *any* of the programs that are failing fail under gdb, I'd want to know just what instruction is at the place where they're taking a SIGILL. If gdb heisenbergs things too much, then the basic brute force thing to do would be to instrument the kernel itself to report on what happened, and what it sees at the "bad instruction" address, using printk. If the memory value actually looks like a legit instruction, it would confirm the hypothesis that you've got an icache maintenance problem. I note that the Ingenic patch has a "flushcaches" routine that has hardwired assumptions about the cache organization. Could those be incorrect on the chip you're using? Regards, and happy hunting, Kevin K. Nils Faerber wrote: > Hello! > I am rather playing than really working on a Ingenic JZ4730 based > device. The JZ4730 is a MIPS32 SOC included in many types of devices, > like media players and thelike but also in small power efficient > subnotebooks (this is the device I am trying to support based on the > Ingebic Linux kernel patch). > > The current kernel patch from Ingenic > > http://www.ingenic.cn/eng/productServ/App/JZ4730/pfCustomPage.aspx > or > ftp://ftp.ingenic.cn/3sw/01linux/02kernel/linux-2.6.24/linux-2.6.24.3-jz-20090218.patch.gz > > for the patch (I used an even older patch to start my board support but > they basically only added newer CPU types in later patches). > > The support for my board is almost in place but I see from time to time > failing applications with "illegal instruction" faults. Most shell > applications work pretty fine, especially more complex GUI applications > seem to fail, like a webbrowser or such. > I also tested this with different GCC and glibc version which makes me > pretty sure that I am seeing a kernel problem here rather than a > userspace problem. > > I am pretty clueless how to debug this. Apropos debig as another hint: > Some application work if I start them in GDB but fail outside. > > Any hint how to start debugging this would be greatly appreciated! And a > fix would be like a dream ;) > > Many thanks! > > Cheers > nils faerber > > From arthur.webkid@gmail.com Mon Mar 9 08:43:16 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 09 Mar 2009 08:43:20 +0000 (GMT) Received: from wf-out-1314.google.com ([209.85.200.168]:59343 "EHLO wf-out-1314.google.com") by ftp.linux-mips.org with ESMTP id S20808938AbZCIInQ (ORCPT ); Mon, 9 Mar 2009 08:43:16 +0000 Received: by wf-out-1314.google.com with SMTP id 25so1872562wfc.21 for ; Mon, 09 Mar 2009 01:43:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:in-reply-to:references :date:message-id:subject:from:to:cc:content-type; bh=JhXvzy/T3mprdjjxu/gsoG3hADereAPslUNIibhga/Y=; b=v/DPsZqY3syaGv2aUhW/cmP3SLruLZGZIBm9xH8HwkCXglYrTXOf4AIXRW032FsiiD Afgtzfs9GR6wIdo+gkz0ZcF7dWj8uKNKWlmYZQUHi+fClKMOjFxJ27lcKr/5iSVQCeE5 UQji+GjLE7PsiFmds2Exz5nrdUEJhuAtQmFjU= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type; b=h51o928/9B6RPpAI0QsL2ulJFzw+Czy4f+CDx5F2b5sf3DIBiGDjLRwRfTCzvz4Vds Tzxx6SGx2PY9G/JM8sJFAhL3sWR1HF/otILYjpz0JjCbCNYC/Bvkt45Hd00gXpR73QcS AYvuJFDhQ7VVI31n6Ug92m/q3hBt3dyxDbk8s= MIME-Version: 1.0 Received: by 10.143.18.21 with SMTP id v21mr2446745wfi.149.1236588194401; Mon, 09 Mar 2009 01:43:14 -0700 (PDT) In-Reply-To: <1236282218.49b02b6a6c724@imp.free.fr> References: <1236282218.49b02b6a6c724@imp.free.fr> Date: Mon, 9 Mar 2009 16:43:14 +0800 Message-ID: <5a350f0f0903090143l432f80f4i9663637153b12f87@mail.gmail.com> Subject: Re: gns mips-l: what next? From: Arthur WebKid To: s.boutayeb@free.fr Cc: gnewsense-dev@nongnu.org, dclark@gnu.org, rms@gnu.org, debian-mips@lists.debian.org, linux-mips@linux-mips.org Content-Type: multipart/alternative; boundary=0016368e21900f8ea50464aba009 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22044 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: arthur.webkid@gmail.com Precedence: bulk X-list: linux-mips --0016368e21900f8ea50464aba009 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Hi It is really a good news for free software/hardware advocates! What is in my mind is promotion of the concept of free software + hardware, with Lemote mini-box and laptops in the Internet, (maybe at FSF recommended hardware?). The more people using Lemote hardware, the more chance they understand their need of freedom, the more they choose gNewSense, the more hackers / developers/ resources we (the gNewSense team) can get. Cheers!! -- Arthur Webkid 2009/3/6 > Hi, > > The "gNewSense mips-l" project ( > http://wiki.gnewsense.org/Projects/GNewSenseToMIPS ) is on a good way, > thanks to > the support of the gNewSense team, of the FSF, of Lemote Tech, and of > various > contributors around the world. > > So far, we have a gNewSense-compliant Debian installer allowing the > execution of > netboot installation procedure from an usb stick and fine-tuned for the > lemote > hardware. The installation and the upgrade uses the archive set by the FSF > at > http://archive.gnewsense.org/gnewsense-mipsel-l/. > > The Lemote hardware ("yeeloong 8089" laptop and "Fuloong 6003" mini box) > boot > from the bsd licensed PMON200 boot loader. > > The netboot install procedure has be proven successful on the "Yeeloong > 8089" > laptop and remains to be tested on the "Fuloong 6003" mini box. We have now > a > nice full-free laptop with beautiful arts designed by the > gNewSense-arts-team, a > working gnome desktop environment. Many things need to be polished: for > example > the apm (the battery of the laptops show a 0% gauge), the webcam is not yet > working), but we have full networking capabilities (both wired and > wireless), a > functional xorg server (thanks to the siliconmotion driver from lemote's > dev), > etc. > > In the same time, Lemote Tech's team has setup a netboot installation > procedure > http://dev.lemote.com/drupal/node/58 and has provided valuable advice, > hardware > resources, code, etc. to the gNewSenseToMips project. This was a big help > for us > all. > > Now, how could we move forward? Maybe: > - improving > - testing > - documenting > - upgrading > - promoting > - upstreaming > - etc. > > That is, many things, but not too much, considering the realistic > perspective > that more talents decide to contribute to the gNewSense project. You are > wellcome! > > Thank you for your comments and for your support! > > Cheers > > Samy > > > -- > To UNSUBSCRIBE, email to debian-mips-REQUEST@lists.debian.org > with a subject of "unsubscribe". Trouble? Contact > listmaster@lists.debian.org > > --0016368e21900f8ea50464aba009 Content-Type: text/html; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable
Hi
=A0
It is really a good news for free software/hardware advocates!
=A0
What is in my mind is promotion of the concept of free software + hard= ware, with Lemote mini-box and laptops in the Internet, (maybe at FSF recom= mended hardware?).
=A0
The more people using Lemote hardware, the more chance they understand= their need of freedom, the more they choose gNewSense, the more hackers / = developers/ resources we (the gNewSense team) can get.
=A0
Cheers!!
=A0
--
Arthur Webkid

2009/3/6 <s.boutayeb@free.fr>
Hi,

The "gNewSense m= ips-l" project (
http://wiki.gnewsense.org/Projects/GNewSense= ToMIPS ) is on a good way, thanks to
the support of the gNewSense team, of the FSF, of Lemote Tech, and of vario= us
contributors around the world.

So far, we have a gNewSense-com= pliant Debian installer allowing the execution of
netboot installation p= rocedure from an usb stick and fine-tuned for the lemote
hardware. The installation and the upgrade uses the archive set by the FSF = at
http://archive.gnewsense.org/gnewsense-mipsel-l/.

Th= e Lemote hardware ("yeeloong 8089" laptop and "Fuloong 6003&= quot; mini box) boot
from the bsd licensed PMON200 boot loader.

The netboot install proce= dure has be proven successful on the "Yeeloong 8089"
laptop an= d remains to be tested on the "Fuloong 6003" mini box. We have no= w a
nice full-free laptop with beautiful arts designed by the gNewSense-arts-te= am, a
working gnome desktop environment. Many things need to be polished= : for example
the apm (the battery of the laptops show a 0% gauge), the = webcam is not yet
working), but we have full networking capabilities (both wired and wireless= ), a
functional xorg server (thanks to the siliconmotion driver from lem= ote's dev),
etc.

In the same time, Lemote Tech's team has= setup a netboot installation procedure
http://d= ev.lemote.com/drupal/node/58 and has provided valuable advice, hardware=
resources, code, etc. to the gNewSenseToMips project. This was a big he= lp for us
all.

Now, how could we move forward? Maybe:
- improving
- test= ing
- documenting
- upgrading
- promoting
- upstreaming
- et= c.

That is, many things, but not too much, considering the realistic= perspective
that more talents decide to contribute to the gNewSense project. You arewellcome!

Thank you for your comments and for your support!

= Cheers

Samy


--
To UNSUBSCRIBE,= email to debian-mi= ps-REQUEST@lists.debian.org
with a subject of "unsubscribe". Trouble? Contact listmaster@lists.debian.org


--0016368e21900f8ea50464aba009-- From nils.faerber@kernelconcepts.de Mon Mar 9 10:00:29 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 09 Mar 2009 10:00:32 +0000 (GMT) Received: from mail.kernelconcepts.de ([212.60.202.196]:37312 "EHLO mail.kernelconcepts.de") by ftp.linux-mips.org with ESMTP id S21102833AbZCIKA3 (ORCPT ); Mon, 9 Mar 2009 10:00:29 +0000 Received: from [192.168.2.28] by mail.kernelconcepts.de with esmtpsa (TLS-1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.63) (envelope-from ) id 1LgcXH-0000cr-GH; Mon, 09 Mar 2009 11:16:39 +0100 Message-ID: <49B4E8BB.8080704@kernelconcepts.de> Date: Mon, 09 Mar 2009 11:00:27 +0100 From: Nils Faerber Organization: kernel concepts GbR User-Agent: Thunderbird 2.0.0.19 (X11/20090105) MIME-Version: 1.0 To: "Kevin D. Kissell" CC: linux-mips@linux-mips.org Subject: Re: Ingenic JZ4730 - illegal instruction References: <49B1510B.8020606@kernelconcepts.de> <49B4D5BC.5020203@paralogos.com> In-Reply-To: <49B4D5BC.5020203@paralogos.com> X-Enigmail-Version: 0.95.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22045 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: nils.faerber@kernelconcepts.de Precedence: bulk X-list: linux-mips Hi Kevin! Kevin D. Kissell schrieb: > The only thing that you've mentioned below that really makes me think > that you're looking at a kernel bug is the comment about things not > failing under GDB. But if *any* of the programs that are failing fail > under gdb, I'd want to know just what instruction is at the place where > they're taking a SIGILL. If gdb heisenbergs things too much, then the > basic brute force thing to do would be to instrument the kernel itself > to report on what happened, and what it sees at the "bad instruction" > address, using printk. If the memory value actually looks like a legit > instruction, it would confirm the hypothesis that you've got an icache > maintenance problem. I note that the Ingenic patch has a "flushcaches" > routine that has hardwired assumptions about the cache organization. > Could those be incorrect on the chip you're using? Thanks for having a thought about the issue! By now I pitily have to admit that my GDB assumption was not all that correct :( After *a*lot* more tries I found an application that actually also fails inside GDB. But with some more tries I can now confirm that applications fail at random points - it is not a single instruction that causes the fault but rather random points. So I think your memory/cache issue theory sounds pretty interesting... I just had a look at the JZ4730 code (in arch/mips/jz4730/) and the only mention of a cache flush is in pm.c which will only be executed in case of going to sleep (i.e. CPU deep sleep aka s2ram). arch/mips/mm/c-r4k.c also contains a JZ_RISC section for setting up cache options and arch/mips/mm/tlbex.c a TLB case special for the JZ. Those look promising! I could very well think of cases where a wrong cache flush could cause such or similar problems. > Regards, and happy hunting, Happy? When I found it maybe. The annoying thing about this is that Ingenic is not very helpful. I emailed them several times already asking for the full datasheet of the CPU with no replay at all yet. The datasheet they hae on their webpage is just the brief with about 60 pages and not very helpful when you ar elooking for details like cache handling etc. So I will have to resort to experiments - trial an error. Thank you very much for your thoughts and idea! > Kevin K. Cheers nils faerber -- kernel concepts GbR Tel: +49-271-771091-12 Sieghuetter Hauptweg 48 Fax: +49-271-771091-19 D-57072 Siegen Mob: +49-176-21024535 http://www.kernelconcepts.de From ralf@h5.dl5rb.org.uk Mon Mar 9 13:40:07 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 09 Mar 2009 13:40:11 +0000 (GMT) Received: from localhost.localdomain ([127.0.0.1]:2710 "EHLO h5.dl5rb.org.uk") by ftp.linux-mips.org with ESMTP id S21366941AbZCINkH (ORCPT ); Mon, 9 Mar 2009 13:40:07 +0000 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id n29De5xV022470; Mon, 9 Mar 2009 14:40:05 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id n29De4a1022468; Mon, 9 Mar 2009 14:40:04 +0100 Date: Mon, 9 Mar 2009 14:40:03 +0100 From: Ralf Baechle To: Kevin Hickey Cc: linux-mips@linux-mips.org Subject: Re: [PATCH 01/10] Initial Au1300 and DBAu1300 support Message-ID: <20090309134003.GE6492@linux-mips.org> References: <1236356409-32357-1-git-send-email-khickey@rmicorp.com> <788248524efc28ba2608ed79bfb7080ee476b12d.1236354153.git.khickey@rmicorp.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <788248524efc28ba2608ed79bfb7080ee476b12d.1236354153.git.khickey@rmicorp.com> User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22046 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Fri, Mar 06, 2009 at 10:20:00AM -0600, Kevin Hickey wrote: > @@ -135,3 +147,9 @@ config SOC_AU1X00 > select SYS_SUPPORTS_32BIT_KERNEL > select SYS_SUPPORTS_APM_EMULATION > select GENERIC_HARDIRQS_NO__DO_IRQ > + > +config AU_INT_CNTLR > + bool > + > +config AU_GPIO_INT_CNTLR > + bool These two definitions should be in patch 2/10 with the code that uses it. > diff --git a/arch/mips/alchemy/common/platform.c b/arch/mips/alchemy/common/platform.c > index 5c76c64..fd096d1 100644 > --- a/arch/mips/alchemy/common/platform.c > +++ b/arch/mips/alchemy/common/platform.c > @@ -65,6 +65,7 @@ static struct platform_device au1xx0_uart_device = { > }, > }; > > +#ifndef CONFIG_SOC_AU13XX > /* OHCI (USB full speed host controller) */ > static struct resource au1xxx_usb_ohci_resources[] = { > [0] = { > @@ -92,6 +93,7 @@ static struct platform_device au1xxx_usb_ohci_device = { > .num_resources = ARRAY_SIZE(au1xxx_usb_ohci_resources), > .resource = au1xxx_usb_ohci_resources, > }; > +#endif Try to avoid this kind of #ifdef. It'll only get more ugly in the future when there are more members of the SOC family that don't have the USB. > +#if 0 > +void __init prom_init(void) > +{ > + unsigned char *memsize_str; > + unsigned long memsize; > + > + prom_argc = (int)fw_arg0; > + prom_argv = (char **)fw_arg1; > + prom_envp = (char **)fw_arg2; > + > + prom_init_cmdline(); > + memsize_str = prom_getenv("memsize"); > + /* KH: TODO - Change back to 128 MB when the second DDR channel is working. */ > + if (!memsize_str) > + memsize = 0x04000000; > + else > + strict_strtol(memsize_str, 0, &memsize); > + add_memory_region(0, memsize, BOOT_MEM_RAM); > +} > +#endif #if 0, so delete? > --- a/arch/mips/include/asm/mach-au1x00/au1000.h > +++ b/arch/mips/include/asm/mach-au1x00/au1000.h > +void static inline au_iowrite32(u32 val, volatile u32 *reg) > +{ > + *reg = val; > +} > + > +static inline u32 au_ioread32(volatile u32 *reg) > +{ > + return *reg; > +} > + > +#define AU_SET_BITS_16(mask, reg) \ > +do { \ > + au_iowrite16((au_ioread16(reg) | mask ), reg); \ > +} while(0) Macros should be bullet proof against side effects: #define au_set_bits_16(mask, reg) \ do { \ volatile u16 *__r = (reg); \ \ au_iowrite16((au_ioread16(__r) | (mask)), __r); \ } while(0) Or simply use an inline function instead. > +#define AU_CLEAR_BITS_16(mask, reg) \ > +do { \ > + au_iowrite16((au_ioread16(reg) & ~mask ), reg); \ > +} while(0) > + > +#define AU_SET_BITS_32(mask, reg) \ > +do { \ > + au_iowrite32((au_ioread32(reg) | mask), reg); \ > +} while(0) > + > +#define AU_CLEAR_BITS_32(mask, reg) \ > +do { \ > + au_iowrite32((au_ioread32(reg) & ~mask), reg); \ > +} while(0) > + > /* arch/mips/au1000/common/clocks.c */ > extern void set_au1x00_speed(unsigned int new_freq); > extern unsigned int get_au1x00_speed(void); > --- /dev/null > +++ b/arch/mips/include/asm/mach-au1x00/au13xx.h > @@ -0,0 +1,207 @@ > +#ifdef CONFIG_SOC_AU13XX > + > +#define NR_INTS 255 Unused macro - did you mean NR_IRQS? Also keep the value of NR_IRQS a multiple of BITS_PER_LONG or unpleasant things might happen. > +#define UART0_ADDR 0xB0100000 > +#define UART1_ADDR 0xB0101000 > +#define UART2_ADDR 0xB0102000 > +#define UART3_ADDR 0xB0103000 > + > +#define KSEG1_OFFSET 0xA0000000 This constant duplicates KSEG1 defined in . > +#define GPIO_INT_CTRLR_BASE 0x10200000 > +/* > + * Linux uses IRQ 0-7 for the 8 causes. That means that all of our channel > + * bits need to be offset by 8 either when passed to do_IRQ or when received > + * through the irq_chip calls > + * > + * KH: TODO - This is duplicated from gpio_int.h Is that the right thing to do? > + */ > +#define GPINT_LINUX_IRQ_OFFSET 8 > + > +#define AU1300_IRQ_UART1 17 > +#define AU1300_IRQ_UART2 25 > +#define AU1300_IRQ_UART3 27 > +#define AU1300_IRQ_SD1 32 > +#define AU1300_IRQ_SD2 38 > +#define AU1300_IRQ_PSC0 48 > +#define AU1300_IRQ_PSC1 52 > +#define AU1300_IRQ_PSC2 56 > +#define AU1300_IRQ_PSC3 60 > +#define AU1300_IRQ_NAND 62 > +#define AU1300_IRQ_DDMA 75 > +#define AU1300_IRQ_GPU 78 > +#define AU1300_IRQ_MPU 77 > +#define AU1300_IRQ_MMU 76 > +#define AU1300_IRQ_UDMA 79 > +#define AU1300_IRQ_TOY_TICK 80 > +#define AU1300_IRQ_TOYMATCH_0 81 > +#define AU1300_IRQ_TOYMATCH_1 82 > +#define AU1300_IRQ_TOYMATCH_2 83 > +#define AU1300_IRQ_RTC_TICK 84 > +#define AU1300_IRQ_RTCMATCH_0 85 > +#define AU1300_IRQ_RTCMATCH_1 86 > +#define AU1300_IRQ_RTCMATCH_2 87 > +#define AU1300_IRQ_UART0 88 > +#define AU1300_IRQ_SD0 89 > +#define AU1300_IRQ_USB 90 > +#define AU1300_IRQ_LCD 91 > +#define AU1300_IRQ_BSA 94 > +#define AU1300_IRQ_MPE 93 > +#define AU1300_IRQ_ITE 92 > +#define AU1300_IRQ_AES 95 > +#define AU1300_IRQ_CIM 96 > + > +#define LCD_PHYS_ADDR 0x15000000 > + > +#define AU1200_LCD_INT (GPINT_LINUX_IRQ_OFFSET + AU1300_IRQ_LCD) > +#define AU1000_RTC_MATCH2_INT (GPINT_LINUX_IRQ_OFFSET + AU1300_IRQ_RTCMATCH_2) > + > +#define SD0_PHYS_ADDR 0x10600000 > +#define SD1_PHYS_ADDR 0x10601000 > + > + > +#define USB_BASE_PHYS_ADDR 0x14021000 > +#define USB_EHCI_BASE 0x14020000 > +#define USB_EHCI_LEN 0x400 > +#define USB_OHCI_BASE 0x14020800 > +#define USB_OHCI_LEN 0x400 > +#define USB_UOC_BASE 0x14022000 > +#define USB_UOC_LEN 0x20 > +#define USB_UDC_BASE 0x14022000 > +#define USB_UDC_LEN 0x2000 > + > +#if !defined(ASSEMBLER) There is no ASSEMBLER macro defined by cpp. Within the kernel please use #ifndef __ASSEMBLY__ instead. However this bug suggests you don't use this header in assembly code at all so maybe the whole ifdef should go? > +typedef volatile struct See Documentation/volatile-considered-harmful.txt ... > +{ > + // setup registers Please use /* ... */ only within the kernel. You did run your patches through scripts/checkpatch.pl, no? > + u32 dwc_ctrl1; //0x0000 See Documentation/volatile-considered-harmful.txt ... Ralf From kevink@paralogos.com Mon Mar 9 14:12:08 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 09 Mar 2009 14:12:10 +0000 (GMT) Received: from aux-209-217-49-36.oklahoma.net ([209.217.49.36]:4359 "EHLO proteus.paralogos.com") by ftp.linux-mips.org with ESMTP id S21367011AbZCIOMI (ORCPT ); Mon, 9 Mar 2009 14:12:08 +0000 Received: from [127.0.0.1] ([217.109.65.213]) by proteus.paralogos.com (8.9.3/8.9.3) with ESMTP id NAA12849; Sun, 8 Mar 2009 13:49:56 -0600 Message-ID: <49B523B6.6090006@paralogos.com> Date: Mon, 09 Mar 2009 15:12:06 +0100 From: "Kevin D. Kissell" User-Agent: Thunderbird 2.0.0.19 (Windows/20081209) MIME-Version: 1.0 To: Nils Faerber CC: linux-mips@linux-mips.org Subject: Re: Ingenic JZ4730 - illegal instruction References: <49B1510B.8020606@kernelconcepts.de> <49B4D5BC.5020203@paralogos.com> <49B4E8BB.8080704@kernelconcepts.de> In-Reply-To: <49B4E8BB.8080704@kernelconcepts.de> X-Enigmail-Version: 0.95.7 Content-Type: multipart/alternative; boundary="------------070104040208070002010004" Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22047 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: kevink@paralogos.com Precedence: bulk X-list: linux-mips This is a multi-part message in MIME format. --------------070104040208070002010004 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit I don't have time to go chasing this stuff any further on your behalf, but it *does* smell to me like an icache management problem. Remember, MIPS processors almost universally have split I/D caches and no coherence support between them, so if you either (a) forget to do an explicit D-cache write-back operation after copying to a page mapped write-back that's going to be used as instructions/text, or (b) forget to do an explicit I-cache invalidate when you re-use a page for instructions that has been previously used for a different instruction page, you will have problems, even without going into DMA I/O coherence issues. If your problem were (b), though, you'd be seeing bad answers, segmentation violations, bus errors, etc., at least as often as you'd be seeing illegal instruction exceptions. So my money would be on (a). The need for cache management is so fundamental to Linux for MIPS that all the necessary general hooks have been there for years. If I were you, I'd focus on the definitions of the primitives that you spotted in c-r4k.c. Does the stuff in the JZ_RISC section correspond to the assembly language flush sequence done in the Ingenic patch to head.S? Are you sure that the JZ_RISC section is in fact the version of those functions that's being built into your kernel? Regards, Kevin K. Nils Faerber wrote: > Hi Kevin! > > Kevin D. Kissell schrieb: > >> The only thing that you've mentioned below that really makes me think >> that you're looking at a kernel bug is the comment about things not >> failing under GDB. But if *any* of the programs that are failing fail >> under gdb, I'd want to know just what instruction is at the place where >> they're taking a SIGILL. If gdb heisenbergs things too much, then the >> basic brute force thing to do would be to instrument the kernel itself >> to report on what happened, and what it sees at the "bad instruction" >> address, using printk. If the memory value actually looks like a legit >> instruction, it would confirm the hypothesis that you've got an icache >> maintenance problem. I note that the Ingenic patch has a "flushcaches" >> routine that has hardwired assumptions about the cache organization. >> Could those be incorrect on the chip you're using? >> > > Thanks for having a thought about the issue! > > By now I pitily have to admit that my GDB assumption was not all that > correct :( After *a*lot* more tries I found an application that actually > also fails inside GDB. But with some more tries I can now confirm that > applications fail at random points - it is not a single instruction that > causes the fault but rather random points. > So I think your memory/cache issue theory sounds pretty interesting... > I just had a look at the JZ4730 code (in arch/mips/jz4730/) and the only > mention of a cache flush is in pm.c which will only be executed in case > of going to sleep (i.e. CPU deep sleep aka s2ram). > arch/mips/mm/c-r4k.c also contains a JZ_RISC section for setting up > cache options and arch/mips/mm/tlbex.c a TLB case special for the JZ. > > Those look promising! > I could very well think of cases where a wrong cache flush could cause > such or similar problems. > > >> Regards, and happy hunting, >> > > Happy? When I found it maybe. The annoying thing about this is that > Ingenic is not very helpful. I emailed them several times already asking > for the full datasheet of the CPU with no replay at all yet. The > datasheet they hae on their webpage is just the brief with about 60 > pages and not very helpful when you ar elooking for details like cache > handling etc. > > So I will have to resort to experiments - trial an error. > > Thank you very much for your thoughts and idea! > > >> Kevin K. >> > Cheers > nils faerber > > --------------070104040208070002010004 Content-Type: text/html; charset=UTF-8 Content-Transfer-Encoding: 8bit I don't have time to go chasing this stuff any further on your behalf, but it *does* smell to me like an icache management problem.  Remember, MIPS processors almost universally have split I/D caches and no coherence support between them, so if you either (a) forget to do an explicit D-cache write-back operation after copying to a page mapped write-back that's going to be used as instructions/text, or (b) forget to do an explicit I-cache invalidate when you re-use a page for instructions that has been previously used for a different instruction page, you will have problems, even without going into DMA I/O coherence issues.  If your problem were (b), though, you'd be seeing bad answers, segmentation violations, bus errors, etc., at least as often as you'd be seeing illegal instruction exceptions.  So my money would be on (a).

The need for cache management is so fundamental to Linux for MIPS that all the necessary general hooks have been there for years.  If I were you, I'd focus on the definitions of the primitives that you spotted in c-r4k.c.  Does the stuff in the JZ_RISC section correspond to the assembly language flush sequence done in the Ingenic patch to head.S?  Are you sure that the JZ_RISC section is in fact the version of those functions that's being built into your kernel?

          Regards,

          Kevin K.

Nils Faerber wrote: 
Hi Kevin!

Kevin D. Kissell schrieb:
  
The only thing that you've mentioned below that really makes me think
that you're looking at a kernel bug is the comment about things not
failing under GDB.  But if *any* of the programs that are failing fail
under gdb, I'd want to know just what instruction is at the place where
they're taking a SIGILL. If gdb heisenbergs things too much, then the
basic brute force thing to do would be to instrument the kernel itself
to report on what happened, and what it sees at the "bad instruction"
address, using printk.  If the memory value actually looks like a legit
instruction, it would confirm the hypothesis that you've got an icache
maintenance problem.  I note that the Ingenic patch has a "flushcaches"
routine that has hardwired assumptions about the cache organization. 
Could those be incorrect on the chip you're using?
    

Thanks for having a thought about the issue!

By now I pitily have to admit that my GDB assumption was not all that
correct :( After *a*lot* more tries I found an application that actually
also fails inside GDB. But with some more tries I can now confirm that
applications fail at random points - it is not a single instruction that
causes the fault but rather random points.
So I think your memory/cache issue theory sounds pretty interesting...
I just had a look at the JZ4730 code (in arch/mips/jz4730/) and the only
 mention of a cache flush is in pm.c which will only be executed in case
of going to sleep (i.e. CPU deep sleep aka s2ram).
arch/mips/mm/c-r4k.c also contains a JZ_RISC section for setting up
cache options and arch/mips/mm/tlbex.c a TLB case special for the JZ.

Those look promising!
I could very well think of cases where a wrong cache flush could cause
such or similar problems.

  
         Regards, and happy hunting,
    

Happy? When I found it maybe. The annoying thing about this is that
Ingenic is not very helpful. I emailed them several times already asking
for the full datasheet of the CPU with no replay at all yet. The
datasheet they hae on their webpage is just the brief with about 60
pages and not very helpful when you ar elooking for details like cache
handling etc.

So I will have to resort to experiments - trial an error.

Thank you very much for your thoughts and idea!

  
         Kevin K.
    
Cheers
  nils faerber
--------------070104040208070002010004-- From nils.faerber@kernelconcepts.de Mon Mar 9 15:05:26 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 09 Mar 2009 15:05:28 +0000 (GMT) Received: from mail.kernelconcepts.de ([212.60.202.196]:10919 "EHLO mail.kernelconcepts.de") by ftp.linux-mips.org with ESMTP id S21367118AbZCIPFW (ORCPT ); Mon, 9 Mar 2009 15:05:22 +0000 Received: from [192.168.2.28] by mail.kernelconcepts.de with esmtpsa (TLS-1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.63) (envelope-from ) id 1LghIK-00043g-Mr; Mon, 09 Mar 2009 16:21:32 +0100 Message-ID: <49B5302F.4070301@kernelconcepts.de> Date: Mon, 09 Mar 2009 16:05:19 +0100 From: Nils Faerber Organization: kernel concepts GbR User-Agent: Thunderbird 2.0.0.19 (X11/20090105) MIME-Version: 1.0 To: "Kevin D. Kissell" CC: linux-mips@linux-mips.org Subject: Re: Ingenic JZ4730 - illegal instruction References: <49B1510B.8020606@kernelconcepts.de> <49B4D5BC.5020203@paralogos.com> <49B4E8BB.8080704@kernelconcepts.de> <49B523B6.6090006@paralogos.com> In-Reply-To: <49B523B6.6090006@paralogos.com> X-Enigmail-Version: 0.95.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22048 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: nils.faerber@kernelconcepts.de Precedence: bulk X-list: linux-mips Kevin D. Kissell schrieb: > I don't have time to go chasing this stuff any further on your behalf, I do not expect that either ;) I am already quite happy that you shared your experience with me - it already helped me a lot to fid some points in the code that could be the culprit and I can dig further from here. > but it *does* smell to me like an icache management problem. Remember, > MIPS processors almost universally have split I/D caches and no > coherence support between them, so if you either (a) forget to do an > explicit D-cache write-back operation after copying to a page mapped > write-back that's going to be used as instructions/text, or (b) forget > to do an explicit I-cache invalidate when you re-use a page for > instructions that has been previously used for a different instruction > page, you will have problems, even without going into DMA I/O coherence > issues. If your problem were (b), though, you'd be seeing bad answers, > segmentation violations, bus errors, etc., at least as often as you'd be > seeing illegal instruction exceptions. So my money would be on (a). Yes, it is only illegal instructions, no other faults. > The need for cache management is so fundamental to Linux for MIPS that > all the necessary general hooks have been there for years. If I were > you, I'd focus on the definitions of the primitives that you spotted in > c-r4k.c. Does the stuff in the JZ_RISC section correspond to the OK. > assembly language flush sequence done in the Ingenic patch to head.S? > Are you sure that the JZ_RISC section is in fact the version of those > functions that's being built into your kernel? Well, there is CONFIG_JZRISC=y in the kernel .config and a switch(current_cpu_type) { case CPU_JZRISC: ...} so I would assume it is being used. But I will verify that the CONFIG_JZRISC=y is correctly translated into a current_cpu_type. Oh, one last question, in order to rule out the cache as bug-spot would the kernel option "run uncached" "solve" the issue (and be darn slow)? > Regards, > Kevin K. Thanks a lot so far! It helped me a great deal to start to understand what is going on here... Cheers nils faerber -- kernel concepts GbR Tel: +49-271-771091-12 Sieghuetter Hauptweg 48 Fax: +49-271-771091-19 D-57072 Siegen Mob: +49-176-21024535 http://www.kernelconcepts.de From kevink@paralogos.com Mon Mar 9 15:45:22 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 09 Mar 2009 15:45:24 +0000 (GMT) Received: from aux-209-217-49-36.oklahoma.net ([209.217.49.36]:19719 "EHLO proteus.paralogos.com") by ftp.linux-mips.org with ESMTP id S21367121AbZCIPpT (ORCPT ); Mon, 9 Mar 2009 15:45:19 +0000 Received: from [192.168.236.58] ([217.109.65.213]) by proteus.paralogos.com (8.9.3/8.9.3) with ESMTP id PAA16671; Sun, 8 Mar 2009 15:23:08 -0600 Message-ID: <49B53987.8020206@paralogos.com> Date: Mon, 09 Mar 2009 10:45:11 -0500 From: "Kevin D. Kissell" User-Agent: Thunderbird 2.0.0.19 (Windows/20081209) MIME-Version: 1.0 To: Nils Faerber CC: linux-mips@linux-mips.org Subject: Re: Ingenic JZ4730 - illegal instruction References: <49B1510B.8020606@kernelconcepts.de> <49B4D5BC.5020203@paralogos.com> <49B4E8BB.8080704@kernelconcepts.de> <49B523B6.6090006@paralogos.com> <49B5302F.4070301@kernelconcepts.de> In-Reply-To: <49B5302F.4070301@kernelconcepts.de> Content-Type: multipart/alternative; boundary="------------050905060109090504070609" Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22049 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: kevink@paralogos.com Precedence: bulk X-list: linux-mips This is a multi-part message in MIME format. --------------050905060109090504070609 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Nils Faerber wrote: > Kevin D. Kissell schrieb: > >> Are you sure that the JZ_RISC section is in fact the version of those >> functions that's being built into your kernel? >> > > Well, there is CONFIG_JZRISC=y in the kernel .config and a > switch(current_cpu_type) { case CPU_JZRISC: ...} so I would assume it is > being used. But I will verify that the CONFIG_JZRISC=y is correctly > translated into a current_cpu_type. > Your assumption is reasonable. But given that things aren't working, yes, it's good to verify. > Oh, one last question, in order to rule out the cache as bug-spot would > the kernel option "run uncached" "solve" the issue (and be darn slow)? > It would certainly solve the issue, and would *probably* result in a system that would be fully functional but slow. Very high end and very low end systems can be rendered unusable by forcing uncached operation, but it's certainly worth a try. Also, if your cache control logic supports both write-back and write-through operation, if you set the default cache "attribute" for kernel and page tables (which is essentially what you're doing under-the-hood when you configure for uncached operation) to write-through, that should cure the problems with copying text pages, but *not* those with re-using them, with less performance impact. I'd be a little surprised if the Ingenic part offered both modes, though. Regards, Kevin K. --------------050905060109090504070609 Content-Type: text/html; charset=UTF-8 Content-Transfer-Encoding: 8bit Nils Faerber wrote: 
Kevin D. Kissell schrieb:
  
Are you sure that the JZ_RISC section is in fact the version of those
functions that's being built into your kernel?
    

Well, there is CONFIG_JZRISC=y in the kernel .config and a
switch(current_cpu_type) { case CPU_JZRISC: ...} so I would assume it is
being used. But I will verify that the CONFIG_JZRISC=y is correctly
translated into a current_cpu_type.
Your assumption is reasonable.  But given that things aren't working, yes, it's good to verify.
Oh, one last question, in order to rule out the cache as bug-spot would
the kernel option "run uncached" "solve" the issue (and be darn slow)?
It would certainly solve the issue, and would *probably* result in a system that would be fully functional but slow.  Very high end and very low end systems can be rendered unusable by forcing uncached operation, but it's certainly worth a try.  Also, if your cache control logic supports both write-back and write-through operation, if you set the default cache "attribute" for kernel and page tables (which is essentially what you're doing under-the-hood when you configure for uncached operation) to write-through, that should cure the problems with copying text pages, but *not* those with re-using them, with less performance impact.  I'd be a little surprised if the Ingenic part offered both modes, though.

          Regards,

          Kevin K.
--------------050905060109090504070609-- From nils.faerber@kernelconcepts.de Mon Mar 9 16:26:44 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 09 Mar 2009 16:26:47 +0000 (GMT) Received: from mail.kernelconcepts.de ([212.60.202.196]:23684 "EHLO mail.kernelconcepts.de") by ftp.linux-mips.org with ESMTP id S20808084AbZCIQ0o (ORCPT ); Mon, 9 Mar 2009 16:26:44 +0000 Received: from [192.168.2.28] by mail.kernelconcepts.de with esmtpsa (TLS-1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.63) (envelope-from ) id 1LgiZ6-0004p1-Pu for linux-mips@linux-mips.org; Mon, 09 Mar 2009 17:42:56 +0100 Message-ID: <49B54342.8070004@kernelconcepts.de> Date: Mon, 09 Mar 2009 17:26:42 +0100 From: Nils Faerber Organization: kernel concepts GbR User-Agent: Thunderbird 2.0.0.19 (X11/20090105) MIME-Version: 1.0 To: linux-mips@linux-mips.org Subject: Re: Ingenic JZ4730 - illegal instruction References: <49B1510B.8020606@kernelconcepts.de> <49B4D5BC.5020203@paralogos.com> <49B4E8BB.8080704@kernelconcepts.de> <49B523B6.6090006@paralogos.com> <49B5302F.4070301@kernelconcepts.de> <49B53987.8020206@paralogos.com> In-Reply-To: <49B53987.8020206@paralogos.com> X-Enigmail-Version: 0.95.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22050 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: nils.faerber@kernelconcepts.de Precedence: bulk X-list: linux-mips Kevin D. Kissell schrieb: > Nils Faerber wrote: >> Kevin D. Kissell schrieb: >>> Are you sure that the JZ_RISC section is in fact the version of those >>> functions that's being built into your kernel? >> Well, there is CONFIG_JZRISC=y in the kernel .config and a >> switch(current_cpu_type) { case CPU_JZRISC: ...} so I would assume it is >> being used. But I will verify that the CONFIG_JZRISC=y is correctly >> translated into a current_cpu_type. > Your assumption is reasonable. But given that things aren't working, > yes, it's good to verify. It should be proper - it is as I can see set by cpu_probe. >> Oh, one last question, in order to rule out the cache as bug-spot would >> the kernel option "run uncached" "solve" the issue (and be darn slow)? > It would certainly solve the issue, and would *probably* result in a > system that would be fully functional but slow. Very high end and very It is *very* slow - you can almost watch every single instruction ;) > low end systems can be rendered unusable by forcing uncached operation, > but it's certainly worth a try. Also, if your cache control logic It seems to run - I am still stuck at the GUI login screen, everything is so darn slow now. Testing for he fault could take ages now, a game of patience it seems ;) > supports both write-back and write-through operation, if you set the > default cache "attribute" for kernel and page tables (which is > essentially what you're doing under-the-hood when you configure for > uncached operation) to write-through, that should cure the problems with > copying text pages, but *not* those with re-using them, with less > performance impact. I'd be a little surprised if the Ingenic part > offered both modes, though. The really bad thing is that I do not have the full datasheet to the CPU so I basically have no idea what this thing really supports or not. So I can only try and test. Luckily this is just a toy project and not a commecial contract work (which I would not have accepted without proper documentation). PS: Login is done now and I suddenly see apps initialisiing that obviously silently failed before - so I am pretty sure now that uncached does work, which means that the cache handling has the bug I am looking for. > Regards, > Kevin K. Cheers nils faerber -- kernel concepts GbR Tel: +49-271-771091-12 Sieghuetter Hauptweg 48 Fax: +49-271-771091-19 D-57072 Siegen Mob: +49-176-21024535 http://www.kernelconcepts.de From ralf@h5.dl5rb.org.uk Mon Mar 9 19:39:04 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 09 Mar 2009 19:39:07 +0000 (GMT) Received: from localhost.localdomain ([127.0.0.1]:9916 "EHLO h5.dl5rb.org.uk") by ftp.linux-mips.org with ESMTP id S21367141AbZCITjE (ORCPT ); Mon, 9 Mar 2009 19:39:04 +0000 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id n29Jd3u6014514; Mon, 9 Mar 2009 20:39:03 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id n29Jd2e1014504; Mon, 9 Mar 2009 20:39:02 +0100 Date: Mon, 9 Mar 2009 20:39:02 +0100 From: Ralf Baechle To: Marian Jancar Cc: linux-mips@linux-mips.org Subject: Re: gcc: mips32 vs mips3 Message-ID: <20090309193902.GA993@linux-mips.org> References: <49B1556E.3030903@satca.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <49B1556E.3030903@satca.net> User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22051 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Fri, Mar 06, 2009 at 05:55:10PM +0100, Marian Jancar wrote: > which option is supposed to compile faster code, -mips3 or -mips32? That question doesn't quite make sense. A MIPS32 processor can't execute MIPS III code and a MIPS III processor can't execute MIPS32 code. Only a MIPS64 processor could execute code compiled for either MIPS32 or MIPS III. So choose the option to match the architecture of your processor. Ralf From stoyboyker@gmail.com Tue Mar 10 05:11:34 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 10 Mar 2009 05:11:39 +0000 (GMT) Received: from yw-out-1718.google.com ([74.125.46.158]:54105 "EHLO yw-out-1718.google.com") by ftp.linux-mips.org with ESMTP id S20808163AbZCJFLe (ORCPT ); Tue, 10 Mar 2009 05:11:34 +0000 Received: by yw-out-1718.google.com with SMTP id 5so878840ywm.24 for ; Mon, 09 Mar 2009 22:11:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer:in-reply-to:references; bh=Ox/QT7fLQ77qQ17iFZ7GtoWdGE01c9E7NMXgyR5NX9U=; b=crKD7B14ww9qAg3ABFucJ9sRoMW9dTGoAYUb0edJ7RNOMLw+hxMKXS8Nk0T1yL9XgG ZjZqqF4GCUBRKmbdX+0aFBeRreWrffO/LH5mq6zckzDeRAK8jXPd8J1zE9ghPjeURUiM shVqUHjsFUI8YWJ28tXoXO+xhOoxE2ENG7bHw= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; b=GMLpsBDs+C6JLiTkzBIiB8MtHOLh0YsNhWB8lTCfZHgwTZXjQQ6xP1GyCHboptPTao M4T5Tc+4njjPJdS2YhvaHfWSTK9OpA0Q2Ssn1QETIMKaxOKaB4FLRPBOMtOhHdKV4wvo QnErs76c1iJtvol1AjxzkZFTkRXtxB2siQmss= Received: by 10.100.44.4 with SMTP id r4mr4187806anr.100.1236661891410; Mon, 09 Mar 2009 22:11:31 -0700 (PDT) Received: from localhost.localdomain (ppp-70-225-161-38.dsl.chmpil.ameritech.net [70.225.161.38]) by mx.google.com with ESMTPS id c23sm8940194ana.52.2009.03.09.22.11.30 (version=TLSv1/SSLv3 cipher=RC4-MD5); Mon, 09 Mar 2009 22:11:30 -0700 (PDT) From: Stoyan Gaydarov To: linux-kernel@vger.kernel.org Cc: Stoyan Gaydarov , ralf@linux-mips.org, linux-mips@linux-mips.org Subject: [PATCH 06/25] [mips] BUG to BUG_ON changes Date: Tue, 10 Mar 2009 00:10:31 -0500 Message-Id: <1236661850-8237-7-git-send-email-stoyboyker@gmail.com> X-Mailer: git-send-email 1.6.1.3 In-Reply-To: <1236661850-8237-6-git-send-email-stoyboyker@gmail.com> References: <1236661850-8237-1-git-send-email-stoyboyker@gmail.com> <1236661850-8237-2-git-send-email-stoyboyker@gmail.com> <1236661850-8237-3-git-send-email-stoyboyker@gmail.com> <1236661850-8237-4-git-send-email-stoyboyker@gmail.com> <1236661850-8237-5-git-send-email-stoyboyker@gmail.com> <1236661850-8237-6-git-send-email-stoyboyker@gmail.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22052 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: stoyboyker@gmail.com Precedence: bulk X-list: linux-mips Signed-off-by: Stoyan Gaydarov --- arch/mips/jazz/jazzdma.c | 3 +-- arch/mips/kernel/traps.c | 3 +-- arch/mips/mm/ioremap.c | 9 +++------ 3 files changed, 5 insertions(+), 10 deletions(-) diff --git a/arch/mips/jazz/jazzdma.c b/arch/mips/jazz/jazzdma.c index c672c08..f0fd636 100644 --- a/arch/mips/jazz/jazzdma.c +++ b/arch/mips/jazz/jazzdma.c @@ -68,8 +68,7 @@ static int __init vdma_init(void) */ pgtbl = (VDMA_PGTBL_ENTRY *)__get_free_pages(GFP_KERNEL | GFP_DMA, get_order(VDMA_PGTBL_SIZE)); - if (!pgtbl) - BUG(); + BUG_ON(!pgtbl); dma_cache_wback_inv((unsigned long)pgtbl, VDMA_PGTBL_SIZE); pgtbl = (VDMA_PGTBL_ENTRY *)KSEG1ADDR(pgtbl); diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index b2d7041..89956d5 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -1277,8 +1277,7 @@ static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs) u32 *w; unsigned char *b; - if (!cpu_has_veic && !cpu_has_vint) - BUG(); + BUG_ON(!cpu_has_veic && !cpu_has_vint); if (addr == NULL) { handler = (unsigned long) do_default_vi; diff --git a/arch/mips/mm/ioremap.c b/arch/mips/mm/ioremap.c index 59945b9..0c43248 100644 --- a/arch/mips/mm/ioremap.c +++ b/arch/mips/mm/ioremap.c @@ -27,8 +27,7 @@ static inline void remap_area_pte(pte_t * pte, unsigned long address, end = address + size; if (end > PMD_SIZE) end = PMD_SIZE; - if (address >= end) - BUG(); + BUG_ON(address >= end); pfn = phys_addr >> PAGE_SHIFT; do { if (!pte_none(*pte)) { @@ -52,8 +51,7 @@ static inline int remap_area_pmd(pmd_t * pmd, unsigned long address, if (end > PGDIR_SIZE) end = PGDIR_SIZE; phys_addr -= address; - if (address >= end) - BUG(); + BUG_ON(address >= end); do { pte_t * pte = pte_alloc_kernel(pmd, address); if (!pte) @@ -75,8 +73,7 @@ static int remap_area_pages(unsigned long address, phys_t phys_addr, phys_addr -= address; dir = pgd_offset(&init_mm, address); flush_cache_all(); - if (address >= end) - BUG(); + BUG_ON(address >= end); do { pud_t *pud; pmd_t *pmd; -- 1.6.1.3 From nietzsche@lysator.liu.se Tue Mar 10 17:12:11 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 10 Mar 2009 17:12:15 +0000 (GMT) Received: from mail.lysator.liu.se ([130.236.254.3]:36529 "EHLO mail.lysator.liu.se") by ftp.linux-mips.org with ESMTP id S21365597AbZCJRML (ORCPT ); Tue, 10 Mar 2009 17:12:11 +0000 Received: from mail.lysator.liu.se (localhost [127.0.0.1]) by mail.lysator.liu.se (Postfix) with ESMTP id E028940028; Tue, 10 Mar 2009 18:12:01 +0100 (CET) Received: from [192.168.10.105] (c-30bde555.035-105-73746f38.cust.bredbandsbolaget.se [85.229.189.48]) (using TLSv1 with cipher AES128-SHA (128/128 bits)) (No client certificate requested) by mail.lysator.liu.se (Postfix) with ESMTP id B3DDA40021; Tue, 10 Mar 2009 18:12:01 +0100 (CET) Cc: linux-mips@linux-mips.org Message-Id: From: Markus Gothe To: ard In-Reply-To: <20090308160328.GC9943@kwaak.net> Content-Type: multipart/signed; protocol="application/pgp-signature"; micalg=pgp-sha1; boundary="Apple-Mail-2-699887765" Content-Transfer-Encoding: 7bit Mime-Version: 1.0 (Apple Message framework v930.3) Subject: Re: Ingenic JZ4730 - illegal instruction Date: Tue, 10 Mar 2009 18:12:05 +0100 References: <49B1510B.8020606@kernelconcepts.de> <20090308160328.GC9943@kwaak.net> X-Pgp-Agent: GPGMail 1.2.0 (v56) X-Mailer: Apple Mail (2.930.3) X-Virus-Scanned: ClamAV using ClamSMTP Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22053 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: nietzsche@lysator.liu.se Precedence: bulk X-list: linux-mips This is an OpenPGP/MIME signed message (RFC 2440 and 3156) --Apple-Mail-2-699887765 Content-Type: text/plain; charset=US-ASCII; format=flowed; delsp=yes Content-Transfer-Encoding: 7bit Afaik it's running Xiptech uCLinux/Stuff. When I dug into the Xburst-subarch it seemed to miss lots of stuff that you'd expect in a MIPS Corp. CPU core. //Markus On 8 Mar 2009, at 17:03, ard wrote: > Hello, > > On Sun, Mar 08, 2009 at 03:53:49PM +0100, Markus Gothe wrote: >> Well, the Xburst-arch seems to be pretty fucked up beyond all repair. > > Hmmm, that doesn't sound promising. But do you have references > for that? > Maybe google has some more info than since I first started > searching. > Anyway: for now it happily runs debian, and for what I can see, > the kernel patches have no real changes except for extra drivers > and extra board and powermanagement drivers. > So if you have hints in which way the xburst deviates from > "standard" mips, it could help us a lot. > In the mean time I am going to subscribe to the ingenic forum > ( http://www.ingenic.cn/eng/forum/vvFrmDefault.aspx ) > that contains more characters that I can't read than characters > that I can read :-(. > > Regards, > Ard > > > -- > .signature not found > --Apple-Mail-2-699887765 content-type: application/pgp-signature; x-mac-type=70674453; name=PGP.sig content-description: This is a digitally signed message part content-disposition: inline; filename=PGP.sig content-transfer-encoding: 7bit -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.8 (Darwin) iEYEARECAAYFAkm2n2UACgkQ6I0XmJx2Nrwl/ACfTm1S8mQwd2Xo/BRwI2uJyby+ JzwAoKtciwMIwkaZHWZ53f110t3nn8tv =f0tp -----END PGP SIGNATURE----- --Apple-Mail-2-699887765-- From dvomlehn@cisco.com Tue Mar 10 19:18:46 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 10 Mar 2009 19:18:52 +0000 (GMT) Received: from sj-iport-1.cisco.com ([171.71.176.70]:24920 "EHLO sj-iport-1.cisco.com") by ftp.linux-mips.org with ESMTP id S21366122AbZCJTSq (ORCPT ); Tue, 10 Mar 2009 19:18:46 +0000 X-IronPort-AV: E=Sophos;i="4.38,337,1233532800"; d="scan'208";a="153684893" Received: from sj-dkim-4.cisco.com ([171.71.179.196]) by sj-iport-1.cisco.com with ESMTP; 10 Mar 2009 19:18:38 +0000 Received: from sj-core-2.cisco.com (sj-core-2.cisco.com [171.71.177.254]) by sj-dkim-4.cisco.com (8.12.11/8.12.11) with ESMTP id n2AJIc0J032013; Tue, 10 Mar 2009 12:18:38 -0700 Received: from cliff.cisco.com (cliff.cisco.com [171.69.11.141]) by sj-core-2.cisco.com (8.13.8/8.13.8) with ESMTP id n2AJIcxY000810; Tue, 10 Mar 2009 19:18:38 GMT Received: from cuplxvomd02.corp.sa.net ([64.101.20.155]) by cliff.cisco.com (8.6.12/8.6.5) with ESMTP id TAA26825; Tue, 10 Mar 2009 19:18:28 GMT Date: Tue, 10 Mar 2009 12:18:28 -0700 From: VomLehn To: Paul Gortmaker Cc: linux-mips@linux-mips.org, ralf@linux-mips.org Subject: Re: [PATCH][MIPS] Use CP0 Count register to implement more granular ndelay Message-ID: <20090310191828.GA30449@cuplxvomd02.corp.sa.net> References: <20090227230950.GA29546@cuplxvomd02.corp.sa.net> <7d1d9c250902281310o7c03da24jcb8760fdfef4d46b@mail.gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <7d1d9c250902281310o7c03da24jcb8760fdfef4d46b@mail.gmail.com> User-Agent: Mutt/1.5.18 (2008-05-17) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; l=10534; t=1236712718; x=1237576718; c=relaxed/simple; s=sjdkim4002; h=Content-Type:From:Subject:Content-Transfer-Encoding:MIME-Version; d=cisco.com; i=dvomlehn@cisco.com; z=From:=20VomLehn=20 |Subject:=20Re=3A=20[PATCH][MIPS]=20Use=20CP0=20Count=20reg ister=20to=20implement=20more=0A=09granular=20ndelay |Sender:=20; bh=zbiMAHknSPe0mdYV1VTFU9XelsBmVIHq/vkWyYpD5is=; b=Gy/nW1CAGOqHmtW35JIZOrk0ovsGNyYU/27kSCea6kKolq9vIHa7hfjTbl q42/WG/DU7fp7W4rCw94bL4mCAMArLeWcBoNW0dLbTe/eJt0WBw4m0jrTsB7 rxLuWxok7t; Authentication-Results: sj-dkim-4; header.From=dvomlehn@cisco.com; dkim=pass ( sig from cisco.com/sjdkim4002 verified; ); Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22054 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dvomlehn@cisco.com Precedence: bulk X-list: linux-mips On Sat, Feb 28, 2009 at 04:10:46PM -0500, Paul Gortmaker wrote: > On Fri, Feb 27, 2009 at 6:09 PM, VomLehn wrote: > > The default implementation of ndelay uses udelay, which will result in the > > rounding up of any requested interval to the next highest number of > > microseconds. This may be a much longer delay than was desired. However, > > if the tick rate of the CP0 Count register is known, it is possible to > > implement an accurate ndelay that works on multiple MIPS processors. > > Presumably the only case where this would ever matter is for delays > that needed to be much less than udelay(1) -- is there a lot of these > out there? According to git grep, the only user of ndelay in > arch/mips is lasat. And, if what is there is working now, then one > could argue that the calls for the short delays are not explicitly > required to be less than udelay(1). I'm working on patches that have a requirement for a 100 nsec delay, which was the motivation for this. I'm trying to mainline code that has been sitting outside the kernel tree for something like 3-1/2 years, but this requires hitting a moving target with a moving gun, so it's taking a while... > > To use this, enable CONFIG_CP0_COUNT_NDELAY and modify the platform startup > > code to call init_ndelay as early as possible. A good place to call it > > is probably the prom_init function. The argument to init_ndelay should be > > the CP0 Count register tick rate, in kHz. The tick rate is typically half > > the processor clock rate so, if you have a 700 MHz processor, the CP0 Count > > register would tick at 350 MHz and you would pass 3500000 to init_ndelay. > > > > At the risk of being obvious, you will need to ensure that ndelay isn't used > > until after the call to init_ndelay. There are no checks to enforce this as > > it would increase the latency in ndelay, but, in order to make it obvious > > that init_ndelay hasn't been called early enough, the initial ndelay > > parameters are set to cause a really large delay. > > I didn't see the arch_initcall for the init_ndelay placed anywhere in > this patch. Two reasons for this: 1. I haven't convinced myself that an arch_init call is early enough; you might need it earlier. I'm open to feedback about this. 2. Doing this as an arch_initcall requires that init_ndelay call some currently undefined function to get the CP0 Count tick rate, whereas it is presently called with that value. Again, I'm open to feedback. > > +config CP0_COUNT_NDELAY > > + bool "Use coprocessor 0 Count register for ndelay functionality" > > + default n > > Does there need to be some sort of depends here to cover off any > limitations where it is known that it won't work? I don't have the breadth of knowledge required to say what processors have a CP0 Count register. Any suggestions? > > +/* Maximum amount of time that will be handled with ndelay, in nanoseconds. > > + * Values bigger than this will be bounced up to udelay. */ > > +#define _MAX_DIRECT_NDELAY 65535 > > Why the leading underscore here? Maybe MAX_CP0_NDELAY would be a > better choice if it has to be changed anyway? I've spent lots of time doing standards and am following the C convention of "hiding" things that aren't part of the published interface with an underscore. The name you suggested has the downside that it implies you can't call ndelay with a bigger value, which isn't true. This is just the cut-over to using udelay. > > + > > +#define ndelay(n) _ndelay(n) > > + > > +extern struct fast_ratio _ndelay_param; > > > ...and here ; not sure why the leading underscore. The previous comment about hiding things that aren't part of the published interface applies. > > +static inline void _ndelay(unsigned long nsecs) > > +{ > > + int start; > > + > > + /* The expected thing would be to do the first read of the Count > > + * register later, just before entering the delay loop. Reading here > > + * ensures that very short intervals will exit the first time through > > + * that loop. */ > > + start = read_c0_count(); > > Is this really going to all work on mips64? I've spent hours > debugging silent boot death on mips64 due to bad variable choices used > for stuff playing with read_c0_count when mips went to generic > clockevents on r4k, and it wasn't fun. I don't have a MIPS64 box to play with, but the manuals make it look like I've got a 32-bit Count register. It is also recommended that, though you *can* set Count, you don't. I'm assuming this has been followed. If not, then your suggestion about a dependency in Kconfig should limit this to 32-bit systems. > > +#ifndef _ASM_MACH_POWERTV_FAST_RATIO_H_ > > +#define _ASM_MACH_POWERTV_FAST_RATIO_H_ > > s/MACH_POWERTV_// is probably what you wanted to do here. Yes, this is bleed-through from the out-of-tree implementation and should be changed. > > +/* Instances of this structure will normally be declared with the attribute > > + * __read_mostly since it only makes sense to use the fast-ratio code if > > + * you fill in the structure once for many calls to evalue the result. */ > > +struct fast_ratio { > > + unsigned long k; > > + unsigned int s; > > + unsigned long r; > > +}; > > Use of "int" again tends to make me nervous. Not to worry. The variable s is a shift count. Since the C standard assures us that ints can hold values up to 32767, this should work until we hit the MIPS32768 architecture. :-) > > +/* This elements are initialized to a value that will cause huge delays to > > + * arise from use of ndelay before calling init_ndelay. This should make such > > + * mistakes obvious enough to easily find and correct. */ > > I think it would be better to have something like: > > if (unlikely(not_calibrated)) > WARN_ON_ONCE(...) If you have to use ndelay instead of udelay, you may very well care about the extra few nanoseconds this would take. > > +struct fast_ratio _ndelay_param __read_mostly = { > > + .k = 0, > > + .s = 0, > > + .r = ULONG_MAX / 2, > > +}; > > +EXPORT_SYMBOL(_ndelay_param); > > Not sure why the leading underscore here either. Same reason as above. > > +#ifndef assert > > +#define assert(x) BUG_ON(!(x)) > > +#endif > > +#endif > > I suspect the thing you will be asked to do here is dump the whole > __KERNEL__ test and assert usage and simply just use BUG_ON right in > the code. Agreed, this is left-over cruft from testing and should be removed. > > +#ifndef BITS_PER_LLONG > > +#define BITS_PER_LLONG ((BITS_PER_LONG * sizeof(long long)) / sizeof(long)) > > +#endif > > Is BITS_PER_LLONG really defined anywhere for anything? See below. > > +/* Type for intermediate calculations, along with the number of bits and > > + * the maximum size. This should be the biggest unsigned type for which > > + * division and modulus by unsigned long are defined on this > > + * architecture. */ > > +#ifdef CONFIG_HAVE_ULLONG_DIV_AND_MOD > > I've not seen any instances of this CONFIG option either. > > > +typedef unsigned long long intermediate_t; > > +#define BITS_PER_ACC BITS_PER_LLONG > > +#define ACC_MAX ULLONG_MAX > > +#else > > +typedef unsigned long intermediate_t; > > +#define BITS_PER_ACC BITS_PER_LONG > > +#define ACC_MAX ULLONG_MAX > > +#endif > > This might fall into the loophole of Documentation/CodingStyle -- > chapter 5; i.e: > > ...but if there is a clear reason for why it under certain circumstances > might be an "unsigned int" and under other configurations might be > "unsigned long", then by all means go ahead and use a typedef. This is fuzzy. The code was developed and tested in userspace for both sizes, but it turns out we don't support division and modulus operations of unsigned long longs by unsigned longs in kernel space, at least at present. Support this would allow additional precision. So, I scratched my head a bit and left it in to see what comments it might provoke. I'm still undecided as to what I should do with it... > > + > > +/* > > Don't these need to start with /** if you want to have them > automagically parsed? Good point. > > +int init_fast_ratio(unsigned int max_x, unsigned long a, > > + unsigned long b, struct fast_ratio *fr) > > +{ > > +#define SHIFT_ROUND_UP(_v, _n) (((_n) < 0) ? \ > > + (((unsigned long long) (_v)) << -(_n)) : \ > > + (((_v) + ((1ull << (_n)) - 1)) >> (_n))) > > +#define ROUNDING_CONST(_s) (((_s) < 0) ? 0 : ((1ull << (_s)) - 1)) > > You've created a fast_ratio.h ; any reason why these #defines don't > live there rather than in the middle of this function? And if there > is any implicit trickery being used that might not be obvious to Joe > Average, then a comment or two wouldn't go amiss. I know that it is > over my head to parse on the fly, but that doesn't say much. :-) The macros aren't part of the interface, so I don't want to put them in the header file. They only used in this particular function, so I only have them defined here. > > +#undef SHIFT_ROUND_UP > > +#undef ROUNDING_CONST > > This is a .c file, so I don't see the need to undef anything at the end. Information hiding, they aren't used outside the function, so they are not defined outside the function. Nested function definitions or scoping rules for #defines would accomplish the same thing. > Generally speaking, I think this could be two separate commits -- one > that implements the basic ndelay uses read_c0_count() concept (if > really required), and then an add-on commit that does the uber > optimization of the whole ratio thing? Then if it turns out that one > hunk gets the green light, and the other doesn't, well then at least > you get to see that one part of your work goes forward. It could be, but I don't know of a current user of the fast-ratio work outside of ndelay, and I like the extra dynamic range and precision it gives you for ndelay. If there is an objection to the fast-ratio stuff, I could recast ndelay as stand-alone but my preference is to have both. I'll tweak this patch and resend a new version. David VomLehn From ralf@h5.dl5rb.org.uk Tue Mar 10 20:12:34 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 10 Mar 2009 20:12:36 +0000 (GMT) Received: from localhost.localdomain ([127.0.0.1]:60126 "EHLO h5.dl5rb.org.uk") by ftp.linux-mips.org with ESMTP id S21367157AbZCJUMe (ORCPT ); Tue, 10 Mar 2009 20:12:34 +0000 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id n2AKCSH0015973; Tue, 10 Mar 2009 21:12:29 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id n2AKCPj0015970; Tue, 10 Mar 2009 21:12:25 +0100 Date: Tue, 10 Mar 2009 21:12:25 +0100 From: Ralf Baechle To: VomLehn Cc: Paul Gortmaker , linux-mips@linux-mips.org Subject: Re: [PATCH][MIPS] Use CP0 Count register to implement more granular ndelay Message-ID: <20090310201224.GA12379@linux-mips.org> References: <20090227230950.GA29546@cuplxvomd02.corp.sa.net> <7d1d9c250902281310o7c03da24jcb8760fdfef4d46b@mail.gmail.com> <20090310191828.GA30449@cuplxvomd02.corp.sa.net> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20090310191828.GA30449@cuplxvomd02.corp.sa.net> User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22055 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Tue, Mar 10, 2009 at 12:18:28PM -0700, VomLehn wrote: > > > +config CP0_COUNT_NDELAY > > > + bool "Use coprocessor 0 Count register for ndelay functionality" > > > + default n > > > > Does there need to be some sort of depends here to cover off any > > limitations where it is known that it won't work? > > I don't have the breadth of knowledge required to say what processors have > a CP0 Count register. Any suggestions? All MIPS III, MIPS IV, MIPS32 and MIPS64 processors have a 32-bit count register which typically is clocked at half the maximum instruction issue rate, more rarely at the full rate. A few processors like the RM53230 family can select the increment rate at reset-time to either the full or half instruction issue rate. Others have the option of totally halting it in special low-power, low-performance modes. The count rate might also be affected by clock scaling. Ralf From joey@infodrom.org Tue Mar 10 21:07:11 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 10 Mar 2009 21:07:35 +0000 (GMT) Received: from luonnotar.infodrom.org ([217.114.79.202]:57779 "EHLO luonnotar.infodrom.org") by ftp.linux-mips.org with ESMTP id S21366010AbZCJVHL (ORCPT ); Tue, 10 Mar 2009 21:07:11 +0000 Received: by luonnotar.infodrom.org (Postfix, from userid 10) id 1384C13400A; Tue, 10 Mar 2009 22:07:10 +0100 (CET) Received: by finlandia.home.infodrom.org (Postfix, from userid 501) id D8DA02B3E03; Tue, 10 Mar 2009 22:04:24 +0100 (CET) Date: Tue, 10 Mar 2009 22:04:24 +0100 From: Joey Schulze To: debian-mips@lists.debian.org, linux-mips@linux-mips.org Subject: MIPS Development Meeting Message-ID: <20090310210424.GY20125@finlandia.home.infodrom.org> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22056 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: joey@infodrom.org Precedence: bulk X-list: linux-mips Hi, we () are organising a MIPS development meeting at the end of next month for a long weekend. It will take place from April 30th to May 3rd in Essen, Germany, at the facility of Linuxhotel (). If you are interested, please let me know in advance and I'll give you details. Regards, Joey -- In the beginning was the word, and the word was content-type: text/plain Please always Cc to me when replying to me on the lists. From ralf@h5.dl5rb.org.uk Tue Mar 10 21:30:15 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 10 Mar 2009 21:30:17 +0000 (GMT) Received: from localhost.localdomain ([127.0.0.1]:50341 "EHLO h5.dl5rb.org.uk") by ftp.linux-mips.org with ESMTP id S20808035AbZCJVaP (ORCPT ); Tue, 10 Mar 2009 21:30:15 +0000 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id n2ALUChO018560; Tue, 10 Mar 2009 22:30:12 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id n2ALU8EH018558; Tue, 10 Mar 2009 22:30:08 +0100 Date: Tue, 10 Mar 2009 22:30:08 +0100 From: Ralf Baechle To: Xiaotian Feng Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH V1] mips: fix mips syscall wrapper sys_32_ipc bug Message-ID: <20090310213008.GA18047@linux-mips.org> References: <1236563112-24287-1-git-send-email-Xiaotian.Feng@windriver.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1236563112-24287-1-git-send-email-Xiaotian.Feng@windriver.com> User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22057 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Mon, Mar 09, 2009 at 09:45:12AM +0800, Xiaotian Feng wrote: > > There's a typo in mips syscall wrapper sys_32_ipc. If CONFIG_SYSVIPC > is not set, it will cause mips linux compile error. > > Signed-off-by: Xiaotian Feng Thanks, applied. Ralf From nietzsche@lysator.liu.se Wed Mar 11 02:25:04 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 11 Mar 2009 02:25:10 +0000 (GMT) Received: from mail.lysator.liu.se ([130.236.254.3]:205 "EHLO mail.lysator.liu.se") by ftp.linux-mips.org with ESMTP id S21367154AbZCKCZE (ORCPT ); Wed, 11 Mar 2009 02:25:04 +0000 Received: from mail.lysator.liu.se (localhost [127.0.0.1]) by mail.lysator.liu.se (Postfix) with ESMTP id A2E6E4006B; Wed, 11 Mar 2009 03:24:55 +0100 (CET) Received: from [192.168.10.105] (c-30bde555.035-105-73746f38.cust.bredbandsbolaget.se [85.229.189.48]) (using TLSv1 with cipher AES128-SHA (128/128 bits)) (No client certificate requested) by mail.lysator.liu.se (Postfix) with ESMTP id 8293840068; Wed, 11 Mar 2009 03:24:55 +0100 (CET) Cc: debian-mips@lists.debian.org, linux-mips@linux-mips.org Message-Id: <89D65DB4-9BDF-4409-908C-78A68F09545F@lysator.liu.se> From: Markus Gothe To: Joey Schulze In-Reply-To: <20090310210424.GY20125@finlandia.home.infodrom.org> Content-Type: multipart/signed; protocol="application/pgp-signature"; micalg=pgp-sha1; boundary="Apple-Mail-1-733061503" Content-Transfer-Encoding: 7bit Mime-Version: 1.0 (Apple Message framework v930.3) Subject: Re: MIPS Development Meeting Date: Wed, 11 Mar 2009 03:24:59 +0100 References: <20090310210424.GY20125@finlandia.home.infodrom.org> X-Pgp-Agent: GPGMail 1.2.0 (v56) X-Mailer: Apple Mail (2.930.3) X-Virus-Scanned: ClamAV using ClamSMTP Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22058 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: nietzsche@lysator.liu.se Precedence: bulk X-list: linux-mips This is an OpenPGP/MIME signed message (RFC 2440 and 3156) --Apple-Mail-1-733061503 Content-Type: text/plain; charset=ISO-8859-1; format=flowed; delsp=yes Content-Transfer-Encoding: quoted-printable Thx, for the info... Essen is quite close to D=FCsseldorf and the =20 Linuxhotel facility is a great stay I can tell from 2007 years Gnash =20 Hackathon. Essen City itself in spring is nice... //Markus On 10 Mar 2009, at 22:04, Joey Schulze wrote: > Hi, > > we () are organising a MIPS development meeting > at the end of next month for a long weekend. It will take place from > April 30th to May 3rd in Essen, Germany, at the facility of Linuxhotel > (). > > If you are interested, please let me know in advance and I'll give you > details. > > Regards, > > Joey > > --=20 > In the beginning was the word, and the word was content-type: text/=20 > plain > > Please always Cc to me when replying to me on the lists. > --Apple-Mail-1-733061503 content-type: application/pgp-signature; x-mac-type=70674453; name=PGP.sig content-description: This is a digitally signed message part content-disposition: inline; filename=PGP.sig content-transfer-encoding: 7bit -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.8 (Darwin) iEYEARECAAYFAkm3IPsACgkQ6I0XmJx2NrzYLwCfTysH8CWvb3rDUhwBgs8aOkLy l6oAoKA4yxpv7BNNJliY8fUanPVIt6+M =QAHb -----END PGP SIGNATURE----- --Apple-Mail-1-733061503-- From ralf@h5.dl5rb.org.uk Wed Mar 11 11:28:10 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 11 Mar 2009 11:28:13 +0000 (GMT) Received: from localhost.localdomain ([127.0.0.1]:5576 "EHLO h5.dl5rb.org.uk") by ftp.linux-mips.org with ESMTP id S20808998AbZCKL2K (ORCPT ); Wed, 11 Mar 2009 11:28:10 +0000 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id n2BBS7wQ025227; Wed, 11 Mar 2009 12:28:07 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id n2BBS6oi025225; Wed, 11 Mar 2009 12:28:06 +0100 Date: Wed, 11 Mar 2009 12:28:06 +0100 From: Ralf Baechle To: linux-mips@linux-mips.org Cc: Thomas Gleixner Subject: __do_IRQ() going away Message-ID: <20090311112806.GA24541@linux-mips.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22059 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips __do_IRQ() is deprecated since a long time and there are plans to remove it for 2.6.30. The MIPS platforms seem to fall into three classes: o Platforms setting CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ to explicitly disable __do_IRQ(): capcella_defconfig, cobalt_defconfig, e55_defconfig, fulong_defconfig, ip27_defconfig, jazz_defconfig, jmr3927_defconfig, lasat_defconfig, mpc30x_defconfig, pnx8335-stb225_defconfig, pnx8550-jbs_defconfig, pnx8550-stb810_defconfig, rb532_defconfig, rbtx49xx_defconfig, tb0219_defconfig, tb0226_defconfig, tb0287_defconfig and workpad_defconfig. o Platforms that don't set CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ but don't seem to use __do_IRQ(): bcm47xx_defconfig, cavium-octeon_defconfig, excite_defconfig, ip22_defconfig, ip28_defconfig, msp71xx_defconfig, wrppmc_defconfig, o Platforms that still seem to rely on __do_IRQ(): o All Sibyte platforms: bigsur_defconfig and sb1250-swarm_defconfig o All Alchemy platforms: db1000_defconfig, db1100_defconfig, db1200_defconfig, db1500_defconfig, db1550_defconfig, mtx1_defconfig, pb1100_defconfig, pb1500_defconfig and pb1550_defconfig o malta_defconfig. The platform code itself is ok but irq-gic.c, irq-msc01.c, irq-msc01.c and irq_cpu.c are still using set_irq_chip and need fixing. o And the rest: decstation_defconfig, emma2rh_defconfig, ip32_defconfig, yosemite_defconfig, mipssim_defconfig and rm200_defconfig. For now I've checked in the following patch into linux-queue. Ralf MIPS: Enable GENERIC_HARDIRQS_NO__DO_IRQ for all platforms __do_IRQ() is deprecated and will go away. Signed-off-by: Ralf Baechle arch/mips/Kconfig | 12 +----------- 1 file changed, 1 insertion(+), 11 deletions(-) --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -77,7 +77,6 @@ config MIPS_COBALT select SYS_SUPPORTS_32BIT_KERNEL select SYS_SUPPORTS_64BIT_KERNEL select SYS_SUPPORTS_LITTLE_ENDIAN - select GENERIC_HARDIRQS_NO__DO_IRQ config MACH_DECSTATION bool "DECstations" @@ -132,7 +131,6 @@ config MACH_JAZZ select SYS_SUPPORTS_32BIT_KERNEL select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL select SYS_SUPPORTS_100HZ - select GENERIC_HARDIRQS_NO__DO_IRQ help This a family of machines based on the MIPS R4030 chipset which was used by several vendors to build RISC/os and Windows NT workstations. @@ -154,7 +152,6 @@ config LASAT select SYS_SUPPORTS_32BIT_KERNEL select SYS_SUPPORTS_64BIT_KERNEL if BROKEN select SYS_SUPPORTS_LITTLE_ENDIAN - select GENERIC_HARDIRQS_NO__DO_IRQ config LEMOTE_FULONG bool "Lemote Fulong mini-PC" @@ -175,7 +172,6 @@ config LEMOTE_FULONG select SYS_SUPPORTS_LITTLE_ENDIAN select SYS_SUPPORTS_HIGHMEM select SYS_HAS_EARLY_PRINTK - select GENERIC_HARDIRQS_NO__DO_IRQ select GENERIC_ISA_DMA_SUPPORT_BROKEN select CPU_HAS_WB help @@ -246,7 +242,6 @@ config MACH_VR41XX select CEVT_R4K select CSRC_R4K select SYS_HAS_CPU_VR41XX - select GENERIC_HARDIRQS_NO__DO_IRQ config NXP_STB220 bool "NXP STB220 board" @@ -360,7 +355,6 @@ config SGI_IP27 select SYS_SUPPORTS_BIG_ENDIAN select SYS_SUPPORTS_NUMA select SYS_SUPPORTS_SMP - select GENERIC_HARDIRQS_NO__DO_IRQ help This are the SGI Origin 200, Origin 2000 and Onyx 2 Graphics workstations. To compile a Linux kernel that runs on these, say Y @@ -559,7 +553,6 @@ config MIKROTIK_RB532 select CEVT_R4K select CSRC_R4K select DMA_NONCOHERENT - select GENERIC_HARDIRQS_NO__DO_IRQ select HW_HAS_PCI select IRQ_CPU select SYS_HAS_CPU_MIPS32_R1 @@ -697,8 +690,7 @@ config SCHED_OMIT_FRAME_POINTER default y config GENERIC_HARDIRQS_NO__DO_IRQ - bool - default n + def_bool y # # Select some configuration options automatically based on user selections. @@ -905,7 +897,6 @@ config SOC_PNX833X select SYS_SUPPORTS_32BIT_KERNEL select SYS_SUPPORTS_LITTLE_ENDIAN select SYS_SUPPORTS_BIG_ENDIAN - select GENERIC_HARDIRQS_NO__DO_IRQ select GENERIC_GPIO select CPU_MIPSR2_IRQ_VI @@ -924,7 +915,6 @@ config SOC_PNX8550 select SYS_HAS_CPU_MIPS32_R1 select SYS_HAS_EARLY_PRINTK select SYS_SUPPORTS_32BIT_KERNEL - select GENERIC_HARDIRQS_NO__DO_IRQ select GENERIC_GPIO config SWAP_IO_SPACE From ralf@h5.dl5rb.org.uk Wed Mar 11 14:09:21 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 11 Mar 2009 14:09:24 +0000 (GMT) Received: from localhost.localdomain ([127.0.0.1]:36561 "EHLO h5.dl5rb.org.uk") by ftp.linux-mips.org with ESMTP id S21103627AbZCKOJV (ORCPT ); Wed, 11 Mar 2009 14:09:21 +0000 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id n2BE9JkU003963; Wed, 11 Mar 2009 15:09:19 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id n2BE9I5i003955; Wed, 11 Mar 2009 15:09:18 +0100 Date: Wed, 11 Mar 2009 15:09:18 +0100 From: Ralf Baechle To: Shinya Kuribayashi Cc: linux-mips@linux-mips.org Subject: Re: [PATCH] MIPS: NEC VR5500 processor support fixup Message-ID: <20090311140918.GA3907@linux-mips.org> References: <49ACF2EF.3080903@necel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <49ACF2EF.3080903@necel.com> User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22060 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Tue, Mar 03, 2009 at 06:05:51PM +0900, Shinya Kuribayashi wrote: Thanks, applied! Ralf From ralf@h5.dl5rb.org.uk Wed Mar 11 19:18:30 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 11 Mar 2009 19:18:35 +0000 (GMT) Received: from localhost.localdomain ([127.0.0.1]:59827 "EHLO h5.dl5rb.org.uk") by ftp.linux-mips.org with ESMTP id S20808194AbZCKTSa (ORCPT ); Wed, 11 Mar 2009 19:18:30 +0000 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id n2BJIPMH005303; Wed, 11 Mar 2009 20:18:25 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id n2BJIENP005299; Wed, 11 Mar 2009 20:18:14 +0100 Date: Wed, 11 Mar 2009 20:18:14 +0100 From: Ralf Baechle To: Stoyan Gaydarov Cc: linux-kernel@vger.kernel.org, linux-mips@linux-mips.org Subject: Re: [PATCH 06/25] [mips] BUG to BUG_ON changes Message-ID: <20090311191814.GA3112@linux-mips.org> References: <1236661850-8237-1-git-send-email-stoyboyker@gmail.com> <1236661850-8237-2-git-send-email-stoyboyker@gmail.com> <1236661850-8237-3-git-send-email-stoyboyker@gmail.com> <1236661850-8237-4-git-send-email-stoyboyker@gmail.com> <1236661850-8237-5-git-send-email-stoyboyker@gmail.com> <1236661850-8237-6-git-send-email-stoyboyker@gmail.com> <1236661850-8237-7-git-send-email-stoyboyker@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1236661850-8237-7-git-send-email-stoyboyker@gmail.com> User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22061 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Tue, Mar 10, 2009 at 12:10:31AM -0500, Stoyan Gaydarov wrote: I wonder if this patch series was generated with http://www.emn.fr/x-info/coccinelle/rules/bugon.html ? That semantic patch misses the same places that your patch is missing. The patch below should catch all occurances below arch/mips. Ralf Signed-off-by: Ralf Baechle arch/mips/jazz/jazzdma.c | 3 +-- arch/mips/kernel/traps.c | 3 +-- arch/mips/mm/highmem.c | 9 +++------ arch/mips/mm/init.c | 3 +-- arch/mips/mm/ioremap.c | 9 +++------ 5 files changed, 9 insertions(+), 18 deletions(-) diff --git a/arch/mips/jazz/jazzdma.c b/arch/mips/jazz/jazzdma.c index c672c08..f0fd636 100644 --- a/arch/mips/jazz/jazzdma.c +++ b/arch/mips/jazz/jazzdma.c @@ -68,8 +68,7 @@ static int __init vdma_init(void) */ pgtbl = (VDMA_PGTBL_ENTRY *)__get_free_pages(GFP_KERNEL | GFP_DMA, get_order(VDMA_PGTBL_SIZE)); - if (!pgtbl) - BUG(); + BUG_ON(!pgtbl); dma_cache_wback_inv((unsigned long)pgtbl, VDMA_PGTBL_SIZE); pgtbl = (VDMA_PGTBL_ENTRY *)KSEG1ADDR(pgtbl); diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index b2d7041..89956d5 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -1277,8 +1277,7 @@ static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs) u32 *w; unsigned char *b; - if (!cpu_has_veic && !cpu_has_vint) - BUG(); + BUG_ON(!cpu_has_veic && !cpu_has_vint); if (addr == NULL) { handler = (unsigned long) do_default_vi; diff --git a/arch/mips/mm/highmem.c b/arch/mips/mm/highmem.c index 8f2cd8e..060d28d 100644 --- a/arch/mips/mm/highmem.c +++ b/arch/mips/mm/highmem.c @@ -17,8 +17,7 @@ void *__kmap(struct page *page) void __kunmap(struct page *page) { - if (in_interrupt()) - BUG(); + BUG_ON(in_interrupt()); if (!PageHighMem(page)) return; kunmap_high(page); @@ -46,8 +45,7 @@ void *__kmap_atomic(struct page *page, enum km_type type) idx = type + KM_TYPE_NR*smp_processor_id(); vaddr = __fix_to_virt(FIX_KMAP_BEGIN + idx); #ifdef CONFIG_DEBUG_HIGHMEM - if (!pte_none(*(kmap_pte-idx))) - BUG(); + BUG_ON(!pte_none(*(kmap_pte - idx))); #endif set_pte(kmap_pte-idx, mk_pte(page, kmap_prot)); local_flush_tlb_one((unsigned long)vaddr); @@ -66,8 +64,7 @@ void __kunmap_atomic(void *kvaddr, enum km_type type) return; } - if (vaddr != __fix_to_virt(FIX_KMAP_BEGIN+idx)) - BUG(); + BUG_ON(vaddr != __fix_to_virt(FIX_KMAP_BEGIN + idx)); /* * force other mappings to Oops if they'll try to access diff --git a/arch/mips/mm/init.c b/arch/mips/mm/init.c index 137c14b..d934894 100644 --- a/arch/mips/mm/init.c +++ b/arch/mips/mm/init.c @@ -307,8 +307,7 @@ void __init fixrange_init(unsigned long start, unsigned long end, if (pmd_none(*pmd)) { pte = (pte_t *) alloc_bootmem_low_pages(PAGE_SIZE); set_pmd(pmd, __pmd((unsigned long)pte)); - if (pte != pte_offset_kernel(pmd, 0)) - BUG(); + BUG_ON(pte != pte_offset_kernel(pmd, 0)); } vaddr += PMD_SIZE; } diff --git a/arch/mips/mm/ioremap.c b/arch/mips/mm/ioremap.c index 59945b9..0c43248 100644 --- a/arch/mips/mm/ioremap.c +++ b/arch/mips/mm/ioremap.c @@ -27,8 +27,7 @@ static inline void remap_area_pte(pte_t * pte, unsigned long address, end = address + size; if (end > PMD_SIZE) end = PMD_SIZE; - if (address >= end) - BUG(); + BUG_ON(address >= end); pfn = phys_addr >> PAGE_SHIFT; do { if (!pte_none(*pte)) { @@ -52,8 +51,7 @@ static inline int remap_area_pmd(pmd_t * pmd, unsigned long address, if (end > PGDIR_SIZE) end = PGDIR_SIZE; phys_addr -= address; - if (address >= end) - BUG(); + BUG_ON(address >= end); do { pte_t * pte = pte_alloc_kernel(pmd, address); if (!pte) @@ -75,8 +73,7 @@ static int remap_area_pages(unsigned long address, phys_t phys_addr, phys_addr -= address; dir = pgd_offset(&init_mm, address); flush_cache_all(); - if (address >= end) - BUG(); + BUG_ON(address >= end); do { pud_t *pud; pmd_t *pmd; From ralf@h5.dl5rb.org.uk Wed Mar 11 19:59:08 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 11 Mar 2009 19:59:11 +0000 (GMT) Received: from localhost.localdomain ([127.0.0.1]:54723 "EHLO h5.dl5rb.org.uk") by ftp.linux-mips.org with ESMTP id S21366501AbZCKT7I (ORCPT ); Wed, 11 Mar 2009 19:59:08 +0000 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id n2BJx6Kv007546; Wed, 11 Mar 2009 20:59:06 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id n2BJx41B007543; Wed, 11 Mar 2009 20:59:04 +0100 Date: Wed, 11 Mar 2009 20:59:04 +0100 From: Ralf Baechle To: Atsushi Nemoto Cc: linux-mips@linux-mips.org Subject: Re: [PATCH] TXx9: update defconfigs Message-ID: <20090311195904.GD3112@linux-mips.org> References: <1236177944-24243-1-git-send-email-anemo@mba.ocn.ne.jp> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1236177944-24243-1-git-send-email-anemo@mba.ocn.ne.jp> User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22062 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Wed, Mar 04, 2009 at 11:45:44PM +0900, Atsushi Nemoto wrote: > From: Atsushi Nemoto > Date: Wed, 4 Mar 2009 23:45:44 +0900 > To: linux-mips@linux-mips.org > Cc: ralf@linux-mips.org > Subject: [PATCH] TXx9: update defconfigs > > Enable following features: > * MTD (PHYSMAP) > * LED (LEDS_GPIO) > * RBTX4939 > * 7SEGLED > * IDE (IDE_TX4938, IDE_TX4939) > * SMC91X > * RTC_DRV_TX4939 Guess this one still belongs into 2.6.29 to cut some of the rough edges for the users. Applied, thanks Atsushi-San! Ralf From nietzsche@lysator.liu.se Wed Mar 11 23:23:28 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 11 Mar 2009 23:23:35 +0000 (GMT) Received: from mail.lysator.liu.se ([130.236.254.3]:61629 "EHLO mail.lysator.liu.se") by ftp.linux-mips.org with ESMTP id S20808404AbZCKXX2 (ORCPT ); Wed, 11 Mar 2009 23:23:28 +0000 Received: from mail.lysator.liu.se (localhost [127.0.0.1]) by mail.lysator.liu.se (Postfix) with ESMTP id 627F740009; Thu, 12 Mar 2009 00:23:19 +0100 (CET) Received: from [192.168.10.105] (c-30bde555.035-105-73746f38.cust.bredbandsbolaget.se [85.229.189.48]) (using TLSv1 with cipher AES128-SHA (128/128 bits)) (No client certificate requested) by mail.lysator.liu.se (Postfix) with ESMTP id 4097040007; Thu, 12 Mar 2009 00:23:19 +0100 (CET) Cc: linux-mips@linux-mips.org, Thomas Gleixner Message-Id: <1977ADB0-36B0-4370-B3E5-A8D5DC5EEE36@lysator.liu.se> From: Markus Gothe To: Ralf Baechle In-Reply-To: <20090311112806.GA24541@linux-mips.org> Content-Type: multipart/signed; protocol="application/pgp-signature"; micalg=pgp-sha1; boundary="Apple-Mail-24-808569442" Content-Transfer-Encoding: 7bit Mime-Version: 1.0 (Apple Message framework v930.3) Subject: Re: __do_IRQ() going away Date: Thu, 12 Mar 2009 00:23:27 +0100 References: <20090311112806.GA24541@linux-mips.org> X-Pgp-Agent: GPGMail 1.2.0 (v56) X-Mailer: Apple Mail (2.930.3) X-Virus-Scanned: ClamAV using ClamSMTP Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22063 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: nietzsche@lysator.liu.se Precedence: bulk X-list: linux-mips This is an OpenPGP/MIME signed message (RFC 2440 and 3156) --Apple-Mail-24-808569442 Content-Type: text/plain; charset=US-ASCII; format=flowed; delsp=yes Content-Transfer-Encoding: 7bit I'll have a quick look at the NEC EMMA2 code, for review... //Markus On 11 Mar 2009, at 12:28, Ralf Baechle wrote: > __do_IRQ() is deprecated since a long time and there are plans to > remove > it for 2.6.30. The MIPS platforms seem to fall into three classes: > > o Platforms setting CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ to explicitly > disable > __do_IRQ(): > capcella_defconfig, cobalt_defconfig, e55_defconfig, > fulong_defconfig, ip27_defconfig, jazz_defconfig, jmr3927_defconfig, > lasat_defconfig, mpc30x_defconfig, pnx8335-stb225_defconfig, > pnx8550-jbs_defconfig, pnx8550-stb810_defconfig, rb532_defconfig, > rbtx49xx_defconfig, tb0219_defconfig, tb0226_defconfig, > tb0287_defconfig and workpad_defconfig. > > o Platforms that don't set CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ but > don't > seem to use __do_IRQ(): > > bcm47xx_defconfig, cavium-octeon_defconfig, excite_defconfig, > ip22_defconfig, ip28_defconfig, msp71xx_defconfig, wrppmc_defconfig, > > o Platforms that still seem to rely on __do_IRQ(): > o All Sibyte platforms: > bigsur_defconfig and sb1250-swarm_defconfig > > o All Alchemy platforms: > db1000_defconfig, db1100_defconfig, db1200_defconfig, > db1500_defconfig, > db1550_defconfig, mtx1_defconfig, pb1100_defconfig, pb1500_defconfig > and pb1550_defconfig > > o malta_defconfig. The platform code itself is ok but irq-gic.c, > irq-msc01.c, irq-msc01.c and irq_cpu.c are still using set_irq_chip > and need fixing. > > o And the rest: > decstation_defconfig, emma2rh_defconfig, ip32_defconfig, > yosemite_defconfig, mipssim_defconfig and rm200_defconfig. > > For now I've checked in the following patch into linux-queue. > > Ralf > > MIPS: Enable GENERIC_HARDIRQS_NO__DO_IRQ for all platforms > > __do_IRQ() is deprecated and will go away. > > Signed-off-by: Ralf Baechle > > arch/mips/Kconfig | 12 +----------- > 1 file changed, 1 insertion(+), 11 deletions(-) > > --- a/arch/mips/Kconfig > +++ b/arch/mips/Kconfig > @@ -77,7 +77,6 @@ config MIPS_COBALT > select SYS_SUPPORTS_32BIT_KERNEL > select SYS_SUPPORTS_64BIT_KERNEL > select SYS_SUPPORTS_LITTLE_ENDIAN > - select GENERIC_HARDIRQS_NO__DO_IRQ > > config MACH_DECSTATION > bool "DECstations" > @@ -132,7 +131,6 @@ config MACH_JAZZ > select SYS_SUPPORTS_32BIT_KERNEL > select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL > select SYS_SUPPORTS_100HZ > - select GENERIC_HARDIRQS_NO__DO_IRQ > help > This a family of machines based on the MIPS R4030 chipset which was > used by several vendors to build RISC/os and Windows NT > workstations. > @@ -154,7 +152,6 @@ config LASAT > select SYS_SUPPORTS_32BIT_KERNEL > select SYS_SUPPORTS_64BIT_KERNEL if BROKEN > select SYS_SUPPORTS_LITTLE_ENDIAN > - select GENERIC_HARDIRQS_NO__DO_IRQ > > config LEMOTE_FULONG > bool "Lemote Fulong mini-PC" > @@ -175,7 +172,6 @@ config LEMOTE_FULONG > select SYS_SUPPORTS_LITTLE_ENDIAN > select SYS_SUPPORTS_HIGHMEM > select SYS_HAS_EARLY_PRINTK > - select GENERIC_HARDIRQS_NO__DO_IRQ > select GENERIC_ISA_DMA_SUPPORT_BROKEN > select CPU_HAS_WB > help > @@ -246,7 +242,6 @@ config MACH_VR41XX > select CEVT_R4K > select CSRC_R4K > select SYS_HAS_CPU_VR41XX > - select GENERIC_HARDIRQS_NO__DO_IRQ > > config NXP_STB220 > bool "NXP STB220 board" > @@ -360,7 +355,6 @@ config SGI_IP27 > select SYS_SUPPORTS_BIG_ENDIAN > select SYS_SUPPORTS_NUMA > select SYS_SUPPORTS_SMP > - select GENERIC_HARDIRQS_NO__DO_IRQ > help > This are the SGI Origin 200, Origin 2000 and Onyx 2 Graphics > workstations. To compile a Linux kernel that runs on these, say Y > @@ -559,7 +553,6 @@ config MIKROTIK_RB532 > select CEVT_R4K > select CSRC_R4K > select DMA_NONCOHERENT > - select GENERIC_HARDIRQS_NO__DO_IRQ > select HW_HAS_PCI > select IRQ_CPU > select SYS_HAS_CPU_MIPS32_R1 > @@ -697,8 +690,7 @@ config SCHED_OMIT_FRAME_POINTER > default y > > config GENERIC_HARDIRQS_NO__DO_IRQ > - bool > - default n > + def_bool y > > # > # Select some configuration options automatically based on user > selections. > @@ -905,7 +897,6 @@ config SOC_PNX833X > select SYS_SUPPORTS_32BIT_KERNEL > select SYS_SUPPORTS_LITTLE_ENDIAN > select SYS_SUPPORTS_BIG_ENDIAN > - select GENERIC_HARDIRQS_NO__DO_IRQ > select GENERIC_GPIO > select CPU_MIPSR2_IRQ_VI > > @@ -924,7 +915,6 @@ config SOC_PNX8550 > select SYS_HAS_CPU_MIPS32_R1 > select SYS_HAS_EARLY_PRINTK > select SYS_SUPPORTS_32BIT_KERNEL > - select GENERIC_HARDIRQS_NO__DO_IRQ > select GENERIC_GPIO > > config SWAP_IO_SPACE > --Apple-Mail-24-808569442 content-type: application/pgp-signature; x-mac-type=70674453; name=PGP.sig content-description: This is a digitally signed message part content-disposition: inline; filename=PGP.sig content-transfer-encoding: 7bit -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.8 (Darwin) iEYEARECAAYFAkm4R+8ACgkQ6I0XmJx2Nrww9wCg2M/lbvGoVN6EhM4UwUsk6Ros yS8AoJwfcFi/Z28mwXn/AoovsKdSiT4h =4VbH -----END PGP SIGNATURE----- --Apple-Mail-24-808569442-- From dvomlehn@cisco.com Thu Mar 12 03:29:16 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 12 Mar 2009 03:29:22 +0000 (GMT) Received: from sj-iport-2.cisco.com ([171.71.176.71]:15406 "EHLO sj-iport-2.cisco.com") by ftp.linux-mips.org with ESMTP id S21367257AbZCLD3Q (ORCPT ); Thu, 12 Mar 2009 03:29:16 +0000 X-IronPort-AV: E=Sophos;i="4.38,347,1233532800"; d="scan'208";a="140657381" Received: from sj-dkim-2.cisco.com ([171.71.179.186]) by sj-iport-2.cisco.com with ESMTP; 12 Mar 2009 03:28:56 +0000 Received: from sj-core-2.cisco.com (sj-core-2.cisco.com [171.71.177.254]) by sj-dkim-2.cisco.com (8.12.11/8.12.11) with ESMTP id n2C3Suqv014942; Wed, 11 Mar 2009 20:28:56 -0700 Received: from cliff.cisco.com (cliff.cisco.com [171.69.11.141]) by sj-core-2.cisco.com (8.13.8/8.13.8) with ESMTP id n2C3SuSv018217; Thu, 12 Mar 2009 03:28:56 GMT Received: from cuplxvomd02.corp.sa.net ([64.101.20.155]) by cliff.cisco.com (8.6.12/8.6.5) with ESMTP id DAA00222; Thu, 12 Mar 2009 03:28:50 GMT Date: Wed, 11 Mar 2009 20:28:50 -0700 From: VomLehn To: Linux MIPS Mailing List Cc: Ralf Baechle Subject: [PATCH][MIPS] Use CP0 Count register to implement more granular ndelay Message-ID: <20090312032850.GA9379@cuplxvomd02.corp.sa.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline User-Agent: Mutt/1.5.18 (2008-05-17) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; l=18348; t=1236828536; x=1237692536; c=relaxed/simple; s=sjdkim2002; h=Content-Type:From:Subject:Content-Transfer-Encoding:MIME-Version; d=cisco.com; i=dvomlehn@cisco.com; z=From:=20VomLehn=20 |Subject:=20[PATCH][MIPS]=20Use=20CP0=20Count=20register=20 to=20implement=20more=20granular=0A=09ndelay |Sender:=20; bh=GvPIih9vNdrxljmKWQ2m8kjyBdhwkbQCqWREMYt3xhE=; b=LCzt85djezSSVOZ6+hiKJiBw8L7phSu/JDG9Jyo90Z73UONz0MWcaphPG+ SMxnToz+Cp332ruXoQVTci6wTnBWcIbLJ1wcOJIyvqlWHYxDQdzsyXTIds1a rgZthjmoaF; Authentication-Results: sj-dkim-2; header.From=dvomlehn@cisco.com; dkim=pass ( sig from cisco.com/sjdkim2002 verified; ); Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22064 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dvomlehn@cisco.com Precedence: bulk X-list: linux-mips The default implementation of ndelay uses udelay, which will result in the rounding up of any requested interval to the next highest number of microseconds. This may be a much longer delay than was desired. However, if the tick rate of the CP0 Count register is known, it is possible to implement an accurate ndelay that works on multiple MIPS processors. To use this, enable CONFIG_CP0_COUNT_NDELAY and modify the platform startup code to call init_ndelay as early as possible. A good place to call it is probably the prom_init function. The argument to init_ndelay should be the CP0 Count register tick rate, in kHz. The tick rate is typically half the processor clock rate so, if you have a 700 MHz processor, the CP0 Count register would tick at 350 MHz and you would pass 3500000 to init_ndelay. This is version 3. Changes from version 2 include: o Correct the BUG_ON comparison as it has a reversed sense from assert. Sorry, dumb mistake. o Remove unnecessary of comparison to see if an unsigned long variable is bigger than ULONG_MAX. o Created a "safe" version of ndelay that disables interrupts to avoid the possibility of a long interrupt processing interval turning a very short delay into a much longer delay. If you know interrupts are disabled, you can use no_interrupt_ndelay. Changes from version 1 include: o Added definitions for MIPS1, MIPS2, MIPS3, and MIPS4 configurations o Restricted use of CP0 Count register-based ndelay to MIPS2, MIPS3, MIPS32, and MIPS64 configurations. o Replaced assert code with BUG_ON o Corrected name of preprocessor symbol avoid multiple inclusions of fast-ratio.h and delay.h o Used '/**' to mark comments intended to be automatically parsed. Signed-off-by: David VomLehn --- arch/mips/Kconfig | 30 +++++ arch/mips/include/asm/delay.h | 100 +++++++++++++++++++ arch/mips/include/asm/fast-ratio.h | 53 ++++++++++ arch/mips/lib/Makefile | 6 - arch/mips/lib/delay.c | 59 +++++++++++ arch/mips/lib/fast-ratio.c | 187 +++++++++++++++++++++++++++++++++++++ 6 files changed, 433 insertions(+), 2 deletions(-) Index: linux-2.6/arch/mips/Kconfig =================================================================== --- linux-2.6.orig/arch/mips/Kconfig +++ linux-2.6/arch/mips/Kconfig @@ -1371,6 +1371,26 @@ config WEAK_REORDERING_BEYOND_LLSC endmenu # +# Collect various processors by instruction family +# +config MIPS1 + bool + default y if CPU_R3000 || CPU_TX39XX + +config MIPS2 + bool + default y if CPU_R6000 + +config MIPS3 + bool + default y if CPU_LOONGSON2 || CPU_R4300 || CPU_R4X00 || CPU_TX49XX || \ + CPU_VR41XX + +config MIPS4 + bool + default y if CPU_R8000 || CPU_R10000 + +# # These two indicate any level of the MIPS32 and MIPS64 architecture # config CPU_MIPS32 @@ -1876,6 +1896,16 @@ config NR_CPUS source "kernel/time/Kconfig" +config CP0_COUNT_NDELAY + bool "Use coprocessor 0 Count register for ndelay functionality" + depends on CPU_MIPS3 || CPU_MIPS4 || CPU_MIPS32 || CPU_MIPS64 + default n + help + Implements the ndelay function using the coprocessor 0 Count + register. Using this requires including a call to init_ndelay + with the Count register increment frequency, in KHz, in one + of the early initialization functions. + # # Timer Interrupt Frequency Configuration # Index: linux-2.6/arch/mips/include/asm/delay.h =================================================================== --- linux-2.6.orig/arch/mips/include/asm/delay.h +++ linux-2.6/arch/mips/include/asm/delay.h @@ -109,4 +109,104 @@ static inline void __udelay(unsigned lon #define MAX_UDELAY_MS (1000 / HZ) #endif +#ifdef CONFIG_CP0_COUNT_NDELAY +/* + * Definitions for using MIPS CP0 Count register-based ndelay. If + * CONFIG_CP0_COUNT_NDELAY is not defined, ndelay will default to using + * udelay. + */ + +#include +#include +#include + +/* Maximum amount of time that will be handled with ndelay, in nanoseconds. + * Values bigger than this will be bounced up to udelay. */ +#define _MAX_DIRECT_NDELAY 65535 + +#define ndelay(n) _safe_ndelay(n) + +extern struct fast_ratio _ndelay_param; + +/* + * Compute the number of CP0 Count ticks corresponding to the interval + * @nsecs: Interval, expressed in nanoseconds + * Breaking this out as its own function makes it easier to test. + */ +static inline unsigned int _ndelay_ticks(unsigned int nsecs) +{ + return fast_ratio(nsecs, &_ndelay_param); +} + +/** + * Delay for at least the given number of nanoseconds + * @nsecs: Number of nanoseconds to delay + * + * This function uses the CP0 Count register to give a pretty accurate delay + * for very short delay periods. Very small delays will, unavoidably, be + * dominated by the instructions in this function but this should converge + * to the true delay reasonably quickly before nsecs gets very large. + * + * NOTE: Failure to call init_ndelay will result in *very* long delay times. + * This is done deliberately to ensure that, if you use ndelay and forget to + * call init_delay first, you will notice your mistake quickly. + * + * NOTE: If we are interrupted for so long that the Count register can + * by more than half of the total value, the test will wrap and you will wind + * up with a much longer delay than you expect. So, only call this if you: + * o Have interrupts disabled, or + * o Are sure this can never be interrupted for more than half the time + * it takes for the Count register to wrap. + * Otherwise, use ndelay. + */ +static inline void no_interrupt_ndelay(unsigned long nsecs) +{ + int start; + + /* The expected thing would be to do the first read of the Count + * register later, just before entering the delay loop. Reading here + * ensures that very short intervals will exit the first time through + * that loop. */ + start = read_c0_count(); + + if (unlikely(nsecs > _MAX_DIRECT_NDELAY)) + udelay(DIV_ROUND_UP(nsecs, 1000)); /* Would overflow counter */ + + else { + int end; + int now; + + end = start + _ndelay_ticks(nsecs); + + do { + now = read_c0_count(); + } while (end - now > 0); + } +} + +/** + * Delay for at least the given number of nanoseconds + * @nsecs: Number of nanoseconds to delay + * + * This is the safe version that disables interrupts to avoid the possibility + * of very long interrupts causing the comparision to wrap. Don't use this + * directly; use ndelay. + */ +static inline void _safe_ndelay(unsigned long nsecs) +{ + unsigned long flags; + + local_irq_save(flags); + no_interrupt_ndelay(nsecs); + local_irq_restore(flags); +} + +extern int init_ndelay(unsigned int count_freq); +#else +static inline int init_ndelay(unsigned int count_freq) +{ + return 0; +} +#endif + #endif /* _ASM_DELAY_H */ Index: linux-2.6/arch/mips/include/asm/fast-ratio.h =================================================================== --- /dev/null +++ linux-2.6/arch/mips/include/asm/fast-ratio.h @@ -0,0 +1,53 @@ +/* + * fast-ratio.h + * + * Definitions for using fast evaluator for expressions of the form: + * a + * x * - + * b + * + * where x can be constrained to some maximum value and a and b are constants. + * + * Copyright (C) 2009 Cisco Systems, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _ASM_FAST_RATIO_H_ +#define _ASM_FAST_RATIO_H_ + +/* Instances of this structure will normally be declared with the attribute + * __read_mostly since it only makes sense to use the fast-ratio code if + * you fill in the structure once for many calls to evalue the result. */ +struct fast_ratio { + unsigned long k; + unsigned int s; + unsigned long r; +}; + +/** + * Evaluate x * (a / b), a and b constant, as transformed for speed. + * @x: Value to multiply by a / b + * @fr: Pointer to &struct fast_ratio with transformed values for a and b + * Returns x * (a / b), rounded up in an unsigned long value + */ +static inline unsigned long fast_ratio(unsigned long x, struct fast_ratio *fr) +{ + return (x * fr->k + fr->r) >> fr->s; +} + +extern int init_fast_ratio(unsigned int max_x, unsigned long a, + unsigned long b, struct fast_ratio *fr); +#endif Index: linux-2.6/arch/mips/lib/Makefile =================================================================== --- linux-2.6.orig/arch/mips/lib/Makefile +++ linux-2.6/arch/mips/lib/Makefile @@ -2,8 +2,8 @@ # Makefile for MIPS-specific library files.. # -lib-y += csum_partial.o memcpy.o memcpy-inatomic.o memset.o strlen_user.o \ - strncpy_user.o strnlen_user.o uncached.o +lib-y += csum_partial.o fast-ratio.o memcpy.o memcpy-inatomic.o memset.o \ + strlen_user.o strncpy_user.o strnlen_user.o uncached.o obj-y += iomap.o obj-$(CONFIG_PCI) += iomap-pci.o @@ -29,5 +29,7 @@ obj-$(CONFIG_CPU_TX49XX) += dump_tlb.o obj-$(CONFIG_CPU_VR41XX) += dump_tlb.o obj-$(CONFIG_CPU_CAVIUM_OCTEON) += dump_tlb.o +obj-$(CONFIG_CP0_COUNT_NDELAY) += delay.o + # libgcc-style stuff needed in the kernel obj-y += ashldi3.o ashrdi3.o cmpdi2.o lshrdi3.o ucmpdi2.o Index: linux-2.6/arch/mips/lib/delay.c =================================================================== --- /dev/null +++ linux-2.6/arch/mips/lib/delay.c @@ -0,0 +1,59 @@ +/* + * delay.c + * + * Code implementing ndelay using the MIPS CP0 Count register. + * + * Copyright (C) 2009 Cisco Systems, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include + +/* This elements are initialized to a value that will cause huge delays to + * arise from use of ndelay before calling init_ndelay. This should make such + * mistakes obvious enough to easily find and correct. */ +struct fast_ratio _ndelay_param __read_mostly = { + .k = 0, + .s = 0, + .r = ULONG_MAX / 2, +}; +EXPORT_SYMBOL(_ndelay_param); + +/** + * Called to initialize the values for the ndelay function + * @f: Frequency, in KHz, of the CP0 Count register increment rate + */ +int __init init_ndelay(unsigned int f) +{ + int ret; + + ret = init_fast_ratio(_MAX_DIRECT_NDELAY, f, 1000000, &_ndelay_param); + + if (ret) + pr_err("Unable to initialize ndelay parameters, errno %d\n", + ret); + else + pr_info("Set ndelay fast_ratio parameters: k %lu s %d r %lu\n", + _ndelay_param.k, _ndelay_param.s, _ndelay_param.r); + + return ret; +} Index: linux-2.6/arch/mips/lib/fast-ratio.c =================================================================== --- /dev/null +++ linux-2.6/arch/mips/lib/fast-ratio.c @@ -0,0 +1,187 @@ +/* + * fast-ratio.c + * + * Code implementing fast ratio calculator. + * + * Copyright (C) 2009 Cisco Systems, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include + +#ifdef DEBUG +#define dbg(fmt, ...) pr_crit(fmt, ## __VA_ARGS__) +#else +#define dbg(fmt, ...) do { } while (0) +#endif + +#ifndef BITS_PER_LLONG +#define BITS_PER_LLONG ((BITS_PER_LONG * sizeof(long long)) / sizeof(long)) +#endif + +/* Type for intermediate calculations, along with the number of bits and + * the maximum size. This should be the biggest unsigned type for which + * division and modulus by unsigned long are defined on this + * architecture. */ +#ifdef CONFIG_HAVE_ULLONG_DIV_AND_MOD +typedef unsigned long long intermediate_t; +#define BITS_PER_ACC BITS_PER_LLONG +#define ACC_MAX ULLONG_MAX +#else +typedef unsigned long intermediate_t; +#define BITS_PER_ACC BITS_PER_LONG +#define ACC_MAX ULLONG_MAX +#endif + +/** + * Compute transform of equation (x * a)/b for fast computation + * @max_x: Maximum value of x + * @a: Value of a + * @b: value b + * @fr: Pointer to a &struct fast_ratio to hold transformed parameters + * Returns a zero on success, otherwise a negative errno value. Errno values + * are: + * -EDOM Parameter b is zero + * -EINVAL Either max_x is too large or max_x is zero + * -ERANGE The rounded up intermediate value of x * a would not fit + * in an unsigned long. + * + * Mathematically, as long as the ratios: + * a k + * - = --- + * b 2^s + * + * are equal, the specific values of k and s don't matter. There are + * two constraints, however: + * + * o The value of s must be less than BIT_PER_LONG + * o With a rounding constant of r = 2^s - 1, we must have + * x * k + r <= ULONG_MAX + * + * We want k to be as large as possible so that + * it has the maximum precision. Getting the largest k means + * getting the smallest shift. + * + * Note that this is designed to work on both 32-bit systems and 64-bit systems + * using the LP64 model. + */ +int init_fast_ratio(unsigned int max_x, unsigned long a, + unsigned long b, struct fast_ratio *fr) +{ +#define SHIFT_ROUND_UP(_v, _n) (((_n) < 0) ? \ + (((unsigned long long) (_v)) << -(_n)) : \ + (((_v) + ((1ull << (_n)) - 1)) >> (_n))) +#define ROUNDING_CONST(_s) (((_s) < 0) ? 0 : ((1ull << (_s)) - 1)) + intermediate_t scaled_a; + intermediate_t k0; + int s0; + int min_s; + int k_msb; + int s; + int si; + unsigned long long k; + unsigned long long r; + unsigned long long dividend; + + if (b == 0) + return -EDOM; /* Divide by zero */ + + if (max_x == 0) + return -EINVAL; + + if (a == 0) { + fr->k = 0; /* Trivial, result is always zero */ + fr->s = 0; + fr->r = 0; + return 0; + } + + /* Calculate the rounded up value of a / b with the most precision we + * can easily obtain by shifting the value a by n bits to the left. + * This means that the value we get is (a / b) * 2^n. We could get + * an overflow if we used the usual (a + (b - 1))/ b, so we compute the + * rounding value explicitly. If the scale value of a modulus b is + * not zero, we need to increase the result by one. */ + s0 = (BITS_PER_ACC - 1) - ilog2(a); + scaled_a = ((intermediate_t) a) << s0; + + k0 = (scaled_a / b) + ((scaled_a % b == 0) ? 0 : 1); + k_msb = ilog2(k0) + 1; + dbg("scaled_a %llx scaled_a %% b %llx k0 %llx s0 %d k_msb %d\n", + (unsigned long long) scaled_a, + (unsigned long long) scaled_a % b, + (unsigned long long) k0, s0, k_msb); + + /* Find a shift that yields the largest value of k that will avoid an + * overflow on an unsigned long when multiplied by max_x, and rounded + * up. */ + min_s = k_msb; + + for (;;) { + int shft; + unsigned long long ri; + unsigned long long ki; + unsigned long long p; + + shft = min_s - 1; + si = s0 - shft; + ki = SHIFT_ROUND_UP(k0, shft); + ri = ROUNDING_CONST(si); + + /* We must be sure that max_x is smaller than p or the + * following calculation will eventually overflow */ + BUG_ON(sizeof(max_x) > sizeof(p)); + p = max_x * ki; + dividend = p + ri; + dbg("min_s %d shft %d si %d ri %llx ki %llx max_x %x p %llx " + "dividend %llx\n", + min_s, shft, si, ri, ki, max_x, p, dividend); + if ((si > BITS_PER_LONG || dividend > ULONG_MAX)) + break; + min_s--; + } + + s = s0 - min_s; + k = SHIFT_ROUND_UP(k0, min_s); + r = ROUNDING_CONST(s); + dbg("min_s %d s %d k %llx max_x * k %llx r %llx dividend %llx\n", + min_s, s, k, max_x * k, r, max_x * k + r); + + /* If we have a negative shift, we couldn't find a k that would avoid + * an overflow. If that's true, or we have an overflow at the current + * shift, we return an error. */ + if (s < 0 || max_x * k + r > ULONG_MAX) + return -ERANGE; + + /* If the shift we came up with would shift the final result out + * of the register, we've underflowed the result */ + if (s >= BITS_PER_LONG) + return -ERANGE; + + fr->s = s; + fr->k = k; + fr->r = r; + + return 0; +#undef SHIFT_ROUND_UP +#undef ROUNDING_CONST +} From mano@roarinelk.homelinux.net Thu Mar 12 07:26:25 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 12 Mar 2009 07:26:36 +0000 (GMT) Received: from fnoeppeil36.netpark.at ([217.175.205.164]:23522 "EHLO roarinelk.homelinux.net") by ftp.linux-mips.org with ESMTP id S21103106AbZCLH0T (ORCPT ); Thu, 12 Mar 2009 07:26:19 +0000 Received: (qmail 32032 invoked by uid 1000); 12 Mar 2009 08:26:18 +0100 Date: Thu, 12 Mar 2009 08:26:18 +0100 From: Manuel Lauss To: Ralf Baechle Cc: linux-mips@linux-mips.org, Thomas Gleixner Subject: Re: __do_IRQ() going away Message-ID: <20090312072618.GA31978@roarinelk.homelinux.net> References: <20090311112806.GA24541@linux-mips.org> MIME-Version: 1.0 Content-Type: text/plain; charset=unknown-8bit Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20090311112806.GA24541@linux-mips.org> User-Agent: Mutt/1.5.16 (2007-06-09) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22065 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mano@roarinelk.homelinux.net Precedence: bulk X-list: linux-mips On Wed, Mar 11, 2009 at 12:28:06PM +0100, Ralf Baechle wrote: > __do_IRQ() is deprecated since a long time and there are plans to remove > it for 2.6.30. The MIPS platforms seem to fall into three classes: > o Platforms that still seem to rely on __do_IRQ(): > o All Alchemy platforms: > db1000_defconfig, db1100_defconfig, db1200_defconfig, db1500_defconfig, > db1550_defconfig, mtx1_defconfig, pb1100_defconfig, pb1500_defconfig > and pb1550_defconfig I believe that the defconfigs just need to be updated. There are no __do_IRQ invocations in the alchemy/ tree anymore, and generic hardirqs are enabled by CONFIG_SOC_AU1X00. Grsse, Manuel Lauss From ralf@h5.dl5rb.org.uk Thu Mar 12 09:28:14 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 12 Mar 2009 09:28:16 +0000 (GMT) Received: from localhost.localdomain ([127.0.0.1]:26813 "EHLO h5.dl5rb.org.uk") by ftp.linux-mips.org with ESMTP id S21070052AbZCLJ2O (ORCPT ); Thu, 12 Mar 2009 09:28:14 +0000 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id n2C9SCTV005215; Thu, 12 Mar 2009 10:28:12 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id n2C9SAGV005212; Thu, 12 Mar 2009 10:28:10 +0100 Date: Thu, 12 Mar 2009 10:28:10 +0100 From: Ralf Baechle To: Manuel Lauss Cc: linux-mips@linux-mips.org, Thomas Gleixner Subject: Re: __do_IRQ() going away Message-ID: <20090312092810.GA13674@linux-mips.org> References: <20090311112806.GA24541@linux-mips.org> <20090312072618.GA31978@roarinelk.homelinux.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20090312072618.GA31978@roarinelk.homelinux.net> User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22066 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Thu, Mar 12, 2009 at 08:26:18AM +0100, Manuel Lauss wrote: > > On Wed, Mar 11, 2009 at 12:28:06PM +0100, Ralf Baechle wrote: > > __do_IRQ() is deprecated since a long time and there are plans to remove > > it for 2.6.30. The MIPS platforms seem to fall into three classes: > > > o Platforms that still seem to rely on __do_IRQ(): > > o All Alchemy platforms: > > db1000_defconfig, db1100_defconfig, db1200_defconfig, db1500_defconfig, > > db1550_defconfig, mtx1_defconfig, pb1100_defconfig, pb1500_defconfig > > and pb1550_defconfig > > I believe that the defconfigs just need to be updated. There are no > __do_IRQ invocations in the alchemy/ tree anymore, and generic hardirqs are > enabled by CONFIG_SOC_AU1X00. __do_IRQ will be called from the generic code if irq_desc->handle_irq is not set for an interrupt and handle_irq will be left NULL if a platform only calls set_irq_chip or even does a homebrew initialization. Fix is to call set_irq_chip_and_handler or better set_irq_chip_and_handler_name. Iow, now with CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ always set half the platforms will blow up because the function pointer irq_desc->handle_irq is unset. Ralf From manuel.lauss@googlemail.com Thu Mar 12 09:46:30 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 12 Mar 2009 09:46:37 +0000 (GMT) Received: from fk-out-0910.google.com ([209.85.128.189]:36919 "EHLO fk-out-0910.google.com") by ftp.linux-mips.org with ESMTP id S20808485AbZCLJqa convert rfc822-to-8bit (ORCPT ); Thu, 12 Mar 2009 09:46:30 +0000 Received: by fk-out-0910.google.com with SMTP id 26so132035fkx.0 for ; Thu, 12 Mar 2009 02:46:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=gamma; h=domainkey-signature:mime-version:sender:received:in-reply-to :references:date:x-google-sender-auth:message-id:subject:from:to:cc :content-type:content-transfer-encoding; bh=1hrNyj4IZ0v6mfRIvJGd+UklS13/5PQ4B90OHM1DQ9g=; b=jWtduvZXkQZRZMX+639HiSJtNbwWDIVmncIRxVUWwu2/fjIuGnp02OGl+9sT+3tpcJ 2c0WJnH6fI5nb5/AHj2BPxx/QjpbXb4M75egomKfumXHTPKICAxEy6pWSJ0aMfOp4bYV +VwAJ5r1Y4mg/mLKPZZqvtTaVPIQhnVowaUXk= DomainKey-Signature: a=rsa-sha1; c=nofws; d=googlemail.com; s=gamma; h=mime-version:sender:in-reply-to:references:date :x-google-sender-auth:message-id:subject:from:to:cc:content-type :content-transfer-encoding; b=dTuyyQLMHFeU6zSP+vTquFgmqPczMxmi+At4W/qdEhzQ3GFeIMxDryq+6rSK77jf9p /WiHEVs4zh19nnN0b7VkFtl0u5jRsl4IGzp0z9Q7Y3rrQw00Nesi4ma5dc4djJWgDp1k 0jB+NagG/R8tCgrczDxLwrCeYxuG2N5NRIzrM= MIME-Version: 1.0 Received: by 10.103.226.10 with SMTP id d10mr4213628mur.84.1236851188977; Thu, 12 Mar 2009 02:46:28 -0700 (PDT) In-Reply-To: <20090312092810.GA13674@linux-mips.org> References: <20090311112806.GA24541@linux-mips.org> <20090312072618.GA31978@roarinelk.homelinux.net> <20090312092810.GA13674@linux-mips.org> Date: Thu, 12 Mar 2009 10:46:28 +0100 X-Google-Sender-Auth: ab5a8f71a642a2da Message-ID: Subject: Re: __do_IRQ() going away From: Manuel Lauss To: Ralf Baechle Cc: linux-mips@linux-mips.org, Thomas Gleixner Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22067 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mano@roarinelk.homelinux.net Precedence: bulk X-list: linux-mips On Thu, Mar 12, 2009 at 10:28 AM, Ralf Baechle wrote: > On Thu, Mar 12, 2009 at 08:26:18AM +0100, Manuel Lauss wrote: > >> >> On Wed, Mar 11, 2009 at 12:28:06PM +0100, Ralf Baechle wrote: >> > __do_IRQ() is deprecated since a long time and there are plans to remove >> > it for 2.6.30. The MIPS platforms seem to fall into three classes: >> >> > o Platforms that still seem to rely on __do_IRQ(): >> > o All Alchemy platforms: >> > db1000_defconfig, db1100_defconfig, db1200_defconfig, db1500_defconfig, >> > db1550_defconfig, mtx1_defconfig, pb1100_defconfig, pb1500_defconfig >> > and pb1550_defconfig >> >> I believe that the defconfigs just need to be updated. There are no >> __do_IRQ invocations in the alchemy/ tree anymore, and generic hardirqs are >> enabled by CONFIG_SOC_AU1X00. > > __do_IRQ will be called from the generic code if irq_desc->handle_irq is > not set for an interrupt and handle_irq will be left NULL if a platform > only calls set_irq_chip or even does a homebrew initialization. Fix is > to call set_irq_chip_and_handler or better set_irq_chip_and_handler_name. Alchemy does all that... > Iow, now with CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ always set half the > platforms will blow up because the function pointer irq_desc->handle_irq > is unset. ...and it works fine so far on the DB1200 and another 2 boards I have. (I.e. your patch didn't break anything). Unless I'm missing something very big. Manuel Lauss From r0bertz@gentoo.org Thu Mar 12 10:01:19 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 12 Mar 2009 10:01:25 +0000 (GMT) Received: from xylophone.i-cable.com ([203.83.115.99]:39649 "HELO xylophone.i-cable.com") by ftp.linux-mips.org with SMTP id S20808465AbZCLKBT (ORCPT ); Thu, 12 Mar 2009 10:01:19 +0000 Received: (qmail 2049 invoked by uid 508); 12 Mar 2009 10:01:12 -0000 Received: from 203.83.114.121 by xylophone (envelope-from , uid 505) with qmail-scanner-1.25 (clamdscan: 0.93.3/7737. Clear:RC:1(203.83.114.121):. Processed in 0.18152 secs); 12 Mar 2009 10:01:12 -0000 Received: from ip114121.hkicable.com (HELO silicon.i-cable.com) (203.83.114.121) by 0 with SMTP; 12 Mar 2009 10:01:12 -0000 Received: from localhost.localdomain (cm222-167-208-75.hkcable.com.hk [222.167.208.75]) by silicon.i-cable.com (8.13.5/8.13.5) with ESMTP id n2CA10tK023953; Thu, 12 Mar 2009 18:01:12 +0800 (HKT) From: Zhang Le To: linux-mips@linux-mips.org Cc: Zhang Le Subject: [PATCH] MIPS: fix TIF_32BIT undefined problem when seccomp is disabled Date: Thu, 12 Mar 2009 18:00:50 +0800 Message-Id: <1236852050-22266-1-git-send-email-r0bertz@gentoo.org> X-Mailer: git-send-email 1.6.2 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22068 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: r0bertz@gentoo.org Precedence: bulk X-list: linux-mips Signed-off-by: Zhang Le --- arch/mips/include/asm/seccomp.h | 4 ---- arch/mips/include/asm/thread_info.h | 6 ++++++ 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/arch/mips/include/asm/seccomp.h b/arch/mips/include/asm/seccomp.h index a6772e9..ae6306e 100644 --- a/arch/mips/include/asm/seccomp.h +++ b/arch/mips/include/asm/seccomp.h @@ -15,8 +15,6 @@ */ #ifdef CONFIG_MIPS32_O32 -#define TIF_32BIT TIF_32BIT_REGS - #define __NR_seccomp_read_32 4003 #define __NR_seccomp_write_32 4004 #define __NR_seccomp_exit_32 4001 @@ -24,8 +22,6 @@ #elif defined(CONFIG_MIPS32_N32) -#define TIF_32BIT _TIF_32BIT_ADDR - #define __NR_seccomp_read_32 6000 #define __NR_seccomp_write_32 6001 #define __NR_seccomp_exit_32 6058 diff --git a/arch/mips/include/asm/thread_info.h b/arch/mips/include/asm/thread_info.h index 3f76de7..676aa2a 100644 --- a/arch/mips/include/asm/thread_info.h +++ b/arch/mips/include/asm/thread_info.h @@ -127,6 +127,12 @@ register struct thread_info *__current_thread_info __asm__("$28"); #define TIF_LOAD_WATCH 25 /* If set, load watch registers */ #define TIF_SYSCALL_TRACE 31 /* syscall trace active */ +#ifdef CONFIG_MIPS32_O32 +#define TIF_32BIT TIF_32BIT_REGS +#elif defined(CONFIG_MIPS32_N32) +#define TIF_32BIT _TIF_32BIT_ADDR +#endif /* CONFIG_MIPS32_O32 */ + #define _TIF_SYSCALL_TRACE (1<); Thu, 12 Mar 2009 11:20:07 +0000 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id n2CBK4jW009053; Thu, 12 Mar 2009 12:20:05 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id n2CBK4Ox009051; Thu, 12 Mar 2009 12:20:04 +0100 Date: Thu, 12 Mar 2009 12:20:04 +0100 From: Ralf Baechle To: Manuel Lauss Cc: linux-mips@linux-mips.org, Thomas Gleixner Subject: Re: __do_IRQ() going away Message-ID: <20090312112004.GA6121@linux-mips.org> References: <20090311112806.GA24541@linux-mips.org> <20090312072618.GA31978@roarinelk.homelinux.net> <20090312092810.GA13674@linux-mips.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22069 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Thu, Mar 12, 2009 at 10:46:28AM +0100, Manuel Lauss wrote: > > Iow, now with CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ always set half the > > platforms will blow up because the function pointer irq_desc->handle_irq > > is unset. > > ...and it works fine so far on the DB1200 and another 2 boards I have. > (I.e. your patch didn't break anything). Unless I'm missing something > very big. Ah, there is a remaining call to set_irq_chip in the Alchemy code - but that seems to be in "does not happen" code so should be benign. Ralf From anemo@mba.ocn.ne.jp Thu Mar 12 16:19:51 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 12 Mar 2009 16:19:59 +0000 (GMT) Received: from mba.ocn.ne.jp ([122.1.235.107]:7152 "HELO smtp.mba.ocn.ne.jp") by ftp.linux-mips.org with SMTP id S21367622AbZCLQTv (ORCPT ); Thu, 12 Mar 2009 16:19:51 +0000 Received: from localhost (p7055-ipad304funabasi.chiba.ocn.ne.jp [123.217.161.55]) by smtp.mba.ocn.ne.jp (Postfix) with ESMTP id D8172A840; Fri, 13 Mar 2009 01:19:44 +0900 (JST) Date: Fri, 13 Mar 2009 01:19:50 +0900 (JST) Message-Id: <20090313.011950.61509382.anemo@mba.ocn.ne.jp> To: dan.j.williams@intel.com Cc: linux-mips@linux-mips.org, ralf@linux-mips.org, linux-kernel@vger.kernel.org, haavard.skinnemoen@atmel.com Subject: Re: [PATCH 1/2] dmaengine: TXx9 Soc DMA Controller driver From: Atsushi Nemoto In-Reply-To: <20090227.002436.106263719.anemo@mba.ocn.ne.jp> References: <1234538938-23479-1-git-send-email-anemo@mba.ocn.ne.jp> <20090227.002436.106263719.anemo@mba.ocn.ne.jp> X-Fingerprint: 6ACA 1623 39BD 9A94 9B1A B746 CA77 FE94 2874 D52F X-Pgp-Public-Key: http://wwwkeys.pgp.net/pks/lookup?op=get&search=0x2874D52F X-Mailer: Mew version 5.2 on Emacs 21.4 / Mule 5.0 (SAKAKI) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22070 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anemo@mba.ocn.ne.jp Precedence: bulk X-list: linux-mips On Fri, 27 Feb 2009 00:24:36 +0900 (JST), Atsushi Nemoto wrote: > > Can you explain how reserved channels work? It looks like you are > > working around the generic dma channel allocator, maybe it requires > > updating to meet your needs. ... > I need the reserved_chan to make channel 3 named "dma0chan3". If I > can chose chan_id for each channels in dma_device, the reserved_chan > is not needed. So, how about this? If it was accepted, I can remove reserved_chan from txx9dmac driver. ------------------------------------------------------ Subject: dmaengine: Use chan_id provided by DMA device driver From: Atsushi Nemoto If chan_id was already given by the DMA device driver, use it. Otherwise assign an incremental number for each channels. This allows the DMA device driver to reserve some channel ID numbers. Signed-off-by: Atsushi Nemoto --- diff --git a/drivers/dma/dmaengine.c b/drivers/dma/dmaengine.c index 280a9d2..a3679a7 100644 --- a/drivers/dma/dmaengine.c +++ b/drivers/dma/dmaengine.c @@ -609,6 +609,7 @@ EXPORT_SYMBOL(dmaengine_put); int dma_async_device_register(struct dma_device *device) { int chancnt = 0, rc; + unsigned int chan_id = 0; struct dma_chan* chan; atomic_t *idr_ref; @@ -663,7 +664,9 @@ int dma_async_device_register(struct dma_device *device) continue; } - chan->chan_id = chancnt++; + if (!chan->chan_id) + chan->chan_id = chan_id++; + chancnt++; chan->dev->device.class = &dma_devclass; chan->dev->device.parent = device->dev; chan->dev->chan = chan; From tsbogend@alpha.franken.de Fri Mar 13 09:29:15 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 13 Mar 2009 09:29:22 +0000 (GMT) Received: from elvis.franken.de ([193.175.24.41]:55473 "EHLO elvis.franken.de") by ftp.linux-mips.org with ESMTP id S20807695AbZCMJ3P (ORCPT ); Fri, 13 Mar 2009 09:29:15 +0000 Received: from uucp (helo=solo.franken.de) by elvis.franken.de with local-bsmtp (Exim 3.36 #1) id 1Li3ha-0001YX-00; Fri, 13 Mar 2009 10:29:14 +0100 Received: by solo.franken.de (Postfix, from userid 1000) id 2B1F2DE3ED; Fri, 13 Mar 2009 10:29:07 +0100 (CET) Date: Fri, 13 Mar 2009 10:29:07 +0100 To: VomLehn Cc: Linux MIPS Mailing List , Ralf Baechle Subject: Re: [PATCH][MIPS] Use CP0 Count register to implement more granular ndelay Message-ID: <20090313092906.GA6526@alpha.franken.de> References: <20090312032850.GA9379@cuplxvomd02.corp.sa.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20090312032850.GA9379@cuplxvomd02.corp.sa.net> User-Agent: Mutt/1.5.13 (2006-08-11) From: tsbogend@alpha.franken.de (Thomas Bogendoerfer) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22072 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: tsbogend@alpha.franken.de Precedence: bulk X-list: linux-mips Content-Length: 633 Lines: 29 On Wed, Mar 11, 2009 at 08:28:50PM -0700, VomLehn wrote: > # > +# Collect various processors by instruction family > +# > +config MIPS1 > + bool > + default y if CPU_R3000 || CPU_TX39XX > + > +config MIPS2 > + bool > + default y if CPU_R6000 > + > +config MIPS3 > + bool > + default y if CPU_LOONGSON2 || CPU_R4300 || CPU_R4X00 || CPU_TX49XX || \ > + CPU_VR41XX > + > +config MIPS4 > + bool > + default y if CPU_R8000 || CPU_R10000 > + what about all the R5k CPUs ? Thomas. -- Crap can work. Given enough thrust pigs will fly, but it's not necessary a good idea. [ RFC1925, 2.3 ] From ralf@h5.dl5rb.org.uk Fri Mar 13 11:32:43 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 13 Mar 2009 11:32:45 +0000 (GMT) Received: from localhost.localdomain ([127.0.0.1]:28863 "EHLO h5.dl5rb.org.uk") by ftp.linux-mips.org with ESMTP id S21102784AbZCMLcn (ORCPT ); Fri, 13 Mar 2009 11:32:43 +0000 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id n2DBWeHB023954; Fri, 13 Mar 2009 12:32:40 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id n2DBWcud023952; Fri, 13 Mar 2009 12:32:38 +0100 Date: Fri, 13 Mar 2009 12:32:38 +0100 From: Ralf Baechle To: Thomas Bogendoerfer Cc: VomLehn , Linux MIPS Mailing List Subject: Re: [PATCH][MIPS] Use CP0 Count register to implement more granular ndelay Message-ID: <20090313113238.GA30049@linux-mips.org> References: <20090312032850.GA9379@cuplxvomd02.corp.sa.net> <20090313092906.GA6526@alpha.franken.de> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20090313092906.GA6526@alpha.franken.de> User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22073 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Content-Length: 429 Lines: 15 On Fri, Mar 13, 2009 at 10:29:07AM +0100, Thomas Bogendoerfer wrote: > > +config MIPS4 > > + bool > > + default y if CPU_R8000 || CPU_R10000 > > + > > what about all the R5k CPUs ? There is cpu_has_counter which return if a processor actually has a cp0 counter. Also cpu_has_mfc0_count_bug() which indicates usability of the counter. The cp0 counter should rather not be used on early R4000 processors, for example. Ralf From anemo@mba.ocn.ne.jp Fri Mar 13 14:17:01 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 13 Mar 2009 14:17:08 +0000 (GMT) Received: from mba.ocn.ne.jp ([122.1.235.107]:6866 "HELO smtp.mba.ocn.ne.jp") by ftp.linux-mips.org with SMTP id S20808984AbZCMORB (ORCPT ); Fri, 13 Mar 2009 14:17:01 +0000 Received: from localhost (p3109-ipad301funabasi.chiba.ocn.ne.jp [122.17.253.109]) by smtp.mba.ocn.ne.jp (Postfix) with ESMTP id ED075A95A; Fri, 13 Mar 2009 23:16:53 +0900 (JST) Date: Fri, 13 Mar 2009 23:16:59 +0900 (JST) Message-Id: <20090313.231659.41197617.anemo@mba.ocn.ne.jp> To: dan.j.williams@intel.com Cc: linux-mips@linux-mips.org, ralf@linux-mips.org, linux-kernel@vger.kernel.org, haavard.skinnemoen@atmel.com Subject: Re: [PATCH 1/2] dmaengine: TXx9 Soc DMA Controller driver From: Atsushi Nemoto In-Reply-To: <20090313.011950.61509382.anemo@mba.ocn.ne.jp> References: <20090227.002436.106263719.anemo@mba.ocn.ne.jp> <20090313.011950.61509382.anemo@mba.ocn.ne.jp> X-Fingerprint: 6ACA 1623 39BD 9A94 9B1A B746 CA77 FE94 2874 D52F X-Pgp-Public-Key: http://wwwkeys.pgp.net/pks/lookup?op=get&search=0x2874D52F X-Mailer: Mew version 5.2 on Emacs 21.4 / Mule 5.0 (SAKAKI) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22074 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anemo@mba.ocn.ne.jp Precedence: bulk X-list: linux-mips Content-Length: 1559 Lines: 50 On Fri, 13 Mar 2009 01:19:50 +0900 (JST), Atsushi Nemoto wrote: > Subject: dmaengine: Use chan_id provided by DMA device driver > From: Atsushi Nemoto > > If chan_id was already given by the DMA device driver, use it. > Otherwise assign an incremental number for each channels. > > This allows the DMA device driver to reserve some channel ID numbers. ... > @@ -663,7 +664,9 @@ int dma_async_device_register(struct dma_device *device) > continue; > } > > - chan->chan_id = chancnt++; > + if (!chan->chan_id) > + chan->chan_id = chan_id++; > + chancnt++; > chan->dev->device.class = &dma_devclass; > chan->dev->device.parent = device->dev; > chan->dev->chan = chan; This patch will fix another potential problem. Some driver, for example ipu, assumes chan_id is an index of its internal array. But dmaengine core does not guarantee it. /* represent channels in sysfs. Probably want devs too */ list_for_each_entry(chan, &device->channels, device_node) { chan->local = alloc_percpu(typeof(*chan->local)); if (chan->local == NULL) continue; chan->dev = kzalloc(sizeof(*chan->dev), GFP_KERNEL); if (chan->dev == NULL) { free_percpu(chan->local); continue; } chan->chan_id = chancnt++; ... } device->chancnt = chancnt; If alloc_percpu or kzalloc failed, chan_id does not match with its position in device->channels list. And above "continue" looks buggy anyway. Keeping incomplete channels in device->channels list looks very dangerous... --- Atsushi Nemoto From skuribay@ruby.dti.ne.jp Fri Mar 13 15:31:47 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 13 Mar 2009 15:31:53 +0000 (GMT) Received: from smtp14.dti.ne.jp ([202.216.231.189]:15777 "EHLO smtp14.dti.ne.jp") by ftp.linux-mips.org with ESMTP id S20037526AbZCMPbr (ORCPT ); Fri, 13 Mar 2009 15:31:47 +0000 Received: from shinya-kuribayashis-macbook.local (PPPa360.tokyo-ip.dti.ne.jp [210.159.231.110]) by smtp14.dti.ne.jp (3.11s) with ESMTP AUTH id n2DFVXeE015241;Sat, 14 Mar 2009 00:31:33 +0900 (JST) Message-ID: <49BA7C55.5020600@ruby.dti.ne.jp> Date: Sat, 14 Mar 2009 00:31:33 +0900 From: Shinya Kuribayashi User-Agent: Thunderbird 2.0.0.19 (Macintosh/20081209) MIME-Version: 1.0 To: Ralf Baechle CC: linux-mips@linux-mips.org, Thomas Gleixner Subject: MIPS: EMMA2RH: Use handle_edge_irq() handler for GPIO interrupts References: <20090311112806.GA24541@linux-mips.org> In-Reply-To: <20090311112806.GA24541@linux-mips.org> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22075 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: skuribay@ruby.dti.ne.jp Precedence: bulk X-list: linux-mips Content-Length: 3467 Lines: 108 EMMA's GPIO interrupts are latched by GPIO interrupt status register. In this case, we're encouraged to use handle_edge_irq() handler. The following changes are made along with replacing set_irq_chip() with set_irq_chip_and_handler_name(,,handle_edge_irq,"edge"): * Fix emma2rh_gpio_irq_ack not to disable interrupts With handle_edge_irq(), we're not expected to disable interrupts when chip->ack is served, so fix it accordingly. We also add a new emma2rh_gpio_irq_mask_ack() for chip->mask_ack operation. * Remove emma2rh_gpio_irq_end() as chip->end is no longer served. Signed-off-by: Shinya Kuribayashi --- Ralf Baechle wrote: > __do_IRQ() is deprecated since a long time and there are plans to remove > it for 2.6.30. The MIPS platforms seem to fall into three classes: [snip] > o Platforms that still seem to rely on __do_IRQ(): > o All Sibyte platforms: > bigsur_defconfig and sb1250-swarm_defconfig > > o All Alchemy platforms: > db1000_defconfig, db1100_defconfig, db1200_defconfig, db1500_defconfig, > db1550_defconfig, mtx1_defconfig, pb1100_defconfig, pb1500_defconfig > and pb1550_defconfig > > o malta_defconfig. The platform code itself is ok but irq-gic.c, > irq-msc01.c, irq-msc01.c and irq_cpu.c are still using set_irq_chip > and need fixing. > > o And the rest: > decstation_defconfig, emma2rh_defconfig, ip32_defconfig, > yosemite_defconfig, mipssim_defconfig and rm200_defconfig. Here's a patch for EMMA2RH not to call __do_IRQ(). Please review. Thanks, Shinya arch/mips/emma/markeins/irq.c | 28 ++++++++++------------------ 1 files changed, 10 insertions(+), 18 deletions(-) diff --git a/arch/mips/emma/markeins/irq.c b/arch/mips/emma/markeins/irq.c index ce8f5f2..d15556c 100644 --- a/arch/mips/emma/markeins/irq.c +++ b/arch/mips/emma/markeins/irq.c @@ -149,37 +149,28 @@ static void emma2rh_gpio_irq_disable(unsigned int irq) static void emma2rh_gpio_irq_ack(unsigned int irq) { - u32 reg; - irq -= EMMA2RH_GPIO_IRQ_BASE; emma2rh_out32(EMMA2RH_GPIO_INT_ST, ~(1 << irq)); - - reg = emma2rh_in32(EMMA2RH_GPIO_INT_MASK); - reg &= ~(1 << irq); - emma2rh_out32(EMMA2RH_GPIO_INT_MASK, reg); } -static void emma2rh_gpio_irq_end(unsigned int irq) +static void emma2rh_gpio_irq_mask_ack(unsigned int irq) { u32 reg; - if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) { - - irq -= EMMA2RH_GPIO_IRQ_BASE; + irq -= EMMA2RH_GPIO_IRQ_BASE; + emma2rh_out32(EMMA2RH_GPIO_INT_ST, ~(1 << irq)); - reg = emma2rh_in32(EMMA2RH_GPIO_INT_MASK); - reg |= 1 << irq; - emma2rh_out32(EMMA2RH_GPIO_INT_MASK, reg); - } + reg = emma2rh_in32(EMMA2RH_GPIO_INT_MASK); + reg &= ~(1 << irq); + emma2rh_out32(EMMA2RH_GPIO_INT_MASK, reg); } struct irq_chip emma2rh_gpio_irq_controller = { .name = "emma2rh_gpio_irq", .ack = emma2rh_gpio_irq_ack, .mask = emma2rh_gpio_irq_disable, - .mask_ack = emma2rh_gpio_irq_ack, + .mask_ack = emma2rh_gpio_irq_mask_ack, .unmask = emma2rh_gpio_irq_enable, - .end = emma2rh_gpio_irq_end, }; void emma2rh_gpio_irq_init(void) @@ -187,8 +178,9 @@ void emma2rh_gpio_irq_init(void) u32 i; for (i = 0; i < NUM_EMMA2RH_IRQ_GPIO; i++) - set_irq_chip(EMMA2RH_GPIO_IRQ_BASE + i, - &emma2rh_gpio_irq_controller); + set_irq_chip_and_handler_name(EMMA2RH_GPIO_IRQ_BASE + i, + &emma2rh_gpio_irq_controller, + handle_edge_irq, "edge"); } static struct irqaction irq_cascade = { From dvomlehn@cisco.com Fri Mar 13 17:35:26 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 13 Mar 2009 17:35:31 +0000 (GMT) Received: from sj-iport-1.cisco.com ([171.71.176.70]:2698 "EHLO sj-iport-1.cisco.com") by ftp.linux-mips.org with ESMTP id S21102772AbZCMRf0 (ORCPT ); Fri, 13 Mar 2009 17:35:26 +0000 X-IronPort-AV: E=Sophos;i="4.38,358,1233532800"; d="scan'208";a="155500045" Received: from sj-dkim-1.cisco.com ([171.71.179.21]) by sj-iport-1.cisco.com with ESMTP; 13 Mar 2009 17:35:18 +0000 Received: from sj-core-2.cisco.com (sj-core-2.cisco.com [171.71.177.254]) by sj-dkim-1.cisco.com (8.12.11/8.12.11) with ESMTP id n2DHZIf5027080; Fri, 13 Mar 2009 10:35:18 -0700 Received: from cliff.cisco.com (cliff.cisco.com [171.69.11.141]) by sj-core-2.cisco.com (8.13.8/8.13.8) with ESMTP id n2DHZIrP007784; Fri, 13 Mar 2009 17:35:18 GMT Received: from cuplxvomd02.corp.sa.net ([64.101.20.155]) by cliff.cisco.com (8.6.12/8.6.5) with ESMTP id RAA22951; Fri, 13 Mar 2009 17:35:17 GMT Date: Fri, 13 Mar 2009 10:35:17 -0700 From: VomLehn To: Thomas Bogendoerfer Cc: Linux MIPS Mailing List , Ralf Baechle Subject: Re: [PATCH][MIPS] Use CP0 Count register to implement more granular ndelay Message-ID: <20090313173517.GA25355@cuplxvomd02.corp.sa.net> References: <20090312032850.GA9379@cuplxvomd02.corp.sa.net> <20090313092906.GA6526@alpha.franken.de> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20090313092906.GA6526@alpha.franken.de> User-Agent: Mutt/1.5.18 (2008-05-17) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; l=682; t=1236965718; x=1237829718; c=relaxed/simple; s=sjdkim1004; h=Content-Type:From:Subject:Content-Transfer-Encoding:MIME-Version; d=cisco.com; i=dvomlehn@cisco.com; z=From:=20VomLehn=20 |Subject:=20Re=3A=20[PATCH][MIPS]=20Use=20CP0=20Count=20reg ister=20to=20implement=20more=0A=09granular=20ndelay |Sender:=20; bh=n3QdEWEVP7gSMvXs0S30038vmvSBRdo0R5umiJ5Twhg=; b=U+n2qriiY3NC1eol+pf1qejtYaQP0nXCy7uNaj7cp+9gH1dg5UhUJmgX4G 54BClFsK5FClrB/SoyhfHHmwMZJwxVZoQrb5jBTu1pcg0Q8WAHSpHOq1s0oX Eq//kWi6RZUzIpq8lvBZ4/STMp1/0MdEcl7qu3U6Pus74w4Sd8/D8=; Authentication-Results: sj-dkim-1; header.From=dvomlehn@cisco.com; dkim=pass ( sig from cisco.com/sjdkim1004 verified; ); Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22076 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dvomlehn@cisco.com Precedence: bulk X-list: linux-mips Content-Length: 656 Lines: 26 On Fri, Mar 13, 2009 at 10:29:07AM +0100, Thomas Bogendoerfer wrote: > On Wed, Mar 11, 2009 at 08:28:50PM -0700, VomLehn wrote: > > # > > +# Collect various processors by instruction family > > +# > > +config MIPS1 > > + bool > > + default y if CPU_R3000 || CPU_TX39XX > > + > > +config MIPS2 > > + bool > > + default y if CPU_R6000 > > + > > +config MIPS3 > > + bool > > + default y if CPU_LOONGSON2 || CPU_R4300 || CPU_R4X00 || CPU_TX49XX || \ > > + CPU_VR41XX > > + > > +config MIPS4 > > + bool > > + default y if CPU_R8000 || CPU_R10000 > > + > > what about all the R5k CPUs ? Excellent question. What are their names and what is their ISA called? From ralf@h5.dl5rb.org.uk Fri Mar 13 23:00:58 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 13 Mar 2009 23:01:00 +0000 (GMT) Received: from localhost.localdomain ([127.0.0.1]:49043 "EHLO h5.dl5rb.org.uk") by ftp.linux-mips.org with ESMTP id S20808521AbZCMXA6 (ORCPT ); Fri, 13 Mar 2009 23:00:58 +0000 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id n2DN0rOo031553; Sat, 14 Mar 2009 00:00:55 +0100 Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id n2DN0n3l031550; Sat, 14 Mar 2009 00:00:49 +0100 Date: Sat, 14 Mar 2009 00:00:49 +0100 From: Ralf Baechle To: Jan Nikitenko Cc: linux-mips@linux-mips.org, Atsushi Nemoto Subject: Re: fix oops in dma_unmap_page on not coherent mips platforms Message-ID: <20090313230049.GA30319@linux-mips.org> References: <20081128075258.GA10200@nikitenko.systek.local> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20081128075258.GA10200@nikitenko.systek.local> User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22077 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Content-Length: 322 Lines: 10 > dma_cache_wback_inv() expects virtual address, but physical was provided > due to translation via plat_dma_addr_to_phys(). > If replaced with dma_addr_to_virt(), page fault oops from dma_unmap_page() > is gone on au1550 platform. > > Signed-off-by: Jan Nikitenko Applied, finally ... Ralf From umeshyv@gmail.com Sat Mar 14 11:52:35 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 14 Mar 2009 11:52:42 +0000 (GMT) Received: from wf-out-1314.google.com ([209.85.200.174]:17307 "EHLO wf-out-1314.google.com") by ftp.linux-mips.org with ESMTP id S20808138AbZCNLwf (ORCPT ); Sat, 14 Mar 2009 11:52:35 +0000 Received: by wf-out-1314.google.com with SMTP id 25so2257535wfc.21 for ; Sat, 14 Mar 2009 04:52:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:date:message-id:subject :from:to:content-type; bh=AEHLPfuibQn3a0F+4DGDWzZzB/N3h4PrJUuXZrY7Co4=; b=NXL0D4GvXMgmTU+50+byqDRGeXh6x13VXM/T6b8a4oZQ7XHI++bAqoYIASdtQnAxm1 k9Qk/SaVk2GajoScfF6xBeEEiQrPQQMi8F2JLxlysPV9Q7UofdjXuTftJhwcKefcgulR ET8Y+XAt0641651pxhK7MGTwesFTLy6ULbJ40= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:date:message-id:subject:from:to:content-type; b=w/Blp2CD7o83BDXAKOZiYmjEimjv0jkYzfbMqproY5oDlyrhz10zmUudFbhC5EnYKx 84kTwaayiwNNO1ng7H4A1p73zy8Qrvh6wBy3QpYnTCrJUzTcp+dtxUf72ILkX+30TikS VfXf8OUo8bujrFDb5kg8/Ok7fPdYfHfAGhPWo= MIME-Version: 1.0 Received: by 10.143.2.19 with SMTP id e19mr1122435wfi.96.1237031553597; Sat, 14 Mar 2009 04:52:33 -0700 (PDT) Date: Sat, 14 Mar 2009 17:22:33 +0530 Message-ID: Subject: linux-2.6.28.4 regarding From: umeshyv To: linux-mips@linux-mips.org Content-Type: multipart/alternative; boundary=001636e0b56a53ffd6046512dab4 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22078 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: umeshyv@gmail.com Precedence: bulk X-list: linux-mips Content-Length: 831 Lines: 24 --001636e0b56a53ffd6046512dab4 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Hi to all, I downloaded latest kernel for mips (linux-2.6.28.4).How do I configure Asoc driver(wm8731 codec,I2S based) for DbAu1200 development board.Please guide me with your valuable suggestions.waiting for your valuable reply Thanks & Regards Umamahesh Y V --001636e0b56a53ffd6046512dab4 Content-Type: text/html; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Hi to all,
I downloaded latest kernel for mips (linux-2.6.28.4).How do I= configure Asoc driver(wm8731 codec,I2S based)=A0 for DbAu1200 development = board.Please guide me=A0 with your valuable suggestions.waiting for your va= luable reply


Thanks & Regards
Umamahesh Y=A0 V
--001636e0b56a53ffd6046512dab4-- From anemo@mba.ocn.ne.jp Sat Mar 14 16:17:47 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 14 Mar 2009 16:17:53 +0000 (GMT) Received: from mba.ocn.ne.jp ([122.1.235.107]:1530 "HELO smtp.mba.ocn.ne.jp") by ftp.linux-mips.org with SMTP id S21367734AbZCNQRr (ORCPT ); Sat, 14 Mar 2009 16:17:47 +0000 Received: from localhost (p7238-ipad212funabasi.chiba.ocn.ne.jp [58.91.171.238]) by smtp.mba.ocn.ne.jp (Postfix) with ESMTP id 9DB77B5A7; Sun, 15 Mar 2009 01:17:40 +0900 (JST) Date: Sun, 15 Mar 2009 01:17:48 +0900 (JST) Message-Id: <20090315.011748.128619265.anemo@mba.ocn.ne.jp> To: ralf@linux-mips.org Cc: jan.nikitenko@gmail.com, linux-mips@linux-mips.org Subject: Re: fix oops in dma_unmap_page on not coherent mips platforms From: Atsushi Nemoto In-Reply-To: <20090313230049.GA30319@linux-mips.org> References: <20081128075258.GA10200@nikitenko.systek.local> <20090313230049.GA30319@linux-mips.org> X-Fingerprint: 6ACA 1623 39BD 9A94 9B1A B746 CA77 FE94 2874 D52F X-Pgp-Public-Key: http://wwwkeys.pgp.net/pks/lookup?op=get&search=0x2874D52F X-Mailer: Mew version 5.2 on Emacs 21.4 / Mule 5.0 (SAKAKI) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22079 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anemo@mba.ocn.ne.jp Precedence: bulk X-list: linux-mips Content-Length: 590 Lines: 17 On Sat, 14 Mar 2009 00:00:49 +0100, Ralf Baechle wrote: > > dma_cache_wback_inv() expects virtual address, but physical was provided > > due to translation via plat_dma_addr_to_phys(). > > If replaced with dma_addr_to_virt(), page fault oops from dma_unmap_page() > > is gone on au1550 platform. > > > > Signed-off-by: Jan Nikitenko > > Applied, finally ... Good news! And please take a look at this too: http://www.linux-mips.org/cgi-bin/mesg.cgi?a=linux-mips&i=1232638931-6203-1-git-send-email-anemo%40mba.ocn.ne.jp --- Atsushi Nemoto From ori@helicontech.co.il Sun Mar 15 09:23:36 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 15 Mar 2009 09:23:44 +0000 (GMT) Received: from mail-ew0-f180.google.com ([209.85.219.180]:38652 "EHLO mail-ew0-f180.google.com") by ftp.linux-mips.org with ESMTP id S20808875AbZCOJXg (ORCPT ); Sun, 15 Mar 2009 09:23:36 +0000 Received: by ewy28 with SMTP id 28so3396415ewy.0 for ; Sun, 15 Mar 2009 02:23:30 -0700 (PDT) MIME-Version: 1.0 Received: by 10.216.39.85 with SMTP id c63mr1385897web.103.1237109010733; Sun, 15 Mar 2009 02:23:30 -0700 (PDT) Date: Sun, 15 Mar 2009 11:23:30 +0200 Message-ID: <26d57bbb0903150223u7e0cc8bcl28e011f8fea9aa6c@mail.gmail.com> Subject: Printing register value inside kernel panic From: Ori Idan To: linux-mips@linux-mips.org Content-Type: multipart/alternative; boundary=0016365ee476221c35046524e301 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22080 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ori@helicontech.co.il Precedence: bulk X-list: linux-mips Content-Length: 725 Lines: 19 --0016365ee476221c35046524e301 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit I would like to print register values using the function show_registers (defined in traps.c), this function needs a struct pt_regs as a parameter and I have no idea how to fill values inside this struct -- Ori Idan --0016365ee476221c35046524e301 Content-Type: text/html; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit
I would like to print register values using the function show_registers (defined in traps.c), this function needs a struct pt_regs as a parameter and I have no idea how to fill values inside this struct

--
Ori Idan

--0016365ee476221c35046524e301-- From rusty@rustcorp.com.au Mon Mar 16 04:14:45 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 16 Mar 2009 04:14:52 +0000 (GMT) Received: from ozlabs.org ([203.10.76.45]:19606 "EHLO ozlabs.org") by ftp.linux-mips.org with ESMTP id S21365595AbZCPEOp (ORCPT ); Mon, 16 Mar 2009 04:14:45 +0000 Received: from vivaldi.localnet (unknown [150.101.102.135]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPSA id 5785BDDF96; Mon, 16 Mar 2009 15:14:38 +1100 (EST) Subject: [PULL] cpumask updates for mips From: Rusty Russell To: Ralf Baechle Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, mingo@redhat.com, travis@sgi.com CC: linux-kernel@vger.kernel.org CC: mingo@redhat.com CC: travis@sgi.com Date: Mon, 16 Mar 2009 14:44:32 +1030 MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Content-Disposition: inline Message-Id: <200903161444.33255.rusty@rustcorp.com.au> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22081 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: rusty@rustcorp.com.au Precedence: bulk X-list: linux-mips Content-Length: 19713 Lines: 555 The following changes since commit 5bee17f18b595937e6beafeee5197868a3f74a06: Kyle McMartin (1): parisc: sba_iommu: fix build bug when CONFIG_PARISC_AGP=y are available in the git repository at: ssh://master.kernel.org/home/ftp/pub/scm/linux/kernel/git/rusty/linux-2.6-cpumask-for-mips.git master Rusty Russell (6): cpumask: remove the now-obsoleted pcibus_to_cpumask(): mips cpumask: arch_send_call_function_ipi_mask: mips cpumask: prepare for iterators to only go to nr_cpu_ids/nr_cpumask_bits.: mips cpumask: Use accessors code.: mips cpumask: remove dangerous CPU_MASK_ALL_PTR, &CPU_MASK_ALL.: mips cpumask: use mm_cpumask() wrapper: mips arch/mips/alchemy/common/time.c | 2 +- arch/mips/include/asm/mach-ip27/topology.h | 1 - arch/mips/include/asm/mmu_context.h | 10 +++++----- arch/mips/include/asm/smp-ops.h | 2 +- arch/mips/include/asm/smp.h | 3 ++- arch/mips/kernel/irq-gic.c | 2 +- arch/mips/kernel/proc.c | 2 +- arch/mips/kernel/smp-cmp.c | 11 +++++++---- arch/mips/kernel/smp-mt.c | 4 ++-- arch/mips/kernel/smp-up.c | 3 ++- arch/mips/kernel/smp.c | 4 ++-- arch/mips/kernel/smtc.c | 6 +++--- arch/mips/mipssim/sim_smtc.c | 5 +++-- arch/mips/mm/c-octeon.c | 2 +- arch/mips/mti-malta/malta-smtc.c | 4 ++-- arch/mips/pmc-sierra/yosemite/smp.c | 4 ++-- arch/mips/sgi-ip27/ip27-smp.c | 4 ++-- arch/mips/sibyte/bcm1480/irq.c | 2 +- arch/mips/sibyte/bcm1480/smp.c | 7 ++++--- arch/mips/sibyte/sb1250/smp.c | 7 ++++--- 20 files changed, 46 insertions(+), 39 deletions(-) commit 0656e33655680d82e06a5fb2941d5cce8b959b17 Author: Rusty Russell Date: Mon Mar 16 14:17:24 2009 +1030 cpumask: use mm_cpumask() wrapper: mips Makes code futureproof against the impending change to mm->cpu_vm_mask. It's also a chance to use the new cpumask_ ops which take a pointer (the older ones are deprecated, but there's no hurry for arch code). Signed-off-by: Rusty Russell diff --git a/arch/mips/include/asm/mmu_context.h b/arch/mips/include/asm/mmu_context.h index d7f3eb0..7f8204c 100644 --- a/arch/mips/include/asm/mmu_context.h +++ b/arch/mips/include/asm/mmu_context.h @@ -177,8 +177,8 @@ static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next, * Mark current->active_mm as not "active" anymore. * We don't want to mislead possible IPI tlb flush routines. */ - cpu_clear(cpu, prev->cpu_vm_mask); - cpu_set(cpu, next->cpu_vm_mask); + cpumask_clear_cpu(cpu, mm_cpumask(prev)); + cpumask_set_cpu(cpu, mm_cpumask(next)); local_irq_restore(flags); } @@ -234,8 +234,8 @@ activate_mm(struct mm_struct *prev, struct mm_struct *next) TLBMISS_HANDLER_SETUP_PGD(next->pgd); /* mark mmu ownership change */ - cpu_clear(cpu, prev->cpu_vm_mask); - cpu_set(cpu, next->cpu_vm_mask); + cpumask_clear_cpu(cpu, mm_cpumask(prev)); + cpumask_set_cpu(cpu, mm_cpumask(next)); local_irq_restore(flags); } @@ -257,7 +257,7 @@ drop_mmu_context(struct mm_struct *mm, unsigned cpu) local_irq_save(flags); - if (cpu_isset(cpu, mm->cpu_vm_mask)) { + if (cpumask_test_cpu(cpu, mm_cpumask(mm))) { get_new_mmu_context(mm, cpu); #ifdef CONFIG_MIPS_MT_SMTC /* See comments for similar code above */ diff --git a/arch/mips/mm/c-octeon.c b/arch/mips/mm/c-octeon.c index 44d01a0..9e06a31 100644 --- a/arch/mips/mm/c-octeon.c +++ b/arch/mips/mm/c-octeon.c @@ -78,7 +78,7 @@ static void octeon_flush_icache_all_cores(struct vm_area_struct *vma) * cores it has been used on */ if (vma) - mask = vma->vm_mm->cpu_vm_mask; + mask = *mm_cpumask(vma->vm_mm); else mask = cpu_online_map; cpu_clear(cpu, mask); commit 3c2f65bfe709f6cc9290a181c6fd55560c2105a3 Author: Rusty Russell Date: Mon Mar 16 14:17:23 2009 +1030 cpumask: remove dangerous CPU_MASK_ALL_PTR, &CPU_MASK_ALL.: mips Impact: cleanup (Thanks to Al Viro for reminding me of this, via Ingo) CPU_MASK_ALL is the (deprecated) "all bits set" cpumask, defined as so: #define CPU_MASK_ALL (cpumask_t) { { ... } } Taking the address of such a temporary is questionable at best, unfortunately 321a8e9d (cpumask: add CPU_MASK_ALL_PTR macro) added CPU_MASK_ALL_PTR: #define CPU_MASK_ALL_PTR (&CPU_MASK_ALL) Which formalizes this practice. One day gcc could bite us over this usage (though we seem to have gotten away with it so far). So replace everywhere which used &CPU_MASK_ALL or CPU_MASK_ALL_PTR with the modern "cpu_all_mask" (a real struct cpumask *), and remove CPU_MASK_ALL_PTR altogether. Signed-off-by: Rusty Russell Acked-by: Ingo Molnar Reported-by: Al Viro Cc: Mike Travis diff --git a/arch/mips/alchemy/common/time.c b/arch/mips/alchemy/common/time.c index f58d4ff..e653513 100644 --- a/arch/mips/alchemy/common/time.c +++ b/arch/mips/alchemy/common/time.c @@ -89,7 +89,7 @@ static struct clock_event_device au1x_rtcmatch2_clockdev = { .irq = AU1000_RTC_MATCH2_INT, .set_next_event = au1x_rtcmatch2_set_next_event, .set_mode = au1x_rtcmatch2_set_mode, - .cpumask = CPU_MASK_ALL_PTR, + .cpumask = cpu_all_mask, }; static struct irqaction au1x_rtcmatch2_irqaction = { commit 982de1f1ed0908953a115bb1f45abd7c10e0e218 Author: Rusty Russell Date: Mon Mar 16 14:17:23 2009 +1030 cpumask: Use accessors code.: mips Impact: use new API Use the accessors rather than frobbing bits directly. Most of this is in arch code I haven't even compiled, but is straightforward. Signed-off-by: Rusty Russell Signed-off-by: Mike Travis diff --git a/arch/mips/kernel/smp-cmp.c b/arch/mips/kernel/smp-cmp.c index 725e455..efa2016 100644 --- a/arch/mips/kernel/smp-cmp.c +++ b/arch/mips/kernel/smp-cmp.c @@ -53,7 +53,10 @@ static int __init allowcpus(char *str) cpus_clear(cpu_allow_map); if (cpulist_parse(str, &cpu_allow_map) == 0) { cpu_set(0, cpu_allow_map); - cpus_and(cpu_possible_map, cpu_possible_map, cpu_allow_map); + unsigned int i; + for (i = 1; i < nr_cpu_ids; i++) + if (!cpumask_test_cpu(i, cpu_allow_map)) + set_cpu_possible(i, false); len = cpulist_scnprintf(buf, sizeof(buf)-1, &cpu_possible_map); buf[len] = '\0'; pr_debug("Allowable CPUs: %s\n", buf); diff --git a/arch/mips/kernel/smp.c b/arch/mips/kernel/smp.c index 664ba8c..5b97ca3 100644 --- a/arch/mips/kernel/smp.c +++ b/arch/mips/kernel/smp.c @@ -183,7 +183,7 @@ void __init smp_prepare_cpus(unsigned int max_cpus) mp_ops->prepare_cpus(max_cpus); set_cpu_sibling_map(0); #ifndef CONFIG_HOTPLUG_CPU - cpu_present_map = cpu_possible_map; + init_cpu_present(&cpu_possible_map); #endif } commit 9e1d1737d800c4d90a64804b5eb2798cbcc5e114 Author: Rusty Russell Date: Mon Mar 16 14:17:22 2009 +1030 cpumask: prepare for iterators to only go to nr_cpu_ids/nr_cpumask_bits.: mips Impact: cleanup, futureproof In fact, all cpumask ops will only be valid (in general) for bit numbers < nr_cpu_ids. So use that instead of NR_CPUS in various places. This is always safe: no cpu number can be >= nr_cpu_ids, and nr_cpu_ids is initialized to NR_CPUS at boot. Signed-off-by: Rusty Russell Signed-off-by: Mike Travis Acked-by: Ingo Molnar diff --git a/arch/mips/kernel/irq-gic.c b/arch/mips/kernel/irq-gic.c index 494a49a..232f8fb 100644 --- a/arch/mips/kernel/irq-gic.c +++ b/arch/mips/kernel/irq-gic.c @@ -182,7 +182,7 @@ static void gic_set_affinity(unsigned int irq, const struct cpumask *cpumask) _intrmap[irq].cpunum = first_cpu(tmp); /* Update the pcpu_masks */ - for (i = 0; i < NR_CPUS; i++) + for (i = 0; i < nr_cpu_ids; i++) clear_bit(irq, pcpu_masks[i].pcpu_mask); set_bit(irq, pcpu_masks[first_cpu(tmp)].pcpu_mask); diff --git a/arch/mips/kernel/proc.c b/arch/mips/kernel/proc.c index 26760ca..f362c95 100644 --- a/arch/mips/kernel/proc.c +++ b/arch/mips/kernel/proc.c @@ -86,7 +86,7 @@ static void *c_start(struct seq_file *m, loff_t *pos) { unsigned long i = *pos; - return i < NR_CPUS ? (void *) (i + 1) : NULL; + return i < nr_cpu_ids ? (void *) (i + 1) : NULL; } static void *c_next(struct seq_file *m, void *v, loff_t *pos) diff --git a/arch/mips/kernel/smp-cmp.c b/arch/mips/kernel/smp-cmp.c index 44b25cf..725e455 100644 --- a/arch/mips/kernel/smp-cmp.c +++ b/arch/mips/kernel/smp-cmp.c @@ -224,7 +224,7 @@ void __init cmp_smp_setup(void) cpu_set(0, mt_fpu_cpumask); #endif /* CONFIG_MIPS_MT_FPAFF */ - for (i = 1; i < NR_CPUS; i++) { + for (i = 1; i < nr_cpu_ids; i++) { if (amon_cpu_avail(i)) { cpu_set(i, cpu_possible_map); __cpu_number_map[i] = ++ncpu; diff --git a/arch/mips/kernel/smtc.c b/arch/mips/kernel/smtc.c index b6cca01..047cefd 100644 --- a/arch/mips/kernel/smtc.c +++ b/arch/mips/kernel/smtc.c @@ -422,8 +422,8 @@ void smtc_prepare_cpus(int cpus) if (vpelimit > 0 && nvpe > vpelimit) nvpe = vpelimit; ntc = ((val & MVPCONF0_PTC) >> MVPCONF0_PTC_SHIFT) + 1; - if (ntc > NR_CPUS) - ntc = NR_CPUS; + if (ntc > nr_cpu_ids) + ntc = nr_cpu_ids; if (tclimit > 0 && ntc > tclimit) ntc = tclimit; slop = ntc % nvpe; @@ -701,7 +701,7 @@ void smtc_forward_irq(unsigned int irq) */ /* If no one is eligible, service locally */ - if (target >= NR_CPUS) { + if (target >= nr_cpu_ids) { do_IRQ_no_affinity(irq); return; } diff --git a/arch/mips/sibyte/bcm1480/irq.c b/arch/mips/sibyte/bcm1480/irq.c index 12b465d..e89ae4c 100644 --- a/arch/mips/sibyte/bcm1480/irq.c +++ b/arch/mips/sibyte/bcm1480/irq.c @@ -195,7 +195,7 @@ static void ack_bcm1480_irq(unsigned int irq) if (pending) { #ifdef CONFIG_SMP int i; - for (i=0; i Date: Mon Mar 16 14:17:21 2009 +1030 cpumask: arch_send_call_function_ipi_mask: mips We're weaning the core code off handing cpumask's around on-stack. This introduces arch_send_call_function_ipi_mask(), and by defining it, the old arch_send_call_function_ipi is defined by the core code. We also take the chance to wean the implementations off the obsolescent for_each_cpu_mask(): making send_ipi_mask take the pointer seemed the most natural way to ensure all implementations used for_each_cpu. Signed-off-by: Rusty Russell diff --git a/arch/mips/include/asm/smp-ops.h b/arch/mips/include/asm/smp-ops.h index 43c207e..5f28881 100644 --- a/arch/mips/include/asm/smp-ops.h +++ b/arch/mips/include/asm/smp-ops.h @@ -17,7 +17,7 @@ struct plat_smp_ops { void (*send_ipi_single)(int cpu, unsigned int action); - void (*send_ipi_mask)(cpumask_t mask, unsigned int action); + void (*send_ipi_mask)(const struct cpumask *mask, unsigned int action); void (*init_secondary)(void); void (*smp_finish)(void); void (*cpus_done)(void); diff --git a/arch/mips/include/asm/smp.h b/arch/mips/include/asm/smp.h index 40e5ef1..0483444 100644 --- a/arch/mips/include/asm/smp.h +++ b/arch/mips/include/asm/smp.h @@ -58,6 +58,7 @@ static inline void smp_send_reschedule(int cpu) extern asmlinkage void smp_call_function_interrupt(void); extern void arch_send_call_function_single_ipi(int cpu); -extern void arch_send_call_function_ipi(cpumask_t mask); +extern void arch_send_call_function_ipi_mask(const struct cpumask *mask); +#define arch_send_call_function_ipi_mask arch_send_call_function_ipi_mask #endif /* __ASM_SMP_H */ diff --git a/arch/mips/kernel/smp-cmp.c b/arch/mips/kernel/smp-cmp.c index f27beca..44b25cf 100644 --- a/arch/mips/kernel/smp-cmp.c +++ b/arch/mips/kernel/smp-cmp.c @@ -135,11 +135,11 @@ void cmp_send_ipi_single(int cpu, unsigned int action) local_irq_restore(flags); } -static void cmp_send_ipi_mask(cpumask_t mask, unsigned int action) +static void cmp_send_ipi_mask(const struct cpumask *mask, unsigned int action) { unsigned int i; - for_each_cpu_mask(i, mask) + for_each_cpu(i, mask) cmp_send_ipi_single(i, action); } diff --git a/arch/mips/kernel/smp-mt.c b/arch/mips/kernel/smp-mt.c index 6f7ee5a..9538ca4 100644 --- a/arch/mips/kernel/smp-mt.c +++ b/arch/mips/kernel/smp-mt.c @@ -141,11 +141,11 @@ static void vsmp_send_ipi_single(int cpu, unsigned int action) local_irq_restore(flags); } -static void vsmp_send_ipi_mask(cpumask_t mask, unsigned int action) +static void vsmp_send_ipi_mask(const struct cpumask *mask, unsigned int action) { unsigned int i; - for_each_cpu_mask(i, mask) + for_each_cpu(i, mask) vsmp_send_ipi_single(i, action); } diff --git a/arch/mips/kernel/smp-up.c b/arch/mips/kernel/smp-up.c index ead6c30..dace5d7 100644 --- a/arch/mips/kernel/smp-up.c +++ b/arch/mips/kernel/smp-up.c @@ -18,7 +18,8 @@ void up_send_ipi_single(int cpu, unsigned int action) panic(KERN_ERR "%s called", __func__); } -static inline void up_send_ipi_mask(cpumask_t mask, unsigned int action) +static inline void up_send_ipi_mask(const struct cpumask *mask, + unsigned int action) { panic(KERN_ERR "%s called", __func__); } diff --git a/arch/mips/kernel/smp.c b/arch/mips/kernel/smp.c index 3da9470..664ba8c 100644 --- a/arch/mips/kernel/smp.c +++ b/arch/mips/kernel/smp.c @@ -128,7 +128,7 @@ asmlinkage __cpuinit void start_secondary(void) cpu_idle(); } -void arch_send_call_function_ipi(cpumask_t mask) +void arch_send_call_function_ipi_mask(const struct cpumask *mask) { mp_ops->send_ipi_mask(mask, SMP_CALL_FUNCTION); } diff --git a/arch/mips/mipssim/sim_smtc.c b/arch/mips/mipssim/sim_smtc.c index d6e4f65..5da30b6 100644 --- a/arch/mips/mipssim/sim_smtc.c +++ b/arch/mips/mipssim/sim_smtc.c @@ -43,11 +43,12 @@ static void ssmtc_send_ipi_single(int cpu, unsigned int action) /* "CPU" may be TC of same VPE, VPE of same CPU, or different CPU */ } -static inline void ssmtc_send_ipi_mask(cpumask_t mask, unsigned int action) +static inline void ssmtc_send_ipi_mask(const struct cpumask *mask, + unsigned int action) { unsigned int i; - for_each_cpu_mask(i, mask) + for_each_cpu(i, mask) ssmtc_send_ipi_single(i, action); } diff --git a/arch/mips/mti-malta/malta-smtc.c b/arch/mips/mti-malta/malta-smtc.c index aabd727..9f3ab5f 100644 --- a/arch/mips/mti-malta/malta-smtc.c +++ b/arch/mips/mti-malta/malta-smtc.c @@ -21,11 +21,11 @@ static void msmtc_send_ipi_single(int cpu, unsigned int action) smtc_send_ipi(cpu, LINUX_SMP_IPI, action); } -static void msmtc_send_ipi_mask(cpumask_t mask, unsigned int action) +static void msmtc_send_ipi_mask(const struct cpumask *mask, unsigned int action) { unsigned int i; - for_each_cpu_mask(i, mask) + for_each_cpu(i, mask) msmtc_send_ipi_single(i, action); } diff --git a/arch/mips/pmc-sierra/yosemite/smp.c b/arch/mips/pmc-sierra/yosemite/smp.c index f78c29b..bb4779e 100644 --- a/arch/mips/pmc-sierra/yosemite/smp.c +++ b/arch/mips/pmc-sierra/yosemite/smp.c @@ -96,11 +96,11 @@ static void yos_send_ipi_single(int cpu, unsigned int action) } } -static void yos_send_ipi_mask(cpumask_t mask, unsigned int action) +static void yos_send_ipi_mask(const struct cpumask *mask, unsigned int action) { unsigned int i; - for_each_cpu_mask(i, mask) + for_each_cpu(i, mask) yos_send_ipi_single(i, action); } diff --git a/arch/mips/sgi-ip27/ip27-smp.c b/arch/mips/sgi-ip27/ip27-smp.c index 5b47d6b..4ffb255 100644 --- a/arch/mips/sgi-ip27/ip27-smp.c +++ b/arch/mips/sgi-ip27/ip27-smp.c @@ -165,11 +165,11 @@ static void ip27_send_ipi_single(int destid, unsigned int action) REMOTE_HUB_SEND_INTR(COMPACT_TO_NASID_NODEID(cpu_to_node(destid)), irq); } -static void ip27_send_ipi_mask(cpumask_t mask, unsigned int action) +static void ip27_send_ipi(const struct cpumask *mask, unsigned int action) { unsigned int i; - for_each_cpu_mask(i, mask) + for_each_cpu(i, mask) ip27_send_ipi_single(i, action); } diff --git a/arch/mips/sibyte/bcm1480/smp.c b/arch/mips/sibyte/bcm1480/smp.c index dddfda8..48ef140 100644 --- a/arch/mips/sibyte/bcm1480/smp.c +++ b/arch/mips/sibyte/bcm1480/smp.c @@ -82,11 +82,12 @@ static void bcm1480_send_ipi_single(int cpu, unsigned int action) __raw_writeq((((u64)action)<< 48), mailbox_0_set_regs[cpu]); } -static void bcm1480_send_ipi_mask(cpumask_t mask, unsigned int action) +static void bcm1480_send_ipi_mask(const struct cpumask *mask, + unsigned int action) { unsigned int i; - for_each_cpu_mask(i, mask) + for_each_cpu(i, mask) bcm1480_send_ipi_single(i, action); } diff --git a/arch/mips/sibyte/sb1250/smp.c b/arch/mips/sibyte/sb1250/smp.c index 5950a28..7fda6d2 100644 --- a/arch/mips/sibyte/sb1250/smp.c +++ b/arch/mips/sibyte/sb1250/smp.c @@ -70,11 +70,12 @@ static void sb1250_send_ipi_single(int cpu, unsigned int action) __raw_writeq((((u64)action) << 48), mailbox_set_regs[cpu]); } -static inline void sb1250_send_ipi_mask(cpumask_t mask, unsigned int action) +static inline void sb1250_send_ipi_mask(const struct cpumask *mask, + unsigned int action) { unsigned int i; - for_each_cpu_mask(i, mask) + for_each_cpu(i, mask) sb1250_send_ipi_single(i, action); } commit faad087e648decd8a7e4ae7bc04cc802a0100a81 Author: Rusty Russell Date: Mon Mar 16 14:17:19 2009 +1030 cpumask: remove the now-obsoleted pcibus_to_cpumask(): mips Impact: reduce stack usage for large NR_CPUS cpumask_of_pcibus() is the new version. Signed-off-by: Rusty Russell diff --git a/arch/mips/include/asm/mach-ip27/topology.h b/arch/mips/include/asm/mach-ip27/topology.h index 55d4815..b9b933b 100644 --- a/arch/mips/include/asm/mach-ip27/topology.h +++ b/arch/mips/include/asm/mach-ip27/topology.h @@ -30,7 +30,6 @@ extern struct cpuinfo_ip27 sn_cpu_info[NR_CPUS]; struct pci_bus; extern int pcibus_to_node(struct pci_bus *); -#define pcibus_to_cpumask(bus) (cpu_online_map) #define cpumask_of_pcibus(bus) (cpu_online_mask) extern unsigned char __node_distances[MAX_COMPACT_NODES][MAX_COMPACT_NODES]; From khickey@rmicorp.com Mon Mar 16 13:47:51 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 16 Mar 2009 13:47:58 +0000 (GMT) Received: from mx1.rmicorp.com ([63.111.213.197]:54796 "EHLO mx1.rmicorp.com") by ftp.linux-mips.org with ESMTP id S21368500AbZCPNrv (ORCPT ); Mon, 16 Mar 2009 13:47:51 +0000 Received: from 10.8.0.20 ([10.8.0.20]) by hq-ex-mb01.razamicroelectronics.com ([10.1.1.40]) via Exchange Front-End Server webmail.razamicroelectronics.com ([10.1.1.41]) with Microsoft Exchange Server HTTP-DAV ; Mon, 16 Mar 2009 13:47:41 +0000 Received: from kh-d820 by webmail.razamicroelectronics.com; 16 Mar 2009 08:47:41 -0500 Subject: Re: linux-2.6.28.4 regarding From: Kevin Hickey To: umeshyv Cc: linux-mips@linux-mips.org In-Reply-To: References: Content-Type: text/plain Content-Transfer-Encoding: 7bit Date: Mon, 16 Mar 2009 08:47:41 -0500 Message-Id: <1237211261.7473.3.camel@kh-d820> Mime-Version: 1.0 X-Mailer: Evolution 2.22.3.1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22082 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: khickey@rmicorp.com Precedence: bulk X-list: linux-mips Content-Length: 8719 Lines: 312 On Sat, 2009-03-14 at 17:22 +0530, umeshyv wrote: > Hi to all, > I downloaded latest kernel for mips (linux-2.6.28.4).How do I > configure Asoc driver(wm8731 codec,I2S based) for DbAu1200 > development board.Please guide me with your valuable > suggestions.waiting for your valuable reply > I just recently had the same request from someone else and created a pair of patches for this. It has only been through limited testing so I can't promise that it's perfect, but it basically works. >From 4fec1f6b93b09df62294d8fb08ae9d5266453d5f Mon Sep 17 00:00:00 2001 From: khickey Date: Wed, 11 Mar 2009 21:06:51 +0000 Subject: [PATCH] DB1200: Sample I2S audio sound machine Added a sound machine in the model of sample-ac97 for I2S audio with the WM8731 codec. Signed-off-by: Kevin Hickey git-svn-id: svn://coredev/Linux-kernel/trunk@65 35c7ba61-0b3b-44cf-8ad4-8c98d727fa3b --- sound/soc/au1x/Kconfig | 9 ++ sound/soc/au1x/Makefile | 2 + sound/soc/au1x/sample-i2s.c | 187 +++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 198 insertions(+), 0 deletions(-) create mode 100644 sound/soc/au1x/sample-i2s.c diff --git a/sound/soc/au1x/Kconfig b/sound/soc/au1x/Kconfig index c7ca3f2..abf333b 100644 --- a/sound/soc/au1x/Kconfig +++ b/sound/soc/au1x/Kconfig @@ -22,6 +22,15 @@ config SND_SOC_AU1XPSC_AC97 ## ## Boards ## +config SND_SOC_SAMPLE_PSC_I2S + tristate "Sample Au12x0/Au1550 PSC I2S sound machine" + depends on SND_SOC_AU1XPSC + select SND_SOC_AU1XPSC_I2S + select SND_SOC_WM8731 + help + This is a sample I2S sound machine for use with the DB1200 + development board, which has a WM8731 codec. + config SND_SOC_SAMPLE_PSC_AC97 tristate "Sample Au12x0/Au1550 PSC AC97 sound machine" depends on SND_SOC_AU1XPSC diff --git a/sound/soc/au1x/Makefile b/sound/soc/au1x/Makefile index b48bb36..b8e54a4 100644 --- a/sound/soc/au1x/Makefile +++ b/sound/soc/au1x/Makefile @@ -9,7 +9,9 @@ obj-$(CONFIG_SND_SOC_AU1XPSC_AC97) += snd-soc-au1xpsc-ac97.o # Boards snd-soc-sample-ac97-objs := sample-ac97.o +snd-soc-sample-i2s-objs := sample-i2s.o snd-soc-hmp10-ac97-objs := hmp10-ac97.o obj-$(CONFIG_SND_SOC_SAMPLE_PSC_AC97) += snd-soc-sample-ac97.o +obj-$(CONFIG_SND_SOC_SAMPLE_PSC_I2S) += snd-soc-sample-i2s.o obj-$(CONFIG_SND_SOC_HMP10_AC97) += snd-soc-hmp10-ac97.o diff --git a/sound/soc/au1x/sample-i2s.c b/sound/soc/au1x/sample-i2s.c new file mode 100644 index 0000000..612cfaa --- /dev/null +++ b/sound/soc/au1x/sample-i2s.c @@ -0,0 +1,187 @@ +/* + * Sample Au12x0 PSC I2S sound machine. + * + * Copyright (c) 2009 RMI Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms outlined in the file COPYING at the root of this + * source archive. + * + * This is a very generic I2S sound machine driver for boards which + * have I2S audio at PSC1 (e.g. DB1200 demoboards). + * + * This file is based on sample-ac97.c by Manuel Lauss + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#ifdef CONFIG_MIPS_DB1200 +#include +#endif + +#include "../codecs/wm8731.h" +#include "psc.h" + +static int au1xpsc_sample_i2s_init(struct snd_soc_codec *codec) +{ + snd_soc_dapm_sync(codec); + return 0; +} + +static int au1xpsc_sample_hw_params(struct snd_pcm_substream *substream, + struct snd_pcm_hw_params *params) +{ + struct snd_soc_pcm_runtime *rtd = substream->private_data; + struct snd_soc_dai *codec_dai = rtd->dai->codec_dai; + int ret = 0; + + ret = snd_soc_dai_set_fmt(codec_dai, SND_SOC_DAIFMT_I2S | + SND_SOC_DAIFMT_CBM_CFM); + return ret; +} + + +static struct snd_soc_ops au1xpsc_sample_ops = { + .hw_params = au1xpsc_sample_hw_params, +}; + +static struct snd_soc_dai_link au1xpsc_sample_i2s_dai = { + .name = "I2S", + .stream_name = "I2S WM8731", + .cpu_dai = &au1xpsc_i2s_dai, /* see psc-i2s.c */ + .codec_dai = &wm8731_dai, /* see codecs/wm8731.c */ + .init = au1xpsc_sample_i2s_init, + .ops = &au1xpsc_sample_ops, +}; + +static struct snd_soc_card au1xpsc_sample_i2s_machine = { + .name = "Au1xxx PSC I2S Audio", + .dai_link = &au1xpsc_sample_i2s_dai, + .platform = &au1xpsc_soc_platform, /* see dbdma2.c */ + .num_links = 1, + .platform = &au1xpsc_soc_platform, /* see dbdma2.c */ +}; + +static struct wm8731_setup_data au1xpsc_sample_wm8731_setup = { + .i2c_bus = 0, + .i2c_address = 0x1b, +}; + +static struct snd_soc_device au1xpsc_sample_i2s_devdata = { + .card = &au1xpsc_sample_i2s_machine, + .codec_dev = &soc_codec_dev_wm8731, + .codec_data = &au1xpsc_sample_wm8731_setup, +}; + +static struct resource au1xpsc_psc1_res[] = { + [0] = { + .start = CPHYSADDR(PSC1_BASE_ADDR), + .end = CPHYSADDR(PSC1_BASE_ADDR) + 0x000fffff, + .flags = IORESOURCE_MEM, + }, + [1] = { +#ifdef CONFIG_SOC_AU1200 + .start = AU1200_PSC1_INT, + .end = AU1200_PSC1_INT, +#elif defined(CONFIG_SOC_AU1550) + .start = AU1550_PSC1_INT, + .end = AU1550_PSC1_INT, +#elif defined(CONFIG_SOC_AU13XX) + .start = AU1300_IRQ_PSC1, + .end = AU1300_IRQ_PSC1, +#endif + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = DSCR_CMD0_PSC1_TX, + .end = DSCR_CMD0_PSC1_TX, + .flags = IORESOURCE_DMA, + }, + [3] = { + .start = DSCR_CMD0_PSC1_RX, + .end = DSCR_CMD0_PSC1_RX, + .flags = IORESOURCE_DMA, + }, +}; + +static struct platform_device *au1xpsc_sample_i2s_dev; + +static int __init au1xpsc_sample_i2s_load(void) +{ + int ret; + +#ifdef CONFIG_SOC_AU1200 + unsigned long io; + + /* modify sys_pinfunc for AC97 on PSC1 */ + io = au_readl(SYS_PINFUNC); + io |= SYS_PINFUNC_P1C; + io &= ~(SYS_PINFUNC_P1A | SYS_PINFUNC_P1B); + au_writel(io, SYS_PINFUNC); + au_sync(); + +#endif + + /* + * The DB1200 has a mux coming out of PSC1 that switches between AC97 + * and I2S. The default is AC97 so we have to make sure to change it + * here. + */ +#ifdef CONFIG_MIPS_DB1200 + AU_SET_BITS_16(BCSR_RESETS_PCS1MUX, &bcsr->resets); +#endif + + ret = -ENOMEM; + + /* setup PSC clock source for AC97 part: external clock provided + * by codec. The psc-ac97.c driver depends on this setting! + */ + au_writel(PSC_SEL_CLK_SERCLK, PSC1_BASE_ADDR + PSC_SEL_OFFSET); + au_sync(); + + au1xpsc_sample_i2s_dev = platform_device_alloc("soc-audio", -1); + if (!au1xpsc_sample_i2s_dev) + goto out; + + au1xpsc_sample_i2s_dev->resource = + kmemdup(au1xpsc_psc1_res, sizeof(struct resource) * + ARRAY_SIZE(au1xpsc_psc1_res), GFP_KERNEL); + au1xpsc_sample_i2s_dev->num_resources = ARRAY_SIZE(au1xpsc_psc1_res); + au1xpsc_sample_i2s_dev->id = 1; + + platform_set_drvdata(au1xpsc_sample_i2s_dev, + &au1xpsc_sample_i2s_devdata); + au1xpsc_sample_i2s_devdata.dev = &au1xpsc_sample_i2s_dev->dev; + ret = platform_device_add(au1xpsc_sample_i2s_dev); + + if (ret) { + platform_device_put(au1xpsc_sample_i2s_dev); + au1xpsc_sample_i2s_dev = NULL; + } + +out: + return ret; +} + +static void __exit au1xpsc_sample_i2s_exit(void) +{ + platform_device_unregister(au1xpsc_sample_i2s_dev); +} + +module_init(au1xpsc_sample_i2s_load); +module_exit(au1xpsc_sample_i2s_exit); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("Au1xxx PSC sample I2S machine"); +MODULE_AUTHOR("Kevin Hickey "); -- 1.5.4.3 >From 6a54eade32f3df84af3644ea7991f48e7ea91f99 Mon Sep 17 00:00:00 2001 From: khickey Date: Fri, 13 Mar 2009 14:01:04 +0000 Subject: [PATCH] DB1200: Bugfix - WM8731 powerup The existing WM8731 code was not powering up the codec properly, resulting in no sound. The clock output, oscillator and DAC were all staying powered down. git-svn-id: svn://coredev/Linux-kernel/trunk@69 35c7ba61-0b3b-44cf-8ad4-8c98d727fa3b --- sound/soc/codecs/wm8731.c | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/sound/soc/codecs/wm8731.c b/sound/soc/codecs/wm8731.c index c444b9f..0dcf172 100644 --- a/sound/soc/codecs/wm8731.c +++ b/sound/soc/codecs/wm8731.c @@ -418,8 +418,8 @@ static int wm8731_set_bias_level(struct snd_soc_codec *codec, switch (level) { case SND_SOC_BIAS_ON: - /* vref/mid, osc on, dac unmute */ - wm8731_write(codec, WM8731_PWR, reg); + /* Turn everything on */ + wm8731_write(codec, WM8731_PWR, 0); break; case SND_SOC_BIAS_PREPARE: break; -- 1.5.4.3 -- Kevin Hickey Alchemy Solutions RMI Corporation khickey@rmicorp.com P: 512.691.8044 From dan.j.williams@gmail.com Mon Mar 16 21:20:58 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 16 Mar 2009 21:21:06 +0000 (GMT) Received: from wa-out-1112.google.com ([209.85.146.183]:40197 "EHLO wa-out-1112.google.com") by ftp.linux-mips.org with ESMTP id S21368802AbZCPVU6 convert rfc822-to-8bit (ORCPT ); Mon, 16 Mar 2009 21:20:58 +0000 Received: by wa-out-1112.google.com with SMTP id k40so1625003wah.0 for ; Mon, 16 Mar 2009 14:20:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:sender:received:in-reply-to :references:date:x-google-sender-auth:message-id:subject:from:to:cc :content-type:content-transfer-encoding; bh=rh65yimJLUOeclwc2iRiIW46PYmDLRKdVvFqqBdg3Tc=; b=A8oWo3V3Jm1YNBP29oWi98is7mmf02iunvW9q7Qt5pmMwr4MifK4vnkS8ii2mWZDxZ G9yUELUXCV3U8EOIvvW7MPX35cADLt8R2VAI8CFN+9v/Hds/sFTDrP8vcKfa1cbAsUb8 hgp/+OX2FZ8B74PAWpwDPLbox2mI3N3EcGiVM= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:sender:in-reply-to:references:date :x-google-sender-auth:message-id:subject:from:to:cc:content-type :content-transfer-encoding; b=XbFoBZsH3XLRTm3jfncuWpNGHRQLsANwS4NCMWHt6ZB3KGFUgi5pc4sOiVOzoysnhj VTW8y1P935ot4Xmt+FWYX4mdTCbPmXRkysY7ZX1TLmPyIic6QtAuUJFDv3u/yiW+O60M q9k/Wiocgu/vL5r9wtOQiKdzFOCEDBQlclMho= MIME-Version: 1.0 Received: by 10.114.195.19 with SMTP id s19mr3577131waf.10.1237238456217; Mon, 16 Mar 2009 14:20:56 -0700 (PDT) In-Reply-To: <20090227.002436.106263719.anemo@mba.ocn.ne.jp> References: <1234538938-23479-1-git-send-email-anemo@mba.ocn.ne.jp> <20090227.002436.106263719.anemo@mba.ocn.ne.jp> Date: Mon, 16 Mar 2009 14:20:56 -0700 X-Google-Sender-Auth: f4811340525b1313 Message-ID: Subject: Re: [PATCH 1/2] dmaengine: TXx9 Soc DMA Controller driver From: Dan Williams To: Atsushi Nemoto Cc: linux-mips@linux-mips.org, ralf@linux-mips.org, linux-kernel@vger.kernel.org, haavard.skinnemoen@atmel.com Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22083 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dan.j.williams@intel.com Precedence: bulk X-list: linux-mips Content-Length: 5924 Lines: 144 On Thu, Feb 26, 2009 at 8:24 AM, Atsushi Nemoto wrote: > On Wed, 25 Feb 2009 18:45:28 -0700, Dan Williams wrote: >> Some comments and questions below. > > Thank you for review. > >> > +static struct txx9dmac_dev *to_txx9dmac_dev(struct dma_device *ddev) >> > +{ >> > + if (ddev->device_prep_dma_memcpy) >> > + return container_of(ddev, struct txx9dmac_dev, dma_memcpy); >> > + return container_of(ddev, struct txx9dmac_dev, dma); >> > +} >> >> Can you explain why you need two dma_devices per txx9dmac_dev? My >> initial reaction is that it should be a bug if callers to >> to_txx9dmac_dev() don't know what type of channel they are holding. > > I created two dma_devices: one for private slave dma channels and one > for public memcpy channel. I will explain later in this mail. > >> > + dma_async_tx_descriptor_init(&desc->txd, &dc->chan); >> > + desc->txd.tx_submit = txx9dmac_tx_submit; >> > + desc->txd.flags = DMA_CTRL_ACK; >> > + INIT_LIST_HEAD(&desc->txd.tx_list); >> > + desc->txd.phys = dma_map_single(chan2parent(&dc->chan), &desc->hwdesc, >> > + ddev->descsize, DMA_TO_DEVICE); >> > + return desc; >> > +} >> >> By setting DMA_CTRL_ACK by default this means that async_tx can never >> attach attach a dependent operation to a txx9 descriptor. This may >> not be a problem in practice because async_tx will only do this to >> satisfy inter-channel dependencies. For example memcpy on chan-foo >> followed by xor on chan-bar. For future proofing the driver I would >> rely on clients properly setting the ack bit when they call >> ->device_prep_dma_memcpy > > The desc->txd.flags will be overwritten in txx9dmac_prep_xxx. The > reason setting DMA_CTRL_ACK here is to make the desc can be pulled > from freelist in txx9dmac_desc_get(). Thanks for clarification... > Maybe I should move this DMA_CTRL_ACK setting to txx9dmac_desc_put()? Perhaps a comment. I think this scheme is ok, it just raised alarm bells as I read it. [..] >> > +static irqreturn_t txx9dmac_interrupt(int irq, void *dev_id) >> > +{ >> > +#ifdef TXX9_DMA_HAVE_IRQ_PER_CHAN >> > + struct txx9dmac_chan *dc = dev_id; >> > + >> > + dev_vdbg(chan2dev(&dc->chan), "interrupt: status=%#x\n", >> > + channel_readl(dc, CSR)); >> > + >> > + tasklet_schedule(&dc->tasklet); >> > +#else >> > + struct txx9dmac_dev *ddev = dev_id; >> > + >> > + dev_vdbg(ddev->dma.dev, "interrupt: status=%#x\n", >> > + dma_readl(ddev, MCR)); >> > + >> > + tasklet_schedule(&ddev->tasklet); >> > +#endif >> > + /* >> > + * Just disable the interrupts. We'll turn them back on in the >> > + * softirq handler. >> > + */ >> > + disable_irq_nosync(irq); >> > + >> > + return IRQ_HANDLED; >> > +} >> >> Why do you need to disable interrupts here? > > Because interrupts are not cleared until txx9dmac_tasklet() calls > txx9dmac_scan_descriptors() and it writes to CSR. Touching CSR in > txx9dmac_interrupt() seems bad while dc->lock spinlock does not > protect from interrupts. I chose calling disable_irq here instead of > replace all spin_lock with spin_lock_irqsave. I believe in this case you are protected by the fact this IRQ handler will not race against itself, i.e. even though other interrupts are enabled this handler will be masked until it returns. > >> > + dev_vdbg(chan2dev(chan), "alloc_chan_resources\n"); >> > + >> > + if (chan == &ddev->reserved_chan) { >> > + /* reserved */ >> > + return 0; >> > + } >> >> Can you explain how reserved channels work? It looks like you are >> working around the generic dma channel allocator, maybe it requires >> updating to meet your needs. > > OK, let me try to explain. This DMAC have four channels and one FIFO > buffer. Each channel can be configured for memory-memory or > device-memory transfer, but only one channel can do alignment-free > memory-memory transfer at a time while the channel should occupy the > FIFO buffer for effective transfers. > > Instead of dynamically assign the FIFO buffer to channels, I chose > make one dedicated channel for memory-memory transfer. The dedicated > channel is public. Other channels are private and used for slave > transfer. Some devices in the SoC are wired to certain DMA channel. > The platform code will give a channel number for memory-memory > transfer via platform_data. > > The txx9dmac_probe() creates two dma_device: one for private slave > channels and one for a public memory channel. It also creates five > dma_chan: four dma_chan are wrapped by txx9dmac_chan and other one > dma_chan is used to reserve a memcpy channel number in slave > dma_device. > > For example, if channel 2 was selected for memcpy, the dma_device for > slave (txx9dmac_dev.dma) contains txx9dmac_chan[0,1], reserved_chan > and txx9dmac_chan[3] in this order and the dma_device for memcpy > (txx9dmac_dev.dma_memcpy) contains txx9dmac_chan[2]. > > Now we have dma0chan0, dma0chan1, dma0chan2, dma0chan3 and dma1chan0. > > The txx9dmac_probe() calls dma_request_channel() to reserve dma0chan2. > > I need the reserved_chan to make channel 3 named "dma0chan3". If I > can chose chan_id for each channels in dma_device, the reserved_chan > is not needed. Can you post the code that communicates chan_id to the routine calling dma_request_channel? I am not understanding why you need to control chan_id. Why not have the filter_fn passed to dma_request_channel ignore non-private devices? > And if I could make only one channel in dma_device public, I need only > one dma_device. But I suppose it is not easy while DMA_PRIVATE is not > per-channel attribute now. Yes, that would be awkward given how the other capability bits are handled. -- Dan From dan.j.williams@intel.com Mon Mar 16 21:50:54 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 16 Mar 2009 21:51:02 +0000 (GMT) Received: from mga01.intel.com ([192.55.52.88]:38424 "EHLO mga01.intel.com") by ftp.linux-mips.org with ESMTP id S20808557AbZCPVuy (ORCPT ); Mon, 16 Mar 2009 21:50:54 +0000 Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga101.fm.intel.com with ESMTP; 16 Mar 2009 14:42:56 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="4.38,375,1233561600"; d="scan'208";a="439402677" Received: from dwillia2-linux.ch.intel.com (HELO [10.2.42.224]) ([10.2.42.224]) by fmsmga002.fm.intel.com with ESMTP; 16 Mar 2009 14:46:18 -0700 Subject: Re: [PATCH 1/2] dmaengine: TXx9 Soc DMA Controller driver From: Dan Williams To: Atsushi Nemoto Cc: "linux-mips@linux-mips.org" , "ralf@linux-mips.org" , "linux-kernel@vger.kernel.org" , "haavard.skinnemoen@atmel.com" In-Reply-To: <20090313.231659.41197617.anemo@mba.ocn.ne.jp> References: <20090227.002436.106263719.anemo@mba.ocn.ne.jp> <20090313.011950.61509382.anemo@mba.ocn.ne.jp> <20090313.231659.41197617.anemo@mba.ocn.ne.jp> Content-Type: text/plain Date: Mon, 16 Mar 2009 14:50:46 -0700 Message-Id: <1237240246.27945.6.camel@dwillia2-linux.ch.intel.com> Mime-Version: 1.0 X-Mailer: Evolution 2.22.3.1 (2.22.3.1-1.fc9) Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22084 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dan.j.williams@intel.com Precedence: bulk X-list: linux-mips Content-Length: 3234 Lines: 101 On Fri, 2009-03-13 at 07:16 -0700, Atsushi Nemoto wrote: > On Fri, 13 Mar 2009 01:19:50 +0900 (JST), Atsushi Nemoto wrote: > > Subject: dmaengine: Use chan_id provided by DMA device driver > > From: Atsushi Nemoto > > > > If chan_id was already given by the DMA device driver, use it. > > Otherwise assign an incremental number for each channels. > > > > This allows the DMA device driver to reserve some channel ID numbers. > ... > > @@ -663,7 +664,9 @@ int dma_async_device_register(struct dma_device *device) > > continue; > > } > > > > - chan->chan_id = chancnt++; > > + if (!chan->chan_id) > > + chan->chan_id = chan_id++; > > + chancnt++; > > chan->dev->device.class = &dma_devclass; > > chan->dev->device.parent = device->dev; > > chan->dev->chan = chan; > > This patch will fix another potential problem. Some driver, for > example ipu, assumes chan_id is an index of its internal array. But > dmaengine core does not guarantee it. > > /* represent channels in sysfs. Probably want devs too */ > list_for_each_entry(chan, &device->channels, device_node) { > chan->local = alloc_percpu(typeof(*chan->local)); > if (chan->local == NULL) > continue; > chan->dev = kzalloc(sizeof(*chan->dev), GFP_KERNEL); > if (chan->dev == NULL) { > free_percpu(chan->local); > continue; > } > > chan->chan_id = chancnt++; > ... > } > device->chancnt = chancnt; > > If alloc_percpu or kzalloc failed, chan_id does not match with its > position in device->channels list. > > > And above "continue" looks buggy anyway. Keeping incomplete channels > in device->channels list looks very dangerous... Yes it does. Here is the proposed fix: -----> dmaengine: fail device registration if channel registration fails From: Dan Williams Atsushi points out: "If alloc_percpu or kzalloc failed, chan_id does not match with its position in device->channels list. And above "continue" looks buggy anyway. Keeping incomplete channels in device->channels list looks very dangerous..." Reported-by: Atsushi Nemoto Signed-off-by: Dan Williams --- drivers/dma/dmaengine.c | 8 ++++++-- 1 files changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/dma/dmaengine.c b/drivers/dma/dmaengine.c index a589930..fa14e8b 100644 --- a/drivers/dma/dmaengine.c +++ b/drivers/dma/dmaengine.c @@ -652,13 +652,15 @@ int dma_async_device_register(struct dma_device *device) /* represent channels in sysfs. Probably want devs too */ list_for_each_entry(chan, &device->channels, device_node) { + rc = -ENOMEM; chan->local = alloc_percpu(typeof(*chan->local)); if (chan->local == NULL) - continue; + goto err_out; chan->dev = kzalloc(sizeof(*chan->dev), GFP_KERNEL); if (chan->dev == NULL) { free_percpu(chan->local); - continue; + chan->local = NULL; + goto err_out; } chan->chan_id = chancnt++; @@ -675,6 +677,8 @@ int dma_async_device_register(struct dma_device *device) if (rc) { free_percpu(chan->local); chan->local = NULL; + kfree(chan->dev); + atomic_dec(idr_ref); goto err_out; } chan->client_count = 0; From anemo@mba.ocn.ne.jp Tue Mar 17 01:52:42 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 17 Mar 2009 01:52:49 +0000 (GMT) Received: from fwtops.0.225.230.202.in-addr.arpa ([202.230.225.126]:21983 "EHLO topsms.toshiba-tops.co.jp") by ftp.linux-mips.org with ESMTP id S21368806AbZCQBwm convert rfc822-to-8bit (ORCPT ); Tue, 17 Mar 2009 01:52:42 +0000 Received: from topsms.toshiba-tops.co.jp (localhost.localdomain [127.0.0.1]) by localhost.toshiba-tops.co.jp (Postfix) with ESMTP id 647E942BFB; Tue, 17 Mar 2009 10:46:03 +0900 (JST) Received: from srd2sd.toshiba-tops.co.jp (srd2sd.toshiba-tops.co.jp [172.17.28.2]) by topsms.toshiba-tops.co.jp (Postfix) with ESMTP id 4F39D1DCFC; Tue, 17 Mar 2009 10:46:03 +0900 (JST) Received: from localhost (fragile [172.17.28.65]) by srd2sd.toshiba-tops.co.jp (8.12.10/8.12.10) with ESMTP id n2H1qVnf026516; Tue, 17 Mar 2009 10:52:31 +0900 (JST) (envelope-from anemo@mba.ocn.ne.jp) Date: Tue, 17 Mar 2009 10:52:30 +0900 (JST) Message-Id: <20090317.105230.118904211.nemoto@toshiba-tops.co.jp> To: dan.j.williams@intel.com Cc: linux-mips@linux-mips.org, ralf@linux-mips.org, linux-kernel@vger.kernel.org, haavard.skinnemoen@atmel.com Subject: Re: [PATCH 1/2] dmaengine: TXx9 Soc DMA Controller driver From: Atsushi Nemoto In-Reply-To: References: <20090227.002436.106263719.anemo@mba.ocn.ne.jp> X-Fingerprint: 6ACA 1623 39BD 9A94 9B1A B746 CA77 FE94 2874 D52F X-Pgp-Public-Key: http://wwwkeys.pgp.net/pks/lookup?op=get&search=0x2874D52F X-Mailer: Mew version 6.1 on Emacs 22.2 / Mule 5.0 (SAKAKI) Mime-Version: 1.0 Content-Type: Text/Plain; charset=iso-8859-1 Content-Transfer-Encoding: 8BIT Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22085 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anemo@mba.ocn.ne.jp Precedence: bulk X-list: linux-mips Content-Length: 2585 Lines: 74 On Mon, 16 Mar 2009 14:20:56 -0700, Dan Williams wrote: > > Maybe I should move this DMA_CTRL_ACK setting to txx9dmac_desc_put()? > > Perhaps a comment. I think this scheme is ok, it just raised alarm > bells as I read it. OK, I will do. > >> > + disable_irq_nosync(irq); > >> > + > >> > + return IRQ_HANDLED; > >> > +} > >> > >> Why do you need to disable interrupts here? > > > > Because interrupts are not cleared until txx9dmac_tasklet() calls > > txx9dmac_scan_descriptors() and it writes to CSR. Touching CSR in > > txx9dmac_interrupt() seems bad while dc->lock spinlock does not > > protect from interrupts. I chose calling disable_irq here instead of > > replace all spin_lock with spin_lock_irqsave. > > I believe in this case you are protected by the fact this IRQ handler > will not race against itself, i.e. even though other interrupts are > enabled this handler will be masked until it returns. Yes, IRQ handler will be masked, but tasklet will not be masked. If I did not disable irq here, the kernel hangs just after returning from this IRQ handler (and before tasklet routine is invoked). > > I need the reserved_chan to make channel 3 named "dma0chan3". If I > > can chose chan_id for each channels in dma_device, the reserved_chan > > is not needed. > > Can you post the code that communicates chan_id to the routine calling > dma_request_channel? I am not understanding why you need to control > chan_id. Why not have the filter_fn passed to dma_request_channel > ignore non-private devices? You mean the filter_fn provided by client driver? I don't want to let client driver know which channel is used for memcpy. And if "dma0chan3" was not the Ch3 of the DMAC, it looks confusing... Here is an excerpt from client under construction. struct txx9aclc_dmadata { struct resource *dma_res; struct txx9dmac_slave dma_slave; struct dma_chan *dma_chan; ... }; static bool filter(struct dma_chan *chan, void *param) { struct txx9aclc_dmadata *dmadata = param; if (strcmp(dev_name(chan->device->dev), dmadata->dma_res->name) == 0 && dmadata->dma_res->start == chan->chan_id) { chan->private = &dmadata->dma_slave; return true; } return false; } struct txx9dmac_slave *ds = &dmadata->dma_slave; ... dmadata->dma_res = platform_get_resource(pdev, IORESOURCE_DMA, 0); ... dmadata->dma_chan = dma_request_channel(mask, filter, dmadata); The IORESOURCE_DMA resource for the client device contains a name of a DMA driver (dma_res->name) and its channel ID (dma_res->start). --- Atsushi Nemoto From anemo@mba.ocn.ne.jp Tue Mar 17 02:20:27 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 17 Mar 2009 02:20:35 +0000 (GMT) Received: from fwtops.0.225.230.202.in-addr.arpa ([202.230.225.126]:3334 "EHLO topsms.toshiba-tops.co.jp") by ftp.linux-mips.org with ESMTP id S21368719AbZCQCU1 (ORCPT ); Tue, 17 Mar 2009 02:20:27 +0000 Received: from topsms.toshiba-tops.co.jp (localhost.localdomain [127.0.0.1]) by localhost.toshiba-tops.co.jp (Postfix) with ESMTP id 732FA42B62; Tue, 17 Mar 2009 11:13:50 +0900 (JST) Received: from srd2sd.toshiba-tops.co.jp (srd2sd.toshiba-tops.co.jp [172.17.28.2]) by topsms.toshiba-tops.co.jp (Postfix) with ESMTP id 6665F42A59; Tue, 17 Mar 2009 11:13:50 +0900 (JST) Received: from localhost (fragile [172.17.28.65]) by srd2sd.toshiba-tops.co.jp (8.12.10/8.12.10) with ESMTP id n2H2KJnf026653; Tue, 17 Mar 2009 11:20:19 +0900 (JST) (envelope-from anemo@mba.ocn.ne.jp) Date: Tue, 17 Mar 2009 11:20:19 +0900 (JST) Message-Id: <20090317.112019.147212126.nemoto@toshiba-tops.co.jp> To: dan.j.williams@intel.com Cc: linux-mips@linux-mips.org, ralf@linux-mips.org, linux-kernel@vger.kernel.org, haavard.skinnemoen@atmel.com Subject: Re: [PATCH 1/2] dmaengine: TXx9 Soc DMA Controller driver From: Atsushi Nemoto In-Reply-To: <1237240246.27945.6.camel@dwillia2-linux.ch.intel.com> References: <20090313.011950.61509382.anemo@mba.ocn.ne.jp> <20090313.231659.41197617.anemo@mba.ocn.ne.jp> <1237240246.27945.6.camel@dwillia2-linux.ch.intel.com> X-Fingerprint: 6ACA 1623 39BD 9A94 9B1A B746 CA77 FE94 2874 D52F X-Pgp-Public-Key: http://wwwkeys.pgp.net/pks/lookup?op=get&search=0x2874D52F X-Mailer: Mew version 6.1 on Emacs 22.2 / Mule 5.0 (SAKAKI) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22086 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anemo@mba.ocn.ne.jp Precedence: bulk X-list: linux-mips Content-Length: 1008 Lines: 28 On Mon, 16 Mar 2009 14:50:46 -0700, Dan Williams wrote: > > And above "continue" looks buggy anyway. Keeping incomplete channels > > in device->channels list looks very dangerous... > > Yes it does. Here is the proposed fix: > -----> > dmaengine: fail device registration if channel registration fails > > From: Dan Williams > > Atsushi points out: > "If alloc_percpu or kzalloc failed, chan_id does not match with its > position in device->channels list. > > And above "continue" looks buggy anyway. Keeping incomplete channels > in device->channels list looks very dangerous..." > > Reported-by: Atsushi Nemoto > Signed-off-by: Dan Williams Thanks, but it seems a hole sill exists. If alloc_percpu or kzalloc for the first channel failed, when idr_ref will be freed ? Hmm.. why idr_ref is dynamically allocated? Just putting it in dma_device makes thing more simple, no? --- Atsushi Nemoto From dan.j.williams@gmail.com Tue Mar 17 04:52:14 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 17 Mar 2009 04:52:22 +0000 (GMT) Received: from wa-out-1112.google.com ([209.85.146.182]:16380 "EHLO wa-out-1112.google.com") by ftp.linux-mips.org with ESMTP id S19202470AbZCQEwO convert rfc822-to-8bit (ORCPT ); Tue, 17 Mar 2009 04:52:14 +0000 Received: by wa-out-1112.google.com with SMTP id k40so1714622wah.0 for ; Mon, 16 Mar 2009 21:52:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:sender:received:in-reply-to :references:date:x-google-sender-auth:message-id:subject:from:to:cc :content-type:content-transfer-encoding; bh=5oZ19K8/HWHNTi3tQMRaj0Ok/OrTjY8lgX3exPmXLR4=; b=mBMNiU3jZYdZg3jlFjudt4m09/uPlRvAYu9D0XDWVPDgjlzqBDAEUf9mxOK3m6F1Me mm7gz6vMf8mdrJBDbdSno0VfqC5vjv1mzpSKyPFBEyOouVzX8lVnhJ0UrqS8qaBVEBEm JJTTY4f7xOcL7IV0QLR6bUs2tdLWK6wf0JINE= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:sender:in-reply-to:references:date :x-google-sender-auth:message-id:subject:from:to:cc:content-type :content-transfer-encoding; b=vQBQrh13kCqFh5hWGbazCGAEpu4a5k7SQIEGbYjrqyesCwwGLvjEEx4gpyqMIdvWNl SEPQQlwZe32ho4biOrq4ZOIxEICqXyhloKVi30r4P2ENNovq0F4gU1ZuS73fHUUEP2/z ZiMBvF0BlWwE8YQ17hDwbHu4XNFnd0FhUqJiw= MIME-Version: 1.0 Received: by 10.114.131.11 with SMTP id e11mr3938263wad.75.1237265531756; Mon, 16 Mar 2009 21:52:11 -0700 (PDT) In-Reply-To: <20090317.112019.147212126.nemoto@toshiba-tops.co.jp> References: <20090313.011950.61509382.anemo@mba.ocn.ne.jp> <20090313.231659.41197617.anemo@mba.ocn.ne.jp> <1237240246.27945.6.camel@dwillia2-linux.ch.intel.com> <20090317.112019.147212126.nemoto@toshiba-tops.co.jp> Date: Mon, 16 Mar 2009 21:52:10 -0700 X-Google-Sender-Auth: 3f7286a669fae652 Message-ID: Subject: Re: [PATCH 1/2] dmaengine: TXx9 Soc DMA Controller driver From: Dan Williams To: Atsushi Nemoto Cc: linux-mips@linux-mips.org, ralf@linux-mips.org, linux-kernel@vger.kernel.org, haavard.skinnemoen@atmel.com Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22088 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dan.j.williams@intel.com Precedence: bulk X-list: linux-mips Content-Length: 1922 Lines: 56 On Mon, Mar 16, 2009 at 7:20 PM, Atsushi Nemoto wrote: > On Mon, 16 Mar 2009 14:50:46 -0700, Dan Williams wrote: >> > And above "continue" looks buggy anyway. Keeping incomplete channels >> > in device->channels list looks very dangerous... >> >> Yes it does. Here is the proposed fix: >> -----> >> dmaengine: fail device registration if channel registration fails >> >> From: Dan Williams >> >> Atsushi points out: >> "If alloc_percpu or kzalloc failed, chan_id does not match with its >> position in device->channels list. >> >> And above "continue" looks buggy anyway. Keeping incomplete channels >> in device->channels list looks very dangerous..." >> >> Reported-by: Atsushi Nemoto >> Signed-off-by: Dan Williams > > Thanks, but it seems a hole sill exists. If alloc_percpu or kzalloc > for the first channel failed, when idr_ref will be freed ? > True, we need a check like the following: /* if we never registered a channel just release the idr */ if (atomic_read(idr_ref) == 0) { mutex_lock(&dma_list_mutex); idr_remove(&dma_idr, device->dev_id); mutex_unlock(&dma_list_mutex); kfree(idr_ref); return rc; } > Hmm.. why idr_ref is dynamically allocated? Just putting it in > dma_device makes thing more simple, no? > The sysfs device has a longer lifetime than dma_device. See commit 41d5e59c [1]. -- Dan [1] http://git.kernel.org/?p=linux/kernel/git/djbw/async_tx.git;a=commitdiff;h=41d5e59c > --- > Atsushi Nemoto > -- > To unsubscribe from this list: send the line "unsubscribe linux-kernel" in > the body of a message to majordomo@vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html > Please read the FAQ at http://www.tux.org/lkml/ > From shinya.kuribayashi@necel.com Tue Mar 17 06:31:57 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 17 Mar 2009 06:32:04 +0000 (GMT) Received: from TYO202.gate.nec.co.jp ([202.32.8.206]:34030 "EHLO tyo202.gate.nec.co.jp") by ftp.linux-mips.org with ESMTP id S21367164AbZCQGb5 (ORCPT ); Tue, 17 Mar 2009 06:31:57 +0000 Received: from relay11.aps.necel.com ([10.29.19.46]) by tyo202.gate.nec.co.jp (8.13.8/8.13.4) with ESMTP id n2H6Vr2N019705; Tue, 17 Mar 2009 15:31:53 +0900 (JST) Received: from realmbox21.aps.necel.com ([10.29.19.28] [10.29.19.28]) by relay11.aps.necel.com with ESMTP; Tue, 17 Mar 2009 15:31:53 +0900 Received: from [10.114.181.78] ([10.114.181.78] [10.114.181.78]) by mbox02.aps.necel.com with ESMTP; Tue, 17 Mar 2009 15:31:53 +0900 Message-Id: <49BF4410.8080006@necel.com> Date: Tue, 17 Mar 2009 15:32:48 +0900 From: Shinya Kuribayashi User-Agent: Thunderbird 2.0.0.19 (Windows/20081209) MIME-Version: 1.0 To: linux-mips@linux-mips.org, ralf@linux-mips.org Subject: MIPS: Enable prefetch option for VR5500 processor References: <49ACF2EF.3080903@necel.com> In-Reply-To: <49ACF2EF.3080903@necel.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22089 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: shinya.kuribayashi@necel.com Precedence: bulk X-list: linux-mips Content-Length: 691 Lines: 26 MIPS: Enable prefetch option for VR5500 processor Signed-off-by: Shinya Kuribayashi --- Hi Ralf, I haven't finished fixing up for VR5500 processor support, sigh :-( I hope this is the last one, and don't miss anything essential. Shinya arch/mips/mm/c-r4k.c | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index c43f4b2..b42b9d2 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -781,6 +781,7 @@ static void __cpuinit probe_pcache(void) c->dcache.waybit = 0; c->options |= MIPS_CPU_CACHE_CDEX_P; + c->options |= MIPS_CPU_PREFETCH; break; case CPU_TX49XX: From umeshyv@gmail.com Tue Mar 17 06:59:55 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 17 Mar 2009 07:00:01 +0000 (GMT) Received: from rv-out-0708.google.com ([209.85.198.242]:9605 "EHLO rv-out-0708.google.com") by ftp.linux-mips.org with ESMTP id S21368974AbZCQG7z (ORCPT ); Tue, 17 Mar 2009 06:59:55 +0000 Received: by rv-out-0708.google.com with SMTP id c5so3630765rvf.24 for ; Mon, 16 Mar 2009 23:59:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:in-reply-to:references :date:message-id:subject:from:to:cc:content-type; bh=xbhLTBcoGc86qykosa01mCah8taPLNV2Z0uDthakn2w=; b=ocPFphurV/LhJTi5Oz/QTXfkFldHmuw9t8KGYb/ero1T6ge99IAB6UnXSLQFNJx8WV MWSufjcaCF9D6rL8mbQBIA+3qug7R/xsdRQxozuErpLGNnCJwep3JxiOAVcrbVNyeXQV Ot+5hGcvxygfd9vN46fpwfvGBEcYSEBQT8u9E= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type; b=cDoMexIhEuRTagsqv5Y4C0mHMelJodhzIL4/vMJtdZY37IWHObwCmVScjIRYoofacz qQu/EPc/HDEEAWuAgbczP9a3uXyqULM7HvjeX0kOEPH+6NJBGhPTZMw8OxuIMFVKg9pR MOlynEHOlaRtn0Oo5Y8+WsclqY8wzPEMZ5CuA= MIME-Version: 1.0 Received: by 10.142.174.8 with SMTP id w8mr2620555wfe.207.1237273193212; Mon, 16 Mar 2009 23:59:53 -0700 (PDT) In-Reply-To: <1237211261.7473.3.camel@kh-d820> References: <1237211261.7473.3.camel@kh-d820> Date: Tue, 17 Mar 2009 12:29:53 +0530 Message-ID: Subject: Re: linux-2.6.28.4 regarding From: umeshyv To: Kevin Hickey Cc: linux-mips@linux-mips.org Content-Type: multipart/alternative; boundary=000e0cd22d522bfa1c04654b1dbe Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22090 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: umeshyv@gmail.com Precedence: bulk X-list: linux-mips Content-Length: 1343 Lines: 31 --000e0cd22d522bfa1c04654b1dbe Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Hi Thanks for your reply.My request is can you send the patch as files so that I dont make any mistakes in applying patch.Is there any news updates for media player and MAE player since I download the older version since I use buildroot (uclibc) ,I was ended up with errors and actually I would like to know whether anyone tried to compile media player and MAE driver using buildroot and is there any updations.Please kindly update me waiting for your valuable suggestions and help. Thanks & Regards Umamahesh Y V India --000e0cd22d522bfa1c04654b1dbe Content-Type: text/html; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Hi
Thanks for your reply.My request is can you send the patch as files s= o that I dont make any mistakes in applying patch.Is there any news updates= for media player and MAE player since I download the older version since I= use buildroot (uclibc) ,I was ended up with errors and actually I would li= ke to know whether anyone tried to compile media player and MAE driver usin= g buildroot and is there any updations.Please kindly update me waiting for = your valuable suggestions and help.

Thanks & Regards
Umamahesh Y V
India
--000e0cd22d522bfa1c04654b1dbe-- From anemo@mba.ocn.ne.jp Tue Mar 17 16:09:45 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 17 Mar 2009 16:09:52 +0000 (GMT) Received: from mba.ocn.ne.jp ([122.1.235.107]:37853 "HELO smtp.mba.ocn.ne.jp") by ftp.linux-mips.org with SMTP id S21369100AbZCQQJp convert rfc822-to-8bit (ORCPT ); Tue, 17 Mar 2009 16:09:45 +0000 Received: from localhost (p3110-ipad206funabasi.chiba.ocn.ne.jp [222.145.77.110]) by smtp.mba.ocn.ne.jp (Postfix) with ESMTP id 51961A9DF; Wed, 18 Mar 2009 01:09:37 +0900 (JST) Date: Wed, 18 Mar 2009 01:09:39 +0900 (JST) Message-Id: <20090318.010939.128619068.anemo@mba.ocn.ne.jp> To: dan.j.williams@intel.com Cc: linux-mips@linux-mips.org, ralf@linux-mips.org, linux-kernel@vger.kernel.org, haavard.skinnemoen@atmel.com Subject: Re: [PATCH 1/2] dmaengine: TXx9 Soc DMA Controller driver From: Atsushi Nemoto In-Reply-To: References: <1237240246.27945.6.camel@dwillia2-linux.ch.intel.com> <20090317.112019.147212126.nemoto@toshiba-tops.co.jp> X-Fingerprint: 6ACA 1623 39BD 9A94 9B1A B746 CA77 FE94 2874 D52F X-Pgp-Public-Key: http://wwwkeys.pgp.net/pks/lookup?op=get&search=0x2874D52F X-Mailer: Mew version 5.2 on Emacs 21.4 / Mule 5.0 (SAKAKI) Mime-Version: 1.0 Content-Type: Text/Plain; charset=iso-8859-1 Content-Transfer-Encoding: 8BIT Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22091 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anemo@mba.ocn.ne.jp Precedence: bulk X-list: linux-mips Content-Length: 2411 Lines: 74 On Mon, 16 Mar 2009 21:52:10 -0700, Dan Williams wrote: > > Hmm.. why idr_ref is dynamically allocated? Just putting it in > > dma_device makes thing more simple, no? > > The sysfs device has a longer lifetime than dma_device. See commit > 41d5e59c [1]. The sysfs device for dma_chan (dma_chan_dev) has a shorter lifetime than dma_device, doesn't it? I mean something like this (only compile tested): ------------------------------------------------------ Subject: dmaengine: Add idr_ref to dma_device This fixes memory leak on some error path. Signed-off-by: Atsushi Nemoto --- diff --git a/drivers/dma/dmaengine.c b/drivers/dma/dmaengine.c index 280a9d2..0708931 100644 --- a/drivers/dma/dmaengine.c +++ b/drivers/dma/dmaengine.c @@ -153,7 +153,6 @@ static void chan_dev_release(struct device *dev) mutex_lock(&dma_list_mutex); idr_remove(&dma_idr, chan_dev->dev_id); mutex_unlock(&dma_list_mutex); - kfree(chan_dev->idr_ref); } kfree(chan_dev); } @@ -610,7 +609,6 @@ int dma_async_device_register(struct dma_device *device) { int chancnt = 0, rc; struct dma_chan* chan; - atomic_t *idr_ref; if (!device) return -ENODEV; @@ -637,10 +635,7 @@ int dma_async_device_register(struct dma_device *device) BUG_ON(!device->device_issue_pending); BUG_ON(!device->dev); - idr_ref = kmalloc(sizeof(*idr_ref), GFP_KERNEL); - if (!idr_ref) - return -ENOMEM; - atomic_set(idr_ref, 0); + atomic_set(&device->idr_ref, 0); idr_retry: if (!idr_pre_get(&dma_idr, GFP_KERNEL)) return -ENOMEM; @@ -667,9 +662,9 @@ int dma_async_device_register(struct dma_device *device) chan->dev->device.class = &dma_devclass; chan->dev->device.parent = device->dev; chan->dev->chan = chan; - chan->dev->idr_ref = idr_ref; + chan->dev->idr_ref = &device->idr_ref; chan->dev->dev_id = device->dev_id; - atomic_inc(idr_ref); + atomic_inc(&device->idr_ref); dev_set_name(&chan->dev->device, "dma%dchan%d", device->dev_id, chan->chan_id); diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h index 1956c8d..9e99d82 100644 --- a/include/linux/dmaengine.h +++ b/include/linux/dmaengine.h @@ -234,6 +234,7 @@ struct dma_device { int dev_id; struct device *dev; + atomic_t idr_ref; int (*device_alloc_chan_resources)(struct dma_chan *chan); void (*device_free_chan_resources)(struct dma_chan *chan); From sshtylyov@ru.mvista.com Tue Mar 17 16:47:10 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 17 Mar 2009 16:47:17 +0000 (GMT) Received: from h155.mvista.com ([63.81.120.155]:8735 "EHLO imap.sh.mvista.com") by ftp.linux-mips.org with ESMTP id S21366146AbZCQQrK (ORCPT ); Tue, 17 Mar 2009 16:47:10 +0000 Received: from [192.168.1.234] (unknown [10.150.0.9]) by imap.sh.mvista.com (Postfix) with ESMTP id AB6893EC9; Tue, 17 Mar 2009 09:47:06 -0700 (PDT) Message-ID: <49BFD438.3070805@ru.mvista.com> Date: Tue, 17 Mar 2009 19:47:52 +0300 From: Sergei Shtylyov Organization: MontaVista Software Inc. User-Agent: Mozilla/5.0 (X11; U; Linux i686; rv:1.7.2) Gecko/20040803 X-Accept-Language: ru, en-us, en-gb MIME-Version: 1.0 To: Shinya Kuribayashi Cc: linux-mips@linux-mips.org, ralf@linux-mips.org Subject: Re: MIPS: Enable prefetch option for VR5500 processor References: <49ACF2EF.3080903@necel.com> <49BF4410.8080006@necel.com> In-Reply-To: <49BF4410.8080006@necel.com> Content-Type: text/plain; charset=us-ascii; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22092 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sshtylyov@ru.mvista.com Precedence: bulk X-list: linux-mips Content-Length: 753 Lines: 30 Hello. Shinya Kuribayashi wrote: > MIPS: Enable prefetch option for VR5500 processor > Signed-off-by: Shinya Kuribayashi > --- > Hi Ralf, > I haven't finished fixing up for VR5500 processor support, sigh :-( > I hope this is the last one, and don't miss anything essential. > Shinya > diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c > index c43f4b2..b42b9d2 100644 > --- a/arch/mips/mm/c-r4k.c > +++ b/arch/mips/mm/c-r4k.c > @@ -781,6 +781,7 @@ static void __cpuinit probe_pcache(void) > c->dcache.waybit = 0; > > c->options |= MIPS_CPU_CACHE_CDEX_P; > + c->options |= MIPS_CPU_PREFETCH; Why not: c->options |= MIPS_CPU_CACHE_CDEX_P | MIPS_CPU_PREFETCH; WBR, Sergei From dan.j.williams@gmail.com Tue Mar 17 17:02:16 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 17 Mar 2009 17:02:23 +0000 (GMT) Received: from wa-out-1112.google.com ([209.85.146.182]:23912 "EHLO wa-out-1112.google.com") by ftp.linux-mips.org with ESMTP id S21369186AbZCQRCQ convert rfc822-to-8bit (ORCPT ); Tue, 17 Mar 2009 17:02:16 +0000 Received: by wa-out-1112.google.com with SMTP id n4so39823wag.0 for ; Tue, 17 Mar 2009 10:02:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:sender:received:in-reply-to :references:date:x-google-sender-auth:message-id:subject:from:to:cc :content-type:content-transfer-encoding; bh=o/O0DAgTOtEHU8RYPwJ8tU43q8nCF8+0R641sYeP+4Y=; b=k3EF8wKV0u4P27Z6cCnTXLR7RMvJ6IbBWt0Idp6eIi3Rqhe2bWalFq5rMdgLWJZqBk XXmgId+gVHDbv9D8XKFLN60xujxMHIbUAtYqCCjAWpoaP00S7I9kJOCz8p6Cs84PoLsu jKByAop4fdU8zz60VhYYFAw2MaZge9nBRjnAA= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:sender:in-reply-to:references:date :x-google-sender-auth:message-id:subject:from:to:cc:content-type :content-transfer-encoding; b=EZQbcPDxYrEc/5e5NFfsf1Icz8kWFMWrglBVAXzo3D5njEHS8sNLxz7e4mcLfCian6 mVpz5/gHm2j4LNItfMBdSgQG0O/2webxN07aqgM4dcCcfaWoQEm42yB14JHHO+/8VG5s GdG9m6jhZ4SGw6SxRT+QbZiu++tiTTnsFgs6U= MIME-Version: 1.0 Received: by 10.115.32.1 with SMTP id k1mr148480waj.66.1237309334166; Tue, 17 Mar 2009 10:02:14 -0700 (PDT) In-Reply-To: <20090318.010939.128619068.anemo@mba.ocn.ne.jp> References: <1237240246.27945.6.camel@dwillia2-linux.ch.intel.com> <20090317.112019.147212126.nemoto@toshiba-tops.co.jp> <20090318.010939.128619068.anemo@mba.ocn.ne.jp> Date: Tue, 17 Mar 2009 10:02:14 -0700 X-Google-Sender-Auth: a990513ae9a75193 Message-ID: Subject: Re: [PATCH 1/2] dmaengine: TXx9 Soc DMA Controller driver From: Dan Williams To: Atsushi Nemoto Cc: linux-mips@linux-mips.org, ralf@linux-mips.org, linux-kernel@vger.kernel.org, haavard.skinnemoen@atmel.com Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22093 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dan.j.williams@intel.com Precedence: bulk X-list: linux-mips Content-Length: 644 Lines: 14 On Tue, Mar 17, 2009 at 9:09 AM, Atsushi Nemoto wrote: > On Mon, 16 Mar 2009 21:52:10 -0700, Dan Williams wrote: >> > Hmm.. why idr_ref is dynamically allocated? Just putting it in >> > dma_device makes thing more simple, no? >> >> The sysfs device has a longer lifetime than dma_device. See commit >> 41d5e59c [1]. > > The sysfs device for dma_chan (dma_chan_dev) has a shorter lifetime > than dma_device, doesn't it? No, dma_async_device_unregister(), and the freeing of dma_device, may finish before chan_dev_release is called. Userspace gates the final release of dma_chan_dev objects. From shinya.kuribayashi@necel.com Wed Mar 18 00:03:10 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 18 Mar 2009 00:03:19 +0000 (GMT) Received: from TYO201.gate.nec.co.jp ([202.32.8.193]:50601 "EHLO tyo201.gate.nec.co.jp") by ftp.linux-mips.org with ESMTP id S21369220AbZCRADK (ORCPT ); Wed, 18 Mar 2009 00:03:10 +0000 Received: from relay11.aps.necel.com ([10.29.19.46]) by tyo201.gate.nec.co.jp (8.13.8/8.13.4) with ESMTP id n2I02qO3005077; Wed, 18 Mar 2009 09:03:06 +0900 (JST) Received: from realmbox21.aps.necel.com ([10.29.19.32] [10.29.19.32]) by relay11.aps.necel.com with ESMTP; Wed, 18 Mar 2009 09:03:06 +0900 Received: from [10.114.181.78] ([10.114.181.78] [10.114.181.78]) by mbox02.aps.necel.com with ESMTP; Wed, 18 Mar 2009 09:03:06 +0900 Message-Id: <49C03A71.1070905@necel.com> Date: Wed, 18 Mar 2009 09:04:01 +0900 From: Shinya Kuribayashi User-Agent: Thunderbird 2.0.0.19 (Windows/20081209) MIME-Version: 1.0 To: Sergei Shtylyov CC: linux-mips@linux-mips.org, ralf@linux-mips.org Subject: [PATCH revised] MIPS: Enable prefetch option for VR5500 processor References: <49ACF2EF.3080903@necel.com> <49BF4410.8080006@necel.com> <49BFD438.3070805@ru.mvista.com> In-Reply-To: <49BFD438.3070805@ru.mvista.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22094 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: shinya.kuribayashi@necel.com Precedence: bulk X-list: linux-mips Content-Length: 687 Lines: 29 Signed-off-by: Shinya Kuribayashi --- Hi, Sergei Shtylyov wrote: > Why not: > > c->options |= MIPS_CPU_CACHE_CDEX_P | MIPS_CPU_PREFETCH; Thank you, patch revised. Shinya arch/mips/mm/c-r4k.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index c43f4b2..871e828 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -780,7 +780,7 @@ static void __cpuinit probe_pcache(void) c->dcache.ways = 2; c->dcache.waybit = 0; - c->options |= MIPS_CPU_CACHE_CDEX_P; + c->options |= MIPS_CPU_CACHE_CDEX_P | MIPS_CPU_PREFETCH; break; case CPU_TX49XX: From anemo@mba.ocn.ne.jp Wed Mar 18 00:49:46 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 18 Mar 2009 00:49:54 +0000 (GMT) Received: from fwtops.0.225.230.202.in-addr.arpa ([202.230.225.126]:5520 "EHLO topsms.toshiba-tops.co.jp") by ftp.linux-mips.org with ESMTP id S21369240AbZCRAtq convert rfc822-to-8bit (ORCPT ); Wed, 18 Mar 2009 00:49:46 +0000 Received: from topsms.toshiba-tops.co.jp (localhost.localdomain [127.0.0.1]) by localhost.toshiba-tops.co.jp (Postfix) with ESMTP id 2C63B42CE2; Wed, 18 Mar 2009 09:43:05 +0900 (JST) Received: from srd2sd.toshiba-tops.co.jp (srd2sd.toshiba-tops.co.jp [172.17.28.2]) by topsms.toshiba-tops.co.jp (Postfix) with ESMTP id 1FCE642B7A; Wed, 18 Mar 2009 09:43:05 +0900 (JST) Received: from localhost (fragile [172.17.28.65]) by srd2sd.toshiba-tops.co.jp (8.12.10/8.12.10) with ESMTP id n2I0nZnf030763; Wed, 18 Mar 2009 09:49:36 +0900 (JST) (envelope-from anemo@mba.ocn.ne.jp) Date: Wed, 18 Mar 2009 09:49:35 +0900 (JST) Message-Id: <20090318.094935.238694196.nemoto@toshiba-tops.co.jp> To: dan.j.williams@intel.com Cc: linux-mips@linux-mips.org, ralf@linux-mips.org, linux-kernel@vger.kernel.org, haavard.skinnemoen@atmel.com Subject: Re: [PATCH 1/2] dmaengine: TXx9 Soc DMA Controller driver From: Atsushi Nemoto In-Reply-To: References: <20090318.010939.128619068.anemo@mba.ocn.ne.jp> X-Fingerprint: 6ACA 1623 39BD 9A94 9B1A B746 CA77 FE94 2874 D52F X-Pgp-Public-Key: http://wwwkeys.pgp.net/pks/lookup?op=get&search=0x2874D52F X-Mailer: Mew version 6.1 on Emacs 22.2 / Mule 5.0 (SAKAKI) Mime-Version: 1.0 Content-Type: Text/Plain; charset=iso-8859-1 Content-Transfer-Encoding: 8BIT Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22095 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anemo@mba.ocn.ne.jp Precedence: bulk X-list: linux-mips Content-Length: 812 Lines: 21 On Tue, 17 Mar 2009 10:02:14 -0700, Dan Williams wrote: > >> The sysfs device has a longer lifetime than dma_device. See commit > >> 41d5e59c [1]. > > > > The sysfs device for dma_chan (dma_chan_dev) has a shorter lifetime > > than dma_device, doesn't it? > > No, dma_async_device_unregister(), and the freeing of dma_device, may > finish before chan_dev_release is called. Userspace gates the final > release of dma_chan_dev objects. You mean, if the sysfs device file was opened when dma_async_device_unregister() was called, the sysfs device will not be released until the sysfs device file is closed, right? If so I can see. BTW, there are another holes in dma_async_device_register. If idr_pre_get or idr_get_new was failed, idr_ref will not be freed. --- Atsushi Nemoto From dan.j.williams@gmail.com Wed Mar 18 01:23:49 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 18 Mar 2009 01:23:56 +0000 (GMT) Received: from yx-out-1718.google.com ([74.125.44.157]:65531 "EHLO yx-out-1718.google.com") by ftp.linux-mips.org with ESMTP id S21369164AbZCRBXt convert rfc822-to-8bit (ORCPT ); Wed, 18 Mar 2009 01:23:49 +0000 Received: by yx-out-1718.google.com with SMTP id 3so182340yxi.24 for ; Tue, 17 Mar 2009 18:23:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:sender:received:in-reply-to :references:date:x-google-sender-auth:message-id:subject:from:to:cc :content-type:content-transfer-encoding; bh=q+UUpo1M3Pk8FcE8+NLeOArNUlMO+QfeBw4F84KMbJE=; b=JVwML4bJzEjP+Mm8fOYZ1IeT4q7qw+b+4Jx2JVAbpFxwBaGDZmgILSte+C3E4VA3kF /FRNdm5AmamaPW6CAZe3qeuha7yczM2luybbHnUglTVAwoS7c8iqDmT9eCQ0B8Ozg18S i1ZpddrnjpYcEXZWc30MCuNUP8CPCPFy8nOcQ= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:sender:in-reply-to:references:date :x-google-sender-auth:message-id:subject:from:to:cc:content-type :content-transfer-encoding; b=CH9mMjHavDdvxhVHtYjdx+ZUy3xBxKnq64nXM1hgSET19K8scRfyit0iP43gfswgW0 7JukRp37rZ+CM9UtL1kpgC24vl1S3QEV3s0q6hiU2gO5Kon+CntCvfA8/MM3ik+5x+TV DyabHlt/lmiM2k55wjDXiBmzkDxMBXNQlCrKw= MIME-Version: 1.0 Received: by 10.114.147.7 with SMTP id u7mr386842wad.138.1237339427032; Tue, 17 Mar 2009 18:23:47 -0700 (PDT) In-Reply-To: <20090318.094935.238694196.nemoto@toshiba-tops.co.jp> References: <20090318.010939.128619068.anemo@mba.ocn.ne.jp> <20090318.094935.238694196.nemoto@toshiba-tops.co.jp> Date: Tue, 17 Mar 2009 18:23:46 -0700 X-Google-Sender-Auth: c02529558b46bc28 Message-ID: Subject: Re: [PATCH 1/2] dmaengine: TXx9 Soc DMA Controller driver From: Dan Williams To: Atsushi Nemoto Cc: linux-mips@linux-mips.org, ralf@linux-mips.org, linux-kernel@vger.kernel.org, haavard.skinnemoen@atmel.com Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22096 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dan.j.williams@intel.com Precedence: bulk X-list: linux-mips Content-Length: 647 Lines: 15 On Tue, Mar 17, 2009 at 5:49 PM, Atsushi Nemoto wrote: > On Tue, 17 Mar 2009 10:02:14 -0700, Dan Williams wrote: > BTW, there are another holes in dma_async_device_register. If > idr_pre_get or idr_get_new was failed, idr_ref will not be freed. Thanks for these fixlets, I appreciate it. Now, back to the issue at hand. Does your driver still need direct control over chan->chan_id, or can it now rely on the fact that dma_async_device_register() will fail if a channel is not initialized? Or, just use some platform_data to identify the channel in the same manner as atmel-mci? Regards, Dan From anemo@mba.ocn.ne.jp Wed Mar 18 02:02:03 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 18 Mar 2009 02:02:10 +0000 (GMT) Received: from fwtops.0.225.230.202.in-addr.arpa ([202.230.225.126]:12492 "EHLO topsms.toshiba-tops.co.jp") by ftp.linux-mips.org with ESMTP id S21367690AbZCRCCD (ORCPT ); Wed, 18 Mar 2009 02:02:03 +0000 Received: from topsms.toshiba-tops.co.jp (localhost.localdomain [127.0.0.1]) by localhost.toshiba-tops.co.jp (Postfix) with ESMTP id 6E45C42B62; Wed, 18 Mar 2009 10:55:23 +0900 (JST) Received: from srd2sd.toshiba-tops.co.jp (srd2sd.toshiba-tops.co.jp [172.17.28.2]) by topsms.toshiba-tops.co.jp (Postfix) with ESMTP id 62B0C18DBD; Wed, 18 Mar 2009 10:55:23 +0900 (JST) Received: from localhost (fragile [172.17.28.65]) by srd2sd.toshiba-tops.co.jp (8.12.10/8.12.10) with ESMTP id n2I21tnf031027; Wed, 18 Mar 2009 11:01:55 +0900 (JST) (envelope-from anemo@mba.ocn.ne.jp) Date: Wed, 18 Mar 2009 11:01:54 +0900 (JST) Message-Id: <20090318.110154.76582864.nemoto@toshiba-tops.co.jp> To: dan.j.williams@intel.com Cc: linux-mips@linux-mips.org, ralf@linux-mips.org, linux-kernel@vger.kernel.org, haavard.skinnemoen@atmel.com Subject: Re: [PATCH 1/2] dmaengine: TXx9 Soc DMA Controller driver From: Atsushi Nemoto In-Reply-To: References: <20090318.094935.238694196.nemoto@toshiba-tops.co.jp> X-Fingerprint: 6ACA 1623 39BD 9A94 9B1A B746 CA77 FE94 2874 D52F X-Pgp-Public-Key: http://wwwkeys.pgp.net/pks/lookup?op=get&search=0x2874D52F Organization: TOSHIBA Personal Computer System Corporation X-Mailer: Mew version 6.1 on Emacs 22.2 / Mule 5.0 (SAKAKI) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22097 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anemo@mba.ocn.ne.jp Precedence: bulk X-list: linux-mips Content-Length: 832 Lines: 19 On Tue, 17 Mar 2009 18:23:46 -0700, Dan Williams wrote: > Now, back to the issue at hand. Does your driver still need direct > control over chan->chan_id, or can it now rely on the fact that > dma_async_device_register() will fail if a channel is not initialized? > Or, just use some platform_data to identify the channel in the same > manner as atmel-mci? Yes, I still want to control chan->chan_id. The atmel-mci does not select "channel". It just pick the first usable channel of the dma_device specified by platform_data. I suppose dw_dmac is symmetric (it can use any channel for any slave). But TXx9 SoC DMAC channels are hardwired to each peripheral devices. And I want to call Channel-3 of DMAC-0 "dma0chan3" even if Channel-2 was assigned to for public memcpy channel. --- Atsushi Nemoto From dan.j.williams@gmail.com Wed Mar 18 17:26:16 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 18 Mar 2009 17:26:24 +0000 (GMT) Received: from rv-out-0708.google.com ([209.85.198.244]:35828 "EHLO rv-out-0708.google.com") by ftp.linux-mips.org with ESMTP id S21369439AbZCRR0Q convert rfc822-to-8bit (ORCPT ); Wed, 18 Mar 2009 17:26:16 +0000 Received: by rv-out-0708.google.com with SMTP id c5so112952rvf.24 for ; Wed, 18 Mar 2009 10:26:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:sender:received:in-reply-to :references:date:x-google-sender-auth:message-id:subject:from:to:cc :content-type:content-transfer-encoding; bh=0qVPW0G0Tse6YsIcJhqNwRYqUkjthcU3O4ni+S1XXek=; b=JeYShPRstK0P5uFFClVv+Jjp2eoQUFriY5tynFhxFzFBK/HxQRfUmQd01RziEcsRyp yVx+z0HhUsqnAUu17PzmiASiXsH3k3DWNCAxkp/rptMu69ftwbEVHSjlClllJVk7ad3r 1OwAAkwnz3PgEuZE7nRO2PFFsVZfUSVUBaN1U= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:sender:in-reply-to:references:date :x-google-sender-auth:message-id:subject:from:to:cc:content-type :content-transfer-encoding; b=ZrSv2qsjXBUbpsHC+56sSwYdxPvd9k2aBeHehz/CNiPasckXoefvaXVuoOnBvgcOeW etKkmBjMnEToEBwkxOMF/8kt37Eo4YBuijYQRAHP9qVmISrezOugwPM9KGi0V9d4AQVo Pn1l8WkDCUgvwAPOQ8SqHcHmvhlYvj52QSl4Y= MIME-Version: 1.0 Received: by 10.114.37.1 with SMTP id k1mr906098wak.172.1237397173491; Wed, 18 Mar 2009 10:26:13 -0700 (PDT) In-Reply-To: <20090318.110154.76582864.nemoto@toshiba-tops.co.jp> References: <20090318.094935.238694196.nemoto@toshiba-tops.co.jp> <20090318.110154.76582864.nemoto@toshiba-tops.co.jp> Date: Wed, 18 Mar 2009 10:26:13 -0700 X-Google-Sender-Auth: 28eaa50d7ef021f8 Message-ID: Subject: Re: [PATCH 1/2] dmaengine: TXx9 Soc DMA Controller driver From: Dan Williams To: Atsushi Nemoto Cc: linux-mips@linux-mips.org, ralf@linux-mips.org, linux-kernel@vger.kernel.org, haavard.skinnemoen@atmel.com Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22098 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dan.j.williams@intel.com Precedence: bulk X-list: linux-mips Content-Length: 1314 Lines: 27 On Tue, Mar 17, 2009 at 7:01 PM, Atsushi Nemoto wrote: > On Tue, 17 Mar 2009 18:23:46 -0700, Dan Williams wrote: >> Or, just use some platform_data to identify the channel in the same >> manner as atmel-mci? > > Yes, I still want to control chan->chan_id. > > The atmel-mci does not select "channel". It just pick the first > usable channel of the dma_device specified by platform_data. I > suppose dw_dmac is symmetric (it can use any channel for any slave). You are right, it does not hardwire the channel, but it does hardwire the device, see at32_add_device_mci [1]. > But TXx9 SoC DMAC channels are hardwired to each peripheral devices. I think creating a dma_device instance per channel and specifying that device like atmel-mci is the more future-proof way to go. > And I want to call Channel-3 of DMAC-0 "dma0chan3" even if Channel-2 > was assigned to for public memcpy channel. The problem is you could pass in the chan_id to guarantee 'chan3', but there is no guarantee that you will get 'dma0', as the driver has no knowledge of what other dma devices may be in the system. [1] http://git.kernel.org/?p=linux/kernel/git/torvalds/linux-2.6.git;a=blob;f=arch/avr32/mach-at32ap/at32ap700x.c;h=3fbfd1e32a9ee79af4f4545d95a9543b9070d189;hb=HEAD#l1327 From craig@nadler.us Thu Mar 19 23:27:36 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 19 Mar 2009 23:27:43 +0000 (GMT) Received: from ultra1.eskimo.com ([204.122.16.64]:15494 "EHLO ultra1.eskimo.com") by ftp.linux-mips.org with ESMTP id S21369669AbZCSX1g (ORCPT ); Thu, 19 Mar 2009 23:27:36 +0000 Received: from ultra1.eskimo.com (localhost [127.0.0.1]) by ultra1.eskimo.com (8.14.0/8.14.0) with ESMTP id n2JNRVGd031323 for ; Thu, 19 Mar 2009 16:27:31 -0700 Received: (from sqrlmail@localhost) by ultra1.eskimo.com (8.14.0/8.12.10/Submit) id n2JNRQKV031305; Thu, 19 Mar 2009 19:27:26 -0400 X-Authentication-Warning: ultra1.eskimo.com: sqrlmail set sender to craig@nadler.us using -f Received: from fw.drs-ss.com ([63.237.78.40]) (proxying for 192.168.22.238) (SquirrelMail authenticated user cwn) by www.eskimo.com with HTTP; Thu, 19 Mar 2009 19:27:25 -0400 (EDT) Message-ID: <0124667e2b16bc6c1ec9870b17e5ddbb.squirrel@www.eskimo.com> Date: Thu, 19 Mar 2009 19:27:25 -0400 (EDT) Subject: PCI IO access problem on BCM1480 From: "Craig Nadler" To: linux-mips@linux-mips.org User-Agent: SquirrelMail/1.4.17 MIME-Version: 1.0 Content-Type: text/plain;charset=iso-8859-1 Content-Transfer-Encoding: 8bit X-Priority: 3 (Normal) Importance: Normal Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22099 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: craig@nadler.us Precedence: bulk X-list: linux-mips Content-Length: 11593 Lines: 263 I'm have problems using a Technobox 4960 4-port RS-232 PMC (PCI) card on a board based on the Broadcom 1480 (MIPS) SOC. Each serial port on the PMC card uses a 16550A UART accessed using BAR2 thru BAR5. The BCM1480 based system board is running Linux 2.6.20.1 and a boot loader software called CFE from Broadcom. I/O port accesses over the PCI bus from the CPU to the PMC card don't seem to work. Any time I try to read an I/O register over the PCI bus I get a "Data Bus Error" kernel panic. The SOC manual says that the base address for PCI I/O Space is 0x2C000000. Below is the output of lspci -vvx to show what is on the PCI bus and how it's configured. Below that is a kernel panic caused by reading the first byte of the IO registers for the first RS-232 serial port on the card. Any help would be very much appreciated. Best Regards, Craig Nadler root@mobo-5 /root# lspci -vvx 0000:00:00.0 Host bridge: Broadcom Corporation SiByte BCM1x55/BCM1x80 PCI (rev 01) Subsystem: Broadcom Corporation: Unknown device 1280 Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- SERR- (64-bit, prefetchable) Expansion ROM at 73000000 [disabled] [size=64K] Capabilities: [d0] Message Signalled Interrupts: 64bit+ Queue=0/5 Enable- Address: 0000000000000000 Data: 0000 Capabilities: [e0] PCI-X non-bridge device. Command: DPERE- ERO+ RBC=0 OST=3 Status: Bus=0 Dev=0 Func=0 64bit+ 133MHz+ SCD- USC-, DC=bridge, DMMRBC=0, DMOST=3, DMCRS=0, RSCEM- 00: 6d 16 12 00 46 01 b0 22 01 00 00 06 08 fc 00 00 10: 0c 00 00 60 00 00 00 00 0c 00 00 70 00 00 00 00 20: 0c 00 00 00 00 00 00 00 00 00 00 00 6d 16 80 12 30: 00 00 00 73 d0 00 00 00 00 00 00 00 08 01 00 00 0000:00:01.0 Bridge: Tundra Semiconductor Corp. Tsi148 [Tempe] (rev 01) Subsystem: Tundra Semiconductor Corp.: Unknown device 0000 Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- Status: Cap+ 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- SERR- TAbort- SERR- Reset- FastB2B- Capabilities: [40] #08 [2001] Capabilities: [5c] #08 [4000] Capabilities: [74] #08 [b800] 00: 6d 16 11 00 47 01 10 00 01 00 04 06 00 00 01 00 10: 00 00 00 00 00 00 00 00 00 01 01 00 11 01 00 00 20: 10 00 00 00 11 00 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 00 00 02 00 0001:00:02.0 PCI bridge: Broadcom Corporation SiByte BCM1x80 Secondary bridge (rev 01) (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- SERR- Reset- FastB2B- Capabilities: [40] #08 [2001] Capabilities: [5c] #08 [4000] Capabilities: [74] #08 [b800] 00: 6d 16 11 00 47 01 10 00 01 00 04 06 00 00 01 00 10: 00 00 00 00 00 00 00 00 00 02 04 00 81 81 00 20 20: 00 41 00 41 11 00 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 00 00 02 00 0001:00:04.0 Host bridge: Broadcom Corporation SiByte BCM1x80 Host Bridge (rev 01) Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR- FastB2B- Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- SERR- (32-bit, prefetchable) Region 2: Memory at 70000000 (32-bit, prefetchable) [size=4K] Region 4: Memory at (64-bit, prefetchable) 00: 6d 16 14 00 46 00 00 20 01 00 00 06 00 00 00 00 10: 08 00 00 60 08 00 00 40 08 00 00 70 00 00 00 00 20: 0c 00 00 00 00 00 00 00 00 00 00 00 ff ff 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 ff 01 00 00 0001:02:01.0 PCI bridge: Advanced Micro Devices [AMD] AMD-8131 PCI-X Bridge (rev 12) (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr+ Stepping- SERR+ FastB2B- Status: Cap+ 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- SERR- Reset- FastB2B- Capabilities: [a0] Capabilities: [b8] #08 [8000] Capabilities: [c0] #08 [0041] 00: 22 10 50 74 57 01 30 02 12 00 04 06 00 ff 81 00 10: 00 00 00 00 00 00 00 00 02 03 03 00 81 81 20 22 20: 10 00 00 00 11 00 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 a0 00 00 00 00 00 00 00 00 00 02 00 0001:02:01.1 PIC: Advanced Micro Devices [AMD] AMD-8131 PCI-X IOAPIC (rev 01) (prog-if 10 [IO-APIC]) Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- SERR- TAbort- SERR- Reset- FastB2B- Capabilities: [a0] Capabilities: [b8] #08 [8000] 00: 22 10 50 74 57 01 30 02 12 00 04 06 00 ff 81 00 10: 00 00 00 00 00 00 00 00 02 04 04 00 11 01 20 22 20: 10 00 00 00 11 00 01 00 00 00 00 00 00 00 00 00 30: ff ff 00 00 a0 00 00 00 00 00 00 00 00 00 02 00 0001:02:02.1 PIC: Advanced Micro Devices [AMD] AMD-8131 PCI-X IOAPIC (rev 01) (prog-if 10 [IO-APIC]) Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- SERR- TAbort- SERR- ] xyly_ioctl+0x5dc/0xaa8 [xyly] [] do_ioctl+0x9c/0xe0 [] vfs_ioctl+0x260/0x410 [] sys_ioctl+0xb4/0x100 [] handle_sys64+0x54/0x70 Code: 00000000 dc440000 ffa20020 0801da7e df830028 1085001c 24070008 1487ff6 5 Segmentation fault From tsbogend@alpha.franken.de Fri Mar 20 10:24:34 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 20 Mar 2009 10:24:42 +0000 (GMT) Received: from elvis.franken.de ([193.175.24.41]:59588 "EHLO elvis.franken.de") by ftp.linux-mips.org with ESMTP id S21369799AbZCTKYe (ORCPT ); Fri, 20 Mar 2009 10:24:34 +0000 Received: from uucp (helo=solo.franken.de) by elvis.franken.de with local-bsmtp (Exim 3.36 #1) id 1Lkbtw-0007Lf-00; Fri, 20 Mar 2009 11:24:32 +0100 Received: by solo.franken.de (Postfix, from userid 1000) id 1E552C2B2E; Fri, 20 Mar 2009 11:15:49 +0100 (CET) Date: Fri, 20 Mar 2009 11:15:49 +0100 To: Craig Nadler Cc: linux-mips@linux-mips.org Subject: Re: PCI IO access problem on BCM1480 Message-ID: <20090320101548.GA6747@alpha.franken.de> References: <0124667e2b16bc6c1ec9870b17e5ddbb.squirrel@www.eskimo.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <0124667e2b16bc6c1ec9870b17e5ddbb.squirrel@www.eskimo.com> User-Agent: Mutt/1.5.13 (2006-08-11) From: tsbogend@alpha.franken.de (Thomas Bogendoerfer) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22100 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: tsbogend@alpha.franken.de Precedence: bulk X-list: linux-mips Content-Length: 669 Lines: 15 On Thu, Mar 19, 2009 at 07:27:25PM -0400, Craig Nadler wrote: > I'm have problems using a Technobox 4960 4-port RS-232 PMC (PCI) card > on a board based on the Broadcom 1480 (MIPS) SOC. Each serial port on > the PMC card uses a 16550A UART accessed using BAR2 thru BAR5. The > BCM1480 based system board is running Linux 2.6.20.1 and a boot > loader software called CFE from Broadcom. could you try a newer kernel ? I've fixed PCI IO access some time ago. It should be included in 2.6.25 and newer. Thomas. -- Crap can work. Given enough thrust pigs will fly, but it's not necessary a good idea. [ RFC1925, 2.3 ] From r0bertz@gentoo.org Fri Mar 20 19:10:42 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 20 Mar 2009 19:10:48 +0000 (GMT) Received: from apollo.i-cable.com ([203.83.115.103]:29648 "HELO apollo.i-cable.com") by ftp.linux-mips.org with SMTP id S21369896AbZCTTKm (ORCPT ); Fri, 20 Mar 2009 19:10:42 +0000 Received: (qmail 22764 invoked by uid 508); 20 Mar 2009 19:10:34 -0000 Received: from 203.83.114.122 by apollo (envelope-from , uid 505) with qmail-scanner-1.25 (clamdscan: 0.93.3/7730. Clear:RC:1(203.83.114.122):. Processed in 0.161682 secs); 20 Mar 2009 19:10:34 -0000 Received: from ip114122.hkicable.com (HELO xenon.i-cable.com) (203.83.114.122) by 0 with SMTP; 20 Mar 2009 19:10:34 -0000 Received: from localhost.localdomain (cm222-167-208-75.hkcable.com.hk [222.167.208.75]) by xenon.i-cable.com (8.13.5/8.13.5) with ESMTP id n2KJAW9w028117; Sat, 21 Mar 2009 03:10:33 +0800 (CST) From: Zhang Le To: linux-mips@linux-mips.org Cc: Zhang Le Subject: [PATCH] MIPS: rename CPU_LOONGSON2 to CPU_LOONGSON2E Date: Sat, 21 Mar 2009 03:10:20 +0800 Message-Id: <1237576220-4479-1-git-send-email-r0bertz@gentoo.org> X-Mailer: git-send-email 1.6.2 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22101 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: r0bertz@gentoo.org Precedence: bulk X-list: linux-mips Content-Length: 1502 Lines: 41 This is for future inclusion of Loongson 2F patches. Because Gcc 4.4 (not released yet) has different -march argument for these two CPUs, we should be able to distinguish them. Signed-off-by: Zhang Le --- arch/mips/Kconfig | 4 ++-- arch/mips/Makefile | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 206cb79..dcb675d 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -1014,8 +1014,8 @@ choice prompt "CPU type" default CPU_R4X00 -config CPU_LOONGSON2 - bool "Loongson 2" +config CPU_LOONGSON2E + bool "Loongson 2E" depends on SYS_HAS_CPU_LOONGSON2 select CPU_SUPPORTS_32BIT_KERNEL select CPU_SUPPORTS_64BIT_KERNEL diff --git a/arch/mips/Makefile b/arch/mips/Makefile index 22dab2e..097a7fa 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -119,7 +119,7 @@ cflags-$(CONFIG_CPU_R4300) += -march=r4300 -Wa,--trap cflags-$(CONFIG_CPU_VR41XX) += -march=r4100 -Wa,--trap cflags-$(CONFIG_CPU_R4X00) += -march=r4600 -Wa,--trap cflags-$(CONFIG_CPU_TX49XX) += -march=r4600 -Wa,--trap -cflags-$(CONFIG_CPU_LOONGSON2) += -march=r4600 -Wa,--trap +cflags-$(CONFIG_CPU_LOONGSON2E) += -march=r4600 -Wa,--trap cflags-$(CONFIG_CPU_MIPS32_R1) += $(call cc-option,-march=mips32,-mips32 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS32) \ -Wa,-mips32 -Wa,--trap cflags-$(CONFIG_CPU_MIPS32_R2) += $(call cc-option,-march=mips32r2,-mips32r2 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS32) \ -- 1.6.2 From robert.zhangle@gmail.com Fri Mar 20 19:24:27 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 20 Mar 2009 19:24:33 +0000 (GMT) Received: from xylophone.i-cable.com ([203.83.115.99]:4267 "HELO xylophone.i-cable.com") by ftp.linux-mips.org with SMTP id S21369901AbZCTTY1 (ORCPT ); Fri, 20 Mar 2009 19:24:27 +0000 Received: (qmail 2945 invoked by uid 508); 20 Mar 2009 19:24:24 -0000 Received: from 203.83.114.122 by xylophone (envelope-from , uid 505) with qmail-scanner-1.25 (clamdscan: 0.93.3/7737. Clear:RC:1(203.83.114.122):. Processed in 0.194305 secs); 20 Mar 2009 19:24:24 -0000 Received: from ip114122.hkicable.com (HELO xenon.i-cable.com) (203.83.114.122) by 0 with SMTP; 20 Mar 2009 19:24:23 -0000 Received: from localhost (cm222-167-208-75.hkcable.com.hk [222.167.208.75]) by xenon.i-cable.com (8.13.5/8.13.5) with ESMTP id n2KJON1H028774 for ; Sat, 21 Mar 2009 03:24:23 +0800 (CST) Date: Sat, 21 Mar 2009 03:24:20 +0800 From: Zhang Le To: linux-mips@linux-mips.org Subject: Re: [PATCH] MIPS: rename CPU_LOONGSON2 to CPU_LOONGSON2E Message-ID: <20090320192419.GA14445@adriano.hkcable.com.hk> Mail-Followup-To: linux-mips@linux-mips.org References: <1237576220-4479-1-git-send-email-r0bertz@gentoo.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1237576220-4479-1-git-send-email-r0bertz@gentoo.org> User-Agent: Mutt/1.5.19 (2009-01-05) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22102 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: r0bertz@gentoo.org Precedence: bulk X-list: linux-mips Content-Length: 1706 Lines: 46 On 03:10 Sat 21 Mar , Zhang Le wrote: > This is for future inclusion of Loongson 2F patches. Because Gcc 4.4 (not > released yet) has different -march argument for these two CPUs, we should > be able to distinguish them. Sorry, please hold on. It seems I missed something. I will send another soon. > > Signed-off-by: Zhang Le > --- > arch/mips/Kconfig | 4 ++-- > arch/mips/Makefile | 2 +- > 2 files changed, 3 insertions(+), 3 deletions(-) > > diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig > index 206cb79..dcb675d 100644 > --- a/arch/mips/Kconfig > +++ b/arch/mips/Kconfig > @@ -1014,8 +1014,8 @@ choice > prompt "CPU type" > default CPU_R4X00 > > -config CPU_LOONGSON2 > - bool "Loongson 2" > +config CPU_LOONGSON2E > + bool "Loongson 2E" > depends on SYS_HAS_CPU_LOONGSON2 > select CPU_SUPPORTS_32BIT_KERNEL > select CPU_SUPPORTS_64BIT_KERNEL > diff --git a/arch/mips/Makefile b/arch/mips/Makefile > index 22dab2e..097a7fa 100644 > --- a/arch/mips/Makefile > +++ b/arch/mips/Makefile > @@ -119,7 +119,7 @@ cflags-$(CONFIG_CPU_R4300) += -march=r4300 -Wa,--trap > cflags-$(CONFIG_CPU_VR41XX) += -march=r4100 -Wa,--trap > cflags-$(CONFIG_CPU_R4X00) += -march=r4600 -Wa,--trap > cflags-$(CONFIG_CPU_TX49XX) += -march=r4600 -Wa,--trap > -cflags-$(CONFIG_CPU_LOONGSON2) += -march=r4600 -Wa,--trap > +cflags-$(CONFIG_CPU_LOONGSON2E) += -march=r4600 -Wa,--trap > cflags-$(CONFIG_CPU_MIPS32_R1) += $(call cc-option,-march=mips32,-mips32 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS32) \ > -Wa,-mips32 -Wa,--trap > cflags-$(CONFIG_CPU_MIPS32_R2) += $(call cc-option,-march=mips32r2,-mips32r2 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS32) \ > -- > 1.6.2 > From robert.zhangle@gmail.com Fri Mar 20 19:30:07 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 20 Mar 2009 19:30:14 +0000 (GMT) Received: from sitar.i-cable.com ([203.83.115.100]:40184 "HELO sitar.i-cable.com") by ftp.linux-mips.org with SMTP id S21369896AbZCTTaH (ORCPT ); Fri, 20 Mar 2009 19:30:07 +0000 Received: (qmail 24083 invoked by uid 508); 20 Mar 2009 19:29:59 -0000 Received: from 203.83.114.122 by sitar (envelope-from , uid 505) with qmail-scanner-1.25 (clamdscan: 0.93.3/8786. Clear:RC:1(203.83.114.122):. Processed in 0.096849 secs); 20 Mar 2009 19:29:59 -0000 Received: from ip114122.hkicable.com (HELO xenon.i-cable.com) (203.83.114.122) by 0 with SMTP; 20 Mar 2009 19:29:59 -0000 Received: from localhost (cm222-167-208-75.hkcable.com.hk [222.167.208.75]) by xenon.i-cable.com (8.13.5/8.13.5) with ESMTP id n2KJTwn1029021 for ; Sat, 21 Mar 2009 03:29:59 +0800 (CST) Date: Sat, 21 Mar 2009 03:29:55 +0800 From: Zhang Le To: linux-mips@linux-mips.org Subject: Re: [PATCH] MIPS: rename CPU_LOONGSON2 to CPU_LOONGSON2E Message-ID: <20090320192954.GB14445@adriano.hkcable.com.hk> Mail-Followup-To: linux-mips@linux-mips.org References: <1237576220-4479-1-git-send-email-r0bertz@gentoo.org> <20090320192419.GA14445@adriano.hkcable.com.hk> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20090320192419.GA14445@adriano.hkcable.com.hk> User-Agent: Mutt/1.5.19 (2009-01-05) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22103 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: r0bertz@gentoo.org Precedence: bulk X-list: linux-mips Content-Length: 1953 Lines: 53 On 03:24 Sat 21 Mar , Zhang Le wrote: > On 03:10 Sat 21 Mar , Zhang Le wrote: > > This is for future inclusion of Loongson 2F patches. Because Gcc 4.4 (not > > released yet) has different -march argument for these two CPUs, we should > > be able to distinguish them. > > Sorry, please hold on. It seems I missed something. > I will send another soon. Oops, this requires much more changes than I originally thought. I will see what I can come up with. Sorry. > > > > > Signed-off-by: Zhang Le > > --- > > arch/mips/Kconfig | 4 ++-- > > arch/mips/Makefile | 2 +- > > 2 files changed, 3 insertions(+), 3 deletions(-) > > > > diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig > > index 206cb79..dcb675d 100644 > > --- a/arch/mips/Kconfig > > +++ b/arch/mips/Kconfig > > @@ -1014,8 +1014,8 @@ choice > > prompt "CPU type" > > default CPU_R4X00 > > > > -config CPU_LOONGSON2 > > - bool "Loongson 2" > > +config CPU_LOONGSON2E > > + bool "Loongson 2E" > > depends on SYS_HAS_CPU_LOONGSON2 > > select CPU_SUPPORTS_32BIT_KERNEL > > select CPU_SUPPORTS_64BIT_KERNEL > > diff --git a/arch/mips/Makefile b/arch/mips/Makefile > > index 22dab2e..097a7fa 100644 > > --- a/arch/mips/Makefile > > +++ b/arch/mips/Makefile > > @@ -119,7 +119,7 @@ cflags-$(CONFIG_CPU_R4300) += -march=r4300 -Wa,--trap > > cflags-$(CONFIG_CPU_VR41XX) += -march=r4100 -Wa,--trap > > cflags-$(CONFIG_CPU_R4X00) += -march=r4600 -Wa,--trap > > cflags-$(CONFIG_CPU_TX49XX) += -march=r4600 -Wa,--trap > > -cflags-$(CONFIG_CPU_LOONGSON2) += -march=r4600 -Wa,--trap > > +cflags-$(CONFIG_CPU_LOONGSON2E) += -march=r4600 -Wa,--trap > > cflags-$(CONFIG_CPU_MIPS32_R1) += $(call cc-option,-march=mips32,-mips32 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS32) \ > > -Wa,-mips32 -Wa,--trap > > cflags-$(CONFIG_CPU_MIPS32_R2) += $(call cc-option,-march=mips32r2,-mips32r2 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS32) \ > > -- > > 1.6.2 > > > From khickey@rmicorp.com Fri Mar 20 20:51:56 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 20 Mar 2009 20:52:03 +0000 (GMT) Received: from mx1.rmicorp.com ([63.111.213.197]:60824 "EHLO mx1.rmicorp.com") by ftp.linux-mips.org with ESMTP id S21368294AbZCTUv4 (ORCPT ); Fri, 20 Mar 2009 20:51:56 +0000 Received: from sark.razamicroelectronics.com ([10.8.0.254]) by mx1.rmicorp.com with Microsoft SMTPSVC(6.0.3790.3959); Fri, 20 Mar 2009 13:51:46 -0700 Received: from localhost.localdomain (unknown [10.8.0.60]) by sark.razamicroelectronics.com (Postfix) with ESMTP id 28AC6EE76A6; Fri, 20 Mar 2009 14:11:47 -0600 (CST) From: Kevin Hickey To: ralf@linux-mips.org, linux-mips@linux-mips.org Subject: [PATCH v2 0/6] Alchemy: Basic Au1300 and DBAu1300 support Date: Fri, 20 Mar 2009 15:51:40 -0500 Message-Id: <1237582306-10800-1-git-send-email-khickey@rmicorp.com> X-Mailer: git-send-email 1.5.4.3 In-Reply-To: <> References: <> X-OriginalArrivalTime: 20 Mar 2009 20:51:47.0696 (UTC) FILETIME=[AF8CA700:01C9A99D] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22104 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: khickey@rmicorp.com Precedence: bulk X-list: linux-mips Content-Length: 2476 Lines: 42 This patch series introduces support for the RMI Alchemy Au1300 series of SOCs and the DBAu1300 (or DB1300) development board. With this set the basic CPU and board are supported. I have code for several of the peripherals, including USB, MMC, IDE, and Ethernet and will submit those patches after these have been accepted. Though some of the new code added here could be useful for other boards (the DB1200 in particular), I did my best to limit this patch set to additions only. It should not disturb any other boards. To verify this I built and tested the updated directory for an on a DB1200 board. A future patch set may include some integration of this new code into the DB1200 configuration. =Kevin arch/mips/Kconfig | 1 + arch/mips/Makefile | 6 + arch/mips/alchemy/Kconfig | 22 ++ arch/mips/alchemy/common/Makefile | 6 +- arch/mips/alchemy/common/au13xx_res.c | 74 ++++++ arch/mips/alchemy/common/dbdma.c | 46 ++++- arch/mips/alchemy/common/gpio_int.c | 265 ++++++++++++++++++++++ arch/mips/alchemy/common/platform.c | 70 ++++++ arch/mips/alchemy/common/time.c | 5 + arch/mips/alchemy/devboards/Makefile | 6 + arch/mips/alchemy/devboards/cascade_irq.c | 142 ++++++++++++ arch/mips/alchemy/devboards/db1300/Makefile | 6 + arch/mips/alchemy/devboards/db1300/board_setup.c | 124 ++++++++++ arch/mips/alchemy/devboards/leds.c | 58 +++++ arch/mips/include/asm/cpu.h | 10 +- arch/mips/include/asm/mach-au1x00/au1000.h | 50 ++++ arch/mips/include/asm/mach-au1x00/au13xx.h | 201 ++++++++++++++++ arch/mips/include/asm/mach-au1x00/au1xxx.h | 3 + arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h | 33 +++ arch/mips/include/asm/mach-au1x00/dev_boards.h | 44 ++++ arch/mips/include/asm/mach-au1x00/gpio_int.h | 237 +++++++++++++++++++ arch/mips/include/asm/mach-au1x00/irq.h | 34 +++ arch/mips/include/asm/mips-boards/db1300.h | 121 ++++++++++ arch/mips/kernel/cpu-probe.c | 20 ++ arch/mips/mm/c-r4k.c | 1 + arch/mips/mm/tlbex.c | 1 + drivers/video/Kconfig | 2 +- 27 files changed, 1582 insertions(+), 6 deletions(-) From khickey@rmicorp.com Fri Mar 20 20:52:21 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 20 Mar 2009 20:52:28 +0000 (GMT) Received: from mx1.rmicorp.com ([63.111.213.197]:60824 "EHLO mx1.rmicorp.com") by ftp.linux-mips.org with ESMTP id S21369890AbZCTUv5 (ORCPT ); Fri, 20 Mar 2009 20:51:57 +0000 Received: from sark.razamicroelectronics.com ([10.8.0.254]) by mx1.rmicorp.com with Microsoft SMTPSVC(6.0.3790.3959); Fri, 20 Mar 2009 13:51:47 -0700 Received: from localhost.localdomain (unknown [10.8.0.60]) by sark.razamicroelectronics.com (Postfix) with ESMTP id 3B540EE76DA; Fri, 20 Mar 2009 14:11:47 -0600 (CST) From: Kevin Hickey To: ralf@linux-mips.org, linux-mips@linux-mips.org Cc: Kevin Hickey Subject: [PATCH v2 3/6] Alchemy: Au1300/DB1300 UART support Date: Fri, 20 Mar 2009 15:51:43 -0500 Message-Id: <1237582306-10800-4-git-send-email-khickey@rmicorp.com> X-Mailer: git-send-email 1.5.4.3 In-Reply-To: <1237582306-10800-3-git-send-email-khickey@rmicorp.com> References: <> <1237582306-10800-1-git-send-email-khickey@rmicorp.com> <1237582306-10800-2-git-send-email-khickey@rmicorp.com> <1237582306-10800-3-git-send-email-khickey@rmicorp.com> X-OriginalArrivalTime: 20 Mar 2009 20:51:48.0493 (UTC) FILETIME=[B00643D0:01C9A99D] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22105 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: khickey@rmicorp.com Precedence: bulk X-list: linux-mips Content-Length: 1942 Lines: 58 Adds support for the UART on the Au1300 SOC and the DB1300 board. This includes enabling EARLY_PRINTK for Alchemy. Signed-off-by: Kevin Hickey --- arch/mips/Kconfig | 1 + arch/mips/alchemy/common/platform.c | 5 +++++ arch/mips/include/asm/mach-au1x00/au1000.h | 5 +++++ 3 files changed, 11 insertions(+), 0 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index e61465a..b030770 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -21,6 +21,7 @@ choice config MACH_ALCHEMY bool "Alchemy processor based machines" + select SYS_HAS_EARLY_PRINTK config BASLER_EXCITE bool "Basler eXcite smart camera" diff --git a/arch/mips/alchemy/common/platform.c b/arch/mips/alchemy/common/platform.c index 5c76c64..78fd862 100644 --- a/arch/mips/alchemy/common/platform.c +++ b/arch/mips/alchemy/common/platform.c @@ -52,6 +52,11 @@ static struct plat_serial8250_port au1x00_uart_data[] = { #elif defined(CONFIG_SOC_AU1200) PORT(UART0_ADDR, AU1200_UART0_INT), PORT(UART1_ADDR, AU1200_UART1_INT), +#elif defined(CONFIG_SOC_AU13XX) + PORT(UART2_ADDR, AU1300_IRQ_UART2 + GPINT_LINUX_IRQ_OFFSET), + PORT(UART0_ADDR, AU1300_IRQ_UART0 + GPINT_LINUX_IRQ_OFFSET), + PORT(UART1_ADDR, AU1300_IRQ_UART1 + GPINT_LINUX_IRQ_OFFSET), + PORT(UART3_ADDR, AU1300_IRQ_UART3 + GPINT_LINUX_IRQ_OFFSET), #endif #endif /* CONFIG_SERIAL_8250_AU1X00 */ { }, diff --git a/arch/mips/include/asm/mach-au1x00/au1000.h b/arch/mips/include/asm/mach-au1x00/au1000.h index c7fe356..f669556 100644 --- a/arch/mips/include/asm/mach-au1x00/au1000.h +++ b/arch/mips/include/asm/mach-au1x00/au1000.h @@ -1277,7 +1277,12 @@ enum soc_au1200_ints { #define MAC_RX_BUFF3_ADDR 0x34 /* UARTS 0-3 */ +#ifdef CONFIG_SOC_AU13XX +#define UART_BASE UART2_ADDR +#else #define UART_BASE UART0_ADDR +#endif + #ifdef CONFIG_SOC_AU1200 #define UART_DEBUG_BASE UART1_ADDR #else -- 1.5.4.3 From khickey@rmicorp.com Fri Mar 20 20:52:46 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 20 Mar 2009 20:52:54 +0000 (GMT) Received: from mx1.rmicorp.com ([63.111.213.197]:60824 "EHLO mx1.rmicorp.com") by ftp.linux-mips.org with ESMTP id S21369934AbZCTUv7 (ORCPT ); Fri, 20 Mar 2009 20:51:59 +0000 Received: from sark.razamicroelectronics.com ([10.8.0.254]) by mx1.rmicorp.com with Microsoft SMTPSVC(6.0.3790.3959); Fri, 20 Mar 2009 13:51:46 -0700 Received: from localhost.localdomain (unknown [10.8.0.60]) by sark.razamicroelectronics.com (Postfix) with ESMTP id 383F0EE76D9; Fri, 20 Mar 2009 14:11:47 -0600 (CST) From: Kevin Hickey To: ralf@linux-mips.org, linux-mips@linux-mips.org Cc: Kevin Hickey Subject: [PATCH v2 2/6] Alchemy: Au1300 new interrupt controller Date: Fri, 20 Mar 2009 15:51:42 -0500 Message-Id: <1237582306-10800-3-git-send-email-khickey@rmicorp.com> X-Mailer: git-send-email 1.5.4.3 In-Reply-To: <1237582306-10800-2-git-send-email-khickey@rmicorp.com> References: <> <1237582306-10800-1-git-send-email-khickey@rmicorp.com> <1237582306-10800-2-git-send-email-khickey@rmicorp.com> X-OriginalArrivalTime: 20 Mar 2009 20:51:47.0711 (UTC) FILETIME=[AF8EF0F0:01C9A99D] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22106 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: khickey@rmicorp.com Precedence: bulk X-list: linux-mips Content-Length: 28550 Lines: 875 The Au1300 has a new interrupt controller (relative to the rest of the Alchemy line). The differences were great enough to justify adding a whole new module. Included in this patch is the new interrupt controller, a new implementation of the cascade interrupt controller on the DB1300 board and some code to drive LEDs on the DB1300 that is used by the interrupt controller. Since the cascade interrupt controller is virtually indentical (with the exception of some constants) between the DB1300 and DB1200, a future optimization may be to use the same code for both boards. Signed-off-by: Kevin Hickey --- arch/mips/alchemy/Kconfig | 16 ++ arch/mips/alchemy/common/Makefile | 5 +- arch/mips/alchemy/common/gpio_int.c | 265 ++++++++++++++++++++++++++ arch/mips/alchemy/devboards/Makefile | 5 + arch/mips/alchemy/devboards/cascade_irq.c | 142 ++++++++++++++ arch/mips/alchemy/devboards/leds.c | 58 ++++++ arch/mips/include/asm/mach-au1x00/gpio_int.h | 237 +++++++++++++++++++++++ arch/mips/include/asm/mach-au1x00/irq.h | 34 ++++ 8 files changed, 761 insertions(+), 1 deletions(-) create mode 100644 arch/mips/alchemy/common/gpio_int.c create mode 100644 arch/mips/alchemy/devboards/cascade_irq.c create mode 100644 arch/mips/alchemy/devboards/leds.c create mode 100644 arch/mips/include/asm/mach-au1x00/gpio_int.h create mode 100644 arch/mips/include/asm/mach-au1x00/irq.h diff --git a/arch/mips/alchemy/Kconfig b/arch/mips/alchemy/Kconfig index 50d426d..2e189c2 100644 --- a/arch/mips/alchemy/Kconfig +++ b/arch/mips/alchemy/Kconfig @@ -114,22 +114,32 @@ endchoice config SOC_AU1000 bool select SOC_AU1X00 + select AU_INT_CNTLR config SOC_AU1100 bool select SOC_AU1X00 + select AU_INT_CNTLR config SOC_AU1500 bool select SOC_AU1X00 + select AU_INT_CNTLR config SOC_AU1550 bool select SOC_AU1X00 + select AU_INT_CNTLR config SOC_AU1200 bool select SOC_AU1X00 + select AU_INT_CNTLR + +config SOC_AU13XX + bool + select SOC_AU1X00 + select AU_GPIO_INT_CNTLR config SOC_AU1X00 bool @@ -141,3 +151,9 @@ config SOC_AU1X00 select SYS_SUPPORTS_32BIT_KERNEL select SYS_SUPPORTS_APM_EMULATION select GENERIC_HARDIRQS_NO__DO_IRQ + +config AU_INT_CNTLR + bool + +config AU_GPIO_INT_CNTLR + bool diff --git a/arch/mips/alchemy/common/Makefile b/arch/mips/alchemy/common/Makefile index d50d476..faa6afd 100644 --- a/arch/mips/alchemy/common/Makefile +++ b/arch/mips/alchemy/common/Makefile @@ -5,10 +5,13 @@ # Makefile for the Alchemy Au1xx0 CPUs, generic files. # -obj-y += prom.o irq.o puts.o time.o reset.o \ +obj-y += prom.o puts.o time.o reset.o \ clocks.o platform.o power.o setup.o \ sleeper.o dma.o dbdma.o gpio.o obj-$(CONFIG_PCI) += pci.o +obj-$(CONFIG_AU_GPIO_INT_CNTLR) += gpio_int.o +obj-$(CONFIG_AU_INT_CNTLR) += irq.o + EXTRA_CFLAGS += -Werror diff --git a/arch/mips/alchemy/common/gpio_int.c b/arch/mips/alchemy/common/gpio_int.c new file mode 100644 index 0000000..e6ae8a7 --- /dev/null +++ b/arch/mips/alchemy/common/gpio_int.c @@ -0,0 +1,265 @@ +/* + * Copyright 2008 RMI Corporation + * Author: Kevin Hickey + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#include +#include +#include /* For functions called by do_IRQ */ +#include + +#include +#include + +struct gpio_int_regs *const gpio_int = + (struct gpio_int_regs *)(GPIO_INT_CTRLR_BASE + KSEG1); + +static struct gpio_int_cfg __initdata basic_irqs[]; + +void (*board_irq_dispatch)(int) = NULL; + +#ifdef CONFIG_SOC_AU13XX +static struct gpio_int_cfg __initdata basic_irqs[] = { + { AU1300_IRQ_DDMA, 1, LEVEL_HIGH, HW_INT_1, DEV_CTRL }, + + { AU1300_IRQ_RTC_TICK, 1, RISING, HW_INT_1, DEV_CTRL }, + { AU1300_IRQ_TOY_TICK, 1, RISING, HW_INT_1, DEV_CTRL }, + + { AU1300_IRQ_LCD, 1, LEVEL_HIGH, HW_INT_1, DEV_CTRL }, + + { AU1300_IRQ_UART1, 1, LEVEL_HIGH, HW_INT_1, DEV_CTRL }, + { AU1300_IRQ_UART1, 1, LEVEL_HIGH, HW_INT_1, DEV_CTRL }, + { AU1300_IRQ_UART2, 1, LEVEL_HIGH, HW_INT_1, DEV_CTRL }, + { AU1300_IRQ_UART3, 1, LEVEL_HIGH, HW_INT_1, DEV_CTRL }, + + { AU1300_IRQ_SD1, 1, LEVEL_HIGH, HW_INT_1, DEV_CTRL }, + { AU1300_IRQ_SD2, 1, LEVEL_HIGH, HW_INT_1, DEV_CTRL }, + + { AU1300_IRQ_USB, 1, LEVEL_HIGH, HW_INT_1, DEV_CTRL }, + + { AU1300_IRQ_BSA, 1, LEVEL_HIGH, HW_INT_1, DEV_CTRL }, + { AU1300_IRQ_MPE, 1, RISING, HW_INT_1, DEV_CTRL }, + { AU1300_IRQ_ITE, 1, LEVEL_HIGH, HW_INT_1, DEV_CTRL }, + + { AU1300_IRQ_RTCMATCH_1, 1, RISING, HW_INT_1, DEV_CTRL }, + { AU1300_IRQ_RTCMATCH_1, 1, RISING, HW_INT_1, DEV_CTRL }, + { AU1300_IRQ_RTCMATCH_2, 0, RISING, HW_INT_0, DEV_CTRL }, + + { AU1300_IRQ_TOYMATCH_1, 1, RISING, HW_INT_1, DEV_CTRL }, + { AU1300_IRQ_TOYMATCH_1, 1, RISING, HW_INT_1, DEV_CTRL }, + { AU1300_IRQ_TOYMATCH_2, 1, RISING, HW_INT_1, DEV_CTRL }, + + + /* KH: TODO - Move this to the board file. */ + { 5, 0, LEVEL_HIGH, HW_INT_0, GPIO_IN }, +}; + +/* + * KH: TODO - Consider moving to board specific location... + */ +static struct gpio_int_cfg __initdata basic_gpios[] = { + { 32, 0, DISABLED, HW_INT_0, DEV_CTRL }, + { 33, 0, DISABLED, HW_INT_0, DEV_CTRL }, + { 34, 0, DISABLED, HW_INT_0, DEV_CTRL }, + { 35, 0, DISABLED, HW_INT_0, DEV_CTRL }, + { 36, 0, DISABLED, HW_INT_0, DEV_CTRL }, + { 37, 0, DISABLED, HW_INT_0, DEV_CTRL }, +}; +#endif + +int __initdata nr_basic_irqs = ARRAY_SIZE(basic_irqs); + +/* + **************************************************************************** + * Functions and delcaration for irq_chip + **************************************************************************** + */ +void gpio_int_ack(unsigned int irq) +{ + u32 intr = irq - GPINT_LINUX_IRQ_OFFSET; + u32 bank = GPINT_BANK_FROM_INT(intr); + u32 bit = GPINT_BIT_FROM_INT(bank, intr); + + au_iowrite32(bit, &gpio_int->int_pend[bank]); +} + +void gpio_int_mask(unsigned int irq) +{ + u32 intr = irq - GPINT_LINUX_IRQ_OFFSET; + u32 bank = GPINT_BANK_FROM_INT(intr); + u32 bit = GPINT_BIT_FROM_INT(bank, intr); + + au_iowrite32(bit, &gpio_int->int_maskclr[bank]); +} + +void gpio_int_unmask(unsigned int irq) +{ + u32 intr = irq - GPINT_LINUX_IRQ_OFFSET; + u32 bank = GPINT_BANK_FROM_INT(intr); + u32 bit = GPINT_BIT_FROM_INT(bank, intr); + + au_iowrite32(bit, &gpio_int->int_mask[bank]); +} + +void gpio_int_mask_ack(unsigned int irq) +{ + u32 intr = irq - GPINT_LINUX_IRQ_OFFSET; + u32 bank = GPINT_BANK_FROM_INT(intr); + u32 bit = GPINT_BIT_FROM_INT(bank, intr); + + au_iowrite32(bit, &gpio_int->int_maskclr[bank]); + au_iowrite32(bit, &gpio_int->int_pend[bank]); +} + +static struct irq_chip gpio_int_irq_type = { + .name = "Au GPIO/INT", + .ack = gpio_int_ack, + .mask = gpio_int_mask, + .unmask = gpio_int_unmask, + .mask_ack = gpio_int_mask_ack +}; +/*****************************************************************************/ + +void set_pin_cfg(const struct gpio_int_cfg *cfg) +{ + u32 tmp; + tmp = GPINT_PINCTL_N(cfg->pinctl); + tmp |= GPINT_INTLINE_N(cfg->intline); + tmp |= GPINT_INTCFG_N(cfg->intcfg); + tmp |= cfg->intwake ? GPINT_INTWAKE_ENABLE : 0; + au_iowrite32(tmp, &gpio_int->gp_int[cfg->number]); +} + +void set_gpio(u8 gpio, u8 value) +{ + u32 bank = GPINT_BANK_FROM_GPIO(gpio); + u32 bit = GPINT_BIT_FROM_GPIO(bank, gpio); + + if (value == 0) + au_iowrite32(1 << bit, &gpio_int->pin_valclr[bank]); + else + au_iowrite32(1 << bit, &gpio_int->pin_val[bank]); +} + +u8 get_gpio(u8 gpio) +{ + u32 bank = GPINT_BANK_FROM_GPIO(gpio); + u32 bit = GPINT_BIT_FROM_GPIO(bank, gpio); + u32 tmp; + + tmp = au_ioread32(&gpio_int->pin_val[bank]); + return tmp >> bit; +} + + +void __init arch_init_irq(void) +{ + int i; + + /* + * Initialize the basic MIPS interrupt components. + */ + mips_cpu_irq_init(); + + for (i = 0; i < GPINT_NUM_BANKS; ++i) + gpio_int->int_maskclr[i] = ~0UL; + + + for (i = 0; i < ARRAY_SIZE(basic_gpios); ++i) + set_pin_cfg(&basic_gpios[i]); + + for (i = 0; i < nr_basic_irqs; ++i) { + printk(KERN_DEBUG "Initializing IRQ %d\n", + basic_irqs[i].number); + set_pin_cfg(&basic_irqs[i]); + if (basic_irqs[i].intcfg == LEVEL_LOW) + set_irq_chip_and_handler_name( + basic_irqs[i].number + GPINT_LINUX_IRQ_OFFSET, + &gpio_int_irq_type, + handle_level_irq, + "lowlevel"); + else if (basic_irqs[i].intcfg == LEVEL_HIGH) + set_irq_chip_and_handler_name( + basic_irqs[i].number + GPINT_LINUX_IRQ_OFFSET, + &gpio_int_irq_type, + handle_level_irq, + "highlevel"); + else if (basic_irqs[i].intcfg == FALLING) + set_irq_chip_and_handler_name( + basic_irqs[i].number + GPINT_LINUX_IRQ_OFFSET, + &gpio_int_irq_type, + handle_edge_irq, + "fallingedge"); + else if (basic_irqs[i].intcfg == RISING) + set_irq_chip_and_handler_name( + basic_irqs[i].number + GPINT_LINUX_IRQ_OFFSET, + &gpio_int_irq_type, + handle_edge_irq, + "risingedge"); + else if (basic_irqs[i].intcfg == ANY_CHANGE) + set_irq_chip_and_handler_name( + basic_irqs[i].number + GPINT_LINUX_IRQ_OFFSET, + &gpio_int_irq_type, + handle_edge_irq, + "bothedge"); + else + set_irq_chip( + basic_irqs[i].number + GPINT_LINUX_IRQ_OFFSET, + &gpio_int_irq_type); + } + + set_c0_status(IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4); + + board_init_irq(); +} + +asmlinkage void plat_irq_dispatch(void) +{ + unsigned int intr; + u32 bank; + u32 reg_msk; + unsigned int pending = read_c0_status() & read_c0_cause(); + /* + * C0 timer tick + */ + if (pending & CAUSEF_IP7) + do_IRQ(MIPS_CPU_IRQ_BASE + 7); + else if (pending & (CAUSEF_IP2 | CAUSEF_IP3)) { + intr = au_ioread32(&gpio_int->pri_enc); + bank = GPINT_BANK_FROM_INT(intr); + reg_msk = GPINT_BIT_FROM_INT(bank, intr); + + if (intr != 127) { + if (board_irq_dispatch) + board_irq_dispatch(intr); + + do_IRQ(GPINT_LINUX_IRQ_OFFSET + intr); + } + } else { + printk(KERN_WARNING + "ALCHEMY GPIO_INT: Unexpected cause was set. %08x\n", + pending); + spurious_interrupt(); + } + +} + diff --git a/arch/mips/alchemy/devboards/Makefile b/arch/mips/alchemy/devboards/Makefile index 0d2d224..8cce4d0 100644 --- a/arch/mips/alchemy/devboards/Makefile +++ b/arch/mips/alchemy/devboards/Makefile @@ -17,3 +17,8 @@ obj-$(CONFIG_MIPS_DB1500) += db1x00/ obj-$(CONFIG_MIPS_DB1550) += db1x00/ obj-$(CONFIG_MIPS_BOSPORUS) += db1x00/ obj-$(CONFIG_MIPS_MIRAGE) += db1x00/ + +# These two files are used only by DB1300 today but will be used by DB1200 and +# possibly others in the future. +obj-$(CONFIG_MIPS_DB1300) += cascade_irq.o +obj-$(CONFIG_MIPS_DB1300) += leds.o diff --git a/arch/mips/alchemy/devboards/cascade_irq.c b/arch/mips/alchemy/devboards/cascade_irq.c new file mode 100644 index 0000000..6d0a965 --- /dev/null +++ b/arch/mips/alchemy/devboards/cascade_irq.c @@ -0,0 +1,142 @@ +/* + * Copyright 2003-2008 RMI Corporation. All rights reserved. + * Author: Kevin Hickey + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED BY RMI Corporation 'AS IS' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL RMI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include +#include +#include +#include +#include + +#include + +/* + * The following must be declared/defined in an included file: + * - volatile struct bcsr_regs (declared) + * (which much include fields int_status, intset_mask, intclr_mask, intset, + * and intclr) + * - volatile struct bcsr_regs *const bcsr (defined) + * - CASCADE_IRQ_MIN + * - CASCADE_IRQ_MAX + * - CASCADE_IRQ_TYPE_STRING + * - CASCADE_IRQ (System IRQ to which the cascade is connected) + */ + +void __init board_init_irq(void); + +irqreturn_t cascade_handler(int irq, void *dev_id) +{ + u16 int_status = au_ioread16(&db_bcsr->int_status); + int irq_in_service; + + au_iowrite16(int_status, &db_bcsr->int_status); + for ( ; int_status; int_status &= int_status - 1) { + irq_in_service = CASCADE_IRQ_MIN + __ffs(int_status); + db_set_hex((u8)(irq_in_service)); + do_IRQ(irq_in_service); + } + + return IRQ_RETVAL(1); +} + +DEFINE_MUTEX(cascade_use_count_mutex); +static int cascade_use_count; + +static void cascade_mask(unsigned int irq) +{ + au_iowrite16(1 << (irq - CASCADE_IRQ_MIN), &db_bcsr->intclr_mask); +} + +static void cascade_unmask(unsigned int irq) +{ + au_iowrite16(1 << (irq - CASCADE_IRQ_MIN), &db_bcsr->intset_mask); +} + +static void cascade_enable(unsigned int irq) +{ + au_iowrite16(1 << (irq - CASCADE_IRQ_MIN), &db_bcsr->intset); + cascade_unmask(irq); +} + +static void cascade_disable(unsigned int irq) +{ + au_iowrite16(1 << (irq - CASCADE_IRQ_MIN), &db_bcsr->intclr); + cascade_mask(irq); +} + + +static unsigned int cascade_startup(unsigned int irq) +{ + int retval = 0; + + mutex_lock(&cascade_use_count_mutex); + ++cascade_use_count; + if (cascade_use_count == 1) + retval = request_irq(CASCADE_IRQ, + &cascade_handler, 0, "Cascade", + &cascade_handler); + mutex_unlock(&cascade_use_count_mutex); + + cascade_enable(irq); + cascade_unmask(irq); + + return retval; +} + +static void cascade_shutdown(unsigned int irq) +{ + cascade_mask(irq); + cascade_disable(irq); + + mutex_lock(&cascade_use_count_mutex); + --cascade_use_count; + if (cascade_use_count == 0) + free_irq(CASCADE_IRQ, &cascade_handler); + mutex_unlock(&cascade_use_count_mutex); +} + +static struct irq_chip cascade_irq_type = { + .name = CASCADE_IRQ_TYPE_STRING, + .startup = cascade_startup, + .shutdown = cascade_shutdown, + .mask = cascade_mask, + .enable = cascade_enable, + .disable = cascade_disable, + .unmask = cascade_unmask, + .mask_ack = cascade_mask +}; + +void __init board_init_irq(void) +{ + int irq; + + for (irq = CASCADE_IRQ_MIN; + irq < CASCADE_IRQ_MAX; ++irq) { + printk(KERN_DEBUG "Initializing IRQ %d\n", irq); + set_irq_chip_and_handler(irq, &cascade_irq_type, + handle_level_irq); + cascade_disable(irq); + } +} diff --git a/arch/mips/alchemy/devboards/leds.c b/arch/mips/alchemy/devboards/leds.c new file mode 100644 index 0000000..75be345 --- /dev/null +++ b/arch/mips/alchemy/devboards/leds.c @@ -0,0 +1,58 @@ +/* + * Copyright 2003-2008 RMI Corporation. All rights reserved. + * Author: Kevin Hickey + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED BY RMI Corporation 'AS IS' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL RMI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include + +/* + * Requires the following to be defined in the board-specifc .h file: + * - HEX_REGS_KSEG1_ADDR + * - struct hex_regs with members: + * - hex (set the hex value) + * - BCSR_REGS_KSEG1_ADDR + * - struct bcsr_regs + */ + +static hex_regs *const hex = (hex_regs *)(HEX_REGS_KSEG1_ADDR); + +/* + * Takes a u8 because though the register is 16 bits, only 8 appear + */ +void db_set_hex(u8 val) +{ + au_iowrite16((u16)val, &hex->hex); +} + +/* + * 2 dots use the least significant 2 bits + * Setting a bit lights the LED (opposite of the register) + */ +void db_set_hex_dots(u8 val) +{ + u16 leds = au_ioread16(&db_bcsr->disk_leds); + leds |= 0x3; + leds &= (~(val & 0x3)); + au_iowrite16(leds, &db_bcsr->disk_leds); +} diff --git a/arch/mips/include/asm/mach-au1x00/gpio_int.h b/arch/mips/include/asm/mach-au1x00/gpio_int.h new file mode 100644 index 0000000..f1b11fa --- /dev/null +++ b/arch/mips/include/asm/mach-au1x00/gpio_int.h @@ -0,0 +1,237 @@ +/* + * Copyright 2008 RMI Corporation + * Author: Kevin Hickey + * + * Defines and macros for the GPIO and Interrupt controller for Alchemy, + * introduced in the Au13xx series. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#ifndef _GPIO_INT_H +#define _GPIO_INT_H + +#include + +/* + * There are a total 128 'channels' defined by the Au13xx databook. However, + * this requires 4 sperate 32bit registers for programming. Each register is + * called a 'bank' for ease of use. + */ +#define GPINT_BANK0 0 +#define GPINT_BANK1 1 +#define GPINT_BANK2 2 +#define GPINT_BANK3 3 + +#define GPINT_NUM_BANKS 4 /* 0-3 */ +#define GPINT_MAX_BANK (GPINT_BANK3) + +#define GPINT_GPIO_PER_BANK 32 +#define GPINT_INTS_PER_BANK GPINT_GPIO_PER_BANK + +/* Total number of interrupts our architecture allows */ +#define GPINT_MAX_INTS (GPINT_NUM_BANKS*GPINT_INTS_PER_BANK) + +/* Current maximum supported GPIO/INTERRUPTs */ +#define GPINT_NUM_GPIO GPINT_MAX_INTS +#define GPINT_NUM_INTERRUPTS GPINT_MAX_INTS + +/* Starting GPIO/INTERRUPT for each bank */ +#define GPINT_BANK0_START 0 +#define GPINT_BANK1_START 32 +#define GPINT_BANK2_START 64 +#define GPINT_BANK3_START 96 + +/* divide by 32 to get bank */ +#define GPINT_BANK_FROM_GPIO(n) (n>>5) +#define GPINT_BANK_FROM_INT(n) GPINT_BANK_FROM_GPIO(n) +/* multiply by 32 to get base */ +#define GPINT_BIT_FROM_GPIO(b, n) (1<<(n-(b<<5))) +#define GPINT_BIT_FROM_INT(b, n) GPINT_BIT_FROM_GPIO(b, n) + +struct gpio_int_regs { + /* R/W1S */ + /* u32 pin_val0; 0x00 */ + /* u32 pin_val1; 0x04 */ + /* u32 pin_val2; 0x08 */ + /* u32 pin_val3; 0x0C */ + u32 pin_val[GPINT_NUM_BANKS]; + + /* W1C */ + /* u32 pin_valclr0 0x10 */ + /* u32 pin_valclr1; 0x14 */ + /* u32 pin_valclr2; 0x18 */ + /* u32 pin_valclr3; 0x1C */ + u32 pin_valclr[GPINT_NUM_BANKS]; + + /* R/W1C */ + /* u32 int_pend0; 0x20 */ + /* u32 int_pend1; 0x24 */ + /* u32 int_pend2; 0x28 */ + /* u32 int_pend3; 0x2c */ + u32 int_pend[GPINT_NUM_BANKS]; + + u32 pri_enc; /* 0x30 */ + u32 _resvd0[3]; /* 0x34-0x3c */ + + /* R/W1S */ + /* u32 int_mask0; 0x40 */ + /* u32 int_mask1; 0x44 */ + /* u32 int_mask2; 0x48 */ + /* u32 int_mask3; 0x4c */ + u32 int_mask[GPINT_NUM_BANKS]; + + /* W1C */ + /* u32 int_maskclr0; 0x50 */ + /* u32 int_maskclr1; 0x54 */ + /* u32 int_maskclr2; 0x58 */ + /* u32 int_maskclr3; 0x5C */ + u32 int_maskclr[GPINT_NUM_BANKS]; + + /* R/W */ + u32 dma_sel; /* 0x60 */ + u32 _resvd1[(0x80-0x64)/4]; /* 0x64-0x7C */ + + /* W */ + /* u32 dev_sel0; 0x80 */ + /* u32 dev_sel1; 0x84 */ + /* u32 dev_sel2; 0x88 */ + /* u32 dev_sel3; 0x8C */ + u32 dev_sel[GPINT_NUM_BANKS]; + + /* W */ + /* u32 dev_selclr0; 0x90 */ + /* u32 dev_selclr1; 0x94 */ + /* u32 dev_selclr2; 0x98 */ + /* u32 dev_selclr3; 0x9C */ + u32 dev_selclr[GPINT_NUM_BANKS]; + + /* R */ + /* u32 reset_val0; 0xA0 */ + /* u32 reset_val1; 0xA4 */ + /* u32 reset_val2; 0xA8 */ + /* u32 reset_val3; 0xAC */ + u32 reset_val[GPINT_NUM_BANKS]; + + /* 0xB0 - 0xFFC */ + u32 _resvd2[(0x1000-0xB0)/4]; + + /* R/W -- when interrupt mask is clear */ + /* R -- when interrupt mask is set */ + /* u32 gp_int0; 0x1000 */ + /* u32 gp_int1; 0x1004 */ + /* u32 gp_int2; 0x1008 */ + /* u32 gp_int2; 0x100C */ + /* u32 gp_intN; 0x1000 + (N*4) */ + u32 gp_int[GPINT_MAX_INTS]; +}; + +extern struct gpio_int_regs *const gpio_int; + +#define GPINT_DMASEL_DMA0 (0) +#define GPINT_DMASEL_DMA0_N(n) (((n)&0xFF)< + * + * Defines and macros for the GPIO and Interrupt controller for Alchemy, + * introduced in the Au13xx series. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#ifndef _MACH_AU1X00_INT_H +#define _MACH_AU1X00_INT_H + +#define NR_IRQS 255 +#define MIPS_CPU_IRQ_BASE 0 + +#endif /* _MACH_AU1X00_INT_H */ -- 1.5.4.3 From khickey@rmicorp.com Fri Mar 20 20:53:11 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 20 Mar 2009 20:53:19 +0000 (GMT) Received: from mx1.rmicorp.com ([63.111.213.197]:60824 "EHLO mx1.rmicorp.com") by ftp.linux-mips.org with ESMTP id S21369953AbZCTUwA (ORCPT ); Fri, 20 Mar 2009 20:52:00 +0000 Received: from sark.razamicroelectronics.com ([10.8.0.254]) by mx1.rmicorp.com with Microsoft SMTPSVC(6.0.3790.3959); Fri, 20 Mar 2009 13:51:46 -0700 Received: from localhost.localdomain (unknown [10.8.0.60]) by sark.razamicroelectronics.com (Postfix) with ESMTP id 34C51EE76D8; Fri, 20 Mar 2009 14:11:47 -0600 (CST) From: Kevin Hickey To: ralf@linux-mips.org, linux-mips@linux-mips.org Cc: Kevin Hickey Subject: [PATCH v2 1/6] Alchemy: Initial Au1300 and DBAu1300 support Date: Fri, 20 Mar 2009 15:51:41 -0500 Message-Id: <1237582306-10800-2-git-send-email-khickey@rmicorp.com> X-Mailer: git-send-email 1.5.4.3 In-Reply-To: <1237582306-10800-1-git-send-email-khickey@rmicorp.com> References: <> <1237582306-10800-1-git-send-email-khickey@rmicorp.com> X-OriginalArrivalTime: 20 Mar 2009 20:51:47.0727 (UTC) FILETIME=[AF9161F0:01C9A99D] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22107 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: khickey@rmicorp.com Precedence: bulk X-list: linux-mips Content-Length: 25777 Lines: 798 This patch introduces the new RMI Alchemy Au1300 series SOC to the kernel, as well as its first development board, the DBAu1300 (or DB1300). This patch is just the basic CPU identification and some resouce constants. Also included are some new Alchemy IO functions and macros, named to match with the current kernel standard. They include au_iowrite32, au_ioread32, etc. These are used heavily in the Au1300/DB1300 code so they need to be included here. Signed-off-by: Kevin Hickey --- arch/mips/Makefile | 6 + arch/mips/alchemy/Kconfig | 6 + arch/mips/alchemy/devboards/Makefile | 1 + arch/mips/alchemy/devboards/db1300/Makefile | 6 + arch/mips/alchemy/devboards/db1300/board_setup.c | 124 +++++++++++++ arch/mips/include/asm/cpu.h | 10 +- arch/mips/include/asm/mach-au1x00/au1000.h | 45 +++++ arch/mips/include/asm/mach-au1x00/au13xx.h | 201 ++++++++++++++++++++++ arch/mips/include/asm/mach-au1x00/au1xxx.h | 3 + arch/mips/include/asm/mach-au1x00/dev_boards.h | 44 +++++ arch/mips/include/asm/mips-boards/db1300.h | 121 +++++++++++++ arch/mips/kernel/cpu-probe.c | 20 ++ arch/mips/mm/c-r4k.c | 1 + arch/mips/mm/tlbex.c | 1 + 14 files changed, 586 insertions(+), 3 deletions(-) create mode 100644 arch/mips/alchemy/devboards/db1300/Makefile create mode 100644 arch/mips/alchemy/devboards/db1300/board_setup.c create mode 100644 arch/mips/include/asm/mach-au1x00/au13xx.h create mode 100644 arch/mips/include/asm/mach-au1x00/dev_boards.h create mode 100644 arch/mips/include/asm/mips-boards/db1300.h diff --git a/arch/mips/Makefile b/arch/mips/Makefile index 21b00e9..15e1577 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -255,6 +255,12 @@ core-$(CONFIG_MIPS_DB1200) += arch/mips/alchemy/devboards/ cflags-$(CONFIG_MIPS_DB1200) += -I$(srctree)/arch/mips/include/asm/mach-db1x00 load-$(CONFIG_MIPS_DB1200) += 0xffffffff80100000 +# RMI Alchemy DBAu1300 development board +# +core-$(CONFIG_MIPS_DB1300) += arch/mips/alchemy/devboards/ +cflags-$(CONFIG_MIPS_DB1300) += -I$(srctree)/arch/mips/include/asm/mach-db1x00 +load-$(CONFIG_MIPS_DB1300) += 0xffffffff80100000 + # # AMD Alchemy Bosporus eval board # diff --git a/arch/mips/alchemy/Kconfig b/arch/mips/alchemy/Kconfig index 7f8ef13..50d426d 100644 --- a/arch/mips/alchemy/Kconfig +++ b/arch/mips/alchemy/Kconfig @@ -53,6 +53,12 @@ config MIPS_DB1550 select MIPS_DISABLE_OBSOLETE_IDE select SYS_SUPPORTS_LITTLE_ENDIAN +config MIPS_DB1300 + bool "Alchemy DBAu1300 Development Board" + select SOC_AU13XX + select DMA_COHERENT + select SYS_SUPPORTS_LITTLE_ENDIAN + config MIPS_MIRAGE bool "Alchemy Mirage board" select DMA_NONCOHERENT diff --git a/arch/mips/alchemy/devboards/Makefile b/arch/mips/alchemy/devboards/Makefile index 730f9f2..0d2d224 100644 --- a/arch/mips/alchemy/devboards/Makefile +++ b/arch/mips/alchemy/devboards/Makefile @@ -12,6 +12,7 @@ obj-$(CONFIG_MIPS_PB1550) += pb1550/ obj-$(CONFIG_MIPS_DB1000) += db1x00/ obj-$(CONFIG_MIPS_DB1100) += db1x00/ obj-$(CONFIG_MIPS_DB1200) += pb1200/ +obj-$(CONFIG_MIPS_DB1300) += db1300/ obj-$(CONFIG_MIPS_DB1500) += db1x00/ obj-$(CONFIG_MIPS_DB1550) += db1x00/ obj-$(CONFIG_MIPS_BOSPORUS) += db1x00/ diff --git a/arch/mips/alchemy/devboards/db1300/Makefile b/arch/mips/alchemy/devboards/db1300/Makefile new file mode 100644 index 0000000..edaff49 --- /dev/null +++ b/arch/mips/alchemy/devboards/db1300/Makefile @@ -0,0 +1,6 @@ +# +# Copyright 2008 RMI Corporation. All rights reserved. +# Author: Kevin Hickey +# + +obj-y := board_setup.o mmc.o diff --git a/arch/mips/alchemy/devboards/db1300/board_setup.c b/arch/mips/alchemy/devboards/db1300/board_setup.c new file mode 100644 index 0000000..be887d4 --- /dev/null +++ b/arch/mips/alchemy/devboards/db1300/board_setup.c @@ -0,0 +1,123 @@ +/* + * Copyright 2003-2008 RMI Corporation. All rights reserved. + * Author: Kevin Hickey + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED BY RMI Corporation 'AS IS' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL RMI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include /* for printk */ + +#include +#include +#include + +#define DB1300_SYSTEM_TYPE_STRING "RMI DBAu1300 Development Board" + +struct bcsr_regs *const bcsr = + (struct bcsr_regs *)(DB1300_BCSR_REGS_PHYS_ADDR + KSEG1); + +extern void (*board_timer_ticked)(void); +extern void (*board_irq_dispatch)(unsigned int); + +/* + * Called by the timer to do board-specific things. In this case, blink an LED + * on every 1000th timer tick. + */ +void db1300_board_timer_ticked(void) +{ + static u8 dots = 1; + static u32 delayer; + + if (++delayer % 1000 == 0) { + db_set_hex_dots(dots++); + dots %= 4; + } +} + +/* + * Called by plat_irq_dispatch to do board-specific things (i.e. display the + * interrupt on a hex output). This should *not* be used for board-specific + * interrupt handling; for that register a new interrupt handler as a device + * driver would do. + */ +void db1300_board_irq_dispatch(unsigned int irq) +{ + if (irq != AU1300_IRQ_RTCMATCH_2) + db_set_hex((u8)irq); +} + +void __init board_setup(void) +{ + char *argptr = NULL; + + printk(KERN_INFO DB1300_SYSTEM_TYPE_STRING "\n"); + + /* + * Add some text to the command line to point the au1200fb driver to + * the board switch. + */ + argptr = prom_getcmdline(); + strcat(argptr, "console=ttyS0,115200 video=au1200fb:panel:bs"); + + /* + * Enable VBUS to the USB Host port + */ + au_set_bits_16(BCSR_RESETS_USB_HOST, &bcsr->resets); + + board_timer_ticked = db1300_board_timer_ticked; + board_irq_dispatch = db1300_board_irq_dispatch; +} + +void board_reset(void) +{ + /* KH: TODO - write board_reset() */ +} + +const char *get_system_type(void) +{ + return DB1300_SYSTEM_TYPE_STRING; +} + +/* + * Board specific functions for the Au1200 Framebuffer driver + */ + +int board_au1200fb_panel(void) +{ + u16 switches = (au_ioread16(&db_bcsr->switches) & 0x0f00) >> 8; + + return switches; +} + +int board_au1200fb_panel_init(void) +{ + /* Apply power */ + au_set_bits_16(0x7, &db_bcsr->board); + return 0; +} + +int board_au1200fb_panel_shutdown(void) +{ + /* Remove power */ + au_clear_bits_16(0x7, &db_bcsr->board); + return 0; +} diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h index c018727..e3528a7 100644 --- a/arch/mips/include/asm/cpu.h +++ b/arch/mips/include/asm/cpu.h @@ -33,9 +33,9 @@ #define PRID_COMP_TOSHIBA 0x070000 #define PRID_COMP_LSI 0x080000 #define PRID_COMP_LEXRA 0x0b0000 +#define PRID_COMP_RMI 0x0c0000 #define PRID_COMP_CAVIUM 0x0d0000 - /* * Assigned values for the product ID register. In order to detect a * certain CPU type exactly eventually additional registers may need to @@ -115,9 +115,13 @@ #define PRID_IMP_BCM3302 0x9000 /* - * These are the PRID's for when 23:16 == PRID_COMP_CAVIUM + * These are the PRID's for when 23:16 == PRID_COMP_RMI */ +#define PRID_IMP_AU13XX 0x8000 +/* + * These are the PRID's for when 23:16 == PRID_COMP_CAVIUM + */ #define PRID_IMP_CAVIUM_CN38XX 0x0000 #define PRID_IMP_CAVIUM_CN31XX 0x0100 #define PRID_IMP_CAVIUM_CN30XX 0x0200 @@ -210,7 +214,7 @@ enum cpu_type_enum { */ CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K, CPU_AU1000, CPU_AU1100, CPU_AU1200, CPU_AU1210, CPU_AU1250, CPU_AU1500, - CPU_AU1550, CPU_PR4450, CPU_BCM3302, CPU_BCM4710, + CPU_AU1550, CPU_AU13XX, CPU_PR4450, CPU_BCM3302, CPU_BCM4710, /* * MIPS64 class processors diff --git a/arch/mips/include/asm/mach-au1x00/au1000.h b/arch/mips/include/asm/mach-au1x00/au1000.h index 62f91f5..c7fe356 100644 --- a/arch/mips/include/asm/mach-au1x00/au1000.h +++ b/arch/mips/include/asm/mach-au1x00/au1000.h @@ -6,6 +6,9 @@ * Copyright 2000-2001, 2006-2008 MontaVista Software Inc. * Author: MontaVista Software, Inc. * + * Copyright 2008 RMI Corporation + * Author: Kevin Hickey + * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the * Free Software Foundation; either version 2 of the License, or (at your @@ -43,6 +46,8 @@ #include #include +#include + /* cpu pipeline flush */ void static inline au_sync(void) { @@ -130,6 +135,46 @@ static inline int au1xxx_cpu_needs_config_od(void) return 0; } +void static inline au_iowrite16(u16 val, volatile u16 *reg) +{ + *reg = val; +} + +static inline u16 au_ioread16(volatile u16 *reg) +{ + return *reg; +} + +void static inline au_iowrite32(u32 val, volatile u32 *reg) +{ + *reg = val; +} + +static inline u32 au_ioread32(volatile u32 *reg) +{ + return *reg; +} + +static inline void au_set_bits_16(u16 mask, volatile u16 *reg) +{ + au_iowrite16((au_ioread16(reg) | mask), reg); +} + +static inline void au_clear_bits_16(u16 mask, volatile u16 *reg) +{ + au_iowrite16((au_ioread16(reg) & ~mask), reg); +} + +static inline void au_set_bits_32(u32 mask, volatile u32 *reg) +{ + au_iowrite32((au_ioread32(reg) | mask), reg); +} + +static inline void au_clear_bits_32(u32 mask, volatile u32 *reg) +{ + au_iowrite32((au_ioread32(reg) & ~mask), reg); +} + /* arch/mips/au1000/common/clocks.c */ extern void set_au1x00_speed(unsigned int new_freq); extern unsigned int get_au1x00_speed(void); diff --git a/arch/mips/include/asm/mach-au1x00/au13xx.h b/arch/mips/include/asm/mach-au1x00/au13xx.h new file mode 100644 index 0000000..ea05234 --- /dev/null +++ b/arch/mips/include/asm/mach-au1x00/au13xx.h @@ -0,0 +1,201 @@ +/* + * Copyright 2008 RMI Corporation + * Author: Kevin Hickey + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef _AU13XX_H +#define _AU13XX_H + +#ifdef CONFIG_SOC_AU13XX +#include + +#define UART0_ADDR 0xB0100000 +#define UART1_ADDR 0xB0101000 +#define UART2_ADDR 0xB0102000 +#define UART3_ADDR 0xB0103000 + +#define GPIO_INT_CTRLR_BASE 0x10200000 +/* + * Linux uses IRQ 0-7 for the 8 causes. That means that all of our channel + * bits need to be offset by 8 either when passed to do_IRQ or when received + * through the irq_chip calls + * + * KH: TODO - This is duplicated from gpio_int.h Is that the right thing to do? + */ +#define GPINT_LINUX_IRQ_OFFSET 8 + +#define AU1300_IRQ_UART1 17 +#define AU1300_IRQ_UART2 25 +#define AU1300_IRQ_UART3 27 +#define AU1300_IRQ_SD1 32 +#define AU1300_IRQ_SD2 38 +#define AU1300_IRQ_PSC0 48 +#define AU1300_IRQ_PSC1 52 +#define AU1300_IRQ_PSC2 56 +#define AU1300_IRQ_PSC3 60 +#define AU1300_IRQ_NAND 62 +#define AU1300_IRQ_DDMA 75 +#define AU1300_IRQ_GPU 78 +#define AU1300_IRQ_MPU 77 +#define AU1300_IRQ_MMU 76 +#define AU1300_IRQ_UDMA 79 +#define AU1300_IRQ_TOY_TICK 80 +#define AU1300_IRQ_TOYMATCH_0 81 +#define AU1300_IRQ_TOYMATCH_1 82 +#define AU1300_IRQ_TOYMATCH_2 83 +#define AU1300_IRQ_RTC_TICK 84 +#define AU1300_IRQ_RTCMATCH_0 85 +#define AU1300_IRQ_RTCMATCH_1 86 +#define AU1300_IRQ_RTCMATCH_2 87 +#define AU1300_IRQ_UART0 88 +#define AU1300_IRQ_SD0 89 +#define AU1300_IRQ_USB 90 +#define AU1300_IRQ_LCD 91 +#define AU1300_IRQ_BSA 94 +#define AU1300_IRQ_MPE 93 +#define AU1300_IRQ_ITE 92 +#define AU1300_IRQ_AES 95 +#define AU1300_IRQ_CIM 96 + +#define LCD_PHYS_ADDR 0x15000000 + +#define AU1200_LCD_INT (GPINT_LINUX_IRQ_OFFSET + AU1300_IRQ_LCD) +#define AU1000_RTC_MATCH2_INT (GPINT_LINUX_IRQ_OFFSET + AU1300_IRQ_RTCMATCH_2) + +#define SD0_PHYS_ADDR 0x10600000 +#define SD1_PHYS_ADDR 0x10601000 + + +#define USB_BASE_PHYS_ADDR 0x14021000 +#define USB_EHCI_BASE 0x14020000 +#define USB_EHCI_LEN 0x400 +#define USB_OHCI_BASE 0x14020800 +#define USB_OHCI_LEN 0x400 +#define USB_UOC_BASE 0x14022000 +#define USB_UOC_LEN 0x20 +#define USB_UDC_BASE 0x14022000 +#define USB_UDC_LEN 0x2000 + +struct au13xx_usb_regs { + u32 dwc_ctrl1; + u32 dwc_ctrl2; + u32 reserved0[2]; + + u32 vbus_timer; + u32 sbus_ctrl; + u32 msr_err; + u32 dwc_ctrl3; + + u32 dwc_ctrl4; + u32 reserved1; + u32 otg_status; + u32 dwc_ctrl5; + + u32 dwc_ctrl6; + u32 dwc_ctrl7; + + u32 reserved2[(0xC0-0x38)/4]; + + u32 phy_status; + u32 intr_status; + u32 intr_enable; + +}; + +#define USB_DWC_CTRL1_OTGD (1<<2) +#define USB_DWC_CTRL1_HSTRS (1<<1) +#define USB_DWC_CTRL1_DCRS (1<<0) + +#define USB_DWC_CTRL2_HTBSE1 (1<<11) +#define USB_DWC_CTRL2_HTBSE0 (1<<10) +#define USB_DWC_CTRL2_LTBSE1 (1<<9) +#define USB_DWC_CTRL2_LTBSE0 (1<<8) +#define USB_DWC_CTRL2_LPBKE1 (1<<5) +#define USB_DWC_CTRL2_LPBKE0 (1<<4) +#define USB_DWC_CTRL2_VBUSD (1<<3) +#define USB_DWC_CTRL2_PH1RS (1<<2) +#define USB_DWC_CTRL2_PHY0RS (1<<1) +#define USB_DWC_CTRL2_PHYRS (1<<0) + +#define USB_VBUS_TIMER(n) (n) + +#define USB_SBUS_CTRL_SBCA (1<<2) +#define USB_SBUS_CTRL_HWSZ (1<<1) +#define USB_SBUS_CTRL_BSZ (1<<0) + +#define USB_MSR_ERR_ILLBM (1<<18) +#define USB_MSR_ERR_ILLBRST (1<<17) +#define USB_MSR_ERR_UADDRSTS (1<<16) +#define USB_MSR_ERR_BMMSK (1<<2) +#define USB_MSR_ERR_BRSTMSK (1<<1) +#define USB_MSR_ERR_UADMK (1<<0) + +#define USB_DWC_CTRL3_VATEST_EN (1<<20) +#define USB_DWC_CTRL3_OHC1_CLKEN (1<<19) +#define USB_DWC_CTRL3_OHC0_CLKEN (1<<18) +#define USB_DWC_CTRL3_EHC_CLKEN (1<<17) +#define USB_DWC_CTRL3_OTG_CLKEN (1<<16) +#define USB_DWC_CTRL3_OHCI_SUSP (1<<3) +#define USB_DWC_CTRL3_VBUS_VALID_PORT1 (1<<2) +#define USB_DWC_CTRL3_VBUS_VALID_PORT0 (1<<1) +#define USB_DWC_CTRL3_VBUS_VALID_SEL (1<<0) + +#define USB_DWC_CTRL4_USB_MODE (1<<16) +#define USB_DWC_CTRL4_AHB_CLKDIV(n) ((n&0xF)<<0) + +#define USB_OTG_STATUS_IDPULLUP (1<<8) +#define USB_OTG_STATUS_IDDIG (1<<7) +#define USB_OTG_STATUS_DISCHRGVBUS (1<<6) +#define USB_OTG_STATUS_CHRGVBUS (1<<5) +#define USB_OTG_STATUS_DRVVBUS (1<<4) +#define USB_OTG_STATUS_SESSIONEND (1<<3) +#define USB_OTG_STATUS_VBUSVALID (1<<2) +#define USB_OTG_STATUS_BVALID (1<<1) +#define USB_OTG_STATUS_AVALID (1<<0) + +#define USB_DWC_CTRL5_REFCLK_DIV(n) ((n&3)<<18) +#define USB_DWC_CTRL5_REFCLK_EN(n) ((n&3)<<16) +#define USB_DWC_CTRL5_SIDDQ (1<<1) +#define USB_DWC_CTRL5_COMMONONN (1<<0) + +#define USB_DWC_CTRL6_DMPULLDOWN_PORT1 (1<<3) +#define USB_DWC_CTRL6_DPPULLDOWN_PORT1 (1<<2) +#define USB_DWC_CTRL6_DMPULLDOWN_PORT2 (1<<1) +#define USB_DWC_CTRL6_DPPULLDOWN_PORT2 (1<<0) + +#define USB_DWC_CTRL7_OHC_STARTCLK (1<<0) + +#define USB_PHY_STATUS_VBUS (1<<0) + +#define USB_INTR_S2A (1<<6) +#define USB_INTR_FORCE (1<<5) +#define USB_INTR_PHY (1<<4) +#define USB_INTR_DEVICE (1<<3) +#define USB_INTR_EHCI (1<<2) +#define USB_INTR_OHCI1 (1<<1) +#define USB_INTR_OHCI0 (1<<0) + +#define AU1000_USB_HOST_INT (AU1300_IRQ_USB + GPINT_LINUX_IRQ_OFFSET) + +#endif /* CONFIG_SOC_AU13XX */ +#endif /* _AU13XX_H */ diff --git a/arch/mips/include/asm/mach-au1x00/au1xxx.h b/arch/mips/include/asm/mach-au1x00/au1xxx.h index 1b36550..9a6d9f1 100644 --- a/arch/mips/include/asm/mach-au1x00/au1xxx.h +++ b/arch/mips/include/asm/mach-au1x00/au1xxx.h @@ -38,6 +38,9 @@ #elif defined(CONFIG_MIPS_DB1200) #include +#elif defined(CONFIG_MIPS_DB1300) +#include + #endif #endif /* _AU1XXX_H_ */ diff --git a/arch/mips/include/asm/mach-au1x00/dev_boards.h b/arch/mips/include/asm/mach-au1x00/dev_boards.h new file mode 100644 index 0000000..27bca17 --- /dev/null +++ b/arch/mips/include/asm/mach-au1x00/dev_boards.h @@ -0,0 +1,44 @@ +/* + * Copyright 2003-2008 RMI Corporation. All rights reserved. + * Author: Kevin Hickey + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED BY RMI Corporation 'AS IS' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL RMI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#ifndef _AU_DEV_BOARDS_H +#define _AU_DEV_BOARDS_H + +#ifdef CONFIG_MIPS_DB1300 +#include +#endif + +#ifdef CONFIG_MIPS_DB1200 +#include +#endif + +void db_set_hex(u8 val); + +/* + * 2 dots use 2 bits + */ +void db_set_hex_dots(u8 val); + +#endif /* _AU_DEV_BOARDS_H */ diff --git a/arch/mips/include/asm/mips-boards/db1300.h b/arch/mips/include/asm/mips-boards/db1300.h new file mode 100644 index 0000000..122432a --- /dev/null +++ b/arch/mips/include/asm/mips-boards/db1300.h @@ -0,0 +1,121 @@ +/* + * Copyright 2003-2008 RMI Corporation. All rights reserved. + * Author: Kevin Hickey + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED BY RMI Corporation 'AS IS' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL RMI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ +#ifndef ASM_DB1300_H +#define ASM_DB1300_H +#ifdef CONFIG_MIPS_DB1300 +#include +#include + +struct db1300_hex_regs { + u16 hex; /* Write 8-bit value here */ + u16 reserved; + u16 blank; /* Write 11b to blank */ +}; + + +#define DB1300_HEX_REGS_PHYS_ADDR 0x19C00000 + +/* For alchemy/dev_boards/leds.c */ +typedef struct db1300_hex_regs hex_regs; +#define HEX_REGS_KSEG1_ADDR (DB1300_HEX_REGS_PHYS_ADDR + KSEG1) + +struct bcsr_regs { + /*00*/ u16 whoami; + u16 reserved0; + /*04*/ u16 status; + u16 reserved1; + /*08*/ u16 switches; + u16 reserved2; + /*0C*/ u16 resets; + u16 reserved3; + + /*10*/ u16 pcmcia; + u16 reserved4; + /*14*/ u16 board; + u16 reserved5; + /*18*/ u16 disk_leds; + u16 reserved6; + /*1C*/ u16 system; + u16 reserved7; + + /*20*/ u16 intclr; + u16 reserved8; + /*24*/ u16 intset; + u16 reserved9; + /*28*/ u16 intclr_mask; + u16 reserved10; + /*2C*/ u16 intset_mask; + u16 reserved11; + + /*30*/ u16 sig_status; + u16 reserved12; + /*34*/ u16 int_status; + u16 reserved13; + /*38*/ u16 reserved14; + u16 reserved15; + /*3C*/ u16 reserved16; + u16 reserved17; +}; + +#define DB1300_BCSR_REGS_PHYS_ADDR 0x19800000 +#define BCSR_REGS_KSEG1_ADDR (KSEG1 + DB1300_BCSR_REGS_PHYS_ADDR) + +static volatile struct bcsr_regs *const db_bcsr = + (struct bcsr_regs *)(DB1300_BCSR_REGS_PHYS_ADDR + KSEG1); + +#define BCSR_STATUS_SD1_WP (1<<10) +#define BCSR_INT_SD1_INSERT (1<<12) + +#define BCSR_RESETS_USB_OTG 0x4000 +#define BCSR_RESETS_USB_HOST 0x8000 + +#define CASCADE_IRQ_MIN 129 + +enum db1300_cascade_irqs { + DB1300_IDE_IRQ = CASCADE_IRQ_MIN, + DB1300_ETHERNET_IRQ, + DB1300_AC97_IRQ, + DB1300_AC97_PEN_IRQ, +}; + +#define CASCADE_IRQ_MAX DB1300_AC97_PEN_IRQ + +#define CASCADE_IRQ (5 + GPINT_LINUX_IRQ_OFFSET) +#define CASCADE_IRQ_TYPE_STRING "DB1300 Cascade" + +/* + * Defines for au1xxx-ide + * See the CPLD/BCSR datasheet for details + */ +#define IDE_PHYS_ADDR 0x18800000 +#define IDE_REG_SHIFT 5 +#define IDE_INT DB1300_IDE_IRQ +#define IDE_DDMA_REQ DSCR_CMD0_DMA_REQ1 +#define IDE_RQSIZE 128 +#define IDE_PHYS_LEN (16 << IDE_REG_SHIFT) + + +#endif /* CONFIG_MIPS_DB1300 */ +#endif /* ASM_DB1300_H */ diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index a7162a4..03e0ae7 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -189,6 +189,7 @@ void __init check_wait(void) case CPU_AU1200: case CPU_AU1210: case CPU_AU1250: + case CPU_AU13XX: cpu_wait = au1k_wait; break; case CPU_20KC: @@ -819,6 +820,20 @@ static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu) } } +static inline void cpu_probe_rmi(struct cpuinfo_mips *c, unsigned int cpu) +{ + decode_configs(c); + switch (c->processor_id & 0xff00) { + case PRID_IMP_AU13XX: + c->cputype = CPU_AU13XX; + __cpu_name[cpu] = "Au13xx"; + break; + default: + panic("Unknown RMI Core!\n"); + break; + } +} + static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu) { decode_configs(c); @@ -936,6 +951,11 @@ __cpuinit void cpu_probe(void) case PRID_COMP_CAVIUM: cpu_probe_cavium(c, cpu); break; + case PRID_COMP_RMI: + cpu_probe_rmi(c, cpu); + break; + default: + c->cputype = CPU_UNKNOWN; } BUG_ON(!__cpu_name[cpu]); diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index c43f4b2..2b4736a 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -1033,6 +1033,7 @@ static void __cpuinit probe_pcache(void) case CPU_AU1200: case CPU_AU1210: case CPU_AU1250: + case CPU_AU13XX: c->icache.flags |= MIPS_CACHE_IC_F_DC; break; } diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index 4294203..ee5e2de 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -299,6 +299,7 @@ static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l, case CPU_AU1200: case CPU_AU1210: case CPU_AU1250: + case CPU_AU13XX: case CPU_PR4450: uasm_i_nop(p); tlbw(p); -- 1.5.4.3 From khickey@rmicorp.com Fri Mar 20 20:53:36 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 20 Mar 2009 20:53:43 +0000 (GMT) Received: from mx1.rmicorp.com ([63.111.213.197]:60824 "EHLO mx1.rmicorp.com") by ftp.linux-mips.org with ESMTP id S20809009AbZCTUwB (ORCPT ); Fri, 20 Mar 2009 20:52:01 +0000 Received: from sark.razamicroelectronics.com ([10.8.0.254]) by mx1.rmicorp.com with Microsoft SMTPSVC(6.0.3790.3959); Fri, 20 Mar 2009 13:51:49 -0700 Received: from localhost.localdomain (unknown [10.8.0.60]) by sark.razamicroelectronics.com (Postfix) with ESMTP id 419D8EE76DD; Fri, 20 Mar 2009 14:11:47 -0600 (CST) From: Kevin Hickey To: ralf@linux-mips.org, linux-mips@linux-mips.org Cc: Kevin Hickey Subject: [PATCH v2 6/6] Alchemy: Au1300: Add LCD framebuffer support Date: Fri, 20 Mar 2009 15:51:46 -0500 Message-Id: <1237582306-10800-7-git-send-email-khickey@rmicorp.com> X-Mailer: git-send-email 1.5.4.3 In-Reply-To: <1237582306-10800-6-git-send-email-khickey@rmicorp.com> References: <> <1237582306-10800-1-git-send-email-khickey@rmicorp.com> <1237582306-10800-2-git-send-email-khickey@rmicorp.com> <1237582306-10800-3-git-send-email-khickey@rmicorp.com> <1237582306-10800-4-git-send-email-khickey@rmicorp.com> <1237582306-10800-5-git-send-email-khickey@rmicorp.com> <1237582306-10800-6-git-send-email-khickey@rmicorp.com> X-OriginalArrivalTime: 20 Mar 2009 20:51:49.0868 (UTC) FILETIME=[B0D812C0:01C9A99D] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22108 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: khickey@rmicorp.com Precedence: bulk X-list: linux-mips Content-Length: 563 Lines: 22 Signed-off-by: Kevin Hickey --- drivers/video/Kconfig | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig index fb19803..9f571df 100644 --- a/drivers/video/Kconfig +++ b/drivers/video/Kconfig @@ -1713,7 +1713,7 @@ config FB_AU1100 config FB_AU1200 bool "Au1200 LCD Driver" - depends on (FB = y) && MIPS && SOC_AU1200 + depends on (FB = y) && MIPS && (SOC_AU1200 || SOC_AU13XX) select FB_CFB_FILLRECT select FB_CFB_COPYAREA select FB_CFB_IMAGEBLIT -- 1.5.4.3 From khickey@rmicorp.com Fri Mar 20 20:54:01 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 20 Mar 2009 20:54:08 +0000 (GMT) Received: from mx1.rmicorp.com ([63.111.213.197]:60824 "EHLO mx1.rmicorp.com") by ftp.linux-mips.org with ESMTP id S21369947AbZCTUwC (ORCPT ); Fri, 20 Mar 2009 20:52:02 +0000 Received: from sark.razamicroelectronics.com ([10.8.0.254]) by mx1.rmicorp.com with Microsoft SMTPSVC(6.0.3790.3959); Fri, 20 Mar 2009 13:51:49 -0700 Received: from localhost.localdomain (unknown [10.8.0.60]) by sark.razamicroelectronics.com (Postfix) with ESMTP id 3FAA1EE76DC; Fri, 20 Mar 2009 14:11:47 -0600 (CST) From: Kevin Hickey To: ralf@linux-mips.org, linux-mips@linux-mips.org Cc: Kevin Hickey Subject: [PATCH v2 5/6] Alchemy: DB1300 blink leds on timer tick Date: Fri, 20 Mar 2009 15:51:45 -0500 Message-Id: <1237582306-10800-6-git-send-email-khickey@rmicorp.com> X-Mailer: git-send-email 1.5.4.3 In-Reply-To: <1237582306-10800-5-git-send-email-khickey@rmicorp.com> References: <> <1237582306-10800-1-git-send-email-khickey@rmicorp.com> <1237582306-10800-2-git-send-email-khickey@rmicorp.com> <1237582306-10800-3-git-send-email-khickey@rmicorp.com> <1237582306-10800-4-git-send-email-khickey@rmicorp.com> <1237582306-10800-5-git-send-email-khickey@rmicorp.com> X-OriginalArrivalTime: 20 Mar 2009 20:51:49.0883 (UTC) FILETIME=[B0DA5CB0:01C9A99D] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22109 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: khickey@rmicorp.com Precedence: bulk X-list: linux-mips Content-Length: 945 Lines: 34 Blinks the dots on the hex display on the DB1300 board every 1000 timer ticks. This can help tell the difference between a soft and hard hung board. Signed-off-by: Kevin Hickey --- arch/mips/alchemy/common/time.c | 5 +++++ 1 files changed, 5 insertions(+), 0 deletions(-) diff --git a/arch/mips/alchemy/common/time.c b/arch/mips/alchemy/common/time.c index f58d4ff..d2352c5 100644 --- a/arch/mips/alchemy/common/time.c +++ b/arch/mips/alchemy/common/time.c @@ -57,6 +57,8 @@ static struct clocksource au1x_counter1_clocksource = { .rating = 100, }; +void (*board_timer_ticked)(void) = NULL; + static int au1x_rtcmatch2_set_next_event(unsigned long delta, struct clock_event_device *cd) { @@ -67,6 +69,9 @@ static int au1x_rtcmatch2_set_next_event(unsigned long delta, au_writel(delta, SYS_RTCMATCH2); au_sync(); + if (board_timer_ticked) + board_timer_ticked(); + return 0; } -- 1.5.4.3 From khickey@rmicorp.com Fri Mar 20 20:54:25 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 20 Mar 2009 20:54:33 +0000 (GMT) Received: from mx1.rmicorp.com ([63.111.213.197]:60824 "EHLO mx1.rmicorp.com") by ftp.linux-mips.org with ESMTP id S21369952AbZCTUwC (ORCPT ); Fri, 20 Mar 2009 20:52:02 +0000 Received: from sark.razamicroelectronics.com ([10.8.0.254]) by mx1.rmicorp.com with Microsoft SMTPSVC(6.0.3790.3959); Fri, 20 Mar 2009 13:51:47 -0700 Received: from localhost.localdomain (unknown [10.8.0.60]) by sark.razamicroelectronics.com (Postfix) with ESMTP id 3D913EE76DB; Fri, 20 Mar 2009 14:11:47 -0600 (CST) From: Kevin Hickey To: ralf@linux-mips.org, linux-mips@linux-mips.org Cc: Kevin Hickey Subject: [PATCH v2 4/6] Alchemy: Au1300/DB1300 peripheral resource declarations Date: Fri, 20 Mar 2009 15:51:44 -0500 Message-Id: <1237582306-10800-5-git-send-email-khickey@rmicorp.com> X-Mailer: git-send-email 1.5.4.3 In-Reply-To: <1237582306-10800-4-git-send-email-khickey@rmicorp.com> References: <> <1237582306-10800-1-git-send-email-khickey@rmicorp.com> <1237582306-10800-2-git-send-email-khickey@rmicorp.com> <1237582306-10800-3-git-send-email-khickey@rmicorp.com> <1237582306-10800-4-git-send-email-khickey@rmicorp.com> X-OriginalArrivalTime: 20 Mar 2009 20:51:49.0868 (UTC) FILETIME=[B0D812C0:01C9A99D] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22110 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: khickey@rmicorp.com Precedence: bulk X-list: linux-mips Content-Length: 10453 Lines: 307 This adds some declarations for peripheral resouces for the first few supported peripherals. This includes USB, LCD, IDE and MMC. Signed-off-by: Kevin Hickey --- arch/mips/alchemy/common/Makefile | 1 + arch/mips/alchemy/common/au13xx_res.c | 74 ++++++++++++++++++++++ arch/mips/alchemy/common/dbdma.c | 46 +++++++++++++- arch/mips/alchemy/common/platform.c | 65 +++++++++++++++++++ arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h | 33 ++++++++++ 5 files changed, 218 insertions(+), 1 deletions(-) create mode 100644 arch/mips/alchemy/common/au13xx_res.c diff --git a/arch/mips/alchemy/common/Makefile b/arch/mips/alchemy/common/Makefile index faa6afd..4e533be 100644 --- a/arch/mips/alchemy/common/Makefile +++ b/arch/mips/alchemy/common/Makefile @@ -9,6 +9,7 @@ obj-y += prom.o puts.o time.o reset.o \ clocks.o platform.o power.o setup.o \ sleeper.o dma.o dbdma.o gpio.o +obj-$(CONFIG_SOC_AU13XX) += au13xx_res.o obj-$(CONFIG_PCI) += pci.o obj-$(CONFIG_AU_GPIO_INT_CNTLR) += gpio_int.o diff --git a/arch/mips/alchemy/common/au13xx_res.c b/arch/mips/alchemy/common/au13xx_res.c new file mode 100644 index 0000000..7d86479 --- /dev/null +++ b/arch/mips/alchemy/common/au13xx_res.c @@ -0,0 +1,74 @@ +/* + * Copyright 2003-2008 RMI Corporation. All rights reserved. + * Author: Kevin Hickey + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED BY RMI Corporation 'AS IS' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL RMI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + */ + +#include +#include +#include + +#include + +#ifdef CONFIG_SOC_AU13XX +/* + * USB Resources for Au13xx + */ +static struct resource au13xx_usb_ehci_resources[] = { + [0] = { + .start = USB_EHCI_BASE, + .end = USB_EHCI_BASE + USB_EHCI_LEN - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AU1300_IRQ_USB + GPINT_LINUX_IRQ_OFFSET, + .end = AU1300_IRQ_USB + GPINT_LINUX_IRQ_OFFSET, + .flags = IORESOURCE_IRQ, + }, +}; + +static u64 ehci_dmamask = DMA_32BIT_MASK; + +static struct platform_device au13xx_usb_ehci_device = { + .name = "au13xx-ehci", + .id = 0, + .dev = { + .dma_mask = &ehci_dmamask, + .coherent_dma_mask = DMA_32BIT_MASK, + }, + .num_resources = ARRAY_SIZE(au13xx_usb_ehci_resources), + .resource = au13xx_usb_ehci_resources, +}; + +static struct platform_device *au13xx_platform_devices[] __initdata = { + &au13xx_usb_ehci_device, +}; + +static int __init au13xx_add_devices(void) +{ + return platform_add_devices(au13xx_platform_devices, + ARRAY_SIZE(au13xx_platform_devices)); +} + +arch_initcall(au13xx_add_devices); + +#endif /* CONFIG_SOC_AU13XX */ diff --git a/arch/mips/alchemy/common/dbdma.c b/arch/mips/alchemy/common/dbdma.c index 3ab6d80..7fda56b 100644 --- a/arch/mips/alchemy/common/dbdma.c +++ b/arch/mips/alchemy/common/dbdma.c @@ -38,7 +38,8 @@ #include #include -#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) +#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) || \ + defined(CONFIG_SOC_AU13XX) /* * The Descriptor Based DMA supports up to 16 channels. @@ -150,6 +151,47 @@ static dbdev_tab_t dbdev_tab[] = { #endif /* CONFIG_SOC_AU1200 */ +#ifdef CONFIG_SOC_AU13XX + { DSCR_CMD0_UART0_TX, DEV_FLAGS_OUT, 0, 8, 0x10100004, 0, 0 }, + { DSCR_CMD0_UART0_RX, DEV_FLAGS_IN, 0, 8, 0x10100000, 0, 0 }, + { DSCR_CMD0_UART1_TX, DEV_FLAGS_OUT, 0, 8, 0x01011004, 0, 0 }, + { DSCR_CMD0_UART1_RX, DEV_FLAGS_IN, 0, 8, 0x10101000, 0, 0 }, + { DSCR_CMD0_UART2_TX, DEV_FLAGS_OUT, 0, 8, 0x01012004, 0, 0 }, + { DSCR_CMD0_UART2_RX, DEV_FLAGS_IN, 0, 8, 0x10102000, 0, 0 }, + { DSCR_CMD0_UART3_TX, DEV_FLAGS_OUT, 0, 8, 0x01013004, 0, 0 }, + { DSCR_CMD0_UART3_RX, DEV_FLAGS_IN, 0, 8, 0x10103000, 0, 0 }, + + { DSCR_CMD0_SDMS_TX0, DEV_FLAGS_OUT, 4, 8, 0x10600000, 0, 0 }, + { DSCR_CMD0_SDMS_RX0, DEV_FLAGS_IN, 4, 8, 0x10600004, 0, 0 }, + { DSCR_CMD0_SDMS_TX1, DEV_FLAGS_OUT, 8, 8, 0x10601000, 0, 0 }, + { DSCR_CMD0_SDMS_RX1, DEV_FLAGS_IN, 8, 8, 0x10601004, 0, 0 }, + + { DSCR_CMD0_AES_RX, DEV_FLAGS_IN , 4, 32, 0x10300008, 0, 0 }, + { DSCR_CMD0_AES_TX, DEV_FLAGS_OUT, 4, 32, 0x10300004, 0, 0 }, + + { DSCR_CMD0_PSC0_TX, DEV_FLAGS_OUT, 0, 16, 0x10a0001c, 0, 0 }, + { DSCR_CMD0_PSC0_RX, DEV_FLAGS_IN, 0, 16, 0x10a0001c, 0, 0 }, + { DSCR_CMD0_PSC1_TX, DEV_FLAGS_OUT, 0, 16, 0x10a0101c, 0, 0 }, + { DSCR_CMD0_PSC1_RX, DEV_FLAGS_IN, 0, 16, 0x10a0101c, 0, 0 }, + { DSCR_CMD0_PSC2_TX, DEV_FLAGS_OUT, 0, 16, 0x10a0201c, 0, 0 }, + { DSCR_CMD0_PSC2_RX, DEV_FLAGS_IN, 0, 16, 0x10a0201c, 0, 0 }, + { DSCR_CMD0_PSC3_TX, DEV_FLAGS_OUT, 0, 16, 0x10a0301c, 0, 0 }, + { DSCR_CMD0_PSC3_RX, DEV_FLAGS_IN, 0, 16, 0x10a0301c, 0, 0 }, + + { DSCR_CMD0_LCD, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, + { DSCR_CMD0_NAND_FLASH, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 }, + + { DSCR_CMD0_SDMS_TX2, DEV_FLAGS_OUT, 4, 8, 0x10602000, 0, 0 }, + { DSCR_CMD0_SDMS_RX2, DEV_FLAGS_IN, 4, 8, 0x10602004, 0, 0 }, + + { DSCR_CMD0_CIM_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, + + { DSCR_CMD0_UDMA, DEV_FLAGS_ANYUSE, 0, 32, 0x14001810, 0, 0 }, + + { DSCR_CMD0_DMA_REQ0, 0, 0, 0, 0x00000000, 0, 0 }, + { DSCR_CMD0_DMA_REQ1, 0, 0, 0, 0x00000000, 0, 0 }, +#endif /* CONFIG_SOC_AU13XX */ + { DSCR_CMD0_THROTTLE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, { DSCR_CMD0_ALWAYS, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 }, @@ -881,6 +923,8 @@ static void au1xxx_dbdma_init(void) irq_nr = AU1550_DDMA_INT; #elif defined(CONFIG_SOC_AU1200) irq_nr = AU1200_DDMA_INT; +#elif defined(CONFIG_SOC_AU13XX) + irq_nr = AU1300_IRQ_DDMA + GPINT_LINUX_IRQ_OFFSET; #else #error Unknown Au1x00 SOC #endif diff --git a/arch/mips/alchemy/common/platform.c b/arch/mips/alchemy/common/platform.c index 78fd862..6d2acff 100644 --- a/arch/mips/alchemy/common/platform.c +++ b/arch/mips/alchemy/common/platform.c @@ -336,14 +336,79 @@ static struct platform_device pbdb_smbus_device = { }; #endif +#ifdef CONFIG_SOC_AU13XX +static struct resource au1200_lcd_resources[] = { + [0] = { + .start = LCD_PHYS_ADDR, + .end = LCD_PHYS_ADDR + 0x800 - 1, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AU1300_IRQ_LCD + 8, + .end = AU1300_IRQ_LCD + 8, + .flags = IORESOURCE_IRQ, + } +}; + +static u64 au1200_lcd_dmamask = DMA_32BIT_MASK; + +static struct platform_device au1200_lcd_device = { + .name = "au1200-lcd", + .id = 0, + .dev = { + .dma_mask = &au1200_lcd_dmamask, + .coherent_dma_mask = DMA_32BIT_MASK, + }, + .num_resources = ARRAY_SIZE(au1200_lcd_resources), + .resource = au1200_lcd_resources, +}; + +extern struct platform_device au13xx_mmc1_device; + +extern struct au1xmmc_platform_data au1xmmc_platdata[2]; +static struct resource ide_resources[] = { + [0] = { + .start = IDE_PHYS_ADDR, + .end = IDE_PHYS_ADDR + IDE_PHYS_LEN - 1, + .flags = IORESOURCE_MEM + }, + [1] = { + .start = IDE_INT, + .end = IDE_INT, + .flags = IORESOURCE_IRQ + } +}; + +static u64 ide_dmamask = DMA_32BIT_MASK; + +static struct platform_device ide_device = { + .name = "au1200-ide", + .id = 0, + .dev = { + .dma_mask = &ide_dmamask, + .coherent_dma_mask = DMA_32BIT_MASK, + }, + .num_resources = ARRAY_SIZE(ide_resources), + .resource = ide_resources +}; + +#endif + + static struct platform_device *au1xxx_platform_devices[] __initdata = { &au1xx0_uart_device, +#ifdef CONFIG_SOC_AU13XX + &au1200_lcd_device, + &ide_device, + &au13xx_mmc1_device, &au1xxx_usb_ohci_device, +#endif &au1x00_pcmcia_device, #ifdef CONFIG_FB_AU1100 &au1100_lcd_device, #endif #ifdef CONFIG_SOC_AU1200 + &au1xxx_usb_ohci_device, &au1xxx_usb_ehci_device, &au1xxx_usb_gdt_device, &au1xxx_usb_otg_device, diff --git a/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h b/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h index 06f68f4..1c36b9f 100644 --- a/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h +++ b/arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h @@ -195,6 +195,39 @@ typedef volatile struct au1xxx_ddma_desc { #define DSCR_CMD0_CIM_SYNC 26 #endif /* CONFIG_SOC_AU1200 */ +#ifdef CONFIG_SOC_AU13XX +#define DSCR_CMD0_UART0_TX 0 +#define DSCR_CMD0_UART0_RX 1 +#define DSCR_CMD0_UART1_TX 2 +#define DSCR_CMD0_UART1_RX 3 +#define DSCR_CMD0_UART2_TX 4 +#define DSCR_CMD0_UART2_RX 5 +#define DSCR_CMD0_UART3_TX 6 +#define DSCR_CMD0_UART3_RX 7 +#define DSCR_CMD0_SDMS_TX0 8 +#define DSCR_CMD0_SDMS_RX0 9 +#define DSCR_CMD0_SDMS_TX1 10 +#define DSCR_CMD0_SDMS_RX1 11 +#define DSCR_CMD0_AES_TX 12 +#define DSCR_CMD0_AES_RX 13 +#define DSCR_CMD0_PSC0_TX 14 +#define DSCR_CMD0_PSC0_RX 15 +#define DSCR_CMD0_PSC1_TX 16 +#define DSCR_CMD0_PSC1_RX 17 +#define DSCR_CMD0_PSC2_TX 18 +#define DSCR_CMD0_PSC2_RX 19 +#define DSCR_CMD0_PSC3_TX 20 +#define DSCR_CMD0_PSC3_RX 21 +#define DSCR_CMD0_LCD 22 +#define DSCR_CMD0_NAND_FLASH 23 +#define DSCR_CMD0_SDMS_TX2 24 +#define DSCR_CMD0_SDMS_RX2 25 +#define DSCR_CMD0_CIM_SYNC 26 +#define DSCR_CMD0_UDMA 27 +#define DSCR_CMD0_DMA_REQ0 28 +#define DSCR_CMD0_DMA_REQ1 29 +#endif /* CONFIG_SOC_AU13XX */ + #define DSCR_CMD0_THROTTLE 30 #define DSCR_CMD0_ALWAYS 31 #define DSCR_NDEV_IDS 32 -- 1.5.4.3 From nils.faerber@kernelconcepts.de Fri Mar 20 23:45:37 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 20 Mar 2009 23:45:44 +0000 (GMT) Received: from mail.kernelconcepts.de ([212.60.202.196]:6573 "EHLO mail.kernelconcepts.de") by ftp.linux-mips.org with ESMTP id S21367165AbZCTXph (ORCPT ); Fri, 20 Mar 2009 23:45:37 +0000 Received: from [92.227.178.70] (helo=[192.168.178.35]) by mail.kernelconcepts.de with esmtpsa (TLS-1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.63) (envelope-from ) id 1LkogM-0003Ed-TG for linux-mips@linux-mips.org; Sat, 21 Mar 2009 01:03:23 +0100 Message-ID: <49C42A9B.5050103@kernelconcepts.de> Date: Sat, 21 Mar 2009 00:45:31 +0100 From: Nils Faerber User-Agent: Thunderbird 2.0.0.19 (X11/20090105) MIME-Version: 1.0 To: linux-mips@linux-mips.org Subject: Need help iterpreting reg-dump X-Enigmail-Version: 0.95.0 Content-Type: text/plain; charset=ISO-8859-15 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22111 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: nils.faerber@kernelconcepts.de Precedence: bulk X-list: linux-mips Content-Length: 2999 Lines: 77 Hello all! By some (unlucky :) coincidence I recently came into posession of a Ingenic JZ4730 based subnotebook and am since trying to get a more recent kernel to boot. The only base I have at hand is 2.6.24.3 - sorry for that. I already described most of the details in an earlier post "Ingenic JZ4730 - illegal instruction". Anyway I chased the issue further an now found at lteast a single point in the kernel where the SIGILL for the applicaiton is generated, it is arch/mips/kernel/unaligned.c When I set the action to UNALIGNED_ACTION_SHOW I get the following dump whenever an application causes the fault to happen: [42949562.570000] Cpu 0 [42949562.570000] $ 0 : 00000000 10000400 ffffff93 00000020 [42949562.580000] $ 4 : 00000001 0000006d 000000c0 2aad225d [42949562.580000] $ 8 : 00000040 fffffffe 0000000c 0000000c [42949562.590000] $12 : 0000006d 00000003 00000003 00000000 [42949562.590000] $16 : 2aad2ee8 2aad2ef0 005ab1d8 005ab1e0 [42949562.600000] $20 : 7f8faae0 2b2a6340 7f8faa40 2aad2ee8 [42949562.610000] $24 : 00000000 2b283010 [42949562.610000] $28 : 2b2ae420 7f8faa08 00000001 2b27bda0 [42949562.620000] Hi : 00000002 [42949562.620000] Lo : 0f02cdc0 [42949562.620000] epc : 7f8faa00 0x7f8faa00 Not tainted [42949562.630000] ra : 2b27bda0 0x2b27bda0 [42949562.630000] Status: 00000413 USER EXL IE [42949562.640000] Cause : 00800010 [42949562.640000] BadVA : 00000001 [42949562.640000] PrId : 02d0024f (Ingenic JZRISC) [42949562.650000] Modules linked in: [42949562.650000] Process gpe-info (pid: 1476, threadinfo=87cac000, task=87dc29d 8) [42949562.660000] Stack : 2b2ae420 7f8faa58 00000000 2b665794 2b2ae420 2b665794 2b27b8a0 2b27b8d8 [42949562.670000] 2b750950 004b6ab8 2b74a75c 00000010 2b2ae420 2aad2e30 00000003 00000005 [42949562.680000] 2aad2250 005a27d0 a2879f2e 547d42ae 2aad2e40 00000001 00598ad0 2aad2e30 [42949562.680000] 005a27d0 7f8faae0 7f8faad8 2b27b72c 7f8faaf0 2b27c8ec 00000000 40237200 [42949562.690000] eb851eb8 401c0051 7ff80000 7ff80000 7ff80000 7ff80000 7ff80000 7ff80000 [42949562.700000] ... [42949562.710000] Call Trace: [42949562.710000] [42949562.710000] [42949562.710000] Code: 2aad2ef0 8fbc0010 8c000001 <0000bd36> 2b27bd7c 2b2ae4 20 7f8faa58 00000000 2b665794 The interesting point for me is now that I always end up in the unaligned handler and never in some other random handler. This tells me that the cache is probably not the faulty part (since then different illegal instrcustion should occur) but rather the unalignement handling. I am not familiar enough with MIPS to decipher the dump into something useful. So could someone maybe give me at least a hint in which direction to look? A little bit more specific than just "CPU manual" would be great ;) Many thanks in advance! Cheers nils faerber -- kernel concepts GbR Tel: +49-271-771091-12 Sieghuetter Hauptweg 48 Fax: +49-271-771091-19 D-57072 Siegen Mob: +49-176-21024535 -- From weiyi.huang@gmail.com Sat Mar 21 05:50:56 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 21 Mar 2009 05:51:03 +0000 (GMT) Received: from ti-out-0910.google.com ([209.85.142.191]:47180 "EHLO ti-out-0910.google.com") by ftp.linux-mips.org with ESMTP id S21366539AbZCUFu4 (ORCPT ); Sat, 21 Mar 2009 05:50:56 +0000 Received: by ti-out-0910.google.com with SMTP id d27so817130tid.20 for ; Fri, 20 Mar 2009 22:50:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:subject:date :message-id:x-mailer; bh=uoz5f6sF0GoQ+7vkYNoPWgpmBJ6eUnF9PvrvOg2JhOI=; b=BzKraesYEEUcyCOZQSt34uHvfsUtv8wnTCW2PzorvVgLn3hVMYlg70M163CHskkokW 2IZZorXVWzYZuzEe/CNzKT80zsRfBITuttJIp4x9OuxKb50BbmZL1YAzZtnp71D2QLq9 DBAToOra96VPbfYMS+wNxNDwnbu//SKHLfOns= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:subject:date:message-id:x-mailer; b=pQkDCEQiM10jU7QNmZHJWUn74y9Fp8fy9kh1Y/4WVisRQON9NaKv0Wl50BWmo2k59j 374T5Ps8KVc/SgX8C7B6B6tGJP4MAIEvAvv4pRg//obIIwixyqgOECEPXKg7Op2EFl02 i5PwEsZEKackqT4ythVk/nUdY06cGBLX869uk= Received: by 10.110.46.3 with SMTP id t3mr6186245tit.20.1237614653014; Fri, 20 Mar 2009 22:50:53 -0700 (PDT) Received: from localhost.localdomain ([58.212.81.44]) by mx.google.com with ESMTPS id a14sm458187tia.27.2009.03.20.22.50.51 (version=TLSv1/SSLv3 cipher=RC4-MD5); Fri, 20 Mar 2009 22:50:52 -0700 (PDT) From: Huang Weiyi To: ralf@linux-mips.org Cc: linux-mips@linux-mips.org, Huang Weiyi Subject: [PATCH] MIPS: remove duplicated #include Date: Sat, 21 Mar 2009 13:50:48 +0800 Message-Id: <1237614648-3840-1-git-send-email-weiyi.huang@gmail.com> X-Mailer: git-send-email 1.6.0.4 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22112 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: weiyi.huang@gmail.com Precedence: bulk X-list: linux-mips Content-Length: 586 Lines: 22 Remove duplicated #include in arch/mips/kernel/linux32.c. Signed-off-by: Huang Weiyi --- arch/mips/kernel/linux32.c | 1 - 1 files changed, 0 insertions(+), 1 deletions(-) diff --git a/arch/mips/kernel/linux32.c b/arch/mips/kernel/linux32.c index 1a86f84..49aac6e 100644 --- a/arch/mips/kernel/linux32.c +++ b/arch/mips/kernel/linux32.c @@ -32,7 +32,6 @@ #include #include #include -#include #include #include #include -- 1.6.0.4 From kevink@paralogos.com Sat Mar 21 10:37:37 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 21 Mar 2009 10:37:43 +0000 (GMT) Received: from gateway09.websitewelcome.com ([69.93.35.26]:41402 "HELO gateway09.websitewelcome.com") by ftp.linux-mips.org with SMTP id S21367474AbZCUKhh (ORCPT ); Sat, 21 Mar 2009 10:37:37 +0000 Received: (qmail 24306 invoked from network); 21 Mar 2009 10:38:04 -0000 Received: from gator750.hostgator.com (174.132.194.2) by gateway09.websitewelcome.com with SMTP; 21 Mar 2009 10:38:04 -0000 Received: from [217.109.65.213] (port=1379 helo=[192.168.236.58]) by gator750.hostgator.com with esmtpa (Exim 4.69) (envelope-from ) id 1Lkya4-000264-DI; Sat, 21 Mar 2009 05:37:32 -0500 Message-ID: <49C4C36B.7010606@paralogos.com> Date: Sat, 21 Mar 2009 05:37:31 -0500 From: "Kevin D. Kissell" User-Agent: Thunderbird 2.0.0.21 (Windows/20090302) MIME-Version: 1.0 To: Nils Faerber CC: linux-mips@linux-mips.org Subject: Re: Need help iterpreting reg-dump References: <49C42A9B.5050103@kernelconcepts.de> In-Reply-To: <49C42A9B.5050103@kernelconcepts.de> Content-Type: text/plain; charset=ISO-8859-15; format=flowed Content-Transfer-Encoding: 7bit X-AntiAbuse: This header was added to track abuse, please include it with any abuse report X-AntiAbuse: Primary Hostname - gator750.hostgator.com X-AntiAbuse: Original Domain - linux-mips.org X-AntiAbuse: Originator/Caller UID/GID - [47 12] / [47 12] X-AntiAbuse: Sender Address Domain - paralogos.com Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22113 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: kevink@paralogos.com Precedence: bulk X-list: linux-mips Content-Length: 4759 Lines: 108 Do the programs that are failing contain floating point code? The most interesting thing about your dump is that the EPC address, which should point to the instruction generating the fault, looks to be a user stack address, which suggests a trampoline function. It just so happens that the FPU emulator logic sets up a sort of trampoline to deal with instructions in the delay slots of FP branches, and this trampoline deliberately causes an unaligned access trap as a way of transferring control back to the kernel. Furthermore, the unaligned access trap is a "lw $0,1($0)", which would cause the BadVA value to be 0x00000001 - which is what your dump is reporting. Unfortunately, the trampoline is set just *above* the top of the user stack, so the stack dump in the diagnostic output below won't show it, nor the "cookie" (0x0000bd36) that should have followed it in memory to confirm that it's a deliberate trap (the stack needs to be aligned anyway, so we put in a sort of signature). So, while I can't prove anything conclusive based on the dump below, it suggests that the processor took a CP1 exception on an instruction that was emulated as an FP branch, so that the branch delay slot instruction had to be executed off the top of the stack in the delay slot emulation code, but that something was screwed up so that the call to do_dsemulret() in do_ade() returned zero, so the unaligned access handling threw a signal instead of ignoring it. The diagnostic code probably hasn't been armed in years, but if you #define DSEMUL_TRACE when the code in arch/mips/math-emu is built (or just hack it into dsemul.h or dsemul.c), it would help confirm or deny the hypothesis. Regards, Kevin K. Nils Faerber wrote: > Hello all! > By some (unlucky :) coincidence I recently came into posession of a > Ingenic JZ4730 based subnotebook and am since trying to get a more > recent kernel to boot. The only base I have at hand is 2.6.24.3 - sorry > for that. I already described most of the details in an earlier post > "Ingenic JZ4730 - illegal instruction". > Anyway I chased the issue further an now found at lteast a single point > in the kernel where the SIGILL for the applicaiton is generated, it is > arch/mips/kernel/unaligned.c > > When I set the action to UNALIGNED_ACTION_SHOW I get the following dump > whenever an application causes the fault to happen: > > [42949562.570000] Cpu 0 > [42949562.570000] $ 0 : 00000000 10000400 ffffff93 00000020 > [42949562.580000] $ 4 : 00000001 0000006d 000000c0 2aad225d > [42949562.580000] $ 8 : 00000040 fffffffe 0000000c 0000000c > [42949562.590000] $12 : 0000006d 00000003 00000003 00000000 > [42949562.590000] $16 : 2aad2ee8 2aad2ef0 005ab1d8 005ab1e0 > [42949562.600000] $20 : 7f8faae0 2b2a6340 7f8faa40 2aad2ee8 > [42949562.610000] $24 : 00000000 2b283010 > [42949562.610000] $28 : 2b2ae420 7f8faa08 00000001 2b27bda0 > [42949562.620000] Hi : 00000002 > [42949562.620000] Lo : 0f02cdc0 > [42949562.620000] epc : 7f8faa00 0x7f8faa00 Not tainted > [42949562.630000] ra : 2b27bda0 0x2b27bda0 > [42949562.630000] Status: 00000413 USER EXL IE > [42949562.640000] Cause : 00800010 > [42949562.640000] BadVA : 00000001 > [42949562.640000] PrId : 02d0024f (Ingenic JZRISC) > [42949562.650000] Modules linked in: > [42949562.650000] Process gpe-info (pid: 1476, threadinfo=87cac000, > task=87dc29d > 8) > [42949562.660000] Stack : 2b2ae420 7f8faa58 00000000 2b665794 2b2ae420 > 2b665794 > 2b27b8a0 2b27b8d8 > [42949562.670000] 2b750950 004b6ab8 2b74a75c 00000010 2b2ae420 > 2aad2e30 > 00000003 00000005 > [42949562.680000] 2aad2250 005a27d0 a2879f2e 547d42ae 2aad2e40 > 00000001 > 00598ad0 2aad2e30 > [42949562.680000] 005a27d0 7f8faae0 7f8faad8 2b27b72c 7f8faaf0 > 2b27c8ec > 00000000 40237200 > [42949562.690000] eb851eb8 401c0051 7ff80000 7ff80000 7ff80000 > 7ff80000 > 7ff80000 7ff80000 > [42949562.700000] ... > [42949562.710000] Call Trace: > [42949562.710000] > [42949562.710000] > [42949562.710000] Code: 2aad2ef0 8fbc0010 8c000001 <0000bd36> 2b27bd7c > 2b2ae4 > 20 7f8faa58 00000000 2b665794 > > > The interesting point for me is now that I always end up in the > unaligned handler and never in some other random handler. This tells me > that the cache is probably not the faulty part (since then different > illegal instrcustion should occur) but rather the unalignement handling. > I am not familiar enough with MIPS to decipher the dump into something > useful. > So could someone maybe give me at least a hint in which direction to > look? A little bit more specific than just "CPU manual" would be great ;) > > Many thanks in advance! > > Cheers > nils faerber > > From anemo@mba.ocn.ne.jp Sat Mar 21 12:29:23 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 21 Mar 2009 12:29:30 +0000 (GMT) Received: from mba.ocn.ne.jp ([122.1.235.107]:46062 "HELO smtp.mba.ocn.ne.jp") by ftp.linux-mips.org with SMTP id S21369760AbZCUM3V convert rfc822-to-8bit (ORCPT ); Sat, 21 Mar 2009 12:29:21 +0000 Received: from localhost (p3064-ipad303funabasi.chiba.ocn.ne.jp [123.217.149.64]) by smtp.mba.ocn.ne.jp (Postfix) with ESMTP id AAE1AA7AD; Sat, 21 Mar 2009 21:29:14 +0900 (JST) Date: Sat, 21 Mar 2009 21:29:20 +0900 (JST) Message-Id: <20090321.212920.25912728.anemo@mba.ocn.ne.jp> To: dan.j.williams@intel.com Cc: linux-mips@linux-mips.org, ralf@linux-mips.org, linux-kernel@vger.kernel.org, haavard.skinnemoen@atmel.com Subject: Re: [PATCH 1/2] dmaengine: TXx9 Soc DMA Controller driver From: Atsushi Nemoto In-Reply-To: References: <20090318.110154.76582864.nemoto@toshiba-tops.co.jp> X-Fingerprint: 6ACA 1623 39BD 9A94 9B1A B746 CA77 FE94 2874 D52F X-Pgp-Public-Key: http://wwwkeys.pgp.net/pks/lookup?op=get&search=0x2874D52F X-Mailer: Mew version 5.2 on Emacs 21.4 / Mule 5.0 (SAKAKI) Mime-Version: 1.0 Content-Type: Text/Plain; charset=iso-8859-1 Content-Transfer-Encoding: 8BIT Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22114 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anemo@mba.ocn.ne.jp Precedence: bulk X-list: linux-mips Content-Length: 1267 Lines: 30 On Wed, 18 Mar 2009 10:26:13 -0700, Dan Williams wrote: > > The atmel-mci does not select "channel". It just pick the first > > usable channel of the dma_device specified by platform_data. I > > suppose dw_dmac is symmetric (it can use any channel for any slave). > > You are right, it does not hardwire the channel, but it does hardwire > the device, see at32_add_device_mci [1]. > > > But TXx9 SoC DMAC channels are hardwired to each peripheral devices. > > I think creating a dma_device instance per channel and specifying that > device like atmel-mci is the more future-proof way to go. Well, I have considered it but it looks overkill for me at that time. Maybe time to think again... > > And I want to call Channel-3 of DMAC-0 "dma0chan3" even if Channel-2 > > was assigned to for public memcpy channel. > > The problem is you could pass in the chan_id to guarantee 'chan3', but > there is no guarantee that you will get 'dma0', as the driver has no > knowledge of what other dma devices may be in the system. Yes, I do not expect 'dma0'. My filter function uses dev_name(chan->device->dev), which is "txx9dmac.0" in this case. Anyway, "one dma-device per channel" manner will make things much simpler. --- Atsushi Nemoto From skuribay@ruby.dti.ne.jp Sat Mar 21 13:04:27 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 21 Mar 2009 13:04:34 +0000 (GMT) Received: from smtp14.dti.ne.jp ([202.216.231.189]:65535 "EHLO smtp14.dti.ne.jp") by ftp.linux-mips.org with ESMTP id S21369760AbZCUNE1 (ORCPT ); Sat, 21 Mar 2009 13:04:27 +0000 Received: from [192.168.1.5] (PPPax1767.tokyo-ip.dti.ne.jp [210.159.179.17]) by smtp14.dti.ne.jp (3.11s) with ESMTP AUTH id n2LD4Ls8018579;Sat, 21 Mar 2009 22:04:24 +0900 (JST) Message-ID: <49C4E5D5.4070408@ruby.dti.ne.jp> Date: Sat, 21 Mar 2009 22:04:21 +0900 From: Shinya Kuribayashi User-Agent: Thunderbird 2.0.0.21 (X11/20090318) MIME-Version: 1.0 To: ralf@linux-mips.org, linux-mips@linux-mips.org Subject: [PATCH] MIPS: Mark Eins: Fix cascading interrupt dispatcher Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22115 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: skuribay@ruby.dti.ne.jp Precedence: bulk X-list: linux-mips Content-Length: 1663 Lines: 50 * Fix mis-calculated IRQ bitshift on cascading interrupts * Prevent cascading interrupt bits being processed afterward Signed-off-by: Shinya Kuribayashi --- arch/mips/emma/markeins/irq.c | 10 ++++++---- 1 files changed, 6 insertions(+), 4 deletions(-) diff --git a/arch/mips/emma/markeins/irq.c b/arch/mips/emma/markeins/irq.c index c2583ec..263132d 100644 --- a/arch/mips/emma/markeins/irq.c +++ b/arch/mips/emma/markeins/irq.c @@ -213,8 +213,7 @@ void emma2rh_irq_dispatch(void) emma2rh_in32(EMMA2RH_BHIF_INT_EN_0); #ifdef EMMA2RH_SW_CASCADE - if (intStatus & - (1 << ((EMMA2RH_SW_CASCADE - EMMA2RH_IRQ_INT0) & (32 - 1)))) { + if (intStatus & (1UL << EMMA2RH_SW_CASCADE)) { u32 swIntStatus; swIntStatus = emma2rh_in32(EMMA2RH_BHIF_SW_INT) & emma2rh_in32(EMMA2RH_BHIF_SW_INT_EN); @@ -225,6 +224,8 @@ void emma2rh_irq_dispatch(void) } } } + /* Skip S/W interrupt */ + intStatus &= ~(1UL << EMMA2RH_SW_CASCADE); #endif for (i = 0, bitmask = 1; i < 32; i++, bitmask <<= 1) { @@ -238,8 +239,7 @@ void emma2rh_irq_dispatch(void) emma2rh_in32(EMMA2RH_BHIF_INT_EN_1); #ifdef EMMA2RH_GPIO_CASCADE - if (intStatus & - (1 << ((EMMA2RH_GPIO_CASCADE - EMMA2RH_IRQ_INT0) & (32 - 1)))) { + if (intStatus & (1UL << (EMMA2RH_GPIO_CASCADE % 32))) { u32 gpioIntStatus; gpioIntStatus = emma2rh_in32(EMMA2RH_GPIO_INT_ST) & emma2rh_in32(EMMA2RH_GPIO_INT_MASK); @@ -250,6 +250,8 @@ void emma2rh_irq_dispatch(void) } } } + /* Skip GPIO interrupt */ + intStatus &= ~(1UL << (EMMA2RH_GPIO_CASCADE % 32)); #endif for (i = 32, bitmask = 1; i < 64; i++, bitmask <<= 1) { From skuribay@ruby.dti.ne.jp Sat Mar 21 13:06:16 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 21 Mar 2009 13:06:23 +0000 (GMT) Received: from smtp14.dti.ne.jp ([202.216.231.189]:1152 "EHLO smtp14.dti.ne.jp") by ftp.linux-mips.org with ESMTP id S21368468AbZCUNGQ (ORCPT ); Sat, 21 Mar 2009 13:06:16 +0000 Received: from [192.168.1.5] (PPPax1767.tokyo-ip.dti.ne.jp [210.159.179.17]) by smtp14.dti.ne.jp (3.11s) with ESMTP AUTH id n2LD6Eqm018597;Sat, 21 Mar 2009 22:06:14 +0900 (JST) Message-ID: <49C4E646.7010309@ruby.dti.ne.jp> Date: Sat, 21 Mar 2009 22:06:14 +0900 From: Shinya Kuribayashi User-Agent: Thunderbird 2.0.0.21 (X11/20090318) MIME-Version: 1.0 To: ralf@linux-mips.org, linux-mips@linux-mips.org Subject: [PATCH] MIPS: EMMA2RH: Use handle_edge_irq() handler for GPIO interrupts References: <49C4E5D5.4070408@ruby.dti.ne.jp> In-Reply-To: <49C4E5D5.4070408@ruby.dti.ne.jp> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22116 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: skuribay@ruby.dti.ne.jp Precedence: bulk X-list: linux-mips Content-Length: 2564 Lines: 80 EMMA's GPIO interrupts are latched by GPIO interrupt status register. In this case, we're encouraged to use handle_edge_irq() handler. The following changes are made along with replacing set_irq_chip() with set_irq_chip_and_handler_name(,,handle_edge_irq,"edge"): * Fix emma2rh_gpio_irq_ack not to disable interrupts With handle_edge_irq(), we're not expected to disable interrupts when chip->ack is served, so fix it accordingly. We also add a new emma2rh_gpio_irq_mask_ack() for chip->mask_ack operation, instead. * Remove emma2rh_gpio_irq_end(), as chip->end is no longer served. Signed-off-by: Shinya Kuribayashi --- arch/mips/emma/markeins/irq.c | 28 ++++++++++------------------ 1 files changed, 10 insertions(+), 18 deletions(-) diff --git a/arch/mips/emma/markeins/irq.c b/arch/mips/emma/markeins/irq.c index 263132d..1e6457c 100644 --- a/arch/mips/emma/markeins/irq.c +++ b/arch/mips/emma/markeins/irq.c @@ -149,37 +149,28 @@ static void emma2rh_gpio_irq_disable(unsigned int irq) static void emma2rh_gpio_irq_ack(unsigned int irq) { - u32 reg; - irq -= EMMA2RH_GPIO_IRQ_BASE; emma2rh_out32(EMMA2RH_GPIO_INT_ST, ~(1 << irq)); - - reg = emma2rh_in32(EMMA2RH_GPIO_INT_MASK); - reg &= ~(1 << irq); - emma2rh_out32(EMMA2RH_GPIO_INT_MASK, reg); } -static void emma2rh_gpio_irq_end(unsigned int irq) +static void emma2rh_gpio_irq_mask_ack(unsigned int irq) { u32 reg; - if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) { - - irq -= EMMA2RH_GPIO_IRQ_BASE; + irq -= EMMA2RH_GPIO_IRQ_BASE; + emma2rh_out32(EMMA2RH_GPIO_INT_ST, ~(1 << irq)); - reg = emma2rh_in32(EMMA2RH_GPIO_INT_MASK); - reg |= 1 << irq; - emma2rh_out32(EMMA2RH_GPIO_INT_MASK, reg); - } + reg = emma2rh_in32(EMMA2RH_GPIO_INT_MASK); + reg &= ~(1 << irq); + emma2rh_out32(EMMA2RH_GPIO_INT_MASK, reg); } struct irq_chip emma2rh_gpio_irq_controller = { .name = "emma2rh_gpio_irq", .ack = emma2rh_gpio_irq_ack, .mask = emma2rh_gpio_irq_disable, - .mask_ack = emma2rh_gpio_irq_ack, + .mask_ack = emma2rh_gpio_irq_mask_ack, .unmask = emma2rh_gpio_irq_enable, - .end = emma2rh_gpio_irq_end, }; void emma2rh_gpio_irq_init(void) @@ -187,8 +178,9 @@ void emma2rh_gpio_irq_init(void) u32 i; for (i = 0; i < NUM_EMMA2RH_IRQ_GPIO; i++) - set_irq_chip(EMMA2RH_GPIO_IRQ_BASE + i, - &emma2rh_gpio_irq_controller); + set_irq_chip_and_handler_name(EMMA2RH_GPIO_IRQ_BASE + i, + &emma2rh_gpio_irq_controller, + handle_edge_irq, "edge"); } static struct irqaction irq_cascade = { From skuribay@ruby.dti.ne.jp Sat Mar 21 13:08:14 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 21 Mar 2009 13:08:21 +0000 (GMT) Received: from smtp14.dti.ne.jp ([202.216.231.189]:1920 "EHLO smtp14.dti.ne.jp") by ftp.linux-mips.org with ESMTP id S21366774AbZCUNIO (ORCPT ); Sat, 21 Mar 2009 13:08:14 +0000 Received: from [192.168.1.5] (PPPax1767.tokyo-ip.dti.ne.jp [210.159.179.17]) by smtp14.dti.ne.jp (3.11s) with ESMTP AUTH id n2LD8CXr018616;Sat, 21 Mar 2009 22:08:12 +0900 (JST) Message-ID: <49C4E6BC.8040902@ruby.dti.ne.jp> Date: Sat, 21 Mar 2009 22:08:12 +0900 From: Shinya Kuribayashi User-Agent: Thunderbird 2.0.0.21 (X11/20090318) MIME-Version: 1.0 To: ralf@linux-mips.org, linux-mips@linux-mips.org Subject: [PATCH] MIPS: EMMA2RH: Use set_irq_chip_and_handler_name References: <49C4E5D5.4070408@ruby.dti.ne.jp> <49C4E646.7010309@ruby.dti.ne.jp> In-Reply-To: <49C4E646.7010309@ruby.dti.ne.jp> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22117 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: skuribay@ruby.dti.ne.jp Precedence: bulk X-list: linux-mips Content-Length: 1280 Lines: 38 Fix two remaining set_irq_chip_and_handler() users which are encourated to migrate to set_irq_chip_and_handler_name(). Signed-off-by: Shinya Kuribayashi --- arch/mips/emma/markeins/irq.c | 12 ++++++------ 1 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/mips/emma/markeins/irq.c b/arch/mips/emma/markeins/irq.c index 1e6457c..2bbc41a 100644 --- a/arch/mips/emma/markeins/irq.c +++ b/arch/mips/emma/markeins/irq.c @@ -80,9 +80,9 @@ void emma2rh_irq_init(void) u32 i; for (i = 0; i < NUM_EMMA2RH_IRQ; i++) - set_irq_chip_and_handler(EMMA2RH_IRQ_BASE + i, - &emma2rh_irq_controller, - handle_level_irq); + set_irq_chip_and_handler_name(EMMA2RH_IRQ_BASE + i, + &emma2rh_irq_controller, + handle_level_irq, "level"); } static void emma2rh_sw_irq_enable(unsigned int irq) @@ -120,9 +120,9 @@ void emma2rh_sw_irq_init(void) u32 i; for (i = 0; i < NUM_EMMA2RH_IRQ_SW; i++) - set_irq_chip_and_handler(EMMA2RH_SW_IRQ_BASE + i, - &emma2rh_sw_irq_controller, - handle_level_irq); + set_irq_chip_and_handler_name(EMMA2RH_SW_IRQ_BASE + i, + &emma2rh_sw_irq_controller, + handle_level_irq, "level"); } static void emma2rh_gpio_irq_enable(unsigned int irq) From skuribay@ruby.dti.ne.jp Sat Mar 21 13:11:52 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 21 Mar 2009 13:11:58 +0000 (GMT) Received: from smtp14.dti.ne.jp ([202.216.231.189]:3968 "EHLO smtp14.dti.ne.jp") by ftp.linux-mips.org with ESMTP id S21369751AbZCUNLw (ORCPT ); Sat, 21 Mar 2009 13:11:52 +0000 Received: from [192.168.1.5] (PPPax1767.tokyo-ip.dti.ne.jp [210.159.179.17]) by smtp14.dti.ne.jp (3.11s) with ESMTP AUTH id n2LDBnwY018643;Sat, 21 Mar 2009 22:11:50 +0900 (JST) Message-ID: <49C4E795.4070400@ruby.dti.ne.jp> Date: Sat, 21 Mar 2009 22:11:49 +0900 From: Shinya Kuribayashi User-Agent: Thunderbird 2.0.0.21 (X11/20090318) MIME-Version: 1.0 To: ralf@linux-mips.org, linux-mips@linux-mips.org Subject: [PATCH] MIPS: EMMA2RH: Set UART mapbase References: <49C4E5D5.4070408@ruby.dti.ne.jp> <49C4E646.7010309@ruby.dti.ne.jp> <49C4E6BC.8040902@ruby.dti.ne.jp> In-Reply-To: <49C4E6BC.8040902@ruby.dti.ne.jp> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22118 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: skuribay@ruby.dti.ne.jp Precedence: bulk X-list: linux-mips Content-Length: 1334 Lines: 34 Signed-off-by: Shinya Kuribayashi --- arch/mips/emma/markeins/platform.c | 3 +++ 1 files changed, 3 insertions(+), 0 deletions(-) diff --git a/arch/mips/emma/markeins/platform.c b/arch/mips/emma/markeins/platform.c index d5f47e4..80ae12e 100644 --- a/arch/mips/emma/markeins/platform.c +++ b/arch/mips/emma/markeins/platform.c @@ -110,6 +110,7 @@ struct platform_device i2c_emma_devices[] = { static struct plat_serial8250_port platform_serial_ports[] = { [0] = { .membase= (void __iomem*)KSEG1ADDR(EMMA2RH_PFUR0_BASE + 3), + .mapbase = EMMA2RH_PFUR0_BASE + 3, .irq = EMMA2RH_IRQ_PFUR0, .uartclk = EMMA2RH_SERIAL_CLOCK, .regshift = 4, @@ -117,6 +118,7 @@ static struct plat_serial8250_port platform_serial_ports[] = { .flags = EMMA2RH_SERIAL_FLAGS, }, [1] = { .membase = (void __iomem*)KSEG1ADDR(EMMA2RH_PFUR1_BASE + 3), + .mapbase = EMMA2RH_PFUR1_BASE + 3, .irq = EMMA2RH_IRQ_PFUR1, .uartclk = EMMA2RH_SERIAL_CLOCK, .regshift = 4, @@ -124,6 +126,7 @@ static struct plat_serial8250_port platform_serial_ports[] = { .flags = EMMA2RH_SERIAL_FLAGS, }, [2] = { .membase = (void __iomem*)KSEG1ADDR(EMMA2RH_PFUR2_BASE + 3), + .mapbase = EMMA2RH_PFUR2_BASE + 3, .irq = EMMA2RH_IRQ_PFUR2, .uartclk = EMMA2RH_SERIAL_CLOCK, .regshift = 4, From dmitri.vorobiev@movial.com Sun Mar 22 22:12:43 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 22 Mar 2009 22:12:50 +0000 (GMT) Received: from gw01.mail.saunalahti.fi ([195.197.172.115]:45974 "EHLO gw01.mail.saunalahti.fi") by ftp.linux-mips.org with ESMTP id S21370127AbZCVWMj (ORCPT ); Sun, 22 Mar 2009 22:12:39 +0000 Received: from localhost.localdomain (a88-114-245-69.elisa-laajakaista.fi [88.114.245.69]) by gw01.mail.saunalahti.fi (Postfix) with ESMTP id 29C8F151410; Mon, 23 Mar 2009 00:12:34 +0200 (EET) From: Dmitri Vorobiev To: ralf@linux-mips.org, linux-mips@linux-mips.org Subject: [PATCH 0/3] A few MIPS cleanups Date: Mon, 23 Mar 2009 00:12:26 +0200 Message-Id: <1237759949-8223-1-git-send-email-dmitri.vorobiev@movial.com> X-Mailer: git-send-email 1.5.6.3 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22119 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dmitri.vorobiev@movial.com Precedence: bulk X-list: linux-mips Content-Length: 79 Lines: 6 Hi Ralf, A couple of cleanup patches follow. Please consider. Thanks, Dmitri From dmitri.vorobiev@movial.com Sun Mar 22 22:13:07 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 22 Mar 2009 22:13:14 +0000 (GMT) Received: from gw01.mail.saunalahti.fi ([195.197.172.115]:46230 "EHLO gw01.mail.saunalahti.fi") by ftp.linux-mips.org with ESMTP id S21370128AbZCVWMl (ORCPT ); Sun, 22 Mar 2009 22:12:41 +0000 Received: from localhost.localdomain (a88-114-245-69.elisa-laajakaista.fi [88.114.245.69]) by gw01.mail.saunalahti.fi (Postfix) with ESMTP id 4BE7C1514B2; Mon, 23 Mar 2009 00:12:38 +0200 (EET) From: Dmitri Vorobiev To: ralf@linux-mips.org, linux-mips@linux-mips.org Cc: Dmitri Vorobiev Subject: [PATCH 1/3] [MIPS] Malta: make a needlessly global integer variable static Date: Mon, 23 Mar 2009 00:12:27 +0200 Message-Id: <1237759949-8223-2-git-send-email-dmitri.vorobiev@movial.com> X-Mailer: git-send-email 1.5.6.3 In-Reply-To: <1237759949-8223-1-git-send-email-dmitri.vorobiev@movial.com> References: <1237759949-8223-1-git-send-email-dmitri.vorobiev@movial.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22120 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dmitri.vorobiev@movial.com Precedence: bulk X-list: linux-mips Content-Length: 1314 Lines: 40 The variable `mips_revision_corid' is needlessly defined global in arch/mips/mti-malta/malta-init.c, and this patch makes it static. Build-tested with malta_defconfig. Signed-off-by: Dmitri Vorobiev --- arch/mips/include/asm/mips-boards/generic.h | 2 -- arch/mips/mti-malta/malta-init.c | 2 +- 2 files changed, 1 insertions(+), 3 deletions(-) diff --git a/arch/mips/include/asm/mips-boards/generic.h b/arch/mips/include/asm/mips-boards/generic.h index 7f0b034..c0da1a8 100644 --- a/arch/mips/include/asm/mips-boards/generic.h +++ b/arch/mips/include/asm/mips-boards/generic.h @@ -71,8 +71,6 @@ #define MIPS_REVISION_CORID (((*(volatile u32 *)ioremap(MIPS_REVISION_REG, 4)) >> 10) & 0x3f) -extern int mips_revision_corid; - #define MIPS_REVISION_SCON_OTHER 0 #define MIPS_REVISION_SCON_SOCITSC 1 #define MIPS_REVISION_SCON_SOCITSCP 2 diff --git a/arch/mips/mti-malta/malta-init.c b/arch/mips/mti-malta/malta-init.c index 4832af2..475038a 100644 --- a/arch/mips/mti-malta/malta-init.c +++ b/arch/mips/mti-malta/malta-init.c @@ -48,7 +48,7 @@ int *_prom_argv, *_prom_envp; int init_debug = 0; -int mips_revision_corid; +static int mips_revision_corid; int mips_revision_sconid; /* Bonito64 system controller register base. */ -- 1.5.6.3 From dmitri.vorobiev@movial.com Sun Mar 22 22:13:32 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 22 Mar 2009 22:13:38 +0000 (GMT) Received: from gw01.mail.saunalahti.fi ([195.197.172.115]:46998 "EHLO gw01.mail.saunalahti.fi") by ftp.linux-mips.org with ESMTP id S21370132AbZCVWMo (ORCPT ); Sun, 22 Mar 2009 22:12:44 +0000 Received: from localhost.localdomain (a88-114-245-69.elisa-laajakaista.fi [88.114.245.69]) by gw01.mail.saunalahti.fi (Postfix) with ESMTP id 696C4151410; Mon, 23 Mar 2009 00:12:41 +0200 (EET) From: Dmitri Vorobiev To: ralf@linux-mips.org, linux-mips@linux-mips.org Cc: Dmitri Vorobiev Subject: [PATCH 2/3] [MIPS] Fix global namespace pollution in arch/mips/kernel/smp-up.c Date: Mon, 23 Mar 2009 00:12:28 +0200 Message-Id: <1237759949-8223-3-git-send-email-dmitri.vorobiev@movial.com> X-Mailer: git-send-email 1.5.6.3 In-Reply-To: <1237759949-8223-2-git-send-email-dmitri.vorobiev@movial.com> References: <1237759949-8223-1-git-send-email-dmitri.vorobiev@movial.com> <1237759949-8223-2-git-send-email-dmitri.vorobiev@movial.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22121 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dmitri.vorobiev@movial.com Precedence: bulk X-list: linux-mips Content-Length: 1743 Lines: 74 The following symbols in arch/mips/kernel/smp-up.c are needlessly defined global: up_send_ipi_single() up_init_secondary() up_smp_finish() up_cpus_done() up_boot_secondary() up_smp_setup() up_prepare_cpus() This patch makes the symbols static. Build-tested using malta_defconfig. Signed-off-by: Dmitri Vorobiev --- arch/mips/kernel/smp-up.c | 14 +++++++------- 1 files changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/mips/kernel/smp-up.c b/arch/mips/kernel/smp-up.c index ead6c30..878e373 100644 --- a/arch/mips/kernel/smp-up.c +++ b/arch/mips/kernel/smp-up.c @@ -13,7 +13,7 @@ /* * Send inter-processor interrupt */ -void up_send_ipi_single(int cpu, unsigned int action) +static void up_send_ipi_single(int cpu, unsigned int action) { panic(KERN_ERR "%s called", __func__); } @@ -27,31 +27,31 @@ static inline void up_send_ipi_mask(cpumask_t mask, unsigned int action) * After we've done initial boot, this function is called to allow the * board code to clean up state, if needed */ -void __cpuinit up_init_secondary(void) +static void __cpuinit up_init_secondary(void) { } -void __cpuinit up_smp_finish(void) +static void __cpuinit up_smp_finish(void) { } /* Hook for after all CPUs are online */ -void up_cpus_done(void) +static void up_cpus_done(void) { } /* * Firmware CPU startup hook */ -void __cpuinit up_boot_secondary(int cpu, struct task_struct *idle) +static void __cpuinit up_boot_secondary(int cpu, struct task_struct *idle) { } -void __init up_smp_setup(void) +static void __init up_smp_setup(void) { } -void __init up_prepare_cpus(unsigned int max_cpus) +static void __init up_prepare_cpus(unsigned int max_cpus) { } -- 1.5.6.3 From dmitri.vorobiev@movial.com Sun Mar 22 22:13:55 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 22 Mar 2009 22:14:01 +0000 (GMT) Received: from gw01.mail.saunalahti.fi ([195.197.172.115]:47510 "EHLO gw01.mail.saunalahti.fi") by ftp.linux-mips.org with ESMTP id S21370133AbZCVWMr (ORCPT ); Sun, 22 Mar 2009 22:12:47 +0000 Received: from localhost.localdomain (a88-114-245-69.elisa-laajakaista.fi [88.114.245.69]) by gw01.mail.saunalahti.fi (Postfix) with ESMTP id 89486151410; Mon, 23 Mar 2009 00:12:44 +0200 (EET) From: Dmitri Vorobiev To: ralf@linux-mips.org, linux-mips@linux-mips.org Cc: Dmitri Vorobiev Subject: [PATCH 3/3] [MIPS] Make a needlessly global symbol static in arch/mips/kernel/smp.c Date: Mon, 23 Mar 2009 00:12:29 +0200 Message-Id: <1237759949-8223-4-git-send-email-dmitri.vorobiev@movial.com> X-Mailer: git-send-email 1.5.6.3 In-Reply-To: <1237759949-8223-3-git-send-email-dmitri.vorobiev@movial.com> References: <1237759949-8223-1-git-send-email-dmitri.vorobiev@movial.com> <1237759949-8223-2-git-send-email-dmitri.vorobiev@movial.com> <1237759949-8223-3-git-send-email-dmitri.vorobiev@movial.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22122 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dmitri.vorobiev@movial.com Precedence: bulk X-list: linux-mips Content-Length: 801 Lines: 26 The variable cpu_callin_map is needlessly defined global, so let's make it static now. Build-tested using malta_defconfig. Signed-off-by: Dmitri Vorobiev --- arch/mips/kernel/smp.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/mips/kernel/smp.c b/arch/mips/kernel/smp.c index 3da9470..c937506 100644 --- a/arch/mips/kernel/smp.c +++ b/arch/mips/kernel/smp.c @@ -44,7 +44,7 @@ #include #endif /* CONFIG_MIPS_MT_SMTC */ -volatile cpumask_t cpu_callin_map; /* Bitmask of started secondaries */ +static volatile cpumask_t cpu_callin_map; /* Bitmask of started secondaries */ int __cpu_number_map[NR_CPUS]; /* Map physical to logical */ int __cpu_logical_map[NR_CPUS]; /* Map logical to physical */ -- 1.5.6.3 From nils.faerber@kernelconcepts.de Mon Mar 23 01:30:59 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 23 Mar 2009 01:31:05 +0000 (GMT) Received: from mail.kernelconcepts.de ([212.60.202.196]:39661 "EHLO mail.kernelconcepts.de") by ftp.linux-mips.org with ESMTP id S21369218AbZCWBa5 (ORCPT ); Mon, 23 Mar 2009 01:30:57 +0000 Received: from [78.49.132.203] (helo=[192.168.178.35]) by mail.kernelconcepts.de with esmtpsa (TLS-1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.63) (envelope-from ) id 1LlZHf-0003pl-9v; Mon, 23 Mar 2009 02:48:59 +0100 Message-ID: <49C6E64D.6090006@kernelconcepts.de> Date: Mon, 23 Mar 2009 02:30:53 +0100 From: Nils Faerber User-Agent: Thunderbird 2.0.0.19 (X11/20090105) MIME-Version: 1.0 To: "Kevin D. Kissell" CC: linux-mips@linux-mips.org Subject: Re: Need help iterpreting reg-dump References: <49C42A9B.5050103@kernelconcepts.de> <49C4C36B.7010606@paralogos.com> In-Reply-To: <49C4C36B.7010606@paralogos.com> X-Enigmail-Version: 0.95.0 Content-Type: text/plain; charset=ISO-8859-15 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22123 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: nils.faerber@kernelconcepts.de Precedence: bulk X-list: linux-mips Content-Length: 13773 Lines: 335 Hallo Kevin! First of all many thanks for your thoughts and especially your explanations of some of the kernel's internals! Kevin D. Kissell schrieb: [...] > So, while I can't prove anything conclusive based on the dump below, it > suggests that the processor took a CP1 exception on an instruction that > was emulated as an FP branch, so that the branch delay slot instruction > had to be executed off the top of the stack in the delay slot emulation > code, but that something was screwed up so that the call to > do_dsemulret() in do_ade() returned zero, so the unaligned access > handling threw a signal instead of ignoring it. > > The diagnostic code probably hasn't been armed in years, but if you > #define DSEMUL_TRACE when the code in arch/mips/math-emu is built (or > just hack it into dsemul.h or dsemul.c), it would help confirm or deny > the hypothesis. I have added some more debug outputs to the code. I can confirm now defnitely that the dsemul path is run and the the SIGILL is the result of a dsemul_ret returning 0, also see the below extended dumps. The strange thing is the fault does not always occur and if it occurs it does not always happen in the same place of the application. So I assume that this is not a problem of the application itself deliberatley executing a certain instruction but rather a side effect of something different - like wrong caches. On the other hand again it is strange that only the dsemul path seems to be triggered. Could it be that the exception that is used for math emulation can also have other causes in different CPU implementations? The JZ4730 has some DSP alike SIMD instructions... but then again why can't it be traced to a single instruction inside the application (i.e. rather seems to happen randomly)? > Regards, > Kevin K. Cheers nils faerber [42949414.060000] do_dsemulret: bad magics, insn=0x8c830004 [42949414.080000] do_dsemulret: cannot access emuframe [42949414.080000] Cpu 0 [42949414.090000] $ 0 : 00000000 10000400 00000000 00000000 [42949414.090000] $ 4 : 8033e528 80000000 00000024 0041469c [42949414.100000] $ 8 : 10000401 1000001e 00000003 00000022 [42949414.100000] $12 : 2ac9a200 2aca0000 ffffffff 00401820 [42949414.110000] $16 : 14400022 87d45f30 ffffffff 00414660 [42949414.110000] $20 : 00000000 00000000 00000000 2ac0fa18 [42949414.120000] $24 : 00000047 00000000 [42949414.130000] $28 : 87d44000 87d45ee8 00000000 80020bf0 [42949414.130000] Hi : 0000002c [42949414.130000] Lo : 0003aac9 [42949414.140000] epc : 80034098 do_dsemulret+0x3c/0xf4 Not tainted [42949414.140000] ra : 80020bf0 do_ade+0x20/0x3c0 [42949414.150000] Status: 10000403 KERNEL EXL IE [42949414.150000] Cause : 10800010 [42949414.160000] BadVA : 14400026 [42949414.160000] PrId : 02d0024f (Ingenic JZRISC) [42949414.160000] Modules linked in: [42949414.170000] Process keylaunch (pid: 1222, threadinfo=87d44000, task=87d6e1 78) [42949414.180000] Stack : 87d6e178 802dca50 8c830004 30620002 87d45f30 0041bbe1 80020bf0 00414660 [42949414.180000] 00414660 0041bbe1 ffffffff 00414660 00414660 0041bbe1 ffffffff 00414660 [42949414.190000] 80018fa0 80019120 004d8474 004d843c 004d844c 004d8a02 ffffffff 00000000 [42949414.200000] 00000000 10000400 2ae66754 00418690 0041bbd9 0041bbe1 00000024 0041469c [42949414.210000] 00000023 00414690 00000003 00000022 2ac9a200 2aca0000 ffffffff 00401820 [42949414.220000] ... [42949414.220000] Call Trace: [42949414.230000] [<80034098>] do_dsemulret+0x3c/0xf4 [42949414.230000] [<80020bf0>] do_ade+0x20/0x3c0 [42949414.230000] [<80018fa0>] ret_from_exception+0x0/0x24 [42949414.240000] [42949414.240000] [42949414.240000] Code: 1460002b 2484e528 00601021 <8e060004> 8e070008 3c0480 34 00431025 2484e550 10400013 [42949414.290000] do_dsemulret: cannot access emuframe [42949414.290000] Cpu 0 [42949414.300000] $ 0 : 00000000 10000400 fffffff2 00000000 [42949414.300000] $ 4 : 8033e528 80000000 00000024 0041469c [42949414.310000] $ 8 : 10000401 1000001e 00000003 00000022 [42949414.310000] $12 : 2ac9a200 2aca0000 ffffffff 00401820 [42949414.320000] $16 : 14400022 87d45f30 ffffffff 00414660 [42949414.320000] $20 : 00000000 00000000 00000000 2ac0fa18 [42949414.330000] $24 : 00000047 00000000 [42949414.330000] $28 : 87d44000 87d45ee8 00000000 80020bf0 [42949414.340000] Hi : 0000002c [42949414.340000] Lo : 0003aac9 [42949414.350000] epc : 8003409c do_dsemulret+0x40/0xf4 Not tainted [42949414.350000] ra : 80020bf0 do_ade+0x20/0x3c0 [42949414.360000] Status: 10000403 KERNEL EXL IE [42949414.360000] Cause : 00800010 [42949414.370000] BadVA : 1440002a [42949414.370000] PrId : 02d0024f (Ingenic JZRISC) [42949414.370000] Modules linked in: [42949414.380000] Process keylaunch (pid: 1222, threadinfo=87d44000, task=87d6e1 78) [42949414.380000] Stack : 87d6e178 802dca50 8c830004 30620002 87d45f30 0041bbe1 80020bf0 00414660 [42949414.390000] 00414660 0041bbe1 ffffffff 00414660 00414660 0041bbe1 ffffffff 00414660 [42949414.400000] 80018fa0 80019120 004d8474 004d843c 004d844c 004d8a02 ffffffff 00000000 [42949414.410000] 00000000 10000400 2ae66754 00418690 0041bbd9 0041bbe1 00000024 0041469c [42949414.420000] 00000023 00414690 00000003 00000022 2ac9a200 2aca0000 ffffffff 00401820 [42949414.430000] ... [42949414.430000] Call Trace: [42949414.430000] [<8003409c>] do_dsemulret+0x40/0xf4 [42949414.440000] [<80020bf0>] do_ade+0x20/0x3c0 [42949414.440000] [<80018fa0>] ret_from_exception+0x0/0x24 [42949414.450000] [42949414.450000] [42949414.450000] Code: 2484e528 00601021 8e060004 <8e070008> 3c048034 004310 25 2484e550 10400013 00c02821 [42949414.550000] do_dsemulret: bad magics, insn=0x00000024 [42949414.560000] do_dsemulret: cannot access emuframe [42949414.560000] Cpu 0 [42949414.560000] $ 0 : 00000000 10000400 00000000 803bf8d0 [42949414.570000] $ 4 : 8037c3d0 87d9fefc 00000005 00000005 [42949414.570000] $ 8 : ebd8a1cf 00000005 feced300 ffffffff [42949414.580000] $12 : ec71384f 00000005 ffffffff 803bfd88 [42949414.590000] $16 : 14400022 87d45f30 ffffffff 00414660 [42949414.590000] $20 : 00000000 00000000 00000000 2ac0fa18 [42949414.600000] $24 : 00000001 803bfda8 [42949414.600000] $28 : 87d44000 87d45ee8 00000000 800340bc [42949414.610000] Hi : 00989643 [42949414.610000] Lo : d5905180 [42949414.610000] epc : 800340d4 do_dsemulret+0x78/0xf4 Not tainted [42949414.620000] ra : 800340bc do_dsemulret+0x60/0xf4 [42949414.630000] Status: 10000403 KERNEL EXL IE [42949414.630000] Cause : 20800010 [42949414.630000] BadVA : 1440002e [42949414.640000] PrId : 02d0024f (Ingenic JZRISC) [42949414.640000] Modules linked in: [42949414.650000] Process keylaunch (pid: 1222, threadinfo=87d44000, task=87d6e1 78) [42949414.650000] Stack : 87d6e178 00000024 00000024 0041469c 87d45f30 0041bbe1 80020bf0 00414660 [42949414.660000] 00414660 0041bbe1 ffffffff 00414660 00414660 0041bbe1 ffffffff 00414660 [42949414.670000] 80018fa0 80019120 004d8474 004d843c 004d844c 004d8a02 ffffffff 00000000 [42949414.680000] 00000000 10000400 2ae66754 00418690 0041bbd9 0041bbe1 00000024 0041469c [42949414.690000] 00000023 00414690 00000003 00000022 2ac9a200 2aca0000 ffffffff 00401820 [42949414.700000] ... [42949414.700000] Call Trace: [42949414.700000] [<800340d4>] do_dsemulret+0x78/0xf4 [42949414.710000] [<80020bf0>] do_ade+0x20/0x3c0 [42949414.710000] [<80018fa0>] ret_from_exception+0x0/0x24 [42949414.720000] [42949414.720000] [42949414.720000] Code: 24420001 ac620014 00001021 <8e03000c> 14400010 240400 0a ae2300ac 24020001 8fbf0018 [42949416.460000] do_dsemulret: bad magics, insn=0x8c830004 [42949416.460000] do_dsemulret: cannot access emuframe [42949416.470000] Cpu 0 [42949416.470000] $ 0 : 00000000 10000400 00000000 00000000 [42949416.480000] $ 4 : 8033e528 80000000 00425c90 00000019 [42949416.480000] $ 8 : 10000401 1000001e 36384658 72617453 [42949416.490000] $12 : 87d744c0 00000000 87d744c0 00000000 [42949416.490000] $16 : 14400022 87b0bf30 00414008 0000003f [42949416.500000] $20 : 00425c90 00400000 00400000 00000000 [42949416.500000] $24 : 00000003 00000000 [42949416.510000] $28 : 87b0a000 87b0bee8 2ae64858 80020bf0 [42949416.520000] Hi : 307e68e8 [42949416.520000] Lo : e1cb4540 [42949416.520000] epc : 80034098 do_dsemulret+0x3c/0xf4 Not tainted [42949416.530000] ra : 80020bf0 do_ade+0x20/0x3c0 [42949416.530000] Status: 10000403 KERNEL EXL IE [42949416.540000] Cause : 10800010 [42949416.540000] BadVA : 14400026 [42949416.540000] PrId : 02d0024f (Ingenic JZRISC) [42949416.550000] Modules linked in: [42949416.550000] Process keylaunch (pid: 1274, threadinfo=87b0a000, task=87daed f8) [42949416.560000] Stack : 87daedf8 802dca50 8c830004 30620002 87b0bf30 0041bbd9 80020bf0 0000003f [42949416.570000] 00425c94 0041bbd9 00414008 0000003f 00425c94 0041bbd9 00414008 0000003f [42949416.580000] 80018fa0 80019120 004d928c 004d8e44 004d9254 004daa9c ffffffff 00000000 [42949416.590000] 00000000 10000400 2ae66754 00000001 0041bbd1 00000001 00425c90 00000019 [42949416.600000] ffffffff ffffffff 36384658 72617453 87d744c0 00000000 87d744c0 00000000 [42949416.600000] ... [42949416.610000] Call Trace: [42949416.610000] [<80034098>] do_dsemulret+0x3c/0xf4 [42949416.610000] [<80020bf0>] do_ade+0x20/0x3c0 [42949416.620000] [<80018fa0>] ret_from_exception+0x0/0x24 [42949416.620000] [42949416.630000] [42949416.630000] Code: 1460002b 2484e528 00601021 <8e060004> 8e070008 3c0480 34 00431025 2484e550 10400013 [42949417.210000] do_dsemulret: bad magics, insn=0xaca20000 [42949417.970000] do_dsemulret: cannot access emuframe [42949417.970000] Cpu 0 [42949417.980000] $ 0 : 00000000 10000400 fffffff2 00000000 [42949417.980000] $ 4 : 8033e528 80000000 00425c90 00000019 [42949417.990000] $ 8 : 10000401 1000001e 36384658 72617453 [42949417.990000] $12 : 87d744c0 00000000 87d744c0 00000000 [42949418.000000] $16 : 14400022 87b0bf30 00414008 0000003f [42949418.000000] $20 : 00425c90 00400000 00400000 00000000 [42949418.010000] $24 : 00000003 00000000 [42949418.020000] $28 : 87b0a000 87b0bee8 2ae64858 80020bf0 [42949418.020000] Hi : 307e68e8 [42949418.020000] Lo : e1cb4540 [42949418.030000] epc : 8003409c do_dsemulret+0x40/0xf4 Not tainted [42949418.030000] ra : 80020bf0 do_ade+0x20/0x3c0 [42949418.040000] Status: 10000403 KERNEL EXL IE [42949418.040000] Cause : 00800010 [42949418.050000] BadVA : 1440002a [42949418.050000] PrId : 02d0024f (Ingenic JZRISC) [42949418.060000] Modules linked in: [42949418.060000] Process keylaunch (pid: 1274, threadinfo=87b0a000, task=87daed f8) [42949418.070000] Stack : 87daedf8 802dca50 8c830004 30620002 87b0bf30 0041bbd9 80020bf0 0000003f [42949418.070000] 00425c94 0041bbd9 00414008 0000003f 00425c94 0041bbd9 00414008 0000003f [42949418.080000] 80018fa0 80019120 004d928c 004d8e44 004d9254 004daa9c ffffffff 00000000 [42949418.090000] 00000000 10000400 2ae66754 00000001 0041bbd1 00000001 00425c90 00000019 [42949418.100000] ffffffff ffffffff 36384658 72617453 87d744c0 00000000 87d744c0 00000000 [42949418.110000] ... [42949418.110000] Call Trace: [42949418.120000] [<8003409c>] do_dsemulret+0x40/0xf4 [42949418.120000] [<80020bf0>] do_ade+0x20/0x3c0 [42949418.120000] [<80018fa0>] ret_from_exception+0x0/0x24 [42949418.130000] [42949418.130000] [42949418.130000] Code: 2484e528 00601021 8e060004 <8e070008> 3c048034 004310 25 2484e550 10400013 00c02821 [42949419.210000] do_dsemulret: bad magics, insn=0x00425c90 [42949419.210000] do_dsemulret: cannot access emuframe [42949419.220000] Cpu 0 [42949419.220000] $ 0 : 00000000 10000400 00000000 803bf8d0 [42949419.220000] $ 4 : 8037c3d0 87d9fefc 00000006 00000000 [42949419.230000] $ 8 : 3c317acd 00000006 feced300 ffffffff [42949419.230000] $12 : 3cca114d 00000006 ffffffff 803bfd88 [42949419.240000] $16 : 14400022 87b0bf30 00414008 0000003f [42949419.250000] $20 : 00425c90 00400000 00400000 00000000 [42949419.250000] $24 : 00000001 803bfda8 [42949419.260000] $28 : 87b0a000 87b0bee8 2ae64858 800340bc [42949419.260000] Hi : 00989644 [42949419.270000] Lo : eb524680 [42949419.270000] epc : 800340d4 do_dsemulret+0x78/0xf4 Not tainted [42949419.280000] ra : 800340bc do_dsemulret+0x60/0xf4 [42949419.280000] Status: 10000403 KERNEL EXL IE [42949419.290000] Cause : 20800010 [42949419.290000] BadVA : 1440002e [42949419.290000] PrId : 02d0024f (Ingenic JZRISC) [42949419.300000] Modules linked in: [42949419.300000] Process keylaunch (pid: 1274, threadinfo=87b0a000, task=87daed f8) [42949419.310000] Stack : 87daedf8 00425c90 00425c90 00000019 87b0bf30 0041bbd9 80020bf0 0000003f [42949419.320000] 00425c94 0041bbd9 00414008 0000003f 00425c94 0041bbd9 00414008 0000003f [42949419.320000] 80018fa0 80019120 004d928c 004d8e44 004d9254 004daa9c ffffffff 00000000 [42949419.330000] 00000000 10000400 2ae66754 00000001 0041bbd1 00000001 00425c90 00000019 [42949419.340000] ffffffff ffffffff 36384658 72617453 87d744c0 00000000 87d744c0 00000000 [42949419.350000] ... [42949419.350000] Call Trace: [42949419.360000] [<800340d4>] do_dsemulret+0x78/0xf4 [42949419.360000] [<80020bf0>] do_ade+0x20/0x3c0 [42949419.370000] [<80018fa0>] ret_from_exception+0x0/0x24 [42949419.370000] [42949419.370000] [42949419.370000] Code: 24420001 ac620014 00001021 <8e03000c> 14400010 240400 0a ae2300ac 24020001 8fbf0018 -- kernel concepts GbR Tel: +49-271-771091-12 Sieghuetter Hauptweg 48 Fax: +49-271-771091-19 D-57072 Siegen Mob: +49-176-21024535 -- From nietzsche@lysator.liu.se Mon Mar 23 01:46:32 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 23 Mar 2009 01:46:38 +0000 (GMT) Received: from mail.lysator.liu.se ([130.236.254.3]:50051 "EHLO mail.lysator.liu.se") by ftp.linux-mips.org with ESMTP id S21366687AbZCWBqc (ORCPT ); Mon, 23 Mar 2009 01:46:32 +0000 Received: from mail.lysator.liu.se (localhost [127.0.0.1]) by mail.lysator.liu.se (Postfix) with ESMTP id 33C0140022; Mon, 23 Mar 2009 02:46:23 +0100 (CET) Received: from [192.168.10.105] (c-30bde555.035-105-73746f38.cust.bredbandsbolaget.se [85.229.189.48]) (using TLSv1 with cipher AES128-SHA (128/128 bits)) (No client certificate requested) by mail.lysator.liu.se (Postfix) with ESMTP id 0483A40019; Mon, 23 Mar 2009 02:46:23 +0100 (CET) Cc: "Kevin D. Kissell" , linux-mips@linux-mips.org Message-Id: <6C19836D-11E7-4DC6-A387-33DE8911D887@lysator.liu.se> From: Markus Gothe To: Nils Faerber In-Reply-To: <49C6E64D.6090006@kernelconcepts.de> Content-Type: multipart/signed; protocol="application/pgp-signature"; micalg=pgp-sha1; boundary="Apple-Mail-4--379935989" Content-Transfer-Encoding: 7bit Mime-Version: 1.0 (Apple Message framework v930.3) Subject: Re: Need help iterpreting reg-dump Date: Mon, 23 Mar 2009 02:46:25 +0100 References: <49C42A9B.5050103@kernelconcepts.de> <49C4C36B.7010606@paralogos.com> <49C6E64D.6090006@kernelconcepts.de> X-Pgp-Agent: GPGMail 1.2.0 (v56) X-Mailer: Apple Mail (2.930.3) X-Virus-Scanned: ClamAV using ClamSMTP Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 22124 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: nietzsche@lysator.liu.se Precedence: bulk X-list: linux-mips Content-Length: 15353 Lines: 388 This is an OpenPGP/MIME signed message (RFC 2440 and 3156) --Apple-Mail-4--379935989 Content-Type: text/plain; charset=US-ASCII; format=flowed; delsp=yes Content-Transfer-Encoding: 7bit As you can se the Read-Address (ra) is within do_ade(..