From roel.kluin@gmail.com Fri Jan 2 15:09:59 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 02 Jan 2009 15:10:04 +0000 (GMT) Received: from nf-out-0910.google.com ([64.233.182.184]:26696 "EHLO nf-out-0910.google.com") by ftp.linux-mips.org with ESMTP id S22774218AbZABPJ7 (ORCPT ); Fri, 2 Jan 2009 15:09:59 +0000 Received: by nf-out-0910.google.com with SMTP id h3so872995nfh.14 for ; Fri, 02 Jan 2009 07:09:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:message-id:date:from :user-agent:mime-version:to:cc:subject:content-type :content-transfer-encoding; bh=dmnEB+GhJDgh6sg5w0OitCDzYTiMlF4/FRw0HkgpiYY=; b=KMESLaVQtX8Qg2RU6kZSYcnWFxIW2ysJEHk2IdKpaiFM2Y/odzb5xu3xJdIMytY9+c kiVtbHoGLdEq/6deap9pZyub2JhnpMlmqjmoYAEJPP5ENUSzbkfVbqlEg1j30kIdREpi uEnjJn83OX563KjdQ2QBEFNfYT7gCRYAtsHjo= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=message-id:date:from:user-agent:mime-version:to:cc:subject :content-type:content-transfer-encoding; b=uGvGsUj8IlYgw6v6uhX4Rxwm2CYZK/GwUqDCCjj690n5q9T5zZeA5VwBcqY7uCgZOf 6SZ2hrasBlmvNfz3Ab+06mry2DuqBnHFvDmPengzaxPXIja52UEcWWqENwXGZu5e8rN0 YKFE1Td7A8MnjRQWtkN902Rd+8IMCrLFB5PEs= Received: by 10.210.109.10 with SMTP id h10mr21005103ebc.10.1230908998270; Fri, 02 Jan 2009 07:09:58 -0800 (PST) Received: from ?192.168.1.148? (d133062.upc-d.chello.nl [213.46.133.62]) by mx.google.com with ESMTPS id f3sm31650819nfh.34.2009.01.02.07.09.57 (version=TLSv1/SSLv3 cipher=RC4-MD5); Fri, 02 Jan 2009 07:09:57 -0800 (PST) Message-ID: <495E2E47.6080605@gmail.com> Date: Fri, 02 Jan 2009 16:09:59 +0100 From: Roel Kluin User-Agent: Thunderbird 2.0.0.18 (X11/20081105) MIME-Version: 1.0 To: ralf@linux-mips.org CC: linux-mips@linux-mips.org Subject: [PATCH] MIPS: unsigned result is always greater than 0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21678 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: roel.kluin@gmail.com Precedence: bulk X-list: linux-mips Content-Length: 1037 Lines: 38 unsigned result is always greater than 0 Signed-off-by: Roel Kluin --- I cannot determine whether the same bug occurs as well in assembly. Also shouldn't similar checks occur in atomic64_sub_return and in atomic64_add_return for negative values of i? diff --git a/arch/mips/include/asm/atomic.h b/arch/mips/include/asm/atomic.h index 1232be3..3cd07a9 100644 --- a/arch/mips/include/asm/atomic.h +++ b/arch/mips/include/asm/atomic.h @@ -296,9 +296,10 @@ static __inline__ int atomic_sub_if_positive(int i, atomic_t * v) raw_local_irq_save(flags); result = v->counter; - result -= i; - if (result >= 0) + if (i <= result) { + result -= i; v->counter = result; + } raw_local_irq_restore(flags); } @@ -677,9 +678,10 @@ static __inline__ long atomic64_sub_if_positive(long i, atomic64_t * v) raw_local_irq_save(flags); result = v->counter; - result -= i; - if (result >= 0) + if (i >= result) { + result -= i; v->counter = result; + } raw_local_irq_restore(flags); } From James.Bottomley@HansenPartnership.com Fri Jan 2 16:25:22 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 02 Jan 2009 16:25:27 +0000 (GMT) Received: from accolon.hansenpartnership.com ([76.243.235.52]:44975 "EHLO accolon.hansenpartnership.com") by ftp.linux-mips.org with ESMTP id S24208572AbZABQZW (ORCPT ); Fri, 2 Jan 2009 16:25:22 +0000 Received: from localhost (localhost [127.0.0.1]) by accolon.hansenpartnership.com (Postfix) with ESMTP id 5D62A81D1; Fri, 2 Jan 2009 10:25:13 -0600 (CST) Received: from accolon.hansenpartnership.com ([127.0.0.1]) by localhost (redscar.int.hansenpartnership.com [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id x2-u+a9EgmIX; Fri, 2 Jan 2009 10:25:11 -0600 (CST) Received: from [153.66.150.222] (mulgrave-w.int.hansenpartnership.com [153.66.150.222]) by accolon.hansenpartnership.com (Postfix) with ESMTP id B83448131; Fri, 2 Jan 2009 10:25:10 -0600 (CST) Subject: Re: [PATCH] SCSI: fix the return type of the remove() method in sgiwd93.c From: James Bottomley To: Kay Sievers Cc: Vorobiev Dmitri , linux-scsi@vger.kernel.org, linux-mips@linux-mips.org, Greg KH In-Reply-To: <1228340496.6977.19.camel@nga> References: <1227140357-29921-1-git-send-email-dmitri.vorobiev@movial.fi> <1228327306.5551.36.camel@localhost.localdomain> <35647.88.114.226.209.1228329736.squirrel@webmail.movial.fi> <1228330800.5551.58.camel@localhost.localdomain> <1228337529.5551.72.camel@localhost.localdomain> <1228338142.5551.77.camel@localhost.localdomain> <1228340025.5551.87.camel@localhost.localdomain> <1228340496.6977.19.camel@nga> Content-Type: text/plain Date: Fri, 02 Jan 2009 10:25:10 -0600 Message-Id: <1230913510.3304.2.camel@localhost.localdomain> Mime-Version: 1.0 X-Mailer: Evolution 2.22.3.1 (2.22.3.1-1.fc9) Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21679 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: James.Bottomley@HansenPartnership.com Precedence: bulk X-list: linux-mips Content-Length: 28845 Lines: 737 On Wed, 2008-12-03 at 22:41 +0100, Kay Sievers wrote: > On Wed, 2008-12-03 at 15:33 -0600, James Bottomley wrote: > > Sure ... can you send a copy of it rather than me having to pull it out > > of your git tree. > > Sure, here is it. These are the files I could compile-test. I have > another patch, which touches the stuff I couldn't compile, I will send > that in the next days. > > Thanks, > Kay > > > From: Kay Sievers > Subject: SCSI: struct device - replace bus_id with dev_name(), dev_set_name() > > CC: James E.J. Bottomley > Signed-off-by: Kay Sievers > Signed-off-by: Greg Kroah-Hartman > --- > drivers/misc/enclosure.c | 8 +++--- > drivers/scsi/aic94xx/aic94xx_tmf.c | 2 - > drivers/scsi/hosts.c | 6 +---- > drivers/scsi/ipr.c | 2 - > drivers/scsi/ipr.h | 2 - > drivers/scsi/libsas/sas_discover.c | 2 - > drivers/scsi/libsas/sas_dump.c | 2 - > drivers/scsi/libsas/sas_port.c | 2 - > drivers/scsi/raid_class.c | 3 -- > drivers/scsi/scsi_debug.c | 4 +-- > drivers/scsi/scsi_ioctl.c | 3 +- > drivers/scsi/scsi_scan.c | 7 ++---- > drivers/scsi/scsi_sysfs.c | 12 ++++------ > drivers/scsi/scsi_transport_fc.c | 18 +++++++-------- > drivers/scsi/scsi_transport_iscsi.c | 11 +++------ > drivers/scsi/scsi_transport_sas.c | 42 ++++++++++++++++++------------------ > drivers/scsi/scsi_transport_srp.c | 2 - > drivers/scsi/sd.c | 2 - > drivers/scsi/ses.c | 2 - > 19 files changed, 63 insertions(+), 69 deletions(-) Sorry, dropped the ball a bit on this. I've attached the updated version: it copes with the legacy 20 character copy in the ioctl by brute force and also adds several other dev->bus_id -> dev_name(dev) conversions. James --- From: Kay Sievers Date: Wed, 3 Dec 2008 22:41:36 +0100 Subject: [SCSI] struct device - replace bus_id with dev_name(), dev_set_name() [jejb: limit ioctl to returning 20 characters to avoid overrun on long device names and add a few more conversions] Signed-off-by: Kay Sievers Signed-off-by: Greg Kroah-Hartman Signed-off-by: James Bottomley --- drivers/misc/enclosure.c | 8 +++--- drivers/scsi/NCR_D700.c | 2 +- drivers/scsi/advansys.c | 2 +- drivers/scsi/aic94xx/aic94xx_tmf.c | 2 +- drivers/scsi/hosts.c | 6 +--- drivers/scsi/ibmvscsi/ibmvfc.c | 4 +- drivers/scsi/ipr.c | 2 +- drivers/scsi/ipr.h | 2 +- drivers/scsi/lasi700.c | 3 +- drivers/scsi/libsas/sas_discover.c | 2 +- drivers/scsi/libsas/sas_dump.c | 2 +- drivers/scsi/libsas/sas_port.c | 2 +- drivers/scsi/raid_class.c | 3 +- drivers/scsi/scsi_debug.c | 4 +- drivers/scsi/scsi_ioctl.c | 9 ++++++- drivers/scsi/scsi_scan.c | 7 ++--- drivers/scsi/scsi_sysfs.c | 12 ++++----- drivers/scsi/scsi_transport_fc.c | 18 +++++++------- drivers/scsi/scsi_transport_iscsi.c | 11 +++----- drivers/scsi/scsi_transport_sas.c | 42 ++++++++++++++++++---------------- drivers/scsi/scsi_transport_srp.c | 2 +- drivers/scsi/sd.c | 2 +- drivers/scsi/ses.c | 2 +- drivers/scsi/sim710.c | 4 +- drivers/scsi/sni_53c710.c | 3 +- drivers/scsi/zalon.c | 4 +- 26 files changed, 79 insertions(+), 81 deletions(-) diff --git a/drivers/misc/enclosure.c b/drivers/misc/enclosure.c index 0736cff..3cf61ec 100644 --- a/drivers/misc/enclosure.c +++ b/drivers/misc/enclosure.c @@ -119,7 +119,7 @@ enclosure_register(struct device *dev, const char *name, int components, edev->edev.class = &enclosure_class; edev->edev.parent = get_device(dev); edev->cb = cb; - snprintf(edev->edev.bus_id, BUS_ID_SIZE, "%s", name); + dev_set_name(&edev->edev, name); err = device_register(&edev->edev); if (err) goto err; @@ -170,7 +170,7 @@ EXPORT_SYMBOL_GPL(enclosure_unregister); static void enclosure_link_name(struct enclosure_component *cdev, char *name) { strcpy(name, "enclosure_device:"); - strcat(name, cdev->cdev.bus_id); + strcat(name, dev_name(&cdev->cdev)); } static void enclosure_remove_links(struct enclosure_component *cdev) @@ -256,9 +256,9 @@ enclosure_component_register(struct enclosure_device *edev, cdev = &ecomp->cdev; cdev->parent = get_device(&edev->edev); if (name) - snprintf(cdev->bus_id, BUS_ID_SIZE, "%s", name); + dev_set_name(cdev, name); else - snprintf(cdev->bus_id, BUS_ID_SIZE, "%u", number); + dev_set_name(cdev, "%u", number); cdev->release = enclosure_component_release; cdev->groups = enclosure_groups; diff --git a/drivers/scsi/NCR_D700.c b/drivers/scsi/NCR_D700.c index 9e64b21..c889d84 100644 --- a/drivers/scsi/NCR_D700.c +++ b/drivers/scsi/NCR_D700.c @@ -318,7 +318,7 @@ NCR_D700_probe(struct device *dev) return -ENOMEM; p->dev = dev; - snprintf(p->name, sizeof(p->name), "D700(%s)", dev->bus_id); + snprintf(p->name, sizeof(p->name), "D700(%s)", dev_name(dev)); if (request_irq(irq, NCR_D700_intr, IRQF_SHARED, p->name, p)) { printk(KERN_ERR "D700: request_irq failed\n"); kfree(p); diff --git a/drivers/scsi/advansys.c b/drivers/scsi/advansys.c index 2f60272..7507d8b 100644 --- a/drivers/scsi/advansys.c +++ b/drivers/scsi/advansys.c @@ -2527,7 +2527,7 @@ static void asc_prt_scsi_host(struct Scsi_Host *s) { struct asc_board *boardp = shost_priv(s); - printk("Scsi_Host at addr 0x%p, device %s\n", s, boardp->dev->bus_id); + printk("Scsi_Host at addr 0x%p, device %s\n", s, dev_name(boardp->dev)); printk(" host_busy %u, host_no %d, last_reset %d,\n", s->host_busy, s->host_no, (unsigned)s->last_reset); diff --git a/drivers/scsi/aic94xx/aic94xx_tmf.c b/drivers/scsi/aic94xx/aic94xx_tmf.c index d4640ef..78eb86f 100644 --- a/drivers/scsi/aic94xx/aic94xx_tmf.c +++ b/drivers/scsi/aic94xx/aic94xx_tmf.c @@ -189,7 +189,7 @@ int asd_I_T_nexus_reset(struct domain_device *dev) asd_clear_nexus_I_T(dev, NEXUS_PHASE_PRE); /* send a hard reset */ ASD_DPRINTK("sending %s reset to %s\n", - reset_type ? "hard" : "soft", phy->dev.bus_id); + reset_type ? "hard" : "soft", dev_name(&phy->dev)); res = sas_phy_reset(phy, reset_type); if (res == TMF_RESP_FUNC_COMPLETE) { /* wait for the maximum settle time */ diff --git a/drivers/scsi/hosts.c b/drivers/scsi/hosts.c index 3fdbb13..aa670a1 100644 --- a/drivers/scsi/hosts.c +++ b/drivers/scsi/hosts.c @@ -388,8 +388,7 @@ struct Scsi_Host *scsi_host_alloc(struct scsi_host_template *sht, int privsize) shost->dma_boundary = 0xffffffff; device_initialize(&shost->shost_gendev); - snprintf(shost->shost_gendev.bus_id, BUS_ID_SIZE, "host%d", - shost->host_no); + dev_set_name(&shost->shost_gendev, "host%d", shost->host_no); #ifndef CONFIG_SYSFS_DEPRECATED shost->shost_gendev.bus = &scsi_bus_type; #endif @@ -398,8 +397,7 @@ struct Scsi_Host *scsi_host_alloc(struct scsi_host_template *sht, int privsize) device_initialize(&shost->shost_dev); shost->shost_dev.parent = &shost->shost_gendev; shost->shost_dev.class = &shost_class; - snprintf(shost->shost_dev.bus_id, BUS_ID_SIZE, "host%d", - shost->host_no); + dev_set_name(&shost->shost_dev, "host%d", shost->host_no); shost->shost_dev.groups = scsi_sysfs_shost_attr_groups; shost->ehandler = kthread_run(scsi_error_handler, shost, diff --git a/drivers/scsi/ibmvscsi/ibmvfc.c b/drivers/scsi/ibmvscsi/ibmvfc.c index 44f202f..253414e 100644 --- a/drivers/scsi/ibmvscsi/ibmvfc.c +++ b/drivers/scsi/ibmvscsi/ibmvfc.c @@ -1145,10 +1145,10 @@ static void ibmvfc_set_login_info(struct ibmvfc_host *vhost) login_info->async.len = vhost->async_crq.size * sizeof(*vhost->async_crq.msgs); strncpy(login_info->partition_name, vhost->partition_name, IBMVFC_MAX_NAME); strncpy(login_info->device_name, - vhost->host->shost_gendev.bus_id, IBMVFC_MAX_NAME); + dev_name(&vhost->host->shost_gendev), IBMVFC_MAX_NAME); location = of_get_property(of_node, "ibm,loc-code", NULL); - location = location ? location : vhost->dev->bus_id; + location = location ? location : dev_name(vhost->dev); strncpy(login_info->drc_name, location, IBMVFC_MAX_NAME); } diff --git a/drivers/scsi/ipr.c b/drivers/scsi/ipr.c index 0edfb1f..841f460 100644 --- a/drivers/scsi/ipr.c +++ b/drivers/scsi/ipr.c @@ -2184,7 +2184,7 @@ static void ipr_dump_location_data(struct ipr_ioa_cfg *ioa_cfg, sizeof(struct ipr_dump_entry_header); driver_dump->location_entry.hdr.data_type = IPR_DUMP_DATA_TYPE_ASCII; driver_dump->location_entry.hdr.id = IPR_DUMP_LOCATION_ID; - strcpy(driver_dump->location_entry.location, ioa_cfg->pdev->dev.bus_id); + strcpy(driver_dump->location_entry.location, dev_name(&ioa_cfg->pdev->dev)); driver_dump->hdr.num_entries++; } diff --git a/drivers/scsi/ipr.h b/drivers/scsi/ipr.h index 5945914..8f872f8 100644 --- a/drivers/scsi/ipr.h +++ b/drivers/scsi/ipr.h @@ -1272,7 +1272,7 @@ struct ipr_dump_entry_header { struct ipr_dump_location_entry { struct ipr_dump_entry_header hdr; - u8 location[BUS_ID_SIZE]; + u8 location[20]; }__attribute__((packed)); struct ipr_dump_trace_entry { diff --git a/drivers/scsi/lasi700.c b/drivers/scsi/lasi700.c index 3126824..4a4e695 100644 --- a/drivers/scsi/lasi700.c +++ b/drivers/scsi/lasi700.c @@ -103,8 +103,7 @@ lasi700_probe(struct parisc_device *dev) hostdata = kzalloc(sizeof(*hostdata), GFP_KERNEL); if (!hostdata) { - printk(KERN_ERR "%s: Failed to allocate host data\n", - dev->dev.bus_id); + dev_printk(KERN_ERR, dev, "Failed to allocate host data\n"); return -ENOMEM; } diff --git a/drivers/scsi/libsas/sas_discover.c b/drivers/scsi/libsas/sas_discover.c index 709a6f7..facc5bf 100644 --- a/drivers/scsi/libsas/sas_discover.c +++ b/drivers/scsi/libsas/sas_discover.c @@ -169,7 +169,7 @@ int sas_notify_lldd_dev_found(struct domain_device *dev) if (res) { printk("sas: driver on pcidev %s cannot handle " "device %llx, error:%d\n", - sas_ha->dev->bus_id, + dev_name(sas_ha->dev), SAS_ADDR(dev->sas_addr), res); } } diff --git a/drivers/scsi/libsas/sas_dump.c b/drivers/scsi/libsas/sas_dump.c index bf34a23..c17c250 100644 --- a/drivers/scsi/libsas/sas_dump.c +++ b/drivers/scsi/libsas/sas_dump.c @@ -56,7 +56,7 @@ void sas_dprint_phye(int phyid, enum phy_event pe) void sas_dprint_hae(struct sas_ha_struct *sas_ha, enum ha_event he) { - SAS_DPRINTK("ha %s: %s event\n", sas_ha->dev->bus_id, + SAS_DPRINTK("ha %s: %s event\n", dev_name(sas_ha->dev), sas_hae_str[he]); } diff --git a/drivers/scsi/libsas/sas_port.c b/drivers/scsi/libsas/sas_port.c index 139935a..e6ac59c 100644 --- a/drivers/scsi/libsas/sas_port.c +++ b/drivers/scsi/libsas/sas_port.c @@ -113,7 +113,7 @@ static void sas_form_port(struct asd_sas_phy *phy) sas_port_add_phy(port->port, phy->phy); SAS_DPRINTK("%s added to %s, phy_mask:0x%x (%16llx)\n", - phy->phy->dev.bus_id,port->port->dev.bus_id, + dev_name(&phy->phy->dev), dev_name(&port->port->dev), port->phy_mask, SAS_ADDR(port->attached_sas_addr)); diff --git a/drivers/scsi/raid_class.c b/drivers/scsi/raid_class.c index 913a931..8e5c169 100644 --- a/drivers/scsi/raid_class.c +++ b/drivers/scsi/raid_class.c @@ -237,8 +237,7 @@ int raid_component_add(struct raid_template *r,struct device *raid_dev, rc->dev.parent = get_device(component_dev); rc->num = rd->component_count++; - snprintf(rc->dev.bus_id, sizeof(rc->dev.bus_id), - "component-%d", rc->num); + dev_set_name(&rc->dev, "component-%d", rc->num); list_add_tail(&rc->node, &rd->component_list); rc->dev.class = &raid_class.class; err = device_add(&rc->dev); diff --git a/drivers/scsi/scsi_debug.c b/drivers/scsi/scsi_debug.c index 27c633f..6eebd0b 100644 --- a/drivers/scsi/scsi_debug.c +++ b/drivers/scsi/scsi_debug.c @@ -2508,7 +2508,7 @@ static void pseudo_0_release(struct device *dev) } static struct device pseudo_primary = { - .bus_id = "pseudo_0", + .init_name = "pseudo_0", .release = pseudo_0_release, }; @@ -2680,7 +2680,7 @@ static int sdebug_add_adapter(void) sdbg_host->dev.bus = &pseudo_lld_bus; sdbg_host->dev.parent = &pseudo_primary; sdbg_host->dev.release = &sdebug_release_adapter; - sprintf(sdbg_host->dev.bus_id, "adapter%d", scsi_debug_add_host); + dev_set_name(&sdbg_host->dev, "adapter%d", scsi_debug_add_host); error = device_register(&sdbg_host->dev); diff --git a/drivers/scsi/scsi_ioctl.c b/drivers/scsi/scsi_ioctl.c index 2ae4f8f..b98f763 100644 --- a/drivers/scsi/scsi_ioctl.c +++ b/drivers/scsi/scsi_ioctl.c @@ -167,10 +167,17 @@ EXPORT_SYMBOL(scsi_set_medium_removal); static int scsi_ioctl_get_pci(struct scsi_device *sdev, void __user *arg) { struct device *dev = scsi_get_device(sdev->host); + const char *name; if (!dev) return -ENXIO; - return copy_to_user(arg, dev->bus_id, sizeof(dev->bus_id))? -EFAULT: 0; + + name = dev_name(dev); + + /* compatibility with old ioctl which only returned + * 20 characters */ + return copy_to_user(arg, name, min(strlen(name), (size_t)20)) + ? -EFAULT: 0; } diff --git a/drivers/scsi/scsi_scan.c b/drivers/scsi/scsi_scan.c index 18486b5..f8493f2 100644 --- a/drivers/scsi/scsi_scan.c +++ b/drivers/scsi/scsi_scan.c @@ -411,8 +411,7 @@ static struct scsi_target *scsi_alloc_target(struct device *parent, device_initialize(dev); starget->reap_ref = 1; dev->parent = get_device(parent); - sprintf(dev->bus_id, "target%d:%d:%d", - shost->host_no, channel, id); + dev_set_name(dev, "target%d:%d:%d", shost->host_no, channel, id); #ifndef CONFIG_SYSFS_DEPRECATED dev->bus = &scsi_bus_type; #endif @@ -1021,7 +1020,7 @@ static int scsi_probe_and_add_lun(struct scsi_target *starget, if (rescan || !scsi_device_created(sdev)) { SCSI_LOG_SCAN_BUS(3, printk(KERN_INFO "scsi scan: device exists on %s\n", - sdev->sdev_gendev.bus_id)); + dev_name(&sdev->sdev_gendev))); if (sdevp) *sdevp = sdev; else @@ -1160,7 +1159,7 @@ static void scsi_sequential_lun_scan(struct scsi_target *starget, struct Scsi_Host *shost = dev_to_shost(starget->dev.parent); SCSI_LOG_SCAN_BUS(3, printk(KERN_INFO "scsi scan: Sequential scan of" - "%s\n", starget->dev.bus_id)); + "%s\n", dev_name(&starget->dev))); max_dev_lun = min(max_scsi_luns, shost->max_lun); /* diff --git a/drivers/scsi/scsi_sysfs.c b/drivers/scsi/scsi_sysfs.c index 93c28f3..da63802 100644 --- a/drivers/scsi/scsi_sysfs.c +++ b/drivers/scsi/scsi_sysfs.c @@ -1079,16 +1079,14 @@ void scsi_sysfs_device_initialize(struct scsi_device *sdev) device_initialize(&sdev->sdev_gendev); sdev->sdev_gendev.bus = &scsi_bus_type; sdev->sdev_gendev.type = &scsi_dev_type; - sprintf(sdev->sdev_gendev.bus_id,"%d:%d:%d:%d", - sdev->host->host_no, sdev->channel, sdev->id, - sdev->lun); - + dev_set_name(&sdev->sdev_gendev, "%d:%d:%d:%d", + sdev->host->host_no, sdev->channel, sdev->id, sdev->lun); + device_initialize(&sdev->sdev_dev); sdev->sdev_dev.parent = &sdev->sdev_gendev; sdev->sdev_dev.class = &sdev_class; - snprintf(sdev->sdev_dev.bus_id, BUS_ID_SIZE, - "%d:%d:%d:%d", sdev->host->host_no, - sdev->channel, sdev->id, sdev->lun); + dev_set_name(&sdev->sdev_dev, "%d:%d:%d:%d", + sdev->host->host_no, sdev->channel, sdev->id, sdev->lun); sdev->scsi_level = starget->scsi_level; transport_setup_device(&sdev->sdev_gendev); spin_lock_irqsave(shost->host_lock, flags); diff --git a/drivers/scsi/scsi_transport_fc.c b/drivers/scsi/scsi_transport_fc.c index 062304d..dcef787 100644 --- a/drivers/scsi/scsi_transport_fc.c +++ b/drivers/scsi/scsi_transport_fc.c @@ -2486,8 +2486,8 @@ fc_rport_create(struct Scsi_Host *shost, int channel, device_initialize(dev); /* takes self reference */ dev->parent = get_device(&shost->shost_gendev); /* parent reference */ dev->release = fc_rport_dev_release; - sprintf(dev->bus_id, "rport-%d:%d-%d", - shost->host_no, channel, rport->number); + dev_set_name(dev, "rport-%d:%d-%d", + shost->host_no, channel, rport->number); transport_setup_device(dev); error = device_add(dev); @@ -3164,8 +3164,8 @@ fc_vport_setup(struct Scsi_Host *shost, int channel, struct device *pdev, device_initialize(dev); /* takes self reference */ dev->parent = get_device(pdev); /* takes parent reference */ dev->release = fc_vport_dev_release; - sprintf(dev->bus_id, "vport-%d:%d-%d", - shost->host_no, channel, vport->number); + dev_set_name(dev, "vport-%d:%d-%d", + shost->host_no, channel, vport->number); transport_setup_device(dev); error = device_add(dev); @@ -3188,19 +3188,19 @@ fc_vport_setup(struct Scsi_Host *shost, int channel, struct device *pdev, */ if (pdev != &shost->shost_gendev) { error = sysfs_create_link(&shost->shost_gendev.kobj, - &dev->kobj, dev->bus_id); + &dev->kobj, dev_name(dev)); if (error) printk(KERN_ERR "%s: Cannot create vport symlinks for " "%s, err=%d\n", - __func__, dev->bus_id, error); + __func__, dev_name(dev), error); } spin_lock_irqsave(shost->host_lock, flags); vport->flags &= ~FC_VPORT_CREATING; spin_unlock_irqrestore(shost->host_lock, flags); dev_printk(KERN_NOTICE, pdev, - "%s created via shost%d channel %d\n", dev->bus_id, + "%s created via shost%d channel %d\n", dev_name(dev), shost->host_no, channel); *ret_vport = vport; @@ -3297,7 +3297,7 @@ fc_vport_terminate(struct fc_vport *vport) return stat; if (dev->parent != &shost->shost_gendev) - sysfs_remove_link(&shost->shost_gendev.kobj, dev->bus_id); + sysfs_remove_link(&shost->shost_gendev.kobj, dev_name(dev)); transport_remove_device(dev); device_del(dev); transport_destroy_device(dev); @@ -3329,7 +3329,7 @@ fc_vport_sched_delete(struct work_struct *work) dev_printk(KERN_ERR, vport->dev.parent, "%s: %s could not be deleted created via " "shost%d channel %d - error %d\n", __func__, - vport->dev.bus_id, vport->shost->host_no, + dev_name(&vport->dev), vport->shost->host_no, vport->channel, stat); } diff --git a/drivers/scsi/scsi_transport_iscsi.c b/drivers/scsi/scsi_transport_iscsi.c index 4a803eb..75c9297 100644 --- a/drivers/scsi/scsi_transport_iscsi.c +++ b/drivers/scsi/scsi_transport_iscsi.c @@ -187,8 +187,7 @@ iscsi_create_endpoint(int dd_size) ep->id = id; ep->dev.class = &iscsi_endpoint_class; - snprintf(ep->dev.bus_id, BUS_ID_SIZE, "ep-%llu", - (unsigned long long) id); + dev_set_name(&ep->dev, "ep-%llu", (unsigned long long) id); err = device_register(&ep->dev); if (err) goto free_ep; @@ -724,8 +723,7 @@ int iscsi_add_session(struct iscsi_cls_session *session, unsigned int target_id) } session->target_id = id; - snprintf(session->dev.bus_id, BUS_ID_SIZE, "session%u", - session->sid); + dev_set_name(&session->dev, "session%u", session->sid); err = device_add(&session->dev); if (err) { iscsi_cls_session_printk(KERN_ERR, session, @@ -898,8 +896,7 @@ iscsi_create_conn(struct iscsi_cls_session *session, int dd_size, uint32_t cid) if (!get_device(&session->dev)) goto free_conn; - snprintf(conn->dev.bus_id, BUS_ID_SIZE, "connection%d:%u", - session->sid, cid); + dev_set_name(&conn->dev, "connection%d:%u", session->sid, cid); conn->dev.parent = &session->dev; conn->dev.release = iscsi_conn_release; err = device_register(&conn->dev); @@ -1816,7 +1813,7 @@ iscsi_register_transport(struct iscsi_transport *tt) priv->t.create_work_queue = 1; priv->dev.class = &iscsi_transport_class; - snprintf(priv->dev.bus_id, BUS_ID_SIZE, "%s", tt->name); + dev_set_name(&priv->dev, "%s", tt->name); err = device_register(&priv->dev); if (err) goto free_priv; diff --git a/drivers/scsi/scsi_transport_sas.c b/drivers/scsi/scsi_transport_sas.c index 3666093..50988cb 100644 --- a/drivers/scsi/scsi_transport_sas.c +++ b/drivers/scsi/scsi_transport_sas.c @@ -207,7 +207,7 @@ static int sas_bsg_initialize(struct Scsi_Host *shost, struct sas_rphy *rphy) struct request_queue *q; int error; struct device *dev; - char namebuf[BUS_ID_SIZE]; + char namebuf[20]; const char *name; void (*release)(struct device *); @@ -219,7 +219,7 @@ static int sas_bsg_initialize(struct Scsi_Host *shost, struct sas_rphy *rphy) if (rphy) { q = blk_init_queue(sas_non_host_smp_request, NULL); dev = &rphy->dev; - name = dev->bus_id; + name = dev_name(dev); release = NULL; } else { q = blk_init_queue(sas_host_smp_request, NULL); @@ -629,10 +629,10 @@ struct sas_phy *sas_phy_alloc(struct device *parent, int number) INIT_LIST_HEAD(&phy->port_siblings); if (scsi_is_sas_expander_device(parent)) { struct sas_rphy *rphy = dev_to_rphy(parent); - sprintf(phy->dev.bus_id, "phy-%d:%d:%d", shost->host_no, + dev_set_name(&phy->dev, "phy-%d:%d:%d", shost->host_no, rphy->scsi_target_id, number); } else - sprintf(phy->dev.bus_id, "phy-%d:%d", shost->host_no, number); + dev_set_name(&phy->dev, "phy-%d:%d", shost->host_no, number); transport_setup_device(&phy->dev); @@ -770,7 +770,7 @@ static void sas_port_create_link(struct sas_port *port, int res; res = sysfs_create_link(&port->dev.kobj, &phy->dev.kobj, - phy->dev.bus_id); + dev_name(&phy->dev)); if (res) goto err; res = sysfs_create_link(&phy->dev.kobj, &port->dev.kobj, "port"); @@ -785,7 +785,7 @@ err: static void sas_port_delete_link(struct sas_port *port, struct sas_phy *phy) { - sysfs_remove_link(&port->dev.kobj, phy->dev.bus_id); + sysfs_remove_link(&port->dev.kobj, dev_name(&phy->dev)); sysfs_remove_link(&phy->dev.kobj, "port"); } @@ -821,11 +821,11 @@ struct sas_port *sas_port_alloc(struct device *parent, int port_id) if (scsi_is_sas_expander_device(parent)) { struct sas_rphy *rphy = dev_to_rphy(parent); - sprintf(port->dev.bus_id, "port-%d:%d:%d", shost->host_no, - rphy->scsi_target_id, port->port_identifier); + dev_set_name(&port->dev, "port-%d:%d:%d", shost->host_no, + rphy->scsi_target_id, port->port_identifier); } else - sprintf(port->dev.bus_id, "port-%d:%d", shost->host_no, - port->port_identifier); + dev_set_name(&port->dev, "port-%d:%d", shost->host_no, + port->port_identifier); transport_setup_device(&port->dev); @@ -935,7 +935,7 @@ void sas_port_delete(struct sas_port *port) if (port->is_backlink) { struct device *parent = port->dev.parent; - sysfs_remove_link(&port->dev.kobj, parent->bus_id); + sysfs_remove_link(&port->dev.kobj, dev_name(parent)); port->is_backlink = 0; } @@ -984,7 +984,8 @@ void sas_port_add_phy(struct sas_port *port, struct sas_phy *phy) /* If this trips, you added a phy that was already * part of a different port */ if (unlikely(tmp != phy)) { - dev_printk(KERN_ERR, &port->dev, "trying to add phy %s fails: it's already part of another port\n", phy->dev.bus_id); + dev_printk(KERN_ERR, &port->dev, "trying to add phy %s fails: it's already part of another port\n", + dev_name(&phy->dev)); BUG(); } } else { @@ -1023,7 +1024,7 @@ void sas_port_mark_backlink(struct sas_port *port) return; port->is_backlink = 1; res = sysfs_create_link(&port->dev.kobj, &parent->kobj, - parent->bus_id); + dev_name(parent)); if (res) goto err; return; @@ -1367,11 +1368,12 @@ struct sas_rphy *sas_end_device_alloc(struct sas_port *parent) rdev->rphy.dev.release = sas_end_device_release; if (scsi_is_sas_expander_device(parent->dev.parent)) { struct sas_rphy *rphy = dev_to_rphy(parent->dev.parent); - sprintf(rdev->rphy.dev.bus_id, "end_device-%d:%d:%d", - shost->host_no, rphy->scsi_target_id, parent->port_identifier); + dev_set_name(&rdev->rphy.dev, "end_device-%d:%d:%d", + shost->host_no, rphy->scsi_target_id, + parent->port_identifier); } else - sprintf(rdev->rphy.dev.bus_id, "end_device-%d:%d", - shost->host_no, parent->port_identifier); + dev_set_name(&rdev->rphy.dev, "end_device-%d:%d", + shost->host_no, parent->port_identifier); rdev->rphy.identify.device_type = SAS_END_DEVICE; sas_rphy_initialize(&rdev->rphy); transport_setup_device(&rdev->rphy.dev); @@ -1411,8 +1413,8 @@ struct sas_rphy *sas_expander_alloc(struct sas_port *parent, mutex_lock(&sas_host->lock); rdev->rphy.scsi_target_id = sas_host->next_expander_id++; mutex_unlock(&sas_host->lock); - sprintf(rdev->rphy.dev.bus_id, "expander-%d:%d", - shost->host_no, rdev->rphy.scsi_target_id); + dev_set_name(&rdev->rphy.dev, "expander-%d:%d", + shost->host_no, rdev->rphy.scsi_target_id); rdev->rphy.identify.device_type = type; sas_rphy_initialize(&rdev->rphy); transport_setup_device(&rdev->rphy.dev); @@ -1445,7 +1447,7 @@ int sas_rphy_add(struct sas_rphy *rphy) transport_add_device(&rphy->dev); transport_configure_device(&rphy->dev); if (sas_bsg_initialize(shost, rphy)) - printk("fail to a bsg device %s\n", rphy->dev.bus_id); + printk("fail to a bsg device %s\n", dev_name(&rphy->dev)); mutex_lock(&sas_host->lock); diff --git a/drivers/scsi/scsi_transport_srp.c b/drivers/scsi/scsi_transport_srp.c index 8a7af95..21a045e 100644 --- a/drivers/scsi/scsi_transport_srp.c +++ b/drivers/scsi/scsi_transport_srp.c @@ -212,7 +212,7 @@ struct srp_rport *srp_rport_add(struct Scsi_Host *shost, rport->roles = ids->roles; id = atomic_inc_return(&to_srp_host_attrs(shost)->next_port_id); - sprintf(rport->dev.bus_id, "port-%d:%d", shost->host_no, id); + dev_set_name(&rport->dev, "port-%d:%d", shost->host_no, id); transport_setup_device(&rport->dev); diff --git a/drivers/scsi/sd.c b/drivers/scsi/sd.c index 62b28d5..835aebf 100644 --- a/drivers/scsi/sd.c +++ b/drivers/scsi/sd.c @@ -1876,7 +1876,7 @@ static int sd_probe(struct device *dev) device_initialize(&sdkp->dev); sdkp->dev.parent = &sdp->sdev_gendev; sdkp->dev.class = &sd_disk_class; - strncpy(sdkp->dev.bus_id, sdp->sdev_gendev.bus_id, BUS_ID_SIZE); + dev_set_name(&sdkp->dev, dev_name(&sdp->sdev_gendev)); if (device_add(&sdkp->dev)) goto out_free_index; diff --git a/drivers/scsi/ses.c b/drivers/scsi/ses.c index 7f0df29..e946e05 100644 --- a/drivers/scsi/ses.c +++ b/drivers/scsi/ses.c @@ -526,7 +526,7 @@ static int ses_intf_add(struct device *cdev, if (!scomp) goto err_free; - edev = enclosure_register(cdev->parent, sdev->sdev_gendev.bus_id, + edev = enclosure_register(cdev->parent, dev_name(&sdev->sdev_gendev), components, &ses_enclosure_callbacks); if (IS_ERR(edev)) { err = PTR_ERR(edev); diff --git a/drivers/scsi/sim710.c b/drivers/scsi/sim710.c index d63d229..6dc8b84 100644 --- a/drivers/scsi/sim710.c +++ b/drivers/scsi/sim710.c @@ -102,7 +102,7 @@ sim710_probe_common(struct device *dev, unsigned long base_addr, struct NCR_700_Host_Parameters *hostdata = kzalloc(sizeof(struct NCR_700_Host_Parameters), GFP_KERNEL); - printk(KERN_NOTICE "sim710: %s\n", dev->bus_id); + printk(KERN_NOTICE "sim710: %s\n", dev_name(dev)); printk(KERN_NOTICE "sim710: irq = %d, clock = %d, base = 0x%lx, scsi_id = %d\n", irq, clock, base_addr, scsi_id); @@ -305,7 +305,7 @@ sim710_eisa_probe(struct device *dev) scsi_id = ffs(val) - 1; if(scsi_id > 7 || (val & ~(1<bus_id); + printk(KERN_ERR "sim710.c, EISA card %s has incorrect scsi_id, setting to 7\n", dev_name(dev)); scsi_id = 7; } } else { diff --git a/drivers/scsi/sni_53c710.c b/drivers/scsi/sni_53c710.c index 2bbef4c..77f0b2c 100644 --- a/drivers/scsi/sni_53c710.c +++ b/drivers/scsi/sni_53c710.c @@ -78,8 +78,7 @@ static int __init snirm710_probe(struct platform_device *dev) base = res->start; hostdata = kzalloc(sizeof(*hostdata), GFP_KERNEL); if (!hostdata) { - printk(KERN_ERR "%s: Failed to allocate host data\n", - dev->dev.bus_id); + dev_printk(KERN_ERR, dev, "Failed to allocate host data\n"); return -ENOMEM; } diff --git a/drivers/scsi/zalon.c b/drivers/scsi/zalon.c index 3c4a300..a8d61a6 100644 --- a/drivers/scsi/zalon.c +++ b/drivers/scsi/zalon.c @@ -137,8 +137,8 @@ zalon_probe(struct parisc_device *dev) goto fail; if (request_irq(dev->irq, ncr53c8xx_intr, IRQF_SHARED, "zalon", host)) { - printk(KERN_ERR "%s: irq problem with %d, detaching\n ", - dev->dev.bus_id, dev->irq); + dev_printk(KERN_ERR, dev, "irq problem with %d, detaching\n ", + dev->irq); goto fail; } -- 1.5.6.6 From kay.sievers@vrfy.org Fri Jan 2 16:31:08 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 02 Jan 2009 16:31:11 +0000 (GMT) Received: from mail-ew0-f21.google.com ([209.85.219.21]:3494 "EHLO mail-ew0-f21.google.com") by ftp.linux-mips.org with ESMTP id S24208002AbZABQbI (ORCPT ); Fri, 2 Jan 2009 16:31:08 +0000 Received: by ewy14 with SMTP id 14so6778941ewy.0 for ; Fri, 02 Jan 2009 08:31:02 -0800 (PST) Received: by 10.210.29.11 with SMTP id c11mr4077231ebc.29.1230913862688; Fri, 02 Jan 2009 08:31:02 -0800 (PST) Received: by 10.210.127.8 with HTTP; Fri, 2 Jan 2009 08:31:02 -0800 (PST) Message-ID: Date: Fri, 2 Jan 2009 17:31:02 +0100 From: "Kay Sievers" To: "James Bottomley" Subject: Re: [PATCH] SCSI: fix the return type of the remove() method in sgiwd93.c Cc: "Vorobiev Dmitri" , linux-scsi@vger.kernel.org, linux-mips@linux-mips.org, "Greg KH" In-Reply-To: <1230913510.3304.2.camel@localhost.localdomain> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Content-Disposition: inline References: <1227140357-29921-1-git-send-email-dmitri.vorobiev@movial.fi> <1228330800.5551.58.camel@localhost.localdomain> <1228337529.5551.72.camel@localhost.localdomain> <1228338142.5551.77.camel@localhost.localdomain> <1228340025.5551.87.camel@localhost.localdomain> <1228340496.6977.19.camel@nga> <1230913510.3304.2.camel@localhost.localdomain> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21680 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: kay.sievers@vrfy.org Precedence: bulk X-list: linux-mips Content-Length: 449 Lines: 14 On Fri, Jan 2, 2009 at 17:25, James Bottomley wrote: > Sorry, dropped the ball a bit on this. I've attached the updated > version: it copes with the legacy 20 character copy in the ioctl by > brute force and also adds several other dev->bus_id -> dev_name(dev) > conversions. Very nice. Thanks! Will you get that in 2.6.29 through your SCSI tree, or should the copy in Greg's tree be updated? Thanks, Kay From James.Bottomley@HansenPartnership.com Fri Jan 2 16:33:08 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 02 Jan 2009 16:33:10 +0000 (GMT) Received: from accolon.hansenpartnership.com ([76.243.235.52]:17856 "EHLO accolon.hansenpartnership.com") by ftp.linux-mips.org with ESMTP id S24208002AbZABQdI (ORCPT ); Fri, 2 Jan 2009 16:33:08 +0000 Received: from localhost (localhost [127.0.0.1]) by accolon.hansenpartnership.com (Postfix) with ESMTP id 569D481DC; Fri, 2 Jan 2009 10:33:01 -0600 (CST) Received: from accolon.hansenpartnership.com ([127.0.0.1]) by localhost (redscar.int.hansenpartnership.com [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id KorKJGzqVqKG; Fri, 2 Jan 2009 10:33:00 -0600 (CST) Received: from [153.66.150.222] (mulgrave-w.int.hansenpartnership.com [153.66.150.222]) by accolon.hansenpartnership.com (Postfix) with ESMTP id 2D0C97F63; Fri, 2 Jan 2009 10:33:00 -0600 (CST) Subject: Re: [PATCH] SCSI: fix the return type of the remove() method in sgiwd93.c From: James Bottomley To: Kay Sievers Cc: Vorobiev Dmitri , linux-scsi@vger.kernel.org, linux-mips@linux-mips.org, Greg KH In-Reply-To: References: <1227140357-29921-1-git-send-email-dmitri.vorobiev@movial.fi> <1228330800.5551.58.camel@localhost.localdomain> <1228337529.5551.72.camel@localhost.localdomain> <1228338142.5551.77.camel@localhost.localdomain> <1228340025.5551.87.camel@localhost.localdomain> <1228340496.6977.19.camel@nga> <1230913510.3304.2.camel@localhost.localdomain> Content-Type: text/plain Date: Fri, 02 Jan 2009 10:32:59 -0600 Message-Id: <1230913979.3304.3.camel@localhost.localdomain> Mime-Version: 1.0 X-Mailer: Evolution 2.22.3.1 (2.22.3.1-1.fc9) Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21681 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: James.Bottomley@HansenPartnership.com Precedence: bulk X-list: linux-mips Content-Length: 553 Lines: 18 On Fri, 2009-01-02 at 17:31 +0100, Kay Sievers wrote: > On Fri, Jan 2, 2009 at 17:25, James Bottomley > wrote: > > Sorry, dropped the ball a bit on this. I've attached the updated > > version: it copes with the legacy 20 character copy in the ioctl by > > brute force and also adds several other dev->bus_id -> dev_name(dev) > > conversions. > > Very nice. Thanks! > > Will you get that in 2.6.29 through your SCSI tree, or should the copy > in Greg's tree be updated? I'll send it with my next set. James From sgi-linux-mips@m.gmane.org Sun Jan 4 14:54:04 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 04 Jan 2009 14:54:06 +0000 (GMT) Received: from main.gmane.org ([80.91.229.2]:19842 "EHLO ciao.gmane.org") by ftp.linux-mips.org with ESMTP id S24207815AbZADOyE (ORCPT ); Sun, 4 Jan 2009 14:54:04 +0000 Received: from list by ciao.gmane.org with local (Exim 4.43) id 1LJUMd-00017h-6K for linux-mips@linux-mips.org; Sun, 04 Jan 2009 14:54:03 +0000 Received: from vpn40.rz.tu-ilmenau.de ([141.24.172.40]) by main.gmane.org with esmtp (Gmexim 0.1 (Debian)) id 1AlnuQ-0007hv-00 for ; Sun, 04 Jan 2009 14:54:03 +0000 Received: from opencode by vpn40.rz.tu-ilmenau.de with local (Gmexim 0.1 (Debian)) id 1AlnuQ-0007hv-00 for ; Sun, 04 Jan 2009 14:54:03 +0000 X-Injected-Via-Gmane: http://gmane.org/ To: linux-mips@linux-mips.org From: Andi Subject: SMP8634 Linux boot Date: Sun, 04 Jan 2009 15:53:50 +0100 Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-Complaints-To: usenet@ger.gmane.org X-Gmane-NNTP-Posting-Host: vpn40.rz.tu-ilmenau.de User-Agent: Thunderbird 2.0.0.18 (X11/20081125) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21682 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: opencode@gmx.net Precedence: bulk X-list: linux-mips Content-Length: 874 Lines: 19 Hi List, First of all, sorry for asking a slightly off topic question on that list but it has something to do with MIPS and Linux though. As I don't have a working zboot image, I am trying to load zboot or yamon via JTAG to a SMP8634 board in order to boot Linux afterwards. I followed the instructions described in smp8634-documentation and was able to build a yamon and reboot image which successfully loads on a plain smp8634. Unfortunately, this is not the case when building yamon with XENV support or when trying to load a zboot image instead. On the other hand I can't load Linux on a yamon without XENV support, yet. After loading xboot which fails to load zboot now, do I have to initialize the memory mapping or other registers prior loading any other code like yamon or zboot? If so, which one? Any help to load Linux is very appreciated. Best regards, Andi From medson@avtrex.com Mon Jan 5 03:35:19 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 05 Jan 2009 03:35:22 +0000 (GMT) Received: from smtp1.dnsmadeeasy.com ([205.234.170.134]:39070 "EHLO smtp1.dnsmadeeasy.com") by ftp.linux-mips.org with ESMTP id S24063297AbZAEDfT convert rfc822-to-8bit (ORCPT ); Mon, 5 Jan 2009 03:35:19 +0000 Received: from smtp1.dnsmadeeasy.com (localhost [127.0.0.1]) by smtp1.dnsmadeeasy.com (Postfix) with ESMTP id E792432221A; Mon, 5 Jan 2009 03:35:07 +0000 (UTC) X-Authenticated-Name: js.dnsmadeeasy X-Transit-System: In case of SPAM please contact abuse@dnsmadeeasy.com Received: from avtrex.com (unknown [173.8.135.205]) by smtp1.dnsmadeeasy.com (Postfix) with ESMTP; Mon, 5 Jan 2009 03:35:07 +0000 (UTC) Content-class: urn:content-classes:message MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT X-MimeOLE: Produced By Microsoft Exchange V6.5 Subject: RE: SMP8634 Linux boot Date: Sun, 4 Jan 2009 19:35:05 -0800 Message-ID: <01049E563C8ECC43AD6B53A5AF419B380128FE3B@avtrex-server2.hq2.avtrex.com> In-Reply-To: X-MS-Has-Attach: X-MS-TNEF-Correlator: Thread-Topic: SMP8634 Linux boot Thread-Index: AclufGPRqkJP5+S0TX6x55Twb7U56AAaYNeA From: "Mark Edson" To: "Andi" , Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21683 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: medson@avtrex.com Precedence: bulk X-list: linux-mips Content-Length: 2029 Lines: 60 We use MAJIC-LT boot loader. Our steps on the MAJIC-LT host are: $ cd /opt/edtm/targets/sigma_vantage $ /opt/edtm/bin/monice -v4kec -d majic-lt:e -l (monice should report connected) MON> ew 0xa003fffc =3 MON> ew 0xa003fffc =2 MON> ew 0xa0030000 =0xE34111BA MON> ew 0xa003fffc =0xa4444 MON> ew 0xa003fffc =0 MON> ew 0xa006f000 = 0x60000 MON> l yamon.elf MON> l reset.elf Mon> g And that gives us a YAMON> prompt on the serial console of the 8634. From _that_ YAMON> prompt, we load the real xenv/zboot/yamon like this: YAMON> load uu 0xb0100000 (send zboot2.bin.uu) YAMON> load uu 0xb0200000 (send zbimage-yamon.uu) YAMON> pflash write 0 0xb0100000 YAMON> pflash write 0x40000 0xb0200000 200704 Then when you reboot w/o JTAG, it should give you a YAMON prompt on the console. Good luck... Mark -----Original Message----- From: linux-mips-bounce@linux-mips.org [mailto:linux-mips-bounce@linux-mips.org] On Behalf Of Andi Sent: Sunday, January 04, 2009 6:54 AM To: linux-mips@linux-mips.org Subject: SMP8634 Linux boot Hi List, First of all, sorry for asking a slightly off topic question on that list but it has something to do with MIPS and Linux though. As I don't have a working zboot image, I am trying to load zboot or yamon via JTAG to a SMP8634 board in order to boot Linux afterwards. I followed the instructions described in smp8634-documentation and was able to build a yamon and reboot image which successfully loads on a plain smp8634. Unfortunately, this is not the case when building yamon with XENV support or when trying to load a zboot image instead. On the other hand I can't load Linux on a yamon without XENV support, yet. After loading xboot which fails to load zboot now, do I have to initialize the memory mapping or other registers prior loading any other code like yamon or zboot? If so, which one? Any help to load Linux is very appreciated. Best regards, Andi From David.Daney@caviumnetworks.com Mon Jan 5 23:31:06 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 05 Jan 2009 23:31:09 +0000 (GMT) Received: from mail3.caviumnetworks.com ([12.108.191.235]:53743 "EHLO mail3.caviumnetworks.com") by ftp.linux-mips.org with ESMTP id S24190235AbZAEXbG (ORCPT ); Mon, 5 Jan 2009 23:31:06 +0000 Received: from exch4.caveonetworks.com (Not Verified[192.168.16.23]) by mail3.caviumnetworks.com with MailMarshal (v6,2,2,3503) id ; Mon, 05 Jan 2009 18:29:26 -0500 Received: from exch4.caveonetworks.com ([192.168.16.23]) by exch4.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Mon, 5 Jan 2009 15:29:18 -0800 Received: from dd1.caveonetworks.com ([64.169.86.201]) by exch4.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Mon, 5 Jan 2009 15:29:18 -0800 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.2/8.14.2) with ESMTP id n05NTFMY018505; Mon, 5 Jan 2009 15:29:15 -0800 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.2/8.14.2/Submit) id n05NTFrX018503; Mon, 5 Jan 2009 15:29:15 -0800 From: David Daney To: linux-mips@linux-mips.org Cc: David Daney Subject: [PATCH] MIPS: Use hardware watchpoints on all R1 and R2 CPUs. Date: Mon, 5 Jan 2009 15:29:14 -0800 Message-Id: <1231198154-18480-1-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.5.6.6 X-OriginalArrivalTime: 05 Jan 2009 23:29:18.0310 (UTC) FILETIME=[6DFC6860:01C96F8D] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21684 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Content-Length: 550 Lines: 23 The previous definition inadvertently omits Octeon. Signed-off-by: David Daney --- arch/mips/Kconfig | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index ea2b262..39b7081 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -1360,7 +1360,7 @@ config CPU_SUPPORTS_64BIT_KERNEL # config HARDWARE_WATCHPOINTS bool - default y if CPU_MIPS32 || CPU_MIPS64 + default y if CPU_MIPSR1 || CPU_MIPSR2 menu "Kernel type" -- 1.5.6.6 From David.Daney@caviumnetworks.com Mon Jan 5 23:31:26 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 05 Jan 2009 23:31:29 +0000 (GMT) Received: from mail3.caviumnetworks.com ([12.108.191.235]:54255 "EHLO mail3.caviumnetworks.com") by ftp.linux-mips.org with ESMTP id S24207836AbZAEXbG (ORCPT ); Mon, 5 Jan 2009 23:31:06 +0000 Received: from exch4.caveonetworks.com (Not Verified[192.168.16.23]) by mail3.caviumnetworks.com with MailMarshal (v6,2,2,3503) id ; Mon, 05 Jan 2009 18:30:09 -0500 Received: from exch4.caveonetworks.com ([192.168.16.23]) by exch4.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Mon, 5 Jan 2009 15:30:01 -0800 Received: from dd1.caveonetworks.com ([64.169.86.201]) by exch4.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Mon, 5 Jan 2009 15:30:01 -0800 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.2/8.14.2) with ESMTP id n05NTxjV018563; Mon, 5 Jan 2009 15:29:59 -0800 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.2/8.14.2/Submit) id n05NTwLq018562; Mon, 5 Jan 2009 15:29:58 -0800 From: David Daney To: linux-mips@linux-mips.org Cc: David Daney Subject: [PATCH] MIPS: Read watch registers with interrupts disabled. Date: Mon, 5 Jan 2009 15:29:58 -0800 Message-Id: <1231198198-18539-1-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.5.6.6 X-OriginalArrivalTime: 05 Jan 2009 23:30:01.0404 (UTC) FILETIME=[87AC07C0:01C96F8D] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21685 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Content-Length: 1762 Lines: 59 If a context switch occurred between the watch exception and reading the watch registers, it would be possible for the new process to corrupt their state. Enabling interrupts only after the watch registers are read avoids this race. Signed-off-by: David Daney --- arch/mips/kernel/genex.S | 6 +++++- arch/mips/kernel/traps.c | 8 +++++++- 2 files changed, 12 insertions(+), 2 deletions(-) diff --git a/arch/mips/kernel/genex.S b/arch/mips/kernel/genex.S index fb6f731..8882e57 100644 --- a/arch/mips/kernel/genex.S +++ b/arch/mips/kernel/genex.S @@ -458,7 +458,11 @@ NESTED(nmi_handler, PT_SIZE, sp) BUILD_HANDLER fpe fpe fpe silent /* #15 */ BUILD_HANDLER mdmx mdmx sti silent /* #22 */ #ifdef CONFIG_HARDWARE_WATCHPOINTS - BUILD_HANDLER watch watch sti silent /* #23 */ + /* + * For watch, interrupts will be enabled after the watch + * registers are read. + */ + BUILD_HANDLER watch watch cli silent /* #23 */ #else BUILD_HANDLER watch watch sti verbose /* #23 */ #endif diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index f6083c6..7a97b3f 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -944,6 +944,9 @@ asmlinkage void do_mdmx(struct pt_regs *regs) force_sig(SIGILL, current); } +/* + * Called with interrupts disabled. + */ asmlinkage void do_watch(struct pt_regs *regs) { u32 cause; @@ -963,9 +966,12 @@ asmlinkage void do_watch(struct pt_regs *regs) */ if (test_tsk_thread_flag(current, TIF_LOAD_WATCH)) { mips_read_watch_registers(); + local_irq_enable(); force_sig(SIGTRAP, current); - } else + } else { mips_clear_watch_registers(); + local_irq_enable(); + } } asmlinkage void do_mcheck(struct pt_regs *regs) -- 1.5.6.6 From mano@roarinelk.homelinux.net Tue Jan 6 09:34:57 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 06 Jan 2009 09:34:59 +0000 (GMT) Received: from fnoeppeil48.netpark.at ([217.175.205.176]:31958 "EHLO roarinelk.homelinux.net") by ftp.linux-mips.org with ESMTP id S24053316AbZAFJey (ORCPT ); Tue, 6 Jan 2009 09:34:54 +0000 Received: (qmail 8452 invoked from network); 6 Jan 2009 10:34:53 +0100 Received: from scarran.roarinelk.net (HELO localhost.localdomain) (192.168.0.242) by 192.168.0.1 with SMTP; 6 Jan 2009 10:34:53 +0100 From: Manuel Lauss To: Linux-MIPS Cc: Manuel Lauss Subject: [PATCH] Alchemy: time.c build fix Date: Tue, 6 Jan 2009 10:34:52 +0100 Message-Id: <1231234492-25733-1-git-send-email-mano@roarinelk.homelinux.net> X-Mailer: git-send-email 1.6.0.6 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21686 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mano@roarinelk.homelinux.net Precedence: bulk X-list: linux-mips Content-Length: 736 Lines: 23 in Linus' current -git the cpumask member is now a pointer. Signed-off-by: Manuel Lauss --- arch/mips/alchemy/common/time.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/mips/alchemy/common/time.c b/arch/mips/alchemy/common/time.c index 307514f..183180a 100644 --- a/arch/mips/alchemy/common/time.c +++ b/arch/mips/alchemy/common/time.c @@ -69,7 +69,7 @@ static struct clock_event_device au1x_rtcmatch2_clockdev = { .irq = AU1000_RTC_MATCH2_INT, .set_next_event = au1x_rtcmatch2_set_next_event, .set_mode = au1x_rtcmatch2_set_mode, - .cpumask = CPU_MASK_ALL, + .cpumask = CPU_MASK_ALL_PTR, }; static struct irqaction au1x_rtcmatch2_irqaction = { -- 1.6.0.6 From dvomlehn@cisco.com Tue Jan 6 21:46:35 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 06 Jan 2009 21:46:38 +0000 (GMT) Received: from rtp-iport-1.cisco.com ([64.102.122.148]:33128 "EHLO rtp-iport-1.cisco.com") by ftp.linux-mips.org with ESMTP id S21102852AbZAFVqf convert rfc822-to-8bit (ORCPT ); Tue, 6 Jan 2009 21:46:35 +0000 X-IronPort-AV: E=Sophos;i="4.37,221,1231113600"; d="scan'208";a="32901298" Received: from rtp-dkim-2.cisco.com ([64.102.121.159]) by rtp-iport-1.cisco.com with ESMTP; 06 Jan 2009 21:46:28 +0000 Received: from rtp-core-1.cisco.com (rtp-core-1.cisco.com [64.102.124.12]) by rtp-dkim-2.cisco.com (8.12.11/8.12.11) with ESMTP id n06LkRGE029640; Tue, 6 Jan 2009 16:46:27 -0500 Received: from xbh-rtp-211.amer.cisco.com (xbh-rtp-211.cisco.com [64.102.31.102]) by rtp-core-1.cisco.com (8.13.8/8.13.8) with ESMTP id n06LkR62004272; Tue, 6 Jan 2009 21:46:28 GMT Received: from xmb-rtp-218.amer.cisco.com ([64.102.31.117]) by xbh-rtp-211.amer.cisco.com with Microsoft SMTPSVC(6.0.3790.1830); Tue, 6 Jan 2009 16:46:27 -0500 X-MimeOLE: Produced By Microsoft Exchange V6.5 Content-class: urn:content-classes:message MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT Subject: RE: [PATCH] MIPS: unsigned result is always greater than 0 Date: Tue, 6 Jan 2009 16:46:19 -0500 Message-ID: In-Reply-To: <495E2E47.6080605@gmail.com> X-MS-Has-Attach: X-MS-TNEF-Correlator: Thread-Topic: [PATCH] MIPS: unsigned result is always greater than 0 Thread-Index: Acls7EfWnUJEqqivROa5wJWiY2zpvQDWuIJg References: <495E2E47.6080605@gmail.com> From: "David VomLehn (dvomlehn)" To: "Roel Kluin" , Cc: X-OriginalArrivalTime: 06 Jan 2009 21:46:27.0831 (UTC) FILETIME=[3A81C870:01C97048] DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; l=1894; t=1231278387; x=1232142387; c=relaxed/simple; s=rtpdkim2001; h=Content-Type:From:Subject:Content-Transfer-Encoding:MIME-Version; d=cisco.com; i=dvomlehn@cisco.com; z=From:=20=22David=20VomLehn=20(dvomlehn)=22=20 |Subject:=20RE=3A=20[PATCH]=20MIPS=3A=20unsigned=20result=2 0is=20always=20greater=20than=200 |Sender:=20 |To:=20=22Roel=20Kluin=22=20,=20; bh=jWocxyxDaCUg6B9soHVdslVwborpn2SdrpMosvPKt5g=; b=o1CdR8E+mq0D2iyvmxmn4adI2dGkEh5rR6b5vBKZUAB+3eke1Fsfu3V7Ur JmOMaojtM1NG+J0dARJOWvOdwwCevC5Zr3kKpC4h3HCdN4JK6jCIjmYW4mNT G1mZm080s4; Authentication-Results: rtp-dkim-2; header.From=dvomlehn@cisco.com; dkim=pass ( sig from cisco.com/rtpdkim2001 verified; ); Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21688 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dvomlehn@cisco.com Precedence: bulk X-list: linux-mips > -----Original Message----- > From: linux-mips-bounce@linux-mips.org > [mailto:linux-mips-bounce@linux-mips.org] On Behalf Of Roel Kluin > Sent: Friday, January 02, 2009 7:10 AM > To: ralf@linux-mips.org > Cc: linux-mips@linux-mips.org > Subject: [PATCH] MIPS: unsigned result is always greater than 0 > > unsigned result is always greater than 0 > > Signed-off-by: Roel Kluin > --- > I cannot determine whether the same bug occurs as well in assembly. > Also shouldn't similar checks occur in atomic64_sub_return and in > atomic64_add_return for negative values of i? > > diff --git a/arch/mips/include/asm/atomic.h > b/arch/mips/include/asm/atomic.h > index 1232be3..3cd07a9 100644 > --- a/arch/mips/include/asm/atomic.h > +++ b/arch/mips/include/asm/atomic.h > @@ -296,9 +296,10 @@ static __inline__ int > atomic_sub_if_positive(int i, atomic_t * v) > > raw_local_irq_save(flags); > result = v->counter; > - result -= i; > - if (result >= 0) > + if (i <= result) { > + result -= i; > v->counter = result; > + } > raw_local_irq_restore(flags); > } > > @@ -677,9 +678,10 @@ static __inline__ long > atomic64_sub_if_positive(long i, atomic64_t * v) > > raw_local_irq_save(flags); > result = v->counter; > - result -= i; > - if (result >= 0) > + if (i >= result) { > + result -= i; > v->counter = result; > + } > raw_local_irq_restore(flags); > } I agree that the code as it exists is wrong, but, as I see it, the problem is that the type of result should be changed from unsigned long to int. This fixes the comparison so it works correctly. In addition, such a change means that result would be the same type as the counter element of atomic_t, avoiding possible surprises should longs be larger than ints. From David.Daney@caviumnetworks.com Thu Jan 8 01:41:57 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 08 Jan 2009 01:42:00 +0000 (GMT) Received: from mail3.caviumnetworks.com ([12.108.191.235]:42278 "EHLO mail3.caviumnetworks.com") by ftp.linux-mips.org with ESMTP id S21103469AbZAHBl5 (ORCPT ); Thu, 8 Jan 2009 01:41:57 +0000 Received: from exch4.caveonetworks.com (Not Verified[192.168.16.23]) by mail3.caviumnetworks.com with MailMarshal (v6,2,2,3503) id ; Wed, 07 Jan 2009 20:41:40 -0500 Received: from exch4.caveonetworks.com ([192.168.16.23]) by exch4.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Wed, 7 Jan 2009 17:41:39 -0800 Received: from dd1.caveonetworks.com ([64.169.86.201]) by exch4.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Wed, 7 Jan 2009 17:41:39 -0800 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.2/8.14.2) with ESMTP id n081fbfN025951; Wed, 7 Jan 2009 17:41:37 -0800 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.2/8.14.2/Submit) id n081fapH025949; Wed, 7 Jan 2009 17:41:36 -0800 From: David Daney To: linux-mips@linux-mips.org Cc: David Daney Subject: [PATCH] MIPS: Add option for running kernel in mapped address space. Date: Wed, 7 Jan 2009 17:41:36 -0800 Message-Id: <1231378896-25925-1-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.5.6.6 X-OriginalArrivalTime: 08 Jan 2009 01:41:39.0673 (UTC) FILETIME=[403BBC90:01C97132] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21689 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips This is a preliminary patch to allow the kernel to run in mapped address space via a wired TLB entry. Probably in a future version I would factor out the OCTEON specific parts to a separate patch. Each supported processor would probably need to doctor up its kernel-entry-init.h in a similar manner. Signed-off-by: David Daney --- arch/mips/Kconfig | 17 +++++++ arch/mips/Makefile | 10 ++++- .../asm/mach-cavium-octeon/kernel-entry-init.h | 50 ++++++++++++++++++++ arch/mips/include/asm/page.h | 10 ++++- arch/mips/include/asm/pgtable-64.h | 7 ++- arch/mips/kernel/traps.c | 23 +++++++-- arch/mips/kernel/vmlinux.lds.S | 11 ++++- arch/mips/mm/page.c | 6 ++ arch/mips/mm/tlb-r4k.c | 4 ++ 9 files changed, 129 insertions(+), 9 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 780b520..d9c46a4 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -1431,6 +1431,23 @@ config PAGE_SIZE_64KB endchoice +config MAPPED_KERNEL + bool "Mapped kernel" + help + Select this option if you want the kernel's code and data to + be in mapped memory. The kernel will be mapped using a + single wired TLB entry, thus reducing the number of + available TLB entries by one. Kernel modules will be able + to use a more efficient calling convention. + +config PHYS_LOAD_ADDRESS + hex "Physical load address" + depends on MAPPED_KERNEL + default ffffffff81400000 + help + The physical load address reflected as the program header + physical address in the kernel ELF image. + config BOARD_SCACHE bool diff --git a/arch/mips/Makefile b/arch/mips/Makefile index 0bc2120..5468f6d 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -82,7 +82,10 @@ all-$(CONFIG_BOOT_ELF64) := $(vmlinux-64) cflags-y += -G 0 -mno-abicalls -fno-pic -pipe cflags-y += -msoft-float LDFLAGS_vmlinux += -G 0 -static -n -nostdlib + +ifndef CONFIG_MAPPED_KERNEL MODFLAGS += -mlong-calls +endif cflags-y += -ffreestanding @@ -605,6 +608,11 @@ endif cflags-y += -I$(srctree)/arch/mips/include/asm/mach-generic drivers-$(CONFIG_PCI) += arch/mips/pci/ +ifdef CONFIG_MAPPED_KERNEL + PHYS_LOAD_ADDRESS = -D"PHYSADDR=0x$(CONFIG_PHYS_LOAD_ADDRESS)" + load-y = 0xffffffffc0000000 +endif + ifdef CONFIG_32BIT ifdef CONFIG_CPU_LITTLE_ENDIAN JIFFIES = jiffies_64 @@ -662,7 +670,7 @@ OBJCOPYFLAGS += --remove-section=.reginfo CPPFLAGS_vmlinux.lds := \ $(KBUILD_CFLAGS) \ - -D"LOADADDR=$(load-y)" \ + -D"LOADADDR=$(load-y)" $(PHYS_LOAD_ADDRESS) \ -D"JIFFIES=$(JIFFIES)" \ -D"DATAOFFSET=$(if $(dataoffset-y),$(dataoffset-y),0)" diff --git a/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h b/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h index 0b2b5eb..bf36d82 100644 --- a/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h +++ b/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h @@ -27,6 +27,56 @@ # a3 = address of boot descriptor block .set push .set arch=octeon +#ifdef CONFIG_MAPPED_KERNEL + # Set up the TLB index 0 for wired access to kernel. + # Assume we were loaded with sufficient alignment so that we + # can cover the image with two pages. + dla v0, _end + dla v1, _text + dsubu v0, v0, v1 # size of image + move v1, zero + li t1, -1 # shift count. +1: dsrl v0, v0, 1 # mask into v1 + dsll v1, v1, 1 + daddiu t1, t1, 1 + ori v1, v1, 1 + bne v0, zero, 1b + daddiu t2, t1, -6 + mtc0 v1, $5, 0 # PageMask + dla t3, 0xffffffffc0000000 # kernel address + dmtc0 t3, $10, 0 # EntryHi + bal 1f +1: dla v0, 0x7fffffff + and ra, ra, v0 # physical address of pc in ra + dsrl v1, v1, 1 + nor v1, v1, zero + and ra, ra, v1 + dsubu v1, t3, ra # virtual to physical offset into v1 + dsrlv v0, ra, t1 + dsllv v0, v0, t2 + ori v0, v0, 0x1f + dmtc0 v0, $2, 0 # EntryLo1 + dsrlv v0, ra, t1 + daddiu v0, v0, 1 + dsllv v0, v0, t2 + ori v0, v0, 0x1f + dmtc0 v0, $3, 0 # EntryLo2 + mtc0 $0, $0, 0 # Set index to zero + tlbwi + li v0, 1 + mtc0 v0, $6, 0 # Wired + dla v0, phys_to_kernel_offset + sd v1, 0(v0) + dla v0, kernel_image_end + li v1, 2 + dsllv v1, v1, t1 + daddu v1, v1, t3 + sd v1, 0(v0) + dla v0, continue_in_mapped_space + jr v0 + +continue_in_mapped_space: +#endif # Read the cavium mem control register dmfc0 v0, CP0_CVMMEMCTL_REG # Clear the lower 6 bits, the CVMSEG size diff --git a/arch/mips/include/asm/page.h b/arch/mips/include/asm/page.h index fe7a88e..5a20413 100644 --- a/arch/mips/include/asm/page.h +++ b/arch/mips/include/asm/page.h @@ -151,7 +151,15 @@ typedef struct { unsigned long pgprot; } pgprot_t; ((unsigned long)(x) - PAGE_OFFSET + PHYS_OFFSET) #endif #define __va(x) ((void *)((unsigned long)(x) + PAGE_OFFSET - PHYS_OFFSET)) -#define __pa_symbol(x) __pa(RELOC_HIDE((unsigned long)(x), 0)) + +#ifndef __ASSEMBLY__ +# ifdef CONFIG_MAPPED_KERNEL +extern unsigned long phys_to_kernel_offset; +# define __pa_symbol(x) (RELOC_HIDE((unsigned long)(x), 0) - phys_to_kernel_offset) +# else +# define __pa_symbol(x) __pa(RELOC_HIDE((unsigned long)(x), 0)) +# endif +#endif #define pfn_to_kaddr(pfn) __va((pfn) << PAGE_SHIFT) diff --git a/arch/mips/include/asm/pgtable-64.h b/arch/mips/include/asm/pgtable-64.h index 943515f..1905a43 100644 --- a/arch/mips/include/asm/pgtable-64.h +++ b/arch/mips/include/asm/pgtable-64.h @@ -107,7 +107,12 @@ #if defined(CONFIG_MODULES) && defined(KBUILD_64BIT_SYM32) && \ VMALLOC_START != CKSSEG /* Load modules into 32bit-compatible segment. */ -#define MODULE_START CKSSEG +#ifdef CONFIG_MAPPED_KERNEL +extern unsigned long kernel_image_end; +#define MODULE_START kernel_image_end +#else +#define MODULE_START CKSSEG +#endif #define MODULE_END (FIXADDR_START-2*PAGE_SIZE) extern pgd_t module_pg_dir[PTRS_PER_PGD]; #endif diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index 1055348..b44bcf8 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -49,6 +49,8 @@ #include #include +#include "../mm/uasm.h" + extern void check_wait(void); extern asmlinkage void r4k_wait(void); extern asmlinkage void rollback_handle_int(void); @@ -1295,9 +1297,18 @@ void *set_except_vector(int n, void *addr) exception_handlers[n] = handler; if (n == 0 && cpu_has_divec) { - *(u32 *)(ebase + 0x200) = 0x08000000 | - (0x03ffffff & (handler >> 2)); - local_flush_icache_range(ebase + 0x200, ebase + 0x204); + unsigned long jump_mask = ~((1 << 28) - 1); + u32 *buf = (u32 *)(ebase + 0x200); + unsigned int k0 = 26; + if((handler & jump_mask) == ((ebase + 0x200) & jump_mask)) { + uasm_i_j(&buf, handler & jump_mask); + uasm_i_nop(&buf); + } else { + UASM_i_LA(&buf, k0, handler); + uasm_i_jr(&buf, k0); + uasm_i_nop(&buf); + } + local_flush_icache_range(ebase + 0x200, (unsigned long)buf); } return (void *)old_handler; } @@ -1570,6 +1581,8 @@ void __cpuinit per_cpu_trap_init(void) evpe(vpflags); } else set_c0_cause(CAUSEF_IV); + } else { + clear_c0_cause(CAUSEF_IV); } /* @@ -1670,9 +1683,9 @@ void __init trap_init(void) return; /* Already done */ #endif - if (cpu_has_veic || cpu_has_vint) + if (cpu_has_veic || cpu_has_vint) { ebase = (unsigned long) alloc_bootmem_low_pages(0x200 + VECTORSPACING*64); - else { + } else { ebase = CAC_BASE; if (cpu_has_mips_r2) ebase += (read_c0_ebase() & 0x3ffff000); diff --git a/arch/mips/kernel/vmlinux.lds.S b/arch/mips/kernel/vmlinux.lds.S index 58738c8..f96c332 100644 --- a/arch/mips/kernel/vmlinux.lds.S +++ b/arch/mips/kernel/vmlinux.lds.S @@ -4,11 +4,20 @@ #undef mips #define mips mips OUTPUT_ARCH(mips) +#ifdef PHYSADDR +ENTRY(phys_entry) +#define AT_LOCATION AT(PHYSADDR) +#else ENTRY(kernel_entry) +#define AT_LOCATION +#endif PHDRS { - text PT_LOAD FLAGS(7); /* RWX */ + text PT_LOAD AT_LOCATION FLAGS(7); /* RWX */ note PT_NOTE FLAGS(4); /* R__ */ } +#ifdef PHYSADDR +phys_entry = kernel_entry - LOADADDR + PHYSADDR; +#endif jiffies = JIFFIES; SECTIONS diff --git a/arch/mips/mm/page.c b/arch/mips/mm/page.c index 1417c64..0070aa0 100644 --- a/arch/mips/mm/page.c +++ b/arch/mips/mm/page.c @@ -687,3 +687,9 @@ void copy_page(void *to, void *from) } #endif /* CONFIG_SIBYTE_DMA_PAGEOPS */ + +#ifdef CONFIG_MAPPED_KERNEL +/* Initialized so it is not clobbered when .bss is zeroed. */ +unsigned long phys_to_kernel_offset = 1; +unsigned long kernel_image_end = 1; +#endif diff --git a/arch/mips/mm/tlb-r4k.c b/arch/mips/mm/tlb-r4k.c index 5ce2fa7..ebe4ee8 100644 --- a/arch/mips/mm/tlb-r4k.c +++ b/arch/mips/mm/tlb-r4k.c @@ -477,8 +477,12 @@ void __cpuinit tlb_init(void) */ probe_tlb(config); write_c0_pagemask(PM_DEFAULT_MASK); +#ifndef CONFIG_MAPPED_KERNEL write_c0_wired(0); +#endif +#ifndef CONFIG_CPU_CAVIUM_OCTEON write_c0_framemask(0); +#endif temp_tlb_entry = current_cpu_data.tlbsize - 1; /* From this point on the ARC firmware is dead. */ -- 1.5.6.6 From ihar.hrachyshka@gmail.com Thu Jan 8 16:58:44 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 08 Jan 2009 16:58:47 +0000 (GMT) Received: from mail-bw0-f13.google.com ([209.85.218.13]:37338 "EHLO mail-bw0-f13.google.com") by ftp.linux-mips.org with ESMTP id S21365000AbZAHQ6o (ORCPT ); Thu, 8 Jan 2009 16:58:44 +0000 Received: by bwz6 with SMTP id 6so24011501bwz.0 for ; Thu, 08 Jan 2009 08:58:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:message-id:date:from:to :subject:in-reply-to:mime-version:content-type :content-transfer-encoding:content-disposition:references; bh=vNyNdLZKCaj+q9wKXAGe1eG1KXQzwwrWlJ8D1kLKrPc=; b=pk0Il809fh+6TOkSF5npBNrwyrHNqElwyjcFvdnQu91luoecVowDqQFNTCbQAGvdmu E2ON0rFs6U8RBK907jQ7q8THKiNI+3Zqalxlna9nxbvgRXKp2yic/x3vzAqpYSVvPLf1 Zgek0DA5wUK1IvevfLDJvEWs/gMNDChk5P5P8= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=message-id:date:from:to:subject:in-reply-to:mime-version :content-type:content-transfer-encoding:content-disposition :references; b=tfWiC0+vDb5d6EHwmCNz3bqbBD15CceJ5ZKqV06+fQpy1kf9opiQWCjLAOCNDWkrEm W/Wtviw5qbDblKax5WzSSqiON9WXq25hPrIUj8fNW+VwsjO/j6sMMt0XXy1YaTnu1W4t bQ6RIP2G5ND2Da3OfMwIcA9lnao4acZjtoKaU= Received: by 10.181.21.2 with SMTP id y2mr9385703bki.144.1231433918191; Thu, 08 Jan 2009 08:58:38 -0800 (PST) Received: by 10.180.255.19 with HTTP; Thu, 8 Jan 2009 08:58:38 -0800 (PST) Message-ID: Date: Thu, 8 Jan 2009 18:58:38 +0200 From: "Ihar Hrachyshka" To: linux-mips@linux-mips.org Subject: Re: NXP STB225 board support In-Reply-To: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Content-Disposition: inline References: Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21690 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ihar.hrachyshka@gmail.com Precedence: bulk X-list: linux-mips On Tue, Dec 23, 2008 at 4:48 PM, Ihar Hrachyshka wrote: > Hello! > I try to start vanilla linux kernel on pnx-8335-stb225 board. What I did: > 1. ARCH=mips make pnx-8335-stb225_defconfig > 2. ARCH=mips make > 3. Prepared U-Boot image with mkimage. > > After booting it up I get the following output on my UART: > > Linux version 2.6.28-rc9.netflix.PR12_RC2 (booxter@EPBYMINW0568) (gcc > version 4.2.1) #3 PREEMPT Tue Dec 23 15:52:10 EET 2008 > CPU revision is: 00019068 (MIPS 4KEc) > Determined physical RAM map: > memory: 10000000 @ 00000000 (usable) > Zone PFN ranges: > Normal 0x00000000 -> 0x00010000 > Movable zone start PFN for each node > early_node_map[1] active PFN ranges > 0: 0x00000000 -> 0x00010000 > Built 1 zonelists in Zone order, mobility grouping on. Total pages: 65024 > Kernel command line: > mtdparts=gen_nand:128k(Boot0),1M(Boot1),512k(Env),4M(Kernel),16M(Filesystem) > ip3902.mac_address=00:60:37:03:00:00 ip=10.6.2.53:10.6.27.3 > Unknown boot option `ip3902.mac_address=00:60:37:03:00:00': ignoring > Primary instruction cache 16kB, VIPT, 2-way, linesize 16 bytes. > Primary data cache 8kB, 4-way, VIPT, no aliases, linesize 16 bytes > PID hash table entries: 1024 (order: 10, 4096 bytes) > CPU clock is 320 MHz > Console: colour dummy device 80x25 > console [ttyS0] enabled > > After this last message there is no any activity. It seems that kernel > hanged. What can I do to see what's going on (maybe stack trace)? Any > suggestions? > Has anyone started the board successfully with vanilla kernel? > > Thanks in advance, > Ihar Hrachyshka > Bisecting my Linus vanilla git, I found that the problem appeared after the following patch was applied: http://git.kernel.org/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commitdiff;h=566f74f6b2f8b85d5b8d6caaf97e5672cecd3e3e After reverting the patch, Linus vanilla git kernel again boots ok on the board. Please, take a look. From kevink@paralogos.com Thu Jan 8 19:23:42 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 08 Jan 2009 19:23:44 +0000 (GMT) Received: from aux-209-217-49-36.oklahoma.net ([209.217.49.36]:13326 "EHLO proteus.paralogos.com") by ftp.linux-mips.org with ESMTP id S21365018AbZAHTXm (ORCPT ); Thu, 8 Jan 2009 19:23:42 +0000 Received: from [192.168.236.58] ([217.109.65.213]) by proteus.paralogos.com (8.9.3/8.9.3) with ESMTP id NAA28505; Thu, 8 Jan 2009 13:54:37 -0600 Message-ID: <496652B7.60500@paralogos.com> Date: Thu, 08 Jan 2009 13:23:35 -0600 From: "Kevin D. Kissell" User-Agent: Thunderbird 2.0.0.19 (Windows/20081209) MIME-Version: 1.0 To: Ihar Hrachyshka CC: linux-mips@linux-mips.org Subject: Re: NXP STB225 board support References: In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21691 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: kevink@paralogos.com Precedence: bulk X-list: linux-mips Ihar Hrachyshka wrote: > > > Bisecting my Linus vanilla git, I found that the problem appeared > after the following patch was applied: > > http://git.kernel.org/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commitdiff;h=566f74f6b2f8b85d5b8d6caaf97e5672cecd3e3e > > After reverting the patch, Linus vanilla git kernel again boots ok on > the board. Please, take a look. Could one of the Cavium guys explain why the new code for V2 cores does "ebase += ..." and not "ebase = "? Kevin K. From Kenneth.Reese@caviumnetworks.com Thu Jan 8 19:35:09 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 08 Jan 2009 19:35:12 +0000 (GMT) Received: from mail3.caviumnetworks.com ([12.108.191.235]:62570 "EHLO mail3.caviumnetworks.com") by ftp.linux-mips.org with ESMTP id S21365010AbZAHTfJ (ORCPT ); Thu, 8 Jan 2009 19:35:09 +0000 Received: from exch4.caveonetworks.com (Not Verified[192.168.16.23]) by mail3.caviumnetworks.com with MailMarshal (v6,2,2,3503) id ; Thu, 08 Jan 2009 14:34:51 -0500 Received: from exch4.caveonetworks.com ([192.168.16.23]) by exch4.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Thu, 8 Jan 2009 11:34:41 -0800 Received: from [192.168.162.106] ([64.169.86.201]) by exch4.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Thu, 8 Jan 2009 11:34:41 -0800 Message-ID: <49665551.2050804@caviumnetworks.com> Date: Thu, 08 Jan 2009 11:34:41 -0800 From: Chad Reese User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.8.0.14eol) Gecko/20070505 Iceape/1.0.9 (Debian-1.0.13~pre080323b-0etch3) MIME-Version: 1.0 To: "Kevin D. Kissell" CC: Ihar Hrachyshka , linux-mips@linux-mips.org Subject: Re: NXP STB225 board support References: <496652B7.60500@paralogos.com> In-Reply-To: <496652B7.60500@paralogos.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 08 Jan 2009 19:34:41.0618 (UTC) FILETIME=[26DCEB20:01C971C8] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21692 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: kreese@caviumnetworks.com Precedence: bulk X-list: linux-mips Kevin D. Kissell wrote: > Ihar Hrachyshka wrote: > > > > > > Bisecting my Linus vanilla git, I found that the problem appeared > > after the following patch was applied: > > > > > http://git.kernel.org/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commitdiff;h=566f74f6b2f8b85d5b8d6caaf97e5672cecd3e3e > > > > After reverting the patch, Linus vanilla git kernel again boots ok on > > the board. Please, take a look. > > Could one of the Cavium guys explain why the new code for V2 cores does > "ebase += ..." and not "ebase = "? The value "(read_c0_ebase() & 0x3ffff000)" is a physical address and must be converted into Mips KSEG address by adding CAC_BASE. My guess is that something about the NXP STB225 isn't fully Mips r2 and doesn't implement the ebase register correctly. I'm afraid I don't know anything about that processor. Chad From David.Daney@caviumnetworks.com Thu Jan 8 19:43:04 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 08 Jan 2009 19:43:06 +0000 (GMT) Received: from mail3.caviumnetworks.com ([12.108.191.235]:25459 "EHLO mail3.caviumnetworks.com") by ftp.linux-mips.org with ESMTP id S21103357AbZAHTnE (ORCPT ); Thu, 8 Jan 2009 19:43:04 +0000 Received: from exch4.caveonetworks.com (Not Verified[192.168.16.23]) by mail3.caviumnetworks.com with MailMarshal (v6,2,2,3503) id ; Thu, 08 Jan 2009 14:42:51 -0500 Received: from exch4.caveonetworks.com ([192.168.16.23]) by exch4.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Thu, 8 Jan 2009 11:42:04 -0800 Received: from dd1.caveonetworks.com ([64.169.86.201]) by exch4.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Thu, 8 Jan 2009 11:42:04 -0800 Message-ID: <4966570C.9010300@caviumnetworks.com> Date: Thu, 08 Jan 2009 11:42:04 -0800 From: David Daney User-Agent: Thunderbird 2.0.0.19 (X11/20090105) MIME-Version: 1.0 To: "Kevin D. Kissell" CC: Ihar Hrachyshka , linux-mips@linux-mips.org Subject: Re: NXP STB225 board support References: <496652B7.60500@paralogos.com> In-Reply-To: <496652B7.60500@paralogos.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 08 Jan 2009 19:42:04.0635 (UTC) FILETIME=[2EEBF2B0:01C971C9] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21693 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Kevin D. Kissell wrote: > Ihar Hrachyshka wrote: > > > > > > Bisecting my Linus vanilla git, I found that the problem appeared > > after the following patch was applied: > > > > > http://git.kernel.org/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commitdiff;h=566f74f6b2f8b85d5b8d6caaf97e5672cecd3e3e > > > > > After reverting the patch, Linus vanilla git kernel again boots ok on > > the board. Please, take a look. > > Could one of the Cavium guys explain why the new code for V2 cores does > "ebase += ..." and not "ebase = "? > We need to add the offset to the proper segment (CAC_BASE). That said, the change to set_uncached_handler looks incorrect. It should be adding onto uncached_ebase not ebase. Someone should probably fix that. David Daney From David.Daney@caviumnetworks.com Thu Jan 8 20:23:15 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 08 Jan 2009 20:23:18 +0000 (GMT) Received: from smtp2.caviumnetworks.com ([209.113.159.134]:41989 "EHLO smtp2.caviumnetworks.com") by ftp.linux-mips.org with ESMTP id S21365031AbZAHUXP (ORCPT ); Thu, 8 Jan 2009 20:23:15 +0000 Received: from exch4.caveonetworks.com (Not Verified[192.168.16.23]) by smtp2.caviumnetworks.com with MailMarshal (v6,2,2,3503) id ; Thu, 08 Jan 2009 15:22:09 -0500 Received: from exch4.caveonetworks.com ([192.168.16.23]) by exch4.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Thu, 8 Jan 2009 12:21:26 -0800 Received: from dd1.caveonetworks.com ([64.169.86.201]) by exch4.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Thu, 8 Jan 2009 12:21:26 -0800 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.2/8.14.2) with ESMTP id n08KLNGw008473; Thu, 8 Jan 2009 12:21:23 -0800 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.2/8.14.2/Submit) id n08KLLLx008470; Thu, 8 Jan 2009 12:21:21 -0800 From: David Daney To: rusty@rustcorp.com.au, torvalds@linux-foundation.org Cc: linux-kernel@vger.kernel.org, linux-mips@linux-mips.org, David Daney Subject: [PATCH] cpumask fallout: Initialize irq_default_affinity earlier. Date: Thu, 8 Jan 2009 12:21:21 -0800 Message-Id: <1231446081-8448-1-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.5.6.6 X-OriginalArrivalTime: 08 Jan 2009 20:21:26.0317 (UTC) FILETIME=[AE9805D0:01C971CE] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21694 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Move the initialization of irq_default_affinity to early_irq_init as core_initcall is too late. irq_default_affinity can be used in init_IRQ and potentially timer and SMP init as well. All of these happen before core_initcall. Moving the initialization to early_irq_init ensures that it is initialized before it is used. Signed-off-by: David Daney --- Only tested on my mips/cavium_octeon port that (if the benevolent spirits are willing) will be pushed up from Ralf's linux-mips.org tree in the very near future. Also the tested configuration is without CONFIG_SPARSE_IRQ, so that was not tested, but it should be safe as it is the same code. kernel/irq/handle.c | 8 ++++++++ kernel/irq/internals.h | 4 ++++ kernel/irq/manage.c | 4 +--- 3 files changed, 13 insertions(+), 3 deletions(-) diff --git a/kernel/irq/handle.c b/kernel/irq/handle.c index c20db0b..54802ca 100644 --- a/kernel/irq/handle.c +++ b/kernel/irq/handle.c @@ -134,6 +134,10 @@ int __init early_irq_init(void) int legacy_count; int i; +#ifdef CONFIG_SMP + init_irq_default_affinity(); +#endif + desc = irq_desc_legacy; legacy_count = ARRAY_SIZE(irq_desc_legacy); @@ -219,6 +223,10 @@ int __init early_irq_init(void) int count; int i; +#ifdef CONFIG_SMP + init_irq_default_affinity(); +#endif + desc = irq_desc; count = ARRAY_SIZE(irq_desc); diff --git a/kernel/irq/internals.h b/kernel/irq/internals.h index e6d0a43..066ff94 100644 --- a/kernel/irq/internals.h +++ b/kernel/irq/internals.h @@ -32,6 +32,10 @@ static inline void unregister_handler_proc(unsigned int irq, extern int irq_select_affinity_usr(unsigned int irq); +#ifdef CONFIG_SMP +extern void init_irq_default_affinity(void); +#endif + /* * Debugging printout: */ diff --git a/kernel/irq/manage.c b/kernel/irq/manage.c index cd0cd8d..2f87aae 100644 --- a/kernel/irq/manage.c +++ b/kernel/irq/manage.c @@ -18,13 +18,11 @@ #ifdef CONFIG_SMP cpumask_var_t irq_default_affinity; -static int init_irq_default_affinity(void) +void __init init_irq_default_affinity(void) { alloc_cpumask_var(&irq_default_affinity, GFP_KERNEL); cpumask_setall(irq_default_affinity); - return 0; } -core_initcall(init_irq_default_affinity); /** * synchronize_irq - wait for pending IRQ handlers (on other CPUs) -- 1.5.6.6 From torvalds@linux-foundation.org Thu Jan 8 20:34:17 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 08 Jan 2009 20:34:19 +0000 (GMT) Received: from smtp1.linux-foundation.org ([140.211.169.13]:58752 "EHLO smtp1.linux-foundation.org") by ftp.linux-mips.org with ESMTP id S21365020AbZAHUeP (ORCPT ); Thu, 8 Jan 2009 20:34:15 +0000 Received: from imap1.linux-foundation.org (imap1.linux-foundation.org [140.211.169.55]) by smtp1.linux-foundation.org (8.14.2/8.13.5/Debian-3ubuntu1.1) with ESMTP id n08KXcKk029966 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Thu, 8 Jan 2009 12:33:39 -0800 Received: from localhost (localhost [127.0.0.1]) by imap1.linux-foundation.org (8.13.5.20060308/8.13.5/Debian-3ubuntu1.1) with ESMTP id n08KXcbH012826; Thu, 8 Jan 2009 12:33:38 -0800 Date: Thu, 8 Jan 2009 12:33:38 -0800 (PST) From: Linus Torvalds X-X-Sender: torvalds@localhost.localdomain To: David Daney cc: rusty@rustcorp.com.au, linux-kernel@vger.kernel.org, linux-mips@linux-mips.org Subject: Re: [PATCH] cpumask fallout: Initialize irq_default_affinity earlier. In-Reply-To: <1231446081-8448-1-git-send-email-ddaney@caviumnetworks.com> Message-ID: References: <1231446081-8448-1-git-send-email-ddaney@caviumnetworks.com> User-Agent: Alpine 2.00 (LFD 1167 2008-08-23) MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII X-MIMEDefang-Filter: lf$Revision: 1.188 $ X-Scanned-By: MIMEDefang 2.63 on 140.211.169.13 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21695 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: torvalds@linux-foundation.org Precedence: bulk X-list: linux-mips On Thu, 8 Jan 2009, David Daney wrote: > > +#ifdef CONFIG_SMP > + init_irq_default_affinity(); > +#endif Don't do this. It's horrible. It makes the code much harder to read. What's so wrong with initializing affinity on UP? It's still conceptually a fine thing to do, although it's obviously trivially a no-op. Also, since it's only used in "handle.c", why not just move it there? Then, just make it static, and make it a no-op for the non-SMP case. Ok? In fact, I think it already is a no-op in the UP case, and you can literally just do static inline void __init init_irq_default_affinity(void) { alloc_cpumask_var(&irq_default_affinity, GFP_KERNEL); cpumask_setall(irq_default_affinity); } and be done with it. I think it should all compile away to nothing if CONFIG_SMP isn't set. Linus From David.Daney@caviumnetworks.com Thu Jan 8 20:50:49 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 08 Jan 2009 20:50:51 +0000 (GMT) Received: from mail3.caviumnetworks.com ([12.108.191.235]:729 "EHLO mail3.caviumnetworks.com") by ftp.linux-mips.org with ESMTP id S21365020AbZAHUut (ORCPT ); Thu, 8 Jan 2009 20:50:49 +0000 Received: from exch4.caveonetworks.com (Not Verified[192.168.16.23]) by mail3.caviumnetworks.com with MailMarshal (v6,2,2,3503) id ; Thu, 08 Jan 2009 15:50:03 -0500 Received: from exch4.caveonetworks.com ([192.168.16.23]) by exch4.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Thu, 8 Jan 2009 12:49:18 -0800 Received: from dd1.caveonetworks.com ([64.169.86.201]) by exch4.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Thu, 8 Jan 2009 12:49:18 -0800 Message-ID: <496666CE.3050205@caviumnetworks.com> Date: Thu, 08 Jan 2009 12:49:18 -0800 From: David Daney User-Agent: Thunderbird 2.0.0.19 (X11/20090105) MIME-Version: 1.0 To: Linus Torvalds CC: rusty@rustcorp.com.au, linux-kernel@vger.kernel.org, linux-mips@linux-mips.org Subject: Re: [PATCH] cpumask fallout: Initialize irq_default_affinity earlier. References: <1231446081-8448-1-git-send-email-ddaney@caviumnetworks.com> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 08 Jan 2009 20:49:18.0545 (UTC) FILETIME=[9351C410:01C971D2] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21696 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Linus Torvalds wrote: [...] > In fact, I think it already is a no-op in the UP case, and you can > literally just do > > static inline void __init init_irq_default_affinity(void) > { > alloc_cpumask_var(&irq_default_affinity, GFP_KERNEL); > cpumask_setall(irq_default_affinity); > } > > and be done with it. I think it should all compile away to nothing if > CONFIG_SMP isn't set. The 'inline' seems gratuitous to me. Since it is static GCC should do the Right Thing. However since you suggested it, I am testing it that way. David Daney From torvalds@linux-foundation.org Thu Jan 8 20:57:08 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 08 Jan 2009 20:57:10 +0000 (GMT) Received: from smtp1.linux-foundation.org ([140.211.169.13]:3496 "EHLO smtp1.linux-foundation.org") by ftp.linux-mips.org with ESMTP id S21365037AbZAHU5I (ORCPT ); Thu, 8 Jan 2009 20:57:08 +0000 Received: from imap1.linux-foundation.org (imap1.linux-foundation.org [140.211.169.55]) by smtp1.linux-foundation.org (8.14.2/8.13.5/Debian-3ubuntu1.1) with ESMTP id n08Kv08T031699 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Thu, 8 Jan 2009 12:57:01 -0800 Received: from localhost (localhost [127.0.0.1]) by imap1.linux-foundation.org (8.13.5.20060308/8.13.5/Debian-3ubuntu1.1) with ESMTP id n08Kux7v032239; Thu, 8 Jan 2009 12:56:59 -0800 Date: Thu, 8 Jan 2009 12:56:59 -0800 (PST) From: Linus Torvalds X-X-Sender: torvalds@localhost.localdomain To: David Daney cc: rusty@rustcorp.com.au, linux-kernel@vger.kernel.org, linux-mips@linux-mips.org Subject: Re: [PATCH] cpumask fallout: Initialize irq_default_affinity earlier. In-Reply-To: <496666CE.3050205@caviumnetworks.com> Message-ID: References: <1231446081-8448-1-git-send-email-ddaney@caviumnetworks.com> <496666CE.3050205@caviumnetworks.com> User-Agent: Alpine 2.00 (LFD 1167 2008-08-23) MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII X-MIMEDefang-Filter: lf$Revision: 1.188 $ X-Scanned-By: MIMEDefang 2.63 on 140.211.169.13 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21697 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: torvalds@linux-foundation.org Precedence: bulk X-list: linux-mips On Thu, 8 Jan 2009, David Daney wrote: > > The 'inline' seems gratuitous to me. Since it is static GCC should do > the Right Thing. However since you suggested it, I am testing it that > way. Trust me, gcc very seldom does the Right Thing(tm) when it comes to inlining. Linus From travis@sgi.com Thu Jan 8 21:25:55 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 08 Jan 2009 21:25:57 +0000 (GMT) Received: from relay1.sgi.com ([192.48.179.29]:29374 "EHLO relay.sgi.com") by ftp.linux-mips.org with ESMTP id S21365035AbZAHVZz (ORCPT ); Thu, 8 Jan 2009 21:25:55 +0000 Received: from cthulhu.engr.sgi.com (cthulhu.engr.sgi.com [150.166.39.100]) by relay1.corp.sgi.com (Postfix) with ESMTP id AB64F8F80A5; Thu, 8 Jan 2009 13:25:48 -0800 (PST) Received: from [134.15.31.35] (vpn-2-travis.corp.sgi.com [134.15.31.35]) by cthulhu.engr.sgi.com (8.12.10/8.12.10/SuSE Linux 0.7) with ESMTP id n08LPlF5029428; Thu, 8 Jan 2009 13:25:47 -0800 Message-ID: <49666F5B.2090605@sgi.com> Date: Thu, 08 Jan 2009 13:25:47 -0800 From: Mike Travis User-Agent: Thunderbird 2.0.0.6 (X11/20070801) MIME-Version: 1.0 To: David Daney CC: Linus Torvalds , rusty@rustcorp.com.au, linux-kernel@vger.kernel.org, linux-mips@linux-mips.org Subject: Re: [PATCH] cpumask fallout: Initialize irq_default_affinity earlier. References: <1231446081-8448-1-git-send-email-ddaney@caviumnetworks.com> <496666CE.3050205@caviumnetworks.com> In-Reply-To: <496666CE.3050205@caviumnetworks.com> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21698 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: travis@sgi.com Precedence: bulk X-list: linux-mips David Daney wrote: > Linus Torvalds wrote: > [...] >> In fact, I think it already is a no-op in the UP case, and you can >> literally just do >> >> static inline void __init init_irq_default_affinity(void) >> { >> alloc_cpumask_var(&irq_default_affinity, GFP_KERNEL); >> cpumask_setall(irq_default_affinity); >> } >> >> and be done with it. I think it should all compile away to nothing if >> CONFIG_SMP isn't set. > > The 'inline' seems gratuitous to me. Since it is static GCC should do > the Right Thing. However since you suggested it, I am testing it that way. > > David Daney It will probably need to be: alloc_bootmem_cpumask_var(&irq_default_affinity); I am testing it on x86_64 as well. Thanks, Mike From David.Daney@caviumnetworks.com Thu Jan 8 22:54:27 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 08 Jan 2009 22:54:29 +0000 (GMT) Received: from mail3.caviumnetworks.com ([12.108.191.235]:52887 "EHLO mail3.caviumnetworks.com") by ftp.linux-mips.org with ESMTP id S21365046AbZAHWy1 (ORCPT ); Thu, 8 Jan 2009 22:54:27 +0000 Received: from exch4.caveonetworks.com (Not Verified[192.168.16.23]) by mail3.caviumnetworks.com with MailMarshal (v6,2,2,3503) id ; Thu, 08 Jan 2009 17:53:38 -0500 Received: from exch4.caveonetworks.com ([192.168.16.23]) by exch4.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Thu, 8 Jan 2009 14:53:04 -0800 Received: from dd1.caveonetworks.com ([64.169.86.201]) by exch4.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Thu, 8 Jan 2009 14:53:04 -0800 Message-ID: <496683D0.6000509@caviumnetworks.com> Date: Thu, 08 Jan 2009 14:53:04 -0800 From: David Daney User-Agent: Thunderbird 2.0.0.19 (X11/20090105) MIME-Version: 1.0 To: Linus Torvalds , Rusty Russell CC: Linux Kernel Mailing List , Mike Travis , linux-mips Subject: [PATCH 0/2] cpumask fallout: Initialize irq_default_affinity earlier et al. Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 08 Jan 2009 22:53:04.0638 (UTC) FILETIME=[DD9DA1E0:01C971E3] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21699 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips As I said in 2/2: Move the initialization of irq_default_affinity to early_irq_init as core_initcall is too late. irq_default_affinity can be used in init_IRQ and potentially timer and SMP init as well. All of these happen before core_initcall. Moving the initialization to early_irq_init ensures that it is initialized before it is used. Mike Travis pointed out that irq_default_affinity depends on CONFIG_GENERIC_HARDIRQS in addition to CONFIG_SMP. So to make things consistent, I added 1/2 so that the irq_*_affinity functions and irq_default_affinity are defined for the same conditions that they are declared. I Took Linus' suggestion to move init_irq_default_affinity over to kernel/irq/handle.c, however due to the way that cpumask_*() are defined, it is still necessary to have the ugly ifdefs, but now they are localized to init_irq_default_affinity. Mike Travis also suggested that alloc_bootmem_cpumask_var() be used in preference to alloc_cpumask_var, so I incorporated that suggestion as well. I tested both with and without CONFIG_SMP, on mips/cavium_octeon, Mike tested a similar(but not identical patch) on x86_64. I will reply with the two patches. David Daney (2): Make irq_*_affinity depend on CONFIG_GENERIC_HARDIRQS too. cpumask fallout: Initialize irq_default_affinity earlier (v2). kernel/irq/handle.c | 12 ++++++++++++ kernel/irq/manage.c | 10 +--------- 2 files changed, 13 insertions(+), 9 deletions(-) From David.Daney@caviumnetworks.com Thu Jan 8 22:56:34 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 08 Jan 2009 22:56:36 +0000 (GMT) Received: from mail3.caviumnetworks.com ([12.108.191.235]:39321 "EHLO mail3.caviumnetworks.com") by ftp.linux-mips.org with ESMTP id S21365046AbZAHW4e (ORCPT ); Thu, 8 Jan 2009 22:56:34 +0000 Received: from exch4.caveonetworks.com (Not Verified[192.168.16.23]) by mail3.caviumnetworks.com with MailMarshal (v6,2,2,3503) id ; Thu, 08 Jan 2009 17:55:54 -0500 Received: from exch4.caveonetworks.com ([192.168.16.23]) by exch4.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Thu, 8 Jan 2009 14:55:49 -0800 Received: from dd1.caveonetworks.com ([64.169.86.201]) by exch4.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Thu, 8 Jan 2009 14:55:49 -0800 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.2/8.14.2) with ESMTP id n08MtlZx029481; Thu, 8 Jan 2009 14:55:47 -0800 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.2/8.14.2/Submit) id n08Mtka5029480; Thu, 8 Jan 2009 14:55:46 -0800 From: David Daney To: rusty@rustcorp.com.au, torvalds@linux-foundation.org Cc: linux-kernel@vger.kernel.org, linux-mips@linux-mips.org, travis@sgi.com, David Daney Subject: [PATCH 2/2] cpumask fallout: Initialize irq_default_affinity earlier (v2). Date: Thu, 8 Jan 2009 14:55:45 -0800 Message-Id: <1231455345-29453-2-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.5.6.6 In-Reply-To: <496683D0.6000509@caviumnetworks.com> References: <496683D0.6000509@caviumnetworks.com> X-OriginalArrivalTime: 08 Jan 2009 22:55:49.0635 (UTC) FILETIME=[3FF62D30:01C971E4] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21700 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Move the initialization of irq_default_affinity to early_irq_init as core_initcall is too late. irq_default_affinity can be used in init_IRQ and potentially timer and SMP init as well. All of these happen before core_initcall. Moving the initialization to early_irq_init ensures that it is initialized before it is used. Signed-off-by: David Daney --- kernel/irq/handle.c | 12 ++++++++++++ kernel/irq/manage.c | 8 -------- 2 files changed, 12 insertions(+), 8 deletions(-) diff --git a/kernel/irq/handle.c b/kernel/irq/handle.c index c20db0b..a9fbb01 100644 --- a/kernel/irq/handle.c +++ b/kernel/irq/handle.c @@ -39,6 +39,14 @@ void handle_bad_irq(unsigned int irq, struct irq_desc *desc) ack_bad_irq(irq); } +static inline void __init init_irq_default_affinity(void) +{ +#if defined(CONFIG_SMP) && defined(CONFIG_GENERIC_HARDIRQS) + alloc_bootmem_cpumask_var(&irq_default_affinity); + cpumask_setall(irq_default_affinity); +#endif +} + /* * Linux has a controller-independent interrupt architecture. * Every controller has a 'controller-template', that is used @@ -134,6 +142,8 @@ int __init early_irq_init(void) int legacy_count; int i; + init_irq_default_affinity(); + desc = irq_desc_legacy; legacy_count = ARRAY_SIZE(irq_desc_legacy); @@ -219,6 +229,8 @@ int __init early_irq_init(void) int count; int i; + init_irq_default_affinity(); + desc = irq_desc; count = ARRAY_SIZE(irq_desc); diff --git a/kernel/irq/manage.c b/kernel/irq/manage.c index 618a64f..291f036 100644 --- a/kernel/irq/manage.c +++ b/kernel/irq/manage.c @@ -18,14 +18,6 @@ #if defined(CONFIG_SMP) && defined(CONFIG_GENERIC_HARDIRQS) cpumask_var_t irq_default_affinity; -static int init_irq_default_affinity(void) -{ - alloc_cpumask_var(&irq_default_affinity, GFP_KERNEL); - cpumask_setall(irq_default_affinity); - return 0; -} -core_initcall(init_irq_default_affinity); - /** * synchronize_irq - wait for pending IRQ handlers (on other CPUs) * @irq: interrupt number to wait for -- 1.5.6.6 From David.Daney@caviumnetworks.com Thu Jan 8 22:56:53 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 08 Jan 2009 22:56:56 +0000 (GMT) Received: from mail3.caviumnetworks.com ([12.108.191.235]:39065 "EHLO mail3.caviumnetworks.com") by ftp.linux-mips.org with ESMTP id S21365048AbZAHW4e (ORCPT ); Thu, 8 Jan 2009 22:56:34 +0000 Received: from exch4.caveonetworks.com (Not Verified[192.168.16.23]) by mail3.caviumnetworks.com with MailMarshal (v6,2,2,3503) id ; Thu, 08 Jan 2009 17:55:59 -0500 Received: from exch4.caveonetworks.com ([192.168.16.23]) by exch4.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Thu, 8 Jan 2009 14:55:49 -0800 Received: from dd1.caveonetworks.com ([64.169.86.201]) by exch4.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Thu, 8 Jan 2009 14:55:49 -0800 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.2/8.14.2) with ESMTP id n08MtkCd029477; Thu, 8 Jan 2009 14:55:46 -0800 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.2/8.14.2/Submit) id n08MtjO3029475; Thu, 8 Jan 2009 14:55:45 -0800 From: David Daney To: rusty@rustcorp.com.au, torvalds@linux-foundation.org Cc: linux-kernel@vger.kernel.org, linux-mips@linux-mips.org, travis@sgi.com, David Daney Subject: [PATCH 1/2] Make irq_*_affinity depend on CONFIG_GENERIC_HARDIRQS too. Date: Thu, 8 Jan 2009 14:55:44 -0800 Message-Id: <1231455345-29453-1-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.5.6.6 In-Reply-To: <496683D0.6000509@caviumnetworks.com> References: <496683D0.6000509@caviumnetworks.com> X-OriginalArrivalTime: 08 Jan 2009 22:55:49.0635 (UTC) FILETIME=[3FF62D30:01C971E4] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21701 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips In interrupt.h these functions are declared only if CONFIG_GENERIC_HARDIRQS is set. We should define them under identical conditions. Signed-off-by: David Daney --- kernel/irq/manage.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/kernel/irq/manage.c b/kernel/irq/manage.c index cd0cd8d..618a64f 100644 --- a/kernel/irq/manage.c +++ b/kernel/irq/manage.c @@ -15,7 +15,7 @@ #include "internals.h" -#ifdef CONFIG_SMP +#if defined(CONFIG_SMP) && defined(CONFIG_GENERIC_HARDIRQS) cpumask_var_t irq_default_affinity; static int init_irq_default_affinity(void) -- 1.5.6.6 From ihar.hrachyshka@gmail.com Thu Jan 8 23:04:31 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 08 Jan 2009 23:04:33 +0000 (GMT) Received: from mail-bw0-f13.google.com ([209.85.218.13]:18394 "EHLO mail-bw0-f13.google.com") by ftp.linux-mips.org with ESMTP id S21365068AbZAHXEb (ORCPT ); Thu, 8 Jan 2009 23:04:31 +0000 Received: by bwz6 with SMTP id 6so24578567bwz.0 for ; Thu, 08 Jan 2009 15:04:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:message-id:date:from:to :subject:cc:in-reply-to:mime-version:content-type :content-transfer-encoding:content-disposition:references; bh=eASU8P5nK7k3iz8ta0J02HsvqsNMXJBkx/zsSGS8dk8=; b=TI4THdvC/JUm9rx/U3b4h5d6u9Lva8CDJ3eJIBxF5ZVwcs7kI8pFntwhHxAGaLw0zn jU2tm9Qp7dqwcXghT0Ac6QD6t1+RYMtzig0hrmC1yeeAvdD4Ng4aeO4jLdzR5YQK1Llm dpmE/Us22hK84P9HMtTVoczN4AsyUkhzJyd2o= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=message-id:date:from:to:subject:cc:in-reply-to:mime-version :content-type:content-transfer-encoding:content-disposition :references; b=tEVtRW4zkDaIv8PkKmMsvj+NGjE8zqh854B5quEaCSqF5ooBPreuDHn4oTSDLzKJ66 BOIUc3a1fIAQblFrGQT63X3Pwl3rTLv82I2FGB+eRtdiqhdHFyuNnsgyjCoNJFAOpoFg OBsd69TEmLMBkhw3cGeVSLhQrPfgwOOQ9UIFE= Received: by 10.181.148.2 with SMTP id a2mr9490848bko.117.1231455864721; Thu, 08 Jan 2009 15:04:24 -0800 (PST) Received: by 10.180.255.19 with HTTP; Thu, 8 Jan 2009 15:04:24 -0800 (PST) Message-ID: Date: Fri, 9 Jan 2009 01:04:24 +0200 From: "Ihar Hrachyshka" To: "David Daney" Subject: Re: [PATCH 2/2] cpumask fallout: Initialize irq_default_affinity earlier (v2). Cc: rusty@rustcorp.com.au, torvalds@linux-foundation.org, linux-kernel@vger.kernel.org, linux-mips@linux-mips.org, travis@sgi.com In-Reply-To: <1231455345-29453-2-git-send-email-ddaney@caviumnetworks.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Content-Disposition: inline References: <496683D0.6000509@caviumnetworks.com> <1231455345-29453-2-git-send-email-ddaney@caviumnetworks.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21702 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ihar.hrachyshka@gmail.com Precedence: bulk X-list: linux-mips #ifdef X void func(args) { operation(); } #else void func(args) { } #endif is better than: void func(args) { #ifdef X operation(); #endif } IMHO. On Fri, Jan 9, 2009 at 12:55 AM, David Daney wrote: > Move the initialization of irq_default_affinity to early_irq_init as > core_initcall is too late. > > irq_default_affinity can be used in init_IRQ and potentially timer and > SMP init as well. All of these happen before core_initcall. Moving > the initialization to early_irq_init ensures that it is initialized > before it is used. > > Signed-off-by: David Daney > --- > kernel/irq/handle.c | 12 ++++++++++++ > kernel/irq/manage.c | 8 -------- > 2 files changed, 12 insertions(+), 8 deletions(-) > > diff --git a/kernel/irq/handle.c b/kernel/irq/handle.c > index c20db0b..a9fbb01 100644 > --- a/kernel/irq/handle.c > +++ b/kernel/irq/handle.c > @@ -39,6 +39,14 @@ void handle_bad_irq(unsigned int irq, struct irq_desc *desc) > ack_bad_irq(irq); > } > > +static inline void __init init_irq_default_affinity(void) > +{ > +#if defined(CONFIG_SMP) && defined(CONFIG_GENERIC_HARDIRQS) > + alloc_bootmem_cpumask_var(&irq_default_affinity); > + cpumask_setall(irq_default_affinity); > +#endif > +} > + > /* > * Linux has a controller-independent interrupt architecture. > * Every controller has a 'controller-template', that is used > @@ -134,6 +142,8 @@ int __init early_irq_init(void) > int legacy_count; > int i; > > + init_irq_default_affinity(); > + > desc = irq_desc_legacy; > legacy_count = ARRAY_SIZE(irq_desc_legacy); > > @@ -219,6 +229,8 @@ int __init early_irq_init(void) > int count; > int i; > > + init_irq_default_affinity(); > + > desc = irq_desc; > count = ARRAY_SIZE(irq_desc); > > diff --git a/kernel/irq/manage.c b/kernel/irq/manage.c > index 618a64f..291f036 100644 > --- a/kernel/irq/manage.c > +++ b/kernel/irq/manage.c > @@ -18,14 +18,6 @@ > #if defined(CONFIG_SMP) && defined(CONFIG_GENERIC_HARDIRQS) > cpumask_var_t irq_default_affinity; > > -static int init_irq_default_affinity(void) > -{ > - alloc_cpumask_var(&irq_default_affinity, GFP_KERNEL); > - cpumask_setall(irq_default_affinity); > - return 0; > -} > -core_initcall(init_irq_default_affinity); > - > /** > * synchronize_irq - wait for pending IRQ handlers (on other CPUs) > * @irq: interrupt number to wait for > -- > 1.5.6.6 > > > From travis@sgi.com Thu Jan 8 23:11:30 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 08 Jan 2009 23:11:32 +0000 (GMT) Received: from relay2.sgi.com ([192.48.179.30]:17311 "EHLO relay.sgi.com") by ftp.linux-mips.org with ESMTP id S21365051AbZAHXL2 (ORCPT ); Thu, 8 Jan 2009 23:11:28 +0000 Received: from cthulhu.engr.sgi.com (cthulhu.engr.sgi.com [150.166.39.100]) by relay2.corp.sgi.com (Postfix) with ESMTP id 9E1A930405F; Thu, 8 Jan 2009 15:11:21 -0800 (PST) Received: from [134.15.31.35] (vpn-2-travis.corp.sgi.com [134.15.31.35]) by cthulhu.engr.sgi.com (8.12.10/8.12.10/SuSE Linux 0.7) with ESMTP id n08NBKF5007087; Thu, 8 Jan 2009 15:11:20 -0800 Message-ID: <49668818.1060900@sgi.com> Date: Thu, 08 Jan 2009 15:11:20 -0800 From: Mike Travis User-Agent: Thunderbird 2.0.0.6 (X11/20070801) MIME-Version: 1.0 To: David Daney CC: rusty@rustcorp.com.au, torvalds@linux-foundation.org, linux-kernel@vger.kernel.org, linux-mips@linux-mips.org, Ingo Molnar Subject: Re: [PATCH 2/2] cpumask fallout: Initialize irq_default_affinity earlier (v2). References: <496683D0.6000509@caviumnetworks.com> <1231455345-29453-2-git-send-email-ddaney@caviumnetworks.com> In-Reply-To: <1231455345-29453-2-git-send-email-ddaney@caviumnetworks.com> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21703 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: travis@sgi.com Precedence: bulk X-list: linux-mips It's essentially the same as I tested on x86_64 so you can add my Acked-by: Mike Travis Thanks! Mike David Daney wrote: > Move the initialization of irq_default_affinity to early_irq_init as > core_initcall is too late. > > irq_default_affinity can be used in init_IRQ and potentially timer and > SMP init as well. All of these happen before core_initcall. Moving > the initialization to early_irq_init ensures that it is initialized > before it is used. > > Signed-off-by: David Daney > --- > kernel/irq/handle.c | 12 ++++++++++++ > kernel/irq/manage.c | 8 -------- > 2 files changed, 12 insertions(+), 8 deletions(-) > > diff --git a/kernel/irq/handle.c b/kernel/irq/handle.c > index c20db0b..a9fbb01 100644 > --- a/kernel/irq/handle.c > +++ b/kernel/irq/handle.c > @@ -39,6 +39,14 @@ void handle_bad_irq(unsigned int irq, struct irq_desc *desc) > ack_bad_irq(irq); > } > > +static inline void __init init_irq_default_affinity(void) > +{ > +#if defined(CONFIG_SMP) && defined(CONFIG_GENERIC_HARDIRQS) > + alloc_bootmem_cpumask_var(&irq_default_affinity); > + cpumask_setall(irq_default_affinity); > +#endif > +} > + > /* > * Linux has a controller-independent interrupt architecture. > * Every controller has a 'controller-template', that is used > @@ -134,6 +142,8 @@ int __init early_irq_init(void) > int legacy_count; > int i; > > + init_irq_default_affinity(); > + > desc = irq_desc_legacy; > legacy_count = ARRAY_SIZE(irq_desc_legacy); > > @@ -219,6 +229,8 @@ int __init early_irq_init(void) > int count; > int i; > > + init_irq_default_affinity(); > + > desc = irq_desc; > count = ARRAY_SIZE(irq_desc); > > diff --git a/kernel/irq/manage.c b/kernel/irq/manage.c > index 618a64f..291f036 100644 > --- a/kernel/irq/manage.c > +++ b/kernel/irq/manage.c > @@ -18,14 +18,6 @@ > #if defined(CONFIG_SMP) && defined(CONFIG_GENERIC_HARDIRQS) > cpumask_var_t irq_default_affinity; > > -static int init_irq_default_affinity(void) > -{ > - alloc_cpumask_var(&irq_default_affinity, GFP_KERNEL); > - cpumask_setall(irq_default_affinity); > - return 0; > -} > -core_initcall(init_irq_default_affinity); > - > /** > * synchronize_irq - wait for pending IRQ handlers (on other CPUs) > * @irq: interrupt number to wait for From David.Daney@caviumnetworks.com Fri Jan 9 00:47:33 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 09 Jan 2009 00:47:39 +0000 (GMT) Received: from mail3.caviumnetworks.com ([12.108.191.235]:38973 "EHLO mail3.caviumnetworks.com") by ftp.linux-mips.org with ESMTP id S21102853AbZAIArd (ORCPT ); Fri, 9 Jan 2009 00:47:33 +0000 Received: from exch4.caveonetworks.com (Not Verified[192.168.16.23]) by mail3.caviumnetworks.com with MailMarshal (v6,2,2,3503) id ; Thu, 08 Jan 2009 19:47:13 -0500 Received: from exch4.caveonetworks.com ([192.168.16.23]) by exch4.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Thu, 8 Jan 2009 16:46:43 -0800 Received: from dd1.caveonetworks.com ([64.169.86.201]) by exch4.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Thu, 8 Jan 2009 16:46:43 -0800 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.2/8.14.2) with ESMTP id n090kfbP000359; Thu, 8 Jan 2009 16:46:41 -0800 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.2/8.14.2/Submit) id n090kfY2000357; Thu, 8 Jan 2009 16:46:41 -0800 From: David Daney To: linux-mips@linux-mips.org Cc: David Daney , Tomaso Paoletti Subject: [PATCH 03/20] MIPS: Add Cavium OCTEON processor support files to arch/mips/cavium-octeon. Date: Thu, 8 Jan 2009 16:46:40 -0800 Message-Id: <1231462000-334-1-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.5.6.6 X-OriginalArrivalTime: 09 Jan 2009 00:46:43.0675 (UTC) FILETIME=[BE141AB0:01C971F3] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21704 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips These are the rest of the new files needed to add OCTEON processor support to the Linux kernel. Other than Makefile and Kconfig which should be obvious, we have: csrc-octeon.c -- Clock source driver for OCTEON. dma-octeon.c -- Helper functions for mapping DMA memory. flash_setup.c -- Register on-board flash with the MTD subsystem. octeon-irq.c -- OCTEON interrupt controller managment. octeon-memcpy.S -- Optimized memcpy() implementation. serial.c -- Register 8250 platform driver and early console. setup.c -- Early architecture initialization. smp.c -- OCTEON SMP support. octeon_switch.S -- Scheduler context switch for OCTEON. c-octeon.c -- OCTEON cache controller support. cex-oct.S -- OCTEON cache exception handler. asm/mach-cavium-octeon/*.h -- Architecture include files. Signed-off-by: Tomaso Paoletti Signed-off-by: David Daney --- This is the second update of the original 03/20. Changes from the original are: * Improve octeon_init_cvmcount in csrc-octeon.c * Remove some unused PCI code in setup.c * Set more cpu_has_* values in cpu-feature-overrides.h * Fix comment in irq.h * Update for cpumask changes in 2.6.28-git9 This patch and the revised 02/20 (Message-Id: <1230074534-20664-1-git-send-email-ddaney@caviumnetworks.com>) should replace the corresponding files from the original 20 patch set. arch/mips/cavium-octeon/Kconfig | 85 ++ arch/mips/cavium-octeon/Makefile | 16 + arch/mips/cavium-octeon/csrc-octeon.c | 58 ++ arch/mips/cavium-octeon/dma-octeon.c | 32 + arch/mips/cavium-octeon/flash_setup.c | 84 ++ arch/mips/cavium-octeon/octeon-irq.c | 497 +++++++++++ arch/mips/cavium-octeon/octeon-memcpy.S | 521 +++++++++++ arch/mips/cavium-octeon/serial.c | 136 +++ arch/mips/cavium-octeon/setup.c | 929 ++++++++++++++++++++ arch/mips/cavium-octeon/smp.c | 211 +++++ .../asm/mach-cavium-octeon/cpu-feature-overrides.h | 78 ++ .../include/asm/mach-cavium-octeon/dma-coherence.h | 64 ++ arch/mips/include/asm/mach-cavium-octeon/irq.h | 244 +++++ .../asm/mach-cavium-octeon/kernel-entry-init.h | 131 +++ arch/mips/include/asm/mach-cavium-octeon/war.h | 26 + arch/mips/include/asm/octeon/octeon.h | 248 ++++++ arch/mips/kernel/octeon_switch.S | 506 +++++++++++ arch/mips/mm/c-octeon.c | 307 +++++++ arch/mips/mm/cex-oct.S | 70 ++ 19 files changed, 4243 insertions(+), 0 deletions(-) create mode 100644 arch/mips/cavium-octeon/Kconfig create mode 100644 arch/mips/cavium-octeon/Makefile create mode 100644 arch/mips/cavium-octeon/csrc-octeon.c create mode 100644 arch/mips/cavium-octeon/dma-octeon.c create mode 100644 arch/mips/cavium-octeon/flash_setup.c create mode 100644 arch/mips/cavium-octeon/octeon-irq.c create mode 100644 arch/mips/cavium-octeon/octeon-memcpy.S create mode 100644 arch/mips/cavium-octeon/serial.c create mode 100644 arch/mips/cavium-octeon/setup.c create mode 100644 arch/mips/cavium-octeon/smp.c create mode 100644 arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h create mode 100644 arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h create mode 100644 arch/mips/include/asm/mach-cavium-octeon/irq.h create mode 100644 arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h create mode 100644 arch/mips/include/asm/mach-cavium-octeon/war.h create mode 100644 arch/mips/include/asm/octeon/octeon.h create mode 100644 arch/mips/kernel/octeon_switch.S create mode 100644 arch/mips/mm/c-octeon.c create mode 100644 arch/mips/mm/cex-oct.S diff --git a/arch/mips/cavium-octeon/Kconfig b/arch/mips/cavium-octeon/Kconfig new file mode 100644 index 0000000..094c17e --- /dev/null +++ b/arch/mips/cavium-octeon/Kconfig @@ -0,0 +1,85 @@ +config CAVIUM_OCTEON_SPECIFIC_OPTIONS + bool "Enable Octeon specific options" + depends on CPU_CAVIUM_OCTEON + default "y" + +config CAVIUM_OCTEON_2ND_KERNEL + bool "Build the kernel to be used as a 2nd kernel on the same chip" + depends on CAVIUM_OCTEON_SPECIFIC_OPTIONS + default "n" + help + This option configures this kernel to be linked at a different + address and use the 2nd uart for output. This allows a kernel built + with this option to be run at the same time as one built without this + option. + +config CAVIUM_OCTEON_HW_FIX_UNALIGNED + bool "Enable hardware fixups of unaligned loads and stores" + depends on CAVIUM_OCTEON_SPECIFIC_OPTIONS + default "y" + help + Configure the Octeon hardware to automatically fix unaligned loads + and stores. Normally unaligned accesses are fixed using a kernel + exception handler. This option enables the hardware automatic fixups, + which requires only an extra 3 cycles. Disable this option if you + are running code that relies on address exceptions on unaligned + accesses. + +config CAVIUM_OCTEON_CVMSEG_SIZE + int "Number of L1 cache lines reserved for CVMSEG memory" + depends on CAVIUM_OCTEON_SPECIFIC_OPTIONS + range 0 54 + default 1 + help + CVMSEG LM is a segment that accesses portions of the dcache as a + local memory; the larger CVMSEG is, the smaller the cache is. + This selects the size of CVMSEG LM, which is in cache blocks. The + legally range is from zero to 54 cache blocks (i.e. CVMSEG LM is + between zero and 6192 bytes). + +config CAVIUM_OCTEON_LOCK_L2 + bool "Lock often used kernel code in the L2" + depends on CAVIUM_OCTEON_SPECIFIC_OPTIONS + default "y" + help + Enable locking parts of the kernel into the L2 cache. + +config CAVIUM_OCTEON_LOCK_L2_TLB + bool "Lock the TLB handler in L2" + depends on CAVIUM_OCTEON_LOCK_L2 + default "y" + help + Lock the low level TLB fast path into L2. + +config CAVIUM_OCTEON_LOCK_L2_EXCEPTION + bool "Lock the exception handler in L2" + depends on CAVIUM_OCTEON_LOCK_L2 + default "y" + help + Lock the low level exception handler into L2. + +config CAVIUM_OCTEON_LOCK_L2_LOW_LEVEL_INTERRUPT + bool "Lock the interrupt handler in L2" + depends on CAVIUM_OCTEON_LOCK_L2 + default "y" + help + Lock the low level interrupt handler into L2. + +config CAVIUM_OCTEON_LOCK_L2_INTERRUPT + bool "Lock the 2nd level interrupt handler in L2" + depends on CAVIUM_OCTEON_LOCK_L2 + default "y" + help + Lock the 2nd level interrupt handler in L2. + +config CAVIUM_OCTEON_LOCK_L2_MEMCPY + bool "Lock memcpy() in L2" + depends on CAVIUM_OCTEON_LOCK_L2 + default "y" + help + Lock the kernel's implementation of memcpy() into L2. + +config ARCH_SPARSEMEM_ENABLE + def_bool y + select SPARSEMEM_STATIC + depends on CPU_CAVIUM_OCTEON diff --git a/arch/mips/cavium-octeon/Makefile b/arch/mips/cavium-octeon/Makefile new file mode 100644 index 0000000..1c2a7fa --- /dev/null +++ b/arch/mips/cavium-octeon/Makefile @@ -0,0 +1,16 @@ +# +# Makefile for the Cavium Octeon specific kernel interface routines +# under Linux. +# +# This file is subject to the terms and conditions of the GNU General Public +# License. See the file "COPYING" in the main directory of this archive +# for more details. +# +# Copyright (C) 2005-2008 Cavium Networks +# + +obj-y := setup.o serial.o octeon-irq.o csrc-octeon.o +obj-y += dma-octeon.o flash_setup.o +obj-y += octeon-memcpy.o + +obj-$(CONFIG_SMP) += smp.o diff --git a/arch/mips/cavium-octeon/csrc-octeon.c b/arch/mips/cavium-octeon/csrc-octeon.c new file mode 100644 index 0000000..70fd92c --- /dev/null +++ b/arch/mips/cavium-octeon/csrc-octeon.c @@ -0,0 +1,58 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2007 by Ralf Baechle + */ +#include +#include + +#include + +#include +#include + +/* + * Set the current core's cvmcount counter to the value of the + * IPD_CLK_COUNT. We do this on all cores as they are brought + * on-line. This allows for a read from a local cpu register to + * access a synchronized counter. + * + */ +void octeon_init_cvmcount(void) +{ + unsigned long flags; + unsigned loops = 2; + + /* Clobber loops so GCC will not unroll the following while loop. */ + asm("" : "+r" (loops)); + + local_irq_save(flags); + /* + * Loop several times so we are executing from the cache, + * which should give more deterministic timing. + */ + while (loops--) + write_c0_cvmcount(cvmx_read_csr(CVMX_IPD_CLK_COUNT)); + local_irq_restore(flags); +} + +static cycle_t octeon_cvmcount_read(void) +{ + return read_c0_cvmcount(); +} + +static struct clocksource clocksource_mips = { + .name = "OCTEON_CVMCOUNT", + .read = octeon_cvmcount_read, + .mask = CLOCKSOURCE_MASK(64), + .flags = CLOCK_SOURCE_IS_CONTINUOUS, +}; + +void __init plat_time_init(void) +{ + clocksource_mips.rating = 300; + clocksource_set_clock(&clocksource_mips, mips_hpt_frequency); + clocksource_register(&clocksource_mips); +} diff --git a/arch/mips/cavium-octeon/dma-octeon.c b/arch/mips/cavium-octeon/dma-octeon.c new file mode 100644 index 0000000..01b1ef9 --- /dev/null +++ b/arch/mips/cavium-octeon/dma-octeon.c @@ -0,0 +1,32 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2000 Ani Joshi + * Copyright (C) 2000, 2001 Ralf Baechle + * Copyright (C) 2005 Ilya A. Volynets-Evenbakh + * swiped from i386, and cloned for MIPS by Geert, polished by Ralf. + * IP32 changes by Ilya. + * Cavium Networks: Create new dma setup for Cavium Networks Octeon based on + * the kernels original. + */ +#include +#include + +#include + +dma_addr_t octeon_map_dma_mem(struct device *dev, void *ptr, size_t size) +{ + /* Without PCI/PCIe this function can be called for Octeon internal + devices such as USB. These devices all support 64bit addressing */ + mb(); + return virt_to_phys(ptr); +} + +void octeon_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr) +{ + /* Without PCI/PCIe this function can be called for Octeon internal + * devices such as USB. These devices all support 64bit addressing */ + return; +} diff --git a/arch/mips/cavium-octeon/flash_setup.c b/arch/mips/cavium-octeon/flash_setup.c new file mode 100644 index 0000000..553d36c --- /dev/null +++ b/arch/mips/cavium-octeon/flash_setup.c @@ -0,0 +1,84 @@ +/* + * Octeon Bootbus flash setup + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2007, 2008 Cavium Networks + */ +#include +#include +#include +#include + +#include + +static struct map_info flash_map; +static struct mtd_info *mymtd; +#ifdef CONFIG_MTD_PARTITIONS +static int nr_parts; +static struct mtd_partition *parts; +static const char *part_probe_types[] = { + "cmdlinepart", +#ifdef CONFIG_MTD_REDBOOT_PARTS + "RedBoot", +#endif + NULL +}; +#endif + +/** + * Module/ driver initialization. + * + * Returns Zero on success + */ +static int __init flash_init(void) +{ + /* + * Read the bootbus region 0 setup to determine the base + * address of the flash. + */ + union cvmx_mio_boot_reg_cfgx region_cfg; + region_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(0)); + if (region_cfg.s.en) { + /* + * The bootloader always takes the flash and sets its + * address so the entire flash fits below + * 0x1fc00000. This way the flash aliases to + * 0x1fc00000 for booting. Software can access the + * full flash at the true address, while core boot can + * access 4MB. + */ + /* Use this name so old part lines work */ + flash_map.name = "phys_mapped_flash"; + flash_map.phys = region_cfg.s.base << 16; + flash_map.size = 0x1fc00000 - flash_map.phys; + flash_map.bankwidth = 1; + flash_map.virt = ioremap(flash_map.phys, flash_map.size); + pr_notice("Bootbus flash: Setting flash for %luMB flash at " + "0x%08lx\n", flash_map.size >> 20, flash_map.phys); + simple_map_init(&flash_map); + mymtd = do_map_probe("cfi_probe", &flash_map); + if (mymtd) { + mymtd->owner = THIS_MODULE; + +#ifdef CONFIG_MTD_PARTITIONS + nr_parts = parse_mtd_partitions(mymtd, + part_probe_types, + &parts, 0); + if (nr_parts > 0) + add_mtd_partitions(mymtd, parts, nr_parts); + else + add_mtd_device(mymtd); +#else + add_mtd_device(mymtd); +#endif + } else { + pr_err("Failed to register MTD device for flash\n"); + } + } + return 0; +} + +late_initcall(flash_init); diff --git a/arch/mips/cavium-octeon/octeon-irq.c b/arch/mips/cavium-octeon/octeon-irq.c new file mode 100644 index 0000000..fc72984 --- /dev/null +++ b/arch/mips/cavium-octeon/octeon-irq.c @@ -0,0 +1,497 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2004-2008 Cavium Networks + */ +#include +#include +#include + +#include + +DEFINE_RWLOCK(octeon_irq_ciu0_rwlock); +DEFINE_RWLOCK(octeon_irq_ciu1_rwlock); +DEFINE_SPINLOCK(octeon_irq_msi_lock); + +static void octeon_irq_core_ack(unsigned int irq) +{ + unsigned int bit = irq - OCTEON_IRQ_SW0; + /* + * We don't need to disable IRQs to make these atomic since + * they are already disabled earlier in the low level + * interrupt code. + */ + clear_c0_status(0x100 << bit); + /* The two user interrupts must be cleared manually. */ + if (bit < 2) + clear_c0_cause(0x100 << bit); +} + +static void octeon_irq_core_eoi(unsigned int irq) +{ + irq_desc_t *desc = irq_desc + irq; + unsigned int bit = irq - OCTEON_IRQ_SW0; + /* + * If an IRQ is being processed while we are disabling it the + * handler will attempt to unmask the interrupt after it has + * been disabled. + */ + if (desc->status & IRQ_DISABLED) + return; + + /* There is a race here. We should fix it. */ + + /* + * We don't need to disable IRQs to make these atomic since + * they are already disabled earlier in the low level + * interrupt code. + */ + set_c0_status(0x100 << bit); +} + +static void octeon_irq_core_enable(unsigned int irq) +{ + unsigned long flags; + unsigned int bit = irq - OCTEON_IRQ_SW0; + + /* + * We need to disable interrupts to make sure our updates are + * atomic. + */ + local_irq_save(flags); + set_c0_status(0x100 << bit); + local_irq_restore(flags); +} + +static void octeon_irq_core_disable_local(unsigned int irq) +{ + unsigned long flags; + unsigned int bit = irq - OCTEON_IRQ_SW0; + /* + * We need to disable interrupts to make sure our updates are + * atomic. + */ + local_irq_save(flags); + clear_c0_status(0x100 << bit); + local_irq_restore(flags); +} + +static void octeon_irq_core_disable(unsigned int irq) +{ +#ifdef CONFIG_SMP + on_each_cpu((void (*)(void *)) octeon_irq_core_disable_local, + (void *) (long) irq, 1); +#else + octeon_irq_core_disable_local(irq); +#endif +} + +static struct irq_chip octeon_irq_chip_core = { + .name = "Core", + .enable = octeon_irq_core_enable, + .disable = octeon_irq_core_disable, + .ack = octeon_irq_core_ack, + .eoi = octeon_irq_core_eoi, +}; + + +static void octeon_irq_ciu0_ack(unsigned int irq) +{ + /* + * In order to avoid any locking accessing the CIU, we + * acknowledge CIU interrupts by disabling all of them. This + * way we can use a per core register and avoid any out of + * core locking requirements. This has the side affect that + * CIU interrupts can't be processed recursively. + * + * We don't need to disable IRQs to make these atomic since + * they are already disabled earlier in the low level + * interrupt code. + */ + clear_c0_status(0x100 << 2); +} + +static void octeon_irq_ciu0_eoi(unsigned int irq) +{ + /* + * Enable all CIU interrupts again. We don't need to disable + * IRQs to make these atomic since they are already disabled + * earlier in the low level interrupt code. + */ + set_c0_status(0x100 << 2); +} + +static void octeon_irq_ciu0_enable(unsigned int irq) +{ + int coreid = cvmx_get_core_num(); + unsigned long flags; + uint64_t en0; + int bit = irq - OCTEON_IRQ_WORKQ0; /* Bit 0-63 of EN0 */ + + /* + * A read lock is used here to make sure only one core is ever + * updating the CIU enable bits at a time. During an enable + * the cores don't interfere with each other. During a disable + * the write lock stops any enables that might cause a + * problem. + */ + read_lock_irqsave(&octeon_irq_ciu0_rwlock, flags); + en0 = cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2)); + en0 |= 1ull << bit; + cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), en0); + cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2)); + read_unlock_irqrestore(&octeon_irq_ciu0_rwlock, flags); +} + +static void octeon_irq_ciu0_disable(unsigned int irq) +{ + int bit = irq - OCTEON_IRQ_WORKQ0; /* Bit 0-63 of EN0 */ + unsigned long flags; + uint64_t en0; +#ifdef CONFIG_SMP + int cpu; + write_lock_irqsave(&octeon_irq_ciu0_rwlock, flags); + for_each_online_cpu(cpu) { + int coreid = cpu_logical_map(cpu); + en0 = cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2)); + en0 &= ~(1ull << bit); + cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), en0); + } + /* + * We need to do a read after the last update to make sure all + * of them are done. + */ + cvmx_read_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num() * 2)); + write_unlock_irqrestore(&octeon_irq_ciu0_rwlock, flags); +#else + int coreid = cvmx_get_core_num(); + local_irq_save(flags); + en0 = cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2)); + en0 &= ~(1ull << bit); + cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), en0); + cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2)); + local_irq_restore(flags); +#endif +} + +#ifdef CONFIG_SMP +static void octeon_irq_ciu0_set_affinity(unsigned int irq, const struct cpumask *dest) +{ + int cpu; + int bit = irq - OCTEON_IRQ_WORKQ0; /* Bit 0-63 of EN0 */ + + write_lock(&octeon_irq_ciu0_rwlock); + for_each_online_cpu(cpu) { + int coreid = cpu_logical_map(cpu); + uint64_t en0 = + cvmx_read_csr(CVMX_CIU_INTX_EN0(coreid * 2)); + if (cpumask_test_cpu(cpu, dest)) + en0 |= 1ull << bit; + else + en0 &= ~(1ull << bit); + cvmx_write_csr(CVMX_CIU_INTX_EN0(coreid * 2), en0); + } + /* + * We need to do a read after the last update to make sure all + * of them are done. + */ + cvmx_read_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num() * 2)); + write_unlock(&octeon_irq_ciu0_rwlock); +} +#endif + +static struct irq_chip octeon_irq_chip_ciu0 = { + .name = "CIU0", + .enable = octeon_irq_ciu0_enable, + .disable = octeon_irq_ciu0_disable, + .ack = octeon_irq_ciu0_ack, + .eoi = octeon_irq_ciu0_eoi, +#ifdef CONFIG_SMP + .set_affinity = octeon_irq_ciu0_set_affinity, +#endif +}; + + +static void octeon_irq_ciu1_ack(unsigned int irq) +{ + /* + * In order to avoid any locking accessing the CIU, we + * acknowledge CIU interrupts by disabling all of them. This + * way we can use a per core register and avoid any out of + * core locking requirements. This has the side affect that + * CIU interrupts can't be processed recursively. We don't + * need to disable IRQs to make these atomic since they are + * already disabled earlier in the low level interrupt code. + */ + clear_c0_status(0x100 << 3); +} + +static void octeon_irq_ciu1_eoi(unsigned int irq) +{ + /* + * Enable all CIU interrupts again. We don't need to disable + * IRQs to make these atomic since they are already disabled + * earlier in the low level interrupt code. + */ + set_c0_status(0x100 << 3); +} + +static void octeon_irq_ciu1_enable(unsigned int irq) +{ + int coreid = cvmx_get_core_num(); + unsigned long flags; + uint64_t en1; + int bit = irq - OCTEON_IRQ_WDOG0; /* Bit 0-63 of EN1 */ + + /* + * A read lock is used here to make sure only one core is ever + * updating the CIU enable bits at a time. During an enable + * the cores don't interfere with each other. During a disable + * the write lock stops any enables that might cause a + * problem. + */ + read_lock_irqsave(&octeon_irq_ciu1_rwlock, flags); + en1 = cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1)); + en1 |= 1ull << bit; + cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), en1); + cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1)); + read_unlock_irqrestore(&octeon_irq_ciu1_rwlock, flags); +} + +static void octeon_irq_ciu1_disable(unsigned int irq) +{ + int bit = irq - OCTEON_IRQ_WDOG0; /* Bit 0-63 of EN1 */ + unsigned long flags; + uint64_t en1; +#ifdef CONFIG_SMP + int cpu; + write_lock_irqsave(&octeon_irq_ciu1_rwlock, flags); + for_each_online_cpu(cpu) { + int coreid = cpu_logical_map(cpu); + en1 = cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1)); + en1 &= ~(1ull << bit); + cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), en1); + } + /* + * We need to do a read after the last update to make sure all + * of them are done. + */ + cvmx_read_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num() * 2 + 1)); + write_unlock_irqrestore(&octeon_irq_ciu1_rwlock, flags); +#else + int coreid = cvmx_get_core_num(); + local_irq_save(flags); + en1 = cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1)); + en1 &= ~(1ull << bit); + cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), en1); + cvmx_read_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1)); + local_irq_restore(flags); +#endif +} + +#ifdef CONFIG_SMP +static void octeon_irq_ciu1_set_affinity(unsigned int irq, const struct cpumask *dest) +{ + int cpu; + int bit = irq - OCTEON_IRQ_WDOG0; /* Bit 0-63 of EN1 */ + + write_lock(&octeon_irq_ciu1_rwlock); + for_each_online_cpu(cpu) { + int coreid = cpu_logical_map(cpu); + uint64_t en1 = + cvmx_read_csr(CVMX_CIU_INTX_EN1 + (coreid * 2 + 1)); + if (cpumask_test_cpu(cpu, dest)) + en1 |= 1ull << bit; + else + en1 &= ~(1ull << bit); + cvmx_write_csr(CVMX_CIU_INTX_EN1(coreid * 2 + 1), en1); + } + /* + * We need to do a read after the last update to make sure all + * of them are done. + */ + cvmx_read_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num() * 2 + 1)); + write_unlock(&octeon_irq_ciu1_rwlock); +} +#endif + +static struct irq_chip octeon_irq_chip_ciu1 = { + .name = "CIU1", + .enable = octeon_irq_ciu1_enable, + .disable = octeon_irq_ciu1_disable, + .ack = octeon_irq_ciu1_ack, + .eoi = octeon_irq_ciu1_eoi, +#ifdef CONFIG_SMP + .set_affinity = octeon_irq_ciu1_set_affinity, +#endif +}; + +#ifdef CONFIG_PCI_MSI + +static void octeon_irq_msi_ack(unsigned int irq) +{ + if (!octeon_has_feature(OCTEON_FEATURE_PCIE)) { + /* These chips have PCI */ + cvmx_write_csr(CVMX_NPI_NPI_MSI_RCV, + 1ull << (irq - OCTEON_IRQ_MSI_BIT0)); + } else { + /* + * These chips have PCIe. Thankfully the ACK doesn't + * need any locking. + */ + cvmx_write_csr(CVMX_PEXP_NPEI_MSI_RCV0, + 1ull << (irq - OCTEON_IRQ_MSI_BIT0)); + } +} + +static void octeon_irq_msi_eoi(unsigned int irq) +{ + /* Nothing needed */ +} + +static void octeon_irq_msi_enable(unsigned int irq) +{ + if (!octeon_has_feature(OCTEON_FEATURE_PCIE)) { + /* + * Octeon PCI doesn't have the ability to mask/unmask + * MSI interrupts individually. Instead of + * masking/unmasking them in groups of 16, we simple + * assume MSI devices are well behaved. MSI + * interrupts are always enable and the ACK is assumed + * to be enough. + */ + } else { + /* These chips have PCIe. Note that we only support + * the first 64 MSI interrupts. Unfortunately all the + * MSI enables are in the same register. We use + * MSI0's lock to control access to them all. + */ + uint64_t en; + unsigned long flags; + spin_lock_irqsave(&octeon_irq_msi_lock, flags); + en = cvmx_read_csr(CVMX_PEXP_NPEI_MSI_ENB0); + en |= 1ull << (irq - OCTEON_IRQ_MSI_BIT0); + cvmx_write_csr(CVMX_PEXP_NPEI_MSI_ENB0, en); + cvmx_read_csr(CVMX_PEXP_NPEI_MSI_ENB0); + spin_unlock_irqrestore(&octeon_irq_msi_lock, flags); + } +} + +static void octeon_irq_msi_disable(unsigned int irq) +{ + if (!octeon_has_feature(OCTEON_FEATURE_PCIE)) { + /* See comment in enable */ + } else { + /* + * These chips have PCIe. Note that we only support + * the first 64 MSI interrupts. Unfortunately all the + * MSI enables are in the same register. We use + * MSI0's lock to control access to them all. + */ + uint64_t en; + unsigned long flags; + spin_lock_irqsave(&octeon_irq_msi_lock, flags); + en = cvmx_read_csr(CVMX_PEXP_NPEI_MSI_ENB0); + en &= ~(1ull << (irq - OCTEON_IRQ_MSI_BIT0)); + cvmx_write_csr(CVMX_PEXP_NPEI_MSI_ENB0, en); + cvmx_read_csr(CVMX_PEXP_NPEI_MSI_ENB0); + spin_unlock_irqrestore(&octeon_irq_msi_lock, flags); + } +} + +static struct irq_chip octeon_irq_chip_msi = { + .name = "MSI", + .enable = octeon_irq_msi_enable, + .disable = octeon_irq_msi_disable, + .ack = octeon_irq_msi_ack, + .eoi = octeon_irq_msi_eoi, +}; +#endif + +void __init arch_init_irq(void) +{ + int irq; + +#ifdef CONFIG_SMP + /* Set the default affinity to the boot cpu. */ + cpumask_clear(irq_default_affinity); + cpumask_set_cpu(smp_processor_id(), irq_default_affinity); +#endif + + if (NR_IRQS < OCTEON_IRQ_LAST) + pr_err("octeon_irq_init: NR_IRQS is set too low\n"); + + /* 0 - 15 reserved for i8259 master and slave controller. */ + + /* 17 - 23 Mips internal */ + for (irq = OCTEON_IRQ_SW0; irq <= OCTEON_IRQ_TIMER; irq++) { + set_irq_chip_and_handler(irq, &octeon_irq_chip_core, + handle_percpu_irq); + } + + /* 24 - 87 CIU_INT_SUM0 */ + for (irq = OCTEON_IRQ_WORKQ0; irq <= OCTEON_IRQ_BOOTDMA; irq++) { + set_irq_chip_and_handler(irq, &octeon_irq_chip_ciu0, + handle_percpu_irq); + } + + /* 88 - 151 CIU_INT_SUM1 */ + for (irq = OCTEON_IRQ_WDOG0; irq <= OCTEON_IRQ_RESERVED151; irq++) { + set_irq_chip_and_handler(irq, &octeon_irq_chip_ciu1, + handle_percpu_irq); + } + +#ifdef CONFIG_PCI_MSI + /* 152 - 215 PCI/PCIe MSI interrupts */ + for (irq = OCTEON_IRQ_MSI_BIT0; irq <= OCTEON_IRQ_MSI_BIT63; irq++) { + set_irq_chip_and_handler(irq, &octeon_irq_chip_msi, + handle_percpu_irq); + } +#endif + set_c0_status(0x300 << 2); +} + +asmlinkage void plat_irq_dispatch(void) +{ + const unsigned long core_id = cvmx_get_core_num(); + const uint64_t ciu_sum0_address = CVMX_CIU_INTX_SUM0(core_id * 2); + const uint64_t ciu_en0_address = CVMX_CIU_INTX_EN0(core_id * 2); + const uint64_t ciu_sum1_address = CVMX_CIU_INT_SUM1; + const uint64_t ciu_en1_address = CVMX_CIU_INTX_EN1(core_id * 2 + 1); + unsigned long cop0_cause; + unsigned long cop0_status; + uint64_t ciu_en; + uint64_t ciu_sum; + + while (1) { + cop0_cause = read_c0_cause(); + cop0_status = read_c0_status(); + cop0_cause &= cop0_status; + cop0_cause &= ST0_IM; + + if (unlikely(cop0_cause & STATUSF_IP2)) { + ciu_sum = cvmx_read_csr(ciu_sum0_address); + ciu_en = cvmx_read_csr(ciu_en0_address); + ciu_sum &= ciu_en; + if (likely(ciu_sum)) + do_IRQ(fls64(ciu_sum) + OCTEON_IRQ_WORKQ0 - 1); + else + spurious_interrupt(); + } else if (unlikely(cop0_cause & STATUSF_IP3)) { + ciu_sum = cvmx_read_csr(ciu_sum1_address); + ciu_en = cvmx_read_csr(ciu_en1_address); + ciu_sum &= ciu_en; + if (likely(ciu_sum)) + do_IRQ(fls64(ciu_sum) + OCTEON_IRQ_WDOG0 - 1); + else + spurious_interrupt(); + } else if (likely(cop0_cause)) { + do_IRQ(fls(cop0_cause) - 9 + MIPS_CPU_IRQ_BASE); + } else { + break; + } + } +} diff --git a/arch/mips/cavium-octeon/octeon-memcpy.S b/arch/mips/cavium-octeon/octeon-memcpy.S new file mode 100644 index 0000000..88e0cdd --- /dev/null +++ b/arch/mips/cavium-octeon/octeon-memcpy.S @@ -0,0 +1,521 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Unified implementation of memcpy, memmove and the __copy_user backend. + * + * Copyright (C) 1998, 99, 2000, 01, 2002 Ralf Baechle (ralf@gnu.org) + * Copyright (C) 1999, 2000, 01, 2002 Silicon Graphics, Inc. + * Copyright (C) 2002 Broadcom, Inc. + * memcpy/copy_user author: Mark Vandevoorde + * + * Mnemonic names for arguments to memcpy/__copy_user + */ + +#include +#include +#include + +#define dst a0 +#define src a1 +#define len a2 + +/* + * Spec + * + * memcpy copies len bytes from src to dst and sets v0 to dst. + * It assumes that + * - src and dst don't overlap + * - src is readable + * - dst is writable + * memcpy uses the standard calling convention + * + * __copy_user copies up to len bytes from src to dst and sets a2 (len) to + * the number of uncopied bytes due to an exception caused by a read or write. + * __copy_user assumes that src and dst don't overlap, and that the call is + * implementing one of the following: + * copy_to_user + * - src is readable (no exceptions when reading src) + * copy_from_user + * - dst is writable (no exceptions when writing dst) + * __copy_user uses a non-standard calling convention; see + * arch/mips/include/asm/uaccess.h + * + * When an exception happens on a load, the handler must + # ensure that all of the destination buffer is overwritten to prevent + * leaking information to user mode programs. + */ + +/* + * Implementation + */ + +/* + * The exception handler for loads requires that: + * 1- AT contain the address of the byte just past the end of the source + * of the copy, + * 2- src_entry <= src < AT, and + * 3- (dst - src) == (dst_entry - src_entry), + * The _entry suffix denotes values when __copy_user was called. + * + * (1) is set up up by uaccess.h and maintained by not writing AT in copy_user + * (2) is met by incrementing src by the number of bytes copied + * (3) is met by not doing loads between a pair of increments of dst and src + * + * The exception handlers for stores adjust len (if necessary) and return. + * These handlers do not need to overwrite any data. + * + * For __rmemcpy and memmove an exception is always a kernel bug, therefore + * they're not protected. + */ + +#define EXC(inst_reg,addr,handler) \ +9: inst_reg, addr; \ + .section __ex_table,"a"; \ + PTR 9b, handler; \ + .previous + +/* + * Only on the 64-bit kernel we can made use of 64-bit registers. + */ +#ifdef CONFIG_64BIT +#define USE_DOUBLE +#endif + +#ifdef USE_DOUBLE + +#define LOAD ld +#define LOADL ldl +#define LOADR ldr +#define STOREL sdl +#define STORER sdr +#define STORE sd +#define ADD daddu +#define SUB dsubu +#define SRL dsrl +#define SRA dsra +#define SLL dsll +#define SLLV dsllv +#define SRLV dsrlv +#define NBYTES 8 +#define LOG_NBYTES 3 + +/* + * As we are sharing code base with the mips32 tree (which use the o32 ABI + * register definitions). We need to redefine the register definitions from + * the n64 ABI register naming to the o32 ABI register naming. + */ +#undef t0 +#undef t1 +#undef t2 +#undef t3 +#define t0 $8 +#define t1 $9 +#define t2 $10 +#define t3 $11 +#define t4 $12 +#define t5 $13 +#define t6 $14 +#define t7 $15 + +#else + +#define LOAD lw +#define LOADL lwl +#define LOADR lwr +#define STOREL swl +#define STORER swr +#define STORE sw +#define ADD addu +#define SUB subu +#define SRL srl +#define SLL sll +#define SRA sra +#define SLLV sllv +#define SRLV srlv +#define NBYTES 4 +#define LOG_NBYTES 2 + +#endif /* USE_DOUBLE */ + +#ifdef CONFIG_CPU_LITTLE_ENDIAN +#define LDFIRST LOADR +#define LDREST LOADL +#define STFIRST STORER +#define STREST STOREL +#define SHIFT_DISCARD SLLV +#else +#define LDFIRST LOADL +#define LDREST LOADR +#define STFIRST STOREL +#define STREST STORER +#define SHIFT_DISCARD SRLV +#endif + +#define FIRST(unit) ((unit)*NBYTES) +#define REST(unit) (FIRST(unit)+NBYTES-1) +#define UNIT(unit) FIRST(unit) + +#define ADDRMASK (NBYTES-1) + + .text + .set noreorder + .set noat + +/* + * A combined memcpy/__copy_user + * __copy_user sets len to 0 for success; else to an upper bound of + * the number of uncopied bytes. + * memcpy sets v0 to dst. + */ + .align 5 +LEAF(memcpy) /* a0=dst a1=src a2=len */ + move v0, dst /* return value */ +__memcpy: +FEXPORT(__copy_user) + /* + * Note: dst & src may be unaligned, len may be 0 + * Temps + */ + # + # Octeon doesn't care if the destination is unaligned. The hardware + # can fix it faster than we can special case the assembly. + # + pref 0, 0(src) + sltu t0, len, NBYTES # Check if < 1 word + bnez t0, copy_bytes_checklen + and t0, src, ADDRMASK # Check if src unaligned + bnez t0, src_unaligned + sltu t0, len, 4*NBYTES # Check if < 4 words + bnez t0, less_than_4units + sltu t0, len, 8*NBYTES # Check if < 8 words + bnez t0, less_than_8units + sltu t0, len, 16*NBYTES # Check if < 16 words + bnez t0, cleanup_both_aligned + sltu t0, len, 128+1 # Check if len < 129 + bnez t0, 1f # Skip prefetch if len is too short + sltu t0, len, 256+1 # Check if len < 257 + bnez t0, 1f # Skip prefetch if len is too short + pref 0, 128(src) # We must not prefetch invalid addresses + # + # This is where we loop if there is more than 128 bytes left +2: pref 0, 256(src) # We must not prefetch invalid addresses + # + # This is where we loop if we can't prefetch anymore +1: +EXC( LOAD t0, UNIT(0)(src), l_exc) +EXC( LOAD t1, UNIT(1)(src), l_exc_copy) +EXC( LOAD t2, UNIT(2)(src), l_exc_copy) +EXC( LOAD t3, UNIT(3)(src), l_exc_copy) + SUB len, len, 16*NBYTES +EXC( STORE t0, UNIT(0)(dst), s_exc_p16u) +EXC( STORE t1, UNIT(1)(dst), s_exc_p15u) +EXC( STORE t2, UNIT(2)(dst), s_exc_p14u) +EXC( STORE t3, UNIT(3)(dst), s_exc_p13u) +EXC( LOAD t0, UNIT(4)(src), l_exc_copy) +EXC( LOAD t1, UNIT(5)(src), l_exc_copy) +EXC( LOAD t2, UNIT(6)(src), l_exc_copy) +EXC( LOAD t3, UNIT(7)(src), l_exc_copy) +EXC( STORE t0, UNIT(4)(dst), s_exc_p12u) +EXC( STORE t1, UNIT(5)(dst), s_exc_p11u) +EXC( STORE t2, UNIT(6)(dst), s_exc_p10u) + ADD src, src, 16*NBYTES +EXC( STORE t3, UNIT(7)(dst), s_exc_p9u) + ADD dst, dst, 16*NBYTES +EXC( LOAD t0, UNIT(-8)(src), l_exc_copy) +EXC( LOAD t1, UNIT(-7)(src), l_exc_copy) +EXC( LOAD t2, UNIT(-6)(src), l_exc_copy) +EXC( LOAD t3, UNIT(-5)(src), l_exc_copy) +EXC( STORE t0, UNIT(-8)(dst), s_exc_p8u) +EXC( STORE t1, UNIT(-7)(dst), s_exc_p7u) +EXC( STORE t2, UNIT(-6)(dst), s_exc_p6u) +EXC( STORE t3, UNIT(-5)(dst), s_exc_p5u) +EXC( LOAD t0, UNIT(-4)(src), l_exc_copy) +EXC( LOAD t1, UNIT(-3)(src), l_exc_copy) +EXC( LOAD t2, UNIT(-2)(src), l_exc_copy) +EXC( LOAD t3, UNIT(-1)(src), l_exc_copy) +EXC( STORE t0, UNIT(-4)(dst), s_exc_p4u) +EXC( STORE t1, UNIT(-3)(dst), s_exc_p3u) +EXC( STORE t2, UNIT(-2)(dst), s_exc_p2u) +EXC( STORE t3, UNIT(-1)(dst), s_exc_p1u) + sltu t0, len, 256+1 # See if we can prefetch more + beqz t0, 2b + sltu t0, len, 128 # See if we can loop more time + beqz t0, 1b + nop + # + # Jump here if there are less than 16*NBYTES left. + # +cleanup_both_aligned: + beqz len, done + sltu t0, len, 8*NBYTES + bnez t0, less_than_8units + nop +EXC( LOAD t0, UNIT(0)(src), l_exc) +EXC( LOAD t1, UNIT(1)(src), l_exc_copy) +EXC( LOAD t2, UNIT(2)(src), l_exc_copy) +EXC( LOAD t3, UNIT(3)(src), l_exc_copy) + SUB len, len, 8*NBYTES +EXC( STORE t0, UNIT(0)(dst), s_exc_p8u) +EXC( STORE t1, UNIT(1)(dst), s_exc_p7u) +EXC( STORE t2, UNIT(2)(dst), s_exc_p6u) +EXC( STORE t3, UNIT(3)(dst), s_exc_p5u) +EXC( LOAD t0, UNIT(4)(src), l_exc_copy) +EXC( LOAD t1, UNIT(5)(src), l_exc_copy) +EXC( LOAD t2, UNIT(6)(src), l_exc_copy) +EXC( LOAD t3, UNIT(7)(src), l_exc_copy) +EXC( STORE t0, UNIT(4)(dst), s_exc_p4u) +EXC( STORE t1, UNIT(5)(dst), s_exc_p3u) +EXC( STORE t2, UNIT(6)(dst), s_exc_p2u) +EXC( STORE t3, UNIT(7)(dst), s_exc_p1u) + ADD src, src, 8*NBYTES + beqz len, done + ADD dst, dst, 8*NBYTES + # + # Jump here if there are less than 8*NBYTES left. + # +less_than_8units: + sltu t0, len, 4*NBYTES + bnez t0, less_than_4units + nop +EXC( LOAD t0, UNIT(0)(src), l_exc) +EXC( LOAD t1, UNIT(1)(src), l_exc_copy) +EXC( LOAD t2, UNIT(2)(src), l_exc_copy) +EXC( LOAD t3, UNIT(3)(src), l_exc_copy) + SUB len, len, 4*NBYTES +EXC( STORE t0, UNIT(0)(dst), s_exc_p4u) +EXC( STORE t1, UNIT(1)(dst), s_exc_p3u) +EXC( STORE t2, UNIT(2)(dst), s_exc_p2u) +EXC( STORE t3, UNIT(3)(dst), s_exc_p1u) + ADD src, src, 4*NBYTES + beqz len, done + ADD dst, dst, 4*NBYTES + # + # Jump here if there are less than 4*NBYTES left. This means + # we may need to copy up to 3 NBYTES words. + # +less_than_4units: + sltu t0, len, 1*NBYTES + bnez t0, copy_bytes_checklen + nop + # + # 1) Copy NBYTES, then check length again + # +EXC( LOAD t0, 0(src), l_exc) + SUB len, len, NBYTES + sltu t1, len, 8 +EXC( STORE t0, 0(dst), s_exc_p1u) + ADD src, src, NBYTES + bnez t1, copy_bytes_checklen + ADD dst, dst, NBYTES + # + # 2) Copy NBYTES, then check length again + # +EXC( LOAD t0, 0(src), l_exc) + SUB len, len, NBYTES + sltu t1, len, 8 +EXC( STORE t0, 0(dst), s_exc_p1u) + ADD src, src, NBYTES + bnez t1, copy_bytes_checklen + ADD dst, dst, NBYTES + # + # 3) Copy NBYTES, then check length again + # +EXC( LOAD t0, 0(src), l_exc) + SUB len, len, NBYTES + ADD src, src, NBYTES + ADD dst, dst, NBYTES + b copy_bytes_checklen +EXC( STORE t0, -8(dst), s_exc_p1u) + +src_unaligned: +#define rem t8 + SRL t0, len, LOG_NBYTES+2 # +2 for 4 units/iter + beqz t0, cleanup_src_unaligned + and rem, len, (4*NBYTES-1) # rem = len % 4*NBYTES +1: +/* + * Avoid consecutive LD*'s to the same register since some mips + * implementations can't issue them in the same cycle. + * It's OK to load FIRST(N+1) before REST(N) because the two addresses + * are to the same unit (unless src is aligned, but it's not). + */ +EXC( LDFIRST t0, FIRST(0)(src), l_exc) +EXC( LDFIRST t1, FIRST(1)(src), l_exc_copy) + SUB len, len, 4*NBYTES +EXC( LDREST t0, REST(0)(src), l_exc_copy) +EXC( LDREST t1, REST(1)(src), l_exc_copy) +EXC( LDFIRST t2, FIRST(2)(src), l_exc_copy) +EXC( LDFIRST t3, FIRST(3)(src), l_exc_copy) +EXC( LDREST t2, REST(2)(src), l_exc_copy) +EXC( LDREST t3, REST(3)(src), l_exc_copy) + ADD src, src, 4*NBYTES +EXC( STORE t0, UNIT(0)(dst), s_exc_p4u) +EXC( STORE t1, UNIT(1)(dst), s_exc_p3u) +EXC( STORE t2, UNIT(2)(dst), s_exc_p2u) +EXC( STORE t3, UNIT(3)(dst), s_exc_p1u) + bne len, rem, 1b + ADD dst, dst, 4*NBYTES + +cleanup_src_unaligned: + beqz len, done + and rem, len, NBYTES-1 # rem = len % NBYTES + beq rem, len, copy_bytes + nop +1: +EXC( LDFIRST t0, FIRST(0)(src), l_exc) +EXC( LDREST t0, REST(0)(src), l_exc_copy) + SUB len, len, NBYTES +EXC( STORE t0, 0(dst), s_exc_p1u) + ADD src, src, NBYTES + bne len, rem, 1b + ADD dst, dst, NBYTES + +copy_bytes_checklen: + beqz len, done + nop +copy_bytes: + /* 0 < len < NBYTES */ +#define COPY_BYTE(N) \ +EXC( lb t0, N(src), l_exc); \ + SUB len, len, 1; \ + beqz len, done; \ +EXC( sb t0, N(dst), s_exc_p1) + + COPY_BYTE(0) + COPY_BYTE(1) +#ifdef USE_DOUBLE + COPY_BYTE(2) + COPY_BYTE(3) + COPY_BYTE(4) + COPY_BYTE(5) +#endif +EXC( lb t0, NBYTES-2(src), l_exc) + SUB len, len, 1 + jr ra +EXC( sb t0, NBYTES-2(dst), s_exc_p1) +done: + jr ra + nop + END(memcpy) + +l_exc_copy: + /* + * Copy bytes from src until faulting load address (or until a + * lb faults) + * + * When reached by a faulting LDFIRST/LDREST, THREAD_BUADDR($28) + * may be more than a byte beyond the last address. + * Hence, the lb below may get an exception. + * + * Assumes src < THREAD_BUADDR($28) + */ + LOAD t0, TI_TASK($28) + nop + LOAD t0, THREAD_BUADDR(t0) +1: +EXC( lb t1, 0(src), l_exc) + ADD src, src, 1 + sb t1, 0(dst) # can't fault -- we're copy_from_user + bne src, t0, 1b + ADD dst, dst, 1 +l_exc: + LOAD t0, TI_TASK($28) + nop + LOAD t0, THREAD_BUADDR(t0) # t0 is just past last good address + nop + SUB len, AT, t0 # len number of uncopied bytes + /* + * Here's where we rely on src and dst being incremented in tandem, + * See (3) above. + * dst += (fault addr - src) to put dst at first byte to clear + */ + ADD dst, t0 # compute start address in a1 + SUB dst, src + /* + * Clear len bytes starting at dst. Can't call __bzero because it + * might modify len. An inefficient loop for these rare times... + */ + beqz len, done + SUB src, len, 1 +1: sb zero, 0(dst) + ADD dst, dst, 1 + bnez src, 1b + SUB src, src, 1 + jr ra + nop + + +#define SEXC(n) \ +s_exc_p ## n ## u: \ + jr ra; \ + ADD len, len, n*NBYTES + +SEXC(16) +SEXC(15) +SEXC(14) +SEXC(13) +SEXC(12) +SEXC(11) +SEXC(10) +SEXC(9) +SEXC(8) +SEXC(7) +SEXC(6) +SEXC(5) +SEXC(4) +SEXC(3) +SEXC(2) +SEXC(1) + +s_exc_p1: + jr ra + ADD len, len, 1 +s_exc: + jr ra + nop + + .align 5 +LEAF(memmove) + ADD t0, a0, a2 + ADD t1, a1, a2 + sltu t0, a1, t0 # dst + len <= src -> memcpy + sltu t1, a0, t1 # dst >= src + len -> memcpy + and t0, t1 + beqz t0, __memcpy + move v0, a0 /* return value */ + beqz a2, r_out + END(memmove) + + /* fall through to __rmemcpy */ +LEAF(__rmemcpy) /* a0=dst a1=src a2=len */ + sltu t0, a1, a0 + beqz t0, r_end_bytes_up # src >= dst + nop + ADD a0, a2 # dst = dst + len + ADD a1, a2 # src = src + len + +r_end_bytes: + lb t0, -1(a1) + SUB a2, a2, 0x1 + sb t0, -1(a0) + SUB a1, a1, 0x1 + bnez a2, r_end_bytes + SUB a0, a0, 0x1 + +r_out: + jr ra + move a2, zero + +r_end_bytes_up: + lb t0, (a1) + SUB a2, a2, 0x1 + sb t0, (a0) + ADD a1, a1, 0x1 + bnez a2, r_end_bytes_up + ADD a0, a0, 0x1 + + jr ra + move a2, zero + END(__rmemcpy) diff --git a/arch/mips/cavium-octeon/serial.c b/arch/mips/cavium-octeon/serial.c new file mode 100644 index 0000000..8240728 --- /dev/null +++ b/arch/mips/cavium-octeon/serial.c @@ -0,0 +1,136 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2004-2007 Cavium Networks + */ +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include + +#ifdef CONFIG_GDB_CONSOLE +#define DEBUG_UART 0 +#else +#define DEBUG_UART 1 +#endif + +unsigned int octeon_serial_in(struct uart_port *up, int offset) +{ + int rv = cvmx_read_csr((uint64_t)(up->membase + (offset << 3))); + if (offset == UART_IIR && (rv & 0xf) == 7) { + /* Busy interrupt, read the USR (39) and try again. */ + cvmx_read_csr((uint64_t)(up->membase + (39 << 3))); + rv = cvmx_read_csr((uint64_t)(up->membase + (offset << 3))); + } + return rv; +} + +void octeon_serial_out(struct uart_port *up, int offset, int value) +{ + /* + * If bits 6 or 7 of the OCTEON UART's LCR are set, it quits + * working. + */ + if (offset == UART_LCR) + value &= 0x9f; + cvmx_write_csr((uint64_t)(up->membase + (offset << 3)), (u8)value); +} + +/* + * Allocated in .bss, so it is all zeroed. + */ +#define OCTEON_MAX_UARTS 3 +static struct plat_serial8250_port octeon_uart8250_data[OCTEON_MAX_UARTS + 1]; +static struct platform_device octeon_uart8250_device = { + .name = "serial8250", + .id = PLAT8250_DEV_PLATFORM, + .dev = { + .platform_data = octeon_uart8250_data, + }, +}; + +static void __init octeon_uart_set_common(struct plat_serial8250_port *p) +{ + p->flags = ASYNC_SKIP_TEST | UPF_SHARE_IRQ | UPF_FIXED_TYPE; + p->type = PORT_OCTEON; + p->iotype = UPIO_MEM; + p->regshift = 3; /* I/O addresses are every 8 bytes */ + p->uartclk = mips_hpt_frequency; + p->serial_in = octeon_serial_in; + p->serial_out = octeon_serial_out; +} + +static int __init octeon_serial_init(void) +{ + int enable_uart0; + int enable_uart1; + int enable_uart2; + struct plat_serial8250_port *p; + +#ifdef CONFIG_CAVIUM_OCTEON_2ND_KERNEL + /* + * If we are configured to run as the second of two kernels, + * disable uart0 and enable uart1. Uart0 is owned by the first + * kernel + */ + enable_uart0 = 0; + enable_uart1 = 1; +#else + /* + * We are configured for the first kernel. We'll enable uart0 + * if the bootloader told us to use 0, otherwise will enable + * uart 1. + */ + enable_uart0 = (octeon_get_boot_uart() == 0); + enable_uart1 = (octeon_get_boot_uart() == 1); +#ifdef CONFIG_KGDB + enable_uart1 = 1; +#endif +#endif + + /* Right now CN52XX is the only chip with a third uart */ + enable_uart2 = OCTEON_IS_MODEL(OCTEON_CN52XX); + + p = octeon_uart8250_data; + if (enable_uart0) { + /* Add a ttyS device for hardware uart 0 */ + octeon_uart_set_common(p); + p->membase = (void *) CVMX_MIO_UARTX_RBR(0); + p->mapbase = CVMX_MIO_UARTX_RBR(0) & ((1ull << 49) - 1); + p->irq = OCTEON_IRQ_UART0; + p++; + } + + if (enable_uart1) { + /* Add a ttyS device for hardware uart 1 */ + octeon_uart_set_common(p); + p->membase = (void *) CVMX_MIO_UARTX_RBR(1); + p->mapbase = CVMX_MIO_UARTX_RBR(1) & ((1ull << 49) - 1); + p->irq = OCTEON_IRQ_UART1; + p++; + } + if (enable_uart2) { + /* Add a ttyS device for hardware uart 2 */ + octeon_uart_set_common(p); + p->membase = (void *) CVMX_MIO_UART2_RBR; + p->mapbase = CVMX_MIO_UART2_RBR & ((1ull << 49) - 1); + p->irq = OCTEON_IRQ_UART2; + p++; + } + + BUG_ON(p > &octeon_uart8250_data[OCTEON_MAX_UARTS]); + + return platform_device_register(&octeon_uart8250_device); +} + +device_initcall(octeon_serial_init); diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c new file mode 100644 index 0000000..e085fed --- /dev/null +++ b/arch/mips/cavium-octeon/setup.c @@ -0,0 +1,929 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2004-2007 Cavium Networks + * Copyright (C) 2008 Wind River Systems + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include /* for memset */ +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#ifdef CONFIG_CAVIUM_DECODE_RSL +extern void cvmx_interrupt_rsl_decode(void); +extern int __cvmx_interrupt_ecc_report_single_bit_errors; +extern void cvmx_interrupt_rsl_enable(void); +#endif + +extern struct plat_smp_ops octeon_smp_ops; + +#ifdef CONFIG_PCI +extern void pci_console_init(const char *arg); +#endif + +#ifdef CONFIG_CAVIUM_RESERVE32 +extern uint64_t octeon_reserve32_memory; +#endif +static unsigned long long MAX_MEMORY = 512ull << 20; + +struct octeon_boot_descriptor *octeon_boot_desc_ptr; + +struct cvmx_bootinfo *octeon_bootinfo; +EXPORT_SYMBOL(octeon_bootinfo); + +#ifdef CONFIG_CAVIUM_RESERVE32 +uint64_t octeon_reserve32_memory; +EXPORT_SYMBOL(octeon_reserve32_memory); +#endif + +static int octeon_uart; + +extern asmlinkage void handle_int(void); +extern asmlinkage void plat_irq_dispatch(void); + +/** + * Return non zero if we are currently running in the Octeon simulator + * + * Returns + */ +int octeon_is_simulation(void) +{ + return octeon_bootinfo->board_type == CVMX_BOARD_TYPE_SIM; +} +EXPORT_SYMBOL(octeon_is_simulation); + +/** + * Return true if Octeon is in PCI Host mode. This means + * Linux can control the PCI bus. + * + * Returns Non zero if Octeon in host mode. + */ +int octeon_is_pci_host(void) +{ +#ifdef CONFIG_PCI + return octeon_bootinfo->config_flags & CVMX_BOOTINFO_CFG_FLAG_PCI_HOST; +#else + return 0; +#endif +} + +/** + * Get the clock rate of Octeon + * + * Returns Clock rate in HZ + */ +uint64_t octeon_get_clock_rate(void) +{ + if (octeon_is_simulation()) + octeon_bootinfo->eclock_hz = 6000000; + return octeon_bootinfo->eclock_hz; +} +EXPORT_SYMBOL(octeon_get_clock_rate); + +/** + * Write to the LCD display connected to the bootbus. This display + * exists on most Cavium evaluation boards. If it doesn't exist, then + * this function doesn't do anything. + * + * @s: String to write + */ +void octeon_write_lcd(const char *s) +{ + if (octeon_bootinfo->led_display_base_addr) { + void __iomem *lcd_address = + ioremap_nocache(octeon_bootinfo->led_display_base_addr, + 8); + int i; + for (i = 0; i < 8; i++, s++) { + if (*s) + iowrite8(*s, lcd_address + i); + else + iowrite8(' ', lcd_address + i); + } + iounmap(lcd_address); + } +} + +/** + * Return the console uart passed by the bootloader + * + * Returns uart (0 or 1) + */ +int octeon_get_boot_uart(void) +{ + int uart; +#ifdef CONFIG_CAVIUM_OCTEON_2ND_KERNEL + uart = 1; +#else + uart = (octeon_boot_desc_ptr->flags & OCTEON_BL_FLAG_CONSOLE_UART1) ? + 1 : 0; +#endif + return uart; +} + +/** + * Get the coremask Linux was booted on. + * + * Returns Core mask + */ +int octeon_get_boot_coremask(void) +{ + return octeon_boot_desc_ptr->core_mask; +} + +/** + * Check the hardware BIST results for a CPU + */ +void octeon_check_cpu_bist(void) +{ + const int coreid = cvmx_get_core_num(); + unsigned long long mask; + unsigned long long bist_val; + + /* Check BIST results for COP0 registers */ + mask = 0x1f00000000ull; + bist_val = read_octeon_c0_icacheerr(); + if (bist_val & mask) + pr_err("Core%d BIST Failure: CacheErr(icache) = 0x%llx\n", + coreid, bist_val); + + bist_val = read_octeon_c0_dcacheerr(); + if (bist_val & 1) + pr_err("Core%d L1 Dcache parity error: " + "CacheErr(dcache) = 0x%llx\n", + coreid, bist_val); + + mask = 0xfc00000000000000ull; + bist_val = read_c0_cvmmemctl(); + if (bist_val & mask) + pr_err("Core%d BIST Failure: COP0_CVM_MEM_CTL = 0x%llx\n", + coreid, bist_val); + + write_octeon_c0_dcacheerr(0); +} + +#ifdef CONFIG_CAVIUM_RESERVE32_USE_WIRED_TLB +/** + * Called on every core to setup the wired tlb entry needed + * if CONFIG_CAVIUM_RESERVE32_USE_WIRED_TLB is set. + * + */ +static void octeon_hal_setup_per_cpu_reserved32(void *unused) +{ + /* + * The config has selected to wire the reserve32 memory for all + * userspace applications. We need to put a wired TLB entry in for each + * 512MB of reserve32 memory. We only handle double 256MB pages here, + * so reserve32 must be multiple of 512MB. + */ + uint32_t size = CONFIG_CAVIUM_RESERVE32; + uint32_t entrylo0 = + 0x7 | ((octeon_reserve32_memory & ((1ul << 40) - 1)) >> 6); + uint32_t entrylo1 = entrylo0 + (256 << 14); + uint32_t entryhi = (0x80000000UL - (CONFIG_CAVIUM_RESERVE32 << 20)); + while (size >= 512) { +#if 0 + pr_info("CPU%d: Adding double wired TLB entry for 0x%lx\n", + smp_processor_id(), entryhi); +#endif + add_wired_entry(entrylo0, entrylo1, entryhi, PM_256M); + entrylo0 += 512 << 14; + entrylo1 += 512 << 14; + entryhi += 512 << 20; + size -= 512; + } +} +#endif /* CONFIG_CAVIUM_RESERVE32_USE_WIRED_TLB */ + +/** + * Called to release the named block which was used to made sure + * that nobody used the memory for something else during + * init. Now we'll free it so userspace apps can use this + * memory region with bootmem_alloc. + * + * This function is called only once from prom_free_prom_memory(). + */ +void octeon_hal_setup_reserved32(void) +{ +#ifdef CONFIG_CAVIUM_RESERVE32_USE_WIRED_TLB + on_each_cpu(octeon_hal_setup_per_cpu_reserved32, NULL, 0, 1); +#endif +} + +/** + * Reboot Octeon + * + * @command: Command to pass to the bootloader. Currently ignored. + */ +static void octeon_restart(char *command) +{ + /* Disable all watchdogs before soft reset. They don't get cleared */ +#ifdef CONFIG_SMP + int cpu; + for_each_online_cpu(cpu) + cvmx_write_csr(CVMX_CIU_WDOGX(cpu_logical_map(cpu)), 0); +#else + cvmx_write_csr(CVMX_CIU_WDOGX(cvmx_get_core_num()), 0); +#endif + + mb(); + while (1) + cvmx_write_csr(CVMX_CIU_SOFT_RST, 1); +} + + +/** + * Permanently stop a core. + * + * @arg: Ignored. + */ +static void octeon_kill_core(void *arg) +{ + mb(); + if (octeon_is_simulation()) { + /* The simulator needs the watchdog to stop for dead cores */ + cvmx_write_csr(CVMX_CIU_WDOGX(cvmx_get_core_num()), 0); + /* A break instruction causes the simulator stop a core */ + asm volatile ("sync\nbreak"); + } +} + + +/** + * Halt the system + */ +static void octeon_halt(void) +{ + smp_call_function(octeon_kill_core, NULL, 0); + + switch (octeon_bootinfo->board_type) { + case CVMX_BOARD_TYPE_NAO38: + /* Driving a 1 to GPIO 12 shuts off this board */ + cvmx_write_csr(CVMX_GPIO_BIT_CFGX(12), 1); + cvmx_write_csr(CVMX_GPIO_TX_SET, 0x1000); + break; + default: + octeon_write_lcd("PowerOff"); + break; + } + + octeon_kill_core(NULL); +} + +#if 0 +/** + * Platform time init specifics. + * Returns + */ +void __init plat_time_init(void) +{ + /* Nothing special here, but we are required to have one */ +} + +#endif + +/** + * Handle all the error condition interrupts that might occur. + * + */ +#ifdef CONFIG_CAVIUM_DECODE_RSL +static irqreturn_t octeon_rlm_interrupt(int cpl, void *dev_id) +{ + cvmx_interrupt_rsl_decode(); + return IRQ_HANDLED; +} +#endif + +/** + * Return a string representing the system type + * + * Returns + */ +const char *octeon_board_type_string(void) +{ + static char name[80]; + sprintf(name, "%s (%s)", + cvmx_board_type_to_string(octeon_bootinfo->board_type), + octeon_model_get_string(read_c0_prid())); + return name; +} + +const char *get_system_type(void) + __attribute__ ((alias("octeon_board_type_string"))); + +void octeon_user_io_init(void) +{ + union octeon_cvmemctl cvmmemctl; + union cvmx_iob_fau_timeout fau_timeout; + union cvmx_pow_nw_tim nm_tim; + uint64_t cvmctl; + + /* Get the current settings for CP0_CVMMEMCTL_REG */ + cvmmemctl.u64 = read_c0_cvmmemctl(); + /* R/W If set, marked write-buffer entries time out the same + * as as other entries; if clear, marked write-buffer entries + * use the maximum timeout. */ + cvmmemctl.s.dismarkwblongto = 1; + /* R/W If set, a merged store does not clear the write-buffer + * entry timeout state. */ + cvmmemctl.s.dismrgclrwbto = 0; + /* R/W Two bits that are the MSBs of the resultant CVMSEG LM + * word location for an IOBDMA. The other 8 bits come from the + * SCRADDR field of the IOBDMA. */ + cvmmemctl.s.iobdmascrmsb = 0; + /* R/W If set, SYNCWS and SYNCS only order marked stores; if + * clear, SYNCWS and SYNCS only order unmarked + * stores. SYNCWSMARKED has no effect when DISSYNCWS is + * set. */ + cvmmemctl.s.syncwsmarked = 0; + /* R/W If set, SYNCWS acts as SYNCW and SYNCS acts as SYNC. */ + cvmmemctl.s.dissyncws = 0; + /* R/W If set, no stall happens on write buffer full. */ + if (OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2)) + cvmmemctl.s.diswbfst = 1; + else + cvmmemctl.s.diswbfst = 0; + /* R/W If set (and SX set), supervisor-level loads/stores can + * use XKPHYS addresses with <48>==0 */ + cvmmemctl.s.xkmemenas = 0; + + /* R/W If set (and UX set), user-level loads/stores can use + * XKPHYS addresses with VA<48>==0 */ + cvmmemctl.s.xkmemenau = 0; + + /* R/W If set (and SX set), supervisor-level loads/stores can + * use XKPHYS addresses with VA<48>==1 */ + cvmmemctl.s.xkioenas = 0; + + /* R/W If set (and UX set), user-level loads/stores can use + * XKPHYS addresses with VA<48>==1 */ + cvmmemctl.s.xkioenau = 0; + + /* R/W If set, all stores act as SYNCW (NOMERGE must be set + * when this is set) RW, reset to 0. */ + cvmmemctl.s.allsyncw = 0; + + /* R/W If set, no stores merge, and all stores reach the + * coherent bus in order. */ + cvmmemctl.s.nomerge = 0; + /* R/W Selects the bit in the counter used for DID time-outs 0 + * = 231, 1 = 230, 2 = 229, 3 = 214. Actual time-out is + * between 1x and 2x this interval. For example, with + * DIDTTO=3, expiration interval is between 16K and 32K. */ + cvmmemctl.s.didtto = 0; + /* R/W If set, the (mem) CSR clock never turns off. */ + cvmmemctl.s.csrckalwys = 0; + /* R/W If set, mclk never turns off. */ + cvmmemctl.s.mclkalwys = 0; + /* R/W Selects the bit in the counter used for write buffer + * flush time-outs (WBFLT+11) is the bit position in an + * internal counter used to determine expiration. The write + * buffer expires between 1x and 2x this interval. For + * example, with WBFLT = 0, a write buffer expires between 2K + * and 4K cycles after the write buffer entry is allocated. */ + cvmmemctl.s.wbfltime = 0; + /* R/W If set, do not put Istream in the L2 cache. */ + cvmmemctl.s.istrnol2 = 0; + /* R/W The write buffer threshold. */ + cvmmemctl.s.wbthresh = 10; + /* R/W If set, CVMSEG is available for loads/stores in + * kernel/debug mode. */ +#if CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0 + cvmmemctl.s.cvmsegenak = 1; +#else + cvmmemctl.s.cvmsegenak = 0; +#endif + /* R/W If set, CVMSEG is available for loads/stores in + * supervisor mode. */ + cvmmemctl.s.cvmsegenas = 0; + /* R/W If set, CVMSEG is available for loads/stores in user + * mode. */ + cvmmemctl.s.cvmsegenau = 0; + /* R/W Size of local memory in cache blocks, 54 (6912 bytes) + * is max legal value. */ + cvmmemctl.s.lmemsz = CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE; + + + if (smp_processor_id() == 0) + pr_notice("CVMSEG size: %d cache lines (%d bytes)\n", + CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE, + CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE * 128); + + write_c0_cvmmemctl(cvmmemctl.u64); + + /* Move the performance counter interrupts to IRQ 6 */ + cvmctl = read_c0_cvmctl(); + cvmctl &= ~(7 << 7); + cvmctl |= 6 << 7; + write_c0_cvmctl(cvmctl); + + /* Set a default for the hardware timeouts */ + fau_timeout.u64 = 0; + fau_timeout.s.tout_val = 0xfff; + /* Disable tagwait FAU timeout */ + fau_timeout.s.tout_enb = 0; + cvmx_write_csr(CVMX_IOB_FAU_TIMEOUT, fau_timeout.u64); + + nm_tim.u64 = 0; + /* 4096 cycles */ + nm_tim.s.nw_tim = 3; + cvmx_write_csr(CVMX_POW_NW_TIM, nm_tim.u64); + + write_octeon_c0_icacheerr(0); + write_c0_derraddr1(0); +} + +/** + * Early entry point for arch setup + */ +void __init prom_init(void) +{ + struct cvmx_sysinfo *sysinfo; + const int coreid = cvmx_get_core_num(); + int i; + int argc; + struct uart_port octeon_port; +#ifdef CONFIG_CAVIUM_RESERVE32 + int64_t addr = -1; +#endif + /* + * The bootloader passes a pointer to the boot descriptor in + * $a3, this is available as fw_arg3. + */ + octeon_boot_desc_ptr = (struct octeon_boot_descriptor *)fw_arg3; + octeon_bootinfo = + cvmx_phys_to_ptr(octeon_boot_desc_ptr->cvmx_desc_vaddr); + cvmx_bootmem_init(cvmx_phys_to_ptr(octeon_bootinfo->phy_mem_desc_addr)); + + /* + * Only enable the LED controller if we're running on a CN38XX, CN58XX, + * or CN56XX. The CN30XX and CN31XX don't have an LED controller. + */ + if (!octeon_is_simulation() && + octeon_has_feature(OCTEON_FEATURE_LED_CONTROLLER)) { + cvmx_write_csr(CVMX_LED_EN, 0); + cvmx_write_csr(CVMX_LED_PRT, 0); + cvmx_write_csr(CVMX_LED_DBG, 0); + cvmx_write_csr(CVMX_LED_PRT_FMT, 0); + cvmx_write_csr(CVMX_LED_UDD_CNTX(0), 32); + cvmx_write_csr(CVMX_LED_UDD_CNTX(1), 32); + cvmx_write_csr(CVMX_LED_UDD_DATX(0), 0); + cvmx_write_csr(CVMX_LED_UDD_DATX(1), 0); + cvmx_write_csr(CVMX_LED_EN, 1); + } +#ifdef CONFIG_CAVIUM_RESERVE32 + /* + * We need to temporarily allocate all memory in the reserve32 + * region. This makes sure the kernel doesn't allocate this + * memory when it is getting memory from the + * bootloader. Later, after the memory allocations are + * complete, the reserve32 will be freed. + */ +#ifdef CONFIG_CAVIUM_RESERVE32_USE_WIRED_TLB + if (CONFIG_CAVIUM_RESERVE32 & 0x1ff) + pr_err("CAVIUM_RESERVE32 isn't a multiple of 512MB. " + "This is required if CAVIUM_RESERVE32_USE_WIRED_TLB " + "is set\n"); + else + addr = cvmx_bootmem_phy_named_block_alloc(CONFIG_CAVIUM_RESERVE32 << 20, + 0, 0, 512 << 20, + "CAVIUM_RESERVE32", 0); +#else + /* + * Allocate memory for RESERVED32 aligned on 2MB boundary. This + * is in case we later use hugetlb entries with it. + */ + addr = cvmx_bootmem_phy_named_block_alloc(CONFIG_CAVIUM_RESERVE32 << 20, + 0, 0, 2 << 20, + "CAVIUM_RESERVE32", 0); +#endif + if (addr < 0) + pr_err("Failed to allocate CAVIUM_RESERVE32 memory area\n"); + else + octeon_reserve32_memory = addr; +#endif + +#ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2 + if (cvmx_read_csr(CVMX_L2D_FUS3) & (3ull << 34)) { + pr_info("Skipping L2 locking due to reduced L2 cache size\n"); + } else { + uint32_t ebase = read_c0_ebase() & 0x3ffff000; +#ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_TLB + /* TLB refill */ + cvmx_l2c_lock_mem_region(ebase, 0x100); +#endif +#ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_EXCEPTION + /* General exception */ + cvmx_l2c_lock_mem_region(ebase + 0x180, 0x80); +#endif +#ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_LOW_LEVEL_INTERRUPT + /* Interrupt handler */ + cvmx_l2c_lock_mem_region(ebase + 0x200, 0x80); +#endif +#ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_INTERRUPT + cvmx_l2c_lock_mem_region(__pa_symbol(handle_int), 0x100); + cvmx_l2c_lock_mem_region(__pa_symbol(plat_irq_dispatch), 0x80); +#endif +#ifdef CONFIG_CAVIUM_OCTEON_LOCK_L2_MEMCPY + cvmx_l2c_lock_mem_region(__pa_symbol(memcpy), 0x480); +#endif + } +#endif + + sysinfo = cvmx_sysinfo_get(); + memset(sysinfo, 0, sizeof(*sysinfo)); + sysinfo->system_dram_size = octeon_bootinfo->dram_size << 20; + sysinfo->phy_mem_desc_ptr = + cvmx_phys_to_ptr(octeon_bootinfo->phy_mem_desc_addr); + sysinfo->core_mask = octeon_bootinfo->core_mask; + sysinfo->exception_base_addr = octeon_bootinfo->exception_base_addr; + sysinfo->cpu_clock_hz = octeon_bootinfo->eclock_hz; + sysinfo->dram_data_rate_hz = octeon_bootinfo->dclock_hz * 2; + sysinfo->board_type = octeon_bootinfo->board_type; + sysinfo->board_rev_major = octeon_bootinfo->board_rev_major; + sysinfo->board_rev_minor = octeon_bootinfo->board_rev_minor; + memcpy(sysinfo->mac_addr_base, octeon_bootinfo->mac_addr_base, + sizeof(sysinfo->mac_addr_base)); + sysinfo->mac_addr_count = octeon_bootinfo->mac_addr_count; + memcpy(sysinfo->board_serial_number, + octeon_bootinfo->board_serial_number, + sizeof(sysinfo->board_serial_number)); + sysinfo->compact_flash_common_base_addr = + octeon_bootinfo->compact_flash_common_base_addr; + sysinfo->compact_flash_attribute_base_addr = + octeon_bootinfo->compact_flash_attribute_base_addr; + sysinfo->led_display_base_addr = octeon_bootinfo->led_display_base_addr; + sysinfo->dfa_ref_clock_hz = octeon_bootinfo->dfa_ref_clock_hz; + sysinfo->bootloader_config_flags = octeon_bootinfo->config_flags; + + + octeon_check_cpu_bist(); + + octeon_uart = octeon_get_boot_uart(); + + /* + * Disable All CIU Interrupts. The ones we need will be + * enabled later. Read the SUM register so we know the write + * completed. + */ + cvmx_write_csr(CVMX_CIU_INTX_EN0((coreid * 2)), 0); + cvmx_write_csr(CVMX_CIU_INTX_EN0((coreid * 2 + 1)), 0); + cvmx_write_csr(CVMX_CIU_INTX_EN1((coreid * 2)), 0); + cvmx_write_csr(CVMX_CIU_INTX_EN1((coreid * 2 + 1)), 0); + cvmx_read_csr(CVMX_CIU_INTX_SUM0((coreid * 2))); + +#ifdef CONFIG_SMP + octeon_write_lcd("LinuxSMP"); +#else + octeon_write_lcd("Linux"); +#endif + +#ifdef CONFIG_CAVIUM_GDB + /* + * When debugging the linux kernel, force the cores to enter + * the debug exception handler to break in. + */ + if (octeon_get_boot_debug_flag()) { + cvmx_write_csr(CVMX_CIU_DINT, 1 << cvmx_get_core_num()); + cvmx_read_csr(CVMX_CIU_DINT); + } +#endif + + /* + * BIST should always be enabled when doing a soft reset. L2 + * Cache locking for instance is not cleared unless BIST is + * enabled. Unfortunately due to a chip errata G-200 for + * Cn38XX and CN31XX, BIST msut be disabled on these parts. + */ + if (OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2) || + OCTEON_IS_MODEL(OCTEON_CN31XX)) + cvmx_write_csr(CVMX_CIU_SOFT_BIST, 0); + else + cvmx_write_csr(CVMX_CIU_SOFT_BIST, 1); + + /* Default to 64MB in the simulator to speed things up */ + if (octeon_is_simulation()) + MAX_MEMORY = 64ull << 20; + + arcs_cmdline[0] = 0; + argc = octeon_boot_desc_ptr->argc; + for (i = 0; i < argc; i++) { + const char *arg = + cvmx_phys_to_ptr(octeon_boot_desc_ptr->argv[i]); + if ((strncmp(arg, "MEM=", 4) == 0) || + (strncmp(arg, "mem=", 4) == 0)) { + sscanf(arg + 4, "%llu", &MAX_MEMORY); + MAX_MEMORY <<= 20; + if (MAX_MEMORY == 0) + MAX_MEMORY = 32ull << 30; + } else if (strcmp(arg, "ecc_verbose") == 0) { +#ifdef CONFIG_CAVIUM_REPORT_SINGLE_BIT_ECC + __cvmx_interrupt_ecc_report_single_bit_errors = 1; + pr_notice("Reporting of single bit ECC errors is " + "turned on\n"); +#endif + } else if (strlen(arcs_cmdline) + strlen(arg) + 1 < + sizeof(arcs_cmdline) - 1) { + strcat(arcs_cmdline, " "); + strcat(arcs_cmdline, arg); + } + } + + if (strstr(arcs_cmdline, "console=") == NULL) { +#ifdef CONFIG_GDB_CONSOLE + strcat(arcs_cmdline, " console=gdb"); +#else +#ifdef CONFIG_CAVIUM_OCTEON_2ND_KERNEL + strcat(arcs_cmdline, " console=ttyS0,115200"); +#else + if (octeon_uart == 1) + strcat(arcs_cmdline, " console=ttyS1,115200"); + else + strcat(arcs_cmdline, " console=ttyS0,115200"); +#endif +#endif + } + + if (octeon_is_simulation()) { + /* + * The simulator uses a mtdram device pre filled with + * the filesystem. Also specify the calibration delay + * to avoid calculating it every time. + */ + strcat(arcs_cmdline, " rw root=1f00" + " lpj=60176 slram=root,0x40000000,+1073741824"); + } + + mips_hpt_frequency = octeon_get_clock_rate(); + + octeon_init_cvmcount(); + + _machine_restart = octeon_restart; + _machine_halt = octeon_halt; + + memset(&octeon_port, 0, sizeof(octeon_port)); + /* + * For early_serial_setup we don't set the port type or + * UPF_FIXED_TYPE. + */ + octeon_port.flags = ASYNC_SKIP_TEST | UPF_SHARE_IRQ; + octeon_port.iotype = UPIO_MEM; + /* I/O addresses are every 8 bytes */ + octeon_port.regshift = 3; + /* Clock rate of the chip */ + octeon_port.uartclk = mips_hpt_frequency; + octeon_port.fifosize = 64; + octeon_port.mapbase = 0x0001180000000800ull + (1024 * octeon_uart); + octeon_port.membase = cvmx_phys_to_ptr(octeon_port.mapbase); + octeon_port.serial_in = octeon_serial_in; + octeon_port.serial_out = octeon_serial_out; +#ifdef CONFIG_CAVIUM_OCTEON_2ND_KERNEL + octeon_port.line = 0; +#else + octeon_port.line = octeon_uart; +#endif + octeon_port.irq = 42 + octeon_uart; + early_serial_setup(&octeon_port); + + octeon_user_io_init(); + register_smp_ops(&octeon_smp_ops); +} + +void __init plat_mem_setup(void) +{ + uint64_t mem_alloc_size; + uint64_t total; + int64_t memory; + + total = 0; + + /* First add the init memory we will be returning. */ + memory = __pa_symbol(&__init_begin) & PAGE_MASK; + mem_alloc_size = (__pa_symbol(&__init_end) & PAGE_MASK) - memory; + if (mem_alloc_size > 0) { + add_memory_region(memory, mem_alloc_size, BOOT_MEM_RAM); + total += mem_alloc_size; + } + + /* + * The Mips memory init uses the first memory location for + * some memory vectors. When SPARSEMEM is in use, it doesn't + * verify that the size is big enough for the final + * vectors. Making the smallest chuck 4MB seems to be enough + * to consistantly work. + */ + mem_alloc_size = 4 << 20; + if (mem_alloc_size > MAX_MEMORY) + mem_alloc_size = MAX_MEMORY; + + /* + * When allocating memory, we want incrementing addresses from + * bootmem_alloc so the code in add_memory_region can merge + * regions next to each other. + */ + cvmx_bootmem_lock(); + while ((boot_mem_map.nr_map < BOOT_MEM_MAP_MAX) + && (total < MAX_MEMORY)) { +#if defined(CONFIG_64BIT) || defined(CONFIG_64BIT_PHYS_ADDR) + memory = cvmx_bootmem_phy_alloc(mem_alloc_size, + __pa_symbol(&__init_end), -1, + 0x100000, + CVMX_BOOTMEM_FLAG_NO_LOCKING); +#elif defined(CONFIG_HIGHMEM) + memory = cvmx_bootmem_phy_alloc(mem_alloc_size, 0, 1ull << 31, + 0x100000, + CVMX_BOOTMEM_FLAG_NO_LOCKING); +#else + memory = cvmx_bootmem_phy_alloc(mem_alloc_size, 0, 512 << 20, + 0x100000, + CVMX_BOOTMEM_FLAG_NO_LOCKING); +#endif + if (memory >= 0) { + /* + * This function automatically merges address + * regions next to each other if they are + * received in incrementing order. + */ + add_memory_region(memory, mem_alloc_size, BOOT_MEM_RAM); + total += mem_alloc_size; + } else { + break; + } + } + cvmx_bootmem_unlock(); + +#ifdef CONFIG_CAVIUM_RESERVE32 + /* + * Now that we've allocated the kernel memory it is safe to + * free the reserved region. We free it here so that builtin + * drivers can use the memory. + */ + if (octeon_reserve32_memory) + cvmx_bootmem_free_named("CAVIUM_RESERVE32"); +#endif /* CONFIG_CAVIUM_RESERVE32 */ + + if (total == 0) + panic("Unable to allocate memory from " + "cvmx_bootmem_phy_alloc\n"); +} + + +int prom_putchar(char c) +{ + uint64_t lsrval; + + /* Spin until there is room */ + do { + lsrval = cvmx_read_csr(CVMX_MIO_UARTX_LSR(octeon_uart)); + } while ((lsrval & 0x20) == 0); + + /* Write the byte */ + cvmx_write_csr(CVMX_MIO_UARTX_THR(octeon_uart), c); + return 1; +} + +void prom_free_prom_memory(void) +{ +#ifdef CONFIG_CAVIUM_DECODE_RSL + cvmx_interrupt_rsl_enable(); + + /* Add an interrupt handler for general failures. */ + if (request_irq(OCTEON_IRQ_RML, octeon_rlm_interrupt, IRQF_SHARED, + "RML/RSL", octeon_rlm_interrupt)) { + panic("Unable to request_irq(OCTEON_IRQ_RML)\n"); + } +#endif + + /* This call is here so that it is performed after any TLB + initializations. It needs to be after these in case the + CONFIG_CAVIUM_RESERVE32_USE_WIRED_TLB option is set */ + octeon_hal_setup_reserved32(); +} + +static struct octeon_cf_data octeon_cf_data; + +static int __init octeon_cf_device_init(void) +{ + union cvmx_mio_boot_reg_cfgx mio_boot_reg_cfg; + unsigned long base_ptr, region_base, region_size; + struct platform_device *pd; + struct resource cf_resources[3]; + unsigned int num_resources; + int i; + int ret = 0; + + /* Setup octeon-cf platform device if present. */ + base_ptr = 0; + if (octeon_bootinfo->major_version == 1 + && octeon_bootinfo->minor_version >= 1) { + if (octeon_bootinfo->compact_flash_common_base_addr) + base_ptr = + octeon_bootinfo->compact_flash_common_base_addr; + } else { + base_ptr = 0x1d000800; + } + + if (!base_ptr) + return ret; + + /* Find CS0 region. */ + for (i = 0; i < 8; i++) { + mio_boot_reg_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(i)); + region_base = mio_boot_reg_cfg.s.base << 16; + region_size = (mio_boot_reg_cfg.s.size + 1) << 16; + if (mio_boot_reg_cfg.s.en && base_ptr >= region_base + && base_ptr < region_base + region_size) + break; + } + if (i >= 7) { + /* i and i + 1 are CS0 and CS1, both must be less than 8. */ + goto out; + } + octeon_cf_data.base_region = i; + octeon_cf_data.is16bit = mio_boot_reg_cfg.s.width; + octeon_cf_data.base_region_bias = base_ptr - region_base; + memset(cf_resources, 0, sizeof(cf_resources)); + num_resources = 0; + cf_resources[num_resources].flags = IORESOURCE_MEM; + cf_resources[num_resources].start = region_base; + cf_resources[num_resources].end = region_base + region_size - 1; + num_resources++; + + + if (!(base_ptr & 0xfffful)) { + /* + * Boot loader signals availability of DMA (true_ide + * mode) by setting low order bits of base_ptr to + * zero. + */ + + /* Asume that CS1 immediately follows. */ + mio_boot_reg_cfg.u64 = + cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(i + 1)); + region_base = mio_boot_reg_cfg.s.base << 16; + region_size = (mio_boot_reg_cfg.s.size + 1) << 16; + if (!mio_boot_reg_cfg.s.en) + goto out; + + cf_resources[num_resources].flags = IORESOURCE_MEM; + cf_resources[num_resources].start = region_base; + cf_resources[num_resources].end = region_base + region_size - 1; + num_resources++; + + octeon_cf_data.dma_engine = 0; + cf_resources[num_resources].flags = IORESOURCE_IRQ; + cf_resources[num_resources].start = OCTEON_IRQ_BOOTDMA; + cf_resources[num_resources].end = OCTEON_IRQ_BOOTDMA; + num_resources++; + } else { + octeon_cf_data.dma_engine = -1; + } + + pd = platform_device_alloc("pata_octeon_cf", -1); + if (!pd) { + ret = -ENOMEM; + goto out; + } + pd->dev.platform_data = &octeon_cf_data; + + ret = platform_device_add_resources(pd, cf_resources, num_resources); + if (ret) + goto fail; + + ret = platform_device_add(pd); + if (ret) + goto fail; + + return ret; +fail: + platform_device_put(pd); +out: + return ret; +} +device_initcall(octeon_cf_device_init); diff --git a/arch/mips/cavium-octeon/smp.c b/arch/mips/cavium-octeon/smp.c new file mode 100644 index 0000000..24e0ad6 --- /dev/null +++ b/arch/mips/cavium-octeon/smp.c @@ -0,0 +1,211 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2004-2008 Cavium Networks + */ +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include + +volatile unsigned long octeon_processor_boot = 0xff; +volatile unsigned long octeon_processor_sp; +volatile unsigned long octeon_processor_gp; + +static irqreturn_t mailbox_interrupt(int irq, void *dev_id) +{ + const int coreid = cvmx_get_core_num(); + uint64_t action; + + /* Load the mailbox register to figure out what we're supposed to do */ + action = cvmx_read_csr(CVMX_CIU_MBOX_CLRX(coreid)); + + /* Clear the mailbox to clear the interrupt */ + cvmx_write_csr(CVMX_CIU_MBOX_CLRX(coreid), action); + + if (action & SMP_CALL_FUNCTION) + smp_call_function_interrupt(); + + /* Check if we've been told to flush the icache */ + if (action & SMP_ICACHE_FLUSH) + asm volatile ("synci 0($0)\n"); + return IRQ_HANDLED; +} + +/** + * Cause the function described by call_data to be executed on the passed + * cpu. When the function has finished, increment the finished field of + * call_data. + */ +void octeon_send_ipi_single(int cpu, unsigned int action) +{ + int coreid = cpu_logical_map(cpu); + /* + pr_info("SMP: Mailbox send cpu=%d, coreid=%d, action=%u\n", cpu, + coreid, action); + */ + cvmx_write_csr(CVMX_CIU_MBOX_SETX(coreid), action); +} + +static inline void octeon_send_ipi_mask(cpumask_t mask, unsigned int action) +{ + unsigned int i; + + for_each_cpu_mask(i, mask) + octeon_send_ipi_single(i, action); +} + +/** + * Detect available CPUs, populate phys_cpu_present_map + */ +static void octeon_smp_setup(void) +{ + const int coreid = cvmx_get_core_num(); + int cpus; + int id; + + int core_mask = octeon_get_boot_coremask(); + + cpus_clear(cpu_possible_map); + __cpu_number_map[coreid] = 0; + __cpu_logical_map[0] = coreid; + cpu_set(0, cpu_possible_map); + + cpus = 1; + for (id = 0; id < 16; id++) { + if ((id != coreid) && (core_mask & (1 << id))) { + cpu_set(cpus, cpu_possible_map); + __cpu_number_map[id] = cpus; + __cpu_logical_map[cpus] = id; + cpus++; + } + } +} + +/** + * Firmware CPU startup hook + * + */ +static void octeon_boot_secondary(int cpu, struct task_struct *idle) +{ + int count; + + pr_info("SMP: Booting CPU%02d (CoreId %2d)...\n", cpu, + cpu_logical_map(cpu)); + + octeon_processor_sp = __KSTK_TOS(idle); + octeon_processor_gp = (unsigned long)(task_thread_info(idle)); + octeon_processor_boot = cpu_logical_map(cpu); + mb(); + + count = 10000; + while (octeon_processor_sp && count) { + /* Waiting for processor to get the SP and GP */ + udelay(1); + count--; + } + if (count == 0) + pr_err("Secondary boot timeout\n"); +} + +/** + * After we've done initial boot, this function is called to allow the + * board code to clean up state, if needed + */ +static void octeon_init_secondary(void) +{ + const int coreid = cvmx_get_core_num(); + union cvmx_ciu_intx_sum0 interrupt_enable; + + octeon_check_cpu_bist(); + octeon_init_cvmcount(); + /* + pr_info("SMP: CPU%d (CoreId %lu) started\n", cpu, coreid); + */ + /* Enable Mailbox interrupts to this core. These are the only + interrupts allowed on line 3 */ + cvmx_write_csr(CVMX_CIU_MBOX_CLRX(coreid), 0xffffffff); + interrupt_enable.u64 = 0; + interrupt_enable.s.mbox = 0x3; + cvmx_write_csr(CVMX_CIU_INTX_EN0((coreid * 2)), interrupt_enable.u64); + cvmx_write_csr(CVMX_CIU_INTX_EN0((coreid * 2 + 1)), 0); + cvmx_write_csr(CVMX_CIU_INTX_EN1((coreid * 2)), 0); + cvmx_write_csr(CVMX_CIU_INTX_EN1((coreid * 2 + 1)), 0); + /* Enable core interrupt processing for 2,3 and 7 */ + set_c0_status(0x8c01); +} + +/** + * Callout to firmware before smp_init + * + */ +void octeon_prepare_cpus(unsigned int max_cpus) +{ + cvmx_write_csr(CVMX_CIU_MBOX_CLRX(cvmx_get_core_num()), 0xffffffff); + if (request_irq(OCTEON_IRQ_MBOX0, mailbox_interrupt, IRQF_SHARED, + "mailbox0", mailbox_interrupt)) { + panic("Cannot request_irq(OCTEON_IRQ_MBOX0)\n"); + } + if (request_irq(OCTEON_IRQ_MBOX1, mailbox_interrupt, IRQF_SHARED, + "mailbox1", mailbox_interrupt)) { + panic("Cannot request_irq(OCTEON_IRQ_MBOX1)\n"); + } +} + +/** + * Last chance for the board code to finish SMP initialization before + * the CPU is "online". + */ +static void octeon_smp_finish(void) +{ +#ifdef CONFIG_CAVIUM_GDB + unsigned long tmp; + /* Pulse MCD0 signal on Ctrl-C to stop all the cores. Also set the MCD0 + to be not masked by this core so we know the signal is received by + someone */ + asm volatile ("dmfc0 %0, $22\n" + "ori %0, %0, 0x9100\n" "dmtc0 %0, $22\n" : "=r" (tmp)); +#endif + + octeon_user_io_init(); + + /* to generate the first CPU timer interrupt */ + write_c0_compare(read_c0_count() + mips_hpt_frequency / HZ); +} + +/** + * Hook for after all CPUs are online + */ +static void octeon_cpus_done(void) +{ +#ifdef CONFIG_CAVIUM_GDB + unsigned long tmp; + /* Pulse MCD0 signal on Ctrl-C to stop all the cores. Also set the MCD0 + to be not masked by this core so we know the signal is received by + someone */ + asm volatile ("dmfc0 %0, $22\n" + "ori %0, %0, 0x9100\n" "dmtc0 %0, $22\n" : "=r" (tmp)); +#endif +} + +struct plat_smp_ops octeon_smp_ops = { + .send_ipi_single = octeon_send_ipi_single, + .send_ipi_mask = octeon_send_ipi_mask, + .init_secondary = octeon_init_secondary, + .smp_finish = octeon_smp_finish, + .cpus_done = octeon_cpus_done, + .boot_secondary = octeon_boot_secondary, + .smp_setup = octeon_smp_setup, + .prepare_cpus = octeon_prepare_cpus, +}; diff --git a/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h new file mode 100644 index 0000000..04ce6e6 --- /dev/null +++ b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h @@ -0,0 +1,78 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2004 Cavium Networks + */ +#ifndef __ASM_MACH_CAVIUM_OCTEON_CPU_FEATURE_OVERRIDES_H +#define __ASM_MACH_CAVIUM_OCTEON_CPU_FEATURE_OVERRIDES_H + +#include +#include + +/* + * Cavium Octeons are MIPS64v2 processors + */ +#define cpu_dcache_line_size() 128 +#define cpu_icache_line_size() 128 + + +#define cpu_has_4kex 1 +#define cpu_has_3k_cache 0 +#define cpu_has_4k_cache 0 +#define cpu_has_tx39_cache 0 +#define cpu_has_fpu 0 +#define cpu_has_counter 1 +#define cpu_has_watch 1 +#define cpu_has_divec 1 +#define cpu_has_vce 0 +#define cpu_has_cache_cdex_p 0 +#define cpu_has_cache_cdex_s 0 +#define cpu_has_prefetch 1 + +/* + * We should disable LL/SC on non SMP systems as it is faster to + * disable interrupts for atomic access than a LL/SC. Unfortunatly we + * cannot as this breaks asm/futex.h + */ +#define cpu_has_llsc 1 +#define cpu_has_vtag_icache 1 +#define cpu_has_dc_aliases 0 +#define cpu_has_ic_fills_f_dc 0 +#define cpu_has_64bits 1 +#define cpu_has_octeon_cache 1 +#define cpu_has_saa octeon_has_saa() +#define cpu_has_mips32r1 0 +#define cpu_has_mips32r2 0 +#define cpu_has_mips64r1 0 +#define cpu_has_mips64r2 1 +#define cpu_has_dsp 0 +#define cpu_has_mipsmt 0 +#define cpu_has_userlocal 0 +#define cpu_has_vint 0 +#define cpu_has_veic 0 +#define ARCH_HAS_READ_CURRENT_TIMER 1 +#define ARCH_HAS_IRQ_PER_CPU 1 +#define ARCH_HAS_SPINLOCK_PREFETCH 1 +#define spin_lock_prefetch(x) prefetch(x) +#define PREFETCH_STRIDE 128 + +static inline int read_current_timer(unsigned long *result) +{ + asm volatile ("rdhwr %0,$31\n" +#ifndef CONFIG_64BIT + "\tsll %0, 0" +#endif + : "=r" (*result)); + return 0; +} + +static inline int octeon_has_saa(void) +{ + int id; + asm volatile ("mfc0 %0, $15,0" : "=r" (id)); + return id >= 0x000d0300; +} + +#endif diff --git a/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h b/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h new file mode 100644 index 0000000..f30fce9 --- /dev/null +++ b/arch/mips/include/asm/mach-cavium-octeon/dma-coherence.h @@ -0,0 +1,64 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2006 Ralf Baechle + * + * + * Similar to mach-generic/dma-coherence.h except + * plat_device_is_coherent hard coded to return 1. + * + */ +#ifndef __ASM_MACH_CAVIUM_OCTEON_DMA_COHERENCE_H +#define __ASM_MACH_CAVIUM_OCTEON_DMA_COHERENCE_H + +struct device; + +dma_addr_t octeon_map_dma_mem(struct device *, void *, size_t); +void octeon_unmap_dma_mem(struct device *, dma_addr_t); + +static inline dma_addr_t plat_map_dma_mem(struct device *dev, void *addr, + size_t size) +{ + return octeon_map_dma_mem(dev, addr, size); +} + +static inline dma_addr_t plat_map_dma_mem_page(struct device *dev, + struct page *page) +{ + return octeon_map_dma_mem(dev, page_address(page), PAGE_SIZE); +} + +static inline unsigned long plat_dma_addr_to_phys(dma_addr_t dma_addr) +{ + return dma_addr; +} + +static inline void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr) +{ + octeon_unmap_dma_mem(dev, dma_addr); +} + +static inline int plat_dma_supported(struct device *dev, u64 mask) +{ + return 1; +} + +static inline void plat_extra_sync_for_device(struct device *dev) +{ + mb(); +} + +static inline int plat_device_is_coherent(struct device *dev) +{ + return 1; +} + +static inline int plat_dma_mapping_error(struct device *dev, + dma_addr_t dma_addr) +{ + return dma_addr == -1; +} + +#endif /* __ASM_MACH_CAVIUM_OCTEON_DMA_COHERENCE_H */ diff --git a/arch/mips/include/asm/mach-cavium-octeon/irq.h b/arch/mips/include/asm/mach-cavium-octeon/irq.h new file mode 100644 index 0000000..d32220f --- /dev/null +++ b/arch/mips/include/asm/mach-cavium-octeon/irq.h @@ -0,0 +1,244 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2004-2008 Cavium Networks + */ +#ifndef __OCTEON_IRQ_H__ +#define __OCTEON_IRQ_H__ + +#define NR_IRQS OCTEON_IRQ_LAST +#define MIPS_CPU_IRQ_BASE OCTEON_IRQ_SW0 + +/* 0 - 7 represent the i8259 master */ +#define OCTEON_IRQ_I8259M0 0 +#define OCTEON_IRQ_I8259M1 1 +#define OCTEON_IRQ_I8259M2 2 +#define OCTEON_IRQ_I8259M3 3 +#define OCTEON_IRQ_I8259M4 4 +#define OCTEON_IRQ_I8259M5 5 +#define OCTEON_IRQ_I8259M6 6 +#define OCTEON_IRQ_I8259M7 7 +/* 8 - 15 represent the i8259 slave */ +#define OCTEON_IRQ_I8259S0 8 +#define OCTEON_IRQ_I8259S1 9 +#define OCTEON_IRQ_I8259S2 10 +#define OCTEON_IRQ_I8259S3 11 +#define OCTEON_IRQ_I8259S4 12 +#define OCTEON_IRQ_I8259S5 13 +#define OCTEON_IRQ_I8259S6 14 +#define OCTEON_IRQ_I8259S7 15 +/* 16 - 23 represent the 8 MIPS standard interrupt sources */ +#define OCTEON_IRQ_SW0 16 +#define OCTEON_IRQ_SW1 17 +#define OCTEON_IRQ_CIU0 18 +#define OCTEON_IRQ_CIU1 19 +#define OCTEON_IRQ_CIU4 20 +#define OCTEON_IRQ_5 21 +#define OCTEON_IRQ_PERF 22 +#define OCTEON_IRQ_TIMER 23 +/* 24 - 87 represent the sources in CIU_INTX_EN0 */ +#define OCTEON_IRQ_WORKQ0 24 +#define OCTEON_IRQ_WORKQ1 25 +#define OCTEON_IRQ_WORKQ2 26 +#define OCTEON_IRQ_WORKQ3 27 +#define OCTEON_IRQ_WORKQ4 28 +#define OCTEON_IRQ_WORKQ5 29 +#define OCTEON_IRQ_WORKQ6 30 +#define OCTEON_IRQ_WORKQ7 31 +#define OCTEON_IRQ_WORKQ8 32 +#define OCTEON_IRQ_WORKQ9 33 +#define OCTEON_IRQ_WORKQ10 34 +#define OCTEON_IRQ_WORKQ11 35 +#define OCTEON_IRQ_WORKQ12 36 +#define OCTEON_IRQ_WORKQ13 37 +#define OCTEON_IRQ_WORKQ14 38 +#define OCTEON_IRQ_WORKQ15 39 +#define OCTEON_IRQ_GPIO0 40 +#define OCTEON_IRQ_GPIO1 41 +#define OCTEON_IRQ_GPIO2 42 +#define OCTEON_IRQ_GPIO3 43 +#define OCTEON_IRQ_GPIO4 44 +#define OCTEON_IRQ_GPIO5 45 +#define OCTEON_IRQ_GPIO6 46 +#define OCTEON_IRQ_GPIO7 47 +#define OCTEON_IRQ_GPIO8 48 +#define OCTEON_IRQ_GPIO9 49 +#define OCTEON_IRQ_GPIO10 50 +#define OCTEON_IRQ_GPIO11 51 +#define OCTEON_IRQ_GPIO12 52 +#define OCTEON_IRQ_GPIO13 53 +#define OCTEON_IRQ_GPIO14 54 +#define OCTEON_IRQ_GPIO15 55 +#define OCTEON_IRQ_MBOX0 56 +#define OCTEON_IRQ_MBOX1 57 +#define OCTEON_IRQ_UART0 58 +#define OCTEON_IRQ_UART1 59 +#define OCTEON_IRQ_PCI_INT0 60 +#define OCTEON_IRQ_PCI_INT1 61 +#define OCTEON_IRQ_PCI_INT2 62 +#define OCTEON_IRQ_PCI_INT3 63 +#define OCTEON_IRQ_PCI_MSI0 64 +#define OCTEON_IRQ_PCI_MSI1 65 +#define OCTEON_IRQ_PCI_MSI2 66 +#define OCTEON_IRQ_PCI_MSI3 67 +#define OCTEON_IRQ_RESERVED68 68 /* Summary of CIU_INT_SUM1 */ +#define OCTEON_IRQ_TWSI 69 +#define OCTEON_IRQ_RML 70 +#define OCTEON_IRQ_TRACE 71 +#define OCTEON_IRQ_GMX_DRP0 72 +#define OCTEON_IRQ_GMX_DRP1 73 +#define OCTEON_IRQ_IPD_DRP 74 +#define OCTEON_IRQ_KEY_ZERO 75 +#define OCTEON_IRQ_TIMER0 76 +#define OCTEON_IRQ_TIMER1 77 +#define OCTEON_IRQ_TIMER2 78 +#define OCTEON_IRQ_TIMER3 79 +#define OCTEON_IRQ_USB0 80 +#define OCTEON_IRQ_PCM 81 +#define OCTEON_IRQ_MPI 82 +#define OCTEON_IRQ_TWSI2 83 +#define OCTEON_IRQ_POWIQ 84 +#define OCTEON_IRQ_IPDPPTHR 85 +#define OCTEON_IRQ_MII0 86 +#define OCTEON_IRQ_BOOTDMA 87 +/* 88 - 151 represent the sources in CIU_INTX_EN1 */ +#define OCTEON_IRQ_WDOG0 88 +#define OCTEON_IRQ_WDOG1 89 +#define OCTEON_IRQ_WDOG2 90 +#define OCTEON_IRQ_WDOG3 91 +#define OCTEON_IRQ_WDOG4 92 +#define OCTEON_IRQ_WDOG5 93 +#define OCTEON_IRQ_WDOG6 94 +#define OCTEON_IRQ_WDOG7 95 +#define OCTEON_IRQ_WDOG8 96 +#define OCTEON_IRQ_WDOG9 97 +#define OCTEON_IRQ_WDOG10 98 +#define OCTEON_IRQ_WDOG11 99 +#define OCTEON_IRQ_WDOG12 100 +#define OCTEON_IRQ_WDOG13 101 +#define OCTEON_IRQ_WDOG14 102 +#define OCTEON_IRQ_WDOG15 103 +#define OCTEON_IRQ_UART2 104 +#define OCTEON_IRQ_USB1 105 +#define OCTEON_IRQ_MII1 106 +#define OCTEON_IRQ_RESERVED107 107 +#define OCTEON_IRQ_RESERVED108 108 +#define OCTEON_IRQ_RESERVED109 109 +#define OCTEON_IRQ_RESERVED110 110 +#define OCTEON_IRQ_RESERVED111 111 +#define OCTEON_IRQ_RESERVED112 112 +#define OCTEON_IRQ_RESERVED113 113 +#define OCTEON_IRQ_RESERVED114 114 +#define OCTEON_IRQ_RESERVED115 115 +#define OCTEON_IRQ_RESERVED116 116 +#define OCTEON_IRQ_RESERVED117 117 +#define OCTEON_IRQ_RESERVED118 118 +#define OCTEON_IRQ_RESERVED119 119 +#define OCTEON_IRQ_RESERVED120 120 +#define OCTEON_IRQ_RESERVED121 121 +#define OCTEON_IRQ_RESERVED122 122 +#define OCTEON_IRQ_RESERVED123 123 +#define OCTEON_IRQ_RESERVED124 124 +#define OCTEON_IRQ_RESERVED125 125 +#define OCTEON_IRQ_RESERVED126 126 +#define OCTEON_IRQ_RESERVED127 127 +#define OCTEON_IRQ_RESERVED128 128 +#define OCTEON_IRQ_RESERVED129 129 +#define OCTEON_IRQ_RESERVED130 130 +#define OCTEON_IRQ_RESERVED131 131 +#define OCTEON_IRQ_RESERVED132 132 +#define OCTEON_IRQ_RESERVED133 133 +#define OCTEON_IRQ_RESERVED134 134 +#define OCTEON_IRQ_RESERVED135 135 +#define OCTEON_IRQ_RESERVED136 136 +#define OCTEON_IRQ_RESERVED137 137 +#define OCTEON_IRQ_RESERVED138 138 +#define OCTEON_IRQ_RESERVED139 139 +#define OCTEON_IRQ_RESERVED140 140 +#define OCTEON_IRQ_RESERVED141 141 +#define OCTEON_IRQ_RESERVED142 142 +#define OCTEON_IRQ_RESERVED143 143 +#define OCTEON_IRQ_RESERVED144 144 +#define OCTEON_IRQ_RESERVED145 145 +#define OCTEON_IRQ_RESERVED146 146 +#define OCTEON_IRQ_RESERVED147 147 +#define OCTEON_IRQ_RESERVED148 148 +#define OCTEON_IRQ_RESERVED149 149 +#define OCTEON_IRQ_RESERVED150 150 +#define OCTEON_IRQ_RESERVED151 151 + +#ifdef CONFIG_PCI_MSI +/* 152 - 215 represent the MSI interrupts 0-63 */ +#define OCTEON_IRQ_MSI_BIT0 152 +#define OCTEON_IRQ_MSI_BIT1 153 +#define OCTEON_IRQ_MSI_BIT2 154 +#define OCTEON_IRQ_MSI_BIT3 155 +#define OCTEON_IRQ_MSI_BIT4 156 +#define OCTEON_IRQ_MSI_BIT5 157 +#define OCTEON_IRQ_MSI_BIT6 158 +#define OCTEON_IRQ_MSI_BIT7 159 +#define OCTEON_IRQ_MSI_BIT8 160 +#define OCTEON_IRQ_MSI_BIT9 161 +#define OCTEON_IRQ_MSI_BIT10 162 +#define OCTEON_IRQ_MSI_BIT11 163 +#define OCTEON_IRQ_MSI_BIT12 164 +#define OCTEON_IRQ_MSI_BIT13 165 +#define OCTEON_IRQ_MSI_BIT14 166 +#define OCTEON_IRQ_MSI_BIT15 167 +#define OCTEON_IRQ_MSI_BIT16 168 +#define OCTEON_IRQ_MSI_BIT17 169 +#define OCTEON_IRQ_MSI_BIT18 170 +#define OCTEON_IRQ_MSI_BIT19 171 +#define OCTEON_IRQ_MSI_BIT20 172 +#define OCTEON_IRQ_MSI_BIT21 173 +#define OCTEON_IRQ_MSI_BIT22 174 +#define OCTEON_IRQ_MSI_BIT23 175 +#define OCTEON_IRQ_MSI_BIT24 176 +#define OCTEON_IRQ_MSI_BIT25 177 +#define OCTEON_IRQ_MSI_BIT26 178 +#define OCTEON_IRQ_MSI_BIT27 179 +#define OCTEON_IRQ_MSI_BIT28 180 +#define OCTEON_IRQ_MSI_BIT29 181 +#define OCTEON_IRQ_MSI_BIT30 182 +#define OCTEON_IRQ_MSI_BIT31 183 +#define OCTEON_IRQ_MSI_BIT32 184 +#define OCTEON_IRQ_MSI_BIT33 185 +#define OCTEON_IRQ_MSI_BIT34 186 +#define OCTEON_IRQ_MSI_BIT35 187 +#define OCTEON_IRQ_MSI_BIT36 188 +#define OCTEON_IRQ_MSI_BIT37 189 +#define OCTEON_IRQ_MSI_BIT38 190 +#define OCTEON_IRQ_MSI_BIT39 191 +#define OCTEON_IRQ_MSI_BIT40 192 +#define OCTEON_IRQ_MSI_BIT41 193 +#define OCTEON_IRQ_MSI_BIT42 194 +#define OCTEON_IRQ_MSI_BIT43 195 +#define OCTEON_IRQ_MSI_BIT44 196 +#define OCTEON_IRQ_MSI_BIT45 197 +#define OCTEON_IRQ_MSI_BIT46 198 +#define OCTEON_IRQ_MSI_BIT47 199 +#define OCTEON_IRQ_MSI_BIT48 200 +#define OCTEON_IRQ_MSI_BIT49 201 +#define OCTEON_IRQ_MSI_BIT50 202 +#define OCTEON_IRQ_MSI_BIT51 203 +#define OCTEON_IRQ_MSI_BIT52 204 +#define OCTEON_IRQ_MSI_BIT53 205 +#define OCTEON_IRQ_MSI_BIT54 206 +#define OCTEON_IRQ_MSI_BIT55 207 +#define OCTEON_IRQ_MSI_BIT56 208 +#define OCTEON_IRQ_MSI_BIT57 209 +#define OCTEON_IRQ_MSI_BIT58 210 +#define OCTEON_IRQ_MSI_BIT59 211 +#define OCTEON_IRQ_MSI_BIT60 212 +#define OCTEON_IRQ_MSI_BIT61 213 +#define OCTEON_IRQ_MSI_BIT62 214 +#define OCTEON_IRQ_MSI_BIT63 215 + +#define OCTEON_IRQ_LAST 216 +#else +#define OCTEON_IRQ_LAST 152 +#endif + +#endif diff --git a/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h b/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h new file mode 100644 index 0000000..0b2b5eb --- /dev/null +++ b/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h @@ -0,0 +1,131 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2005-2008 Cavium Networks, Inc + */ +#ifndef __ASM_MACH_CAVIUM_OCTEON_KERNEL_ENTRY_H +#define __ASM_MACH_CAVIUM_OCTEON_KERNEL_ENTRY_H + + +#define CP0_CYCLE_COUNTER $9, 6 +#define CP0_CVMCTL_REG $9, 7 +#define CP0_CVMMEMCTL_REG $11,7 +#define CP0_PRID_REG $15, 0 +#define CP0_PRID_OCTEON_PASS1 0x000d0000 +#define CP0_PRID_OCTEON_CN30XX 0x000d0200 + +.macro kernel_entry_setup + # Registers set by bootloader: + # (only 32 bits set by bootloader, all addresses are physical + # addresses, and need to have the appropriate memory region set + # by the kernel + # a0 = argc + # a1 = argv (kseg0 compat addr) + # a2 = 1 if init core, zero otherwise + # a3 = address of boot descriptor block + .set push + .set arch=octeon + # Read the cavium mem control register + dmfc0 v0, CP0_CVMMEMCTL_REG + # Clear the lower 6 bits, the CVMSEG size + dins v0, $0, 0, 6 + ori v0, CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE + dmtc0 v0, CP0_CVMMEMCTL_REG # Write the cavium mem control register + dmfc0 v0, CP0_CVMCTL_REG # Read the cavium control register +#ifdef CONFIG_CAVIUM_OCTEON_HW_FIX_UNALIGNED + # Disable unaligned load/store support but leave HW fixup enabled + or v0, v0, 0x5001 + xor v0, v0, 0x1001 +#else + # Disable unaligned load/store and HW fixup support + or v0, v0, 0x5001 + xor v0, v0, 0x5001 +#endif + # Read the processor ID register + mfc0 v1, CP0_PRID_REG + # Disable instruction prefetching (Octeon Pass1 errata) + or v0, v0, 0x2000 + # Skip reenable of prefetching for Octeon Pass1 + beq v1, CP0_PRID_OCTEON_PASS1, skip + nop + # Reenable instruction prefetching, not on Pass1 + xor v0, v0, 0x2000 + # Strip off pass number off of processor id + srl v1, 8 + sll v1, 8 + # CN30XX needs some extra stuff turned off for better performance + bne v1, CP0_PRID_OCTEON_CN30XX, skip + nop + # CN30XX Use random Icache replacement + or v0, v0, 0x400 + # CN30XX Disable instruction prefetching + or v0, v0, 0x2000 +skip: + # Write the cavium control register + dmtc0 v0, CP0_CVMCTL_REG + sync + # Flush dcache after config change + cache 9, 0($0) + # Get my core id + rdhwr v0, $0 + # Jump the master to kernel_entry + bne a2, zero, octeon_main_processor + nop + +#ifdef CONFIG_SMP + + # + # All cores other than the master need to wait here for SMP bootstrap + # to begin + # + + # This is the variable where the next core to boot os stored + PTR_LA t0, octeon_processor_boot +octeon_spin_wait_boot: + # Get the core id of the next to be booted + LONG_L t1, (t0) + # Keep looping if it isn't me + bne t1, v0, octeon_spin_wait_boot + nop + # Get my GP from the global variable + PTR_LA t0, octeon_processor_gp + LONG_L gp, (t0) + # Get my SP from the global variable + PTR_LA t0, octeon_processor_sp + LONG_L sp, (t0) + # Set the SP global variable to zero so the master knows we've started + LONG_S zero, (t0) +#ifdef __OCTEON__ + syncw + syncw +#else + sync +#endif + # Jump to the normal Linux SMP entry point + j smp_bootstrap + nop +#else /* CONFIG_SMP */ + + # + # Someone tried to boot SMP with a non SMP kernel. All extra cores + # will halt here. + # +octeon_wait_forever: + wait + b octeon_wait_forever + nop + +#endif /* CONFIG_SMP */ +octeon_main_processor: + .set pop +.endm + +/* + * Do SMP slave processor setup necessary before we can savely execute C code. + */ + .macro smp_slave_setup + .endm + +#endif /* __ASM_MACH_CAVIUM_OCTEON_KERNEL_ENTRY_H */ diff --git a/arch/mips/include/asm/mach-cavium-octeon/war.h b/arch/mips/include/asm/mach-cavium-octeon/war.h new file mode 100644 index 0000000..c4712d7 --- /dev/null +++ b/arch/mips/include/asm/mach-cavium-octeon/war.h @@ -0,0 +1,26 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2002, 2004, 2007 by Ralf Baechle + * Copyright (C) 2008 Cavium Networks + */ +#ifndef __ASM_MIPS_MACH_CAVIUM_OCTEON_WAR_H +#define __ASM_MIPS_MACH_CAVIUM_OCTEON_WAR_H + +#define R4600_V1_INDEX_ICACHEOP_WAR 0 +#define R4600_V1_HIT_CACHEOP_WAR 0 +#define R4600_V2_HIT_CACHEOP_WAR 0 +#define R5432_CP0_INTERRUPT_WAR 0 +#define BCM1250_M3_WAR 0 +#define SIBYTE_1956_WAR 0 +#define MIPS4K_ICACHE_REFILL_WAR 0 +#define MIPS_CACHE_SYNC_WAR 0 +#define TX49XX_ICACHE_INDEX_INV_WAR 0 +#define RM9000_CDEX_SMP_WAR 0 +#define ICACHE_REFILLS_WORKAROUND_WAR 0 +#define R10000_LLSC_WAR 0 +#define MIPS34K_MISSED_ITLB_WAR 0 + +#endif /* __ASM_MIPS_MACH_CAVIUM_OCTEON_WAR_H */ diff --git a/arch/mips/include/asm/octeon/octeon.h b/arch/mips/include/asm/octeon/octeon.h new file mode 100644 index 0000000..edc6760 --- /dev/null +++ b/arch/mips/include/asm/octeon/octeon.h @@ -0,0 +1,248 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2004-2008 Cavium Networks + */ +#ifndef __ASM_OCTEON_OCTEON_H +#define __ASM_OCTEON_OCTEON_H + +#include "cvmx.h" + +extern uint64_t octeon_bootmem_alloc_range_phys(uint64_t size, + uint64_t alignment, + uint64_t min_addr, + uint64_t max_addr, + int do_locking); +extern void *octeon_bootmem_alloc(uint64_t size, uint64_t alignment, + int do_locking); +extern void *octeon_bootmem_alloc_range(uint64_t size, uint64_t alignment, + uint64_t min_addr, uint64_t max_addr, + int do_locking); +extern void *octeon_bootmem_alloc_named(uint64_t size, uint64_t alignment, + char *name); +extern void *octeon_bootmem_alloc_named_range(uint64_t size, uint64_t min_addr, + uint64_t max_addr, uint64_t align, + char *name); +extern void *octeon_bootmem_alloc_named_address(uint64_t size, uint64_t address, + char *name); +extern int octeon_bootmem_free_named(char *name); +extern void octeon_bootmem_lock(void); +extern void octeon_bootmem_unlock(void); + +extern int octeon_is_simulation(void); +extern int octeon_is_pci_host(void); +extern int octeon_usb_is_ref_clk(void); +extern uint64_t octeon_get_clock_rate(void); +extern const char *octeon_board_type_string(void); +extern const char *octeon_get_pci_interrupts(void); +extern int octeon_get_southbridge_interrupt(void); +extern int octeon_get_boot_coremask(void); +extern int octeon_get_boot_num_arguments(void); +extern const char *octeon_get_boot_argument(int arg); +extern void octeon_hal_setup_reserved32(void); +extern void octeon_user_io_init(void); +struct octeon_cop2_state; +extern unsigned long octeon_crypto_enable(struct octeon_cop2_state *state); +extern void octeon_crypto_disable(struct octeon_cop2_state *state, + unsigned long flags); + +extern void octeon_init_cvmcount(void); + +#define OCTEON_ARGV_MAX_ARGS 64 +#define OCTOEN_SERIAL_LEN 20 + +struct octeon_boot_descriptor { + /* Start of block referenced by assembly code - do not change! */ + uint32_t desc_version; + uint32_t desc_size; + uint64_t stack_top; + uint64_t heap_base; + uint64_t heap_end; + /* Only used by bootloader */ + uint64_t entry_point; + uint64_t desc_vaddr; + /* End of This block referenced by assembly code - do not change! */ + uint32_t exception_base_addr; + uint32_t stack_size; + uint32_t heap_size; + /* Argc count for application. */ + uint32_t argc; + uint32_t argv[OCTEON_ARGV_MAX_ARGS]; + +#define BOOT_FLAG_INIT_CORE (1 << 0) +#define OCTEON_BL_FLAG_DEBUG (1 << 1) +#define OCTEON_BL_FLAG_NO_MAGIC (1 << 2) + /* If set, use uart1 for console */ +#define OCTEON_BL_FLAG_CONSOLE_UART1 (1 << 3) + /* If set, use PCI console */ +#define OCTEON_BL_FLAG_CONSOLE_PCI (1 << 4) + /* Call exit on break on serial port */ +#define OCTEON_BL_FLAG_BREAK (1 << 5) + + uint32_t flags; + uint32_t core_mask; + /* DRAM size in megabyes. */ + uint32_t dram_size; + /* physical address of free memory descriptor block. */ + uint32_t phy_mem_desc_addr; + /* used to pass flags from app to debugger. */ + uint32_t debugger_flags_base_addr; + /* CPU clock speed, in hz. */ + uint32_t eclock_hz; + /* DRAM clock speed, in hz. */ + uint32_t dclock_hz; + /* SPI4 clock in hz. */ + uint32_t spi_clock_hz; + uint16_t board_type; + uint8_t board_rev_major; + uint8_t board_rev_minor; + uint16_t chip_type; + uint8_t chip_rev_major; + uint8_t chip_rev_minor; + char board_serial_number[OCTOEN_SERIAL_LEN]; + uint8_t mac_addr_base[6]; + uint8_t mac_addr_count; + uint64_t cvmx_desc_vaddr; +}; + +union octeon_cvmemctl { + uint64_t u64; + struct { + /* RO 1 = BIST fail, 0 = BIST pass */ + uint64_t tlbbist:1; + /* RO 1 = BIST fail, 0 = BIST pass */ + uint64_t l1cbist:1; + /* RO 1 = BIST fail, 0 = BIST pass */ + uint64_t l1dbist:1; + /* RO 1 = BIST fail, 0 = BIST pass */ + uint64_t dcmbist:1; + /* RO 1 = BIST fail, 0 = BIST pass */ + uint64_t ptgbist:1; + /* RO 1 = BIST fail, 0 = BIST pass */ + uint64_t wbfbist:1; + /* Reserved */ + uint64_t reserved:22; + /* R/W If set, marked write-buffer entries time out + * the same as as other entries; if clear, marked + * write-buffer entries use the maximum timeout. */ + uint64_t dismarkwblongto:1; + /* R/W If set, a merged store does not clear the + * write-buffer entry timeout state. */ + uint64_t dismrgclrwbto:1; + /* R/W Two bits that are the MSBs of the resultant + * CVMSEG LM word location for an IOBDMA. The other 8 + * bits come from the SCRADDR field of the IOBDMA. */ + uint64_t iobdmascrmsb:2; + /* R/W If set, SYNCWS and SYNCS only order marked + * stores; if clear, SYNCWS and SYNCS only order + * unmarked stores. SYNCWSMARKED has no effect when + * DISSYNCWS is set. */ + uint64_t syncwsmarked:1; + /* R/W If set, SYNCWS acts as SYNCW and SYNCS acts as + * SYNC. */ + uint64_t dissyncws:1; + /* R/W If set, no stall happens on write buffer + * full. */ + uint64_t diswbfst:1; + /* R/W If set (and SX set), supervisor-level + * loads/stores can use XKPHYS addresses with + * VA<48>==0 */ + uint64_t xkmemenas:1; + /* R/W If set (and UX set), user-level loads/stores + * can use XKPHYS addresses with VA<48>==0 */ + uint64_t xkmemenau:1; + /* R/W If set (and SX set), supervisor-level + * loads/stores can use XKPHYS addresses with + * VA<48>==1 */ + uint64_t xkioenas:1; + /* R/W If set (and UX set), user-level loads/stores + * can use XKPHYS addresses with VA<48>==1 */ + uint64_t xkioenau:1; + /* R/W If set, all stores act as SYNCW (NOMERGE must + * be set when this is set) RW, reset to 0. */ + uint64_t allsyncw:1; + /* R/W If set, no stores merge, and all stores reach + * the coherent bus in order. */ + uint64_t nomerge:1; + /* R/W Selects the bit in the counter used for DID + * time-outs 0 = 231, 1 = 230, 2 = 229, 3 = + * 214. Actual time-out is between 1x and 2x this + * interval. For example, with DIDTTO=3, expiration + * interval is between 16K and 32K. */ + uint64_t didtto:2; + /* R/W If set, the (mem) CSR clock never turns off. */ + uint64_t csrckalwys:1; + /* R/W If set, mclk never turns off. */ + uint64_t mclkalwys:1; + /* R/W Selects the bit in the counter used for write + * buffer flush time-outs (WBFLT+11) is the bit + * position in an internal counter used to determine + * expiration. The write buffer expires between 1x and + * 2x this interval. For example, with WBFLT = 0, a + * write buffer expires between 2K and 4K cycles after + * the write buffer entry is allocated. */ + uint64_t wbfltime:3; + /* R/W If set, do not put Istream in the L2 cache. */ + uint64_t istrnol2:1; + /* R/W The write buffer threshold. */ + uint64_t wbthresh:4; + /* Reserved */ + uint64_t reserved2:2; + /* R/W If set, CVMSEG is available for loads/stores in + * kernel/debug mode. */ + uint64_t cvmsegenak:1; + /* R/W If set, CVMSEG is available for loads/stores in + * supervisor mode. */ + uint64_t cvmsegenas:1; + /* R/W If set, CVMSEG is available for loads/stores in + * user mode. */ + uint64_t cvmsegenau:1; + /* R/W Size of local memory in cache blocks, 54 (6912 + * bytes) is max legal value. */ + uint64_t lmemsz:6; + } s; +}; + +struct octeon_cf_data { + unsigned long base_region_bias; + unsigned int base_region; /* The chip select region used by CF */ + int is16bit; /* 0 - 8bit, !0 - 16bit */ + int dma_engine; /* -1 for no DMA */ +}; + +extern void octeon_write_lcd(const char *s); +extern void octeon_check_cpu_bist(void); +extern int octeon_get_boot_debug_flag(void); +extern int octeon_get_boot_uart(void); + +struct uart_port; +extern unsigned int octeon_serial_in(struct uart_port *, int); +extern void octeon_serial_out(struct uart_port *, int, int); + +/** + * Write a 32bit value to the Octeon NPI register space + * + * @address: Address to write to + * @val: Value to write + */ +static inline void octeon_npi_write32(uint64_t address, uint32_t val) +{ + cvmx_write64_uint32(address ^ 4, val); + cvmx_read64_uint32(address ^ 4); +} + + +/** + * Read a 32bit value from the Octeon NPI register space + * + * @address: Address to read + * Returns The result + */ +static inline uint32_t octeon_npi_read32(uint64_t address) +{ + return cvmx_read64_uint32(address ^ 4); +} + +#endif /* __ASM_OCTEON_OCTEON_H */ diff --git a/arch/mips/kernel/octeon_switch.S b/arch/mips/kernel/octeon_switch.S new file mode 100644 index 0000000..d523896 --- /dev/null +++ b/arch/mips/kernel/octeon_switch.S @@ -0,0 +1,506 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1994, 1995, 1996, 1998, 1999, 2002, 2003 Ralf Baechle + * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) + * Copyright (C) 1994, 1995, 1996, by Andreas Busse + * Copyright (C) 1999 Silicon Graphics, Inc. + * Copyright (C) 2000 MIPS Technologies, Inc. + * written by Carsten Langgaard, carstenl@mips.com + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +/* + * Offset to the current process status flags, the first 32 bytes of the + * stack are not used. + */ +#define ST_OFF (_THREAD_SIZE - 32 - PT_SIZE + PT_STATUS) + +/* + * task_struct *resume(task_struct *prev, task_struct *next, + * struct thread_info *next_ti) + */ + .align 7 + LEAF(resume) + .set arch=octeon +#ifndef CONFIG_CPU_HAS_LLSC + sw zero, ll_bit +#endif + mfc0 t1, CP0_STATUS + LONG_S t1, THREAD_STATUS(a0) + cpu_save_nonscratch a0 + LONG_S ra, THREAD_REG31(a0) + + /* check if we need to save COP2 registers */ + PTR_L t2, TASK_THREAD_INFO(a0) + LONG_L t0, ST_OFF(t2) + bbit0 t0, 30, 1f + + /* Disable COP2 in the stored process state */ + li t1, ST0_CU2 + xor t0, t1 + LONG_S t0, ST_OFF(t2) + + /* Enable COP2 so we can save it */ + mfc0 t0, CP0_STATUS + or t0, t1 + mtc0 t0, CP0_STATUS + + /* Save COP2 */ + daddu a0, THREAD_CP2 + jal octeon_cop2_save + dsubu a0, THREAD_CP2 + + /* Disable COP2 now that we are done */ + mfc0 t0, CP0_STATUS + li t1, ST0_CU2 + xor t0, t1 + mtc0 t0, CP0_STATUS + +1: +#if CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0 + /* Check if we need to store CVMSEG state */ + mfc0 t0, $11,7 /* CvmMemCtl */ + bbit0 t0, 6, 3f /* Is user access enabled? */ + + /* Store the CVMSEG state */ + /* Extract the size of CVMSEG */ + andi t0, 0x3f + /* Multiply * (cache line size/sizeof(long)/2) */ + sll t0, 7-LONGLOG-1 + li t1, -32768 /* Base address of CVMSEG */ + LONG_ADDI t2, a0, THREAD_CVMSEG /* Where to store CVMSEG to */ + synciobdma +2: + .set noreorder + LONG_L t8, 0(t1) /* Load from CVMSEG */ + subu t0, 1 /* Decrement loop var */ + LONG_L t9, LONGSIZE(t1)/* Load from CVMSEG */ + LONG_ADDU t1, LONGSIZE*2 /* Increment loc in CVMSEG */ + LONG_S t8, 0(t2) /* Store CVMSEG to thread storage */ + LONG_ADDU t2, LONGSIZE*2 /* Increment loc in thread storage */ + bnez t0, 2b /* Loop until we've copied it all */ + LONG_S t9, -LONGSIZE(t2)/* Store CVMSEG to thread storage */ + .set reorder + + /* Disable access to CVMSEG */ + mfc0 t0, $11,7 /* CvmMemCtl */ + xori t0, t0, 0x40 /* Bit 6 is CVMSEG user enable */ + mtc0 t0, $11,7 /* CvmMemCtl */ +#endif +3: + /* + * The order of restoring the registers takes care of the race + * updating $28, $29 and kernelsp without disabling ints. + */ + move $28, a2 + cpu_restore_nonscratch a1 + +#if (_THREAD_SIZE - 32) < 0x8000 + PTR_ADDIU t0, $28, _THREAD_SIZE - 32 +#else + PTR_LI t0, _THREAD_SIZE - 32 + PTR_ADDU t0, $28 +#endif + set_saved_sp t0, t1, t2 + + mfc0 t1, CP0_STATUS /* Do we really need this? */ + li a3, 0xff01 + and t1, a3 + LONG_L a2, THREAD_STATUS(a1) + nor a3, $0, a3 + and a2, a3 + or a2, t1 + mtc0 a2, CP0_STATUS + move v0, a0 + jr ra + END(resume) + +/* + * void octeon_cop2_save(struct octeon_cop2_state *a0) + */ + .align 7 + LEAF(octeon_cop2_save) + + dmfc0 t9, $9,7 /* CvmCtl register. */ + + /* Save the COP2 CRC state */ + dmfc2 t0, 0x0201 + dmfc2 t1, 0x0202 + dmfc2 t2, 0x0200 + sd t0, OCTEON_CP2_CRC_IV(a0) + sd t1, OCTEON_CP2_CRC_LENGTH(a0) + sd t2, OCTEON_CP2_CRC_POLY(a0) + /* Skip next instructions if CvmCtl[NODFA_CP2] set */ + bbit1 t9, 28, 1f + + /* Save the LLM state */ + dmfc2 t0, 0x0402 + dmfc2 t1, 0x040A + sd t0, OCTEON_CP2_LLM_DAT(a0) + sd t1, OCTEON_CP2_LLM_DAT+8(a0) + +1: bbit1 t9, 26, 3f /* done if CvmCtl[NOCRYPTO] set */ + + /* Save the COP2 crypto state */ + /* this part is mostly common to both pass 1 and later revisions */ + dmfc2 t0, 0x0084 + dmfc2 t1, 0x0080 + dmfc2 t2, 0x0081 + dmfc2 t3, 0x0082 + sd t0, OCTEON_CP2_3DES_IV(a0) + dmfc2 t0, 0x0088 + sd t1, OCTEON_CP2_3DES_KEY(a0) + dmfc2 t1, 0x0111 /* only necessary for pass 1 */ + sd t2, OCTEON_CP2_3DES_KEY+8(a0) + dmfc2 t2, 0x0102 + sd t3, OCTEON_CP2_3DES_KEY+16(a0) + dmfc2 t3, 0x0103 + sd t0, OCTEON_CP2_3DES_RESULT(a0) + dmfc2 t0, 0x0104 + sd t1, OCTEON_CP2_AES_INP0(a0) /* only necessary for pass 1 */ + dmfc2 t1, 0x0105 + sd t2, OCTEON_CP2_AES_IV(a0) + dmfc2 t2, 0x0106 + sd t3, OCTEON_CP2_AES_IV+8(a0) + dmfc2 t3, 0x0107 + sd t0, OCTEON_CP2_AES_KEY(a0) + dmfc2 t0, 0x0110 + sd t1, OCTEON_CP2_AES_KEY+8(a0) + dmfc2 t1, 0x0100 + sd t2, OCTEON_CP2_AES_KEY+16(a0) + dmfc2 t2, 0x0101 + sd t3, OCTEON_CP2_AES_KEY+24(a0) + mfc0 t3, $15,0 /* Get the processor ID register */ + sd t0, OCTEON_CP2_AES_KEYLEN(a0) + li t0, 0x000d0000 /* This is the processor ID of Octeon Pass1 */ + sd t1, OCTEON_CP2_AES_RESULT(a0) + sd t2, OCTEON_CP2_AES_RESULT+8(a0) + /* Skip to the Pass1 version of the remainder of the COP2 state */ + beq t3, t0, 2f + + /* the non-pass1 state when !CvmCtl[NOCRYPTO] */ + dmfc2 t1, 0x0240 + dmfc2 t2, 0x0241 + dmfc2 t3, 0x0242 + dmfc2 t0, 0x0243 + sd t1, OCTEON_CP2_HSH_DATW(a0) + dmfc2 t1, 0x0244 + sd t2, OCTEON_CP2_HSH_DATW+8(a0) + dmfc2 t2, 0x0245 + sd t3, OCTEON_CP2_HSH_DATW+16(a0) + dmfc2 t3, 0x0246 + sd t0, OCTEON_CP2_HSH_DATW+24(a0) + dmfc2 t0, 0x0247 + sd t1, OCTEON_CP2_HSH_DATW+32(a0) + dmfc2 t1, 0x0248 + sd t2, OCTEON_CP2_HSH_DATW+40(a0) + dmfc2 t2, 0x0249 + sd t3, OCTEON_CP2_HSH_DATW+48(a0) + dmfc2 t3, 0x024A + sd t0, OCTEON_CP2_HSH_DATW+56(a0) + dmfc2 t0, 0x024B + sd t1, OCTEON_CP2_HSH_DATW+64(a0) + dmfc2 t1, 0x024C + sd t2, OCTEON_CP2_HSH_DATW+72(a0) + dmfc2 t2, 0x024D + sd t3, OCTEON_CP2_HSH_DATW+80(a0) + dmfc2 t3, 0x024E + sd t0, OCTEON_CP2_HSH_DATW+88(a0) + dmfc2 t0, 0x0250 + sd t1, OCTEON_CP2_HSH_DATW+96(a0) + dmfc2 t1, 0x0251 + sd t2, OCTEON_CP2_HSH_DATW+104(a0) + dmfc2 t2, 0x0252 + sd t3, OCTEON_CP2_HSH_DATW+112(a0) + dmfc2 t3, 0x0253 + sd t0, OCTEON_CP2_HSH_IVW(a0) + dmfc2 t0, 0x0254 + sd t1, OCTEON_CP2_HSH_IVW+8(a0) + dmfc2 t1, 0x0255 + sd t2, OCTEON_CP2_HSH_IVW+16(a0) + dmfc2 t2, 0x0256 + sd t3, OCTEON_CP2_HSH_IVW+24(a0) + dmfc2 t3, 0x0257 + sd t0, OCTEON_CP2_HSH_IVW+32(a0) + dmfc2 t0, 0x0258 + sd t1, OCTEON_CP2_HSH_IVW+40(a0) + dmfc2 t1, 0x0259 + sd t2, OCTEON_CP2_HSH_IVW+48(a0) + dmfc2 t2, 0x025E + sd t3, OCTEON_CP2_HSH_IVW+56(a0) + dmfc2 t3, 0x025A + sd t0, OCTEON_CP2_GFM_MULT(a0) + dmfc2 t0, 0x025B + sd t1, OCTEON_CP2_GFM_MULT+8(a0) + sd t2, OCTEON_CP2_GFM_POLY(a0) + sd t3, OCTEON_CP2_GFM_RESULT(a0) + sd t0, OCTEON_CP2_GFM_RESULT+8(a0) + jr ra + +2: /* pass 1 special stuff when !CvmCtl[NOCRYPTO] */ + dmfc2 t3, 0x0040 + dmfc2 t0, 0x0041 + dmfc2 t1, 0x0042 + dmfc2 t2, 0x0043 + sd t3, OCTEON_CP2_HSH_DATW(a0) + dmfc2 t3, 0x0044 + sd t0, OCTEON_CP2_HSH_DATW+8(a0) + dmfc2 t0, 0x0045 + sd t1, OCTEON_CP2_HSH_DATW+16(a0) + dmfc2 t1, 0x0046 + sd t2, OCTEON_CP2_HSH_DATW+24(a0) + dmfc2 t2, 0x0048 + sd t3, OCTEON_CP2_HSH_DATW+32(a0) + dmfc2 t3, 0x0049 + sd t0, OCTEON_CP2_HSH_DATW+40(a0) + dmfc2 t0, 0x004A + sd t1, OCTEON_CP2_HSH_DATW+48(a0) + sd t2, OCTEON_CP2_HSH_IVW(a0) + sd t3, OCTEON_CP2_HSH_IVW+8(a0) + sd t0, OCTEON_CP2_HSH_IVW+16(a0) + +3: /* pass 1 or CvmCtl[NOCRYPTO] set */ + jr ra + END(octeon_cop2_save) + +/* + * void octeon_cop2_restore(struct octeon_cop2_state *a0) + */ + .align 7 + .set push + .set noreorder + LEAF(octeon_cop2_restore) + /* First cache line was prefetched before the call */ + pref 4, 128(a0) + dmfc0 t9, $9,7 /* CvmCtl register. */ + + pref 4, 256(a0) + ld t0, OCTEON_CP2_CRC_IV(a0) + pref 4, 384(a0) + ld t1, OCTEON_CP2_CRC_LENGTH(a0) + ld t2, OCTEON_CP2_CRC_POLY(a0) + + /* Restore the COP2 CRC state */ + dmtc2 t0, 0x0201 + dmtc2 t1, 0x1202 + bbit1 t9, 28, 2f /* Skip LLM if CvmCtl[NODFA_CP2] is set */ + dmtc2 t2, 0x4200 + + /* Restore the LLM state */ + ld t0, OCTEON_CP2_LLM_DAT(a0) + ld t1, OCTEON_CP2_LLM_DAT+8(a0) + dmtc2 t0, 0x0402 + dmtc2 t1, 0x040A + +2: + bbit1 t9, 26, done_restore /* done if CvmCtl[NOCRYPTO] set */ + nop + + /* Restore the COP2 crypto state common to pass 1 and pass 2 */ + ld t0, OCTEON_CP2_3DES_IV(a0) + ld t1, OCTEON_CP2_3DES_KEY(a0) + ld t2, OCTEON_CP2_3DES_KEY+8(a0) + dmtc2 t0, 0x0084 + ld t0, OCTEON_CP2_3DES_KEY+16(a0) + dmtc2 t1, 0x0080 + ld t1, OCTEON_CP2_3DES_RESULT(a0) + dmtc2 t2, 0x0081 + ld t2, OCTEON_CP2_AES_INP0(a0) /* only really needed for pass 1 */ + dmtc2 t0, 0x0082 + ld t0, OCTEON_CP2_AES_IV(a0) + dmtc2 t1, 0x0098 + ld t1, OCTEON_CP2_AES_IV+8(a0) + dmtc2 t2, 0x010A /* only really needed for pass 1 */ + ld t2, OCTEON_CP2_AES_KEY(a0) + dmtc2 t0, 0x0102 + ld t0, OCTEON_CP2_AES_KEY+8(a0) + dmtc2 t1, 0x0103 + ld t1, OCTEON_CP2_AES_KEY+16(a0) + dmtc2 t2, 0x0104 + ld t2, OCTEON_CP2_AES_KEY+24(a0) + dmtc2 t0, 0x0105 + ld t0, OCTEON_CP2_AES_KEYLEN(a0) + dmtc2 t1, 0x0106 + ld t1, OCTEON_CP2_AES_RESULT(a0) + dmtc2 t2, 0x0107 + ld t2, OCTEON_CP2_AES_RESULT+8(a0) + mfc0 t3, $15,0 /* Get the processor ID register */ + dmtc2 t0, 0x0110 + li t0, 0x000d0000 /* This is the processor ID of Octeon Pass1 */ + dmtc2 t1, 0x0100 + bne t0, t3, 3f /* Skip the next stuff for non-pass1 */ + dmtc2 t2, 0x0101 + + /* this code is specific for pass 1 */ + ld t0, OCTEON_CP2_HSH_DATW(a0) + ld t1, OCTEON_CP2_HSH_DATW+8(a0) + ld t2, OCTEON_CP2_HSH_DATW+16(a0) + dmtc2 t0, 0x0040 + ld t0, OCTEON_CP2_HSH_DATW+24(a0) + dmtc2 t1, 0x0041 + ld t1, OCTEON_CP2_HSH_DATW+32(a0) + dmtc2 t2, 0x0042 + ld t2, OCTEON_CP2_HSH_DATW+40(a0) + dmtc2 t0, 0x0043 + ld t0, OCTEON_CP2_HSH_DATW+48(a0) + dmtc2 t1, 0x0044 + ld t1, OCTEON_CP2_HSH_IVW(a0) + dmtc2 t2, 0x0045 + ld t2, OCTEON_CP2_HSH_IVW+8(a0) + dmtc2 t0, 0x0046 + ld t0, OCTEON_CP2_HSH_IVW+16(a0) + dmtc2 t1, 0x0048 + dmtc2 t2, 0x0049 + b done_restore /* unconditional branch */ + dmtc2 t0, 0x004A + +3: /* this is post-pass1 code */ + ld t2, OCTEON_CP2_HSH_DATW(a0) + ld t0, OCTEON_CP2_HSH_DATW+8(a0) + ld t1, OCTEON_CP2_HSH_DATW+16(a0) + dmtc2 t2, 0x0240 + ld t2, OCTEON_CP2_HSH_DATW+24(a0) + dmtc2 t0, 0x0241 + ld t0, OCTEON_CP2_HSH_DATW+32(a0) + dmtc2 t1, 0x0242 + ld t1, OCTEON_CP2_HSH_DATW+40(a0) + dmtc2 t2, 0x0243 + ld t2, OCTEON_CP2_HSH_DATW+48(a0) + dmtc2 t0, 0x0244 + ld t0, OCTEON_CP2_HSH_DATW+56(a0) + dmtc2 t1, 0x0245 + ld t1, OCTEON_CP2_HSH_DATW+64(a0) + dmtc2 t2, 0x0246 + ld t2, OCTEON_CP2_HSH_DATW+72(a0) + dmtc2 t0, 0x0247 + ld t0, OCTEON_CP2_HSH_DATW+80(a0) + dmtc2 t1, 0x0248 + ld t1, OCTEON_CP2_HSH_DATW+88(a0) + dmtc2 t2, 0x0249 + ld t2, OCTEON_CP2_HSH_DATW+96(a0) + dmtc2 t0, 0x024A + ld t0, OCTEON_CP2_HSH_DATW+104(a0) + dmtc2 t1, 0x024B + ld t1, OCTEON_CP2_HSH_DATW+112(a0) + dmtc2 t2, 0x024C + ld t2, OCTEON_CP2_HSH_IVW(a0) + dmtc2 t0, 0x024D + ld t0, OCTEON_CP2_HSH_IVW+8(a0) + dmtc2 t1, 0x024E + ld t1, OCTEON_CP2_HSH_IVW+16(a0) + dmtc2 t2, 0x0250 + ld t2, OCTEON_CP2_HSH_IVW+24(a0) + dmtc2 t0, 0x0251 + ld t0, OCTEON_CP2_HSH_IVW+32(a0) + dmtc2 t1, 0x0252 + ld t1, OCTEON_CP2_HSH_IVW+40(a0) + dmtc2 t2, 0x0253 + ld t2, OCTEON_CP2_HSH_IVW+48(a0) + dmtc2 t0, 0x0254 + ld t0, OCTEON_CP2_HSH_IVW+56(a0) + dmtc2 t1, 0x0255 + ld t1, OCTEON_CP2_GFM_MULT(a0) + dmtc2 t2, 0x0256 + ld t2, OCTEON_CP2_GFM_MULT+8(a0) + dmtc2 t0, 0x0257 + ld t0, OCTEON_CP2_GFM_POLY(a0) + dmtc2 t1, 0x0258 + ld t1, OCTEON_CP2_GFM_RESULT(a0) + dmtc2 t2, 0x0259 + ld t2, OCTEON_CP2_GFM_RESULT+8(a0) + dmtc2 t0, 0x025E + dmtc2 t1, 0x025A + dmtc2 t2, 0x025B + +done_restore: + jr ra + nop + END(octeon_cop2_restore) + .set pop + +/* + * void octeon_mult_save() + * sp is assumed to point to a struct pt_regs + * + * NOTE: This is called in SAVE_SOME in stackframe.h. It can only + * safely modify k0 and k1. + */ + .align 7 + .set push + .set noreorder + LEAF(octeon_mult_save) + dmfc0 k0, $9,7 /* CvmCtl register. */ + bbit1 k0, 27, 1f /* Skip CvmCtl[NOMUL] */ + nop + + /* Save the multiplier state */ + v3mulu k0, $0, $0 + v3mulu k1, $0, $0 + sd k0, PT_MTP(sp) /* PT_MTP has P0 */ + v3mulu k0, $0, $0 + sd k1, PT_MTP+8(sp) /* PT_MTP+8 has P1 */ + ori k1, $0, 1 + v3mulu k1, k1, $0 + sd k0, PT_MTP+16(sp) /* PT_MTP+16 has P2 */ + v3mulu k0, $0, $0 + sd k1, PT_MPL(sp) /* PT_MPL has MPL0 */ + v3mulu k1, $0, $0 + sd k0, PT_MPL+8(sp) /* PT_MPL+8 has MPL1 */ + jr ra + sd k1, PT_MPL+16(sp) /* PT_MPL+16 has MPL2 */ + +1: /* Resume here if CvmCtl[NOMUL] */ + jr ra + END(octeon_mult_save) + .set pop + +/* + * void octeon_mult_restore() + * sp is assumed to point to a struct pt_regs + * + * NOTE: This is called in RESTORE_SOME in stackframe.h. + */ + .align 7 + .set push + .set noreorder + LEAF(octeon_mult_restore) + dmfc0 k1, $9,7 /* CvmCtl register. */ + ld v0, PT_MPL(sp) /* MPL0 */ + ld v1, PT_MPL+8(sp) /* MPL1 */ + ld k0, PT_MPL+16(sp) /* MPL2 */ + bbit1 k1, 27, 1f /* Skip CvmCtl[NOMUL] */ + /* Normally falls through, so no time wasted here */ + nop + + /* Restore the multiplier state */ + ld k1, PT_MTP+16(sp) /* P2 */ + MTM0 v0 /* MPL0 */ + ld v0, PT_MTP+8(sp) /* P1 */ + MTM1 v1 /* MPL1 */ + ld v1, PT_MTP(sp) /* P0 */ + MTM2 k0 /* MPL2 */ + MTP2 k1 /* P2 */ + MTP1 v0 /* P1 */ + jr ra + MTP0 v1 /* P0 */ + +1: /* Resume here if CvmCtl[NOMUL] */ + jr ra + nop + END(octeon_mult_restore) + .set pop + diff --git a/arch/mips/mm/c-octeon.c b/arch/mips/mm/c-octeon.c new file mode 100644 index 0000000..44d01a0 --- /dev/null +++ b/arch/mips/mm/c-octeon.c @@ -0,0 +1,307 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2005-2007 Cavium Networks + */ +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +unsigned long long cache_err_dcache[NR_CPUS]; + +/** + * Octeon automatically flushes the dcache on tlb changes, so + * from Linux's viewpoint it acts much like a physically + * tagged cache. No flushing is needed + * + */ +static void octeon_flush_data_cache_page(unsigned long addr) +{ + /* Nothing to do */ +} + +static inline void octeon_local_flush_icache(void) +{ + asm volatile ("synci 0($0)"); +} + +/* + * Flush local I-cache for the specified range. + */ +static void local_octeon_flush_icache_range(unsigned long start, + unsigned long end) +{ + octeon_local_flush_icache(); +} + +/** + * Flush caches as necessary for all cores affected by a + * vma. If no vma is supplied, all cores are flushed. + * + * @vma: VMA to flush or NULL to flush all icaches. + */ +static void octeon_flush_icache_all_cores(struct vm_area_struct *vma) +{ + extern void octeon_send_ipi_single(int cpu, unsigned int action); +#ifdef CONFIG_SMP + int cpu; + cpumask_t mask; +#endif + + mb(); + octeon_local_flush_icache(); +#ifdef CONFIG_SMP + preempt_disable(); + cpu = smp_processor_id(); + + /* + * If we have a vma structure, we only need to worry about + * cores it has been used on + */ + if (vma) + mask = vma->vm_mm->cpu_vm_mask; + else + mask = cpu_online_map; + cpu_clear(cpu, mask); + for_each_cpu_mask(cpu, mask) + octeon_send_ipi_single(cpu, SMP_ICACHE_FLUSH); + + preempt_enable(); +#endif +} + + +/** + * Called to flush the icache on all cores + */ +static void octeon_flush_icache_all(void) +{ + octeon_flush_icache_all_cores(NULL); +} + + +/** + * Called to flush all memory associated with a memory + * context. + * + * @mm: Memory context to flush + */ +static void octeon_flush_cache_mm(struct mm_struct *mm) +{ + /* + * According to the R4K version of this file, CPUs without + * dcache aliases don't need to do anything here + */ +} + + +/** + * Flush a range of kernel addresses out of the icache + * + */ +static void octeon_flush_icache_range(unsigned long start, unsigned long end) +{ + octeon_flush_icache_all_cores(NULL); +} + + +/** + * Flush the icache for a trampoline. These are used for interrupt + * and exception hooking. + * + * @addr: Address to flush + */ +static void octeon_flush_cache_sigtramp(unsigned long addr) +{ + struct vm_area_struct *vma; + + vma = find_vma(current->mm, addr); + octeon_flush_icache_all_cores(vma); +} + + +/** + * Flush a range out of a vma + * + * @vma: VMA to flush + * @start: + * @end: + */ +static void octeon_flush_cache_range(struct vm_area_struct *vma, + unsigned long start, unsigned long end) +{ + if (vma->vm_flags & VM_EXEC) + octeon_flush_icache_all_cores(vma); +} + + +/** + * Flush a specific page of a vma + * + * @vma: VMA to flush page for + * @page: Page to flush + * @pfn: + */ +static void octeon_flush_cache_page(struct vm_area_struct *vma, + unsigned long page, unsigned long pfn) +{ + if (vma->vm_flags & VM_EXEC) + octeon_flush_icache_all_cores(vma); +} + + +/** + * Probe Octeon's caches + * + */ +static void __devinit probe_octeon(void) +{ + unsigned long icache_size; + unsigned long dcache_size; + unsigned int config1; + struct cpuinfo_mips *c = ¤t_cpu_data; + + switch (c->cputype) { + case CPU_CAVIUM_OCTEON: + config1 = read_c0_config1(); + c->icache.linesz = 2 << ((config1 >> 19) & 7); + c->icache.sets = 64 << ((config1 >> 22) & 7); + c->icache.ways = 1 + ((config1 >> 16) & 7); + c->icache.flags |= MIPS_CACHE_VTAG; + icache_size = + c->icache.sets * c->icache.ways * c->icache.linesz; + c->icache.waybit = ffs(icache_size / c->icache.ways) - 1; + c->dcache.linesz = 128; + if (OCTEON_IS_MODEL(OCTEON_CN3XXX)) + c->dcache.sets = 1; /* CN3XXX has one Dcache set */ + else + c->dcache.sets = 2; /* CN5XXX has two Dcache sets */ + c->dcache.ways = 64; + dcache_size = + c->dcache.sets * c->dcache.ways * c->dcache.linesz; + c->dcache.waybit = ffs(dcache_size / c->dcache.ways) - 1; + c->options |= MIPS_CPU_PREFETCH; + break; + + default: + panic("Unsupported Cavium Networks CPU type\n"); + break; + } + + /* compute a couple of other cache variables */ + c->icache.waysize = icache_size / c->icache.ways; + c->dcache.waysize = dcache_size / c->dcache.ways; + + c->icache.sets = icache_size / (c->icache.linesz * c->icache.ways); + c->dcache.sets = dcache_size / (c->dcache.linesz * c->dcache.ways); + + if (smp_processor_id() == 0) { + pr_notice("Primary instruction cache %ldkB, %s, %d way, " + "%d sets, linesize %d bytes.\n", + icache_size >> 10, + cpu_has_vtag_icache ? + "virtually tagged" : "physically tagged", + c->icache.ways, c->icache.sets, c->icache.linesz); + + pr_notice("Primary data cache %ldkB, %d-way, %d sets, " + "linesize %d bytes.\n", + dcache_size >> 10, c->dcache.ways, + c->dcache.sets, c->dcache.linesz); + } +} + + +/** + * Setup the Octeon cache flush routines + * + */ +void __devinit octeon_cache_init(void) +{ + extern unsigned long ebase; + extern char except_vec2_octeon; + + memcpy((void *)(ebase + 0x100), &except_vec2_octeon, 0x80); + octeon_flush_cache_sigtramp(ebase + 0x100); + + probe_octeon(); + + shm_align_mask = PAGE_SIZE - 1; + + flush_cache_all = octeon_flush_icache_all; + __flush_cache_all = octeon_flush_icache_all; + flush_cache_mm = octeon_flush_cache_mm; + flush_cache_page = octeon_flush_cache_page; + flush_cache_range = octeon_flush_cache_range; + flush_cache_sigtramp = octeon_flush_cache_sigtramp; + flush_icache_all = octeon_flush_icache_all; + flush_data_cache_page = octeon_flush_data_cache_page; + flush_icache_range = octeon_flush_icache_range; + local_flush_icache_range = local_octeon_flush_icache_range; + + build_clear_page(); + build_copy_page(); +} + +/** + * Handle a cache error exception + */ + +static void cache_parity_error_octeon(int non_recoverable) +{ + unsigned long coreid = cvmx_get_core_num(); + uint64_t icache_err = read_octeon_c0_icacheerr(); + + pr_err("Cache error exception:\n"); + pr_err("cp0_errorepc == %lx\n", read_c0_errorepc()); + if (icache_err & 1) { + pr_err("CacheErr (Icache) == %llx\n", + (unsigned long long)icache_err); + write_octeon_c0_icacheerr(0); + } + if (cache_err_dcache[coreid] & 1) { + pr_err("CacheErr (Dcache) == %llx\n", + (unsigned long long)cache_err_dcache[coreid]); + cache_err_dcache[coreid] = 0; + } + + if (non_recoverable) + panic("Can't handle cache error: nested exception"); +} + +/** + * Called when the the exception is not recoverable + */ + +asmlinkage void cache_parity_error_octeon_recoverable(void) +{ + cache_parity_error_octeon(0); +} + +/** + * Called when the the exception is recoverable + */ + +asmlinkage void cache_parity_error_octeon_non_recoverable(void) +{ + cache_parity_error_octeon(1); +} + diff --git a/arch/mips/mm/cex-oct.S b/arch/mips/mm/cex-oct.S new file mode 100644 index 0000000..3db8553 --- /dev/null +++ b/arch/mips/mm/cex-oct.S @@ -0,0 +1,70 @@ +/* + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2006 Cavium Networks + * Cache error handler + */ + +#include +#include +#include +#include + +/* + * Handle cache error. Indicate to the second level handler whether + * the exception is recoverable. + */ + LEAF(except_vec2_octeon) + + .set push + .set mips64r2 + .set noreorder + .set noat + + + /* due to an errata we need to read the COP0 CacheErr (Dcache) + * before any cache/DRAM access */ + + rdhwr k0, $0 /* get core_id */ + PTR_LA k1, cache_err_dcache + sll k0, k0, 3 + PTR_ADDU k1, k0, k1 /* k1 = &cache_err_dcache[core_id] */ + + dmfc0 k0, CP0_CACHEERR, 1 + sd k0, (k1) + dmtc0 $0, CP0_CACHEERR, 1 + + /* check whether this is a nested exception */ + mfc0 k1, CP0_STATUS + andi k1, k1, ST0_EXL + beqz k1, 1f + nop + j cache_parity_error_octeon_non_recoverable + nop + + /* exception is recoverable */ +1: j handle_cache_err + nop + + .set pop + END(except_vec2_octeon) + + /* We need to jump to handle_cache_err so that the previous handler + * can fit within 0x80 bytes. We also move from 0xFFFFFFFFAXXXXXXX + * space (uncached) to the 0xFFFFFFFF8XXXXXXX space (cached). */ + LEAF(handle_cache_err) + .set push + .set noreorder + .set noat + + SAVE_ALL + KMODE + jal cache_parity_error_octeon_recoverable + nop + j ret_from_exception + nop + + .set pop + END(handle_cache_err) -- 1.5.6.6 From dvomlehn@cisco.com Fri Jan 9 01:26:30 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 09 Jan 2009 01:26:33 +0000 (GMT) Received: from rtp-iport-2.cisco.com ([64.102.122.149]:21292 "EHLO rtp-iport-2.cisco.com") by ftp.linux-mips.org with ESMTP id S21102853AbZAIB0a (ORCPT ); Fri, 9 Jan 2009 01:26:30 +0000 X-IronPort-AV: E=Sophos;i="4.37,236,1231113600"; d="scan'208";a="33239475" Received: from rtp-dkim-2.cisco.com ([64.102.121.159]) by rtp-iport-2.cisco.com with ESMTP; 09 Jan 2009 01:26:23 +0000 Received: from rtp-core-1.cisco.com (rtp-core-1.cisco.com [64.102.124.12]) by rtp-dkim-2.cisco.com (8.12.11/8.12.11) with ESMTP id n091QNsk019718 for ; Thu, 8 Jan 2009 20:26:23 -0500 Received: from sausatlsmtp1.sciatl.com (sausatlsmtp1.cisco.com [192.133.217.33]) by rtp-core-1.cisco.com (8.13.8/8.13.8) with ESMTP id n091QNm1007894 for ; Fri, 9 Jan 2009 01:26:23 GMT Received: from default.com ([192.133.217.33]) by sausatlsmtp1.sciatl.com with Microsoft SMTPSVC(6.0.3790.3959); Thu, 8 Jan 2009 20:26:22 -0500 Received: from sausatlbhs02.corp.sa.net ([192.133.216.42]) by sausatlsmtp1.sciatl.com with Microsoft SMTPSVC(6.0.3790.3959); Thu, 8 Jan 2009 20:26:21 -0500 Received: from [64.101.20.155] ([64.101.20.155]) by sausatlbhs02.corp.sa.net with Microsoft SMTPSVC(6.0.3790.3959); Thu, 8 Jan 2009 20:26:20 -0500 Subject: Re: [PATCH] MIPS: Add option for running kernel in mapped address space. From: David VomLehn Reply-To: dvomlehn@cisco.com To: David Daney Cc: linux-mips@linux-mips.org In-Reply-To: <1231378896-25925-1-git-send-email-ddaney@caviumnetworks.com> References: <1231378896-25925-1-git-send-email-ddaney@caviumnetworks.com> Content-Type: text/plain Date: Thu, 08 Jan 2009 17:26:11 -0800 Message-Id: <1231464371.32488.43.camel@cuplxvomd02.corp.sa.net> Mime-Version: 1.0 X-Mailer: Evolution 2.12.3 (2.12.3-5.fc8) Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 09 Jan 2009 01:26:20.0801 (UTC) FILETIME=[46F4BF10:01C971F9] X-ST-MF-Message-Resent: 1/8/2009 20:26 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; l=6974; t=1231464383; x=1232328383; c=relaxed/simple; s=rtpdkim2001; h=Content-Type:From:Subject:Content-Transfer-Encoding:MIME-Version; d=cisco.com; i=dvomlehn@cisco.com; z=From:=20David=20VomLehn=20 |Subject:=20Re=3A=20[PATCH]=20MIPS=3A=20Add=20option=20for= 20running=20kernel=20in=20mapped=20address=0A=09space. |Sender:=20 |To:=20David=20Daney=20; bh=BoQGvfEzWVuJxy1PVrZYPFiNhBI8HffFM9YgteGpsv0=; b=IPV5hG3FRE3F2cjyhi0l/Nfni6tG6Y43/jlyGlbTbi3LrYHkrTEVsGGqis YM49BsiHqTl2XKd1/rw7ws52GBGs6dWpG0OtkD3x7r7p4Ae1g5wGfFO7ei4t D+FI1bFneb; Authentication-Results: rtp-dkim-2; header.From=dvomlehn@cisco.com; dkim=pass ( sig from cisco.com/rtpdkim2001 verified; ); Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21705 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dvomlehn@cisco.com Precedence: bulk X-list: linux-mips On Wed, 2009-01-07 at 17:41 -0800, David Daney wrote: > This is a preliminary patch to allow the kernel to run in mapped > address space via a wired TLB entry. Probably in a future version I > would factor out the OCTEON specific parts to a separate patch. Yes, please do the factoring. > diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig > index 780b520..d9c46a4 100644 > --- a/arch/mips/Kconfig > +++ b/arch/mips/Kconfig > @@ -1431,6 +1431,23 @@ config PAGE_SIZE_64KB > > endchoice > > +config MAPPED_KERNEL > + bool "Mapped kernel" > + help > + Select this option if you want the kernel's code and data to > + be in mapped memory. The kernel will be mapped using a > + single wired TLB entry, thus reducing the number of > + available TLB entries by one. Kernel modules will be able > + to use a more efficient calling convention. This is currently only supported on 64-bit processors, so this should depend on CONFIG_64BIT. > diff --git a/arch/mips/Makefile b/arch/mips/Makefile > index 0bc2120..5468f6d 100644 > --- a/arch/mips/Makefile > +++ b/arch/mips/Makefile ... > @@ -662,7 +670,7 @@ OBJCOPYFLAGS += --remove-section=.reginfo > > CPPFLAGS_vmlinux.lds := \ > $(KBUILD_CFLAGS) \ > - -D"LOADADDR=$(load-y)" \ > + -D"LOADADDR=$(load-y)" $(PHYS_LOAD_ADDRESS) \ > -D"JIFFIES=$(JIFFIES)" \ > -D"DATAOFFSET=$(if $(dataoffset-y),$(dataoffset-y),0)" It seems more consistent to just eliminate PHYS_LOAD_ADDRESS entirely and add a line here reading: -D"PHYSADDR=0x$(CONFIG_PHYS_LOAD_ADDRESS)" \ > > diff --git a/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h b/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h > index 0b2b5eb..bf36d82 100644 > --- a/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h > +++ b/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h > @@ -27,6 +27,56 @@ > # a3 = address of boot descriptor block > .set push > .set arch=octeon > +#ifdef CONFIG_MAPPED_KERNEL > + # Set up the TLB index 0 for wired access to kernel. > + # Assume we were loaded with sufficient alignment so that we > + # can cover the image with two pages. This seems like a pretty big assumption. Possible ways to handle this: o Generalize to handle n pages. o Hang in a loop here if the assumption is not met o Check later on whether the assumption was true and print a message. I'm not really sure how to do this last one, though. > + dla v0, _end > + dla v1, _text > + dsubu v0, v0, v1 # size of image > + move v1, zero > + li t1, -1 # shift count. > +1: dsrl v0, v0, 1 # mask into v1 > + dsll v1, v1, 1 > + daddiu t1, t1, 1 > + ori v1, v1, 1 > + bne v0, zero, 1b > + daddiu t2, t1, -6 > + mtc0 v1, $5, 0 # PageMask > + dla t3, 0xffffffffc0000000 # kernel address I think this should be CKSSEG rather than a magic constant. > + dmtc0 t3, $10, 0 # EntryHi > + bal 1f > +1: dla v0, 0x7fffffff Another magic constant; don't know if there is already a define that really applies, though. Perhaps add something to asm-mips/inst.h? > diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c > index 1055348..b44bcf8 100644 > --- a/arch/mips/kernel/traps.c > +++ b/arch/mips/kernel/traps.c > @@ -49,6 +49,8 @@ > #include > #include > > +#include "../mm/uasm.h" This looks like it would be a good idea to consider moving uasm.h to include/asm-mips, or possibly splitting it into two header files, one of which would move to include/asm-mips. > + > extern void check_wait(void); > extern asmlinkage void r4k_wait(void); > extern asmlinkage void rollback_handle_int(void); > @@ -1295,9 +1297,18 @@ void *set_except_vector(int n, void *addr) > > exception_handlers[n] = handler; > if (n == 0 && cpu_has_divec) { > - *(u32 *)(ebase + 0x200) = 0x08000000 | > - (0x03ffffff & (handler >> 2)); > - local_flush_icache_range(ebase + 0x200, ebase + 0x204); > + unsigned long jump_mask = ~((1 << 28) - 1); The 28 is a magic constant specifying the number of bits of the offset in a jump instruction. Perhaps define jump_mask in asm-mips/inst.h since it is related to the instruction format? > + u32 *buf = (u32 *)(ebase + 0x200); > + unsigned int k0 = 26; You are using k0 as a constant by defining it as a variable. You could just have a #define here, but my suggestion is that it would be better to add defines to asm-mips/inst.h (something like "#define REG_K0 26" might be suitable for meeting this particular need) > + if((handler & jump_mask) == ((ebase + 0x200) & jump_mask)) { > + uasm_i_j(&buf, handler & jump_mask); > + uasm_i_nop(&buf); > + } else { > + UASM_i_LA(&buf, k0, handler); > + uasm_i_jr(&buf, k0); > + uasm_i_nop(&buf); > + } > + local_flush_icache_range(ebase + 0x200, (unsigned long)buf); > } > return (void *)old_handler; > } > /* > @@ -1670,9 +1683,9 @@ void __init trap_init(void) > return; /* Already done */ > #endif > > - if (cpu_has_veic || cpu_has_vint) > + if (cpu_has_veic || cpu_has_vint) { > ebase = (unsigned long) alloc_bootmem_low_pages(0x200 + VECTORSPACING*64); > - else { > + } else { Checkpatch will complain about this, and it doesn't really add value to make the change. > diff --git a/arch/mips/mm/page.c b/arch/mips/mm/page.c > index 1417c64..0070aa0 100644 > --- a/arch/mips/mm/page.c > +++ b/arch/mips/mm/page.c > @@ -687,3 +687,9 @@ void copy_page(void *to, void *from) > } > > #endif /* CONFIG_SIBYTE_DMA_PAGEOPS */ > + > +#ifdef CONFIG_MAPPED_KERNEL > +/* Initialized so it is not clobbered when .bss is zeroed. */ > +unsigned long phys_to_kernel_offset = 1; > +unsigned long kernel_image_end = 1; > +#endif Clearly there is some magic happening here, but the such wizardry needs more documentation. I can deduce that these must be overwritten before we get to kernel_entry; who sets these? I don't know for sure what kernel_image_end is, but I am guessing that it is the physical address of the end of the kernel. If so, you can eliminate it as a piece of magic by calculating it at run time as the sum of the address of the start of the kernel and the size. -- David VomLehn, dvomlehn@cisco.com - - - - - Cisco - - - - - This e-mail and any attachments may contain information which is confidential, proprietary, privileged or otherwise protected by law. The information is solely intended for the named addressee (or a person responsible for delivering it to the addressee). If you are not the intended recipient of this message, you are not authorized to read, print, retain, copy or disseminate this message or any part of it. If you have received this e-mail in error, please notify the sender immediately by return e-mail and delete it from your computer. From David.Daney@caviumnetworks.com Fri Jan 9 02:34:31 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 09 Jan 2009 02:34:33 +0000 (GMT) Received: from mail3.caviumnetworks.com ([12.108.191.235]:65437 "EHLO mail3.caviumnetworks.com") by ftp.linux-mips.org with ESMTP id S21365019AbZAICeb (ORCPT ); Fri, 9 Jan 2009 02:34:31 +0000 Received: from exch4.caveonetworks.com (Not Verified[192.168.16.23]) by mail3.caviumnetworks.com with MailMarshal (v6,2,2,3503) id ; Thu, 08 Jan 2009 21:34:11 -0500 Received: from exch4.caveonetworks.com ([192.168.16.23]) by exch4.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Thu, 8 Jan 2009 18:33:12 -0800 Received: from dd1.caveonetworks.com ([64.169.86.201]) by exch4.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Thu, 8 Jan 2009 18:33:12 -0800 Message-ID: <4966B768.9050909@caviumnetworks.com> Date: Thu, 08 Jan 2009 18:33:12 -0800 From: David Daney User-Agent: Thunderbird 2.0.0.19 (X11/20090105) MIME-Version: 1.0 To: dvomlehn@cisco.com CC: linux-mips@linux-mips.org Subject: Re: [PATCH] MIPS: Add option for running kernel in mapped address space. References: <1231378896-25925-1-git-send-email-ddaney@caviumnetworks.com> <1231464371.32488.43.camel@cuplxvomd02.corp.sa.net> In-Reply-To: <1231464371.32488.43.camel@cuplxvomd02.corp.sa.net> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 09 Jan 2009 02:33:12.0093 (UTC) FILETIME=[9DDF54D0:01C97202] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21706 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips David VomLehn wrote: > On Wed, 2009-01-07 at 17:41 -0800, David Daney wrote: >> This is a preliminary patch to allow the kernel to run in mapped >> address space via a wired TLB entry. Probably in a future version I >> would factor out the OCTEON specific parts to a separate patch. > > Yes, please do the factoring. Everything in good time. My real intent was to generate feedback about the general ideas. > >> diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig >> index 780b520..d9c46a4 100644 >> --- a/arch/mips/Kconfig >> +++ b/arch/mips/Kconfig >> @@ -1431,6 +1431,23 @@ config PAGE_SIZE_64KB >> >> endchoice >> >> +config MAPPED_KERNEL >> + bool "Mapped kernel" >> + help >> + Select this option if you want the kernel's code and data to >> + be in mapped memory. The kernel will be mapped using a >> + single wired TLB entry, thus reducing the number of >> + available TLB entries by one. Kernel modules will be able >> + to use a more efficient calling convention. > > This is currently only supported on 64-bit processors, so this should > depend on CONFIG_64BIT. It should be trivial to extend to 32-bit kernels as well. I may try it on the mips32 based STB I have at home. But as it currently stands, you are correct. > >> diff --git a/arch/mips/Makefile b/arch/mips/Makefile >> index 0bc2120..5468f6d 100644 >> --- a/arch/mips/Makefile >> +++ b/arch/mips/Makefile > ... >> @@ -662,7 +670,7 @@ OBJCOPYFLAGS += --remove-section=.reginfo >> >> CPPFLAGS_vmlinux.lds := \ >> $(KBUILD_CFLAGS) \ >> - -D"LOADADDR=$(load-y)" \ >> + -D"LOADADDR=$(load-y)" $(PHYS_LOAD_ADDRESS) \ >> -D"JIFFIES=$(JIFFIES)" \ >> -D"DATAOFFSET=$(if $(dataoffset-y),$(dataoffset-y),0)" > > It seems more consistent to just eliminate PHYS_LOAD_ADDRESS entirely > and add a line here reading: > -D"PHYSADDR=0x$(CONFIG_PHYS_LOAD_ADDRESS)" \ There is some macro trickery in vmlinux.lds.S that checks to see if it is defined, so I cannot unconditionally define it. > >> >> diff --git a/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h b/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h >> index 0b2b5eb..bf36d82 100644 >> --- a/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h >> +++ b/arch/mips/include/asm/mach-cavium-octeon/kernel-entry-init.h >> @@ -27,6 +27,56 @@ >> # a3 = address of boot descriptor block >> .set push >> .set arch=octeon >> +#ifdef CONFIG_MAPPED_KERNEL >> + # Set up the TLB index 0 for wired access to kernel. >> + # Assume we were loaded with sufficient alignment so that we >> + # can cover the image with two pages. > > This seems like a pretty big assumption. Possible ways to handle this: > o Generalize to handle n pages. This is an optimization, burning through TLB entries is not going to help things. > o Hang in a loop here if the assumption is not met Possible. > o Check later on whether the assumption was true and print a message. > I'm not really sure how to do this last one, though. Also possible. This is all very low-level board code, if you want the optimization, you need to load at a suitable physical address. > >> + dla v0, _end >> + dla v1, _text >> + dsubu v0, v0, v1 # size of image >> + move v1, zero >> + li t1, -1 # shift count. >> +1: dsrl v0, v0, 1 # mask into v1 >> + dsll v1, v1, 1 >> + daddiu t1, t1, 1 >> + ori v1, v1, 1 >> + bne v0, zero, 1b >> + daddiu t2, t1, -6 >> + mtc0 v1, $5, 0 # PageMask >> + dla t3, 0xffffffffc0000000 # kernel address > > I think this should be CKSSEG rather than a magic constant. > >> + dmtc0 t3, $10, 0 # EntryHi >> + bal 1f >> +1: dla v0, 0x7fffffff > > Another magic constant; don't know if there is already a define that > really applies, though. Perhaps add something to asm-mips/inst.h? > Both are worth investigating. Each board could (and may have to) do it differently. >> diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c >> index 1055348..b44bcf8 100644 >> --- a/arch/mips/kernel/traps.c >> +++ b/arch/mips/kernel/traps.c >> @@ -49,6 +49,8 @@ >> #include >> #include >> >> +#include "../mm/uasm.h" > > This looks like it would be a good idea to consider moving uasm.h to > include/asm-mips, or possibly splitting it into two header files, one of > which would move to include/asm-mips. > That was my thought as well. This being a quick-and-dirty hack, I took the low road and did it this way. >> + >> extern void check_wait(void); >> extern asmlinkage void r4k_wait(void); >> extern asmlinkage void rollback_handle_int(void); >> @@ -1295,9 +1297,18 @@ void *set_except_vector(int n, void *addr) >> >> exception_handlers[n] = handler; >> if (n == 0 && cpu_has_divec) { >> - *(u32 *)(ebase + 0x200) = 0x08000000 | >> - (0x03ffffff & (handler >> 2)); >> - local_flush_icache_range(ebase + 0x200, ebase + 0x204); >> + unsigned long jump_mask = ~((1 << 28) - 1); > > The 28 is a magic constant specifying the number of bits of the offset > in a jump instruction. Perhaps define jump_mask in asm-mips/inst.h since > it is related to the instruction format? Correct. > >> + u32 *buf = (u32 *)(ebase + 0x200); >> + unsigned int k0 = 26; > > You are using k0 as a constant by defining it as a variable. You could > just have a #define here, but my suggestion is that it would be better > to add defines to asm-mips/inst.h (something like "#define REG_K0 26" > might be suitable for meeting this particular need) Yes, the constants should probably be factored out of the TLB and page code. Then they could be used here as well. [...] >> >> - if (cpu_has_veic || cpu_has_vint) >> + if (cpu_has_veic || cpu_has_vint) { >> ebase = (unsigned long) alloc_bootmem_low_pages(0x200 + VECTORSPACING*64); >> - else { >> + } else { > > Checkpatch will complain about this, and it doesn't really add value to > make the change. > IANACPL (I am not a checkpatch lawyer), but I think it is correct. If one clause of an if has braces they both should. However that was left over from my debugging and if it were to be changed, should be part of a code cleanup patch. >> diff --git a/arch/mips/mm/page.c b/arch/mips/mm/page.c >> index 1417c64..0070aa0 100644 >> --- a/arch/mips/mm/page.c >> +++ b/arch/mips/mm/page.c >> @@ -687,3 +687,9 @@ void copy_page(void *to, void *from) >> } >> >> #endif /* CONFIG_SIBYTE_DMA_PAGEOPS */ >> + >> +#ifdef CONFIG_MAPPED_KERNEL >> +/* Initialized so it is not clobbered when .bss is zeroed. */ >> +unsigned long phys_to_kernel_offset = 1; >> +unsigned long kernel_image_end = 1; >> +#endif > > Clearly there is some magic happening here, but the such wizardry needs > more documentation. Clearly. > I can deduce that these must be overwritten before > we get to kernel_entry; One of the first things done at kernel_entry is to zero out .bss, if you want to communicate with things that happen before kernel_entry, you cannot use .bss. > who sets these? The code in kernel-entry-init.h > I don't know for sure what kernel_image_end is, but I am guessing that > it is the physical address of the end of the kernel. It is the virtual address of the first page past the kernel's virtual mapping. This is where we can start mapping modules. David Daney From theperan@gmail.com Fri Jan 9 12:08:28 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 09 Jan 2009 12:08:30 +0000 (GMT) Received: from fg-out-1718.google.com ([72.14.220.152]:62530 "EHLO fg-out-1718.google.com") by ftp.linux-mips.org with ESMTP id S21103375AbZAIMI2 (ORCPT ); Fri, 9 Jan 2009 12:08:28 +0000 Received: by fg-out-1718.google.com with SMTP id d23so3263603fga.32 for ; Fri, 09 Jan 2009 04:08:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:message-id:date:from:to :subject:in-reply-to:mime-version:content-type :content-transfer-encoding:content-disposition:references; bh=Jar7yL2qhUXE4QGstr6UCqWlu8vpMWc/mZ1jcZlq7Mw=; b=U2CqLesy0VMzRVXqmrUA/+I6ROSE10dM5CPgm9fnHZ9K2RyDVVVvOLsOvMCM3K5Ep4 h+IOyw26sKagMWAMY8g1MFcRgoTEIuMrCaSINnon7NI9zagHLrd8TAuk9wtwa1edzc+c 53h1PYf15GElhO1Q2IDGwGHwtrvaxieQUFPtk= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=message-id:date:from:to:subject:in-reply-to:mime-version :content-type:content-transfer-encoding:content-disposition :references; b=cJxOam+WtFUzOKI/LYGJrW5HNDY3u+1I0BBi0TomfNJCfJdf/HqsWs0FGfwzlVBNYX zGX4XAB2+iJM3ftt2sROpMRIUVHtRvnGFEtdWSZXlfed2HYR6UkcwVvdTlzANh7eBi4o KM3MuuVcTOSsuUunV0vLw0kPRNHA9b70nZT1w= Received: by 10.86.65.9 with SMTP id n9mr14830524fga.61.1231502906822; Fri, 09 Jan 2009 04:08:26 -0800 (PST) Received: by 10.86.72.13 with HTTP; Fri, 9 Jan 2009 04:08:26 -0800 (PST) Message-ID: <164c42ea0901090408h377e9f4eqb417443ef7a1ad@mail.gmail.com> Date: Fri, 9 Jan 2009 13:08:26 +0100 From: "Per Andreas Gulbrandsen" To: linux-mips@linux-mips.org Subject: Problem compiling glibc In-Reply-To: <164c42ea0901080443sace24b2v176bcc0a4d23836a@mail.gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Content-Disposition: inline References: <164c42ea0901080443sace24b2v176bcc0a4d23836a@mail.gmail.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21707 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: theperan@gmail.com Precedence: bulk X-list: linux-mips Hi. I first sent this mail to clfs-support (cross-compile linux from scratch), but got the advice to try asking for help here. I'm following the clfs guide for cross compiling a linux system for mips (alchemy, CLFS_TARGET="mipsel-unknown-linux-gnu"). SVN Version SVN-20090107-MIPS. My host system is openSuse 11 (CLFS_HOST="x86_64-cross-linux-gnu"). I've checked host requirements and I have all tools specified there. I get stuck in 5.11, Constructing Cross-Compile Tools - glibc. When I try to make glibc I get the following error: mipsel-unknown-linux-gnu-gcc -mabi=32 ../sysdeps/unix/sysv/linux/sa_len.c -c -std=gnu99 -fgnu89-inline -O2 -Wall -Winline -Wwrite-strings -fmerge-all-constants -g -Wstrict-prototypes -I../include -I/mnt/clfs/sources/glibc-build/socket -I/mnt/clfs/sources/glibc-build -I../ports/sysdeps/mips/elf -I../ports/sysdeps/unix/sysv/linux/mips/mips32 -I../ports/sysdeps/unix/sysv/linux/mips/nptl -I../ports/sysdeps/unix/sysv/linux/mips -I../nptl/sysdeps/unix/sysv/linux -I../nptl/sysdeps/pthread -I../sysdeps/pthread -I../ports/sysdeps/unix/sysv/linux -I../sysdeps/unix/sysv/linux -I../sysdeps/gnu -I../sysdeps/unix/common -I../sysdeps/unix/mman -I../sysdeps/unix/inet -I../nptl/sysdeps/unix/sysv -I../ports/sysdeps/unix/sysv -I../sysdeps/unix/sysv -I../ports/sysdeps/unix/mips/mips32 -I../ports/sysdeps/unix/mips -I../nptl/sysdeps/unix -I../ports/sysdeps/unix -I../sysdeps/unix -I../sysdeps/posix -I../ports/sysdeps/mips/mips32 -I../ports/sysdeps/mips -I../sysdeps/ieee754/flt-32 -I../sysdeps/ieee754/dbl-64 -I../sysdeps/wordsize-32 -I../ports/sysdeps/mips/fpu -I../ports/sysdeps/mips/nptl -I../sysdeps/ieee754 -I../sysdeps/generic/elf -I../sysdeps/generic -I../nptl -I../ports -I.. -I../libio -I. -nostdinc -isystem /mnt/clfs/cross-tools/bin/../lib/gcc/mipsel-unknown-linux-gnu/4.3.2/include -isystem /mnt/clfs/cross-tools/bin/../lib/gcc/mipsel-unknown-linux-gnu/4.3.2/include-fixed -isystem /tools/include -D_LIBC_REENTRANT -include ../include/libc-symbols.h -DPIC -o /mnt/clfs/sources/glibc-build/socket/sa_len.o -MD -MP -MF /mnt/clfs/sources/glibc-build/socket/sa_len.o.dt -MT/mnt/clfs/sources/glibc-build/socket/sa_len.o In file included from /tools/include/asm/byteorder.h:65, from /tools/include/linux/atalk.h:4, from ../sysdeps/unix/sysv/linux/netatalk/at.h:25, from ../sysdeps/unix/sysv/linux/sa_len.c:22: /tools/include/linux/byteorder.h:8:3: error: #error Fix asm/byteorder.h to define one endianness make[2]: *** [/mnt/clfs/sources/glibc-build/socket/sa_len.o] Error 1 make[2]: Leaving directory `/mnt/clfs/sources/glibc-2.8/socket' make[1]: *** [socket/subdir_lib] Error 2 make[1]: Leaving directory `/mnt/clfs/sources/glibc-2.8' make: *** [all] Error 2 I've looked at asm/byteorder.h, but I can't figure out what to do. I can't understand how I'm suppose to "fix" it. I've tried different stuff, i.e. undefing __MIPSEB__ and/or __BIG_ENDIAN if __MIPSEB__ is defined. But I still get the same error. However, If I undef __BIG_ENDIAN in /tools/include/linux/byteorder.h just before the check that triggers the error it compiles. But this doesn't seem like a very good solution. Seems like I should get rid of the initial definition of __BIG_ENDIAN (alt. __MIPSEB). Can anyone please advice? I'd like to get this right, and not just hack my way through it. -- mvh Per Andreas Gulbrandsen From anemo@mba.ocn.ne.jp Fri Jan 9 13:36:17 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 09 Jan 2009 13:36:20 +0000 (GMT) Received: from mba.ocn.ne.jp ([122.1.235.107]:42188 "HELO smtp.mba.ocn.ne.jp") by ftp.linux-mips.org with SMTP id S21365064AbZAINgR (ORCPT ); Fri, 9 Jan 2009 13:36:17 +0000 Received: from localhost (p2189-ipad205funabasi.chiba.ocn.ne.jp [222.146.97.189]) by smtp.mba.ocn.ne.jp (Postfix) with ESMTP id 80903A785; Fri, 9 Jan 2009 22:36:11 +0900 (JST) Date: Fri, 09 Jan 2009 22:36:13 +0900 (JST) Message-Id: <20090109.223613.61508682.anemo@mba.ocn.ne.jp> To: theperan@gmail.com Cc: linux-mips@linux-mips.org Subject: Re: Problem compiling glibc From: Atsushi Nemoto In-Reply-To: <164c42ea0901090408h377e9f4eqb417443ef7a1ad@mail.gmail.com> References: <164c42ea0901080443sace24b2v176bcc0a4d23836a@mail.gmail.com> <164c42ea0901090408h377e9f4eqb417443ef7a1ad@mail.gmail.com> X-Fingerprint: 6ACA 1623 39BD 9A94 9B1A B746 CA77 FE94 2874 D52F X-Pgp-Public-Key: http://wwwkeys.pgp.net/pks/lookup?op=get&search=0x2874D52F X-Mailer: Mew version 5.2 on Emacs 21.4 / Mule 5.0 (SAKAKI) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21708 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anemo@mba.ocn.ne.jp Precedence: bulk X-list: linux-mips On Fri, 9 Jan 2009 13:08:26 +0100, "Per Andreas Gulbrandsen" wrote: > /tools/include/linux/byteorder.h:8:3: error: #error Fix > asm/byteorder.h to define one endianness > make[2]: *** [/mnt/clfs/sources/glibc-build/socket/sa_len.o] Error 1 > make[2]: Leaving directory `/mnt/clfs/sources/glibc-2.8/socket' > make[1]: *** [socket/subdir_lib] Error 2 > make[1]: Leaving directory `/mnt/clfs/sources/glibc-2.8' > make: *** [all] Error 2 > > I've looked at asm/byteorder.h, but I can't figure out what to do. I > can't understand how I'm suppose to "fix" it. I've tried different > stuff, i.e. undefing __MIPSEB__ and/or __BIG_ENDIAN if __MIPSEB__ is > defined. But I still get the same error. > However, If I undef __BIG_ENDIAN in /tools/include/linux/byteorder.h > just before the check that triggers the error it compiles. But this > doesn't seem like a very good solution. Seems like I should get rid of > the initial definition of __BIG_ENDIAN (alt. __MIPSEB). Can anyone > please advice? I'd like to get this right, and not just hack my way I suppose this patchset will fix this problem. (already mainlined) http://lkml.org/lkml/2009/1/6/341 --- Atsushi Nemoto From rusty@rustcorp.com.au Sat Jan 10 05:11:31 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 10 Jan 2009 05:11:34 +0000 (GMT) Received: from ozlabs.org ([203.10.76.45]:11197 "EHLO ozlabs.org") by ftp.linux-mips.org with ESMTP id S21103489AbZAJFLb (ORCPT ); Sat, 10 Jan 2009 05:11:31 +0000 Received: from vivaldi.localnet (unknown [150.101.102.135]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPSA id 6D9AADE0B4; Sat, 10 Jan 2009 16:11:26 +1100 (EST) From: Rusty Russell To: Linus Torvalds Subject: Re: [PATCH] cpumask fallout: Initialize irq_default_affinity earlier. Date: Sat, 10 Jan 2009 15:41:13 +1030 User-Agent: KMail/1.10.3 (Linux/2.6.27-9-generic; KDE/4.1.3; i686; ; ) Cc: David Daney , linux-kernel@vger.kernel.org, linux-mips@linux-mips.org References: <1231446081-8448-1-git-send-email-ddaney@caviumnetworks.com> <496666CE.3050205@caviumnetworks.com> In-Reply-To: MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit Content-Disposition: inline Message-Id: <200901101541.15192.rusty@rustcorp.com.au> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21710 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: rusty@rustcorp.com.au Precedence: bulk X-list: linux-mips Content-Length: 515 Lines: 18 On Friday 09 January 2009 07:26:59 Linus Torvalds wrote: > > On Thu, 8 Jan 2009, David Daney wrote: > > > > The 'inline' seems gratuitous to me. Since it is static GCC should do > > the Right Thing. However since you suggested it, I am testing it that > > way. > > Trust me, gcc very seldom does the Right Thing(tm) when it comes to > inlining. > > Linus Note that there's a downside: with inline funcs in .c files you don't get a warning should they become unused in future cleanups. Cheers, Rusty. From f.fainelli@gmail.com Sun Jan 11 16:09:04 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 11 Jan 2009 16:09:06 +0000 (GMT) Received: from fg-out-1718.google.com ([72.14.220.152]:16639 "EHLO fg-out-1718.google.com") by ftp.linux-mips.org with ESMTP id S21365700AbZAKQJE convert rfc822-to-8bit (ORCPT ); Sun, 11 Jan 2009 16:09:04 +0000 Received: by fg-out-1718.google.com with SMTP id d23so3597383fga.32 for ; Sun, 11 Jan 2009 08:09:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:sender:from:to:subject:date :user-agent:cc:references:in-reply-to:mime-version:content-type :content-transfer-encoding:content-disposition:message-id; bh=UefxnE99J9DrXPQQpvzAi+yJrLRo5QTvb+jX/SiimGI=; b=xuShZJPaTzqHjaZBcfNDDPr3SFKDiaamSyVArV2bEGzgNZLVuItnfQqOjCDBXCSMM6 CcGntGSW6PYQylrSZAMm0aefWrr9wmyr8M4gLMA9Ycr2vFEIAkEd+wyAo2olIJQRvWkC oK5y943GKBGBTNdLg6ZJpSnQBAFWvBwl4E8uk= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:from:to:subject:date:user-agent:cc:references:in-reply-to :mime-version:content-type:content-transfer-encoding :content-disposition:message-id; b=vPXDSP5eJ2WoeQelKMAKIyZjsDoEw0h2brqdYbSAW9qMXmSwfzJsWnX/FLsfheKvLU tayfZQJfEZzY0Sk3LiEEhdqEmspEa+/CBQiMMKm9/a09CPrgdNJ9LCSYFmsHvyghMzGq jXwgUD7I9KjyMROWCP+9VaqPUaw3vaSix8P9I= Received: by 10.86.84.18 with SMTP id h18mr16110622fgb.22.1231690143194; Sun, 11 Jan 2009 08:09:03 -0800 (PST) Received: from ?192.168.1.23? (93.17.192-77.rev.gaoland.net [77.192.17.93]) by mx.google.com with ESMTPS id 3sm6848015fge.37.2009.01.11.08.09.01 (version=TLSv1/SSLv3 cipher=RC4-MD5); Sun, 11 Jan 2009 08:09:02 -0800 (PST) From: Florian Fainelli To: Phil Sutter Subject: Re: [PATCH] define io_map_base for rc32434's PCI controller Date: Sun, 11 Jan 2009 17:08:58 +0100 User-Agent: KMail/1.9.9 Cc: ralf@linux-mips.org, linux-mips@linux-mips.org References: <1226445364-5402-1-git-send-email-n0-1@freewrt.org> In-Reply-To: <1226445364-5402-1-git-send-email-n0-1@freewrt.org> MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-15" Content-Transfer-Encoding: 8BIT Content-Disposition: inline Message-Id: <200901111708.59195.florian@openwrt.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21711 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips Content-Length: 526 Lines: 17 Ralf, This patch still applies to current linux-queue/linux.git, can you merge it please ? Thanks a lot. Le Wednesday 12 November 2008 00:16:04 Phil Sutter, vous avez écrit : > The code is rather based on trial-and-error than knowledge. Verified Via > Rhine functionality in PIO as well as MMIO mode. > > Signed-off-by: Phil Sutter > Tested-by: Florian Fainelli > --- -- Best regards, Florian Fainelli Email : florian@openwrt.org http://openwrt.org ------------------------------- From ralf@h5.dl5rb.org.uk Sun Jan 11 17:44:55 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 11 Jan 2009 17:44:58 +0000 (GMT) Received: from h5.dl5rb.org.uk ([81.2.74.5]:39057 "EHLO mail.linux-mips.net") by ftp.linux-mips.org with ESMTP id S21365705AbZAKRoz (ORCPT ); Sun, 11 Jan 2009 17:44:55 +0000 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by mail.linux-mips.net (8.14.3/8.14.2) with ESMTP id n0BHiprp001754; Sun, 11 Jan 2009 17:44:51 GMT Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id n0BHio6U001752; Sun, 11 Jan 2009 17:44:50 GMT Date: Sun, 11 Jan 2009 17:44:50 +0000 From: Ralf Baechle To: Florian Fainelli Cc: Phil Sutter , linux-mips@linux-mips.org Subject: Re: [PATCH] define io_map_base for rc32434's PCI controller Message-ID: <20090111174450.GB21239@linux-mips.org> References: <1226445364-5402-1-git-send-email-n0-1@freewrt.org> <200901111708.59195.florian@openwrt.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <200901111708.59195.florian@openwrt.org> User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21712 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Content-Length: 354 Lines: 10 On Sun, Jan 11, 2009 at 05:08:58PM +0100, Florian Fainelli wrote: > This patch still applies to current linux-queue/linux.git, can you merge it > please ? Thanks a lot. I sent a pull request for the stuff in the upstream-linus tree earlier today. To avoid possible confusion and I'll roll the next tree for him only after he pulled this one. Ralf From ralf@h5.dl5rb.org.uk Mon Jan 12 01:27:09 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 12 Jan 2009 01:27:11 +0000 (GMT) Received: from h5.dl5rb.org.uk ([81.2.74.5]:33983 "EHLO mail.linux-mips.net") by ftp.linux-mips.org with ESMTP id S21365113AbZALB1J (ORCPT ); Mon, 12 Jan 2009 01:27:09 +0000 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by mail.linux-mips.net (8.14.3/8.14.2) with ESMTP id n0C1QtTJ005856; Mon, 12 Jan 2009 01:26:55 GMT Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id n0C1QsZF005855; Mon, 12 Jan 2009 01:26:54 GMT Date: Mon, 12 Jan 2009 01:26:54 +0000 From: Ralf Baechle To: "David VomLehn (dvomlehn)" Cc: Roel Kluin , linux-mips@linux-mips.org Subject: Re: [PATCH] MIPS: unsigned result is always greater than 0 Message-ID: <20090112012654.GB27976@linux-mips.org> References: <495E2E47.6080605@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21713 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Content-Length: 7447 Lines: 254 On Tue, Jan 06, 2009 at 04:46:19PM -0500, David VomLehn (dvomlehn) wrote: > I agree that the code as it exists is wrong, but, as I see it, the > problem is that the type of result should be changed from unsigned long > to int. This fixes the comparison so it works correctly. In addition, > such a change means that result would be the same type as the counter > element of atomic_t, avoiding possible surprises should longs be larger > than ints. Originally that code was intended only for R2000-class processors. But LL/SC don't work correctly on XKPHYS addresses on some R5000-class processors, so we avoid these instructions on the affected processors running 64-bit kernels and use the fallback method of disabling interrupts anyway, so long indeed might be longer than int. What in the end saves us is that atomic_sub_if_positive's only caller atomic_dec_if_positive is only being used by the RM9000 watchdog driver and the RM9000 doesn't suffer from the mentioned CPU bug. Still no reason not to fix it. I changed the intermediate variables used in all functions that operate on atomic_t to int rsp. long for the atomic64_* functions for consistency - which as a nice side effect also shaves of almost 2kB from the kernel due to the elemination of gcc-generated non-sense sign extension code. Ralf MIPS: atomic_*(): Change type of intermediate variables. This shaves of 1912 bytes of an IP27 defconfig kernel and avoids unexpected overflow behaviour in atomic_sub_if_positive. Apply the same changes to the atomic64_* functions for consistency. Signed-off-by: Ralf Baechle diff --git a/arch/mips/include/asm/atomic.h b/arch/mips/include/asm/atomic.h index c996c3b..1b332e1 100644 --- a/arch/mips/include/asm/atomic.h +++ b/arch/mips/include/asm/atomic.h @@ -50,7 +50,7 @@ static __inline__ void atomic_add(int i, atomic_t * v) { if (cpu_has_llsc && R10000_LLSC_WAR) { - unsigned long temp; + int temp; __asm__ __volatile__( " .set mips3 \n" @@ -62,7 +62,7 @@ static __inline__ void atomic_add(int i, atomic_t * v) : "=&r" (temp), "=m" (v->counter) : "Ir" (i), "m" (v->counter)); } else if (cpu_has_llsc) { - unsigned long temp; + int temp; __asm__ __volatile__( " .set mips3 \n" @@ -95,7 +95,7 @@ static __inline__ void atomic_add(int i, atomic_t * v) static __inline__ void atomic_sub(int i, atomic_t * v) { if (cpu_has_llsc && R10000_LLSC_WAR) { - unsigned long temp; + int temp; __asm__ __volatile__( " .set mips3 \n" @@ -107,7 +107,7 @@ static __inline__ void atomic_sub(int i, atomic_t * v) : "=&r" (temp), "=m" (v->counter) : "Ir" (i), "m" (v->counter)); } else if (cpu_has_llsc) { - unsigned long temp; + int temp; __asm__ __volatile__( " .set mips3 \n" @@ -135,12 +135,12 @@ static __inline__ void atomic_sub(int i, atomic_t * v) */ static __inline__ int atomic_add_return(int i, atomic_t * v) { - unsigned long result; + int result; smp_llsc_mb(); if (cpu_has_llsc && R10000_LLSC_WAR) { - unsigned long temp; + int temp; __asm__ __volatile__( " .set mips3 \n" @@ -154,7 +154,7 @@ static __inline__ int atomic_add_return(int i, atomic_t * v) : "Ir" (i), "m" (v->counter) : "memory"); } else if (cpu_has_llsc) { - unsigned long temp; + int temp; __asm__ __volatile__( " .set mips3 \n" @@ -187,12 +187,12 @@ static __inline__ int atomic_add_return(int i, atomic_t * v) static __inline__ int atomic_sub_return(int i, atomic_t * v) { - unsigned long result; + int result; smp_llsc_mb(); if (cpu_has_llsc && R10000_LLSC_WAR) { - unsigned long temp; + int temp; __asm__ __volatile__( " .set mips3 \n" @@ -206,7 +206,7 @@ static __inline__ int atomic_sub_return(int i, atomic_t * v) : "Ir" (i), "m" (v->counter) : "memory"); } else if (cpu_has_llsc) { - unsigned long temp; + int temp; __asm__ __volatile__( " .set mips3 \n" @@ -247,12 +247,12 @@ static __inline__ int atomic_sub_return(int i, atomic_t * v) */ static __inline__ int atomic_sub_if_positive(int i, atomic_t * v) { - unsigned long result; + int result; smp_llsc_mb(); if (cpu_has_llsc && R10000_LLSC_WAR) { - unsigned long temp; + int temp; __asm__ __volatile__( " .set mips3 \n" @@ -270,7 +270,7 @@ static __inline__ int atomic_sub_if_positive(int i, atomic_t * v) : "Ir" (i), "m" (v->counter) : "memory"); } else if (cpu_has_llsc) { - unsigned long temp; + int temp; __asm__ __volatile__( " .set mips3 \n" @@ -429,7 +429,7 @@ static __inline__ int atomic_add_unless(atomic_t *v, int a, int u) static __inline__ void atomic64_add(long i, atomic64_t * v) { if (cpu_has_llsc && R10000_LLSC_WAR) { - unsigned long temp; + long temp; __asm__ __volatile__( " .set mips3 \n" @@ -441,7 +441,7 @@ static __inline__ void atomic64_add(long i, atomic64_t * v) : "=&r" (temp), "=m" (v->counter) : "Ir" (i), "m" (v->counter)); } else if (cpu_has_llsc) { - unsigned long temp; + long temp; __asm__ __volatile__( " .set mips3 \n" @@ -474,7 +474,7 @@ static __inline__ void atomic64_add(long i, atomic64_t * v) static __inline__ void atomic64_sub(long i, atomic64_t * v) { if (cpu_has_llsc && R10000_LLSC_WAR) { - unsigned long temp; + long temp; __asm__ __volatile__( " .set mips3 \n" @@ -486,7 +486,7 @@ static __inline__ void atomic64_sub(long i, atomic64_t * v) : "=&r" (temp), "=m" (v->counter) : "Ir" (i), "m" (v->counter)); } else if (cpu_has_llsc) { - unsigned long temp; + long temp; __asm__ __volatile__( " .set mips3 \n" @@ -514,12 +514,12 @@ static __inline__ void atomic64_sub(long i, atomic64_t * v) */ static __inline__ long atomic64_add_return(long i, atomic64_t * v) { - unsigned long result; + long result; smp_llsc_mb(); if (cpu_has_llsc && R10000_LLSC_WAR) { - unsigned long temp; + long temp; __asm__ __volatile__( " .set mips3 \n" @@ -533,7 +533,7 @@ static __inline__ long atomic64_add_return(long i, atomic64_t * v) : "Ir" (i), "m" (v->counter) : "memory"); } else if (cpu_has_llsc) { - unsigned long temp; + long temp; __asm__ __volatile__( " .set mips3 \n" @@ -566,12 +566,12 @@ static __inline__ long atomic64_add_return(long i, atomic64_t * v) static __inline__ long atomic64_sub_return(long i, atomic64_t * v) { - unsigned long result; + long result; smp_llsc_mb(); if (cpu_has_llsc && R10000_LLSC_WAR) { - unsigned long temp; + long temp; __asm__ __volatile__( " .set mips3 \n" @@ -585,7 +585,7 @@ static __inline__ long atomic64_sub_return(long i, atomic64_t * v) : "Ir" (i), "m" (v->counter) : "memory"); } else if (cpu_has_llsc) { - unsigned long temp; + long temp; __asm__ __volatile__( " .set mips3 \n" @@ -626,12 +626,12 @@ static __inline__ long atomic64_sub_return(long i, atomic64_t * v) */ static __inline__ long atomic64_sub_if_positive(long i, atomic64_t * v) { - unsigned long result; + long result; smp_llsc_mb(); if (cpu_has_llsc && R10000_LLSC_WAR) { - unsigned long temp; + long temp; __asm__ __volatile__( " .set mips3 \n" @@ -649,7 +649,7 @@ static __inline__ long atomic64_sub_if_positive(long i, atomic64_t * v) : "Ir" (i), "m" (v->counter) : "memory"); } else if (cpu_has_llsc) { - unsigned long temp; + long temp; __asm__ __volatile__( " .set mips3 \n" From dmitri.vorobiev@movial.fi Mon Jan 12 09:09:33 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 12 Jan 2009 09:09:35 +0000 (GMT) Received: from smtp.movial.fi ([62.236.91.34]:21975 "EHLO smtp.movial.fi") by ftp.linux-mips.org with ESMTP id S21103096AbZALJJd (ORCPT ); Mon, 12 Jan 2009 09:09:33 +0000 Received: from localhost (mailscanner.hel.movial.fi [172.17.81.9]) by smtp.movial.fi (Postfix) with ESMTP id 2EC2FC80D7 for ; Mon, 12 Jan 2009 11:09:25 +0200 (EET) X-Virus-Scanned: Debian amavisd-new at movial.fi Received: from smtp.movial.fi ([62.236.91.34]) by localhost (mailscanner.hel.movial.fi [172.17.81.9]) (amavisd-new, port 10026) with ESMTP id BBF07XYUIt5s for ; Mon, 12 Jan 2009 11:09:25 +0200 (EET) Received: from [172.17.49.48] (sd048.hel.movial.fi [172.17.49.48]) by smtp.movial.fi (Postfix) with ESMTP id F3420C8012 for ; Mon, 12 Jan 2009 11:09:24 +0200 (EET) Message-ID: <496B08C4.7000300@movial.fi> Date: Mon, 12 Jan 2009 11:09:24 +0200 From: Dmitri Vorobiev Organization: Movial Creative Technologies User-Agent: Icedove 1.5.0.14eol (X11/20090105) MIME-Version: 1.0 To: linux-mips@linux-mips.org Subject: malta_defconfig build busted again Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21714 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dmitri.vorobiev@movial.fi Precedence: bulk X-list: linux-mips Content-Length: 639 Lines: 20 $ make ARCH=mips CROSS_COMPILE=mips-unknown-linux-gnu- mrproper [skipped] $ make ARCH=mips CROSS_COMPILE=mips-unknown-linux-gnu- malta_defconfig [skipped] # # configuration written to .config # $ make ARCH=mips CROSS_COMPILE=mips-unknown-linux-gnu- [skipped] CC arch/mips/kernel/mips-mt-fpaff.o arch/mips/kernel/mips-mt-fpaff.c: In function `mipsmt_sys_sched_setaffinity': arch/mips/kernel/mips-mt-fpaff.c:82: error: structure has no member named `euid'arch/mips/kernel/mips-mt-fpaff.c:82: error: structure has no member named `uid' make[1]: *** [arch/mips/kernel/mips-mt-fpaff.o] Error 1 make: *** [arch/mips/kernel] Error 2 From travis@cthulhu.engr.sgi.com Mon Jan 12 22:05:30 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 12 Jan 2009 22:05:32 +0000 (GMT) Received: from relay3.sgi.com ([192.48.171.31]:36230 "EHLO relay.sgi.com") by ftp.linux-mips.org with ESMTP id S21103411AbZALWFa (ORCPT ); Mon, 12 Jan 2009 22:05:30 +0000 Received: from cthulhu.engr.sgi.com (cthulhu.engr.sgi.com [150.166.39.100]) by relay3.corp.sgi.com (Postfix) with ESMTP id 5D242AC00A; Mon, 12 Jan 2009 14:05:21 -0800 (PST) Received: from polaris-admin.engr.sgi.com (polaris-admin.engr.sgi.com [150.166.41.54]) by cthulhu.engr.sgi.com (8.12.10/8.12.10/SuSE Linux 0.7) with ESMTP id n0CM5KF7012556; Mon, 12 Jan 2009 14:05:20 -0800 Received: by polaris-admin.engr.sgi.com (Postfix, from userid 5508) id 671C25646613; Mon, 12 Jan 2009 14:05:20 -0800 (PST) Message-Id: <20090112220520.303833000@polaris-admin.engr.sgi.com> References: <20090112220519.566749000@polaris-admin.engr.sgi.com> User-Agent: quilt/0.46-1 Date: Mon, 12 Jan 2009 14:05:24 -0800 From: Mike Travis To: Ingo Molnar Cc: Rusty Russell , Andrew Morton , Jack Steiner , linux-kernel@vger.kernel.org, Ralf Baechle , Subject: [PATCH 5/8] mips irq: update mips for new irq_desc Content-Disposition: inline; filename=irq:update-mips-to-new-irq_desc Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21715 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: travis@sgi.com Precedence: bulk X-list: linux-mips Content-Length: 2492 Lines: 75 Impact: cleanup, update to new cpumask API Irq_desc.affinity and irq_desc.pending_mask are now cpumask_var_t's so access to them should be using the new cpumask API. Signed-off-by: Mike Travis Cc: Ralf Baechle Cc: --- arch/mips/include/asm/irq.h | 2 +- arch/mips/kernel/irq-gic.c | 2 +- arch/mips/kernel/smtc.c | 2 +- arch/mips/mti-malta/malta-smtc.c | 5 +++-- 4 files changed, 6 insertions(+), 5 deletions(-) --- linux-2.6-for-ingo.orig/arch/mips/include/asm/irq.h +++ linux-2.6-for-ingo/arch/mips/include/asm/irq.h @@ -66,7 +66,7 @@ extern void smtc_forward_irq(unsigned in */ #define IRQ_AFFINITY_HOOK(irq) \ do { \ - if (!cpu_isset(smp_processor_id(), irq_desc[irq].affinity)) { \ + if (!cpumask_test_cpu(smp_processor_id(), irq_desc[irq].affinity)) {\ smtc_forward_irq(irq); \ irq_exit(); \ return; \ --- linux-2.6-for-ingo.orig/arch/mips/kernel/irq-gic.c +++ linux-2.6-for-ingo/arch/mips/kernel/irq-gic.c @@ -187,7 +187,7 @@ static void gic_set_affinity(unsigned in set_bit(irq, pcpu_masks[first_cpu(tmp)].pcpu_mask); } - irq_desc[irq].affinity = *cpumask; + cpumask_copy(irq_desc[irq].affinity, cpumask); spin_unlock_irqrestore(&gic_lock, flags); } --- linux-2.6-for-ingo.orig/arch/mips/kernel/smtc.c +++ linux-2.6-for-ingo/arch/mips/kernel/smtc.c @@ -686,7 +686,7 @@ void smtc_forward_irq(unsigned int irq) * and efficiency, we just pick the easiest one to find. */ - target = first_cpu(irq_desc[irq].affinity); + target = cpumask_first(irq_desc[irq].affinity); /* * We depend on the platform code to have correctly processed --- linux-2.6-for-ingo.orig/arch/mips/mti-malta/malta-smtc.c +++ linux-2.6-for-ingo/arch/mips/mti-malta/malta-smtc.c @@ -116,7 +116,7 @@ struct plat_smp_ops msmtc_smp_ops = { void plat_set_irq_affinity(unsigned int irq, const struct cpumask *affinity) { - cpumask_t tmask = *affinity; + cpumask_t tmask; int cpu = 0; void smtc_set_irq_affinity(unsigned int irq, cpumask_t aff); @@ -139,11 +139,12 @@ void plat_set_irq_affinity(unsigned int * be made to forward to an offline "CPU". */ + cpumask_copy(&tmask, affinity); for_each_cpu(cpu, affinity) { if ((cpu_data[cpu].vpe_id != 0) || !cpu_online(cpu)) cpu_clear(cpu, tmask); } - irq_desc[irq].affinity = tmask; + cpumask_copy(irq_desc[irq].affinity, &tmask); if (cpus_empty(tmask)) /* -- From mano@roarinelk.homelinux.net Tue Jan 13 13:53:02 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 13 Jan 2009 13:53:05 +0000 (GMT) Received: from fnoeppeil36.netpark.at ([217.175.205.164]:16794 "EHLO roarinelk.homelinux.net") by ftp.linux-mips.org with ESMTP id S21103556AbZAMNxC (ORCPT ); Tue, 13 Jan 2009 13:53:02 +0000 Received: (qmail 18397 invoked by uid 1000); 13 Jan 2009 14:49:58 +0100 Date: Tue, 13 Jan 2009 14:49:58 +0100 From: Manuel Lauss To: Ralf Baechle Cc: Linux-MIPS Subject: [PATCH] Alchemy: time.c compile fix (cpumask) Message-ID: <20090113134958.GA18314@roarinelk.homelinux.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline User-Agent: Mutt/1.5.16 (2007-06-09) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21716 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mano@roarinelk.homelinux.net Precedence: bulk X-list: linux-mips Content-Length: 742 Lines: 23 The 'cpumask' member of struct clock_event_device is a pointer now. Signed-off-by: Manuel Lauss --- arch/mips/alchemy/common/time.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/mips/alchemy/common/time.c b/arch/mips/alchemy/common/time.c index 3288014..6fd441d 100644 --- a/arch/mips/alchemy/common/time.c +++ b/arch/mips/alchemy/common/time.c @@ -89,7 +89,7 @@ static struct clock_event_device au1x_rtcmatch2_clockdev = { .irq = AU1000_RTC_MATCH2_INT, .set_next_event = au1x_rtcmatch2_set_next_event, .set_mode = au1x_rtcmatch2_set_mode, - .cpumask = CPU_MASK_ALL, + .cpumask = CPU_MASK_ALL_PTR, }; static struct irqaction au1x_rtcmatch2_irqaction = { -- 1.6.1 From mano@roarinelk.homelinux.net Tue Jan 13 13:56:06 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 13 Jan 2009 13:56:08 +0000 (GMT) Received: from fnoeppeil36.netpark.at ([217.175.205.164]:46761 "EHLO roarinelk.homelinux.net") by ftp.linux-mips.org with ESMTP id S21103576AbZAMN4G (ORCPT ); Tue, 13 Jan 2009 13:56:06 +0000 Received: (qmail 18451 invoked by uid 1000); 13 Jan 2009 14:53:02 +0100 Date: Tue, 13 Jan 2009 14:53:02 +0100 From: Manuel Lauss To: Ralf Baechle Cc: Linux-MIPS Subject: [PATCH] Alchemy: remove superfluous cpu-model constants. Message-ID: <20090113135302.GA18442@roarinelk.homelinux.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline User-Agent: Mutt/1.5.16 (2007-06-09) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21717 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mano@roarinelk.homelinux.net Precedence: bulk X-list: linux-mips Content-Length: 4726 Lines: 160 All currently existing Alchemy models are identical in terms of cpu core and cache size/organization. The parts in the mips kernel which need to know the exact CPU revision extract it from the c0_prid register already, and there are no other in-tree users. This patch removes the various CPU_AU1000 model constants in favor of a single CPU_ALCHEMY constant. Should a new variant with slightly different "company options" or "processor revision" bits in c0_prid appear, it will be supported immediately (minus an exact model string in cpuinfo). Signed-off-by: Manuel Lauss --- arch/mips/include/asm/cpu.h | 3 +-- arch/mips/kernel/cpu-probe.c | 21 ++++----------------- arch/mips/mm/c-r4k.c | 17 +++++------------ arch/mips/mm/tlbex.c | 8 +------- 4 files changed, 11 insertions(+), 38 deletions(-) diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h index c018727..3bdc0e3 100644 --- a/arch/mips/include/asm/cpu.h +++ b/arch/mips/include/asm/cpu.h @@ -209,8 +209,7 @@ enum cpu_type_enum { * MIPS32 class processors */ CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K, - CPU_AU1000, CPU_AU1100, CPU_AU1200, CPU_AU1210, CPU_AU1250, CPU_AU1500, - CPU_AU1550, CPU_PR4450, CPU_BCM3302, CPU_BCM4710, + CPU_ALCHEMY, CPU_PR4450, CPU_BCM3302, CPU_BCM4710, /* * MIPS64 class processors diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index a7162a4..0f33858 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -182,13 +182,7 @@ void __init check_wait(void) case CPU_TX49XX: cpu_wait = r4k_wait_irqoff; break; - case CPU_AU1000: - case CPU_AU1100: - case CPU_AU1500: - case CPU_AU1550: - case CPU_AU1200: - case CPU_AU1210: - case CPU_AU1250: + case CPU_ALCHEMY: cpu_wait = au1k_wait; break; case CPU_20KC: @@ -782,37 +776,30 @@ static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu) switch (c->processor_id & 0xff00) { case PRID_IMP_AU1_REV1: case PRID_IMP_AU1_REV2: + c->cputype = CPU_ALCHEMY; switch ((c->processor_id >> 24) & 0xff) { case 0: - c->cputype = CPU_AU1000; __cpu_name[cpu] = "Au1000"; break; case 1: - c->cputype = CPU_AU1500; __cpu_name[cpu] = "Au1500"; break; case 2: - c->cputype = CPU_AU1100; __cpu_name[cpu] = "Au1100"; break; case 3: - c->cputype = CPU_AU1550; __cpu_name[cpu] = "Au1550"; break; case 4: - c->cputype = CPU_AU1200; __cpu_name[cpu] = "Au1200"; - if ((c->processor_id & 0xff) == 2) { - c->cputype = CPU_AU1250; + if ((c->processor_id & 0xff) == 2) __cpu_name[cpu] = "Au1250"; - } break; case 5: - c->cputype = CPU_AU1210; __cpu_name[cpu] = "Au1210"; break; default: - panic("Unknown Au Core!"); + __cpu_name[cpu] = "Au1xxx"; break; } break; diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index 6e99665..2f9cded 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -1006,13 +1006,7 @@ static void __cpuinit probe_pcache(void) c->icache.flags |= MIPS_CACHE_VTAG; break; - case CPU_AU1000: - case CPU_AU1500: - case CPU_AU1100: - case CPU_AU1550: - case CPU_AU1200: - case CPU_AU1210: - case CPU_AU1250: + case CPU_ALCHEMY: c->icache.flags |= MIPS_CACHE_IC_F_DC; break; } @@ -1224,7 +1218,7 @@ void au1x00_fixup_config_od(void) /* * Au1100 errata actually keeps silence about this bit, so we set it * just in case for those revisions that require it to be set according - * to arch/mips/au1000/common/cputable.c + * to the (now gone) cpu table. */ case 0x02030200: /* Au1100 AB */ case 0x02030201: /* Au1100 BA */ @@ -1294,11 +1288,10 @@ static void __cpuinit coherency_setup(void) break; /* * We need to catch the early Alchemy SOCs with - * the write-only co_config.od bit and set it back to one... + * the write-only co_config.od bit and set it back to one on: + * Au1000 rev DA, HA, HB; Au1100 AB, BA, BC, Au1500 AB */ - case CPU_AU1000: /* rev. DA, HA, HB */ - case CPU_AU1100: /* rev. AB, BA, BC ?? */ - case CPU_AU1500: /* rev. AB */ + case CPU_ALCHEMY: au1x00_fixup_config_od(); break; diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index 4294203..00ac573 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -292,13 +292,7 @@ static void __cpuinit build_tlb_write_entry(u32 **p, struct uasm_label **l, case CPU_R4300: case CPU_5KC: case CPU_TX49XX: - case CPU_AU1000: - case CPU_AU1100: - case CPU_AU1500: - case CPU_AU1550: - case CPU_AU1200: - case CPU_AU1210: - case CPU_AU1250: + case CPU_ALCHEMY: case CPU_PR4450: uasm_i_nop(p); tlbw(p); -- 1.6.1 From ihar.hrachyshka@gmail.com Tue Jan 13 14:11:35 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 13 Jan 2009 14:11:37 +0000 (GMT) Received: from rn-out-0910.google.com ([64.233.170.188]:52675 "EHLO rn-out-0910.google.com") by ftp.linux-mips.org with ESMTP id S21103605AbZAMOLf (ORCPT ); Tue, 13 Jan 2009 14:11:35 +0000 Received: by rn-out-0910.google.com with SMTP id j66so20405rne.9 for ; Tue, 13 Jan 2009 06:11:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:subject:from:to:content-type :date:message-id:mime-version:x-mailer:content-transfer-encoding; bh=X4GbO46qrS6uk9ZEjOme04B+9LMhfUo1JmE6HsrWghk=; b=cNR1UdxqQwkO7ZOniDwKMdDIWB6WFCjsszZasnYZoKz2DI8c19tL4iFot3nMymKU0x n3J4yc+PC3XYgWsaU3YLFbDZiuWxNsBswR/8pE5hst1IpV38oxVrnNxKSP889/oNft3X WOx8wppN19VMTYCApM50JTMpNTs6OVnY+TlGY= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=subject:from:to:content-type:date:message-id:mime-version:x-mailer :content-transfer-encoding; b=TZzeVMOBHLNlxiq5PpIT+MUzCe4Pqu0jL/E/tnbA7RdnCYpVV5r590pSnIhlwodZii HdXfqNlLeT+j45f3tmDFnaW2t9Us+7G9J+mYeDgT95i/MvIynpo9wtoh2MnBUICf28ea HgmN/dnjvge6dfHPZWZP0NZ0BlOtBL+CZV2jY= Received: by 10.100.108.20 with SMTP id g20mr16437642anc.14.1231855893881; Tue, 13 Jan 2009 06:11:33 -0800 (PST) Received: from ?10.6.11.31? (cpmsq.epam.com [217.21.56.2]) by mx.google.com with ESMTPS id c9sm6653587ana.8.2009.01.13.06.11.30 (version=SSLv3 cipher=RC4-MD5); Tue, 13 Jan 2009 06:11:31 -0800 (PST) Subject: [PATCH] Added serial UART support for PNX833X devices. From: Ihar Hrachyshka To: linux-mips@linux-mips.org Content-Type: text/plain Date: Tue, 13 Jan 2009 16:11:26 +0200 Message-Id: <1231855886.25974.22.camel@EPBYMINW0568> Mime-Version: 1.0 X-Mailer: Evolution 2.24.2 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21718 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ihar.hrachyshka@gmail.com Precedence: bulk X-list: linux-mips Content-Length: 656 Lines: 24 Enabled serial UART driver for PNX833X devices. Signed-off-by: Manuel Lauss --- drivers/serial/Kconfig | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 3e525e3..7d7f576 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -982,7 +982,7 @@ config SERIAL_SH_SCI_CONSOLE config SERIAL_PNX8XXX bool "Enable PNX8XXX SoCs' UART Support" - depends on MIPS && SOC_PNX8550 + depends on MIPS && (SOC_PNX8550 || SOC_PNX833X) select SERIAL_CORE help If you have a MIPS-based Philips SoC such as PNX8550 or PNX8330 -- 1.5.6.3 From ihar.hrachyshka@gmail.com Tue Jan 13 14:19:21 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 13 Jan 2009 14:19:24 +0000 (GMT) Received: from an-out-0708.google.com ([209.85.132.240]:59347 "EHLO an-out-0708.google.com") by ftp.linux-mips.org with ESMTP id S21103557AbZAMOTV (ORCPT ); Tue, 13 Jan 2009 14:19:21 +0000 Received: by an-out-0708.google.com with SMTP id d14so9075and.24 for ; Tue, 13 Jan 2009 06:19:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:subject:from:to:content-type :date:message-id:mime-version:x-mailer:content-transfer-encoding; bh=C5bvhM89DPdUKBaPz2AmWOuUXcCHy7DYDMEewyVhYm8=; b=eUWoijcJ5YWcA084UynLPd/OzpSJi1Hq4tId0LG8i3aYdmkyI/mJEdH90+AsPIpgAJ aU2oq2m9x+ktxgEjk3ICkbkof+OLqe+mGCEo2BfRMA+9JGGzNvYCNNaFl/Kf399EiFZ8 GmptnsAArwV+mxDxhn5WZ4GTP+91XQW8n8+pE= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=subject:from:to:content-type:date:message-id:mime-version:x-mailer :content-transfer-encoding; b=lUSoAmdW1yTyvK3hN+8lKsJqnlABHSagTEi+C8t9U4VRULFIpgIMdBtL2CFYBY7zJe 6/bk+hiH6hjqpmDjmERhOO3ETseMvgBIUe2V8M+HnzDzpU9IInFczm40gMNZJ+5s4JGy PUCcopvNBzyIZHuXgJnE6k/yorVxyPAH/IEb8= Received: by 10.100.232.10 with SMTP id e10mr16448230anh.36.1231856360284; Tue, 13 Jan 2009 06:19:20 -0800 (PST) Received: from ?10.6.11.31? (cpmsq.epam.com [217.21.56.2]) by mx.google.com with ESMTPS id b32sm8370136ana.34.2009.01.13.06.19.18 (version=SSLv3 cipher=RC4-MD5); Tue, 13 Jan 2009 06:19:19 -0800 (PST) Subject: [PATCH] Added serial UART support for PNX833X devices. From: Ihar Hrachyshka To: linux-mips@linux-mips.org Content-Type: text/plain Date: Tue, 13 Jan 2009 16:19:17 +0200 Message-Id: <1231856357.25974.23.camel@EPBYMINW0568> Mime-Version: 1.0 X-Mailer: Evolution 2.24.2 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21719 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ihar.hrachyshka@gmail.com Precedence: bulk X-list: linux-mips Content-Length: 656 Lines: 24 Enabled serial UART driver for PNX833X devices. Signed-off-by: Ihar Hrachyshka --- drivers/serial/Kconfig | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 3e525e3..7d7f576 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -982,7 +982,7 @@ config SERIAL_SH_SCI_CONSOLE config SERIAL_PNX8XXX bool "Enable PNX8XXX SoCs' UART Support" - depends on MIPS && SOC_PNX8550 + depends on MIPS && (SOC_PNX8550 || SOC_PNX833X) select SERIAL_CORE help If you have a MIPS-based Philips SoC such as PNX8550 or PNX8330 -- 1.5.6.3 From ihar.hrachyshka@gmail.com Tue Jan 13 14:20:17 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 13 Jan 2009 14:20:20 +0000 (GMT) Received: from mail-bw0-f13.google.com ([209.85.218.13]:18679 "EHLO mail-bw0-f13.google.com") by ftp.linux-mips.org with ESMTP id S21103557AbZAMOUR (ORCPT ); Tue, 13 Jan 2009 14:20:17 +0000 Received: by bwz6 with SMTP id 6so83930bwz.0 for ; Tue, 13 Jan 2009 06:20:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:in-reply-to:references :date:message-id:subject:from:to:content-type :content-transfer-encoding; bh=5zrVlxErMebRBTLOeExn+B0oBeXsmDTxkUUzYHrte8g=; b=LdMevHpIcLIoPzhVsWGIQ+h42mIEGmH8I+yj45j5zCmCNNDsOllvBY3VOeaV5tnhRb T/2J8gdzvzvU49UZvMna9qhpV2bVW44poPDRNd+DJAr3PGAflkaSSE0aCQce/OE2320R wbjustD040wz6JarsK36TEFRXVJziCm1V9IMg= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :content-type:content-transfer-encoding; b=XUpRNbTDVyWzb6Nr41Car8Op1edrQbYnFeAsjU3ydC5LNRe+xOyhYRajnvqn7RgL46 IbDQCKfW/0288MQoodefZH1DBIXOP2+sW/o048a5amWK0Pho5h3vR0s2Ru34dmk6JK5J CmuFvlwxDZSHlPgyJz7LPxMReHb4TWxjzlv0g= MIME-Version: 1.0 Received: by 10.181.216.12 with SMTP id t12mr11399669bkq.122.1231856410419; Tue, 13 Jan 2009 06:20:10 -0800 (PST) In-Reply-To: <1231855886.25974.22.camel@EPBYMINW0568> References: <1231855886.25974.22.camel@EPBYMINW0568> Date: Tue, 13 Jan 2009 16:20:10 +0200 Message-ID: Subject: Re: [PATCH] Added serial UART support for PNX833X devices. From: Ihar Hrachyshka To: linux-mips@linux-mips.org Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21720 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ihar.hrachyshka@gmail.com Precedence: bulk X-list: linux-mips Content-Length: 873 Lines: 29 Sorry guys. That patch had a wrong signer one ;) Resent. On Tue, Jan 13, 2009 at 4:11 PM, Ihar Hrachyshka wrote: > Enabled serial UART driver for PNX833X devices. > > Signed-off-by: Manuel Lauss > --- > drivers/serial/Kconfig | 2 +- > 1 files changed, 1 insertions(+), 1 deletions(-) > > diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig > index 3e525e3..7d7f576 100644 > --- a/drivers/serial/Kconfig > +++ b/drivers/serial/Kconfig > @@ -982,7 +982,7 @@ config SERIAL_SH_SCI_CONSOLE > > config SERIAL_PNX8XXX > bool "Enable PNX8XXX SoCs' UART Support" > - depends on MIPS && SOC_PNX8550 > + depends on MIPS && (SOC_PNX8550 || SOC_PNX833X) > select SERIAL_CORE > help > If you have a MIPS-based Philips SoC such as PNX8550 or PNX8330 > -- > 1.5.6.3 > > > From mano@roarinelk.homelinux.net Tue Jan 13 14:38:54 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 13 Jan 2009 14:38:56 +0000 (GMT) Received: from fnoeppeil36.netpark.at ([217.175.205.164]:10624 "EHLO roarinelk.homelinux.net") by ftp.linux-mips.org with ESMTP id S21103512AbZAMOiy (ORCPT ); Tue, 13 Jan 2009 14:38:54 +0000 Received: (qmail 18794 invoked by uid 1000); 13 Jan 2009 15:35:52 +0100 Date: Tue, 13 Jan 2009 15:35:52 +0100 From: Manuel Lauss To: Linux-MIPS Subject: [RFC PATCH] Alchemy: detect Au1300 Message-ID: <20090113143552.GA18721@roarinelk.homelinux.net> References: <20090113135302.GA18442@roarinelk.homelinux.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20090113135302.GA18442@roarinelk.homelinux.net> User-Agent: Mutt/1.5.16 (2007-06-09) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21721 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mano@roarinelk.homelinux.net Precedence: bulk X-list: linux-mips Content-Length: 2685 Lines: 95 Add code to detect Au1300 and its variants. c0_prid uses a layout different from previous Alchemy chips and company ID switched to RMI. Core and cache-wise it is compatible with previous Alchemy chips. Signed-off-by: Manuel Lauss --- This patch depends on "Alchemy: remove superfluous cpu-model constants." Information was pieced together from the Au1300 databook, and obviously only compile tested. (Also, the irq controller looks completely different so this patch alone is insufficient to get linux working on it). arch/mips/include/asm/cpu.h | 1 + arch/mips/kernel/cpu-probe.c | 39 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 40 insertions(+), 0 deletions(-) diff --git a/arch/mips/include/asm/cpu.h b/arch/mips/include/asm/cpu.h index 3bdc0e3..8dd3038 100644 --- a/arch/mips/include/asm/cpu.h +++ b/arch/mips/include/asm/cpu.h @@ -33,6 +33,7 @@ #define PRID_COMP_TOSHIBA 0x070000 #define PRID_COMP_LSI 0x080000 #define PRID_COMP_LEXRA 0x0b0000 +#define PRID_COMP_RMI 0x0c0000 #define PRID_COMP_CAVIUM 0x0d0000 diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index 0f33858..9499610 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include #include @@ -886,6 +887,41 @@ static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu) } } +static inline void cpu_probe_rmi(struct cpuinfo_mips *c, unsigned int cpu) +{ + decode_configs(c); + switch (c->processor_id & 0xff000000) { + case 0x80000000: /* Au1300 */ + c->cputype = CPU_ALCHEMY; + + /* OTP-ROM Config0 register indicates the presence + * of various peripherals. Combinations of those + * bits are marketed unter different names. + */ + switch (__raw_readl((void *)0xb0002000)) { + case 0x00000000: + __cpu_name[cpu] = "Au1380"; + break; + case 0x0000000d: + __cpu_name[cpu] = "Au1370"; + break; + case 0x00000010: + __cpu_name[cpu] = "Au1350"; + break; + case 0x0000001d: + __cpu_name[cpu] = "Au1340"; + break; + default: + __cpu_name[cpu] = "Au1300"; + break; + } + default: + printk(KERN_INFO "Unknown RMI chip!\n"); + c->cputype = CPU_UNKNOWN; + break; + } +} + const char *__cpu_name[NR_CPUS]; __cpuinit void cpu_probe(void) @@ -920,6 +956,9 @@ __cpuinit void cpu_probe(void) case PRID_COMP_NXP: cpu_probe_nxp(c, cpu); break; + case PRID_COMP_RMI: + cpu_probe_rmi(c, cpu); + break; case PRID_COMP_CAVIUM: cpu_probe_cavium(c, cpu); break; -- 1.6.1 From khickey@rmicorp.com Tue Jan 13 14:42:22 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 13 Jan 2009 14:42:24 +0000 (GMT) Received: from mx1.razamicroelectronics.com ([63.111.213.197]:25259 "EHLO hq-ex-mb01.razamicroelectronics.com") by ftp.linux-mips.org with ESMTP id S21103512AbZAMOmW (ORCPT ); Tue, 13 Jan 2009 14:42:22 +0000 Received: from 10.8.0.20 ([10.8.0.20]) by hq-ex-mb01.razamicroelectronics.com ([10.1.1.40]) via Exchange Front-End Server webmail.razamicroelectronics.com ([10.1.1.41]) with Microsoft Exchange Server HTTP-DAV ; Tue, 13 Jan 2009 14:42:13 +0000 Received: from kh-d820 by webmail.razamicroelectronics.com; 13 Jan 2009 08:42:13 -0600 Subject: Re: [RFC PATCH] Alchemy: detect Au1300 From: Kevin Hickey To: Manuel Lauss Cc: Linux-MIPS In-Reply-To: <20090113143552.GA18721@roarinelk.homelinux.net> References: <20090113135302.GA18442@roarinelk.homelinux.net> <20090113143552.GA18721@roarinelk.homelinux.net> Content-Type: text/plain Content-Transfer-Encoding: 7bit Date: Tue, 13 Jan 2009 08:42:13 -0600 Message-Id: <1231857733.11541.1.camel@kh-d820> Mime-Version: 1.0 X-Mailer: Evolution 2.22.3.1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21722 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: khickey@rmicorp.com Precedence: bulk X-list: linux-mips Content-Length: 893 Lines: 25 It might make sense to hold off on this patch for now. I am going to be pushing out the first tested Au13xx code shortly. This detection and much more are covered. =Kevin On Tue, 2009-01-13 at 15:35 +0100, Manuel Lauss wrote: > Add code to detect Au1300 and its variants. c0_prid uses a layout > different from previous Alchemy chips and company ID switched to RMI. > > Core and cache-wise it is compatible with previous Alchemy chips. > > Signed-off-by: Manuel Lauss > --- > This patch depends on "Alchemy: remove superfluous cpu-model constants." > Information was pieced together from the Au1300 databook, and obviously > only compile tested. (Also, the irq controller looks completely different > so this patch alone is insufficient to get linux working on it). -- Kevin Hickey Alchemy Solutions RMI Corporation khickey@rmicorp.com P: 512.691.8044 From mano@roarinelk.homelinux.net Tue Jan 13 15:02:35 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 13 Jan 2009 15:02:37 +0000 (GMT) Received: from fnoeppeil36.netpark.at ([217.175.205.164]:16065 "EHLO roarinelk.homelinux.net") by ftp.linux-mips.org with ESMTP id S21103616AbZAMPCf (ORCPT ); Tue, 13 Jan 2009 15:02:35 +0000 Received: (qmail 18996 invoked by uid 1000); 13 Jan 2009 15:59:34 +0100 Date: Tue, 13 Jan 2009 15:59:34 +0100 From: Manuel Lauss To: Kevin Hickey Cc: Linux-MIPS Subject: Re: [RFC PATCH] Alchemy: detect Au1300 Message-ID: <20090113145934.GA18959@roarinelk.homelinux.net> References: <20090113135302.GA18442@roarinelk.homelinux.net> <20090113143552.GA18721@roarinelk.homelinux.net> <1231857733.11541.1.camel@kh-d820> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1231857733.11541.1.camel@kh-d820> User-Agent: Mutt/1.5.16 (2007-06-09) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21723 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mano@roarinelk.homelinux.net Precedence: bulk X-list: linux-mips Content-Length: 286 Lines: 12 On Tue, Jan 13, 2009 at 08:42:13AM -0600, Kevin Hickey wrote: > It might make sense to hold off on this patch for now. I am going to be > pushing out the first tested Au13xx code shortly. This detection and > much more are covered. Oh, cool, even better! Thanks! > =Kevin -- ml. From ihar.hrachyshka@gmail.com Tue Jan 13 15:07:55 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 13 Jan 2009 15:07:57 +0000 (GMT) Received: from an-out-0708.google.com ([209.85.132.244]:59334 "EHLO an-out-0708.google.com") by ftp.linux-mips.org with ESMTP id S21103613AbZAMPHz (ORCPT ); Tue, 13 Jan 2009 15:07:55 +0000 Received: by an-out-0708.google.com with SMTP id d14so17801and.24 for ; Tue, 13 Jan 2009 07:07:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:subject:from:to:content-type :date:message-id:mime-version:x-mailer:content-transfer-encoding; bh=zynWAcqnwVH9cJGXKfyE0gvkC/tlUSvpVzZve4F+jQs=; b=YNA3BeKXGrVBr7yxKZVKCdiF0Uidq0hMFn1vnpIVGW2TkKSVCaIIw6LPrSCkS5BkyD nZ9X+SFwX/RU4DNg0KFfsEHWmqz8W9H2drquSQndatuvNBnl2ZBM7W8lLOWb4fwE4LWX bP3UHDok0TmLfgzax+rFmqU0Zx816irvwylrY= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=subject:from:to:content-type:date:message-id:mime-version:x-mailer :content-transfer-encoding; b=dLeBVCefUPYSi83nO8OYd1g3L8vB6ZAoceA0icRDbcfzHSv5Q+0wkB2uLr8lgahZk/ rv30Gk/YTMwoD3OF94Px3DtyDurwRvWfhe9HPzdJP/pXofU/vaAua3x7y2jiMG6om0h2 Hq22sFWZhUyNxtDNqbBsV7RuE7iSpI48glZlo= Received: by 10.100.178.9 with SMTP id a9mr16477181anf.59.1231859273628; Tue, 13 Jan 2009 07:07:53 -0800 (PST) Received: from ?10.6.11.31? (cpmsq.epam.com [217.21.56.2]) by mx.google.com with ESMTPS id c1sm7833715ana.19.2009.01.13.07.07.51 (version=SSLv3 cipher=RC4-MD5); Tue, 13 Jan 2009 07:07:52 -0800 (PST) Subject: [pnx833x_port]: device name prefix - ttyS or ttySA? From: Ihar Hrachyshka To: linux-mips@linux-mips.org Content-Type: text/plain Date: Tue, 13 Jan 2009 17:07:50 +0200 Message-Id: <1231859270.25974.32.camel@EPBYMINW0568> Mime-Version: 1.0 X-Mailer: Evolution 2.24.2 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21724 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ihar.hrachyshka@gmail.com Precedence: bulk X-list: linux-mips Content-Length: 297 Lines: 6 In 'drivers/serial/pnx833x_port.c' we define the prefix for UART serial device as "ttyS". Anyway, we use major:minor numbers for SA1100 serial driver (that are 204:5). Why don't we use "ttySA" prefix then? That's what different embedded build systems expect for populating /dev (f.e. buildroot). From f.fainelli@gmail.com Tue Jan 13 17:30:56 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 13 Jan 2009 17:31:02 +0000 (GMT) Received: from mail-bw0-f13.google.com ([209.85.218.13]:55778 "EHLO mail-bw0-f13.google.com") by ftp.linux-mips.org with ESMTP id S21103555AbZAMRa4 convert rfc822-to-8bit (ORCPT ); Tue, 13 Jan 2009 17:30:56 +0000 Received: by bwz6 with SMTP id 6so382548bwz.0 for ; Tue, 13 Jan 2009 09:30:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:sender:from:to:subject:date :user-agent:cc:references:in-reply-to:mime-version:content-type :content-transfer-encoding:content-disposition:message-id; bh=16FP2KSxRW74YuLo3Fr9ke/aMPgHh8JgsuvF94kVkCs=; b=qR/uuUjqkEPDmM2De0nsaQDqU5ALN2wxZeIU+8tOggoMWZhmYeByHepU+AHSMZgP3n uKHCRyaMAgqJBLrCqFxS6+3LHrnxm9vuvnqiDqA3tDt5ApK5qSOsVJ/qc+GbhAd4p4e4 A+HFp4hELaCml6v+j2BJXF8/HU4dEZxSC/v1g= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:from:to:subject:date:user-agent:cc:references:in-reply-to :mime-version:content-type:content-transfer-encoding :content-disposition:message-id; b=mleboKyxVJxUfaKsNt8nVkhnSotZAe2OGKdl5CMezKixL5aRVv6uyB2ca+YAOo5PH1 QrBROcyA7WJ1JATmvLWEs5CGOo0pwi7Mvf2g+XmG44XzlU3Hbuih9Gagd3xvinXdV1e9 0m6O4RPuA4C68FIIWyJanv6NVkZwVTp9osrxo= Received: by 10.103.245.18 with SMTP id x18mr11413270mur.62.1231867848086; Tue, 13 Jan 2009 09:30:48 -0800 (PST) Received: from flowlan.maisel.int-evry.fr ([157.159.47.25]) by mx.google.com with ESMTPS id n7sm17217050mue.54.2009.01.13.09.30.46 (version=TLSv1/SSLv3 cipher=RC4-MD5); Tue, 13 Jan 2009 09:30:47 -0800 (PST) From: Florian Fainelli To: Ihar Hrachyshka Subject: Re: [pnx833x_port]: device name prefix - ttyS or ttySA? Date: Tue, 13 Jan 2009 18:30:31 +0100 User-Agent: KMail/1.9.9 Cc: linux-mips@linux-mips.org References: <1231859270.25974.32.camel@EPBYMINW0568> In-Reply-To: <1231859270.25974.32.camel@EPBYMINW0568> MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-15" Content-Transfer-Encoding: 8BIT Content-Disposition: inline Message-Id: <200901131830.32900.florian@openwrt.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21725 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips Content-Length: 710 Lines: 19 Hi, Le Tuesday 13 January 2009 16:07:50 Ihar Hrachyshka, vous avez écrit : > In 'drivers/serial/pnx833x_port.c' we define the prefix for UART serial > device as "ttyS". Anyway, we use major:minor numbers for SA1100 serial > driver (that are 204:5). Why don't we use "ttySA" prefix then? That's > what different embedded build systems expect for populating /dev (f.e. > buildroot). In my experience, everything that is not ttyS is a bit confusing either when creating the devices in the roots, or when using the serial console in the kernel command line. So I will vote for ttyS. My 2 cents. -- Best regards, Florian Fainelli Email : florian@openwrt.org http://openwrt.org ------------------------------- From sshtylyov@ru.mvista.com Tue Jan 13 17:38:49 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 13 Jan 2009 17:38:51 +0000 (GMT) Received: from h155.mvista.com ([63.81.120.155]:32544 "EHLO imap.sh.mvista.com") by ftp.linux-mips.org with ESMTP id S21103555AbZAMRit (ORCPT ); Tue, 13 Jan 2009 17:38:49 +0000 Received: from [192.168.1.234] (unknown [10.150.0.9]) by imap.sh.mvista.com (Postfix) with ESMTP id 317723EC9; Tue, 13 Jan 2009 09:38:46 -0800 (PST) Message-ID: <496CD1CB.60805@ru.mvista.com> Date: Tue, 13 Jan 2009 20:39:23 +0300 From: Sergei Shtylyov Organization: MontaVista Software Inc. User-Agent: Mozilla/5.0 (X11; U; Linux i686; rv:1.7.2) Gecko/20040803 X-Accept-Language: ru, en-us, en-gb MIME-Version: 1.0 To: Ihar Hrachyshka Cc: linux-mips@linux-mips.org Subject: Re: [pnx833x_port]: device name prefix - ttyS or ttySA? References: <1231859270.25974.32.camel@EPBYMINW0568> In-Reply-To: <1231859270.25974.32.camel@EPBYMINW0568> Content-Type: text/plain; charset=us-ascii; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21726 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sshtylyov@ru.mvista.com Precedence: bulk X-list: linux-mips Content-Length: 229 Lines: 11 Hello. Ihar Hrachyshka wrote: > In 'drivers/serial/pnx833x_port.c' we define the prefix for UART serial > device as "ttyS". Anyway, we use major:minor numbers for SA1100 serial > driver (that are 204:5). Why? WBR, Sergei From ihar.hrachyshka@gmail.com Tue Jan 13 18:13:17 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 13 Jan 2009 18:13:19 +0000 (GMT) Received: from mail-bw0-f13.google.com ([209.85.218.13]:54163 "EHLO mail-bw0-f13.google.com") by ftp.linux-mips.org with ESMTP id S21103627AbZAMSNR (ORCPT ); Tue, 13 Jan 2009 18:13:17 +0000 Received: by bwz6 with SMTP id 6so448758bwz.0 for ; Tue, 13 Jan 2009 10:13:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:in-reply-to:references :date:message-id:subject:from:to:content-type :content-transfer-encoding; bh=kBAcKo0UxlTgn8Lbgf28BmpiYtMqHq1WUP5K6uORiWs=; b=H58lblTLpH72oCtLikcBblmmByIeH2lBcB4qEyQ7h32oG5WzwQsaEuYAQdYHkTuFLH ivGsCmmMxPaXwOt/5xcCIS4MgnPLvx6hX0v5HI4a7K8Tx16q1EabKf36S4xK0r4XufzQ z4SyhacGnOcFgbObBLCgFp+qBGqfUFDWZGV58= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :content-type:content-transfer-encoding; b=HxAX6tLBXOU0lb0IcZxJS+KM5Ze5L6SOgoh117C/rPxjnk77f2KgvuQOo7jcbO39ZY 7XaPMTVfSqST1XoQYpUv6Vb/UeWmz+tKmOELtPTp9r15w4YRciRrV3RtIKUxlkqpkrIX TqlZvBxnQeoICqs1eJ9Oqou9o7Xuhinf+pVwA= MIME-Version: 1.0 Received: by 10.181.197.1 with SMTP id z1mr11458354bkp.118.1231870390825; Tue, 13 Jan 2009 10:13:10 -0800 (PST) In-Reply-To: References: <1231859270.25974.32.camel@EPBYMINW0568> Date: Tue, 13 Jan 2009 20:13:10 +0200 Message-ID: Subject: Re: [pnx833x_port]: device name prefix - ttyS or ttySA? From: Ihar Hrachyshka To: Daniel James Laird , linux-mips@linux-mips.org Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21727 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ihar.hrachyshka@gmail.com Precedence: bulk X-list: linux-mips Content-Length: 1802 Lines: 43 On Tue, Jan 13, 2009 at 7:09 PM, Daniel James Laird wrote: > I cant find the file you are talking about however Sorry, I misspelled the file name. It's 'drivers/serial/pnx8xxx_uart.c' instead. > I think that the major number should infact be 4 with a minor number of 64,65,66 etc. This seems to be what other devices do. This would mean you can still be ttyS... but not clash with SA1100 if that's what you mean. You're wrong. There are lots of board specific serial drivers that define special major-minor numbers. For example look at sc26xx, mpc52xx_uart, bfin_5xx drivers. The problem with pnx8xxx_uart driver is that it uses special major:minor numbers for generic ttyS* devices. I think we need one of these changes: 1) make a special CONFIG_PNX8XXX_UART_TTYS option for switching between ttyS*+4:64 and ttySA*+204:5 variants (see f.e. atmel_serial driver). Of course this CONFIG_PNX8XXX_UART_TTYS option will be disabled if CONFIG_SERIAL_8250 enabled. 2) Just stick with ttySA*+204:5 (not with ttyS*+204:5 as it's now). Please tell me what you prefer and I'll send you a patch. > > With regards, > Daniel Laird > > Daniel Laird, Software Engineer > NXP Semiconductors, BU Home, BL STB > > -----Original Message----- > From: linux-mips-bounce@linux-mips.org [mailto:linux-mips-bounce@linux-mips.org] On Behalf Of Ihar Hrachyshka > Sent: 2009 Jan 13 15:08 > To: linux-mips@linux-mips.org > Subject: [pnx833x_port]: device name prefix - ttyS or ttySA? > > In 'drivers/serial/pnx833x_port.c' we define the prefix for UART serial > device as "ttyS". Anyway, we use major:minor numbers for SA1100 serial > driver (that are 204:5). Why don't we use "ttySA" prefix then? That's > what different embedded build systems expect for populating /dev (f.e. > buildroot). > > > From ihar.hrachyshka@gmail.com Tue Jan 13 18:15:19 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 13 Jan 2009 18:15:21 +0000 (GMT) Received: from mail-bw0-f13.google.com ([209.85.218.13]:36016 "EHLO mail-bw0-f13.google.com") by ftp.linux-mips.org with ESMTP id S21103632AbZAMSPT convert rfc822-to-8bit (ORCPT ); Tue, 13 Jan 2009 18:15:19 +0000 Received: by bwz6 with SMTP id 6so451725bwz.0 for ; Tue, 13 Jan 2009 10:15:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:in-reply-to:references :date:message-id:subject:from:to:cc:content-type :content-transfer-encoding; bh=Rh5iKykZkzkGf+gn8VustrI+zNR4eBFUFTiFIKFUvgw=; b=SBUh1dn3zCrDr7Yg+ayQAFM1z5N7bYUA/1e4XFAqPCQJuUIN55arbC4DEFDnpFsAI3 05rrEI76RpouRTxvTdeEvgqZA5kkaNB/uZcAEpFfvQkYz4z8ZNArF1ZYVACE/JenyAIq ucGE4qxqwOAoVuaH64sF4kX9jCAJLslGPcXXU= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type:content-transfer-encoding; b=M+TUkasBx1T0HJKu1eS+ey4vs7YgCC5vf9/YkJczR1axjcp5YoXOcfvCG2F+58FYrD ZRBr912srQWfzu4G2MLH84pciglF8/dkwQdwSTI5Z6dkULilY2IDZXBq6acfqbCrN0x3 4z5t/fRLsETkJzUNQrZdFtm/gI9jOaWzWYX0E= MIME-Version: 1.0 Received: by 10.181.235.6 with SMTP id m6mr11470022bkr.131.1231870512750; Tue, 13 Jan 2009 10:15:12 -0800 (PST) In-Reply-To: <200901131830.32900.florian@openwrt.org> References: <1231859270.25974.32.camel@EPBYMINW0568> <200901131830.32900.florian@openwrt.org> Date: Tue, 13 Jan 2009 20:15:12 +0200 Message-ID: Subject: Re: [pnx833x_port]: device name prefix - ttyS or ttySA? From: Ihar Hrachyshka To: Florian Fainelli Cc: linux-mips@linux-mips.org Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8BIT Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21728 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ihar.hrachyshka@gmail.com Precedence: bulk X-list: linux-mips Content-Length: 975 Lines: 26 On Tue, Jan 13, 2009 at 7:30 PM, Florian Fainelli wrote: > Hi, > > Le Tuesday 13 January 2009 16:07:50 Ihar Hrachyshka, vous avez écrit : >> In 'drivers/serial/pnx833x_port.c' we define the prefix for UART serial >> device as "ttyS". Anyway, we use major:minor numbers for SA1100 serial >> driver (that are 204:5). Why don't we use "ttySA" prefix then? That's >> what different embedded build systems expect for populating /dev (f.e. >> buildroot). > > In my experience, everything that is not ttyS is a bit confusing either when > creating the devices in the roots, or when using the serial console in the > kernel command line. So I will vote for ttyS. The problem is that use-case with generic 8250 and board specific serial drivers both enabled is not a fantasy. So we need to differentiate between them. > > My 2 cents. > -- > Best regards, Florian Fainelli > Email : florian@openwrt.org > http://openwrt.org > ------------------------------- > From David.Daney@caviumnetworks.com Tue Jan 13 18:47:51 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 13 Jan 2009 18:47:53 +0000 (GMT) Received: from mail3.caviumnetworks.com ([12.108.191.235]:51515 "EHLO mail3.caviumnetworks.com") by ftp.linux-mips.org with ESMTP id S21103675AbZAMSrv (ORCPT ); Tue, 13 Jan 2009 18:47:51 +0000 Received: from exch4.caveonetworks.com (Not Verified[192.168.16.23]) by mail3.caviumnetworks.com with MailMarshal (v6,2,2,3503) id ; Tue, 13 Jan 2009 13:46:41 -0500 Received: from exch4.caveonetworks.com ([192.168.16.23]) by exch4.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Tue, 13 Jan 2009 10:45:40 -0800 Received: from dd1.caveonetworks.com ([64.169.86.201]) by exch4.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Tue, 13 Jan 2009 10:45:40 -0800 Message-ID: <496CE153.5010802@caviumnetworks.com> Date: Tue, 13 Jan 2009 10:45:39 -0800 From: David Daney User-Agent: Thunderbird 2.0.0.19 (X11/20090105) MIME-Version: 1.0 To: Andrew Morton , Rusty Russell , Linus Torvalds CC: Linux Kernel Mailing List , linux-mips , Mike Travis Subject: [PATCH 0/2] cpumask fallout: Initialize irq_default_affinity earlier et al. (v3) Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 13 Jan 2009 18:45:40.0076 (UTC) FILETIME=[21A1FAC0:01C975AF] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21729 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Content-Length: 2212 Lines: 54 Now that mips/OCTEON support has been merged, this patch set has slightly more urgency. The interrupt affinity on OCTEON is determined by irq_default_affinity, because that is what the code in kernel/irq/manage.c uses to set affinity. Since for the majority of devices (Serial, Compact Flash, Network...) we want interrupts to be handled on a single CPU, we set irq_default_affinity to the boot CPU in init_IRQ(). The problem we have is that with the new cpumask infrastructure, irq_default_affinity is being initialized in core_initcall which undoes our initialization. As I said in 2/2: Move the initialization of irq_default_affinity to early_irq_init as core_initcall is too late. irq_default_affinity can be used in init_IRQ and potentially timer and SMP init as well. All of these happen before core_initcall. Moving the initialization to early_irq_init ensures that it is initialized before it is used. Mike Travis pointed out that irq_default_affinity depends on CONFIG_GENERIC_HARDIRQS in addition to CONFIG_SMP. So to make things consistent, I added 1/2 so that the irq_*_affinity functions and irq_default_affinity are defined for the same conditions that they are declared. I Took Linus' suggestion to move init_irq_default_affinity over to kernel/irq/handle.c, however due to the way that cpumask_*() are defined, it is still necessary to have the ugly ifdefs, but now they are localized to init_irq_default_affinity. Mike Travis also suggested that alloc_bootmem_cpumask_var() be used in preference to alloc_cpumask_var, so I incorporated that suggestion as well. I tested both with and without CONFIG_SMP, on mips/cavium_octeon, Mike tested a similar(but not identical patch) on x86_64. Changes from v2 of this set are just a small rearrangement of the #ifdefs suggested by Ihar Hrachyshka that make the code look a bit cleaner. I will reply with the two patches. David Daney (2): Make irq_*_affinity depend on CONFIG_GENERIC_HARDIRQS too. cpumask fallout: Initialize irq_default_affinity earlier (v3). kernel/irq/handle.c | 16 ++++++++++++++++ kernel/irq/manage.c | 10 +--------- 2 files changed, 17 insertions(+), 9 deletions(-) From David.Daney@caviumnetworks.com Tue Jan 13 18:49:50 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 13 Jan 2009 18:49:52 +0000 (GMT) Received: from mail3.caviumnetworks.com ([12.108.191.235]:17471 "EHLO mail3.caviumnetworks.com") by ftp.linux-mips.org with ESMTP id S21103679AbZAMStt (ORCPT ); Tue, 13 Jan 2009 18:49:49 +0000 Received: from exch4.caveonetworks.com (Not Verified[192.168.16.23]) by mail3.caviumnetworks.com with MailMarshal (v6,2,2,3503) id ; Tue, 13 Jan 2009 13:48:46 -0500 Received: from exch4.caveonetworks.com ([192.168.16.23]) by exch4.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Tue, 13 Jan 2009 10:47:44 -0800 Received: from dd1.caveonetworks.com ([64.169.86.201]) by exch4.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Tue, 13 Jan 2009 10:47:43 -0800 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.2/8.14.2) with ESMTP id n0DIldDc021246; Tue, 13 Jan 2009 10:47:39 -0800 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.2/8.14.2/Submit) id n0DIlddc021245; Tue, 13 Jan 2009 10:47:39 -0800 From: David Daney To: rusty@rustcorp.com.au, torvalds@linux-foundation.org, akpm@linux-foundation.org Cc: linux-kernel@vger.kernel.org, linux-mips@linux-mips.org, travis@sgi.com, David Daney Subject: [PATCH 2/2] cpumask fallout: Initialize irq_default_affinity earlier (v3). Date: Tue, 13 Jan 2009 10:47:38 -0800 Message-Id: <1231872458-21218-2-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.5.6.6 In-Reply-To: <496CE153.5010802@caviumnetworks.com> References: <496CE153.5010802@caviumnetworks.com> X-OriginalArrivalTime: 13 Jan 2009 18:47:43.0949 (UTC) FILETIME=[6B777FD0:01C975AF] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21730 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Content-Length: 2151 Lines: 78 Move the initialization of irq_default_affinity to early_irq_init as core_initcall is too late. irq_default_affinity can be used in init_IRQ and potentially timer and SMP init as well. All of these happen before core_initcall. Moving the initialization to early_irq_init ensures that it is initialized before it is used. Signed-off-by: David Daney Acked-by: Mike Travis --- kernel/irq/handle.c | 16 ++++++++++++++++ kernel/irq/manage.c | 8 -------- 2 files changed, 16 insertions(+), 8 deletions(-) diff --git a/kernel/irq/handle.c b/kernel/irq/handle.c index c20db0b..3aba8d1 100644 --- a/kernel/irq/handle.c +++ b/kernel/irq/handle.c @@ -39,6 +39,18 @@ void handle_bad_irq(unsigned int irq, struct irq_desc *desc) ack_bad_irq(irq); } +#if defined(CONFIG_SMP) && defined(CONFIG_GENERIC_HARDIRQS) +static void __init init_irq_default_affinity(void) +{ + alloc_bootmem_cpumask_var(&irq_default_affinity); + cpumask_setall(irq_default_affinity); +} +#else +static void __init init_irq_default_affinity(void) +{ +} +#endif + /* * Linux has a controller-independent interrupt architecture. * Every controller has a 'controller-template', that is used @@ -134,6 +146,8 @@ int __init early_irq_init(void) int legacy_count; int i; + init_irq_default_affinity(); + desc = irq_desc_legacy; legacy_count = ARRAY_SIZE(irq_desc_legacy); @@ -219,6 +233,8 @@ int __init early_irq_init(void) int count; int i; + init_irq_default_affinity(); + desc = irq_desc; count = ARRAY_SIZE(irq_desc); diff --git a/kernel/irq/manage.c b/kernel/irq/manage.c index 618a64f..291f036 100644 --- a/kernel/irq/manage.c +++ b/kernel/irq/manage.c @@ -18,14 +18,6 @@ #if defined(CONFIG_SMP) && defined(CONFIG_GENERIC_HARDIRQS) cpumask_var_t irq_default_affinity; -static int init_irq_default_affinity(void) -{ - alloc_cpumask_var(&irq_default_affinity, GFP_KERNEL); - cpumask_setall(irq_default_affinity); - return 0; -} -core_initcall(init_irq_default_affinity); - /** * synchronize_irq - wait for pending IRQ handlers (on other CPUs) * @irq: interrupt number to wait for -- 1.5.6.6 From David.Daney@caviumnetworks.com Tue Jan 13 18:50:09 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 13 Jan 2009 18:50:11 +0000 (GMT) Received: from mail3.caviumnetworks.com ([12.108.191.235]:20287 "EHLO mail3.caviumnetworks.com") by ftp.linux-mips.org with ESMTP id S21103680AbZAMStu (ORCPT ); Tue, 13 Jan 2009 18:49:50 +0000 Received: from exch4.caveonetworks.com (Not Verified[192.168.16.23]) by mail3.caviumnetworks.com with MailMarshal (v6,2,2,3503) id ; Tue, 13 Jan 2009 13:48:45 -0500 Received: from exch4.caveonetworks.com ([192.168.16.23]) by exch4.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Tue, 13 Jan 2009 10:47:44 -0800 Received: from dd1.caveonetworks.com ([64.169.86.201]) by exch4.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Tue, 13 Jan 2009 10:47:43 -0800 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.2/8.14.2) with ESMTP id n0DIldpT021242; Tue, 13 Jan 2009 10:47:39 -0800 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.2/8.14.2/Submit) id n0DIlcuo021240; Tue, 13 Jan 2009 10:47:38 -0800 From: David Daney To: rusty@rustcorp.com.au, torvalds@linux-foundation.org, akpm@linux-foundation.org Cc: linux-kernel@vger.kernel.org, linux-mips@linux-mips.org, travis@sgi.com, David Daney Subject: [PATCH 1/2] Make irq_*_affinity depend on CONFIG_GENERIC_HARDIRQS too. Date: Tue, 13 Jan 2009 10:47:37 -0800 Message-Id: <1231872458-21218-1-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.5.6.6 In-Reply-To: <496CE153.5010802@caviumnetworks.com> References: <496CE153.5010802@caviumnetworks.com> X-OriginalArrivalTime: 13 Jan 2009 18:47:43.0949 (UTC) FILETIME=[6B777FD0:01C975AF] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21731 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Content-Length: 636 Lines: 25 In interrupt.h these functions are declared only if CONFIG_GENERIC_HARDIRQS is set. We should define them under identical conditions. Signed-off-by: David Daney --- kernel/irq/manage.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/kernel/irq/manage.c b/kernel/irq/manage.c index cd0cd8d..618a64f 100644 --- a/kernel/irq/manage.c +++ b/kernel/irq/manage.c @@ -15,7 +15,7 @@ #include "internals.h" -#ifdef CONFIG_SMP +#if defined(CONFIG_SMP) && defined(CONFIG_GENERIC_HARDIRQS) cpumask_var_t irq_default_affinity; static int init_irq_default_affinity(void) -- 1.5.6.6 From David.Daney@caviumnetworks.com Tue Jan 13 20:47:56 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 13 Jan 2009 20:48:01 +0000 (GMT) Received: from mail3.caviumnetworks.com ([12.108.191.235]:7732 "EHLO mail3.caviumnetworks.com") by ftp.linux-mips.org with ESMTP id S21364955AbZAMUr4 (ORCPT ); Tue, 13 Jan 2009 20:47:56 +0000 Received: from exch4.caveonetworks.com (Not Verified[192.168.16.23]) by mail3.caviumnetworks.com with MailMarshal (v6,2,2,3503) id ; Tue, 13 Jan 2009 15:47:41 -0500 Received: from exch4.caveonetworks.com ([192.168.16.23]) by exch4.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Tue, 13 Jan 2009 12:46:50 -0800 Received: from dd1.caveonetworks.com ([64.169.86.201]) by exch4.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Tue, 13 Jan 2009 12:46:49 -0800 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.2/8.14.2) with ESMTP id n0DKkjuw030165; Tue, 13 Jan 2009 12:46:45 -0800 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.2/8.14.2/Submit) id n0DKki0V030163; Tue, 13 Jan 2009 12:46:44 -0800 From: David Daney To: linux-mips@linux-mips.org Cc: David Daney Subject: [PATCH] 8250: Initialize more fields in early_serial_setup. Date: Tue, 13 Jan 2009 12:46:44 -0800 Message-Id: <1231879604-30140-1-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.5.6.6 X-OriginalArrivalTime: 13 Jan 2009 20:46:49.0639 (UTC) FILETIME=[0EA14370:01C975C0] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21732 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Content-Length: 748 Lines: 24 The initial patch that initialized the fields individually omitted a couple that evidently are required by mips/rb532. This should fix it. Signed-off-by: David Daney --- drivers/serial/8250.c | 2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/drivers/serial/8250.c b/drivers/serial/8250.c index 1889a63..e2c3a85 100644 --- a/drivers/serial/8250.c +++ b/drivers/serial/8250.c @@ -2837,6 +2837,8 @@ int __init early_serial_setup(struct uart_port *port) p->regshift = port->regshift; p->iotype = port->iotype; p->flags = port->flags; + p->type = port->type; + p->line = port->line; p->mapbase = port->mapbase; p->private_data = port->private_data; -- 1.5.6.6 From ihar.hrachyshka@gmail.com Wed Jan 14 13:55:49 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 14 Jan 2009 13:55:51 +0000 (GMT) Received: from yw-out-1718.google.com ([74.125.46.158]:52130 "EHLO yw-out-1718.google.com") by ftp.linux-mips.org with ESMTP id S21365750AbZANNzo (ORCPT ); Wed, 14 Jan 2009 13:55:44 +0000 Received: by yw-out-1718.google.com with SMTP id 9so200704ywk.24 for ; Wed, 14 Jan 2009 05:55:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:subject:from:to:content-type :date:message-id:mime-version:x-mailer:content-transfer-encoding; bh=pae7GQIf1G2edhxm2QW2xBMtSItzIXj2ulDnj/vs6es=; b=XqZgo7ZWPqK46HyBrXKtTU0uk4qbkG/6X/hYKEraEN5w8cWDc/zkytCf70vmaVkPzc k3TbQO8Kz/ni7K9RU5N653pv8uMF2hwxeklB4IPIW16Fs3y6R+4hK6JiEG3m91qE+p5k g0dJa6aBtzqjDWMPWvbyrAwVKXwqGveYyEHww= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=subject:from:to:content-type:date:message-id:mime-version:x-mailer :content-transfer-encoding; b=I+L2NV5fDG5MbbVMhx15gbryBGVus5j2eyhx7liJ8J06+/BhRZgRYf4FNSYDiv3Vnp ZiwtPifMBOEt2uaQsL78rAiJO/hhm212+WFEoH14i2B9UtJAP4Lqfpo1fxsF5ORJA7+G KozN+QlsrYZmPgW0BUHXTm2eOBH7ZmK8QIrEs= Received: by 10.100.3.13 with SMTP id 13mr93889anc.26.1231941341082; Wed, 14 Jan 2009 05:55:41 -0800 (PST) Received: from ?10.6.11.31? (cpmsq.epam.com [217.21.56.2]) by mx.google.com with ESMTPS id d12sm27840221and.2.2009.01.14.05.55.39 (version=SSLv3 cipher=RC4-MD5); Wed, 14 Jan 2009 05:55:40 -0800 (PST) Subject: [PATCH] Don't use ttyS* serial device name for board specific PNX8XXX UART serial From: Ihar Hrachyshka To: linux-mips@linux-mips.org Content-Type: text/plain Date: Wed, 14 Jan 2009 15:55:38 +0200 Message-Id: <1231941338.7186.3.camel@EPBYMINW0568> Mime-Version: 1.0 X-Mailer: Evolution 2.24.2 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21733 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ihar.hrachyshka@gmail.com Precedence: bulk X-list: linux-mips Content-Length: 1465 Lines: 46 Don't use ttyS* serial device name for board specific PNX8XXX UART serial. Rather create ttySA* to reflect that the driver uses device with major:minor numbers for SA1100 serial driver. Signed-off-by: Ihar Hrachyshka --- drivers/serial/pnx8xxx_uart.c | 8 ++++---- 1 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/serial/pnx8xxx_uart.c b/drivers/serial/pnx8xxx_uart.c index 22e30d2..6785ee9 100644 --- a/drivers/serial/pnx8xxx_uart.c +++ b/drivers/serial/pnx8xxx_uart.c @@ -636,7 +636,7 @@ static struct uart_ops pnx8xxx_pops = { /* * Setup the PNX8XXX serial ports. * - * Note also that we support "console=ttySx" where "x" is either 0 or 1. + * Note also that we support "console=ttySAx" where "x" is either 0 or 1. */ static void __init pnx8xxx_init_ports(void) { @@ -728,7 +728,7 @@ pnx8xxx_console_setup(struct console *co, char *options) static struct uart_driver pnx8xxx_reg; static struct console pnx8xxx_console = { - .name = "ttyS", + .name = "ttySA", .write = pnx8xxx_console_write, .device = uart_console_device, .setup = pnx8xxx_console_setup, @@ -752,8 +752,8 @@ console_initcall(pnx8xxx_rs_console_init); static struct uart_driver pnx8xxx_reg = { .owner = THIS_MODULE, - .driver_name = "ttyS", - .dev_name = "ttyS", + .driver_name = "ttySA", + .dev_name = "ttySA", .major = SERIAL_PNX8XXX_MAJOR, .minor = MINOR_START, .nr = NR_PORTS, -- 1.5.6.3 From ihar.hrachyshka@gmail.com Wed Jan 14 14:35:47 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 14 Jan 2009 14:35:49 +0000 (GMT) Received: from rn-out-0910.google.com ([64.233.170.190]:34614 "EHLO rn-out-0910.google.com") by ftp.linux-mips.org with ESMTP id S21365069AbZANOfr (ORCPT ); Wed, 14 Jan 2009 14:35:47 +0000 Received: by rn-out-0910.google.com with SMTP id j66so535587rne.9 for ; Wed, 14 Jan 2009 06:35:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:subject:from:to:content-type :date:message-id:mime-version:x-mailer:content-transfer-encoding; bh=UojVWJGzYgmKKUnEMHR9vIk4l2ZrjmXP5MnljWHatKs=; b=r75e23UZJGALZgZDlVRSNfJtH/TNCLZx3MOmBUn9geDbco9miAK9WTnDSDgLrDm2QM 7m/Ujq2aYN8LmLIBmAhZBogd/o7ZJiWzHUoLn3kBEN/FOaWKA5P8cM5O90u6/uUAkjnd O5cmGV2sIJbRWvbHBGASugoiHqr3UOXch0svs= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=subject:from:to:content-type:date:message-id:mime-version:x-mailer :content-transfer-encoding; b=CZzb+fwcPwfnGdKIY+MCvV376KcAJSFVEl45tm2lF7Jumd8iSnODj1eFUp/msCA41H 1Zf61kucMKNqGyM0AZEgPn0CK+i27XP9fUTWs4TEpVg9BlWYN0dM5vRl0xnADIuAJTci TZi0SGFOCBi8dHSqQY7summgrgHbCYQGycp8c= Received: by 10.100.164.20 with SMTP id m20mr105936ane.121.1231943745524; Wed, 14 Jan 2009 06:35:45 -0800 (PST) Received: from ?10.6.11.31? (cpmsq.epam.com [217.21.56.2]) by mx.google.com with ESMTPS id c40sm9040412anc.16.2009.01.14.06.35.44 (version=SSLv3 cipher=RC4-MD5); Wed, 14 Jan 2009 06:35:44 -0800 (PST) Subject: [PATCH] Don't use ttyS* serial device name for board specific PNX8XXX UART serial From: Ihar Hrachyshka To: linux-mips@linux-mips.org Content-Type: text/plain Date: Wed, 14 Jan 2009 16:35:42 +0200 Message-Id: <1231943742.8457.6.camel@EPBYMINW0568> Mime-Version: 1.0 X-Mailer: Evolution 2.24.2 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21734 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ihar.hrachyshka@gmail.com Precedence: bulk X-list: linux-mips Content-Length: 1813 Lines: 63 I think that's a better solution for the problem I said so please commit this patch rather previous one... --- Don't use ttyS[0-1] serial device name for board specific PNX8XXX UART serial. Rather create ttyPNX[0-1]. Also changed minor number to be different with sa1100 serial driver one. Signed-off-by: Ihar Hrachyshka --- drivers/serial/pnx8xxx_uart.c | 11 +++++------ 1 files changed, 5 insertions(+), 6 deletions(-) diff --git a/drivers/serial/pnx8xxx_uart.c b/drivers/serial/pnx8xxx_uart.c index 22e30d2..96870f1 100644 --- a/drivers/serial/pnx8xxx_uart.c +++ b/drivers/serial/pnx8xxx_uart.c @@ -34,9 +34,8 @@ #include #include -/* We'll be using StrongARM sa1100 serial port major/minor */ #define SERIAL_PNX8XXX_MAJOR 204 -#define MINOR_START 5 +#define MINOR_START 96 #define NR_PORTS 2 @@ -636,7 +635,7 @@ static struct uart_ops pnx8xxx_pops = { /* * Setup the PNX8XXX serial ports. * - * Note also that we support "console=ttySx" where "x" is either 0 or 1. + * Note also that we support "console=ttyPNXx" where "x" is either 0 or 1. */ static void __init pnx8xxx_init_ports(void) { @@ -728,7 +727,7 @@ pnx8xxx_console_setup(struct console *co, char *options) static struct uart_driver pnx8xxx_reg; static struct console pnx8xxx_console = { - .name = "ttyS", + .name = "ttyPNX", .write = pnx8xxx_console_write, .device = uart_console_device, .setup = pnx8xxx_console_setup, @@ -752,8 +751,8 @@ console_initcall(pnx8xxx_rs_console_init); static struct uart_driver pnx8xxx_reg = { .owner = THIS_MODULE, - .driver_name = "ttyS", - .dev_name = "ttyS", + .driver_name = "ttyPNX", + .dev_name = "ttyPNX", .major = SERIAL_PNX8XXX_MAJOR, .minor = MINOR_START, .nr = NR_PORTS, -- 1.5.6.3 From David.Daney@caviumnetworks.com Wed Jan 14 17:31:20 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 14 Jan 2009 17:31:22 +0000 (GMT) Received: from mail3.caviumnetworks.com ([12.108.191.235]:31309 "EHLO mail3.caviumnetworks.com") by ftp.linux-mips.org with ESMTP id S21365776AbZANRbU (ORCPT ); Wed, 14 Jan 2009 17:31:20 +0000 Received: from exch4.caveonetworks.com (Not Verified[192.168.16.23]) by mail3.caviumnetworks.com with MailMarshal (v6,2,2,3503) id ; Wed, 14 Jan 2009 12:31:02 -0500 Received: from exch4.caveonetworks.com ([192.168.16.23]) by exch4.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Wed, 14 Jan 2009 09:30:52 -0800 Received: from dd1.caveonetworks.com ([64.169.86.201]) by exch4.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Wed, 14 Jan 2009 09:30:52 -0800 Message-ID: <496E214C.4090206@caviumnetworks.com> Date: Wed, 14 Jan 2009 09:30:52 -0800 From: David Daney User-Agent: Thunderbird 2.0.0.19 (X11/20090105) MIME-Version: 1.0 To: linux-mips@linux-mips.org Subject: Re: [PATCH] 8250: Initialize more fields in early_serial_setup. References: <1231879604-30140-1-git-send-email-ddaney@caviumnetworks.com> In-Reply-To: <1231879604-30140-1-git-send-email-ddaney@caviumnetworks.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 14 Jan 2009 17:30:52.0284 (UTC) FILETIME=[D91D03C0:01C9766D] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21735 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Content-Length: 945 Lines: 26 David Daney wrote: > The initial patch that initialized the fields individually omitted a > couple that evidently are required by mips/rb532. This should fix it. > > Signed-off-by: David Daney > --- > drivers/serial/8250.c | 2 ++ > 1 files changed, 2 insertions(+), 0 deletions(-) > > diff --git a/drivers/serial/8250.c b/drivers/serial/8250.c > index 1889a63..e2c3a85 100644 > --- a/drivers/serial/8250.c > +++ b/drivers/serial/8250.c > @@ -2837,6 +2837,8 @@ int __init early_serial_setup(struct uart_port *port) > p->regshift = port->regshift; > p->iotype = port->iotype; > p->flags = port->flags; > + p->type = port->type; > + p->line = port->line; > p->mapbase = port->mapbase; > p->private_data = port->private_data; > Some one got to this before I did. Linus already committed a substantially similar patch as 125c97d8a59888c5678734c2b70cbd08c847bd99 David Daney From f.fainelli@gmail.com Wed Jan 14 17:52:43 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 14 Jan 2009 17:52:46 +0000 (GMT) Received: from mail-bw0-f13.google.com ([209.85.218.13]:455 "EHLO mail-bw0-f13.google.com") by ftp.linux-mips.org with ESMTP id S21365086AbZANRwn convert rfc822-to-8bit (ORCPT ); Wed, 14 Jan 2009 17:52:43 +0000 Received: by bwz6 with SMTP id 6so1979178bwz.0 for ; Wed, 14 Jan 2009 09:52:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:sender:from:to:subject:date :user-agent:cc:references:in-reply-to:mime-version:content-type :content-transfer-encoding:content-disposition:message-id; bh=b24Tn7uxHsu4PkCmu4kjy+V6Jn4JnfB0fMTsfut/Yts=; b=aF/pXf+mZMxqetW/ZL3oxRAY2NfmOyimBly9CZMT3Bf8s7Vg8wnArxcW6yu+7Qz3hS foFu/QBZJ/DU465bNbca/4QlZcmBZCFZwZLf9Ib6fhM2ypVuQS2SVLXcgaXo3mfCp5r0 O0YK87JjF3Uw5zV63AZ5o8rvBtSzd2K6sqKb8= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:from:to:subject:date:user-agent:cc:references:in-reply-to :mime-version:content-type:content-transfer-encoding :content-disposition:message-id; b=a5T1uXk/s9UJOp3hEHse73/hBzf6EUat/W43+hja8+qMBunLt+6IvgoQwqgPauXAsb FAcp/GbR4yZtBKwGHCjLf6jne1eXkush3ryDlnuXDauU4Kd142rKRizpg25P6tzBU/rT S6ARJEgsIclzEHujZrx3vIP+utVftAC8cKMIE= Received: by 10.103.229.12 with SMTP id g12mr208623mur.16.1231955557223; Wed, 14 Jan 2009 09:52:37 -0800 (PST) Received: from ?157.159.15.69? ([157.159.15.69]) by mx.google.com with ESMTPS id s10sm61458664muh.7.2009.01.14.09.52.36 (version=TLSv1/SSLv3 cipher=RC4-MD5); Wed, 14 Jan 2009 09:52:36 -0800 (PST) From: Florian Fainelli To: Phil Sutter Subject: Re: [PATCH] MIPS: rb532: detect uart type, add platform device Date: Wed, 14 Jan 2009 18:52:20 +0100 User-Agent: KMail/1.9.9 Cc: Linux-Mips List , Ralf Baechle , David Daney References: <1231954029-13860-1-git-send-email-n0-1@freewrt.org> In-Reply-To: <1231954029-13860-1-git-send-email-n0-1@freewrt.org> MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-15" Content-Transfer-Encoding: 8BIT Content-Disposition: inline Message-Id: <200901141852.20918.florian@openwrt.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21736 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips Content-Length: 466 Lines: 18 Hi Phil, Le Wednesday 14 January 2009 18:27:09 Phil Sutter, vous avez écrit : > Auto-detection works just fine, so use it instead of specifying the type > manually. Also define a platform device for the uart, as suggested by > David Daney. Thanks ! > > Signed-off-by: Phil Sutter Acked-by: Florian Fainelli -- Best regards, Florian Fainelli Email : florian@openwrt.org http://openwrt.org ------------------------------- From f.fainelli@gmail.com Wed Jan 14 18:02:12 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 14 Jan 2009 18:02:14 +0000 (GMT) Received: from mail-bw0-f13.google.com ([209.85.218.13]:28147 "EHLO mail-bw0-f13.google.com") by ftp.linux-mips.org with ESMTP id S21365086AbZANSCM convert rfc822-to-8bit (ORCPT ); Wed, 14 Jan 2009 18:02:12 +0000 Received: by bwz6 with SMTP id 6so1993336bwz.0 for ; Wed, 14 Jan 2009 10:02:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:sender:from:to:subject:date :user-agent:cc:references:in-reply-to:mime-version:content-type :content-transfer-encoding:content-disposition:message-id; bh=jcAqcVa4JM82rzh1IRnKm7umuPY28E6ZgDtV4Kj2paA=; b=JeX+Cffo8P06OrckH0xc0YY22lOk8RVllf30ZpWbWr5Fsyz1Qy7CyPhjm5FSLDZrGC UsCpfqaeeNctZIEpXTQnQs69i8piV7G8iAujgCJWhfo4I1HgYUV3OSVsknwqlFSaCv9O 1lq/5NR/EruTms0kf6n5ORlm81N7iI3PuRWEA= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:from:to:subject:date:user-agent:cc:references:in-reply-to :mime-version:content-type:content-transfer-encoding :content-disposition:message-id; b=a/78NA6GHO6affA0BPwMRUIc3EvVTG7/IaNVyUGYmmwIvGgnZw+67oTACGrKRys12W YwvsSV/wa8BAv5B6O2pjurxtXvhKsGBdYV37j8r/8FK+BykNspx889BmZ22exijT3h4Z OCUhJwqt78EArtlMsUBCk5sF6VDjDJXwgSX+A= Received: by 10.103.172.9 with SMTP id z9mr214050muo.39.1231956124399; Wed, 14 Jan 2009 10:02:04 -0800 (PST) Received: from ?157.159.15.69? ([157.159.15.69]) by mx.google.com with ESMTPS id s10sm61475406muh.7.2009.01.14.10.02.02 (version=TLSv1/SSLv3 cipher=RC4-MD5); Wed, 14 Jan 2009 10:02:03 -0800 (PST) From: Florian Fainelli To: Phil Sutter Subject: Re: [PATCH] MIPS: rb532: use driver_data instead of platform_data Date: Wed, 14 Jan 2009 19:01:47 +0100 User-Agent: KMail/1.9.9 Cc: Linux-Mips List , jeff@garzik.org, ralf@linux-mips.org References: <20090112.215202.194850308.davem@davemloft.net> <1231954874-31245-1-git-send-email-n0-1@freewrt.org> In-Reply-To: <1231954874-31245-1-git-send-email-n0-1@freewrt.org> MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-15" Content-Transfer-Encoding: 8BIT Content-Disposition: inline Message-Id: <200901141901.47947.florian@openwrt.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21737 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips Content-Length: 477 Lines: 16 Le Wednesday 14 January 2009 18:41:14 Phil Sutter, vous avez écrit : > As the korina ethernet driver uses platform_get_drvdata() to extract the > driver specific data from the platform device, driver_data has to be > used here. Right, thanks for changing this. > > Signed-off-by: Phil Sutter Acked-by: Florian Fainelli -- Best regards, Florian Fainelli Email : florian@openwrt.org http://openwrt.org ------------------------------- From sshtylyov@ru.mvista.com Wed Jan 14 22:04:22 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 14 Jan 2009 22:04:24 +0000 (GMT) Received: from h155.mvista.com ([63.81.120.155]:10444 "EHLO imap.sh.mvista.com") by ftp.linux-mips.org with ESMTP id S21365088AbZANWEW (ORCPT ); Wed, 14 Jan 2009 22:04:22 +0000 Received: from [127.0.0.1] (unknown [10.150.0.9]) by imap.sh.mvista.com (Postfix) with ESMTP id 704F63ECB; Wed, 14 Jan 2009 14:04:18 -0800 (PST) Message-ID: <496E615E.9060006@ru.mvista.com> Date: Thu, 15 Jan 2009 01:04:14 +0300 From: Sergei Shtylyov User-Agent: Thunderbird 2.0.0.19 (Windows/20081209) MIME-Version: 1.0 To: Ihar Hrachyshka Cc: linux-mips@linux-mips.org Subject: Re: [PATCH] Don't use ttyS* serial device name for board specific PNX8XXX UART serial References: <1231943742.8457.6.camel@EPBYMINW0568> In-Reply-To: <1231943742.8457.6.camel@EPBYMINW0568> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21738 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sshtylyov@ru.mvista.com Precedence: bulk X-list: linux-mips Content-Length: 1282 Lines: 42 Hello. Ihar Hrachyshka wrote: > I think that's a better solution for the problem I said so please commit > this patch rather previous one... > Such comments are to be placed after --- tearline. Using several such tearlines makes it harder to apply your patch... And why do you expect the MIPS maintainer to commit a patch to the serial driver? Such patches should be addressed to linux-serial@vger.kernel.org and (most probably) Alan Cox... > --- > > Don't use ttyS[0-1] serial device name for board specific PNX8XXX UART > serial. Rather create ttyPNX[0-1]. Also changed minor number to be > different with sa1100 serial driver one. > > Signed-off-by: Ihar Hrachyshka > [...] > diff --git a/drivers/serial/pnx8xxx_uart.c b/drivers/serial/pnx8xxx_uart.c > index 22e30d2..96870f1 100644 > --- a/drivers/serial/pnx8xxx_uart.c > +++ b/drivers/serial/pnx8xxx_uart.c > @@ -34,9 +34,8 @@ > #include > #include > > -/* We'll be using StrongARM sa1100 serial port major/minor */ > #define SERIAL_PNX8XXX_MAJOR 204 > -#define MINOR_START 5 > +#define MINOR_START 96 > This major-minor pair is reserved for the Altix serial cards. Have you tried registering the minor on http://www.lanana.org WBR, Sergei From ihar.hrachyshka@gmail.com Wed Jan 14 22:20:33 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 14 Jan 2009 22:20:36 +0000 (GMT) Received: from yx-out-1718.google.com ([74.125.44.154]:7651 "EHLO yx-out-1718.google.com") by ftp.linux-mips.org with ESMTP id S21365088AbZANWUd (ORCPT ); Wed, 14 Jan 2009 22:20:33 +0000 Received: by yx-out-1718.google.com with SMTP id 36so310251yxh.24 for ; Wed, 14 Jan 2009 14:20:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:in-reply-to:references :date:message-id:subject:from:to:cc:content-type :content-transfer-encoding; bh=suHlho8mOWVv6b1X1SO9K9SqMQXTrAcYJbSCeNHQDYA=; b=nciNnATQ0NSYleHGRUVaTV1JJHXoQawls5U58XRWEhUXwm8hfJBJigEGdUHc71bjJu S0QS+ubKZZ7jriNj96mCjx1fjdcEoN8fBIAhqvCUU0V3+3TAgC8pB246Bj2B7gbHao4R Ru/HBevVySnYyJ7cngrPn9OHVWXSISFIDSlRQ= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type:content-transfer-encoding; b=tB9V4xq8OrgF0Qm1m37Wuk7YsxQwwh3tkoW6kq5BRcJOs0SMMrXFB91MJv/w31c07S IsU++Va2if/dFNzqhUyoC+jUaIn3YUvnnFIei7StEpDwPRmmOK06rx9aC5CAPHbMzwPy 1rSO0pcITPWgRoCuPOqNt0XqGvUJleBxi3JZU= MIME-Version: 1.0 Received: by 10.150.11.14 with SMTP id 14mr2679057ybk.101.1231971630835; Wed, 14 Jan 2009 14:20:30 -0800 (PST) In-Reply-To: <496E615E.9060006@ru.mvista.com> References: <1231943742.8457.6.camel@EPBYMINW0568> <496E615E.9060006@ru.mvista.com> Date: Thu, 15 Jan 2009 00:20:30 +0200 Message-ID: Subject: Re: [PATCH] Don't use ttyS* serial device name for board specific PNX8XXX UART serial From: Ihar Hrachyshka To: Sergei Shtylyov Cc: linux-mips@linux-mips.org Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21739 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ihar.hrachyshka@gmail.com Precedence: bulk X-list: linux-mips Content-Length: 1598 Lines: 54 On Thu, Jan 15, 2009 at 12:04 AM, Sergei Shtylyov wrote: > Hello. > > Ihar Hrachyshka wrote: >> >> I think that's a better solution for the problem I said so please commit >> this patch rather previous one... >> > > Such comments are to be placed after --- tearline. Using several such > tearlines makes it harder to apply your patch... > And why do you expect the MIPS maintainer to commit a patch to the serial > driver? Such patches should be addressed to linux-serial@vger.kernel.org and > (most probably) Alan Cox... I thought that if it's a driver for mips piece of hardware then I need to send it to mips guys. Ok, I'll send it to linux-serial. > >> --- >> >> Don't use ttyS[0-1] serial device name for board specific PNX8XXX UART >> serial. Rather create ttyPNX[0-1]. Also changed minor number to be >> different with sa1100 serial driver one. >> >> Signed-off-by: Ihar Hrachyshka >> > > [...] >> >> diff --git a/drivers/serial/pnx8xxx_uart.c b/drivers/serial/pnx8xxx_uart.c >> index 22e30d2..96870f1 100644 >> --- a/drivers/serial/pnx8xxx_uart.c >> +++ b/drivers/serial/pnx8xxx_uart.c >> @@ -34,9 +34,8 @@ >> #include >> #include >> -/* We'll be using StrongARM sa1100 serial port major/minor */ >> #define SERIAL_PNX8XXX_MAJOR 204 >> -#define MINOR_START 5 >> +#define MINOR_START 96 >> > > This major-minor pair is reserved for the Altix serial cards. Have you > tried registering the minor on http://www.lanana.org Thanks for info. I sent the request. > > WBR, Sergei > > > From weiyi.huang@gmail.com Wed Jan 14 22:56:51 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 14 Jan 2009 22:56:53 +0000 (GMT) Received: from ti-out-0910.google.com ([209.85.142.191]:26287 "EHLO ti-out-0910.google.com") by ftp.linux-mips.org with ESMTP id S21365777AbZANW4v (ORCPT ); Wed, 14 Jan 2009 22:56:51 +0000 Received: by ti-out-0910.google.com with SMTP id i7so483188tid.20 for ; Wed, 14 Jan 2009 14:56:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:date:from:to:subject:cc :message-id:mime-version:content-type:content-transfer-encoding :x-mailer; bh=k2Lk4p+p9meSzuDu7y5LHWNifGxTCTDpztqw1lW9Ed8=; b=kaXxTAmy6yoRzVy4ssPRIXIsVRV0LeHb0TlbL4F2QWrwv1WjK70CcLjFfXZt4NhyCv I5gUnsGmlnybCzrO4FFJPI7vAlJ48oDmFNI+KwlfCZmwed2aptKFTFQZpmDRCnkXic8s Y3ur9jIWHeq5Ki85JndHGecUHKQc1zVh7zJzU= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=date:from:to:subject:cc:message-id:mime-version:content-type :content-transfer-encoding:x-mailer; b=cSumFKc0drpdHRv4VYOMMQye0qHyTJDLssVPYZSXLTLRRNaMG+2M585Rap3epyTec5 MaMotntOMKNjiYqU/4g3vnf22nROk8MlBCoHuIqsDodsNdIbWm3QbbOCAcOSILe6xiyC 1W9Y37zT8QPVUAGoo1PhO9F3uL1d+ELlnKrXg= Received: by 10.110.28.15 with SMTP id b15mr724141tib.56.1231973805811; Wed, 14 Jan 2009 14:56:45 -0800 (PST) Received: from ?192.168.2.20? ([222.95.172.180]) by mx.google.com with ESMTPS id b4sm1970334tic.2.2009.01.14.14.56.43 (version=TLSv1/SSLv3 cipher=RC4-MD5); Wed, 14 Jan 2009 14:56:44 -0800 (PST) Date: Thu, 15 Jan 2009 06:56:46 +0800 From: Huang Weiyi To: ralf@linux-mips.org Subject: MIPS: remove duplicated #include's Cc: linux-mips@linux-mips.org Message-Id: <20090115065459.1F13.WEIYI.HUANG@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="US-ASCII" Content-Transfer-Encoding: 7bit X-Mailer: Becky! ver. 2.24.02 [en] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21740 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: weiyi.huang@gmail.com Precedence: bulk X-list: linux-mips Content-Length: 686 Lines: 24 Removed duplicated #include's in arch/mips/cavium-octeon/setup.c Signed-off-by: Huang Weiyi diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c index e085fed..5f4e49b 100644 --- a/arch/mips/cavium-octeon/setup.c +++ b/arch/mips/cavium-octeon/setup.c @@ -15,13 +15,11 @@ #include #include #include /* for memset */ -#include #include #include #include #include #include -#include #include #include From travis@sgi.com Wed Jan 14 23:44:11 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 14 Jan 2009 23:44:14 +0000 (GMT) Received: from relay1.sgi.com ([192.48.179.29]:1491 "EHLO relay.sgi.com") by ftp.linux-mips.org with ESMTP id S21365810AbZANXoL (ORCPT ); Wed, 14 Jan 2009 23:44:11 +0000 Received: from cthulhu.engr.sgi.com (cthulhu.engr.sgi.com [150.166.39.100]) by relay1.corp.sgi.com (Postfix) with ESMTP id 7332D8F8046; Wed, 14 Jan 2009 15:43:59 -0800 (PST) Received: from [134.15.31.35] (vpn-2-travis.corp.sgi.com [134.15.31.35]) by cthulhu.engr.sgi.com (8.12.10/8.12.10/SuSE Linux 0.7) with ESMTP id n0ENhtF5021029; Wed, 14 Jan 2009 15:43:55 -0800 Message-ID: <496E78BA.5040609@sgi.com> Date: Wed, 14 Jan 2009 15:43:54 -0800 From: Mike Travis User-Agent: Thunderbird 2.0.0.6 (X11/20070801) MIME-Version: 1.0 To: Ingo Molnar CC: Rusty Russell , Yinghai Lu , Thomas Gleixner , "H. Peter Anvin" , Tony Luck , IA64 , Ralf Baechle , linux-mips@linux-mips.org, David Howells , Koichi Yasutake , linux-am33-list@redhat.com, "David S. Miller" , SPARC , LKML Subject: Re: crash: IP: [] __bitmap_intersects+0x48/0x73 [PATCH supplied] References: <496BF6D5.9030403@sgi.com> <20090113130048.GB31147@elte.hu> <496CAF5A.3010304@sgi.com> <496D0F46.2010907@sgi.com> <496D2172.6030608@sgi.com> <20090114165431.GA18826@elte.hu> <20090114165524.GA21742@elte.hu> <20090114175126.GA21078@elte.hu> In-Reply-To: <20090114175126.GA21078@elte.hu> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21741 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: travis@sgi.com Precedence: bulk X-list: linux-mips Content-Length: 7784 Lines: 218 Ingo Molnar wrote: > also, with latest tip/master the ia64 cross-build still fails: > > /home/mingo/tip/arch/ia64/kernel/irq_ia64.c: In function `ia64_handle_irq': > /home/mingo/tip/arch/ia64/kernel/irq_ia64.c:498: error: structure has no member named `irqs' > /home/mingo/tip/arch/ia64/kernel/irq_ia64.c:500: error: structure has no member named `irqs' > /home/mingo/tip/arch/ia64/kernel/irq_ia64.c: In function `ia64_process_pending_intr': > /home/mingo/tip/arch/ia64/kernel/irq_ia64.c:556: error: structure has no member named `irqs' > /home/mingo/tip/arch/ia64/kernel/irq_ia64.c:558: error: structure has no member named `irqs' > make[2]: *** [arch/ia64/kernel/irq_ia64.o] Error 1 > make[2]: *** Waiting for unfinished jobs.... > > and so does the MIPS build: > > /home/mingo/tip/arch/mips/sgi-ip22/ip22-int.c: In function 'indy_buserror_irq': > /home/mingo/tip/arch/mips/sgi-ip22/ip22-int.c:158: error: 'struct kernel_stat' has no member named 'irqs' > make[2]: *** [arch/mips/sgi-ip22/ip22-int.o] Error 1 > make[2]: *** Waiting for unfinished jobs.... > /home/mingo/tip/arch/mips/sgi-ip22/ip22-time.c: In function 'indy_8254timer_irq': > /home/mingo/tip/arch/mips/sgi-ip22/ip22-time.c:125: error: 'struct kernel_stat' has no member named 'irqs' > make[2]: *** [arch/mips/sgi-ip22/ip22-time.o] Error 1 > make[1]: *** [arch/mips/sgi-ip22] Error 2 > make[1]: *** Waiting for unfinished jobs.... > > Ingo Hi Ingo, This appears to be a fallout of the sparse irqs changes. Here is a suggested patch. Btw, my ia64 build fails under tip/cpus4096 because this commit is not present: commit e65e49d0f3714f4a6a42f6f6a19926ba33fcda75 Author: Mike Travis Date: Mon Jan 12 15:27:13 2009 -0800 irq: update all arches for new irq_desc With that patch also applied, the defconfig for ia64 builds correctly. (Sorry, cannot test build the others right now.) Thanks, Mike --- Subject: irq: fix build errors referencing old kstat.irqs array Impact: fix build error Since the SPARSE IRQS changes redefined how the kstat irqs are organized, arch's must use the new accessor function: kstat_incr_irqs_this_cpu(irq, DESC); If CONFIG_SPARSE_IRQS is set, then DESC is a pointer to the irq_desc which has a pointer to the kstat_irqs. If not, then the .irqs field of struct kernel_stat is used instead. Signed-off-by: Mike Travis # IA64 Cc: Tony Luck Cc: # MIPS Cc: Ralf Baechle Cc: # MN10300 Cc: David Howells Cc: Koichi Yasutake Cc: # SPARC Cc: David S. Miller Cc: --- arch/ia64/kernel/irq_ia64.c | 12 ++++++++---- arch/mips/kernel/smtc.c | 4 +++- arch/mips/sgi-ip22/ip22-int.c | 2 +- arch/mips/sgi-ip22/ip22-time.c | 2 +- arch/mips/sibyte/bcm1480/smp.c | 3 ++- arch/mips/sibyte/sb1250/smp.c | 3 ++- arch/mn10300/kernel/mn10300-watchdog.c | 3 ++- arch/sparc/kernel/time_64.c | 2 +- 8 files changed, 20 insertions(+), 11 deletions(-) --- linux-2.6-for-ingo.orig/arch/ia64/kernel/irq_ia64.c +++ linux-2.6-for-ingo/arch/ia64/kernel/irq_ia64.c @@ -493,11 +493,13 @@ ia64_handle_irq (ia64_vector vector, str saved_tpr = ia64_getreg(_IA64_REG_CR_TPR); ia64_srlz_d(); while (vector != IA64_SPURIOUS_INT_VECTOR) { + struct irq_desc *desc = irq_to_desc(vector); + if (unlikely(IS_LOCAL_TLB_FLUSH(vector))) { smp_local_flush_tlb(); - kstat_this_cpu.irqs[vector]++; + kstat_incr_irqs_this_cpu(vector, desc); } else if (unlikely(IS_RESCHEDULE(vector))) - kstat_this_cpu.irqs[vector]++; + kstat_incr_irqs_this_cpu(vector, desc); else { int irq = local_vector_to_irq(vector); @@ -551,11 +553,13 @@ void ia64_process_pending_intr(void) * Perform normal interrupt style processing */ while (vector != IA64_SPURIOUS_INT_VECTOR) { + struct irq_desc *desc = irq_to_desc(vector); + if (unlikely(IS_LOCAL_TLB_FLUSH(vector))) { smp_local_flush_tlb(); - kstat_this_cpu.irqs[vector]++; + kstat_incr_irqs_this_cpu(vector, desc); } else if (unlikely(IS_RESCHEDULE(vector))) - kstat_this_cpu.irqs[vector]++; + kstat_incr_irqs_this_cpu(vector, desc); else { struct pt_regs *old_regs = set_irq_regs(NULL); int irq = local_vector_to_irq(vector); --- linux-2.6-for-ingo.orig/arch/mips/kernel/smtc.c +++ linux-2.6-for-ingo/arch/mips/kernel/smtc.c @@ -921,11 +921,13 @@ void ipi_decode(struct smtc_ipi *pipi) struct clock_event_device *cd; void *arg_copy = pipi->arg; int type_copy = pipi->type; + int irq = MIPS_CPU_IRQ_BASE + 1; + smtc_ipi_nq(&freeIPIq, pipi); switch (type_copy) { case SMTC_CLOCK_TICK: irq_enter(); - kstat_this_cpu.irqs[MIPS_CPU_IRQ_BASE + 1]++; + kstat_incr_irqs_this_cpu(irq, irq_to_desc(irq)); cd = &per_cpu(mips_clockevent_device, cpu); cd->event_handler(cd); irq_exit(); --- linux-2.6-for-ingo.orig/arch/mips/sgi-ip22/ip22-int.c +++ linux-2.6-for-ingo/arch/mips/sgi-ip22/ip22-int.c @@ -155,7 +155,7 @@ static void indy_buserror_irq(void) int irq = SGI_BUSERR_IRQ; irq_enter(); - kstat_this_cpu.irqs[irq]++; + kstat_incr_irqs_this_cpu(irq, irq_to_desc(irq)); ip22_be_interrupt(irq); irq_exit(); } --- linux-2.6-for-ingo.orig/arch/mips/sgi-ip22/ip22-time.c +++ linux-2.6-for-ingo/arch/mips/sgi-ip22/ip22-time.c @@ -122,7 +122,7 @@ void indy_8254timer_irq(void) char c; irq_enter(); - kstat_this_cpu.irqs[irq]++; + kstat_incr_irqs_this_cpu(irq, irq_to_desc(irq)); printk(KERN_ALERT "Oops, got 8254 interrupt.\n"); ArcRead(0, &c, 1, &cnt); ArcEnterInteractiveMode(); --- linux-2.6-for-ingo.orig/arch/mips/sibyte/bcm1480/smp.c +++ linux-2.6-for-ingo/arch/mips/sibyte/bcm1480/smp.c @@ -178,9 +178,10 @@ struct plat_smp_ops bcm1480_smp_ops = { void bcm1480_mailbox_interrupt(void) { int cpu = smp_processor_id(); + int irq = K_BCM1480_INT_MBOX_0_0; unsigned int action; - kstat_this_cpu.irqs[K_BCM1480_INT_MBOX_0_0]++; + kstat_incr_irqs_this_cpu(irq, irq_to_desc(irq)); /* Load the mailbox register to figure out what we're supposed to do */ action = (__raw_readq(mailbox_0_regs[cpu]) >> 48) & 0xffff; --- linux-2.6-for-ingo.orig/arch/mips/sibyte/sb1250/smp.c +++ linux-2.6-for-ingo/arch/mips/sibyte/sb1250/smp.c @@ -166,9 +166,10 @@ struct plat_smp_ops sb_smp_ops = { void sb1250_mailbox_interrupt(void) { int cpu = smp_processor_id(); + int irq = K_INT_MBOX_0; unsigned int action; - kstat_this_cpu.irqs[K_INT_MBOX_0]++; + kstat_incr_irqs_this_cpu(irq, irq_to_desc(irq)); /* Load the mailbox register to figure out what we're supposed to do */ action = (____raw_readq(mailbox_regs[cpu]) >> 48) & 0xffff; --- linux-2.6-for-ingo.orig/arch/mn10300/kernel/mn10300-watchdog.c +++ linux-2.6-for-ingo/arch/mn10300/kernel/mn10300-watchdog.c @@ -130,6 +130,7 @@ void watchdog_interrupt(struct pt_regs * * the stack NMI-atomically, it's safe to use smp_processor_id(). */ int sum, cpu = smp_processor_id(); + int irq = NMIIRQ; u8 wdt, tmp; wdt = WDCTR & ~WDCTR_WDCNE; @@ -138,7 +139,7 @@ void watchdog_interrupt(struct pt_regs * NMICR = NMICR_WDIF; nmi_count(cpu)++; - kstat_this_cpu.irqs[NMIIRQ]++; + kstat_incr_irqs_this_cpu(irq, irq_to_desc(irq)); sum = irq_stat[cpu].__irq_count; if (last_irq_sums[cpu] == sum) { --- linux-2.6-for-ingo.orig/arch/sparc/kernel/time_64.c +++ linux-2.6-for-ingo/arch/sparc/kernel/time_64.c @@ -727,7 +727,7 @@ void timer_interrupt(int irq, struct pt_ irq_enter(); - kstat_this_cpu.irqs[0]++; + kstat_incr_irqs_this_cpu(0, irq_to_desc(0)); if (unlikely(!evt->event_handler)) { printk(KERN_WARNING From ralf@h5.dl5rb.org.uk Thu Jan 15 00:06:28 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 15 Jan 2009 00:06:31 +0000 (GMT) Received: from h5.dl5rb.org.uk ([81.2.74.5]:43240 "EHLO h5.dl5rb.org.uk") by ftp.linux-mips.org with ESMTP id S21365813AbZAOAG2 (ORCPT ); Thu, 15 Jan 2009 00:06:28 +0000 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id n0F06QUR004162; Thu, 15 Jan 2009 00:06:27 GMT Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id n0F06PgS004160; Thu, 15 Jan 2009 00:06:25 GMT Date: Thu, 15 Jan 2009 00:06:25 +0000 From: Ralf Baechle To: Huang Weiyi Cc: linux-mips@linux-mips.org Subject: Re: MIPS: remove duplicated #include's Message-ID: <20090115000625.GA4140@linux-mips.org> References: <20090115065459.1F13.WEIYI.HUANG@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20090115065459.1F13.WEIYI.HUANG@gmail.com> User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21742 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Content-Length: 283 Lines: 11 On Thu, Jan 15, 2009 at 06:56:46AM +0800, Huang Weiyi wrote: > Removed duplicated #include's in > arch/mips/cavium-octeon/setup.c > > Signed-off-by: Huang Weiyi Applied after fixing the rejects caused by your whitespace mangling mail client ... Ralf From mingo@elte.hu Thu Jan 15 10:15:04 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 15 Jan 2009 10:15:08 +0000 (GMT) Received: from mx2.mail.elte.hu ([157.181.151.9]:36306 "EHLO mx2.mail.elte.hu") by ftp.linux-mips.org with ESMTP id S21103583AbZAOKPE (ORCPT ); Thu, 15 Jan 2009 10:15:04 +0000 Received: from elvis.elte.hu ([157.181.1.14]) by mx2.mail.elte.hu with esmtp (Exim) id 1LNPFB-0006bA-2n from ; Thu, 15 Jan 2009 11:14:39 +0100 Received: by elvis.elte.hu (Postfix, from userid 1004) id 4256B3E21AA; Thu, 15 Jan 2009 11:14:27 +0100 (CET) Date: Thu, 15 Jan 2009 11:14:28 +0100 From: Ingo Molnar To: Mike Travis Cc: Rusty Russell , Yinghai Lu , Thomas Gleixner , "H. Peter Anvin" , Tony Luck , IA64 , Ralf Baechle , linux-mips@linux-mips.org, David Howells , Koichi Yasutake , linux-am33-list@redhat.com, "David S. Miller" , SPARC , LKML Subject: Re: crash: IP: [] __bitmap_intersects+0x48/0x73 [PATCH supplied] Message-ID: <20090115101428.GG5833@elte.hu> References: <496BF6D5.9030403@sgi.com> <20090113130048.GB31147@elte.hu> <496CAF5A.3010304@sgi.com> <496D0F46.2010907@sgi.com> <496D2172.6030608@sgi.com> <20090114165431.GA18826@elte.hu> <20090114165524.GA21742@elte.hu> <20090114175126.GA21078@elte.hu> <496E78BA.5040609@sgi.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <496E78BA.5040609@sgi.com> User-Agent: Mutt/1.5.18 (2008-05-17) Received-SPF: neutral (mx2: 157.181.1.14 is neither permitted nor denied by domain of elte.hu) client-ip=157.181.1.14; envelope-from=mingo@elte.hu; helo=elvis.elte.hu; X-ELTE-VirusStatus: clean X-ELTE-SpamScore: -1.5 X-ELTE-SpamLevel: X-ELTE-SpamCheck: no X-ELTE-SpamVersion: ELTE 2.0 X-ELTE-SpamCheck-Details: score=-1.5 required=5.9 tests=BAYES_00 autolearn=no SpamAssassin version=3.2.3 -1.5 BAYES_00 BODY: Bayesian spam probability is 0 to 1% [score: 0.0000] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21743 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mingo@elte.hu Precedence: bulk X-list: linux-mips Content-Length: 2003 Lines: 49 * Mike Travis wrote: > Ingo Molnar wrote: > > also, with latest tip/master the ia64 cross-build still fails: > > > > /home/mingo/tip/arch/ia64/kernel/irq_ia64.c: In function `ia64_handle_irq': > > /home/mingo/tip/arch/ia64/kernel/irq_ia64.c:498: error: structure has no member named `irqs' > > /home/mingo/tip/arch/ia64/kernel/irq_ia64.c:500: error: structure has no member named `irqs' > > /home/mingo/tip/arch/ia64/kernel/irq_ia64.c: In function `ia64_process_pending_intr': > > /home/mingo/tip/arch/ia64/kernel/irq_ia64.c:556: error: structure has no member named `irqs' > > /home/mingo/tip/arch/ia64/kernel/irq_ia64.c:558: error: structure has no member named `irqs' > > make[2]: *** [arch/ia64/kernel/irq_ia64.o] Error 1 > > make[2]: *** Waiting for unfinished jobs.... > > > > and so does the MIPS build: > > > > /home/mingo/tip/arch/mips/sgi-ip22/ip22-int.c: In function 'indy_buserror_irq': > > /home/mingo/tip/arch/mips/sgi-ip22/ip22-int.c:158: error: 'struct kernel_stat' has no member named 'irqs' > > make[2]: *** [arch/mips/sgi-ip22/ip22-int.o] Error 1 > > make[2]: *** Waiting for unfinished jobs.... > > /home/mingo/tip/arch/mips/sgi-ip22/ip22-time.c: In function 'indy_8254timer_irq': > > /home/mingo/tip/arch/mips/sgi-ip22/ip22-time.c:125: error: 'struct kernel_stat' has no member named 'irqs' > > make[2]: *** [arch/mips/sgi-ip22/ip22-time.o] Error 1 > > make[1]: *** [arch/mips/sgi-ip22] Error 2 > > make[1]: *** Waiting for unfinished jobs.... > > > > Ingo > > Hi Ingo, > > This appears to be a fallout of the sparse irqs changes. Here is a > suggested patch. > > Btw, my ia64 build fails under tip/cpus4096 because this commit is not > present: > > commit e65e49d0f3714f4a6a42f6f6a19926ba33fcda75 > Author: Mike Travis > Date: Mon Jan 12 15:27:13 2009 -0800 > > irq: update all arches for new irq_desc it is present: [mingo@hera tip]$ git log cpus4096 | grep e65e49d commit e65e49d0f3714f4a6a42f6f6a19926ba33fcda75 Ingo From mingo@elte.hu Thu Jan 15 10:16:32 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 15 Jan 2009 10:16:35 +0000 (GMT) Received: from mx2.mail.elte.hu ([157.181.151.9]:15829 "EHLO mx2.mail.elte.hu") by ftp.linux-mips.org with ESMTP id S21103656AbZAOKQc (ORCPT ); Thu, 15 Jan 2009 10:16:32 +0000 Received: from elvis.elte.hu ([157.181.1.14]) by mx2.mail.elte.hu with esmtp (Exim) id 1LNPGu-00077H-4u from ; Thu, 15 Jan 2009 11:16:22 +0100 Received: by elvis.elte.hu (Postfix, from userid 1004) id A07F33E21AA; Thu, 15 Jan 2009 11:16:15 +0100 (CET) Date: Thu, 15 Jan 2009 11:16:17 +0100 From: Ingo Molnar To: Mike Travis Cc: Rusty Russell , Yinghai Lu , Thomas Gleixner , "H. Peter Anvin" , Tony Luck , IA64 , Ralf Baechle , linux-mips@linux-mips.org, David Howells , Koichi Yasutake , linux-am33-list@redhat.com, "David S. Miller" , SPARC , LKML Subject: Re: crash: IP: [] __bitmap_intersects+0x48/0x73 [PATCH supplied] Message-ID: <20090115101617.GH5833@elte.hu> References: <496BF6D5.9030403@sgi.com> <20090113130048.GB31147@elte.hu> <496CAF5A.3010304@sgi.com> <496D0F46.2010907@sgi.com> <496D2172.6030608@sgi.com> <20090114165431.GA18826@elte.hu> <20090114165524.GA21742@elte.hu> <20090114175126.GA21078@elte.hu> <496E78BA.5040609@sgi.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <496E78BA.5040609@sgi.com> User-Agent: Mutt/1.5.18 (2008-05-17) Received-SPF: neutral (mx2: 157.181.1.14 is neither permitted nor denied by domain of elte.hu) client-ip=157.181.1.14; envelope-from=mingo@elte.hu; helo=elvis.elte.hu; X-ELTE-VirusStatus: clean X-ELTE-SpamScore: 1.0 X-ELTE-SpamLevel: s X-ELTE-SpamCheck: no X-ELTE-SpamVersion: ELTE 2.0 X-ELTE-SpamCheck-Details: score=1.0 required=5.9 tests=BAYES_50 autolearn=no SpamAssassin version=3.2.3 1.0 BAYES_50 BODY: Bayesian spam probability is 40 to 60% [score: 0.4106] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21744 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mingo@elte.hu Precedence: bulk X-list: linux-mips Content-Length: 166 Lines: 8 * Mike Travis wrote: > Subject: irq: fix build errors referencing old kstat.irqs array i've picked this up into tip/cpus4096, thanks Mike, Ingo From mingo@elte.hu Thu Jan 15 12:22:37 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 15 Jan 2009 12:22:39 +0000 (GMT) Received: from mx2.mail.elte.hu ([157.181.151.9]:42437 "EHLO mx2.mail.elte.hu") by ftp.linux-mips.org with ESMTP id S21365922AbZAOMWh (ORCPT ); Thu, 15 Jan 2009 12:22:37 +0000 Received: from elvis.elte.hu ([157.181.1.14]) by mx2.mail.elte.hu with esmtp (Exim) id 1LNREW-0004TW-IT from ; Thu, 15 Jan 2009 13:22:03 +0100 Received: by elvis.elte.hu (Postfix, from userid 1004) id AD5D53E21AA; Thu, 15 Jan 2009 13:21:57 +0100 (CET) Date: Thu, 15 Jan 2009 13:21:56 +0100 From: Ingo Molnar To: Mike Travis Cc: Rusty Russell , Yinghai Lu , Thomas Gleixner , "H. Peter Anvin" , Tony Luck , IA64 , Ralf Baechle , linux-mips@linux-mips.org, David Howells , Koichi Yasutake , linux-am33-list@redhat.com, "David S. Miller" , SPARC , LKML Subject: Re: crash: IP: [] __bitmap_intersects+0x48/0x73 [PATCH supplied] Message-ID: <20090115122156.GA20349@elte.hu> References: <496BF6D5.9030403@sgi.com> <20090113130048.GB31147@elte.hu> <496CAF5A.3010304@sgi.com> <496D0F46.2010907@sgi.com> <496D2172.6030608@sgi.com> <20090114165431.GA18826@elte.hu> <20090114165524.GA21742@elte.hu> <20090114175126.GA21078@elte.hu> <496E78BA.5040609@sgi.com> <20090115101617.GH5833@elte.hu> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20090115101617.GH5833@elte.hu> User-Agent: Mutt/1.5.18 (2008-05-17) Received-SPF: neutral (mx2: 157.181.1.14 is neither permitted nor denied by domain of elte.hu) client-ip=157.181.1.14; envelope-from=mingo@elte.hu; helo=elvis.elte.hu; X-ELTE-VirusStatus: clean X-ELTE-SpamScore: 0.5 X-ELTE-SpamLevel: X-ELTE-SpamCheck: no X-ELTE-SpamVersion: ELTE 2.0 X-ELTE-SpamCheck-Details: score=0.5 required=5.9 tests=BAYES_40 autolearn=no SpamAssassin version=3.2.3 0.5 BAYES_40 BODY: Bayesian spam probability is 20 to 40% [score: 0.3119] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21745 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mingo@elte.hu Precedence: bulk X-list: linux-mips Content-Length: 394 Lines: 11 FYI, there's new warnings due to cpumask changes: arch/x86/kernel/cpu/intel_cacheinfo.c: In function ‘show_cache_disable’: arch/x86/kernel/cpu/intel_cacheinfo.c:710: warning: unused variable ‘mask’ arch/x86/kernel/cpu/intel_cacheinfo.c: In function ‘store_cache_disable’: arch/x86/kernel/cpu/intel_cacheinfo.c:745: warning: unused variable ‘mask’ on 32-bit defconfig. Ingo From anemo@mba.ocn.ne.jp Thu Jan 15 14:25:15 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 15 Jan 2009 14:25:17 +0000 (GMT) Received: from mba.ocn.ne.jp ([122.1.235.107]:10438 "HELO smtp.mba.ocn.ne.jp") by ftp.linux-mips.org with SMTP id S21365139AbZAOOZP (ORCPT ); Thu, 15 Jan 2009 14:25:15 +0000 Received: from localhost (p8187-ipad206funabasi.chiba.ocn.ne.jp [222.145.82.187]) by smtp.mba.ocn.ne.jp (Postfix) with ESMTP id 542809DD8; Thu, 15 Jan 2009 23:25:09 +0900 (JST) Date: Thu, 15 Jan 2009 23:25:10 +0900 (JST) Message-Id: <20090115.232510.65192869.anemo@mba.ocn.ne.jp> To: ddaney@caviumnetworks.com Cc: linux-mips@linux-mips.org, tpaoletti@caviumnetworks.com Subject: Re: [PATCH 20/20] MIPS: Add Cavium OCTEON to arch/mips/Kconfig From: Atsushi Nemoto In-Reply-To: <1229038418-31833-20-git-send-email-ddaney@caviumnetworks.com> References: <4941A2F5.1010202@caviumnetworks.com> <1229038418-31833-20-git-send-email-ddaney@caviumnetworks.com> X-Fingerprint: 6ACA 1623 39BD 9A94 9B1A B746 CA77 FE94 2874 D52F X-Pgp-Public-Key: http://wwwkeys.pgp.net/pks/lookup?op=get&search=0x2874D52F X-Mailer: Mew version 5.2 on Emacs 21.4 / Mule 5.0 (SAKAKI) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21746 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anemo@mba.ocn.ne.jp Precedence: bulk X-list: linux-mips Content-Length: 998 Lines: 28 On Thu, 11 Dec 2008 15:33:38 -0800, David Daney wrote: > --- a/arch/mips/Kconfig > +++ b/arch/mips/Kconfig > @@ -595,6 +595,44 @@ config WR_PPMC > This enables support for the Wind River MIPS32 4KC PPMC evaluation > board, which is based on GT64120 bridge chip. > > +config CAVIUM_OCTEON_SIMULATOR > + bool "Support for the Cavium Networks Octeon Simulator" > + select CEVT_R4K > + select 64BIT_PHYS_ADDR > + select DMA_COHERENT > + select SYS_SUPPORTS_64BIT_KERNEL > + select SYS_SUPPORTS_BIG_ENDIAN > + select SYS_SUPPORTS_HIGHMEM > + select CPU_CAVIUM_OCTEON > + help > + The Octeon simulator is software performance model of the Cavium > + Octeon Processor. It supports simulating Octeon processors on x86 > + hardware. All other board entries use SYS_HAS_CPU_XXXX intermediate variable to select CPU. Please defined SYS_HAS_CPU_CAVIUM_OCTEON and use it. Othersize every other board configs will be asked for CPU_CAVIUM_OCTEON. --- Atsushi Nemoto From n0-1@nwl.cc Thu Jan 15 14:38:51 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 15 Jan 2009 14:38:54 +0000 (GMT) Received: from orbit.nwl.cc ([91.121.169.95]:24014 "EHLO mail.nwl.cc") by ftp.linux-mips.org with ESMTP id S21365139AbZAOOiv (ORCPT ); Thu, 15 Jan 2009 14:38:51 +0000 Received: from base (localhost [127.0.0.1]) by mail.nwl.cc (Postfix) with ESMTP id 5F0CF4043837; Thu, 15 Jan 2009 15:38:46 +0100 (CET) From: Phil Sutter To: Linux-Mips List Cc: florian@openwrt.org, ralf@linux-mips.org, ddaney@caviumnetworks.com Subject: [PATCH] MIPS: rb532: detect uart type, add platform device Date: Thu, 15 Jan 2009 15:38:38 +0100 X-Mailer: git-send-email 1.5.6.4 Message-Id: <20090115143846.5F0CF4043837@mail.nwl.cc> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21747 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: n0-1@freewrt.org Precedence: bulk X-list: linux-mips Content-Length: 2321 Lines: 90 Auto-detection works just fine, so use it instead of specifying the type manually. Also define a platform device for the uart, as suggested by David Daney. Signed-off-by: Phil Sutter --- arch/mips/rb532/devices.c | 26 ++++++++++++++++++++++++++ arch/mips/rb532/serial.c | 2 +- 2 files changed, 27 insertions(+), 1 deletions(-) diff --git a/arch/mips/rb532/devices.c b/arch/mips/rb532/devices.c index c1c2918..9b6b744 100644 --- a/arch/mips/rb532/devices.c +++ b/arch/mips/rb532/devices.c @@ -24,6 +24,7 @@ #include #include #include +#include #include @@ -39,6 +40,8 @@ #define ETH0_RX_DMA_ADDR (DMA0_BASE_ADDR + 0 * DMA_CHAN_OFFSET) #define ETH0_TX_DMA_ADDR (DMA0_BASE_ADDR + 1 * DMA_CHAN_OFFSET) +extern unsigned int idt_cpu_freq; + static struct resource korina_dev0_res[] = { { .name = "korina_regs", @@ -214,12 +217,32 @@ static struct platform_device rb532_wdt = { .num_resources = ARRAY_SIZE(rb532_wdt_res), }; +static struct plat_serial8250_port rb532_uart_res[] = { + { + .membase = (char *)KSEG1ADDR(REGBASE + UART0BASE), + .irq = UART0_IRQ, + .regshift = 2, + .iotype = UPIO_MEM, + .flags = UPF_BOOT_AUTOCONF, + }, + { + .flags = 0, + } +}; + +static struct platform_device rb532_uart = { + .name = "serial8250", + .id = PLAT8250_DEV_PLATFORM, + .dev.platform_data = &rb532_uart_res, +}; + static struct platform_device *rb532_devs[] = { &korina_dev0, &nand_slot0, &cf_slot0, &rb532_led, &rb532_button, + &rb532_uart, &rb532_wdt }; @@ -294,6 +317,9 @@ static int __init plat_setup_devices(void) /* Initialise the NAND device */ rb532_nand_setup(); + /* set the uart clock to the current cpu frequency */ + rb532_uart_res[0].uartclk = idt_cpu_freq; + return platform_add_devices(rb532_devs, ARRAY_SIZE(rb532_devs)); } diff --git a/arch/mips/rb532/serial.c b/arch/mips/rb532/serial.c index 3e0d7ec..00ed19f 100644 --- a/arch/mips/rb532/serial.c +++ b/arch/mips/rb532/serial.c @@ -36,7 +36,7 @@ extern unsigned int idt_cpu_freq; static struct uart_port rb532_uart = { - .type = PORT_16550A, + .flags = UPF_BOOT_AUTOCONF, .line = 0, .irq = UART0_IRQ, .iotype = UPIO_MEM, -- 1.5.6.4 From n0-1@nwl.cc Thu Jan 15 14:41:57 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 15 Jan 2009 14:41:59 +0000 (GMT) Received: from orbit.nwl.cc ([91.121.169.95]:27086 "EHLO mail.nwl.cc") by ftp.linux-mips.org with ESMTP id S21365931AbZAOOl5 (ORCPT ); Thu, 15 Jan 2009 14:41:57 +0000 Received: from base (localhost [127.0.0.1]) by mail.nwl.cc (Postfix) with ESMTP id 98F404043831; Thu, 15 Jan 2009 15:41:51 +0100 (CET) From: Phil Sutter To: Linux-Mips List Cc: florian@openwrt.org, ralf@linux-mips.org, jeff@garzik.org Subject: [PATCH] MIPS: rb532: use driver_data instead of platform_data Date: Thu, 15 Jan 2009 15:41:44 +0100 X-Mailer: git-send-email 1.5.6.4 In-Reply-To: <20090112.215202.194850308.davem@davemloft.net> References: <20090112.215202.194850308.davem@davemloft.net> Message-Id: <20090115144151.98F404043831@mail.nwl.cc> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21748 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: n0-1@freewrt.org Precedence: bulk X-list: linux-mips Content-Length: 777 Lines: 25 As the korina ethernet driver uses platform_get_drvdata() to extract the driver specific data from the platform device, driver_data has to be used here. Signed-off-by: Phil Sutter --- arch/mips/rb532/devices.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/mips/rb532/devices.c b/arch/mips/rb532/devices.c index 9b6b744..3c74561 100644 --- a/arch/mips/rb532/devices.c +++ b/arch/mips/rb532/devices.c @@ -89,7 +89,7 @@ static struct korina_device korina_dev0_data = { static struct platform_device korina_dev0 = { .id = -1, .name = "korina", - .dev.platform_data = &korina_dev0_data, + .dev.driver_data = &korina_dev0_data, .resource = korina_dev0_res, .num_resources = ARRAY_SIZE(korina_dev0_res), }; -- 1.5.6.4 From f.fainelli@gmail.com Thu Jan 15 15:46:56 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 15 Jan 2009 15:46:59 +0000 (GMT) Received: from fg-out-1718.google.com ([72.14.220.158]:17128 "EHLO fg-out-1718.google.com") by ftp.linux-mips.org with ESMTP id S21365163AbZAOPq4 (ORCPT ); Thu, 15 Jan 2009 15:46:56 +0000 Received: by fg-out-1718.google.com with SMTP id d23so551447fga.32 for ; Thu, 15 Jan 2009 07:46:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:sender:from:date:subject :mime-version:x-uid:x-length:to:content-type :content-transfer-encoding:content-disposition:message-id; bh=wsShpYo4XmtV9Manx+3ZZdJpGX/4L46HA8/J1ulhCxc=; b=hppTXskPwT3gAaq0LyvedtSwiPtBBOyFfQTz/OjNdKwQA4Q3Tn4L3VfaW4VgtHOEiK g788Zyz2Ia3TlNMPz50GSgDjpUrriA7o1NLJ/YxLgDf3VxdxY/4RkkNG1Xj/7DaNKHqJ a6D1VxIqQZluv1zL/+9ATgiy97lvu03B4z0Qs= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:from:date:subject:mime-version:x-uid:x-length:to :content-type:content-transfer-encoding:content-disposition :message-id; b=BfeeV12ImzbwAONca0pIkqr/p1V7xig28Ww1qjFB2tCaBLLFDGEzNT6Wixo42+gtrS cyofucAGQov+TGxjzpUR0GbmyAXxsIbruD61N7NH/Z2xITJMn9oLkZQ1Dw+FkONjib7g 8I+UplORr6Yj+i+vGwGS3qC8fuSTGEQWwNPJI= Received: by 10.103.224.17 with SMTP id b17mr726150mur.61.1232034414664; Thu, 15 Jan 2009 07:46:54 -0800 (PST) Received: from ?192.168.2.188? (lab.openpattern.org [82.240.16.241]) by mx.google.com with ESMTPS id j2sm92879mue.5.2009.01.15.07.46.51 (version=TLSv1/SSLv3 cipher=RC4-MD5); Thu, 15 Jan 2009 07:46:53 -0800 (PST) From: Florian Fainelli Date: Thu, 15 Jan 2009 16:46:48 +0100 Subject: [PATCH] au1000: convert to using gpiolib MIME-Version: 1.0 X-UID: 50 X-Length: 11115 To: ralf@linux-mips.org, Manuel Lauss , Linux-MIPS Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Content-Disposition: inline Message-Id: <200901151646.49591.florian@openwrt.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21749 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips Content-Length: 9859 Lines: 361 This patch converts the GPIO board code to use gpiolib. Signed-off-by: Florian Fainelli --- diff --git a/arch/mips/alchemy/Kconfig b/arch/mips/alchemy/Kconfig index 7f8ef13..2fc5c13 100644 --- a/arch/mips/alchemy/Kconfig +++ b/arch/mips/alchemy/Kconfig @@ -135,3 +135,4 @@ config SOC_AU1X00 select SYS_SUPPORTS_32BIT_KERNEL select SYS_SUPPORTS_APM_EMULATION select GENERIC_HARDIRQS_NO__DO_IRQ + select ARCH_REQUIRE_GPIOLIB diff --git a/arch/mips/alchemy/common/gpio.c b/arch/mips/alchemy/common/gpio.c index e660ddd..46be37b 100644 --- a/arch/mips/alchemy/common/gpio.c +++ b/arch/mips/alchemy/common/gpio.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2007, OpenWrt.org, Florian Fainelli + * Copyright (C) 2007-2009, OpenWrt.org, Florian Fainelli * Architecture specific GPIO support * * This program is free software; you can redistribute it and/or modify it @@ -27,122 +27,175 @@ * others have a second one : GPIO2 */ +#include #include +#include +#include +#include #include #include -#define gpio1 sys -#if !defined(CONFIG_SOC_AU1000) - -static struct au1x00_gpio2 *const gpio2 = (struct au1x00_gpio2 *) GPIO2_BASE; -#define GPIO2_OUTPUT_ENABLE_MASK 0x00010000 +struct au1000_gpio_chip { + struct gpio_chip chip; + void __iomem *regbase; +}; -static int au1xxx_gpio2_read(unsigned gpio) +#if !defined(CONFIG_SOC_AU1000) +static int au1000_gpio2_get(struct gpio_chip *chip, unsigned offset) { - gpio -= AU1XXX_GPIO_BASE; - return ((gpio2->pinstate >> gpio) & 0x01); + u32 mask = 1 << offset; + struct au1000_gpio_chip *gpch; + + gpch = container_of(chip, struct au1000_gpio_chip, chip); + return readl(gpch->regbase + AU1000_GPIO2_ST) & mask; } -static void au1xxx_gpio2_write(unsigned gpio, int value) +static void au1000_gpio2_set(struct gpio_chip *chip, + unsigned offset, int value) { - gpio -= AU1XXX_GPIO_BASE; + u32 mask = ((GPIO2_OUT_EN_MASK << offset) | (!!value << offset)); + struct au1000_gpio_chip *gpch; + unsigned long flags; + + gpch = container_of(chip, struct au1000_gpio_chip, chip); - gpio2->output = (GPIO2_OUTPUT_ENABLE_MASK << gpio) | ((!!value) << gpio); + local_irq_save(flags); + writel(mask, gpch->regbase + AU1000_GPIO2_OUT); + local_irq_restore(flags); } -static int au1xxx_gpio2_direction_input(unsigned gpio) +static int au1000_gpio2_direction_input(struct gpio_chip *chip, unsigned offset) { - gpio -= AU1XXX_GPIO_BASE; - gpio2->dir &= ~(0x01 << gpio); + u32 mask = 1 << offset; + u32 tmp; + struct au1000_gpio_chip *gpch; + unsigned long flags; + + gpch = container_of(chip, struct au1000_gpio_chip, chip); + + local_irq_save(flags); + tmp = readl(gpch->regbase + AU1000_GPIO2_DIR); + tmp &= ~mask; + writel(tmp, gpch->regbase + AU1000_GPIO2_DIR); + local_irq_restore(flags); + return 0; } -static int au1xxx_gpio2_direction_output(unsigned gpio, int value) +static int au1000_gpio2_direction_output(struct gpio_chip *chip, + unsigned offset, int value) { - gpio -= AU1XXX_GPIO_BASE; - gpio2->dir |= 0x01 << gpio; - gpio2->output = (GPIO2_OUTPUT_ENABLE_MASK << gpio) | ((!!value) << gpio); + u32 mask = 1 << offset; + u32 out_mask = ((GPIO2_OUT_EN_MASK << offset) | (!!value << offset)); + u32 tmp; + struct au1000_gpio_chip *gpch; + unsigned long flags; + + gpch = container_of(chip, struct au1000_gpio_chip, chip); + + local_irq_save(flags); + tmp = readl(gpch->regbase + AU1000_GPIO2_DIR); + tmp |= mask; + writel(tmp, gpch->regbase + AU1000_GPIO2_DIR); + writel(out_mask, gpch->regbase + AU1000_GPIO2_OUT); + local_irq_restore(flags); + return 0; } - #endif /* !defined(CONFIG_SOC_AU1000) */ -static int au1xxx_gpio1_read(unsigned gpio) +static int au1000_gpio1_get(struct gpio_chip *chip, unsigned offset) { - return (gpio1->pinstaterd >> gpio) & 0x01; + u32 mask = 1 << offset; + struct au1000_gpio_chip *gpch; + + gpch = container_of(chip, struct au1000_gpio_chip, chip); + return readl(gpch->regbase + AU1000_GPIO1_ST) & mask; } -static void au1xxx_gpio1_write(unsigned gpio, int value) +static void au1000_gpio1_set(struct gpio_chip *chip, + unsigned offset, int value) { + u32 mask = 1 << offset; + u32 reg_offset; + struct au1000_gpio_chip *gpch; + unsigned long flags; + + gpch = container_of(chip, struct au1000_gpio_chip, chip); + if (value) - gpio1->outputset = (0x01 << gpio); + reg_offset = AU1000_GPIO1_OUT; else - /* Output a zero */ - gpio1->outputclr = (0x01 << gpio); + reg_offset = AU1000_GPIO1_CLR; + + local_irq_save(flags); + writel(mask, gpch->regbase + reg_offset); + local_irq_restore(flags); } -static int au1xxx_gpio1_direction_input(unsigned gpio) +static int au1000_gpio1_direction_input(struct gpio_chip *chip, unsigned offset) { - gpio1->pininputen = (0x01 << gpio); + u32 mask = 1 << offset; + struct au1000_gpio_chip *gpch; + + gpch = container_of(chip, struct au1000_gpio_chip, chip); + writel(mask, gpch->regbase + AU1000_GPIO1_ST); + return 0; } -static int au1xxx_gpio1_direction_output(unsigned gpio, int value) +static int au1000_gpio1_direction_output(struct gpio_chip *chip, + unsigned offset, int value) { - gpio1->trioutclr = (0x01 & gpio); - au1xxx_gpio1_write(gpio, value); + u32 mask = 1 << offset; + struct au1000_gpio_chip *gpch; + + gpch = container_of(chip, struct au1000_gpio_chip, chip); + + writel(mask, gpch->regbase + AU1000_GPIO1_TRI_OUT); + au1000_gpio1_set(chip, offset, value); + return 0; } -int au1xxx_gpio_get_value(unsigned gpio) -{ - if (gpio >= AU1XXX_GPIO_BASE) -#if defined(CONFIG_SOC_AU1000) - return 0; -#else - return au1xxx_gpio2_read(gpio); +struct au1000_gpio_chip au1000_gpio_chip[] = { + [0] = { + .regbase = (void __iomem *)SYS_BASE, + .chip = { + .label = "au1000-gpio1", + .direction_input = au1000_gpio1_direction_input, + .direction_output = au1000_gpio1_direction_output, + .get = au1000_gpio1_get, + .set = au1000_gpio1_set, + .base = 0, + .ngpio = 32, + }, + }, +#if !defined(CONFIG_SOC_AU1000) + [1] = { + .regbase = (void __iomem *)GPIO2_BASE, + .chip = { + .label = "au1000-gpio2", + .direction_input = au1000_gpio2_direction_input, + .direction_output = au1000_gpio2_direction_output, + .get = au1000_gpio2_get, + .set = au1000_gpio2_set, + .base = AU1XXX_GPIO_BASE, + .ngpio = 32, + }, + }, #endif - else - return au1xxx_gpio1_read(gpio); -} -EXPORT_SYMBOL(au1xxx_gpio_get_value); +}; -void au1xxx_gpio_set_value(unsigned gpio, int value) +static int __init au1000_gpio_init(void) { - if (gpio >= AU1XXX_GPIO_BASE) -#if defined(CONFIG_SOC_AU1000) - ; -#else - au1xxx_gpio2_write(gpio, value); -#endif - else - au1xxx_gpio1_write(gpio, value); -} -EXPORT_SYMBOL(au1xxx_gpio_set_value); + gpiochip_add(&au1000_gpio_chip[0].chip); +#if !defined(CONFIG_SOC_AU1000) + gpiochip_add(&au1000_gpio_chip[1].chip); -int au1xxx_gpio_direction_input(unsigned gpio) -{ - if (gpio >= AU1XXX_GPIO_BASE) -#if defined(CONFIG_SOC_AU1000) - return -ENODEV; -#else - return au1xxx_gpio2_direction_input(gpio); + return 0; #endif - - return au1xxx_gpio1_direction_input(gpio); } -EXPORT_SYMBOL(au1xxx_gpio_direction_input); +arch_initcall(au1000_gpio_init); -int au1xxx_gpio_direction_output(unsigned gpio, int value) -{ - if (gpio >= AU1XXX_GPIO_BASE) -#if defined(CONFIG_SOC_AU1000) - return -ENODEV; -#else - return au1xxx_gpio2_direction_output(gpio, value); -#endif - - return au1xxx_gpio1_direction_output(gpio, value); -} -EXPORT_SYMBOL(au1xxx_gpio_direction_output); diff --git a/arch/mips/include/asm/mach-au1x00/gpio.h b/arch/mips/include/asm/mach-au1x00/gpio.h index 2dc61e0..34d9b72 100644 --- a/arch/mips/include/asm/mach-au1x00/gpio.h +++ b/arch/mips/include/asm/mach-au1x00/gpio.h @@ -5,65 +5,29 @@ #define AU1XXX_GPIO_BASE 200 -struct au1x00_gpio2 { - u32 dir; - u32 reserved; - u32 output; - u32 pinstate; - u32 inten; - u32 enable; -}; +/* GPIO bank 1 offsets */ +#define AU1000_GPIO1_TRI_OUT 0x0100 +#define AU1000_GPIO1_OUT 0x0108 +#define AU1000_GPIO1_ST 0x0110 +#define AU1000_GPIO1_CLR 0x010C -extern int au1xxx_gpio_get_value(unsigned gpio); -extern void au1xxx_gpio_set_value(unsigned gpio, int value); -extern int au1xxx_gpio_direction_input(unsigned gpio); -extern int au1xxx_gpio_direction_output(unsigned gpio, int value); +/* GPIO bank 2 offsets */ +#define AU1000_GPIO2_DIR 0x00 +#define AU1000_GPIO2_RSVD 0x04 +#define AU1000_GPIO2_OUT 0x08 +#define AU1000_GPIO2_ST 0x0C +#define AU1000_GPIO2_INT 0x10 +#define AU1000_GPIO2_EN 0x14 +#define GPIO2_OUT_EN_MASK 0x00010000 -/* Wrappers for the arch-neutral GPIO API */ +#define gpio_to_irq(gpio) NULL -static inline int gpio_request(unsigned gpio, const char *label) -{ - /* Not yet implemented */ - return 0; -} +#define gpio_get_value __gpio_get_value +#define gpio_set_value __gpio_set_value -static inline void gpio_free(unsigned gpio) -{ - /* Not yet implemented */ -} +#define gpio_cansleep __gpio_cansleep -static inline int gpio_direction_input(unsigned gpio) -{ - return au1xxx_gpio_direction_input(gpio); -} - -static inline int gpio_direction_output(unsigned gpio, int value) -{ - return au1xxx_gpio_direction_output(gpio, value); -} - -static inline int gpio_get_value(unsigned gpio) -{ - return au1xxx_gpio_get_value(gpio); -} - -static inline void gpio_set_value(unsigned gpio, int value) -{ - au1xxx_gpio_set_value(gpio, value); -} - -static inline int gpio_to_irq(unsigned gpio) -{ - return gpio; -} - -static inline int irq_to_gpio(unsigned irq) -{ - return irq; -} - -/* For cansleep */ #include #endif /* _AU1XXX_GPIO_H_ */ From travis@sgi.com Thu Jan 15 16:44:21 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 15 Jan 2009 16:44:23 +0000 (GMT) Received: from relay2.sgi.com ([192.48.179.30]:62355 "EHLO relay.sgi.com") by ftp.linux-mips.org with ESMTP id S21365943AbZAOQoV (ORCPT ); Thu, 15 Jan 2009 16:44:21 +0000 Received: from cthulhu.engr.sgi.com (cthulhu.engr.sgi.com [150.166.39.100]) by relay2.corp.sgi.com (Postfix) with ESMTP id 9E7DD30408A; Thu, 15 Jan 2009 08:44:11 -0800 (PST) Received: from [134.15.31.35] (vpn-2-travis.corp.sgi.com [134.15.31.35]) by cthulhu.engr.sgi.com (8.12.10/8.12.10/SuSE Linux 0.7) with ESMTP id n0FGi8F5014298; Thu, 15 Jan 2009 08:44:08 -0800 Message-ID: <496F67D8.4060507@sgi.com> Date: Thu, 15 Jan 2009 08:44:08 -0800 From: Mike Travis User-Agent: Thunderbird 2.0.0.6 (X11/20070801) MIME-Version: 1.0 To: Ingo Molnar CC: Rusty Russell , Yinghai Lu , Thomas Gleixner , "H. Peter Anvin" , Tony Luck , IA64 , Ralf Baechle , linux-mips@linux-mips.org, David Howells , Koichi Yasutake , linux-am33-list@redhat.com, "David S. Miller" , SPARC , LKML Subject: Re: crash: IP: [] __bitmap_intersects+0x48/0x73 [PATCH supplied] References: <496BF6D5.9030403@sgi.com> <20090113130048.GB31147@elte.hu> <496CAF5A.3010304@sgi.com> <496D0F46.2010907@sgi.com> <496D2172.6030608@sgi.com> <20090114165431.GA18826@elte.hu> <20090114165524.GA21742@elte.hu> <20090114175126.GA21078@elte.hu> <496E78BA.5040609@sgi.com> <20090115101428.GG5833@elte.hu> In-Reply-To: <20090115101428.GG5833@elte.hu> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21750 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: travis@sgi.com Precedence: bulk X-list: linux-mips Content-Length: 2749 Lines: 84 Ingo Molnar wrote: > * Mike Travis wrote: > >> Ingo Molnar wrote: >>> also, with latest tip/master the ia64 cross-build still fails: >>> >>> /home/mingo/tip/arch/ia64/kernel/irq_ia64.c: In function `ia64_handle_irq': >>> /home/mingo/tip/arch/ia64/kernel/irq_ia64.c:498: error: structure has no member named `irqs' >>> /home/mingo/tip/arch/ia64/kernel/irq_ia64.c:500: error: structure has no member named `irqs' >>> /home/mingo/tip/arch/ia64/kernel/irq_ia64.c: In function `ia64_process_pending_intr': >>> /home/mingo/tip/arch/ia64/kernel/irq_ia64.c:556: error: structure has no member named `irqs' >>> /home/mingo/tip/arch/ia64/kernel/irq_ia64.c:558: error: structure has no member named `irqs' >>> make[2]: *** [arch/ia64/kernel/irq_ia64.o] Error 1 >>> make[2]: *** Waiting for unfinished jobs.... >>> >>> and so does the MIPS build: >>> >>> /home/mingo/tip/arch/mips/sgi-ip22/ip22-int.c: In function 'indy_buserror_irq': >>> /home/mingo/tip/arch/mips/sgi-ip22/ip22-int.c:158: error: 'struct kernel_stat' has no member named 'irqs' >>> make[2]: *** [arch/mips/sgi-ip22/ip22-int.o] Error 1 >>> make[2]: *** Waiting for unfinished jobs.... >>> /home/mingo/tip/arch/mips/sgi-ip22/ip22-time.c: In function 'indy_8254timer_irq': >>> /home/mingo/tip/arch/mips/sgi-ip22/ip22-time.c:125: error: 'struct kernel_stat' has no member named 'irqs' >>> make[2]: *** [arch/mips/sgi-ip22/ip22-time.o] Error 1 >>> make[1]: *** [arch/mips/sgi-ip22] Error 2 >>> make[1]: *** Waiting for unfinished jobs.... >>> >>> Ingo >> Hi Ingo, >> >> This appears to be a fallout of the sparse irqs changes. Here is a >> suggested patch. >> >> Btw, my ia64 build fails under tip/cpus4096 because this commit is not >> present: >> >> commit e65e49d0f3714f4a6a42f6f6a19926ba33fcda75 >> Author: Mike Travis >> Date: Mon Jan 12 15:27:13 2009 -0800 >> >> irq: update all arches for new irq_desc > > it is present: > > [mingo@hera tip]$ git log cpus4096 | grep e65e49d > commit e65e49d0f3714f4a6a42f6f6a19926ba33fcda75 > > Ingo Hmm, the exact same command on my work tree produces nothing. If I generate a whole new tip/cpus4096 tree, it's then there. Once again a victim of git remote updating - not! There must be something that I'm doing wrong: Non-working tree: 21> git-describe v2.6.29-rc1-19-g92296c6 22> git-status # On branch cpus4096 # Your branch is behind 'tip/cpus4096' by 233 commits, and can be fast-forwarded. 23> git-remote update Updating linus Updating tip 24> git-status # On branch cpus4096 # Your branch is behind 'tip/cpus4096' by 233 commits, and can be fast-forwarded. 25> git-describe v2.6.29-rc1-19-g92296c6 New (working) tree: 2> git-describe v2.6.29-rc1-252-g5cd7376 ??? Thanks, Mike From travis@sgi.com Thu Jan 15 16:46:41 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 15 Jan 2009 16:46:44 +0000 (GMT) Received: from relay3.sgi.com ([192.48.171.31]:15533 "EHLO relay.sgi.com") by ftp.linux-mips.org with ESMTP id S21365943AbZAOQql (ORCPT ); Thu, 15 Jan 2009 16:46:41 +0000 Received: from cthulhu.engr.sgi.com (cthulhu.engr.sgi.com [150.166.39.100]) by relay3.corp.sgi.com (Postfix) with ESMTP id 910E2AC015; Thu, 15 Jan 2009 08:46:32 -0800 (PST) Received: from [134.15.31.35] (vpn-2-travis.corp.sgi.com [134.15.31.35]) by cthulhu.engr.sgi.com (8.12.10/8.12.10/SuSE Linux 0.7) with ESMTP id n0FGkQF5014487; Thu, 15 Jan 2009 08:46:27 -0800 Message-ID: <496F6862.5070104@sgi.com> Date: Thu, 15 Jan 2009 08:46:26 -0800 From: Mike Travis User-Agent: Thunderbird 2.0.0.6 (X11/20070801) MIME-Version: 1.0 To: Ingo Molnar CC: Rusty Russell , Yinghai Lu , Thomas Gleixner , "H. Peter Anvin" , Tony Luck , IA64 , Ralf Baechle , linux-mips@linux-mips.org, David Howells , Koichi Yasutake , linux-am33-list@redhat.com, "David S. Miller" , SPARC , LKML Subject: Re: crash: IP: [] __bitmap_intersects+0x48/0x73 [PATCH supplied] References: <496BF6D5.9030403@sgi.com> <20090113130048.GB31147@elte.hu> <496CAF5A.3010304@sgi.com> <496D0F46.2010907@sgi.com> <496D2172.6030608@sgi.com> <20090114165431.GA18826@elte.hu> <20090114165524.GA21742@elte.hu> <20090114175126.GA21078@elte.hu> <496E78BA.5040609@sgi.com> <20090115101617.GH5833@elte.hu> In-Reply-To: <20090115101617.GH5833@elte.hu> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21751 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: travis@sgi.com Precedence: bulk X-list: linux-mips Content-Length: 318 Lines: 14 Ingo Molnar wrote: > * Mike Travis wrote: > >> Subject: irq: fix build errors referencing old kstat.irqs array > > i've picked this up into tip/cpus4096, thanks Mike, > > Ingo I sent it as a patch because I wasn't sure if you wanted in the cpus4096 branch or the sparseirqs branch. Thanks, Mike From mingo@elte.hu Thu Jan 15 17:35:43 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 15 Jan 2009 17:35:45 +0000 (GMT) Received: from mx2.mail.elte.hu ([157.181.151.9]:50614 "EHLO mx2.mail.elte.hu") by ftp.linux-mips.org with ESMTP id S21365245AbZAORfl (ORCPT ); Thu, 15 Jan 2009 17:35:41 +0000 Received: from elvis.elte.hu ([157.181.1.14]) by mx2.mail.elte.hu with esmtp (Exim) id 1LNW7Z-0007hn-HY from ; Thu, 15 Jan 2009 18:35:15 +0100 Received: by elvis.elte.hu (Postfix, from userid 1004) id 9B88D3E21AA; Thu, 15 Jan 2009 18:35:05 +0100 (CET) Date: Thu, 15 Jan 2009 18:35:06 +0100 From: Ingo Molnar To: Mike Travis Cc: Rusty Russell , Yinghai Lu , Thomas Gleixner , "H. Peter Anvin" , Tony Luck , IA64 , Ralf Baechle , linux-mips@linux-mips.org, David Howells , Koichi Yasutake , linux-am33-list@redhat.com, "David S. Miller" , SPARC , LKML Subject: Re: crash: IP: [] __bitmap_intersects+0x48/0x73 [PATCH supplied] Message-ID: <20090115173506.GB22472@elte.hu> References: <20090113130048.GB31147@elte.hu> <496CAF5A.3010304@sgi.com> <496D0F46.2010907@sgi.com> <496D2172.6030608@sgi.com> <20090114165431.GA18826@elte.hu> <20090114165524.GA21742@elte.hu> <20090114175126.GA21078@elte.hu> <496E78BA.5040609@sgi.com> <20090115101428.GG5833@elte.hu> <496F67D8.4060507@sgi.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <496F67D8.4060507@sgi.com> User-Agent: Mutt/1.5.18 (2008-05-17) Received-SPF: neutral (mx2: 157.181.1.14 is neither permitted nor denied by domain of elte.hu) client-ip=157.181.1.14; envelope-from=mingo@elte.hu; helo=elvis.elte.hu; X-ELTE-VirusStatus: clean X-ELTE-SpamScore: -1.5 X-ELTE-SpamLevel: X-ELTE-SpamCheck: no X-ELTE-SpamVersion: ELTE 2.0 X-ELTE-SpamCheck-Details: score=-1.5 required=5.9 tests=BAYES_00 autolearn=no SpamAssassin version=3.2.3 -1.5 BAYES_00 BODY: Bayesian spam probability is 0 to 1% [score: 0.0000] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21752 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mingo@elte.hu Precedence: bulk X-list: linux-mips Content-Length: 241 Lines: 14 * Mike Travis wrote: > Non-working tree: > > 21> git-describe > v2.6.29-rc1-19-g92296c6 > > 22> git-status why do you use git-dash commands? Latest git does not have them. Maybe you have an older Git version? Ingo From David.Daney@caviumnetworks.com Thu Jan 15 17:46:48 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 15 Jan 2009 17:46:51 +0000 (GMT) Received: from mail3.caviumnetworks.com ([12.108.191.235]:33143 "EHLO mail3.caviumnetworks.com") by ftp.linux-mips.org with ESMTP id S21365948AbZAORqs (ORCPT ); Thu, 15 Jan 2009 17:46:48 +0000 Received: from exch4.caveonetworks.com (Not Verified[192.168.16.23]) by mail3.caviumnetworks.com with MailMarshal (v6,2,2,3503) id ; Thu, 15 Jan 2009 12:45:11 -0500 Received: from exch4.caveonetworks.com ([192.168.16.23]) by exch4.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Thu, 15 Jan 2009 09:44:21 -0800 Received: from dd1.caveonetworks.com ([64.169.86.201]) by exch4.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Thu, 15 Jan 2009 09:44:20 -0800 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.2/8.14.2) with ESMTP id n0FHiIoW028700; Thu, 15 Jan 2009 09:44:18 -0800 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.2/8.14.2/Submit) id n0FHiHQV028698; Thu, 15 Jan 2009 09:44:17 -0800 From: David Daney To: linux-mips@linux-mips.org Cc: David Daney , Atsushi Nemoto Subject: [PATCH] MIPS: Only allow Cavium OCTEON to be configured for boards that support it. Date: Thu, 15 Jan 2009 09:44:17 -0800 Message-Id: <1232041457-28675-1-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.5.6.6 X-OriginalArrivalTime: 15 Jan 2009 17:44:20.0998 (UTC) FILETIME=[E58EBA60:01C97738] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21753 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Content-Length: 1461 Lines: 49 Signed-off-by: David Daney CC: Atsushi Nemoto --- arch/mips/Kconfig | 8 ++++++-- 1 files changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 6dddea3..bdb1790 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -603,7 +603,7 @@ config CAVIUM_OCTEON_SIMULATOR select SYS_SUPPORTS_64BIT_KERNEL select SYS_SUPPORTS_BIG_ENDIAN select SYS_SUPPORTS_HIGHMEM - select CPU_CAVIUM_OCTEON + select SYS_HAS_CPU_CPU_CAVIUM_OCTEON help The Octeon simulator is software performance model of the Cavium Octeon Processor. It supports simulating Octeon processors on x86 @@ -618,7 +618,7 @@ config CAVIUM_OCTEON_REFERENCE_BOARD select SYS_SUPPORTS_BIG_ENDIAN select SYS_SUPPORTS_HIGHMEM select SYS_HAS_EARLY_PRINTK - select CPU_CAVIUM_OCTEON + select SYS_HAS_CPU_CPU_CAVIUM_OCTEON select SWAP_IO_SPACE help This option supports all of the Octeon reference boards from Cavium @@ -1237,6 +1237,7 @@ config CPU_SB1 config CPU_CAVIUM_OCTEON bool "Cavium Octeon processor" + depends on SYS_HAS_CPU_CPU_CAVIUM_OCTEON select IRQ_CPU select IRQ_CPU_OCTEON select CPU_HAS_PREFETCH @@ -1317,6 +1318,9 @@ config SYS_HAS_CPU_RM9000 config SYS_HAS_CPU_SB1 bool +config SYS_HAS_CPU_CPU_CAVIUM_OCTEON + bool + # # CPU may reorder R->R, R->W, W->R, W->W # Reordering beyond LL and SC is handled in WEAK_REORDERING_BEYOND_LLSC -- 1.5.6.6 From David.Daney@caviumnetworks.com Thu Jan 15 17:47:33 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 15 Jan 2009 17:47:36 +0000 (GMT) Received: from mail3.caviumnetworks.com ([12.108.191.235]:39032 "EHLO mail3.caviumnetworks.com") by ftp.linux-mips.org with ESMTP id S21365238AbZAORrd (ORCPT ); Thu, 15 Jan 2009 17:47:33 +0000 Received: from exch4.caveonetworks.com (Not Verified[192.168.16.23]) by mail3.caviumnetworks.com with MailMarshal (v6,2,2,3503) id ; Thu, 15 Jan 2009 12:47:26 -0500 Received: from exch4.caveonetworks.com ([192.168.16.23]) by exch4.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Thu, 15 Jan 2009 09:46:41 -0800 Received: from dd1.caveonetworks.com ([64.169.86.201]) by exch4.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Thu, 15 Jan 2009 09:46:40 -0800 Message-ID: <496F7680.2090805@caviumnetworks.com> Date: Thu, 15 Jan 2009 09:46:40 -0800 From: David Daney User-Agent: Thunderbird 2.0.0.19 (X11/20090105) MIME-Version: 1.0 To: David Daney CC: linux-mips@linux-mips.org, Atsushi Nemoto Subject: Re: [PATCH] MIPS: Only allow Cavium OCTEON to be configured for boards that support it. References: <1232041457-28675-1-git-send-email-ddaney@caviumnetworks.com> In-Reply-To: <1232041457-28675-1-git-send-email-ddaney@caviumnetworks.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 15 Jan 2009 17:46:40.0981 (UTC) FILETIME=[38FE7050:01C97739] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21754 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Content-Length: 431 Lines: 19 David Daney wrote: > Signed-off-by: David Daney > CC: Atsushi Nemoto > --- > arch/mips/Kconfig | 8 ++++++-- > 1 files changed, 6 insertions(+), 2 deletions(-) > [...] > > +config SYS_HAS_CPU_CPU_CAVIUM_OCTEON > + bool > + Probably there are too may CPUs in the name. These are things that are only found after mailing the patch. I will send a fixed patch. David Daney From David.Daney@caviumnetworks.com Thu Jan 15 17:57:43 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 15 Jan 2009 17:57:45 +0000 (GMT) Received: from mail3.caviumnetworks.com ([12.108.191.235]:45700 "EHLO mail3.caviumnetworks.com") by ftp.linux-mips.org with ESMTP id S21365949AbZAOR5l (ORCPT ); Thu, 15 Jan 2009 17:57:41 +0000 Received: from exch4.caveonetworks.com (Not Verified[192.168.16.23]) by mail3.caviumnetworks.com with MailMarshal (v6,2,2,3503) id ; Thu, 15 Jan 2009 12:57:29 -0500 Received: from exch4.caveonetworks.com ([192.168.16.23]) by exch4.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Thu, 15 Jan 2009 09:56:31 -0800 Received: from dd1.caveonetworks.com ([64.169.86.201]) by exch4.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Thu, 15 Jan 2009 09:56:31 -0800 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.2/8.14.2) with ESMTP id n0FHuR3C004838; Thu, 15 Jan 2009 09:56:27 -0800 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.2/8.14.2/Submit) id n0FHuRSC004837; Thu, 15 Jan 2009 09:56:27 -0800 From: David Daney To: linux-mips@linux-mips.org Cc: David Daney , Atsushi Nemoto Subject: [PATCH] MIPS: Only allow Cavium OCTEON to be configured for boards that support it (v2). Date: Thu, 15 Jan 2009 09:56:27 -0800 Message-Id: <1232042187-4814-1-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.5.6.6 X-OriginalArrivalTime: 15 Jan 2009 17:56:31.0552 (UTC) FILETIME=[99006C00:01C9773A] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21755 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Content-Length: 1445 Lines: 49 Signed-off-by: David Daney CC: Atsushi Nemoto --- arch/mips/Kconfig | 8 ++++++-- 1 files changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 6dddea3..31191c5 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -603,7 +603,7 @@ config CAVIUM_OCTEON_SIMULATOR select SYS_SUPPORTS_64BIT_KERNEL select SYS_SUPPORTS_BIG_ENDIAN select SYS_SUPPORTS_HIGHMEM - select CPU_CAVIUM_OCTEON + select SYS_HAS_CPU_CAVIUM_OCTEON help The Octeon simulator is software performance model of the Cavium Octeon Processor. It supports simulating Octeon processors on x86 @@ -618,7 +618,7 @@ config CAVIUM_OCTEON_REFERENCE_BOARD select SYS_SUPPORTS_BIG_ENDIAN select SYS_SUPPORTS_HIGHMEM select SYS_HAS_EARLY_PRINTK - select CPU_CAVIUM_OCTEON + select SYS_HAS_CPU_CAVIUM_OCTEON select SWAP_IO_SPACE help This option supports all of the Octeon reference boards from Cavium @@ -1237,6 +1237,7 @@ config CPU_SB1 config CPU_CAVIUM_OCTEON bool "Cavium Octeon processor" + depends on SYS_HAS_CPU_CAVIUM_OCTEON select IRQ_CPU select IRQ_CPU_OCTEON select CPU_HAS_PREFETCH @@ -1317,6 +1318,9 @@ config SYS_HAS_CPU_RM9000 config SYS_HAS_CPU_SB1 bool +config SYS_HAS_CPU_CAVIUM_OCTEON + bool + # # CPU may reorder R->R, R->W, W->R, W->W # Reordering beyond LL and SC is handled in WEAK_REORDERING_BEYOND_LLSC -- 1.5.6.6 From schwab@suse.de Thu Jan 15 18:00:01 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 15 Jan 2009 18:00:03 +0000 (GMT) Received: from ns2.suse.de ([195.135.220.15]:34770 "EHLO mx2.suse.de") by ftp.linux-mips.org with ESMTP id S21365949AbZAOSAB (ORCPT ); Thu, 15 Jan 2009 18:00:01 +0000 Received: from Relay1.suse.de (mail2.suse.de [195.135.221.8]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mx2.suse.de (Postfix) with ESMTP id 4628A483BB; Thu, 15 Jan 2009 18:59:57 +0100 (CET) From: Andreas Schwab To: Mike Travis Cc: Ingo Molnar , Rusty Russell , Yinghai Lu , Thomas Gleixner , "H. Peter Anvin" , Tony Luck , IA64 , Ralf Baechle , linux-mips@linux-mips.org, David Howells , Koichi Yasutake , linux-am33-list@redhat.com, "David S. Miller" , SPARC , LKML Subject: Re: crash: IP: [] __bitmap_intersects+0x48/0x73 [PATCH supplied] References: <496BF6D5.9030403@sgi.com> <20090113130048.GB31147@elte.hu> <496CAF5A.3010304@sgi.com> <496D0F46.2010907@sgi.com> <496D2172.6030608@sgi.com> <20090114165431.GA18826@elte.hu> <20090114165524.GA21742@elte.hu> <20090114175126.GA21078@elte.hu> <496E78BA.5040609@sgi.com> <20090115101428.GG5833@elte.hu> <496F67D8.4060507@sgi.com> X-Yow: NOW, I'm supposed to SCRAMBLE two, and HOLD th' MAYO!! Date: Thu, 15 Jan 2009 18:59:54 +0100 In-Reply-To: <496F67D8.4060507@sgi.com> (Mike Travis's message of "Thu, 15 Jan 2009 08:44:08 -0800") Message-ID: User-Agent: Gnus/5.110009 (No Gnus v0.9) Emacs/22.3 (gnu/linux) MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: 8bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21756 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: schwab@suse.de Precedence: bulk X-list: linux-mips Content-Length: 467 Lines: 16 Mike Travis writes: > 23> git-remote update > Updating linus > Updating tip This only updates the remotes, but does not merge anything into your local branch. You need to run "git merge tip" to do that. Andreas. -- Andreas Schwab, SuSE Labs, schwab@suse.de SuSE Linux Products GmbH, Maxfeldstraße 5, 90409 Nürnberg, Germany PGP key fingerprint = 58CA 54C7 6D53 942B 1756 01D3 44D5 214B 8276 4ED5 "And now for something completely different." From David.Daney@caviumnetworks.com Thu Jan 15 19:40:03 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 15 Jan 2009 19:40:05 +0000 (GMT) Received: from mail3.caviumnetworks.com ([12.108.191.235]:16165 "EHLO mail3.caviumnetworks.com") by ftp.linux-mips.org with ESMTP id S21365961AbZAOTkD (ORCPT ); Thu, 15 Jan 2009 19:40:03 +0000 Received: from exch4.caveonetworks.com (Not Verified[192.168.16.23]) by mail3.caviumnetworks.com with MailMarshal (v6,2,2,3503) id ; Thu, 15 Jan 2009 14:38:50 -0500 Received: from exch4.caveonetworks.com ([192.168.16.23]) by exch4.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Thu, 15 Jan 2009 11:38:19 -0800 Received: from dd1.caveonetworks.com ([64.169.86.201]) by exch4.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Thu, 15 Jan 2009 11:38:18 -0800 Message-ID: <496F90AA.7070407@caviumnetworks.com> Date: Thu, 15 Jan 2009 11:38:18 -0800 From: David Daney User-Agent: Thunderbird 2.0.0.19 (X11/20090105) MIME-Version: 1.0 To: Manuel Lauss CC: Linux-MIPS , Ralf Baechle Subject: Re: [PATCH 06/14] MIPS: print irq handler description References: <80cf5c7a0db39a7230bae7766264acbfc68d200e.1229846412.git.mano@roarinelk.homelinux.net> <535458cb8c8f570089b2712a1e73ca7314d5b7c7.1229846413.git.mano@roarinelk.homelinux.net> In-Reply-To: <535458cb8c8f570089b2712a1e73ca7314d5b7c7.1229846413.git.mano@roarinelk.homelinux.net> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 15 Jan 2009 19:38:18.0739 (UTC) FILETIME=[D12B3430:01C97748] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21757 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Content-Length: 2729 Lines: 70 Manuel Lauss wrote: > Add the name set by set_irq_chip_and_handler_name() to the output of Alchemy is the only mips cpu that uses set_irq_chip_and_handler_name()... > /proc/interrupts, like so: > > db1200 ~ # cat /proc/interrupts > CPU0 > 8: 52 Alchemy-IC0-hilevel serial > 10: 171 Alchemy-IC0-hilevel au1xxx-mmc > 11: 47 Alchemy-IC0-hilevel Au1xxx dbdma > 18: 1 Alchemy-IC0-hilevel au1550-spi > 29: 1250997 Alchemy-IC0-riseedge timer > 37: 211 Alchemy-IC0-hilevel ehci_hcd:usb1, ohci_hcd:usb2 > 38: 0 Alchemy-IC0-hilevel lcd > 72: 2623 DB1200 CPLD-level ide0 > 73: 257 DB1200 CPLD-level eth0 > 84: 1 DB1200 CPLD-level sd_insert > 85: 0 DB1200 CPLD-level sd_eject > > ERR: 0 > > Signed-off-by: Manuel Lauss > --- > arch/mips/kernel/irq.c | 1 + > 1 files changed, 1 insertions(+), 0 deletions(-) > > diff --git a/arch/mips/kernel/irq.c b/arch/mips/kernel/irq.c > index 4b4007b..a0ff2b6 100644 > --- a/arch/mips/kernel/irq.c > +++ b/arch/mips/kernel/irq.c > @@ -111,6 +111,7 @@ int show_interrupts(struct seq_file *p, void *v) > seq_printf(p, "%10u ", kstat_cpu(j).irqs[i]); > #endif > seq_printf(p, " %14s", irq_desc[i].chip->name); > + seq_printf(p, "-%-8s", irq_desc[i].name); > seq_printf(p, " %s", action->name); > ... so for most mips CPUs we now get something ugly like this: octeon:~# cat /proc/interrupts CPU0 CPU1 CPU2 CPU3 23: 7371 7120 5747 5373 Core- timer 56: 6171 9482 7023 8102 CIU0- mailbox0 57: 0 0 0 0 CIU0- mailbox1 58: 156 0 0 0 CIU0- serial 64: 376 0 0 0 CIU0- MSI[0:63] 86: 0 0 0 0 CIU0- mgmt0 87: 1928 0 0 0 CIU0- pata_octeon_cf 88: 7 0 0 0 CIU1- watchdog 89: 0 7 0 0 CIU1- watchdog 90: 0 0 7 0 CIU1- watchdog 91: 0 0 0 7 CIU1- watchdog 106: 0 0 0 0 CIU1- mgmt1 152: 376 0 0 0 MSI- eth0 From mano@roarinelk.homelinux.net Thu Jan 15 19:50:37 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 15 Jan 2009 19:50:41 +0000 (GMT) Received: from fnoeppeil36.netpark.at ([217.175.205.164]:58064 "EHLO roarinelk.homelinux.net") by ftp.linux-mips.org with ESMTP id S21365967AbZAOTuh (ORCPT ); Thu, 15 Jan 2009 19:50:37 +0000 Received: (qmail 8812 invoked by uid 1000); 15 Jan 2009 20:49:21 +0100 Date: Thu, 15 Jan 2009 20:49:21 +0100 From: Manuel Lauss To: David Daney Cc: Linux-MIPS , Ralf Baechle Subject: Re: [PATCH 06/14] MIPS: print irq handler description Message-ID: <20090115194921.GB8656@roarinelk.homelinux.net> References: <80cf5c7a0db39a7230bae7766264acbfc68d200e.1229846412.git.mano@roarinelk.homelinux.net> <535458cb8c8f570089b2712a1e73ca7314d5b7c7.1229846413.git.mano@roarinelk.homelinux.net> <496F90AA.7070407@caviumnetworks.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <496F90AA.7070407@caviumnetworks.com> User-Agent: Mutt/1.5.16 (2007-06-09) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21758 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mano@roarinelk.homelinux.net Precedence: bulk X-list: linux-mips Content-Length: 1726 Lines: 52 Hi David, On Thu, Jan 15, 2009 at 11:38:18AM -0800, David Daney wrote: >> Add the name set by set_irq_chip_and_handler_name() to the output of > > Alchemy is the only mips cpu that uses set_irq_chip_and_handler_name()... > ... so for most mips CPUs we now get something ugly like this: > > octeon:~# cat /proc/interrupts > CPU0 CPU1 CPU2 CPU3 > 23: 7371 7120 5747 5373 Core- > timer Ouch, I see. Well, I certainly have no objections if you want to revert the patch, but I like that I can see how triggers are set up (nice esp. for gpio's and my homebrew userspace gpio interface). Or how about this? --- From: Manuel Lauss Subject: [PATCH] MIPS: only print handler name if its actually set. David Daney reports that Alchemy is the only in-tree user of set_irq_handler_and_name(). On other systems this leaves ugly "-" strings in cpuinfo. So, only print the handler string if it was actually set. Signed-off-by: Manuel Lauss --- arch/mips/kernel/irq.c | 3 ++- 1 files changed, 2 insertions(+), 1 deletions(-) diff --git a/arch/mips/kernel/irq.c b/arch/mips/kernel/irq.c index a0ff2b6..9061ae9 100644 --- a/arch/mips/kernel/irq.c +++ b/arch/mips/kernel/irq.c @@ -111,7 +111,8 @@ int show_interrupts(struct seq_file *p, void *v) seq_printf(p, "%10u ", kstat_cpu(j).irqs[i]); #endif seq_printf(p, " %14s", irq_desc[i].chip->name); - seq_printf(p, "-%-8s", irq_desc[i].name); + if (irq_desc[i].name) + seq_printf(p, "-%-8s", irq_desc[i].name); seq_printf(p, " %s", action->name); for (action=action->next; action; action = action->next) -- 1.6.0.6 From David.Daney@caviumnetworks.com Thu Jan 15 19:59:19 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 15 Jan 2009 19:59:22 +0000 (GMT) Received: from mail3.caviumnetworks.com ([12.108.191.235]:10562 "EHLO mail3.caviumnetworks.com") by ftp.linux-mips.org with ESMTP id S21365965AbZAOT7T (ORCPT ); Thu, 15 Jan 2009 19:59:19 +0000 Received: from exch4.caveonetworks.com (Not Verified[192.168.16.23]) by mail3.caviumnetworks.com with MailMarshal (v6,2,2,3503) id ; Thu, 15 Jan 2009 14:59:13 -0500 Received: from exch4.caveonetworks.com ([192.168.16.23]) by exch4.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Thu, 15 Jan 2009 11:58:50 -0800 Received: from dd1.caveonetworks.com ([64.169.86.201]) by exch4.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Thu, 15 Jan 2009 11:58:49 -0800 Message-ID: <496F9579.7050300@caviumnetworks.com> Date: Thu, 15 Jan 2009 11:58:49 -0800 From: David Daney User-Agent: Thunderbird 2.0.0.19 (X11/20090105) MIME-Version: 1.0 To: Manuel Lauss CC: Linux-MIPS , Ralf Baechle Subject: Re: [PATCH 06/14] MIPS: print irq handler description References: <80cf5c7a0db39a7230bae7766264acbfc68d200e.1229846412.git.mano@roarinelk.homelinux.net> <535458cb8c8f570089b2712a1e73ca7314d5b7c7.1229846413.git.mano@roarinelk.homelinux.net> <496F90AA.7070407@caviumnetworks.com> <20090115194921.GB8656@roarinelk.homelinux.net> In-Reply-To: <20090115194921.GB8656@roarinelk.homelinux.net> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 15 Jan 2009 19:58:49.0781 (UTC) FILETIME=[AEED4E50:01C9774B] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21759 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Content-Length: 485 Lines: 16 Manuel Lauss wrote: [...] > Or how about this? > [...] seq_printf(p, " %14s", irq_desc[i].chip->name); > - seq_printf(p, "-%-8s", irq_desc[i].name); > + if (irq_desc[i].name) > + seq_printf(p, "-%-8s", irq_desc[i].name); > seq_printf(p, " %s", action->name); I will let you and Ralf decide. However it would be nice if action->name lined up with a mixture of NULL and non-NULL irq_desc[i].name. It is not clear to me if this is the case with your patch. David Daney From mano@roarinelk.homelinux.net Thu Jan 15 20:23:26 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 15 Jan 2009 20:23:28 +0000 (GMT) Received: from fnoeppeil36.netpark.at ([217.175.205.164]:61573 "EHLO roarinelk.homelinux.net") by ftp.linux-mips.org with ESMTP id S21365339AbZAOUX0 (ORCPT ); Thu, 15 Jan 2009 20:23:26 +0000 Received: (qmail 9201 invoked by uid 1000); 15 Jan 2009 21:22:10 +0100 Date: Thu, 15 Jan 2009 21:22:10 +0100 From: Manuel Lauss To: David Daney Cc: Linux-MIPS , Ralf Baechle Subject: Re: [PATCH 06/14] MIPS: print irq handler description Message-ID: <20090115202210.GC8656@roarinelk.homelinux.net> References: <80cf5c7a0db39a7230bae7766264acbfc68d200e.1229846412.git.mano@roarinelk.homelinux.net> <535458cb8c8f570089b2712a1e73ca7314d5b7c7.1229846413.git.mano@roarinelk.homelinux.net> <496F90AA.7070407@caviumnetworks.com> <20090115194921.GB8656@roarinelk.homelinux.net> <496F9579.7050300@caviumnetworks.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <496F9579.7050300@caviumnetworks.com> User-Agent: Mutt/1.5.16 (2007-06-09) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21760 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mano@roarinelk.homelinux.net Precedence: bulk X-list: linux-mips Content-Length: 731 Lines: 23 David, On Thu, Jan 15, 2009 at 11:58:49AM -0800, David Daney wrote: > Manuel Lauss wrote: > [...] >> Or how about this? > [...] seq_printf(p, " %14s", irq_desc[i].chip->name); >> - seq_printf(p, "-%-8s", irq_desc[i].name); >> + if (irq_desc[i].name) >> + seq_printf(p, "-%-8s", irq_desc[i].name); >> seq_printf(p, " %s", action->name); > > I will let you and Ralf decide. However it would be nice if action->name > lined up with a mixture of NULL and non-NULL irq_desc[i].name. It is not > clear to me if this is the case with your patch. Good point, no it's not the case unfortunately; the gap between the controller and irq names becomes unaesthetically wide. So please revert the patch. Thanks! Manuel Lauss From David.Daney@caviumnetworks.com Thu Jan 15 20:57:27 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 15 Jan 2009 20:57:52 +0000 (GMT) Received: from mail3.caviumnetworks.com ([12.108.191.235]:51878 "EHLO mail3.caviumnetworks.com") by ftp.linux-mips.org with ESMTP id S21365972AbZAOU51 (ORCPT ); Thu, 15 Jan 2009 20:57:27 +0000 Received: from exch4.caveonetworks.com (Not Verified[192.168.16.23]) by mail3.caviumnetworks.com with MailMarshal (v6,2,2,3503) id ; Thu, 15 Jan 2009 15:56:59 -0500 Received: from exch4.caveonetworks.com ([192.168.16.23]) by exch4.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Thu, 15 Jan 2009 12:56:10 -0800 Received: from dd1.caveonetworks.com ([64.169.86.201]) by exch4.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Thu, 15 Jan 2009 12:56:10 -0800 Message-ID: <496FA2E9.9030403@caviumnetworks.com> Date: Thu, 15 Jan 2009 12:56:09 -0800 From: David Daney User-Agent: Thunderbird 2.0.0.19 (X11/20090105) MIME-Version: 1.0 To: IDE/ATA development list , linux-mips Subject: [PATCH 0/2] libata: Add OCTEON Compact Flash driver. Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 15 Jan 2009 20:56:10.0112 (UTC) FILETIME=[B1862800:01C97753] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21761 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Content-Length: 900 Lines: 28 Greetings ata hackers, Linus recently merged support for the mips/Octeon cpu. Please consider adding this driver for the Compact Flash system present on many of the OCTEON development boards. This is a two part patch set, the first part adds a new column to the ata_timing table (for dmack_hold). This is used by the second patch which is the driver itself. I will reply with the two patches. Thanks, David Daney (2): libata: Add another column to the ata_timing table. libata: New driver for OCTEON SOC Compact Flash interface (v6). drivers/ata/Kconfig | 9 + drivers/ata/Makefile | 1 + drivers/ata/libata-core.c | 72 ++-- drivers/ata/pata_octeon_cf.c | 956 ++++++++++++++++++++++++++++++++++++++++++ include/linux/libata.h | 9 +- 5 files changed, 1009 insertions(+), 38 deletions(-) create mode 100644 drivers/ata/pata_octeon_cf.c From David.Daney@caviumnetworks.com Thu Jan 15 20:58:09 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 15 Jan 2009 20:58:12 +0000 (GMT) Received: from mail3.caviumnetworks.com ([12.108.191.235]:30375 "EHLO mail3.caviumnetworks.com") by ftp.linux-mips.org with ESMTP id S21365977AbZAOU6I (ORCPT ); Thu, 15 Jan 2009 20:58:08 +0000 Received: from exch4.caveonetworks.com (Not Verified[192.168.16.23]) by mail3.caviumnetworks.com with MailMarshal (v6,2,2,3503) id ; Thu, 15 Jan 2009 15:57:59 -0500 Received: from exch4.caveonetworks.com ([192.168.16.23]) by exch4.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Thu, 15 Jan 2009 12:57:36 -0800 Received: from dd1.caveonetworks.com ([64.169.86.201]) by exch4.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Thu, 15 Jan 2009 12:57:36 -0800 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.2/8.14.2) with ESMTP id n0FKvXgV016256; Thu, 15 Jan 2009 12:57:33 -0800 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.2/8.14.2/Submit) id n0FKvXpR016254; Thu, 15 Jan 2009 12:57:33 -0800 From: David Daney To: linux-ide@vger.kernel.org Cc: linux-mips@linux-mips.org, David Daney Subject: [PATCH 1/2] libata: Add another column to the ata_timing table. Date: Thu, 15 Jan 2009 12:57:32 -0800 Message-Id: <1232053053-16232-1-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.5.6.6 In-Reply-To: <496FA2E9.9030403@caviumnetworks.com> References: <496FA2E9.9030403@caviumnetworks.com> X-OriginalArrivalTime: 15 Jan 2009 20:57:36.0064 (UTC) FILETIME=[E4C16400:01C97753] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21762 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Content-Length: 6403 Lines: 141 The forthcoming OCTEON SOC Compact Flash driver needs an additional timing value that was not available in the ata_timing table. I add a new column for dmack_hold time. The values were obtained from the Compact Flash specification Rev 4.1. Signed-off-by: David Daney --- drivers/ata/libata-core.c | 72 +++++++++++++++++++++++---------------------- include/linux/libata.h | 9 ++++-- 2 files changed, 43 insertions(+), 38 deletions(-) diff --git a/drivers/ata/libata-core.c b/drivers/ata/libata-core.c index 71218d7..8fe0012 100644 --- a/drivers/ata/libata-core.c +++ b/drivers/ata/libata-core.c @@ -3029,33 +3029,33 @@ int sata_set_spd(struct ata_link *link) */ static const struct ata_timing ata_timing[] = { -/* { XFER_PIO_SLOW, 120, 290, 240, 960, 290, 240, 960, 0 }, */ - { XFER_PIO_0, 70, 290, 240, 600, 165, 150, 600, 0 }, - { XFER_PIO_1, 50, 290, 93, 383, 125, 100, 383, 0 }, - { XFER_PIO_2, 30, 290, 40, 330, 100, 90, 240, 0 }, - { XFER_PIO_3, 30, 80, 70, 180, 80, 70, 180, 0 }, - { XFER_PIO_4, 25, 70, 25, 120, 70, 25, 120, 0 }, - { XFER_PIO_5, 15, 65, 25, 100, 65, 25, 100, 0 }, - { XFER_PIO_6, 10, 55, 20, 80, 55, 20, 80, 0 }, - - { XFER_SW_DMA_0, 120, 0, 0, 0, 480, 480, 960, 0 }, - { XFER_SW_DMA_1, 90, 0, 0, 0, 240, 240, 480, 0 }, - { XFER_SW_DMA_2, 60, 0, 0, 0, 120, 120, 240, 0 }, - - { XFER_MW_DMA_0, 60, 0, 0, 0, 215, 215, 480, 0 }, - { XFER_MW_DMA_1, 45, 0, 0, 0, 80, 50, 150, 0 }, - { XFER_MW_DMA_2, 25, 0, 0, 0, 70, 25, 120, 0 }, - { XFER_MW_DMA_3, 25, 0, 0, 0, 65, 25, 100, 0 }, - { XFER_MW_DMA_4, 25, 0, 0, 0, 55, 20, 80, 0 }, - -/* { XFER_UDMA_SLOW, 0, 0, 0, 0, 0, 0, 0, 150 }, */ - { XFER_UDMA_0, 0, 0, 0, 0, 0, 0, 0, 120 }, - { XFER_UDMA_1, 0, 0, 0, 0, 0, 0, 0, 80 }, - { XFER_UDMA_2, 0, 0, 0, 0, 0, 0, 0, 60 }, - { XFER_UDMA_3, 0, 0, 0, 0, 0, 0, 0, 45 }, - { XFER_UDMA_4, 0, 0, 0, 0, 0, 0, 0, 30 }, - { XFER_UDMA_5, 0, 0, 0, 0, 0, 0, 0, 20 }, - { XFER_UDMA_6, 0, 0, 0, 0, 0, 0, 0, 15 }, +/* { XFER_PIO_SLOW, 120, 290, 240, 960, 290, 240, 0, 960, 0 }, */ + { XFER_PIO_0, 70, 290, 240, 600, 165, 150, 0, 600, 0 }, + { XFER_PIO_1, 50, 290, 93, 383, 125, 100, 0, 383, 0 }, + { XFER_PIO_2, 30, 290, 40, 330, 100, 90, 0, 240, 0 }, + { XFER_PIO_3, 30, 80, 70, 180, 80, 70, 0, 180, 0 }, + { XFER_PIO_4, 25, 70, 25, 120, 70, 25, 0, 120, 0 }, + { XFER_PIO_5, 15, 65, 25, 100, 65, 25, 0, 100, 0 }, + { XFER_PIO_6, 10, 55, 20, 80, 55, 20, 0, 80, 0 }, + + { XFER_SW_DMA_0, 120, 0, 0, 0, 480, 480, 50, 960, 0 }, + { XFER_SW_DMA_1, 90, 0, 0, 0, 240, 240, 30, 480, 0 }, + { XFER_SW_DMA_2, 60, 0, 0, 0, 120, 120, 20, 240, 0 }, + + { XFER_MW_DMA_0, 60, 0, 0, 0, 215, 215, 20, 480, 0 }, + { XFER_MW_DMA_1, 45, 0, 0, 0, 80, 50, 5, 150, 0 }, + { XFER_MW_DMA_2, 25, 0, 0, 0, 70, 25, 5, 120, 0 }, + { XFER_MW_DMA_3, 25, 0, 0, 0, 65, 25, 5, 100, 0 }, + { XFER_MW_DMA_4, 25, 0, 0, 0, 55, 20, 5, 80, 0 }, + +/* { XFER_UDMA_SLOW, 0, 0, 0, 0, 0, 0, 0, 0, 150 }, */ + { XFER_UDMA_0, 0, 0, 0, 0, 0, 0, 0, 0, 120 }, + { XFER_UDMA_1, 0, 0, 0, 0, 0, 0, 0, 0, 80 }, + { XFER_UDMA_2, 0, 0, 0, 0, 0, 0, 0, 0, 60 }, + { XFER_UDMA_3, 0, 0, 0, 0, 0, 0, 0, 0, 45 }, + { XFER_UDMA_4, 0, 0, 0, 0, 0, 0, 0, 0, 30 }, + { XFER_UDMA_5, 0, 0, 0, 0, 0, 0, 0, 0, 20 }, + { XFER_UDMA_6, 0, 0, 0, 0, 0, 0, 0, 0, 15 }, { 0xFF } }; @@ -3065,14 +3065,15 @@ static const struct ata_timing ata_timing[] = { static void ata_timing_quantize(const struct ata_timing *t, struct ata_timing *q, int T, int UT) { - q->setup = EZ(t->setup * 1000, T); - q->act8b = EZ(t->act8b * 1000, T); - q->rec8b = EZ(t->rec8b * 1000, T); - q->cyc8b = EZ(t->cyc8b * 1000, T); - q->active = EZ(t->active * 1000, T); - q->recover = EZ(t->recover * 1000, T); - q->cycle = EZ(t->cycle * 1000, T); - q->udma = EZ(t->udma * 1000, UT); + q->setup = EZ(t->setup * 1000, T); + q->act8b = EZ(t->act8b * 1000, T); + q->rec8b = EZ(t->rec8b * 1000, T); + q->cyc8b = EZ(t->cyc8b * 1000, T); + q->active = EZ(t->active * 1000, T); + q->recover = EZ(t->recover * 1000, T); + q->dmack_hold = EZ(t->dmack_hold * 1000, T); + q->cycle = EZ(t->cycle * 1000, T); + q->udma = EZ(t->udma * 1000, UT); } void ata_timing_merge(const struct ata_timing *a, const struct ata_timing *b, @@ -3084,6 +3085,7 @@ void ata_timing_merge(const struct ata_timing *a, const struct ata_timing *b, if (what & ATA_TIMING_CYC8B ) m->cyc8b = max(a->cyc8b, b->cyc8b); if (what & ATA_TIMING_ACTIVE ) m->active = max(a->active, b->active); if (what & ATA_TIMING_RECOVER) m->recover = max(a->recover, b->recover); + if (what & ATA_TIMING_DMACK_HOLD) m->dmack_hold = max(a->dmack_hold, b->dmack_hold); if (what & ATA_TIMING_CYCLE ) m->cycle = max(a->cycle, b->cycle); if (what & ATA_TIMING_UDMA ) m->udma = max(a->udma, b->udma); } diff --git a/include/linux/libata.h b/include/linux/libata.h index b6b8a7f..9c308b4 100644 --- a/include/linux/libata.h +++ b/include/linux/libata.h @@ -401,12 +401,14 @@ enum { ATA_TIMING_CYC8B, ATA_TIMING_ACTIVE = (1 << 4), ATA_TIMING_RECOVER = (1 << 5), - ATA_TIMING_CYCLE = (1 << 6), - ATA_TIMING_UDMA = (1 << 7), + ATA_TIMING_DMACK_HOLD = (1 << 6), + ATA_TIMING_CYCLE = (1 << 7), + ATA_TIMING_UDMA = (1 << 8), ATA_TIMING_ALL = ATA_TIMING_SETUP | ATA_TIMING_ACT8B | ATA_TIMING_REC8B | ATA_TIMING_CYC8B | ATA_TIMING_ACTIVE | ATA_TIMING_RECOVER | - ATA_TIMING_CYCLE | ATA_TIMING_UDMA, + ATA_TIMING_DMACK_HOLD | ATA_TIMING_CYCLE | + ATA_TIMING_UDMA, }; enum ata_xfer_mask { @@ -866,6 +868,7 @@ struct ata_timing { unsigned short cyc8b; /* t0 for 8-bit I/O */ unsigned short active; /* t2 or tD */ unsigned short recover; /* t2i or tK */ + unsigned short dmack_hold; /* tj */ unsigned short cycle; /* t0 */ unsigned short udma; /* t2CYCTYP/2 */ }; -- 1.5.6.6 From David.Daney@caviumnetworks.com Thu Jan 15 20:58:30 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 15 Jan 2009 20:58:33 +0000 (GMT) Received: from mail3.caviumnetworks.com ([12.108.191.235]:40615 "EHLO mail3.caviumnetworks.com") by ftp.linux-mips.org with ESMTP id S21365972AbZAOU6N (ORCPT ); Thu, 15 Jan 2009 20:58:13 +0000 Received: from exch4.caveonetworks.com (Not Verified[192.168.16.23]) by mail3.caviumnetworks.com with MailMarshal (v6,2,2,3503) id ; Thu, 15 Jan 2009 15:57:59 -0500 Received: from exch4.caveonetworks.com ([192.168.16.23]) by exch4.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Thu, 15 Jan 2009 12:57:38 -0800 Received: from dd1.caveonetworks.com ([64.169.86.201]) by exch4.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Thu, 15 Jan 2009 12:57:38 -0800 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.2/8.14.2) with ESMTP id n0FKvXSv016260; Thu, 15 Jan 2009 12:57:33 -0800 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.2/8.14.2/Submit) id n0FKvX9K016259; Thu, 15 Jan 2009 12:57:33 -0800 From: David Daney To: linux-ide@vger.kernel.org Cc: linux-mips@linux-mips.org, David Daney Subject: [PATCH 2/2] libata: New driver for OCTEON SOC Compact Flash interface (v6). Date: Thu, 15 Jan 2009 12:57:33 -0800 Message-Id: <1232053053-16232-2-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.5.6.6 In-Reply-To: <496FA2E9.9030403@caviumnetworks.com> References: <496FA2E9.9030403@caviumnetworks.com> X-OriginalArrivalTime: 15 Jan 2009 20:57:38.0111 (UTC) FILETIME=[E5F9BCF0:01C97753] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21763 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Content-Length: 28021 Lines: 1018 Cavium OCTEON processor support was recently merged, so now we have this CF driver for your consideration. Most OCTEON variants have *no* DMA or interrupt support on the CF interface so for these, only PIO is supported. Although if DMA is available, we do take advantage of it. This sixth version is essentially unchanged from the previous. Other than this patch commentary, I changed the type of several local variables from 'unsigned int' to 'int' Thanks, Signed-off-by: David Daney --- drivers/ata/Kconfig | 9 + drivers/ata/Makefile | 1 + drivers/ata/pata_octeon_cf.c | 956 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 966 insertions(+), 0 deletions(-) create mode 100644 drivers/ata/pata_octeon_cf.c diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig index 1a7be96..503a908 100644 --- a/drivers/ata/Kconfig +++ b/drivers/ata/Kconfig @@ -698,6 +698,15 @@ config PATA_IXP4XX_CF If unsure, say N. +config PATA_OCTEON_CF + tristate "OCTEON Boot Bus Compact Flash support" + depends on CPU_CAVIUM_OCTEON + help + This option enables a polled compact flash driver for use with + compact flash cards attached to the OCTEON boot bus. + + If unsure, say N. + config PATA_SCC tristate "Toshiba's Cell Reference Set IDE support" depends on PCI && PPC_CELLEB diff --git a/drivers/ata/Makefile b/drivers/ata/Makefile index 674965f..7f1ecf9 100644 --- a/drivers/ata/Makefile +++ b/drivers/ata/Makefile @@ -69,6 +69,7 @@ obj-$(CONFIG_PATA_IXP4XX_CF) += pata_ixp4xx_cf.o obj-$(CONFIG_PATA_SCC) += pata_scc.o obj-$(CONFIG_PATA_SCH) += pata_sch.o obj-$(CONFIG_PATA_BF54X) += pata_bf54x.o +obj-$(CONFIG_PATA_OCTEON_CF) += pata_octeon_cf.o obj-$(CONFIG_PATA_PLATFORM) += pata_platform.o obj-$(CONFIG_PATA_OF_PLATFORM) += pata_of_platform.o obj-$(CONFIG_PATA_ICSIDE) += pata_icside.o diff --git a/drivers/ata/pata_octeon_cf.c b/drivers/ata/pata_octeon_cf.c new file mode 100644 index 0000000..a7afa85 --- /dev/null +++ b/drivers/ata/pata_octeon_cf.c @@ -0,0 +1,956 @@ +/* + * Driver for the Octeon bootbus compact flash. + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2005-2008 Cavium Networks + * Copyright (C) 2008 Wind River Systems + */ + +#include +#include +#include +#include +#include +#include +#include + +#include + +/* + * The Octeon bootbus compact flash interface is connected in at least + * 3 different configurations on various evaluation boards: + * + * -- 8 bits no irq, no DMA + * -- 16 bits no irq, no DMA + * -- 16 bits True IDE mode with DMA, but no irq. + * + * In the last case the DMA engine can generate an interrupt when the + * transfer is complete. For the first two cases only PIO is supported. + * + */ + +#define DRV_NAME "pata_octeon_cf" +#define DRV_VERSION "2.1" + + +struct octeon_cf_port { + struct workqueue_struct *wq; + struct delayed_work delayed_finish; + struct ata_port *ap; + int dma_finished; +}; + +static struct scsi_host_template octeon_cf_sht = { + ATA_PIO_SHT(DRV_NAME), +}; + +/** + * Convert nanosecond based time to setting used in the + * boot bus timing register, based on timing multiple + */ +static unsigned int ns_to_tim_reg(unsigned int tim_mult, unsigned int nsecs) +{ + unsigned int val; + + /* + * Compute # of eclock periods to get desired duration in + * nanoseconds. + */ + val = DIV_ROUND_UP(nsecs * (octeon_get_clock_rate() / 1000000), + 1000 * tim_mult); + + return val; +} + +static void octeon_cf_set_boot_reg_cfg(int cs) +{ + union cvmx_mio_boot_reg_cfgx reg_cfg; + reg_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs)); + reg_cfg.s.dmack = 0; /* Don't assert DMACK on access */ + reg_cfg.s.tim_mult = 2; /* Timing mutiplier 2x */ + reg_cfg.s.rd_dly = 0; /* Sample on falling edge of BOOT_OE */ + reg_cfg.s.sam = 0; /* Don't combine write and output enable */ + reg_cfg.s.we_ext = 0; /* No write enable extension */ + reg_cfg.s.oe_ext = 0; /* No read enable extension */ + reg_cfg.s.en = 1; /* Enable this region */ + reg_cfg.s.orbit = 0; /* Don't combine with previos region */ + reg_cfg.s.ale = 0; /* Don't do address multiplexing */ + cvmx_write_csr(CVMX_MIO_BOOT_REG_CFGX(cs), reg_cfg.u64); +} + +/** + * Called after libata determines the needed PIO mode. This + * function programs the Octeon bootbus regions to support the + * timing requirements of the PIO mode. + * + * @ap: ATA port information + * @dev: ATA device + */ +static void octeon_cf_set_piomode(struct ata_port *ap, struct ata_device *dev) +{ + struct octeon_cf_data *ocd = ap->dev->platform_data; + union cvmx_mio_boot_reg_timx reg_tim; + int cs = ocd->base_region; + int T; + struct ata_timing timing; + + int use_iordy; + int trh; + int pause; + /* These names are timing parameters from the ATA spec */ + int t1; + int t2; + int t2i; + + T = (int)(2000000000000LL / octeon_get_clock_rate()); + + if (ata_timing_compute(dev, dev->pio_mode, &timing, T, T)) + BUG(); + + t1 = timing.setup; + if (t1) + t1--; + t2 = timing.active; + if (t2) + t2--; + t2i = timing.act8b; + if (t2i) + t2i--; + + trh = ns_to_tim_reg(2, 20); + if (trh) + trh--; + + pause = timing.cycle - timing.active - timing.setup - trh; + if (pause) + pause--; + + octeon_cf_set_boot_reg_cfg(cs); + if (ocd->dma_engine >= 0) + /* True IDE mode, program both chip selects. */ + octeon_cf_set_boot_reg_cfg(cs + 1); + + + use_iordy = ata_pio_need_iordy(dev); + + reg_tim.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_TIMX(cs)); + /* Disable page mode */ + reg_tim.s.pagem = 0; + /* Enable dynamic timing */ + reg_tim.s.waitm = use_iordy; + /* Pages are disabled */ + reg_tim.s.pages = 0; + /* We don't use multiplexed address mode */ + reg_tim.s.ale = 0; + /* Not used */ + reg_tim.s.page = 0; + /* Time after IORDY to coninue to assert the data */ + reg_tim.s.wait = 0; + /* Time to wait to complete the cycle. */ + reg_tim.s.pause = pause; + /* How long to hold after a write to de-assert CE. */ + reg_tim.s.wr_hld = trh; + /* How long to wait after a read to de-assert CE. */ + reg_tim.s.rd_hld = trh; + /* How long write enable is asserted */ + reg_tim.s.we = t2; + /* How long read enable is asserted */ + reg_tim.s.oe = t2; + /* Time after CE that read/write starts */ + reg_tim.s.ce = ns_to_tim_reg(2, 5); + /* Time before CE that address is valid */ + reg_tim.s.adr = 0; + + /* Program the bootbus region timing for the data port chip select. */ + cvmx_write_csr(CVMX_MIO_BOOT_REG_TIMX(cs), reg_tim.u64); + if (ocd->dma_engine >= 0) + /* True IDE mode, program both chip selects. */ + cvmx_write_csr(CVMX_MIO_BOOT_REG_TIMX(cs + 1), reg_tim.u64); +} + +static void octeon_cf_set_dmamode(struct ata_port *ap, struct ata_device *dev) +{ + struct octeon_cf_data *ocd = dev->link->ap->dev->platform_data; + union cvmx_mio_boot_dma_timx dma_tim; + unsigned int oe_a; + unsigned int oe_n; + unsigned int dma_ackh; + unsigned int dma_arq; + unsigned int pause; + unsigned int T0, Tkr, Td; + unsigned int tim_mult; + + const struct ata_timing *timing; + + timing = ata_timing_find_mode(dev->dma_mode); + T0 = timing->cycle; + Td = timing->active; + Tkr = timing->recover; + dma_ackh = timing->dmack_hold; + + dma_tim.u64 = 0; + /* dma_tim.s.tim_mult = 0 --> 4x */ + tim_mult = 4; + + /* not spec'ed, value in eclocks, not affected by tim_mult */ + dma_arq = 8; + pause = 25 - dma_arq * 1000 / + (octeon_get_clock_rate() / 1000000); /* Tz */ + + oe_a = Td; + /* Tkr from cf spec, lengthened to meet T0 */ + oe_n = max(T0 - oe_a, Tkr); + + dma_tim.s.dmack_pi = 1; + + dma_tim.s.oe_n = ns_to_tim_reg(tim_mult, oe_n); + dma_tim.s.oe_a = ns_to_tim_reg(tim_mult, oe_a); + + /* + * This is tI, C.F. spec. says 0, but Sony CF card requires + * more, we use 20 nS. + */ + dma_tim.s.dmack_s = ns_to_tim_reg(tim_mult, 20);; + dma_tim.s.dmack_h = ns_to_tim_reg(tim_mult, dma_ackh); + + dma_tim.s.dmarq = dma_arq; + dma_tim.s.pause = ns_to_tim_reg(tim_mult, pause); + + dma_tim.s.rd_dly = 0; /* Sample right on edge */ + + /* writes only */ + dma_tim.s.we_n = ns_to_tim_reg(tim_mult, oe_n); + dma_tim.s.we_a = ns_to_tim_reg(tim_mult, oe_a); + + pr_debug("ns to ticks (mult %d) of %d is: %d\n", tim_mult, 60, + ns_to_tim_reg(tim_mult, 60)); + pr_debug("oe_n: %d, oe_a: %d, dmack_s: %d, dmack_h: " + "%d, dmarq: %d, pause: %d\n", + dma_tim.s.oe_n, dma_tim.s.oe_a, dma_tim.s.dmack_s, + dma_tim.s.dmack_h, dma_tim.s.dmarq, dma_tim.s.pause); + + cvmx_write_csr(CVMX_MIO_BOOT_DMA_TIMX(ocd->dma_engine), + dma_tim.u64); + +} + +/** + * Handle an 8 bit I/O request. + * + * @dev: Device to access + * @buffer: Data buffer + * @buflen: Length of the buffer. + * @rw: True to write. + */ +static unsigned int octeon_cf_data_xfer8(struct ata_device *dev, + unsigned char *buffer, + unsigned int buflen, + int rw) +{ + struct ata_port *ap = dev->link->ap; + void __iomem *data_addr = ap->ioaddr.data_addr; + unsigned long words; + int count; + + words = buflen; + if (rw) { + count = 16; + while (words--) { + iowrite8(*buffer, data_addr); + buffer++; + /* + * Every 16 writes do a read so the bootbus + * FIFO doesn't fill up. + */ + if (--count == 0) { + ioread8(ap->ioaddr.altstatus_addr); + count = 16; + } + } + } else { + ioread8_rep(data_addr, buffer, words); + } + return buflen; +} + +/** + * Handle a 16 bit I/O request. + * + * @dev: Device to access + * @buffer: Data buffer + * @buflen: Length of the buffer. + * @rw: True to write. + */ +static unsigned int octeon_cf_data_xfer16(struct ata_device *dev, + unsigned char *buffer, + unsigned int buflen, + int rw) +{ + struct ata_port *ap = dev->link->ap; + void __iomem *data_addr = ap->ioaddr.data_addr; + unsigned long words; + int count; + + words = buflen / 2; + if (rw) { + count = 16; + while (words--) { + iowrite16(*(uint16_t *)buffer, data_addr); + buffer += sizeof(uint16_t); + /* + * Every 16 writes do a read so the bootbus + * FIFO doesn't fill up. + */ + if (--count == 0) { + ioread8(ap->ioaddr.altstatus_addr); + count = 16; + } + } + } else { + while (words--) { + *(uint16_t *)buffer = ioread16(data_addr); + buffer += sizeof(uint16_t); + } + } + /* Transfer trailing 1 byte, if any. */ + if (unlikely(buflen & 0x01)) { + __le16 align_buf[1] = { 0 }; + + if (rw == READ) { + align_buf[0] = cpu_to_le16(ioread16(data_addr)); + memcpy(buffer, align_buf, 1); + } else { + memcpy(align_buf, buffer, 1); + iowrite16(le16_to_cpu(align_buf[0]), data_addr); + } + words++; + } + return buflen; +} + +/** + * Read the taskfile for 16bit non-True IDE only. + */ +static void octeon_cf_tf_read16(struct ata_port *ap, struct ata_taskfile *tf) +{ + u16 blob; + /* The base of the registers is at ioaddr.data_addr. */ + void __iomem *base = ap->ioaddr.data_addr; + + blob = __raw_readw(base + 0xc); + tf->feature = blob >> 8; + + blob = __raw_readw(base + 2); + tf->nsect = blob & 0xff; + tf->lbal = blob >> 8; + + blob = __raw_readw(base + 4); + tf->lbam = blob & 0xff; + tf->lbah = blob >> 8; + + blob = __raw_readw(base + 6); + tf->device = blob & 0xff; + tf->command = blob >> 8; + + if (tf->flags & ATA_TFLAG_LBA48) { + if (likely(ap->ioaddr.ctl_addr)) { + iowrite8(tf->ctl | ATA_HOB, ap->ioaddr.ctl_addr); + + blob = __raw_readw(base + 0xc); + tf->hob_feature = blob >> 8; + + blob = __raw_readw(base + 2); + tf->hob_nsect = blob & 0xff; + tf->hob_lbal = blob >> 8; + + blob = __raw_readw(base + 4); + tf->hob_lbam = blob & 0xff; + tf->hob_lbah = blob >> 8; + + iowrite8(tf->ctl, ap->ioaddr.ctl_addr); + ap->last_ctl = tf->ctl; + } else { + WARN_ON(1); + } + } +} + +static u8 octeon_cf_check_status16(struct ata_port *ap) +{ + u16 blob; + void __iomem *base = ap->ioaddr.data_addr; + + blob = __raw_readw(base + 6); + return blob >> 8; +} + +static int octeon_cf_softreset16(struct ata_link *link, unsigned int *classes, + unsigned long deadline) +{ + struct ata_port *ap = link->ap; + void __iomem *base = ap->ioaddr.data_addr; + int rc; + u8 err; + + DPRINTK("about to softreset\n"); + __raw_writew(ap->ctl, base + 0xe); + udelay(20); + __raw_writew(ap->ctl | ATA_SRST, base + 0xe); + udelay(20); + __raw_writew(ap->ctl, base + 0xe); + + rc = ata_sff_wait_after_reset(link, 1, deadline); + if (rc) { + ata_link_printk(link, KERN_ERR, "SRST failed (errno=%d)\n", rc); + return rc; + } + + /* determine by signature whether we have ATA or ATAPI devices */ + classes[0] = ata_sff_dev_classify(&link->device[0], 1, &err); + DPRINTK("EXIT, classes[0]=%u [1]=%u\n", classes[0], classes[1]); + return 0; +} + +/** + * Load the taskfile for 16bit non-True IDE only. The device_addr is + * not loaded, we do this as part of octeon_cf_exec_command16. + */ +static void octeon_cf_tf_load16(struct ata_port *ap, + const struct ata_taskfile *tf) +{ + unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR; + /* The base of the registers is at ioaddr.data_addr. */ + void __iomem *base = ap->ioaddr.data_addr; + + if (tf->ctl != ap->last_ctl) { + iowrite8(tf->ctl, ap->ioaddr.ctl_addr); + ap->last_ctl = tf->ctl; + ata_wait_idle(ap); + } + if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) { + __raw_writew(tf->hob_feature << 8, base + 0xc); + __raw_writew(tf->hob_nsect | tf->hob_lbal << 8, base + 2); + __raw_writew(tf->hob_lbam | tf->hob_lbah << 8, base + 4); + VPRINTK("hob: feat 0x%X nsect 0x%X, lba 0x%X 0x%X 0x%X\n", + tf->hob_feature, + tf->hob_nsect, + tf->hob_lbal, + tf->hob_lbam, + tf->hob_lbah); + } + if (is_addr) { + __raw_writew(tf->feature << 8, base + 0xc); + __raw_writew(tf->nsect | tf->lbal << 8, base + 2); + __raw_writew(tf->lbam | tf->lbah << 8, base + 4); + VPRINTK("feat 0x%X nsect 0x%X, lba 0x%X 0x%X 0x%X\n", + tf->feature, + tf->nsect, + tf->lbal, + tf->lbam, + tf->lbah); + } + ata_wait_idle(ap); +} + + +static void octeon_cf_dev_select(struct ata_port *ap, unsigned int device) +{ +/* There is only one device, do nothing. */ + return; +} + +/* + * Issue ATA command to host controller. The device_addr is also sent + * as it must be written in a combined write with the command. + */ +static void octeon_cf_exec_command16(struct ata_port *ap, + const struct ata_taskfile *tf) +{ + /* The base of the registers is at ioaddr.data_addr. */ + void __iomem *base = ap->ioaddr.data_addr; + u16 blob; + + if (tf->flags & ATA_TFLAG_DEVICE) { + VPRINTK("device 0x%X\n", tf->device); + blob = tf->device; + } else { + blob = 0; + } + + DPRINTK("ata%u: cmd 0x%X\n", ap->print_id, tf->command); + blob |= (tf->command << 8); + __raw_writew(blob, base + 6); + + + ata_wait_idle(ap); +} + +static u8 octeon_cf_irq_on(struct ata_port *ap) +{ + return 0; +} + +static void octeon_cf_irq_clear(struct ata_port *ap) +{ + return; +} + +static void octeon_cf_dma_setup(struct ata_queued_cmd *qc) +{ + struct ata_port *ap = qc->ap; + struct octeon_cf_port *cf_port; + + cf_port = (struct octeon_cf_port *)ap->private_data; + DPRINTK("ENTER\n"); + /* issue r/w command */ + qc->cursg = qc->sg; + cf_port->dma_finished = 0; + ap->ops->sff_exec_command(ap, &qc->tf); + DPRINTK("EXIT\n"); +} + +/** + * Start a DMA transfer that was already setup + * + * @qc: Information about the DMA + */ +static void octeon_cf_dma_start(struct ata_queued_cmd *qc) +{ + struct octeon_cf_data *ocd = qc->ap->dev->platform_data; + union cvmx_mio_boot_dma_cfgx mio_boot_dma_cfg; + union cvmx_mio_boot_dma_intx mio_boot_dma_int; + struct scatterlist *sg; + + VPRINTK("%d scatterlists\n", qc->n_elem); + + /* Get the scatter list entry we need to DMA into */ + sg = qc->cursg; + BUG_ON(!sg); + + /* + * Clear the DMA complete status. + */ + mio_boot_dma_int.u64 = 0; + mio_boot_dma_int.s.done = 1; + cvmx_write_csr(CVMX_MIO_BOOT_DMA_INTX(ocd->dma_engine), + mio_boot_dma_int.u64); + + /* Enable the interrupt. */ + cvmx_write_csr(CVMX_MIO_BOOT_DMA_INT_ENX(ocd->dma_engine), + mio_boot_dma_int.u64); + + /* Set the direction of the DMA */ + mio_boot_dma_cfg.u64 = 0; + mio_boot_dma_cfg.s.en = 1; + mio_boot_dma_cfg.s.rw = ((qc->tf.flags & ATA_TFLAG_WRITE) != 0); + + /* + * Don't stop the DMA if the device deasserts DMARQ. Many + * compact flashes deassert DMARQ for a short time between + * sectors. Instead of stopping and restarting the DMA, we'll + * let the hardware do it. If the DMA is really stopped early + * due to an error condition, a later timeout will force us to + * stop. + */ + mio_boot_dma_cfg.s.clr = 0; + + /* Size is specified in 16bit words and minus one notation */ + mio_boot_dma_cfg.s.size = sg_dma_len(sg) / 2 - 1; + + /* We need to swap the high and low bytes of every 16 bits */ + mio_boot_dma_cfg.s.swap8 = 1; + + mio_boot_dma_cfg.s.adr = sg_dma_address(sg); + + VPRINTK("%s %d bytes address=%p\n", + (mio_boot_dma_cfg.s.rw) ? "write" : "read", sg->length, + (void *)(unsigned long)mio_boot_dma_cfg.s.adr); + + cvmx_write_csr(CVMX_MIO_BOOT_DMA_CFGX(ocd->dma_engine), + mio_boot_dma_cfg.u64); +} + +/** + * + * LOCKING: + * spin_lock_irqsave(host lock) + * + */ +static unsigned int octeon_cf_dma_finished(struct ata_port *ap, + struct ata_queued_cmd *qc) +{ + struct ata_eh_info *ehi = &ap->link.eh_info; + struct octeon_cf_data *ocd = ap->dev->platform_data; + union cvmx_mio_boot_dma_cfgx dma_cfg; + union cvmx_mio_boot_dma_intx dma_int; + struct octeon_cf_port *cf_port; + u8 status; + + VPRINTK("ata%u: protocol %d task_state %d\n", + ap->print_id, qc->tf.protocol, ap->hsm_task_state); + + + if (ap->hsm_task_state != HSM_ST_LAST) + return 0; + + cf_port = (struct octeon_cf_port *)ap->private_data; + + dma_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_DMA_CFGX(ocd->dma_engine)); + if (dma_cfg.s.size != 0xfffff) { + /* Error, the transfer was not complete. */ + qc->err_mask |= AC_ERR_HOST_BUS; + ap->hsm_task_state = HSM_ST_ERR; + } + + /* Stop and clear the dma engine. */ + dma_cfg.u64 = 0; + dma_cfg.s.size = -1; + cvmx_write_csr(CVMX_MIO_BOOT_DMA_CFGX(ocd->dma_engine), dma_cfg.u64); + + /* Disable the interrupt. */ + dma_int.u64 = 0; + cvmx_write_csr(CVMX_MIO_BOOT_DMA_INT_ENX(ocd->dma_engine), dma_int.u64); + + /* Clear the DMA complete status */ + dma_int.s.done = 1; + cvmx_write_csr(CVMX_MIO_BOOT_DMA_INTX(ocd->dma_engine), dma_int.u64); + + status = ap->ops->sff_check_status(ap); + + ata_sff_hsm_move(ap, qc, status, 0); + + if (unlikely(qc->err_mask) && (qc->tf.protocol == ATA_PROT_DMA)) + ata_ehi_push_desc(ehi, "DMA stat 0x%x", status); + + return 1; +} + +/* + * Check if any queued commands have more DMAs, if so start the next + * transfer, else do end of transfer handling. + */ +static irqreturn_t octeon_cf_interrupt(int irq, void *dev_instance) +{ + struct ata_host *host = dev_instance; + struct octeon_cf_port *cf_port; + int i; + unsigned int handled = 0; + unsigned long flags; + + spin_lock_irqsave(&host->lock, flags); + + DPRINTK("ENTER\n"); + for (i = 0; i < host->n_ports; i++) { + u8 status; + struct ata_port *ap; + struct ata_queued_cmd *qc; + union cvmx_mio_boot_dma_intx dma_int; + union cvmx_mio_boot_dma_cfgx dma_cfg; + struct octeon_cf_data *ocd; + + ap = host->ports[i]; + ocd = ap->dev->platform_data; + if (!ap || (ap->flags & ATA_FLAG_DISABLED)) + continue; + + ocd = ap->dev->platform_data; + cf_port = (struct octeon_cf_port *)ap->private_data; + dma_int.u64 = + cvmx_read_csr(CVMX_MIO_BOOT_DMA_INTX(ocd->dma_engine)); + dma_cfg.u64 = + cvmx_read_csr(CVMX_MIO_BOOT_DMA_CFGX(ocd->dma_engine)); + + qc = ata_qc_from_tag(ap, ap->link.active_tag); + + if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)) && + (qc->flags & ATA_QCFLAG_ACTIVE)) { + if (dma_int.s.done && !dma_cfg.s.en) { + if (!sg_is_last(qc->cursg)) { + qc->cursg = sg_next(qc->cursg); + handled = 1; + octeon_cf_dma_start(qc); + continue; + } else { + cf_port->dma_finished = 1; + } + } + if (!cf_port->dma_finished) + continue; + status = ioread8(ap->ioaddr.altstatus_addr); + if (status & (ATA_BUSY | ATA_DRQ)) { + /* + * We are busy, try to handle it + * later. This is the DMA finished + * interrupt, and it could take a + * little while for the card to be + * ready for more commands. + */ + /* Clear DMA irq. */ + dma_int.u64 = 0; + dma_int.s.done = 1; + cvmx_write_csr(CVMX_MIO_BOOT_DMA_INTX(ocd->dma_engine), + dma_int.u64); + + queue_delayed_work(cf_port->wq, + &cf_port->delayed_finish, 1); + handled = 1; + } else { + handled |= octeon_cf_dma_finished(ap, qc); + } + } + } + spin_unlock_irqrestore(&host->lock, flags); + DPRINTK("EXIT\n"); + return IRQ_RETVAL(handled); +} + +static void octeon_cf_delayed_finish(struct work_struct *work) +{ + struct octeon_cf_port *cf_port = container_of(work, + struct octeon_cf_port, + delayed_finish.work); + struct ata_port *ap = cf_port->ap; + struct ata_host *host = ap->host; + struct ata_queued_cmd *qc; + unsigned long flags; + u8 status; + + spin_lock_irqsave(&host->lock, flags); + + /* + * If the port is not waiting for completion, it must have + * handled it previously. The hsm_task_state is + * protected by host->lock. + */ + if (ap->hsm_task_state != HSM_ST_LAST || !cf_port->dma_finished) + goto out; + + status = ioread8(ap->ioaddr.altstatus_addr); + if (status & (ATA_BUSY | ATA_DRQ)) { + /* Still busy, try again. */ + queue_delayed_work(cf_port->wq, + &cf_port->delayed_finish, 1); + goto out; + } + qc = ata_qc_from_tag(ap, ap->link.active_tag); + if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)) && + (qc->flags & ATA_QCFLAG_ACTIVE)) + octeon_cf_dma_finished(ap, qc); +out: + spin_unlock_irqrestore(&host->lock, flags); +} + +static void octeon_cf_dev_config(struct ata_device *dev) +{ + /* + * A maximum of 2^20 - 1 16 bit transfers are possible with + * the bootbus DMA. So we need to throttle max_sectors to + * (2^12 - 1 == 4095) to assure that this can never happen. + */ + dev->max_sectors = min(dev->max_sectors, 4095U); +} + +/* + * Trap if driver tries to do standard bmdma commands. They are not + * supported. + */ +static void unreachable_qc(struct ata_queued_cmd *qc) +{ + BUG(); +} + +static u8 unreachable_port(struct ata_port *ap) +{ + BUG(); +} + +static unsigned int octeon_cf_qc_issue(struct ata_queued_cmd *qc) +{ + struct ata_port *ap = qc->ap; + + switch (qc->tf.protocol) { + case ATA_PROT_DMA: + WARN_ON(qc->tf.flags & ATA_TFLAG_POLLING); + + ap->ops->sff_tf_load(ap, &qc->tf); /* load tf registers */ + octeon_cf_dma_setup(qc); /* set up dma */ + octeon_cf_dma_start(qc); /* initiate dma */ + ap->hsm_task_state = HSM_ST_LAST; + break; + + case ATAPI_PROT_DMA: + dev_err(ap->dev, "Error, ATAPI not supported\n"); + BUG(); + + default: + return ata_sff_qc_issue(qc); + } + + return 0; +} + +static struct ata_port_operations octeon_cf_ops = { + .inherits = &ata_sff_port_ops, + .qc_prep = ata_noop_qc_prep, + .qc_issue = octeon_cf_qc_issue, + .sff_dev_select = octeon_cf_dev_select, + .sff_irq_on = octeon_cf_irq_on, + .sff_irq_clear = octeon_cf_irq_clear, + .bmdma_setup = unreachable_qc, + .bmdma_start = unreachable_qc, + .bmdma_stop = unreachable_qc, + .bmdma_status = unreachable_port, + .cable_detect = ata_cable_40wire, + .set_piomode = octeon_cf_set_piomode, + .set_dmamode = octeon_cf_set_dmamode, + .dev_config = octeon_cf_dev_config, +}; + +static int __devinit octeon_cf_probe(struct platform_device *pdev) +{ + struct resource *res_cs0, *res_cs1; + + void __iomem *cs0; + void __iomem *cs1 = NULL; + struct ata_host *host; + struct ata_port *ap; + struct octeon_cf_data *ocd; + int irq = 0; + irq_handler_t irq_handler = NULL; + void __iomem *base; + struct octeon_cf_port *cf_port; + + res_cs0 = platform_get_resource(pdev, IORESOURCE_MEM, 0); + + if (!res_cs0) + return -EINVAL; + + ocd = pdev->dev.platform_data; + + cs0 = devm_ioremap_nocache(&pdev->dev, res_cs0->start, + res_cs0->end - res_cs0->start + 1); + + if (!cs0) + return -ENOMEM; + + /* Determine from availability of DMA if True IDE mode or not */ + if (ocd->dma_engine >= 0) { + res_cs1 = platform_get_resource(pdev, IORESOURCE_MEM, 1); + if (!res_cs1) + return -EINVAL; + + cs1 = devm_ioremap_nocache(&pdev->dev, res_cs1->start, + res_cs0->end - res_cs1->start + 1); + + if (!cs1) + return -ENOMEM; + } + + cf_port = kzalloc(sizeof(*cf_port), GFP_KERNEL); + if (!cf_port) + return -ENOMEM; + + /* allocate host */ + host = ata_host_alloc(&pdev->dev, 1); + if (!host) + goto free_cf_port; + + ap = host->ports[0]; + ap->private_data = cf_port; + cf_port->ap = ap; + ap->ops = &octeon_cf_ops; + ap->pio_mask = 0x7f; /* Support PIO 0-6 */ + ap->flags |= ATA_FLAG_MMIO | ATA_FLAG_NO_LEGACY + | ATA_FLAG_NO_ATAPI | ATA_FLAG_PIO_POLLING; + + base = cs0 + ocd->base_region_bias; + if (!ocd->is16bit) { + ap->ioaddr.cmd_addr = base; + ata_sff_std_ports(&ap->ioaddr); + + ap->ioaddr.altstatus_addr = base + 0xe; + ap->ioaddr.ctl_addr = base + 0xe; + octeon_cf_ops.sff_data_xfer = octeon_cf_data_xfer8; + } else if (cs1) { + /* Presence of cs1 indicates True IDE mode. */ + ap->ioaddr.cmd_addr = base + (ATA_REG_CMD << 1) + 1; + ap->ioaddr.data_addr = base + (ATA_REG_DATA << 1); + ap->ioaddr.error_addr = base + (ATA_REG_ERR << 1) + 1; + ap->ioaddr.feature_addr = base + (ATA_REG_FEATURE << 1) + 1; + ap->ioaddr.nsect_addr = base + (ATA_REG_NSECT << 1) + 1; + ap->ioaddr.lbal_addr = base + (ATA_REG_LBAL << 1) + 1; + ap->ioaddr.lbam_addr = base + (ATA_REG_LBAM << 1) + 1; + ap->ioaddr.lbah_addr = base + (ATA_REG_LBAH << 1) + 1; + ap->ioaddr.device_addr = base + (ATA_REG_DEVICE << 1) + 1; + ap->ioaddr.status_addr = base + (ATA_REG_STATUS << 1) + 1; + ap->ioaddr.command_addr = base + (ATA_REG_CMD << 1) + 1; + ap->ioaddr.altstatus_addr = cs1 + (6 << 1) + 1; + ap->ioaddr.ctl_addr = cs1 + (6 << 1) + 1; + octeon_cf_ops.sff_data_xfer = octeon_cf_data_xfer16; + + ap->mwdma_mask = 0x1f; /* Support MWDMA 0-4 */ + irq = platform_get_irq(pdev, 0); + irq_handler = octeon_cf_interrupt; + + /* True IDE mode needs delayed work to poll for not-busy. */ + cf_port->wq = create_singlethread_workqueue(DRV_NAME); + if (!cf_port->wq) + goto free_cf_port; + INIT_DELAYED_WORK(&cf_port->delayed_finish, + octeon_cf_delayed_finish); + + } else { + /* 16 bit but not True IDE */ + octeon_cf_ops.sff_data_xfer = octeon_cf_data_xfer16; + octeon_cf_ops.softreset = octeon_cf_softreset16; + octeon_cf_ops.sff_check_status = octeon_cf_check_status16; + octeon_cf_ops.sff_tf_read = octeon_cf_tf_read16; + octeon_cf_ops.sff_tf_load = octeon_cf_tf_load16; + octeon_cf_ops.sff_exec_command = octeon_cf_exec_command16; + + ap->ioaddr.data_addr = base + ATA_REG_DATA; + ap->ioaddr.nsect_addr = base + ATA_REG_NSECT; + ap->ioaddr.lbal_addr = base + ATA_REG_LBAL; + ap->ioaddr.ctl_addr = base + 0xe; + ap->ioaddr.altstatus_addr = base + 0xe; + } + + ata_port_desc(ap, "cmd %p ctl %p", base, ap->ioaddr.ctl_addr); + + + dev_info(&pdev->dev, "version " DRV_VERSION" %d bit%s.\n", + (ocd->is16bit) ? 16 : 8, + (cs1) ? ", True IDE" : ""); + + + return ata_host_activate(host, irq, irq_handler, 0, &octeon_cf_sht); + +free_cf_port: + kfree(cf_port); + return -ENOMEM; +} + +static struct platform_driver octeon_cf_driver = { + .probe = octeon_cf_probe, + .driver = { + .name = DRV_NAME, + .owner = THIS_MODULE, + }, +}; + +static int __init octeon_cf_init(void) +{ + return platform_driver_register(&octeon_cf_driver); +} + + +MODULE_AUTHOR("David Daney "); +MODULE_DESCRIPTION("low-level driver for Cavium OCTEON Compact Flash PATA"); +MODULE_LICENSE("GPL"); +MODULE_VERSION(DRV_VERSION); +MODULE_ALIAS("platform:" DRV_NAME); + +module_init(octeon_cf_init); -- 1.5.6.6 From mano@roarinelk.homelinux.net Thu Jan 15 21:00:07 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 15 Jan 2009 21:00:11 +0000 (GMT) Received: from fnoeppeil36.netpark.at ([217.175.205.164]:51682 "EHLO roarinelk.homelinux.net") by ftp.linux-mips.org with ESMTP id S21365976AbZAOVAH (ORCPT ); Thu, 15 Jan 2009 21:00:07 +0000 Received: (qmail 9689 invoked by uid 1000); 15 Jan 2009 21:58:51 +0100 Date: Thu, 15 Jan 2009 21:58:51 +0100 From: Manuel Lauss To: Florian Fainelli Cc: ralf@linux-mips.org, Linux-MIPS Subject: Re: [PATCH] au1000: convert to using gpiolib Message-ID: <20090115205851.GD8656@roarinelk.homelinux.net> References: <200901151646.49591.florian@openwrt.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <200901151646.49591.florian@openwrt.org> User-Agent: Mutt/1.5.16 (2007-06-09) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21764 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mano@roarinelk.homelinux.net Precedence: bulk X-list: linux-mips Content-Length: 3903 Lines: 116 Hi Florian, On Thu, Jan 15, 2009 at 04:46:48PM +0100, Florian Fainelli wrote: > This patch converts the GPIO board code to use gpiolib Very nice; a few minor things though: > --- a/arch/mips/alchemy/common/gpio.c > +++ b/arch/mips/alchemy/common/gpio.c > -static void au1xxx_gpio2_write(unsigned gpio, int value) > +static void au1000_gpio2_set(struct gpio_chip *chip, > + unsigned offset, int value) > { > - gpio -= AU1XXX_GPIO_BASE; > + u32 mask = ((GPIO2_OUT_EN_MASK << offset) | (!!value << offset)); > + struct au1000_gpio_chip *gpch; > + unsigned long flags; > + > + gpch = container_of(chip, struct au1000_gpio_chip, chip); > > - gpio2->output = (GPIO2_OUTPUT_ENABLE_MASK << gpio) | ((!!value) << gpio); > + local_irq_save(flags); > + writel(mask, gpch->regbase + AU1000_GPIO2_OUT); > + local_irq_restore(flags); Because of the 'enable | value' scheme I believe you don't require any locking here. > +struct au1000_gpio_chip au1000_gpio_chip[] = { > + [0] = { > + .regbase = (void __iomem *)SYS_BASE, > + .chip = { > + .label = "au1000-gpio1", > + .direction_input = au1000_gpio1_direction_input, > + .direction_output = au1000_gpio1_direction_output, > + .get = au1000_gpio1_get, > + .set = au1000_gpio1_set, > + .base = 0, > + .ngpio = 32, > + }, > + }, > +#if !defined(CONFIG_SOC_AU1000) > + [1] = { > + .regbase = (void __iomem *)GPIO2_BASE, > + .chip = { > + .label = "au1000-gpio2", > + .direction_input = au1000_gpio2_direction_input, > + .direction_output = au1000_gpio2_direction_output, > + .get = au1000_gpio2_get, > + .set = au1000_gpio2_set, > + .base = AU1XXX_GPIO_BASE, > + .ngpio = 32, > + }, > + }, > #endif > - else > - return au1xxx_gpio1_read(gpio); > -} > -EXPORT_SYMBOL(au1xxx_gpio_get_value); > +}; [...] > +static int __init au1000_gpio_init(void) > { > - if (gpio >= AU1XXX_GPIO_BASE) > -#if defined(CONFIG_SOC_AU1000) > - ; > -#else > - au1xxx_gpio2_write(gpio, value); > -#endif > - else > - au1xxx_gpio1_write(gpio, value); > -} > -EXPORT_SYMBOL(au1xxx_gpio_set_value); > + gpiochip_add(&au1000_gpio_chip[0].chip); > +#if !defined(CONFIG_SOC_AU1000) > + gpiochip_add(&au1000_gpio_chip[1].chip); > [...] > +arch_initcall(au1000_gpio_init); Can you please make the gpiolib registration dependent on a CONFIG symbol? I.e. make the au1000_gpio{,2}_direction() and friends calls globally visible but let the individual boards decide whether they want to use the gpio numbering imposed by this patch. Long explanation: I maintain a number of modules with a common connector interface, based on different architectures (sh, mips and arm so far). I also maintain a few baseboards which can carry theese modules. Modules provide 16 gpios numbered 0-15, which are used by the baseboards. Since I need to keep the baseboard code free of arch-specific hacks, every module provides its own gpio-chip which distributes the gpio-lib calls to various on- and off-chip peripherals. On my alchemy board in particular, those 16 gpios are provided by a mixture of gpio1, gpio2 and FPGA based pins (yes I repeatedly moanoed to the hw guys about this but pin multiplexing and required features make a sane implementation difficult; but at least I was allowed to write the VHDL for the fpga-based gpios). If this explanation doesn't make sense I'll gladly whip up an addon patch. > diff --git a/arch/mips/include/asm/mach-au1x00/gpio.h b/arch/mips/include/asm/mach-au1x00/gpio.h > index 2dc61e0..34d9b72 100644 > --- a/arch/mips/include/asm/mach-au1x00/gpio.h > +++ b/arch/mips/include/asm/mach-au1x00/gpio.h > @@ -5,65 +5,29 @@ > > #define AU1XXX_GPIO_BASE 200 please change this to AU1XXX_GPIO2_BASE (it's the base number of the GPIO2 block pins after all) Thanks! Manuel Lauss From alan@lxorguk.ukuu.org.uk Thu Jan 15 21:13:19 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 15 Jan 2009 21:13:21 +0000 (GMT) Received: from earthlight.etchedpixels.co.uk ([81.2.110.250]:32722 "EHLO lxorguk.ukuu.org.uk") by ftp.linux-mips.org with ESMTP id S21365986AbZAOVNT (ORCPT ); Thu, 15 Jan 2009 21:13:19 +0000 Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by lxorguk.ukuu.org.uk (8.14.2/8.14.2) with ESMTP id n0FLDXxn029733; Thu, 15 Jan 2009 21:13:33 GMT Date: Thu, 15 Jan 2009 21:13:33 +0000 From: Alan Cox To: David Daney Cc: linux-ide@vger.kernel.org, linux-mips@linux-mips.org, David Daney Subject: Re: [PATCH 2/2] libata: New driver for OCTEON SOC Compact Flash interface (v6). Message-ID: <20090115211333.1440db46@lxorguk.ukuu.org.uk> In-Reply-To: <1232053053-16232-2-git-send-email-ddaney@caviumnetworks.com> References: <496FA2E9.9030403@caviumnetworks.com> <1232053053-16232-2-git-send-email-ddaney@caviumnetworks.com> X-Mailer: Claws Mail 3.5.0 (GTK+ 2.12.12; x86_64-redhat-linux-gnu) Organization: Red Hat UK Cyf., Amberley Place, 107-111 Peascod Street, Windsor, Berkshire, SL4 1TE, Y Deyrnas Gyfunol. Cofrestrwyd yng Nghymru a Lloegr o'r rhif cofrestru 3798903 Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21765 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: alan@lxorguk.ukuu.org.uk Precedence: bulk X-list: linux-mips Content-Length: 388 Lines: 15 > + reg_cfg.s.orbit = 0; /* Don't combine with previos region */ previous ... > +static unsigned int octeon_cf_qc_issue(struct ata_queued_cmd *qc) > + case ATAPI_PROT_DMA: > + dev_err(ap->dev, "Error, ATAPI not supported\n"); > + BUG(); Looks as if you should also have a check_atapi_dma function that always returns non zero (or a mode filter for atapi -> pio) Looks good to me. From David.Daney@caviumnetworks.com Fri Jan 16 01:45:56 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 16 Jan 2009 01:45:58 +0000 (GMT) Received: from mail3.caviumnetworks.com ([12.108.191.235]:2916 "EHLO mail3.caviumnetworks.com") by ftp.linux-mips.org with ESMTP id S21366010AbZAPBp4 (ORCPT ); Fri, 16 Jan 2009 01:45:56 +0000 Received: from exch4.caveonetworks.com (Not Verified[192.168.16.23]) by mail3.caviumnetworks.com with MailMarshal (v6,2,2,3503) id ; Thu, 15 Jan 2009 20:45:26 -0500 Received: from exch4.caveonetworks.com ([192.168.16.23]) by exch4.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Thu, 15 Jan 2009 17:44:27 -0800 Received: from dd1.caveonetworks.com ([64.169.86.201]) by exch4.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Thu, 15 Jan 2009 17:44:27 -0800 Message-ID: <496FE67B.9000509@caviumnetworks.com> Date: Thu, 15 Jan 2009 17:44:27 -0800 From: David Daney User-Agent: Thunderbird 2.0.0.19 (X11/20090105) MIME-Version: 1.0 To: IDE/ATA development list , linux-mips Subject: [PATCH 0/2] libata: Add OCTEON Compact Flash driver (v7). Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 16 Jan 2009 01:44:27.0094 (UTC) FILETIME=[F7542760:01C9777B] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21766 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Content-Length: 944 Lines: 28 Linus recently merged support for the mips/Octeon cpu. please consider adding this driver for the Compact Flash system present on many of the OCTEON development boards. Fixes from v6 as suggested by Alan Cox and described in patch 2/2. This is a two part patch set, the first part adds a new column to the ata_timing table (for dmack_hold). This is used by the second patch which is the driver itself. I will reply with the two patches. Thanks, David Daney (2): libata: Add another column to the ata_timing table. libata: New driver for OCTEON SOC Compact Flash interface (v7). drivers/ata/Kconfig | 9 + drivers/ata/Makefile | 1 + drivers/ata/libata-core.c | 72 ++-- drivers/ata/pata_octeon_cf.c | 965 ++++++++++++++++++++++++++++++++++++++++++ include/linux/libata.h | 9 +- 5 files changed, 1018 insertions(+), 38 deletions(-) create mode 100644 drivers/ata/pata_octeon_cf.c From David.Daney@caviumnetworks.com Fri Jan 16 01:46:34 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 16 Jan 2009 01:46:37 +0000 (GMT) Received: from mail3.caviumnetworks.com ([12.108.191.235]:48228 "EHLO mail3.caviumnetworks.com") by ftp.linux-mips.org with ESMTP id S21366010AbZAPBqe (ORCPT ); Fri, 16 Jan 2009 01:46:34 +0000 Received: from exch4.caveonetworks.com (Not Verified[192.168.16.23]) by mail3.caviumnetworks.com with MailMarshal (v6,2,2,3503) id ; Thu, 15 Jan 2009 20:46:27 -0500 Received: from exch4.caveonetworks.com ([192.168.16.23]) by exch4.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Thu, 15 Jan 2009 17:45:37 -0800 Received: from dd1.caveonetworks.com ([64.169.86.201]) by exch4.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Thu, 15 Jan 2009 17:45:37 -0800 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.2/8.14.2) with ESMTP id n0G1jWoq031187; Thu, 15 Jan 2009 17:45:32 -0800 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.2/8.14.2/Submit) id n0G1jW74031185; Thu, 15 Jan 2009 17:45:32 -0800 From: David Daney To: linux-ide@vger.kernel.org Cc: linux-mips@linux-mips.org, David Daney Subject: [PATCH 1/2] libata: Add another column to the ata_timing table. Date: Thu, 15 Jan 2009 17:45:31 -0800 Message-Id: <1232070332-31163-1-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.5.6.6 In-Reply-To: <496FE67B.9000509@caviumnetworks.com> References: <496FE67B.9000509@caviumnetworks.com> X-OriginalArrivalTime: 16 Jan 2009 01:45:37.0515 (UTC) FILETIME=[214D8BB0:01C9777C] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21767 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Content-Length: 6403 Lines: 141 The forthcoming OCTEON SOC Compact Flash driver needs an additional timing value that was not available in the ata_timing table. I add a new column for dmack_hold time. The values were obtained from the Compact Flash specification Rev 4.1. Signed-off-by: David Daney --- drivers/ata/libata-core.c | 72 +++++++++++++++++++++++---------------------- include/linux/libata.h | 9 ++++-- 2 files changed, 43 insertions(+), 38 deletions(-) diff --git a/drivers/ata/libata-core.c b/drivers/ata/libata-core.c index 71218d7..8fe0012 100644 --- a/drivers/ata/libata-core.c +++ b/drivers/ata/libata-core.c @@ -3029,33 +3029,33 @@ int sata_set_spd(struct ata_link *link) */ static const struct ata_timing ata_timing[] = { -/* { XFER_PIO_SLOW, 120, 290, 240, 960, 290, 240, 960, 0 }, */ - { XFER_PIO_0, 70, 290, 240, 600, 165, 150, 600, 0 }, - { XFER_PIO_1, 50, 290, 93, 383, 125, 100, 383, 0 }, - { XFER_PIO_2, 30, 290, 40, 330, 100, 90, 240, 0 }, - { XFER_PIO_3, 30, 80, 70, 180, 80, 70, 180, 0 }, - { XFER_PIO_4, 25, 70, 25, 120, 70, 25, 120, 0 }, - { XFER_PIO_5, 15, 65, 25, 100, 65, 25, 100, 0 }, - { XFER_PIO_6, 10, 55, 20, 80, 55, 20, 80, 0 }, - - { XFER_SW_DMA_0, 120, 0, 0, 0, 480, 480, 960, 0 }, - { XFER_SW_DMA_1, 90, 0, 0, 0, 240, 240, 480, 0 }, - { XFER_SW_DMA_2, 60, 0, 0, 0, 120, 120, 240, 0 }, - - { XFER_MW_DMA_0, 60, 0, 0, 0, 215, 215, 480, 0 }, - { XFER_MW_DMA_1, 45, 0, 0, 0, 80, 50, 150, 0 }, - { XFER_MW_DMA_2, 25, 0, 0, 0, 70, 25, 120, 0 }, - { XFER_MW_DMA_3, 25, 0, 0, 0, 65, 25, 100, 0 }, - { XFER_MW_DMA_4, 25, 0, 0, 0, 55, 20, 80, 0 }, - -/* { XFER_UDMA_SLOW, 0, 0, 0, 0, 0, 0, 0, 150 }, */ - { XFER_UDMA_0, 0, 0, 0, 0, 0, 0, 0, 120 }, - { XFER_UDMA_1, 0, 0, 0, 0, 0, 0, 0, 80 }, - { XFER_UDMA_2, 0, 0, 0, 0, 0, 0, 0, 60 }, - { XFER_UDMA_3, 0, 0, 0, 0, 0, 0, 0, 45 }, - { XFER_UDMA_4, 0, 0, 0, 0, 0, 0, 0, 30 }, - { XFER_UDMA_5, 0, 0, 0, 0, 0, 0, 0, 20 }, - { XFER_UDMA_6, 0, 0, 0, 0, 0, 0, 0, 15 }, +/* { XFER_PIO_SLOW, 120, 290, 240, 960, 290, 240, 0, 960, 0 }, */ + { XFER_PIO_0, 70, 290, 240, 600, 165, 150, 0, 600, 0 }, + { XFER_PIO_1, 50, 290, 93, 383, 125, 100, 0, 383, 0 }, + { XFER_PIO_2, 30, 290, 40, 330, 100, 90, 0, 240, 0 }, + { XFER_PIO_3, 30, 80, 70, 180, 80, 70, 0, 180, 0 }, + { XFER_PIO_4, 25, 70, 25, 120, 70, 25, 0, 120, 0 }, + { XFER_PIO_5, 15, 65, 25, 100, 65, 25, 0, 100, 0 }, + { XFER_PIO_6, 10, 55, 20, 80, 55, 20, 0, 80, 0 }, + + { XFER_SW_DMA_0, 120, 0, 0, 0, 480, 480, 50, 960, 0 }, + { XFER_SW_DMA_1, 90, 0, 0, 0, 240, 240, 30, 480, 0 }, + { XFER_SW_DMA_2, 60, 0, 0, 0, 120, 120, 20, 240, 0 }, + + { XFER_MW_DMA_0, 60, 0, 0, 0, 215, 215, 20, 480, 0 }, + { XFER_MW_DMA_1, 45, 0, 0, 0, 80, 50, 5, 150, 0 }, + { XFER_MW_DMA_2, 25, 0, 0, 0, 70, 25, 5, 120, 0 }, + { XFER_MW_DMA_3, 25, 0, 0, 0, 65, 25, 5, 100, 0 }, + { XFER_MW_DMA_4, 25, 0, 0, 0, 55, 20, 5, 80, 0 }, + +/* { XFER_UDMA_SLOW, 0, 0, 0, 0, 0, 0, 0, 0, 150 }, */ + { XFER_UDMA_0, 0, 0, 0, 0, 0, 0, 0, 0, 120 }, + { XFER_UDMA_1, 0, 0, 0, 0, 0, 0, 0, 0, 80 }, + { XFER_UDMA_2, 0, 0, 0, 0, 0, 0, 0, 0, 60 }, + { XFER_UDMA_3, 0, 0, 0, 0, 0, 0, 0, 0, 45 }, + { XFER_UDMA_4, 0, 0, 0, 0, 0, 0, 0, 0, 30 }, + { XFER_UDMA_5, 0, 0, 0, 0, 0, 0, 0, 0, 20 }, + { XFER_UDMA_6, 0, 0, 0, 0, 0, 0, 0, 0, 15 }, { 0xFF } }; @@ -3065,14 +3065,15 @@ static const struct ata_timing ata_timing[] = { static void ata_timing_quantize(const struct ata_timing *t, struct ata_timing *q, int T, int UT) { - q->setup = EZ(t->setup * 1000, T); - q->act8b = EZ(t->act8b * 1000, T); - q->rec8b = EZ(t->rec8b * 1000, T); - q->cyc8b = EZ(t->cyc8b * 1000, T); - q->active = EZ(t->active * 1000, T); - q->recover = EZ(t->recover * 1000, T); - q->cycle = EZ(t->cycle * 1000, T); - q->udma = EZ(t->udma * 1000, UT); + q->setup = EZ(t->setup * 1000, T); + q->act8b = EZ(t->act8b * 1000, T); + q->rec8b = EZ(t->rec8b * 1000, T); + q->cyc8b = EZ(t->cyc8b * 1000, T); + q->active = EZ(t->active * 1000, T); + q->recover = EZ(t->recover * 1000, T); + q->dmack_hold = EZ(t->dmack_hold * 1000, T); + q->cycle = EZ(t->cycle * 1000, T); + q->udma = EZ(t->udma * 1000, UT); } void ata_timing_merge(const struct ata_timing *a, const struct ata_timing *b, @@ -3084,6 +3085,7 @@ void ata_timing_merge(const struct ata_timing *a, const struct ata_timing *b, if (what & ATA_TIMING_CYC8B ) m->cyc8b = max(a->cyc8b, b->cyc8b); if (what & ATA_TIMING_ACTIVE ) m->active = max(a->active, b->active); if (what & ATA_TIMING_RECOVER) m->recover = max(a->recover, b->recover); + if (what & ATA_TIMING_DMACK_HOLD) m->dmack_hold = max(a->dmack_hold, b->dmack_hold); if (what & ATA_TIMING_CYCLE ) m->cycle = max(a->cycle, b->cycle); if (what & ATA_TIMING_UDMA ) m->udma = max(a->udma, b->udma); } diff --git a/include/linux/libata.h b/include/linux/libata.h index b6b8a7f..9c308b4 100644 --- a/include/linux/libata.h +++ b/include/linux/libata.h @@ -401,12 +401,14 @@ enum { ATA_TIMING_CYC8B, ATA_TIMING_ACTIVE = (1 << 4), ATA_TIMING_RECOVER = (1 << 5), - ATA_TIMING_CYCLE = (1 << 6), - ATA_TIMING_UDMA = (1 << 7), + ATA_TIMING_DMACK_HOLD = (1 << 6), + ATA_TIMING_CYCLE = (1 << 7), + ATA_TIMING_UDMA = (1 << 8), ATA_TIMING_ALL = ATA_TIMING_SETUP | ATA_TIMING_ACT8B | ATA_TIMING_REC8B | ATA_TIMING_CYC8B | ATA_TIMING_ACTIVE | ATA_TIMING_RECOVER | - ATA_TIMING_CYCLE | ATA_TIMING_UDMA, + ATA_TIMING_DMACK_HOLD | ATA_TIMING_CYCLE | + ATA_TIMING_UDMA, }; enum ata_xfer_mask { @@ -866,6 +868,7 @@ struct ata_timing { unsigned short cyc8b; /* t0 for 8-bit I/O */ unsigned short active; /* t2 or tD */ unsigned short recover; /* t2i or tK */ + unsigned short dmack_hold; /* tj */ unsigned short cycle; /* t0 */ unsigned short udma; /* t2CYCTYP/2 */ }; -- 1.5.6.6 From David.Daney@caviumnetworks.com Fri Jan 16 01:46:54 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 16 Jan 2009 01:46:57 +0000 (GMT) Received: from mail3.caviumnetworks.com ([12.108.191.235]:50020 "EHLO mail3.caviumnetworks.com") by ftp.linux-mips.org with ESMTP id S21366013AbZAPBqg (ORCPT ); Fri, 16 Jan 2009 01:46:36 +0000 Received: from exch4.caveonetworks.com (Not Verified[192.168.16.23]) by mail3.caviumnetworks.com with MailMarshal (v6,2,2,3503) id ; Thu, 15 Jan 2009 20:46:27 -0500 Received: from exch4.caveonetworks.com ([192.168.16.23]) by exch4.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Thu, 15 Jan 2009 17:45:37 -0800 Received: from dd1.caveonetworks.com ([64.169.86.201]) by exch4.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Thu, 15 Jan 2009 17:45:37 -0800 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.2/8.14.2) with ESMTP id n0G1jXdt031191; Thu, 15 Jan 2009 17:45:33 -0800 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.2/8.14.2/Submit) id n0G1jXW4031190; Thu, 15 Jan 2009 17:45:33 -0800 From: David Daney To: linux-ide@vger.kernel.org Cc: linux-mips@linux-mips.org, David Daney Subject: [PATCH 2/2] libata: New driver for OCTEON SOC Compact Flash interface (v7). Date: Thu, 15 Jan 2009 17:45:32 -0800 Message-Id: <1232070332-31163-2-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.5.6.6 In-Reply-To: <496FE67B.9000509@caviumnetworks.com> References: <496FE67B.9000509@caviumnetworks.com> X-OriginalArrivalTime: 16 Jan 2009 01:45:37.0577 (UTC) FILETIME=[21570190:01C9777C] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21768 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Content-Length: 28209 Lines: 1031 Cavium OCTEON processor support was recently merged, so now we have this CF driver for your consideration. Most OCTEON variants have *no* DMA or interrupt support on the CF interface so for these, only PIO is supported. Although if DMA is available, we do take advantage of it. Signed-off-by: David Daney --- Differences from previous version (v6): 1) Spelling fixes in comments. 2) Added check_atapi_dma handler to the port operations. Both changes as suggested by Alan Cox. drivers/ata/Kconfig | 9 + drivers/ata/Makefile | 1 + drivers/ata/pata_octeon_cf.c | 965 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 975 insertions(+), 0 deletions(-) create mode 100644 drivers/ata/pata_octeon_cf.c diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig index 1a7be96..503a908 100644 --- a/drivers/ata/Kconfig +++ b/drivers/ata/Kconfig @@ -698,6 +698,15 @@ config PATA_IXP4XX_CF If unsure, say N. +config PATA_OCTEON_CF + tristate "OCTEON Boot Bus Compact Flash support" + depends on CPU_CAVIUM_OCTEON + help + This option enables a polled compact flash driver for use with + compact flash cards attached to the OCTEON boot bus. + + If unsure, say N. + config PATA_SCC tristate "Toshiba's Cell Reference Set IDE support" depends on PCI && PPC_CELLEB diff --git a/drivers/ata/Makefile b/drivers/ata/Makefile index 674965f..7f1ecf9 100644 --- a/drivers/ata/Makefile +++ b/drivers/ata/Makefile @@ -69,6 +69,7 @@ obj-$(CONFIG_PATA_IXP4XX_CF) += pata_ixp4xx_cf.o obj-$(CONFIG_PATA_SCC) += pata_scc.o obj-$(CONFIG_PATA_SCH) += pata_sch.o obj-$(CONFIG_PATA_BF54X) += pata_bf54x.o +obj-$(CONFIG_PATA_OCTEON_CF) += pata_octeon_cf.o obj-$(CONFIG_PATA_PLATFORM) += pata_platform.o obj-$(CONFIG_PATA_OF_PLATFORM) += pata_of_platform.o obj-$(CONFIG_PATA_ICSIDE) += pata_icside.o diff --git a/drivers/ata/pata_octeon_cf.c b/drivers/ata/pata_octeon_cf.c new file mode 100644 index 0000000..0fe4ef3 --- /dev/null +++ b/drivers/ata/pata_octeon_cf.c @@ -0,0 +1,965 @@ +/* + * Driver for the Octeon bootbus compact flash. + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 2005 - 2009 Cavium Networks + * Copyright (C) 2008 Wind River Systems + */ + +#include +#include +#include +#include +#include +#include +#include + +#include + +/* + * The Octeon bootbus compact flash interface is connected in at least + * 3 different configurations on various evaluation boards: + * + * -- 8 bits no irq, no DMA + * -- 16 bits no irq, no DMA + * -- 16 bits True IDE mode with DMA, but no irq. + * + * In the last case the DMA engine can generate an interrupt when the + * transfer is complete. For the first two cases only PIO is supported. + * + */ + +#define DRV_NAME "pata_octeon_cf" +#define DRV_VERSION "2.1" + + +struct octeon_cf_port { + struct workqueue_struct *wq; + struct delayed_work delayed_finish; + struct ata_port *ap; + int dma_finished; +}; + +static struct scsi_host_template octeon_cf_sht = { + ATA_PIO_SHT(DRV_NAME), +}; + +/** + * Convert nanosecond based time to setting used in the + * boot bus timing register, based on timing multiple + */ +static unsigned int ns_to_tim_reg(unsigned int tim_mult, unsigned int nsecs) +{ + unsigned int val; + + /* + * Compute # of eclock periods to get desired duration in + * nanoseconds. + */ + val = DIV_ROUND_UP(nsecs * (octeon_get_clock_rate() / 1000000), + 1000 * tim_mult); + + return val; +} + +static void octeon_cf_set_boot_reg_cfg(int cs) +{ + union cvmx_mio_boot_reg_cfgx reg_cfg; + reg_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs)); + reg_cfg.s.dmack = 0; /* Don't assert DMACK on access */ + reg_cfg.s.tim_mult = 2; /* Timing mutiplier 2x */ + reg_cfg.s.rd_dly = 0; /* Sample on falling edge of BOOT_OE */ + reg_cfg.s.sam = 0; /* Don't combine write and output enable */ + reg_cfg.s.we_ext = 0; /* No write enable extension */ + reg_cfg.s.oe_ext = 0; /* No read enable extension */ + reg_cfg.s.en = 1; /* Enable this region */ + reg_cfg.s.orbit = 0; /* Don't combine with previous region */ + reg_cfg.s.ale = 0; /* Don't do address multiplexing */ + cvmx_write_csr(CVMX_MIO_BOOT_REG_CFGX(cs), reg_cfg.u64); +} + +/** + * Called after libata determines the needed PIO mode. This + * function programs the Octeon bootbus regions to support the + * timing requirements of the PIO mode. + * + * @ap: ATA port information + * @dev: ATA device + */ +static void octeon_cf_set_piomode(struct ata_port *ap, struct ata_device *dev) +{ + struct octeon_cf_data *ocd = ap->dev->platform_data; + union cvmx_mio_boot_reg_timx reg_tim; + int cs = ocd->base_region; + int T; + struct ata_timing timing; + + int use_iordy; + int trh; + int pause; + /* These names are timing parameters from the ATA spec */ + int t1; + int t2; + int t2i; + + T = (int)(2000000000000LL / octeon_get_clock_rate()); + + if (ata_timing_compute(dev, dev->pio_mode, &timing, T, T)) + BUG(); + + t1 = timing.setup; + if (t1) + t1--; + t2 = timing.active; + if (t2) + t2--; + t2i = timing.act8b; + if (t2i) + t2i--; + + trh = ns_to_tim_reg(2, 20); + if (trh) + trh--; + + pause = timing.cycle - timing.active - timing.setup - trh; + if (pause) + pause--; + + octeon_cf_set_boot_reg_cfg(cs); + if (ocd->dma_engine >= 0) + /* True IDE mode, program both chip selects. */ + octeon_cf_set_boot_reg_cfg(cs + 1); + + + use_iordy = ata_pio_need_iordy(dev); + + reg_tim.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_TIMX(cs)); + /* Disable page mode */ + reg_tim.s.pagem = 0; + /* Enable dynamic timing */ + reg_tim.s.waitm = use_iordy; + /* Pages are disabled */ + reg_tim.s.pages = 0; + /* We don't use multiplexed address mode */ + reg_tim.s.ale = 0; + /* Not used */ + reg_tim.s.page = 0; + /* Time after IORDY to coninue to assert the data */ + reg_tim.s.wait = 0; + /* Time to wait to complete the cycle. */ + reg_tim.s.pause = pause; + /* How long to hold after a write to de-assert CE. */ + reg_tim.s.wr_hld = trh; + /* How long to wait after a read to de-assert CE. */ + reg_tim.s.rd_hld = trh; + /* How long write enable is asserted */ + reg_tim.s.we = t2; + /* How long read enable is asserted */ + reg_tim.s.oe = t2; + /* Time after CE that read/write starts */ + reg_tim.s.ce = ns_to_tim_reg(2, 5); + /* Time before CE that address is valid */ + reg_tim.s.adr = 0; + + /* Program the bootbus region timing for the data port chip select. */ + cvmx_write_csr(CVMX_MIO_BOOT_REG_TIMX(cs), reg_tim.u64); + if (ocd->dma_engine >= 0) + /* True IDE mode, program both chip selects. */ + cvmx_write_csr(CVMX_MIO_BOOT_REG_TIMX(cs + 1), reg_tim.u64); +} + +static void octeon_cf_set_dmamode(struct ata_port *ap, struct ata_device *dev) +{ + struct octeon_cf_data *ocd = dev->link->ap->dev->platform_data; + union cvmx_mio_boot_dma_timx dma_tim; + unsigned int oe_a; + unsigned int oe_n; + unsigned int dma_ackh; + unsigned int dma_arq; + unsigned int pause; + unsigned int T0, Tkr, Td; + unsigned int tim_mult; + + const struct ata_timing *timing; + + timing = ata_timing_find_mode(dev->dma_mode); + T0 = timing->cycle; + Td = timing->active; + Tkr = timing->recover; + dma_ackh = timing->dmack_hold; + + dma_tim.u64 = 0; + /* dma_tim.s.tim_mult = 0 --> 4x */ + tim_mult = 4; + + /* not spec'ed, value in eclocks, not affected by tim_mult */ + dma_arq = 8; + pause = 25 - dma_arq * 1000 / + (octeon_get_clock_rate() / 1000000); /* Tz */ + + oe_a = Td; + /* Tkr from cf spec, lengthened to meet T0 */ + oe_n = max(T0 - oe_a, Tkr); + + dma_tim.s.dmack_pi = 1; + + dma_tim.s.oe_n = ns_to_tim_reg(tim_mult, oe_n); + dma_tim.s.oe_a = ns_to_tim_reg(tim_mult, oe_a); + + /* + * This is tI, C.F. spec. says 0, but Sony CF card requires + * more, we use 20 nS. + */ + dma_tim.s.dmack_s = ns_to_tim_reg(tim_mult, 20);; + dma_tim.s.dmack_h = ns_to_tim_reg(tim_mult, dma_ackh); + + dma_tim.s.dmarq = dma_arq; + dma_tim.s.pause = ns_to_tim_reg(tim_mult, pause); + + dma_tim.s.rd_dly = 0; /* Sample right on edge */ + + /* writes only */ + dma_tim.s.we_n = ns_to_tim_reg(tim_mult, oe_n); + dma_tim.s.we_a = ns_to_tim_reg(tim_mult, oe_a); + + pr_debug("ns to ticks (mult %d) of %d is: %d\n", tim_mult, 60, + ns_to_tim_reg(tim_mult, 60)); + pr_debug("oe_n: %d, oe_a: %d, dmack_s: %d, dmack_h: " + "%d, dmarq: %d, pause: %d\n", + dma_tim.s.oe_n, dma_tim.s.oe_a, dma_tim.s.dmack_s, + dma_tim.s.dmack_h, dma_tim.s.dmarq, dma_tim.s.pause); + + cvmx_write_csr(CVMX_MIO_BOOT_DMA_TIMX(ocd->dma_engine), + dma_tim.u64); + +} + +/** + * Handle an 8 bit I/O request. + * + * @dev: Device to access + * @buffer: Data buffer + * @buflen: Length of the buffer. + * @rw: True to write. + */ +static unsigned int octeon_cf_data_xfer8(struct ata_device *dev, + unsigned char *buffer, + unsigned int buflen, + int rw) +{ + struct ata_port *ap = dev->link->ap; + void __iomem *data_addr = ap->ioaddr.data_addr; + unsigned long words; + int count; + + words = buflen; + if (rw) { + count = 16; + while (words--) { + iowrite8(*buffer, data_addr); + buffer++; + /* + * Every 16 writes do a read so the bootbus + * FIFO doesn't fill up. + */ + if (--count == 0) { + ioread8(ap->ioaddr.altstatus_addr); + count = 16; + } + } + } else { + ioread8_rep(data_addr, buffer, words); + } + return buflen; +} + +/** + * Handle a 16 bit I/O request. + * + * @dev: Device to access + * @buffer: Data buffer + * @buflen: Length of the buffer. + * @rw: True to write. + */ +static unsigned int octeon_cf_data_xfer16(struct ata_device *dev, + unsigned char *buffer, + unsigned int buflen, + int rw) +{ + struct ata_port *ap = dev->link->ap; + void __iomem *data_addr = ap->ioaddr.data_addr; + unsigned long words; + int count; + + words = buflen / 2; + if (rw) { + count = 16; + while (words--) { + iowrite16(*(uint16_t *)buffer, data_addr); + buffer += sizeof(uint16_t); + /* + * Every 16 writes do a read so the bootbus + * FIFO doesn't fill up. + */ + if (--count == 0) { + ioread8(ap->ioaddr.altstatus_addr); + count = 16; + } + } + } else { + while (words--) { + *(uint16_t *)buffer = ioread16(data_addr); + buffer += sizeof(uint16_t); + } + } + /* Transfer trailing 1 byte, if any. */ + if (unlikely(buflen & 0x01)) { + __le16 align_buf[1] = { 0 }; + + if (rw == READ) { + align_buf[0] = cpu_to_le16(ioread16(data_addr)); + memcpy(buffer, align_buf, 1); + } else { + memcpy(align_buf, buffer, 1); + iowrite16(le16_to_cpu(align_buf[0]), data_addr); + } + words++; + } + return buflen; +} + +/** + * Read the taskfile for 16bit non-True IDE only. + */ +static void octeon_cf_tf_read16(struct ata_port *ap, struct ata_taskfile *tf) +{ + u16 blob; + /* The base of the registers is at ioaddr.data_addr. */ + void __iomem *base = ap->ioaddr.data_addr; + + blob = __raw_readw(base + 0xc); + tf->feature = blob >> 8; + + blob = __raw_readw(base + 2); + tf->nsect = blob & 0xff; + tf->lbal = blob >> 8; + + blob = __raw_readw(base + 4); + tf->lbam = blob & 0xff; + tf->lbah = blob >> 8; + + blob = __raw_readw(base + 6); + tf->device = blob & 0xff; + tf->command = blob >> 8; + + if (tf->flags & ATA_TFLAG_LBA48) { + if (likely(ap->ioaddr.ctl_addr)) { + iowrite8(tf->ctl | ATA_HOB, ap->ioaddr.ctl_addr); + + blob = __raw_readw(base + 0xc); + tf->hob_feature = blob >> 8; + + blob = __raw_readw(base + 2); + tf->hob_nsect = blob & 0xff; + tf->hob_lbal = blob >> 8; + + blob = __raw_readw(base + 4); + tf->hob_lbam = blob & 0xff; + tf->hob_lbah = blob >> 8; + + iowrite8(tf->ctl, ap->ioaddr.ctl_addr); + ap->last_ctl = tf->ctl; + } else { + WARN_ON(1); + } + } +} + +static u8 octeon_cf_check_status16(struct ata_port *ap) +{ + u16 blob; + void __iomem *base = ap->ioaddr.data_addr; + + blob = __raw_readw(base + 6); + return blob >> 8; +} + +static int octeon_cf_softreset16(struct ata_link *link, unsigned int *classes, + unsigned long deadline) +{ + struct ata_port *ap = link->ap; + void __iomem *base = ap->ioaddr.data_addr; + int rc; + u8 err; + + DPRINTK("about to softreset\n"); + __raw_writew(ap->ctl, base + 0xe); + udelay(20); + __raw_writew(ap->ctl | ATA_SRST, base + 0xe); + udelay(20); + __raw_writew(ap->ctl, base + 0xe); + + rc = ata_sff_wait_after_reset(link, 1, deadline); + if (rc) { + ata_link_printk(link, KERN_ERR, "SRST failed (errno=%d)\n", rc); + return rc; + } + + /* determine by signature whether we have ATA or ATAPI devices */ + classes[0] = ata_sff_dev_classify(&link->device[0], 1, &err); + DPRINTK("EXIT, classes[0]=%u [1]=%u\n", classes[0], classes[1]); + return 0; +} + +/** + * Load the taskfile for 16bit non-True IDE only. The device_addr is + * not loaded, we do this as part of octeon_cf_exec_command16. + */ +static void octeon_cf_tf_load16(struct ata_port *ap, + const struct ata_taskfile *tf) +{ + unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR; + /* The base of the registers is at ioaddr.data_addr. */ + void __iomem *base = ap->ioaddr.data_addr; + + if (tf->ctl != ap->last_ctl) { + iowrite8(tf->ctl, ap->ioaddr.ctl_addr); + ap->last_ctl = tf->ctl; + ata_wait_idle(ap); + } + if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) { + __raw_writew(tf->hob_feature << 8, base + 0xc); + __raw_writew(tf->hob_nsect | tf->hob_lbal << 8, base + 2); + __raw_writew(tf->hob_lbam | tf->hob_lbah << 8, base + 4); + VPRINTK("hob: feat 0x%X nsect 0x%X, lba 0x%X 0x%X 0x%X\n", + tf->hob_feature, + tf->hob_nsect, + tf->hob_lbal, + tf->hob_lbam, + tf->hob_lbah); + } + if (is_addr) { + __raw_writew(tf->feature << 8, base + 0xc); + __raw_writew(tf->nsect | tf->lbal << 8, base + 2); + __raw_writew(tf->lbam | tf->lbah << 8, base + 4); + VPRINTK("feat 0x%X nsect 0x%X, lba 0x%X 0x%X 0x%X\n", + tf->feature, + tf->nsect, + tf->lbal, + tf->lbam, + tf->lbah); + } + ata_wait_idle(ap); +} + + +static void octeon_cf_dev_select(struct ata_port *ap, unsigned int device) +{ +/* There is only one device, do nothing. */ + return; +} + +/* + * Issue ATA command to host controller. The device_addr is also sent + * as it must be written in a combined write with the command. + */ +static void octeon_cf_exec_command16(struct ata_port *ap, + const struct ata_taskfile *tf) +{ + /* The base of the registers is at ioaddr.data_addr. */ + void __iomem *base = ap->ioaddr.data_addr; + u16 blob; + + if (tf->flags & ATA_TFLAG_DEVICE) { + VPRINTK("device 0x%X\n", tf->device); + blob = tf->device; + } else { + blob = 0; + } + + DPRINTK("ata%u: cmd 0x%X\n", ap->print_id, tf->command); + blob |= (tf->command << 8); + __raw_writew(blob, base + 6); + + + ata_wait_idle(ap); +} + +static u8 octeon_cf_irq_on(struct ata_port *ap) +{ + return 0; +} + +static void octeon_cf_irq_clear(struct ata_port *ap) +{ + return; +} + +static void octeon_cf_dma_setup(struct ata_queued_cmd *qc) +{ + struct ata_port *ap = qc->ap; + struct octeon_cf_port *cf_port; + + cf_port = (struct octeon_cf_port *)ap->private_data; + DPRINTK("ENTER\n"); + /* issue r/w command */ + qc->cursg = qc->sg; + cf_port->dma_finished = 0; + ap->ops->sff_exec_command(ap, &qc->tf); + DPRINTK("EXIT\n"); +} + +/** + * Start a DMA transfer that was already setup + * + * @qc: Information about the DMA + */ +static void octeon_cf_dma_start(struct ata_queued_cmd *qc) +{ + struct octeon_cf_data *ocd = qc->ap->dev->platform_data; + union cvmx_mio_boot_dma_cfgx mio_boot_dma_cfg; + union cvmx_mio_boot_dma_intx mio_boot_dma_int; + struct scatterlist *sg; + + VPRINTK("%d scatterlists\n", qc->n_elem); + + /* Get the scatter list entry we need to DMA into */ + sg = qc->cursg; + BUG_ON(!sg); + + /* + * Clear the DMA complete status. + */ + mio_boot_dma_int.u64 = 0; + mio_boot_dma_int.s.done = 1; + cvmx_write_csr(CVMX_MIO_BOOT_DMA_INTX(ocd->dma_engine), + mio_boot_dma_int.u64); + + /* Enable the interrupt. */ + cvmx_write_csr(CVMX_MIO_BOOT_DMA_INT_ENX(ocd->dma_engine), + mio_boot_dma_int.u64); + + /* Set the direction of the DMA */ + mio_boot_dma_cfg.u64 = 0; + mio_boot_dma_cfg.s.en = 1; + mio_boot_dma_cfg.s.rw = ((qc->tf.flags & ATA_TFLAG_WRITE) != 0); + + /* + * Don't stop the DMA if the device deasserts DMARQ. Many + * compact flashes deassert DMARQ for a short time between + * sectors. Instead of stopping and restarting the DMA, we'll + * let the hardware do it. If the DMA is really stopped early + * due to an error condition, a later timeout will force us to + * stop. + */ + mio_boot_dma_cfg.s.clr = 0; + + /* Size is specified in 16bit words and minus one notation */ + mio_boot_dma_cfg.s.size = sg_dma_len(sg) / 2 - 1; + + /* We need to swap the high and low bytes of every 16 bits */ + mio_boot_dma_cfg.s.swap8 = 1; + + mio_boot_dma_cfg.s.adr = sg_dma_address(sg); + + VPRINTK("%s %d bytes address=%p\n", + (mio_boot_dma_cfg.s.rw) ? "write" : "read", sg->length, + (void *)(unsigned long)mio_boot_dma_cfg.s.adr); + + cvmx_write_csr(CVMX_MIO_BOOT_DMA_CFGX(ocd->dma_engine), + mio_boot_dma_cfg.u64); +} + +/** + * + * LOCKING: + * spin_lock_irqsave(host lock) + * + */ +static unsigned int octeon_cf_dma_finished(struct ata_port *ap, + struct ata_queued_cmd *qc) +{ + struct ata_eh_info *ehi = &ap->link.eh_info; + struct octeon_cf_data *ocd = ap->dev->platform_data; + union cvmx_mio_boot_dma_cfgx dma_cfg; + union cvmx_mio_boot_dma_intx dma_int; + struct octeon_cf_port *cf_port; + u8 status; + + VPRINTK("ata%u: protocol %d task_state %d\n", + ap->print_id, qc->tf.protocol, ap->hsm_task_state); + + + if (ap->hsm_task_state != HSM_ST_LAST) + return 0; + + cf_port = (struct octeon_cf_port *)ap->private_data; + + dma_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_DMA_CFGX(ocd->dma_engine)); + if (dma_cfg.s.size != 0xfffff) { + /* Error, the transfer was not complete. */ + qc->err_mask |= AC_ERR_HOST_BUS; + ap->hsm_task_state = HSM_ST_ERR; + } + + /* Stop and clear the dma engine. */ + dma_cfg.u64 = 0; + dma_cfg.s.size = -1; + cvmx_write_csr(CVMX_MIO_BOOT_DMA_CFGX(ocd->dma_engine), dma_cfg.u64); + + /* Disable the interrupt. */ + dma_int.u64 = 0; + cvmx_write_csr(CVMX_MIO_BOOT_DMA_INT_ENX(ocd->dma_engine), dma_int.u64); + + /* Clear the DMA complete status */ + dma_int.s.done = 1; + cvmx_write_csr(CVMX_MIO_BOOT_DMA_INTX(ocd->dma_engine), dma_int.u64); + + status = ap->ops->sff_check_status(ap); + + ata_sff_hsm_move(ap, qc, status, 0); + + if (unlikely(qc->err_mask) && (qc->tf.protocol == ATA_PROT_DMA)) + ata_ehi_push_desc(ehi, "DMA stat 0x%x", status); + + return 1; +} + +/* + * Check if any queued commands have more DMAs, if so start the next + * transfer, else do end of transfer handling. + */ +static irqreturn_t octeon_cf_interrupt(int irq, void *dev_instance) +{ + struct ata_host *host = dev_instance; + struct octeon_cf_port *cf_port; + int i; + unsigned int handled = 0; + unsigned long flags; + + spin_lock_irqsave(&host->lock, flags); + + DPRINTK("ENTER\n"); + for (i = 0; i < host->n_ports; i++) { + u8 status; + struct ata_port *ap; + struct ata_queued_cmd *qc; + union cvmx_mio_boot_dma_intx dma_int; + union cvmx_mio_boot_dma_cfgx dma_cfg; + struct octeon_cf_data *ocd; + + ap = host->ports[i]; + ocd = ap->dev->platform_data; + if (!ap || (ap->flags & ATA_FLAG_DISABLED)) + continue; + + ocd = ap->dev->platform_data; + cf_port = (struct octeon_cf_port *)ap->private_data; + dma_int.u64 = + cvmx_read_csr(CVMX_MIO_BOOT_DMA_INTX(ocd->dma_engine)); + dma_cfg.u64 = + cvmx_read_csr(CVMX_MIO_BOOT_DMA_CFGX(ocd->dma_engine)); + + qc = ata_qc_from_tag(ap, ap->link.active_tag); + + if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)) && + (qc->flags & ATA_QCFLAG_ACTIVE)) { + if (dma_int.s.done && !dma_cfg.s.en) { + if (!sg_is_last(qc->cursg)) { + qc->cursg = sg_next(qc->cursg); + handled = 1; + octeon_cf_dma_start(qc); + continue; + } else { + cf_port->dma_finished = 1; + } + } + if (!cf_port->dma_finished) + continue; + status = ioread8(ap->ioaddr.altstatus_addr); + if (status & (ATA_BUSY | ATA_DRQ)) { + /* + * We are busy, try to handle it + * later. This is the DMA finished + * interrupt, and it could take a + * little while for the card to be + * ready for more commands. + */ + /* Clear DMA irq. */ + dma_int.u64 = 0; + dma_int.s.done = 1; + cvmx_write_csr(CVMX_MIO_BOOT_DMA_INTX(ocd->dma_engine), + dma_int.u64); + + queue_delayed_work(cf_port->wq, + &cf_port->delayed_finish, 1); + handled = 1; + } else { + handled |= octeon_cf_dma_finished(ap, qc); + } + } + } + spin_unlock_irqrestore(&host->lock, flags); + DPRINTK("EXIT\n"); + return IRQ_RETVAL(handled); +} + +static void octeon_cf_delayed_finish(struct work_struct *work) +{ + struct octeon_cf_port *cf_port = container_of(work, + struct octeon_cf_port, + delayed_finish.work); + struct ata_port *ap = cf_port->ap; + struct ata_host *host = ap->host; + struct ata_queued_cmd *qc; + unsigned long flags; + u8 status; + + spin_lock_irqsave(&host->lock, flags); + + /* + * If the port is not waiting for completion, it must have + * handled it previously. The hsm_task_state is + * protected by host->lock. + */ + if (ap->hsm_task_state != HSM_ST_LAST || !cf_port->dma_finished) + goto out; + + status = ioread8(ap->ioaddr.altstatus_addr); + if (status & (ATA_BUSY | ATA_DRQ)) { + /* Still busy, try again. */ + queue_delayed_work(cf_port->wq, + &cf_port->delayed_finish, 1); + goto out; + } + qc = ata_qc_from_tag(ap, ap->link.active_tag); + if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)) && + (qc->flags & ATA_QCFLAG_ACTIVE)) + octeon_cf_dma_finished(ap, qc); +out: + spin_unlock_irqrestore(&host->lock, flags); +} + +static void octeon_cf_dev_config(struct ata_device *dev) +{ + /* + * A maximum of 2^20 - 1 16 bit transfers are possible with + * the bootbus DMA. So we need to throttle max_sectors to + * (2^12 - 1 == 4095) to assure that this can never happen. + */ + dev->max_sectors = min(dev->max_sectors, 4095U); +} + +/* + * Trap if driver tries to do standard bmdma commands. They are not + * supported. + */ +static void unreachable_qc(struct ata_queued_cmd *qc) +{ + BUG(); +} + +static u8 unreachable_port(struct ata_port *ap) +{ + BUG(); +} + +/* + * We don't do ATAPI DMA so return 0. + */ +static int octeon_cf_check_atapi_dma(struct ata_queued_cmd *qc) +{ + return 0; +} + +static unsigned int octeon_cf_qc_issue(struct ata_queued_cmd *qc) +{ + struct ata_port *ap = qc->ap; + + switch (qc->tf.protocol) { + case ATA_PROT_DMA: + WARN_ON(qc->tf.flags & ATA_TFLAG_POLLING); + + ap->ops->sff_tf_load(ap, &qc->tf); /* load tf registers */ + octeon_cf_dma_setup(qc); /* set up dma */ + octeon_cf_dma_start(qc); /* initiate dma */ + ap->hsm_task_state = HSM_ST_LAST; + break; + + case ATAPI_PROT_DMA: + dev_err(ap->dev, "Error, ATAPI not supported\n"); + BUG(); + + default: + return ata_sff_qc_issue(qc); + } + + return 0; +} + +static struct ata_port_operations octeon_cf_ops = { + .inherits = &ata_sff_port_ops, + .check_atapi_dma = octeon_cf_check_atapi_dma, + .qc_prep = ata_noop_qc_prep, + .qc_issue = octeon_cf_qc_issue, + .sff_dev_select = octeon_cf_dev_select, + .sff_irq_on = octeon_cf_irq_on, + .sff_irq_clear = octeon_cf_irq_clear, + .bmdma_setup = unreachable_qc, + .bmdma_start = unreachable_qc, + .bmdma_stop = unreachable_qc, + .bmdma_status = unreachable_port, + .cable_detect = ata_cable_40wire, + .set_piomode = octeon_cf_set_piomode, + .set_dmamode = octeon_cf_set_dmamode, + .dev_config = octeon_cf_dev_config, +}; + +static int __devinit octeon_cf_probe(struct platform_device *pdev) +{ + struct resource *res_cs0, *res_cs1; + + void __iomem *cs0; + void __iomem *cs1 = NULL; + struct ata_host *host; + struct ata_port *ap; + struct octeon_cf_data *ocd; + int irq = 0; + irq_handler_t irq_handler = NULL; + void __iomem *base; + struct octeon_cf_port *cf_port; + + res_cs0 = platform_get_resource(pdev, IORESOURCE_MEM, 0); + + if (!res_cs0) + return -EINVAL; + + ocd = pdev->dev.platform_data; + + cs0 = devm_ioremap_nocache(&pdev->dev, res_cs0->start, + res_cs0->end - res_cs0->start + 1); + + if (!cs0) + return -ENOMEM; + + /* Determine from availability of DMA if True IDE mode or not */ + if (ocd->dma_engine >= 0) { + res_cs1 = platform_get_resource(pdev, IORESOURCE_MEM, 1); + if (!res_cs1) + return -EINVAL; + + cs1 = devm_ioremap_nocache(&pdev->dev, res_cs1->start, + res_cs0->end - res_cs1->start + 1); + + if (!cs1) + return -ENOMEM; + } + + cf_port = kzalloc(sizeof(*cf_port), GFP_KERNEL); + if (!cf_port) + return -ENOMEM; + + /* allocate host */ + host = ata_host_alloc(&pdev->dev, 1); + if (!host) + goto free_cf_port; + + ap = host->ports[0]; + ap->private_data = cf_port; + cf_port->ap = ap; + ap->ops = &octeon_cf_ops; + ap->pio_mask = 0x7f; /* Support PIO 0-6 */ + ap->flags |= ATA_FLAG_MMIO | ATA_FLAG_NO_LEGACY + | ATA_FLAG_NO_ATAPI | ATA_FLAG_PIO_POLLING; + + base = cs0 + ocd->base_region_bias; + if (!ocd->is16bit) { + ap->ioaddr.cmd_addr = base; + ata_sff_std_ports(&ap->ioaddr); + + ap->ioaddr.altstatus_addr = base + 0xe; + ap->ioaddr.ctl_addr = base + 0xe; + octeon_cf_ops.sff_data_xfer = octeon_cf_data_xfer8; + } else if (cs1) { + /* Presence of cs1 indicates True IDE mode. */ + ap->ioaddr.cmd_addr = base + (ATA_REG_CMD << 1) + 1; + ap->ioaddr.data_addr = base + (ATA_REG_DATA << 1); + ap->ioaddr.error_addr = base + (ATA_REG_ERR << 1) + 1; + ap->ioaddr.feature_addr = base + (ATA_REG_FEATURE << 1) + 1; + ap->ioaddr.nsect_addr = base + (ATA_REG_NSECT << 1) + 1; + ap->ioaddr.lbal_addr = base + (ATA_REG_LBAL << 1) + 1; + ap->ioaddr.lbam_addr = base + (ATA_REG_LBAM << 1) + 1; + ap->ioaddr.lbah_addr = base + (ATA_REG_LBAH << 1) + 1; + ap->ioaddr.device_addr = base + (ATA_REG_DEVICE << 1) + 1; + ap->ioaddr.status_addr = base + (ATA_REG_STATUS << 1) + 1; + ap->ioaddr.command_addr = base + (ATA_REG_CMD << 1) + 1; + ap->ioaddr.altstatus_addr = cs1 + (6 << 1) + 1; + ap->ioaddr.ctl_addr = cs1 + (6 << 1) + 1; + octeon_cf_ops.sff_data_xfer = octeon_cf_data_xfer16; + + ap->mwdma_mask = 0x1f; /* Support MWDMA 0-4 */ + irq = platform_get_irq(pdev, 0); + irq_handler = octeon_cf_interrupt; + + /* True IDE mode needs delayed work to poll for not-busy. */ + cf_port->wq = create_singlethread_workqueue(DRV_NAME); + if (!cf_port->wq) + goto free_cf_port; + INIT_DELAYED_WORK(&cf_port->delayed_finish, + octeon_cf_delayed_finish); + + } else { + /* 16 bit but not True IDE */ + octeon_cf_ops.sff_data_xfer = octeon_cf_data_xfer16; + octeon_cf_ops.softreset = octeon_cf_softreset16; + octeon_cf_ops.sff_check_status = octeon_cf_check_status16; + octeon_cf_ops.sff_tf_read = octeon_cf_tf_read16; + octeon_cf_ops.sff_tf_load = octeon_cf_tf_load16; + octeon_cf_ops.sff_exec_command = octeon_cf_exec_command16; + + ap->ioaddr.data_addr = base + ATA_REG_DATA; + ap->ioaddr.nsect_addr = base + ATA_REG_NSECT; + ap->ioaddr.lbal_addr = base + ATA_REG_LBAL; + ap->ioaddr.ctl_addr = base + 0xe; + ap->ioaddr.altstatus_addr = base + 0xe; + } + + ata_port_desc(ap, "cmd %p ctl %p", base, ap->ioaddr.ctl_addr); + + + dev_info(&pdev->dev, "version " DRV_VERSION" %d bit%s.\n", + (ocd->is16bit) ? 16 : 8, + (cs1) ? ", True IDE" : ""); + + + return ata_host_activate(host, irq, irq_handler, 0, &octeon_cf_sht); + +free_cf_port: + kfree(cf_port); + return -ENOMEM; +} + +static struct platform_driver octeon_cf_driver = { + .probe = octeon_cf_probe, + .driver = { + .name = DRV_NAME, + .owner = THIS_MODULE, + }, +}; + +static int __init octeon_cf_init(void) +{ + return platform_driver_register(&octeon_cf_driver); +} + + +MODULE_AUTHOR("David Daney "); +MODULE_DESCRIPTION("low-level driver for Cavium OCTEON Compact Flash PATA"); +MODULE_LICENSE("GPL"); +MODULE_VERSION(DRV_VERSION); +MODULE_ALIAS("platform:" DRV_NAME); + +module_init(octeon_cf_init); -- 1.5.6.6 From f.fainelli@gmail.com Fri Jan 16 10:11:01 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 16 Jan 2009 10:11:13 +0000 (GMT) Received: from mail-bw0-f13.google.com ([209.85.218.13]:30629 "EHLO mail-bw0-f13.google.com") by ftp.linux-mips.org with ESMTP id S21365849AbZAPKKd (ORCPT ); Fri, 16 Jan 2009 10:10:33 +0000 Received: by bwz6 with SMTP id 6so4443133bwz.0 for ; Fri, 16 Jan 2009 02:10:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:sender:received:in-reply-to :references:date:x-google-sender-auth:message-id:subject:from:to:cc :content-type; bh=dsgDLXtW9cKPTv1SIMBiK5iWWrY7WGkFWapSiH95juM=; b=EdUMvDQbNlR8cRxAIeCjUGRyuSjHte/5YdrxQ4/Z6j7N9hsigCkCbG2BiRT5M+lBLv I0fCvBPkm/gdFYg1UWTAIYmE/JfAowFrR0f4DFT4ZwVo/GS/sgp6k1Jb7Pa6szty5ESi hrov/7Di0oX6OVFLEWi6XjG5FcyQ+Elo5pfa8= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:sender:in-reply-to:references:date :x-google-sender-auth:message-id:subject:from:to:cc:content-type; b=ob0WkB6fdd2Hxmk0/p2G2K3pKwVIy0fQiOkRRlHGbC0YQ5SH5aDcou4eAz8tJ1FSTy LJGOgHDvonL+S9IuoKa9b38kKddfJ0Bwdv3eCAKLCuRUnZtdp+KVYYoV8vZZX+cDi2Go yyb2vVkfq4blVyTz8W+GD/awYzzXgzVp7ZbzM= MIME-Version: 1.0 Received: by 10.181.155.9 with SMTP id h9mr784604bko.176.1232100625616; Fri, 16 Jan 2009 02:10:25 -0800 (PST) In-Reply-To: <20090115205851.GD8656@roarinelk.homelinux.net> References: <200901151646.49591.florian@openwrt.org> <20090115205851.GD8656@roarinelk.homelinux.net> Date: Fri, 16 Jan 2009 11:10:25 +0100 X-Google-Sender-Auth: f9b3a3c4d4d36dc8 Message-ID: <86ee6fd0901160210pdb7f52nf761f8706a56f8fe@mail.gmail.com> Subject: Re: [PATCH] au1000: convert to using gpiolib From: Florian Fainelli To: Manuel Lauss Cc: ralf@linux-mips.org, Linux-MIPS Content-Type: multipart/alternative; boundary=0016368e2b181e1090046096c88c Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21769 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips Content-Length: 12009 Lines: 295 --0016368e2b181e1090046096c88c Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Hi Manuel, 2009/1/15 Manuel Lauss > Hi Florian, > > On Thu, Jan 15, 2009 at 04:46:48PM +0100, Florian Fainelli wrote: > > This patch converts the GPIO board code to use gpiolib > > Because of the 'enable | value' scheme I believe you don't require any > locking here. Right, thanks. > > > > > +struct au1000_gpio_chip au1000_gpio_chip[] = { > > + [0] = { > > + .regbase = (void __iomem *)SYS_BASE, > > + .chip = { > > + .label = "au1000-gpio1", > > + .direction_input = > au1000_gpio1_direction_input, > > + .direction_output = > au1000_gpio1_direction_output, > > + .get = au1000_gpio1_get, > > + .set = au1000_gpio1_set, > > + .base = 0, > > + .ngpio = 32, > > + }, > > + }, > > +#if !defined(CONFIG_SOC_AU1000) > > + [1] = { > > + .regbase = (void __iomem > *)GPIO2_BASE, > > + .chip = { > > + .label = "au1000-gpio2", > > + .direction_input = > au1000_gpio2_direction_input, > > + .direction_output = > au1000_gpio2_direction_output, > > + .get = au1000_gpio2_get, > > + .set = au1000_gpio2_set, > > + .base = AU1XXX_GPIO_BASE, > > + .ngpio = 32, > > + }, > > + }, > > #endif > > - else > > - return au1xxx_gpio1_read(gpio); > > -} > > -EXPORT_SYMBOL(au1xxx_gpio_get_value); > > +}; > [...] > > +static int __init au1000_gpio_init(void) > > { > > - if (gpio >= AU1XXX_GPIO_BASE) > > -#if defined(CONFIG_SOC_AU1000) > > - ; > > -#else > > - au1xxx_gpio2_write(gpio, value); > > -#endif > > - else > > - au1xxx_gpio1_write(gpio, value); > > -} > > -EXPORT_SYMBOL(au1xxx_gpio_set_value); > > + gpiochip_add(&au1000_gpio_chip[0].chip); > > +#if !defined(CONFIG_SOC_AU1000) > > + gpiochip_add(&au1000_gpio_chip[1].chip); > > > [...] > > +arch_initcall(au1000_gpio_init); > > Can you please make the gpiolib registration dependent on a > CONFIG symbol? I.e. make the au1000_gpio{,2}_direction() and > friends calls globally visible but let the individual boards > decide whether they want to use the gpio numbering imposed by > this patch. Would something like #ifdef CONFIG_AU1000_NON_STD_GPIOS be ok with you ? Or maybe we could get the base information from board-specific code ? > > > Long explanation: I maintain a number of modules with a common connector > interface, based on different architectures (sh, mips and arm so far). > I also maintain a few baseboards which can carry theese modules. Modules > provide 16 gpios numbered 0-15, which are used by the baseboards. Since > I need to keep the baseboard code free of arch-specific hacks, every module > provides its own gpio-chip which distributes the gpio-lib calls to various > on- and off-chip peripherals. On my alchemy board in particular, those 16 > gpios are provided by a mixture of gpio1, gpio2 and FPGA based pins (yes > I repeatedly moanoed to the hw guys about this but pin multiplexing and > required features make a sane implementation difficult; but at least I was > allowed to write the VHDL for the fpga-based gpios). Your explanation makes perfect sense to me. > > > If this explanation doesn't make sense I'll gladly whip up an addon patch. > > > > diff --git a/arch/mips/include/asm/mach-au1x00/gpio.h > b/arch/mips/include/asm/mach-au1x00/gpio.h > > index 2dc61e0..34d9b72 100644 > > --- a/arch/mips/include/asm/mach-au1x00/gpio.h > > +++ b/arch/mips/include/asm/mach-au1x00/gpio.h > > @@ -5,65 +5,29 @@ > > > > #define AU1XXX_GPIO_BASE 200 > > please change this to AU1XXX_GPIO2_BASE (it's the base number > of the GPIO2 block pins after all) Ok. Thanks for your comments, I will respin with your comments. --0016368e2b181e1090046096c88c Content-Type: text/html; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Hi Manuel,

2009/1/15 Manuel Lauss <mano@roarinelk.homelinux.net>
Hi Florian,

On Thu, Jan 15, 2009 at 04:46:48PM +0100, Florian Fainelli wrote:
> This patch converts the GPIO board code to use gpiolib
<= br>
Because of the 'enable | value' scheme I believe you don'= t require any
locking here.

Right, thanks.
 



> +struct au1000_gpio_chip au1000_gpio_chip[] =3D {
> +     [0] =3D {
> +             .regbase     &nb= sp;                  =3D (void= __iomem *)SYS_BASE,
> +             .chip =3D {
> +                    = ; .label                  =3D = "au1000-gpio1",
> +                    = ; .direction_input        =3D au1000_gpio1_direction_in= put,
> +                    = ; .direction_output       =3D au1000_gpio1_direction_output,=
> +                    = ; .get                    = ;=3D au1000_gpio1_get,
> +                    = ; .set                    = ;=3D au1000_gpio1_set,
> +                    = ; .base                   =3D = 0,
> +                    = ; .ngpio                  =3D = 32,
> +             },
> +     },
> +#if !defined(CONFIG_SOC_AU1000)
> +     [1] =3D {
> +             .regbase     &nb= sp;                  =3D (void= __iomem *)GPIO2_BASE,
> +             .chip =3D {
> +                    = ; .label                  =3D = "au1000-gpio2",
> +                    = ; .direction_input        =3D au1000_gpio2_direction_in= put,
> +                    = ; .direction_output       =3D au1000_gpio2_direction_output,=
> +                    = ; .get                    = ;=3D au1000_gpio2_get,
> +                    = ; .set                    = ;=3D au1000_gpio2_set,
> +                    = ; .base                   =3D = AU1XXX_GPIO_BASE,
> +                    = ; .ngpio                  =3D = 32,
> +             },
> +     },
>  #endif
> -     else
> -             return au1xxx_gpio1_read(g= pio);
> -}
> -EXPORT_SYMBOL(au1xxx_gpio_get_value);
> +};
[...]
> +static int __init au1000_gpio_init(void)
>  {
> -     if (gpio >=3D AU1XXX_GPIO_BASE)
> -#if defined(CONFIG_SOC_AU1000)
> -             ;
> -#else
> -             au1xxx_gpio2_write(gpio, v= alue);
> -#endif
> -     else
> -             au1xxx_gpio1_write(gpio, v= alue);
> -}
> -EXPORT_SYMBOL(au1xxx_gpio_set_value);
> +     gpiochip_add(&au1000_gpio_chip[0].chip);
> +#if !defined(CONFIG_SOC_AU1000)
> +     gpiochip_add(&au1000_gpio_chip[1].chip);
>
[...]
> +arch_initcall(au1000_gpio_init);

Can you please make the gpiolib registration dependent on a
CONFIG symbol?  I.e. make the au1000_gpio{,2}_direction() and
friends calls globally visible but let the individual boards
decide whether they want to use the gpio numbering imposed by
this patch.

Would something like #ifdef CONFIG_AU1000_= NON_STD_GPIOS be ok with you ?
Or maybe we could get the base informatio= n from board-specific code ?
 


Long explanation:  I maintain a number of modules with a common connec= tor
interface, based on different architectures (sh, mips and arm so far).
I also maintain a few baseboards which can carry theese modules.  Modu= les
provide 16 gpios numbered 0-15, which are used by the baseboards.  Sin= ce
I need to keep the baseboard code free of arch-specific hacks, every module=
provides its own gpio-chip which distributes the gpio-lib calls to various<= br> on- and off-chip peripherals.  On my alchemy board in particular, thos= e 16
gpios are provided by a mixture of gpio1, gpio2 and FPGA based pins (yes I repeatedly moanoed to the hw guys about this but pin multiplexing and
required features make a sane implementation difficult; but at least I was<= br> allowed to write the VHDL for the fpga-based gpios).

Y= our explanation makes perfect sense to me.
 


If this explanation doesn't make sense I'll gladly whip up an addon= patch.


> diff --git a/arch/mips/include/asm/mach-au1x00/gpio.h b/arch/mips/incl= ude/asm/mach-au1x00/gpio.h
> index 2dc61e0..34d9b72 100644
> --- a/arch/mips/include/asm/mach-au1x00/gpio.h
> +++ b/arch/mips/include/asm/mach-au1x00/gpio.h
> @@ -5,65 +5,29 @@
>
>  #define AU1XXX_GPIO_BASE     200

please change this to AU1XXX_GPIO2_BASE (it's the base number
of the GPIO2 block pins after all)

Ok.
 
Th= anks for your comments, I will respin with your comments.
--0016368e2b181e1090046096c88c-- From sshtylyov@ru.mvista.com Fri Jan 16 13:05:13 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 16 Jan 2009 13:05:22 +0000 (GMT) Received: from h155.mvista.com ([63.81.120.155]:36540 "EHLO imap.sh.mvista.com") by ftp.linux-mips.org with ESMTP id S21366038AbZAPMvp (ORCPT ); Fri, 16 Jan 2009 12:51:45 +0000 Received: from [127.0.0.1] (unknown [10.150.0.9]) by imap.sh.mvista.com (Postfix) with ESMTP id B408F3ECC; Fri, 16 Jan 2009 04:51:32 -0800 (PST) Message-ID: <497082D1.5030504@ru.mvista.com> Date: Fri, 16 Jan 2009 15:51:29 +0300 From: Sergei Shtylyov User-Agent: Thunderbird 2.0.0.19 (Windows/20081209) MIME-Version: 1.0 To: Atsushi Nemoto Cc: linux-ide@vger.kernel.org, Bartlomiej Zolnierkiewicz , linux-mips@linux-mips.org, stable Subject: Re: [PATCH] tx4939ide: Do not use zero count PRD entry References: <1230215558-9197-1-git-send-email-anemo@mba.ocn.ne.jp> In-Reply-To: <1230215558-9197-1-git-send-email-anemo@mba.ocn.ne.jp> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21770 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sshtylyov@ru.mvista.com Precedence: bulk X-list: linux-mips Content-Length: 795 Lines: 35 Hello. Atsushi Nemoto wrote: > This fixes data corruption on some heavy load. > > Signed-off-by: Atsushi Nemoto > Acked-by: Sergei Shtylyov > diff --git a/drivers/ide/tx4939ide.c b/drivers/ide/tx4939ide.c > index bafb7d1..30d0d25 100644 > --- a/drivers/ide/tx4939ide.c > +++ b/drivers/ide/tx4939ide.c > @@ -259,6 +259,12 @@ static int tx4939ide_build_dmatable(ide_drive_t *drive, struct request *rq) > bcount = 0x10000 - (cur_addr & 0xffff); > if (bcount > cur_len) > bcount = cur_len; > + /* > + * This workaround for zero count seems required. > + * (standard ide_build_dmatable do it too) > s/do/does/ > + */ > + if ((bcount & 0xffff) == 0x0000) > Why not just bcount == 0x10000? MBR, Sergei From anemo@mba.ocn.ne.jp Fri Jan 16 14:26:04 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 16 Jan 2009 14:26:08 +0000 (GMT) Received: from mba.ocn.ne.jp ([122.1.235.107]:15612 "HELO smtp.mba.ocn.ne.jp") by ftp.linux-mips.org with SMTP id S21365860AbZAPOZa (ORCPT ); Fri, 16 Jan 2009 14:25:30 +0000 Received: from localhost (p4226-ipad212funabasi.chiba.ocn.ne.jp [58.91.168.226]) by smtp.mba.ocn.ne.jp (Postfix) with ESMTP id B799B9CEC; Fri, 16 Jan 2009 23:25:24 +0900 (JST) Date: Fri, 16 Jan 2009 23:25:27 +0900 (JST) Message-Id: <20090116.232527.59651191.anemo@mba.ocn.ne.jp> To: sshtylyov@ru.mvista.com Cc: linux-ide@vger.kernel.org, bzolnier@gmail.com, linux-mips@linux-mips.org, stable@kernel.org Subject: Re: [PATCH] tx4939ide: Do not use zero count PRD entry From: Atsushi Nemoto In-Reply-To: <497082D1.5030504@ru.mvista.com> References: <1230215558-9197-1-git-send-email-anemo@mba.ocn.ne.jp> <497082D1.5030504@ru.mvista.com> X-Fingerprint: 6ACA 1623 39BD 9A94 9B1A B746 CA77 FE94 2874 D52F X-Pgp-Public-Key: http://wwwkeys.pgp.net/pks/lookup?op=get&search=0x2874D52F X-Mailer: Mew version 5.2 on Emacs 21.4 / Mule 5.0 (SAKAKI) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21771 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anemo@mba.ocn.ne.jp Precedence: bulk X-list: linux-mips Content-Length: 531 Lines: 20 On Fri, 16 Jan 2009 15:51:29 +0300, Sergei Shtylyov wrote: > > + * This workaround for zero count seems required. > > + * (standard ide_build_dmatable do it too) > > s/do/does/ Thanks! > > + if ((bcount & 0xffff) == 0x0000) > > Why not just bcount == 0x10000? Indeed. It is just because ide_build_dmatable does so :) I will prepare another patch, while the patch is already mainlined and queued for stable, and this time changes are not suitable for stable tree. --- Atsushi Nemoto From mano@roarinelk.homelinux.net Fri Jan 16 17:48:26 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 16 Jan 2009 17:48:28 +0000 (GMT) Received: from fnoeppeil36.netpark.at ([217.175.205.164]:55682 "EHLO roarinelk.homelinux.net") by ftp.linux-mips.org with ESMTP id S21365664AbZAPRs0 (ORCPT ); Fri, 16 Jan 2009 17:48:26 +0000 Received: (qmail 18781 invoked by uid 1000); 16 Jan 2009 18:47:53 +0100 Date: Fri, 16 Jan 2009 18:47:53 +0100 From: Manuel Lauss To: Florian Fainelli Cc: ralf@linux-mips.org, Linux-MIPS Subject: Re: [PATCH] au1000: convert to using gpiolib Message-ID: <20090116174753.GA18764@roarinelk.homelinux.net> References: <200901151646.49591.florian@openwrt.org> <20090115205851.GD8656@roarinelk.homelinux.net> <86ee6fd0901160210pdb7f52nf761f8706a56f8fe@mail.gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <86ee6fd0901160210pdb7f52nf761f8706a56f8fe@mail.gmail.com> User-Agent: Mutt/1.5.16 (2007-06-09) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21772 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mano@roarinelk.homelinux.net Precedence: bulk X-list: linux-mips Content-Length: 717 Lines: 20 Hi Florian, On Fri, Jan 16, 2009 at 11:10:25AM +0100, Florian Fainelli wrote: > > Can you please make the gpiolib registration dependent on a > > CONFIG symbol? I.e. make the au1000_gpio{,2}_direction() and > > friends calls globally visible but let the individual boards > > decide whether they want to use the gpio numbering imposed by > > this patch. > > > Would something like #ifdef CONFIG_AU1000_NON_STD_GPIOS be ok with you ? > Or maybe we could get the base information from board-specific code ? Well, we could move the core_initcall() to all boards' setup function, and stick a comment on top of it explaining why it's there. Config symbol or the above, either is fine with me. Thanks! Manuel Lauss From msundius@cisco.com Fri Jan 16 21:46:37 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 16 Jan 2009 21:46:40 +0000 (GMT) Received: from rtp-iport-1.cisco.com ([64.102.122.148]:31021 "EHLO rtp-iport-1.cisco.com") by ftp.linux-mips.org with ESMTP id S21365904AbZAPVqh (ORCPT ); Fri, 16 Jan 2009 21:46:37 +0000 X-IronPort-AV: E=Sophos;i="4.37,278,1231113600"; d="scan'208";a="34065900" Received: from rtp-dkim-2.cisco.com ([64.102.121.159]) by rtp-iport-1.cisco.com with ESMTP; 16 Jan 2009 21:46:30 +0000 Received: from rtp-core-2.cisco.com (rtp-core-2.cisco.com [64.102.124.13]) by rtp-dkim-2.cisco.com (8.12.11/8.12.11) with ESMTP id n0GLkUE0019361 for ; Fri, 16 Jan 2009 16:46:30 -0500 Received: from sausatlsmtp1.sciatl.com (sausatlsmtp1.cisco.com [192.133.217.33]) by rtp-core-2.cisco.com (8.13.8/8.13.8) with ESMTP id n0GLkU3m007724 for ; Fri, 16 Jan 2009 21:46:30 GMT Received: from default.com ([192.133.217.33]) by sausatlsmtp1.sciatl.com with Microsoft SMTPSVC(6.0.3790.3959); Fri, 16 Jan 2009 16:46:27 -0500 Received: from sausatlbhs02.corp.sa.net ([192.133.216.42]) by sausatlsmtp1.sciatl.com with Microsoft SMTPSVC(6.0.3790.3959); Fri, 16 Jan 2009 16:46:24 -0500 Received: from CUPLXSUNDISM01.corp.sa.net ([64.101.21.60]) by sausatlbhs02.corp.sa.net with Microsoft SMTPSVC(6.0.3790.3959); Fri, 16 Jan 2009 16:46:24 -0500 Message-ID: <4971002D.2090907@cisco.com> Date: Fri, 16 Jan 2009 13:46:21 -0800 From: Michael Sundius User-Agent: Thunderbird 2.0.0.14 (X11/20080501) MIME-Version: 1.0 To: Christoph Lameter CC: Dave Hansen , Randy Dunlap , "Sundius, Michael" , Thomas Bogendoerfer , linux-mm@kvack.org, linux-mips@linux-mips.org, jfraser@broadcom.com, Andy Whitcroft , msundius@sundius.com Subject: Re: sparsemem support for mips with highmem References: <48A4AC39.7020707@sciatl.com> <1218753308.23641.56.camel@nimitz> <48A4C542.5000308@sciatl.com> <20080815080331.GA6689@alpha.franken.de> <1218815299.23641.80.camel@nimitz> <48A5AADE.1050808@sciatl.com> <20080815163302.GA9846@alpha.franken.de> <48A5B9F1.3080201@sciatl.com> <1218821875.23641.103.camel@nimitz> <48A5C831.3070002@sciatl.com> <20080818094412.09086445.rdunlap@xenotime.net> <48A9E89C.4020408@linux-foundation.org> <1219094865.23641.118.camel@nimitz> <48A9EAA9.1080909@linux-foundation.org> In-Reply-To: <48A9EAA9.1080909@linux-foundation.org> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 16 Jan 2009 21:46:24.0324 (UTC) FILETIME=[E08C2840:01C97823] X-ST-MF-Message-Resent: 1/16/2009 16:46 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; l=2460; t=1232142390; x=1233006390; c=relaxed/simple; s=rtpdkim2001; h=Content-Type:From:Subject:Content-Transfer-Encoding:MIME-Version; d=cisco.com; i=msundius@cisco.com; z=From:=20Michael=20Sundius=20 |Subject:=20Re=3A=20sparsemem=20support=20for=20mips=20with =20highmem |Sender:=20 |To:=20Christoph=20Lameter=20; bh=okOxMMyILXhoHPpyJ22h2rSlK4WI+Fu9ej9H9Pb4gSw=; b=nqLHTii4OXSx9+1HNnhLebvVIoyuzwbvzH+jEE/rcazDXBUsd0C2+/a+rE Tduh7QlMkvOEsOwTz9cNOf2G1C+Bz0RP9M52hIw3zygb5gIbTKntIKU8Snni IWcE/jmBz/; Authentication-Results: rtp-dkim-2; header.From=msundius@cisco.com; dkim=pass ( sig from cisco.com/rtpdkim2001 verified; ); Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21773 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: msundius@cisco.com Precedence: bulk X-list: linux-mips Content-Length: 2398 Lines: 64 Christoph Lameter wrote: > > Dave Hansen wrote: > > On Mon, 2008-08-18 at 16:24 -0500, Christoph Lameter wrote: > >> This overhead can be avoided by configuring sparsemem to use a > virtual vmemmap > >> (CONFIG_SPARSEMEM_VMEMMAP). In that case it can be used for non > NUMA since the > >> overhead is less than even FLATMEM. > > > > Is that all it takes these days, or do you need some other arch-specific > > code to help out? > > Some information is in mm/sparse-vmemmap.c. Simplest configuration is > to use > vmalloc for the populate function. Otherwise the arch can do what it > wants to > reduce the overhead of virtual mappings (in the x86 case we use a 2M TLB > entry, and since 2M TLBs are also used for the 1-1 physical mapping the > overhead is the same as for 1-1 mappings). > > Well, I finally gotten around to turning the vmemmap on for our sparsemem on Mips. I have a question about what you said above and how that applies to mips. you said that the simplest configuration is to use vmalloc for the populate function. could you expand on that? (i didn't see that the populate function used vmalloc or maybe we are talking about a different populate function). I've noticed that from looking at the kernel, only 64 bit processors or at least processors that use a 3 level page table have the vmemmap_populate() function implemented. in looking at the function vmemmap_populate_basepages() (called by most vmemmap_populate funcs) it seems to create a 3 level page table. not sure what my question here is, but maybe what do I have to do to make this work w/ mips which i understand uses only 2 levels can I just take out the part of the function that sets up the middle level table? Has anyone done this on mips? mike - - - - - Cisco - - - - - This e-mail and any attachments may contain information which is confidential, proprietary, privileged or otherwise protected by law. The information is solely intended for the named addressee (or a person responsible for delivering it to the addressee). If you are not the intended recipient of this message, you are not authorized to read, print, retain, copy or disseminate this message or any part of it. If you have received this e-mail in error, please notify the sender immediately by return e-mail and delete it from your computer. From mano@roarinelk.homelinux.net Sat Jan 17 17:44:13 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 17 Jan 2009 17:44:17 +0000 (GMT) Received: from fnoeppeil36.netpark.at ([217.175.205.164]:15528 "EHLO roarinelk.homelinux.net") by ftp.linux-mips.org with ESMTP id S21366117AbZAQRoN (ORCPT ); Sat, 17 Jan 2009 17:44:13 +0000 Received: (qmail 27309 invoked from network); 17 Jan 2009 18:44:11 +0100 Received: from scarran.roarinelk.net (HELO localhost.localdomain) (192.168.0.242) by 192.168.0.1 with SMTP; 17 Jan 2009 18:44:11 +0100 From: Manuel Lauss To: irda-users@lists.sourceforge.net Cc: Linux-MIPS , Manuel Lauss Subject: [RFC PATCH] au1k_ir.c: convert to platform device Date: Sat, 17 Jan 2009 18:44:22 +0100 Message-Id: <1232214262-20322-1-git-send-email-mano@roarinelk.homelinux.net> X-Mailer: git-send-email 1.6.0.6 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21774 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mano@roarinelk.homelinux.net Precedence: bulk X-list: linux-mips Content-Length: 45242 Lines: 1622 General driver overhaul: Compile fixes and platform_device conversion; removal of devboard-specific hacks in favour of platform data. Signed-off-by: Manuel Lauss --- Compile-tested only; I don't have the hardware. I'll send the platform-specific parts later once this patch has been accepted (shouldn't be a big deal, this driver didn't compile for ages and noone noticed). arch/mips/include/asm/mach-au1x00/au1000-irda.h | 18 + arch/mips/include/asm/mach-au1x00/au1000.h | 39 - drivers/net/irda/Kconfig | 9 +- drivers/net/irda/au1000_ircc.h | 125 --- drivers/net/irda/au1k_ir.c | 1140 +++++++++++++---------- 5 files changed, 664 insertions(+), 667 deletions(-) create mode 100644 arch/mips/include/asm/mach-au1x00/au1000-irda.h delete mode 100644 drivers/net/irda/au1000_ircc.h diff --git a/arch/mips/include/asm/mach-au1x00/au1000-irda.h b/arch/mips/include/asm/mach-au1x00/au1000-irda.h new file mode 100644 index 0000000..c2926d6 --- /dev/null +++ b/arch/mips/include/asm/mach-au1x00/au1000-irda.h @@ -0,0 +1,18 @@ +/* + * au1000-irda.h -- IrDA peripheral platform information. + * + * Au1000, Au1100 + */ + +#ifndef _ALCHEMY_AU1000_IRDA_H_ +#define _ALCHEMY_AU1000_IRDA_H_ + +#define AU1000_IRDA_PHY_MODE_OFF 0 +#define AU1000_IRDA_PHY_MODE_SIR 1 +#define AU1000_IRDA_PHY_MODE_FIR 2 + +struct au1k_irda_platform_data { + void(*set_phy_mode)(int mode); +}; + +#endif diff --git a/arch/mips/include/asm/mach-au1x00/au1000.h b/arch/mips/include/asm/mach-au1x00/au1000.h index b4f30df..01c6c5a 100644 --- a/arch/mips/include/asm/mach-au1x00/au1000.h +++ b/arch/mips/include/asm/mach-au1x00/au1000.h @@ -1423,45 +1423,6 @@ enum soc_au1200_ints { #define SSI_ENABLE_CD (1 << 1) #define SSI_ENABLE_E (1 << 0) -/* IrDA Controller */ -#define IRDA_BASE 0xB0300000 -#define IR_RING_PTR_STATUS (IRDA_BASE + 0x00) -#define IR_RING_BASE_ADDR_H (IRDA_BASE + 0x04) -#define IR_RING_BASE_ADDR_L (IRDA_BASE + 0x08) -#define IR_RING_SIZE (IRDA_BASE + 0x0C) -#define IR_RING_PROMPT (IRDA_BASE + 0x10) -#define IR_RING_ADDR_CMPR (IRDA_BASE + 0x14) -#define IR_INT_CLEAR (IRDA_BASE + 0x18) -#define IR_CONFIG_1 (IRDA_BASE + 0x20) -# define IR_RX_INVERT_LED (1 << 0) -# define IR_TX_INVERT_LED (1 << 1) -# define IR_ST (1 << 2) -# define IR_SF (1 << 3) -# define IR_SIR (1 << 4) -# define IR_MIR (1 << 5) -# define IR_FIR (1 << 6) -# define IR_16CRC (1 << 7) -# define IR_TD (1 << 8) -# define IR_RX_ALL (1 << 9) -# define IR_DMA_ENABLE (1 << 10) -# define IR_RX_ENABLE (1 << 11) -# define IR_TX_ENABLE (1 << 12) -# define IR_LOOPBACK (1 << 14) -# define IR_SIR_MODE (IR_SIR | IR_DMA_ENABLE | \ - IR_RX_ALL | IR_RX_ENABLE | IR_SF | IR_16CRC) -#define IR_SIR_FLAGS (IRDA_BASE + 0x24) -#define IR_ENABLE (IRDA_BASE + 0x28) -# define IR_RX_STATUS (1 << 9) -# define IR_TX_STATUS (1 << 10) -#define IR_READ_PHY_CONFIG (IRDA_BASE + 0x2C) -#define IR_WRITE_PHY_CONFIG (IRDA_BASE + 0x30) -#define IR_MAX_PKT_LEN (IRDA_BASE + 0x34) -#define IR_RX_BYTE_CNT (IRDA_BASE + 0x38) -#define IR_CONFIG_2 (IRDA_BASE + 0x3C) -# define IR_MODE_INV (1 << 0) -# define IR_ONE_PIN (1 << 1) -#define IR_INTERFACE_CONFIG (IRDA_BASE + 0x40) - /* GPIO */ #define SYS_PINFUNC 0xB190002C # define SYS_PF_USB (1 << 15) /* 2nd USB device/host */ diff --git a/drivers/net/irda/Kconfig b/drivers/net/irda/Kconfig index e631755..f55284a 100644 --- a/drivers/net/irda/Kconfig +++ b/drivers/net/irda/Kconfig @@ -258,8 +258,13 @@ config TOSHIBA_FIR donauboe. config AU1000_FIR - tristate "Alchemy Au1000 SIR/FIR" - depends on SOC_AU1000 && IRDA + tristate "Alchemy Au1xxx SIR/FIR" + depends on MACH_ALCHEMY && IRDA + help + Say Y/M here to build support for the intergrated IrDA controllers + on the Alchemy Au1000 and Au1100 SoCs. + + Say M to build a module; it will be called au1k_ir.ko config SMC_IRCC_FIR tristate "SMSC IrCC (EXPERIMENTAL)" diff --git a/drivers/net/irda/au1000_ircc.h b/drivers/net/irda/au1000_ircc.h deleted file mode 100644 index c072c09..0000000 --- a/drivers/net/irda/au1000_ircc.h +++ /dev/null @@ -1,125 +0,0 @@ -/* - * - * BRIEF MODULE DESCRIPTION - * Au1000 IrDA driver. - * - * Copyright 2001 MontaVista Software Inc. - * Author: MontaVista Software, Inc. - * ppopov@mvista.com or source@mvista.com - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#ifndef AU1000_IRCC_H -#define AU1000_IRCC_H - -#include - -#include -#include -#include - -#define NUM_IR_IFF 1 -#define NUM_IR_DESC 64 -#define RING_SIZE_4 0x0 -#define RING_SIZE_16 0x3 -#define RING_SIZE_64 0xF -#define MAX_NUM_IR_DESC 64 -#define MAX_BUF_SIZE 2048 - -#define BPS_115200 0 -#define BPS_57600 1 -#define BPS_38400 2 -#define BPS_19200 5 -#define BPS_9600 11 -#define BPS_2400 47 - -/* Ring descriptor flags */ -#define AU_OWN (1<<7) /* tx,rx */ - -#define IR_DIS_CRC (1<<6) /* tx */ -#define IR_BAD_CRC (1<<5) /* tx */ -#define IR_NEED_PULSE (1<<4) /* tx */ -#define IR_FORCE_UNDER (1<<3) /* tx */ -#define IR_DISABLE_TX (1<<2) /* tx */ -#define IR_HW_UNDER (1<<0) /* tx */ -#define IR_TX_ERROR (IR_DIS_CRC|IR_BAD_CRC|IR_HW_UNDER) - -#define IR_PHY_ERROR (1<<6) /* rx */ -#define IR_CRC_ERROR (1<<5) /* rx */ -#define IR_MAX_LEN (1<<4) /* rx */ -#define IR_FIFO_OVER (1<<3) /* rx */ -#define IR_SIR_ERROR (1<<2) /* rx */ -#define IR_RX_ERROR (IR_PHY_ERROR|IR_CRC_ERROR| \ - IR_MAX_LEN|IR_FIFO_OVER|IR_SIR_ERROR) - -typedef struct db_dest { - struct db_dest *pnext; - volatile u32 *vaddr; - dma_addr_t dma_addr; -} db_dest_t; - - -typedef struct ring_desc { - u8 count_0; /* 7:0 */ - u8 count_1; /* 12:8 */ - u8 reserved; - u8 flags; - u8 addr_0; /* 7:0 */ - u8 addr_1; /* 15:8 */ - u8 addr_2; /* 23:16 */ - u8 addr_3; /* 31:24 */ -} ring_dest_t; - - -/* Private data for each instance */ -struct au1k_private { - - db_dest_t *pDBfree; - db_dest_t db[2*NUM_IR_DESC]; - volatile ring_dest_t *rx_ring[NUM_IR_DESC]; - volatile ring_dest_t *tx_ring[NUM_IR_DESC]; - db_dest_t *rx_db_inuse[NUM_IR_DESC]; - db_dest_t *tx_db_inuse[NUM_IR_DESC]; - u32 rx_head; - u32 tx_head; - u32 tx_tail; - u32 tx_full; - - iobuff_t rx_buff; - - struct net_device *netdev; - - struct timeval stamp; - struct timeval now; - struct qos_info qos; - struct irlap_cb *irlap; - - u8 open; - u32 speed; - u32 newspeed; - - u32 intr_work_done; /* number of Rx and Tx pkts processed in the isr */ - struct timer_list timer; - - spinlock_t lock; /* For serializing operations */ -}; -#endif /* AU1000_IRCC_H */ diff --git a/drivers/net/irda/au1k_ir.c b/drivers/net/irda/au1k_ir.c index 9411640..3ecb631 100644 --- a/drivers/net/irda/au1k_ir.c +++ b/drivers/net/irda/au1k_ir.c @@ -18,96 +18,197 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. */ -#include -#include + #include -#include +#include #include -#include -#include #include -#include -#include - -#include -#include -#include -#if defined(CONFIG_MIPS_PB1000) || defined(CONFIG_MIPS_PB1100) -#include -#elif defined(CONFIG_MIPS_DB1000) || defined(CONFIG_MIPS_DB1100) -#include -#else -#error au1k_ir: unsupported board -#endif +#include +#include +#include +#include +#include #include #include #include #include -#include "au1000_ircc.h" -static int au1k_irda_net_init(struct net_device *); -static int au1k_irda_start(struct net_device *); -static int au1k_irda_stop(struct net_device *dev); -static int au1k_irda_hard_xmit(struct sk_buff *, struct net_device *); -static int au1k_irda_rx(struct net_device *); -static void au1k_irda_interrupt(int, void *); -static void au1k_tx_timeout(struct net_device *); -static int au1k_irda_ioctl(struct net_device *, struct ifreq *, int); -static int au1k_irda_set_speed(struct net_device *dev, int speed); +#include +#include + +/* registers */ +#define IR_RING_PTR_STATUS 0x00 +#define IR_RING_BASE_ADDR_H 0x04 +#define IR_RING_BASE_ADDR_L 0x08 +#define IR_RING_SIZE 0x0C +#define IR_RING_PROMPT 0x10 +#define IR_RING_ADDR_CMPR 0x14 +#define IR_INT_CLEAR 0x18 +#define IR_CONFIG_1 0x20 +#define IR_SIR_FLAGS 0x24 +#define IR_ENABLE 0x28 +#define IR_READ_PHY_CONFIG 0x2C +#define IR_WRITE_PHY_CONFIG 0x30 +#define IR_MAX_PKT_LEN 0x34 +#define IR_RX_BYTE_CNT 0x38 +#define IR_CONFIG_2 0x3C +#define IR_INTERFACE_CONFIG 0x40 + +/* Config1 */ +#define IR_RX_INVERT_LED (1 << 0) +#define IR_TX_INVERT_LED (1 << 1) +#define IR_ST (1 << 2) +#define IR_SF (1 << 3) +#define IR_SIR (1 << 4) +#define IR_MIR (1 << 5) +#define IR_FIR (1 << 6) +#define IR_16CRC (1 << 7) +#define IR_TD (1 << 8) +#define IR_RX_ALL (1 << 9) +#define IR_DMA_ENABLE (1 << 10) +#define IR_RX_ENABLE (1 << 11) +#define IR_TX_ENABLE (1 << 12) +#define IR_LOOPBACK (1 << 14) +#define IR_SIR_MODE (IR_SIR | IR_DMA_ENABLE | \ + IR_RX_ALL | IR_RX_ENABLE | IR_SF | \ + IR_16CRC) + +/* ir_enable */ +#define IR_RX_STATUS (1 << 9) +#define IR_TX_STATUS (1 << 10) +/* Config2 */ +#define IR_MODE_INV (1 << 0) +#define IR_ONE_PIN (1 << 1) + + +#define NUM_IR_DESC 64 +#define RING_SIZE_4 0x0 +#define RING_SIZE_16 0x3 +#define RING_SIZE_64 0xF +#define MAX_NUM_IR_DESC 64 +#define MAX_BUF_SIZE 2048 + +/* Ring descriptor flags */ +#define AU_OWN (1<<7) /* tx,rx */ + +#define IR_DIS_CRC (1<<6) /* tx */ +#define IR_BAD_CRC (1<<5) /* tx */ +#define IR_NEED_PULSE (1<<4) /* tx */ +#define IR_FORCE_UNDER (1<<3) /* tx */ +#define IR_DISABLE_TX (1<<2) /* tx */ +#define IR_HW_UNDER (1<<0) /* tx */ +#define IR_TX_ERROR (IR_DIS_CRC | IR_BAD_CRC | IR_HW_UNDER) + +#define IR_PHY_ERROR (1<<6) /* rx */ +#define IR_CRC_ERROR (1<<5) /* rx */ +#define IR_MAX_LEN (1<<4) /* rx */ +#define IR_FIFO_OVER (1<<3) /* rx */ +#define IR_SIR_ERROR (1<<2) /* rx */ +#define IR_RX_ERROR (IR_PHY_ERROR | IR_CRC_ERROR | \ + IR_MAX_LEN | IR_FIFO_OVER | IR_SIR_ERROR) + +struct db_dest { + struct db_dest *pnext; + volatile u32 *vaddr; + dma_addr_t dma_addr; +}; + +struct ring_dest { + u8 count_0; /* 7:0 */ + u8 count_1; /* 12:8 */ + u8 reserved; + u8 flags; + u8 addr_0; /* 7:0 */ + u8 addr_1; /* 15:8 */ + u8 addr_2; /* 23:16 */ + u8 addr_3; /* 31:24 */ +}; + +/* Private data for each instance */ +struct au1k_private { + void __iomem *iobase; + int irq_rx, irq_tx; + + struct db_dest *pDBfree; + struct db_dest db[2*NUM_IR_DESC]; + volatile struct ring_dest *rx_ring[NUM_IR_DESC]; + volatile struct ring_dest *tx_ring[NUM_IR_DESC]; + struct db_dest *rx_db_inuse[NUM_IR_DESC]; + struct db_dest *tx_db_inuse[NUM_IR_DESC]; + u32 rx_head; + u32 tx_head; + u32 tx_tail; + u32 tx_full; + + iobuff_t rx_buff; + + struct net_device *netdev; + struct net_device_stats stats; + struct timeval stamp; + struct timeval now; + struct qos_info qos; + struct irlap_cb *irlap; + + u8 open; + u32 speed; + u32 newspeed; -static void *dma_alloc(size_t, dma_addr_t *); -static void dma_free(void *, size_t); + struct timer_list timer; + + spinlock_t lock; /* For serializing operations */ + struct resource *ioarea; + struct au1k_irda_platform_data *platdata; +}; static int qos_mtt_bits = 0x07; /* 1 ms or more */ -static struct net_device *ir_devs[NUM_IR_IFF]; static char version[] __devinitdata = "au1k_ircc:1.2 ppopov@mvista.com\n"; #define RUN_AT(x) (jiffies + (x)) -#if defined(CONFIG_MIPS_DB1000) || defined(CONFIG_MIPS_DB1100) -static BCSR * const bcsr = (BCSR *)0xAE000000; -#endif static DEFINE_SPINLOCK(ir_lock); +static void au1k_irda_plat_set_phy_mode(struct au1k_private *p, int mode) +{ + if (p->platdata && p->platdata->set_phy_mode) + p->platdata->set_phy_mode(mode); +} + +static inline unsigned long irda_read(struct au1k_private *p, + unsigned long ofs) +{ /* * IrDA peripheral bug. You have to read the register * twice to get the right value. */ -u32 read_ir_reg(u32 addr) -{ - readl(addr); - return readl(addr); + (void)au_readl((unsigned long)(p->iobase) + ofs); + return au_readl((unsigned long)(p->iobase) + ofs); } +static inline void irda_write(struct au1k_private *p, unsigned long ofs, + unsigned long val) +{ + au_writel(val, (unsigned long)(p->iobase) + ofs); +} /* * Buffer allocation/deallocation routines. The buffer descriptor returned - * has the virtual and dma address of a buffer suitable for + * has the virtual and dma address of a buffer suitable for * both, receive and transmit operations. */ -static db_dest_t *GetFreeDB(struct au1k_private *aup) +static struct db_dest *GetFreeDB(struct au1k_private *aup) { - db_dest_t *pDB; - pDB = aup->pDBfree; + struct db_dest *db; + db = aup->pDBfree; - if (pDB) { - aup->pDBfree = pDB->pnext; - } - return pDB; -} + if (db) + aup->pDBfree = db->pnext; -static void ReleaseDB(struct au1k_private *aup, db_dest_t *pDB) -{ - db_dest_t *pDBfree = aup->pDBfree; - if (pDBfree) - pDBfree->pnext = pDB; - aup->pDBfree = pDB; + return db; } - /* DMA memory allocation, derived from pci_alloc_consistent. However, the Au1000 data cache is coherent (when programmed @@ -136,56 +237,20 @@ static void dma_free(void *vaddr, size_t size) } -static void +static void setup_hw_rings(struct au1k_private *aup, u32 rx_base, u32 tx_base) { int i; for (i=0; irx_ring[i] = (volatile ring_dest_t *) - (rx_base + sizeof(ring_dest_t)*i); + aup->rx_ring[i] = (volatile struct ring_dest *) + (rx_base + sizeof(struct ring_dest)*i); } for (i=0; itx_ring[i] = (volatile ring_dest_t *) - (tx_base + sizeof(ring_dest_t)*i); + aup->tx_ring[i] = (volatile struct ring_dest *) + (tx_base + sizeof(struct ring_dest)*i); } } -static int au1k_irda_init(void) -{ - static unsigned version_printed = 0; - struct au1k_private *aup; - struct net_device *dev; - int err; - - if (version_printed++ == 0) printk(version); - - dev = alloc_irdadev(sizeof(struct au1k_private)); - if (!dev) - return -ENOMEM; - - dev->irq = AU1000_IRDA_RX_INT; /* TX has its own interrupt */ - err = au1k_irda_net_init(dev); - if (err) - goto out; - err = register_netdev(dev); - if (err) - goto out1; - ir_devs[0] = dev; - printk(KERN_INFO "IrDA: Registered device %s\n", dev->name); - return 0; - -out1: - aup = netdev_priv(dev); - dma_free((void *)aup->db[0].vaddr, - MAX_BUF_SIZE * 2*NUM_IR_DESC); - dma_free((void *)aup->rx_ring[0], - 2 * MAX_NUM_IR_DESC*(sizeof(ring_dest_t))); - kfree(aup->rx_buff.head); -out: - free_netdev(dev); - return err; -} - static int au1k_irda_init_iobuf(iobuff_t *io, int size) { io->head = kmalloc(size, GFP_KERNEL); @@ -198,104 +263,123 @@ static int au1k_irda_init_iobuf(iobuff_t *io, int size) return io->head ? 0 : -ENOMEM; } -static int au1k_irda_net_init(struct net_device *dev) +/* + * Set the IrDA communications speed. + */ +static int au1k_irda_set_speed(struct net_device *dev, int speed) { + unsigned long flags; struct au1k_private *aup = netdev_priv(dev); - int i, retval = 0, err; - db_dest_t *pDB, *pDBfree; - dma_addr_t temp; + u32 control; + int ret = 0, timeout = 10, i; + volatile struct ring_dest *ptxd; - err = au1k_irda_init_iobuf(&aup->rx_buff, 14384); - if (err) - goto out1; + if (speed == aup->speed) + return ret; - dev->open = au1k_irda_start; - dev->hard_start_xmit = au1k_irda_hard_xmit; - dev->stop = au1k_irda_stop; - dev->do_ioctl = au1k_irda_ioctl; - dev->tx_timeout = au1k_tx_timeout; + spin_lock_irqsave(&ir_lock, flags); - irda_init_max_qos_capabilies(&aup->qos); + /* disable PHY first */ + irda_write(aup, IR_ENABLE, irda_read(aup, IR_ENABLE) & ~0x8000); - /* The only value we must override it the baudrate */ - aup->qos.baud_rate.bits = IR_9600|IR_19200|IR_38400|IR_57600| - IR_115200|IR_576000 |(IR_4000000 << 8); - - aup->qos.min_turn_time.bits = qos_mtt_bits; - irda_qos_bits_to_value(&aup->qos); + /* disable RX/TX */ + irda_write(aup, IR_CONFIG_1, + irda_read(aup, IR_CONFIG_1) & ~(IR_RX_ENABLE | IR_TX_ENABLE)); + au_sync_delay(1); + while (irda_read(aup, IR_ENABLE) & (IR_RX_STATUS | IR_TX_STATUS)) { + mdelay(1); + if (!timeout--) { + printk(KERN_ERR "%s: rx/tx disable timeout\n", + dev->name); + break; + } + } - retval = -ENOMEM; + /* disable DMA */ + irda_write(aup, IR_CONFIG_1, + irda_read(aup, IR_CONFIG_1) & ~IR_DMA_ENABLE); + au_sync_delay(1); - /* Tx ring follows rx ring + 512 bytes */ - /* we need a 1k aligned buffer */ - aup->rx_ring[0] = (ring_dest_t *) - dma_alloc(2*MAX_NUM_IR_DESC*(sizeof(ring_dest_t)), &temp); - if (!aup->rx_ring[0]) - goto out2; + /* After we disable tx/rx. the index pointers go back to zero. */ + aup->tx_head = aup->tx_tail = aup->rx_head = 0; + for (i = 0; i < NUM_IR_DESC; i++) { + ptxd = aup->tx_ring[i]; + ptxd->flags = 0; + ptxd->count_0 = 0; + ptxd->count_1 = 0; + } - /* allocate the data buffers */ - aup->db[0].vaddr = - (void *)dma_alloc(MAX_BUF_SIZE * 2*NUM_IR_DESC, &temp); - if (!aup->db[0].vaddr) - goto out3; + for (i = 0; i < NUM_IR_DESC; i++) { + ptxd = aup->rx_ring[i]; + ptxd->count_0 = 0; + ptxd->count_1 = 0; + ptxd->flags = AU_OWN; + } - setup_hw_rings(aup, (u32)aup->rx_ring[0], (u32)aup->rx_ring[0] + 512); + if (speed == 4000000) + au1k_irda_plat_set_phy_mode(aup, AU1000_IRDA_PHY_MODE_FIR); + else + au1k_irda_plat_set_phy_mode(aup, AU1000_IRDA_PHY_MODE_SIR); - pDBfree = NULL; - pDB = aup->db; - for (i=0; i<(2*NUM_IR_DESC); i++) { - pDB->pnext = pDBfree; - pDBfree = pDB; - pDB->vaddr = - (u32 *)((unsigned)aup->db[0].vaddr + MAX_BUF_SIZE*i); - pDB->dma_addr = (dma_addr_t)virt_to_bus(pDB->vaddr); - pDB++; + switch (speed) { + case 9600: + irda_write(aup, IR_WRITE_PHY_CONFIG, 11<<10 | 12<<5); + irda_write(aup, IR_CONFIG_1, IR_SIR_MODE); + break; + case 19200: + irda_write(aup, IR_WRITE_PHY_CONFIG, 5<<10 | 12<<5); + irda_write(aup, IR_CONFIG_1, IR_SIR_MODE); + break; + case 38400: + irda_write(aup, IR_WRITE_PHY_CONFIG, 2<<10 | 12<<5); + irda_write(aup, IR_CONFIG_1, IR_SIR_MODE); + break; + case 57600: + irda_write(aup, IR_WRITE_PHY_CONFIG, 1<<10 | 12<<5); + irda_write(aup, IR_CONFIG_1, IR_SIR_MODE); + break; + case 115200: + irda_write(aup, IR_WRITE_PHY_CONFIG, 12<<5); + irda_write(aup, IR_CONFIG_1, IR_SIR_MODE); + break; + case 4000000: + irda_write(aup, IR_WRITE_PHY_CONFIG, 0xf); + irda_write(aup, IR_CONFIG_1, IR_FIR | IR_DMA_ENABLE | + IR_RX_ENABLE); + break; + default: + printk(KERN_ERR "%s unsupported speed %x\n", dev->name, speed); + ret = -EINVAL; + break; } - aup->pDBfree = pDBfree; - /* attach a data buffer to each descriptor */ - for (i=0; irx_ring[i]->addr_0 = (u8)(pDB->dma_addr & 0xff); - aup->rx_ring[i]->addr_1 = (u8)((pDB->dma_addr>>8) & 0xff); - aup->rx_ring[i]->addr_2 = (u8)((pDB->dma_addr>>16) & 0xff); - aup->rx_ring[i]->addr_3 = (u8)((pDB->dma_addr>>24) & 0xff); - aup->rx_db_inuse[i] = pDB; - } - for (i=0; itx_ring[i]->addr_0 = (u8)(pDB->dma_addr & 0xff); - aup->tx_ring[i]->addr_1 = (u8)((pDB->dma_addr>>8) & 0xff); - aup->tx_ring[i]->addr_2 = (u8)((pDB->dma_addr>>16) & 0xff); - aup->tx_ring[i]->addr_3 = (u8)((pDB->dma_addr>>24) & 0xff); - aup->tx_ring[i]->count_0 = 0; - aup->tx_ring[i]->count_1 = 0; - aup->tx_ring[i]->flags = 0; - aup->tx_db_inuse[i] = pDB; - } + aup->speed = speed; + irda_write(aup, IR_ENABLE, irda_read(aup, IR_ENABLE) | 0x8000); + au_sync(); -#if defined(CONFIG_MIPS_DB1000) || defined(CONFIG_MIPS_DB1100) - /* power on */ - bcsr->resets &= ~BCSR_RESETS_IRDA_MODE_MASK; - bcsr->resets |= BCSR_RESETS_IRDA_MODE_FULL; + control = irda_read(aup, IR_ENABLE); + irda_write(aup, IR_RING_PROMPT, 0); au_sync(); -#endif - return 0; + if (control & (1<<14)) { + printk(KERN_ERR "%s: configuration error\n", dev->name); + } else { + if (control & (1<<11)) + printk(KERN_DEBUG "%s Valid SIR config\n", dev->name); + if (control & (1<<12)) + printk(KERN_DEBUG "%s Valid MIR config\n", dev->name); + if (control & (1<<13)) + printk(KERN_DEBUG "%s Valid FIR config\n", dev->name); + if (control & (1<<10)) + printk(KERN_DEBUG "%s TX enabled\n", dev->name); + if (control & (1<<9)) + printk(KERN_DEBUG "%s RX enabled\n", dev->name); + } -out3: - dma_free((void *)aup->rx_ring[0], - 2 * MAX_NUM_IR_DESC*(sizeof(ring_dest_t))); -out2: - kfree(aup->rx_buff.head); -out1: - printk(KERN_ERR "au1k_init_module failed. Returns %d\n", retval); - return retval; + spin_unlock_irqrestore(&ir_lock, flags); + return ret; } - static int au1k_init(struct net_device *dev) { struct au1k_private *aup = netdev_priv(dev); @@ -305,7 +389,7 @@ static int au1k_init(struct net_device *dev) /* bring the device out of reset */ control = 0xe; /* coherent, clock enable, one half system clock */ - + #ifndef CONFIG_CPU_LITTLE_ENDIAN control |= 1; #endif @@ -317,106 +401,48 @@ static int au1k_init(struct net_device *dev) aup->rx_ring[i]->flags = AU_OWN; } - writel(control, IR_INTERFACE_CONFIG); + irda_write(aup, IR_INTERFACE_CONFIG, control); au_sync_delay(10); - writel(read_ir_reg(IR_ENABLE) & ~0x8000, IR_ENABLE); /* disable PHY */ + /* disable PHY */ + irda_write(aup, IR_ENABLE, irda_read(aup, IR_ENABLE) & ~0x8000); au_sync_delay(1); - writel(MAX_BUF_SIZE, IR_MAX_PKT_LEN); + irda_write(aup, IR_MAX_PKT_LEN, MAX_BUF_SIZE); ring_address = (u32)virt_to_phys((void *)aup->rx_ring[0]); - writel(ring_address >> 26, IR_RING_BASE_ADDR_H); - writel((ring_address >> 10) & 0xffff, IR_RING_BASE_ADDR_L); + irda_write(aup, IR_RING_BASE_ADDR_H, ring_address >> 26); + irda_write(aup, IR_RING_BASE_ADDR_L, (ring_address >> 10) & 0xffff); - writel(RING_SIZE_64<<8 | RING_SIZE_64<<12, IR_RING_SIZE); + irda_write(aup, IR_RING_SIZE, RING_SIZE_64<<8 | RING_SIZE_64<<12); - writel(1<<2 | IR_ONE_PIN, IR_CONFIG_2); /* 48MHz */ - writel(0, IR_RING_ADDR_CMPR); + irda_write(aup, IR_CONFIG_2, 1<<2 | IR_ONE_PIN); /* 48MHz */ + irda_write(aup, IR_RING_ADDR_CMPR, 0); au1k_irda_set_speed(dev, 9600); return 0; } -static int au1k_irda_start(struct net_device *dev) -{ - int retval; - char hwname[32]; - struct au1k_private *aup = netdev_priv(dev); - - if ((retval = au1k_init(dev))) { - printk(KERN_ERR "%s: error in au1k_init\n", dev->name); - return retval; - } - - if ((retval = request_irq(AU1000_IRDA_TX_INT, &au1k_irda_interrupt, - 0, dev->name, dev))) { - printk(KERN_ERR "%s: unable to get IRQ %d\n", - dev->name, dev->irq); - return retval; - } - if ((retval = request_irq(AU1000_IRDA_RX_INT, &au1k_irda_interrupt, - 0, dev->name, dev))) { - free_irq(AU1000_IRDA_TX_INT, dev); - printk(KERN_ERR "%s: unable to get IRQ %d\n", - dev->name, dev->irq); - return retval; - } - - /* Give self a hardware name */ - sprintf(hwname, "Au1000 SIR/FIR"); - aup->irlap = irlap_open(dev, &aup->qos, hwname); - netif_start_queue(dev); - - writel(read_ir_reg(IR_CONFIG_2) | 1<<8, IR_CONFIG_2); /* int enable */ - - aup->timer.expires = RUN_AT((3*HZ)); - aup->timer.data = (unsigned long)dev; - return 0; -} - -static int au1k_irda_stop(struct net_device *dev) -{ - struct au1k_private *aup = netdev_priv(dev); - - /* disable interrupts */ - writel(read_ir_reg(IR_CONFIG_2) & ~(1<<8), IR_CONFIG_2); - writel(0, IR_CONFIG_1); - writel(0, IR_INTERFACE_CONFIG); /* disable clock */ - au_sync(); - - if (aup->irlap) { - irlap_close(aup->irlap); - aup->irlap = NULL; - } - - netif_stop_queue(dev); - del_timer(&aup->timer); - - /* disable the interrupt */ - free_irq(AU1000_IRDA_TX_INT, dev); - free_irq(AU1000_IRDA_RX_INT, dev); - return 0; -} - -static void __exit au1k_irda_exit(void) +static void update_rx_stats(struct net_device *dev, u32 status, u32 count) { - struct net_device *dev = ir_devs[0]; struct au1k_private *aup = netdev_priv(dev); + struct net_device_stats *ps = &aup->stats; - unregister_netdev(dev); + ps->rx_packets++; - dma_free((void *)aup->db[0].vaddr, - MAX_BUF_SIZE * 2*NUM_IR_DESC); - dma_free((void *)aup->rx_ring[0], - 2 * MAX_NUM_IR_DESC*(sizeof(ring_dest_t))); - kfree(aup->rx_buff.head); - free_netdev(dev); + if (status & IR_RX_ERROR) { + ps->rx_errors++; + if (status & (IR_PHY_ERROR | IR_FIFO_OVER)) + ps->rx_missed_errors++; + if (status & IR_MAX_LEN) + ps->rx_length_errors++; + if (status & IR_CRC_ERROR) + ps->rx_crc_errors++; + } else + ps->rx_bytes += count; } - -static inline void -update_tx_stats(struct net_device *dev, u32 status, u32 pkt_len) +static void update_tx_stats(struct net_device *dev, u32 status, u32 pkt_len) { struct au1k_private *aup = netdev_priv(dev); struct net_device_stats *ps = &aup->stats; @@ -430,15 +456,14 @@ update_tx_stats(struct net_device *dev, u32 status, u32 pkt_len) } } - static void au1k_tx_ack(struct net_device *dev) { struct au1k_private *aup = netdev_priv(dev); - volatile ring_dest_t *ptxd; + volatile struct ring_dest *ptxd; ptxd = aup->tx_ring[aup->tx_tail]; while (!(ptxd->flags & AU_OWN) && (aup->tx_tail != aup->tx_head)) { - update_tx_stats(dev, ptxd->flags, + update_tx_stats(dev, ptxd->flags, ptxd->count_1<<8 | ptxd->count_0); ptxd->count_0 = 0; ptxd->count_1 = 0; @@ -457,131 +482,28 @@ static void au1k_tx_ack(struct net_device *dev) if (aup->newspeed) { au1k_irda_set_speed(dev, aup->newspeed); aup->newspeed = 0; - } - else { - writel(read_ir_reg(IR_CONFIG_1) & ~IR_TX_ENABLE, - IR_CONFIG_1); + } else { + irda_write(aup, IR_CONFIG_1, + irda_read(aup, IR_CONFIG_1) & ~IR_TX_ENABLE); au_sync(); - writel(read_ir_reg(IR_CONFIG_1) | IR_RX_ENABLE, - IR_CONFIG_1); - writel(0, IR_RING_PROMPT); + irda_write(aup, IR_CONFIG_1, + irda_read(aup, IR_CONFIG_1) | IR_RX_ENABLE); + irda_write(aup, IR_RING_PROMPT, 0); au_sync(); } } } - -/* - * Au1000 transmit routine. - */ -static int au1k_irda_hard_xmit(struct sk_buff *skb, struct net_device *dev) -{ - struct au1k_private *aup = netdev_priv(dev); - int speed = irda_get_next_speed(skb); - volatile ring_dest_t *ptxd; - u32 len; - - u32 flags; - db_dest_t *pDB; - - if (speed != aup->speed && speed != -1) { - aup->newspeed = speed; - } - - if ((skb->len == 0) && (aup->newspeed)) { - if (aup->tx_tail == aup->tx_head) { - au1k_irda_set_speed(dev, speed); - aup->newspeed = 0; - } - dev_kfree_skb(skb); - return 0; - } - - ptxd = aup->tx_ring[aup->tx_head]; - flags = ptxd->flags; - - if (flags & AU_OWN) { - printk(KERN_DEBUG "%s: tx_full\n", dev->name); - netif_stop_queue(dev); - aup->tx_full = 1; - return 1; - } - else if (((aup->tx_head + 1) & (NUM_IR_DESC - 1)) == aup->tx_tail) { - printk(KERN_DEBUG "%s: tx_full\n", dev->name); - netif_stop_queue(dev); - aup->tx_full = 1; - return 1; - } - - pDB = aup->tx_db_inuse[aup->tx_head]; - -#if 0 - if (read_ir_reg(IR_RX_BYTE_CNT) != 0) { - printk("tx warning: rx byte cnt %x\n", - read_ir_reg(IR_RX_BYTE_CNT)); - } -#endif - - if (aup->speed == 4000000) { - /* FIR */ - skb_copy_from_linear_data(skb, pDB->vaddr, skb->len); - ptxd->count_0 = skb->len & 0xff; - ptxd->count_1 = (skb->len >> 8) & 0xff; - - } - else { - /* SIR */ - len = async_wrap_skb(skb, (u8 *)pDB->vaddr, MAX_BUF_SIZE); - ptxd->count_0 = len & 0xff; - ptxd->count_1 = (len >> 8) & 0xff; - ptxd->flags |= IR_DIS_CRC; - au_writel(au_readl(0xae00000c) & ~(1<<13), 0xae00000c); - } - ptxd->flags |= AU_OWN; - au_sync(); - - writel(read_ir_reg(IR_CONFIG_1) | IR_TX_ENABLE, IR_CONFIG_1); - writel(0, IR_RING_PROMPT); - au_sync(); - - dev_kfree_skb(skb); - aup->tx_head = (aup->tx_head + 1) & (NUM_IR_DESC - 1); - dev->trans_start = jiffies; - return 0; -} - - -static inline void -update_rx_stats(struct net_device *dev, u32 status, u32 count) -{ - struct au1k_private *aup = netdev_priv(dev); - struct net_device_stats *ps = &aup->stats; - - ps->rx_packets++; - - if (status & IR_RX_ERROR) { - ps->rx_errors++; - if (status & (IR_PHY_ERROR|IR_FIFO_OVER)) - ps->rx_missed_errors++; - if (status & IR_MAX_LEN) - ps->rx_length_errors++; - if (status & IR_CRC_ERROR) - ps->rx_crc_errors++; - } - else - ps->rx_bytes += count; -} - /* * Au1000 receive routine. */ static int au1k_irda_rx(struct net_device *dev) { struct au1k_private *aup = netdev_priv(dev); + volatile struct ring_dest *prxd; struct sk_buff *skb; - volatile ring_dest_t *prxd; + struct db_dest *pDB; u32 flags, count; - db_dest_t *pDB; prxd = aup->rx_ring[aup->rx_head]; flags = prxd->flags; @@ -589,10 +511,10 @@ static int au1k_irda_rx(struct net_device *dev) while (!(flags & AU_OWN)) { pDB = aup->rx_db_inuse[aup->rx_head]; count = prxd->count_1<<8 | prxd->count_0; - if (!(flags & IR_RX_ERROR)) { + if (!(flags & IR_RX_ERROR)) { /* good frame */ update_rx_stats(dev, flags, count); - skb=alloc_skb(count+1,GFP_ATOMIC); + skb = alloc_skb(count + 1, GFP_ATOMIC); if (skb == NULL) { aup->netdev->stats.rx_dropped++; continue; @@ -602,7 +524,8 @@ static int au1k_irda_rx(struct net_device *dev) skb_put(skb, count); else skb_put(skb, count-2); - skb_copy_to_linear_data(skb, pDB->vaddr, count - 2); + skb_copy_to_linear_data(skb, (void *)pDB->vaddr, + count - 2); skb->dev = dev; skb_reset_mac_header(skb); skb->protocol = htons(ETH_P_IRDA); @@ -612,7 +535,7 @@ static int au1k_irda_rx(struct net_device *dev) } prxd->flags |= AU_OWN; aup->rx_head = (aup->rx_head + 1) & (NUM_IR_DESC - 1); - writel(0, IR_RING_PROMPT); + irda_write(aup, IR_RING_PROMPT, 0); au_sync(); /* next descriptor */ @@ -623,12 +546,12 @@ static int au1k_irda_rx(struct net_device *dev) return 0; } - static irqreturn_t au1k_irda_interrupt(int dummy, void *dev_id) { struct net_device *dev = dev_id; + struct au1k_private *aup = netdev_priv(dev); - writel(0, IR_INT_CLEAR); /* ack irda interrupts */ + irda_write(aup, IR_INT_CLEAR, 0); /* ack irda interrupts */ au1k_irda_rx(dev); au1k_tx_ack(dev); @@ -636,159 +559,168 @@ static irqreturn_t au1k_irda_interrupt(int dummy, void *dev_id) return IRQ_HANDLED; } - -/* - * The Tx ring has been full longer than the watchdog timeout - * value. The transmitter must be hung? - */ -static void au1k_tx_timeout(struct net_device *dev) +static int au1k_irda_start(struct net_device *dev) { - u32 speed; + int retval; + char hwname[32]; struct au1k_private *aup = netdev_priv(dev); - printk(KERN_ERR "%s: tx timeout\n", dev->name); - speed = aup->speed; - aup->speed = 0; - au1k_irda_set_speed(dev, speed); - aup->tx_full = 0; - netif_wake_queue(dev); + retval = au1k_init(dev); + if (retval) { + printk(KERN_ERR "%s: error in au1k_init\n", dev->name); + return retval; + } + + retval = request_irq(aup->irq_tx, &au1k_irda_interrupt, 0, + dev->name, dev); + if (retval) { + printk(KERN_ERR "%s: unable to get IRQ %d\n", + dev->name, dev->irq); + return retval; + } + retval = request_irq(aup->irq_rx, &au1k_irda_interrupt, 0, + dev->name, dev); + if (retval) { + free_irq(aup->irq_tx, dev); + printk(KERN_ERR "%s: unable to get IRQ %d\n", + dev->name, dev->irq); + return retval; + } + + /* Give self a hardware name */ + sprintf(hwname, "Au1000 SIR/FIR"); + aup->irlap = irlap_open(dev, &aup->qos, hwname); + netif_start_queue(dev); + + /* int enable */ + irda_write(aup, IR_CONFIG_2, irda_read(aup, IR_CONFIG_2) | 1<<8); + + /* power up */ + au1k_irda_plat_set_phy_mode(aup, AU1000_IRDA_PHY_MODE_SIR); + + aup->timer.expires = RUN_AT((3*HZ)); + aup->timer.data = (unsigned long)dev; + return 0; } +static int au1k_irda_stop(struct net_device *dev) +{ + struct au1k_private *aup = netdev_priv(dev); + + au1k_irda_plat_set_phy_mode(aup, AU1000_IRDA_PHY_MODE_OFF); + + /* disable interrupts */ + irda_write(aup, IR_CONFIG_2, irda_read(aup, IR_CONFIG_2) & ~(1<<8)); + irda_write(aup, IR_CONFIG_1, 0); + irda_write(aup, IR_INTERFACE_CONFIG, 0); /* disable clock */ + au_sync(); + + if (aup->irlap) { + irlap_close(aup->irlap); + aup->irlap = NULL; + } + + netif_stop_queue(dev); + del_timer(&aup->timer); + + /* disable the interrupt */ + free_irq(aup->irq_tx, dev); + free_irq(aup->irq_rx, dev); + + return 0; +} /* - * Set the IrDA communications speed. + * Au1000 transmit routine. */ -static int -au1k_irda_set_speed(struct net_device *dev, int speed) +static int au1k_irda_hard_xmit(struct sk_buff *skb, struct net_device *dev) { - unsigned long flags; struct au1k_private *aup = netdev_priv(dev); - u32 control; - int ret = 0, timeout = 10, i; - volatile ring_dest_t *ptxd; -#if defined(CONFIG_MIPS_DB1000) || defined(CONFIG_MIPS_DB1100) - unsigned long irda_resets; -#endif - - if (speed == aup->speed) - return ret; - - spin_lock_irqsave(&ir_lock, flags); + int speed = irda_get_next_speed(skb); + volatile struct ring_dest *ptxd; + struct db_dest *pDB; + u32 len, flags; - /* disable PHY first */ - writel(read_ir_reg(IR_ENABLE) & ~0x8000, IR_ENABLE); + if (speed != aup->speed && speed != -1) + aup->newspeed = speed; - /* disable RX/TX */ - writel(read_ir_reg(IR_CONFIG_1) & ~(IR_RX_ENABLE|IR_TX_ENABLE), - IR_CONFIG_1); - au_sync_delay(1); - while (read_ir_reg(IR_ENABLE) & (IR_RX_STATUS | IR_TX_STATUS)) { - mdelay(1); - if (!timeout--) { - printk(KERN_ERR "%s: rx/tx disable timeout\n", - dev->name); - break; + if ((skb->len == 0) && (aup->newspeed)) { + if (aup->tx_tail == aup->tx_head) { + au1k_irda_set_speed(dev, speed); + aup->newspeed = 0; } + dev_kfree_skb(skb); + return 0; } - /* disable DMA */ - writel(read_ir_reg(IR_CONFIG_1) & ~IR_DMA_ENABLE, IR_CONFIG_1); - au_sync_delay(1); + ptxd = aup->tx_ring[aup->tx_head]; + flags = ptxd->flags; - /* - * After we disable tx/rx. the index pointers - * go back to zero. - */ - aup->tx_head = aup->tx_tail = aup->rx_head = 0; - for (i=0; itx_ring[i]; - ptxd->flags = 0; - ptxd->count_0 = 0; - ptxd->count_1 = 0; + if (flags & AU_OWN) { + printk(KERN_DEBUG "%s: tx_full\n", dev->name); + netif_stop_queue(dev); + aup->tx_full = 1; + return 1; + } else if (((aup->tx_head + 1) & (NUM_IR_DESC - 1)) == aup->tx_tail) { + printk(KERN_DEBUG "%s: tx_full\n", dev->name); + netif_stop_queue(dev); + aup->tx_full = 1; + return 1; } - for (i=0; irx_ring[i]; - ptxd->count_0 = 0; - ptxd->count_1 = 0; - ptxd->flags = AU_OWN; - } + pDB = aup->tx_db_inuse[aup->tx_head]; - if (speed == 4000000) { -#if defined(CONFIG_MIPS_DB1000) || defined(CONFIG_MIPS_DB1100) - bcsr->resets |= BCSR_RESETS_FIR_SEL; -#else /* Pb1000 and Pb1100 */ - writel(1<<13, CPLD_AUX1); -#endif +#if 0 + if (irda_read(aup, IR_RX_BYTE_CNT) != 0) { + printk(KERN_DEBUG "tx warning: rx byte cnt %x\n", + irda_read(aup, IR_RX_BYTE_CNT)); } - else { -#if defined(CONFIG_MIPS_DB1000) || defined(CONFIG_MIPS_DB1100) - bcsr->resets &= ~BCSR_RESETS_FIR_SEL; -#else /* Pb1000 and Pb1100 */ - writel(readl(CPLD_AUX1) & ~(1<<13), CPLD_AUX1); #endif - } - switch (speed) { - case 9600: - writel(11<<10 | 12<<5, IR_WRITE_PHY_CONFIG); - writel(IR_SIR_MODE, IR_CONFIG_1); - break; - case 19200: - writel(5<<10 | 12<<5, IR_WRITE_PHY_CONFIG); - writel(IR_SIR_MODE, IR_CONFIG_1); - break; - case 38400: - writel(2<<10 | 12<<5, IR_WRITE_PHY_CONFIG); - writel(IR_SIR_MODE, IR_CONFIG_1); - break; - case 57600: - writel(1<<10 | 12<<5, IR_WRITE_PHY_CONFIG); - writel(IR_SIR_MODE, IR_CONFIG_1); - break; - case 115200: - writel(12<<5, IR_WRITE_PHY_CONFIG); - writel(IR_SIR_MODE, IR_CONFIG_1); - break; - case 4000000: - writel(0xF, IR_WRITE_PHY_CONFIG); - writel(IR_FIR|IR_DMA_ENABLE|IR_RX_ENABLE, IR_CONFIG_1); - break; - default: - printk(KERN_ERR "%s unsupported speed %x\n", dev->name, speed); - ret = -EINVAL; - break; + if (aup->speed == 4000000) { + /* FIR */ + skb_copy_from_linear_data(skb, (void *)pDB->vaddr, skb->len); + ptxd->count_0 = skb->len & 0xff; + ptxd->count_1 = (skb->len >> 8) & 0xff; + } else { + /* SIR */ + len = async_wrap_skb(skb, (u8 *)pDB->vaddr, MAX_BUF_SIZE); + ptxd->count_0 = len & 0xff; + ptxd->count_1 = (len >> 8) & 0xff; + ptxd->flags |= IR_DIS_CRC; } - - aup->speed = speed; - writel(read_ir_reg(IR_ENABLE) | 0x8000, IR_ENABLE); + ptxd->flags |= AU_OWN; au_sync(); - control = read_ir_reg(IR_ENABLE); - writel(0, IR_RING_PROMPT); + irda_write(aup, IR_CONFIG_1, + irda_read(aup, IR_CONFIG_1) | IR_TX_ENABLE); + irda_write(aup, IR_RING_PROMPT, 0); au_sync(); - if (control & (1<<14)) { - printk(KERN_ERR "%s: configuration error\n", dev->name); - } - else { - if (control & (1<<11)) - printk(KERN_DEBUG "%s Valid SIR config\n", dev->name); - if (control & (1<<12)) - printk(KERN_DEBUG "%s Valid MIR config\n", dev->name); - if (control & (1<<13)) - printk(KERN_DEBUG "%s Valid FIR config\n", dev->name); - if (control & (1<<10)) - printk(KERN_DEBUG "%s TX enabled\n", dev->name); - if (control & (1<<9)) - printk(KERN_DEBUG "%s RX enabled\n", dev->name); - } + dev_kfree_skb(skb); + aup->tx_head = (aup->tx_head + 1) & (NUM_IR_DESC - 1); + dev->trans_start = jiffies; + return 0; +} - spin_unlock_irqrestore(&ir_lock, flags); - return ret; +/* + * The Tx ring has been full longer than the watchdog timeout + * value. The transmitter must be hung? + */ +static void au1k_tx_timeout(struct net_device *dev) +{ + u32 speed; + struct au1k_private *aup = netdev_priv(dev); + + printk(KERN_ERR "%s: tx timeout\n", dev->name); + speed = aup->speed; + aup->speed = 0; + au1k_irda_set_speed(dev, speed); + aup->tx_full = 0; + netif_wake_queue(dev); } -static int +static int au1k_irda_ioctl(struct net_device *dev, struct ifreq *ifreq, int cmd) { struct if_irda_req *rq = (struct if_irda_req *)ifreq; @@ -830,8 +762,214 @@ au1k_irda_ioctl(struct net_device *dev, struct ifreq *ifreq, int cmd) return ret; } +static int __devinit au1k_irda_net_init(struct net_device *dev) +{ + struct au1k_private *aup = netdev_priv(dev); + struct db_dest *pDB, *pDBfree; + int i, retval = 0, err; + dma_addr_t temp; + + err = au1k_irda_init_iobuf(&aup->rx_buff, 14384); + if (err) + goto out1; + + dev->open = au1k_irda_start; + dev->hard_start_xmit = au1k_irda_hard_xmit; + dev->stop = au1k_irda_stop; + dev->do_ioctl = au1k_irda_ioctl; + dev->tx_timeout = au1k_tx_timeout; + + irda_init_max_qos_capabilies(&aup->qos); + + /* The only value we must override it the baudrate */ + aup->qos.baud_rate.bits = IR_9600 | IR_19200 | IR_38400 | + IR_57600 | IR_115200 | IR_576000 | (IR_4000000 << 8); + + aup->qos.min_turn_time.bits = qos_mtt_bits; + irda_qos_bits_to_value(&aup->qos); + + retval = -ENOMEM; + + /* Tx ring follows rx ring + 512 bytes */ + /* we need a 1k aligned buffer */ + aup->rx_ring[0] = (struct ring_dest *) + dma_alloc(2*MAX_NUM_IR_DESC*(sizeof(struct ring_dest)), &temp); + if (!aup->rx_ring[0]) + goto out2; + + /* allocate the data buffers */ + aup->db[0].vaddr = + (void *)dma_alloc(MAX_BUF_SIZE * 2*NUM_IR_DESC, &temp); + if (!aup->db[0].vaddr) + goto out3; + + setup_hw_rings(aup, (u32)aup->rx_ring[0], (u32)aup->rx_ring[0] + 512); + + pDBfree = NULL; + pDB = aup->db; + for (i = 0; i < (2 * NUM_IR_DESC); i++) { + pDB->pnext = pDBfree; + pDBfree = pDB; + pDB->vaddr = + (u32 *)((unsigned)aup->db[0].vaddr + MAX_BUF_SIZE*i); + pDB->dma_addr = (dma_addr_t)virt_to_bus(pDB->vaddr); + pDB++; + } + aup->pDBfree = pDBfree; + + /* attach a data buffer to each descriptor */ + for (i = 0; i < NUM_IR_DESC; i++) { + pDB = GetFreeDB(aup); + if (!pDB) + goto out3; + aup->rx_ring[i]->addr_0 = (u8)(pDB->dma_addr & 0xff); + aup->rx_ring[i]->addr_1 = (u8)((pDB->dma_addr>>8) & 0xff); + aup->rx_ring[i]->addr_2 = (u8)((pDB->dma_addr>>16) & 0xff); + aup->rx_ring[i]->addr_3 = (u8)((pDB->dma_addr>>24) & 0xff); + aup->rx_db_inuse[i] = pDB; + } + for (i = 0; i < NUM_IR_DESC; i++) { + pDB = GetFreeDB(aup); + if (!pDB) + goto out3; + aup->tx_ring[i]->addr_0 = (u8)(pDB->dma_addr & 0xff); + aup->tx_ring[i]->addr_1 = (u8)((pDB->dma_addr>>8) & 0xff); + aup->tx_ring[i]->addr_2 = (u8)((pDB->dma_addr>>16) & 0xff); + aup->tx_ring[i]->addr_3 = (u8)((pDB->dma_addr>>24) & 0xff); + aup->tx_ring[i]->count_0 = 0; + aup->tx_ring[i]->count_1 = 0; + aup->tx_ring[i]->flags = 0; + aup->tx_db_inuse[i] = pDB; + } + + return 0; + +out3: + dma_free((void *)aup->rx_ring[0], + 2 * MAX_NUM_IR_DESC*(sizeof(struct ring_dest))); +out2: + kfree(aup->rx_buff.head); +out1: + printk(KERN_ERR "au1k_irda_net_init() failed. Returns %d\n", retval); + return retval; +} + +static int __devinit au1k_irda_probe(struct platform_device *pdev) +{ + struct au1k_private *aup; + struct net_device *dev; + struct resource *r; + int err; + + dev = alloc_irdadev(sizeof(struct au1k_private)); + if (!dev) + return -ENOMEM; + + aup = netdev_priv(dev); + + aup->platdata = pdev->dev.platform_data; + + err = -EINVAL; + r = platform_get_resource(pdev, IORESOURCE_IRQ, 0); + if (!r) + goto out; + + aup->irq_tx = r->start; + + r = platform_get_resource(pdev, IORESOURCE_IRQ, 1); + if (!r) + goto out; + + aup->irq_rx = r->start; + + r = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!r) + goto out; + + err = -EBUSY; + aup->ioarea = request_mem_region(r->start, r->end - r->start + 1, + pdev->name); + if (!aup->ioarea) + goto out; + + aup->iobase = ioremap_nocache(r->start, r->end - r->start + 1); + if (!aup->iobase) + goto out2; + + dev->irq = aup->irq_rx; + + err = au1k_irda_net_init(dev); + if (err) + goto out3; + err = register_netdev(dev); + if (err) + goto out4; + + platform_set_drvdata(pdev, dev); + + printk(KERN_INFO "IrDA: Registered device %s\n", dev->name); + return 0; + +out4: + dma_free((void *)aup->db[0].vaddr, + MAX_BUF_SIZE * 2 * NUM_IR_DESC); + dma_free((void *)aup->rx_ring[0], + 2 * MAX_NUM_IR_DESC*(sizeof(struct ring_dest))); + kfree(aup->rx_buff.head); +out3: + iounmap(aup->iobase); +out2: + release_resource(aup->ioarea); + kfree(aup->ioarea); +out: + free_netdev(dev); + return err; +} + +static int __devexit au1k_irda_remove(struct platform_device *pdev) +{ + struct net_device *dev = platform_get_drvdata(pdev); + struct au1k_private *aup = netdev_priv(dev); + + unregister_netdev(dev); + + dma_free((void *)aup->db[0].vaddr, + MAX_BUF_SIZE * 2*NUM_IR_DESC); + dma_free((void *)aup->rx_ring[0], + 2 * MAX_NUM_IR_DESC*(sizeof(struct ring_dest))); + kfree(aup->rx_buff.head); + + iounmap(aup->iobase); + release_resource(aup->ioarea); + kfree(aup->ioarea); + + free_netdev(dev); + + return 0; +} + +static struct platform_driver au1k_irda_driver = { + .driver = { + .name = "au1000-irda", + .owner = THIS_MODULE, + }, + .probe = au1k_irda_probe, + .remove = __devexit_p(au1k_irda_remove), +}; + +static int __init au1k_irda_load(void) +{ + printk(version); + return platform_driver_probe(&au1k_irda_driver, au1k_irda_probe); +} + +static void __exit au1k_irda_unload(void) +{ + return platform_driver_unregister(&au1k_irda_driver); +} + MODULE_AUTHOR("Pete Popov "); MODULE_DESCRIPTION("Au1000 IrDA Device Driver"); -module_init(au1k_irda_init); -module_exit(au1k_irda_exit); +module_init(au1k_irda_load); +module_exit(au1k_irda_unload); -- 1.6.0.6 From mano@roarinelk.homelinux.net Sat Jan 17 17:59:29 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 17 Jan 2009 17:59:32 +0000 (GMT) Received: from fnoeppeil36.netpark.at ([217.175.205.164]:2973 "EHLO roarinelk.homelinux.net") by ftp.linux-mips.org with ESMTP id S21366120AbZAQR73 (ORCPT ); Sat, 17 Jan 2009 17:59:29 +0000 Received: (qmail 27414 invoked from network); 17 Jan 2009 18:59:27 +0100 Received: from scarran.roarinelk.net (HELO localhost.localdomain) (192.168.0.242) by 192.168.0.1 with SMTP; 17 Jan 2009 18:59:27 +0100 From: Manuel Lauss To: irda-users@lists.sourceforge.net, Samuel Ortiz Cc: Linux-MIPS , Manuel Lauss Subject: [RFC PATCH] au1k_ir.c: convert to platform device v2 Date: Sat, 17 Jan 2009 18:59:36 +0100 Message-Id: <1232215176-21969-1-git-send-email-mano@roarinelk.homelinux.net> X-Mailer: git-send-email 1.6.0.6 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21775 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mano@roarinelk.homelinux.net Precedence: bulk X-list: linux-mips Content-Length: 45360 Lines: 1629 General driver overhaul: Compile fixes and platform_device conversion; removal of devboard-specific hacks in favor of platform data. Signed-off-by: Manuel Lauss --- Compile-tested only; I don't have the hardware. I'll send the platform-specific parts later once this patch has been accepted. V2: dropped net_device_stats from au1k_priv since netdev provides those too. arch/mips/include/asm/mach-au1x00/au1000-irda.h | 18 + arch/mips/include/asm/mach-au1x00/au1000.h | 39 - drivers/net/irda/Kconfig | 9 +- drivers/net/irda/au1000_ircc.h | 125 --- drivers/net/irda/au1k_ir.c | 1145 +++++++++++++---------- 5 files changed, 665 insertions(+), 671 deletions(-) create mode 100644 arch/mips/include/asm/mach-au1x00/au1000-irda.h delete mode 100644 drivers/net/irda/au1000_ircc.h diff --git a/arch/mips/include/asm/mach-au1x00/au1000-irda.h b/arch/mips/include/asm/mach-au1x00/au1000-irda.h new file mode 100644 index 0000000..c2926d6 --- /dev/null +++ b/arch/mips/include/asm/mach-au1x00/au1000-irda.h @@ -0,0 +1,18 @@ +/* + * au1000-irda.h -- IrDA peripheral platform information. + * + * Au1000, Au1100 + */ + +#ifndef _ALCHEMY_AU1000_IRDA_H_ +#define _ALCHEMY_AU1000_IRDA_H_ + +#define AU1000_IRDA_PHY_MODE_OFF 0 +#define AU1000_IRDA_PHY_MODE_SIR 1 +#define AU1000_IRDA_PHY_MODE_FIR 2 + +struct au1k_irda_platform_data { + void(*set_phy_mode)(int mode); +}; + +#endif diff --git a/arch/mips/include/asm/mach-au1x00/au1000.h b/arch/mips/include/asm/mach-au1x00/au1000.h index b4f30df..01c6c5a 100644 --- a/arch/mips/include/asm/mach-au1x00/au1000.h +++ b/arch/mips/include/asm/mach-au1x00/au1000.h @@ -1423,45 +1423,6 @@ enum soc_au1200_ints { #define SSI_ENABLE_CD (1 << 1) #define SSI_ENABLE_E (1 << 0) -/* IrDA Controller */ -#define IRDA_BASE 0xB0300000 -#define IR_RING_PTR_STATUS (IRDA_BASE + 0x00) -#define IR_RING_BASE_ADDR_H (IRDA_BASE + 0x04) -#define IR_RING_BASE_ADDR_L (IRDA_BASE + 0x08) -#define IR_RING_SIZE (IRDA_BASE + 0x0C) -#define IR_RING_PROMPT (IRDA_BASE + 0x10) -#define IR_RING_ADDR_CMPR (IRDA_BASE + 0x14) -#define IR_INT_CLEAR (IRDA_BASE + 0x18) -#define IR_CONFIG_1 (IRDA_BASE + 0x20) -# define IR_RX_INVERT_LED (1 << 0) -# define IR_TX_INVERT_LED (1 << 1) -# define IR_ST (1 << 2) -# define IR_SF (1 << 3) -# define IR_SIR (1 << 4) -# define IR_MIR (1 << 5) -# define IR_FIR (1 << 6) -# define IR_16CRC (1 << 7) -# define IR_TD (1 << 8) -# define IR_RX_ALL (1 << 9) -# define IR_DMA_ENABLE (1 << 10) -# define IR_RX_ENABLE (1 << 11) -# define IR_TX_ENABLE (1 << 12) -# define IR_LOOPBACK (1 << 14) -# define IR_SIR_MODE (IR_SIR | IR_DMA_ENABLE | \ - IR_RX_ALL | IR_RX_ENABLE | IR_SF | IR_16CRC) -#define IR_SIR_FLAGS (IRDA_BASE + 0x24) -#define IR_ENABLE (IRDA_BASE + 0x28) -# define IR_RX_STATUS (1 << 9) -# define IR_TX_STATUS (1 << 10) -#define IR_READ_PHY_CONFIG (IRDA_BASE + 0x2C) -#define IR_WRITE_PHY_CONFIG (IRDA_BASE + 0x30) -#define IR_MAX_PKT_LEN (IRDA_BASE + 0x34) -#define IR_RX_BYTE_CNT (IRDA_BASE + 0x38) -#define IR_CONFIG_2 (IRDA_BASE + 0x3C) -# define IR_MODE_INV (1 << 0) -# define IR_ONE_PIN (1 << 1) -#define IR_INTERFACE_CONFIG (IRDA_BASE + 0x40) - /* GPIO */ #define SYS_PINFUNC 0xB190002C # define SYS_PF_USB (1 << 15) /* 2nd USB device/host */ diff --git a/drivers/net/irda/Kconfig b/drivers/net/irda/Kconfig index e631755..f55284a 100644 --- a/drivers/net/irda/Kconfig +++ b/drivers/net/irda/Kconfig @@ -258,8 +258,13 @@ config TOSHIBA_FIR donauboe. config AU1000_FIR - tristate "Alchemy Au1000 SIR/FIR" - depends on SOC_AU1000 && IRDA + tristate "Alchemy Au1xxx SIR/FIR" + depends on MACH_ALCHEMY && IRDA + help + Say Y/M here to build support for the intergrated IrDA controllers + on the Alchemy Au1000 and Au1100 SoCs. + + Say M to build a module; it will be called au1k_ir.ko config SMC_IRCC_FIR tristate "SMSC IrCC (EXPERIMENTAL)" diff --git a/drivers/net/irda/au1000_ircc.h b/drivers/net/irda/au1000_ircc.h deleted file mode 100644 index c072c09..0000000 --- a/drivers/net/irda/au1000_ircc.h +++ /dev/null @@ -1,125 +0,0 @@ -/* - * - * BRIEF MODULE DESCRIPTION - * Au1000 IrDA driver. - * - * Copyright 2001 MontaVista Software Inc. - * Author: MontaVista Software, Inc. - * ppopov@mvista.com or source@mvista.com - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License as published by the - * Free Software Foundation; either version 2 of the License, or (at your - * option) any later version. - * - * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED - * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN - * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT - * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF - * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF - * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * You should have received a copy of the GNU General Public License along - * with this program; if not, write to the Free Software Foundation, Inc., - * 675 Mass Ave, Cambridge, MA 02139, USA. - */ - -#ifndef AU1000_IRCC_H -#define AU1000_IRCC_H - -#include - -#include -#include -#include - -#define NUM_IR_IFF 1 -#define NUM_IR_DESC 64 -#define RING_SIZE_4 0x0 -#define RING_SIZE_16 0x3 -#define RING_SIZE_64 0xF -#define MAX_NUM_IR_DESC 64 -#define MAX_BUF_SIZE 2048 - -#define BPS_115200 0 -#define BPS_57600 1 -#define BPS_38400 2 -#define BPS_19200 5 -#define BPS_9600 11 -#define BPS_2400 47 - -/* Ring descriptor flags */ -#define AU_OWN (1<<7) /* tx,rx */ - -#define IR_DIS_CRC (1<<6) /* tx */ -#define IR_BAD_CRC (1<<5) /* tx */ -#define IR_NEED_PULSE (1<<4) /* tx */ -#define IR_FORCE_UNDER (1<<3) /* tx */ -#define IR_DISABLE_TX (1<<2) /* tx */ -#define IR_HW_UNDER (1<<0) /* tx */ -#define IR_TX_ERROR (IR_DIS_CRC|IR_BAD_CRC|IR_HW_UNDER) - -#define IR_PHY_ERROR (1<<6) /* rx */ -#define IR_CRC_ERROR (1<<5) /* rx */ -#define IR_MAX_LEN (1<<4) /* rx */ -#define IR_FIFO_OVER (1<<3) /* rx */ -#define IR_SIR_ERROR (1<<2) /* rx */ -#define IR_RX_ERROR (IR_PHY_ERROR|IR_CRC_ERROR| \ - IR_MAX_LEN|IR_FIFO_OVER|IR_SIR_ERROR) - -typedef struct db_dest { - struct db_dest *pnext; - volatile u32 *vaddr; - dma_addr_t dma_addr; -} db_dest_t; - - -typedef struct ring_desc { - u8 count_0; /* 7:0 */ - u8 count_1; /* 12:8 */ - u8 reserved; - u8 flags; - u8 addr_0; /* 7:0 */ - u8 addr_1; /* 15:8 */ - u8 addr_2; /* 23:16 */ - u8 addr_3; /* 31:24 */ -} ring_dest_t; - - -/* Private data for each instance */ -struct au1k_private { - - db_dest_t *pDBfree; - db_dest_t db[2*NUM_IR_DESC]; - volatile ring_dest_t *rx_ring[NUM_IR_DESC]; - volatile ring_dest_t *tx_ring[NUM_IR_DESC]; - db_dest_t *rx_db_inuse[NUM_IR_DESC]; - db_dest_t *tx_db_inuse[NUM_IR_DESC]; - u32 rx_head; - u32 tx_head; - u32 tx_tail; - u32 tx_full; - - iobuff_t rx_buff; - - struct net_device *netdev; - - struct timeval stamp; - struct timeval now; - struct qos_info qos; - struct irlap_cb *irlap; - - u8 open; - u32 speed; - u32 newspeed; - - u32 intr_work_done; /* number of Rx and Tx pkts processed in the isr */ - struct timer_list timer; - - spinlock_t lock; /* For serializing operations */ -}; -#endif /* AU1000_IRCC_H */ diff --git a/drivers/net/irda/au1k_ir.c b/drivers/net/irda/au1k_ir.c index 9411640..be84af5 100644 --- a/drivers/net/irda/au1k_ir.c +++ b/drivers/net/irda/au1k_ir.c @@ -18,96 +18,196 @@ * with this program; if not, write to the Free Software Foundation, Inc., * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. */ -#include -#include + #include -#include +#include #include -#include -#include #include -#include -#include - -#include -#include -#include -#if defined(CONFIG_MIPS_PB1000) || defined(CONFIG_MIPS_PB1100) -#include -#elif defined(CONFIG_MIPS_DB1000) || defined(CONFIG_MIPS_DB1100) -#include -#else -#error au1k_ir: unsupported board -#endif +#include +#include +#include +#include +#include #include #include #include #include -#include "au1000_ircc.h" -static int au1k_irda_net_init(struct net_device *); -static int au1k_irda_start(struct net_device *); -static int au1k_irda_stop(struct net_device *dev); -static int au1k_irda_hard_xmit(struct sk_buff *, struct net_device *); -static int au1k_irda_rx(struct net_device *); -static void au1k_irda_interrupt(int, void *); -static void au1k_tx_timeout(struct net_device *); -static int au1k_irda_ioctl(struct net_device *, struct ifreq *, int); -static int au1k_irda_set_speed(struct net_device *dev, int speed); +#include +#include + +/* registers */ +#define IR_RING_PTR_STATUS 0x00 +#define IR_RING_BASE_ADDR_H 0x04 +#define IR_RING_BASE_ADDR_L 0x08 +#define IR_RING_SIZE 0x0C +#define IR_RING_PROMPT 0x10 +#define IR_RING_ADDR_CMPR 0x14 +#define IR_INT_CLEAR 0x18 +#define IR_CONFIG_1 0x20 +#define IR_SIR_FLAGS 0x24 +#define IR_ENABLE 0x28 +#define IR_READ_PHY_CONFIG 0x2C +#define IR_WRITE_PHY_CONFIG 0x30 +#define IR_MAX_PKT_LEN 0x34 +#define IR_RX_BYTE_CNT 0x38 +#define IR_CONFIG_2 0x3C +#define IR_INTERFACE_CONFIG 0x40 + +/* Config1 */ +#define IR_RX_INVERT_LED (1 << 0) +#define IR_TX_INVERT_LED (1 << 1) +#define IR_ST (1 << 2) +#define IR_SF (1 << 3) +#define IR_SIR (1 << 4) +#define IR_MIR (1 << 5) +#define IR_FIR (1 << 6) +#define IR_16CRC (1 << 7) +#define IR_TD (1 << 8) +#define IR_RX_ALL (1 << 9) +#define IR_DMA_ENABLE (1 << 10) +#define IR_RX_ENABLE (1 << 11) +#define IR_TX_ENABLE (1 << 12) +#define IR_LOOPBACK (1 << 14) +#define IR_SIR_MODE (IR_SIR | IR_DMA_ENABLE | \ + IR_RX_ALL | IR_RX_ENABLE | IR_SF | \ + IR_16CRC) + +/* ir_enable */ +#define IR_RX_STATUS (1 << 9) +#define IR_TX_STATUS (1 << 10) +/* Config2 */ +#define IR_MODE_INV (1 << 0) +#define IR_ONE_PIN (1 << 1) + + +#define NUM_IR_DESC 64 +#define RING_SIZE_4 0x0 +#define RING_SIZE_16 0x3 +#define RING_SIZE_64 0xF +#define MAX_NUM_IR_DESC 64 +#define MAX_BUF_SIZE 2048 + +/* Ring descriptor flags */ +#define AU_OWN (1<<7) /* tx,rx */ + +#define IR_DIS_CRC (1<<6) /* tx */ +#define IR_BAD_CRC (1<<5) /* tx */ +#define IR_NEED_PULSE (1<<4) /* tx */ +#define IR_FORCE_UNDER (1<<3) /* tx */ +#define IR_DISABLE_TX (1<<2) /* tx */ +#define IR_HW_UNDER (1<<0) /* tx */ +#define IR_TX_ERROR (IR_DIS_CRC | IR_BAD_CRC | IR_HW_UNDER) + +#define IR_PHY_ERROR (1<<6) /* rx */ +#define IR_CRC_ERROR (1<<5) /* rx */ +#define IR_MAX_LEN (1<<4) /* rx */ +#define IR_FIFO_OVER (1<<3) /* rx */ +#define IR_SIR_ERROR (1<<2) /* rx */ +#define IR_RX_ERROR (IR_PHY_ERROR | IR_CRC_ERROR | \ + IR_MAX_LEN | IR_FIFO_OVER | IR_SIR_ERROR) + +struct db_dest { + struct db_dest *pnext; + volatile u32 *vaddr; + dma_addr_t dma_addr; +}; + +struct ring_dest { + u8 count_0; /* 7:0 */ + u8 count_1; /* 12:8 */ + u8 reserved; + u8 flags; + u8 addr_0; /* 7:0 */ + u8 addr_1; /* 15:8 */ + u8 addr_2; /* 23:16 */ + u8 addr_3; /* 31:24 */ +}; + +/* Private data for each instance */ +struct au1k_private { + void __iomem *iobase; + int irq_rx, irq_tx; + + struct db_dest *pDBfree; + struct db_dest db[2*NUM_IR_DESC]; + volatile struct ring_dest *rx_ring[NUM_IR_DESC]; + volatile struct ring_dest *tx_ring[NUM_IR_DESC]; + struct db_dest *rx_db_inuse[NUM_IR_DESC]; + struct db_dest *tx_db_inuse[NUM_IR_DESC]; + u32 rx_head; + u32 tx_head; + u32 tx_tail; + u32 tx_full; + + iobuff_t rx_buff; + + struct net_device *netdev; + struct timeval stamp; + struct timeval now; + struct qos_info qos; + struct irlap_cb *irlap; + + u8 open; + u32 speed; + u32 newspeed; -static void *dma_alloc(size_t, dma_addr_t *); -static void dma_free(void *, size_t); + struct timer_list timer; + + spinlock_t lock; /* For serializing operations */ + struct resource *ioarea; + struct au1k_irda_platform_data *platdata; +}; static int qos_mtt_bits = 0x07; /* 1 ms or more */ -static struct net_device *ir_devs[NUM_IR_IFF]; static char version[] __devinitdata = "au1k_ircc:1.2 ppopov@mvista.com\n"; #define RUN_AT(x) (jiffies + (x)) -#if defined(CONFIG_MIPS_DB1000) || defined(CONFIG_MIPS_DB1100) -static BCSR * const bcsr = (BCSR *)0xAE000000; -#endif static DEFINE_SPINLOCK(ir_lock); +static void au1k_irda_plat_set_phy_mode(struct au1k_private *p, int mode) +{ + if (p->platdata && p->platdata->set_phy_mode) + p->platdata->set_phy_mode(mode); +} + +static inline unsigned long irda_read(struct au1k_private *p, + unsigned long ofs) +{ /* * IrDA peripheral bug. You have to read the register * twice to get the right value. */ -u32 read_ir_reg(u32 addr) -{ - readl(addr); - return readl(addr); + (void)au_readl((unsigned long)(p->iobase) + ofs); + return au_readl((unsigned long)(p->iobase) + ofs); } +static inline void irda_write(struct au1k_private *p, unsigned long ofs, + unsigned long val) +{ + au_writel(val, (unsigned long)(p->iobase) + ofs); +} /* * Buffer allocation/deallocation routines. The buffer descriptor returned - * has the virtual and dma address of a buffer suitable for + * has the virtual and dma address of a buffer suitable for * both, receive and transmit operations. */ -static db_dest_t *GetFreeDB(struct au1k_private *aup) +static struct db_dest *GetFreeDB(struct au1k_private *aup) { - db_dest_t *pDB; - pDB = aup->pDBfree; + struct db_dest *db; + db = aup->pDBfree; - if (pDB) { - aup->pDBfree = pDB->pnext; - } - return pDB; -} + if (db) + aup->pDBfree = db->pnext; -static void ReleaseDB(struct au1k_private *aup, db_dest_t *pDB) -{ - db_dest_t *pDBfree = aup->pDBfree; - if (pDBfree) - pDBfree->pnext = pDB; - aup->pDBfree = pDB; + return db; } - /* DMA memory allocation, derived from pci_alloc_consistent. However, the Au1000 data cache is coherent (when programmed @@ -136,56 +236,20 @@ static void dma_free(void *vaddr, size_t size) } -static void +static void setup_hw_rings(struct au1k_private *aup, u32 rx_base, u32 tx_base) { int i; for (i=0; irx_ring[i] = (volatile ring_dest_t *) - (rx_base + sizeof(ring_dest_t)*i); + aup->rx_ring[i] = (volatile struct ring_dest *) + (rx_base + sizeof(struct ring_dest)*i); } for (i=0; itx_ring[i] = (volatile ring_dest_t *) - (tx_base + sizeof(ring_dest_t)*i); + aup->tx_ring[i] = (volatile struct ring_dest *) + (tx_base + sizeof(struct ring_dest)*i); } } -static int au1k_irda_init(void) -{ - static unsigned version_printed = 0; - struct au1k_private *aup; - struct net_device *dev; - int err; - - if (version_printed++ == 0) printk(version); - - dev = alloc_irdadev(sizeof(struct au1k_private)); - if (!dev) - return -ENOMEM; - - dev->irq = AU1000_IRDA_RX_INT; /* TX has its own interrupt */ - err = au1k_irda_net_init(dev); - if (err) - goto out; - err = register_netdev(dev); - if (err) - goto out1; - ir_devs[0] = dev; - printk(KERN_INFO "IrDA: Registered device %s\n", dev->name); - return 0; - -out1: - aup = netdev_priv(dev); - dma_free((void *)aup->db[0].vaddr, - MAX_BUF_SIZE * 2*NUM_IR_DESC); - dma_free((void *)aup->rx_ring[0], - 2 * MAX_NUM_IR_DESC*(sizeof(ring_dest_t))); - kfree(aup->rx_buff.head); -out: - free_netdev(dev); - return err; -} - static int au1k_irda_init_iobuf(iobuff_t *io, int size) { io->head = kmalloc(size, GFP_KERNEL); @@ -198,104 +262,123 @@ static int au1k_irda_init_iobuf(iobuff_t *io, int size) return io->head ? 0 : -ENOMEM; } -static int au1k_irda_net_init(struct net_device *dev) +/* + * Set the IrDA communications speed. + */ +static int au1k_irda_set_speed(struct net_device *dev, int speed) { + unsigned long flags; struct au1k_private *aup = netdev_priv(dev); - int i, retval = 0, err; - db_dest_t *pDB, *pDBfree; - dma_addr_t temp; + u32 control; + int ret = 0, timeout = 10, i; + volatile struct ring_dest *ptxd; - err = au1k_irda_init_iobuf(&aup->rx_buff, 14384); - if (err) - goto out1; + if (speed == aup->speed) + return ret; - dev->open = au1k_irda_start; - dev->hard_start_xmit = au1k_irda_hard_xmit; - dev->stop = au1k_irda_stop; - dev->do_ioctl = au1k_irda_ioctl; - dev->tx_timeout = au1k_tx_timeout; + spin_lock_irqsave(&ir_lock, flags); - irda_init_max_qos_capabilies(&aup->qos); + /* disable PHY first */ + irda_write(aup, IR_ENABLE, irda_read(aup, IR_ENABLE) & ~0x8000); - /* The only value we must override it the baudrate */ - aup->qos.baud_rate.bits = IR_9600|IR_19200|IR_38400|IR_57600| - IR_115200|IR_576000 |(IR_4000000 << 8); - - aup->qos.min_turn_time.bits = qos_mtt_bits; - irda_qos_bits_to_value(&aup->qos); + /* disable RX/TX */ + irda_write(aup, IR_CONFIG_1, + irda_read(aup, IR_CONFIG_1) & ~(IR_RX_ENABLE | IR_TX_ENABLE)); + au_sync_delay(1); + while (irda_read(aup, IR_ENABLE) & (IR_RX_STATUS | IR_TX_STATUS)) { + mdelay(1); + if (!timeout--) { + printk(KERN_ERR "%s: rx/tx disable timeout\n", + dev->name); + break; + } + } - retval = -ENOMEM; + /* disable DMA */ + irda_write(aup, IR_CONFIG_1, + irda_read(aup, IR_CONFIG_1) & ~IR_DMA_ENABLE); + au_sync_delay(1); - /* Tx ring follows rx ring + 512 bytes */ - /* we need a 1k aligned buffer */ - aup->rx_ring[0] = (ring_dest_t *) - dma_alloc(2*MAX_NUM_IR_DESC*(sizeof(ring_dest_t)), &temp); - if (!aup->rx_ring[0]) - goto out2; + /* After we disable tx/rx. the index pointers go back to zero. */ + aup->tx_head = aup->tx_tail = aup->rx_head = 0; + for (i = 0; i < NUM_IR_DESC; i++) { + ptxd = aup->tx_ring[i]; + ptxd->flags = 0; + ptxd->count_0 = 0; + ptxd->count_1 = 0; + } - /* allocate the data buffers */ - aup->db[0].vaddr = - (void *)dma_alloc(MAX_BUF_SIZE * 2*NUM_IR_DESC, &temp); - if (!aup->db[0].vaddr) - goto out3; + for (i = 0; i < NUM_IR_DESC; i++) { + ptxd = aup->rx_ring[i]; + ptxd->count_0 = 0; + ptxd->count_1 = 0; + ptxd->flags = AU_OWN; + } - setup_hw_rings(aup, (u32)aup->rx_ring[0], (u32)aup->rx_ring[0] + 512); + if (speed == 4000000) + au1k_irda_plat_set_phy_mode(aup, AU1000_IRDA_PHY_MODE_FIR); + else + au1k_irda_plat_set_phy_mode(aup, AU1000_IRDA_PHY_MODE_SIR); - pDBfree = NULL; - pDB = aup->db; - for (i=0; i<(2*NUM_IR_DESC); i++) { - pDB->pnext = pDBfree; - pDBfree = pDB; - pDB->vaddr = - (u32 *)((unsigned)aup->db[0].vaddr + MAX_BUF_SIZE*i); - pDB->dma_addr = (dma_addr_t)virt_to_bus(pDB->vaddr); - pDB++; + switch (speed) { + case 9600: + irda_write(aup, IR_WRITE_PHY_CONFIG, 11<<10 | 12<<5); + irda_write(aup, IR_CONFIG_1, IR_SIR_MODE); + break; + case 19200: + irda_write(aup, IR_WRITE_PHY_CONFIG, 5<<10 | 12<<5); + irda_write(aup, IR_CONFIG_1, IR_SIR_MODE); + break; + case 38400: + irda_write(aup, IR_WRITE_PHY_CONFIG, 2<<10 | 12<<5); + irda_write(aup, IR_CONFIG_1, IR_SIR_MODE); + break; + case 57600: + irda_write(aup, IR_WRITE_PHY_CONFIG, 1<<10 | 12<<5); + irda_write(aup, IR_CONFIG_1, IR_SIR_MODE); + break; + case 115200: + irda_write(aup, IR_WRITE_PHY_CONFIG, 12<<5); + irda_write(aup, IR_CONFIG_1, IR_SIR_MODE); + break; + case 4000000: + irda_write(aup, IR_WRITE_PHY_CONFIG, 0xf); + irda_write(aup, IR_CONFIG_1, IR_FIR | IR_DMA_ENABLE | + IR_RX_ENABLE); + break; + default: + printk(KERN_ERR "%s unsupported speed %x\n", dev->name, speed); + ret = -EINVAL; + break; } - aup->pDBfree = pDBfree; - /* attach a data buffer to each descriptor */ - for (i=0; irx_ring[i]->addr_0 = (u8)(pDB->dma_addr & 0xff); - aup->rx_ring[i]->addr_1 = (u8)((pDB->dma_addr>>8) & 0xff); - aup->rx_ring[i]->addr_2 = (u8)((pDB->dma_addr>>16) & 0xff); - aup->rx_ring[i]->addr_3 = (u8)((pDB->dma_addr>>24) & 0xff); - aup->rx_db_inuse[i] = pDB; - } - for (i=0; itx_ring[i]->addr_0 = (u8)(pDB->dma_addr & 0xff); - aup->tx_ring[i]->addr_1 = (u8)((pDB->dma_addr>>8) & 0xff); - aup->tx_ring[i]->addr_2 = (u8)((pDB->dma_addr>>16) & 0xff); - aup->tx_ring[i]->addr_3 = (u8)((pDB->dma_addr>>24) & 0xff); - aup->tx_ring[i]->count_0 = 0; - aup->tx_ring[i]->count_1 = 0; - aup->tx_ring[i]->flags = 0; - aup->tx_db_inuse[i] = pDB; - } + aup->speed = speed; + irda_write(aup, IR_ENABLE, irda_read(aup, IR_ENABLE) | 0x8000); + au_sync(); -#if defined(CONFIG_MIPS_DB1000) || defined(CONFIG_MIPS_DB1100) - /* power on */ - bcsr->resets &= ~BCSR_RESETS_IRDA_MODE_MASK; - bcsr->resets |= BCSR_RESETS_IRDA_MODE_FULL; + control = irda_read(aup, IR_ENABLE); + irda_write(aup, IR_RING_PROMPT, 0); au_sync(); -#endif - return 0; + if (control & (1<<14)) { + printk(KERN_ERR "%s: configuration error\n", dev->name); + } else { + if (control & (1<<11)) + printk(KERN_DEBUG "%s Valid SIR config\n", dev->name); + if (control & (1<<12)) + printk(KERN_DEBUG "%s Valid MIR config\n", dev->name); + if (control & (1<<13)) + printk(KERN_DEBUG "%s Valid FIR config\n", dev->name); + if (control & (1<<10)) + printk(KERN_DEBUG "%s TX enabled\n", dev->name); + if (control & (1<<9)) + printk(KERN_DEBUG "%s RX enabled\n", dev->name); + } -out3: - dma_free((void *)aup->rx_ring[0], - 2 * MAX_NUM_IR_DESC*(sizeof(ring_dest_t))); -out2: - kfree(aup->rx_buff.head); -out1: - printk(KERN_ERR "au1k_init_module failed. Returns %d\n", retval); - return retval; + spin_unlock_irqrestore(&ir_lock, flags); + return ret; } - static int au1k_init(struct net_device *dev) { struct au1k_private *aup = netdev_priv(dev); @@ -305,7 +388,7 @@ static int au1k_init(struct net_device *dev) /* bring the device out of reset */ control = 0xe; /* coherent, clock enable, one half system clock */ - + #ifndef CONFIG_CPU_LITTLE_ENDIAN control |= 1; #endif @@ -317,109 +400,49 @@ static int au1k_init(struct net_device *dev) aup->rx_ring[i]->flags = AU_OWN; } - writel(control, IR_INTERFACE_CONFIG); + irda_write(aup, IR_INTERFACE_CONFIG, control); au_sync_delay(10); - writel(read_ir_reg(IR_ENABLE) & ~0x8000, IR_ENABLE); /* disable PHY */ + /* disable PHY */ + irda_write(aup, IR_ENABLE, irda_read(aup, IR_ENABLE) & ~0x8000); au_sync_delay(1); - writel(MAX_BUF_SIZE, IR_MAX_PKT_LEN); + irda_write(aup, IR_MAX_PKT_LEN, MAX_BUF_SIZE); ring_address = (u32)virt_to_phys((void *)aup->rx_ring[0]); - writel(ring_address >> 26, IR_RING_BASE_ADDR_H); - writel((ring_address >> 10) & 0xffff, IR_RING_BASE_ADDR_L); + irda_write(aup, IR_RING_BASE_ADDR_H, ring_address >> 26); + irda_write(aup, IR_RING_BASE_ADDR_L, (ring_address >> 10) & 0xffff); - writel(RING_SIZE_64<<8 | RING_SIZE_64<<12, IR_RING_SIZE); + irda_write(aup, IR_RING_SIZE, RING_SIZE_64<<8 | RING_SIZE_64<<12); - writel(1<<2 | IR_ONE_PIN, IR_CONFIG_2); /* 48MHz */ - writel(0, IR_RING_ADDR_CMPR); + irda_write(aup, IR_CONFIG_2, 1<<2 | IR_ONE_PIN); /* 48MHz */ + irda_write(aup, IR_RING_ADDR_CMPR, 0); au1k_irda_set_speed(dev, 9600); return 0; } -static int au1k_irda_start(struct net_device *dev) -{ - int retval; - char hwname[32]; - struct au1k_private *aup = netdev_priv(dev); - - if ((retval = au1k_init(dev))) { - printk(KERN_ERR "%s: error in au1k_init\n", dev->name); - return retval; - } - - if ((retval = request_irq(AU1000_IRDA_TX_INT, &au1k_irda_interrupt, - 0, dev->name, dev))) { - printk(KERN_ERR "%s: unable to get IRQ %d\n", - dev->name, dev->irq); - return retval; - } - if ((retval = request_irq(AU1000_IRDA_RX_INT, &au1k_irda_interrupt, - 0, dev->name, dev))) { - free_irq(AU1000_IRDA_TX_INT, dev); - printk(KERN_ERR "%s: unable to get IRQ %d\n", - dev->name, dev->irq); - return retval; - } - - /* Give self a hardware name */ - sprintf(hwname, "Au1000 SIR/FIR"); - aup->irlap = irlap_open(dev, &aup->qos, hwname); - netif_start_queue(dev); - - writel(read_ir_reg(IR_CONFIG_2) | 1<<8, IR_CONFIG_2); /* int enable */ - - aup->timer.expires = RUN_AT((3*HZ)); - aup->timer.data = (unsigned long)dev; - return 0; -} - -static int au1k_irda_stop(struct net_device *dev) -{ - struct au1k_private *aup = netdev_priv(dev); - - /* disable interrupts */ - writel(read_ir_reg(IR_CONFIG_2) & ~(1<<8), IR_CONFIG_2); - writel(0, IR_CONFIG_1); - writel(0, IR_INTERFACE_CONFIG); /* disable clock */ - au_sync(); - - if (aup->irlap) { - irlap_close(aup->irlap); - aup->irlap = NULL; - } - - netif_stop_queue(dev); - del_timer(&aup->timer); - - /* disable the interrupt */ - free_irq(AU1000_IRDA_TX_INT, dev); - free_irq(AU1000_IRDA_RX_INT, dev); - return 0; -} - -static void __exit au1k_irda_exit(void) +static void update_rx_stats(struct net_device *dev, u32 status, u32 count) { - struct net_device *dev = ir_devs[0]; - struct au1k_private *aup = netdev_priv(dev); + struct net_device_stats *ps = &dev->stats; - unregister_netdev(dev); + ps->rx_packets++; - dma_free((void *)aup->db[0].vaddr, - MAX_BUF_SIZE * 2*NUM_IR_DESC); - dma_free((void *)aup->rx_ring[0], - 2 * MAX_NUM_IR_DESC*(sizeof(ring_dest_t))); - kfree(aup->rx_buff.head); - free_netdev(dev); + if (status & IR_RX_ERROR) { + ps->rx_errors++; + if (status & (IR_PHY_ERROR | IR_FIFO_OVER)) + ps->rx_missed_errors++; + if (status & IR_MAX_LEN) + ps->rx_length_errors++; + if (status & IR_CRC_ERROR) + ps->rx_crc_errors++; + } else + ps->rx_bytes += count; } - -static inline void -update_tx_stats(struct net_device *dev, u32 status, u32 pkt_len) +static void update_tx_stats(struct net_device *dev, u32 status, u32 pkt_len) { - struct au1k_private *aup = netdev_priv(dev); - struct net_device_stats *ps = &aup->stats; + struct net_device_stats *ps = &dev->stats; ps->tx_packets++; ps->tx_bytes += pkt_len; @@ -430,15 +453,14 @@ update_tx_stats(struct net_device *dev, u32 status, u32 pkt_len) } } - static void au1k_tx_ack(struct net_device *dev) { struct au1k_private *aup = netdev_priv(dev); - volatile ring_dest_t *ptxd; + volatile struct ring_dest *ptxd; ptxd = aup->tx_ring[aup->tx_tail]; while (!(ptxd->flags & AU_OWN) && (aup->tx_tail != aup->tx_head)) { - update_tx_stats(dev, ptxd->flags, + update_tx_stats(dev, ptxd->flags, ptxd->count_1<<8 | ptxd->count_0); ptxd->count_0 = 0; ptxd->count_1 = 0; @@ -457,131 +479,28 @@ static void au1k_tx_ack(struct net_device *dev) if (aup->newspeed) { au1k_irda_set_speed(dev, aup->newspeed); aup->newspeed = 0; - } - else { - writel(read_ir_reg(IR_CONFIG_1) & ~IR_TX_ENABLE, - IR_CONFIG_1); + } else { + irda_write(aup, IR_CONFIG_1, + irda_read(aup, IR_CONFIG_1) & ~IR_TX_ENABLE); au_sync(); - writel(read_ir_reg(IR_CONFIG_1) | IR_RX_ENABLE, - IR_CONFIG_1); - writel(0, IR_RING_PROMPT); + irda_write(aup, IR_CONFIG_1, + irda_read(aup, IR_CONFIG_1) | IR_RX_ENABLE); + irda_write(aup, IR_RING_PROMPT, 0); au_sync(); } } } - -/* - * Au1000 transmit routine. - */ -static int au1k_irda_hard_xmit(struct sk_buff *skb, struct net_device *dev) -{ - struct au1k_private *aup = netdev_priv(dev); - int speed = irda_get_next_speed(skb); - volatile ring_dest_t *ptxd; - u32 len; - - u32 flags; - db_dest_t *pDB; - - if (speed != aup->speed && speed != -1) { - aup->newspeed = speed; - } - - if ((skb->len == 0) && (aup->newspeed)) { - if (aup->tx_tail == aup->tx_head) { - au1k_irda_set_speed(dev, speed); - aup->newspeed = 0; - } - dev_kfree_skb(skb); - return 0; - } - - ptxd = aup->tx_ring[aup->tx_head]; - flags = ptxd->flags; - - if (flags & AU_OWN) { - printk(KERN_DEBUG "%s: tx_full\n", dev->name); - netif_stop_queue(dev); - aup->tx_full = 1; - return 1; - } - else if (((aup->tx_head + 1) & (NUM_IR_DESC - 1)) == aup->tx_tail) { - printk(KERN_DEBUG "%s: tx_full\n", dev->name); - netif_stop_queue(dev); - aup->tx_full = 1; - return 1; - } - - pDB = aup->tx_db_inuse[aup->tx_head]; - -#if 0 - if (read_ir_reg(IR_RX_BYTE_CNT) != 0) { - printk("tx warning: rx byte cnt %x\n", - read_ir_reg(IR_RX_BYTE_CNT)); - } -#endif - - if (aup->speed == 4000000) { - /* FIR */ - skb_copy_from_linear_data(skb, pDB->vaddr, skb->len); - ptxd->count_0 = skb->len & 0xff; - ptxd->count_1 = (skb->len >> 8) & 0xff; - - } - else { - /* SIR */ - len = async_wrap_skb(skb, (u8 *)pDB->vaddr, MAX_BUF_SIZE); - ptxd->count_0 = len & 0xff; - ptxd->count_1 = (len >> 8) & 0xff; - ptxd->flags |= IR_DIS_CRC; - au_writel(au_readl(0xae00000c) & ~(1<<13), 0xae00000c); - } - ptxd->flags |= AU_OWN; - au_sync(); - - writel(read_ir_reg(IR_CONFIG_1) | IR_TX_ENABLE, IR_CONFIG_1); - writel(0, IR_RING_PROMPT); - au_sync(); - - dev_kfree_skb(skb); - aup->tx_head = (aup->tx_head + 1) & (NUM_IR_DESC - 1); - dev->trans_start = jiffies; - return 0; -} - - -static inline void -update_rx_stats(struct net_device *dev, u32 status, u32 count) -{ - struct au1k_private *aup = netdev_priv(dev); - struct net_device_stats *ps = &aup->stats; - - ps->rx_packets++; - - if (status & IR_RX_ERROR) { - ps->rx_errors++; - if (status & (IR_PHY_ERROR|IR_FIFO_OVER)) - ps->rx_missed_errors++; - if (status & IR_MAX_LEN) - ps->rx_length_errors++; - if (status & IR_CRC_ERROR) - ps->rx_crc_errors++; - } - else - ps->rx_bytes += count; -} - /* * Au1000 receive routine. */ static int au1k_irda_rx(struct net_device *dev) { struct au1k_private *aup = netdev_priv(dev); + volatile struct ring_dest *prxd; struct sk_buff *skb; - volatile ring_dest_t *prxd; + struct db_dest *pDB; u32 flags, count; - db_dest_t *pDB; prxd = aup->rx_ring[aup->rx_head]; flags = prxd->flags; @@ -589,12 +508,12 @@ static int au1k_irda_rx(struct net_device *dev) while (!(flags & AU_OWN)) { pDB = aup->rx_db_inuse[aup->rx_head]; count = prxd->count_1<<8 | prxd->count_0; - if (!(flags & IR_RX_ERROR)) { + if (!(flags & IR_RX_ERROR)) { /* good frame */ update_rx_stats(dev, flags, count); - skb=alloc_skb(count+1,GFP_ATOMIC); + skb = alloc_skb(count + 1, GFP_ATOMIC); if (skb == NULL) { - aup->netdev->stats.rx_dropped++; + dev->stats.rx_dropped++; continue; } skb_reserve(skb, 1); @@ -602,7 +521,8 @@ static int au1k_irda_rx(struct net_device *dev) skb_put(skb, count); else skb_put(skb, count-2); - skb_copy_to_linear_data(skb, pDB->vaddr, count - 2); + skb_copy_to_linear_data(skb, (void *)pDB->vaddr, + count - 2); skb->dev = dev; skb_reset_mac_header(skb); skb->protocol = htons(ETH_P_IRDA); @@ -612,7 +532,7 @@ static int au1k_irda_rx(struct net_device *dev) } prxd->flags |= AU_OWN; aup->rx_head = (aup->rx_head + 1) & (NUM_IR_DESC - 1); - writel(0, IR_RING_PROMPT); + irda_write(aup, IR_RING_PROMPT, 0); au_sync(); /* next descriptor */ @@ -623,12 +543,12 @@ static int au1k_irda_rx(struct net_device *dev) return 0; } - static irqreturn_t au1k_irda_interrupt(int dummy, void *dev_id) { struct net_device *dev = dev_id; + struct au1k_private *aup = netdev_priv(dev); - writel(0, IR_INT_CLEAR); /* ack irda interrupts */ + irda_write(aup, IR_INT_CLEAR, 0); /* ack irda interrupts */ au1k_irda_rx(dev); au1k_tx_ack(dev); @@ -636,159 +556,168 @@ static irqreturn_t au1k_irda_interrupt(int dummy, void *dev_id) return IRQ_HANDLED; } - -/* - * The Tx ring has been full longer than the watchdog timeout - * value. The transmitter must be hung? - */ -static void au1k_tx_timeout(struct net_device *dev) +static int au1k_irda_start(struct net_device *dev) { - u32 speed; + int retval; + char hwname[32]; struct au1k_private *aup = netdev_priv(dev); - printk(KERN_ERR "%s: tx timeout\n", dev->name); - speed = aup->speed; - aup->speed = 0; - au1k_irda_set_speed(dev, speed); - aup->tx_full = 0; - netif_wake_queue(dev); + retval = au1k_init(dev); + if (retval) { + printk(KERN_ERR "%s: error in au1k_init\n", dev->name); + return retval; + } + + retval = request_irq(aup->irq_tx, &au1k_irda_interrupt, 0, + dev->name, dev); + if (retval) { + printk(KERN_ERR "%s: unable to get IRQ %d\n", + dev->name, dev->irq); + return retval; + } + retval = request_irq(aup->irq_rx, &au1k_irda_interrupt, 0, + dev->name, dev); + if (retval) { + free_irq(aup->irq_tx, dev); + printk(KERN_ERR "%s: unable to get IRQ %d\n", + dev->name, dev->irq); + return retval; + } + + /* Give self a hardware name */ + sprintf(hwname, "Au1000 SIR/FIR"); + aup->irlap = irlap_open(dev, &aup->qos, hwname); + netif_start_queue(dev); + + /* int enable */ + irda_write(aup, IR_CONFIG_2, irda_read(aup, IR_CONFIG_2) | 1<<8); + + /* power up */ + au1k_irda_plat_set_phy_mode(aup, AU1000_IRDA_PHY_MODE_SIR); + + aup->timer.expires = RUN_AT((3*HZ)); + aup->timer.data = (unsigned long)dev; + return 0; } +static int au1k_irda_stop(struct net_device *dev) +{ + struct au1k_private *aup = netdev_priv(dev); + + au1k_irda_plat_set_phy_mode(aup, AU1000_IRDA_PHY_MODE_OFF); + + /* disable interrupts */ + irda_write(aup, IR_CONFIG_2, irda_read(aup, IR_CONFIG_2) & ~(1<<8)); + irda_write(aup, IR_CONFIG_1, 0); + irda_write(aup, IR_INTERFACE_CONFIG, 0); /* disable clock */ + au_sync(); + + if (aup->irlap) { + irlap_close(aup->irlap); + aup->irlap = NULL; + } + + netif_stop_queue(dev); + del_timer(&aup->timer); + + /* disable the interrupt */ + free_irq(aup->irq_tx, dev); + free_irq(aup->irq_rx, dev); + + return 0; +} /* - * Set the IrDA communications speed. + * Au1000 transmit routine. */ -static int -au1k_irda_set_speed(struct net_device *dev, int speed) +static int au1k_irda_hard_xmit(struct sk_buff *skb, struct net_device *dev) { - unsigned long flags; struct au1k_private *aup = netdev_priv(dev); - u32 control; - int ret = 0, timeout = 10, i; - volatile ring_dest_t *ptxd; -#if defined(CONFIG_MIPS_DB1000) || defined(CONFIG_MIPS_DB1100) - unsigned long irda_resets; -#endif - - if (speed == aup->speed) - return ret; - - spin_lock_irqsave(&ir_lock, flags); + int speed = irda_get_next_speed(skb); + volatile struct ring_dest *ptxd; + struct db_dest *pDB; + u32 len, flags; - /* disable PHY first */ - writel(read_ir_reg(IR_ENABLE) & ~0x8000, IR_ENABLE); + if (speed != aup->speed && speed != -1) + aup->newspeed = speed; - /* disable RX/TX */ - writel(read_ir_reg(IR_CONFIG_1) & ~(IR_RX_ENABLE|IR_TX_ENABLE), - IR_CONFIG_1); - au_sync_delay(1); - while (read_ir_reg(IR_ENABLE) & (IR_RX_STATUS | IR_TX_STATUS)) { - mdelay(1); - if (!timeout--) { - printk(KERN_ERR "%s: rx/tx disable timeout\n", - dev->name); - break; + if ((skb->len == 0) && (aup->newspeed)) { + if (aup->tx_tail == aup->tx_head) { + au1k_irda_set_speed(dev, speed); + aup->newspeed = 0; } + dev_kfree_skb(skb); + return 0; } - /* disable DMA */ - writel(read_ir_reg(IR_CONFIG_1) & ~IR_DMA_ENABLE, IR_CONFIG_1); - au_sync_delay(1); + ptxd = aup->tx_ring[aup->tx_head]; + flags = ptxd->flags; - /* - * After we disable tx/rx. the index pointers - * go back to zero. - */ - aup->tx_head = aup->tx_tail = aup->rx_head = 0; - for (i=0; itx_ring[i]; - ptxd->flags = 0; - ptxd->count_0 = 0; - ptxd->count_1 = 0; + if (flags & AU_OWN) { + printk(KERN_DEBUG "%s: tx_full\n", dev->name); + netif_stop_queue(dev); + aup->tx_full = 1; + return 1; + } else if (((aup->tx_head + 1) & (NUM_IR_DESC - 1)) == aup->tx_tail) { + printk(KERN_DEBUG "%s: tx_full\n", dev->name); + netif_stop_queue(dev); + aup->tx_full = 1; + return 1; } - for (i=0; irx_ring[i]; - ptxd->count_0 = 0; - ptxd->count_1 = 0; - ptxd->flags = AU_OWN; - } + pDB = aup->tx_db_inuse[aup->tx_head]; - if (speed == 4000000) { -#if defined(CONFIG_MIPS_DB1000) || defined(CONFIG_MIPS_DB1100) - bcsr->resets |= BCSR_RESETS_FIR_SEL; -#else /* Pb1000 and Pb1100 */ - writel(1<<13, CPLD_AUX1); -#endif +#if 0 + if (irda_read(aup, IR_RX_BYTE_CNT) != 0) { + printk(KERN_DEBUG "tx warning: rx byte cnt %x\n", + irda_read(aup, IR_RX_BYTE_CNT)); } - else { -#if defined(CONFIG_MIPS_DB1000) || defined(CONFIG_MIPS_DB1100) - bcsr->resets &= ~BCSR_RESETS_FIR_SEL; -#else /* Pb1000 and Pb1100 */ - writel(readl(CPLD_AUX1) & ~(1<<13), CPLD_AUX1); #endif - } - switch (speed) { - case 9600: - writel(11<<10 | 12<<5, IR_WRITE_PHY_CONFIG); - writel(IR_SIR_MODE, IR_CONFIG_1); - break; - case 19200: - writel(5<<10 | 12<<5, IR_WRITE_PHY_CONFIG); - writel(IR_SIR_MODE, IR_CONFIG_1); - break; - case 38400: - writel(2<<10 | 12<<5, IR_WRITE_PHY_CONFIG); - writel(IR_SIR_MODE, IR_CONFIG_1); - break; - case 57600: - writel(1<<10 | 12<<5, IR_WRITE_PHY_CONFIG); - writel(IR_SIR_MODE, IR_CONFIG_1); - break; - case 115200: - writel(12<<5, IR_WRITE_PHY_CONFIG); - writel(IR_SIR_MODE, IR_CONFIG_1); - break; - case 4000000: - writel(0xF, IR_WRITE_PHY_CONFIG); - writel(IR_FIR|IR_DMA_ENABLE|IR_RX_ENABLE, IR_CONFIG_1); - break; - default: - printk(KERN_ERR "%s unsupported speed %x\n", dev->name, speed); - ret = -EINVAL; - break; + if (aup->speed == 4000000) { + /* FIR */ + skb_copy_from_linear_data(skb, (void *)pDB->vaddr, skb->len); + ptxd->count_0 = skb->len & 0xff; + ptxd->count_1 = (skb->len >> 8) & 0xff; + } else { + /* SIR */ + len = async_wrap_skb(skb, (u8 *)pDB->vaddr, MAX_BUF_SIZE); + ptxd->count_0 = len & 0xff; + ptxd->count_1 = (len >> 8) & 0xff; + ptxd->flags |= IR_DIS_CRC; } - - aup->speed = speed; - writel(read_ir_reg(IR_ENABLE) | 0x8000, IR_ENABLE); + ptxd->flags |= AU_OWN; au_sync(); - control = read_ir_reg(IR_ENABLE); - writel(0, IR_RING_PROMPT); + irda_write(aup, IR_CONFIG_1, + irda_read(aup, IR_CONFIG_1) | IR_TX_ENABLE); + irda_write(aup, IR_RING_PROMPT, 0); au_sync(); - if (control & (1<<14)) { - printk(KERN_ERR "%s: configuration error\n", dev->name); - } - else { - if (control & (1<<11)) - printk(KERN_DEBUG "%s Valid SIR config\n", dev->name); - if (control & (1<<12)) - printk(KERN_DEBUG "%s Valid MIR config\n", dev->name); - if (control & (1<<13)) - printk(KERN_DEBUG "%s Valid FIR config\n", dev->name); - if (control & (1<<10)) - printk(KERN_DEBUG "%s TX enabled\n", dev->name); - if (control & (1<<9)) - printk(KERN_DEBUG "%s RX enabled\n", dev->name); - } + dev_kfree_skb(skb); + aup->tx_head = (aup->tx_head + 1) & (NUM_IR_DESC - 1); + dev->trans_start = jiffies; + return 0; +} - spin_unlock_irqrestore(&ir_lock, flags); - return ret; +/* + * The Tx ring has been full longer than the watchdog timeout + * value. The transmitter must be hung? + */ +static void au1k_tx_timeout(struct net_device *dev) +{ + u32 speed; + struct au1k_private *aup = netdev_priv(dev); + + printk(KERN_ERR "%s: tx timeout\n", dev->name); + speed = aup->speed; + aup->speed = 0; + au1k_irda_set_speed(dev, speed); + aup->tx_full = 0; + netif_wake_queue(dev); } -static int +static int au1k_irda_ioctl(struct net_device *dev, struct ifreq *ifreq, int cmd) { struct if_irda_req *rq = (struct if_irda_req *)ifreq; @@ -830,8 +759,214 @@ au1k_irda_ioctl(struct net_device *dev, struct ifreq *ifreq, int cmd) return ret; } +static int __devinit au1k_irda_net_init(struct net_device *dev) +{ + struct au1k_private *aup = netdev_priv(dev); + struct db_dest *pDB, *pDBfree; + int i, retval = 0, err; + dma_addr_t temp; + + err = au1k_irda_init_iobuf(&aup->rx_buff, 14384); + if (err) + goto out1; + + dev->open = au1k_irda_start; + dev->hard_start_xmit = au1k_irda_hard_xmit; + dev->stop = au1k_irda_stop; + dev->do_ioctl = au1k_irda_ioctl; + dev->tx_timeout = au1k_tx_timeout; + + irda_init_max_qos_capabilies(&aup->qos); + + /* The only value we must override it the baudrate */ + aup->qos.baud_rate.bits = IR_9600 | IR_19200 | IR_38400 | + IR_57600 | IR_115200 | IR_576000 | (IR_4000000 << 8); + + aup->qos.min_turn_time.bits = qos_mtt_bits; + irda_qos_bits_to_value(&aup->qos); + + retval = -ENOMEM; + + /* Tx ring follows rx ring + 512 bytes */ + /* we need a 1k aligned buffer */ + aup->rx_ring[0] = (struct ring_dest *) + dma_alloc(2*MAX_NUM_IR_DESC*(sizeof(struct ring_dest)), &temp); + if (!aup->rx_ring[0]) + goto out2; + + /* allocate the data buffers */ + aup->db[0].vaddr = + (void *)dma_alloc(MAX_BUF_SIZE * 2*NUM_IR_DESC, &temp); + if (!aup->db[0].vaddr) + goto out3; + + setup_hw_rings(aup, (u32)aup->rx_ring[0], (u32)aup->rx_ring[0] + 512); + + pDBfree = NULL; + pDB = aup->db; + for (i = 0; i < (2 * NUM_IR_DESC); i++) { + pDB->pnext = pDBfree; + pDBfree = pDB; + pDB->vaddr = + (u32 *)((unsigned)aup->db[0].vaddr + MAX_BUF_SIZE*i); + pDB->dma_addr = (dma_addr_t)virt_to_bus(pDB->vaddr); + pDB++; + } + aup->pDBfree = pDBfree; + + /* attach a data buffer to each descriptor */ + for (i = 0; i < NUM_IR_DESC; i++) { + pDB = GetFreeDB(aup); + if (!pDB) + goto out3; + aup->rx_ring[i]->addr_0 = (u8)(pDB->dma_addr & 0xff); + aup->rx_ring[i]->addr_1 = (u8)((pDB->dma_addr>>8) & 0xff); + aup->rx_ring[i]->addr_2 = (u8)((pDB->dma_addr>>16) & 0xff); + aup->rx_ring[i]->addr_3 = (u8)((pDB->dma_addr>>24) & 0xff); + aup->rx_db_inuse[i] = pDB; + } + for (i = 0; i < NUM_IR_DESC; i++) { + pDB = GetFreeDB(aup); + if (!pDB) + goto out3; + aup->tx_ring[i]->addr_0 = (u8)(pDB->dma_addr & 0xff); + aup->tx_ring[i]->addr_1 = (u8)((pDB->dma_addr>>8) & 0xff); + aup->tx_ring[i]->addr_2 = (u8)((pDB->dma_addr>>16) & 0xff); + aup->tx_ring[i]->addr_3 = (u8)((pDB->dma_addr>>24) & 0xff); + aup->tx_ring[i]->count_0 = 0; + aup->tx_ring[i]->count_1 = 0; + aup->tx_ring[i]->flags = 0; + aup->tx_db_inuse[i] = pDB; + } + + return 0; + +out3: + dma_free((void *)aup->rx_ring[0], + 2 * MAX_NUM_IR_DESC*(sizeof(struct ring_dest))); +out2: + kfree(aup->rx_buff.head); +out1: + printk(KERN_ERR "au1k_irda_net_init() failed. Returns %d\n", retval); + return retval; +} + +static int __devinit au1k_irda_probe(struct platform_device *pdev) +{ + struct au1k_private *aup; + struct net_device *dev; + struct resource *r; + int err; + + dev = alloc_irdadev(sizeof(struct au1k_private)); + if (!dev) + return -ENOMEM; + + aup = netdev_priv(dev); + + aup->platdata = pdev->dev.platform_data; + + err = -EINVAL; + r = platform_get_resource(pdev, IORESOURCE_IRQ, 0); + if (!r) + goto out; + + aup->irq_tx = r->start; + + r = platform_get_resource(pdev, IORESOURCE_IRQ, 1); + if (!r) + goto out; + + aup->irq_rx = r->start; + + r = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!r) + goto out; + + err = -EBUSY; + aup->ioarea = request_mem_region(r->start, r->end - r->start + 1, + pdev->name); + if (!aup->ioarea) + goto out; + + aup->iobase = ioremap_nocache(r->start, r->end - r->start + 1); + if (!aup->iobase) + goto out2; + + dev->irq = aup->irq_rx; + + err = au1k_irda_net_init(dev); + if (err) + goto out3; + err = register_netdev(dev); + if (err) + goto out4; + + platform_set_drvdata(pdev, dev); + + printk(KERN_INFO "IrDA: Registered device %s\n", dev->name); + return 0; + +out4: + dma_free((void *)aup->db[0].vaddr, + MAX_BUF_SIZE * 2 * NUM_IR_DESC); + dma_free((void *)aup->rx_ring[0], + 2 * MAX_NUM_IR_DESC*(sizeof(struct ring_dest))); + kfree(aup->rx_buff.head); +out3: + iounmap(aup->iobase); +out2: + release_resource(aup->ioarea); + kfree(aup->ioarea); +out: + free_netdev(dev); + return err; +} + +static int __devexit au1k_irda_remove(struct platform_device *pdev) +{ + struct net_device *dev = platform_get_drvdata(pdev); + struct au1k_private *aup = netdev_priv(dev); + + unregister_netdev(dev); + + dma_free((void *)aup->db[0].vaddr, + MAX_BUF_SIZE * 2*NUM_IR_DESC); + dma_free((void *)aup->rx_ring[0], + 2 * MAX_NUM_IR_DESC*(sizeof(struct ring_dest))); + kfree(aup->rx_buff.head); + + iounmap(aup->iobase); + release_resource(aup->ioarea); + kfree(aup->ioarea); + + free_netdev(dev); + + return 0; +} + +static struct platform_driver au1k_irda_driver = { + .driver = { + .name = "au1000-irda", + .owner = THIS_MODULE, + }, + .probe = au1k_irda_probe, + .remove = __devexit_p(au1k_irda_remove), +}; + +static int __init au1k_irda_load(void) +{ + printk(version); + return platform_driver_probe(&au1k_irda_driver, au1k_irda_probe); +} + +static void __exit au1k_irda_unload(void) +{ + return platform_driver_unregister(&au1k_irda_driver); +} + MODULE_AUTHOR("Pete Popov "); MODULE_DESCRIPTION("Au1000 IrDA Device Driver"); -module_init(au1k_irda_init); -module_exit(au1k_irda_exit); +module_init(au1k_irda_load); +module_exit(au1k_irda_unload); -- 1.6.0.6 From anemo@mba.ocn.ne.jp Mon Jan 19 14:10:25 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 19 Jan 2009 14:10:28 +0000 (GMT) Received: from mba.ocn.ne.jp ([122.1.235.107]:48363 "HELO smtp.mba.ocn.ne.jp") by ftp.linux-mips.org with SMTP id S21366094AbZASOKZ (ORCPT ); Mon, 19 Jan 2009 14:10:25 +0000 Received: from localhost.localdomain (p1127-ipad204funabasi.chiba.ocn.ne.jp [222.146.88.127]) by smtp.mba.ocn.ne.jp (Postfix) with ESMTP id 3ED37A47B; Mon, 19 Jan 2009 23:10:20 +0900 (JST) From: Atsushi Nemoto To: linux-ide@vger.kernel.org Cc: Bartlomiej Zolnierkiewicz , sshtylyov@ru.mvista.com, linux-mips@linux-mips.org Subject: [PATCH] tx4939ide: typo fix and minor cleanup Date: Mon, 19 Jan 2009 23:10:25 +0900 Message-Id: <1232374225-5325-1-git-send-email-anemo@mba.ocn.ne.jp> X-Mailer: git-send-email 1.5.6.3 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21776 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anemo@mba.ocn.ne.jp Precedence: bulk X-list: linux-mips Content-Length: 935 Lines: 28 The bcount is greater than 0 and less than or equal to 0x10000. Thus '(bcount & 0xffff) == 0x0000' can be simplified as 'bcount == 0x10000'. Suggested-by: Sergei Shtylyov Signed-off-by: Atsushi Nemoto --- drivers/ide/tx4939ide.c | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/ide/tx4939ide.c b/drivers/ide/tx4939ide.c index 882f6f0..40b0812 100644 --- a/drivers/ide/tx4939ide.c +++ b/drivers/ide/tx4939ide.c @@ -261,9 +261,9 @@ static int tx4939ide_build_dmatable(ide_drive_t *drive, struct request *rq) bcount = cur_len; /* * This workaround for zero count seems required. - * (standard ide_build_dmatable do it too) + * (standard ide_build_dmatable does it too) */ - if ((bcount & 0xffff) == 0x0000) + if (bcount == 0x10000) bcount = 0x8000; *table++ = bcount & 0xffff; *table++ = cur_addr; -- 1.5.6.3 From f.fainelli@gmail.com Mon Jan 19 17:12:31 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 19 Jan 2009 17:12:34 +0000 (GMT) Received: from ug-out-1314.google.com ([66.249.92.175]:63723 "EHLO ug-out-1314.google.com") by ftp.linux-mips.org with ESMTP id S21365752AbZASRMb convert rfc822-to-8bit (ORCPT ); Mon, 19 Jan 2009 17:12:31 +0000 Received: by ug-out-1314.google.com with SMTP id k40so221433ugc.2 for ; Mon, 19 Jan 2009 09:12:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:sender:from:to:subject:date :user-agent:cc:references:in-reply-to:mime-version:content-type :content-transfer-encoding:content-disposition:message-id; bh=GdA38ahhiAFWduC7YfwypjlqrkqJMWmw65lCGAK62hE=; b=keY7ltQ7o/Kk5R/WftHxPjgrpPxoEnUUBCrSDCMa+34jFUpNG5+isrBZAV0RB9Uvlo ZI0HfHh6917MAGgRTuGh/vu36WuCPltD2YnJQUol0B4ZgiYoZM3M4sR1kAwzMMoJYyaa yZNBJIWehpJ3hRQzb/SRy9m15yzMJp+oUiBzw= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:from:to:subject:date:user-agent:cc:references:in-reply-to :mime-version:content-type:content-transfer-encoding :content-disposition:message-id; b=utdBX+mnwJ0wup5L/Y9gduUrusRg1WUnrFHLTPIx0Rd3DyOhvYAv//4A3+LtXm2iwN 3mlnM7Js2Uop3CXIEBjXsaLeyHe3IzhBW10vh21dS4pydj8lbPrfNCOaDhvcSJESLVpm KoQdZCqPo/XZRPdxjYoqxJQVXla2/9s9zhNQ8= Received: by 10.67.116.12 with SMTP id t12mr1692586ugm.58.1232385150641; Mon, 19 Jan 2009 09:12:30 -0800 (PST) Received: from flowlan.maisel.int-evry.fr ([157.159.47.25]) by mx.google.com with ESMTPS id k30sm10585105ugc.59.2009.01.19.09.12.29 (version=TLSv1/SSLv3 cipher=RC4-MD5); Mon, 19 Jan 2009 09:12:29 -0800 (PST) From: Florian Fainelli To: Manuel Lauss Subject: Re: [PATCH] au1000: convert to using gpiolib Date: Mon, 19 Jan 2009 18:12:23 +0100 User-Agent: KMail/1.9.9 Cc: ralf@linux-mips.org, Linux-MIPS References: <200901151646.49591.florian@openwrt.org> <86ee6fd0901160210pdb7f52nf761f8706a56f8fe@mail.gmail.com> <20090116174753.GA18764@roarinelk.homelinux.net> In-Reply-To: <20090116174753.GA18764@roarinelk.homelinux.net> MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 8BIT Content-Disposition: inline Message-Id: <200901191812.24377.florian@openwrt.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21777 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips Content-Length: 11086 Lines: 395 Hi Manuel, Le Friday 16 January 2009 18:47:53 Manuel Lauss, vous avez écrit : > Hi Florian, > > On Fri, Jan 16, 2009 at 11:10:25AM +0100, Florian Fainelli wrote: > > > Can you please make the gpiolib registration dependent on a > > > CONFIG symbol? I.e. make the au1000_gpio{,2}_direction() and > > > friends calls globally visible but let the individual boards > > > decide whether they want to use the gpio numbering imposed by > > > this patch. > > > > Would something like #ifdef CONFIG_AU1000_NON_STD_GPIOS be ok with you ? > > Or maybe we could get the base information from board-specific code ? > > Well, we could move the core_initcall() to all boards' setup function, > and stick a comment on top of it explaining why it's there. > > Config symbol or the above, either is fine with me. I would prefer the config symbol, there is only one file to change ;). Patch attached below: -- From: Florian Fainelli Subject: [PATCH v2] au1000: convert to using gpiolib This patch converts the GPIO board code to use gpiolib. Changes from v1: - allow users not to use the default gpio accessors - do not lock au1000_gpio2_set Signed-off-by: Florian Fainelli -- diff --git a/arch/mips/alchemy/Kconfig b/arch/mips/alchemy/Kconfig index 7f8ef13..2fc5c13 100644 --- a/arch/mips/alchemy/Kconfig +++ b/arch/mips/alchemy/Kconfig @@ -135,3 +135,4 @@ config SOC_AU1X00 select SYS_SUPPORTS_32BIT_KERNEL select SYS_SUPPORTS_APM_EMULATION select GENERIC_HARDIRQS_NO__DO_IRQ + select ARCH_REQUIRE_GPIOLIB diff --git a/arch/mips/alchemy/common/gpio.c b/arch/mips/alchemy/common/gpio.c index e660ddd..9ac1e4c 100644 --- a/arch/mips/alchemy/common/gpio.c +++ b/arch/mips/alchemy/common/gpio.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2007, OpenWrt.org, Florian Fainelli + * Copyright (C) 2007-2009, OpenWrt.org, Florian Fainelli * Architecture specific GPIO support * * This program is free software; you can redistribute it and/or modify it @@ -27,122 +27,172 @@ * others have a second one : GPIO2 */ +#include #include +#include +#include +#include #include #include -#define gpio1 sys -#if !defined(CONFIG_SOC_AU1000) - -static struct au1x00_gpio2 *const gpio2 = (struct au1x00_gpio2 *) GPIO2_BASE; -#define GPIO2_OUTPUT_ENABLE_MASK 0x00010000 +struct au1000_gpio_chip { + struct gpio_chip chip; + void __iomem *regbase; +}; -static int au1xxx_gpio2_read(unsigned gpio) +#if !defined(CONFIG_SOC_AU1000) +static int au1000_gpio2_get(struct gpio_chip *chip, unsigned offset) { - gpio -= AU1XXX_GPIO_BASE; - return ((gpio2->pinstate >> gpio) & 0x01); + u32 mask = 1 << offset; + struct au1000_gpio_chip *gpch; + + gpch = container_of(chip, struct au1000_gpio_chip, chip); + return readl(gpch->regbase + AU1000_GPIO2_ST) & mask; } -static void au1xxx_gpio2_write(unsigned gpio, int value) +static void au1000_gpio2_set(struct gpio_chip *chip, + unsigned offset, int value) { - gpio -= AU1XXX_GPIO_BASE; + u32 mask = ((GPIO2_OUT_EN_MASK << offset) | (!!value << offset)); + struct au1000_gpio_chip *gpch; - gpio2->output = (GPIO2_OUTPUT_ENABLE_MASK << gpio) | ((!!value) << gpio); + gpch = container_of(chip, struct au1000_gpio_chip, chip); + writel(mask, gpch->regbase + AU1000_GPIO2_OUT); } -static int au1xxx_gpio2_direction_input(unsigned gpio) +static int au1000_gpio2_direction_input(struct gpio_chip *chip, unsigned offset) { - gpio -= AU1XXX_GPIO_BASE; - gpio2->dir &= ~(0x01 << gpio); + u32 mask = 1 << offset; + u32 tmp; + struct au1000_gpio_chip *gpch; + unsigned long flags; + + gpch = container_of(chip, struct au1000_gpio_chip, chip); + + local_irq_save(flags); + tmp = readl(gpch->regbase + AU1000_GPIO2_DIR); + tmp &= ~mask; + writel(tmp, gpch->regbase + AU1000_GPIO2_DIR); + local_irq_restore(flags); + return 0; } -static int au1xxx_gpio2_direction_output(unsigned gpio, int value) +static int au1000_gpio2_direction_output(struct gpio_chip *chip, + unsigned offset, int value) { - gpio -= AU1XXX_GPIO_BASE; - gpio2->dir |= 0x01 << gpio; - gpio2->output = (GPIO2_OUTPUT_ENABLE_MASK << gpio) | ((!!value) << gpio); + u32 mask = 1 << offset; + u32 out_mask = ((GPIO2_OUT_EN_MASK << offset) | (!!value << offset)); + u32 tmp; + struct au1000_gpio_chip *gpch; + unsigned long flags; + + gpch = container_of(chip, struct au1000_gpio_chip, chip); + + local_irq_save(flags); + tmp = readl(gpch->regbase + AU1000_GPIO2_DIR); + tmp |= mask; + writel(tmp, gpch->regbase + AU1000_GPIO2_DIR); + writel(out_mask, gpch->regbase + AU1000_GPIO2_OUT); + local_irq_restore(flags); + return 0; } - #endif /* !defined(CONFIG_SOC_AU1000) */ -static int au1xxx_gpio1_read(unsigned gpio) +static int au1000_gpio1_get(struct gpio_chip *chip, unsigned offset) { - return (gpio1->pinstaterd >> gpio) & 0x01; + u32 mask = 1 << offset; + struct au1000_gpio_chip *gpch; + + gpch = container_of(chip, struct au1000_gpio_chip, chip); + return readl(gpch->regbase + AU1000_GPIO1_ST) & mask; } -static void au1xxx_gpio1_write(unsigned gpio, int value) +static void au1000_gpio1_set(struct gpio_chip *chip, + unsigned offset, int value) { + u32 mask = 1 << offset; + u32 reg_offset; + struct au1000_gpio_chip *gpch; + unsigned long flags; + + gpch = container_of(chip, struct au1000_gpio_chip, chip); + if (value) - gpio1->outputset = (0x01 << gpio); + reg_offset = AU1000_GPIO1_OUT; else - /* Output a zero */ - gpio1->outputclr = (0x01 << gpio); + reg_offset = AU1000_GPIO1_CLR; + + local_irq_save(flags); + writel(mask, gpch->regbase + reg_offset); + local_irq_restore(flags); } -static int au1xxx_gpio1_direction_input(unsigned gpio) +static int au1000_gpio1_direction_input(struct gpio_chip *chip, unsigned offset) { - gpio1->pininputen = (0x01 << gpio); + u32 mask = 1 << offset; + struct au1000_gpio_chip *gpch; + + gpch = container_of(chip, struct au1000_gpio_chip, chip); + writel(mask, gpch->regbase + AU1000_GPIO1_ST); + return 0; } -static int au1xxx_gpio1_direction_output(unsigned gpio, int value) +static int au1000_gpio1_direction_output(struct gpio_chip *chip, + unsigned offset, int value) { - gpio1->trioutclr = (0x01 & gpio); - au1xxx_gpio1_write(gpio, value); + u32 mask = 1 << offset; + struct au1000_gpio_chip *gpch; + + gpch = container_of(chip, struct au1000_gpio_chip, chip); + + writel(mask, gpch->regbase + AU1000_GPIO1_TRI_OUT); + au1000_gpio1_set(chip, offset, value); + return 0; } -int au1xxx_gpio_get_value(unsigned gpio) -{ - if (gpio >= AU1XXX_GPIO_BASE) -#if defined(CONFIG_SOC_AU1000) - return 0; -#else - return au1xxx_gpio2_read(gpio); +struct au1000_gpio_chip au1000_gpio_chip[] = { + [0] = { + .regbase = (void __iomem *)SYS_BASE, + .chip = { + .label = "au1000-gpio1", + .direction_input = au1000_gpio1_direction_input, + .direction_output = au1000_gpio1_direction_output, + .get = au1000_gpio1_get, + .set = au1000_gpio1_set, + .base = 0, + .ngpio = 32, + }, + }, +#if !defined(CONFIG_SOC_AU1000) + [1] = { + .regbase = (void __iomem *)GPIO2_BASE, + .chip = { + .label = "au1000-gpio2", + .direction_input = au1000_gpio2_direction_input, + .direction_output = au1000_gpio2_direction_output, + .get = au1000_gpio2_get, + .set = au1000_gpio2_set, + .base = AU1XXX_GPIO2_BASE, + .ngpio = 32, + }, + }, #endif - else - return au1xxx_gpio1_read(gpio); -} -EXPORT_SYMBOL(au1xxx_gpio_get_value); +}; -void au1xxx_gpio_set_value(unsigned gpio, int value) +static int __init au1000_gpio_init(void) { - if (gpio >= AU1XXX_GPIO_BASE) -#if defined(CONFIG_SOC_AU1000) - ; -#else - au1xxx_gpio2_write(gpio, value); -#endif - else - au1xxx_gpio1_write(gpio, value); -} -EXPORT_SYMBOL(au1xxx_gpio_set_value); + gpiochip_add(&au1000_gpio_chip[0].chip); +#if !defined(CONFIG_SOC_AU1000) + gpiochip_add(&au1000_gpio_chip[1].chip); -int au1xxx_gpio_direction_input(unsigned gpio) -{ - if (gpio >= AU1XXX_GPIO_BASE) -#if defined(CONFIG_SOC_AU1000) - return -ENODEV; -#else - return au1xxx_gpio2_direction_input(gpio); + return 0; #endif - - return au1xxx_gpio1_direction_input(gpio); } -EXPORT_SYMBOL(au1xxx_gpio_direction_input); - -int au1xxx_gpio_direction_output(unsigned gpio, int value) -{ - if (gpio >= AU1XXX_GPIO_BASE) -#if defined(CONFIG_SOC_AU1000) - return -ENODEV; -#else - return au1xxx_gpio2_direction_output(gpio, value); +#ifndef CONFIG_AU1X00_NON_STD_GPIOS +arch_initcall(au1000_gpio_init); #endif - - return au1xxx_gpio1_direction_output(gpio, value); -} -EXPORT_SYMBOL(au1xxx_gpio_direction_output); diff --git a/arch/mips/include/asm/mach-au1x00/gpio.h b/arch/mips/include/asm/mach-au1x00/gpio.h index 2dc61e0..f1a5d48 100644 --- a/arch/mips/include/asm/mach-au1x00/gpio.h +++ b/arch/mips/include/asm/mach-au1x00/gpio.h @@ -3,67 +3,31 @@ #include -#define AU1XXX_GPIO_BASE 200 +#define AU1XXX_GPIO2_BASE 200 -struct au1x00_gpio2 { - u32 dir; - u32 reserved; - u32 output; - u32 pinstate; - u32 inten; - u32 enable; -}; +/* GPIO bank 1 offsets */ +#define AU1000_GPIO1_TRI_OUT 0x0100 +#define AU1000_GPIO1_OUT 0x0108 +#define AU1000_GPIO1_ST 0x0110 +#define AU1000_GPIO1_CLR 0x010C -extern int au1xxx_gpio_get_value(unsigned gpio); -extern void au1xxx_gpio_set_value(unsigned gpio, int value); -extern int au1xxx_gpio_direction_input(unsigned gpio); -extern int au1xxx_gpio_direction_output(unsigned gpio, int value); +/* GPIO bank 2 offsets */ +#define AU1000_GPIO2_DIR 0x00 +#define AU1000_GPIO2_RSVD 0x04 +#define AU1000_GPIO2_OUT 0x08 +#define AU1000_GPIO2_ST 0x0C +#define AU1000_GPIO2_INT 0x10 +#define AU1000_GPIO2_EN 0x14 +#define GPIO2_OUT_EN_MASK 0x00010000 -/* Wrappers for the arch-neutral GPIO API */ +#define gpio_to_irq(gpio) NULL -static inline int gpio_request(unsigned gpio, const char *label) -{ - /* Not yet implemented */ - return 0; -} +#define gpio_get_value __gpio_get_value +#define gpio_set_value __gpio_set_value -static inline void gpio_free(unsigned gpio) -{ - /* Not yet implemented */ -} +#define gpio_cansleep __gpio_cansleep -static inline int gpio_direction_input(unsigned gpio) -{ - return au1xxx_gpio_direction_input(gpio); -} - -static inline int gpio_direction_output(unsigned gpio, int value) -{ - return au1xxx_gpio_direction_output(gpio, value); -} - -static inline int gpio_get_value(unsigned gpio) -{ - return au1xxx_gpio_get_value(gpio); -} - -static inline void gpio_set_value(unsigned gpio, int value) -{ - au1xxx_gpio_set_value(gpio, value); -} - -static inline int gpio_to_irq(unsigned gpio) -{ - return gpio; -} - -static inline int irq_to_gpio(unsigned irq) -{ - return irq; -} - -/* For cansleep */ #include #endif /* _AU1XXX_GPIO_H_ */ -- Best regards, Florian Fainelli Email : florian@openwrt.org http://openwrt.org ------------------------------- From n0-1@nwl.cc Mon Jan 19 22:43:08 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 19 Jan 2009 22:43:10 +0000 (GMT) Received: from orbit.nwl.cc ([91.121.169.95]:58081 "EHLO mail.nwl.cc") by ftp.linux-mips.org with ESMTP id S21365788AbZASWnH (ORCPT ); Mon, 19 Jan 2009 22:43:07 +0000 Received: from base (localhost [127.0.0.1]) by mail.nwl.cc (Postfix) with ESMTP id 1B5A9400E106; Mon, 19 Jan 2009 23:43:02 +0100 (CET) From: Phil Sutter To: Linux-Mips List Cc: ralf@linux-mips.org, florian@openwrt.org Subject: [PATCH 3/5] MIPS: rb532: move dev3 init code to devices.c Date: Mon, 19 Jan 2009 23:42:52 +0100 X-Mailer: git-send-email 1.5.6.4 In-Reply-To: <1232404974-18497-2-git-send-email-n0-1@freewrt.org> References: <1232404974-18497-1-git-send-email-n0-1@freewrt.org> <1232404974-18497-2-git-send-email-n0-1@freewrt.org> Message-Id: <20090119224302.1B5A9400E106@mail.nwl.cc> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21778 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: n0-1@freewrt.org Precedence: bulk X-list: linux-mips Content-Length: 3589 Lines: 141 This code doesn't belong to gpio.c, as it's completely unrelated to GPIO. As dev1 and dev2 init code is in devices.c, it seems to be a more adequate place. Signed-off-by: Phil Sutter --- arch/mips/rb532/devices.c | 39 +++++++++++++++++++++++++++++++++++++++ arch/mips/rb532/gpio.c | 39 --------------------------------------- 2 files changed, 39 insertions(+), 39 deletions(-) diff --git a/arch/mips/rb532/devices.c b/arch/mips/rb532/devices.c index 3c74561..1a0209e 100644 --- a/arch/mips/rb532/devices.c +++ b/arch/mips/rb532/devices.c @@ -42,6 +42,34 @@ extern unsigned int idt_cpu_freq; +static struct mpmc_device dev3; + +void set_latch_u5(unsigned char or_mask, unsigned char nand_mask) +{ + unsigned long flags; + + spin_lock_irqsave(&dev3.lock, flags); + + dev3.state = (dev3.state | or_mask) & ~nand_mask; + writeb(dev3.state, dev3.base); + + spin_unlock_irqrestore(&dev3.lock, flags); +} +EXPORT_SYMBOL(set_latch_u5); + +unsigned char get_latch_u5(void) +{ + return dev3.state; +} +EXPORT_SYMBOL(get_latch_u5); + +static struct resource rb532_dev3_ctl_res[] = { + { + .name = "dev3_ctl", + .flags = IORESOURCE_MEM, + } +}; + static struct resource korina_dev0_res[] = { { .name = "korina_regs", @@ -314,6 +342,17 @@ static int __init plat_setup_devices(void) nand_slot0_res[0].start = readl(IDT434_REG_BASE + DEV2BASE); nand_slot0_res[0].end = nand_slot0_res[0].start + 0x1000; + /* Read the third (multi purpose) resources from the DC */ + rb532_dev3_ctl_res[0].start = readl(IDT434_REG_BASE + DEV3BASE); + rb532_dev3_ctl_res[0].end = rb532_dev3_ctl_res[0].start + 0x1000; + + dev3.base = ioremap_nocache(rb532_dev3_ctl_res[0].start, 0x1000); + + if (!dev3.base) { + printk(KERN_ERR "rb532: cannot remap device controller 3\n"); + return -ENXIO; + } + /* Initialise the NAND device */ rb532_nand_setup(); diff --git a/arch/mips/rb532/gpio.c b/arch/mips/rb532/gpio.c index 7e0cb4f..b9cb428 100644 --- a/arch/mips/rb532/gpio.c +++ b/arch/mips/rb532/gpio.c @@ -41,8 +41,6 @@ struct rb532_gpio_chip { void __iomem *regbase; }; -struct mpmc_device dev3; - static struct resource rb532_gpio_reg0_res[] = { { .name = "gpio_reg0", @@ -52,13 +50,6 @@ static struct resource rb532_gpio_reg0_res[] = { } }; -static struct resource rb532_dev3_ctl_res[] = { - { - .name = "dev3_ctl", - .flags = IORESOURCE_MEM, - } -}; - void set_434_reg(unsigned reg_offs, unsigned bit, unsigned len, unsigned val) { unsigned long flags; @@ -86,25 +77,6 @@ unsigned get_434_reg(unsigned reg_offs) } EXPORT_SYMBOL(get_434_reg); -void set_latch_u5(unsigned char or_mask, unsigned char nand_mask) -{ - unsigned long flags; - - spin_lock_irqsave(&dev3.lock, flags); - - dev3.state = (dev3.state | or_mask) & ~nand_mask; - writeb(dev3.state, dev3.base); - - spin_unlock_irqrestore(&dev3.lock, flags); -} -EXPORT_SYMBOL(set_latch_u5); - -unsigned char get_latch_u5(void) -{ - return dev3.state; -} -EXPORT_SYMBOL(get_latch_u5); - /* rb532_set_bit - sanely set a bit * * bitval: new value for the bit @@ -241,17 +213,6 @@ int __init rb532_gpio_init(void) /* Register our GPIO chip */ gpiochip_add(&rb532_gpio_chip->chip); - rb532_dev3_ctl_res[0].start = readl(IDT434_REG_BASE + DEV3BASE); - rb532_dev3_ctl_res[0].end = rb532_dev3_ctl_res[0].start + 0x1000; - - r = rb532_dev3_ctl_res; - dev3.base = ioremap_nocache(r->start, r->end - r->start); - - if (!dev3.base) { - printk(KERN_ERR "rb532: cannot remap device controller 3\n"); - return -ENXIO; - } - return 0; } arch_initcall(rb532_gpio_init); -- 1.5.6.4 From n0-1@nwl.cc Mon Jan 19 22:43:27 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 19 Jan 2009 22:43:30 +0000 (GMT) Received: from orbit.nwl.cc ([91.121.169.95]:58849 "EHLO mail.nwl.cc") by ftp.linux-mips.org with ESMTP id S21366174AbZASWnK (ORCPT ); Mon, 19 Jan 2009 22:43:10 +0000 Received: from base (localhost [127.0.0.1]) by mail.nwl.cc (Postfix) with ESMTP id EAA84400E123; Mon, 19 Jan 2009 23:43:04 +0100 (CET) From: Phil Sutter To: Linux-Mips List Cc: ralf@linux-mips.org, florian@openwrt.org Subject: [PATCH 5/5] MIPS: rb532: simplify dev3 init Date: Mon, 19 Jan 2009 23:42:54 +0100 X-Mailer: git-send-email 1.5.6.4 In-Reply-To: <1232404974-18497-4-git-send-email-n0-1@freewrt.org> References: <1232404974-18497-1-git-send-email-n0-1@freewrt.org> <1232404974-18497-2-git-send-email-n0-1@freewrt.org> <1232404974-18497-3-git-send-email-n0-1@freewrt.org> <1232404974-18497-4-git-send-email-n0-1@freewrt.org> Message-Id: <20090119224304.EAA84400E123@mail.nwl.cc> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21779 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: n0-1@freewrt.org Precedence: bulk X-list: linux-mips Content-Length: 1560 Lines: 47 As rb532_dev3_ctl_res is not used by any platform device, it can be dropped when not used for holding the physical address of the device 3 controller. Also a size of one byte should suffice when ioremapping the physical address mentioned above, as only a single byte is being read from and written to it. Signed-off-by: Phil Sutter --- arch/mips/rb532/devices.c | 14 ++------------ 1 files changed, 2 insertions(+), 12 deletions(-) diff --git a/arch/mips/rb532/devices.c b/arch/mips/rb532/devices.c index 1a0209e..4a5f05b 100644 --- a/arch/mips/rb532/devices.c +++ b/arch/mips/rb532/devices.c @@ -63,13 +63,6 @@ unsigned char get_latch_u5(void) } EXPORT_SYMBOL(get_latch_u5); -static struct resource rb532_dev3_ctl_res[] = { - { - .name = "dev3_ctl", - .flags = IORESOURCE_MEM, - } -}; - static struct resource korina_dev0_res[] = { { .name = "korina_regs", @@ -342,11 +335,8 @@ static int __init plat_setup_devices(void) nand_slot0_res[0].start = readl(IDT434_REG_BASE + DEV2BASE); nand_slot0_res[0].end = nand_slot0_res[0].start + 0x1000; - /* Read the third (multi purpose) resources from the DC */ - rb532_dev3_ctl_res[0].start = readl(IDT434_REG_BASE + DEV3BASE); - rb532_dev3_ctl_res[0].end = rb532_dev3_ctl_res[0].start + 0x1000; - - dev3.base = ioremap_nocache(rb532_dev3_ctl_res[0].start, 0x1000); + /* Read and map device controller 3 */ + dev3.base = ioremap_nocache(readl(IDT434_REG_BASE + DEV3BASE), 1); if (!dev3.base) { printk(KERN_ERR "rb532: cannot remap device controller 3\n"); -- 1.5.6.4 From n0-1@nwl.cc Mon Jan 19 22:43:47 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 19 Jan 2009 22:43:51 +0000 (GMT) Received: from orbit.nwl.cc ([91.121.169.95]:59617 "EHLO mail.nwl.cc") by ftp.linux-mips.org with ESMTP id S21366187AbZASWnN (ORCPT ); Mon, 19 Jan 2009 22:43:13 +0000 Received: from base (localhost [127.0.0.1]) by mail.nwl.cc (Postfix) with ESMTP id B8BF1400E125; Mon, 19 Jan 2009 23:43:07 +0100 (CET) From: Phil Sutter To: Linux-Mips List Cc: ralf@linux-mips.org, florian@openwrt.org Subject: [PATCH 2/5] MIPS: rb532: fix set_latch_u5() Date: Mon, 19 Jan 2009 23:42:51 +0100 X-Mailer: git-send-email 1.5.6.4 In-Reply-To: <1232404974-18497-1-git-send-email-n0-1@freewrt.org> References: <1232404974-18497-1-git-send-email-n0-1@freewrt.org> Message-Id: <20090119224307.B8BF1400E125@mail.nwl.cc> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21780 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: n0-1@freewrt.org Precedence: bulk X-list: linux-mips Content-Length: 746 Lines: 25 The data to be written is just a byte, so use writeb instead of writel. Also, dev3.base contains the address, not the data so referencing here is wrong. Signed-off-by: Phil Sutter --- arch/mips/rb532/gpio.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/mips/rb532/gpio.c b/arch/mips/rb532/gpio.c index 40deb11..7e0cb4f 100644 --- a/arch/mips/rb532/gpio.c +++ b/arch/mips/rb532/gpio.c @@ -93,7 +93,7 @@ void set_latch_u5(unsigned char or_mask, unsigned char nand_mask) spin_lock_irqsave(&dev3.lock, flags); dev3.state = (dev3.state | or_mask) & ~nand_mask; - writel(dev3.state, &dev3.base); + writeb(dev3.state, dev3.base); spin_unlock_irqrestore(&dev3.lock, flags); } -- 1.5.6.4 From n0-1@nwl.cc Mon Jan 19 22:44:08 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 19 Jan 2009 22:44:10 +0000 (GMT) Received: from orbit.nwl.cc ([91.121.169.95]:60641 "EHLO mail.nwl.cc") by ftp.linux-mips.org with ESMTP id S21366188AbZASWnW (ORCPT ); Mon, 19 Jan 2009 22:43:22 +0000 Received: from base (localhost [127.0.0.1]) by mail.nwl.cc (Postfix) with ESMTP id C4A6B400E106; Mon, 19 Jan 2009 23:43:16 +0100 (CET) From: Phil Sutter To: Linux-Mips List Cc: ralf@linux-mips.org, florian@openwrt.org Subject: [PATCH 4/5] MIPS: rb532: remove {get,set}_434_reg() Date: Mon, 19 Jan 2009 23:42:53 +0100 X-Mailer: git-send-email 1.5.6.4 In-Reply-To: <1232404974-18497-3-git-send-email-n0-1@freewrt.org> References: <1232404974-18497-1-git-send-email-n0-1@freewrt.org> <1232404974-18497-2-git-send-email-n0-1@freewrt.org> <1232404974-18497-3-git-send-email-n0-1@freewrt.org> Message-Id: <20090119224316.C4A6B400E106@mail.nwl.cc> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21781 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: n0-1@freewrt.org Precedence: bulk X-list: linux-mips Content-Length: 1213 Lines: 49 These kernel symbols are unused. Also, since dev3 init has been moved to devices.c, set_434_reg() breaks compiling as it uses dev3. Signed-off-by: Phil Sutter --- arch/mips/rb532/gpio.c | 27 --------------------------- 1 files changed, 0 insertions(+), 27 deletions(-) diff --git a/arch/mips/rb532/gpio.c b/arch/mips/rb532/gpio.c index b9cb428..a916ac8 100644 --- a/arch/mips/rb532/gpio.c +++ b/arch/mips/rb532/gpio.c @@ -50,33 +50,6 @@ static struct resource rb532_gpio_reg0_res[] = { } }; -void set_434_reg(unsigned reg_offs, unsigned bit, unsigned len, unsigned val) -{ - unsigned long flags; - unsigned data; - unsigned i = 0; - - spin_lock_irqsave(&dev3.lock, flags); - - data = readl(IDT434_REG_BASE + reg_offs); - for (i = 0; i != len; ++i) { - if (val & (1 << i)) - data |= (1 << (i + bit)); - else - data &= ~(1 << (i + bit)); - } - writel(data, (IDT434_REG_BASE + reg_offs)); - - spin_unlock_irqrestore(&dev3.lock, flags); -} -EXPORT_SYMBOL(set_434_reg); - -unsigned get_434_reg(unsigned reg_offs) -{ - return readl(IDT434_REG_BASE + reg_offs); -} -EXPORT_SYMBOL(get_434_reg); - /* rb532_set_bit - sanely set a bit * * bitval: new value for the bit -- 1.5.6.4 From n0-1@nwl.cc Mon Jan 19 22:44:27 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 19 Jan 2009 22:44:29 +0000 (GMT) Received: from orbit.nwl.cc ([91.121.169.95]:61409 "EHLO mail.nwl.cc") by ftp.linux-mips.org with ESMTP id S21366189AbZASWnh (ORCPT ); Mon, 19 Jan 2009 22:43:37 +0000 Received: from base (localhost [127.0.0.1]) by mail.nwl.cc (Postfix) with ESMTP id C9AB7400E106; Mon, 19 Jan 2009 23:43:31 +0100 (CET) From: Phil Sutter To: Linux-Mips List Cc: ralf@linux-mips.org, florian@openwrt.org Subject: [PATCH 1/5] MIPS: rb532: fix init of rb532_dev3_ctl_res Date: Mon, 19 Jan 2009 23:42:50 +0100 X-Mailer: git-send-email 1.5.6.4 Message-Id: <20090119224331.C9AB7400E106@mail.nwl.cc> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21782 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: n0-1@freewrt.org Precedence: bulk X-list: linux-mips Content-Length: 1059 Lines: 34 This register just contains the address of the actual resource, so initialisation has to be the same as cf_slot0_res and nand_slot0_res. Signed-off-by: Phil Sutter --- arch/mips/rb532/gpio.c | 5 +++-- 1 files changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/mips/rb532/gpio.c b/arch/mips/rb532/gpio.c index d75eb19..40deb11 100644 --- a/arch/mips/rb532/gpio.c +++ b/arch/mips/rb532/gpio.c @@ -55,8 +55,6 @@ static struct resource rb532_gpio_reg0_res[] = { static struct resource rb532_dev3_ctl_res[] = { { .name = "dev3_ctl", - .start = REGBASE + DEV3BASE, - .end = REGBASE + DEV3BASE + sizeof(struct dev_reg) - 1, .flags = IORESOURCE_MEM, } }; @@ -243,6 +241,9 @@ int __init rb532_gpio_init(void) /* Register our GPIO chip */ gpiochip_add(&rb532_gpio_chip->chip); + rb532_dev3_ctl_res[0].start = readl(IDT434_REG_BASE + DEV3BASE); + rb532_dev3_ctl_res[0].end = rb532_dev3_ctl_res[0].start + 0x1000; + r = rb532_dev3_ctl_res; dev3.base = ioremap_nocache(r->start, r->end - r->start); -- 1.5.6.4 From mcdonald.shane@gmail.com Tue Jan 20 03:39:49 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 20 Jan 2009 03:39:52 +0000 (GMT) Received: from el-out-1112.google.com ([209.85.162.180]:23469 "EHLO el-out-1112.google.com") by ftp.linux-mips.org with ESMTP id S21365093AbZATDjt (ORCPT ); Tue, 20 Jan 2009 03:39:49 +0000 Received: by el-out-1112.google.com with SMTP id o28so856880ele.7 for ; Mon, 19 Jan 2009 19:39:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:received:to:subject:cc :message-id:from:date; bh=NURPsoG8Zmxtuf5W5nQudBA7vRsKrz+2RyHjDPqXk00=; b=oAq7cuuKW241vAlOewkGnFqUlS0V9Ez24DP7f5joqd7Mjv9h8Cr2PHzucWDIjf67N7 qVG05SfBK9k4t9l/4AJRXJUf4RUOScFL/ZvZ1Quc1GZmwHq1G4Ayvv06DXCh7u20kTPz xQkcGmlisa5gZGDEyWzWgPIsyAvrQ98fWaeck= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=to:subject:cc:message-id:from:date; b=wQzfjhFOp+pbrD0XZ+flE20jgXvWQJ/nruG3aMgx1C+bhItUh4UeSXqXlZx8VD35Is qERuNrp4QWXKQJJidnweVrL0GHjOAybQdoBOWME2PAmpRoBQJ7Ot+ZEljayHwyAUo8Hi J7hFFt2L7Z+H6ykVahUYIXWKJE6P1b0zh2oAA= Received: by 10.64.232.9 with SMTP id e9mr3106381qbh.13.1232422787534; Mon, 19 Jan 2009 19:39:47 -0800 (PST) Received: from localhost (207-47-250-91.sktn.hsdb.sasknet.sk.ca [207.47.250.91]) by mx.google.com with ESMTPS id 25sm11438415qbw.23.2009.01.19.19.39.45 (version=TLSv1/SSLv3 cipher=RC4-MD5); Mon, 19 Jan 2009 19:39:46 -0800 (PST) Received: from shane by localhost with local (Exim 4.63) (envelope-from ) id 1LP7Sp-0000fM-IR; Mon, 19 Jan 2009 21:39:43 -0600 To: linux-mips@linux-mips.org Subject: Panic on boot on RM7035C-based board with 2.6.29-rc2 Cc: ralf@linux-mips.org Message-Id: From: Shane McDonald Date: Mon, 19 Jan 2009 21:39:43 -0600 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21783 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mcdonald.shane@gmail.com Precedence: bulk X-list: linux-mips Content-Length: 12984 Lines: 362 This past weekend, I updated my RM7035C-based board to 2.6.29-rc2, and it now panics on boot. It ran fine on 2.6.29-rc1. My board is a PMC-Sierra Xiao Hu thin-client board (http://www.linuxjournal.com/article/7854). This board is not currently supported in the mainline kernel, although I am slowly trying to clean up the code to submit it for inclusion. This board is based on the ITE 8172 eval board, which was supported in kernels up to and including 2.6.18. The Xiao Hu board also serves as the base of the Linksys NSS4000 NAS device. My code was originally based on the NSS4000 2.6.18-based BSP available on the Linksys website, but has been stripped down and slightly cleaned up. After running a git bisect, I found the panic was introduced in commit a29b1ad4f45ce0db1d6ece289f334fe9528ae47b, MIPS: Avoid destructive invalidation on partial cachelines. Reversing the patch on 2.6.29-rc2 clears up the problem. I'm not quite sure how to proceed with this, or if there's a patch required to arch/mips/mm/c-r4k.c. Any insights would be appreciated. I have included the output of my boot up to the point of the panic. I have also attached the start of my config, hopefully including all relevant parts. I thank you for any assistance I receive! Shane McDonald -- Board reset!..............rl0: address is 00:e0:04:00:20:ab PMON version 1.2.3 [PMC,EL,FP,NET] Algorithmics Ltd. Aug 8 2005 19:05:58 This is free software, and comes with ABSOLUTELY NO WARRANTY, you are welcome to redistribute it without restriction. CPLD id FFFFh, type FFh, ver FFh Flash mfg 01h, id 7E2301h CPU type RM7065. Rev 5.3. 600 MHz/100 MHz. Memory size 128 MB. Icache size 16 KB, 32/line (4 way) Dcache size 16 KB, 32/line (4 way) Scache size 256 KB, 32/line (4 way) PMON> boot 192.168.0.105:/shane/vmlinux-attempt29rc2 Loading file: 192.168.0.105:/shane/vmlinux-attempt29rc2 (elf) 0x80100000/5345172 + 0x80618f94/120892 Entry address is 801043e0 PMON> g -- root=/dev/hda1 cca=3 Linux version 2.6.29-rc2-attempt-1 (shane@xiaohu) (gcc version 4.1.2 20061115 (prerelease) (Debian 4.1.1-21)) #1 Sun Jan 18 08:26:04 CST 2009 memsize: 128 Memory size: 128MB CPU revision is: 00002753 (RM7000) FPU revision is: 00002750 Determined physical RAM map: memory: 08000000 @ 00000000 (usable) Zone PFN ranges: DMA 0x00000000 -> 0x00001000 Normal 0x00001000 -> 0x00008000 Movable zone start PFN for each node early_node_map[1] active PFN ranges 0: 0x00000000 -> 0x00008000 Built 1 zonelists in Zone order, mobility grouping on. Total pages: 32512 Kernel command line: mtdparts=phys_mapped_flash:128k(bootenv),11264k(linux),2048k(linuxrtconfig),-(rootfs) jffs2_orphaned_inodes=delete root=/dev/hda1 cca=3 console=ttyS0,115200 Primary instruction cache 16kB, VIPT, 4-way, linesize 32 bytes. Primary data cache 16kB, 4-way, VIPT, no aliases, linesize 32 bytes Secondary cache size 256K, linesize 32 bytes. PID hash table entries: 512 (order: 9, 2048 bytes) calculating r4koff... 00124f7f(1199999) CPU frequency 600.00 MHz Dentry cache hash table entries: 16384 (order: 4, 65536 bytes) Inode-cache hash table entries: 8192 (order: 3, 32768 bytes) Memory: 123400k/131072k available (4067k kernel code, 7492k reserved, 997k data, 152k init, 0k highmem) Calibrating delay loop... 598.01 BogoMIPS (lpj=1196032) Mount-cache hash table entries: 512 net_namespace: 672 bytes xor: measuring software checksum speed 8regs : 565.000 MB/sec 8regs_prefetch: 504.000 MB/sec 32regs : 716.000 MB/sec 32regs_prefetch: 621.000 MB/sec xor: using function: 32regs (716.000 MB/sec) NET: Registered protocol family 16 registering PCI controller with io_map_base unset bio: create slab at 0 SCSI subsystem initialized usbcore: registered new interface driver usbfs usbcore: registered new interface driver hub usbcore: registered new device driver usb it8172 fixup: Resetting IDE adapter 0000:00:01.5 pci 0000:00:13.0: PME# supported from D1 D3hot pci 0000:00:13.0: PME# disabled pci 0000:00:13.1: PME# supported from D1 D3hot pci 0000:00:13.1: PME# disabled pci 0000:00:13.2: PME# supported from D0 D1 D2 D3hot D3cold pci 0000:00:13.2: PME# disabled NET: Registered protocol family 2 IP route cache hash table entries: 1024 (order: 0, 4096 bytes) TCP established hash table entries: 4096 (order: 3, 32768 bytes) TCP bind hash table entries: 4096 (order: 2, 16384 bytes) TCP: Hash tables configured (established 4096 bind 4096) TCP reno registered NET: Registered protocol family 1 VFS: Disk quotas dquot_6.5.2 Dquot-cache hash table entries: 1024 (order 0, 4096 bytes) Installing knfsd (copyright (C) 1996 okir@monad.swb.de). NTFS driver 2.1.29 [Flags: R/O]. SGI XFS with ACLs, security attributes, large block/inode numbers, no debug enabled SGI XFS Quota Management subsystem msgmni has been set to 241 alg: No test for stdrng (krng) async_tx: api initialized (sync-only) io scheduler noop registered io scheduler anticipatory registered io scheduler deadline registered io scheduler cfq registered (default) it8172 fixup: Configuring IDE adapter 0000:00:01.5 Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled serial8250.0: ttyS0 at I/O 0x14011800 (irq = 23) is a 16550A console [ttyS0] enabled loop: module loaded 8139too Fast Ethernet driver 0.9.28 eth0: RealTek RTL8139 at 0xb0105000, 00:e0:04:00:20:ab, IRQ 39 tun: Universal TUN/TAP device driver, 1.6 tun: (C) 1999-2004 Max Krasnyansky Uniform Multi-Platform E-IDE driver IT8172 0000:00:01.5: IDE controller (0x1283:0x8172 rev 0x01) IT8172 0000:00:01.5: 100% native mode on irq 34 ide0: BM-DMA at 0x14018cc0-0x14018cc7 hda: Maxtor 5T030H3, ATA DISK drive hda: UDMA/33 mode selected ide0 at 0x140179f0-0x140179f7,0x14017bf6 on irq 34 ide_generic: please use "probe_mask=0x3f" module parameter for probing all legacy ISA IDE ports ide_generic: I/O resource 0x1F0-0x1F7 not free. ide_generic: I/O resource 0x170-0x177 not free. ide-gd driver 1.18 hda: max request size: 128KiB hda: 60030432 sectors (30735 MB) w/2048KiB Cache, CHS=59554/16/63 hda: cache flushes not supported hda:Unhandled kernel unaligned access or invalid instruction[#1]: Cpu 0 $ 0 : 00000000 9004fc01 87975fff 00020000 $ 4 : 87975000 00001000 00000001 00000002 $ 8 : 00000001 00000000 00000008 0000c840 $12 : 3e007e00 00000020 8799a660 00000020 $16 : 87975000 00001000 00000002 00000000 $20 : 00000001 8798ec00 87985a00 878a1000 $24 : 00000000 803a068c $28 : 8781e000 8781fa18 00000000 801156b8 Hi : 0000012b Lo : 020f8000 epc : 801184bc r4k_dma_cache_inv+0xcc/0x12c Not tainted ra : 801156b8 dma_map_sg+0xbc/0x110 Status: 9004fc03 KERNEL EXL IE Cause : 00000010 BadVA : 87975fff PrId : 00002753 (RM7000) Process swapper (pid: 1, threadinfo=8781e000, task=8781da78, tls=00000000) Stack : 87985a00 878a1000 00000000 8039da7c 87975000 8781b000 801156b8 878bb400 87985a00 803a87e8 00000000 805e5220 a7984000 878a1000 00000002 878a1000 00000000 803a8bc4 00000000 87985a00 8799b5f4 8798a980 00000008 87985a00 00000002 878a1000 8798ec00 00000001 803a8df0 8799b5f4 8799b5f4 80354f88 00001000 00000000 8798ec00 878a1000 8781fb00 8051af40 8051b230 803a5184 ... Call Trace: [<801184bc>] r4k_dma_cache_inv+0xcc/0x12c [<801156b8>] dma_map_sg+0xbc/0x110 [<803a8bc4>] ide_build_dmatable+0x3c/0x184 [<803a8df0>] ide_dma_setup+0x44/0x104 [<803a5184>] do_rw_taskfile+0x254/0x2a0 [<803ac4f8>] ide_do_rw_disk+0x29c/0x320 [<8039e95c>] do_ide_request+0x5c4/0x934 [<80349140>] generic_unplug_device+0x3c/0x64 [<8015bc88>] sync_page+0x58/0x70 [<8010a9d8>] __wait_on_bit_lock+0x7c/0x164 [<8015bbfc>] __lock_page+0x6c/0x80 [<8015c644>] read_cache_page_async+0x184/0x220 [<8015c6f4>] read_cache_page+0x14/0x74 [<801e573c>] read_dev_sector+0x44/0xbc [<801e6424>] msdos_partition+0x80/0x6f0 [<801e60f8>] rescan_partitions+0x184/0x400 [<801bd754>] __blkdev_get+0x258/0x31c [<801e5e9c>] register_disk+0xd4/0x160 [<8034f468>] add_disk+0xf0/0x154 [<803aaf44>] ide_gd_probe+0x148/0x19c [<803918b4>] driver_probe_device+0x168/0x298 [<80391a54>] __driver_attach+0x70/0xa8 [<80390acc>] bus_for_each_dev+0x60/0xac [<80391190>] bus_add_driver+0xcc/0x254 [<80391ca8>] driver_register+0xb4/0x158 [<8010c9fc>] __kprobes_text_end+0x64/0x1e0 [<805f35f0>] kernel_init+0x8c/0xfc [<8010eb2c>] kernel_thread_helper+0x10/0x18 Code: bc950000 00851021 2442ffff 3c038062 90649157 00041823 00431024 02031824 Kernel panic - not syncing: Attempted to kill init! -- # # Automatically generated make config: don't edit # Linux kernel version: 2.6.29-rc2 # Sun Jan 18 07:14:02 2009 # CONFIG_MIPS=y # # Machine selection # CONFIG_ZONE_DMA=y # CONFIG_MACH_ALCHEMY is not set # CONFIG_BASLER_EXCITE is not set # CONFIG_BCM47XX is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set # CONFIG_LASAT is not set # CONFIG_LEMOTE_FULONG is not set # CONFIG_MIPS_MALTA is not set # CONFIG_MIPS_SIM is not set # CONFIG_MACH_EMMA is not set # CONFIG_MACH_VR41XX is not set # CONFIG_NXP_STB220 is not set # CONFIG_NXP_STB225 is not set # CONFIG_PNX8550_JBS is not set # CONFIG_PNX8550_STB810 is not set # CONFIG_PMC_MSP is not set CONFIG_PMC_XIAOHU=y # CONFIG_PMC_YOSEMITE is not set # CONFIG_SGI_IP22 is not set # CONFIG_SGI_IP27 is not set # CONFIG_SGI_IP28 is not set # CONFIG_SGI_IP32 is not set # CONFIG_SIBYTE_CRHINE is not set # CONFIG_SIBYTE_CARMEL is not set # CONFIG_SIBYTE_CRHONE is not set # CONFIG_SIBYTE_RHONE is not set # CONFIG_SIBYTE_SWARM is not set # CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_SENTOSA is not set # CONFIG_SIBYTE_BIGSUR is not set # CONFIG_SNI_RM is not set # CONFIG_MACH_TX39XX is not set # CONFIG_MACH_TX49XX is not set # CONFIG_MIKROTIK_RB532 is not set # CONFIG_WR_PPMC is not set # CONFIG_CAVIUM_OCTEON_SIMULATOR is not set # CONFIG_CAVIUM_OCTEON_REFERENCE_BOARD is not set CONFIG_RWSEM_GENERIC_SPINLOCK=y # CONFIG_ARCH_HAS_ILOG2_U32 is not set # CONFIG_ARCH_HAS_ILOG2_U64 is not set CONFIG_ARCH_SUPPORTS_OPROFILE=y CONFIG_GENERIC_FIND_NEXT_BIT=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_GENERIC_CLOCKEVENTS=y CONFIG_GENERIC_TIME=y CONFIG_GENERIC_CMOS_UPDATE=y CONFIG_SCHED_OMIT_FRAME_POINTER=y # CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ is not set CONFIG_CEVT_R4K_LIB=y CONFIG_CEVT_R4K=y CONFIG_CSRC_R4K_LIB=y CONFIG_CSRC_R4K=y CONFIG_DMA_NONCOHERENT=y CONFIG_DMA_NEED_PCI_MAP_STATE=y # CONFIG_HOTPLUG_CPU is not set # CONFIG_NO_IOPORT is not set CONFIG_GENERIC_ISA_DMA=y # CONFIG_CPU_BIG_ENDIAN is not set CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y CONFIG_IRQ_CPU=y CONFIG_MIPS_L1_CACHE_SHIFT=5 # # CPU selection # # CONFIG_CPU_LOONGSON2 is not set # CONFIG_CPU_MIPS32_R1 is not set # CONFIG_CPU_MIPS32_R2 is not set # CONFIG_CPU_MIPS64_R1 is not set # CONFIG_CPU_MIPS64_R2 is not set # CONFIG_CPU_R3000 is not set # CONFIG_CPU_TX39XX is not set # CONFIG_CPU_VR41XX is not set # CONFIG_CPU_R4300 is not set # CONFIG_CPU_R4X00 is not set # CONFIG_CPU_TX49XX is not set # CONFIG_CPU_R5000 is not set # CONFIG_CPU_R5432 is not set # CONFIG_CPU_R5500 is not set # CONFIG_CPU_R6000 is not set # CONFIG_CPU_NEVADA is not set # CONFIG_CPU_R8000 is not set # CONFIG_CPU_R10000 is not set CONFIG_CPU_RM7000=y # CONFIG_CPU_RM9000 is not set # CONFIG_CPU_SB1 is not set # CONFIG_CPU_CAVIUM_OCTEON is not set CONFIG_SYS_HAS_CPU_RM7000=y CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y CONFIG_SYS_SUPPORTS_64BIT_KERNEL=y CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y CONFIG_CPU_SUPPORTS_64BIT_KERNEL=y # # Kernel type # CONFIG_32BIT=y # CONFIG_64BIT is not set CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_8KB is not set # CONFIG_PAGE_SIZE_16KB is not set # CONFIG_PAGE_SIZE_64KB is not set CONFIG_BOARD_SCACHE=y CONFIG_RM7000_CPU_SCACHE=y CONFIG_CPU_HAS_PREFETCH=y CONFIG_MIPS_MT_DISABLED=y # CONFIG_MIPS_MT_SMP is not set # CONFIG_MIPS_MT_SMTC is not set CONFIG_CPU_HAS_LLSC=y CONFIG_CPU_HAS_SYNC=y CONFIG_GENERIC_HARDIRQS=y CONFIG_GENERIC_IRQ_PROBE=y CONFIG_CPU_SUPPORTS_HIGHMEM=y CONFIG_ARCH_FLATMEM_ENABLE=y CONFIG_ARCH_POPULATES_NODE_MAP=y CONFIG_SELECT_MEMORY_MODEL=y CONFIG_FLATMEM_MANUAL=y # CONFIG_DISCONTIGMEM_MANUAL is not set # CONFIG_SPARSEMEM_MANUAL is not set CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 # CONFIG_PHYS_ADDR_T_64BIT is not set CONFIG_ZONE_DMA_FLAG=1 CONFIG_BOUNCE=y CONFIG_VIRT_TO_BUS=y CONFIG_UNEVICTABLE_LRU=y # CONFIG_NO_HZ is not set # CONFIG_HIGH_RES_TIMERS is not set CONFIG_GENERIC_CLOCKEVENTS_BUILD=y # CONFIG_HZ_48 is not set # CONFIG_HZ_100 is not set # CONFIG_HZ_128 is not set CONFIG_HZ_250=y # CONFIG_HZ_256 is not set # CONFIG_HZ_1000 is not set # CONFIG_HZ_1024 is not set CONFIG_SYS_SUPPORTS_ARBIT_HZ=y CONFIG_HZ=250 CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set # CONFIG_KEXEC is not set CONFIG_SECCOMP=y CONFIG_LOCKDEP_SUPPORT=y CONFIG_STACKTRACE_SUPPORT=y CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" From mano@roarinelk.homelinux.net Tue Jan 20 10:03:54 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 20 Jan 2009 10:03:56 +0000 (GMT) Received: from fnoeppeil36.netpark.at ([217.175.205.164]:7629 "EHLO roarinelk.homelinux.net") by ftp.linux-mips.org with ESMTP id S21366208AbZATKDy (ORCPT ); Tue, 20 Jan 2009 10:03:54 +0000 Received: (qmail 19003 invoked by uid 1000); 20 Jan 2009 11:03:53 +0100 Date: Tue, 20 Jan 2009 11:03:53 +0100 From: Manuel Lauss To: Ralf Baechle Cc: Linux-MIPS Subject: [PATCH] Alchemy: fix edge irq handling Message-ID: <20090120100353.GA18971@roarinelk.homelinux.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline User-Agent: Mutt/1.5.16 (2007-06-09) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21784 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mano@roarinelk.homelinux.net Precedence: bulk X-list: linux-mips Content-Length: 2644 Lines: 83 Introduce separate mack_ack callbacks which really do shut up the edge-triggered irqs when called. Without this change, high-frequency edge interrupts can result in an endless irq storm, hanging the system. This can be easily triggered for example by setting an irq to falling edge type and manually connecting the associated pin to ground. Signed-off-by: Manuel Lauss --- arch/mips/alchemy/common/irq.c | 32 ++++++++++++++++++++++++-------- 1 files changed, 24 insertions(+), 8 deletions(-) diff --git a/arch/mips/alchemy/common/irq.c b/arch/mips/alchemy/common/irq.c index c88c821..60da581 100644 --- a/arch/mips/alchemy/common/irq.c +++ b/arch/mips/alchemy/common/irq.c @@ -320,6 +320,16 @@ static void au1x_ic0_mask(unsigned int irq_nr) au_sync(); } +static void au1x_ic0_maskack(unsigned int irq_nr) +{ + unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE; + au_writel(1 << bit, IC0_MASKCLR); + au_writel(1 << bit, IC0_WAKECLR); + au_writel(1 << bit, IC0_FALLINGCLR); + au_writel(1 << bit, IC0_RISINGCLR); + au_sync(); +} + static void au1x_ic1_mask(unsigned int irq_nr) { unsigned int bit = irq_nr - AU1000_INTC1_INT_BASE; @@ -328,6 +338,16 @@ static void au1x_ic1_mask(unsigned int irq_nr) au_sync(); } +static void au1x_ic1_maskack(unsigned int irq_nr) +{ + unsigned int bit = irq_nr - AU1000_INTC1_INT_BASE; + au_writel(1 << bit, IC1_MASKCLR); + au_writel(1 << bit, IC1_WAKECLR); + au_writel(1 << bit, IC1_FALLINGCLR); + au_writel(1 << bit, IC1_RISINGCLR); + au_sync(); +} + static void au1x_ic0_ack(unsigned int irq_nr) { unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE; @@ -379,25 +399,21 @@ static int au1x_ic1_setwake(unsigned int irq, unsigned int on) /* * irq_chips for both ICs; this way the mask handlers can be * as short as possible. - * - * NOTE: the ->ack() callback is used by the handle_edge_irq - * flowhandler only, the ->mask_ack() one by handle_level_irq, - * so no need for an irq_chip for each type of irq (level/edge). */ static struct irq_chip au1x_ic0_chip = { .name = "Alchemy-IC0", - .ack = au1x_ic0_ack, /* edge */ + .ack = au1x_ic0_ack, .mask = au1x_ic0_mask, - .mask_ack = au1x_ic0_mask, /* level */ + .mask_ack = au1x_ic0_maskack, .unmask = au1x_ic0_unmask, .set_type = au1x_ic_settype, }; static struct irq_chip au1x_ic1_chip = { .name = "Alchemy-IC1", - .ack = au1x_ic1_ack, /* edge */ + .ack = au1x_ic1_ack, .mask = au1x_ic1_mask, - .mask_ack = au1x_ic1_mask, /* level */ + .mask_ack = au1x_ic1_maskack, .unmask = au1x_ic1_unmask, .set_type = au1x_ic_settype, .set_wake = au1x_ic1_setwake, -- 1.6.1 From anemo@mba.ocn.ne.jp Tue Jan 20 14:07:39 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 20 Jan 2009 14:07:42 +0000 (GMT) Received: from mba.ocn.ne.jp ([122.1.235.107]:13523 "HELO smtp.mba.ocn.ne.jp") by ftp.linux-mips.org with SMTP id S21365133AbZATOHj (ORCPT ); Tue, 20 Jan 2009 14:07:39 +0000 Received: from localhost.localdomain (p1210-ipad205funabasi.chiba.ocn.ne.jp [222.146.96.210]) by smtp.mba.ocn.ne.jp (Postfix) with ESMTP id 65E94A108; Tue, 20 Jan 2009 23:07:34 +0900 (JST) From: Atsushi Nemoto To: linux-mips@linux-mips.org Cc: ralf@linux-mips.org Subject: [PATCH] TXx9: Add support for TX4939 internal RTC Date: Tue, 20 Jan 2009 23:07:41 +0900 Message-Id: <1232460461-4325-1-git-send-email-anemo@mba.ocn.ne.jp> X-Mailer: git-send-email 1.5.6.3 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21785 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anemo@mba.ocn.ne.jp Precedence: bulk X-list: linux-mips Content-Length: 2003 Lines: 68 Add platform support to use rtc-tx4939 driver. Signed-off-by: Atsushi Nemoto --- arch/mips/include/asm/txx9/tx4939.h | 1 + arch/mips/txx9/generic/setup_tx4939.c | 22 ++++++++++++++++++++++ arch/mips/txx9/rbtx4939/setup.c | 1 + 3 files changed, 24 insertions(+), 0 deletions(-) diff --git a/arch/mips/include/asm/txx9/tx4939.h b/arch/mips/include/asm/txx9/tx4939.h index 88badb4..964ef7e 100644 --- a/arch/mips/include/asm/txx9/tx4939.h +++ b/arch/mips/include/asm/txx9/tx4939.h @@ -541,5 +541,6 @@ void tx4939_irq_init(void); int tx4939_irq(void); void tx4939_mtd_init(int ch); void tx4939_ata_init(void); +void tx4939_rtc_init(void); #endif /* __ASM_TXX9_TX4939_H */ diff --git a/arch/mips/txx9/generic/setup_tx4939.c b/arch/mips/txx9/generic/setup_tx4939.c index 6c0049a..5544096 100644 --- a/arch/mips/txx9/generic/setup_tx4939.c +++ b/arch/mips/txx9/generic/setup_tx4939.c @@ -435,6 +435,28 @@ void __init tx4939_ata_init(void) platform_device_register(&ata1_dev); } +void __init tx4939_rtc_init(void) +{ + static struct resource res[] = { + { + .start = TX4939_RTC_REG & 0xfffffffffULL, + .end = (TX4939_RTC_REG & 0xfffffffffULL) + 0x100 - 1, + .flags = IORESOURCE_MEM, + }, { + .start = TXX9_IRQ_BASE + TX4939_IR_RTC, + .flags = IORESOURCE_IRQ, + }, + }; + static struct platform_device rtc_dev = { + .name = "tx4939rtc", + .id = -1, + .num_resources = ARRAY_SIZE(res), + .resource = res, + }; + + platform_device_register(&rtc_dev); +} + static void __init tx4939_stop_unused_modules(void) { __u64 pcfg, rst = 0, ckd = 0; diff --git a/arch/mips/txx9/rbtx4939/setup.c b/arch/mips/txx9/rbtx4939/setup.c index 98fbd93..656603b 100644 --- a/arch/mips/txx9/rbtx4939/setup.c +++ b/arch/mips/txx9/rbtx4939/setup.c @@ -336,6 +336,7 @@ static void __init rbtx4939_device_init(void) rbtx4939_led_setup(); tx4939_wdt_init(); tx4939_ata_init(); + tx4939_rtc_init(); } static void __init rbtx4939_setup(void) -- 1.5.6.3 From anemo@mba.ocn.ne.jp Tue Jan 20 14:12:17 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 20 Jan 2009 14:12:20 +0000 (GMT) Received: from mba.ocn.ne.jp ([122.1.235.107]:29921 "HELO smtp.mba.ocn.ne.jp") by ftp.linux-mips.org with SMTP id S21366218AbZATOMR (ORCPT ); Tue, 20 Jan 2009 14:12:17 +0000 Received: from localhost.localdomain (p1210-ipad205funabasi.chiba.ocn.ne.jp [222.146.96.210]) by smtp.mba.ocn.ne.jp (Postfix) with ESMTP id 9CE15AA85; Tue, 20 Jan 2009 23:12:12 +0900 (JST) From: Atsushi Nemoto To: linux-mips@linux-mips.org Cc: ralf@linux-mips.org, linux-mtd@lists.infradead.org, dwmw2@infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/5] RBTX4939: Add MTD support Date: Tue, 20 Jan 2009 23:12:16 +0900 Message-Id: <1232460738-4714-2-git-send-email-anemo@mba.ocn.ne.jp> X-Mailer: git-send-email 1.5.6.3 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21786 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anemo@mba.ocn.ne.jp Precedence: bulk X-list: linux-mips Content-Length: 5883 Lines: 212 Add platform support for NOR flash chips on RBTX4939 board. This board has complex flash mappings, controlled by its DIPSW setting. Signed-off-by: Atsushi Nemoto --- arch/mips/include/asm/txx9/rbtx4939.h | 9 ++ arch/mips/txx9/rbtx4939/setup.c | 157 +++++++++++++++++++++++++++++++++ 2 files changed, 166 insertions(+), 0 deletions(-) diff --git a/arch/mips/include/asm/txx9/rbtx4939.h b/arch/mips/include/asm/txx9/rbtx4939.h index 1acf428..e517899 100644 --- a/arch/mips/include/asm/txx9/rbtx4939.h +++ b/arch/mips/include/asm/txx9/rbtx4939.h @@ -130,4 +130,13 @@ void rbtx4939_prom_init(void); void rbtx4939_irq_setup(void); +struct mtd_partition; +struct map_info; +struct rbtx4939_flash_data { + unsigned int width; + unsigned int nr_parts; + struct mtd_partition *parts; + void (*map_init)(struct map_info *map); +}; + #endif /* __ASM_TXX9_RBTX4939_H */ diff --git a/arch/mips/txx9/rbtx4939/setup.c b/arch/mips/txx9/rbtx4939/setup.c index 74839f2..eee8763 100644 --- a/arch/mips/txx9/rbtx4939/setup.c +++ b/arch/mips/txx9/rbtx4939/setup.c @@ -16,6 +16,9 @@ #include #include #include +#include +#include +#include #include #include #include @@ -282,6 +285,159 @@ static void rbtx4939_7segled_putc(unsigned int pos, unsigned char val) __rbtx4939_7segled_putc(pos, val); } +#if defined(CONFIG_MTD_RBTX4939) || defined(CONFIG_MTD_RBTX4939_MODULE) +/* special mapping for boot rom */ +static unsigned long rbtx4939_flash_fixup_ofs(unsigned long ofs) +{ + u8 bdipsw = readb(rbtx4939_bdipsw_addr) & 0x0f; + unsigned char shift; + + if (bdipsw & 8) { + /* BOOT Mode: USER ROM1 / USER ROM2 */ + shift = bdipsw & 3; + /* rotate A[23:22] */ + return (ofs & ~0xc00000) | ((((ofs >> 22) + shift) & 3) << 22); + } +#ifdef __BIG_ENDIAN + if (bdipsw == 0) + /* BOOT Mode: Monitor ROM */ + ofs ^= 0x400000; /* swap A[22] */ +#endif + return ofs; +} + +static map_word rbtx4939_flash_read16(struct map_info *map, unsigned long ofs) +{ + map_word r; + + ofs = rbtx4939_flash_fixup_ofs(ofs); + r.x[0] = __raw_readw(map->virt + ofs); + return r; +} + +static void rbtx4939_flash_write16(struct map_info *map, const map_word datum, + unsigned long ofs) +{ + ofs = rbtx4939_flash_fixup_ofs(ofs); + __raw_writew(datum.x[0], map->virt + ofs); + mb(); /* see inline_map_write() in mtd/map.h */ +} + +static void rbtx4939_flash_copy_from(struct map_info *map, void *to, + unsigned long from, ssize_t len) +{ + u8 bdipsw = readb(rbtx4939_bdipsw_addr) & 0x0f; + unsigned char shift; + ssize_t curlen; + + from += (unsigned long)map->virt; + if (bdipsw & 8) { + /* BOOT Mode: USER ROM1 / USER ROM2 */ + shift = bdipsw & 3; + while (len) { + curlen = min((unsigned long)len, + 0x400000 - (from & (0x400000 - 1))); + memcpy(to, + (void *)((from & ~0xc00000) | + ((((from >> 22) + shift) & 3) << 22)), + curlen); + len -= curlen; + from += curlen; + to += curlen; + } + return; + } +#ifdef __BIG_ENDIAN + if (bdipsw == 0) { + /* BOOT Mode: Monitor ROM */ + while (len) { + curlen = min((unsigned long)len, + 0x400000 - (from & (0x400000 - 1))); + memcpy(to, (void *)(from ^ 0x400000), curlen); + len -= curlen; + from += curlen; + to += curlen; + } + return; + } +#endif + memcpy(to, (void *)from, len); +} + +static void rbtx4939_flash_map_init(struct map_info *map) +{ + map->read = rbtx4939_flash_read16; + map->write = rbtx4939_flash_write16; + map->copy_from = rbtx4939_flash_copy_from; +} + +static void __init rbtx4939_mtd_init(void) +{ + static struct { + struct platform_device dev; + struct resource res; + struct rbtx4939_flash_data data; + } pdevs[4]; + int i; + static char names[4][8]; + static struct mtd_partition parts[4]; + struct rbtx4939_flash_data *boot_pdata = &pdevs[0].data; + u8 bdipsw = readb(rbtx4939_bdipsw_addr) & 0x0f; + + if (bdipsw & 8) { + /* BOOT Mode: USER ROM1 / USER ROM2 */ + boot_pdata->nr_parts = 4; + for (i = 0; i < boot_pdata->nr_parts; i++) { + sprintf(names[i], "img%d", 4 - i); + parts[i].name = names[i]; + parts[i].size = 0x400000; + parts[i].offset = MTDPART_OFS_NXTBLK; + } + } else if (bdipsw == 0) { + /* BOOT Mode: Monitor ROM */ + boot_pdata->nr_parts = 2; + strcpy(names[0], "big"); + strcpy(names[1], "little"); + for (i = 0; i < boot_pdata->nr_parts; i++) { + parts[i].name = names[i]; + parts[i].size = 0x400000; + parts[i].offset = MTDPART_OFS_NXTBLK; + } + } else { + /* BOOT Mode: ROM Emulator */ + boot_pdata->nr_parts = 2; + parts[0].name = "boot"; + parts[0].offset = 0xc00000; + parts[0].size = 0x400000; + parts[1].name = "user"; + parts[1].offset = 0; + parts[1].size = 0xc00000; + } + boot_pdata->parts = parts; + boot_pdata->map_init = rbtx4939_flash_map_init; + + for (i = 0; i < ARRAY_SIZE(pdevs); i++) { + struct resource *r = &pdevs[i].res; + struct platform_device *dev = &pdevs[i].dev; + + r->start = 0x1f000000 - i * 0x1000000; + r->end = r->start + 0x1000000 - 1; + r->flags = IORESOURCE_MEM; + pdevs[i].data.width = 2; + dev->num_resources = 1; + dev->resource = r; + dev->id = i; + dev->name = "rbtx4939-flash"; + dev->dev.platform_data = &pdevs[i].data; + platform_device_register(dev); + } +} +#else +static void __init rbtx4939_mtd_init(void) +{ +} +#endif + static void __init rbtx4939_arch_init(void) { rbtx4939_pci_setup(); @@ -333,6 +489,7 @@ static void __init rbtx4939_device_init(void) platform_device_add_data(pdev, &smc_pdata, sizeof(smc_pdata)) || platform_device_add(pdev)) platform_device_put(pdev); + rbtx4939_mtd_init(); /* TC58DVM82A1FT: tDH=10ns, tWP=tRP=tREADID=35ns */ tx4939_ndfmc_init(10, 35, (1 << 1) | (1 << 2), -- 1.5.6.3 From anemo@mba.ocn.ne.jp Tue Jan 20 14:12:37 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 20 Jan 2009 14:12:41 +0000 (GMT) Received: from mba.ocn.ne.jp ([122.1.235.107]:37345 "HELO smtp.mba.ocn.ne.jp") by ftp.linux-mips.org with SMTP id S21366219AbZATOMR (ORCPT ); Tue, 20 Jan 2009 14:12:17 +0000 Received: from localhost.localdomain (p1210-ipad205funabasi.chiba.ocn.ne.jp [222.146.96.210]) by smtp.mba.ocn.ne.jp (Postfix) with ESMTP id 2456DA99F; Tue, 20 Jan 2009 23:12:13 +0900 (JST) From: Atsushi Nemoto To: linux-mips@linux-mips.org Cc: ralf@linux-mips.org, linux-mtd@lists.infradead.org, dwmw2@infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 3/5] MTD: TXx9 SoC NAND Flash Memory Controller driver (v2) Date: Tue, 20 Jan 2009 23:12:17 +0900 Message-Id: <1232460738-4714-3-git-send-email-anemo@mba.ocn.ne.jp> X-Mailer: git-send-email 1.5.6.3 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21787 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anemo@mba.ocn.ne.jp Precedence: bulk X-list: linux-mips Content-Length: 13798 Lines: 477 This patch adds support for the integrated NAND flash controller of the TXx9 family. Once upon a time there were tx4925ndfmc and tx4938ndfmc driver. They were removed due to bitrot in 2005. This new driver is completely rewritten based on a driver in CELF patch archive. Signed-off-by: Atsushi Nemoto --- drivers/mtd/nand/Kconfig | 6 + drivers/mtd/nand/Makefile | 1 + drivers/mtd/nand/txx9ndfmc.c | 426 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 433 insertions(+), 0 deletions(-) create mode 100644 drivers/mtd/nand/txx9ndfmc.c diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig index 8b12e6e..e43c9b0 100644 --- a/drivers/mtd/nand/Kconfig +++ b/drivers/mtd/nand/Kconfig @@ -427,4 +427,10 @@ config MTD_NAND_SH_FLCTL Several Renesas SuperH CPU has FLCTL. This option enables support for NAND Flash using FLCTL. This driver support SH7723. +config MTD_NAND_TXX9NDFMC + tristate "NAND Flash support for TXx9 SoC" + depends on SOC_TX4938 || SOC_TX4939 + help + This enables the NAND flash controller on the TXx9 SoCs. + endif # MTD_NAND diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile index b661586..aec0352 100644 --- a/drivers/mtd/nand/Makefile +++ b/drivers/mtd/nand/Makefile @@ -36,5 +36,6 @@ obj-$(CONFIG_MTD_NAND_FSL_ELBC) += fsl_elbc_nand.o obj-$(CONFIG_MTD_NAND_FSL_UPM) += fsl_upm.o obj-$(CONFIG_MTD_NAND_SH_FLCTL) += sh_flctl.o obj-$(CONFIG_MTD_NAND_MXC) += mxc_nand.o +obj-$(CONFIG_MTD_NAND_TXX9NDFMC) += txx9ndfmc.o nand-objs := nand_base.o nand_bbt.o diff --git a/drivers/mtd/nand/txx9ndfmc.c b/drivers/mtd/nand/txx9ndfmc.c new file mode 100644 index 0000000..4c5c847 --- /dev/null +++ b/drivers/mtd/nand/txx9ndfmc.c @@ -0,0 +1,426 @@ +/* + * TXx9 NAND flash memory controller driver + * Based on RBTX49xx patch from CELF patch archive. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * (C) Copyright TOSHIBA CORPORATION 2004-2007 + * All Rights Reserved. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* TXX9 NDFMC Registers */ +#define TXX9_NDFDTR 0x00 +#define TXX9_NDFMCR 0x04 +#define TXX9_NDFSR 0x08 +#define TXX9_NDFISR 0x0c +#define TXX9_NDFIMR 0x10 +#define TXX9_NDFSPR 0x14 +#define TXX9_NDFRSTR 0x18 /* not TX4939 */ + +/* NDFMCR : NDFMC Mode Control */ +#define TXX9_NDFMCR_WE 0x80 +#define TXX9_NDFMCR_ECC_ALL 0x60 +#define TXX9_NDFMCR_ECC_RESET 0x60 +#define TXX9_NDFMCR_ECC_READ 0x40 +#define TXX9_NDFMCR_ECC_ON 0x20 +#define TXX9_NDFMCR_ECC_OFF 0x00 +#define TXX9_NDFMCR_CE 0x10 +#define TXX9_NDFMCR_BSPRT 0x04 /* TX4925/TX4926 only */ +#define TXX9_NDFMCR_ALE 0x02 +#define TXX9_NDFMCR_CLE 0x01 +/* TX4939 only */ +#define TXX9_NDFMCR_X16 0x0400 +#define TXX9_NDFMCR_DMAREQ_MASK 0x0300 +#define TXX9_NDFMCR_DMAREQ_NODMA 0x0000 +#define TXX9_NDFMCR_DMAREQ_128 0x0100 +#define TXX9_NDFMCR_DMAREQ_256 0x0200 +#define TXX9_NDFMCR_DMAREQ_512 0x0300 +#define TXX9_NDFMCR_CS_MASK 0x0c +#define TXX9_NDFMCR_CS(ch) ((ch) << 2) + +/* NDFMCR : NDFMC Status */ +#define TXX9_NDFSR_BUSY 0x80 +/* TX4939 only */ +#define TXX9_NDFSR_DMARUN 0x40 + +/* NDFMCR : NDFMC Reset */ +#define TXX9_NDFRSTR_RST 0x01 + +struct txx9ndfmc_priv { + struct platform_device *dev; + struct nand_chip chip; + struct mtd_info mtd; + int cs; + char mtdname[BUS_ID_SIZE + 2]; +}; + +#define MAX_TXX9NDFMC_DEV 4 +struct txx9ndfmc_drvdata { + struct mtd_info *mtds[MAX_TXX9NDFMC_DEV]; + void __iomem *base; + unsigned char hold; /* in gbusclock */ + unsigned char spw; /* in gbusclock */ + struct nand_hw_control hw_control; +}; + +static struct platform_device *mtd_to_platdev(struct mtd_info *mtd) +{ + struct nand_chip *chip = mtd->priv; + struct txx9ndfmc_priv *txx9_priv = chip->priv; + return txx9_priv->dev; +} + +static void __iomem *ndregaddr(struct platform_device *dev, unsigned int reg) +{ + struct txx9ndfmc_drvdata *drvdata = platform_get_drvdata(dev); + struct txx9ndfmc_platform_data *plat = dev->dev.platform_data; + + return drvdata->base + (reg << plat->shift); +} + +static u32 txx9ndfmc_read(struct platform_device *dev, unsigned int reg) +{ + return __raw_readl(ndregaddr(dev, reg)); +} + +static void txx9ndfmc_write(struct platform_device *dev, + u32 val, unsigned int reg) +{ + __raw_writel(val, ndregaddr(dev, reg)); +} + +static uint8_t txx9ndfmc_read_byte(struct mtd_info *mtd) +{ + struct platform_device *dev = mtd_to_platdev(mtd); + + return txx9ndfmc_read(dev, TXX9_NDFDTR); +} + +static void txx9ndfmc_write_buf(struct mtd_info *mtd, const uint8_t *buf, + int len) +{ + struct platform_device *dev = mtd_to_platdev(mtd); + void __iomem *ndfdtr = ndregaddr(dev, TXX9_NDFDTR); + u32 mcr = txx9ndfmc_read(dev, TXX9_NDFMCR); + + txx9ndfmc_write(dev, mcr | TXX9_NDFMCR_WE, TXX9_NDFMCR); + while (len--) + __raw_writel(*buf++, ndfdtr); + txx9ndfmc_write(dev, mcr, TXX9_NDFMCR); +} + +static void txx9ndfmc_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) +{ + struct platform_device *dev = mtd_to_platdev(mtd); + void __iomem *ndfdtr = ndregaddr(dev, TXX9_NDFDTR); + + while (len--) + *buf++ = __raw_readl(ndfdtr); +} + +static int txx9ndfmc_verify_buf(struct mtd_info *mtd, const uint8_t *buf, + int len) +{ + struct platform_device *dev = mtd_to_platdev(mtd); + void __iomem *ndfdtr = ndregaddr(dev, TXX9_NDFDTR); + + while (len--) + if (*buf++ != (uint8_t)__raw_readl(ndfdtr)) + return -EFAULT; + return 0; +} + +static void txx9ndfmc_cmd_ctrl(struct mtd_info *mtd, int cmd, + unsigned int ctrl) +{ + struct nand_chip *chip = mtd->priv; + struct txx9ndfmc_priv *txx9_priv = chip->priv; + struct platform_device *dev = txx9_priv->dev; + struct txx9ndfmc_platform_data *plat = dev->dev.platform_data; + + if (ctrl & NAND_CTRL_CHANGE) { + u32 mcr = txx9ndfmc_read(dev, TXX9_NDFMCR); + + mcr &= ~(TXX9_NDFMCR_CLE | TXX9_NDFMCR_ALE | TXX9_NDFMCR_CE); + mcr |= ctrl & NAND_CLE ? TXX9_NDFMCR_CLE : 0; + mcr |= ctrl & NAND_ALE ? TXX9_NDFMCR_ALE : 0; + /* TXX9_NDFMCR_CE bit is 0:high 1:low */ + mcr |= ctrl & NAND_NCE ? TXX9_NDFMCR_CE : 0; + if (txx9_priv->cs >= 0 && (ctrl & NAND_NCE)) { + mcr &= ~TXX9_NDFMCR_CS_MASK; + mcr |= TXX9_NDFMCR_CS(txx9_priv->cs); + } + txx9ndfmc_write(dev, mcr, TXX9_NDFMCR); + } + if (cmd != NAND_CMD_NONE) + txx9ndfmc_write(dev, cmd & 0xff, TXX9_NDFDTR); + if (plat->flags & NDFMC_PLAT_FLAG_DUMMYWRITE) { + /* dummy write to update external latch */ + if ((ctrl & NAND_CTRL_CHANGE) && cmd == NAND_CMD_NONE) + txx9ndfmc_write(dev, 0, TXX9_NDFDTR); + } + mmiowb(); +} + +static int txx9ndfmc_dev_ready(struct mtd_info *mtd) +{ + struct platform_device *dev = mtd_to_platdev(mtd); + + return !(txx9ndfmc_read(dev, TXX9_NDFSR) & TXX9_NDFSR_BUSY); +} + +static int txx9ndfmc_calculate_ecc(struct mtd_info *mtd, const uint8_t *dat, + uint8_t *ecc_code) +{ + struct platform_device *dev = mtd_to_platdev(mtd); + u32 mcr = txx9ndfmc_read(dev, TXX9_NDFMCR); + + mcr &= ~TXX9_NDFMCR_ECC_ALL; + txx9ndfmc_write(dev, mcr | TXX9_NDFMCR_ECC_OFF, TXX9_NDFMCR); + txx9ndfmc_write(dev, mcr | TXX9_NDFMCR_ECC_READ, TXX9_NDFMCR); + ecc_code[1] = txx9ndfmc_read(dev, TXX9_NDFDTR); + ecc_code[0] = txx9ndfmc_read(dev, TXX9_NDFDTR); + ecc_code[2] = txx9ndfmc_read(dev, TXX9_NDFDTR); + txx9ndfmc_write(dev, mcr | TXX9_NDFMCR_ECC_OFF, TXX9_NDFMCR); + return 0; +} + +static void txx9ndfmc_enable_hwecc(struct mtd_info *mtd, int mode) +{ + struct platform_device *dev = mtd_to_platdev(mtd); + u32 mcr = txx9ndfmc_read(dev, TXX9_NDFMCR); + + mcr &= ~TXX9_NDFMCR_ECC_ALL; + txx9ndfmc_write(dev, mcr | TXX9_NDFMCR_ECC_RESET, TXX9_NDFMCR); + txx9ndfmc_write(dev, mcr | TXX9_NDFMCR_ECC_OFF, TXX9_NDFMCR); + txx9ndfmc_write(dev, mcr | TXX9_NDFMCR_ECC_ON, TXX9_NDFMCR); +} + +static void txx9ndfmc_initialize(struct platform_device *dev) +{ + struct txx9ndfmc_platform_data *plat = dev->dev.platform_data; + struct txx9ndfmc_drvdata *drvdata = platform_get_drvdata(dev); + int tmout = 100; + + if (plat->flags & NDFMC_PLAT_FLAG_NO_RSTR) + ; /* no NDFRSTR. Write to NDFSPR resets the NDFMC. */ + else { + /* reset NDFMC */ + txx9ndfmc_write(dev, + txx9ndfmc_read(dev, TXX9_NDFRSTR) | + TXX9_NDFRSTR_RST, + TXX9_NDFRSTR); + while (txx9ndfmc_read(dev, TXX9_NDFRSTR) & TXX9_NDFRSTR_RST) { + if (--tmout == 0) { + dev_err(&dev->dev, "reset failed.\n"); + break; + } + udelay(1); + } + } + /* setup Hold Time, Strobe Pulse Width */ + txx9ndfmc_write(dev, (drvdata->hold << 4) | drvdata->spw, TXX9_NDFSPR); + txx9ndfmc_write(dev, + (plat->flags & NDFMC_PLAT_FLAG_USE_BSPRT) ? + TXX9_NDFMCR_BSPRT : 0, TXX9_NDFMCR); +} + +#define TXX9NDFMC_NS_TO_CYC(gbusclk, ns) \ + DIV_ROUND_UP((ns) * DIV_ROUND_UP(gbusclk, 1000), 1000000) + +static int __init txx9ndfmc_probe(struct platform_device *dev) +{ + struct txx9ndfmc_platform_data *plat = dev->dev.platform_data; +#ifdef CONFIG_MTD_PARTITIONS + static const char *probes[] = { "cmdlinepart", NULL }; +#endif + int hold, spw; + int i; + struct txx9ndfmc_drvdata *drvdata; + unsigned long gbusclk = plat->gbus_clock; + struct resource *res; + + res = platform_get_resource(dev, IORESOURCE_MEM, 0); + if (!res) + return -ENODEV; + drvdata = devm_kzalloc(&dev->dev, sizeof(*drvdata), GFP_KERNEL); + if (!drvdata) + return -ENOMEM; + if (!devm_request_mem_region(&dev->dev, res->start, + resource_size(res), dev_name(&dev->dev))) + return -EBUSY; + drvdata->base = devm_ioremap(&dev->dev, res->start, + resource_size(res)); + if (!drvdata->base) + return -EBUSY; + + hold = plat->hold ?: 20; /* tDH */ + spw = plat->spw ?: 90; /* max(tREADID, tWP, tRP) */ + + hold = TXX9NDFMC_NS_TO_CYC(gbusclk, hold); + spw = TXX9NDFMC_NS_TO_CYC(gbusclk, spw); + if (plat->flags & NDFMC_PLAT_FLAG_HOLDADD) + hold -= 2; /* actual hold time : (HOLD + 2) BUSCLK */ + spw -= 1; /* actual wait time : (SPW + 1) BUSCLK */ + hold = clamp(hold, 1, 15); + drvdata->hold = hold; + spw = clamp(spw, 1, 15); + drvdata->spw = spw; + dev_info(&dev->dev, "CLK:%ldMHz HOLD:%d SPW:%d\n", + (gbusclk + 500000) / 1000000, hold, spw); + + spin_lock_init(&drvdata->hw_control.lock); + init_waitqueue_head(&drvdata->hw_control.wq); + + platform_set_drvdata(dev, drvdata); + txx9ndfmc_initialize(dev); + + for (i = 0; i < MAX_TXX9NDFMC_DEV; i++) { + struct txx9ndfmc_priv *txx9_priv; + struct nand_chip *chip; + struct mtd_info *mtd; +#ifdef CONFIG_MTD_PARTITIONS + int nr_parts; + struct mtd_partition *parts; +#endif + + if (!(plat->ch_mask & (1 << i))) + continue; + txx9_priv = kzalloc(sizeof(struct txx9ndfmc_priv), + GFP_KERNEL); + if (!txx9_priv) { + dev_err(&dev->dev, "Unable to allocate " + "TXx9 NDFMC MTD device structure.\n"); + continue; + } + chip = &txx9_priv->chip; + mtd = &txx9_priv->mtd; + mtd->owner = THIS_MODULE; + + mtd->priv = chip; + + chip->read_byte = txx9ndfmc_read_byte; + chip->read_buf = txx9ndfmc_read_buf; + chip->write_buf = txx9ndfmc_write_buf; + chip->verify_buf = txx9ndfmc_verify_buf; + chip->cmd_ctrl = txx9ndfmc_cmd_ctrl; + chip->dev_ready = txx9ndfmc_dev_ready; + chip->ecc.calculate = txx9ndfmc_calculate_ecc; + chip->ecc.correct = nand_correct_data; + chip->ecc.hwctl = txx9ndfmc_enable_hwecc; + chip->ecc.mode = NAND_ECC_HW; + chip->ecc.size = 256; + chip->ecc.bytes = 3; + chip->chip_delay = 100; + chip->controller = &drvdata->hw_control; + + chip->priv = txx9_priv; + txx9_priv->dev = dev; + + if (plat->ch_mask != 1) { + txx9_priv->cs = i; + sprintf(txx9_priv->mtdname, "%s:%u", + dev_name(&dev->dev), i); + } else { + txx9_priv->cs = -1; + strcpy(txx9_priv->mtdname, dev_name(&dev->dev)); + } + if (plat->wide_mask & (1 << i)) + chip->options |= NAND_BUSWIDTH_16; + + if (nand_scan(mtd, 1)) { + kfree(txx9_priv); + continue; + } + mtd->name = txx9_priv->mtdname; + +#ifdef CONFIG_MTD_PARTITIONS + nr_parts = parse_mtd_partitions(mtd, probes, &parts, 0); + if (nr_parts > 0) { + add_mtd_partitions(mtd, parts, nr_parts); + kfree(parts); + } +#endif + add_mtd_device(mtd); + drvdata->mtds[i] = mtd; + } + + return 0; +} + +static int __exit txx9ndfmc_remove(struct platform_device *dev) +{ + struct txx9ndfmc_drvdata *drvdata = platform_get_drvdata(dev); + int i; + + platform_set_drvdata(dev, NULL); + if (!drvdata) + return 0; + for (i = 0; i < MAX_TXX9NDFMC_DEV; i++) { + struct mtd_info *mtd = drvdata->mtds[i]; + struct nand_chip *chip; + struct txx9ndfmc_priv *txx9_priv; + + if (!mtd) + continue; + chip = mtd->priv; + txx9_priv = chip->priv; + +#ifdef CONFIG_MTD_PARTITIONS + del_mtd_partitions(mtd); +#endif + del_mtd_device(mtd); + kfree(txx9_priv); + } + return 0; +} + +#ifdef CONFIG_PM +static int txx9ndfmc_resume(struct platform_device *dev) +{ + if (platform_get_drvdata(dev)) + txx9ndfmc_initialize(dev); + return 0; +} +#else +#define txx9ndfmc_resume NULL +#endif + +static struct platform_driver txx9ndfmc_driver = { + .remove = __exit_p(txx9ndfmc_remove), + .resume = txx9ndfmc_resume, + .driver = { + .name = "txx9ndfmc", + .owner = THIS_MODULE, + }, +}; + +static int __init txx9ndfmc_init(void) +{ + return platform_driver_probe(&txx9ndfmc_driver, txx9ndfmc_probe); +} + +static void __exit txx9ndfmc_exit(void) +{ + platform_driver_unregister(&txx9ndfmc_driver); +} + +module_init(txx9ndfmc_init); +module_exit(txx9ndfmc_exit); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("TXx9 SoC NAND flash controller driver"); +MODULE_ALIAS("platform:txx9ndfmc"); -- 1.5.6.3 From anemo@mba.ocn.ne.jp Tue Jan 20 14:12:58 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 20 Jan 2009 14:13:01 +0000 (GMT) Received: from mba.ocn.ne.jp ([122.1.235.107]:12513 "HELO smtp.mba.ocn.ne.jp") by ftp.linux-mips.org with SMTP id S21366211AbZATOMR (ORCPT ); Tue, 20 Jan 2009 14:12:17 +0000 Received: from localhost.localdomain (p1210-ipad205funabasi.chiba.ocn.ne.jp [222.146.96.210]) by smtp.mba.ocn.ne.jp (Postfix) with ESMTP id C5989A4D2; Tue, 20 Jan 2009 23:12:11 +0900 (JST) From: Atsushi Nemoto To: linux-mips@linux-mips.org Cc: ralf@linux-mips.org, linux-mtd@lists.infradead.org, dwmw2@infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/5] TXx9: Add NDFMC support Date: Tue, 20 Jan 2009 23:12:15 +0900 Message-Id: <1232460738-4714-1-git-send-email-anemo@mba.ocn.ne.jp> X-Mailer: git-send-email 1.5.6.3 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21788 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anemo@mba.ocn.ne.jp Precedence: bulk X-list: linux-mips Content-Length: 7441 Lines: 220 Add platform support for NAND Flash Memory Controller of TXx9 SoCs. Signed-off-by: Atsushi Nemoto --- arch/mips/include/asm/txx9/ndfmc.h | 30 ++++++++++++++++++++++++++++++ arch/mips/include/asm/txx9/tx4938.h | 1 + arch/mips/include/asm/txx9/tx4939.h | 2 ++ arch/mips/txx9/generic/setup.c | 21 +++++++++++++++++++++ arch/mips/txx9/generic/setup_tx4938.c | 21 +++++++++++++++++++++ arch/mips/txx9/generic/setup_tx4939.c | 17 +++++++++++++++++ arch/mips/txx9/rbtx4938/setup.c | 2 ++ arch/mips/txx9/rbtx4939/setup.c | 4 ++++ 8 files changed, 98 insertions(+), 0 deletions(-) create mode 100644 arch/mips/include/asm/txx9/ndfmc.h diff --git a/arch/mips/include/asm/txx9/ndfmc.h b/arch/mips/include/asm/txx9/ndfmc.h new file mode 100644 index 0000000..fa67f3d --- /dev/null +++ b/arch/mips/include/asm/txx9/ndfmc.h @@ -0,0 +1,30 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * (C) Copyright TOSHIBA CORPORATION 2007 + */ +#ifndef __ASM_TXX9_NDFMC_H +#define __ASM_TXX9_NDFMC_H + +#define NDFMC_PLAT_FLAG_USE_BSPRT 0x01 +#define NDFMC_PLAT_FLAG_NO_RSTR 0x02 +#define NDFMC_PLAT_FLAG_HOLDADD 0x04 +#define NDFMC_PLAT_FLAG_DUMMYWRITE 0x08 + +struct txx9ndfmc_platform_data { + unsigned int shift; + unsigned int gbus_clock; + unsigned int hold; /* hold time in nanosecond */ + unsigned int spw; /* strobe pulse width in nanosecond */ + unsigned int flags; + unsigned char ch_mask; /* available channel bitmask */ + unsigned char wp_mask; /* write-protect bitmask */ + unsigned char wide_mask; /* 16bit-nand bitmask */ +}; + +void txx9_ndfmc_init(unsigned long baseaddr, + const struct txx9ndfmc_platform_data *plat_data); + +#endif /* __ASM_TXX9_NDFMC_H */ diff --git a/arch/mips/include/asm/txx9/tx4938.h b/arch/mips/include/asm/txx9/tx4938.h index 0b06815..cd8bc20 100644 --- a/arch/mips/include/asm/txx9/tx4938.h +++ b/arch/mips/include/asm/txx9/tx4938.h @@ -291,6 +291,7 @@ int tx4938_pcic1_map_irq(const struct pci_dev *dev, u8 slot); void tx4938_setup_pcierr_irq(void); void tx4938_irq_init(void); void tx4938_mtd_init(int ch); +void tx4938_ndfmc_init(unsigned int hold, unsigned int spw); struct tx4938ide_platform_info { /* diff --git a/arch/mips/include/asm/txx9/tx4939.h b/arch/mips/include/asm/txx9/tx4939.h index 964ef7e..af456c7 100644 --- a/arch/mips/include/asm/txx9/tx4939.h +++ b/arch/mips/include/asm/txx9/tx4939.h @@ -541,6 +541,8 @@ void tx4939_irq_init(void); int tx4939_irq(void); void tx4939_mtd_init(int ch); void tx4939_ata_init(void); +void tx4939_ndfmc_init(unsigned int hold, unsigned int spw, + unsigned char ch_mask, unsigned char wide_mask); void tx4939_rtc_init(void); #endif /* __ASM_TXX9_TX4939_H */ diff --git a/arch/mips/txx9/generic/setup.c b/arch/mips/txx9/generic/setup.c index a13a08b..8a266c6 100644 --- a/arch/mips/txx9/generic/setup.c +++ b/arch/mips/txx9/generic/setup.c @@ -32,6 +32,7 @@ #include #include #include +#include #ifdef CONFIG_CPU_TX49XX #include #endif @@ -691,6 +692,26 @@ void __init txx9_physmap_flash_init(int no, unsigned long addr, #endif } +void __init txx9_ndfmc_init(unsigned long baseaddr, + const struct txx9ndfmc_platform_data *pdata) +{ +#if defined(CONFIG_MTD_NAND_TXX9NDFMC) || \ + defined(CONFIG_MTD_NAND_TXX9NDFMC_MODULE) + struct resource res = { + .start = baseaddr, + .end = baseaddr + 0x1000 - 1, + .flags = IORESOURCE_MEM, + }; + struct platform_device *pdev = platform_device_alloc("txx9ndfmc", -1); + + if (!pdev || + platform_device_add_resources(pdev, &res, 1) || + platform_device_add_data(pdev, pdata, sizeof(*pdata)) || + platform_device_add(pdev)) + platform_device_put(pdev); +#endif +} + #if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE) static DEFINE_SPINLOCK(txx9_iocled_lock); diff --git a/arch/mips/txx9/generic/setup_tx4938.c b/arch/mips/txx9/generic/setup_tx4938.c index 25819ff..f0844f8 100644 --- a/arch/mips/txx9/generic/setup_tx4938.c +++ b/arch/mips/txx9/generic/setup_tx4938.c @@ -23,6 +23,7 @@ #include #include #include +#include #include static void __init tx4938_wdr_init(void) @@ -382,6 +383,26 @@ void __init tx4938_ata_init(unsigned int irq, unsigned int shift, int tune) platform_device_put(pdev); } +void __init tx4938_ndfmc_init(unsigned int hold, unsigned int spw) +{ + struct txx9ndfmc_platform_data plat_data = { + .shift = 1, + .gbus_clock = txx9_gbus_clock, + .hold = hold, + .spw = spw, + .ch_mask = 1, + }; + unsigned long baseaddr = TX4938_NDFMC_REG & 0xfffffffffULL; + +#ifdef __BIG_ENDIAN + baseaddr += 4; +#endif + if ((__raw_readq(&tx4938_ccfgptr->pcfg) & + (TX4938_PCFG_ATA_SEL|TX4938_PCFG_ISA_SEL|TX4938_PCFG_NDF_SEL)) == + TX4938_PCFG_NDF_SEL) + txx9_ndfmc_init(baseaddr, &plat_data); +} + static void __init tx4938_stop_unused_modules(void) { __u64 pcfg, rst = 0, ckd = 0; diff --git a/arch/mips/txx9/generic/setup_tx4939.c b/arch/mips/txx9/generic/setup_tx4939.c index 5544096..ec56b91 100644 --- a/arch/mips/txx9/generic/setup_tx4939.c +++ b/arch/mips/txx9/generic/setup_tx4939.c @@ -27,6 +27,7 @@ #include #include #include +#include #include static void __init tx4939_wdr_init(void) @@ -435,6 +436,22 @@ void __init tx4939_ata_init(void) platform_device_register(&ata1_dev); } +void __init tx4939_ndfmc_init(unsigned int hold, unsigned int spw, + unsigned char ch_mask, unsigned char wide_mask) +{ + struct txx9ndfmc_platform_data plat_data = { + .shift = 1, + .gbus_clock = txx9_gbus_clock, + .hold = hold, + .spw = spw, + .flags = NDFMC_PLAT_FLAG_NO_RSTR | NDFMC_PLAT_FLAG_HOLDADD | + NDFMC_PLAT_FLAG_DUMMYWRITE, + .ch_mask = ch_mask, + .wide_mask = wide_mask, + }; + txx9_ndfmc_init(TX4939_NDFMC_REG & 0xfffffffffULL, &plat_data); +} + void __init tx4939_rtc_init(void) { static struct resource res[] = { diff --git a/arch/mips/txx9/rbtx4938/setup.c b/arch/mips/txx9/rbtx4938/setup.c index 547ff29..65d13df 100644 --- a/arch/mips/txx9/rbtx4938/setup.c +++ b/arch/mips/txx9/rbtx4938/setup.c @@ -352,6 +352,8 @@ static void __init rbtx4938_device_init(void) rbtx4938_ne_init(); tx4938_wdt_init(); rbtx4938_mtd_init(); + /* TC58DVM82A1FT: tDH=10ns, tWP=tRP=tREADID=35ns */ + tx4938_ndfmc_init(10, 35); tx4938_ata_init(RBTX4938_IRQ_IOC_ATA, 0, 1); txx9_iocled_init(RBTX4938_LED_ADDR - IO_BASE, -1, 8, 1, "green", NULL); } diff --git a/arch/mips/txx9/rbtx4939/setup.c b/arch/mips/txx9/rbtx4939/setup.c index 656603b..74839f2 100644 --- a/arch/mips/txx9/rbtx4939/setup.c +++ b/arch/mips/txx9/rbtx4939/setup.c @@ -333,6 +333,10 @@ static void __init rbtx4939_device_init(void) platform_device_add_data(pdev, &smc_pdata, sizeof(smc_pdata)) || platform_device_add(pdev)) platform_device_put(pdev); + /* TC58DVM82A1FT: tDH=10ns, tWP=tRP=tREADID=35ns */ + tx4939_ndfmc_init(10, 35, + (1 << 1) | (1 << 2), + (1 << 2)); /* ch1:8bit, ch2:16bit */ rbtx4939_led_setup(); tx4939_wdt_init(); tx4939_ata_init(); -- 1.5.6.3 From anemo@mba.ocn.ne.jp Tue Jan 20 14:13:18 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 20 Jan 2009 14:13:20 +0000 (GMT) Received: from mba.ocn.ne.jp ([122.1.235.107]:44257 "HELO smtp.mba.ocn.ne.jp") by ftp.linux-mips.org with SMTP id S21366220AbZATOMS (ORCPT ); Tue, 20 Jan 2009 14:12:18 +0000 Received: from localhost.localdomain (p1210-ipad205funabasi.chiba.ocn.ne.jp [222.146.96.210]) by smtp.mba.ocn.ne.jp (Postfix) with ESMTP id 1AA35A99C; Tue, 20 Jan 2009 23:12:14 +0900 (JST) From: Atsushi Nemoto To: linux-mips@linux-mips.org Cc: ralf@linux-mips.org, linux-mtd@lists.infradead.org, dwmw2@infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 4/5] MTD: RBTX4939 map driver Date: Tue, 20 Jan 2009 23:12:18 +0900 Message-Id: <1232460738-4714-4-git-send-email-anemo@mba.ocn.ne.jp> X-Mailer: git-send-email 1.5.6.3 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21789 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anemo@mba.ocn.ne.jp Precedence: bulk X-list: linux-mips Content-Length: 6667 Lines: 250 This is a map driver for NOR flash chips on RBTX4939 board. Signed-off-by: Atsushi Nemoto --- drivers/mtd/maps/Kconfig | 6 + drivers/mtd/maps/Makefile | 1 + drivers/mtd/maps/rbtx4939-flash.c | 205 +++++++++++++++++++++++++++++++++++++ 3 files changed, 212 insertions(+), 0 deletions(-) create mode 100644 drivers/mtd/maps/rbtx4939-flash.c diff --git a/drivers/mtd/maps/Kconfig b/drivers/mtd/maps/Kconfig index 0225cbb..162f32b 100644 --- a/drivers/mtd/maps/Kconfig +++ b/drivers/mtd/maps/Kconfig @@ -542,6 +542,12 @@ config MTD_INTEL_VR_NOR Map driver for a NOR flash bank located on the Expansion Bus of the Intel Vermilion Range chipset. +config MTD_RBTX4939 + tristate "Map driver for RBTX4939 board" + depends on TOSHIBA_RBTX4939 && MTD_CFI && MTD_COMPLEX_MAPPINGS + help + Map driver for NOR flash chips on RBTX4939 board. + config MTD_PLATRAM tristate "Map driver for platform device RAM (mtd-ram)" select MTD_RAM diff --git a/drivers/mtd/maps/Makefile b/drivers/mtd/maps/Makefile index 6d9ba35..f53a7dc 100644 --- a/drivers/mtd/maps/Makefile +++ b/drivers/mtd/maps/Makefile @@ -61,3 +61,4 @@ obj-$(CONFIG_MTD_PLATRAM) += plat-ram.o obj-$(CONFIG_MTD_OMAP_NOR) += omap_nor.o obj-$(CONFIG_MTD_INTEL_VR_NOR) += intel_vr_nor.o obj-$(CONFIG_MTD_BFIN_ASYNC) += bfin-async-flash.o +obj-$(CONFIG_MTD_RBTX4939) += rbtx4939-flash.o diff --git a/drivers/mtd/maps/rbtx4939-flash.c b/drivers/mtd/maps/rbtx4939-flash.c new file mode 100644 index 0000000..389b60f --- /dev/null +++ b/drivers/mtd/maps/rbtx4939-flash.c @@ -0,0 +1,205 @@ +/* + * rbtx4939-flash (based on physmap.c) + * + * This is a simplified physmap driver with map_init callback function. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * Copyright (C) 2009 Atsushi Nemoto + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct rbtx4939_flash_info { + struct mtd_info *mtd; + struct map_info map; +#ifdef CONFIG_MTD_PARTITIONS + int nr_parts; +#endif +}; + +static int rbtx4939_flash_remove(struct platform_device *dev) +{ + struct rbtx4939_flash_info *info; + + info = platform_get_drvdata(dev); + if (!info) + return 0; + platform_set_drvdata(dev, NULL); + + if (info->mtd) { +#ifdef CONFIG_MTD_PARTITIONS + struct rbtx4939_flash_data *pdata = dev->dev.platform_data; + + if (info->nr_parts || pdata->nr_parts) + del_mtd_partitions(info->mtd); + else + del_mtd_device(info->mtd); +#else + del_mtd_device(info->mtd); +#endif + map_destroy(info->mtd); + } + return 0; +} + +static const char *rom_probe_types[] = { "cfi_probe", "jedec_probe", NULL }; +#ifdef CONFIG_MTD_PARTITIONS +static const char *part_probe_types[] = { "cmdlinepart", NULL }; +#endif + +static int rbtx4939_flash_probe(struct platform_device *dev) +{ + struct rbtx4939_flash_data *pdata; + struct rbtx4939_flash_info *info; + struct resource *res; + const char **probe_type; + int err = 0; + unsigned long size; +#ifdef CONFIG_MTD_PARTITIONS + struct mtd_partition *parts; +#endif + + pdata = dev->dev.platform_data; + if (!pdata) + return -ENODEV; + + res = platform_get_resource(dev, IORESOURCE_MEM, 0); + if (!res) + return -ENODEV; + info = devm_kzalloc(&dev->dev, sizeof(struct rbtx4939_flash_info), + GFP_KERNEL); + if (!info) + return -ENOMEM; + + platform_set_drvdata(dev, info); + + size = resource_size(res); + pr_notice("rbtx4939 platform flash device: %pR\n", res); + + if (!devm_request_mem_region(&dev->dev, res->start, size, + dev_name(&dev->dev))) + return -EBUSY; + + info->map.name = dev_name(&dev->dev); + info->map.phys = res->start; + info->map.size = size; + info->map.bankwidth = pdata->width; + + info->map.virt = devm_ioremap(&dev->dev, info->map.phys, size); + if (!info->map.virt) + return -EBUSY; + + if (pdata->map_init) + (*pdata->map_init)(&info->map); + else + simple_map_init(&info->map); + + probe_type = rom_probe_types; + for (; !info->mtd && *probe_type; probe_type++) + info->mtd = do_map_probe(*probe_type, &info->map); + if (!info->mtd) { + dev_err(&dev->dev, "map_probe failed\n"); + err = -ENXIO; + goto err_out; + } + info->mtd->owner = THIS_MODULE; + if (err) + goto err_out; + +#ifdef CONFIG_MTD_PARTITIONS + err = parse_mtd_partitions(info->mtd, part_probe_types, &parts, 0); + if (err > 0) { + add_mtd_partitions(info->mtd, parts, err); + return 0; + } + + if (pdata->nr_parts) { + pr_notice("Using rbtx4939 partition information\n"); + add_mtd_partitions(info->mtd, pdata->parts, pdata->nr_parts); + return 0; + } +#endif + + add_mtd_device(info->mtd); + return 0; + +err_out: + rbtx4939_flash_remove(dev); + return err; +} + +#ifdef CONFIG_PM +static int rbtx4939_flash_suspend(struct platform_device *dev, + pm_message_t state) +{ + struct rbtx4939_flash_info *info = platform_get_drvdata(dev); + + if (info->mtd->suspend) + return info->mtd->suspend(info->mtd); + return 0; +} + +static int rbtx4939_flash_resume(struct platform_device *dev) +{ + struct rbtx4939_flash_info *info = platform_get_drvdata(dev); + + if (info->mtd->resume) + info->mtd->resume(info->mtd); + return 0; +} + +static void rbtx4939_flash_shutdown(struct platform_device *dev) +{ + struct rbtx4939_flash_info *info = platform_get_drvdata(dev); + + if (info->mtd->suspend && info->mtd->resume) + if (info->mtd->suspend(info->mtd) == 0) + info->mtd->resume(info->mtd); +} +#else +#define rbtx4939_flash_suspend NULL +#define rbtx4939_flash_resume NULL +#define rbtx4939_flash_shutdown NULL +#endif + +static struct platform_driver rbtx4939_flash_driver = { + .probe = rbtx4939_flash_probe, + .remove = rbtx4939_flash_remove, + .suspend = rbtx4939_flash_suspend, + .resume = rbtx4939_flash_resume, + .shutdown = rbtx4939_flash_shutdown, + .driver = { + .name = "rbtx4939-flash", + .owner = THIS_MODULE, + }, +}; + +static int __init rbtx4939_flash_init(void) +{ + return platform_driver_register(&rbtx4939_flash_driver); +} + +static void __exit rbtx4939_flash_exit(void) +{ + platform_driver_unregister(&rbtx4939_flash_driver); +} + +module_init(rbtx4939_flash_init); +module_exit(rbtx4939_flash_exit); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("RBTX4939 MTD map driver"); +MODULE_ALIAS("platform:rbtx4939-flash"); -- 1.5.6.3 From anemo@mba.ocn.ne.jp Tue Jan 20 14:15:30 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 20 Jan 2009 14:15:32 +0000 (GMT) Received: from mba.ocn.ne.jp ([122.1.235.107]:25303 "HELO smtp.mba.ocn.ne.jp") by ftp.linux-mips.org with SMTP id S21366220AbZATOPa (ORCPT ); Tue, 20 Jan 2009 14:15:30 +0000 Received: from localhost (p1210-ipad205funabasi.chiba.ocn.ne.jp [222.146.96.210]) by smtp.mba.ocn.ne.jp (Postfix) with ESMTP id BF1FE3F30; Tue, 20 Jan 2009 23:15:25 +0900 (JST) Date: Tue, 20 Jan 2009 23:15:32 +0900 (JST) Message-Id: <20090120.231532.05599671.anemo@mba.ocn.ne.jp> To: linux-mips@linux-mips.org Cc: ralf@linux-mips.org, linux-mtd@lists.infradead.org, dwmw2@infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 1/5] TXx9: Add NDFMC support From: Atsushi Nemoto In-Reply-To: <1232460738-4714-1-git-send-email-anemo@mba.ocn.ne.jp> References: <1232460738-4714-1-git-send-email-anemo@mba.ocn.ne.jp> X-Fingerprint: 6ACA 1623 39BD 9A94 9B1A B746 CA77 FE94 2874 D52F X-Pgp-Public-Key: http://wwwkeys.pgp.net/pks/lookup?op=get&search=0x2874D52F X-Mailer: Mew version 5.2 on Emacs 21.4 / Mule 5.0 (SAKAKI) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21790 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anemo@mba.ocn.ne.jp Precedence: bulk X-list: linux-mips Content-Length: 263 Lines: 8 On Tue, 20 Jan 2009 23:12:15 +0900, Atsushi Nemoto wrote: > Add platform support for NAND Flash Memory Controller of TXx9 SoCs. Oops, this patchset contains only four patches, not five. Do not expect patch 5/5. Sorry. --- Atsushi Nemoto From khickey@rmicorp.com Wed Jan 21 00:47:26 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 21 Jan 2009 00:47:28 +0000 (GMT) Received: from mx1.rmicorp.com ([63.111.213.197]:1222 "EHLO hq-ex-mb01.razamicroelectronics.com") by ftp.linux-mips.org with ESMTP id S21366243AbZAUAr0 (ORCPT ); Wed, 21 Jan 2009 00:47:26 +0000 Received: from 10.8.0.24 ([10.8.0.24]) by hq-ex-mb01.razamicroelectronics.com ([10.1.1.40]) via Exchange Front-End Server webmail.razamicroelectronics.com ([10.1.1.41]) with Microsoft Exchange Server HTTP-DAV ; Wed, 21 Jan 2009 00:47:17 +0000 Received: from kh-d820 by webmail.razamicroelectronics.com; 20 Jan 2009 18:47:18 -0600 Subject: Re: [PATCH] Alchemy: fix edge irq handling From: Kevin Hickey To: Manuel Lauss Cc: Ralf Baechle , Linux-MIPS In-Reply-To: <20090120100353.GA18971@roarinelk.homelinux.net> References: <20090120100353.GA18971@roarinelk.homelinux.net> Content-Type: text/plain Content-Transfer-Encoding: 7bit Date: Tue, 20 Jan 2009 18:47:18 -0600 Message-Id: <1232498838.3678.17.camel@kh-d820> Mime-Version: 1.0 X-Mailer: Evolution 2.22.3.1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21791 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: khickey@rmicorp.com Precedence: bulk X-list: linux-mips Content-Length: 3211 Lines: 93 Manuel, Have you actually seen this happen (outside of inducing it manually)? I have some concern that by doing this we may either miss interrupts on devices that send a lot (by design) or miss a design bug in a system because we are masking out some interrupts. I know that system stability is important, but I don't like hiding problems. =Kevin On Tue, 2009-01-20 at 11:03 +0100, Manuel Lauss wrote: > Introduce separate mack_ack callbacks which really do shut up the > edge-triggered irqs when called. Without this change, high-frequency > edge interrupts can result in an endless irq storm, hanging the system. > > This can be easily triggered for example by setting an irq to falling > edge type and manually connecting the associated pin to ground. > > Signed-off-by: Manuel Lauss > --- > arch/mips/alchemy/common/irq.c | 32 ++++++++++++++++++++++++-------- > 1 files changed, 24 insertions(+), 8 deletions(-) > > diff --git a/arch/mips/alchemy/common/irq.c b/arch/mips/alchemy/common/irq.c > index c88c821..60da581 100644 > --- a/arch/mips/alchemy/common/irq.c > +++ b/arch/mips/alchemy/common/irq.c > @@ -320,6 +320,16 @@ static void au1x_ic0_mask(unsigned int irq_nr) > au_sync(); > } > > +static void au1x_ic0_maskack(unsigned int irq_nr) > +{ > + unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE; > + au_writel(1 << bit, IC0_MASKCLR); > + au_writel(1 << bit, IC0_WAKECLR); > + au_writel(1 << bit, IC0_FALLINGCLR); > + au_writel(1 << bit, IC0_RISINGCLR); > + au_sync(); > +} > + > static void au1x_ic1_mask(unsigned int irq_nr) > { > unsigned int bit = irq_nr - AU1000_INTC1_INT_BASE; > @@ -328,6 +338,16 @@ static void au1x_ic1_mask(unsigned int irq_nr) > au_sync(); > } > > +static void au1x_ic1_maskack(unsigned int irq_nr) > +{ > + unsigned int bit = irq_nr - AU1000_INTC1_INT_BASE; > + au_writel(1 << bit, IC1_MASKCLR); > + au_writel(1 << bit, IC1_WAKECLR); > + au_writel(1 << bit, IC1_FALLINGCLR); > + au_writel(1 << bit, IC1_RISINGCLR); > + au_sync(); > +} > + > static void au1x_ic0_ack(unsigned int irq_nr) > { > unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE; > @@ -379,25 +399,21 @@ static int au1x_ic1_setwake(unsigned int irq, unsigned int on) > /* > * irq_chips for both ICs; this way the mask handlers can be > * as short as possible. > - * > - * NOTE: the ->ack() callback is used by the handle_edge_irq > - * flowhandler only, the ->mask_ack() one by handle_level_irq, > - * so no need for an irq_chip for each type of irq (level/edge). > */ > static struct irq_chip au1x_ic0_chip = { > .name = "Alchemy-IC0", > - .ack = au1x_ic0_ack, /* edge */ > + .ack = au1x_ic0_ack, > .mask = au1x_ic0_mask, > - .mask_ack = au1x_ic0_mask, /* level */ > + .mask_ack = au1x_ic0_maskack, > .unmask = au1x_ic0_unmask, > .set_type = au1x_ic_settype, > }; > > static struct irq_chip au1x_ic1_chip = { > .name = "Alchemy-IC1", > - .ack = au1x_ic1_ack, /* edge */ > + .ack = au1x_ic1_ack, > .mask = au1x_ic1_mask, > - .mask_ack = au1x_ic1_mask, /* level */ > + .mask_ack = au1x_ic1_maskack, > .unmask = au1x_ic1_unmask, > .set_type = au1x_ic_settype, > .set_wake = au1x_ic1_setwake, -- =Kevin From David.Daney@caviumnetworks.com Wed Jan 21 01:50:45 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 21 Jan 2009 01:50:47 +0000 (GMT) Received: from mail3.caviumnetworks.com ([12.108.191.235]:5882 "EHLO mail3.caviumnetworks.com") by ftp.linux-mips.org with ESMTP id S21366249AbZAUBup (ORCPT ); Wed, 21 Jan 2009 01:50:45 +0000 Received: from exch4.caveonetworks.com (Not Verified[192.168.16.23]) by mail3.caviumnetworks.com with MailMarshal (v6,2,2,3503) id ; Tue, 20 Jan 2009 20:50:17 -0500 Received: from exch4.caveonetworks.com ([192.168.16.23]) by exch4.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Tue, 20 Jan 2009 17:50:15 -0800 Received: from dd1.caveonetworks.com ([64.169.86.201]) by exch4.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Tue, 20 Jan 2009 17:50:15 -0800 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.2/8.14.2) with ESMTP id n0L1o8SG009488; Tue, 20 Jan 2009 17:50:11 -0800 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.2/8.14.2/Submit) id n0L1o7CJ009486; Tue, 20 Jan 2009 17:50:07 -0800 From: David Daney To: linux-ide@vger.kernel.org Cc: linux-mips@linux-mips.org, David Daney Subject: [PATCH] libata: Remove some redundant casts from pata_octeon_cf.c Date: Tue, 20 Jan 2009 17:49:58 -0800 Message-Id: <1232502598-9464-1-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.5.6.6 X-OriginalArrivalTime: 21 Jan 2009 01:50:15.0549 (UTC) FILETIME=[9B16EAD0:01C97B6A] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21792 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Content-Length: 1294 Lines: 39 Signed-off-by: David Daney --- drivers/ata/pata_octeon_cf.c | 6 +++--- 1 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/ata/pata_octeon_cf.c b/drivers/ata/pata_octeon_cf.c index 0fe4ef3..0e71be1 100644 --- a/drivers/ata/pata_octeon_cf.c +++ b/drivers/ata/pata_octeon_cf.c @@ -503,7 +503,7 @@ static void octeon_cf_dma_setup(struct ata_queued_cmd *qc) struct ata_port *ap = qc->ap; struct octeon_cf_port *cf_port; - cf_port = (struct octeon_cf_port *)ap->private_data; + cf_port = ap->private_data; DPRINTK("ENTER\n"); /* issue r/w command */ qc->cursg = qc->sg; @@ -596,7 +596,7 @@ static unsigned int octeon_cf_dma_finished(struct ata_port *ap, if (ap->hsm_task_state != HSM_ST_LAST) return 0; - cf_port = (struct octeon_cf_port *)ap->private_data; + cf_port = ap->private_data; dma_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_DMA_CFGX(ocd->dma_engine)); if (dma_cfg.s.size != 0xfffff) { @@ -657,7 +657,7 @@ static irqreturn_t octeon_cf_interrupt(int irq, void *dev_instance) continue; ocd = ap->dev->platform_data; - cf_port = (struct octeon_cf_port *)ap->private_data; + cf_port = ap->private_data; dma_int.u64 = cvmx_read_csr(CVMX_MIO_BOOT_DMA_INTX(ocd->dma_engine)); dma_cfg.u64 = -- 1.5.6.6 From mano@roarinelk.homelinux.net Wed Jan 21 06:48:58 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 21 Jan 2009 06:49:00 +0000 (GMT) Received: from fnoeppeil36.netpark.at ([217.175.205.164]:47514 "EHLO roarinelk.homelinux.net") by ftp.linux-mips.org with ESMTP id S21365687AbZAUGs6 (ORCPT ); Wed, 21 Jan 2009 06:48:58 +0000 Received: (qmail 27110 invoked by uid 1000); 21 Jan 2009 07:48:56 +0100 Date: Wed, 21 Jan 2009 07:48:56 +0100 From: Manuel Lauss To: Kevin Hickey Cc: Ralf Baechle , Linux-MIPS Subject: Re: [PATCH] Alchemy: fix edge irq handling Message-ID: <20090121064856.GA27020@roarinelk.homelinux.net> References: <20090120100353.GA18971@roarinelk.homelinux.net> <1232498838.3678.17.camel@kh-d820> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1232498838.3678.17.camel@kh-d820> User-Agent: Mutt/1.5.16 (2007-06-09) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21793 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mano@roarinelk.homelinux.net Precedence: bulk X-list: linux-mips Content-Length: 1161 Lines: 30 Hi Kevin, > Have you actually seen this happen (outside of inducing it manually)? I > have some concern that by doing this we may either miss interrupts on > devices that send a lot (by design) or miss a design bug in a system > because we are masking out some interrupts. I know that system > stability is important, but I don't like hiding problems. Yes, in a customer project. A simple pushbutton which connects a pulled-up gpio pin to ground. Push it, instant hang (handler called over and over again) when it is not debounced. With a single edge and a much lower edge-frequency it obviously works fine (see timer). (And, handle_edge_irq() _does_ call mask_ack() after all). Best regards, Manuel Lauss > =Kevin > > On Tue, 2009-01-20 at 11:03 +0100, Manuel Lauss wrote: > > Introduce separate mack_ack callbacks which really do shut up the > > edge-triggered irqs when called. Without this change, high-frequency > > edge interrupts can result in an endless irq storm, hanging the system. > > > > This can be easily triggered for example by setting an irq to falling > > edge type and manually connecting the associated pin to ground. > > From cl@linux-foundation.org Wed Jan 21 14:43:11 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 21 Jan 2009 14:43:15 +0000 (GMT) Received: from smtp.ultrahosting.com ([74.213.174.254]:6028 "EHLO smtp.ultrahosting.com") by ftp.linux-mips.org with ESMTP id S21365847AbZAUOnL (ORCPT ); Wed, 21 Jan 2009 14:43:11 +0000 Received: from localhost (smtp.ultrahosting.com [127.0.0.1]) by smtp.ultrahosting.com (Postfix) with ESMTP id ACEB182C46B for ; Wed, 21 Jan 2009 09:44:17 -0500 (EST) X-Virus-Scanned: amavisd-new at ultrahosting.com Received: from smtp.ultrahosting.com ([74.213.174.254]) by localhost (smtp.ultrahosting.com [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id oCsyhwPfuJne for ; Wed, 21 Jan 2009 09:44:17 -0500 (EST) Received: from qirst.com (unknown [74.213.171.31]) by smtp.ultrahosting.com (Postfix) with ESMTP id D967382C46D for ; Wed, 21 Jan 2009 09:44:16 -0500 (EST) Received: from cl (helo=localhost) by qirst.com with local-esmtp (Exim 4.69) (envelope-from ) id 1LPeFC-0003UH-RE; Wed, 21 Jan 2009 09:39:50 -0500 Date: Wed, 21 Jan 2009 09:39:50 -0500 (EST) From: Christoph Lameter X-X-Sender: cl@qirst.com To: Michael Sundius cc: Dave Hansen , Randy Dunlap , "Sundius, Michael" , Thomas Bogendoerfer , linux-mm@kvack.org, linux-mips@linux-mips.org, jfraser@broadcom.com, Andy Whitcroft , msundius@sundius.com Subject: Re: sparsemem support for mips with highmem In-Reply-To: <4971002D.2090907@cisco.com> Message-ID: References: <48A4AC39.7020707@sciatl.com> <1218753308.23641.56.camel@nimitz> <48A4C542.5000308@sciatl.com> <20080815080331.GA6689@alpha.franken.de> <1218815299.23641.80.camel@nimitz> <48A5AADE.1050808@sciatl.com> <20080815163302.GA9846@alpha.franken.de> <48A5B9F1.3080201@sciatl.com> <1218821875.23641.103.camel@nimitz> <48A5C831.3070002@sciatl.com> <20080818094412.09086445.rdunlap@xenotime.net> <48A9E89C.4020408@linux-foundation.org> <1219094865.23641.118.camel@nimitz> <48A9EAA9.1080909@linux-foundation.org> <4971002D.2090907@cisco.com> User-Agent: Alpine 1.10 (DEB 962 2008-03-14) MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21794 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: cl@linux-foundation.org Precedence: bulk X-list: linux-mips Content-Length: 676 Lines: 18 On Fri, 16 Jan 2009, Michael Sundius wrote: > you said that the simplest configuration is to use vmalloc for the populate > function. > could you expand on that? (i didn't see that the populate function used > vmalloc or maybe > we are talking about a different populate function). If you place the vmemmap in the vmalloc area then its easy to reserve virtual space for the vmemmap. You can use the vmalloc populate functions to populate the vmemmap. > this work w/ mips which i understand uses only 2 levels can I just take out > the part of > the function that sets up the middle level table? Sure. Hoever, the vmemmap populate stuff will do that automagically for you. From n0-1@nwl.cc Thu Jan 22 00:38:19 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 22 Jan 2009 00:38:22 +0000 (GMT) Received: from orbit.nwl.cc ([91.121.169.95]:21141 "EHLO mail.nwl.cc") by ftp.linux-mips.org with ESMTP id S21366284AbZAVAiT (ORCPT ); Thu, 22 Jan 2009 00:38:19 +0000 Received: from nuty (localhost [127.0.0.1]) by mail.nwl.cc (Postfix) with ESMTP id 1D458400E106; Thu, 22 Jan 2009 01:38:14 +0100 (CET) Date: Thu, 22 Jan 2009 01:41:34 +0100 From: Phil Sutter To: Ralf Baechle Cc: linux-mips@linux-mips.org Subject: Re: [PATCH] MIPS: rb532: remove unused rb532_gpio_set_func() Mail-Followup-To: Ralf Baechle , linux-mips@linux-mips.org References: <20081128193322.D103C386DBBE@mail.ifyouseekate.net> <20081128194353.DC55A386DBBE@mail.ifyouseekate.net> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20081128194353.DC55A386DBBE@mail.ifyouseekate.net> User-Agent: Mutt/1.5.11 Message-Id: <20090122003814.1D458400E106@mail.nwl.cc> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21795 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: n0-1@freewrt.org Precedence: bulk X-list: linux-mips Content-Length: 601 Lines: 14 Hi, On Fri, Nov 28, 2008 at 08:46:29PM +0100, Phil Sutter wrote: > Since disabling of the alternate function of a GPIO pin is being done > implicitly when changing it's direction, the above mentioned function is > not being called anymore and can be removed. Please do not apply this patch. In fact, the function in question should be exported as kernel symbol, as else there is no possibility for drivers to turn on alternate function for a GPIO pin. This is of particular use when trying to read the S1 button state, as the corresponding GPIO pin is multiplexed with UART0 input. Greetings, Phil From anemo@mba.ocn.ne.jp Thu Jan 22 15:42:17 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 22 Jan 2009 15:42:21 +0000 (GMT) Received: from mba.ocn.ne.jp ([122.1.235.107]:15080 "HELO smtp.mba.ocn.ne.jp") by ftp.linux-mips.org with SMTP id S21103349AbZAVPmR (ORCPT ); Thu, 22 Jan 2009 15:42:17 +0000 Received: from localhost.localdomain (p7001-ipad208funabasi.chiba.ocn.ne.jp [60.43.108.1]) by smtp.mba.ocn.ne.jp (Postfix) with ESMTP id F20DDA857; Fri, 23 Jan 2009 00:42:10 +0900 (JST) From: Atsushi Nemoto To: linux-mips@linux-mips.org Cc: ralf@linux-mips.org Subject: [PATCH] Synchronize dma_map_page and dma_map_single Date: Fri, 23 Jan 2009 00:42:11 +0900 Message-Id: <1232638931-6203-1-git-send-email-anemo@mba.ocn.ne.jp> X-Mailer: git-send-email 1.5.6.3 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21796 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anemo@mba.ocn.ne.jp Precedence: bulk X-list: linux-mips Content-Length: 1495 Lines: 47 Synchronize dma_map_page/dma_unmap_page and dma_map_single/dma_unmap_single. This will reduce unnecessary writeback/invalidate. Signed-off-by: Atsushi Nemoto --- This patch depends on a patch titled "fix oops in dma_unmap_page on not coherent mips platforms". by Jan Nikitenko. http://www.linux-mips.org/cgi-bin/mesg.cgi?a=linux-mips&i=20081128075258.GA10200%40nikitenko.systek.local arch/mips/mm/dma-default.c | 13 ++----------- 1 files changed, 2 insertions(+), 11 deletions(-) diff --git a/arch/mips/mm/dma-default.c b/arch/mips/mm/dma-default.c index bed56f1..96b0061 100644 --- a/arch/mips/mm/dma-default.c +++ b/arch/mips/mm/dma-default.c @@ -209,7 +209,7 @@ dma_addr_t dma_map_page(struct device *dev, struct page *page, unsigned long addr; addr = (unsigned long) page_address(page) + offset; - dma_cache_wback_inv(addr, size); + __dma_sync(addr, size, direction); } return plat_map_dma_mem_page(dev, page) + offset; @@ -220,16 +220,7 @@ EXPORT_SYMBOL(dma_map_page); void dma_unmap_page(struct device *dev, dma_addr_t dma_address, size_t size, enum dma_data_direction direction) { - BUG_ON(direction == DMA_NONE); - - if (!plat_device_is_coherent(dev) && direction != DMA_TO_DEVICE) { - unsigned long addr; - - addr = dma_addr_to_virt(dma_address); - dma_cache_wback_inv(addr, size); - } - - plat_unmap_dma_mem(dev, dma_address); + dma_unmap_single(dev, dma_address, size, direction); } EXPORT_SYMBOL(dma_unmap_page); -- 1.5.6.3 From n0-1@nwl.cc Thu Jan 22 18:29:03 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 22 Jan 2009 18:29:06 +0000 (GMT) Received: from orbit.nwl.cc ([91.121.169.95]:12676 "EHLO mail.nwl.cc") by ftp.linux-mips.org with ESMTP id S21103481AbZAVS3D (ORCPT ); Thu, 22 Jan 2009 18:29:03 +0000 Received: from base (localhost [127.0.0.1]) by mail.nwl.cc (Postfix) with ESMTP id 07E45400E106; Thu, 22 Jan 2009 19:28:57 +0100 (CET) From: Phil Sutter To: Linux-Mips List Cc: Ralf Baechle Subject: [PATCH] rb532: update headers Date: Thu, 22 Jan 2009 19:28:50 +0100 X-Mailer: git-send-email 1.5.6.4 In-Reply-To: <20081128193322.D103C386DBBE@mail.ifyouseekate.net> References: <20081128193322.D103C386DBBE@mail.ifyouseekate.net> Message-Id: <20090122182858.07E45400E106@mail.nwl.cc> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21797 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: n0-1@freewrt.org Precedence: bulk X-list: linux-mips Content-Length: 1512 Lines: 40 Remove the {set,get}_434_reg() prototypes, as the functions have been removed. Also move the prototypes for {get,set}_latch_u5() to the correct place. Signed-off-by: Phil Sutter --- arch/mips/include/asm/mach-rc32434/gpio.h | 4 ---- arch/mips/include/asm/mach-rc32434/rb.h | 3 +++ 2 files changed, 3 insertions(+), 4 deletions(-) diff --git a/arch/mips/include/asm/mach-rc32434/gpio.h b/arch/mips/include/asm/mach-rc32434/gpio.h index b5cf645..ca92c81 100644 --- a/arch/mips/include/asm/mach-rc32434/gpio.h +++ b/arch/mips/include/asm/mach-rc32434/gpio.h @@ -80,10 +80,6 @@ struct rb532_gpio_reg { /* Compact Flash GPIO pin */ #define CF_GPIO_NUM 13 -extern void set_434_reg(unsigned reg_offs, unsigned bit, unsigned len, unsigned val); -extern unsigned get_434_reg(unsigned reg_offs); -extern void set_latch_u5(unsigned char or_mask, unsigned char nand_mask); -extern unsigned char get_latch_u5(void); extern void rb532_gpio_set_ilevel(int bit, unsigned gpio); extern void rb532_gpio_set_istat(int bit, unsigned gpio); diff --git a/arch/mips/include/asm/mach-rc32434/rb.h b/arch/mips/include/asm/mach-rc32434/rb.h index f25a849..6dc5f8d 100644 --- a/arch/mips/include/asm/mach-rc32434/rb.h +++ b/arch/mips/include/asm/mach-rc32434/rb.h @@ -83,4 +83,7 @@ struct mpmc_device { void __iomem *base; }; +extern void set_latch_u5(unsigned char or_mask, unsigned char nand_mask); +extern unsigned char get_latch_u5(void); + #endif /* __ASM_RC32434_RB_H */ -- 1.5.6.4 From n0-1@nwl.cc Thu Jan 22 18:32:56 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 22 Jan 2009 18:32:59 +0000 (GMT) Received: from orbit.nwl.cc ([91.121.169.95]:22739 "EHLO mail.nwl.cc") by ftp.linux-mips.org with ESMTP id S21103489AbZAVSc4 (ORCPT ); Thu, 22 Jan 2009 18:32:56 +0000 Received: from base (localhost [127.0.0.1]) by mail.nwl.cc (Postfix) with ESMTP id 39B48400E106; Thu, 22 Jan 2009 19:32:51 +0100 (CET) From: Phil Sutter To: Linux-Mips List Cc: Ralf Baechle Subject: [PATCH] MIPS: rb532: export rb532_gpio_set_func() Date: Thu, 22 Jan 2009 19:32:43 +0100 X-Mailer: git-send-email 1.5.6.4 In-Reply-To: <20081128193322.D103C386DBBE@mail.ifyouseekate.net> References: <20081128193322.D103C386DBBE@mail.ifyouseekate.net> Message-Id: <20090122183251.39B48400E106@mail.nwl.cc> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21798 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: n0-1@freewrt.org Precedence: bulk X-list: linux-mips Content-Length: 1510 Lines: 43 This kernel symbol provides a way for drivers to switch on alternate function for a certain GPIO pin. Turning it off is done implicitly when changing the GPIO direction, as that would be fixed when using the given pin als alternate function. Signed-off-by: Phil Sutter --- arch/mips/include/asm/mach-rc32434/gpio.h | 1 + arch/mips/rb532/gpio.c | 5 +++-- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/mips/include/asm/mach-rc32434/gpio.h b/arch/mips/include/asm/mach-rc32434/gpio.h index ca92c81..3cb50d1 100644 --- a/arch/mips/include/asm/mach-rc32434/gpio.h +++ b/arch/mips/include/asm/mach-rc32434/gpio.h @@ -82,5 +82,6 @@ struct rb532_gpio_reg { extern void rb532_gpio_set_ilevel(int bit, unsigned gpio); extern void rb532_gpio_set_istat(int bit, unsigned gpio); +extern void rb532_gpio_set_func(unsigned gpio); #endif /* _RC32434_GPIO_H_ */ diff --git a/arch/mips/rb532/gpio.c b/arch/mips/rb532/gpio.c index f338681..37de05d 100644 --- a/arch/mips/rb532/gpio.c +++ b/arch/mips/rb532/gpio.c @@ -174,10 +174,11 @@ EXPORT_SYMBOL(rb532_gpio_set_istat); /* * Configure GPIO alternate function */ -static void rb532_gpio_set_func(int bit, unsigned gpio) +void rb532_gpio_set_func(unsigned gpio) { - rb532_set_bit(bit, gpio, rb532_gpio_chip->regbase + GPIOFUNC); + rb532_set_bit(1, gpio, rb532_gpio_chip->regbase + GPIOFUNC); } +EXPORT_SYMBOL(rb532_gpio_set_func); int __init rb532_gpio_init(void) { -- 1.5.6.4 From n0-1@nwl.cc Thu Jan 22 19:12:21 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 22 Jan 2009 19:12:24 +0000 (GMT) Received: from orbit.nwl.cc ([91.121.169.95]:12972 "EHLO mail.nwl.cc") by ftp.linux-mips.org with ESMTP id S21103563AbZAVTMV (ORCPT ); Thu, 22 Jan 2009 19:12:21 +0000 Received: from base (localhost [127.0.0.1]) by mail.nwl.cc (Postfix) with ESMTP id 15285400E106; Thu, 22 Jan 2009 20:12:16 +0100 (CET) From: Phil Sutter To: Dmitry Torokhov Cc: linux-input@vger.kernel.org, Ralf Baechle , linux-mips@linux-mips.org, Florian Fainelli Subject: [PATCH 2/2] input: add driver for S1 button of rb532 Date: Thu, 22 Jan 2009 20:12:08 +0100 X-Mailer: git-send-email 1.5.6.4 In-Reply-To: <1232651528-19870-2-git-send-email-n0-1@freewrt.org> References: <1232651528-19870-1-git-send-email-n0-1@freewrt.org> <1232651528-19870-2-git-send-email-n0-1@freewrt.org> Message-Id: <20090122191216.15285400E106@mail.nwl.cc> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21799 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: n0-1@freewrt.org Precedence: bulk X-list: linux-mips Content-Length: 5197 Lines: 167 Mikrotik's Routerboard 532 has two builtin buttons, from which one triggers a hardware reset. The other one is accessible through GPIO pin 1. Sadly, this pin is being multiplexed with UART0 input, so enabling it as interrupt source (as implied by the gpio-keys driver) is not possible unless UART0 has been turned off. The later one though is a rather bad idea as the Routerboard is an embedded device with only a single serial port, so it's almost always used as serial console device. This patch adds a driver based on INPUT_POLLDEV, which disables the UART and reconfigures GPIO pin 1 temporarily while reading the button state. This procedure works fine and has been tested as part of another, unpublished driver for this device. Signed-off-by: Phil Sutter --- drivers/input/misc/Kconfig | 8 +++ drivers/input/misc/Makefile | 1 + drivers/input/misc/rb532_button.c | 111 +++++++++++++++++++++++++++++++++++++ 3 files changed, 120 insertions(+), 0 deletions(-) create mode 100644 drivers/input/misc/rb532_button.c diff --git a/drivers/input/misc/Kconfig b/drivers/input/misc/Kconfig index 67e5553..9666462 100644 --- a/drivers/input/misc/Kconfig +++ b/drivers/input/misc/Kconfig @@ -227,4 +227,12 @@ config INPUT_PCF50633_PMU Say Y to include support for delivering PMU events via input layer on NXP PCF50633. +config INPUT_RB532_BUTTON + tristate "Mikrotik Routerboard 532 button interface" + depends on MIKROTIK_RB532 + select INPUT_POLLDEV + help + Say Y here if you want support for the S1 button built into + Mikrotik's Routerboard 532. + endif diff --git a/drivers/input/misc/Makefile b/drivers/input/misc/Makefile index bb62e6e..0bb6a0e 100644 --- a/drivers/input/misc/Makefile +++ b/drivers/input/misc/Makefile @@ -22,3 +22,4 @@ obj-$(CONFIG_INPUT_UINPUT) += uinput.o obj-$(CONFIG_INPUT_APANEL) += apanel.o obj-$(CONFIG_INPUT_SGI_BTNS) += sgi_btns.o obj-$(CONFIG_INPUT_PCF50633_PMU) += pcf50633-input.o +obj-$(CONFIG_INPUT_RB532_BUTTON) += rb532_button.o diff --git a/drivers/input/misc/rb532_button.c b/drivers/input/misc/rb532_button.c new file mode 100644 index 0000000..05f2f49 --- /dev/null +++ b/drivers/input/misc/rb532_button.c @@ -0,0 +1,111 @@ +/* + * Support for the S1 button on Routerboard 532 + * + * Copyright (C) 2009 Phil Sutter + */ + +#include +#include +#include + +#include +#include + +#define DRV_NAME "rb532-button" + +#define RB532_BTN_RATE 100 /* msec */ +#define RB532_BTN_KSYM BTN_0 + +/* The S1 button state is provided by GPIO pin 1. But as this + * pin is also used for uart input as alternate function, the + * operational modes must be switched first: + * 1) disable uart using set_latch_u5() + * 2) turn off alternate function implicitly through + * gpio_direction_input() + * 3) read the GPIO's current value + * 4) undo step 2 by enabling alternate function (in this + * mode the GPIO direction is fixed, so no change needed) + * 5) turn on uart again + * The GPIO value occurs to be inverted, so pin high means + * button is not pressed. + */ +static bool rb532_button_pressed(void) { + int val; + + set_latch_u5(0, LO_FOFF); + gpio_direction_input(GPIO_BTN_S1); + + val = gpio_get_value(GPIO_BTN_S1); + + rb532_gpio_set_func(GPIO_BTN_S1); + set_latch_u5(LO_FOFF, 0); + + return !val; +} + +static void rb532_button_poll(struct input_polled_dev *poll_dev) +{ + input_report_key(poll_dev->input, RB532_BTN_KSYM, + rb532_button_pressed()); + input_sync(poll_dev->input); +} + +static int __devinit rb532_button_probe(struct platform_device *pdev) +{ + struct input_polled_dev *poll_dev; + + poll_dev = input_allocate_polled_device(); + if (!poll_dev) + return -ENOMEM; + + poll_dev->poll = rb532_button_poll; + poll_dev->poll_interval = RB532_BTN_RATE; + + poll_dev->input->name = "rb532 button"; + poll_dev->input->phys = "rb532/button0"; + poll_dev->input->id.bustype = BUS_HOST; + poll_dev->input->dev.parent = &pdev->dev; + + dev_set_drvdata(&pdev->dev, poll_dev); + + input_set_capability(poll_dev->input, EV_KEY, RB532_BTN_KSYM); + + return input_register_polled_device(poll_dev); +} + +static int __devexit rb532_button_remove(struct platform_device *pdev) +{ + struct input_polled_dev *poll_dev = dev_get_drvdata(&pdev->dev); + + input_unregister_polled_device(poll_dev); + input_free_polled_device(poll_dev); + dev_set_drvdata(&pdev->dev, NULL); + + return 0; +} + +static struct platform_driver rb532_button_driver = { + .probe = rb532_button_probe, + .remove = __devexit_p(rb532_button_remove), + .driver = { + .name = DRV_NAME, + .owner = THIS_MODULE, + }, +}; + +static int __init rb532_button_init(void) +{ + return platform_driver_register(&rb532_button_driver); +} + +static void __exit rb532_button_exit(void) +{ + platform_driver_unregister(&rb532_button_driver); +} + +module_init(rb532_button_init); +module_exit(rb532_button_exit); + +MODULE_AUTHOR("Phil Sutter "); +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("Support for S1 button on Routerboard 532"); -- 1.5.6.4 From n0-1@nwl.cc Thu Jan 22 19:12:40 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 22 Jan 2009 19:12:44 +0000 (GMT) Received: from orbit.nwl.cc ([91.121.169.95]:14508 "EHLO mail.nwl.cc") by ftp.linux-mips.org with ESMTP id S21103572AbZAVTMZ (ORCPT ); Thu, 22 Jan 2009 19:12:25 +0000 Received: from base (localhost [127.0.0.1]) by mail.nwl.cc (Postfix) with ESMTP id 4B109400E123; Thu, 22 Jan 2009 20:12:19 +0100 (CET) From: Phil Sutter To: Dmitry Torokhov Cc: linux-input@vger.kernel.org, Ralf Baechle , linux-mips@linux-mips.org, Florian Fainelli Subject: [PATCH 1/2] MIPS: rb532: prepare board support for rb532-button Date: Thu, 22 Jan 2009 20:12:07 +0100 X-Mailer: git-send-email 1.5.6.4 In-Reply-To: <1232651528-19870-1-git-send-email-n0-1@freewrt.org> References: <1232651528-19870-1-git-send-email-n0-1@freewrt.org> Message-Id: <20090122191219.4B109400E123@mail.nwl.cc> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21800 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: n0-1@freewrt.org Precedence: bulk X-list: linux-mips Content-Length: 1733 Lines: 59 Add a macro containing the S1 button GPIO pin index, as done for NAND and CompactFlash GPIO pins. Also remove gpio-keys specific device code and rename the button device to mach it's driver. Signed-off-by: Phil Sutter --- arch/mips/include/asm/mach-rc32434/gpio.h | 3 +++ arch/mips/rb532/devices.c | 19 +------------------ 2 files changed, 4 insertions(+), 18 deletions(-) diff --git a/arch/mips/include/asm/mach-rc32434/gpio.h b/arch/mips/include/asm/mach-rc32434/gpio.h index 3cb50d1..12ee8d5 100644 --- a/arch/mips/include/asm/mach-rc32434/gpio.h +++ b/arch/mips/include/asm/mach-rc32434/gpio.h @@ -80,6 +80,9 @@ struct rb532_gpio_reg { /* Compact Flash GPIO pin */ #define CF_GPIO_NUM 13 +/* S1 button GPIO (shared with UART0_SIN) */ +#define GPIO_BTN_S1 1 + extern void rb532_gpio_set_ilevel(int bit, unsigned gpio); extern void rb532_gpio_set_istat(int bit, unsigned gpio); extern void rb532_gpio_set_func(unsigned gpio); diff --git a/arch/mips/rb532/devices.c b/arch/mips/rb532/devices.c index 4a5f05b..7b585de 100644 --- a/arch/mips/rb532/devices.c +++ b/arch/mips/rb532/devices.c @@ -200,26 +200,9 @@ static struct platform_device rb532_led = { .id = -1, }; -static struct gpio_keys_button rb532_gpio_btn[] = { - { - .gpio = 1, - .code = BTN_0, - .desc = "S1", - .active_low = 1, - } -}; - -static struct gpio_keys_platform_data rb532_gpio_btn_data = { - .buttons = rb532_gpio_btn, - .nbuttons = ARRAY_SIZE(rb532_gpio_btn), -}; - static struct platform_device rb532_button = { - .name = "gpio-keys", + .name = "rb532-button", .id = -1, - .dev = { - .platform_data = &rb532_gpio_btn_data, - } }; static struct resource rb532_wdt_res[] = { -- 1.5.6.4 From n0-1@nwl.cc Thu Jan 22 19:13:01 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 22 Jan 2009 19:13:04 +0000 (GMT) Received: from orbit.nwl.cc ([91.121.169.95]:20943 "EHLO mail.nwl.cc") by ftp.linux-mips.org with ESMTP id S21103573AbZAVTMg (ORCPT ); Thu, 22 Jan 2009 19:12:36 +0000 Received: from base (localhost [127.0.0.1]) by mail.nwl.cc (Postfix) with ESMTP id F05AF400E106; Thu, 22 Jan 2009 20:12:30 +0100 (CET) From: Phil Sutter To: Dmitry Torokhov Cc: linux-input@vger.kernel.org, Ralf Baechle , linux-mips@linux-mips.org, Florian Fainelli Subject: Driver for the S1 button of rb532 Date: Thu, 22 Jan 2009 20:12:06 +0100 X-Mailer: git-send-email 1.5.6.4 Message-Id: <20090122191230.F05AF400E106@mail.nwl.cc> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21801 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: n0-1@freewrt.org Precedence: bulk X-list: linux-mips Content-Length: 439 Lines: 13 Hi, I've written a polled input device driver for the S1 button built into the Routerboard 532. Sadly, the gpio-keys driver can't be used, as it turns on the GPIO as interrupt source (which then has to stay configured for this use), which would render the serial console unusable as it uses the same pin in alternate function mode. I've split up the changes into two parts to divide BSP changes from the actual driver. Greetings, Phil From linux-mips@kernelport.de Fri Jan 23 19:40:09 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 23 Jan 2009 19:40:11 +0000 (GMT) Received: from mail.bugwerft.de ([212.112.241.193]:51842 "EHLO mail.bugwerft.de") by ftp.linux-mips.org with ESMTP id S21366036AbZAWTkJ (ORCPT ); Fri, 23 Jan 2009 19:40:09 +0000 Received: from localhost (localhost.localdomain [127.0.0.1]) by mail.bugwerft.de (Postfix) with ESMTP id 55AA48F849D for ; Fri, 23 Jan 2009 20:40:03 +0100 (CET) Received: from mail.bugwerft.de ([127.0.0.1]) by localhost (mail.bugwerft.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id GrqDKLTp9I9k for ; Fri, 23 Jan 2009 20:40:03 +0100 (CET) Received: from [10.1.1.26] (unknown [192.168.22.14]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.bugwerft.de (Postfix) with ESMTP id 9046A8F849C for ; Fri, 23 Jan 2009 20:40:02 +0100 (CET) Subject: Au1550 with kernel linux-2.6.28.1 From: Frank Neuber To: linux-mips@linux-mips.org Content-Type: text/plain Date: Fri, 23 Jan 2009 20:40:00 +0100 Message-Id: <1232739600.28527.289.camel@t60p> Mime-Version: 1.0 X-Mailer: Evolution 2.12.1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21802 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: linux-mips@kernelport.de Precedence: bulk X-list: linux-mips Content-Length: 955 Lines: 23 Hi List, at the moment I run a 2.6.16.11 on this core. Because of some trouble with the USB 2.0 EHCI controller (which is wired on the internal PCI bus) I am thinking about running a more recent kernel. It was easy to build linux-2.6.28.1 based on the db1550_defconfig using the mips_4KCle-gcc (gcc version 4.0.0 (DENX ELDK 4.1 4.0.0)) toolchain. But I see nothing on the serial console after starting the kernel. Some time ago (10 month I think) I was testing the head of the git mips kernel and the system was booting with some trouble on the pci bus but I was able so see someting on the serial console. A quick search on this list show me http://www.linux-mips.org/archives/linux-mips/2008-11/msg00099.html the last activity on the alchemy chip. I just want to ask who is working with the au1550 on a more recent kernel than 2.6.16.11. I'll start now with some early printk to solve booting problems and than we will see ..... Kind regards, FN From mano@roarinelk.homelinux.net Sat Jan 24 07:57:34 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 24 Jan 2009 07:57:40 +0000 (GMT) Received: from fnoeppeil36.netpark.at ([217.175.205.164]:34964 "EHLO roarinelk.homelinux.net") by ftp.linux-mips.org with ESMTP id S21366147AbZAXH5X (ORCPT ); Sat, 24 Jan 2009 07:57:23 +0000 Received: (qmail 22699 invoked from network); 24 Jan 2009 08:57:20 +0100 Received: from scarran.roarinelk.net (192.168.0.242) by fnoeppeil36.netpark.at with SMTP; 24 Jan 2009 08:57:20 +0100 Date: Sat, 24 Jan 2009 08:57:34 +0100 From: Manuel Lauss To: Frank Neuber Cc: linux-mips@linux-mips.org Subject: Re: Au1550 with kernel linux-2.6.28.1 Message-ID: <20090124085734.5b6b5c66@scarran.roarinelk.net> In-Reply-To: <1232739600.28527.289.camel@t60p> References: <1232739600.28527.289.camel@t60p> Organization: Private X-Mailer: Claws Mail 3.6.1 (GTK+ 2.14.5; i686-pc-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21803 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mano@roarinelk.homelinux.net Precedence: bulk X-list: linux-mips Content-Length: 1513 Lines: 37 Hallo Frank, On Fri, 23 Jan 2009 20:40:00 +0100 Frank Neuber wrote: > at the moment I run a 2.6.16.11 on this core. Because of some trouble > with the USB 2.0 EHCI controller (which is wired on the internal PCI > bus) I am thinking about running a more recent kernel. > It was easy to build linux-2.6.28.1 based on the db1550_defconfig using > the mips_4KCle-gcc (gcc version 4.0.0 (DENX ELDK 4.1 4.0.0)) toolchain. > But I see nothing on the serial console after starting the kernel. Some > time ago (10 month I think) I was testing the head of the git mips > kernel and the system was booting with some trouble on the pci bus but I > was able so see someting on the serial console. > > A quick search on this list show me > http://www.linux-mips.org/archives/linux-mips/2008-11/msg00099.html > the last activity on the alchemy chip. That stuff went in in time for 2.6.29-rc2, so it's unlikely to be the cause of your problems. > I just want to ask who is working with the au1550 on a more recent > kernel than 2.6.16.11. > I'll start now with some early printk to solve booting problems and than > we will see ..... I know of at least one person running 2.6.26 or .27 on a Au1550. You should start by throwing away the defconfig ;-). Create a new config with only au1x00 serial and serial console enabled and then add new devices one at a time and see where it breaks. (Btw, which board? I'd love to get my hands on other alchemy boards to test on). Thanks! Manuel Lauss From geert@linux-m68k.org Sat Jan 24 08:34:56 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 24 Jan 2009 08:34:58 +0000 (GMT) Received: from monty.telenet-ops.be ([195.130.132.56]:53383 "EHLO monty.telenet-ops.be") by ftp.linux-mips.org with ESMTP id S21366151AbZAXIex (ORCPT ); Sat, 24 Jan 2009 08:34:53 +0000 Received: from localhost (localhost.localdomain [127.0.0.1]) by monty.telenet-ops.be (Postfix) with SMTP id 5FB2C54007; Sat, 24 Jan 2009 09:34:52 +0100 (CET) Received: from anakin.of.borg (d54C15368.access.telenet.be [84.193.83.104]) by monty.telenet-ops.be (Postfix) with ESMTP id 40DD65403D; Sat, 24 Jan 2009 09:34:46 +0100 (CET) Received: from anakin.of.borg (localhost [127.0.0.1]) by anakin.of.borg (8.14.3/8.14.3/Debian-5) with ESMTP id n0O8Yj3l002485 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NOT); Sat, 24 Jan 2009 09:34:45 +0100 Received: from localhost (geert@localhost) by anakin.of.borg (8.14.3/8.14.3/Submit) with ESMTP id n0O8YiMS002373; Sat, 24 Jan 2009 09:34:44 +0100 X-Authentication-Warning: anakin.of.borg: geert owned process doing -bs Date: Sat, 24 Jan 2009 09:34:43 +0100 (CET) From: Geert Uytterhoeven To: Phil Sutter cc: Dmitry Torokhov , linux-input@vger.kernel.org, Ralf Baechle , linux-mips@linux-mips.org, Florian Fainelli Subject: Re: [PATCH 2/2] input: add driver for S1 button of rb532 In-Reply-To: <20090122191216.15285400E106@mail.nwl.cc> Message-ID: References: <1232651528-19870-1-git-send-email-n0-1@freewrt.org> <1232651528-19870-2-git-send-email-n0-1@freewrt.org> <20090122191216.15285400E106@mail.nwl.cc> MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21804 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: geert@linux-m68k.org Precedence: bulk X-list: linux-mips Content-Length: 1185 Lines: 27 On Thu, 22 Jan 2009, Phil Sutter wrote: > Mikrotik's Routerboard 532 has two builtin buttons, from which one > triggers a hardware reset. The other one is accessible through GPIO pin > 1. Sadly, this pin is being multiplexed with UART0 input, so enabling it > as interrupt source (as implied by the gpio-keys driver) is not possible > unless UART0 has been turned off. The later one though is a rather bad > idea as the Routerboard is an embedded device with only a single serial > port, so it's almost always used as serial console device. > > This patch adds a driver based on INPUT_POLLDEV, which disables the UART > and reconfigures GPIO pin 1 temporarily while reading the button state. > This procedure works fine and has been tested as part of another, > unpublished driver for this device. What happens when you receive UART input while the UART is disabled? Is it lost? Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds From linux-mips@kernelport.de Sat Jan 24 08:57:38 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 24 Jan 2009 08:57:40 +0000 (GMT) Received: from mail.bugwerft.de ([212.112.241.193]:29134 "EHLO mail.bugwerft.de") by ftp.linux-mips.org with ESMTP id S21366144AbZAXI5i (ORCPT ); Sat, 24 Jan 2009 08:57:38 +0000 Received: from localhost (localhost.localdomain [127.0.0.1]) by mail.bugwerft.de (Postfix) with ESMTP id A6D068F849D; Sat, 24 Jan 2009 09:57:32 +0100 (CET) Received: from mail.bugwerft.de ([127.0.0.1]) by localhost (mail.bugwerft.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 3Xe2-7LZt6En; Sat, 24 Jan 2009 09:57:31 +0100 (CET) Received: from [10.1.1.26] (unknown [192.168.22.14]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.bugwerft.de (Postfix) with ESMTP id 68CD68F849C; Sat, 24 Jan 2009 09:57:30 +0100 (CET) Subject: Re: Au1550 with kernel linux-2.6.28.1 From: Frank Neuber To: Manuel Lauss Cc: linux-mips@linux-mips.org In-Reply-To: <20090124085734.5b6b5c66@scarran.roarinelk.net> References: <1232739600.28527.289.camel@t60p> <20090124085734.5b6b5c66@scarran.roarinelk.net> Content-Type: text/plain Date: Sat, 24 Jan 2009 09:57:28 +0100 Message-Id: <1232787448.28527.302.camel@t60p> Mime-Version: 1.0 X-Mailer: Evolution 2.12.1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21805 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: linux-mips@kernelport.de Precedence: bulk X-list: linux-mips Content-Length: 1570 Lines: 40 Hi Manuel, thank you for your quick response. Am Samstag, den 24.01.2009, 08:57 +0100 schrieb Manuel Lauss: > > I just want to ask who is working with the au1550 on a more recent > > kernel than 2.6.16.11. > > I'll start now with some early printk to solve booting problems and than > > we will see ..... > > I know of at least one person running 2.6.26 or .27 on a Au1550. > You should start by throwing away the defconfig ;-). Create a new > config with only au1x00 serial and serial console enabled and then add > new devices one at a time and see where it breaks. Yestoday I tested the earlyprintk stuff witout luck :-( I simply added this CMDLINE earlycon=uart,mmio,0x11100000,115200n8 console=ttyS0,115200n8 panic=1 The drivers/serial/8250_early.o is build in the kernel but without adding CONFIG_EARLY_PRINTK or CONFIG_SYS_HAS_EARLY_PRINTK. Maybe this is the problem. On the running kernel I see this. Serial: 8250/16550 driver $Revision: 1.90 $ 5 ports, IRQ sharing enabled serial8250.7: ttyS0 at MMIO 0x11100000 (irq = 0) is a 16550A serial8250.7: ttyS1 at MMIO 0x11200000 (irq = 8) is a 16550A serial8250.7: ttyS2 at MMIO 0x11400000 (irq = 9) is a 16550A The console is console=ttyS0,115200n8 .... Now I'll go more deep into the kernel. > > (Btw, which board? I'd love to get my hands on other alchemy boards to > test on). It is a customer board not available on the market. It is possible for you to connect me to this person. Maybe we can share some know how. At the moment I work on USB Analog/DVB stuff more deep on MIPS. Kind Regards, Frank From yoichi_yuasa@tripeaks.co.jp Sat Jan 24 13:15:48 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 24 Jan 2009 13:15:50 +0000 (GMT) Received: from mow300.po.2iij.NET ([210.128.50.200]:30892 "EHLO mow.po.2iij.net") by ftp.linux-mips.org with ESMTP id S21365744AbZAXNPs (ORCPT ); Sat, 24 Jan 2009 13:15:48 +0000 Received: by mow.po.2iij.net (mow300) id n0ODFiYZ003613; Sat, 24 Jan 2009 22:15:44 +0900 Received: from delta (133.6.30.125.dy.iij4u.or.jp [125.30.6.133]) by mbox.po.2iij.net (po-mbox304) id n0ODFgML029203 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NOT); Sat, 24 Jan 2009 22:15:43 +0900 Date: Sat, 24 Jan 2009 22:15:42 +0900 From: Yoichi Yuasa To: Ralf Baechle Cc: yoichi_yuasa@tripeaks.co.jp, linux-mips Subject: [PATCH][MIPS] fix oops in r4k_dma_cache_inv Message-Id: <20090124221542.bcc6c19f.yoichi_yuasa@tripeaks.co.jp> Organization: TriPeaks Corporation X-Mailer: Sylpheed 2.4.8 (GTK+ 2.12.9; i486-pc-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21806 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: yoichi_yuasa@tripeaks.co.jp Precedence: bulk X-list: linux-mips Content-Length: 2703 Lines: 72 This patch adds alignment for cache operation address in r4k_dma_cache_inv(). The following oops is fixed by it. Unhandled kernel unaligned access or invalid instruction[#1]: Cpu 0 $ 0 : 00000000 9000c400 8f9a9fff 803e0000 $ 4 : 8f9a9000 00001000 00000001 00000002 $ 8 : 00000000 00000000 8f998084 8f986600 $12 : 00000000 00000000 00000008 00000008 $16 : 8f9a9000 8f9a3500 00000000 00000001 $20 : 00000002 803e0000 803d0000 00000000 $24 : 00000000 80240000 $28 : 8f81a000 8f81b708 803d0000 8009560c Hi : 10623d20 Lo : 4fdf2cc8 epc : 80098470 r4k_dma_cache_inv+0x28/0x64 Not tainted ra : 8009560c dma_map_sg+0xf8/0x14c Status: 9000c402 KERNEL EXL Cause : 00800010 BadVA : 8f9a9fff PrId : 000028a0 (Nevada) Modules linked in: Process swapper (pid: 1, threadinfo=8f81a000, task=8f820000, tls=00000000) Stack : 8f967424 8f967510 8f9a03ee 8f99e140 8f999300 8f998074 8f998000 00000003 803e0000 80253a38 8f967424 8f967510 80370000 8024e344 00000000 8f9a3580 00000008 8f81b770 8f998074 8f99e140 802389fc 8f999458 8f998000 80253a38 80253db4 80253cbc 800df150 00000000 80257af8 8f9a0360 8f99e140 9000c401 8f9a0360 8f99e140 8f986600 8f9674a8 802391ac 8f81b844 8f967400 80224788 ... Call Trace: [<80098470>] r4k_dma_cache_inv+0x28/0x64 [<8009560c>] dma_map_sg+0xf8/0x14c [<8024e344>] ata_qc_issue+0x1ec/0x308 [<80253db4>] ata_scsi_translate+0x134/0x1e8 [<802391ac>] scsi_dispatch_cmd+0x10c/0x270 [<8024028c>] scsi_request_fn+0x28c/0x53c Signed-off-by: Yoichi Yuasa diff -pruN -X /home/yuasa/Memo/dontdiff linux-orig/arch/mips/mm/c-r4k.c linux/arch/mips/mm/c-r4k.c --- linux-orig/arch/mips/mm/c-r4k.c 2009-01-15 10:27:30.170434561 +0900 +++ linux/arch/mips/mm/c-r4k.c 2009-01-15 17:06:07.326434524 +0900 @@ -612,6 +612,8 @@ static void r4k_dma_cache_wback_inv(unsi static void r4k_dma_cache_inv(unsigned long addr, unsigned long size) { + unsigned long lsize = cpu_dcache_line_size(); + /* Catch bad driver code */ BUG_ON(size == 0); @@ -620,7 +622,8 @@ static void r4k_dma_cache_inv(unsigned l r4k_blast_scache(); else { cache_op(Hit_Writeback_Inv_SD, addr); - cache_op(Hit_Writeback_Inv_SD, addr + size - 1); + cache_op(Hit_Writeback_Inv_SD, + (addr + size - 1) & ~(lsize - 1)); blast_inv_scache_range(addr, addr + size); } return; @@ -631,7 +634,7 @@ static void r4k_dma_cache_inv(unsigned l } else { R4600_HIT_CACHEOP_WAR_IMPL; cache_op(Hit_Writeback_Inv_D, addr); - cache_op(Hit_Writeback_Inv_D, addr + size - 1); + cache_op(Hit_Writeback_Inv_D, (addr + size - 1) & ~(lsize - 1)); blast_inv_dcache_range(addr, addr + size); } From n0-1@nwl.cc Sat Jan 24 14:17:12 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 24 Jan 2009 14:17:14 +0000 (GMT) Received: from orbit.nwl.cc ([91.121.169.95]:26289 "EHLO mail.nwl.cc") by ftp.linux-mips.org with ESMTP id S21366074AbZAXORM (ORCPT ); Sat, 24 Jan 2009 14:17:12 +0000 Received: from mail.nwl.cc (localhost [127.0.0.1]) by mail.nwl.cc (Postfix) with ESMTP id D6A3F4E66C; Sat, 24 Jan 2009 15:17:05 +0100 (CET) Received: from nuty (localhost [127.0.0.1]) by mail.nwl.cc (Postfix) with ESMTP id 96C694CEAE; Sat, 24 Jan 2009 15:17:05 +0100 (CET) Date: Sat, 24 Jan 2009 15:20:27 +0100 From: Phil Sutter To: Geert Uytterhoeven Cc: Dmitry Torokhov , linux-input@vger.kernel.org, Ralf Baechle , linux-mips@linux-mips.org, Florian Fainelli Subject: Re: [PATCH 2/2] input: add driver for S1 button of rb532 Mail-Followup-To: Geert Uytterhoeven , Dmitry Torokhov , linux-input@vger.kernel.org, Ralf Baechle , linux-mips@linux-mips.org, Florian Fainelli References: <1232651528-19870-1-git-send-email-n0-1@freewrt.org> <1232651528-19870-2-git-send-email-n0-1@freewrt.org> <20090122191216.15285400E106@mail.nwl.cc> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.11 Message-Id: <20090124141705.96C694CEAE@mail.nwl.cc> X-Virus-Scanned: ClamAV using ClamSMTP Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21807 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: n0-1@freewrt.org Precedence: bulk X-list: linux-mips Content-Length: 1133 Lines: 27 Hi, On Sat, Jan 24, 2009 at 09:34:43AM +0100, Geert Uytterhoeven wrote: > What happens when you receive UART input while the UART is disabled? Is it > lost? Yes, the input is lost, as well as any output sent by the device while UART0 is disabled. I've tested this adding a msleep() of 5s in between the calls to set_latch_u5() and increasing the delay between polls to 10s. I've tried to reproduce this behaviour without the changes from above using a loop flooding the output of the serial console with increasing numbers, with somehow strange results. Instead of missing some output, occasionally the log shows additional characters (some non-printable). Also (seldomly) digits are replaced by other chars (also not necesarily printable). So I can at least assume the two drivers interfere with each other, which could lead to bad results when using the UART for more advanced stuff. Although it may be possible to introduce some kind of locking for the serial output, I doubt this can be done with the input part, as the device is turned off while polling so data shouldn't even reach the device. Any ideas? Greetings, Phil From bzolnier@gmail.com Sat Jan 24 14:21:15 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 24 Jan 2009 14:21:17 +0000 (GMT) Received: from mu-out-0910.google.com ([209.85.134.187]:53650 "EHLO mu-out-0910.google.com") by ftp.linux-mips.org with ESMTP id S21366094AbZAXOVP (ORCPT ); Sat, 24 Jan 2009 14:21:15 +0000 Received: by mu-out-0910.google.com with SMTP id w9so3616553mue.4 for ; Sat, 24 Jan 2009 06:21:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:subject:date :user-agent:cc:references:in-reply-to:mime-version:content-type :content-transfer-encoding:content-disposition:message-id; bh=9b+KxPgu2K2+5HXTswSJV9yKM27bxsHBCtu+yb3Ekxc=; b=xsDyQFyR8DIyc7L9XhrQWnPc7ceIJai43F0jCoHi2OwDwnAAC8nSeAI2LL7+H7Fe5u ZclSosu/TYF8GQlghKpjedz9Tzoyi6g2VdiF0q1pyiT+c4sfijDAaTNjCg+1Zq16H4o0 RauJrhp8hnTRYoWhxo9w1OIzrRmSnnaPG+fNE= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:subject:date:user-agent:cc:references:in-reply-to :mime-version:content-type:content-transfer-encoding :content-disposition:message-id; b=KdLnbIeoIGH3+L/8RoXPr798SG3Z5fdmMdka1I3csfrERTlB4yi5qF0QKidE63gMGE qeeyKI+ZVuZChbjpWHJ7n1rerO1Tme7cgrd1ky6Wk7YIm32ZLpTS9s7TxI8C48t9ZqBx gJPXjaOH1DMrcS0ST8OSxZ6oELg+q7vRHUp30= Received: by 10.103.243.9 with SMTP id v9mr882072mur.91.1232806874220; Sat, 24 Jan 2009 06:21:14 -0800 (PST) Received: from localhost.localdomain (chello089077051219.chello.pl [89.77.51.219]) by mx.google.com with ESMTPS id 23sm10880688mun.28.2009.01.24.06.21.12 (version=TLSv1/SSLv3 cipher=RC4-MD5); Sat, 24 Jan 2009 06:21:13 -0800 (PST) From: Bartlomiej Zolnierkiewicz To: Atsushi Nemoto Subject: Re: [PATCH] tx4939ide: typo fix and minor cleanup Date: Sat, 24 Jan 2009 15:10:01 +0100 User-Agent: KMail/1.10.3 (Linux/2.6.29-rc2-next-20090123; KDE/4.1.3; i686; ; ) Cc: linux-ide@vger.kernel.org, sshtylyov@ru.mvista.com, linux-mips@linux-mips.org References: <1232374225-5325-1-git-send-email-anemo@mba.ocn.ne.jp> In-Reply-To: <1232374225-5325-1-git-send-email-anemo@mba.ocn.ne.jp> MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit Content-Disposition: inline Message-Id: <200901241510.01660.bzolnier@gmail.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21808 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: bzolnier@gmail.com Precedence: bulk X-list: linux-mips Content-Length: 318 Lines: 8 On Monday 19 January 2009, Atsushi Nemoto wrote: > The bcount is greater than 0 and less than or equal to 0x10000. > Thus '(bcount & 0xffff) == 0x0000' can be simplified as 'bcount == 0x10000'. > > Suggested-by: Sergei Shtylyov > Signed-off-by: Atsushi Nemoto applied From ralf@h5.dl5rb.org.uk Sat Jan 24 19:11:03 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 24 Jan 2009 19:11:05 +0000 (GMT) Received: from h5.dl5rb.org.uk ([81.2.74.5]:34199 "EHLO h5.dl5rb.org.uk") by ftp.linux-mips.org with ESMTP id S21366177AbZAXTK7 (ORCPT ); Sat, 24 Jan 2009 19:10:59 +0000 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id n0OJAvhY014533; Sat, 24 Jan 2009 19:10:58 GMT Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id n0OJAtxV014518; Sat, 24 Jan 2009 19:10:55 GMT Date: Sat, 24 Jan 2009 19:10:55 +0000 From: Ralf Baechle To: Yoichi Yuasa Cc: linux-mips Subject: Re: [PATCH][MIPS] fix oops in r4k_dma_cache_inv Message-ID: <20090124191055.GA29966@linux-mips.org> References: <20090124221542.bcc6c19f.yoichi_yuasa@tripeaks.co.jp> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20090124221542.bcc6c19f.yoichi_yuasa@tripeaks.co.jp> User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21809 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Content-Length: 1841 Lines: 51 On Sat, Jan 24, 2009 at 10:15:42PM +0900, Yoichi Yuasa wrote: Patch looks ok - but I think we also have to assume that the starting address of the range might be miss-aligned, so how about this patch? Ralf Signed-off-by: Ralf Baechle diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index 56290a7..c43f4b2 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -619,8 +619,20 @@ static void r4k_dma_cache_inv(unsigned long addr, unsigned long size) if (size >= scache_size) r4k_blast_scache(); else { - cache_op(Hit_Writeback_Inv_SD, addr); - cache_op(Hit_Writeback_Inv_SD, addr + size - 1); + unsigned long lsize = cpu_scache_line_size(); + unsigned long almask = ~(lsize - 1); + + /* + * There is no clearly documented alignment requirement + * for the cache instruction on MIPS processors and + * some processors, among them the RM5200 and RM7000 + * QED processors will throw an address error for cache + * hit ops with insufficient alignment. Solved by + * aligning the address to cache line size. + */ + cache_op(Hit_Writeback_Inv_SD, addr & almask); + cache_op(Hit_Writeback_Inv_SD, + (addr + size - 1) & almask); blast_inv_scache_range(addr, addr + size); } return; @@ -629,9 +641,12 @@ static void r4k_dma_cache_inv(unsigned long addr, unsigned long size) if (cpu_has_safe_index_cacheops && size >= dcache_size) { r4k_blast_dcache(); } else { + unsigned long lsize = cpu_dcache_line_size(); + unsigned long almask = ~(lsize - 1); + R4600_HIT_CACHEOP_WAR_IMPL; - cache_op(Hit_Writeback_Inv_D, addr); - cache_op(Hit_Writeback_Inv_D, addr + size - 1); + cache_op(Hit_Writeback_Inv_D, addr & almask); + cache_op(Hit_Writeback_Inv_D, (addr + size - 1) & almask); blast_inv_dcache_range(addr, addr + size); } From frank.neuber@kernelport.de Sat Jan 24 23:20:36 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 24 Jan 2009 23:20:38 +0000 (GMT) Received: from mail.bugwerft.de ([212.112.241.193]:37595 "EHLO mail.bugwerft.de") by ftp.linux-mips.org with ESMTP id S21366305AbZAXXUg (ORCPT ); Sat, 24 Jan 2009 23:20:36 +0000 Received: from localhost (localhost.localdomain [127.0.0.1]) by mail.bugwerft.de (Postfix) with ESMTP id 84C1E8F849D; Sun, 25 Jan 2009 00:20:30 +0100 (CET) Received: from mail.bugwerft.de ([127.0.0.1]) by localhost (mail.bugwerft.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id uUijuvTGdGZo; Sun, 25 Jan 2009 00:20:29 +0100 (CET) Received: from [10.1.1.26] (ip-77-25-15-184.web.vodafone.de [77.25.15.184]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.bugwerft.de (Postfix) with ESMTP id 82BC78F849C; Sun, 25 Jan 2009 00:20:27 +0100 (CET) Subject: Re: Au1550 with kernel linux-2.6.28.1 From: Frank Neuber To: Manuel Lauss Cc: linux-mips@linux-mips.org In-Reply-To: <1232787448.28527.302.camel@t60p> References: <1232739600.28527.289.camel@t60p> <20090124085734.5b6b5c66@scarran.roarinelk.net> <1232787448.28527.302.camel@t60p> Content-Type: text/plain Date: Sun, 25 Jan 2009 00:20:24 +0100 Message-Id: <1232839224.28527.336.camel@t60p> Mime-Version: 1.0 X-Mailer: Evolution 2.12.1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21810 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: frank.neuber@kernelport.de Precedence: bulk X-list: linux-mips Content-Length: 1899 Lines: 71 Hi Manuel, after trying the standard early printk without luck I implemented my own: --- kernel/printk.c.orig 2009-01-24 23:48:08.000000000 +0100 +++ kernel/printk.c 2009-01-24 23:49:42.000000000 +0100 @@ -481,8 +481,30 @@ _call_console_drivers(start_print, end, msg_level); } +#include +#include + +void serial_putc (const char c) +{ + volatile u32 *uart_lsr = (volatile u32*)(UART0_ADDR+UART_LSR); + volatile u32 *uart_tx = (volatile u32*)(UART0_ADDR+UART_TX); + + if (c == '\n') serial_putc ('\r'); + + /* Wait for fifo to shift out some bytes */ + while((*uart_lsr&UART_LSR_THRE)==0); + + *uart_tx = (u32)c; +} + static void emit_log_char(char c) { +#if 1 + if (c == '\n'){ + serial_putc('\r'); + } + serial_putc(c); +#endif LOG_BUF(log_end) = c; log_end++; if (log_end - log_start > log_buf_len) The same result, I see nothing :-( This means I run into trouble in the very early assembler part of the kernel. I know the ARM kernel has some debug features implemented (using the serial port). Has the mips kernel a comparable debug possebility? I striped down the defconfig as you sad and start the kernel using uboot: tc# bootm 0x80500000 ## Booting image at 80500000 ... Image Name: Linux-2.6.28.1 Created: 2009-01-24 21:39:57 UTC Image Type: MIPS Linux Kernel Image (gzip compressed) Data Size: 894213 Bytes = 873.3 kB Load Address: 80100000 Entry Point: 80104690 Verifying Checksum ... OK Uncompressing Kernel Image ... OK Starting kernel ... Could the entry point be the problem? He is very close to the load address. Because I have no JTAG for mips it is not easy to check what is going on here .... Now I have no idea what can I do next ... Kind Regards, Frank From dvomlehn@cisco.com Sun Jan 25 01:59:50 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 25 Jan 2009 01:59:53 +0000 (GMT) Received: from rtp-iport-1.cisco.com ([64.102.122.148]:33455 "EHLO rtp-iport-1.cisco.com") by ftp.linux-mips.org with ESMTP id S21366344AbZAYB7u convert rfc822-to-8bit (ORCPT ); Sun, 25 Jan 2009 01:59:50 +0000 X-IronPort-AV: E=Sophos;i="4.37,320,1231113600"; d="scan'208";a="34805453" Received: from rtp-dkim-1.cisco.com ([64.102.121.158]) by rtp-iport-1.cisco.com with ESMTP; 25 Jan 2009 01:59:43 +0000 Received: from rtp-core-2.cisco.com (rtp-core-2.cisco.com [64.102.124.13]) by rtp-dkim-1.cisco.com (8.12.11/8.12.11) with ESMTP id n0P1xhsb026661; Sat, 24 Jan 2009 20:59:43 -0500 Received: from xbh-rtp-201.amer.cisco.com (xbh-rtp-201.cisco.com [64.102.31.12]) by rtp-core-2.cisco.com (8.13.8/8.13.8) with ESMTP id n0P1xhgx021990; Sun, 25 Jan 2009 01:59:43 GMT Received: from xmb-rtp-218.amer.cisco.com ([64.102.31.117]) by xbh-rtp-201.amer.cisco.com with Microsoft SMTPSVC(6.0.3790.1830); Sat, 24 Jan 2009 20:59:43 -0500 X-MimeOLE: Produced By Microsoft Exchange V6.5 Content-class: urn:content-classes:message MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT Subject: 2.6.28 will not boot on 24K processor, ebase incorrectly modified in set_uncached_handler Date: Sat, 24 Jan 2009 20:59:42 -0500 Message-ID: X-MS-Has-Attach: X-MS-TNEF-Correlator: Thread-Topic: 2.6.28 will not boot on 24K processor, ebase incorrectly modified in set_uncached_handler Thread-Index: Acl+kJaro0S6RTnZTS6pVkaviRzJAg== From: "David VomLehn (dvomlehn)" To: Cc: "Dezhong Diao (dediao)" , "Victor Williams Jr (williavi)" , "Michael Sundius -X (msundius - Yoh Services LLC at Cisco)" X-OriginalArrivalTime: 25 Jan 2009 01:59:43.0592 (UTC) FILETIME=[97526680:01C97E90] DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; l=676; t=1232848783; x=1233712783; c=relaxed/simple; s=rtpdkim1001; h=Content-Type:From:Subject:Content-Transfer-Encoding:MIME-Version; d=cisco.com; i=dvomlehn@cisco.com; z=From:=20=22David=20VomLehn=20(dvomlehn)=22=20 |Subject:=202.6.28=20will=20not=20boot=20on=2024K=20process or,=20ebase=20incorrectly=20modified=20in=20set_uncached_han dler |Sender:=20 |To:=20; bh=TLeCNFAsy+bYEhPXFDWM8OyPL5qx09X8z2ozNv/p5Vg=; b=OOT3xTMuZNY7PPSRLuMZsb3tE0n6NGn4eTklXKU+qtu/YkrrgfNgU/dKS5 f6tb9DbWnntTaKpo7iS9JXWkVz82t9YPLQwzvq1D3xsXfPnBA4u6IwVmKrKD nOqm9ahLkg; Authentication-Results: rtp-dkim-1; header.From=dvomlehn@cisco.com; dkim=pass ( sig from cisco.com/rtpdkim1001 verified; ); Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21811 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dvomlehn@cisco.com Precedence: bulk X-list: linux-mips Content-Length: 654 Lines: 22 The 2.6.28 kernel dies in memcpy when called from set_vi_srs_handler on a 24K processor. The problem is that ebase has an invalid value. The original value of ebase comes from a bootmem allocation, but the following code in set_uncached_handler takes a perfectly good kseg0 address and turns it into an invalid kseg1 address. if (cpu_has_mips_r2) ebase += (read_c0_ebase() & 0x3ffff000); This code was added in commit 566f74f6b2f8b85d5b8d6caaf97e5672cecd3e3e. I have no idea why ebase needs to be modified at all, so I have no patch to offer. When I removed these two lines, my kernel booted to a shell prompt. -- David VomLehn, dvomlehn@cisco.com From frank.neuber@kernelport.de Sun Jan 25 08:20:26 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 25 Jan 2009 08:20:28 +0000 (GMT) Received: from mail.bugwerft.de ([212.112.241.193]:54725 "EHLO mail.bugwerft.de") by ftp.linux-mips.org with ESMTP id S21366115AbZAYIU0 (ORCPT ); Sun, 25 Jan 2009 08:20:26 +0000 Received: from localhost (localhost.localdomain [127.0.0.1]) by mail.bugwerft.de (Postfix) with ESMTP id 735338F849D; Sun, 25 Jan 2009 09:20:20 +0100 (CET) Received: from mail.bugwerft.de ([127.0.0.1]) by localhost (mail.bugwerft.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id QDvjJff10iPd; Sun, 25 Jan 2009 09:20:20 +0100 (CET) Received: from [10.1.1.26] (ip-77-25-15-184.web.vodafone.de [77.25.15.184]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.bugwerft.de (Postfix) with ESMTP id D44038F849C; Sun, 25 Jan 2009 09:20:18 +0100 (CET) Subject: Re: Au1550 with kernel linux-2.6.28.1 (SOLVED) From: Frank Neuber To: Manuel Lauss Cc: linux-mips@linux-mips.org In-Reply-To: <1232839224.28527.336.camel@t60p> References: <1232739600.28527.289.camel@t60p> <20090124085734.5b6b5c66@scarran.roarinelk.net> <1232787448.28527.302.camel@t60p> <1232839224.28527.336.camel@t60p> Content-Type: text/plain Date: Sun, 25 Jan 2009 09:20:16 +0100 Message-Id: <1232871616.28527.347.camel@t60p> Mime-Version: 1.0 X-Mailer: Evolution 2.12.1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21812 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: frank.neuber@kernelport.de Precedence: bulk X-list: linux-mips Content-Length: 1252 Lines: 33 Hi List, after a sleepness nigth I got an idea .... Because I need an uImage I had to build a Image first. The buildprocess of the kernel call this wrong line mips_4KCle-objcopy --remove-section=.reginfo vmlinux arch/mips/boot/Image if I add this rule in the Makefile $(obj)/Image: $(VMLINUX) FORCE $(call if_changed,objcopy) @echo ' Kernel: $@ is ready' On older kernelversions this works well! The rigth one is this: mips_4KCle-objcopy -O binary -R .note -R .comment -S vmlinux arch/mips/boot/Image I typed the last steps by hand for now and it works gzip -f -9 < arch/mips/boot/Image > arch/mips/boot/zImage /bin/sh /tmp/linux-2.6.28.1/scripts/mkuboot.sh -A mips -O linux -T kernel -C gzip -a 0x80100000 -e 0x80104690 -n 'Linux-2.6.28.1' -d arch/mips/boot/zImage uImage (keep in mind the -a 0x80100000 -e 0x80104690 parameters are greped from vmlinux with TEXT_ADDR := $(shell awk '/_text/ { printf "0x%s", $$1 ; exit }' < $(TOPDIR)/System.map) ENTRY_ADDR := $(shell awk '/kernel_entry/ { printf "0x%s", $$1 ; exit }' < $(TOPDIR)/System.map) ) Than I can see my first early printk messages :-) huhuuu Now I can work on. BTW: why is uImage not supported by the kernel build system for MIPS? Regards, Frank From kevink@paralogos.com Sun Jan 25 10:18:29 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 25 Jan 2009 10:18:31 +0000 (GMT) Received: from aux-209-217-49-36.oklahoma.net ([209.217.49.36]:14084 "EHLO proteus.paralogos.com") by ftp.linux-mips.org with ESMTP id S21365077AbZAYKS3 (ORCPT ); Sun, 25 Jan 2009 10:18:29 +0000 Received: from [192.168.236.58] ([217.109.65.213]) by proteus.paralogos.com (8.9.3/8.9.3) with ESMTP id EAA19667; Sun, 25 Jan 2009 04:50:55 -0600 Message-ID: <497C3C6F.3000209@paralogos.com> Date: Sun, 25 Jan 2009 04:18:23 -0600 From: "Kevin D. Kissell" User-Agent: Thunderbird 2.0.0.19 (Windows/20081209) MIME-Version: 1.0 To: "David VomLehn (dvomlehn)" CC: linux-mips@linux-mips.org, "Dezhong Diao (dediao)" , "Victor Williams Jr (williavi)" , "Michael Sundius -X (msundius - Yoh Services LLC at Cisco)" Subject: Re: 2.6.28 will not boot on 24K processor, ebase incorrectly modified in set_uncached_handler References: In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21813 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: kevink@paralogos.com Precedence: bulk X-list: linux-mips Content-Length: 1038 Lines: 27 David VomLehn (dvomlehn) wrote: > The 2.6.28 kernel dies in memcpy when called from set_vi_srs_handler on > a > 24K processor. The problem is that ebase has an invalid value. The > original > value of ebase comes from a bootmem allocation, but the following code > in > set_uncached_handler takes a perfectly good kseg0 address and turns it > into > an invalid kseg1 address. > > if (cpu_has_mips_r2) > ebase += (read_c0_ebase() & 0x3ffff000); > > This code was added in commit 566f74f6b2f8b85d5b8d6caaf97e5672cecd3e3e. > I remember worrying about why it was "+=" and not "=" when others had problems with that patch. See the thread "NXP STB225 board support" from January 8 or so. When I asked about that, I got a comment that the add operation was correct, but that patch *should* have said "uncached_ebase += (read_c0_ebase() & 0x3ffff000);" I guess uncache_ebase is assumed to contain something interesting in some non-address bits. Try pre-pending "uncached_" to that "ebase"... Regards, Kevin K. From mcdonald.shane@gmail.com Sun Jan 25 12:27:17 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 25 Jan 2009 12:27:20 +0000 (GMT) Received: from yw-out-1718.google.com ([74.125.46.152]:21412 "EHLO yw-out-1718.google.com") by ftp.linux-mips.org with ESMTP id S21365855AbZAYM1R (ORCPT ); Sun, 25 Jan 2009 12:27:17 +0000 Received: by yw-out-1718.google.com with SMTP id 9so2088913ywk.24 for ; Sun, 25 Jan 2009 04:27:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:in-reply-to:references :date:message-id:subject:from:to:cc:content-type :content-transfer-encoding; bh=3yPgh+ysdcwafuomWMITlbHSV9KEeIMsGEOYZFlL3pY=; b=mrFRoR9aOuNI4J4xkWJmdvKTVFcQ2Lw+PYTktmV3BZJK/n4LdIF20ntzxZTW0kYCJ2 Ut8k3yfpPP3I5OtpnHK1c1Hs0vkgGo/8NTll066ItkFesAVspP8IVHjq327/sJB2AzO7 URIi+RHisDKgmV57nCT2dNRjK3AN3fyt1eivk= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type:content-transfer-encoding; b=nVQXxUhgmqqWhUYRyQoMBz9Hgvuk/w8pb+CGqnlvtO71gjkeGMjR+KVzjzkHmKaAiQ 1O212p9xBDJdIr418nIRc6XeckyX1Bqi/cjSfzBwtlu7XGim5bk8VWvKqhG9Spuy0Yt8 cxG178kwZumjDk7kEfpvB+F9M0NxdISq4hSrs= MIME-Version: 1.0 Received: by 10.90.96.1 with SMTP id t1mr533603agb.73.1232886436246; Sun, 25 Jan 2009 04:27:16 -0800 (PST) In-Reply-To: <20090124191055.GA29966@linux-mips.org> References: <20090124221542.bcc6c19f.yoichi_yuasa@tripeaks.co.jp> <20090124191055.GA29966@linux-mips.org> Date: Sun, 25 Jan 2009 06:27:16 -0600 Message-ID: Subject: Re: [PATCH][MIPS] fix oops in r4k_dma_cache_inv From: Shane McDonald To: Ralf Baechle Cc: Yoichi Yuasa , linux-mips Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21814 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mcdonald.shane@gmail.com Precedence: bulk X-list: linux-mips Content-Length: 2644 Lines: 56 On Sat, Jan 24, 2009 at 1:10 PM, Ralf Baechle wrote: > On Sat, Jan 24, 2009 at 10:15:42PM +0900, Yoichi Yuasa wrote: > > Patch looks ok - but I think we also have to assume that the starting > address of the range might be miss-aligned, so how about this patch? > > Ralf > > Signed-off-by: Ralf Baechle > > diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c > index 56290a7..c43f4b2 100644 > --- a/arch/mips/mm/c-r4k.c > +++ b/arch/mips/mm/c-r4k.c > @@ -619,8 +619,20 @@ static void r4k_dma_cache_inv(unsigned long addr, unsigned long size) > if (size >= scache_size) > r4k_blast_scache(); > else { > - cache_op(Hit_Writeback_Inv_SD, addr); > - cache_op(Hit_Writeback_Inv_SD, addr + size - 1); > + unsigned long lsize = cpu_scache_line_size(); > + unsigned long almask = ~(lsize - 1); > + > + /* > + * There is no clearly documented alignment requirement > + * for the cache instruction on MIPS processors and > + * some processors, among them the RM5200 and RM7000 > + * QED processors will throw an address error for cache > + * hit ops with insufficient alignment. Solved by > + * aligning the address to cache line size. > + */ > + cache_op(Hit_Writeback_Inv_SD, addr & almask); > + cache_op(Hit_Writeback_Inv_SD, > + (addr + size - 1) & almask); > blast_inv_scache_range(addr, addr + size); > } > return; > @@ -629,9 +641,12 @@ static void r4k_dma_cache_inv(unsigned long addr, unsigned long size) > if (cpu_has_safe_index_cacheops && size >= dcache_size) { > r4k_blast_dcache(); > } else { > + unsigned long lsize = cpu_dcache_line_size(); > + unsigned long almask = ~(lsize - 1); > + > R4600_HIT_CACHEOP_WAR_IMPL; > - cache_op(Hit_Writeback_Inv_D, addr); > - cache_op(Hit_Writeback_Inv_D, addr + size - 1); > + cache_op(Hit_Writeback_Inv_D, addr & almask); > + cache_op(Hit_Writeback_Inv_D, (addr + size - 1) & almask); > blast_inv_dcache_range(addr, addr + size); > } > This patch resolves the oops on my RM7035C-based board. Tested-by: Shane McDonald From yoichi_yuasa@tripeaks.co.jp Sun Jan 25 12:31:51 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 25 Jan 2009 12:31:53 +0000 (GMT) Received: from mow300.po.2iij.NET ([210.128.50.200]:54474 "EHLO mow.po.2iij.net") by ftp.linux-mips.org with ESMTP id S21364913AbZAYMbv (ORCPT ); Sun, 25 Jan 2009 12:31:51 +0000 Received: by mow.po.2iij.net (mow300) id n0PCVmAd002661; Sun, 25 Jan 2009 21:31:48 +0900 Received: from delta (133.6.30.125.dy.iij4u.or.jp [125.30.6.133]) by mbox.po.2iij.net (po-mbox305) id n0PCVjRg000510 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NOT); Sun, 25 Jan 2009 21:31:46 +0900 Date: Sun, 25 Jan 2009 21:30:38 +0900 From: Yoichi Yuasa To: Ralf Baechle Cc: yoichi_yuasa@tripeaks.co.jp, linux-mips Subject: Re: [PATCH][MIPS] fix oops in r4k_dma_cache_inv Message-Id: <20090125213038.0f54be07.yoichi_yuasa@tripeaks.co.jp> In-Reply-To: <20090124191055.GA29966@linux-mips.org> References: <20090124221542.bcc6c19f.yoichi_yuasa@tripeaks.co.jp> <20090124191055.GA29966@linux-mips.org> Organization: TriPeaks Corporation X-Mailer: Sylpheed 2.4.8 (GTK+ 2.12.9; i486-pc-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21815 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: yoichi_yuasa@tripeaks.co.jp Precedence: bulk X-list: linux-mips Content-Length: 2094 Lines: 58 It's good for me. Acked-by: Yoichi Yuasa On Sat, 24 Jan 2009 19:10:55 +0000 Ralf Baechle wrote: > On Sat, Jan 24, 2009 at 10:15:42PM +0900, Yoichi Yuasa wrote: > > Patch looks ok - but I think we also have to assume that the starting > address of the range might be miss-aligned, so how about this patch? > > Ralf > > Signed-off-by: Ralf Baechle > > diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c > index 56290a7..c43f4b2 100644 > --- a/arch/mips/mm/c-r4k.c > +++ b/arch/mips/mm/c-r4k.c > @@ -619,8 +619,20 @@ static void r4k_dma_cache_inv(unsigned long addr, unsigned long size) > if (size >= scache_size) > r4k_blast_scache(); > else { > - cache_op(Hit_Writeback_Inv_SD, addr); > - cache_op(Hit_Writeback_Inv_SD, addr + size - 1); > + unsigned long lsize = cpu_scache_line_size(); > + unsigned long almask = ~(lsize - 1); > + > + /* > + * There is no clearly documented alignment requirement > + * for the cache instruction on MIPS processors and > + * some processors, among them the RM5200 and RM7000 > + * QED processors will throw an address error for cache > + * hit ops with insufficient alignment. Solved by > + * aligning the address to cache line size. > + */ > + cache_op(Hit_Writeback_Inv_SD, addr & almask); > + cache_op(Hit_Writeback_Inv_SD, > + (addr + size - 1) & almask); > blast_inv_scache_range(addr, addr + size); > } > return; > @@ -629,9 +641,12 @@ static void r4k_dma_cache_inv(unsigned long addr, unsigned long size) > if (cpu_has_safe_index_cacheops && size >= dcache_size) { > r4k_blast_dcache(); > } else { > + unsigned long lsize = cpu_dcache_line_size(); > + unsigned long almask = ~(lsize - 1); > + > R4600_HIT_CACHEOP_WAR_IMPL; > - cache_op(Hit_Writeback_Inv_D, addr); > - cache_op(Hit_Writeback_Inv_D, addr + size - 1); > + cache_op(Hit_Writeback_Inv_D, addr & almask); > + cache_op(Hit_Writeback_Inv_D, (addr + size - 1) & almask); > blast_inv_dcache_range(addr, addr + size); > } > From yoichi_yuasa@tripeaks.co.jp Sun Jan 25 12:32:10 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 25 Jan 2009 12:32:12 +0000 (GMT) Received: from mow300.po.2iij.NET ([210.128.50.200]:54730 "EHLO mow.po.2iij.net") by ftp.linux-mips.org with ESMTP id S21366146AbZAYMbx (ORCPT ); Sun, 25 Jan 2009 12:31:53 +0000 Received: by mow.po.2iij.net (mow300) id n0PCVo0b002664; Sun, 25 Jan 2009 21:31:50 +0900 Received: from delta (133.6.30.125.dy.iij4u.or.jp [125.30.6.133]) by mbox.po.2iij.net (po-mbox301) id n0PCVjLw016789 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NOT); Sun, 25 Jan 2009 21:31:45 +0900 Date: Sun, 25 Jan 2009 21:25:11 +0900 From: Yoichi Yuasa To: Ralf Baechle Cc: yoichi_yuasa@tripeaks.co.jp, linux-mips Subject: [PATCH][MIPS] Cobalt: add select PCI Message-Id: <20090125212511.b64bc630.yoichi_yuasa@tripeaks.co.jp> Organization: TriPeaks Corporation X-Mailer: Sylpheed 2.4.8 (GTK+ 2.12.9; i486-pc-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21816 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: yoichi_yuasa@tripeaks.co.jp Precedence: bulk X-list: linux-mips Content-Length: 535 Lines: 15 PCI bus is always required for Cobalt ID. Signed-off-by: Yoichi Yuasa diff -pruN -X /home/yuasa/Memo/dontdiff linux-orig/arch/mips/Kconfig linux/arch/mips/Kconfig --- linux-orig/arch/mips/Kconfig 2008-10-19 22:36:34.973823677 +0900 +++ linux/arch/mips/Kconfig 2008-10-19 22:33:58.440903373 +0900 @@ -72,6 +72,7 @@ config MIPS_COBALT select IRQ_CPU select IRQ_GT641XX select PCI_GT64XXX_PCI0 + select PCI select SYS_HAS_CPU_NEVADA select SYS_HAS_EARLY_PRINTK select SYS_SUPPORTS_32BIT_KERNEL From yoichi_yuasa@tripeaks.co.jp Sun Jan 25 13:46:03 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 25 Jan 2009 13:46:07 +0000 (GMT) Received: from mow300.po.2iij.net ([210.128.50.200]:40415 "EHLO mow.po.2iij.net") by ftp.linux-mips.org with ESMTP id S21366184AbZAYNqD (ORCPT ); Sun, 25 Jan 2009 13:46:03 +0000 Received: by mow.po.2iij.net (mow300) id n0PDk0Xv013713; Sun, 25 Jan 2009 22:46:00 +0900 Received: from delta (133.6.30.125.dy.iij4u.or.jp [125.30.6.133]) by mbox.po.2iij.net (po-mbox301) id n0PDjvGh015083 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NOT); Sun, 25 Jan 2009 22:45:57 +0900 Date: Sun, 25 Jan 2009 22:45:57 +0900 From: Yoichi Yuasa To: Ralf Baechle Cc: yoichi_yuasa@tripeaks.co.jp, linux-mips Subject: [PATCH][MIPS] add return value check to user_termio_to_kernel_termios() Message-Id: <20090125224557.8582051b.yoichi_yuasa@tripeaks.co.jp> Organization: TriPeaks Corporation X-Mailer: Sylpheed 2.4.8 (GTK+ 2.12.9; i486-pc-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21818 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: yoichi_yuasa@tripeaks.co.jp Precedence: bulk X-list: linux-mips Content-Length: 1460 Lines: 29 Signed-off-by: Yoichi Yuasa diff -pruN -X /home/yuasa/Memo/dontdiff linux-orig/arch/mips/include/asm/termios.h linux/arch/mips/include/asm/termios.h --- linux-orig/arch/mips/include/asm/termios.h 2008-10-19 22:33:14.114377349 +0900 +++ linux/arch/mips/include/asm/termios.h 2008-10-19 22:41:25.322369698 +0900 @@ -97,14 +97,14 @@ struct termio { #define user_termio_to_kernel_termios(termios, termio) \ ({ \ unsigned short tmp; \ - get_user(tmp, &(termio)->c_iflag); \ - (termios)->c_iflag = (0xffff0000 & ((termios)->c_iflag)) | tmp; \ - get_user(tmp, &(termio)->c_oflag); \ - (termios)->c_oflag = (0xffff0000 & ((termios)->c_oflag)) | tmp; \ - get_user(tmp, &(termio)->c_cflag); \ - (termios)->c_cflag = (0xffff0000 & ((termios)->c_cflag)) | tmp; \ - get_user(tmp, &(termio)->c_lflag); \ - (termios)->c_lflag = (0xffff0000 & ((termios)->c_lflag)) | tmp; \ + if (!get_user(tmp, &(termio)->c_iflag)) \ + (termios)->c_iflag = (0xffff0000 & ((termios)->c_iflag)) | tmp; \ + if (!get_user(tmp, &(termio)->c_oflag)) \ + (termios)->c_oflag = (0xffff0000 & ((termios)->c_oflag)) | tmp; \ + if (!get_user(tmp, &(termio)->c_cflag)) \ + (termios)->c_cflag = (0xffff0000 & ((termios)->c_cflag)) | tmp; \ + if (!get_user(tmp, &(termio)->c_lflag)) \ + (termios)->c_lflag = (0xffff0000 & ((termios)->c_lflag)) | tmp; \ get_user((termios)->c_line, &(termio)->c_line); \ copy_from_user((termios)->c_cc, (termio)->c_cc, NCC); \ }) From dvomlehn@cisco.com Sun Jan 25 21:50:54 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 25 Jan 2009 21:50:56 +0000 (GMT) Received: from rtp-iport-2.cisco.com ([64.102.122.149]:43293 "EHLO rtp-iport-2.cisco.com") by ftp.linux-mips.org with ESMTP id S21365236AbZAYVus convert rfc822-to-8bit (ORCPT ); Sun, 25 Jan 2009 21:50:48 +0000 X-IronPort-AV: E=Sophos;i="4.37,323,1231113600"; d="scan'208";a="34796660" Received: from rtp-dkim-1.cisco.com ([64.102.121.158]) by rtp-iport-2.cisco.com with ESMTP; 25 Jan 2009 21:50:27 +0000 Received: from rtp-core-1.cisco.com (rtp-core-1.cisco.com [64.102.124.12]) by rtp-dkim-1.cisco.com (8.12.11/8.12.11) with ESMTP id n0PLoRrj014113; Sun, 25 Jan 2009 16:50:27 -0500 Received: from xbh-rtp-211.amer.cisco.com (xbh-rtp-211.cisco.com [64.102.31.102]) by rtp-core-1.cisco.com (8.13.8/8.13.8) with ESMTP id n0PLoRR1018130; Sun, 25 Jan 2009 21:50:27 GMT Received: from xmb-rtp-218.amer.cisco.com ([64.102.31.117]) by xbh-rtp-211.amer.cisco.com with Microsoft SMTPSVC(6.0.3790.1830); Sun, 25 Jan 2009 16:50:26 -0500 X-MimeOLE: Produced By Microsoft Exchange V6.5 Content-class: urn:content-classes:message MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT Subject: RE: 2.6.28 will not boot on 24K processor, ebase incorrectly modified in set_uncached_handler Date: Sun, 25 Jan 2009 16:50:25 -0500 Message-ID: In-Reply-To: <497C3C6F.3000209@paralogos.com> X-MS-Has-Attach: X-MS-TNEF-Correlator: Thread-Topic: 2.6.28 will not boot on 24K processor, ebase incorrectly modified in set_uncached_handler Thread-Index: Acl+1kXP3jArc75MQT+Qvx8eRtjzGgAYEbsQ References: <497C3C6F.3000209@paralogos.com> From: "David VomLehn (dvomlehn)" To: "Kevin D. Kissell" Cc: , "Dezhong Diao (dediao)" , "Victor Williams Jr (williavi)" , "Michael Sundius -X (msundius - Yoh Services LLC at Cisco)" X-OriginalArrivalTime: 25 Jan 2009 21:50:26.0804 (UTC) FILETIME=[EECB6B40:01C97F36] DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; l=1754; t=1232920227; x=1233784227; c=relaxed/simple; s=rtpdkim1001; h=Content-Type:From:Subject:Content-Transfer-Encoding:MIME-Version; d=cisco.com; i=dvomlehn@cisco.com; z=From:=20=22David=20VomLehn=20(dvomlehn)=22=20 |Subject:=20RE=3A=202.6.28=20will=20not=20boot=20on=2024K=2 0processor,=20ebase=20incorrectly=20modified=20in=20set_unca ched_handler |Sender:=20 |To:=20=22Kevin=20D.=20Kissell=22=20; bh=BXqohsHEWbPE2dT/MTS0xpFkavViVUpDSf92xFRsphQ=; b=rdKPFDedOx+xMcc/4pslfCUjlcnoyQAlA6US4sXVWZyiEjMPHtROV8hpt4 cSqI+tPKvycp7wCHIv4TVQR4RMTkC930fUyIu6QrqG0raIyO2QB5AmQfSJTL gnyb4mAM8q; Authentication-Results: rtp-dkim-1; header.From=dvomlehn@cisco.com; dkim=pass ( sig from cisco.com/rtpdkim1001 verified; ); Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21819 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dvomlehn@cisco.com Precedence: bulk X-list: linux-mips Content-Length: 1654 Lines: 47 > From: Kevin D. Kissell [mailto:kevink@paralogos.com] > Sent: Sunday, January 25, 2009 2:18 AM > To: David VomLehn (dvomlehn) > Cc: linux-mips@linux-mips.org; Dezhong Diao (dediao); Victor > Williams Jr (williavi); Michael Sundius -X (msundius - Yoh > Services LLC at Cisco) > Subject: Re: 2.6.28 will not boot on 24K processor, ebase > incorrectly modified in set_uncached_handler > > David VomLehn (dvomlehn) wrote: > > The 2.6.28 kernel dies in memcpy when called from > set_vi_srs_handler on > > a > > 24K processor. The problem is that ebase has an invalid value. The > > original > > value of ebase comes from a bootmem allocation, but the > following code > > in > > set_uncached_handler takes a perfectly good kseg0 address > and turns it > > into > > an invalid kseg1 address. > > > > if (cpu_has_mips_r2) > > ebase += (read_c0_ebase() & 0x3ffff000); > > > > This code was added in commit > 566f74f6b2f8b85d5b8d6caaf97e5672cecd3e3e. > > > I remember worrying about why it was "+=" and not "=" when others had > problems with that patch. See the thread "NXP STB225 board > support" from > January 8 or so. When I asked about that, I got a comment > that the add > operation was correct, but that patch *should* have said > "uncached_ebase > += (read_c0_ebase() & 0x3ffff000);" I guess uncache_ebase is > assumed to > contain something interesting in some non-address bits. Try > pre-pending > "uncached_" to that "ebase"... Just adding uncached_ to the ebase doesn't appear to work. Looking at the git log makes it a bit unclear as to exactly who made this change, but it would be helpful to know what was intended. From linux-mips@kernelport.de Mon Jan 26 10:21:46 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 26 Jan 2009 10:21:49 +0000 (GMT) Received: from mail.bugwerft.de ([212.112.241.193]:18890 "EHLO mail.bugwerft.de") by ftp.linux-mips.org with ESMTP id S21189190AbZAZKVq (ORCPT ); Mon, 26 Jan 2009 10:21:46 +0000 Received: from localhost (localhost.localdomain [127.0.0.1]) by mail.bugwerft.de (Postfix) with ESMTP id 961958F849D for ; Mon, 26 Jan 2009 11:21:40 +0100 (CET) Received: from mail.bugwerft.de ([127.0.0.1]) by localhost (mail.bugwerft.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id bDL3AU3bYx6T for ; Mon, 26 Jan 2009 11:21:40 +0100 (CET) Received: from [10.1.1.26] (unknown [192.168.22.14]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.bugwerft.de (Postfix) with ESMTP id AA9788F849C for ; Mon, 26 Jan 2009 11:21:38 +0100 (CET) Subject: Au1550 with kernel linux-2.6.28.1 PCI Cardbus mappings too large From: Frank Neuber To: linux-mips In-Reply-To: <1232871616.28527.347.camel@t60p> References: <1232739600.28527.289.camel@t60p> <20090124085734.5b6b5c66@scarran.roarinelk.net> <1232787448.28527.302.camel@t60p> <1232839224.28527.336.camel@t60p> <1232871616.28527.347.camel@t60p> Content-Type: text/plain Date: Mon, 26 Jan 2009 11:21:36 +0100 Message-Id: <1232965296.28527.427.camel@t60p> Mime-Version: 1.0 X-Mailer: Evolution 2.12.1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21820 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: linux-mips@kernelport.de Precedence: bulk X-list: linux-mips Content-Length: 2703 Lines: 70 Hello again, as I sad I want to use a USB controller wired on the pci bus. The EHCI Probe (usb_hcd_pci_probe) fails with "controller already in use" error because the request_mem_region gives an error. I think the Problem is that the CardBus bridge eat the mem. As a refence you can compare the CadrBus mem window on 2.6.28.1 with 2.6.16.11. At the moment I have no idea how can I fix this resource conflict ... I found a pcibios_fixup_bus fuction that reorganize the dev->resource[i] values but I'm not sure if this is called during pci init. I'll check this now. Is there a PCI guru for mips on the list? Kind regards, Frank Kernel 2.6.28.1 output pci 0000:00:0c.0: PME# supported from D1 D3hot D3cold pci 0000:00:0c.0: PME# disabled pci 0000:00:0c.1: PME# supported from D1 D3hot D3cold pci 0000:00:0c.1: PME# disabled pci 0000:00:0c.2: PME# supported from D0 D1 D2 D3hot D3cold pci 0000:00:0c.2: PME# disabled pci 0000:00:0d.0: PME# supported from D0 D1 D2 D3hot D3cold pci 0000:00:0d.0: PME# disabled pci 0000:00:0d.1: PME# supported from D0 D1 D2 D3hot D3cold pci 0000:00:0d.1: PME# disabled pci 0000:00:0c.0: BAR 0: can't allocate mem resource [0x50000000-0x4fffffff] pci 0000:00:0c.1: BAR 0: can't allocate mem resource [0x50000000-0x4fffffff] pci 0000:00:0d.0: BAR 0: can't allocate mem resource [0x50000000-0x4fffffff] pci 0000:00:0d.1: BAR 0: can't allocate mem resource [0x50000000-0x4fffffff] pci 0000:00:0c.2: BAR 0: can't allocate mem resource [0x50000000-0x4fffffff] pci 0000:00:0d.0: CardBus bridge, secondary bus 0000:01 pci 0000:00:0d.0: IO window: 0x001000-0x0010ff pci 0000:00:0d.0: IO window: 0x001400-0x0014ff pci 0000:00:0d.0: PREFETCH window: 0x40000000-0x43ffffff pci 0000:00:0d.0: MEM window: 0x44000000-0x47ffffff pci 0000:00:0d.1: CardBus bridge, secondary bus 0000:05 pci 0000:00:0d.1: IO window: 0x001800-0x0018ff pci 0000:00:0d.1: IO window: 0x001c00-0x001cff pci 0000:00:0d.1: PREFETCH window: 0x48000000-0x4bffffff pci 0000:00:0d.1: MEM window: 0x4c000000-0x4fffffff PCI: Enabling device 0000:00:0d.0 (0000 -> 0003) PCI: Enabling device 0000:00:0d.1 (0000 -> 0003) Kernel 2.6.16.11 output PCI: Bus 1, cardbus bridge: 0000:00:0d.0 IO window: 00001000-000010ff IO window: 00001400-000014ff PREFETCH window: 40000000-41ffffff MEM window: 42000000-43ffffff PCI: Bus 5, cardbus bridge: 0000:00:0d.1 IO window: 00001800-000018ff IO window: 00001c00-00001cff PREFETCH window: 44000000-45ffffff MEM window: 46000000-47ffffff PCI: Enabling device 0000:00:0d.0 (0000 -> 0003) PCI: Setting latency timer of device 0000:00:0d.0 to 64 PCI: Enabling device 0000:00:0d.1 (0000 -> 0003) PCI: Setting latency timer of device 0000:00:0d.1 to 64 From ihar.hrachyshka@gmail.com Mon Jan 26 22:35:47 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 26 Jan 2009 22:35:49 +0000 (GMT) Received: from fk-out-0910.google.com ([209.85.128.189]:45350 "EHLO fk-out-0910.google.com") by ftp.linux-mips.org with ESMTP id S21102800AbZAZWfr (ORCPT ); Mon, 26 Jan 2009 22:35:47 +0000 Received: by fk-out-0910.google.com with SMTP id 26so2928094fkx.0 for ; Mon, 26 Jan 2009 14:35:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:mime-version:received:in-reply-to:references :date:message-id:subject:from:to:cc:content-type :content-transfer-encoding; bh=u+JER7oNwEnAN8U8nRYIkZ0GtA60pvJSLxyVPc0NfXE=; b=n49sCFNJjV6I2wmSsOA9EuIuv21c1kKiGIO8O938oQeG/Xo4cHQupskeHxmfhQfwUe BdGmqOGXXM/fmOa8Eblkhi1oGRTePmXH71GTaCmKI8dKJCURqU4mkCM0juUPtCMDTrc1 L5CRsG0AehanNfcZnsTs5Kdzle6MkMrg0ygRU= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type:content-transfer-encoding; b=IbiH64yF/EGjYK4qgl5UHj0v/BZOs+W0Vfi4UtsbjTAeDK4B9kLVJFz3CnOsraH0A2 LIgl1OUbBeo8tdxYX9EtdYr3dzlroi+OQO0CNHJF2aZM0FbhgFstzL3UNTbmifRCnIWv JRcvjYUKYHF9VqmeNwXCC1hJaeB8TjwxBsISQ= MIME-Version: 1.0 Received: by 10.181.5.1 with SMTP id h1mr1202692bki.56.1233009345552; Mon, 26 Jan 2009 14:35:45 -0800 (PST) In-Reply-To: References: <497C3C6F.3000209@paralogos.com> Date: Tue, 27 Jan 2009 00:35:45 +0200 Message-ID: Subject: Re: 2.6.28 will not boot on 24K processor, ebase incorrectly modified in set_uncached_handler From: Ihar Hrachyshka To: "David VomLehn (dvomlehn)" Cc: "Kevin D. Kissell" , linux-mips@linux-mips.org, "Dezhong Diao (dediao)" , "Victor Williams Jr (williavi)" , "Michael Sundius -X (msundius - Yoh Services LLC at Cisco)" Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21821 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ihar.hrachyshka@gmail.com Precedence: bulk X-list: linux-mips Content-Length: 1932 Lines: 55 On Sun, Jan 25, 2009 at 11:50 PM, David VomLehn (dvomlehn) wrote: >> From: Kevin D. Kissell [mailto:kevink@paralogos.com] >> Sent: Sunday, January 25, 2009 2:18 AM >> To: David VomLehn (dvomlehn) >> Cc: linux-mips@linux-mips.org; Dezhong Diao (dediao); Victor >> Williams Jr (williavi); Michael Sundius -X (msundius - Yoh >> Services LLC at Cisco) >> Subject: Re: 2.6.28 will not boot on 24K processor, ebase >> incorrectly modified in set_uncached_handler >> >> David VomLehn (dvomlehn) wrote: >> > The 2.6.28 kernel dies in memcpy when called from >> set_vi_srs_handler on >> > a >> > 24K processor. The problem is that ebase has an invalid value. The >> > original >> > value of ebase comes from a bootmem allocation, but the >> following code >> > in >> > set_uncached_handler takes a perfectly good kseg0 address >> and turns it >> > into >> > an invalid kseg1 address. >> > >> > if (cpu_has_mips_r2) >> > ebase += (read_c0_ebase() & 0x3ffff000); >> > >> > This code was added in commit >> 566f74f6b2f8b85d5b8d6caaf97e5672cecd3e3e. >> > >> I remember worrying about why it was "+=" and not "=" when others had >> problems with that patch. See the thread "NXP STB225 board >> support" from >> January 8 or so. When I asked about that, I got a comment >> that the add >> operation was correct, but that patch *should* have said >> "uncached_ebase >> += (read_c0_ebase() & 0x3ffff000);" I guess uncache_ebase is >> assumed to >> contain something interesting in some non-address bits. Try >> pre-pending >> "uncached_" to that "ebase"... > > Just adding uncached_ to the ebase doesn't appear to work. Looking at > the git > log makes it a bit unclear as to exactly who made this change, but it > would > be helpful to know what was intended. > > If the patch invoked broke lots of subarchs why should we have it in the first place? Can't we just revert it until we have a fix for this bug? From f.fainelli@gmail.com Mon Jan 26 22:41:03 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 26 Jan 2009 22:41:07 +0000 (GMT) Received: from mail-ew0-f17.google.com ([209.85.219.17]:43176 "EHLO mail-ew0-f17.google.com") by ftp.linux-mips.org with ESMTP id S21102800AbZAZWlD convert rfc822-to-8bit (ORCPT ); Mon, 26 Jan 2009 22:41:03 +0000 Received: by ewy10 with SMTP id 10so6241229ewy.0 for ; Mon, 26 Jan 2009 14:40:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:sender:from:to:subject:date :user-agent:cc:references:in-reply-to:mime-version:content-type :content-transfer-encoding:content-disposition:message-id; bh=Vw3kwwD9ovMcTkbj4Wrl6Y4/c+7NRiwWMsiER7mlO+Q=; b=a1e62pfIt2DQ/WgxTfqOR4dsfNMNZ1cfTWNiO6LJUGdRHAynN6PLRs91g0zHc4pLYt mkC4DbzALa1+my0qtoZ17NAGut9a3PLdv3lhnUGZvWsRvVUKsRys8VWQ2bRmIYkUY0wT QBp60qnzFT5roZ33K7qMXmDbBuabHdmZ9gmp8= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:from:to:subject:date:user-agent:cc:references:in-reply-to :mime-version:content-type:content-transfer-encoding :content-disposition:message-id; b=LUf6PLW+f+A/+oCHPij2hkWR+cqe+C9k+AF1DfMDeSzQT03+A5Oof9tIijR1k77kp3 gVPZchKNLq5BuBzj9kFoYUtQebbinn3RTmZwaTjAiLsXa8o7m/7c+5SYAsbOccQR6vyN DZPrQqumvmHZ6fCPgQ8LnugAZpKcUcjkNvAno= Received: by 10.103.212.2 with SMTP id o2mr3693447muq.131.1233009657412; Mon, 26 Jan 2009 14:40:57 -0800 (PST) Received: from lenovo.mimichou.home (florian.mimichou.net [82.241.112.26]) by mx.google.com with ESMTPS id j6sm14151363mue.54.2009.01.26.14.40.56 (version=TLSv1/SSLv3 cipher=RC4-MD5); Mon, 26 Jan 2009 14:40:56 -0800 (PST) From: Florian Fainelli To: Manuel Lauss Subject: Re: [PATCH] au1000: convert to using gpiolib Date: Mon, 26 Jan 2009 23:40:27 +0100 User-Agent: KMail/1.9.9 Cc: ralf@linux-mips.org, Linux-MIPS References: <200901151646.49591.florian@openwrt.org> <20090116174753.GA18764@roarinelk.homelinux.net> <200901191812.24377.florian@openwrt.org> In-Reply-To: <200901191812.24377.florian@openwrt.org> MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 8BIT Content-Disposition: inline Message-Id: <200901262340.27613.florian@openwrt.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21822 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips Content-Length: 443 Lines: 15 Hi Manuel, Le Monday 19 January 2009 18:12:23 Florian Fainelli, vous avez écrit : > This patch converts the GPIO board code to use gpiolib. > Changes from v1: > - allow users not to use the default gpio accessors > - do not lock au1000_gpio2_set I did not receive comments from you on this patch, can I consider it being ok ? -- Best regards, Florian Fainelli Email : florian@openwrt.org http://openwrt.org ------------------------------- From khickey@rmicorp.com Tue Jan 27 02:18:59 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 27 Jan 2009 02:19:01 +0000 (GMT) Received: from mx1.rmicorp.com ([63.111.213.197]:62913 "EHLO hq-ex-mb01.razamicroelectronics.com") by ftp.linux-mips.org with ESMTP id S21366006AbZA0CSx (ORCPT ); Tue, 27 Jan 2009 02:18:53 +0000 Received: from 71.145.136.190 ([71.145.136.190]) by hq-ex-mb01.razamicroelectronics.com ([10.1.1.40]) via Exchange Front-End Server webmail.razamicroelectronics.com ([10.1.1.41]) with Microsoft Exchange Server HTTP-DAV ; Tue, 27 Jan 2009 02:18:45 +0000 Received: from kh-d820 by webmail.razamicroelectronics.com; 26 Jan 2009 20:18:46 -0600 Subject: Re: [PATCH] Alchemy: fix edge irq handling From: Kevin Hickey To: Manuel Lauss Cc: Ralf Baechle , Linux-MIPS In-Reply-To: <20090121064856.GA27020@roarinelk.homelinux.net> References: <20090120100353.GA18971@roarinelk.homelinux.net> <1232498838.3678.17.camel@kh-d820> <20090121064856.GA27020@roarinelk.homelinux.net> Content-Type: text/plain Content-Transfer-Encoding: 7bit Date: Mon, 26 Jan 2009 20:18:45 -0600 Message-Id: <1233022725.14733.10.camel@kh-d820> Mime-Version: 1.0 X-Mailer: Evolution 2.22.3.1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21823 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: khickey@rmicorp.com Precedence: bulk X-list: linux-mips Content-Length: 1607 Lines: 38 I am still concerned about this patch. Just last week we encountered similar behavior that turned out to be a board design error. I had a similar patch in that kernel that allowed me to run without error. Our Windows CE developer, however, did not and ended up finding the board bug. Fixing the board improved performance and system stability - had we not been running CE we probably would not have found the issue until much later and with greater effort. Your example below is similar - debouncing the switch in hardware seems a better solution (albeit likely an expensive one) than patching the mainline kernel. And I reiterate: some devices send a lot of interrupts by design; we should honor their requests, not mask them out. =Kevin On Wed, 2009-01-21 at 07:48 +0100, Manuel Lauss wrote: > Hi Kevin, > > > Have you actually seen this happen (outside of inducing it manually)? I > > have some concern that by doing this we may either miss interrupts on > > devices that send a lot (by design) or miss a design bug in a system > > because we are masking out some interrupts. I know that system > > stability is important, but I don't like hiding problems. > > Yes, in a customer project. A simple pushbutton which connects a pulled-up > gpio pin to ground. Push it, instant hang (handler called over and over > again) when it is not debounced. With a single edge and a much lower > edge-frequency it obviously works fine (see timer). > > (And, handle_edge_irq() _does_ call mask_ack() after all). -- Kevin Hickey Alchemy Solutions RMI Corporation khickey@rmicorp.com P: 512.691.8044 From mano@roarinelk.homelinux.net Tue Jan 27 06:20:38 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 27 Jan 2009 06:20:40 +0000 (GMT) Received: from fnoeppeil36.netpark.at ([217.175.205.164]:6348 "EHLO roarinelk.homelinux.net") by ftp.linux-mips.org with ESMTP id S21102777AbZA0GUi (ORCPT ); Tue, 27 Jan 2009 06:20:38 +0000 Received: (qmail 14761 invoked by uid 1000); 27 Jan 2009 07:20:36 +0100 Date: Tue, 27 Jan 2009 07:20:36 +0100 From: Manuel Lauss To: Kevin Hickey Cc: Ralf Baechle , Linux-MIPS Subject: Re: [PATCH] Alchemy: fix edge irq handling Message-ID: <20090127062036.GA14558@roarinelk.homelinux.net> References: <20090120100353.GA18971@roarinelk.homelinux.net> <1232498838.3678.17.camel@kh-d820> <20090121064856.GA27020@roarinelk.homelinux.net> <1233022725.14733.10.camel@kh-d820> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1233022725.14733.10.camel@kh-d820> User-Agent: Mutt/1.5.16 (2007-06-09) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21824 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mano@roarinelk.homelinux.net Precedence: bulk X-list: linux-mips Content-Length: 1294 Lines: 26 Kevin, On Mon, Jan 26, 2009 at 08:18:45PM -0600, Kevin Hickey wrote: > Your example below is similar - debouncing the switch in hardware seems > a better solution (albeit likely an expensive one) than patching the > mainline kernel. And I reiterate: some devices send a lot of interrupts > by design; we should honor their requests, not mask them out. I agree in principle, but what's the point of honoring the requests if they come in faster than the cpu can handle them? I think that's why the handle_edge_irq() flowhandler masks the interrupt when another edge comes in while the handler for the previous one is still running. This is also the problem I'm running into: the second (and following) edges don't get acked when the flowhandler tries to mask them, resulting in the irq storm. If I explicitly ack it in the irq handler itself, all is well. The current in-tree irq code bahaves differently than in <=2.6.28; this patch restores this behaviour, and I believe it is the way the mask_ack() callback is supposed to work. It affects only edge interrupts which come in faster than the cpu can handle them; for all others there's no change (other than 2 more stores in the mask fastpath). (Or maybe it's a logic bug in handle_edge_irq(); I don't know.) Thanks, Manuel Lauss From mano@roarinelk.homelinux.net Tue Jan 27 06:58:28 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 27 Jan 2009 06:58:30 +0000 (GMT) Received: from fnoeppeil36.netpark.at ([217.175.205.164]:7073 "EHLO roarinelk.homelinux.net") by ftp.linux-mips.org with ESMTP id S21366037AbZA0G62 (ORCPT ); Tue, 27 Jan 2009 06:58:28 +0000 Received: (qmail 14992 invoked by uid 1000); 27 Jan 2009 07:58:27 +0100 Date: Tue, 27 Jan 2009 07:58:27 +0100 From: Manuel Lauss To: Florian Fainelli Cc: ralf@linux-mips.org, Linux-MIPS Subject: Re: [PATCH] au1000: convert to using gpiolib Message-ID: <20090127065827.GA14985@roarinelk.homelinux.net> References: <200901151646.49591.florian@openwrt.org> <20090116174753.GA18764@roarinelk.homelinux.net> <200901191812.24377.florian@openwrt.org> <200901262340.27613.florian@openwrt.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <200901262340.27613.florian@openwrt.org> User-Agent: Mutt/1.5.16 (2007-06-09) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21825 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mano@roarinelk.homelinux.net Precedence: bulk X-list: linux-mips Content-Length: 440 Lines: 15 Florian, > Le Monday 19 January 2009 18:12:23 Florian Fainelli, vous avez ?crit?: > > This patch converts the GPIO board code to use gpiolib. > > Changes from v1: > > - allow users not to use the default gpio accessors > > - do not lock au1000_gpio2_set > > I did not receive comments from you on this patch, can I consider it being > ok ? Oh sorry. Please export all the au1000_gpioX_* functions and I'm happy. Thanks! Manuel Lauss From linux-mips@kernelport.de Tue Jan 27 08:44:13 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 27 Jan 2009 08:44:15 +0000 (GMT) Received: from mail.bugwerft.de ([212.112.241.193]:5539 "EHLO mail.bugwerft.de") by ftp.linux-mips.org with ESMTP id S21366063AbZA0IoN (ORCPT ); Tue, 27 Jan 2009 08:44:13 +0000 Received: from localhost (localhost.localdomain [127.0.0.1]) by mail.bugwerft.de (Postfix) with ESMTP id D877E49400C for ; Tue, 27 Jan 2009 09:44:07 +0100 (CET) Received: from mail.bugwerft.de ([127.0.0.1]) by localhost (mail.bugwerft.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id bbtM+o9PEzjX for ; Tue, 27 Jan 2009 09:44:07 +0100 (CET) Received: from [10.1.1.26] (unknown [192.168.22.14]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.bugwerft.de (Postfix) with ESMTP id 9BD4949400B for ; Tue, 27 Jan 2009 09:44:06 +0100 (CET) Subject: AU1550 Kernel bug detected[#1] clockevents_register_device From: Frank Neuber To: Linux-MIPS Content-Type: text/plain; charset=UTF-8 Date: Tue, 27 Jan 2009 09:44:02 +0100 Message-Id: <1233045842.28527.459.camel@t60p> Mime-Version: 1.0 X-Mailer: Evolution 2.12.1 Content-Transfer-Encoding: 8bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21826 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: linux-mips@kernelport.de Precedence: bulk X-list: linux-mips Content-Length: 3057 Lines: 80 Hi, to find my PCI problem I want to use git to find the last working version. I just start with head and found a compile error: arch/mips/alchemy/common/time.c:93: error: incompatible types in initialization I comment this line ".cpumask = CPU_MASK_ALL," and build again. This is the result. Somethig is wrong with the timer ... <5>Linux version 2.6.29-rc2-00351-g5ee8100-dirty (neuber@t60p) (gcc version 4.0.0 (DENX ELDK 4.1 4.0.0)) #2 Tue Jan 27 09:03:59 CET 2009 <6>CPU revision is: 03030200 (Au1550) <6>(PRId 03030200) @ 336.00 MHz <6>AMD Alchemy Au1550/Db1550 Board <6>Determined physical RAM map: <6> memory: 08000000 @ 00000000 (usable) <4>Zone PFN ranges: <4> Normal 0x00000000 -> 0x00008000 <4>Movable zone start PFN for each node <4>early_node_map[1] active PFN ranges <4> 0: 0x00000000 -> 0x00008000 <7>On node 0 totalpages: 32768 <7>free_area_init_node: node 0, pgdat 804c5b00, node_mem_map 81000000 <7> Normal zone: 256 pages used for memmap <7> Normal zone: 0 pages reserved <7> Normal zone: 32512 pages, LIFO batch:7 <4>Built 1 zonelists in Zone order, mobility grouping on. Total pages: 32512 <5>Kernel command line: console=ttyS0,115200n8 panic=1 ip=192.168.100.101::192.168.100.100:255.255.255.0:tc:eth0:off root=/dev/mtdblock0 rw rootfstype=jffs2 <4>Primary instruction cache 16kB, VIPT, 4-way, linesize 32 bytes. <4>Primary data cache 16kB, 4-way, VIPT, no aliases, linesize 32 bytes <4>PID hash table entries: 512 (order: 9, 2048 bytes) <4>Kernel bug detected[#1]: <4>Cpu 0 <4>$ 0 : 00000000 00032954 00000000 00000001 <4>$ 4 : 804ab750 00000000 0003b9ad 00000000 <4>$ 8 : 000225c1 00000000 000225c1 00000000 <4>$12 : 00000000 00000000 3b9aca00 804ab6e0 <4>$16 : 804ab750 804ab750 804f0000 804f0000 <4>$20 : 00ff0000 87fb4298 00000002 00000000 <4>$24 : 804a9d00 8011d8fc <4>$28 : 804a8000 804a9f58 87ff7ab0 804c9814 <4>Hi : 00000008 <4>Lo : 00000000 <4>epc : 8015e554 clockevents_register_device+0x34/0x110 <4> Not tainted <4>ra : 804c9814 plat_time_init+0x1ac/0x26c <4>Status: 10003c02 KERNEL EXL <4>Cause : 00808034 <4>PrId : 03030200 (Au1550) <4>Modules linked in: <4>Process swapper (pid: 0, threadinfo=804a8000, task=804aa000, tls=00000000) <4>Stack : 804ab6e0 8015d1ec 804c9634 87fb4298 804ab750 804ee585 804f0000 804f0000 <4> 00ff0000 804c9814 804e7914 804ee585 804f0000 804f0000 804e7914 804c87f4 <4> 00000000 804e7914 00000316 00000316 804c82cc 00000000 804ee500 00000000 <4> 20000000 00000000 00000000 ff000000 87ff17b8 00000000 00000000 00000000 <4> 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 <4> ... <4>Call Trace: <4>[<8015e554>] clockevents_register_device+0x34/0x110 <4>[<804c9814>] plat_time_init+0x1ac/0x26c <4>[<804c87f4>] start_kernel+0x1f8/0x3e4 <4> <4> <4>Code: 00028036 8c830020 2c630001 <00038036> 8c820010 1040002c 24020001 3c10804b 8e03e558 <0>Kernel panic - not syncing: Attempted to kill the idle task! <0>Rebooting in 1 seconds..<5> <4>** Resetting Integrated � From mano@roarinelk.homelinux.net Tue Jan 27 09:11:08 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 27 Jan 2009 09:11:11 +0000 (GMT) Received: from fnoeppeil36.netpark.at ([217.175.205.164]:24299 "EHLO roarinelk.homelinux.net") by ftp.linux-mips.org with ESMTP id S21366070AbZA0JLI (ORCPT ); Tue, 27 Jan 2009 09:11:08 +0000 Received: (qmail 15910 invoked by uid 1000); 27 Jan 2009 10:11:08 +0100 Date: Tue, 27 Jan 2009 10:11:07 +0100 From: Manuel Lauss To: Frank Neuber Cc: Linux-MIPS Subject: Re: AU1550 Kernel bug detected[#1] clockevents_register_device Message-ID: <20090127091107.GA15890@roarinelk.homelinux.net> References: <1233045842.28527.459.camel@t60p> MIME-Version: 1.0 Content-Type: text/plain; charset=unknown-8bit Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <1233045842.28527.459.camel@t60p> User-Agent: Mutt/1.5.16 (2007-06-09) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21827 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mano@roarinelk.homelinux.net Precedence: bulk X-list: linux-mips Content-Length: 457 Lines: 14 On Tue, Jan 27, 2009 at 09:44:02AM +0100, Frank Neuber wrote: > Hi, > to find my PCI problem I want to use git to find the last working > version. > I just start with head and found a compile error: > arch/mips/alchemy/common/time.c:93: error: incompatible types in > initialization > I comment this line ".cpumask = CPU_MASK_ALL," you need to change it to "CPU_MASK_ALL_PTR". Commenting it is not a very good idea ;-) Beste Grüsse, Manuel Lauss From f.fainelli@gmail.com Tue Jan 27 09:19:04 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 27 Jan 2009 09:19:06 +0000 (GMT) Received: from fg-out-1718.google.com ([72.14.220.152]:1717 "EHLO fg-out-1718.google.com") by ftp.linux-mips.org with ESMTP id S20021569AbZA0JTE convert rfc822-to-8bit (ORCPT ); Tue, 27 Jan 2009 09:19:04 +0000 Received: by fg-out-1718.google.com with SMTP id 16so41291fgg.32 for ; Tue, 27 Jan 2009 01:19:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:sender:from:to:subject:date :user-agent:cc:references:in-reply-to:mime-version:content-type :content-transfer-encoding:content-disposition:message-id; bh=vQJJWP7pMdY779Il1HZesa3G6k9aIgyYe9wAgtnhOYM=; b=Yw66/5C3v34DNVYs4yMVEY7QD07N4KCmzMVo9x6WNShmCn8zg600w75+Me88f+2kRE VIU12S6ZWGMfMWXa91hsvET+HMqk2UQf33fbahh7Ac8AR9i0odwOoyqFj3EC+RJkX9IE iTqaWmtoGgKwxQXzBJC2bq2wll8PuJ1l5r0DI= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:from:to:subject:date:user-agent:cc:references:in-reply-to :mime-version:content-type:content-transfer-encoding :content-disposition:message-id; b=HxLiPJ9hYMGR6O+RdTUMVFD531ZBP6etenKnGO1XDVQ8WGhLv/7lnqX6ktsj2vZ9/M LZrmXSYn6jvjxWJaKc2SL2cq0xay4ojz9LMFboAAqJKrpmTOYQJK57l4PJAB6e2bcTWR RJEOCL2y6sncHBEI4ZIFb87SVeZzeJRdKkkJg= Received: by 10.86.93.19 with SMTP id q19mr301259fgb.62.1233047943423; Tue, 27 Jan 2009 01:19:03 -0800 (PST) Received: from lenovo.mimichou.home (florian.mimichou.net [82.241.112.26]) by mx.google.com with ESMTPS id l19sm6187471fgb.42.2009.01.27.01.19.01 (version=TLSv1/SSLv3 cipher=RC4-MD5); Tue, 27 Jan 2009 01:19:02 -0800 (PST) From: Florian Fainelli To: Manuel Lauss Subject: Re: AU1550 Kernel bug detected[#1] clockevents_register_device Date: Tue, 27 Jan 2009 10:18:30 +0100 User-Agent: KMail/1.9.9 Cc: Frank Neuber , Linux-MIPS References: <1233045842.28527.459.camel@t60p> <20090127091107.GA15890@roarinelk.homelinux.net> In-Reply-To: <20090127091107.GA15890@roarinelk.homelinux.net> MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 8BIT Content-Disposition: inline Message-Id: <200901271018.31863.florian@openwrt.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21828 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips Content-Length: 1464 Lines: 40 Le Tuesday 27 January 2009 10:11:07 Manuel Lauss, vous avez écrit : > On Tue, Jan 27, 2009 at 09:44:02AM +0100, Frank Neuber wrote: > > Hi, > > to find my PCI problem I want to use git to find the last working > > version. > > I just start with head and found a compile error: > > arch/mips/alchemy/common/time.c:93: error: incompatible types in > > initialization > > I comment this line ".cpumask = CPU_MASK_ALL," > > you need to change it to "CPU_MASK_ALL_PTR". Commenting it is not a very > good idea ;-) This build failure also happens on linux-queue. Patch below. -- From: Florian Fainelli Subject: [PATCH] alchemy: fix build failure on time.c This patch fixes the following build failure : arch/mips/alchemy/common/time.c:93: error: incompatible types in initialization Reported-by: Frank Neuber Signed-off-by: Manuel Lauss Signed-off-by: Florian Fainelli --- diff --git a/arch/mips/alchemy/common/time.c b/arch/mips/alchemy/common/time.c index 3288014..6fd441d 100644 --- a/arch/mips/alchemy/common/time.c +++ b/arch/mips/alchemy/common/time.c @@ -89,7 +89,7 @@ static struct clock_event_device au1x_rtcmatch2_clockdev = { .irq = AU1000_RTC_MATCH2_INT, .set_next_event = au1x_rtcmatch2_set_next_event, .set_mode = au1x_rtcmatch2_set_mode, - .cpumask = CPU_MASK_ALL, + .cpumask = CPU_MASK_ALL_PTR, }; static struct irqaction au1x_rtcmatch2_irqaction = { From f.fainelli@gmail.com Tue Jan 27 09:24:16 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 27 Jan 2009 09:24:18 +0000 (GMT) Received: from mail-ew0-f17.google.com ([209.85.219.17]:56981 "EHLO mail-ew0-f17.google.com") by ftp.linux-mips.org with ESMTP id S20021569AbZA0JYQ convert rfc822-to-8bit (ORCPT ); Tue, 27 Jan 2009 09:24:16 +0000 Received: by ewy10 with SMTP id 10so6465528ewy.0 for ; Tue, 27 Jan 2009 01:24:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:sender:from:to:subject:date :user-agent:cc:references:in-reply-to:mime-version:content-type :content-transfer-encoding:content-disposition:message-id; bh=x3hCGYIXCxCOzFPJ5clRuFNsbfXm5XmYQeukHQqCQKg=; b=ACEzXvQG9TSgtK8RXkbH4DXyRva/8Fb0rNg+Ozdr0gfc10WcYOEIPkwQszfxztK3xf OWcFx2T6la3qTHFbHgTTuWBzipnFB+78yS7u0SX69lDrS/vWPJ54CQaa7yTPV8Wno17d dcfF7xM9TJwl/Q6rg4gxZvRd3Vm3StWGRKibA= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:from:to:subject:date:user-agent:cc:references:in-reply-to :mime-version:content-type:content-transfer-encoding :content-disposition:message-id; b=fm4q4q9HjpUzYIsrLip9FHtVhzpuMpuFLA84VxTqEIQd2t+Vxxm8oG3DuGDq7FJfZB LWv+WSAtUwJhe8xROf+aQ5Dkduh0WRFjyACnomI4de5i+l4Vl25v62Eq7XpRp4XefWAg wtE9Hlr29rk0/Zr8OiNbfKndO0W1VmeRsZZNA= Received: by 10.103.222.1 with SMTP id z1mr3824971muq.100.1233048250711; Tue, 27 Jan 2009 01:24:10 -0800 (PST) Received: from lenovo.mimichou.home (florian.mimichou.net [82.241.112.26]) by mx.google.com with ESMTPS id w5sm25134498mue.55.2009.01.27.01.24.08 (version=TLSv1/SSLv3 cipher=RC4-MD5); Tue, 27 Jan 2009 01:24:09 -0800 (PST) From: Florian Fainelli To: Manuel Lauss Subject: Re: AU1550 Kernel bug detected[#1] clockevents_register_device Date: Tue, 27 Jan 2009 10:23:37 +0100 User-Agent: KMail/1.9.9 Cc: Frank Neuber , Linux-MIPS References: <1233045842.28527.459.camel@t60p> <20090127091107.GA15890@roarinelk.homelinux.net> <200901271018.31863.florian@openwrt.org> In-Reply-To: <200901271018.31863.florian@openwrt.org> MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 8BIT Content-Disposition: inline Message-Id: <200901271023.38127.florian@openwrt.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21829 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips Content-Length: 1060 Lines: 30 Le Tuesday 27 January 2009 10:18:30 Florian Fainelli, vous avez écrit : > Le Tuesday 27 January 2009 10:11:07 Manuel Lauss, vous avez écrit : > > On Tue, Jan 27, 2009 at 09:44:02AM +0100, Frank Neuber wrote: > > > Hi, > > > to find my PCI problem I want to use git to find the last working > > > version. > > > I just start with head and found a compile error: > > > arch/mips/alchemy/common/time.c:93: error: incompatible types in > > > initialization > > > I comment this line ".cpumask = CPU_MASK_ALL," > > > > you need to change it to "CPU_MASK_ALL_PTR". Commenting it is not a very > > good idea ;-) > > This build failure also happens on linux-queue. Patch below. > -- > From: Florian Fainelli > Subject: [PATCH] alchemy: fix build failure on time.c > > This patch fixes the following build failure : > > arch/mips/alchemy/common/time.c:93: error: incompatible types in > initialization Errm sorry, this was not for linux-queue ;) -- Best regards, Florian Fainelli Email : florian@openwrt.org http://openwrt.org ------------------------------- From f.fainelli@gmail.com Tue Jan 27 09:40:04 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 27 Jan 2009 09:40:07 +0000 (GMT) Received: from fg-out-1718.google.com ([72.14.220.157]:46812 "EHLO fg-out-1718.google.com") by ftp.linux-mips.org with ESMTP id S21102823AbZA0JkE convert rfc822-to-8bit (ORCPT ); Tue, 27 Jan 2009 09:40:04 +0000 Received: by fg-out-1718.google.com with SMTP id 16so48274fgg.32 for ; Tue, 27 Jan 2009 01:40:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:sender:from:to:subject:date :user-agent:cc:references:in-reply-to:mime-version:content-type :content-transfer-encoding:content-disposition:message-id; bh=m4KqlN+/AVFedZOSmAUHeDCcDsnsE8dw0Z1IPbl73sc=; b=NRTHF6ixHb3Ks7XwRV7XJNMokCt0FUukBW4ZHe7URpw+PPhWR5ASWeFsHqcHX0KOB9 xEPjzy8ZMaPL/3KxRAGRrRW6JPgNizruFVleA4nbtMl+UPVcSVv0xZFRGighs2u6EYw6 J9ZqBaWARfu2qXsqRkwF+GDnZOKH4WGoCYkjQ= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:from:to:subject:date:user-agent:cc:references:in-reply-to :mime-version:content-type:content-transfer-encoding :content-disposition:message-id; b=vlPZmeUbNs60iA7taMwA8TPHl414paEEuyPvbV4s/uqlEPj8J9QHM8G7haxSCXOcIq hDhLmaWORf+uZSgDAiVZ/9WUE4N+j+2hExpdeHfOnz8xF+dgbWohfCs/KrLF/CeXmdr7 YYOHUeDFvXcUvR4odXF8lgQlYBYBSGZ+EXbZ4= Received: by 10.223.112.132 with SMTP id w4mr444948fap.67.1233049203838; Tue, 27 Jan 2009 01:40:03 -0800 (PST) Received: from lenovo.mimichou.home (florian.mimichou.net [82.241.112.26]) by mx.google.com with ESMTPS id 25sm24419616mul.8.2009.01.27.01.40.01 (version=TLSv1/SSLv3 cipher=RC4-MD5); Tue, 27 Jan 2009 01:40:02 -0800 (PST) From: Florian Fainelli To: Manuel Lauss Subject: Re: [PATCH] au1000: convert to using gpiolib Date: Tue, 27 Jan 2009 10:39:30 +0100 User-Agent: KMail/1.9.9 Cc: ralf@linux-mips.org, Linux-MIPS References: <200901151646.49591.florian@openwrt.org> <200901262340.27613.florian@openwrt.org> <20090127065827.GA14985@roarinelk.homelinux.net> In-Reply-To: <20090127065827.GA14985@roarinelk.homelinux.net> MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 8BIT Content-Disposition: inline Message-Id: <200901271039.31680.florian@openwrt.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21830 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips Content-Length: 11057 Lines: 400 Le Tuesday 27 January 2009 07:58:27 Manuel Lauss, vous avez écrit : > Florian, > > > Le Monday 19 January 2009 18:12:23 Florian Fainelli, vous avez ?crit?: > > > This patch converts the GPIO board code to use gpiolib. > > > Changes from v1: > > > - allow users not to use the default gpio accessors > > > - do not lock au1000_gpio2_set > > > > I did not receive comments from you on this patch, can I consider it > > being ok ? > > Oh sorry. Please export all the au1000_gpioX_* functions and I'm happy. > > Thanks! > Manuel Lauss Here we go. Thanks ! -- From: Florian Fainelli Subject: [PATCH v3] Alchemy: convert to gpiolib This patch converts Alchemy SoC GPIO code to use gpiolib instead of the old GENERIC_GPIO implementation. Changes from v2: - export all gpio accessors so that custom boards can use them Changes from v1: - allow users not to use the default gpio accessors - do not lock au1000_gpio2_set Signed-off-by: Florian Fainelli --- diff --git a/arch/mips/alchemy/Kconfig b/arch/mips/alchemy/Kconfig index 7f8ef13..2fc5c13 100644 --- a/arch/mips/alchemy/Kconfig +++ b/arch/mips/alchemy/Kconfig @@ -135,3 +135,4 @@ config SOC_AU1X00 select SYS_SUPPORTS_32BIT_KERNEL select SYS_SUPPORTS_APM_EMULATION select GENERIC_HARDIRQS_NO__DO_IRQ + select ARCH_REQUIRE_GPIOLIB diff --git a/arch/mips/alchemy/common/gpio.c b/arch/mips/alchemy/common/gpio.c index e660ddd..535c565 100644 --- a/arch/mips/alchemy/common/gpio.c +++ b/arch/mips/alchemy/common/gpio.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2007, OpenWrt.org, Florian Fainelli + * Copyright (C) 2007-2009, OpenWrt.org, Florian Fainelli * Architecture specific GPIO support * * This program is free software; you can redistribute it and/or modify it @@ -27,122 +27,180 @@ * others have a second one : GPIO2 */ +#include #include +#include +#include +#include #include #include -#define gpio1 sys -#if !defined(CONFIG_SOC_AU1000) - -static struct au1x00_gpio2 *const gpio2 = (struct au1x00_gpio2 *) GPIO2_BASE; -#define GPIO2_OUTPUT_ENABLE_MASK 0x00010000 +struct au1000_gpio_chip { + struct gpio_chip chip; + void __iomem *regbase; +}; -static int au1xxx_gpio2_read(unsigned gpio) +#if !defined(CONFIG_SOC_AU1000) +int au1000_gpio2_get(struct gpio_chip *chip, unsigned offset) { - gpio -= AU1XXX_GPIO_BASE; - return ((gpio2->pinstate >> gpio) & 0x01); + u32 mask = 1 << offset; + struct au1000_gpio_chip *gpch; + + gpch = container_of(chip, struct au1000_gpio_chip, chip); + return readl(gpch->regbase + AU1000_GPIO2_ST) & mask; } +EXPORT_SYMBOL(au1000_gpio2_get); -static void au1xxx_gpio2_write(unsigned gpio, int value) +void au1000_gpio2_set(struct gpio_chip *chip, + unsigned offset, int value) { - gpio -= AU1XXX_GPIO_BASE; + u32 mask = ((GPIO2_OUT_EN_MASK << offset) | (!!value << offset)); + struct au1000_gpio_chip *gpch; - gpio2->output = (GPIO2_OUTPUT_ENABLE_MASK << gpio) | ((!!value) << gpio); + gpch = container_of(chip, struct au1000_gpio_chip, chip); + writel(mask, gpch->regbase + AU1000_GPIO2_OUT); } +EXPORT_SYMBOL(au1000_gpio2_set); -static int au1xxx_gpio2_direction_input(unsigned gpio) +int au1000_gpio2_direction_input(struct gpio_chip *chip, unsigned offset) { - gpio -= AU1XXX_GPIO_BASE; - gpio2->dir &= ~(0x01 << gpio); + u32 mask = 1 << offset; + u32 tmp; + struct au1000_gpio_chip *gpch; + unsigned long flags; + + gpch = container_of(chip, struct au1000_gpio_chip, chip); + + local_irq_save(flags); + tmp = readl(gpch->regbase + AU1000_GPIO2_DIR); + tmp &= ~mask; + writel(tmp, gpch->regbase + AU1000_GPIO2_DIR); + local_irq_restore(flags); + return 0; } +EXPORT_SYMBOL(au1000_gpio2_direction_input); -static int au1xxx_gpio2_direction_output(unsigned gpio, int value) +int au1000_gpio2_direction_output(struct gpio_chip *chip, + unsigned offset, int value) { - gpio -= AU1XXX_GPIO_BASE; - gpio2->dir |= 0x01 << gpio; - gpio2->output = (GPIO2_OUTPUT_ENABLE_MASK << gpio) | ((!!value) << gpio); + u32 mask = 1 << offset; + u32 out_mask = ((GPIO2_OUT_EN_MASK << offset) | (!!value << offset)); + u32 tmp; + struct au1000_gpio_chip *gpch; + unsigned long flags; + + gpch = container_of(chip, struct au1000_gpio_chip, chip); + + local_irq_save(flags); + tmp = readl(gpch->regbase + AU1000_GPIO2_DIR); + tmp |= mask; + writel(tmp, gpch->regbase + AU1000_GPIO2_DIR); + writel(out_mask, gpch->regbase + AU1000_GPIO2_OUT); + local_irq_restore(flags); + return 0; } - +EXPORT_SYMBOL(au1000_gpio2_direction_output); #endif /* !defined(CONFIG_SOC_AU1000) */ -static int au1xxx_gpio1_read(unsigned gpio) +int au1000_gpio1_get(struct gpio_chip *chip, unsigned offset) { - return (gpio1->pinstaterd >> gpio) & 0x01; + u32 mask = 1 << offset; + struct au1000_gpio_chip *gpch; + + gpch = container_of(chip, struct au1000_gpio_chip, chip); + return readl(gpch->regbase + AU1000_GPIO1_ST) & mask; } +EXPORT_SYMBOL(au1000_gpio1_get); -static void au1xxx_gpio1_write(unsigned gpio, int value) +void au1000_gpio1_set(struct gpio_chip *chip, + unsigned offset, int value) { + u32 mask = 1 << offset; + u32 reg_offset; + struct au1000_gpio_chip *gpch; + unsigned long flags; + + gpch = container_of(chip, struct au1000_gpio_chip, chip); + if (value) - gpio1->outputset = (0x01 << gpio); + reg_offset = AU1000_GPIO1_OUT; else - /* Output a zero */ - gpio1->outputclr = (0x01 << gpio); -} + reg_offset = AU1000_GPIO1_CLR; -static int au1xxx_gpio1_direction_input(unsigned gpio) -{ - gpio1->pininputen = (0x01 << gpio); - return 0; + local_irq_save(flags); + writel(mask, gpch->regbase + reg_offset); + local_irq_restore(flags); } +EXPORT_SYMBOL(au1000_gpio1_set); -static int au1xxx_gpio1_direction_output(unsigned gpio, int value) +int au1000_gpio1_direction_input(struct gpio_chip *chip, unsigned offset) { - gpio1->trioutclr = (0x01 & gpio); - au1xxx_gpio1_write(gpio, value); + u32 mask = 1 << offset; + struct au1000_gpio_chip *gpch; + + gpch = container_of(chip, struct au1000_gpio_chip, chip); + writel(mask, gpch->regbase + AU1000_GPIO1_ST); + return 0; } +EXPORT_SYMBOL(au1000_gpio1_direction_input); -int au1xxx_gpio_get_value(unsigned gpio) +int au1000_gpio1_direction_output(struct gpio_chip *chip, + unsigned offset, int value) { - if (gpio >= AU1XXX_GPIO_BASE) -#if defined(CONFIG_SOC_AU1000) - return 0; -#else - return au1xxx_gpio2_read(gpio); -#endif - else - return au1xxx_gpio1_read(gpio); -} -EXPORT_SYMBOL(au1xxx_gpio_get_value); + u32 mask = 1 << offset; + struct au1000_gpio_chip *gpch; -void au1xxx_gpio_set_value(unsigned gpio, int value) -{ - if (gpio >= AU1XXX_GPIO_BASE) -#if defined(CONFIG_SOC_AU1000) - ; -#else - au1xxx_gpio2_write(gpio, value); -#endif - else - au1xxx_gpio1_write(gpio, value); -} -EXPORT_SYMBOL(au1xxx_gpio_set_value); + gpch = container_of(chip, struct au1000_gpio_chip, chip); -int au1xxx_gpio_direction_input(unsigned gpio) -{ - if (gpio >= AU1XXX_GPIO_BASE) -#if defined(CONFIG_SOC_AU1000) - return -ENODEV; -#else - return au1xxx_gpio2_direction_input(gpio); -#endif + writel(mask, gpch->regbase + AU1000_GPIO1_TRI_OUT); + au1000_gpio1_set(chip, offset, value); - return au1xxx_gpio1_direction_input(gpio); + return 0; } -EXPORT_SYMBOL(au1xxx_gpio_direction_input); +EXPORT_SYMBOL(au1000_gpio1_direction_output); + +struct au1000_gpio_chip au1000_gpio_chip[] = { + [0] = { + .regbase = (void __iomem *)SYS_BASE, + .chip = { + .label = "au1000-gpio1", + .direction_input = au1000_gpio1_direction_input, + .direction_output = au1000_gpio1_direction_output, + .get = au1000_gpio1_get, + .set = au1000_gpio1_set, + .base = 0, + .ngpio = 32, + }, + }, +#if !defined(CONFIG_SOC_AU1000) + [1] = { + .regbase = (void __iomem *)GPIO2_BASE, + .chip = { + .label = "au1000-gpio2", + .direction_input = au1000_gpio2_direction_input, + .direction_output = au1000_gpio2_direction_output, + .get = au1000_gpio2_get, + .set = au1000_gpio2_set, + .base = AU1XXX_GPIO2_BASE, + .ngpio = 32, + }, + }, +#endif +}; -int au1xxx_gpio_direction_output(unsigned gpio, int value) +static int __init au1000_gpio_init(void) { - if (gpio >= AU1XXX_GPIO_BASE) -#if defined(CONFIG_SOC_AU1000) - return -ENODEV; -#else - return au1xxx_gpio2_direction_output(gpio, value); -#endif + gpiochip_add(&au1000_gpio_chip[0].chip); +#if !defined(CONFIG_SOC_AU1000) + gpiochip_add(&au1000_gpio_chip[1].chip); - return au1xxx_gpio1_direction_output(gpio, value); + return 0; +#endif } -EXPORT_SYMBOL(au1xxx_gpio_direction_output); +#ifndef CONFIG_AU1X00_NON_STD_GPIOS +arch_initcall(au1000_gpio_init); +#endif diff --git a/arch/mips/include/asm/mach-au1x00/gpio.h b/arch/mips/include/asm/mach-au1x00/gpio.h index 2dc61e0..f1a5d48 100644 --- a/arch/mips/include/asm/mach-au1x00/gpio.h +++ b/arch/mips/include/asm/mach-au1x00/gpio.h @@ -3,67 +3,31 @@ #include -#define AU1XXX_GPIO_BASE 200 +#define AU1XXX_GPIO2_BASE 200 -struct au1x00_gpio2 { - u32 dir; - u32 reserved; - u32 output; - u32 pinstate; - u32 inten; - u32 enable; -}; +/* GPIO bank 1 offsets */ +#define AU1000_GPIO1_TRI_OUT 0x0100 +#define AU1000_GPIO1_OUT 0x0108 +#define AU1000_GPIO1_ST 0x0110 +#define AU1000_GPIO1_CLR 0x010C -extern int au1xxx_gpio_get_value(unsigned gpio); -extern void au1xxx_gpio_set_value(unsigned gpio, int value); -extern int au1xxx_gpio_direction_input(unsigned gpio); -extern int au1xxx_gpio_direction_output(unsigned gpio, int value); +/* GPIO bank 2 offsets */ +#define AU1000_GPIO2_DIR 0x00 +#define AU1000_GPIO2_RSVD 0x04 +#define AU1000_GPIO2_OUT 0x08 +#define AU1000_GPIO2_ST 0x0C +#define AU1000_GPIO2_INT 0x10 +#define AU1000_GPIO2_EN 0x14 +#define GPIO2_OUT_EN_MASK 0x00010000 -/* Wrappers for the arch-neutral GPIO API */ +#define gpio_to_irq(gpio) NULL -static inline int gpio_request(unsigned gpio, const char *label) -{ - /* Not yet implemented */ - return 0; -} +#define gpio_get_value __gpio_get_value +#define gpio_set_value __gpio_set_value -static inline void gpio_free(unsigned gpio) -{ - /* Not yet implemented */ -} +#define gpio_cansleep __gpio_cansleep -static inline int gpio_direction_input(unsigned gpio) -{ - return au1xxx_gpio_direction_input(gpio); -} - -static inline int gpio_direction_output(unsigned gpio, int value) -{ - return au1xxx_gpio_direction_output(gpio, value); -} - -static inline int gpio_get_value(unsigned gpio) -{ - return au1xxx_gpio_get_value(gpio); -} - -static inline void gpio_set_value(unsigned gpio, int value) -{ - au1xxx_gpio_set_value(gpio, value); -} - -static inline int gpio_to_irq(unsigned gpio) -{ - return gpio; -} - -static inline int irq_to_gpio(unsigned irq) -{ - return irq; -} - -/* For cansleep */ #include #endif /* _AU1XXX_GPIO_H_ */ From mano@roarinelk.homelinux.net Tue Jan 27 09:47:17 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 27 Jan 2009 09:47:19 +0000 (GMT) Received: from fnoeppeil36.netpark.at ([217.175.205.164]:27034 "EHLO roarinelk.homelinux.net") by ftp.linux-mips.org with ESMTP id S20030929AbZA0JrR (ORCPT ); Tue, 27 Jan 2009 09:47:17 +0000 Received: (qmail 16192 invoked by uid 1000); 27 Jan 2009 10:47:16 +0100 Date: Tue, 27 Jan 2009 10:47:16 +0100 From: Manuel Lauss To: Florian Fainelli Cc: ralf@linux-mips.org, Linux-MIPS Subject: Re: [PATCH] au1000: convert to using gpiolib Message-ID: <20090127094716.GA16179@roarinelk.homelinux.net> References: <200901151646.49591.florian@openwrt.org> <200901262340.27613.florian@openwrt.org> <20090127065827.GA14985@roarinelk.homelinux.net> <200901271039.31680.florian@openwrt.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <200901271039.31680.florian@openwrt.org> User-Agent: Mutt/1.5.16 (2007-06-09) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21831 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mano@roarinelk.homelinux.net Precedence: bulk X-list: linux-mips Content-Length: 736 Lines: 23 On Tue, Jan 27, 2009 at 10:39:30AM +0100, Florian Fainelli wrote: > Le Tuesday 27 January 2009 07:58:27 Manuel Lauss, vous avez ?crit?: > > Florian, > > > > > Le Monday 19 January 2009 18:12:23 Florian Fainelli, vous avez ?crit?: > > > > This patch converts the GPIO board code to use gpiolib. > > > > Changes from v1: > > > > - allow users not to use the default gpio accessors > > > > - do not lock au1000_gpio2_set > > > > > > I did not receive comments from you on this patch, can I consider it > > > being ok ? > > > > Oh sorry. Please export all the au1000_gpioX_* functions and I'm happy. > > > > Thanks! > > Manuel Lauss > > Here we go. Thanks ! One last nit: please also add function prototypes to the gpio header. -- ml. From f.fainelli@gmail.com Tue Jan 27 10:03:12 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 27 Jan 2009 10:03:15 +0000 (GMT) Received: from nf-out-0910.google.com ([64.233.182.191]:62724 "EHLO nf-out-0910.google.com") by ftp.linux-mips.org with ESMTP id S21102775AbZA0KDM convert rfc822-to-8bit (ORCPT ); Tue, 27 Jan 2009 10:03:12 +0000 Received: by nf-out-0910.google.com with SMTP id h3so1839183nfh.14 for ; Tue, 27 Jan 2009 02:03:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:sender:from:to:subject:date :user-agent:cc:references:in-reply-to:mime-version:content-type :content-transfer-encoding:content-disposition:message-id; bh=9ZfxdmLarJeERWuWtcYbR7eOgLL4aarewr5Kq5g5WA0=; b=Gch0d67CoBqn9M7ujeqwOdpy0JsNpxyXA+uhRikivqJDWlNFs4cxqss04TjiM0lMrE 7tWYF9gCyKO8bUY2P17Yn9dJsC0Z+M7l9jqmzGYhOJ9IJJMBcchuaA5mCTsC6v4MwxZ+ 1Ou+CG1+ay/9AQX2zG00fAyeDXjPkDPFIX8wc= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=sender:from:to:subject:date:user-agent:cc:references:in-reply-to :mime-version:content-type:content-transfer-encoding :content-disposition:message-id; b=vehaowQvI9iQowi7/y8t/7eOxjn7gEqmb8R0Ipgz/yQ+HlDmyTb/4/a1tl5nx+uDbh t3h3WsFLHjbCLKSTVK6RD+5Qixb2r2Hp+y7WDS4y92NQtHckhSLmuXW0EI7131m8rUXb X2L8EYxRHy5F1skRD9cQ6cUmhw4iZEGiRXvpc= Received: by 10.86.91.3 with SMTP id o3mr578952fgb.35.1233050590646; Tue, 27 Jan 2009 02:03:10 -0800 (PST) Received: from lenovo.mimichou.home (florian.mimichou.net [82.241.112.26]) by mx.google.com with ESMTPS id l12sm9384111fgb.58.2009.01.27.02.03.08 (version=TLSv1/SSLv3 cipher=RC4-MD5); Tue, 27 Jan 2009 02:03:09 -0800 (PST) From: Florian Fainelli To: Manuel Lauss Subject: Re: [PATCH] au1000: convert to using gpiolib Date: Tue, 27 Jan 2009 11:02:36 +0100 User-Agent: KMail/1.9.9 Cc: ralf@linux-mips.org, Linux-MIPS References: <200901151646.49591.florian@openwrt.org> <200901271039.31680.florian@openwrt.org> <20090127094716.GA16179@roarinelk.homelinux.net> In-Reply-To: <20090127094716.GA16179@roarinelk.homelinux.net> MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 8BIT Content-Disposition: inline Message-Id: <200901271102.37230.florian@openwrt.org> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21832 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: florian@openwrt.org Precedence: bulk X-list: linux-mips Content-Length: 12089 Lines: 421 Le Tuesday 27 January 2009 10:47:16 Manuel Lauss, vous avez écrit : > On Tue, Jan 27, 2009 at 10:39:30AM +0100, Florian Fainelli wrote: > > Le Tuesday 27 January 2009 07:58:27 Manuel Lauss, vous avez ?crit?: > > > Florian, > > > > > > > Le Monday 19 January 2009 18:12:23 Florian Fainelli, vous avez ?crit?: > > > > > This patch converts the GPIO board code to use gpiolib. > > > > > Changes from v1: > > > > > - allow users not to use the default gpio accessors > > > > > - do not lock au1000_gpio2_set > > > > > > > > I did not receive comments from you on this patch, can I consider it > > > > being ok ? > > > > > > Oh sorry. Please export all the au1000_gpioX_* functions and I'm > > > happy. > > > > > > Thanks! > > > Manuel Lauss > > > > Here we go. Thanks ! > > One last nit: please also add function prototypes to the gpio header. Right, sorry about that. -- From: Florian Fainelli Subject: [PATCH v4] Alchemy: convert to gpiolib This patch converts Alchemy SoC GPIO code to use gpiolib instead of the old GENERIC_GPIO implementation. Changes from v3: - add function prototypes in gpio header Changes from v2: - export all gpio accessors so that custom boards can use them Changes from v1: - allow users not to use the default gpio accessors - do not lock au1000_gpio2_set Signed-off-by: Florian Fainelli --- diff --git a/arch/mips/alchemy/Kconfig b/arch/mips/alchemy/Kconfig index 7f8ef13..2fc5c13 100644 --- a/arch/mips/alchemy/Kconfig +++ b/arch/mips/alchemy/Kconfig @@ -135,3 +135,4 @@ config SOC_AU1X00 select SYS_SUPPORTS_32BIT_KERNEL select SYS_SUPPORTS_APM_EMULATION select GENERIC_HARDIRQS_NO__DO_IRQ + select ARCH_REQUIRE_GPIOLIB diff --git a/arch/mips/alchemy/common/gpio.c b/arch/mips/alchemy/common/gpio.c index e660ddd..535c565 100644 --- a/arch/mips/alchemy/common/gpio.c +++ b/arch/mips/alchemy/common/gpio.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2007, OpenWrt.org, Florian Fainelli + * Copyright (C) 2007-2009, OpenWrt.org, Florian Fainelli * Architecture specific GPIO support * * This program is free software; you can redistribute it and/or modify it @@ -27,122 +27,180 @@ * others have a second one : GPIO2 */ +#include #include +#include +#include +#include #include #include -#define gpio1 sys -#if !defined(CONFIG_SOC_AU1000) - -static struct au1x00_gpio2 *const gpio2 = (struct au1x00_gpio2 *) GPIO2_BASE; -#define GPIO2_OUTPUT_ENABLE_MASK 0x00010000 +struct au1000_gpio_chip { + struct gpio_chip chip; + void __iomem *regbase; +}; -static int au1xxx_gpio2_read(unsigned gpio) +#if !defined(CONFIG_SOC_AU1000) +int au1000_gpio2_get(struct gpio_chip *chip, unsigned offset) { - gpio -= AU1XXX_GPIO_BASE; - return ((gpio2->pinstate >> gpio) & 0x01); + u32 mask = 1 << offset; + struct au1000_gpio_chip *gpch; + + gpch = container_of(chip, struct au1000_gpio_chip, chip); + return readl(gpch->regbase + AU1000_GPIO2_ST) & mask; } +EXPORT_SYMBOL(au1000_gpio2_get); -static void au1xxx_gpio2_write(unsigned gpio, int value) +void au1000_gpio2_set(struct gpio_chip *chip, + unsigned offset, int value) { - gpio -= AU1XXX_GPIO_BASE; + u32 mask = ((GPIO2_OUT_EN_MASK << offset) | (!!value << offset)); + struct au1000_gpio_chip *gpch; - gpio2->output = (GPIO2_OUTPUT_ENABLE_MASK << gpio) | ((!!value) << gpio); + gpch = container_of(chip, struct au1000_gpio_chip, chip); + writel(mask, gpch->regbase + AU1000_GPIO2_OUT); } +EXPORT_SYMBOL(au1000_gpio2_set); -static int au1xxx_gpio2_direction_input(unsigned gpio) +int au1000_gpio2_direction_input(struct gpio_chip *chip, unsigned offset) { - gpio -= AU1XXX_GPIO_BASE; - gpio2->dir &= ~(0x01 << gpio); + u32 mask = 1 << offset; + u32 tmp; + struct au1000_gpio_chip *gpch; + unsigned long flags; + + gpch = container_of(chip, struct au1000_gpio_chip, chip); + + local_irq_save(flags); + tmp = readl(gpch->regbase + AU1000_GPIO2_DIR); + tmp &= ~mask; + writel(tmp, gpch->regbase + AU1000_GPIO2_DIR); + local_irq_restore(flags); + return 0; } +EXPORT_SYMBOL(au1000_gpio2_direction_input); -static int au1xxx_gpio2_direction_output(unsigned gpio, int value) +int au1000_gpio2_direction_output(struct gpio_chip *chip, + unsigned offset, int value) { - gpio -= AU1XXX_GPIO_BASE; - gpio2->dir |= 0x01 << gpio; - gpio2->output = (GPIO2_OUTPUT_ENABLE_MASK << gpio) | ((!!value) << gpio); + u32 mask = 1 << offset; + u32 out_mask = ((GPIO2_OUT_EN_MASK << offset) | (!!value << offset)); + u32 tmp; + struct au1000_gpio_chip *gpch; + unsigned long flags; + + gpch = container_of(chip, struct au1000_gpio_chip, chip); + + local_irq_save(flags); + tmp = readl(gpch->regbase + AU1000_GPIO2_DIR); + tmp |= mask; + writel(tmp, gpch->regbase + AU1000_GPIO2_DIR); + writel(out_mask, gpch->regbase + AU1000_GPIO2_OUT); + local_irq_restore(flags); + return 0; } - +EXPORT_SYMBOL(au1000_gpio2_direction_output); #endif /* !defined(CONFIG_SOC_AU1000) */ -static int au1xxx_gpio1_read(unsigned gpio) +int au1000_gpio1_get(struct gpio_chip *chip, unsigned offset) { - return (gpio1->pinstaterd >> gpio) & 0x01; + u32 mask = 1 << offset; + struct au1000_gpio_chip *gpch; + + gpch = container_of(chip, struct au1000_gpio_chip, chip); + return readl(gpch->regbase + AU1000_GPIO1_ST) & mask; } +EXPORT_SYMBOL(au1000_gpio1_get); -static void au1xxx_gpio1_write(unsigned gpio, int value) +void au1000_gpio1_set(struct gpio_chip *chip, + unsigned offset, int value) { + u32 mask = 1 << offset; + u32 reg_offset; + struct au1000_gpio_chip *gpch; + unsigned long flags; + + gpch = container_of(chip, struct au1000_gpio_chip, chip); + if (value) - gpio1->outputset = (0x01 << gpio); + reg_offset = AU1000_GPIO1_OUT; else - /* Output a zero */ - gpio1->outputclr = (0x01 << gpio); -} + reg_offset = AU1000_GPIO1_CLR; -static int au1xxx_gpio1_direction_input(unsigned gpio) -{ - gpio1->pininputen = (0x01 << gpio); - return 0; + local_irq_save(flags); + writel(mask, gpch->regbase + reg_offset); + local_irq_restore(flags); } +EXPORT_SYMBOL(au1000_gpio1_set); -static int au1xxx_gpio1_direction_output(unsigned gpio, int value) +int au1000_gpio1_direction_input(struct gpio_chip *chip, unsigned offset) { - gpio1->trioutclr = (0x01 & gpio); - au1xxx_gpio1_write(gpio, value); + u32 mask = 1 << offset; + struct au1000_gpio_chip *gpch; + + gpch = container_of(chip, struct au1000_gpio_chip, chip); + writel(mask, gpch->regbase + AU1000_GPIO1_ST); + return 0; } +EXPORT_SYMBOL(au1000_gpio1_direction_input); -int au1xxx_gpio_get_value(unsigned gpio) +int au1000_gpio1_direction_output(struct gpio_chip *chip, + unsigned offset, int value) { - if (gpio >= AU1XXX_GPIO_BASE) -#if defined(CONFIG_SOC_AU1000) - return 0; -#else - return au1xxx_gpio2_read(gpio); -#endif - else - return au1xxx_gpio1_read(gpio); -} -EXPORT_SYMBOL(au1xxx_gpio_get_value); + u32 mask = 1 << offset; + struct au1000_gpio_chip *gpch; -void au1xxx_gpio_set_value(unsigned gpio, int value) -{ - if (gpio >= AU1XXX_GPIO_BASE) -#if defined(CONFIG_SOC_AU1000) - ; -#else - au1xxx_gpio2_write(gpio, value); -#endif - else - au1xxx_gpio1_write(gpio, value); -} -EXPORT_SYMBOL(au1xxx_gpio_set_value); + gpch = container_of(chip, struct au1000_gpio_chip, chip); -int au1xxx_gpio_direction_input(unsigned gpio) -{ - if (gpio >= AU1XXX_GPIO_BASE) -#if defined(CONFIG_SOC_AU1000) - return -ENODEV; -#else - return au1xxx_gpio2_direction_input(gpio); -#endif + writel(mask, gpch->regbase + AU1000_GPIO1_TRI_OUT); + au1000_gpio1_set(chip, offset, value); - return au1xxx_gpio1_direction_input(gpio); + return 0; } -EXPORT_SYMBOL(au1xxx_gpio_direction_input); +EXPORT_SYMBOL(au1000_gpio1_direction_output); + +struct au1000_gpio_chip au1000_gpio_chip[] = { + [0] = { + .regbase = (void __iomem *)SYS_BASE, + .chip = { + .label = "au1000-gpio1", + .direction_input = au1000_gpio1_direction_input, + .direction_output = au1000_gpio1_direction_output, + .get = au1000_gpio1_get, + .set = au1000_gpio1_set, + .base = 0, + .ngpio = 32, + }, + }, +#if !defined(CONFIG_SOC_AU1000) + [1] = { + .regbase = (void __iomem *)GPIO2_BASE, + .chip = { + .label = "au1000-gpio2", + .direction_input = au1000_gpio2_direction_input, + .direction_output = au1000_gpio2_direction_output, + .get = au1000_gpio2_get, + .set = au1000_gpio2_set, + .base = AU1XXX_GPIO2_BASE, + .ngpio = 32, + }, + }, +#endif +}; -int au1xxx_gpio_direction_output(unsigned gpio, int value) +static int __init au1000_gpio_init(void) { - if (gpio >= AU1XXX_GPIO_BASE) -#if defined(CONFIG_SOC_AU1000) - return -ENODEV; -#else - return au1xxx_gpio2_direction_output(gpio, value); -#endif + gpiochip_add(&au1000_gpio_chip[0].chip); +#if !defined(CONFIG_SOC_AU1000) + gpiochip_add(&au1000_gpio_chip[1].chip); - return au1xxx_gpio1_direction_output(gpio, value); + return 0; +#endif } -EXPORT_SYMBOL(au1xxx_gpio_direction_output); +#ifndef CONFIG_AU1X00_NON_STD_GPIOS +arch_initcall(au1000_gpio_init); +#endif diff --git a/arch/mips/include/asm/mach-au1x00/gpio.h b/arch/mips/include/asm/mach-au1x00/gpio.h index 2dc61e0..099f70f 100644 --- a/arch/mips/include/asm/mach-au1x00/gpio.h +++ b/arch/mips/include/asm/mach-au1x00/gpio.h @@ -2,68 +2,42 @@ #define _AU1XXX_GPIO_H_ #include +#include -#define AU1XXX_GPIO_BASE 200 +#define AU1XXX_GPIO2_BASE 200 -struct au1x00_gpio2 { - u32 dir; - u32 reserved; - u32 output; - u32 pinstate; - u32 inten; - u32 enable; -}; +/* GPIO bank 1 offsets */ +#define AU1000_GPIO1_TRI_OUT 0x0100 +#define AU1000_GPIO1_OUT 0x0108 +#define AU1000_GPIO1_ST 0x0110 +#define AU1000_GPIO1_CLR 0x010C -extern int au1xxx_gpio_get_value(unsigned gpio); -extern void au1xxx_gpio_set_value(unsigned gpio, int value); -extern int au1xxx_gpio_direction_input(unsigned gpio); -extern int au1xxx_gpio_direction_output(unsigned gpio, int value); +/* GPIO bank 2 offsets */ +#define AU1000_GPIO2_DIR 0x00 +#define AU1000_GPIO2_RSVD 0x04 +#define AU1000_GPIO2_OUT 0x08 +#define AU1000_GPIO2_ST 0x0C +#define AU1000_GPIO2_INT 0x10 +#define AU1000_GPIO2_EN 0x14 +#define GPIO2_OUT_EN_MASK 0x00010000 -/* Wrappers for the arch-neutral GPIO API */ +#define gpio_to_irq(gpio) NULL -static inline int gpio_request(unsigned gpio, const char *label) -{ - /* Not yet implemented */ - return 0; -} +#define gpio_get_value __gpio_get_value +#define gpio_set_value __gpio_set_value -static inline void gpio_free(unsigned gpio) -{ - /* Not yet implemented */ -} +#define gpio_cansleep __gpio_cansleep -static inline int gpio_direction_input(unsigned gpio) -{ - return au1xxx_gpio_direction_input(gpio); -} - -static inline int gpio_direction_output(unsigned gpio, int value) -{ - return au1xxx_gpio_direction_output(gpio, value); -} - -static inline int gpio_get_value(unsigned gpio) -{ - return au1xxx_gpio_get_value(gpio); -} - -static inline void gpio_set_value(unsigned gpio, int value) -{ - au1xxx_gpio_set_value(gpio, value); -} - -static inline int gpio_to_irq(unsigned gpio) -{ - return gpio; -} - -static inline int irq_to_gpio(unsigned irq) -{ - return irq; -} - -/* For cansleep */ #include +int au1000_gpio2_get(struct gpio_chip *chip, unsigned offset); +void au1000_gpio2_set(struct gpio_chip *chip, unsigned offset, int value); +int au1000_gpio2_direction_input(struct gpio_chip *chip, unsigned offset); +int au1000_gpio2_direction_output(struct gpio_chip *chip, unsigned offset, int value); +int au1000_gpio1_get(struct gpio_chip *chip, unsigned offset); +void au1000_gpio1_set(struct gpio_chip *chip, unsigned offset, int value); +int au1000_gpio1_direction_input(struct gpio_chip *chip, unsigned offset); +int au1000_gpio1_direction_output(struct gpio_chip *chip, unsigned offset, int value); + #endif /* _AU1XXX_GPIO_H_ */ From mano@roarinelk.homelinux.net Tue Jan 27 10:11:13 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 27 Jan 2009 10:11:17 +0000 (GMT) Received: from fnoeppeil36.netpark.at ([217.175.205.164]:57043 "EHLO roarinelk.homelinux.net") by ftp.linux-mips.org with ESMTP id S21102776AbZA0KLN (ORCPT ); Tue, 27 Jan 2009 10:11:13 +0000 Received: (qmail 16361 invoked by uid 1000); 27 Jan 2009 11:11:12 +0100 Date: Tue, 27 Jan 2009 11:11:12 +0100 From: Manuel Lauss To: Florian Fainelli Cc: ralf@linux-mips.org, Linux-MIPS Subject: Re: [PATCH] au1000: convert to using gpiolib Message-ID: <20090127101112.GA16351@roarinelk.homelinux.net> References: <200901151646.49591.florian@openwrt.org> <200901271039.31680.florian@openwrt.org> <20090127094716.GA16179@roarinelk.homelinux.net> <200901271102.37230.florian@openwrt.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <200901271102.37230.florian@openwrt.org> User-Agent: Mutt/1.5.16 (2007-06-09) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21833 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mano@roarinelk.homelinux.net Precedence: bulk X-list: linux-mips Content-Length: 1600 Lines: 50 On Tue, Jan 27, 2009 at 11:02:36AM +0100, Florian Fainelli wrote: > Le Tuesday 27 January 2009 10:47:16 Manuel Lauss, vous avez ?crit?: > > On Tue, Jan 27, 2009 at 10:39:30AM +0100, Florian Fainelli wrote: > > > Le Tuesday 27 January 2009 07:58:27 Manuel Lauss, vous avez ?crit?: > > > > Florian, > > > > > > > > > Le Monday 19 January 2009 18:12:23 Florian Fainelli, vous avez ?crit?: > > > > > > This patch converts the GPIO board code to use gpiolib. > > > > > > Changes from v1: > > > > > > - allow users not to use the default gpio accessors > > > > > > - do not lock au1000_gpio2_set > > > > > > > > > > I did not receive comments from you on this patch, can I consider it > > > > > being ok ? > > > > > > > > Oh sorry. Please export all the au1000_gpioX_* functions and I'm > > > > happy. > > > > > > > > Thanks! > > > > Manuel Lauss > > > > > > Here we go. Thanks ! > > > > One last nit: please also add function prototypes to the gpio header. > > Right, sorry about that. > -- > From: Florian Fainelli > Subject: [PATCH v4] Alchemy: convert to gpiolib > > This patch converts Alchemy SoC GPIO code to use > gpiolib instead of the old GENERIC_GPIO implementation. > > Changes from v3: > - add function prototypes in gpio header > > Changes from v2: > - export all gpio accessors so that custom boards can use them > > Changes from v1: > - allow users not to use the default gpio accessors > - do not lock au1000_gpio2_set > > Signed-off-by: Florian Fainelli Acked-by: Manuel Lauss Thank you! Manuel Lauss From linux-mips@kernelport.de Tue Jan 27 10:13:11 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 27 Jan 2009 10:13:13 +0000 (GMT) Received: from mail.bugwerft.de ([212.112.241.193]:53703 "EHLO mail.bugwerft.de") by ftp.linux-mips.org with ESMTP id S21102776AbZA0KNL (ORCPT ); Tue, 27 Jan 2009 10:13:11 +0000 Received: from localhost (localhost.localdomain [127.0.0.1]) by mail.bugwerft.de (Postfix) with ESMTP id 6554449400C; Tue, 27 Jan 2009 11:13:05 +0100 (CET) Received: from mail.bugwerft.de ([127.0.0.1]) by localhost (mail.bugwerft.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 5PLGHENaW6NQ; Tue, 27 Jan 2009 11:13:05 +0100 (CET) Received: from [10.1.1.26] (unknown [192.168.22.14]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.bugwerft.de (Postfix) with ESMTP id 9A47C49400B; Tue, 27 Jan 2009 11:13:03 +0100 (CET) Subject: Re: AU1550 Kernel bug detected[#1] clockevents_register_device From: Frank Neuber To: Manuel Lauss , Florian Fainelli Cc: Linux-MIPS In-Reply-To: <20090127091107.GA15890@roarinelk.homelinux.net> References: <1233045842.28527.459.camel@t60p> <20090127091107.GA15890@roarinelk.homelinux.net> Content-Type: text/plain Date: Tue, 27 Jan 2009 11:13:01 +0100 Message-Id: <1233051181.28527.485.camel@t60p> Mime-Version: 1.0 X-Mailer: Evolution 2.12.1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21834 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: linux-mips@kernelport.de Precedence: bulk X-list: linux-mips Content-Length: 4339 Lines: 99 Thank you all, now the head kernel comes up. Why is that fix not in the git? Maby I use the wrong git repository for MIPS kernel. At the moment I use the linus git: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git Am Dienstag, den 27.01.2009, 10:11 +0100 schrieb Manuel Lauss: > > I just start with head and found a compile error: > > arch/mips/alchemy/common/time.c:93: error: incompatible types in > > initialization > > I comment this line ".cpumask = CPU_MASK_ALL," > > you need to change it to "CPU_MASK_ALL_PTR". Commenting it is not a very > good idea ;-) Yea sure, but it was a try ... ;-) The PCI and PCMCIA problems are going on in the same way: I tested the CardBus. As you can see the two CardBus bridges maps the whole PCI memory into. If I plug in something it is not accessable because the yenta_cardbus 0000:00:0d.0: No cardbus resource! error ... I think somting is wrong with PCI resource management here. I can't believe that nobody is using the PCI or Cardbus on the AU1550 with the current kernel. I can give you a lspci -vvv of the working system 2.6.16.1 ---cut--- 00:0d.0 Class 0607: 104c:ac55 (rev 01) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- SERR- Reset+ 16bInt- PostWrite- 16-bit legacy interface ports at 0001 ---cut--- And the 2.6.29-rc2 ---cut--- 00:0d.0 Class 0607: 104c:ac55 (rev 01) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- Status: Cap+ 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- SERR- Reset+ 16bInt- PostWrite- 16-bit legacy interface ports at 0001 ---cut--- You can see in the current PCI System the Region 0 is missing and the Memory windows are much more bigger. Also the IRQ is different. I don't understand this at the moment. This is the relevant bootlog: ---cut--- pci 0000:00:0c.0: PME# supported from D1 D3hot D3cold pci 0000:00:0c.0: PME# disabled pci 0000:00:0c.1: PME# supported from D1 D3hot D3cold pci 0000:00:0c.1: PME# disabled pci 0000:00:0c.2: PME# supported from D0 D1 D2 D3hot D3cold pci 0000:00:0c.2: PME# disabled pci 0000:00:0d.0: PME# supported from D0 D1 D2 D3hot D3cold pci 0000:00:0d.0: PME# disabled pci 0000:00:0d.1: PME# supported from D0 D1 D2 D3hot D3cold pci 0000:00:0d.1: PME# disabled pci 0000:00:0c.0: BAR 0: can't allocate mem resource [0x50000000-0x4fffffff] pci 0000:00:0c.1: BAR 0: can't allocate mem resource [0x50000000-0x4fffffff] pci 0000:00:0d.0: BAR 0: can't allocate mem resource [0x50000000-0x4fffffff] pci 0000:00:0d.1: BAR 0: can't allocate mem resource [0x50000000-0x4fffffff] pci 0000:00:0c.2: BAR 0: can't allocate mem resource [0x50000000-0x4fffffff] pci 0000:00:0d.0: CardBus bridge, secondary bus 0000:01 pci 0000:00:0d.0: IO window: 0x001000-0x0010ff pci 0000:00:0d.0: IO window: 0x001400-0x0014ff pci 0000:00:0d.0: PREFETCH window: 0x40000000-0x43ffffff pci 0000:00:0d.0: MEM window: 0x44000000-0x47ffffff pci 0000:00:0d.1: CardBus bridge, secondary bus 0000:05 pci 0000:00:0d.1: IO window: 0x001800-0x0018ff pci 0000:00:0d.1: IO window: 0x001c00-0x001cff pci 0000:00:0d.1: PREFETCH window: 0x48000000-0x4bffffff pci 0000:00:0d.1: MEM window: 0x4c000000-0x4fffffff PCI: Enabling device 0000:00:0d.0 (0000 -> 0003) PCI: Enabling device 0000:00:0d.1 (0000 -> 0003) ---cut--- From mano@roarinelk.homelinux.net Tue Jan 27 12:11:25 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 27 Jan 2009 12:11:27 +0000 (GMT) Received: from fnoeppeil36.netpark.at ([217.175.205.164]:11175 "EHLO roarinelk.homelinux.net") by ftp.linux-mips.org with ESMTP id S21102885AbZA0MLZ (ORCPT ); Tue, 27 Jan 2009 12:11:25 +0000 Received: (qmail 17157 invoked by uid 1000); 27 Jan 2009 13:11:23 +0100 Date: Tue, 27 Jan 2009 13:11:23 +0100 From: Manuel Lauss To: Frank Neuber Cc: Florian Fainelli , Linux-MIPS Subject: Re: AU1550 Kernel bug detected[#1] clockevents_register_device Message-ID: <20090127121123.GA17132@roarinelk.homelinux.net> References: <1233045842.28527.459.camel@t60p> <20090127091107.GA15890@roarinelk.homelinux.net> <1233051181.28527.485.camel@t60p> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1233051181.28527.485.camel@t60p> User-Agent: Mutt/1.5.16 (2007-06-09) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21835 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mano@roarinelk.homelinux.net Precedence: bulk X-list: linux-mips Content-Length: 1433 Lines: 37 On Tue, Jan 27, 2009 at 11:13:01AM +0100, Frank Neuber wrote: > Thank you all, > now the head kernel comes up. > Why is that fix not in the git? Maby I use the wrong git repository for > MIPS kernel. At the moment I use the linus git: > git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6.git I sent a patch for this 2 weeks ago; Ralf is probably busy with other stuff atm. > Am Dienstag, den 27.01.2009, 10:11 +0100 schrieb Manuel Lauss: > > > I just start with head and found a compile error: > > > arch/mips/alchemy/common/time.c:93: error: incompatible types in > > > initialization > > > I comment this line ".cpumask = CPU_MASK_ALL," > > > > you need to change it to "CPU_MASK_ALL_PTR". Commenting it is not a very > > good idea ;-) > Yea sure, but it was a try ... ;-) > > The PCI and PCMCIA problems are going on in the same way: > I tested the CardBus. As you can see the two CardBus bridges maps the > whole PCI memory into. If I plug in something it is not accessable > because the > yenta_cardbus 0000:00:0d.0: No cardbus resource! > error ... > I think somting is wrong with PCI resource management here. > I can't believe that nobody is using the PCI or Cardbus on the AU1550 > with the current kernel. I'm no PCI expert, but I'm pretty sure resource assignment is done by generic, not mips-specific, code. Please try the linux-pci and/or linux-kernel lists. Beste Gruesse, Manuel Lauss From linux-mips@kernelport.de Tue Jan 27 12:42:51 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 27 Jan 2009 12:42:53 +0000 (GMT) Received: from mail.bugwerft.de ([212.112.241.193]:26581 "EHLO mail.bugwerft.de") by ftp.linux-mips.org with ESMTP id S21103021AbZA0Mmt (ORCPT ); Tue, 27 Jan 2009 12:42:49 +0000 Received: from localhost (localhost.localdomain [127.0.0.1]) by mail.bugwerft.de (Postfix) with ESMTP id 7ED9749400C; Tue, 27 Jan 2009 13:42:43 +0100 (CET) Received: from mail.bugwerft.de ([127.0.0.1]) by localhost (mail.bugwerft.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 7J0YABQ8XiUW; Tue, 27 Jan 2009 13:42:43 +0100 (CET) Received: from [10.1.1.26] (unknown [192.168.22.14]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.bugwerft.de (Postfix) with ESMTP id 477A049400B; Tue, 27 Jan 2009 13:42:42 +0100 (CET) Subject: Re: AU1550 Kernel bug detected[#1] clockevents_register_device From: Frank Neuber To: Manuel Lauss Cc: Florian Fainelli , Linux-MIPS In-Reply-To: <20090127121123.GA17132@roarinelk.homelinux.net> References: <1233045842.28527.459.camel@t60p> <20090127091107.GA15890@roarinelk.homelinux.net> <1233051181.28527.485.camel@t60p> <20090127121123.GA17132@roarinelk.homelinux.net> Content-Type: text/plain Date: Tue, 27 Jan 2009 13:42:40 +0100 Message-Id: <1233060160.28527.497.camel@t60p> Mime-Version: 1.0 X-Mailer: Evolution 2.12.1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21836 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: linux-mips@kernelport.de Precedence: bulk X-list: linux-mips Content-Length: 823 Lines: 25 Am Dienstag, den 27.01.2009, 13:11 +0100 schrieb Manuel Lauss: > > I think somting is wrong with PCI resource management here. > > I can't believe that nobody is using the PCI or Cardbus on the AU1550 > > with the current kernel. > > I'm no PCI expert, but I'm pretty sure resource assignment is done by > generic, not mips-specific, code. Please try the linux-pci and/or > linux-kernel lists. At the moment I buld a matrix of working kernel versions regarding the PCI stuff on the AU1550 For now I can say that the versions 2.6.18, 2.6.18-rc1 is crashing after showing the linux banner 2.6.18-rc2, 2.6.18-rc4, 2.6.19, 2.6.20, 2.6.23 produce this: Skipping PCI bus scan due to resource conflict The version 2.6.24 has the same behavior as the current git head. I will inform you about more results Regards, Frank From drow@false.org Tue Jan 27 15:29:27 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 27 Jan 2009 15:29:30 +0000 (GMT) Received: from NaN.false.org ([208.75.86.248]:26517 "EHLO nan.false.org") by ftp.linux-mips.org with ESMTP id S21103021AbZA0P31 (ORCPT ); Tue, 27 Jan 2009 15:29:27 +0000 Received: from nan.false.org (localhost [127.0.0.1]) by nan.false.org (Postfix) with ESMTP id 440A810A3F; Tue, 27 Jan 2009 15:29:25 +0000 (GMT) Received: from caradoc.them.org (209.195.188.212.nauticom.net [209.195.188.212]) by nan.false.org (Postfix) with ESMTP id 02F1410A2F; Tue, 27 Jan 2009 15:29:25 +0000 (GMT) Received: from drow by caradoc.them.org with local (Exim 4.69) (envelope-from ) id 1LRpsS-0006Vw-94; Tue, 27 Jan 2009 10:29:24 -0500 Date: Tue, 27 Jan 2009 10:29:24 -0500 From: Daniel Jacobowitz To: Kumba Cc: libc-ports@sources.redhat.com, Linux MIPS List Subject: Re: [PATCH]: R10000 Needs LL/SC Workaround in Glibc Message-ID: <20090127152924.GA16379@caradoc.them.org> References: <490A912A.8030901@gentoo.org> <490C907A.40005@loowit.net> <4928D912.4050103@gentoo.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <4928D912.4050103@gentoo.org> User-Agent: Mutt/1.5.17 (2008-05-11) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21837 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dan@debian.org Precedence: bulk X-list: linux-mips Content-Length: 1516 Lines: 41 On Sat, Nov 22, 2008 at 11:16:18PM -0500, Kumba wrote: > Here's try #2. The gcc-side is already sent in and accepted. If I'm > still missing anything, please let me know! > > Joshua Kinard > Gentoo/MIPS > kumba@gentoo.org > > > 2008-11-22 Joshua Kinard > > * ports/sysdeps/mips/bits/atomic.h > (R10K_BEQZ_INSN, R10K_NOPS_INSN): Define depending on ISA. > (__arch_compare_and_exchange_xxx_32_int): Replace 'beqz' insn with > R10K_BEQZ_INSN and add R10K_NOPS_INSN. > (__arch_compare_and_exchange_xxx_64_int): Likewise > (__arch_exchange_xxx_32_int): Likewise > (__arch_exchange_xxx_64_int): Likewise > (__arch_exchange_and_add_32_int): Likewise > (__arch_exchange_and_add_64_int): Likewise Thinking about this... MIPS I: 28 NOPs is really horrid. Not so much on this processor if the code is all in cache, but I guess that older/simpler processors are going to sit for a number of cycles chewing through those NOPs. Are distributions still building MIPS I code? Can we assume that people who want to run glibc on an R10K can at least get something for MIPS II? MIPS II, MIPS III, MIPS IV: Using beqzl does not seem particularly horrid - although it's still a shame since this branch is in fact anti-likely. It will almost never be taken. Other platforms: !(MIPS II or MIPS III or MIPS IV) is not the same as (MIPS I)! Please don't activate this workaround on builds that won't run on an R10K, like MIPS32. -- Daniel Jacobowitz CodeSourcery From macro@linux-mips.org Tue Jan 27 16:13:40 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 27 Jan 2009 16:13:43 +0000 (GMT) Received: from localhost.localdomain ([127.0.0.1]:13278 "EHLO localhost.localdomain") by ftp.linux-mips.org with ESMTP id S21103021AbZA0QNk (ORCPT ); Tue, 27 Jan 2009 16:13:40 +0000 Date: Tue, 27 Jan 2009 16:13:40 +0000 (GMT) From: "Maciej W. Rozycki" To: Daniel Jacobowitz cc: Kumba , libc-ports@sources.redhat.com, Linux MIPS List Subject: Re: [PATCH]: R10000 Needs LL/SC Workaround in Glibc In-Reply-To: <20090127152924.GA16379@caradoc.them.org> Message-ID: References: <490A912A.8030901@gentoo.org> <490C907A.40005@loowit.net> <4928D912.4050103@gentoo.org> <20090127152924.GA16379@caradoc.them.org> User-Agent: Alpine 1.10 (LFD 962 2008-03-14) MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21838 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: macro@linux-mips.org Precedence: bulk X-list: linux-mips Content-Length: 1863 Lines: 43 On Tue, 27 Jan 2009, Daniel Jacobowitz wrote: > > 2008-11-22 Joshua Kinard > > > > * ports/sysdeps/mips/bits/atomic.h > > (R10K_BEQZ_INSN, R10K_NOPS_INSN): Define depending on ISA. > > (__arch_compare_and_exchange_xxx_32_int): Replace 'beqz' insn with > > R10K_BEQZ_INSN and add R10K_NOPS_INSN. > > (__arch_compare_and_exchange_xxx_64_int): Likewise > > (__arch_exchange_xxx_32_int): Likewise > > (__arch_exchange_xxx_64_int): Likewise > > (__arch_exchange_and_add_32_int): Likewise > > (__arch_exchange_and_add_64_int): Likewise > > Thinking about this... > > MIPS I: 28 NOPs is really horrid. Not so much on this processor if > the code is all in cache, but I guess that older/simpler processors > are going to sit for a number of cycles chewing through those NOPs. > Are distributions still building MIPS I code? Can we assume that > people who want to run glibc on an R10K can at least get something > for MIPS II? I agree this is horrible. I would rather not have a workaround for a broken chip in the official sources at all than badly hit good chips (comprising the vast majority). Unless this can be made a compile-time option, so that whoever is interested in it can use "-march=mips1 -mfix-r10000" or suchlike to get it activated, I am against the change. > MIPS II, MIPS III, MIPS IV: Using beqzl does not seem particularly > horrid - although it's still a shame since this branch is in fact > anti-likely. It will almost never be taken. Again if only "-march=mips2 -mfix-r10000" etc. activates it, then I am fine with that, otherwise it is a no-no for me. > Other platforms: !(MIPS II or MIPS III or MIPS IV) is not the same as > (MIPS I)! Please don't activate this workaround on builds that won't > run on an R10K, like MIPS32. Nothing to add here. ;) Maciej From laurent@guerby.net Tue Jan 27 17:49:16 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 27 Jan 2009 17:49:19 +0000 (GMT) Received: from 39.mail-out.ovh.net ([213.251.138.60]:60607 "HELO 39.mail-out.ovh.net") by ftp.linux-mips.org with SMTP id S21103029AbZA0RtQ (ORCPT ); Tue, 27 Jan 2009 17:49:16 +0000 Received: (qmail 16194 invoked by uid 503); 27 Jan 2009 17:49:36 -0000 Received: from b6.ovh.net (HELO mail148.ha.ovh.net) (213.186.33.56) by 39.mail-out.ovh.net with SMTP; 27 Jan 2009 17:49:36 -0000 Received: from b0.ovh.net (HELO queue-out) (213.186.33.50) by b0.ovh.net with SMTP; 27 Jan 2009 17:49:00 -0000 Received: from unknown (HELO ?192.168.1.101?) (laurent%guerby.net@79.90.156.11) by ns0.ovh.net with SMTP; 27 Jan 2009 17:48:57 -0000 Subject: IP35 Origin 300/3000 support? From: Laurent GUERBY To: Linux MIPS List , Debian MIPS Content-Type: text/plain Date: Tue, 27 Jan 2009 18:49:10 +0100 Message-Id: <1233078550.17541.573.camel@localhost> Mime-Version: 1.0 X-Mailer: Evolution 2.24.2 Content-Transfer-Encoding: 7bit X-Ovh-Tracer-Id: 5262737641428491939 X-Ovh-Remote: 79.90.156.11 () X-Ovh-Local: 213.186.33.20 (ns0.ovh.net) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21839 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: laurent@guerby.net Precedence: bulk X-list: linux-mips Content-Length: 364 Lines: 20 Hi, The wiki page: http://www.linux-mips.org/wiki/IP35 states "IP35 is not yet supported by Linux. A port initially targeting only the Origin 300 has been started". The last edit of the wiki was in 2007, does anyone know if it is now supported by Linux/Debian? Would access to hardware help? Thanks in advance, Laurent http://gcc.gnu.org/wiki/CompileFarm From David.Daney@caviumnetworks.com Tue Jan 27 17:51:42 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 27 Jan 2009 17:51:44 +0000 (GMT) Received: from mail3.caviumnetworks.com ([12.108.191.235]:5362 "EHLO mail3.caviumnetworks.com") by ftp.linux-mips.org with ESMTP id S21103029AbZA0Rvm (ORCPT ); Tue, 27 Jan 2009 17:51:42 +0000 Received: from exch4.caveonetworks.com (Not Verified[192.168.16.23]) by mail3.caviumnetworks.com with MailMarshal (v6,2,2,3503) id ; Tue, 27 Jan 2009 12:49:36 -0500 Received: from exch4.caveonetworks.com ([192.168.16.23]) by exch4.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Tue, 27 Jan 2009 09:48:34 -0800 Received: from dd1.caveonetworks.com ([64.169.86.201]) by exch4.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Tue, 27 Jan 2009 09:48:34 -0800 Message-ID: <497F48F2.90309@caviumnetworks.com> Date: Tue, 27 Jan 2009 09:48:34 -0800 From: David Daney User-Agent: Thunderbird 2.0.0.19 (X11/20090105) MIME-Version: 1.0 To: Andrew Morton , Linus Torvalds CC: Linux Kernel Mailing List , linux-mips , Mike Travis Subject: [Resend PATCH 0/2] cpumask fallout: Initialize irq_default_affinity earlier et al. (v3) Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 27 Jan 2009 17:48:34.0161 (UTC) FILETIME=[79695610:01C980A7] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21840 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Content-Length: 2258 Lines: 56 This seems to have fallen through the cracks, so I am resending: Now that mips/OCTEON support has been merged, this patch set has slightly more urgency. The interrupt affinity on OCTEON is determined by irq_default_affinity, as that is what the code in kernel/irq/manage.c uses to set affinity. Since for the majority of devices (Serial, Compact Flash, Network...) we want interrupts to be handled on a single CPU, we set irq_default_affinity to the boot CPU in init_IRQ(). The problem we have is that with the new cpumask infrastructure, irq_default_affinity is being initialized in core_initcall which undoes our initialization. As I said in 2/2: Move the initialization of irq_default_affinity to early_irq_init as core_initcall is too late. irq_default_affinity can be used in init_IRQ and potentially timer and SMP init as well. All of these happen before core_initcall. Moving the initialization to early_irq_init ensures that it is initialized before it is used. Mike Travis pointed out that irq_default_affinity depends on CONFIG_GENERIC_HARDIRQS in addition to CONFIG_SMP. So to make things consistent, I added 1/2 so that the irq_*_affinity functions and irq_default_affinity are defined for the same conditions that they are declared. I Took Linus' suggestion to move init_irq_default_affinity over to kernel/irq/handle.c, however due to the way that cpumask_*() are defined, it is still necessary to have the ugly ifdefs, but now they are localized to init_irq_default_affinity. Mike Travis also suggested that alloc_bootmem_cpumask_var() be used in preference to alloc_cpumask_var, so I incorporated that suggestion as well. I tested both with and without CONFIG_SMP, on mips/cavium_octeon, Mike tested a similar(but not identical patch) on x86_64. Changes from v2 of this set are just a small rearrangement of the #ifdefs suggested by Ihar Hrachyshka that make the code look a bit cleaner. I will reply with the two patches. David Daney (2): Make irq_*_affinity depend on CONFIG_GENERIC_HARDIRQS too. cpumask fallout: Initialize irq_default_affinity earlier (v3). kernel/irq/handle.c | 16 ++++++++++++++++ kernel/irq/manage.c | 10 +--------- 2 files changed, 17 insertions(+), 9 deletions(-) From David.Daney@caviumnetworks.com Tue Jan 27 17:54:15 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 27 Jan 2009 17:54:18 +0000 (GMT) Received: from mail3.caviumnetworks.com ([12.108.191.235]:14325 "EHLO mail3.caviumnetworks.com") by ftp.linux-mips.org with ESMTP id S21103029AbZA0RyP (ORCPT ); Tue, 27 Jan 2009 17:54:15 +0000 Received: from exch4.caveonetworks.com (Not Verified[192.168.16.23]) by mail3.caviumnetworks.com with MailMarshal (v6,2,2,3503) id ; Tue, 27 Jan 2009 12:53:42 -0500 Received: from exch4.caveonetworks.com ([192.168.16.23]) by exch4.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Tue, 27 Jan 2009 09:53:29 -0800 Received: from dd1.caveonetworks.com ([64.169.86.201]) by exch4.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Tue, 27 Jan 2009 09:53:29 -0800 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.2/8.14.2) with ESMTP id n0RHrP1p024139; Tue, 27 Jan 2009 09:53:25 -0800 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.2/8.14.2/Submit) id n0RHrPtY024138; Tue, 27 Jan 2009 09:53:25 -0800 From: David Daney To: torvalds@linux-foundation.org, akpm@linux-foundation.org Cc: linux-kernel@vger.kernel.org, linux-mips@linux-mips.org, travis@sgi.com, David Daney Subject: [PATCH 2/2] cpumask fallout: Initialize irq_default_affinity earlier (v3). Date: Tue, 27 Jan 2009 09:53:22 -0800 Message-Id: <1233078802-24111-2-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.5.6.6 In-Reply-To: <497F48F2.90309@caviumnetworks.com> References: <497F48F2.90309@caviumnetworks.com> X-OriginalArrivalTime: 27 Jan 2009 17:53:29.0561 (UTC) FILETIME=[297BCC90:01C980A8] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21841 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Content-Length: 2151 Lines: 78 Move the initialization of irq_default_affinity to early_irq_init as core_initcall is too late. irq_default_affinity can be used in init_IRQ and potentially timer and SMP init as well. All of these happen before core_initcall. Moving the initialization to early_irq_init ensures that it is initialized before it is used. Signed-off-by: David Daney Acked-by: Mike Travis --- kernel/irq/handle.c | 16 ++++++++++++++++ kernel/irq/manage.c | 8 -------- 2 files changed, 16 insertions(+), 8 deletions(-) diff --git a/kernel/irq/handle.c b/kernel/irq/handle.c index c20db0b..3aba8d1 100644 --- a/kernel/irq/handle.c +++ b/kernel/irq/handle.c @@ -39,6 +39,18 @@ void handle_bad_irq(unsigned int irq, struct irq_desc *desc) ack_bad_irq(irq); } +#if defined(CONFIG_SMP) && defined(CONFIG_GENERIC_HARDIRQS) +static void __init init_irq_default_affinity(void) +{ + alloc_bootmem_cpumask_var(&irq_default_affinity); + cpumask_setall(irq_default_affinity); +} +#else +static void __init init_irq_default_affinity(void) +{ +} +#endif + /* * Linux has a controller-independent interrupt architecture. * Every controller has a 'controller-template', that is used @@ -134,6 +146,8 @@ int __init early_irq_init(void) int legacy_count; int i; + init_irq_default_affinity(); + desc = irq_desc_legacy; legacy_count = ARRAY_SIZE(irq_desc_legacy); @@ -219,6 +233,8 @@ int __init early_irq_init(void) int count; int i; + init_irq_default_affinity(); + desc = irq_desc; count = ARRAY_SIZE(irq_desc); diff --git a/kernel/irq/manage.c b/kernel/irq/manage.c index 618a64f..291f036 100644 --- a/kernel/irq/manage.c +++ b/kernel/irq/manage.c @@ -18,14 +18,6 @@ #if defined(CONFIG_SMP) && defined(CONFIG_GENERIC_HARDIRQS) cpumask_var_t irq_default_affinity; -static int init_irq_default_affinity(void) -{ - alloc_cpumask_var(&irq_default_affinity, GFP_KERNEL); - cpumask_setall(irq_default_affinity); - return 0; -} -core_initcall(init_irq_default_affinity); - /** * synchronize_irq - wait for pending IRQ handlers (on other CPUs) * @irq: interrupt number to wait for -- 1.5.6.6 From David.Daney@caviumnetworks.com Tue Jan 27 17:54:35 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 27 Jan 2009 17:54:37 +0000 (GMT) Received: from mail3.caviumnetworks.com ([12.108.191.235]:14581 "EHLO mail3.caviumnetworks.com") by ftp.linux-mips.org with ESMTP id S21103417AbZA0RyQ (ORCPT ); Tue, 27 Jan 2009 17:54:16 +0000 Received: from exch4.caveonetworks.com (Not Verified[192.168.16.23]) by mail3.caviumnetworks.com with MailMarshal (v6,2,2,3503) id ; Tue, 27 Jan 2009 12:53:42 -0500 Received: from exch4.caveonetworks.com ([192.168.16.23]) by exch4.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Tue, 27 Jan 2009 09:53:29 -0800 Received: from dd1.caveonetworks.com ([64.169.86.201]) by exch4.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Tue, 27 Jan 2009 09:53:29 -0800 Received: from dd1.caveonetworks.com (localhost.localdomain [127.0.0.1]) by dd1.caveonetworks.com (8.14.2/8.14.2) with ESMTP id n0RHrOrr024135; Tue, 27 Jan 2009 09:53:24 -0800 Received: (from ddaney@localhost) by dd1.caveonetworks.com (8.14.2/8.14.2/Submit) id n0RHrMTM024133; Tue, 27 Jan 2009 09:53:22 -0800 From: David Daney To: torvalds@linux-foundation.org, akpm@linux-foundation.org Cc: linux-kernel@vger.kernel.org, linux-mips@linux-mips.org, travis@sgi.com, David Daney Subject: [PATCH 1/2] Make irq_*_affinity depend on CONFIG_GENERIC_HARDIRQS too. Date: Tue, 27 Jan 2009 09:53:21 -0800 Message-Id: <1233078802-24111-1-git-send-email-ddaney@caviumnetworks.com> X-Mailer: git-send-email 1.5.6.6 In-Reply-To: <497F48F2.90309@caviumnetworks.com> References: <497F48F2.90309@caviumnetworks.com> X-OriginalArrivalTime: 27 Jan 2009 17:53:29.0561 (UTC) FILETIME=[297BCC90:01C980A8] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21842 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Content-Length: 636 Lines: 25 In interrupt.h these functions are declared only if CONFIG_GENERIC_HARDIRQS is set. We should define them under identical conditions. Signed-off-by: David Daney --- kernel/irq/manage.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/kernel/irq/manage.c b/kernel/irq/manage.c index cd0cd8d..618a64f 100644 --- a/kernel/irq/manage.c +++ b/kernel/irq/manage.c @@ -15,7 +15,7 @@ #include "internals.h" -#ifdef CONFIG_SMP +#if defined(CONFIG_SMP) && defined(CONFIG_GENERIC_HARDIRQS) cpumask_var_t irq_default_affinity; static int init_irq_default_affinity(void) -- 1.5.6.6 From ralf@h5.dl5rb.org.uk Tue Jan 27 18:58:07 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 27 Jan 2009 18:58:10 +0000 (GMT) Received: from h5.dl5rb.org.uk ([81.2.74.5]:35544 "EHLO h5.dl5rb.org.uk") by ftp.linux-mips.org with ESMTP id S21103358AbZA0S6H (ORCPT ); Tue, 27 Jan 2009 18:58:07 +0000 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id n0RIw3Xu005155; Tue, 27 Jan 2009 18:58:04 GMT Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id n0RIvxAp005151; Tue, 27 Jan 2009 18:57:59 GMT Date: Tue, 27 Jan 2009 18:57:59 +0000 From: Ralf Baechle To: Laurent GUERBY Cc: Linux MIPS List , Debian MIPS Subject: Re: IP35 Origin 300/3000 support? Message-ID: <20090127185759.GA2234@linux-mips.org> References: <1233078550.17541.573.camel@localhost> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1233078550.17541.573.camel@localhost> User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21843 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Content-Length: 912 Lines: 26 On Tue, Jan 27, 2009 at 06:49:10PM +0100, Laurent GUERBY wrote: > The wiki page: > > http://www.linux-mips.org/wiki/IP35 > > states "IP35 is not yet supported by Linux. A port initially targeting > only the Origin 300 has been started". > > The last edit of the wiki was in 2007, does anyone know if it is now > supported by Linux/Debian? No; the page accurately reflects the status of kernel development where I stopped. > Would access to hardware help? Only to a limited degree - the project has currently not yet reached the stage where access to more hardware would really be useful. But before somebody dumps the hardware I can be convinced to give it a good home :-) At some point having access to more configurations will be essential - dealing with different configurations on Origin class hardware is very complex. My current hardware is a single module, Origin 300 with 4 R10000 CPUs. Ralf From laurent@guerby.net Tue Jan 27 19:44:37 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 27 Jan 2009 19:44:39 +0000 (GMT) Received: from 30.mail-out.ovh.net ([213.186.62.213]:2978 "HELO 30.mail-out.ovh.net") by ftp.linux-mips.org with SMTP id S21103374AbZA0Toh (ORCPT ); Tue, 27 Jan 2009 19:44:37 +0000 Received: (qmail 18603 invoked by uid 503); 27 Jan 2009 19:44:57 -0000 Received: from b9.ovh.net (HELO mail23.ha.ovh.net) (213.186.33.59) by 30.mail-out.ovh.net with SMTP; 27 Jan 2009 19:44:57 -0000 Received: from b0.ovh.net (HELO queue-out) (213.186.33.50) by b0.ovh.net with SMTP; 27 Jan 2009 19:44:36 -0000 Received: from 11.156.90-79.rev.gaoland.net (HELO ?192.168.1.101?) (laurent%guerby.net@79.90.156.11) by ns0.ovh.net with SMTP; 27 Jan 2009 19:44:35 -0000 Subject: Re: IP35 Origin 300/3000 support? From: Laurent GUERBY To: Ralf Baechle Cc: Linux MIPS List , Debian MIPS In-Reply-To: <20090127185759.GA2234@linux-mips.org> References: <1233078550.17541.573.camel@localhost> <20090127185759.GA2234@linux-mips.org> Content-Type: text/plain Date: Tue, 27 Jan 2009 20:44:30 +0100 Message-Id: <1233085470.17541.610.camel@localhost> Mime-Version: 1.0 X-Mailer: Evolution 2.24.2 Content-Transfer-Encoding: 7bit X-Ovh-Tracer-Id: 7215329553932623538 X-Ovh-Remote: 79.90.156.11 (11.156.90-79.rev.gaoland.net) X-Ovh-Local: 213.186.33.20 (ns0.ovh.net) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21844 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: laurent@guerby.net Precedence: bulk X-list: linux-mips Content-Length: 1471 Lines: 41 On Tue, 2009-01-27 at 18:57 +0000, Ralf Baechle wrote: > On Tue, Jan 27, 2009 at 06:49:10PM +0100, Laurent GUERBY wrote: > > > The wiki page: > > > > http://www.linux-mips.org/wiki/IP35 > > > > states "IP35 is not yet supported by Linux. A port initially targeting > > only the Origin 300 has been started". > > > > The last edit of the wiki was in 2007, does anyone know if it is now > > supported by Linux/Debian? > > No; the page accurately reflects the status of kernel development where I > stopped. > > > Would access to hardware help? > > Only to a limited degree - the project has currently not yet reached the > stage where access to more hardware would really be useful. But before > somebody dumps the hardware I can be convinced to give it a good home :-) > At some point having access to more configurations will be essential - > dealing with different configurations on Origin class hardware is very > complex. My current hardware is a single module, Origin 300 with > 4 R10000 CPUs. For the compile farm project I manage I was proposed a donation of the exact same hardware (Origin 300 with 4 cpus and 2GB RAM). I'll let you know when I have more information. BTW, in the SGI/MIPS family, do you know what is the most powerful hardware currently supported (hardware not weighting near a ton, more like a workstation or a few U)? Bootstraping GCC takes a while these days :). Thanks for your help, Laurent http://gcc.gnu.org/wiki/CompileFarm From akpm@linux-foundation.org Tue Jan 27 21:15:13 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 27 Jan 2009 21:15:15 +0000 (GMT) Received: from smtp1.linux-foundation.org ([140.211.169.13]:16865 "EHLO smtp1.linux-foundation.org") by ftp.linux-mips.org with ESMTP id S21102852AbZA0VPN (ORCPT ); Tue, 27 Jan 2009 21:15:13 +0000 Received: from imap1.linux-foundation.org (imap1.linux-foundation.org [140.211.169.55]) by smtp1.linux-foundation.org (8.14.2/8.13.5/Debian-3ubuntu1.1) with ESMTP id n0RLEum5021046 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Tue, 27 Jan 2009 13:14:57 -0800 Received: from akpm.corp.google.com (localhost [127.0.0.1]) by imap1.linux-foundation.org (8.13.5.20060308/8.13.5/Debian-3ubuntu1.1) with SMTP id n0RLEsrF029545; Tue, 27 Jan 2009 13:14:55 -0800 Date: Tue, 27 Jan 2009 13:14:54 -0800 From: Andrew Morton To: Atsushi Nemoto Cc: linux-mips@linux-mips.org, ralf@linux-mips.org, linux-mtd@lists.infradead.org, dwmw2@infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 2/5] RBTX4939: Add MTD support Message-Id: <20090127131454.d2f147df.akpm@linux-foundation.org> In-Reply-To: <1232460738-4714-2-git-send-email-anemo@mba.ocn.ne.jp> References: <1232460738-4714-2-git-send-email-anemo@mba.ocn.ne.jp> X-Mailer: Sylpheed version 2.2.4 (GTK+ 2.8.20; i486-pc-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-MIMEDefang-Filter: lf$Revision: 1.188 $ X-Scanned-By: MIMEDefang 2.63 on 140.211.169.13 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21845 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: akpm@linux-foundation.org Precedence: bulk X-list: linux-mips Content-Length: 2168 Lines: 73 On Tue, 20 Jan 2009 23:12:16 +0900 Atsushi Nemoto wrote: > +static void rbtx4939_flash_copy_from(struct map_info *map, void *to, > + unsigned long from, ssize_t len) > +{ > + u8 bdipsw = readb(rbtx4939_bdipsw_addr) & 0x0f; > + unsigned char shift; > + ssize_t curlen; > + > + from += (unsigned long)map->virt; > + if (bdipsw & 8) { > + /* BOOT Mode: USER ROM1 / USER ROM2 */ > + shift = bdipsw & 3; > + while (len) { > + curlen = min((unsigned long)len, > + 0x400000 - (from & (0x400000 - 1))); > + memcpy(to, > + (void *)((from & ~0xc00000) | > + ((((from >> 22) + shift) & 3) << 22)), > + curlen); > + len -= curlen; > + from += curlen; > + to += curlen; > + } > + return; > + } > +#ifdef __BIG_ENDIAN > + if (bdipsw == 0) { > + /* BOOT Mode: Monitor ROM */ > + while (len) { > + curlen = min((unsigned long)len, > + 0x400000 - (from & (0x400000 - 1))); > + memcpy(to, (void *)(from ^ 0x400000), curlen); > + len -= curlen; > + from += curlen; > + to += curlen; > + } > + return; > + } > +#endif > + memcpy(to, (void *)from, len); > +} min_t is the preferred way of preventing that warning. Well. Actually the preferred way is to get the types right - often the code simply goofed, and people use casts/min_t to hide that. But in this case, yes, casting literal constants to ssize_t would be a bit silly. --- a/arch/mips/txx9/rbtx4939/setup.c~mtd-rbtx4939-add-mtd-support-fix +++ a/arch/mips/txx9/rbtx4939/setup.c @@ -335,7 +335,7 @@ static void rbtx4939_flash_copy_from(str /* BOOT Mode: USER ROM1 / USER ROM2 */ shift = bdipsw & 3; while (len) { - curlen = min((unsigned long)len, + curlen = min_t(unsigned long, len, 0x400000 - (from & (0x400000 - 1))); memcpy(to, (void *)((from & ~0xc00000) | @@ -351,7 +351,7 @@ static void rbtx4939_flash_copy_from(str if (bdipsw == 0) { /* BOOT Mode: Monitor ROM */ while (len) { - curlen = min((unsigned long)len, + curlen = min_t(unsigned long, len, 0x400000 - (from & (0x400000 - 1))); memcpy(to, (void *)(from ^ 0x400000), curlen); len -= curlen; _ From ralf@h5.dl5rb.org.uk Tue Jan 27 22:10:13 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 27 Jan 2009 22:10:15 +0000 (GMT) Received: from h5.dl5rb.org.uk ([81.2.74.5]:21398 "EHLO h5.dl5rb.org.uk") by ftp.linux-mips.org with ESMTP id S21103376AbZA0WKN (ORCPT ); Tue, 27 Jan 2009 22:10:13 +0000 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id n0RMA95P010941; Tue, 27 Jan 2009 22:10:09 GMT Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id n0RMA338010936; Tue, 27 Jan 2009 22:10:03 GMT Date: Tue, 27 Jan 2009 22:10:03 +0000 From: Ralf Baechle To: Laurent GUERBY Cc: Linux MIPS List , Debian MIPS Subject: Re: IP35 Origin 300/3000 support? Message-ID: <20090127221003.GB2234@linux-mips.org> References: <1233078550.17541.573.camel@localhost> <20090127185759.GA2234@linux-mips.org> <1233085470.17541.610.camel@localhost> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1233085470.17541.610.camel@localhost> User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21846 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Content-Length: 1553 Lines: 31 On Tue, Jan 27, 2009 at 08:44:30PM +0100, Laurent GUERBY wrote: > For the compile farm project I manage I was proposed a donation of the > exact same hardware (Origin 300 with 4 cpus and 2GB RAM). I'll let > you know when I have more information. > > BTW, in the SGI/MIPS family, do you know what is the most powerful > hardware currently supported (hardware not weighting near a ton, more > like a workstation or a few U)? Bootstraping GCC takes a while these > days :). Some R10000-family based workstation that would be then. That leaves the choice between the Indigo 2 R10000 (supported in tree), O2 (R10000 version not supported in-tree and external patches not stable afaik) and the Octane which is only supported by external patches. If you're just after raw computing power for bootstrapping GCC then maybe what you want is something like a Broadcom Swarm or Big Sur evaluation board which have 2 rsp. 4 pretty beefy cores with FPU. Maybe there is also something Cavium-based that works reasonably well - my Cavium system unfortunately has no PATA or SATA controller and no PCI slots thus no local storage. My personal wish to eval board developers - design those things to be usable like workstations or headless servers, with the option of local storage and a system controller along the lines of an Origins that allows remote reset etc. Costs one microcontroller extra, adds alots of usability. Malta got that one right (send a break on the serial console for reset) and Cavium has an extra serial port for that sort of use. Ralf From msundius@cisco.com Tue Jan 27 23:00:48 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 27 Jan 2009 23:00:50 +0000 (GMT) Received: from sj-iport-2.cisco.com ([171.71.176.71]:38837 "EHLO sj-iport-2.cisco.com") by ftp.linux-mips.org with ESMTP id S21103024AbZA0XAs (ORCPT ); Tue, 27 Jan 2009 23:00:48 +0000 X-IronPort-AV: E=Sophos;i="4.37,335,1231113600"; d="scan'208";a="126261784" Received: from sj-dkim-1.cisco.com ([171.71.179.21]) by sj-iport-2.cisco.com with ESMTP; 27 Jan 2009 23:00:41 +0000 Received: from sj-core-1.cisco.com (sj-core-1.cisco.com [171.71.177.237]) by sj-dkim-1.cisco.com (8.12.11/8.12.11) with ESMTP id n0RN0fVv004098 for ; Tue, 27 Jan 2009 15:00:41 -0800 Received: from sausatlsmtp2.sciatl.com (sausatlsmtp2.cisco.com [192.133.217.159]) by sj-core-1.cisco.com (8.13.8/8.13.8) with ESMTP id n0RN0eUj005090 for ; Tue, 27 Jan 2009 23:00:41 GMT Received: from default.com ([192.133.217.159]) by sausatlsmtp2.sciatl.com with Microsoft SMTPSVC(6.0.3790.3959); Tue, 27 Jan 2009 18:00:39 -0500 Received: from sausatlbhs02.corp.sa.net ([192.133.216.42]) by sausatlsmtp2.sciatl.com with Microsoft SMTPSVC(6.0.3790.3959); Tue, 27 Jan 2009 18:00:38 -0500 Received: from CUPLXSUNDISM01.corp.sa.net ([64.101.21.60]) by sausatlbhs02.corp.sa.net with Microsoft SMTPSVC(6.0.3790.3959); Tue, 27 Jan 2009 18:00:38 -0500 Message-ID: <497F9214.1000609@cisco.com> Date: Tue, 27 Jan 2009 15:00:36 -0800 From: Michael Sundius User-Agent: Thunderbird 2.0.0.14 (X11/20080501) MIME-Version: 1.0 To: linux-mips@linux-mips.org, "VomLehn, David" , msundius@sundius.com Subject: memcpy and prefetch Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 27 Jan 2009 23:00:38.0394 (UTC) FILETIME=[11EC8DA0:01C980D3] X-ST-MF-Message-Resent: 1/27/2009 18:00 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; l=1270; t=1233097241; x=1233961241; c=relaxed/simple; s=sjdkim1004; h=Content-Type:From:Subject:Content-Transfer-Encoding:MIME-Version; d=cisco.com; i=msundius@cisco.com; z=From:=20Michael=20Sundius=20 |Subject:=20memcpy=20and=20prefetch |Sender:=20; bh=aL3Py1fSERdlXqIqC0rdvxeaxMBBarUg/YtcjYwGw1M=; b=DyhFDYJSp+lE7g/kRojI4ZJLN0nf/LiyRz49N+F2RC9/8h9/Qj8Uu5/AEA 6AiU3oCCVZDoJLciQIe71Pfy1wCHcEkjyA8NXYkYw3evKZuLvvQkz6pR0w8p BtqeegbsIIBszhbiQCcKlq8l0/qIL/D30VSdf4PdP3N3uShbfOeek=; Authentication-Results: sj-dkim-1; header.From=msundius@cisco.com; dkim=pass ( sig from cisco.com/sjdkim1004 verified; ); Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21847 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: msundius@cisco.com Precedence: bulk X-list: linux-mips Content-Length: 1240 Lines: 32 I know this topic has been written about but so excuse me if I am redundant. I saw lots of talk in the archives but I don't know if a solution was ever arrived at. so: what is the current state of the use of prefetch in memcpy()? it seems that it is #undef-ed if CONFIG_DMA_COHERENT is not turned on. is this still because the memcpy does not check to prevent a prefetch of addresses beyond the end of the buffer? If so, what was the reason a solution was abandoned.... also has anyone out there written a memcopy that does use prefetch intelligently (for mips32 that is)? thanks Mike - - - - - Cisco - - - - - This e-mail and any attachments may contain information which is confidential, proprietary, privileged or otherwise protected by law. The information is solely intended for the named addressee (or a person responsible for delivering it to the addressee). If you are not the intended recipient of this message, you are not authorized to read, print, retain, copy or disseminate this message or any part of it. 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From David.Daney@caviumnetworks.com Tue Jan 27 23:09:20 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 27 Jan 2009 23:09:22 +0000 (GMT) Received: from mail3.caviumnetworks.com ([12.108.191.235]:61983 "EHLO mail3.caviumnetworks.com") by ftp.linux-mips.org with ESMTP id S21103024AbZA0XJU (ORCPT ); Tue, 27 Jan 2009 23:09:20 +0000 Received: from exch4.caveonetworks.com (Not Verified[192.168.16.23]) by mail3.caviumnetworks.com with MailMarshal (v6,2,2,3503) id ; Tue, 27 Jan 2009 18:08:38 -0500 Received: from exch4.caveonetworks.com ([192.168.16.23]) by exch4.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Tue, 27 Jan 2009 15:07:45 -0800 Received: from dd1.caveonetworks.com ([64.169.86.201]) by exch4.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Tue, 27 Jan 2009 15:07:45 -0800 Message-ID: <497F93C1.3090401@caviumnetworks.com> Date: Tue, 27 Jan 2009 15:07:45 -0800 From: David Daney User-Agent: Thunderbird 2.0.0.19 (X11/20090105) MIME-Version: 1.0 To: Michael Sundius CC: linux-mips@linux-mips.org, "VomLehn, David" , msundius@sundius.com Subject: Re: memcpy and prefetch References: <497F9214.1000609@cisco.com> In-Reply-To: <497F9214.1000609@cisco.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 27 Jan 2009 23:07:45.0622 (UTC) FILETIME=[10925F60:01C980D4] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21848 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Content-Length: 885 Lines: 26 Michael Sundius wrote: > I know this topic has been written about but so excuse me if I am > redundant. > I saw lots of talk in the archives but I don't know if a solution was > ever arrived > at. so: > > what is the current state of the use of prefetch in memcpy()? it seems that > it is #undef-ed if CONFIG_DMA_COHERENT is not turned on. > > is this still because the memcpy does not check to prevent a prefetch of > addresses beyond the end of the buffer? > > If so, what was the reason a solution was abandoned.... > > also has anyone out there written a memcopy that does use prefetch > intelligently (for mips32 that is)? > The Cavium OCTEON port overrides the default memcpy and does use prefetch. It was recently merged (2.6.29-rc2). Look at octeon-memcpy.S I have thought that memcpy could be generated by mm/page.c as copy_page and clear_page are. David Daney From frank.neuber@kernelport.de Wed Jan 28 09:19:43 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 28 Jan 2009 09:19:45 +0000 (GMT) Received: from mail.bugwerft.de ([212.112.241.193]:56455 "EHLO mail.bugwerft.de") by ftp.linux-mips.org with ESMTP id S21366292AbZA1JTn (ORCPT ); Wed, 28 Jan 2009 09:19:43 +0000 Received: from localhost (localhost.localdomain [127.0.0.1]) by mail.bugwerft.de (Postfix) with ESMTP id B530749400C; Wed, 28 Jan 2009 10:19:37 +0100 (CET) Received: from mail.bugwerft.de ([127.0.0.1]) by localhost (mail.bugwerft.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id uuU6oxZLnpAG; Wed, 28 Jan 2009 10:19:37 +0100 (CET) Received: from [10.1.1.26] (ip-77-25-15-184.web.vodafone.de [77.25.15.184]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.bugwerft.de (Postfix) with ESMTP id 7B26249400B; Wed, 28 Jan 2009 10:19:36 +0100 (CET) Subject: Re: AU1550 Kernel bug detected[#1] clockevents_register_device From: Frank Neuber To: Manuel Lauss Cc: Florian Fainelli , Linux-MIPS In-Reply-To: <1233060160.28527.497.camel@t60p> References: <1233045842.28527.459.camel@t60p> <20090127091107.GA15890@roarinelk.homelinux.net> <1233051181.28527.485.camel@t60p> <20090127121123.GA17132@roarinelk.homelinux.net> <1233060160.28527.497.camel@t60p> Content-Type: text/plain Date: Wed, 28 Jan 2009 10:19:34 +0100 Message-Id: <1233134374.28527.524.camel@t60p> Mime-Version: 1.0 X-Mailer: Evolution 2.12.1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21849 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: frank.neuber@kernelport.de Precedence: bulk X-list: linux-mips Content-Length: 2120 Lines: 65 Am Dienstag, den 27.01.2009, 13:42 +0100 schrieb Frank Neuber: > Am Dienstag, den 27.01.2009, 13:11 +0100 schrieb Manuel Lauss: > > > I think somting is wrong with PCI resource management here. > > > I can't believe that nobody is using the PCI or Cardbus on the AU1550 > > > with the current kernel. > > > > I'm no PCI expert, but I'm pretty sure resource assignment is done by > > generic, not mips-specific, code. Please try the linux-pci and/or > > linux-kernel lists. > At the moment I buld a matrix of working kernel versions regarding the > PCI stuff on the AU1550 > > For now I can say that the versions > 2.6.18, 2.6.18-rc1 > is crashing after showing the linux banner > I found the problem for this error. It is because we compare 32 and 64 bit numbers in __request_resource. > 2.6.18-rc2, 2.6.18-rc4, 2.6.19, 2.6.20, 2.6.23 produce this: > Skipping PCI bus scan due to resource conflict I changed this: diff --git a/include/asm-mips/mach-au1x00/au1000.h b/include/asm-mips/mach-au1x00/au1000.h index 3bdce91..8616c09 100644 --- a/include/asm-mips/mach-au1x00/au1000.h +++ b/include/asm-mips/mach-au1x00/au1000.h @@ -1679,12 +1679,21 @@ enum soc_au1200_ints { #define Au1500_PCI_MEM_START 0x440000000ULL #define Au1500_PCI_MEM_END 0x44FFFFFFFULL +#if 1 +#define PCI_IO_START 0x00001000 +#define PCI_IO_END 0x000FFFFF +#define PCI_MEM_START 0x40000000 +#define PCI_MEM_END 0x4FFFFFFF +#define PCI_FIRST_DEVFN (0 << 3) +#define PCI_LAST_DEVFN (19 << 3) +#else #define PCI_IO_START (Au1500_PCI_IO_START + 0x1000) #define PCI_IO_END (Au1500_PCI_IO_END) #define PCI_MEM_START (Au1500_PCI_MEM_START) #define PCI_MEM_END (Au1500_PCI_MEM_END) #define PCI_FIRST_DEVFN (0<<3) #define PCI_LAST_DEVFN (19<<3) +#endif #define IOPORT_RESOURCE_START 0x00001000 /* skip legacy probing */ #define IOPORT_RESOURCE_END 0xffffffff Now I think a have to look at 64 problems in the resource management of th PCI subsystem > > The version 2.6.24 has the same behavior as the current git head. > > I will inform you about more results > > Regards, > Frank > From mano@roarinelk.homelinux.net Wed Jan 28 09:38:51 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 28 Jan 2009 09:38:53 +0000 (GMT) Received: from fnoeppeil36.netpark.at ([217.175.205.164]:9423 "EHLO roarinelk.homelinux.net") by ftp.linux-mips.org with ESMTP id S21366421AbZA1Jis (ORCPT ); Wed, 28 Jan 2009 09:38:48 +0000 Received: (qmail 25450 invoked by uid 1000); 28 Jan 2009 10:38:46 +0100 Date: Wed, 28 Jan 2009 10:38:46 +0100 From: Manuel Lauss To: Frank Neuber Cc: Florian Fainelli , Linux-MIPS Subject: Re: AU1550 Kernel bug detected[#1] clockevents_register_device Message-ID: <20090128093846.GA25402@roarinelk.homelinux.net> References: <1233045842.28527.459.camel@t60p> <20090127091107.GA15890@roarinelk.homelinux.net> <1233051181.28527.485.camel@t60p> <20090127121123.GA17132@roarinelk.homelinux.net> <1233060160.28527.497.camel@t60p> <1233134374.28527.524.camel@t60p> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1233134374.28527.524.camel@t60p> User-Agent: Mutt/1.5.16 (2007-06-09) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21850 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mano@roarinelk.homelinux.net Precedence: bulk X-list: linux-mips Content-Length: 2385 Lines: 64 On Wed, Jan 28, 2009 at 10:19:34AM +0100, Frank Neuber wrote: > > Am Dienstag, den 27.01.2009, 13:42 +0100 schrieb Frank Neuber: > > Am Dienstag, den 27.01.2009, 13:11 +0100 schrieb Manuel Lauss: > > > > I think somting is wrong with PCI resource management here. > > > > I can't believe that nobody is using the PCI or Cardbus on the AU1550 > > > > with the current kernel. > > > > > > I'm no PCI expert, but I'm pretty sure resource assignment is done by > > > generic, not mips-specific, code. Please try the linux-pci and/or > > > linux-kernel lists. > > At the moment I buld a matrix of working kernel versions regarding the > > PCI stuff on the AU1550 > > > > For now I can say that the versions > > 2.6.18, 2.6.18-rc1 > > is crashing after showing the linux banner > > > > I found the problem for this error. It is because we compare 32 and 64 > bit numbers in __request_resource. > > 2.6.18-rc2, 2.6.18-rc4, 2.6.19, 2.6.20, 2.6.23 produce this: > > Skipping PCI bus scan due to resource conflict > I changed this: > > diff --git a/include/asm-mips/mach-au1x00/au1000.h > b/include/asm-mips/mach-au1x00/au1000.h > index 3bdce91..8616c09 100644 > --- a/include/asm-mips/mach-au1x00/au1000.h > +++ b/include/asm-mips/mach-au1x00/au1000.h > @@ -1679,12 +1679,21 @@ enum soc_au1200_ints { > #define Au1500_PCI_MEM_START 0x440000000ULL > #define Au1500_PCI_MEM_END 0x44FFFFFFFULL > > +#if 1 > +#define PCI_IO_START 0x00001000 > +#define PCI_IO_END 0x000FFFFF > +#define PCI_MEM_START 0x40000000 > +#define PCI_MEM_END 0x4FFFFFFF > +#define PCI_FIRST_DEVFN (0 << 3) > +#define PCI_LAST_DEVFN (19 << 3) > +#else > #define PCI_IO_START (Au1500_PCI_IO_START + 0x1000) > #define PCI_IO_END (Au1500_PCI_IO_END) > #define PCI_MEM_START (Au1500_PCI_MEM_START) > #define PCI_MEM_END (Au1500_PCI_MEM_END) > #define PCI_FIRST_DEVFN (0<<3) > #define PCI_LAST_DEVFN (19<<3) > +#endif > > #define IOPORT_RESOURCE_START 0x00001000 /* skip legacy probing */ > #define IOPORT_RESOURCE_END 0xffffffff > > > Now I think a have to look at 64 problems in the resource management of > th PCI subsystem Do hou have CONFIG_64BIT_PHYS_ADDR=y set in your .config? If I remember correctly, __fixup_bigphys_addr() in alchemy/common/setup.c should take care of this 36bit problem (in the same way you did, btw). Best regards, Manuel Lauss From mano@roarinelk.homelinux.net Wed Jan 28 09:45:53 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 28 Jan 2009 09:45:55 +0000 (GMT) Received: from fnoeppeil36.netpark.at ([217.175.205.164]:58504 "EHLO roarinelk.homelinux.net") by ftp.linux-mips.org with ESMTP id S21366296AbZA1Jpx (ORCPT ); Wed, 28 Jan 2009 09:45:53 +0000 Received: (qmail 25517 invoked by uid 1000); 28 Jan 2009 10:45:52 +0100 Date: Wed, 28 Jan 2009 10:45:52 +0100 From: Manuel Lauss To: Frank Neuber Cc: Florian Fainelli , Linux-MIPS Subject: Re: AU1550 Kernel bug detected[#1] clockevents_register_device Message-ID: <20090128094552.GA25480@roarinelk.homelinux.net> References: <1233045842.28527.459.camel@t60p> <20090127091107.GA15890@roarinelk.homelinux.net> <1233051181.28527.485.camel@t60p> <20090127121123.GA17132@roarinelk.homelinux.net> <1233060160.28527.497.camel@t60p> <1233134374.28527.524.camel@t60p> <20090128093846.GA25402@roarinelk.homelinux.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20090128093846.GA25402@roarinelk.homelinux.net> User-Agent: Mutt/1.5.16 (2007-06-09) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21851 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mano@roarinelk.homelinux.net Precedence: bulk X-list: linux-mips Content-Length: 648 Lines: 22 > > --- a/include/asm-mips/mach-au1x00/au1000.h > > +++ b/include/asm-mips/mach-au1x00/au1000.h > > @@ -1679,12 +1679,21 @@ enum soc_au1200_ints { > > #define Au1500_PCI_MEM_START 0x440000000ULL > > #define Au1500_PCI_MEM_END 0x44FFFFFFFULL > > > > +#if 1 > > +#define PCI_IO_START 0x00001000 > > +#define PCI_IO_END 0x000FFFFF > > +#define PCI_MEM_START 0x40000000 > > +#define PCI_MEM_END 0x4FFFFFFF > > +#define PCI_FIRST_DEVFN (0 << 3) > > +#define PCI_LAST_DEVFN (19 << 3) The current -git sources already have this change. How come yours don't? (it was changed before 2.6.24). Best regards, Manuel Lauss From frank.neuber@kernelport.de Wed Jan 28 10:32:01 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 28 Jan 2009 10:32:04 +0000 (GMT) Received: from mail.bugwerft.de ([212.112.241.193]:29865 "EHLO mail.bugwerft.de") by ftp.linux-mips.org with ESMTP id S21103468AbZA1KcB (ORCPT ); Wed, 28 Jan 2009 10:32:01 +0000 Received: from localhost (localhost.localdomain [127.0.0.1]) by mail.bugwerft.de (Postfix) with ESMTP id 5DAC649400C; Wed, 28 Jan 2009 11:31:55 +0100 (CET) Received: from mail.bugwerft.de ([127.0.0.1]) by localhost (mail.bugwerft.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id VJXl21x4zGGv; Wed, 28 Jan 2009 11:31:55 +0100 (CET) Received: from [10.1.1.26] (ip-77-25-15-184.web.vodafone.de [77.25.15.184]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.bugwerft.de (Postfix) with ESMTP id 778E049400B; Wed, 28 Jan 2009 11:31:53 +0100 (CET) Subject: Re: AU1550 Kernel bug detected[#1] clockevents_register_device From: Frank Neuber To: Manuel Lauss Cc: Florian Fainelli , Linux-MIPS In-Reply-To: <20090128093846.GA25402@roarinelk.homelinux.net> References: <1233045842.28527.459.camel@t60p> <20090127091107.GA15890@roarinelk.homelinux.net> <1233051181.28527.485.camel@t60p> <20090127121123.GA17132@roarinelk.homelinux.net> <1233060160.28527.497.camel@t60p> <1233134374.28527.524.camel@t60p> <20090128093846.GA25402@roarinelk.homelinux.net> Content-Type: text/plain Date: Wed, 28 Jan 2009 11:31:50 +0100 Message-Id: <1233138710.28527.539.camel@t60p> Mime-Version: 1.0 X-Mailer: Evolution 2.12.1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21852 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: frank.neuber@kernelport.de Precedence: bulk X-list: linux-mips Content-Length: 758 Lines: 23 Am Mittwoch, den 28.01.2009, 10:38 +0100 schrieb Manuel Lauss: > > Now I think a have to look at 64 problems in the resource management of > > th PCI subsystem > > Do hou have CONFIG_64BIT_PHYS_ADDR=y set in your .config? If I remember > correctly, __fixup_bigphys_addr() in alchemy/common/setup.c should take care > of this 36bit problem (in the same way you did, btw). It think it was set to no (it was EXPERIMENTAL). Now ,after I realized what the problem is, I tested this with CONFIG_64BIT_PHYS_ADDR=y and the kernel 2.6.19 comes up without this patch. But the 2.6.23 not. Neither with the patch nor with CONFIG_64BIT_PHYS_ADDR I can enjoy again "Skipping PCI bus scan due to resource conflict" Ahrrr ... I'll have a look at this. Regards, Frank From ralf@h5.dl5rb.org.uk Wed Jan 28 10:38:14 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 28 Jan 2009 10:38:16 +0000 (GMT) Received: from h5.dl5rb.org.uk ([81.2.74.5]:40418 "EHLO h5.dl5rb.org.uk") by ftp.linux-mips.org with ESMTP id S21366309AbZA1KiO (ORCPT ); Wed, 28 Jan 2009 10:38:14 +0000 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id n0SAbuGC025217; Wed, 28 Jan 2009 10:37:56 GMT Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id n0SAbrc2025215; Wed, 28 Jan 2009 10:37:53 GMT Date: Wed, 28 Jan 2009 10:37:53 +0000 From: Ralf Baechle To: David Daney Cc: Michael Sundius , linux-mips@linux-mips.org, "VomLehn, David" , msundius@sundius.com Subject: Re: memcpy and prefetch Message-ID: <20090128103753.GC2234@linux-mips.org> References: <497F9214.1000609@cisco.com> <497F93C1.3090401@caviumnetworks.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <497F93C1.3090401@caviumnetworks.com> User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21853 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Content-Length: 442 Lines: 12 On Tue, Jan 27, 2009 at 03:07:45PM -0800, David Daney wrote: > The Cavium OCTEON port overrides the default memcpy and does use > prefetch. It was recently merged (2.6.29-rc2). Look at octeon-memcpy.S > > I have thought that memcpy could be generated by mm/page.c as copy_page > and clear_page are. No, these two only generate copy_page and clear_page. I and Thiemo were considering to extend this to a full memcopy however. Ralf From frank.neuber@kernelport.de Wed Jan 28 10:38:46 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 28 Jan 2009 10:38:49 +0000 (GMT) Received: from mail.bugwerft.de ([212.112.241.193]:10154 "EHLO mail.bugwerft.de") by ftp.linux-mips.org with ESMTP id S21366309AbZA1Kif (ORCPT ); Wed, 28 Jan 2009 10:38:35 +0000 Received: from localhost (localhost.localdomain [127.0.0.1]) by mail.bugwerft.de (Postfix) with ESMTP id 8CFB749400C; Wed, 28 Jan 2009 11:38:29 +0100 (CET) Received: from mail.bugwerft.de ([127.0.0.1]) by localhost (mail.bugwerft.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id b2QltD7MR7XO; Wed, 28 Jan 2009 11:38:29 +0100 (CET) Received: from [10.1.1.26] (ip-77-25-15-184.web.vodafone.de [77.25.15.184]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.bugwerft.de (Postfix) with ESMTP id 1A59E49400B; Wed, 28 Jan 2009 11:38:27 +0100 (CET) Subject: Re: AU1550 Kernel bug detected[#1] clockevents_register_device From: Frank Neuber To: Manuel Lauss Cc: Florian Fainelli , Linux-MIPS In-Reply-To: <20090128094552.GA25480@roarinelk.homelinux.net> References: <1233045842.28527.459.camel@t60p> <20090127091107.GA15890@roarinelk.homelinux.net> <1233051181.28527.485.camel@t60p> <20090127121123.GA17132@roarinelk.homelinux.net> <1233060160.28527.497.camel@t60p> <1233134374.28527.524.camel@t60p> <20090128093846.GA25402@roarinelk.homelinux.net> <20090128094552.GA25480@roarinelk.homelinux.net> Content-Type: text/plain Date: Wed, 28 Jan 2009 11:38:25 +0100 Message-Id: <1233139105.28527.547.camel@t60p> Mime-Version: 1.0 X-Mailer: Evolution 2.12.1 Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21854 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: frank.neuber@kernelport.de Precedence: bulk X-list: linux-mips Content-Length: 1020 Lines: 28 Am Mittwoch, den 28.01.2009, 10:45 +0100 schrieb Manuel Lauss: > > > --- a/include/asm-mips/mach-au1x00/au1000.h > > > +++ b/include/asm-mips/mach-au1x00/au1000.h > > > @@ -1679,12 +1679,21 @@ enum soc_au1200_ints { > > > #define Au1500_PCI_MEM_START 0x440000000ULL > > > #define Au1500_PCI_MEM_END 0x44FFFFFFFULL > > > > > > +#if 1 > > > +#define PCI_IO_START 0x00001000 > > > +#define PCI_IO_END 0x000FFFFF > > > +#define PCI_MEM_START 0x40000000 > > > +#define PCI_MEM_END 0x4FFFFFFF > > > +#define PCI_FIRST_DEVFN (0 << 3) > > > +#define PCI_LAST_DEVFN (19 << 3) > > The current -git sources already have this change. How come yours > don't? (it was changed before 2.6.24). Because I try to track down the PCI resource management problem in 2.6.24 I want to test older versions which does not have this problem (like 2.6.16) or now after enabeling CONFIG_64BIT_PHYS_ADDR 2.6.19. For next I will look at 2.6.23 what the problem is with the recource conflict .... Regards, Frank From chaenel@free.fr Wed Jan 28 11:49:59 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 28 Jan 2009 11:50:02 +0000 (GMT) Received: from smtp6-g21.free.fr ([212.27.42.6]:40901 "EHLO smtp6-g21.free.fr") by ftp.linux-mips.org with ESMTP id S21366439AbZA1Lt7 (ORCPT ); Wed, 28 Jan 2009 11:49:59 +0000 Received: from smtp6-g21.free.fr (localhost [127.0.0.1]) by smtp6-g21.free.fr (Postfix) with ESMTP id 46F0FE0808B for ; Wed, 28 Jan 2009 12:49:55 +0100 (CET) Received: from [192.168.1.100] (server.a3ip.com [82.229.124.93]) by smtp6-g21.free.fr (Postfix) with ESMTP id 4F242E08056 for ; Wed, 28 Jan 2009 12:49:53 +0100 (CET) Message-ID: <49804660.8040802@free.fr> Date: Wed, 28 Jan 2009 12:49:52 +0100 From: Cyril HAENEL User-Agent: Thunderbird 2.0.0.19 (X11/20090114) MIME-Version: 1.0 To: linux-mips@linux-mips.org Subject: Question about the SMP8634/SMP8635 MIPS processor Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21855 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: chaenel@free.fr Precedence: bulk X-list: linux-mips Content-Length: 1653 Lines: 46 Hi, I am new to the list, I recently bought a set-top-box (Netbox 8160) which uses a SMP8635 MIPS processor. The original fimware is a disaster and for fun I want to try to build my own linux based firmware for this set-to-box. I am absolutely not afraid, because I do a lot of embedded linux at office (on ARM9 arch and Blackfin arch). The board of this set-top-box is pretty simple, there is the SMP8635 processor, 256MB of DDRAM, 16 MB of NOR flash, mini pci with atheros wifi card, ethernet MII phy, and 2 DVB-T tuners (maybe USB2 or PCI, for now I don't now). The SMP8635 processor comes from Sigma Design and I found on its FTP site a 2.6.15 kernel with associated patches for the SMP863x processors serie. My problem is that they doesn't provide the datasheet alone, visibly they provide it with the SMP8634 developement board (http://www.sigmadesigns.com/public/Products/SMP8630/SMP8630_series.html). And to begin to developp on this board, I need at least to know where is located the JTAG. It will be the starting point to try to access the NOR flash to backup the original firmware, and play with the board. I don't see any SPI eeprom/flash thus I think even the boot loader is located the 16MB nor flash, so I thing at startup the processor directly try to execute code from the NOR, maybe at adress 0x0. Is someone has some information on this processor ? Or maybe the datasheet ? With the datasheet I will be have to locate the JTAG pin :) Thank you for reading my message, and sorry because my english is not perfect. I wish you a good day Regards, Cyril HAENEL -- Cyril Haenel Registered Linux User #332632 From ralf@h5.dl5rb.org.uk Wed Jan 28 12:40:50 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 28 Jan 2009 12:40:52 +0000 (GMT) Received: from h5.dl5rb.org.uk ([81.2.74.5]:12489 "EHLO h5.dl5rb.org.uk") by ftp.linux-mips.org with ESMTP id S21103511AbZA1Mku (ORCPT ); Wed, 28 Jan 2009 12:40:50 +0000 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id n0SCenB5028009; Wed, 28 Jan 2009 12:40:49 GMT Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id n0SCelpK028000; Wed, 28 Jan 2009 12:40:47 GMT Date: Wed, 28 Jan 2009 12:40:47 +0000 From: Ralf Baechle To: Yoichi Yuasa Cc: linux-mips Subject: Re: [PATCH][MIPS] add return value check to user_termio_to_kernel_termios() Message-ID: <20090128124047.GA25706@linux-mips.org> References: <20090125224557.8582051b.yoichi_yuasa@tripeaks.co.jp> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20090125224557.8582051b.yoichi_yuasa@tripeaks.co.jp> User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21856 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Content-Length: 1780 Lines: 36 On Sun, Jan 25, 2009 at 10:45:57PM +0900, Yoichi Yuasa wrote: > diff -pruN -X /home/yuasa/Memo/dontdiff linux-orig/arch/mips/include/asm/termios.h linux/arch/mips/include/asm/termios.h > --- linux-orig/arch/mips/include/asm/termios.h 2008-10-19 22:33:14.114377349 +0900 > +++ linux/arch/mips/include/asm/termios.h 2008-10-19 22:41:25.322369698 +0900 > @@ -97,14 +97,14 @@ struct termio { > #define user_termio_to_kernel_termios(termios, termio) \ > ({ \ > unsigned short tmp; \ > - get_user(tmp, &(termio)->c_iflag); \ > - (termios)->c_iflag = (0xffff0000 & ((termios)->c_iflag)) | tmp; \ > - get_user(tmp, &(termio)->c_oflag); \ > - (termios)->c_oflag = (0xffff0000 & ((termios)->c_oflag)) | tmp; \ > - get_user(tmp, &(termio)->c_cflag); \ > - (termios)->c_cflag = (0xffff0000 & ((termios)->c_cflag)) | tmp; \ > - get_user(tmp, &(termio)->c_lflag); \ > - (termios)->c_lflag = (0xffff0000 & ((termios)->c_lflag)) | tmp; \ > + if (!get_user(tmp, &(termio)->c_iflag)) \ > + (termios)->c_iflag = (0xffff0000 & ((termios)->c_iflag)) | tmp; \ > + if (!get_user(tmp, &(termio)->c_oflag)) \ > + (termios)->c_oflag = (0xffff0000 & ((termios)->c_oflag)) | tmp; \ > + if (!get_user(tmp, &(termio)->c_cflag)) \ > + (termios)->c_cflag = (0xffff0000 & ((termios)->c_cflag)) | tmp; \ > + if (!get_user(tmp, &(termio)->c_lflag)) \ > + (termios)->c_lflag = (0xffff0000 & ((termios)->c_lflag)) | tmp; \ > get_user((termios)->c_line, &(termio)->c_line); \ > copy_from_user((termios)->c_cc, (termio)->c_cc, NCC); \ Duh... That sort of trivial thing is not fatal but just shouldn't happen. And other architectures have the same bug even. Your patch leaves the last get_user and the copy_from_user return values unchecked. I'll sort that out. Thanks for reporting and patch! Ralf From ralf@h5.dl5rb.org.uk Wed Jan 28 13:40:09 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 28 Jan 2009 13:40:11 +0000 (GMT) Received: from h5.dl5rb.org.uk ([81.2.74.5]:19436 "EHLO h5.dl5rb.org.uk") by ftp.linux-mips.org with ESMTP id S21366314AbZA1NkJ (ORCPT ); Wed, 28 Jan 2009 13:40:09 +0000 Received: from h5.dl5rb.org.uk (localhost.localdomain [127.0.0.1]) by h5.dl5rb.org.uk (8.14.3/8.14.3) with ESMTP id n0SDe8KQ002541; Wed, 28 Jan 2009 13:40:08 GMT Received: (from ralf@localhost) by h5.dl5rb.org.uk (8.14.3/8.14.3/Submit) id n0SDe7iP002540; Wed, 28 Jan 2009 13:40:07 GMT Date: Wed, 28 Jan 2009 13:40:07 +0000 From: Ralf Baechle To: Yoichi Yuasa Cc: linux-mips Subject: Re: [PATCH][MIPS] add return value check to user_termio_to_kernel_termios() Message-ID: <20090128134007.GA29709@linux-mips.org> References: <20090125224557.8582051b.yoichi_yuasa@tripeaks.co.jp> <20090128124047.GA25706@linux-mips.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20090128124047.GA25706@linux-mips.org> User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21857 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Content-Length: 4936 Lines: 147 On Wed, Jan 28, 2009 at 12:40:47PM +0000, Ralf Baechle wrote: > Duh... That sort of trivial thing is not fatal but just shouldn't > happen. And other architectures have the same bug even. Your patch > leaves the last get_user and the copy_from_user return values unchecked. > I'll sort that out. How about this patch which also gets rid of the rest of the macro soup by replacing them with inline functions. How about this? Ralf Signed-off-by: Ralf Baechle commit 848091da998d2f0d5fe70c6bcd34a0cdf5c7f2b2 Author: Yoichi Yuasa Date: Sun Jan 25 22:45:57 2009 +0900 MIPS: Add return value checks to user_termio_to_kernel_termios() Signed-off-by: Yoichi Yuasa Signed-off-by: Ralf Baechle diff --git a/arch/mips/include/asm/termios.h b/arch/mips/include/asm/termios.h index a275661..8f77f77 100644 --- a/arch/mips/include/asm/termios.h +++ b/arch/mips/include/asm/termios.h @@ -9,6 +9,7 @@ #ifndef _ASM_TERMIOS_H #define _ASM_TERMIOS_H +#include #include #include @@ -94,38 +95,81 @@ struct termio { /* * Translate a "termio" structure into a "termios". Ugh. */ -#define user_termio_to_kernel_termios(termios, termio) \ -({ \ - unsigned short tmp; \ - get_user(tmp, &(termio)->c_iflag); \ - (termios)->c_iflag = (0xffff0000 & ((termios)->c_iflag)) | tmp; \ - get_user(tmp, &(termio)->c_oflag); \ - (termios)->c_oflag = (0xffff0000 & ((termios)->c_oflag)) | tmp; \ - get_user(tmp, &(termio)->c_cflag); \ - (termios)->c_cflag = (0xffff0000 & ((termios)->c_cflag)) | tmp; \ - get_user(tmp, &(termio)->c_lflag); \ - (termios)->c_lflag = (0xffff0000 & ((termios)->c_lflag)) | tmp; \ - get_user((termios)->c_line, &(termio)->c_line); \ - copy_from_user((termios)->c_cc, (termio)->c_cc, NCC); \ -}) +static inline int user_termio_to_kernel_termios(struct ktermios *termios, + struct termio __user *termio) +{ + unsigned short iflag, oflag, cflag, lflag; + unsigned int err; + + if (!access_ok(VERIFY_READ, termio, sizeof(struct termio))) + return -EFAULT; + + err = __get_user(iflag, &termio->c_iflag); + termios->c_iflag = (termios->c_iflag & 0xffff0000) | iflag; + err |=__get_user(oflag, &termio->c_oflag); + termios->c_oflag = (termios->c_oflag & 0xffff0000) | oflag; + err |=__get_user(cflag, &termio->c_cflag); + termios->c_cflag = (termios->c_cflag & 0xffff0000) | cflag; + err |=__get_user(lflag, &termio->c_lflag); + termios->c_lflag = (termios->c_lflag & 0xffff0000) | lflag; + err |=__get_user(termios->c_line, &termio->c_line); + if (err) + return -EFAULT; + + if (__copy_from_user(termios->c_cc, termio->c_cc, NCC)) + return -EFAULT; + + return 0; +} /* * Translate a "termios" structure into a "termio". Ugh. */ -#define kernel_termios_to_user_termio(termio, termios) \ -({ \ - put_user((termios)->c_iflag, &(termio)->c_iflag); \ - put_user((termios)->c_oflag, &(termio)->c_oflag); \ - put_user((termios)->c_cflag, &(termio)->c_cflag); \ - put_user((termios)->c_lflag, &(termio)->c_lflag); \ - put_user((termios)->c_line, &(termio)->c_line); \ - copy_to_user((termio)->c_cc, (termios)->c_cc, NCC); \ -}) - -#define user_termios_to_kernel_termios(k, u) copy_from_user(k, u, sizeof(struct termios2)) -#define kernel_termios_to_user_termios(u, k) copy_to_user(u, k, sizeof(struct termios2)) -#define user_termios_to_kernel_termios_1(k, u) copy_from_user(k, u, sizeof(struct termios)) -#define kernel_termios_to_user_termios_1(u, k) copy_to_user(u, k, sizeof(struct termios)) +static inline int kernel_termios_to_user_termio(struct termio __user *termio, + struct ktermios *termios) +{ + int err; + + if (!access_ok(VERIFY_WRITE, termio, sizeof(struct termio))) + return -EFAULT; + + err = __put_user(termios->c_iflag, &termio->c_iflag); + err |= __put_user(termios->c_oflag, &termio->c_oflag); + err |= __put_user(termios->c_cflag, &termio->c_cflag); + err |= __put_user(termios->c_lflag, &termio->c_lflag); + err |= __put_user(termios->c_line, &termio->c_line); + if (err) + return -EFAULT; + + if (__copy_to_user(termio->c_cc, termios->c_cc, NCC)) + return -EFAULT; + + return 0; +} + +static inline int user_termios_to_kernel_termios(struct ktermios __user *k, + struct termios2 *u) +{ + return copy_from_user(k, u, sizeof(struct termios2)) ? -EFAULT : 0; +} + +static inline int kernel_termios_to_user_termios(struct termios2 __user *u, + struct ktermios *k) +{ + return copy_to_user(u, k, sizeof(struct termios2)) ? -EFAULT : 0; +} + +static inline int user_termios_to_kernel_termios_1(struct ktermios *k, + struct termios __user *u) +{ + return copy_from_user(k, u, sizeof(struct termios)) ? -EFAULT : 0; +} + +static inline int kernel_termios_to_user_termios_1(struct termios __user *u, + struct ktermios *k) +{ + return copy_to_user(u, k, sizeof(struct termios)) ? -EFAULT : 0; +} #endif /* defined(__KERNEL__) */ From anemo@mba.ocn.ne.jp Wed Jan 28 15:28:57 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 28 Jan 2009 15:28:59 +0000 (GMT) Received: from mba.ocn.ne.jp ([122.1.235.107]:10708 "HELO smtp.mba.ocn.ne.jp") by ftp.linux-mips.org with SMTP id S21102816AbZA1P24 (ORCPT ); Wed, 28 Jan 2009 15:28:56 +0000 Received: from localhost (p4220-ipad312funabasi.chiba.ocn.ne.jp [123.217.222.220]) by smtp.mba.ocn.ne.jp (Postfix) with ESMTP id 95D0AABDD; Thu, 29 Jan 2009 00:28:50 +0900 (JST) Date: Thu, 29 Jan 2009 00:28:50 +0900 (JST) Message-Id: <20090129.002850.118974677.anemo@mba.ocn.ne.jp> To: ralf@linux-mips.org Cc: ddaney@caviumnetworks.com, msundius@cisco.com, linux-mips@linux-mips.org, dvomlehn@cisco.com, msundius@sundius.com Subject: Re: memcpy and prefetch From: Atsushi Nemoto In-Reply-To: <20090128103753.GC2234@linux-mips.org> References: <497F9214.1000609@cisco.com> <497F93C1.3090401@caviumnetworks.com> <20090128103753.GC2234@linux-mips.org> X-Fingerprint: 6ACA 1623 39BD 9A94 9B1A B746 CA77 FE94 2874 D52F X-Pgp-Public-Key: http://wwwkeys.pgp.net/pks/lookup?op=get&search=0x2874D52F X-Mailer: Mew version 5.2 on Emacs 21.4 / Mule 5.0 (SAKAKI) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21858 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anemo@mba.ocn.ne.jp Precedence: bulk X-list: linux-mips Content-Length: 792 Lines: 23 On Wed, 28 Jan 2009 10:37:53 +0000, Ralf Baechle wrote: > > The Cavium OCTEON port overrides the default memcpy and does use > > prefetch. It was recently merged (2.6.29-rc2). Look at octeon-memcpy.S > > > > I have thought that memcpy could be generated by mm/page.c as copy_page > > and clear_page are. > > No, these two only generate copy_page and clear_page. I and Thiemo were > considering to extend this to a full memcopy however. BTW, this code in memcpy.S (and memcpy-atomic.S) looks weird. #if !defined(CONFIG_DMA_COHERENT) || !defined(CONFIG_DMA_IP27) #undef CONFIG_CPU_HAS_PREFETCH #endif #ifdef CONFIG_MIPS_MALTA #undef CONFIG_CPU_HAS_PREFETCH #endif Are there any configuration which do not undef CONFIG_CPU_HAS_PREFETCH ? ;-) --- Atsushi Nemoto From David.Daney@caviumnetworks.com Wed Jan 28 16:36:15 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 28 Jan 2009 16:36:17 +0000 (GMT) Received: from mail3.caviumnetworks.com ([12.108.191.235]:9098 "EHLO mail3.caviumnetworks.com") by ftp.linux-mips.org with ESMTP id S21103451AbZA1QgP (ORCPT ); Wed, 28 Jan 2009 16:36:15 +0000 Received: from exch4.caveonetworks.com (Not Verified[192.168.16.23]) by mail3.caviumnetworks.com with MailMarshal (v6,2,2,3503) id ; Wed, 28 Jan 2009 11:35:46 -0500 Received: from exch4.caveonetworks.com ([192.168.16.23]) by exch4.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Wed, 28 Jan 2009 08:35:03 -0800 Received: from dd1.caveonetworks.com ([64.169.86.201]) by exch4.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Wed, 28 Jan 2009 08:35:02 -0800 Message-ID: <49808936.2040407@caviumnetworks.com> Date: Wed, 28 Jan 2009 08:35:02 -0800 From: David Daney User-Agent: Thunderbird 2.0.0.19 (X11/20090105) MIME-Version: 1.0 To: Cyril HAENEL CC: linux-mips@linux-mips.org Subject: Re: Question about the SMP8634/SMP8635 MIPS processor References: <49804660.8040802@free.fr> In-Reply-To: <49804660.8040802@free.fr> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 28 Jan 2009 16:35:02.0947 (UTC) FILETIME=[5E893F30:01C98166] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21859 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@caviumnetworks.com Precedence: bulk X-list: linux-mips Content-Length: 2064 Lines: 46 Cyril HAENEL wrote: [...] > The SMP8635 processor comes from Sigma Design and I found on its FTP > site a 2.6.15 kernel with associated patches for the SMP863x processors > serie. > > My problem is that they doesn't provide the datasheet alone, visibly > they provide it with the SMP8634 developement board > (http://www.sigmadesigns.com/public/Products/SMP8630/SMP8630_series.html). > In the past the datasheet was only available under NDA... > And to begin to developp on this board, I need at least to know where is > located the JTAG. It will be the starting point to try to access the NOR > flash to backup the original firmware, and play with the board. > I don't see any SPI eeprom/flash thus I think even the boot loader is > located the 16MB nor flash, so I thing at startup the processor directly > try to execute code from the NOR, maybe at adress 0x0. > The 8634 has an internal 'security' processor that executes code out of on-chip flash/RAM. This security processor boots the main CPU only after verifying that the boot loader's cryptographic signatures are valid. Unless the factory firmware is permissive, there is very little you can do with it. > Is someone has some information on this processor ? Or maybe the > datasheet ? With the datasheet I will be have to locate the JTAG pin :) The JTAG is multiplexed with the second serial port. Often you have to change a strapping pin so that JTAG is enabled when the board is powered on. Different boards have a variety of JTAG connectors, you would have to search for it on your board. Generally it is some form of 14 pin dual-inline header. If you haven't already found it, probably the first thing you want to do is find primary serial port. Most configurations print at least a couple of lines indicating DRAM configuration before booting. If you are lucky you may be able to get to a YAMON prompt from the serial port. The zboot loader may read a character from the serial port. '0', '1', '2', and '3' will override the default boot image. David Daney From chaenel@free.fr Wed Jan 28 17:01:53 2009 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 28 Jan 2009 17:01:55 +0000 (GMT) Received: from smtp1-g21.free.fr ([212.27.42.1]:30862 "EHLO smtp1-g21.free.fr") by ftp.linux-mips.org with ESMTP id S21366333AbZA1RBx (ORCPT ); Wed, 28 Jan 2009 17:01:53 +0000 Received: from smtp1-g21.free.fr (localhost [127.0.0.1]) by smtp1-g21.free.fr (Postfix) with ESMTP id 9AD879401FF; Wed, 28 Jan 2009 18:01:49 +0100 (CET) Received: from [192.168.1.100] (server.a3ip.com [82.229.124.93]) by smtp1-g21.free.fr (Postfix) with ESMTP id 7968C940167; Wed, 28 Jan 2009 18:01:45 +0100 (CET) Message-ID: <49808F73.1000301@free.fr> Date: Wed, 28 Jan 2009 18:01:39 +0100 From: Cyril HAENEL User-Agent: Thunderbird 2.0.0.19 (X11/20090114) MIME-Version: 1.0 To: David Daney CC: linux-mips@linux-mips.org Subject: Re: Question about the SMP8634/SMP8635 MIPS processor References: <49804660.8040802@free.fr> <49808936.2040407@caviumnetworks.com> In-Reply-To: <49808936.2040407@caviumnetworks.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 8bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 21860 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: chaenel@free.fr Precedence: bulk X-list: linux-mips Content-Length: 2866 Lines: 77 David Daney a écrit : > Cyril HAENEL wrote: > [...] >> The SMP8635 processor comes from Sigma Design and I found on its FTP >> site a 2.6.15 kernel with associated patches for the SMP863x >> processors serie. >> >> My problem is that they doesn't provide the datasheet alone, visibly >> they provide it with the SMP8634 developement board >> (http://www.sigmadesigns.com/public/Products/SMP8630/SMP8630_series.html). >> >> > > In the past the datasheet was only available under NDA... Maybe I can ask them.... Or maybe I must buy the development kit, but I thing price will be very high ! > >> And to begin to developp on this board, I need at least to know where >> is located the JTAG. It will be the starting point to try to access >> the NOR flash to backup the original firmware, and play with the board. >> I don't see any SPI eeprom/flash thus I think even the boot loader is >> located the 16MB nor flash, so I thing at startup the processor >> directly try to execute code from the NOR, maybe at adress 0x0. >> > > The 8634 has an internal 'security' processor that executes code out > of on-chip flash/RAM. This security processor boots the main CPU only > after verifying that the boot loader's cryptographic signatures are > valid. Unless the factory firmware is permissive, there is very > little you can do with it. Ok, thus the 8635 has an internal flash and some security routine at startup. Not a goo