From amit10ks@gmail.com Mon Sep  1 13:33:05 2008
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Date:	Mon, 1 Sep 2008 18:03:04 +0530
From:	"amit singh" <amit10ks@gmail.com>
To:	linux-mips@linux-mips.org
Subject: need to join developer group
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hi need to join developer group
.amit kr singh
noida

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<div dir="ltr">hi need to join developer group <br>.amit kr singh<br>noida<br><br></div>

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From anemo@mba.ocn.ne.jp Mon Sep  1 14:22:42 2008
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From:	Atsushi Nemoto <anemo@mba.ocn.ne.jp>
To:	linux-mips@linux-mips.org
Cc:	ralf@linux-mips.org
Subject: [PATCH 2/6] TXx9: Microoptimize interrupt handlers
Date:	Mon,  1 Sep 2008 22:22:37 +0900
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The IOC interrupt status register on RBTX49XX only have 8 bits.  Use
8-bit version of __fls() to optimize interrupt handlers.

Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
---
 arch/mips/txx9/rbtx4927/irq.c   |    6 +++---
 arch/mips/txx9/rbtx4938/irq.c   |    8 ++++----
 include/asm-mips/txx9/generic.h |   18 ++++++++++++++++++
 3 files changed, 25 insertions(+), 7 deletions(-)

diff --git a/arch/mips/txx9/rbtx4927/irq.c b/arch/mips/txx9/rbtx4927/irq.c
index 22076e3..9c14ebb 100644
--- a/arch/mips/txx9/rbtx4927/irq.c
+++ b/arch/mips/txx9/rbtx4927/irq.c
@@ -133,9 +133,9 @@ static int toshiba_rbtx4927_irq_nested(int sw_irq)
 	u8 level3;
 
 	level3 = readb(rbtx4927_imstat_addr) & 0x1f;
-	if (level3)
-		sw_irq = RBTX4927_IRQ_IOC + fls(level3) - 1;
-	return sw_irq;
+	if (unlikely(!level3))
+		return -1;
+	return RBTX4927_IRQ_IOC + __fls8(level3);
 }
 
 static void __init toshiba_rbtx4927_irq_ioc_init(void)
diff --git a/arch/mips/txx9/rbtx4938/irq.c b/arch/mips/txx9/rbtx4938/irq.c
index ca2f830..7d21bef 100644
--- a/arch/mips/txx9/rbtx4938/irq.c
+++ b/arch/mips/txx9/rbtx4938/irq.c
@@ -85,10 +85,10 @@ static int toshiba_rbtx4938_irq_nested(int sw_irq)
 	u8 level3;
 
 	level3 = readb(rbtx4938_imstat_addr);
-	if (level3)
-		/* must use fls so onboard ATA has priority */
-		sw_irq = RBTX4938_IRQ_IOC + fls(level3) - 1;
-	return sw_irq;
+	if (unlikely(!level3))
+		return -1;
+	/* must use fls so onboard ATA has priority */
+	return RBTX4938_IRQ_IOC + __fls8(level3);
 }
 
 static void __init
diff --git a/include/asm-mips/txx9/generic.h b/include/asm-mips/txx9/generic.h
index 1e1a9f2..dc85515 100644
--- a/include/asm-mips/txx9/generic.h
+++ b/include/asm-mips/txx9/generic.h
@@ -64,4 +64,22 @@ struct physmap_flash_data;
 void txx9_physmap_flash_init(int no, unsigned long addr, unsigned long size,
 			     const struct physmap_flash_data *pdata);
 
+/* 8 bit version of __fls(): find first bit set (returns 0..7) */
+static inline unsigned int __fls8(unsigned char x)
+{
+	int r = 7;
+
+	if (!(x & 0xf0)) {
+		r -= 4;
+		x <<= 4;
+	}
+	if (!(x & 0xc0)) {
+		r -= 2;
+		x <<= 2;
+	}
+	if (!(x & 0x80))
+		r -= 1;
+	return r;
+}
+
 #endif /* __ASM_TXX9_GENERIC_H */
-- 
1.5.6.3


From anemo@mba.ocn.ne.jp Mon Sep  1 14:23:21 2008
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From:	Atsushi Nemoto <anemo@mba.ocn.ne.jp>
To:	linux-mips@linux-mips.org
Cc:	ralf@linux-mips.org
Subject: [PATCH 1/6] TXx9: stop_unused_modules
Date:	Mon,  1 Sep 2008 22:22:36 +0900
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TXx9 SoCs have pin multiplex.  Stop some controller modules which can
not be used due to pin configurations.

Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
---
 arch/mips/txx9/generic/setup_tx4927.c |   31 ++++++++++++++++++
 arch/mips/txx9/generic/setup_tx4938.c |   56 +++++++++++++++++++++++++++++++++
 2 files changed, 87 insertions(+), 0 deletions(-)

diff --git a/arch/mips/txx9/generic/setup_tx4927.c b/arch/mips/txx9/generic/setup_tx4927.c
index c4248cb..914e93c 100644
--- a/arch/mips/txx9/generic/setup_tx4927.c
+++ b/arch/mips/txx9/generic/setup_tx4927.c
@@ -252,3 +252,34 @@ void __init tx4927_mtd_init(int ch)
 		return;	/* disabled */
 	txx9_physmap_flash_init(ch, start, size, &pdata);
 }
+
+static void __init tx4927_stop_unused_modules(void)
+{
+	__u64 pcfg, rst = 0, ckd = 0;
+	char buf[128];
+
+	buf[0] = '\0';
+	local_irq_disable();
+	pcfg = ____raw_readq(&tx4927_ccfgptr->pcfg);
+	if (!(pcfg & TX4927_PCFG_SEL2)) {
+		rst |= TX4927_CLKCTR_ACLRST;
+		ckd |= TX4927_CLKCTR_ACLCKD;
+		strcat(buf, " ACLC");
+	}
+	if (rst | ckd) {
+		txx9_set64(&tx4927_ccfgptr->clkctr, rst);
+		txx9_set64(&tx4927_ccfgptr->clkctr, ckd);
+	}
+	local_irq_enable();
+	if (buf[0])
+		pr_info("%s: stop%s\n", txx9_pcode_str, buf);
+}
+
+static int __init tx4927_late_init(void)
+{
+	if (txx9_pcode != 0x4927)
+		return -ENODEV;
+	tx4927_stop_unused_modules();
+	return 0;
+}
+late_initcall(tx4927_late_init);
diff --git a/arch/mips/txx9/generic/setup_tx4938.c b/arch/mips/txx9/generic/setup_tx4938.c
index 0d8517a..af724e5 100644
--- a/arch/mips/txx9/generic/setup_tx4938.c
+++ b/arch/mips/txx9/generic/setup_tx4938.c
@@ -334,3 +334,59 @@ void __init tx4938_mtd_init(int ch)
 		return;	/* disabled */
 	txx9_physmap_flash_init(ch, start, size, &pdata);
 }
+
+static void __init tx4938_stop_unused_modules(void)
+{
+	__u64 pcfg, rst = 0, ckd = 0;
+	char buf[128];
+
+	buf[0] = '\0';
+	local_irq_disable();
+	pcfg = ____raw_readq(&tx4938_ccfgptr->pcfg);
+	switch (txx9_pcode) {
+	case 0x4937:
+		if (!(pcfg & TX4938_PCFG_SEL2)) {
+			rst |= TX4938_CLKCTR_ACLRST;
+			ckd |= TX4938_CLKCTR_ACLCKD;
+			strcat(buf, " ACLC");
+		}
+		break;
+	case 0x4938:
+		if (!(pcfg & TX4938_PCFG_SEL2) ||
+		    (pcfg & TX4938_PCFG_ETH0_SEL)) {
+			rst |= TX4938_CLKCTR_ACLRST;
+			ckd |= TX4938_CLKCTR_ACLCKD;
+			strcat(buf, " ACLC");
+		}
+		if ((pcfg &
+		     (TX4938_PCFG_ATA_SEL | TX4938_PCFG_ISA_SEL |
+		      TX4938_PCFG_NDF_SEL))
+		    != TX4938_PCFG_NDF_SEL) {
+			rst |= TX4938_CLKCTR_NDFRST;
+			ckd |= TX4938_CLKCTR_NDFCKD;
+			strcat(buf, " NDFMC");
+		}
+		if (!(pcfg & TX4938_PCFG_SPI_SEL)) {
+			rst |= TX4938_CLKCTR_SPIRST;
+			ckd |= TX4938_CLKCTR_SPICKD;
+			strcat(buf, " SPI");
+		}
+		break;
+	}
+	if (rst | ckd) {
+		txx9_set64(&tx4938_ccfgptr->clkctr, rst);
+		txx9_set64(&tx4938_ccfgptr->clkctr, ckd);
+	}
+	local_irq_enable();
+	if (buf[0])
+		pr_info("%s: stop%s\n", txx9_pcode_str, buf);
+}
+
+static int __init tx4938_late_init(void)
+{
+	if (txx9_pcode != 0x4937 && txx9_pcode != 0x4938)
+		return -ENODEV;
+	tx4938_stop_unused_modules();
+	return 0;
+}
+late_initcall(tx4938_late_init);
-- 
1.5.6.3


From anemo@mba.ocn.ne.jp Mon Sep  1 14:23:42 2008
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From:	Atsushi Nemoto <anemo@mba.ocn.ne.jp>
To:	linux-mips@linux-mips.org
Cc:	ralf@linux-mips.org
Subject: [PATCH 3/6] TXx9: IOC LED support
Date:	Mon,  1 Sep 2008 22:22:38 +0900
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Add leds-gpio platform device for controlling LEDs connected to IOC on
RBTX49XX and JMR3927 board.

Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
---
 arch/mips/txx9/generic/setup.c   |  111 ++++++++++++++++++++++++++++++++++++++
 arch/mips/txx9/jmr3927/setup.c   |    5 ++
 arch/mips/txx9/rbtx4927/setup.c  |    1 +
 arch/mips/txx9/rbtx4938/setup.c  |    1 +
 include/asm-mips/txx9/generic.h  |    4 ++
 include/asm-mips/txx9/rbtx4927.h |    1 +
 6 files changed, 123 insertions(+), 0 deletions(-)

diff --git a/arch/mips/txx9/generic/setup.c b/arch/mips/txx9/generic/setup.c
index 0f91e83..b25b479 100644
--- a/arch/mips/txx9/generic/setup.c
+++ b/arch/mips/txx9/generic/setup.c
@@ -23,6 +23,7 @@
 #include <linux/platform_device.h>
 #include <linux/serial_core.h>
 #include <linux/mtd/physmap.h>
+#include <linux/leds.h>
 #include <asm/bootinfo.h>
 #include <asm/time.h>
 #include <asm/reboot.h>
@@ -648,3 +649,113 @@ void __init txx9_physmap_flash_init(int no, unsigned long addr,
 		platform_device_put(pdev);
 #endif
 }
+
+#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE)
+static DEFINE_SPINLOCK(txx9_iocled_lock);
+
+#define TXX9_IOCLED_MAXLEDS 8
+
+struct txx9_iocled_data {
+	struct gpio_chip chip;
+	u8 cur_val;
+	void __iomem *mmioaddr;
+	struct gpio_led_platform_data pdata;
+	struct gpio_led leds[TXX9_IOCLED_MAXLEDS];
+	char names[TXX9_IOCLED_MAXLEDS][32];
+};
+
+static int txx9_iocled_get(struct gpio_chip *chip, unsigned int offset)
+{
+	struct txx9_iocled_data *data =
+		container_of(chip, struct txx9_iocled_data, chip);
+	return data->cur_val & (1 << offset);
+}
+
+static void txx9_iocled_set(struct gpio_chip *chip, unsigned int offset,
+			    int value)
+{
+	struct txx9_iocled_data *data =
+		container_of(chip, struct txx9_iocled_data, chip);
+	unsigned long flags;
+	spin_lock_irqsave(&txx9_iocled_lock, flags);
+	if (value)
+		data->cur_val |= 1 << offset;
+	else
+		data->cur_val &= ~(1 << offset);
+	writeb(data->cur_val, data->mmioaddr);
+	mmiowb();
+	spin_unlock_irqrestore(&txx9_iocled_lock, flags);
+}
+
+static int txx9_iocled_dir_in(struct gpio_chip *chip, unsigned int offset)
+{
+	return 0;
+}
+
+static int txx9_iocled_dir_out(struct gpio_chip *chip, unsigned int offset,
+			       int value)
+{
+	txx9_iocled_set(chip, offset, value);
+	return 0;
+}
+
+void __init txx9_iocled_init(unsigned long baseaddr,
+			     int basenum, unsigned int num, int lowactive,
+			     const char *color, char **deftriggers)
+{
+	struct txx9_iocled_data *iocled;
+	struct platform_device *pdev;
+	int i;
+	static char *default_triggers[] __initdata = {
+		"heartbeat",
+		"ide-disk",
+		"nand-disk",
+		NULL,
+	};
+
+	if (!deftriggers)
+		deftriggers = default_triggers;
+	iocled = kzalloc(sizeof(*iocled), GFP_KERNEL);
+	if (!iocled)
+		return;
+	iocled->mmioaddr = ioremap(baseaddr, 1);
+	if (!iocled->mmioaddr)
+		return;
+	iocled->chip.get = txx9_iocled_get;
+	iocled->chip.set = txx9_iocled_set;
+	iocled->chip.direction_input = txx9_iocled_dir_in;
+	iocled->chip.direction_output = txx9_iocled_dir_out;
+	iocled->chip.label = "iocled";
+	iocled->chip.base = basenum;
+	iocled->chip.ngpio = num;
+	if (gpiochip_add(&iocled->chip))
+		return;
+	if (basenum < 0)
+		basenum = iocled->chip.base;
+
+	pdev = platform_device_alloc("leds-gpio", basenum);
+	if (!pdev)
+		return;
+	iocled->pdata.num_leds = num;
+	iocled->pdata.leds = iocled->leds;
+	for (i = 0; i < num; i++) {
+		struct gpio_led *led = &iocled->leds[i];
+		snprintf(iocled->names[i], sizeof(iocled->names[i]),
+			 "iocled:%s:%u", color, i);
+		led->name = iocled->names[i];
+		led->gpio = basenum + i;
+		led->active_low = lowactive;
+		if (deftriggers && *deftriggers)
+			led->default_trigger = *deftriggers++;
+	}
+	pdev->dev.platform_data = &iocled->pdata;
+	if (platform_device_add(pdev))
+		platform_device_put(pdev);
+}
+#else /* CONFIG_LEDS_GPIO */
+void __init txx9_iocled_init(unsigned long baseaddr,
+			     int basenum, unsigned int num, int lowactive,
+			     const char *color, char **deftriggers)
+{
+}
+#endif /* CONFIG_LEDS_GPIO */
diff --git a/arch/mips/txx9/jmr3927/setup.c b/arch/mips/txx9/jmr3927/setup.c
index 0f3843c..25e50a7 100644
--- a/arch/mips/txx9/jmr3927/setup.c
+++ b/arch/mips/txx9/jmr3927/setup.c
@@ -200,10 +200,15 @@ static void __init jmr3927_mtd_init(void)
 
 static void __init jmr3927_device_init(void)
 {
+	unsigned long iocled_base = JMR3927_IOC_LED_ADDR - IO_BASE;
+#ifdef __LITTLE_ENDIAN
+	iocled_base |= 1;
+#endif
 	__swizzle_addr_b = jmr3927_swizzle_addr_b;
 	jmr3927_rtc_init();
 	tx3927_wdt_init();
 	jmr3927_mtd_init();
+	txx9_iocled_init(iocled_base, -1, 8, 1, "green", NULL);
 }
 
 struct txx9_board_vec jmr3927_vec __initdata = {
diff --git a/arch/mips/txx9/rbtx4927/setup.c b/arch/mips/txx9/rbtx4927/setup.c
index abe32c1..4a74423 100644
--- a/arch/mips/txx9/rbtx4927/setup.c
+++ b/arch/mips/txx9/rbtx4927/setup.c
@@ -321,6 +321,7 @@ static void __init rbtx4927_device_init(void)
 	rbtx4927_ne_init();
 	tx4927_wdt_init();
 	rbtx4927_mtd_init();
+	txx9_iocled_init(RBTX4927_LED_ADDR - IO_BASE, -1, 3, 1, "green", NULL);
 }
 
 struct txx9_board_vec rbtx4927_vec __initdata = {
diff --git a/arch/mips/txx9/rbtx4938/setup.c b/arch/mips/txx9/rbtx4938/setup.c
index ec6e812..e077cc4 100644
--- a/arch/mips/txx9/rbtx4938/setup.c
+++ b/arch/mips/txx9/rbtx4938/setup.c
@@ -352,6 +352,7 @@ static void __init rbtx4938_device_init(void)
 	rbtx4938_ne_init();
 	tx4938_wdt_init();
 	rbtx4938_mtd_init();
+	txx9_iocled_init(RBTX4938_LED_ADDR - IO_BASE, -1, 8, 1, "green", NULL);
 }
 
 struct txx9_board_vec rbtx4938_vec __initdata = {
diff --git a/include/asm-mips/txx9/generic.h b/include/asm-mips/txx9/generic.h
index dc85515..4316a3e 100644
--- a/include/asm-mips/txx9/generic.h
+++ b/include/asm-mips/txx9/generic.h
@@ -82,4 +82,8 @@ static inline unsigned int __fls8(unsigned char x)
 	return r;
 }
 
+void txx9_iocled_init(unsigned long baseaddr,
+		      int basenum, unsigned int num, int lowactive,
+		      const char *color, char **deftriggers);
+
 #endif /* __ASM_TXX9_GENERIC_H */
diff --git a/include/asm-mips/txx9/rbtx4927.h b/include/asm-mips/txx9/rbtx4927.h
index c601546..b2adab3 100644
--- a/include/asm-mips/txx9/rbtx4927.h
+++ b/include/asm-mips/txx9/rbtx4927.h
@@ -34,6 +34,7 @@
 #define RBTX4927_PCIIO		0x16000000
 #define RBTX4927_PCIIO_SIZE	0x01000000
 
+#define RBTX4927_LED_ADDR	(IO_BASE + TXX9_CE(2) + 0x00001000)
 #define RBTX4927_IMASK_ADDR	(IO_BASE + TXX9_CE(2) + 0x00002000)
 #define RBTX4927_IMSTAT_ADDR	(IO_BASE + TXX9_CE(2) + 0x00002006)
 #define RBTX4927_SOFTINT_ADDR	(IO_BASE + TXX9_CE(2) + 0x00003000)
-- 
1.5.6.3


From anemo@mba.ocn.ne.jp Mon Sep  1 14:24:01 2008
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From:	Atsushi Nemoto <anemo@mba.ocn.ne.jp>
To:	linux-mips@linux-mips.org
Cc:	ralf@linux-mips.org
Subject: [PATCH 4/6] TXx9: Add TX4939 SoC support
Date:	Mon,  1 Sep 2008 22:22:39 +0900
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Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
---
 arch/mips/pci/Makefile                |    1 +
 arch/mips/pci/pci-tx4939.c            |  109 +++++++
 arch/mips/txx9/Kconfig                |    7 +
 arch/mips/txx9/generic/Makefile       |    1 +
 arch/mips/txx9/generic/irq_tx4939.c   |  215 +++++++++++++
 arch/mips/txx9/generic/setup_tx4939.c |  460 ++++++++++++++++++++++++++++
 include/asm-mips/txx9/tx4939.h        |  544 +++++++++++++++++++++++++++++++++
 7 files changed, 1337 insertions(+), 0 deletions(-)
 create mode 100644 arch/mips/pci/pci-tx4939.c
 create mode 100644 arch/mips/txx9/generic/irq_tx4939.c
 create mode 100644 arch/mips/txx9/generic/setup_tx4939.c
 create mode 100644 include/asm-mips/txx9/tx4939.h

diff --git a/arch/mips/pci/Makefile b/arch/mips/pci/Makefile
index 15e01ae..9a20985 100644
--- a/arch/mips/pci/Makefile
+++ b/arch/mips/pci/Makefile
@@ -44,6 +44,7 @@ obj-$(CONFIG_TANBAC_TB0287)	+= fixup-tb0287.o
 obj-$(CONFIG_TOSHIBA_JMR3927)	+= fixup-jmr3927.o
 obj-$(CONFIG_SOC_TX4927)	+= pci-tx4927.o
 obj-$(CONFIG_SOC_TX4938)	+= pci-tx4938.o
+obj-$(CONFIG_SOC_TX4939)	+= pci-tx4939.o
 obj-$(CONFIG_TOSHIBA_RBTX4927)	+= fixup-rbtx4927.o
 obj-$(CONFIG_TOSHIBA_RBTX4938)	+= fixup-rbtx4938.o
 obj-$(CONFIG_VICTOR_MPC30X)	+= fixup-mpc30x.o
diff --git a/arch/mips/pci/pci-tx4939.c b/arch/mips/pci/pci-tx4939.c
new file mode 100644
index 0000000..5fecf1c
--- /dev/null
+++ b/arch/mips/pci/pci-tx4939.c
@@ -0,0 +1,109 @@
+/*
+ * linux/arch/mips/pci/pci-tx4939.c
+ *
+ * Based on linux/arch/mips/txx9/rbtx4939/setup.c,
+ *	    and RBTX49xx patch from CELF patch archive.
+ *
+ * Copyright 2001, 2003-2005 MontaVista Software Inc.
+ * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
+ * (C) Copyright TOSHIBA CORPORATION 2000-2001, 2004-2007
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <linux/init.h>
+#include <linux/pci.h>
+#include <linux/kernel.h>
+#include <linux/interrupt.h>
+#include <asm/txx9/generic.h>
+#include <asm/txx9/tx4939.h>
+
+int __init tx4939_report_pciclk(void)
+{
+	int pciclk = 0;
+
+	pr_info("PCIC --%s PCICLK:",
+		(__raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_PCI66) ?
+		" PCI66" : "");
+	if (__raw_readq(&tx4939_ccfgptr->pcfg) & TX4939_PCFG_PCICLKEN_ALL) {
+		pciclk = txx9_master_clock * 20 / 6;
+		if (!(__raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_PCI66))
+			pciclk /= 2;
+		printk(KERN_CONT "Internal(%u.%uMHz)",
+		       (pciclk + 50000) / 1000000,
+		       ((pciclk + 50000) / 100000) % 10);
+	} else {
+		printk(KERN_CONT "External");
+		pciclk = -1;
+	}
+	printk(KERN_CONT "\n");
+	return pciclk;
+}
+
+void __init tx4939_report_pci1clk(void)
+{
+	unsigned int pciclk = txx9_master_clock * 20 / 6;
+
+	pr_info("PCIC1 -- PCICLK:%u.%uMHz\n",
+		(pciclk + 50000) / 1000000,
+		((pciclk + 50000) / 100000) % 10);
+}
+
+int __init tx4939_pcic1_map_irq(const struct pci_dev *dev, u8 slot)
+{
+	if (get_tx4927_pcicptr(dev->bus->sysdata) == tx4939_pcic1ptr) {
+		switch (slot) {
+		case TX4927_PCIC_IDSEL_AD_TO_SLOT(31):
+			if (__raw_readq(&tx4939_ccfgptr->pcfg) &
+			    TX4939_PCFG_ET0MODE)
+				return TXX9_IRQ_BASE + TX4939_IR_ETH(0);
+			break;
+		case TX4927_PCIC_IDSEL_AD_TO_SLOT(30):
+			if (__raw_readq(&tx4939_ccfgptr->pcfg) &
+			    TX4939_PCFG_ET1MODE)
+				return TXX9_IRQ_BASE + TX4939_IR_ETH(1);
+			break;
+		}
+		return 0;
+	}
+	return -1;
+}
+
+int __init tx4939_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
+{
+	int irq = tx4939_pcic1_map_irq(dev, slot);
+
+	if (irq >= 0)
+		return irq;
+	irq = pin;
+	/* IRQ rotation */
+	irq--;	/* 0-3 */
+	irq = (irq + 33 - slot) % 4;
+	irq++;	/* 1-4 */
+
+	switch (irq) {
+	case 1:
+		irq = TXX9_IRQ_BASE + TX4939_IR_INTA;
+		break;
+	case 2:
+		irq = TXX9_IRQ_BASE + TX4939_IR_INTB;
+		break;
+	case 3:
+		irq = TXX9_IRQ_BASE + TX4939_IR_INTC;
+		break;
+	case 4:
+		irq = TXX9_IRQ_BASE + TX4939_IR_INTD;
+		break;
+	}
+	return irq;
+}
+
+void __init tx4939_setup_pcierr_irq(void)
+{
+	if (request_irq(TXX9_IRQ_BASE + TX4939_IR_PCIERR,
+			tx4927_pcierr_interrupt,
+			IRQF_DISABLED, "PCI error",
+			(void *)TX4939_PCIC_REG))
+		pr_warning("Failed to request irq for PCIERR\n");
+}
diff --git a/arch/mips/txx9/Kconfig b/arch/mips/txx9/Kconfig
index aade334..58691a1 100644
--- a/arch/mips/txx9/Kconfig
+++ b/arch/mips/txx9/Kconfig
@@ -71,6 +71,13 @@ config SOC_TX4938
 	select PCI_TX4927
 	select GPIO_TXX9
 
+config SOC_TX4939
+	bool
+	select CEVT_TXX9
+	select HAS_TXX9_SERIAL
+	select HW_HAS_PCI
+	select PCI_TX4927
+
 config TOSHIBA_FPCIB0
 	bool "FPCIB0 Backplane Support"
 	depends on PCI && MACH_TXX9
diff --git a/arch/mips/txx9/generic/Makefile b/arch/mips/txx9/generic/Makefile
index 986852c..0030d23 100644
--- a/arch/mips/txx9/generic/Makefile
+++ b/arch/mips/txx9/generic/Makefile
@@ -7,6 +7,7 @@ obj-$(CONFIG_PCI)	+= pci.o
 obj-$(CONFIG_SOC_TX3927)	+= setup_tx3927.o irq_tx3927.o
 obj-$(CONFIG_SOC_TX4927)	+= mem_tx4927.o setup_tx4927.o irq_tx4927.o
 obj-$(CONFIG_SOC_TX4938)	+= mem_tx4927.o setup_tx4938.o irq_tx4938.o
+obj-$(CONFIG_SOC_TX4939)	+= setup_tx4939.o irq_tx4939.o
 obj-$(CONFIG_TOSHIBA_FPCIB0)	+= smsc_fdc37m81x.o
 obj-$(CONFIG_SPI)		+= spi_eeprom.o
 
diff --git a/arch/mips/txx9/generic/irq_tx4939.c b/arch/mips/txx9/generic/irq_tx4939.c
new file mode 100644
index 0000000..013213a
--- /dev/null
+++ b/arch/mips/txx9/generic/irq_tx4939.c
@@ -0,0 +1,215 @@
+/*
+ * TX4939 irq routines
+ * Based on linux/arch/mips/kernel/irq_txx9.c,
+ *	    and RBTX49xx patch from CELF patch archive.
+ *
+ * Copyright 2001, 2003-2005 MontaVista Software Inc.
+ * Author: MontaVista Software, Inc.
+ *         ahennessy@mvista.com
+ *         source@mvista.com
+ * Copyright (C) 2000-2001,2005-2007 Toshiba Corporation
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+/*
+ * TX4939 defines 64 IRQs.
+ * Similer to irq_txx9.c but different register layouts.
+ */
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/types.h>
+#include <asm/irq_cpu.h>
+#include <asm/txx9irq.h>
+#include <asm/txx9/tx4939.h>
+
+/* IRCER : Int. Control Enable */
+#define TXx9_IRCER_ICE	0x00000001
+
+/* IRCR : Int. Control */
+#define TXx9_IRCR_LOW	0x00000000
+#define TXx9_IRCR_HIGH	0x00000001
+#define TXx9_IRCR_DOWN	0x00000002
+#define TXx9_IRCR_UP	0x00000003
+#define TXx9_IRCR_EDGE(cr)	((cr) & 0x00000002)
+
+/* IRSCR : Int. Status Control */
+#define TXx9_IRSCR_EIClrE	0x00000100
+#define TXx9_IRSCR_EIClr_MASK	0x0000000f
+
+/* IRCSR : Int. Current Status */
+#define TXx9_IRCSR_IF	0x00010000
+
+#define irc_dlevel	0
+#define irc_elevel	1
+
+static struct {
+	unsigned char level;
+	unsigned char mode;
+} tx4939irq[TX4939_NUM_IR] __read_mostly;
+
+static void tx4939_irq_unmask(unsigned int irq)
+{
+	unsigned int irq_nr = irq - TXX9_IRQ_BASE;
+	u32 __iomem *lvlp;
+	int ofs;
+	if (irq_nr < 32) {
+		irq_nr--;
+		lvlp = &tx4939_ircptr->lvl[(irq_nr % 16) / 2].r;
+	} else {
+		irq_nr -= 32;
+		lvlp = &tx4939_ircptr->lvl[8 + (irq_nr % 16) / 2].r;
+	}
+	ofs = (irq_nr & 16) + (irq_nr & 1) * 8;
+	__raw_writel((__raw_readl(lvlp) & ~(0xff << ofs))
+		     | (tx4939irq[irq_nr].level << ofs),
+		     lvlp);
+}
+
+static inline void tx4939_irq_mask(unsigned int irq)
+{
+	unsigned int irq_nr = irq - TXX9_IRQ_BASE;
+	u32 __iomem *lvlp;
+	int ofs;
+	if (irq_nr < 32) {
+		irq_nr--;
+		lvlp = &tx4939_ircptr->lvl[(irq_nr % 16) / 2].r;
+	} else {
+		irq_nr -= 32;
+		lvlp = &tx4939_ircptr->lvl[8 + (irq_nr % 16) / 2].r;
+	}
+	ofs = (irq_nr & 16) + (irq_nr & 1) * 8;
+	__raw_writel((__raw_readl(lvlp) & ~(0xff << ofs))
+		     | (irc_dlevel << ofs),
+		     lvlp);
+	mmiowb();
+}
+
+static void tx4939_irq_mask_ack(unsigned int irq)
+{
+	unsigned int irq_nr = irq - TXX9_IRQ_BASE;
+
+	tx4939_irq_mask(irq);
+	if (TXx9_IRCR_EDGE(tx4939irq[irq_nr].mode)) {
+		irq_nr--;
+		/* clear edge detection */
+		__raw_writel((TXx9_IRSCR_EIClrE | (irq_nr & 0xf))
+			     << (irq_nr & 0x10),
+			     &tx4939_ircptr->edc.r);
+	}
+}
+
+static int tx4939_irq_set_type(unsigned int irq, unsigned int flow_type)
+{
+	unsigned int irq_nr = irq - TXX9_IRQ_BASE;
+	u32 cr;
+	u32 __iomem *crp;
+	int ofs;
+	int mode;
+
+	if (flow_type & IRQF_TRIGGER_PROBE)
+		return 0;
+	switch (flow_type & IRQF_TRIGGER_MASK) {
+	case IRQF_TRIGGER_RISING:
+		mode = TXx9_IRCR_UP;
+		break;
+	case IRQF_TRIGGER_FALLING:
+		mode = TXx9_IRCR_DOWN;
+		break;
+	case IRQF_TRIGGER_HIGH:
+		mode = TXx9_IRCR_HIGH;
+		break;
+	case IRQF_TRIGGER_LOW:
+		mode = TXx9_IRCR_LOW;
+		break;
+	default:
+		return -EINVAL;
+	}
+	if (irq_nr < 32) {
+		irq_nr--;
+		crp = &tx4939_ircptr->dm[(irq_nr & 8) >> 3].r;
+	} else {
+		irq_nr -= 32;
+		crp = &tx4939_ircptr->dm2[((irq_nr & 8) >> 3)].r;
+	}
+	ofs = (((irq_nr & 16) >> 1) | (irq_nr & (8 - 1))) * 2;
+	cr = __raw_readl(crp);
+	cr &= ~(0x3 << ofs);
+	cr |= (mode & 0x3) << ofs;
+	__raw_writel(cr, crp);
+	tx4939irq[irq_nr].mode = mode;
+	return 0;
+}
+
+static struct irq_chip tx4939_irq_chip = {
+	.name		= "TX4939",
+	.ack		= tx4939_irq_mask_ack,
+	.mask		= tx4939_irq_mask,
+	.mask_ack	= tx4939_irq_mask_ack,
+	.unmask		= tx4939_irq_unmask,
+	.set_type	= tx4939_irq_set_type,
+};
+
+static int tx4939_irq_set_pri(int irc_irq, int new_pri)
+{
+	int old_pri;
+
+	if ((unsigned int)irc_irq >= TX4939_NUM_IR)
+		return 0;
+	old_pri = tx4939irq[irc_irq].level;
+	tx4939irq[irc_irq].level = new_pri;
+	return old_pri;
+}
+
+void __init tx4939_irq_init(void)
+{
+	int i;
+
+	mips_cpu_irq_init();
+	/* disable interrupt control */
+	__raw_writel(0, &tx4939_ircptr->den.r);
+	__raw_writel(0, &tx4939_ircptr->maskint.r);
+	__raw_writel(0, &tx4939_ircptr->maskext.r);
+	/* irq_base + 0 is not used */
+	for (i = 1; i < TX4939_NUM_IR; i++) {
+		tx4939irq[i].level = 4; /* middle level */
+		tx4939irq[i].mode = TXx9_IRCR_LOW;
+		set_irq_chip_and_handler(TXX9_IRQ_BASE + i,
+					 &tx4939_irq_chip, handle_level_irq);
+	}
+
+	/* mask all IRC interrupts */
+	__raw_writel(0, &tx4939_ircptr->msk.r);
+	for (i = 0; i < 16; i++)
+		__raw_writel(0, &tx4939_ircptr->lvl[i].r);
+	/* setup IRC interrupt mode (Low Active) */
+	for (i = 0; i < 2; i++)
+		__raw_writel(0, &tx4939_ircptr->dm[i].r);
+	for (i = 0; i < 2; i++)
+		__raw_writel(0, &tx4939_ircptr->dm2[i].r);
+	/* enable interrupt control */
+	__raw_writel(TXx9_IRCER_ICE, &tx4939_ircptr->den.r);
+	__raw_writel(irc_elevel, &tx4939_ircptr->msk.r);
+
+	set_irq_chained_handler(MIPS_CPU_IRQ_BASE + TX4939_IRC_INT,
+				handle_simple_irq);
+
+	/* raise priority for errors, timers, sio */
+	tx4939_irq_set_pri(TX4939_IR_WTOERR, 7);
+	tx4939_irq_set_pri(TX4939_IR_PCIERR, 7);
+	tx4939_irq_set_pri(TX4939_IR_PCIPME, 7);
+	for (i = 0; i < TX4939_NUM_IR_TMR; i++)
+		tx4939_irq_set_pri(TX4939_IR_TMR(i), 6);
+	for (i = 0; i < TX4939_NUM_IR_SIO; i++)
+		tx4939_irq_set_pri(TX4939_IR_SIO(i), 5);
+}
+
+int tx4939_irq(void)
+{
+	u32 csr = __raw_readl(&tx4939_ircptr->cs.r);
+
+	if (likely(!(csr & TXx9_IRCSR_IF)))
+		return TXX9_IRQ_BASE + (csr & (TX4939_NUM_IR - 1));
+	return -1;
+}
diff --git a/arch/mips/txx9/generic/setup_tx4939.c b/arch/mips/txx9/generic/setup_tx4939.c
new file mode 100644
index 0000000..f14a497
--- /dev/null
+++ b/arch/mips/txx9/generic/setup_tx4939.c
@@ -0,0 +1,460 @@
+/*
+ * TX4939 setup routines
+ * Based on linux/arch/mips/txx9/generic/setup_tx4938.c,
+ *	    and RBTX49xx patch from CELF patch archive.
+ *
+ * 2003-2005 (c) MontaVista Software, Inc.
+ * (C) Copyright TOSHIBA CORPORATION 2000-2001, 2004-2007
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <linux/init.h>
+#include <linux/ioport.h>
+#include <linux/delay.h>
+#include <linux/netdevice.h>
+#include <linux/notifier.h>
+#include <linux/sysdev.h>
+#include <linux/ethtool.h>
+#include <linux/param.h>
+#include <linux/ptrace.h>
+#include <linux/mtd/physmap.h>
+#include <asm/bootinfo.h>
+#include <asm/reboot.h>
+#include <asm/traps.h>
+#include <asm/txx9irq.h>
+#include <asm/txx9tmr.h>
+#include <asm/txx9/generic.h>
+#include <asm/txx9/tx4939.h>
+
+static void __init tx4939_wdr_init(void)
+{
+	/* report watchdog reset status */
+	if (____raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_WDRST)
+		pr_warning("Watchdog reset detected at 0x%lx\n",
+			   read_c0_errorepc());
+	/* clear WatchDogReset (W1C) */
+	tx4939_ccfg_set(TX4939_CCFG_WDRST);
+	/* do reset on watchdog */
+	tx4939_ccfg_set(TX4939_CCFG_WR);
+}
+
+void __init tx4939_wdt_init(void)
+{
+	txx9_wdt_init(TX4939_TMR_REG(2) & 0xfffffffffULL);
+}
+
+static void tx4939_machine_restart(char *command)
+{
+	local_irq_disable();
+	pr_emerg("Rebooting (with %s watchdog reset)...\n",
+		 (____raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_WDREXEN) ?
+		 "external" : "internal");
+	/* clear watchdog status */
+	tx4939_ccfg_set(TX4939_CCFG_WDRST);	/* W1C */
+	txx9_wdt_now(TX4939_TMR_REG(2) & 0xfffffffffULL);
+	while (!(____raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_WDRST))
+		;
+	mdelay(10);
+	if (____raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_WDREXEN) {
+		pr_emerg("Rebooting (with internal watchdog reset)...\n");
+		/* External WDRST failed.  Do internal watchdog reset */
+		tx4939_ccfg_clear(TX4939_CCFG_WDREXEN);
+	}
+	/* fallback */
+	(*_machine_halt)();
+}
+
+void show_registers(struct pt_regs *regs);
+static int tx4939_be_handler(struct pt_regs *regs, int is_fixup)
+{
+	int data = regs->cp0_cause & 4;
+	console_verbose();
+	pr_err("%cBE exception at %#lx\n",
+	       data ? 'D' : 'I', regs->cp0_epc);
+	pr_err("ccfg:%llx, toea:%llx\n",
+	       (unsigned long long)____raw_readq(&tx4939_ccfgptr->ccfg),
+	       (unsigned long long)____raw_readq(&tx4939_ccfgptr->toea));
+#ifdef CONFIG_PCI
+	tx4927_report_pcic_status();
+#endif
+	show_registers(regs);
+	panic("BusError!");
+}
+static void __init tx4939_be_init(void)
+{
+	board_be_handler = tx4939_be_handler;
+}
+
+static struct resource tx4939_sdram_resource[4];
+static struct resource tx4939_sram_resource;
+#define TX4939_SRAM_SIZE 0x800
+
+void __init tx4939_add_memory_regions(void)
+{
+	int i;
+	unsigned long start, size;
+	u64 win;
+
+	for (i = 0; i < 4; i++) {
+		if (!((__u32)____raw_readq(&tx4939_ddrcptr->winen) & (1 << i)))
+			continue;
+		win = ____raw_readq(&tx4939_ddrcptr->win[i]);
+		start = (unsigned long)(win >> 48);
+		size = (((unsigned long)(win >> 32) & 0xffff) + 1) - start;
+		add_memory_region(start << 20, size << 20, BOOT_MEM_RAM);
+	}
+}
+
+void __init tx4939_setup(void)
+{
+	int i;
+	__u32 divmode;
+	__u64 pcfg;
+	int cpuclk = 0;
+
+	txx9_reg_res_init(TX4939_REV_PCODE(), TX4939_REG_BASE,
+			  TX4939_REG_SIZE);
+	set_c0_config(TX49_CONF_CWFON);
+
+	/* SDRAMC,EBUSC are configured by PROM */
+	for (i = 0; i < 4; i++) {
+		if (!(TX4939_EBUSC_CR(i) & 0x8))
+			continue;	/* disabled */
+		txx9_ce_res[i].start = (unsigned long)TX4939_EBUSC_BA(i);
+		txx9_ce_res[i].end =
+			txx9_ce_res[i].start + TX4939_EBUSC_SIZE(i) - 1;
+		request_resource(&iomem_resource, &txx9_ce_res[i]);
+	}
+
+	/* clocks */
+	if (txx9_master_clock) {
+		/* calculate cpu_clock from master_clock */
+		divmode = (__u32)____raw_readq(&tx4939_ccfgptr->ccfg) &
+			TX4939_CCFG_MULCLK_MASK;
+		cpuclk = txx9_master_clock * 20 / 2;
+		switch (divmode) {
+		case TX4939_CCFG_MULCLK_8:
+			cpuclk = cpuclk / 3 * 4 /* / 6 *  8 */; break;
+		case TX4939_CCFG_MULCLK_9:
+			cpuclk = cpuclk / 2 * 3 /* / 6 *  9 */; break;
+		case TX4939_CCFG_MULCLK_10:
+			cpuclk = cpuclk / 3 * 5 /* / 6 * 10 */; break;
+		case TX4939_CCFG_MULCLK_11:
+			cpuclk = cpuclk / 6 * 11; break;
+		case TX4939_CCFG_MULCLK_12:
+			cpuclk = cpuclk * 2 /* / 6 * 12 */; break;
+		case TX4939_CCFG_MULCLK_13:
+			cpuclk = cpuclk / 6 * 13; break;
+		case TX4939_CCFG_MULCLK_14:
+			cpuclk = cpuclk / 3 * 7 /* / 6 * 14 */; break;
+		case TX4939_CCFG_MULCLK_15:
+			cpuclk = cpuclk / 2 * 5 /* / 6 * 15 */; break;
+		}
+		txx9_cpu_clock = cpuclk;
+	} else {
+		if (txx9_cpu_clock == 0)
+			txx9_cpu_clock = 400000000;	/* 400MHz */
+		/* calculate master_clock from cpu_clock */
+		cpuclk = txx9_cpu_clock;
+		divmode = (__u32)____raw_readq(&tx4939_ccfgptr->ccfg) &
+			TX4939_CCFG_MULCLK_MASK;
+		switch (divmode) {
+		case TX4939_CCFG_MULCLK_8:
+			txx9_master_clock = cpuclk * 6 / 8; break;
+		case TX4939_CCFG_MULCLK_9:
+			txx9_master_clock = cpuclk * 6 / 9; break;
+		case TX4939_CCFG_MULCLK_10:
+			txx9_master_clock = cpuclk * 6 / 10; break;
+		case TX4939_CCFG_MULCLK_11:
+			txx9_master_clock = cpuclk * 6 / 11; break;
+		case TX4939_CCFG_MULCLK_12:
+			txx9_master_clock = cpuclk * 6 / 12; break;
+		case TX4939_CCFG_MULCLK_13:
+			txx9_master_clock = cpuclk * 6 / 13; break;
+		case TX4939_CCFG_MULCLK_14:
+			txx9_master_clock = cpuclk * 6 / 14; break;
+		case TX4939_CCFG_MULCLK_15:
+			txx9_master_clock = cpuclk * 6 / 15; break;
+		}
+		txx9_master_clock /= 10; /* * 2 / 20 */
+	}
+	/* calculate gbus_clock from cpu_clock */
+	divmode = (__u32)____raw_readq(&tx4939_ccfgptr->ccfg) &
+		TX4939_CCFG_YDIVMODE_MASK;
+	txx9_gbus_clock = txx9_cpu_clock;
+	switch (divmode) {
+	case TX4939_CCFG_YDIVMODE_2:
+		txx9_gbus_clock /= 2; break;
+	case TX4939_CCFG_YDIVMODE_3:
+		txx9_gbus_clock /= 3; break;
+	case TX4939_CCFG_YDIVMODE_5:
+		txx9_gbus_clock /= 5; break;
+	case TX4939_CCFG_YDIVMODE_6:
+		txx9_gbus_clock /= 6; break;
+	}
+	/* change default value to udelay/mdelay take reasonable time */
+	loops_per_jiffy = txx9_cpu_clock / HZ / 2;
+
+	/* CCFG */
+	tx4939_wdr_init();
+	/* clear BusErrorOnWrite flag (W1C) */
+	tx4939_ccfg_set(TX4939_CCFG_WDRST | TX4939_CCFG_BEOW);
+	/* enable Timeout BusError */
+	if (txx9_ccfg_toeon)
+		tx4939_ccfg_set(TX4939_CCFG_TOE);
+
+	/* DMA selection */
+	txx9_clear64(&tx4939_ccfgptr->pcfg, TX4939_PCFG_DMASEL_ALL);
+
+	/* Use external clock for external arbiter */
+	if (!(____raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_PCIARB))
+		txx9_clear64(&tx4939_ccfgptr->pcfg, TX4939_PCFG_PCICLKEN_ALL);
+
+	pr_info("%s -- %dMHz(M%dMHz,G%dMHz) CRIR:%08x CCFG:%llx PCFG:%llx\n",
+		txx9_pcode_str,
+		(cpuclk + 500000) / 1000000,
+		(txx9_master_clock + 500000) / 1000000,
+		(txx9_gbus_clock + 500000) / 1000000,
+		(__u32)____raw_readq(&tx4939_ccfgptr->crir),
+		(unsigned long long)____raw_readq(&tx4939_ccfgptr->ccfg),
+		(unsigned long long)____raw_readq(&tx4939_ccfgptr->pcfg));
+
+	pr_info("%s DDRC -- EN:%08x", txx9_pcode_str,
+		(__u32)____raw_readq(&tx4939_ddrcptr->winen));
+	for (i = 0; i < 4; i++) {
+		__u64 win = ____raw_readq(&tx4939_ddrcptr->win[i]);
+		if (!((__u32)____raw_readq(&tx4939_ddrcptr->winen) & (1 << i)))
+			continue;	/* disabled */
+		printk(KERN_CONT " #%d:%016llx", i, (unsigned long long)win);
+		tx4939_sdram_resource[i].name = "DDR SDRAM";
+		tx4939_sdram_resource[i].start =
+			(unsigned long)(win >> 48) << 20;
+		tx4939_sdram_resource[i].end =
+			((((unsigned long)(win >> 32) & 0xffff) + 1) <<
+			 20) - 1;
+		tx4939_sdram_resource[i].flags = IORESOURCE_MEM;
+		request_resource(&iomem_resource, &tx4939_sdram_resource[i]);
+	}
+	printk(KERN_CONT "\n");
+
+	/* SRAM */
+	if (____raw_readq(&tx4939_sramcptr->cr) & 1) {
+		unsigned int size = TX4939_SRAM_SIZE;
+		tx4939_sram_resource.name = "SRAM";
+		tx4939_sram_resource.start =
+			(____raw_readq(&tx4939_sramcptr->cr) >> (39-11))
+			& ~(size - 1);
+		tx4939_sram_resource.end =
+			tx4939_sram_resource.start + TX4939_SRAM_SIZE - 1;
+		tx4939_sram_resource.flags = IORESOURCE_MEM;
+		request_resource(&iomem_resource, &tx4939_sram_resource);
+	}
+
+	/* TMR */
+	/* disable all timers */
+	for (i = 0; i < TX4939_NR_TMR; i++)
+		txx9_tmr_init(TX4939_TMR_REG(i) & 0xfffffffffULL);
+
+	/* DMA */
+	for (i = 0; i < 2; i++)
+		____raw_writeq(TX4938_DMA_MCR_MSTEN,
+			       (void __iomem *)(TX4939_DMA_REG(i) + 0x50));
+
+	/* set PCIC1 reset (required to prevent hangup on BIST) */
+	txx9_set64(&tx4939_ccfgptr->clkctr, TX4939_CLKCTR_PCI1RST);
+	pcfg = ____raw_readq(&tx4939_ccfgptr->pcfg);
+	if (pcfg & (TX4939_PCFG_ET0MODE | TX4939_PCFG_ET1MODE)) {
+		mdelay(1);	/* at least 128 cpu clock */
+		/* clear PCIC1 reset */
+		txx9_clear64(&tx4939_ccfgptr->clkctr, TX4939_CLKCTR_PCI1RST);
+	} else {
+		pr_info("%s: stop PCIC1\n", txx9_pcode_str);
+		/* stop PCIC1 */
+		txx9_set64(&tx4939_ccfgptr->clkctr, TX4939_CLKCTR_PCI1CKD);
+	}
+	if (!(pcfg & TX4939_PCFG_ET0MODE)) {
+		pr_info("%s: stop ETH0\n", txx9_pcode_str);
+		txx9_set64(&tx4939_ccfgptr->clkctr, TX4939_CLKCTR_ETH0RST);
+		txx9_set64(&tx4939_ccfgptr->clkctr, TX4939_CLKCTR_ETH0CKD);
+	}
+	if (!(pcfg & TX4939_PCFG_ET1MODE)) {
+		pr_info("%s: stop ETH1\n", txx9_pcode_str);
+		txx9_set64(&tx4939_ccfgptr->clkctr, TX4939_CLKCTR_ETH1RST);
+		txx9_set64(&tx4939_ccfgptr->clkctr, TX4939_CLKCTR_ETH1CKD);
+	}
+
+	_machine_restart = tx4939_machine_restart;
+	board_be_init = tx4939_be_init;
+}
+
+void __init tx4939_time_init(unsigned int tmrnr)
+{
+	if (____raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_TINTDIS)
+		txx9_clockevent_init(TX4939_TMR_REG(tmrnr) & 0xfffffffffULL,
+				     TXX9_IRQ_BASE + TX4939_IR_TMR(tmrnr),
+				     TXX9_IMCLK);
+}
+
+void __init tx4939_sio_init(unsigned int sclk, unsigned int cts_mask)
+{
+	int i;
+	unsigned int ch_mask = 0;
+	__u64 pcfg = __raw_readq(&tx4939_ccfgptr->pcfg);
+
+	cts_mask |= ~1;	/* only SIO0 have RTS/CTS */
+	if ((pcfg & TX4939_PCFG_SIO2MODE_MASK) != TX4939_PCFG_SIO2MODE_SIO0)
+		cts_mask |= 1 << 0; /* disable SIO0 RTS/CTS by PCFG setting */
+	if ((pcfg & TX4939_PCFG_SIO2MODE_MASK) != TX4939_PCFG_SIO2MODE_SIO2)
+		ch_mask |= 1 << 2; /* disable SIO2 by PCFG setting */
+	if (pcfg & TX4939_PCFG_SIO3MODE)
+		ch_mask |= 1 << 3; /* disable SIO3 by PCFG setting */
+	for (i = 0; i < 4; i++) {
+		if ((1 << i) & ch_mask)
+			continue;
+		txx9_sio_init(TX4939_SIO_REG(i) & 0xfffffffffULL,
+			      TXX9_IRQ_BASE + TX4939_IR_SIO(i),
+			      i, sclk, (1 << i) & cts_mask);
+	}
+}
+
+#if defined(CONFIG_TC35815) || defined(CONFIG_TC35815_MODULE)
+static int tx4939_get_eth_speed(struct net_device *dev)
+{
+	struct ethtool_cmd cmd = { ETHTOOL_GSET };
+	int speed = 100;	/* default 100Mbps */
+	int err;
+	if (!dev->ethtool_ops || !dev->ethtool_ops->get_settings)
+		return speed;
+	err = dev->ethtool_ops->get_settings(dev, &cmd);
+	if (err < 0)
+		return speed;
+	speed = cmd.speed == SPEED_100 ? 100 : 10;
+	return speed;
+}
+static int tx4939_netdev_event(struct notifier_block *this,
+			       unsigned long event,
+			       void *ptr)
+{
+	struct net_device *dev = ptr;
+	if (event == NETDEV_CHANGE && netif_carrier_ok(dev)) {
+		__u64 bit = 0;
+		if (dev->irq == TXX9_IRQ_BASE + TX4939_IR_ETH(0))
+			bit = TX4939_PCFG_SPEED0;
+		else if (dev->irq == TXX9_IRQ_BASE + TX4939_IR_ETH(1))
+			bit = TX4939_PCFG_SPEED1;
+		if (bit) {
+			int speed = tx4939_get_eth_speed(dev);
+			if (speed == 100)
+				txx9_set64(&tx4939_ccfgptr->pcfg, bit);
+			else
+				txx9_clear64(&tx4939_ccfgptr->pcfg, bit);
+		}
+	}
+	return NOTIFY_DONE;
+}
+
+static struct notifier_block tx4939_netdev_notifier = {
+	.notifier_call = tx4939_netdev_event,
+	.priority = 1,
+};
+
+void __init tx4939_ethaddr_init(unsigned char *addr0, unsigned char *addr1)
+{
+	u64 pcfg = __raw_readq(&tx4939_ccfgptr->pcfg);
+
+	if (addr0 && (pcfg & TX4939_PCFG_ET0MODE))
+		txx9_ethaddr_init(TXX9_IRQ_BASE + TX4939_IR_ETH(0), addr0);
+	if (addr1 && (pcfg & TX4939_PCFG_ET1MODE))
+		txx9_ethaddr_init(TXX9_IRQ_BASE + TX4939_IR_ETH(1), addr1);
+	register_netdevice_notifier(&tx4939_netdev_notifier);
+}
+#else
+void __init tx4939_ethaddr_init(unsigned char *addr0, unsigned char *addr1)
+{
+}
+#endif
+
+void __init tx4939_mtd_init(int ch)
+{
+	struct physmap_flash_data pdata = {
+		.width = TX4939_EBUSC_WIDTH(ch) / 8,
+	};
+	unsigned long start = txx9_ce_res[ch].start;
+	unsigned long size = txx9_ce_res[ch].end - start + 1;
+
+	if (!(TX4939_EBUSC_CR(ch) & 0x8))
+		return;	/* disabled */
+	txx9_physmap_flash_init(ch, start, size, &pdata);
+}
+
+static void __init tx4939_stop_unused_modules(void)
+{
+	__u64 pcfg, rst = 0, ckd = 0;
+	char buf[128];
+
+	buf[0] = '\0';
+	local_irq_disable();
+	pcfg = ____raw_readq(&tx4939_ccfgptr->pcfg);
+	if ((pcfg & TX4939_PCFG_I2SMODE_MASK) !=
+	    TX4939_PCFG_I2SMODE_ACLC) {
+		rst |= TX4939_CLKCTR_ACLRST;
+		ckd |= TX4939_CLKCTR_ACLCKD;
+		strcat(buf, " ACLC");
+	}
+	if ((pcfg & TX4939_PCFG_I2SMODE_MASK) !=
+	    TX4939_PCFG_I2SMODE_I2S &&
+	    (pcfg & TX4939_PCFG_I2SMODE_MASK) !=
+	    TX4939_PCFG_I2SMODE_I2S_ALT) {
+		rst |= TX4939_CLKCTR_I2SRST;
+		ckd |= TX4939_CLKCTR_I2SCKD;
+		strcat(buf, " I2S");
+	}
+	if (!(pcfg & TX4939_PCFG_ATA0MODE)) {
+		rst |= TX4939_CLKCTR_ATA0RST;
+		ckd |= TX4939_CLKCTR_ATA0CKD;
+		strcat(buf, " ATA0");
+	}
+	if (!(pcfg & TX4939_PCFG_ATA1MODE)) {
+		rst |= TX4939_CLKCTR_ATA1RST;
+		ckd |= TX4939_CLKCTR_ATA1CKD;
+		strcat(buf, " ATA1");
+	}
+	if (pcfg & TX4939_PCFG_SPIMODE) {
+		rst |= TX4939_CLKCTR_SPIRST;
+		ckd |= TX4939_CLKCTR_SPICKD;
+		strcat(buf, " SPI");
+	}
+	if (!(pcfg & (TX4939_PCFG_VSSMODE | TX4939_PCFG_VPSMODE))) {
+		rst |= TX4939_CLKCTR_VPCRST;
+		ckd |= TX4939_CLKCTR_VPCCKD;
+		strcat(buf, " VPC");
+	}
+	if ((pcfg & TX4939_PCFG_SIO2MODE_MASK) != TX4939_PCFG_SIO2MODE_SIO2) {
+		rst |= TX4939_CLKCTR_SIO2RST;
+		ckd |= TX4939_CLKCTR_SIO2CKD;
+		strcat(buf, " SIO2");
+	}
+	if (pcfg & TX4939_PCFG_SIO3MODE) {
+		rst |= TX4939_CLKCTR_SIO3RST;
+		ckd |= TX4939_CLKCTR_SIO3CKD;
+		strcat(buf, " SIO3");
+	}
+	if (rst | ckd) {
+		txx9_set64(&tx4939_ccfgptr->clkctr, rst);
+		txx9_set64(&tx4939_ccfgptr->clkctr, ckd);
+	}
+	local_irq_enable();
+	if (buf[0])
+		pr_info("%s: stop%s\n", txx9_pcode_str, buf);
+}
+
+static int __init tx4939_late_init(void)
+{
+	if (txx9_pcode != 0x4939)
+		return -ENODEV;
+	tx4939_stop_unused_modules();
+	return 0;
+}
+late_initcall(tx4939_late_init);
diff --git a/include/asm-mips/txx9/tx4939.h b/include/asm-mips/txx9/tx4939.h
new file mode 100644
index 0000000..7ce2dff
--- /dev/null
+++ b/include/asm-mips/txx9/tx4939.h
@@ -0,0 +1,544 @@
+/*
+ * Definitions for TX4939
+ *
+ * Copyright (C) 2000-2001,2005-2006 Toshiba Corporation
+ * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
+ * terms of the GNU General Public License version 2. This program is
+ * licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+#ifndef __ASM_TXX9_TX4939_H
+#define __ASM_TXX9_TX4939_H
+
+/* some controllers are compatible with 4927/4938 */
+#include <asm/txx9/tx4938.h>
+
+#ifdef CONFIG_64BIT
+#define TX4939_REG_BASE	0xffffffffff1f0000UL /* == TX4938_REG_BASE */
+#else
+#define TX4939_REG_BASE	0xff1f0000UL /* == TX4938_REG_BASE */
+#endif
+#define TX4939_REG_SIZE	0x00010000 /* == TX4938_REG_SIZE */
+
+#define TX4939_ATA_REG(ch)	(TX4939_REG_BASE + 0x3000 + (ch) * 0x1000)
+#define TX4939_NDFMC_REG	(TX4939_REG_BASE + 0x5000)
+#define TX4939_SRAMC_REG	(TX4939_REG_BASE + 0x6000)
+#define TX4939_CRYPTO_REG	(TX4939_REG_BASE + 0x6800)
+#define TX4939_PCIC1_REG	(TX4939_REG_BASE + 0x7000)
+#define TX4939_DDRC_REG		(TX4939_REG_BASE + 0x8000)
+#define TX4939_EBUSC_REG	(TX4939_REG_BASE + 0x9000)
+#define TX4939_VPC_REG		(TX4939_REG_BASE + 0xa000)
+#define TX4939_DMA_REG(ch)	(TX4939_REG_BASE + 0xb000 + (ch) * 0x800)
+#define TX4939_PCIC_REG		(TX4939_REG_BASE + 0xd000)
+#define TX4939_CCFG_REG		(TX4939_REG_BASE + 0xe000)
+#define TX4939_IRC_REG		(TX4939_REG_BASE + 0xe800)
+#define TX4939_NR_TMR	6	/* 0xf000,0xf100,0xf200,0xfd00,0xfe00,0xff00 */
+#define TX4939_TMR_REG(ch)	\
+	(TX4939_REG_BASE + 0xf000 + ((ch) + ((ch) >= 3) * 10) * 0x100)
+#define TX4939_NR_SIO	4	/* 0xf300, 0xf400, 0xf380, 0xf480 */
+#define TX4939_SIO_REG(ch)	\
+	(TX4939_REG_BASE + 0xf300 + (((ch) & 1) << 8) + (((ch) & 2) << 6))
+#define TX4939_ACLC_REG		(TX4939_REG_BASE + 0xf700)
+#define TX4939_SPI_REG		(TX4939_REG_BASE + 0xf800)
+#define TX4939_I2C_REG		(TX4939_REG_BASE + 0xf900)
+#define TX4939_I2S_REG		(TX4939_REG_BASE + 0xfa00)
+#define TX4939_RTC_REG		(TX4939_REG_BASE + 0xfb00)
+#define TX4939_CIR_REG		(TX4939_REG_BASE + 0xfc00)
+
+struct tx4939_le_reg {
+	__u32 r;
+	__u32 unused;
+};
+
+struct tx4939_ddrc_reg {
+	struct tx4939_le_reg ctl[47];
+	__u64 unused0[17];
+	__u64 winen;
+	__u64 win[4];
+};
+
+struct tx4939_ccfg_reg {
+	__u64 ccfg;
+	__u64 crir;
+	__u64 pcfg;
+	__u64 toea;
+	__u64 clkctr;
+	__u64 unused0;
+	__u64 garbc;
+	__u64 unused1[2];
+	__u64 ramp;
+	__u64 unused2[2];
+	__u64 dskwctrl;
+	__u64 mclkosc;
+	__u64 mclkctl;
+	__u64 unused3[17];
+	struct {
+		__u64 mr;
+		__u64 dr;
+	} gpio[2];
+};
+
+struct tx4939_irc_reg {
+	struct tx4939_le_reg den;
+	struct tx4939_le_reg scipb;
+	struct tx4939_le_reg dm[2];
+	struct tx4939_le_reg lvl[16];
+	struct tx4939_le_reg msk;
+	struct tx4939_le_reg edc;
+	struct tx4939_le_reg pnd0;
+	struct tx4939_le_reg cs;
+	struct tx4939_le_reg pnd1;
+	struct tx4939_le_reg dm2[2];
+	struct tx4939_le_reg dbr[2];
+	struct tx4939_le_reg dben;
+	struct tx4939_le_reg unused0[2];
+	struct tx4939_le_reg flag[2];
+	struct tx4939_le_reg pol;
+	struct tx4939_le_reg cnt;
+	struct tx4939_le_reg maskint;
+	struct tx4939_le_reg maskext;
+};
+
+struct tx4939_rtc_reg {
+	__u32 ctl;
+	__u32 adr;
+	__u32 dat;
+	__u32 tbc;
+};
+
+struct tx4939_crypto_reg {
+	struct tx4939_le_reg csr;
+	struct tx4939_le_reg idesptr;
+	struct tx4939_le_reg cdesptr;
+	struct tx4939_le_reg buserr;
+	struct tx4939_le_reg cip_tout;
+	struct tx4939_le_reg cir;
+	union {
+		struct {
+			struct tx4939_le_reg data[8];
+			struct tx4939_le_reg ctrl;
+		} gen;
+		struct {
+			struct {
+				struct tx4939_le_reg l;
+				struct tx4939_le_reg u;
+			} key[3], ini;
+			struct tx4939_le_reg ctrl;
+		} des;
+		struct {
+			struct tx4939_le_reg key[4];
+			struct tx4939_le_reg ini[4];
+			struct tx4939_le_reg ctrl;
+		} aes;
+		struct {
+			struct {
+				struct tx4939_le_reg l;
+				struct tx4939_le_reg u;
+			} cnt;
+			struct tx4939_le_reg ini[5];
+			struct tx4939_le_reg unused;
+			struct tx4939_le_reg ctrl;
+		} hash;
+	} cdr;
+	struct tx4939_le_reg unused0[7];
+	struct tx4939_le_reg rcsr;
+	struct tx4939_le_reg rpr;
+	__u64 rdr;
+	__u64 ror[3];
+	struct tx4939_le_reg unused1[2];
+	struct tx4939_le_reg xorslr;
+	struct tx4939_le_reg xorsur;
+};
+
+struct tx4939_crypto_desc {
+	__u32 src;
+	__u32 dst;
+	__u32 next;
+	__u32 ctrl;
+	__u32 index;
+	__u32 xor;
+};
+
+struct tx4939_vpc_reg {
+	struct tx4939_le_reg csr;
+	struct {
+		struct tx4939_le_reg ctrlA;
+		struct tx4939_le_reg ctrlB;
+		struct tx4939_le_reg idesptr;
+		struct tx4939_le_reg cdesptr;
+	} port[3];
+	struct tx4939_le_reg buserr;
+};
+
+struct tx4939_vpc_desc {
+	__u32 src;
+	__u32 next;
+	__u32 ctrl1;
+	__u32 ctrl2;
+};
+
+/*
+ * IRC
+ */
+#define TX4939_IR_NONE	0
+#define TX4939_IR_DDR	1
+#define TX4939_IR_WTOERR	2
+#define TX4939_NUM_IR_INT	3
+#define TX4939_IR_INT(n)	(3 + (n))
+#define TX4939_NUM_IR_ETH	2
+#define TX4939_IR_ETH(n)	((n) ? 43 : 6)
+#define TX4939_IR_VIDEO	7
+#define TX4939_IR_CIR	8
+#define TX4939_NUM_IR_SIO	4
+#define TX4939_IR_SIO(n)	((n) ? 43 + (n) : 9)	/* 9,44-46 */
+#define TX4939_NUM_IR_DMA	4
+#define TX4939_IR_DMA(ch, n)	(((ch) ? 22 : 10) + (n)) /* 10-13,22-25 */
+#define TX4939_IR_IRC	14
+#define TX4939_IR_PDMAC	15
+#define TX4939_NUM_IR_TMR	6
+#define TX4939_IR_TMR(n)	(((n) >= 3 ? 45 : 16) + (n)) /* 16-18,48-50 */
+#define TX4939_NUM_IR_ATA	2
+#define TX4939_IR_ATA(n)	(19 + (n))
+#define TX4939_IR_ACLC	21
+#define TX4939_IR_CIPHER	26
+#define TX4939_IR_INTA	27
+#define TX4939_IR_INTB	28
+#define TX4939_IR_INTC	29
+#define TX4939_IR_INTD	30
+#define TX4939_IR_I2C	33
+#define TX4939_IR_SPI	34
+#define TX4939_IR_PCIC	35
+#define TX4939_IR_PCIC1	36
+#define TX4939_IR_PCIERR	37
+#define TX4939_IR_PCIPME	38
+#define TX4939_IR_NDFMC	39
+#define TX4939_IR_ACLCPME	40
+#define TX4939_IR_RTC	41
+#define TX4939_IR_RND	42
+#define TX4939_IR_I2S	47
+#define TX4939_NUM_IR	64
+
+#define TX4939_IRC_INT	2	/* IP[2] in Status register */
+
+/*
+ * CCFG
+ */
+/* CCFG : Chip Configuration */
+#define TX4939_CCFG_PCIBOOT	0x0000040000000000ULL
+#define TX4939_CCFG_WDRST	0x0000020000000000ULL
+#define TX4939_CCFG_WDREXEN	0x0000010000000000ULL
+#define TX4939_CCFG_BCFG_MASK	0x000000ff00000000ULL
+#define TX4939_CCFG_GTOT_MASK	0x06000000
+#define TX4939_CCFG_GTOT_4096	0x06000000
+#define TX4939_CCFG_GTOT_2048	0x04000000
+#define TX4939_CCFG_GTOT_1024	0x02000000
+#define TX4939_CCFG_GTOT_512	0x00000000
+#define TX4939_CCFG_TINTDIS	0x01000000
+#define TX4939_CCFG_PCI66	0x00800000
+#define TX4939_CCFG_PCIMODE	0x00400000
+#define TX4939_CCFG_SSCG	0x00100000
+#define TX4939_CCFG_MULCLK_MASK	0x000e0000
+#define TX4939_CCFG_MULCLK_8	(0x7 << 17)
+#define TX4939_CCFG_MULCLK_9	(0x0 << 17)
+#define TX4939_CCFG_MULCLK_10	(0x1 << 17)
+#define TX4939_CCFG_MULCLK_11	(0x2 << 17)
+#define TX4939_CCFG_MULCLK_12	(0x3 << 17)
+#define TX4939_CCFG_MULCLK_13	(0x4 << 17)
+#define TX4939_CCFG_MULCLK_14	(0x5 << 17)
+#define TX4939_CCFG_MULCLK_15	(0x6 << 17)
+#define TX4939_CCFG_BEOW	0x00010000
+#define TX4939_CCFG_WR	0x00008000
+#define TX4939_CCFG_TOE	0x00004000
+#define TX4939_CCFG_PCIARB	0x00002000
+#define TX4939_CCFG_YDIVMODE_MASK	0x00001c00
+#define TX4939_CCFG_YDIVMODE_2	(0x0 << 10)
+#define TX4939_CCFG_YDIVMODE_3	(0x1 << 10)
+#define TX4939_CCFG_YDIVMODE_5	(0x6 << 10)
+#define TX4939_CCFG_YDIVMODE_6	(0x7 << 10)
+#define TX4939_CCFG_PTSEL	0x00000200
+#define TX4939_CCFG_BESEL	0x00000100
+#define TX4939_CCFG_SYSSP_MASK	0x000000c0
+#define TX4939_CCFG_ACKSEL	0x00000020
+#define TX4939_CCFG_ROMW	0x00000010
+#define TX4939_CCFG_ENDIAN	0x00000004
+#define TX4939_CCFG_ARMODE	0x00000002
+#define TX4939_CCFG_ACEHOLD	0x00000001
+
+/* PCFG : Pin Configuration */
+#define TX4939_PCFG_SIO2MODE_MASK	0xc000000000000000ULL
+#define TX4939_PCFG_SIO2MODE_GPIO	0x8000000000000000ULL
+#define TX4939_PCFG_SIO2MODE_SIO2	0x4000000000000000ULL
+#define TX4939_PCFG_SIO2MODE_SIO0	0x0000000000000000ULL
+#define TX4939_PCFG_SPIMODE	0x2000000000000000ULL
+#define TX4939_PCFG_I2CMODE	0x1000000000000000ULL
+#define TX4939_PCFG_I2SMODE_MASK	0x0c00000000000000ULL
+#define TX4939_PCFG_I2SMODE_GPIO	0x0c00000000000000ULL
+#define TX4939_PCFG_I2SMODE_I2S	0x0800000000000000ULL
+#define TX4939_PCFG_I2SMODE_I2S_ALT	0x0400000000000000ULL
+#define TX4939_PCFG_I2SMODE_ACLC	0x0000000000000000ULL
+#define TX4939_PCFG_SIO3MODE	0x0200000000000000ULL
+#define TX4939_PCFG_DMASEL3	0x0004000000000000ULL
+#define TX4939_PCFG_DMASEL3_SIO0	0x0004000000000000ULL
+#define TX4939_PCFG_DMASEL3_NDFC	0x0000000000000000ULL
+#define TX4939_PCFG_VSSMODE	0x0000200000000000ULL
+#define TX4939_PCFG_VPSMODE	0x0000100000000000ULL
+#define TX4939_PCFG_ET1MODE	0x0000080000000000ULL
+#define TX4939_PCFG_ET0MODE	0x0000040000000000ULL
+#define TX4939_PCFG_ATA1MODE	0x0000020000000000ULL
+#define TX4939_PCFG_ATA0MODE	0x0000010000000000ULL
+#define TX4939_PCFG_BP_PLL	0x0000000100000000ULL
+
+#define TX4939_PCFG_SYSCLKEN	0x08000000
+#define TX4939_PCFG_PCICLKEN_ALL	0x000f0000
+#define TX4939_PCFG_PCICLKEN(ch)	(0x00010000<<(ch))
+#define TX4939_PCFG_SPEED1	0x00002000
+#define TX4939_PCFG_SPEED0	0x00001000
+#define TX4939_PCFG_ITMODE	0x00000300
+#define TX4939_PCFG_DMASEL_ALL	(0x00000007 | TX4939_PCFG_DMASEL3)
+#define TX4939_PCFG_DMASEL2	0x00000004
+#define TX4939_PCFG_DMASEL2_DRQ2	0x00000000
+#define TX4939_PCFG_DMASEL2_SIO0	0x00000004
+#define TX4939_PCFG_DMASEL1	0x00000002
+#define TX4939_PCFG_DMASEL1_DRQ1	0x00000000
+#define TX4939_PCFG_DMASEL0	0x00000001
+#define TX4939_PCFG_DMASEL0_DRQ0	0x00000000
+
+/* CLKCTR : Clock Control */
+#define TX4939_CLKCTR_IOSCKD	0x8000000000000000ULL
+#define TX4939_CLKCTR_SYSCKD	0x4000000000000000ULL
+#define TX4939_CLKCTR_TM5CKD	0x2000000000000000ULL
+#define TX4939_CLKCTR_TM4CKD	0x1000000000000000ULL
+#define TX4939_CLKCTR_TM3CKD	0x0800000000000000ULL
+#define TX4939_CLKCTR_CIRCKD	0x0400000000000000ULL
+#define TX4939_CLKCTR_SIO3CKD	0x0200000000000000ULL
+#define TX4939_CLKCTR_SIO2CKD	0x0100000000000000ULL
+#define TX4939_CLKCTR_SIO1CKD	0x0080000000000000ULL
+#define TX4939_CLKCTR_VPCCKD	0x0040000000000000ULL
+#define TX4939_CLKCTR_EPCICKD	0x0020000000000000ULL
+#define TX4939_CLKCTR_ETH1CKD	0x0008000000000000ULL
+#define TX4939_CLKCTR_ATA1CKD	0x0004000000000000ULL
+#define TX4939_CLKCTR_BROMCKD	0x0002000000000000ULL
+#define TX4939_CLKCTR_NDCCKD	0x0001000000000000ULL
+#define TX4939_CLKCTR_I2CCKD	0x0000800000000000ULL
+#define TX4939_CLKCTR_ETH0CKD	0x0000400000000000ULL
+#define TX4939_CLKCTR_SPICKD	0x0000200000000000ULL
+#define TX4939_CLKCTR_SRAMCKD	0x0000100000000000ULL
+#define TX4939_CLKCTR_PCI1CKD	0x0000080000000000ULL
+#define TX4939_CLKCTR_DMA1CKD	0x0000040000000000ULL
+#define TX4939_CLKCTR_ACLCKD	0x0000020000000000ULL
+#define TX4939_CLKCTR_ATA0CKD	0x0000010000000000ULL
+#define TX4939_CLKCTR_DMA0CKD	0x0000008000000000ULL
+#define TX4939_CLKCTR_PCICCKD	0x0000004000000000ULL
+#define TX4939_CLKCTR_I2SCKD	0x0000002000000000ULL
+#define TX4939_CLKCTR_TM0CKD	0x0000001000000000ULL
+#define TX4939_CLKCTR_TM1CKD	0x0000000800000000ULL
+#define TX4939_CLKCTR_TM2CKD	0x0000000400000000ULL
+#define TX4939_CLKCTR_SIO0CKD	0x0000000200000000ULL
+#define TX4939_CLKCTR_CYPCKD	0x0000000100000000ULL
+#define TX4939_CLKCTR_IOSRST	0x80000000
+#define TX4939_CLKCTR_SYSRST	0x40000000
+#define TX4939_CLKCTR_TM5RST	0x20000000
+#define TX4939_CLKCTR_TM4RST	0x10000000
+#define TX4939_CLKCTR_TM3RST	0x08000000
+#define TX4939_CLKCTR_CIRRST	0x04000000
+#define TX4939_CLKCTR_SIO3RST	0x02000000
+#define TX4939_CLKCTR_SIO2RST	0x01000000
+#define TX4939_CLKCTR_SIO1RST	0x00800000
+#define TX4939_CLKCTR_VPCRST	0x00400000
+#define TX4939_CLKCTR_EPCIRST	0x00200000
+#define TX4939_CLKCTR_ETH1RST	0x00080000
+#define TX4939_CLKCTR_ATA1RST	0x00040000
+#define TX4939_CLKCTR_BROMRST	0x00020000
+#define TX4939_CLKCTR_NDCRST	0x00010000
+#define TX4939_CLKCTR_I2CRST	0x00008000
+#define TX4939_CLKCTR_ETH0RST	0x00004000
+#define TX4939_CLKCTR_SPIRST	0x00002000
+#define TX4939_CLKCTR_SRAMRST	0x00001000
+#define TX4939_CLKCTR_PCI1RST	0x00000800
+#define TX4939_CLKCTR_DMA1RST	0x00000400
+#define TX4939_CLKCTR_ACLRST	0x00000200
+#define TX4939_CLKCTR_ATA0RST	0x00000100
+#define TX4939_CLKCTR_DMA0RST	0x00000080
+#define TX4939_CLKCTR_PCICRST	0x00000040
+#define TX4939_CLKCTR_I2SRST	0x00000020
+#define TX4939_CLKCTR_TM0RST	0x00000010
+#define TX4939_CLKCTR_TM1RST	0x00000008
+#define TX4939_CLKCTR_TM2RST	0x00000004
+#define TX4939_CLKCTR_SIO0RST	0x00000002
+#define TX4939_CLKCTR_CYPRST	0x00000001
+
+/*
+ * RTC
+ */
+#define TX4939_RTCCTL_ALME	0x00000080
+#define TX4939_RTCCTL_ALMD	0x00000040
+#define TX4939_RTCCTL_BUSY	0x00000020
+
+#define TX4939_RTCCTL_COMMAND	0x00000007
+#define TX4939_RTCCTL_COMMAND_NOP	0x00000000
+#define TX4939_RTCCTL_COMMAND_GETTIME	0x00000001
+#define TX4939_RTCCTL_COMMAND_SETTIME	0x00000002
+#define TX4939_RTCCTL_COMMAND_GETALARM	0x00000003
+#define TX4939_RTCCTL_COMMAND_SETALARM	0x00000004
+
+#define TX4939_RTCTBC_PM	0x00000080
+#define TX4939_RTCTBC_COMP	0x0000007f
+
+#define TX4939_RTC_REG_RAMSIZE	0x00000100
+#define TX4939_RTC_REG_RWBSIZE	0x00000006
+
+/*
+ * CRYPTO
+ */
+#define TX4939_CRYPTO_CSR_SAESO	0x08000000
+#define TX4939_CRYPTO_CSR_SAESI	0x04000000
+#define TX4939_CRYPTO_CSR_SDESO	0x02000000
+#define TX4939_CRYPTO_CSR_SDESI	0x01000000
+#define TX4939_CRYPTO_CSR_INDXBST_MASK	0x00700000
+#define TX4939_CRYPTO_CSR_INDXBST(n)	((n) << 20)
+#define TX4939_CRYPTO_CSR_TOINT	0x00080000
+#define TX4939_CRYPTO_CSR_DCINT	0x00040000
+#define TX4939_CRYPTO_CSR_GBINT	0x00010000
+#define TX4939_CRYPTO_CSR_INDXAST_MASK	0x0000e000
+#define TX4939_CRYPTO_CSR_INDXAST(n)	((n) << 13)
+#define TX4939_CRYPTO_CSR_CSWAP_MASK	0x00001800
+#define TX4939_CRYPTO_CSR_CSWAP_NONE	0x00000000
+#define TX4939_CRYPTO_CSR_CSWAP_IN	0x00000800
+#define TX4939_CRYPTO_CSR_CSWAP_OUT	0x00001000
+#define TX4939_CRYPTO_CSR_CSWAP_BOTH	0x00001800
+#define TX4939_CRYPTO_CSR_CDIV_MASK	0x00000600
+#define TX4939_CRYPTO_CSR_CDIV_DIV2	0x00000000
+#define TX4939_CRYPTO_CSR_CDIV_DIV1	0x00000200
+#define TX4939_CRYPTO_CSR_CDIV_DIV2ALT	0x00000400
+#define TX4939_CRYPTO_CSR_CDIV_DIV1ALT	0x00000600
+#define TX4939_CRYPTO_CSR_PDINT_MASK	0x000000c0
+#define TX4939_CRYPTO_CSR_PDINT_ALL	0x00000000
+#define TX4939_CRYPTO_CSR_PDINT_END	0x00000040
+#define TX4939_CRYPTO_CSR_PDINT_NEXT	0x00000080
+#define TX4939_CRYPTO_CSR_PDINT_NONE	0x000000c0
+#define TX4939_CRYPTO_CSR_GINTE	0x00000008
+#define TX4939_CRYPTO_CSR_RSTD	0x00000004
+#define TX4939_CRYPTO_CSR_RSTC	0x00000002
+#define TX4939_CRYPTO_CSR_ENCR	0x00000001
+
+/* bits for tx4939_crypto_reg.cdr.gen.ctrl */
+#define TX4939_CRYPTO_CTX_ENGINE_MASK	0x00000003
+#define TX4939_CRYPTO_CTX_ENGINE_DES	0x00000000
+#define TX4939_CRYPTO_CTX_ENGINE_AES	0x00000001
+#define TX4939_CRYPTO_CTX_ENGINE_MD5	0x00000002
+#define TX4939_CRYPTO_CTX_ENGINE_SHA1	0x00000003
+#define TX4939_CRYPTO_CTX_TDMS	0x00000010
+#define TX4939_CRYPTO_CTX_CMS	0x00000020
+#define TX4939_CRYPTO_CTX_DMS	0x00000040
+#define TX4939_CRYPTO_CTX_UPDATE	0x00000080
+
+/* bits for tx4939_crypto_desc.ctrl */
+#define TX4939_CRYPTO_DESC_OB_CNT_MASK	0xffe00000
+#define TX4939_CRYPTO_DESC_OB_CNT(cnt)	((cnt) << 21)
+#define TX4939_CRYPTO_DESC_IB_CNT_MASK	0x001ffc00
+#define TX4939_CRYPTO_DESC_IB_CNT(cnt)	((cnt) << 10)
+#define TX4939_CRYPTO_DESC_START	0x00000200
+#define TX4939_CRYPTO_DESC_END	0x00000100
+#define TX4939_CRYPTO_DESC_XOR	0x00000010
+#define TX4939_CRYPTO_DESC_LAST	0x00000008
+#define TX4939_CRYPTO_DESC_ERR_MASK	0x00000006
+#define TX4939_CRYPTO_DESC_ERR_NONE	0x00000000
+#define TX4939_CRYPTO_DESC_ERR_TOUT	0x00000002
+#define TX4939_CRYPTO_DESC_ERR_DIGEST	0x00000004
+#define TX4939_CRYPTO_DESC_OWN	0x00000001
+
+/* bits for tx4939_crypto_desc.index */
+#define TX4939_CRYPTO_DESC_HASH_IDX_MASK	0x00000070
+#define TX4939_CRYPTO_DESC_HASH_IDX(idx)	((idx) << 4)
+#define TX4939_CRYPTO_DESC_ENCRYPT_IDX_MASK	0x00000007
+#define TX4939_CRYPTO_DESC_ENCRYPT_IDX(idx)	((idx) << 0)
+
+#define TX4939_CRYPTO_NR_SET	6
+
+#define TX4939_CRYPTO_RCSR_INTE	0x00000008
+#define TX4939_CRYPTO_RCSR_RST	0x00000004
+#define TX4939_CRYPTO_RCSR_FIN	0x00000002
+#define TX4939_CRYPTO_RCSR_ST	0x00000001
+
+/*
+ * VPC
+ */
+#define TX4939_VPC_CSR_GBINT	0x00010000
+#define TX4939_VPC_CSR_SWAPO	0x00000020
+#define TX4939_VPC_CSR_SWAPI	0x00000010
+#define TX4939_VPC_CSR_GINTE	0x00000008
+#define TX4939_VPC_CSR_RSTD	0x00000004
+#define TX4939_VPC_CSR_RSTVPC	0x00000002
+
+#define TX4939_VPC_CTRLA_VDPSN	0x00000200
+#define TX4939_VPC_CTRLA_PBUSY	0x00000100
+#define TX4939_VPC_CTRLA_DCINT	0x00000080
+#define TX4939_VPC_CTRLA_UOINT	0x00000040
+#define TX4939_VPC_CTRLA_PDINT_MASK	0x00000030
+#define TX4939_VPC_CTRLA_PDINT_ALL	0x00000000
+#define TX4939_VPC_CTRLA_PDINT_NEXT	0x00000010
+#define TX4939_VPC_CTRLA_PDINT_NONE	0x00000030
+#define TX4939_VPC_CTRLA_VDVLDP	0x00000008
+#define TX4939_VPC_CTRLA_VDMODE	0x00000004
+#define TX4939_VPC_CTRLA_VDFOR	0x00000002
+#define TX4939_VPC_CTRLA_ENVPC	0x00000001
+
+/* bits for tx4939_vpc_desc.ctrl1 */
+#define TX4939_VPC_DESC_CTRL1_ERR_MASK	0x00000006
+#define TX4939_VPC_DESC_CTRL1_OWN	0x00000001
+
+#define tx4939_ddrcptr	((struct tx4939_ddrc_reg __iomem *)TX4939_DDRC_REG)
+#define tx4939_ebuscptr		tx4938_ebuscptr
+#define tx4939_ircptr \
+		((struct tx4939_irc_reg __iomem *)TX4939_IRC_REG)
+#define tx4939_pcicptr		tx4938_pcicptr
+#define tx4939_pcic1ptr		tx4938_pcic1ptr
+#define tx4939_ccfgptr \
+		((struct tx4939_ccfg_reg __iomem *)TX4939_CCFG_REG)
+#define tx4939_sramcptr		tx4938_sramcptr
+#define tx4939_rtcptr \
+		((struct tx4939_rtc_reg __iomem *)TX4939_RTC_REG)
+#define tx4939_cryptoptr \
+		((struct tx4939_crypto_reg __iomem *)TX4939_CRYPTO_REG)
+#define tx4939_vpcptr	((struct tx4939_vpc_reg __iomem *)TX4939_VPC_REG)
+
+#define TX4939_REV_MAJ_MIN()	\
+	((__u32)__raw_readq(&tx4939_ccfgptr->crir) & 0x00ff)
+#define TX4939_REV_PCODE()	\
+	((__u32)__raw_readq(&tx4939_ccfgptr->crir) >> 16)
+#define TX4939_CCFG_BCFG()	\
+	((__u32)((__raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_BCFG_MASK) \
+		 >> 32))
+
+#define tx4939_ccfg_clear(bits)	tx4938_ccfg_clear(bits)
+#define tx4939_ccfg_set(bits)	tx4938_ccfg_set(bits)
+#define tx4939_ccfg_change(change, new)	tx4938_ccfg_change(change, new)
+
+#define TX4939_EBUSC_CR(ch)	TX4927_EBUSC_CR(ch)
+#define TX4939_EBUSC_BA(ch)	TX4927_EBUSC_BA(ch)
+#define TX4939_EBUSC_SIZE(ch)	TX4927_EBUSC_SIZE(ch)
+#define TX4939_EBUSC_WIDTH(ch)	\
+	(16 >> ((__u32)(TX4939_EBUSC_CR(ch) >> 20) & 0x1))
+
+/* SCLK0 = MSTCLK * 429/19 * 16/245 / 2  (14.745MHz for MST 20MHz) */
+#define TX4939_SCLK0(mst)	\
+	((((mst) + 245/2) / 245UL * 429 * 16 + 19) / 19 / 2)
+
+void tx4939_wdt_init(void);
+void tx4939_add_memory_regions(void);
+void tx4939_setup(void);
+void tx4939_time_init(unsigned int tmrnr);
+void tx4939_sio_init(unsigned int sclk, unsigned int cts_mask);
+void tx4939_spi_init(int busid);
+void tx4939_ethaddr_init(unsigned char *addr0, unsigned char *addr1);
+int tx4939_report_pciclk(void);
+void tx4939_report_pci1clk(void);
+struct pci_dev;
+int tx4939_pcic1_map_irq(const struct pci_dev *dev, u8 slot);
+int tx4939_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
+void tx4939_setup_pcierr_irq(void);
+void tx4939_irq_init(void);
+int tx4939_irq(void);
+void tx4939_mtd_init(int ch);
+
+#endif /* __ASM_TXX9_TX4939_H */
-- 
1.5.6.3


From anemo@mba.ocn.ne.jp Mon Sep  1 14:24:21 2008
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From:	Atsushi Nemoto <anemo@mba.ocn.ne.jp>
To:	linux-mips@linux-mips.org
Cc:	ralf@linux-mips.org
Subject: [PATCH 5/6] TXx9: Add RBTX4939 board support
Date:	Mon,  1 Sep 2008 22:22:40 +0900
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Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
---
 arch/mips/Makefile               |    8 +-
 arch/mips/txx9/Kconfig           |    8 +
 arch/mips/txx9/generic/setup.c   |    5 +
 arch/mips/txx9/rbtx4939/Makefile |    3 +
 arch/mips/txx9/rbtx4939/irq.c    |   96 ++++++++++++
 arch/mips/txx9/rbtx4939/prom.c   |   17 ++
 arch/mips/txx9/rbtx4939/setup.c  |  306 ++++++++++++++++++++++++++++++++++++++
 include/asm-mips/txx9/boards.h   |    3 +
 include/asm-mips/txx9/rbtx4939.h |  133 +++++++++++++++++
 9 files changed, 573 insertions(+), 6 deletions(-)
 create mode 100644 arch/mips/txx9/rbtx4939/Makefile
 create mode 100644 arch/mips/txx9/rbtx4939/irq.c
 create mode 100644 arch/mips/txx9/rbtx4939/prom.c
 create mode 100644 arch/mips/txx9/rbtx4939/setup.c
 create mode 100644 include/asm-mips/txx9/rbtx4939.h

diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index 9aab51c..87f6722 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -567,15 +567,11 @@ cflags-$(CONFIG_MIKROTIK_RB532) += -Iinclude/asm-mips/mach-rc32434
 load-$(CONFIG_MIKROTIK_RB532)	+= 0xffffffff80101000
 
 #
-# Toshiba RBTX4927 board or
-# Toshiba RBTX4937 board
+# Toshiba RBTX49XX boards
 #
 core-$(CONFIG_TOSHIBA_RBTX4927)	+= arch/mips/txx9/rbtx4927/
-
-#
-# Toshiba RBTX4938 board
-#
 core-$(CONFIG_TOSHIBA_RBTX4938) += arch/mips/txx9/rbtx4938/
+core-$(CONFIG_TOSHIBA_RBTX4939) += arch/mips/txx9/rbtx4939/
 
 cflags-y			+= -Iinclude/asm-mips/mach-generic
 drivers-$(CONFIG_PCI)		+= arch/mips/pci/
diff --git a/arch/mips/txx9/Kconfig b/arch/mips/txx9/Kconfig
index 58691a1..17052db 100644
--- a/arch/mips/txx9/Kconfig
+++ b/arch/mips/txx9/Kconfig
@@ -45,6 +45,14 @@ config TOSHIBA_RBTX4938
 	  This Toshiba board is based on the TX4938 processor. Say Y here to
 	  support this machine type
 
+config TOSHIBA_RBTX4939
+	bool "Toshiba RBTX4939 bobard"
+	depends on MACH_TX49XX
+	select SOC_TX4939
+	help
+	  This Toshiba board is based on the TX4939 processor. Say Y here to
+	  support this machine type
+
 config SOC_TX3927
 	bool
 	select CEVT_TXX9
diff --git a/arch/mips/txx9/generic/setup.c b/arch/mips/txx9/generic/setup.c
index b25b479..8731e16 100644
--- a/arch/mips/txx9/generic/setup.c
+++ b/arch/mips/txx9/generic/setup.c
@@ -371,6 +371,11 @@ static void __init select_board(void)
 		txx9_board_vec = &rbtx4938_vec;
 		break;
 #endif
+#ifdef CONFIG_TOSHIBA_RBTX4939
+	case 0x4939:
+		txx9_board_vec = &rbtx4939_vec;
+		break;
+#endif
 	}
 #endif
 }
diff --git a/arch/mips/txx9/rbtx4939/Makefile b/arch/mips/txx9/rbtx4939/Makefile
new file mode 100644
index 0000000..3232cd0
--- /dev/null
+++ b/arch/mips/txx9/rbtx4939/Makefile
@@ -0,0 +1,3 @@
+obj-y	 += irq.o setup.o prom.o
+
+EXTRA_CFLAGS += -Werror
diff --git a/arch/mips/txx9/rbtx4939/irq.c b/arch/mips/txx9/rbtx4939/irq.c
new file mode 100644
index 0000000..500cc0a
--- /dev/null
+++ b/arch/mips/txx9/rbtx4939/irq.c
@@ -0,0 +1,96 @@
+/*
+ * Toshiba RBTX4939 interrupt routines
+ * Based on linux/arch/mips/txx9/rbtx4938/irq.c,
+ *	    and RBTX49xx patch from CELF patch archive.
+ *
+ * Copyright (C) 2000-2001,2005-2006 Toshiba Corporation
+ * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
+ * terms of the GNU General Public License version 2. This program is
+ * licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <asm/mipsregs.h>
+#include <asm/txx9/rbtx4939.h>
+
+/*
+ * RBTX4939 IOC controller definition
+ */
+
+static void rbtx4939_ioc_irq_unmask(unsigned int irq)
+{
+	int ioc_nr = irq - RBTX4939_IRQ_IOC;
+
+	writeb(readb(rbtx4939_ien_addr) | (1 << ioc_nr), rbtx4939_ien_addr);
+}
+
+static void rbtx4939_ioc_irq_mask(unsigned int irq)
+{
+	int ioc_nr = irq - RBTX4939_IRQ_IOC;
+
+	writeb(readb(rbtx4939_ien_addr) & ~(1 << ioc_nr), rbtx4939_ien_addr);
+	mmiowb();
+}
+
+static struct irq_chip rbtx4939_ioc_irq_chip = {
+	.name		= "IOC",
+	.ack		= rbtx4939_ioc_irq_mask,
+	.mask		= rbtx4939_ioc_irq_mask,
+	.mask_ack	= rbtx4939_ioc_irq_mask,
+	.unmask		= rbtx4939_ioc_irq_unmask,
+};
+
+
+static inline int rbtx4939_ioc_irqroute(void)
+{
+	unsigned char istat = readb(rbtx4939_ifac2_addr);
+
+	if (unlikely(istat == 0))
+		return -1;
+	return RBTX4939_IRQ_IOC + __fls8(istat);
+}
+
+static int rbtx4939_irq_dispatch(int pending)
+{
+	int irq;
+
+	if (pending & CAUSEF_IP7)
+		return MIPS_CPU_IRQ_BASE + 7;
+	irq = tx4939_irq();
+	if (likely(irq >= 0)) {
+		/* redirect IOC interrupts */
+		switch (irq) {
+		case RBTX4939_IRQ_IOCINT:
+			irq = rbtx4939_ioc_irqroute();
+			break;
+		}
+	} else if (pending & CAUSEF_IP0)
+		irq = MIPS_CPU_IRQ_BASE + 0;
+	else if (pending & CAUSEF_IP1)
+		irq = MIPS_CPU_IRQ_BASE + 1;
+	else
+		irq = -1;
+	return irq;
+}
+
+void __init rbtx4939_irq_setup(void)
+{
+	int i;
+
+	/* mask all IOC interrupts */
+	writeb(0, rbtx4939_ien_addr);
+
+	/* clear SoftInt interrupts */
+	writeb(0, rbtx4939_softint_addr);
+
+	txx9_irq_dispatch = rbtx4939_irq_dispatch;
+
+	tx4939_irq_init();
+	for (i = RBTX4939_IRQ_IOC;
+	     i < RBTX4939_IRQ_IOC + RBTX4939_NR_IRQ_IOC; i++)
+		set_irq_chip_and_handler(i, &rbtx4939_ioc_irq_chip,
+					 handle_level_irq);
+
+	set_irq_chained_handler(RBTX4939_IRQ_IOCINT, handle_simple_irq);
+}
diff --git a/arch/mips/txx9/rbtx4939/prom.c b/arch/mips/txx9/rbtx4939/prom.c
new file mode 100644
index 0000000..bd277ec
--- /dev/null
+++ b/arch/mips/txx9/rbtx4939/prom.c
@@ -0,0 +1,17 @@
+/*
+ * rbtx4939 specific prom routines
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#include <linux/init.h>
+#include <asm/txx9/generic.h>
+#include <asm/txx9/rbtx4939.h>
+
+void __init rbtx4939_prom_init(void)
+{
+	tx4939_add_memory_regions();
+	txx9_sio_putchar_init(TX4939_SIO_REG(0) & 0xfffffffffULL);
+}
diff --git a/arch/mips/txx9/rbtx4939/setup.c b/arch/mips/txx9/rbtx4939/setup.c
new file mode 100644
index 0000000..277864d
--- /dev/null
+++ b/arch/mips/txx9/rbtx4939/setup.c
@@ -0,0 +1,306 @@
+/*
+ * Toshiba RBTX4939 setup routines.
+ * Based on linux/arch/mips/txx9/rbtx4938/setup.c,
+ *	    and RBTX49xx patch from CELF patch archive.
+ *
+ * Copyright (C) 2000-2001,2005-2007 Toshiba Corporation
+ * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
+ * terms of the GNU General Public License version 2. This program is
+ * licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/platform_device.h>
+#include <linux/leds.h>
+#include <asm/reboot.h>
+#include <asm/txx9/generic.h>
+#include <asm/txx9/pci.h>
+#include <asm/txx9/rbtx4939.h>
+
+static void rbtx4939_machine_restart(char *command)
+{
+	local_irq_disable();
+	writeb(1, rbtx4939_reseten_addr);
+	writeb(1, rbtx4939_softreset_addr);
+	while (1)
+		;
+}
+
+static void __init rbtx4939_time_init(void)
+{
+	tx4939_time_init(0);
+}
+
+static void __init rbtx4939_pci_setup(void)
+{
+#ifdef CONFIG_PCI
+	int extarb = !(__raw_readq(&tx4939_ccfgptr->ccfg) & TX4939_CCFG_PCIARB);
+	struct pci_controller *c = &txx9_primary_pcic;
+
+	register_pci_controller(c);
+
+	tx4939_report_pciclk();
+	tx4927_pcic_setup(tx4939_pcicptr, c, extarb);
+	if (!(__raw_readq(&tx4939_ccfgptr->pcfg) & TX4939_PCFG_ATA1MODE) &&
+	    (__raw_readq(&tx4939_ccfgptr->pcfg) &
+	     (TX4939_PCFG_ET0MODE | TX4939_PCFG_ET1MODE))) {
+		tx4939_report_pci1clk();
+
+		/* mem:64K(max), io:64K(max) (enough for ETH0,ETH1) */
+		c = txx9_alloc_pci_controller(NULL, 0, 0x10000, 0, 0x10000);
+		register_pci_controller(c);
+		tx4927_pcic_setup(tx4939_pcic1ptr, c, 0);
+	}
+
+	tx4939_setup_pcierr_irq();
+#endif /* CONFIG_PCI */
+}
+
+static unsigned long long default_ebccr[] __initdata = {
+	0x01c0000000007608ULL, /* 64M ROM */
+	0x017f000000007049ULL, /* 1M IOC */
+	0x0180000000408608ULL, /* ISA */
+	0,
+};
+
+static void __init rbtx4939_ebusc_setup(void)
+{
+	int i;
+	unsigned int sp;
+
+	/* use user-configured speed */
+	sp = TX4939_EBUSC_CR(0) & 0x30;
+	default_ebccr[0] |= sp;
+	default_ebccr[1] |= sp;
+	default_ebccr[2] |= sp;
+	/* initialise by myself */
+	for (i = 0; i < ARRAY_SIZE(default_ebccr); i++) {
+		if (default_ebccr[i])
+			____raw_writeq(default_ebccr[i],
+				       &tx4939_ebuscptr->cr[i]);
+		else
+			____raw_writeq(____raw_readq(&tx4939_ebuscptr->cr[i])
+				       & ~8,
+				       &tx4939_ebuscptr->cr[i]);
+	}
+}
+
+static void __init rbtx4939_update_ioc_pen(void)
+{
+	__u64 pcfg = ____raw_readq(&tx4939_ccfgptr->pcfg);
+	__u64 ccfg = ____raw_readq(&tx4939_ccfgptr->ccfg);
+	__u8 pe1 = readb(rbtx4939_pe1_addr);
+	__u8 pe2 = readb(rbtx4939_pe2_addr);
+	__u8 pe3 = readb(rbtx4939_pe3_addr);
+	if (pcfg & TX4939_PCFG_ATA0MODE)
+		pe1 |= RBTX4939_PE1_ATA(0);
+	else
+		pe1 &= ~RBTX4939_PE1_ATA(0);
+	if (pcfg & TX4939_PCFG_ATA1MODE) {
+		pe1 |= RBTX4939_PE1_ATA(1);
+		pe1 &= ~(RBTX4939_PE1_RMII(0) | RBTX4939_PE1_RMII(1));
+	} else {
+		pe1 &= ~RBTX4939_PE1_ATA(1);
+		if (pcfg & TX4939_PCFG_ET0MODE)
+			pe1 |= RBTX4939_PE1_RMII(0);
+		else
+			pe1 &= ~RBTX4939_PE1_RMII(0);
+		if (pcfg & TX4939_PCFG_ET1MODE)
+			pe1 |= RBTX4939_PE1_RMII(1);
+		else
+			pe1 &= ~RBTX4939_PE1_RMII(1);
+	}
+	if (ccfg & TX4939_CCFG_PTSEL)
+		pe3 &= ~(RBTX4939_PE3_VP | RBTX4939_PE3_VP_P |
+			 RBTX4939_PE3_VP_S);
+	else {
+		__u64 vmode = pcfg &
+			(TX4939_PCFG_VSSMODE | TX4939_PCFG_VPSMODE);
+		if (vmode == 0)
+			pe3 &= ~(RBTX4939_PE3_VP | RBTX4939_PE3_VP_P |
+				 RBTX4939_PE3_VP_S);
+		else if (vmode == TX4939_PCFG_VPSMODE) {
+			pe3 |= RBTX4939_PE3_VP_P;
+			pe3 &= ~(RBTX4939_PE3_VP | RBTX4939_PE3_VP_S);
+		} else if (vmode == TX4939_PCFG_VSSMODE) {
+			pe3 |= RBTX4939_PE3_VP | RBTX4939_PE3_VP_S;
+			pe3 &= ~RBTX4939_PE3_VP_P;
+		} else {
+			pe3 |= RBTX4939_PE3_VP | RBTX4939_PE3_VP_P;
+			pe3 &= ~RBTX4939_PE3_VP_S;
+		}
+	}
+	if (pcfg & TX4939_PCFG_SPIMODE) {
+		if (pcfg & TX4939_PCFG_SIO2MODE_GPIO)
+			pe2 &= ~(RBTX4939_PE2_SIO2 | RBTX4939_PE2_SIO0);
+		else {
+			if (pcfg & TX4939_PCFG_SIO2MODE_SIO2) {
+				pe2 |= RBTX4939_PE2_SIO2;
+				pe2 &= ~RBTX4939_PE2_SIO0;
+			} else {
+				pe2 |= RBTX4939_PE2_SIO0;
+				pe2 &= ~RBTX4939_PE2_SIO2;
+			}
+		}
+		if (pcfg & TX4939_PCFG_SIO3MODE)
+			pe2 |= RBTX4939_PE2_SIO3;
+		else
+			pe2 &= ~RBTX4939_PE2_SIO3;
+		pe2 &= ~RBTX4939_PE2_SPI;
+	} else {
+		pe2 |= RBTX4939_PE2_SPI;
+		pe2 &= ~(RBTX4939_PE2_SIO3 | RBTX4939_PE2_SIO2 |
+			 RBTX4939_PE2_SIO0);
+	}
+	if ((pcfg & TX4939_PCFG_I2SMODE_MASK) == TX4939_PCFG_I2SMODE_GPIO)
+		pe2 |= RBTX4939_PE2_GPIO;
+	else
+		pe2 &= ~RBTX4939_PE2_GPIO;
+	writeb(pe1, rbtx4939_pe1_addr);
+	writeb(pe2, rbtx4939_pe2_addr);
+	writeb(pe3, rbtx4939_pe3_addr);
+}
+
+#define RBTX4939_MAX_7SEGLEDS	8
+
+#if defined(CONFIG_LEDS_CLASS) || defined(CONFIG_LEDS_CLASS_MODULE)
+static u8 led_val[RBTX4939_MAX_7SEGLEDS];
+struct rbtx4939_led_data {
+	struct led_classdev cdev;
+	char name[32];
+	unsigned int num;
+};
+
+/* Use "dot" in 7seg LEDs */
+static void rbtx4939_led_brightness_set(struct led_classdev *led_cdev,
+					enum led_brightness value)
+{
+	struct rbtx4939_led_data *led_dat =
+		container_of(led_cdev, struct rbtx4939_led_data, cdev);
+	unsigned int num = led_dat->num;
+	unsigned long flags;
+
+	local_irq_save(flags);
+	led_val[num] = (led_val[num] & 0x7f) | (value ? 0x80 : 0);
+	writeb(led_val[num], rbtx4939_7seg_addr(num / 4, num % 4));
+	local_irq_restore(flags);
+}
+
+static int __init rbtx4939_led_probe(struct platform_device *pdev)
+{
+	struct rbtx4939_led_data *leds_data;
+	int i;
+	static char *default_triggers[] __initdata = {
+		"heartbeat",
+		"ide-disk",
+		"nand-disk",
+	};
+
+	leds_data = kzalloc(sizeof(*leds_data) * RBTX4939_MAX_7SEGLEDS,
+			    GFP_KERNEL);
+	if (!leds_data)
+		return -ENOMEM;
+	for (i = 0; i < RBTX4939_MAX_7SEGLEDS; i++) {
+		int rc;
+		struct rbtx4939_led_data *led_dat = &leds_data[i];
+
+		led_dat->num = i;
+		led_dat->cdev.brightness_set = rbtx4939_led_brightness_set;
+		sprintf(led_dat->name, "rbtx4939:amber:%u", i);
+		led_dat->cdev.name = led_dat->name;
+		if (i < ARRAY_SIZE(default_triggers))
+			led_dat->cdev.default_trigger = default_triggers[i];
+		rc = led_classdev_register(&pdev->dev, &led_dat->cdev);
+		if (rc < 0)
+			return rc;
+		led_dat->cdev.brightness_set(&led_dat->cdev, 0);
+	}
+	return 0;
+
+}
+
+static struct platform_driver rbtx4939_led_driver = {
+	.driver  = {
+		.name = "rbtx4939-led",
+		.owner = THIS_MODULE,
+	},
+};
+
+static void __init rbtx4939_led_setup(void)
+{
+	platform_device_register_simple("rbtx4939-led", -1, NULL, 0);
+	platform_driver_probe(&rbtx4939_led_driver, rbtx4939_led_probe);
+}
+#else
+static inline void rbtx4939_led_setup(void)
+{
+}
+#endif
+
+static void __init rbtx4939_arch_init(void)
+{
+	rbtx4939_pci_setup();
+}
+
+static void __init rbtx4939_device_init(void)
+{
+#if defined(CONFIG_TC35815) || defined(CONFIG_TC35815_MODULE)
+	int i, j;
+	unsigned char ethaddr[2][6];
+	for (i = 0; i < 2; i++) {
+		unsigned long area = CKSEG1 + 0x1fff0000 + (i * 0x10);
+		if (readb(rbtx4939_bdipsw_addr) & 8) {
+			u16 buf[3];
+			area -= 0x03000000;
+			for (j = 0; j < 3; j++)
+				buf[j] = le16_to_cpup((u16 *)(area + j * 2));
+			memcpy(ethaddr[i], buf, 6);
+		} else
+			memcpy(ethaddr[i], (void *)area, 6);
+	}
+	tx4939_ethaddr_init(ethaddr[0], ethaddr[1]);
+#endif
+	rbtx4939_led_setup();
+	tx4939_wdt_init();
+}
+
+static void __init rbtx4939_setup(void)
+{
+	rbtx4939_ebusc_setup();
+	/* always enable ATA0 */
+	txx9_set64(&tx4939_ccfgptr->pcfg, TX4939_PCFG_ATA0MODE);
+	rbtx4939_update_ioc_pen();
+	if (txx9_master_clock == 0)
+		txx9_master_clock = 20000000;
+	tx4939_setup();
+
+	_machine_restart = rbtx4939_machine_restart;
+
+	pr_info("RBTX4939 (Rev %02x) --- FPGA(Rev %02x) DIPSW:%02x,%02x\n",
+		readb(rbtx4939_board_rev_addr), readb(rbtx4939_ioc_rev_addr),
+		readb(rbtx4939_udipsw_addr), readb(rbtx4939_bdipsw_addr));
+
+#ifdef CONFIG_PCI
+	txx9_alloc_pci_controller(&txx9_primary_pcic, 0, 0, 0, 0);
+	txx9_board_pcibios_setup = tx4927_pcibios_setup;
+#else
+	set_io_port_base(RBTX4939_ETHER_BASE);
+#endif
+
+	tx4939_sio_init(TX4939_SCLK0(txx9_master_clock), 0);
+}
+
+struct txx9_board_vec rbtx4939_vec __initdata = {
+	.system = "Tothiba RBTX4939",
+	.prom_init = rbtx4939_prom_init,
+	.mem_setup = rbtx4939_setup,
+	.irq_setup = rbtx4939_irq_setup,
+	.time_init = rbtx4939_time_init,
+	.device_init = rbtx4939_device_init,
+	.arch_init = rbtx4939_arch_init,
+#ifdef CONFIG_PCI
+	.pci_map_irq = tx4939_pci_map_irq,
+#endif
+};
diff --git a/include/asm-mips/txx9/boards.h b/include/asm-mips/txx9/boards.h
index 4abc814..cbe9476 100644
--- a/include/asm-mips/txx9/boards.h
+++ b/include/asm-mips/txx9/boards.h
@@ -8,3 +8,6 @@ BOARD_VEC(rbtx4937_vec)
 #ifdef CONFIG_TOSHIBA_RBTX4938
 BOARD_VEC(rbtx4938_vec)
 #endif
+#ifdef CONFIG_TOSHIBA_RBTX4939
+BOARD_VEC(rbtx4939_vec)
+#endif
diff --git a/include/asm-mips/txx9/rbtx4939.h b/include/asm-mips/txx9/rbtx4939.h
new file mode 100644
index 0000000..1acf428
--- /dev/null
+++ b/include/asm-mips/txx9/rbtx4939.h
@@ -0,0 +1,133 @@
+/*
+ * Definitions for RBTX4939
+ *
+ * (C) Copyright TOSHIBA CORPORATION 2005-2006
+ * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
+ * terms of the GNU General Public License version 2. This program is
+ * licensed "as is" without any warranty of any kind, whether express
+ * or implied.
+ */
+#ifndef __ASM_TXX9_RBTX4939_H
+#define __ASM_TXX9_RBTX4939_H
+
+#include <asm/addrspace.h>
+#include <asm/txx9irq.h>
+#include <asm/txx9/generic.h>
+#include <asm/txx9/tx4939.h>
+
+/* Address map */
+#define RBTX4939_IOC_REG_ADDR	(IO_BASE + TXX9_CE(1) + 0x00000000)
+#define RBTX4939_BOARD_REV_ADDR	(IO_BASE + TXX9_CE(1) + 0x00000000)
+#define RBTX4939_IOC_REV_ADDR	(IO_BASE + TXX9_CE(1) + 0x00000002)
+#define RBTX4939_CONFIG1_ADDR	(IO_BASE + TXX9_CE(1) + 0x00000004)
+#define RBTX4939_CONFIG2_ADDR	(IO_BASE + TXX9_CE(1) + 0x00000006)
+#define RBTX4939_CONFIG3_ADDR	(IO_BASE + TXX9_CE(1) + 0x00000008)
+#define RBTX4939_CONFIG4_ADDR	(IO_BASE + TXX9_CE(1) + 0x0000000a)
+#define RBTX4939_USTAT_ADDR	(IO_BASE + TXX9_CE(1) + 0x00001000)
+#define RBTX4939_UDIPSW_ADDR	(IO_BASE + TXX9_CE(1) + 0x00001002)
+#define RBTX4939_BDIPSW_ADDR	(IO_BASE + TXX9_CE(1) + 0x00001004)
+#define RBTX4939_IEN_ADDR	(IO_BASE + TXX9_CE(1) + 0x00002000)
+#define RBTX4939_IPOL_ADDR	(IO_BASE + TXX9_CE(1) + 0x00002002)
+#define RBTX4939_IFAC1_ADDR	(IO_BASE + TXX9_CE(1) + 0x00002004)
+#define RBTX4939_IFAC2_ADDR	(IO_BASE + TXX9_CE(1) + 0x00002006)
+#define RBTX4939_SOFTINT_ADDR	(IO_BASE + TXX9_CE(1) + 0x00003000)
+#define RBTX4939_ISASTAT_ADDR	(IO_BASE + TXX9_CE(1) + 0x00004000)
+#define RBTX4939_PCISTAT_ADDR	(IO_BASE + TXX9_CE(1) + 0x00004002)
+#define RBTX4939_ROME_ADDR	(IO_BASE + TXX9_CE(1) + 0x00004004)
+#define RBTX4939_SPICS_ADDR	(IO_BASE + TXX9_CE(1) + 0x00004006)
+#define RBTX4939_AUDI_ADDR	(IO_BASE + TXX9_CE(1) + 0x00004008)
+#define RBTX4939_ISAGPIO_ADDR	(IO_BASE + TXX9_CE(1) + 0x0000400a)
+#define RBTX4939_PE1_ADDR	(IO_BASE + TXX9_CE(1) + 0x00005000)
+#define RBTX4939_PE2_ADDR	(IO_BASE + TXX9_CE(1) + 0x00005002)
+#define RBTX4939_PE3_ADDR	(IO_BASE + TXX9_CE(1) + 0x00005004)
+#define RBTX4939_VP_ADDR	(IO_BASE + TXX9_CE(1) + 0x00005006)
+#define RBTX4939_VPRESET_ADDR	(IO_BASE + TXX9_CE(1) + 0x00005008)
+#define RBTX4939_VPSOUT_ADDR	(IO_BASE + TXX9_CE(1) + 0x0000500a)
+#define RBTX4939_VPSIN_ADDR	(IO_BASE + TXX9_CE(1) + 0x0000500c)
+#define RBTX4939_7SEG_ADDR(s, ch)	\
+	(IO_BASE + TXX9_CE(1) + 0x00006000 + (s) * 16 + ((ch) & 3) * 2)
+#define RBTX4939_SOFTRESET_ADDR	(IO_BASE + TXX9_CE(1) + 0x00007000)
+#define RBTX4939_RESETEN_ADDR	(IO_BASE + TXX9_CE(1) + 0x00007002)
+#define RBTX4939_RESETSTAT_ADDR	(IO_BASE + TXX9_CE(1) + 0x00007004)
+#define RBTX4939_ETHER_BASE	(IO_BASE + TXX9_CE(1) + 0x00020000)
+
+/* Ethernet port address */
+#define RBTX4939_ETHER_ADDR	(RBTX4939_ETHER_BASE + 0x300)
+
+/* bits for IEN/IPOL/IFAC */
+#define RBTX4938_INTB_ISA0	0
+#define RBTX4938_INTB_ISA11	1
+#define RBTX4938_INTB_ISA12	2
+#define RBTX4938_INTB_ISA15	3
+#define RBTX4938_INTB_I2S	4
+#define RBTX4938_INTB_SW	5
+#define RBTX4938_INTF_ISA0	(1 << RBTX4938_INTB_ISA0)
+#define RBTX4938_INTF_ISA11	(1 << RBTX4938_INTB_ISA11)
+#define RBTX4938_INTF_ISA12	(1 << RBTX4938_INTB_ISA12)
+#define RBTX4938_INTF_ISA15	(1 << RBTX4938_INTB_ISA15)
+#define RBTX4938_INTF_I2S	(1 << RBTX4938_INTB_I2S)
+#define RBTX4938_INTF_SW	(1 << RBTX4938_INTB_SW)
+
+/* bits for PE1,PE2,PE3 */
+#define RBTX4939_PE1_ATA(ch)	(0x01 << (ch))
+#define RBTX4939_PE1_RMII(ch)	(0x04 << (ch))
+#define RBTX4939_PE2_SIO0	0x01
+#define RBTX4939_PE2_SIO2	0x02
+#define RBTX4939_PE2_SIO3	0x04
+#define RBTX4939_PE2_CIR	0x08
+#define RBTX4939_PE2_SPI	0x10
+#define RBTX4939_PE2_GPIO	0x20
+#define RBTX4939_PE3_VP	0x01
+#define RBTX4939_PE3_VP_P	0x02
+#define RBTX4939_PE3_VP_S	0x04
+
+#define rbtx4939_board_rev_addr	((u8 __iomem *)RBTX4939_BOARD_REV_ADDR)
+#define rbtx4939_ioc_rev_addr	((u8 __iomem *)RBTX4939_IOC_REV_ADDR)
+#define rbtx4939_config1_addr	((u8 __iomem *)RBTX4939_CONFIG1_ADDR)
+#define rbtx4939_config2_addr	((u8 __iomem *)RBTX4939_CONFIG2_ADDR)
+#define rbtx4939_config3_addr	((u8 __iomem *)RBTX4939_CONFIG3_ADDR)
+#define rbtx4939_config4_addr	((u8 __iomem *)RBTX4939_CONFIG4_ADDR)
+#define rbtx4939_ustat_addr	((u8 __iomem *)RBTX4939_USTAT_ADDR)
+#define rbtx4939_udipsw_addr	((u8 __iomem *)RBTX4939_UDIPSW_ADDR)
+#define rbtx4939_bdipsw_addr	((u8 __iomem *)RBTX4939_BDIPSW_ADDR)
+#define rbtx4939_ien_addr	((u8 __iomem *)RBTX4939_IEN_ADDR)
+#define rbtx4939_ipol_addr	((u8 __iomem *)RBTX4939_IPOL_ADDR)
+#define rbtx4939_ifac1_addr	((u8 __iomem *)RBTX4939_IFAC1_ADDR)
+#define rbtx4939_ifac2_addr	((u8 __iomem *)RBTX4939_IFAC2_ADDR)
+#define rbtx4939_softint_addr	((u8 __iomem *)RBTX4939_SOFTINT_ADDR)
+#define rbtx4939_isastat_addr	((u8 __iomem *)RBTX4939_ISASTAT_ADDR)
+#define rbtx4939_pcistat_addr	((u8 __iomem *)RBTX4939_PCISTAT_ADDR)
+#define rbtx4939_rome_addr	((u8 __iomem *)RBTX4939_ROME_ADDR)
+#define rbtx4939_spics_addr	((u8 __iomem *)RBTX4939_SPICS_ADDR)
+#define rbtx4939_audi_addr	((u8 __iomem *)RBTX4939_AUDI_ADDR)
+#define rbtx4939_isagpio_addr	((u8 __iomem *)RBTX4939_ISAGPIO_ADDR)
+#define rbtx4939_pe1_addr	((u8 __iomem *)RBTX4939_PE1_ADDR)
+#define rbtx4939_pe2_addr	((u8 __iomem *)RBTX4939_PE2_ADDR)
+#define rbtx4939_pe3_addr	((u8 __iomem *)RBTX4939_PE3_ADDR)
+#define rbtx4939_vp_addr	((u8 __iomem *)RBTX4939_VP_ADDR)
+#define rbtx4939_vpreset_addr	((u8 __iomem *)RBTX4939_VPRESET_ADDR)
+#define rbtx4939_vpsout_addr	((u8 __iomem *)RBTX4939_VPSOUT_ADDR)
+#define rbtx4939_vpsin_addr	((u8 __iomem *)RBTX4939_VPSIN_ADDR)
+#define rbtx4939_7seg_addr(s, ch) \
+				((u8 __iomem *)RBTX4939_7SEG_ADDR(s, ch))
+#define rbtx4939_softreset_addr	((u8 __iomem *)RBTX4939_SOFTRESET_ADDR)
+#define rbtx4939_reseten_addr	((u8 __iomem *)RBTX4939_RESETEN_ADDR)
+#define rbtx4939_resetstat_addr	((u8 __iomem *)RBTX4939_RESETSTAT_ADDR)
+
+/*
+ * IRQ mappings
+ */
+#define RBTX4939_NR_IRQ_IOC	8
+
+#define RBTX4939_IRQ_IOC	(TXX9_IRQ_BASE + TX4939_NUM_IR)
+#define RBTX4939_IRQ_END	(RBTX4939_IRQ_IOC + RBTX4939_NR_IRQ_IOC)
+
+/* IOC (ISA, etc) */
+#define RBTX4939_IRQ_IOCINT	(TXX9_IRQ_BASE + TX4939_IR_INT(0))
+/* Onboard 10M Ether */
+#define RBTX4939_IRQ_ETHER	(TXX9_IRQ_BASE + TX4939_IR_INT(1))
+
+void rbtx4939_prom_init(void);
+void rbtx4939_irq_setup(void);
+
+#endif /* __ASM_TXX9_RBTX4939_H */
-- 
1.5.6.3


From anemo@mba.ocn.ne.jp Mon Sep  1 14:24:41 2008
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From:	Atsushi Nemoto <anemo@mba.ocn.ne.jp>
To:	linux-mips@linux-mips.org
Cc:	ralf@linux-mips.org
Subject: [PATCH 6/6] TXx9: Implement prom_free_prom_memory
Date:	Mon,  1 Sep 2008 22:22:41 +0900
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Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
---
 arch/mips/txx9/generic/setup.c |    6 ++++++
 1 files changed, 6 insertions(+), 0 deletions(-)

diff --git a/arch/mips/txx9/generic/setup.c b/arch/mips/txx9/generic/setup.c
index 8731e16..419f574 100644
--- a/arch/mips/txx9/generic/setup.c
+++ b/arch/mips/txx9/generic/setup.c
@@ -28,6 +28,7 @@
 #include <asm/time.h>
 #include <asm/reboot.h>
 #include <asm/r4kcache.h>
+#include <asm/sections.h>
 #include <asm/txx9/generic.h>
 #include <asm/txx9/pci.h>
 #include <asm/txx9tmr.h>
@@ -393,6 +394,11 @@ void __init prom_init(void)
 
 void __init prom_free_prom_memory(void)
 {
+	unsigned long saddr = PAGE_SIZE;
+	unsigned long eaddr = __pa_symbol(&_text);
+
+	if (saddr < eaddr)
+		free_init_pages("prom memory", saddr, eaddr);
 }
 
 const char *get_system_type(void)
-- 
1.5.6.3


From ralf@linux-mips.org Mon Sep  1 15:25:15 2008
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Subject: Re: [PATCH 1/6] TXx9: stop_unused_modules
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On Mon, Sep 01, 2008 at 10:22:36PM +0900, Atsushi Nemoto wrote:

> TXx9 SoCs have pin multiplex.  Stop some controller modules which can
> not be used due to pin configurations.

Whole series queued for 2.6.28.

  Ralf

From Geert.Uytterhoeven@sonycom.com Mon Sep  1 17:28:31 2008
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	Hi Nemoto-san,

On Mon, 1 Sep 2008, Atsushi Nemoto wrote:
> Add leds-gpio platform device for controlling LEDs connected to IOC on
> RBTX49XX and JMR3927 board.

Thanks, LED[1-3] on my RBTX4927 work fine now!

If I'm correct LED4 and LED5 are not connected to the IOC, but to the
PIO of the TX4927. Do you have a driver for those LEDs, too?
Perhaps I just missed it, I only applied this single patch.

With kind regards,

Geert Uytterhoeven
Software Architect

Sony Techsoft Centre Europe
The Corporate Village · Da Vincilaan 7-D1 · B-1935 Zaventem · Belgium

Phone:    +32 (0)2 700 8453
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From ralf@linux-mips.org Tue Sep  2 11:19:37 2008
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Subject: Re: [2.6 patch] remove drivers/pcmcia/au1000_pb1x00.c
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On Sun, Aug 31, 2008 at 07:09:52PM +0300, Adrian Bunk wrote:

> drivers/pcmcia/au1000_pb1x00.c was added in 2003 but #include's 
> linux/tqueue.h that was removed in 2002.
> 
> This file clearly never compiled after it was added to the tree.
> 
> Signed-off-by: Adrian Bunk <bunk@kernel.org>

Acked-by: Ralf Baechle <ralf@linux-mips.org>

  Ralf

From anemo@mba.ocn.ne.jp Tue Sep  2 14:44:40 2008
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From:	Atsushi Nemoto <anemo@mba.ocn.ne.jp>
To:	linux-mips@linux-mips.org
Cc:	ralf@linux-mips.org
Subject: [PATCH] RBTX4927: Add gpio-led support
Date:	Tue,  2 Sep 2008 22:44:38 +0900
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Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
---
 arch/mips/txx9/rbtx4927/setup.c |   25 +++++++++++++++++++++----
 1 files changed, 21 insertions(+), 4 deletions(-)

diff --git a/arch/mips/txx9/rbtx4927/setup.c b/arch/mips/txx9/rbtx4927/setup.c
index 4a74423..01129a9 100644
--- a/arch/mips/txx9/rbtx4927/setup.c
+++ b/arch/mips/txx9/rbtx4927/setup.c
@@ -49,6 +49,7 @@
 #include <linux/platform_device.h>
 #include <linux/delay.h>
 #include <linux/gpio.h>
+#include <linux/leds.h>
 #include <asm/io.h>
 #include <asm/reboot.h>
 #include <asm/txx9/generic.h>
@@ -210,10 +211,6 @@ static void __init rbtx4927_mem_setup(void)
 	/* TX4927-SIO DTR on (PIO[15]) */
 	gpio_request(15, "sio-dtr");
 	gpio_direction_output(15, 1);
-	gpio_request(0, "led");
-	gpio_direction_output(0, 1);
-	gpio_request(1, "led");
-	gpio_direction_output(1, 1);
 
 	tx4927_sio_init(0, 0);
 #ifdef CONFIG_SERIAL_TXX9_CONSOLE
@@ -315,6 +312,25 @@ static void __init rbtx4927_mtd_init(void)
 		tx4927_mtd_init(i);
 }
 
+static void __init rbtx4927_gpioled_init(void)
+{
+	static struct gpio_led leds[] = {
+		{ .name = "gpioled:green:0", .gpio = 0, .active_low = 1, },
+		{ .name = "gpioled:green:1", .gpio = 1, .active_low = 1, },
+	};
+	static struct gpio_led_platform_data pdata = {
+		.num_leds = ARRAY_SIZE(leds),
+		.leds = leds,
+	};
+	struct platform_device *pdev = platform_device_alloc("leds-gpio", 0);
+
+	if (!pdev)
+		return;
+	pdev->dev.platform_data = &pdata;
+	if (platform_device_add(pdev))
+		platform_device_put(pdev);
+}
+
 static void __init rbtx4927_device_init(void)
 {
 	toshiba_rbtx4927_rtc_init();
@@ -322,6 +338,7 @@ static void __init rbtx4927_device_init(void)
 	tx4927_wdt_init();
 	rbtx4927_mtd_init();
 	txx9_iocled_init(RBTX4927_LED_ADDR - IO_BASE, -1, 3, 1, "green", NULL);
+	rbtx4927_gpioled_init();
 }
 
 struct txx9_board_vec rbtx4927_vec __initdata = {
-- 
1.5.6.3


From anemo@mba.ocn.ne.jp Tue Sep  2 14:45:06 2008
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Subject: Re: [PATCH 3/6] TXx9: IOC LED support
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On Mon, 1 Sep 2008 18:28:29 +0200 (CEST), Geert Uytterhoeven <Geert.Uytterhoeven@sonycom.com> wrote:
> If I'm correct LED4 and LED5 are not connected to the IOC, but to the
> PIO of the TX4927. Do you have a driver for those LEDs, too?
> Perhaps I just missed it, I only applied this single patch.

Done ;)

Note that the patch depends on some patches in linux-queue tree, but
it would be simple enough so that you can apply it manually.

---
Atsushi Nemoto

From Geert.Uytterhoeven@sonycom.com Tue Sep  2 15:18:43 2008
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	Hi Nemoto-san,

On Tue, 2 Sep 2008, Atsushi Nemoto wrote:
> On Mon, 1 Sep 2008 18:28:29 +0200 (CEST), Geert Uytterhoeven <Geert.Uytterhoeven@sonycom.com> wrote:
> > If I'm correct LED4 and LED5 are not connected to the IOC, but to the
> > PIO of the TX4927. Do you have a driver for those LEDs, too?
> > Perhaps I just missed it, I only applied this single patch.
> 
> Done ;)
> 
> Note that the patch depends on some patches in linux-queue tree, but
> it would be simple enough so that you can apply it manually.

Thanks a lot! It works fine.

With kind regards,

Geert Uytterhoeven
Software Architect

Sony Techsoft Centre Europe
The Corporate Village · Da Vincilaan 7-D1 · B-1935 Zaventem · Belgium

Phone:    +32 (0)2 700 8453
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---584349381-946661120-1220365117=:3986--

From sshtylyov@ru.mvista.com Wed Sep  3 11:04:48 2008
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Subject: Re: [PATCH 4/6] TXx9: Add TX4939 SoC support
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Hello.

Atsushi Nemoto wrote:

> Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
>   

   At last. Cool. I know this SoC has IDE controller. Planning on 
submitting a driver?

WBR, Sergei



From sshtylyov@ru.mvista.com Wed Sep  3 11:13:33 2008
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Subject: Re: [PATCH 2/6] TXx9: Microoptimize interrupt handlers
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Hello.

Atsushi Nemoto wrote:

> The IOC interrupt status register on RBTX49XX only have 8 bits.  Use
> 8-bit version of __fls() to optimize interrupt handlers.
>   

   But doesn't the patch also change the result of 
toshiba_rbtx49{27|38}_irq_nested() if the register reads back as 0?

> Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
> ---
>  arch/mips/txx9/rbtx4927/irq.c   |    6 +++---
>  arch/mips/txx9/rbtx4938/irq.c   |    8 ++++----
>  include/asm-mips/txx9/generic.h |   18 ++++++++++++++++++
>  3 files changed, 25 insertions(+), 7 deletions(-)
>
> diff --git a/arch/mips/txx9/rbtx4927/irq.c b/arch/mips/txx9/rbtx4927/irq.c
> index 22076e3..9c14ebb 100644
> --- a/arch/mips/txx9/rbtx4927/irq.c
> +++ b/arch/mips/txx9/rbtx4927/irq.c
> @@ -133,9 +133,9 @@ static int toshiba_rbtx4927_irq_nested(int sw_irq)
>  	u8 level3;
>  
>  	level3 = readb(rbtx4927_imstat_addr) & 0x1f;
> -	if (level3)
> -		sw_irq = RBTX4927_IRQ_IOC + fls(level3) - 1;
> -	return sw_irq;
> +	if (unlikely(!level3))
> +		return -1;
> +	return RBTX4927_IRQ_IOC + __fls8(level3);
>  }
>  
>  static void __init toshiba_rbtx4927_irq_ioc_init(void)
> diff --git a/arch/mips/txx9/rbtx4938/irq.c b/arch/mips/txx9/rbtx4938/irq.c
> index ca2f830..7d21bef 100644
> --- a/arch/mips/txx9/rbtx4938/irq.c
> +++ b/arch/mips/txx9/rbtx4938/irq.c
> @@ -85,10 +85,10 @@ static int toshiba_rbtx4938_irq_nested(int sw_irq)
>  	u8 level3;
>  
>  	level3 = readb(rbtx4938_imstat_addr);
> -	if (level3)
> -		/* must use fls so onboard ATA has priority */
> -		sw_irq = RBTX4938_IRQ_IOC + fls(level3) - 1;
> -	return sw_irq;
> +	if (unlikely(!level3))
> +		return -1;
> +	/* must use fls so onboard ATA has priority */
> +	return RBTX4938_IRQ_IOC + __fls8(level3);
>  }
>  
>  static void __init

WBR, Sergei



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From:	Jakub Narebski <jnareb@gmail.com>
Subject: [ANNOUNCE] Git User's Survey 2008
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Hi all,

We would like to ask you a few questions about your use of the Git
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The results will be published on the Git Wiki
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From anemo@mba.ocn.ne.jp Wed Sep  3 16:52:59 2008
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Subject: Re: [PATCH 2/6] TXx9: Microoptimize interrupt handlers
From:	Atsushi Nemoto <anemo@mba.ocn.ne.jp>
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On Wed, 03 Sep 2008 14:13:26 +0400, Sergei Shtylyov <sshtylyov@ru.mvista.com> wrote:
> > The IOC interrupt status register on RBTX49XX only have 8 bits.  Use
> > 8-bit version of __fls() to optimize interrupt handlers.
> >   
> 
>    But doesn't the patch also change the result of 
> toshiba_rbtx49{27|38}_irq_nested() if the register reads back as 0?

Yes, now _irq_nested() returns -1 if no interrupts, and it will be
counted as spurious interrupts.  I think this is a little bonus ;)

---
Atsushi Nemoto

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Subject: Re: [PATCH 4/6] TXx9: Add TX4939 SoC support
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On Wed, 03 Sep 2008 14:04:39 +0400, Sergei Shtylyov <sshtylyov@ru.mvista.com> wrote:
>    At last. Cool. I know this SoC has IDE controller. Planning on 
> submitting a driver?

Yes, but I'm wondering whether it is worth to submit before converting
to ata driver.  It seems the drivers/ide in in deep
cleanup/refactoring state.  (linux-next contains 100 patches from
Bartlomiej!)

Do you think a new ide driver will be accepted?

---
Atsushi Nemoto

From sshtylyov@ru.mvista.com Wed Sep  3 22:31:56 2008
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Subject: Re: [PATCH 4/6] TXx9: Add TX4939 SoC support
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Hello.

Atsushi Nemoto wrote:

>>    At last. Cool. I know this SoC has IDE controller. Planning on 
>> submitting a driver?
>>     

   I myself have the source (outdated and needing a big hammer) and even 
the documentaion AFAIR but lack both the hardware (at least locally 
accessible) and time.

> Yes, but I'm wondering whether it is worth to submit before converting
> to ata driver.

   Well,  IDE is still more embedded friendly (not coupled with SCSI -- 
unlike libata)...

> It seems the drivers/ide in in deep
> cleanup/refactoring state.  (linux-next contains 100 patches from
> Bartlomiej!)
>
> Do you think a new ide driver will be accepted?
>   

   Of course it will. But due to much of refactoring that's been 
happening it will require some work to move it forward from the older 
version (I guess you have it as well): IDE drivers should now be pretty 
close to the libata ones functionally.

> ---
> Atsushi Nemoto

MBR, Sergei



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Subject: Re: [PATCH 4/6] TXx9: Add TX4939 SoC support
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On Thu, 04 Sep 2008 01:31:47 +0400, Sergei Shtylyov <sshtylyov@ru.mvista.com> wrote:
> > It seems the drivers/ide in in deep
> > cleanup/refactoring state.  (linux-next contains 100 patches from
> > Bartlomiej!)
> >
> > Do you think a new ide driver will be accepted?
> 
>    Of course it will. But due to much of refactoring that's been 
> happening it will require some work to move it forward from the older 
> version (I guess you have it as well): IDE drivers should now be pretty 
> close to the libata ones functionally.

I have a driver for current mainline and it is based on the driver in
CELF patch archive.  I will try to update the driver against
linux-next tree.

---
Atsushi Nemoto

From tsbogend@alpha.franken.de Thu Sep  4 22:05:46 2008
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From:	Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Subject: [PATCH] IP22: Fix detection of second HPC3 on Challenge S
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The second HPC3 coulde be found only on Guiness systems (Challenge-S),
but not on fullhouse (Indigo2) systems.

Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
---

 arch/mips/sgi-ip22/ip22-platform.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/arch/mips/sgi-ip22/ip22-platform.c b/arch/mips/sgi-ip22/ip22-platform.c
index 9bbb90b..deddbf0 100644
--- a/arch/mips/sgi-ip22/ip22-platform.c
+++ b/arch/mips/sgi-ip22/ip22-platform.c
@@ -150,7 +150,7 @@ static int __init sgiseeq_devinit(void)
 		return res;
 
 	/* Second HPC is missing? */
-	if (!ip22_is_fullhouse() ||
+	if (ip22_is_fullhouse() ||
 	    get_dbe(tmp, (unsigned int *)&hpc3c1->pbdma[1]))
 		return 0;
 

From br1@einfach.org Thu Sep  4 22:51:26 2008
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From:	Bruno Randolf <br1@einfach.org>
Subject: [PATCH] au1000: fix gpio output
To:	florian@openwrt.org, linux-mips@linux-mips.org
Date:	Thu, 04 Sep 2008 23:51:06 +0200
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when setting the output state of one GPIO pin we have to keep the state of the
other pins, hence use binary OR. also gpio_direction_output() wants to set an
initial value, so add that too.

this fixes a problem with the USB power switch on mtx-1 boards.

Signed-off-by: Bruno Randolf <br1@einfach.org>
---

 arch/mips/au1000/common/gpio.c |    4 +++-
 1 files changed, 3 insertions(+), 1 deletions(-)

diff --git a/arch/mips/au1000/common/gpio.c b/arch/mips/au1000/common/gpio.c
index b485d94..1f05843 100644
--- a/arch/mips/au1000/common/gpio.c
+++ b/arch/mips/au1000/common/gpio.c
@@ -61,7 +61,8 @@ static int au1xxx_gpio2_direction_input(unsigned gpio)
 static int au1xxx_gpio2_direction_output(unsigned gpio, int value)
 {
 	gpio -= AU1XXX_GPIO_BASE;
-	gpio2->dir = (0x01 << gpio) | (value << gpio);
+	gpio2->dir |= 0x01 << gpio;
+	gpio2->output = (GPIO2_OUTPUT_ENABLE_MASK << gpio) | (value << gpio);
 	return 0;
 }
 
@@ -90,6 +91,7 @@ static int au1xxx_gpio1_direction_input(unsigned gpio)
 static int au1xxx_gpio1_direction_output(unsigned gpio, int value)
 {
 	gpio1->trioutclr = (0x01 & gpio);
+	au1xxx_gpio1_write(gpio, value);
 	return 0;
 }
 


From dmitri.vorobiev@movial.fi Tue Sep  9 12:14:24 2008
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Hi,

<<<<<<<<

[dmitri.vorobiev@amber linux-2.6.27-rc5]$ make ARCH=mips CROSS_COMPILE=mips-unknown-linux-gnu- malta_defconfig
#
# configuration written to .config
#
[dmitri.vorobiev@amber linux-2.6.27-rc5]$ make ARCH=mips CROSS_COMPILE=mips-unknown-linux-gnu-
scripts/kconfig/conf -s arch/mips/Kconfig
#
# configuration written to .config
#
  CHK     include/linux/version.h
  CHK     include/linux/utsrelease.h
  CALL    scripts/checksyscalls.sh
  CHK     include/linux/compile.h
  CC      arch/mips/kernel/mips-mt-fpaff.o
arch/mips/kernel/mips-mt-fpaff.c: In function 'mipsmt_sys_sched_setaffinity':
arch/mips/kernel/mips-mt-fpaff.c:82: error: 'struct task_struct' has no member named 'euid'
arch/mips/kernel/mips-mt-fpaff.c:82: error: 'struct task_struct' has no member named 'uid'
make[1]: *** [arch/mips/kernel/mips-mt-fpaff.o] Error 1
make: *** [arch/mips/kernel] Error 2
[dmitri.vorobiev@amber linux-2.6.27-rc5]$

<<<<<<<<

Thanks,
Dmitri

Andrew Morton wrote:
> ftp://ftp.kernel.org/pub/linux/kernel/people/akpm/patches/2.6/2.6.27-rc5/2.6.27-rc5-mm1/
> 
> - This kernel doesn't work very well if selinux is enabled: /proc/net
>   breaks.
> 
> - suspend-to-RAM (and probably -to-disk) has regressed on one machine.
> 
> - Various other weird bumps, bangs and rattles, all of which have been
>   reported, not all of which have been acknowledgedacpi^W^W^W^W.
> 
> - I seem to have a very large number of patches outstanding against a
>   very large number of subsystems.  Many of which have already been sent
>   to the relevant maintainer at least once.
> 
> 
> Boilerplate:
> 
> - See the `hot-fixes' directory for any important updates to this patchset.
> 
> - To fetch an -mm tree using git, use (for example)
> 
>   git-fetch git://git.kernel.org/pub/scm/linux/kernel/git/smurf/linux-trees.git tag v2.6.16-rc2-mm1
>   git-checkout -b local-v2.6.16-rc2-mm1 v2.6.16-rc2-mm1
> 
> - -mm kernel commit activity can be reviewed by subscribing to the
>   mm-commits mailing list.
> 
>         echo "subscribe mm-commits" | mail majordomo@vger.kernel.org
> 
> - If you hit a bug in -mm and it is not obvious which patch caused it, it is
>   most valuable if you can perform a bisection search to identify which patch
>   introduced the bug.  Instructions for this process are at
> 
>         http://www.zip.com.au/~akpm/linux/patches/stuff/bisecting-mm-trees.txt
> 
>   But beware that this process takes some time (around ten rebuilds and
>   reboots), so consider reporting the bug first and if we cannot immediately
>   identify the faulty patch, then perform the bisection search.
> 
> - When reporting bugs, please try to Cc: the relevant maintainer and mailing
>   list on any email.
> 
> - When reporting bugs in this kernel via email, please also rewrite the
>   email Subject: in some manner to reflect the nature of the bug.  Some
>   developers filter by Subject: when looking for messages to read.
> 
> - Occasional snapshots of the -mm lineup are uploaded to
>   ftp://ftp.kernel.org/pub/linux/kernel/people/akpm/mm/ and are announced on
>   the mm-commits list.  These probably are at least compilable.
> 
> - More-than-daily -mm snapshots may be found at
>   http://userweb.kernel.org/~akpm/mmotm/.  These are almost certainly not
>   compileable.
> 
> 
> 
> Changes since 2.6.27-rc1-mm1:
> 
>  origin.patch
>  git-jg-misc.patch
>  git-libata-all.patch
>  git-xtensa.patch
> 
>  git trees
> 
> -remove-newline-from-the-description-of-module-parameters.patch
> -pnp-fix-formatting-of-dbg_pnp_show_resources-output.patch
> -missing-symbol-prefix-on-vmlinuxldsh.patch
> -missing-symbol-prefix-on-vmlinuxldsh-checkpatch-fixes.patch
> -mm-hugetlb-dont-crash-when-hpage_shift-is-0.patch
> -seq_file-fix-bug-when-seq_read-reads-nothing.patch
> -pci-make-pci_register_driver-a-macro.patch
> -acpi-add-checking-for-null-early-param.patch
> -calgary-fix-a-comparison-warning-the-pci-calgary-64-driver.patch
> -use-warn-in-arch-x86-mm-ioremapc.patch
> -use-warn-in-arch-x86-mm-pageattrc.patch
> -use-warn-in-arch-x86-kernel.patch
> -arch-x86-pci-irqc-attempt-to-clean-up-code-layout.patch
> -i386-vmalloc-size-fix.patch
> -x86-calgary-replace-num_dma_pages-with-iommu_num_pages.patch
> -x86-export-is_uv_system.patch
> -x86-tracehook_signal_handler.patch
> -x86-tracehook-syscall.patch
> -x86-tracehook-asm-syscallh.patch
> -x86-signals-use-asm-syscallh.patch
> -x86-tracehook-tif_notify_resume.patch
> -intel_agp-official-name-for-gm45-chipset.patch
> -amd64-agp-run-fallback-when-no-bridges-found-not-when-driver-registration-fails.patch
> -agp-use-dev_printk-when-possible.patch
> -ppc-use-the-common-ascii-hex-helpers.patch
> -powerpc-replace-__function__-with-__func__.patch
> -drivers-base-driverc-remove-unused-to_dev-macro.patch
> -dev_printk-constify-the-dev-argument.patch
> -drm-remove-defines-for-non-linux-systems.patch
> -sis-drm-fix-the-memory-allocator-if-the-sis-fb-is-built-as-a-module.patch
> -sis-drm-fix-a-pointer-cast-warning.patch
> -v4l-link-tuner-before-saa7134.patch
> -v4l-drx397xdc-sparse-annotations.patch
> -v4l-drx397xdc-replace-__function__-occurrences.patch
> -v4l-fix-kernel-doc-warning-function-name-and-docbook-filename.patch
> -drivers-media-video-vinoc-needs-v4l2-ioctlh.patch
> -i2c-renesas-highlander-fpga-smbus-support.patch
> -hid-wellspring-device-quirks.patch
> -migrate_timers-add-comment-use-spinlock_irq.patch
> -drivers-input-serio-xilinx_ps2c-fix-warning.patch
> -wistron_btns-add-support-for-fujitsu-siemens-amilo-pro-edition-v3505.patch
> -maple-allow-removal-and-reinsertion-of-keyboard-driver-module.patch
> -input-bcm5974-055-smoother-motion-irq-simplification.patch
> -genksyms-parser-fix-the-__attribute__-rule.patch
> -genksyms-include-extern-information-in-dumps.patch
> -libata-scsi-dont-start-hotplug-work-queue-if-hotplug-is-disabled.patch
> -libata-core-make-sure-that-ata_force_tbl-is-freed-in-case-of-an-error.patch
> -pata_viac-add-flag-for-vx800-and-add-a-function-for-fixing-internal-bugs-for-via-chipsets.patch
> -cdrom-dont-check-cdc_play_audio-in-cdrom_count_tracks.patch
> -drivers-mtd-nand-nandsimc-needs-div64h.patch
> -jffs2-summary-allocation-dont-use-vmalloc.patch
> -mtd-diskonchipc-fix-sparse-endian-warnings.patch
> -mtdpart-handle-remaining-checkpatch-findings.patch
> -blackfin-nfc-driver-fix-bug-do-not-clobber-the-status-from-the-first-256-bytes-if-operating-on-512-pages.patch
> -blackfin-nfc-driver-fix-bug-hw-ecc-calc-by-making-sure-we-extract-11-bits-from-each-register-instead-of-10.patch
> -blackfin-nfc-driver-add-support-for-the-ecc-layout-the-blackfin-bootrom-uses.patch
> -blackfin-nfc-driver-add-proper-devinit-devexit-markings-to-probe-remove-functions.patch
> -blackfin-nfc-driver-enable-blackfin-nand-hwecc-support-by-default.patch
> -blackfin-nfc-driver-use-standard-dev_err-rather-than-printk.patch
> -blackfin-nfc-driver-cleanup-the-error-exit-path-of-bf5xx_nand_probe-function.patch
> -drivers-mtd-nand-nandsimc-fix-printk-warnings.patch
> -mtd-dataflash-otp-support.patch
> -random32-seeding-improvement.patch
> -bridge-send-correct-mtu-value-in-pmtu.patch
> -bridge-send-correct-mtu-value-in-pmtu-revised.patch
> -net-use-the-common-ascii-hex-helpers.patch
> -atm-fix-const-assignment-discard-warnings-in-the-atm-networking-driver.patch
> -atm-fix-direct-casts-of-pointers-to-u32-in-the-interphase-driver.patch
> -bluetooth-add-quirks-for-a-few-hci_usb-devices.patch
> -nsc-ircc-default-to-dongle-type-9-on-ibm-hardware.patch
> -irda-replace-__function__-with-__func__.patch
> -hysdn-remove-the-packed-attribute-from-poftimstamp_tag.patch
> -isdn-use-the-common-ascii-hex-helpers.patch
> -via-velocity-give-a-structure-to-the-rx-tx-fields.patch
> -via-velocity-fix-sleep-with-spinlock-bug-during-mtu-change.patch
> -hamradio-add-missing-sanity-check-to-tty-operation.patch
> -pegasus-add-blacklist-support-to-fix-belkin-bluetooth-dongle.patch
> -drivers-net-ehea-ehea_mainc-release-mutex-in-error-handling-code.patch
> -tg3-adapt-tg3-to-use-reworked-pci-pm-code.patch
> -sky2-adapt-to-use-reworked-pci-pm-code.patch
> -configure-out-file-locking-features.patch
> -use-warn-in-kernel-lockdepc.patch
> -sched-do_wait_for_common-use-signal_pending_state.patch
> -wait_task_inactive-dont-consider-task-nivcsw.patch
> -sched-type-fix.patch
> -netfilter-conntrack_helper-needs-to-include-rculisth.patch
> -drivers-usb-class-cdc-acmc-use-correct-type-for-cpu-flags.patch
> -drivers-usb-class-cdc-wdmc-fix-build-with-config_pm=n.patch
> -cxacru-fix-printk-format-flag-in-error-message.patch
> -cdc-acm-dont-unlock-acm-mutex-on-error-path.patch
> -usb-move-usb-mon-up-to-misc-options-in-kconfig.patch
> -pl2023-remove-usb-id-4348-5523-handled-by-ch341.patch
> -usb-storage-unusual_devs-entries-for-iriver-t10-and-datafab-cfsm-reader.patch
> -usb-core-driver-fix-warning.patch
> -usb-hubc-fix-build-with-config_pm=n.patch
> -ath5k-mask-out-unneeded-interrupts.patch
> -ath5k-unify-resets.patch
> -net-ieee80211-adjust-error-handling.patch
> -wireless-replace-__function__-with-__func__.patch
> -xfs-use-get_unaligned_-helpers.patch
> -xfs-clean-up-stale-references-to-semaphores.patch
> -xfs-replace-the-xfs-buf-iodone-semaphore-with-a-completion.patch
> -xfs-extend-completions-to-provide-xfs-object-flush-requirements.patch
> -xfs-replace-inode-flush-semaphore-with-a-completion.patch
> -xfs-replace-dquot-flush-semaphore-with-a-completion.patch
> -xfs-remove-the-sema_t-from-xfs.patch
> -xtensa-warn-about-including-asm-rwsemh-directly.patch
> -xtensa-replace-remaining-__function__-occurences.patch
> -xtensa-use-newer-__spin_lock_unlocked-macro.patch
> -modules-extend-initcall_debug-functionality-to-the-module-loader.patch
> -powerpc-86xx-mpc8610_hpcd-add-watchdog-node.patch
> -kdump-report-actual-value-of-vmcoreinfo_osrelease-in-vmcoreinfo.patch
> -vt8623fb-fix-kernel-oops.patch
> -block-ccissc-remove-pointless-curr_queue-calculation.patch
> -spi-new-orion_spi-driver.patch
> -spi-new-orion_spi-driver-fixes.patch
> -relay-fix-4-off-by-one-errors-occuring-when-writing-to-a-cpu-buffer.patch
> -semaphore-__down_common-use-signal_pending_state.patch
> -genirq-better-warning-on-irqchip-set_type-failure.patch
> -proc-fix-inode-number-bogorithmetic.patch
> -proc-switch-inode-number-allocation-to-ida.patch
> -blackfin-rtc-driver-if-we-dont-define-irq_set_freq-the-common-rtc-dev-layer-will-give-us-the-same-behavior-of-returning-enotty.patch
> -blackfin-rtc-driver-fix-bug-only-rtc-interrupt-can-wake-up-deeper-sleep-core.patch
> -blackfin-rtc-driver-add-support-for-power-management-framework.patch
> -blackfin-rtc-driver-dont-bother-passing-the-rtc-struct-down-to-bfin_rtc_int_setclear-since-it-isnt-needed-shaves-off-100bytes.patch
> -blackfin-rtc-driver-disable-the-write-complete-irq-upon-close.patch
> -blackfin-rtc-driver-wait-for-the-write-complete-interrupt-complete-before-sleeping.patch
> -blackfin-rtc-driver-convert-pie-handling-to-irq_set_state-as-pointed-out-by-david-brownell.patch
> -blackfin-rtc-driver-drop-pie-stopwatch-code-since-the-hardware-can-only-do-a-max-of-1hz-and-this-same-functionality-is-provided-by-uie.patch
> -backlight-add-more-information-output-to-pwm_backlight.patch
> -backlight-add-module_alias-to-pwm_backlight-driver.patch
> -remove-the-deprecated-cli-sti-functions.patch
> -drivers-telephony-ixjc-depends-on-pnp.patch
> -docsrc-build-documentation-sources.patch
> -docsrc-fix-procfs-example.patch
> -docsrc-fix-ifenslave-type.patch
> -docsrc-fix-crc32hash-type.patch
> -docsrc-fix-getdelays-printk-formats.patch
> -firmware-use-dev_printk-when-possible.patch
> -make-ioctlh-compatible-with-userland.patch
> -rtc-pcf8563-remove-client-validation.patch
> -rtc-m48t59-reduce-structure-m48t59_private.patch
> -ali-m7101-pmu-also-available-on-sun-netras-too.patch
> -firmware-memmap-cleanup.patch
> -applesmc-support-for-intel-imac.patch
> -applesmc-add-support-for-macbook-v3.patch
> -drivers-hwmon-w83791dc-fix-unused-var-warning.patch
> -hwmon-adc124s501-generic-driver.patch
> -hwmon-adc124s501-generic-driver-update.patch
> -i5k_amb-provide-labels-for-temperature-sensors.patch
> -drivers-mtd-chips-jedec_probec-fix-am29dl800bb-device-id.patch
> -forcedeth-bug-fix-realtek-phy-8211c-errata.patch
> -drivers-net-netxen-netxen_nic_hwc-fix-printk-warnings.patch
> -maintainers-mention-lockd-and-sunrpc-in-nfs-entries.patch
> -rcu-fix-synchronize_rcu-so-that-kernel-doc-works.patch
> -ftrace-disable-function-tracing-bringing-up-new-cpu.patch
> -ftrace-make-output-nicely-spaced-for-up-to-999-cpus.patch
> -clocksource-fix-a-print-format-error-in-the-acpi-pm-clocksource-driver-and-check-range.patch
> -clocksource-keep-track-of-original-clocksource-frequency.patch
> -clocksource-introduce-clocksource_forward_now.patch
> -clocksource-introduce-clock_monotonic_raw.patch
> -posix-timers-fix-posix_timer_event-vs-dequeue_signal-race.patch
> -posix-timers-do_schedule_next_timer-fix-the-setting-of-si_overrun.patch
> -unrevert-usb-dont-explicitly-reenable-root-hub-status-interrupts.patch
> -rtc-rtc-rs5c732-add-support-for-ricoh-r2025s-d-rtc.patch
> -devpts-switch-to-ida.patch
> -devpts-switch-to-ida-checkpatch-fixes.patch
> -byteorder-add-a-new-include-linux-swabh-to-define-byteswapping-functions.patch
> -byteorder-add-include-linux-byteorderh-to-define-endian-helpers.patch
> 
>  Merged into mainline or a subsystem tree
> 
> +res_counter-fix-off-by-one-bug-in-setting-limit.patch
> +forcedeth-fix-kexec-regression.patch
> +atmel_lcdfb-fix-oops-in-rmmod-when-framebuffer-fails-to-register.patch
> +tracehook-comment-pasto-fixes.patch
> 
>  2.6.27 queue
> 
> -linux-next-git-rejects.patch
> -linux-next-fixup.patch
> 
>  Unneeded
> 
> +security-selinux-include-netlabelh-fix-two-build-errors.patch
> +mfd-ucb1400-sound-driver-uses-depends-on-ac97_bus.patch
> +drivers-mfd-ucb1400_corec-needs-gpio.patch
> +drivers-mfd-ucb1400_corec-further-unbork.patch
> +kbuild-ftrace-dont-assume-that-scripts-recordmcountpl-is-executable.patch
> +fb-metronome-printk-format-warning.patch
> 
>  linux-next fixes
> 
> +introduce-generic-header-file-for-the-software-io-tlb.patch
> 
>  Early 2.6.28
> 
> +acpi-ec-dont-degrade-to-poll-mode-at-storm-automatically.patch
> +acpi-ec-dont-degrade-to-poll-mode-at-storm-automatically-cleanup.patch
> +toshiba_acpi-add-support-for-bluetooth-toggling-through-rfkill-v7.patch
> +toshiba_acpi-add-support-for-bluetooth-toggling-through-rfkill-v7-fix.patch
> +toshiba_acpi-add-support-for-bluetooth-toggling-through-rfkill-v7-fix-fix.patch
> +acpi-toshiba_acpic-fix-sparse-signedness-mismatch-warnings.patch
> 
>  ACPI things
> 
> +x86-fix-shadowed-variable-warning.patch
> +x86-use-dev_printk-in-quirk-message.patch
> +x86-make-poll_idle-behave-more-like-the-other-idle-methods.patch
> +x86-make-poll_idle-behave-more-like-the-other-idle-methods-checkpatch-fixes.patch
> +x86-init-annotations-in-early_printk-setup.patch
> +x86-adjust-dependencies-for-config_x86_cmov.patch
> +x86-pgd_cdtor-cleanup.patch
> +x86-x86_physvirt_bits-field-also-for-i386.patch
> +x86-adjust-vmalloc_sync_all-for-xen-2nd-try.patch
> +x86-fix-ticket-spin-lock-asm-constraints.patch
> +x86-64-reduce-boot-fixmap-space.patch
> +x86-64-add-two-__cpuinit-annotations.patch
> +x86-64-eliminate-dead-code.patch
> +x86-64-slightly-streamline-32-bit-syscall-entry-code.patch
> +x86_64-add-memory-hotremove-config-option.patch
> +arch-x86-kernel-early_printkc-remove-unused-enable_debug_console.patch
> +x86-use-common-header-for-software-io-tlb.patch
> 
>  x86 things
> 
> +drivers-rtc-rtc-bq4802c-dont-use-bin_2_bcd-and-bcd_2_bin.patch
> 
>  ALSA fix
> 
> +agp-follow-lspci-device-vendor-style.patch
> 
>  AGP update
> 
> +powerpc-convert-config_ppc_merge-to-config_ppc-for-legacy-io-checks.patch
> 
>  powerpc tweak
> 
> +fs-sysfs-dirc-remove-unused-__sysfs_get_dentry.patch
> +platform-add-new-device-registration-helper.patch
> 
>  device driver core updates
> 
> +v4l-dvb-gspca-fix-wrong-retry-counting.patch
> 
>  v4l
> 
> +fs-gfs2-use-an-is_err-test-rather-than-a-null-test.patch
> 
>  GFS fix
> 
> +fs-dlm-configc-choose-better-identifiers.patch
> 
>  DLM fix
> 
> +hid-fix-gyration-build-error.patch
> 
>  HID fix
> 
> +hrtimer-reorder-struct-hrtimer-to-save-8-bytes-on-64-bit-builds.patch
> +ntp-improve-adjtimex-frequency-rounding.patch
> +posix-timers-dont-switch-to-group_leader-if-it_process-dies.patch
> +posix-timers-always-do-get_task_structtimer-it_process.patch
> +posix-timers-sys_timer_create-remove-the-buggy-pf_exiting-check.patch
> +posix-timers-sys_timer_create-simplify-and-s-tasklist-rcu.patch
> +posix-timers-move-the-initialization-of-timer-sigq-from-send-to-create-path.patch
> +posix-timers-sys_timer_create-cleanup-the-error-handling.patch
> +posix-timers-kill-it_sigev_signo-and-it_sigev_value.patch
> +posix-timers-lock_timer-kill-the-bogus-it_id-check.patch
> +posix-timers-lock_timer-make-it-readable.patch
> 
>  Time-management things
> 
> +ia64-uv-provide-a-led-driver-for-uv-systems.patch
> +ia64-uv-use-led-to-indicate-cpu-is-active.patch
> +ia64-uv-use-blinking-led-for-heartbeat-display.patch
> +ia64-uv-use-blinking-led-for-heartbeat-display-fix.patch
> +ia64-avoid-invoking-irq-handlers-on-offline-cpus.patch
> +ia64-use-common-header-for-software-io-tlb.patch
> +ia64-fix-the-difference-between-node_mem_map-and-node_start_pfn.patch
> 
>  ia64 things
> 
> +drivers-input-touchscreen-ucb1400_tsc-needs-gpio.patch
> +serio_raw-add-support-for-translated-serio_i8042xl-ports.patch
> +bcm5974-064-minor-cleanups-for-scripts-checkpatchpl.patch
> +bcm5974-064-finger-tracking-and-counting-improved-further.patch
> +bcm5974-063-btn_touch-event-added-for-mousedev.patch
> 
>  input things
> 
> +scripts-package-dont-break-if-%_smp_mflags-isnt-set.patch
> +scripts-package-allow-custom-options-to-rpm.patch
> +scripts-checksyscallssh-fix-for-non-gnu-sed.patch
> +setlocalversion-dont-include-svn-change-count.patch
> +adjust-init-section-definitions.patch
> 
>  kbuild things
> 
> +leds-avoid-needless-strlen-for-attributes.patch
> +leds-wrap-use-default-on-trigger-for-power-led.patch
> +led-driver-for-leds-on-pcengines-alix2-and-alix3-boards.patch
> 
>  LED things
> 
> +libata-fix-lba28-lba48-off-by-one-bug-in-atah.patch
> +libata-blackfin-pata-driver-add-proper-pm-operation-into-atapi-driver.patch
> +libata-blackfin-pata-driver-add-proper-pm-operation-into-atapi-driver-fix.patch
> +libata-reorder-ata_device-to-remove-8-bytes-of-padding-on-64-bits.patch
> +pata_sil680-convert-config_ppc_merge-to-config_ppc.patch
> 
>  ata things
> 
> +m32r-export-empty_zero_page.patch
> +m32r-export-__ndelay.patch
> +m32r-kernel-cleanups.patch
> 
>  m32r things
> 
> -git-ubi-git-rejects.patch
> 
>  Unneeded
> 
> +mmc-fix-comment-in-include-linux-mmc-hosth.patch
> 
>  mmc fix
> 
> +mtd-maps-make-uclinux-mapping-driver-depend-on-mtd_ram-since-it-only-probes-that.patch
> +tmio_nand-fix-base-address-programming.patch
> 
>  MTD things
> 
> +net-fix-compilation-ng-when-config_module.patch
> +netfilter-xt_time-gives-a-wrong-monthday-in-a-leap-year.patch
> +drivers-atm-use-div_round_up.patch
> +drivers-net-wan-use-div_round_up.patch
> +hci_usb-replace-mb-with-smp_mb.patch
> +irda-follow-lspci-device-vendor-style.patch
> 
>  net things
> 
> +drivers-isdn-capi-kcapic-adjust-error-handling-code-involving-capi_ctr_put.patch
> +misdn-endian-annotations-for-struct-zt.patch
> +misdn-annotate-iomem-pointer-and-add-statics.patch
> +misdn-misc-timerdev-fixes.patch
> 
>  ISDN things
> 
> +skty2-adapt-to-the-reworked-pci-pm.patch
> +e100-adapt-to-the-reworked-pci-pm.patch
> +the-overdue-eepro100-removal.patch
> +forcedeth-add-pci_enable_device-to-nv_resume.patch
> +driver-net-skgec-restart-the-interface-when-its-options-or-pauseparam-is-set.patch
> +fs-enet-remove-code-associated-with-config_ppc_merge.patch
> +netdev-drop-config_ppc_merge-from-kconfig.patch
> +e1000e-avoid-duplicated-output-of-device-name-in-kernel-warning.patch
> +e1000e-avoid-duplicated-output-of-device-name-in-kernel-warning-checkpatch-fixes.patch
> +e1000e-avoid-duplicated-output-of-device-name-in-kernel-warning-fix.patch
> +forcdeth-increase-max_interrupt_work.patch
> +atl1e-remove-the-unneeded-struct-atl1e_adapter.patch
> 
>  netdev things
> 
> +backlight-driver-for-tabletkiosk-sahara-touchit-213-tablet-pc.patch
> +backlight-driver-for-tabletkiosk-sahara-touchit-213-tablet-pc-update-2.patch
> +backlight-driver-for-tabletkiosk-sahara-touchit-213-tablet-pc-update-2-checkpatch-fixes.patch
> 
>  backlight things
> 
> +bq27x00_battery-use-unaligned-access-helper.patch
> 
>  battery things
> 
> +nfs-err_ptr-is-expected-on-failure-from-nfs_do_clone_mount.patch
> +sunrpc-do-not-pin-sunrpc-module-in-the-memory.patch
> +nfs-remove-8-bytes-of-padding-from-struct-nfs_fattr-on-64-bit-builds.patch
> 
>  NFS things
> 
> +parisc-lib-make-code-static.patch
> +drivers-parisc-make-code-static.patch
> 
>  parisc things
> 
> +pci-tidy-pme-support-messages-checkpatch-fixes.patch
> 
>  pci thing
> 
> +arch-s390-kernel-ptracec-fix-build.patch
> 
>  repair s390
> 
> +initramfs-fix-compilation-warning.patch
> +less-softirq-vectors.patch
> +dyn_array-use-%pf-instead-of-print_fn_descriptor_symbol.patch
> +dyn_array-fix-typo.patch
> +sched-fix-init_hrtick-section-mismatch-warning.patch
> +sched-clarify-ifdef-tangle.patch
> +lockstat-documentation-update.patch
> +fix-fastboot-make-the-raid-autodetect-code-wait-for-all-devices-to-init.patch
> +rcu-spinlocks-take-an-unsigned-long-flags.patch
> +rcu-fix-sparse-shadowed-variable-warning.patch
> +ftrace-warn-on-failure-to-disable-mcount-callers.patch
> +ftrace-remove-direct-reference-to-mcount-in-trace-code.patch
> 
>  random ingo stuff
> 
> +scsi-remove-the-unused-scsi_qlogic_fc_firmware-option.patch
> +drivers-scsi-a2091c-make-2-functions-static.patch
> +drivers-scsi-a3000c-make-2-functions-static.patch
> +drivers-scsi-use-div_round_up.patch
> +drivers-scsi-megaraid-use-div_round_up.patch
> +drivers-scsi-device_handler-scsi_dh_emcc-suppress-warning.patch
> 
>  More scsi things :(
> 
> -git-block-git-rejects.patch
> 
>  Unneeded
> 
> +drivers-block-use-div_round_up.patch
> +floppy-support-arbitrary-first-sector-numbers.patch
> 
>  block things
> 
> +drivers-rtc-kconfig-dont-build-rtc-cmoso-on-sparc32.patch
> 
>  Repair sparc32 build
> 
> +usb-remove-code-associated-with-config_ppc_merge.patch
> +drivers-usb-misc-use-an-is_err-test-rather-than-a-null-test.patch
> +drivers-usb-musb-disable-it-on-superh.patch
> 
>  usb things
> 
> +fs_mbcache-dont-needlessly-make-it-built-in.patch
> +vfs-make-security_inode_setattr-calling-consistent.patch
> +vfs-fix-vfs_rename_dir-for-fs_rename_does_d_move-filesystems.patch
> +include-linux-fsh-put-declarations-in-__kernel__.patch
> 
>  vfs things
> 
> +pika-warp-appliance-watchdog-timer.patch
> 
>  watchdog thing
> 
> +ath9k-uses-needs-led_classdev_register.patch
> 
>  wireless thing
> 
> +modules-remove-stop_machine-during-module-load.patch
> +modules-remove-stop_machine-during-module-load-checkpatch-fixes.patch
> 
>  modules things
> 
> +async_tx-fix-the-bug-in-async_tx_run_dependencies.patch
> +rtc-bunch-of-drivers-fix-no-irq-case-handing.patch
> 
>  More 2.6.27 things
> 
> +drivers-media-video-cafe_ccicc-needs-mmh.patch
> +jbd2-abort-instead-of-waiting-for-nonexistent-transactions.patch
> +misdn-dsp_cmxc-fix-size-checks.patch
> +h8300-kallsyms-exclude-local-symbols.patch
> +leds-pca955x-add-proper-error-handling-and-fix-bogus-memory-handling.patch
> +drivers-mmc-card-blockc-fix-refcount-leak-in-mmc_block_open.patch
> +drivers-net-skfp-pmfc-use-offsetof-macro.patch
> +drivers-net-atl1e-dont-take-the-mdio_lock-in-atl1e_probe.patch
> +e1000e-prevent-corruption-of-eeprom-nvm.patch
> +drivers-net-mlx4-allocc-needs-mmh.patch
> +nec-fix-for-hibernate-and-rmmod-oops-fix.patch
> +net-forcedeth-call-restore-mac-addr-in-nv_shutdown-path-v2.patch
> +net-forcedeth-call-restore-mac-addr-in-nv_shutdown-path-v2-fix.patch
> +nfs-bug_on-in-nfs_follow_mountpoint.patch
> +fix-pciehp_free_irq.patch
> +pci-hotplug-fakephp-fix-deadlock-again.patch
> +sched_clock-fix-nohz-interaction.patch
> +acpi_pmc-use-proper-read-function-also-in-errata-mode.patch
> +acpi_pmc-check-for-monotonicity.patch
> +clockevents-prevent-clockevent-event_handler-ending-up-handler_noop.patch
> +x86-delay-early-cpu-initialization-until-cpuid-is-done.patch
> +x86-move-mtrr-cpu-cap-setting-early-in-early_init_xxxx.patch
> +x86-add-io-delay-quirk-for-presario-f700.patch
> +posix-timers-use-struct-pid-instead-of-struct-task_struct.patch
> +posix-timers-check-it_signal-instead-of-it_pid-to-validate-the-timer.patch
> +posix-timers-simplify-de_thread-exit_itimers-path.patch
> 
>  Things which might be needed in 2.6.27 but which go via subsystem trees.
> 
> +memrlimit-cgroup-mm-owner-callback-changes-to-add-task-info.patch
> +mm-owner-fix-race-between-swap-and-exit.patch
> +mm-owner-fix-race-between-swap-and-exit-fix.patch
> +mm-page_allocc-free_area_init_nodes-fix-inappropriate-use-of-enum.patch
> +hugetlb-handle-updating-of-accessed-and-dirty-in-hugetlb_fault.patch
> +show-memory-section-to-node-relationship-in-sysfs.patch
> +mlock-mlocked-pages-are-unevictable-fix.patch
> +doc-unevictable-lru-and-mlocked-pages-documentation-update-2.patch
> +mmap-handle-mlocked-pages-during-map-remap-unmap-mlock-fix-__mlock_vma_pages_range-comment-block.patch
> +mmap-handle-mlocked-pages-during-map-remap-unmap-mlock-backout-locked_vm-adjustment-during-mmap.patch
> +mmap-handle-mlocked-pages-during-map-remap-unmap-mlock-resubmit-locked_vm-adjustment-as-separate-patch.patch
> +mmap-handle-mlocked-pages-during-map-remap-unmap-mlock-resubmit-locked_vm-adjustment-as-separate-patch-fix.patch
> +mmap-handle-mlocked-pages-during-map-remap-unmap-mlock-fix-return-value-for-munmap-mlock-vma-race.patch
> +mmap-handle-mlocked-pages-during-map-remap-unmap-mlock-update-locked_vm-on-munmap-of-mlocked-region.patch
> +mlock-revert-mainline-handling-of-mlock-error-return.patch
> +mlock-make-mlock-error-return-posixly-correct.patch
> +mlock-make-mlock-error-return-posixly-correct-fix.patch
> +mm-pagecache-insertion-fewer-atomics.patch
> +mm-unlockless-reclaim.patch
> +mm-page-lock-use-lock-bitops.patch
> +fs-buffer-lock-use-lock-bitops.patch
> +mm-page-allocator-minor-speedup.patch
> +mm-rewrite-vmap-layer.patch
> +mm-rewrite-vmap-layer-fix.patch
> +mm-rewrite-vmap-layer-fix-fix.patch
> +mm-rewrite-vmap-layer-fix-fix-fix.patch
> +mm-hugetlbc-make-functions-static-use-null-rather-than-0.patch
> 
>  Memory management updates
> 
> +uclinux-fix-gzip-header-parsing-in-binfmt_flatc.patch
> 
>  nommu
> 
> +h8300-update-timer-handler-delete-files.patch
> +h8300-update-timer-handler-new-files.patch
> +h8300-update-timer-handler-misc-update.patch
> +h8300-kconfig-cleanup.patch
> +h8300-generic_bug-support.patch
> +h8300-generic_bug-support-checkpatch-fixes.patch
> +asm-h8300-mdh-remove-cvs-keyword.patch
> 
>  h8/300
> 
> +alpha-miata-remove-dead-url.patch
> 
>  alpha
> 
> +pm-rework-disabling-of-user-mode-helpers-during-suspend-hibernation.patch
> +pm-rework-disabling-of-user-mode-helpers-during-suspend-hibernation-cleanup.patch
> +#
> +container-freezer-add-tif_freeze-flag-to-all-architectures.patch
> +container-freezer-add-tif_freeze-flag-to-all-architectures-fix.patch
> +container-freezer-make-refrigerator-always-available.patch
> +container-freezer-implement-freezer-cgroup-subsystem.patch
> +container-freezer-implement-freezer-cgroup-subsystem-checkpatch-fixes.patch
> +container-freezer-implement-freezer-cgroup-subsystem-fix-freezer-kconfig.patch
> +container-freezer-implement-freezer-cgroup-subsystem-uninline-thaw_process.patch
> +container-freezer-implement-freezer-cgroup-subsystem-uninline-thaw_process-fix.patch
> +container-freezer-implement-freezer-cgroup-subsystem-cleanup-comment.patch
> +container-freezer-skip-frozen-cgroups-during-power-management-resume.patch
> +container-freezer-prevent-frozen-tasks-or-cgroups-from-changing.patch
> +container-freezer-make-freezer-state-names-less-generic.patch
> +container-freezer-rename-check_if_frozen.patch
> +container-freezer-document-the-cgroup-freezer-subsystem.patch
> 
>  Power managememt
> 
> +maintainers-remove-hga-framebuffer-driver-entry.patch
> +include-linux-mounth-remove-cvs-keyword.patch
> +kernel-dmac-remove-a-cvs-keyword.patch
> +inith-remove-long-dead-__setup_null_param-macro.patch
> +drivers-misc-use-div_round_up.patch
> +fs-make-linux-kernel-parsers-match_table_t-const.patch
> +eeepc-laptop-use-standard-interfaces.patch
> +fix-documentation-filesystems-ramfs-rootfs-initramfstxt.patch
> +nubus-fix-mis-indented-statement.patch
> +identify_ramdisk_image-correct-typo-about-return-value-in-comment.patch
> +fix-random-typos.patch
> +add-phys_addr_t-for-holding-physical-addresses.patch
> +make-pfn_phys-explicitly-return-phys_addr_t.patch
> +redefine-resource_size_t-as-phys_addr_t.patch
> +separate-atomic_t-declaration-from-asm-atomich-into-asm-atomic_defh.patch
> +separate-atomic_t-declaration-from-asm-atomich-into-asm-atomic_defh-fix.patch
> +separate-atomic_t-declaration-from-asm-atomich-into-asm-atomic_defh-fix-fix.patch
> +fix-a-race-condtion-of-oops_in_progress.patch
> +fix-a-race-condtion-of-oops_in_progress-fix.patch
> +percpu-counters-clean-up-percpu_counter_sum_and_set-interface.patch
> +vsprintf-use-new-vsprintf-symbolic-function-pointer-format.patch
> +vsprintf-use-new-vsprintf-symbolic-function-pointer-format-cleanup.patch
> +wait-kill-is_sync_wait.patch
> +kconfig-eliminate-def_bool-n-constructs.patch
> +initramfs-add-option-to-preserve-mtime-from-initramfs-cpio-images.patch
> +make-taint-bit-reliable-v3.patch
> +make-taint-bit-reliable-v3-fix.patch
> 
>  Misc
> 
> +compat-move-cp_compat_stat-to-common-code.patch
> +compat-generic-compat-get-settimeofday.patch
> +compat-generic-compat-get-settimeofday-checkpatch-fixes.patch
> 
>  compat hnadling
> 
> +x86-rename-iommu_num_pages-function-to-iommu_nr_pages.patch
> +sparc64-rename-iommu_num_pages-function-to-iommu_nr_pages.patch
> +powerpc-rename-iommu_num_pages-function-to-iommu_nr_pages.patch
> +introduce-generic-iommu_num_pages-function.patch
> +x86-convert-gart-driver-to-generic-iommu_num_pages-function.patch
> +x86-amd-iommu-convert-driver-to-generic-iommu_num_pages-function.patch
> +x86-convert-calgary-iommu-driver-to-generic-iommu_num_pages-function.patch
> +powerpc-use-iommu_num_pages-function-in-iommu-code.patch
> +alpha-use-iommu_num_pages-function-in-iommu-code.patch
> +sparc64-use-iommu_num_pages-function-in-iommu-code.patch
> 
>  IOMMU
> 
> +checkpatch-square-brackets-exemption-for-array-slices-in-braces.patch
> +checkpatch-values-double-ampersand-may-be-unary.patch
> +checkpatch-conditional-indent-labels-have-different-indent-rules.patch
> +checkpatch-switch-indent-allow-plain-return.patch
> +checkpatch-add-tests-for-the-attribute-matcher.patch
> +checkpatch-____cacheline_aligned-et-al-are-modifiers.patch
> +checkpatch-complex-macros-fix-up-extension-handling.patch
> +checkpatch-fix-up-comment-checks-search-to-scan-the-entire-block.patch
> +checkpatch-include-asm-checks-should-be-anchored.patch
> +checkpatch-reduce-warnings-for-include-of-asm-fooh-to-check-from-arch-barc.patch
> +checkpatch-report-any-absolute-references-to-kernel-source-files.patch
> +checkpatch-report-the-real-first-line-of-all-suspect-indents.patch
> +checkpatch-suspect-indent-skip-over-preprocessor-label-and-blank-lines.patch
> +checkpatch-%lx-tests-should-hand-%%-as-a-literal.patch
> +checkpatch-report-the-correct-lines-for-single-statement-blocks.patch
> +checkpatch-perform-indent-checks-on-perl.patch
> +checkpatch-version-022.patch
> +checkpatch-case-default-checks-should-only-check-changed-lines.patch
> +checkpatch-suppress-errors-triggered-by-short-patch.patch
> +checkpatch-handle-comment-quote-nesting-correctly.patch
> +checkpatch-check-line-endings-in-text-format-files.patch
> +checkpatch-suspect-indent-count-condition-lines-correctly.patch
> +checkpatch-ensure-we-only-apply-checks-to-the-lines-within-hunks.patch
> +checkpatch-version-023.patch
> 
>  checkpatch updates
> 
> +oss-remove-references-to-dead-sound-oss-vars-aedsp16_msssbpro.patch
> 
>  OSS drivers
> 
> +binfmt_somc-add-module_license.patch
> 
>  binfmt
> 
> +make-probe_serial_gsc-static.patch
> +serial-mpc52xx_uart-remove-code-associated-with-config_ppc_merge.patch
> 
>  serial
> 
> +mpc52xx_psc_spi-remove-code-associated-with-config_ppc_merge.patch
> 
>  spi
> 
> +i2o-fix-32-64bit-dma-locking.patch
> 
>  i2o
> 
> +drivers-net-xen-netfrontc-use-div_round_up.patch
> 
>  xen
> 
> +ecryptfs-remove-retry-loop-in-ecryptfs_readdir.patch
> 
>  ecryptfs
> 
> +autofs4-cleanup-autofs-mount-type-usage.patch
> +autofs4-track-uid-and-gid-of-last-mount-requester.patch
> +autofs4-track-uid-and-gid-of-last-mount-requester-fix.patch
> +autofs4-devicer-node-ioctl-docoumentation.patch
> +autofs4-add-miscellaneous-device-for-ioctls.patch
> +autofs4-add-miscellaneous-device-for-ioctls-fix.patch
> +autofs4-add-miscellaneous-device-for-ioctls-fix-2.patch
> +autofs4-add-miscellaneous-device-for-ioctls-fix-fix-3.patch
> 
>  autofs
> 
> +rtc-pcf8563-remove-client-validation.patch
> +rtc-ds1374-wakeup-support-update.patch
> +rtc-add-device-driver-for-dallas-ds3234-spi-rtc-chip-fix.patch
> +rtc-rtc-rs5c372-add-support-for-ricoh-r2025s-d-rtc.patch
> +rtc-file-close-consistently-disables-repeating-irqs.patch
> +rtc-cmos-strongly-avoid-hpet-emulation.patch
> +rtc-use-config_ppc-instead-of-config_ppc_merge.patch
> +rtc-rtc-m41t80c-add-support-for-the-st-m41t65-rtc.patch
> 
>  rtc
> 
> +make-gpiochip-label-const.patch
> +gpio-max7301-fix-the-race-between-chip-addition-and-pins-reconfiguration.patch
> 
>  gpio
> 
> +fb-push-down-the-bkl-in-the-ioctl-handler.patch
> +fb-push-down-the-bkl-in-the-ioctl-handler-checkpatch-fixes.patch
> +radeonfb-revert-fix-radeon-ddc-regression.patch
> +fb-convert-lock-unlock_kernel-into-local-fb-mutex.patch
> +neofb-reduce-panning-function.patch
> +viafb-viafbmodes-viafbtxt.patch
> +viafb-viafbmodes-viafbtxt-fix.patch
> +viafb-viafbmodes-viafbtxt-fix-fix.patch
> +viafb-makefile-kconfig.patch
> +viafb-accelc-accelh.patch
> +viafb-accelc-accelh-checkpatch-fixes.patch
> +viafb-accelc-accelh-update.patch
> +viafb-chiph-debugh.patch
> +viafb-dvic-dvih-globalc-and-globalh.patch
> +viafb-dvic-dvih-globalc-and-globalh-checkpatch-fixes.patch
> +viafb-hwc-hwh.patch
> +viafb-hwc-hwh-checkpatch-fixes.patch
> +viafb-ifacec-ifaceh-ioctlc-ioctlh.patch
> +viafb-lcdc-lcdh-lcdtblh.patch
> +viafb-makefile-shareh.patch
> +viafb-tbl1636c-tbl1636h-tbldpasettingc-tbldpasettingh.patch
> +viafb-viafbdevc-viafbdevh.patch
> +viafb-viafbdevc-viafbdevh-checkpatch-fixes.patch
> +viafb-viafbdevc-update.patch
> +viafb-via_i2cc-via_i2ch-viamodec-viamodeh.patch
> +viafb-via_utilityc-via_utilityh-vt1636c-vt1636h.patch
> +viafb-maintainers-entry.patch
> +fbdev-kconfig-update.patch
> +fbdev-kconfig-update-fix.patch
> +neofb-kill-some-redundant-code.patch
> +vga16fb-remove-open_lock-mutex.patch
> +neofb-remove-open_lock-mutex.patch
> +tdfxfb-do-not-make-changes-to-default-tdfx_fix.patch
> +intelfb-support-945gme-as-used-in-asus-eee-901.patch
> +cirrusfb-remove-information-about-memory-size-during-mode-change.patch
> +cirrusfb-simplify-clock-calculation.patch
> +cirrusfb-remove-24-bpp-mode.patch
> +cirrusfb-drop-device-pointers-from-cirrusfb_info.patch
> +cirrusfb-use-modedb-and-add-mode_option-parameter-2nd-rev.patch
> +cirrusfb-add-__devinit-attribute-to-probing-functions.patch
> +cirrusfb-eliminate-crt-registers-from-global-structure.patch
> +cirrusfb-drop-clock-fields-from-cirrusfb_regs-structure.patch
> +atmel_lcdfb-disallow-setting-larger-resolution-than-the-framebuffer-memory-can-handle.patch
> +efifb-imacfb-consolidation-hardware-support.patch
> 
>  fbdev
> 
> +pnp-remove-printk-with-outdated-version.patch
> +pnp-make-the-resource-type-an-unsigned-long.patch
> +pnp-make-the-resource-type-an-unsigned-long-fix.patch
> 
>  pnp
> 
> +telephony-remove-cvs-keywords.patch
> 
>  telephony
> 
> +ext2-fix-ext2-block-reservation-early-enospc-issue.patch
> 
>  ext2
> 
> +ext3-dont-try-to-resize-if-there-are-no-reserved-gdt-blocks-left.patch
> +ext3-fix-ext3-block-reservation-early-enospc-issue.patch
> +jbd-abort-instead-of-waiting-for-nonexistent-transactions.patch
> 
>  ext3
> 
> +hfsplus-quieten-down-mounting-hfsplus-journaled-fs-read-only.patch
> +hfsplus-fix-buffer-overflow-with-a-corrupted-image.patch
> +hfsplus-check-read_mapping_page-return-value.patch
> +hfsplus-fix-another-bug-when-reading-a-corrupted-image.patch
> +hfsplus-check-hfs_bnode_find-return-value.patch
> 
>  hfsplus
> 
> +reiserfs-procfsc-remove-cvs-keywords.patch
> +fs-reiserfs-use-an-is_err-test-rather-than-a-null-test.patch
> 
>  reiserfs
> 
> +quota-remove-cvs-keywords.patch
> 
>  quota
> 
> +cgroups-fix-probable-race-with-put_css_set-and-find_css_set.patch
> +cgroups-fix-probable-race-with-put_css_set-and-find_css_set-fix.patch
> 
>  cgroups
> 
> +devcgroup-use-kmemdup.patch
> +devcgroup-remove-unused-variable.patch
> +devcgroup-remove-spin_lock.patch
> 
>  devcgroup
> 
> -memrlimit-cgroup-mm-owner-callback-changes-to-add-task-info.patch
> +memrlimit-setup-the-memrlimit-controller-mm_owner-fix.patch
> +memrlimit-add-memrlimit-controller-accounting-and-control-memory-rlimit-enhance-mm_owner_changed-callback-to-deal-with-exited-owner.patch
> +memrlimit-add-memrlimit-controller-accounting-and-control-mm_owner-fix.patch
> +memrlimit-add-memrlimit-controller-accounting-and-control-mm_owner-fix-checkpatch-fixes.patch
> +memrlimit-add-memrlimit-controller-accounting-and-control-memory-rlimit-fix-crash-on-fork.patch
> 
>  memrlimit controller
> 
> +cpuset-use-seq_cpumask-seq_nodemask.patch
> +cpusetc-remove-extra-variable.patch
> 
>  cpusets
> 
> +irq-warn-about-irqf_disabledirqf_shared.patch
> 
>  genirq
> 
> +make-ptrace_untrace-static.patch
> 
>  ptrace
> 
> +kdump-update-elfcorehdr-documentation-to-reflect-supported-architectures.patch
> +kdump-use-is_kdump_kernel-in-sba_init.patch
> +kdump-add-is_vmcore_usable-and-vmcore_unusable.patch
> +kdump-add-is_vmcore_usable-and-vmcore_unusable-update.patch
> +kdump-use-is_vmcore_usable-and-vmcore_unusable-in-reserve_elfcorehdr.patch
> +kdump-ia64-always-reserve-elfcore-header-memory-in-crash-kernel.patch
> 
>  kdump
> 
> +message-queues-increase-range-limits.patch
> +message-queues-increase-range-limits-checkpatch-fixes.patch
> 
>  IPC
> 
> +compat_binfmt_elf-definition-tweak.patch
> 
>  elf
> 
> +applicomc-fix-apparently-broken-code-in-do_ac_read.patch
> +char-moxac-sparse-annotation.patch
> 
>  char drivers
> 
> +firmware-use-dev_printk-when-possible.patch
> 
>  firmware
> 
> +fs-partitions-acornc-remove-dead-code.patch
> 
>  partitions
> 
> +proc-move-sysrq-trigger-out-of-fs-proc.patch
> +proc-fix-return-value-of-proc_reg_open-in-too-late-case.patch
> +proc-proc_sys_root-tweak.patch
> +proc-remove-dummy-vmcore_open.patch
> +proc-remove-unused-get_dma_list.patch
> 
>  procfs
> 
> +sysctl-simplify-strategy.patch
> 
>  sysctl
> 
> +pid_ns-de_thread-kill-the-now-unneeded-child_reaper-change.patch
> +pid_ns-kill-the-now-unused-task_child_reaper.patch
> 
>  pidns
> 
> +trace-code-and-documentation-merging-documentation-tracetxt-with-documentation-filesystems-relaytxt.patch
> +rename-lib-trace-files-to-kernel-relay_debugfs-and-enhancements.patch
> +rename-lib-trace-files-to-kernel-relay_debugfs-and-enhancements-fix.patch
> 
>  relayfs
> 
> +make-i82443bxgx_edac-coexist-with-intel_agp.patch
> 
>  edac
> 
> +parport-remove-cvs-keywords.patch
> 
>  parport
> 
> +tpm-work-around-bug-in-broadcom-bcm0102-chipset.patch
> +tpm-include-moderated-for-non-subscribers-notation-in-maintainers.patch
> +drivers-char-tpm-tpmc-fix-error-patch-memory-leak.patch
> 
>  tpm
> 
> +w1-be-able-to-manually-add-and-remove-slaves-fix.patch
> 
>  Fix w1-be-able-to-manually-add-and-remove-slaves.patch
> 
> +gru-driver-minor-updates.patch
> +gru-driver-minor-updates-fix.patch
> 
>  GRU updates
> 
> +kernel-call-constructors-fix-3.patch
> -gcov-create-links-to-gcda-files-in-build-directory.patch
> +gcov-architecture-specific-compile-flag-adjustments-x86_64-fix-2.patch
> 
>  gcov
> 
> -resource-add-new-ioresource_clk-type-v2.patch
> -i2c-sh_mobile-ioresource_clk-support.patch
> 
>  Dropped
> 
> +byteorder-add-new-headers-for-make-headers-install.patch
> +byteorder-use-generic-c-version-for-value-byteswapping.patch
> 
>  byteorder
> 
> +ipc-semc-make-free_un-static.patch
> +make-fs-proc-proc_sysctlc-grab_header-static.patch
> +make-hp_wmi_notify-static.patch
> +make-kprobesc-kretprobe_table_lock-static.patch
> +acpi-use-bcd2bin-bin2bcd.patch
> +alpha-use-bcd2bin-bin2bcd.patch
> +cris-use-bcd2bin-bin2bcd.patch
> +drivers-rtc-use-bcd2bin-bin2bcd.patch
> +rtc-use-bcd2bin-bin2bcd.patch
> +mips-use-bcd2bin-bin2bcd.patch
> +mn10300-use-bcd2bin-bin2bcd.patch
> +i2c-use-bcd2bin-bin2bcd.patch
> +drivers-scsi-sr_vendorc-use-bcd2bin.patch
> +remove-the-obsolete-bcdbin-binbcd-macros.patch
> +include-linux-bcdh-remove-comments.patch
> +fs-kconfig-move-ext2-ext3-ext4-jbd-jbd2-out.patch
> +fs-kconfig-move-autofs-autofs4-out.patch
> +fs-kconfig-move-cifs-out.patch
> 
>  cleanups
> 
> +nilfs2-continuous-snapshotting-file-system.patch
> +nilfs2-continuous-snapshotting-file-system-fix.patch
> +nilfs2-continuous-snapshotting-file-system-fix-fix-2.patch
> 
>  New log-based fs
> 
> +reiser4-compile-warning-cleanups.patch
> +reiser4-use-wake_up_process-instead-of-wake_up-when-possible.patch
> +reiser4-track-upstream-changes.patch
> 
>  reiser4 fixes
> 
> 690 commits in 682 patch files
> 
> All patches:
> 
> ftp://ftp.kernel.org/pub/linux/kernel/people/akpm/patches/2.6/2.6.27-rc5/2.6.27-rc5-mm1/patch-list
> 
> --
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From anemo@mba.ocn.ne.jp Tue Sep  9 17:08:25 2008
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Date:	Wed, 10 Sep 2008 01:08:24 +0900 (JST)
Message-Id: <20080910.010824.07456636.anemo@mba.ocn.ne.jp>
To:	linux-mips@linux-mips.org
Cc:	linux-ide@vger.kernel.org,
	Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>,
	ralf@linux-mips.org, sshtylyov@ru.mvista.com
Subject: [PATCH 1/2] ide: Add tx4939ide driver
From:	Atsushi Nemoto <anemo@mba.ocn.ne.jp>
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This is the driver for the Toshiba TX4939 SoC ATA controller.

This controller has standard ATA taskfile registers and DMA
command/status registers, but the register layout is swapped on big
endian.  There are some other endian issue and some special registers
which requires many custom dma_ops/port_ops routines.

Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
---
This patch is against linux-next 20080905.

 drivers/ide/Kconfig          |    6 +
 drivers/ide/mips/Makefile    |    1 +
 drivers/ide/mips/tx4939ide.c |  762 ++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 769 insertions(+), 0 deletions(-)
 create mode 100644 drivers/ide/mips/tx4939ide.c

diff --git a/drivers/ide/Kconfig b/drivers/ide/Kconfig
index 325461c..0ed731a 100644
--- a/drivers/ide/Kconfig
+++ b/drivers/ide/Kconfig
@@ -736,6 +736,12 @@ config BLK_DEV_IDE_AU1XXX_SEQTS_PER_RQ
        default "128"
        depends on BLK_DEV_IDE_AU1XXX
 
+config BLK_DEV_IDE_TX4939
+	tristate "TX4939 internal IDE support"
+	depends on SOC_TX4939
+	select BLK_DEV_IDEDMA_SFF
+	select IDE_TIMINGS
+
 config IDE_ARM
 	tristate "ARM IDE support"
 	depends on ARM && (ARCH_CLPS7500 || ARCH_RPC || ARCH_SHARK)
diff --git a/drivers/ide/mips/Makefile b/drivers/ide/mips/Makefile
index 677c7b2..1e0ad98 100644
--- a/drivers/ide/mips/Makefile
+++ b/drivers/ide/mips/Makefile
@@ -1,4 +1,5 @@
 obj-$(CONFIG_BLK_DEV_IDE_SWARM)		+= swarm.o
 obj-$(CONFIG_BLK_DEV_IDE_AU1XXX)	+= au1xxx-ide.o
+obj-$(CONFIG_BLK_DEV_IDE_TX4939)	+= tx4939ide.o
 
 EXTRA_CFLAGS    := -Idrivers/ide
diff --git a/drivers/ide/mips/tx4939ide.c b/drivers/ide/mips/tx4939ide.c
new file mode 100644
index 0000000..ba9776d
--- /dev/null
+++ b/drivers/ide/mips/tx4939ide.c
@@ -0,0 +1,762 @@
+/*
+ * TX4939 internal IDE driver
+ * Based on RBTX49xx patch from CELF patch archive.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * (C) Copyright TOSHIBA CORPORATION 2005-2007
+ */
+
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/ide.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+
+#define MODNAME	"tx4939ide"
+
+/* ATA Shadow Registers (8bit except for DATA which is 16bit) */
+#define TX4939IDE_DATA	0x000
+#define TX4939IDE_Error_Ft	0x001
+#define TX4939IDE_Sec	0x002
+#define TX4939IDE_LBA0	0x003
+#define TX4939IDE_LBA1	0x004
+#define TX4939IDE_LBA2	0x005
+#define TX4939IDE_Device	0x006
+#define TX4939IDE_St_Cmd	0x007
+#define TX4939IDE_Alt_DevCtl	0x402
+/* H/W DMA Registers  */
+#define TX4939IDE_DMA_Cmd	0x800	/* 8bit */
+#define TX4939IDE_DMA_stat	0x802	/* 8bit */
+#define TX4939IDE_PRD_Ptr	0x804	/* 32bit */
+/* ATA100 CORE Registers (16bit) */
+#define TX4939IDE_Sys_Ctl	0xc00
+#define TX4939IDE_Xfer_Cnt_1	0xc08
+#define TX4939IDE_Xfer_Cnt_2	0xc0a
+#define TX4939IDE_Sec_Cnt	0xc10
+#define TX4939IDE_Strt_AddL	0xc18
+#define TX4939IDE_Strt_AddU	0xc20
+#define TX4939IDE_Add_Ctl	0xc28
+#define TX4939IDE_Lo_BCnt	0xc30
+#define TX4939IDE_Up_BCnt	0xc38
+#define TX4939IDE_PIO_Acc	0xc88
+#define TX4939IDE_H_Rst_Tim	0xc90
+#define TX4939IDE_int_ctl	0xc98
+#define TX4939IDE_Pkt_Cmd	0xcb8
+#define TX4939IDE_Bxfer_cntH	0xcc0
+#define TX4939IDE_Bxfer_cntL	0xcc8
+#define TX4939IDE_Dev_TErr	0xcd0
+#define TX4939IDE_Pkt_xfer_ct	0xcd8
+#define TX4939IDE_Strt_AddT	0xce0
+
+/* bits for int_ctl */
+#define TX4939IDE_INT_ADDRERR	0x80
+#define TX4939IDE_INT_REACHMUL	0x40
+#define TX4939IDE_INT_DEVTIMING	0x20
+#define TX4939IDE_INT_UDMATERM	0x10
+#define TX4939IDE_INT_TIMER	0x08
+#define TX4939IDE_INT_BUSERR	0x04
+#define TX4939IDE_INT_XFEREND	0x02
+#define TX4939IDE_INT_HOST	0x01
+
+#define TX4939IDE_IGNORE_INTS	\
+	(TX4939IDE_INT_ADDRERR | TX4939IDE_INT_REACHMUL | \
+	 TX4939IDE_INT_DEVTIMING | TX4939IDE_INT_UDMATERM | \
+	 TX4939IDE_INT_TIMER)
+
+#ifdef __BIG_ENDIAN
+#define TX4939IDE_REG32(reg)	(TX4939IDE_##reg ^ 4)
+#define TX4939IDE_REG16(reg)	(TX4939IDE_##reg ^ 6)
+#define TX4939IDE_REG8(reg)	(TX4939IDE_##reg ^ 7)
+#else
+#define TX4939IDE_REG32(reg)	(TX4939IDE_##reg)
+#define TX4939IDE_REG16(reg)	(TX4939IDE_##reg)
+#define TX4939IDE_REG8(reg)	(TX4939IDE_##reg)
+#endif
+
+#define TX4939IDE_readl(base, reg) \
+	__raw_readl((void __iomem *)((base) + TX4939IDE_REG32(reg)))
+#define TX4939IDE_readw(base, reg) \
+	__raw_readw((void __iomem *)((base) + TX4939IDE_REG16(reg)))
+#define TX4939IDE_readb(base, reg) \
+	__raw_readb((void __iomem *)((base) + TX4939IDE_REG8(reg)))
+#define TX4939IDE_writel(val, base, reg) \
+	__raw_writel(val, (void __iomem *)((base) + TX4939IDE_REG32(reg)))
+#define TX4939IDE_writew(val, base, reg) \
+	__raw_writew(val, (void __iomem *)((base) + TX4939IDE_REG16(reg)))
+#define TX4939IDE_writeb(val, base, reg) \
+	__raw_writeb(val, (void __iomem *)((base) + TX4939IDE_REG8(reg)))
+
+#define TX4939IDE_BASE(hwif)	((hwif)->io_ports.data_addr & ~0xfff)
+
+static void tx4939ide_set_mode(ide_drive_t *drive, const u8 speed)
+{
+	ide_hwif_t *hwif = HWIF(drive);
+	unsigned long base = TX4939IDE_BASE(hwif);
+	int is_slave = drive->dn & 1;
+	u16 value;
+	int safe_speed = speed;
+	int i;
+
+	for (i = 0; i < MAX_DRIVES; i++) {
+		if (drive != &hwif->drives[i] &&
+		    (hwif->drives[i].dev_flags & IDE_DFLAG_PRESENT))
+			safe_speed = min(safe_speed,
+					 (int)hwif->drives[i].current_speed);
+	}
+
+	/* Data Transfer Mode Select */
+	switch (speed) {
+	case XFER_UDMA_5:
+		value = 0x00d0;
+		break;
+	case XFER_UDMA_4:
+		value = 0x00c0;
+		break;
+	case XFER_UDMA_3:
+		value = 0x00b0;
+		break;
+	case XFER_UDMA_2:
+		value = 0x00a0;
+		break;
+	case XFER_UDMA_1:
+		value = 0x0090;
+		break;
+	case XFER_UDMA_0:
+		value = 0x0080;
+		break;
+	case XFER_MW_DMA_2:
+		value = 0x0070;
+		break;
+	case XFER_MW_DMA_1:
+		value = 0x0060;
+		break;
+	case XFER_MW_DMA_0:
+		value = 0x0050;
+		break;
+	case XFER_PIO_4:
+		value = 0x0040;
+		break;
+	case XFER_PIO_3:
+		value = 0x0030;
+		break;
+	case XFER_PIO_2:
+		value = 0x0020;
+		break;
+	case XFER_PIO_1:
+		value = 0x0010;
+		break;
+	default:
+	case XFER_PIO_0:
+		value = 0x0000;
+		break;
+	}
+	/* Command Transfer Mode Select */
+	switch (safe_speed) {
+	case XFER_UDMA_5:
+	case XFER_UDMA_4:
+	case XFER_UDMA_3:
+	case XFER_UDMA_2:
+	case XFER_UDMA_1:
+	case XFER_UDMA_0:
+	case XFER_MW_DMA_2:
+	case XFER_MW_DMA_1:
+	case XFER_MW_DMA_0:
+	case XFER_PIO_4:
+		value |= 0x0400;
+		break;
+	case XFER_PIO_3:
+		value |= 0x0300;
+		break;
+	case XFER_PIO_2:
+		value |= 0x0200;
+		break;
+	case XFER_PIO_1:
+		value |= 0x0100;
+		break;
+	default:
+	case XFER_PIO_0:
+		value |= 0x0000;
+		break;
+	}
+
+	if (is_slave)
+		hwif->select_data =
+			(hwif->select_data & ~0xffff0000) | (value << 16);
+	else
+		hwif->select_data = (hwif->select_data & ~0x0000ffff) | value;
+	TX4939IDE_writew(value, base, Sys_Ctl);
+}
+
+static void tx4939ide_set_pio_mode(ide_drive_t *drive, const u8 pio)
+{
+	tx4939ide_set_mode(drive, XFER_PIO_0 + pio);
+}
+
+static void tx4939ide_check_error_ints(ide_hwif_t *hwif, u16 stat)
+{
+	if (stat & TX4939IDE_INT_BUSERR) {
+		unsigned long base = TX4939IDE_BASE(hwif);
+		/* reset FIFO */
+		TX4939IDE_writew(TX4939IDE_readw(base, Sys_Ctl) |
+				 0x4000,
+				 base, Sys_Ctl);
+	}
+	if (stat & (TX4939IDE_INT_ADDRERR | TX4939IDE_INT_REACHMUL |
+		    TX4939IDE_INT_DEVTIMING | TX4939IDE_INT_BUSERR))
+		pr_err("%s: Error interrupt %#x (%s%s%s%s )\n",
+		       hwif->name, stat,
+		       (stat & TX4939IDE_INT_ADDRERR) ?
+		       " Address-Error" : "",
+		       (stat & TX4939IDE_INT_REACHMUL) ?
+		       " Reach-Multiple" : "",
+		       (stat & TX4939IDE_INT_DEVTIMING) ?
+		       " DEV-Timing" : "",
+		       (stat & TX4939IDE_INT_BUSERR) ?
+		       " Bus-Error" : "");
+}
+
+static void tx4939ide_clear_irq(ide_drive_t *drive)
+{
+	ide_hwif_t *hwif;
+	unsigned long base;
+	u16 ctl;
+
+	/*
+	 * tx4939ide_dma_test_irq() and tx4939ide_dma_end() do all
+	 * jobs for DMA case.
+	 */
+	if (drive->waiting_for_dma)
+		return;
+	hwif = HWIF(drive);
+	base = TX4939IDE_BASE(hwif);
+	ctl = TX4939IDE_readw(base, int_ctl);
+
+	tx4939ide_check_error_ints(hwif, ctl);
+	TX4939IDE_writew(ctl, base, int_ctl);
+}
+
+static u8 tx4939ide_cable_detect(ide_hwif_t *hwif)
+{
+	unsigned long base = TX4939IDE_BASE(hwif);
+
+	return (TX4939IDE_readw(base, Sys_Ctl) & 0x2000)
+		? ATA_CBL_PATA40 : ATA_CBL_PATA80;
+}
+
+static void tx4939ide_dma_host_set(ide_drive_t *drive, int on)
+{
+	ide_hwif_t *hwif	= HWIF(drive);
+	u8 unit			= drive->dn & 1;
+	unsigned long base = TX4939IDE_BASE(hwif);
+	u8 dma_stat = TX4939IDE_readb(base, DMA_stat);
+
+	if (on)
+		dma_stat |= (1 << (5 + unit));
+	else
+		dma_stat &= ~(1 << (5 + unit));
+
+	TX4939IDE_writeb(dma_stat, base, DMA_stat);
+}
+
+static int __tx4939ide_dma_setup(ide_drive_t *drive)
+{
+	ide_hwif_t *hwif = drive->hwif;
+	struct request *rq = HWGROUP(drive)->rq;
+	unsigned int reading;
+	u8 dma_stat;
+	unsigned long base = TX4939IDE_BASE(hwif);
+
+	if (rq_data_dir(rq))
+		reading = 0;
+	else
+		reading = 1 << 3;
+
+	/* fall back to pio! */
+	if (!ide_build_dmatable(drive, rq)) {
+		ide_map_sg(drive, rq);
+		return 1;
+	}
+#ifdef __BIG_ENDIAN
+	{
+		unsigned int *table = hwif->dmatable_cpu;
+		while (1) {
+			cpu_to_le64s((u64 *)table);
+			if (*table & 0x80000000)
+				break;
+			table += 2;
+		}
+	}
+#endif
+
+	/* PRD table */
+	TX4939IDE_writel(hwif->dmatable_dma, base, PRD_Ptr);
+
+	/* specify r/w */
+	TX4939IDE_writeb(reading, base, DMA_Cmd);
+
+	/* read DMA status for INTR & ERROR flags */
+	dma_stat = TX4939IDE_readb(base, DMA_stat);
+
+	/* clear INTR & ERROR flags */
+	TX4939IDE_writeb(dma_stat | 6, base, DMA_stat);
+	/* recover intmask cleared by writing to bit2 of DMA_stat */
+	TX4939IDE_writew(TX4939IDE_IGNORE_INTS << 8, base, int_ctl);
+
+	drive->waiting_for_dma = 1;
+	return 0;
+}
+
+static int tx4939ide_dma_setup(ide_drive_t *drive)
+{
+	ide_hwif_t *hwif = HWIF(drive);
+	unsigned long base = TX4939IDE_BASE(hwif);
+	int is_slave = drive->dn & 1;
+	unsigned int nframes;
+	int rc, i;
+	unsigned int sect_size = queue_hardsect_size(drive->queue);
+	u16 select_data;
+
+	select_data = (hwif->select_data >> (is_slave ? 16 : 0)) & 0xffff;
+	TX4939IDE_writew(select_data, base, Sys_Ctl);
+	if (is_slave)
+		TX4939IDE_writew(sect_size / 2, base, Xfer_Cnt_2);
+	else
+		TX4939IDE_writew(sect_size / 2, base, Xfer_Cnt_1);
+
+	rc = __tx4939ide_dma_setup(drive);
+	if (rc == 0) {
+		/* Number of sectors to transfer. */
+		nframes = 0;
+		for (i = 0; i < hwif->sg_nents; i++)
+			nframes += sg_dma_len(&hwif->sg_table[i]);
+		BUG_ON(nframes % sect_size != 0);
+		nframes /= sect_size;
+		BUG_ON(nframes == 0);
+		TX4939IDE_writew(nframes, base, Sec_Cnt);
+	}
+	return rc;
+}
+
+static void tx4939ide_dma_start(ide_drive_t *drive)
+{
+	ide_hwif_t *hwif = drive->hwif;
+	unsigned long base = TX4939IDE_BASE(hwif);
+	u8 dma_cmd;
+
+	/* Note that this is done *after* the cmd has
+	 * been issued to the drive, as per the BM-IDE spec.
+	 */
+	dma_cmd = TX4939IDE_readb(base, DMA_Cmd);
+	/* start DMA */
+	TX4939IDE_writeb(dma_cmd | 1, base, DMA_Cmd);
+
+	wmb();
+}
+
+static int tx4939ide_dma_end(ide_drive_t *drive)
+{
+	ide_hwif_t *hwif = drive->hwif;
+	u8 dma_stat = 0, dma_cmd = 0;
+	unsigned long base = TX4939IDE_BASE(hwif);
+	u16 ctl = TX4939IDE_readw(base, int_ctl);
+
+	drive->waiting_for_dma = 0;
+
+	/* get DMA command mode */
+	dma_cmd = TX4939IDE_readb(base, DMA_Cmd);
+	/* stop DMA */
+	TX4939IDE_writeb(dma_cmd & ~1, base, DMA_Cmd);
+
+	/* get DMA status */
+	dma_stat = TX4939IDE_readb(base, DMA_stat);
+
+	/* clear the INTR & ERROR bits */
+	TX4939IDE_writeb(dma_stat | 6, base, DMA_stat);
+	/* recover intmask cleared by writing to bit2 of DMA_stat */
+	TX4939IDE_writew(TX4939IDE_IGNORE_INTS << 8, base, int_ctl);
+
+	/* purge DMA mappings */
+	ide_destroy_dmatable(drive);
+	/* verify good DMA status */
+	wmb();
+
+	if ((dma_stat & 7) == 0 &&
+	    (ctl & (TX4939IDE_INT_XFEREND | TX4939IDE_INT_HOST)) ==
+	    (TX4939IDE_INT_XFEREND | TX4939IDE_INT_HOST))
+		/* INT_IDE lost... bug? */
+		return 0;
+	return (dma_stat & 7) != 4 ? (0x10 | dma_stat) : 0;
+}
+
+/* returns 1 if dma irq issued, 0 otherwise */
+static int tx4939ide_dma_test_irq(ide_drive_t *drive)
+{
+	ide_hwif_t *hwif = HWIF(drive);
+	unsigned long base = TX4939IDE_BASE(hwif);
+	u16 ctl = TX4939IDE_readw(base, int_ctl);
+	u8 dma_stat, stat;
+	u16 ide_int;
+	int found = 0;
+
+	tx4939ide_check_error_ints(hwif, ctl);
+	ide_int = ctl & (TX4939IDE_INT_XFEREND | TX4939IDE_INT_HOST);
+	switch (ide_int) {
+	case TX4939IDE_INT_HOST:
+		/* On error, XFEREND might not be asserted. */
+		stat = TX4939IDE_readb(base, Alt_DevCtl);
+		if ((stat & (ATA_BUSY|ATA_DRQ|ATA_ERR)) == ATA_ERR) {
+			pr_err("%s: detect error %x in %s\n",
+			       drive->name, stat, __func__);
+			found = 1;
+		}
+		/* FALLTHRU */
+	case TX4939IDE_INT_XFEREND:
+		/*
+		 * If only one of XFERINT and HOST was asserted, mask
+		 * this interrupt and wait for an another one.  Note
+		 * that write to bit2 of DMA_stat will clear all
+		 * mask bits.
+		 */
+		ctl |= ide_int << 8;
+		break;
+	case TX4939IDE_INT_HOST | TX4939IDE_INT_XFEREND:
+		dma_stat = TX4939IDE_readb(base, DMA_stat);
+		if (!(dma_stat & 4))
+			pr_debug("%s: weired interrupt status. "
+				 "DMA_stat %#02x int_ctl %#04x\n",
+				 hwif->name, dma_stat, ctl);
+		found = 1;
+		break;
+	}
+	/*
+	 * Do not clear XFERINT, HOST now.  They will be cleared by
+	 * clearing bit2 of DMA_stat.
+	 */
+	ctl &= ~ide_int;
+	TX4939IDE_writew(ctl, base, int_ctl);
+	return found;
+}
+
+static void tx4939ide_hwif_init(ide_hwif_t *hwif)
+{
+	unsigned long base = TX4939IDE_BASE(hwif);
+	int timeout;
+
+	/* Soft Reset */
+	TX4939IDE_writew(0x8000, base, Sys_Ctl);
+	mmiowb();
+	udelay(1);	/* at least 20 UPSCLK (100ns for 200MHz GBUSCLK) */
+	/* ATA Hard Reset */
+	TX4939IDE_writew(0x0800, base, Sys_Ctl);
+	timeout = 1000;
+	while (TX4939IDE_readw(base, Sys_Ctl) & 0x0800) {
+		if (timeout--)
+			break;
+		udelay(1);
+	}
+	/* mask some interrupts and clear all interrupts */
+	TX4939IDE_writew((TX4939IDE_IGNORE_INTS << 8) | 0xff, base, int_ctl);
+
+#ifdef __BIG_ENDIAN
+	/* This setting does not affect PRD fetch */
+	/* ByteSwap=1, Endian=00 */
+	TX4939IDE_writew(0xc911, base, Add_Ctl);
+#else
+	TX4939IDE_writew(0xc901, base, Add_Ctl);
+#endif
+
+	TX4939IDE_writew(0x0008, base, Lo_BCnt);
+	TX4939IDE_writew(0, base, Up_BCnt);
+}
+
+static int tx4939ide_init_dma(ide_hwif_t *hwif, const struct ide_port_info *d)
+{
+	return ide_allocate_dma_engine(hwif);
+}
+
+#ifdef __BIG_ENDIAN
+/* custom iops (independent from SWAP_IO_SPACE) */
+static u8 mm_inb(unsigned long port)
+{
+	return (u8)readb((void __iomem *)port);
+}
+static void mm_outb(u8 value, unsigned long port)
+{
+	writeb(value, (void __iomem *)port);
+}
+static void mm_tf_load(ide_drive_t *drive, ide_task_t *task)
+{
+	ide_hwif_t *hwif = drive->hwif;
+	struct ide_io_ports *io_ports = &hwif->io_ports;
+	struct ide_taskfile *tf = &task->tf;
+	u8 HIHI = (task->tf_flags & IDE_TFLAG_LBA48) ? 0xE0 : 0xEF;
+
+	if (task->tf_flags & IDE_TFLAG_FLAGGED)
+		HIHI = 0xFF;
+
+	if (task->tf_flags & IDE_TFLAG_OUT_DATA) {
+		u16 data = (tf->hob_data << 8) | tf->data;
+
+		__raw_writew(data, (void __iomem *)io_ports->data_addr);
+	}
+
+	if (task->tf_flags & IDE_TFLAG_OUT_HOB_FEATURE)
+		mm_outb(tf->hob_feature, io_ports->feature_addr);
+	if (task->tf_flags & IDE_TFLAG_OUT_HOB_NSECT)
+		mm_outb(tf->hob_nsect, io_ports->nsect_addr);
+	if (task->tf_flags & IDE_TFLAG_OUT_HOB_LBAL)
+		mm_outb(tf->hob_lbal, io_ports->lbal_addr);
+	if (task->tf_flags & IDE_TFLAG_OUT_HOB_LBAM)
+		mm_outb(tf->hob_lbam, io_ports->lbam_addr);
+	if (task->tf_flags & IDE_TFLAG_OUT_HOB_LBAH)
+		mm_outb(tf->hob_lbah, io_ports->lbah_addr);
+
+	if (task->tf_flags & IDE_TFLAG_OUT_FEATURE)
+		mm_outb(tf->feature, io_ports->feature_addr);
+	if (task->tf_flags & IDE_TFLAG_OUT_NSECT)
+		mm_outb(tf->nsect, io_ports->nsect_addr);
+	if (task->tf_flags & IDE_TFLAG_OUT_LBAL)
+		mm_outb(tf->lbal, io_ports->lbal_addr);
+	if (task->tf_flags & IDE_TFLAG_OUT_LBAM)
+		mm_outb(tf->lbam, io_ports->lbam_addr);
+	if (task->tf_flags & IDE_TFLAG_OUT_LBAH)
+		mm_outb(tf->lbah, io_ports->lbah_addr);
+
+	if (task->tf_flags & IDE_TFLAG_OUT_DEVICE) {
+		unsigned long base = TX4939IDE_BASE(hwif);
+		mm_outb((tf->device & HIHI) | drive->select,
+			 io_ports->device_addr);
+		/* Fix ATA100 CORE System Control Register */
+		TX4939IDE_writew(TX4939IDE_readw(base, Sys_Ctl) & 0x07f0,
+				 base, Sys_Ctl);
+	}
+}
+static void mm_tf_read(ide_drive_t *drive, ide_task_t *task)
+{
+	ide_hwif_t *hwif = drive->hwif;
+	struct ide_io_ports *io_ports = &hwif->io_ports;
+	struct ide_taskfile *tf = &task->tf;
+
+	if (task->tf_flags & IDE_TFLAG_IN_DATA) {
+		u16 data;
+
+		data = __raw_readw((void __iomem *)io_ports->data_addr);
+		tf->data = data & 0xff;
+		tf->hob_data = (data >> 8) & 0xff;
+	}
+
+	/* be sure we're looking at the low order bits */
+	mm_outb(ATA_DEVCTL_OBS & ~0x80, io_ports->ctl_addr);
+
+	if (task->tf_flags & IDE_TFLAG_IN_FEATURE)
+		tf->feature = mm_inb(io_ports->feature_addr);
+	if (task->tf_flags & IDE_TFLAG_IN_NSECT)
+		tf->nsect  = mm_inb(io_ports->nsect_addr);
+	if (task->tf_flags & IDE_TFLAG_IN_LBAL)
+		tf->lbal   = mm_inb(io_ports->lbal_addr);
+	if (task->tf_flags & IDE_TFLAG_IN_LBAM)
+		tf->lbam   = mm_inb(io_ports->lbam_addr);
+	if (task->tf_flags & IDE_TFLAG_IN_LBAH)
+		tf->lbah   = mm_inb(io_ports->lbah_addr);
+	if (task->tf_flags & IDE_TFLAG_IN_DEVICE)
+		tf->device = mm_inb(io_ports->device_addr);
+
+	if (task->tf_flags & IDE_TFLAG_LBA48) {
+		mm_outb(ATA_DEVCTL_OBS | 0x80, io_ports->ctl_addr);
+
+		if (task->tf_flags & IDE_TFLAG_IN_HOB_FEATURE)
+			tf->hob_feature = mm_inb(io_ports->feature_addr);
+		if (task->tf_flags & IDE_TFLAG_IN_HOB_NSECT)
+			tf->hob_nsect   = mm_inb(io_ports->nsect_addr);
+		if (task->tf_flags & IDE_TFLAG_IN_HOB_LBAL)
+			tf->hob_lbal    = mm_inb(io_ports->lbal_addr);
+		if (task->tf_flags & IDE_TFLAG_IN_HOB_LBAM)
+			tf->hob_lbam    = mm_inb(io_ports->lbam_addr);
+		if (task->tf_flags & IDE_TFLAG_IN_HOB_LBAH)
+			tf->hob_lbah    = mm_inb(io_ports->lbah_addr);
+	}
+}
+
+static void mm_insw_swap(unsigned long port, void *addr, u32 count)
+{
+	unsigned short *ptr = addr;
+	unsigned long size = count * 2;
+	port &= ~1;
+	while (count--)
+		*ptr++ = le16_to_cpu(__raw_readw((void __iomem *)port));
+	__ide_flush_dcache_range((unsigned long)addr, size);
+}
+static void mm_outsw_swap(unsigned long port, void *addr, u32 count)
+{
+	unsigned short *ptr = addr;
+	unsigned long size = count * 2;
+	port &= ~1;
+	while (count--) {
+		__raw_writew(cpu_to_le16(*ptr), (void __iomem *)port);
+		ptr++;
+	}
+	__ide_flush_dcache_range((unsigned long)addr, size);
+}
+static void mmio_input_data_swap(ide_drive_t *drive, struct request *rq,
+				 void *buf, unsigned int len)
+{
+	mm_insw_swap(drive->hwif->io_ports.data_addr, buf, (len + 1) / 2);
+}
+static void mmio_output_data_swap(ide_drive_t *drive, struct request *rq,
+				  void *buf, unsigned int len)
+{
+	mm_outsw_swap(drive->hwif->io_ports.data_addr, buf, (len + 1) / 2);
+}
+
+static u8 tx4939ide_read_sff_dma_status(ide_hwif_t *hwif)
+{
+	unsigned long base = TX4939IDE_BASE(hwif);
+	return TX4939IDE_readb(base, DMA_stat);
+}
+
+static const struct ide_tp_ops tx4939ide_tp_ops = {
+	.exec_command		= ide_exec_command,
+	.read_status		= ide_read_status,
+	.read_altstatus		= ide_read_altstatus,
+	.read_sff_dma_status	= tx4939ide_read_sff_dma_status,
+
+	.set_irq		= ide_set_irq,
+
+	.tf_load		= mm_tf_load,
+	.tf_read		= mm_tf_read,
+
+	.input_data		= mmio_input_data_swap,
+	.output_data		= mmio_output_data_swap,
+};
+#endif	/* __BIG_ENDIAN */
+
+static const struct ide_port_ops tx4939ide_port_ops = {
+	.set_pio_mode = tx4939ide_set_pio_mode,
+	.set_dma_mode = tx4939ide_set_mode,
+	.clear_irq = tx4939ide_clear_irq,
+	.cable_detect = tx4939ide_cable_detect,
+};
+
+static const struct ide_dma_ops tx4939ide_dma_ops = {
+	.dma_host_set = tx4939ide_dma_host_set,
+	.dma_setup = tx4939ide_dma_setup,
+	.dma_exec_cmd = ide_dma_exec_cmd,
+	.dma_start = tx4939ide_dma_start,
+	.dma_end = tx4939ide_dma_end,
+	.dma_test_irq = tx4939ide_dma_test_irq,
+	.dma_lost_irq = ide_dma_lost_irq,
+	.dma_timeout = ide_dma_timeout,
+};
+
+static const struct ide_port_info tx4939ide_port_info __initdata = {
+	.init_hwif = tx4939ide_hwif_init,
+	.init_dma = tx4939ide_init_dma,
+	.port_ops = &tx4939ide_port_ops,
+	.dma_ops = &tx4939ide_dma_ops,
+#ifdef __BIG_ENDIAN
+	.tp_ops = &tx4939ide_tp_ops,
+#endif
+	.host_flags = IDE_HFLAG_MMIO,
+	.pio_mask = ATA_PIO4,
+	.mwdma_mask = ATA_MWDMA2,
+	.swdma_mask = ATA_SWDMA2,
+	.udma_mask = ATA_UDMA5,
+};
+
+static int __init tx4939ide_probe(struct platform_device *pdev)
+{
+	hw_regs_t hw;
+	hw_regs_t *hws[] = { &hw, NULL, NULL, NULL };
+	struct ide_host *host;
+	struct resource *res;
+	int irq;
+	unsigned long mapbase;
+	int ret;
+
+	irq = platform_get_irq(pdev, 0);
+	if (irq < 0)
+		return -ENODEV;
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res)
+		return -ENODEV;
+
+	mapbase = (unsigned long)devm_ioremap(&pdev->dev, res->start,
+					      res->end - res->start + 1);
+	if (!mapbase)
+		return -EBUSY;
+	memset(&hw, 0, sizeof(hw));
+	hw.io_ports.data_addr = mapbase + TX4939IDE_REG8(DATA);
+	hw.io_ports.error_addr = mapbase + TX4939IDE_REG8(Error_Ft);
+	hw.io_ports.nsect_addr = mapbase + TX4939IDE_REG8(Sec);
+	hw.io_ports.lbal_addr = mapbase + TX4939IDE_REG8(LBA0);
+	hw.io_ports.lbam_addr = mapbase + TX4939IDE_REG8(LBA1);
+	hw.io_ports.lbah_addr = mapbase + TX4939IDE_REG8(LBA2);
+	hw.io_ports.device_addr = mapbase + TX4939IDE_REG8(Device);
+	hw.io_ports.command_addr = mapbase + TX4939IDE_REG8(St_Cmd);
+	hw.io_ports.ctl_addr = mapbase + TX4939IDE_REG8(Alt_DevCtl);
+	hw.irq = irq;
+	hw.dev = &pdev->dev;
+
+	pr_info("TX4939 IDE interface (%lx,%d)\n", mapbase, irq);
+	ret = ide_host_add(&tx4939ide_port_info, hws, &host);
+	if (ret)
+		return ret;
+	platform_set_drvdata(pdev, host);
+	return 0;
+}
+
+static int __exit tx4939ide_remove(struct platform_device *pdev)
+{
+	struct ide_host *host = platform_get_drvdata(pdev);
+
+	ide_host_remove(host);
+	return 0;
+}
+
+#ifdef CONFIG_PM
+static int tx4939ide_resume(struct platform_device *dev)
+{
+	struct ide_host *host = platform_get_drvdata(dev);
+	ide_hwif_t *hwif = host->ports[0];
+	unsigned long base = TX4939IDE_BASE(hwif);
+
+	tx4939ide_hwif_init(hwif);
+
+	/* restore Sys_Ctl */
+	TX4939IDE_writew(hwif->select_data & 0xffff, base, Sys_Ctl);
+	return 0;
+}
+#else
+#define tx4939ide_resume	NULL
+#endif
+
+static struct platform_driver tx4939ide_driver = {
+	.driver = {
+		.name = MODNAME,
+		.owner = THIS_MODULE,
+	},
+	.remove = __exit_p(tx4939ide_remove),
+	.resume = tx4939ide_resume,
+};
+
+static int __init tx4939ide_init(void)
+{
+	return platform_driver_probe(&tx4939ide_driver, tx4939ide_probe);
+}
+
+static void __exit tx4939ide_exit(void)
+{
+	platform_driver_unregister(&tx4939ide_driver);
+}
+
+module_init(tx4939ide_init);
+module_exit(tx4939ide_exit);
+
+MODULE_DESCRIPTION("TX4939 internal IDE driver");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:tx4939ide");
-- 
1.5.6.3


From anemo@mba.ocn.ne.jp Tue Sep  9 17:08:44 2008
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	Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>,
	ralf@linux-mips.org, sshtylyov@ru.mvista.com
Subject: [PATCH 2/2] TXx9: Add TX4939 ATA support
From:	Atsushi Nemoto <anemo@mba.ocn.ne.jp>
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Add a helper routine to register tx4939ide driver and use it on
RBTX4939 board.

Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
---
This patch is against linux-next 20080905.

 arch/mips/txx9/generic/setup_tx4939.c |   29 +++++++++++++++++++++++++++++
 arch/mips/txx9/rbtx4939/setup.c       |    1 +
 include/asm-mips/txx9/tx4939.h        |    1 +
 3 files changed, 31 insertions(+), 0 deletions(-)

diff --git a/arch/mips/txx9/generic/setup_tx4939.c b/arch/mips/txx9/generic/setup_tx4939.c
index f14a497..ee00bde 100644
--- a/arch/mips/txx9/generic/setup_tx4939.c
+++ b/arch/mips/txx9/generic/setup_tx4939.c
@@ -20,6 +20,7 @@
 #include <linux/param.h>
 #include <linux/ptrace.h>
 #include <linux/mtd/physmap.h>
+#include <linux/platform_device.h>
 #include <asm/bootinfo.h>
 #include <asm/reboot.h>
 #include <asm/traps.h>
@@ -389,6 +390,34 @@ void __init tx4939_mtd_init(int ch)
 	txx9_physmap_flash_init(ch, start, size, &pdata);
 }
 
+void __init tx4939_ata_init(void)
+{
+	__u64 pcfg = __raw_readq(&tx4939_ccfgptr->pcfg);
+	if (pcfg & (TX4939_PCFG_ATA0MODE | TX4939_PCFG_ATA1MODE)) {
+		struct resource res[2];
+		int i;
+		memset(res, 0, sizeof(res));
+		for (i = 0; i < 2; i++) {
+			if (i == 0 &&
+			    !(pcfg & TX4939_PCFG_ATA0MODE))
+				continue;
+			if (i == 1 &&
+			    (pcfg & (TX4939_PCFG_ATA1MODE |
+				     TX4939_PCFG_ET1MODE |
+				     TX4939_PCFG_ET0MODE)) !=
+			    TX4939_PCFG_ATA1MODE)
+				continue;
+			res[0].start = TX4939_ATA_REG(i) & 0xfffffffffULL;
+			res[0].end = res[0].start + 0x1000 - 1;
+			res[0].flags = IORESOURCE_MEM;
+			res[1].start = TXX9_IRQ_BASE + TX4939_IR_ATA(i);
+			res[1].flags = IORESOURCE_IRQ;
+			platform_device_register_simple("tx4939ide", i,
+							res, ARRAY_SIZE(res));
+		}
+	}
+}
+
 static void __init tx4939_stop_unused_modules(void)
 {
 	__u64 pcfg, rst = 0, ckd = 0;
diff --git a/arch/mips/txx9/rbtx4939/setup.c b/arch/mips/txx9/rbtx4939/setup.c
index 277864d..9855d7b 100644
--- a/arch/mips/txx9/rbtx4939/setup.c
+++ b/arch/mips/txx9/rbtx4939/setup.c
@@ -264,6 +264,7 @@ static void __init rbtx4939_device_init(void)
 #endif
 	rbtx4939_led_setup();
 	tx4939_wdt_init();
+	tx4939_ata_init();
 }
 
 static void __init rbtx4939_setup(void)
diff --git a/include/asm-mips/txx9/tx4939.h b/include/asm-mips/txx9/tx4939.h
index 7ce2dff..88badb4 100644
--- a/include/asm-mips/txx9/tx4939.h
+++ b/include/asm-mips/txx9/tx4939.h
@@ -540,5 +540,6 @@ void tx4939_setup_pcierr_irq(void);
 void tx4939_irq_init(void);
 int tx4939_irq(void);
 void tx4939_mtd_init(int ch);
+void tx4939_ata_init(void);
 
 #endif /* __ASM_TXX9_TX4939_H */
-- 
1.5.6.3


From alan@lxorguk.ukuu.org.uk Tue Sep  9 17:45:14 2008
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Date:	Tue, 9 Sep 2008 17:44:59 +0100
From:	Alan Cox <alan@lxorguk.ukuu.org.uk>
To:	Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Cc:	linux-mips@linux-mips.org, linux-ide@vger.kernel.org,
	Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>,
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Subject: Re: [PATCH 1/2] ide: Add tx4939ide driver
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> command/status registers, but the register layout is swapped on big
> endian.  There are some other endian issue and some special registers
> which requires many custom dma_ops/port_ops routines.

It would probably be a lot cleaner using the libata framework, and also
go obsolete less soon.

> +#define TX4939IDE_readl(base, reg) \
> +	__raw_readl((void __iomem *)((base) + TX4939IDE_REG32(reg)))
> +#define TX4939IDE_readw(base, reg) \
> +	__raw_readw((void __iomem *)((base) + TX4939IDE_REG16(reg)))
> +#define TX4939IDE_readb(base, reg) \
> +	__raw_readb((void __iomem *)((base) + TX4939IDE_REG8(reg)))
> +#define TX4939IDE_writel(val, base, reg) \
> +	__raw_writel(val, (void __iomem *)((base) + TX4939IDE_REG32(reg)))
> +#define TX4939IDE_writew(val, base, reg) \
> +	__raw_writew(val, (void __iomem *)((base) + TX4939IDE_REG16(reg)))
> +#define TX4939IDE_writeb(val, base, reg) \
> +	__raw_writeb(val, (void __iomem *)((base) + TX4939IDE_REG8(reg)))

It's generally frowned upon to hide all the detail in macros, it is much
easier to read and understand the code if you don't do this.

> +#define TX4939IDE_BASE(hwif)	((hwif)->io_ports.data_addr & ~0xfff)

Why do you have void __iomem casts all over the write methods not in the
_BASE() method - that would let sparse do its job properly

> +	for (i = 0; i < MAX_DRIVES; i++) {
> +		if (drive != &hwif->drives[i] &&

You don't actually need the first test. This also appears wrong. In your
tests MW_DMA_0 is 'faster' than PIO4 but in fact MW_DMA_0 PIO timings are
*slower* than PIO4 so the mode is not in fact slower.

> +	case XFER_MW_DMA_2:
> +	case XFER_MW_DMA_1:
> +	case XFER_MW_DMA_0:
> +	case XFER_PIO_4:
> +		value |= 0x0400;
> +		break;

This looks odd according to the speed tables. Can you clarify what is
going on ?

> +#ifdef __BIG_ENDIAN
> +	{
> +		unsigned int *table = hwif->dmatable_cpu;
> +		while (1) {
> +			cpu_to_le64s((u64 *)table);
> +			if (*table & 0x80000000)
> +				break;

You modify the table but you never ensure the data is not still in
temporary variables from the compiler or flushed from cache


From sshtylyov@ru.mvista.com Tue Sep  9 18:07:41 2008
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	linux-ide@vger.kernel.org,
	Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>,
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Subject: Re: [PATCH 1/2] ide: Add tx4939ide driver
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Hello.

Alan Cox wrote:

>>+#define TX4939IDE_readl(base, reg) \
>>+	__raw_readl((void __iomem *)((base) + TX4939IDE_REG32(reg)))
>>+#define TX4939IDE_readw(base, reg) \
>>+	__raw_readw((void __iomem *)((base) + TX4939IDE_REG16(reg)))
>>+#define TX4939IDE_readb(base, reg) \
>>+	__raw_readb((void __iomem *)((base) + TX4939IDE_REG8(reg)))
>>+#define TX4939IDE_writel(val, base, reg) \
>>+	__raw_writel(val, (void __iomem *)((base) + TX4939IDE_REG32(reg)))
>>+#define TX4939IDE_writew(val, base, reg) \
>>+	__raw_writew(val, (void __iomem *)((base) + TX4939IDE_REG16(reg)))
>>+#define TX4939IDE_writeb(val, base, reg) \
>>+	__raw_writeb(val, (void __iomem *)((base) + TX4939IDE_REG8(reg)))

> It's generally frowned upon to hide all the detail in macros, it is much
> easier to read and understand the code if you don't do this.

>>+#define TX4939IDE_BASE(hwif)	((hwif)->io_ports.data_addr & ~0xfff)

> Why do you have void __iomem casts all over the write methods not in the
> _BASE() method - that would let sparse do its job properly

    I don't get why there's need for & at all -- isn't IDE data register 
address always on 4K boundary?

>>+	for (i = 0; i < MAX_DRIVES; i++) {
>>+		if (drive != &hwif->drives[i] &&

> You don't actually need the first test.

    No, he does need it -- in order not to clamp the new PIO mode based on the 
previosly selected one. Although, one should call ide_get_paired_drive() ISO 
this loop.

> This also appears wrong. In your
> tests MW_DMA_0 is 'faster' than PIO4 but in fact MW_DMA_0 PIO timings are
> *slower* than PIO4 so the mode is not in fact slower.

    I don't think it's about the DMA timings at all. Though indeed, MWDMA0/1 
do (iff it's drive's max) implies slower max PIO mode than PIO4.

>>+	case XFER_MW_DMA_2:
>>+	case XFER_MW_DMA_1:
>>+	case XFER_MW_DMA_0:
>>+	case XFER_PIO_4:
>>+		value |= 0x0400;
>>+		break;

> This looks odd according to the speed tables. Can you clarify what is
> going on ?

    This apparently selects the command PIO timing safest for both drives but 
does this incorrectly -- the current DMA (or even PIO) mode shouldn't be a 
part of the equation.  There are several examples how to do this including 
siimage.c and cs5535.c...

MBR, Sergei

From sshtylyov@ru.mvista.com Tue Sep  9 18:49:54 2008
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Atsushi Nemoto wrote:
> This is the driver for the Toshiba TX4939 SoC ATA controller.

> This controller has standard ATA taskfile registers and DMA
> command/status registers, but the register layout is swapped on big
> endian.  There are some other endian issue and some special registers
> which requires many custom dma_ops/port_ops routines.

> Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
> ---
> This patch is against linux-next 20080905.

>  drivers/ide/Kconfig          |    6 +
>  drivers/ide/mips/Makefile    |    1 +
>  drivers/ide/mips/tx4939ide.c |  762 ++++++++++++++++++++++++++++++++++++++++++
>  3 files changed, 769 insertions(+), 0 deletions(-)
>  create mode 100644 drivers/ide/mips/tx4939ide.c

> diff --git a/drivers/ide/mips/tx4939ide.c b/drivers/ide/mips/tx4939ide.c
> new file mode 100644
> index 0000000..ba9776d
> --- /dev/null
> +++ b/drivers/ide/mips/tx4939ide.c
> @@ -0,0 +1,762 @@

[...]

> +static void tx4939ide_set_mode(ide_drive_t *drive, const u8 speed)
> +{
> +	ide_hwif_t *hwif = HWIF(drive);
> +	unsigned long base = TX4939IDE_BASE(hwif);
> +	int is_slave = drive->dn & 1;
> +	u16 value;
> +	int safe_speed = speed;
> +	int i;
> +
> +	for (i = 0; i < MAX_DRIVES; i++) {

    Use ide_get_paired_drive() ISO this loop.

> +		if (drive != &hwif->drives[i] &&
> +		    (hwif->drives[i].dev_flags & IDE_DFLAG_PRESENT))
> +			safe_speed = min(safe_speed,
> +					 (int)hwif->drives[i].current_speed);

    You shouldn't clamp the command PIO mode timings like this, and shouldn't 
do it at all when DMA mode is set. Call ide_get_best_pio_mode(255, 4) to get 
the mate drive's fastest PIO mode which should be a clamping value.

> +	/* Command Transfer Mode Select */
> +	switch (safe_speed) {
> +	case XFER_UDMA_5:
> +	case XFER_UDMA_4:
> +	case XFER_UDMA_3:
> +	case XFER_UDMA_2:
> +	case XFER_UDMA_1:
> +	case XFER_UDMA_0:
> +	case XFER_MW_DMA_2:

    You shouldn't change the command PIO mode when DMA mode is selected.

> +	case XFER_MW_DMA_1:
> +	case XFER_MW_DMA_0:
> +	case XFER_PIO_4:

    MWDMA0/1 timings don't match PIO4, they are [much] slower.

> +		value |= 0x0400;
> +		break;
> +	case XFER_PIO_3:
> +		value |= 0x0300;
> +		break;
> +	case XFER_PIO_2:
> +		value |= 0x0200;
> +		break;
> +	case XFER_PIO_1:
> +		value |= 0x0100;
> +		break;
> +	default:
> +	case XFER_PIO_0:
> +		value |= 0x0000;
> +		break;
> +	}
 > +
> +	if (is_slave)
> +		hwif->select_data =
> +			(hwif->select_data & ~0xffff0000) | (value << 16);

    Why not just 0x0000ffff?

> +	else
> +		hwif->select_data = (hwif->select_data & ~0x0000ffff) | value;

    Why not just 0xffff0000?

> +	TX4939IDE_writew(value, base, Sys_Ctl);
> +}
> +
> +static void tx4939ide_set_pio_mode(ide_drive_t *drive, const u8 pio)
> +{
> +	tx4939ide_set_mode(drive, XFER_PIO_0 + pio);
> +}

    I suggest that you implement tx4939ide_set_{dma|pio}_mode() as seperate 
functions, possibly using a common function to do a final part. These 2 
methods are quite different functionally.

> +
> +static void tx4939ide_check_error_ints(ide_hwif_t *hwif, u16 stat)
> +{
> +	if (stat & TX4939IDE_INT_BUSERR) {
> +		unsigned long base = TX4939IDE_BASE(hwif);
> +		/* reset FIFO */
> +		TX4939IDE_writew(TX4939IDE_readw(base, Sys_Ctl) |
> +				 0x4000,
> +				 base, Sys_Ctl);
> +	}
> +	if (stat & (TX4939IDE_INT_ADDRERR | TX4939IDE_INT_REACHMUL |
> +		    TX4939IDE_INT_DEVTIMING | TX4939IDE_INT_BUSERR))
> +		pr_err("%s: Error interrupt %#x (%s%s%s%s )\n",
> +		       hwif->name, stat,
> +		       (stat & TX4939IDE_INT_ADDRERR) ?
> +		       " Address-Error" : "",
> +		       (stat & TX4939IDE_INT_REACHMUL) ?
> +		       " Reach-Multiple" : "",
> +		       (stat & TX4939IDE_INT_DEVTIMING) ?
> +		       " DEV-Timing" : "",
> +		       (stat & TX4939IDE_INT_BUSERR) ?
> +		       " Bus-Error" : "");
> +}
> +
> +static void tx4939ide_clear_irq(ide_drive_t *drive)
> +{
> +	ide_hwif_t *hwif;
> +	unsigned long base;
> +	u16 ctl;
> +
> +	/*
> +	 * tx4939ide_dma_test_irq() and tx4939ide_dma_end() do all
> +	 * jobs for DMA case.
> +	 */
> +	if (drive->waiting_for_dma)
> +		return;
> +	hwif = HWIF(drive);
> +	base = TX4939IDE_BASE(hwif);
> +	ctl = TX4939IDE_readw(base, int_ctl);
> +
> +	tx4939ide_check_error_ints(hwif, ctl);
> +	TX4939IDE_writew(ctl, base, int_ctl);
> +}
> +
> +static int tx4939ide_dma_setup(ide_drive_t *drive)
> +{
> +	ide_hwif_t *hwif = HWIF(drive);
> +	unsigned long base = TX4939IDE_BASE(hwif);
> +	int is_slave = drive->dn & 1;
> +	unsigned int nframes;
> +	int rc, i;
> +	unsigned int sect_size = queue_hardsect_size(drive->queue);
> +	u16 select_data;
> +
> +	select_data = (hwif->select_data >> (is_slave ? 16 : 0)) & 0xffff;
> +	TX4939IDE_writew(select_data, base, Sys_Ctl);

    Unfortunately, programming the timings from the dma_setup() method isn't 
enough since it won't be called for PIO transfers.  You'll have to use the 
selectproc() method.

MBR, Sergei

From kevink@paralogos.com Tue Sep  9 21:31:51 2008
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I've managed to steal enough time to rework the SMTC support
for the MIPS 34K (and, I suppose 1004K) processors so that it
works again near the head of the source tree.  This involved
a complete rework of the clocking model to be compatible with
new common timing event system, which finally enables "tickless"
operation in SMTC, something it needed pretty badly.  I also
solved the problem with using the "wait_irqoff" idle loop
under SMTC.

There are going to be three patches that will follow.  The
first two are relatively localized fixes to problems with
FPU affinity and with IPI replay that I came across in testing
the new code.  The last is a pretty big patch, but it all
pretty much hangs together and I couldn't see any sensible
way to partition it.

	Regards,

	Kevin K.

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From 7c2d12934d74cb5e97a4c3083b38e79d597e9b31 Mon Sep 17 00:00:00 2001
From: Kevin D. Kissell <kevink@paralogos.com>
Date: Tue, 9 Sep 2008 21:33:36 +0200
Subject: [PATCH] Fixed holes in SMTC and FPU affinity support.
 Signed-off-by: Kevin D. Kissell <kevink@paralogos.com>
Content-Length: 1671
Lines: 48

---
 arch/mips/kernel/process.c |   19 ++++++++++++-------
 1 files changed, 12 insertions(+), 7 deletions(-)

diff --git a/arch/mips/kernel/process.c b/arch/mips/kernel/process.c
index 2c09a44..75277c8 100644
--- a/arch/mips/kernel/process.c
+++ b/arch/mips/kernel/process.c
@@ -55,7 +55,7 @@ void __noreturn cpu_idle(void)
 	while (1) {
 		tick_nohz_stop_sched_tick();
 		while (!need_resched()) {
-#ifdef CONFIG_SMTC_IDLE_HOOK_DEBUG
+#ifdef CONFIG_MIPS_MT_SMTC
 			extern void smtc_idle_loop_hook(void);
 
 			smtc_idle_loop_hook();
@@ -155,14 +155,19 @@ int copy_thread(int nr, unsigned long clone_flags, unsigned long usp,
 	clear_tsk_thread_flag(p, TIF_USEDFPU);
 
 #ifdef CONFIG_MIPS_MT_FPAFF
+	clear_tsk_thread_flag(p, TIF_FPUBOUND);
 	/*
-	 * FPU affinity support is cleaner if we track the
-	 * user-visible CPU affinity from the very beginning.
-	 * The generic cpus_allowed mask will already have
-	 * been copied from the parent before copy_thread
-	 * is invoked.
+	 * FPU affinity support requires that we be subtle.
+	 * The basic fork support code will have copied
+	 * the parent's cpus_allowed set, but what the child
+	 * needs to inherit is the "user" version, which
+	 * carries the program/user controlled CPU affinity
+	 * properties that are supposed to be inherited,
+	 * but not the transient, overlayed, hardware
+	 * affinity constraints.
 	 */
-	p->thread.user_cpus_allowed = p->cpus_allowed;
+	p->thread.user_cpus_allowed = current->thread.user_cpus_allowed;
+	p->cpus_allowed = current->thread.user_cpus_allowed;
 #endif /* CONFIG_MIPS_MT_FPAFF */
 
 	if (clone_flags & CLONE_SETTLS)
-- 
1.5.3.3


--------------040406000605030509060700--

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From ac801c3b5c31eb0d53bf08538965f82f59f5f39d Mon Sep 17 00:00:00 2001
From: Kevin D. Kissell <kevink@paralogos.com>
Date: Tue, 9 Sep 2008 21:48:52 +0200
Subject: [PATCH] Rework of SMTC support to make it work with the new clock event
 system, allowing "tickless" operation, and to make it compatible
 with the use of the "wait_irqoff" idle loop.  The new clocking
 scheme means that the previously optional IPI instant replay
 mechanism is now required, and has been made more robust.
 Signed-off-by: Kevin D. Kissell <kevink@paralogos.com>
Content-Length: 40528
Lines: 1367

---
 arch/mips/Kconfig                        |   26 +--
 arch/mips/kernel/Makefile                |    1 +
 arch/mips/kernel/cevt-r4k.c              |  173 +++++------------
 arch/mips/kernel/cevt-smtc.c             |  321 ++++++++++++++++++++++++++++++
 arch/mips/kernel/cpu-probe.c             |   10 +-
 arch/mips/kernel/genex.S                 |    4 +-
 arch/mips/kernel/smtc.c                  |  254 +++++++++++++-----------
 arch/mips/mips-boards/malta/malta_smtc.c |    9 +-
 include/asm-mips/cevt-r4k.h              |   46 +++++
 include/asm-mips/irqflags.h              |   26 ++-
 include/asm-mips/smtc.h                  |    8 +-
 11 files changed, 598 insertions(+), 280 deletions(-)
 create mode 100644 arch/mips/kernel/cevt-smtc.c
 create mode 100644 include/asm-mips/cevt-r4k.h

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 24c5dee..30e6cdd 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -1496,7 +1496,6 @@ config MIPS_MT_SMTC
 	depends on CPU_MIPS32_R2
 	#depends on CPU_MIPS64_R2		# once there is hardware ...
 	depends on SYS_SUPPORTS_MULTITHREADING
-	select GENERIC_CLOCKEVENTS_BROADCAST
 	select CPU_MIPSR2_IRQ_VI
 	select CPU_MIPSR2_IRQ_EI
 	select MIPS_MT
@@ -1544,32 +1543,17 @@ config MIPS_VPE_LOADER
 	  Includes a loader for loading an elf relocatable object
 	  onto another VPE and running it.
 
-config MIPS_MT_SMTC_INSTANT_REPLAY
-	bool "Low-latency Dispatch of Deferred SMTC IPIs"
-	depends on MIPS_MT_SMTC && !PREEMPT
-	default y
-	help
-	  SMTC pseudo-interrupts between TCs are deferred and queued
-	  if the target TC is interrupt-inhibited (IXMT). In the first
-	  SMTC prototypes, these queued IPIs were serviced on return
-	  to user mode, or on entry into the kernel idle loop. The
-	  INSTANT_REPLAY option dispatches them as part of local_irq_restore()
-	  processing, which adds runtime overhead (hence the option to turn
-	  it off), but ensures that IPIs are handled promptly even under
-	  heavy I/O interrupt load.
-
 config MIPS_MT_SMTC_IM_BACKSTOP
 	bool "Use per-TC register bits as backstop for inhibited IM bits"
 	depends on MIPS_MT_SMTC
-	default y
+	default n
 	help
 	  To support multiple TC microthreads acting as "CPUs" within
 	  a VPE, VPE-wide interrupt mask bits must be specially manipulated
 	  during interrupt handling. To support legacy drivers and interrupt
 	  controller management code, SMTC has a "backstop" to track and
 	  if necessary restore the interrupt mask. This has some performance
-	  impact on interrupt service overhead. Disable it only if you know
-	  what you are doing.
+	  impact on interrupt service overhead.
 
 config MIPS_MT_SMTC_IRQAFF
 	bool "Support IRQ affinity API"
@@ -1579,10 +1563,8 @@ config MIPS_MT_SMTC_IRQAFF
 	  Enables SMP IRQ affinity API (/proc/irq/*/smp_affinity, etc.)
 	  for SMTC Linux kernel. Requires platform support, of which
 	  an example can be found in the MIPS kernel i8259 and Malta
-	  platform code.  It is recommended that MIPS_MT_SMTC_INSTANT_REPLAY
-	  be enabled if MIPS_MT_SMTC_IRQAFF is used. Adds overhead to
-	  interrupt dispatch, and should be used only if you know what
-	  you are doing.
+	  platform code.  Adds some overhead to interrupt dispatch, and 
+	  should be used only if you know what you are doing.
 
 config MIPS_VPE_LOADER_TOM
 	bool "Load VPE program into memory hidden from linux"
diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile
index 65e46a6..4710a6d 100644
--- a/arch/mips/kernel/Makefile
+++ b/arch/mips/kernel/Makefile
@@ -10,6 +10,7 @@ obj-y		+= cpu-probe.o branch.o entry.o genex.o irq.o process.o \
 
 obj-$(CONFIG_CEVT_BCM1480)	+= cevt-bcm1480.o
 obj-$(CONFIG_CEVT_R4K)		+= cevt-r4k.o
+obj-$(CONFIG_MIPS_MT_SMTC)	+= cevt-smtc.o
 obj-$(CONFIG_CEVT_DS1287)	+= cevt-ds1287.o
 obj-$(CONFIG_CEVT_GT641XX)	+= cevt-gt641xx.o
 obj-$(CONFIG_CEVT_SB1250)	+= cevt-sb1250.o
diff --git a/arch/mips/kernel/cevt-r4k.c b/arch/mips/kernel/cevt-r4k.c
index 24a2d90..4a4c59f 100644
--- a/arch/mips/kernel/cevt-r4k.c
+++ b/arch/mips/kernel/cevt-r4k.c
@@ -12,6 +12,14 @@
 
 #include <asm/smtc_ipi.h>
 #include <asm/time.h>
+#include <asm/cevt-r4k.h>
+
+/*
+ * The SMTC Kernel for the 34K, 1004K, et. al. replaces several
+ * of these routines with SMTC-specific variants.
+ */
+
+#ifndef CONFIG_MIPS_MT_SMTC
 
 static int mips_next_event(unsigned long delta,
                            struct clock_event_device *evt)
@@ -19,60 +27,27 @@ static int mips_next_event(unsigned long delta,
 	unsigned int cnt;
 	int res;
 
-#ifdef CONFIG_MIPS_MT_SMTC
-	{
-	unsigned long flags, vpflags;
-	local_irq_save(flags);
-	vpflags = dvpe();
-#endif
 	cnt = read_c0_count();
 	cnt += delta;
 	write_c0_compare(cnt);
 	res = ((int)(read_c0_count() - cnt) > 0) ? -ETIME : 0;
-#ifdef CONFIG_MIPS_MT_SMTC
-	evpe(vpflags);
-	local_irq_restore(flags);
-	}
-#endif
 	return res;
 }
 
-static void mips_set_mode(enum clock_event_mode mode,
-                          struct clock_event_device *evt)
+#endif /* CONFIG_MIPS_MT_SMTC */
+
+void mips_set_clock_mode(enum clock_event_mode mode,
+				struct clock_event_device *evt)
 {
 	/* Nothing to do ...  */
 }
 
-static DEFINE_PER_CPU(struct clock_event_device, mips_clockevent_device);
-static int cp0_timer_irq_installed;
+DEFINE_PER_CPU(struct clock_event_device, mips_clockevent_device);
+int cp0_timer_irq_installed;
 
-/*
- * Timer ack for an R4k-compatible timer of a known frequency.
- */
-static void c0_timer_ack(void)
-{
-	write_c0_compare(read_c0_compare());
-}
+#ifndef CONFIG_MIPS_MT_SMTC
 
-/*
- * Possibly handle a performance counter interrupt.
- * Return true if the timer interrupt should not be checked
- */
-static inline int handle_perf_irq(int r2)
-{
-	/*
-	 * The performance counter overflow interrupt may be shared with the
-	 * timer interrupt (cp0_perfcount_irq < 0). If it is and a
-	 * performance counter has overflowed (perf_irq() == IRQ_HANDLED)
-	 * and we can't reliably determine if a counter interrupt has also
-	 * happened (!r2) then don't check for a timer interrupt.
-	 */
-	return (cp0_perfcount_irq < 0) &&
-		perf_irq() == IRQ_HANDLED &&
-		!r2;
-}
-
-static irqreturn_t c0_compare_interrupt(int irq, void *dev_id)
+irqreturn_t c0_compare_interrupt(int irq, void *dev_id)
 {
 	const int r2 = cpu_has_mips_r2;
 	struct clock_event_device *cd;
@@ -93,12 +68,8 @@ static irqreturn_t c0_compare_interrupt(int irq, void *dev_id)
 	 * interrupt.  Being the paranoiacs we are we check anyway.
 	 */
 	if (!r2 || (read_c0_cause() & (1 << 30))) {
-		c0_timer_ack();
-#ifdef CONFIG_MIPS_MT_SMTC
-		if (cpu_data[cpu].vpe_id)
-			goto out;
-		cpu = 0;
-#endif
+		/* Clear Count/Compare Interrupt */
+		write_c0_compare(read_c0_compare());
 		cd = &per_cpu(mips_clockevent_device, cpu);
 		cd->event_handler(cd);
 	}
@@ -107,65 +78,16 @@ out:
 	return IRQ_HANDLED;
 }
 
-static struct irqaction c0_compare_irqaction = {
+#endif /* Not CONFIG_MIPS_MT_SMTC */
+
+struct irqaction c0_compare_irqaction = {
 	.handler = c0_compare_interrupt,
-#ifdef CONFIG_MIPS_MT_SMTC
-	.flags = IRQF_DISABLED,
-#else
 	.flags = IRQF_DISABLED | IRQF_PERCPU,
-#endif
 	.name = "timer",
 };
 
-#ifdef CONFIG_MIPS_MT_SMTC
-DEFINE_PER_CPU(struct clock_event_device, smtc_dummy_clockevent_device);
-
-static void smtc_set_mode(enum clock_event_mode mode,
-                          struct clock_event_device *evt)
-{
-}
-
-static void mips_broadcast(cpumask_t mask)
-{
-	unsigned int cpu;
-
-	for_each_cpu_mask(cpu, mask)
-		smtc_send_ipi(cpu, SMTC_CLOCK_TICK, 0);
-}
-
-static void setup_smtc_dummy_clockevent_device(void)
-{
-	//uint64_t mips_freq = mips_hpt_^frequency;
-	unsigned int cpu = smp_processor_id();
-	struct clock_event_device *cd;
 
-	cd = &per_cpu(smtc_dummy_clockevent_device, cpu);
-
-	cd->name		= "SMTC";
-	cd->features		= CLOCK_EVT_FEAT_DUMMY;
-
-	/* Calculate the min / max delta */
-	cd->mult	= 0; //div_sc((unsigned long) mips_freq, NSEC_PER_SEC, 32);
-	cd->shift		= 0; //32;
-	cd->max_delta_ns	= 0; //clockevent_delta2ns(0x7fffffff, cd);
-	cd->min_delta_ns	= 0; //clockevent_delta2ns(0x30, cd);
-
-	cd->rating		= 200;
-	cd->irq			= 17; //-1;
-//	if (cpu)
-//		cd->cpumask	= CPU_MASK_ALL; // cpumask_of_cpu(cpu);
-//	else
-		cd->cpumask	= cpumask_of_cpu(cpu);
-
-	cd->set_mode		= smtc_set_mode;
-
-	cd->broadcast		= mips_broadcast;
-
-	clockevents_register_device(cd);
-}
-#endif
-
-static void mips_event_handler(struct clock_event_device *dev)
+void mips_event_handler(struct clock_event_device *dev)
 {
 }
 
@@ -177,7 +99,23 @@ static int c0_compare_int_pending(void)
 	return (read_c0_cause() >> cp0_compare_irq) & 0x100;
 }
 
-static int c0_compare_int_usable(void)
+/*
+ * Compare interrupt can be routed and latched outside the core,
+ * so a single execution hazard barrier may not be enough to give
+ * it time to clear as seen in the Cause register.  4 time the
+ * pipeline depth seems reasonably conservative, and empirically
+ * works better in configurations with high CPU/bus clock ratios.
+ */
+
+#define compare_change_hazard() \
+	do { \
+		irq_disable_hazard(); \
+		irq_disable_hazard(); \
+		irq_disable_hazard(); \
+		irq_disable_hazard(); \
+	} while (0)
+
+int c0_compare_int_usable(void)
 {
 	unsigned int delta;
 	unsigned int cnt;
@@ -187,7 +125,7 @@ static int c0_compare_int_usable(void)
 	 */
 	if (c0_compare_int_pending()) {
 		write_c0_compare(read_c0_count());
-		irq_disable_hazard();
+		compare_change_hazard();
 		if (c0_compare_int_pending())
 			return 0;
 	}
@@ -196,7 +134,7 @@ static int c0_compare_int_usable(void)
 		cnt = read_c0_count();
 		cnt += delta;
 		write_c0_compare(cnt);
-		irq_disable_hazard();
+		compare_change_hazard();
 		if ((int)(read_c0_count() - cnt) < 0)
 		    break;
 		/* increase delta if the timer was already expired */
@@ -205,11 +143,12 @@ static int c0_compare_int_usable(void)
 	while ((int)(read_c0_count() - cnt) <= 0)
 		;	/* Wait for expiry  */
 
+	compare_change_hazard();
 	if (!c0_compare_int_pending())
 		return 0;
 
 	write_c0_compare(read_c0_count());
-	irq_disable_hazard();
+	compare_change_hazard();
 	if (c0_compare_int_pending())
 		return 0;
 
@@ -219,6 +158,8 @@ static int c0_compare_int_usable(void)
 	return 1;
 }
 
+#ifndef CONFIG_MIPS_MT_SMTC
+
 int __cpuinit mips_clockevent_init(void)
 {
 	uint64_t mips_freq = mips_hpt_frequency;
@@ -229,17 +170,6 @@ int __cpuinit mips_clockevent_init(void)
 	if (!cpu_has_counter || !mips_hpt_frequency)
 		return -ENXIO;
 
-#ifdef CONFIG_MIPS_MT_SMTC
-	setup_smtc_dummy_clockevent_device();
-
-	/*
-	 * On SMTC we only register VPE0's compare interrupt as clockevent
-	 * device.
-	 */
-	if (cpu)
-		return 0;
-#endif
-
 	if (!c0_compare_int_usable())
 		return -ENXIO;
 
@@ -265,13 +195,9 @@ int __cpuinit mips_clockevent_init(void)
 
 	cd->rating		= 300;
 	cd->irq			= irq;
-#ifdef CONFIG_MIPS_MT_SMTC
-	cd->cpumask		= CPU_MASK_ALL;
-#else
 	cd->cpumask		= cpumask_of_cpu(cpu);
-#endif
 	cd->set_next_event	= mips_next_event;
-	cd->set_mode		= mips_set_mode;
+	cd->set_mode		= mips_set_clock_mode;
 	cd->event_handler	= mips_event_handler;
 
 	clockevents_register_device(cd);
@@ -281,12 +207,9 @@ int __cpuinit mips_clockevent_init(void)
 
 	cp0_timer_irq_installed = 1;
 
-#ifdef CONFIG_MIPS_MT_SMTC
-#define CPUCTR_IMASKBIT (0x100 << cp0_compare_irq)
-	setup_irq_smtc(irq, &c0_compare_irqaction, CPUCTR_IMASKBIT);
-#else
 	setup_irq(irq, &c0_compare_irqaction);
-#endif
 
 	return 0;
 }
+
+#endif /* Not CONFIG_MIPS_MT_SMTC */
diff --git a/arch/mips/kernel/cevt-smtc.c b/arch/mips/kernel/cevt-smtc.c
new file mode 100644
index 0000000..5162fe4
--- /dev/null
+++ b/arch/mips/kernel/cevt-smtc.c
@@ -0,0 +1,321 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2007 MIPS Technologies, Inc.
+ * Copyright (C) 2007 Ralf Baechle <ralf@linux-mips.org>
+ * Copyright (C) 2008 Kevin D. Kissell, Paralogos sarl
+ */
+#include <linux/clockchips.h>
+#include <linux/interrupt.h>
+#include <linux/percpu.h>
+
+#include <asm/smtc_ipi.h>
+#include <asm/time.h>
+#include <asm/cevt-r4k.h>
+
+/*
+ * Variant clock event timer support for SMTC on MIPS 34K, 1004K
+ * or other MIPS MT cores.
+ *
+ * Notes on SMTC Support:
+ *
+ * SMTC has multiple microthread TCs pretending to be Linux CPUs.
+ * But there's only one Count/Compare pair per VPE, and Compare
+ * interrupts are taken opportunisitically by available TCs
+ * bound to the VPE with the Count register.  The new timer
+ * framework provides for global broadcasts, but we really
+ * want VPE-level multicasts for best behavior. So instead
+ * of invoking the high-level clock-event broadcast code,
+ * this version of SMTC support uses the historical SMTC
+ * multicast mechanisms "under the hood", appearing to the
+ * generic clock layer as if the interrupts are per-CPU.
+ *
+ * The approach taken here is to maintain a set of NR_CPUS
+ * virtual timers, and track which "CPU" needs to be alerted
+ * at each event.
+ *
+ * It's unlikely that we'll see a MIPS MT core with more than
+ * 2 VPEs, but we *know* that we won't need to handle more
+ * VPEs than we have "CPUs".  So NCPUs arrays of NCPUs elements
+ * is always going to be overkill, but always going to be enough.
+ */
+
+unsigned long smtc_nexttime[NR_CPUS][NR_CPUS];
+static int smtc_nextinvpe[NR_CPUS];
+
+/*
+ * Timestamps stored are absolute values to be programmed
+ * into Count register.  Valid timestamps will never be zero.
+ * If a Zero Count value is actually calculated, it is converted
+ * to be a 1, which will introduce 1 or two CPU cycles of error
+ * roughly once every four billion events, which at 1000 HZ means
+ * about once every 50 days.  If that's actually a problem, one
+ * could alternate squashing 0 to 1 and to -1.
+ */
+
+#define MAKEVALID(x) (((x) == 0L) ? 1L : (x))
+#define ISVALID(x) ((x) != 0L)
+
+/*
+ * Time comparison is subtle, as it's really truncated
+ * modular arithmetic.
+ */
+
+#define IS_SOONER(a, b, reference) \
+    (((a) - (unsigned long)(reference)) < ((b) - (unsigned long)(reference)))
+
+/*
+ * CATCHUP_INCREMENT, used when the function falls behind the counter.
+ * Could be an increasing function instead of a constant;
+ */
+
+#define CATCHUP_INCREMENT 64
+
+static int mips_next_event(unsigned long delta,
+				struct clock_event_device *evt)
+{
+	unsigned long flags;
+	unsigned int mtflags;
+	unsigned long timestamp, reference, previous;
+	unsigned long nextcomp = 0L;
+	int vpe = current_cpu_data.vpe_id;
+	int cpu = smp_processor_id();
+	local_irq_save(flags);
+	mtflags = dmt();
+
+	/*
+	 * Maintain the per-TC virtual timer
+	 * and program the per-VPE shared Count register
+	 * as appropriate here...
+	 */
+	reference = (unsigned long)read_c0_count();
+	timestamp = MAKEVALID(reference + delta);
+	/*
+	 * To really model the clock, we have to catch the case
+	 * where the current next-in-VPE timestamp is the old
+	 * timestamp for the calling CPE, but the new value is
+	 * in fact later.  In that case, we have to do a full
+	 * scan and discover the new next-in-VPE CPU id and
+	 * timestamp.
+	 */
+	previous = smtc_nexttime[vpe][cpu];
+	if (cpu == smtc_nextinvpe[vpe] && ISVALID(previous)
+	    && IS_SOONER(previous, timestamp, reference)) {
+		int i;
+		int soonest = cpu;
+
+		/*
+		 * Update timestamp array here, so that new
+		 * value gets considered along with those of
+		 * other virtual CPUs on the VPE.
+		 */
+		smtc_nexttime[vpe][cpu] = timestamp;
+		for_each_online_cpu(i) {
+			if (ISVALID(smtc_nexttime[vpe][i])
+			    && IS_SOONER(smtc_nexttime[vpe][i],
+				smtc_nexttime[vpe][soonest], reference)) {
+				    soonest = i;
+			}
+		}
+		smtc_nextinvpe[vpe] = soonest;
+		nextcomp = smtc_nexttime[vpe][soonest];
+	/*
+	 * Otherwise, we don't have to process the whole array rank,
+	 * we just have to see if the event horizon has gotten closer.
+	 */
+	} else {
+		if (!ISVALID(smtc_nexttime[vpe][smtc_nextinvpe[vpe]]) ||
+		    IS_SOONER(timestamp,
+			smtc_nexttime[vpe][smtc_nextinvpe[vpe]], reference)) {
+			    smtc_nextinvpe[vpe] = cpu;
+			    nextcomp = timestamp;
+		}
+		/*
+		 * Since next-in-VPE may me the same as the executing
+		 * virtual CPU, we update the array *after* checking
+		 * its value.
+		 */
+		smtc_nexttime[vpe][cpu] = timestamp;
+	}
+
+	/*
+	 * It may be that, in fact, we don't need to update Compare,
+	 * but if we do, we want to make sure we didn't fall into
+	 * a crack just behind Count.
+	 */
+	if (ISVALID(nextcomp)) {
+		write_c0_compare(nextcomp);
+		ehb();
+		/*
+		 * We never return an error, we just make sure
+		 * that we trigger the handlers as quickly as
+		 * we can if we fell behind.
+		 */
+		while ((nextcomp - (unsigned long)read_c0_count())
+			> (unsigned long)LONG_MAX) {
+			nextcomp += CATCHUP_INCREMENT;
+			write_c0_compare(nextcomp);
+			ehb();
+		}
+	}
+	emt(mtflags);
+	local_irq_restore(flags);
+	return 0;
+}
+
+
+void smtc_distribute_timer(int vpe)
+{
+	unsigned long flags;
+	unsigned int mtflags;
+	int cpu;
+	struct clock_event_device *cd;
+	unsigned long nextstamp = 0L;
+	unsigned long reference;
+
+
+repeat:
+	for_each_online_cpu(cpu) {
+	    /*
+	     * Find virtual CPUs within the current VPE who have
+	     * unserviced timer requests whose time is now past.
+	     */
+	    local_irq_save(flags);
+	    mtflags = dmt();
+	    if (cpu_data[cpu].vpe_id == vpe &&
+		ISVALID(smtc_nexttime[vpe][cpu])) {
+		reference = (unsigned long)read_c0_count();
+		if ((smtc_nexttime[vpe][cpu] - reference)
+			 > (unsigned long)LONG_MAX) {
+			    smtc_nexttime[vpe][cpu] = 0L;
+			    emt(mtflags);
+			    local_irq_restore(flags);
+			    /*
+			     * We don't send IPIs to ourself.
+			     */
+			    if (cpu != smp_processor_id()) {
+				smtc_send_ipi(cpu, SMTC_CLOCK_TICK, 0);
+			    } else {
+				cd = &per_cpu(mips_clockevent_device, cpu);
+				cd->event_handler(cd);
+			    }
+		} else {
+			/* Local to VPE but Valid Time not yet reached. */
+			if (!ISVALID(nextstamp) ||
+			    IS_SOONER(smtc_nexttime[vpe][cpu], nextstamp,
+			    reference)) {
+				smtc_nextinvpe[vpe] = cpu;
+				nextstamp = smtc_nexttime[vpe][cpu];
+			}
+			emt(mtflags);
+			local_irq_restore(flags);
+		}
+	    } else {
+		emt(mtflags);
+		local_irq_restore(flags);
+
+	    }
+	}
+	/* Reprogram for interrupt at next soonest timestamp for VPE */
+	if (ISVALID(nextstamp)) {
+		write_c0_compare(nextstamp);
+		ehb();
+		if ((nextstamp - (unsigned long)read_c0_count())
+			> (unsigned long)LONG_MAX)
+				goto repeat;
+	}
+}
+
+
+irqreturn_t c0_compare_interrupt(int irq, void *dev_id)
+{
+	int cpu = smp_processor_id();
+
+	/* If we're running SMTC, we've got MIPS MT and therefore MIPS32R2 */
+	handle_perf_irq(1);
+
+	if (read_c0_cause() & (1 << 30)) {
+		/* Clear Count/Compare Interrupt */
+		write_c0_compare(read_c0_compare());
+		smtc_distribute_timer(cpu_data[cpu].vpe_id);
+	}
+	return IRQ_HANDLED;
+}
+
+
+int __cpuinit mips_clockevent_init(void)
+{
+	uint64_t mips_freq = mips_hpt_frequency;
+	unsigned int cpu = smp_processor_id();
+	struct clock_event_device *cd;
+	unsigned int irq;
+	int i;
+	int j;
+
+	if (!cpu_has_counter || !mips_hpt_frequency)
+		return -ENXIO;
+	if (cpu == 0) {
+		for (i = 0; i < num_possible_cpus(); i++) {
+			smtc_nextinvpe[i] = 0;
+			for (j = 0; j < num_possible_cpus(); j++)
+				smtc_nexttime[i][j] = 0L;
+		}
+		/*
+		 * SMTC also can't have the usablility test
+		 * run by secondary TCs once Compare is in use.
+		 */
+		if (!c0_compare_int_usable())
+			return -ENXIO;
+	}
+
+	/*
+	 * With vectored interrupts things are getting platform specific.
+	 * get_c0_compare_int is a hook to allow a platform to return the
+	 * interrupt number of it's liking.
+	 */
+	irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq;
+	if (get_c0_compare_int)
+		irq = get_c0_compare_int();
+
+	cd = &per_cpu(mips_clockevent_device, cpu);
+
+	cd->name		= "MIPS";
+	cd->features		= CLOCK_EVT_FEAT_ONESHOT;
+
+	/* Calculate the min / max delta */
+	cd->mult	= div_sc((unsigned long) mips_freq, NSEC_PER_SEC, 32);
+	cd->shift		= 32;
+	cd->max_delta_ns	= clockevent_delta2ns(0x7fffffff, cd);
+	cd->min_delta_ns	= clockevent_delta2ns(0x300, cd);
+
+	cd->rating		= 300;
+	cd->irq			= irq;
+	cd->cpumask		= cpumask_of_cpu(cpu);
+	cd->set_next_event	= mips_next_event;
+	cd->set_mode		= mips_set_clock_mode;
+	cd->event_handler	= mips_event_handler;
+
+	clockevents_register_device(cd);
+
+	/*
+	 * On SMTC we only want to do the data structure
+	 * initialization and IRQ setup once.
+	 */
+	if (cpu)
+		return 0;
+	/*
+	 * And we need the hwmask associated with the c0_compare
+	 * vector to be initialized.
+	 */
+	irq_hwmask[irq] = (0x100 << cp0_compare_irq);
+	if (cp0_timer_irq_installed)
+		return 0;
+
+	cp0_timer_irq_installed = 1;
+
+	setup_irq(irq, &c0_compare_irqaction);
+
+	return 0;
+}
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 335a6ae..537caec 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -65,14 +65,18 @@ static void r4k_wait(void)
  * interrupt is requested" restriction in the MIPS32/MIPS64 architecture makes
  * using this version a gamble.
  */
-static void r4k_wait_irqoff(void)
+void r4k_wait_irqoff(void)
 {
 	local_irq_disable();
 	if (!need_resched())
-		__asm__("	.set	mips3		\n"
+		__asm__("	.set	push		\n"
+			"	.set	mips3		\n"
 			"	wait			\n"
-			"	.set	mips0		\n");
+			"	.set	pop		\n");
 	local_irq_enable();
+	__asm__(" 	.globl __pastwait	\n"
+		"__pastwait:			\n");
+	return;
 }
 
 /*
diff --git a/arch/mips/kernel/genex.S b/arch/mips/kernel/genex.S
index c6ada98..4f25712 100644
--- a/arch/mips/kernel/genex.S
+++ b/arch/mips/kernel/genex.S
@@ -245,8 +245,8 @@ NESTED(except_vec_vi_handler, 0, sp)
 	and	t0, a0, t1
 #ifdef CONFIG_MIPS_MT_SMTC_IM_BACKSTOP
 	mfc0	t2, CP0_TCCONTEXT
-	or	t0, t0, t2
-	mtc0	t0, CP0_TCCONTEXT
+	or	t2, t0, t2
+	mtc0	t2, CP0_TCCONTEXT
 #endif /* CONFIG_MIPS_MT_SMTC_IM_BACKSTOP */
 	xor	t1, t1, t0
 	mtc0	t1, CP0_STATUS
diff --git a/arch/mips/kernel/smtc.c b/arch/mips/kernel/smtc.c
index 3e86318..9685a64 100644
--- a/arch/mips/kernel/smtc.c
+++ b/arch/mips/kernel/smtc.c
@@ -1,4 +1,21 @@
-/* Copyright (C) 2004 Mips Technologies, Inc */
+/*
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
+ *
+ * Copyright (C) 2004 Mips Technologies, Inc
+ * Copyright (C) 2008 Kevin D. Kissell
+ */
 
 #include <linux/clockchips.h>
 #include <linux/kernel.h>
@@ -21,7 +38,6 @@
 #include <asm/time.h>
 #include <asm/addrspace.h>
 #include <asm/smtc.h>
-#include <asm/smtc_ipi.h>
 #include <asm/smtc_proc.h>
 
 /*
@@ -58,11 +74,6 @@ unsigned long irq_hwmask[NR_IRQS];
 
 asiduse smtc_live_asid[MAX_SMTC_TLBS][MAX_SMTC_ASIDS];
 
-/*
- * Clock interrupt "latch" buffers, per "CPU"
- */
-
-static atomic_t ipi_timer_latch[NR_CPUS];
 
 /*
  * Number of InterProcessor Interrupt (IPI) message buffers to allocate
@@ -70,7 +81,7 @@ static atomic_t ipi_timer_latch[NR_CPUS];
 
 #define IPIBUF_PER_CPU 4
 
-static struct smtc_ipi_q IPIQ[NR_CPUS];
+struct smtc_ipi_q IPIQ[NR_CPUS];
 static struct smtc_ipi_q freeIPIq;
 
 
@@ -282,7 +293,7 @@ static void smtc_configure_tlb(void)
  * phys_cpu_present_map and the logical/physical mappings.
  */
 
-int __init mipsmt_build_cpu_map(int start_cpu_slot)
+int __init smtc_build_cpu_map(int start_cpu_slot)
 {
 	int i, ntcs;
 
@@ -325,7 +336,12 @@ static void smtc_tc_setup(int vpe, int tc, int cpu)
 	write_tc_c0_tcstatus((read_tc_c0_tcstatus()
 			& ~(TCSTATUS_TKSU | TCSTATUS_DA | TCSTATUS_IXMT))
 			| TCSTATUS_A);
-	write_tc_c0_tccontext(0);
+	/*
+	 * TCContext gets an offset from the base of the IPIQ array
+	 * to be used in low-level code to detect the presence of
+	 * an active IPI queue
+	 */
+	write_tc_c0_tccontext((sizeof(struct smtc_ipi_q) * cpu) << 16);
 	/* Bind tc to vpe */
 	write_tc_c0_tcbind(vpe);
 	/* In general, all TCs should have the same cpu_data indications */
@@ -336,10 +352,18 @@ static void smtc_tc_setup(int vpe, int tc, int cpu)
 		cpu_data[cpu].options &= ~MIPS_CPU_FPU;
 	cpu_data[cpu].vpe_id = vpe;
 	cpu_data[cpu].tc_id = tc;
+	/* Multi-core SMTC hasn't been tested, but be prepared */
+	cpu_data[cpu].core = (read_vpe_c0_ebase() >> 1) & 0xff;
 }
 
+/*
+ * Tweak to get Count registes in as close a sync as possible.
+ * Value seems good for 34K-class cores.
+ */
+
+#define CP0_SKEW 8
 
-void mipsmt_prepare_cpus(void)
+void smtc_prepare_cpus(int cpus)
 {
 	int i, vpe, tc, ntc, nvpe, tcpervpe[NR_CPUS], slop, cpu;
 	unsigned long flags;
@@ -363,13 +387,13 @@ void mipsmt_prepare_cpus(void)
 		IPIQ[i].head = IPIQ[i].tail = NULL;
 		spin_lock_init(&IPIQ[i].lock);
 		IPIQ[i].depth = 0;
-		atomic_set(&ipi_timer_latch[i], 0);
 	}
 
 	/* cpu_data index starts at zero */
 	cpu = 0;
 	cpu_data[cpu].vpe_id = 0;
 	cpu_data[cpu].tc_id = 0;
+	cpu_data[cpu].core = (read_c0_ebase() >> 1) & 0xff;
 	cpu++;
 
 	/* Report on boot-time options */
@@ -484,7 +508,8 @@ void mipsmt_prepare_cpus(void)
 			write_vpe_c0_compare(0);
 			/* Propagate Config7 */
 			write_vpe_c0_config7(read_c0_config7());
-			write_vpe_c0_count(read_c0_count());
+			write_vpe_c0_count(read_c0_count() + CP0_SKEW);
+			ehb();
 		}
 		/* enable multi-threading within VPE */
 		write_vpe_c0_vpecontrol(read_vpe_c0_vpecontrol() | VPECONTROL_TE);
@@ -585,24 +610,22 @@ void __cpuinit smtc_boot_secondary(int cpu, struct task_struct *idle)
 
 void smtc_init_secondary(void)
 {
-	/*
-	 * Start timer on secondary VPEs if necessary.
-	 * plat_timer_setup has already have been invoked by init/main
-	 * on "boot" TC.  Like per_cpu_trap_init() hack, this assumes that
-	 * SMTC init code assigns TCs consdecutively and in ascending order
-	 * to across available VPEs.
-	 */
-	if (((read_c0_tcbind() & TCBIND_CURTC) != 0) &&
-	    ((read_c0_tcbind() & TCBIND_CURVPE)
-	    != cpu_data[smp_processor_id() - 1].vpe_id)){
-		write_c0_compare(read_c0_count() + mips_hpt_frequency/HZ);
-	}
-
 	local_irq_enable();
 }
 
 void smtc_smp_finish(void)
 {
+	int cpu = smp_processor_id();
+
+	/*
+	 * Lowest-numbered CPU per VPE starts a clock tick.
+	 * Like per_cpu_trap_init() hack, this assumes that
+	 * SMTC init code assigns TCs consdecutively and
+	 * in ascending order across available VPEs.
+	 */
+	if (cpu > 0 && (cpu_data[cpu].vpe_id != cpu_data[cpu - 1].vpe_id))
+		write_c0_compare(read_c0_count() + mips_hpt_frequency/HZ);
+
 	printk("TC %d going on-line as CPU %d\n",
 		cpu_data[smp_processor_id()].tc_id, smp_processor_id());
 }
@@ -755,6 +778,8 @@ void smtc_send_ipi(int cpu, int type, unsigned int action)
 	struct smtc_ipi *pipi;
 	long flags;
 	int mtflags;
+	unsigned long tcrestart;
+	extern void r4k_wait_irqoff(void), __pastwait(void);
 
 	if (cpu == smp_processor_id()) {
 		printk("Cannot Send IPI to self!\n");
@@ -771,8 +796,6 @@ void smtc_send_ipi(int cpu, int type, unsigned int action)
 	pipi->arg = (void *)action;
 	pipi->dest = cpu;
 	if (cpu_data[cpu].vpe_id != cpu_data[smp_processor_id()].vpe_id) {
-		if (type == SMTC_CLOCK_TICK)
-			atomic_inc(&ipi_timer_latch[cpu]);
 		/* If not on same VPE, enqueue and send cross-VPE interrupt */
 		smtc_ipi_nq(&IPIQ[cpu], pipi);
 		LOCK_CORE_PRA();
@@ -800,22 +823,29 @@ void smtc_send_ipi(int cpu, int type, unsigned int action)
 
 		if ((tcstatus & TCSTATUS_IXMT) != 0) {
 			/*
-			 * Spin-waiting here can deadlock,
-			 * so we queue the message for the target TC.
+			 * If we're in the the irq-off version of the wait
+			 * loop, we need to force exit from the wait and
+			 * do a direct post of the IPI.
+			 */
+			if (cpu_wait == r4k_wait_irqoff) {
+				tcrestart = read_tc_c0_tcrestart();
+				if (tcrestart >= (unsigned long)r4k_wait_irqoff
+				    && tcrestart < (unsigned long)__pastwait) {
+					write_tc_c0_tcrestart(__pastwait);
+					tcstatus &= ~TCSTATUS_IXMT;
+					write_tc_c0_tcstatus(tcstatus);
+					goto postdirect;
+				}
+			}
+			/*
+			 * Otherwise we queue the message for the target TC
+			 * to pick up when he does a local_irq_restore()
 			 */
 			write_tc_c0_tchalt(0);
 			UNLOCK_CORE_PRA();
-			/* Try to reduce redundant timer interrupt messages */
-			if (type == SMTC_CLOCK_TICK) {
-			    if (atomic_postincrement(&ipi_timer_latch[cpu])!=0){
-				smtc_ipi_nq(&freeIPIq, pipi);
-				return;
-			    }
-			}
 			smtc_ipi_nq(&IPIQ[cpu], pipi);
 		} else {
-			if (type == SMTC_CLOCK_TICK)
-				atomic_inc(&ipi_timer_latch[cpu]);
+postdirect:
 			post_direct_ipi(cpu, pipi);
 			write_tc_c0_tchalt(0);
 			UNLOCK_CORE_PRA();
@@ -884,7 +914,7 @@ static void ipi_call_interrupt(void)
 	smp_call_function_interrupt();
 }
 
-DECLARE_PER_CPU(struct clock_event_device, smtc_dummy_clockevent_device);
+DECLARE_PER_CPU(struct clock_event_device, mips_clockevent_device);
 
 void ipi_decode(struct smtc_ipi *pipi)
 {
@@ -892,20 +922,13 @@ void ipi_decode(struct smtc_ipi *pipi)
 	struct clock_event_device *cd;
 	void *arg_copy = pipi->arg;
 	int type_copy = pipi->type;
-	int ticks;
-
 	smtc_ipi_nq(&freeIPIq, pipi);
 	switch (type_copy) {
 	case SMTC_CLOCK_TICK:
 		irq_enter();
 		kstat_this_cpu.irqs[MIPS_CPU_IRQ_BASE + 1]++;
-		cd = &per_cpu(smtc_dummy_clockevent_device, cpu);
-		ticks = atomic_read(&ipi_timer_latch[cpu]);
-		atomic_sub(ticks, &ipi_timer_latch[cpu]);
-		while (ticks) {
-			cd->event_handler(cd);
-			ticks--;
-		}
+		cd = &per_cpu(mips_clockevent_device, cpu);
+		cd->event_handler(cd);
 		irq_exit();
 		break;
 
@@ -938,24 +961,48 @@ void ipi_decode(struct smtc_ipi *pipi)
 	}
 }
 
+/*
+ * Similar to smtc_ipi_replay(), but invoked from context restore,
+ * so it reuses the current exception frame rather than set up a
+ * new one with self_ipi.
+ */
+
 void deferred_smtc_ipi(void)
 {
-	struct smtc_ipi *pipi;
-	unsigned long flags;
-/* DEBUG */
-	int q = smp_processor_id();
+	int cpu = smp_processor_id();
 
 	/*
 	 * Test is not atomic, but much faster than a dequeue,
 	 * and the vast majority of invocations will have a null queue.
+	 * If irq_disabled when this was called, then any IPIs queued
+	 * after we test last will be taken on the next irq_enable/restore.
+	 * If interrupts were enabled, then any IPIs added after the
+	 * last test will be taken directly.
 	 */
-	if (IPIQ[q].head != NULL) {
-		while((pipi = smtc_ipi_dq(&IPIQ[q])) != NULL) {
-			/* ipi_decode() should be called with interrupts off */
-			local_irq_save(flags);
+
+	while (IPIQ[cpu].head != NULL) {
+		struct smtc_ipi_q *q = &IPIQ[cpu];
+		struct smtc_ipi *pipi;
+		unsigned long flags;
+
+		/*
+		 * It may be possible we'll come in with interrupts
+		 * already enabled.
+		 */
+		local_irq_save(flags);
+
+		spin_lock(&q->lock);
+		pipi = __smtc_ipi_dq(q);
+		spin_unlock(&q->lock);
+		if (pipi != NULL)
 			ipi_decode(pipi);
-			local_irq_restore(flags);
-		}
+		/*
+		 * The use of the __raw_local restore isn't
+		 * as obviously necessary here as in smtc_ipi_replay(),
+		 * but it's more efficient, given that we're already
+		 * running down the IPI queue.
+		 */
+		__raw_local_irq_restore(flags);
 	}
 }
 
@@ -1067,55 +1114,53 @@ static void setup_cross_vpe_interrupts(unsigned int nvpe)
 
 /*
  * SMTC-specific hacks invoked from elsewhere in the kernel.
- *
- * smtc_ipi_replay is called from raw_local_irq_restore which is only ever
- * called with interrupts disabled.  We do rely on interrupts being disabled
- * here because using spin_lock_irqsave()/spin_unlock_irqrestore() would
- * result in a recursive call to raw_local_irq_restore().
  */
 
-static void __smtc_ipi_replay(void)
+ /*
+  * smtc_ipi_replay is called from raw_local_irq_restore
+  */
+
+void smtc_ipi_replay(void)
 {
 	unsigned int cpu = smp_processor_id();
 
 	/*
 	 * To the extent that we've ever turned interrupts off,
 	 * we may have accumulated deferred IPIs.  This is subtle.
-	 * If we use the smtc_ipi_qdepth() macro, we'll get an
-	 * exact number - but we'll also disable interrupts
-	 * and create a window of failure where a new IPI gets
-	 * queued after we test the depth but before we re-enable
-	 * interrupts. So long as IXMT never gets set, however,
 	 * we should be OK:  If we pick up something and dispatch
 	 * it here, that's great. If we see nothing, but concurrent
 	 * with this operation, another TC sends us an IPI, IXMT
 	 * is clear, and we'll handle it as a real pseudo-interrupt
-	 * and not a pseudo-pseudo interrupt.
+	 * and not a pseudo-pseudo interrupt.  The important thing
+	 * is to do the last check for queued message *after* the
+	 * re-enabling of interrupts.
 	 */
-	if (IPIQ[cpu].depth > 0) {
-		while (1) {
-			struct smtc_ipi_q *q = &IPIQ[cpu];
-			struct smtc_ipi *pipi;
-			extern void self_ipi(struct smtc_ipi *);
-
-			spin_lock(&q->lock);
-			pipi = __smtc_ipi_dq(q);
-			spin_unlock(&q->lock);
-			if (!pipi)
-				break;
+	while (IPIQ[cpu].head != NULL) {
+		struct smtc_ipi_q *q = &IPIQ[cpu];
+		struct smtc_ipi *pipi;
+		unsigned long flags;
 
+		/*
+		 * It's just possible we'll come in with interrupts
+		 * already enabled.
+		 */
+		local_irq_save(flags);
+
+		spin_lock(&q->lock);
+		pipi = __smtc_ipi_dq(q);
+		spin_unlock(&q->lock);
+		/*
+		 ** But use a raw restore here to avoid recursion.
+		 */
+		__raw_local_irq_restore(flags);
+
+		if (pipi) {
 			self_ipi(pipi);
 			smtc_cpu_stats[cpu].selfipis++;
 		}
 	}
 }
 
-void smtc_ipi_replay(void)
-{
-	raw_local_irq_disable();
-	__smtc_ipi_replay();
-}
-
 EXPORT_SYMBOL(smtc_ipi_replay);
 
 void smtc_idle_loop_hook(void)
@@ -1194,40 +1239,13 @@ void smtc_idle_loop_hook(void)
 		}
 	}
 
-	/*
-	 * Now that we limit outstanding timer IPIs, check for hung TC
-	 */
-	for (tc = 0; tc < NR_CPUS; tc++) {
-		/* Don't check ourself - we'll dequeue IPIs just below */
-		if ((tc != smp_processor_id()) &&
-		    atomic_read(&ipi_timer_latch[tc]) > timerq_limit) {
-		    if (clock_hang_reported[tc] == 0) {
-			pdb_msg += sprintf(pdb_msg,
-				"TC %d looks hung with timer latch at %d\n",
-				tc, atomic_read(&ipi_timer_latch[tc]));
-			clock_hang_reported[tc]++;
-			}
-		}
-	}
 	emt(mtflags);
 	local_irq_restore(flags);
 	if (pdb_msg != &id_ho_db_msg[0])
 		printk("CPU%d: %s", smp_processor_id(), id_ho_db_msg);
 #endif /* CONFIG_SMTC_IDLE_HOOK_DEBUG */
 
-	/*
-	 * Replay any accumulated deferred IPIs. If "Instant Replay"
-	 * is in use, there should never be any.
-	 */
-#ifndef CONFIG_MIPS_MT_SMTC_INSTANT_REPLAY
-	{
-		unsigned long flags;
-
-		local_irq_save(flags);
-		__smtc_ipi_replay();
-		local_irq_restore(flags);
-	}
-#endif /* CONFIG_MIPS_MT_SMTC_INSTANT_REPLAY */
+	smtc_ipi_replay();
 }
 
 void smtc_soft_dump(void)
@@ -1243,10 +1261,6 @@ void smtc_soft_dump(void)
 		printk("%d: %ld\n", i, smtc_cpu_stats[i].selfipis);
 	}
 	smtc_ipi_qdump();
-	printk("Timer IPI Backlogs:\n");
-	for (i=0; i < NR_CPUS; i++) {
-		printk("%d: %d\n", i, atomic_read(&ipi_timer_latch[i]));
-	}
 	printk("%d Recoveries of \"stolen\" FPU\n",
 	       atomic_read(&smtc_fpu_recoveries));
 }
diff --git a/arch/mips/mips-boards/malta/malta_smtc.c b/arch/mips/mips-boards/malta/malta_smtc.c
index 5ea705e..f84a46a 100644
--- a/arch/mips/mips-boards/malta/malta_smtc.c
+++ b/arch/mips/mips-boards/malta/malta_smtc.c
@@ -84,12 +84,17 @@ static void msmtc_cpus_done(void)
 
 static void __init msmtc_smp_setup(void)
 {
-	mipsmt_build_cpu_map(0);
+	/*
+	 * we won't get the definitive value until
+	 * we've run smtc_prepare_cpus later, but
+	 * we would appear to need an upper bound now.
+	 */
+	smp_num_siblings = smtc_build_cpu_map(0);
 }
 
 static void __init msmtc_prepare_cpus(unsigned int max_cpus)
 {
-	mipsmt_prepare_cpus();
+	smtc_prepare_cpus(max_cpus);
 }
 
 struct plat_smp_ops msmtc_smp_ops = {
diff --git a/include/asm-mips/cevt-r4k.h b/include/asm-mips/cevt-r4k.h
new file mode 100644
index 0000000..fa4328f
--- /dev/null
+++ b/include/asm-mips/cevt-r4k.h
@@ -0,0 +1,46 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2008 Kevin D. Kissell
+ */
+
+/*
+ * Definitions used for common event timer implementation
+ * for MIPS 4K-type processors and their MIPS MT variants.
+ * Avoids unsightly extern declarations in C files.
+ */
+#ifndef __ASM_CEVT_R4K_H
+#define __ASM_CEVT_R4K_H
+
+DECLARE_PER_CPU(struct clock_event_device, mips_clockevent_device);
+
+void mips_event_handler(struct clock_event_device *dev);
+int c0_compare_int_usable(void);
+void mips_set_clock_mode(enum clock_event_mode, struct clock_event_device *);
+irqreturn_t c0_compare_interrupt(int, void *);
+
+extern struct irqaction c0_compare_irqaction;
+extern int cp0_timer_irq_installed;
+
+/*
+ * Possibly handle a performance counter interrupt.
+ * Return true if the timer interrupt should not be checked
+ */
+
+static inline int handle_perf_irq(int r2)
+{
+	/*
+	 * The performance counter overflow interrupt may be shared with the
+	 * timer interrupt (cp0_perfcount_irq < 0). If it is and a
+	 * performance counter has overflowed (perf_irq() == IRQ_HANDLED)
+	 * and we can't reliably determine if a counter interrupt has also
+	 * happened (!r2) then don't check for a timer interrupt.
+	 */
+	return (cp0_perfcount_irq < 0) &&
+		perf_irq() == IRQ_HANDLED &&
+		!r2;
+}
+
+#endif /* __ASM_CEVT_R4K_H */
diff --git a/include/asm-mips/irqflags.h b/include/asm-mips/irqflags.h
index 881e886..701ec0b 100644
--- a/include/asm-mips/irqflags.h
+++ b/include/asm-mips/irqflags.h
@@ -38,8 +38,17 @@ __asm__(
 	"	.set	pop						\n"
 	"	.endm");
 
+extern void smtc_ipi_replay(void);
+
 static inline void raw_local_irq_enable(void)
 {
+#ifdef CONFIG_MIPS_MT_SMTC
+	/*
+	 * SMTC kernel needs to do a software replay of queued
+	 * IPIs, at the cost of call overhead on each local_irq_enable()
+	 */
+	smtc_ipi_replay();
+#endif
 	__asm__ __volatile__(
 		"raw_local_irq_enable"
 		: /* no outputs */
@@ -47,6 +56,7 @@ static inline void raw_local_irq_enable(void)
 		: "memory");
 }
 
+
 /*
  * For cli() we have to insert nops to make sure that the new value
  * has actually arrived in the status register before the end of this
@@ -185,15 +195,14 @@ __asm__(
 	"	.set	pop						\n"
 	"	.endm							\n");
 
-extern void smtc_ipi_replay(void);
 
 static inline void raw_local_irq_restore(unsigned long flags)
 {
 	unsigned long __tmp1;
 
-#ifdef CONFIG_MIPS_MT_SMTC_INSTANT_REPLAY
+#ifdef CONFIG_MIPS_MT_SMTC
 	/*
-	 * CONFIG_MIPS_MT_SMTC_INSTANT_REPLAY does prompt replay of deferred
+	 * SMTC kernel needs to do a software replay of queued
 	 * IPIs, at the cost of branch and call overhead on each
 	 * local_irq_restore()
 	 */
@@ -208,6 +217,17 @@ static inline void raw_local_irq_restore(unsigned long flags)
 		: "memory");
 }
 
+static inline void __raw_local_irq_restore(unsigned long flags)
+{
+	unsigned long __tmp1;
+
+	__asm__ __volatile__(
+		"raw_local_irq_restore\t%0"
+		: "=r" (__tmp1)
+		: "0" (flags)
+		: "memory");
+}
+
 static inline int raw_irqs_disabled_flags(unsigned long flags)
 {
 #ifdef CONFIG_MIPS_MT_SMTC
diff --git a/include/asm-mips/smtc.h b/include/asm-mips/smtc.h
index 3639b28..ea60bf0 100644
--- a/include/asm-mips/smtc.h
+++ b/include/asm-mips/smtc.h
@@ -6,6 +6,7 @@
  */
 
 #include <asm/mips_mt.h>
+#include <asm/smtc_ipi.h>
 
 /*
  * System-wide SMTC status information
@@ -38,14 +39,15 @@ struct mm_struct;
 struct task_struct;
 
 void smtc_get_new_mmu_context(struct mm_struct *mm, unsigned long cpu);
-
+void self_ipi(struct smtc_ipi *);
 void smtc_flush_tlb_asid(unsigned long asid);
-extern int mipsmt_build_cpu_map(int startslot);
-extern void mipsmt_prepare_cpus(void);
+extern int smtc_build_cpu_map(int startslot);
+extern void smtc_prepare_cpus(int cpus);
 extern void smtc_smp_finish(void);
 extern void smtc_boot_secondary(int cpu, struct task_struct *t);
 extern void smtc_cpus_done(void);
 
+
 /*
  * Sharing the TLB between multiple VPEs means that the
  * "random" index selection function is not allowed to
-- 
1.5.3.3


--------------060403060504020202070903--

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From 61a869c6b8d97c761a7ba60ea316ae6b83e01ef1 Mon Sep 17 00:00:00 2001
From: Kevin D. Kissell <kevink@paralogos.com>
Date: Tue, 9 Sep 2008 21:35:01 +0200
Subject: [PATCH] Close tiny holes in the SMTC IPI replay system.
 Signed-off-by: Kevin D. Kissell <kevink@paralogos.com>
Content-Length: 4112
Lines: 136

---
 arch/mips/kernel/entry.S      |   10 +++---
 include/asm-mips/stackframe.h |   72 ++++++++++++++++++++++++++++++++++------
 2 files changed, 66 insertions(+), 16 deletions(-)

diff --git a/arch/mips/kernel/entry.S b/arch/mips/kernel/entry.S
index e29598a..ffa3310 100644
--- a/arch/mips/kernel/entry.S
+++ b/arch/mips/kernel/entry.S
@@ -79,11 +79,6 @@ FEXPORT(syscall_exit)
 
 FEXPORT(restore_all)			# restore full frame
 #ifdef CONFIG_MIPS_MT_SMTC
-/* Detect and execute deferred IPI "interrupts" */
-	LONG_L	s0, TI_REGS($28)
-	LONG_S	sp, TI_REGS($28)
-	jal	deferred_smtc_ipi
-	LONG_S	s0, TI_REGS($28)
 #ifdef CONFIG_MIPS_MT_SMTC_IM_BACKSTOP
 /* Re-arm any temporarily masked interrupts not explicitly "acked" */
 	mfc0	v0, CP0_TCSTATUS
@@ -112,6 +107,11 @@ FEXPORT(restore_all)			# restore full frame
 	xor	t0, t0, t3
 	mtc0	t0, CP0_TCCONTEXT
 #endif /* CONFIG_MIPS_MT_SMTC_IM_BACKSTOP */
+/* Detect and execute deferred IPI "interrupts" */
+	LONG_L	s0, TI_REGS($28)
+	LONG_S	sp, TI_REGS($28)
+	jal	deferred_smtc_ipi
+	LONG_S	s0, TI_REGS($28)
 #endif /* CONFIG_MIPS_MT_SMTC */
 	.set	noat
 	RESTORE_TEMP
diff --git a/include/asm-mips/stackframe.h b/include/asm-mips/stackframe.h
index 051e1af..4c37c4e 100644
--- a/include/asm-mips/stackframe.h
+++ b/include/asm-mips/stackframe.h
@@ -297,14 +297,31 @@
 #ifdef CONFIG_MIPS_MT_SMTC
 		.set	mips32r2
 		/*
-		 * This may not really be necessary if ints are already
-		 * inhibited here.
+		 * We need to make sure the read-modify-write
+		 * of Status below isn't perturbed by an interrupt
+		 * or cross-TC access, so we need to do at least a DMT,
+		 * protected by an interrupt-inhibit. But setting IXMT
+		 * also creates a few-cycle window where an IPI could
+		 * be queued and not be detected before potentially
+		 * returning to a WAIT or user-mode loop. It must be
+		 * replayed.
+		 *
+		 * We're in the middle of a context switch, and
+		 * we can't dispatch it directly without trashing
+		 * some registers, so we'll try to detect this unlikely
+		 * case and program a software interrupt in the VPE,
+		 * as would be done for a cross-VPE IPI.  To accomodate
+		 * the handling of that case, we're doing a DVPE instead
+		 * of just a DMT here to protect against other threads.
+		 * This is a lot of cruft to cover a tiny window.
+		 * If you can find a better design, implement it!
+		 *
 		 */
 		mfc0	v0, CP0_TCSTATUS
 		ori	v0, TCSTATUS_IXMT
 		mtc0	v0, CP0_TCSTATUS
 		_ehb
-		DMT	5				# dmt a1
+		DVPE	5				# dvpe a1
 		jal	mips_ihb
 #endif /* CONFIG_MIPS_MT_SMTC */
 		mfc0	a0, CP0_STATUS
@@ -325,17 +342,50 @@
  */
 		LONG_L	v1, PT_TCSTATUS(sp)
 		_ehb
-		mfc0	v0, CP0_TCSTATUS
+		mfc0	a0, CP0_TCSTATUS
 		andi	v1, TCSTATUS_IXMT
-		/* We know that TCStatua.IXMT should be set from above */
-		xori	v0, v0, TCSTATUS_IXMT
-		or	v0, v0, v1
-		mtc0	v0, CP0_TCSTATUS
-		_ehb
-		andi	a1, a1, VPECONTROL_TE
+		bnez	v1, 0f
+
+/*
+ * We'd like to detect any IPIs queued in the tiny window
+ * above and request an software interrupt to service them
+ * when we ERET.
+ *
+ * Computing the offset into the IPIQ array of the executing
+ * TC's IPI queue in-line would be tedious.  We use part of
+ * the TCContext register to hold 16 bits of offset that we
+ * can add in-line to find the queue head.
+ */
+		mfc0	v0, CP0_TCCONTEXT
+		la	a2, IPIQ
+		srl	v0, v0, 16
+		addu	a2, a2, v0
+		LONG_L	v0, 0(a2)
+		beqz	v0, 0f
+/*
+ * If we have a queue, provoke dispatch within the VPE by setting C_SW1
+ */
+		mfc0	v0, CP0_CAUSE
+		ori	v0, v0, C_SW1
+		mtc0	v0, CP0_CAUSE
+0:
+		/*
+		 * This test should really never branch but
+		 * let's be prudent here.  Having atomized
+		 * the shared register modifications, we can
+		 * now EVPE, and must do so before interrupts
+		 * are potentially re-enabled.
+		 */
+		andi	a1, a1, MVPCONTROL_EVP
 		beqz	a1, 1f
-		emt
+		evpe
 1:
+		/* We know that TCStatua.IXMT should be set from above */
+		xori	a0, a0, TCSTATUS_IXMT
+		or	a0, a0, v1
+		mtc0	a0, CP0_TCSTATUS
+		_ehb
+
 		.set	mips0
 #endif /* CONFIG_MIPS_MT_SMTC */
 		LONG_L	v1, PT_EPC(sp)
-- 
1.5.3.3


--------------080009040507040709070608--

From thomas.petazzoni@enix.org Wed Sep 10 08:09:18 2008
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From:	Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
To:	ralf@linux-mips.org
Cc:	ths@networkno.de, linux-mips@linux-mips.org,
	michael@free-electrons.com,
	Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Subject: [PATCH 1/1] mips: clear IV bit in CP0 cause if the CPU doesn't support divec
Date:	Tue,  9 Sep 2008 10:15:25 +0200
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When the kernel thinks that the CPU doesn't support the divec feature
(cpu_has_divec is false), reset the corresponding IV bit in the CP0
cause register, so that things will work correctly if the bootloader
had a different idea of the CPU support of the divec feature.

The problem has been found while trying to boot a 2.6.24 kernel for
the Qemu board using U-Boot inside Qemu. For the same CPU type, U-Boot
thinks that divec is supported, and the kernel doesn't. So U-Boot sets
the IV bit, but when the kernel boots and doesn't reset the IV bit,
things break when the first interrupts occur. The Qemu board has been
removed from the kernel in 2.6.25, but the problem might also occur
with other platforms.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Thiemo Seufer <ths@networkno.de>
Cc: linux-mips@linux-mips.org
---
 arch/mips/kernel/traps.c |    3 +++
 1 files changed, 3 insertions(+), 0 deletions(-)

diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index 6bee290..8b1e507 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -1467,6 +1467,9 @@ void __cpuinit per_cpu_trap_init(void)
 		} else
 			set_c0_cause(CAUSEF_IV);
 	}
+	else {
+		clear_c0_cause(CAUSEF_IV);
+	}
 
 	/*
 	 * Before R2 both interrupt numbers were fixed to 7, so on R2 only:
-- 
1.5.4.3


From tsbogend@alpha.franken.de Wed Sep 10 09:32:07 2008
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Subject: Re: [PATCH 1/1] mips: clear IV bit in CP0 cause if the CPU doesn't support divec
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On Tue, Sep 09, 2008 at 10:15:25AM +0200, Thomas Petazzoni wrote:
> +	else {
> +		clear_c0_cause(CAUSEF_IV);
> +	}

so we now touch a bit, which is at least marked reserved for R10k CPUs
and hope nobody did something else with it ?

Thomas.

-- 
Crap can work. Given enough thrust pigs will fly, but it's not necessary a
good idea.                                                [ RFC1925, 2.3 ]

From kevink@paralogos.com Wed Sep 10 12:08:56 2008
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Subject: Re: [PATCH 1/1] mips: clear IV bit in CP0 cause if the CPU doesn't
 support divec
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I think it's important to know whether it's U-Boot or Linux that's confused.
As Thomas Bogendoerfer pointed out, it's not good practice to flip bits 
whose
use is unknown to the kernel.  If in fact the CPU in question does 
support IV,
was correctly identified as such by U-Boot, but isn't recognized by the MIPS
Linux kernel, then we ought to fix Linux to recognize the CPU.  If it 
doesn't
support IV, but U-Boot thought it did, then U-Boot is broken and ought to
be fixed.  If you you're stuck with a broken U-Boot for some reason, then
there ought to be some platform-specific place to put a hack.

          Regards,

          Kevin K.

Thomas Petazzoni wrote:
> When the kernel thinks that the CPU doesn't support the divec feature
> (cpu_has_divec is false), reset the corresponding IV bit in the CP0
> cause register, so that things will work correctly if the bootloader
> had a different idea of the CPU support of the divec feature.
>
> The problem has been found while trying to boot a 2.6.24 kernel for
> the Qemu board using U-Boot inside Qemu. For the same CPU type, U-Boot
> thinks that divec is supported, and the kernel doesn't. So U-Boot sets
> the IV bit, but when the kernel boots and doesn't reset the IV bit,
> things break when the first interrupts occur. The Qemu board has been
> removed from the kernel in 2.6.25, but the problem might also occur
> with other platforms.
>
> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> Cc: Thiemo Seufer <ths@networkno.de>
> Cc: linux-mips@linux-mips.org
> ---
>  arch/mips/kernel/traps.c |    3 +++
>  1 files changed, 3 insertions(+), 0 deletions(-)
>
> diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
> index 6bee290..8b1e507 100644
> --- a/arch/mips/kernel/traps.c
> +++ b/arch/mips/kernel/traps.c
> @@ -1467,6 +1467,9 @@ void __cpuinit per_cpu_trap_init(void)
>  		} else
>  			set_c0_cause(CAUSEF_IV);
>  	}
> +	else {
> +		clear_c0_cause(CAUSEF_IV);
> +	}
>  
>  	/*
>  	 * Before R2 both interrupt numbers were fixed to 7, so on R2 only:
>   

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From:	"Ramgopal Kota" <rkota@broadcom.com>
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Date:	Wed, 10 Sep 2008 07:31:21 -0700
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Hi,

I am facing a problem with MTD partitions with linux 2.6.
I have a Spansion Flash of 8MB. where the number of erase regions are 2 ,

1st erase region has 127 64KB sectors
2nd erase region has 8 8KB sectors.   ( This is at the end of the flash)

I want to create 4 partitions.
NAME  --  SIZE
BOOT  --  128KB.
OS      --  2MB
JFFS    --  (8MB - 8KB)
DUMP   --  8KB

Kernel prints a error message that "JFFS Partition is read-only".
Can a partition span across 2 various erase regions ?
(I see that there is a check for the same in the mtdpart.c while adding a p=
artition.)

Is there any work-around using MTDPART_OFS_APPEND & MTDPART_OFS_NXTBLK flag=
s ??
Any help is highly appreciable ??

Ramgopal Kota

--_000_6C370B347C3FE8438C9692873287D2E110068DF9C3SJEXCHCCR01co_
Content-Type: text/html;
 charset=us-ascii
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<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META http-equiv=3DContent-Type content=3D"text/html; charset=3Dus-ascii">
<META content=3D"MSHTML 6.00.2900.3314" name=3DGENERATOR></HEAD>
<BODY>
<DIV><SPAN class=3D828112214-10092008><FONT face=3DVerdana=20
size=3D2>Hi,</FONT></SPAN></DIV>
<DIV><SPAN class=3D828112214-10092008><FONT face=3DVerdana=20
size=3D2></FONT></SPAN>&nbsp;</DIV>
<DIV><SPAN class=3D828112214-10092008><FONT face=3DVerdana size=3D2>I am fa=
cing a=20
problem with MTD partitions with linux 2.6.</FONT></SPAN></DIV>
<DIV><SPAN class=3D828112214-10092008><FONT face=3DVerdana size=3D2>I have =
a Spansion=20
Flash of 8MB. where the number of erase regions are 2 ,</FONT></SPAN></DIV>
<DIV><SPAN class=3D828112214-10092008><FONT face=3DVerdana=20
size=3D2></FONT></SPAN>&nbsp;</DIV>
<DIV><SPAN class=3D828112214-10092008><FONT face=3DVerdana size=3D2>1st era=
se region=20
has 127 64KB sectors</FONT></SPAN></DIV>
<DIV><SPAN class=3D828112214-10092008><FONT face=3DVerdana size=3D2>2nd era=
se region=20
has 8 8KB sectors.&nbsp;&nbsp; ( This is at the end of the=20
flash)</FONT></SPAN></DIV>
<DIV><SPAN class=3D828112214-10092008><FONT face=3DVerdana=20
size=3D2></FONT></SPAN>&nbsp;</DIV>
<DIV><SPAN class=3D828112214-10092008><FONT face=3DVerdana size=3D2>I want =
to=20
create&nbsp;4 partitions.</FONT></SPAN></DIV>
<DIV><SPAN class=3D828112214-10092008><FONT face=3DVerdana size=3D2>NAME&nb=
sp;=20
--&nbsp; SIZE</FONT></SPAN></DIV>
<DIV><SPAN class=3D828112214-10092008><FONT face=3DVerdana size=3D2>BOOT&nb=
sp;=20
--&nbsp; 128KB.</FONT></SPAN></DIV>
<DIV><SPAN class=3D828112214-10092008><FONT face=3DVerdana=20
size=3D2>OS&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; --&nbsp; 2MB</FONT></SPAN></DIV>
<DIV><SPAN class=3D828112214-10092008><FONT face=3DVerdana=20
size=3D2>JFFS&nbsp;&nbsp;&nbsp; --&nbsp; (8MB - 8KB)</FONT></SPAN></DIV>
<DIV><SPAN class=3D828112214-10092008></SPAN><SPAN class=3D828112214-100920=
08><FONT=20
face=3DVerdana size=3D2>DUMP&nbsp;&nbsp; --&nbsp; 8KB</FONT></SPAN></DIV>
<DIV><SPAN class=3D828112214-10092008><FONT face=3DVerdana=20
size=3D2></FONT></SPAN>&nbsp;</DIV>
<DIV><SPAN class=3D828112214-10092008><FONT face=3DVerdana size=3D2>Kernel =
prints a=20
error message that "JFFS Partition is read-only".</FONT></SPAN></DIV>
<DIV><SPAN class=3D828112214-10092008><FONT face=3DVerdana size=3D2>Can a p=
artition=20
span across 2 various erase regions ?</FONT></SPAN></DIV>
<DIV><SPAN class=3D828112214-10092008><FONT face=3DVerdana size=3D2>(I see =
that there=20
is a check for the same in the mtdpart.c while adding a=20
partition.)</FONT></SPAN></DIV>
<DIV><SPAN class=3D828112214-10092008><FONT face=3DVerdana=20
size=3D2></FONT></SPAN>&nbsp;</DIV>
<DIV><SPAN class=3D828112214-10092008><FONT face=3DVerdana size=3D2>Is ther=
e any=20
work-around using <FONT face=3DArial size=3D2>MTDPART_OFS_APPEND &amp; <FON=
T=20
face=3DArial size=3D2>MTDPART_OFS_NXTBLK flags ??</FONT></FONT></FONT></SPA=
N></DIV>
<DIV><SPAN class=3D828112214-10092008><FONT face=3DArial size=3D2>Any help =
is highly=20
appreciable ??</FONT></SPAN></DIV>
<DIV><SPAN class=3D828112214-10092008><FONT face=3DArial=20
size=3D2></FONT></SPAN>&nbsp;</DIV>
<DIV><SPAN class=3D828112214-10092008><FONT face=3DArial size=3D2>Ramgopal=
=20
Kota</FONT></SPAN></DIV></BODY></HTML>

--_000_6C370B347C3FE8438C9692873287D2E110068DF9C3SJEXCHCCR01co_--


From anemo@mba.ocn.ne.jp Wed Sep 10 16:06:47 2008
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Subject: Re: [PATCH 1/2] ide: Add tx4939ide driver
From:	Atsushi Nemoto <anemo@mba.ocn.ne.jp>
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On Tue, 9 Sep 2008 17:44:59 +0100, Alan Cox <alan@lxorguk.ukuu.org.uk> wrote:
> > command/status registers, but the register layout is swapped on big
> > endian.  There are some other endian issue and some special registers
> > which requires many custom dma_ops/port_ops routines.
> 
> It would probably be a lot cleaner using the libata framework, and also
> go obsolete less soon.

Yes, that's future plan.

> > +#define TX4939IDE_writeb(val, base, reg) \
> > +	__raw_writeb(val, (void __iomem *)((base) + TX4939IDE_REG8(reg)))
> 
> It's generally frowned upon to hide all the detail in macros, it is much
> easier to read and understand the code if you don't do this.

OK, I'll try to make much readble.

> > +#define TX4939IDE_BASE(hwif)	((hwif)->io_ports.data_addr & ~0xfff)
> 
> Why do you have void __iomem casts all over the write methods not in the
> _BASE() method - that would let sparse do its job properly

Indeed. I'll do it.

> > +	for (i = 0; i < MAX_DRIVES; i++) {
> > +		if (drive != &hwif->drives[i] &&
> 
> You don't actually need the first test. This also appears wrong. In your
> tests MW_DMA_0 is 'faster' than PIO4 but in fact MW_DMA_0 PIO timings are
> *slower* than PIO4 so the mode is not in fact slower.
> 
> > +	case XFER_MW_DMA_2:
> > +	case XFER_MW_DMA_1:
> > +	case XFER_MW_DMA_0:
> > +	case XFER_PIO_4:
> > +		value |= 0x0400;
> > +		break;
> 
> This looks odd according to the speed tables. Can you clarify what is
> going on ?

As you and Sergei pointed out, the code seems somewhat broken.  I'll
rework on it.

> > +#ifdef __BIG_ENDIAN
> > +	{
> > +		unsigned int *table = hwif->dmatable_cpu;
> > +		while (1) {
> > +			cpu_to_le64s((u64 *)table);
> > +			if (*table & 0x80000000)
> > +				break;
> 
> You modify the table but you never ensure the data is not still in
> temporary variables from the compiler or flushed from cache

The dmatable_cpu is allocated by pci_alloc_consistent so that flush is
not needed.  But... this is not PCI device.  I should not use
ide_allocate_dma_engine().  I'll fix it.

Thank you for review.
---
Atsushi Nemoto

From anemo@mba.ocn.ne.jp Wed Sep 10 16:12:55 2008
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Subject: Re: [PATCH 1/2] ide: Add tx4939ide driver
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On Tue, 09 Sep 2008 21:08:14 +0400, Sergei Shtylyov <sshtylyov@ru.mvista.com> wrote:
> >>+#define TX4939IDE_BASE(hwif)	((hwif)->io_ports.data_addr & ~0xfff)
> 
> > Why do you have void __iomem casts all over the write methods not in the
> > _BASE() method - that would let sparse do its job properly
> 
>     I don't get why there's need for & at all -- isn't IDE data register 
> address always on 4K boundary?

On little endian, yes.  On big endian, this controller flips addr[2:0].

---
Atsushi Nemoto

From skuribay@ruby.dti.ne.jp Wed Sep 10 16:29:11 2008
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Subject: Re: [PATCH 1/1] mips: clear IV bit in CP0 cause if the CPU doesn't
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Kevin D. Kissell wrote:
> I think it's important to know whether it's U-Boot or Linux that's confused.
> As Thomas Bogendoerfer pointed out, it's not good practice to flip bits whose
> use is unknown to the kernel.  If in fact the CPU in question does support IV,
> was correctly identified as such by U-Boot, but isn't recognized by the MIPS
> Linux kernel, then we ought to fix Linux to recognize the CPU.  If it doesn't
> support IV, but U-Boot thought it did, then U-Boot is broken and ought to
> be fixed.  If you you're stuck with a broken U-Boot for some reason, then
> there ought to be some platform-specific place to put a hack.

It seems the culprit is U-Boot/MIPS `qemu-mips' target. It apparently
sets IV bit in its local initialization.

u-boot/board/qemu-mips/lowlevel_init.S
---------------------------------------
http://git.denx.de/?p=u-boot.git;a=blob;f=board/qemu-mips/lowlevel_init.S;hb=HEAD

/* Memory sub-system initialization code */

#include <config.h>
#include <asm/regdef.h>
#include <asm/mipsregs.h>

	.text
	.set noreorder
	.set mips32

	.globl	lowlevel_init
lowlevel_init:

	/*
	 * Step 2) Establish Status Register
	 * (set BEV, clear ERL, clear EXL, clear IE)
	 */
	li	t1, 0x00400000
	mtc0	t1, CP0_STATUS

	/*
	 * Step 3) Establish CP0 Config0
	 * (set K0=3)
	 */
	li	t1, 0x00000003
	mtc0	t1, CP0_CONFIG

	/*
	 * Step 7) Establish Cause
	 * (set IV bit)
	 */
	li	t1, 0x00800000
	mtc0	t1, CP0_CAUSE

	/* Establish Wired (and Random) */
	mtc0	zero, CP0_WIRED
	nop

	jr	ra
	nop

--->8--->8--->8--->8---


On the other hand, a normal U-Boot/MIPS startup routine doesn't set any
CP0.CAUSE bits; it just clears all bits right after system reset.

u-boot/cpu/mips/start.S
------------------------
http://git.denx.de/?p=u-boot.git;a=blob;f=cpu/mips/start.S;hb=HEAD

	(snipped)

	/* Clear watch registers.
	 */
	mtc0	zero, CP0_WATCHLO
	mtc0	zero, CP0_WATCHHI

	/* WP(Watch Pending), SW0/1 should be cleared. */
	mtc0	zero, CP0_CAUSE

	setup_c0_status_reset

	/* Init Timer */
	mtc0	zero, CP0_COUNT
	mtc0	zero, CP0_COMPARE

	(snipped)

So this issue only happens on U-Boot/MIPS `qemu-mips' target, I think.


  Shinya


From anemo@mba.ocn.ne.jp Wed Sep 10 16:32:19 2008
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Subject: Re: [PATCH 1/2] ide: Add tx4939ide driver
From:	Atsushi Nemoto <anemo@mba.ocn.ne.jp>
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On Tue, 09 Sep 2008 21:50:32 +0400, Sergei Shtylyov <sshtylyov@ru.mvista.com> wrote:
> > +static void tx4939ide_set_mode(ide_drive_t *drive, const u8 speed)
> > +{
> > +	ide_hwif_t *hwif = HWIF(drive);
> > +	unsigned long base = TX4939IDE_BASE(hwif);
> > +	int is_slave = drive->dn & 1;
> > +	u16 value;
> > +	int safe_speed = speed;
> > +	int i;
> > +
> > +	for (i = 0; i < MAX_DRIVES; i++) {
> 
>     Use ide_get_paired_drive() ISO this loop.

Thanks.  That's what I needed.

> > +		if (drive != &hwif->drives[i] &&
> > +		    (hwif->drives[i].dev_flags & IDE_DFLAG_PRESENT))
> > +			safe_speed = min(safe_speed,
> > +					 (int)hwif->drives[i].current_speed);
> 
>     You shouldn't clamp the command PIO mode timings like this, and shouldn't 
> do it at all when DMA mode is set. Call ide_get_best_pio_mode(255, 4) to get 
> the mate drive's fastest PIO mode which should be a clamping value.
> 
> > +	/* Command Transfer Mode Select */
> > +	switch (safe_speed) {
> > +	case XFER_UDMA_5:
> > +	case XFER_UDMA_4:
> > +	case XFER_UDMA_3:
> > +	case XFER_UDMA_2:
> > +	case XFER_UDMA_1:
> > +	case XFER_UDMA_0:
> > +	case XFER_MW_DMA_2:
> 
>     You shouldn't change the command PIO mode when DMA mode is selected.

But the "Command Transfer Mode Select" bits affects access timings on
setting task registers for DMA command.  Hmm... do you mean I should
not do it _here_?

> > +	case XFER_MW_DMA_1:
> > +	case XFER_MW_DMA_0:
> > +	case XFER_PIO_4:
> 
>     MWDMA0/1 timings don't match PIO4, they are [much] slower.

Oh thanks.  I will fix it.

> > +		hwif->select_data =
> > +			(hwif->select_data & ~0xffff0000) | (value << 16);
> 
>     Why not just 0x0000ffff?
> 
> > +	else
> > +		hwif->select_data = (hwif->select_data & ~0x0000ffff) | value;
> 
>     Why not just 0xffff0000?

Indeed.

> > +static void tx4939ide_set_pio_mode(ide_drive_t *drive, const u8 pio)
> > +{
> > +	tx4939ide_set_mode(drive, XFER_PIO_0 + pio);
> > +}
> 
>     I suggest that you implement tx4939ide_set_{dma|pio}_mode() as seperate 
> functions, possibly using a common function to do a final part. These 2 
> methods are quite different functionally.
> 
> > +static int tx4939ide_dma_setup(ide_drive_t *drive)
> > +{
> > +	ide_hwif_t *hwif = HWIF(drive);
> > +	unsigned long base = TX4939IDE_BASE(hwif);
> > +	int is_slave = drive->dn & 1;
> > +	unsigned int nframes;
> > +	int rc, i;
> > +	unsigned int sect_size = queue_hardsect_size(drive->queue);
> > +	u16 select_data;
> > +
> > +	select_data = (hwif->select_data >> (is_slave ? 16 : 0)) & 0xffff;
> > +	TX4939IDE_writew(select_data, base, Sys_Ctl);
> 
>     Unfortunately, programming the timings from the dma_setup() method isn't 
> enough since it won't be called for PIO transfers.  You'll have to use the 
> selectproc() method.

Thanks.  I should rework whole timing setup code.

---
Atsushi Nemoto

From anemo@mba.ocn.ne.jp Wed Sep 10 16:44:02 2008
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From:	Atsushi Nemoto <anemo@mba.ocn.ne.jp>
To:	linux-mips@linux-mips.org
Cc:	ralf@linux-mips.org
Subject: [PATCH] TXx9: Fix RBTX4939 ethernet address initialization
Date:	Thu, 11 Sep 2008 00:44:04 +0900
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Fix location of ethernet adddress when booted from external ROM.

Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
---
This is a patch for linux-queue tree.  This patch can be folded into
the patch titled "TXx9: Add RBTX4939 board support".

 arch/mips/txx9/rbtx4939/setup.c |   13 +++++++++----
 1 files changed, 9 insertions(+), 4 deletions(-)

diff --git a/arch/mips/txx9/rbtx4939/setup.c b/arch/mips/txx9/rbtx4939/setup.c
index 277864d..df324f8 100644
--- a/arch/mips/txx9/rbtx4939/setup.c
+++ b/arch/mips/txx9/rbtx4939/setup.c
@@ -249,16 +249,21 @@ static void __init rbtx4939_device_init(void)
 #if defined(CONFIG_TC35815) || defined(CONFIG_TC35815_MODULE)
 	int i, j;
 	unsigned char ethaddr[2][6];
+	u8 bdipsw = readb(rbtx4939_bdipsw_addr) & 0x0f;
 	for (i = 0; i < 2; i++) {
 		unsigned long area = CKSEG1 + 0x1fff0000 + (i * 0x10);
-		if (readb(rbtx4939_bdipsw_addr) & 8) {
+		if (bdipsw == 0)
+			memcpy(ethaddr[i], (void *)area, 6);
+		else {
 			u16 buf[3];
-			area -= 0x03000000;
+			if (bdipsw & 8)
+				area -= 0x03000000;
+			else
+				area -= 0x01000000;
 			for (j = 0; j < 3; j++)
 				buf[j] = le16_to_cpup((u16 *)(area + j * 2));
 			memcpy(ethaddr[i], buf, 6);
-		} else
-			memcpy(ethaddr[i], (void *)area, 6);
+		}
 	}
 	tx4939_ethaddr_init(ethaddr[0], ethaddr[1]);
 #endif
-- 
1.5.6.3


From sshtylyov@ru.mvista.com Wed Sep 10 16:54:39 2008
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	bzolnier@gmail.com, ralf@linux-mips.org
Subject: Re: [PATCH 1/2] ide: Add tx4939ide driver
References: <20080910.010824.07456636.anemo@mba.ocn.ne.jp>	<48C6B768.4010200@ru.mvista.com> <20080911.003222.51867360.anemo@mba.ocn.ne.jp>
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Hello.

Atsushi Nemoto wrote:

>>>+		if (drive != &hwif->drives[i] &&
>>>+		    (hwif->drives[i].dev_flags & IDE_DFLAG_PRESENT))
>>>+			safe_speed = min(safe_speed,
>>>+					 (int)hwif->drives[i].current_speed);

>>    You shouldn't clamp the command PIO mode timings like this, and shouldn't 
>>do it at all when DMA mode is set. Call ide_get_best_pio_mode(255, 4) to get 
>>the mate drive's fastest PIO mode which should be a clamping value.

>>>+	/* Command Transfer Mode Select */
>>>+	switch (safe_speed) {
>>>+	case XFER_UDMA_5:
>>>+	case XFER_UDMA_4:
>>>+	case XFER_UDMA_3:
>>>+	case XFER_UDMA_2:
>>>+	case XFER_UDMA_1:
>>>+	case XFER_UDMA_0:
>>>+	case XFER_MW_DMA_2:

>>    You shouldn't change the command PIO mode when DMA mode is selected.

> But the "Command Transfer Mode Select" bits affects access timings on
> setting task registers for DMA command.

    So what? PIO and DMA are different protocols on IDE bus, so they shouldn't 
affect each other. The IDE core will always tune the best PIO mode for you, so 
the optimal command timings will be set.

>  Hmm... do you mean I should not do it _here_?

    You should only change command PIO timings only when PIO mode is changed.

>>>+	case XFER_MW_DMA_1:
>>>+	case XFER_MW_DMA_0:
>>>+	case XFER_PIO_4:

>>    MWDMA0/1 timings don't match PIO4, they are [much] slower.

> Oh thanks.  I will fix it.

    Just do not change PIO mode when selecitng DMA mode at all.

>>>+		hwif->select_data =
>>>+			(hwif->select_data & ~0xffff0000) | (value << 16);

>>    Why not just 0x0000ffff?

>>>+	else
>>>+		hwif->select_data = (hwif->select_data & ~0x0000ffff) | value;

>>    Why not just 0xffff0000?

> Indeed.

    Acltually, this is somewhat wrong WRT the programming the command PIO 
timings in the bits 8..10: they should be set to the same value (matching to 
the last "safest" PIO mode set) for both drives, so you should only "switch" 
bits 4 thru 7 of this register.

MBR, Sergei


From sshtylyov@ru.mvista.com Wed Sep 10 17:33:02 2008
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	linux-ide@vger.kernel.org, bzolnier@gmail.com, ralf@linux-mips.org
Subject: Re: [PATCH 1/2] ide: Add tx4939ide driver
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Hello, I just wrote:

>    Acltually, this is somewhat wrong WRT the programming the command PIO 
> timings in the bits 8..10: they should be set to the same value 

    Hmm, probably isn't actually wrong, though usually IDE controllers have a 
single command timings register per channel.

MBR, Sergei


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From:	Ralf Baechle <ralf@linux-mips.org>
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	support divec
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On Wed, Sep 10, 2008 at 01:11:45PM +0200, Kevin D. Kissell wrote:

> I think it's important to know whether it's U-Boot or Linux that's confused.
> As Thomas Bogendoerfer pointed out, it's not good practice to flip bits  
> whose
> use is unknown to the kernel.  If in fact the CPU in question does  
> support IV,
> was correctly identified as such by U-Boot, but isn't recognized by the MIPS
> Linux kernel, then we ought to fix Linux to recognize the CPU.  If it  
> doesn't
> support IV, but U-Boot thought it did, then U-Boot is broken and ought to
> be fixed.  If you you're stuck with a broken U-Boot for some reason, then
> there ought to be some platform-specific place to put a hack.

What happened is this:

        if (cpu_has_divec) {
                if (cpu_has_mipsmt) {
                        unsigned int vpflags = dvpe();
                        set_c0_cause(CAUSEF_IV);
			evpe(vpflags);
		} else
                        set_c0_cause(CAUSEF_IV);
	}

but include/asm-mips/mach-qemu/cpu-feature-overrides.h was defining
cpu_has_divec as 0.  It should have been either undefined (for runtime
probing) or 1.  Iow, it was a platform specific bug.

With the large number of wild pre-MIPS32/64 architecture variants around I
feel a little uneasy to just zero the field unless I know that bit 23
really is the IV bit on a particular processor.  Just as an example, the
RM7000 has the IV bit on bit 24, not bit 23 like MIPS32 and the
functionality also differs a little.

  Ralf

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Subject: Re: [PATCH 1/2] ide: Add tx4939ide driver
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Hello.

Atsushi Nemoto wrote:

> This is the driver for the Toshiba TX4939 SoC ATA controller.
>
> This controller has standard ATA taskfile registers and DMA
> command/status registers, but the register layout is swapped on big
> endian.  There are some other endian issue and some special registers
> which requires many custom dma_ops/port_ops routines.
>
> Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>  

[...]

> diff --git a/drivers/ide/mips/Makefile b/drivers/ide/mips/Makefile
> index 677c7b2..1e0ad98 100644
> --- a/drivers/ide/mips/Makefile
> +++ b/drivers/ide/mips/Makefile
> @@ -1,4 +1,5 @@
>  obj-$(CONFIG_BLK_DEV_IDE_SWARM)		+= swarm.o
>  obj-$(CONFIG_BLK_DEV_IDE_AU1XXX)	+= au1xxx-ide.o
> +obj-$(CONFIG_BLK_DEV_IDE_TX4939)	+= tx4939ide.o
>  
>  EXTRA_CFLAGS    := -Idrivers/ide
> diff --git a/drivers/ide/mips/tx4939ide.c b/drivers/ide/mips/tx4939ide.c
> new file mode 100644
> index 0000000..ba9776d
> --- /dev/null
> +++ b/drivers/ide/mips/tx4939ide.c
> @@ -0,0 +1,762 @@
> +#ifdef __BIG_ENDIAN
> +#define TX4939IDE_REG32(reg)	(TX4939IDE_##reg ^ 4)
> +#define TX4939IDE_REG16(reg)	(TX4939IDE_##reg ^ 6)
> +#define TX4939IDE_REG8(reg)	(TX4939IDE_##reg ^ 7)
> +#else
> +#define TX4939IDE_REG32(reg)	(TX4939IDE_##reg)
> +#define TX4939IDE_REG16(reg)	(TX4939IDE_##reg)
> +#define TX4939IDE_REG8(reg)	(TX4939IDE_##reg)
> +#endif
> +
> +#define TX4939IDE_readl(base, reg) \
> +	__raw_readl((void __iomem *)((base) + TX4939IDE_REG32(reg)))
> +#define TX4939IDE_readw(base, reg) \
> +	__raw_readw((void __iomem *)((base) + TX4939IDE_REG16(reg)))
> +#define TX4939IDE_readb(base, reg) \
> +	__raw_readb((void __iomem *)((base) + TX4939IDE_REG8(reg)))
> +#define TX4939IDE_writel(val, base, reg) \
> +	__raw_writel(val, (void __iomem *)((base) + TX4939IDE_REG32(reg)))
> +#define TX4939IDE_writew(val, base, reg) \
> +	__raw_writew(val, (void __iomem *)((base) + TX4939IDE_REG16(reg)))
> +#define TX4939IDE_writeb(val, base, reg) \
> +	__raw_writeb(val, (void __iomem *)((base) + TX4939IDE_REG8(reg)))
>   

   Why dont you #define __swizzle_addr_[bwlq]() in 
include/asm/mach/magle-port.h?
Or you never use read[bwlq]() accessorts for the SoC registers?

> +static void tx4939ide_check_error_ints(ide_hwif_t *hwif, u16 stat)
> +{
> +	if (stat & TX4939IDE_INT_BUSERR) {
> +		unsigned long base = TX4939IDE_BASE(hwif);
> +		/* reset FIFO */
> +		TX4939IDE_writew(TX4939IDE_readw(base, Sys_Ctl) |
> +				 0x4000,
> +				 base, Sys_Ctl);
>   

   Are you sure bit 14 is self-clearing? The datashhet doesn't seem to 
say that...

> +static void tx4939ide_clear_irq(ide_drive_t *drive)
> +{
> +	ide_hwif_t *hwif;
> +	unsigned long base;
> +	u16 ctl;
> +
> +	/*
> +	 * tx4939ide_dma_test_irq() and tx4939ide_dma_end() do all
> +	 * jobs for DMA case.
> +	 */
> +	if (drive->waiting_for_dma)
> +		return;
> +	hwif = HWIF(drive);
> +	base = TX4939IDE_BASE(hwif);
>   

   I think you might cache the base address in hwif->extra_base to avoid 
masking with ~0xfff every time...

> +static u8 tx4939ide_cable_detect(ide_hwif_t *hwif)
> +{
> +	unsigned long base = TX4939IDE_BASE(hwif);
> +
> +	return (TX4939IDE_readw(base, Sys_Ctl) & 0x2000)
> +		? ATA_CBL_PATA40 : ATA_CBL_PATA80;
>   

   Could you keep ? on the same line as the 1st operand?

> +static int __tx4939ide_dma_setup(ide_drive_t *drive)
> +{
> +	ide_hwif_t *hwif = drive->hwif;
> +	struct request *rq = HWGROUP(drive)->rq;
> +	unsigned int reading;
> +	u8 dma_stat;
> +	unsigned long base = TX4939IDE_BASE(hwif);
> +
> +	if (rq_data_dir(rq))
> +		reading = 0;
> +	else
> +		reading = 1 << 3;
> +
> +	/* fall back to pio! */
> +	if (!ide_build_dmatable(drive, rq)) {
> +		ide_map_sg(drive, rq);
> +		return 1;
> +	}
> +#ifdef __BIG_ENDIAN
> +	{
> +		unsigned int *table = hwif->dmatable_cpu;
> +		while (1) {
> +			cpu_to_le64s((u64 *)table);
> +			if (*table & 0x80000000)
> +				break;
> +			table += 2;
> +		}
> +	}
> +#endif
>   

   Ugh...

> +static int tx4939ide_dma_setup(ide_drive_t *drive)
> +{
> +	ide_hwif_t *hwif = HWIF(drive);
> +	unsigned long base = TX4939IDE_BASE(hwif);
> +	int is_slave = drive->dn & 1;
> +	unsigned int nframes;
> +	int rc, i;
> +	unsigned int sect_size = queue_hardsect_size(drive->queue);
> +	u16 select_data;
> +
> +	select_data = (hwif->select_data >> (is_slave ? 16 : 0)) & 0xffff;
> +	TX4939IDE_writew(select_data, base, Sys_Ctl);
> +	if (is_slave)
> +		TX4939IDE_writew(sect_size / 2, base, Xfer_Cnt_2);
> +	else
> +		TX4939IDE_writew(sect_size / 2, base, Xfer_Cnt_1);
>   

	TX4939IDE_writew(sect_size / 2, base, is_slave ? Xfer_Cnt_2 : Xfer_Cnt_1);

> +	rc = __tx4939ide_dma_setup(drive);
> +	if (rc == 0) {
> +		/* Number of sectors to transfer. */
> +		nframes = 0;
> +		for (i = 0; i < hwif->sg_nents; i++)
> +			nframes += sg_dma_len(&hwif->sg_table[i]);
> +		BUG_ON(nframes % sect_size != 0);
> +		nframes /= sect_size;
> +		BUG_ON(nframes == 0);
> +		TX4939IDE_writew(nframes, base, Sec_Cnt);
>   

   Ugh, it looks much easier in my TC86C001 driver... doesn't 
hwgroup->rq->nr_sectors give you a number of 512 sectors?
Why bother with other (multiple of 512) sizes when you can always 
program transfer in 512-byte sectors? Or was I wrong there?

> +static int tx4939ide_dma_end(ide_drive_t *drive)
> +{
> +	if ((dma_stat & 7) == 0 &&
> +	    (ctl & (TX4939IDE_INT_XFEREND | TX4939IDE_INT_HOST)) ==
> +	    (TX4939IDE_INT_XFEREND | TX4939IDE_INT_HOST))
> +		/* INT_IDE lost... bug? */
> +		return 0;
>   

   You shouldn't fake the BMDMA interrupt. If it's not there, it's not 
there. Or does this actually happen?

> +	return (dma_stat & 7) != 4 ? (0x10 | dma_stat) : 0;
> +}
> +
> +/* returns 1 if dma irq issued, 0 otherwise */
> +static int tx4939ide_dma_test_irq(ide_drive_t *drive)
> +{
> +	ide_hwif_t *hwif = HWIF(drive);
> +	unsigned long base = TX4939IDE_BASE(hwif);
> +	u16 ctl = TX4939IDE_readw(base, int_ctl);
> +	u8 dma_stat, stat;
> +	u16 ide_int;
> +	int found = 0;
> +
> +	tx4939ide_check_error_ints(hwif, ctl);
> +	ide_int = ctl & (TX4939IDE_INT_XFEREND | TX4939IDE_INT_HOST);
> +	switch (ide_int) {
> +	case TX4939IDE_INT_HOST:
> +		/* On error, XFEREND might not be asserted. */
> +		stat = TX4939IDE_readb(base, Alt_DevCtl);
> +		if ((stat & (ATA_BUSY|ATA_DRQ|ATA_ERR)) == ATA_ERR) {
> +			pr_err("%s: detect error %x in %s\n",
> +			       drive->name, stat, __func__);
> +			found = 1;
> +		}

   Again, you shouldn't fake the BMDMA interrupt... this is not needed.

> +		/* FALLTHRU */
> +	case TX4939IDE_INT_XFEREND:
> +		/*
> +		 * If only one of XFERINT and HOST was asserted, mask
> +		 * this interrupt and wait for an another one.  Note
>   

   This comment somewhat contradicts the code which returns 1 if only 
HOST interupt is asserted if ERR is set.

> +		 * that write to bit2 of DMA_stat will clear all
> +		 * mask bits.
> +		 */
> +		ctl |= ide_int << 8;
> +		break;
> +	case TX4939IDE_INT_HOST | TX4939IDE_INT_XFEREND:
> +		dma_stat = TX4939IDE_readb(base, DMA_stat);
> +		if (!(dma_stat & 4))
> +			pr_debug("%s: weired interrupt status. "
>   

   Weird.

> +				 "DMA_stat %#02x int_ctl %#04x\n",
> +				 hwif->name, dma_stat, ctl);
> +		found = 1;
>   

   No fakes -- unless that really happens. :-)

> +static void tx4939ide_hwif_init(ide_hwif_t *hwif)
> +{
> +	unsigned long base = TX4939IDE_BASE(hwif);
> +	int timeout;
> +
> +	/* Soft Reset */
> +	TX4939IDE_writew(0x8000, base, Sys_Ctl);
> +	mmiowb();
> +	udelay(1);	/* at least 20 UPSCLK (100ns for 200MHz GBUSCLK) */
> +	/* ATA Hard Reset */
> +	TX4939IDE_writew(0x0800, base, Sys_Ctl);
> +	timeout = 1000;
> +	while (TX4939IDE_readw(base, Sys_Ctl) & 0x0800) {
> +		if (timeout--)
> +			break;
> +		udelay(1);
> +	}
>   

   Don't do this -- there's nothing gained from the ATA hard reset but 
an extra delay; I removed such stuff from the TC86C001 driver. The IDE 
core will soft-reset the bus if needed...

> #ifdef __BIG_ENDIAN
> +/* custom iops (independent from SWAP_IO_SPACE) */
>   
> +static u8 mm_inb(unsigned long port)
> +{
> +	return (u8)readb((void __iomem *)port);
> +}
> +static void mm_outb(u8 value, unsigned long port)
> +{
> +	writeb(value, (void __iomem *)port);
> +}
> +static void mm_tf_load(ide_drive_t *drive, ide_task_t *task)
> +{
>   
[...]
> +	if (task->tf_flags & IDE_TFLAG_OUT_DEVICE) {
> +		unsigned long base = TX4939IDE_BASE(hwif);
> +		mm_outb((tf->device & HIHI) | drive->select,
> +			 io_ports->device_addr);
>   

   I'm seeing no sense in re-defining so far...

> +		/* Fix ATA100 CORE System Control Register */
> +		TX4939IDE_writew(TX4939IDE_readw(base, Sys_Ctl) & 0x07f0,
> +				 base, Sys_Ctl);
>   

   Ah... you're doing it here (but not in LE mode?). I think to avoid 
duplicating ide_tf_load() you need ot use selectproc().

> +	}
> +}
> +static void mm_tf_read(ide_drive_t *drive, ide_task_t *task)
> +{
> +	ide_hwif_t *hwif = drive->hwif;
> +	struct ide_io_ports *io_ports = &hwif->io_ports;
> +	struct ide_taskfile *tf = &task->tf;
> +
> +	if (task->tf_flags & IDE_TFLAG_IN_DATA) {
>   

   I wish there was no such flag...

> +		u16 data;
> +
> +		data = __raw_readw((void __iomem *)io_ports->data_addr);
>   

    Ugh...

> +static void mm_insw_swap(unsigned long port, void *addr, u32 count)
> +{
> +	unsigned short *ptr = addr;
> +	unsigned long size = count * 2;
> +	port &= ~1;
> +	while (count--)
> +		*ptr++ = le16_to_cpu(__raw_readw((void __iomem *)port));
> +	__ide_flush_dcache_range((unsigned long)addr, size);
>   

   Why is this needed BTW?

> +static const struct ide_tp_ops tx4939ide_tp_ops = {
> +	.exec_command		= ide_exec_command,
> +	.read_status		= ide_read_status,
> +	.read_altstatus		= ide_read_altstatus,
> +	.read_sff_dma_status	= tx4939ide_read_sff_dma_status,
>   

   Hum, it should be re-defined in both LE and BE mode (but actually not 
called anyway).

> +
> +	.set_irq		= ide_set_irq,
> +
> +	.tf_load		= mm_tf_load,
> +	.tf_read		= mm_tf_read,
> +
> +	.input_data		= mmio_input_data_swap,
> +	.output_data		= mmio_output_data_swap,
> +};
> +#endif	/* __BIG_ENDIAN */
> +
> +static const struct ide_port_info tx4939ide_port_info __initdata = {
> +	.init_hwif = tx4939ide_hwif_init,
> +	.init_dma = tx4939ide_init_dma,
> +	.port_ops = &tx4939ide_port_ops,
> +	.dma_ops = &tx4939ide_dma_ops,
> +#ifdef __BIG_ENDIAN
> +	.tp_ops = &tx4939ide_tp_ops,
> +#endif
> +	.host_flags = IDE_HFLAG_MMIO,
> +	.pio_mask = ATA_PIO4,
> +	.mwdma_mask = ATA_MWDMA2,
> +	.swdma_mask = ATA_SWDMA2,
>   

   No, SWDMA isn't supported.

> +	.udma_mask = ATA_UDMA5,
> +};
> +
> +static int __init tx4939ide_probe(struct platform_device *pdev)
> +{
> +	hw_regs_t hw;
> +	hw_regs_t *hws[] = { &hw, NULL, NULL, NULL };
> +	struct ide_host *host;
> +	struct resource *res;
> +	int irq;
> +	unsigned long mapbase;
> +	int ret;
> +
> +	irq = platform_get_irq(pdev, 0);
> +	if (irq < 0)
> +		return -ENODEV;
> +	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +	if (!res)
> +		return -ENODEV;
> +
> +	mapbase = (unsigned long)devm_ioremap(&pdev->dev, res->start,
> +					      res->end - res->start + 1);
> +	if (!mapbase)
> +		return -EBUSY;
> +	memset(&hw, 0, sizeof(hw));
> +	hw.io_ports.data_addr = mapbase + TX4939IDE_REG8(DATA);
>   

   Wrong, should be TX4939IDE_REG16(). I wonder how it manages to work 
in BE mode with this...

> +#ifdef CONFIG_PM
> +static int tx4939ide_resume(struct platform_device *dev)
> +{
> +	struct ide_host *host = platform_get_drvdata(dev);
> +	ide_hwif_t *hwif = host->ports[0];
> +	unsigned long base = TX4939IDE_BASE(hwif);
> +
> +	tx4939ide_hwif_init(hwif);
>   

   ATA hard reset when coming out of suspend? Nice... :-)

MBR, Sergei



From ddaney@avtrex.com Thu Sep 11 06:34:54 2008
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Subject: [Patch 0/6] MIPS: Hardware watch register support for gdb (version
 4).
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Esteemed kernel hackers,

To follow is my forth pass at MIPS watch register support.

This version has been tested on:

* MIPS 4KEc (mips32) with a single set of watch registers watchhi not
  reporting I, R, and W conditions.

* MIPS 4KEc (mips32r2) with four sets of watch registers.

* R5000 SGI O2 (mips4 64bit) with no watch register support.

The patches are against 2.6.27-rc6

To use the patch you will need a suitably patched version of gdb.  The
patch against the HEAD of gdb's cvs can be found here:

http://sourceware.org/ml/gdb-patches/2008-09/msg00230.html

The previous version of this patch is here:
http://www.linux-mips.org/cgi-bin/mesg.cgi?a=linux-mips&i=48B71ADD.601%40avtrex.com

The main changes from the previous version are as follows...

* The characteristics of each watch register set are communicated via
  ptrace because according to the mips32 reference, each set can have
  different masks and I, R, W bit support.  Previously only the
  characteristics of the first set were returned.

* The alignment of the structures passed via ptrace are explicitly
  specified as various versions of gcc align 64-bit objects
  differently.

Six patches to follow.

Thanks
David Daney


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Subject: [Patch 1/6] MIPS: Add HARDWARE_WATCHPOINTS configure option.
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Add HARDWARE_WATCHPOINTS configure option.

This is automatically set for all MIPS32 and MIPS64 processors.

Signed-off-by: David Daney <ddaney@avtrex.com>
---
 arch/mips/Kconfig |    7 +++++++
 1 files changed, 7 insertions(+), 0 deletions(-)

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 49896a2..7c724ea 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -1272,6 +1272,13 @@ config CPU_SUPPORTS_32BIT_KERNEL
 config CPU_SUPPORTS_64BIT_KERNEL
 	bool
 
+#
+# Set to y for ptrace access to watch registers.
+#
+config HARDWARE_WATCHPOINTS
+       bool
+       default y if CPU_MIPS32 || CPU_MIPS64
+
 menu "Kernel type"
 
 choice
-- 
1.5.5.1


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 code.
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Add HARDWARE_WATCHPOINTS definitions and support code.

This is the main support code for the patch.  Here we just add the
code, the following patches hook it up.

Signed-off-by: David Daney <ddaney@avtrex.com>
---
 arch/mips/kernel/Makefile      |    2 +-
 arch/mips/kernel/watch.c       |  188 ++++++++++++++++++++++++++++++++++++++++
 include/asm-mips/cpu-info.h    |    6 ++
 include/asm-mips/processor.h   |   20 ++++
 include/asm-mips/thread_info.h |    2 +
 include/asm-mips/watch.h       |   32 +++++++
 6 files changed, 249 insertions(+), 1 deletions(-)
 create mode 100644 arch/mips/kernel/watch.c
 create mode 100644 include/asm-mips/watch.h

diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile
index 706f939..2504f15 100644
--- a/arch/mips/kernel/Makefile
+++ b/arch/mips/kernel/Makefile
@@ -6,7 +6,7 @@ extra-y		:= head.o init_task.o vmlinux.lds
 
 obj-y		+= cpu-probe.o branch.o entry.o genex.o irq.o process.o \
 		   ptrace.o reset.o setup.o signal.o syscall.o \
-		   time.o topology.o traps.o unaligned.o
+		   time.o topology.o traps.o unaligned.o watch.o
 
 obj-$(CONFIG_CEVT_BCM1480)	+= cevt-bcm1480.o
 obj-$(CONFIG_CEVT_R4K)		+= cevt-r4k.o
diff --git a/arch/mips/kernel/watch.c b/arch/mips/kernel/watch.c
new file mode 100644
index 0000000..e9c4f5d
--- /dev/null
+++ b/arch/mips/kernel/watch.c
@@ -0,0 +1,188 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2008 David Daney
+ */
+
+#include <linux/sched.h>
+
+#include <asm/processor.h>
+#include <asm/watch.h>
+
+/*
+ * Install the watch registers for the current thread.  A maximum of
+ * four registers are installed although the machine may have more.
+ */
+void mips_install_watch_registers(void)
+{
+	struct mips3264_watch_reg_state *watches =
+		&current->thread.watch.mips3264;
+	switch (current_cpu_data.watch_reg_use_cnt) {
+	default:
+		BUG();
+	case 4:
+		write_c0_watchlo3(watches->watchlo[3]);
+		/* Write 1 to the I, R, and W bits to clear them, and
+		   1 to G so all ASIDs are trapped. */
+		write_c0_watchhi3(0x40000007 | watches->watchhi[3]);
+	case 3:
+		write_c0_watchlo2(watches->watchlo[2]);
+		write_c0_watchhi2(0x40000007 | watches->watchhi[2]);
+	case 2:
+		write_c0_watchlo1(watches->watchlo[1]);
+		write_c0_watchhi1(0x40000007 | watches->watchhi[1]);
+	case 1:
+		write_c0_watchlo0(watches->watchlo[0]);
+		write_c0_watchhi0(0x40000007 | watches->watchhi[0]);
+	}
+}
+
+/*
+ * Read back the watchhi registers so the user space debugger has
+ * access to the I, R, and W bits.  A maximum of four registers are
+ * read although the machine may have more.
+ */
+void mips_read_watch_registers(void)
+{
+	struct mips3264_watch_reg_state *watches =
+		&current->thread.watch.mips3264;
+	switch (current_cpu_data.watch_reg_use_cnt) {
+	default:
+		BUG();
+	case 4:
+		watches->watchhi[3] = (read_c0_watchhi3() & 0x0fff);
+	case 3:
+		watches->watchhi[2] = (read_c0_watchhi2() & 0x0fff);
+	case 2:
+		watches->watchhi[1] = (read_c0_watchhi1() & 0x0fff);
+	case 1:
+		watches->watchhi[0] = (read_c0_watchhi0() & 0x0fff);
+	}
+	if (current_cpu_data.watch_reg_use_cnt == 1 &&
+	    (watches->watchhi[0] & 7) == 0) {
+		/* Pathological case of release 1 architecture that
+		 * doesn't set the condition bits.  We assume that
+		 * since we got here, the watch condition was met and
+		 * signal that the conditions requested in watchlo
+		 * were met.  */
+		watches->watchhi[0] |= (watches->watchlo[0] & 7);
+	}
+ }
+
+/*
+ * Disable all watch registers.  Although only four registers are
+ * installed, all are cleared to eliminate the possibility of endless
+ * looping in the watch handler.
+ */
+void mips_clear_watch_registers(void)
+{
+	switch (current_cpu_data.watch_reg_count) {
+	default:
+		BUG();
+	case 8:
+		write_c0_watchlo7(0);
+	case 7:
+		write_c0_watchlo6(0);
+	case 6:
+		write_c0_watchlo5(0);
+	case 5:
+		write_c0_watchlo4(0);
+	case 4:
+		write_c0_watchlo3(0);
+	case 3:
+		write_c0_watchlo2(0);
+	case 2:
+		write_c0_watchlo1(0);
+	case 1:
+		write_c0_watchlo0(0);
+	}
+}
+
+__init void mips_probe_watch_registers(struct cpuinfo_mips *c)
+{
+	unsigned int t;
+
+	if ((c->options & MIPS_CPU_WATCH) == 0)
+		return;
+	/*
+	 * Check which of the I,R and W bits are supported, then
+	 * disable the register.
+	 */
+	write_c0_watchlo0(7);
+	t = read_c0_watchlo0();
+	write_c0_watchlo0(0);
+	c->watch_reg_masks[0] = t & 7;
+
+	/* Write the mask bits and read them back to determine which
+	 * can be used. */
+	c->watch_reg_count = 1;
+	c->watch_reg_use_cnt = 1;
+	t = read_c0_watchhi0();
+	write_c0_watchhi0(t | 0xff8);
+	t = read_c0_watchhi0();
+	c->watch_reg_masks[0] |= (t & 0xff8);
+	if ((t & 0x80000000) == 0)
+		return;
+
+	write_c0_watchlo1(7);
+	t = read_c0_watchlo1();
+	write_c0_watchlo1(0);
+	c->watch_reg_masks[1] = t & 7;
+
+	c->watch_reg_count = 2;
+	c->watch_reg_use_cnt = 2;
+	t = read_c0_watchhi1();
+	write_c0_watchhi1(t | 0xff8);
+	t = read_c0_watchhi1();
+	c->watch_reg_masks[1] |= (t & 0xff8);
+	if ((t & 0x80000000) == 0)
+		return;
+
+	write_c0_watchlo2(7);
+	t = read_c0_watchlo2();
+	write_c0_watchlo2(0);
+	c->watch_reg_masks[2] = t & 7;
+
+	c->watch_reg_count = 3;
+	c->watch_reg_use_cnt = 3;
+	t = read_c0_watchhi2();
+	write_c0_watchhi2(t | 0xff8);
+	t = read_c0_watchhi2();
+	c->watch_reg_masks[2] |= (t & 0xff8);
+	if ((t & 0x80000000) == 0)
+		return;
+
+	write_c0_watchlo3(7);
+	t = read_c0_watchlo3();
+	write_c0_watchlo3(0);
+	c->watch_reg_masks[3] = t & 7;
+
+	c->watch_reg_count = 4;
+	c->watch_reg_use_cnt = 4;
+	t = read_c0_watchhi3();
+	write_c0_watchhi3(t | 0xff8);
+	t = read_c0_watchhi3();
+	c->watch_reg_masks[3] |= (t & 0xff8);
+	if ((t & 0x80000000) == 0)
+		return;
+
+	/* We use at most 4, but probe and report up to 8. */
+	c->watch_reg_count = 5;
+	t = read_c0_watchhi4();
+	if ((t & 0x80000000) == 0)
+		return;
+
+	c->watch_reg_count = 6;
+	t = read_c0_watchhi5();
+	if ((t & 0x80000000) == 0)
+		return;
+
+	c->watch_reg_count = 7;
+	t = read_c0_watchhi6();
+	if ((t & 0x80000000) == 0)
+		return;
+
+	c->watch_reg_count = 8;
+}
diff --git a/include/asm-mips/cpu-info.h b/include/asm-mips/cpu-info.h
index 2de73db..744cd8f 100644
--- a/include/asm-mips/cpu-info.h
+++ b/include/asm-mips/cpu-info.h
@@ -12,6 +12,8 @@
 #ifndef __ASM_CPU_INFO_H
 #define __ASM_CPU_INFO_H
 
+#include <linux/types.h>
+
 #include <asm/cache.h>
 
 /*
@@ -69,6 +71,10 @@ struct cpuinfo_mips {
 	int			tc_id;   /* Thread Context number */
 #endif
 	void 			*data;	/* Additional data */
+	unsigned int		watch_reg_count;   /* Number that exist */
+	unsigned int		watch_reg_use_cnt; /* Usable by ptrace */
+#define NUM_WATCH_REGS 4
+	u16			watch_reg_masks[NUM_WATCH_REGS];
 } __attribute__((aligned(SMP_CACHE_BYTES)));
 
 extern struct cpuinfo_mips cpu_data[];
diff --git a/include/asm-mips/processor.h b/include/asm-mips/processor.h
index a1e4453..18ee58e 100644
--- a/include/asm-mips/processor.h
+++ b/include/asm-mips/processor.h
@@ -105,6 +105,19 @@ struct mips_dsp_state {
 	{0,} \
 }
 
+struct mips3264_watch_reg_state {
+	/* The width of watchlo is 32 in a 32 bit kernel and 64 in a
+	   64 bit kernel.  We use unsigned long as it has the same
+	   property. */
+	unsigned long watchlo[NUM_WATCH_REGS];
+	/* Only the mask and IRW bits from watchhi. */
+	u16 watchhi[NUM_WATCH_REGS];
+};
+
+union mips_watch_reg_state {
+	struct mips3264_watch_reg_state mips3264;
+};
+
 typedef struct {
 	unsigned long seg;
 } mm_segment_t;
@@ -137,6 +150,9 @@ struct thread_struct {
 	/* Saved state of the DSP ASE, if available. */
 	struct mips_dsp_state dsp;
 
+	/* Saved watch register state, if available. */
+	union mips_watch_reg_state watch;
+
 	/* Other stuff associated with the thread. */
 	unsigned long cp0_badvaddr;	/* Last user fault */
 	unsigned long cp0_baduaddr;	/* Last kernel fault accessing USEG */
@@ -193,6 +209,10 @@ struct thread_struct {
 		.dspcontrol	= 0,				\
 	},							\
 	/*							\
+	 * saved watch register stuff				\
+	 */							\
+	.watch = {{{0,},},},					\
+	/*							\
 	 * Other stuff associated with the process		\
 	 */							\
 	.cp0_badvaddr		= 0,				\
diff --git a/include/asm-mips/thread_info.h b/include/asm-mips/thread_info.h
index bb30606..3f76de7 100644
--- a/include/asm-mips/thread_info.h
+++ b/include/asm-mips/thread_info.h
@@ -124,6 +124,7 @@ register struct thread_info *__current_thread_info __asm__("$28");
 #define TIF_32BIT_REGS		22	/* also implies 16/32 fprs */
 #define TIF_32BIT_ADDR		23	/* 32-bit address space (o32/n32) */
 #define TIF_FPUBOUND		24	/* thread bound to FPU-full CPU set */
+#define TIF_LOAD_WATCH		25	/* If set, load watch registers */
 #define TIF_SYSCALL_TRACE	31	/* syscall trace active */
 
 #define _TIF_SYSCALL_TRACE	(1<<TIF_SYSCALL_TRACE)
@@ -140,6 +141,7 @@ register struct thread_info *__current_thread_info __asm__("$28");
 #define _TIF_32BIT_REGS		(1<<TIF_32BIT_REGS)
 #define _TIF_32BIT_ADDR		(1<<TIF_32BIT_ADDR)
 #define _TIF_FPUBOUND		(1<<TIF_FPUBOUND)
+#define _TIF_LOAD_WATCH		(1<<TIF_LOAD_WATCH)
 
 /* work to do on interrupt/exception return */
 #define _TIF_WORK_MASK		(0x0000ffef & ~_TIF_SECCOMP)
diff --git a/include/asm-mips/watch.h b/include/asm-mips/watch.h
new file mode 100644
index 0000000..20126ec
--- /dev/null
+++ b/include/asm-mips/watch.h
@@ -0,0 +1,32 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2008 David Daney
+ */
+#ifndef _ASM_WATCH_H
+#define _ASM_WATCH_H
+
+#include <linux/bitops.h>
+
+#include <asm/mipsregs.h>
+
+void mips_install_watch_registers(void);
+void mips_read_watch_registers(void);
+void mips_clear_watch_registers(void);
+void mips_probe_watch_registers(struct cpuinfo_mips *c);
+
+#ifdef CONFIG_HARDWARE_WATCHPOINTS
+#define __restore_watch() do {						\
+	if (unlikely(test_bit(TIF_LOAD_WATCH,				\
+			      &current_thread_info()->flags))) {	\
+		mips_install_watch_registers();				\
+	}								\
+} while (0)
+
+#else
+#define __restore_watch() do {} while (0)
+#endif
+
+#endif /* _ASM_WATCH_H */
-- 
1.5.5.1


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Subject: [Patch 3/6] MIPS: Probe watch registers and report configuration.
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Probe watch registers and report configuration.

Probe for watch register characteristics, and report them in /proc/cpuinfo.

Signed-off-by: David Daney <ddaney@avtrex.com>
---
 arch/mips/kernel/cpu-probe.c |    2 ++
 arch/mips/kernel/proc.c      |    9 +++++++--
 2 files changed, 9 insertions(+), 2 deletions(-)

diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 335a6ae..d0d07b8 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -21,6 +21,7 @@
 #include <asm/fpu.h>
 #include <asm/mipsregs.h>
 #include <asm/system.h>
+#include <asm/watch.h>
 
 /*
  * Not all of the MIPS CPUs have the "wait" instruction available. Moreover,
@@ -685,6 +686,7 @@ static inline void spram_config(void) {}
 static inline void cpu_probe_mips(struct cpuinfo_mips *c)
 {
 	decode_configs(c);
+	mips_probe_watch_registers(c);
 	switch (c->processor_id & 0xff00) {
 	case PRID_IMP_4KC:
 		c->cputype = CPU_4KC;
diff --git a/arch/mips/kernel/proc.c b/arch/mips/kernel/proc.c
index 36f0653..9d60679 100644
--- a/arch/mips/kernel/proc.c
+++ b/arch/mips/kernel/proc.c
@@ -50,8 +50,13 @@ static int show_cpuinfo(struct seq_file *m, void *v)
 	seq_printf(m, "tlb_entries\t\t: %d\n", cpu_data[n].tlbsize);
 	seq_printf(m, "extra interrupt vector\t: %s\n",
 	              cpu_has_divec ? "yes" : "no");
-	seq_printf(m, "hardware watchpoint\t: %s\n",
-	              cpu_has_watch ? "yes" : "no");
+	seq_printf(m, "hardware watchpoint\t: %s",
+		   cpu_has_watch ? "yes, " : "no\n");
+	if (cpu_has_watch)
+		seq_printf(m,
+			   "count: %d, address/irw mask: 0x%04x\n",
+			   cpu_data[n].watch_reg_count,
+			   cpu_data[n].watch_reg_masks[0]);
 	seq_printf(m, "ASEs implemented\t:%s%s%s%s%s%s\n",
 		      cpu_has_mips16 ? " mips16" : "",
 		      cpu_has_mdmx ? " mdmx" : "",
-- 
1.5.5.1


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Subject: [Patch 4/6] MIPS: Watch exception handling for HARDWARE_WATCHPOINTS.
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Watch exception handling for HARDWARE_WATCHPOINTS.

Here we hook up the watch exception handler so that it sends SIGTRAP when
the hardware watch registers are triggered.

Signed-off-by: David Daney <ddaney@avtrex.com>
---
 arch/mips/kernel/genex.S |    4 ++++
 arch/mips/kernel/traps.c |   14 +++++++++-----
 2 files changed, 13 insertions(+), 5 deletions(-)

diff --git a/arch/mips/kernel/genex.S b/arch/mips/kernel/genex.S
index c6ada98..15a9bde 100644
--- a/arch/mips/kernel/genex.S
+++ b/arch/mips/kernel/genex.S
@@ -416,7 +416,11 @@ NESTED(nmi_handler, PT_SIZE, sp)
 	BUILD_HANDLER tr tr sti silent			/* #13 */
 	BUILD_HANDLER fpe fpe fpe silent		/* #15 */
 	BUILD_HANDLER mdmx mdmx sti silent		/* #22 */
+#ifdef 	CONFIG_HARDWARE_WATCHPOINTS
+	BUILD_HANDLER watch watch sti silent		/* #23 */
+#else
 	BUILD_HANDLER watch watch sti verbose		/* #23 */
+#endif
 	BUILD_HANDLER mcheck mcheck cli verbose		/* #24 */
 	BUILD_HANDLER mt mt sti silent			/* #25 */
 	BUILD_HANDLER dsp dsp sti silent		/* #26 */
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index 6bee290..5fbf591 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -42,6 +42,7 @@
 #include <asm/tlbdebug.h>
 #include <asm/traps.h>
 #include <asm/uaccess.h>
+#include <asm/watch.h>
 #include <asm/mmu_context.h>
 #include <asm/types.h>
 #include <asm/stacktrace.h>
@@ -908,12 +909,15 @@ asmlinkage void do_mdmx(struct pt_regs *regs)
 asmlinkage void do_watch(struct pt_regs *regs)
 {
 	/*
-	 * We use the watch exception where available to detect stack
-	 * overflows.
+	 * If the current thread has the watch registers loaded, save
+	 * their values and send SIGTRAP.  Otherwise another thread
+	 * left the registers set, clear them and continue.
 	 */
-	dump_tlb_all();
-	show_regs(regs);
-	panic("Caught WATCH exception - probably caused by stack overflow.");
+	if (test_tsk_thread_flag(current, TIF_LOAD_WATCH)) {
+		mips_read_watch_registers();
+		force_sig(SIGTRAP, current);
+	} else
+		mips_clear_watch_registers();
 }
 
 asmlinkage void do_mcheck(struct pt_regs *regs)
-- 
1.5.5.1


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Subject: [Patch 5/6] MIPS: Scheduler support for HARDWARE_WATCHPOINTS.
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Scheduler support for HARDWARE_WATCHPOINTS.

Here we hook up the scheduler.  Whenever we switch to a new process,
we check to see if the watch registers should be installed, and do it
if needed.

Signed-off-by: David Daney <ddaney@avtrex.com>
---
 include/asm-mips/system.h |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)

diff --git a/include/asm-mips/system.h b/include/asm-mips/system.h
index a944eda..cd30f83 100644
--- a/include/asm-mips/system.h
+++ b/include/asm-mips/system.h
@@ -20,6 +20,7 @@
 #include <asm/cmpxchg.h>
 #include <asm/cpu-features.h>
 #include <asm/dsp.h>
+#include <asm/watch.h>
 #include <asm/war.h>
 
 
@@ -76,6 +77,7 @@ do {									\
 		__restore_dsp(current);					\
 	if (cpu_has_userlocal)						\
 		write_c0_userlocal(current_thread_info()->tp_value);	\
+	__restore_watch();						\
 } while (0)
 
 static inline unsigned long __xchg_u32(volatile int * m, unsigned int val)
-- 
1.5.5.1


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Subject: [Patch 6/6] MIPS: Ptrace support for HARDWARE_WATCHPOINTS
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Ptrace support for HARDWARE_WATCHPOINTS

This is the final part of the watch register patch.  Here we hook up
ptrace so that the user space debugger (gdb), can set and read the
registers.

Signed-off-by: David Daney <ddaney@avtrex.com>
---
 arch/mips/kernel/ptrace.c   |  100 ++++++++++++++++++++++++++++++++++++++++++-
 arch/mips/kernel/ptrace32.c |   15 ++++++
 include/asm-mips/ptrace.h   |   38 ++++++++++++++++
 3 files changed, 152 insertions(+), 1 deletions(-)

diff --git a/arch/mips/kernel/ptrace.c b/arch/mips/kernel/ptrace.c
index 35234b9..ee41f8a 100644
--- a/arch/mips/kernel/ptrace.c
+++ b/arch/mips/kernel/ptrace.c
@@ -46,7 +46,8 @@
  */
 void ptrace_disable(struct task_struct *child)
 {
-	/* Nothing to do.. */
+	/* Don't load the watchpoint registers for the ex-child. */
+	clear_tsk_thread_flag(child, TIF_LOAD_WATCH);
 }
 
 /*
@@ -167,6 +168,93 @@ int ptrace_setfpregs(struct task_struct *child, __u32 __user *data)
 	return 0;
 }
 
+int ptrace_get_watch_regs(struct task_struct *child,
+			  struct pt_watch_regs __user *addr)
+{
+	enum pt_watch_style style;
+	int i;
+
+	if (!cpu_has_watch || current_cpu_data.watch_reg_use_cnt == 0)
+		return -EIO;
+	if (!access_ok(VERIFY_WRITE, addr, sizeof(struct pt_watch_regs)))
+		return -EIO;
+
+#ifdef CONFIG_32BIT
+	style = pt_watch_style_mips32;
+#define WATCH_STYLE mips32
+#else
+	style = pt_watch_style_mips64;
+#define WATCH_STYLE mips64
+#endif
+
+	__put_user(style, &addr->style);
+	__put_user(current_cpu_data.watch_reg_use_cnt,
+		   &addr->WATCH_STYLE.num_valid);
+	for (i = 0; i < current_cpu_data.watch_reg_use_cnt; i++) {
+		__put_user(child->thread.watch.mips3264.watchlo[i],
+			   &addr->WATCH_STYLE.watchlo[i]);
+		__put_user(child->thread.watch.mips3264.watchhi[i] & 0xfff,
+			   &addr->WATCH_STYLE.watchhi[i]);
+		__put_user(current_cpu_data.watch_reg_masks[i],
+			   &addr->WATCH_STYLE.watch_masks[i]);
+	}
+	for (; i < 8; i++) {
+		__put_user(0, &addr->WATCH_STYLE.watchlo[i]);
+		__put_user(0, &addr->WATCH_STYLE.watchhi[i]);
+		__put_user(0, &addr->WATCH_STYLE.watch_masks[i]);
+	}
+
+	return 0;
+}
+
+int ptrace_set_watch_regs(struct task_struct *child,
+			  struct pt_watch_regs __user *addr)
+{
+	int i;
+	int watch_active = 0;
+	unsigned long lt[NUM_WATCH_REGS];
+	u16 ht[NUM_WATCH_REGS];
+
+	if (!cpu_has_watch || current_cpu_data.watch_reg_use_cnt == 0)
+		return -EIO;
+	if (!access_ok(VERIFY_READ, addr, sizeof(struct pt_watch_regs)))
+		return -EIO;
+	/* Check the values. */
+	for (i = 0; i < current_cpu_data.watch_reg_use_cnt; i++) {
+		__get_user(lt[i], &addr->WATCH_STYLE.watchlo[i]);
+#ifdef CONFIG_32BIT
+		if (lt[i] & __UA_LIMIT)
+			return -EINVAL;
+#else
+		if (test_tsk_thread_flag(child, TIF_32BIT_ADDR)) {
+			if (lt[i] & 0xffffffff80000000UL)
+				return -EINVAL;
+		} else {
+			if (lt[i] & __UA_LIMIT)
+				return -EINVAL;
+		}
+#endif
+		__get_user(ht[i], &addr->WATCH_STYLE.watchhi[i]);
+		if (ht[i] & ~0xff8)
+			return -EINVAL;
+	}
+	/* Install them. */
+	for (i = 0; i < current_cpu_data.watch_reg_use_cnt; i++) {
+		if (lt[i] & 7)
+			watch_active = 1;
+		child->thread.watch.mips3264.watchlo[i] = lt[i];
+		/* Set the G bit. */
+		child->thread.watch.mips3264.watchhi[i] = ht[i];
+	}
+
+	if (watch_active)
+		set_tsk_thread_flag(child, TIF_LOAD_WATCH);
+	else
+		clear_tsk_thread_flag(child, TIF_LOAD_WATCH);
+
+	return 0;
+}
+
 long arch_ptrace(struct task_struct *child, long request, long addr, long data)
 {
 	int ret;
@@ -440,6 +528,16 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data)
 				(unsigned long __user *) data);
 		break;
 
+	case PTRACE_GET_WATCH_REGS:
+		ret = ptrace_get_watch_regs(child,
+					(struct pt_watch_regs __user *) addr);
+		break;
+
+	case PTRACE_SET_WATCH_REGS:
+		ret = ptrace_set_watch_regs(child,
+					(struct pt_watch_regs __user *) addr);
+		break;
+
 	default:
 		ret = ptrace_request(child, request, addr, data);
 		break;
diff --git a/arch/mips/kernel/ptrace32.c b/arch/mips/kernel/ptrace32.c
index 76818be..3e219de 100644
--- a/arch/mips/kernel/ptrace32.c
+++ b/arch/mips/kernel/ptrace32.c
@@ -42,6 +42,11 @@ int ptrace_setregs(struct task_struct *child, __s64 __user *data);
 int ptrace_getfpregs(struct task_struct *child, __u32 __user *data);
 int ptrace_setfpregs(struct task_struct *child, __u32 __user *data);
 
+int ptrace_get_watch_regs(struct task_struct *child,
+			  struct pt_watch_regs __user *addr);
+int ptrace_set_watch_regs(struct task_struct *child,
+			  struct pt_watch_regs __user *addr);
+
 /*
  * Tracing a 32-bit process with a 64-bit strace and vice versa will not
  * work.  I don't know how to fix this.
@@ -410,6 +415,16 @@ asmlinkage int sys32_ptrace(int request, int pid, int addr, int data)
 				(unsigned long __user *) (unsigned long) data);
 		break;
 
+	case PTRACE_GET_WATCH_REGS:
+		ret = ptrace_get_watch_regs(child,
+			(struct pt_watch_regs __user *) (unsigned long) addr);
+		break;
+
+	case PTRACE_SET_WATCH_REGS:
+		ret = ptrace_set_watch_regs(child,
+			(struct pt_watch_regs __user *) (unsigned long) addr);
+		break;
+
 	default:
 		ret = ptrace_request(child, request, addr, data);
 		break;
diff --git a/include/asm-mips/ptrace.h b/include/asm-mips/ptrace.h
index 786f7e3..a9f2201 100644
--- a/include/asm-mips/ptrace.h
+++ b/include/asm-mips/ptrace.h
@@ -71,6 +71,44 @@ struct pt_regs {
 #define PTRACE_POKEDATA_3264	0xc3
 #define PTRACE_GET_THREAD_AREA_3264	0xc4
 
+/* Read and write watchpoint registers.  */
+enum pt_watch_style {
+	pt_watch_style_mips32,
+	pt_watch_style_mips64
+};
+struct mips32_watch_regs {
+	uint32_t watchlo[8];
+	/* Lower 16 bits of watchhi. */
+	uint16_t watchhi[8];
+	/* Valid mask and I R W bits.
+	 * bit 0 -- 1 if W bit is usable.
+	 * bit 1 -- 1 if R bit is usable.
+	 * bit 2 -- 1 if I bit is usable.
+	 * bits 3 - 11 -- Valid watchhi mask bits.
+	 */
+	uint16_t watch_masks[8];
+	/* The number of valid watch register pairs.  */
+	uint32_t num_valid;
+} __attribute__ ((aligned (8)));
+
+struct mips64_watch_regs {
+	uint64_t watchlo[8];
+	uint16_t watchhi[8];
+	uint16_t watch_masks[8];
+	uint32_t num_valid;
+} __attribute__ ((aligned (8)));
+
+struct pt_watch_regs {
+	enum pt_watch_style style;
+	union {
+		struct mips32_watch_regs mips32;
+		struct mips32_watch_regs mips64;
+	};
+};
+
+#define PTRACE_GET_WATCH_REGS	0xd0
+#define PTRACE_SET_WATCH_REGS	0xd1
+
 #ifdef __KERNEL__
 
 #include <linux/linkage.h>
-- 
1.5.5.1


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Subject: Re: [Patch 2/6] MIPS: Add HARDWARE_WATCHPOINTS definitions and
 support code.
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On Wed, 10 Sep 2008, David Daney wrote:

Given

> +	case 4:
> +		write_c0_watchlo3(watches->watchlo[3]);
> +		/* Write 1 to the I, R, and W bits to clear them, and
> +		   1 to G so all ASIDs are trapped. */
> +		write_c0_watchhi3(0x40000007 | watches->watchhi[3]);
> +	case 3:
> +		write_c0_watchlo2(watches->watchlo[2]);
> +		write_c0_watchhi2(0x40000007 | watches->watchhi[2]);
> +	case 2:
> +		write_c0_watchlo1(watches->watchlo[1]);
> +		write_c0_watchhi1(0x40000007 | watches->watchhi[1]);
> +	case 1:
> +		write_c0_watchlo0(watches->watchlo[0]);
> +		write_c0_watchhi0(0x40000007 | watches->watchhi[0]);

and

> +	case 4:
> +		watches->watchhi[3] = (read_c0_watchhi3() & 0x0fff);
> +	case 3:
> +		watches->watchhi[2] = (read_c0_watchhi2() & 0x0fff);
> +	case 2:
> +		watches->watchhi[1] = (read_c0_watchhi1() & 0x0fff);
> +	case 1:
> +		watches->watchhi[0] = (read_c0_watchhi0() & 0x0fff);

and

> +	case 8:
> +		write_c0_watchlo7(0);
> +	case 7:
> +		write_c0_watchlo6(0);
> +	case 6:
> +		write_c0_watchlo5(0);
> +	case 5:
> +		write_c0_watchlo4(0);
> +	case 4:
> +		write_c0_watchlo3(0);
> +	case 3:
> +		write_c0_watchlo2(0);
> +	case 2:
> +		write_c0_watchlo1(0);
> +	case 1:
> +		write_c0_watchlo0(0);

do the same for each registers, perhaps it makes sense to create
read_c0_watchhi(), write_c0_watchlo(), and write_c0_watchhi() macros
that take the watchdog register index as a parameter? Then the above can
be turned in simple loops.

> +	write_c0_watchlo0(7);
> +	t = read_c0_watchlo0();
> +	write_c0_watchlo0(0);
> +	c->watch_reg_masks[0] = t & 7;
> +
> +	/* Write the mask bits and read them back to determine which
> +	 * can be used. */
> +	c->watch_reg_count = 1;
> +	c->watch_reg_use_cnt = 1;
> +	t = read_c0_watchhi0();
> +	write_c0_watchhi0(t | 0xff8);
> +	t = read_c0_watchhi0();
> +	c->watch_reg_masks[0] |= (t & 0xff8);
> +	if ((t & 0x80000000) == 0)
> +		return;
> +
> +	write_c0_watchlo1(7);
> +	t = read_c0_watchlo1();
> +	write_c0_watchlo1(0);
> +	c->watch_reg_masks[1] = t & 7;
> +
> +	c->watch_reg_count = 2;
> +	c->watch_reg_use_cnt = 2;
> +	t = read_c0_watchhi1();
> +	write_c0_watchhi1(t | 0xff8);
> +	t = read_c0_watchhi1();
> +	c->watch_reg_masks[1] |= (t & 0xff8);
> +	if ((t & 0x80000000) == 0)
> +		return;
> +
> +	write_c0_watchlo2(7);
> +	t = read_c0_watchlo2();
> +	write_c0_watchlo2(0);
> +	c->watch_reg_masks[2] = t & 7;
> +
> +	c->watch_reg_count = 3;
> +	c->watch_reg_use_cnt = 3;
> +	t = read_c0_watchhi2();
> +	write_c0_watchhi2(t | 0xff8);
> +	t = read_c0_watchhi2();
> +	c->watch_reg_masks[2] |= (t & 0xff8);
> +	if ((t & 0x80000000) == 0)
> +		return;
> +
> +	write_c0_watchlo3(7);
> +	t = read_c0_watchlo3();
> +	write_c0_watchlo3(0);
> +	c->watch_reg_masks[3] = t & 7;
> +
> +	c->watch_reg_count = 4;
> +	c->watch_reg_use_cnt = 4;
> +	t = read_c0_watchhi3();
> +	write_c0_watchhi3(t | 0xff8);
> +	t = read_c0_watchhi3();
> +	c->watch_reg_masks[3] |= (t & 0xff8);
> +	if ((t & 0x80000000) == 0)
> +		return;

Same here

> +	/* We use at most 4, but probe and report up to 8. */
> +	c->watch_reg_count = 5;
> +	t = read_c0_watchhi4();
> +	if ((t & 0x80000000) == 0)
> +		return;
> +
> +	c->watch_reg_count = 6;
> +	t = read_c0_watchhi5();
> +	if ((t & 0x80000000) == 0)
> +		return;
> +
> +	c->watch_reg_count = 7;
> +	t = read_c0_watchhi6();
> +	if ((t & 0x80000000) == 0)
> +		return;
> +
> +	c->watch_reg_count = 8;

and here

BTW, no check for read_c0_watchhi7()?

Gr{oetje,eeting}s,

						Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
							    -- Linus Torvalds

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Hello.

Atsushi Nemoto wrote:

> Add a helper routine to register tx4939ide driver and use it on
> RBTX4939 board.
>
> Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
>   
[...]
> diff --git a/arch/mips/txx9/generic/setup_tx4939.c b/arch/mips/txx9/generic/setup_tx4939.c
> index f14a497..ee00bde 100644
> --- a/arch/mips/txx9/generic/setup_tx4939.c
> +++ b/arch/mips/txx9/generic/setup_tx4939.c
>   
[...]
> @@ -389,6 +390,34 @@ void __init tx4939_mtd_init(int ch)
>  	txx9_physmap_flash_init(ch, start, size, &pdata);
>  }
>  
> +void __init tx4939_ata_init(void)
> +{
> +	__u64 pcfg = __raw_readq(&tx4939_ccfgptr->pcfg);
> +	if (pcfg & (TX4939_PCFG_ATA0MODE | TX4939_PCFG_ATA1MODE)) {
> +		struct resource res[2];
> +		int i;
> +		memset(res, 0, sizeof(res));
> +		for (i = 0; i < 2; i++) {
> +			if (i == 0 &&
> +			    !(pcfg & TX4939_PCFG_ATA0MODE))
> +				continue;
> +			if (i == 1 &&
> +			    (pcfg & (TX4939_PCFG_ATA1MODE |
> +				     TX4939_PCFG_ET1MODE |
> +				     TX4939_PCFG_ET0MODE)) !=
> +			    TX4939_PCFG_ATA1MODE)
> +				continue;
> +			res[0].start = TX4939_ATA_REG(i) & 0xfffffffffULL;
> +			res[0].end = res[0].start + 0x1000 - 1;
> +			res[0].flags = IORESOURCE_MEM;
> +			res[1].start = TXX9_IRQ_BASE + TX4939_IR_ATA(i);
> +			res[1].flags = IORESOURCE_IRQ;
> +			platform_device_register_simple("tx4939ide", i,
> +							res, ARRAY_SIZE(res));
>   

   Hm, why not declare both IDE platform devices statically an then 
register them depending on the TX4939_PCFG_ATA[01]MODE bits?
This loop doesn't look nice. You could at least have used an array to 
check TX4939_PCFG_ATA[01]MODE bitmasks but I think it's better to just 
declare devices statically...

MBR, Sergei



From geert@linux-m68k.org Thu Sep 11 11:09:39 2008
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From:	Geert Uytterhoeven <geert@linux-m68k.org>
To:	Jeremy Fitzhardinge <jeremy@goop.org>
cc:	Ingo Molnar <mingo@elte.hu>, Alex Nixon <alex.nixon@citrix.com>,
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Subject: Re: [PATCH 0/3] Globally defining phys_addr_t
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On Thu, 11 Sep 2008, Jeremy Fitzhardinge wrote:
> This is a repost of a little 3-patch series which Andrew has been
> carrying in -mm.  It cleans up the definition of phys_addr_t to make it
> kernel-wide rather than x86-specific, and fixes up PFN_PHYS() to use it
> to avoid address truncation.
> 
> We currently have a few workarounds for this problem in the tree, but
> Alex found another bug caused by PFN_PHYS(), so it's probably better if
> you bring these patches into tip.git for now.
> 
> PowerPC also defines a phys_addr_t with the same meaning as x86; the
> powerpc arch maintainers are happy with these patches.

If I'm not mistaking, this is also true for some MIPS machines.

Gr{oetje,eeting}s,

						Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
							    -- Linus Torvalds

From dmitri.vorobiev@movial.fi Thu Sep 11 11:16:23 2008
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Subject: Re: 2.6.27-rc5-mm1
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Ping!

It's not nice that one of the MIPS defconfigs doesn't build, is it?

Dmitri

Dmitri Vorobiev wrote:
> Hi,
> 
> <<<<<<<<
> 
> [dmitri.vorobiev@amber linux-2.6.27-rc5]$ make ARCH=mips CROSS_COMPILE=mips-unknown-linux-gnu- malta_defconfig
> #
> # configuration written to .config
> #
> [dmitri.vorobiev@amber linux-2.6.27-rc5]$ make ARCH=mips CROSS_COMPILE=mips-unknown-linux-gnu-
> scripts/kconfig/conf -s arch/mips/Kconfig
> #
> # configuration written to .config
> #
>   CHK     include/linux/version.h
>   CHK     include/linux/utsrelease.h
>   CALL    scripts/checksyscalls.sh
>   CHK     include/linux/compile.h
>   CC      arch/mips/kernel/mips-mt-fpaff.o
> arch/mips/kernel/mips-mt-fpaff.c: In function 'mipsmt_sys_sched_setaffinity':
> arch/mips/kernel/mips-mt-fpaff.c:82: error: 'struct task_struct' has no member named 'euid'
> arch/mips/kernel/mips-mt-fpaff.c:82: error: 'struct task_struct' has no member named 'uid'
> make[1]: *** [arch/mips/kernel/mips-mt-fpaff.o] Error 1
> make: *** [arch/mips/kernel] Error 2
> [dmitri.vorobiev@amber linux-2.6.27-rc5]$
> 
> <<<<<<<<
> 
> Thanks,
> Dmitri
> 
> Andrew Morton wrote:
>> ftp://ftp.kernel.org/pub/linux/kernel/people/akpm/patches/2.6/2.6.27-rc5/2.6.27-rc5-mm1/
>>
>> - This kernel doesn't work very well if selinux is enabled: /proc/net
>>   breaks.
>>
>> - suspend-to-RAM (and probably -to-disk) has regressed on one machine.
>>
>> - Various other weird bumps, bangs and rattles, all of which have been
>>   reported, not all of which have been acknowledgedacpi^W^W^W^W.
>>
>> - I seem to have a very large number of patches outstanding against a
>>   very large number of subsystems.  Many of which have already been sent
>>   to the relevant maintainer at least once.
>>
>>
>> Boilerplate:
>>
>> - See the `hot-fixes' directory for any important updates to this patchset.
>>
>> - To fetch an -mm tree using git, use (for example)
>>
>>   git-fetch git://git.kernel.org/pub/scm/linux/kernel/git/smurf/linux-trees.git tag v2.6.16-rc2-mm1
>>   git-checkout -b local-v2.6.16-rc2-mm1 v2.6.16-rc2-mm1
>>
>> - -mm kernel commit activity can be reviewed by subscribing to the
>>   mm-commits mailing list.
>>
>>         echo "subscribe mm-commits" | mail majordomo@vger.kernel.org
>>
>> - If you hit a bug in -mm and it is not obvious which patch caused it, it is
>>   most valuable if you can perform a bisection search to identify which patch
>>   introduced the bug.  Instructions for this process are at
>>
>>         http://www.zip.com.au/~akpm/linux/patches/stuff/bisecting-mm-trees.txt
>>
>>   But beware that this process takes some time (around ten rebuilds and
>>   reboots), so consider reporting the bug first and if we cannot immediately
>>   identify the faulty patch, then perform the bisection search.
>>
>> - When reporting bugs, please try to Cc: the relevant maintainer and mailing
>>   list on any email.
>>
>> - When reporting bugs in this kernel via email, please also rewrite the
>>   email Subject: in some manner to reflect the nature of the bug.  Some
>>   developers filter by Subject: when looking for messages to read.
>>
>> - Occasional snapshots of the -mm lineup are uploaded to
>>   ftp://ftp.kernel.org/pub/linux/kernel/people/akpm/mm/ and are announced on
>>   the mm-commits list.  These probably are at least compilable.
>>
>> - More-than-daily -mm snapshots may be found at
>>   http://userweb.kernel.org/~akpm/mmotm/.  These are almost certainly not
>>   compileable.
>>
>>
>>
>> Changes since 2.6.27-rc1-mm1:
>>
>>  origin.patch
>>  git-jg-misc.patch
>>  git-libata-all.patch
>>  git-xtensa.patch
>>
>>  git trees
>>
>> -remove-newline-from-the-description-of-module-parameters.patch
>> -pnp-fix-formatting-of-dbg_pnp_show_resources-output.patch
>> -missing-symbol-prefix-on-vmlinuxldsh.patch
>> -missing-symbol-prefix-on-vmlinuxldsh-checkpatch-fixes.patch
>> -mm-hugetlb-dont-crash-when-hpage_shift-is-0.patch
>> -seq_file-fix-bug-when-seq_read-reads-nothing.patch
>> -pci-make-pci_register_driver-a-macro.patch
>> -acpi-add-checking-for-null-early-param.patch
>> -calgary-fix-a-comparison-warning-the-pci-calgary-64-driver.patch
>> -use-warn-in-arch-x86-mm-ioremapc.patch
>> -use-warn-in-arch-x86-mm-pageattrc.patch
>> -use-warn-in-arch-x86-kernel.patch
>> -arch-x86-pci-irqc-attempt-to-clean-up-code-layout.patch
>> -i386-vmalloc-size-fix.patch
>> -x86-calgary-replace-num_dma_pages-with-iommu_num_pages.patch
>> -x86-export-is_uv_system.patch
>> -x86-tracehook_signal_handler.patch
>> -x86-tracehook-syscall.patch
>> -x86-tracehook-asm-syscallh.patch
>> -x86-signals-use-asm-syscallh.patch
>> -x86-tracehook-tif_notify_resume.patch
>> -intel_agp-official-name-for-gm45-chipset.patch
>> -amd64-agp-run-fallback-when-no-bridges-found-not-when-driver-registration-fails.patch
>> -agp-use-dev_printk-when-possible.patch
>> -ppc-use-the-common-ascii-hex-helpers.patch
>> -powerpc-replace-__function__-with-__func__.patch
>> -drivers-base-driverc-remove-unused-to_dev-macro.patch
>> -dev_printk-constify-the-dev-argument.patch
>> -drm-remove-defines-for-non-linux-systems.patch
>> -sis-drm-fix-the-memory-allocator-if-the-sis-fb-is-built-as-a-module.patch
>> -sis-drm-fix-a-pointer-cast-warning.patch
>> -v4l-link-tuner-before-saa7134.patch
>> -v4l-drx397xdc-sparse-annotations.patch
>> -v4l-drx397xdc-replace-__function__-occurrences.patch
>> -v4l-fix-kernel-doc-warning-function-name-and-docbook-filename.patch
>> -drivers-media-video-vinoc-needs-v4l2-ioctlh.patch
>> -i2c-renesas-highlander-fpga-smbus-support.patch
>> -hid-wellspring-device-quirks.patch
>> -migrate_timers-add-comment-use-spinlock_irq.patch
>> -drivers-input-serio-xilinx_ps2c-fix-warning.patch
>> -wistron_btns-add-support-for-fujitsu-siemens-amilo-pro-edition-v3505.patch
>> -maple-allow-removal-and-reinsertion-of-keyboard-driver-module.patch
>> -input-bcm5974-055-smoother-motion-irq-simplification.patch
>> -genksyms-parser-fix-the-__attribute__-rule.patch
>> -genksyms-include-extern-information-in-dumps.patch
>> -libata-scsi-dont-start-hotplug-work-queue-if-hotplug-is-disabled.patch
>> -libata-core-make-sure-that-ata_force_tbl-is-freed-in-case-of-an-error.patch
>> -pata_viac-add-flag-for-vx800-and-add-a-function-for-fixing-internal-bugs-for-via-chipsets.patch
>> -cdrom-dont-check-cdc_play_audio-in-cdrom_count_tracks.patch
>> -drivers-mtd-nand-nandsimc-needs-div64h.patch
>> -jffs2-summary-allocation-dont-use-vmalloc.patch
>> -mtd-diskonchipc-fix-sparse-endian-warnings.patch
>> -mtdpart-handle-remaining-checkpatch-findings.patch
>> -blackfin-nfc-driver-fix-bug-do-not-clobber-the-status-from-the-first-256-bytes-if-operating-on-512-pages.patch
>> -blackfin-nfc-driver-fix-bug-hw-ecc-calc-by-making-sure-we-extract-11-bits-from-each-register-instead-of-10.patch
>> -blackfin-nfc-driver-add-support-for-the-ecc-layout-the-blackfin-bootrom-uses.patch
>> -blackfin-nfc-driver-add-proper-devinit-devexit-markings-to-probe-remove-functions.patch
>> -blackfin-nfc-driver-enable-blackfin-nand-hwecc-support-by-default.patch
>> -blackfin-nfc-driver-use-standard-dev_err-rather-than-printk.patch
>> -blackfin-nfc-driver-cleanup-the-error-exit-path-of-bf5xx_nand_probe-function.patch
>> -drivers-mtd-nand-nandsimc-fix-printk-warnings.patch
>> -mtd-dataflash-otp-support.patch
>> -random32-seeding-improvement.patch
>> -bridge-send-correct-mtu-value-in-pmtu.patch
>> -bridge-send-correct-mtu-value-in-pmtu-revised.patch
>> -net-use-the-common-ascii-hex-helpers.patch
>> -atm-fix-const-assignment-discard-warnings-in-the-atm-networking-driver.patch
>> -atm-fix-direct-casts-of-pointers-to-u32-in-the-interphase-driver.patch
>> -bluetooth-add-quirks-for-a-few-hci_usb-devices.patch
>> -nsc-ircc-default-to-dongle-type-9-on-ibm-hardware.patch
>> -irda-replace-__function__-with-__func__.patch
>> -hysdn-remove-the-packed-attribute-from-poftimstamp_tag.patch
>> -isdn-use-the-common-ascii-hex-helpers.patch
>> -via-velocity-give-a-structure-to-the-rx-tx-fields.patch
>> -via-velocity-fix-sleep-with-spinlock-bug-during-mtu-change.patch
>> -hamradio-add-missing-sanity-check-to-tty-operation.patch
>> -pegasus-add-blacklist-support-to-fix-belkin-bluetooth-dongle.patch
>> -drivers-net-ehea-ehea_mainc-release-mutex-in-error-handling-code.patch
>> -tg3-adapt-tg3-to-use-reworked-pci-pm-code.patch
>> -sky2-adapt-to-use-reworked-pci-pm-code.patch
>> -configure-out-file-locking-features.patch
>> -use-warn-in-kernel-lockdepc.patch
>> -sched-do_wait_for_common-use-signal_pending_state.patch
>> -wait_task_inactive-dont-consider-task-nivcsw.patch
>> -sched-type-fix.patch
>> -netfilter-conntrack_helper-needs-to-include-rculisth.patch
>> -drivers-usb-class-cdc-acmc-use-correct-type-for-cpu-flags.patch
>> -drivers-usb-class-cdc-wdmc-fix-build-with-config_pm=n.patch
>> -cxacru-fix-printk-format-flag-in-error-message.patch
>> -cdc-acm-dont-unlock-acm-mutex-on-error-path.patch
>> -usb-move-usb-mon-up-to-misc-options-in-kconfig.patch
>> -pl2023-remove-usb-id-4348-5523-handled-by-ch341.patch
>> -usb-storage-unusual_devs-entries-for-iriver-t10-and-datafab-cfsm-reader.patch
>> -usb-core-driver-fix-warning.patch
>> -usb-hubc-fix-build-with-config_pm=n.patch
>> -ath5k-mask-out-unneeded-interrupts.patch
>> -ath5k-unify-resets.patch
>> -net-ieee80211-adjust-error-handling.patch
>> -wireless-replace-__function__-with-__func__.patch
>> -xfs-use-get_unaligned_-helpers.patch
>> -xfs-clean-up-stale-references-to-semaphores.patch
>> -xfs-replace-the-xfs-buf-iodone-semaphore-with-a-completion.patch
>> -xfs-extend-completions-to-provide-xfs-object-flush-requirements.patch
>> -xfs-replace-inode-flush-semaphore-with-a-completion.patch
>> -xfs-replace-dquot-flush-semaphore-with-a-completion.patch
>> -xfs-remove-the-sema_t-from-xfs.patch
>> -xtensa-warn-about-including-asm-rwsemh-directly.patch
>> -xtensa-replace-remaining-__function__-occurences.patch
>> -xtensa-use-newer-__spin_lock_unlocked-macro.patch
>> -modules-extend-initcall_debug-functionality-to-the-module-loader.patch
>> -powerpc-86xx-mpc8610_hpcd-add-watchdog-node.patch
>> -kdump-report-actual-value-of-vmcoreinfo_osrelease-in-vmcoreinfo.patch
>> -vt8623fb-fix-kernel-oops.patch
>> -block-ccissc-remove-pointless-curr_queue-calculation.patch
>> -spi-new-orion_spi-driver.patch
>> -spi-new-orion_spi-driver-fixes.patch
>> -relay-fix-4-off-by-one-errors-occuring-when-writing-to-a-cpu-buffer.patch
>> -semaphore-__down_common-use-signal_pending_state.patch
>> -genirq-better-warning-on-irqchip-set_type-failure.patch
>> -proc-fix-inode-number-bogorithmetic.patch
>> -proc-switch-inode-number-allocation-to-ida.patch
>> -blackfin-rtc-driver-if-we-dont-define-irq_set_freq-the-common-rtc-dev-layer-will-give-us-the-same-behavior-of-returning-enotty.patch
>> -blackfin-rtc-driver-fix-bug-only-rtc-interrupt-can-wake-up-deeper-sleep-core.patch
>> -blackfin-rtc-driver-add-support-for-power-management-framework.patch
>> -blackfin-rtc-driver-dont-bother-passing-the-rtc-struct-down-to-bfin_rtc_int_setclear-since-it-isnt-needed-shaves-off-100bytes.patch
>> -blackfin-rtc-driver-disable-the-write-complete-irq-upon-close.patch
>> -blackfin-rtc-driver-wait-for-the-write-complete-interrupt-complete-before-sleeping.patch
>> -blackfin-rtc-driver-convert-pie-handling-to-irq_set_state-as-pointed-out-by-david-brownell.patch
>> -blackfin-rtc-driver-drop-pie-stopwatch-code-since-the-hardware-can-only-do-a-max-of-1hz-and-this-same-functionality-is-provided-by-uie.patch
>> -backlight-add-more-information-output-to-pwm_backlight.patch
>> -backlight-add-module_alias-to-pwm_backlight-driver.patch
>> -remove-the-deprecated-cli-sti-functions.patch
>> -drivers-telephony-ixjc-depends-on-pnp.patch
>> -docsrc-build-documentation-sources.patch
>> -docsrc-fix-procfs-example.patch
>> -docsrc-fix-ifenslave-type.patch
>> -docsrc-fix-crc32hash-type.patch
>> -docsrc-fix-getdelays-printk-formats.patch
>> -firmware-use-dev_printk-when-possible.patch
>> -make-ioctlh-compatible-with-userland.patch
>> -rtc-pcf8563-remove-client-validation.patch
>> -rtc-m48t59-reduce-structure-m48t59_private.patch
>> -ali-m7101-pmu-also-available-on-sun-netras-too.patch
>> -firmware-memmap-cleanup.patch
>> -applesmc-support-for-intel-imac.patch
>> -applesmc-add-support-for-macbook-v3.patch
>> -drivers-hwmon-w83791dc-fix-unused-var-warning.patch
>> -hwmon-adc124s501-generic-driver.patch
>> -hwmon-adc124s501-generic-driver-update.patch
>> -i5k_amb-provide-labels-for-temperature-sensors.patch
>> -drivers-mtd-chips-jedec_probec-fix-am29dl800bb-device-id.patch
>> -forcedeth-bug-fix-realtek-phy-8211c-errata.patch
>> -drivers-net-netxen-netxen_nic_hwc-fix-printk-warnings.patch
>> -maintainers-mention-lockd-and-sunrpc-in-nfs-entries.patch
>> -rcu-fix-synchronize_rcu-so-that-kernel-doc-works.patch
>> -ftrace-disable-function-tracing-bringing-up-new-cpu.patch
>> -ftrace-make-output-nicely-spaced-for-up-to-999-cpus.patch
>> -clocksource-fix-a-print-format-error-in-the-acpi-pm-clocksource-driver-and-check-range.patch
>> -clocksource-keep-track-of-original-clocksource-frequency.patch
>> -clocksource-introduce-clocksource_forward_now.patch
>> -clocksource-introduce-clock_monotonic_raw.patch
>> -posix-timers-fix-posix_timer_event-vs-dequeue_signal-race.patch
>> -posix-timers-do_schedule_next_timer-fix-the-setting-of-si_overrun.patch
>> -unrevert-usb-dont-explicitly-reenable-root-hub-status-interrupts.patch
>> -rtc-rtc-rs5c732-add-support-for-ricoh-r2025s-d-rtc.patch
>> -devpts-switch-to-ida.patch
>> -devpts-switch-to-ida-checkpatch-fixes.patch
>> -byteorder-add-a-new-include-linux-swabh-to-define-byteswapping-functions.patch
>> -byteorder-add-include-linux-byteorderh-to-define-endian-helpers.patch
>>
>>  Merged into mainline or a subsystem tree
>>
>> +res_counter-fix-off-by-one-bug-in-setting-limit.patch
>> +forcedeth-fix-kexec-regression.patch
>> +atmel_lcdfb-fix-oops-in-rmmod-when-framebuffer-fails-to-register.patch
>> +tracehook-comment-pasto-fixes.patch
>>
>>  2.6.27 queue
>>
>> -linux-next-git-rejects.patch
>> -linux-next-fixup.patch
>>
>>  Unneeded
>>
>> +security-selinux-include-netlabelh-fix-two-build-errors.patch
>> +mfd-ucb1400-sound-driver-uses-depends-on-ac97_bus.patch
>> +drivers-mfd-ucb1400_corec-needs-gpio.patch
>> +drivers-mfd-ucb1400_corec-further-unbork.patch
>> +kbuild-ftrace-dont-assume-that-scripts-recordmcountpl-is-executable.patch
>> +fb-metronome-printk-format-warning.patch
>>
>>  linux-next fixes
>>
>> +introduce-generic-header-file-for-the-software-io-tlb.patch
>>
>>  Early 2.6.28
>>
>> +acpi-ec-dont-degrade-to-poll-mode-at-storm-automatically.patch
>> +acpi-ec-dont-degrade-to-poll-mode-at-storm-automatically-cleanup.patch
>> +toshiba_acpi-add-support-for-bluetooth-toggling-through-rfkill-v7.patch
>> +toshiba_acpi-add-support-for-bluetooth-toggling-through-rfkill-v7-fix.patch
>> +toshiba_acpi-add-support-for-bluetooth-toggling-through-rfkill-v7-fix-fix.patch
>> +acpi-toshiba_acpic-fix-sparse-signedness-mismatch-warnings.patch
>>
>>  ACPI things
>>
>> +x86-fix-shadowed-variable-warning.patch
>> +x86-use-dev_printk-in-quirk-message.patch
>> +x86-make-poll_idle-behave-more-like-the-other-idle-methods.patch
>> +x86-make-poll_idle-behave-more-like-the-other-idle-methods-checkpatch-fixes.patch
>> +x86-init-annotations-in-early_printk-setup.patch
>> +x86-adjust-dependencies-for-config_x86_cmov.patch
>> +x86-pgd_cdtor-cleanup.patch
>> +x86-x86_physvirt_bits-field-also-for-i386.patch
>> +x86-adjust-vmalloc_sync_all-for-xen-2nd-try.patch
>> +x86-fix-ticket-spin-lock-asm-constraints.patch
>> +x86-64-reduce-boot-fixmap-space.patch
>> +x86-64-add-two-__cpuinit-annotations.patch
>> +x86-64-eliminate-dead-code.patch
>> +x86-64-slightly-streamline-32-bit-syscall-entry-code.patch
>> +x86_64-add-memory-hotremove-config-option.patch
>> +arch-x86-kernel-early_printkc-remove-unused-enable_debug_console.patch
>> +x86-use-common-header-for-software-io-tlb.patch
>>
>>  x86 things
>>
>> +drivers-rtc-rtc-bq4802c-dont-use-bin_2_bcd-and-bcd_2_bin.patch
>>
>>  ALSA fix
>>
>> +agp-follow-lspci-device-vendor-style.patch
>>
>>  AGP update
>>
>> +powerpc-convert-config_ppc_merge-to-config_ppc-for-legacy-io-checks.patch
>>
>>  powerpc tweak
>>
>> +fs-sysfs-dirc-remove-unused-__sysfs_get_dentry.patch
>> +platform-add-new-device-registration-helper.patch
>>
>>  device driver core updates
>>
>> +v4l-dvb-gspca-fix-wrong-retry-counting.patch
>>
>>  v4l
>>
>> +fs-gfs2-use-an-is_err-test-rather-than-a-null-test.patch
>>
>>  GFS fix
>>
>> +fs-dlm-configc-choose-better-identifiers.patch
>>
>>  DLM fix
>>
>> +hid-fix-gyration-build-error.patch
>>
>>  HID fix
>>
>> +hrtimer-reorder-struct-hrtimer-to-save-8-bytes-on-64-bit-builds.patch
>> +ntp-improve-adjtimex-frequency-rounding.patch
>> +posix-timers-dont-switch-to-group_leader-if-it_process-dies.patch
>> +posix-timers-always-do-get_task_structtimer-it_process.patch
>> +posix-timers-sys_timer_create-remove-the-buggy-pf_exiting-check.patch
>> +posix-timers-sys_timer_create-simplify-and-s-tasklist-rcu.patch
>> +posix-timers-move-the-initialization-of-timer-sigq-from-send-to-create-path.patch
>> +posix-timers-sys_timer_create-cleanup-the-error-handling.patch
>> +posix-timers-kill-it_sigev_signo-and-it_sigev_value.patch
>> +posix-timers-lock_timer-kill-the-bogus-it_id-check.patch
>> +posix-timers-lock_timer-make-it-readable.patch
>>
>>  Time-management things
>>
>> +ia64-uv-provide-a-led-driver-for-uv-systems.patch
>> +ia64-uv-use-led-to-indicate-cpu-is-active.patch
>> +ia64-uv-use-blinking-led-for-heartbeat-display.patch
>> +ia64-uv-use-blinking-led-for-heartbeat-display-fix.patch
>> +ia64-avoid-invoking-irq-handlers-on-offline-cpus.patch
>> +ia64-use-common-header-for-software-io-tlb.patch
>> +ia64-fix-the-difference-between-node_mem_map-and-node_start_pfn.patch
>>
>>  ia64 things
>>
>> +drivers-input-touchscreen-ucb1400_tsc-needs-gpio.patch
>> +serio_raw-add-support-for-translated-serio_i8042xl-ports.patch
>> +bcm5974-064-minor-cleanups-for-scripts-checkpatchpl.patch
>> +bcm5974-064-finger-tracking-and-counting-improved-further.patch
>> +bcm5974-063-btn_touch-event-added-for-mousedev.patch
>>
>>  input things
>>
>> +scripts-package-dont-break-if-%_smp_mflags-isnt-set.patch
>> +scripts-package-allow-custom-options-to-rpm.patch
>> +scripts-checksyscallssh-fix-for-non-gnu-sed.patch
>> +setlocalversion-dont-include-svn-change-count.patch
>> +adjust-init-section-definitions.patch
>>
>>  kbuild things
>>
>> +leds-avoid-needless-strlen-for-attributes.patch
>> +leds-wrap-use-default-on-trigger-for-power-led.patch
>> +led-driver-for-leds-on-pcengines-alix2-and-alix3-boards.patch
>>
>>  LED things
>>
>> +libata-fix-lba28-lba48-off-by-one-bug-in-atah.patch
>> +libata-blackfin-pata-driver-add-proper-pm-operation-into-atapi-driver.patch
>> +libata-blackfin-pata-driver-add-proper-pm-operation-into-atapi-driver-fix.patch
>> +libata-reorder-ata_device-to-remove-8-bytes-of-padding-on-64-bits.patch
>> +pata_sil680-convert-config_ppc_merge-to-config_ppc.patch
>>
>>  ata things
>>
>> +m32r-export-empty_zero_page.patch
>> +m32r-export-__ndelay.patch
>> +m32r-kernel-cleanups.patch
>>
>>  m32r things
>>
>> -git-ubi-git-rejects.patch
>>
>>  Unneeded
>>
>> +mmc-fix-comment-in-include-linux-mmc-hosth.patch
>>
>>  mmc fix
>>
>> +mtd-maps-make-uclinux-mapping-driver-depend-on-mtd_ram-since-it-only-probes-that.patch
>> +tmio_nand-fix-base-address-programming.patch
>>
>>  MTD things
>>
>> +net-fix-compilation-ng-when-config_module.patch
>> +netfilter-xt_time-gives-a-wrong-monthday-in-a-leap-year.patch
>> +drivers-atm-use-div_round_up.patch
>> +drivers-net-wan-use-div_round_up.patch
>> +hci_usb-replace-mb-with-smp_mb.patch
>> +irda-follow-lspci-device-vendor-style.patch
>>
>>  net things
>>
>> +drivers-isdn-capi-kcapic-adjust-error-handling-code-involving-capi_ctr_put.patch
>> +misdn-endian-annotations-for-struct-zt.patch
>> +misdn-annotate-iomem-pointer-and-add-statics.patch
>> +misdn-misc-timerdev-fixes.patch
>>
>>  ISDN things
>>
>> +skty2-adapt-to-the-reworked-pci-pm.patch
>> +e100-adapt-to-the-reworked-pci-pm.patch
>> +the-overdue-eepro100-removal.patch
>> +forcedeth-add-pci_enable_device-to-nv_resume.patch
>> +driver-net-skgec-restart-the-interface-when-its-options-or-pauseparam-is-set.patch
>> +fs-enet-remove-code-associated-with-config_ppc_merge.patch
>> +netdev-drop-config_ppc_merge-from-kconfig.patch
>> +e1000e-avoid-duplicated-output-of-device-name-in-kernel-warning.patch
>> +e1000e-avoid-duplicated-output-of-device-name-in-kernel-warning-checkpatch-fixes.patch
>> +e1000e-avoid-duplicated-output-of-device-name-in-kernel-warning-fix.patch
>> +forcdeth-increase-max_interrupt_work.patch
>> +atl1e-remove-the-unneeded-struct-atl1e_adapter.patch
>>
>>  netdev things
>>
>> +backlight-driver-for-tabletkiosk-sahara-touchit-213-tablet-pc.patch
>> +backlight-driver-for-tabletkiosk-sahara-touchit-213-tablet-pc-update-2.patch
>> +backlight-driver-for-tabletkiosk-sahara-touchit-213-tablet-pc-update-2-checkpatch-fixes.patch
>>
>>  backlight things
>>
>> +bq27x00_battery-use-unaligned-access-helper.patch
>>
>>  battery things
>>
>> +nfs-err_ptr-is-expected-on-failure-from-nfs_do_clone_mount.patch
>> +sunrpc-do-not-pin-sunrpc-module-in-the-memory.patch
>> +nfs-remove-8-bytes-of-padding-from-struct-nfs_fattr-on-64-bit-builds.patch
>>
>>  NFS things
>>
>> +parisc-lib-make-code-static.patch
>> +drivers-parisc-make-code-static.patch
>>
>>  parisc things
>>
>> +pci-tidy-pme-support-messages-checkpatch-fixes.patch
>>
>>  pci thing
>>
>> +arch-s390-kernel-ptracec-fix-build.patch
>>
>>  repair s390
>>
>> +initramfs-fix-compilation-warning.patch
>> +less-softirq-vectors.patch
>> +dyn_array-use-%pf-instead-of-print_fn_descriptor_symbol.patch
>> +dyn_array-fix-typo.patch
>> +sched-fix-init_hrtick-section-mismatch-warning.patch
>> +sched-clarify-ifdef-tangle.patch
>> +lockstat-documentation-update.patch
>> +fix-fastboot-make-the-raid-autodetect-code-wait-for-all-devices-to-init.patch
>> +rcu-spinlocks-take-an-unsigned-long-flags.patch
>> +rcu-fix-sparse-shadowed-variable-warning.patch
>> +ftrace-warn-on-failure-to-disable-mcount-callers.patch
>> +ftrace-remove-direct-reference-to-mcount-in-trace-code.patch
>>
>>  random ingo stuff
>>
>> +scsi-remove-the-unused-scsi_qlogic_fc_firmware-option.patch
>> +drivers-scsi-a2091c-make-2-functions-static.patch
>> +drivers-scsi-a3000c-make-2-functions-static.patch
>> +drivers-scsi-use-div_round_up.patch
>> +drivers-scsi-megaraid-use-div_round_up.patch
>> +drivers-scsi-device_handler-scsi_dh_emcc-suppress-warning.patch
>>
>>  More scsi things :(
>>
>> -git-block-git-rejects.patch
>>
>>  Unneeded
>>
>> +drivers-block-use-div_round_up.patch
>> +floppy-support-arbitrary-first-sector-numbers.patch
>>
>>  block things
>>
>> +drivers-rtc-kconfig-dont-build-rtc-cmoso-on-sparc32.patch
>>
>>  Repair sparc32 build
>>
>> +usb-remove-code-associated-with-config_ppc_merge.patch
>> +drivers-usb-misc-use-an-is_err-test-rather-than-a-null-test.patch
>> +drivers-usb-musb-disable-it-on-superh.patch
>>
>>  usb things
>>
>> +fs_mbcache-dont-needlessly-make-it-built-in.patch
>> +vfs-make-security_inode_setattr-calling-consistent.patch
>> +vfs-fix-vfs_rename_dir-for-fs_rename_does_d_move-filesystems.patch
>> +include-linux-fsh-put-declarations-in-__kernel__.patch
>>
>>  vfs things
>>
>> +pika-warp-appliance-watchdog-timer.patch
>>
>>  watchdog thing
>>
>> +ath9k-uses-needs-led_classdev_register.patch
>>
>>  wireless thing
>>
>> +modules-remove-stop_machine-during-module-load.patch
>> +modules-remove-stop_machine-during-module-load-checkpatch-fixes.patch
>>
>>  modules things
>>
>> +async_tx-fix-the-bug-in-async_tx_run_dependencies.patch
>> +rtc-bunch-of-drivers-fix-no-irq-case-handing.patch
>>
>>  More 2.6.27 things
>>
>> +drivers-media-video-cafe_ccicc-needs-mmh.patch
>> +jbd2-abort-instead-of-waiting-for-nonexistent-transactions.patch
>> +misdn-dsp_cmxc-fix-size-checks.patch
>> +h8300-kallsyms-exclude-local-symbols.patch
>> +leds-pca955x-add-proper-error-handling-and-fix-bogus-memory-handling.patch
>> +drivers-mmc-card-blockc-fix-refcount-leak-in-mmc_block_open.patch
>> +drivers-net-skfp-pmfc-use-offsetof-macro.patch
>> +drivers-net-atl1e-dont-take-the-mdio_lock-in-atl1e_probe.patch
>> +e1000e-prevent-corruption-of-eeprom-nvm.patch
>> +drivers-net-mlx4-allocc-needs-mmh.patch
>> +nec-fix-for-hibernate-and-rmmod-oops-fix.patch
>> +net-forcedeth-call-restore-mac-addr-in-nv_shutdown-path-v2.patch
>> +net-forcedeth-call-restore-mac-addr-in-nv_shutdown-path-v2-fix.patch
>> +nfs-bug_on-in-nfs_follow_mountpoint.patch
>> +fix-pciehp_free_irq.patch
>> +pci-hotplug-fakephp-fix-deadlock-again.patch
>> +sched_clock-fix-nohz-interaction.patch
>> +acpi_pmc-use-proper-read-function-also-in-errata-mode.patch
>> +acpi_pmc-check-for-monotonicity.patch
>> +clockevents-prevent-clockevent-event_handler-ending-up-handler_noop.patch
>> +x86-delay-early-cpu-initialization-until-cpuid-is-done.patch
>> +x86-move-mtrr-cpu-cap-setting-early-in-early_init_xxxx.patch
>> +x86-add-io-delay-quirk-for-presario-f700.patch
>> +posix-timers-use-struct-pid-instead-of-struct-task_struct.patch
>> +posix-timers-check-it_signal-instead-of-it_pid-to-validate-the-timer.patch
>> +posix-timers-simplify-de_thread-exit_itimers-path.patch
>>
>>  Things which might be needed in 2.6.27 but which go via subsystem trees.
>>
>> +memrlimit-cgroup-mm-owner-callback-changes-to-add-task-info.patch
>> +mm-owner-fix-race-between-swap-and-exit.patch
>> +mm-owner-fix-race-between-swap-and-exit-fix.patch
>> +mm-page_allocc-free_area_init_nodes-fix-inappropriate-use-of-enum.patch
>> +hugetlb-handle-updating-of-accessed-and-dirty-in-hugetlb_fault.patch
>> +show-memory-section-to-node-relationship-in-sysfs.patch
>> +mlock-mlocked-pages-are-unevictable-fix.patch
>> +doc-unevictable-lru-and-mlocked-pages-documentation-update-2.patch
>> +mmap-handle-mlocked-pages-during-map-remap-unmap-mlock-fix-__mlock_vma_pages_range-comment-block.patch
>> +mmap-handle-mlocked-pages-during-map-remap-unmap-mlock-backout-locked_vm-adjustment-during-mmap.patch
>> +mmap-handle-mlocked-pages-during-map-remap-unmap-mlock-resubmit-locked_vm-adjustment-as-separate-patch.patch
>> +mmap-handle-mlocked-pages-during-map-remap-unmap-mlock-resubmit-locked_vm-adjustment-as-separate-patch-fix.patch
>> +mmap-handle-mlocked-pages-during-map-remap-unmap-mlock-fix-return-value-for-munmap-mlock-vma-race.patch
>> +mmap-handle-mlocked-pages-during-map-remap-unmap-mlock-update-locked_vm-on-munmap-of-mlocked-region.patch
>> +mlock-revert-mainline-handling-of-mlock-error-return.patch
>> +mlock-make-mlock-error-return-posixly-correct.patch
>> +mlock-make-mlock-error-return-posixly-correct-fix.patch
>> +mm-pagecache-insertion-fewer-atomics.patch
>> +mm-unlockless-reclaim.patch
>> +mm-page-lock-use-lock-bitops.patch
>> +fs-buffer-lock-use-lock-bitops.patch
>> +mm-page-allocator-minor-speedup.patch
>> +mm-rewrite-vmap-layer.patch
>> +mm-rewrite-vmap-layer-fix.patch
>> +mm-rewrite-vmap-layer-fix-fix.patch
>> +mm-rewrite-vmap-layer-fix-fix-fix.patch
>> +mm-hugetlbc-make-functions-static-use-null-rather-than-0.patch
>>
>>  Memory management updates
>>
>> +uclinux-fix-gzip-header-parsing-in-binfmt_flatc.patch
>>
>>  nommu
>>
>> +h8300-update-timer-handler-delete-files.patch
>> +h8300-update-timer-handler-new-files.patch
>> +h8300-update-timer-handler-misc-update.patch
>> +h8300-kconfig-cleanup.patch
>> +h8300-generic_bug-support.patch
>> +h8300-generic_bug-support-checkpatch-fixes.patch
>> +asm-h8300-mdh-remove-cvs-keyword.patch
>>
>>  h8/300
>>
>> +alpha-miata-remove-dead-url.patch
>>
>>  alpha
>>
>> +pm-rework-disabling-of-user-mode-helpers-during-suspend-hibernation.patch
>> +pm-rework-disabling-of-user-mode-helpers-during-suspend-hibernation-cleanup.patch
>> +#
>> +container-freezer-add-tif_freeze-flag-to-all-architectures.patch
>> +container-freezer-add-tif_freeze-flag-to-all-architectures-fix.patch
>> +container-freezer-make-refrigerator-always-available.patch
>> +container-freezer-implement-freezer-cgroup-subsystem.patch
>> +container-freezer-implement-freezer-cgroup-subsystem-checkpatch-fixes.patch
>> +container-freezer-implement-freezer-cgroup-subsystem-fix-freezer-kconfig.patch
>> +container-freezer-implement-freezer-cgroup-subsystem-uninline-thaw_process.patch
>> +container-freezer-implement-freezer-cgroup-subsystem-uninline-thaw_process-fix.patch
>> +container-freezer-implement-freezer-cgroup-subsystem-cleanup-comment.patch
>> +container-freezer-skip-frozen-cgroups-during-power-management-resume.patch
>> +container-freezer-prevent-frozen-tasks-or-cgroups-from-changing.patch
>> +container-freezer-make-freezer-state-names-less-generic.patch
>> +container-freezer-rename-check_if_frozen.patch
>> +container-freezer-document-the-cgroup-freezer-subsystem.patch
>>
>>  Power managememt
>>
>> +maintainers-remove-hga-framebuffer-driver-entry.patch
>> +include-linux-mounth-remove-cvs-keyword.patch
>> +kernel-dmac-remove-a-cvs-keyword.patch
>> +inith-remove-long-dead-__setup_null_param-macro.patch
>> +drivers-misc-use-div_round_up.patch
>> +fs-make-linux-kernel-parsers-match_table_t-const.patch
>> +eeepc-laptop-use-standard-interfaces.patch
>> +fix-documentation-filesystems-ramfs-rootfs-initramfstxt.patch
>> +nubus-fix-mis-indented-statement.patch
>> +identify_ramdisk_image-correct-typo-about-return-value-in-comment.patch
>> +fix-random-typos.patch
>> +add-phys_addr_t-for-holding-physical-addresses.patch
>> +make-pfn_phys-explicitly-return-phys_addr_t.patch
>> +redefine-resource_size_t-as-phys_addr_t.patch
>> +separate-atomic_t-declaration-from-asm-atomich-into-asm-atomic_defh.patch
>> +separate-atomic_t-declaration-from-asm-atomich-into-asm-atomic_defh-fix.patch
>> +separate-atomic_t-declaration-from-asm-atomich-into-asm-atomic_defh-fix-fix.patch
>> +fix-a-race-condtion-of-oops_in_progress.patch
>> +fix-a-race-condtion-of-oops_in_progress-fix.patch
>> +percpu-counters-clean-up-percpu_counter_sum_and_set-interface.patch
>> +vsprintf-use-new-vsprintf-symbolic-function-pointer-format.patch
>> +vsprintf-use-new-vsprintf-symbolic-function-pointer-format-cleanup.patch
>> +wait-kill-is_sync_wait.patch
>> +kconfig-eliminate-def_bool-n-constructs.patch
>> +initramfs-add-option-to-preserve-mtime-from-initramfs-cpio-images.patch
>> +make-taint-bit-reliable-v3.patch
>> +make-taint-bit-reliable-v3-fix.patch
>>
>>  Misc
>>
>> +compat-move-cp_compat_stat-to-common-code.patch
>> +compat-generic-compat-get-settimeofday.patch
>> +compat-generic-compat-get-settimeofday-checkpatch-fixes.patch
>>
>>  compat hnadling
>>
>> +x86-rename-iommu_num_pages-function-to-iommu_nr_pages.patch
>> +sparc64-rename-iommu_num_pages-function-to-iommu_nr_pages.patch
>> +powerpc-rename-iommu_num_pages-function-to-iommu_nr_pages.patch
>> +introduce-generic-iommu_num_pages-function.patch
>> +x86-convert-gart-driver-to-generic-iommu_num_pages-function.patch
>> +x86-amd-iommu-convert-driver-to-generic-iommu_num_pages-function.patch
>> +x86-convert-calgary-iommu-driver-to-generic-iommu_num_pages-function.patch
>> +powerpc-use-iommu_num_pages-function-in-iommu-code.patch
>> +alpha-use-iommu_num_pages-function-in-iommu-code.patch
>> +sparc64-use-iommu_num_pages-function-in-iommu-code.patch
>>
>>  IOMMU
>>
>> +checkpatch-square-brackets-exemption-for-array-slices-in-braces.patch
>> +checkpatch-values-double-ampersand-may-be-unary.patch
>> +checkpatch-conditional-indent-labels-have-different-indent-rules.patch
>> +checkpatch-switch-indent-allow-plain-return.patch
>> +checkpatch-add-tests-for-the-attribute-matcher.patch
>> +checkpatch-____cacheline_aligned-et-al-are-modifiers.patch
>> +checkpatch-complex-macros-fix-up-extension-handling.patch
>> +checkpatch-fix-up-comment-checks-search-to-scan-the-entire-block.patch
>> +checkpatch-include-asm-checks-should-be-anchored.patch
>> +checkpatch-reduce-warnings-for-include-of-asm-fooh-to-check-from-arch-barc.patch
>> +checkpatch-report-any-absolute-references-to-kernel-source-files.patch
>> +checkpatch-report-the-real-first-line-of-all-suspect-indents.patch
>> +checkpatch-suspect-indent-skip-over-preprocessor-label-and-blank-lines.patch
>> +checkpatch-%lx-tests-should-hand-%%-as-a-literal.patch
>> +checkpatch-report-the-correct-lines-for-single-statement-blocks.patch
>> +checkpatch-perform-indent-checks-on-perl.patch
>> +checkpatch-version-022.patch
>> +checkpatch-case-default-checks-should-only-check-changed-lines.patch
>> +checkpatch-suppress-errors-triggered-by-short-patch.patch
>> +checkpatch-handle-comment-quote-nesting-correctly.patch
>> +checkpatch-check-line-endings-in-text-format-files.patch
>> +checkpatch-suspect-indent-count-condition-lines-correctly.patch
>> +checkpatch-ensure-we-only-apply-checks-to-the-lines-within-hunks.patch
>> +checkpatch-version-023.patch
>>
>>  checkpatch updates
>>
>> +oss-remove-references-to-dead-sound-oss-vars-aedsp16_msssbpro.patch
>>
>>  OSS drivers
>>
>> +binfmt_somc-add-module_license.patch
>>
>>  binfmt
>>
>> +make-probe_serial_gsc-static.patch
>> +serial-mpc52xx_uart-remove-code-associated-with-config_ppc_merge.patch
>>
>>  serial
>>
>> +mpc52xx_psc_spi-remove-code-associated-with-config_ppc_merge.patch
>>
>>  spi
>>
>> +i2o-fix-32-64bit-dma-locking.patch
>>
>>  i2o
>>
>> +drivers-net-xen-netfrontc-use-div_round_up.patch
>>
>>  xen
>>
>> +ecryptfs-remove-retry-loop-in-ecryptfs_readdir.patch
>>
>>  ecryptfs
>>
>> +autofs4-cleanup-autofs-mount-type-usage.patch
>> +autofs4-track-uid-and-gid-of-last-mount-requester.patch
>> +autofs4-track-uid-and-gid-of-last-mount-requester-fix.patch
>> +autofs4-devicer-node-ioctl-docoumentation.patch
>> +autofs4-add-miscellaneous-device-for-ioctls.patch
>> +autofs4-add-miscellaneous-device-for-ioctls-fix.patch
>> +autofs4-add-miscellaneous-device-for-ioctls-fix-2.patch
>> +autofs4-add-miscellaneous-device-for-ioctls-fix-fix-3.patch
>>
>>  autofs
>>
>> +rtc-pcf8563-remove-client-validation.patch
>> +rtc-ds1374-wakeup-support-update.patch
>> +rtc-add-device-driver-for-dallas-ds3234-spi-rtc-chip-fix.patch
>> +rtc-rtc-rs5c372-add-support-for-ricoh-r2025s-d-rtc.patch
>> +rtc-file-close-consistently-disables-repeating-irqs.patch
>> +rtc-cmos-strongly-avoid-hpet-emulation.patch
>> +rtc-use-config_ppc-instead-of-config_ppc_merge.patch
>> +rtc-rtc-m41t80c-add-support-for-the-st-m41t65-rtc.patch
>>
>>  rtc
>>
>> +make-gpiochip-label-const.patch
>> +gpio-max7301-fix-the-race-between-chip-addition-and-pins-reconfiguration.patch
>>
>>  gpio
>>
>> +fb-push-down-the-bkl-in-the-ioctl-handler.patch
>> +fb-push-down-the-bkl-in-the-ioctl-handler-checkpatch-fixes.patch
>> +radeonfb-revert-fix-radeon-ddc-regression.patch
>> +fb-convert-lock-unlock_kernel-into-local-fb-mutex.patch
>> +neofb-reduce-panning-function.patch
>> +viafb-viafbmodes-viafbtxt.patch
>> +viafb-viafbmodes-viafbtxt-fix.patch
>> +viafb-viafbmodes-viafbtxt-fix-fix.patch
>> +viafb-makefile-kconfig.patch
>> +viafb-accelc-accelh.patch
>> +viafb-accelc-accelh-checkpatch-fixes.patch
>> +viafb-accelc-accelh-update.patch
>> +viafb-chiph-debugh.patch
>> +viafb-dvic-dvih-globalc-and-globalh.patch
>> +viafb-dvic-dvih-globalc-and-globalh-checkpatch-fixes.patch
>> +viafb-hwc-hwh.patch
>> +viafb-hwc-hwh-checkpatch-fixes.patch
>> +viafb-ifacec-ifaceh-ioctlc-ioctlh.patch
>> +viafb-lcdc-lcdh-lcdtblh.patch
>> +viafb-makefile-shareh.patch
>> +viafb-tbl1636c-tbl1636h-tbldpasettingc-tbldpasettingh.patch
>> +viafb-viafbdevc-viafbdevh.patch
>> +viafb-viafbdevc-viafbdevh-checkpatch-fixes.patch
>> +viafb-viafbdevc-update.patch
>> +viafb-via_i2cc-via_i2ch-viamodec-viamodeh.patch
>> +viafb-via_utilityc-via_utilityh-vt1636c-vt1636h.patch
>> +viafb-maintainers-entry.patch
>> +fbdev-kconfig-update.patch
>> +fbdev-kconfig-update-fix.patch
>> +neofb-kill-some-redundant-code.patch
>> +vga16fb-remove-open_lock-mutex.patch
>> +neofb-remove-open_lock-mutex.patch
>> +tdfxfb-do-not-make-changes-to-default-tdfx_fix.patch
>> +intelfb-support-945gme-as-used-in-asus-eee-901.patch
>> +cirrusfb-remove-information-about-memory-size-during-mode-change.patch
>> +cirrusfb-simplify-clock-calculation.patch
>> +cirrusfb-remove-24-bpp-mode.patch
>> +cirrusfb-drop-device-pointers-from-cirrusfb_info.patch
>> +cirrusfb-use-modedb-and-add-mode_option-parameter-2nd-rev.patch
>> +cirrusfb-add-__devinit-attribute-to-probing-functions.patch
>> +cirrusfb-eliminate-crt-registers-from-global-structure.patch
>> +cirrusfb-drop-clock-fields-from-cirrusfb_regs-structure.patch
>> +atmel_lcdfb-disallow-setting-larger-resolution-than-the-framebuffer-memory-can-handle.patch
>> +efifb-imacfb-consolidation-hardware-support.patch
>>
>>  fbdev
>>
>> +pnp-remove-printk-with-outdated-version.patch
>> +pnp-make-the-resource-type-an-unsigned-long.patch
>> +pnp-make-the-resource-type-an-unsigned-long-fix.patch
>>
>>  pnp
>>
>> +telephony-remove-cvs-keywords.patch
>>
>>  telephony
>>
>> +ext2-fix-ext2-block-reservation-early-enospc-issue.patch
>>
>>  ext2
>>
>> +ext3-dont-try-to-resize-if-there-are-no-reserved-gdt-blocks-left.patch
>> +ext3-fix-ext3-block-reservation-early-enospc-issue.patch
>> +jbd-abort-instead-of-waiting-for-nonexistent-transactions.patch
>>
>>  ext3
>>
>> +hfsplus-quieten-down-mounting-hfsplus-journaled-fs-read-only.patch
>> +hfsplus-fix-buffer-overflow-with-a-corrupted-image.patch
>> +hfsplus-check-read_mapping_page-return-value.patch
>> +hfsplus-fix-another-bug-when-reading-a-corrupted-image.patch
>> +hfsplus-check-hfs_bnode_find-return-value.patch
>>
>>  hfsplus
>>
>> +reiserfs-procfsc-remove-cvs-keywords.patch
>> +fs-reiserfs-use-an-is_err-test-rather-than-a-null-test.patch
>>
>>  reiserfs
>>
>> +quota-remove-cvs-keywords.patch
>>
>>  quota
>>
>> +cgroups-fix-probable-race-with-put_css_set-and-find_css_set.patch
>> +cgroups-fix-probable-race-with-put_css_set-and-find_css_set-fix.patch
>>
>>  cgroups
>>
>> +devcgroup-use-kmemdup.patch
>> +devcgroup-remove-unused-variable.patch
>> +devcgroup-remove-spin_lock.patch
>>
>>  devcgroup
>>
>> -memrlimit-cgroup-mm-owner-callback-changes-to-add-task-info.patch
>> +memrlimit-setup-the-memrlimit-controller-mm_owner-fix.patch
>> +memrlimit-add-memrlimit-controller-accounting-and-control-memory-rlimit-enhance-mm_owner_changed-callback-to-deal-with-exited-owner.patch
>> +memrlimit-add-memrlimit-controller-accounting-and-control-mm_owner-fix.patch
>> +memrlimit-add-memrlimit-controller-accounting-and-control-mm_owner-fix-checkpatch-fixes.patch
>> +memrlimit-add-memrlimit-controller-accounting-and-control-memory-rlimit-fix-crash-on-fork.patch
>>
>>  memrlimit controller
>>
>> +cpuset-use-seq_cpumask-seq_nodemask.patch
>> +cpusetc-remove-extra-variable.patch
>>
>>  cpusets
>>
>> +irq-warn-about-irqf_disabledirqf_shared.patch
>>
>>  genirq
>>
>> +make-ptrace_untrace-static.patch
>>
>>  ptrace
>>
>> +kdump-update-elfcorehdr-documentation-to-reflect-supported-architectures.patch
>> +kdump-use-is_kdump_kernel-in-sba_init.patch
>> +kdump-add-is_vmcore_usable-and-vmcore_unusable.patch
>> +kdump-add-is_vmcore_usable-and-vmcore_unusable-update.patch
>> +kdump-use-is_vmcore_usable-and-vmcore_unusable-in-reserve_elfcorehdr.patch
>> +kdump-ia64-always-reserve-elfcore-header-memory-in-crash-kernel.patch
>>
>>  kdump
>>
>> +message-queues-increase-range-limits.patch
>> +message-queues-increase-range-limits-checkpatch-fixes.patch
>>
>>  IPC
>>
>> +compat_binfmt_elf-definition-tweak.patch
>>
>>  elf
>>
>> +applicomc-fix-apparently-broken-code-in-do_ac_read.patch
>> +char-moxac-sparse-annotation.patch
>>
>>  char drivers
>>
>> +firmware-use-dev_printk-when-possible.patch
>>
>>  firmware
>>
>> +fs-partitions-acornc-remove-dead-code.patch
>>
>>  partitions
>>
>> +proc-move-sysrq-trigger-out-of-fs-proc.patch
>> +proc-fix-return-value-of-proc_reg_open-in-too-late-case.patch
>> +proc-proc_sys_root-tweak.patch
>> +proc-remove-dummy-vmcore_open.patch
>> +proc-remove-unused-get_dma_list.patch
>>
>>  procfs
>>
>> +sysctl-simplify-strategy.patch
>>
>>  sysctl
>>
>> +pid_ns-de_thread-kill-the-now-unneeded-child_reaper-change.patch
>> +pid_ns-kill-the-now-unused-task_child_reaper.patch
>>
>>  pidns
>>
>> +trace-code-and-documentation-merging-documentation-tracetxt-with-documentation-filesystems-relaytxt.patch
>> +rename-lib-trace-files-to-kernel-relay_debugfs-and-enhancements.patch
>> +rename-lib-trace-files-to-kernel-relay_debugfs-and-enhancements-fix.patch
>>
>>  relayfs
>>
>> +make-i82443bxgx_edac-coexist-with-intel_agp.patch
>>
>>  edac
>>
>> +parport-remove-cvs-keywords.patch
>>
>>  parport
>>
>> +tpm-work-around-bug-in-broadcom-bcm0102-chipset.patch
>> +tpm-include-moderated-for-non-subscribers-notation-in-maintainers.patch
>> +drivers-char-tpm-tpmc-fix-error-patch-memory-leak.patch
>>
>>  tpm
>>
>> +w1-be-able-to-manually-add-and-remove-slaves-fix.patch
>>
>>  Fix w1-be-able-to-manually-add-and-remove-slaves.patch
>>
>> +gru-driver-minor-updates.patch
>> +gru-driver-minor-updates-fix.patch
>>
>>  GRU updates
>>
>> +kernel-call-constructors-fix-3.patch
>> -gcov-create-links-to-gcda-files-in-build-directory.patch
>> +gcov-architecture-specific-compile-flag-adjustments-x86_64-fix-2.patch
>>
>>  gcov
>>
>> -resource-add-new-ioresource_clk-type-v2.patch
>> -i2c-sh_mobile-ioresource_clk-support.patch
>>
>>  Dropped
>>
>> +byteorder-add-new-headers-for-make-headers-install.patch
>> +byteorder-use-generic-c-version-for-value-byteswapping.patch
>>
>>  byteorder
>>
>> +ipc-semc-make-free_un-static.patch
>> +make-fs-proc-proc_sysctlc-grab_header-static.patch
>> +make-hp_wmi_notify-static.patch
>> +make-kprobesc-kretprobe_table_lock-static.patch
>> +acpi-use-bcd2bin-bin2bcd.patch
>> +alpha-use-bcd2bin-bin2bcd.patch
>> +cris-use-bcd2bin-bin2bcd.patch
>> +drivers-rtc-use-bcd2bin-bin2bcd.patch
>> +rtc-use-bcd2bin-bin2bcd.patch
>> +mips-use-bcd2bin-bin2bcd.patch
>> +mn10300-use-bcd2bin-bin2bcd.patch
>> +i2c-use-bcd2bin-bin2bcd.patch
>> +drivers-scsi-sr_vendorc-use-bcd2bin.patch
>> +remove-the-obsolete-bcdbin-binbcd-macros.patch
>> +include-linux-bcdh-remove-comments.patch
>> +fs-kconfig-move-ext2-ext3-ext4-jbd-jbd2-out.patch
>> +fs-kconfig-move-autofs-autofs4-out.patch
>> +fs-kconfig-move-cifs-out.patch
>>
>>  cleanups
>>
>> +nilfs2-continuous-snapshotting-file-system.patch
>> +nilfs2-continuous-snapshotting-file-system-fix.patch
>> +nilfs2-continuous-snapshotting-file-system-fix-fix-2.patch
>>
>>  New log-based fs
>>
>> +reiser4-compile-warning-cleanups.patch
>> +reiser4-use-wake_up_process-instead-of-wake_up-when-possible.patch
>> +reiser4-track-upstream-changes.patch
>>
>>  reiser4 fixes
>>
>> 690 commits in 682 patch files
>>
>> All patches:
>>
>> ftp://ftp.kernel.org/pub/linux/kernel/people/akpm/patches/2.6/2.6.27-rc5/2.6.27-rc5-mm1/patch-list
>>
>> --
>> To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
>> the body of a message to majordomo@vger.kernel.org
>> More majordomo info at  http://vger.kernel.org/majordomo-info.html
>> Please read the FAQ at  http://www.tux.org/lkml/
> 
> --
> To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
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From kevink@paralogos.com Thu Sep 11 15:13:13 2008
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Date:	Thu, 11 Sep 2008 16:12:08 +0200
From:	"Kevin D. Kissell" <kevink@paralogos.com>
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To:	Linux MIPS Org <linux-mips@linux-mips.org>
Subject: Re: SMTC Patches [0 of 3] (how about 4)
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As sometimes happens, after releasing the trio of patches the other night,
further testing showed that there was still some quirky FPU-affinity 
behavior
when run on an 34Kf.  Further investigation turned up some odd little holes,
which I've fixed, but the misbehavior was mostly due to the default number
of FP emulations to be performed before declaring a process "FP intensive",
which depends on loops_per_jiffy, being so low that "make" was being
declared to be an FPU-intensive program.  This, too, has been dealt with.
I'm going to follow  this message with a "Patch 4 of 3" message containig
a patch which is meant  to be applied after the first 3 - it eliminates 
a part
of patch 1 of 3.  It's probably technically feasible to generate a patch 
that
replaces patch 1, but git and I get along poorly enough where I'd probably
just make a mess.

          Regards,

          Kevin K.

Kevin D. Kissell wrote:
> I've managed to steal enough time to rework the SMTC support
> for the MIPS 34K (and, I suppose 1004K) processors so that it
> works again near the head of the source tree.  This involved
> a complete rework of the clocking model to be compatible with
> new common timing event system, which finally enables "tickless"
> operation in SMTC, something it needed pretty badly.  I also
> solved the problem with using the "wait_irqoff" idle loop
> under SMTC.
>
> There are going to be three patches that will follow.  The
> first two are relatively localized fixes to problems with
> FPU affinity and with IPI replay that I came across in testing
> the new code.  The last is a pretty big patch, but it all
> pretty much hangs together and I couldn't see any sensible
> way to partition it.
>
>     Regards,
>
>     Kevin K.
>
>


From kevink@paralogos.com Thu Sep 11 15:15:33 2008
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From 9b7b2bb9b4beeaf2fdb7085be6d8b2892c16751e Mon Sep 17 00:00:00 2001
From: Kevin D. Kissell <kevink@paralogos.com>
Date: Thu, 11 Sep 2008 15:42:19 +0200
Subject: [PATCH] Fix some holes in the automated FPU affinity logic for SMTC and SMVP.
 Signed-off-by: Kevin D. Kissell <kevink@paralogos.com>


diff --git a/arch/mips/kernel/mips-mt-fpaff.c b/arch/mips/kernel/mips-mt-fpaff.c
index df4d3f2..dc9eb72 100644
--- a/arch/mips/kernel/mips-mt-fpaff.c
+++ b/arch/mips/kernel/mips-mt-fpaff.c
@@ -159,7 +159,7 @@ __setup("fpaff=", fpaff_thresh);
 /*
  * FPU Use Factor empirically derived from experiments on 34K
  */
-#define FPUSEFACTOR 333
+#define FPUSEFACTOR 2000
 
 static __init int mt_fp_affinity_init(void)
 {
diff --git a/arch/mips/kernel/process.c b/arch/mips/kernel/process.c
index 75277c8..8dd44ea 100644
--- a/arch/mips/kernel/process.c
+++ b/arch/mips/kernel/process.c
@@ -152,22 +152,18 @@ int copy_thread(int nr, unsigned long clone_flags, unsigned long usp,
 	 */
 	p->thread.cp0_status = read_c0_status() & ~(ST0_CU2|ST0_CU1);
 	childregs->cp0_status &= ~(ST0_CU2|ST0_CU1);
+#ifdef CONFIG_MIPS_MT_SMTC
+	/*
+	 * SMTC restores TCStatus after Status, and the CU bits
+	 * are aliased there.
+	 */
+	childregs->cp0_tcstatus &= ~(ST0_CU2|ST0_CU1);
+#endif
+
 	clear_tsk_thread_flag(p, TIF_USEDFPU);
 
 #ifdef CONFIG_MIPS_MT_FPAFF
 	clear_tsk_thread_flag(p, TIF_FPUBOUND);
-	/*
-	 * FPU affinity support requires that we be subtle.
-	 * The basic fork support code will have copied
-	 * the parent's cpus_allowed set, but what the child
-	 * needs to inherit is the "user" version, which
-	 * carries the program/user controlled CPU affinity
-	 * properties that are supposed to be inherited,
-	 * but not the transient, overlayed, hardware
-	 * affinity constraints.
-	 */
-	p->thread.user_cpus_allowed = current->thread.user_cpus_allowed;
-	p->cpus_allowed = current->thread.user_cpus_allowed;
 #endif /* CONFIG_MIPS_MT_FPAFF */
 
 	if (clone_flags & CLONE_SETTLS)
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index f9165d1..0d1329e 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -807,8 +807,10 @@ static void mt_ase_fp_affinity(void)
 		if (cpus_intersects(current->cpus_allowed, mt_fpu_cpumask)) {
 			cpumask_t tmask;
 
-			cpus_and(tmask, current->thread.user_cpus_allowed,
-			         mt_fpu_cpumask);
+			current->thread.user_cpus_allowed
+				= current->cpus_allowed;
+			cpus_and(tmask, current->cpus_allowed,
+				mt_fpu_cpumask);
 			set_cpus_allowed(current, tmask);
 			set_thread_flag(TIF_FPUBOUND);
 		}
-- 
1.5.3.3


--------------080409070604030702060502--

From kevink@paralogos.com Thu Sep 11 15:58:24 2008
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Date:	Thu, 11 Sep 2008 16:59:54 +0200
From:	"Kevin D. Kissell" <kevink@paralogos.com>
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To:	Dmitri Vorobiev <dmitri.vorobiev@movial.fi>
CC:	Andrew Morton <akpm@linux-foundation.org>,
	linux-kernel@vger.kernel.org, linux-mips@linux-mips.org
Subject: Re: 2.6.27-rc5-mm1
References: <20080904224004.d3dd3076.akpm@linux-foundation.org> <48C658F5.1040208@movial.fi> <48C8EFF0.2080805@movial.fi>
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I don't know why the default Malta platform build assumes a MIPS MT core
doing some kind of virtual SMP - otherwise CONFIG_MIPS_MT_FPAFF
wouldn't be set.  I'd have thought that one would configure for a basic 
MIPS32
or MIPS32R2 single-threaded core like 4KC or 24K.  But even assuming the
quirky default, you're right, it ought to build.

          Regards,

          Kevin K.

Dmitri Vorobiev wrote:
> Ping!
>
> It's not nice that one of the MIPS defconfigs doesn't build, is it?
>
> Dmitri
>
> Dmitri Vorobiev wrote:
>   
>> Hi,
>>
>> <<<<<<<<
>>
>> [dmitri.vorobiev@amber linux-2.6.27-rc5]$ make ARCH=mips CROSS_COMPILE=mips-unknown-linux-gnu- malta_defconfig
>> #
>> # configuration written to .config
>> #
>> [dmitri.vorobiev@amber linux-2.6.27-rc5]$ make ARCH=mips CROSS_COMPILE=mips-unknown-linux-gnu-
>> scripts/kconfig/conf -s arch/mips/Kconfig
>> #
>> # configuration written to .config
>> #
>>   CHK     include/linux/version.h
>>   CHK     include/linux/utsrelease.h
>>   CALL    scripts/checksyscalls.sh
>>   CHK     include/linux/compile.h
>>   CC      arch/mips/kernel/mips-mt-fpaff.o
>> arch/mips/kernel/mips-mt-fpaff.c: In function 'mipsmt_sys_sched_setaffinity':
>> arch/mips/kernel/mips-mt-fpaff.c:82: error: 'struct task_struct' has no member named 'euid'
>> arch/mips/kernel/mips-mt-fpaff.c:82: error: 'struct task_struct' has no member named 'uid'
>> make[1]: *** [arch/mips/kernel/mips-mt-fpaff.o] Error 1
>> make: *** [arch/mips/kernel] Error 2
>> [dmitri.vorobiev@amber linux-2.6.27-rc5]$
>>
>> <<<<<<<<
>>
>> Thanks,
>> Dmitri
>>
>> Andrew Morton wrote:
>>     
>>> ftp://ftp.kernel.org/pub/linux/kernel/people/akpm/patches/2.6/2.6.27-rc5/2.6.27-rc5-mm1/
>>>
>>> - This kernel doesn't work very well if selinux is enabled: /proc/net
>>>   breaks.
>>>
>>> - suspend-to-RAM (and probably -to-disk) has regressed on one machine.
>>>
>>> - Various other weird bumps, bangs and rattles, all of which have been
>>>   reported, not all of which have been acknowledgedacpi^W^W^W^W.
>>>
>>> - I seem to have a very large number of patches outstanding against a
>>>   very large number of subsystems.  Many of which have already been sent
>>>   to the relevant maintainer at least once.
>>>
>>>
>>> Boilerplate:
>>>
>>> - See the `hot-fixes' directory for any important updates to this patchset.
>>>
>>> - To fetch an -mm tree using git, use (for example)
>>>
>>>   git-fetch git://git.kernel.org/pub/scm/linux/kernel/git/smurf/linux-trees.git tag v2.6.16-rc2-mm1
>>>   git-checkout -b local-v2.6.16-rc2-mm1 v2.6.16-rc2-mm1
>>>
>>> - -mm kernel commit activity can be reviewed by subscribing to the
>>>   mm-commits mailing list.
>>>
>>>         echo "subscribe mm-commits" | mail majordomo@vger.kernel.org
>>>
>>> - If you hit a bug in -mm and it is not obvious which patch caused it, it is
>>>   most valuable if you can perform a bisection search to identify which patch
>>>   introduced the bug.  Instructions for this process are at
>>>
>>>         http://www.zip.com.au/~akpm/linux/patches/stuff/bisecting-mm-trees.txt
>>>
>>>   But beware that this process takes some time (around ten rebuilds and
>>>   reboots), so consider reporting the bug first and if we cannot immediately
>>>   identify the faulty patch, then perform the bisection search.
>>>
>>> - When reporting bugs, please try to Cc: the relevant maintainer and mailing
>>>   list on any email.
>>>
>>> - When reporting bugs in this kernel via email, please also rewrite the
>>>   email Subject: in some manner to reflect the nature of the bug.  Some
>>>   developers filter by Subject: when looking for messages to read.
>>>
>>> - Occasional snapshots of the -mm lineup are uploaded to
>>>   ftp://ftp.kernel.org/pub/linux/kernel/people/akpm/mm/ and are announced on
>>>   the mm-commits list.  These probably are at least compilable.
>>>
>>> - More-than-daily -mm snapshots may be found at
>>>   http://userweb.kernel.org/~akpm/mmotm/.  These are almost certainly not
>>>   compileable.
>>>
>>>
>>>
>>> Changes since 2.6.27-rc1-mm1:
>>>
>>>  origin.patch
>>>  git-jg-misc.patch
>>>  git-libata-all.patch
>>>  git-xtensa.patch
>>>
>>>  git trees
>>>
>>> -remove-newline-from-the-description-of-module-parameters.patch
>>> -pnp-fix-formatting-of-dbg_pnp_show_resources-output.patch
>>> -missing-symbol-prefix-on-vmlinuxldsh.patch
>>> -missing-symbol-prefix-on-vmlinuxldsh-checkpatch-fixes.patch
>>> -mm-hugetlb-dont-crash-when-hpage_shift-is-0.patch
>>> -seq_file-fix-bug-when-seq_read-reads-nothing.patch
>>> -pci-make-pci_register_driver-a-macro.patch
>>> -acpi-add-checking-for-null-early-param.patch
>>> -calgary-fix-a-comparison-warning-the-pci-calgary-64-driver.patch
>>> -use-warn-in-arch-x86-mm-ioremapc.patch
>>> -use-warn-in-arch-x86-mm-pageattrc.patch
>>> -use-warn-in-arch-x86-kernel.patch
>>> -arch-x86-pci-irqc-attempt-to-clean-up-code-layout.patch
>>> -i386-vmalloc-size-fix.patch
>>> -x86-calgary-replace-num_dma_pages-with-iommu_num_pages.patch
>>> -x86-export-is_uv_system.patch
>>> -x86-tracehook_signal_handler.patch
>>> -x86-tracehook-syscall.patch
>>> -x86-tracehook-asm-syscallh.patch
>>> -x86-signals-use-asm-syscallh.patch
>>> -x86-tracehook-tif_notify_resume.patch
>>> -intel_agp-official-name-for-gm45-chipset.patch
>>> -amd64-agp-run-fallback-when-no-bridges-found-not-when-driver-registration-fails.patch
>>> -agp-use-dev_printk-when-possible.patch
>>> -ppc-use-the-common-ascii-hex-helpers.patch
>>> -powerpc-replace-__function__-with-__func__.patch
>>> -drivers-base-driverc-remove-unused-to_dev-macro.patch
>>> -dev_printk-constify-the-dev-argument.patch
>>> -drm-remove-defines-for-non-linux-systems.patch
>>> -sis-drm-fix-the-memory-allocator-if-the-sis-fb-is-built-as-a-module.patch
>>> -sis-drm-fix-a-pointer-cast-warning.patch
>>> -v4l-link-tuner-before-saa7134.patch
>>> -v4l-drx397xdc-sparse-annotations.patch
>>> -v4l-drx397xdc-replace-__function__-occurrences.patch
>>> -v4l-fix-kernel-doc-warning-function-name-and-docbook-filename.patch
>>> -drivers-media-video-vinoc-needs-v4l2-ioctlh.patch
>>> -i2c-renesas-highlander-fpga-smbus-support.patch
>>> -hid-wellspring-device-quirks.patch
>>> -migrate_timers-add-comment-use-spinlock_irq.patch
>>> -drivers-input-serio-xilinx_ps2c-fix-warning.patch
>>> -wistron_btns-add-support-for-fujitsu-siemens-amilo-pro-edition-v3505.patch
>>> -maple-allow-removal-and-reinsertion-of-keyboard-driver-module.patch
>>> -input-bcm5974-055-smoother-motion-irq-simplification.patch
>>> -genksyms-parser-fix-the-__attribute__-rule.patch
>>> -genksyms-include-extern-information-in-dumps.patch
>>> -libata-scsi-dont-start-hotplug-work-queue-if-hotplug-is-disabled.patch
>>> -libata-core-make-sure-that-ata_force_tbl-is-freed-in-case-of-an-error.patch
>>> -pata_viac-add-flag-for-vx800-and-add-a-function-for-fixing-internal-bugs-for-via-chipsets.patch
>>> -cdrom-dont-check-cdc_play_audio-in-cdrom_count_tracks.patch
>>> -drivers-mtd-nand-nandsimc-needs-div64h.patch
>>> -jffs2-summary-allocation-dont-use-vmalloc.patch
>>> -mtd-diskonchipc-fix-sparse-endian-warnings.patch
>>> -mtdpart-handle-remaining-checkpatch-findings.patch
>>> -blackfin-nfc-driver-fix-bug-do-not-clobber-the-status-from-the-first-256-bytes-if-operating-on-512-pages.patch
>>> -blackfin-nfc-driver-fix-bug-hw-ecc-calc-by-making-sure-we-extract-11-bits-from-each-register-instead-of-10.patch
>>> -blackfin-nfc-driver-add-support-for-the-ecc-layout-the-blackfin-bootrom-uses.patch
>>> -blackfin-nfc-driver-add-proper-devinit-devexit-markings-to-probe-remove-functions.patch
>>> -blackfin-nfc-driver-enable-blackfin-nand-hwecc-support-by-default.patch
>>> -blackfin-nfc-driver-use-standard-dev_err-rather-than-printk.patch
>>> -blackfin-nfc-driver-cleanup-the-error-exit-path-of-bf5xx_nand_probe-function.patch
>>> -drivers-mtd-nand-nandsimc-fix-printk-warnings.patch
>>> -mtd-dataflash-otp-support.patch
>>> -random32-seeding-improvement.patch
>>> -bridge-send-correct-mtu-value-in-pmtu.patch
>>> -bridge-send-correct-mtu-value-in-pmtu-revised.patch
>>> -net-use-the-common-ascii-hex-helpers.patch
>>> -atm-fix-const-assignment-discard-warnings-in-the-atm-networking-driver.patch
>>> -atm-fix-direct-casts-of-pointers-to-u32-in-the-interphase-driver.patch
>>> -bluetooth-add-quirks-for-a-few-hci_usb-devices.patch
>>> -nsc-ircc-default-to-dongle-type-9-on-ibm-hardware.patch
>>> -irda-replace-__function__-with-__func__.patch
>>> -hysdn-remove-the-packed-attribute-from-poftimstamp_tag.patch
>>> -isdn-use-the-common-ascii-hex-helpers.patch
>>> -via-velocity-give-a-structure-to-the-rx-tx-fields.patch
>>> -via-velocity-fix-sleep-with-spinlock-bug-during-mtu-change.patch
>>> -hamradio-add-missing-sanity-check-to-tty-operation.patch
>>> -pegasus-add-blacklist-support-to-fix-belkin-bluetooth-dongle.patch
>>> -drivers-net-ehea-ehea_mainc-release-mutex-in-error-handling-code.patch
>>> -tg3-adapt-tg3-to-use-reworked-pci-pm-code.patch
>>> -sky2-adapt-to-use-reworked-pci-pm-code.patch
>>> -configure-out-file-locking-features.patch
>>> -use-warn-in-kernel-lockdepc.patch
>>> -sched-do_wait_for_common-use-signal_pending_state.patch
>>> -wait_task_inactive-dont-consider-task-nivcsw.patch
>>> -sched-type-fix.patch
>>> -netfilter-conntrack_helper-needs-to-include-rculisth.patch
>>> -drivers-usb-class-cdc-acmc-use-correct-type-for-cpu-flags.patch
>>> -drivers-usb-class-cdc-wdmc-fix-build-with-config_pm=n.patch
>>> -cxacru-fix-printk-format-flag-in-error-message.patch
>>> -cdc-acm-dont-unlock-acm-mutex-on-error-path.patch
>>> -usb-move-usb-mon-up-to-misc-options-in-kconfig.patch
>>> -pl2023-remove-usb-id-4348-5523-handled-by-ch341.patch
>>> -usb-storage-unusual_devs-entries-for-iriver-t10-and-datafab-cfsm-reader.patch
>>> -usb-core-driver-fix-warning.patch
>>> -usb-hubc-fix-build-with-config_pm=n.patch
>>> -ath5k-mask-out-unneeded-interrupts.patch
>>> -ath5k-unify-resets.patch
>>> -net-ieee80211-adjust-error-handling.patch
>>> -wireless-replace-__function__-with-__func__.patch
>>> -xfs-use-get_unaligned_-helpers.patch
>>> -xfs-clean-up-stale-references-to-semaphores.patch
>>> -xfs-replace-the-xfs-buf-iodone-semaphore-with-a-completion.patch
>>> -xfs-extend-completions-to-provide-xfs-object-flush-requirements.patch
>>> -xfs-replace-inode-flush-semaphore-with-a-completion.patch
>>> -xfs-replace-dquot-flush-semaphore-with-a-completion.patch
>>> -xfs-remove-the-sema_t-from-xfs.patch
>>> -xtensa-warn-about-including-asm-rwsemh-directly.patch
>>> -xtensa-replace-remaining-__function__-occurences.patch
>>> -xtensa-use-newer-__spin_lock_unlocked-macro.patch
>>> -modules-extend-initcall_debug-functionality-to-the-module-loader.patch
>>> -powerpc-86xx-mpc8610_hpcd-add-watchdog-node.patch
>>> -kdump-report-actual-value-of-vmcoreinfo_osrelease-in-vmcoreinfo.patch
>>> -vt8623fb-fix-kernel-oops.patch
>>> -block-ccissc-remove-pointless-curr_queue-calculation.patch
>>> -spi-new-orion_spi-driver.patch
>>> -spi-new-orion_spi-driver-fixes.patch
>>> -relay-fix-4-off-by-one-errors-occuring-when-writing-to-a-cpu-buffer.patch
>>> -semaphore-__down_common-use-signal_pending_state.patch
>>> -genirq-better-warning-on-irqchip-set_type-failure.patch
>>> -proc-fix-inode-number-bogorithmetic.patch
>>> -proc-switch-inode-number-allocation-to-ida.patch
>>> -blackfin-rtc-driver-if-we-dont-define-irq_set_freq-the-common-rtc-dev-layer-will-give-us-the-same-behavior-of-returning-enotty.patch
>>> -blackfin-rtc-driver-fix-bug-only-rtc-interrupt-can-wake-up-deeper-sleep-core.patch
>>> -blackfin-rtc-driver-add-support-for-power-management-framework.patch
>>> -blackfin-rtc-driver-dont-bother-passing-the-rtc-struct-down-to-bfin_rtc_int_setclear-since-it-isnt-needed-shaves-off-100bytes.patch
>>> -blackfin-rtc-driver-disable-the-write-complete-irq-upon-close.patch
>>> -blackfin-rtc-driver-wait-for-the-write-complete-interrupt-complete-before-sleeping.patch
>>> -blackfin-rtc-driver-convert-pie-handling-to-irq_set_state-as-pointed-out-by-david-brownell.patch
>>> -blackfin-rtc-driver-drop-pie-stopwatch-code-since-the-hardware-can-only-do-a-max-of-1hz-and-this-same-functionality-is-provided-by-uie.patch
>>> -backlight-add-more-information-output-to-pwm_backlight.patch
>>> -backlight-add-module_alias-to-pwm_backlight-driver.patch
>>> -remove-the-deprecated-cli-sti-functions.patch
>>> -drivers-telephony-ixjc-depends-on-pnp.patch
>>> -docsrc-build-documentation-sources.patch
>>> -docsrc-fix-procfs-example.patch
>>> -docsrc-fix-ifenslave-type.patch
>>> -docsrc-fix-crc32hash-type.patch
>>> -docsrc-fix-getdelays-printk-formats.patch
>>> -firmware-use-dev_printk-when-possible.patch
>>> -make-ioctlh-compatible-with-userland.patch
>>> -rtc-pcf8563-remove-client-validation.patch
>>> -rtc-m48t59-reduce-structure-m48t59_private.patch
>>> -ali-m7101-pmu-also-available-on-sun-netras-too.patch
>>> -firmware-memmap-cleanup.patch
>>> -applesmc-support-for-intel-imac.patch
>>> -applesmc-add-support-for-macbook-v3.patch
>>> -drivers-hwmon-w83791dc-fix-unused-var-warning.patch
>>> -hwmon-adc124s501-generic-driver.patch
>>> -hwmon-adc124s501-generic-driver-update.patch
>>> -i5k_amb-provide-labels-for-temperature-sensors.patch
>>> -drivers-mtd-chips-jedec_probec-fix-am29dl800bb-device-id.patch
>>> -forcedeth-bug-fix-realtek-phy-8211c-errata.patch
>>> -drivers-net-netxen-netxen_nic_hwc-fix-printk-warnings.patch
>>> -maintainers-mention-lockd-and-sunrpc-in-nfs-entries.patch
>>> -rcu-fix-synchronize_rcu-so-that-kernel-doc-works.patch
>>> -ftrace-disable-function-tracing-bringing-up-new-cpu.patch
>>> -ftrace-make-output-nicely-spaced-for-up-to-999-cpus.patch
>>> -clocksource-fix-a-print-format-error-in-the-acpi-pm-clocksource-driver-and-check-range.patch
>>> -clocksource-keep-track-of-original-clocksource-frequency.patch
>>> -clocksource-introduce-clocksource_forward_now.patch
>>> -clocksource-introduce-clock_monotonic_raw.patch
>>> -posix-timers-fix-posix_timer_event-vs-dequeue_signal-race.patch
>>> -posix-timers-do_schedule_next_timer-fix-the-setting-of-si_overrun.patch
>>> -unrevert-usb-dont-explicitly-reenable-root-hub-status-interrupts.patch
>>> -rtc-rtc-rs5c732-add-support-for-ricoh-r2025s-d-rtc.patch
>>> -devpts-switch-to-ida.patch
>>> -devpts-switch-to-ida-checkpatch-fixes.patch
>>> -byteorder-add-a-new-include-linux-swabh-to-define-byteswapping-functions.patch
>>> -byteorder-add-include-linux-byteorderh-to-define-endian-helpers.patch
>>>
>>>  Merged into mainline or a subsystem tree
>>>
>>> +res_counter-fix-off-by-one-bug-in-setting-limit.patch
>>> +forcedeth-fix-kexec-regression.patch
>>> +atmel_lcdfb-fix-oops-in-rmmod-when-framebuffer-fails-to-register.patch
>>> +tracehook-comment-pasto-fixes.patch
>>>
>>>  2.6.27 queue
>>>
>>> -linux-next-git-rejects.patch
>>> -linux-next-fixup.patch
>>>
>>>  Unneeded
>>>
>>> +security-selinux-include-netlabelh-fix-two-build-errors.patch
>>> +mfd-ucb1400-sound-driver-uses-depends-on-ac97_bus.patch
>>> +drivers-mfd-ucb1400_corec-needs-gpio.patch
>>> +drivers-mfd-ucb1400_corec-further-unbork.patch
>>> +kbuild-ftrace-dont-assume-that-scripts-recordmcountpl-is-executable.patch
>>> +fb-metronome-printk-format-warning.patch
>>>
>>>  linux-next fixes
>>>
>>> +introduce-generic-header-file-for-the-software-io-tlb.patch
>>>
>>>  Early 2.6.28
>>>
>>> +acpi-ec-dont-degrade-to-poll-mode-at-storm-automatically.patch
>>> +acpi-ec-dont-degrade-to-poll-mode-at-storm-automatically-cleanup.patch
>>> +toshiba_acpi-add-support-for-bluetooth-toggling-through-rfkill-v7.patch
>>> +toshiba_acpi-add-support-for-bluetooth-toggling-through-rfkill-v7-fix.patch
>>> +toshiba_acpi-add-support-for-bluetooth-toggling-through-rfkill-v7-fix-fix.patch
>>> +acpi-toshiba_acpic-fix-sparse-signedness-mismatch-warnings.patch
>>>
>>>  ACPI things
>>>
>>> +x86-fix-shadowed-variable-warning.patch
>>> +x86-use-dev_printk-in-quirk-message.patch
>>> +x86-make-poll_idle-behave-more-like-the-other-idle-methods.patch
>>> +x86-make-poll_idle-behave-more-like-the-other-idle-methods-checkpatch-fixes.patch
>>> +x86-init-annotations-in-early_printk-setup.patch
>>> +x86-adjust-dependencies-for-config_x86_cmov.patch
>>> +x86-pgd_cdtor-cleanup.patch
>>> +x86-x86_physvirt_bits-field-also-for-i386.patch
>>> +x86-adjust-vmalloc_sync_all-for-xen-2nd-try.patch
>>> +x86-fix-ticket-spin-lock-asm-constraints.patch
>>> +x86-64-reduce-boot-fixmap-space.patch
>>> +x86-64-add-two-__cpuinit-annotations.patch
>>> +x86-64-eliminate-dead-code.patch
>>> +x86-64-slightly-streamline-32-bit-syscall-entry-code.patch
>>> +x86_64-add-memory-hotremove-config-option.patch
>>> +arch-x86-kernel-early_printkc-remove-unused-enable_debug_console.patch
>>> +x86-use-common-header-for-software-io-tlb.patch
>>>
>>>  x86 things
>>>
>>> +drivers-rtc-rtc-bq4802c-dont-use-bin_2_bcd-and-bcd_2_bin.patch
>>>
>>>  ALSA fix
>>>
>>> +agp-follow-lspci-device-vendor-style.patch
>>>
>>>  AGP update
>>>
>>> +powerpc-convert-config_ppc_merge-to-config_ppc-for-legacy-io-checks.patch
>>>
>>>  powerpc tweak
>>>
>>> +fs-sysfs-dirc-remove-unused-__sysfs_get_dentry.patch
>>> +platform-add-new-device-registration-helper.patch
>>>
>>>  device driver core updates
>>>
>>> +v4l-dvb-gspca-fix-wrong-retry-counting.patch
>>>
>>>  v4l
>>>
>>> +fs-gfs2-use-an-is_err-test-rather-than-a-null-test.patch
>>>
>>>  GFS fix
>>>
>>> +fs-dlm-configc-choose-better-identifiers.patch
>>>
>>>  DLM fix
>>>
>>> +hid-fix-gyration-build-error.patch
>>>
>>>  HID fix
>>>
>>> +hrtimer-reorder-struct-hrtimer-to-save-8-bytes-on-64-bit-builds.patch
>>> +ntp-improve-adjtimex-frequency-rounding.patch
>>> +posix-timers-dont-switch-to-group_leader-if-it_process-dies.patch
>>> +posix-timers-always-do-get_task_structtimer-it_process.patch
>>> +posix-timers-sys_timer_create-remove-the-buggy-pf_exiting-check.patch
>>> +posix-timers-sys_timer_create-simplify-and-s-tasklist-rcu.patch
>>> +posix-timers-move-the-initialization-of-timer-sigq-from-send-to-create-path.patch
>>> +posix-timers-sys_timer_create-cleanup-the-error-handling.patch
>>> +posix-timers-kill-it_sigev_signo-and-it_sigev_value.patch
>>> +posix-timers-lock_timer-kill-the-bogus-it_id-check.patch
>>> +posix-timers-lock_timer-make-it-readable.patch
>>>
>>>  Time-management things
>>>
>>> +ia64-uv-provide-a-led-driver-for-uv-systems.patch
>>> +ia64-uv-use-led-to-indicate-cpu-is-active.patch
>>> +ia64-uv-use-blinking-led-for-heartbeat-display.patch
>>> +ia64-uv-use-blinking-led-for-heartbeat-display-fix.patch
>>> +ia64-avoid-invoking-irq-handlers-on-offline-cpus.patch
>>> +ia64-use-common-header-for-software-io-tlb.patch
>>> +ia64-fix-the-difference-between-node_mem_map-and-node_start_pfn.patch
>>>
>>>  ia64 things
>>>
>>> +drivers-input-touchscreen-ucb1400_tsc-needs-gpio.patch
>>> +serio_raw-add-support-for-translated-serio_i8042xl-ports.patch
>>> +bcm5974-064-minor-cleanups-for-scripts-checkpatchpl.patch
>>> +bcm5974-064-finger-tracking-and-counting-improved-further.patch
>>> +bcm5974-063-btn_touch-event-added-for-mousedev.patch
>>>
>>>  input things
>>>
>>> +scripts-package-dont-break-if-%_smp_mflags-isnt-set.patch
>>> +scripts-package-allow-custom-options-to-rpm.patch
>>> +scripts-checksyscallssh-fix-for-non-gnu-sed.patch
>>> +setlocalversion-dont-include-svn-change-count.patch
>>> +adjust-init-section-definitions.patch
>>>
>>>  kbuild things
>>>
>>> +leds-avoid-needless-strlen-for-attributes.patch
>>> +leds-wrap-use-default-on-trigger-for-power-led.patch
>>> +led-driver-for-leds-on-pcengines-alix2-and-alix3-boards.patch
>>>
>>>  LED things
>>>
>>> +libata-fix-lba28-lba48-off-by-one-bug-in-atah.patch
>>> +libata-blackfin-pata-driver-add-proper-pm-operation-into-atapi-driver.patch
>>> +libata-blackfin-pata-driver-add-proper-pm-operation-into-atapi-driver-fix.patch
>>> +libata-reorder-ata_device-to-remove-8-bytes-of-padding-on-64-bits.patch
>>> +pata_sil680-convert-config_ppc_merge-to-config_ppc.patch
>>>
>>>  ata things
>>>
>>> +m32r-export-empty_zero_page.patch
>>> +m32r-export-__ndelay.patch
>>> +m32r-kernel-cleanups.patch
>>>
>>>  m32r things
>>>
>>> -git-ubi-git-rejects.patch
>>>
>>>  Unneeded
>>>
>>> +mmc-fix-comment-in-include-linux-mmc-hosth.patch
>>>
>>>  mmc fix
>>>
>>> +mtd-maps-make-uclinux-mapping-driver-depend-on-mtd_ram-since-it-only-probes-that.patch
>>> +tmio_nand-fix-base-address-programming.patch
>>>
>>>  MTD things
>>>
>>> +net-fix-compilation-ng-when-config_module.patch
>>> +netfilter-xt_time-gives-a-wrong-monthday-in-a-leap-year.patch
>>> +drivers-atm-use-div_round_up.patch
>>> +drivers-net-wan-use-div_round_up.patch
>>> +hci_usb-replace-mb-with-smp_mb.patch
>>> +irda-follow-lspci-device-vendor-style.patch
>>>
>>>  net things
>>>
>>> +drivers-isdn-capi-kcapic-adjust-error-handling-code-involving-capi_ctr_put.patch
>>> +misdn-endian-annotations-for-struct-zt.patch
>>> +misdn-annotate-iomem-pointer-and-add-statics.patch
>>> +misdn-misc-timerdev-fixes.patch
>>>
>>>  ISDN things
>>>
>>> +skty2-adapt-to-the-reworked-pci-pm.patch
>>> +e100-adapt-to-the-reworked-pci-pm.patch
>>> +the-overdue-eepro100-removal.patch
>>> +forcedeth-add-pci_enable_device-to-nv_resume.patch
>>> +driver-net-skgec-restart-the-interface-when-its-options-or-pauseparam-is-set.patch
>>> +fs-enet-remove-code-associated-with-config_ppc_merge.patch
>>> +netdev-drop-config_ppc_merge-from-kconfig.patch
>>> +e1000e-avoid-duplicated-output-of-device-name-in-kernel-warning.patch
>>> +e1000e-avoid-duplicated-output-of-device-name-in-kernel-warning-checkpatch-fixes.patch
>>> +e1000e-avoid-duplicated-output-of-device-name-in-kernel-warning-fix.patch
>>> +forcdeth-increase-max_interrupt_work.patch
>>> +atl1e-remove-the-unneeded-struct-atl1e_adapter.patch
>>>
>>>  netdev things
>>>
>>> +backlight-driver-for-tabletkiosk-sahara-touchit-213-tablet-pc.patch
>>> +backlight-driver-for-tabletkiosk-sahara-touchit-213-tablet-pc-update-2.patch
>>> +backlight-driver-for-tabletkiosk-sahara-touchit-213-tablet-pc-update-2-checkpatch-fixes.patch
>>>
>>>  backlight things
>>>
>>> +bq27x00_battery-use-unaligned-access-helper.patch
>>>
>>>  battery things
>>>
>>> +nfs-err_ptr-is-expected-on-failure-from-nfs_do_clone_mount.patch
>>> +sunrpc-do-not-pin-sunrpc-module-in-the-memory.patch
>>> +nfs-remove-8-bytes-of-padding-from-struct-nfs_fattr-on-64-bit-builds.patch
>>>
>>>  NFS things
>>>
>>> +parisc-lib-make-code-static.patch
>>> +drivers-parisc-make-code-static.patch
>>>
>>>  parisc things
>>>
>>> +pci-tidy-pme-support-messages-checkpatch-fixes.patch
>>>
>>>  pci thing
>>>
>>> +arch-s390-kernel-ptracec-fix-build.patch
>>>
>>>  repair s390
>>>
>>> +initramfs-fix-compilation-warning.patch
>>> +less-softirq-vectors.patch
>>> +dyn_array-use-%pf-instead-of-print_fn_descriptor_symbol.patch
>>> +dyn_array-fix-typo.patch
>>> +sched-fix-init_hrtick-section-mismatch-warning.patch
>>> +sched-clarify-ifdef-tangle.patch
>>> +lockstat-documentation-update.patch
>>> +fix-fastboot-make-the-raid-autodetect-code-wait-for-all-devices-to-init.patch
>>> +rcu-spinlocks-take-an-unsigned-long-flags.patch
>>> +rcu-fix-sparse-shadowed-variable-warning.patch
>>> +ftrace-warn-on-failure-to-disable-mcount-callers.patch
>>> +ftrace-remove-direct-reference-to-mcount-in-trace-code.patch
>>>
>>>  random ingo stuff
>>>
>>> +scsi-remove-the-unused-scsi_qlogic_fc_firmware-option.patch
>>> +drivers-scsi-a2091c-make-2-functions-static.patch
>>> +drivers-scsi-a3000c-make-2-functions-static.patch
>>> +drivers-scsi-use-div_round_up.patch
>>> +drivers-scsi-megaraid-use-div_round_up.patch
>>> +drivers-scsi-device_handler-scsi_dh_emcc-suppress-warning.patch
>>>
>>>  More scsi things :(
>>>
>>> -git-block-git-rejects.patch
>>>
>>>  Unneeded
>>>
>>> +drivers-block-use-div_round_up.patch
>>> +floppy-support-arbitrary-first-sector-numbers.patch
>>>
>>>  block things
>>>
>>> +drivers-rtc-kconfig-dont-build-rtc-cmoso-on-sparc32.patch
>>>
>>>  Repair sparc32 build
>>>
>>> +usb-remove-code-associated-with-config_ppc_merge.patch
>>> +drivers-usb-misc-use-an-is_err-test-rather-than-a-null-test.patch
>>> +drivers-usb-musb-disable-it-on-superh.patch
>>>
>>>  usb things
>>>
>>> +fs_mbcache-dont-needlessly-make-it-built-in.patch
>>> +vfs-make-security_inode_setattr-calling-consistent.patch
>>> +vfs-fix-vfs_rename_dir-for-fs_rename_does_d_move-filesystems.patch
>>> +include-linux-fsh-put-declarations-in-__kernel__.patch
>>>
>>>  vfs things
>>>
>>> +pika-warp-appliance-watchdog-timer.patch
>>>
>>>  watchdog thing
>>>
>>> +ath9k-uses-needs-led_classdev_register.patch
>>>
>>>  wireless thing
>>>
>>> +modules-remove-stop_machine-during-module-load.patch
>>> +modules-remove-stop_machine-during-module-load-checkpatch-fixes.patch
>>>
>>>  modules things
>>>
>>> +async_tx-fix-the-bug-in-async_tx_run_dependencies.patch
>>> +rtc-bunch-of-drivers-fix-no-irq-case-handing.patch
>>>
>>>  More 2.6.27 things
>>>
>>> +drivers-media-video-cafe_ccicc-needs-mmh.patch
>>> +jbd2-abort-instead-of-waiting-for-nonexistent-transactions.patch
>>> +misdn-dsp_cmxc-fix-size-checks.patch
>>> +h8300-kallsyms-exclude-local-symbols.patch
>>> +leds-pca955x-add-proper-error-handling-and-fix-bogus-memory-handling.patch
>>> +drivers-mmc-card-blockc-fix-refcount-leak-in-mmc_block_open.patch
>>> +drivers-net-skfp-pmfc-use-offsetof-macro.patch
>>> +drivers-net-atl1e-dont-take-the-mdio_lock-in-atl1e_probe.patch
>>> +e1000e-prevent-corruption-of-eeprom-nvm.patch
>>> +drivers-net-mlx4-allocc-needs-mmh.patch
>>> +nec-fix-for-hibernate-and-rmmod-oops-fix.patch
>>> +net-forcedeth-call-restore-mac-addr-in-nv_shutdown-path-v2.patch
>>> +net-forcedeth-call-restore-mac-addr-in-nv_shutdown-path-v2-fix.patch
>>> +nfs-bug_on-in-nfs_follow_mountpoint.patch
>>> +fix-pciehp_free_irq.patch
>>> +pci-hotplug-fakephp-fix-deadlock-again.patch
>>> +sched_clock-fix-nohz-interaction.patch
>>> +acpi_pmc-use-proper-read-function-also-in-errata-mode.patch
>>> +acpi_pmc-check-for-monotonicity.patch
>>> +clockevents-prevent-clockevent-event_handler-ending-up-handler_noop.patch
>>> +x86-delay-early-cpu-initialization-until-cpuid-is-done.patch
>>> +x86-move-mtrr-cpu-cap-setting-early-in-early_init_xxxx.patch
>>> +x86-add-io-delay-quirk-for-presario-f700.patch
>>> +posix-timers-use-struct-pid-instead-of-struct-task_struct.patch
>>> +posix-timers-check-it_signal-instead-of-it_pid-to-validate-the-timer.patch
>>> +posix-timers-simplify-de_thread-exit_itimers-path.patch
>>>
>>>  Things which might be needed in 2.6.27 but which go via subsystem trees.
>>>
>>> +memrlimit-cgroup-mm-owner-callback-changes-to-add-task-info.patch
>>> +mm-owner-fix-race-between-swap-and-exit.patch
>>> +mm-owner-fix-race-between-swap-and-exit-fix.patch
>>> +mm-page_allocc-free_area_init_nodes-fix-inappropriate-use-of-enum.patch
>>> +hugetlb-handle-updating-of-accessed-and-dirty-in-hugetlb_fault.patch
>>> +show-memory-section-to-node-relationship-in-sysfs.patch
>>> +mlock-mlocked-pages-are-unevictable-fix.patch
>>> +doc-unevictable-lru-and-mlocked-pages-documentation-update-2.patch
>>> +mmap-handle-mlocked-pages-during-map-remap-unmap-mlock-fix-__mlock_vma_pages_range-comment-block.patch
>>> +mmap-handle-mlocked-pages-during-map-remap-unmap-mlock-backout-locked_vm-adjustment-during-mmap.patch
>>> +mmap-handle-mlocked-pages-during-map-remap-unmap-mlock-resubmit-locked_vm-adjustment-as-separate-patch.patch
>>> +mmap-handle-mlocked-pages-during-map-remap-unmap-mlock-resubmit-locked_vm-adjustment-as-separate-patch-fix.patch
>>> +mmap-handle-mlocked-pages-during-map-remap-unmap-mlock-fix-return-value-for-munmap-mlock-vma-race.patch
>>> +mmap-handle-mlocked-pages-during-map-remap-unmap-mlock-update-locked_vm-on-munmap-of-mlocked-region.patch
>>> +mlock-revert-mainline-handling-of-mlock-error-return.patch
>>> +mlock-make-mlock-error-return-posixly-correct.patch
>>> +mlock-make-mlock-error-return-posixly-correct-fix.patch
>>> +mm-pagecache-insertion-fewer-atomics.patch
>>> +mm-unlockless-reclaim.patch
>>> +mm-page-lock-use-lock-bitops.patch
>>> +fs-buffer-lock-use-lock-bitops.patch
>>> +mm-page-allocator-minor-speedup.patch
>>> +mm-rewrite-vmap-layer.patch
>>> +mm-rewrite-vmap-layer-fix.patch
>>> +mm-rewrite-vmap-layer-fix-fix.patch
>>> +mm-rewrite-vmap-layer-fix-fix-fix.patch
>>> +mm-hugetlbc-make-functions-static-use-null-rather-than-0.patch
>>>
>>>  Memory management updates
>>>
>>> +uclinux-fix-gzip-header-parsing-in-binfmt_flatc.patch
>>>
>>>  nommu
>>>
>>> +h8300-update-timer-handler-delete-files.patch
>>> +h8300-update-timer-handler-new-files.patch
>>> +h8300-update-timer-handler-misc-update.patch
>>> +h8300-kconfig-cleanup.patch
>>> +h8300-generic_bug-support.patch
>>> +h8300-generic_bug-support-checkpatch-fixes.patch
>>> +asm-h8300-mdh-remove-cvs-keyword.patch
>>>
>>>  h8/300
>>>
>>> +alpha-miata-remove-dead-url.patch
>>>
>>>  alpha
>>>
>>> +pm-rework-disabling-of-user-mode-helpers-during-suspend-hibernation.patch
>>> +pm-rework-disabling-of-user-mode-helpers-during-suspend-hibernation-cleanup.patch
>>> +#
>>> +container-freezer-add-tif_freeze-flag-to-all-architectures.patch
>>> +container-freezer-add-tif_freeze-flag-to-all-architectures-fix.patch
>>> +container-freezer-make-refrigerator-always-available.patch
>>> +container-freezer-implement-freezer-cgroup-subsystem.patch
>>> +container-freezer-implement-freezer-cgroup-subsystem-checkpatch-fixes.patch
>>> +container-freezer-implement-freezer-cgroup-subsystem-fix-freezer-kconfig.patch
>>> +container-freezer-implement-freezer-cgroup-subsystem-uninline-thaw_process.patch
>>> +container-freezer-implement-freezer-cgroup-subsystem-uninline-thaw_process-fix.patch
>>> +container-freezer-implement-freezer-cgroup-subsystem-cleanup-comment.patch
>>> +container-freezer-skip-frozen-cgroups-during-power-management-resume.patch
>>> +container-freezer-prevent-frozen-tasks-or-cgroups-from-changing.patch
>>> +container-freezer-make-freezer-state-names-less-generic.patch
>>> +container-freezer-rename-check_if_frozen.patch
>>> +container-freezer-document-the-cgroup-freezer-subsystem.patch
>>>
>>>  Power managememt
>>>
>>> +maintainers-remove-hga-framebuffer-driver-entry.patch
>>> +include-linux-mounth-remove-cvs-keyword.patch
>>> +kernel-dmac-remove-a-cvs-keyword.patch
>>> +inith-remove-long-dead-__setup_null_param-macro.patch
>>> +drivers-misc-use-div_round_up.patch
>>> +fs-make-linux-kernel-parsers-match_table_t-const.patch
>>> +eeepc-laptop-use-standard-interfaces.patch
>>> +fix-documentation-filesystems-ramfs-rootfs-initramfstxt.patch
>>> +nubus-fix-mis-indented-statement.patch
>>> +identify_ramdisk_image-correct-typo-about-return-value-in-comment.patch
>>> +fix-random-typos.patch
>>> +add-phys_addr_t-for-holding-physical-addresses.patch
>>> +make-pfn_phys-explicitly-return-phys_addr_t.patch
>>> +redefine-resource_size_t-as-phys_addr_t.patch
>>> +separate-atomic_t-declaration-from-asm-atomich-into-asm-atomic_defh.patch
>>> +separate-atomic_t-declaration-from-asm-atomich-into-asm-atomic_defh-fix.patch
>>> +separate-atomic_t-declaration-from-asm-atomich-into-asm-atomic_defh-fix-fix.patch
>>> +fix-a-race-condtion-of-oops_in_progress.patch
>>> +fix-a-race-condtion-of-oops_in_progress-fix.patch
>>> +percpu-counters-clean-up-percpu_counter_sum_and_set-interface.patch
>>> +vsprintf-use-new-vsprintf-symbolic-function-pointer-format.patch
>>> +vsprintf-use-new-vsprintf-symbolic-function-pointer-format-cleanup.patch
>>> +wait-kill-is_sync_wait.patch
>>> +kconfig-eliminate-def_bool-n-constructs.patch
>>> +initramfs-add-option-to-preserve-mtime-from-initramfs-cpio-images.patch
>>> +make-taint-bit-reliable-v3.patch
>>> +make-taint-bit-reliable-v3-fix.patch
>>>
>>>  Misc
>>>
>>> +compat-move-cp_compat_stat-to-common-code.patch
>>> +compat-generic-compat-get-settimeofday.patch
>>> +compat-generic-compat-get-settimeofday-checkpatch-fixes.patch
>>>
>>>  compat hnadling
>>>
>>> +x86-rename-iommu_num_pages-function-to-iommu_nr_pages.patch
>>> +sparc64-rename-iommu_num_pages-function-to-iommu_nr_pages.patch
>>> +powerpc-rename-iommu_num_pages-function-to-iommu_nr_pages.patch
>>> +introduce-generic-iommu_num_pages-function.patch
>>> +x86-convert-gart-driver-to-generic-iommu_num_pages-function.patch
>>> +x86-amd-iommu-convert-driver-to-generic-iommu_num_pages-function.patch
>>> +x86-convert-calgary-iommu-driver-to-generic-iommu_num_pages-function.patch
>>> +powerpc-use-iommu_num_pages-function-in-iommu-code.patch
>>> +alpha-use-iommu_num_pages-function-in-iommu-code.patch
>>> +sparc64-use-iommu_num_pages-function-in-iommu-code.patch
>>>
>>>  IOMMU
>>>
>>> +checkpatch-square-brackets-exemption-for-array-slices-in-braces.patch
>>> +checkpatch-values-double-ampersand-may-be-unary.patch
>>> +checkpatch-conditional-indent-labels-have-different-indent-rules.patch
>>> +checkpatch-switch-indent-allow-plain-return.patch
>>> +checkpatch-add-tests-for-the-attribute-matcher.patch
>>> +checkpatch-____cacheline_aligned-et-al-are-modifiers.patch
>>> +checkpatch-complex-macros-fix-up-extension-handling.patch
>>> +checkpatch-fix-up-comment-checks-search-to-scan-the-entire-block.patch
>>> +checkpatch-include-asm-checks-should-be-anchored.patch
>>> +checkpatch-reduce-warnings-for-include-of-asm-fooh-to-check-from-arch-barc.patch
>>> +checkpatch-report-any-absolute-references-to-kernel-source-files.patch
>>> +checkpatch-report-the-real-first-line-of-all-suspect-indents.patch
>>> +checkpatch-suspect-indent-skip-over-preprocessor-label-and-blank-lines.patch
>>> +checkpatch-%lx-tests-should-hand-%%-as-a-literal.patch
>>> +checkpatch-report-the-correct-lines-for-single-statement-blocks.patch
>>> +checkpatch-perform-indent-checks-on-perl.patch
>>> +checkpatch-version-022.patch
>>> +checkpatch-case-default-checks-should-only-check-changed-lines.patch
>>> +checkpatch-suppress-errors-triggered-by-short-patch.patch
>>> +checkpatch-handle-comment-quote-nesting-correctly.patch
>>> +checkpatch-check-line-endings-in-text-format-files.patch
>>> +checkpatch-suspect-indent-count-condition-lines-correctly.patch
>>> +checkpatch-ensure-we-only-apply-checks-to-the-lines-within-hunks.patch
>>> +checkpatch-version-023.patch
>>>
>>>  checkpatch updates
>>>
>>> +oss-remove-references-to-dead-sound-oss-vars-aedsp16_msssbpro.patch
>>>
>>>  OSS drivers
>>>
>>> +binfmt_somc-add-module_license.patch
>>>
>>>  binfmt
>>>
>>> +make-probe_serial_gsc-static.patch
>>> +serial-mpc52xx_uart-remove-code-associated-with-config_ppc_merge.patch
>>>
>>>  serial
>>>
>>> +mpc52xx_psc_spi-remove-code-associated-with-config_ppc_merge.patch
>>>
>>>  spi
>>>
>>> +i2o-fix-32-64bit-dma-locking.patch
>>>
>>>  i2o
>>>
>>> +drivers-net-xen-netfrontc-use-div_round_up.patch
>>>
>>>  xen
>>>
>>> +ecryptfs-remove-retry-loop-in-ecryptfs_readdir.patch
>>>
>>>  ecryptfs
>>>
>>> +autofs4-cleanup-autofs-mount-type-usage.patch
>>> +autofs4-track-uid-and-gid-of-last-mount-requester.patch
>>> +autofs4-track-uid-and-gid-of-last-mount-requester-fix.patch
>>> +autofs4-devicer-node-ioctl-docoumentation.patch
>>> +autofs4-add-miscellaneous-device-for-ioctls.patch
>>> +autofs4-add-miscellaneous-device-for-ioctls-fix.patch
>>> +autofs4-add-miscellaneous-device-for-ioctls-fix-2.patch
>>> +autofs4-add-miscellaneous-device-for-ioctls-fix-fix-3.patch
>>>
>>>  autofs
>>>
>>> +rtc-pcf8563-remove-client-validation.patch
>>> +rtc-ds1374-wakeup-support-update.patch
>>> +rtc-add-device-driver-for-dallas-ds3234-spi-rtc-chip-fix.patch
>>> +rtc-rtc-rs5c372-add-support-for-ricoh-r2025s-d-rtc.patch
>>> +rtc-file-close-consistently-disables-repeating-irqs.patch
>>> +rtc-cmos-strongly-avoid-hpet-emulation.patch
>>> +rtc-use-config_ppc-instead-of-config_ppc_merge.patch
>>> +rtc-rtc-m41t80c-add-support-for-the-st-m41t65-rtc.patch
>>>
>>>  rtc
>>>
>>> +make-gpiochip-label-const.patch
>>> +gpio-max7301-fix-the-race-between-chip-addition-and-pins-reconfiguration.patch
>>>
>>>  gpio
>>>
>>> +fb-push-down-the-bkl-in-the-ioctl-handler.patch
>>> +fb-push-down-the-bkl-in-the-ioctl-handler-checkpatch-fixes.patch
>>> +radeonfb-revert-fix-radeon-ddc-regression.patch
>>> +fb-convert-lock-unlock_kernel-into-local-fb-mutex.patch
>>> +neofb-reduce-panning-function.patch
>>> +viafb-viafbmodes-viafbtxt.patch
>>> +viafb-viafbmodes-viafbtxt-fix.patch
>>> +viafb-viafbmodes-viafbtxt-fix-fix.patch
>>> +viafb-makefile-kconfig.patch
>>> +viafb-accelc-accelh.patch
>>> +viafb-accelc-accelh-checkpatch-fixes.patch
>>> +viafb-accelc-accelh-update.patch
>>> +viafb-chiph-debugh.patch
>>> +viafb-dvic-dvih-globalc-and-globalh.patch
>>> +viafb-dvic-dvih-globalc-and-globalh-checkpatch-fixes.patch
>>> +viafb-hwc-hwh.patch
>>> +viafb-hwc-hwh-checkpatch-fixes.patch
>>> +viafb-ifacec-ifaceh-ioctlc-ioctlh.patch
>>> +viafb-lcdc-lcdh-lcdtblh.patch
>>> +viafb-makefile-shareh.patch
>>> +viafb-tbl1636c-tbl1636h-tbldpasettingc-tbldpasettingh.patch
>>> +viafb-viafbdevc-viafbdevh.patch
>>> +viafb-viafbdevc-viafbdevh-checkpatch-fixes.patch
>>> +viafb-viafbdevc-update.patch
>>> +viafb-via_i2cc-via_i2ch-viamodec-viamodeh.patch
>>> +viafb-via_utilityc-via_utilityh-vt1636c-vt1636h.patch
>>> +viafb-maintainers-entry.patch
>>> +fbdev-kconfig-update.patch
>>> +fbdev-kconfig-update-fix.patch
>>> +neofb-kill-some-redundant-code.patch
>>> +vga16fb-remove-open_lock-mutex.patch
>>> +neofb-remove-open_lock-mutex.patch
>>> +tdfxfb-do-not-make-changes-to-default-tdfx_fix.patch
>>> +intelfb-support-945gme-as-used-in-asus-eee-901.patch
>>> +cirrusfb-remove-information-about-memory-size-during-mode-change.patch
>>> +cirrusfb-simplify-clock-calculation.patch
>>> +cirrusfb-remove-24-bpp-mode.patch
>>> +cirrusfb-drop-device-pointers-from-cirrusfb_info.patch
>>> +cirrusfb-use-modedb-and-add-mode_option-parameter-2nd-rev.patch
>>> +cirrusfb-add-__devinit-attribute-to-probing-functions.patch
>>> +cirrusfb-eliminate-crt-registers-from-global-structure.patch
>>> +cirrusfb-drop-clock-fields-from-cirrusfb_regs-structure.patch
>>> +atmel_lcdfb-disallow-setting-larger-resolution-than-the-framebuffer-memory-can-handle.patch
>>> +efifb-imacfb-consolidation-hardware-support.patch
>>>
>>>  fbdev
>>>
>>> +pnp-remove-printk-with-outdated-version.patch
>>> +pnp-make-the-resource-type-an-unsigned-long.patch
>>> +pnp-make-the-resource-type-an-unsigned-long-fix.patch
>>>
>>>  pnp
>>>
>>> +telephony-remove-cvs-keywords.patch
>>>
>>>  telephony
>>>
>>> +ext2-fix-ext2-block-reservation-early-enospc-issue.patch
>>>
>>>  ext2
>>>
>>> +ext3-dont-try-to-resize-if-there-are-no-reserved-gdt-blocks-left.patch
>>> +ext3-fix-ext3-block-reservation-early-enospc-issue.patch
>>> +jbd-abort-instead-of-waiting-for-nonexistent-transactions.patch
>>>
>>>  ext3
>>>
>>> +hfsplus-quieten-down-mounting-hfsplus-journaled-fs-read-only.patch
>>> +hfsplus-fix-buffer-overflow-with-a-corrupted-image.patch
>>> +hfsplus-check-read_mapping_page-return-value.patch
>>> +hfsplus-fix-another-bug-when-reading-a-corrupted-image.patch
>>> +hfsplus-check-hfs_bnode_find-return-value.patch
>>>
>>>  hfsplus
>>>
>>> +reiserfs-procfsc-remove-cvs-keywords.patch
>>> +fs-reiserfs-use-an-is_err-test-rather-than-a-null-test.patch
>>>
>>>  reiserfs
>>>
>>> +quota-remove-cvs-keywords.patch
>>>
>>>  quota
>>>
>>> +cgroups-fix-probable-race-with-put_css_set-and-find_css_set.patch
>>> +cgroups-fix-probable-race-with-put_css_set-and-find_css_set-fix.patch
>>>
>>>  cgroups
>>>
>>> +devcgroup-use-kmemdup.patch
>>> +devcgroup-remove-unused-variable.patch
>>> +devcgroup-remove-spin_lock.patch
>>>
>>>  devcgroup
>>>
>>> -memrlimit-cgroup-mm-owner-callback-changes-to-add-task-info.patch
>>> +memrlimit-setup-the-memrlimit-controller-mm_owner-fix.patch
>>> +memrlimit-add-memrlimit-controller-accounting-and-control-memory-rlimit-enhance-mm_owner_changed-callback-to-deal-with-exited-owner.patch
>>> +memrlimit-add-memrlimit-controller-accounting-and-control-mm_owner-fix.patch
>>> +memrlimit-add-memrlimit-controller-accounting-and-control-mm_owner-fix-checkpatch-fixes.patch
>>> +memrlimit-add-memrlimit-controller-accounting-and-control-memory-rlimit-fix-crash-on-fork.patch
>>>
>>>  memrlimit controller
>>>
>>> +cpuset-use-seq_cpumask-seq_nodemask.patch
>>> +cpusetc-remove-extra-variable.patch
>>>
>>>  cpusets
>>>
>>> +irq-warn-about-irqf_disabledirqf_shared.patch
>>>
>>>  genirq
>>>
>>> +make-ptrace_untrace-static.patch
>>>
>>>  ptrace
>>>
>>> +kdump-update-elfcorehdr-documentation-to-reflect-supported-architectures.patch
>>> +kdump-use-is_kdump_kernel-in-sba_init.patch
>>> +kdump-add-is_vmcore_usable-and-vmcore_unusable.patch
>>> +kdump-add-is_vmcore_usable-and-vmcore_unusable-update.patch
>>> +kdump-use-is_vmcore_usable-and-vmcore_unusable-in-reserve_elfcorehdr.patch
>>> +kdump-ia64-always-reserve-elfcore-header-memory-in-crash-kernel.patch
>>>
>>>  kdump
>>>
>>> +message-queues-increase-range-limits.patch
>>> +message-queues-increase-range-limits-checkpatch-fixes.patch
>>>
>>>  IPC
>>>
>>> +compat_binfmt_elf-definition-tweak.patch
>>>
>>>  elf
>>>
>>> +applicomc-fix-apparently-broken-code-in-do_ac_read.patch
>>> +char-moxac-sparse-annotation.patch
>>>
>>>  char drivers
>>>
>>> +firmware-use-dev_printk-when-possible.patch
>>>
>>>  firmware
>>>
>>> +fs-partitions-acornc-remove-dead-code.patch
>>>
>>>  partitions
>>>
>>> +proc-move-sysrq-trigger-out-of-fs-proc.patch
>>> +proc-fix-return-value-of-proc_reg_open-in-too-late-case.patch
>>> +proc-proc_sys_root-tweak.patch
>>> +proc-remove-dummy-vmcore_open.patch
>>> +proc-remove-unused-get_dma_list.patch
>>>
>>>  procfs
>>>
>>> +sysctl-simplify-strategy.patch
>>>
>>>  sysctl
>>>
>>> +pid_ns-de_thread-kill-the-now-unneeded-child_reaper-change.patch
>>> +pid_ns-kill-the-now-unused-task_child_reaper.patch
>>>
>>>  pidns
>>>
>>> +trace-code-and-documentation-merging-documentation-tracetxt-with-documentation-filesystems-relaytxt.patch
>>> +rename-lib-trace-files-to-kernel-relay_debugfs-and-enhancements.patch
>>> +rename-lib-trace-files-to-kernel-relay_debugfs-and-enhancements-fix.patch
>>>
>>>  relayfs
>>>
>>> +make-i82443bxgx_edac-coexist-with-intel_agp.patch
>>>
>>>  edac
>>>
>>> +parport-remove-cvs-keywords.patch
>>>
>>>  parport
>>>
>>> +tpm-work-around-bug-in-broadcom-bcm0102-chipset.patch
>>> +tpm-include-moderated-for-non-subscribers-notation-in-maintainers.patch
>>> +drivers-char-tpm-tpmc-fix-error-patch-memory-leak.patch
>>>
>>>  tpm
>>>
>>> +w1-be-able-to-manually-add-and-remove-slaves-fix.patch
>>>
>>>  Fix w1-be-able-to-manually-add-and-remove-slaves.patch
>>>
>>> +gru-driver-minor-updates.patch
>>> +gru-driver-minor-updates-fix.patch
>>>
>>>  GRU updates
>>>
>>> +kernel-call-constructors-fix-3.patch
>>> -gcov-create-links-to-gcda-files-in-build-directory.patch
>>> +gcov-architecture-specific-compile-flag-adjustments-x86_64-fix-2.patch
>>>
>>>  gcov
>>>
>>> -resource-add-new-ioresource_clk-type-v2.patch
>>> -i2c-sh_mobile-ioresource_clk-support.patch
>>>
>>>  Dropped
>>>
>>> +byteorder-add-new-headers-for-make-headers-install.patch
>>> +byteorder-use-generic-c-version-for-value-byteswapping.patch
>>>
>>>  byteorder
>>>
>>> +ipc-semc-make-free_un-static.patch
>>> +make-fs-proc-proc_sysctlc-grab_header-static.patch
>>> +make-hp_wmi_notify-static.patch
>>> +make-kprobesc-kretprobe_table_lock-static.patch
>>> +acpi-use-bcd2bin-bin2bcd.patch
>>> +alpha-use-bcd2bin-bin2bcd.patch
>>> +cris-use-bcd2bin-bin2bcd.patch
>>> +drivers-rtc-use-bcd2bin-bin2bcd.patch
>>> +rtc-use-bcd2bin-bin2bcd.patch
>>> +mips-use-bcd2bin-bin2bcd.patch
>>> +mn10300-use-bcd2bin-bin2bcd.patch
>>> +i2c-use-bcd2bin-bin2bcd.patch
>>> +drivers-scsi-sr_vendorc-use-bcd2bin.patch
>>> +remove-the-obsolete-bcdbin-binbcd-macros.patch
>>> +include-linux-bcdh-remove-comments.patch
>>> +fs-kconfig-move-ext2-ext3-ext4-jbd-jbd2-out.patch
>>> +fs-kconfig-move-autofs-autofs4-out.patch
>>> +fs-kconfig-move-cifs-out.patch
>>>
>>>  cleanups
>>>
>>> +nilfs2-continuous-snapshotting-file-system.patch
>>> +nilfs2-continuous-snapshotting-file-system-fix.patch
>>> +nilfs2-continuous-snapshotting-file-system-fix-fix-2.patch
>>>
>>>  New log-based fs
>>>
>>> +reiser4-compile-warning-cleanups.patch
>>> +reiser4-use-wake_up_process-instead-of-wake_up-when-possible.patch
>>> +reiser4-track-upstream-changes.patch
>>>
>>>  reiser4 fixes
>>>
>>> 690 commits in 682 patch files
>>>
>>> All patches:
>>>
>>> ftp://ftp.kernel.org/pub/linux/kernel/people/akpm/patches/2.6/2.6.27-rc5/2.6.27-rc5-mm1/patch-list
>>>
>>> --
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>>>       
>> --
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>
>
>
>   

From anemo@mba.ocn.ne.jp Thu Sep 11 16:03:52 2008
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Subject: Re: [PATCH 1/2] ide: Add tx4939ide driver
From:	Atsushi Nemoto <anemo@mba.ocn.ne.jp>
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On Wed, 10 Sep 2008 19:55:16 +0400, Sergei Shtylyov <sshtylyov@ru.mvista.com> wrote:
> > But the "Command Transfer Mode Select" bits affects access timings on
> > setting task registers for DMA command.
> 
>     So what? PIO and DMA are different protocols on IDE bus, so they shouldn't 
> affect each other. The IDE core will always tune the best PIO mode for you, so 
> the optimal command timings will be set.

Hmm, that would be a thing I had misunderstood.  I thought
set_pio_mode is not called when the drive was DMA capable.

Thank you for detailed review!

---
Atsushi Nemoto

From ddaney@avtrex.com Thu Sep 11 16:05:52 2008
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Subject: Re: [Patch 2/6] MIPS: Add HARDWARE_WATCHPOINTS definitions and support
 code.
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Geert Uytterhoeven wrote:
> On Wed, 10 Sep 2008, David Daney wrote:
> 
> Given
> 
>> +	case 4:
>> +		write_c0_watchlo3(watches->watchlo[3]);
>> +		/* Write 1 to the I, R, and W bits to clear them, and
>> +		   1 to G so all ASIDs are trapped. */
>> +		write_c0_watchhi3(0x40000007 | watches->watchhi[3]);
>> +	case 3:
>> +		write_c0_watchlo2(watches->watchlo[2]);
>> +		write_c0_watchhi2(0x40000007 | watches->watchhi[2]);
>> +	case 2:
>> +		write_c0_watchlo1(watches->watchlo[1]);
>> +		write_c0_watchhi1(0x40000007 | watches->watchhi[1]);
>> +	case 1:
>> +		write_c0_watchlo0(watches->watchlo[0]);
>> +		write_c0_watchhi0(0x40000007 | watches->watchhi[0]);
> 
> and
> 
>> +	case 4:
>> +		watches->watchhi[3] = (read_c0_watchhi3() & 0x0fff);
>> +	case 3:
>> +		watches->watchhi[2] = (read_c0_watchhi2() & 0x0fff);
>> +	case 2:
>> +		watches->watchhi[1] = (read_c0_watchhi1() & 0x0fff);
>> +	case 1:
>> +		watches->watchhi[0] = (read_c0_watchhi0() & 0x0fff);

[...]

> do the same for each registers, perhaps it makes sense to create
> read_c0_watchhi(), write_c0_watchlo(), and write_c0_watchhi() macros
> that take the watchdog register index as a parameter? Then the above can
> be turned in simple loops.

I thought that too when I first started looking at it, but the
{read,write}_c0_watchhi{0,1,2,3,4,5,6,7} macros expand to a single
machine instruction.  The bit pattern of the instruction is determined
at compile time, so you would need something like the switch statement
somewhere.  Explicitly showing it in the code seemed as good as hiding
the complexity in some macro or access function.

[...]

>> +	c->watch_reg_count = 7;
>> +	t = read_c0_watchhi6();
>> +	if ((t & 0x80000000) == 0)
>> +		return;
>> +
>> +	c->watch_reg_count = 8;
> 
> and here
> 
> BTW, no check for read_c0_watchhi7()?
> 

The current patch uses a maximum of four register sets, since we are
only reporting the number of sets, we don't care about the
characteristics of watchhi[7] and thus don't need to read it.

Thanks,
David Daney

From sshtylyov@ru.mvista.com Thu Sep 11 16:17:28 2008
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Subject: Re: [PATCH 1/2] ide: Add tx4939ide driver
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Atsushi Nemoto wrote:

>>>But the "Command Transfer Mode Select" bits affects access timings on
>>>setting task registers for DMA command.

>>    So what? PIO and DMA are different protocols on IDE bus, so they shouldn't 
>>affect each other. The IDE core will always tune the best PIO mode for you, so 
>>the optimal command timings will be set.

> Hmm, that would be a thing I had misunderstood.  I thought
> set_pio_mode is not called when the drive was DMA capable.

    PIO autotuning was optional before (done only if the driver requested it 
via setting drive->autotune), but now done always.

MBR, Sergei

From florian@openwrt.org Thu Sep 11 16:48:49 2008
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From:	Florian Fainelli <florian@openwrt.org>
Date:	Thu, 11 Sep 2008 17:48:00 +0200
Subject: [PATCH] rb532: provide GPIO_BUILTIN_NR and irq_to_gpio/gpio_to_irq
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This patchs defines the number of built-in the GPIOs present
on the SoC as Documentation/gpio.txt recommends to do.
Define irq_to_gpio/gpio_to_irq to return the right values so that
it fixes a compilation error on drivers/gpio/gpiolib.c
when enabling debugfs.

Signed-off-by: Florian Fainelli <florian@openwrt.org>
---
diff --git a/include/asm-mips/mach-rc32434/gpio.h b/include/asm-mips/mach-rc32434/gpio.h
index 77ac353..ff40eab 100644
--- a/include/asm-mips/mach-rc32434/gpio.h
+++ b/include/asm-mips/mach-rc32434/gpio.h
@@ -14,16 +14,16 @@
 #define _RC32434_GPIO_H_
 
 #include <linux/types.h>
+#include <asm-generic/gpio.h>
 
-#define gpio_get_value __gpio_get_value
-#define gpio_set_value __gpio_set_value
-
-#define gpio_cansleep __gpio_cansleep
+#define NR_BUILTIN_GPIO		32
 
-#define gpio_to_irq(gpio)	IRQ_GPIO(gpio)
-#define irq_to_gpio(irq)	IRQ_TO_GPIO(irq)
+#define gpio_get_value	__gpio_get_value
+#define gpio_set_value	__gpio_set_value
+#define gpio_cansleep	__gpio_cansleep
 
-#include <asm-generic/gpio.h>
+#define gpio_to_irq(gpio)	(8 + 4 * 32 + gpio)
+#define irq_to_gpio(irq)	(irq - (8 + 4 * 32))
 
 struct rb532_gpio_reg {
 	u32   gpiofunc;   /* GPIO Function Register

From anemo@mba.ocn.ne.jp Thu Sep 11 16:52:40 2008
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Subject: Re: [PATCH 1/2] ide: Add tx4939ide driver
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On Thu, 11 Sep 2008 03:02:05 +0400, Sergei Shtylyov <sshtylyov@ru.mvista.com> wrote:
> > +#define TX4939IDE_readl(base, reg) \
> > +	__raw_readl((void __iomem *)((base) + TX4939IDE_REG32(reg)))
> > +#define TX4939IDE_readw(base, reg) \
> > +	__raw_readw((void __iomem *)((base) + TX4939IDE_REG16(reg)))
> > +#define TX4939IDE_readb(base, reg) \
> > +	__raw_readb((void __iomem *)((base) + TX4939IDE_REG8(reg)))
> > +#define TX4939IDE_writel(val, base, reg) \
> > +	__raw_writel(val, (void __iomem *)((base) + TX4939IDE_REG32(reg)))
> > +#define TX4939IDE_writew(val, base, reg) \
> > +	__raw_writew(val, (void __iomem *)((base) + TX4939IDE_REG16(reg)))
> > +#define TX4939IDE_writeb(val, base, reg) \
> > +	__raw_writeb(val, (void __iomem *)((base) + TX4939IDE_REG8(reg)))
> >   
> 
>    Why dont you #define __swizzle_addr_[bwlq]() in 
> include/asm/mach/magle-port.h?
> Or you never use read[bwlq]() accessorts for the SoC registers?

Because __swizzle_addr_[bwlq]() affects _all_ device including PCI
devices.  I hope all PCI driver works as is, so put all dirty things
in platform specific driver ;-)

> > +static void tx4939ide_check_error_ints(ide_hwif_t *hwif, u16 stat)
> > +{
> > +	if (stat & TX4939IDE_INT_BUSERR) {
> > +		unsigned long base = TX4939IDE_BASE(hwif);
> > +		/* reset FIFO */
> > +		TX4939IDE_writew(TX4939IDE_readw(base, Sys_Ctl) |
> > +				 0x4000,
> > +				 base, Sys_Ctl);
> >   
> 
>    Are you sure bit 14 is self-clearing? The datashhet doesn't seem to 
> say that...

Well, I cannot remember...  I thought I checked that bit cleard by
reading it, but actually the bit is write-only.  Maybe clearing
explicitly would be a safe bet.

> > +	hwif = HWIF(drive);
> > +	base = TX4939IDE_BASE(hwif);
> >   
> 
>    I think you might cache the base address in hwif->extra_base to avoid 
> masking with ~0xfff every time...

OK, I will try it.

> > +static u8 tx4939ide_cable_detect(ide_hwif_t *hwif)
> > +{
> > +	unsigned long base = TX4939IDE_BASE(hwif);
> > +
> > +	return (TX4939IDE_readw(base, Sys_Ctl) & 0x2000)
> > +		? ATA_CBL_PATA40 : ATA_CBL_PATA80;
> >   
> 
>    Could you keep ? on the same line as the 1st operand?

OK.

> > +	select_data = (hwif->select_data >> (is_slave ? 16 : 0)) & 0xffff;
> > +	TX4939IDE_writew(select_data, base, Sys_Ctl);
> > +	if (is_slave)
> > +		TX4939IDE_writew(sect_size / 2, base, Xfer_Cnt_2);
> > +	else
> > +		TX4939IDE_writew(sect_size / 2, base, Xfer_Cnt_1);
> >   
> 
> 	TX4939IDE_writew(sect_size / 2, base, is_slave ? Xfer_Cnt_2 : Xfer_Cnt_1);

OK.

> > +	rc = __tx4939ide_dma_setup(drive);
> > +	if (rc == 0) {
> > +		/* Number of sectors to transfer. */
> > +		nframes = 0;
> > +		for (i = 0; i < hwif->sg_nents; i++)
> > +			nframes += sg_dma_len(&hwif->sg_table[i]);
> > +		BUG_ON(nframes % sect_size != 0);
> > +		nframes /= sect_size;
> > +		BUG_ON(nframes == 0);
> > +		TX4939IDE_writew(nframes, base, Sec_Cnt);
> >   
> 
>    Ugh, it looks much easier in my TC86C001 driver... doesn't 
> hwgroup->rq->nr_sectors give you a number of 512 sectors?
> Why bother with other (multiple of 512) sizes when you can always 
> program transfer in 512-byte sectors? Or was I wrong there?

Hmm.  Good idea.  I will try it.

> > +static int tx4939ide_dma_end(ide_drive_t *drive)
> > +{
> > +	if ((dma_stat & 7) == 0 &&
> > +	    (ctl & (TX4939IDE_INT_XFEREND | TX4939IDE_INT_HOST)) ==
> > +	    (TX4939IDE_INT_XFEREND | TX4939IDE_INT_HOST))
> > +		/* INT_IDE lost... bug? */
> > +		return 0;
> >   
> 
>    You shouldn't fake the BMDMA interrupt. If it's not there, it's not 
> there. Or does this actually happen?

IIRC, Yes.

> > +		/*
> > +		 * If only one of XFERINT and HOST was asserted, mask
> > +		 * this interrupt and wait for an another one.  Note
> >   
> 
>    This comment somewhat contradicts the code which returns 1 if only 
> HOST interupt is asserted if ERR is set.

Indeed.  I will make the comment more precise.

> > +	case TX4939IDE_INT_HOST | TX4939IDE_INT_XFEREND:
> > +		dma_stat = TX4939IDE_readb(base, DMA_stat);
> > +		if (!(dma_stat & 4))
> > +			pr_debug("%s: weired interrupt status. "
> >   
> 
>    Weird.

Sure.  But it can happen IIRC...

> > +static void tx4939ide_hwif_init(ide_hwif_t *hwif)
> > +{
> > +	unsigned long base = TX4939IDE_BASE(hwif);
> > +	int timeout;
> > +
> > +	/* Soft Reset */
> > +	TX4939IDE_writew(0x8000, base, Sys_Ctl);
> > +	mmiowb();
> > +	udelay(1);	/* at least 20 UPSCLK (100ns for 200MHz GBUSCLK) */
> > +	/* ATA Hard Reset */
> > +	TX4939IDE_writew(0x0800, base, Sys_Ctl);
> > +	timeout = 1000;
> > +	while (TX4939IDE_readw(base, Sys_Ctl) & 0x0800) {
> > +		if (timeout--)
> > +			break;
> > +		udelay(1);
> > +	}
> 
>    Don't do this -- there's nothing gained from the ATA hard reset but 
> an extra delay; I removed such stuff from the TC86C001 driver. The IDE 
> core will soft-reset the bus if needed...

OK.

> > #ifdef __BIG_ENDIAN
> > +/* custom iops (independent from SWAP_IO_SPACE) */
> >   
> > +static u8 mm_inb(unsigned long port)
> > +{
> > +	return (u8)readb((void __iomem *)port);
> > +}
> > +static void mm_outb(u8 value, unsigned long port)
> > +{
> > +	writeb(value, (void __iomem *)port);
> > +}
> > +static void mm_tf_load(ide_drive_t *drive, ide_task_t *task)
> > +{
> >   
> [...]
> > +	if (task->tf_flags & IDE_TFLAG_OUT_DEVICE) {
> > +		unsigned long base = TX4939IDE_BASE(hwif);
> > +		mm_outb((tf->device & HIHI) | drive->select,
> > +			 io_ports->device_addr);
> >   
> 
>    I'm seeing no sense in re-defining so far...
> 
> > +		/* Fix ATA100 CORE System Control Register */
> > +		TX4939IDE_writew(TX4939IDE_readw(base, Sys_Ctl) & 0x07f0,
> > +				 base, Sys_Ctl);
> >   
> 
>    Ah... you're doing it here (but not in LE mode?). I think to avoid 
> duplicating ide_tf_load() you need ot use selectproc().

Oh, my fault.  LE mode also needs this fix.  I still need ide_tf_load
on BE mode to support IDE_TFLAG_OUT_DATA.

> > +static void mm_insw_swap(unsigned long port, void *addr, u32 count)
> > +{
> > +	unsigned short *ptr = addr;
> > +	unsigned long size = count * 2;
> > +	port &= ~1;
> > +	while (count--)
> > +		*ptr++ = le16_to_cpu(__raw_readw((void __iomem *)port));
> > +	__ide_flush_dcache_range((unsigned long)addr, size);
> >   
> 
>    Why is this needed BTW?

Do you mean __ide_flush_dcache_range?  This is needed to avoid cache
inconsistency on PIO drive.  PIO transfer only writes to cache but
upper layers expects the data is in main memory.

> > +static const struct ide_tp_ops tx4939ide_tp_ops = {
> > +	.exec_command		= ide_exec_command,
> > +	.read_status		= ide_read_status,
> > +	.read_altstatus		= ide_read_altstatus,
> > +	.read_sff_dma_status	= tx4939ide_read_sff_dma_status,
> >   
> 
>    Hum, it should be re-defined in both LE and BE mode (but actually not 
> called anyway).

What do you mean?  Please elaborate?

> > +	.host_flags = IDE_HFLAG_MMIO,
> > +	.pio_mask = ATA_PIO4,
> > +	.mwdma_mask = ATA_MWDMA2,
> > +	.swdma_mask = ATA_SWDMA2,
> >   
> 
>    No, SWDMA isn't supported.

Oh, indeed.

> > +	mapbase = (unsigned long)devm_ioremap(&pdev->dev, res->start,
> > +					      res->end - res->start + 1);
> > +	if (!mapbase)
> > +		return -EBUSY;
> > +	memset(&hw, 0, sizeof(hw));
> > +	hw.io_ports.data_addr = mapbase + TX4939IDE_REG8(DATA);
> >   
> 
>    Wrong, should be TX4939IDE_REG16(). I wonder how it manages to work 
> in BE mode with this...

Well, "port &= ~1" in mm_insw_swap() and mm_outsw_swap do the trick.

> > +#ifdef CONFIG_PM
> > +static int tx4939ide_resume(struct platform_device *dev)
> > +{
> > +	struct ide_host *host = platform_get_drvdata(dev);
> > +	ide_hwif_t *hwif = host->ports[0];
> > +	unsigned long base = TX4939IDE_BASE(hwif);
> > +
> > +	tx4939ide_hwif_init(hwif);
> >   
> 
>    ATA hard reset when coming out of suspend? Nice... :-)

Will be fixed in tx4939ide_hwif_init().


Thanks!

---
Atsushi Nemoto

From florian@openwrt.org Thu Sep 11 16:56:27 2008
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From:	Florian Fainelli <florian@openwrt.org>
Date:	Thu, 11 Sep 2008 17:55:41 +0200
Subject: [PATCH] rb532: do not use phys_t
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MIPS include types.h says that using phys_t is bad, which in
fact is an unsigned long, so use an unsigned long directly.

Signed-off-by: Florian Fainelli <florian@openwrt.org>
---
diff --git a/arch/mips/rb532/prom.c b/arch/mips/rb532/prom.c
index 46ca24d..c37ceda 100644
--- a/arch/mips/rb532/prom.c
+++ b/arch/mips/rb532/prom.c
@@ -123,8 +123,8 @@ void __init prom_setup_cmdline(void)
 void __init prom_init(void)
 {
 	struct ddr_ram __iomem *ddr;
-	phys_t memsize;
-	phys_t ddrbase;
+	unsigned long memsize;
+	unsigned long ddrbase;
 
 	ddr = ioremap_nocache(ddr_reg[0].start,
 			ddr_reg[0].end - ddr_reg[0].start);

From jeremy@goop.org Thu Sep 11 17:06:23 2008
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Geert Uytterhoeven wrote:
>> PowerPC also defines a phys_addr_t with the same meaning as x86; the
>> powerpc arch maintainers are happy with these patches.
>>     
>
> If I'm not mistaking, this is also true for some MIPS machines.
>   

Nothing turns up in a grep over arch/mips and include/asm-mips.

    J

From macro@linux-mips.org Thu Sep 11 17:15:53 2008
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On Thu, 11 Sep 2008, Florian Fainelli wrote:

> MIPS include types.h says that using phys_t is bad, which in
> fact is an unsigned long, so use an unsigned long directly.

 That is bad indeed.  A physical address might not fit in unsigned long.  
Actually the upstream is apparently adopting phys_addr_t for this purpose 
right now, so you might consider waiting with your patch till the thing 
settles down.  Note that by using a generic type you take away semantics 
which will make future adjustments more difficult.

  Maciej

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On Thu, 11 Sep 2008, Jeremy Fitzhardinge wrote:

> > If I'm not mistaking, this is also true for some MIPS machines.
> >   
> 
> Nothing turns up in a grep over arch/mips and include/asm-mips.

 It's called phys_t for MIPS.  It's time to make it consistent probably.

  Maciej

From khickey@rmicorp.com Thu Sep 11 18:59:44 2008
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From:	Kevin Hickey <khickey@rmicorp.com>
To:	linux-mips@linux-mips.org, ralf@linux-mips.org,
	linux-usb@vger.kernel.org, mano@roarinelk.homelinux.net
Cc:	Kevin Hickey <khickey@rmicorp.com>
Subject: [PATCH] Au1200 USB Device Controller and device-only OTG
Date:	Thu, 11 Sep 2008 12:59:27 -0500
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This patch adds support for the USB Device Controller on the Au1200 SOC as
well as basic device-only OTG (On-The-Go) support.  There are some defines and
hooks for future expansion to full OTG support.

This has been tested with the g_zero gadget as well as the g_file_storage
gadget on a DB1250 board.

Signed-off-by: Kevin Hickey <khickey@rmicorp.com>
---
 arch/mips/configs/db1200_defconfig |   21 +
 drivers/usb/core/Kconfig           |    2 -
 drivers/usb/gadget/Kconfig         |   49 +-
 drivers/usb/gadget/Makefile        |    5 +
 drivers/usb/gadget/au1200_otg.c    |  854 +++++++++++
 drivers/usb/gadget/au1200_otg.h    |  138 ++
 drivers/usb/gadget/au1200_udc.c    | 2862 ++++++++++++++++++++++++++++++++++++
 drivers/usb/gadget/au1200_udc.h    |  816 ++++++++++
 drivers/usb/gadget/au1200_uoc.h    | 1021 +++++++++++++
 drivers/usb/gadget/gadget_chips.h  |    6 +
 include/linux/usb/otg.h            |    7 +-
 11 files changed, 5770 insertions(+), 11 deletions(-)
 create mode 100644 drivers/usb/gadget/au1200_otg.c
 create mode 100644 drivers/usb/gadget/au1200_otg.h
 create mode 100644 drivers/usb/gadget/au1200_udc.c
 create mode 100644 drivers/usb/gadget/au1200_udc.h
 create mode 100644 drivers/usb/gadget/au1200_uoc.h

diff --git a/arch/mips/configs/db1200_defconfig b/arch/mips/configs/db1200_defconfig
index ab17973..b69fec3 100644
--- a/arch/mips/configs/db1200_defconfig
+++ b/arch/mips/configs/db1200_defconfig
@@ -914,13 +914,34 @@ CONFIG_USB_ARCH_HAS_EHCI=y
 #
 CONFIG_USB_GADGET=m
 # CONFIG_USB_GADGET_DEBUG_FILES is not set
+CONFIG_USB_GADGET_SELECTED=y
+# CONFIG_USB_GADGET_AMD5536UDC is not set
+# CONFIG_USB_GADGET_ATMEL_USBA is not set
+# CONFIG_USB_GADGET_FSL_USB2 is not set
 # CONFIG_USB_GADGET_NET2280 is not set
 # CONFIG_USB_GADGET_PXA2XX is not set
+# CONFIG_USB_GADGET_M66592 is not set
 # CONFIG_USB_GADGET_GOKU is not set
 # CONFIG_USB_GADGET_LH7A40X is not set
 # CONFIG_USB_GADGET_OMAP is not set
+CONFIG_USB_GADGET_AU1200=y
+CONFIG_USB_AU1200=m
+# CONFIG_USB_GADGET_S3C2410 is not set
 # CONFIG_USB_GADGET_AT91 is not set
 # CONFIG_USB_GADGET_DUMMY_HCD is not set
+CONFIG_USB_GADGET_DUALSPEED=y
+CONFIG_USB_PORT_AU1200OTG=y
+CONFIG_USB_AU1200OTG=m
+CONFIG_USB_ZERO=m
+# CONFIG_USB_ETH is not set
+CONFIG_USB_GADGETFS=m
+CONFIG_USB_FILE_STORAGE=m
+# CONFIG_USB_FILE_STORAGE_TEST is not set
+# CONFIG_USB_G_SERIAL is not set
+# CONFIG_USB_MIDI_GADGET is not set
+CONFIG_MMC=y
+# CONFIG_MMC_DEBUG is not set
+# CONFIG_MMC_UNSAFE_RESUME is not set
 # CONFIG_USB_GADGET_DUALSPEED is not set
 
 #
diff --git a/drivers/usb/core/Kconfig b/drivers/usb/core/Kconfig
index cc9f397..cc54c55 100644
--- a/drivers/usb/core/Kconfig
+++ b/drivers/usb/core/Kconfig
@@ -106,8 +106,6 @@ config USB_OTG
 	bool
 	depends on USB && EXPERIMENTAL
 	select USB_SUSPEND
-	default n
-
 
 config USB_OTG_WHITELIST
 	bool "Rely on OTG Targeted Peripherals List"
diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig
index acc95b2..ceb8a17 100644
--- a/drivers/usb/gadget/Kconfig
+++ b/drivers/usb/gadget/Kconfig
@@ -315,16 +315,28 @@ config USB_OMAP
 	default USB_GADGET
 	select USB_GADGET_SELECTED
 
-config USB_OTG
-	boolean "OTG Support"
-	depends on USB_GADGET_OMAP && ARCH_OMAP_OTG && USB_OHCI_HCD
+config USB_GADGET_AU1200
+	boolean "AU1200 USB Device Controller"
+	depends on SOC_AU1200
+	select USB_GADGET_DUALSPEED
 	help
-	   The most notable feature of USB OTG is support for a
-	   "Dual-Role" device, which can act as either a device
-	   or a host.  The initial role choice can be changed
-	   later, when two dual-role devices talk to each other.
+	   The RMI Alchemy Au1200 and Au1250 SOCs include a full On-The-Go port
+	   with USB 1.1 and USB 2.0 support.  The device port supports 4
+	   bidirectional endpoints plus the default endpoint ep0.
+
+	   This driver provides the device mode for the On-The-Go port.  The
+	   port will not be active unless the au1200_otg driver is loaded or
+	   built statically.
+
+	   Say "y" to link the driver statically, or "m" to build a
+	   dynamically linked module called "au1200_udc" and force all
+	   gadget drivers to also be dynamically linked.
 
-	   Select this only if your OMAP board has a Mini-AB connector.
+config USB_AU1200
+	tristate
+	depends on USB_GADGET_AU1200
+	default USB_GADGET
+	select USB_GADGET_SELECTED
 
 config USB_GADGET_S3C2410
 	boolean "S3C2410 USB Device Controller"
@@ -407,6 +419,27 @@ config USB_GADGET_DUALSPEED
 	  Means that gadget drivers should include extra descriptors
 	  and code to handle dual-speed controllers.
 
+config USB_PORT_AU1200OTG
+	boolean "AU1200 USB portmux control (On-The-Go support)"
+	depends on USB_GADGET_AU1200 || USB_EHCI_HCD || USB_OHCI_HCD
+	default n
+	help
+	   The AU1200 and Au1200 USB device port can be used as either a host
+	   port or a device port.  This driver configures the port based on
+	   hardware or software set criteria.  It is required to be loaded for
+	   au1200_udc to be useful.
+
+	   NOTE: Currently, only device-port mode is supported.  Host-port and
+	   other On The Go modes will be supported in a future release.
+
+	   Say "y" to link this driver statically or "m" to build a dynamically
+	   linked module called "au1200_otg".
+
+config USB_AU1200OTG
+	tristate
+	depends on USB_PORT_AU1200OTG
+	default USB_AU1200
+
 #
 # USB Gadget Drivers
 #
diff --git a/drivers/usb/gadget/Makefile b/drivers/usb/gadget/Makefile
index fcb5cb9..d2af7cd 100644
--- a/drivers/usb/gadget/Makefile
+++ b/drivers/usb/gadget/Makefile
@@ -12,6 +12,7 @@ obj-$(CONFIG_USB_PXA25X)	+= pxa25x_udc.o
 obj-$(CONFIG_USB_PXA27X)	+= pxa27x_udc.o
 obj-$(CONFIG_USB_GOKU)		+= goku_udc.o
 obj-$(CONFIG_USB_OMAP)		+= omap_udc.o
+obj-$(CONFIG_USB_AU1200)	+= au1200_udc.o
 obj-$(CONFIG_USB_LH7A40X)	+= lh7a40x_udc.o
 obj-$(CONFIG_USB_S3C2410)	+= s3c2410_udc.o
 obj-$(CONFIG_USB_AT91)		+= at91_udc.o
@@ -49,3 +50,7 @@ obj-$(CONFIG_USB_G_PRINTER)	+= g_printer.o
 obj-$(CONFIG_USB_MIDI_GADGET)	+= g_midi.o
 obj-$(CONFIG_USB_CDC_COMPOSITE) += g_cdc.o
 
+#
+# AU1200 USB OTG options
+#
+obj-$(CONFIG_USB_AU1200OTG)	+= au1200_otg.o
diff --git a/drivers/usb/gadget/au1200_otg.c b/drivers/usb/gadget/au1200_otg.c
new file mode 100644
index 0000000..a110aff
--- /dev/null
+++ b/drivers/usb/gadget/au1200_otg.c
@@ -0,0 +1,854 @@
+/*
+ * Au1200 On The Go port driver.
+ */
+
+/*
+ * Copyright (C) 2008 RMI Corporation (http://www.rmicorp.com)
+ * Author: Kevin Hickey (khickey@rmicorp.com)
+ *
+ * THIS SOFTWARE IS PROVIDED BY RMI Corporation 'AS IS' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO
+ * EVENT SHALL RMI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+/*****************************************************************************
+ *  Includes
+ *****************************************************************************/
+
+#include <linux/module.h>
+#include <linux/pci.h>
+#include <linux/kernel.h>
+#include <linux/version.h>
+#include <linux/delay.h>
+#include <linux/ioport.h>
+#include <linux/sched.h>
+#include <linux/slab.h>
+#include <linux/smp_lock.h>
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/timer.h>
+#include <linux/list.h>
+#include <linux/interrupt.h>
+
+#include <asm/byteorder.h>
+#include <linux/io.h>
+#include <asm/irq.h>
+#include <asm/system.h>
+#include <asm/unaligned.h>
+
+#include <linux/platform_device.h>
+
+#include <asm/mach-au1x00/au1000.h>
+#include <asm/mach-au1x00/au1000_gpio.h>
+
+#include <linux/usb.h>
+#include <linux/usb/gadget.h>
+#include <linux/usb/otg.h>
+
+#define	DRIVER_DESC		"Au1200 USB OTG Controller"
+#define DRIVER_NAME_FOR_PRINT   OTG_DRIVER_NAME
+
+#include "au1200_otg.h"
+#include "au1200_uoc.h"
+
+
+/*****************************************************************************
+ *  Function Declarations
+ *****************************************************************************/
+
+static u32 otg_app_query(int);
+static int au1200otg_set_peripheral(struct otg_transceiver *,
+		struct usb_gadget *);
+
+
+/*****************************************************************************
+ *  Data
+ *****************************************************************************/
+
+static const char driver_name[] = OTG_DRIVER_NAME;
+static const char driver_desc[] = DRIVER_DESC;
+
+static struct otg *the_controller;
+static const char *transceiver_label = "au1200_otg";
+
+static u32 init_state;
+
+struct usb_otg_gadget_extension otg_gadget_extension = {
+	.request = NULL,
+	.query   = otg_app_query,
+	.notify  = NULL
+};
+
+static u32 state_mask;
+u32 otg_tmr_high_count;
+
+/*****************************************************************************
+ *  Function Definitions
+ *****************************************************************************/
+
+/**
+ * \brief
+ * fill OTG transceiver struct
+ *
+ * \param  transceiver  OTG transceiver
+ *
+ * \return              void
+ */
+static inline void otg_init_transceiver(struct otg_transceiver *transceiver)
+{
+	transceiver->dev            = NULL;
+	transceiver->label          = transceiver_label;
+	transceiver->default_a      = 0;
+	transceiver->state          = OTG_STATE_UNDEFINED;
+	transceiver->prv_state      = OTG_STATE_UNDEFINED;
+	transceiver->params         = 0;
+	transceiver->otg_priv       = (void *) &otg_gadget_extension;
+	transceiver->host           = NULL;
+	transceiver->gadget         = NULL;
+	transceiver->port_status    = 0;
+	transceiver->port_change    = 0;
+	transceiver->set_host       = NULL;
+	transceiver->set_peripheral = au1200otg_set_peripheral;
+	transceiver->set_power      = NULL;
+	transceiver->start_srp      = NULL;
+	transceiver->start_hnp      = NULL;
+}
+
+/**
+ * \brief
+ * OTG state change
+ *
+ * subset of OTG states to support the gadget only or
+ * ID pin configuration
+ *
+ * \param  otg          OTG controller info
+ * \param  event_code   event that requested a state change
+ * \param  pEvt_mask
+ *
+ * \return              events that were not handled here
+ */
+u32 otg_change_state(struct otg *otg, u32 _event, u32 *pEvt_mask)
+{
+	u32  event_code = _event;
+	u32  uoc_status = get_status(otg);
+
+	if (GOT_EVENT(OTG_GADGET_READY, event_code) &&
+			((otg->transceiver.state & OTG_STATE_MASK) !=
+			 OTG_STATE_UNDEFINED)) {
+
+		/* Switch from "NO_B_DEVICE" states to normal operation or   */
+		/*       deactivate operations in case gadget was unloaded   */
+
+		CHANGE_STATE(otg, OTG_STATE_UNDEFINED, pEvt_mask);
+	}
+	if ((OTG_INT_TMX & event_code) && otg_tmr_high_count) {
+
+		/* a long timer is running : decrement the high part         */
+
+		restart_timer(otg);
+		otg_tmr_high_count--;
+		RES_EVENT(OTG_INT_TMX, event_code);
+	}
+
+	do {
+		switch (otg->transceiver.state & OTG_STATE_MASK) {
+		/* NOT_ASSIGNED (yet): init state, 1st time after loading     */
+		/* ======================================================     */
+
+		case OTG_STATE_UNDEFINED:
+
+			CHECK_STATE(otg, OTG_STATE_UNDEFINED, pEvt_mask);
+
+			if (IS_FLAG_RES(otg, OTG_FLAGS_ACTIV)) {
+
+				/* seems to be the first time: let it run !   */
+
+				SET_FLAG(otg, OTG_FLAGS_ACTIV);
+			}
+
+			/*      muxer is still neutral                        */
+
+			RES_EVENT((OTG_INT_IDC | OTG_INT_TMX), event_code);
+
+			if (IS_FLAG_RES(otg, OTG_GADGET_READY)) {
+				if (IS_BIT_RES(OTG_STS_ID, uoc_status)) {
+
+					/* ID pin connected: A-device (host)  */
+
+					if (OTG_STATE_NO_B_DEVICE_A !=
+							otg->transceiver.state)
+						CHANGE_STATE(otg,
+							OTG_STATE_NO_B_DEVICE_A,
+							pEvt_mask);
+				} else if (IS_BIT_SET(OTG_STS_ID, uoc_status)) {
+
+					/* ID pin not connected:
+					 * disable(neutral)*/
+
+					if (OTG_STATE_NO_B_DEVICE_B !=
+							otg->transceiver.state)
+						CHANGE_STATE(otg,
+							OTG_STATE_NO_B_DEVICE_B,
+							pEvt_mask);
+				}
+			} else if ((OTG_STATE_NO_B_DEVICE_A ==
+						otg->transceiver.state) ||
+					(OTG_STATE_NO_B_DEVICE_B ==
+					 otg->transceiver.state)) {
+
+				/* Exit "not ready" state                     */
+				/* ----------------------                     */
+
+				RES_EVENT(OTG_GADGET_READY, event_code);
+				CHANGE_STATE(otg, OTG_STATE_UNDEFINED,
+						pEvt_mask);
+			}
+
+			/* ================================================== */
+
+			else {
+
+				/* ID pin is not connected: B-device
+				 * (peripheral)*/
+
+				CHANGE_STATE(otg, OTG_STATE_B_IDLE, pEvt_mask);
+			}
+			break;
+
+		case OTG_STATE_B_IDLE:
+			/* B_IDLE: init state for B-devices                  */
+			/*         monitor VBus, no connection, no activity  */
+
+			CHECK_STATE(otg, OTG_STATE_B_IDLE, pEvt_mask);
+
+			if (IS_BIT_SET(OTG_STS_SESSVLD, uoc_status)) {
+				/* Session valid => B_PERIPHERAL             */
+
+				RES_EVENT(OTG_INT_SVC, event_code);
+				CHANGE_STATE(otg, OTG_STATE_B_PERIPHERAL,
+						pEvt_mask);
+				if (otg_gadget_extension.notify) {
+					otg_gadget_extension.notify(
+							OTG_GADGET_EVT_SVALID);
+				}
+			}
+			break;
+
+		case OTG_STATE_B_PERIPHERAL:
+			/* B_PERIPHERAL: connected to A-host, responding     */
+			/*               VBus driven by A, remote activity   */
+
+			CHECK_STATE(otg, OTG_STATE_B_PERIPHERAL, pEvt_mask);
+
+			if (IS_BIT_RES(OTG_STS_SESSVLD, uoc_status)) {
+				/* ID pin changed | ~Session valid => B_IDLE */
+
+				RES_EVENT((OTG_INT_IDC | OTG_INT_SVC),
+						event_code);
+				CHANGE_STATE(otg, OTG_STATE_B_IDLE, pEvt_mask);
+				if (otg_gadget_extension.notify) {
+					otg_gadget_extension.notify(
+							OTG_GADGET_EVT_SVDROP);
+				}
+			}
+			break;
+
+		default:
+			/* something went wrong */
+			BUG();
+			break;
+	}
+	} while ((otg->transceiver.state ^ otg->transceiver.prv_state) &
+			(OTG_STATE_MASK));
+
+
+	DBG("OTG-state change done\n");
+
+	return event_code;
+}
+
+/**
+ * \brief
+ * OTG state change request
+ *
+ * \param  dev    OTG device info
+ * \param  params
+ *
+ * \return void
+ */
+static inline void otg_req_state_chg(struct otg *otg, u32 params)
+{
+	u32 temp, tmp2;
+	unsigned long flags;
+
+	local_irq_save(flags);
+
+	/* disable global OTG interrupt, clear int status:                   */
+	temp = ~((u32) OTG_INT_GLOBAL) & readl(&otg->regs->inten);
+	writel(temp, &otg->regs->inten);
+	tmp2 = readl(&otg->regs->intr);
+	writel(tmp2, &otg->regs->intr);
+	temp &= tmp2;
+
+	/* update OTG state:                                                 */
+	otg_change_state(otg, (params | temp), &temp);
+
+	/* enable global OTG interrupt:                                      */
+	state_mask = ~temp & OTG_INT_ADDS;
+	writel((OTG_INT_ADDS | temp | OTG_INT_GLOBAL), &otg->regs->inten);
+	local_irq_restore(flags);
+}
+
+/**
+ * \brief
+ * OTG set transceiver:
+ *
+ * \param  pointer to transceiver struct
+ *
+ * \return void
+ */
+int otg_set_transceiver(struct otg_transceiver *transceiver)
+{
+	struct otg *otg = the_controller;
+
+	if (unlikely(transceiver != otg_to_transceiver(otg))) {
+		ERR("USB OTG: unknown transceiver\n");
+		return -EINVAL;
+	} else
+		return 0;
+}
+
+/**
+ * \brief
+ * OTG get transceiver: provide info to others
+ *
+ * \param  void
+ *
+ * \return pointer to transceiver struct
+ */
+struct otg_transceiver *otg_get_transceiver(void)
+{
+	return otg_to_transceiver(the_controller);
+}
+
+/**
+ * \brief
+ * Bind/unbind the OTG controller to/from usb gadget
+ *
+ * \param  transceiver  this transceiver
+ * \param  gadget       usb gadget info
+ *
+ * \return error code
+ */
+static int au1200otg_set_peripheral(struct otg_transceiver *transceiver,
+		struct usb_gadget *gadget)
+{
+	struct otg *otg = the_controller;
+	int flag = 0;
+
+	if (unlikely(transceiver != otg_to_transceiver(otg))) {
+		ERR("USB OTG: unknown transceiver\n");
+		return -EINVAL;
+	}
+	if (gadget) {
+		if (transceiver->gadget) {
+			ERR("USB gadget: OTG driver already registered\n");
+			return -EBUSY;
+		}
+		DBG("bind OTG driver to USB gadget\n");
+		transceiver->gadget = gadget;
+		SET_FLAG(otg, OTG_GADGET_READY | OTG_B_BUS_REQ);
+
+		/* Now checking consistence ...                              */
+		/* Depending on the driver loading sequence is possible      */
+		/* that the "Load state defaults" function was already       */
+		/*  called so the state could be inconsistent.               */
+		if (transceiver->host && !transceiver->host->is_b_host)
+			flag |= 1;
+		transceiver->gadget->is_a_peripheral = flag;
+
+		if (IS_FLAG_SET(otg, OTG_FLAGS_ACTIV))
+			otg_req_state_chg(otg, OTG_GADGET_READY);
+
+		if (IS_BIT_SET(OTG_STS_SESSVLD, readl(&otg->regs->sts)) &&
+				(otg->transceiver.state & OTG_STATE_MASK)
+				== OTG_STATE_B_PERIPHERAL) {
+			VDBG("calling gadget: connect\n");
+			otg_gadget_extension.notify(OTG_GADGET_EVT_SVALID);
+		}
+		return 0;
+	} else {
+		DBG("unbind OTG driver from USB gadget\n");
+		RES_FLAG(otg, OTG_GADGET_READY | OTG_B_BUS_REQ);
+		if (IS_FLAG_SET(otg, OTG_FLAGS_ACTIV))
+			otg_req_state_chg(otg, OTG_GADGET_READY);
+
+		transceiver->gadget = NULL;
+		return 0;
+	}
+}
+
+/**
+ * \brief
+ * OTG application query
+ *
+ * \param  index   select status info data
+ *
+ * \return status
+ */
+static u32 otg_app_query(int index)
+{
+	struct otg *otg = the_controller;
+	u32  temp = 0;
+
+	if (index == 0) {
+		temp = otg->transceiver.params |
+			readl(&otg->regs->sts);
+
+		if (((readl(&otg->regs->ctl) & OTG_CTL_MUX_MASK) ==
+					OTG_CTL_ENABLE_UDC) &&
+				((temp & OTG_STS_PSUS) ||
+				 (~temp & OTG_STS_VBUSVLD)))
+			temp |= OTG_FLAGS_UDC_SUSP;
+	} else if (index == 1)
+		temp = otg->transceiver.state;
+
+	return temp;
+}
+
+/**
+ * \brief
+ * OTG ISR calling the main state machine
+ *
+ * \param  irq    IRQ number
+ * \param  _dev
+ * \param  r
+ *
+ * \return IRQ_HANDLED(system code)
+ */
+static irqreturn_t otg_isr(int irq, void *dev)
+{
+	struct otg *otg = (struct otg *) dev;
+	u32         interrupts, int_mask, temp;
+
+	int_mask = readl(&otg->regs->inten);
+	if ((OTG_INT_GLOBAL & int_mask) &&
+			(int_mask &= ~((u32) OTG_INT_GLOBAL)) &&
+			(interrupts = int_mask &
+			 (temp = readl(&otg->regs->intr)))) {
+
+		writel(int_mask, &otg->regs->inten);
+		/* clear interrupt status */
+		writel(temp, &otg->regs->intr);
+		/* filter out additional WA interrupts, they're done         */
+		/*       don't want to see them in the state machine         */
+
+		if (interrupts & ~state_mask) {
+
+			/* events pending for the state machine              */
+
+			otg_change_state(otg, (interrupts & ~state_mask),
+					&int_mask);
+		}
+
+		/* enable interrupts and keep information about WA ints:     */
+
+		state_mask = OTG_INT_ADDS & ~int_mask;
+		writel((OTG_INT_ADDS | int_mask | OTG_INT_GLOBAL),
+				&otg->regs->inten);
+	}
+	return IRQ_HANDLED;
+}
+
+/**
+ * \brief
+ * OTG probe: init hardware, register the driver
+ *
+ * \param  otg   otg controller info
+ *
+ * \return  success
+ */
+static inline int __init otg_probe(struct otg *otg)
+{
+	int         retval;
+	u32         temp;
+	int         i;
+
+	/* initialize the OTG controller */
+
+	VDBG("OTG init ...\n");
+
+#ifdef VERBOSE
+	/* print regs */
+	print_regs(otg);
+#endif
+	/* Make sure we'll remember the initial state                        */
+	init_state = readl(&otg->regs->ctl);
+	VDBG("  OTG init state was %08x\n", init_state);
+
+	/* turn on the OTG controller                                        */
+	writel((init_state | OTG_CTL_PADEN), &otg->regs->ctl);
+
+	/* initialize flags                                                  */
+	otg->transceiver.params = 0;
+
+	/* make sure all interrupts are disabled                             */
+	writel(OTG_INT_DISALL, &otg->regs->inten);
+	writel(OTG_INT_ENALL, &otg->regs->intr);
+
+	/* Set multiplexer to neutral, get power control, drop VBus          */
+
+	if (((init_state & OTG_CTL_MUX_MASK) == OTG_CTL_ENABLE_UHC) &&
+			((((init_state & OTG_CTL_PPO) &&
+			  (init_state & OTG_CTL_PPWR))) ||
+			 ((~init_state & OTG_CTL_PPO) &&
+			  (readl(&otg->regs->sts) & OTG_STS_SESSVLD)))) {
+
+		/* VBus still powered try to discharge VBus and set timer    */
+
+		DBG("Setting init state, trying to discharge VBus ...\n");
+
+		for (i = 0; i < 4; i++) {
+			writel(TIMER_PERIOD, &otg->regs->tmr);
+			writel((OTG_CTL_PADEN | OTG_CTL_IDSNSEN |
+						OTG_CTL_PPO | OTG_CTL_DISCHRG |
+						OTG_CTL_TMR_UNCOND),
+						&otg->regs->ctl);
+			while (!(readl(&otg->regs->sts) & OTG_STS_TMH))
+				udelay(1);
+		}
+		writel((OTG_CTL_PADEN | OTG_CTL_IDSNSEN | OTG_CTL_PPO),
+				&otg->regs->ctl);
+		writel(OTG_INT_ENALL, &otg->regs->intr);
+#ifdef DEBUG
+		if (readl(&otg->regs->sts) & OTG_STS_SESSVLD)
+			DBG("  VBus still high, external host connected\n");
+		else
+			DBG("  VBus discharged\n");
+#endif
+	} else {
+		DBG("Setting init state\n");
+
+		writel((OTG_CTL_PADEN | OTG_CTL_IDSNSEN | OTG_CTL_PPO),
+				&otg->regs->ctl);
+	}
+
+	VDBG("OTG init done\n");
+
+	/* registering to the device driver */
+	if (usb_gadget_register_otg(otg_get_transceiver)) {
+		ERR("gadget driver registration failed\n");
+		retval = -ENODEV;
+		goto err1;
+	}
+
+	/* finally activate OTG functionality */
+	/* Enable timer interrupt, start timer, set state                    */
+
+	SET_OTG_TIMER(otg, IDSNS_WAIT);
+	CHANGE_STATE(otg, OTG_STATE_UNDEFINED, &temp);
+	CHECK_STATE(otg, OTG_STATE_UNDEFINED, &temp);
+
+	/* clear all interrupts before enable */
+	writel(readl(&otg->regs->intr), &otg->regs->intr);
+
+	state_mask = ~temp & OTG_INT_ADDS;
+	writel((OTG_INT_ADDS | temp | OTG_INT_GLOBAL), &otg->regs->inten);
+
+	DBG("OTG-HW initialized, now checking ID ...\n");
+
+	return 0;
+
+	usb_gadget_unregister_otg();
+err1:
+	return retval;
+}
+
+/**
+ * \brief
+ * OTG remove: deregister the driver, clean-up hardware
+ *
+ * \param  otg   otg controller info
+ *
+ * \return void
+ */
+static inline void __exit otg_remove(struct otg *otg)
+{
+	int muxer;
+
+	/* unregistering from the usb gadget */
+	usb_gadget_unregister_otg();
+
+	/* clean up the OTG controller */
+
+	/* Disable all interrupts                                            */
+	writel(OTG_INT_DISALL, &otg->regs->inten);
+	writel(OTG_INT_ENALL, &otg->regs->intr);
+
+	/* reset state, terminate all connections                            */
+	CHANGE_STATE(otg, OTG_STATE_UNDEFINED, &state_mask);
+	CHECK_STATE(otg, OTG_STATE_UNDEFINED, &state_mask);
+	otg->transceiver.params = 0;
+
+	muxer = init_state & (OTG_CTL_ENABLE_UHC | OTG_CTL_ENABLE_UDC);
+
+
+	/* Don't assign the port to the device controller                    */
+
+	if (!(muxer ^ OTG_CTL_ENABLE_UDC)) {
+
+		init_state &= ~((u32)(OTG_CTL_MUX_MASK | OTG_CTL_PUEN));
+		muxer = OTG_CTL_DISABLE_ALL;
+	}
+	VDBG("OTG writing back corrected init state: %08x\n", init_state);
+
+	/* Now, that's the moment to remember                                */
+	/* Set dev muxer and pull up bits, turn off the OTG controller       */
+
+	/* Turn off VBus                                                     */
+	writel(init_state, &otg->regs->ctl);
+
+	if (!(muxer ^ OTG_CTL_ENABLE_UHC))
+		INFO("disabling OTG-HW, port is assigned to host\n");
+	else if (!(muxer ^ OTG_CTL_ENABLE_UDC))
+		INFO("disabling OTG-HW, port is assigned to device\n");
+	else
+		INFO("disabling OTG-HW, port is not assigned\n");
+
+	VDBG("OTG exit: OTG-HW disabled\n");
+
+	if (!muxer)
+		INFO("OTG HW disabled, port is not assigned\n");
+}
+
+/**
+ * \brief
+ * OTG dev probe: enable, init controller hardware
+ *
+ * \param  dev   platform device info
+ *
+ * \return success
+ */
+static int __init otg_drv_probe(struct device *dev)
+{
+	struct platform_device *pdev = to_platform_device(dev);
+	struct otg *otg;
+	u32         resource, len, irq;
+	void       *base;
+	int         retval;
+	char        buf[8] = {0, 0, 0, 0, 0, 0, 0, 0}, *bufp;
+
+	/* alloc, and start init */
+	otg = kmalloc(sizeof(struct otg), GFP_KERNEL);
+	if (!otg) {
+		ERR("couldn't allocate memory for OTG driver\n");
+		retval = -ENOMEM;
+		goto err1;
+	}
+	DBG("kmalloc: OTG driver: %p\n", otg);
+
+	/* hold global device pointer */
+	the_controller = otg;
+
+	memset(otg, 0, sizeof(struct otg));
+	spin_lock_init(&otg->lock);
+
+	if (pdev->resource[0].flags != IORESOURCE_MEM) {
+		ERR("resource is not IORESOURCE_MEM\n");
+		retval = -ENOMEM;
+		goto err2;
+	}
+	resource = pdev->resource[0].start;
+	len = pdev->resource[0].end + 1 - pdev->resource[0].start;
+	if (pdev->resource[1].flags != IORESOURCE_IRQ) {
+		ERR("resource is not IORESOURCE_IRQ\n");
+		retval = -ENOMEM;
+		goto err2;
+	}
+	irq = pdev->resource[1].start;
+
+	otg->pdev = pdev;
+
+	au_writel((au_readl(USB_MSR_BASE + USB_MSR_MCFG) |
+				(1 << USBMSRMCFG_GMEMEN)),
+				(USB_MSR_BASE + USB_MSR_MCFG));
+	au_readl(USB_MSR_BASE + USB_MSR_MCFG);
+	au_sync();
+
+	otg->enabled = 1;
+
+	if (!request_mem_region(resource, len, driver_name)) {
+		ERR("controller already in use\n");
+		retval = -EBUSY;
+		goto err3;
+	}
+	otg->region = 1;
+
+	base = ioremap_nocache(resource, len);
+	if (!base) {
+		ERR("couldn't map memory\n");
+		retval = -EFAULT;
+		goto err4;
+	}
+	otg->regs = (struct otg_regs *) base;
+	bufp = buf;
+
+	otg->chiprev = (u16) read_c0_prid() & 0xff;
+
+	/* OTG transceiver info */
+	otg->transceiver.dev = dev;
+	otg_init_transceiver(otg_to_transceiver(otg));
+
+	/* make sure all interrupts are disabled */
+	writel(OTG_INT_DISALL, &otg->regs->inten);
+	writel(OTG_INT_ENALL, &otg->regs->intr);
+	readl(&otg->regs->inten);
+
+	/* irq setup after old hardware is cleaned up */
+	if (!irq) {
+		ERR("No IRQ. Check system setup!\n");
+		retval = -ENODEV;
+		goto err5;
+	}
+	snprintf(buf, sizeof buf, "%d", irq);
+	bufp = buf;
+	if (request_irq(irq, otg_isr, IRQF_SHARED,
+				driver_name, otg) != 0) {
+		ERR("request interrupt %s failed\n", bufp);
+		retval = -EBUSY;
+		goto err5;
+	}
+	otg->got_irq = 1;
+
+	/* done */
+	INFO("%s\n", driver_desc);
+	INFO("irq %s, mem %08x, chip rev %02x (Au1200 %s)\n",
+			bufp, resource, otg->chiprev,
+			(otg->chiprev ? "AC" : "AB"));
+
+	retval = otg_probe(otg);
+	if (retval == 0) {
+		dev_set_drvdata(dev, otg);
+		return 0;
+	}
+
+	otg->got_irq = 0;
+	free_irq(irq, otg);
+err5:
+
+	otg->regs = NULL;
+	iounmap(base);
+err4:
+	otg->region = 0;
+	release_mem_region(resource, len);
+err3:
+	otg->enabled = 0;
+	au_writel((au_readl(USB_MSR_BASE + USB_MSR_MCFG) &
+				~((u32)(1 << USBMSRMCFG_GMEMEN))),
+			(USB_MSR_BASE + USB_MSR_MCFG));
+	au_readl(USB_MSR_BASE + USB_MSR_MCFG);
+	/* au_sync(); */
+	udelay(1000);
+err2:
+	otg->pdev = NULL;
+	the_controller = NULL;
+	DBG("kfree: OTG driver: %p\n", otg);
+	kfree(otg);
+err1:
+	otg = NULL;
+
+	return retval;
+}
+
+/**
+ * \brief
+ * OTG dev remove: clean-up, disable controller hardware
+ *
+ * \param  dev   platform device info
+ *
+ * \return void
+ */
+static int __exit otg_drv_remove(struct device *dev)
+{
+	struct platform_device *pdev = to_platform_device(dev);
+	struct otg *otg = dev_get_drvdata(dev);
+
+	otg_remove(otg);
+
+	otg->got_irq = 0;
+	free_irq(pdev->resource[1].start, otg);
+	iounmap(otg->regs);
+	otg->regs = NULL;
+	otg->region = 0;
+	release_mem_region(pdev->resource[0].start,
+			pdev->resource[0].end + 1
+			- pdev->resource[0].start);
+	otg->enabled = 0;
+
+	au_readl(USB_MSR_BASE + USB_MSR_MCFG);
+	au_sync();
+
+	otg->pdev = NULL;
+	the_controller = NULL;
+	DBG("kfree: OTG driver: %p\n", otg);
+	kfree(otg);
+	otg = NULL;
+	dev_set_drvdata(dev, NULL);
+	return 0;
+}
+
+
+/*****************************************************************************
+ *  More data
+ *****************************************************************************/
+
+/**
+ * \brief
+ * driver struct to be used for driver registration
+ *
+ */
+static struct device_driver otg_device_driver = {
+	.name =		"au1xxx-uoc",
+	.bus =		&platform_bus_type,
+	.probe =	otg_drv_probe,
+	.remove =	otg_drv_remove,
+	/* 	.suspend =	otg_drv_suspend, */
+	/* 	.resume =	otg_drv_resume, */
+};
+
+/* This comment closes the module definition from above. There can be multiple
+   definitions of this kind in a file. See the doxygen documentation for more
+   information. */
+/** \}*/
+
+MODULE_DESCRIPTION(DRIVER_DESC);
+MODULE_AUTHOR("Kevin Hickey");
+MODULE_LICENSE("GPL");
+
+static int __init init(void)
+{
+	return driver_register(&otg_device_driver);
+}
+static void __exit cleanup(void)
+{
+	driver_unregister(&otg_device_driver);
+}
+
+module_init(init);
+module_exit(cleanup);
diff --git a/drivers/usb/gadget/au1200_otg.h b/drivers/usb/gadget/au1200_otg.h
new file mode 100644
index 0000000..8c2e3a5
--- /dev/null
+++ b/drivers/usb/gadget/au1200_otg.h
@@ -0,0 +1,138 @@
+/*
+ * Declarations for the Au1200 On The Go port driver.
+ */
+
+/*
+ * Copyright (C) 2008 RMI Corporation (http://www.rmicorp.com)
+ * Author: Kevin Hickey (khickey@rmicorp.com)
+ *
+ * THIS SOFTWARE IS PROVIDED BY RMI Corporation 'AS IS' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO
+ * EVENT SHALL RMI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef AU1200_OTG_H
+#define AU1200_OTG_H
+
+/**********************************
+ * OTG sub-state definitions
+ ***********************************/
+
+#define OTG_STATE_MASK                  0x0F
+
+#define OTG_STATE_NO_B_DEVICE_A         (0x60 | OTG_STATE_UNDEFINED)
+#define OTG_STATE_NO_B_DEVICE_B         (0x40 | OTG_STATE_UNDEFINED)
+
+#define OTG_STATE_B_HOST_WT             (0x10 | OTG_STATE_B_HOST)
+#define OTG_STATE_B_PERIPHERAL_WT       (0x10 | OTG_STATE_B_PERIPHERAL)
+#define OTG_STATE_B_PERIPHERAL_DC       (0x20 | OTG_STATE_B_PERIPHERAL)
+#define OTG_STATE_B_SRP_WAIT_SE0        (0x10 | OTG_STATE_B_SRP_INIT)
+#define OTG_STATE_B_SRP_D_PULSE         (0x20 | OTG_STATE_B_SRP_INIT)
+#define OTG_STATE_B_SRP_V_PULSE         (0x30 | OTG_STATE_B_SRP_INIT)
+#define OTG_STATE_B_SRP_V_DCHRG         (0x40 | OTG_STATE_B_SRP_INIT)
+#define OTG_STATE_B_SRP_WAIT_VBUS       (0x50 | OTG_STATE_B_SRP_INIT)
+
+#define OTG_STATE_A_IDLE_WAIT_DP        (0x10 | OTG_STATE_A_IDLE)
+#define OTG_STATE_A_IDLE_WAIT_VP        (0x20 | OTG_STATE_A_IDLE)
+#define OTG_STATE_A_IDLE_WAIT_MP        (0x30 | OTG_STATE_A_IDLE)
+#define OTG_STATE_A_IDLE_WAIT_DV        (0x40 | OTG_STATE_A_IDLE)
+#define OTG_STATE_A_WAIT_BCON_VB        (0x10 | OTG_STATE_A_WAIT_BCON)
+#define OTG_STATE_A_WAIT_VFALL_DN       (0x10 | OTG_STATE_A_WAIT_VFALL)
+
+
+/**********************************
+ *  typical timer values
+ **********************************/
+
+#define OTG_TMR_WAIT_VFALL     10   /* (  ) A waits for VBus                 */
+#define OTG_TMR_A_WAIT_VRISE   100  /* (  ) A waits for VBus                 */
+#define OTG_TMR_A_WAIT_BCON    200  /* (  ) A waits for B-connect (1.. s)    */
+#define OTG_TMR_A_IDLE_BDIS    250  /* (ms) A waits for B-disc (200.. ms)    */
+#define OTG_TMR_B_WAIT_ADISCON 600  /* (us) B waits for A to disconnect <1ms */
+#define OTG_TMR_B_ACON_BRST    200  /* (us) B waits before starting reset    */
+#define OTG_TMR_B_ASE0_BRST    5    /* (ms) B waits for A-conn (3.125.. ms)  */
+#define OTG_TMR_B_AIDL_BDIS    50   /* (ms) B waits before dc (5..150ms)     */
+#define OTG_TMR_SRP_WAIT_SE0   2    /* (  ) B SRP idle wait                  */
+#define OTG_TMR_SRP_WAIT_DP    7    /* (ms) B SRP D_PULSE (5..10ms)          */
+#define OTG_TMR_SRP_WAIT_VP    80   /* (ms) B SRP V_PULSE (5..100ms)         */
+#define OTG_TMR_SRP_DCHRG_V    30   /* (  ) B SRP VBus discharge             */
+#define OTG_TMR_SRP_WAIT_VRS   5800 /* (ms) B SRP waits for VBus (5..6s)     */
+#define OTG_TMR_ASRP_WAIT_MP   4    /* (  ) A SRP min. pulse                 */
+#define OTG_TMR_ASRP_WAIT_DP   10   /* (ms) A SRP D_PULSE TO                 */
+#define OTG_TMR_ASRP_WAIT_VP   200  /* (ms) A SRP V_PULSE TO                 */
+#define OTG_TMR_ASRP_WAIT_DV   200  /* (  ) A SRP waits for V_PULSE          */
+#define OTG_TMR_A_BCON_VB      50   /* (  ) A waits for VBus after connect   */
+
+#define OTG_TMR_IDSNS_WAIT     10   /* (ms) ID sense wait                    */
+#define TIMER_PERIOD           1000 /* 10 ms, if longer than 10ms            */
+
+/**********************************
+ * OTG state parameters
+ **********************************/
+
+#define OTG_HOST_READY         (1<<20)   /* indicates a USB host driver is   */
+/* running                          */
+#define OTG_GADGET_READY       (1<<21)   /* indicates a USB gadget driver is */
+/* running                          */
+#define OTG_A_BUS_REQ          (1<<22)   /* used by appl-SW to request a     */
+/* VBus rise, auto-reset by driver  */
+#define OTG_A_BUS_DROP         (1<<23)   /* used by appl-SW to request a     */
+/* VBus drop, auto-reset by driver  */
+#define OTG_A_CLR_ERR          (1<<24)   /* used by appl-SW to request VBerr */
+/* clean-up, auto-reset by driver   */
+#define OTG_AB_HNP_REQ         (1<<25)   /* used by appl-SW to initiate      */
+/* HNP, auto-reset by driver        */
+#define OTG_B_BUS_REQ          (1<<26)   /* used by appl-SW to request       */
+/* B-device functionality, ...      */
+#define OTG_B_BUS_DIS          (1<<27)   /* used by appl-SW to request       */
+/* disable B-device functionality   */
+#define OTG_B_aSSN_REQ         (1<<28)   /* used by appl-SW to initiate SRP, */
+/* auto-reset by the driver         */
+#define OTG_B_SRP_ERROR        (1<<29)   /* indicates invalid HW conditions  */
+/* during SRP, reset by writing "1" */
+#define OTG_A_VBUS_FAILED      (1<<30)   /* indicates a VBus error, reset by */
+/* writing "1", when setting        */
+/* CLR_ERR or when leaving A-states */
+#define OTG_UDC_RWK_REQ        (1<<31)   /* call UDC function to force a     */
+/* remote wake-up                   */
+
+#define SW_REQUEST_MASK        (OTG_A_BUS_REQ | OTG_A_BUS_DROP | \
+		OTG_A_CLR_ERR | OTG_B_aSSN_REQ | \
+		OTG_B_BUS_REQ | OTG_B_BUS_DIS | \
+		OTG_UDC_RWK_REQ)
+
+/*********************************************************************/
+
+/*
+ * gadget events for notify function
+ */
+#define OTG_GADGET_EVT_SVDROP  (1<<0)    /* Session valid drop       */
+#define OTG_GADGET_EVT_SVALID  (1<<1)    /* Session valid            */
+#define OTG_GADGET_REQ_WAKE    (1<<2)    /* Request remote wake-up   */
+#define OTG_FLAGS_UDC_SUSP     (1<<17)   /* gadget phy suspended     */
+
+/*****************************************************************************
+ *  Data
+ *****************************************************************************/
+struct usb_otg_gadget_extension {
+	int (*request) (u32);	/* function call for state change requests */
+	u32 (*query) (int);	/* function call to query state            */
+	void (*notify) (u32);   /* filled in by gadget for notification    */
+};
+
+#endif /* AU1200_OTG_H */
diff --git a/drivers/usb/gadget/au1200_udc.c b/drivers/usb/gadget/au1200_udc.c
new file mode 100644
index 0000000..5289181
--- /dev/null
+++ b/drivers/usb/gadget/au1200_udc.c
@@ -0,0 +1,2862 @@
+/*
+ * RMI Au1200 UDC high/full speed USB device controller.
+ */
+
+/*
+ * Copyright (C) 2008 RMI Corporation (http://www.rmicorp.com)
+ * Author: Kevin Hickey (khickey@rmicorp.com)
+ *
+ * Adapted from the AMD5536 UDC module.
+ *
+ * THIS SOFTWARE IS PROVIDED BY RMI Corporation 'AS IS' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO
+ * EVENT SHALL RMI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+/*****************************************************************************
+ * Defines
+ *****************************************************************************/
+
+/* debug control */
+/* #define UDC_DEBUG */
+/* #define UDC_VERBOSE */
+/* #define UDC_REGISTER_DUMP */
+
+/* Driver strings */
+#define UDC_MOD_DESCRIPTION         "RMI Au1200 UDC - USB Device Controller"
+
+/*****************************************************************************
+ *  Includes
+ *****************************************************************************/
+/* system */
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/version.h>
+#include <linux/delay.h>
+#include <linux/ioport.h>
+#include <linux/sched.h>
+#include <linux/slab.h>
+#include <linux/smp_lock.h>
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/timer.h>
+#include <linux/list.h>
+#include <linux/interrupt.h>
+#include <linux/ioctl.h>
+#include <linux/fs.h>
+#include <linux/dma-mapping.h>
+#include <linux/dmapool.h>
+#include <linux/moduleparam.h>
+#include <linux/device.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+
+#include <asm/byteorder.h>
+#include <asm/system.h>
+#include <asm/unaligned.h>
+
+/* MIPS config */
+#include <asm/mach-au1x00/au1xxx.h>
+
+/* gadget stack */
+#include <linux/usb/ch9.h>
+#include <linux/usb/gadget.h>
+#include <linux/usb/otg.h>
+
+/* udc specific */
+#include "au1200_udc.h"
+
+/*****************************************************************************
+ *  Static Function Declarations
+ *****************************************************************************/
+static void udc_tasklet_disconnect(unsigned long);
+static void empty_req_queue(struct udc_ep *);
+static int udc_probe(struct udc *dev);
+static void udc_basic_init(struct udc *dev);
+static void udc_setup_endpoints(struct udc *dev);
+static void udc_soft_reset(struct udc *dev);
+static void udc_free_request(struct usb_ep *usbep, struct usb_request *usbreq);
+static struct udc_data_dma *udc_get_last_dma_desc(struct udc_request *req);
+static int udc_free_dma_chain(struct udc *dev, struct udc_request *req);
+static inline int startup_registers(struct udc *dev);
+static int udc_remote_wakeup(struct udc *dev);
+static int udc_suspend(struct udc *dev);
+static int udc_resume(struct udc *dev);
+static void udc_clear_NAK(struct udc_ep *ep);
+
+static int execute_bulk_request_with_dma(struct usb_ep *usbep,
+					 struct usb_request *usbreq, gfp_t gfp);
+
+static void udc_tasklet_execute_request(unsigned long);
+
+/*****************************************************************************
+ *  Data
+ *****************************************************************************/
+/* description */
+static const char mod_desc[] = UDC_MOD_DESCRIPTION;
+static const char name[] = DRIVER_NAME_FOR_PRINT;
+
+/* structure to hold endpoint function pointers */
+static struct usb_ep_ops udc_ep_ops;
+
+/* received setup data */
+static union udc_setup_data setup_data;
+
+/* pointer to device object */
+static struct udc       *udc;
+
+/* irq spin lock for soft reset */
+spinlock_t udc_irq_spinlock;
+/* stall spin lock */
+spinlock_t udc_stall_spinlock;
+
+/* this is used for dma chaining */
+static int udc_gfp_flags;
+
+/* count soft resets after suspend to avoid loop */
+static int soft_reset_occured;
+static int soft_reset_after_usbreset_occured;
+
+#ifdef UDC_USE_TIMER
+/* timer */
+static struct timer_list udc_timer;
+static int stop_timer;
+int set_rde = -1;
+DECLARE_COMPLETION(on_exit);
+static struct timer_list udc_pollstall_timer;
+static int stop_pollstall_timer;
+DECLARE_COMPLETION(on_pollstall_exit);
+#endif
+
+/* tasklet for usb disconnect */
+DECLARE_TASKLET(disconnect_tasklet, udc_tasklet_disconnect,
+		(unsigned long)&udc);
+
+/* otg registering count */
+static u32 otg_reg_count;
+
+/* gadget registering count */
+static u32 gadget_bind_count;
+
+/* endpoint names used for print */
+static const char ep0_string[] = "ep0in";
+static const char *ep_string[] = {
+	ep0_string,
+	"ep1in-int", "ep2in-bulk", "ep3in-bulk", "ep4in-bulk", "ep5in-bulk",
+	"ep6in-bulk", "ep7in-bulk", "ep8in-bulk", "ep9in-bulk", "ep10in-bulk",
+	"ep11in-bulk", "ep12in-bulk", "ep13in-bulk", "ep14in-bulk",
+	"ep15in-bulk", "ep0out", "ep1out-bulk", "ep2out-bulk", "ep3out-bulk",
+	"ep4out-bulk", "ep5out-bulk", "ep6out-bulk", "ep7out-bulk",
+	"ep8out-bulk", "ep9out-bulk", "ep10out-bulk", "ep11out-bulk",
+	"ep12out-bulk", "ep13out-bulk", "ep14out-bulk", "ep15out-bulk"
+};
+
+
+#ifdef UDC_DEBUG
+/* data for debuging only */
+static unsigned long no_pref_req;
+static unsigned long no_req;
+static u32 same_cfg;
+static u32 num_enums;
+#endif
+
+/****** following flags can be set by module parameters */
+/* DMA usage flag */
+static int use_dma = 1;
+/* packet per buffer dma */
+static int use_dma_ppb = 1;
+/* with per descr. update */
+static int use_dma_ppb_du;
+/* buffer fill mode */
+static int use_dma_bufferfill_mode;
+/* full speed only mode */
+static int use_fullspeed;
+/* tx buffer size for high speed */
+static unsigned long hs_tx_buf = UDC_EPIN_BUFF_SIZE;
+
+/* module parameters */
+module_param(use_dma, bool, S_IRUGO);
+MODULE_PARM_DESC(use_dma, "true for DMA");
+module_param(use_dma_ppb, bool, S_IRUGO);
+MODULE_PARM_DESC(use_dma_ppb, "true for DMA in packet per buffer mode");
+module_param(use_dma_ppb_du, bool, S_IRUGO);
+MODULE_PARM_DESC(use_dma_ppb_du,
+	"true for DMA in packet per buffer mode with descriptor update");
+module_param(use_fullspeed, bool, S_IRUGO);
+MODULE_PARM_DESC(use_fullspeed, "true for fullspeed only");
+module_param(hs_tx_buf, long, S_IRUGO);
+MODULE_PARM_DESC(hs_tx_buf,
+		 "high speed tx buffer size for data endpoints in dwords");
+
+MODULE_DESCRIPTION(UDC_MOD_DESCRIPTION);
+MODULE_AUTHOR("Kevin Hickey");
+MODULE_LICENSE("GPL");
+
+/*****************************************************************************
+ *  Function Definitions
+ *****************************************************************************/
+/* printing registers --------------------------------------------------------*/
+/**
+ * Prints UDC device registers and endpoint irq registers
+ *
+ * \param dev pointer to device struct
+ */
+static void print_regs(struct udc *dev)
+{
+	DBG("------- Device registers -------\n");
+	DBG("dev config     = %08lx\n", (unsigned long) dev->regs->cfg);
+	DBG("dev control    = %08lx\n", (unsigned long) dev->regs->ctl);
+	DBG("dev status     = %08lx\n", (unsigned long) dev->regs->sts);
+	DBG("\n");
+	DBG("dev int's      = %08lx\n", (unsigned long) dev->regs->irqsts);
+	DBG("dev intmask    = %08lx\n", (unsigned long) dev->regs->irqmsk);
+	DBG("\n");
+	DBG("dev ep int's   = %08lx\n", (unsigned long) dev->regs->ep_irqsts);
+	DBG("dev ep intmask = %08lx\n", (unsigned long) dev->regs->ep_irqmsk);
+	DBG("\n");
+	DBG("USE DMA        = %d\n", use_dma);
+	if (use_dma) {
+		DBG("DMA mode       = ");
+		if (use_dma_ppb && !use_dma_ppb_du)
+			DBG("PPBNDU (packet per buffer w/o desc. update)\n");
+		else if (use_dma_ppb_du && use_dma_ppb_du)
+			DBG("PPBDU (packet per buffer with desc. update)\n");
+		if (use_dma_bufferfill_mode)
+			DBG("BF (buffer fill mode)\n");
+	}
+
+	if (!use_dma)
+		INFO("FIFO mode\n");
+#ifdef UDC_USE_TIMER
+	INFO("RDE timer is used\n");
+#endif
+	DBG("-------------------------------------------------------\n");
+}
+
+#ifdef UDC_DEBUG
+/**
+ * Prints misc information, to be removed
+ *
+ * \param dev           pointer to device struct
+ */
+static void print_misc(struct udc *dev)
+{
+	print_regs(dev);
+
+	if (use_dma)
+		INFO("no_req=%ld no_pref_req=%ld\n", no_req, no_pref_req);
+}
+#endif
+
+/**
+ * Masks unused interrupts
+ *
+ * \param dev           pointer to device struct
+ * \return 0 if success
+ */
+static int udc_mask_unused_interrupts(struct udc *dev)
+{
+	u32 tmp;
+
+	/* mask all dev interrupts */
+	tmp =   UDC_BIT(UDC_DEVINT_ENUM) |
+		UDC_BIT(UDC_DEVINT_US) |
+		UDC_BIT(UDC_DEVINT_UR) |
+		UDC_BIT(UDC_DEVINT_ES) |
+		UDC_BIT(UDC_DEVINT_SI) |
+		UDC_BIT(UDC_DEVINT_SOF)|
+		UDC_BIT(UDC_DEVINT_SC);
+	iowrite32(tmp, &dev->regs->irqmsk);
+
+	/* mask all ep interrupts */
+	iowrite32(UDC_EPINT_MSK_DISABLE_ALL, &dev->regs->ep_irqmsk);
+
+	return 0;
+}
+
+/**
+ * Enables endpoint 0 interrupts
+ *
+ * \param dev           pointer to device struct
+ * \return 0 if success
+ */
+static int udc_enable_ep0_interrupts(struct udc *dev)
+{
+	u32 tmp;
+
+	tmp = ioread32(&dev->regs->ep_irqmsk);
+	tmp &= ~(UDC_BIT(UDC_EPINT_IN_EP0) | UDC_BIT(UDC_EPINT_OUT_EP0));
+
+	iowrite32(tmp, &dev->regs->ep_irqmsk);
+
+	return 0;
+}
+
+/**
+ * Calculates fifo start of endpoint based on preceeding endpoints
+ *
+ * \param ep           pointer to ep struct
+ * \return 0 if success
+ */
+static u32 *udc_calc_txfifo_addr(const struct udc *dev, unsigned ep_num)
+{
+	u32 tmp;
+	int i;
+	u32 *retval = dev->txfifo;
+
+	/* traverse ep's */
+	for (i = 0; i < ep_num; ++i) {
+		if (dev->ep[i].regs) {
+			/* read fifo size */
+			tmp = ioread32(&dev->ep[i].regs->bufin_framenum);
+			tmp = UDC_GETBITS(tmp, UDC_EPIN_BUFF_SIZE);
+			retval += tmp;
+		}
+	}
+	return retval;
+}
+
+/**
+ * Enables endpoint, is called by gadget driver
+ *
+ * \param usbep         pointer to ep struct
+ * \param desc          pointer to endpoint descriptor
+ * \return 0 if success
+ */
+static int udc_ep_enable(struct usb_ep *usbep,
+		const struct usb_endpoint_descriptor *desc)
+{
+	struct udc_ep           *ep;
+	struct udc              *dev;
+	u32                     tmp;
+	unsigned long           iflags;
+	u8 udc_csr_epix;
+
+	VDBG("udc_enable()\n");
+
+	ep = container_of(usbep, struct udc_ep, ep);
+	if (!usbep
+			|| usbep->name == ep0_string
+			|| !desc
+			|| desc->bDescriptorType != USB_DT_ENDPOINT) {
+		ERR("udc_enable: !usbep=%d !desc=%d ep->desc!=NULL=%d \
+				usbep->name==ep0_string=%d \
+				desc->bDescriptorType!=USB_DT_ENDPOINT=%d\n",
+				!usbep, !desc, ep->desc != NULL,
+				usbep->name == ep0_string,
+				desc->bDescriptorType != USB_DT_ENDPOINT);
+		return -EINVAL;
+	}
+
+	dev = ep->dev;
+
+	/* exit on suspend */
+	if (dev->sys_suspended)
+		return -ESHUTDOWN;
+
+	if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)
+		return -ESHUTDOWN;
+
+	spin_lock_irqsave(&dev->lock, iflags);
+	ep->desc = desc;
+
+	ep->halted = 0;
+
+	/* set traffic type */
+	tmp = ioread32(&ep->regs->ctl);
+	tmp = UDC_ADDBITS(tmp, desc->bmAttributes, UDC_EPCTL_ET);
+	iowrite32(tmp, &ep->regs->ctl);
+
+	/* set max packet size */
+	tmp = ioread32(&ep->regs->bufout_maxpkt);
+	tmp = UDC_ADDBITS(tmp, desc->wMaxPacketSize, UDC_EP_MAX_PKT_SIZE);
+	ep->ep.maxpacket = desc->wMaxPacketSize;
+	iowrite32(tmp, &ep->regs->bufout_maxpkt);
+
+	/* IN ep */
+	if (ep->in) {
+		/* ep ix in UDC CSR register space */
+		udc_csr_epix = ep->num;
+
+		/* set buffer size (tx fifo entries) */
+		tmp = ioread32(&ep->regs->bufin_framenum);
+		/* double buffering: fifo size = 2 x max packet size */
+		tmp = UDC_ADDBITS(
+				tmp,
+				desc->wMaxPacketSize * UDC_EPIN_BUFF_SIZE_MULT /
+				UDC_DWORD_BYTES,
+				UDC_EPIN_BUFF_SIZE);
+		iowrite32(tmp, &ep->regs->bufin_framenum);
+
+		/* calc. tx fifo base addr */
+		ep->txfifo = udc_calc_txfifo_addr(dev, ep->num);
+
+		/* flush fifo */
+		tmp = ioread32(&ep->regs->ctl);
+		tmp |= UDC_BIT(UDC_EPCTL_F);
+		iowrite32(tmp, &ep->regs->ctl);
+
+	} /* OUT ep */
+	else {
+		/* ep ix in UDC CSR register space */
+		udc_csr_epix = ep->num - UDC_CSR_EP_OUT_IX_OFS;
+
+		if (ep->num != UDC_EP0OUT_IX)
+			dev->data_ep_enabled = 1;
+	}
+
+	/***** UDC CSR reg ****************************/
+	/* set ep values  */
+	tmp = ioread32(&dev->csr->ne[udc_csr_epix]);
+	/* max packet */
+	tmp = UDC_ADDBITS(tmp, desc->wMaxPacketSize, UDC_CSR_NE_MAX_PKT);
+	/* ep number */
+	tmp = UDC_ADDBITS(tmp, desc->bEndpointAddress, UDC_CSR_NE_NUM);
+	/* ep direction */
+	tmp = UDC_ADDBITS(tmp, ep->in, UDC_CSR_NE_DIR);
+	/* ep type */
+	tmp = UDC_ADDBITS(tmp, desc->bmAttributes, UDC_CSR_NE_TYPE);
+	/* ep config */
+	tmp = UDC_ADDBITS(tmp, dev->cur_config, UDC_CSR_NE_CFG);
+	/* ep interface */
+	tmp = UDC_ADDBITS(tmp, dev->cur_intf, UDC_CSR_NE_INTF);
+	/* ep alt */
+	tmp = UDC_ADDBITS(tmp, dev->cur_alt, UDC_CSR_NE_ALT);
+	/* write reg */
+	iowrite32(tmp, &dev->csr->ne[udc_csr_epix]);
+
+	/* enable ep irq */
+	tmp = ioread32(&dev->regs->ep_irqmsk);
+	tmp &= UDC_UNMASK_BIT(ep->num);
+	iowrite32(tmp, &dev->regs->ep_irqmsk);
+
+	/* clear NAK by writing CNAK */
+	/* avoid BNA for OUT DMA,  dont clear NAK until DMA desc. written */
+	if (ep->in)
+		udc_clear_NAK(ep);
+
+	DBG("%s enabled\n", usbep->name);
+
+	spin_unlock_irqrestore(&dev->lock, iflags);
+	return 0;
+}
+
+/**
+ * Enables device interrupts for SET_INTF and SET_CONFIG
+ *
+ * \param dev           pointer to device struct
+ * \return 0 if success
+ */
+static int udc_enable_dev_setup_interrupts(struct udc *dev)
+{
+	u32 tmp;
+
+	/* read irq mask */
+	tmp = ioread32(&dev->regs->irqmsk);
+
+	/* enable SET_INTERFACE, SET_CONFIG and other needed irq's */
+	tmp &= UDC_UNMASK_BIT(UDC_DEVINT_SI)
+		& UDC_UNMASK_BIT(UDC_DEVINT_SC)
+		& UDC_UNMASK_BIT(UDC_DEVINT_UR)
+		& UDC_UNMASK_BIT(UDC_DEVINT_ENUM);
+	iowrite32(tmp, &dev->regs->irqmsk);
+
+	return 0;
+}
+
+/**
+ * Resets endpoint
+ *
+ * \param regs          pointer to device register struct
+ * \param ep            pointer to endpoint
+ */
+static void ep_init(struct udc_regs *regs, struct udc_ep *ep)
+{
+	u32             tmp;
+
+	VDBG("ep-%d reset\n", ep->num);
+	ep->desc = 0;
+	ep->ep.ops = &udc_ep_ops;
+	INIT_LIST_HEAD(&ep->queue);
+
+	ep->ep.maxpacket = (u16) ~0;
+	if (!(ep->dev->sys_suspended)) {
+		/* set NAK  */
+		tmp = ioread32(&ep->regs->ctl);
+		tmp |= UDC_BIT(UDC_EPCTL_SNAK);
+		iowrite32(tmp, &ep->regs->ctl);
+		ep->naking = 1;
+
+		/* disable interrupt */
+		tmp = ioread32(&regs->ep_irqmsk);
+		tmp |= UDC_BIT(ep->num);
+		iowrite32(tmp, &regs->ep_irqmsk);
+
+		if (ep->in) {
+			/* unset P and IN bit of potential former DMA */
+			tmp = ioread32(&ep->regs->ctl);
+			tmp &= UDC_UNMASK_BIT(UDC_EPCTL_P);
+			iowrite32(tmp, &ep->regs->ctl);
+
+			tmp = ioread32(&ep->regs->sts);
+			tmp |= UDC_BIT(UDC_EPSTS_IN);
+			iowrite32(tmp, &ep->regs->sts);
+
+			/* flush the fifo */
+			tmp = ioread32(&ep->regs->ctl);
+			tmp |= UDC_BIT(UDC_EPCTL_F);
+			iowrite32(tmp, &ep->regs->ctl);
+
+		}
+		/* reset desc pointer */
+		iowrite32(0, &ep->regs->desptr);
+	}
+
+
+}
+
+/**
+ * Disables endpoint, is called by gadget driver
+ *
+ * \param usbep            pointer to ep struct
+ * \return 0 if success
+ */
+static int udc_disable(struct usb_ep *usbep)
+{
+	struct udc_ep   *ep;
+	struct udc	*dev;
+	unsigned long	iflags;
+
+	if (!usbep)
+		return -EINVAL;
+
+	ep = container_of(usbep, struct udc_ep, ep);
+	dev = ep->dev;
+
+	if (usbep->name == ep0_string || !ep->desc)
+		return -EINVAL;
+
+	DBG("Disable %s\n", usbep->name);
+
+	spin_lock_irqsave(&dev->lock, iflags);
+	empty_req_queue(ep);
+	ep_init(dev->regs, ep);
+	spin_unlock_irqrestore(&dev->lock, iflags);
+
+	return 0;
+}
+
+/**
+ * Allocates request packet, called by gadget driver
+ */
+static struct usb_request *
+udc_alloc_request(struct usb_ep *usbep, gfp_t gfp)
+{
+	struct udc_request      *req;
+	struct udc_data_dma     *dma_desc;
+	struct udc_ep   	*ep;
+	struct udc		*dev;
+
+	static int		serial;
+
+	VDBG("udc_alloc_req()\n");
+	if (!usbep)
+		return 0;
+
+	ep = container_of(usbep, struct udc_ep, ep);
+	dev = ep->dev;
+	udc_gfp_flags = gfp;
+
+	req = kmalloc(sizeof(struct udc_request), gfp);
+	if (!req)
+		return 0;
+
+	memset(req, 0, sizeof *req);
+	req->req.dma = DMA_DONT_USE;
+	INIT_LIST_HEAD(&req->queue);
+	req->ready_for_p_bit = false;
+
+	req->serial_number = serial++;
+
+	/* KH TODO: Extract to function to be used by this
+	 * and prepare_dma_chain. */
+	gfp = GFP_ATOMIC | GFP_DMA;
+	/* ep0 in requests are allocated from data pool here */
+	dma_desc = dma_pool_alloc(dev->data_requests, gfp,
+			&req->td_phys);
+	if (!dma_desc) {
+		kfree(req);
+		return 0;
+	}
+
+	VDBG("udc_alloc_req: req = %lx dma_desc = %lx, \
+			req->td_phys = %lx\n",
+			(unsigned long)req, (unsigned long) dma_desc,
+			(unsigned long)req->td_phys);
+	/* prevent from using desc. - set HOST BUSY */
+	dma_desc->status = UDC_ADDBITS(dma_desc->status,
+			UDC_DMA_STP_STS_BS_HOST_BUSY,
+			UDC_DMA_STP_STS_BS);
+	dma_desc->bufptr = __constant_cpu_to_le32(DMA_DONT_USE);
+	dma_desc->next = req->td_phys;
+	req->td_data = dma_desc;
+	req->chain_len = 1;
+
+	return &req->req;
+}
+
+/**
+ * Frees request packet, called by gadget driver
+ */
+static void udc_free_request(struct usb_ep *usbep, struct usb_request *usbreq)
+{
+	struct udc_ep   	*ep;
+	struct udc_request      *req;
+
+	if (!usbep || !usbreq)
+		return;
+
+	ep = container_of(usbep, struct udc_ep, ep);
+	req = container_of(usbreq, struct udc_request, req);
+
+	WARN_ON(!list_empty(&req->queue));
+	if (req->td_data) {
+		if (req->chain_len > 1)
+			udc_free_dma_chain(ep->dev, req);
+
+		/* Free the first entry, not done by udc_free_dma_chain */
+		dma_pool_free(ep->dev->data_requests, req->td_data,
+			      req->td_phys);
+	}
+	kfree(req);
+}
+
+/**
+ * Completes request packet
+ */
+static void
+complete_req(struct udc_ep *ep, struct udc_request *req, int sts)
+{
+	unsigned                halted;
+
+	/* unmap DMA */
+	if (req->req.dma != DMA_DONT_USE) {
+		dma_unmap_single(0,
+				 req->req.dma,
+				 req->req.length,
+				 ep->in ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
+
+		req->req.dma = DMA_DONT_USE;
+	}
+
+	halted = ep->halted;
+	ep->halted = 1;
+
+	/* set new status if pending */
+	if (req->req.status == -EINPROGRESS)
+		req->req.status = sts;
+
+	list_del_init(&req->queue);
+
+	req->req.complete(&ep->ep, &req->req);
+
+	up(&ep->in_use);
+	ep->halted = halted;
+}
+
+/**
+ * Frees pci pool descriptors of a DMA chain
+ */
+static int udc_free_dma_chain(struct udc *dev, struct udc_request *req)
+{
+
+	int ret_val = 0;
+	struct udc_data_dma     *td;
+	struct udc_data_dma     *td_last = NULL;
+	unsigned int i;
+
+	/* Do not free first desc., will be done by free for request */
+	td_last = req->td_data;
+	td = phys_to_virt(td_last->next);
+
+	for (i = 1; i < req->chain_len; i++) {
+
+		dma_pool_free(dev->data_requests, td,
+				(dma_addr_t) td_last->next);
+		td_last = td;
+		td = phys_to_virt(td_last->next);
+	}
+
+	return ret_val;
+}
+
+/**
+ * Iterates to the end of a DMA chain and returns last descriptor
+ */
+static struct udc_data_dma *udc_get_last_dma_desc(struct udc_request *req)
+{
+	struct udc_data_dma     *td;
+
+	td = req->td_data;
+	while (td && !(td->status & UDC_BIT(UDC_DMA_IN_STS_L)))
+		td = phys_to_virt(td->next);
+
+	return td;
+
+}
+
+static inline void udc_set_rde(struct udc *dev)
+{
+	UDC_SET_BIT(UDC_DEVCTL_RDE, &dev->regs->ctl);
+}
+
+/*
+ * Print a single DMA descriptor.  Used by print_descriptor_chain.
+ */
+static void print_dma_descriptor(struct udc_data_dma *desc)
+{
+	INFO("DMA Descriptor:\n");
+	INFO("Address:0x%8.8x\n", (u32)desc);
+	INFO("Status: 0x%8.8x\n", desc->status);
+	INFO("Buffer: 0x%8.8x\n", desc->bufptr);
+	INFO("Next:   0x%8.8x\n", desc->next);
+}
+
+/*
+ * Walk and print a descriptor chain.  Useful for debugging and error output
+ */
+static void print_descriptor_chain(struct udc_ep *ep)
+{
+	struct udc_data_dma *desc = phys_to_virt(ep->regs->desptr);
+
+	INFO("DMA Descriptor Chain (%s: 0x%8.8X)\n", ep->ep.name,
+			ep->regs->desptr);
+	print_dma_descriptor(desc);
+	while (desc && !(desc->status & UDC_BIT(UDC_DMA_IN_STS_L)) &&
+		       (desc->next != ep->regs->desptr)) {
+		desc = (struct udc_data_dma *)(phys_to_virt(desc->next));
+		print_dma_descriptor(desc);
+	}
+
+}
+
+struct udc_data_dma *prepare_dma_chain(struct udc_ep *ep,
+		struct udc_request *req, gfp_t gfp)
+{
+	int i;
+	struct usb_ep *usbep = &ep->ep;
+	struct usb_request *usbreq = &req->req;
+	struct udc_data_dma *td = req->td_data;
+	struct udc_data_dma *next = NULL;
+	dma_addr_t dma_addr;
+
+	td->bufptr = usbreq->dma;
+	td->status = 0;
+	if (ep->in)
+		td->status = UDC_ADDBITS(td->status,
+				ep->ep.maxpacket,
+				UDC_DMA_IN_STS_TXBYTES);
+
+	for (i = usbep->maxpacket; i < usbreq->length; i += usbep->maxpacket) {
+		if (td->next == (u32)req->td_phys) {
+			next = dma_pool_alloc(ep->dev->data_requests,
+					gfp, &dma_addr);
+			if (next == NULL) {
+				ERR("%s allocation failed!\n", __func__);
+				return NULL;
+			}
+
+			++req->chain_len;
+			/* Last points to first */
+			next->next = (u32)req->td_phys;
+			td->next = dma_addr;
+		} else {
+			next = (struct udc_data_dma *)phys_to_virt(td->next);
+		}
+
+		next->bufptr = usbreq->dma + i;
+		next->status = 0;
+		if (ep->in)
+			next->status = UDC_ADDBITS(next->status,
+						   ep->ep.maxpacket,
+						   UDC_DMA_IN_STS_TXBYTES);
+		td = next;
+	}
+
+	return td;
+}
+
+static void udc_clear_NAK(struct udc_ep *ep)
+{
+	u32 tmp = ioread32(&ep->regs->ctl);
+	int i = 0;
+
+	while (tmp & UDC_BIT(UDC_EPCTL_NAK)) {
+		tmp |= UDC_BIT(UDC_EPCTL_CNAK);
+		iowrite32(tmp, &ep->regs->ctl);
+		au_sync();
+
+		udelay(100);
+		tmp = ioread32(&ep->regs->ctl);
+		++i;
+		if (i % 100 == 0)
+			INFO("Tried to CNAK %d times.\n", i);
+	}
+
+	ep->naking = 0;
+}
+
+static int execute_bulk_request_with_dma(struct usb_ep *usbep,
+					  struct usb_request *usbreq, gfp_t gfp)
+{
+	int			retval;
+	struct udc 		*dev;
+	struct udc_ep 		*ep;
+	struct udc_request	*req;
+	unsigned long 		iflags;
+	struct udc_data_dma	*td;
+
+	ep = container_of(usbep, struct udc_ep, ep);
+	req = container_of(usbreq, struct udc_request, req);
+	dev = ep->dev;
+	td = req->td_data;		/* For notational convenience */
+
+	/* We don't want the isr to start acting on this request while we're
+	 * setting it up.  */
+	spin_lock_irqsave(&dev->lock, iflags);
+
+	usbreq->actual = 0;
+	usbreq->status = -EINPROGRESS;
+
+	/* Map the buffer allocated for the request into DMA space.
+	 * Remember that the CPU should not access this memory until it is
+	 * unmapped.  */
+	if (usbreq->length > 0 && usbreq->dma == DMA_DONT_USE) {
+		usbreq->dma = dma_map_single(dev->pdev,
+					     usbreq->buf,
+					     usbreq->length,
+			ep->in ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
+	}
+
+	td = prepare_dma_chain(ep, req, gfp);
+	if (td == NULL) {
+		retval = -ENOMEM;
+		goto finish;
+	}
+
+	if (ep->in && usbreq->length % usbep->maxpacket != 0)
+		td->status = UDC_ADDBITS(td->status,
+					usbreq->length % usbep->maxpacket,
+					UDC_DMA_IN_STS_TXBYTES);
+
+	td->status |= UDC_BIT(UDC_DMA_OUT_STS_L);
+
+	/* Set the endpoint descriptor register to start the transfer */
+	iowrite32((u32)req->td_phys, &ep->regs->desptr);
+	au_sync();
+
+	udc_clear_NAK(ep);
+
+finish:
+	spin_unlock_irqrestore(&dev->lock, iflags);
+	return retval;
+}
+
+static void udc_tasklet_execute_request(unsigned long ep_as_ul)
+{
+	struct udc_ep *ep = (struct udc_ep *)ep_as_ul;
+	struct udc_request *req;
+
+	down(&ep->in_et);
+
+	if (!list_empty(&ep->queue) && !down_trylock(&ep->in_use)) {
+		req = list_entry(ep->queue.next, struct udc_request, queue);
+
+		execute_bulk_request_with_dma(&ep->ep, &req->req,
+				udc_gfp_flags);
+		if (ep->in)
+			UDC_UNSET_BIT(ep->num, &ep->dev->regs->ep_irqmsk);
+		else
+			udc_set_rde(ep->dev);
+
+		/* Harmless to do on out EPs and saves a branch */
+		req->ready_for_p_bit = true;
+	}
+
+	up(&ep->in_et);
+}
+
+/**
+ * Queues a request packet, called by gadget driver
+ */
+static int udc_queue(struct usb_ep *usbep, struct usb_request *usbreq,
+		gfp_t gfp)
+{
+	int retval = 0;
+	unsigned long           iflags = 0;
+	struct udc_ep   	*ep;
+	struct udc_request      *req;
+	struct udc              *dev;
+
+	/* check the inputs */
+
+	if (!usbep || !usbreq || !usbreq->complete || !usbreq->buf)
+		return -EINVAL;
+
+	req = container_of(usbreq, struct udc_request, req);
+	ep = container_of(usbep, struct udc_ep, ep);
+	dev = ep->dev;
+
+	if (!ep->desc && (ep->num != 0 && ep->num != UDC_EP0OUT_IX))
+		return -EINVAL;
+
+	/* exit on suspend */
+	if (dev->sys_suspended)
+		return -ESHUTDOWN;
+
+	if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)
+		return -ESHUTDOWN;
+
+	spin_lock_irqsave(&dev->lock, iflags);
+	if (ep->num != UDC_EP0OUT_IX && ep->num != UDC_EP0IN_IX) {
+		list_add_tail(&req->queue, &ep->queue);
+		tasklet_schedule(&ep->execute_tasklet);
+		goto finished;
+	} else {
+		if (usbreq->length > 0) {
+			list_add_tail(&req->queue, &ep->queue);
+			execute_bulk_request_with_dma(usbep, usbreq, gfp);
+			UDC_UNSET_BIT(ep->num, &dev->regs->ep_irqmsk);
+			goto finished;
+		} else {
+			/* IN zlp's are handled by hardware */
+			complete_req(ep, req, 0);
+			if (dev->set_cfg_not_acked) {
+				UDC_SET_BIT(UDC_DEVCTL_CSR_DONE,
+						&dev->regs->ctl);
+				dev->set_cfg_not_acked = 0;
+			}
+			goto finished;
+		}
+	}
+
+finished:
+	spin_unlock_irqrestore(&dev->lock, iflags);
+	return retval;
+}
+
+/**
+ * Empty request queue of an endpoint
+ */
+static void empty_req_queue(struct udc_ep *ep)
+{
+	struct udc_request      *req;
+
+	ep->halted = 1;
+	while (!list_empty(&ep->queue)) {
+		req = list_entry(ep->queue.next,
+				struct udc_request,
+				queue);
+		complete_req(ep, req, -ESHUTDOWN);
+	}
+}
+
+/**
+ * Dequeues a request packet, called by gadget driver
+ */
+static int udc_dequeue(struct usb_ep *usbep, struct usb_request *usbreq)
+{
+	struct udc_ep   	*ep;
+	struct udc_request      *req;
+	unsigned long           iflags;
+
+	if (!usbep || !usbreq)
+		return -EINVAL;
+
+	ep = container_of(usbep, struct udc_ep, ep);
+	if (!ep->desc && (ep->num != 0 && ep->num != UDC_EP0OUT_IX))
+		return -EINVAL;
+
+	req = container_of(usbreq, struct udc_request, req);
+
+	spin_lock_irqsave(&ep->dev->lock, iflags);
+	complete_req(ep, req, -ECONNRESET);
+	spin_unlock_irqrestore(&ep->dev->lock, iflags);
+
+	return 0;
+}
+
+/**
+ * Halt or clear halt of endpoint, called by gadget driver
+ */
+static int udc_set_halt(struct usb_ep *usbep, int halt)
+{
+	struct udc_ep   *ep;
+	unsigned long iflags;
+	int retval = 0;
+
+	if (!usbep)
+		return -EINVAL;
+
+	DBG("set_halt %s: halt=%d\n", usbep->name, halt);
+
+	/* TODO: DRY */
+	ep = container_of(usbep, struct udc_ep, ep);
+	if (!ep->desc && (ep->num != 0 && ep->num != UDC_EP0OUT_IX))
+		return -EINVAL;
+	if (!ep->dev->driver || ep->dev->gadget.speed == USB_SPEED_UNKNOWN)
+		return -ESHUTDOWN;
+	if (ep->dev->sys_suspended)
+		return -ESHUTDOWN;
+
+	spin_lock_irqsave(&udc_stall_spinlock, iflags);
+	/* halt or clear halt */
+	if (halt) {
+		if (ep->num != 0) {
+			UDC_SET_BIT(UDC_EPCTL_S, &ep->regs->ctl);
+			ep->halted = 1;
+		}
+	} else {
+		if (ep->halted) {
+			UDC_UNSET_BIT(UDC_EPCTL_S, &ep->regs->ctl);
+			udc_clear_NAK(ep);
+			ep->halted = 0;
+		}
+	}
+	spin_unlock_irqrestore(&udc_stall_spinlock, iflags);
+	return retval;
+}
+
+/**
+ * Return fifo fill state, called by gadget driver
+ * This is equivalent to unimplemented
+ */
+static int udc_fifo_status(struct usb_ep *usbep)
+{
+	return 0;
+}
+
+/**
+ * Flush the endpoint fifo, called by gadget driver
+ * This is equivalent to unimplemented
+ */
+static void udc_fifo_flush(struct usb_ep *usbep)
+{
+	return;
+}
+
+static struct usb_ep_ops udc_ep_ops = {
+	.enable         = udc_ep_enable,
+	.disable        = udc_disable,
+
+	.queue          = udc_queue,
+	.dequeue        = udc_dequeue,
+
+	.alloc_request  = udc_alloc_request,
+	.free_request   = udc_free_request,
+
+	.set_halt       = udc_set_halt,
+	.fifo_status    = udc_fifo_status,
+	.fifo_flush     = udc_fifo_flush,
+};
+
+/*-------------------------------------------------------------------------*/
+
+/**
+ * Get frame count fifo, called by gadget driver
+ * This is equivalent to unimplemented
+ */
+static int udc_get_frame(struct usb_gadget *gadget)
+{
+	return 0;
+}
+
+/**
+ * Remote wakeup gadget interface
+ */
+static int udc_wakeup(struct usb_gadget *gadget)
+{
+	struct udc              *dev;
+
+	if (!gadget)
+		return -EINVAL;
+	dev = container_of(gadget, struct udc, gadget);
+	udc_remote_wakeup(dev);
+
+	return 0;
+}
+
+/**
+ * gadget ioctl, used for OTG support notification
+ * \return 1 if OTG supported, else 0
+ */
+static int udc_gadget_ioctl(struct usb_gadget *gadget, unsigned cmd,
+			     unsigned long par)
+{
+	struct udc              *dev;
+	int                     retval = 0;
+	unsigned long           iflags;
+	u32 tmp;
+
+	if (!gadget)
+		return -ENODEV;
+	dev = container_of(gadget, struct udc, gadget);
+	spin_lock_irqsave(&dev->lock, iflags);
+	tmp = ioread32(&dev->regs->cfg);
+
+	if (tmp & UDC_BIT(UDC_DEVCFG_HNPSFEN))
+		retval = 1;
+	else
+		retval = 0;
+	spin_unlock_irqrestore(&dev->lock, iflags);
+	return retval;
+}
+
+static const struct usb_gadget_ops udc_ops = {
+	.wakeup         = udc_wakeup,
+	.get_frame      = udc_get_frame,
+	.ioctl          = udc_gadget_ioctl,
+};
+
+/**
+ * Setups endpoint parameters, adds endpoints to linked list
+ */
+static void make_ep_lists(struct udc *dev)
+{
+	/* make gadget ep lists */
+	INIT_LIST_HEAD(&dev->gadget.ep_list);
+	list_add_tail(&dev->ep[UDC_EPIN_STATUS_IX].ep.ep_list,
+		      &dev->gadget.ep_list);
+	list_add_tail(&dev->ep[UDC_EPIN_IX].ep.ep_list, &dev->gadget.ep_list);
+	list_add_tail(&dev->ep[UDC_EPOUT_IX].ep.ep_list,
+		       &dev->gadget.ep_list);
+
+	/* fifo config */
+	dev->ep[UDC_EPIN_STATUS_IX].fifo_depth = UDC_EPIN_SMALLINT_BUFF_SIZE;
+	if (dev->gadget.speed == USB_SPEED_FULL)
+		dev->ep[UDC_EPIN_IX].fifo_depth = UDC_FS_EPIN_BUFF_SIZE;
+	else if (dev->gadget.speed == USB_SPEED_HIGH)
+		dev->ep[UDC_EPIN_IX].fifo_depth = hs_tx_buf;
+	dev->ep[UDC_EPOUT_IX].fifo_depth = UDC_RXFIFO_SIZE;
+}
+
+/**
+ * Init registers at driver load time
+ */
+static int startup_registers(struct udc *dev)
+{
+	u32 tmp;
+	DBG("In startup_registers()\n");
+
+	/* init controller by soft reset */
+	udc_soft_reset(dev);
+
+	/* mask not needed interrupts */
+	udc_mask_unused_interrupts(dev);
+
+	/* put into initial config */
+	udc_basic_init(dev);
+	/* link up all endpoints */
+	udc_setup_endpoints(dev);
+
+	/* program speed */
+	tmp = ioread32(&dev->regs->cfg);
+	if (use_fullspeed)
+		tmp = UDC_ADDBITS(tmp, UDC_DEVCFG_SPD_FS, UDC_DEVCFG_SPD);
+	else
+		tmp = UDC_ADDBITS(tmp, UDC_DEVCFG_SPD_HS, UDC_DEVCFG_SPD);
+	iowrite32(tmp, &dev->regs->cfg);
+
+	DBG("After speed program\n");
+
+	return 0;
+}
+
+/**
+ * Inits UDC context
+ */
+static void udc_basic_init(struct udc *dev)
+{
+	dev->gadget.speed = USB_SPEED_UNKNOWN;
+
+	/* disable DMA */
+	UDC_UNSET_BIT(UDC_DEVCTL_RDE, &dev->regs->ctl);
+	UDC_UNSET_BIT(UDC_DEVCTL_TDE, &dev->regs->ctl);
+
+	/* enable dynamic CSR programming */
+	UDC_SET_BITS((UDC_BIT(UDC_DEVCFG_CSR_PRG) |
+		      UDC_BIT(UDC_DEVCFG_SP) |
+		      UDC_BIT(UDC_DEVCFG_RWKP)),
+		     &dev->regs->cfg);
+
+	make_ep_lists(dev);
+
+	dev->data_ep_enabled = 0;
+	dev->data_ep_queued = 0;
+}
+
+/**
+ * Sets initial endpoint parameters
+ *
+ * \param dev           pointer to device struct
+ */
+static void udc_setup_endpoints(struct udc *dev)
+{
+	struct udc_ep   *ep;
+	u32     tmp;
+
+	DBG("udc_setup_endpoints()\n");
+
+	/* read enum speed */
+	tmp = ioread32(&dev->regs->sts);
+	tmp = UDC_GETBITS(tmp, UDC_DEVSTS_ENUM_SPEED);
+	if (tmp ==  UDC_DEVSTS_ENUM_SPEED_HIGH)
+		dev->gadget.speed = USB_SPEED_HIGH;
+	else if (tmp ==  UDC_DEVSTS_ENUM_SPEED_FULL)
+		dev->gadget.speed = USB_SPEED_FULL;
+
+	/* set basic ep parameters */
+	for (tmp = 0; tmp < UDC_EP_NUM; tmp++) {
+		ep = &dev->ep[tmp];
+		ep->dev = dev;
+		ep->ep.name = ep_string[tmp];
+		ep->num = tmp;
+		/* txfifo size is calculated at enable time */
+		ep->txfifo = dev->txfifo;
+
+		/* fifo size */
+		if (tmp < UDC_EPIN_NUM) {
+			ep->fifo_depth = UDC_TXFIFO_SIZE;
+			ep->in = 1;
+		} else {
+			ep->fifo_depth = UDC_RXFIFO_SIZE;
+			ep->in = 0;
+
+		}
+		ep->regs = &dev->ep_regs[tmp];
+		/* ep will be reset only if ep was not enabled before to avoid
+		   disabling ep interrupts when ENUM interrupt occurs but ep is
+		   not enabled by gadget driver  */
+		if (!ep->desc)
+			ep_init(dev->regs, ep);
+
+		/* nak OUT endpoints until enable - not for ep0*/
+		if (tmp > UDC_EPIN_NUM) {
+			UDC_SET_BIT(UDC_EPCTL_SNAK, &ep->regs->ctl);
+			ep->naking = 1;
+		}
+	}
+
+	DBG("Done setting up ep params\n");
+
+	/* EP0 max packet */
+	if (dev->gadget.speed == USB_SPEED_FULL) {
+		dev->ep[UDC_EP0IN_IX].ep.maxpacket = UDC_FS_EP0IN_MAX_PKT_SIZE;
+		dev->ep[UDC_EP0OUT_IX].ep.maxpacket =
+			UDC_FS_EP0OUT_MAX_PKT_SIZE;
+	} else if (dev->gadget.speed == USB_SPEED_HIGH) {
+		dev->ep[UDC_EP0IN_IX].ep.maxpacket = UDC_EP0IN_MAX_PKT_SIZE;
+		dev->ep[UDC_EP0OUT_IX].ep.maxpacket = UDC_EP0OUT_MAX_PKT_SIZE;
+	}
+
+	DBG("Done setting up EP0 max packet\n");
+
+	/* with suspend bug workaround, ep0 params for gadget driver
+	   are set at gadget driver bind() call */
+	dev->gadget.ep0 = &dev->ep[UDC_EP0IN_IX].ep;
+	dev->ep[UDC_EP0IN_IX].halted = 0;
+	INIT_LIST_HEAD(&dev->gadget.ep0->ep_list);
+
+	/* init cfg/alt/int */
+	dev->cur_config = 0;
+	dev->cur_intf = 0;
+	dev->cur_alt = 0;
+
+	DBG("udc_setup_endpoints done\n");
+}
+
+/**
+ * Bringup after Connect event,
+ * initial bringup to be ready for ep0 events
+ */
+static void usb_connect(struct udc *dev)
+{
+	INFO("USB Connect\n");
+
+	dev->connected = 1;
+
+	/* put into initial config */
+	udc_basic_init(dev);
+
+	/* enable device setup interrupts */
+	udc_enable_dev_setup_interrupts(dev);
+}
+
+/**
+ * Calls gadget with disconnect event and resets the UDC and makes
+ * initial bringup to be ready for ep0 events
+ */
+static void usb_disconnect(struct udc *dev)
+{
+	INFO("USB Disconnect\n");
+
+	dev->connected = 0;
+
+	/* mask interrupts */
+	udc_mask_unused_interrupts(dev);
+
+	tasklet_schedule(&disconnect_tasklet);
+}
+
+/**
+ * Tasklet for disconnect to be outside of interrupt
+ * context
+ */
+static void udc_tasklet_disconnect(unsigned long par)
+{
+	struct udc *dev = (struct udc *)(*((struct udc **) par));
+	u32 tmp;
+
+	DBG("Tasklet disconnect\n");
+	if (dev->driver) {
+		/* call gadget to reset configs etc. */
+		if (spin_is_locked(&dev->lock)) {
+			spin_unlock(&dev->lock);
+			dev->driver->disconnect(&dev->gadget);
+			spin_lock(&dev->lock);
+		} else
+			dev->driver->disconnect(&dev->gadget);
+
+		/* empty queues */
+		for (tmp = 0; tmp < UDC_EP_NUM; tmp++)
+			empty_req_queue(&dev->ep[tmp]);
+	}
+
+	/* disable ep0 */
+	ep_init(dev->regs, &dev->ep[UDC_EP0IN_IX]);
+
+	if (!soft_reset_occured) {
+		/* init controller by soft reset */
+		udc_soft_reset(dev);
+		soft_reset_occured++;
+	}
+	/* re-enable dev interrupts */
+	udc_enable_dev_setup_interrupts(dev);
+	/* back to full speed ? */
+	if (use_fullspeed) {
+		tmp = ioread32(&dev->regs->cfg);
+		tmp = UDC_ADDBITS(tmp, UDC_DEVCFG_SPD_FS, UDC_DEVCFG_SPD);
+		iowrite32(tmp, &dev->regs->cfg);
+	}
+}
+
+/**
+ * Reset the UDC core
+ */
+static void udc_soft_reset(struct udc *dev)
+{
+	DBG("Soft reset\n");
+	/* reset possible waiting interrupts, because int.
+	   status is lost after soft reset */
+	/* ep int. status reset */
+	iowrite32(UDC_EPINT_MSK_DISABLE_ALL, &dev->regs->ep_irqsts);
+	/* device int. status reset */
+	iowrite32(UDC_DEV_MSK_DISABLE, &dev->regs->irqsts);
+
+	spin_lock_irq(&udc_irq_spinlock);
+	iowrite32(UDC_BIT(UDC_DEVCFG_SOFTRESET), &dev->regs->cfg);
+	ioread32(&dev->regs->cfg);
+	spin_unlock_irq(&udc_irq_spinlock);
+
+}
+
+/**
+ * Called by OTG driver to notify us regarding an OTG event
+ *
+ * \param code           notify code
+ */
+void otg_notify(unsigned int code)
+{
+	DBG("OTG notify code=%d\n", code);
+	switch (code) {
+	case OTG_GADGET_EVT_SVDROP:
+		/* disconnect event */
+		usb_disconnect(udc);
+		break;
+	case OTG_GADGET_EVT_SVALID:
+		/* connect event */
+		usb_connect(udc);
+		break;
+	case OTG_GADGET_REQ_WAKE:
+		/* remote wakeup event */
+		udc_remote_wakeup(udc);
+		break;
+	}
+}
+
+/**
+ * Inits endpoint 0 so that SETUP packets are processed
+ *
+ * \param dev           pointer to device struct
+ */
+static void activate_control_endpoints(struct udc *dev)
+{
+	u32 tmp;
+	struct udc_ep 	*ep0in = &dev->ep[UDC_EP0IN_IX];
+	struct udc_ep 	*ep0out = &dev->ep[UDC_EP0OUT_IX];
+
+	DBG("activate_control_endpoints\n");
+
+	/* flush fifo */
+	UDC_SET_BIT(UDC_EPCTL_F, &ep0in->regs->ctl);
+
+	/* set ep0 directions */
+	ep0in->in = 1;
+	ep0out->in = 0;
+
+	/* set buffer size (tx fifo entries) of EP0_IN */
+	tmp = ioread32(&ep0in->regs->bufin_framenum);
+	if (dev->gadget.speed == USB_SPEED_FULL)
+		tmp = UDC_ADDBITS(tmp, UDC_FS_EPIN0_BUFF_SIZE,
+		      UDC_EPIN_BUFF_SIZE);
+	else if (dev->gadget.speed == USB_SPEED_HIGH)
+		tmp = UDC_ADDBITS(tmp, UDC_EPIN0_BUFF_SIZE, UDC_EPIN_BUFF_SIZE);
+	iowrite32(tmp, &ep0in->regs->bufin_framenum);
+
+	/* set max packet size of EP0_IN */
+	tmp = ioread32(&ep0in->regs->bufout_maxpkt);
+	if (dev->gadget.speed == USB_SPEED_FULL)
+		tmp = UDC_ADDBITS(tmp, UDC_FS_EP0IN_MAX_PKT_SIZE,
+				  UDC_EP_MAX_PKT_SIZE);
+	else if (dev->gadget.speed == USB_SPEED_HIGH)
+		tmp = UDC_ADDBITS(tmp, UDC_EP0IN_MAX_PKT_SIZE,
+				  UDC_EP_MAX_PKT_SIZE);
+	iowrite32(tmp, &ep0in->regs->bufout_maxpkt);
+
+	/* set max packet size of EP0_OUT */
+	tmp = ioread32(&ep0out->regs->bufout_maxpkt);
+	if (dev->gadget.speed == USB_SPEED_FULL)
+		tmp = UDC_ADDBITS(tmp, UDC_FS_EP0OUT_MAX_PKT_SIZE,
+				  UDC_EP_MAX_PKT_SIZE);
+	else if (dev->gadget.speed == USB_SPEED_HIGH)
+		tmp = UDC_ADDBITS(tmp, UDC_EP0OUT_MAX_PKT_SIZE,
+				  UDC_EP_MAX_PKT_SIZE);
+	iowrite32(tmp, &ep0out->regs->bufout_maxpkt);
+
+	/* set max packet size of EP0 in UDC CSR  */
+	tmp = ioread32(&dev->csr->ne[0]);
+	if (dev->gadget.speed == USB_SPEED_FULL)
+		tmp = UDC_ADDBITS(tmp, UDC_FS_EP0OUT_MAX_PKT_SIZE,
+				  UDC_CSR_NE_MAX_PKT);
+	else if (dev->gadget.speed == USB_SPEED_HIGH)
+		tmp = UDC_ADDBITS(tmp, UDC_EP0OUT_MAX_PKT_SIZE,
+				  UDC_CSR_NE_MAX_PKT);
+	iowrite32(tmp, &dev->csr->ne[0]);
+
+	ep0out->td->status |= UDC_BIT(UDC_DMA_OUT_STS_L);
+	/* write dma desc address */
+	iowrite32(ep0out->td_stp_dma, &ep0out->regs->subptr);
+	iowrite32(ep0out->td_phys, &ep0out->regs->desptr);
+	/* enable DMA */
+	UDC_SET_BITS((UDC_BIT(UDC_DEVCTL_MODE)
+		      | UDC_BIT(UDC_DEVCTL_RDE)
+		      | UDC_BIT(UDC_DEVCTL_TDE)),
+		     &dev->regs->ctl);
+
+	if (use_dma_bufferfill_mode)
+		UDC_SET_BIT(UDC_DEVCTL_BF, &dev->regs->ctl);
+	else if (use_dma_ppb_du)
+		UDC_SET_BIT(UDC_DEVCTL_DU, &dev->regs->ctl);
+
+	/* clear NAK by writing CNAK for EP0IN */
+	udc_clear_NAK(ep0in);
+	udc_clear_NAK(ep0out);
+}
+
+/**
+ * \brief
+ * Make endpoint 0 ready for control traffic
+ */
+static int setup_ep0(struct udc *dev)
+{
+	activate_control_endpoints(dev);
+	/* enable ep0 interrupts */
+	udc_enable_ep0_interrupts(dev);
+	/* enable device setup interrupts */
+	udc_enable_dev_setup_interrupts(dev);
+
+	return 0;
+}
+
+/**
+ * Called by gadget driver to register itself
+ */
+int usb_gadget_register_driver(struct usb_gadget_driver *driver)
+{
+	struct udc              *dev = udc;
+	int                     retval;
+	u32 tmp;
+
+	DBG("In usb_gadget_register_driver\n");
+
+	DBG("Driver speed is %d\n", driver->speed);
+	if (!driver || !driver->bind
+			|| !driver->unbind
+			|| !driver->setup
+			|| driver->speed != USB_SPEED_HIGH)
+		return -EINVAL;
+	if (!dev)
+		return -ENODEV;
+	if (dev->driver)
+		return -EBUSY;
+
+	driver->driver.bus = 0;
+	dev->driver = driver;
+	dev->gadget.dev.driver = &driver->driver;
+
+	device_create_file(&dev->pdev->dev, &dev_attr_function);
+	device_create_file(&dev->pdev->dev, &dev_attr_queues);
+
+#ifdef CONFIG_USB_OTG
+	DBG("Gadget is OTG\n");
+	dev->gadget.is_otg = 1;
+#endif
+	retval = driver->bind(&dev->gadget);
+	/* e.g. ether gadget needs driver_data on both ep0 endpoints */
+	dev->ep[UDC_EP0OUT_IX].ep.driver_data =
+		dev->ep[UDC_EP0IN_IX].ep.driver_data;
+
+	gadget_bind_count++;
+	if (retval) {
+		DBG("binding to  %s returning %d\n",
+				driver->driver.name, retval);
+		dev->driver = 0;
+		dev->gadget.dev.driver = 0;
+		return retval;
+	} else {
+		DBG("Binding successful\n");
+	}
+
+	/* if otg driver already registered */
+	/* call otg bind() to mux udc to phy */
+	if (dev->otg_transceiver) {
+		dev->otg_transceiver->set_peripheral(
+				dev->otg_transceiver, &dev->gadget);
+		/* clear SD */
+		tmp = ioread32(&dev->regs->ctl);
+		tmp = tmp & UDC_CLEAR_BIT(UDC_DEVCTL_SD);
+		iowrite32(tmp, &dev->regs->ctl);
+	}
+
+	return 0;
+}
+EXPORT_SYMBOL(usb_gadget_register_driver);
+
+/**
+ * Called by OTG driver to register itself
+ */
+int usb_gadget_register_otg(struct otg_transceiver *(*get_transceiver)(void))
+{
+	struct udc              *dev = udc;
+	int                     retval;
+	u32 tmp;
+
+	if (!get_transceiver)
+		return -EINVAL;
+	if (!dev)
+		return -ENODEV;
+	if (dev->otg_transceiver)
+		return -EBUSY;
+
+	dev->otg_transceiver = get_transceiver();
+
+	if (!dev->otg_transceiver->otg_priv)
+		return -EINVAL;
+	dev->otg_driver = (struct usb_otg_gadget_extension *)
+		dev->otg_transceiver->otg_priv;
+
+	/* init registers here first with suspend bug */
+	if (!otg_reg_count) {
+		startup_registers(dev);
+		otg_reg_count++;
+	}
+
+	/* set notify function */
+	dev->otg_driver->notify = otg_notify;
+	DBG("otg_driver->notify set.\n");
+	/* if gadget driver already registered */
+	/* call gadget bind() to switch to mux udc to phy */
+	if (dev->driver) {
+		/* otg driver bind() */
+		retval = dev->otg_transceiver->set_peripheral(
+				dev->otg_transceiver, &dev->gadget);
+		if (retval) {
+			DBG("error bind to uoc driver\n");
+			dev->otg_driver = NULL;
+			dev->otg_transceiver = NULL;
+			return retval;
+		}
+		/* get ready for ep0 traffic */
+		setup_ep0(dev);
+
+		/* clear SD */
+		tmp = ioread32(&dev->regs->ctl);
+		tmp = tmp & UDC_CLEAR_BIT(UDC_DEVCTL_SD);
+		iowrite32(tmp, &dev->regs->ctl);
+	}
+
+	INFO("registered uoc driver\n");
+
+	return 0;
+}
+EXPORT_SYMBOL(usb_gadget_register_otg);
+
+/**
+ * Called by OTG driver to unregister itself
+ */
+int usb_gadget_unregister_otg(void)
+{
+	struct udc      *dev = udc;
+	unsigned long   flags;
+
+	if (!dev)
+		return -ENODEV;
+
+	spin_lock_irqsave(&dev->lock, flags);
+
+	/* mask not needed interrupts */
+	udc_mask_unused_interrupts(dev);
+
+	spin_unlock_irqrestore(&dev->lock, flags);
+
+	dev->otg_supported = 0;
+	if (dev->otg_transceiver) {
+		dev->otg_transceiver->set_peripheral(dev->otg_transceiver,
+				NULL);
+		dev->otg_transceiver = NULL;
+	}
+	if (dev->otg_driver) {
+		dev->otg_driver->notify = NULL;
+		dev->otg_driver = NULL;
+	}
+
+	/* set SD */
+	UDC_SET_BIT(UDC_DEVCTL_SD, &dev->regs->ctl);
+
+	DBG("unregistered uoc driver\n");
+	return 0;
+}
+EXPORT_SYMBOL(usb_gadget_unregister_otg);
+
+/**
+ *  shutdown requests and disconnect from gadget
+ */
+static void shutdown(struct udc *dev, struct usb_gadget_driver *driver)
+{
+	int tmp;
+
+	/* empty queues and init hardware */
+	udc_basic_init(dev);
+	for (tmp = 0; tmp < UDC_EP_NUM; tmp++)
+		empty_req_queue(&dev->ep[tmp]);
+
+	if (dev->gadget.speed != USB_SPEED_UNKNOWN)
+		driver->disconnect(&dev->gadget);
+	udc_setup_endpoints(dev);
+}
+
+/**
+ * Called by gadget driver to unregister itself
+ */
+int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
+{
+	struct udc      *dev = udc;
+	unsigned long   iflags;
+
+	if (!dev)
+		return -ENODEV;
+	if (!driver || driver != dev->driver)
+		return -EINVAL;
+	if (gadget_bind_count) {
+		spin_lock_irqsave(&dev->lock, iflags);
+		shutdown(dev, driver);
+		spin_unlock_irqrestore(&dev->lock, iflags);
+	}
+
+	/* unbind from otg driver first */
+	if (dev->otg_transceiver) {
+		dev->otg_transceiver->set_peripheral(
+				dev->otg_transceiver, NULL);
+	}
+
+	if (gadget_bind_count)
+		driver->unbind(&dev->gadget);
+
+	gadget_bind_count = 0;
+	dev->driver = 0;
+
+	/* set SD */
+	UDC_SET_BIT(UDC_DEVCTL_SD, &dev->regs->ctl);
+	DBG("%s: unregistered\n", driver->driver.name);
+
+	return 0;
+}
+EXPORT_SYMBOL(usb_gadget_unregister_driver);
+
+void update_req_count(struct udc_request *req)
+{
+	struct udc_data_dma *last_desc;
+	unsigned int count;
+	unsigned int tmp;
+
+	last_desc = udc_get_last_dma_desc(req);
+	count = UDC_GETBITS(last_desc->status, UDC_DMA_OUT_STS_RXBYTES);
+	if (count == 0) {
+		/* on 64k packets the RXBYTES field is zero */
+		if (req->req.length == UDC_DMA_MAXPACKET)
+			count = UDC_DMA_MAXPACKET;
+	}
+
+	VDBG("Received %lx bytes\n", (unsigned long) count);
+
+	tmp = req->req.length - req->req.actual;
+	if (count > tmp) {
+		ERR("Buffer overrun!\n");
+		req->req.status = -EOVERFLOW;
+		count = tmp;
+	}
+
+	req->req.actual += count;
+}
+
+/**
+ * Check for and clear BNA and Hardware errors
+ * returns nonzero if any errors were found
+ */
+static inline int check_and_clear_errors(struct udc_ep *ep)
+{
+	u32 				epsts;
+
+	epsts = ioread32(&ep->regs->sts);
+	/* BNA event */
+	if (epsts & UDC_BIT(UDC_EPSTS_BNA)) {
+		ERR("BNA occurred - %s: desptr = 0x%8.8x\n", ep->ep.name,
+		       ep->regs->desptr);
+		UDC_SET_BIT(UDC_EPSTS_BNA, &ep->regs->sts);
+		return 1;
+	}
+
+	/* HE event */
+	if (epsts & UDC_BIT(UDC_EPSTS_HE)) {
+		ERR("HE occured on %s\n", ep->ep.name);
+		UDC_SET_BIT(UDC_EPSTS_HE, &ep->regs->sts);
+		return 1;
+	}
+
+	return 0;
+}
+
+/**
+ * Interrupt handler for data OUT traffic
+ */
+static inline int udc_data_out_isr(struct udc *dev, int ep_ix)
+{
+	int 				ret_val = 0;
+	u32				tmp;
+	struct udc_ep   		*ep;
+	struct udc_request              *req;
+	unsigned long 			iflags;
+	struct udc_data_dma 		*last_desc;
+	unsigned 			dma_done;
+
+	VDBG("ep%d irq\n", ep_ix);
+	ep = &dev->ep[ep_ix];
+
+	spin_lock_irqsave(&dev->lock, iflags);
+
+	tmp = ioread32(&ep->regs->sts);
+	/* BNA event ? */
+	if (tmp & UDC_BIT(UDC_EPSTS_BNA)) {
+		ERR("BNA occurred - %s: desptr = 0x%8.8x\n", ep->ep.name,
+		       ep->regs->desptr);
+		/* clear BNA */
+		ep->regs->sts = UDC_BIT(UDC_EPSTS_BNA);
+		au_sync();
+		goto finished;
+	}
+
+	/* HE event ? */
+	if (tmp & UDC_BIT(UDC_EPSTS_HE)) {
+		ERR("HE occured on %s\n", ep->ep.name);
+
+		/* clear HE */
+		ep->regs->sts = UDC_BIT(UDC_EPSTS_HE);
+		au_sync();
+
+		ret_val = 1;
+		goto finished;
+	}
+
+	/*
+	epsts = ioread32(&ep->regs->sts);
+	if (check_and_clear_errors(ep))
+		goto finished;
+		*/
+
+	if (!list_empty(&ep->queue))
+		req = list_entry(ep->queue.next, struct udc_request, queue);
+	else {
+		INFO("In %s but there is no queued request.\n", __func__);
+		goto finished;
+	}
+
+	/* check for DMA done */
+	last_desc = udc_get_last_dma_desc(req);
+	dma_done = UDC_GETBITS(last_desc->status, UDC_DMA_OUT_STS_BS);
+
+	if (dma_done == UDC_DMA_OUT_STS_BS_DMA_DONE) {
+		update_req_count(req);
+		complete_req(ep, req, 0);
+		tasklet_schedule(&ep->execute_tasklet);
+	} else {
+		INFO("Got a DMA done interrupt but DMA is not done.\n");
+		print_descriptor_chain(ep);
+	}
+
+finished:
+	/* clear OUT bits in ep status */
+	ep->regs->sts = UDC_EPSTS_OUT_CLEAR;
+	au_sync();
+
+	spin_unlock_irqrestore(&dev->lock, iflags);
+	return ret_val;
+}
+
+/**
+ * Interrupt handler for data IN traffic
+ */
+static inline int udc_data_in_isr(struct udc *dev, int ep_ix)
+{
+	int ret_val = 0;
+	u32 epsts;
+	struct udc_ep  *ep;
+	unsigned long 			iflags;
+	struct udc_request *req;
+
+	spin_lock_irqsave(&dev->lock, iflags);
+
+	ep = &dev->ep[ep_ix];
+	epsts = ioread32(&ep->regs->sts);
+
+	/* BNA */
+	if (epsts & UDC_BIT(UDC_EPSTS_BNA)) {
+		ERR("BNA ep%din occured - DESPTR = %08lx \n", ep->num,
+			(long unsigned int)ep->regs->desptr);
+
+		/* clear BNA */
+		ep->regs->sts = UDC_BIT(UDC_EPSTS_BNA);
+		au_sync();
+
+		goto finished;
+	}
+
+	/* HE event */
+	if (epsts & UDC_BIT(UDC_EPSTS_HE)) {
+		ERR("HE occured on %s\n", ep->ep.name);
+
+		/* clear HE */
+		ep->regs->sts = UDC_BIT(UDC_EPSTS_HE);
+		au_sync();
+
+		ret_val = 1;
+		goto finished;
+	}
+	/*
+	epsts = ioread32(&ep->regs->sts);
+	if (check_and_clear_errors(ep))
+		goto finished;
+		*/
+
+	if (!list_empty(&ep->queue)) {
+		req = list_entry(ep->queue.next, struct udc_request, queue);
+	} else {
+		/* This is not all that unusual - the host can be greedy when
+		 * it wants IN data and might beat the gadget to queueing a
+		 * request.
+		 */
+		goto finished;
+	}
+
+	/* DMA completion */
+	if (epsts & UDC_BIT(UDC_EPSTS_TDC)) {
+		/* Disable this IRQ to prevent flooding */
+		dev->regs->ep_irqmsk |= UDC_BIT(ep->num);
+		au_sync();
+
+		complete_req(ep, req, 0);
+		tasklet_schedule(&ep->execute_tasklet);
+	}
+
+	if (epsts & UDC_BIT(UDC_EPSTS_IN)) {
+		/* set poll demand bit */
+		if (req->ready_for_p_bit) {
+			req->ready_for_p_bit = false;
+			ep->regs->ctl |= UDC_BIT(UDC_EPCTL_P);
+			au_sync();
+		}
+	}
+
+finished:
+	/* clear status bits */
+	UDC_SET_BITS(epsts, &ep->regs->sts);
+	spin_unlock_irqrestore(&dev->lock, iflags);
+	return ret_val;
+}
+
+/**
+ * Interrupt handler for Control OUT traffic
+ *
+ * \param dev           pointer to UDC device object
+ * \return 0 if success
+ */
+static inline int udc_control_out_isr(struct udc *dev)
+{
+	int ret_val = 0;
+	u32 tmp;
+	int setup_supported;
+	struct udc_ep   *ep0in;
+	struct udc_ep   *ep0out;
+
+	ep0out = &dev->ep[UDC_EP0OUT_IX];
+	ep0in = &dev->ep[UDC_EP0IN_IX];
+
+	/* clear irq */
+	UDC_SET_BIT(UDC_EPINT_OUT_EP0, &dev->regs->ep_irqsts);
+	if (check_and_clear_errors(ep0out))
+		goto finished;
+
+	tmp = ep0out->regs->sts;
+
+	/* type of data: SETUP or DATA 0 bytes */
+	tmp = UDC_GETBITS(tmp, UDC_EPSTS_OUT);
+	/* setup data */
+	if (tmp == UDC_EPSTS_OUT_SETUP) {
+		dev->waiting_zlp_ack_ep0in = 0;
+
+		ep0out->regs->sts |= UDC_EPSTS_OUT_CLEAR;
+
+		setup_data.data[0] = dev->ep[UDC_EP0OUT_IX].td_stp->data12;
+		setup_data.data[1] = dev->ep[UDC_EP0OUT_IX].td_stp->data34;
+		ep0out->td_stp->status = UDC_DMA_STP_STS_BS_HOST_READY;
+
+		/* determine direction of control data */
+		if ((setup_data.request.bRequestType & USB_DIR_IN) == 0) {
+			dev->gadget.ep0 = &dev->ep[UDC_EP0OUT_IX].ep;
+		} else {
+			dev->gadget.ep0 = &dev->ep[UDC_EP0IN_IX].ep;
+			udc_set_rde(dev);
+		}
+
+		setup_supported = dev->driver->setup(&dev->gadget,
+						     &setup_data.request);
+
+		tmp = ioread32(&dev->ep[UDC_EP0IN_IX].regs->ctl);
+
+		if (setup_supported >= 0 &&
+				setup_supported < UDC_EP0IN_MAXPACKET) {
+			ep0in->regs->ctl |= UDC_BIT(UDC_EPCTL_CNAK);
+		} else if (setup_supported < 0) {
+			/* if unsupported request then stall */
+			ep0in->regs->ctl |= UDC_BIT(UDC_EPCTL_S);
+			au_sync();
+		}
+
+		ep0out->regs->ctl |= UDC_BIT(UDC_EPCTL_CNAK);
+		au_sync();
+	} else if (tmp == UDC_EPSTS_OUT_DATA) {
+		/* no req if 0 packet, just reactivate */
+		if (list_empty(&ep0out->queue)) {
+			ep0out->td->status =
+				UDC_ADDBITS(ep0out->td->status,
+						UDC_DMA_OUT_STS_BS_HOST_READY,
+						UDC_DMA_OUT_STS_BS);
+		} else {
+			udc_data_out_isr(dev, UDC_EP0OUT_IX);
+			ep0out->regs->desptr = ep0out->td_phys;
+		}
+		udc_set_rde(dev);
+	}
+
+finished:
+	ep0out->regs->sts = UDC_EPSTS_OUT_CLEAR;
+	return ret_val;
+}
+
+/**
+ * Interrupt handler for Control IN traffic
+ *
+ * \param dev           pointer to UDC device object
+ * \return 0 if success
+ */
+static inline int udc_control_in_isr(struct udc *dev)
+{
+	int ret_val = 0;
+	u32 tmp;
+	struct udc_ep *ep;
+	struct udc_request *req;
+
+	ep = &dev->ep[UDC_EP0IN_IX];
+
+	UDC_SET_BIT(UDC_EPINT_IN_EP0, &dev->regs->ep_irqsts);
+
+	tmp = ep->regs->sts;
+	if (!list_empty(&ep->queue)) {
+		req = list_entry(ep->queue.next, struct udc_request, queue);
+
+		/* DMA completion */
+		if (tmp & UDC_BIT(UDC_EPSTS_TDC)) {
+			ep->regs->ctl |= UDC_BIT(UDC_EPCTL_CNAK);
+		} else if (tmp & UDC_BIT(UDC_EPSTS_IN)) {
+			ep->regs->desptr = (u32)req->td_phys;
+			req->td_data->status = UDC_ADDBITS(req->td_data->status,
+						UDC_DMA_STP_STS_BS_HOST_READY,
+						UDC_DMA_STP_STS_BS);
+			au_sync();
+
+			ep->regs->ctl |= UDC_BIT(UDC_EPCTL_P);
+
+			/* All bytes are always transferred */
+			req->req.actual = req->req.length;
+			complete_req(ep, req, 0);
+			au_sync();
+		}
+	}
+	ep->regs->sts = ep->regs->sts;
+	au_sync();
+
+	return ret_val;
+}
+
+/**
+ * Interrupt handler for global device events
+ *
+ * \param dev           pointer to UDC device object
+ * \param dev_irq       device interrupt bit of DEVINT register
+ * \return 0 if success
+ */
+static inline int udc_dev_isr(struct udc *dev, u32 dev_irq)
+{
+	int ret_val = 0;
+	u32 tmp;
+	u32 cfg;
+	struct udc_ep *ep;
+	u16 i;
+	u8 udc_csr_epix;
+
+	DBG("Got interrupt.  dev_irq is %8.8X\n", dev_irq);
+
+	/* SET_CONFIG irq ? */
+	if (dev_irq & UDC_BIT(UDC_DEVINT_SC)) {
+
+		/* read config value */
+		tmp = ioread32(&dev->regs->sts);
+		cfg = UDC_GETBITS(tmp, UDC_DEVSTS_CFG);
+#ifdef UDC_DEBUG
+		/* this is needed for debug only */
+		if (cfg == dev->cur_config)
+			same_cfg = 1;
+		else
+			same_cfg = 0;
+		VDBG("same_cfg=%d\n", same_cfg);
+#endif
+		DBG("SET_CONFIG interrupt: config=%d\n", cfg);
+		dev->cur_config = cfg;
+		dev->set_cfg_not_acked = 1;
+
+		/* make usb request for gadget driver */
+		memset(&setup_data, 0 , sizeof(union udc_setup_data));
+		setup_data.request.bRequest = USB_REQ_SET_CONFIGURATION;
+		setup_data.request.wValue = dev->cur_config;
+
+		/* programm the NE registers */
+		for (i = 0; i < UDC_EP_NUM; i++) {
+			ep = &dev->ep[i];
+			if (ep->in) {
+
+				/* ep ix in UDC CSR register space */
+				udc_csr_epix = ep->num;
+
+
+			} /* OUT ep */
+			else {
+				/* ep ix in UDC CSR register space */
+				udc_csr_epix = ep->num - UDC_CSR_EP_OUT_IX_OFS;
+			}
+
+			tmp = ioread32(&dev->csr->ne[udc_csr_epix]);
+			/* ep cfg */
+			tmp = UDC_ADDBITS(tmp, ep->dev->cur_config,
+					UDC_CSR_NE_CFG);
+			/* write reg */
+			iowrite32(tmp, &dev->csr->ne[udc_csr_epix]);
+
+			/* clear stall bits */
+			ep->halted = 0;
+			tmp = ioread32(&ep->regs->ctl);
+			tmp = tmp & UDC_CLEAR_BIT(UDC_EPCTL_S);
+			iowrite32(tmp, &ep->regs->ctl);
+		}
+		/* call gadget zero with setup data received */
+		spin_unlock(&dev->lock);
+		tmp = dev->driver->setup(&dev->gadget, &setup_data.request);
+		spin_lock(&dev->lock);
+
+	} /* SET_INTERFACE ? */
+	if (dev_irq & UDC_BIT(UDC_DEVINT_SI)) {
+		dev->set_cfg_not_acked = 1;
+		/* read interface and alt setting values */
+		tmp = ioread32(&dev->regs->sts);
+		dev->cur_alt = UDC_GETBITS(tmp, UDC_DEVSTS_ALT);
+		dev->cur_intf = UDC_GETBITS(tmp, UDC_DEVSTS_INTF);
+
+		/* make usb request for gadget driver */
+		memset(&setup_data, 0 , sizeof(union udc_setup_data));
+		setup_data.request.bRequest = USB_REQ_SET_INTERFACE;
+		setup_data.request.bRequestType = USB_RECIP_INTERFACE;
+		setup_data.request.wValue = dev->cur_alt;
+		setup_data.request.wIndex = dev->cur_intf;
+
+		DBG("SET_INTERFACE interrupt: alt=%d intf=%d\n",
+				dev->cur_alt, dev->cur_intf);
+
+		for (i = 0; i < UDC_EP_NUM; i++) {
+			ep = &dev->ep[i];
+			if (ep->in) {
+
+				/* ep ix in UDC CSR register space */
+				udc_csr_epix = ep->num;
+
+
+			} /* OUT ep */
+			else {
+				/* ep ix in UDC CSR register space */
+				udc_csr_epix = ep->num - UDC_CSR_EP_OUT_IX_OFS;
+			}
+
+			/***** UDC CSR reg ****************************/
+			/* set ep values  */
+			tmp = ioread32(&dev->csr->ne[udc_csr_epix]);
+			/* ep interface */
+			tmp = UDC_ADDBITS(tmp, ep->dev->cur_intf,
+					UDC_CSR_NE_INTF);
+			/* ep alt */
+			tmp = UDC_ADDBITS(tmp, ep->dev->cur_alt,
+					UDC_CSR_NE_ALT);
+			/* write reg */
+			iowrite32(tmp, &dev->csr->ne[udc_csr_epix]);
+
+			/* clear stall bits */
+			ep->halted = 0;
+			tmp = ioread32(&ep->regs->ctl);
+			tmp = tmp & UDC_CLEAR_BIT(UDC_EPCTL_S);
+			iowrite32(tmp, &ep->regs->ctl);
+		}
+
+		/* call gadget zero with setup data received */
+		spin_unlock(&dev->lock);
+		tmp = dev->driver->setup(&dev->gadget, &setup_data.request);
+		spin_lock(&dev->lock);
+
+	} /* USB reset */
+	if (dev_irq & UDC_BIT(UDC_DEVINT_UR)) {
+		DBG("USB Reset interrupt\n");
+
+		/* allow soft reset when suspend occurs */
+		soft_reset_occured = 0;
+
+		dev->waiting_zlp_ack_ep0in = 0;
+		dev->set_cfg_not_acked = 0;
+
+		/* mask not needed interrupts */
+		udc_mask_unused_interrupts(dev);
+
+		/* call gadget to reset configs etc. */
+		spin_unlock(&dev->lock);
+		dev->driver->disconnect(&dev->gadget);
+		spin_lock(&dev->lock);
+
+		/* disable ep0 to empty req queue */
+		empty_req_queue(&dev->ep[UDC_EP0IN_IX]);
+		ep_init(dev->regs,
+				&dev->ep[UDC_EP0IN_IX]);
+
+		/* soft reset when rxfifo not empty */
+		tmp = ioread32(&dev->regs->sts);
+		if (!(tmp & UDC_BIT(UDC_DEVSTS_RXFIFO_EMPTY)) &&
+				!soft_reset_after_usbreset_occured) {
+			udc_soft_reset(dev);
+			soft_reset_after_usbreset_occured++;
+		}
+
+		/* put into initial config */
+		udc_basic_init(dev);
+
+		/* enable device setup interrupts */
+		udc_enable_dev_setup_interrupts(dev);
+
+	} /* USB suspend */
+
+	if (dev_irq & UDC_BIT(UDC_DEVINT_ENUM)) {
+		DBG("ENUM interrupt\n");
+#ifdef UDC_DEBUG
+		num_enums++;
+		DBG("%d enumerations !\n", num_enums);
+#endif
+		soft_reset_after_usbreset_occured = 0;
+
+		/* disable ep0 to empty req queue */
+		empty_req_queue(&dev->ep[UDC_EP0IN_IX]);
+		ep_init(dev->regs, &dev->ep[UDC_EP0IN_IX]);
+
+		/* link up all endpoints */
+		udc_setup_endpoints(dev);
+		if (dev->gadget.speed == USB_SPEED_HIGH)
+			INFO("Connect: Speed = HIGH_SPEED\n");
+		else if (dev->gadget.speed == USB_SPEED_FULL)
+			INFO("Connect: Speed = FULL_SPEED\n");
+
+		/* init ep 0 */
+		activate_control_endpoints(dev);
+
+		/* enable ep0 interrupts */
+		udc_enable_ep0_interrupts(dev);
+	}
+
+	return ret_val;
+}
+
+static irqreturn_t udc_irq(int irq, void *pdev)
+{
+	struct udc *dev = pdev;
+	u32 reg;
+	u16 i;
+	u32 ep_irq;
+
+	/* If UDC is suspended, then don't touch any register, otherwise
+	   system hangs in endless retry => possibly hang !!! */
+	if (dev->otg_driver && dev->otg_driver->query) {
+		if (dev->otg_driver->query(0) & OTG_FLAGS_UDC_SUSP)
+			return IRQ_HANDLED;
+	} else {
+		return IRQ_HANDLED;
+	}
+
+	if (dev->sys_suspended)
+		return IRQ_HANDLED;
+
+	spin_lock(&dev->lock);
+
+	/* check for ep irq */
+	reg = ioread32(&dev->regs->ep_irqsts);
+	if (reg) {
+		/* EP0 OUT */
+		if (reg & UDC_BIT(UDC_EPINT_OUT_EP0))
+			udc_control_out_isr(dev);
+
+		if (reg & UDC_BIT(UDC_EPINT_IN_EP0))
+			udc_control_in_isr(dev);
+
+		/* data endpoint */
+		/* iterate ep's */
+		for (i = 1; i < UDC_EP_NUM; i++) {
+			ep_irq = 1 << i;
+			/* irq for out ep ? */
+			if ((reg & ep_irq) && i > UDC_EPIN_NUM) {
+				/* clear irq */
+				iowrite32(ep_irq, &dev->regs->ep_irqsts);
+				udc_data_out_isr(dev, i);
+			} /* irq for in ep ? */
+			if ((reg & ep_irq) && i < UDC_EPIN_NUM && i > 0) {
+				/* clear irq */
+				iowrite32(ep_irq, &dev->regs->ep_irqsts);
+				udc_data_in_isr(dev, i);
+			}
+
+		}
+
+	}
+
+	/* check for dev irq */
+	reg = ioread32(&dev->regs->irqsts);
+	if (reg) {
+		/* clear irq */
+		iowrite32(reg, &dev->regs->irqsts);
+		udc_dev_isr(dev, reg);
+	}
+
+
+	spin_unlock(&dev->lock);
+	return IRQ_HANDLED;
+}
+
+/**
+ * Tears down device
+ *
+ * \param pdev        pointer to device struct
+ */
+static void gadget_release(struct device *pdev)
+{
+	struct udc *dev = dev_get_drvdata(pdev);
+	kfree(dev);
+}
+
+static void udc_remove(struct udc *dev)
+{
+	u32 tmp;
+	/* disable UDC memory, DMA and clock */
+	tmp = ioread32((u32 *) (USB_MSR_BASE + USB_MSR_MCFG));
+	tmp &= UDC_CLEAR_BIT(USBMSRMCFG_DMEMEN)
+		& UDC_CLEAR_BIT(USBMSRMCFG_DBMEN)
+		& UDC_CLEAR_BIT(USBMSRMCFG_UDCCLKEN);
+	iowrite32(tmp, (u32 *)(USB_MSR_BASE + USB_MSR_MCFG));
+
+	device_unregister(&udc->gadget.dev);
+	udc = 0;
+}
+
+static void udc_drv_remove(struct device *_dev)
+{
+	struct platform_device *pdev = to_platform_device(_dev);
+	struct udc *dev = dev_get_drvdata(_dev);
+
+#ifdef UDC_DEBUG
+	print_misc(dev);
+#endif
+	/* gadget driver registered ? */
+	if (dev->driver) {
+		WARN("unregistering %s on driver remove\n",
+				dev->driver->driver.name);
+		usb_gadget_unregister_driver(dev->driver);
+	}
+	/* otg driver registered ? */
+	if (dev->otg_transceiver) {
+		/* should have been done already by driver model core */
+		WARN("uoc driver is still registered\n");
+	}
+	/* dma pool cleanup */
+	if (dev->data_requests)
+		dma_pool_destroy(dev->data_requests);
+	if (dev->stp_requests) {
+		/* cleanup DMA desc's for ep0in */
+		dma_pool_free(dev->stp_requests,
+				dev->ep[UDC_EP0OUT_IX].td_stp,
+				dev->ep[UDC_EP0OUT_IX].td_stp_dma);
+		dma_pool_free(dev->stp_requests,
+				dev->ep[UDC_EP0OUT_IX].td,
+				dev->ep[UDC_EP0OUT_IX].td_phys);
+
+		dma_pool_destroy(dev->stp_requests);
+	}
+
+	/* init controller by soft reset */
+	iowrite32(UDC_BIT(UDC_DEVCFG_SOFTRESET), &dev->regs->cfg);
+
+	if (dev->irq_registered)
+		free_irq(pdev->resource[1].start, dev);
+	if (dev->regs)
+		iounmap(dev->regs);
+	if (dev->mem_region)
+		release_mem_region(pdev->resource[0].start,
+				pdev->resource[0].end + 1
+				- pdev->resource[0].start);
+
+	device_remove_file(&pdev->dev, &dev_attr_registers);
+	dev_set_drvdata(_dev, 0);
+	udc_remove(dev);
+}
+
+__init static int init_dma_pools(struct udc *dev)
+{
+	struct udc_stp_dma      *td_stp;
+	struct udc_data_dma     *td_data;
+	int retval;
+
+	/* consistent DMA mode setting ? */
+	if (use_dma_ppb) {
+		use_dma_bufferfill_mode = 0;
+	} else {
+		use_dma_ppb_du = 0;
+		use_dma_bufferfill_mode = 1;
+	}
+
+	/* DMA setup */
+	dev->data_requests = dma_pool_create("data_requests", NULL,
+			sizeof(struct udc_data_dma),
+			UDC_POOL_ALIGN,
+			UDC_POOL_CROSS);
+	if (!dev->data_requests) {
+		DBG("can't get request data pool\n");
+		retval = -ENOMEM;
+		goto finished;
+	}
+
+	/* EP0 in dma regs = dev control regs */
+	dev->ep[UDC_EP0IN_IX].dma = &dev->regs->ctl;
+
+	/* dma desc for setup data */
+	dev->stp_requests = dma_pool_create("setup requests", NULL,
+			sizeof(struct udc_stp_dma),
+			UDC_POOL_ALIGN,
+			UDC_POOL_CROSS);
+	if (!dev->stp_requests) {
+		DBG("can't get stp request pool\n");
+		retval = -ENOMEM;
+		goto finished;
+	}
+	/* setup */
+	td_stp = dma_pool_alloc(dev->stp_requests, UDC_POOL_GFP_STP,
+			&dev->ep[UDC_EP0OUT_IX].td_stp_dma);
+	if (td_stp == NULL) {
+		retval = -ENOMEM;
+		goto finished;
+	}
+	dev->ep[UDC_EP0OUT_IX].td_stp = td_stp;
+	/* data: 0 packets !? */
+	td_data = dma_pool_alloc(dev->stp_requests, UDC_POOL_GFP_STP,
+			&dev->ep[UDC_EP0OUT_IX].td_phys);
+	if (td_data == NULL) {
+		retval = -ENOMEM;
+		goto finished;
+	}
+	dev->ep[UDC_EP0OUT_IX].td = td_data;
+	/* point to itself */
+	dev->ep[UDC_EP0OUT_IX].td->next = dev->ep[UDC_EP0OUT_IX].td_phys;
+	return 0;
+
+finished:
+	return retval;
+}
+
+/**
+ * Called by kernel  init device context
+ */
+static int udc_drv_probe(struct device *_dev)
+{
+	char                    tmp[8];
+	struct udc              *dev;
+	struct platform_device *pdev = to_platform_device(_dev);
+	u32                     resource;
+	u32                     len;
+	u32                     irq;
+	int                     retval = 0;
+	u32                     reg;
+
+	/* basic init */
+	reg = ioread32((u32 *) (USB_MSR_BASE + USB_MSR_MCFG));
+	if (reg == 0) {
+		/* default value */
+		reg = USBMSRMCFG_DEFAULT;
+		iowrite32(reg, (u32 *)(USB_MSR_BASE + USB_MSR_MCFG));
+		ioread32((u32 *)(USB_MSR_BASE + USB_MSR_MCFG));
+		udelay(1000);
+	}
+	/* enable UDC memory, DMA, clock, cacheable memory,
+	 * read combining and prefetch enable */
+	reg |= UDC_BIT(USBMSRMCFG_DMEMEN) | UDC_BIT(USBMSRMCFG_DBMEN)
+		| UDC_BIT(USBMSRMCFG_UDCCLKEN)
+		| UDC_BIT(USBMSRMCFG_PHYPLLEN)
+#ifdef CONFIG_DMA_COHERENT
+		| UDC_BIT(USBMSRMCFG_UCAM)
+#endif
+		| UDC_BIT(USBMSRMCFG_RDCOMB)
+		| UDC_BIT(USBMSRMCFG_PFEN);
+	iowrite32(reg, (u32 *)(USB_MSR_BASE + USB_MSR_MCFG));
+
+	/* one udc only */
+	if (udc) {
+		WARN("already probed.\n");
+		return -EBUSY;
+	}
+
+	/* init */
+	dev = kmalloc(sizeof(struct udc), GFP_KERNEL);
+	if (!dev) {
+		retval = -ENOMEM;
+		goto finished;
+	}
+	memset(dev, 0, sizeof(struct udc));
+
+	dev->pdev = _dev;
+
+	/* check platform resources */
+	if (pdev->resource[0].flags != IORESOURCE_MEM) {
+		ERR("resource[0] must be IORESOURCE_MEM\n");
+		retval = -ENOMEM;
+		goto finished;
+	}
+	resource = pdev->resource[0].start;
+	len = pdev->resource[0].end + 1 - pdev->resource[0].start;
+	if (pdev->resource[1].flags != IORESOURCE_IRQ) {
+		ERR("resource[1] must be IORESOURCE_IRQ\n");
+		retval = -ENOMEM;
+		goto finished;
+	}
+	irq = pdev->resource[1].start;
+
+	/* platform device resource allocation */
+	/* mem */
+	if (!request_mem_region(resource, len, name)) {
+		ERR("controller already in use\n");
+		retval = -EBUSY;
+		goto finished;
+	}
+	dev->mem_region = 1;
+
+	dev->virt_addr = ioremap_nocache(resource, len);
+	if (dev->virt_addr == NULL) {
+		DBG("start address cannot be mapped\n");
+		retval = -EFAULT;
+		goto finished;
+	}
+
+	/* irq */
+	if (!irq) {
+		ERR("irq not set\n");
+		retval = -ENODEV;
+		goto finished;
+	}
+	snprintf(tmp, sizeof tmp, "%d", irq);
+	if (request_irq(irq, udc_irq, IRQF_SHARED, name, dev) != 0) {
+		ERR("error on request_irq() with %s\n", tmp);
+		retval = -EBUSY;
+		goto finished;
+	}
+	dev->irq_registered = 1;
+
+	dev_set_drvdata(_dev, dev);
+
+	/* chip revision */
+	dev->chiprev = 0;
+
+	/* chip rev for Au1200 */
+	dev->chiprev = (u16) read_c0_prid() & 0xff;
+
+	/* init dma pools */
+	if (use_dma) {
+		retval = init_dma_pools(dev);
+		if (retval != 0)
+			goto finished;
+	}
+
+	dev->phys_addr = resource;
+	dev->irq = irq;
+	dev->pdev = _dev;
+	dev->gadget.dev.parent = _dev;
+	dev->gadget.dev.dma_mask = _dev->dma_mask;
+	/* general probing */
+	if (udc_probe(dev) != 0)
+		goto finished;
+	return retval;
+
+finished:
+	if (dev)
+		udc_drv_remove(_dev);
+	return retval;
+}
+
+/**
+ * general probe
+ */
+__init int udc_probe(struct udc *dev)
+{
+	char                    tmp[128];
+	u32 reg;
+	int retval;
+
+	/* device struct setup */
+	spin_lock_init(&dev->lock);
+	spin_lock_init(&udc_irq_spinlock);
+	spin_lock_init(&udc_stall_spinlock);
+	dev->gadget.ops = &udc_ops;
+
+	strcpy(dev->gadget.dev.bus_id, "gadget");
+	dev->gadget.dev.release = gadget_release;
+	dev->gadget.name = name;
+	dev->gadget.is_dualspeed = 1;
+
+	/* udc csr registers base */
+	dev->csr = (struct udc_csrs *)(dev->virt_addr + UDC_CSR_ADDR);
+	/* dev registers base */
+	dev->regs = (struct udc_regs *)(dev->virt_addr + UDC_DEVCFG_ADDR);
+	/* ep registers base */
+	dev->ep_regs = (struct udc_ep_regs *)(dev->virt_addr + UDC_EPREGS_ADDR);
+	/* fifo's base */
+	dev->rxfifo = (u32 *) (dev->virt_addr + UDC_RXFIFO_ADDR);
+	dev->txfifo = (u32 *) (dev->virt_addr + UDC_TXFIFO_ADDR);
+
+	/* init registers, interrupts, ... */
+	{
+		u32 tmp;
+
+		dev->gadget.ep0 = &dev->ep[UDC_EP0IN_IX].ep;
+		dev->ep[UDC_EP0IN_IX].halted = 0;
+		INIT_LIST_HEAD(&dev->gadget.ep0->ep_list);
+		dev->gadget.speed = USB_SPEED_HIGH;
+		make_ep_lists(dev);
+		/* basic endpoint init */
+		for (tmp = 0; tmp < UDC_EP_NUM; tmp++) {
+			struct udc_ep   *ep = &dev->ep[tmp];
+
+			ep->ep.name = ep_string[tmp];
+			ep->dev = dev;
+			ep->num = tmp;
+			/* txfifo size is calculated at enable time */
+			ep->txfifo = dev->txfifo;
+
+			/* fifo size */
+			if (tmp < UDC_EPIN_NUM) {
+				ep->fifo_depth = UDC_TXFIFO_SIZE;
+				ep->in = 1;
+			} else {
+				ep->fifo_depth = UDC_RXFIFO_SIZE;
+				ep->in = 0;
+
+			}
+
+			ep->regs = &dev->ep_regs[tmp];
+			if (!ep->desc) {
+				ep->desc = 0;
+				INIT_LIST_HEAD(&ep->queue);
+
+				ep->ep.maxpacket = ~0;
+				ep->ep.ops = &udc_ep_ops;
+			}
+
+			tasklet_init(&ep->execute_tasklet,
+					udc_tasklet_execute_request,
+					(unsigned long)ep);
+					init_MUTEX(&ep->in_use);
+					init_MUTEX(&ep->in_et);
+		}
+		dev->ep[UDC_EP0IN_IX].ep.maxpacket = UDC_EP0IN_MAX_PKT_SIZE;
+		dev->ep[UDC_EP0OUT_IX].ep.maxpacket = UDC_EP0OUT_MAX_PKT_SIZE;
+	}
+
+
+	INFO("%s\n", mod_desc);
+
+	snprintf(tmp, sizeof tmp, "%d", dev->irq);
+	INFO("irq %s, mem %08lx, chip rev %02x (Au1200 %s)\n",
+			tmp, dev->phys_addr, dev->chiprev,
+			(dev->chiprev == 0) ? "AB" : "AC");
+#ifdef CONFIG_DMA_COHERENT
+	/* coherent DMA not possible with AB silicon */
+	if (dev->chiprev == UDC_AUAB_REV) {
+		ERR("Your chip revision is %s, it must be at least %s to use"
+				" coherent DMA. \nPlease change DMA_COHERENT to"
+				" DMA_NONCOHERENT in arch/mips/Kconfig and"
+				" re-compile .\n", "AB", "AC");
+		retval = -ENODEV;
+		goto finished;
+	}
+#endif
+
+#ifdef CONFIG_DMA_COHERENT
+	INFO("Compiled for coherent memory.\n");
+#endif
+#ifdef CONFIG_DMA_NONCOHERENT
+	INFO("Compiled for non-coherent memory.\n");
+#endif
+	udc = dev;
+
+	retval = device_register(&dev->gadget.dev);
+	if (retval) {
+		ERR("Failed to register gadget device\n");
+		goto finished;
+	}
+	device_create_file(&pdev->dev, &dev_attr_registers);
+
+	/* set SD */
+	reg = ioread32(&dev->regs->ctl);
+	reg |= UDC_BIT(UDC_DEVCTL_SD);
+	iowrite32(reg, &dev->regs->ctl);
+	/* print dev register info */
+	print_regs(dev);
+	return 0;
+
+finished:
+	return retval;
+}
+
+
+/**
+ *  Initiates a remote wakeup
+ *
+ * \return 0 if success
+ */
+/* initiate remote wakeup */
+static int udc_remote_wakeup(struct udc *dev)
+{
+	INFO("UDC initiates remote wakeup\n");
+
+	UDC_SET_BIT(UDC_DEVCTL_RES, &dev->regs->ctl);
+	UDC_UNSET_BIT(UDC_DEVCTL_RES, &dev->regs->ctl);
+
+	return 0;
+}
+
+/**
+ *  Suspends UDC
+ */
+static int udc_suspend(struct udc *dev)
+{
+	int retval = 0;
+
+	u32 tmp;
+	INFO("UDC suspend\n");
+	/* mask interrupts */
+	udc_mask_unused_interrupts(dev);
+
+	if (dev->driver && dev->driver->disconnect) {
+		/* call gadget to reset context */
+		if (spin_is_locked(&dev->lock)) {
+			spin_unlock(&dev->lock);
+			dev->driver->disconnect(&dev->gadget);
+			spin_lock(&dev->lock);
+		} else
+			dev->driver->disconnect(&dev->gadget);
+
+		/* disable ep0 to empty req queue */
+		empty_req_queue(&dev->ep[UDC_EP0IN_IX]);
+		ep_init(dev->regs,
+				&dev->ep[UDC_EP0IN_IX]);
+
+		/* init controller by soft reset */
+		udc_soft_reset(dev);
+
+	}
+	if (dev->otg_driver && dev->otg_transceiver
+			&& dev->otg_transceiver->set_peripheral) {
+		/* if UDC is supended by Host or already disconnected then
+		   don't force disconnect by unbind() */
+		if (dev->otg_driver->query) {
+			if (!(dev->otg_driver->query(0) & OTG_FLAGS_UDC_SUSP)) {
+				/* unbind from otg driver -> host disconnect */
+				dev->otg_transceiver->set_peripheral(
+						dev->otg_transceiver, NULL);
+				dev->connected = 0;
+			}
+		} else {
+			/* unbind from otg driver -> host disconnect */
+			dev->otg_transceiver->set_peripheral(
+					dev->otg_transceiver, NULL);
+			dev->connected = 0;
+		}
+	}
+
+	dev->sys_suspended = 1;
+
+	/* switch off UDC clock */
+			tmp = ioread32((u32 *)(USB_MSR_BASE + USB_MSR_MCFG));
+			tmp &= UDC_CLEAR_BIT(USBMSRMCFG_UDCCLKEN);
+			iowrite32(tmp, (u32 *)(USB_MSR_BASE + USB_MSR_MCFG));
+
+	return retval;
+}
+
+static int udc_resume(struct udc *dev)
+{
+	int retval = 0;
+
+	u32 tmp;
+	INFO("UDC resume\n");
+	/* switch on UDC clock */
+	tmp = ioread32((u32 *)(USB_MSR_BASE + USB_MSR_MCFG));
+	tmp |= UDC_BIT(USBMSRMCFG_UDCCLKEN);
+	iowrite32(tmp, (u32 *)(USB_MSR_BASE + USB_MSR_MCFG));
+
+	dev->sys_suspended = 0;
+
+	usb_connect(dev);
+	if (dev->otg_transceiver && dev->otg_transceiver->set_peripheral) {
+		/* bind to otg driver */
+		dev->otg_transceiver->set_peripheral(dev->otg_transceiver,
+						     &dev->gadget);
+	}
+	return retval;
+}
+
+static int udc_au1xxx_drv_probe(struct device *dev)
+{
+	int retval;
+
+	DBG("udc_au1xxx_drv_probe()\n");
+	retval = udc_drv_probe(dev);
+	return retval;
+}
+
+static int udc_au1xxx_drv_remove(struct device *dev)
+{
+	DBG("udc_au1xxx_drv_remove()\n");
+	udc_drv_remove(dev);
+	return 0;
+}
+
+static int udc_au1xxx_drv_suspend(struct device *dev, pm_message_t state)
+{
+	struct udc *udc_dev = dev_get_drvdata(dev);
+	return udc_suspend(udc_dev);
+}
+
+static int udc_au1xxx_drv_resume(struct device *dev)
+{
+	struct udc *udc_dev = dev_get_drvdata(dev);
+	return udc_resume(udc_dev);
+}
+
+static struct device_driver udc_au1xxx_driver = {
+	.name		= "au1xxx-udc",
+	.bus		= &platform_bus_type,
+	.probe		= udc_au1xxx_drv_probe,
+	.remove		= udc_au1xxx_drv_remove,
+	.suspend	= udc_au1xxx_drv_suspend,
+	.resume	    = udc_au1xxx_drv_resume,
+};
+
+
+static int __init init(void)
+{
+	int rc;
+
+	/* probe by device system */
+	rc = driver_register(&udc_au1xxx_driver);
+
+	return rc;
+}
+module_init(init);
+
+static void __exit cleanup(void)
+{
+	/* unregister at device system */
+	driver_unregister(&udc_au1xxx_driver);
+
+}
+module_exit(cleanup);
+
diff --git a/drivers/usb/gadget/au1200_udc.h b/drivers/usb/gadget/au1200_udc.h
new file mode 100644
index 0000000..2a4f7bf
--- /dev/null
+++ b/drivers/usb/gadget/au1200_udc.h
@@ -0,0 +1,816 @@
+/*
+ * Header for driver for RMI Au1200 UDC high/full speed USB device controller
+ */
+/*
+ * Copyright (C) 2008 RMI Corporation (http://www.rmicorp.com)
+ * Author: Kevin Hickey (khickey@rmicorp.com)
+ *
+ * Adapted from the AMD5536 UDC module.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef AU1200UDC_H
+#define AU1200UDC_H
+
+/*****************************************************************************
+ *  Constants
+ *****************************************************************************/
+
+/* Driver  constants -------------------------------------------------------*/
+#define DRIVER_NAME_FOR_PRINT "au1200_udc"
+
+/* Platform specific -------------------------------------------------------*/
+#define UDC_POOL_ALIGN       32
+#define UDC_POOL_CROSS       4096
+#define UDC_POOL_GFP_STP     (GFP_ATOMIC | GFP_DMA)
+
+#ifndef USBMSRMCFG_UCAM
+#define USBMSRMCFG_UCAM           7
+#endif
+#define USBMSRMCFG_DEFAULT        0x00d02000
+
+/* Au1200 rev. */
+#define UDC_AUAB_REV 0
+#define UDC_AUAC_REV 1
+#define UDC_AUA0 0
+
+/* Global CSR's -------------------------------------------------------------*/
+/* UDC CSR's */
+#define UDC_CSR_ADDR                            0x500
+
+/* EP NE bits */
+/* EP number */
+#define UDC_CSR_NE_NUM_MASK                     0x0000000f
+#define UDC_CSR_NE_NUM_OFS                      0
+/* EP direction */
+#define UDC_CSR_NE_DIR_MASK                     0x00000010
+#define UDC_CSR_NE_DIR_OFS                      4
+/* EP type */
+#define UDC_CSR_NE_TYPE_MASK                    0x00000060
+#define UDC_CSR_NE_TYPE_OFS                     5
+/* EP config number */
+#define UDC_CSR_NE_CFG_MASK                     0x00000780
+#define UDC_CSR_NE_CFG_OFS                      7
+/* EP interface number */
+#define UDC_CSR_NE_INTF_MASK                    0x00007800
+#define UDC_CSR_NE_INTF_OFS                     11
+/* EP alt setting */
+#define UDC_CSR_NE_ALT_MASK                     0x00078000
+#define UDC_CSR_NE_ALT_OFS                      15
+
+/* max pkt */
+#define UDC_CSR_NE_MAX_PKT_MASK                 0x3ff80000
+#define UDC_CSR_NE_MAX_PKT_OFS                  19
+
+/* Device Config Register ---------------------------------------------------*/
+#define UDC_DEVCFG_ADDR                         0x400
+
+#define UDC_DEVCFG_SOFTRESET                    31
+#define UDC_DEVCFG_HNPSFEN                      30
+#define UDC_DEVCFG_DMARST                       29
+#define UDC_DEVCFG_SET_DESC                     18
+#define UDC_DEVCFG_CSR_PRG                      17
+#define UDC_DEVCFG_STATUS                       7
+#define UDC_DEVCFG_DIR                          6
+#define UDC_DEVCFG_PI                           5
+#define UDC_DEVCFG_SS                           4
+#define UDC_DEVCFG_SP                           3
+#define UDC_DEVCFG_RWKP                         2
+
+#define UDC_DEVCFG_SPD_MASK                     0x3
+#define UDC_DEVCFG_SPD_OFS                      0
+#define UDC_DEVCFG_SPD_HS                       0x0
+#define UDC_DEVCFG_SPD_FS                       0x1
+#define UDC_DEVCFG_SPD_LS                       0x2
+/*#define UDC_DEVCFG_SPD_FS                     0x3*/
+
+
+/* Device Control Register --------------------------------------------------*/
+#define UDC_DEVCTL_ADDR                         0x404
+
+#define UDC_DEVCTL_THLEN_MASK                   0xff000000
+#define UDC_DEVCTL_THLEN_OFS                    24
+
+#define UDC_DEVCTL_BRLEN_MASK                   0x00ff0000
+#define UDC_DEVCTL_BRLEN_OFS                    16
+
+#define UDC_DEVCTL_CSR_DONE                     13
+#define UDC_DEVCTL_DEVNAK                       12
+#define UDC_DEVCTL_SD                           10
+#define UDC_DEVCTL_MODE                         9
+#define UDC_DEVCTL_BREN                         8
+#define UDC_DEVCTL_THE                          7
+#define UDC_DEVCTL_BF                           6
+#define UDC_DEVCTL_BE                           5
+#define UDC_DEVCTL_DU                           4
+#define UDC_DEVCTL_TDE                          3
+#define UDC_DEVCTL_RDE                          2
+#define UDC_DEVCTL_RES                          0
+
+
+/* Device Status Register ---------------------------------------------------*/
+#define UDC_DEVSTS_ADDR                         0x408
+
+#define UDC_DEVSTS_TS_MASK                      0xfffc0000
+#define UDC_DEVSTS_TS_OFS                       18
+
+#define UDC_DEVSTS_SESSVLD                      17
+#define UDC_DEVSTS_PHY_ERROR                    16
+#define UDC_DEVSTS_RXFIFO_EMPTY                 15
+
+#define UDC_DEVSTS_ENUM_SPEED_MASK              0x00006000
+#define UDC_DEVSTS_ENUM_SPEED_OFS               13
+#define UDC_DEVSTS_ENUM_SPEED_FULL              1
+#define UDC_DEVSTS_ENUM_SPEED_HIGH              0
+
+#define UDC_DEVSTS_SUSP                         12
+
+#define UDC_DEVSTS_ALT_MASK                     0x00000f00
+#define UDC_DEVSTS_ALT_OFS                      8
+
+#define UDC_DEVSTS_INTF_MASK                    0x000000f0
+#define UDC_DEVSTS_INTF_OFS                     4
+
+#define UDC_DEVSTS_CFG_MASK                     0x0000000f
+#define UDC_DEVSTS_CFG_OFS                      0
+
+
+/* Device Interrupt Register ------------------------------------------------*/
+#define UDC_DEVINT_ADDR                         0x40c
+
+#define UDC_DEVINT_ENUM                         6
+#define UDC_DEVINT_SOF                          5
+#define UDC_DEVINT_US                           4
+#define UDC_DEVINT_UR                           3
+#define UDC_DEVINT_ES                           2
+#define UDC_DEVINT_SI                           1
+#define UDC_DEVINT_SC                           0
+
+/* Device Interrupt Mask Register -------------------------------------------*/
+#define UDC_DEVINT_MSK_ADDR                     0x410
+
+#define UDC_DEVINT_MSK                          0x3f
+
+/* Endpoint Interrupt Register ----------------------------------------------*/
+#define UDC_EPINT_ADDR                          0x414
+
+#define UDC_EPINT_OUT_MASK                      0xffff0000
+#define UDC_EPINT_OUT_OFS                       16
+#define UDC_EPINT_IN_MASK                       0x0000ffff
+#define UDC_EPINT_IN_OFS                        0
+
+#define UDC_EPINT_IN_EP0                        0
+#define UDC_EPINT_IN_EP1                        1
+#define UDC_EPINT_IN_EP2                        2
+#define UDC_EPINT_IN_EP3                        3
+#define UDC_EPINT_OUT_EP0                       16
+#define UDC_EPINT_OUT_EP1                       17
+#define UDC_EPINT_OUT_EP2                       18
+#define UDC_EPINT_OUT_EP3                       19
+
+#define UDC_EPINT_EP0_ENABLE_MSK                0x001e001e
+
+/* Endpoint Interrupt Mask Register -----------------------------------------*/
+#define UDC_EPINT_MSK_ADDR                      0x418
+
+#define UDC_EPINT_OUT_MSK_MASK                  0xffff0000
+#define UDC_EPINT_OUT_MSK_OFS                   16
+#define UDC_EPINT_IN_MSK_MASK                   0x0000ffff
+#define UDC_EPINT_IN_MSK_OFS                    0
+
+#define UDC_EPINT_MSK_DISABLE_ALL               (UDC_EPINT_OUT_MASK |\
+						 UDC_EPINT_IN_MASK)
+/* mask non-EP0 endpoints */
+#define UDC_EPDATAINT_MSK_DISABLE               0xfffefffe
+/* mask all dev interrupts */
+#define UDC_DEV_MSK_DISABLE                     0x7f
+
+/* Endpoint-specific CSR's --------------------------------------------------*/
+/* Endpoint Control Registers -----------------------------------------------*/
+#define UDC_EPREGS_ADDR                         0x0
+#define UDC_EPIN_REGS_ADDR                      0x0
+#define UDC_EPOUT_REGS_ADDR                     0x200
+
+#define UDC_EPCTL_ADDR                          0x0
+
+#define UDC_EPCTL_RRDY                          9
+#define UDC_EPCTL_CNAK                          8
+#define UDC_EPCTL_SNAK                          7
+#define UDC_EPCTL_NAK                           6
+
+#define UDC_EPCTL_ET_MASK                       0x00000030
+#define UDC_EPCTL_ET_OFS                        4
+#define UDC_EPCTL_ET_CONTROL                    0
+#define UDC_EPCTL_ET_ISO                        1
+#define UDC_EPCTL_ET_BULK                       2
+#define UDC_EPCTL_ET_INTERRUPT                  3
+
+#define UDC_EPCTL_P                             3
+#define UDC_EPCTL_SN                            2
+#define UDC_EPCTL_F                             1
+#define UDC_EPCTL_S                             0
+
+/* Endpoint Status Registers ------------------------------------------------*/
+#define UDC_EPSTS_ADDR                          0x4
+
+#define UDC_EPSTS_RX_PKT_SIZE_MASK              0x007ff800
+#define UDC_EPSTS_RX_PKT_SIZE_OFS               11
+
+#define UDC_EPSTS_TDC                           10
+#define UDC_EPSTS_HE                            9
+#define UDC_EPSTS_BNA                           7
+#define UDC_EPSTS_IN                            6
+
+#define UDC_EPSTS_OUT_MASK                      0x00000030
+#define UDC_EPSTS_OUT_OFS                       4
+#define UDC_EPSTS_OUT_DATA                      1
+#define UDC_EPSTS_OUT_DATA_CLEAR                0x10
+#define UDC_EPSTS_OUT_SETUP                     2
+#define UDC_EPSTS_OUT_SETUP_CLEAR               0x20
+#define UDC_EPSTS_OUT_CLEAR                     0x30
+
+/* Endpoint Buffer Size IN/ Receive Packet Frame Number OUT  Registers ------*/
+#define UDC_EPIN_BUFF_SIZE_ADDR                 0x8
+#define UDC_EPOUT_FRAME_NUMBER_ADDR             0x8
+
+#define UDC_EPIN_BUFF_SIZE_MASK                 0x0000ffff
+#define UDC_EPIN_BUFF_SIZE_OFS                  0
+/*  EP0in txfifo = 128 bytes*/
+#define UDC_EPIN0_BUFF_SIZE                     32
+/*  EP0in fullspeed txfifo = 128 bytes*/
+#define UDC_FS_EPIN0_BUFF_SIZE                  32
+
+/* fifo size mult = fifo size / max packet */
+#define UDC_EPIN_BUFF_SIZE_MULT                 2
+
+/* EPin data fifo size = 1024 bytes DOUBLE BUFFERING */
+#define UDC_EPIN_BUFF_SIZE                      256
+/* EPin small INT data fifo size = 128 bytes */
+#define UDC_EPIN_SMALLINT_BUFF_SIZE             32
+
+/* EPin fullspeed data fifo size = 128 bytes DOUBLE BUFFERING */
+#define UDC_FS_EPIN_BUFF_SIZE                   32
+
+#define UDC_EPOUT_FRAME_NUMBER_MASK             0x0000ffff
+#define UDC_EPOUT_FRAME_NUMBER_OFS              0
+
+/* Endpoint Buffer Size OUT/Max Packet Size Registers -----------------------*/
+#define UDC_EPOUT_BUFF_SIZE_ADDR                0x0c
+#define UDC_EP_MAX_PKT_SIZE_ADDR                0x0c
+
+#define UDC_EPOUT_BUFF_SIZE_MASK                0xffff0000
+#define UDC_EPOUT_BUFF_SIZE_OFS                 16
+#define UDC_EP_MAX_PKT_SIZE_MASK                0x0000ffff
+#define UDC_EP_MAX_PKT_SIZE_OFS                 0
+/* EP0in max packet size = 64 bytes */
+#define UDC_EP0IN_MAX_PKT_SIZE                  64
+/* EP0out max packet size = 64 bytes */
+#define UDC_EP0OUT_MAX_PKT_SIZE                 64
+/* EP0in fullspeed max packet size = 64 bytes */
+#define UDC_FS_EP0IN_MAX_PKT_SIZE               64
+/* EP0out fullspeed max packet size = 64 bytes */
+#define UDC_FS_EP0OUT_MAX_PKT_SIZE              64
+
+/* Endpoint dma descriptors ------------------------------------------------*/
+/* Setup data */
+/* Status dword */
+#define UDC_DMA_STP_STS_CFG_MASK                0x0fff0000
+#define UDC_DMA_STP_STS_CFG_OFS                 16
+#define UDC_DMA_STP_STS_CFG_ALT_MASK            0x000f0000
+#define UDC_DMA_STP_STS_CFG_ALT_OFS             16
+#define UDC_DMA_STP_STS_CFG_INTF_MASK           0x00f00000
+#define UDC_DMA_STP_STS_CFG_INTF_OFS            20
+#define UDC_DMA_STP_STS_CFG_NUM_MASK            0x0f000000
+#define UDC_DMA_STP_STS_CFG_NUM_OFS             24
+#define UDC_DMA_STP_STS_RX_MASK                 0x30000000
+#define UDC_DMA_STP_STS_RX_OFS                  28
+#define UDC_DMA_STP_STS_BS_MASK                 0xc0000000
+#define UDC_DMA_STP_STS_BS_OFS                  30
+#define UDC_DMA_STP_STS_BS_HOST_READY           0
+#define UDC_DMA_STP_STS_BS_DMA_BUSY             1
+#define UDC_DMA_STP_STS_BS_DMA_DONE             2
+#define UDC_DMA_STP_STS_BS_HOST_BUSY            3
+/* IN data */
+/* Status dword */
+#define UDC_DMA_IN_STS_TXBYTES_MASK            0x0000ffff
+#define UDC_DMA_IN_STS_TXBYTES_OFS             0
+#define UDC_DMA_IN_STS_FRAMENUM_MASK           0x07ff0000
+#define UDC_DMA_IN_STS_FRAMENUM_OFS            0
+#define UDC_DMA_IN_STS_L                       27
+#define UDC_DMA_IN_STS_TX_MASK                 0x30000000
+#define UDC_DMA_IN_STS_TX_OFS                  28
+#define UDC_DMA_IN_STS_BS_MASK                 0xc0000000
+#define UDC_DMA_IN_STS_BS_OFS                  30
+#define UDC_DMA_IN_STS_BS_HOST_READY           0
+#define UDC_DMA_IN_STS_BS_DMA_BUSY             1
+#define UDC_DMA_IN_STS_BS_DMA_DONE             2
+#define UDC_DMA_IN_STS_BS_HOST_BUSY            3
+/* OUT data */
+/* Status dword */
+#define UDC_DMA_OUT_STS_RXBYTES_MASK            0x0000ffff
+#define UDC_DMA_OUT_STS_RXBYTES_OFS             0
+#define UDC_DMA_OUT_STS_FRAMENUM_MASK           0x07ff0000
+#define UDC_DMA_OUT_STS_FRAMENUM_OFS            0
+#define UDC_DMA_OUT_STS_L                       27
+#define UDC_DMA_OUT_STS_RX_MASK                 0x30000000
+#define UDC_DMA_OUT_STS_RX_OFS                  28
+#define UDC_DMA_OUT_STS_BS_MASK                 0xc0000000
+#define UDC_DMA_OUT_STS_BS_OFS                  30
+#define UDC_DMA_OUT_STS_BS_HOST_READY           0
+#define UDC_DMA_OUT_STS_BS_DMA_BUSY             1
+#define UDC_DMA_OUT_STS_BS_DMA_DONE             2
+#define UDC_DMA_OUT_STS_BS_HOST_BUSY            3
+/* other constants */
+/* max ep0in packet */
+#define UDC_EP0IN_MAXPACKET                     1000
+/* max dma packet */
+#define UDC_DMA_MAXPACKET                       65536
+/* DMA buffer len for temp request, should be the same as the upper
+   layer gadget is using */
+#define UDC_DMA_TEMP_BUFFER_LEN                 4096
+/* un-usable DMA address */
+#define DMA_DONT_USE                           (~(dma_addr_t)0)
+
+/* other Endpoint register addresses and values-----------------------------*/
+#define UDC_EP_SUBPTR_ADDR                      0x10
+#define UDC_EP_DESPTR_ADDR                      0x14
+#define UDC_EP_WRITE_CONFIRM_ADDR               0x1c
+
+/* EP number as layouted in AHB space */
+#define UDC_EP_NUM                              32
+#define UDC_EPIN_NUM                            16
+#define UDC_EPIN_NUM_USED                       5
+#define UDC_EPOUT_NUM                           16
+/* EP number of EP's really used = EP0 + 8 data EP's */
+#define UDC_USED_EP_NUM                         9
+/* UDC CSR regs are aligned but AHB regs not - offset for OUT EP's */
+#define UDC_CSR_EP_OUT_IX_OFS                   12
+
+#define UDC_EP0OUT_IX                           16
+#define UDC_EP0IN_IX                            0
+
+/* max packet */
+#define UDC_HS_BULK_MAXPKT                      512
+
+/* Rx fifo address and size = 1k -------------------------------------------*/
+#define UDC_RXFIFO_ADDR                         0x800
+#define UDC_RXFIFO_SIZE                         0x400
+
+/* Tx fifo address and size = 1.5k -----------------------------------------*/
+#define UDC_TXFIFO_ADDR                         0xc00
+#define UDC_TXFIFO_SIZE                         0x600
+
+/* default data endpoints --------------------------------------------------*/
+#define UDC_EPIN_STATUS_IX                      1
+#define UDC_EPIN_IX                             2
+#define UDC_EPOUT_IX                            18
+
+/* general constants -------------------------------------------------------*/
+#define UDC_DWORD_BYTES                         4
+#define UDC_BITS_PER_BYTE_SHIFT                 3
+#define UDC_BYTE_MASK                           0xff
+#define UDC_BITS_PER_BYTE                       8
+
+/* char device constants ---------------------------------------------------*/
+/* names */
+#ifdef UDC_DEBUG
+#ifdef UDC_DRIVER_NAME
+#define UDC_DEVICE_NAME UDC_DRIVER_NAME
+#else
+#define UDC_DEVICE_NAME "amd5536udc"
+#endif
+#define UDC_DEVICE_FILE_NAME "amd5536udc_dev"
+#define UDC_DEVICE_FILE_INODE "/dev/amd5536udc_dev"
+/* major number */
+#define UDC_MAJOR_NUM   240
+#endif
+
+#ifdef __KERNEL__
+/* kernel wrappers */
+#define device_create_file(x, y) do {} while (0)
+#define device_remove_file device_create_file
+
+#ifndef WARN_ON
+#define WARN_ON(a) do {} while (0)
+#endif
+
+#ifndef BUG_ON
+#define BUG_ON(cond)do {if (unlikely((cond) != 0)) BUG(); } while (0)
+#endif
+
+#ifndef likely
+#define likely(a) (a)
+#define unlikely(a) (a)
+#endif
+
+#ifndef container_of
+#define container_of list_entry
+#endif
+
+#endif
+
+/* MIPS specific -----------------------------------------------------------*/
+
+/*****************************************************************************
+ * Includes
+ *****************************************************************************/
+#include "au1200_otg.h"
+
+/*****************************************************************************
+ *  Types
+ *****************************************************************************/
+
+/* UDC CSR's */
+struct udc_csrs {
+
+	/* sca - setup command address */
+	u32 sca;
+
+	/* ep ne's */
+	u32 ne[UDC_USED_EP_NUM];
+} __attribute__ ((packed));
+
+/* AHB subsystem CSR registers */
+struct udc_regs {
+
+	/* device configuration */
+	u32 cfg;
+
+	/* device control */
+	u32 ctl;
+
+	/* device status */
+	u32 sts;
+
+	/* device interrupt */
+	u32 irqsts;
+
+	/* device interrupt mask */
+	u32 irqmsk;
+
+	/* endpoint interrupt  */
+	u32 ep_irqsts;
+
+	/* endpoint interrupt mask */
+	u32 ep_irqmsk;
+} __attribute__ ((packed));
+
+/* endpoint specific registers */
+struct udc_ep_regs {
+
+	/* endpoint control */
+	u32 ctl;
+
+	/* endpoint status */
+	u32 sts;
+
+	/* endpoint buffer size in/ receive packet frame number out  */
+	u32 bufin_framenum;
+
+	/* endpoint buffer size out/max packet size */
+	u32 bufout_maxpkt;
+
+	/* endpoint setup buffer pointer */
+	u32 subptr;
+
+	/* endpoint data descriptor pointer */
+	u32 desptr;
+
+	/* reserverd */
+	u32 reserved;
+
+	/* write/read confirmation */
+	u32 confirm;
+
+}  __attribute__ ((packed));
+
+#ifdef __KERNEL__
+/* control data DMA desc */
+struct udc_stp_dma {
+	/* status quadlet */
+	u32     status;
+	/* reserved */
+	u32     _reserved;
+	/* first setup word */
+	u32     data12;
+	/* second setup word */
+	u32     data34;
+} __attribute__((aligned(16)));
+
+/* normal data DMA desc */
+struct udc_data_dma {
+	/* status quadlet */
+	u32     status;
+	/* reserved */
+	u32     _reserved;
+	/* buffer pointer */
+	u32     bufptr;
+	/* next descriptor pointer */
+	u32     next;
+} __attribute__((aligned(16)));
+
+/* request packet */
+struct udc_request {
+	/* embedded gadget ep */
+	struct usb_request                  req;
+
+	/* flags */
+	unsigned                            dma_going:1,
+					    dma_done : 1;
+	/* phys. address */
+	dma_addr_t                          td_phys;
+	/* first dma desc. of chain */
+	struct udc_data_dma                 *td_data;
+
+	struct list_head                    queue;
+
+	/* chain length */
+	unsigned                            chain_len;
+	int				    serial_number;
+	bool				    ready_for_p_bit;
+
+};
+
+/* UDC specific endpoint parameters */
+struct udc_ep {
+	struct usb_ep                       ep;
+	struct udc_ep_regs                  *regs;
+	u32                                 *txfifo;
+	u32                                 *dma;
+	dma_addr_t                          td_phys;
+	dma_addr_t                          td_stp_dma;
+	struct udc_stp_dma                  *td_stp;
+	struct udc_data_dma                 *td;
+	/* temp request */
+	struct udc_request                  *req;
+	unsigned                            req_used;
+	unsigned                            req_completed;
+
+	/* NAK state */
+	unsigned                            naking;
+	struct tasklet_struct			execute_tasklet;
+	struct semaphore				in_use;
+	struct semaphore				in_et;
+
+	struct udc                          *dev;
+
+	/* queue for requests */
+	struct list_head                        queue;
+	const struct usb_endpoint_descriptor    *desc;
+	unsigned                                halted;
+	unsigned                                num:5,
+						fifo_depth : 14,
+						in : 1;
+};
+
+/* device struct */
+struct udc {
+	struct usb_gadget               gadget;
+	spinlock_t                      lock;
+	/* all endpoints */
+	struct udc_ep                   ep[UDC_EP_NUM];
+	struct usb_gadget_driver        *driver;
+	struct otg_transceiver          *otg_transceiver;
+	struct usb_otg_gadget_extension *otg_driver;
+	/* operational flags */
+	unsigned                        active:1,
+					waiting_zlp_ack_ep0in : 1,
+					set_cfg_not_acked : 1,
+					irq_registered : 1,
+					otg_supported : 1,
+					data_ep_enabled : 1,
+					data_ep_queued : 1,
+					mem_region : 1,
+					selfpowered : 1,
+					sys_suspended : 1,
+					connected;
+
+	u16                             chiprev;
+
+	/* registers */
+	struct device                   *pdev;
+	struct udc_csrs                 *csr;
+	struct udc_regs                 *regs;
+	struct udc_ep_regs              *ep_regs;
+	u32                             *rxfifo;
+	u32                             *txfifo;
+
+	/* DMA desc pools */
+	struct dma_pool                 *data_requests;
+	struct dma_pool                 *stp_requests;
+
+	/* device data */
+	unsigned long                   phys_addr;
+	void                            *virt_addr;
+	unsigned                        irq;
+
+	/* states */
+	u16                             cur_config;
+	u16                             cur_intf;
+	u16                             cur_alt;
+};
+
+/* setup request data */
+union udc_setup_data {
+	u32                        data[2];
+	struct usb_ctrlrequest     request;
+};
+#endif /*__KERNEL__*/
+
+/*****************************************************************************
+ *  Macros
+ *****************************************************************************/
+
+/***************************************
+ * SET and GET bitfields in u32 values
+ * via constants for mask/offset:
+ * <bit_field_stub_name> is the text between
+ * UDC_ and _MASK|_OFS of appropiate
+ * constant
+ ****************************************/
+/* set bitfield value in u32 u32Val */
+#define UDC_ADDBITS(u32Val, bitfield_val, bitfield_stub_name)\
+	(((u32Val) & (((u32) ~((u32) bitfield_stub_name##_MASK))))\
+	 |(((bitfield_val) << ((u32) bitfield_stub_name##_OFS))\
+		 & ((u32) bitfield_stub_name##_MASK)))
+
+/* set bitfield value in zero-initialized u32 u32Val */
+/* => bitfield bits in u32Val are all zero */
+#define UDC_INIT_SETBITS(u32Val, bitfield_val, bitfield_stub_name)\
+	((u32Val)\
+	 |(((bitfield_val) << ((u32) bitfield_stub_name##_OFS))\
+		 &((u32) bitfield_stub_name##_MASK)))
+
+/* get bitfield value from u32 u32Val */
+#define UDC_GETBITS(u32Val, bitfield_stub_name)\
+	((u32Val & ((u32) bitfield_stub_name##_MASK))\
+	 >> ((u32) bitfield_stub_name##_OFS))
+
+/* SET and GET bits in u32 values ------------------------------------------*/
+#define UDC_BIT(bit_stub_name) (1 << bit_stub_name)
+#define UDC_UNMASK_BIT(bit_stub_name) (~UDC_BIT(bit_stub_name))
+#define UDC_CLEAR_BIT(bit_stub_name) (~UDC_BIT(bit_stub_name))
+
+#define UDC_SET_BIT(bit_number, register_address)			\
+	do {								\
+		iowrite32(ioread32((register_address)) | (1 << bit_number),\
+				(register_address));			\
+		au_sync();						\
+	} while (0)
+
+/* Note that this takes a set of bits and does not shift them */
+#define	UDC_SET_BITS(bits_to_set, register_address)			\
+	do {								\
+		iowrite32(ioread32((register_address)) | (bits_to_set),	\
+				(register_address));			\
+		au_sync();						\
+	} while (0)
+
+#define UDC_UNSET_BIT(bit_number, register_address)			\
+	do {								\
+		iowrite32(ioread32((register_address)) & ~(1 << bit_number),\
+				(register_address)); 			\
+		au_sync();						\
+	} while (0)
+
+/* misc --------------------------------------------------------------------*/
+#define        DIR_STRING(bAddress) (((bAddress) & USB_DIR_IN) ? "in" : "out")
+
+/* print macros ------------------------------------------------------------*/
+
+#ifdef UDC_VERBOSE
+#ifndef UDC_DEBUG
+#define UDC_DEBUG
+#endif
+#endif
+
+/**
+ * \brief
+ * Macro for printing information in drivers
+ *
+ * This macro is used for printing kernel messages in driver source code.
+ * It should be used for printing useful information about states and called
+ * functions for normal operation (not for errors and warnings).
+ *
+ * \param fmt is format string for printk
+ * \param args... are arguments given to printk (number depends on <fmt>)
+ * \return code from printk
+ */
+#define INFO(args...) \
+	printk(KERN_INFO DRIVER_NAME_FOR_PRINT ": " args)
+
+/**
+ * \brief
+ * Macro for printing warnings in drivers
+ *
+ * This macro is used for printing kernel messages in driver source code.
+ * It should be used for printing warnings.
+ *
+ * \param fmt is format string for printk
+ * \param args... are arguments given to printk (number depends on <fmt>)
+ * \return code from printk
+ */
+#ifdef WARN
+#undef WARN
+#endif
+#define WARN(args...) \
+	printk(KERN_WARNING DRIVER_NAME_FOR_PRINT " warning: " args)
+
+/**
+ * \brief
+ * Macro for printing errors in drivers
+ *
+ * This macro is used for printing kernel messages in driver source code.
+ * It should be used for printing errors.
+ *
+ * \param fmt is format string for printk
+ * \param args... are arguments given to printk (number depends on <fmt>)
+ * \return code from printk
+ */
+#define ERR(args...) \
+	printk(KERN_ERR DRIVER_NAME_FOR_PRINT " error: " args)
+
+/**
+ * \brief
+ * Macro for printing debug messages in drivers
+ *
+ * This macro is used for printing kernel messages in driver source code
+ * when UDC_DEBUG is defined
+ * It should be used for printing debug messages.
+ *
+ * \param fmt is format string for printk
+ * \param args... are arguments given to printk (number depends on <fmt>)
+ * \return code from printk
+ */
+#ifdef UDC_DEBUG
+#define DBG(args...) \
+	printk(KERN_DEBUG DRIVER_NAME_FOR_PRINT " debug: " args)
+#else
+
+#define DBG(args...) \
+	do {} while (0)
+#endif
+
+/**
+ * \brief
+ * Macro for printing verbose debug messages in drivers
+ *
+ * This macro is used for printing kernel messages in driver source code
+ * when UDC_DEBUG and UDC_VERBOSE is defined
+ * It should be used for printing debug messages.
+ *
+ * \param fmt is format string for printk
+ * \param args... are arguments given to printk (number depends on <fmt>)
+ * \return code from printk
+ */
+#ifdef UDC_VERBOSE
+#define VDBG DBG
+#else
+#define VDBG(args...) \
+	do {} while (0)
+#endif
+
+/*****************************************************************************
+ *  Data
+ *****************************************************************************/
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+#ifdef __cplusplus
+} /* extern "C" */
+#endif
+
+/*****************************************************************************
+ *  Functions
+ *****************************************************************************/
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+
+#ifdef __cplusplus
+} /* extern "C" */
+#endif
+
+/*****************************************************************************
+ *  Inline Functions
+ *****************************************************************************/
+
+#endif /* #ifdef  AU1200UDC_H */
diff --git a/drivers/usb/gadget/au1200_uoc.h b/drivers/usb/gadget/au1200_uoc.h
new file mode 100644
index 0000000..569668a
--- /dev/null
+++ b/drivers/usb/gadget/au1200_uoc.h
@@ -0,0 +1,1021 @@
+/*
+ * Declarations and macros for the Au1200 On The Go port driver.
+ */
+
+/*
+ * Copyright (C) 2008 RMI Corporation (http://www.rmicorp.com)
+ * Author: Kevin Hickey (khickey@rmicorp.com)
+ *
+ * Adapted from earlier work by Karsten Boge
+ *
+ * THIS SOFTWARE IS PROVIDED BY RMI Corporation 'AS IS' AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO
+ * EVENT SHALL RMI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef AU1200_UOC_H
+#define AU1200_UOC_H
+
+
+/*****************************************************************************
+*  Config options
+*****************************************************************************/
+#ifdef VERBOSE
+#ifndef DEBUG
+#define DEBUG
+#endif
+#endif
+
+
+/*****************************************************************************
+*  Constants
+*****************************************************************************/
+
+#define OTG_DRIVER_NAME        "au1200_otg"
+#define OTG_FLAGS_ACTIV        (1<<19)   /* full OTG functionality is activ  */
+
+/**********************************
+*  Register definitions
+**********************************/
+/* capabilities */
+#define OTG_CAP_APU            (1<<15)   /* automatic pull-up enable         */
+
+/* multiplexer */
+#define OTG_MUX_DISABLE_ALL    0         /* not assigned                     */
+#define OTG_MUX_ENABLE_UHC     (2<<0)    /* assigned to host                 */
+#define OTG_MUX_ENABLE_UDC     (3<<0)    /* assigned to device               */
+#define OTG_MUX_PUEN           (1<<2)    /* pull-up enable                   */
+#define OTG_MUX_VBUSVLD        (1<<8)    /* VBus valid                       */
+
+/* status */
+#define OTG_STS_ID             (1<<0)    /* ID pin status                    */
+#define OTG_STS_VBUSVLD        (1<<1)    /* VBus valid                       */
+#define OTG_STS_SESSVLD        (1<<2)    /* Session valid                    */
+#define OTG_STS_SESSEND        (1<<3)    /* Session end                      */
+#define OTG_STS_LST            (3<<4)    /* Line state                       */
+#define OTG_STS_LST_J          (1<<4)    /* Line state                       */
+#define OTG_STS_LST_K          (2<<4)    /* Line state                       */
+#define OTG_STS_PSPD           (3<<6)    /* Port speed                       */
+#define OTG_STS_PSPD_LS        (1<<7)    /* Port speed                       */
+#define OTG_STS_PSPD_FS        (2<<7)    /* Port speed                       */
+#define OTG_STS_FSOE           (1<<8)    /* FS output enable (OHC)           */
+#define OTG_STS_PCON           (1<<9)    /* Port connected                   */
+#define OTG_STS_PSUS           (1<<10)   /* Port suspended                   */
+#define OTG_STS_TMH            (1<<11)   /* Timer halted                     */
+#define OTG_STS_HNP_EN         (1<<12)   /* HNP enabled for B-dev            */
+#define OTG_STS_HNP_SUPP       (1<<13)   /* A-host supports HNP              */
+#define OTG_STS_HNP_ALTSUPP    (1<<14)   /* A-host supports alt. HNP         */
+#define OTG_STS_HNPSTS         (OTG_STS_HNP_EN | OTG_STS_HNP_SUPP | \
+		OTG_STS_HNP_ALTSUPP)
+#define OTG_STS_OC             (1<<15)   /* over-current                     */
+#define OTG_STS_DPR            (1<<16)   /* Downstream port reset            */
+
+/* control */
+#define OTG_CTL_DISABLE_ALL    0         /* not assigned                     */
+#define OTG_CTL_ENABLE_UHC     (2<<0)    /* assigned to host                 */
+#define OTG_CTL_ENABLE_UDC     (3<<0)    /* assigned to device               */
+#define OTG_CTL_MUX_MASK       (3<<0)    /* port mux mask                    */
+#define OTG_CTL_PPWR           (1<<2)    /* port power switch                */
+#define OTG_CTL_PPO            (1<<3)    /* port power override              */
+#define OTG_CTL_CHRG           (1<<4)    /* charge VBus                      */
+#define OTG_CTL_DISCHRG        (1<<5)    /* discharge VBus                   */
+#define OTG_CTL_IDSNSEN        (1<<6)    /* ID sense enable, ID-PU           */
+#define OTG_CTL_PADEN          (1<<7)
+#define OTG_CTL_PUEN           (1<<8)    /* pull-up enable                   */
+#define OTG_CTL_DMPDEN         (1<<9)    /* pull-down enable                 */
+#define OTG_CTL_HNPSFEN        (1<<10)   /* HNP SET_FEATURE enable           */
+#define OTG_CTL_WPCS_DEAS      (2<<16)   /* deassert port connect            */
+#define OTG_CTL_WPCS_ASRT      (3<<16)   /* assert port connect              */
+#define OTG_CTL_WPSS_DEAS      (2<<18)   /* deassert port suspend            */
+#define OTG_CTL_WPSS_ASRT      (3<<18)   /* assert port suspend              */
+/* timer conditions */
+#define OTG_CTL_TMR_RLP        (1<<28)   /* timer reload policy              */
+#define OTG_CTL_TMR_ALL        (0xf<<24) /* stop timer                       */
+#define OTG_CTL_TMR_STOP       0         /* timer disabled                   */
+#define OTG_CTL_TMR_UNCOND     (1<<24)   /* count unconditionally            */
+#define OTG_CTL_TMR_SE0        (2<<24)   /* count if LSt = FS-SE0            */
+#define OTG_CTL_TMR_FSJ        (3<<24)   /* count if LSt = FS-J              */
+#define OTG_CTL_TMR_FSK        (4<<24)   /* count if LSt = FS-K              */
+#define OTG_CTL_TMR_NOSE0      (5<<24)   /* count if LSt <> FS-SE0           */
+#define OTG_CTL_TMR_NORX       (6<<24)   /* count if Rx inactiv              */
+#define OTG_CTL_TMR_ID         (7<<24)   /* count if ID = 0                  */
+
+/* interrupts */
+#define OTG_INT_GLOBAL         (1<<31)   /* global interrupt enable          */
+#define OTG_INT_ENALL          0x7fff    /* enable all                       */
+#define OTG_INT_DISALL         0         /* disable all                      */
+#define OTG_INT_IDC            (1<<0)    /* ID pin change                    */
+#define OTG_INT_VBVC           (1<<1)    /* VBUS valid change                */
+#define OTG_INT_SVC            (1<<2)    /* Session valid change             */
+#define OTG_INT_SEC            (1<<3)    /* Session end change               */
+#define OTG_INT_LSTC           (1<<4)    /* Line state change                */
+#define OTG_INT_PSPDC          (1<<5)    /* Port speed change                */
+#define OTG_INT_FSOEC          (1<<6)    /* FS/LS OE change                  */
+#define OTG_INT_HSDD           (1<<7)    /* HS disconnect detected           */
+#define OTG_INT_RXACT          (1<<8)    /* Rx activity detected             */
+#define OTG_INT_PCC            (1<<9)    /* Port connect change              */
+#define OTG_INT_PSC            (1<<10)   /* Port suspend change              */
+#define OTG_INT_TMX            (1<<11)   /* Timer expired                    */
+#define OTG_INT_HNPFC          (1<<12)   /* HNP feature change               */
+#define OTG_INT_OCD            (1<<13)   /* over current detected            */
+#define OTG_INT_DPRC           (1<<14)   /* Downstream port reset change     */
+
+#define OTG_INT_ADDS   OTG_INT_SVC
+
+/**********************************
+ *  OTG state dependend data
+ **********************************/
+
+/*
+ * generic
+ */
+#define OTG_CTL_DEFAULT                      (OTG_CTL_PADEN | \
+		OTG_CTL_IDSNSEN)
+#define OTG_CTL_HOST_DEFAULT                 (OTG_CTL_DEFAULT | \
+		OTG_CTL_ENABLE_UHC)
+#ifdef CONFIG_USB_OTG
+#define OTG_CTL_PERIPHERAL_DEFAULT           (OTG_CTL_DEFAULT | \
+		OTG_CTL_HNPSFEN | \
+		OTG_CTL_ENABLE_UDC | \
+		OTG_CTL_PPO | OTG_CTL_PUEN)
+#else
+#define OTG_CTL_PERIPHERAL_DEFAULT           (OTG_CTL_DEFAULT | \
+		OTG_CTL_ENABLE_UDC | \
+		OTG_CTL_PPO | OTG_CTL_PUEN)
+#endif
+
+#define OTG_INT_DEFAULT                      OTG_INT_IDC
+
+/*
+ * OTG_STATE_UNDEFINED
+ */
+#define OTG_STATE_UNDEFINED_CONTROL          (OTG_CTL_DEFAULT | OTG_CTL_PPO | \
+		OTG_CTL_TMR_UNCOND)
+#define OTG_STATE_UNDEFINED_STATUS           0
+#define OTG_STATE_UNDEFINED_STATUS_MASK      0
+#define OTG_STATE_UNDEFINED_INTERRUPTS       OTG_INT_TMX
+
+/*
+ * OTG_STATE_NO_B_DEVICE_A
+ */
+#define OTG_STATE_NO_B_DEVICE_A_CONTROL      OTG_CTL_HOST_DEFAULT
+#define OTG_STATE_NO_B_DEVICE_A_STATUS       0
+#define OTG_STATE_NO_B_DEVICE_A_STATUS_MASK  0
+#define OTG_STATE_NO_B_DEVICE_A_INTERRUPTS   OTG_INT_DEFAULT
+
+/*
+ * OTG_STATE_NO_B_DEVICE_B
+ */
+#define OTG_STATE_NO_B_DEVICE_B_CONTROL      (OTG_CTL_DEFAULT | OTG_CTL_PPO)
+#define OTG_STATE_NO_B_DEVICE_B_STATUS       0
+#define OTG_STATE_NO_B_DEVICE_B_STATUS_MASK  0
+#define OTG_STATE_NO_B_DEVICE_B_INTERRUPTS   OTG_INT_DEFAULT
+
+/*
+ * OTG_STATE_A_IDLE
+ */
+#define OTG_STATE_A_IDLE_CONTROL             (OTG_CTL_DEFAULT | OTG_CTL_PPO)
+#define OTG_STATE_A_IDLE_STATUS              0
+#define OTG_STATE_A_IDLE_STATUS_MASK         0
+#define OTG_STATE_A_IDLE_INTERRUPTS          (OTG_INT_DEFAULT | OTG_INT_SVC | \
+		OTG_INT_LSTC)
+
+/*
+ * OTG_STATE_A_IDLE_WAIT_DP
+ */
+#define OTG_STATE_A_IDLE_WAIT_DP_CONTROL     (OTG_STATE_A_IDLE_CONTROL | \
+		OTG_CTL_TMR_UNCOND)
+#define OTG_STATE_A_IDLE_WAIT_DP_STATUS      0
+#define OTG_STATE_A_IDLE_WAIT_DP_STATUS_MASK 0
+#define OTG_STATE_A_IDLE_WAIT_DP_INTERRUPTS  (OTG_STATE_A_IDLE_INTERRUPTS | \
+		OTG_INT_TMX)
+
+/*
+ * OTG_STATE_A_IDLE_WAIT_VP
+ */
+#define OTG_STATE_A_IDLE_WAIT_VP_CONTROL     (OTG_STATE_A_IDLE_CONTROL | \
+		OTG_CTL_TMR_UNCOND)
+#define OTG_STATE_A_IDLE_WAIT_VP_STATUS      0
+#define OTG_STATE_A_IDLE_WAIT_VP_STATUS_MASK 0
+#define OTG_STATE_A_IDLE_WAIT_VP_INTERRUPTS  (OTG_STATE_A_IDLE_INTERRUPTS | \
+		OTG_INT_TMX)
+
+/*
+ * OTG_STATE_A_IDLE_WAIT_MP
+ */
+#define OTG_STATE_A_IDLE_WAIT_MP_CONTROL     (OTG_STATE_A_IDLE_CONTROL | \
+		OTG_CTL_TMR_UNCOND)
+#define OTG_STATE_A_IDLE_WAIT_MP_STATUS      0
+#define OTG_STATE_A_IDLE_WAIT_MP_STATUS_MASK 0
+#define OTG_STATE_A_IDLE_WAIT_MP_INTERRUPTS  (OTG_STATE_A_IDLE_INTERRUPTS | \
+		OTG_INT_TMX)
+
+/*
+ * OTG_STATE_A_IDLE_WAIT_DV
+ */
+#define OTG_STATE_A_IDLE_WAIT_DV_CONTROL     (OTG_STATE_A_IDLE_CONTROL | \
+		OTG_CTL_TMR_UNCOND)
+#define OTG_STATE_A_IDLE_WAIT_DV_STATUS      0
+#define OTG_STATE_A_IDLE_WAIT_DV_STATUS_MASK 0
+#define OTG_STATE_A_IDLE_WAIT_DV_INTERRUPTS  (OTG_STATE_A_IDLE_INTERRUPTS | \
+		OTG_INT_TMX)
+
+/*
+ * OTG_STATE_A_WAIT_VRISE
+ */
+#define OTG_STATE_A_WAIT_VRISE_CONTROL       (OTG_CTL_HOST_DEFAULT | \
+		OTG_CTL_TMR_UNCOND)
+#define OTG_STATE_A_WAIT_VRISE_STATUS        0
+#define OTG_STATE_A_WAIT_VRISE_STATUS_MASK   0
+#define OTG_STATE_A_WAIT_VRISE_INTERRUPTS    (OTG_INT_DEFAULT | OTG_INT_TMX | \
+		OTG_INT_VBVC)
+
+/*
+ * OTG_STATE_A_WAIT_BCON
+ */
+#define OTG_STATE_A_WAIT_BCON_CONTROL        OTG_CTL_HOST_DEFAULT
+#define OTG_STATE_A_WAIT_BCON_STATUS         0
+#define OTG_STATE_A_WAIT_BCON_STATUS_MASK    0
+#define OTG_STATE_A_WAIT_BCON_INTERRUPTS     (OTG_INT_DEFAULT | OTG_INT_TMX | \
+		OTG_INT_VBVC | OTG_INT_PCC)
+
+/*
+ * OTG_STATE_A_WAIT_BCON_VB
+ */
+#define OTG_STATE_A_WAIT_BCON_VB_CONTROL     (OTG_STATE_A_WAIT_BCON_CONTROL | \
+		OTG_CTL_TMR_UNCOND)
+#define OTG_STATE_A_WAIT_BCON_VB_STATUS      0
+#define OTG_STATE_A_WAIT_BCON_VB_STATUS_MASK 0
+#define OTG_STATE_A_WAIT_BCON_VB_INTERRUPTS  OTG_STATE_A_WAIT_BCON_INTERRUPTS
+
+/*
+ * OTG_STATE_A_HOST
+ */
+#define OTG_STATE_A_HOST_CONTROL             OTG_CTL_HOST_DEFAULT
+#define OTG_STATE_A_HOST_STATUS              0
+#define OTG_STATE_A_HOST_STATUS_MASK         0
+#ifdef CONFIG_USB_OTG
+#ifndef VERBOSE
+#define OTG_STATE_A_HOST_INTERRUPTS          (OTG_INT_DEFAULT | \
+		OTG_INT_VBVC | OTG_INT_DPRC | \
+		OTG_INT_PCC | OTG_INT_PSC)
+#else
+#define OTG_STATE_A_HOST_INTERRUPTS          (OTG_INT_DEFAULT | \
+		OTG_INT_VBVC | OTG_INT_DPRC | \
+		OTG_INT_PCC | OTG_INT_PSC | \
+		OTG_INT_PSPDC)
+/* OTG_INT_LSTC */
+#endif
+#else
+/* IDPIN mode only                                                   */
+#define OTG_STATE_A_HOST_INTERRUPTS          OTG_INT_IDC
+#endif
+
+/*
+ * OTG_STATE_A_SUSPEND
+ */
+#define OTG_STATE_A_SUSPEND_CONTROL          (OTG_CTL_HOST_DEFAULT | \
+		OTG_CTL_TMR_UNCOND)
+#define OTG_STATE_A_SUSPEND_STATUS           0
+#define OTG_STATE_A_SUSPEND_STATUS_MASK      0
+#define OTG_STATE_A_SUSPEND_INTERRUPTS       (OTG_INT_DEFAULT | OTG_INT_TMX | \
+		OTG_INT_VBVC |  OTG_INT_DPRC | \
+		OTG_INT_PCC | OTG_INT_PSC)
+
+/*
+ * OTG_STATE_A_PERIPHERAL
+ */
+#define OTG_STATE_A_PERIPHERAL_CONTROL       (OTG_CTL_PERIPHERAL_DEFAULT | \
+		OTG_CTL_PPWR | OTG_CTL_DMPDEN)
+#define OTG_STATE_A_PERIPHERAL_STATUS        0
+#define OTG_STATE_A_PERIPHERAL_STATUS_MASK   0
+#ifndef VERBOSE
+#define OTG_STATE_A_PERIPHERAL_INTERRUPTS    (OTG_INT_DEFAULT | \
+		OTG_INT_VBVC | OTG_INT_OCD | \
+		OTG_INT_PCC | OTG_INT_PSC)
+#else
+#define OTG_STATE_A_PERIPHERAL_INTERRUPTS    (OTG_INT_DEFAULT | \
+		OTG_INT_VBVC | OTG_INT_OCD | \
+		OTG_INT_PCC | OTG_INT_PSC | \
+		OTG_INT_PSPDC)
+/* OTG_INT_LSTC */
+#endif
+
+/*
+ * OTG_STATE_A_VBUS_ERR
+ */
+#define OTG_STATE_A_VBUS_ERR_CONTROL         (OTG_CTL_HOST_DEFAULT | \
+		OTG_CTL_PPO | OTG_CTL_DISCHRG)
+#define OTG_STATE_A_VBUS_ERR_STATUS          0
+#define OTG_STATE_A_VBUS_ERR_STATUS_MASK     0
+#define OTG_STATE_A_VBUS_ERR_INTERRUPTS      OTG_INT_DEFAULT
+
+/*
+ * OTG_STATE_A_WAIT_VFALL
+ */
+#define OTG_STATE_A_WAIT_VFALL_CONTROL       (OTG_CTL_HOST_DEFAULT | \
+		OTG_CTL_PPO)
+#define OTG_STATE_A_WAIT_VFALL_STATUS        0
+#define OTG_STATE_A_WAIT_VFALL_STATUS_MASK   0
+#define OTG_STATE_A_WAIT_VFALL_INTERRUPTS    (OTG_INT_DEFAULT | OTG_INT_SEC)
+
+/*
+ * OTG_STATE_A_WAIT_VFALL_DN
+ */
+#define OTG_STATE_A_WAIT_VFALL_DN_CONTROL    (OTG_STATE_A_WAIT_VFALL_CONTROL | \
+		OTG_CTL_DISCHRG)
+#define OTG_STATE_A_WAIT_VFALL_DN_STATUS      0
+#define OTG_STATE_A_WAIT_VFALL_DN_STATUS_MASK 0
+#define OTG_STATE_A_WAIT_VFALL_DN_INTERRUPTS  OTG_STATE_A_WAIT_VFALL_INTERRUPTS
+
+/*
+ * OTG_STATE_A_WAIT_BDISCON
+ */
+#define OTG_STATE_A_WAIT_BDISCON_CONTROL     (OTG_CTL_DEFAULT | \
+		OTG_CTL_PPO | OTG_CTL_PPWR | \
+		OTG_CTL_TMR_UNCOND)
+#define OTG_STATE_A_WAIT_BDISCON_STATUS      0
+#define OTG_STATE_A_WAIT_BDISCON_STATUS_MASK 0
+#define OTG_STATE_A_WAIT_BDISCON_INTERRUPTS  (OTG_INT_DEFAULT | OTG_INT_TMX | \
+		OTG_INT_VBVC | OTG_INT_OCD | \
+		OTG_INT_PSPDC | OTG_INT_LSTC)
+
+/*
+ * OTG_STATE_B_IDLE
+ */
+/*** HS-A0 WA: BUG-3885: VB_SESS_VLD value too high                        ***/
+/*** HS-A0 WA: BUG-3943: gadget suspend issue                              ***/
+#define OTG_STATE_B_IDLE_CONTROL             (OTG_CTL_PERIPHERAL_DEFAULT & \
+		~((u32) (OTG_CTL_PUEN | \
+				OTG_CTL_ENABLE_UDC)))
+#define OTG_STATE_B_IDLE_STATUS              0
+#define OTG_STATE_B_IDLE_STATUS_MASK         0
+#ifdef CONFIG_USB_OTG
+#define OTG_STATE_B_IDLE_INTERRUPTS          (OTG_INT_DEFAULT | OTG_INT_SVC)
+#else
+#ifdef CONFIG_USB_OTGMUX_IDPIN
+/* IDPIN mode                                                        */
+#define OTG_STATE_B_IDLE_INTERRUPTS          (OTG_INT_IDC | OTG_INT_SVC)
+#else
+/* gadget mode                                                       */
+#define OTG_STATE_B_IDLE_INTERRUPTS          OTG_INT_SVC
+#endif
+#endif
+
+/*
+ * OTG_STATE_B_PERIPHERAL
+ */
+#define OTG_STATE_B_PERIPHERAL_CONTROL       (OTG_CTL_PERIPHERAL_DEFAULT | \
+		OTG_CTL_DMPDEN)
+#define OTG_STATE_B_PERIPHERAL_STATUS        0
+#define OTG_STATE_B_PERIPHERAL_STATUS_MASK   0
+#ifdef CONFIG_USB_OTG
+#ifndef VERBOSE
+#define OTG_STATE_B_PERIPHERAL_INTERRUPTS    (OTG_INT_DEFAULT | OTG_INT_SVC | \
+		OTG_INT_PCC | OTG_INT_PSC | \
+		OTG_INT_HNPFC)
+#else
+#define OTG_STATE_B_PERIPHERAL_INTERRUPTS    (OTG_INT_DEFAULT | OTG_INT_SVC | \
+		OTG_INT_PCC | OTG_INT_PSC | \
+		OTG_INT_HNPFC | OTG_INT_PSPDC)
+/* OTG_INT_LSTC */
+#endif
+#else
+#ifdef CONFIG_USB_OTGMUX_IDPIN
+/* IDPIN mode                                                        */
+#define OTG_STATE_B_PERIPHERAL_INTERRUPTS    (OTG_INT_IDC | OTG_INT_SVC)
+#else
+/* gadget mode                                                       */
+#define OTG_STATE_B_PERIPHERAL_INTERRUPTS    OTG_INT_SVC
+#endif
+#endif
+
+/*
+ * OTG_STATE_B_PERIPHERAL_WT
+ */
+#define OTG_STATE_B_PERIPHERAL_WT_CONTROL    (OTG_STATE_B_PERIPHERAL_CONTROL | \
+		OTG_CTL_PPO | OTG_CTL_TMR_UNCOND)
+#define OTG_STATE_B_PERIPHERAL_WT_STATUS      0
+#define OTG_STATE_B_PERIPHERAL_WT_STATUS_MASK 0
+#define OTG_STATE_B_PERIPHERAL_WT_INTERRUPTS (OTG_STATE_B_PERIPHERAL_INTERRUPTS\
+		| OTG_INT_TMX)
+
+/*
+ * OTG_STATE_B_PERIPHERAL_DC
+ */
+#define OTG_STATE_B_PERIPHERAL_DC_CONTROL    (OTG_CTL_HOST_DEFAULT | \
+		OTG_CTL_PPO | OTG_CTL_DMPDEN | \
+		OTG_CTL_TMR_UNCOND)
+#define OTG_STATE_B_PERIPHERAL_DC_STATUS      0
+#define OTG_STATE_B_PERIPHERAL_DC_STATUS_MASK 0
+#define OTG_STATE_B_PERIPHERAL_DC_INTERRUPTS (OTG_STATE_B_PERIPHERAL_INTERRUPTS\
+		| OTG_INT_TMX | OTG_INT_LSTC)
+
+/*
+ * OTG_STATE_B_WAIT_ACON
+ */
+#define OTG_STATE_B_WAIT_ACON_CONTROL        (OTG_CTL_HOST_DEFAULT | \
+		OTG_CTL_PPO | OTG_CTL_TMR_UNCOND)
+#define OTG_STATE_B_WAIT_ACON_STATUS         0
+#define OTG_STATE_B_WAIT_ACON_STATUS_MASK    0
+#define OTG_STATE_B_WAIT_ACON_INTERRUPTS     (OTG_INT_DEFAULT | OTG_INT_SVC | \
+		OTG_INT_PCC | OTG_INT_PSC | \
+		OTG_INT_HNPFC | OTG_INT_TMX)
+
+/*
+ * OTG_STATE_B_HOST
+ */
+#define OTG_STATE_B_HOST_CONTROL             (OTG_CTL_HOST_DEFAULT | \
+		OTG_CTL_PPO)
+#define OTG_STATE_B_HOST_STATUS              0
+#define OTG_STATE_B_HOST_STATUS_MASK         0
+#define OTG_STATE_B_HOST_INTERRUPTS          (OTG_INT_DEFAULT | OTG_INT_SVC | \
+		OTG_INT_PCC | OTG_INT_SVC | \
+		OTG_INT_PSPDC)
+
+/*
+ * OTG_STATE_B_HOST_WT
+ */
+#define OTG_STATE_B_HOST_WT_CONTROL          (OTG_STATE_B_HOST_CONTROL | \
+		OTG_CTL_TMR_UNCOND)
+#define OTG_STATE_B_HOST_WT_STATUS           0
+#define OTG_STATE_B_HOST_WT_STATUS_MASK      0
+#define OTG_STATE_B_HOST_WT_INTERRUPTS       (OTG_INT_DEFAULT | OTG_INT_SVC | \
+		OTG_INT_PCC | OTG_INT_TMX)
+
+/*
+ * OTG_STATE_B_SRP_INIT
+ */
+#define OTG_STATE_B_SRP_INIT_CONTROL         OTG_STATE_B_IDLE_CONTROL
+#define OTG_STATE_B_SRP_INIT_STATUS          0
+#define OTG_STATE_B_SRP_INIT_STATUS_MASK     0
+#define OTG_STATE_B_SRP_INIT_INTERRUPTS      OTG_INT_DEFAULT
+
+/*
+ * OTG_STATE_B_SRP_WTSE0
+ */
+#define OTG_STATE_B_SRP_WAIT_SE0_CONTROL     (OTG_STATE_B_SRP_INIT_CONTROL | \
+		OTG_CTL_TMR_UNCOND)
+#define OTG_STATE_B_SRP_WAIT_SE0_STATUS      0
+#define OTG_STATE_B_SRP_WAIT_SE0_STATUS_MASK 0
+#define OTG_STATE_B_SRP_WAIT_SE0_INTERRUPTS  (OTG_STATE_B_SRP_INIT_INTERRUPTS \
+		| OTG_INT_TMX | OTG_INT_LSTC)
+
+/*
+ * OTG_STATE_B_SRP_D_PLS
+ *
+ * note: changing to this state requires an additional call:
+ *       set_srp_conditions (dev);
+ *       reset_srp_conditions (dev) is required for the next state
+ */
+#define OTG_STATE_B_SRP_D_PULSE_CONTROL      (OTG_CTL_PERIPHERAL_DEFAULT | \
+		OTG_CTL_PUEN | \
+		OTG_CTL_TMR_UNCOND)
+#define OTG_STATE_B_SRP_D_PULSE_STATUS       0
+#define OTG_STATE_B_SRP_D_PULSE_STATUS_MASK  0
+#define OTG_STATE_B_SRP_D_PULSE_INTERRUPTS   (OTG_STATE_B_SRP_INIT_INTERRUPTS \
+		| OTG_INT_SEC | OTG_INT_TMX)
+
+/*
+ * OTG_STATE_B_SRP_V_PLS
+ */
+#define OTG_STATE_B_SRP_V_PULSE_CONTROL      (OTG_STATE_B_SRP_INIT_CONTROL | \
+		OTG_CTL_CHRG | \
+		OTG_CTL_TMR_UNCOND)
+#define OTG_STATE_B_SRP_V_PULSE_STATUS       0
+#define OTG_STATE_B_SRP_V_PULSE_STATUS_MASK  0
+#define OTG_STATE_B_SRP_V_PULSE_INTERRUPTS   (OTG_STATE_B_SRP_INIT_INTERRUPTS \
+		| OTG_INT_TMX)
+
+/*
+ * OTG_STATE_B_SRP_V_DCG
+ */
+#define OTG_STATE_B_SRP_V_DCHRG_CONTROL      (OTG_STATE_B_SRP_INIT_CONTROL | \
+		OTG_CTL_DISCHRG | \
+		OTG_CTL_TMR_UNCOND)
+#define OTG_STATE_B_SRP_V_DCHRG_STATUS       0
+#define OTG_STATE_B_SRP_V_DCHRG_STATUS_MASK  0
+#define OTG_STATE_B_SRP_V_DCHRG_INTERRUPTS   (OTG_STATE_B_SRP_INIT_INTERRUPTS \
+		| OTG_INT_TMX)
+
+/*
+ * OTG_STATE_B_SRP_WTVB
+ */
+#define OTG_STATE_B_SRP_WAIT_VBUS_CONTROL    (OTG_STATE_B_SRP_INIT_CONTROL | \
+		OTG_CTL_TMR_UNCOND)
+#define OTG_STATE_B_SRP_WAIT_VBUS_STATUS      0
+#define OTG_STATE_B_SRP_WAIT_VBUS_STATUS_MASK 0
+#define OTG_STATE_B_SRP_WAIT_VBUS_INTERRUPTS (OTG_STATE_B_SRP_INIT_INTERRUPTS \
+		| OTG_INT_SVC | OTG_INT_TMX)
+
+/*********************************/
+
+/* other */
+
+#define OTG_APP_REQ_ACK        0
+
+
+/*****************************************************************************
+*  Types
+*****************************************************************************/
+
+
+/*****************************************************************************
+*  Macros
+*****************************************************************************/
+
+/* printing messages */
+
+#define INFO(args...) \
+	printk(KERN_INFO DRIVER_NAME_FOR_PRINT ": " args)
+
+#ifdef WARN
+#undef WARN
+#endif
+
+#define WARN(args...) \
+	printk(KERN_WARNING DRIVER_NAME_FOR_PRINT " warning: " args)
+
+#define ERR(args...) \
+	printk(KERN_ERR DRIVER_NAME_FOR_PRINT " error: " args)
+
+#ifdef DEBUG
+#define DBG(args...) \
+	printk(KERN_DEBUG DRIVER_NAME_FOR_PRINT " debug: " args)
+#else
+#define DBG(args...) \
+	do {} while (0)
+#endif
+
+#ifdef VERBOSE
+#define VDBG DBG
+#else
+#define VDBG(args...) \
+	do { } while (0)
+#endif
+
+/****************************************************************************/
+
+/* this should always return "1" and print something in verbose mode */
+#ifdef VERBOSE
+#define VDBG_SPC(fmt, args...) \
+	(VDBG(fmt, args) ? 1 : 1)
+#else
+#define VDBG_SPC(fmt, args...) 1
+#endif
+
+/* query bit(s) (long: 32-bit access) */
+#define IS_BIT_RES(data, code) \
+	(!((data) & (code)) ? \
+	 (VDBG_SPC("  OTG HW status: %s is reset\n", #data)) : 0)
+
+#define IS_BIT_SET(data, code) \
+	(((data) & (code)) ? \
+	 (VDBG_SPC("  OTG HW status: %s is set\n", #data)) : 0)
+
+/* query SW flag(s) */
+#define IS_FLAG_RES(dev, data) \
+	(!((data) & (dev)->transceiver.params) ? \
+	 (VDBG_SPC("  OTG SW status: %s is reset\n", #data)) : 0)
+
+#define IS_FLAG_SET(dev, data) \
+	(((data) & (dev)->transceiver.params) ? \
+	 (VDBG_SPC("  OTG SW status: %s is set\n", #data)) : 0)
+
+/* query event bit(s) */
+#define GOT_EVENT(data, code) \
+	(((data) & (code)) ? \
+	 (VDBG_SPC("  OTG event: %s\n", #data)) : 0)
+
+/* set SW flag */
+#ifdef VERBOSE
+#define SET_FLAG(dev, data) \
+do { \
+	if (!((data) & (dev)->transceiver.params)) \
+		DBG("  OTG SW status change: set flag %s\n", #data); \
+	(dev)->transceiver.params |= (data) \
+} while (0);
+#else
+#define SET_FLAG(dev, data) \
+	((dev)->transceiver.params |= (data))
+#endif
+
+/* reset SW flag */
+#ifdef VERBOSE
+#define RES_FLAG(dev, data) \
+do { \
+	if ((data) & (dev)->transceiver.params) \
+		DBG("  OTG SW status change: reset flag %s\n", #data); \
+	(dev)->transceiver.params &= ~((u32) (data)) \
+} while (0);
+#else
+#define RES_FLAG(dev, data) \
+	((dev)->transceiver.params &= ~((u32) (data)))
+#endif
+
+/* reset event bit */
+#define RES_EVENT(data, code) \
+	((code) &= ~((u32) (data)))
+/* NOTE: this is not really needed so far, might be replaced with */
+/* #define RES_EVENT(data, code) \                                */
+/* 	do {} while (0)                                           */
+
+/* change OTG state */
+#ifdef CONFIG_USB_OTG
+#define PREPARE_STATE_CHANGE(dev, new_state) \
+	switch ((new_state) & OTG_STATE_MASK) { \
+	case OTG_STATE_UNDEFINED: \
+		set_undef_state_defaults((dev)); \
+		break; \
+	case OTG_STATE_A_IDLE: \
+		set_a_state_defaults((dev)); \
+		break; \
+	case OTG_STATE_B_IDLE: \
+		set_b_state_defaults((dev)); \
+		break; \
+	default: \
+		break; \
+	} \
+	do {} while (0)
+#else
+#define PREPARE_STATE_CHANGE(dev, new_state) \
+	do {} while (0)
+#endif
+
+#define CHANGE_STATE(dev, new_state, pMask) \
+do { \
+	PREPARE_STATE_CHANGE(dev, new_state); \
+	iowrite32((new_state##_CONTROL), &(dev)->regs->ctl); \
+	*(pMask) = (new_state##_INTERRUPTS); \
+	(dev)->transceiver.state = (new_state); \
+	DBG("OTG new state: %s\n", #new_state); \
+} while (0);
+
+/* verify OTG state */
+#ifndef CONFIG_OTG_TEST_MODE
+
+#define CHECK_STATE(dev, act_state, pMask) \
+do { \
+	*(pMask) = (act_state##_INTERRUPTS); \
+	(dev)->transceiver.prv_state = (act_state); \
+	VDBG("OTG state: %s\n", #act_state); \
+} while (0);
+#else
+#define CHECK_STATE(dev, act_state, pMask) \
+do {\
+	*(pMask) = (act_state##_INTERRUPTS); \
+	(dev)->transceiver.prv_state = (act_state); \
+	if (((ioread32(&(dev)->regs->sts) ^ (act_state##_STATUS))) & \
+	    act_state##_STATUS_MASK) \
+		WARN("OTG warning: incorrect status\n"); \
+	VDBG("OTG state: %s\n", #act_state); \
+} while (0);
+#endif
+
+/* set timer */
+#define SET_OTG_TIMER(dev, val) \
+	set_timer((dev), ((OTG_TMR_##val) * 100))
+
+/* set timer (<1ms) */
+#define SET_OTG_TIMER_SHORT(dev, val) \
+	set_timer((dev), ((OTG_TMR_##val) / 10))
+
+/* set timer (>10ms) */
+#define SET_OTG_TIMER_LONG(dev, val) \
+	set_timer_long ((dev), ((OTG_TMR_##val) / 10))
+
+#ifdef VERBOSE
+#define HS_DISCON_WARNING() \
+	if (!(OTG_CTL_ENABLE_UHC ^ \
+	      (OTG_CTL_MUX_MASK & ioread32(&dev->regs->ctl))) && \
+	    !(OTG_STS_PSPD & ioread32(&dev->regs->sts))) \
+		DBG("  OTG warning: disable UHC from HS-mode\n")
+#else
+#define HS_DISCON_WARNING() \
+	do { } while (0)
+#endif
+
+
+/*****************************************************************************
+*  Data
+*****************************************************************************/
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+struct otg_regs {
+	u32  cap;               /* capabilities */
+	u32  mux;               /* mux */
+	u32  sts;               /* status */
+	u32  ctl;               /* control */
+	u32  tmr;               /* timer */
+	u32  intr;              /* interrupt request */
+	u32  inten;             /* interrupt enable */
+} __attribute__ ((packed));
+
+
+struct otg {
+	spinlock_t              lock;
+	unsigned                enabled:1,
+				got_irq : 1,
+				region : 1;
+	u16                     chiprev;
+
+	struct platform_device  *pdev;
+	struct otg_regs         *regs;
+	struct otg_transceiver  transceiver;
+};
+#define otg_transceiver_to_otg(pTransceiver) \
+	container_of(otg, struct otg, pTransceiver)
+#define otg_to_transceiver(pOtg) \
+	(&pOtg->transceiver)
+
+#ifdef __cplusplus
+} /* extern "C" */
+#endif
+
+/*****************************************************************************
+*  Functions
+*****************************************************************************/
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+extern int usb_gadget_register_otg(struct otg_transceiver * (
+			*get_transceiver)(void));
+extern int usb_gadget_unregister_otg(void);
+
+void otg_init_state(struct otg *);
+int otg_exit_state(struct otg *);
+
+#ifdef DEBUG
+static void print_regs(struct otg *);
+#endif  /* DEBUG */
+
+#ifdef __cplusplus
+} /* extern "C" */
+#endif
+
+
+/*****************************************************************************
+*  Inline Functions
+*****************************************************************************/
+
+extern u32 otg_tmr_high_count;
+extern struct otg_ctl *otg_ctl;
+
+#ifdef CONFIG_USB_OTG
+/**
+ * \brief
+ * set neutral state information
+ *
+ * \param  dev   OTG controller info
+ *
+ * \return void
+ */
+static inline void set_undef_state_defaults(struct otg *dev)
+{
+	dev->transceiver.default_a = 0;
+	if (dev->transceiver.host)
+		dev->transceiver.host->is_b_host = 0;
+	if (dev->transceiver.gadget)
+		dev->transceiver.gadget->is_a_peripheral = 0;
+}
+
+/**
+ * \brief
+ * set A state information
+ *
+ * \param  dev   OTG controller info
+ *
+ * \return void
+ */
+static inline void set_a_state_defaults(struct otg *dev)
+{
+	dev->transceiver.default_a = 1;
+	if (dev->transceiver.host)
+		dev->transceiver.host->is_b_host = 0;
+	if (dev->transceiver.gadget)
+		dev->transceiver.gadget->is_a_peripheral = 1;
+}
+
+/**
+ * \brief
+ * set B state information
+ *
+ * \param  dev   OTG controller info
+ *
+ * \return void
+ */
+static inline void set_b_state_defaults(struct otg *dev)
+{
+	dev->transceiver.default_a = 0;
+	if (dev->transceiver.host)
+		dev->transceiver.host->is_b_host = 1;
+	if (dev->transceiver.gadget)
+		dev->transceiver.gadget->is_a_peripheral = 0;
+}
+
+/**
+ * \brief
+ * set B state information
+ *
+ * \param  dev   OTG controller info
+ *
+ * \return void
+ */
+static inline void reset_b_hnp_enable(struct otg *dev)
+{
+	if (dev->transceiver.host)
+		dev->transceiver.host->b_hnp_enable = 0;
+	VDBG("  OTG action: HNP disabled in B-device\n");
+}
+
+/**
+ * \brief
+ * set B state information
+ *
+ * \param  dev   OTG controller info
+ *
+ * \return void
+ */
+static inline int is_b_hnp_enabled(struct otg *dev)
+{
+	int retVal = 0;
+
+	if (dev->transceiver.host &&
+		dev->transceiver.host->b_hnp_enable) {
+		VDBG("  OTG status: HNP is enabled in HS-B-device\n");
+		retVal = 1;
+	}
+#ifdef VERBOSE
+	else
+		DBG("  OTG status: HNP is disabled in B-device\n");
+#endif
+	return retVal;
+}
+#endif
+
+/**
+ * \brief
+ * Read the status register
+ *
+ * \param  dev   OTG controller info
+ *
+ * \return status
+ */
+static inline u32 get_status(struct otg *dev)
+{
+	return ioread32(&dev->regs->sts);
+}
+
+/**
+ * \brief
+ * Load and start the timer for an unconditional run
+ *
+ * \param  dev   OTG controller info
+ * \param  val   Value to load
+ *
+ * \return void
+ */
+static inline void set_timer(struct otg *dev, u32 val)
+{
+	otg_tmr_high_count = 0;
+
+	iowrite32((val), &dev->regs->tmr);
+	VDBG("  OTG action: start timer: %d0 us\n", val);
+}
+
+/**
+ * \brief
+ * Load and start the timer for an unconditional run
+ *
+ * \param  dev   OTG controller info
+ * \param  val   Value to load
+ *
+ * \return void
+ */
+static inline void set_timer_long(struct otg *dev, u32 val)
+{
+	otg_tmr_high_count = val - 1;
+
+	iowrite32(TIMER_PERIOD, &dev->regs->tmr);
+	VDBG("  OTG action: start timer: %d0 ms\n", val);
+}
+
+/**
+ * \brief
+ * Re-start the timer (value already loaded)
+ *
+ * \param  dev   OTG controller info
+ *
+ * \return void
+ */
+static inline void restart_timer(struct otg *dev)
+{
+	iowrite32((ioread32(&dev->regs->ctl) | OTG_CTL_TMR_UNCOND),
+			&dev->regs->ctl);
+}
+
+/**
+ * \brief
+ * Reset the timer while running (value already loaded)
+ *
+ * \param  dev   OTG controller info
+ *
+ * \return void
+ */
+static inline void reset_timer(struct otg *dev)
+{
+	u32 temp;
+
+	temp = ioread32(&dev->regs->ctl);
+	iowrite32((temp & ~((u32) OTG_CTL_TMR_ALL)), &dev->regs->ctl);
+	iowrite32(temp, &dev->regs->ctl);
+	VDBG("  OTG action: re-start timer\n");
+}
+
+/**
+ * \brief
+ * Prepare the D-pulse
+ *
+ * \param  dev   OTG controller info
+ *
+ * \return void
+ */
+static inline void set_srp_conditions(struct otg *dev)
+{
+	VDBG("  OTG action: SRP init: no action needed due to A0 WAs\n");
+}
+
+/**
+ * \brief
+ * Reset conditions after SRP
+ *
+ * activates the auto-pull-up feature so after SRP the host
+ * will detect a device connect after calling this function
+ *
+ * \param  dev   OTG controller info
+ *
+ * \return void
+ */
+static inline void reset_srp_conditions(struct otg *dev)
+{
+	VDBG("  OTG action: SRP done: no action needed due to A0 WAs\n");
+}
+
+/**
+ * \brief
+ * enable HNP for both devices
+ *
+ * \param  dev   OTG controller info
+ *
+ * \return success
+ */
+static inline int otg_enable_hnp(struct otg *dev)
+{
+	int  retVal = 0;
+	return retVal;
+}
+
+#ifdef DEBUG
+/**
+ * \brief
+ * Print OTG controller registers (debug mode only)
+ *
+ * \param dev    OTG controller info
+ *
+ * \return void
+ */
+static inline void print_regs(struct otg *dev)
+{
+	DBG("-- UOC registers ---\n");
+	DBG("otg cap   = %08x\n", ioread32(&dev->regs->cap));
+	DBG("otg mux   = %08x\n", ioread32(&dev->regs->mux));
+	DBG("otg sts   = %08x\n", ioread32(&dev->regs->sts));
+	DBG("otg ctl   = %08x\n", ioread32(&dev->regs->ctl));
+	DBG("otg tmr   = %08x\n", ioread32(&dev->regs->tmr));
+	DBG("otg intr  = %08x\n", ioread32(&dev->regs->intr));
+	DBG("otg inten = %08x\n", ioread32(&dev->regs->inten));
+	DBG("--------------------\n");
+}
+#endif /* DEBUG */
+
+#endif /* AU1200_UOC_H */
diff --git a/drivers/usb/gadget/gadget_chips.h b/drivers/usb/gadget/gadget_chips.h
index 17d9905..8151d74 100644
--- a/drivers/usb/gadget/gadget_chips.h
+++ b/drivers/usb/gadget/gadget_chips.h
@@ -78,6 +78,12 @@
 #define	gadget_is_omap(g)	0
 #endif
 
+#ifdef CONFIG_USB_GADGET_AU1200
+#define gadget_is_au1200(g)	!strcmp("au1200_udc", (g)->name)
+#else
+#define gadget_is_au1200(g)	0
+#endif
+
 /* not yet ported 2.4 --> 2.6 */
 #ifdef CONFIG_USB_GADGET_N9604
 #define	gadget_is_n9604(g)	!strcmp("n9604_udc", (g)->name)
diff --git a/include/linux/usb/otg.h b/include/linux/usb/otg.h
index 1db25d1..5b88c43 100644
--- a/include/linux/usb/otg.h
+++ b/include/linux/usb/otg.h
@@ -45,7 +45,12 @@ struct otg_transceiver {
 
 	u8			default_a;
 	enum usb_otg_state	state;
-
+#ifdef CONFIG_USB_PORT_AU1200OTG
+	u8			prv_state;
+	u32			params;
+	void			*otg_priv;
+	u8			hostcount;
+#endif
 	struct usb_bus		*host;
 	struct usb_gadget	*gadget;
 
-- 
1.5.4.3


From sshtylyov@ru.mvista.com Thu Sep 11 23:33:21 2008
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To:	Atsushi Nemoto <anemo@mba.ocn.ne.jp>
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	Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>,
	ralf@linux-mips.org
Subject: Re: [PATCH 1/2] ide: Add tx4939ide driver
References: <20080910.010824.07456636.anemo@mba.ocn.ne.jp>
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Hello.

Atsushi Nemoto wrote:

> This is the driver for the Toshiba TX4939 SoC ATA controller.
>
> This controller has standard ATA taskfile registers and DMA
> command/status registers, but the register layout is swapped on big
> endian.  There are some other endian issue and some special registers
> which requires many custom dma_ops/port_ops routines.
>
> Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
>   
[...]
> diff --git a/drivers/ide/mips/tx4939ide.c b/drivers/ide/mips/tx4939ide.c
> new file mode 100644
> index 0000000..ba9776d
> --- /dev/null
> +++ b/drivers/ide/mips/tx4939ide.c
> @@ -0,0 +1,762 @@
>   
[...]
> +static void tx4939ide_dma_host_set(ide_drive_t *drive, int on)
> +{
> +	ide_hwif_t *hwif	= HWIF(drive);
> +	u8 unit			= drive->dn & 1;
> +	unsigned long base = TX4939IDE_BASE(hwif);
> +	u8 dma_stat = TX4939IDE_readb(base, DMA_stat);
> +
> +	if (on)
> +		dma_stat |= (1 << (5 + unit));
> +	else
> +		dma_stat &= ~(1 << (5 + unit));
> +
> +	TX4939IDE_writeb(dma_stat, base, DMA_stat);
> +}
>   

   BTW, you could save on using ide_dma_host_set() in LE mode if you'd 
set hwif->dma_base properly...

> +static int __tx4939ide_dma_setup(ide_drive_t *drive)
> +{
> +	ide_hwif_t *hwif = drive->hwif;
> +	struct request *rq = HWGROUP(drive)->rq;
> +	unsigned int reading;
> +	u8 dma_stat;
> +	unsigned long base = TX4939IDE_BASE(hwif);
> +
[...]
> +
> +	/* read DMA status for INTR & ERROR flags */
> +	dma_stat = TX4939IDE_readb(base, DMA_stat);
> +
> +	/* clear INTR & ERROR flags */
> +	TX4939IDE_writeb(dma_stat | 6, base, DMA_stat);
> +	/* recover intmask cleared by writing to bit2 of DMA_stat */
> +	TX4939IDE_writew(TX4939IDE_IGNORE_INTS << 8, base, int_ctl);
>   

   I think it might be worth factoring the BMDMA status clearing code 
into a separate function...

> +
> +	drive->waiting_for_dma = 1;
> +	return 0;
> +}
> +
> +static int tx4939ide_dma_setup(ide_drive_t *drive)
> +{
> +	ide_hwif_t *hwif = HWIF(drive);
> +	unsigned long base = TX4939IDE_BASE(hwif);
> +	int is_slave = drive->dn & 1;
> +	unsigned int nframes;
> +	int rc, i;
> +	unsigned int sect_size = queue_hardsect_size(drive->queue);
> +	u16 select_data;
> +
> +	select_data = (hwif->select_data >> (is_slave ? 16 : 0)) & 0xffff;
> +	TX4939IDE_writew(select_data, base, Sys_Ctl);
> +	if (is_slave)
> +		TX4939IDE_writew(sect_size / 2, base, Xfer_Cnt_2);
> +	else
> +		TX4939IDE_writew(sect_size / 2, base, Xfer_Cnt_1);
> +
> +	rc = __tx4939ide_dma_setup(drive);
>   

   Hm, I think you need to call this earlier and do an early exit if it 
returns 1.

> +	if (rc == 0) {
>   

   Better check for !=0, return early and avoid unnecessary 
indentatiuon, isn't it?

> +		/* Number of sectors to transfer. */
> +		nframes = 0;
> +		for (i = 0; i < hwif->sg_nents; i++)
> +			nframes += sg_dma_len(&hwif->sg_table[i]);
> +		BUG_ON(nframes % sect_size != 0);
> +		nframes /= sect_size;
> +		BUG_ON(nframes == 0);
> +		TX4939IDE_writew(nframes, base, Sec_Cnt);
> +	}
> +	return rc;
> +}
> +
> +static void tx4939ide_dma_start(ide_drive_t *drive)
> +{
> +	ide_hwif_t *hwif = drive->hwif;
> +	unsigned long base = TX4939IDE_BASE(hwif);
> +	u8 dma_cmd;
> +
> +	/* Note that this is done *after* the cmd has
> +	 * been issued to the drive, as per the BM-IDE spec.
> +	 */
> +	dma_cmd = TX4939IDE_readb(base, DMA_Cmd);
> +	/* start DMA */
> +	TX4939IDE_writeb(dma_cmd | 1, base, DMA_Cmd);
> +
> +	wmb();
> +}
>   

   You could save by using ide_dma_start() in LE mode too...

> +#ifdef __BIG_ENDIAN
> +/* custom iops (independent from SWAP_IO_SPACE) */
> +static u8 mm_inb(unsigned long port)
> +{
> +	return (u8)readb((void __iomem *)port);
> +}
> +static void mm_outb(u8 value, unsigned long port)
> +{
> +	writeb(value, (void __iomem *)port);
> +}
>   

   I'm not sure readb()/writeb() are good substitute for 
__raw_readb()/__raw_writeb() as __swizzle_addr_b() might be actually 
changing the address...

MBR, Sergei



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Subject: Re: [PATCH 1/2] ide: Add tx4939ide driver
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On Fri, 12 Sep 2008 02:33:12 +0400, Sergei Shtylyov <sshtylyov@ru.mvista.com> wrote:
> > +static void tx4939ide_dma_host_set(ide_drive_t *drive, int on)
> > +{
> > +	ide_hwif_t *hwif	= HWIF(drive);
> > +	u8 unit			= drive->dn & 1;
> > +	unsigned long base = TX4939IDE_BASE(hwif);
> > +	u8 dma_stat = TX4939IDE_readb(base, DMA_stat);
> > +
> > +	if (on)
> > +		dma_stat |= (1 << (5 + unit));
> > +	else
> > +		dma_stat &= ~(1 << (5 + unit));
> > +
> > +	TX4939IDE_writeb(dma_stat, base, DMA_stat);
> > +}
> >   
> 
>    BTW, you could save on using ide_dma_host_set() in LE mode if you'd 
> set hwif->dma_base properly...

Yes.  I like endian-free approach in general, but there is already
some ifdefs in this driver.  I have no strong opinion here.

> > +static int __tx4939ide_dma_setup(ide_drive_t *drive)
> > +{
> > +	ide_hwif_t *hwif = drive->hwif;
> > +	struct request *rq = HWGROUP(drive)->rq;
> > +	unsigned int reading;
> > +	u8 dma_stat;
> > +	unsigned long base = TX4939IDE_BASE(hwif);
> > +
> [...]
> > +
> > +	/* read DMA status for INTR & ERROR flags */
> > +	dma_stat = TX4939IDE_readb(base, DMA_stat);
> > +
> > +	/* clear INTR & ERROR flags */
> > +	TX4939IDE_writeb(dma_stat | 6, base, DMA_stat);
> > +	/* recover intmask cleared by writing to bit2 of DMA_stat */
> > +	TX4939IDE_writew(TX4939IDE_IGNORE_INTS << 8, base, int_ctl);
> >   
> 
>    I think it might be worth factoring the BMDMA status clearing code 
> into a separate function...

OK.  Good idea.

> > +static int tx4939ide_dma_setup(ide_drive_t *drive)
> > +{
> > +	ide_hwif_t *hwif = HWIF(drive);
> > +	unsigned long base = TX4939IDE_BASE(hwif);
> > +	int is_slave = drive->dn & 1;
> > +	unsigned int nframes;
> > +	int rc, i;
> > +	unsigned int sect_size = queue_hardsect_size(drive->queue);
> > +	u16 select_data;
> > +
> > +	select_data = (hwif->select_data >> (is_slave ? 16 : 0)) & 0xffff;
> > +	TX4939IDE_writew(select_data, base, Sys_Ctl);
> > +	if (is_slave)
> > +		TX4939IDE_writew(sect_size / 2, base, Xfer_Cnt_2);
> > +	else
> > +		TX4939IDE_writew(sect_size / 2, base, Xfer_Cnt_1);
> > +
> > +	rc = __tx4939ide_dma_setup(drive);
> 
>    Hm, I think you need to call this earlier and do an early exit if it 
> returns 1.
> 
> > +	if (rc == 0) {
> >   
> 
>    Better check for !=0, return early and avoid unnecessary 
> indentatiuon, isn't it?

It mighet be better.  I'll try it.

> > +static void tx4939ide_dma_start(ide_drive_t *drive)
> > +{
> > +	ide_hwif_t *hwif = drive->hwif;
> > +	unsigned long base = TX4939IDE_BASE(hwif);
> > +	u8 dma_cmd;
> > +
> > +	/* Note that this is done *after* the cmd has
> > +	 * been issued to the drive, as per the BM-IDE spec.
> > +	 */
> > +	dma_cmd = TX4939IDE_readb(base, DMA_Cmd);
> > +	/* start DMA */
> > +	TX4939IDE_writeb(dma_cmd | 1, base, DMA_Cmd);
> > +
> > +	wmb();
> > +}
> >   
> 
>    You could save by using ide_dma_start() in LE mode too...

Ditto.

> > +#ifdef __BIG_ENDIAN
> > +/* custom iops (independent from SWAP_IO_SPACE) */
> > +static u8 mm_inb(unsigned long port)
> > +{
> > +	return (u8)readb((void __iomem *)port);
> > +}
> > +static void mm_outb(u8 value, unsigned long port)
> > +{
> > +	writeb(value, (void __iomem *)port);
> > +}
> >   
> 
>    I'm not sure readb()/writeb() are good substitute for 
> __raw_readb()/__raw_writeb() as __swizzle_addr_b() might be actually 
> changing the address...

__swizzle_addr_b() used for both readb() and __raw_readb().  ioswabb()
is used for readb() and __raw_ioswabb() is used for __raw_readb().
Hm, __raw_readb() might be better for consistency, though I cannot
imagine any custom ioswabb() ;-)

---
Atsushi Nemoto

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Subject: Re: [PATCH 1/2] ide: Add tx4939ide driver
References: <20080910.010824.07456636.anemo@mba.ocn.ne.jp>	<48C99CA8.5030602@ru.mvista.com> <20080912.233717.27957136.anemo@mba.ocn.ne.jp>
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Hello.

Atsushi Nemoto wrote:

>>>+static void tx4939ide_dma_host_set(ide_drive_t *drive, int on)
>>>+{
>>>+	ide_hwif_t *hwif	= HWIF(drive);
>>>+	u8 unit			= drive->dn & 1;
>>>+	unsigned long base = TX4939IDE_BASE(hwif);
>>>+	u8 dma_stat = TX4939IDE_readb(base, DMA_stat);
>>>+
>>>+	if (on)
>>>+		dma_stat |= (1 << (5 + unit));
>>>+	else
>>>+		dma_stat &= ~(1 << (5 + unit));
>>>+
>>>+	TX4939IDE_writeb(dma_stat, base, DMA_stat);
>>>+}

>>   BTW, you could save on using ide_dma_host_set() in LE mode if you'd 
>>set hwif->dma_base properly...

> Yes.  I like endian-free approach in general, but there is already
> some ifdefs in this driver.  I have no strong opinion here.

    Unfortunately, the way SFF-8038i registers were implemented in TX4939 
necessiates BE specific #ifdef'ery.  Or at least the run-time endianness 
detection and passing the right struct *_ops to the IDE core -- but that would 
burden the driver with unused and/or unneeded code for the opposite endiannes. 
  It could've been somewhat easied by the use of hwif->dma_{command|status}, 
etc. but those were recently removed (then again, if the DMA engine is not 
SFF-8038i compatible, those fields make little sense)...

>>>+static int __tx4939ide_dma_setup(ide_drive_t *drive)
>>>+{
>>>+	ide_hwif_t *hwif = drive->hwif;
>>>+	struct request *rq = HWGROUP(drive)->rq;
>>>+	unsigned int reading;
>>>+	u8 dma_stat;
>>>+	unsigned long base = TX4939IDE_BASE(hwif);
>>>+

>>[...]

>>>+
>>>+	/* read DMA status for INTR & ERROR flags */
>>>+	dma_stat = TX4939IDE_readb(base, DMA_stat);
>>>+
>>>+	/* clear INTR & ERROR flags */
>>>+	TX4939IDE_writeb(dma_stat | 6, base, DMA_stat);
>>>+	/* recover intmask cleared by writing to bit2 of DMA_stat */
>>>+	TX4939IDE_writew(TX4939IDE_IGNORE_INTS << 8, base, int_ctl);
>>>  
>>
>>   I think it might be worth factoring the BMDMA status clearing code 
>>into a separate function...

    ...along with the int_ctl write, of course.

> OK.  Good idea.

>>>+#ifdef __BIG_ENDIAN
>>>+/* custom iops (independent from SWAP_IO_SPACE) */
>>>+static u8 mm_inb(unsigned long port)
>>>+{
>>>+	return (u8)readb((void __iomem *)port);
>>>+}
>>>+static void mm_outb(u8 value, unsigned long port)
>>>+{
>>>+	writeb(value, (void __iomem *)port);
>>>+}

>>   I'm not sure readb()/writeb() are good substitute for 
>>__raw_readb()/__raw_writeb() as __swizzle_addr_b() might be actually 
>>changing the address...

> __swizzle_addr_b() used for both readb() and __raw_readb().  ioswabb()

    Ah, I missed that. :-/
    More's the reason to rely on the default methods where possible.

> ---
> Atsushi Nemoto

MBR, Sergei

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Subject: Re: [PATCH 1/2] ide: Add tx4939ide driver
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Atsushi Nemoto wrote:

>>>+static void tx4939ide_check_error_ints(ide_hwif_t *hwif, u16 stat)
>>>+{
>>>+	if (stat & TX4939IDE_INT_BUSERR) {
>>>+		unsigned long base = TX4939IDE_BASE(hwif);
>>>+		/* reset FIFO */
>>>+		TX4939IDE_writew(TX4939IDE_readw(base, Sys_Ctl) |
>>>+				 0x4000,
>>>+				 base, Sys_Ctl);

>>   Are you sure bit 14 is self-clearing? The datashhet doesn't seem to 
>>say that...

> Well, I cannot remember...  I thought I checked that bit cleard by
> reading it, but actually the bit is write-only.  Maybe clearing
> explicitly would be a safe bet.

    It's also write-only on TC86C001, and the original driver (as well as 
mine) cleared it explicitly.

>>>+	rc = __tx4939ide_dma_setup(drive);
>>>+	if (rc == 0) {
>>>+		/* Number of sectors to transfer. */
>>>+		nframes = 0;
>>>+		for (i = 0; i < hwif->sg_nents; i++)
>>>+			nframes += sg_dma_len(&hwif->sg_table[i]);
>>>+		BUG_ON(nframes % sect_size != 0);
>>>+		nframes /= sect_size;
>>>+		BUG_ON(nframes == 0);
>>>+		TX4939IDE_writew(nframes, base, Sec_Cnt);

>>   Ugh, it looks much easier in my TC86C001 driver... doesn't 
>>hwgroup->rq->nr_sectors give you a number of 512 sectors?
>>Why bother with other (multiple of 512) sizes when you can always 
>>program transfer in 512-byte sectors? Or was I wrong there?

    Anyway, the TX3939 datasheet says that sector size must be a multiple of 
256 words when transferring more than 1 sector.

> Hmm.  Good idea.  I will try it.

    At least it worked with a CD-ROM for me. :-)

>>>+static int tx4939ide_dma_end(ide_drive_t *drive)
>>>+{
>>>+	if ((dma_stat & 7) == 0 &&
>>>+	    (ctl & (TX4939IDE_INT_XFEREND | TX4939IDE_INT_HOST)) ==
>>>+	    (TX4939IDE_INT_XFEREND | TX4939IDE_INT_HOST))
>>>+		/* INT_IDE lost... bug? */
>>>+		return 0;

>>   You shouldn't fake the BMDMA interrupt. If it's not there, it's not 
>>there. Or does this actually happen?

> IIRC, Yes.

    Hum, let me think... worth printing a message if this happens.

>>>+		/*
>>>+		 * If only one of XFERINT and HOST was asserted, mask
>>>+		 * this interrupt and wait for an another one.  Note

>>   This comment somewhat contradicts the code which returns 1 if only 
>>HOST interupt is asserted if ERR is set.

    Which is not its business to test. I think you should remove that above 
check -- if there's INTRQ asserted, then it's asserted. I wonder if BMIDE 
interrupt bit gets set in that case (suspecting it's not)...

> Indeed.  I will make the comment more precise.

>>>+	case TX4939IDE_INT_HOST | TX4939IDE_INT_XFEREND:
>>>+		dma_stat = TX4939IDE_readb(base, DMA_stat);
>>>+		if (!(dma_stat & 4))
>>>+			pr_debug("%s: weired interrupt status. "
>>>  

>>   Weird.

> Sure.  But it can happen IIRC...

    I meant the typo. :-)

>>>#ifdef __BIG_ENDIAN
>>>+/* custom iops (independent from SWAP_IO_SPACE) */
>>>  
>>>+static u8 mm_inb(unsigned long port)
>>>+{
>>>+	return (u8)readb((void __iomem *)port);
>>>+}
>>>+static void mm_outb(u8 value, unsigned long port)
>>>+{
>>>+	writeb(value, (void __iomem *)port);
>>>+}
>>>+static void mm_tf_load(ide_drive_t *drive, ide_task_t *task)
>>>+{
>>>  

>>[...]

>>>+	if (task->tf_flags & IDE_TFLAG_OUT_DEVICE) {
>>>+		unsigned long base = TX4939IDE_BASE(hwif);
>>>+		mm_outb((tf->device & HIHI) | drive->select,
>>>+			 io_ports->device_addr);

>>   I'm seeing no sense in re-defining so far...

>>>+		/* Fix ATA100 CORE System Control Register */
>>>+		TX4939IDE_writew(TX4939IDE_readw(base, Sys_Ctl) & 0x07f0,
>>>+				 base, Sys_Ctl);

>>   Ah... you're doing it here (but not in LE mode?). I think to avoid 
>>duplicating ide_tf_load() you need ot use selectproc().

> Oh, my fault.  LE mode also needs this fix.  I still need ide_tf_load
> on BE mode to support IDE_TFLAG_OUT_DATA.

   Yeah, that totally useless flag...

>>>+static void mm_insw_swap(unsigned long port, void *addr, u32 count)
>>>+{
>>>+	unsigned short *ptr = addr;
>>>+	unsigned long size = count * 2;
>>>+	port &= ~1;
>>>+	while (count--)
>>>+		*ptr++ = le16_to_cpu(__raw_readw((void __iomem *)port));
>>>+	__ide_flush_dcache_range((unsigned long)addr, size);

>>   Why is this needed BTW?

> Do you mean __ide_flush_dcache_range?  This is needed to avoid cache
> inconsistency on PIO drive.  PIO transfer only writes to cache but
> upper layers expects the data is in main memory.

    Hum, then I wonder why it's MIPS specific...

>>>+static const struct ide_tp_ops tx4939ide_tp_ops = {
>>>+	.exec_command		= ide_exec_command,
>>>+	.read_status		= ide_read_status,
>>>+	.read_altstatus		= ide_read_altstatus,
>>>+	.read_sff_dma_status	= tx4939ide_read_sff_dma_status,

>>   Hum, it should be re-defined in both LE and BE mode (but actually not 
>>called anyway).

> What do you mean?  Please elaborate?

    I mean that in LE mode you're using ide_read_sff_dma_status() but not 
setting hwif->dma_base, so it won't work. But since it shouldn't be called in 
this driver's case, this doesn't hurt.

MBR, Sergei

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On Fri, 12 Sep 2008 19:34:06 +0400, Sergei Shtylyov <sshtylyov@ru.mvista.com> wrote:
> >>   You shouldn't fake the BMDMA interrupt. If it's not there, it's not 
> >>there. Or does this actually happen?
> 
> > IIRC, Yes.
> 
>     Hum, let me think... worth printing a message if this happens.

It might be.  I'll try it.

> >>>+		/*
> >>>+		 * If only one of XFERINT and HOST was asserted, mask
> >>>+		 * this interrupt and wait for an another one.  Note
> 
> >>   This comment somewhat contradicts the code which returns 1 if only 
> >>HOST interupt is asserted if ERR is set.
> 
>     Which is not its business to test. I think you should remove that above 
> check -- if there's INTRQ asserted, then it's asserted. I wonder if BMIDE 
> interrupt bit gets set in that case (suspecting it's not)...

Well, let me explain a bit.  The datasheed say I should wait _both_
XFERINT and HOST interrupt.  So, if only one of them was asserted, I
mask it and wait another one.  But on the error case, only HOST was
asserted and XFERINT was never asserted.  Then I could not exit from
"waiting another one" state, until timeout.

> >>>+			pr_debug("%s: weired interrupt status. "
> >>>  
> 
> >>   Weird.
> 
> > Sure.  But it can happen IIRC...
> 
>     I meant the typo. :-)

Oh, thanks!

> >>>+	__ide_flush_dcache_range((unsigned long)addr, size);
> 
> >>   Why is this needed BTW?
> 
> > Do you mean __ide_flush_dcache_range?  This is needed to avoid cache
> > inconsistency on PIO drive.  PIO transfer only writes to cache but
> > upper layers expects the data is in main memory.
> 
>     Hum, then I wonder why it's MIPS specific...

SPARC also have it.  And there were some discussions for ARM IIRC.

> >>>+	.read_sff_dma_status	= tx4939ide_read_sff_dma_status,
> 
> >>   Hum, it should be re-defined in both LE and BE mode (but actually not 
> >>called anyway).
> 
> > What do you mean?  Please elaborate?
> 
>     I mean that in LE mode you're using ide_read_sff_dma_status() but not 
> setting hwif->dma_base, so it won't work. But since it shouldn't be called in 
> this driver's case, this doesn't hurt.

Yes, I see, thanks.

---
Atsushi Nemoto

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Hello.

Atsushi Nemoto wrote:

>>>>>+		/*
>>>>>+		 * If only one of XFERINT and HOST was asserted, mask
>>>>>+		 * this interrupt and wait for an another one.  Note

>>>>  This comment somewhat contradicts the code which returns 1 if only 
>>>>HOST interupt is asserted if ERR is set.

>>    Which is not its business to test. I think you should remove that above 
>>check -- if there's INTRQ asserted, then it's asserted. I wonder if BMIDE 
>>interrupt bit gets set in that case (suspecting it's not)...

> Well, let me explain a bit.  The datasheed say I should wait _both_
> XFERINT and HOST interrupt.  So, if only one of them was asserted, I

    Since this is SFF-8038i compatible, you should first check if the spec'ed
interrupt status bit (called IDE_INT here) is set. If it isn't [always] get
set when it should, you may check for other interrupt bits (XFEREND/HOST/etc.)
and take the necessary measures if you detect interrupt on them.

> mask it and wait another one.  But on the error case, only HOST was
> asserted and XFERINT was never asserted.

    And I suspect that IDE_INT also doesn't get set, right? The check for 
ERR=1 however is not needed. If the drive does assert its interrupt signal 
(INTRQ), it knows better why.

> Then I could not exit from "waiting another one" state, until timeout.

    Well, at least most of the other [PCI] drivers will wait for timeout in 
the case of the DMA status register bit 2 (IDE_INT here) not set -- despite 
some IDE chips do have bits indicating the INTRQ status from IDE bus. But 
usually, INTRQ still comes thru to this bit even if a command ends in error... 
This isn't the case here?

MBR, Sergei

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Atsushi Nemoto wrote:

>>>>>+		/*
>>>>>+		 * If only one of XFERINT and HOST was asserted, mask
>>>>>+		 * this interrupt and wait for an another one.  Note

>>>>  This comment somewhat contradicts the code which returns 1 if only 
>>>>HOST interupt is asserted if ERR is set.

>>    Which is not its business to test. I think you should remove that above 
>>check -- if there's INTRQ asserted, then it's asserted. I wonder if BMIDE 
>>interrupt bit gets set in that case (suspecting it's not)...

> Well, let me explain a bit.  The datasheed say I should wait _both_
> XFERINT and HOST interrupt.  So, if only one of them was asserted, I
> mask it and wait another one.  But on the error case, only HOST was
> asserted and XFERINT was never asserted.  Then I could not exit from
> "waiting another one" state, until timeout.

    Hmm, I got it: you decide whether it's worth waiting more for XFEREND 
interrupt based on whether ERR is set or not. I suppose IDE_INT doesn't get 
set in case the command gets endede with ERR set?

MBR, Sergei

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From:	Yoshinori Sato <ysato@users.sourceforge.jp>
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At Mon, 08 Sep 2008 23:07:09 -0400,
Yoshinori Sato wrote:
> 
> At Tue, 9 Sep 2008 00:39:40 +0100 (BST),
> Hugh Dickins wrote:
> > 
> > On Mon, 8 Sep 2008, Yoshinori Sato wrote:
> > > At Sun, 7 Sep 2008 23:56:27 -0700,
> > > Andrew Morton wrote:
> > > > 
> > > > This patch broke kallsyms on powerpc.  Please see
> > > > http://ozlabs.org/pipermail/linuxppc-dev/2008-September/062549.html
> > > 
> > > Hmm...
> > > h8300 local symbol head of '.L'.
> > > But powerpc don't have '.L' pattern.
> > > I think add condition "str[1] == 'L'".
> > 
> > No, that won't work right on PowerPC if there's function called
> > something like LookUpTable: we want the symbol ".LookUpTable".
> > 
> > Hugh
> 
> OK.
> This case can't pattern match.
> I Add h8300 special mode.
> 
> -- 
> Yoshinori Sato
> <ysato@users.sourceforge.jp>

It's OK?
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>

diff --git a/arch/h8300/Makefile b/arch/h8300/Makefile
index a556447..644beb6 100644
--- a/arch/h8300/Makefile
+++ b/arch/h8300/Makefile
@@ -37,6 +37,7 @@ KBUILD_CFLAGS += -D__linux__
 KBUILD_CFLAGS += -DUTS_SYSNAME=\"uClinux\"
 KBUILD_AFLAGS += -DPLATFORM=$(PLATFORM) -DMODEL=$(MODEL) $(cflags-y)
 LDFLAGS += $(ldflags-y)
+KALLSYMS += --symbol-prefix='_' --exclude-prefix='.'
 
 CROSS_COMPILE = h8300-elf-
 LIBGCC := $(shell $(CROSS-COMPILE)$(CC) $(KBUILD_CFLAGS) -print-libgcc-file-name)
diff --git a/arch/mips/Makefile b/arch/mips/Makefile
index 9aab51c..582fb2e 100644
--- a/arch/mips/Makefile
+++ b/arch/mips/Makefile
@@ -649,6 +649,8 @@ core-y			+= arch/mips/kernel/ arch/mips/mm/ arch/mips/math-emu/
 
 drivers-$(CONFIG_OPROFILE)	+= arch/mips/oprofile/
 
+KSYMALL += --exclude-prefix='$'
+
 ifdef CONFIG_LASAT
 rom.bin rom.sw: vmlinux
 	$(Q)$(MAKE) $(build)=arch/mips/lasat/image $@
diff --git a/scripts/kallsyms.c b/scripts/kallsyms.c
index ad2434b..7e0d79d 100644
--- a/scripts/kallsyms.c
+++ b/scripts/kallsyms.c
@@ -37,6 +37,7 @@ static unsigned int table_size, table_cnt;
 static unsigned long long _text, _stext, _etext, _sinittext, _einittext;
 static int all_symbols = 0;
 static char symbol_prefix_char = '\0';
+static char exclude_prefix_char = '\0';
 
 int token_profit[0x10000];
 
@@ -47,7 +48,10 @@ unsigned char best_table_len[256];
 
 static void usage(void)
 {
-	fprintf(stderr, "Usage: kallsyms [--all-symbols] [--symbol-prefix=<prefix char>] < in.map > out.S\n");
+	fprintf(stderr, "Usage: kallsyms [--all-symbols]"
+		        " [--symbol-prefix=<prefix char>]"
+		        " [--exclude-prefix=<prefix char>]"
+		        " < in.map > out.S\n");
 	exit(1);
 }
 
@@ -105,8 +109,8 @@ static int read_symbol(FILE *in, struct sym_entry *s)
 	else if (toupper(stype) == 'U' ||
 		 is_arm_mapping_symbol(sym))
 		return -1;
-	/* exclude also MIPS ELF local symbols ($L123 instead of .L123) */
-	else if (str[0] == '$')
+	/* exclude also local symbols */
+	else if (exclude_prefix_char && str[0] == exclude_prefix_char)
 		return -1;
 	/* exclude debugging symbols */
 	else if (stype == 'N')
@@ -543,6 +547,12 @@ int main(int argc, char **argv)
 				if ((*p == '"' && *(p+2) == '"') || (*p == '\'' && *(p+2) == '\''))
 					p++;
 				symbol_prefix_char = *p;
+			} else if (strncmp(argv[i], "--exclude-prefix=", 17) == 0) {
+				char *p = &argv[i][17];
+				/* skip quote */
+				if ((*p == '"' && *(p+2) == '"') || (*p == '\'' && *(p+2) == '\''))
+					p++;
+				exclude_prefix_char = *p;
 			} else
 				usage();
 		}

-- 
Yoshinori Sato
<ysato@users.sourceforge.jp>

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Subject: Re: [PATCH 1/2] ide: Add tx4939ide driver
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On Fri, 12 Sep 2008 21:19:20 +0400, Sergei Shtylyov <sshtylyov@ru.mvista.com> wrote:
> > Well, let me explain a bit.  The datasheed say I should wait _both_
> > XFERINT and HOST interrupt.  So, if only one of them was asserted, I
> > mask it and wait another one.  But on the error case, only HOST was
> > asserted and XFERINT was never asserted.  Then I could not exit from
> > "waiting another one" state, until timeout.
> 
>     Hmm, I got it: you decide whether it's worth waiting more for XFEREND 
> interrupt based on whether ERR is set or not. I suppose IDE_INT doesn't get 
> set in case the command gets endede with ERR set?

IIRC, yes.  And anyway, the interrupt signal from this controller to
CPU is not asserted because HOSTINT was masked by int_ctl register to
wait for XFERINT interrupt.

So, regardless of IDE_INT was set or not, no more interrupt raised to
CPU.

Many of strangeness of interrupt handling in this driver is based on
the fact that the IDE_INT bit in DMA status register does not refrect
the controllers interrupt status directly.  And the implementation of
the IDE_INT bit is actually broken.  Claring the IDE_INT bit also
clears all mask bits in int_ctl registers.  Usually this sort of
behaviour is called "bug". ;)

---
Atsushi Nemoto

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Subject: Re: [PATCH 1/2] ide: Add tx4939ide driver
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On Thu, 11 Sep 2008 00:06:49 +0900 (JST), Atsushi Nemoto <anemo@mba.ocn.ne.jp> wrote:
> The dmatable_cpu is allocated by pci_alloc_consistent so that flush is
> not needed.  But... this is not PCI device.  I should not use
> ide_allocate_dma_engine().  I'll fix it.

Fortunately such a fix will not be needed.  A patch making
ide_allocate_dma_engine() independent from PCI already posted (
"[PATCH 4/8] ide: switch to DMA-mapping API part 2").  I can use
ide_allocate_dma_engine() with non-PCI device safely.  Thanks.

---
Atsushi Nemoto

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Subject: Re: [PATCH] sparse: Make pre_buffer dynamically increasable
From:	Atsushi Nemoto <anemo@mba.ocn.ne.jp>
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On Sun, 20 Jul 2008 00:22:24 +0900 (JST), Atsushi Nemoto <anemo@mba.ocn.ne.jp> wrote:
> I got this error when running sparse on mips kernel with gcc 4.3:
> 
> builtin:272:1: warning: Newline in string or character constant
> 
> The linux-mips kernel uses '$(CC) -dM -E' to generates arguments for
> sparse.  With gcc 4.3, it generates lot of '-D' options and causes
> pre_buffer overflow.  The linux-mips kernel can filter unused symbols
> out to avoid overflow, but sparse should be fixed anyway.
> 
> This patch make pre_buffer dynamically increasable and add extra
> checking for overflow instead of silently truncating.
> 
> Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>

Ping?

> ---
> diff --git a/lib.c b/lib.c
> index 0abcc9a..6e8d09b 100644
> --- a/lib.c
> +++ b/lib.c
> @@ -186,7 +186,8 @@ void die(const char *fmt, ...)
>  }
>  
>  static unsigned int pre_buffer_size;
> -static char pre_buffer[8192];
> +static unsigned int pre_buffer_alloc_size;
> +static char *pre_buffer;
>  
>  int Waddress_space = 1;
>  int Wbitwise = 0;
> @@ -232,12 +233,20 @@ void add_pre_buffer(const char *fmt, ...)
>  	unsigned int size;
>  
>  	va_start(args, fmt);
> +	if (pre_buffer_alloc_size < pre_buffer_size + getpagesize()) {
> +		pre_buffer_alloc_size += getpagesize();
> +		pre_buffer = realloc(pre_buffer, pre_buffer_alloc_size);
> +		if (!pre_buffer)
> +			die("Unable to allocate more pre_buffer space");
> +	}
>  	size = pre_buffer_size;
>  	size += vsnprintf(pre_buffer + size,
> -		sizeof(pre_buffer) - size,
> +		pre_buffer_alloc_size - size,
>  		fmt, args);
>  	pre_buffer_size = size;
>  	va_end(args);
> +	if (pre_buffer_size >= pre_buffer_alloc_size - 1)
> +		die("pre_buffer overflow");
>  }
>  
>  static char **handle_switch_D(char *arg, char **next)


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Subject: Re: [PATCH] sparse: Make pre_buffer dynamically increasable
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On Sat, Sep 13, 2008 at 8:49 AM, Atsushi Nemoto <anemo@mba.ocn.ne.jp> wrote:
>> This patch make pre_buffer dynamically increasable and add extra
>> checking for overflow instead of silently truncating.
>>

The better way is just remove the pre_buffer completely. Just tokenize
the buffer
and append the result token on the fly.

Can you try out the patch I attached? It does just that.

Chris

------=_Part_33116_12975714.1221328785085
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------=_Part_33116_12975714.1221328785085--

From sshtylyov@ru.mvista.com Sat Sep 13 22:48:16 2008
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Date:	Sun, 14 Sep 2008 01:48:06 +0400
From:	Sergei Shtylyov <sshtylyov@ru.mvista.com>
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To:	Atsushi Nemoto <anemo@mba.ocn.ne.jp>
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	Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>,
	ralf@linux-mips.org
Subject: Re: [PATCH 1/2] ide: Add tx4939ide driver
References: <20080910.010824.07456636.anemo@mba.ocn.ne.jp>
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Hello.

Atsushi Nemoto wrote:

> This is the driver for the Toshiba TX4939 SoC ATA controller.
>
> This controller has standard ATA taskfile registers and DMA
> command/status registers, but the register layout is swapped on big
> endian.  There are some other endian issue and some special registers
> which requires many custom dma_ops/port_ops routines.
>
> Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
>   
[...]
> diff --git a/drivers/ide/mips/tx4939ide.c b/drivers/ide/mips/tx4939ide.c
> new file mode 100644
> index 0000000..ba9776d
> --- /dev/null
> +++ b/drivers/ide/mips/tx4939ide.c
> @@ -0,0 +1,762 @@
>   
[...]
> +static void tx4939ide_hwif_init(ide_hwif_t *hwif)
> +{
>   
[...]
> +
> +#ifdef __BIG_ENDIAN
> +	/* This setting does not affect PRD fetch */
> +	/* ByteSwap=1, Endian=00 */
> +	TX4939IDE_writew(0xc911, base, Add_Ctl);
> +#else
> +	TX4939IDE_writew(0xc901, base, Add_Ctl);
> +#endif
>   

   Aren't these the default register values? Is there a sense in writing 
them?

> +#ifdef __BIG_ENDIAN
> +/* custom iops (independent from SWAP_IO_SPACE) */
> +static u8 mm_inb(unsigned long port)
> +{
> +	return (u8)readb((void __iomem *)port);
> +}
> +static void mm_outb(u8 value, unsigned long port)
> +{
> +	writeb(value, (void __iomem *)port);
> +}
> +static void mm_tf_load(ide_drive_t *drive, ide_task_t *task)
> +{
> +	ide_hwif_t *hwif = drive->hwif;
> +	struct ide_io_ports *io_ports = &hwif->io_ports;
> +	struct ide_taskfile *tf = &task->tf;
> +	u8 HIHI = (task->tf_flags & IDE_TFLAG_LBA48) ? 0xE0 : 0xEF;
> +
> +	if (task->tf_flags & IDE_TFLAG_FLAGGED)
> +		HIHI = 0xFF;
> +
> +	if (task->tf_flags & IDE_TFLAG_OUT_DATA) {
> +		u16 data = (tf->hob_data << 8) | tf->data;
> +
> +		__raw_writew(data, (void __iomem *)io_ports->data_addr);
>   

   This doesn't look consistent (aside from the TX4939IDE_REG8/16 issue) 
-- mm_outsw_swap() calls cpu_to_le16() before writing 16-bit data but 
this code doesn't. So, either one of those should be wrong...

> +static void mm_tf_read(ide_drive_t *drive, ide_task_t *task)
> +{
> +	ide_hwif_t *hwif = drive->hwif;
> +	struct ide_io_ports *io_ports = &hwif->io_ports;
> +	struct ide_taskfile *tf = &task->tf;
> +
> +	if (task->tf_flags & IDE_TFLAG_IN_DATA) {
> +		u16 data;
> +
> +		data = __raw_readw((void __iomem *)io_ports->data_addr);
> +		tf->data = data & 0xff;
> +		tf->hob_data = (data >> 8) & 0xff;
>   

    Same here...

> +static void mm_insw_swap(unsigned long port, void *addr, u32 count)
> +{
> +	unsigned short *ptr = addr;
> +	unsigned long size = count * 2;
> +	port &= ~1;
> +	while (count--)
> +		*ptr++ = le16_to_cpu(__raw_readw((void __iomem *)port));
> +	__ide_flush_dcache_range((unsigned long)addr, size);
> +}
> +static void mm_outsw_swap(unsigned long port, void *addr, u32 count)
> +{
> +	unsigned short *ptr = addr;
> +	unsigned long size = count * 2;
> +	port &= ~1;
> +	while (count--) {
> +		__raw_writew(cpu_to_le16(*ptr), (void __iomem *)port);
> +		ptr++;
> +	}
> +	__ide_flush_dcache_range((unsigned long)addr, size);
> +}
>   

    Hum... but is it really correct to convert from/to LE order above? 
I'm prett sure that data is expected in LE order -- look ar 
ide_fix_driveid() for example...

MBR, Sergei



From anemo@mba.ocn.ne.jp Sun Sep 14 13:41:51 2008
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	sam@ravnborg.org, viro@zeniv.linux.org.uk
Subject: Re: [PATCH] sparse: Make pre_buffer dynamically increasable
From:	Atsushi Nemoto <anemo@mba.ocn.ne.jp>
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On Sat, 13 Sep 2008 10:59:45 -0700, "Christopher Li" <sparse@chrisli.org> wrote:
> The better way is just remove the pre_buffer completely. Just tokenize
> the buffer
> and append the result token on the fly.
> 
> Can you try out the patch I attached? It does just that.

Thanks, it works for me.

---
Atsushi Nemoto

From anemo@mba.ocn.ne.jp Sun Sep 14 14:05:04 2008
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To:	sshtylyov@ru.mvista.com
Cc:	linux-mips@linux-mips.org, linux-ide@vger.kernel.org,
	bzolnier@gmail.com, ralf@linux-mips.org
Subject: Re: [PATCH 1/2] ide: Add tx4939ide driver
From:	Atsushi Nemoto <anemo@mba.ocn.ne.jp>
In-Reply-To: <48CC3516.9080404@ru.mvista.com>
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On Sun, 14 Sep 2008 01:48:06 +0400, Sergei Shtylyov <sshtylyov@ru.mvista.com> wrote:
> > +#ifdef __BIG_ENDIAN
> > +	/* This setting does not affect PRD fetch */
> > +	/* ByteSwap=1, Endian=00 */
> > +	TX4939IDE_writew(0xc911, base, Add_Ctl);
> > +#else
> > +	TX4939IDE_writew(0xc901, base, Add_Ctl);
> > +#endif
> >   
> 
>    Aren't these the default register values? Is there a sense in writing 
> them?

Indeed.  It seems redundant.

> > +#ifdef __BIG_ENDIAN
> > +/* custom iops (independent from SWAP_IO_SPACE) */
> > +static u8 mm_inb(unsigned long port)
> > +{
> > +	return (u8)readb((void __iomem *)port);
> > +}
> > +static void mm_outb(u8 value, unsigned long port)
> > +{
> > +	writeb(value, (void __iomem *)port);
> > +}
> > +static void mm_tf_load(ide_drive_t *drive, ide_task_t *task)
> > +{
> > +	ide_hwif_t *hwif = drive->hwif;
> > +	struct ide_io_ports *io_ports = &hwif->io_ports;
> > +	struct ide_taskfile *tf = &task->tf;
> > +	u8 HIHI = (task->tf_flags & IDE_TFLAG_LBA48) ? 0xE0 : 0xEF;
> > +
> > +	if (task->tf_flags & IDE_TFLAG_FLAGGED)
> > +		HIHI = 0xFF;
> > +
> > +	if (task->tf_flags & IDE_TFLAG_OUT_DATA) {
> > +		u16 data = (tf->hob_data << 8) | tf->data;
> > +
> > +		__raw_writew(data, (void __iomem *)io_ports->data_addr);
> >   
> 
>    This doesn't look consistent (aside from the TX4939IDE_REG8/16 issue) 
> -- mm_outsw_swap() calls cpu_to_le16() before writing 16-bit data but 
> this code doesn't. So, either one of those should be wrong...

Thanks, this code should be wrong.  IDE_TFLAG_OUT_DATA is totally
untested...

> > +static void mm_insw_swap(unsigned long port, void *addr, u32 count)
> > +{
> > +	unsigned short *ptr = addr;
> > +	unsigned long size = count * 2;
> > +	port &= ~1;
> > +	while (count--)
> > +		*ptr++ = le16_to_cpu(__raw_readw((void __iomem *)port));
> > +	__ide_flush_dcache_range((unsigned long)addr, size);
> > +}
> > +static void mm_outsw_swap(unsigned long port, void *addr, u32 count)
> > +{
> > +	unsigned short *ptr = addr;
> > +	unsigned long size = count * 2;
> > +	port &= ~1;
> > +	while (count--) {
> > +		__raw_writew(cpu_to_le16(*ptr), (void __iomem *)port);
> > +		ptr++;
> > +	}
> > +	__ide_flush_dcache_range((unsigned long)addr, size);
> > +}
> >   
> 
>     Hum... but is it really correct to convert from/to LE order above? 
> I'm prett sure that data is expected in LE order -- look ar 
> ide_fix_driveid() for example...

Well, do you mean I should use cpu_to_le16 in mm_insw_swap and
le16_to_cpu in mm_outsw_swap?  Or can I avoid these swapping entirely
in some way?

---
Atsushi Nemoto

From sshtylyov@ru.mvista.com Sun Sep 14 21:55:20 2008
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Date:	Mon, 15 Sep 2008 00:55:11 +0400
From:	Sergei Shtylyov <sshtylyov@ru.mvista.com>
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To:	Atsushi Nemoto <anemo@mba.ocn.ne.jp>
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	Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>,
	ralf@linux-mips.org
Subject: Re: [PATCH 1/2] ide: Add tx4939ide driver
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Hello, I wrote:

>> +static void mm_insw_swap(unsigned long port, void *addr, u32 count)
>> +{
>> +    unsigned short *ptr = addr;
>> +    unsigned long size = count * 2;
>> +    port &= ~1;
>> +    while (count--)
>> +        *ptr++ = le16_to_cpu(__raw_readw((void __iomem *)port));
>> +    __ide_flush_dcache_range((unsigned long)addr, size);
>> +}
>> +static void mm_outsw_swap(unsigned long port, void *addr, u32 count)
>> +{
>> +    unsigned short *ptr = addr;
>> +    unsigned long size = count * 2;
>> +    port &= ~1;
>> +    while (count--) {
>> +        __raw_writew(cpu_to_le16(*ptr), (void __iomem *)port);
>> +        ptr++;
>> +    }
>> +    __ide_flush_dcache_range((unsigned long)addr, size);
>> +}
>>   
>
>    Hum... but is it really correct to convert from/to LE order above? 
> I'm prett sure that data is expected in LE order -- look ar 
> ide_fix_driveid() for example...
>

   Assuming that the IDE data words' MSB appears at offset 6 and LSB at 
offset 7 (which would seem logical), the data is actually in BE (CPU) 
orger, so
mm_insw_swap() should use cpu_to_le16() and mm_outsw_swap() le16_to_cpu()...

MBR, Sergei



From ralf@linux-mips.org Mon Sep 15 08:29:48 2008
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From:	Ralf Baechle <ralf@linux-mips.org>
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Subject: Re: [PATCH 0/3] Globally defining phys_addr_t
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On Thu, Sep 11, 2008 at 12:03:36PM +0200, Geert Uytterhoeven wrote:

> On Thu, 11 Sep 2008, Jeremy Fitzhardinge wrote:
> > This is a repost of a little 3-patch series which Andrew has been
> > carrying in -mm.  It cleans up the definition of phys_addr_t to make it
> > kernel-wide rather than x86-specific, and fixes up PFN_PHYS() to use it
> > to avoid address truncation.
> > 
> > We currently have a few workarounds for this problem in the tree, but
> > Alex found another bug caused by PFN_PHYS(), so it's probably better if
> > you bring these patches into tip.git for now.
> > 
> > PowerPC also defines a phys_addr_t with the same meaning as x86; the
> > powerpc arch maintainers are happy with these patches.
> 
> If I'm not mistaking, this is also true for some MIPS machines.

Jeremy probably missed it because it's called phys_t on MIPS.  It's usually
the same size as unsigned long but a few of the 32-bit Alchemy SOCs have
peripherals placed outside of the 32-bit physical address space so for
those CONFIG_64BIT_PHYS_ADDR will be defined and phys_t be unsigned long
long and used for some pagetable stuff to map those devices into the 32-bit
virtual address space.

UM uses a phys_t for its pagetables.

A single data type for everybody is enough.  phys_addr_t or phys_t I don't
care; I went for phys_t because it's shorter, less to type.

  Ralf

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Subject: Re: [PATCH 1/2] ide: Add tx4939ide driver
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On Mon, 15 Sep 2008 00:55:11 +0400, Sergei Shtylyov <sshtylyov@ru.mvista.com> wrote:
> >    Hum... but is it really correct to convert from/to LE order above? 
> > I'm prett sure that data is expected in LE order -- look ar 
> > ide_fix_driveid() for example...
> >
> 
>    Assuming that the IDE data words' MSB appears at offset 6 and LSB at 
> offset 7 (which would seem logical), the data is actually in BE (CPU) 
> orger, so
> mm_insw_swap() should use cpu_to_le16() and mm_outsw_swap() le16_to_cpu()...

Thanks, I see.

---
Atsushi Nemoto

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Date:	Mon, 15 Sep 2008 20:50:54 -0400
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Subject: [PATCH] [MIPS] vr41xx: unsigned irq cannot be negative
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unsigned irq cannot be negative

Signed-off-by: Roel Kluin <roel.kluin@gmail.com>
---
diff --git a/arch/mips/vr41xx/common/irq.c b/arch/mips/vr41xx/common/irq.c
index cba36a2..92dd1a0 100644
--- a/arch/mips/vr41xx/common/irq.c
+++ b/arch/mips/vr41xx/common/irq.c
@@ -72,6 +72,7 @@ static void irq_dispatch(unsigned int irq)
 	cascade = irq_cascade + irq;
 	if (cascade->get_irq != NULL) {
 		unsigned int source_irq = irq;
+		int ret;
 		desc = irq_desc + source_irq;
 		if (desc->chip->mask_ack)
 			desc->chip->mask_ack(source_irq);
@@ -79,8 +80,9 @@ static void irq_dispatch(unsigned int irq)
 			desc->chip->mask(source_irq);
 			desc->chip->ack(source_irq);
 		}
-		irq = cascade->get_irq(irq);
-		if (irq < 0)
+		ret = cascade->get_irq(irq);
+		irq = ret;
+		if (ret < 0)
 			atomic_inc(&irq_err_count);
 		else
 			irq_dispatch(irq);

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From:	David Brownell <david-b@pacbell.net>
To:	Kevin Hickey <khickey@rmicorp.com>
Subject: Re: [PATCH] Au1200 USB Device Controller and device-only OTG
Date:	Mon, 15 Sep 2008 12:16:01 -0700
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On Thursday 11 September 2008, Kevin Hickey wrote:
> basic device-only OTG (On-The-Go) support

That does't look like it's done right.  For starters, it abuses
Kconfig to handle a board-specific config option.  Put that data
in platform_data instead ...

Second, it breaks some previously-working code.

Third, it misbehaves even on an x86 config.  Needs something like
the appended patch.

- Dave


--- g26.orig/drivers/usb/gadget/Kconfig	2008-09-15 12:10:22.000000000 -0700
+++ g26/drivers/usb/gadget/Kconfig	2008-09-15 12:10:06.000000000 -0700
@@ -490,7 +490,7 @@ config USB_GADGET_DUALSPEED
 
 config USB_PORT_AU1200OTG
 	boolean "AU1200 USB portmux control (On-The-Go support)"
-	depends on USB_GADGET_AU1200 || USB_EHCI_HCD || USB_OHCI_HCD
+	depends on USB_GADGET_AU1200 && (USB_EHCI_HCD || USB_OHCI_HCD)
 	default n
 	help
 	   The AU1200 and Au1200 USB device port can be used as either a host


From khickey@rmicorp.com Mon Sep 15 20:39:01 2008
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Subject: Re: [PATCH] Au1200 USB Device Controller and device-only OTG
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On Mon, 2008-09-15 at 12:16 -0700, David Brownell wrote:
> On Thursday 11 September 2008, Kevin Hickey wrote:
> > basic device-only OTG (On-The-Go) support
>=20
> That does't look like it's done right.  For starters, it abuses
> Kconfig to handle a board-specific config option.  Put that data
> in platform_data instead ...
I don't understand what you mean by this.  Can you be more specific?
>=20
> Second, it breaks some previously-working code.
Can you be more specific?
>=20
> Third, it misbehaves even on an x86 config.  Needs something like
> the appended patch.
Does it only misbehave on an x86 config or also on a MIPS config?  I
have no problems when building for DB1200. =20
>=20
> - Dave
>=20
>=20
> --- g26.orig/drivers/usb/gadget/Kconfig	2008-09-15 12:10:22.000000000 =
-0700
> +++ g26/drivers/usb/gadget/Kconfig	2008-09-15 12:10:06.000000000 -0700
> @@ -490,7 +490,7 @@ config USB_GADGET_DUALSPEED
> =20
>  config USB_PORT_AU1200OTG
>  	boolean "AU1200 USB portmux control (On-The-Go support)"
> -	depends on USB_GADGET_AU1200 || USB_EHCI_HCD || USB_OHCI_HCD
> +	depends on USB_GADGET_AU1200 && (USB_EHCI_HCD || USB_OHCI_HCD)
>  	default n
>  	help
>  	   The AU1200 and Au1200 USB device port can be used as either a =
host
>=20
--=20
Kevin Hickey
Alchemy Solutions
RMI Corporation
khickey@rmicorp.com
P: 512.691.8044

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OTG</TITLE>
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<P><FONT SIZE=3D2>On Mon, 2008-09-15 at 12:16 -0700, David Brownell =
wrote:<BR>
&gt; On Thursday 11 September 2008, Kevin Hickey wrote:<BR>
&gt; &gt; basic device-only OTG (On-The-Go) support<BR>
&gt;<BR>
&gt; That does't look like it's done right.&nbsp; For starters, it =
abuses<BR>
&gt; Kconfig to handle a board-specific config option.&nbsp; Put that =
data<BR>
&gt; in platform_data instead ...<BR>
I don't understand what you mean by this.&nbsp; Can you be more =
specific?<BR>
&gt;<BR>
&gt; Second, it breaks some previously-working code.<BR>
Can you be more specific?<BR>
&gt;<BR>
&gt; Third, it misbehaves even on an x86 config.&nbsp; Needs something =
like<BR>
&gt; the appended patch.<BR>
Does it only misbehave on an x86 config or also on a MIPS config?&nbsp; =
I<BR>
have no problems when building for DB1200.&nbsp;<BR>
&gt;<BR>
&gt; - Dave<BR>
&gt;<BR>
&gt;<BR>
&gt; --- =
g26.orig/drivers/usb/gadget/Kconfig&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
2008-09-15 12:10:22.000000000 -0700<BR>
&gt; +++ g26/drivers/usb/gadget/Kconfig&nbsp;&nbsp;&nbsp; 2008-09-15 =
12:10:06.000000000 -0700<BR>
&gt; @@ -490,7 +490,7 @@ config USB_GADGET_DUALSPEED<BR>
&gt;&nbsp;<BR>
&gt;&nbsp; config USB_PORT_AU1200OTG<BR>
&gt;&nbsp; &nbsp;&nbsp;&nbsp;&nbsp; boolean &quot;AU1200 USB portmux =
control (On-The-Go support)&quot;<BR>
&gt; -&nbsp;&nbsp;&nbsp;&nbsp; depends on USB_GADGET_AU1200 || =
USB_EHCI_HCD || USB_OHCI_HCD<BR>
&gt; +&nbsp;&nbsp;&nbsp;&nbsp; depends on USB_GADGET_AU1200 &amp;&amp; =
(USB_EHCI_HCD || USB_OHCI_HCD)<BR>
&gt;&nbsp; &nbsp;&nbsp;&nbsp;&nbsp; default n<BR>
&gt;&nbsp; &nbsp;&nbsp;&nbsp;&nbsp; help<BR>
&gt;&nbsp; &nbsp;&nbsp;&nbsp;&nbsp; &nbsp;&nbsp; The AU1200 and Au1200 =
USB device port can be used as either a host<BR>
&gt;<BR>
--<BR>
Kevin Hickey<BR>
Alchemy Solutions<BR>
RMI Corporation<BR>
khickey@rmicorp.com<BR>
P: 512.691.8044<BR>
</FONT>
</P>

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From zeisberg@informatik.uni-freiburg.de Mon Sep 15 21:02:50 2008
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From:	=?utf-8?q?Uwe=20Kleine-K=C3=B6nig?= 
	<ukleinek@informatik.uni-freiburg.de>
To:	linux-kernel@vger.kernel.org
Cc:	David Brownell <david-b@pacbell.net>,
	Ralf Baechle <ralf@linux-mips.org>, linux-mips@linux-mips.org,
	Guennadi Liakhovetski <g.liakhovetski@pengutronix.de>,
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	Andrew Morton <akpm@linux-foundation.org>,
	Russell King <rmk+kernel@arm.linux.org.uk>
Subject: [PATCH] gpio_free might sleep, mips architecture
Date:	Mon, 15 Sep 2008 22:02:41 +0200
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According to the documentation gpio_free should only be called from task
context only.  To make this more explicit add a might sleep to all
implementations.

This patch changes the gpio_free implementations for the mips
architecture.

Signed-off-by: Uwe Kleine-König <ukleinek@informatik.uni-freiburg.de>
Cc: David Brownell <david-b@pacbell.net>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: linux-mips@linux-mips.org
Cc: Guennadi Liakhovetski <g.liakhovetski@pengutronix.de>
Cc: Greg KH <greg@kroah.com>
Cc: Kay Sievers <kay.sievers@vrfy.org>
Cc: Andrew Morton <akpm@linux-foundation.org>
Cc: Russell King <rmk+kernel@arm.linux.org.uk>
---
 include/asm-mips/mach-au1x00/gpio.h  |    2 ++
 include/asm-mips/mach-bcm47xx/gpio.h |    3 +++
 include/asm-mips/mach-rc32434/gpio.h |    2 ++
 3 files changed, 7 insertions(+), 0 deletions(-)

diff --git a/include/asm-mips/mach-au1x00/gpio.h b/include/asm-mips/mach-au1x00/gpio.h
index 2dc61e0..31eddba 100644
--- a/include/asm-mips/mach-au1x00/gpio.h
+++ b/include/asm-mips/mach-au1x00/gpio.h
@@ -1,6 +1,7 @@
 #ifndef _AU1XXX_GPIO_H_
 #define _AU1XXX_GPIO_H_
 
+#include <linux/kernel.h>
 #include <linux/types.h>
 
 #define AU1XXX_GPIO_BASE	200
@@ -31,6 +32,7 @@ static inline int gpio_request(unsigned gpio, const char *label)
 static inline void gpio_free(unsigned gpio)
 {
 	/* Not yet implemented */
+	might_sleep();
 }
 
 static inline int gpio_direction_input(unsigned gpio)
diff --git a/include/asm-mips/mach-bcm47xx/gpio.h b/include/asm-mips/mach-bcm47xx/gpio.h
index cfc8f4d..af17ccd 100644
--- a/include/asm-mips/mach-bcm47xx/gpio.h
+++ b/include/asm-mips/mach-bcm47xx/gpio.h
@@ -9,6 +9,8 @@
 #ifndef __BCM47XX_GPIO_H
 #define __BCM47XX_GPIO_H
 
+#include <linux/kernel.h>
+
 #define BCM47XX_EXTIF_GPIO_LINES	5
 #define BCM47XX_CHIPCO_GPIO_LINES	16
 
@@ -25,6 +27,7 @@ static inline int gpio_request(unsigned gpio, const char *label)
 
 static inline void gpio_free(unsigned gpio)
 {
+	might_sleep();
 }
 
 static inline int gpio_to_irq(unsigned gpio)
diff --git a/include/asm-mips/mach-rc32434/gpio.h b/include/asm-mips/mach-rc32434/gpio.h
index f946f5f..9b4722e 100644
--- a/include/asm-mips/mach-rc32434/gpio.h
+++ b/include/asm-mips/mach-rc32434/gpio.h
@@ -13,6 +13,7 @@
 #ifndef _RC32434_GPIO_H_
 #define _RC32434_GPIO_H_
 
+#include <linux/kernel.h>
 #include <linux/types.h>
 
 struct rb532_gpio_reg {
@@ -88,6 +89,7 @@ static inline int gpio_request(unsigned gpio, const char *label)
 static inline void gpio_free(unsigned gpio)
 {
 	/* Not yet implemented */
+	might_sleep();
 }
 
 static inline int gpio_direction_input(unsigned gpio)
-- 
1.5.6.5


From yoichi_yuasa@tripeaks.co.jp Tue Sep 16 03:02:53 2008
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	linux-mips@linux-mips.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH] [MIPS] vr41xx: unsigned irq cannot be negative
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On Mon, 15 Sep 2008 20:50:54 -0400
roel kluin <roel.kluin@gmail.com> wrote:

> unsigned irq cannot be negative
> 
> Signed-off-by: Roel Kluin <roel.kluin@gmail.com>

Acked-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>

Yoichi

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From:	David Brownell <david-b@pacbell.net>
To:	Kevin Hickey <khickey@rmicorp.com>
Subject: Re: [PATCH] Au1200 USB Device Controller and device-only OTG
Date:	Mon, 15 Sep 2008 23:53:59 -0700
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On Monday 15 September 2008, Kevin Hickey wrote:
> On Mon, 2008-09-15 at 12:16 -0700, David Brownell wrote:
> > On Thursday 11 September 2008, Kevin Hickey wrote:
> > > basic device-only OTG (On-The-Go) support
> > 
> > That does't look like it's done right.  For starters, it abuses
> > Kconfig to handle a board-specific config option.  Put that data
> > in platform_data instead ...
>
> I don't understand what you mean by this.  Can you be more specific?

The need for CONFIG_USB_AU1200OTG is board-specific,
and doesn't belong in Kconfig.

Also, the au1200_otg code should live with platform code ...
plan for it to become "real OTG support" (at least for cable
based role switching), and then it becomes clear that it does
not belong in the drivers/usb host or gadget directories (since
it affects both).  At this point I have a preference for such
stuff to live in arch/... directories


> > Second, it breaks some previously-working code.
>
> Can you be more specific?

Breaks the orignal OMAP OTG support:

> > -config USB_OTG
> > -       boolean "OTG Support"
> > -       depends on USB_GADGET_OMAP && ARCH_OMAP_OTG && USB_OHCI_HCD

... by removing that stuff.

 
> > Third, it misbehaves even on an x86 config.  Needs something like
> > the appended patch.
>
> Does it only misbehave on an x86 config or also on a MIPS config?  I
> have no problems when building for DB1200.

Read the patch and you'll see what's going on.  Any non-MIPS config
gets broken.

- Dave


 
> > 
> > - Dave
> > 
> > 
> > --- g26.orig/drivers/usb/gadget/Kconfig	2008-09-15 12:10:22.000000000 -0700
> > +++ g26/drivers/usb/gadget/Kconfig	2008-09-15 12:10:06.000000000 -0700
> > @@ -490,7 +490,7 @@ config USB_GADGET_DUALSPEED
> >  
> >  config USB_PORT_AU1200OTG
> >  	boolean "AU1200 USB portmux control (On-The-Go support)"
> > -	depends on USB_GADGET_AU1200 || USB_EHCI_HCD || USB_OHCI_HCD
> > +	depends on USB_GADGET_AU1200 && (USB_EHCI_HCD || USB_OHCI_HCD)
> >  	default n
> >  	help
> >  	   The AU1200 and Au1200 USB device port can be used as either a host
> > 
> 



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Date:	Tue, 16 Sep 2008 10:58:02 +0200
From:	Ralf Baechle <ralf@linux-mips.org>
To:	roel kluin <roel.kluin@gmail.com>
Cc:	yoichi_yuasa@tripeaks.co.jp, linux-mips@linux-mips.org,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH] [MIPS] vr41xx: unsigned irq cannot be negative
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On Mon, Sep 15, 2008 at 08:50:54PM -0400, roel kluin wrote:

Thanks, applied.

  Ralf

From sshtylyov@ru.mvista.com Tue Sep 16 11:36:27 2008
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To:	Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Cc:	linux-mips@linux-mips.org, linux-ide@vger.kernel.org,
	bzolnier@gmail.com, ralf@linux-mips.org
Subject: Re: [PATCH 1/2] ide: Add tx4939ide driver
References: <20080910.010824.07456636.anemo@mba.ocn.ne.jp>	<48CC3516.9080404@ru.mvista.com> <20080914.220512.126760706.anemo@mba.ocn.ne.jp>
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Hello.

Atsushi Nemoto wrote:

>>> +#ifdef __BIG_ENDIAN
>>> +/* custom iops (independent from SWAP_IO_SPACE) */
>>> +static u8 mm_inb(unsigned long port)
>>> +{
>>> +	return (u8)readb((void __iomem *)port);
>>> +}
>>> +static void mm_outb(u8 value, unsigned long port)
>>> +{
>>> +	writeb(value, (void __iomem *)port);
>>> +}
>>> +static void mm_tf_load(ide_drive_t *drive, ide_task_t *task)
>>> +{
>>> +	ide_hwif_t *hwif = drive->hwif;
>>> +	struct ide_io_ports *io_ports = &hwif->io_ports;
>>> +	struct ide_taskfile *tf = &task->tf;
>>> +	u8 HIHI = (task->tf_flags & IDE_TFLAG_LBA48) ? 0xE0 : 0xEF;
>>> +
>>> +	if (task->tf_flags & IDE_TFLAG_FLAGGED)
>>> +		HIHI = 0xFF;
>>> +
>>> +	if (task->tf_flags & IDE_TFLAG_OUT_DATA) {
>>> +		u16 data = (tf->hob_data << 8) | tf->data;
>>> +
>>> +		__raw_writew(data, (void __iomem *)io_ports->data_addr);
>>>   
>>>       
>>    This doesn't look consistent (aside from the TX4939IDE_REG8/16 issue) 
>> -- mm_outsw_swap() calls cpu_to_le16() before writing 16-bit data but 
>> this code doesn't. So, either one of those should be wrong...
>>     
>
> Thanks, this code should be wrong.  IDE_TFLAG_OUT_DATA is totally
> untested...
>   

   Hum, not necessarily...
   If the data register is BE, this should work correctly, if I don't 
mistake (once you fix the data register's address).

MBR, Sergei



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Date:	Tue, 16 Sep 2008 14:44:21 +0400
From:	Sergei Shtylyov <sshtylyov@ru.mvista.com>
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To:	roel kluin <roel.kluin@gmail.com>
Cc:	ralf@linux-mips.org, yoichi_yuasa@tripeaks.co.jp,
	linux-mips@linux-mips.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH] [MIPS] vr41xx: unsigned irq cannot be negative
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Hello.

roel kluin wrote:

> unsigned irq cannot be negative
>
> Signed-off-by: Roel Kluin <roel.kluin@gmail.com>
> ---
> diff --git a/arch/mips/vr41xx/common/irq.c b/arch/mips/vr41xx/common/irq.c
> index cba36a2..92dd1a0 100644
> --- a/arch/mips/vr41xx/common/irq.c
> +++ b/arch/mips/vr41xx/common/irq.c
> @@ -72,6 +72,7 @@ static void irq_dispatch(unsigned int irq)
>  	cascade = irq_cascade + irq;
>  	if (cascade->get_irq != NULL) {
>  		unsigned int source_irq = irq;
> +		int ret;
>   

   Keep an empty line after the declaration block please.

> @@ -79,8 +80,9 @@ static void irq_dispatch(unsigned int irq)
>  			desc->chip->mask(source_irq);
>  			desc->chip->ack(source_irq);
>  		}
> -		irq = cascade->get_irq(irq);
> -		if (irq < 0)
> +		ret = cascade->get_irq(irq);
> +		irq = ret;
> +		if (ret < 0)
>  			atomic_inc(&irq_err_count);
>  		else
>  			irq_dispatch(irq);
>   

  How about this:

		ret = cascade->get_irq(irq);
		if (ret < 0)
 			atomic_inc(&irq_err_count);
 		else
 			irq_dispatch(ret);


WBR, Sergei



From anemo@mba.ocn.ne.jp Tue Sep 16 16:20:25 2008
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Subject: Re: [PATCH 1/2] ide: Add tx4939ide driver
From:	Atsushi Nemoto <anemo@mba.ocn.ne.jp>
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On Tue, 16 Sep 2008 14:29:27 +0400, Sergei Shtylyov <sshtylyov@ru.mvista.com> wrote:
> >>    This doesn't look consistent (aside from the TX4939IDE_REG8/16 issue) 
> >> -- mm_outsw_swap() calls cpu_to_le16() before writing 16-bit data but 
> >> this code doesn't. So, either one of those should be wrong...
> >
> > Thanks, this code should be wrong.  IDE_TFLAG_OUT_DATA is totally
> > untested...
> 
>    Hum, not necessarily...
>    If the data register is BE, this should work correctly, if I don't 
> mistake (once you fix the data register's address).

Hmm... or ide_tf_load()/ide_tf_read() is broken for big endian MIPS ?
(and possibly SPARC etc.)

__ide_mm_writesw(port, &data, 1) should be used instead of writew()
for IDE_TFLAG_OUT_DATA?

---
Atsushi Nemoto

From sshtylyov@ru.mvista.com Tue Sep 16 16:32:05 2008
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Subject: Re: [PATCH 1/2] ide: Add tx4939ide driver
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Atsushi Nemoto wrote:

>>>>   This doesn't look consistent (aside from the TX4939IDE_REG8/16 issue) 
>>>>-- mm_outsw_swap() calls cpu_to_le16() before writing 16-bit data but 
>>>>this code doesn't. So, either one of those should be wrong...

>>>Thanks, this code should be wrong.  IDE_TFLAG_OUT_DATA is totally
>>>untested...

>>   Hum, not necessarily...
>>   If the data register is BE, this should work correctly, if I don't 
>>mistake (once you fix the data register's address).

> Hmm... or ide_tf_load()/ide_tf_read() is broken for big endian MIPS ?
> (and possibly SPARC etc.)

    Probably it is. But hardly anybody cares -- as I said, that flag seems 
totally useless.

> __ide_mm_writesw(port, &data, 1) should be used instead of writew()
> for IDE_TFLAG_OUT_DATA?

MBR, Sergei

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	bzolnier@gmail.com, ralf@linux-mips.org
Subject: Re: [PATCH 1/2] ide: Add tx4939ide driver
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Hello.

Atsushi Nemoto wrote:

>>>>   This doesn't look consistent (aside from the TX4939IDE_REG8/16 issue) 
>>>>-- mm_outsw_swap() calls cpu_to_le16() before writing 16-bit data but 
>>>>this code doesn't. So, either one of those should be wrong...
>>>
>>>Thanks, this code should be wrong.  IDE_TFLAG_OUT_DATA is totally
>>>untested...
>>
>>   Hum, not necessarily...
>>   If the data register is BE, this should work correctly, if I don't 
>>mistake (once you fix the data register's address).

> Hmm... or ide_tf_load()/ide_tf_read() is broken for big endian MIPS ?
> (and possibly SPARC etc.)

> __ide_mm_writesw(port, &data, 1) should be used instead of writew()
> for IDE_TFLAG_OUT_DATA?

    Probably the code there relies on the writew() doing the necessary byte 
swapping -- the same as ata_{in|out}_data() must be reying on ins[wl]() and 
outs[wl]() to do that, as well as on __ide_mm_reads[wl]() and 
__ide_mm_writes[wl]() -- which boil down to reads[wl]() and writes[wl]() on MIPS.
    What's not clear to me is why in MIPS read[wlq]() vs reads[wlq](), 
write[wlq]() vs writes[wl], in[wlq]() vs ins[wlq](), and out[wlq]() vs 
outs[wlq]() are using the different byte swapping: the single form uses 
ioswab[wlq]() while the sting form uses __mem_ioswab[wlq]() -- and those are 
defined as one swapping bytes and the other not in 
incluse/asm-mips/mach-generic/mangle-port.h. Cananybody shed some light on this?

> ---
> Atsushi Nemoto

MBR, Sergei

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	linux-mips@linux-mips.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH] [MIPS] vr41xx: unsigned irq cannot be negative
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Sergei Shtylyov wrote:
> Hello.

>> @@ -79,8 +80,9 @@ static void irq_dispatch(unsigned int irq)
>>              desc->chip->mask(source_irq);
>>              desc->chip->ack(source_irq);
>>          }
>> -        irq = cascade->get_irq(irq);
>> -        if (irq < 0)
>> +        ret = cascade->get_irq(irq);
>> +        irq = ret;
>> +        if (ret < 0)
>>              atomic_inc(&irq_err_count);
>>          else
>>              irq_dispatch(irq);
>>   
> 
>  How about this:
> 
>         ret = cascade->get_irq(irq);
>         if (ret < 0)
>             atomic_inc(&irq_err_count);
>         else
>             irq_dispatch(ret);
> 
> 
> WBR, Sergei

good suggestion, but shouldn't we then remove source_irq
as well?

Signed-off-by: Roel Kluin <roel.kluin@gmail.com>
---
diff --git a/arch/mips/vr41xx/common/irq.c b/arch/mips/vr41xx/common/irq.c
index cba36a2..ab4e327 100644
--- a/arch/mips/vr41xx/common/irq.c
+++ b/arch/mips/vr41xx/common/irq.c
@@ -63,6 +63,7 @@ static void irq_dispatch(unsigned int irq)
 {
 	irq_cascade_t *cascade;
 	struct irq_desc *desc;
+	int ret;
 
 	if (irq >= NR_IRQS) {
 		atomic_inc(&irq_err_count);
@@ -71,21 +72,22 @@ static void irq_dispatch(unsigned int irq)
 
 	cascade = irq_cascade + irq;
 	if (cascade->get_irq != NULL) {
-		unsigned int source_irq = irq;
-		desc = irq_desc + source_irq;
+		desc = irq_desc + irq;
 		if (desc->chip->mask_ack)
-			desc->chip->mask_ack(source_irq);
+			desc->chip->mask_ack(irq);
 		else {
-			desc->chip->mask(source_irq);
-			desc->chip->ack(source_irq);
+			desc->chip->mask(irq);
+			desc->chip->ack(irq);
 		}
-		irq = cascade->get_irq(irq);
-		if (irq < 0)
+
+		ret = cascade->get_irq(irq);
+		if (ret < 0)
 			atomic_inc(&irq_err_count);
 		else
-			irq_dispatch(irq);
+			irq_dispatch(ret);
+
 		if (!(desc->status & IRQ_DISABLED) && desc->chip->unmask)
-			desc->chip->unmask(source_irq);
+			desc->chip->unmask(irq);
 	} else
 		do_IRQ(irq);
 }


From sshtylyov@ru.mvista.com Tue Sep 16 22:02:20 2008
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To:	Atsushi Nemoto <anemo@mba.ocn.ne.jp>
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	bzolnier@gmail.com, ralf@linux-mips.org
Subject: Re: [PATCH 1/2] ide: Add tx4939ide driver
References: <48CC3516.9080404@ru.mvista.com>	<20080914.220512.126760706.anemo@mba.ocn.ne.jp>	<48CF8A87.6030908@ru.mvista.com> <20080917.002034.27955909.anemo@mba.ocn.ne.jp> <48CFDDAD.4050209@ru.mvista.com>
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Hello, I wrote:

>>>>>   This doesn't look consistent (aside from the TX4939IDE_REG8/16 
>>>>> issue) -- mm_outsw_swap() calls cpu_to_le16() before writing 
>>>>> 16-bit data but this code doesn't. So, either one of those should 
>>>>> be wrong...
>>>>
>>>> Thanks, this code should be wrong.  IDE_TFLAG_OUT_DATA is totally
>>>> untested...
>>>
>>>   Hum, not necessarily...
>>>   If the data register is BE, this should work correctly, if I don't 
>>> mistake (once you fix the data register's address).
>
>> Hmm... or ide_tf_load()/ide_tf_read() is broken for big endian MIPS ?
>> (and possibly SPARC etc.)
>
>> __ide_mm_writesw(port, &data, 1) should be used instead of writew()
>> for IDE_TFLAG_OUT_DATA?
>
>    Probably the code there relies on the writew() doing the necessary 
> byte swapping -- the same as ata_{in|out}_data() must be reying on 
> ins[wl]() and outs[wl]() to do that, as well as on 
> __ide_mm_reads[wl]() and __ide_mm_writes[wl]() -- which boil down to 
> reads[wl]() and writes[wl]() on MIPS.
>    What's not clear to me is why in MIPS read[wlq]() vs reads[wlq](), 
> write[wlq]() vs writes[wl], in[wlq]() vs ins[wlq](), and out[wlq]() vs 
> outs[wlq]() are using the different byte swapping: the single form 
> uses ioswab[wlq]() while the sting form uses __mem_ioswab[wlq]() -- 
> and those are defined as one swapping bytes and the other not in 
> incluse/asm-mips/mach-generic/mangle-port.h. Cananybody shed some 
> light on this?

   Oh, I think I understand: the "single" versions take/return the value 
in host endian but the "string" version must treat the data as a stream 
of bytes.

MBR, Sergei



From sshtylyov@ru.mvista.com Tue Sep 16 22:16:05 2008
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	bzolnier@gmail.com, ralf@linux-mips.org
Subject: Re: [PATCH 1/2] ide: Add tx4939ide driver
References: <48CA8BEE.1090305@ru.mvista.com>	<20080913.005904.07457691.anemo@mba.ocn.ne.jp>	<48CAA498.9090804@ru.mvista.com> <20080913.213226.106262199.anemo@mba.ocn.ne.jp>
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Hello.

Atsushi Nemoto wrote:

>>> Well, let me explain a bit.  The datasheed say I should wait _both_
>>> XFERINT and HOST interrupt.  So, if only one of them was asserted, I
>>> mask it and wait another one.  But on the error case, only HOST was
>>> asserted and XFERINT was never asserted.  Then I could not exit from
>>> "waiting another one" state, until timeout.
>>>       
>>     Hmm, I got it: you decide whether it's worth waiting more for XFEREND 
>> interrupt based on whether ERR is set or not. I suppose IDE_INT doesn't get 
>> set in case the command gets endede with ERR set?
>>     
>
> IIRC, yes.  And anyway, the interrupt signal from this controller to
>   

Thats wrong -- According t the spec. the bit should be set following any 
assertion of INTRQ on IDE bus (possibly not at once though -- after 
flushing FIFO). Well, no wonder with such description of the bits as:


INT_IDE (RWC) [Interrupt]
Is “1” when data transfer completes. This bit is cleared by writing “1” 
to it.
When this bit is set to ‘1’, the following bits of the ATA Interrupt 
Controller Register will be
reset: bits [15:8] (Mask Address Error INT, Mask Reach Multiple INT, 
Mask DEV
Timing Error, Mask Ultra DMA DEV Terminate, Mask Timer INT, Mask Bus 
Error, Mask
Data Transfer End, Mask Host INT), and bits [1:0] (Data Transfer End, 
Host INT).

> CPU is not asserted because HOSTINT was masked by int_ctl register to
> wait for XFERINT interrupt.
>
> So, regardless of IDE_INT was set or not, no more interrupt raised to
> CPU.
>   

Ah, it gets purposedly masked out...

> Many of strangeness of interrupt handling in this driver is based on
> the fact that the IDE_INT bit in DMA status register does not refrect
> the controllers interrupt status directly.

It also seems to reflect the wrong status, i.e. that of the XFEREND 
interrupt...

> And the implementation of
> the IDE_INT bit is actually broken.  Claring the IDE_INT bit also
> clears all mask bits in int_ctl registers.  Usually this sort of
> behaviour is called "bug". ;)
>   

Hm, I thought that was done on purpose to "accelerate" interrupt 
handling or something... it can help indeed if you're not masking those 
interrupts.

> ---
> Atsushi Nemoto
>   

MBR, Sergei



From sshtylyov@ru.mvista.com Tue Sep 16 22:39:36 2008
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	bzolnier@gmail.com, ralf@linux-mips.org
Subject: Re: [PATCH 1/2] ide: Add tx4939ide driver
References: <48CA8BEE.1090305@ru.mvista.com>	<20080913.005904.07457691.anemo@mba.ocn.ne.jp>	<48CAA498.9090804@ru.mvista.com> <20080913.213226.106262199.anemo@mba.ocn.ne.jp> <48D0220B.4090601@ru.mvista.com>
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Hello, I wrote:

> Thats wrong -- According t the spec. the bit should be set following 
> any assertion of INTRQ on IDE bus (possibly not at once though -- 
> after flushing FIFO). Well, no wonder with such description of the 
> bits as:
>
>
> INT_IDE (RWC) [Interrupt]
> Is “1” when data transfer completes. This bit is cleared by writing 
> “1” to it.
> When this bit is set to ‘1’, the following bits of the ATA Interrupt 
> Controller Register will be
> reset: bits [15:8] (Mask Address Error INT, Mask Reach Multiple INT, 
> Mask DEV
> Timing Error, Mask Ultra DMA DEV Terminate, Mask Timer INT, Mask Bus 
> Error, Mask
> Data Transfer End, Mask Host INT), and bits [1:0] (Data Transfer End, 
> Host INT).

   Forgot to mentiom that from this description it's not even clear if 
the int_ctl register bits are cleared when 1 is written to this bit or 
when the controller sets it. :-)

MBR, Sergei



From sshtylyov@ru.mvista.com Tue Sep 16 22:59:33 2008
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To:	Atsushi Nemoto <anemo@mba.ocn.ne.jp>
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	Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>,
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Subject: Re: [PATCH 1/2] ide: Add tx4939ide driver
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Hello.

Atsushi Nemoto wrote:

> This is the driver for the Toshiba TX4939 SoC ATA controller.
>
> This controller has standard ATA taskfile registers and DMA
> command/status registers, but the register layout is swapped on big
> endian.  There are some other endian issue and some special registers
> which requires many custom dma_ops/port_ops routines.
>
> Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
>   
[...]
> diff --git a/drivers/ide/mips/tx4939ide.c b/drivers/ide/mips/tx4939ide.c
> new file mode 100644
> index 0000000..ba9776d
> --- /dev/null
> +++ b/drivers/ide/mips/tx4939ide.c
> @@ -0,0 +1,762 @@
>   
[...]
> +static int __tx4939ide_dma_setup(ide_drive_t *drive)
> +{
> +	ide_hwif_t *hwif = drive->hwif;
> +	struct request *rq = HWGROUP(drive)->rq;
> +	unsigned int reading;
> +	u8 dma_stat;
> +	unsigned long base = TX4939IDE_BASE(hwif);
> +
> +	if (rq_data_dir(rq))
> +		reading = 0;
> +	else
> +		reading = 1 << 3;
> +
> +	/* fall back to pio! */
> +	if (!ide_build_dmatable(drive, rq)) {
> +		ide_map_sg(drive, rq);
> +		return 1;
> +	}
> +#ifdef __BIG_ENDIAN
> +	{
> +		unsigned int *table = hwif->dmatable_cpu;
>   

   s/unsigned int/__le32/ perhaps?

> +		while (1) {
> +			cpu_to_le64s((u64 *)table);
>   

   Wait, PRD is already already in LE format, so this should be 
le64_to_cpus().

> +			if (*table & 0x80000000)
>   

   Hum... you don't have to check that with ide_build_dmatable() 
returning the PRD count...

> +				break;
> +			table += 2;
> +		}
> +	}
> +#endif
>   

MBR, Sergei



From Weiwei.Wang@windriver.com Wed Sep 17 03:27:07 2008
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From:	Weiwei Wang <weiwei.wang@windriver.com>
To:	linux-mips@linux-mips.org, jgarzik@redhat.com, ralf@linux-mips.org
Subject: [PATCH] convert sbmac tx to spin_lock_irqsave to prevent early IRQ enable
Date:	Wed, 17 Sep 2008 10:25:37 +0800
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Netpoll will call the interrupt handler with interrupts
disabled when using kgdboe, so spin_lock_irqsave() should
be used instead of spin_lock_irq() to prevent interrupts
from being incorrectly enabled.

Signed-off-by: Weiwei Wang <weiwei.wang@windriver.com>
---
 drivers/net/sb1250-mac.c |   12 +++++++-----
 1 files changed, 7 insertions(+), 5 deletions(-)

diff --git a/drivers/net/sb1250-mac.c b/drivers/net/sb1250-mac.c
index fe41e4e..ce10cfa 100644
--- a/drivers/net/sb1250-mac.c
+++ b/drivers/net/sb1250-mac.c
@@ -2069,9 +2069,10 @@ static irqreturn_t sbmac_intr(int irq,void *dev_instance)
 static int sbmac_start_tx(struct sk_buff *skb, struct net_device *dev)
 {
 	struct sbmac_softc *sc = netdev_priv(dev);
+	unsigned long flags;
 
 	/* lock eth irq */
-	spin_lock_irq (&sc->sbm_lock);
+	spin_lock_irqsave(&sc->sbm_lock, flags);
 
 	/*
 	 * Put the buffer on the transmit ring.  If we
@@ -2081,14 +2082,14 @@ static int sbmac_start_tx(struct sk_buff *skb, struct net_device *dev)
 	if (sbdma_add_txbuffer(&(sc->sbm_txdma),skb)) {
 		/* XXX save skb that we could not send */
 		netif_stop_queue(dev);
-		spin_unlock_irq(&sc->sbm_lock);
+		spin_unlock_irqrestore(&sc->sbm_lock, flags);
 
 		return 1;
 	}
 
 	dev->trans_start = jiffies;
 
-	spin_unlock_irq (&sc->sbm_lock);
+	spin_unlock_irqrestore(&sc->sbm_lock, flags);
 
 	return 0;
 }
@@ -2568,14 +2569,15 @@ static void sbmac_mii_poll(struct net_device *dev)
 static void sbmac_tx_timeout (struct net_device *dev)
 {
 	struct sbmac_softc *sc = netdev_priv(dev);
+	unsigned long flags;
 
-	spin_lock_irq (&sc->sbm_lock);
+	spin_lock_irqsave(&sc->sbm_lock, flags);
 
 
 	dev->trans_start = jiffies;
 	dev->stats.tx_errors++;
 
-	spin_unlock_irq (&sc->sbm_lock);
+	spin_unlock_irqrestore(&sc->sbm_lock, flags);
 
 	printk (KERN_WARNING "%s: Transmit timed out\n",dev->name);
 }
-- 
1.5.5.1


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From:	Bryan Phillippe <u1@terran.org>
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Subject: MIPS checksum bug
Date:	Tue, 16 Sep 2008 22:15:41 -0700
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Hello,

It appears that the following problem once reported for Sparc64  
affects MIPS/64 as well:

original report: http://www.spinics.net/lists/sparclinux/msg00173.html
resolution: http://www.spinics.net/lists/sparclinux/msg00179.html

The net result is that when TCP fragments unacked segments due to PMTU  
discovery, the shortened segment can have a bad TCP csum.  I'm testing  
on Linux-2.6.26 (FWIW, on a Cavium CN3010).  My repro is fairly  
simple: MIPS/64 client behind a Linux router, where the Linux router  
has an outbound MTU of 1492.  When the client attempts to send  
segments of size 1460 (1500), the router sends back an ICMP  
unreachable/PMTU and the client resends the first portion of the  
segment reduced to 1452 (1492), and the segments *often* (but not  
always) have a bad TCP csum.  Note that you can't have hardware  
checksums enabled or the bug is masked.

I've experimented with the following change:

--- /home/bp/tmp/csum_partial.S.orig	2008-09-16 12:01:00.000000000 -0700
+++ arch/mips/lib/csum_partial.S	2008-09-16 11:51:44.000000000 -0700
@@ -281,6 +281,23 @@
	.set	reorder
	/* Add the passed partial csum.  */
	ADDC(sum, a2)
+
+	/* fold checksum again to clear the high bits before returning */
+	.set	push
+	.set	noat
+#ifdef USE_DOUBLE
+	dsll32	v1, sum, 0
+	daddu	sum, v1
+	sltu	v1, sum, v1
+	dsra32	sum, sum, 0
+	addu	sum, v1
+#endif
+	sll	v1, sum, 16
+	addu	sum, v1
+	sltu	v1, sum, v1
+	srl	sum, sum, 16
+	addu	sum, v1
+
	jr	ra
	.set	noreorder
	END(csum_partial)

and it seems to fix the problem for me.  Can you comment?

Thanks,
--
-bp


From macro@linux-mips.org Wed Sep 17 11:40:18 2008
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From:	"Maciej W. Rozycki" <macro@linux-mips.org>
To:	Bryan Phillippe <u1@terran.org>
cc:	linux-mips@linux-mips.org
Subject: Re: MIPS checksum bug
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On Tue, 16 Sep 2008, Bryan Phillippe wrote:

> I've experimented with the following change:
> 
> --- /home/bp/tmp/csum_partial.S.orig	2008-09-16 12:01:00.000000000 -0700
> +++ arch/mips/lib/csum_partial.S	2008-09-16 11:51:44.000000000 -0700
> @@ -281,6 +281,23 @@
> 	.set	reorder
> 	/* Add the passed partial csum.  */
> 	ADDC(sum, a2)
> +
> +	/* fold checksum again to clear the high bits before returning */
> +	.set	push
> +	.set	noat
> +#ifdef USE_DOUBLE
> +	dsll32	v1, sum, 0
> +	daddu	sum, v1
> +	sltu	v1, sum, v1
> +	dsra32	sum, sum, 0
> +	addu	sum, v1
> +#endif
> +	sll	v1, sum, 16
> +	addu	sum, v1
> +	sltu	v1, sum, v1
> +	srl	sum, sum, 16
> +	addu	sum, v1
> +
> 	jr	ra
> 	.set	noreorder
> 	END(csum_partial)
> 
> and it seems to fix the problem for me.  Can you comment?

 It seems obvious that a carry from the bit #15 in the last addition of
the passed checksum -- ADDC(sum, a2) -- will negate the effect of the
folding.  However a simpler fix should do as well.  Try if the following
patch works for you.  Please note this is completely untested and further
optimisation is possible, but I've skipped it in this version for clarity.

 Thanks for raising the issue.

  Maciej

Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
--- a/arch/mips/lib/csum_partial.S	2008-05-05 02:55:23.000000000 
+0000
+++ b/arch/mips/lib/csum_partial.S	2008-09-17 10:32:37.000000000 
+0000
@@ -253,6 +253,9 @@ LEAF(csum_partial)
 
 1:	ADDC(sum, t1)
 
+	/* Add the passed partial csum.  */
+	ADDC(sum, a2)
+
 	/* fold checksum */
 	.set	push
 	.set	noat
@@ -278,11 +281,8 @@ LEAF(csum_partial)
 	andi	sum, 0xffff
 	.set	pop
 1:
-	.set	reorder
-	/* Add the passed partial csum.  */
-	ADDC(sum, a2)
 	jr	ra
-	.set	noreorder
+	 nop
 	END(csum_partial)
 
 

From jgarzik@redhat.com Wed Sep 17 12:40:59 2008
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From:	Jeff Garzik <jgarzik@redhat.com>
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On Wed, Sep 17, 2008 at 10:25:37AM +0800, Weiwei Wang wrote:
> Netpoll will call the interrupt handler with interrupts
> disabled when using kgdboe, so spin_lock_irqsave() should
> be used instead of spin_lock_irq() to prevent interrupts
> from being incorrectly enabled.
> 
> Signed-off-by: Weiwei Wang <weiwei.wang@windriver.com>
> ---
>  drivers/net/sb1250-mac.c |   12 +++++++-----
>  1 files changed, 7 insertions(+), 5 deletions(-)

Please send to jeff@garzik.org or jgarzik@pobox.com.

	Jeff




From anemo@mba.ocn.ne.jp Wed Sep 17 14:23:45 2008
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Subject: Re: MIPS checksum bug
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On Wed, 17 Sep 2008 11:40:01 +0100 (BST), "Maciej W. Rozycki" <macro@linux-mips.org> wrote:
> > and it seems to fix the problem for me.  Can you comment?
> 
>  It seems obvious that a carry from the bit #15 in the last addition of
> the passed checksum -- ADDC(sum, a2) -- will negate the effect of the
> folding.  However a simpler fix should do as well.  Try if the following
> patch works for you.  Please note this is completely untested and further
> optimisation is possible, but I've skipped it in this version for clarity.

Well, csum_partial()'s return value is __wsum (32-bit).  So strictly
there is no need to folding into 16-bit.

I think this bug was introduced by my commit
ed99e2bc1dc5dc54eb5a019f4975562dbef20103 ("[MIPS] Optimize
csum_partial for 64bit kernel").  This commit changed ADDC to using
daddu for 64-bit kernel and that was wrong for the last addition of
partial csum which should be 32-bit addition.

Here is my proposal fix.  Bryan, could you try it too?

diff --git a/arch/mips/lib/csum_partial.S b/arch/mips/lib/csum_partial.S
index 8d77841..8b15766 100644
--- a/arch/mips/lib/csum_partial.S
+++ b/arch/mips/lib/csum_partial.S
@@ -60,6 +60,14 @@
 	ADD	sum, v1;					\
 	.set	pop
 
+#define ADDC32(sum,reg)						\
+	.set	push;						\
+	.set	noat;						\
+	addu	sum, reg;					\
+	sltu	v1, sum, reg;					\
+	addu	sum, v1;					\
+	.set	pop
+
 #define CSUM_BIGCHUNK1(src, offset, sum, _t0, _t1, _t2, _t3)	\
 	LOAD	_t0, (offset + UNIT(0))(src);			\
 	LOAD	_t1, (offset + UNIT(1))(src);			\
@@ -280,7 +288,7 @@ LEAF(csum_partial)
 1:
 	.set	reorder
 	/* Add the passed partial csum.  */
-	ADDC(sum, a2)
+	ADDC32(sum, a2)
 	jr	ra
 	.set	noreorder
 	END(csum_partial)
@@ -681,7 +689,7 @@ EXC(	sb	t0, NBYTES-2(dst), .Ls_exc)
 	.set	pop
 1:
 	.set reorder
-	ADDC(sum, psum)
+	ADDC32(sum, psum)
 	jr	ra
 	.set noreorder
 

From macro@linux-mips.org Wed Sep 17 15:47:54 2008
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On Wed, 17 Sep 2008, Atsushi Nemoto wrote:

> On Wed, 17 Sep 2008 11:40:01 +0100 (BST), "Maciej W. Rozycki" <macro@linux-mips.org> wrote:
> > > and it seems to fix the problem for me.  Can you comment?
> > 
> >  It seems obvious that a carry from the bit #15 in the last addition of
> > the passed checksum -- ADDC(sum, a2) -- will negate the effect of the
> > folding.  However a simpler fix should do as well.  Try if the following
> > patch works for you.  Please note this is completely untested and further
> > optimisation is possible, but I've skipped it in this version for clarity.
> 
> Well, csum_partial()'s return value is __wsum (32-bit).  So strictly
> there is no need to folding into 16-bit.

 Hmm, what's the purpose of doing the fold in csum_partial() then?

 Anyway, having looked at the code again the byte swap at the end means
the passed checksum should be added afterwards, so my proposal is
incorrect.  Your suggestion to use 32-bit addition in all cases is 
certainly valid.

  Maciej

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On Wed, 17 Sep 2008 01:59:24 +0400, Sergei Shtylyov <sshtylyov@ru.mvista.com> wrote:
> > +		unsigned int *table = hwif->dmatable_cpu;
> >   
> 
>    s/unsigned int/__le32/ perhaps?

Yes.  And __le64 would be much better.

> > +		while (1) {
> > +			cpu_to_le64s((u64 *)table);
> >   
> 
>    Wait, PRD is already already in LE format, so this should be 
> le64_to_cpus().

OK.

> > +			if (*table & 0x80000000)
> >   
> 
>    Hum... you don't have to check that with ide_build_dmatable() 
> returning the PRD count...

Indeed.  I'll do it.  Thanks.

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	Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>,
	ralf@linux-mips.org, sshtylyov@ru.mvista.com
Subject: [PATCH 2/2] TXx9: Add TX4939 ATA support (v2)
From:	Atsushi Nemoto <anemo@mba.ocn.ne.jp>
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Add a helper routine to register tx4939ide driver and use it on
RBTX4939 board.

Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
---
This patch is against linux-next 20080916.

Changes since v1:
* Use static resource arrays and platform_device array.

 arch/mips/txx9/generic/setup_tx4939.c |   46 +++++++++++++++++++++++++++++++++
 arch/mips/txx9/rbtx4939/setup.c       |    1 +
 include/asm-mips/txx9/tx4939.h        |    1 +
 3 files changed, 48 insertions(+), 0 deletions(-)

diff --git a/arch/mips/txx9/generic/setup_tx4939.c b/arch/mips/txx9/generic/setup_tx4939.c
index f14a497..6c0049a 100644
--- a/arch/mips/txx9/generic/setup_tx4939.c
+++ b/arch/mips/txx9/generic/setup_tx4939.c
@@ -20,6 +20,7 @@
 #include <linux/param.h>
 #include <linux/ptrace.h>
 #include <linux/mtd/physmap.h>
+#include <linux/platform_device.h>
 #include <asm/bootinfo.h>
 #include <asm/reboot.h>
 #include <asm/traps.h>
@@ -389,6 +390,51 @@ void __init tx4939_mtd_init(int ch)
 	txx9_physmap_flash_init(ch, start, size, &pdata);
 }
 
+#define TX4939_ATA_REG_PHYS(ch) (TX4939_ATA_REG(ch) & 0xfffffffffULL)
+void __init tx4939_ata_init(void)
+{
+	static struct resource ata0_res[] = {
+		{
+			.start = TX4939_ATA_REG_PHYS(0),
+			.end = TX4939_ATA_REG_PHYS(0) + 0x1000 - 1,
+			.flags = IORESOURCE_MEM,
+		}, {
+			.start = TXX9_IRQ_BASE + TX4939_IR_ATA(0),
+			.flags = IORESOURCE_IRQ,
+		},
+	};
+	static struct resource ata1_res[] = {
+		{
+			.start = TX4939_ATA_REG_PHYS(1),
+			.end = TX4939_ATA_REG_PHYS(1) + 0x1000 - 1,
+			.flags = IORESOURCE_MEM,
+		}, {
+			.start = TXX9_IRQ_BASE + TX4939_IR_ATA(1),
+			.flags = IORESOURCE_IRQ,
+		},
+	};
+	static struct platform_device ata0_dev = {
+		.name = "tx4939ide",
+		.id = 0,
+		.num_resources = ARRAY_SIZE(ata0_res),
+		.resource = ata0_res,
+	};
+	static struct platform_device ata1_dev = {
+		.name = "tx4939ide",
+		.id = 1,
+		.num_resources = ARRAY_SIZE(ata1_res),
+		.resource = ata1_res,
+	};
+	__u64 pcfg = __raw_readq(&tx4939_ccfgptr->pcfg);
+
+	if (pcfg & TX4939_PCFG_ATA0MODE)
+		platform_device_register(&ata0_dev);
+	if ((pcfg & (TX4939_PCFG_ATA1MODE |
+		     TX4939_PCFG_ET1MODE |
+		     TX4939_PCFG_ET0MODE)) == TX4939_PCFG_ATA1MODE)
+		platform_device_register(&ata1_dev);
+}
+
 static void __init tx4939_stop_unused_modules(void)
 {
 	__u64 pcfg, rst = 0, ckd = 0;
diff --git a/arch/mips/txx9/rbtx4939/setup.c b/arch/mips/txx9/rbtx4939/setup.c
index 277864d..9855d7b 100644
--- a/arch/mips/txx9/rbtx4939/setup.c
+++ b/arch/mips/txx9/rbtx4939/setup.c
@@ -264,6 +264,7 @@ static void __init rbtx4939_device_init(void)
 #endif
 	rbtx4939_led_setup();
 	tx4939_wdt_init();
+	tx4939_ata_init();
 }
 
 static void __init rbtx4939_setup(void)
diff --git a/include/asm-mips/txx9/tx4939.h b/include/asm-mips/txx9/tx4939.h
index 7ce2dff..88badb4 100644
--- a/include/asm-mips/txx9/tx4939.h
+++ b/include/asm-mips/txx9/tx4939.h
@@ -540,5 +540,6 @@ void tx4939_setup_pcierr_irq(void);
 void tx4939_irq_init(void);
 int tx4939_irq(void);
 void tx4939_mtd_init(int ch);
+void tx4939_ata_init(void);
 
 #endif /* __ASM_TXX9_TX4939_H */
-- 
1.5.6.3

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To:	linux-mips@linux-mips.org
Cc:	linux-ide@vger.kernel.org,
	Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>,
	ralf@linux-mips.org, sshtylyov@ru.mvista.com
Subject: [PATCH 1/2] ide: Add tx4939ide driver (v2)
From:	Atsushi Nemoto <anemo@mba.ocn.ne.jp>
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This is the driver for the Toshiba TX4939 SoC ATA controller.

This controller has standard ATA taskfile registers and DMA
command/status registers, but the register layout is swapped on big
endian.  There are some other endian issue and some special registers
which requires many custom dma_ops/port_ops routines.

Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
---
This patch is against linux-next 20080916.

Changes since v1:
* rework IO accessors
* rework pio/dma timing setup
* use ide_get_pair_dev
* do not do ATA hard reset
* and so on  (Many thanks to Sergei)

 drivers/ide/Kconfig          |    6 +
 drivers/ide/mips/Makefile    |    1 +
 drivers/ide/mips/tx4939ide.c |  744 ++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 751 insertions(+), 0 deletions(-)
 create mode 100644 drivers/ide/mips/tx4939ide.c

diff --git a/drivers/ide/Kconfig b/drivers/ide/Kconfig
index 325461c..0ed731a 100644
--- a/drivers/ide/Kconfig
+++ b/drivers/ide/Kconfig
@@ -736,6 +736,12 @@ config BLK_DEV_IDE_AU1XXX_SEQTS_PER_RQ
        default "128"
        depends on BLK_DEV_IDE_AU1XXX
 
+config BLK_DEV_IDE_TX4939
+	tristate "TX4939 internal IDE support"
+	depends on SOC_TX4939
+	select BLK_DEV_IDEDMA_SFF
+	select IDE_TIMINGS
+
 config IDE_ARM
 	tristate "ARM IDE support"
 	depends on ARM && (ARCH_CLPS7500 || ARCH_RPC || ARCH_SHARK)
diff --git a/drivers/ide/mips/Makefile b/drivers/ide/mips/Makefile
index 677c7b2..1e0ad98 100644
--- a/drivers/ide/mips/Makefile
+++ b/drivers/ide/mips/Makefile
@@ -1,4 +1,5 @@
 obj-$(CONFIG_BLK_DEV_IDE_SWARM)		+= swarm.o
 obj-$(CONFIG_BLK_DEV_IDE_AU1XXX)	+= au1xxx-ide.o
+obj-$(CONFIG_BLK_DEV_IDE_TX4939)	+= tx4939ide.o
 
 EXTRA_CFLAGS    := -Idrivers/ide
diff --git a/drivers/ide/mips/tx4939ide.c b/drivers/ide/mips/tx4939ide.c
new file mode 100644
index 0000000..e008e1e
--- /dev/null
+++ b/drivers/ide/mips/tx4939ide.c
@@ -0,0 +1,744 @@
+/*
+ * TX4939 internal IDE driver
+ * Based on RBTX49xx patch from CELF patch archive.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * (C) Copyright TOSHIBA CORPORATION 2005-2007
+ */
+
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/ide.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+
+#define MODNAME	"tx4939ide"
+
+/* ATA Shadow Registers (8bit except for DATA which is 16bit) */
+#define TX4939IDE_DATA	0x000
+#define TX4939IDE_Error_Ft	0x001
+#define TX4939IDE_Sec	0x002
+#define TX4939IDE_LBA0	0x003
+#define TX4939IDE_LBA1	0x004
+#define TX4939IDE_LBA2	0x005
+#define TX4939IDE_Device	0x006
+#define TX4939IDE_St_Cmd	0x007
+#define TX4939IDE_Alt_DevCtl	0x402
+/* H/W DMA Registers  */
+#define TX4939IDE_DMA_Cmd	0x800	/* 8bit */
+#define TX4939IDE_DMA_stat	0x802	/* 8bit */
+#define TX4939IDE_PRD_Ptr	0x804	/* 32bit */
+/* ATA100 CORE Registers (16bit) */
+#define TX4939IDE_Sys_Ctl	0xc00
+#define TX4939IDE_Xfer_Cnt_1	0xc08
+#define TX4939IDE_Xfer_Cnt_2	0xc0a
+#define TX4939IDE_Sec_Cnt	0xc10
+#define TX4939IDE_Strt_AddL	0xc18
+#define TX4939IDE_Strt_AddU	0xc20
+#define TX4939IDE_Add_Ctl	0xc28
+#define TX4939IDE_Lo_BCnt	0xc30
+#define TX4939IDE_Up_BCnt	0xc38
+#define TX4939IDE_PIO_Acc	0xc88
+#define TX4939IDE_H_Rst_Tim	0xc90
+#define TX4939IDE_int_ctl	0xc98
+#define TX4939IDE_Pkt_Cmd	0xcb8
+#define TX4939IDE_Bxfer_cntH	0xcc0
+#define TX4939IDE_Bxfer_cntL	0xcc8
+#define TX4939IDE_Dev_TErr	0xcd0
+#define TX4939IDE_Pkt_xfer_ct	0xcd8
+#define TX4939IDE_Strt_AddT	0xce0
+
+/* bits for int_ctl */
+#define TX4939IDE_INT_ADDRERR	0x80
+#define TX4939IDE_INT_REACHMUL	0x40
+#define TX4939IDE_INT_DEVTIMING	0x20
+#define TX4939IDE_INT_UDMATERM	0x10
+#define TX4939IDE_INT_TIMER	0x08
+#define TX4939IDE_INT_BUSERR	0x04
+#define TX4939IDE_INT_XFEREND	0x02
+#define TX4939IDE_INT_HOST	0x01
+
+#define TX4939IDE_IGNORE_INTS	\
+	(TX4939IDE_INT_ADDRERR | TX4939IDE_INT_REACHMUL | \
+	 TX4939IDE_INT_DEVTIMING | TX4939IDE_INT_UDMATERM | \
+	 TX4939IDE_INT_TIMER)
+
+#ifdef __BIG_ENDIAN
+#define tx4939ide_swizzlel(a)	((a) ^ 4)
+#define tx4939ide_swizzlew(a)	((a) ^ 6)
+#define tx4939ide_swizzleb(a)	((a) ^ 7)
+#else
+#define tx4939ide_swizzlel(a)	(a)
+#define tx4939ide_swizzlew(a)	(a)
+#define tx4939ide_swizzleb(a)	(a)
+#endif
+
+static u16 tx4939ide_readw(void __iomem *base, u32 reg)
+{
+	return __raw_readw(base + tx4939ide_swizzlew(reg));
+}
+static u8 tx4939ide_readb(void __iomem *base, u32 reg)
+{
+	return __raw_readb(base + tx4939ide_swizzleb(reg));
+}
+static void tx4939ide_writel(u32 val, void __iomem *base, u32 reg)
+{
+	__raw_writel(val, base + tx4939ide_swizzlel(reg));
+}
+static void tx4939ide_writew(u16 val, void __iomem *base, u32 reg)
+{
+	__raw_writew(val, base + tx4939ide_swizzlew(reg));
+}
+static void tx4939ide_writeb(u8 val, void __iomem *base, u32 reg)
+{
+	__raw_writeb(val, base + tx4939ide_swizzleb(reg));
+}
+
+#define TX4939IDE_BASE(hwif)	((void __iomem *)(hwif)->extra_base)
+
+static void tx4939ide_selectproc(ide_drive_t *drive)
+{
+	ide_hwif_t *hwif = HWIF(drive);
+	void __iomem *base = TX4939IDE_BASE(hwif);
+	int is_slave = drive->dn & 1;
+
+	/* set selected transfer mode */
+	tx4939ide_writew(hwif->select_data >> (is_slave ? 16 : 0),
+			 base, TX4939IDE_Sys_Ctl);
+}
+
+static void tx4939ide_set_pio_mode(ide_drive_t *drive, const u8 pio)
+{
+	ide_hwif_t *hwif = HWIF(drive);
+	int is_slave = drive->dn & 1;
+	u32 mask, val;
+	u8 safe = pio;
+	ide_drive_t *pair;
+
+	pair = ide_get_pair_dev(drive);
+	if (pair)
+		safe = min(safe, ide_get_best_pio_mode(pair, 255, 4));
+	/*
+	 * Update Command Transfer Mode for master/slave and Data
+	 * Transfer Mode for this drive.
+	 */
+	mask = is_slave ? 0x07f00700 : 0x070007f0;
+	val = (safe << 24) | (safe << 8) | (pio << (is_slave ? 20 : 4));
+	hwif->select_data = (hwif->select_data & ~mask) | val;
+	tx4939ide_selectproc(drive);
+}
+
+static void tx4939ide_set_dma_mode(ide_drive_t *drive, const u8 mode)
+{
+	ide_hwif_t *hwif = HWIF(drive);
+	int is_slave = drive->dn & 1;
+	u32 mask, val;
+
+	/* Update Data Transfer Mode for this drive. */
+	mask = 0x00f0;
+	if (mode >= XFER_UDMA_0)
+		val = 8 + (mode - XFER_UDMA_0);
+	else if (mode >= XFER_MW_DMA_0)
+		val = 5 + (mode - XFER_MW_DMA_0);
+	else
+		val = mode - XFER_PIO_0;
+	val <<= 4;
+	if (is_slave) {
+		mask <<= 16;
+		val <<= 16;
+	}
+	hwif->select_data = (hwif->select_data & ~mask) | val;
+	tx4939ide_selectproc(drive);
+}
+
+static void tx4939ide_check_error_ints(ide_hwif_t *hwif, u16 stat)
+{
+	if (stat & TX4939IDE_INT_BUSERR) {
+		void __iomem *base = TX4939IDE_BASE(hwif);
+		/* reset FIFO */
+		tx4939ide_writew(tx4939ide_readw(base, TX4939IDE_Sys_Ctl) |
+				 0x4000,
+				 base, TX4939IDE_Sys_Ctl);
+		/* wait 12GBUSCLK (typ. 60ns @ GBUS200MHz) */
+		ndelay(400);
+		tx4939ide_writew(tx4939ide_readw(base, TX4939IDE_Sys_Ctl) &
+				 ~0x4000,
+				 base, TX4939IDE_Sys_Ctl);
+	}
+	if (stat & (TX4939IDE_INT_ADDRERR | TX4939IDE_INT_REACHMUL |
+		    TX4939IDE_INT_DEVTIMING | TX4939IDE_INT_BUSERR))
+		pr_err("%s: Error interrupt %#x (%s%s%s%s )\n",
+		       hwif->name, stat,
+		       (stat & TX4939IDE_INT_ADDRERR) ?
+		       " Address-Error" : "",
+		       (stat & TX4939IDE_INT_REACHMUL) ?
+		       " Reach-Multiple" : "",
+		       (stat & TX4939IDE_INT_DEVTIMING) ?
+		       " DEV-Timing" : "",
+		       (stat & TX4939IDE_INT_BUSERR) ?
+		       " Bus-Error" : "");
+}
+
+static void tx4939ide_clear_irq(ide_drive_t *drive)
+{
+	ide_hwif_t *hwif;
+	void __iomem *base;
+	u16 ctl;
+
+	/*
+	 * tx4939ide_dma_test_irq() and tx4939ide_dma_end() do all
+	 * jobs for DMA case.
+	 */
+	if (drive->waiting_for_dma)
+		return;
+	hwif = HWIF(drive);
+	base = TX4939IDE_BASE(hwif);
+	ctl = tx4939ide_readw(base, TX4939IDE_int_ctl);
+
+	tx4939ide_check_error_ints(hwif, ctl);
+	tx4939ide_writew(ctl, base, TX4939IDE_int_ctl);
+}
+
+static u8 tx4939ide_cable_detect(ide_hwif_t *hwif)
+{
+	void __iomem *base = TX4939IDE_BASE(hwif);
+
+	return (tx4939ide_readw(base, TX4939IDE_Sys_Ctl) & 0x2000) ?
+		ATA_CBL_PATA40 : ATA_CBL_PATA80;
+}
+
+#ifdef __BIG_ENDIAN
+static void tx4939ide_dma_host_set(ide_drive_t *drive, int on)
+{
+	ide_hwif_t *hwif	= HWIF(drive);
+	u8 unit			= drive->dn & 1;
+	void __iomem *base = TX4939IDE_BASE(hwif);
+	u8 dma_stat = tx4939ide_readb(base, TX4939IDE_DMA_stat);
+
+	if (on)
+		dma_stat |= (1 << (5 + unit));
+	else
+		dma_stat &= ~(1 << (5 + unit));
+
+	tx4939ide_writeb(dma_stat, base, TX4939IDE_DMA_stat);
+}
+#else
+#define tx4939ide_dma_host_set	ide_dma_host_set
+#endif
+
+static void tx4939ide_clear_dma_status(u8 dma_stat, void __iomem *base)
+{
+	/* clear INTR & ERROR flags */
+	tx4939ide_writeb(dma_stat | 6, base, TX4939IDE_DMA_stat);
+	/* recover intmask cleared by writing to bit2 of DMA_stat */
+	tx4939ide_writew(TX4939IDE_IGNORE_INTS << 8, base, TX4939IDE_int_ctl);
+}
+
+static int __tx4939ide_dma_setup(ide_drive_t *drive)
+{
+	ide_hwif_t *hwif = drive->hwif;
+	struct request *rq = HWGROUP(drive)->rq;
+	unsigned int reading;
+	u8 dma_stat;
+	void __iomem *base = TX4939IDE_BASE(hwif);
+	int nent;
+
+	if (rq_data_dir(rq))
+		reading = 0;
+	else
+		reading = 1 << 3;
+
+	/* fall back to pio! */
+	nent = ide_build_dmatable(drive, rq);
+	if (!nent) {
+		ide_map_sg(drive, rq);
+		return 1;
+	}
+#ifdef __BIG_ENDIAN
+	{
+		__le64 *table = (__le64 *)hwif->dmatable_cpu;
+
+		while (nent--)
+			le64_to_cpus(table++);
+	}
+#endif
+
+	/* PRD table */
+	tx4939ide_writel(hwif->dmatable_dma, base, TX4939IDE_PRD_Ptr);
+
+	/* specify r/w */
+	tx4939ide_writeb(reading, base, TX4939IDE_DMA_Cmd);
+
+	/* read DMA status for INTR & ERROR flags */
+	dma_stat = tx4939ide_readb(base, TX4939IDE_DMA_stat);
+
+	/* clear INTR & ERROR flags */
+	tx4939ide_clear_dma_status(dma_stat, base);
+
+	drive->waiting_for_dma = 1;
+	return 0;
+}
+
+static int tx4939ide_dma_setup(ide_drive_t *drive)
+{
+	ide_hwif_t *hwif = HWIF(drive);
+	void __iomem *base = TX4939IDE_BASE(hwif);
+	int err;
+
+	err = __tx4939ide_dma_setup(drive);
+	if (err)
+		return err;
+	tx4939ide_writew(SECTOR_SIZE / 2, base, (drive->dn & 1) ?
+			 TX4939IDE_Xfer_Cnt_2 : TX4939IDE_Xfer_Cnt_1);
+	tx4939ide_writew(HWGROUP(drive)->rq->nr_sectors, base,
+			 TX4939IDE_Sec_Cnt);
+	return 0;
+}
+
+static int tx4939ide_dma_end(ide_drive_t *drive)
+{
+	ide_hwif_t *hwif = drive->hwif;
+	u8 dma_stat = 0, dma_cmd = 0;
+	void __iomem *base = TX4939IDE_BASE(hwif);
+	u16 ctl = tx4939ide_readw(base, TX4939IDE_int_ctl);
+
+	drive->waiting_for_dma = 0;
+
+	/* get DMA command mode */
+	dma_cmd = tx4939ide_readb(base, TX4939IDE_DMA_Cmd);
+	/* stop DMA */
+	tx4939ide_writeb(dma_cmd & ~1, base, TX4939IDE_DMA_Cmd);
+
+	/* get DMA status */
+	dma_stat = tx4939ide_readb(base, TX4939IDE_DMA_stat);
+
+	/* clear the INTR & ERROR bits */
+	tx4939ide_clear_dma_status(dma_stat, base);
+
+	/* purge DMA mappings */
+	ide_destroy_dmatable(drive);
+	/* verify good DMA status */
+	wmb();
+
+	if ((dma_stat & 7) == 0 &&
+	    (ctl & (TX4939IDE_INT_XFEREND | TX4939IDE_INT_HOST)) ==
+	    (TX4939IDE_INT_XFEREND | TX4939IDE_INT_HOST)) {
+		/* INT_IDE lost... bug? */
+		pr_warning("%s: INT_IDE lost?", hwif->name);
+		return 0;
+	}
+	return (dma_stat & 7) != 4 ? (0x10 | dma_stat) : 0;
+}
+
+/* returns 1 if dma irq issued, 0 otherwise */
+static int tx4939ide_dma_test_irq(ide_drive_t *drive)
+{
+	ide_hwif_t *hwif = HWIF(drive);
+	void __iomem *base = TX4939IDE_BASE(hwif);
+	u16 ctl = tx4939ide_readw(base, TX4939IDE_int_ctl);
+	u8 dma_stat, stat;
+	u16 ide_int;
+	int found = 0;
+
+	tx4939ide_check_error_ints(hwif, ctl);
+	ide_int = ctl & (TX4939IDE_INT_XFEREND | TX4939IDE_INT_HOST);
+	switch (ide_int) {
+	case TX4939IDE_INT_HOST:
+		/* On error, XFEREND might not be asserted. */
+		stat = tx4939ide_readb(base, TX4939IDE_Alt_DevCtl);
+		if ((stat & (ATA_BUSY|ATA_DRQ|ATA_ERR)) == ATA_ERR) {
+			pr_err("%s: detect error %x in %s\n",
+			       drive->name, stat, __func__);
+			found = 1;
+		}
+		/* FALLTHRU */
+	case TX4939IDE_INT_XFEREND:
+		/*
+		 * If only one of XFERINT and HOST was asserted
+		 * (without error --- see above), mask this interrupt
+		 * and wait for an another one.  Note that write to
+		 * bit2 of DMA_stat will clear all mask bits.
+		 */
+		ctl |= ide_int << 8;
+		break;
+	case TX4939IDE_INT_HOST | TX4939IDE_INT_XFEREND:
+		dma_stat = tx4939ide_readb(base, TX4939IDE_DMA_stat);
+		if (!(dma_stat & 4))
+			pr_debug("%s: weird interrupt status. "
+				 "DMA_stat %#02x int_ctl %#04x\n",
+				 hwif->name, dma_stat, ctl);
+		found = 1;
+		break;
+	}
+	/*
+	 * Do not clear XFERINT, HOST now.  They will be cleared by
+	 * clearing bit2 of DMA_stat.
+	 */
+	ctl &= ~ide_int;
+	tx4939ide_writew(ctl, base, TX4939IDE_int_ctl);
+	return found;
+}
+
+static void tx4939ide_init_iops(ide_hwif_t *hwif)
+{
+	/* use extra_base for base address of the all registers */
+	hwif->extra_base = hwif->io_ports.data_addr & ~0xfff;
+}
+
+static void tx4939ide_init_hwif(ide_hwif_t *hwif)
+{
+	void __iomem *base = TX4939IDE_BASE(hwif);
+
+	/* Soft Reset */
+	tx4939ide_writew(0x8000, base, TX4939IDE_Sys_Ctl);
+	mmiowb();
+	udelay(1);	/* at least 20 UPSCLK (100ns for 200MHz GBUSCLK) */
+	tx4939ide_writew(0x0000, base, TX4939IDE_Sys_Ctl);
+	/* mask some interrupts and clear all interrupts */
+	tx4939ide_writew((TX4939IDE_IGNORE_INTS << 8) | 0xff, base,
+			 TX4939IDE_int_ctl);
+
+	tx4939ide_writew(0x0008, base, TX4939IDE_Lo_BCnt);
+	tx4939ide_writew(0, base, TX4939IDE_Up_BCnt);
+}
+
+static int tx4939ide_init_dma(ide_hwif_t *hwif, const struct ide_port_info *d)
+{
+	hwif->dma_base = (unsigned long)TX4939IDE_BASE(hwif) +
+		tx4939ide_swizzleb(TX4939IDE_DMA_Cmd);
+	/*
+	 * Note that we cannot use ATA_DMA_TABLE_OFS,ATA_DMA_STATUS
+	 * for big endian.
+	 */
+	return ide_allocate_dma_engine(hwif);
+}
+
+static u8 tx4939ide_read_sff_dma_status(ide_hwif_t *hwif)
+{
+	void __iomem *base = TX4939IDE_BASE(hwif);
+	return tx4939ide_readb(base, TX4939IDE_DMA_stat);
+}
+
+#ifdef __BIG_ENDIAN
+/* custom iops (independent from SWAP_IO_SPACE) */
+static u8 mm_inb(unsigned long port)
+{
+	return (u8)__raw_readb((void __iomem *)port);
+}
+static void mm_outb(u8 value, unsigned long port)
+{
+	__raw_writeb(value, (void __iomem *)port);
+}
+static void mm_tf_load(ide_drive_t *drive, ide_task_t *task)
+{
+	ide_hwif_t *hwif = drive->hwif;
+	struct ide_io_ports *io_ports = &hwif->io_ports;
+	struct ide_taskfile *tf = &task->tf;
+	u8 HIHI = (task->tf_flags & IDE_TFLAG_LBA48) ? 0xE0 : 0xEF;
+
+	if (task->tf_flags & IDE_TFLAG_FLAGGED)
+		HIHI = 0xFF;
+
+	if (task->tf_flags & IDE_TFLAG_OUT_DATA) {
+		u16 data = (tf->hob_data << 8) | tf->data;
+
+		/* no endian swap */
+		__raw_writew(data, (void __iomem *)io_ports->data_addr);
+	}
+
+	if (task->tf_flags & IDE_TFLAG_OUT_HOB_FEATURE)
+		mm_outb(tf->hob_feature, io_ports->feature_addr);
+	if (task->tf_flags & IDE_TFLAG_OUT_HOB_NSECT)
+		mm_outb(tf->hob_nsect, io_ports->nsect_addr);
+	if (task->tf_flags & IDE_TFLAG_OUT_HOB_LBAL)
+		mm_outb(tf->hob_lbal, io_ports->lbal_addr);
+	if (task->tf_flags & IDE_TFLAG_OUT_HOB_LBAM)
+		mm_outb(tf->hob_lbam, io_ports->lbam_addr);
+	if (task->tf_flags & IDE_TFLAG_OUT_HOB_LBAH)
+		mm_outb(tf->hob_lbah, io_ports->lbah_addr);
+
+	if (task->tf_flags & IDE_TFLAG_OUT_FEATURE)
+		mm_outb(tf->feature, io_ports->feature_addr);
+	if (task->tf_flags & IDE_TFLAG_OUT_NSECT)
+		mm_outb(tf->nsect, io_ports->nsect_addr);
+	if (task->tf_flags & IDE_TFLAG_OUT_LBAL)
+		mm_outb(tf->lbal, io_ports->lbal_addr);
+	if (task->tf_flags & IDE_TFLAG_OUT_LBAM)
+		mm_outb(tf->lbam, io_ports->lbam_addr);
+	if (task->tf_flags & IDE_TFLAG_OUT_LBAH)
+		mm_outb(tf->lbah, io_ports->lbah_addr);
+
+	if (task->tf_flags & IDE_TFLAG_OUT_DEVICE)
+		mm_outb((tf->device & HIHI) | drive->select,
+			 io_ports->device_addr);
+}
+static void tx4939ide_tf_load(ide_drive_t *drive, ide_task_t *task)
+{
+	mm_tf_load(drive, task);
+	if (task->tf_flags & IDE_TFLAG_OUT_DEVICE) {
+		ide_hwif_t *hwif = drive->hwif;
+		void __iomem *base = TX4939IDE_BASE(hwif);
+		/* Fix ATA100 CORE System Control Register */
+		tx4939ide_writew(tx4939ide_readw(base, TX4939IDE_Sys_Ctl) &
+				 0x07f0,
+				 base, TX4939IDE_Sys_Ctl);
+	}
+}
+static void mm_tf_read(ide_drive_t *drive, ide_task_t *task)
+{
+	ide_hwif_t *hwif = drive->hwif;
+	struct ide_io_ports *io_ports = &hwif->io_ports;
+	struct ide_taskfile *tf = &task->tf;
+
+	if (task->tf_flags & IDE_TFLAG_IN_DATA) {
+		u16 data;
+
+		/* no endian swap */
+		data = __raw_readw((void __iomem *)io_ports->data_addr);
+		tf->data = data & 0xff;
+		tf->hob_data = (data >> 8) & 0xff;
+	}
+
+	/* be sure we're looking at the low order bits */
+	mm_outb(ATA_DEVCTL_OBS & ~0x80, io_ports->ctl_addr);
+
+	if (task->tf_flags & IDE_TFLAG_IN_FEATURE)
+		tf->feature = mm_inb(io_ports->feature_addr);
+	if (task->tf_flags & IDE_TFLAG_IN_NSECT)
+		tf->nsect  = mm_inb(io_ports->nsect_addr);
+	if (task->tf_flags & IDE_TFLAG_IN_LBAL)
+		tf->lbal   = mm_inb(io_ports->lbal_addr);
+	if (task->tf_flags & IDE_TFLAG_IN_LBAM)
+		tf->lbam   = mm_inb(io_ports->lbam_addr);
+	if (task->tf_flags & IDE_TFLAG_IN_LBAH)
+		tf->lbah   = mm_inb(io_ports->lbah_addr);
+	if (task->tf_flags & IDE_TFLAG_IN_DEVICE)
+		tf->device = mm_inb(io_ports->device_addr);
+
+	if (task->tf_flags & IDE_TFLAG_LBA48) {
+		mm_outb(ATA_DEVCTL_OBS | 0x80, io_ports->ctl_addr);
+
+		if (task->tf_flags & IDE_TFLAG_IN_HOB_FEATURE)
+			tf->hob_feature = mm_inb(io_ports->feature_addr);
+		if (task->tf_flags & IDE_TFLAG_IN_HOB_NSECT)
+			tf->hob_nsect   = mm_inb(io_ports->nsect_addr);
+		if (task->tf_flags & IDE_TFLAG_IN_HOB_LBAL)
+			tf->hob_lbal    = mm_inb(io_ports->lbal_addr);
+		if (task->tf_flags & IDE_TFLAG_IN_HOB_LBAM)
+			tf->hob_lbam    = mm_inb(io_ports->lbam_addr);
+		if (task->tf_flags & IDE_TFLAG_IN_HOB_LBAH)
+			tf->hob_lbah    = mm_inb(io_ports->lbah_addr);
+	}
+}
+
+static void mm_insw_swap(unsigned long port, void *addr, u32 count)
+{
+	unsigned short *ptr = addr;
+	unsigned long size = count * 2;
+	while (count--)
+		*ptr++ = cpu_to_le16(__raw_readw((void __iomem *)port));
+	__ide_flush_dcache_range((unsigned long)addr, size);
+}
+static void mm_outsw_swap(unsigned long port, void *addr, u32 count)
+{
+	unsigned short *ptr = addr;
+	unsigned long size = count * 2;
+	while (count--) {
+		__raw_writew(le16_to_cpu(*ptr), (void __iomem *)port);
+		ptr++;
+	}
+	__ide_flush_dcache_range((unsigned long)addr, size);
+}
+static void mmio_input_data_swap(ide_drive_t *drive, struct request *rq,
+				 void *buf, unsigned int len)
+{
+	mm_insw_swap(drive->hwif->io_ports.data_addr, buf, (len + 1) / 2);
+}
+static void mmio_output_data_swap(ide_drive_t *drive, struct request *rq,
+				  void *buf, unsigned int len)
+{
+	mm_outsw_swap(drive->hwif->io_ports.data_addr, buf, (len + 1) / 2);
+}
+
+static const struct ide_tp_ops tx4939ide_tp_ops = {
+	.exec_command		= ide_exec_command,
+	.read_status		= ide_read_status,
+	.read_altstatus		= ide_read_altstatus,
+	.read_sff_dma_status	= tx4939ide_read_sff_dma_status,
+
+	.set_irq		= ide_set_irq,
+
+	.tf_load		= tx4939ide_tf_load,
+	.tf_read		= mm_tf_read,
+
+	.input_data		= mmio_input_data_swap,
+	.output_data		= mmio_output_data_swap,
+};
+#else	/* __LITTLE_ENDIAN */
+static void tx4939ide_tf_load(ide_drive_t *drive, ide_task_t *task)
+{
+	ide_tf_load(drive, task);
+	if (task->tf_flags & IDE_TFLAG_OUT_DEVICE) {
+		ide_hwif_t *hwif = drive->hwif;
+		void __iomem *base = TX4939IDE_BASE(hwif);
+		/* Fix ATA100 CORE System Control Register */
+		tx4939ide_writew(tx4939ide_readw(base, TX4939IDE_Sys_Ctl) &
+				 0x07f0,
+				 base, TX4939IDE_Sys_Ctl);
+	}
+}
+static const struct ide_tp_ops tx4939ide_tp_ops = {
+	.exec_command		= ide_exec_command,
+	.read_status		= ide_read_status,
+	.read_altstatus		= ide_read_altstatus,
+	.read_sff_dma_status	= tx4939ide_read_sff_dma_status,
+
+	.set_irq		= ide_set_irq,
+
+	.tf_load		= tx4939ide_tf_load,
+	.tf_read		= ide_tf_read,
+
+	.input_data		= ide_input_data,
+	.output_data		= ide_output_data,
+};
+#endif	/* __LITTLE_ENDIAN */
+
+static const struct ide_port_ops tx4939ide_port_ops = {
+	.set_pio_mode = tx4939ide_set_pio_mode,
+	.set_dma_mode = tx4939ide_set_dma_mode,
+	.selectproc = tx4939ide_selectproc,
+	.clear_irq = tx4939ide_clear_irq,
+	.cable_detect = tx4939ide_cable_detect,
+};
+
+static const struct ide_dma_ops tx4939ide_dma_ops = {
+	.dma_host_set = tx4939ide_dma_host_set,
+	.dma_setup = tx4939ide_dma_setup,
+	.dma_exec_cmd = ide_dma_exec_cmd,
+	.dma_start = ide_dma_start,
+	.dma_end = tx4939ide_dma_end,
+	.dma_test_irq = tx4939ide_dma_test_irq,
+	.dma_lost_irq = ide_dma_lost_irq,
+	.dma_timeout = ide_dma_timeout,
+};
+
+static const struct ide_port_info tx4939ide_port_info __initdata = {
+	.init_iops = tx4939ide_init_iops,
+	.init_hwif = tx4939ide_init_hwif,
+	.init_dma = tx4939ide_init_dma,
+	.port_ops = &tx4939ide_port_ops,
+	.dma_ops = &tx4939ide_dma_ops,
+	.tp_ops = &tx4939ide_tp_ops,
+	.host_flags = IDE_HFLAG_MMIO,
+	.pio_mask = ATA_PIO4,
+	.mwdma_mask = ATA_MWDMA2,
+	.swdma_mask = 0,
+	.udma_mask = ATA_UDMA5,
+};
+
+static int __init tx4939ide_probe(struct platform_device *pdev)
+{
+	hw_regs_t hw;
+	hw_regs_t *hws[] = { &hw, NULL, NULL, NULL };
+	struct ide_host *host;
+	struct resource *res;
+	int irq;
+	unsigned long mapbase;
+	int ret;
+
+	irq = platform_get_irq(pdev, 0);
+	if (irq < 0)
+		return -ENODEV;
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!res)
+		return -ENODEV;
+
+	mapbase = (unsigned long)devm_ioremap(&pdev->dev, res->start,
+					      res->end - res->start + 1);
+	if (!mapbase)
+		return -EBUSY;
+	memset(&hw, 0, sizeof(hw));
+	hw.io_ports.data_addr =
+		mapbase + tx4939ide_swizzlew(TX4939IDE_DATA);
+	hw.io_ports.error_addr =
+		mapbase + tx4939ide_swizzleb(TX4939IDE_Error_Ft);
+	hw.io_ports.nsect_addr =
+		mapbase + tx4939ide_swizzleb(TX4939IDE_Sec);
+	hw.io_ports.lbal_addr =
+		mapbase + tx4939ide_swizzleb(TX4939IDE_LBA0);
+	hw.io_ports.lbam_addr =
+		mapbase + tx4939ide_swizzleb(TX4939IDE_LBA1);
+	hw.io_ports.lbah_addr =
+		mapbase + tx4939ide_swizzleb(TX4939IDE_LBA2);
+	hw.io_ports.device_addr =
+		mapbase + tx4939ide_swizzleb(TX4939IDE_Device);
+	hw.io_ports.command_addr =
+		mapbase + tx4939ide_swizzleb(TX4939IDE_St_Cmd);
+	hw.io_ports.ctl_addr =
+		mapbase + tx4939ide_swizzleb(TX4939IDE_Alt_DevCtl);
+	hw.irq = irq;
+	hw.dev = &pdev->dev;
+
+	pr_info("TX4939 IDE interface (%lx,%d)\n", mapbase, irq);
+	ret = ide_host_add(&tx4939ide_port_info, hws, &host);
+	if (ret)
+		return ret;
+	platform_set_drvdata(pdev, host);
+	return 0;
+}
+
+static int __exit tx4939ide_remove(struct platform_device *pdev)
+{
+	struct ide_host *host = platform_get_drvdata(pdev);
+
+	ide_host_remove(host);
+	return 0;
+}
+
+#ifdef CONFIG_PM
+static int tx4939ide_resume(struct platform_device *dev)
+{
+	struct ide_host *host = platform_get_drvdata(dev);
+	ide_hwif_t *hwif = host->ports[0];
+	void __iomem *base = TX4939IDE_BASE(hwif);
+
+	tx4939ide_init_hwif(hwif);
+
+	/* restore Sys_Ctl */
+	tx4939ide_writew(hwif->select_data & 0xffff, base, TX4939IDE_Sys_Ctl);
+	return 0;
+}
+#else
+#define tx4939ide_resume	NULL
+#endif
+
+static struct platform_driver tx4939ide_driver = {
+	.driver = {
+		.name = MODNAME,
+		.owner = THIS_MODULE,
+	},
+	.remove = __exit_p(tx4939ide_remove),
+	.resume = tx4939ide_resume,
+};
+
+static int __init tx4939ide_init(void)
+{
+	return platform_driver_probe(&tx4939ide_driver, tx4939ide_probe);
+}
+
+static void __exit tx4939ide_exit(void)
+{
+	platform_driver_unregister(&tx4939ide_driver);
+}
+
+module_init(tx4939ide_init);
+module_exit(tx4939ide_exit);
+
+MODULE_DESCRIPTION("TX4939 internal IDE driver");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:tx4939ide");
-- 
1.5.6.3

From anemo@mba.ocn.ne.jp Wed Sep 17 16:26:53 2008
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To:	macro@linux-mips.org
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Subject: Re: MIPS checksum bug
From:	Atsushi Nemoto <anemo@mba.ocn.ne.jp>
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On Wed, 17 Sep 2008 15:46:56 +0100 (BST), "Maciej W. Rozycki" <macro@linux-mips.org> wrote:
> > Well, csum_partial()'s return value is __wsum (32-bit).  So strictly
> > there is no need to folding into 16-bit.
> 
>  Hmm, what's the purpose of doing the fold in csum_partial() then?

Well, maybe odd-byte handling requires 16-bit holded values?

---
Atsushi Nemoto

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Date:	Wed, 17 Sep 2008 19:21:23 +0100 (BST)
From:	"Maciej W. Rozycki" <macro@linux-mips.org>
To:	Atsushi Nemoto <anemo@mba.ocn.ne.jp>
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On Thu, 18 Sep 2008, Atsushi Nemoto wrote:

> >  Hmm, what's the purpose of doing the fold in csum_partial() then?
> 
> Well, maybe odd-byte handling requires 16-bit holded values?

 It should be enough to swap odd and even bytes in the word in the
unaligned path.  Though perhaps extra code to do masking would make it no
shorter/faster than what we have now; however the aligned path would
benefit.  Hmm...

  Maciej

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Subject: Re: [PATCH] gpio_free might sleep, mips architecture
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On Mon, 15 Sep 2008 22:02:41 +0200
Uwe Kleine-K__nig <ukleinek@informatik.uni-freiburg.de> wrote:

> According to the documentation gpio_free should only be called from task
> context only.  To make this more explicit add a might sleep to all
> implementations.
> 
> This patch changes the gpio_free implementations for the mips
> architecture.
> 
> Signed-off-by: Uwe Kleine-K__nig <ukleinek@informatik.uni-freiburg.de>
> Cc: David Brownell <david-b@pacbell.net>
> Cc: Ralf Baechle <ralf@linux-mips.org>
> Cc: linux-mips@linux-mips.org
> Cc: Guennadi Liakhovetski <g.liakhovetski@pengutronix.de>
> Cc: Greg KH <greg@kroah.com>
> Cc: Kay Sievers <kay.sievers@vrfy.org>
> Cc: Andrew Morton <akpm@linux-foundation.org>
> Cc: Russell King <rmk+kernel@arm.linux.org.uk>
> ---
>  include/asm-mips/mach-au1x00/gpio.h  |    2 ++
>  include/asm-mips/mach-bcm47xx/gpio.h |    3 +++
>  include/asm-mips/mach-rc32434/gpio.h |    2 ++
>  3 files changed, 7 insertions(+), 0 deletions(-)
> 
> diff --git a/include/asm-mips/mach-au1x00/gpio.h b/include/asm-mips/mach-au1x00/gpio.h
> index 2dc61e0..31eddba 100644
> --- a/include/asm-mips/mach-au1x00/gpio.h
> +++ b/include/asm-mips/mach-au1x00/gpio.h
> @@ -1,6 +1,7 @@
>  #ifndef _AU1XXX_GPIO_H_
>  #define _AU1XXX_GPIO_H_
>  
> +#include <linux/kernel.h>
>  #include <linux/types.h>
>  
>  #define AU1XXX_GPIO_BASE	200
> @@ -31,6 +32,7 @@ static inline int gpio_request(unsigned gpio, const char *label)
>  static inline void gpio_free(unsigned gpio)
>  {
>  	/* Not yet implemented */
> +	might_sleep();
>  }
>  
>  static inline int gpio_direction_input(unsigned gpio)
> diff --git a/include/asm-mips/mach-bcm47xx/gpio.h b/include/asm-mips/mach-bcm47xx/gpio.h
> index cfc8f4d..af17ccd 100644
> --- a/include/asm-mips/mach-bcm47xx/gpio.h
> +++ b/include/asm-mips/mach-bcm47xx/gpio.h
> @@ -9,6 +9,8 @@
>  #ifndef __BCM47XX_GPIO_H
>  #define __BCM47XX_GPIO_H
>  
> +#include <linux/kernel.h>
> +
>  #define BCM47XX_EXTIF_GPIO_LINES	5
>  #define BCM47XX_CHIPCO_GPIO_LINES	16
>  
> @@ -25,6 +27,7 @@ static inline int gpio_request(unsigned gpio, const char *label)
>  
>  static inline void gpio_free(unsigned gpio)
>  {
> +	might_sleep();
>  }
>  
>  static inline int gpio_to_irq(unsigned gpio)
> diff --git a/include/asm-mips/mach-rc32434/gpio.h b/include/asm-mips/mach-rc32434/gpio.h
> index f946f5f..9b4722e 100644
> --- a/include/asm-mips/mach-rc32434/gpio.h
> +++ b/include/asm-mips/mach-rc32434/gpio.h
> @@ -13,6 +13,7 @@
>  #ifndef _RC32434_GPIO_H_
>  #define _RC32434_GPIO_H_
>  
> +#include <linux/kernel.h>
>  #include <linux/types.h>
>  
>  struct rb532_gpio_reg {
> @@ -88,6 +89,7 @@ static inline int gpio_request(unsigned gpio, const char *label)
>  static inline void gpio_free(unsigned gpio)
>  {
>  	/* Not yet implemented */
> +	might_sleep();
>  }
>  

There is no gpio_free() in linux-next's include/asm-mips/mach-rc32434/gpio.h

From jeff@garzik.org Wed Sep 17 22:58:52 2008
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Subject: Re: [PATCH 1/2] ide: Add tx4939ide driver (v2)
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Atsushi Nemoto wrote:
> This is the driver for the Toshiba TX4939 SoC ATA controller.
> 
> This controller has standard ATA taskfile registers and DMA
> command/status registers, but the register layout is swapped on big
> endian.  There are some other endian issue and some special registers
> which requires many custom dma_ops/port_ops routines.
> 
> Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
> ---
> This patch is against linux-next 20080916.
> 
> Changes since v1:
> * rework IO accessors
> * rework pio/dma timing setup
> * use ide_get_pair_dev
> * do not do ATA hard reset
> * and so on  (Many thanks to Sergei)
> 
>  drivers/ide/Kconfig          |    6 +
>  drivers/ide/mips/Makefile    |    1 +
>  drivers/ide/mips/tx4939ide.c |  744 ++++++++++++++++++++++++++++++++++++++++++
>  3 files changed, 751 insertions(+), 0 deletions(-)
>  create mode 100644 drivers/ide/mips/tx4939ide.c

I hope a libata driver is coming, too?



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Subject: Re: MIPS checksum bug
Date:	Wed, 17 Sep 2008 15:52:45 -0700
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Hello All,

I tested the simplified patch below (ADDC32), and it does not address  
the checksum bug.  I suspect the problem is that we're still leaving  
the carry bit in the upper 16 bits of the 32 bit csum returned, and  
this is resulting in a computed checksum that is 1 greater than it  
should be.  The upper 16 bits of the return value of this function  
must be 0, right?

Thanks,
--
-bp


On Sep 17, 2008, at 6:23 AM, Atsushi Nemoto wrote:

> On Wed, 17 Sep 2008 11:40:01 +0100 (BST), "Maciej W. Rozycki" <macro@linux-mips.org 
> > wrote:
>>> and it seems to fix the problem for me.  Can you comment?
>>
>> It seems obvious that a carry from the bit #15 in the last addition  
>> of
>> the passed checksum -- ADDC(sum, a2) -- will negate the effect of the
>> folding.  However a simpler fix should do as well.  Try if the  
>> following
>> patch works for you.  Please note this is completely untested and  
>> further
>> optimisation is possible, but I've skipped it in this version for  
>> clarity.
>
> Well, csum_partial()'s return value is __wsum (32-bit).  So strictly
> there is no need to folding into 16-bit.
>
> I think this bug was introduced by my commit
> ed99e2bc1dc5dc54eb5a019f4975562dbef20103 ("[MIPS] Optimize
> csum_partial for 64bit kernel").  This commit changed ADDC to using
> daddu for 64-bit kernel and that was wrong for the last addition of
> partial csum which should be 32-bit addition.
>
> Here is my proposal fix.  Bryan, could you try it too?
>
> diff --git a/arch/mips/lib/csum_partial.S b/arch/mips/lib/ 
> csum_partial.S
> index 8d77841..8b15766 100644
> --- a/arch/mips/lib/csum_partial.S
> +++ b/arch/mips/lib/csum_partial.S
> @@ -60,6 +60,14 @@
> 	ADD	sum, v1;					\
> 	.set	pop
>
> +#define ADDC32(sum,reg)						\
> +	.set	push;						\
> +	.set	noat;						\
> +	addu	sum, reg;					\
> +	sltu	v1, sum, reg;					\
> +	addu	sum, v1;					\
> +	.set	pop
> +
> #define CSUM_BIGCHUNK1(src, offset, sum, _t0, _t1, _t2, _t3)	\
> 	LOAD	_t0, (offset + UNIT(0))(src);			\
> 	LOAD	_t1, (offset + UNIT(1))(src);			\
> @@ -280,7 +288,7 @@ LEAF(csum_partial)
> 1:
> 	.set	reorder
> 	/* Add the passed partial csum.  */
> -	ADDC(sum, a2)
> +	ADDC32(sum, a2)
> 	jr	ra
> 	.set	noreorder
> 	END(csum_partial)
> @@ -681,7 +689,7 @@ EXC(	sb	t0, NBYTES-2(dst), .Ls_exc)
> 	.set	pop
> 1:
> 	.set reorder
> -	ADDC(sum, psum)
> +	ADDC32(sum, psum)
> 	jr	ra
> 	.set noreorder
>


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Subject: Re: MIPS checksum bug
Date:	Wed, 17 Sep 2008 21:43:02 -0700
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FWIW... your patch (below) seems to actually fix the checksum problem  
in my testing.  What was your concern about it?

--
-bp


On Sep 17, 2008, at 3:40 AM, Maciej W. Rozycki wrote:

> On Tue, 16 Sep 2008, Bryan Phillippe wrote:
>
>> I've experimented with the following change:
>>
>> --- /home/bp/tmp/csum_partial.S.orig	2008-09-16 12:01:00.000000000  
>> -0700
>> +++ arch/mips/lib/csum_partial.S	2008-09-16 11:51:44.000000000 -0700
>> @@ -281,6 +281,23 @@
>> 	.set	reorder
>> 	/* Add the passed partial csum.  */
>> 	ADDC(sum, a2)
>> +
>> +	/* fold checksum again to clear the high bits before returning */
>> +	.set	push
>> +	.set	noat
>> +#ifdef USE_DOUBLE
>> +	dsll32	v1, sum, 0
>> +	daddu	sum, v1
>> +	sltu	v1, sum, v1
>> +	dsra32	sum, sum, 0
>> +	addu	sum, v1
>> +#endif
>> +	sll	v1, sum, 16
>> +	addu	sum, v1
>> +	sltu	v1, sum, v1
>> +	srl	sum, sum, 16
>> +	addu	sum, v1
>> +
>> 	jr	ra
>> 	.set	noreorder
>> 	END(csum_partial)
>>
>> and it seems to fix the problem for me.  Can you comment?
>
> It seems obvious that a carry from the bit #15 in the last addition of
> the passed checksum -- ADDC(sum, a2) -- will negate the effect of the
> folding.  However a simpler fix should do as well.  Try if the  
> following
> patch works for you.  Please note this is completely untested and  
> further
> optimisation is possible, but I've skipped it in this version for  
> clarity.
>
> Thanks for raising the issue.
>
>  Maciej
>
> Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
> --- a/arch/mips/lib/csum_partial.S	2008-05-05 02:55:23.000000000
> +0000
> +++ b/arch/mips/lib/csum_partial.S	2008-09-17 10:32:37.000000000
> +0000
> @@ -253,6 +253,9 @@ LEAF(csum_partial)
>
> 1:	ADDC(sum, t1)
>
> +	/* Add the passed partial csum.  */
> +	ADDC(sum, a2)
> +
> 	/* fold checksum */
> 	.set	push
> 	.set	noat
> @@ -278,11 +281,8 @@ LEAF(csum_partial)
> 	andi	sum, 0xffff
> 	.set	pop
> 1:
> -	.set	reorder
> -	/* Add the passed partial csum.  */
> -	ADDC(sum, a2)
> 	jr	ra
> -	.set	noreorder
> +	 nop
> 	END(csum_partial)
>
>


From zeisberg@informatik.uni-freiburg.de Thu Sep 18 10:32:47 2008
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From:	Uwe =?iso-8859-1?Q?Kleine-K=F6nig?= 
	<ukleinek@informatik.uni-freiburg.de>
To:	Andrew Morton <akpm@linux-foundation.org>
Cc:	linux-kernel@vger.kernel.org, david-b@pacbell.net,
	ralf@linux-mips.org, linux-mips@linux-mips.org,
	g.liakhovetski@pengutronix.de, greg@kroah.com,
	kay.sievers@vrfy.org, rmk+kernel@arm.linux.org.uk
Subject: Re: [PATCH] gpio_free might sleep, mips architecture
Message-ID: <20080918093242.GA7627@informatik.uni-freiburg.de>
Mail-Followup-To: Uwe =?iso-8859-1?Q?Kleine-K=F6nig?= <ukleinek@informatik.uni-freiburg.de>,
	Andrew Morton <akpm@linux-foundation.org>,
	linux-kernel@vger.kernel.org, david-b@pacbell.net,
	ralf@linux-mips.org, linux-mips@linux-mips.org,
	g.liakhovetski@pengutronix.de, greg@kroah.com, kay.sievers@vrfy.org,
	rmk+kernel@arm.linux.org.uk
References: <1216884515-12084-1-git-send-email-Uwe.Kleine-Koenig@digi.com> <1221508963-27259-1-git-send-email-ukleinek@informatik.uni-freiburg.de> <1221508963-27259-2-git-send-email-ukleinek@informatik.uni-freiburg.de> <1221508963-27259-3-git-send-email-ukleinek@informatik.uni-freiburg.de> <20080917143955.2d3727e5.akpm@linux-foundation.org>
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Hello,

Andrew Morton wrote:
> > diff --git a/include/asm-mips/mach-rc32434/gpio.h b/include/asm-mips/mach-rc32434/gpio.h
> > index f946f5f..9b4722e 100644
> > --- a/include/asm-mips/mach-rc32434/gpio.h
> > +++ b/include/asm-mips/mach-rc32434/gpio.h
> > @@ -13,6 +13,7 @@
> >  #ifndef _RC32434_GPIO_H_
> >  #define _RC32434_GPIO_H_
> >  
> > +#include <linux/kernel.h>
> >  #include <linux/types.h>
> >  
> >  struct rb532_gpio_reg {
> > @@ -88,6 +89,7 @@ static inline int gpio_request(unsigned gpio, const char *label)
> >  static inline void gpio_free(unsigned gpio)
> >  {
> >  	/* Not yet implemented */
> > +	might_sleep();
> >  }
> >  
> 
> There is no gpio_free() in linux-next's include/asm-mips/mach-rc32434/gpio.h
This is OK.  This machine type is converted to GPIO lib in linus-next.
So just drop the two hunks for this file.  (Note, you only dropped the
addition of might_sleep, but then including linux/kernel.h isn't needed
either.)

Best regards and thanks
Uwe

-- 
Uwe Kleine-König

exit vi, lesson II:
: w q ! <CR>

NB: write the current file

From macro@linux-mips.org Thu Sep 18 11:06:29 2008
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From:	"Maciej W. Rozycki" <macro@linux-mips.org>
To:	Bryan Phillippe <u1@terran.org>
cc:	linux-mips@linux-mips.org
Subject: Re: MIPS checksum bug
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On Wed, 17 Sep 2008, Bryan Phillippe wrote:

> FWIW... your patch (below) seems to actually fix the checksum problem  
> in my testing.  What was your concern about it?

 For unaligned buffers the passed checksum is added before the result has
been byte-swapped.  That is probably not seen too often as the network
stack normally aligns IP packets, but it does not make the change correct.  

 One possibility with no performance impact to the common aligned case
would be to byte-swap the passed checksum too, but currently I am somewhat
puzzled about the API of the function; specifically as to whether the
checksums passed to and from it are expected to be folded or not.  The use
of a 32-bit type does not imply it is valid for the upper 16 bits to be
non-zero in the values passed.

  Maciej

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Hi all,
=20
Please find the below testcase..
=20
#include <stdio.h>
#include <limits.h>
#include <errno.h>
#include <unistd.h>
#include <stdlib.h>
#include <string.h>
#include <sys/types.h>
#include <sys/stat.h>
=20
#define EXE_NAME "./exe"
=20
char e2BIG[ARG_MAX+1][10];
char *envList[]=3D{NULL};
=20
int main(void)
{
  int ret,ind;
=20
  for(ind =3D 0; ind < ARG_MAX+1; ind++)
    strcpy(e2BIG[ind], "helloword");
=20
  if ((ret =3D chmod(EXE_NAME,0744)) !=3D 0){
    printf("chmod failed\n");
    exit(1);
  }
=20
  /* whne arg list is too long */
  if ((ret =3D execve(EXE_NAME,e2BIG,envList)) =3D=3D -1) {
    if ( errno =3D=3D E2BIG)
      printf("Test Pass\n");
    else
      printf("Test Fail : Got Errno %d\n", errno);
    exit(0);
  }
  else
    printf("execve worked out of limit\n");
  exit(1);
}
=20
On MIPS E2BIG is not getting set as errno instead EFAULT is set, while
on=20
other archs like ARM, PowerPC and i686 I am able to get E2BIG.
=20
Please let me know about the issue...
=20
Let EXE_NAME be any executable....
=20
Thanks,
Halesh

=20



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<div class=3DSection1><pre><font size=3D2 color=3Dblack face=3D"Courier =
New"><span
style=3D'font-size:10.0pt'>Hi =
all,<o:p></o:p></span></font></pre><pre><font
size=3D2 color=3Dblack face=3D"Courier New"><span =
style=3D'font-size:10.0pt'><o:p>&nbsp;</o:p></span></font></pre><pre><fon=
t
size=3D2 color=3Dblack face=3D"Courier New"><span =
style=3D'font-size:10.0pt'>Please find the below =
testcase..<o:p></o:p></span></font></pre><pre><font
size=3D2 color=3Dblack face=3D"Courier New"><span =
style=3D'font-size:10.0pt'><o:p>&nbsp;</o:p></span></font></pre><pre><fon=
t
size=3D2 color=3Dblack face=3D"Courier New"><span =
style=3D'font-size:10.0pt'>#include =
&lt;stdio.h&gt;<o:p></o:p></span></font></pre><pre><font
size=3D2 color=3Dblack face=3D"Courier New"><span =
style=3D'font-size:10.0pt'>#include =
&lt;limits.h&gt;<o:p></o:p></span></font></pre><pre><font
size=3D2 color=3Dblack face=3D"Courier New"><span =
style=3D'font-size:10.0pt'>#include =
&lt;errno.h&gt;<o:p></o:p></span></font></pre><pre><font
size=3D2 color=3Dblack face=3D"Courier New"><span =
style=3D'font-size:10.0pt'>#include =
&lt;unistd.h&gt;<o:p></o:p></span></font></pre><pre><font
size=3D2 color=3Dblack face=3D"Courier New"><span =
style=3D'font-size:10.0pt'>#include =
&lt;stdlib.h&gt;<o:p></o:p></span></font></pre><pre><font
size=3D2 color=3Dblack face=3D"Courier New"><span =
style=3D'font-size:10.0pt'>#include =
&lt;string.h&gt;<o:p></o:p></span></font></pre><pre><font
size=3D2 color=3Dblack face=3D"Courier New"><span =
style=3D'font-size:10.0pt'>#include =
&lt;sys/types.h&gt;<o:p></o:p></span></font></pre><pre><font
size=3D2 color=3Dblack face=3D"Courier New"><span =
style=3D'font-size:10.0pt'>#include =
&lt;sys/stat.h&gt;<o:p></o:p></span></font></pre><pre><font
size=3D2 color=3Dblack face=3D"Courier New"><span =
style=3D'font-size:10.0pt'><o:p>&nbsp;</o:p></span></font></pre><pre><fon=
t
size=3D2 color=3Dblack face=3D"Courier New"><span =
style=3D'font-size:10.0pt'>#define EXE_NAME =
&quot;./exe&quot;<o:p></o:p></span></font></pre><pre><font
size=3D2 color=3Dblack face=3D"Courier New"><span =
style=3D'font-size:10.0pt'><o:p>&nbsp;</o:p></span></font></pre><pre><fon=
t
size=3D2 color=3Dblack face=3D"Courier New"><span =
style=3D'font-size:10.0pt'>char =
e2BIG[ARG_MAX+1][10];<o:p></o:p></span></font></pre><pre><font
size=3D2 color=3Dblack face=3D"Courier New"><span =
style=3D'font-size:10.0pt'>char =
*envList[]=3D{NULL};<o:p></o:p></span></font></pre><pre><font
size=3D2 color=3Dblack face=3D"Courier New"><span =
style=3D'font-size:10.0pt'><o:p>&nbsp;</o:p></span></font></pre><pre><fon=
t
size=3D2 color=3Dblack face=3D"Courier New"><span =
style=3D'font-size:10.0pt'>int =
main(void)<o:p></o:p></span></font></pre><pre><font
size=3D2 color=3Dblack face=3D"Courier New"><span =
style=3D'font-size:10.0pt'>{<o:p></o:p></span></font></pre><pre><font
size=3D2 color=3Dblack face=3D"Courier New"><span =
style=3D'font-size:10.0pt'>&nbsp; int ret,<st1:State
w:st=3D"on"><st1:place =
w:st=3D"on">ind</st1:place></st1:State>;<o:p></o:p></span></font></pre><p=
re><font
size=3D2 color=3Dblack face=3D"Courier New"><span =
style=3D'font-size:10.0pt'><o:p>&nbsp;</o:p></span></font></pre><pre><fon=
t
size=3D2 color=3Dblack face=3D"Courier New"><span =
style=3D'font-size:10.0pt'>&nbsp; for(<st1:State
w:st=3D"on">ind</st1:State> =3D 0; <st1:State =
w:st=3D"on">ind</st1:State> &lt; ARG_MAX+1; <st1:State
w:st=3D"on"><st1:place =
w:st=3D"on">ind++</st1:place></st1:State>)<o:p></o:p></span></font></pre>=
<pre><font
size=3D2 color=3Dblack face=3D"Courier New"><span =
style=3D'font-size:10.0pt'>&nbsp;&nbsp;&nbsp; strcpy(e2BIG[<st1:State
w:st=3D"on"><st1:place w:st=3D"on">ind</st1:place></st1:State>], =
&quot;helloword&quot;);<o:p></o:p></span></font></pre><pre><font
size=3D2 color=3Dblack face=3D"Courier New"><span =
style=3D'font-size:10.0pt'><o:p>&nbsp;</o:p></span></font></pre><pre><fon=
t
size=3D2 color=3Dblack face=3D"Courier New"><span =
style=3D'font-size:10.0pt'>&nbsp; if ((ret =3D chmod(EXE_NAME,0744)) =
!=3D 0){<o:p></o:p></span></font></pre><pre><font
size=3D2 color=3Dblack face=3D"Courier New"><span =
style=3D'font-size:10.0pt'>&nbsp;&nbsp;&nbsp; printf(&quot;chmod =
failed\n&quot;);<o:p></o:p></span></font></pre><pre><font
size=3D2 color=3Dblack face=3D"Courier New"><span =
style=3D'font-size:10.0pt'>&nbsp;&nbsp;&nbsp; =
exit(1);<o:p></o:p></span></font></pre><pre><font
size=3D2 color=3Dblack face=3D"Courier New"><span =
style=3D'font-size:10.0pt'>&nbsp; =
}<o:p></o:p></span></font></pre><pre><font
size=3D2 color=3Dblack face=3D"Courier New"><span =
style=3D'font-size:10.0pt'><o:p>&nbsp;</o:p></span></font></pre><pre><fon=
t
size=3D2 color=3Dblack face=3D"Courier New"><span =
style=3D'font-size:10.0pt'>&nbsp; /* whne arg list is too long =
*/<o:p></o:p></span></font></pre><pre><font
size=3D2 color=3Dblack face=3D"Courier New"><span =
style=3D'font-size:10.0pt'>&nbsp; if ((ret =3D =
execve(EXE_NAME,e2BIG,envList)) =3D=3D -1) =
{<o:p></o:p></span></font></pre><pre><font
size=3D2 color=3Dblack face=3D"Courier New"><span =
style=3D'font-size:10.0pt'>&nbsp;&nbsp;&nbsp; if ( errno =3D=3D =
E2BIG)<o:p></o:p></span></font></pre><pre><font
size=3D2 color=3Dblack face=3D"Courier New"><span =
style=3D'font-size:10.0pt'>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
printf(&quot;Test =
Pass\n&quot;);<o:p></o:p></span></font></pre><pre><font
size=3D2 color=3Dblack face=3D"Courier New"><span =
style=3D'font-size:10.0pt'>&nbsp;&nbsp;&nbsp; =
else<o:p></o:p></span></font></pre><pre><font
size=3D2 color=3Dblack face=3D"Courier New"><span =
style=3D'font-size:10.0pt'>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; =
printf(&quot;Test Fail : Got Errno %d\n&quot;, =
errno);<o:p></o:p></span></font></pre><pre><font
size=3D2 color=3Dblack face=3D"Courier New"><span =
style=3D'font-size:10.0pt'>&nbsp;&nbsp;&nbsp; =
exit(0);<o:p></o:p></span></font></pre><pre><font
size=3D2 color=3Dblack face=3D"Courier New"><span =
style=3D'font-size:10.0pt'>&nbsp; =
}<o:p></o:p></span></font></pre><pre><font
size=3D2 color=3Dblack face=3D"Courier New"><span =
style=3D'font-size:10.0pt'>&nbsp; =
else<o:p></o:p></span></font></pre><pre><font
size=3D2 color=3Dblack face=3D"Courier New"><span =
style=3D'font-size:10.0pt'>&nbsp;&nbsp;&nbsp; printf(&quot;execve worked =
out of limit\n&quot;);<o:p></o:p></span></font></pre><pre><font
size=3D2 color=3Dblack face=3D"Courier New"><span =
style=3D'font-size:10.0pt'>&nbsp; =
exit(1);<o:p></o:p></span></font></pre><pre><font
size=3D2 color=3Dblack face=3D"Courier New"><span =
style=3D'font-size:10.0pt'>}<o:p></o:p></span></font></pre><pre><font
size=3D2 color=3Dblack face=3D"Courier New"><span =
style=3D'font-size:10.0pt'><o:p>&nbsp;</o:p></span></font></pre><pre><fon=
t
size=3D2 color=3Dblack face=3D"Courier New"><span =
style=3D'font-size:10.0pt'>On MIPS E2BIG is not getting set as errno =
instead EFAULT is set, while on =
<o:p></o:p></span></font></pre><pre><font
size=3D2 color=3Dblack face=3D"Courier New"><span =
style=3D'font-size:10.0pt'>other archs like ARM, PowerPC and i686 I am =
able to get E2BIG.<o:p></o:p></span></font></pre><pre><font
size=3D2 color=3Dblack face=3D"Courier New"><span =
style=3D'font-size:10.0pt'><o:p>&nbsp;</o:p></span></font></pre><pre><fon=
t
size=3D2 color=3Dblack face=3D"Courier New"><span =
style=3D'font-size:10.0pt'>Please let me know about the =
issue...<o:p></o:p></span></font></pre><pre><font
size=3D2 color=3Dblack face=3D"Courier New"><span =
style=3D'font-size:10.0pt'><o:p>&nbsp;</o:p></span></font></pre><pre><fon=
t
size=3D2 color=3Dblack face=3D"Courier New"><span =
style=3D'font-size:10.0pt'>Let EXE_NAME be any =
executable....<o:p></o:p></span></font></pre><pre><font
size=3D2 color=3Dblack face=3D"Courier New"><span =
style=3D'font-size:10.0pt'><o:p>&nbsp;</o:p></span></font></pre><pre><fon=
t
size=3D2 color=3Dblack face=3D"Courier New"><span =
style=3D'font-size:10.0pt'>Thanks,<o:p></o:p></span></font></pre><pre><fo=
nt
size=3D2 color=3Dblack face=3D"Courier New"><span =
style=3D'font-size:10.0pt'>Halesh<o:p></o:p></span></font></pre>

<p class=3DMsoNormal><font size=3D2 face=3DArial><span =
style=3D'font-size:10.0pt;
font-family:Arial'><o:p>&nbsp;</o:p></span></font></p>

</div>

<p></p><hr><br>This email is confidential and intended only for the use =
of the individual or entity named above and may contain information that =
is privileged. If you are not the intended recipient, you are notified =
that any dissemination, distribution or copying of this email is =
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From ralf@linux-mips.org Thu Sep 18 15:00:06 2008
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From:	Ralf Baechle <ralf@linux-mips.org>
To:	Uwe =?iso-8859-1?Q?Kleine-K=F6nig?= 
	<ukleinek@informatik.uni-freiburg.de>,
	Andrew Morton <akpm@linux-foundation.org>,
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Subject: Re: [PATCH] gpio_free might sleep, mips architecture
Message-ID: <20080918135950.GA8104@linux-mips.org>
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On Thu, Sep 18, 2008 at 11:32:42AM +0200, Uwe Kleine-König wrote:

> Andrew Morton wrote:
> > > diff --git a/include/asm-mips/mach-rc32434/gpio.h b/include/asm-mips/mach-rc32434/gpio.h
> > > index f946f5f..9b4722e 100644
> > > --- a/include/asm-mips/mach-rc32434/gpio.h
> > > +++ b/include/asm-mips/mach-rc32434/gpio.h
> > > @@ -13,6 +13,7 @@
> > >  #ifndef _RC32434_GPIO_H_
> > >  #define _RC32434_GPIO_H_
> > >  
> > > +#include <linux/kernel.h>
> > >  #include <linux/types.h>
> > >  
> > >  struct rb532_gpio_reg {
> > > @@ -88,6 +89,7 @@ static inline int gpio_request(unsigned gpio, const char *label)
> > >  static inline void gpio_free(unsigned gpio)
> > >  {
> > >  	/* Not yet implemented */
> > > +	might_sleep();
> > >  }
> > >  
> > 
> > There is no gpio_free() in linux-next's include/asm-mips/mach-rc32434/gpio.h
> This is OK.  This machine type is converted to GPIO lib in linus-next.
> So just drop the two hunks for this file.  (Note, you only dropped the
> addition of might_sleep, but then including linux/kernel.h isn't needed
> either.)

A few days ago I've put a patch to move include/asm-mips/ to arch/ like
several other architectures already did so you patch may conflict ...

  Ralf

From anemo@mba.ocn.ne.jp Thu Sep 18 17:10:30 2008
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Subject: Re: [PATCH 1/2] ide: Add tx4939ide driver (v2)
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On Wed, 17 Sep 2008 17:58:45 -0400, Jeff Garzik <jeff@garzik.org> wrote:
> > This is the driver for the Toshiba TX4939 SoC ATA controller.
> 
> I hope a libata driver is coming, too?

Yes, but it is just a plan.  No code for now.

---
Atsushi Nemoto

From anemo@mba.ocn.ne.jp Thu Sep 18 17:16:52 2008
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Subject: Re: MIPS checksum bug
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On Wed, 17 Sep 2008 15:52:45 -0700, Bryan Phillippe <u1@terran.org> wrote:
> I tested the simplified patch below (ADDC32), and it does not address  
> the checksum bug.  I suspect the problem is that we're still leaving  
> the carry bit in the upper 16 bits of the 32 bit csum returned, and  
> this is resulting in a computed checksum that is 1 greater than it  
> should be.  The upper 16 bits of the return value of this function  
> must be 0, right?

Thank you for testing.  Though this patch did not fixed your problem,
I still have a doubt on 64-bit optimization.

If your hardware could run 32-bit kernel, could you confirm the
problem can happens in 32-bit too or not?

---
Atsushi Nemoto

From ralf@linux-mips.org Thu Sep 18 22:17:19 2008
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From:	Ralf Baechle <ralf@linux-mips.org>
To:	"Sadashiiv, Halesh" <halesh.sadashiv@ap.sony.com>
Cc:	linux-mips@linux-mips.org
Subject: Re: execve errno setting on MIPS
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On Thu, Sep 18, 2008 at 05:09:35PM +0530, Sadashiiv, Halesh wrote:
> From: "Sadashiiv, Halesh" <halesh.sadashiv@ap.sony.com>
> Date: Thu, 18 Sep 2008 17:09:35 +0530
> To: linux-mips@linux-mips.org
> Subject: execve errno setting on MIPS
> Content-Type: multipart/alternative;
> 	boundary="----_=_NextPart_001_01C91983.39F24AAB"
> 
> Hi all,
>  
> Please find the below testcase..
>  
> #include <stdio.h>
> #include <limits.h>
> #include <errno.h>
> #include <unistd.h>
> #include <stdlib.h>
> #include <string.h>
> #include <sys/types.h>
> #include <sys/stat.h>
>  
> #define EXE_NAME "./exe"
>  
> char e2BIG[ARG_MAX+1][10];
> char *envList[]={NULL};
>  
> int main(void)
> {
>   int ret,ind;
>  
>   for(ind = 0; ind < ARG_MAX+1; ind++)
>     strcpy(e2BIG[ind], "helloword");
>  
>   if ((ret = chmod(EXE_NAME,0744)) != 0){
>     printf("chmod failed\n");
>     exit(1);
>   }
>  
>   /* whne arg list is too long */
>   if ((ret = execve(EXE_NAME,e2BIG,envList)) == -1) {
>     if ( errno == E2BIG)
>       printf("Test Pass\n");
>     else
>       printf("Test Fail : Got Errno %d\n", errno);
>     exit(0);
>   }
>   else
>     printf("execve worked out of limit\n");
>   exit(1);
> }
>  
> On MIPS E2BIG is not getting set as errno instead EFAULT is set, while
> on 
> other archs like ARM, PowerPC and i686 I am able to get E2BIG.
>  
> Please let me know about the issue...
>  
> Let EXE_NAME be any executable....

Let there be light:

  char *foo[] != char foo[][]

char *e2BIG[ARG_MAX + 1] = {
        [0 ... ARG_MAX] = "helloword"
};

        for (ind = 0; ind < ARG_MAX + 1; ind++)
                strcpy(e2BIG[ind], "helloword");

is different from

char *e2BIG[ARG_MAX + 1] = {
        [0 ... ARG_MAX] = "helloword"
};

The one is two dimensional array, the other an array of pointers to char.

  Ralf

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To:	"Sadashiiv, Halesh" <halesh.sadashiv@ap.sony.com>
Cc:	linux-mips@linux-mips.org
Subject: Re: execve errno setting on MIPS
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On Thu, Sep 18, 2008 at 05:09:35PM +0530, Sadashiiv, Halesh wrote:
> char e2BIG[ARG_MAX+1][10];
> char *envList[]={NULL};
>  
> int main(void)
> {
>   int ret,ind;
>  
>   for(ind = 0; ind < ARG_MAX+1; ind++)
>     strcpy(e2BIG[ind], "helloword");

this is broken and does cause an EFAULT on x86 as well (you should
take the warning from gcc about the second argument of execve serious).

Try:

char *e2BIG[ARG_MAX+1];
char *envList[]={NULL};

int main(void)
{
  int ret,ind;

    for(ind = 0; ind < ARG_MAX+1; ind++)
    	e2BIG[ind] = strdup("helloword");


And it looks like the ARG_MAX limit is bigger than my installed glibc
thinks, because it works at least on x86. When I increase the array two
2 * ARG_MAX I'll get the wanted E2BIG.

Thomas.

-- 
Crap can work. Given enough thrust pigs will fly, but it's not necessary a
good idea.                                                [ RFC1925, 2.3 ]

From ralf@linux-mips.org Thu Sep 18 23:07:39 2008
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From:	Ralf Baechle <ralf@linux-mips.org>
To:	"Maciej W. Rozycki" <macro@linux-mips.org>
Cc:	Atsushi Nemoto <anemo@mba.ocn.ne.jp>, u1@terran.org,
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Subject: Re: MIPS checksum bug
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On Wed, Sep 17, 2008 at 07:21:23PM +0100, Maciej W. Rozycki wrote:

> > >  Hmm, what's the purpose of doing the fold in csum_partial() then?
> > 
> > Well, maybe odd-byte handling requires 16-bit holded values?
> 
>  It should be enough to swap odd and even bytes in the word in the
> unaligned path.  Though perhaps extra code to do masking would make it no
> shorter/faster than what we have now; however the aligned path would
> benefit.  Hmm...

Which is a truely weird operation - but MIPS R2 happens to have a wonderful
instruction for this operation, WSBH / DSBH.

  Ralf

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From:	Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
To:	Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Subject: Re: [PATCH 1/2] ide: Add tx4939ide driver (v2)
Date:	Thu, 18 Sep 2008 16:45:09 -0700
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On Wednesday 17 September 2008 08:13:42 Atsushi Nemoto wrote:
> This is the driver for the Toshiba TX4939 SoC ATA controller.
> 
> This controller has standard ATA taskfile registers and DMA
> command/status registers, but the register layout is swapped on big
> endian.  There are some other endian issue and some special registers
> which requires many custom dma_ops/port_ops routines.
> 
> Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
> ---
> This patch is against linux-next 20080916.
> 
> Changes since v1:
> * rework IO accessors
> * rework pio/dma timing setup
> * use ide_get_pair_dev
> * do not do ATA hard reset
> * and so on  (Many thanks to Sergei)

Sergei, are you OK with this version?

[ I tentatively applied it to pata tree.  I still see the use of legacy
  HWIF()/HWGROUP() macros but I can deal with it myself before pushing
  the patch upstream. ]

From ralf@linux-mips.org Fri Sep 19 02:14:49 2008
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Subject: Re: MIPS checksum bug
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On Fri, Sep 19, 2008 at 01:17:04AM +0900, Atsushi Nemoto wrote:

It seems __csum_partial_copy_user and csum_partial_copy_nocheck were
affected by the same bug.  Below a patch which tries to fix the issue.
I've tested it on 64-bit only.  I seem to observe that TCP transfers
on my test machine are ramping up to full bandwith somewhat more
slowly than on another machine but there are all sorts of reasons which
make that an unscientific test.  Anyway, I'd appreciate if people could
test this on 32-bit and 64-bit machines asap.

  Ralf

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

diff --git a/arch/mips/lib/csum_partial.S b/arch/mips/lib/csum_partial.S
index 8d77841..9143a42 100644
--- a/arch/mips/lib/csum_partial.S
+++ b/arch/mips/lib/csum_partial.S
@@ -53,12 +53,14 @@
 #define UNIT(unit)  ((unit)*NBYTES)
 
 #define ADDC(sum,reg)						\
-	.set	push;						\
-	.set	noat;						\
 	ADD	sum, reg;					\
 	sltu	v1, sum, reg;					\
 	ADD	sum, v1;					\
-	.set	pop
+
+#define ADDC32(sum,reg)						\
+	addu	sum, reg;					\
+	sltu	v1, sum, reg;					\
+	addu	sum, v1;					\
 
 #define CSUM_BIGCHUNK1(src, offset, sum, _t0, _t1, _t2, _t3)	\
 	LOAD	_t0, (offset + UNIT(0))(src);			\
@@ -263,24 +265,25 @@ LEAF(csum_partial)
 	dsra32	sum, sum, 0
 	addu	sum, v1
 #endif
-	sll	v1, sum, 16
-	addu	sum, v1
-	sltu	v1, sum, v1
-	srl	sum, sum, 16
-	addu	sum, v1
 
 	/* odd buffer alignment? */
 	beqz	t7, 1f
 	 nop
-	sll	v1, sum, 8
+#ifdef CPU_MIPSR2
+	wsbh	sum, sum	
+#else
+	li	v1, 0xff00ff
+	and	t0, sum, v1
+	sll	t0, t0, 8
 	srl	sum, sum, 8
-	or	sum, v1
-	andi	sum, 0xffff
+	and	sum, sum, v1
+	or	sum, sum, t0
+#endif
 	.set	pop
 1:
 	.set	reorder
 	/* Add the passed partial csum.  */
-	ADDC(sum, a2)
+	ADDC32(sum, a2)
 	jr	ra
 	.set	noreorder
 	END(csum_partial)
@@ -665,23 +668,24 @@ EXC(	sb	t0, NBYTES-2(dst), .Ls_exc)
 	dsra32	sum, sum, 0
 	addu	sum, v1
 #endif
-	sll	v1, sum, 16
-	addu	sum, v1
-	sltu	v1, sum, v1
-	srl	sum, sum, 16
-	addu	sum, v1
 
 	/* odd buffer alignment? */
 	beqz	odd, 1f
 	 nop
-	sll	v1, sum, 8
+#ifdef CPU_MIPSR2
+	wsbh	sum, sum
+#else
+	li	v1, 0xff00ff
+	and	t0, sum, v1
+	sll	t0, t0, 8
 	srl	sum, sum, 8
-	or	sum, v1
-	andi	sum, 0xffff
+	and	sum, sum, v1
+	or	sum, sum, t0
+#endif
 	.set	pop
 1:
 	.set reorder
-	ADDC(sum, psum)
+	ADDC32(sum, psum)
 	jr	ra
 	.set noreorder
 

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>this is broken and does cause an EFAULT on x86 as well (you should
>take the warning from gcc about the second argument of execve serious).
=20
 Thanks, you are right.
=20
>Try:
=20
>char *e2BIG[ARG_MAX+1];
>char *envList[]=3D{NULL};
>=20
>int main(void)
>{
>  int ret,ind;
>=20
>   for(ind =3D 0; ind < ARG_MAX+1; ind++)
>        e2BIG[ind] =3D strdup("helloword");
>=20
>=20
 It wroks on X86 and other Archs.
>=20
>=20
>And it looks like the ARG_MAX limit is bigger than my installed glibc
>thinks, because it works at least on x86. When I increase the array two
>2 * ARG_MAX I'll get the wanted E2BIG.
=20
 Yes, on MIPS we need to increase the ARM_MAX to 2*ARG_MAX to get E2BIG.
=20
Thanks,
Halesh

=20



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<div class=3DSection1><pre><font size=3D2 color=3Dblack face=3D"Courier =
New"><span
style=3D'font-size:10.0pt;color:black'>&gt;this is broken and does cause =
an EFAULT on x86 as well (you =
should<o:p></o:p></span></font></pre><pre><font
size=3D2 color=3Dblack face=3D"Courier New"><span =
style=3D'font-size:10.0pt;color:black'>&gt;take the warning from gcc =
about the second argument of execve =
serious).<o:p></o:p></span></font></pre><pre><font
size=3D2 color=3Dblack face=3D"Courier New"><span =
style=3D'font-size:10.0pt;color:black'><o:p>&nbsp;</o:p></span></font></p=
re><pre><font
size=3D2 color=3Dblack face=3D"Courier New"><span =
style=3D'font-size:10.0pt;color:black'> Thanks, you are =
right.<o:p></o:p></span></font></pre><pre><font
size=3D2 color=3Dblack face=3D"Courier New"><span =
style=3D'font-size:10.0pt;color:black'><o:p>&nbsp;</o:p></span></font></p=
re><pre><font
size=3D2 color=3Dblack face=3D"Courier New"><span =
style=3D'font-size:10.0pt;color:black'>&gt;Try:<o:p></o:p></span></font><=
/pre><pre><font
size=3D2 color=3Dblack face=3D"Courier New"><span =
style=3D'font-size:10.0pt;color:black'><o:p>&nbsp;</o:p></span></font></p=
re><pre><font
size=3D2 color=3Dblack face=3D"Courier New"><span =
style=3D'font-size:10.0pt;color:black'>&gt;char =
*e2BIG[ARG_MAX+1];<o:p></o:p></span></font></pre><pre><font
size=3D2 color=3Dblack face=3D"Courier New"><span =
style=3D'font-size:10.0pt;color:black'>&gt;char =
*envList[]=3D{NULL};<o:p></o:p></span></font></pre><pre><font
size=3D2 color=3Dblack face=3D"Courier New"><span =
style=3D'font-size:10.0pt;color:black'>&gt;<o:p>&nbsp;</o:p></span></font=
></pre><pre><font
size=3D2 color=3Dblack face=3D"Courier New"><span =
style=3D'font-size:10.0pt;color:black'>&gt;int =
main(void)<o:p></o:p></span></font></pre><pre><font
size=3D2 color=3Dblack face=3D"Courier New"><span =
style=3D'font-size:10.0pt;color:black'>&gt;{<o:p></o:p></span></font></pr=
e><pre><font
size=3D2 color=3Dblack face=3D"Courier New"><span =
style=3D'font-size:10.0pt;color:black'>&gt;&nbsp; int ret,<st1:State
w:st=3D"on"><st1:place =
w:st=3D"on">ind</st1:place></st1:State>;<o:p></o:p></span></font></pre><p=
re><font
size=3D2 color=3Dblack face=3D"Courier New"><span =
style=3D'font-size:10.0pt;color:black'>&gt;<o:p>&nbsp;</o:p></span></font=
></pre><pre><font
size=3D2 color=3Dblack face=3D"Courier New"><span =
style=3D'font-size:10.0pt;color:black'>&gt;&nbsp;&nbsp; for(<st1:State
w:st=3D"on">ind</st1:State> =3D 0; <st1:State =
w:st=3D"on">ind</st1:State> &lt; ARG_MAX+1; <st1:State
w:st=3D"on"><st1:place =
w:st=3D"on">ind++</st1:place></st1:State>)<o:p></o:p></span></font></pre>=
<pre><font
size=3D2 color=3Dblack face=3D"Courier New"><span =
style=3D'font-size:10.0pt;color:black'>&gt;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;=
&nbsp;&nbsp; e2BIG[<st1:State
w:st=3D"on"><st1:place w:st=3D"on">ind</st1:place></st1:State>] =3D =
strdup(&quot;helloword&quot;);<o:p></o:p></span></font></pre><pre><font
size=3D2 color=3Dblack face=3D"Courier New"><span =
style=3D'font-size:10.0pt;color:black'>&gt;<o:p>&nbsp;</o:p></span></font=
></pre><pre><font
size=3D2 color=3Dblack face=3D"Courier New"><span =
style=3D'font-size:10.0pt;color:black'>&gt;<o:p>&nbsp;</o:p></span></font=
></pre><pre><font
size=3D2 color=3Dblack face=3D"Courier New"><span =
style=3D'font-size:10.0pt;color:black'> It wroks on X86 and other =
Archs.<o:p></o:p></span></font></pre><pre><font
size=3D2 color=3Dblack face=3D"Courier New"><span =
style=3D'font-size:10.0pt;color:black'>&gt;<o:p>&nbsp;</o:p></span></font=
></pre><pre><font
size=3D2 color=3Dblack face=3D"Courier New"><span =
style=3D'font-size:10.0pt;color:black'>&gt;<o:p>&nbsp;</o:p></span></font=
></pre><pre><font
size=3D2 color=3Dblack face=3D"Courier New"><span =
style=3D'font-size:10.0pt;color:black'>&gt;And it looks like the ARG_MAX =
limit is bigger than my installed =
glibc<o:p></o:p></span></font></pre><pre><font
size=3D2 color=3Dblack face=3D"Courier New"><span =
style=3D'font-size:10.0pt;color:black'>&gt;thinks, because it works at =
least on x86. When I increase the array =
two<o:p></o:p></span></font></pre><pre><font
size=3D2 color=3Dblack face=3D"Courier New"><span =
style=3D'font-size:10.0pt;color:black'>&gt;2 * ARG_MAX I'll get the =
wanted E2BIG.<o:p></o:p></span></font></pre><pre><font
size=3D2 color=3Dblack face=3D"Courier New"><span =
style=3D'font-size:10.0pt;color:black'><o:p>&nbsp;</o:p></span></font></p=
re><pre><font
size=3D2 color=3Dblack face=3D"Courier New"><span =
style=3D'font-size:10.0pt;color:black'> Yes, on MIPS we need to increase =
the ARM_MAX to 2*ARG_MAX to get =
E2BIG.<o:p></o:p></span></font></pre><pre><font
size=3D2 color=3Dblack face=3D"Courier New"><span =
style=3D'font-size:10.0pt;color:black'><o:p>&nbsp;</o:p></span></font></p=
re><pre><font
size=3D2 color=3Dblack face=3D"Courier New"><span =
style=3D'font-size:10.0pt;color:black'>Thanks,<o:p></o:p></span></font></=
pre><pre><font
size=3D2 color=3Dblack face=3D"Courier New"><span =
style=3D'font-size:10.0pt;color:black'>Halesh<o:p></o:p></span></font></p=
re>

<p class=3DMsoNormal><font size=3D2 face=3DArial><span =
style=3D'font-size:10.0pt;
font-family:Arial'><o:p>&nbsp;</o:p></span></font></p>

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=20
=20
>> The one is two dimensional array, the other an array of pointers to
char.
=20
Yes, Fixed the problem,=20
But on MIPS, ARG_MAX is not considered, I was able to get the E2BIG on
2*ARG_MAX.
=20
Check
http://www.linux-mips.org/archives/linux-mips/2008-09/msg00136.html =20
=20

Thanks,

Halesh



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<div class=3DSection1><pre><font size=3D2 color=3Dblack face=3D"Courier =
New"><span
style=3D'font-size:10.0pt;color:black'><o:p>&nbsp;</o:p></span></font></p=
re><pre><font
size=3D2 color=3Dblack face=3D"Courier New"><span =
style=3D'font-size:10.0pt;color:black'><o:p>&nbsp;</o:p></span></font></p=
re><pre><font
size=3D2 color=3Dblack face=3D"Courier New"><span =
style=3D'font-size:10.0pt;color:black'>&gt;&gt; The one is two =
dimensional array, the other an array of pointers to =
char.<o:p></o:p></span></font></pre><pre><font
size=3D2 color=3Dblack face=3D"Courier New"><span =
style=3D'font-size:10.0pt;color:black'><o:p>&nbsp;</o:p></span></font></p=
re><pre><font
size=3D2 color=3Dblack face=3D"Courier New"><span =
style=3D'font-size:10.0pt;color:black'>Yes, Fixed the problem, =
<o:p></o:p></span></font></pre><pre><font
size=3D2 color=3Dblack face=3D"Courier New"><span =
style=3D'font-size:10.0pt;color:black'>But on MIPS, ARG_MAX is not =
considered, I was able to get the E2BIG on =
2*ARG_MAX.<o:p></o:p></span></font></pre><pre><font
size=3D2 color=3Dblack face=3D"Courier New"><span =
style=3D'font-size:10.0pt;color:black'><o:p>&nbsp;</o:p></span></font></p=
re><pre><font
size=3D2 color=3Dblack face=3D"Courier New"><span =
style=3D'font-size:10.0pt;color:black'>Check<o:p></o:p></span></font></pr=
e><pre><font
size=3D2 color=3Dblack face=3D"Courier New"><span =
style=3D'font-size:10.0pt;color:black'><a
href=3D"http://www.linux-mips.org/archives/linux-mips/2008-09/msg00136.ht=
ml">http://www.linux-mips.org/archives/linux-mips/2008-09/msg00136.html</=
a>&nbsp; <o:p></o:p></span></font></pre><pre><font
size=3D2 color=3Dblack face=3D"Courier New"><span =
style=3D'font-size:10.0pt;color:black'><o:p>&nbsp;</o:p></span></font></p=
re>

<p class=3DMsoNormal><font size=3D2 face=3DArial><span =
style=3D'font-size:10.0pt;
font-family:Arial'>Thanks,<o:p></o:p></span></font></p>

<p class=3DMsoNormal><font size=3D2 face=3DArial><span =
style=3D'font-size:10.0pt;
font-family:Arial'>Halesh<o:p></o:p></span></font></p>

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From dtemirbulatov@gmail.com Fri Sep 19 07:31:37 2008
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Date:	Fri, 19 Sep 2008 10:31:29 +0400
From:	"Dinar Temirbulatov" <dtemirbulatov@gmail.com>
To:	linux-mips@linux-mips.org
Subject: mmap is broken for MIPS64 n32 and o32 abis
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Hi,
I noticed that mmap is not working properly under n32, o32 abis in
MIPS64, for example if we want to map 0xb6000000 address to the
userland under those abis we call  mmap and because the last argument
in old_mmap is off_t and this type is 64-bits wide for MIPS64, we end
up having for example 0xffffffffb6000000 address value. I am sure that
this is not a glibc issue. Following patch adds 32-bit version of mmap
and also it adds mmap64 support for n32 abi since mmap64 was
implemented correctly for n32 too.
                                          thanks, Dinar.

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From tsbogend@alpha.franken.de Fri Sep 19 08:49:17 2008
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To:	"Sadashiiv, Halesh" <halesh.sadashiv@ap.sony.com>
Cc:	linux-mips@linux-mips.org
Subject: Re: execve errno setting on MIPS
Message-ID: <20080919074851.GA26907@alpha.franken.de>
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From:	tsbogend@alpha.franken.de (Thomas Bogendoerfer)
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On Fri, Sep 19, 2008 at 08:57:17AM +0530, Sadashiiv, Halesh wrote:
> >And it looks like the ARG_MAX limit is bigger than my installed glibc
> >thinks, because it works at least on x86. When I increase the array two
> >2 * ARG_MAX I'll get the wanted E2BIG.
>  
>  Yes, on MIPS we need to increase the ARM_MAX to 2*ARG_MAX to get E2BIG.

I've tested only on x86 and I also needed to use 2 * ARG_MAX. This all
depends on the installed glibc, which provides ARG_MAX and the installed
kernel, which sets the rules independand from glibc. If you look at
fs/exec.c in the kernel source, you see these rules. Current kernels
for example have a limit of 

#define MAX_ARG_STRINGS 0x7FFFFFFF

for the number of strings. Looks like E2BIG is triggered by the space
needed for the strings (I only had a quick look at exec.c).

Thomas.

-- 
Crap can work. Given enough thrust pigs will fly, but it's not necessary a
good idea.                                                [ RFC1925, 2.3 ]

From U.Klatt@miwe.de Fri Sep 19 08:58:37 2008
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Hello,

I have a custom hardware (AU1100) with kernel 2.4 and an working binary using floats (compiled with gcc 3.3.5).
Now I am testing with kernel 2.6.

When I use the old binary, float math isn't working anymore.
I have to recompile the source with new gcc 4.1.2 but then the new binary is working only on kernel 2.6.

Can somebody give me some hints, how to chage settings for kernel 2.6 creation or compiler settings to generate an universal binary.

Thanks
Uwe

From sshtylyov@ru.mvista.com Fri Sep 19 10:26:08 2008
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To:	Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
Cc:	Atsushi Nemoto <anemo@mba.ocn.ne.jp>, linux-mips@linux-mips.org,
	linux-ide@vger.kernel.org, ralf@linux-mips.org
Subject: Re: [PATCH 1/2] ide: Add tx4939ide driver (v2)
References: <20080918.001342.52129176.anemo@mba.ocn.ne.jp> <200809181645.10410.bzolnier@gmail.com>
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Hello.

Bartlomiej Zolnierkiewicz wrote:

>> This is the driver for the Toshiba TX4939 SoC ATA controller.
>>
>> This controller has standard ATA taskfile registers and DMA
>> command/status registers, but the register layout is swapped on big
>> endian.  There are some other endian issue and some special registers
>> which requires many custom dma_ops/port_ops routines.
>>
>> Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
>> ---
>> This patch is against linux-next 20080916.
>>
>> Changes since v1:
>> * rework IO accessors
>> * rework pio/dma timing setup
>> * use ide_get_pair_dev
>> * do not do ATA hard reset
>> * and so on  (Many thanks to Sergei)
>>     
>
> Sergei, are you OK with this version?
>   

   I didn't have tome to look at it.

WBR, Sergei



From markus.gothe@27m.se Fri Sep 19 10:42:28 2008
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-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA256

Looks like the FPU-Emulator isn't working. Which kernel versions are
you using?

//Markus

Klatt Uwe wrote:
> Hello,
>
> I have a custom hardware (AU1100) with kernel 2.4 and an working binary
using floats (compiled with gcc 3.3.5).
> Now I am testing with kernel 2.6.
>
> When I use the old binary, float math isn't working anymore.
> I have to recompile the source with new gcc 4.1.2 but then the new
binary is working only on kernel 2.6.
>
> Can somebody give me some hints, how to chage settings for kernel 2.6
creation or compiler settings to generate an universal binary.
>
> Thanks
> Uwe
>


- --
_______________________________________

Mr Markus Gothe
Software Engineer

Phone: +46 (0)13 21 81 20 (ext. 1046)
Fax: +46 (0)13 21 21 15
Mobile: +46 (0)70 348 44 35
Diskettgatan 11, SE-583 35 Linköping, Sweden
www.27m.com
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From macro@linux-mips.org Fri Sep 19 11:12:48 2008
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References: <Pine.LNX.4.55.0809171104290.17103@cliff.in.clinika.pl>
 <20080917.222350.41199051.anemo@mba.ocn.ne.jp>
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On Fri, 19 Sep 2008, Ralf Baechle wrote:

> Which is a truely weird operation - but MIPS R2 happens to have a wonderful
> instruction for this operation, WSBH / DSBH.

 Ah, finally a justification for the R2 ISA!

 Seriously though, I smell a caller somewhere fails to call csum_fold() on
the result obtained from csum_partial() where it should, so it would be
good to fix the bug rather than trying to cover it.  Bryan, would you be
able to track down the caller?

 I can see you have done the microoptimisation I had in mind meanwhile --
thanks for saving me the effort. ;)  There is a delay slot to fill left
though -- will you take care of it too?

  Maciej

From sshtylyov@ru.mvista.com Fri Sep 19 11:15:10 2008
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To:	Dinar Temirbulatov <dtemirbulatov@gmail.com>
Cc:	linux-mips@linux-mips.org
Subject: Re: mmap is broken for MIPS64 n32 and o32 abis
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Hello.

Dinar Temirbulatov wrote:

> I noticed that mmap is not working properly under n32, o32 abis in
> MIPS64, for example if we want to map 0xb6000000 address to the
> userland under those abis we call  mmap and because the last argument
> in old_mmap is off_t and this type is 64-bits wide for MIPS64, we end
> up having for example 0xffffffffb6000000 address value. I am sure that
> this is not a glibc issue. Following patch adds 32-bit version of mmap
> and also it adds mmap64 support for n32 abi since mmap64 was
> implemented correctly for n32 too.
>                                           thanks, Dinar.
>   

  Your patch (BTW, how come it didn't get quoted? -- ah, it's 
text/x-patch) is using both tabs and spaces for indentation. Please use 
tabs only.
And either attach patches as text/plain or include them inline.

WBR, Sergei



From ralf@linux-mips.org Fri Sep 19 11:34:34 2008
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On Fri, Sep 19, 2008 at 09:58:29AM +0200, Klatt Uwe wrote:

> I have a custom hardware (AU1100) with kernel 2.4 and an working binary using floats (compiled with gcc 3.3.5).
> Now I am testing with kernel 2.6.
> 
> When I use the old binary, float math isn't working anymore.
> I have to recompile the source with new gcc 4.1.2 but then the new binary is working only on kernel 2.6.

Are you using the kernel floating point emulator or a software floating
point library?

Whatever, it sounds like a bug.  The kernel is supposed to be backward
compatible with old binaries.

  Ralf

From U.Klatt@miwe.de Fri Sep 19 11:56:27 2008
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Hello Ralf,

I link both binaries with -lm.
Could it be a problem with libc?
I will try to compile the new kernel with old compiler...

Bye
Uwe

> Are you using the kernel floating point emulator or a
> software floating
> point library?
>
> Whatever, it sounds like a bug.  The kernel is supposed to be backward
> compatible with old binaries.
>
>   Ralf
>

From U.Klatt@miwe.de Fri Sep 19 11:58:28 2008
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Hello Markus,

I use kernel 2.6.22.6 (this version is a special version from
hardware manufacturer).
I have complete source and can build this kernel without
problems (crosscompiled on x86).

I think the kernel should have fp emulator:
"Algorithmics/MIPS FPU Emulator v1.5" is displayed on boot.

Uwe

> -----BEGIN PGP SIGNED MESSAGE-----
> Hash: SHA256
>
> Looks like the FPU-Emulator isn't working. Which kernel versions are
> you using?
>
> //Markus
>
> Klatt Uwe wrote:
> > Hello,
> >
> > I have a custom hardware (AU1100) with kernel 2.4 and an
> working binary
> using floats (compiled with gcc 3.3.5).
> > Now I am testing with kernel 2.6.
> >
> > When I use the old binary, float math isn't working anymore.
> > I have to recompile the source with new gcc 4.1.2 but then the new
> binary is working only on kernel 2.6.
> >
> > Can somebody give me some hints, how to chage settings for
> kernel 2.6
> creation or compiler settings to generate an universal binary.
> >
> > Thanks
> > Uwe
> >
>
>
> - --
> _______________________________________
>
> Mr Markus Gothe
> Software Engineer
>
> Phone: +46 (0)13 21 81 20 (ext. 1046)
> Fax: +46 (0)13 21 21 15
> Mobile: +46 (0)70 348 44 35
> Diskettgatan 11, SE-583 35 Linköping, Sweden
> www.27m.com
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> Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org
>
> iD8DBQFI03Pn6I0XmJx2NrwRCH4eAJwMWR2/SrFaWRJAWMul9sK/GvATdQCaAgmJ
> LnzfYvUmO6mzyV5QMKtCmKs=
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>

From ralf@linux-mips.org Fri Sep 19 12:23:07 2008
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Subject: Re: MIPS checksum bug
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On Fri, Sep 19, 2008 at 11:12:22AM +0100, Maciej W. Rozycki wrote:

> > Which is a truely weird operation - but MIPS R2 happens to have a wonderful
> > instruction for this operation, WSBH / DSBH.
> 
>  Ah, finally a justification for the R2 ISA!

As you may recall the real reason is that this instruction was designed
not by engineers but patent law.  Which is f*cked into the head but ...

>  Seriously though, I smell a caller somewhere fails to call csum_fold() on
> the result obtained from csum_partial() where it should, so it would be
> good to fix the bug rather than trying to cover it.  Bryan, would you be
> able to track down the caller?

Not quite.  Internally the IP stack maintains the checksum as a 32-bit
value for performance sake.  It only folds it to 16-bit when it has to.

>  I can see you have done the microoptimisation I had in mind meanwhile --
> thanks for saving me the effort. ;)  There is a delay slot to fill left
> though -- will you take care of it too?

Will do - just couldn't be bothered (too) late last night ...

  Ralf

From ralf@linux-mips.org Fri Sep 19 12:47:45 2008
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Subject: [PATCH] MIPS checksum fix
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On Fri, Sep 19, 2008 at 01:23:04PM +0200, Ralf Baechle wrote:

> >  I can see you have done the microoptimisation I had in mind meanwhile --
> > thanks for saving me the effort. ;)  There is a delay slot to fill left
> > though -- will you take care of it too?
> 
> Will do - just couldn't be bothered (too) late last night ...

Voila.

I'm interested in test reports of this on all sorts of configurations -
32-bit, 64-bit, big / little endian, R2 processors and pre-R2.  In
particular Cavium being the only MIPS64 R2 implementation would be
interesting.  This definately is stuff which should go upstream for 2.6.27.

  Ralf

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

diff --git a/arch/mips/lib/csum_partial.S b/arch/mips/lib/csum_partial.S
index 8d77841..eac0d61 100644
--- a/arch/mips/lib/csum_partial.S
+++ b/arch/mips/lib/csum_partial.S
@@ -53,12 +53,14 @@
 #define UNIT(unit)  ((unit)*NBYTES)
 
 #define ADDC(sum,reg)						\
-	.set	push;						\
-	.set	noat;						\
 	ADD	sum, reg;					\
 	sltu	v1, sum, reg;					\
 	ADD	sum, v1;					\
-	.set	pop
+
+#define ADDC32(sum,reg)						\
+	addu	sum, reg;					\
+	sltu	v1, sum, reg;					\
+	addu	sum, v1;					\
 
 #define CSUM_BIGCHUNK1(src, offset, sum, _t0, _t1, _t2, _t3)	\
 	LOAD	_t0, (offset + UNIT(0))(src);			\
@@ -254,8 +256,6 @@ LEAF(csum_partial)
 1:	ADDC(sum, t1)
 
 	/* fold checksum */
-	.set	push
-	.set	noat
 #ifdef USE_DOUBLE
 	dsll32	v1, sum, 0
 	daddu	sum, v1
@@ -263,24 +263,25 @@ LEAF(csum_partial)
 	dsra32	sum, sum, 0
 	addu	sum, v1
 #endif
-	sll	v1, sum, 16
-	addu	sum, v1
-	sltu	v1, sum, v1
-	srl	sum, sum, 16
-	addu	sum, v1
 
 	/* odd buffer alignment? */
-	beqz	t7, 1f
-	 nop
-	sll	v1, sum, 8
+#ifdef CPU_MIPSR2
+	wsbh	sum, sum	
+	movn	sum, v1, t7
+#else
+	beqz	t7, 1f			/* odd buffer alignment? */
+	 lui	v1, 0x00ff
+	addu	v1, 0x00ff
+	and	t0, sum, v1
+	sll	t0, t0, 8
 	srl	sum, sum, 8
-	or	sum, v1
-	andi	sum, 0xffff
-	.set	pop
+	and	sum, sum, v1
+	or	sum, sum, t0
 1:
+#endif
 	.set	reorder
 	/* Add the passed partial csum.  */
-	ADDC(sum, a2)
+	ADDC32(sum, a2)
 	jr	ra
 	.set	noreorder
 	END(csum_partial)
@@ -656,8 +657,6 @@ EXC(	sb	t0, NBYTES-2(dst), .Ls_exc)
 	ADDC(sum, t2)
 .Ldone:
 	/* fold checksum */
-	.set	push
-	.set	noat
 #ifdef USE_DOUBLE
 	dsll32	v1, sum, 0
 	daddu	sum, v1
@@ -665,23 +664,23 @@ EXC(	sb	t0, NBYTES-2(dst), .Ls_exc)
 	dsra32	sum, sum, 0
 	addu	sum, v1
 #endif
-	sll	v1, sum, 16
-	addu	sum, v1
-	sltu	v1, sum, v1
-	srl	sum, sum, 16
-	addu	sum, v1
 
-	/* odd buffer alignment? */
-	beqz	odd, 1f
-	 nop
-	sll	v1, sum, 8
+#ifdef CPU_MIPSR2
+	wsbh	v1, sum
+	movn	sum, v1, odd
+#else
+	beqz	odd, 1f			/* odd buffer alignment? */
+	 lui	v1, 0x00ff
+	addu	v1, 0x00ff
+	and	t0, sum, v1
+	sll	t0, t0, 8
 	srl	sum, sum, 8
-	or	sum, v1
-	andi	sum, 0xffff
-	.set	pop
+	and	sum, sum, v1
+	or	sum, sum, t0
 1:
+#endif
 	.set reorder
-	ADDC(sum, psum)
+	ADDC32(sum, psum)
 	jr	ra
 	.set noreorder
 

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On Fri, Sep 19, 2008 at 01:47:43PM +0200, Ralf Baechle wrote:

> I'm interested in test reports of this on all sorts of configurations -
> 32-bit, 64-bit, big / little endian, R2 processors and pre-R2.  In
> particular Cavium being the only MIPS64 R2 implementation would be
> interesting.  This definately is stuff which should go upstream for 2.6.27.

There was a trivial bug in the R2 code.

From 97ad23f4696a322cb3bc379a25a8c0f6526751d6 Mon Sep 17 00:00:00 2001
From: Ralf Baechle <ralf@linux-mips.org>
Date: Fri, 19 Sep 2008 14:05:53 +0200
Subject: [PATCH] [MIPS] Fix 64-bit csum_partial, __csum_partial_copy_user and csum_partial_copy
Content-Length: 2461
Lines: 122

On 64-bit machines it wouldn't handle a possible carry when adding the
32-bit folded checksum and checksum argument.

While at it, add a few trivial optimizations, also for R2 processors.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

diff --git a/arch/mips/lib/csum_partial.S b/arch/mips/lib/csum_partial.S
index 8d77841..c77a7a0 100644
--- a/arch/mips/lib/csum_partial.S
+++ b/arch/mips/lib/csum_partial.S
@@ -53,12 +53,14 @@
 #define UNIT(unit)  ((unit)*NBYTES)
 
 #define ADDC(sum,reg)						\
-	.set	push;						\
-	.set	noat;						\
 	ADD	sum, reg;					\
 	sltu	v1, sum, reg;					\
 	ADD	sum, v1;					\
-	.set	pop
+
+#define ADDC32(sum,reg)						\
+	addu	sum, reg;					\
+	sltu	v1, sum, reg;					\
+	addu	sum, v1;					\
 
 #define CSUM_BIGCHUNK1(src, offset, sum, _t0, _t1, _t2, _t3)	\
 	LOAD	_t0, (offset + UNIT(0))(src);			\
@@ -254,8 +256,6 @@ LEAF(csum_partial)
 1:	ADDC(sum, t1)
 
 	/* fold checksum */
-	.set	push
-	.set	noat
 #ifdef USE_DOUBLE
 	dsll32	v1, sum, 0
 	daddu	sum, v1
@@ -263,24 +263,25 @@ LEAF(csum_partial)
 	dsra32	sum, sum, 0
 	addu	sum, v1
 #endif
-	sll	v1, sum, 16
-	addu	sum, v1
-	sltu	v1, sum, v1
-	srl	sum, sum, 16
-	addu	sum, v1
 
 	/* odd buffer alignment? */
-	beqz	t7, 1f
-	 nop
-	sll	v1, sum, 8
+#ifdef CPU_MIPSR2
+	wsbh	v1, sum	
+	movn	sum, v1, t7
+#else
+	beqz	t7, 1f			/* odd buffer alignment? */
+	 lui	v1, 0x00ff
+	addu	v1, 0x00ff
+	and	t0, sum, v1
+	sll	t0, t0, 8
 	srl	sum, sum, 8
-	or	sum, v1
-	andi	sum, 0xffff
-	.set	pop
+	and	sum, sum, v1
+	or	sum, sum, t0
 1:
+#endif
 	.set	reorder
 	/* Add the passed partial csum.  */
-	ADDC(sum, a2)
+	ADDC32(sum, a2)
 	jr	ra
 	.set	noreorder
 	END(csum_partial)
@@ -656,8 +657,6 @@ EXC(	sb	t0, NBYTES-2(dst), .Ls_exc)
 	ADDC(sum, t2)
 .Ldone:
 	/* fold checksum */
-	.set	push
-	.set	noat
 #ifdef USE_DOUBLE
 	dsll32	v1, sum, 0
 	daddu	sum, v1
@@ -665,23 +664,23 @@ EXC(	sb	t0, NBYTES-2(dst), .Ls_exc)
 	dsra32	sum, sum, 0
 	addu	sum, v1
 #endif
-	sll	v1, sum, 16
-	addu	sum, v1
-	sltu	v1, sum, v1
-	srl	sum, sum, 16
-	addu	sum, v1
 
-	/* odd buffer alignment? */
-	beqz	odd, 1f
-	 nop
-	sll	v1, sum, 8
+#ifdef CPU_MIPSR2
+	wsbh	v1, sum
+	movn	sum, v1, odd
+#else
+	beqz	odd, 1f			/* odd buffer alignment? */
+	 lui	v1, 0x00ff
+	addu	v1, 0x00ff
+	and	t0, sum, v1
+	sll	t0, t0, 8
 	srl	sum, sum, 8
-	or	sum, v1
-	andi	sum, 0xffff
-	.set	pop
+	and	sum, sum, v1
+	or	sum, sum, t0
 1:
+#endif
 	.set reorder
-	ADDC(sum, psum)
+	ADDC32(sum, psum)
 	jr	ra
 	.set noreorder
 

From macro@linux-mips.org Fri Sep 19 13:16:01 2008
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On Fri, 19 Sep 2008, Ralf Baechle wrote:

> +	beqz	t7, 1f			/* odd buffer alignment? */
> +	 lui	v1, 0x00ff

 Well, .set reorder to move something from before the branch would have 
been a little bit better for the common aligned case. ;)  There is nothing 
special about branch delay slots in the whole epilogue, so one from just 
before the return might simply be relocated here.

  Maciej

From macro@linux-mips.org Fri Sep 19 13:26:28 2008
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On Fri, 19 Sep 2008, Ralf Baechle wrote:

> >  Seriously though, I smell a caller somewhere fails to call csum_fold() on
> > the result obtained from csum_partial() where it should, so it would be
> > good to fix the bug rather than trying to cover it.  Bryan, would you be
> > able to track down the caller?
> 
> Not quite.  Internally the IP stack maintains the checksum as a 32-bit
> value for performance sake.  It only folds it to 16-bit when it has to.

 That's been my understanding from my little investigation yesterday
evening, but Bryan's problem has come from somewhere after all and
Atsushi-san's 32-bit addition fix didn't reportedly work while full
folding did, so I have assumed there must be some dependency somewhere
where the final folding does not happen.  I have referred to the original
report concerning SPARC64 now and it seems to narrow the problem down to
the 32 MSBs only, so I would prefer to have any confusion cleared.

 Bryan, can you please verify whether Ralf's fix works for you or not?

  Maciej

From macro@linux-mips.org Fri Sep 19 13:34:07 2008
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On Fri, 19 Sep 2008, Dinar Temirbulatov wrote:

> I noticed that mmap is not working properly under n32, o32 abis in
> MIPS64, for example if we want to map 0xb6000000 address to the
> userland under those abis we call  mmap and because the last argument
> in old_mmap is off_t and this type is 64-bits wide for MIPS64, we end
> up having for example 0xffffffffb6000000 address value. I am sure that
> this is not a glibc issue. Following patch adds 32-bit version of mmap
> and also it adds mmap64 support for n32 abi since mmap64 was
> implemented correctly for n32 too.

 Well, neither with the o32 nor with the n32 ABI are 0xb6000000 or
0xffffffffb6000000 (which is the n32's equivalent of the former) valid
user addresses, so your concern is?

  Maciej

From kevink@paralogos.com Fri Sep 19 14:26:28 2008
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When you say "float math isn't working", what do you mean?  When you say 
that the new binary
only works with the 2.6 kernel, what do you mean?  Are you getting bad 
answers, or is the program
crashing?  If it's crashing, and you run it under gdb, where is it 
blowing up, and why?  Are you able
to re-create the "old" binary?   If you do a static link of the program 
using the old tools,
does the resulting binary work better under 2.6?

The FPU emulator has bad some minor cleanup over the past few years, but 
it's been pretty
stable, and I can't recall having seen any serious functional or 
compatibility problems in a long
time.  I think it's more likely that you've got a problem with libraries 
and/or build procedures
for the application.

          Regards,

          Kevin K.

Klatt Uwe wrote:
> Hello,
>
> I have a custom hardware (AU1100) with kernel 2.4 and an working binary using floats (compiled with gcc 3.3.5).
> Now I am testing with kernel 2.6.
>
> When I use the old binary, float math isn't working anymore.
> I have to recompile the source with new gcc 4.1.2 but then the new binary is working only on kernel 2.6.
>
> Can somebody give me some hints, how to chage settings for kernel 2.6 creation or compiler settings to generate an universal binary.
>
> Thanks
> Uwe
>
>
>   

From U.Klatt@miwe.de Fri Sep 19 14:40:11 2008
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Hello everybody,

> I think it's more likely that you've got a problem
> with libraries and/or build procedures
> for the application.
You are right!

It's a problem with shared libs.
When I link static everything works now.
Thank you for your patience.

Bye
Uwe

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On Fri, 19 Sep 2008 14:07:52 +0200, Ralf Baechle <ralf@linux-mips.org> wrote:
> From 97ad23f4696a322cb3bc379a25a8c0f6526751d6 Mon Sep 17 00:00:00 2001
> From: Ralf Baechle <ralf@linux-mips.org>
> Date: Fri, 19 Sep 2008 14:05:53 +0200
> Subject: [PATCH] [MIPS] Fix 64-bit csum_partial, __csum_partial_copy_user and csum_partial_copy

... and __csum_partial_copy_nocheck, you mean? ;)

> On 64-bit machines it wouldn't handle a possible carry when adding the
> 32-bit folded checksum and checksum argument.
> 
> While at it, add a few trivial optimizations, also for R2 processors.

I think it would be better splitting bugfix and optimization.  This
code is too complex to do many things at a time, isn't it?

> @@ -53,12 +53,14 @@
>  #define UNIT(unit)  ((unit)*NBYTES)
>  
>  #define ADDC(sum,reg)						\
> -	.set	push;						\
> -	.set	noat;						\
>  	ADD	sum, reg;					\
>  	sltu	v1, sum, reg;					\
>  	ADD	sum, v1;					\
> -	.set	pop

Is this required?  Just a cleanup?

> @@ -254,8 +256,6 @@ LEAF(csum_partial)
>  1:	ADDC(sum, t1)
>  
>  	/* fold checksum */
> -	.set	push
> -	.set	noat
>  #ifdef USE_DOUBLE
>  	dsll32	v1, sum, 0
>  	daddu	sum, v1
> @@ -263,24 +263,25 @@ LEAF(csum_partial)
>  	dsra32	sum, sum, 0
>  	addu	sum, v1
>  #endif
> -	sll	v1, sum, 16
> -	addu	sum, v1
> -	sltu	v1, sum, v1
> -	srl	sum, sum, 16
> -	addu	sum, v1
>  
>  	/* odd buffer alignment? */
> -	beqz	t7, 1f
> -	 nop
> -	sll	v1, sum, 8
> +#ifdef CPU_MIPSR2
> +	wsbh	v1, sum	
> +	movn	sum, v1, t7
> +#else
> +	beqz	t7, 1f			/* odd buffer alignment? */
> +	 lui	v1, 0x00ff
> +	addu	v1, 0x00ff
> +	and	t0, sum, v1
> +	sll	t0, t0, 8
>  	srl	sum, sum, 8
> -	or	sum, v1
> -	andi	sum, 0xffff
> -	.set	pop
> +	and	sum, sum, v1
> +	or	sum, sum, t0
>  1:
> +#endif

Is this just an optimization?  or contain any fixes?

---
Atsushi Nemoto

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On Fri, 19 Sep 2008, Atsushi Nemoto wrote:

> I think it would be better splitting bugfix and optimization.  This
> code is too complex to do many things at a time, isn't it?

 It's probably easier for people to test a single patch now and it can
then be split at the commitment time.  Of course if something actually
breaks, then keeping changes combined won't help tracking down the cause.  
;)

  Maciej

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Subject: Re: MIPS checksum bug
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On Fri, 19 Sep 2008 01:17:04 +0900 (JST), Atsushi Nemoto <anemo@mba.ocn.ne.jp> wrote:
> Thank you for testing.  Though this patch did not fixed your problem,
> I still have a doubt on 64-bit optimization.
> 
> If your hardware could run 32-bit kernel, could you confirm the
> problem can happens in 32-bit too or not?

I think I found possible breakage on 64-bit path.

There are some "lw" (and "ulw") used in 64-bit path and they should be
"lwu" (and "ulwu" ... but there is no such pseudo insn) to avoid
sign-extention.

Here is a completely untested patch.

diff --git a/arch/mips/lib/csum_partial.S b/arch/mips/lib/csum_partial.S
index 8d77841..40f9174 100644
--- a/arch/mips/lib/csum_partial.S
+++ b/arch/mips/lib/csum_partial.S
@@ -39,12 +39,14 @@
 #ifdef USE_DOUBLE
 
 #define LOAD   ld
+#define LOAD32 lwu
 #define ADD    daddu
 #define NBYTES 8
 
 #else
 
 #define LOAD   lw
+#define LOAD32 lw
 #define ADD    addu
 #define NBYTES 4
 
@@ -60,6 +62,14 @@
 	ADD	sum, v1;					\
 	.set	pop
 
+#define ADDC32(sum,reg)						\
+	.set	push;						\
+	.set	noat;						\
+	addu	sum, reg;					\
+	sltu	v1, sum, reg;					\
+	addu	sum, v1;					\
+	.set	pop
+
 #define CSUM_BIGCHUNK1(src, offset, sum, _t0, _t1, _t2, _t3)	\
 	LOAD	_t0, (offset + UNIT(0))(src);			\
 	LOAD	_t1, (offset + UNIT(1))(src);			\
@@ -132,7 +142,7 @@ LEAF(csum_partial)
 	beqz	t8, .Lqword_align
 	 andi	t8, src, 0x8
 
-	lw	t0, 0x00(src)
+	LOAD32	t0, 0x00(src)
 	LONG_SUBU	a1, a1, 0x4
 	ADDC(sum, t0)
 	PTR_ADDU	src, src, 0x4
@@ -211,7 +221,7 @@ LEAF(csum_partial)
 	LONG_SRL	t8, t8, 0x2
 
 .Lend_words:
-	lw	t0, (src)
+	LOAD32	t0, (src)
 	LONG_SUBU	t8, t8, 0x1
 	ADDC(sum, t0)
 	.set	reorder				/* DADDI_WAR */
@@ -229,6 +239,9 @@ LEAF(csum_partial)
 
 	/* Still a full word to go  */
 	ulw	t1, (src)
+#ifdef USE_DOUBLE
+	add	t1, zero	/* clear upper 32bit */
+#endif
 	PTR_ADDIU	src, 4
 	ADDC(sum, t1)
 
@@ -280,7 +293,7 @@ LEAF(csum_partial)
 1:
 	.set	reorder
 	/* Add the passed partial csum.  */
-	ADDC(sum, a2)
+	ADDC32(sum, a2)
 	jr	ra
 	.set	noreorder
 	END(csum_partial)
@@ -681,7 +694,7 @@ EXC(	sb	t0, NBYTES-2(dst), .Ls_exc)
 	.set	pop
 1:
 	.set reorder
-	ADDC(sum, psum)
+	ADDC32(sum, psum)
 	jr	ra
 	.set noreorder
 

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On Sep 19, 2008, at 5:26 AM, Maciej W. Rozycki wrote:

> On Fri, 19 Sep 2008, Ralf Baechle wrote:
>
>>> Seriously though, I smell a caller somewhere fails to call  
>>> csum_fold() on
>>> the result obtained from csum_partial() where it should, so it  
>>> would be
>>> good to fix the bug rather than trying to cover it.  Bryan, would  
>>> you be
>>> able to track down the caller?
>>
>> Not quite.  Internally the IP stack maintains the checksum as a 32- 
>> bit
>> value for performance sake.  It only folds it to 16-bit when it has  
>> to.
>
> That's been my understanding from my little investigation yesterday
> evening, but Bryan's problem has come from somewhere after all and
> Atsushi-san's 32-bit addition fix didn't reportedly work while full
> folding did, so I have assumed there must be some dependency somewhere
> where the final folding does not happen.  I have referred to the  
> original
> report concerning SPARC64 now and it seems to narrow the problem  
> down to
> the 32 MSBs only, so I would prefer to have any confusion cleared.
>
> Bryan, can you please verify whether Ralf's fix works for you or not?


Ralph is correct on the usage of the checksum by the IP stack, and the  
original problem report on the Sparc64 list is pretty thorough about  
describing how the bug affects the stack.

original report: http://www.spinics.net/lists/sparclinux/msg00173.html
resolution: http://www.spinics.net/lists/sparclinux/msg00179.html

A synopsis is that when TCP resends a portion of a segment whose  
checksum was already previously calculated (correctly), it splits the  
segment into a new and shortened old segment [see net/ipv4/ 
tcp_output.c:tcp_fragment "Copy and checksum data tail into the new  
buffer" ~ line 737ish].  The new segment has its checksum calculated  
via csum_partial_copy_nocheck(), and the shortened old segment has its  
checksum calculated via csum_block_sub() (for fast checksum delta).   
It is the path through csum_block_sub() where the bug occurs, in which  
the output from csum_block_sub() has the upper bits of the csum set  
for the carry, and later when tcp_v4_send_check() is called with the  
skb->csum, the csum is off-by-one.  Obviously all of these need to be  
in the non-hardware checksum case.

I can test a patch later today on the Cavium CN3010 64bit; I have been  
running with the suboptimal but apparently effective fold-relocation  
patch and the problem is completely gone, fwiw.

Also... I was thinking it would be trivial to extract the relevant  
bits of the trigger from this repro and just write a small native app  
to test the csum generation-and-return; I though about doing it myself  
earlier, because I have a tcpdump capture of the segment that was  
triggering the bug.

--
-bp


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On Sat, 20 Sep 2008, Atsushi Nemoto wrote:

> @@ -229,6 +239,9 @@ LEAF(csum_partial)
>  
>  	/* Still a full word to go  */
>  	ulw	t1, (src)
> +#ifdef USE_DOUBLE
> +	add	t1, zero	/* clear upper 32bit */
> +#endif
>  	PTR_ADDIU	src, 4
>  	ADDC(sum, t1)
>  

 Unfortunately you can't zero-extend with a single instruction (you can
use a single sll(v) to sign-extend), unless the R2 ISA provides some
suitable oddity (which I haven't checked).  You want something like:

	dsll32	t1, t1, 0
	dsrl32	t1, t1, 0

instead.

  Maciej

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Maciej W. Rozycki wrote:
> On Sat, 20 Sep 2008, Atsushi Nemoto wrote:
> 
> > @@ -229,6 +239,9 @@ LEAF(csum_partial)
> >  
> >  	/* Still a full word to go  */
> >  	ulw	t1, (src)
> > +#ifdef USE_DOUBLE
> > +	add	t1, zero	/* clear upper 32bit */
> > +#endif
> >  	PTR_ADDIU	src, 4
> >  	ADDC(sum, t1)
> >  
> 
>  Unfortunately you can't zero-extend with a single instruction (you can
> use a single sll(v) to sign-extend), unless the R2 ISA provides some
> suitable oddity (which I haven't checked).

AFAIR dext can do this for MIPS64 R2.


Thiemo

From dtemirbulatov@gmail.com Fri Sep 19 17:53:24 2008
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Date:	Fri, 19 Sep 2008 20:53:20 +0400
From:	"Dinar Temirbulatov" <dtemirbulatov@gmail.com>
To:	"Maciej W. Rozycki" <macro@linux-mips.org>
Subject: Re: mmap is broken for MIPS64 n32 and o32 abis
Cc:	linux-mips@linux-mips.org
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Hi,
The first address 0xb6000000 is a physical memory 32-bit address that
we are trying to map under n32 or o32 and it is valid.
         mmh = open("/dev/mem", O_RDWR | O_SYNC);
         if (mmh < 0) {
             .....
         }
         mmptr = (unsigned short *)mmap((void *)0, 0x1000,
                             PROT_READ | PROT_WRITE, MAP_SHARED,
                             mmh, 0xb6000000);
         ...

and the second one 0xffffffffb6000000 address is that old_mmap have
got on the kernel side when we do mmap under those abis,  calling
do_mmap2 after that with 0xffffffffb6000000 last parameter. This
example above works correctly only under n64 abi.

thanks, Dinar.

On Fri, Sep 19, 2008 at 4:33 PM, Maciej W. Rozycki <macro@linux-mips.org> wrote:
> On Fri, 19 Sep 2008, Dinar Temirbulatov wrote:
>
>> I noticed that mmap is not working properly under n32, o32 abis in
>> MIPS64, for example if we want to map 0xb6000000 address to the
>> userland under those abis we call  mmap and because the last argument
>> in old_mmap is off_t and this type is 64-bits wide for MIPS64, we end
>> up having for example 0xffffffffb6000000 address value. I am sure that
>> this is not a glibc issue. Following patch adds 32-bit version of mmap
>> and also it adds mmap64 support for n32 abi since mmap64 was
>> implemented correctly for n32 too.
>
>  Well, neither with the o32 nor with the n32 ABI are 0xb6000000 or
> 0xffffffffb6000000 (which is the n32's equivalent of the former) valid
> user addresses, so your concern is?
>
>  Maciej
>

From bzolnier@gmail.com Fri Sep 19 18:11:07 2008
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From:	Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
To:	Sergei Shtylyov <sshtylyov@ru.mvista.com>
Subject: Re: [PATCH 1/2] ide: Add tx4939ide driver (v2)
Date:	Fri, 19 Sep 2008 10:10:08 -0700
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On Friday 19 September 2008 02:25:57 Sergei Shtylyov wrote:
> Hello.
> 
> Bartlomiej Zolnierkiewicz wrote:
> 
> >> This is the driver for the Toshiba TX4939 SoC ATA controller.
> >>
> >> This controller has standard ATA taskfile registers and DMA
> >> command/status registers, but the register layout is swapped on big
> >> endian.  There are some other endian issue and some special registers
> >> which requires many custom dma_ops/port_ops routines.
> >>
> >> Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
> >> ---
> >> This patch is against linux-next 20080916.
> >>
> >> Changes since v1:
> >> * rework IO accessors
> >> * rework pio/dma timing setup
> >> * use ide_get_pair_dev
> >> * do not do ATA hard reset
> >> * and so on  (Many thanks to Sergei)
> >>     
> >
> > Sergei, are you OK with this version?
> >   
> 
>    I didn't have tome to look at it.

I didn't mean to rush you.  I just prefer to have it in pata tree
because I may not have much time to work on ide next week and also
since the code looks much better now the further changes could be
addressed more effectively with the incremental patches.

Thanks,
Bart

From macro@linux-mips.org Fri Sep 19 18:25:52 2008
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On Fri, 19 Sep 2008, Dinar Temirbulatov wrote:

>          mmptr = (unsigned short *)mmap((void *)0, 0x1000,
>                              PROT_READ | PROT_WRITE, MAP_SHARED,
>                              mmh, 0xb6000000);

 Ah, so it is the file offset you are concerned about.  Fair enough then.  
Obviously the non-LFS 32-bit variation has to sign-extend the offset as
this is how the off_t type has been defined in this case, though it is
interesting to note that the kernel treats this argument as unsigned while
the C library API defines it as signed and there is no range checking in
between.  Hmm...

  Maciej

From macro@linux-mips.org Sat Sep 20 00:19:10 2008
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On Fri, 19 Sep 2008, Thiemo Seufer wrote:

> >  Unfortunately you can't zero-extend with a single instruction (you can
> > use a single sll(v) to sign-extend), unless the R2 ISA provides some
> > suitable oddity (which I haven't checked).
> 
> AFAIR dext can do this for MIPS64 R2.

 Yeah, I would have thought if anything, it would be something as odd as
that...

  Maciej

From ralf@linux-mips.org Sat Sep 20 01:13:48 2008
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On Fri, Sep 19, 2008 at 05:09:17PM +0100, Maciej W. Rozycki wrote:

> > @@ -229,6 +239,9 @@ LEAF(csum_partial)
> >  
> >  	/* Still a full word to go  */
> >  	ulw	t1, (src)
> > +#ifdef USE_DOUBLE
> > +	add	t1, zero	/* clear upper 32bit */
> > +#endif
> >  	PTR_ADDIU	src, 4
> >  	ADDC(sum, t1)
> >  
> 
>  Unfortunately you can't zero-extend with a single instruction (you can
> use a single sll(v) to sign-extend), unless the R2 ISA provides some
> suitable oddity (which I haven't checked).  You want something like:
> 
> 	dsll32	t1, t1, 0
> 	dsrl32	t1, t1, 0
> 
> instead.

For a one's complement checksum it doesn't matter in which of the 4
halfwords the data ends is loaded.  So the easiest solution is:

	/* Still a full word to go  */
	ulw     t1, (src)
#ifdef USE_DOUBLE
	dsll	t1, t1, 32		/* clear lower 32bit */
#endif
	PTR_ADDIU       src, 4
	ADDC(sum, t1)

  Ralf

From linux-mips@reliableembeddedsystems.com Sat Sep 20 06:09:12 2008
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Hi,

We've got an SMP8634 based set-top box from a 3rd party and are trying to
port some middleware to it.
Everything seems to work out fine, except for one thing ... the amount of
memory for kernel space.

The box physically has two 64MB chips and two 32MB chips.  
The kernel is only seeing the two 32MB chips, apparently attached to DRAM0.

The problem is the following:

1) The middleware requires more memory in kernel space to allocalte big
graphical surfaces.
2) Whatever runs before the kernel is also from a 3rd party and we don't
have access to it.
3) We can't change anything on the box hardware.

This means, we would only be able to patch starting from the Linux kernel.

Do you see any way to swap what the kernel sees to be 128MB instead of 64MB
and the user space 64MB minus whatever is allocated for the initial RAM
disc?
The 64MB for user space are sufficient, we just need more then 64 MB on
kernel space.

Regards,

Robert

-- 
Robert Berger
Embedded Software Specialist

Reliable Embedded Systems
Consulting Training Engineering
Tel.: (+30) 697 593 3428
Fax.:(+30 210) 684 7881
URL: http://www.reliableembeddedsystems.com
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From ddaney@avtrex.com Sat Sep 20 08:07:25 2008
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Date:	Sat, 20 Sep 2008 00:07:10 -0700
From:	David Daney <ddaney@avtrex.com>
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To:	linux-mips@reliableembeddedsystems.com
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Subject: Re: SMP8634 DRAM memory issue
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linux-mips@reliableembeddedsystems.com wrote:
> Hi,
> 
> We've got an SMP8634 based set-top box from a 3rd party and are trying to
> port some middleware to it.
> Everything seems to work out fine, except for one thing ... the amount of
> memory for kernel space.
> 
> The box physically has two 64MB chips and two 32MB chips.  
> The kernel is only seeing the two 32MB chips, apparently attached to DRAM0.
> 
> The problem is the following:
> 
> 1) The middleware requires more memory in kernel space to allocalte big
> graphical surfaces.
> 2) Whatever runs before the kernel is also from a 3rd party and we don't
> have access to it.
> 3) We can't change anything on the box hardware.
> 
> This means, we would only be able to patch starting from the Linux kernel.
> 
> Do you see any way to swap what the kernel sees to be 128MB instead of 64MB
> and the user space 64MB minus whatever is allocated for the initial RAM
> disc?
> The 64MB for user space are sufficient, we just need more then 64 MB on
> kernel space.
> 

It depends if the 128MB is on DRAM0 or DRAM1.  Typically DRAM1 is not
usable by the kernel, although others have tried to access it as high-mem.

If DRAM0 is 128MB, *and* you have access to the kernel command line, you
 might try to append something like 'mem=96M'.  You may need to leave
some space in DRAM0 for the media components.  If not try jacking it up
to mem=12