From dvorobye@movial.fi Fri Aug 1 10:40:49 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 01 Aug 2008 10:42:12 +0100 (BST) Received: from smtp.movial.fi ([62.236.91.34]:57298 "EHLO smtp.movial.fi") by ftp.linux-mips.org with ESMTP id S28574330AbYHAJk3 (ORCPT ); Fri, 1 Aug 2008 10:40:29 +0100 Received: from localhost (mailscanner.hel.movial.fi [172.17.81.9]) by smtp.movial.fi (Postfix) with ESMTP id 2BB87C8011; Fri, 1 Aug 2008 12:40:22 +0300 (EEST) X-Virus-Scanned: Debian amavisd-new at movial.fi Received: from smtp.movial.fi ([62.236.91.34]) by localhost (mailscanner.hel.movial.fi [172.17.81.9]) (amavisd-new, port 10026) with ESMTP id Vu7xFvbgzI7z; Fri, 1 Aug 2008 12:40:22 +0300 (EEST) Received: from sd048.hel.movial.fi (sd048.hel.movial.fi [172.17.49.48]) (using TLSv1 with cipher ADH-AES256-SHA (256/256 bits)) (No client certificate requested) by smtp.movial.fi (Postfix) with ESMTP id EEBA8C8014; Fri, 1 Aug 2008 12:40:21 +0300 (EEST) Received: by sd048.hel.movial.fi (Postfix, from userid 30120) id BB68A10806D; Fri, 1 Aug 2008 12:40:21 +0300 (EEST) From: Dmitri Vorobiev To: linux-mips@linux-mips.org, ralf@linux-mips.org, rpjday@crashcourse.ca Subject: [PATCH 1/7] [MIPS] Remove unused config variable MIPS_INSANE_LARGE Date: Fri, 1 Aug 2008 12:40:15 +0300 Message-Id: <1217583621-4772-2-git-send-email-dmitri.vorobiev@movial.fi> X-Mailer: git-send-email 1.5.6 In-Reply-To: <1217583621-4772-1-git-send-email-dmitri.vorobiev@movial.fi> References: <1217583621-4772-1-git-send-email-dmitri.vorobiev@movial.fi> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20064 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dmitri.vorobiev@movial.fi Precedence: bulk X-list: linux-mips The config variable MIPS_INSANE_LARGE is not used and can be removed. Build-tested using ip27_defconfig. Reported-by: Robert P. J. Day Signed-off-by: Dmitri Vorobiev --- arch/mips/Kconfig | 10 ---------- arch/mips/configs/ip27_defconfig | 1 - arch/mips/configs/ip28_defconfig | 1 - 3 files changed, 0 insertions(+), 12 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index b4c4eaa..8429773 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -1831,16 +1831,6 @@ config HZ source "kernel/Kconfig.preempt" -config MIPS_INSANE_LARGE - bool "Support for large 64-bit configurations" - depends on CPU_R10000 && 64BIT - help - MIPS R10000 does support a 44 bit / 16TB address space as opposed to - previous 64-bit processors which only supported 40 bit / 1TB. If you - need processes of more than 1TB virtual address space, say Y here. - This will result in additional memory usage, so it is not - recommended for normal users. - config KEXEC bool "Kexec system call (EXPERIMENTAL)" depends on EXPERIMENTAL diff --git a/arch/mips/configs/ip27_defconfig b/arch/mips/configs/ip27_defconfig index 138c575..bed6016 100644 --- a/arch/mips/configs/ip27_defconfig +++ b/arch/mips/configs/ip27_defconfig @@ -145,7 +145,6 @@ CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set CONFIG_PREEMPT_BKL=y -# CONFIG_MIPS_INSANE_LARGE is not set # CONFIG_KEXEC is not set CONFIG_SECCOMP=y CONFIG_LOCKDEP_SUPPORT=y diff --git a/arch/mips/configs/ip28_defconfig b/arch/mips/configs/ip28_defconfig index 822b01f..3540707 100644 --- a/arch/mips/configs/ip28_defconfig +++ b/arch/mips/configs/ip28_defconfig @@ -160,7 +160,6 @@ CONFIG_HZ=250 CONFIG_PREEMPT_VOLUNTARY=y # CONFIG_PREEMPT is not set # CONFIG_RCU_TRACE is not set -# CONFIG_MIPS_INSANE_LARGE is not set # CONFIG_KEXEC is not set CONFIG_SECCOMP=y CONFIG_LOCKDEP_SUPPORT=y -- 1.5.6 From dvorobye@movial.fi Fri Aug 1 10:42:30 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 01 Aug 2008 10:42:38 +0100 (BST) Received: from smtp.movial.fi ([62.236.91.34]:56786 "EHLO smtp.movial.fi") by ftp.linux-mips.org with ESMTP id S28574331AbYHAJk3 (ORCPT ); Fri, 1 Aug 2008 10:40:29 +0100 Received: from localhost (mailscanner.hel.movial.fi [172.17.81.9]) by smtp.movial.fi (Postfix) with ESMTP id 45A1EC8014; Fri, 1 Aug 2008 12:40:22 +0300 (EEST) X-Virus-Scanned: Debian amavisd-new at movial.fi Received: from smtp.movial.fi ([62.236.91.34]) by localhost (mailscanner.hel.movial.fi [172.17.81.9]) (amavisd-new, port 10026) with ESMTP id kVkD3Z9K+mzx; Fri, 1 Aug 2008 12:40:22 +0300 (EEST) Received: from sd048.hel.movial.fi (sd048.hel.movial.fi [172.17.49.48]) (using TLSv1 with cipher ADH-AES256-SHA (256/256 bits)) (No client certificate requested) by smtp.movial.fi (Postfix) with ESMTP id F222FC8016; Fri, 1 Aug 2008 12:40:21 +0300 (EEST) Received: by sd048.hel.movial.fi (Postfix, from userid 30120) id C02A710806E; Fri, 1 Aug 2008 12:40:21 +0300 (EEST) From: Dmitri Vorobiev To: linux-mips@linux-mips.org, ralf@linux-mips.org, rpjday@crashcourse.ca Subject: [PATCH 3/7] [MIPS] Remove unused config variable ARCH_SUPPORTS_OPROFILE Date: Fri, 1 Aug 2008 12:40:17 +0300 Message-Id: <1217583621-4772-4-git-send-email-dmitri.vorobiev@movial.fi> X-Mailer: git-send-email 1.5.6 In-Reply-To: <1217583621-4772-1-git-send-email-dmitri.vorobiev@movial.fi> References: <1217583621-4772-1-git-send-email-dmitri.vorobiev@movial.fi> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20065 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dmitri.vorobiev@movial.fi Precedence: bulk X-list: linux-mips The config variable ARCH_SUPPORTS_OPROFILE is defined but never used, and this patch removes the fossil. Reported-by: Robert P. J. Day Signed-off-by: Dmitri Vorobiev --- arch/mips/Kconfig | 4 ---- arch/mips/configs/bcm47xx_defconfig | 1 - arch/mips/configs/bigsur_defconfig | 1 - arch/mips/configs/ip28_defconfig | 1 - arch/mips/configs/jmr3927_defconfig | 1 - arch/mips/configs/rb532_defconfig | 1 - arch/mips/configs/rbtx49xx_defconfig | 1 - arch/mips/configs/sb1250-swarm_defconfig | 1 - arch/mips/configs/tb0219_defconfig | 1 - arch/mips/configs/tb0226_defconfig | 1 - arch/mips/configs/tb0287_defconfig | 1 - 11 files changed, 0 insertions(+), 14 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index fced035..f5e8720 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -633,10 +633,6 @@ config ARCH_HAS_ILOG2_U64 bool default n -config ARCH_SUPPORTS_OPROFILE - bool - default y if !MIPS_MT_SMTC - config GENERIC_FIND_NEXT_BIT bool default y diff --git a/arch/mips/configs/bcm47xx_defconfig b/arch/mips/configs/bcm47xx_defconfig index 0a81d31..9a59bc5 100644 --- a/arch/mips/configs/bcm47xx_defconfig +++ b/arch/mips/configs/bcm47xx_defconfig @@ -44,7 +44,6 @@ CONFIG_BCM47XX=y CONFIG_RWSEM_GENERIC_SPINLOCK=y # CONFIG_ARCH_HAS_ILOG2_U32 is not set # CONFIG_ARCH_HAS_ILOG2_U64 is not set -CONFIG_ARCH_SUPPORTS_OPROFILE=y CONFIG_GENERIC_FIND_NEXT_BIT=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y diff --git a/arch/mips/configs/bigsur_defconfig b/arch/mips/configs/bigsur_defconfig index 9aa8e6e..5034fd0 100644 --- a/arch/mips/configs/bigsur_defconfig +++ b/arch/mips/configs/bigsur_defconfig @@ -60,7 +60,6 @@ CONFIG_SIBYTE_HAS_ZBUS_PROFILING=y CONFIG_RWSEM_GENERIC_SPINLOCK=y # CONFIG_ARCH_HAS_ILOG2_U32 is not set # CONFIG_ARCH_HAS_ILOG2_U64 is not set -CONFIG_ARCH_SUPPORTS_OPROFILE=y CONFIG_GENERIC_FIND_NEXT_BIT=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y diff --git a/arch/mips/configs/ip28_defconfig b/arch/mips/configs/ip28_defconfig index 7f86d72..2f87189 100644 --- a/arch/mips/configs/ip28_defconfig +++ b/arch/mips/configs/ip28_defconfig @@ -44,7 +44,6 @@ CONFIG_SGI_IP28=y CONFIG_RWSEM_GENERIC_SPINLOCK=y # CONFIG_ARCH_HAS_ILOG2_U32 is not set # CONFIG_ARCH_HAS_ILOG2_U64 is not set -CONFIG_ARCH_SUPPORTS_OPROFILE=y CONFIG_GENERIC_FIND_NEXT_BIT=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y diff --git a/arch/mips/configs/jmr3927_defconfig b/arch/mips/configs/jmr3927_defconfig index f7e3527..cbacef0 100644 --- a/arch/mips/configs/jmr3927_defconfig +++ b/arch/mips/configs/jmr3927_defconfig @@ -47,7 +47,6 @@ CONFIG_PICMG_PCI_BACKPLANE_DEFAULT=y CONFIG_RWSEM_GENERIC_SPINLOCK=y # CONFIG_ARCH_HAS_ILOG2_U32 is not set # CONFIG_ARCH_HAS_ILOG2_U64 is not set -CONFIG_ARCH_SUPPORTS_OPROFILE=y CONFIG_GENERIC_FIND_NEXT_BIT=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y diff --git a/arch/mips/configs/rb532_defconfig b/arch/mips/configs/rb532_defconfig index 75eee9a..a8ef6bc 100644 --- a/arch/mips/configs/rb532_defconfig +++ b/arch/mips/configs/rb532_defconfig @@ -47,7 +47,6 @@ CONFIG_MIKROTIK_RB532=y CONFIG_RWSEM_GENERIC_SPINLOCK=y # CONFIG_ARCH_HAS_ILOG2_U32 is not set # CONFIG_ARCH_HAS_ILOG2_U64 is not set -CONFIG_ARCH_SUPPORTS_OPROFILE=y CONFIG_GENERIC_FIND_NEXT_BIT=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y diff --git a/arch/mips/configs/rbtx49xx_defconfig b/arch/mips/configs/rbtx49xx_defconfig index c9633d7..15e8a9a 100644 --- a/arch/mips/configs/rbtx49xx_defconfig +++ b/arch/mips/configs/rbtx49xx_defconfig @@ -57,7 +57,6 @@ CONFIG_PCI_TX4927=y CONFIG_RWSEM_GENERIC_SPINLOCK=y # CONFIG_ARCH_HAS_ILOG2_U32 is not set # CONFIG_ARCH_HAS_ILOG2_U64 is not set -CONFIG_ARCH_SUPPORTS_OPROFILE=y CONFIG_GENERIC_FIND_NEXT_BIT=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y diff --git a/arch/mips/configs/sb1250-swarm_defconfig b/arch/mips/configs/sb1250-swarm_defconfig index 72cef77..d938f14 100644 --- a/arch/mips/configs/sb1250-swarm_defconfig +++ b/arch/mips/configs/sb1250-swarm_defconfig @@ -62,7 +62,6 @@ CONFIG_SIBYTE_HAS_ZBUS_PROFILING=y CONFIG_RWSEM_GENERIC_SPINLOCK=y # CONFIG_ARCH_HAS_ILOG2_U32 is not set # CONFIG_ARCH_HAS_ILOG2_U64 is not set -CONFIG_ARCH_SUPPORTS_OPROFILE=y CONFIG_GENERIC_FIND_NEXT_BIT=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y diff --git a/arch/mips/configs/tb0219_defconfig b/arch/mips/configs/tb0219_defconfig index ebc3662..907a791 100644 --- a/arch/mips/configs/tb0219_defconfig +++ b/arch/mips/configs/tb0219_defconfig @@ -54,7 +54,6 @@ CONFIG_PCI_VR41XX=y CONFIG_RWSEM_GENERIC_SPINLOCK=y # CONFIG_ARCH_HAS_ILOG2_U32 is not set # CONFIG_ARCH_HAS_ILOG2_U64 is not set -CONFIG_ARCH_SUPPORTS_OPROFILE=y CONFIG_GENERIC_FIND_NEXT_BIT=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y diff --git a/arch/mips/configs/tb0226_defconfig b/arch/mips/configs/tb0226_defconfig index b8f6ce3..d06d745 100644 --- a/arch/mips/configs/tb0226_defconfig +++ b/arch/mips/configs/tb0226_defconfig @@ -54,7 +54,6 @@ CONFIG_PCI_VR41XX=y CONFIG_RWSEM_GENERIC_SPINLOCK=y # CONFIG_ARCH_HAS_ILOG2_U32 is not set # CONFIG_ARCH_HAS_ILOG2_U64 is not set -CONFIG_ARCH_SUPPORTS_OPROFILE=y CONFIG_GENERIC_FIND_NEXT_BIT=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y diff --git a/arch/mips/configs/tb0287_defconfig b/arch/mips/configs/tb0287_defconfig index b3dc2c8..7286994 100644 --- a/arch/mips/configs/tb0287_defconfig +++ b/arch/mips/configs/tb0287_defconfig @@ -54,7 +54,6 @@ CONFIG_PCI_VR41XX=y CONFIG_RWSEM_GENERIC_SPINLOCK=y # CONFIG_ARCH_HAS_ILOG2_U32 is not set # CONFIG_ARCH_HAS_ILOG2_U64 is not set -CONFIG_ARCH_SUPPORTS_OPROFILE=y CONFIG_GENERIC_FIND_NEXT_BIT=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y -- 1.5.6 From dvorobye@movial.fi Fri Aug 1 10:42:57 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 01 Aug 2008 10:43:04 +0100 (BST) Received: from smtp.movial.fi ([62.236.91.34]:57554 "EHLO smtp.movial.fi") by ftp.linux-mips.org with ESMTP id S28574328AbYHAJk3 (ORCPT ); Fri, 1 Aug 2008 10:40:29 +0100 Received: from localhost (mailscanner.hel.movial.fi [172.17.81.9]) by smtp.movial.fi (Postfix) with ESMTP id 6C009C806D; Fri, 1 Aug 2008 12:40:22 +0300 (EEST) X-Virus-Scanned: Debian amavisd-new at movial.fi Received: from smtp.movial.fi ([62.236.91.34]) by localhost (mailscanner.hel.movial.fi [172.17.81.9]) (amavisd-new, port 10026) with ESMTP id Os5S+5nNdNz3; Fri, 1 Aug 2008 12:40:22 +0300 (EEST) Received: from sd048.hel.movial.fi (sd048.hel.movial.fi [172.17.49.48]) (using TLSv1 with cipher ADH-AES256-SHA (256/256 bits)) (No client certificate requested) by smtp.movial.fi (Postfix) with ESMTP id 13949C8084; Fri, 1 Aug 2008 12:40:22 +0300 (EEST) Received: by sd048.hel.movial.fi (Postfix, from userid 30120) id D104F108071; Fri, 1 Aug 2008 12:40:21 +0300 (EEST) From: Dmitri Vorobiev To: linux-mips@linux-mips.org, ralf@linux-mips.org, rpjday@crashcourse.ca Subject: [PATCH 5/7] [MIPS] Remove dead code in excite_device.c Date: Fri, 1 Aug 2008 12:40:19 +0300 Message-Id: <1217583621-4772-6-git-send-email-dmitri.vorobiev@movial.fi> X-Mailer: git-send-email 1.5.6 In-Reply-To: <1217583621-4772-1-git-send-email-dmitri.vorobiev@movial.fi> References: <1217583621-4772-1-git-send-email-dmitri.vorobiev@movial.fi> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20066 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dmitri.vorobiev@movial.fi Precedence: bulk X-list: linux-mips The code under the following conditional compilation construct #if defined(CONFIG_EXCITE_FCAP_GPI) || defined(CONFIG_EXCITE_FCAP_GPI_MODULE) #endif does not have any chances to be compiled, since the relevant config options do not exist. This patch removes the dead code. Reported-by: Robert P. J. Day Signed-off-by: Dmitri Vorobiev --- arch/mips/basler/excite/excite_device.c | 69 ------------------------------- 1 files changed, 0 insertions(+), 69 deletions(-) diff --git a/arch/mips/basler/excite/excite_device.c b/arch/mips/basler/excite/excite_device.c index e00bc2d..479a0f7 100644 --- a/arch/mips/basler/excite/excite_device.c +++ b/arch/mips/basler/excite/excite_device.c @@ -159,75 +159,6 @@ static void adjust_resources(struct resource *res, unsigned int n) } } - - -#if defined(CONFIG_EXCITE_FCAP_GPI) || defined(CONFIG_EXCITE_FCAP_GPI_MODULE) -static struct resource xicap_rsrc[] = { - RINIT(0x4840, 0x486f, XICAP_RESOURCE_FIFO_RX, &excite_titan_resource), - RINIT(0x4940, 0x494b, XICAP_RESOURCE_FIFO_TX, &excite_titan_resource), - RINIT(0x5040, 0x5127, XICAP_RESOURCE_XDMA, &excite_titan_resource), - RINIT(0x1000, 0x112f, XICAP_RESOURCE_PKTPROC, &excite_titan_resource), - RINIT(0x1100, 0x110f, XICAP_RESOURCE_PKT_STREAM, &excite_fpga_resource), - RINIT(0x0800, 0x0bff, XICAP_RESOURCE_DMADESC, &excite_scram_resource), - RINIT(slice_xicap, slice_xicap, XICAP_RESOURCE_GPI_SLICE, &excite_gpislice_resource), - RINIT(0x0100, 0x02ff, XICAP_RESOURCE_FIFO_BLK, &excite_fifomem_resource), - RINIT_IRQ(TITAN_IRQ, XICAP_RESOURCE_IRQ) -}; - -static struct platform_device xicap_pdev = { - .name = XICAP_NAME, - .id = XICAP_UNIT, - .num_resources = ARRAY_SIZE(xicap_rsrc), - .resource = xicap_rsrc -}; - -/* - * Create a platform device for the GPI port that receives the - * image data from the embedded camera. - */ -static int __init xicap_devinit(void) -{ - unsigned long tend; - u32 reg; - int retval; - - adjust_resources(xicap_rsrc, ARRAY_SIZE(xicap_rsrc)); - - /* Power up the slice and configure it. */ - reg = titan_readl(CPTC1R); - reg &= ~(0x11100 << slice_xicap); - titan_writel(reg, CPTC1R); - - /* Enable slice & DLL. */ - reg= titan_readl(CPRR); - reg &= ~(0x00030003 << (slice_xicap * 2)); - titan_writel(reg, CPRR); - - /* Wait for DLLs to lock */ - tend = jiffies + DLL_TIMEOUT * HZ; - while (time_before(jiffies, tend)) { - if (!(~titan_readl(CPDSR) & (0x1 << (slice_xicap * 4)))) - break; - yield(); - } - - if (~titan_readl(CPDSR) & (0x1 << (slice_xicap * 4))) { - printk(KERN_ERR "%s: DLL not locked after %u seconds\n", - xicap_pdev.name, DLL_TIMEOUT); - retval = -ETIME; - } else { - /* Register platform device */ - retval = platform_device_register(&xicap_pdev); - } - - return retval; -} - -device_initcall(xicap_devinit); -#endif /* defined(CONFIG_EXCITE_FCAP_GPI) || defined(CONFIG_EXCITE_FCAP_GPI_MODULE) */ - - - #if defined(CONFIG_WDT_RM9K_GPI) || defined(CONFIG_WDT_RM9K_GPI_MODULE) static struct resource wdt_rsrc[] = { RINIT(0, 0, WDT_RESOURCE_COUNTER, &excite_ctr_resource), -- 1.5.6 From dvorobye@movial.fi Fri Aug 1 10:43:21 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 01 Aug 2008 10:43:29 +0100 (BST) Received: from smtp.movial.fi ([62.236.91.34]:61138 "EHLO smtp.movial.fi") by ftp.linux-mips.org with ESMTP id S28574357AbYHAJkg (ORCPT ); Fri, 1 Aug 2008 10:40:36 +0100 Received: from localhost (mailscanner.hel.movial.fi [172.17.81.9]) by smtp.movial.fi (Postfix) with ESMTP id 8CADCC8084; Fri, 1 Aug 2008 12:40:22 +0300 (EEST) X-Virus-Scanned: Debian amavisd-new at movial.fi Received: from smtp.movial.fi ([62.236.91.34]) by localhost (mailscanner.hel.movial.fi [172.17.81.9]) (amavisd-new, port 10026) with ESMTP id 7xjyR2M2Oj8L; Fri, 1 Aug 2008 12:40:22 +0300 (EEST) Received: from sd048.hel.movial.fi (sd048.hel.movial.fi [172.17.49.48]) (using TLSv1 with cipher ADH-AES256-SHA (256/256 bits)) (No client certificate requested) by smtp.movial.fi (Postfix) with ESMTP id 0A368C806C; Fri, 1 Aug 2008 12:40:22 +0300 (EEST) Received: by sd048.hel.movial.fi (Postfix, from userid 30120) id C8B7610806F; Fri, 1 Aug 2008 12:40:21 +0300 (EEST) From: Dmitri Vorobiev To: linux-mips@linux-mips.org, ralf@linux-mips.org, rpjday@crashcourse.ca Subject: [PATCH 2/7] [MIPS] Remove unused config variable MIPS_MT_DISABLED Date: Fri, 1 Aug 2008 12:40:16 +0300 Message-Id: <1217583621-4772-3-git-send-email-dmitri.vorobiev@movial.fi> X-Mailer: git-send-email 1.5.6 In-Reply-To: <1217583621-4772-1-git-send-email-dmitri.vorobiev@movial.fi> References: <1217583621-4772-1-git-send-email-dmitri.vorobiev@movial.fi> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20067 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dmitri.vorobiev@movial.fi Precedence: bulk X-list: linux-mips The config variable MIPS_MT_DISABLED is defined but not actually used anywhere. This patch removes the variable. Reported-by: Robert P. J. Day Signed-off-by: Dmitri Vorobiev --- arch/mips/Kconfig | 8 -------- arch/mips/configs/bcm47xx_defconfig | 1 - arch/mips/configs/bigsur_defconfig | 1 - arch/mips/configs/capcella_defconfig | 1 - arch/mips/configs/cobalt_defconfig | 1 - arch/mips/configs/db1000_defconfig | 1 - arch/mips/configs/db1100_defconfig | 1 - arch/mips/configs/db1200_defconfig | 1 - arch/mips/configs/db1500_defconfig | 1 - arch/mips/configs/db1550_defconfig | 1 - arch/mips/configs/decstation_defconfig | 1 - arch/mips/configs/e55_defconfig | 1 - arch/mips/configs/emma2rh_defconfig | 1 - arch/mips/configs/excite_defconfig | 1 - arch/mips/configs/fulong_defconfig | 1 - arch/mips/configs/ip22_defconfig | 1 - arch/mips/configs/ip27_defconfig | 1 - arch/mips/configs/ip28_defconfig | 1 - arch/mips/configs/ip32_defconfig | 1 - arch/mips/configs/jazz_defconfig | 1 - arch/mips/configs/jmr3927_defconfig | 1 - arch/mips/configs/lasat_defconfig | 1 - arch/mips/configs/malta_defconfig | 1 - arch/mips/configs/mipssim_defconfig | 1 - arch/mips/configs/mpc30x_defconfig | 1 - arch/mips/configs/msp71xx_defconfig | 1 - arch/mips/configs/mtx1_defconfig | 1 - arch/mips/configs/pb1100_defconfig | 1 - arch/mips/configs/pb1500_defconfig | 1 - arch/mips/configs/pb1550_defconfig | 1 - arch/mips/configs/pnx8550-jbs_defconfig | 1 - arch/mips/configs/pnx8550-stb810_defconfig | 1 - arch/mips/configs/rb532_defconfig | 1 - arch/mips/configs/rbtx49xx_defconfig | 1 - arch/mips/configs/rm200_defconfig | 1 - arch/mips/configs/sb1250-swarm_defconfig | 1 - arch/mips/configs/tb0219_defconfig | 1 - arch/mips/configs/tb0226_defconfig | 1 - arch/mips/configs/tb0287_defconfig | 1 - arch/mips/configs/workpad_defconfig | 1 - arch/mips/configs/wrppmc_defconfig | 1 - arch/mips/configs/yosemite_defconfig | 1 - 42 files changed, 0 insertions(+), 49 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 8429773..fced035 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -1380,14 +1380,6 @@ config CPU_HAS_PREFETCH choice prompt "MIPS MT options" -config MIPS_MT_DISABLED - bool "Disable multithreading support." - help - Use this option if your workload can't take advantage of - MIPS hardware multithreading support. On systems that don't have - the option of an MT-enabled processor this option will be the only - option in this menu. - config MIPS_MT_SMP bool "Use 1 TC on each available VPE for SMP" depends on SYS_SUPPORTS_MULTITHREADING diff --git a/arch/mips/configs/bcm47xx_defconfig b/arch/mips/configs/bcm47xx_defconfig index d869433..0a81d31 100644 --- a/arch/mips/configs/bcm47xx_defconfig +++ b/arch/mips/configs/bcm47xx_defconfig @@ -108,7 +108,6 @@ CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_16KB is not set # CONFIG_PAGE_SIZE_64KB is not set CONFIG_CPU_HAS_PREFETCH=y -CONFIG_MIPS_MT_DISABLED=y # CONFIG_MIPS_MT_SMP is not set # CONFIG_MIPS_MT_SMTC is not set CONFIG_CPU_HAS_LLSC=y diff --git a/arch/mips/configs/bigsur_defconfig b/arch/mips/configs/bigsur_defconfig index a3bbbf0..9aa8e6e 100644 --- a/arch/mips/configs/bigsur_defconfig +++ b/arch/mips/configs/bigsur_defconfig @@ -126,7 +126,6 @@ CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_16KB is not set # CONFIG_PAGE_SIZE_64KB is not set # CONFIG_SIBYTE_DMA_PAGEOPS is not set -CONFIG_MIPS_MT_DISABLED=y # CONFIG_MIPS_MT_SMP is not set # CONFIG_MIPS_MT_SMTC is not set CONFIG_CPU_HAS_LLSC=y diff --git a/arch/mips/configs/capcella_defconfig b/arch/mips/configs/capcella_defconfig index 185df23..b35dbe2 100644 --- a/arch/mips/configs/capcella_defconfig +++ b/arch/mips/configs/capcella_defconfig @@ -101,7 +101,6 @@ CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_8KB is not set # CONFIG_PAGE_SIZE_16KB is not set # CONFIG_PAGE_SIZE_64KB is not set -CONFIG_MIPS_MT_DISABLED=y # CONFIG_MIPS_MT_SMP is not set # CONFIG_MIPS_MT_SMTC is not set CONFIG_CPU_HAS_SYNC=y diff --git a/arch/mips/configs/cobalt_defconfig b/arch/mips/configs/cobalt_defconfig index 2678b7e..7f1935a 100644 --- a/arch/mips/configs/cobalt_defconfig +++ b/arch/mips/configs/cobalt_defconfig @@ -100,7 +100,6 @@ CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_8KB is not set # CONFIG_PAGE_SIZE_16KB is not set # CONFIG_PAGE_SIZE_64KB is not set -CONFIG_MIPS_MT_DISABLED=y # CONFIG_MIPS_MT_SMP is not set # CONFIG_MIPS_MT_SMTC is not set CONFIG_CPU_HAS_LLSC=y diff --git a/arch/mips/configs/db1000_defconfig b/arch/mips/configs/db1000_defconfig index ebb8ad6..3266d66 100644 --- a/arch/mips/configs/db1000_defconfig +++ b/arch/mips/configs/db1000_defconfig @@ -109,7 +109,6 @@ CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_16KB is not set # CONFIG_PAGE_SIZE_64KB is not set CONFIG_CPU_HAS_PREFETCH=y -CONFIG_MIPS_MT_DISABLED=y # CONFIG_MIPS_MT_SMP is not set # CONFIG_MIPS_MT_SMTC is not set # CONFIG_MIPS_VPE_LOADER is not set diff --git a/arch/mips/configs/db1100_defconfig b/arch/mips/configs/db1100_defconfig index ad4e5ef..995900c 100644 --- a/arch/mips/configs/db1100_defconfig +++ b/arch/mips/configs/db1100_defconfig @@ -109,7 +109,6 @@ CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_16KB is not set # CONFIG_PAGE_SIZE_64KB is not set CONFIG_CPU_HAS_PREFETCH=y -CONFIG_MIPS_MT_DISABLED=y # CONFIG_MIPS_MT_SMP is not set # CONFIG_MIPS_MT_SMTC is not set # CONFIG_MIPS_VPE_LOADER is not set diff --git a/arch/mips/configs/db1200_defconfig b/arch/mips/configs/db1200_defconfig index d0dc2e8..3842902 100644 --- a/arch/mips/configs/db1200_defconfig +++ b/arch/mips/configs/db1200_defconfig @@ -109,7 +109,6 @@ CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_16KB is not set # CONFIG_PAGE_SIZE_64KB is not set CONFIG_CPU_HAS_PREFETCH=y -CONFIG_MIPS_MT_DISABLED=y # CONFIG_MIPS_MT_SMP is not set # CONFIG_MIPS_MT_SMTC is not set # CONFIG_MIPS_VPE_LOADER is not set diff --git a/arch/mips/configs/db1500_defconfig b/arch/mips/configs/db1500_defconfig index 9155082..2c64da0 100644 --- a/arch/mips/configs/db1500_defconfig +++ b/arch/mips/configs/db1500_defconfig @@ -111,7 +111,6 @@ CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_16KB is not set # CONFIG_PAGE_SIZE_64KB is not set CONFIG_CPU_HAS_PREFETCH=y -CONFIG_MIPS_MT_DISABLED=y # CONFIG_MIPS_MT_SMP is not set # CONFIG_MIPS_MT_SMTC is not set # CONFIG_MIPS_VPE_LOADER is not set diff --git a/arch/mips/configs/db1550_defconfig b/arch/mips/configs/db1550_defconfig index e4e3244..becccf7 100644 --- a/arch/mips/configs/db1550_defconfig +++ b/arch/mips/configs/db1550_defconfig @@ -110,7 +110,6 @@ CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_16KB is not set # CONFIG_PAGE_SIZE_64KB is not set CONFIG_CPU_HAS_PREFETCH=y -CONFIG_MIPS_MT_DISABLED=y # CONFIG_MIPS_MT_SMP is not set # CONFIG_MIPS_MT_SMTC is not set # CONFIG_MIPS_VPE_LOADER is not set diff --git a/arch/mips/configs/decstation_defconfig b/arch/mips/configs/decstation_defconfig index 9e65e6a..84b726e 100644 --- a/arch/mips/configs/decstation_defconfig +++ b/arch/mips/configs/decstation_defconfig @@ -107,7 +107,6 @@ CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_8KB is not set # CONFIG_PAGE_SIZE_16KB is not set # CONFIG_PAGE_SIZE_64KB is not set -CONFIG_MIPS_MT_DISABLED=y # CONFIG_MIPS_MT_SMP is not set # CONFIG_MIPS_MT_SMTC is not set # CONFIG_MIPS_VPE_LOADER is not set diff --git a/arch/mips/configs/e55_defconfig b/arch/mips/configs/e55_defconfig index 1bd84d4..1675d6d 100644 --- a/arch/mips/configs/e55_defconfig +++ b/arch/mips/configs/e55_defconfig @@ -100,7 +100,6 @@ CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_8KB is not set # CONFIG_PAGE_SIZE_16KB is not set # CONFIG_PAGE_SIZE_64KB is not set -CONFIG_MIPS_MT_DISABLED=y # CONFIG_MIPS_MT_SMP is not set # CONFIG_MIPS_MT_SMTC is not set CONFIG_CPU_HAS_SYNC=y diff --git a/arch/mips/configs/emma2rh_defconfig b/arch/mips/configs/emma2rh_defconfig index 634bb4e..eaeca09 100644 --- a/arch/mips/configs/emma2rh_defconfig +++ b/arch/mips/configs/emma2rh_defconfig @@ -107,7 +107,6 @@ CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_8KB is not set # CONFIG_PAGE_SIZE_16KB is not set # CONFIG_PAGE_SIZE_64KB is not set -CONFIG_MIPS_MT_DISABLED=y # CONFIG_MIPS_MT_SMP is not set # CONFIG_MIPS_MT_SMTC is not set # CONFIG_MIPS_VPE_LOADER is not set diff --git a/arch/mips/configs/excite_defconfig b/arch/mips/configs/excite_defconfig index 3572e80..b79d1b8 100644 --- a/arch/mips/configs/excite_defconfig +++ b/arch/mips/configs/excite_defconfig @@ -113,7 +113,6 @@ CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_16KB is not set # CONFIG_PAGE_SIZE_64KB is not set CONFIG_CPU_HAS_PREFETCH=y -CONFIG_MIPS_MT_DISABLED=y # CONFIG_MIPS_MT_SMP is not set # CONFIG_MIPS_MT_SMTC is not set # CONFIG_MIPS_VPE_LOADER is not set diff --git a/arch/mips/configs/fulong_defconfig b/arch/mips/configs/fulong_defconfig index 6209800..fc5d5d4 100644 --- a/arch/mips/configs/fulong_defconfig +++ b/arch/mips/configs/fulong_defconfig @@ -98,7 +98,6 @@ CONFIG_64BIT=y CONFIG_PAGE_SIZE_16KB=y # CONFIG_PAGE_SIZE_64KB is not set CONFIG_BOARD_SCACHE=y -CONFIG_MIPS_MT_DISABLED=y # CONFIG_MIPS_MT_SMP is not set # CONFIG_MIPS_MT_SMTC is not set # CONFIG_MIPS_VPE_LOADER is not set diff --git a/arch/mips/configs/ip22_defconfig b/arch/mips/configs/ip22_defconfig index cc8e6bf..c91f7ef 100644 --- a/arch/mips/configs/ip22_defconfig +++ b/arch/mips/configs/ip22_defconfig @@ -107,7 +107,6 @@ CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_64KB is not set CONFIG_BOARD_SCACHE=y CONFIG_IP22_CPU_SCACHE=y -CONFIG_MIPS_MT_DISABLED=y # CONFIG_MIPS_MT_SMP is not set # CONFIG_MIPS_MT_SMTC is not set CONFIG_CPU_HAS_LLSC=y diff --git a/arch/mips/configs/ip27_defconfig b/arch/mips/configs/ip27_defconfig index bed6016..e51d388 100644 --- a/arch/mips/configs/ip27_defconfig +++ b/arch/mips/configs/ip27_defconfig @@ -102,7 +102,6 @@ CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_16KB is not set # CONFIG_PAGE_SIZE_64KB is not set CONFIG_CPU_HAS_PREFETCH=y -CONFIG_MIPS_MT_DISABLED=y # CONFIG_MIPS_MT_SMP is not set # CONFIG_MIPS_MT_SMTC is not set CONFIG_CPU_HAS_LLSC=y diff --git a/arch/mips/configs/ip28_defconfig b/arch/mips/configs/ip28_defconfig index 3540707..7f86d72 100644 --- a/arch/mips/configs/ip28_defconfig +++ b/arch/mips/configs/ip28_defconfig @@ -121,7 +121,6 @@ CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_16KB is not set # CONFIG_PAGE_SIZE_64KB is not set CONFIG_CPU_HAS_PREFETCH=y -CONFIG_MIPS_MT_DISABLED=y # CONFIG_MIPS_MT_SMP is not set # CONFIG_MIPS_MT_SMTC is not set CONFIG_CPU_HAS_LLSC=y diff --git a/arch/mips/configs/ip32_defconfig b/arch/mips/configs/ip32_defconfig index fe4699d..3794abd 100644 --- a/arch/mips/configs/ip32_defconfig +++ b/arch/mips/configs/ip32_defconfig @@ -113,7 +113,6 @@ CONFIG_PAGE_SIZE_4KB=y CONFIG_BOARD_SCACHE=y CONFIG_R5000_CPU_SCACHE=y CONFIG_RM7000_CPU_SCACHE=y -CONFIG_MIPS_MT_DISABLED=y # CONFIG_MIPS_MT_SMP is not set # CONFIG_MIPS_MT_SMTC is not set # CONFIG_MIPS_VPE_LOADER is not set diff --git a/arch/mips/configs/jazz_defconfig b/arch/mips/configs/jazz_defconfig index bbacc35..181462d 100644 --- a/arch/mips/configs/jazz_defconfig +++ b/arch/mips/configs/jazz_defconfig @@ -114,7 +114,6 @@ CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_8KB is not set # CONFIG_PAGE_SIZE_16KB is not set # CONFIG_PAGE_SIZE_64KB is not set -CONFIG_MIPS_MT_DISABLED=y # CONFIG_MIPS_MT_SMP is not set # CONFIG_MIPS_MT_SMTC is not set # CONFIG_MIPS_VPE_LOADER is not set diff --git a/arch/mips/configs/jmr3927_defconfig b/arch/mips/configs/jmr3927_defconfig index 9d5bd2a..f7e3527 100644 --- a/arch/mips/configs/jmr3927_defconfig +++ b/arch/mips/configs/jmr3927_defconfig @@ -107,7 +107,6 @@ CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_8KB is not set # CONFIG_PAGE_SIZE_16KB is not set # CONFIG_PAGE_SIZE_64KB is not set -CONFIG_MIPS_MT_DISABLED=y # CONFIG_MIPS_MT_SMP is not set # CONFIG_MIPS_MT_SMTC is not set CONFIG_CPU_HAS_SYNC=y diff --git a/arch/mips/configs/lasat_defconfig b/arch/mips/configs/lasat_defconfig index bc9159f..0db2dcf 100644 --- a/arch/mips/configs/lasat_defconfig +++ b/arch/mips/configs/lasat_defconfig @@ -105,7 +105,6 @@ CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_64KB is not set CONFIG_BOARD_SCACHE=y CONFIG_R5000_CPU_SCACHE=y -CONFIG_MIPS_MT_DISABLED=y # CONFIG_MIPS_MT_SMP is not set # CONFIG_MIPS_MT_SMTC is not set CONFIG_CPU_HAS_LLSC=y diff --git a/arch/mips/configs/malta_defconfig b/arch/mips/configs/malta_defconfig index 74daa0c..dee1ceb 100644 --- a/arch/mips/configs/malta_defconfig +++ b/arch/mips/configs/malta_defconfig @@ -121,7 +121,6 @@ CONFIG_PAGE_SIZE_4KB=y CONFIG_BOARD_SCACHE=y CONFIG_MIPS_CPU_SCACHE=y CONFIG_CPU_HAS_PREFETCH=y -# CONFIG_MIPS_MT_DISABLED is not set CONFIG_MIPS_MT_SMP=y # CONFIG_MIPS_MT_SMTC is not set CONFIG_MIPS_MT=y diff --git a/arch/mips/configs/mipssim_defconfig b/arch/mips/configs/mipssim_defconfig index 2c0a631..424a874 100644 --- a/arch/mips/configs/mipssim_defconfig +++ b/arch/mips/configs/mipssim_defconfig @@ -110,7 +110,6 @@ CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_16KB is not set # CONFIG_PAGE_SIZE_64KB is not set CONFIG_CPU_HAS_PREFETCH=y -CONFIG_MIPS_MT_DISABLED=y # CONFIG_MIPS_MT_SMP is not set # CONFIG_MIPS_MT_SMTC is not set CONFIG_SYS_SUPPORTS_MULTITHREADING=y diff --git a/arch/mips/configs/mpc30x_defconfig b/arch/mips/configs/mpc30x_defconfig index 8c720e5..57f5689 100644 --- a/arch/mips/configs/mpc30x_defconfig +++ b/arch/mips/configs/mpc30x_defconfig @@ -101,7 +101,6 @@ CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_8KB is not set # CONFIG_PAGE_SIZE_16KB is not set # CONFIG_PAGE_SIZE_64KB is not set -CONFIG_MIPS_MT_DISABLED=y # CONFIG_MIPS_MT_SMP is not set # CONFIG_MIPS_MT_SMTC is not set CONFIG_CPU_HAS_SYNC=y diff --git a/arch/mips/configs/msp71xx_defconfig b/arch/mips/configs/msp71xx_defconfig index 59d1947..03dde5f 100644 --- a/arch/mips/configs/msp71xx_defconfig +++ b/arch/mips/configs/msp71xx_defconfig @@ -123,7 +123,6 @@ CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_16KB is not set # CONFIG_PAGE_SIZE_64KB is not set CONFIG_CPU_HAS_PREFETCH=y -CONFIG_MIPS_MT_DISABLED=y # CONFIG_MIPS_MT_SMP is not set # CONFIG_MIPS_MT_SMTC is not set # CONFIG_MIPS_VPE_LOADER is not set diff --git a/arch/mips/configs/mtx1_defconfig b/arch/mips/configs/mtx1_defconfig index bacf0dd..07ae765 100644 --- a/arch/mips/configs/mtx1_defconfig +++ b/arch/mips/configs/mtx1_defconfig @@ -112,7 +112,6 @@ CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_16KB is not set # CONFIG_PAGE_SIZE_64KB is not set CONFIG_CPU_HAS_PREFETCH=y -CONFIG_MIPS_MT_DISABLED=y # CONFIG_MIPS_MT_SMP is not set # CONFIG_MIPS_MT_SMTC is not set CONFIG_64BIT_PHYS_ADDR=y diff --git a/arch/mips/configs/pb1100_defconfig b/arch/mips/configs/pb1100_defconfig index 6dfe6f7..fda4b41 100644 --- a/arch/mips/configs/pb1100_defconfig +++ b/arch/mips/configs/pb1100_defconfig @@ -110,7 +110,6 @@ CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_16KB is not set # CONFIG_PAGE_SIZE_64KB is not set CONFIG_CPU_HAS_PREFETCH=y -CONFIG_MIPS_MT_DISABLED=y # CONFIG_MIPS_MT_SMP is not set # CONFIG_MIPS_MT_SMTC is not set # CONFIG_MIPS_VPE_LOADER is not set diff --git a/arch/mips/configs/pb1500_defconfig b/arch/mips/configs/pb1500_defconfig index c965a87..4096e47 100644 --- a/arch/mips/configs/pb1500_defconfig +++ b/arch/mips/configs/pb1500_defconfig @@ -109,7 +109,6 @@ CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_16KB is not set # CONFIG_PAGE_SIZE_64KB is not set CONFIG_CPU_HAS_PREFETCH=y -CONFIG_MIPS_MT_DISABLED=y # CONFIG_MIPS_MT_SMP is not set # CONFIG_MIPS_MT_SMTC is not set # CONFIG_MIPS_VPE_LOADER is not set diff --git a/arch/mips/configs/pb1550_defconfig b/arch/mips/configs/pb1550_defconfig index 0778996..06ed223 100644 --- a/arch/mips/configs/pb1550_defconfig +++ b/arch/mips/configs/pb1550_defconfig @@ -110,7 +110,6 @@ CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_16KB is not set # CONFIG_PAGE_SIZE_64KB is not set CONFIG_CPU_HAS_PREFETCH=y -CONFIG_MIPS_MT_DISABLED=y # CONFIG_MIPS_MT_SMP is not set # CONFIG_MIPS_MT_SMTC is not set # CONFIG_MIPS_VPE_LOADER is not set diff --git a/arch/mips/configs/pnx8550-jbs_defconfig b/arch/mips/configs/pnx8550-jbs_defconfig index 37c7b5f..571806f 100644 --- a/arch/mips/configs/pnx8550-jbs_defconfig +++ b/arch/mips/configs/pnx8550-jbs_defconfig @@ -107,7 +107,6 @@ CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_16KB is not set # CONFIG_PAGE_SIZE_64KB is not set CONFIG_CPU_HAS_PREFETCH=y -CONFIG_MIPS_MT_DISABLED=y # CONFIG_MIPS_MT_SMP is not set # CONFIG_MIPS_MT_SMTC is not set # CONFIG_MIPS_VPE_LOADER is not set diff --git a/arch/mips/configs/pnx8550-stb810_defconfig b/arch/mips/configs/pnx8550-stb810_defconfig index 893e5c4..fa7af42 100644 --- a/arch/mips/configs/pnx8550-stb810_defconfig +++ b/arch/mips/configs/pnx8550-stb810_defconfig @@ -107,7 +107,6 @@ CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_16KB is not set # CONFIG_PAGE_SIZE_64KB is not set CONFIG_CPU_HAS_PREFETCH=y -CONFIG_MIPS_MT_DISABLED=y # CONFIG_MIPS_MT_SMP is not set # CONFIG_MIPS_MT_SMTC is not set # CONFIG_MIPS_VPE_LOADER is not set diff --git a/arch/mips/configs/rb532_defconfig b/arch/mips/configs/rb532_defconfig index f28dc32..75eee9a 100644 --- a/arch/mips/configs/rb532_defconfig +++ b/arch/mips/configs/rb532_defconfig @@ -110,7 +110,6 @@ CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_16KB is not set # CONFIG_PAGE_SIZE_64KB is not set CONFIG_CPU_HAS_PREFETCH=y -CONFIG_MIPS_MT_DISABLED=y # CONFIG_MIPS_MT_SMP is not set # CONFIG_MIPS_MT_SMTC is not set CONFIG_CPU_HAS_LLSC=y diff --git a/arch/mips/configs/rbtx49xx_defconfig b/arch/mips/configs/rbtx49xx_defconfig index e42aed5..c9633d7 100644 --- a/arch/mips/configs/rbtx49xx_defconfig +++ b/arch/mips/configs/rbtx49xx_defconfig @@ -123,7 +123,6 @@ CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_16KB is not set # CONFIG_PAGE_SIZE_64KB is not set CONFIG_CPU_HAS_PREFETCH=y -CONFIG_MIPS_MT_DISABLED=y # CONFIG_MIPS_MT_SMP is not set # CONFIG_MIPS_MT_SMTC is not set CONFIG_CPU_HAS_LLSC=y diff --git a/arch/mips/configs/rm200_defconfig b/arch/mips/configs/rm200_defconfig index 0f4da03..00ee239 100644 --- a/arch/mips/configs/rm200_defconfig +++ b/arch/mips/configs/rm200_defconfig @@ -119,7 +119,6 @@ CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_64KB is not set CONFIG_BOARD_SCACHE=y CONFIG_R5000_CPU_SCACHE=y -CONFIG_MIPS_MT_DISABLED=y # CONFIG_MIPS_MT_SMP is not set # CONFIG_MIPS_MT_SMTC is not set # CONFIG_MIPS_VPE_LOADER is not set diff --git a/arch/mips/configs/sb1250-swarm_defconfig b/arch/mips/configs/sb1250-swarm_defconfig index 1ea9786..72cef77 100644 --- a/arch/mips/configs/sb1250-swarm_defconfig +++ b/arch/mips/configs/sb1250-swarm_defconfig @@ -129,7 +129,6 @@ CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_64KB is not set # CONFIG_SIBYTE_DMA_PAGEOPS is not set CONFIG_CPU_HAS_PREFETCH=y -CONFIG_MIPS_MT_DISABLED=y # CONFIG_MIPS_MT_SMP is not set # CONFIG_MIPS_MT_SMTC is not set CONFIG_SB1_PASS_2_WORKAROUNDS=y diff --git a/arch/mips/configs/tb0219_defconfig b/arch/mips/configs/tb0219_defconfig index b505988..ebc3662 100644 --- a/arch/mips/configs/tb0219_defconfig +++ b/arch/mips/configs/tb0219_defconfig @@ -112,7 +112,6 @@ CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_8KB is not set # CONFIG_PAGE_SIZE_16KB is not set # CONFIG_PAGE_SIZE_64KB is not set -CONFIG_MIPS_MT_DISABLED=y # CONFIG_MIPS_MT_SMP is not set # CONFIG_MIPS_MT_SMTC is not set CONFIG_CPU_HAS_SYNC=y diff --git a/arch/mips/configs/tb0226_defconfig b/arch/mips/configs/tb0226_defconfig index b06a716..b8f6ce3 100644 --- a/arch/mips/configs/tb0226_defconfig +++ b/arch/mips/configs/tb0226_defconfig @@ -112,7 +112,6 @@ CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_8KB is not set # CONFIG_PAGE_SIZE_16KB is not set # CONFIG_PAGE_SIZE_64KB is not set -CONFIG_MIPS_MT_DISABLED=y # CONFIG_MIPS_MT_SMP is not set # CONFIG_MIPS_MT_SMTC is not set CONFIG_CPU_HAS_SYNC=y diff --git a/arch/mips/configs/tb0287_defconfig b/arch/mips/configs/tb0287_defconfig index 46512cf..b3dc2c8 100644 --- a/arch/mips/configs/tb0287_defconfig +++ b/arch/mips/configs/tb0287_defconfig @@ -112,7 +112,6 @@ CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_8KB is not set # CONFIG_PAGE_SIZE_16KB is not set # CONFIG_PAGE_SIZE_64KB is not set -CONFIG_MIPS_MT_DISABLED=y # CONFIG_MIPS_MT_SMP is not set # CONFIG_MIPS_MT_SMTC is not set CONFIG_CPU_HAS_SYNC=y diff --git a/arch/mips/configs/workpad_defconfig b/arch/mips/configs/workpad_defconfig index b437eb7..6d79a28 100644 --- a/arch/mips/configs/workpad_defconfig +++ b/arch/mips/configs/workpad_defconfig @@ -100,7 +100,6 @@ CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_8KB is not set # CONFIG_PAGE_SIZE_16KB is not set # CONFIG_PAGE_SIZE_64KB is not set -CONFIG_MIPS_MT_DISABLED=y # CONFIG_MIPS_MT_SMP is not set # CONFIG_MIPS_MT_SMTC is not set CONFIG_CPU_HAS_SYNC=y diff --git a/arch/mips/configs/wrppmc_defconfig b/arch/mips/configs/wrppmc_defconfig index fc2c567..284aa61 100644 --- a/arch/mips/configs/wrppmc_defconfig +++ b/arch/mips/configs/wrppmc_defconfig @@ -115,7 +115,6 @@ CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_16KB is not set # CONFIG_PAGE_SIZE_64KB is not set CONFIG_CPU_HAS_PREFETCH=y -CONFIG_MIPS_MT_DISABLED=y # CONFIG_MIPS_MT_SMP is not set # CONFIG_MIPS_MT_SMTC is not set # CONFIG_MIPS_VPE_LOADER is not set diff --git a/arch/mips/configs/yosemite_defconfig b/arch/mips/configs/yosemite_defconfig index 7f86c43..356e097 100644 --- a/arch/mips/configs/yosemite_defconfig +++ b/arch/mips/configs/yosemite_defconfig @@ -110,7 +110,6 @@ CONFIG_PAGE_SIZE_4KB=y # CONFIG_PAGE_SIZE_16KB is not set # CONFIG_PAGE_SIZE_64KB is not set CONFIG_CPU_HAS_PREFETCH=y -CONFIG_MIPS_MT_DISABLED=y # CONFIG_MIPS_MT_SMP is not set # CONFIG_MIPS_MT_SMTC is not set # CONFIG_MIPS_VPE_LOADER is not set -- 1.5.6 From dvorobye@movial.fi Fri Aug 1 10:43:46 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 01 Aug 2008 10:43:53 +0100 (BST) Received: from smtp.movial.fi ([62.236.91.34]:61394 "EHLO smtp.movial.fi") by ftp.linux-mips.org with ESMTP id S28574358AbYHAJkg (ORCPT ); Fri, 1 Aug 2008 10:40:36 +0100 Received: from localhost (mailscanner.hel.movial.fi [172.17.81.9]) by smtp.movial.fi (Postfix) with ESMTP id 92F6CC806C; Fri, 1 Aug 2008 12:40:22 +0300 (EEST) X-Virus-Scanned: Debian amavisd-new at movial.fi Received: from smtp.movial.fi ([62.236.91.34]) by localhost (mailscanner.hel.movial.fi [172.17.81.9]) (amavisd-new, port 10026) with ESMTP id W5pcntaJDvBy; Fri, 1 Aug 2008 12:40:22 +0300 (EEST) Received: from sd048.hel.movial.fi (sd048.hel.movial.fi [172.17.49.48]) (using TLSv1 with cipher ADH-AES256-SHA (256/256 bits)) (No client certificate requested) by smtp.movial.fi (Postfix) with ESMTP id 176E3C8092; Fri, 1 Aug 2008 12:40:22 +0300 (EEST) Received: by sd048.hel.movial.fi (Postfix, from userid 30120) id D3CF2108072; Fri, 1 Aug 2008 12:40:21 +0300 (EEST) From: Dmitri Vorobiev To: linux-mips@linux-mips.org, ralf@linux-mips.org, rpjday@crashcourse.ca Subject: [PATCH 6/7] [MIPS] Remove dead code from arch/mips/pmc-sierra/yosemite/irq.c Date: Fri, 1 Aug 2008 12:40:20 +0300 Message-Id: <1217583621-4772-7-git-send-email-dmitri.vorobiev@movial.fi> X-Mailer: git-send-email 1.5.6 In-Reply-To: <1217583621-4772-1-git-send-email-dmitri.vorobiev@movial.fi> References: <1217583621-4772-1-git-send-email-dmitri.vorobiev@movial.fi> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20068 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dmitri.vorobiev@movial.fi Precedence: bulk X-list: linux-mips The code under the following conditional compilation construct #ifdef CONFIG_HT_LEVEL_TRIGGER #endif appeared during early 2.5.x times, but it seems that the relevant enabling config option has never existed. Therefore, it looks like the code under HT_LEVEL_TRIGGER did not have a single chance to be ever compiled. This patch removes the dead lines. Build-tested using the yosemite_defconfig. Reported-by: Robert P. J. Day Signed-off-by: Dmitri Vorobiev --- arch/mips/pmc-sierra/yosemite/irq.c | 31 ------------------------------- 1 files changed, 0 insertions(+), 31 deletions(-) diff --git a/arch/mips/pmc-sierra/yosemite/irq.c b/arch/mips/pmc-sierra/yosemite/irq.c index 4decc28..222948b 100644 --- a/arch/mips/pmc-sierra/yosemite/irq.c +++ b/arch/mips/pmc-sierra/yosemite/irq.c @@ -77,37 +77,6 @@ static void ll_ht_smp_irq_handler(int irq) if (status != 0) OCD_WRITE(RM9000x2_OCD_INTP1STATUS4, IRQ_ACK_BITS); -#ifdef CONFIG_HT_LEVEL_TRIGGER - /* - * Level Trigger Mode only. Send the HT EOI message back to the source. - */ - switch (status) { - case 0x1000000: - OCD_WRITE(RM9000x2_OCD_HTEOI, HYPERTRANSPORT_INTA); - break; - case 0x2000000: - OCD_WRITE(RM9000x2_OCD_HTEOI, HYPERTRANSPORT_INTB); - break; - case 0x4000000: - OCD_WRITE(RM9000x2_OCD_HTEOI, HYPERTRANSPORT_INTC); - break; - case 0x8000000: - OCD_WRITE(RM9000x2_OCD_HTEOI, HYPERTRANSPORT_INTD); - break; - case 0x0000001: - /* PLX */ - OCD_WRITE(RM9000x2_OCD_HTEOI, 0x20); - OCD_WRITE(IRQ_CLEAR_REG, IRQ_ACK_BITS); - break; - case 0xf000000: - OCD_WRITE(RM9000x2_OCD_HTEOI, HYPERTRANSPORT_INTA); - OCD_WRITE(RM9000x2_OCD_HTEOI, HYPERTRANSPORT_INTB); - OCD_WRITE(RM9000x2_OCD_HTEOI, HYPERTRANSPORT_INTC); - OCD_WRITE(RM9000x2_OCD_HTEOI, HYPERTRANSPORT_INTD); - break; - } -#endif /* CONFIG_HT_LEVEL_TRIGGER */ - do_IRQ(irq); } #endif -- 1.5.6 From dvorobye@movial.fi Fri Aug 1 10:44:10 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 01 Aug 2008 10:44:17 +0100 (BST) Received: from smtp.movial.fi ([62.236.91.34]:61650 "EHLO smtp.movial.fi") by ftp.linux-mips.org with ESMTP id S28574356AbYHAJkg (ORCPT ); Fri, 1 Aug 2008 10:40:36 +0100 Received: from localhost (mailscanner.hel.movial.fi [172.17.81.9]) by smtp.movial.fi (Postfix) with ESMTP id B792CC8092; Fri, 1 Aug 2008 12:40:22 +0300 (EEST) X-Virus-Scanned: Debian amavisd-new at movial.fi Received: from smtp.movial.fi ([62.236.91.34]) by localhost (mailscanner.hel.movial.fi [172.17.81.9]) (amavisd-new, port 10026) with ESMTP id tZMOxOEub0Tb; Fri, 1 Aug 2008 12:40:22 +0300 (EEST) Received: from sd048.hel.movial.fi (sd048.hel.movial.fi [172.17.49.48]) (using TLSv1 with cipher ADH-AES256-SHA (256/256 bits)) (No client certificate requested) by smtp.movial.fi (Postfix) with ESMTP id 144D6C808B; Fri, 1 Aug 2008 12:40:22 +0300 (EEST) Received: by sd048.hel.movial.fi (Postfix, from userid 30120) id D8DF8108073; Fri, 1 Aug 2008 12:40:21 +0300 (EEST) From: Dmitri Vorobiev To: linux-mips@linux-mips.org, ralf@linux-mips.org, rpjday@crashcourse.ca Subject: [PATCH 7/7] [MIPS] Remove unused config variable MIPS_DISABLE_OBSOLETE_IDE Date: Fri, 1 Aug 2008 12:40:21 +0300 Message-Id: <1217583621-4772-8-git-send-email-dmitri.vorobiev@movial.fi> X-Mailer: git-send-email 1.5.6 In-Reply-To: <1217583621-4772-1-git-send-email-dmitri.vorobiev@movial.fi> References: <1217583621-4772-1-git-send-email-dmitri.vorobiev@movial.fi> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20069 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dmitri.vorobiev@movial.fi Precedence: bulk X-list: linux-mips The config variable MIPS_DISABLE_OBSOLETE_IDE is never used in the kernel code. Let's remove the superfluous variable. Reported-by: Robert P. J. Day Signed-off-by: Dmitri Vorobiev --- arch/mips/Kconfig | 3 --- arch/mips/au1000/Kconfig | 5 ----- arch/mips/configs/db1200_defconfig | 1 - arch/mips/configs/db1500_defconfig | 1 - arch/mips/configs/db1550_defconfig | 1 - arch/mips/configs/pb1550_defconfig | 1 - 6 files changed, 0 insertions(+), 12 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index a49863c..4b20f2e 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -760,9 +760,6 @@ config MIPS_MSC config MIPS_NILE4 bool -config MIPS_DISABLE_OBSOLETE_IDE - bool - config SYNC_R4K bool diff --git a/arch/mips/au1000/Kconfig b/arch/mips/au1000/Kconfig index 1fe97cc..9ad89cc 100644 --- a/arch/mips/au1000/Kconfig +++ b/arch/mips/au1000/Kconfig @@ -33,7 +33,6 @@ config MIPS_DB1200 bool "Alchemy DB1200 board" select SOC_AU1200 select DMA_COHERENT - select MIPS_DISABLE_OBSOLETE_IDE select SYS_SUPPORTS_LITTLE_ENDIAN config MIPS_DB1500 @@ -41,7 +40,6 @@ config MIPS_DB1500 select SOC_AU1500 select DMA_NONCOHERENT select HW_HAS_PCI - select MIPS_DISABLE_OBSOLETE_IDE select SYS_SUPPORTS_BIG_ENDIAN select SYS_SUPPORTS_LITTLE_ENDIAN @@ -50,7 +48,6 @@ config MIPS_DB1550 select SOC_AU1550 select HW_HAS_PCI select DMA_NONCOHERENT - select MIPS_DISABLE_OBSOLETE_IDE select SYS_SUPPORTS_LITTLE_ENDIAN config MIPS_MIRAGE @@ -79,7 +76,6 @@ config MIPS_PB1200 bool "Alchemy PB1200 board" select SOC_AU1200 select DMA_NONCOHERENT - select MIPS_DISABLE_OBSOLETE_IDE select SYS_SUPPORTS_LITTLE_ENDIAN config MIPS_PB1500 @@ -94,7 +90,6 @@ config MIPS_PB1550 select SOC_AU1550 select DMA_NONCOHERENT select HW_HAS_PCI - select MIPS_DISABLE_OBSOLETE_IDE select SYS_SUPPORTS_LITTLE_ENDIAN config MIPS_XXS1500 diff --git a/arch/mips/configs/db1200_defconfig b/arch/mips/configs/db1200_defconfig index 3842902..dd784cd 100644 --- a/arch/mips/configs/db1200_defconfig +++ b/arch/mips/configs/db1200_defconfig @@ -62,7 +62,6 @@ CONFIG_GENERIC_TIME=y CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y # CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ is not set CONFIG_DMA_COHERENT=y -CONFIG_MIPS_DISABLE_OBSOLETE_IDE=y # CONFIG_CPU_BIG_ENDIAN is not set CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_SYS_SUPPORTS_APM_EMULATION=y diff --git a/arch/mips/configs/db1500_defconfig b/arch/mips/configs/db1500_defconfig index 2c64da0..5514692 100644 --- a/arch/mips/configs/db1500_defconfig +++ b/arch/mips/configs/db1500_defconfig @@ -63,7 +63,6 @@ CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y # CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ is not set CONFIG_DMA_NONCOHERENT=y CONFIG_DMA_NEED_PCI_MAP_STATE=y -CONFIG_MIPS_DISABLE_OBSOLETE_IDE=y # CONFIG_CPU_BIG_ENDIAN is not set CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_SYS_SUPPORTS_APM_EMULATION=y diff --git a/arch/mips/configs/db1550_defconfig b/arch/mips/configs/db1550_defconfig index becccf7..628314c 100644 --- a/arch/mips/configs/db1550_defconfig +++ b/arch/mips/configs/db1550_defconfig @@ -63,7 +63,6 @@ CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y # CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ is not set CONFIG_DMA_NONCOHERENT=y CONFIG_DMA_NEED_PCI_MAP_STATE=y -CONFIG_MIPS_DISABLE_OBSOLETE_IDE=y # CONFIG_CPU_BIG_ENDIAN is not set CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_SYS_SUPPORTS_APM_EMULATION=y diff --git a/arch/mips/configs/pb1550_defconfig b/arch/mips/configs/pb1550_defconfig index 06ed223..d02dc2f 100644 --- a/arch/mips/configs/pb1550_defconfig +++ b/arch/mips/configs/pb1550_defconfig @@ -63,7 +63,6 @@ CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y # CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ is not set CONFIG_DMA_NONCOHERENT=y CONFIG_DMA_NEED_PCI_MAP_STATE=y -CONFIG_MIPS_DISABLE_OBSOLETE_IDE=y # CONFIG_CPU_BIG_ENDIAN is not set CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_SYS_SUPPORTS_APM_EMULATION=y -- 1.5.6 From dvorobye@movial.fi Fri Aug 1 10:44:34 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 01 Aug 2008 10:44:42 +0100 (BST) Received: from smtp.movial.fi ([62.236.91.34]:58066 "EHLO smtp.movial.fi") by ftp.linux-mips.org with ESMTP id S28574332AbYHAJk3 (ORCPT ); Fri, 1 Aug 2008 10:40:29 +0100 Received: from localhost (mailscanner.hel.movial.fi [172.17.81.9]) by smtp.movial.fi (Postfix) with ESMTP id 4F1C2C8016; Fri, 1 Aug 2008 12:40:22 +0300 (EEST) X-Virus-Scanned: Debian amavisd-new at movial.fi Received: from smtp.movial.fi ([62.236.91.34]) by localhost (mailscanner.hel.movial.fi [172.17.81.9]) (amavisd-new, port 10026) with ESMTP id FVUiEkeYXZ1n; Fri, 1 Aug 2008 12:40:22 +0300 (EEST) Received: from sd048.hel.movial.fi (sd048.hel.movial.fi [172.17.49.48]) (using TLSv1 with cipher ADH-AES256-SHA (256/256 bits)) (No client certificate requested) by smtp.movial.fi (Postfix) with ESMTP id 0FE37C806D; Fri, 1 Aug 2008 12:40:22 +0300 (EEST) Received: by sd048.hel.movial.fi (Postfix, from userid 30120) id CA9D9108070; Fri, 1 Aug 2008 12:40:21 +0300 (EEST) From: Dmitri Vorobiev To: linux-mips@linux-mips.org, ralf@linux-mips.org, rpjday@crashcourse.ca Subject: [PATCH 4/7] [MIPS] Remove unused config variable MIPS_BOARDS_GEN Date: Fri, 1 Aug 2008 12:40:18 +0300 Message-Id: <1217583621-4772-5-git-send-email-dmitri.vorobiev@movial.fi> X-Mailer: git-send-email 1.5.6 In-Reply-To: <1217583621-4772-1-git-send-email-dmitri.vorobiev@movial.fi> References: <1217583621-4772-1-git-send-email-dmitri.vorobiev@movial.fi> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20070 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dmitri.vorobiev@movial.fi Precedence: bulk X-list: linux-mips The config variable MIPS_BOARDS_GEN is defined but never used, and this patch removes the forgotten variable. Reported-by: Robert P. J. Day Signed-off-by: Dmitri Vorobiev --- arch/mips/Kconfig | 4 ---- 1 files changed, 0 insertions(+), 4 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index f5e8720..a49863c 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -195,7 +195,6 @@ config MIPS_MALTA select HW_HAS_PCI select I8253 select I8259 - select MIPS_BOARDS_GEN select MIPS_BONITO64 select MIPS_CPU_SCACHE select PCI_GT64XXX_PCI0 @@ -839,9 +838,6 @@ config IRQ_GT641XX config IRQ_GIC bool -config MIPS_BOARDS_GEN - bool - config PCI_GT64XXX_PCI0 bool -- 1.5.6 From dvorobye@movial.fi Fri Aug 1 10:44:59 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 01 Aug 2008 10:45:01 +0100 (BST) Received: from smtp.movial.fi ([62.236.91.34]:57042 "EHLO smtp.movial.fi") by ftp.linux-mips.org with ESMTP id S28574329AbYHAJk3 (ORCPT ); Fri, 1 Aug 2008 10:40:29 +0100 Received: from localhost (mailscanner.hel.movial.fi [172.17.81.9]) by smtp.movial.fi (Postfix) with ESMTP id 18F03C80C8; Fri, 1 Aug 2008 12:40:22 +0300 (EEST) X-Virus-Scanned: Debian amavisd-new at movial.fi Received: from smtp.movial.fi ([62.236.91.34]) by localhost (mailscanner.hel.movial.fi [172.17.81.9]) (amavisd-new, port 10026) with ESMTP id rTJnsSLGTIk2; Fri, 1 Aug 2008 12:40:21 +0300 (EEST) Received: from sd048.hel.movial.fi (sd048.hel.movial.fi [172.17.49.48]) (using TLSv1 with cipher ADH-AES256-SHA (256/256 bits)) (No client certificate requested) by smtp.movial.fi (Postfix) with ESMTP id E256DC8011; Fri, 1 Aug 2008 12:40:21 +0300 (EEST) Received: by sd048.hel.movial.fi (Postfix, from userid 30120) id B36F210806C; Fri, 1 Aug 2008 12:40:21 +0300 (EEST) From: Dmitri Vorobiev To: linux-mips@linux-mips.org, ralf@linux-mips.org, rpjday@crashcourse.ca Subject: [PATCH 0/7] [MIPS] Configuration namespace cleanups, dead code elimination Date: Fri, 1 Aug 2008 12:40:14 +0300 Message-Id: <1217583621-4772-1-git-send-email-dmitri.vorobiev@movial.fi> X-Mailer: git-send-email 1.5.6 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20071 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dmitri.vorobiev@movial.fi Precedence: bulk X-list: linux-mips Hi Ralf, A small round of house cleaning once again, this time inspired by Robert P. J. Day's reports. Please consider. Thanks, Dmitri Vorobiev From glynastill@yahoo.co.uk Fri Aug 1 11:49:31 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 01 Aug 2008 11:49:40 +0100 (BST) Received: from web25806.mail.ukl.yahoo.com ([217.12.10.191]:58297 "HELO web25806.mail.ukl.yahoo.com") by ftp.linux-mips.org with SMTP id S20026712AbYHAKtb convert rfc822-to-8bit (ORCPT ); Fri, 1 Aug 2008 11:49:31 +0100 Received: (qmail 16644 invoked by uid 60001); 1 Aug 2008 10:49:25 -0000 DomainKey-Signature: a=rsa-sha1; q=dns; c=nofws; s=s1024; d=yahoo.co.uk; h=Received:X-Mailer:Date:From:Reply-To:Subject:To:Cc:In-Reply-To:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-ID; b=LvYPZ9vNkBOyHeSDmeqxcBH96Jo7Y79Bo/0p6Jpg5ovR3BrO+RSetC7O1+4dLadv7hFgqV5VO0QXqckM8pQRhFscmo13iyufIJqrGQx2EWvKGkdXbZzD81SHHHGL4GH9tDyNQnJGaQXbMmsAByqeiPUleHtzTlWFXQ2cvDjCadU=; Received: from [83.166.184.142] by web25806.mail.ukl.yahoo.com via HTTP; Fri, 01 Aug 2008 10:49:25 GMT X-Mailer: YahooMailWebService/0.7.218 Date: Fri, 1 Aug 2008 10:49:25 +0000 (GMT) From: Glyn Astill Reply-To: glynastill@yahoo.co.uk Subject: Re: Debian etch on cobalt To: Martin Michlmayr Cc: linux-mips@linux-mips.org In-Reply-To: <20080725234605.GE2512@deprecation.cyrius.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8BIT Message-ID: <197761.16530.qm@web25806.mail.ukl.yahoo.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20072 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: glynastill@yahoo.co.uk Precedence: bulk X-list: linux-mips Hi Chaps, Just a little update on my progress with this, I would post to the debian mips list, but alas I can't seem to sign up. I tried a whole bunch of things but the problem still persisted using etch. As soon as I went down to sarge/oldstable whings were ok. Heres what I've tried, and all of this made no change to the problem: - A fresh etch install, only adding ssh, screen and any packages needed to compile stuff. - Switched out the ram. The machine is using 3.3v ram, I swapped it for 5v as I had no other spare and it's worked fine before. - Tried another qube, (just swapped the disks) - Turned of IDE DMA using hdparm So hardware wize I've tried averything apart from another hard disk (I don't have one spare unfortunately). Sarge seems okay, however I'd rather run etch. Is there anything else I can check? Glyn --- On Sat, 26/7/08, Martin Michlmayr wrote: > From: Martin Michlmayr > Subject: Re: Debian etch on cobalt > To: "Glyn Astill" > Cc: linux-mips@linux-mips.org > Date: Saturday, 26 July, 2008, 12:46 AM > * Glyn Astill [2008-07-25 > 21:45]: > > I tried subscribing to the debian mipsel ilist with no > luck. > > There's no debian-mipsel list. debian-mips is used to > discuss both > the mips and mipsel ports. > > > When I start compiling postgres 8.3.3 it crashes > randomly, if I keep > > rebooting I can get it compiled, however theres > something seriously > > sh*gged here. > > > > Are there known problems? > > It's not a known problem. Do you have a serial > console? Is anything > printed on it when the machine crashes, or is it a hard > lockup without > anything on the console? > -- > Martin Michlmayr > http://www.cyrius.com/ __________________________________________________________ Not happy with your email address?. Get the one you really want - millions of new email addresses available now at Yahoo! http://uk.docs.yahoo.com/ymail/new.html From khickey@rmicorp.com Fri Aug 1 14:19:54 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 01 Aug 2008 14:20:01 +0100 (BST) Received: from mx1.razamicroelectronics.com ([63.111.213.197]:60505 "EHLO hq-ex-mb01.razamicroelectronics.com") by ftp.linux-mips.org with ESMTP id S28573782AbYHANTy (ORCPT ); Fri, 1 Aug 2008 14:19:54 +0100 Received: from sark.razamicroelectronics.com ([10.8.0.254]) by hq-ex-mb01.razamicroelectronics.com with Microsoft SMTPSVC(6.0.3790.3959); Fri, 1 Aug 2008 06:19:46 -0700 Received: from localhost.localdomain (unknown [10.8.0.25]) by sark.razamicroelectronics.com (Postfix) with ESMTP id 85D2C6DA533; Fri, 1 Aug 2008 08:12:33 -0500 (CDT) From: Kevin Hickey To: ralf@linux-mips.org Cc: linux-mips@linux-mips.org, Kevin Hickey Subject: [PATCH] [MIPS] DB1200: fix compile fail when CONFIG_FB_AU1200 is not selected Date: Fri, 1 Aug 2008 08:19:59 -0500 Message-Id: <1217596799-16754-1-git-send-email-khickey@rmicorp.com> X-Mailer: git-send-email 1.5.4.3 In-Reply-To: <> References: <> X-OriginalArrivalTime: 01 Aug 2008 13:19:46.0755 (UTC) FILETIME=[44C93930:01C8F3D9] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20073 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: khickey@rmicorp.com Precedence: bulk X-list: linux-mips There is a temporary variable declared in board_setup that is only used when CONFIG_FB_AU1200 is selected. It needs to be ifdef protected to prevent compile failures. Signed-off-by: Kevin Hickey --- arch/mips/au1000/pb1200/board_setup.c | 2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/arch/mips/au1000/pb1200/board_setup.c b/arch/mips/au1000/pb1200/board_setup.c index 6cb2115..fa03f44 100644 --- a/arch/mips/au1000/pb1200/board_setup.c +++ b/arch/mips/au1000/pb1200/board_setup.c @@ -41,7 +41,9 @@ void board_reset(void) void __init board_setup(void) { +#ifdef CONFIG_FB_AU1200 char *argptr = NULL; +#endif #if 0 { -- 1.5.4.3 From drzeus@drzeus.cx Fri Aug 1 18:05:32 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 01 Aug 2008 18:05:34 +0100 (BST) Received: from server.drzeus.cx ([85.8.24.28]:43472 "EHLO smtp.drzeus.cx") by ftp.linux-mips.org with ESMTP id S28574505AbYHARFc (ORCPT ); Fri, 1 Aug 2008 18:05:32 +0100 Received: from mjolnir.drzeus.cx (wlan248.drzeus.cx [::ffff:10.8.2.248]) (AUTH: LOGIN drzeus, TLS: TLSv1/SSLv3,256bits,AES256-SHA) by smtp.drzeus.cx with esmtp; Fri, 01 Aug 2008 19:05:24 +0200 id 0000000000130005.0000000048934254.0000471A Date: Fri, 1 Aug 2008 19:05:18 +0200 From: Pierre Ossman To: Manuel Lauss Cc: Sergei Shtylyov , linux-mips@linux-mips.org Subject: Re: [PATCH v2] au1xmmc: raise segment size limit. Message-ID: <20080801190518.4dbad293@mjolnir.drzeus.cx> In-Reply-To: <20080729081049.GB3908@roarinelk.homelinux.net> References: <20080729081049.GB3908@roarinelk.homelinux.net> X-Mailer: Claws Mail 3.4.0 (GTK+ 2.13.5; i386-redhat-linux-gnu) Mime-Version: 1.0 Content-Type: multipart/signed; protocol="application/pgp-signature"; micalg=PGP-SHA1; boundary="=_freyr.drzeus.cx-18202-1217610324-0001-2" Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20074 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: drzeus@drzeus.cx Precedence: bulk X-list: linux-mips This is a MIME-formatted message. If you see this text it means that your E-mail software does not support MIME-formatted messages. --=_freyr.drzeus.cx-18202-1217610324-0001-2 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: quoted-printable On Tue, 29 Jul 2008 10:10:49 +0200 Manuel Lauss wrote: > Hello Pierre,=20 >=20 > This is a new version of the previous patch with fixed commit text. >=20 > Please apply this patch as it fixes an oops when MMC-DMA and network > traffic are active at the same time; this seems to be a 2.6.27-only bug > as the current au1xmmc source work fine on 2.6.26. >=20 > Thank you, > Manuel Lauss >=20 > ---=20 applied. --=20 -- Pierre Ossman WARNING: This correspondence is being monitored by the Swedish government. Make sure your server uses encryption for SMTP traffic and consider using PGP for end-to-end encryption. --=_freyr.drzeus.cx-18202-1217610324-0001-2 Content-Type: application/pgp-signature; name="signature.asc" Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename=signature.asc -----BEGIN PGP SIGNATURE----- Version: GnuPG v2.0.9 (GNU/Linux) iEYEARECAAYFAkiTQlEACgkQ7b8eESbyJLhXyQCdFqi6KRGUm8jsozy5jS1FO9XR CIEAn3GOrSq+7zBWJVai+dECtLAwnVWw =Gra0 -----END PGP SIGNATURE----- --=_freyr.drzeus.cx-18202-1217610324-0001-2-- From supinlick@yahoo.com Fri Aug 1 19:21:17 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 01 Aug 2008 19:21:23 +0100 (BST) Received: from web51901.mail.re2.yahoo.com ([206.190.48.64]:37516 "HELO web51901.mail.re2.yahoo.com") by ftp.linux-mips.org with SMTP id S28574679AbYHASVR convert rfc822-to-8bit (ORCPT ); Fri, 1 Aug 2008 19:21:17 +0100 Received: (qmail 45448 invoked by uid 60001); 1 Aug 2008 18:21:07 -0000 DomainKey-Signature: a=rsa-sha1; q=dns; c=nofws; s=s1024; d=yahoo.com; h=Received:X-Mailer:Date:From:Reply-To:Subject:To:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-ID; b=RLDDWiX32FQcLjOLX4yhW9u8OG/2ELeHXlDKcrVak+iWMDn69iPw+Wpi0SN89k3OePvhyvBb93BcwFQ16mHDwta8sji8rsjM0pnc1YerAg8J7lvxdYKxGzCQCJhWXIVSmrvBkrhIEg5P92KJGaYaR4QpQqG3273bPVwCdrJFedc=; Received: from [155.104.37.17] by web51901.mail.re2.yahoo.com via HTTP; Fri, 01 Aug 2008 11:21:07 PDT X-Mailer: YahooMailWebService/0.7.218 Date: Fri, 1 Aug 2008 11:21:07 -0700 (PDT) From: Sean Parker Reply-To: supinlick@yahoo.com Subject: Reading DDR DCR's within Linux init process To: linux-mips@linux-mips.org MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: 8BIT Message-ID: <806819.43646.qm@web51901.mail.re2.yahoo.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20075 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: supinlick@yahoo.com Precedence: bulk X-list: linux-mips Hello- We're using the PMC-Sierra MSP85XX Sequoia processor... (RM9000 family) The BSP has PMON2000 and Linux 2.6.18 port. In configuring/fixing the PMON to properly recognize single- and double-sided RAM modules (no - the BSP did not come from PMC with 'fully' working code in it!) I became familiar with the DDR DCR config process via RAM's I2C access. The problem is we want to be able to dynamically read the DDR DCR's (>0xFF000000) setup by PMON, and use the results of that (physical RAM size, i.e. 2G) to call "add_memory_region" in place of the hard-coded 256M "add_memory_region" already called inside the msp85XX-specific "plat_mem_setup" (arch/mips/pmc-sierra/msp85xx/setup.c) start_kernel ... printk(linux_banner) setup_arch ... arch_mem_init ... plat_mem_setup (assign MSP85XX-specific function pointer used later as "late_time_init" below, and assign others) add_memory_region( 0x0, 0x10000000, ...) <-- hardcoded 256M parse_cmdline_early // normal "mem=" interpretation add_memory_region // how can I get pointer to 0xFF000000+ DDR DCR here // in the process? (before mem_init) mem_init kmem_cache_init setup_per_cpu_pageset numa_policy_init late_time_init = &py_map_ocd <-- this is where lots of DCR's are accessed using pointers provided by ioremap - TOO LATE TO CALL add_memory_region I suppose??? calibrate_delay pidmap_init ... Using command-line parameters (used inside "parse_cmdline_early") is not an option due to our system, and we don't want size-based linux images either. I have successfully been able to read the DDR DCRs inside "late_time_init" obtaining a pointer via ioremap call, but that is not a valid call earlier within the context of the setup_arch sequence - is this true? (I get exceptions when I do that) However in late_time_init is too late to call "add_memory_region". Does anyone have any ideas? Comments? What other call/procedure analogous to ioremap can I make earlier to access the DDR DCR insite setup_arch process? God Bless Sean Parker From tbm@cyrius.com Sun Aug 3 07:59:53 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 03 Aug 2008 08:00:00 +0100 (BST) Received: from sorrow.cyrius.com ([65.19.161.204]:38417 "EHLO sorrow.cyrius.com") by ftp.linux-mips.org with ESMTP id S20030992AbYHCG7x (ORCPT ); Sun, 3 Aug 2008 07:59:53 +0100 Received: by sorrow.cyrius.com (Postfix, from userid 10) id 481BBD8DE; Sun, 3 Aug 2008 06:59:50 +0000 (UTC) Received: by deprecation.cyrius.com (Postfix, from userid 1000) id C749715063A; Sun, 3 Aug 2008 09:58:22 +0300 (IDT) Date: Sun, 3 Aug 2008 09:58:22 +0300 From: Martin Michlmayr To: Glyn Astill Cc: linux-mips@linux-mips.org Subject: Re: Debian etch on cobalt Message-ID: <20080803065822.GE5392@deprecation.cyrius.com> References: <20080725234605.GE2512@deprecation.cyrius.com> <197761.16530.qm@web25806.mail.ukl.yahoo.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <197761.16530.qm@web25806.mail.ukl.yahoo.com> User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20076 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: tbm@cyrius.com Precedence: bulk X-list: linux-mips * Glyn Astill [2008-08-01 10:49]: > Sarge seems okay, however I'd rather run etch. Is there anything else I can check? I'm not sure. There used to be a hang connected to DMA and high network traffic, but this should be fixed in the kernel in etch. -- Martin Michlmayr http://www.cyrius.com/ From glynastill@yahoo.co.uk Sun Aug 3 14:56:06 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 03 Aug 2008 14:56:14 +0100 (BST) Received: from web25805.mail.ukl.yahoo.com ([217.12.10.190]:22355 "HELO web25805.mail.ukl.yahoo.com") by ftp.linux-mips.org with SMTP id S20026462AbYHCN4G convert rfc822-to-8bit (ORCPT ); Sun, 3 Aug 2008 14:56:06 +0100 Received: (qmail 35492 invoked by uid 60001); 3 Aug 2008 13:55:58 -0000 DomainKey-Signature: a=rsa-sha1; q=dns; c=nofws; s=s1024; d=yahoo.co.uk; h=Received:X-Mailer:Date:From:Reply-To:Subject:To:Cc:In-Reply-To:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-ID; b=kza3Sn0Fv/TUKnx/1OD0RVdT3fp7TWbIdNNOk89YvyZVhbjVTGd4ZjxcCvZlz8droIVtxkBsmbnILvmWuAuXlh4HOFohqPDeW2VljIRSBchGKh6M+UGgOD2CPZ7vwqXfNEwqnOJf4qqBHjVrosVq2WxgEc9qTEYW6YAkBGdKb/E=; Received: from [86.3.223.194] by web25805.mail.ukl.yahoo.com via HTTP; Sun, 03 Aug 2008 13:55:58 GMT X-Mailer: YahooMailWebService/0.7.218 Date: Sun, 3 Aug 2008 13:55:58 +0000 (GMT) From: Glyn Astill Reply-To: glynastill@yahoo.co.uk Subject: Re: Debian etch on cobalt To: Martin Michlmayr Cc: linux-mips@linux-mips.org In-Reply-To: <20080803065822.GE5392@deprecation.cyrius.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8BIT Message-ID: <758145.35434.qm@web25805.mail.ukl.yahoo.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20077 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: glynastill@yahoo.co.uk Precedence: bulk X-list: linux-mips Just discovered sarge falls over too, however less frequently. So perhaps it's something else, I'm not sure now. I've switched the drive out, I actually managed to find the original 20gig unit that came with it. One thing I observed today is free memory getting rather low whilst compiling, it shows about 187Mb total, and I've watched it go as low as 8mb free. The only other thing I can think of is it's possibly overheating and falling over. --- On Sun, 3/8/08, Martin Michlmayr wrote: > From: Martin Michlmayr > Subject: Re: Debian etch on cobalt > To: "Glyn Astill" > Cc: linux-mips@linux-mips.org > Date: Sunday, 3 August, 2008, 7:58 AM > * Glyn Astill [2008-08-01 > 10:49]: > > Sarge seems okay, however I'd rather run etch. Is > there anything else I can check? > > I'm not sure. > > There used to be a hang connected to DMA and high network > traffic, but > this should be fixed in the kernel in etch. > -- > Martin Michlmayr > http://www.cyrius.com/ __________________________________________________________ Not happy with your email address?. Get the one you really want - millions of new email addresses available now at Yahoo! http://uk.docs.yahoo.com/ymail/new.html From tsbogend@alpha.franken.de Sun Aug 3 18:41:57 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 03 Aug 2008 18:42:04 +0100 (BST) Received: from elvis.franken.de ([193.175.24.41]:18142 "EHLO elvis.franken.de") by ftp.linux-mips.org with ESMTP id S20038520AbYHCRl5 (ORCPT ); Sun, 3 Aug 2008 18:41:57 +0100 Received: from uucp (helo=solo.franken.de) by elvis.franken.de with local-bsmtp (Exim 3.36 #1) id 1KPhac-0004pW-00; Sun, 03 Aug 2008 19:41:54 +0200 Received: by solo.franken.de (Postfix, from userid 1000) id 985F61DA6F4; Sun, 3 Aug 2008 19:41:46 +0200 (CEST) From: Thomas Bogendoerfer Subject: [PATCH] IP22/28: Switch over to RTC class driver To: linux-mips@linux-mips.org cc: ralf@linux-mips.org Message-Id: <20080803174146.985F61DA6F4@solo.franken.de> Date: Sun, 3 Aug 2008 19:41:46 +0200 (CEST) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20078 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: tsbogend@alpha.franken.de Precedence: bulk X-list: linux-mips This patchset removes some dead code and creates a platform device for the RTC class driver. Signed-off-by: Thomas Bogendoerfer --- arch/mips/sgi-ip22/ip22-platform.c | 15 ++++++++ arch/mips/sgi-ip22/ip22-setup.c | 1 - arch/mips/sgi-ip22/ip22-time.c | 64 ----------------------------------- include/asm-mips/mach-ip22/ds1286.h | 18 ---------- include/asm-mips/mach-ip28/ds1286.h | 4 -- include/linux/ds1286.h | 2 - 6 files changed, 15 insertions(+), 89 deletions(-) diff --git a/arch/mips/sgi-ip22/ip22-platform.c b/arch/mips/sgi-ip22/ip22-platform.c index 6014123..cbca336 100644 --- a/arch/mips/sgi-ip22/ip22-platform.c +++ b/arch/mips/sgi-ip22/ip22-platform.c @@ -192,3 +192,18 @@ static int __init sgi_button_devinit(void) } device_initcall(sgi_button_devinit); + +static int __init sgi_ds1286_devinit(void) +{ + struct resource res; + + memset(&res, 0, sizeof(res)); + res.start = HPC3_CHIP0_BASE + offsetof(struct hpc3_regs, rtcregs); + res.end = res.start + sizeof(hpc3c0->rtcregs); + res.flags = IORESOURCE_MEM; + + return IS_ERR(platform_device_register_simple("rtc-ds1286", -1, + &res, 1)); +} + +device_initcall(sgi_ds1286_devinit); diff --git a/arch/mips/sgi-ip22/ip22-setup.c b/arch/mips/sgi-ip22/ip22-setup.c index 896a1ef..b9a9313 100644 --- a/arch/mips/sgi-ip22/ip22-setup.c +++ b/arch/mips/sgi-ip22/ip22-setup.c @@ -4,7 +4,6 @@ * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) * Copyright (C) 1997, 1998 Ralf Baechle (ralf@gnu.org) */ -#include #include #include #include diff --git a/arch/mips/sgi-ip22/ip22-time.c b/arch/mips/sgi-ip22/ip22-time.c index 10e5054..3dcb27e 100644 --- a/arch/mips/sgi-ip22/ip22-time.c +++ b/arch/mips/sgi-ip22/ip22-time.c @@ -10,7 +10,6 @@ * Copyright (C) 2003, 06 Ralf Baechle (ralf@linux-mips.org) */ #include -#include #include #include #include @@ -29,69 +28,6 @@ #include #include -/* - * Note that mktime uses month from 1 to 12 while rtc_time_to_tm - * uses 0 to 11. - */ -unsigned long read_persistent_clock(void) -{ - unsigned int yrs, mon, day, hrs, min, sec; - unsigned int save_control; - unsigned long flags; - - spin_lock_irqsave(&rtc_lock, flags); - save_control = hpc3c0->rtcregs[RTC_CMD] & 0xff; - hpc3c0->rtcregs[RTC_CMD] = save_control | RTC_TE; - - sec = BCD2BIN(hpc3c0->rtcregs[RTC_SECONDS] & 0xff); - min = BCD2BIN(hpc3c0->rtcregs[RTC_MINUTES] & 0xff); - hrs = BCD2BIN(hpc3c0->rtcregs[RTC_HOURS] & 0x3f); - day = BCD2BIN(hpc3c0->rtcregs[RTC_DATE] & 0xff); - mon = BCD2BIN(hpc3c0->rtcregs[RTC_MONTH] & 0x1f); - yrs = BCD2BIN(hpc3c0->rtcregs[RTC_YEAR] & 0xff); - - hpc3c0->rtcregs[RTC_CMD] = save_control; - spin_unlock_irqrestore(&rtc_lock, flags); - - if (yrs < 45) - yrs += 30; - if ((yrs += 40) < 70) - yrs += 100; - - return mktime(yrs + 1900, mon, day, hrs, min, sec); -} - -int rtc_mips_set_time(unsigned long tim) -{ - struct rtc_time tm; - unsigned int save_control; - unsigned long flags; - - rtc_time_to_tm(tim, &tm); - - tm.tm_mon += 1; /* tm_mon starts at zero */ - tm.tm_year -= 40; - if (tm.tm_year >= 100) - tm.tm_year -= 100; - - spin_lock_irqsave(&rtc_lock, flags); - save_control = hpc3c0->rtcregs[RTC_CMD] & 0xff; - hpc3c0->rtcregs[RTC_CMD] = save_control | RTC_TE; - - hpc3c0->rtcregs[RTC_YEAR] = BIN2BCD(tm.tm_year); - hpc3c0->rtcregs[RTC_MONTH] = BIN2BCD(tm.tm_mon); - hpc3c0->rtcregs[RTC_DATE] = BIN2BCD(tm.tm_mday); - hpc3c0->rtcregs[RTC_HOURS] = BIN2BCD(tm.tm_hour); - hpc3c0->rtcregs[RTC_MINUTES] = BIN2BCD(tm.tm_min); - hpc3c0->rtcregs[RTC_SECONDS] = BIN2BCD(tm.tm_sec); - hpc3c0->rtcregs[RTC_HUNDREDTH_SECOND] = 0; - - hpc3c0->rtcregs[RTC_CMD] = save_control; - spin_unlock_irqrestore(&rtc_lock, flags); - - return 0; -} - static unsigned long dosample(void) { u32 ct0, ct1; diff --git a/include/asm-mips/mach-ip22/ds1286.h b/include/asm-mips/mach-ip22/ds1286.h deleted file mode 100644 index f19f1ea..0000000 --- a/include/asm-mips/mach-ip22/ds1286.h +++ /dev/null @@ -1,18 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1998, 2001, 03 by Ralf Baechle - * - * RTC routines for PC style attached Dallas chip. - */ -#ifndef __ASM_MACH_IP22_DS1286_H -#define __ASM_MACH_IP22_DS1286_H - -#include - -#define rtc_read(reg) (hpc3c0->rtcregs[(reg)] & 0xff) -#define rtc_write(data, reg) do { hpc3c0->rtcregs[(reg)] = (data); } while(0) - -#endif /* __ASM_MACH_IP22_DS1286_H */ diff --git a/include/asm-mips/mach-ip28/ds1286.h b/include/asm-mips/mach-ip28/ds1286.h deleted file mode 100644 index 471bb9a..0000000 --- a/include/asm-mips/mach-ip28/ds1286.h +++ /dev/null @@ -1,4 +0,0 @@ -#ifndef __ASM_MACH_IP28_DS1286_H -#define __ASM_MACH_IP28_DS1286_H -#include -#endif /* __ASM_MACH_IP28_DS1286_H */ diff --git a/include/linux/ds1286.h b/include/linux/ds1286.h index d898986..45ea0aa 100644 --- a/include/linux/ds1286.h +++ b/include/linux/ds1286.h @@ -8,8 +8,6 @@ #ifndef __LINUX_DS1286_H #define __LINUX_DS1286_H -#include - /********************************************************************** * register summary **********************************************************************/ From tsbogend@alpha.franken.de Sun Aug 3 18:42:21 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 03 Aug 2008 18:42:25 +0100 (BST) Received: from elvis.franken.de ([193.175.24.41]:18398 "EHLO elvis.franken.de") by ftp.linux-mips.org with ESMTP id S20038522AbYHCRl5 (ORCPT ); Sun, 3 Aug 2008 18:41:57 +0100 Received: from uucp (helo=solo.franken.de) by elvis.franken.de with local-bsmtp (Exim 3.36 #1) id 1KPhac-0004pW-01; Sun, 03 Aug 2008 19:41:54 +0200 Received: by solo.franken.de (Postfix, from userid 1000) id F29DC1DA6F4; Sun, 3 Aug 2008 19:41:49 +0200 (CEST) From: Thomas Bogendoerfer Subject: [PATCH] IP27: Switch over to RTC class driver To: linux-mips@linux-mips.org cc: ralf@linux-mips.org Message-Id: <20080803174149.F29DC1DA6F4@solo.franken.de> Date: Sun, 3 Aug 2008 19:41:49 +0200 (CEST) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20079 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: tsbogend@alpha.franken.de Precedence: bulk X-list: linux-mips This patchset removes some dead code and creates a platform device for the RTC class driver. Signed-off-by: Thomas Bogendoerfer --- arch/mips/sgi-ip27/ip27-timer.c | 95 +++++++------------------------------- 1 files changed, 18 insertions(+), 77 deletions(-) diff --git a/arch/mips/sgi-ip27/ip27-timer.c b/arch/mips/sgi-ip27/ip27-timer.c index 8b4e854..94a105b 100644 --- a/arch/mips/sgi-ip27/ip27-timer.c +++ b/arch/mips/sgi-ip27/ip27-timer.c @@ -13,12 +13,12 @@ #include #include #include +#include #include #include #include #include -#include #include #include #include @@ -28,51 +28,6 @@ #define TICK_SIZE (tick_nsec / 1000) -#if 0 -static int set_rtc_mmss(unsigned long nowtime) -{ - int retval = 0; - int real_seconds, real_minutes, cmos_minutes; - struct m48t35_rtc *rtc; - nasid_t nid; - - nid = get_nasid(); - rtc = (struct m48t35_rtc *)(KL_CONFIG_CH_CONS_INFO(nid)->memory_base + - IOC3_BYTEBUS_DEV0); - - rtc->control |= M48T35_RTC_READ; - cmos_minutes = BCD2BIN(rtc->min); - rtc->control &= ~M48T35_RTC_READ; - - /* - * Since we're only adjusting minutes and seconds, don't interfere with - * hour overflow. This avoids messing with unknown time zones but - * requires your RTC not to be off by more than 15 minutes - */ - real_seconds = nowtime % 60; - real_minutes = nowtime / 60; - if (((abs(real_minutes - cmos_minutes) + 15)/30) & 1) - real_minutes += 30; /* correct for half hour time zone */ - real_minutes %= 60; - - if (abs(real_minutes - cmos_minutes) < 30) { - real_seconds = BIN2BCD(real_seconds); - real_minutes = BIN2BCD(real_minutes); - rtc->control |= M48T35_RTC_SET; - rtc->sec = real_seconds; - rtc->min = real_minutes; - rtc->control &= ~M48T35_RTC_SET; - } else { - printk(KERN_WARNING - "set_rtc_mmss: can't update from %d to %d\n", - cmos_minutes, real_minutes); - retval = -1; - } - - return retval; -} -#endif - /* Includes for ioc3_init(). */ #include #include @@ -80,37 +35,6 @@ static int set_rtc_mmss(unsigned long nowtime) #include #include -unsigned long read_persistent_clock(void) -{ - unsigned int year, month, date, hour, min, sec; - struct m48t35_rtc *rtc; - nasid_t nid; - - nid = get_nasid(); - rtc = (struct m48t35_rtc *)(KL_CONFIG_CH_CONS_INFO(nid)->memory_base + - IOC3_BYTEBUS_DEV0); - - rtc->control |= M48T35_RTC_READ; - sec = rtc->sec; - min = rtc->min; - hour = rtc->hour; - date = rtc->date; - month = rtc->month; - year = rtc->year; - rtc->control &= ~M48T35_RTC_READ; - - sec = BCD2BIN(sec); - min = BCD2BIN(min); - hour = BCD2BIN(hour); - date = BCD2BIN(date); - month = BCD2BIN(month); - year = BCD2BIN(year); - - year += 1970; - - return mktime(year, month, date, hour, min, sec); -} - static void enable_rt_irq(unsigned int irq) { } @@ -286,6 +210,7 @@ void __cpuinit cpu_time_init(void) void __cpuinit hub_rtc_init(cnodeid_t cnode) { + /* * We only need to initialize the current node. * If this is not the current node then it is a cpuless @@ -301,3 +226,19 @@ void __cpuinit hub_rtc_init(cnodeid_t cnode) LOCAL_HUB_S(PI_RT_PEND_B, 0); } } + +static int __init sgi_ip27_rtc_devinit(void) +{ + struct resource res; + + memset(&res, 0, sizeof(res)); + res.start = KL_CONFIG_CH_CONS_INFO(master_nasid)->memory_base + + IOC3_BYTEBUS_DEV0; + res.end = res.start + 32768; + res.flags = IORESOURCE_MEM; + + return IS_ERR(platform_device_register_simple("rtc-m48t35", -1, + &res, 1)); +} + +device_initcall(sgi_ip27_rtc_devinit); From tsbogend@alpha.franken.de Sun Aug 3 18:42:42 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 03 Aug 2008 18:42:49 +0100 (BST) Received: from elvis.franken.de ([193.175.24.41]:19422 "EHLO elvis.franken.de") by ftp.linux-mips.org with ESMTP id S20038521AbYHCRl5 (ORCPT ); Sun, 3 Aug 2008 18:41:57 +0100 Received: from uucp (helo=solo.franken.de) by elvis.franken.de with local-bsmtp (Exim 3.36 #1) id 1KPhab-0004pW-01; Sun, 03 Aug 2008 19:41:53 +0200 Received: by solo.franken.de (Postfix, from userid 1000) id 797B51DA6F4; Sun, 3 Aug 2008 19:41:40 +0200 (CEST) From: Thomas Bogendoerfer Subject: [PATCH] M48T35: new RTC driver To: rtc-linux@googlegroups.com, linux-mips@linux-mips.org cc: a.zummo@towertech.it, ralf@linux-mips.org Message-Id: <20080803174140.797B51DA6F4@solo.franken.de> Date: Sun, 3 Aug 2008 19:41:40 +0200 (CEST) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20080 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: tsbogend@alpha.franken.de Precedence: bulk X-list: linux-mips This driver replaces the broken ip27-rtc driver in drivers/char and gives back RTC support for SGI IP27 machines. Signed-off-by: Thomas Bogendoerfer --- drivers/rtc/Kconfig | 10 ++ drivers/rtc/Makefile | 1 + drivers/rtc/rtc-m48t35.c | 238 ++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 249 insertions(+), 0 deletions(-) diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig index 90ab738..725d9a5 100644 --- a/drivers/rtc/Kconfig +++ b/drivers/rtc/Kconfig @@ -405,6 +405,16 @@ config RTC_DRV_M48T86 This driver can also be built as a module. If so, the module will be called rtc-m48t86. +config RTC_DRV_M48T35 + tristate "ST M48T35" + depends on SGI_IP27 + help + If you say Y here you will get support for the + ST M48T35 RTC chip. + + This driver can also be built as a module, if so, the module + will be called "rtc-m48t35". + config RTC_DRV_M48T59 tristate "ST M48T59" help diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile index 18622ef..7d10cc0 100644 --- a/drivers/rtc/Makefile +++ b/drivers/rtc/Makefile @@ -36,6 +36,7 @@ obj-$(CONFIG_RTC_DRV_FM3130) += rtc-fm3130.o obj-$(CONFIG_RTC_DRV_ISL1208) += rtc-isl1208.o obj-$(CONFIG_RTC_DRV_M41T80) += rtc-m41t80.o obj-$(CONFIG_RTC_DRV_M41T94) += rtc-m41t94.o +obj-$(CONFIG_RTC_DRV_M48T35) += rtc-m48t35.o obj-$(CONFIG_RTC_DRV_M48T59) += rtc-m48t59.o obj-$(CONFIG_RTC_DRV_M48T86) += rtc-m48t86.o obj-$(CONFIG_RTC_DRV_MAX6900) += rtc-max6900.o diff --git a/drivers/rtc/rtc-m48t35.c b/drivers/rtc/rtc-m48t35.c new file mode 100644 index 0000000..7add023 --- /dev/null +++ b/drivers/rtc/rtc-m48t35.c @@ -0,0 +1,238 @@ +/* + * Driver for the SGS-Thomson M48T35 Timekeeper RAM chip + * + * Copyright (C) 2000 Silicon Graphics, Inc. + * Written by Ulf Carlsson (ulfc@engr.sgi.com) + * + * Copyright (C) 2008 Thomas Bogendoerfer + * + * Based on code written by Paul Gortmaker. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include +#include +#include +#include + +#define DRV_VERSION "1.0" + +struct m48t35_rtc { + u8 pad[0x7ff8]; /* starts at 0x7ff8 */ + u8 control; + u8 sec; + u8 min; + u8 hour; + u8 day; + u8 date; + u8 month; + u8 year; +}; + +#define M48T35_RTC_SET 0x80 +#define M48T35_RTC_READ 0x40 + +struct m48t35_priv { + struct rtc_device *rtc; + struct m48t35_rtc __iomem *reg; + size_t size; + unsigned long baseaddr; + spinlock_t lock; +}; + +static unsigned char days_in_mo[] = { + 0, 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 +}; + +static int m48t35_read_time(struct device *dev, struct rtc_time *tm) +{ + struct m48t35_priv *priv = dev_get_drvdata(dev); + u8 control; + + /* + * Only the values that we read from the RTC are set. We leave + * tm_wday, tm_yday and tm_isdst untouched. Even though the + * RTC has RTC_DAY_OF_WEEK, we ignore it, as it is only updated + * by the RTC when initially set to a non-zero value. + */ + spin_lock_irq(&priv->lock); + control = readb(&priv->reg->control); + writeb(control | M48T35_RTC_READ, &priv->reg->control); + tm->tm_sec = readb(&priv->reg->sec); + tm->tm_min = readb(&priv->reg->min); + tm->tm_hour = readb(&priv->reg->hour); + tm->tm_mday = readb(&priv->reg->date); + tm->tm_mon = readb(&priv->reg->month); + tm->tm_year = readb(&priv->reg->year); + writeb(control, &priv->reg->control); + spin_unlock_irq(&priv->lock); + + tm->tm_sec = BCD2BIN(tm->tm_sec); + tm->tm_min = BCD2BIN(tm->tm_min); + tm->tm_hour = BCD2BIN(tm->tm_hour); + tm->tm_mday = BCD2BIN(tm->tm_mday); + tm->tm_mon = BCD2BIN(tm->tm_mon); + tm->tm_year = BCD2BIN(tm->tm_year); + + /* + * Account for differences between how the RTC uses the values + * and how they are defined in a struct rtc_time; + */ + tm->tm_year += 70; + if (tm->tm_year <= 69) + tm->tm_year += 100; + + tm->tm_mon--; + return rtc_valid_tm(tm); +} + +static int m48t35_set_time(struct device *dev, struct rtc_time *tm) +{ + struct m48t35_priv *priv = dev_get_drvdata(dev); + unsigned char mon, day, hrs, min, sec, leap_yr; + unsigned int yrs; + u8 control; + + yrs = tm->tm_year + 1900; + mon = tm->tm_mon + 1; /* tm_mon starts at zero */ + day = tm->tm_mday; + hrs = tm->tm_hour; + min = tm->tm_min; + sec = tm->tm_sec; + + if (yrs < 1970) + return -EINVAL; + + leap_yr = ((!(yrs % 4) && (yrs % 100)) || !(yrs % 400)); + + if ((mon > 12) || (day == 0)) + return -EINVAL; + + if (day > (days_in_mo[mon] + ((mon == 2) && leap_yr))) + return -EINVAL; + + if ((hrs >= 24) || (min >= 60) || (sec >= 60)) + return -EINVAL; + + yrs -= 1970; + if (yrs > 255) /* They are unsigned */ + return -EINVAL; + + if (yrs > 169) + return -EINVAL; + + if (yrs >= 100) + yrs -= 100; + + sec = BIN2BCD(sec); + min = BIN2BCD(min); + hrs = BIN2BCD(hrs); + day = BIN2BCD(day); + mon = BIN2BCD(mon); + yrs = BIN2BCD(yrs); + + spin_lock_irq(&priv->lock); + control = readb(&priv->reg->control); + writeb(control | M48T35_RTC_SET, &priv->reg->control); + writeb(yrs, &priv->reg->year); + writeb(mon, &priv->reg->month); + writeb(day, &priv->reg->date); + writeb(hrs, &priv->reg->hour); + writeb(min, &priv->reg->min); + writeb(sec, &priv->reg->sec); + writeb(control, &priv->reg->control); + spin_unlock_irq(&priv->lock); + return 0; +} + +static const struct rtc_class_ops m48t35_ops = { + .read_time = m48t35_read_time, + .set_time = m48t35_set_time, +}; + +static int __devinit m48t35_probe(struct platform_device *pdev) +{ + struct rtc_device *rtc; + struct resource *res; + struct m48t35_priv *priv; + int ret = 0; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) + return -ENODEV; + priv = kzalloc(sizeof *priv, GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->size = res->end - res->start + 1; + if (!request_mem_region(res->start, priv->size, pdev->name)) { + ret = -EBUSY; + goto out; + } + priv->baseaddr = res->start; + priv->reg = (struct m48t35_rtc __iomem *)res->start; + if (!priv->reg) { + ret = -ENOMEM; + goto out; + } + spin_lock_init(&priv->lock); + rtc = rtc_device_register("m48t35", &pdev->dev, + &m48t35_ops, THIS_MODULE); + if (IS_ERR(rtc)) { + ret = PTR_ERR(rtc); + goto out; + } + priv->rtc = rtc; + platform_set_drvdata(pdev, priv); + return 0; + +out: + if (priv->rtc) + rtc_device_unregister(priv->rtc); + if (priv->baseaddr) + release_mem_region(priv->baseaddr, priv->size); + kfree(priv); + return ret; +} + +static int __devexit m48t35_remove(struct platform_device *pdev) +{ + struct m48t35_priv *priv = platform_get_drvdata(pdev); + + rtc_device_unregister(priv->rtc); + release_mem_region(priv->baseaddr, priv->size); + kfree(priv); + return 0; +} + +static struct platform_driver m48t35_platform_driver = { + .driver = { + .name = "rtc-m48t35", + .owner = THIS_MODULE, + }, + .probe = m48t35_probe, + .remove = __devexit_p(m48t35_remove), +}; + +static int __init m48t35_init(void) +{ + return platform_driver_register(&m48t35_platform_driver); +} + +static void __exit m48t35_exit(void) +{ + platform_driver_unregister(&m48t35_platform_driver); +} + +MODULE_AUTHOR("Thomas Bogendoerfer "); +MODULE_DESCRIPTION("M48T35 RTC driver"); +MODULE_LICENSE("GPL"); +MODULE_VERSION(DRV_VERSION); +MODULE_ALIAS("platform:rtc-m48t35"); + +module_init(m48t35_init); +module_exit(m48t35_exit); From tsbogend@alpha.franken.de Sun Aug 3 18:43:06 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 03 Aug 2008 18:43:13 +0100 (BST) Received: from elvis.franken.de ([193.175.24.41]:19166 "EHLO elvis.franken.de") by ftp.linux-mips.org with ESMTP id S20038523AbYHCRl5 (ORCPT ); Sun, 3 Aug 2008 18:41:57 +0100 Received: from uucp (helo=solo.franken.de) by elvis.franken.de with local-bsmtp (Exim 3.36 #1) id 1KPhab-0004pW-00; Sun, 03 Aug 2008 19:41:53 +0200 Received: by solo.franken.de (Postfix, from userid 1000) id AF8071DA6F4; Sun, 3 Aug 2008 19:41:37 +0200 (CEST) From: Thomas Bogendoerfer Subject: [PATCH] DS1286: new RTC driver To: rtc-linux@googlegroups.com, linux-mips@linux-mips.org cc: a.zummo@towertech.it, ralf@linux-mips.org Message-Id: <20080803174137.AF8071DA6F4@solo.franken.de> Date: Sun, 3 Aug 2008 19:41:37 +0200 (CEST) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20081 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: tsbogend@alpha.franken.de Precedence: bulk X-list: linux-mips This driver replaces the broken DS1286 driver in drivers/char and gives back RTC support for SGI IP22 and IP28 machines. Signed-off-by: Thomas Bogendoerfer --- drivers/rtc/Kconfig | 6 + drivers/rtc/Makefile | 1 + drivers/rtc/rtc-ds1286.c | 425 ++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 432 insertions(+), 0 deletions(-) diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig index 90ab738..934f630 100644 --- a/drivers/rtc/Kconfig +++ b/drivers/rtc/Kconfig @@ -352,6 +352,12 @@ config RTC_DRV_DS1216 help If you say yes here you get support for the Dallas DS1216 RTC chips. +config RTC_DRV_DS1286 + tristate "Dallas DS1286" + depends on SGI_HAS_DS1286 + help + If you say yes here you get support for the Dallas DS1286 RTC chips. + config RTC_DRV_DS1302 tristate "Dallas DS1302" depends on SH_SECUREEDGE5410 diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile index 18622ef..e060802 100644 --- a/drivers/rtc/Makefile +++ b/drivers/rtc/Makefile @@ -23,6 +23,7 @@ obj-$(CONFIG_RTC_DRV_AT91SAM9) += rtc-at91sam9.o obj-$(CONFIG_RTC_DRV_BFIN) += rtc-bfin.o obj-$(CONFIG_RTC_DRV_CMOS) += rtc-cmos.o obj-$(CONFIG_RTC_DRV_DS1216) += rtc-ds1216.o +obj-$(CONFIG_RTC_DRV_DS1286) += rtc-ds1286.o obj-$(CONFIG_RTC_DRV_DS1302) += rtc-ds1302.o obj-$(CONFIG_RTC_DRV_DS1305) += rtc-ds1305.o obj-$(CONFIG_RTC_DRV_DS1307) += rtc-ds1307.o diff --git a/drivers/rtc/rtc-ds1286.c b/drivers/rtc/rtc-ds1286.c new file mode 100644 index 0000000..2f6def0 --- /dev/null +++ b/drivers/rtc/rtc-ds1286.c @@ -0,0 +1,425 @@ +/* + * DS1286 Real Time Clock interface for Linux + * + * Copyright (C) 1998, 1999, 2000 Ralf Baechle + * Copyright (C) 2008 Thomas Bogendoerfer + * + * Based on code written by Paul Gortmaker. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include +#include +#include +#include +#include + +#define DRV_VERSION "1.0" + +struct ds1286_priv { + struct rtc_device *rtc; + u32 __iomem *rtcregs; + size_t size; + unsigned long baseaddr; + spinlock_t lock; +}; + +static unsigned char days_in_mo[] = { + 0, 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 +}; + +static inline u8 ds1286_rtc_read(struct ds1286_priv *priv, int reg) +{ + return __raw_readl(&priv->rtcregs[reg]) & 0xff; +} + +static inline void ds1286_rtc_write(struct ds1286_priv *priv, u8 data, int reg) +{ + __raw_writel(data, &priv->rtcregs[reg]); +} + +#ifdef CONFIG_RTC_INTF_DEV + +static int ds1286_ioctl(struct device *dev, unsigned int cmd, unsigned long arg) +{ + struct ds1286_priv *priv = dev_get_drvdata(dev); + unsigned long flags; + unsigned char val; + + switch (cmd) { + case RTC_AIE_OFF: + /* Mask alarm int. enab. bit */ + spin_lock_irqsave(&priv->lock, flags); + val = ds1286_rtc_read(priv, RTC_CMD); + val |= RTC_TDM; + ds1286_rtc_write(priv, val, RTC_CMD); + spin_unlock_irqrestore(&priv->lock, flags); + break; + case RTC_AIE_ON: + /* Allow alarm interrupts. */ + spin_lock_irqsave(&priv->lock, flags); + val = ds1286_rtc_read(priv, RTC_CMD); + val &= ~RTC_TDM; + ds1286_rtc_write(priv, val, RTC_CMD); + spin_unlock_irqrestore(&priv->lock, flags); + break; + case RTC_WIE_OFF: + /* Mask watchdog int. enab. bit */ + spin_lock_irqsave(&priv->lock, flags); + val = ds1286_rtc_read(priv, RTC_CMD); + val |= RTC_WAM; + ds1286_rtc_write(priv, val, RTC_CMD); + spin_unlock_irqrestore(&priv->lock, flags); + break; + case RTC_WIE_ON: + /* Allow watchdog interrupts. */ + spin_lock_irqsave(&priv->lock, flags); + val = ds1286_rtc_read(priv, RTC_CMD); + val &= ~RTC_WAM; + ds1286_rtc_write(priv, val, RTC_CMD); + spin_unlock_irqrestore(&priv->lock, flags); + break; + default: + return -ENOIOCTLCMD; + } + return 0; +} + +#else +#define ds1286_ioctl NULL +#endif + +#ifdef CONFIG_PROC_FS + +static int ds1286_proc(struct device *dev, struct seq_file *seq) +{ + struct ds1286_priv *priv = dev_get_drvdata(dev); + unsigned char month, cmd, amode; + const char *s; + + month = ds1286_rtc_read(priv, RTC_MONTH); + seq_printf(seq, + "oscillator\t: %s\n" + "square_wave\t: %s\n", + (month & RTC_EOSC) ? "disabled" : "enabled", + (month & RTC_ESQW) ? "disabled" : "enabled"); + + amode = ((ds1286_rtc_read(priv, RTC_MINUTES_ALARM) & 0x80) >> 5) | + ((ds1286_rtc_read(priv, RTC_HOURS_ALARM) & 0x80) >> 6) | + ((ds1286_rtc_read(priv, RTC_DAY_ALARM) & 0x80) >> 7); + switch (amode) { + case 7: + s = "each minute"; + break; + case 3: + s = "minutes match"; + break; + case 1: + s = "hours and minutes match"; + break; + case 0: + s = "days, hours and minutes match"; + break; + default: + s = "invalid"; + break; + } + seq_printf(seq, "alarm_mode\t: %s\n", s); + + cmd = ds1286_rtc_read(priv, RTC_CMD); + seq_printf(seq, + "alarm_enable\t: %s\n" + "wdog_alarm\t: %s\n" + "alarm_mask\t: %s\n" + "wdog_alarm_mask\t: %s\n" + "interrupt_mode\t: %s\n" + "INTB_mode\t: %s_active\n" + "interrupt_pins\t: %s\n", + (cmd & RTC_TDF) ? "yes" : "no", + (cmd & RTC_WAF) ? "yes" : "no", + (cmd & RTC_TDM) ? "disabled" : "enabled", + (cmd & RTC_WAM) ? "disabled" : "enabled", + (cmd & RTC_PU_LVL) ? "pulse" : "level", + (cmd & RTC_IBH_LO) ? "low" : "high", + (cmd & RTC_IPSW) ? "unswapped" : "swapped"); + return 0; +} + +#else +#define ds1286_proc NULL +#endif + +static int ds1286_read_time(struct device *dev, struct rtc_time *tm) +{ + struct ds1286_priv *priv = dev_get_drvdata(dev); + unsigned char save_control; + unsigned long flags; + unsigned long uip_watchdog = jiffies; + + /* + * read RTC once any update in progress is done. The update + * can take just over 2ms. We wait 10 to 20ms. There is no need to + * to poll-wait (up to 1s - eeccch) for the falling edge of RTC_UIP. + * If you need to know *exactly* when a second has started, enable + * periodic update complete interrupts, (via ioctl) and then + * immediately read /dev/rtc which will block until you get the IRQ. + * Once the read clears, read the RTC time (again via ioctl). Easy. + */ + + if (ds1286_rtc_read(priv, RTC_CMD) & RTC_TE) + while (time_before(jiffies, uip_watchdog + 2*HZ/100)) + barrier(); + + /* + * Only the values that we read from the RTC are set. We leave + * tm_wday, tm_yday and tm_isdst untouched. Even though the + * RTC has RTC_DAY_OF_WEEK, we ignore it, as it is only updated + * by the RTC when initially set to a non-zero value. + */ + spin_lock_irqsave(&priv->lock, flags); + save_control = ds1286_rtc_read(priv, RTC_CMD); + ds1286_rtc_write(priv, (save_control|RTC_TE), RTC_CMD); + + tm->tm_sec = ds1286_rtc_read(priv, RTC_SECONDS); + tm->tm_min = ds1286_rtc_read(priv, RTC_MINUTES); + tm->tm_hour = ds1286_rtc_read(priv, RTC_HOURS) & 0x3f; + tm->tm_mday = ds1286_rtc_read(priv, RTC_DATE); + tm->tm_mon = ds1286_rtc_read(priv, RTC_MONTH) & 0x1f; + tm->tm_year = ds1286_rtc_read(priv, RTC_YEAR); + + ds1286_rtc_write(priv, save_control, RTC_CMD); + spin_unlock_irqrestore(&priv->lock, flags); + + BCD_TO_BIN(tm->tm_sec); + BCD_TO_BIN(tm->tm_min); + BCD_TO_BIN(tm->tm_hour); + BCD_TO_BIN(tm->tm_mday); + BCD_TO_BIN(tm->tm_mon); + BCD_TO_BIN(tm->tm_year); + + /* + * Account for differences between how the RTC uses the values + * and how they are defined in a struct rtc_time; + */ + if (tm->tm_year < 45) + tm->tm_year += 30; + tm->tm_year += 40; + if (tm->tm_year < 70) + tm->tm_year += 100; + + tm->tm_mon--; + + return rtc_valid_tm(tm); +} + +static int ds1286_set_time(struct device *dev, struct rtc_time *tm) +{ + struct ds1286_priv *priv = dev_get_drvdata(dev); + unsigned char mon, day, hrs, min, sec, leap_yr; + unsigned char save_control; + unsigned int yrs; + unsigned long flags; + + + yrs = tm->tm_year + 1900; + mon = tm->tm_mon + 1; /* tm_mon starts at zero */ + day = tm->tm_mday; + hrs = tm->tm_hour; + min = tm->tm_min; + sec = tm->tm_sec; + + if (yrs < 1970) + return -EINVAL; + + leap_yr = ((!(yrs % 4) && (yrs % 100)) || !(yrs % 400)); + + if ((mon > 12) || (day == 0)) + return -EINVAL; + + if (day > (days_in_mo[mon] + ((mon == 2) && leap_yr))) + return -EINVAL; + + if ((hrs >= 24) || (min >= 60) || (sec >= 60)) + return -EINVAL; + + yrs -= 1940; + if (yrs > 255) /* They are unsigned */ + return -EINVAL; + + if (yrs >= 100) + yrs -= 100; + + BIN_TO_BCD(sec); + BIN_TO_BCD(min); + BIN_TO_BCD(hrs); + BIN_TO_BCD(day); + BIN_TO_BCD(mon); + BIN_TO_BCD(yrs); + + spin_lock_irqsave(&priv->lock, flags); + save_control = ds1286_rtc_read(priv, RTC_CMD); + ds1286_rtc_write(priv, (save_control|RTC_TE), RTC_CMD); + + ds1286_rtc_write(priv, yrs, RTC_YEAR); + ds1286_rtc_write(priv, mon, RTC_MONTH); + ds1286_rtc_write(priv, day, RTC_DATE); + ds1286_rtc_write(priv, hrs, RTC_HOURS); + ds1286_rtc_write(priv, min, RTC_MINUTES); + ds1286_rtc_write(priv, sec, RTC_SECONDS); + ds1286_rtc_write(priv, 0, RTC_HUNDREDTH_SECOND); + + ds1286_rtc_write(priv, save_control, RTC_CMD); + spin_unlock_irqrestore(&priv->lock, flags); + return 0; +} + +static int ds1286_read_alarm(struct device *dev, struct rtc_wkalrm *alm) +{ + struct ds1286_priv *priv = dev_get_drvdata(dev); + unsigned char cmd; + unsigned long flags; + + /* + * Only the values that we read from the RTC are set. That + * means only tm_wday, tm_hour, tm_min. + */ + spin_lock_irqsave(&priv->lock, flags); + alm->time.tm_min = ds1286_rtc_read(priv, RTC_MINUTES_ALARM) & 0x7f; + alm->time.tm_hour = ds1286_rtc_read(priv, RTC_HOURS_ALARM) & 0x1f; + alm->time.tm_wday = ds1286_rtc_read(priv, RTC_DAY_ALARM) & 0x07; + cmd = ds1286_rtc_read(priv, RTC_CMD); + spin_unlock_irqrestore(&priv->lock, flags); + + BCD_TO_BIN(alm->time.tm_min); + BCD_TO_BIN(alm->time.tm_hour); + alm->time.tm_sec = 0; + return 0; +} + +static int ds1286_set_alarm(struct device *dev, struct rtc_wkalrm *alm) +{ + struct ds1286_priv *priv = dev_get_drvdata(dev); + unsigned char hrs, min, sec; + + hrs = alm->time.tm_hour; + min = alm->time.tm_min; + sec = alm->time.tm_sec; + + if (hrs >= 24) + hrs = 0xff; + + if (min >= 60) + min = 0xff; + + if (sec != 0) + return -EINVAL; + + min = BIN2BCD(min); + hrs = BIN2BCD(hrs); + + spin_lock(&priv->lock); + ds1286_rtc_write(priv, hrs, RTC_HOURS_ALARM); + ds1286_rtc_write(priv, min, RTC_MINUTES_ALARM); + spin_unlock(&priv->lock); + + return 0; +} + +static const struct rtc_class_ops ds1286_ops = { + .ioctl = ds1286_ioctl, + .proc = ds1286_proc, + .read_time = ds1286_read_time, + .set_time = ds1286_set_time, + .read_alarm = ds1286_read_alarm, + .set_alarm = ds1286_set_alarm, +}; + +static int __devinit ds1286_probe(struct platform_device *pdev) +{ + struct rtc_device *rtc; + struct resource *res; + struct ds1286_priv *priv; + int ret = 0; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) + return -ENODEV; + priv = kzalloc(sizeof *priv, GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->size = res->end - res->start + 1; + if (!request_mem_region(res->start, priv->size, pdev->name)) { + ret = -EBUSY; + goto out; + } + priv->baseaddr = res->start; + priv->rtcregs = ioremap(priv->baseaddr, priv->size); + if (!priv->rtcregs) { + ret = -ENOMEM; + goto out; + } + spin_lock_init(&priv->lock); + rtc = rtc_device_register("ds1286", &pdev->dev, + &ds1286_ops, THIS_MODULE); + if (IS_ERR(rtc)) { + ret = PTR_ERR(rtc); + goto out; + } + priv->rtc = rtc; + platform_set_drvdata(pdev, priv); + return 0; + +out: + if (priv->rtc) + rtc_device_unregister(priv->rtc); + if (priv->rtcregs) + iounmap(priv->rtcregs); + if (priv->baseaddr) + release_mem_region(priv->baseaddr, priv->size); + kfree(priv); + return ret; +} + +static int __devexit ds1286_remove(struct platform_device *pdev) +{ + struct ds1286_priv *priv = platform_get_drvdata(pdev); + + rtc_device_unregister(priv->rtc); + iounmap(priv->rtcregs); + release_mem_region(priv->baseaddr, priv->size); + kfree(priv); + return 0; +} + +static struct platform_driver ds1286_platform_driver = { + .driver = { + .name = "rtc-ds1286", + .owner = THIS_MODULE, + }, + .probe = ds1286_probe, + .remove = __devexit_p(ds1286_remove), +}; + +static int __init ds1286_init(void) +{ + return platform_driver_register(&ds1286_platform_driver); +} + +static void __exit ds1286_exit(void) +{ + platform_driver_unregister(&ds1286_platform_driver); +} + +MODULE_AUTHOR("Thomas Bogendoerfer "); +MODULE_DESCRIPTION("DS1286 RTC driver"); +MODULE_LICENSE("GPL"); +MODULE_VERSION(DRV_VERSION); +MODULE_ALIAS("platform:rtc-ds1286"); + +module_init(ds1286_init); +module_exit(ds1286_exit); From ralf@linux-mips.org Sun Aug 3 23:20:37 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 03 Aug 2008 23:20:46 +0100 (BST) Received: from ditditdahdahdah-dahdahdahditdit.dl5rb.org.uk ([217.169.26.28]:7881 "EHLO ditditdahdahdah-dahdahdahditdit.dl5rb.org.uk") by ftp.linux-mips.org with ESMTP id S20026644AbYHCWUh (ORCPT ); Sun, 3 Aug 2008 23:20:37 +0100 Received: from denk.linux-mips.net (denk.linux-mips.net [127.0.0.1]) by ditditdahdahdah-dahdahdahditdit.dl5rb.org.uk (8.14.2/8.14.1) with ESMTP id m73MKT8u015055; Sun, 3 Aug 2008 23:20:29 +0100 Received: (from ralf@localhost) by denk.linux-mips.net (8.14.2/8.14.2/Submit) id m73MKRnx015054; Sun, 3 Aug 2008 23:20:27 +0100 Date: Sun, 3 Aug 2008 23:20:27 +0100 From: Ralf Baechle To: Thomas Bogendoerfer Cc: rtc-linux@googlegroups.com, linux-mips@linux-mips.org, a.zummo@towertech.it Subject: Re: [PATCH] DS1286: new RTC driver Message-ID: <20080803222027.GA14674@linux-mips.org> References: <20080803174137.AF8071DA6F4@solo.franken.de> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20080803174137.AF8071DA6F4@solo.franken.de> User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20082 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Sun, Aug 03, 2008 at 07:41:37PM +0200, Thomas Bogendoerfer wrote: > This driver replaces the broken DS1286 driver in drivers/char and > gives back RTC support for SGI IP22 and IP28 machines. > > Signed-off-by: Thomas Bogendoerfer Acked-by: Ralf Baechle I would like to see this driver to go into 2.6.27. A while ago MIPS has switched to rtc_class resulting not yet updated platforms such as IP22 to fail to build. Ralf From anemo@mba.ocn.ne.jp Mon Aug 4 02:52:00 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 04 Aug 2008 02:52:11 +0100 (BST) Received: from topsns2.toshiba-tops.co.jp ([202.230.225.126]:57314 "EHLO topsns2.toshiba-tops.co.jp") by ftp.linux-mips.org with ESMTP id S20033935AbYHDBwA (ORCPT ); Mon, 4 Aug 2008 02:52:00 +0100 Received: from no.name.available by topsns2.toshiba-tops.co.jp via smtpd (for ftp.linux-mips.org [213.58.128.207]) with ESMTP; Mon, 4 Aug 2008 10:51:58 +0900 Received: from topsms.toshiba-tops.co.jp (localhost.localdomain [127.0.0.1]) by localhost.toshiba-tops.co.jp (Postfix) with ESMTP id AD58042B17; Mon, 4 Aug 2008 10:51:52 +0900 (JST) Received: from srd2sd.toshiba-tops.co.jp (srd2sd.toshiba-tops.co.jp [172.17.28.2]) by topsms.toshiba-tops.co.jp (Postfix) with ESMTP id A24CF1CE88; Mon, 4 Aug 2008 10:51:52 +0900 (JST) Received: from localhost (fragile [172.17.28.65]) by srd2sd.toshiba-tops.co.jp (8.12.10/8.12.10) with ESMTP id m741ppfl049801; Mon, 4 Aug 2008 10:51:51 +0900 (JST) (envelope-from anemo@mba.ocn.ne.jp) Date: Mon, 04 Aug 2008 10:51:51 +0900 (JST) Message-Id: <20080804.105151.213759441.nemoto@toshiba-tops.co.jp> To: tsbogend@alpha.franken.de Cc: rtc-linux@googlegroups.com, linux-mips@linux-mips.org, a.zummo@towertech.it, ralf@linux-mips.org Subject: Re: [PATCH] M48T35: new RTC driver From: Atsushi Nemoto In-Reply-To: <20080803174140.797B51DA6F4@solo.franken.de> References: <20080803174140.797B51DA6F4@solo.franken.de> X-Fingerprint: 6ACA 1623 39BD 9A94 9B1A B746 CA77 FE94 2874 D52F X-Pgp-Public-Key: http://wwwkeys.pgp.net/pks/lookup?op=get&search=0x2874D52F X-Mailer: Mew version 6.1 on Emacs 22.2 / Mule 5.0 (SAKAKI) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20083 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anemo@mba.ocn.ne.jp Precedence: bulk X-list: linux-mips On Sun, 3 Aug 2008 19:41:40 +0200 (CEST), Thomas Bogendoerfer wrote: > This driver replaces the broken ip27-rtc driver in drivers/char and > gives back RTC support for SGI IP27 machines. ... > +config RTC_DRV_M48T35 > + tristate "ST M48T35" > + depends on SGI_IP27 Is this driver really IP27 specific? Let's make drivers generic as possible. > + if (yrs < 1970) > + return -EINVAL; > + > + leap_yr = ((!(yrs % 4) && (yrs % 100)) || !(yrs % 400)); > + > + if ((mon > 12) || (day == 0)) > + return -EINVAL; > + > + if (day > (days_in_mo[mon] + ((mon == 2) && leap_yr))) > + return -EINVAL; > + > + if ((hrs >= 24) || (min >= 60) || (sec >= 60)) > + return -EINVAL; rtc_valid_tm() can be used? > + if (!request_mem_region(res->start, priv->size, pdev->name)) { > + ret = -EBUSY; > + goto out; > + } > + priv->baseaddr = res->start; > + priv->reg = (struct m48t35_rtc __iomem *)res->start; It seems priv->baseaddr is a physical address and priv->reg is a virtual address. ioremap() is not needed? --- Atsushi Nemoto From tsbogend@alpha.franken.de Mon Aug 4 08:49:28 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 04 Aug 2008 08:49:35 +0100 (BST) Received: from elvis.franken.de ([193.175.24.41]:19349 "EHLO elvis.franken.de") by ftp.linux-mips.org with ESMTP id S20025364AbYHDHt2 (ORCPT ); Mon, 4 Aug 2008 08:49:28 +0100 Received: from uucp (helo=solo.franken.de) by elvis.franken.de with local-bsmtp (Exim 3.36 #1) id 1KPuoo-0002S9-00; Mon, 04 Aug 2008 09:49:26 +0200 Received: by solo.franken.de (Postfix, from userid 1000) id B1FF4C2EA8; Mon, 4 Aug 2008 09:49:09 +0200 (CEST) Date: Mon, 4 Aug 2008 09:49:09 +0200 To: Atsushi Nemoto Cc: rtc-linux@googlegroups.com, linux-mips@linux-mips.org, a.zummo@towertech.it, ralf@linux-mips.org Subject: Re: [PATCH] M48T35: new RTC driver Message-ID: <20080804074909.GA5760@alpha.franken.de> References: <20080803174140.797B51DA6F4@solo.franken.de> <20080804.105151.213759441.nemoto@toshiba-tops.co.jp> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20080804.105151.213759441.nemoto@toshiba-tops.co.jp> User-Agent: Mutt/1.5.13 (2006-08-11) From: tsbogend@alpha.franken.de (Thomas Bogendoerfer) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20084 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: tsbogend@alpha.franken.de Precedence: bulk X-list: linux-mips On Mon, Aug 04, 2008 at 10:51:51AM +0900, Atsushi Nemoto wrote: > On Sun, 3 Aug 2008 19:41:40 +0200 (CEST), Thomas Bogendoerfer wrote: > > This driver replaces the broken ip27-rtc driver in drivers/char and > > gives back RTC support for SGI IP27 machines. > ... > > +config RTC_DRV_M48T35 > > + tristate "ST M48T35" > > + depends on SGI_IP27 > > Is this driver really IP27 specific? Let's make drivers generic as > possible. ok, will change that. > > + if ((hrs >= 24) || (min >= 60) || (sec >= 60)) > > + return -EINVAL; > > rtc_valid_tm() can be used? good idea. > > + priv->baseaddr = res->start; > > + priv->reg = (struct m48t35_rtc __iomem *)res->start; > > It seems priv->baseaddr is a physical address and priv->reg is a > virtual address. ioremap() is not needed? I've misued res->start to pass the pointer, which was used by the old rtc driver. I'll switch over to pass a physical address and add ioremap code. Thomas. -- Crap can work. Given enough thrust pigs will fly, but it's not necessary a good idea. [ RFC1925, 2.3 ] From khickey@rmicorp.com Mon Aug 4 15:06:44 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 04 Aug 2008 15:06:50 +0100 (BST) Received: from mx1.razamicroelectronics.com ([63.111.213.197]:18966 "EHLO hq-ex-mb01.razamicroelectronics.com") by ftp.linux-mips.org with ESMTP id S20039354AbYHDOGo (ORCPT ); Mon, 4 Aug 2008 15:06:44 +0100 Received: from sark.razamicroelectronics.com ([10.8.0.254]) by hq-ex-mb01.razamicroelectronics.com with Microsoft SMTPSVC(6.0.3790.3959); Mon, 4 Aug 2008 07:06:34 -0700 Received: from localhost.localdomain (unknown [10.8.0.25]) by sark.razamicroelectronics.com (Postfix) with ESMTP id D913A6DA53C; Mon, 4 Aug 2008 08:58:57 -0500 (CDT) From: Kevin Hickey To: ralf@linux-mips.org Cc: linux-mips@linux-mips.org, Kevin Hickey Subject: [PATCH] [MIPS] Update defconfigs for Alchemy devel boards Date: Mon, 4 Aug 2008 09:06:48 -0500 Message-Id: <1217858808-31696-1-git-send-email-khickey@rmicorp.com> X-Mailer: git-send-email 1.5.4.3 In-Reply-To: <> References: <> X-OriginalArrivalTime: 04 Aug 2008 14:06:34.0675 (UTC) FILETIME=[4DAD1030:01C8F63B] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20085 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: khickey@rmicorp.com Precedence: bulk X-list: linux-mips The defconfigs for the Alchemy development boards were well out of date and generating warnings. They have been updated to be warning-free under 2.6.27-rc1 and network boot with NFS root support has been added to db1200_defconfig. Signed-off-by: Kevin Hickey --- arch/mips/configs/db1200_defconfig | 700 +++++++++++++++++------------------- arch/mips/configs/db1550_defconfig | 661 ++++++++++++++++------------------ arch/mips/configs/pb1550_defconfig | 659 ++++++++++++++++------------------ 3 files changed, 934 insertions(+), 1086 deletions(-) diff --git a/arch/mips/configs/db1200_defconfig b/arch/mips/configs/db1200_defconfig index ab17973..de8a34f 100644 --- a/arch/mips/configs/db1200_defconfig +++ b/arch/mips/configs/db1200_defconfig @@ -1,79 +1,90 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.20 -# Tue Feb 20 21:47:25 2007 +# Linux kernel version: 2.6.27-rc1 +# Fri Aug 1 22:06:09 2008 # CONFIG_MIPS=y # # Machine selection # -CONFIG_ZONE_DMA=y CONFIG_MACH_ALCHEMY=y -# CONFIG_MIPS_MTX1 is not set -# CONFIG_MIPS_BOSPORUS is not set -# CONFIG_MIPS_PB1000 is not set -# CONFIG_MIPS_PB1100 is not set -# CONFIG_MIPS_PB1500 is not set -# CONFIG_MIPS_PB1550 is not set -# CONFIG_MIPS_PB1200 is not set -# CONFIG_MIPS_DB1000 is not set -# CONFIG_MIPS_DB1100 is not set -# CONFIG_MIPS_DB1500 is not set -# CONFIG_MIPS_DB1550 is not set -CONFIG_MIPS_DB1200=y -# CONFIG_MIPS_MIRAGE is not set # CONFIG_BASLER_EXCITE is not set +# CONFIG_BCM47XX is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set +# CONFIG_LASAT is not set +# CONFIG_LEMOTE_FULONG is not set # CONFIG_MIPS_MALTA is not set -# CONFIG_WR_PPMC is not set # CONFIG_MIPS_SIM is not set -# CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_MIPS_XXS1500 is not set +# CONFIG_MARKEINS is not set +# CONFIG_MACH_VR41XX is not set # CONFIG_PNX8550_JBS is not set # CONFIG_PNX8550_STB810 is not set -# CONFIG_MACH_VR41XX is not set +# CONFIG_PMC_MSP is not set # CONFIG_PMC_YOSEMITE is not set -# CONFIG_MARKEINS is not set # CONFIG_SGI_IP22 is not set # CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP28 is not set # CONFIG_SGI_IP32 is not set -# CONFIG_SIBYTE_BIGSUR is not set -# CONFIG_SIBYTE_SWARM is not set -# CONFIG_SIBYTE_SENTOSA is not set -# CONFIG_SIBYTE_RHONE is not set -# CONFIG_SIBYTE_CARMEL is not set -# CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CARMEL is not set # CONFIG_SIBYTE_CRHONE is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_BIGSUR is not set # CONFIG_SNI_RM is not set -# CONFIG_TOSHIBA_JMR3927 is not set -# CONFIG_TOSHIBA_RBTX4927 is not set -# CONFIG_TOSHIBA_RBTX4938 is not set +# CONFIG_MACH_TX49XX is not set +# CONFIG_MIKROTIK_RB532 is not set +# CONFIG_WR_PPMC is not set +# CONFIG_MIPS_MTX1 is not set +# CONFIG_MIPS_BOSPORUS is not set +# CONFIG_MIPS_DB1000 is not set +# CONFIG_MIPS_DB1100 is not set +CONFIG_MIPS_DB1200=y +# CONFIG_MIPS_DB1500 is not set +# CONFIG_MIPS_DB1550 is not set +# CONFIG_MIPS_MIRAGE is not set +# CONFIG_MIPS_PB1000 is not set +# CONFIG_MIPS_PB1100 is not set +# CONFIG_MIPS_PB1200 is not set +# CONFIG_MIPS_PB1500 is not set +# CONFIG_MIPS_PB1550 is not set +# CONFIG_MIPS_XXS1500 is not set +CONFIG_SOC_AU1200=y +CONFIG_SOC_AU1X00=y CONFIG_RWSEM_GENERIC_SPINLOCK=y # CONFIG_ARCH_HAS_ILOG2_U32 is not set # CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_ARCH_SUPPORTS_OPROFILE=y CONFIG_GENERIC_FIND_NEXT_BIT=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_CLOCKEVENTS=y CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CMOS_UPDATE=y CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y # CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ is not set +CONFIG_CEVT_R4K=y +CONFIG_CSRC_R4K=y CONFIG_DMA_COHERENT=y +# CONFIG_HOTPLUG_CPU is not set CONFIG_MIPS_DISABLE_OBSOLETE_IDE=y +# CONFIG_NO_IOPORT is not set # CONFIG_CPU_BIG_ENDIAN is not set CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_SYS_SUPPORTS_APM_EMULATION=y CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y -CONFIG_SOC_AU1200=y -CONFIG_SOC_AU1X00=y +CONFIG_IRQ_CPU=y CONFIG_MIPS_L1_CACHE_SHIFT=5 # # CPU selection # +# CONFIG_CPU_LOONGSON2 is not set CONFIG_CPU_MIPS32_R1=y # CONFIG_CPU_MIPS32_R2 is not set # CONFIG_CPU_MIPS64_R1 is not set @@ -112,7 +123,6 @@ CONFIG_CPU_HAS_PREFETCH=y CONFIG_MIPS_MT_DISABLED=y # CONFIG_MIPS_MT_SMP is not set # CONFIG_MIPS_MT_SMTC is not set -# CONFIG_MIPS_VPE_LOADER is not set CONFIG_64BIT_PHYS_ADDR=y CONFIG_CPU_HAS_LLSC=y CONFIG_CPU_HAS_SYNC=y @@ -120,6 +130,7 @@ CONFIG_GENERIC_HARDIRQS=y CONFIG_GENERIC_IRQ_PROBE=y CONFIG_CPU_SUPPORTS_HIGHMEM=y CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_ARCH_POPULATES_NODE_MAP=y CONFIG_SELECT_MEMORY_MODEL=y CONFIG_FLATMEM_MANUAL=y # CONFIG_DISCONTIGMEM_MANUAL is not set @@ -127,9 +138,16 @@ CONFIG_FLATMEM_MANUAL=y CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y # CONFIG_SPARSEMEM_STATIC is not set +# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set +CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 # CONFIG_RESOURCES_64BIT is not set -CONFIG_ZONE_DMA_FLAG=1 +CONFIG_ZONE_DMA_FLAG=0 +CONFIG_VIRT_TO_BUS=y +# CONFIG_TICK_ONESHOT is not set +# CONFIG_NO_HZ is not set +# CONFIG_HIGH_RES_TIMERS is not set +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y # CONFIG_HZ_48 is not set # CONFIG_HZ_100 is not set # CONFIG_HZ_128 is not set @@ -143,73 +161,91 @@ CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set # CONFIG_KEXEC is not set +CONFIG_SECCOMP=y CONFIG_LOCKDEP_SUPPORT=y CONFIG_STACKTRACE_SUPPORT=y CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" # -# Code maturity level options +# General setup # CONFIG_EXPERIMENTAL=y CONFIG_BROKEN_ON_SMP=y CONFIG_INIT_ENV_ARG_LIMIT=32 - -# -# General setup -# CONFIG_LOCALVERSION="" CONFIG_LOCALVERSION_AUTO=y CONFIG_SWAP=y CONFIG_SYSVIPC=y -# CONFIG_IPC_NS is not set CONFIG_SYSVIPC_SYSCTL=y # CONFIG_POSIX_MQUEUE is not set # CONFIG_BSD_PROCESS_ACCT is not set # CONFIG_TASKSTATS is not set -# CONFIG_UTS_NS is not set # CONFIG_AUDIT is not set CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_CGROUPS is not set +# CONFIG_GROUP_SCHED is not set CONFIG_SYSFS_DEPRECATED=y +CONFIG_SYSFS_DEPRECATED_V2=y # CONFIG_RELAY is not set +# CONFIG_NAMESPACES is not set +# CONFIG_BLK_DEV_INITRD is not set # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set CONFIG_SYSCTL=y CONFIG_EMBEDDED=y CONFIG_SYSCTL_SYSCALL=y +CONFIG_SYSCTL_SYSCALL_CHECK=y CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_EXTRA_PASS is not set CONFIG_HOTPLUG=y CONFIG_PRINTK=y CONFIG_BUG=y CONFIG_ELF_CORE=y +CONFIG_PCSPKR_PLATFORM=y +CONFIG_COMPAT_BRK=y CONFIG_BASE_FULL=y CONFIG_FUTEX=y +CONFIG_ANON_INODES=y CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y CONFIG_SHMEM=y -CONFIG_SLAB=y CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +# CONFIG_MARKERS is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set +# CONFIG_HAVE_IOREMAP_PROT is not set +# CONFIG_HAVE_KPROBES is not set +# CONFIG_HAVE_KRETPROBES is not set +# CONFIG_HAVE_ARCH_TRACEHOOK is not set +# CONFIG_HAVE_DMA_ATTRS is not set +# CONFIG_USE_GENERIC_SMP_HELPERS is not set +# CONFIG_HAVE_CLK is not set +CONFIG_PROC_PAGE_MONITOR=y +# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set +CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y # CONFIG_TINY_SHMEM is not set CONFIG_BASE_SMALL=0 -# CONFIG_SLOB is not set - -# -# Loadable module support -# CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set CONFIG_MODULE_UNLOAD=y # CONFIG_MODULE_FORCE_UNLOAD is not set CONFIG_MODVERSIONS=y CONFIG_MODULE_SRCVERSION_ALL=y CONFIG_KMOD=y - -# -# Block layer -# CONFIG_BLOCK=y # CONFIG_LBD is not set # CONFIG_BLK_DEV_IO_TRACE is not set # CONFIG_LSF is not set +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set # # IO Schedulers @@ -223,15 +259,13 @@ CONFIG_DEFAULT_AS=y # CONFIG_DEFAULT_CFQ is not set # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="anticipatory" +CONFIG_CLASSIC_RCU=y # # Bus options (PCI, PCMCIA, EISA, ISA, TC) # +# CONFIG_ARCH_SUPPORTS_MSI is not set CONFIG_MMU=y - -# -# PCCARD (PCMCIA/CardBus) support -# CONFIG_PCCARD=m # CONFIG_PCMCIA_DEBUG is not set CONFIG_PCMCIA=m @@ -244,10 +278,6 @@ CONFIG_PCMCIA_IOCTL=y CONFIG_PCMCIA_AU1X00=m # -# PCI Hotplug Support -# - -# # Executable file formats # CONFIG_BINFMT_ELF=y @@ -257,17 +287,13 @@ CONFIG_TRAD_SIGNALS=y # # Power management options # +CONFIG_ARCH_SUSPEND_POSSIBLE=y # CONFIG_PM is not set - -# -# Networking -# CONFIG_NET=y # # Networking options # -# CONFIG_NETDEBUG is not set CONFIG_PACKET=y # CONFIG_PACKET_MMAP is not set CONFIG_UNIX=y @@ -275,13 +301,17 @@ CONFIG_XFRM=y CONFIG_XFRM_USER=m # CONFIG_XFRM_SUB_POLICY is not set CONFIG_XFRM_MIGRATE=y +# CONFIG_XFRM_STATISTICS is not set CONFIG_NET_KEY=y CONFIG_NET_KEY_MIGRATE=y CONFIG_INET=y CONFIG_IP_MULTICAST=y # CONFIG_IP_ADVANCED_ROUTER is not set CONFIG_IP_FIB_HASH=y -# CONFIG_IP_PNP is not set +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +# CONFIG_IP_PNP_RARP is not set # CONFIG_NET_IPIP is not set # CONFIG_NET_IPGRE is not set # CONFIG_IP_MROUTE is not set @@ -295,38 +325,34 @@ CONFIG_IP_FIB_HASH=y CONFIG_INET_XFRM_MODE_TRANSPORT=m CONFIG_INET_XFRM_MODE_TUNNEL=m CONFIG_INET_XFRM_MODE_BEET=m +# CONFIG_INET_LRO is not set CONFIG_INET_DIAG=y CONFIG_INET_TCP_DIAG=y # CONFIG_TCP_CONG_ADVANCED is not set CONFIG_TCP_CONG_CUBIC=y CONFIG_DEFAULT_TCP_CONG="cubic" CONFIG_TCP_MD5SIG=y - -# -# IP: Virtual Server Configuration -# # CONFIG_IP_VS is not set # CONFIG_IPV6 is not set -# CONFIG_INET6_XFRM_TUNNEL is not set -# CONFIG_INET6_TUNNEL is not set CONFIG_NETWORK_SECMARK=y CONFIG_NETFILTER=y # CONFIG_NETFILTER_DEBUG is not set +CONFIG_NETFILTER_ADVANCED=y # # Core Netfilter Configuration # -# CONFIG_NETFILTER_NETLINK is not set -CONFIG_NF_CONNTRACK_ENABLED=m -CONFIG_NF_CONNTRACK_SUPPORT=y -# CONFIG_IP_NF_CONNTRACK_SUPPORT is not set +# CONFIG_NETFILTER_NETLINK_QUEUE is not set +# CONFIG_NETFILTER_NETLINK_LOG is not set CONFIG_NF_CONNTRACK=m CONFIG_NF_CT_ACCT=y CONFIG_NF_CONNTRACK_MARK=y CONFIG_NF_CONNTRACK_SECMARK=y CONFIG_NF_CONNTRACK_EVENTS=y +# CONFIG_NF_CT_PROTO_DCCP is not set CONFIG_NF_CT_PROTO_GRE=m CONFIG_NF_CT_PROTO_SCTP=m +# CONFIG_NF_CT_PROTO_UDPLITE is not set CONFIG_NF_CONNTRACK_AMANDA=m CONFIG_NF_CONNTRACK_FTP=m CONFIG_NF_CONNTRACK_H323=m @@ -336,36 +362,44 @@ CONFIG_NF_CONNTRACK_PPTP=m CONFIG_NF_CONNTRACK_SANE=m CONFIG_NF_CONNTRACK_SIP=m CONFIG_NF_CONNTRACK_TFTP=m +# CONFIG_NF_CT_NETLINK is not set CONFIG_NETFILTER_XTABLES=m CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m CONFIG_NETFILTER_XT_TARGET_MARK=m CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m CONFIG_NETFILTER_XT_TARGET_NFLOG=m +# CONFIG_NETFILTER_XT_TARGET_RATEEST is not set CONFIG_NETFILTER_XT_TARGET_SECMARK=m CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=m CONFIG_NETFILTER_XT_TARGET_TCPMSS=m CONFIG_NETFILTER_XT_MATCH_COMMENT=m CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m +# CONFIG_NETFILTER_XT_MATCH_CONNLIMIT is not set CONFIG_NETFILTER_XT_MATCH_CONNMARK=m CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m CONFIG_NETFILTER_XT_MATCH_DCCP=m CONFIG_NETFILTER_XT_MATCH_DSCP=m CONFIG_NETFILTER_XT_MATCH_ESP=m CONFIG_NETFILTER_XT_MATCH_HELPER=m +# CONFIG_NETFILTER_XT_MATCH_IPRANGE is not set CONFIG_NETFILTER_XT_MATCH_LENGTH=m CONFIG_NETFILTER_XT_MATCH_LIMIT=m CONFIG_NETFILTER_XT_MATCH_MAC=m CONFIG_NETFILTER_XT_MATCH_MARK=m +# CONFIG_NETFILTER_XT_MATCH_OWNER is not set CONFIG_NETFILTER_XT_MATCH_POLICY=m CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m CONFIG_NETFILTER_XT_MATCH_QUOTA=m +# CONFIG_NETFILTER_XT_MATCH_RATEEST is not set CONFIG_NETFILTER_XT_MATCH_REALM=m CONFIG_NETFILTER_XT_MATCH_SCTP=m CONFIG_NETFILTER_XT_MATCH_STATE=m CONFIG_NETFILTER_XT_MATCH_STATISTIC=m CONFIG_NETFILTER_XT_MATCH_STRING=m CONFIG_NETFILTER_XT_MATCH_TCPMSS=m +# CONFIG_NETFILTER_XT_MATCH_TIME is not set +# CONFIG_NETFILTER_XT_MATCH_U32 is not set CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m # @@ -376,20 +410,13 @@ CONFIG_NF_CONNTRACK_PROC_COMPAT=y # CONFIG_IP_NF_QUEUE is not set # CONFIG_IP_NF_IPTABLES is not set # CONFIG_IP_NF_ARPTABLES is not set - -# -# DCCP Configuration (EXPERIMENTAL) -# # CONFIG_IP_DCCP is not set - -# -# SCTP Configuration (EXPERIMENTAL) -# -# CONFIG_IP_SCTP is not set - -# -# TIPC Configuration (EXPERIMENTAL) -# +CONFIG_IP_SCTP=m +# CONFIG_SCTP_DBG_MSG is not set +# CONFIG_SCTP_DBG_OBJCNT is not set +# CONFIG_SCTP_HMAC_NONE is not set +# CONFIG_SCTP_HMAC_SHA1 is not set +CONFIG_SCTP_HMAC_MD5=y # CONFIG_TIPC is not set # CONFIG_ATM is not set # CONFIG_BRIDGE is not set @@ -402,10 +429,6 @@ CONFIG_NF_CONNTRACK_PROC_COMPAT=y # CONFIG_LAPB is not set # CONFIG_ECONET is not set # CONFIG_WAN_ROUTER is not set - -# -# QoS and/or fair queueing -# # CONFIG_NET_SCHED is not set CONFIG_NET_CLS_ROUTE=y @@ -414,9 +437,20 @@ CONFIG_NET_CLS_ROUTE=y # # CONFIG_NET_PKTGEN is not set # CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set # CONFIG_IRDA is not set # CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set + +# +# Wireless +# +# CONFIG_CFG80211 is not set +# CONFIG_WIRELESS_EXT is not set +# CONFIG_MAC80211 is not set # CONFIG_IEEE80211 is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set # # Device Drivers @@ -425,25 +459,21 @@ CONFIG_NET_CLS_ROUTE=y # # Generic Driver Options # +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_STANDALONE=y CONFIG_PREVENT_FIRMWARE_BUILD=y CONFIG_FW_LOADER=y +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" # CONFIG_SYS_HYPERVISOR is not set - -# -# Connector - unified userspace <-> kernelspace linker -# # CONFIG_CONNECTOR is not set - -# -# Memory Technology Devices (MTD) -# CONFIG_MTD=y # CONFIG_MTD_DEBUG is not set # CONFIG_MTD_CONCAT is not set CONFIG_MTD_PARTITIONS=y # CONFIG_MTD_REDBOOT_PARTS is not set # CONFIG_MTD_CMDLINE_PARTS is not set +# CONFIG_MTD_AR7_PARTS is not set # # User Modules And Translation Layers @@ -456,6 +486,7 @@ CONFIG_MTD_BLOCK=y # CONFIG_INFTL is not set # CONFIG_RFD_FTL is not set # CONFIG_SSFDC is not set +# CONFIG_MTD_OOPS is not set # # RAM/ROM/Flash chip drivers @@ -481,7 +512,6 @@ CONFIG_MTD_CFI_UTIL=y # CONFIG_MTD_RAM is not set # CONFIG_MTD_ROM is not set # CONFIG_MTD_ABSENT is not set -# CONFIG_MTD_OBSOLETE_CHIPS is not set # # Mapping drivers for chip access @@ -505,36 +535,23 @@ CONFIG_MTD_ALCHEMY=y # CONFIG_MTD_DOC2000 is not set # CONFIG_MTD_DOC2001 is not set # CONFIG_MTD_DOC2001PLUS is not set - -# -# NAND Flash Device Drivers -# CONFIG_MTD_NAND=y # CONFIG_MTD_NAND_VERIFY_WRITE is not set # CONFIG_MTD_NAND_ECC_SMC is not set +# CONFIG_MTD_NAND_MUSEUM_IDS is not set CONFIG_MTD_NAND_IDS=y # CONFIG_MTD_NAND_AU1550 is not set # CONFIG_MTD_NAND_DISKONCHIP is not set # CONFIG_MTD_NAND_NANDSIM is not set - -# -# OneNAND Flash Device Drivers -# +# CONFIG_MTD_NAND_PLATFORM is not set # CONFIG_MTD_ONENAND is not set # -# Parallel port support +# UBI - Unsorted block images # +# CONFIG_MTD_UBI is not set # CONFIG_PARPORT is not set - -# -# Plug and Play support -# -# CONFIG_PNPACPI is not set - -# -# Block devices -# +CONFIG_BLK_DEV=y # CONFIG_BLK_DEV_COW_COMMON is not set CONFIG_BLK_DEV_LOOP=y # CONFIG_BLK_DEV_CRYPTOLOOP is not set @@ -542,24 +559,20 @@ CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_COUNT=16 CONFIG_BLK_DEV_RAM_SIZE=4096 -CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024 -# CONFIG_BLK_DEV_INITRD is not set +# CONFIG_BLK_DEV_XIP is not set # CONFIG_CDROM_PKTCDVD is not set # CONFIG_ATA_OVER_ETH is not set - -# -# Misc devices -# - -# -# ATA/ATAPI/MFM/RLL support -# +# CONFIG_BLK_DEV_HD is not set +CONFIG_MISC_DEVICES=y +# CONFIG_EEPROM_93CX6 is not set +# CONFIG_ENCLOSURE_SERVICES is not set +CONFIG_HAVE_IDE=y CONFIG_IDE=y CONFIG_IDE_MAX_HWIFS=4 CONFIG_BLK_DEV_IDE=y # -# Please see Documentation/ide.txt for help/info on IDE drives +# Please see Documentation/ide/ide.txt for help/info on IDE drives # # CONFIG_BLK_DEV_IDE_SATA is not set CONFIG_BLK_DEV_IDEDISK=y @@ -570,25 +583,25 @@ CONFIG_BLK_DEV_IDECS=m # CONFIG_BLK_DEV_IDEFLOPPY is not set # CONFIG_BLK_DEV_IDESCSI is not set # CONFIG_IDE_TASK_IOCTL is not set +CONFIG_IDE_PROC_FS=y # # IDE chipset support/bugfixes # CONFIG_IDE_GENERIC=y +# CONFIG_BLK_DEV_PLATFORM is not set CONFIG_BLK_DEV_IDE_AU1XXX=y CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA=y # CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA is not set CONFIG_BLK_DEV_IDE_AU1XXX_SEQTS_PER_RQ=128 -# CONFIG_IDE_ARM is not set # CONFIG_BLK_DEV_IDEDMA is not set -# CONFIG_IDEDMA_AUTO is not set -# CONFIG_BLK_DEV_HD is not set # # SCSI device support # # CONFIG_RAID_ATTRS is not set CONFIG_SCSI=y +CONFIG_SCSI_DMA=y CONFIG_SCSI_TGT=m # CONFIG_SCSI_NETLINK is not set CONFIG_SCSI_PROC_FS=y @@ -611,6 +624,7 @@ CONFIG_SCSI_MULTI_LUN=y # CONFIG_SCSI_CONSTANTS is not set # CONFIG_SCSI_LOGGING is not set CONFIG_SCSI_SCAN_ASYNC=y +CONFIG_SCSI_WAIT_SCAN=m # # SCSI Transports @@ -618,111 +632,51 @@ CONFIG_SCSI_SCAN_ASYNC=y # CONFIG_SCSI_SPI_ATTRS is not set # CONFIG_SCSI_FC_ATTRS is not set # CONFIG_SCSI_ISCSI_ATTRS is not set -# CONFIG_SCSI_SAS_ATTRS is not set # CONFIG_SCSI_SAS_LIBSAS is not set - -# -# SCSI low-level drivers -# +# CONFIG_SCSI_SRP_ATTRS is not set +CONFIG_SCSI_LOWLEVEL=y # CONFIG_ISCSI_TCP is not set # CONFIG_SCSI_DEBUG is not set - -# -# PCMCIA SCSI adapter support -# -# CONFIG_PCMCIA_AHA152X is not set -# CONFIG_PCMCIA_FDOMAIN is not set -# CONFIG_PCMCIA_NINJA_SCSI is not set -# CONFIG_PCMCIA_QLOGIC is not set -# CONFIG_PCMCIA_SYM53C500 is not set - -# -# Serial ATA (prod) and Parallel ATA (experimental) drivers -# +# CONFIG_SCSI_LOWLEVEL_PCMCIA is not set +# CONFIG_SCSI_DH is not set # CONFIG_ATA is not set - -# -# Multi-device support (RAID and LVM) -# # CONFIG_MD is not set - -# -# Fusion MPT device support -# -# CONFIG_FUSION is not set - -# -# IEEE 1394 (FireWire) support -# - -# -# I2O device support -# - -# -# Network device support -# CONFIG_NETDEVICES=y # CONFIG_DUMMY is not set # CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set # CONFIG_EQUALIZER is not set # CONFIG_TUN is not set - -# -# PHY device support -# +# CONFIG_VETH is not set # CONFIG_PHYLIB is not set - -# -# Ethernet (10 or 100Mbit) -# CONFIG_NET_ETHERNET=y -CONFIG_MII=m +CONFIG_MII=y +# CONFIG_AX88796 is not set # CONFIG_MIPS_AU1X00_ENET is not set -# CONFIG_SMC91X is not set +CONFIG_SMC91X=y # CONFIG_DM9000 is not set +# CONFIG_IBM_NEW_EMAC_ZMII is not set +# CONFIG_IBM_NEW_EMAC_RGMII is not set +# CONFIG_IBM_NEW_EMAC_TAH is not set +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set +# CONFIG_B44 is not set +CONFIG_NETDEV_1000=y +CONFIG_NETDEV_10000=y # -# Ethernet (1000 Mbit) -# - -# -# Ethernet (10000 Mbit) -# - -# -# Token Ring devices -# - -# -# Wireless LAN (non-hamradio) -# -# CONFIG_NET_RADIO is not set - -# -# PCMCIA network device support +# Wireless LAN # +# CONFIG_WLAN_PRE80211 is not set +# CONFIG_WLAN_80211 is not set +# CONFIG_IWLWIFI_LEDS is not set # CONFIG_NET_PCMCIA is not set - -# -# Wan interfaces -# # CONFIG_WAN is not set # CONFIG_PPP is not set # CONFIG_SLIP is not set -# CONFIG_SHAPER is not set # CONFIG_NETCONSOLE is not set # CONFIG_NETPOLL is not set # CONFIG_NET_POLL_CONTROLLER is not set - -# -# ISDN subsystem -# # CONFIG_ISDN is not set - -# -# Telephony Support -# # CONFIG_PHONE is not set # @@ -730,6 +684,7 @@ CONFIG_MII=m # CONFIG_INPUT=y # CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set # # Userland interfaces @@ -739,7 +694,6 @@ CONFIG_INPUT_MOUSEDEV_PSAUX=y CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 # CONFIG_INPUT_JOYDEV is not set -# CONFIG_INPUT_TSDEV is not set CONFIG_INPUT_EVDEV=y # CONFIG_INPUT_EVBUG is not set @@ -749,6 +703,7 @@ CONFIG_INPUT_EVDEV=y # CONFIG_INPUT_KEYBOARD is not set # CONFIG_INPUT_MOUSE is not set # CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set # CONFIG_INPUT_TOUCHSCREEN is not set # CONFIG_INPUT_MISC is not set @@ -766,11 +721,12 @@ CONFIG_SERIO_RAW=y # Character devices # CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y CONFIG_VT_CONSOLE=y CONFIG_HW_CONSOLE=y CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_DEVKMEM=y # CONFIG_SERIAL_NONSTANDARD is not set -# CONFIG_AU1X00_GPIO is not set # # Serial drivers @@ -791,20 +747,8 @@ CONFIG_SERIAL_CORE_CONSOLE=y CONFIG_UNIX98_PTYS=y CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=256 - -# -# IPMI -# # CONFIG_IPMI_HANDLER is not set - -# -# Watchdog Cards -# -# CONFIG_WATCHDOG is not set # CONFIG_HW_RANDOM is not set -# CONFIG_RTC is not set -# CONFIG_GEN_RTC is not set -# CONFIG_DTLK is not set # CONFIG_R3964 is not set # @@ -813,61 +757,82 @@ CONFIG_LEGACY_PTY_COUNT=256 # CONFIG_SYNCLINK_CS is not set # CONFIG_CARDMAN_4000 is not set # CONFIG_CARDMAN_4040 is not set +# CONFIG_IPWIRELESS is not set # CONFIG_RAW_DRIVER is not set - -# -# TPM devices -# # CONFIG_TCG_TPM is not set - -# -# I2C support -# # CONFIG_I2C is not set +# CONFIG_SPI is not set +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +# CONFIG_THERMAL_HWMON is not set +# CONFIG_WATCHDOG is not set # -# SPI support +# Sonics Silicon Backplane # -# CONFIG_SPI is not set -# CONFIG_SPI_MASTER is not set +CONFIG_SSB_POSSIBLE=y +# CONFIG_SSB is not set # -# Dallas's 1-wire bus +# Multifunction device drivers # -# CONFIG_W1 is not set +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_HTC_PASIC3 is not set # -# Hardware Monitoring support +# Multimedia devices # -# CONFIG_HWMON is not set -# CONFIG_HWMON_VID is not set # -# Multimedia devices +# Multimedia core support # # CONFIG_VIDEO_DEV is not set +# CONFIG_DVB_CORE is not set +# CONFIG_VIDEO_MEDIA is not set # -# Digital Video Broadcasting Devices +# Multimedia drivers # -# CONFIG_DVB is not set +# CONFIG_DAB is not set # # Graphics support # -# CONFIG_FIRMWARE_EDID is not set +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set CONFIG_FB=y +# CONFIG_FIRMWARE_EDID is not set +# CONFIG_FB_DDC is not set CONFIG_FB_CFB_FILLRECT=y CONFIG_FB_CFB_COPYAREA=y CONFIG_FB_CFB_IMAGEBLIT=y +# CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set +# CONFIG_FB_SYS_FILLRECT is not set +# CONFIG_FB_SYS_COPYAREA is not set +# CONFIG_FB_SYS_IMAGEBLIT is not set +# CONFIG_FB_FOREIGN_ENDIAN is not set +# CONFIG_FB_SYS_FOPS is not set # CONFIG_FB_SVGALIB is not set # CONFIG_FB_MACMODES is not set # CONFIG_FB_BACKLIGHT is not set # CONFIG_FB_MODE_HELPERS is not set # CONFIG_FB_TILEBLITTING is not set + +# +# Frame buffer hardware drivers +# # CONFIG_FB_S1D13XXX is not set CONFIG_FB_AU1200=y # CONFIG_FB_VIRTUAL is not set +# CONFIG_BACKLIGHT_LCD_SUPPORT is not set + +# +# Display device support +# +# CONFIG_DISPLAY_SUPPORT is not set # # Console display driver support @@ -876,107 +841,76 @@ CONFIG_VGA_CONSOLE=y # CONFIG_VGACON_SOFT_SCROLLBACK is not set CONFIG_DUMMY_CONSOLE=y # CONFIG_FRAMEBUFFER_CONSOLE is not set - -# -# Logo configuration -# CONFIG_LOGO=y CONFIG_LOGO_LINUX_MONO=y CONFIG_LOGO_LINUX_VGA16=y CONFIG_LOGO_LINUX_CLUT224=y -# CONFIG_BACKLIGHT_LCD_SUPPORT is not set - -# -# Sound -# # CONFIG_SOUND is not set - -# -# HID Devices -# +CONFIG_HID_SUPPORT=y CONFIG_HID=y # CONFIG_HID_DEBUG is not set - -# -# USB support -# +# CONFIG_HIDRAW is not set +CONFIG_USB_SUPPORT=y CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB_ARCH_HAS_OHCI=y CONFIG_USB_ARCH_HAS_EHCI=y # CONFIG_USB is not set +# CONFIG_USB_OTG_WHITELIST is not set +# CONFIG_USB_OTG_BLACKLIST_HUB is not set # # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' # - -# -# USB Gadget Support -# CONFIG_USB_GADGET=m # CONFIG_USB_GADGET_DEBUG_FILES is not set +CONFIG_USB_GADGET_SELECTED=y +# CONFIG_USB_GADGET_AMD5536UDC is not set +# CONFIG_USB_GADGET_ATMEL_USBA is not set +# CONFIG_USB_GADGET_FSL_USB2 is not set # CONFIG_USB_GADGET_NET2280 is not set -# CONFIG_USB_GADGET_PXA2XX is not set +# CONFIG_USB_GADGET_PXA25X is not set +CONFIG_USB_GADGET_M66592=y +CONFIG_USB_M66592=m +# CONFIG_USB_GADGET_PXA27X is not set # CONFIG_USB_GADGET_GOKU is not set # CONFIG_USB_GADGET_LH7A40X is not set # CONFIG_USB_GADGET_OMAP is not set +# CONFIG_USB_GADGET_S3C2410 is not set # CONFIG_USB_GADGET_AT91 is not set # CONFIG_USB_GADGET_DUMMY_HCD is not set -# CONFIG_USB_GADGET_DUALSPEED is not set - -# -# MMC/SD Card support -# +CONFIG_USB_GADGET_DUALSPEED=y +# CONFIG_USB_ZERO is not set +# CONFIG_USB_ETH is not set +# CONFIG_USB_GADGETFS is not set +# CONFIG_USB_FILE_STORAGE is not set +# CONFIG_USB_G_SERIAL is not set +# CONFIG_USB_MIDI_GADGET is not set +# CONFIG_USB_G_PRINTER is not set +# CONFIG_USB_CDC_COMPOSITE is not set CONFIG_MMC=y # CONFIG_MMC_DEBUG is not set -CONFIG_MMC_BLOCK=y -CONFIG_MMC_AU1X=y - -# -# LED devices -# -# CONFIG_NEW_LEDS is not set - -# -# LED drivers -# - -# -# LED Triggers -# +# CONFIG_MMC_UNSAFE_RESUME is not set # -# InfiniBand support -# - -# -# EDAC - error detection and reporting (RAS) (EXPERIMENTAL) +# MMC/SD Card Drivers # +CONFIG_MMC_BLOCK=y +CONFIG_MMC_BLOCK_BOUNCE=y +# CONFIG_SDIO_UART is not set +# CONFIG_MMC_TEST is not set # -# Real Time Clock +# MMC/SD Host Controller Drivers # +# CONFIG_MMC_SDHCI is not set +CONFIG_MMC_AU1X=y +# CONFIG_MEMSTICK is not set +# CONFIG_NEW_LEDS is not set +# CONFIG_ACCESSIBILITY is not set +CONFIG_RTC_LIB=y # CONFIG_RTC_CLASS is not set - -# -# DMA Engine support -# -# CONFIG_DMA_ENGINE is not set - -# -# DMA Clients -# - -# -# DMA Devices -# - -# -# Auxiliary Display support -# - -# -# Virtualization -# +# CONFIG_DMADEVICES is not set +# CONFIG_UIO is not set # # File systems @@ -992,7 +926,6 @@ CONFIG_EXT3_FS_POSIX_ACL=y CONFIG_EXT3_FS_SECURITY=y # CONFIG_EXT4DEV_FS is not set CONFIG_JBD=y -# CONFIG_JBD_DEBUG is not set CONFIG_FS_MBCACHE=y # CONFIG_REISERFS_FS is not set CONFIG_JFS_FS=y @@ -1002,14 +935,11 @@ CONFIG_JFS_FS=y # CONFIG_JFS_STATISTICS is not set CONFIG_FS_POSIX_ACL=y # CONFIG_XFS_FS is not set -# CONFIG_GFS2_FS is not set # CONFIG_OCFS2_FS is not set -# CONFIG_MINIX_FS is not set -# CONFIG_ROMFS_FS is not set +CONFIG_DNOTIFY=y CONFIG_INOTIFY=y CONFIG_INOTIFY_USER=y # CONFIG_QUOTA is not set -CONFIG_DNOTIFY=y # CONFIG_AUTOFS_FS is not set # CONFIG_AUTOFS4_FS is not set # CONFIG_FUSE_FS is not set @@ -1044,7 +974,6 @@ CONFIG_SYSFS=y CONFIG_TMPFS=y CONFIG_TMPFS_POSIX_ACL=y # CONFIG_HUGETLB_PAGE is not set -CONFIG_RAMFS=y CONFIG_CONFIGFS_FS=m # @@ -1061,27 +990,29 @@ CONFIG_CONFIGFS_FS=m CONFIG_JFFS2_FS=y CONFIG_JFFS2_FS_DEBUG=0 CONFIG_JFFS2_FS_WRITEBUFFER=y +# CONFIG_JFFS2_FS_WBUF_VERIFY is not set # CONFIG_JFFS2_SUMMARY is not set # CONFIG_JFFS2_FS_XATTR is not set # CONFIG_JFFS2_COMPRESSION_OPTIONS is not set CONFIG_JFFS2_ZLIB=y +# CONFIG_JFFS2_LZO is not set CONFIG_JFFS2_RTIME=y # CONFIG_JFFS2_RUBIN is not set CONFIG_CRAMFS=m # CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set # CONFIG_HPFS_FS is not set # CONFIG_QNX4FS_FS is not set +# CONFIG_ROMFS_FS is not set # CONFIG_SYSV_FS is not set # CONFIG_UFS_FS is not set - -# -# Network File Systems -# +CONFIG_NETWORK_FILESYSTEMS=y CONFIG_NFS_FS=y CONFIG_NFS_V3=y # CONFIG_NFS_V3_ACL is not set # CONFIG_NFS_V4 is not set -# CONFIG_NFS_DIRECTIO is not set +CONFIG_ROOT_NFS=y # CONFIG_NFSD is not set CONFIG_LOCKD=y CONFIG_LOCKD_V4=y @@ -1095,17 +1026,12 @@ CONFIG_SMB_FS=y # CONFIG_NCP_FS is not set # CONFIG_CODA_FS is not set # CONFIG_AFS_FS is not set -# CONFIG_9P_FS is not set # # Partition Types # # CONFIG_PARTITION_ADVANCED is not set CONFIG_MSDOS_PARTITION=y - -# -# Native Language Support -# CONFIG_NLS=y CONFIG_NLS_DEFAULT="iso8859-1" CONFIG_NLS_CODEPAGE_437=m @@ -1146,34 +1072,26 @@ CONFIG_NLS_ISO8859_15=m CONFIG_NLS_KOI8_R=m CONFIG_NLS_KOI8_U=m CONFIG_NLS_UTF8=m - -# -# Distributed Lock Manager -# CONFIG_DLM=m -CONFIG_DLM_TCP=y -# CONFIG_DLM_SCTP is not set # CONFIG_DLM_DEBUG is not set # -# Profiling support -# -# CONFIG_PROFILING is not set - -# # Kernel hacking # CONFIG_TRACE_IRQFLAGS_SUPPORT=y # CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_WARN_DEPRECATED=y CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 # CONFIG_MAGIC_SYSRQ is not set # CONFIG_UNUSED_SYMBOLS is not set # CONFIG_DEBUG_FS is not set # CONFIG_HEADERS_CHECK is not set # CONFIG_DEBUG_KERNEL is not set -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_CROSSCOMPILE=y -CONFIG_CMDLINE="mem=48M" +# CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +CONFIG_CMDLINE="" # # Security options @@ -1181,60 +1099,101 @@ CONFIG_CMDLINE="mem=48M" CONFIG_KEYS=y CONFIG_KEYS_DEBUG_PROC_KEYS=y # CONFIG_SECURITY is not set +# CONFIG_SECURITY_FILE_CAPABILITIES is not set +CONFIG_CRYPTO=y # -# Cryptographic options +# Crypto core or helper # -CONFIG_CRYPTO=y CONFIG_CRYPTO_ALGAPI=y CONFIG_CRYPTO_BLKCIPHER=m CONFIG_CRYPTO_HASH=m CONFIG_CRYPTO_MANAGER=m +CONFIG_CRYPTO_GF128MUL=m +CONFIG_CRYPTO_NULL=m +# CONFIG_CRYPTO_CRYPTD is not set +# CONFIG_CRYPTO_AUTHENC is not set +# CONFIG_CRYPTO_TEST is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_SEQIV is not set + +# +# Block modes +# +CONFIG_CRYPTO_CBC=m +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +CONFIG_CRYPTO_ECB=m +CONFIG_CRYPTO_LRW=m +CONFIG_CRYPTO_PCBC=m +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# CONFIG_CRYPTO_HMAC=m CONFIG_CRYPTO_XCBC=m -CONFIG_CRYPTO_NULL=m + +# +# Digest +# +CONFIG_CRYPTO_CRC32C=m CONFIG_CRYPTO_MD4=m CONFIG_CRYPTO_MD5=y +CONFIG_CRYPTO_MICHAEL_MIC=m +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set CONFIG_CRYPTO_SHA1=m CONFIG_CRYPTO_SHA256=m CONFIG_CRYPTO_SHA512=m -CONFIG_CRYPTO_WP512=m CONFIG_CRYPTO_TGR192=m -CONFIG_CRYPTO_GF128MUL=m -CONFIG_CRYPTO_ECB=m -CONFIG_CRYPTO_CBC=m -CONFIG_CRYPTO_PCBC=m -CONFIG_CRYPTO_LRW=m -CONFIG_CRYPTO_DES=m -CONFIG_CRYPTO_FCRYPT=m -CONFIG_CRYPTO_BLOWFISH=m -CONFIG_CRYPTO_TWOFISH=m -CONFIG_CRYPTO_TWOFISH_COMMON=m -CONFIG_CRYPTO_SERPENT=m +CONFIG_CRYPTO_WP512=m + +# +# Ciphers +# CONFIG_CRYPTO_AES=m +CONFIG_CRYPTO_ANUBIS=m +CONFIG_CRYPTO_ARC4=m +CONFIG_CRYPTO_BLOWFISH=m +CONFIG_CRYPTO_CAMELLIA=m CONFIG_CRYPTO_CAST5=m CONFIG_CRYPTO_CAST6=m -CONFIG_CRYPTO_TEA=m -CONFIG_CRYPTO_ARC4=m +CONFIG_CRYPTO_DES=m +CONFIG_CRYPTO_FCRYPT=m CONFIG_CRYPTO_KHAZAD=m -CONFIG_CRYPTO_ANUBIS=m -CONFIG_CRYPTO_DEFLATE=m -CONFIG_CRYPTO_MICHAEL_MIC=m -CONFIG_CRYPTO_CRC32C=m -CONFIG_CRYPTO_CAMELLIA=m -# CONFIG_CRYPTO_TEST is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +CONFIG_CRYPTO_SERPENT=m +CONFIG_CRYPTO_TEA=m +CONFIG_CRYPTO_TWOFISH=m +CONFIG_CRYPTO_TWOFISH_COMMON=m # -# Hardware crypto devices +# Compression # +CONFIG_CRYPTO_DEFLATE=m +# CONFIG_CRYPTO_LZO is not set +CONFIG_CRYPTO_HW=y # # Library routines # CONFIG_BITREVERSE=y +# CONFIG_GENERIC_FIND_FIRST_BIT is not set CONFIG_CRC_CCITT=y # CONFIG_CRC16 is not set +CONFIG_CRC_T10DIF=y +CONFIG_CRC_ITU_T=m CONFIG_CRC32=y +# CONFIG_CRC7 is not set CONFIG_LIBCRC32C=y CONFIG_ZLIB_INFLATE=y CONFIG_ZLIB_DEFLATE=y @@ -1245,3 +1204,4 @@ CONFIG_TEXTSEARCH_FSM=m CONFIG_PLIST=y CONFIG_HAS_IOMEM=y CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y diff --git a/arch/mips/configs/db1550_defconfig b/arch/mips/configs/db1550_defconfig index a190ac0..5266c4d 100644 --- a/arch/mips/configs/db1550_defconfig +++ b/arch/mips/configs/db1550_defconfig @@ -1,80 +1,91 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.20 -# Tue Feb 20 21:47:27 2007 +# Linux kernel version: 2.6.27-rc1 +# Fri Aug 1 22:30:03 2008 # CONFIG_MIPS=y # # Machine selection # -CONFIG_ZONE_DMA=y CONFIG_MACH_ALCHEMY=y -# CONFIG_MIPS_MTX1 is not set -# CONFIG_MIPS_BOSPORUS is not set -# CONFIG_MIPS_PB1000 is not set -# CONFIG_MIPS_PB1100 is not set -# CONFIG_MIPS_PB1500 is not set -# CONFIG_MIPS_PB1550 is not set -# CONFIG_MIPS_PB1200 is not set -# CONFIG_MIPS_DB1000 is not set -# CONFIG_MIPS_DB1100 is not set -# CONFIG_MIPS_DB1500 is not set -CONFIG_MIPS_DB1550=y -# CONFIG_MIPS_DB1200 is not set -# CONFIG_MIPS_MIRAGE is not set -# CONFIG_BASLER_EXCITE is not set +# CONFIG_BCM47XX is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set +# CONFIG_LASAT is not set +# CONFIG_LEMOTE_FULONG is not set # CONFIG_MIPS_MALTA is not set -# CONFIG_WR_PPMC is not set # CONFIG_MIPS_SIM is not set -# CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_MIPS_XXS1500 is not set +# CONFIG_MARKEINS is not set +# CONFIG_MACH_VR41XX is not set # CONFIG_PNX8550_JBS is not set # CONFIG_PNX8550_STB810 is not set -# CONFIG_MACH_VR41XX is not set +# CONFIG_PMC_MSP is not set # CONFIG_PMC_YOSEMITE is not set -# CONFIG_MARKEINS is not set # CONFIG_SGI_IP22 is not set # CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP28 is not set # CONFIG_SGI_IP32 is not set -# CONFIG_SIBYTE_BIGSUR is not set -# CONFIG_SIBYTE_SWARM is not set -# CONFIG_SIBYTE_SENTOSA is not set -# CONFIG_SIBYTE_RHONE is not set -# CONFIG_SIBYTE_CARMEL is not set -# CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CARMEL is not set # CONFIG_SIBYTE_CRHONE is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_BIGSUR is not set # CONFIG_SNI_RM is not set -# CONFIG_TOSHIBA_JMR3927 is not set -# CONFIG_TOSHIBA_RBTX4927 is not set -# CONFIG_TOSHIBA_RBTX4938 is not set +# CONFIG_MACH_TX39XX is not set +# CONFIG_MACH_TX49XX is not set +# CONFIG_MIKROTIK_RB532 is not set +# CONFIG_WR_PPMC is not set +# CONFIG_MIPS_MTX1 is not set +# CONFIG_MIPS_BOSPORUS is not set +# CONFIG_MIPS_DB1000 is not set +# CONFIG_MIPS_DB1100 is not set +# CONFIG_MIPS_DB1200 is not set +# CONFIG_MIPS_DB1500 is not set +CONFIG_MIPS_DB1550=y +# CONFIG_MIPS_MIRAGE is not set +# CONFIG_MIPS_PB1000 is not set +# CONFIG_MIPS_PB1100 is not set +# CONFIG_MIPS_PB1200 is not set +# CONFIG_MIPS_PB1500 is not set +# CONFIG_MIPS_PB1550 is not set +# CONFIG_MIPS_XXS1500 is not set +CONFIG_SOC_AU1550=y +CONFIG_SOC_AU1X00=y CONFIG_RWSEM_GENERIC_SPINLOCK=y # CONFIG_ARCH_HAS_ILOG2_U32 is not set # CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_ARCH_SUPPORTS_OPROFILE=y CONFIG_GENERIC_FIND_NEXT_BIT=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_CLOCKEVENTS=y CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CMOS_UPDATE=y CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y # CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ is not set +CONFIG_CEVT_R4K=y +CONFIG_CSRC_R4K=y CONFIG_DMA_NONCOHERENT=y CONFIG_DMA_NEED_PCI_MAP_STATE=y +# CONFIG_HOTPLUG_CPU is not set CONFIG_MIPS_DISABLE_OBSOLETE_IDE=y +# CONFIG_NO_IOPORT is not set # CONFIG_CPU_BIG_ENDIAN is not set CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_SYS_SUPPORTS_APM_EMULATION=y CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y -CONFIG_SOC_AU1550=y -CONFIG_SOC_AU1X00=y +CONFIG_IRQ_CPU=y CONFIG_MIPS_L1_CACHE_SHIFT=5 # # CPU selection # +# CONFIG_CPU_LOONGSON2 is not set CONFIG_CPU_MIPS32_R1=y # CONFIG_CPU_MIPS32_R2 is not set # CONFIG_CPU_MIPS64_R1 is not set @@ -113,7 +124,6 @@ CONFIG_CPU_HAS_PREFETCH=y CONFIG_MIPS_MT_DISABLED=y # CONFIG_MIPS_MT_SMP is not set # CONFIG_MIPS_MT_SMTC is not set -# CONFIG_MIPS_VPE_LOADER is not set CONFIG_64BIT_PHYS_ADDR=y CONFIG_CPU_HAS_LLSC=y CONFIG_CPU_HAS_SYNC=y @@ -121,6 +131,7 @@ CONFIG_GENERIC_HARDIRQS=y CONFIG_GENERIC_IRQ_PROBE=y CONFIG_CPU_SUPPORTS_HIGHMEM=y CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_ARCH_POPULATES_NODE_MAP=y CONFIG_SELECT_MEMORY_MODEL=y CONFIG_FLATMEM_MANUAL=y # CONFIG_DISCONTIGMEM_MANUAL is not set @@ -128,9 +139,16 @@ CONFIG_FLATMEM_MANUAL=y CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y # CONFIG_SPARSEMEM_STATIC is not set +# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set +CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 CONFIG_RESOURCES_64BIT=y -CONFIG_ZONE_DMA_FLAG=1 +CONFIG_ZONE_DMA_FLAG=0 +CONFIG_VIRT_TO_BUS=y +# CONFIG_TICK_ONESHOT is not set +# CONFIG_NO_HZ is not set +# CONFIG_HIGH_RES_TIMERS is not set +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y # CONFIG_HZ_48 is not set # CONFIG_HZ_100 is not set # CONFIG_HZ_128 is not set @@ -144,72 +162,90 @@ CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set # CONFIG_KEXEC is not set +CONFIG_SECCOMP=y CONFIG_LOCKDEP_SUPPORT=y CONFIG_STACKTRACE_SUPPORT=y CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" # -# Code maturity level options +# General setup # CONFIG_EXPERIMENTAL=y CONFIG_BROKEN_ON_SMP=y CONFIG_INIT_ENV_ARG_LIMIT=32 - -# -# General setup -# CONFIG_LOCALVERSION="" CONFIG_LOCALVERSION_AUTO=y CONFIG_SWAP=y CONFIG_SYSVIPC=y -# CONFIG_IPC_NS is not set CONFIG_SYSVIPC_SYSCTL=y # CONFIG_POSIX_MQUEUE is not set # CONFIG_BSD_PROCESS_ACCT is not set # CONFIG_TASKSTATS is not set -# CONFIG_UTS_NS is not set # CONFIG_AUDIT is not set # CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_CGROUPS is not set +# CONFIG_GROUP_SCHED is not set CONFIG_SYSFS_DEPRECATED=y +CONFIG_SYSFS_DEPRECATED_V2=y CONFIG_RELAY=y +# CONFIG_NAMESPACES is not set +# CONFIG_BLK_DEV_INITRD is not set # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set CONFIG_SYSCTL=y CONFIG_EMBEDDED=y CONFIG_SYSCTL_SYSCALL=y +CONFIG_SYSCTL_SYSCALL_CHECK=y CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_EXTRA_PASS is not set CONFIG_HOTPLUG=y CONFIG_PRINTK=y CONFIG_BUG=y CONFIG_ELF_CORE=y +CONFIG_PCSPKR_PLATFORM=y +CONFIG_COMPAT_BRK=y CONFIG_BASE_FULL=y CONFIG_FUTEX=y +CONFIG_ANON_INODES=y CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y CONFIG_SHMEM=y -CONFIG_SLAB=y CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +# CONFIG_MARKERS is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set +# CONFIG_HAVE_IOREMAP_PROT is not set +# CONFIG_HAVE_KPROBES is not set +# CONFIG_HAVE_KRETPROBES is not set +# CONFIG_HAVE_ARCH_TRACEHOOK is not set +# CONFIG_HAVE_DMA_ATTRS is not set +# CONFIG_USE_GENERIC_SMP_HELPERS is not set +# CONFIG_HAVE_CLK is not set +CONFIG_PROC_PAGE_MONITOR=y +# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set +CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y # CONFIG_TINY_SHMEM is not set CONFIG_BASE_SMALL=0 -# CONFIG_SLOB is not set - -# -# Loadable module support -# CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set CONFIG_MODULE_UNLOAD=y # CONFIG_MODULE_FORCE_UNLOAD is not set CONFIG_MODVERSIONS=y CONFIG_MODULE_SRCVERSION_ALL=y CONFIG_KMOD=y - -# -# Block layer -# CONFIG_BLOCK=y # CONFIG_LBD is not set # CONFIG_BLK_DEV_IO_TRACE is not set # CONFIG_LSF is not set +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set # # IO Schedulers @@ -223,17 +259,17 @@ CONFIG_DEFAULT_AS=y # CONFIG_DEFAULT_CFQ is not set # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="anticipatory" +CONFIG_CLASSIC_RCU=y # # Bus options (PCI, PCMCIA, EISA, ISA, TC) # CONFIG_HW_HAS_PCI=y CONFIG_PCI=y +CONFIG_PCI_DOMAINS=y +# CONFIG_ARCH_SUPPORTS_MSI is not set +CONFIG_PCI_LEGACY=y CONFIG_MMU=y - -# -# PCCARD (PCMCIA/CardBus) support -# CONFIG_PCCARD=m # CONFIG_PCMCIA_DEBUG is not set CONFIG_PCMCIA=m @@ -248,10 +284,6 @@ CONFIG_CARDBUS=y # CONFIG_PD6729 is not set # CONFIG_I82092 is not set CONFIG_PCMCIA_AU1X00=m - -# -# PCI Hotplug Support -# # CONFIG_HOTPLUG_PCI is not set # @@ -264,17 +296,13 @@ CONFIG_TRAD_SIGNALS=y # # Power management options # +CONFIG_ARCH_SUSPEND_POSSIBLE=y # CONFIG_PM is not set - -# -# Networking -# CONFIG_NET=y # # Networking options # -# CONFIG_NETDEBUG is not set CONFIG_PACKET=y # CONFIG_PACKET_MMAP is not set CONFIG_UNIX=y @@ -282,6 +310,7 @@ CONFIG_XFRM=y CONFIG_XFRM_USER=m # CONFIG_XFRM_SUB_POLICY is not set CONFIG_XFRM_MIGRATE=y +# CONFIG_XFRM_STATISTICS is not set CONFIG_NET_KEY=y CONFIG_NET_KEY_MIGRATE=y CONFIG_INET=y @@ -305,23 +334,19 @@ CONFIG_IP_PNP_BOOTP=y CONFIG_INET_XFRM_MODE_TRANSPORT=m CONFIG_INET_XFRM_MODE_TUNNEL=m CONFIG_INET_XFRM_MODE_BEET=m +CONFIG_INET_LRO=m CONFIG_INET_DIAG=y CONFIG_INET_TCP_DIAG=y # CONFIG_TCP_CONG_ADVANCED is not set CONFIG_TCP_CONG_CUBIC=y CONFIG_DEFAULT_TCP_CONG="cubic" CONFIG_TCP_MD5SIG=y - -# -# IP: Virtual Server Configuration -# # CONFIG_IP_VS is not set # CONFIG_IPV6 is not set -# CONFIG_INET6_XFRM_TUNNEL is not set -# CONFIG_INET6_TUNNEL is not set CONFIG_NETWORK_SECMARK=y CONFIG_NETFILTER=y # CONFIG_NETFILTER_DEBUG is not set +CONFIG_NETFILTER_ADVANCED=y # # Core Netfilter Configuration @@ -329,16 +354,15 @@ CONFIG_NETFILTER=y CONFIG_NETFILTER_NETLINK=m CONFIG_NETFILTER_NETLINK_QUEUE=m CONFIG_NETFILTER_NETLINK_LOG=m -CONFIG_NF_CONNTRACK_ENABLED=m -CONFIG_NF_CONNTRACK_SUPPORT=y -# CONFIG_IP_NF_CONNTRACK_SUPPORT is not set CONFIG_NF_CONNTRACK=m CONFIG_NF_CT_ACCT=y CONFIG_NF_CONNTRACK_MARK=y CONFIG_NF_CONNTRACK_SECMARK=y CONFIG_NF_CONNTRACK_EVENTS=y +# CONFIG_NF_CT_PROTO_DCCP is not set CONFIG_NF_CT_PROTO_GRE=m CONFIG_NF_CT_PROTO_SCTP=m +# CONFIG_NF_CT_PROTO_UDPLITE is not set CONFIG_NF_CONNTRACK_AMANDA=m CONFIG_NF_CONNTRACK_FTP=m CONFIG_NF_CONNTRACK_H323=m @@ -354,31 +378,38 @@ CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m CONFIG_NETFILTER_XT_TARGET_MARK=m CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m CONFIG_NETFILTER_XT_TARGET_NFLOG=m +# CONFIG_NETFILTER_XT_TARGET_RATEEST is not set CONFIG_NETFILTER_XT_TARGET_SECMARK=m CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=m CONFIG_NETFILTER_XT_TARGET_TCPMSS=m CONFIG_NETFILTER_XT_MATCH_COMMENT=m CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m +# CONFIG_NETFILTER_XT_MATCH_CONNLIMIT is not set CONFIG_NETFILTER_XT_MATCH_CONNMARK=m CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m CONFIG_NETFILTER_XT_MATCH_DCCP=m CONFIG_NETFILTER_XT_MATCH_DSCP=m CONFIG_NETFILTER_XT_MATCH_ESP=m CONFIG_NETFILTER_XT_MATCH_HELPER=m +# CONFIG_NETFILTER_XT_MATCH_IPRANGE is not set CONFIG_NETFILTER_XT_MATCH_LENGTH=m CONFIG_NETFILTER_XT_MATCH_LIMIT=m CONFIG_NETFILTER_XT_MATCH_MAC=m CONFIG_NETFILTER_XT_MATCH_MARK=m +# CONFIG_NETFILTER_XT_MATCH_OWNER is not set CONFIG_NETFILTER_XT_MATCH_POLICY=m CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m CONFIG_NETFILTER_XT_MATCH_QUOTA=m +# CONFIG_NETFILTER_XT_MATCH_RATEEST is not set CONFIG_NETFILTER_XT_MATCH_REALM=m CONFIG_NETFILTER_XT_MATCH_SCTP=m CONFIG_NETFILTER_XT_MATCH_STATE=m CONFIG_NETFILTER_XT_MATCH_STATISTIC=m CONFIG_NETFILTER_XT_MATCH_STRING=m CONFIG_NETFILTER_XT_MATCH_TCPMSS=m +# CONFIG_NETFILTER_XT_MATCH_TIME is not set +# CONFIG_NETFILTER_XT_MATCH_U32 is not set CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m # @@ -389,20 +420,13 @@ CONFIG_NF_CONNTRACK_PROC_COMPAT=y # CONFIG_IP_NF_QUEUE is not set # CONFIG_IP_NF_IPTABLES is not set # CONFIG_IP_NF_ARPTABLES is not set - -# -# DCCP Configuration (EXPERIMENTAL) -# # CONFIG_IP_DCCP is not set - -# -# SCTP Configuration (EXPERIMENTAL) -# -# CONFIG_IP_SCTP is not set - -# -# TIPC Configuration (EXPERIMENTAL) -# +CONFIG_IP_SCTP=m +# CONFIG_SCTP_DBG_MSG is not set +# CONFIG_SCTP_DBG_OBJCNT is not set +# CONFIG_SCTP_HMAC_NONE is not set +# CONFIG_SCTP_HMAC_SHA1 is not set +CONFIG_SCTP_HMAC_MD5=y # CONFIG_TIPC is not set # CONFIG_ATM is not set # CONFIG_BRIDGE is not set @@ -415,10 +439,6 @@ CONFIG_NF_CONNTRACK_PROC_COMPAT=y # CONFIG_LAPB is not set # CONFIG_ECONET is not set # CONFIG_WAN_ROUTER is not set - -# -# QoS and/or fair queueing -# # CONFIG_NET_SCHED is not set CONFIG_NET_CLS_ROUTE=y @@ -427,15 +447,25 @@ CONFIG_NET_CLS_ROUTE=y # # CONFIG_NET_PKTGEN is not set # CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set # CONFIG_IRDA is not set # CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set + +# +# Wireless +# +# CONFIG_CFG80211 is not set +CONFIG_WIRELESS_EXT=y +CONFIG_WIRELESS_EXT_SYSFS=y +# CONFIG_MAC80211 is not set CONFIG_IEEE80211=m # CONFIG_IEEE80211_DEBUG is not set CONFIG_IEEE80211_CRYPT_WEP=m CONFIG_IEEE80211_CRYPT_CCMP=m -CONFIG_IEEE80211_SOFTMAC=m -# CONFIG_IEEE80211_SOFTMAC_DEBUG is not set -CONFIG_WIRELESS_EXT=y +# CONFIG_IEEE80211_CRYPT_TKIP is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set # # Device Drivers @@ -444,25 +474,21 @@ CONFIG_WIRELESS_EXT=y # # Generic Driver Options # +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_STANDALONE=y CONFIG_PREVENT_FIRMWARE_BUILD=y CONFIG_FW_LOADER=m +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" # CONFIG_SYS_HYPERVISOR is not set - -# -# Connector - unified userspace <-> kernelspace linker -# CONFIG_CONNECTOR=m - -# -# Memory Technology Devices (MTD) -# CONFIG_MTD=y # CONFIG_MTD_DEBUG is not set # CONFIG_MTD_CONCAT is not set CONFIG_MTD_PARTITIONS=y # CONFIG_MTD_REDBOOT_PARTS is not set # CONFIG_MTD_CMDLINE_PARTS is not set +# CONFIG_MTD_AR7_PARTS is not set # # User Modules And Translation Layers @@ -475,6 +501,7 @@ CONFIG_MTD_BLOCK=y # CONFIG_INFTL is not set # CONFIG_RFD_FTL is not set # CONFIG_SSFDC is not set +# CONFIG_MTD_OOPS is not set # # RAM/ROM/Flash chip drivers @@ -500,7 +527,6 @@ CONFIG_MTD_CFI_UTIL=y # CONFIG_MTD_RAM is not set # CONFIG_MTD_ROM is not set # CONFIG_MTD_ABSENT is not set -# CONFIG_MTD_OBSOLETE_CHIPS is not set # # Mapping drivers for chip access @@ -508,6 +534,7 @@ CONFIG_MTD_CFI_UTIL=y # CONFIG_MTD_COMPLEX_MAPPINGS is not set # CONFIG_MTD_PHYSMAP is not set CONFIG_MTD_ALCHEMY=y +# CONFIG_MTD_INTEL_VR_NOR is not set # CONFIG_MTD_PLATRAM is not set # @@ -525,37 +552,24 @@ CONFIG_MTD_ALCHEMY=y # CONFIG_MTD_DOC2000 is not set # CONFIG_MTD_DOC2001 is not set # CONFIG_MTD_DOC2001PLUS is not set - -# -# NAND Flash Device Drivers -# CONFIG_MTD_NAND=m # CONFIG_MTD_NAND_VERIFY_WRITE is not set # CONFIG_MTD_NAND_ECC_SMC is not set +# CONFIG_MTD_NAND_MUSEUM_IDS is not set CONFIG_MTD_NAND_IDS=m CONFIG_MTD_NAND_AU1550=m # CONFIG_MTD_NAND_DISKONCHIP is not set # CONFIG_MTD_NAND_CAFE is not set # CONFIG_MTD_NAND_NANDSIM is not set - -# -# OneNAND Flash Device Drivers -# +# CONFIG_MTD_NAND_PLATFORM is not set # CONFIG_MTD_ONENAND is not set # -# Parallel port support +# UBI - Unsorted block images # +# CONFIG_MTD_UBI is not set # CONFIG_PARPORT is not set - -# -# Plug and Play support -# -# CONFIG_PNPACPI is not set - -# -# Block devices -# +CONFIG_BLK_DEV=y # CONFIG_BLK_CPQ_DA is not set # CONFIG_BLK_CPQ_CISS_DA is not set # CONFIG_BLK_DEV_DAC960 is not set @@ -566,27 +580,25 @@ CONFIG_BLK_DEV_LOOP=y # CONFIG_BLK_DEV_NBD is not set # CONFIG_BLK_DEV_SX8 is not set # CONFIG_BLK_DEV_RAM is not set -# CONFIG_BLK_DEV_INITRD is not set CONFIG_CDROM_PKTCDVD=m CONFIG_CDROM_PKTCDVD_BUFFERS=8 # CONFIG_CDROM_PKTCDVD_WCACHE is not set CONFIG_ATA_OVER_ETH=m - -# -# Misc devices -# +# CONFIG_BLK_DEV_HD is not set +CONFIG_MISC_DEVICES=y +# CONFIG_PHANTOM is not set +# CONFIG_EEPROM_93CX6 is not set CONFIG_SGI_IOC4=m # CONFIG_TIFM_CORE is not set - -# -# ATA/ATAPI/MFM/RLL support -# +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_HP_ILO is not set +CONFIG_HAVE_IDE=y CONFIG_IDE=y CONFIG_IDE_MAX_HWIFS=4 CONFIG_BLK_DEV_IDE=y # -# Please see Documentation/ide.txt for help/info on IDE drives +# Please see Documentation/ide/ide.txt for help/info on IDE drives # # CONFIG_BLK_DEV_IDE_SATA is not set CONFIG_BLK_DEV_IDEDISK=y @@ -597,28 +609,31 @@ CONFIG_BLK_DEV_IDECS=m # CONFIG_BLK_DEV_IDETAPE is not set # CONFIG_BLK_DEV_IDEFLOPPY is not set # CONFIG_IDE_TASK_IOCTL is not set +CONFIG_IDE_PROC_FS=y # # IDE chipset support/bugfixes # CONFIG_IDE_GENERIC=y +# CONFIG_BLK_DEV_PLATFORM is not set +CONFIG_BLK_DEV_IDEDMA_SFF=y + +# +# PCI IDE chipsets support +# CONFIG_BLK_DEV_IDEPCI=y -# CONFIG_IDEPCI_SHARE_IRQ is not set +CONFIG_IDEPCI_PCIBUS_ORDER=y # CONFIG_BLK_DEV_OFFBOARD is not set CONFIG_BLK_DEV_GENERIC=y # CONFIG_BLK_DEV_OPTI621 is not set CONFIG_BLK_DEV_IDEDMA_PCI=y -# CONFIG_BLK_DEV_IDEDMA_FORCED is not set -# CONFIG_IDEDMA_PCI_AUTO is not set # CONFIG_BLK_DEV_AEC62XX is not set # CONFIG_BLK_DEV_ALI15X3 is not set # CONFIG_BLK_DEV_AMD74XX is not set # CONFIG_BLK_DEV_CMD64X is not set # CONFIG_BLK_DEV_TRIFLEX is not set -# CONFIG_BLK_DEV_CY82C693 is not set # CONFIG_BLK_DEV_CS5520 is not set # CONFIG_BLK_DEV_CS5530 is not set -# CONFIG_BLK_DEV_HPT34X is not set # CONFIG_BLK_DEV_HPT366 is not set # CONFIG_BLK_DEV_JMICRON is not set # CONFIG_BLK_DEV_SC1200 is not set @@ -634,61 +649,37 @@ CONFIG_BLK_DEV_IT8213=m # CONFIG_BLK_DEV_TRM290 is not set # CONFIG_BLK_DEV_VIA82CXXX is not set CONFIG_BLK_DEV_TC86C001=m -# CONFIG_IDE_ARM is not set CONFIG_BLK_DEV_IDEDMA=y -# CONFIG_IDEDMA_IVB is not set -# CONFIG_IDEDMA_AUTO is not set -# CONFIG_BLK_DEV_HD is not set # # SCSI device support # CONFIG_RAID_ATTRS=m # CONFIG_SCSI is not set +# CONFIG_SCSI_DMA is not set # CONFIG_SCSI_NETLINK is not set - -# -# Serial ATA (prod) and Parallel ATA (experimental) drivers -# # CONFIG_ATA is not set - -# -# Multi-device support (RAID and LVM) -# # CONFIG_MD is not set - -# -# Fusion MPT device support -# # CONFIG_FUSION is not set # # IEEE 1394 (FireWire) support # -# CONFIG_IEEE1394 is not set # -# I2O device support +# Enable only one of the two stacks, unless you know what you are doing # +# CONFIG_FIREWIRE is not set +# CONFIG_IEEE1394 is not set # CONFIG_I2O is not set - -# -# Network device support -# CONFIG_NETDEVICES=y # CONFIG_DUMMY is not set # CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set # CONFIG_EQUALIZER is not set # CONFIG_TUN is not set - -# -# ARCnet devices -# +# CONFIG_VETH is not set # CONFIG_ARCNET is not set - -# -# PHY device support -# CONFIG_PHYLIB=y # @@ -702,13 +693,13 @@ CONFIG_CICADA_PHY=m CONFIG_VITESSE_PHY=m CONFIG_SMSC_PHY=m # CONFIG_BROADCOM_PHY is not set +# CONFIG_ICPLUS_PHY is not set +# CONFIG_REALTEK_PHY is not set # CONFIG_FIXED_PHY is not set - -# -# Ethernet (10 or 100Mbit) -# +# CONFIG_MDIO_BITBANG is not set CONFIG_NET_ETHERNET=y CONFIG_MII=m +# CONFIG_AX88796 is not set CONFIG_MIPS_AU1X00_ENET=y # CONFIG_HAPPYMEAL is not set # CONFIG_SUNGEM is not set @@ -716,20 +707,21 @@ CONFIG_MIPS_AU1X00_ENET=y # CONFIG_NET_VENDOR_3COM is not set # CONFIG_SMC91X is not set # CONFIG_DM9000 is not set - -# -# Tulip family network device support -# # CONFIG_NET_TULIP is not set # CONFIG_HP100 is not set +# CONFIG_IBM_NEW_EMAC_ZMII is not set +# CONFIG_IBM_NEW_EMAC_RGMII is not set +# CONFIG_IBM_NEW_EMAC_TAH is not set +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set # CONFIG_NET_PCI is not set - -# -# Ethernet (1000 Mbit) -# +# CONFIG_B44 is not set +CONFIG_NETDEV_1000=y # CONFIG_ACENIC is not set # CONFIG_DL2K is not set # CONFIG_E1000 is not set +# CONFIG_E1000E is not set +# CONFIG_IP1000 is not set +# CONFIG_IGB is not set # CONFIG_NS83820 is not set # CONFIG_HAMACHI is not set # CONFIG_YELLOWFIN is not set @@ -737,35 +729,33 @@ CONFIG_MIPS_AU1X00_ENET=y # CONFIG_SIS190 is not set # CONFIG_SKGE is not set # CONFIG_SKY2 is not set -# CONFIG_SK98LIN is not set +# CONFIG_VIA_VELOCITY is not set # CONFIG_TIGON3 is not set # CONFIG_BNX2 is not set CONFIG_QLA3XXX=m # CONFIG_ATL1 is not set - -# -# Ethernet (10000 Mbit) -# +# CONFIG_ATL1E is not set +CONFIG_NETDEV_10000=y # CONFIG_CHELSIO_T1 is not set CONFIG_CHELSIO_T3=m +# CONFIG_IXGBE is not set # CONFIG_IXGB is not set # CONFIG_S2IO is not set # CONFIG_MYRI10GE is not set CONFIG_NETXEN_NIC=m - -# -# Token Ring devices -# +# CONFIG_NIU is not set +# CONFIG_MLX4_CORE is not set +# CONFIG_TEHUTI is not set +# CONFIG_BNX2X is not set +# CONFIG_SFC is not set # CONFIG_TR is not set # -# Wireless LAN (non-hamradio) -# -# CONFIG_NET_RADIO is not set - -# -# PCMCIA network device support +# Wireless LAN # +# CONFIG_WLAN_PRE80211 is not set +# CONFIG_WLAN_80211 is not set +# CONFIG_IWLWIFI_LEDS is not set CONFIG_NET_PCMCIA=y CONFIG_PCMCIA_3C589=m CONFIG_PCMCIA_3C574=m @@ -775,10 +765,6 @@ CONFIG_PCMCIA_NMCLAN=m CONFIG_PCMCIA_SMC91C92=m CONFIG_PCMCIA_XIRC2PS=m CONFIG_PCMCIA_AXNET=m - -# -# Wan interfaces -# # CONFIG_WAN is not set # CONFIG_FDDI is not set # CONFIG_HIPPI is not set @@ -791,21 +777,13 @@ CONFIG_PPP_DEFLATE=m # CONFIG_PPP_BSDCOMP is not set CONFIG_PPP_MPPE=m CONFIG_PPPOE=m +# CONFIG_PPPOL2TP is not set # CONFIG_SLIP is not set CONFIG_SLHC=m -# CONFIG_SHAPER is not set # CONFIG_NETCONSOLE is not set # CONFIG_NETPOLL is not set # CONFIG_NET_POLL_CONTROLLER is not set - -# -# ISDN subsystem -# # CONFIG_ISDN is not set - -# -# Telephony Support -# # CONFIG_PHONE is not set # @@ -813,6 +791,7 @@ CONFIG_SLHC=m # CONFIG_INPUT=y # CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set # # Userland interfaces @@ -822,7 +801,6 @@ CONFIG_INPUT_MOUSEDEV_PSAUX=y CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 # CONFIG_INPUT_JOYDEV is not set -# CONFIG_INPUT_TSDEV is not set CONFIG_INPUT_EVDEV=y # CONFIG_INPUT_EVBUG is not set @@ -832,6 +810,7 @@ CONFIG_INPUT_EVDEV=y # CONFIG_INPUT_KEYBOARD is not set # CONFIG_INPUT_MOUSE is not set # CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set # CONFIG_INPUT_TOUCHSCREEN is not set # CONFIG_INPUT_MISC is not set @@ -850,8 +829,9 @@ CONFIG_SERIO_RAW=m # Character devices # # CONFIG_VT is not set +CONFIG_DEVKMEM=y # CONFIG_SERIAL_NONSTANDARD is not set -# CONFIG_AU1X00_GPIO is not set +# CONFIG_NOZOMI is not set # # Serial drivers @@ -874,23 +854,10 @@ CONFIG_SERIAL_CORE_CONSOLE=y CONFIG_UNIX98_PTYS=y CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=256 - -# -# IPMI -# # CONFIG_IPMI_HANDLER is not set - -# -# Watchdog Cards -# -# CONFIG_WATCHDOG is not set # CONFIG_HW_RANDOM is not set -# CONFIG_RTC is not set -# CONFIG_GEN_RTC is not set -# CONFIG_DTLK is not set # CONFIG_R3964 is not set # CONFIG_APPLICOM is not set -# CONFIG_DRM is not set # # PCMCIA character devices @@ -898,131 +865,85 @@ CONFIG_LEGACY_PTY_COUNT=256 CONFIG_SYNCLINK_CS=m # CONFIG_CARDMAN_4000 is not set # CONFIG_CARDMAN_4040 is not set +# CONFIG_IPWIRELESS is not set # CONFIG_RAW_DRIVER is not set - -# -# TPM devices -# # CONFIG_TCG_TPM is not set - -# -# I2C support -# +CONFIG_DEVPORT=y # CONFIG_I2C is not set +# CONFIG_SPI is not set +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +# CONFIG_THERMAL_HWMON is not set +# CONFIG_WATCHDOG is not set # -# SPI support +# Sonics Silicon Backplane # -# CONFIG_SPI is not set -# CONFIG_SPI_MASTER is not set +CONFIG_SSB_POSSIBLE=y +# CONFIG_SSB is not set # -# Dallas's 1-wire bus +# Multifunction device drivers # -# CONFIG_W1 is not set +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_HTC_PASIC3 is not set # -# Hardware Monitoring support +# Multimedia devices # -# CONFIG_HWMON is not set -# CONFIG_HWMON_VID is not set # -# Multimedia devices +# Multimedia core support # # CONFIG_VIDEO_DEV is not set +# CONFIG_DVB_CORE is not set +# CONFIG_VIDEO_MEDIA is not set # -# Digital Video Broadcasting Devices +# Multimedia drivers # -# CONFIG_DVB is not set +# CONFIG_DAB is not set # # Graphics support # -# CONFIG_FIRMWARE_EDID is not set +# CONFIG_DRM is not set +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set # CONFIG_FB is not set # CONFIG_BACKLIGHT_LCD_SUPPORT is not set # -# Sound +# Display device support # +# CONFIG_DISPLAY_SUPPORT is not set # CONFIG_SOUND is not set - -# -# HID Devices -# +CONFIG_HID_SUPPORT=y # CONFIG_HID is not set - -# -# USB support -# +CONFIG_USB_SUPPORT=y CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB_ARCH_HAS_OHCI=y CONFIG_USB_ARCH_HAS_EHCI=y # CONFIG_USB is not set +# CONFIG_USB_OTG_WHITELIST is not set +# CONFIG_USB_OTG_BLACKLIST_HUB is not set # # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' # - -# -# USB Gadget Support -# # CONFIG_USB_GADGET is not set - -# -# MMC/SD Card support -# # CONFIG_MMC is not set - -# -# LED devices -# +# CONFIG_MEMSTICK is not set # CONFIG_NEW_LEDS is not set - -# -# LED drivers -# - -# -# LED Triggers -# - -# -# InfiniBand support -# +# CONFIG_ACCESSIBILITY is not set # CONFIG_INFINIBAND is not set - -# -# EDAC - error detection and reporting (RAS) (EXPERIMENTAL) -# - -# -# Real Time Clock -# +CONFIG_RTC_LIB=y # CONFIG_RTC_CLASS is not set - -# -# DMA Engine support -# -# CONFIG_DMA_ENGINE is not set - -# -# DMA Clients -# - -# -# DMA Devices -# - -# -# Auxiliary Display support -# - -# -# Virtualization -# +# CONFIG_DMADEVICES is not set +# CONFIG_UIO is not set # # File systems @@ -1038,7 +959,6 @@ CONFIG_EXT3_FS_POSIX_ACL=y CONFIG_EXT3_FS_SECURITY=y # CONFIG_EXT4DEV_FS is not set CONFIG_JBD=y -# CONFIG_JBD_DEBUG is not set CONFIG_FS_MBCACHE=y CONFIG_REISERFS_FS=m # CONFIG_REISERFS_CHECK is not set @@ -1049,14 +969,11 @@ CONFIG_REISERFS_FS_SECURITY=y # CONFIG_JFS_FS is not set CONFIG_FS_POSIX_ACL=y # CONFIG_XFS_FS is not set -# CONFIG_GFS2_FS is not set # CONFIG_OCFS2_FS is not set -# CONFIG_MINIX_FS is not set -# CONFIG_ROMFS_FS is not set +CONFIG_DNOTIFY=y CONFIG_INOTIFY=y CONFIG_INOTIFY_USER=y # CONFIG_QUOTA is not set -CONFIG_DNOTIFY=y CONFIG_AUTOFS_FS=m CONFIG_AUTOFS4_FS=m CONFIG_FUSE_FS=m @@ -1085,7 +1002,6 @@ CONFIG_SYSFS=y CONFIG_TMPFS=y CONFIG_TMPFS_POSIX_ACL=y # CONFIG_HUGETLB_PAGE is not set -CONFIG_RAMFS=y CONFIG_CONFIGFS_FS=m # @@ -1102,22 +1018,21 @@ CONFIG_CONFIGFS_FS=m # CONFIG_JFFS2_FS is not set CONFIG_CRAMFS=m # CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set # CONFIG_HPFS_FS is not set # CONFIG_QNX4FS_FS is not set +# CONFIG_ROMFS_FS is not set # CONFIG_SYSV_FS is not set # CONFIG_UFS_FS is not set - -# -# Network File Systems -# +CONFIG_NETWORK_FILESYSTEMS=y CONFIG_NFS_FS=y # CONFIG_NFS_V3 is not set # CONFIG_NFS_V4 is not set -# CONFIG_NFS_DIRECTIO is not set +CONFIG_ROOT_NFS=y CONFIG_NFSD=m # CONFIG_NFSD_V3 is not set -# CONFIG_NFSD_TCP is not set -CONFIG_ROOT_NFS=y +# CONFIG_NFSD_V4 is not set CONFIG_LOCKD=y CONFIG_EXPORTFS=m CONFIG_NFS_COMMON=y @@ -1130,17 +1045,12 @@ CONFIG_SMB_FS=m # CONFIG_NCP_FS is not set # CONFIG_CODA_FS is not set # CONFIG_AFS_FS is not set -# CONFIG_9P_FS is not set # # Partition Types # # CONFIG_PARTITION_ADVANCED is not set CONFIG_MSDOS_PARTITION=y - -# -# Native Language Support -# CONFIG_NLS=m CONFIG_NLS_DEFAULT="iso8859-1" # CONFIG_NLS_CODEPAGE_437 is not set @@ -1181,33 +1091,25 @@ CONFIG_NLS_DEFAULT="iso8859-1" # CONFIG_NLS_KOI8_R is not set # CONFIG_NLS_KOI8_U is not set # CONFIG_NLS_UTF8 is not set - -# -# Distributed Lock Manager -# CONFIG_DLM=m -CONFIG_DLM_TCP=y -# CONFIG_DLM_SCTP is not set # CONFIG_DLM_DEBUG is not set # -# Profiling support -# -# CONFIG_PROFILING is not set - -# # Kernel hacking # CONFIG_TRACE_IRQFLAGS_SUPPORT=y # CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_WARN_DEPRECATED=y CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 # CONFIG_MAGIC_SYSRQ is not set # CONFIG_UNUSED_SYMBOLS is not set # CONFIG_DEBUG_FS is not set # CONFIG_HEADERS_CHECK is not set # CONFIG_DEBUG_KERNEL is not set -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_CROSSCOMPILE=y +# CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y CONFIG_CMDLINE="" # @@ -1216,60 +1118,102 @@ CONFIG_CMDLINE="" CONFIG_KEYS=y CONFIG_KEYS_DEBUG_PROC_KEYS=y # CONFIG_SECURITY is not set +# CONFIG_SECURITY_FILE_CAPABILITIES is not set +CONFIG_CRYPTO=y # -# Cryptographic options +# Crypto core or helper # -CONFIG_CRYPTO=y CONFIG_CRYPTO_ALGAPI=y CONFIG_CRYPTO_BLKCIPHER=m CONFIG_CRYPTO_HASH=y CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_GF128MUL=m +CONFIG_CRYPTO_NULL=m +# CONFIG_CRYPTO_CRYPTD is not set +# CONFIG_CRYPTO_AUTHENC is not set +# CONFIG_CRYPTO_TEST is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_SEQIV is not set + +# +# Block modes +# +CONFIG_CRYPTO_CBC=m +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +CONFIG_CRYPTO_ECB=m +CONFIG_CRYPTO_LRW=m +CONFIG_CRYPTO_PCBC=m +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# CONFIG_CRYPTO_HMAC=y CONFIG_CRYPTO_XCBC=m -CONFIG_CRYPTO_NULL=m + +# +# Digest +# +CONFIG_CRYPTO_CRC32C=m CONFIG_CRYPTO_MD4=m CONFIG_CRYPTO_MD5=y +CONFIG_CRYPTO_MICHAEL_MIC=m +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set CONFIG_CRYPTO_SHA1=m CONFIG_CRYPTO_SHA256=m CONFIG_CRYPTO_SHA512=m -CONFIG_CRYPTO_WP512=m CONFIG_CRYPTO_TGR192=m -CONFIG_CRYPTO_GF128MUL=m -CONFIG_CRYPTO_ECB=m -CONFIG_CRYPTO_CBC=m -CONFIG_CRYPTO_PCBC=m -CONFIG_CRYPTO_LRW=m -CONFIG_CRYPTO_DES=m -CONFIG_CRYPTO_FCRYPT=m -CONFIG_CRYPTO_BLOWFISH=m -CONFIG_CRYPTO_TWOFISH=m -CONFIG_CRYPTO_TWOFISH_COMMON=m -CONFIG_CRYPTO_SERPENT=m +CONFIG_CRYPTO_WP512=m + +# +# Ciphers +# CONFIG_CRYPTO_AES=m +CONFIG_CRYPTO_ANUBIS=m +CONFIG_CRYPTO_ARC4=m +CONFIG_CRYPTO_BLOWFISH=m +CONFIG_CRYPTO_CAMELLIA=m CONFIG_CRYPTO_CAST5=m CONFIG_CRYPTO_CAST6=m -CONFIG_CRYPTO_TEA=m -CONFIG_CRYPTO_ARC4=m +CONFIG_CRYPTO_DES=m +CONFIG_CRYPTO_FCRYPT=m CONFIG_CRYPTO_KHAZAD=m -CONFIG_CRYPTO_ANUBIS=m -CONFIG_CRYPTO_DEFLATE=m -CONFIG_CRYPTO_MICHAEL_MIC=m -CONFIG_CRYPTO_CRC32C=m -CONFIG_CRYPTO_CAMELLIA=m -# CONFIG_CRYPTO_TEST is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +CONFIG_CRYPTO_SERPENT=m +CONFIG_CRYPTO_TEA=m +CONFIG_CRYPTO_TWOFISH=m +CONFIG_CRYPTO_TWOFISH_COMMON=m # -# Hardware crypto devices +# Compression # +CONFIG_CRYPTO_DEFLATE=m +# CONFIG_CRYPTO_LZO is not set +CONFIG_CRYPTO_HW=y +# CONFIG_CRYPTO_DEV_HIFN_795X is not set # # Library routines # CONFIG_BITREVERSE=y +# CONFIG_GENERIC_FIND_FIRST_BIT is not set CONFIG_CRC_CCITT=m CONFIG_CRC16=m +# CONFIG_CRC_T10DIF is not set +# CONFIG_CRC_ITU_T is not set CONFIG_CRC32=y +# CONFIG_CRC7 is not set CONFIG_LIBCRC32C=m CONFIG_ZLIB_INFLATE=m CONFIG_ZLIB_DEFLATE=m @@ -1280,3 +1224,4 @@ CONFIG_TEXTSEARCH_FSM=m CONFIG_PLIST=y CONFIG_HAS_IOMEM=y CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y diff --git a/arch/mips/configs/pb1550_defconfig b/arch/mips/configs/pb1550_defconfig index 7956f56..d62791c 100644 --- a/arch/mips/configs/pb1550_defconfig +++ b/arch/mips/configs/pb1550_defconfig @@ -1,80 +1,91 @@ # # Automatically generated make config: don't edit -# Linux kernel version: 2.6.20 -# Tue Feb 20 21:47:37 2007 +# Linux kernel version: 2.6.27-rc1 +# Fri Aug 1 22:31:24 2008 # CONFIG_MIPS=y # # Machine selection # -CONFIG_ZONE_DMA=y CONFIG_MACH_ALCHEMY=y -# CONFIG_MIPS_MTX1 is not set -# CONFIG_MIPS_BOSPORUS is not set -# CONFIG_MIPS_PB1000 is not set -# CONFIG_MIPS_PB1100 is not set -# CONFIG_MIPS_PB1500 is not set -CONFIG_MIPS_PB1550=y -# CONFIG_MIPS_PB1200 is not set -# CONFIG_MIPS_DB1000 is not set -# CONFIG_MIPS_DB1100 is not set -# CONFIG_MIPS_DB1500 is not set -# CONFIG_MIPS_DB1550 is not set -# CONFIG_MIPS_DB1200 is not set -# CONFIG_MIPS_MIRAGE is not set -# CONFIG_BASLER_EXCITE is not set +# CONFIG_BCM47XX is not set # CONFIG_MIPS_COBALT is not set # CONFIG_MACH_DECSTATION is not set # CONFIG_MACH_JAZZ is not set +# CONFIG_LASAT is not set +# CONFIG_LEMOTE_FULONG is not set # CONFIG_MIPS_MALTA is not set -# CONFIG_WR_PPMC is not set # CONFIG_MIPS_SIM is not set -# CONFIG_MOMENCO_JAGUAR_ATX is not set -# CONFIG_MIPS_XXS1500 is not set +# CONFIG_MARKEINS is not set +# CONFIG_MACH_VR41XX is not set # CONFIG_PNX8550_JBS is not set # CONFIG_PNX8550_STB810 is not set -# CONFIG_MACH_VR41XX is not set +# CONFIG_PMC_MSP is not set # CONFIG_PMC_YOSEMITE is not set -# CONFIG_MARKEINS is not set # CONFIG_SGI_IP22 is not set # CONFIG_SGI_IP27 is not set +# CONFIG_SGI_IP28 is not set # CONFIG_SGI_IP32 is not set -# CONFIG_SIBYTE_BIGSUR is not set -# CONFIG_SIBYTE_SWARM is not set -# CONFIG_SIBYTE_SENTOSA is not set -# CONFIG_SIBYTE_RHONE is not set -# CONFIG_SIBYTE_CARMEL is not set -# CONFIG_SIBYTE_LITTLESUR is not set # CONFIG_SIBYTE_CRHINE is not set +# CONFIG_SIBYTE_CARMEL is not set # CONFIG_SIBYTE_CRHONE is not set +# CONFIG_SIBYTE_RHONE is not set +# CONFIG_SIBYTE_SWARM is not set +# CONFIG_SIBYTE_LITTLESUR is not set +# CONFIG_SIBYTE_SENTOSA is not set +# CONFIG_SIBYTE_BIGSUR is not set # CONFIG_SNI_RM is not set -# CONFIG_TOSHIBA_JMR3927 is not set -# CONFIG_TOSHIBA_RBTX4927 is not set -# CONFIG_TOSHIBA_RBTX4938 is not set +# CONFIG_MACH_TX39XX is not set +# CONFIG_MACH_TX49XX is not set +# CONFIG_MIKROTIK_RB532 is not set +# CONFIG_WR_PPMC is not set +# CONFIG_MIPS_MTX1 is not set +# CONFIG_MIPS_BOSPORUS is not set +# CONFIG_MIPS_DB1000 is not set +# CONFIG_MIPS_DB1100 is not set +# CONFIG_MIPS_DB1200 is not set +# CONFIG_MIPS_DB1500 is not set +# CONFIG_MIPS_DB1550 is not set +# CONFIG_MIPS_MIRAGE is not set +# CONFIG_MIPS_PB1000 is not set +# CONFIG_MIPS_PB1100 is not set +# CONFIG_MIPS_PB1200 is not set +# CONFIG_MIPS_PB1500 is not set +CONFIG_MIPS_PB1550=y +# CONFIG_MIPS_XXS1500 is not set +CONFIG_SOC_AU1550=y +CONFIG_SOC_AU1X00=y CONFIG_RWSEM_GENERIC_SPINLOCK=y # CONFIG_ARCH_HAS_ILOG2_U32 is not set # CONFIG_ARCH_HAS_ILOG2_U64 is not set +CONFIG_ARCH_SUPPORTS_OPROFILE=y CONFIG_GENERIC_FIND_NEXT_BIT=y CONFIG_GENERIC_HWEIGHT=y CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_GENERIC_CLOCKEVENTS=y CONFIG_GENERIC_TIME=y +CONFIG_GENERIC_CMOS_UPDATE=y CONFIG_SCHED_NO_NO_OMIT_FRAME_POINTER=y # CONFIG_GENERIC_HARDIRQS_NO__DO_IRQ is not set +CONFIG_CEVT_R4K=y +CONFIG_CSRC_R4K=y CONFIG_DMA_NONCOHERENT=y CONFIG_DMA_NEED_PCI_MAP_STATE=y +# CONFIG_HOTPLUG_CPU is not set CONFIG_MIPS_DISABLE_OBSOLETE_IDE=y +# CONFIG_NO_IOPORT is not set # CONFIG_CPU_BIG_ENDIAN is not set CONFIG_CPU_LITTLE_ENDIAN=y CONFIG_SYS_SUPPORTS_APM_EMULATION=y CONFIG_SYS_SUPPORTS_LITTLE_ENDIAN=y -CONFIG_SOC_AU1550=y -CONFIG_SOC_AU1X00=y +CONFIG_IRQ_CPU=y CONFIG_MIPS_L1_CACHE_SHIFT=5 # # CPU selection # +# CONFIG_CPU_LOONGSON2 is not set CONFIG_CPU_MIPS32_R1=y # CONFIG_CPU_MIPS32_R2 is not set # CONFIG_CPU_MIPS64_R1 is not set @@ -113,7 +124,6 @@ CONFIG_CPU_HAS_PREFETCH=y CONFIG_MIPS_MT_DISABLED=y # CONFIG_MIPS_MT_SMP is not set # CONFIG_MIPS_MT_SMTC is not set -# CONFIG_MIPS_VPE_LOADER is not set CONFIG_64BIT_PHYS_ADDR=y CONFIG_CPU_HAS_LLSC=y CONFIG_CPU_HAS_SYNC=y @@ -121,6 +131,7 @@ CONFIG_GENERIC_HARDIRQS=y CONFIG_GENERIC_IRQ_PROBE=y CONFIG_CPU_SUPPORTS_HIGHMEM=y CONFIG_ARCH_FLATMEM_ENABLE=y +CONFIG_ARCH_POPULATES_NODE_MAP=y CONFIG_SELECT_MEMORY_MODEL=y CONFIG_FLATMEM_MANUAL=y # CONFIG_DISCONTIGMEM_MANUAL is not set @@ -128,9 +139,16 @@ CONFIG_FLATMEM_MANUAL=y CONFIG_FLATMEM=y CONFIG_FLAT_NODE_MEM_MAP=y # CONFIG_SPARSEMEM_STATIC is not set +# CONFIG_SPARSEMEM_VMEMMAP_ENABLE is not set +CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 CONFIG_RESOURCES_64BIT=y -CONFIG_ZONE_DMA_FLAG=1 +CONFIG_ZONE_DMA_FLAG=0 +CONFIG_VIRT_TO_BUS=y +# CONFIG_TICK_ONESHOT is not set +# CONFIG_NO_HZ is not set +# CONFIG_HIGH_RES_TIMERS is not set +CONFIG_GENERIC_CLOCKEVENTS_BUILD=y # CONFIG_HZ_48 is not set # CONFIG_HZ_100 is not set # CONFIG_HZ_128 is not set @@ -144,72 +162,90 @@ CONFIG_PREEMPT_NONE=y # CONFIG_PREEMPT_VOLUNTARY is not set # CONFIG_PREEMPT is not set # CONFIG_KEXEC is not set +CONFIG_SECCOMP=y CONFIG_LOCKDEP_SUPPORT=y CONFIG_STACKTRACE_SUPPORT=y CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" # -# Code maturity level options +# General setup # CONFIG_EXPERIMENTAL=y CONFIG_BROKEN_ON_SMP=y CONFIG_INIT_ENV_ARG_LIMIT=32 - -# -# General setup -# CONFIG_LOCALVERSION="" CONFIG_LOCALVERSION_AUTO=y CONFIG_SWAP=y CONFIG_SYSVIPC=y -# CONFIG_IPC_NS is not set CONFIG_SYSVIPC_SYSCTL=y # CONFIG_POSIX_MQUEUE is not set # CONFIG_BSD_PROCESS_ACCT is not set # CONFIG_TASKSTATS is not set -# CONFIG_UTS_NS is not set # CONFIG_AUDIT is not set # CONFIG_IKCONFIG is not set +CONFIG_LOG_BUF_SHIFT=14 +# CONFIG_CGROUPS is not set +# CONFIG_GROUP_SCHED is not set CONFIG_SYSFS_DEPRECATED=y +CONFIG_SYSFS_DEPRECATED_V2=y CONFIG_RELAY=y +# CONFIG_NAMESPACES is not set +# CONFIG_BLK_DEV_INITRD is not set # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set CONFIG_SYSCTL=y CONFIG_EMBEDDED=y CONFIG_SYSCTL_SYSCALL=y +CONFIG_SYSCTL_SYSCALL_CHECK=y CONFIG_KALLSYMS=y # CONFIG_KALLSYMS_EXTRA_PASS is not set CONFIG_HOTPLUG=y CONFIG_PRINTK=y CONFIG_BUG=y CONFIG_ELF_CORE=y +CONFIG_PCSPKR_PLATFORM=y +CONFIG_COMPAT_BRK=y CONFIG_BASE_FULL=y CONFIG_FUTEX=y +CONFIG_ANON_INODES=y CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y CONFIG_SHMEM=y -CONFIG_SLAB=y CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLAB=y +# CONFIG_SLUB is not set +# CONFIG_SLOB is not set +# CONFIG_PROFILING is not set +# CONFIG_MARKERS is not set +CONFIG_HAVE_OPROFILE=y +# CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS is not set +# CONFIG_HAVE_IOREMAP_PROT is not set +# CONFIG_HAVE_KPROBES is not set +# CONFIG_HAVE_KRETPROBES is not set +# CONFIG_HAVE_ARCH_TRACEHOOK is not set +# CONFIG_HAVE_DMA_ATTRS is not set +# CONFIG_USE_GENERIC_SMP_HELPERS is not set +# CONFIG_HAVE_CLK is not set +CONFIG_PROC_PAGE_MONITOR=y +# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set +CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y # CONFIG_TINY_SHMEM is not set CONFIG_BASE_SMALL=0 -# CONFIG_SLOB is not set - -# -# Loadable module support -# CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set CONFIG_MODULE_UNLOAD=y # CONFIG_MODULE_FORCE_UNLOAD is not set CONFIG_MODVERSIONS=y CONFIG_MODULE_SRCVERSION_ALL=y CONFIG_KMOD=y - -# -# Block layer -# CONFIG_BLOCK=y # CONFIG_LBD is not set # CONFIG_BLK_DEV_IO_TRACE is not set # CONFIG_LSF is not set +# CONFIG_BLK_DEV_BSG is not set +# CONFIG_BLK_DEV_INTEGRITY is not set # # IO Schedulers @@ -223,17 +259,17 @@ CONFIG_DEFAULT_AS=y # CONFIG_DEFAULT_CFQ is not set # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="anticipatory" +CONFIG_CLASSIC_RCU=y # # Bus options (PCI, PCMCIA, EISA, ISA, TC) # CONFIG_HW_HAS_PCI=y CONFIG_PCI=y +CONFIG_PCI_DOMAINS=y +# CONFIG_ARCH_SUPPORTS_MSI is not set +CONFIG_PCI_LEGACY=y CONFIG_MMU=y - -# -# PCCARD (PCMCIA/CardBus) support -# CONFIG_PCCARD=m # CONFIG_PCMCIA_DEBUG is not set CONFIG_PCMCIA=m @@ -249,10 +285,6 @@ CONFIG_PD6729=m # CONFIG_I82092 is not set # CONFIG_PCMCIA_AU1X00 is not set CONFIG_PCCARD_NONSTATIC=m - -# -# PCI Hotplug Support -# # CONFIG_HOTPLUG_PCI is not set # @@ -265,17 +297,13 @@ CONFIG_TRAD_SIGNALS=y # # Power management options # +CONFIG_ARCH_SUSPEND_POSSIBLE=y # CONFIG_PM is not set - -# -# Networking -# CONFIG_NET=y # # Networking options # -# CONFIG_NETDEBUG is not set CONFIG_PACKET=y # CONFIG_PACKET_MMAP is not set CONFIG_UNIX=y @@ -283,6 +311,7 @@ CONFIG_XFRM=y CONFIG_XFRM_USER=m # CONFIG_XFRM_SUB_POLICY is not set CONFIG_XFRM_MIGRATE=y +# CONFIG_XFRM_STATISTICS is not set CONFIG_NET_KEY=y CONFIG_NET_KEY_MIGRATE=y CONFIG_INET=y @@ -306,23 +335,19 @@ CONFIG_IP_PNP_BOOTP=y CONFIG_INET_XFRM_MODE_TRANSPORT=m CONFIG_INET_XFRM_MODE_TUNNEL=m CONFIG_INET_XFRM_MODE_BEET=m +CONFIG_INET_LRO=m CONFIG_INET_DIAG=y CONFIG_INET_TCP_DIAG=y # CONFIG_TCP_CONG_ADVANCED is not set CONFIG_TCP_CONG_CUBIC=y CONFIG_DEFAULT_TCP_CONG="cubic" CONFIG_TCP_MD5SIG=y - -# -# IP: Virtual Server Configuration -# # CONFIG_IP_VS is not set # CONFIG_IPV6 is not set -# CONFIG_INET6_XFRM_TUNNEL is not set -# CONFIG_INET6_TUNNEL is not set CONFIG_NETWORK_SECMARK=y CONFIG_NETFILTER=y # CONFIG_NETFILTER_DEBUG is not set +CONFIG_NETFILTER_ADVANCED=y # # Core Netfilter Configuration @@ -330,16 +355,15 @@ CONFIG_NETFILTER=y CONFIG_NETFILTER_NETLINK=m CONFIG_NETFILTER_NETLINK_QUEUE=m CONFIG_NETFILTER_NETLINK_LOG=m -CONFIG_NF_CONNTRACK_ENABLED=m -CONFIG_NF_CONNTRACK_SUPPORT=y -# CONFIG_IP_NF_CONNTRACK_SUPPORT is not set CONFIG_NF_CONNTRACK=m CONFIG_NF_CT_ACCT=y CONFIG_NF_CONNTRACK_MARK=y CONFIG_NF_CONNTRACK_SECMARK=y CONFIG_NF_CONNTRACK_EVENTS=y +# CONFIG_NF_CT_PROTO_DCCP is not set CONFIG_NF_CT_PROTO_GRE=m CONFIG_NF_CT_PROTO_SCTP=m +# CONFIG_NF_CT_PROTO_UDPLITE is not set CONFIG_NF_CONNTRACK_AMANDA=m CONFIG_NF_CONNTRACK_FTP=m CONFIG_NF_CONNTRACK_H323=m @@ -355,31 +379,38 @@ CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m CONFIG_NETFILTER_XT_TARGET_MARK=m CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m CONFIG_NETFILTER_XT_TARGET_NFLOG=m +# CONFIG_NETFILTER_XT_TARGET_RATEEST is not set CONFIG_NETFILTER_XT_TARGET_SECMARK=m CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=m CONFIG_NETFILTER_XT_TARGET_TCPMSS=m CONFIG_NETFILTER_XT_MATCH_COMMENT=m CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m +# CONFIG_NETFILTER_XT_MATCH_CONNLIMIT is not set CONFIG_NETFILTER_XT_MATCH_CONNMARK=m CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m CONFIG_NETFILTER_XT_MATCH_DCCP=m CONFIG_NETFILTER_XT_MATCH_DSCP=m CONFIG_NETFILTER_XT_MATCH_ESP=m CONFIG_NETFILTER_XT_MATCH_HELPER=m +# CONFIG_NETFILTER_XT_MATCH_IPRANGE is not set CONFIG_NETFILTER_XT_MATCH_LENGTH=m CONFIG_NETFILTER_XT_MATCH_LIMIT=m CONFIG_NETFILTER_XT_MATCH_MAC=m CONFIG_NETFILTER_XT_MATCH_MARK=m +# CONFIG_NETFILTER_XT_MATCH_OWNER is not set CONFIG_NETFILTER_XT_MATCH_POLICY=m CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m CONFIG_NETFILTER_XT_MATCH_QUOTA=m +# CONFIG_NETFILTER_XT_MATCH_RATEEST is not set CONFIG_NETFILTER_XT_MATCH_REALM=m CONFIG_NETFILTER_XT_MATCH_SCTP=m CONFIG_NETFILTER_XT_MATCH_STATE=m CONFIG_NETFILTER_XT_MATCH_STATISTIC=m CONFIG_NETFILTER_XT_MATCH_STRING=m CONFIG_NETFILTER_XT_MATCH_TCPMSS=m +# CONFIG_NETFILTER_XT_MATCH_TIME is not set +# CONFIG_NETFILTER_XT_MATCH_U32 is not set CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m # @@ -390,20 +421,13 @@ CONFIG_NF_CONNTRACK_PROC_COMPAT=y # CONFIG_IP_NF_QUEUE is not set # CONFIG_IP_NF_IPTABLES is not set # CONFIG_IP_NF_ARPTABLES is not set - -# -# DCCP Configuration (EXPERIMENTAL) -# # CONFIG_IP_DCCP is not set - -# -# SCTP Configuration (EXPERIMENTAL) -# -# CONFIG_IP_SCTP is not set - -# -# TIPC Configuration (EXPERIMENTAL) -# +CONFIG_IP_SCTP=m +# CONFIG_SCTP_DBG_MSG is not set +# CONFIG_SCTP_DBG_OBJCNT is not set +# CONFIG_SCTP_HMAC_NONE is not set +# CONFIG_SCTP_HMAC_SHA1 is not set +CONFIG_SCTP_HMAC_MD5=y # CONFIG_TIPC is not set # CONFIG_ATM is not set # CONFIG_BRIDGE is not set @@ -416,10 +440,6 @@ CONFIG_NF_CONNTRACK_PROC_COMPAT=y # CONFIG_LAPB is not set # CONFIG_ECONET is not set # CONFIG_WAN_ROUTER is not set - -# -# QoS and/or fair queueing -# # CONFIG_NET_SCHED is not set CONFIG_NET_CLS_ROUTE=y @@ -428,15 +448,25 @@ CONFIG_NET_CLS_ROUTE=y # # CONFIG_NET_PKTGEN is not set # CONFIG_HAMRADIO is not set +# CONFIG_CAN is not set # CONFIG_IRDA is not set # CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set + +# +# Wireless +# +# CONFIG_CFG80211 is not set +CONFIG_WIRELESS_EXT=y +CONFIG_WIRELESS_EXT_SYSFS=y +# CONFIG_MAC80211 is not set CONFIG_IEEE80211=m # CONFIG_IEEE80211_DEBUG is not set CONFIG_IEEE80211_CRYPT_WEP=m CONFIG_IEEE80211_CRYPT_CCMP=m -CONFIG_IEEE80211_SOFTMAC=m -# CONFIG_IEEE80211_SOFTMAC_DEBUG is not set -CONFIG_WIRELESS_EXT=y +# CONFIG_IEEE80211_CRYPT_TKIP is not set +# CONFIG_RFKILL is not set +# CONFIG_NET_9P is not set # # Device Drivers @@ -445,25 +475,21 @@ CONFIG_WIRELESS_EXT=y # # Generic Driver Options # +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_STANDALONE=y CONFIG_PREVENT_FIRMWARE_BUILD=y CONFIG_FW_LOADER=m +CONFIG_FIRMWARE_IN_KERNEL=y +CONFIG_EXTRA_FIRMWARE="" # CONFIG_SYS_HYPERVISOR is not set - -# -# Connector - unified userspace <-> kernelspace linker -# CONFIG_CONNECTOR=m - -# -# Memory Technology Devices (MTD) -# CONFIG_MTD=y # CONFIG_MTD_DEBUG is not set # CONFIG_MTD_CONCAT is not set CONFIG_MTD_PARTITIONS=y # CONFIG_MTD_REDBOOT_PARTS is not set # CONFIG_MTD_CMDLINE_PARTS is not set +# CONFIG_MTD_AR7_PARTS is not set # # User Modules And Translation Layers @@ -476,6 +502,7 @@ CONFIG_MTD_BLOCK=y # CONFIG_INFTL is not set # CONFIG_RFD_FTL is not set # CONFIG_SSFDC is not set +# CONFIG_MTD_OOPS is not set # # RAM/ROM/Flash chip drivers @@ -501,7 +528,6 @@ CONFIG_MTD_CFI_UTIL=y # CONFIG_MTD_RAM is not set # CONFIG_MTD_ROM is not set # CONFIG_MTD_ABSENT is not set -# CONFIG_MTD_OBSOLETE_CHIPS is not set # # Mapping drivers for chip access @@ -509,6 +535,7 @@ CONFIG_MTD_CFI_UTIL=y # CONFIG_MTD_COMPLEX_MAPPINGS is not set # CONFIG_MTD_PHYSMAP is not set CONFIG_MTD_ALCHEMY=y +# CONFIG_MTD_INTEL_VR_NOR is not set # CONFIG_MTD_PLATRAM is not set # @@ -526,30 +553,15 @@ CONFIG_MTD_ALCHEMY=y # CONFIG_MTD_DOC2000 is not set # CONFIG_MTD_DOC2001 is not set # CONFIG_MTD_DOC2001PLUS is not set - -# -# NAND Flash Device Drivers -# # CONFIG_MTD_NAND is not set - -# -# OneNAND Flash Device Drivers -# # CONFIG_MTD_ONENAND is not set # -# Parallel port support +# UBI - Unsorted block images # +# CONFIG_MTD_UBI is not set # CONFIG_PARPORT is not set - -# -# Plug and Play support -# -# CONFIG_PNPACPI is not set - -# -# Block devices -# +CONFIG_BLK_DEV=y # CONFIG_BLK_CPQ_DA is not set # CONFIG_BLK_CPQ_CISS_DA is not set # CONFIG_BLK_DEV_DAC960 is not set @@ -560,27 +572,25 @@ CONFIG_BLK_DEV_LOOP=y # CONFIG_BLK_DEV_NBD is not set # CONFIG_BLK_DEV_SX8 is not set # CONFIG_BLK_DEV_RAM is not set -# CONFIG_BLK_DEV_INITRD is not set CONFIG_CDROM_PKTCDVD=m CONFIG_CDROM_PKTCDVD_BUFFERS=8 # CONFIG_CDROM_PKTCDVD_WCACHE is not set CONFIG_ATA_OVER_ETH=m - -# -# Misc devices -# +# CONFIG_BLK_DEV_HD is not set +CONFIG_MISC_DEVICES=y +# CONFIG_PHANTOM is not set +# CONFIG_EEPROM_93CX6 is not set CONFIG_SGI_IOC4=m # CONFIG_TIFM_CORE is not set - -# -# ATA/ATAPI/MFM/RLL support -# +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_HP_ILO is not set +CONFIG_HAVE_IDE=y CONFIG_IDE=y CONFIG_IDE_MAX_HWIFS=4 CONFIG_BLK_DEV_IDE=y # -# Please see Documentation/ide.txt for help/info on IDE drives +# Please see Documentation/ide/ide.txt for help/info on IDE drives # # CONFIG_BLK_DEV_IDE_SATA is not set CONFIG_BLK_DEV_IDEDISK=y @@ -591,28 +601,31 @@ CONFIG_BLK_DEV_IDECS=m # CONFIG_BLK_DEV_IDETAPE is not set # CONFIG_BLK_DEV_IDEFLOPPY is not set # CONFIG_IDE_TASK_IOCTL is not set +CONFIG_IDE_PROC_FS=y # # IDE chipset support/bugfixes # CONFIG_IDE_GENERIC=y +# CONFIG_BLK_DEV_PLATFORM is not set +CONFIG_BLK_DEV_IDEDMA_SFF=y + +# +# PCI IDE chipsets support +# CONFIG_BLK_DEV_IDEPCI=y -# CONFIG_IDEPCI_SHARE_IRQ is not set +CONFIG_IDEPCI_PCIBUS_ORDER=y # CONFIG_BLK_DEV_OFFBOARD is not set CONFIG_BLK_DEV_GENERIC=y # CONFIG_BLK_DEV_OPTI621 is not set CONFIG_BLK_DEV_IDEDMA_PCI=y -# CONFIG_BLK_DEV_IDEDMA_FORCED is not set -# CONFIG_IDEDMA_PCI_AUTO is not set # CONFIG_BLK_DEV_AEC62XX is not set # CONFIG_BLK_DEV_ALI15X3 is not set # CONFIG_BLK_DEV_AMD74XX is not set # CONFIG_BLK_DEV_CMD64X is not set # CONFIG_BLK_DEV_TRIFLEX is not set -# CONFIG_BLK_DEV_CY82C693 is not set # CONFIG_BLK_DEV_CS5520 is not set # CONFIG_BLK_DEV_CS5530 is not set -# CONFIG_BLK_DEV_HPT34X is not set CONFIG_BLK_DEV_HPT366=y # CONFIG_BLK_DEV_JMICRON is not set # CONFIG_BLK_DEV_SC1200 is not set @@ -628,61 +641,37 @@ CONFIG_BLK_DEV_IT8213=m # CONFIG_BLK_DEV_TRM290 is not set # CONFIG_BLK_DEV_VIA82CXXX is not set CONFIG_BLK_DEV_TC86C001=m -# CONFIG_IDE_ARM is not set CONFIG_BLK_DEV_IDEDMA=y -# CONFIG_IDEDMA_IVB is not set -# CONFIG_IDEDMA_AUTO is not set -# CONFIG_BLK_DEV_HD is not set # # SCSI device support # CONFIG_RAID_ATTRS=m # CONFIG_SCSI is not set +# CONFIG_SCSI_DMA is not set # CONFIG_SCSI_NETLINK is not set - -# -# Serial ATA (prod) and Parallel ATA (experimental) drivers -# # CONFIG_ATA is not set - -# -# Multi-device support (RAID and LVM) -# # CONFIG_MD is not set - -# -# Fusion MPT device support -# # CONFIG_FUSION is not set # # IEEE 1394 (FireWire) support # -# CONFIG_IEEE1394 is not set # -# I2O device support +# Enable only one of the two stacks, unless you know what you are doing # +# CONFIG_FIREWIRE is not set +# CONFIG_IEEE1394 is not set # CONFIG_I2O is not set - -# -# Network device support -# CONFIG_NETDEVICES=y # CONFIG_DUMMY is not set # CONFIG_BONDING is not set +# CONFIG_MACVLAN is not set # CONFIG_EQUALIZER is not set # CONFIG_TUN is not set - -# -# ARCnet devices -# +# CONFIG_VETH is not set # CONFIG_ARCNET is not set - -# -# PHY device support -# CONFIG_PHYLIB=y # @@ -696,13 +685,13 @@ CONFIG_CICADA_PHY=m CONFIG_VITESSE_PHY=m CONFIG_SMSC_PHY=m # CONFIG_BROADCOM_PHY is not set +# CONFIG_ICPLUS_PHY is not set +# CONFIG_REALTEK_PHY is not set # CONFIG_FIXED_PHY is not set - -# -# Ethernet (10 or 100Mbit) -# +# CONFIG_MDIO_BITBANG is not set CONFIG_NET_ETHERNET=y # CONFIG_MII is not set +# CONFIG_AX88796 is not set CONFIG_MIPS_AU1X00_ENET=y # CONFIG_HAPPYMEAL is not set # CONFIG_SUNGEM is not set @@ -710,20 +699,21 @@ CONFIG_MIPS_AU1X00_ENET=y # CONFIG_NET_VENDOR_3COM is not set # CONFIG_SMC91X is not set # CONFIG_DM9000 is not set - -# -# Tulip family network device support -# # CONFIG_NET_TULIP is not set # CONFIG_HP100 is not set +# CONFIG_IBM_NEW_EMAC_ZMII is not set +# CONFIG_IBM_NEW_EMAC_RGMII is not set +# CONFIG_IBM_NEW_EMAC_TAH is not set +# CONFIG_IBM_NEW_EMAC_EMAC4 is not set # CONFIG_NET_PCI is not set - -# -# Ethernet (1000 Mbit) -# +# CONFIG_B44 is not set +CONFIG_NETDEV_1000=y # CONFIG_ACENIC is not set # CONFIG_DL2K is not set # CONFIG_E1000 is not set +# CONFIG_E1000E is not set +# CONFIG_IP1000 is not set +# CONFIG_IGB is not set # CONFIG_NS83820 is not set # CONFIG_HAMACHI is not set # CONFIG_YELLOWFIN is not set @@ -731,40 +721,34 @@ CONFIG_MIPS_AU1X00_ENET=y # CONFIG_SIS190 is not set # CONFIG_SKGE is not set # CONFIG_SKY2 is not set -# CONFIG_SK98LIN is not set +# CONFIG_VIA_VELOCITY is not set # CONFIG_TIGON3 is not set # CONFIG_BNX2 is not set CONFIG_QLA3XXX=m # CONFIG_ATL1 is not set - -# -# Ethernet (10000 Mbit) -# +# CONFIG_ATL1E is not set +CONFIG_NETDEV_10000=y # CONFIG_CHELSIO_T1 is not set CONFIG_CHELSIO_T3=m +# CONFIG_IXGBE is not set # CONFIG_IXGB is not set # CONFIG_S2IO is not set # CONFIG_MYRI10GE is not set CONFIG_NETXEN_NIC=m - -# -# Token Ring devices -# +# CONFIG_NIU is not set +# CONFIG_MLX4_CORE is not set +# CONFIG_TEHUTI is not set +# CONFIG_BNX2X is not set +# CONFIG_SFC is not set # CONFIG_TR is not set # -# Wireless LAN (non-hamradio) -# -# CONFIG_NET_RADIO is not set - -# -# PCMCIA network device support +# Wireless LAN # +# CONFIG_WLAN_PRE80211 is not set +# CONFIG_WLAN_80211 is not set +# CONFIG_IWLWIFI_LEDS is not set # CONFIG_NET_PCMCIA is not set - -# -# Wan interfaces -# # CONFIG_WAN is not set # CONFIG_FDDI is not set # CONFIG_HIPPI is not set @@ -777,21 +761,13 @@ CONFIG_PPP_DEFLATE=m # CONFIG_PPP_BSDCOMP is not set CONFIG_PPP_MPPE=m CONFIG_PPPOE=m +# CONFIG_PPPOL2TP is not set # CONFIG_SLIP is not set CONFIG_SLHC=m -# CONFIG_SHAPER is not set # CONFIG_NETCONSOLE is not set # CONFIG_NETPOLL is not set # CONFIG_NET_POLL_CONTROLLER is not set - -# -# ISDN subsystem -# # CONFIG_ISDN is not set - -# -# Telephony Support -# # CONFIG_PHONE is not set # @@ -799,6 +775,7 @@ CONFIG_SLHC=m # CONFIG_INPUT=y # CONFIG_INPUT_FF_MEMLESS is not set +# CONFIG_INPUT_POLLDEV is not set # # Userland interfaces @@ -808,7 +785,6 @@ CONFIG_INPUT_MOUSEDEV_PSAUX=y CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 # CONFIG_INPUT_JOYDEV is not set -# CONFIG_INPUT_TSDEV is not set CONFIG_INPUT_EVDEV=y # CONFIG_INPUT_EVBUG is not set @@ -818,6 +794,7 @@ CONFIG_INPUT_EVDEV=y # CONFIG_INPUT_KEYBOARD is not set # CONFIG_INPUT_MOUSE is not set # CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set # CONFIG_INPUT_TOUCHSCREEN is not set # CONFIG_INPUT_MISC is not set @@ -836,8 +813,9 @@ CONFIG_SERIO_RAW=m # Character devices # # CONFIG_VT is not set +CONFIG_DEVKMEM=y # CONFIG_SERIAL_NONSTANDARD is not set -# CONFIG_AU1X00_GPIO is not set +# CONFIG_NOZOMI is not set # # Serial drivers @@ -860,23 +838,10 @@ CONFIG_SERIAL_CORE_CONSOLE=y CONFIG_UNIX98_PTYS=y CONFIG_LEGACY_PTYS=y CONFIG_LEGACY_PTY_COUNT=256 - -# -# IPMI -# # CONFIG_IPMI_HANDLER is not set - -# -# Watchdog Cards -# -# CONFIG_WATCHDOG is not set # CONFIG_HW_RANDOM is not set -# CONFIG_RTC is not set -# CONFIG_GEN_RTC is not set -# CONFIG_DTLK is not set # CONFIG_R3964 is not set # CONFIG_APPLICOM is not set -# CONFIG_DRM is not set # # PCMCIA character devices @@ -884,131 +849,85 @@ CONFIG_LEGACY_PTY_COUNT=256 CONFIG_SYNCLINK_CS=m # CONFIG_CARDMAN_4000 is not set # CONFIG_CARDMAN_4040 is not set +# CONFIG_IPWIRELESS is not set # CONFIG_RAW_DRIVER is not set - -# -# TPM devices -# # CONFIG_TCG_TPM is not set - -# -# I2C support -# +CONFIG_DEVPORT=y # CONFIG_I2C is not set +# CONFIG_SPI is not set +# CONFIG_W1 is not set +# CONFIG_POWER_SUPPLY is not set +# CONFIG_HWMON is not set +# CONFIG_THERMAL is not set +# CONFIG_THERMAL_HWMON is not set +# CONFIG_WATCHDOG is not set # -# SPI support +# Sonics Silicon Backplane # -# CONFIG_SPI is not set -# CONFIG_SPI_MASTER is not set +CONFIG_SSB_POSSIBLE=y +# CONFIG_SSB is not set # -# Dallas's 1-wire bus +# Multifunction device drivers # -# CONFIG_W1 is not set +# CONFIG_MFD_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_HTC_PASIC3 is not set # -# Hardware Monitoring support +# Multimedia devices # -# CONFIG_HWMON is not set -# CONFIG_HWMON_VID is not set # -# Multimedia devices +# Multimedia core support # # CONFIG_VIDEO_DEV is not set +# CONFIG_DVB_CORE is not set +# CONFIG_VIDEO_MEDIA is not set # -# Digital Video Broadcasting Devices +# Multimedia drivers # -# CONFIG_DVB is not set +# CONFIG_DAB is not set # # Graphics support # -# CONFIG_FIRMWARE_EDID is not set +# CONFIG_DRM is not set +# CONFIG_VGASTATE is not set +# CONFIG_VIDEO_OUTPUT_CONTROL is not set # CONFIG_FB is not set # CONFIG_BACKLIGHT_LCD_SUPPORT is not set # -# Sound +# Display device support # +# CONFIG_DISPLAY_SUPPORT is not set # CONFIG_SOUND is not set - -# -# HID Devices -# +CONFIG_HID_SUPPORT=y # CONFIG_HID is not set - -# -# USB support -# +CONFIG_USB_SUPPORT=y CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB_ARCH_HAS_OHCI=y CONFIG_USB_ARCH_HAS_EHCI=y # CONFIG_USB is not set +# CONFIG_USB_OTG_WHITELIST is not set +# CONFIG_USB_OTG_BLACKLIST_HUB is not set # # NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support' # - -# -# USB Gadget Support -# # CONFIG_USB_GADGET is not set - -# -# MMC/SD Card support -# # CONFIG_MMC is not set - -# -# LED devices -# +# CONFIG_MEMSTICK is not set # CONFIG_NEW_LEDS is not set - -# -# LED drivers -# - -# -# LED Triggers -# - -# -# InfiniBand support -# +# CONFIG_ACCESSIBILITY is not set # CONFIG_INFINIBAND is not set - -# -# EDAC - error detection and reporting (RAS) (EXPERIMENTAL) -# - -# -# Real Time Clock -# +CONFIG_RTC_LIB=y # CONFIG_RTC_CLASS is not set - -# -# DMA Engine support -# -# CONFIG_DMA_ENGINE is not set - -# -# DMA Clients -# - -# -# DMA Devices -# - -# -# Auxiliary Display support -# - -# -# Virtualization -# +# CONFIG_DMADEVICES is not set +# CONFIG_UIO is not set # # File systems @@ -1024,7 +943,6 @@ CONFIG_EXT3_FS_POSIX_ACL=y CONFIG_EXT3_FS_SECURITY=y # CONFIG_EXT4DEV_FS is not set CONFIG_JBD=y -# CONFIG_JBD_DEBUG is not set CONFIG_FS_MBCACHE=y CONFIG_REISERFS_FS=m # CONFIG_REISERFS_CHECK is not set @@ -1035,14 +953,11 @@ CONFIG_REISERFS_FS_SECURITY=y # CONFIG_JFS_FS is not set CONFIG_FS_POSIX_ACL=y # CONFIG_XFS_FS is not set -# CONFIG_GFS2_FS is not set # CONFIG_OCFS2_FS is not set -# CONFIG_MINIX_FS is not set -# CONFIG_ROMFS_FS is not set +CONFIG_DNOTIFY=y CONFIG_INOTIFY=y CONFIG_INOTIFY_USER=y # CONFIG_QUOTA is not set -CONFIG_DNOTIFY=y CONFIG_AUTOFS_FS=m CONFIG_AUTOFS4_FS=m CONFIG_FUSE_FS=m @@ -1071,7 +986,6 @@ CONFIG_SYSFS=y CONFIG_TMPFS=y CONFIG_TMPFS_POSIX_ACL=y # CONFIG_HUGETLB_PAGE is not set -CONFIG_RAMFS=y CONFIG_CONFIGFS_FS=m # @@ -1088,22 +1002,21 @@ CONFIG_CONFIGFS_FS=m # CONFIG_JFFS2_FS is not set CONFIG_CRAMFS=m # CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set # CONFIG_HPFS_FS is not set # CONFIG_QNX4FS_FS is not set +# CONFIG_ROMFS_FS is not set # CONFIG_SYSV_FS is not set # CONFIG_UFS_FS is not set - -# -# Network File Systems -# +CONFIG_NETWORK_FILESYSTEMS=y CONFIG_NFS_FS=y # CONFIG_NFS_V3 is not set # CONFIG_NFS_V4 is not set -# CONFIG_NFS_DIRECTIO is not set +CONFIG_ROOT_NFS=y CONFIG_NFSD=m # CONFIG_NFSD_V3 is not set -# CONFIG_NFSD_TCP is not set -CONFIG_ROOT_NFS=y +# CONFIG_NFSD_V4 is not set CONFIG_LOCKD=y CONFIG_EXPORTFS=m CONFIG_NFS_COMMON=y @@ -1116,17 +1029,12 @@ CONFIG_SMB_FS=m # CONFIG_NCP_FS is not set # CONFIG_CODA_FS is not set # CONFIG_AFS_FS is not set -# CONFIG_9P_FS is not set # # Partition Types # # CONFIG_PARTITION_ADVANCED is not set CONFIG_MSDOS_PARTITION=y - -# -# Native Language Support -# CONFIG_NLS=m CONFIG_NLS_DEFAULT="iso8859-1" # CONFIG_NLS_CODEPAGE_437 is not set @@ -1167,33 +1075,25 @@ CONFIG_NLS_DEFAULT="iso8859-1" # CONFIG_NLS_KOI8_R is not set # CONFIG_NLS_KOI8_U is not set # CONFIG_NLS_UTF8 is not set - -# -# Distributed Lock Manager -# CONFIG_DLM=m -CONFIG_DLM_TCP=y -# CONFIG_DLM_SCTP is not set # CONFIG_DLM_DEBUG is not set # -# Profiling support -# -# CONFIG_PROFILING is not set - -# # Kernel hacking # CONFIG_TRACE_IRQFLAGS_SUPPORT=y # CONFIG_PRINTK_TIME is not set +CONFIG_ENABLE_WARN_DEPRECATED=y CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=1024 # CONFIG_MAGIC_SYSRQ is not set # CONFIG_UNUSED_SYMBOLS is not set # CONFIG_DEBUG_FS is not set # CONFIG_HEADERS_CHECK is not set # CONFIG_DEBUG_KERNEL is not set -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_CROSSCOMPILE=y +# CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y CONFIG_CMDLINE="" # @@ -1202,60 +1102,102 @@ CONFIG_CMDLINE="" CONFIG_KEYS=y CONFIG_KEYS_DEBUG_PROC_KEYS=y # CONFIG_SECURITY is not set +# CONFIG_SECURITY_FILE_CAPABILITIES is not set +CONFIG_CRYPTO=y # -# Cryptographic options +# Crypto core or helper # -CONFIG_CRYPTO=y CONFIG_CRYPTO_ALGAPI=y CONFIG_CRYPTO_BLKCIPHER=m CONFIG_CRYPTO_HASH=y CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_GF128MUL=m +CONFIG_CRYPTO_NULL=m +# CONFIG_CRYPTO_CRYPTD is not set +# CONFIG_CRYPTO_AUTHENC is not set +# CONFIG_CRYPTO_TEST is not set + +# +# Authenticated Encryption with Associated Data +# +# CONFIG_CRYPTO_CCM is not set +# CONFIG_CRYPTO_GCM is not set +# CONFIG_CRYPTO_SEQIV is not set + +# +# Block modes +# +CONFIG_CRYPTO_CBC=m +# CONFIG_CRYPTO_CTR is not set +# CONFIG_CRYPTO_CTS is not set +CONFIG_CRYPTO_ECB=m +CONFIG_CRYPTO_LRW=m +CONFIG_CRYPTO_PCBC=m +# CONFIG_CRYPTO_XTS is not set + +# +# Hash modes +# CONFIG_CRYPTO_HMAC=y CONFIG_CRYPTO_XCBC=m -CONFIG_CRYPTO_NULL=m + +# +# Digest +# +CONFIG_CRYPTO_CRC32C=m CONFIG_CRYPTO_MD4=m CONFIG_CRYPTO_MD5=y +CONFIG_CRYPTO_MICHAEL_MIC=m +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set CONFIG_CRYPTO_SHA1=m CONFIG_CRYPTO_SHA256=m CONFIG_CRYPTO_SHA512=m -CONFIG_CRYPTO_WP512=m CONFIG_CRYPTO_TGR192=m -CONFIG_CRYPTO_GF128MUL=m -CONFIG_CRYPTO_ECB=m -CONFIG_CRYPTO_CBC=m -CONFIG_CRYPTO_PCBC=m -CONFIG_CRYPTO_LRW=m -CONFIG_CRYPTO_DES=m -CONFIG_CRYPTO_FCRYPT=m -CONFIG_CRYPTO_BLOWFISH=m -CONFIG_CRYPTO_TWOFISH=m -CONFIG_CRYPTO_TWOFISH_COMMON=m -CONFIG_CRYPTO_SERPENT=m +CONFIG_CRYPTO_WP512=m + +# +# Ciphers +# CONFIG_CRYPTO_AES=m +CONFIG_CRYPTO_ANUBIS=m +CONFIG_CRYPTO_ARC4=m +CONFIG_CRYPTO_BLOWFISH=m +CONFIG_CRYPTO_CAMELLIA=m CONFIG_CRYPTO_CAST5=m CONFIG_CRYPTO_CAST6=m -CONFIG_CRYPTO_TEA=m -CONFIG_CRYPTO_ARC4=m +CONFIG_CRYPTO_DES=m +CONFIG_CRYPTO_FCRYPT=m CONFIG_CRYPTO_KHAZAD=m -CONFIG_CRYPTO_ANUBIS=m -CONFIG_CRYPTO_DEFLATE=m -CONFIG_CRYPTO_MICHAEL_MIC=m -CONFIG_CRYPTO_CRC32C=m -CONFIG_CRYPTO_CAMELLIA=m -# CONFIG_CRYPTO_TEST is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_SEED is not set +CONFIG_CRYPTO_SERPENT=m +CONFIG_CRYPTO_TEA=m +CONFIG_CRYPTO_TWOFISH=m +CONFIG_CRYPTO_TWOFISH_COMMON=m # -# Hardware crypto devices +# Compression # +CONFIG_CRYPTO_DEFLATE=m +# CONFIG_CRYPTO_LZO is not set +CONFIG_CRYPTO_HW=y +# CONFIG_CRYPTO_DEV_HIFN_795X is not set # # Library routines # CONFIG_BITREVERSE=y +# CONFIG_GENERIC_FIND_FIRST_BIT is not set CONFIG_CRC_CCITT=m CONFIG_CRC16=m +# CONFIG_CRC_T10DIF is not set +# CONFIG_CRC_ITU_T is not set CONFIG_CRC32=y +# CONFIG_CRC7 is not set CONFIG_LIBCRC32C=m CONFIG_ZLIB_INFLATE=m CONFIG_ZLIB_DEFLATE=m @@ -1266,3 +1208,4 @@ CONFIG_TEXTSEARCH_FSM=m CONFIG_PLIST=y CONFIG_HAS_IOMEM=y CONFIG_HAS_IOPORT=y +CONFIG_HAS_DMA=y -- 1.5.4.3 From tsbogend@alpha.franken.de Mon Aug 4 18:00:30 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 04 Aug 2008 18:00:37 +0100 (BST) Received: from elvis.franken.de ([193.175.24.41]:42413 "EHLO elvis.franken.de") by ftp.linux-mips.org with ESMTP id S20036141AbYHDRAa (ORCPT ); Mon, 4 Aug 2008 18:00:30 +0100 Received: from uucp (helo=solo.franken.de) by elvis.franken.de with local-bsmtp (Exim 3.36 #1) id 1KQ3Q5-0004Bu-00; Mon, 04 Aug 2008 19:00:29 +0200 Received: by solo.franken.de (Postfix, from userid 1000) id AAE18C2EAA; Mon, 4 Aug 2008 19:00:21 +0200 (CEST) From: Thomas Bogendoerfer Subject: [PATCH v2] IP27: Switch over to RTC class driver To: linux-mips@linux-mips.org cc: ralf@linux-mips.org Message-Id: <20080804170021.AAE18C2EAA@solo.franken.de> Date: Mon, 4 Aug 2008 19:00:21 +0200 (CEST) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20086 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: tsbogend@alpha.franken.de Precedence: bulk X-list: linux-mips This patchset removes some dead code and creates a platform device for the RTC class driver. Signed-off-by: Thomas Bogendoerfer --- Changes in v2: - use physical address for resource setup - use late_initcall until ioc3 resource conflict is resolved arch/mips/sgi-ip27/ip27-timer.c | 99 +++++++++------------------------------ 1 files changed, 22 insertions(+), 77 deletions(-) diff --git a/arch/mips/sgi-ip27/ip27-timer.c b/arch/mips/sgi-ip27/ip27-timer.c index 8b4e854..a5f0eec 100644 --- a/arch/mips/sgi-ip27/ip27-timer.c +++ b/arch/mips/sgi-ip27/ip27-timer.c @@ -13,12 +13,12 @@ #include #include #include +#include #include #include #include #include -#include #include #include #include @@ -28,51 +28,6 @@ #define TICK_SIZE (tick_nsec / 1000) -#if 0 -static int set_rtc_mmss(unsigned long nowtime) -{ - int retval = 0; - int real_seconds, real_minutes, cmos_minutes; - struct m48t35_rtc *rtc; - nasid_t nid; - - nid = get_nasid(); - rtc = (struct m48t35_rtc *)(KL_CONFIG_CH_CONS_INFO(nid)->memory_base + - IOC3_BYTEBUS_DEV0); - - rtc->control |= M48T35_RTC_READ; - cmos_minutes = BCD2BIN(rtc->min); - rtc->control &= ~M48T35_RTC_READ; - - /* - * Since we're only adjusting minutes and seconds, don't interfere with - * hour overflow. This avoids messing with unknown time zones but - * requires your RTC not to be off by more than 15 minutes - */ - real_seconds = nowtime % 60; - real_minutes = nowtime / 60; - if (((abs(real_minutes - cmos_minutes) + 15)/30) & 1) - real_minutes += 30; /* correct for half hour time zone */ - real_minutes %= 60; - - if (abs(real_minutes - cmos_minutes) < 30) { - real_seconds = BIN2BCD(real_seconds); - real_minutes = BIN2BCD(real_minutes); - rtc->control |= M48T35_RTC_SET; - rtc->sec = real_seconds; - rtc->min = real_minutes; - rtc->control &= ~M48T35_RTC_SET; - } else { - printk(KERN_WARNING - "set_rtc_mmss: can't update from %d to %d\n", - cmos_minutes, real_minutes); - retval = -1; - } - - return retval; -} -#endif - /* Includes for ioc3_init(). */ #include #include @@ -80,37 +35,6 @@ static int set_rtc_mmss(unsigned long nowtime) #include #include -unsigned long read_persistent_clock(void) -{ - unsigned int year, month, date, hour, min, sec; - struct m48t35_rtc *rtc; - nasid_t nid; - - nid = get_nasid(); - rtc = (struct m48t35_rtc *)(KL_CONFIG_CH_CONS_INFO(nid)->memory_base + - IOC3_BYTEBUS_DEV0); - - rtc->control |= M48T35_RTC_READ; - sec = rtc->sec; - min = rtc->min; - hour = rtc->hour; - date = rtc->date; - month = rtc->month; - year = rtc->year; - rtc->control &= ~M48T35_RTC_READ; - - sec = BCD2BIN(sec); - min = BCD2BIN(min); - hour = BCD2BIN(hour); - date = BCD2BIN(date); - month = BCD2BIN(month); - year = BCD2BIN(year); - - year += 1970; - - return mktime(year, month, date, hour, min, sec); -} - static void enable_rt_irq(unsigned int irq) { } @@ -286,6 +210,7 @@ void __cpuinit cpu_time_init(void) void __cpuinit hub_rtc_init(cnodeid_t cnode) { + /* * We only need to initialize the current node. * If this is not the current node then it is a cpuless @@ -301,3 +226,23 @@ void __cpuinit hub_rtc_init(cnodeid_t cnode) LOCAL_HUB_S(PI_RT_PEND_B, 0); } } + +static int __init sgi_ip27_rtc_devinit(void) +{ + struct resource res; + + memset(&res, 0, sizeof(res)); + res.start = XPHYSADDR(KL_CONFIG_CH_CONS_INFO(master_nasid)->memory_base + + IOC3_BYTEBUS_DEV0); + res.end = res.start + 32768; + res.flags = IORESOURCE_MEM; + + return IS_ERR(platform_device_register_simple("rtc-m48t35", -1, + &res, 1)); +} + +/* + * kludge make this a device_initcall after ioc3 resource conflicts + * are resolved + */ +late_initcall(sgi_ip27_rtc_devinit); From tsbogend@alpha.franken.de Mon Aug 4 18:00:54 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 04 Aug 2008 18:01:03 +0100 (BST) Received: from elvis.franken.de ([193.175.24.41]:42925 "EHLO elvis.franken.de") by ftp.linux-mips.org with ESMTP id S20036152AbYHDRAa (ORCPT ); Mon, 4 Aug 2008 18:00:30 +0100 Received: from uucp (helo=solo.franken.de) by elvis.franken.de with local-bsmtp (Exim 3.36 #1) id 1KQ3Q5-0004Bu-01; Mon, 04 Aug 2008 19:00:29 +0200 Received: by solo.franken.de (Postfix, from userid 1000) id CBA97C2EAC; Mon, 4 Aug 2008 19:00:25 +0200 (CEST) From: Thomas Bogendoerfer Subject: [PATCH v2] M48T35: new RTC driver To: rtc-linux@googlegroups.com, linux-mips@linux-mips.org cc: a.zummo@towertech.it, ralf@linux-mips.org Message-Id: <20080804170025.CBA97C2EAC@solo.franken.de> Date: Mon, 4 Aug 2008 19:00:25 +0200 (CEST) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20087 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: tsbogend@alpha.franken.de Precedence: bulk X-list: linux-mips This driver replaces the broken ip27-rtc driver in drivers/char and gives back RTC support for SGI IP27 machines. Signed-off-by: Thomas Bogendoerfer --- Changes in v2: - don't depend on SGI_IP27 - use rtc_valid_tm() for tm validation - resource is now a physical address and is ioremapped now - added kludge to workaround current ioc3 resource conflict drivers/rtc/Kconfig | 9 ++ drivers/rtc/Makefile | 1 + drivers/rtc/rtc-m48t35.c | 237 ++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 247 insertions(+), 0 deletions(-) diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig index 90ab738..2e5a578 100644 --- a/drivers/rtc/Kconfig +++ b/drivers/rtc/Kconfig @@ -405,6 +405,15 @@ config RTC_DRV_M48T86 This driver can also be built as a module. If so, the module will be called rtc-m48t86. +config RTC_DRV_M48T35 + tristate "ST M48T35" + help + If you say Y here you will get support for the + ST M48T35 RTC chip. + + This driver can also be built as a module, if so, the module + will be called "rtc-m48t35". + config RTC_DRV_M48T59 tristate "ST M48T59" help diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile index 18622ef..7d10cc0 100644 --- a/drivers/rtc/Makefile +++ b/drivers/rtc/Makefile @@ -36,6 +36,7 @@ obj-$(CONFIG_RTC_DRV_FM3130) += rtc-fm3130.o obj-$(CONFIG_RTC_DRV_ISL1208) += rtc-isl1208.o obj-$(CONFIG_RTC_DRV_M41T80) += rtc-m41t80.o obj-$(CONFIG_RTC_DRV_M41T94) += rtc-m41t94.o +obj-$(CONFIG_RTC_DRV_M48T35) += rtc-m48t35.o obj-$(CONFIG_RTC_DRV_M48T59) += rtc-m48t59.o obj-$(CONFIG_RTC_DRV_M48T86) += rtc-m48t86.o obj-$(CONFIG_RTC_DRV_MAX6900) += rtc-max6900.o diff --git a/drivers/rtc/rtc-m48t35.c b/drivers/rtc/rtc-m48t35.c new file mode 100644 index 0000000..e618b9a --- /dev/null +++ b/drivers/rtc/rtc-m48t35.c @@ -0,0 +1,237 @@ +/* + * Driver for the SGS-Thomson M48T35 Timekeeper RAM chip + * + * Copyright (C) 2000 Silicon Graphics, Inc. + * Written by Ulf Carlsson (ulfc@engr.sgi.com) + * + * Copyright (C) 2008 Thomas Bogendoerfer + * + * Based on code written by Paul Gortmaker. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include +#include +#include +#include + +#define DRV_VERSION "1.0" + +struct m48t35_rtc { + u8 pad[0x7ff8]; /* starts at 0x7ff8 */ + u8 control; + u8 sec; + u8 min; + u8 hour; + u8 day; + u8 date; + u8 month; + u8 year; +}; + +#define M48T35_RTC_SET 0x80 +#define M48T35_RTC_READ 0x40 + +struct m48t35_priv { + struct rtc_device *rtc; + struct m48t35_rtc __iomem *reg; + size_t size; + unsigned long baseaddr; + spinlock_t lock; +}; + +static int m48t35_read_time(struct device *dev, struct rtc_time *tm) +{ + struct m48t35_priv *priv = dev_get_drvdata(dev); + u8 control; + + /* + * Only the values that we read from the RTC are set. We leave + * tm_wday, tm_yday and tm_isdst untouched. Even though the + * RTC has RTC_DAY_OF_WEEK, we ignore it, as it is only updated + * by the RTC when initially set to a non-zero value. + */ + spin_lock_irq(&priv->lock); + control = readb(&priv->reg->control); + writeb(control | M48T35_RTC_READ, &priv->reg->control); + tm->tm_sec = readb(&priv->reg->sec); + tm->tm_min = readb(&priv->reg->min); + tm->tm_hour = readb(&priv->reg->hour); + tm->tm_mday = readb(&priv->reg->date); + tm->tm_mon = readb(&priv->reg->month); + tm->tm_year = readb(&priv->reg->year); + writeb(control, &priv->reg->control); + spin_unlock_irq(&priv->lock); + + tm->tm_sec = BCD2BIN(tm->tm_sec); + tm->tm_min = BCD2BIN(tm->tm_min); + tm->tm_hour = BCD2BIN(tm->tm_hour); + tm->tm_mday = BCD2BIN(tm->tm_mday); + tm->tm_mon = BCD2BIN(tm->tm_mon); + tm->tm_year = BCD2BIN(tm->tm_year); + + /* + * Account for differences between how the RTC uses the values + * and how they are defined in a struct rtc_time; + */ + tm->tm_year += 70; + if (tm->tm_year <= 69) + tm->tm_year += 100; + + tm->tm_mon--; + return rtc_valid_tm(tm); +} + +static int m48t35_set_time(struct device *dev, struct rtc_time *tm) +{ + struct m48t35_priv *priv = dev_get_drvdata(dev); + unsigned char mon, day, hrs, min, sec; + unsigned int yrs; + u8 control; + + yrs = tm->tm_year + 1900; + mon = tm->tm_mon + 1; /* tm_mon starts at zero */ + day = tm->tm_mday; + hrs = tm->tm_hour; + min = tm->tm_min; + sec = tm->tm_sec; + + if (!rtc_valid_tm(tm)) + return -EINVAL; + + if (yrs < 1970) + return -EINVAL; + + yrs -= 1970; + if (yrs > 255) /* They are unsigned */ + return -EINVAL; + + if (yrs > 169) + return -EINVAL; + + if (yrs >= 100) + yrs -= 100; + + sec = BIN2BCD(sec); + min = BIN2BCD(min); + hrs = BIN2BCD(hrs); + day = BIN2BCD(day); + mon = BIN2BCD(mon); + yrs = BIN2BCD(yrs); + + spin_lock_irq(&priv->lock); + control = readb(&priv->reg->control); + writeb(control | M48T35_RTC_SET, &priv->reg->control); + writeb(yrs, &priv->reg->year); + writeb(mon, &priv->reg->month); + writeb(day, &priv->reg->date); + writeb(hrs, &priv->reg->hour); + writeb(min, &priv->reg->min); + writeb(sec, &priv->reg->sec); + writeb(control, &priv->reg->control); + spin_unlock_irq(&priv->lock); + return 0; +} + +static const struct rtc_class_ops m48t35_ops = { + .read_time = m48t35_read_time, + .set_time = m48t35_set_time, +}; + +static int __devinit m48t35_probe(struct platform_device *pdev) +{ + struct rtc_device *rtc; + struct resource *res; + struct m48t35_priv *priv; + int ret = 0; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) + return -ENODEV; + priv = kzalloc(sizeof *priv, GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->size = res->end - res->start + 1; + /* + * kludge: remove the #ifndef after ioc3 resource + * conflicts are resolved + */ +#ifndef CONFIG_SGI_IP27 + if (!request_mem_region(res->start, priv->size, pdev->name)) { + ret = -EBUSY; + goto out; + } +#endif + priv->baseaddr = res->start; + priv->reg = ioremap(priv->baseaddr, priv->size); + if (!priv->reg) { + ret = -ENOMEM; + goto out; + } + spin_lock_init(&priv->lock); + rtc = rtc_device_register("m48t35", &pdev->dev, + &m48t35_ops, THIS_MODULE); + if (IS_ERR(rtc)) { + ret = PTR_ERR(rtc); + goto out; + } + priv->rtc = rtc; + platform_set_drvdata(pdev, priv); + return 0; + +out: + if (priv->rtc) + rtc_device_unregister(priv->rtc); + if (priv->reg) + iounmap(priv->reg); + if (priv->baseaddr) + release_mem_region(priv->baseaddr, priv->size); + kfree(priv); + return ret; +} + +static int __devexit m48t35_remove(struct platform_device *pdev) +{ + struct m48t35_priv *priv = platform_get_drvdata(pdev); + + rtc_device_unregister(priv->rtc); + iounmap(priv->reg); +#ifndef CONFIG_SGI_IP27 + release_mem_region(priv->baseaddr, priv->size); +#endif + kfree(priv); + return 0; +} + +static struct platform_driver m48t35_platform_driver = { + .driver = { + .name = "rtc-m48t35", + .owner = THIS_MODULE, + }, + .probe = m48t35_probe, + .remove = __devexit_p(m48t35_remove), +}; + +static int __init m48t35_init(void) +{ + return platform_driver_register(&m48t35_platform_driver); +} + +static void __exit m48t35_exit(void) +{ + platform_driver_unregister(&m48t35_platform_driver); +} + +MODULE_AUTHOR("Thomas Bogendoerfer "); +MODULE_DESCRIPTION("M48T35 RTC driver"); +MODULE_LICENSE("GPL"); +MODULE_VERSION(DRV_VERSION); +MODULE_ALIAS("platform:rtc-m48t35"); + +module_init(m48t35_init); +module_exit(m48t35_exit); From tsbogend@alpha.franken.de Mon Aug 4 18:44:39 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 04 Aug 2008 18:44:46 +0100 (BST) Received: from elvis.franken.de ([193.175.24.41]:3248 "EHLO elvis.franken.de") by ftp.linux-mips.org with ESMTP id S20039720AbYHDRoj (ORCPT ); Mon, 4 Aug 2008 18:44:39 +0100 Received: from uucp (helo=solo.franken.de) by elvis.franken.de with local-bsmtp (Exim 3.36 #1) id 1KQ46n-0003vC-00; Mon, 04 Aug 2008 19:44:37 +0200 Received: by solo.franken.de (Postfix, from userid 1000) id 7BD6FC2EAC; Mon, 4 Aug 2008 19:44:34 +0200 (CEST) From: Thomas Bogendoerfer Subject: [PATCH] Fix data bus error recovery To: linux-mips@linux-mips.org cc: ralf@linux-mips.org Message-Id: <20080804174434.7BD6FC2EAC@solo.franken.de> Date: Mon, 4 Aug 2008 19:44:34 +0200 (CEST) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20088 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: tsbogend@alpha.franken.de Precedence: bulk X-list: linux-mips With -ffunction-section the entries in __dbe_table aren't no longer sorted, so the lookup of exception addresses in do_be() failed for some addresses. To avoid this we now sort __dbe_table. Signed-off-by: Thomas Bogendoerfer --- arch/mips/kernel/traps.c | 6 ++++-- 1 files changed, 4 insertions(+), 2 deletions(-) diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index 426cced..1f579a8 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -373,8 +373,8 @@ void __noreturn die(const char * str, const struct pt_regs * regs) do_exit(SIGSEGV); } -extern const struct exception_table_entry __start___dbe_table[]; -extern const struct exception_table_entry __stop___dbe_table[]; +extern struct exception_table_entry __start___dbe_table[]; +extern struct exception_table_entry __stop___dbe_table[]; __asm__( " .section __dbe_table, \"a\"\n" @@ -1682,4 +1682,6 @@ void __init trap_init(void) flush_icache_range(ebase, ebase + 0x400); flush_tlb_handlers(); + + sort_extable(__start___dbe_table, __stop___dbe_table); } From tsbogend@alpha.franken.de Mon Aug 4 19:57:14 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 04 Aug 2008 19:57:22 +0100 (BST) Received: from elvis.franken.de ([193.175.24.41]:60339 "EHLO elvis.franken.de") by ftp.linux-mips.org with ESMTP id S20037484AbYHDS5O (ORCPT ); Mon, 4 Aug 2008 19:57:14 +0100 Received: from uucp (helo=solo.franken.de) by elvis.franken.de with local-bsmtp (Exim 3.36 #1) id 1KQ5F3-0000hZ-00; Mon, 04 Aug 2008 20:57:13 +0200 Received: by solo.franken.de (Postfix, from userid 1000) id E0CD4C315B; Mon, 4 Aug 2008 20:53:57 +0200 (CEST) From: Thomas Bogendoerfer Subject: [PATCH] Fix WARNING: at kernel/smp.c:290 To: linux-mips@linux-mips.org cc: ralf@linux-mips.org Message-Id: <20080804185357.E0CD4C315B@solo.franken.de> Date: Mon, 4 Aug 2008 20:53:57 +0200 (CEST) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20089 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: tsbogend@alpha.franken.de Precedence: bulk X-list: linux-mips trap_init issues flush_icache_range(), which uses ipi functions to get icache flushing done on all cpus. But this is done before interrupts are enabled and caused WARN_ON messages. This changeset introduces a new local_flush_icache_range() and uses it before interrupts (and additional CPUs) are enabled to avoid this problem. Signed-off-by: Thomas Bogendoerfer --- arch/mips/kernel/traps.c | 12 +++++++----- arch/mips/mm/c-r3k.c | 1 + arch/mips/mm/c-r4k.c | 18 ++++++++++++------ arch/mips/mm/c-tx39.c | 1 + arch/mips/mm/cache.c | 1 + arch/mips/mm/tlbex.c | 6 +++--- include/asm-mips/cacheflush.h | 1 + 7 files changed, 26 insertions(+), 14 deletions(-) diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index 1f579a8..6bee290 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -1200,7 +1200,7 @@ void *set_except_vector(int n, void *addr) if (n == 0 && cpu_has_divec) { *(u32 *)(ebase + 0x200) = 0x08000000 | (0x03ffffff & (handler >> 2)); - flush_icache_range(ebase + 0x200, ebase + 0x204); + local_flush_icache_range(ebase + 0x200, ebase + 0x204); } return (void *)old_handler; } @@ -1283,7 +1283,8 @@ static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs) *w = (*w & 0xffff0000) | (((u32)handler >> 16) & 0xffff); w = (u32 *)(b + ori_offset); *w = (*w & 0xffff0000) | ((u32)handler & 0xffff); - flush_icache_range((unsigned long)b, (unsigned long)(b+handler_len)); + local_flush_icache_range((unsigned long)b, + (unsigned long)(b+handler_len)); } else { /* @@ -1295,7 +1296,8 @@ static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs) w = (u32 *)b; *w++ = 0x08000000 | (((u32)handler >> 2) & 0x03fffff); /* j handler */ *w = 0; - flush_icache_range((unsigned long)b, (unsigned long)(b+8)); + local_flush_icache_range((unsigned long)b, + (unsigned long)(b+8)); } return (void *)old_handler; @@ -1515,7 +1517,7 @@ void __cpuinit per_cpu_trap_init(void) void __init set_handler(unsigned long offset, void *addr, unsigned long size) { memcpy((void *)(ebase + offset), addr, size); - flush_icache_range(ebase + offset, ebase + offset + size); + local_flush_icache_range(ebase + offset, ebase + offset + size); } static char panic_null_cerr[] __cpuinitdata = @@ -1680,7 +1682,7 @@ void __init trap_init(void) signal32_init(); #endif - flush_icache_range(ebase, ebase + 0x400); + local_flush_icache_range(ebase, ebase + 0x400); flush_tlb_handlers(); sort_extable(__start___dbe_table, __stop___dbe_table); diff --git a/arch/mips/mm/c-r3k.c b/arch/mips/mm/c-r3k.c index 27a5b46..5500c20 100644 --- a/arch/mips/mm/c-r3k.c +++ b/arch/mips/mm/c-r3k.c @@ -320,6 +320,7 @@ void __cpuinit r3k_cache_init(void) flush_cache_range = r3k_flush_cache_range; flush_cache_page = r3k_flush_cache_page; flush_icache_range = r3k_flush_icache_range; + local_flush_icache_range = r3k_flush_icache_range; flush_cache_sigtramp = r3k_flush_cache_sigtramp; local_flush_data_cache_page = local_r3k_flush_data_cache_page; diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index 71df339..6e99665 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -543,12 +543,8 @@ struct flush_icache_range_args { unsigned long end; }; -static inline void local_r4k_flush_icache_range(void *args) +static inline void local_r4k_flush_icache_range(unsigned long start, unsigned long end) { - struct flush_icache_range_args *fir_args = args; - unsigned long start = fir_args->start; - unsigned long end = fir_args->end; - if (!cpu_has_ic_fills_f_dc) { if (end - start >= dcache_size) { r4k_blast_dcache(); @@ -564,6 +560,15 @@ static inline void local_r4k_flush_icache_range(void *args) protected_blast_icache_range(start, end); } +static inline void local_r4k_flush_icache_range_ipi(void *args) +{ + struct flush_icache_range_args *fir_args = args; + unsigned long start = fir_args->start; + unsigned long end = fir_args->end; + + local_r4k_flush_icache_range(start, end); +} + static void r4k_flush_icache_range(unsigned long start, unsigned long end) { struct flush_icache_range_args args; @@ -571,7 +576,7 @@ static void r4k_flush_icache_range(unsigned long start, unsigned long end) args.start = start; args.end = end; - r4k_on_each_cpu(local_r4k_flush_icache_range, &args, 1); + r4k_on_each_cpu(local_r4k_flush_icache_range_ipi, &args, 1); instruction_hazard(); } @@ -1375,6 +1380,7 @@ void __cpuinit r4k_cache_init(void) local_flush_data_cache_page = local_r4k_flush_data_cache_page; flush_data_cache_page = r4k_flush_data_cache_page; flush_icache_range = r4k_flush_icache_range; + local_flush_icache_range = local_r4k_flush_icache_range; #if defined(CONFIG_DMA_NONCOHERENT) if (coherentio) { diff --git a/arch/mips/mm/c-tx39.c b/arch/mips/mm/c-tx39.c index a9f7f1f..39c8182 100644 --- a/arch/mips/mm/c-tx39.c +++ b/arch/mips/mm/c-tx39.c @@ -362,6 +362,7 @@ void __cpuinit tx39_cache_init(void) flush_cache_range = (void *) tx39h_flush_icache_all; flush_cache_page = (void *) tx39h_flush_icache_all; flush_icache_range = (void *) tx39h_flush_icache_all; + local_flush_icache_range = (void *) tx39h_flush_icache_all; flush_cache_sigtramp = (void *) tx39h_flush_icache_all; local_flush_data_cache_page = (void *) tx39h_flush_icache_all; diff --git a/arch/mips/mm/cache.c b/arch/mips/mm/cache.c index 034e850..1eb7c71 100644 --- a/arch/mips/mm/cache.c +++ b/arch/mips/mm/cache.c @@ -29,6 +29,7 @@ void (*flush_cache_range)(struct vm_area_struct *vma, unsigned long start, void (*flush_cache_page)(struct vm_area_struct *vma, unsigned long page, unsigned long pfn); void (*flush_icache_range)(unsigned long start, unsigned long end); +void (*local_flush_icache_range)(unsigned long start, unsigned long end); void (*__flush_cache_vmap)(void); void (*__flush_cache_vunmap)(void); diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c index 76da73a..979cf91 100644 --- a/arch/mips/mm/tlbex.c +++ b/arch/mips/mm/tlbex.c @@ -1273,10 +1273,10 @@ void __cpuinit build_tlb_refill_handler(void) void __cpuinit flush_tlb_handlers(void) { - flush_icache_range((unsigned long)handle_tlbl, + local_flush_icache_range((unsigned long)handle_tlbl, (unsigned long)handle_tlbl + sizeof(handle_tlbl)); - flush_icache_range((unsigned long)handle_tlbs, + local_flush_icache_range((unsigned long)handle_tlbs, (unsigned long)handle_tlbs + sizeof(handle_tlbs)); - flush_icache_range((unsigned long)handle_tlbm, + local_flush_icache_range((unsigned long)handle_tlbm, (unsigned long)handle_tlbm + sizeof(handle_tlbm)); } diff --git a/include/asm-mips/cacheflush.h b/include/asm-mips/cacheflush.h index d5c0f2f..03b1d69 100644 --- a/include/asm-mips/cacheflush.h +++ b/include/asm-mips/cacheflush.h @@ -63,6 +63,7 @@ static inline void flush_icache_page(struct vm_area_struct *vma, } extern void (*flush_icache_range)(unsigned long start, unsigned long end); +extern void (*local_flush_icache_range)(unsigned long start, unsigned long end); extern void (*__flush_cache_vmap)(void); From khickey@rmicorp.com Mon Aug 4 21:17:25 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 04 Aug 2008 21:17:28 +0100 (BST) Received: from mx1.razamicroelectronics.com ([63.111.213.197]:59311 "EHLO hq-ex-mb01.razamicroelectronics.com") by ftp.linux-mips.org with ESMTP id S20044521AbYHDURZ (ORCPT ); Mon, 4 Aug 2008 21:17:25 +0100 Received: from sark.razamicroelectronics.com ([10.8.0.254]) by hq-ex-mb01.razamicroelectronics.com with Microsoft SMTPSVC(6.0.3790.3959); Mon, 4 Aug 2008 13:17:16 -0700 Received: from localhost.localdomain (unknown [10.8.0.25]) by sark.razamicroelectronics.com (Postfix) with ESMTP id 0A3366DA536; Mon, 4 Aug 2008 15:09:38 -0500 (CDT) From: Kevin Hickey To: linux-mips@linux-mips.org Cc: ralf@linux-mips.org Subject: [PATCH 0/1] [MIPS] Add USB Device (OTG) support for Au1200 and Au1250 Date: Mon, 4 Aug 2008 15:17:31 -0500 Message-Id: <1217881052-18797-1-git-send-email-khickey@rmicorp.com> X-Mailer: git-send-email 1.5.4.3 In-Reply-To: <> References: <> X-OriginalArrivalTime: 04 Aug 2008 20:17:17.0023 (UTC) FILETIME=[172606F0:01C8F66F] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20090 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: khickey@rmicorp.com Precedence: bulk X-list: linux-mips The following is a patch adding preliminary device-only OTG support for the Au1200 and Au1250. It is made largely of code that I inherited that was never published. This is the largest patch I have submitted thus far, and the first one including a new driver. I welcome comments on anything in the code, as well as the format and presentation of the patch. I will happily rev this to meet the community's standards. Thanks. Kevin Hickey Alchemy Solutions RMI Corporation P: 512.691.8044 From khickey@rmicorp.com Mon Aug 4 21:17:44 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 04 Aug 2008 21:17:56 +0100 (BST) Received: from mx1.razamicroelectronics.com ([63.111.213.197]:59311 "EHLO hq-ex-mb01.razamicroelectronics.com") by ftp.linux-mips.org with ESMTP id S20044522AbYHDUR1 (ORCPT ); Mon, 4 Aug 2008 21:17:27 +0100 Received: from sark.razamicroelectronics.com ([10.8.0.254]) by hq-ex-mb01.razamicroelectronics.com with Microsoft SMTPSVC(6.0.3790.3959); Mon, 4 Aug 2008 13:17:16 -0700 Received: from localhost.localdomain (unknown [10.8.0.25]) by sark.razamicroelectronics.com (Postfix) with ESMTP id 17F6E7BEDDC; Mon, 4 Aug 2008 15:09:38 -0500 (CDT) From: Kevin Hickey To: linux-mips@linux-mips.org Cc: ralf@linux-mips.org, Kevin Hickey Subject: [PATCH] [MIPS] Add USB device (OTG) support for Au1200 and Au1250 Date: Mon, 4 Aug 2008 15:17:32 -0500 Message-Id: <1217881052-18797-2-git-send-email-khickey@rmicorp.com> X-Mailer: git-send-email 1.5.4.3 In-Reply-To: <1217881052-18797-1-git-send-email-khickey@rmicorp.com> References: <> <1217881052-18797-1-git-send-email-khickey@rmicorp.com> X-OriginalArrivalTime: 04 Aug 2008 20:17:17.0086 (UTC) FILETIME=[172FA3E0:01C8F66F] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20091 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: khickey@rmicorp.com Precedence: bulk X-list: linux-mips This patch adds support for the USB Device controller on the Au1200 and Au1250. With this patch, only basic device mode is supported; full On-The-Go functionality will be completed in a later release. Two new drivers are included; au1200_udc is the USB Device Controller driver and au1200_otg is the portmux driver. The portmux driver determines the mode of operation for the port based on software and hardware selectors. Currently, it only supports device mode. These drivers have been tested on a DB1200 board using the g_file_storage gadget. Signed-off-by: Kevin Hickey --- arch/mips/configs/db1200_defconfig | 21 + drivers/usb/core/Kconfig | 2 - drivers/usb/gadget/Kconfig | 49 +- drivers/usb/gadget/Makefile | 5 + drivers/usb/gadget/au1200_otg.c | 882 ++++++++ drivers/usb/gadget/au1200_otg.h | 138 ++ drivers/usb/gadget/au1200_udc.c | 4273 ++++++++++++++++++++++++++++++++++++ drivers/usb/gadget/au1200_udc.h | 869 ++++++++ drivers/usb/gadget/au1200_uoc.h | 1265 +++++++++++ drivers/usb/gadget/gadget_chips.h | 6 + include/linux/usb/otg.h | 7 +- 11 files changed, 7506 insertions(+), 11 deletions(-) create mode 100644 drivers/usb/gadget/au1200_otg.c create mode 100644 drivers/usb/gadget/au1200_otg.h create mode 100644 drivers/usb/gadget/au1200_udc.c create mode 100644 drivers/usb/gadget/au1200_udc.h create mode 100644 drivers/usb/gadget/au1200_uoc.h diff --git a/arch/mips/configs/db1200_defconfig b/arch/mips/configs/db1200_defconfig index d0dc2e8..7511fce 100644 --- a/arch/mips/configs/db1200_defconfig +++ b/arch/mips/configs/db1200_defconfig @@ -914,13 +914,34 @@ CONFIG_USB_ARCH_HAS_EHCI=y # CONFIG_USB_GADGET=m # CONFIG_USB_GADGET_DEBUG_FILES is not set +CONFIG_USB_GADGET_SELECTED=y +# CONFIG_USB_GADGET_AMD5536UDC is not set +# CONFIG_USB_GADGET_ATMEL_USBA is not set +# CONFIG_USB_GADGET_FSL_USB2 is not set # CONFIG_USB_GADGET_NET2280 is not set # CONFIG_USB_GADGET_PXA2XX is not set +# CONFIG_USB_GADGET_M66592 is not set # CONFIG_USB_GADGET_GOKU is not set # CONFIG_USB_GADGET_LH7A40X is not set # CONFIG_USB_GADGET_OMAP is not set +CONFIG_USB_GADGET_AU1200=y +CONFIG_USB_AU1200=m +# CONFIG_USB_GADGET_S3C2410 is not set # CONFIG_USB_GADGET_AT91 is not set # CONFIG_USB_GADGET_DUMMY_HCD is not set +CONFIG_USB_GADGET_DUALSPEED=y +CONFIG_USB_PORT_AU1200OTG=y +CONFIG_USB_AU1200OTG=m +CONFIG_USB_ZERO=m +# CONFIG_USB_ETH is not set +CONFIG_USB_GADGETFS=m +CONFIG_USB_FILE_STORAGE=m +# CONFIG_USB_FILE_STORAGE_TEST is not set +# CONFIG_USB_G_SERIAL is not set +# CONFIG_USB_MIDI_GADGET is not set +CONFIG_MMC=y +# CONFIG_MMC_DEBUG is not set +# CONFIG_MMC_UNSAFE_RESUME is not set # CONFIG_USB_GADGET_DUALSPEED is not set # diff --git a/drivers/usb/core/Kconfig b/drivers/usb/core/Kconfig index cc9f397..cc54c55 100644 --- a/drivers/usb/core/Kconfig +++ b/drivers/usb/core/Kconfig @@ -106,8 +106,6 @@ config USB_OTG bool depends on USB && EXPERIMENTAL select USB_SUSPEND - default n - config USB_OTG_WHITELIST bool "Rely on OTG Targeted Peripherals List" diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig index c6a8c6b..c2dd492 100644 --- a/drivers/usb/gadget/Kconfig +++ b/drivers/usb/gadget/Kconfig @@ -305,16 +305,28 @@ config USB_OMAP default USB_GADGET select USB_GADGET_SELECTED -config USB_OTG - boolean "OTG Support" - depends on USB_GADGET_OMAP && ARCH_OMAP_OTG && USB_OHCI_HCD +config USB_GADGET_AU1200 + boolean "AU1200 USB Device Controller" + depends on SOC_AU1200 + select USB_GADGET_DUALSPEED help - The most notable feature of USB OTG is support for a - "Dual-Role" device, which can act as either a device - or a host. The initial role choice can be changed - later, when two dual-role devices talk to each other. + The RMI Alchemy Au1200 and Au1250 SOCs include a full On-The-Go port + with USB 1.1 and USB 2.0 support. The device port supports 4 + bidirectional endpoints plus the default endpoint ep0. + + This driver provides the device mode for the On-The-Go port. The + port will not be active unless the au1200_otg driver is loaded or + built statically. + + Say "y" to link the driver statically, or "m" to build a + dynamically linked module called "au1200_udc" and force all + gadget drivers to also be dynamically linked. - Select this only if your OMAP board has a Mini-AB connector. +config USB_AU1200 + tristate + depends on USB_GADGET_AU1200 + default USB_GADGET + select USB_GADGET_SELECTED config USB_GADGET_S3C2410 boolean "S3C2410 USB Device Controller" @@ -397,6 +409,27 @@ config USB_GADGET_DUALSPEED Means that gadget drivers should include extra descriptors and code to handle dual-speed controllers. +config USB_PORT_AU1200OTG + boolean "AU1200 USB portmux control (On-The-Go support)" + depends on USB_GADGET_AU1200 || USB_EHCI_HCD || USB_OHCI_HCD + default n + help + The AU1200 and Au1200 USB device port can be used as either a host + port or a device port. This driver configures the port based on + hardware or software set criteria. It is required to be loaded for + au1200_udc to be useful. + + NOTE: Currently, only device-port mode is supported. Host-port and + other On The Go modes will be supported in a future release. + + Say "y" to link this driver statically or "m" to build a dynamically + linked module called "au1200_otg". + +config USB_AU1200OTG + tristate + depends on USB_PORT_AU1200OTG + default USB_AU1200 + # # USB Gadget Drivers # diff --git a/drivers/usb/gadget/Makefile b/drivers/usb/gadget/Makefile index fcb5cb9..d2af7cd 100644 --- a/drivers/usb/gadget/Makefile +++ b/drivers/usb/gadget/Makefile @@ -12,6 +12,7 @@ obj-$(CONFIG_USB_PXA25X) += pxa25x_udc.o obj-$(CONFIG_USB_PXA27X) += pxa27x_udc.o obj-$(CONFIG_USB_GOKU) += goku_udc.o obj-$(CONFIG_USB_OMAP) += omap_udc.o +obj-$(CONFIG_USB_AU1200) += au1200_udc.o obj-$(CONFIG_USB_LH7A40X) += lh7a40x_udc.o obj-$(CONFIG_USB_S3C2410) += s3c2410_udc.o obj-$(CONFIG_USB_AT91) += at91_udc.o @@ -49,3 +50,7 @@ obj-$(CONFIG_USB_G_PRINTER) += g_printer.o obj-$(CONFIG_USB_MIDI_GADGET) += g_midi.o obj-$(CONFIG_USB_CDC_COMPOSITE) += g_cdc.o +# +# AU1200 USB OTG options +# +obj-$(CONFIG_USB_AU1200OTG) += au1200_otg.o diff --git a/drivers/usb/gadget/au1200_otg.c b/drivers/usb/gadget/au1200_otg.c new file mode 100644 index 0000000..d47f48a --- /dev/null +++ b/drivers/usb/gadget/au1200_otg.c @@ -0,0 +1,882 @@ +/* + * Au1200 On The Go port driver. + */ + +/* + * Copyright (C) 2008 RMI Corporation (http://www.rmicorp.com) + * Author: Kevin Hickey (khickey@rmicorp.com) + * + * THIS SOFTWARE IS PROVIDED BY RMI Corporation 'AS IS' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO + * EVENT SHALL RMI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +/***************************************************************************** + * Includes + *****************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include + +#include +#include + +#include +#include +#include + +#define DRIVER_DESC "Au1200 USB OTG Controller" +#define DRIVER_NAME_FOR_PRINT OTG_DRIVER_NAME + +#include "au1200_otg.h" +#include "au1200_uoc.h" + + +/***************************************************************************** + * Function Declarations + *****************************************************************************/ + +static u32 otg_app_query(int); +static int au1200otg_set_peripheral (struct otg_transceiver *, + struct usb_gadget *); + + +/***************************************************************************** + * Data + *****************************************************************************/ + +static const char driver_name [] = OTG_DRIVER_NAME; +static const char driver_desc [] = DRIVER_DESC; + +static struct otg *the_controller; +static const char *transceiver_label = "au1200_otg"; + +static u32 init_state = 0; + +struct usb_otg_gadget_extension otg_gadget_extension = { + .request = NULL, + .query = otg_app_query, + .notify = NULL +}; + +static u32 state_mask; +u32 otg_tmr_high_count = 0; + +/***************************************************************************** + * Function Definitions + *****************************************************************************/ + +/** + * \brief + * fill OTG transceiver struct + * + * \param transceiver OTG transceiver + * + * \return void + */ +static inline void otg_init_transceiver (struct otg_transceiver *transceiver) +{ + transceiver->dev = NULL; + transceiver->label = transceiver_label; + transceiver->default_a = 0; + transceiver->state = OTG_STATE_UNDEFINED; + transceiver->prv_state = OTG_STATE_UNDEFINED; + transceiver->params = 0; + transceiver->otg_priv = (void *) &otg_gadget_extension; + transceiver->host = NULL; + transceiver->gadget = NULL; + transceiver->port_status = 0; + transceiver->port_change = 0; + transceiver->set_host = NULL; + transceiver->set_peripheral = au1200otg_set_peripheral; + transceiver->set_power = NULL; + transceiver->start_srp = NULL; + transceiver->start_hnp = NULL; +} + +/** + * \brief + * OTG state change + * + * subset of OTG states to support the gadget only or + * ID pin configuration + * + * \param otg OTG controller info + * \param event_code event that requested a state change + * \param pEvt_mask + * + * \return events that were not handled here + */ +u32 otg_change_state (struct otg *otg, u32 _event, u32 *pEvt_mask) +{ + u32 event_code = _event; + u32 uoc_status = get_status (otg); + + if (GOT_EVENT (OTG_GADGET_READY, event_code) && + ((otg->transceiver.state & OTG_STATE_MASK) != + OTG_STATE_UNDEFINED)) { + + /* Switch from "NO_B_DEVICE" states to normal operation or */ + /* deactivate operations in case gadget was unloaded */ + + CHANGE_STATE (otg, OTG_STATE_UNDEFINED, pEvt_mask); + } + if ((OTG_INT_TMX & event_code) && otg_tmr_high_count) { + + /* a long timer is running : decrement the high part */ + + restart_timer (otg); + otg_tmr_high_count--; + RES_EVENT (OTG_INT_TMX, event_code); + } + + do switch (otg->transceiver.state & OTG_STATE_MASK) { + + /* NOT_ASSIGNED (yet): init state, 1st time after loading */ + /* ====================================================== */ + + case OTG_STATE_UNDEFINED : + + CHECK_STATE (otg, OTG_STATE_UNDEFINED, pEvt_mask); + + if (IS_FLAG_RES (otg, OTG_FLAGS_ACTIV)) { + + /* seems to be the first time: let it run ! */ + + SET_FLAG (otg, OTG_FLAGS_ACTIV); + } + + /* muxer is still neutral */ + + RES_EVENT ((OTG_INT_IDC | OTG_INT_TMX), event_code); + + if (IS_FLAG_RES (otg, OTG_GADGET_READY)) { + + /* NOT_READY (substate): gadget drivers not ready */ + /* ============================================== */ + /* */ + /* check ID pin and enable host as needed */ + + if (IS_BIT_RES (OTG_STS_ID, uoc_status)) { + + /* ID pin connected: A-device (host) */ + + if (OTG_STATE_NO_B_DEVICE_A != + otg->transceiver.state) { + CHANGE_STATE (otg, + OTG_STATE_NO_B_DEVICE_A, + pEvt_mask); + } + } + else if (IS_BIT_SET (OTG_STS_ID, uoc_status)) { + + /* ID pin not connected: disable (neutral) */ + + if (OTG_STATE_NO_B_DEVICE_B != + otg->transceiver.state) { + CHANGE_STATE (otg, + OTG_STATE_NO_B_DEVICE_B, + pEvt_mask); + } + } + } + else if ((OTG_STATE_NO_B_DEVICE_A == + otg->transceiver.state) || + (OTG_STATE_NO_B_DEVICE_B == + otg->transceiver.state)) { + + /* Exit "not ready" state */ + /* ---------------------- */ + + RES_EVENT (OTG_GADGET_READY, event_code); + CHANGE_STATE (otg, OTG_STATE_UNDEFINED, pEvt_mask); + } + + /* ================================================== */ + + else { + + /* ID pin is not connected: B-device (peripheral) */ + + CHANGE_STATE (otg, OTG_STATE_B_IDLE, pEvt_mask); + } + break; + + case OTG_STATE_B_IDLE : + + /* B_IDLE: init state for B-devices */ + /* monitor VBus, no connection, no activity */ + + CHECK_STATE (otg, OTG_STATE_B_IDLE, pEvt_mask); + + if (IS_BIT_SET (OTG_STS_SESSVLD, uoc_status)) + { + /* Session valid => B_PERIPHERAL */ + + RES_EVENT (OTG_INT_SVC, event_code); + CHANGE_STATE (otg, OTG_STATE_B_PERIPHERAL, pEvt_mask); + if (otg_gadget_extension.notify) { + otg_gadget_extension.notify ( + OTG_GADGET_EVT_SVALID); + } + } + break; + + case OTG_STATE_B_PERIPHERAL : + + /* B_PERIPHERAL: connected to A-host, responding */ + /* VBus driven by A, remote activity */ + + CHECK_STATE (otg, OTG_STATE_B_PERIPHERAL, pEvt_mask); + + if (IS_BIT_RES (OTG_STS_SESSVLD, uoc_status)) + { + /* ID pin changed | ~Session valid => B_IDLE */ + + RES_EVENT ((OTG_INT_IDC | OTG_INT_SVC), event_code); + CHANGE_STATE (otg, OTG_STATE_B_IDLE, pEvt_mask); + if (otg_gadget_extension.notify) { + otg_gadget_extension.notify ( + OTG_GADGET_EVT_SVDROP); + } + } + break; + + /* unlikely */ default : + + /* something went wrong */ + + BUG (); + break; + } + while ((otg->transceiver.state ^ otg->transceiver.prv_state) & + OTG_STATE_MASK); + + DBG ("OTG-state change done\n"); + + return event_code; +} + +/** + * \brief + * OTG state change request + * + * \param dev OTG device info + * \param params + * + * \return void + */ +static inline void otg_req_state_chg (struct otg *otg, u32 params) +{ + u32 temp, tmp2; + unsigned long flags; + + local_irq_save (flags); + + /* disable global OTG interrupt, clear int status: */ + temp = ~((u32) OTG_INT_GLOBAL) & readl (&otg->regs->inten); + writel (temp, &otg->regs->inten); + tmp2 = readl (&otg->regs->intr); + writel (tmp2, &otg->regs->intr); + temp &= tmp2; + + /* update OTG state: */ + otg_change_state (otg, (params | temp), &temp); + + /* enable global OTG interrupt: */ + state_mask = ~temp & OTG_INT_ADDS; + writel ((OTG_INT_ADDS | temp | OTG_INT_GLOBAL), &otg->regs->inten); + local_irq_restore (flags); +} + +/** + * \brief + * OTG set transceiver: + * + * \param pointer to transceiver struct + * + * \return void + */ +int otg_set_transceiver (struct otg_transceiver *transceiver) +{ + struct otg *otg = the_controller; + + if (unlikely (transceiver != otg_to_transceiver (otg))) { + ERR ("USB OTG: unknown transceiver\n"); + return -EINVAL; + } + else { + return 0; + } +} + +/** + * \brief + * OTG get transceiver: provide info to others + * + * \param void + * + * \return pointer to transceiver struct + */ +struct otg_transceiver * otg_get_transceiver (void) +{ + return otg_to_transceiver (the_controller); +} + +/** + * \brief + * Bind/unbind the OTG controller to/from usb gadget + * + * \param transceiver this transceiver + * \param gadget usb gadget info + * + * \return error code + */ +static int au1200otg_set_peripheral (struct otg_transceiver *transceiver, + struct usb_gadget *gadget) +{ + struct otg *otg = the_controller; + int flag = 0; + + if (unlikely (transceiver != otg_to_transceiver (otg))) { + ERR ("USB OTG: unknown transceiver\n"); + return -EINVAL; + } + if (gadget) { + if (transceiver->gadget) { + ERR ("USB gadget: OTG driver already registered\n"); + return -EBUSY; + } + DBG ("bind OTG driver to USB gadget\n"); + transceiver->gadget = gadget; + SET_FLAG (otg, OTG_GADGET_READY | OTG_B_BUS_REQ); + + /* Now checking consistence ... */ + /* Depending on the driver loading sequence is possible */ + /* that the "Load state defaults" function was already */ + /* called so the state could be inconsistent. */ + if (transceiver->host && !transceiver->host->is_b_host) { + flag |= 1; + } + transceiver->gadget->is_a_peripheral = flag; + + if (IS_FLAG_SET (otg, OTG_FLAGS_ACTIV)) { + otg_req_state_chg (otg, OTG_GADGET_READY); + } + if (IS_BIT_SET (OTG_STS_SESSVLD, readl (&otg->regs->sts)) && + (otg->transceiver.state & OTG_STATE_MASK) + == OTG_STATE_B_PERIPHERAL) { + VDBG ("calling gadget: connect\n"); + otg_gadget_extension.notify (OTG_GADGET_EVT_SVALID); + } + return 0; + } + else { + DBG ("unbind OTG driver from USB gadget\n"); + RES_FLAG (otg, OTG_GADGET_READY | OTG_B_BUS_REQ); + if (IS_FLAG_SET (otg, OTG_FLAGS_ACTIV)) { + otg_req_state_chg (otg, OTG_GADGET_READY); + } + transceiver->gadget = NULL; + return 0; + } +} + +/** + * \brief + * OTG application query + * + * \param index select status info data + * + * \return status + */ +static u32 otg_app_query (int index) +{ + struct otg *otg = the_controller; + u32 temp = 0; + + if (index == 0) { + temp = otg->transceiver.params | + readl (&otg->regs->sts); + + if (((readl (&otg->regs->ctl) & OTG_CTL_MUX_MASK) == + OTG_CTL_ENABLE_UDC) && + ((temp & OTG_STS_PSUS) || (~temp & OTG_STS_VBUSVLD))) { + temp |= OTG_FLAGS_UDC_SUSP; + } + } + else if (index == 1) { + temp = otg->transceiver.state; + } + return (temp); +} + +/** + * \brief + * OTG ISR calling the main state machine + * + * \param irq IRQ number + * \param _dev + * \param r + * + * \return IRQ_HANDLED (system code) + */ +static irqreturn_t otg_isr (int irq, void *dev) +{ + struct otg *otg = (struct otg *) dev; + u32 interrupts, int_mask, temp; + + int_mask = readl (&otg->regs->inten); + if ((OTG_INT_GLOBAL & int_mask) && + (int_mask &= ~((u32) OTG_INT_GLOBAL)) && + (interrupts = int_mask & + (temp = readl (&otg->regs->intr)))) { + + writel (int_mask, &otg->regs->inten); + /* clear interrupt status */ + writel (temp, &otg->regs->intr); + /* filter out additional WA interrupts, they're done */ + /* don't want to see them in the state machine */ + + if (interrupts & ~state_mask) { + + /* events pending for the state machine */ + + otg_change_state (otg, (interrupts & ~state_mask), + &int_mask); + } + + /* enable interrupts and keep information about WA ints: */ + + state_mask = OTG_INT_ADDS & ~int_mask; + writel ((OTG_INT_ADDS | int_mask | OTG_INT_GLOBAL), + &otg->regs->inten); + } + return IRQ_HANDLED; +} + +/** + * \brief + * OTG probe: init hardware, register the driver + * + * \param otg otg controller info + * + * \return success + */ +static inline int __init otg_probe (struct otg *otg) +{ + int retval; + u32 temp; + int i; + + /* initialize the OTG controller */ + + VDBG ("OTG init ...\n"); + +#ifdef VERBOSE + /* print regs */ + print_regs (otg); +#endif + /* Make sure we'll remember the initial state */ + init_state = readl (&otg->regs->ctl); + VDBG (" OTG init state was %08x\n", init_state); + + /* turn on the OTG controller */ + writel ((init_state | OTG_CTL_PADEN), &otg->regs->ctl); + + /* initialize flags */ + otg->transceiver.params = 0; + + /* make sure all interrupts are disabled */ + writel (OTG_INT_DISALL, &otg->regs->inten); + writel (OTG_INT_ENALL, &otg->regs->intr); + + /* Set multiplexer to neutral, get power control, drop VBus */ + + if (((init_state & OTG_CTL_MUX_MASK) == OTG_CTL_ENABLE_UHC) && + ((((init_state & OTG_CTL_PPO) && (init_state & OTG_CTL_PPWR))) || + ((~init_state & OTG_CTL_PPO) && + (readl (&otg->regs->sts) & OTG_STS_SESSVLD)))) { + + /* VBus still powered try to discharge VBus and set timer */ + + DBG ("Setting init state, trying to discharge VBus ...\n"); + + for (i = 0; i < 4; i++) { + writel (TIMER_PERIOD, &otg->regs->tmr); + writel ((OTG_CTL_PADEN | OTG_CTL_IDSNSEN | + OTG_CTL_PPO | OTG_CTL_DISCHRG | + OTG_CTL_TMR_UNCOND), &otg->regs->ctl); + do { } + while (!(readl (&otg->regs->sts) & OTG_STS_TMH)); + } + writel ((OTG_CTL_PADEN | OTG_CTL_IDSNSEN | OTG_CTL_PPO), + &otg->regs->ctl); + writel (OTG_INT_ENALL, &otg->regs->intr); +#ifdef DEBUG + if (readl (&otg->regs->sts) & OTG_STS_SESSVLD) { + + DBG (" VBus still high, external host connected\n"); + } + else { + + DBG (" VBus discharged\n"); + } +#endif + } + else { + DBG ("Setting init state\n"); + + writel ((OTG_CTL_PADEN | OTG_CTL_IDSNSEN | OTG_CTL_PPO), + &otg->regs->ctl); + } + + VDBG ("OTG init done\n"); + + /* registering to the device driver */ + if (usb_gadget_register_otg (otg_get_transceiver)) { + ERR ("gadget driver registration failed\n"); + retval = -ENODEV; + goto err1; + } + + /* finally activate OTG functionality */ + /* Enable timer interrupt, start timer, set state */ + + SET_OTG_TIMER (otg, IDSNS_WAIT); + CHANGE_STATE (otg, OTG_STATE_UNDEFINED, &temp); + CHECK_STATE (otg, OTG_STATE_UNDEFINED, &temp); + +/*** HS-A0 WA: BUG-3885: VB_SESS_VLD value too high ***/ +/*** HS-A0 WA: BUG-3943: gadget suspend issue ***/ +/*** HS-A0 WA: BUG-3950: gadget needs disconnect notification ***/ + + /* clear all interrupts before enable */ + writel (readl (&otg->regs->intr), &otg->regs->intr); + + state_mask = ~temp & OTG_INT_ADDS; + writel ((OTG_INT_ADDS | temp | OTG_INT_GLOBAL), &otg->regs->inten); + + DBG ("OTG-HW initialized, now checking ID ...\n"); + + return 0; + + usb_gadget_unregister_otg (); +err1: + return retval; +} + +/** + * \brief + * OTG remove: deregister the driver, clean-up hardware + * + * \param otg otg controller info + * + * \return void + */ +static inline void __exit otg_remove (struct otg *otg) +{ + int muxer; + + /* unregistering from the usb gadget */ + usb_gadget_unregister_otg (); + + /* clean up the OTG controller */ + + /* Disable all interrupts */ + writel (OTG_INT_DISALL, &otg->regs->inten); + writel (OTG_INT_ENALL, &otg->regs->intr); + + /* reset state, terminate all connections */ + CHANGE_STATE (otg, OTG_STATE_UNDEFINED, &state_mask); + CHECK_STATE (otg, OTG_STATE_UNDEFINED, &state_mask); + otg->transceiver.params = 0; + + muxer = init_state & (OTG_CTL_ENABLE_UHC | OTG_CTL_ENABLE_UDC); + + + /* Don't assign the port to the device controller */ + + if (!(muxer ^ OTG_CTL_ENABLE_UDC)) { + + init_state &= ~((u32) (OTG_CTL_MUX_MASK | OTG_CTL_PUEN)); + muxer = OTG_CTL_DISABLE_ALL; + } + VDBG ("OTG writing back corrected init state: %08x\n", init_state); + + /* Now, that's the moment to remember */ + /* Set dev muxer and pull up bits, turn off the OTG controller */ + + /* Turn off VBus */ + AU1000GPIO_SET_BIT (USB_VBUS_GPIO); + writel (init_state, &otg->regs->ctl); + + if (!(muxer ^ OTG_CTL_ENABLE_UHC)) { + INFO ("disabling OTG-HW, port is assigned to host\n"); + } + else if (!(muxer ^ OTG_CTL_ENABLE_UDC)) { + INFO ("disabling OTG-HW, port is assigned to device\n"); + } + else { + INFO ("disabling OTG-HW, port is not assigned\n"); + } + + VDBG ("OTG exit: OTG-HW disabled\n"); + + if (!muxer) { + INFO ("OTG HW disabled, port is not assigned\n"); + } +} + +/** + * \brief + * OTG dev probe: enable, init controller hardware + * + * \param dev platform device info + * + * \return success + */ +static int __init otg_drv_probe (struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + struct otg *otg; + u32 resource, len, irq; + void *base; + int retval; + char buf [8] = {0,0,0,0,0,0,0,0}, *bufp; + + /* alloc, and start init */ + otg = (struct otg *) kmalloc (sizeof(struct otg), GFP_KERNEL); + if (!otg) { + ERR ("couldn't allocate memory for OTG driver\n"); + retval = -ENOMEM; + goto err1; + } + DBG ( "kmalloc: OTG driver: %p\n", otg); + + /* hold global device pointer */ + the_controller = otg; + + memset (otg, 0, sizeof(struct otg)); + spin_lock_init (&otg->lock); + + if (pdev->resource[0].flags != IORESOURCE_MEM) { + ERR ("resource is not IORESOURCE_MEM\n"); + retval = -ENOMEM; + goto err2; + } + resource = pdev->resource[0].start; + len = pdev->resource[0].end + 1 - pdev->resource[0].start; + if (pdev->resource[1].flags != IORESOURCE_IRQ) { + ERR ("resource is not IORESOURCE_IRQ\n"); + retval = -ENOMEM; + goto err2; + } + irq = pdev->resource[1].start; + + otg->pdev = pdev; + + au_writel ((au_readl (USB_MSR_BASE + USB_MSR_MCFG) | + (1 << USBMSRMCFG_GMEMEN)), (USB_MSR_BASE + USB_MSR_MCFG)); + au_readl (USB_MSR_BASE + USB_MSR_MCFG); + au_sync (); + + if (AU1000GPIO_INIT_BIT (USB_VBUS_GPIO)) + WARN ("Couldn't initialize power switch GPIO\n"); + otg->enabled = 1; + + if (!request_mem_region (resource, len, driver_name)) { + ERR ("controller already in use\n"); + retval = -EBUSY; + goto err3; + } + otg->region = 1; + + base = ioremap_nocache (resource, len); + if (!base) { + ERR ("couldn't map memory\n"); + retval = -EFAULT; + goto err4; + } + otg->regs = (struct otg_regs *) base; + bufp = buf; + + otg->chiprev = (u16) read_c0_prid() & 0xff; + + /* OTG transceiver info */ + otg->transceiver.dev = dev; + otg_init_transceiver (otg_to_transceiver (otg)); + + /* make sure all interrupts are disabled */ + writel (OTG_INT_DISALL, &otg->regs->inten); + writel (OTG_INT_ENALL, &otg->regs->intr); + readl (&otg->regs->inten); + + /* irq setup after old hardware is cleaned up */ + if (!irq) { + ERR ("No IRQ. Check system setup!\n"); + retval = -ENODEV; + goto err5; + } + snprintf (buf, sizeof buf, "%d", irq); + bufp = buf; + if (request_irq (irq, otg_isr, IRQF_SHARED, + driver_name, otg) != 0) { + ERR ("request interrupt %s failed\n", bufp); + retval = -EBUSY; + goto err5; + } + otg->got_irq = 1; + + /* done */ + INFO ("%s\n", driver_desc); + INFO ("irq %s, mem %08x, chip rev %02x (Au1200 %s)\n", + bufp, resource, otg->chiprev, (otg->chiprev ? "AC" : "AB")); + + if ((retval = otg_probe (otg)) == 0) { + dev_set_drvdata (dev, otg); + return 0; + } + + otg->got_irq = 0; + free_irq (irq, otg); +err5: + + otg->regs = NULL; + iounmap (base); +err4: + otg->region = 0; + release_mem_region (resource, len); +err3: + otg->enabled = 0; + AU1000GPIO_TERM_BIT (USB_VBUS_GPIO); + au_writel ((au_readl (USB_MSR_BASE + USB_MSR_MCFG) & + ~((u32) (1 << USBMSRMCFG_GMEMEN))), + (USB_MSR_BASE + USB_MSR_MCFG)); + au_readl (USB_MSR_BASE + USB_MSR_MCFG); + /* au_sync (); */ + udelay (1000); +err2: + otg->pdev = NULL; + the_controller = NULL; + DBG ( "kfree: OTG driver: %p\n", otg); + kfree (otg); +err1: + otg = NULL; + + return retval; +} + +/** + * \brief + * OTG dev remove: clean-up, disable controller hardware + * + * \param dev platform device info + * + * \return void + */ +static int __exit otg_drv_remove (struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + struct otg *otg = dev_get_drvdata (dev); + + otg_remove (otg); + + otg->got_irq = 0; + free_irq (pdev->resource[1].start, otg); + iounmap (otg->regs); + otg->regs = NULL; + otg->region = 0; + release_mem_region (pdev->resource[0].start, + pdev->resource[0].end + 1 + - pdev->resource[0].start); + otg->enabled = 0; + AU1000GPIO_TERM_BIT (USB_VBUS_GPIO); + + au_readl (USB_MSR_BASE + USB_MSR_MCFG); + au_sync (); + + otg->pdev = NULL; + the_controller = NULL; + DBG ( "kfree: OTG driver: %p\n", otg); + kfree (otg); + otg = NULL; + dev_set_drvdata(dev, NULL); + return 0; +} + + +/***************************************************************************** + * More data + *****************************************************************************/ + +/** + * \brief + * driver struct to be used for driver registration + * + */ +static struct device_driver otg_device_driver = { + .name = "au1xxx-uoc", + .bus = &platform_bus_type, + .probe = otg_drv_probe, + .remove = otg_drv_remove, +/* .suspend = otg_drv_suspend, */ +/* .resume = otg_drv_resume, */ +}; + +/* This comment closes the module definition from above. There can be multiple + definitions of this kind in a file. See the doxygen documentation for more + information. */ +/** \}*/ + +MODULE_DESCRIPTION (DRIVER_DESC); +MODULE_AUTHOR ("Kevin Hickey"); +MODULE_LICENSE ("GPL"); + +static int __init init (void) +{ + return (driver_register (&otg_device_driver)); +} +static void __exit cleanup (void) +{ + driver_unregister (&otg_device_driver); +} + +module_init (init); +module_exit (cleanup); diff --git a/drivers/usb/gadget/au1200_otg.h b/drivers/usb/gadget/au1200_otg.h new file mode 100644 index 0000000..2cbebf9 --- /dev/null +++ b/drivers/usb/gadget/au1200_otg.h @@ -0,0 +1,138 @@ +/* + * Declarations for the Au1200 On The Go port driver. + */ + +/* + * Copyright (C) 2008 RMI Corporation (http://www.rmicorp.com) + * Author: Kevin Hickey (khickey@rmicorp.com) + * + * THIS SOFTWARE IS PROVIDED BY RMI Corporation 'AS IS' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO + * EVENT SHALL RMI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#ifndef AU1200_OTG_H +#define AU1200_OTG_H + +/********************************** + * OTG sub-state definitions +***********************************/ + +#define OTG_STATE_MASK 0x0F + +#define OTG_STATE_NO_B_DEVICE_A (0x60 | OTG_STATE_UNDEFINED) +#define OTG_STATE_NO_B_DEVICE_B (0x40 | OTG_STATE_UNDEFINED) + +#define OTG_STATE_B_HOST_WT (0x10 | OTG_STATE_B_HOST) +#define OTG_STATE_B_PERIPHERAL_WT (0x10 | OTG_STATE_B_PERIPHERAL) +#define OTG_STATE_B_PERIPHERAL_DC (0x20 | OTG_STATE_B_PERIPHERAL) +#define OTG_STATE_B_SRP_WAIT_SE0 (0x10 | OTG_STATE_B_SRP_INIT) +#define OTG_STATE_B_SRP_D_PULSE (0x20 | OTG_STATE_B_SRP_INIT) +#define OTG_STATE_B_SRP_V_PULSE (0x30 | OTG_STATE_B_SRP_INIT) +#define OTG_STATE_B_SRP_V_DCHRG (0x40 | OTG_STATE_B_SRP_INIT) +#define OTG_STATE_B_SRP_WAIT_VBUS (0x50 | OTG_STATE_B_SRP_INIT) + +#define OTG_STATE_A_IDLE_WAIT_DP (0x10 | OTG_STATE_A_IDLE) +#define OTG_STATE_A_IDLE_WAIT_VP (0x20 | OTG_STATE_A_IDLE) +#define OTG_STATE_A_IDLE_WAIT_MP (0x30 | OTG_STATE_A_IDLE) +#define OTG_STATE_A_IDLE_WAIT_DV (0x40 | OTG_STATE_A_IDLE) +#define OTG_STATE_A_WAIT_BCON_VB (0x10 | OTG_STATE_A_WAIT_BCON) +#define OTG_STATE_A_WAIT_VFALL_DN (0x10 | OTG_STATE_A_WAIT_VFALL) + + +/********************************** +* typical timer values +**********************************/ + +#define OTG_TMR_WAIT_VFALL 10 /* ( ) A waits for VBus */ +#define OTG_TMR_A_WAIT_VRISE 100 /* ( ) A waits for VBus */ +#define OTG_TMR_A_WAIT_BCON 200 /* ( ) A waits for B-connect (1.. s) */ +#define OTG_TMR_A_IDLE_BDIS 250 /* (ms) A waits for B-disc (200.. ms) */ +#define OTG_TMR_B_WAIT_ADISCON 600 /* (us) B waits for A to disconnect <1ms */ +#define OTG_TMR_B_ACON_BRST 200 /* (us) B waits before starting reset */ +#define OTG_TMR_B_ASE0_BRST 5 /* (ms) B waits for A-conn (3.125.. ms) */ +#define OTG_TMR_B_AIDL_BDIS 50 /* (ms) B waits before dc (5..150ms) */ +#define OTG_TMR_SRP_WAIT_SE0 2 /* ( ) B SRP idle wait */ +#define OTG_TMR_SRP_WAIT_DP 7 /* (ms) B SRP D_PULSE (5..10ms) */ +#define OTG_TMR_SRP_WAIT_VP 80 /* (ms) B SRP V_PULSE (5..100ms) */ +#define OTG_TMR_SRP_DCHRG_V 30 /* ( ) B SRP VBus discharge */ +#define OTG_TMR_SRP_WAIT_VRS 5800 /* (ms) B SRP waits for VBus (5..6s) */ +#define OTG_TMR_ASRP_WAIT_MP 4 /* ( ) A SRP min. pulse */ +#define OTG_TMR_ASRP_WAIT_DP 10 /* (ms) A SRP D_PULSE TO */ +#define OTG_TMR_ASRP_WAIT_VP 200 /* (ms) A SRP V_PULSE TO */ +#define OTG_TMR_ASRP_WAIT_DV 200 /* ( ) A SRP waits for V_PULSE */ +#define OTG_TMR_A_BCON_VB 50 /* ( ) A waits for VBus after connect */ + +#define OTG_TMR_IDSNS_WAIT 10 /* (ms) ID sense wait */ +#define TIMER_PERIOD 1000 /* 10 ms, if longer than 10ms */ + +/********************************** + * OTG state parameters + **********************************/ + +#define OTG_HOST_READY (1<<20) /* indicates a USB host driver is */ + /* running */ +#define OTG_GADGET_READY (1<<21) /* indicates a USB gadget driver is */ + /* running */ +#define OTG_A_BUS_REQ (1<<22) /* used by appl-SW to request a */ + /* VBus rise, auto-reset by driver */ +#define OTG_A_BUS_DROP (1<<23) /* used by appl-SW to request a */ + /* VBus drop, auto-reset by driver */ +#define OTG_A_CLR_ERR (1<<24) /* used by appl-SW to request VBerr */ + /* clean-up, auto-reset by driver */ +#define OTG_AB_HNP_REQ (1<<25) /* used by appl-SW to initiate */ + /* HNP, auto-reset by driver */ +#define OTG_B_BUS_REQ (1<<26) /* used by appl-SW to request */ + /* B-device functionality, ... */ +#define OTG_B_BUS_DIS (1<<27) /* used by appl-SW to request */ + /* disable B-device functionality */ +#define OTG_B_aSSN_REQ (1<<28) /* used by appl-SW to initiate SRP, */ + /* auto-reset by the driver */ +#define OTG_B_SRP_ERROR (1<<29) /* indicates invalid HW conditions */ + /* during SRP, reset by writing "1" */ +#define OTG_A_VBUS_FAILED (1<<30) /* indicates a VBus error, reset by */ + /* writing "1", when setting */ + /* CLR_ERR or when leaving A-states */ +#define OTG_UDC_RWK_REQ (1<<31) /* call UDC function to force a */ + /* remote wake-up */ + +#define SW_REQUEST_MASK (OTG_A_BUS_REQ | OTG_A_BUS_DROP | \ + OTG_A_CLR_ERR | OTG_B_aSSN_REQ | \ + OTG_B_BUS_REQ | OTG_B_BUS_DIS | \ + OTG_UDC_RWK_REQ) + +/*********************************************************************/ + +/* + * gadget events for notify function + */ +#define OTG_GADGET_EVT_SVDROP (1<<0) /* Session valid drop */ +#define OTG_GADGET_EVT_SVALID (1<<1) /* Session valid */ +#define OTG_GADGET_REQ_WAKE (1<<2) /* Request remote wake-up */ +#define OTG_FLAGS_UDC_SUSP (1<<17) /* gadget phy suspended */ + +/***************************************************************************** +* Data +*****************************************************************************/ +struct usb_otg_gadget_extension { + int (*request) (u32); /* function call for state change requests */ + u32 (*query) (int); /* function call to query state */ + void (*notify) (u32); /* filled in by gadget for notification */ +}; + +#endif /* AU1200_OTG_H */ diff --git a/drivers/usb/gadget/au1200_udc.c b/drivers/usb/gadget/au1200_udc.c new file mode 100644 index 0000000..17804ae --- /dev/null +++ b/drivers/usb/gadget/au1200_udc.c @@ -0,0 +1,4273 @@ +/* + * RMI Au1200 UDC high/full speed USB device controller. + */ + +/* + * Copyright (C) 2008 RMI Corporation (http://www.rmicorp.com) + * Author: Kevin Hickey (khickey@rmicorp.com) + * + * Adapted from the AMD5536 UDC module. + * + * THIS SOFTWARE IS PROVIDED BY RMI Corporation 'AS IS' AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO + * EVENT SHALL RMI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, + * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, + * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +/***************************************************************************** + * Defines + *****************************************************************************/ + +/* debug control */ +/* #define UDC_DEBUG */ +/* #define UDC_VERBOSE */ +/* #define UDC_REGISTER_DUMP */ + +/* Driver strings */ +#define UDC_MOD_DESCRIPTION "RMI Au1200 UDC - USB Device Controller" + +/***************************************************************************** + * Includes + *****************************************************************************/ +/* system */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +/* MIPS config */ +#include + +/* gadget stack */ +#include +#include +#include + +/* udc specific */ +#include "au1200_udc.h" + +/* use RDE timer */ +#define UDC_USE_TIMER + +/***************************************************************************** + * Static Function Declarations + *****************************************************************************/ +void udc_tasklet_disconnect(unsigned long); +static int udc_rxfifo_read_dwords(struct udc* dev, u32* buf, int dwords); +static void empty_req_queue (struct udc_ep *); +static int udc_probe (struct udc* dev); +static void udc_basic_init (struct udc *dev); +static void udc_setup_endpoints (struct udc *dev); +static void udc_soft_reset(struct udc* dev); +static inline struct udc_request* udc_alloc_bna_dummy(struct udc_ep* ep); +static inline void udc_init_bna_dummy(struct udc_request *req); +static void udc_free_request (struct usb_ep *usbep, struct usb_request *usbreq); +static struct udc_data_dma* udc_get_last_dma_desc(struct udc_request* req); +static u32 udc_get_ppbdu_rxbytes(struct udc_request* req); +static int udc_free_dma_chain(struct udc* dev, struct udc_request* req); +static int udc_create_dma_chain(struct udc_ep* ep, struct udc_request* req, unsigned long buf_len, int gfp_flags); +static inline int startup_registers(struct udc* dev); +#ifdef UDC_USE_TIMER +void udc_timer_function(unsigned long v); +void udc_pollstall_timer_function(unsigned long v); +#endif +static int udc_remote_wakeup(struct udc* dev); +static int udc_suspend(struct udc* dev); +static int udc_resume(struct udc* dev); + +/***************************************************************************** + * Data + *****************************************************************************/ +/* description */ +static const char mod_desc [] = UDC_MOD_DESCRIPTION; +static const char name [] = DRIVER_NAME_FOR_PRINT; + +/* structure to hold endpoint function pointers */ +static struct usb_ep_ops udc_ep_ops; + +/* received setup data */ +static union udc_setup_data setup_data; + +/* pointer to device object */ +static struct udc *udc; + +/* irq spin lock for soft reset */ +spinlock_t udc_irq_spinlock; +/* stall spin lock */ +spinlock_t udc_stall_spinlock; + +/* this is used for dma chaining */ +static int udc_gfp_flags = 0; + +/* slave mode: pending bytes in rx fifo after nyet, +used if EPIN irq came but no req was available */ +static unsigned int udc_rxfifo_pending = 0; + +/* count soft resets after suspend to avoid loop */ +static int soft_reset_occured = 0; +static int soft_reset_after_usbreset_occured = 0; + +#ifdef UDC_USE_TIMER +/* timer */ +static struct timer_list udc_timer; +static int stop_timer = 0; +int set_rde = -1; +DECLARE_COMPLETION(on_exit); +static struct timer_list udc_pollstall_timer; +static int stop_pollstall_timer = 0; +DECLARE_COMPLETION(on_pollstall_exit); +#endif + +/* tasklet for usb disconnect */ +DECLARE_TASKLET(disconnect_tasklet, udc_tasklet_disconnect, (unsigned long) &udc); + +/* CNAK pending field: bit0 = ep0in, bit16 = ep0out */ +static u32 cnak_pending = 0; +#define UDC_QUEUE_CNAK(ep, num) \ + if (readl(&((ep)->regs->ctl)) & UDC_BIT(UDC_EPCTL_NAK)) { \ + DBG("NAK could not be cleared for ep%d\n", num); \ + cnak_pending |= 1 << (num); \ + (ep)->naking = 1; \ + } \ + else \ + cnak_pending = cnak_pending & (~(1<<(num))); + +/* otg registering count */ +static u32 otg_reg_count = 0; + +/* gadget registering count */ +static u32 gadget_bind_count = 0; + +/* endpoint names used for print */ +static const char ep0_string[] = "ep0in"; +static const char *ep_string[] = { + ep0_string, + "ep1in-int", "ep2in-bulk", "ep3in-bulk", "ep4in-bulk", "ep5in-bulk", + "ep6in-bulk", "ep7in-bulk", "ep8in-bulk", "ep9in-bulk", "ep10in-bulk", + "ep11in-bulk", "ep12in-bulk", "ep13in-bulk", "ep14in-bulk", + "ep15in-bulk", "ep0out", "ep1out-bulk", "ep2out-bulk", "ep3out-bulk", + "ep4out-bulk", "ep5out-bulk", "ep6out-bulk", "ep7out-bulk", + "ep8out-bulk", "ep9out-bulk", "ep10out-bulk", "ep11out-bulk", + "ep12out-bulk", "ep13out-bulk", "ep14out-bulk", "ep15out-bulk" +}; + + +#ifdef UDC_DEBUG +/* data for debuging only */ +static unsigned long no_pref_req = 0; +static unsigned long no_req = 0; +static u32 same_cfg = 0; +static u32 num_enums = 0; +#endif + +/****** following flags can be set by module parameters */ +/* DMA usage flag */ +static int use_dma = 1; +/* packet per buffer dma */ +static int use_dma_ppb = 1; +/* with per descr. update */ +static int use_dma_ppb_du = 0; +/* buffer fill mode */ +static int use_dma_bufferfill_mode = 0; +/* full speed only mode */ +static int use_fullspeed = 0; +/* tx buffer size for high speed */ +static unsigned long hs_tx_buf = UDC_EPIN_BUFF_SIZE; + +/* module parameters */ +module_param (use_dma, bool, S_IRUGO ); +MODULE_PARM_DESC (use_dma, "true for DMA"); +module_param (use_dma_ppb, bool, S_IRUGO ); +MODULE_PARM_DESC (use_dma_ppb, "true for DMA in packet per buffer mode"); +module_param (use_dma_ppb_du, bool, S_IRUGO ); +MODULE_PARM_DESC (use_dma_ppb_du, "true for DMA in packet per buffer mode with descriptor update"); +module_param (use_fullspeed, bool, S_IRUGO ); +MODULE_PARM_DESC (use_fullspeed, "true for fullspeed only"); +module_param (hs_tx_buf, long, S_IRUGO ); +MODULE_PARM_DESC (hs_tx_buf, "high speed tx buffer size for data endpoints in dwords"); + +MODULE_DESCRIPTION (UDC_MOD_DESCRIPTION); +MODULE_AUTHOR ("Kevin Hickey"); +MODULE_LICENSE("GPL"); + +/***************************************************************************** + * Function Definitions + *****************************************************************************/ +/* printing registers --------------------------------------------------------*/ +/** + * Prints UDC device registers and endpoint irq registers + * + * \param dev pointer to device struct + */ +static void print_regs(struct udc* dev) +{ + DBG( "------- Device registers -------\n"); + DBG( "dev config = %08lx\n", (unsigned long) dev->regs->cfg); + DBG( "dev control = %08lx\n", (unsigned long) dev->regs->ctl); + DBG( "dev status = %08lx\n", (unsigned long) dev->regs->sts); + DBG( "\n"); + DBG( "dev int's = %08lx\n", (unsigned long) dev->regs->irqsts); + DBG( "dev intmask = %08lx\n", (unsigned long) dev->regs->irqmsk); + DBG( "\n"); + DBG( "dev ep int's = %08lx\n", (unsigned long) dev->regs->ep_irqsts); + DBG( "dev ep intmask = %08lx\n", (unsigned long) dev->regs->ep_irqmsk); + DBG( "\n"); + DBG( "USE DMA = %d\n", use_dma); + if (use_dma && use_dma_ppb && !use_dma_ppb_du) { + DBG( "DMA mode = PPBNDU (packet per buffer WITHOUT desc. update)\n"); + } + else if (use_dma && use_dma_ppb_du && use_dma_ppb_du) { + DBG( "DMA mode = PPBDU (packet per buffer WITH desc. update)\n"); + } + if (use_dma && use_dma_bufferfill_mode) { + DBG( "DMA mode = BF (buffer fill mode)\n"); + } + + if (!use_dma) { + INFO( "FIFO mode\n"); + } +#ifdef UDC_USE_TIMER + INFO("RDE timer is used\n"); +#endif + DBG("-------------------------------------------------------\n"); +} + +#ifdef UDC_DEBUG +/** + * Prints misc information, to be removed + * + * \param dev pointer to device struct + */ +static void print_misc(struct udc* dev) +{ + print_regs(dev); + + if (use_dma) { + + INFO("no_req=%ld no_pref_req=%ld\n", no_req, no_pref_req); + } +} +#endif + +/** + * Masks unused interrupts + * + * \param dev pointer to device struct + * \return 0 if success + */ +static int udc_mask_unused_interrupts(struct udc* dev) +{ + u32 tmp; + + /* mask all dev interrupts */ + tmp = UDC_BIT(UDC_DEVINT_ENUM) | + UDC_BIT(UDC_DEVINT_US) | + UDC_BIT(UDC_DEVINT_UR) | + UDC_BIT(UDC_DEVINT_ES) | + UDC_BIT(UDC_DEVINT_SI) | + UDC_BIT(UDC_DEVINT_SOF)| + UDC_BIT(UDC_DEVINT_SC); + writel(tmp, &dev->regs->irqmsk); + + /* mask all ep interrupts */ + writel(UDC_EPINT_MSK_DISABLE_ALL, &dev->regs->ep_irqmsk); + + return 0; +} + +/** + * Enables endpoint 0 interrupts + * + * \param dev pointer to device struct + * \return 0 if success + */ +static int udc_enable_ep0_interrupts(struct udc* dev) +{ + u32 tmp; + + /* read irq mask */ + tmp = readl(&dev->regs->ep_irqmsk); + /* enable ep0 irq's */ + tmp &= UDC_UNMASK_BIT(UDC_EPINT_IN_EP0) + & UDC_UNMASK_BIT(UDC_EPINT_OUT_EP0); + writel(tmp, &dev->regs->ep_irqmsk); + + return 0; +} + +/** + * Enables device interrupts for SET_INTF and SET_CONFIG + * + * \param dev pointer to device struct + * \return 0 if success + */ +static int udc_enable_dev_setup_interrupts(struct udc* dev) +{ + u32 tmp; + + /* read irq mask */ + tmp = readl(&dev->regs->irqmsk); + + /* enable SET_INTERFACE, SET_CONFIG and other needed irq's */ + tmp &= UDC_UNMASK_BIT(UDC_DEVINT_SI) + & UDC_UNMASK_BIT(UDC_DEVINT_SC) + & UDC_UNMASK_BIT(UDC_DEVINT_UR) + & UDC_UNMASK_BIT(UDC_DEVINT_ENUM); + writel(tmp, &dev->regs->irqmsk); + + return 0; +} + +/** + * Calculates fifo start of endpoint based on preceeding endpoints + * + * \param ep pointer to ep struct + * \return 0 if success + */ +static int udc_set_txfifo_addr(struct udc_ep *ep) +{ + struct udc *dev; + u32 tmp; + int i; + + if (!ep || !(ep->in)) + return -EINVAL; + + dev = ep->dev; + ep->txfifo = dev->txfifo; + + /* traverse ep's */ + for (i = 0; i < ep->num; i++) { + if (dev->ep[i].regs) { + /* read fifo size */ + tmp = readl(&dev->ep[i].regs->bufin_framenum); + tmp = UDC_GETBITS(tmp, UDC_EPIN_BUFF_SIZE); + ep->txfifo+= tmp; + } + } + return 0; +} + +/** + * Enables endpoint, is called by gadget driver + * + * \param usbep pointer to ep struct + * \param desc pointer to endpoint descriptor + * \return 0 if success + */ +static int +udc_enable (struct usb_ep *usbep, const struct usb_endpoint_descriptor *desc) +{ + struct udc_ep *ep; + struct udc *dev; + u32 tmp; + unsigned long iflags; + u8 udc_csr_epix; + + VDBG("udc_enable()\n"); + + ep = container_of (usbep, struct udc_ep, ep); + if (!usbep + || usbep->name == ep0_string + || !desc + || desc->bDescriptorType != USB_DT_ENDPOINT) { + ERR("udc_enable: !usbep=%d !desc=%d ep->desc!=NULL=%d \ + usbep->name==ep0_string=%d desc->bDescriptorType!=USB_DT_ENDPOINT=%d\n", + !usbep, !desc, ep->desc != NULL, usbep->name == ep0_string, + desc->bDescriptorType != USB_DT_ENDPOINT); + return -EINVAL; + } + + dev = ep->dev; + + /* exit on suspend */ + if (dev->sys_suspended) + return -ESHUTDOWN; + + if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN) + return -ESHUTDOWN; + + spin_lock_irqsave (&dev->lock, iflags); + ep->desc = desc; + + ep->halted = 0; + + /* set traffic type */ + tmp = readl(&dev->ep[ep->num].regs->ctl); + tmp = UDC_ADDBITS(tmp, desc->bmAttributes, UDC_EPCTL_ET); + writel(tmp, &dev->ep[ep->num].regs->ctl); + + /* set max packet size */ + tmp = readl(&dev->ep[ep->num].regs->bufout_maxpkt); + tmp = UDC_ADDBITS(tmp, desc->wMaxPacketSize, UDC_EP_MAX_PKT_SIZE); + ep->ep.maxpacket = desc->wMaxPacketSize; + writel(tmp, &dev->ep[ep->num].regs->bufout_maxpkt); + + /* IN ep */ + if (ep->in) { + /* ep ix in UDC CSR register space */ + udc_csr_epix = ep->num; + + /* set buffer size (tx fifo entries) */ + tmp = readl(&dev->ep[ep->num].regs->bufin_framenum); + /* double buffering: fifo size = 2 x max packet size */ + tmp = UDC_ADDBITS( + tmp, + desc->wMaxPacketSize * UDC_EPIN_BUFF_SIZE_MULT / + UDC_DWORD_BYTES, + UDC_EPIN_BUFF_SIZE); + writel(tmp, &dev->ep[ep->num].regs->bufin_framenum); + + /* calc. tx fifo base addr */ + udc_set_txfifo_addr(ep); + + /* flush fifo */ + tmp = readl(&ep->regs->ctl); + tmp |= UDC_BIT(UDC_EPCTL_F); + writel(tmp, &ep->regs->ctl); + + } /* OUT ep */ + else { + /* ep ix in UDC CSR register space */ + udc_csr_epix = ep->num - UDC_CSR_EP_OUT_IX_OFS; + + /* set max packet size UDC CSR */ + tmp = readl(&dev->csr->ne[ep->num - UDC_CSR_EP_OUT_IX_OFS]); + tmp = UDC_ADDBITS(tmp, desc->wMaxPacketSize, UDC_CSR_NE_MAX_PKT); + writel(tmp, &dev->csr->ne[ep->num - UDC_CSR_EP_OUT_IX_OFS]); + + if (use_dma && !ep->in) { + /* alloc and init BNA dummy request */ + ep->bna_dummy_req = udc_alloc_bna_dummy(ep); + udc_init_bna_dummy(ep->bna_dummy_req); + ep->bna_occurred = 0; + } + + if (ep->num != UDC_EP0OUT_IX) + dev->data_ep_enabled = 1; + } + + /***** UDC CSR reg ****************************/ + /* set ep values */ + tmp = readl(&dev->csr->ne[udc_csr_epix]); + /* max packet */ + tmp = UDC_ADDBITS(tmp, desc->wMaxPacketSize, UDC_CSR_NE_MAX_PKT); + /* ep number */ + tmp = UDC_ADDBITS(tmp, desc->bEndpointAddress, UDC_CSR_NE_NUM); + /* ep direction */ + tmp = UDC_ADDBITS(tmp, ep->in, UDC_CSR_NE_DIR); + /* ep type */ + tmp = UDC_ADDBITS(tmp, desc->bmAttributes, UDC_CSR_NE_TYPE); + /* ep config */ + tmp = UDC_ADDBITS(tmp, ep->dev->cur_config, UDC_CSR_NE_CFG); + /* ep interface */ + tmp = UDC_ADDBITS(tmp, ep->dev->cur_intf, UDC_CSR_NE_INTF); + /* ep alt */ + tmp = UDC_ADDBITS(tmp, ep->dev->cur_alt, UDC_CSR_NE_ALT); + /* write reg */ + writel(tmp, &dev->csr->ne[udc_csr_epix]); + + /* enable ep irq */ + tmp = readl(&dev->regs->ep_irqmsk); + tmp &= UDC_UNMASK_BIT(ep->num); + writel(tmp, &dev->regs->ep_irqmsk); + + /* clear NAK by writing CNAK */ + /* avoid BNA for OUT DMA, dont clear NAK until DMA desc. written */ + if (!use_dma || ep->in) { + tmp = readl(&ep->regs->ctl); + tmp |= UDC_BIT(UDC_EPCTL_CNAK); + writel(tmp, &ep->regs->ctl); + ep->naking = 0; + UDC_QUEUE_CNAK(ep, ep->num); + } + tmp = desc->bEndpointAddress; + DBG( "%s enabled\n", usbep->name); + + spin_unlock_irqrestore (&dev->lock, iflags); + return 0; +} +/** + * Resets endpoint + * + * \param regs pointer to device register struct + * \param ep pointer to endpoint + */ +static void ep_init (struct udc_regs *regs, struct udc_ep *ep) +{ + u32 tmp; + + VDBG("ep-%d reset\n", ep->num); + ep->desc = 0; + ep->ep.ops = &udc_ep_ops; + INIT_LIST_HEAD (&ep->queue); + + ep->ep.maxpacket = (u16) ~0; + if (!(ep->dev->sys_suspended)) { + /* set NAK */ + tmp = readl(&ep->regs->ctl); + tmp |= UDC_BIT(UDC_EPCTL_SNAK); + writel(tmp, &ep->regs->ctl); + ep->naking = 1; + + /* disable interrupt */ + tmp = readl(®s->ep_irqmsk); + tmp |= UDC_BIT(ep->num); + writel(tmp, ®s->ep_irqmsk); + + if (ep->in) { + /* unset P and IN bit of potential former DMA */ + tmp = readl(&ep->regs->ctl); + tmp &= UDC_UNMASK_BIT(UDC_EPCTL_P); + writel(tmp, &ep->regs->ctl); + + tmp = readl(&ep->regs->sts); + tmp |= UDC_BIT(UDC_EPSTS_IN); + writel(tmp, &ep->regs->sts); + + /* flush the fifo */ + tmp = readl(&ep->regs->ctl); + tmp |= UDC_BIT(UDC_EPCTL_F); + writel(tmp, &ep->regs->ctl); + + } + /* reset desc pointer */ + writel(0, &ep->regs->desptr); + } + + +} + +/** + * Disables endpoint, is called by gadget driver + * + * \param usbep pointer to ep struct + * \return 0 if success + */ +static int udc_disable (struct usb_ep *usbep) +{ + struct udc_ep *ep = NULL; + unsigned long iflags; + + if (!usbep) + return -EINVAL; + + ep = container_of (usbep, struct udc_ep, ep); + if (usbep->name == ep0_string + || !ep->desc) + return -EINVAL; + + DBG("Disable ep-%d\n", ep->num); + + spin_lock_irqsave(&ep->dev->lock, iflags); + udc_free_request(&ep->ep, &ep->bna_dummy_req->req); + empty_req_queue(ep); + ep_init(ep->dev->regs, ep); + spin_unlock_irqrestore(&ep->dev->lock, iflags); + + return 0; +} + +/** + * Allocates request packet, called by gadget driver + * + * \param _ep pointer to usb ep struct + * \param gfp_flags flags for kmalloc + * \return allocated request packet, 0 if error + */ +static struct usb_request * +udc_alloc_request (struct usb_ep *usbep, gfp_t gfp) +{ + struct udc_request *req; + struct udc_data_dma *dma_desc; + struct udc_ep *ep; + + VDBG("udc_alloc_req()\n"); + if (!usbep) + return 0; + + ep = container_of (usbep, struct udc_ep, ep); + udc_gfp_flags = gfp; + + VDBG("udc_alloc_req(): ep%d\n", ep->num); + req = kmalloc (sizeof (struct udc_request), gfp); + if (!req) + return 0; + + memset (req, 0, sizeof *req); + req->req.dma = DMA_DONT_USE; + INIT_LIST_HEAD (&req->queue); + + if (ep->dma) { + gfp = GFP_ATOMIC | GFP_DMA; + /* ep0 in requests are allocated from data pool here */ + dma_desc = dma_pool_alloc(ep->dev->data_requests, gfp, + &req->td_phys); + if (!dma_desc) { + kfree (req); + return 0; + } + + VDBG("udc_alloc_req: req = %lx dma_desc = %lx, req->td_phys = %lx\n", + (unsigned long) req, (unsigned long) dma_desc, (unsigned long)req->td_phys); + /* prevent from using desc. - set HOST BUSY */ + dma_desc->status = UDC_ADDBITS(dma_desc->status, + UDC_DMA_STP_STS_BS_HOST_BUSY, + UDC_DMA_STP_STS_BS); + dma_desc->bufptr = __constant_cpu_to_le32 (DMA_DONT_USE); + req->td_data = dma_desc; + req->td_data_last = NULL; + req->chain_len = 1; + } + + return &req->req; +} + +/** + * Frees request packet, called by gadget driver + * + * \param usbep pointer to usb ep struct + * \param usbreq pointer to request packet to be freed + */ +static void +udc_free_request (struct usb_ep *usbep, struct usb_request *usbreq) +{ + struct udc_ep *ep; + struct udc_request *req; + + if (!usbep || !usbreq) + return; + + ep = container_of (usbep, struct udc_ep, ep); + req = container_of (usbreq, struct udc_request, req); + VDBG("free_req req=%lx\n", (unsigned long) req); + WARN_ON(!list_empty (&req->queue)); + if (req->td_data) { + VDBG("req->td_data=%lx\n", (unsigned long) req->td_data); + + /* re-link broken chain */ + if (req->td_data_last) { + req->td_data_last->next = req->td_data_last_next; + } + /* free dma chain if created */ + if (req->chain_len > 1) { + udc_free_dma_chain(ep->dev, req); + } + + dma_pool_free (ep->dev->data_requests, req->td_data, req->td_phys); + } + kfree (req); +} + +/* choose dma buffer allocation method */ +#undef USE_KMALLOC +#ifdef CONFIG_DMA_COHERENT +#define USE_KMALLOC +#endif /* CONFIG_DMA_COHERENT */ + +/** + * Init BNA dummy descriptor for HOST BUSY and pointing to itself + * + * \param req pointer to request struct + */ +static inline void udc_init_bna_dummy(struct udc_request *req) +{ + if (req) { + /* set last bit */ + req->td_data->status |= UDC_BIT(UDC_DMA_IN_STS_L); + /* set next pointer to itself */ + req->td_data->next = req->td_phys; + /* set HOST BUSY */ + req->td_data->status + = UDC_ADDBITS(req->td_data->status, + UDC_DMA_STP_STS_BS_DMA_DONE, + UDC_DMA_STP_STS_BS); + } + VDBG("bna desc = %08lx, sts = %08lx\n", + (unsigned long) req->td_data, req->td_data->status); +} + +/** + * Allocate BNA dummy descriptor + * + * \param req pointer to ep struct + * \return pointer to allocated request, NULL if error + */ +static struct udc_request* udc_alloc_bna_dummy(struct udc_ep* ep) +{ + struct udc_request *req = NULL; + struct usb_request *_req = NULL; + + VDBG("ep%d: alloc BNA dummy descriptor\n", ep->num); + /* alloc the dummy request */ + _req = udc_alloc_request(&ep->ep, GFP_ATOMIC); + if (_req) { + req = container_of(_req, struct udc_request, req); + ep->bna_dummy_req = req; + } + return req; +} + + +/** + * Write data to TX fifo for IN packets + * + * \param ep pointer to ep struct + * \param req pointer to request packet + * \return allocated request packet, 0 if error + */ +static void +udc_txfifo_write (struct udc_ep *ep, struct usb_request *req) +{ + u8 *req_buf; + u32 *buf; + int i,j; + unsigned bytes = 0; + unsigned remaining = 0; + + VDBG("udc_txfifo_write()\n"); + + if (!req || !ep) + return; + + req_buf = req->buf + req->actual; + prefetch (req_buf); + remaining = req->length - req->actual; + + buf = (u32*) req_buf; + + bytes = ep->ep.maxpacket; + if (bytes > remaining) + bytes = remaining; + + DBG( "Writing %d bytes to the txfifo\n", bytes ); + + /* dwords first */ + for (i = 0; i < bytes / UDC_DWORD_BYTES; i++) { + writel(*(buf + i), ep->txfifo); + } + + /* remaining bytes must be written by byte access */ + for (j = 0; j < bytes % UDC_DWORD_BYTES; j++) { + writeb((u8) (*(buf + i) >> (j << UDC_BITS_PER_BYTE_SHIFT)), + ep->txfifo); + } + + { + u32 tmp; + + /* NAK if small packet until write confirm completed */ + if (bytes < UDC_SMALL_PACKET) { + /* set NAK */ + tmp = readl(&ep->regs->ctl); + tmp |= UDC_BIT(UDC_EPCTL_SNAK); + writel(tmp, &ep->regs->ctl); + ep->naking = 1; + au_sync(); + } + + /* dummy write confirm */ + writel(0, &ep->regs->confirm); + + /* stop NAKing after small packet DMA */ + if (ep->naking) { + /* clear NAK by writing CNAK */ + tmp = readl(&ep->regs->ctl); + tmp |= UDC_BIT(UDC_EPCTL_CNAK); + writel(tmp, &ep->regs->ctl); + ep->naking = 0; + UDC_QUEUE_CNAK(ep, ep->num); + } + } +} + +/** + * Read dwords from RX fifo for OUT transfers + * + * \param dev pointer to device struct + * \param buf pointer to buffer to be filled + * \param dwords number of dwords to be read + * \return allocated request packet, 0 if error + */ +static int udc_rxfifo_read_dwords(struct udc* dev, u32* buf, int dwords) +{ + int i; + + VDBG("udc_read_dwords(): %d dwords\n", dwords); + + for (i = 0; i < dwords; i++) + { + *(buf + i) = readl(dev->rxfifo); + } + return 0; +} + +/** + * Read bytes from RX fifo for OUT transfers + * + * \param dev pointer to device struct + * \param buf pointer to buffer to be filled + * \param bytes number of bytes to be read + * \return allocated request packet, 0 if error + */ +static int udc_rxfifo_read_bytes(struct udc* dev, u8* buf, int bytes) +{ + int i,j; + u32 tmp; + + VDBG("udc_read_bytes(): %d bytes\n", bytes); + + /* dwords first */ + for (i = 0; i < bytes / UDC_DWORD_BYTES; i++) { + *((u32*) (buf + (i<<2))) = readl(dev->rxfifo); + } + + /* remaining bytes must be read by byte access */ + if (bytes % UDC_DWORD_BYTES) { + tmp = readl(dev->rxfifo); + for (j = 0; j < bytes % UDC_DWORD_BYTES; j++) { + *(buf + (i<<2) + j) = (u8) (tmp & UDC_BYTE_MASK); + tmp = tmp >> UDC_BITS_PER_BYTE; + } + } + + return 0; +} + +/** + * Read data from RX fifo for OUT transfers + * + * \param ep pointer to ep struct + * \param req pointer to request packet + * \return true if request completes for short or max packet, false otherwise + */ +static int +udc_rxfifo_read(struct udc_ep *ep, struct udc_request *req) +{ + u8 *buf; + unsigned buf_space; + unsigned bytes = 0; + unsigned finished = 0; + + /* received number bytes */ + bytes = readl(&ep->regs->sts); + bytes = UDC_GETBITS(bytes, UDC_EPSTS_RX_PKT_SIZE); + + buf_space = req->req.length - req->req.actual; + buf = req->req.buf + req->req.actual; + if (bytes > buf_space) { + if ((buf_space % ep->ep.maxpacket) != 0) { + ERR( "%s: received %d bytes, rx-buffer space = %d bytes => buffer overrun\n", + ep->ep.name, bytes, buf_space); + req->req.status = -EOVERFLOW; + } + bytes = buf_space; + } + req->req.actual += bytes; + + /* last packet ? */ + if (((bytes % ep->ep.maxpacket) != 0) + || (!bytes) + || ((req->req.actual == req->req.length) && !req->req.zero)) + finished = 1; + + /* read rx fifo bytes */ + VDBG("ep %s: rxfifo read %d bytes\n", ep->ep.name, bytes); + udc_rxfifo_read_bytes(ep->dev, buf, bytes); + + return finished; +} + +/** + * create/re-init a DMA descriptor or a DMA descriptor chain + * + * \param ep pointer to endpoint struct + * \param req pointer to request packet + */ +static int prep_dma (struct udc_ep *ep, struct udc_request *req) +{ + int retval = 0; + u32 tmp; + VDBG("prep_dma\n"); + VDBG("prep_dma ep%d req->td_data=%lx\n", + ep->num, (unsigned long) req->td_data); + + /* set buffer pointer */ + req->td_data->bufptr = req->req.dma; + + /* set last bit */ + req->td_data->status |= UDC_BIT(UDC_DMA_IN_STS_L); + + /* build/re-init dma chain if maxpkt scatter mode, not for EP0 */ + if (use_dma_ppb) { + + retval = udc_create_dma_chain(ep, req, ep->ep.maxpacket, udc_gfp_flags); + if (retval != 0) + { + if (retval == -ENOMEM) + INFO("Out of DMA memory (allocation failed)\n"); + return retval; + } + if (ep->in) { + if (req->req.length == ep->ep.maxpacket) { + /* write tx bytes */ + req->td_data->status = UDC_ADDBITS(req->td_data->status, + ep->ep.maxpacket, + UDC_DMA_IN_STS_TXBYTES); + + } + } + + } + + if (ep->in) { + VDBG("IN: use_dma_ppb=%d req->req.length=%d ep->ep.maxpacket=%d ep%d\n", + use_dma_ppb, req->req.length, ep->ep.maxpacket, ep->num); + /* if bytes < max packet then tx bytes must */ + /* be written in packet per buffer mode */ + if (!use_dma_ppb || req->req.length < ep->ep.maxpacket + || ep->num == UDC_EP0OUT_IX || ep->num == UDC_EP0IN_IX) { + /* write tx bytes */ + req->td_data->status = UDC_ADDBITS(req->td_data->status, + req->req.length, + UDC_DMA_IN_STS_TXBYTES); + /* reset frame num */ + req->td_data->status = UDC_ADDBITS(req->td_data->status, + 0, + UDC_DMA_IN_STS_FRAMENUM); + } + /* set HOST BUSY */ + req->td_data->status + = UDC_ADDBITS(req->td_data->status, + UDC_DMA_STP_STS_BS_HOST_BUSY, + UDC_DMA_STP_STS_BS); + } + else { + VDBG("OUT set host ready\n"); + /* set HOST READY */ + req->td_data->status + = UDC_ADDBITS(req->td_data->status, + UDC_DMA_STP_STS_BS_HOST_READY, + UDC_DMA_STP_STS_BS); + + + /* clear NAK by writing CNAK */ + if (ep->naking) { + tmp = readl(&ep->regs->ctl); + tmp |= UDC_BIT(UDC_EPCTL_CNAK); + writel(tmp, &ep->regs->ctl); + ep->naking = 0; + UDC_QUEUE_CNAK(ep, ep->num); + } + + } + + return retval; +} + +/** + * Completes request packet + * + * \param ep pointer to ep struct + * \param req pointer to request packet + * \param sts status of request + */ +static void +complete_req(struct udc_ep *ep, struct udc_request *req, int sts) +{ + struct udc *dev; + unsigned halted; + + VDBG("complete_req(): ep%d\n", ep->num); + + dev = ep->dev; + /* unmap DMA */ + if (req->dma_mapping) { + if (ep->in) + dma_unmap_single(0, + req->req.dma, + req->req.length, + PCI_DMA_TODEVICE); + else + dma_unmap_single(0, + req->req.dma, + req->req.length, + PCI_DMA_FROMDEVICE); + req->dma_mapping = 0; + req->req.dma = DMA_DONT_USE; + } + + halted = ep->halted; + ep->halted = 1; + + /* set new status if pending */ + if (req->req.status == -EINPROGRESS) + req->req.status = sts; + + /* remove from ep queue */ + list_del_init (&req->queue); + + VDBG( "req %p => complete %d bytes at %s with sts %d\n", + &req->req, req->req.length, ep->ep.name, sts); + if (spin_is_locked(&dev->lock)) { + spin_unlock (&dev->lock); + req->req.complete (&ep->ep, &req->req); + spin_lock (&dev->lock); + } + else { + req->req.complete (&ep->ep, &req->req); + } + ep->halted = halted; +} + +/** + * frees pci pool descriptors of a DMA chain + * + * \param dev pointer to device struct + * \param req pointer to request packet + * \return 0 if success + */ +static int udc_free_dma_chain(struct udc* dev, struct udc_request* req) +{ + + int ret_val = 0; + struct udc_data_dma *td; + struct udc_data_dma *td_last = NULL; + unsigned int i; + + DBG("free chain req = %lx\n", (unsigned long) req); + + /* re-link broken chain */ + if (req->td_data_last) { + req->td_data_last->next = req->td_data_last_next; + } + /* do not free first desc., will be done by free for request */ + td_last = req->td_data; +#if defined (CONFIG_SOC_AU1200) && !defined(CONFIG_DMA_COHERENT) + td = UNCAC_ADDR(phys_to_virt(td_last->next)); +#else + td = phys_to_virt(td_last->next); +#endif + + for (i = 1; i < req->chain_len; i++) { + + dma_pool_free (dev->data_requests, td, + (dma_addr_t) td_last->next); + td_last = td; +#if defined (CONFIG_SOC_AU1200) && !defined(CONFIG_DMA_COHERENT) + td = UNCAC_ADDR(phys_to_virt(td_last->next)); +#else + td = phys_to_virt(td_last->next); +#endif + } + + req->td_data_last = NULL; + return ret_val; +} + +/** + * Iterates to the end of a DMA chain and returns last descriptor + * + * \param req pointer to request packet + * \return pointer to last descriptori of chain + */ +static struct udc_data_dma* udc_get_last_dma_desc(struct udc_request* req) +{ + struct udc_data_dma *td; + + td = req->td_data; + while (td && !(td->status & UDC_BIT(UDC_DMA_IN_STS_L))) { +#if defined (CONFIG_SOC_AU1200) && !defined(CONFIG_DMA_COHERENT) + td = UNCAC_ADDR(phys_to_virt(td->next)); +#else + td = phys_to_virt(td->next); +#endif + } + + return td; + +} + +/** + * Iterates to the end of a DMA chain and counts bytes received + * + * \param req pointer to request packet + * \return number of received bytes + */ +static u32 udc_get_ppbdu_rxbytes(struct udc_request* req) +{ + struct udc_data_dma *td; + u32 count; + + td = req->td_data; + /* received number bytes */ + count = UDC_GETBITS(td->status, UDC_DMA_OUT_STS_RXBYTES); + + while (td && !(td->status & UDC_BIT(UDC_DMA_IN_STS_L))) { +#if defined (CONFIG_SOC_AU1200) && !defined(CONFIG_DMA_COHERENT) + td = UNCAC_ADDR(phys_to_virt(td->next)); +#else + td = phys_to_virt(td->next); +#endif + /* received number bytes */ + if (td) { + count += UDC_GETBITS(td->status, UDC_DMA_OUT_STS_RXBYTES); + } + } + + return count; + +} + +/** + * Creates or re-inits a DMA chain + * + * \param ep pointer to endpoint struct + * \param req pointer to request packet + * \param buf_len number of buffer bytes per descriptor (except last short) + */ +static int udc_create_dma_chain(struct udc_ep* ep, struct udc_request* req, unsigned long buf_len, int gfp_flags) +{ + unsigned long bytes = req->req.length; + unsigned int i; + dma_addr_t dma_addr; + struct udc_data_dma *td = NULL; + struct udc_data_dma *last = NULL; + unsigned long txbytes; + unsigned create_new_chain = 0; + unsigned len; + dma_addr_t last_next = DMA_DONT_USE; + + VDBG("udc_create_dma_chain: bytes=%ld buf_len=%ld\n", bytes, buf_len); + dma_addr = DMA_DONT_USE; + + /* unset L bit in first desc for OUT */ + if (!ep->in) { + req->td_data->status &= UDC_CLEAR_BIT(UDC_DMA_IN_STS_L); + } + + /* alloc only new desc's if not already available */ + len = req->req.length / ep->ep.maxpacket; + if (req->req.length % ep->ep.maxpacket) { + len++; + } + + if (len > req->chain_len) { + /* shorter chain already allocated before */ + if (req->chain_len > 1) { + udc_free_dma_chain(ep->dev, req); + } + req->chain_len = len; + create_new_chain = 1; + } + + /* re-link broken chain */ + if (req->td_data_last) { + req->td_data_last->next = req->td_data_last_next; + } + /* if only one td then last_next is root td */ + last_next = req->td_phys; + + td = req->td_data; + /* gen. required number of descriptors and buffers */ + for (i = buf_len; i < bytes; i += buf_len) + { + /* create or determine next desc. */ + if (create_new_chain) { + +#if defined(CONFIG_SOC_AU1200) + gfp_flags = GFP_ATOMIC | GFP_DMA; +#endif + td = dma_pool_alloc (ep->dev->data_requests, gfp_flags, + &dma_addr); + if (!td) + return -ENOMEM; + + td->status = 0; + } + else if (i == buf_len) + { + /* first td */ +#if defined (CONFIG_SOC_AU1200) && !defined(CONFIG_DMA_COHERENT) + td = (struct udc_data_dma*) UNCAC_ADDR(phys_to_virt(req->td_data->next)); +#else + td = (struct udc_data_dma*) phys_to_virt(req->td_data->next); +#endif + td->status = 0; + } + else { +#if defined (CONFIG_SOC_AU1200) && !defined(CONFIG_DMA_COHERENT) + td = (struct udc_data_dma*) UNCAC_ADDR(phys_to_virt(last->next)); +#else + td = (struct udc_data_dma*) phys_to_virt(last->next); +#endif + td->status = 0; + } + + + if (td) { + /* assign buffer */ + td->bufptr = req->req.dma + i; + } + else { + break; + } + + /* short packet ? */ + if ((bytes - i) >= buf_len) { + txbytes = buf_len; + } + else { + /* short packet */ + txbytes = bytes - i; + } + + /* link td and assign tx bytes */ + if (i == buf_len) { + if (create_new_chain) { + req->td_data->next = dma_addr; + } + else { + /* req->td_data->next = virt_to_phys(td); */ + } + /* write tx bytes */ + if (ep->in) { + /* first desc */ + req->td_data->status = UDC_ADDBITS(req->td_data->status, + ep->ep.maxpacket, + UDC_DMA_IN_STS_TXBYTES); + /* second desc */ + td->status = UDC_ADDBITS(td->status, + txbytes, + UDC_DMA_IN_STS_TXBYTES); + } + + last_next = req->td_data->next; + } + else { + if (create_new_chain) { + last->next = dma_addr; + } + if (ep->in) { + /* write tx bytes */ + td->status = UDC_ADDBITS(td->status, + txbytes, + UDC_DMA_IN_STS_TXBYTES); + } + last_next = last->next; + } + last = td; + } + /* set last bit */ + if (td) { + td->status |= UDC_BIT(UDC_DMA_IN_STS_L); + /* last desc. points to itself */ + /* remember broken chain next pointer */ + req->td_data_last_next = td->next; + /* point to itself */ + td->next = last_next; + req->td_data_last = td; + } + + return 0; +} + +/** + * Enabling RX DMA + * + * \param dev pointer to UDC device object + */ +static inline void udc_set_rde(struct udc* dev) +{ + u32 tmp; + + VDBG("udc_set_rde()\n"); +#ifdef UDC_USE_TIMER + /* stop RDE timer */ + if (timer_pending(&udc_timer)) { + set_rde = 0; + mod_timer(&udc_timer, jiffies - 1); + } +#endif + /* set RDE */ + tmp = readl(&dev->regs->ctl); + tmp |= UDC_BIT(UDC_DEVCTL_RDE); + writel(tmp, &dev->regs->ctl); +} + +/** + * Queues a request packet, called by gadget driver + * + * \param usbep pointer to usb ep struct + * \param usbreq pointer to request packet to be freed + * \param gfp flags for alloc + * \return 0 if success + */ +static int +udc_queue (struct usb_ep *usbep, struct usb_request *usbreq, gfp_t gfp) +{ + int retval = 0; + u8 open_rxfifo = 0; + unsigned long iflags; + struct udc_ep *ep; + struct udc_request *req; + struct udc *dev; + u32 tmp; + + VDBG ("udc_queue()\n"); + + /* check the inputs */ + req = container_of (usbreq, struct udc_request, req); + VDBG("!usbep=%d !req=%d !buf=%d !compl=%d !empty_list=%d \n", + !usbep, !usbreq, !usbreq->buf, !usbreq->complete, + !list_empty(&req->queue)); + + if (!usbep || !usbreq || !usbreq->complete || !usbreq->buf + || !list_empty (&req->queue)) + return -EINVAL; + + ep = container_of (usbep, struct udc_ep, ep); + if (!ep->desc && (ep->num != 0 && ep->num != UDC_EP0OUT_IX)) + return -EINVAL; + + VDBG("udc_queue(): ep%d-in=%d\n", ep->num, ep->in); + dev = ep->dev; + + /* exit on suspend */ + if (dev->sys_suspended) + return -ESHUTDOWN; + + if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN) + return -ESHUTDOWN; + + /* map dma (usally done before) */ + if (ep->dma && usbreq->length != 0 && usbreq->dma == DMA_DONT_USE) { + VDBG("DMA map req %lx\n", (unsigned long) req); + if (ep->in) + usbreq->dma = dma_map_single(dev->pdev, + usbreq->buf, + usbreq->length, + PCI_DMA_TODEVICE); + else + usbreq->dma = dma_map_single(dev->pdev, + usbreq->buf, + usbreq->length, + PCI_DMA_FROMDEVICE); + req->dma_mapping = 1; + } + + VDBG( "%s queue req %p, len %d req->td_data=%lx buf %p\n", + usbep->name, usbreq, usbreq->length, (unsigned long) req->td_data, usbreq->buf); + + spin_lock_irqsave (&dev->lock, iflags); + usbreq->actual = 0; + usbreq->status = -EINPROGRESS; + req->dma_done = 0; + + /* on empty queue just do first transfer */ + if (list_empty (&ep->queue)) { + /* zlp */ + if (usbreq->length == 0) { + /* IN zlp's are handled by hardware */ + complete_req(ep, req, 0); + VDBG( "%s: zlp\n", ep->ep.name); + /* if set_config or set_intf is waiting for ack by zlp + then set CSR_DONE */ + if (dev->set_cfg_not_acked) { + tmp = readl(&dev->regs->ctl); + tmp |= UDC_BIT(UDC_DEVCTL_CSR_DONE); + writel(tmp, &dev->regs->ctl); + dev->set_cfg_not_acked = 0; + } + /* setup command is ACK'ed now by zlp */ + if (dev->waiting_zlp_ack_ep0in) { + /* clear NAK by writing CNAK in EP0_IN */ + tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->ctl); + tmp |= UDC_BIT(UDC_EPCTL_CNAK); + writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl); + dev->ep[UDC_EP0IN_IX].naking = 0; + UDC_QUEUE_CNAK(&dev->ep[UDC_EP0IN_IX], UDC_EP0IN_IX); + dev->waiting_zlp_ack_ep0in = 0; + } + goto finished; + } + if (ep->dma) { + retval = prep_dma(ep, req); + if (retval != 0) + goto finished; + /* write desc pointer to enable DMA */ + if (ep->in) { + /* set HOST READY */ + req->td_data->status + = UDC_ADDBITS(req->td_data->status, + UDC_DMA_IN_STS_BS_HOST_READY, + UDC_DMA_IN_STS_BS); + } + + /* disabled rx dma while descriptor update */ + if (!ep->in) { +#ifdef UDC_USE_TIMER + /* stop RDE timer */ + if (timer_pending(&udc_timer)) { + set_rde = 0; + mod_timer(&udc_timer, jiffies - 1); + } +#endif + /* clear RDE */ + tmp = readl(&dev->regs->ctl); + tmp &= UDC_UNMASK_BIT(UDC_DEVCTL_RDE); + writel(tmp, &dev->regs->ctl); + open_rxfifo = 1; + + /* if BNA occurred then let BNA dummy desc. point + to current desc. */ + if (ep->bna_occurred) { + VDBG("copy desc. to BNA dummy desc.\n"); + memcpy(ep->bna_dummy_req->td_data, req->td_data, + sizeof(struct udc_data_dma)); + } + } + /* write desc pointer */ + writel(req->td_phys, &ep->regs->desptr); + + /* clear NAK by writing CNAK */ + if (ep->naking) { + tmp = readl(&ep->regs->ctl); + tmp |= UDC_BIT(UDC_EPCTL_CNAK); + writel(tmp, &ep->regs->ctl); + ep->naking = 0; + UDC_QUEUE_CNAK(ep, ep->num); + } + + if (ep->in) { + /* enable ep irq */ + tmp = readl(&dev->regs->ep_irqmsk); + tmp &= UDC_UNMASK_BIT(ep->num); + writel(tmp, &dev->regs->ep_irqmsk); + } + } + + } else if (ep->dma) { + + /* prep_dma not used for OUT ep's, this is not possible + for PPB modes, because of chain creation reasons */ + if (ep->in) { + retval = prep_dma(ep, req); + if (retval != 0) + goto finished; + } + + } + VDBG("list_add\n"); + /* add request to ep queue */ + if (req) { + + list_add_tail (&req->queue, &ep->queue); + + /* open rxfifo if out data queued */ + if (open_rxfifo) { + /* enable DMA */ + udc_set_rde(dev); + if (ep->num != UDC_EP0OUT_IX) + dev->data_ep_queued = 1; + } + /* stop OUT naking */ + if (!ep->in) { + if (!use_dma && udc_rxfifo_pending) { + DBG("udc_queue(): pending bytes in rxfifo after nyet\n"); + /* read pending bytes afer nyet: referring to isr */ + if (udc_rxfifo_read(ep, req)) { + /* finish */ + complete_req(ep, req, 0); + } + udc_rxfifo_pending = 0; + + } + } + + } + +finished: + spin_unlock_irqrestore (&dev->lock, iflags); + return retval; +} + +/** + * Empty request queue of an endpoint + * + * \param ep pointer to ep struct + */ +static void empty_req_queue(struct udc_ep *ep) +{ + struct udc_request *req; + + ep->halted = 1; + while (!list_empty (&ep->queue)) { + req = list_entry(ep->queue.next, + struct udc_request, + queue); + complete_req(ep, req, -ESHUTDOWN); + } +} + +/** + * Dequeues a request packet, called by gadget driver + * + * \param usbep pointer to usb ep struct + * \param usbreq pointer to request packet to be freed + * \return 0 if success + */ +static int udc_dequeue (struct usb_ep *usbep, struct usb_request *usbreq) +{ + struct udc_ep *ep; + struct udc_request *req; + unsigned req_may_used = 0; + unsigned halted; + unsigned long iflags; + + ep = container_of (usbep, struct udc_ep, ep); + if (!usbep + || !usbreq + || (!ep->desc && (ep->num != 0 && ep->num != UDC_EP0OUT_IX))) + return -EINVAL; + + req = container_of (usbreq, struct udc_request, req); + + spin_lock_irqsave (&ep->dev->lock, iflags); + halted = ep->halted; + ep->halted = 1; + /* request in processing or next one */ + if (ep->queue.next == &req->queue) { + req_may_used = 1; + } + complete_req(ep, req, -ECONNRESET); + ep->halted = halted; + + spin_unlock_irqrestore (&ep->dev->lock, iflags); + if (req_may_used) + return -EOPNOTSUPP; + else + return 0; +} + +/** + * Halt or clear halt of endpoint + * + * \param usbe pointer to ep struct + * \param halt 1 - halt, 0 - clear halt + * \return 0 if success + */ +static int +udc_set_halt (struct usb_ep *usbep, int halt) +{ + struct udc_ep *ep; + u32 tmp; + unsigned long iflags; + int retval = 0; + + if (!usbep) + return -EINVAL; + + DBG("set_halt %s: halt=%d\n", usbep->name, halt); + + ep = container_of (usbep, struct udc_ep, ep); + if (!ep->desc && (ep->num != 0 && ep->num != UDC_EP0OUT_IX)) + return -EINVAL; + if (!ep->dev->driver + || ep->dev->gadget.speed == USB_SPEED_UNKNOWN) + return -ESHUTDOWN; + + /* exit on suspend */ + if (ep->dev->sys_suspended) + return -ESHUTDOWN; + + spin_lock_irqsave (&udc_stall_spinlock, iflags); + /* halt or clear halt */ + if (halt) { + if (ep->num == 0) + ep->dev->stall_ep0in = 1; + else { + /* set STALL */ + /* rxfifo empty not taken into acount */ + tmp = readl(&ep->regs->ctl); + tmp |= UDC_BIT(UDC_EPCTL_S); + writel(tmp, &ep->regs->ctl); + ep->halted = 1; + +#ifdef UDC_USE_TIMER + /* setup poll timer */ + if (!timer_pending(&udc_pollstall_timer)) { + udc_pollstall_timer.expires = jiffies + HZ + * UDC_POLLSTALL_TIMER_USECONDS + / (1000 * 1000); + if (!stop_pollstall_timer) { + DBG("start polltimer\n"); + add_timer(&udc_pollstall_timer); + } + } +#endif + } + } else { + /* ep is halted by set_halt() before */ + if (ep->halted) { + tmp = readl(&ep->regs->ctl); + /* clear stall bit */ + tmp = tmp & UDC_CLEAR_BIT(UDC_EPCTL_S); + /* clear NAK by writing CNAK */ + tmp |= UDC_BIT(UDC_EPCTL_CNAK); + writel(tmp, &ep->regs->ctl); + ep->halted = 0; + UDC_QUEUE_CNAK(ep, ep->num); + } + } + spin_unlock_irqrestore (&udc_stall_spinlock, iflags); + return retval; +} + +/** + * Return fifo fill state (not used, not implemented) + * + * \param usbep pointer to usb ep struct + * \return available bytes in fifo + */ +static int +udc_fifo_status (struct usb_ep *usbep) +{ + return 0; +} + +/** + * Flush the endpoint fifo (not implemented) + * + * \param usbep pointer to usb ep struct + */ +static void +udc_fifo_flush (struct usb_ep *usbep) +{ + return; +} + +/* gadget interface */ +static struct usb_ep_ops udc_ep_ops = { + .enable = udc_enable, + .disable = udc_disable, + + .queue = udc_queue, + .dequeue = udc_dequeue, + + .alloc_request = udc_alloc_request, + .free_request = udc_free_request, + + .set_halt = udc_set_halt, + .fifo_status = udc_fifo_status, + .fifo_flush = udc_fifo_flush, +}; + +/*-------------------------------------------------------------------------*/ + +/** + * Get frame count fifo (not implemented) + * + * \param gadget pointer to gadget struct + * \return frame count + */ +static int udc_get_frame (struct usb_gadget *gadget) +{ + return 0; +} + +/** + * Remote wakeup gadget interface + * + * \param gadget pointer to gadget struct + * \return 0 if success + */ +static int udc_wakeup (struct usb_gadget *gadget) +{ + struct udc *dev; + + if (!gadget) + return -EINVAL; + dev = container_of (gadget, struct udc, gadget); + udc_remote_wakeup(dev); + + return 0; +} + +/** + * gadget ioctl, used for OTG support notification + * + * \param gadget pointer to gadget struct + * \param cmd command + * \param par parmater + * \return 1 if OTG supported, else 0 + */ +static int udc_gadget_ioctl (struct usb_gadget *gadget, unsigned cmd, unsigned long par) +{ + struct udc *dev; + int retval = 0; + unsigned long iflags; + u32 tmp; + + if (!gadget) + return -ENODEV; + dev = container_of (gadget, struct udc, gadget); + spin_lock_irqsave (&dev->lock, iflags); + tmp = readl(&dev->regs->cfg); + + if (tmp & UDC_BIT(UDC_DEVCFG_HNPSFEN)) + retval = 1; + else + retval = 0; + spin_unlock_irqrestore (&dev->lock, iflags); + return retval; +} + +/* gadget operations */ +static const struct usb_gadget_ops udc_ops = { + .wakeup = udc_wakeup, + .get_frame = udc_get_frame, + .ioctl = udc_gadget_ioctl, +}; + +/** + * Setups endpoint parameters, adds endpoints to linked list + * + * \param dev pointer to dev struct + */ +static void make_ep_lists(struct udc *dev) +{ + /* make gadget ep lists */ + INIT_LIST_HEAD (&dev->gadget.ep_list); + list_add_tail (&dev->ep [UDC_EPIN_STATUS_IX].ep.ep_list, &dev->gadget.ep_list); + list_add_tail (&dev->ep [UDC_EPIN_IX].ep.ep_list, &dev->gadget.ep_list); + list_add_tail (&dev->ep [UDC_EPOUT_IX].ep.ep_list, &dev->gadget.ep_list); + + /* fifo config */ + dev->ep [UDC_EPIN_STATUS_IX].fifo_depth = UDC_EPIN_SMALLINT_BUFF_SIZE; + if (dev->gadget.speed == USB_SPEED_FULL) + dev->ep [UDC_EPIN_IX].fifo_depth = UDC_FS_EPIN_BUFF_SIZE; + else if (dev->gadget.speed == USB_SPEED_HIGH) + dev->ep [UDC_EPIN_IX].fifo_depth = hs_tx_buf; + dev->ep [UDC_EPOUT_IX].fifo_depth = UDC_RXFIFO_SIZE; +} + +/** + * \brief + * init registers at driver load time + * + * \param dev pointer to device struc + * \return 0 if success + */ +static int startup_registers(struct udc* dev) +{ + u32 tmp; + DBG( "In startup_registers()\n" ); + + /* init controller by soft reset */ + udc_soft_reset(dev); + + /* mask not needed interrupts */ + udc_mask_unused_interrupts(dev); + + /* put into initial config */ + udc_basic_init (dev); + /* link up all endpoints */ + udc_setup_endpoints (dev); + + /* program speed */ + tmp = readl(&dev->regs->cfg); + if (use_fullspeed) { + tmp = UDC_ADDBITS(tmp, UDC_DEVCFG_SPD_FS, UDC_DEVCFG_SPD); + } + else { + tmp = UDC_ADDBITS(tmp, UDC_DEVCFG_SPD_HS, UDC_DEVCFG_SPD); + } + writel(tmp, &dev->regs->cfg); + + DBG( "After speed program\n" ); + + return 0; +} + +/** + * Inits UDC context + * + * \param dev pointer to device struct + */ +static void udc_basic_init (struct udc *dev) +{ + u32 tmp; + + DBG("udc_basic_init()\n"); + + dev->gadget.speed = USB_SPEED_UNKNOWN; + +#ifdef UDC_USE_TIMER + /* stop RDE timer */ + if (timer_pending(&udc_timer)) { + set_rde = 0; + mod_timer(&udc_timer, jiffies - 1); + } + /* stop poll stall timer */ + if (timer_pending(&udc_pollstall_timer)) { + mod_timer(&udc_pollstall_timer, jiffies - 1); + } +#endif + /* disable DMA */ + tmp = readl(&dev->regs->ctl); + tmp &= UDC_UNMASK_BIT(UDC_DEVCTL_RDE); + tmp &= UDC_UNMASK_BIT(UDC_DEVCTL_TDE); + writel(tmp, &dev->regs->ctl); + + /* enable dynamic CSR programming */ + tmp = readl(&dev->regs->cfg); + tmp |= UDC_BIT(UDC_DEVCFG_CSR_PRG); + /* set self powered */ + tmp |= UDC_BIT(UDC_DEVCFG_SP); + /* set remote wakeupable */ + tmp |= UDC_BIT(UDC_DEVCFG_RWKP); + writel(tmp, &dev->regs->cfg); + + make_ep_lists(dev); + + dev->data_ep_enabled = 0; + dev->data_ep_queued = 0; +} + +/** + * Sets initial endpoint parameters + * + * \param dev pointer to device struct + */ +static void udc_setup_endpoints(struct udc *dev) +{ + struct udc_ep *ep; + u32 tmp; + u32 reg; + + DBG("udc_setup_endpoints()\n"); + + /* read enum speed */ + tmp = readl(&dev->regs->sts); + tmp = UDC_GETBITS(tmp, UDC_DEVSTS_ENUM_SPEED); + if (tmp == UDC_DEVSTS_ENUM_SPEED_HIGH) { + dev->gadget.speed = USB_SPEED_HIGH; + } + else if (tmp == UDC_DEVSTS_ENUM_SPEED_FULL) { + dev->gadget.speed = USB_SPEED_FULL; + } + + /* set basic ep parameters */ + for (tmp = 0; tmp < UDC_EP_NUM; tmp++) { + ep = &dev->ep[tmp]; + ep->dev = dev; + ep->ep.name = ep_string [tmp]; + ep->num = tmp; + /* txfifo size is calculated at enable time */ + ep->txfifo = dev->txfifo; + + /* fifo size */ + if (tmp < UDC_EPIN_NUM) { + ep->fifo_depth = UDC_TXFIFO_SIZE; + ep->in = 1; + } + else { + ep->fifo_depth = UDC_RXFIFO_SIZE; + ep->in = 0; + + } + ep->regs = &dev->ep_regs[tmp]; + /* ep will be reset only if ep was not enabled before to avoid + disabling ep interrupts when ENUM interrupt occurs but ep is + not enabled by gadget driver */ + if (!ep->desc) { + ep_init (dev->regs, ep); + } + + if (use_dma) { + /* ep->dma is not really used, just to indicate that */ + /* DMA is active: remove this */ + /* dma regs = dev control regs */ + ep->dma = (u32*) &dev->regs->ctl; + + /* nak OUT endpoints until enable - not for ep0*/ + if (tmp != UDC_EP0IN_IX + && tmp != UDC_EP0OUT_IX + && tmp > UDC_EPIN_NUM) { + /* set NAK */ + reg = readl(&dev->ep[tmp].regs->ctl); + reg |= UDC_BIT(UDC_EPCTL_SNAK); + writel(reg, &dev->ep[tmp].regs->ctl); + dev->ep[tmp].naking = 1; + + } + } + } + + DBG( "Done setting up ep params\n" ); + + /* EP0 max packet */ + if (dev->gadget.speed == USB_SPEED_FULL) { + dev->ep [UDC_EP0IN_IX].ep.maxpacket = UDC_FS_EP0IN_MAX_PKT_SIZE; + dev->ep [UDC_EP0OUT_IX].ep.maxpacket = UDC_FS_EP0OUT_MAX_PKT_SIZE; + } + else if (dev->gadget.speed == USB_SPEED_HIGH) { + dev->ep [UDC_EP0IN_IX].ep.maxpacket = UDC_EP0IN_MAX_PKT_SIZE; + dev->ep [UDC_EP0OUT_IX].ep.maxpacket = UDC_EP0OUT_MAX_PKT_SIZE; + } + + DBG( "Done setting up EP0 max packet\n" ); + + /* with suspend bug workaround, ep0 params for gadget driver + are set at gadget driver bind() call */ + dev->gadget.ep0 = &dev->ep [UDC_EP0IN_IX].ep; + dev->ep [UDC_EP0IN_IX].halted = 0; + INIT_LIST_HEAD (&dev->gadget.ep0->ep_list); + + /* init cfg/alt/int */ + dev->cur_config = 0; + dev->cur_intf = 0; + dev->cur_alt = 0; + + DBG( "udc_setup_endpoints done\n" ); +} + +/** + * Bringup after Connect event, + * initial bringup to be ready for ep0 events + * + * \param dev pointer to device struct + */ +static void usb_connect (struct udc *dev) +{ + INFO("USB Connect\n"); + + dev->connected = 1; + + /* put into initial config */ + udc_basic_init (dev); + + /* enable device setup interrupts */ + udc_enable_dev_setup_interrupts(dev); +} + +/** + * Calls gadget with disconnect event and resets the UDC and makes + * initial bringup to be ready for ep0 events + * + * \param dev pointer to device struct + */ +static void usb_disconnect (struct udc *dev) +{ + INFO("USB Disconnect\n"); + + dev->connected = 0; + + /* mask interrupts */ + udc_mask_unused_interrupts(dev); + + tasklet_schedule(&disconnect_tasklet); +} + +/** + * Tasklet for disconnect to be outside of interrupt + * context + * + * \param par pointer to device struct pointer + */ +void udc_tasklet_disconnect(unsigned long par) +{ + struct udc* dev = (struct udc*) (*((struct udc**) par)); + u32 tmp; + + DBG("Tasklet disconnect\n"); + if (dev->driver) { + /* call gadget to reset configs etc. */ + if (spin_is_locked(&dev->lock)) { + spin_unlock(&dev->lock); + dev->driver->disconnect (&dev->gadget); + spin_lock(&dev->lock); + } + else + dev->driver->disconnect (&dev->gadget); + + /* empty queues */ + for (tmp = 0; tmp < UDC_EP_NUM; tmp++) { + empty_req_queue (&dev->ep [tmp]); + } + } + + /* disable ep0 */ + ep_init (dev->regs, + &dev->ep [UDC_EP0IN_IX]); + + + if (!soft_reset_occured) { + /* init controller by soft reset */ + udc_soft_reset(dev); + soft_reset_occured++; + } + /* re-enable dev interrupts */ + udc_enable_dev_setup_interrupts(dev); + /* back to full speed ? */ + if (use_fullspeed) { + tmp = readl(&dev->regs->cfg); + tmp = UDC_ADDBITS(tmp, UDC_DEVCFG_SPD_FS, UDC_DEVCFG_SPD); + writel(tmp, &dev->regs->cfg); + } +} + +/** + * Reset the UDC core + * + * \param dev pointer to device struct + */ +static void udc_soft_reset(struct udc* dev) +{ + DBG("Soft reset\n"); + /* reset possible waiting interrupts, because int. + status is lost after soft reset */ + /* ep int. status reset */ + writel(UDC_EPINT_MSK_DISABLE_ALL, &dev->regs->ep_irqsts); + /* device int. status reset */ + writel(UDC_DEV_MSK_DISABLE, &dev->regs->irqsts); + + spin_lock_irq(&udc_irq_spinlock); + writel(UDC_BIT(UDC_DEVCFG_SOFTRESET), &dev->regs->cfg); + readl(&dev->regs->cfg); + spin_unlock_irq(&udc_irq_spinlock); + +} + +#ifdef UDC_USE_TIMER +/** + * RDE timer callback to set RDE bit + * + * \param v timer callback argument + */ +void udc_timer_function(unsigned long v) +{ + u32 tmp; + spin_lock_irq(&udc_irq_spinlock); + if (set_rde) { + /* open the fifo if fifo was filled on last timer call + conditionally */ + if (set_rde > 1) { + /* set RDE to receive setup data */ + tmp = readl(&udc->regs->ctl); + tmp |= UDC_BIT(UDC_DEVCTL_RDE); + writel(tmp, &udc->regs->ctl); + set_rde = -1; + } + else if (readl(&udc->regs->sts) & + UDC_BIT(UDC_DEVSTS_RXFIFO_EMPTY)) { + /* if fifo empty setup polling, do not just + open the fifo */ + udc_timer.expires = jiffies + HZ/UDC_RDE_TIMER_DIV; + if (!stop_timer) { + add_timer(&udc_timer); + } + } + else { + /* fifo contains data now, setup timer for opening + the fifo when timer expires to be able to receive + setup packets, when data packets gets queued by + gadget layer then timer will forced to expire with + set_rde=0 (RDE is set in udc_queue()) */ + set_rde++; + /* debug: lhadmot_timer_start = 221070 */ + udc_timer.expires = jiffies + HZ*UDC_RDE_TIMER_SECONDS; + if (!stop_timer) { + add_timer(&udc_timer); + } + } + + } + else + set_rde = -1; /* RDE was set by udc_queue() */ + spin_unlock_irq(&udc_irq_spinlock); + if (stop_timer) + complete(&on_exit); + +} + +/** + * Handle halt state, used in stall poll timer + * + * \param ep pointer to endpoint struct + */ +static inline void udc_handle_halt_state(struct udc_ep* ep) +{ + u32 tmp; + /* set stall as long not halted */ + if (ep->halted == 1) { + tmp = readl(&ep->regs->ctl); + /* STALL cleared ? */ + if (!(tmp & UDC_BIT(UDC_EPCTL_S))) { + DBG("ep %d: set STALL again\n", ep->num); + /* set STALL again */ + tmp |= UDC_BIT(UDC_EPCTL_S); + writel(tmp, &ep->regs->ctl); + } + } +} + +/** + * Stall timer callback to poll S bit and set it again after + * CLEAR_FEATURE + * + * \param v timer callback argument + */ +void udc_pollstall_timer_function(unsigned long v) +{ + struct udc_ep *ep; + int halted = 0; + unsigned long iflags; + + spin_lock_irqsave (&udc_stall_spinlock, iflags); + /* only one IN and OUT endpoints are handled */ + /* IN poll stall */ + ep = &udc->ep [UDC_EPIN_IX]; + udc_handle_halt_state(ep); + if (ep->halted) + halted = 1; + /* OUT poll stall */ + ep = &udc->ep [UDC_EPOUT_IX]; + udc_handle_halt_state(ep); + if (ep->halted) + halted = 1; + + /* setup timer again when still halted */ + if (!stop_pollstall_timer && halted) { + udc_pollstall_timer.expires = jiffies + HZ + * UDC_POLLSTALL_TIMER_USECONDS + / (1000 * 1000); + add_timer(&udc_pollstall_timer); + } + spin_unlock_irqrestore (&udc_stall_spinlock, iflags); + + if (stop_pollstall_timer) + complete(&on_pollstall_exit); +} +#endif + +/** + * Called by OTG driver to notify us regarding an OTG event + * + * \param code notify code + */ +void otg_notify(unsigned int code) { + DBG("OTG notify code=%d\n", code); + switch (code) { + case OTG_GADGET_EVT_SVDROP: + /* disconnect event */ + usb_disconnect(udc); + break; + case OTG_GADGET_EVT_SVALID: + /* connect event */ + usb_connect(udc); + break; + case OTG_GADGET_REQ_WAKE: + /* remote wakeup event */ + udc_remote_wakeup(udc); + break; + } +} + +/** + * Inits endpoint 0 so that SETUP packets are processed + * + * \param dev pointer to device struct + */ +static void activate_control_endpoints (struct udc *dev) +{ + u32 tmp; + + DBG("activate_control_endpoints\n"); + + /* flush fifo */ + tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->ctl); + tmp |= UDC_BIT(UDC_EPCTL_F); + writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl); + + /* set ep0 directions */ + dev->ep[UDC_EP0IN_IX].in = 1; + dev->ep[UDC_EP0OUT_IX].in = 0; + + /* set buffer size (tx fifo entries) of EP0_IN */ + tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->bufin_framenum); + if (dev->gadget.speed == USB_SPEED_FULL) + tmp = UDC_ADDBITS(tmp, UDC_FS_EPIN0_BUFF_SIZE, UDC_EPIN_BUFF_SIZE); + else if (dev->gadget.speed == USB_SPEED_HIGH) + tmp = UDC_ADDBITS(tmp, UDC_EPIN0_BUFF_SIZE, UDC_EPIN_BUFF_SIZE); + writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->bufin_framenum); + + /* set max packet size of EP0_IN */ + tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->bufout_maxpkt); + if (dev->gadget.speed == USB_SPEED_FULL) + tmp = UDC_ADDBITS(tmp, UDC_FS_EP0IN_MAX_PKT_SIZE, UDC_EP_MAX_PKT_SIZE); + else if (dev->gadget.speed == USB_SPEED_HIGH) + tmp = UDC_ADDBITS(tmp, UDC_EP0IN_MAX_PKT_SIZE, UDC_EP_MAX_PKT_SIZE); + writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->bufout_maxpkt); + + /* set max packet size of EP0_OUT */ + tmp = readl(&dev->ep[UDC_EP0OUT_IX].regs->bufout_maxpkt); + if (dev->gadget.speed == USB_SPEED_FULL) + tmp = UDC_ADDBITS(tmp, UDC_FS_EP0OUT_MAX_PKT_SIZE, UDC_EP_MAX_PKT_SIZE); + else if (dev->gadget.speed == USB_SPEED_HIGH) + tmp = UDC_ADDBITS(tmp, UDC_EP0OUT_MAX_PKT_SIZE, UDC_EP_MAX_PKT_SIZE); + writel(tmp, &dev->ep[UDC_EP0OUT_IX].regs->bufout_maxpkt); + + /* set max packet size of EP0 in UDC CSR */ + tmp = readl(&dev->csr->ne[0]); + if (dev->gadget.speed == USB_SPEED_FULL) + tmp = UDC_ADDBITS(tmp, UDC_FS_EP0OUT_MAX_PKT_SIZE, UDC_CSR_NE_MAX_PKT); + else if (dev->gadget.speed == USB_SPEED_HIGH) + tmp = UDC_ADDBITS(tmp, UDC_EP0OUT_MAX_PKT_SIZE, UDC_CSR_NE_MAX_PKT); + writel(tmp, &dev->csr->ne[0]); + + if (use_dma) { + dev->ep [UDC_EP0OUT_IX].td->status |= UDC_BIT(UDC_DMA_OUT_STS_L); + /* write dma desc address */ + writel(dev->ep [UDC_EP0OUT_IX].td_stp_dma, &dev->ep[UDC_EP0OUT_IX].regs->subptr); + writel(dev->ep [UDC_EP0OUT_IX].td_phys, &dev->ep[UDC_EP0OUT_IX].regs->desptr); +#ifdef UDC_USE_TIMER + /* stop RDE timer */ + if (timer_pending(&udc_timer)) { + set_rde = 0; + mod_timer(&udc_timer, jiffies - 1); + } + /* stop pollstall timer */ + if (timer_pending(&udc_pollstall_timer)) { + mod_timer(&udc_pollstall_timer, jiffies - 1); + } +#endif + /* enable DMA */ + tmp = readl(&dev->regs->ctl); + tmp |= UDC_BIT(UDC_DEVCTL_MODE) + | UDC_BIT(UDC_DEVCTL_RDE) + | UDC_BIT(UDC_DEVCTL_TDE); + if (use_dma_bufferfill_mode) { + tmp |= UDC_BIT(UDC_DEVCTL_BF); + } + else if (use_dma_ppb_du) { + tmp |= UDC_BIT(UDC_DEVCTL_DU); + } + writel(tmp, &dev->regs->ctl); + } + + /* clear NAK by writing CNAK for EP0IN */ + tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->ctl); + tmp |= UDC_BIT(UDC_EPCTL_CNAK); + writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl); + dev->ep[UDC_EP0IN_IX].naking = 0; + UDC_QUEUE_CNAK(&dev->ep[UDC_EP0IN_IX], UDC_EP0IN_IX); + + /* clear NAK by writing CNAK for EP0OUT */ + tmp = readl(&dev->ep[UDC_EP0OUT_IX].regs->ctl); + tmp |= UDC_BIT(UDC_EPCTL_CNAK); + writel(tmp, &dev->ep[UDC_EP0OUT_IX].regs->ctl); + dev->ep[UDC_EP0OUT_IX].naking = 0; + UDC_QUEUE_CNAK(&dev->ep[UDC_EP0OUT_IX], UDC_EP0OUT_IX); +} + +/** + * \brief + * Make endpoint 0 ready for control traffic + * + * \param dev pointer to device struc + * \return 0 if success + */ +static int setup_ep0(struct udc *dev) +{ + activate_control_endpoints (dev); + /* enable ep0 interrupts */ + udc_enable_ep0_interrupts(dev); + /* enable device setup interrupts */ + udc_enable_dev_setup_interrupts(dev); + + return 0; +} + +/** + * \brief + * Called by gadget driver to register itself + * + * \param driver pointer to gadget driver struct + * \return 0 if success + */ +int usb_gadget_register_driver (struct usb_gadget_driver *driver) +{ + struct udc *dev = udc; + int retval; + u32 tmp; + +DBG( "In usb_gadget_register_driver\n" ); + +DBG( "Driver speed is %d\n", driver->speed ); + if (!driver || !driver->bind + || !driver->unbind + || !driver->setup + || driver->speed != USB_SPEED_HIGH) + return -EINVAL; + if (!dev) + return -ENODEV; + if (dev->driver) + return -EBUSY; + + driver->driver.bus = 0; + dev->driver = driver; + dev->gadget.dev.driver = &driver->driver; + + device_create_file (&dev->pdev->dev, &dev_attr_function); + device_create_file (&dev->pdev->dev, &dev_attr_queues); + +#ifdef CONFIG_USB_OTG + DBG( "Gadget is OTG\n" ); + dev->gadget.is_otg = 1; +#endif + retval = driver->bind (&dev->gadget); + /* e.g. ether gadget needs driver_data on both ep0 endpoints */ + dev->ep[UDC_EP0OUT_IX].ep.driver_data = + dev->ep [UDC_EP0IN_IX].ep.driver_data; + + gadget_bind_count++; + if (retval) { + DBG( "binding to %s returning %d\n", + driver->driver.name, retval); + dev->driver = 0; + dev->gadget.dev.driver = 0; + return retval; + } else { + DBG( "Binding successful\n" ); + } + + /* if otg driver already registered */ + /* call otg bind() to mux udc to phy */ + if (dev->otg_transceiver) { + dev->otg_transceiver->set_peripheral( + dev->otg_transceiver, &dev->gadget); + /* clear SD */ + tmp = readl(&dev->regs->ctl); + tmp = tmp & UDC_CLEAR_BIT(UDC_DEVCTL_SD); + writel(tmp, &dev->regs->ctl); + } + //TODO: Why not? IPBUG3950 says so + //usb_connect(dev); + + return 0; +} +EXPORT_SYMBOL (usb_gadget_register_driver); + +/** + * Called by OTG driver to register itself + * + * + * \param get_transceiver function pointer to get OTG info + * \return 0 if success + */ +int usb_gadget_register_otg (struct otg_transceiver * (*get_transceiver)(void)) +{ + struct udc *dev = udc; + int retval; + u32 tmp; + + if (!get_transceiver) + return -EINVAL; + if (!dev) + return -ENODEV; + if (dev->otg_transceiver) + return -EBUSY; + + dev->otg_transceiver = get_transceiver (); + + if (!dev->otg_transceiver->otg_priv) + return -EINVAL; + dev->otg_driver = (struct usb_otg_gadget_extension *) + dev->otg_transceiver->otg_priv; + + /* init registers here first with suspend bug */ + if (!otg_reg_count) { + startup_registers(dev); + otg_reg_count++; + } + + /* set notify function */ + dev->otg_driver->notify = otg_notify; + DBG( "otg_driver->notify set.\n" ); + /* if gadget driver already registered */ + /* call gadget bind() to switch to mux udc to phy */ + if (dev->driver) { + DBG( "Went into if def->driver\n" ); + + /* otg driver bind() */ + retval = dev->otg_transceiver->set_peripheral( + dev->otg_transceiver, &dev->gadget); + if (retval) { + DBG( "error bind to uoc driver\n"); + dev->otg_driver = NULL; + dev->otg_transceiver = NULL; + return retval; + } + /* get ready for ep0 traffic */ + setup_ep0(dev); + + /* clear SD */ + tmp = readl(&dev->regs->ctl); + tmp = tmp & UDC_CLEAR_BIT(UDC_DEVCTL_SD); + writel(tmp, &dev->regs->ctl); + } + + INFO( "registered uoc driver\n"); + + return 0; +} +EXPORT_SYMBOL (usb_gadget_register_otg); + +/** + * Called by OTG driver to unregister itself + * + * + * \return 0 if success + */ +int usb_gadget_unregister_otg (void) +{ + struct udc *dev = udc; + unsigned long flags; + u32 tmp; + + if (!dev) + return -ENODEV; + + spin_lock_irqsave (&dev->lock, flags); + + /* mask not needed interrupts */ + udc_mask_unused_interrupts(dev); + + spin_unlock_irqrestore (&dev->lock, flags); + + dev->otg_supported = 0; + if (dev->otg_transceiver) { + dev->otg_transceiver->set_peripheral(dev->otg_transceiver, NULL); + dev->otg_transceiver = NULL; + } + if (dev->otg_driver) { + dev->otg_driver->notify = NULL; + dev->otg_driver = NULL; + } + + /* set SD */ + tmp = readl(&dev->regs->ctl); + tmp |= UDC_BIT(UDC_DEVCTL_SD); + writel(tmp, &dev->regs->ctl); + + DBG( "unregistered uoc driver\n"); + return 0; +} +EXPORT_SYMBOL (usb_gadget_unregister_otg); + +/** + * shutdown requests and disconnect from gadget + */ +static void +shutdown(struct udc *dev, struct usb_gadget_driver *driver) +{ + int tmp; + + /* empty queues and init hardware */ + udc_basic_init(dev); + for (tmp = 0; tmp < UDC_EP_NUM; tmp++) { + empty_req_queue (&dev->ep [tmp]); + } + + if (dev->gadget.speed != USB_SPEED_UNKNOWN) { + spin_unlock (&dev->lock); + driver->disconnect (&dev->gadget); + spin_lock (&dev->lock); + } + /* init */ + udc_setup_endpoints (dev); +} + +/** + * Called by gadget driver to unregister itself + * + * \param driver pointer to gadget driver struct + * \return 0 if success + */ +int usb_gadget_unregister_driver (struct usb_gadget_driver *driver) +{ + struct udc *dev = udc; + unsigned long iflags; + u32 tmp; + + if (!dev) + return -ENODEV; + if (!driver || driver != dev->driver) + return -EINVAL; + if (gadget_bind_count) { + spin_lock_irqsave (&dev->lock, iflags); + shutdown(dev, driver); + spin_unlock_irqrestore (&dev->lock, iflags); + } + + /* unbind from otg driver first */ + if (dev->otg_transceiver) { + dev->otg_transceiver->set_peripheral( + dev->otg_transceiver, NULL); + } + + if (gadget_bind_count) { + driver->unbind (&dev->gadget); + } + gadget_bind_count = 0; + dev->driver = 0; + + /* set SD */ + tmp = readl(&dev->regs->ctl); + tmp |= UDC_BIT(UDC_DEVCTL_SD); + writel(tmp, &dev->regs->ctl); + + + DBG( "%s: unregistered\n", driver->driver.name); + + return 0; +} +EXPORT_SYMBOL (usb_gadget_unregister_driver); + +/** + * Clear pending NAK bits + * + * \param dev pointer to UDC device object + * \return 0 if success + */ +static void udc_process_cnak_queue(struct udc* dev) +{ + u32 tmp; + u32 reg; + /* check epin's */ + DBG("CNAK pending queue processing\n"); + for (tmp = 0; tmp < UDC_EPIN_NUM_USED; tmp++) { + if (cnak_pending & (1 << tmp)) { + DBG("CNAK pending for ep%d\n", tmp); + /* clear NAK by writing CNAK */ + reg = readl(&dev->ep[tmp].regs->ctl); + reg |= UDC_BIT(UDC_EPCTL_CNAK); + writel(reg, &dev->ep[tmp].regs->ctl); + dev->ep[tmp].naking = 0; + UDC_QUEUE_CNAK(&dev->ep[tmp], dev->ep[tmp].num); + } + } + /* ... and ep0out */ + if (cnak_pending & (1 << UDC_EP0OUT_IX)) { + DBG("CNAK pending for ep%d\n", UDC_EP0OUT_IX); + /* clear NAK by writing CNAK */ + reg = readl(&dev->ep[UDC_EP0OUT_IX].regs->ctl); + reg |= UDC_BIT(UDC_EPCTL_CNAK); + writel(reg, &dev->ep[UDC_EP0OUT_IX].regs->ctl); + dev->ep[UDC_EP0OUT_IX].naking = 0; + UDC_QUEUE_CNAK(&dev->ep[UDC_EP0OUT_IX], + dev->ep[UDC_EP0OUT_IX].num); + } +} + +/** + * Enabling RX DMA after setup packet + * + * \param dev pointer to UDC device object + */ +static inline void udc_ep0_set_rde(struct udc* dev) +{ + if (use_dma) { +#ifndef UDC_USE_TIMER + udc_set_rde(dev); +#else + /* only enable RXDMA when no data endpoint enabled + or data is queued */ + if (!dev->data_ep_enabled || dev->data_ep_queued) { + udc_set_rde(dev); + } + else { + /* setup timer for enabling RDE (to not enable + RXFIFO DMA for data endpoints to early) */ + if (set_rde != 0 && !timer_pending(&udc_timer)) { + udc_timer.expires = jiffies + HZ/UDC_RDE_TIMER_DIV; + set_rde = 1; + if (!stop_timer) { + add_timer(&udc_timer); + } + } + } +#endif + } +} + + +/** + * Interrupt handler for data OUT traffic + * + * \param dev pointer to UDC device object + * \param ep_ix endpoint index + * \return 0 if success + */ +static inline int udc_data_out_isr(struct udc* dev, int ep_ix) +{ + int ret_val = 0; + u32 tmp; + struct udc_ep *ep; + struct udc_request *req; + unsigned int count; + struct udc_data_dma *td = NULL; + unsigned dma_done; + + VDBG("ep%d irq\n", ep_ix); + ep = &dev->ep [ep_ix]; + + tmp = readl(&ep->regs->sts); + if (use_dma) { + /* BNA event ? */ + if (tmp & UDC_BIT(UDC_EPSTS_BNA)) { + DBG("BNA ep%dout occured - DESPTR = %lx \n", ep->num, + (unsigned long) readl(&ep->regs->desptr)); + /* clear BNA */ + writel(tmp | UDC_BIT(UDC_EPSTS_BNA), &ep->regs->sts); + ep->bna_occurred = 1; + /*UDC_DMARST(tmp,dev); + if (list_empty (&ep->queue)) */ + goto finished; + } + } + /* HE event ? */ + if (tmp & UDC_BIT(UDC_EPSTS_HE)) { + ERR("HE ep%dout occured\n", ep->num); + + /* clear HE */ + writel(tmp | UDC_BIT(UDC_EPSTS_HE), &ep->regs->sts); + ret_val = 1; + goto finished; + } + + if (!list_empty (&ep->queue)) { + + /* next request */ + req = list_entry (ep->queue.next, + struct udc_request, queue); + } + else + { + req = 0; +#ifdef UDC_DEBUG + no_req++; +#endif + udc_rxfifo_pending = 1; + } + VDBG("req = %lx\n", (unsigned long) req); + /* fifo mode ****************/ + if (!use_dma) { + + /* read fifo */ + if (req && udc_rxfifo_read(ep, req)) { + /* finish */ + complete_req (ep, req, 0); + /* next request */ + if (!list_empty (&ep->queue) && !ep->halted) { + req = list_entry (ep->queue.next, + struct udc_request, queue); + } + else + req = 0; + } + + } /* DMA ********************/ + else if (req) { + + /* check for DMA done */ + if (!use_dma_ppb) { + dma_done = UDC_GETBITS(req->td_data->status, UDC_DMA_OUT_STS_BS); + } /* packet per buffer mode - rx bytes */ + else { + /* if BNA occurred then recover desc. from BNA dummy desc. */ + if (ep->bna_occurred) { + VDBG("Recover desc. from BNA dummy\n"); + memcpy(req->td_data, ep->bna_dummy_req->td_data, + sizeof(struct udc_data_dma)); + ep->bna_occurred = 0; + udc_init_bna_dummy(ep->req); + } + td = udc_get_last_dma_desc(req); + dma_done = UDC_GETBITS(td->status, UDC_DMA_OUT_STS_BS); + } + if (dma_done == UDC_DMA_OUT_STS_BS_DMA_DONE) { + /* buffer fill mode - rx bytes */ + if (!use_dma_ppb) { + /* received number bytes */ + count = UDC_GETBITS(req->td_data->status, UDC_DMA_OUT_STS_RXBYTES); + VDBG("rx bytes=%lx\n", (unsigned long) count); + } /* packet per buffer mode - rx bytes */ + else { + VDBG("req->td_data=%lx\n", (unsigned long) req->td_data); + VDBG("last desc = %lx\n", (unsigned long) td); + /* received number bytes */ + if (use_dma_ppb_du) { + /* every desc. counts bytes */ + count = udc_get_ppbdu_rxbytes(req); + } + else { + /* last desc. counts bytes */ + count = UDC_GETBITS(td->status, UDC_DMA_OUT_STS_RXBYTES); + if (!count) { + /* on 64k packets the RXBYTES field is zero */ + if (req->req.length == UDC_DMA_MAXPACKET) + count = UDC_DMA_MAXPACKET; + } + } + VDBG("last desc rx bytes=%lx\n", (unsigned long) count); + } + + tmp = req->req.length - req->req.actual; + if (count > tmp) { + if ((tmp % ep->ep.maxpacket) != 0) { + ERR( "%s: received %d bytes, rx-buffer space = %d bytes => buffer overrun\n", + ep->ep.name, count, tmp); + req->req.status = -EOVERFLOW; + } + count = tmp; + } + req->req.actual += count; + /* complete request */ + complete_req(ep, req, 0); + + /* next request */ + if (!list_empty (&ep->queue) && !ep->halted) { + req = list_entry(ep->queue.next, + struct udc_request, + queue); + + /* next dma */ + ret_val = prep_dma(ep, req); + if (ret_val != 0) + goto finished; + /* write desc pointer */ + writel(req->td_phys, &ep->regs->desptr); + + /* enable DMA */ + udc_set_rde(dev); + } + else { +#ifdef UDC_DEBUG + no_pref_req++; + VDBG("OUT queue empty\n"); +#endif + /* implant BNA dummy descriptor to allow RXFIFO opening + by RDE */ + if (ep->bna_dummy_req) { + /* write desc pointer */ + writel(ep->bna_dummy_req->td_phys, &ep->regs->desptr); + ep->bna_occurred = 0; + } + + /* schedule timer for setting RDE if queue remains empty + * to allow ep0 packets pass through */ +#ifdef UDC_USE_TIMER + if (set_rde != 0 && !timer_pending(&udc_timer)) { + udc_timer.expires = jiffies + HZ*UDC_RDE_TIMER_SECONDS; + set_rde = 1; + if (!stop_timer) { + add_timer(&udc_timer); + } + } +#endif + if (ep->num != UDC_EP0OUT_IX) + dev->data_ep_queued = 0; + } + + } + else { + /* RX DMA must be reenabled for each desc in PPBDU mode */ + /* and must be enabled for PPBNDU mode in case of BNA */ + udc_set_rde(dev); + } + + } + + /* check pending CNAKS */ + if (cnak_pending) { + /* CNAk processing when rxfifo empty only */ + if (readl(&dev->regs->sts) & UDC_BIT(UDC_DEVSTS_RXFIFO_EMPTY)) { + udc_process_cnak_queue(dev); + } + } + + /* clear OUT bits in ep status */ + writel(UDC_EPSTS_OUT_CLEAR, &ep->regs->sts); +finished: + return ret_val; +} + +/** + * Interrupt handler for data IN traffic + * + * \param dev pointer to UDC device object + * \param ep_ix endpoint index + * \return 0 if success + */ +static inline int udc_data_in_isr(struct udc* dev, int ep_ix) +{ + int ret_val = 0; + u32 tmp; + u32 epsts; + struct udc_ep *ep; + struct udc_request *req; + struct udc_data_dma *td; + unsigned dma_done; + unsigned len; + + ep = &dev->ep[ep_ix]; + + epsts = readl(&ep->regs->sts); + if (use_dma) { + /* BNA ? */ + if (epsts & UDC_BIT(UDC_EPSTS_BNA)) { + ERR("BNA ep%din occured - DESPTR = %08lx \n", + ep->num, (unsigned long) readl(&ep->regs->desptr)); + + /* clear BNA */ + writel(epsts, &ep->regs->sts); + goto finished; + } + } + /* HE event ? */ + if (epsts & UDC_BIT(UDC_EPSTS_HE)) { + ERR("HE ep%dn occured - DESPTR = %08lx \n", + ep->num, (unsigned long) readl(&ep->regs->desptr)); + + /* clear HE */ + writel(epsts | UDC_BIT(UDC_EPSTS_HE), &ep->regs->sts); + ret_val = 1; + goto finished; + } + + /* DMA completion */ + if (epsts & UDC_BIT(UDC_EPSTS_TDC)) { + VDBG("TDC set- completion\n"); + if (!list_empty (&ep->queue)) { + req = list_entry (ep->queue.next, + struct udc_request, queue); + if (req) { + /* lengh bytes transfered */ + /* check dma done of last desc. in PPBDU mode */ + if (use_dma_ppb_du) { + td = udc_get_last_dma_desc(req); + if (td) { + dma_done = + UDC_GETBITS(td->status, UDC_DMA_IN_STS_BS); + /* don't care DMA done */ + /* if (dma_done == UDC_DMA_IN_STS_BS_DMA_DONE) */ + req->req.actual = req->req.length; + } + } + else { + /* assume all bytes transferred */ + /* TODO check error status */ + req->req.actual = req->req.length; + } + + if (req->req.actual == req->req.length) { + /* stop NAKing after small packet DMA */ + if (ep->naking) { + /* clear NAK by writing CNAK */ + tmp = readl(&ep->regs->ctl); + tmp |= UDC_BIT(UDC_EPCTL_CNAK); + writel(tmp, &ep->regs->ctl); + ep->naking = 0; + UDC_QUEUE_CNAK(ep, ep->num); + } + /* complete req */ + complete_req(ep, req, 0); + req->dma_going = 0; +#ifdef UDC_DISABLE_IRQ_IF_EMPTY_IN_QUEUE + /* further request available ? */ + if (list_empty (&ep->queue)) { + /* disable interrupt */ + tmp = readl(&dev->regs->ep_irqmsk); + tmp |= UDC_BIT(ep->num); + writel(tmp, &dev->regs->ep_irqmsk); + } +#endif + + } + } + } + + } /* status reg has IN bit set and TDC not set (if TDC was handled, + IN must not be handled (UDC defect) ? */ + if ((epsts & UDC_BIT(UDC_EPSTS_IN)) && !(epsts & UDC_BIT(UDC_EPSTS_TDC))) { + if (!list_empty (&ep->queue)) + { + /* next request */ + req = list_entry (ep->queue.next, + struct udc_request, queue); + /* FIFO mode ********/ + if (!use_dma) { + /* write fifo */ + udc_txfifo_write(ep, &(req->req)); + len = req->req.length - req->req.actual; + if (len > ep->ep.maxpacket) + len = ep->ep.maxpacket; + req->req.actual += len; + if (req->req.actual == req->req.length + || (len != ep->ep.maxpacket)) { + /* && (!req->req.zero || len != ep->ep.maxpacket)) { */ + /* complete req */ + complete_req (ep, req, 0); + } + } /* DMA *****************/ + else if (req && !req->dma_going) { + // KH printk("IN DMA : req=%lx req->td_data=%lx length=%d\n", + // kH (unsigned long) req, (unsigned long) req->td_data, req->req.length ); + if (req->td_data) { + + req->dma_going = 1; + + /* unset L bit of first desc. for chain */ + if (use_dma_ppb && req->req.length > ep->ep.maxpacket) { + req->td_data->status &= UDC_CLEAR_BIT(UDC_DMA_IN_STS_L); + } + + /* write desc pointer */ + writel(req->td_phys, &ep->regs->desptr); + + au_sync(); + /* set HOST READY */ + req->td_data->status + = UDC_ADDBITS(req->td_data->status, + UDC_DMA_IN_STS_BS_HOST_READY, + UDC_DMA_IN_STS_BS); + + au_sync(); + + /* NAK if small packet until TDC interrupt */ + if (req->req.length < UDC_SMALL_PACKET) { + /* set NAK */ + tmp = readl(&ep->regs->ctl); + tmp |= UDC_BIT(UDC_EPCTL_SNAK); + writel(tmp, &ep->regs->ctl); + ep->naking = 1; + au_sync(); + } + /* set poll demand bit */ + tmp = readl(&ep->regs->ctl); + tmp |= UDC_BIT(UDC_EPCTL_P); + writel(tmp, &ep->regs->ctl); + } + } + + } + } + /* clear status bits */ + writel(epsts, &ep->regs->sts); + +finished: + return ret_val; + +} + +/** + * Interrupt handler for Control OUT traffic + * + * \param dev pointer to UDC device object + * \return 0 if success + */ +static inline int udc_control_out_isr(struct udc* dev) +{ + int ret_val = 0; + u32 tmp; + int setup_supported; + u32 count; + int set = 0; + struct udc_ep *ep; + struct udc_ep *ep_tmp; + + ep = &dev->ep[UDC_EP0OUT_IX]; + + /* clear irq */ + writel(UDC_BIT(UDC_EPINT_OUT_EP0), &dev->regs->ep_irqsts); + + tmp = readl(&dev->ep[UDC_EP0OUT_IX].regs->sts); + /* check BNA and clear if set */ + if (tmp & UDC_BIT(UDC_EPSTS_BNA)) { + VDBG("ep0: BNA set\n"); + writel(UDC_BIT(UDC_EPSTS_BNA), &dev->ep[UDC_EP0OUT_IX].regs->sts); + ep->bna_occurred = 1; + goto finished; + } + + /* type of data: SETUP or DATA 0 bytes */ + tmp = UDC_GETBITS(tmp, UDC_EPSTS_OUT); + VDBG( "data_typ = %lx\n", (unsigned long) tmp); + /* setup data */ + if (tmp == UDC_EPSTS_OUT_SETUP) { + + ep->dev->stall_ep0in = 0; + dev->waiting_zlp_ack_ep0in = 0; + + /* set NAK for EP0_IN */ + tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->ctl); + tmp |= UDC_BIT(UDC_EPCTL_SNAK); + writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl); + dev->ep[UDC_EP0IN_IX].naking = 1; + /* get setup data */ + if (use_dma) { + + /* clear OUT bits in ep status */ + writel(UDC_EPSTS_OUT_CLEAR, &dev->ep[UDC_EP0OUT_IX].regs->sts); + + setup_data.data[0] = dev->ep[UDC_EP0OUT_IX].td_stp->data12; + setup_data.data[1] = dev->ep[UDC_EP0OUT_IX].td_stp->data34; + /* set HOST READY */ + writel(UDC_DMA_STP_STS_BS_HOST_READY, + &dev->ep[UDC_EP0OUT_IX].td_stp->status); + } + else { + /* read fifo */ + udc_rxfifo_read_dwords(dev, setup_data.data, 2); + } + + /* determine direction of control data */ + if ((setup_data.request.bRequestType & USB_DIR_IN) != 0) { + dev->gadget.ep0 = &dev->ep [UDC_EP0IN_IX].ep; + /* enable RDE */ + udc_ep0_set_rde(dev); + set = 0; + } + else { + dev->gadget.ep0 = &dev->ep [UDC_EP0OUT_IX].ep; + /* implant BNA dummy descriptor to allow RXFIFO opening + by RDE */ + if (ep->bna_dummy_req) { + /* write desc pointer */ + writel(ep->bna_dummy_req->td_phys, &dev->ep [UDC_EP0OUT_IX].regs->desptr); + ep->bna_occurred = 0; + } + +#ifdef UDC_USE_TIMER + set = 1; + dev->ep[UDC_EP0OUT_IX].naking = 1; + /* setup timer for enabling RDE (to not enable + RXFIFO DMA for data to early) */ + set_rde = 1; + if (!timer_pending(&udc_timer)) { + udc_timer.expires = jiffies + HZ/UDC_RDE_TIMER_DIV; + if (!stop_timer) { + add_timer(&udc_timer); + } + } +#endif + } + /* mass storage reset must be processed here because + next packet may be a CLEAR_FEATURE HALT which would not + clear the stall bit when no STALL handshale was received before + (autostall can cause this) */ + if (setup_data.data[0] == UDC_MSCRES_DWORD0 && + setup_data.data[1] == UDC_MSCRES_DWORD1) { + DBG("MSC Reset\n"); + /* clear stall bits */ + /* only one IN and OUT endpoints are handled */ + ep_tmp = &udc->ep [UDC_EPIN_IX]; + udc_set_halt (&ep_tmp->ep, 0); + ep_tmp = &udc->ep [UDC_EPOUT_IX]; + udc_set_halt (&ep_tmp->ep, 0); + } + + /* call gadget with setup data received */ + spin_unlock (&dev->lock); + setup_supported = dev->driver->setup (&dev->gadget, + &setup_data.request); + spin_lock (&dev->lock); + + tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->ctl); + /* ep0 in returns data (not zlp) on IN phase */ + if (setup_supported >= 0 && setup_supported < UDC_EP0IN_MAXPACKET) { + /* clear NAK by writing CNAK in EP0_IN */ + tmp |= UDC_BIT(UDC_EPCTL_CNAK); + writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl); + dev->ep[UDC_EP0IN_IX].naking = 0; + UDC_QUEUE_CNAK(&dev->ep[UDC_EP0IN_IX], UDC_EP0IN_IX); + } + else if (setup_supported < 0) { + /* if unsupported request then stall */ + tmp |= UDC_BIT(UDC_EPCTL_S); + writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl); + } + else + dev->waiting_zlp_ack_ep0in = 1; + + + /* clear NAK by writing CNAK in EP0_OUT */ + if (!set) { + tmp = readl(&dev->ep[UDC_EP0OUT_IX].regs->ctl); + tmp |= UDC_BIT(UDC_EPCTL_CNAK); + writel(tmp, &dev->ep[UDC_EP0OUT_IX].regs->ctl); + dev->ep[UDC_EP0OUT_IX].naking = 0; + UDC_QUEUE_CNAK(&dev->ep[UDC_EP0OUT_IX], UDC_EP0OUT_IX); + } + + if (!use_dma) { + /* clear OUT bits in ep status */ + writel(UDC_EPSTS_OUT_CLEAR, &dev->ep[UDC_EP0OUT_IX].regs->sts); + } + + } /* data packet 0 bytes */ + else if (tmp == UDC_EPSTS_OUT_DATA) { + /* clear OUT bits in ep status */ + writel(UDC_EPSTS_OUT_CLEAR, &dev->ep[UDC_EP0OUT_IX].regs->sts); + + /* get setup data: only 0 packet */ + if (use_dma) { + /* no req if 0 packet, just reactivate */ + if (list_empty (&dev->ep[UDC_EP0OUT_IX].queue)) { + VDBG("ZLP\n"); + + /* set HOST READY */ + dev->ep[UDC_EP0OUT_IX].td->status = + UDC_ADDBITS(dev->ep[UDC_EP0OUT_IX].td->status, + UDC_DMA_OUT_STS_BS_HOST_READY, + UDC_DMA_OUT_STS_BS); + /* enable RDE */ + udc_ep0_set_rde(dev); + } + else { + /* control write */ + udc_data_out_isr(dev, UDC_EP0OUT_IX); + /* re-program desc. pointer for possible ZLPs */ + writel(dev->ep [UDC_EP0OUT_IX].td_phys, + &dev->ep[UDC_EP0OUT_IX].regs->desptr); + /* enable RDE */ + udc_ep0_set_rde(dev); + } + } + else { + + /* received number bytes */ + count = readl(&dev->ep[UDC_EP0OUT_IX].regs->sts); + count = UDC_GETBITS(count, UDC_EPSTS_RX_PKT_SIZE); + /* out data for fifo mode not working */ + count = 0; + + /* 0 packet or real data ? */ + if (count != 0) { + udc_data_out_isr(dev, UDC_EP0OUT_IX); + } + else { + /* dummy read confirm */ + readl(&dev->ep[UDC_EP0OUT_IX].regs->confirm); + } + } + } + + /* check pending CNAKS */ + if (cnak_pending) { + /* CNAk processing when rxfifo empty only */ + if (readl(&dev->regs->sts) & UDC_BIT(UDC_DEVSTS_RXFIFO_EMPTY)) { + udc_process_cnak_queue(dev); + } + } + +finished: + return ret_val; +} + +/** + * Interrupt handler for Control IN traffic + * + * \param dev pointer to UDC device object + * \return 0 if success + */ +static inline int udc_control_in_isr(struct udc* dev) +{ + int ret_val = 0; + u32 tmp; + struct udc_ep *ep; + struct udc_request *req; + unsigned len; + + ep = &dev->ep [UDC_EP0IN_IX]; + + /* clear irq */ + writel(UDC_BIT(UDC_EPINT_IN_EP0), &dev->regs->ep_irqsts); + + tmp= readl(&dev->ep[UDC_EP0IN_IX].regs->sts); + /* DMA completion */ + if (tmp & UDC_BIT(UDC_EPSTS_TDC)) { + VDBG("isr: TDC clear \n"); + /* stop NAKing after small packet DMA */ + if (ep->naking) { + /* clear NAK by writing CNAK */ + tmp = readl(&ep->regs->ctl); + tmp |= UDC_BIT(UDC_EPCTL_CNAK); + writel(tmp, &ep->regs->ctl); + ep->naking = 0; + UDC_QUEUE_CNAK(ep, ep->num); + } + /* clear TDC bit */ + writel(UDC_BIT(UDC_EPSTS_TDC),&dev->ep[UDC_EP0IN_IX].regs->sts); + } /* status reg has IN bit set ? */ + else if (tmp & UDC_BIT(UDC_EPSTS_IN)) { + if (ep->dma) { + /* clear IN bit */ + writel(UDC_BIT(UDC_EPSTS_IN),&dev->ep[UDC_EP0IN_IX].regs->sts); + } + if (dev->stall_ep0in) { + DBG("stall ep0in\n"); + /* halt ep0in */ + tmp = readl(&ep->regs->ctl); + tmp |= UDC_BIT(UDC_EPCTL_S); + writel(tmp, &ep->regs->ctl); + } + else { + if (!list_empty (&ep->queue)) + { + /* next request */ + req = list_entry (ep->queue.next, + struct udc_request, queue); + + if (ep->dma) { + /* write desc pointer */ + writel(req->td_phys, &ep->regs->desptr); + /* set HOST READY */ + req->td_data->status + = UDC_ADDBITS(req->td_data->status, + UDC_DMA_STP_STS_BS_HOST_READY, + UDC_DMA_STP_STS_BS); + au_sync(); + + /* NAK if small packet until TDC interrupt */ + if (req->req.length < UDC_SMALL_PACKET) { + /* set NAK */ + tmp = readl(&ep->regs->ctl); + tmp |= UDC_BIT(UDC_EPCTL_SNAK); + writel(tmp, &ep->regs->ctl); + ep->naking = 1; + au_sync(); + } + /* set poll demand bit */ + tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->ctl); + tmp |= UDC_BIT(UDC_EPCTL_P); + writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl); + + /* all bytes will be transferred */ + req->req.actual = req->req.length; + + /* complete req */ + complete_req(ep, req, 0); + + } + else { + /* write fifo */ + udc_txfifo_write(ep, &(req->req)); + + /* lengh bytes transfered */ + len = req->req.length - req->req.actual; + if (len > ep->ep.maxpacket) + len = ep->ep.maxpacket; + + req->req.actual += len; + if (req->req.actual == req->req.length + || (len != ep->ep.maxpacket)) { + /* && (!req->req.zero || len != ep->ep.maxpacket)) { */ + /* complete req */ + complete_req(ep, req, 0); + } + } + + } + } + ep->halted = 0; + dev->stall_ep0in = 0; + if (!ep->dma) { + /* clear IN bit */ + writel(UDC_BIT(UDC_EPSTS_IN),&dev->ep[UDC_EP0IN_IX].regs->sts); + } + } + + return ret_val; +} + + +/** + * Interrupt handler for global device events + * + * \param dev pointer to UDC device object + * \param dev_irq device interrupt bit of DEVINT register + * \return 0 if success + */ +static inline int udc_dev_isr(struct udc* dev, u32 dev_irq) +{ + int ret_val = 0; + u32 tmp; + u32 cfg; + struct udc_ep *ep; + u16 i; + u8 udc_csr_epix; + + DBG( "Got interrupt. dev_irq is %8.8X\n", dev_irq ); + + /* SET_CONFIG irq ? */ + if (dev_irq & UDC_BIT(UDC_DEVINT_SC)) { + + /* read config value */ + tmp = readl(&dev->regs->sts); + cfg = UDC_GETBITS(tmp, UDC_DEVSTS_CFG); +#ifdef UDC_DEBUG + /* this is needed for debug only */ + if (cfg == dev->cur_config) { + same_cfg = 1; + } + else { + same_cfg = 0; + } + VDBG("same_cfg=%d\n", same_cfg); +#endif + DBG("SET_CONFIG interrupt: config=%d\n", cfg); + dev->cur_config = cfg; + dev->set_cfg_not_acked = 1; + + /* make usb request for gadget driver */ + memset(&setup_data, 0 , sizeof(union udc_setup_data)); + setup_data.request.bRequest = USB_REQ_SET_CONFIGURATION; + setup_data.request.wValue = dev->cur_config; + + /* programm the NE registers */ + /* TODO - put this to extra function or use udc_setup_endpoints() or udc_enable() */ + for (i = 0; i < UDC_EP_NUM; i++) { + ep = &dev->ep[i]; + if (ep->in) { + + /* ep ix in UDC CSR register space */ + udc_csr_epix = ep->num; + + + } /* OUT ep */ + else { + /* ep ix in UDC CSR register space */ + udc_csr_epix = ep->num - UDC_CSR_EP_OUT_IX_OFS; + } + + tmp = readl(&dev->csr->ne[udc_csr_epix]); + /* ep cfg */ + tmp = UDC_ADDBITS(tmp, ep->dev->cur_config, UDC_CSR_NE_CFG); + /* write reg */ + writel(tmp, &dev->csr->ne[udc_csr_epix]); + + /* clear stall bits */ + ep->halted = 0; + tmp = readl(&ep->regs->ctl); + tmp = tmp & UDC_CLEAR_BIT(UDC_EPCTL_S); + writel(tmp, &ep->regs->ctl); + } + /* call gadget zero with setup data received */ + spin_unlock (&dev->lock); + tmp = dev->driver->setup (&dev->gadget, &setup_data.request); + spin_lock (&dev->lock); + + } /* SET_INTERFACE ? */ + if (dev_irq & UDC_BIT(UDC_DEVINT_SI)) { + dev->set_cfg_not_acked = 1; + /* read interface and alt setting values */ + tmp = readl(&dev->regs->sts); + dev->cur_alt = UDC_GETBITS(tmp, UDC_DEVSTS_ALT); + dev->cur_intf = UDC_GETBITS(tmp, UDC_DEVSTS_INTF); + + /* make usb request for gadget driver */ + memset(&setup_data, 0 , sizeof(union udc_setup_data)); + setup_data.request.bRequest = USB_REQ_SET_INTERFACE; + setup_data.request.bRequestType = USB_RECIP_INTERFACE; + setup_data.request.wValue = dev->cur_alt; + setup_data.request.wIndex = dev->cur_intf; + + DBG("SET_INTERFACE interrupt: alt=%d intf=%d\n", dev->cur_alt, dev->cur_intf); + + /* programm the NE registers */ + /* TODO - put this to extra function or use udc_setup_endpoints() or udc_enable() */ + for (i = 0; i < UDC_EP_NUM; i++) { + ep = &dev->ep[i]; + if (ep->in) { + + /* ep ix in UDC CSR register space */ + udc_csr_epix = ep->num; + + + } /* OUT ep */ + else { + /* ep ix in UDC CSR register space */ + udc_csr_epix = ep->num - UDC_CSR_EP_OUT_IX_OFS; + } + + /***** UDC CSR reg ****************************/ + /* set ep values */ + tmp = readl(&dev->csr->ne[udc_csr_epix]); + /* ep interface */ + tmp = UDC_ADDBITS(tmp, ep->dev->cur_intf, UDC_CSR_NE_INTF); + /* tmp = UDC_ADDBITS(tmp, 2, UDC_CSR_NE_INTF); */ + /* ep alt */ + tmp = UDC_ADDBITS(tmp, ep->dev->cur_alt, UDC_CSR_NE_ALT); + /* tmp = UDC_ADDBITS(tmp, 1, UDC_CSR_NE_ALT); */ + /* write reg */ + writel(tmp, &dev->csr->ne[udc_csr_epix]); + + /* clear stall bits */ + ep->halted = 0; + tmp = readl(&ep->regs->ctl); + tmp = tmp & UDC_CLEAR_BIT(UDC_EPCTL_S); + writel(tmp, &ep->regs->ctl); + } + + /* call gadget zero with setup data received */ + spin_unlock (&dev->lock); + tmp = dev->driver->setup (&dev->gadget, &setup_data.request); + spin_lock (&dev->lock); + + } /* USB reset */ + if (dev_irq & UDC_BIT(UDC_DEVINT_UR)) { + DBG("USB Reset interrupt\n"); + + /* allow soft reset when suspend occurs */ + soft_reset_occured = 0; + + dev->waiting_zlp_ack_ep0in = 0; + dev->set_cfg_not_acked = 0; + + /* mask not needed interrupts */ + udc_mask_unused_interrupts(dev); + + /* call gadget to reset configs etc. */ + spin_unlock(&dev->lock); + dev->driver->disconnect(&dev->gadget); + spin_lock(&dev->lock); + + /* disable ep0 to empty req queue */ + empty_req_queue (&dev->ep [UDC_EP0IN_IX]); + ep_init(dev->regs, + &dev->ep [UDC_EP0IN_IX]); + + /* soft reset when rxfifo not empty */ + tmp = readl(&dev->regs->sts); + if (!(tmp & UDC_BIT(UDC_DEVSTS_RXFIFO_EMPTY)) && + !soft_reset_after_usbreset_occured) { + udc_soft_reset(dev); + soft_reset_after_usbreset_occured++; + } + + /* DMA reset to kill potential old DMA hw hang, */ + /* POLL bit is already reset by ep_init() through */ + /* disconnect() */ + UDC_DMARST(tmp,dev); + + /* put into initial config */ + udc_basic_init (dev); + + /* enable device setup interrupts */ + udc_enable_dev_setup_interrupts(dev); + + } /* USB suspend */ +#if 0 + if (dev_irq & UDC_BIT(UDC_DEVINT_US)) { + DBG("USB Suspend interrupt\n"); + + } /* new speed ? */ +#endif + if (dev_irq & UDC_BIT(UDC_DEVINT_ENUM)) { + DBG("ENUM interrupt\n"); +#ifdef UDC_DEBUG + num_enums++; + DBG("%d enumerations !\n", num_enums); +#endif + soft_reset_after_usbreset_occured = 0; + + /* disable ep0 to empty req queue */ + empty_req_queue (&dev->ep [UDC_EP0IN_IX]); + ep_init (dev->regs, + &dev->ep [UDC_EP0IN_IX]); + + /* link up all endpoints */ + udc_setup_endpoints (dev); + if (dev->gadget.speed == USB_SPEED_HIGH) { + INFO("Connect: Speed = HIGH_SPEED\n"); + } + else if (dev->gadget.speed == USB_SPEED_FULL) { + INFO("Connect: Speed = FULL_SPEED\n"); + } + + /* init ep 0 */ + activate_control_endpoints(dev); + + /* enable ep0 interrupts */ + udc_enable_ep0_interrupts(dev); + } + + return ret_val; +} + +/** + * Interrupt Service Routine, see Linux Kernel Doc for parameters + * + * \param irq irq number + * \param pdev pointer to device object + * \param ptregs don't used + */ +static irqreturn_t udc_irq (int irq, void *pdev ) +{ + struct udc *dev = pdev; + u32 reg; + u16 i; + u32 ep_irq; + //DBG( "In udc_irq\n" ); + void *debug_port = ioremap( 0x19c00000, 4 ); + iowrite8( 0x01, debug_port ); + + /* If UDC is suspended, then don't touch any register, otherwise + system hangs in endless retry => possibly hang !!! */ + if (dev->otg_driver && dev->otg_driver->query) { + if (dev->otg_driver->query(0) & OTG_FLAGS_UDC_SUSP) { + //DBG( "Device is suspended. Doing nothing.\n" ); + iowrite8( 0x04, debug_port ); + return IRQ_HANDLED; + } + } else { + //DBG( "Returning early for some reason...\n" ); + iowrite8( 0x08, debug_port ); + return IRQ_HANDLED; + } + + if (dev->sys_suspended) { + //DBG( "dev->sys_suspended is set\n" ); + iowrite8( 0x0C, debug_port ); + return IRQ_HANDLED; + } + + //DBG( "Trying to spin_lock...\n" ); + spin_lock (&dev->lock); + //DBG( "spin_lock acquired...\n" ); + iowrite8( 0x0F, debug_port ); + + + /* check for ep irq */ + reg = readl(&dev->regs->ep_irqsts); + //DBG( "ep_irqsts is %8.8X\n", reg ); + if (reg) + { + /* EP0 OUT */ + if (reg & UDC_BIT(UDC_EPINT_OUT_EP0)) + { + udc_control_out_isr(dev); + } /* EP0 IN */ + if (reg & UDC_BIT(UDC_EPINT_IN_EP0)) { + udc_control_in_isr(dev); + + } + + /* data endpoint */ + /* iterate ep's */ + for (i = 1; i < UDC_EP_NUM; i++) { + ep_irq = 1 << i; + /* irq for out ep ? */ + if ((reg & ep_irq) && i > UDC_EPIN_NUM) { + /* clear irq */ + writel(ep_irq, &dev->regs->ep_irqsts); + udc_data_out_isr(dev,i); + } /* irq for in ep ? */ + if ((reg & ep_irq) && i < UDC_EPIN_NUM && i > 0) { + /* clear irq */ + writel(ep_irq, &dev->regs->ep_irqsts); + udc_data_in_isr(dev,i); + } + + } + + } + iowrite8( 0x10, debug_port ); + + + /* check for dev irq */ + reg = readl(&dev->regs->irqsts); + if (reg) { + /* clear irq */ + writel(reg, &dev->regs->irqsts); + udc_dev_isr(dev, reg); + } + + + spin_unlock (&dev->lock); + iowrite8( 0xFF, debug_port ); + //DBG( "Done with udc_irq, returning IRQ_HANDLED\n" ); + return IRQ_HANDLED; +} + +/** + * Tears down device + * + * \param pdev pointer to device struct + */ +static void gadget_release (struct device *pdev) +{ + struct amd5536udc *dev = dev_get_drvdata(pdev); + kfree (dev); +} + +/** + * Cleanup on device remove + * + * \param dev pointer to udc struct + */ +static void udc_remove(struct udc* dev) +{ + { + u32 tmp; + /* disable UDC memory, DMA and clock */ + tmp = readl((u32*) (USB_MSR_BASE + USB_MSR_MCFG)); + tmp &= UDC_CLEAR_BIT(USBMSRMCFG_DMEMEN) + & UDC_CLEAR_BIT(USBMSRMCFG_DBMEN) + & UDC_CLEAR_BIT(USBMSRMCFG_UDCCLKEN); + au_writel(tmp, USB_MSR_BASE + USB_MSR_MCFG); + } + +#ifdef UDC_USE_TIMER + /* remove timer */ + stop_timer++; + if (timer_pending(&udc_timer)) + wait_for_completion(&on_exit); + if (udc_timer.data) + del_timer_sync(&udc_timer); + /* remove pollstall timer */ + stop_pollstall_timer++; + if (timer_pending(&udc_pollstall_timer)) + wait_for_completion(&on_pollstall_exit); + if (udc_pollstall_timer.data) + del_timer_sync(&udc_pollstall_timer); +#endif + device_unregister( &udc->gadget.dev ); + udc = 0; +} + +/** + * Reset all pci context + * + * \param pdev pointer to pci device struct + */ +static void udc_drv_remove (struct device *_dev) +{ + struct platform_device *pdev = to_platform_device(_dev); + struct udc *dev = dev_get_drvdata (_dev); + +#ifdef UDC_DEBUG + print_misc(dev); +#endif + /* gadget driver registered ? */ + if (dev->driver) { + WARN( "unregistering %s on driver remove\n", dev->driver->driver.name); + usb_gadget_unregister_driver (dev->driver); + } + /* otg driver registered ? */ + if (dev->otg_transceiver) { + /* should have been done already by driver model core */ + WARN( "uoc driver is still registered\n"); + } + /* dma pool cleanup */ + if (dev->data_requests) { + dma_pool_destroy (dev->data_requests); + } + if (dev->stp_requests) { + /* cleanup DMA desc's for ep0in */ + dma_pool_free (dev->stp_requests, + dev->ep [UDC_EP0OUT_IX].td_stp, + dev->ep [UDC_EP0OUT_IX].td_stp_dma); + dma_pool_free (dev->stp_requests, + dev->ep [UDC_EP0OUT_IX].td, + dev->ep [UDC_EP0OUT_IX].td_phys); + + dma_pool_destroy (dev->stp_requests); + } + + /* init controller by soft reset */ + writel(UDC_BIT(UDC_DEVCFG_SOFTRESET), &dev->regs->cfg); + + if (dev->irq_registered) + free_irq (pdev->resource[1].start, dev); + if (dev->regs) + iounmap (dev->regs); + if (dev->mem_region) + release_mem_region (pdev->resource[0].start, + pdev->resource[0].end + 1 + - pdev->resource[0].start); + + device_remove_file (&pdev->dev, &dev_attr_registers); + dev_set_drvdata (_dev, 0); + udc_remove(dev); +} + +/** + * create dma pools on init + * + * \param dev pointer to udc device struct + * \return 0 if success + */ +__init static int init_dma_pools(struct udc* dev) +{ + struct udc_stp_dma *td_stp; + struct udc_data_dma *td_data; + int retval; + + /* consistent DMA mode setting ? */ + if (use_dma_ppb) { + use_dma_bufferfill_mode = 0; + } + else { + use_dma_ppb_du = 0; + use_dma_bufferfill_mode = 1; + } + + /* DMA setup */ + dev->data_requests = dma_pool_create ("data_requests", NULL, + sizeof (struct udc_data_dma), + UDC_PCIPOOL_ALIGN, + UDC_PCIPOOL_CROSS); + if (!dev->data_requests) { + DBG( "can't get request data pool\n"); + retval = -ENOMEM; + goto finished; + } + + /* EP0 in dma regs = dev control regs */ + dev->ep[UDC_EP0IN_IX].dma = &dev->regs->ctl; + + /* dma desc for setup data */ + dev->stp_requests = dma_pool_create ("setup requests", NULL, + sizeof (struct udc_stp_dma), + UDC_PCIPOOL_ALIGN, + UDC_PCIPOOL_CROSS); + if (!dev->stp_requests) { + DBG( "can't get stp request pool\n"); + retval = -ENOMEM; + goto finished; + } + /* setup */ + td_stp = dma_pool_alloc (dev->stp_requests, UDC_PCIPOOL_GFP_STP, + &dev->ep [UDC_EP0OUT_IX].td_stp_dma); + if (td_stp == NULL){ + retval = -ENOMEM; + goto finished; + } + dev->ep [UDC_EP0OUT_IX].td_stp = td_stp; + /* data: 0 packets !? */ + td_data = dma_pool_alloc (dev->stp_requests, UDC_PCIPOOL_GFP_STP, + &dev->ep [UDC_EP0OUT_IX].td_phys); + if (td_data == NULL){ + retval = -ENOMEM; + goto finished; + } + dev->ep [UDC_EP0OUT_IX].td = td_data; + /* point to itself */ + dev->ep [UDC_EP0OUT_IX].td->next = dev->ep [UDC_EP0OUT_IX].td_phys; + return 0; + +finished: + return retval; +} + +/** + * Called by kernel init device context + * + * \param dev pointer to device struct + * \return 0 if success + */ +static int udc_drv_probe (struct device* _dev) +{ + char tmp[8]; + struct udc *dev; + struct platform_device *pdev = to_platform_device(_dev); + u32 resource; + u32 len; + u32 irq; + int retval = 0; + u32 reg; + + /* basic init */ + reg = readl((u32*) (USB_MSR_BASE + USB_MSR_MCFG)); + if (reg == 0) { + /* default value */ + reg = USBMSRMCFG_DEFAULT; + au_writel( reg, USB_MSR_BASE + USB_MSR_MCFG ); + au_readl( USB_MSR_BASE + USB_MSR_MCFG ); + udelay(1000); + } + /* enable UDC memory, DMA, clock, cacheable memory, + * read combining and prefetch enable */ + reg |= UDC_BIT(USBMSRMCFG_DMEMEN) | UDC_BIT(USBMSRMCFG_DBMEN) + | UDC_BIT(USBMSRMCFG_UDCCLKEN) + | UDC_BIT(USBMSRMCFG_PHYPLLEN) +#ifdef CONFIG_DMA_COHERENT + | UDC_BIT(USBMSRMCFG_UCAM) +#endif + | UDC_BIT(USBMSRMCFG_RDCOMB) + | UDC_BIT(USBMSRMCFG_PFEN); + au_writel( reg, USB_MSR_BASE + USB_MSR_MCFG ); + + /* one udc only */ + if (udc) { + WARN("already probed: %04x/%04x\n", UDC_PCI_VENID, UDC_PCI_DEVID); + return -EBUSY; + } + + /* init */ + dev = kmalloc (sizeof (struct udc), GFP_KERNEL ); + if (!dev) { + retval = -ENOMEM; + goto finished; + } + memset (dev, 0, sizeof(struct udc)); + + dev->pdev = _dev; + + /* check platform resources */ + if (pdev->resource[0].flags != IORESOURCE_MEM) { + ERR ("resource[0] must be IORESOURCE_MEM\n"); + retval = -ENOMEM; + goto finished; + } + resource = pdev->resource[0].start; + len = pdev->resource[0].end + 1 - pdev->resource[0].start; + if (pdev->resource[1].flags != IORESOURCE_IRQ) { + ERR ("resource[1] must be IORESOURCE_IRQ\n"); + retval = -ENOMEM; + goto finished; + } + irq = pdev->resource[1].start; + + /* platform device resource allocation */ + /* mem */ + if (!request_mem_region (resource, len, name)) { + ERR ("controller already in use\n"); + retval = -EBUSY; + goto finished; + } + dev->mem_region = 1; + + dev->virt_addr = ioremap_nocache(resource, len); + if (dev->virt_addr == NULL) { + DBG( "start address cannot be mapped\n"); + retval = -EFAULT; + goto finished; + } + + /* irq */ + if (!irq) { + ERR( "irq not set\n"); + retval = -ENODEV; + goto finished; + } + snprintf (tmp, sizeof tmp, "%d", irq); + if (request_irq (irq, udc_irq, IRQF_SHARED, name, dev) != 0) { + ERR( "error on request_irq() with %s\n", tmp); + retval = -EBUSY; + goto finished; + } + dev->irq_registered = 1; + + dev_set_drvdata (_dev, dev); + + /* chip revision */ + dev->chiprev = 0; + + /* chip rev for Au1200 */ + dev->chiprev = (u16) read_c0_prid() & 0xff; + + /* init dma pools */ + if (use_dma) { + retval = init_dma_pools(dev); + if (retval != 0) + goto finished; + } + + dev->phys_addr = resource; + dev->irq = irq; + dev->pdev = _dev; + dev->gadget.dev.parent = _dev; + dev->gadget.dev.dma_mask = _dev->dma_mask; + /* general probing */ + if (udc_probe(dev) != 0) + goto finished; + return retval; + +finished: + if (dev) + udc_drv_remove (_dev); + return retval; +} + +/** + * general probe + * + * \param dev pointer to udc device struct + * \return 0 if success + */ +__init int udc_probe(struct udc* dev) +{ + char tmp[128]; + u32 reg; + int retval; + + /* mark timer as not initialized */ + //udc_timer.data = 0; + //udc_pollstall_timer.data = 0; + + /* device struct setup */ + spin_lock_init(&dev->lock); + spin_lock_init(&udc_irq_spinlock); + spin_lock_init(&udc_stall_spinlock); + dev->gadget.ops = &udc_ops; + + strcpy(dev->gadget.dev.bus_id, "gadget"); + dev->gadget.dev.release = gadget_release; + dev->gadget.name = name; + dev->gadget.is_dualspeed = 1; + + /* udc csr registers base */ + dev->csr = (struct udc_csrs*) (dev->virt_addr + UDC_CSR_ADDR); + /* dev registers base */ + dev->regs = (struct udc_regs *) (dev->virt_addr + UDC_DEVCFG_ADDR); + /* ep registers base */ + dev->ep_regs = (struct udc_ep_regs *) (dev->virt_addr + UDC_EPREGS_ADDR); + /* fifo's base */ + dev->rxfifo = (u32*) (dev->virt_addr + UDC_RXFIFO_ADDR); + dev->txfifo = (u32*) (dev->virt_addr + UDC_TXFIFO_ADDR); + + /* init registers, interrupts, ... */ + { + u32 tmp; + + /* TODO put this to extra function, + * this all is extracted from usb_init() and + * udc_basic_init() but without register access */ + dev->gadget.ep0 = &dev->ep [UDC_EP0IN_IX].ep; + dev->ep [UDC_EP0IN_IX].halted = 0; + INIT_LIST_HEAD (&dev->gadget.ep0->ep_list); + dev->gadget.speed = USB_SPEED_HIGH; + make_ep_lists(dev); + /* basic endpoint init */ + for (tmp = 0; tmp < UDC_EP_NUM; tmp++) { + struct udc_ep *ep = &dev->ep[tmp]; + + ep->ep.name = ep_string[tmp]; + ep->dev = dev; + ep->num = tmp; + /* txfifo size is calculated at enable time */ + ep->txfifo = dev->txfifo; + + /* fifo size */ + if (tmp < UDC_EPIN_NUM) { + ep->fifo_depth = UDC_TXFIFO_SIZE; + ep->in = 1; + } + else { + ep->fifo_depth = UDC_RXFIFO_SIZE; + ep->in = 0; + + } + + ep->regs = &dev->ep_regs [tmp]; + if (!ep->desc) { + ep->desc = 0; + INIT_LIST_HEAD (&ep->queue); + + ep->ep.maxpacket = ~0; + ep->ep.ops = &udc_ep_ops; + } + if (use_dma) { + /* ep->dma is not really used, just to indicate that */ + /* DMA is active */ + /* dma regs = dev control regs */ + ep->dma = (u32*) &dev->regs->ctl; + } + } + dev->ep [UDC_EP0IN_IX].ep.maxpacket = UDC_EP0IN_MAX_PKT_SIZE; + dev->ep [UDC_EP0OUT_IX].ep.maxpacket = UDC_EP0OUT_MAX_PKT_SIZE; + } + + + INFO( "%s\n", mod_desc); + + snprintf (tmp, sizeof tmp, "%d", dev->irq); + INFO( "irq %s, mem %08lx, chip rev %02x (Au1200 %s)\n", + tmp, dev->phys_addr, dev->chiprev, (dev->chiprev == 0) ? "AB" : "AC"); +#ifdef CONFIG_DMA_COHERENT + /* coherent DMA not possible with AB silicon */ + if (dev->chiprev == UDC_AUAB_REV) { + ERR("Your chip revision is %s, it must be at least %s to use coherent DMA. \nPlease change DMA_COHERENT to DMA_NONCOHERENT in arch/mips/Kconfig and re-compile .\n", + "AB", "AC"); + retval = -ENODEV; + goto finished; + } +#endif + +#ifdef UDC_AUA1 + if (dev->chiprev < UDC_AUA1) { + ERR("Your chip revision is %s, it must be at least %s\n", + "AB", "AC"); + retval = -ENODEV; + goto finished; + } +#endif + +#ifdef CONFIG_DMA_COHERENT + INFO("Compiled for coherent memory.\n"); +#endif +#ifdef CONFIG_DMA_NONCOHERENT + INFO("Compiled for non-coherent memory.\n"); +#endif + udc = dev; + + retval = device_register (&dev->gadget.dev); + if ( retval ) { + ERR( "Failed to register gadget device\n" ); + goto finished; + } + device_create_file (&pdev->dev, &dev_attr_registers); + +#ifdef UDC_USE_TIMER + /* timer init */ + init_timer(&udc_timer); + udc_timer.function = udc_timer_function; + udc_timer.data = 1; + /* timer pollstall init */ + init_timer(&udc_pollstall_timer); + udc_pollstall_timer.function = udc_pollstall_timer_function; + udc_pollstall_timer.data = 1; +#endif + + /* set SD */ + reg = readl(&dev->regs->ctl); + reg |= UDC_BIT(UDC_DEVCTL_SD); + writel(reg, &dev->regs->ctl); + + /* print dev register info */ + print_regs(dev); + + return 0; + +finished: + return retval; +} + + +/** + * Initiates a remote wakeup + * + * \return 0 if success + */ +/* initiate remote wakeup */ +static int udc_remote_wakeup(struct udc* dev) +{ + u32 tmp; + + INFO("UDC initiates remote wakeup\n"); + + tmp = readl(&dev->regs->ctl); + tmp |= UDC_BIT(UDC_DEVCTL_RES); + writel(tmp, &dev->regs->ctl); + tmp &= UDC_CLEAR_BIT(UDC_DEVCTL_RES); + writel(tmp, &dev->regs->ctl); + + return 0; +} + +/** + * Suspends UDC + * + * \return 0 if success + */ +static int udc_suspend(struct udc* dev) +{ + int retval = 0; + + u32 tmp; + INFO("UDC suspend\n"); + /* mask interrupts */ + udc_mask_unused_interrupts(dev); + + if (dev->driver && dev->driver->disconnect) { + /* call gadget to reset context */ + if (spin_is_locked(&dev->lock)) { + spin_unlock(&dev->lock); + dev->driver->disconnect (&dev->gadget); + spin_lock(&dev->lock); + } + else + dev->driver->disconnect (&dev->gadget); + + /* disable ep0 to empty req queue */ + empty_req_queue (&dev->ep [UDC_EP0IN_IX]); + ep_init (dev->regs, + &dev->ep [UDC_EP0IN_IX]); + + /* init controller by soft reset */ + udc_soft_reset(dev); + + } + if (dev->otg_driver && dev->otg_transceiver + && dev->otg_transceiver->set_peripheral) { + /* if UDC is supended by Host or already disconnected then + don't force disconnect by unbind() */ + if (dev->otg_driver->query) { + if (!(dev->otg_driver->query(0) & OTG_FLAGS_UDC_SUSP)) { + /* unbind from otg driver -> host disconnect */ + dev->otg_transceiver->set_peripheral(dev->otg_transceiver, NULL); + dev->connected = 0; + } + } + else + { + /* unbind from otg driver -> host disconnect */ + dev->otg_transceiver->set_peripheral (dev->otg_transceiver, NULL); + dev->connected = 0; + } + } + + dev->sys_suspended = 1; + + /* switch off UDC clock */ + tmp = au_readl( USB_MSR_BASE + USB_MSR_MCFG ); + tmp &= UDC_CLEAR_BIT(USBMSRMCFG_UDCCLKEN); + au_writel( tmp, USB_MSR_BASE + USB_MSR_MCFG ); + + return retval; +} + +/** + * Resumes UDC + * + * \return 0 if success + */ +static int udc_resume(struct udc* dev) +{ + int retval = 0; + + u32 tmp; + INFO("UDC resume\n"); + /* switch on UDC clock */ + tmp = au_readl( USB_MSR_BASE + USB_MSR_MCFG ); + tmp |= UDC_BIT(USBMSRMCFG_UDCCLKEN); + au_writel(tmp, USB_MSR_BASE + USB_MSR_MCFG); + + dev->sys_suspended = 0; + + usb_connect(dev); + if (dev->otg_transceiver && dev->otg_transceiver->set_peripheral) { + /* bind to otg driver */ + dev->otg_transceiver->set_peripheral(dev->otg_transceiver, &dev->gadget); + } + return retval; +} + +static int udc_au1xxx_drv_probe(struct device *dev) +{ + int retval; + + DBG("udc_au1xxx_drv_probe()\n"); + retval = udc_drv_probe(dev); + return retval; +} + +static int udc_au1xxx_drv_remove(struct device *dev) +{ + DBG("udc_au1xxx_drv_remove()\n"); + udc_drv_remove(dev); + return 0; +} + +static int udc_au1xxx_drv_suspend(struct device *dev, pm_message_t state) +{ + struct udc *udc_dev = dev_get_drvdata(dev); + return udc_suspend(udc_dev); +} + +static int udc_au1xxx_drv_resume(struct device *dev) +{ + struct udc *udc_dev = dev_get_drvdata(dev); + return udc_resume(udc_dev); +} + +static struct device_driver udc_au1xxx_driver = { + .name = "au1xxx-udc", + .bus = &platform_bus_type, + .probe = udc_au1xxx_drv_probe, + .remove = udc_au1xxx_drv_remove, + .suspend = udc_au1xxx_drv_suspend, + .resume = udc_au1xxx_drv_resume, +}; + + +/** + * Inits driver + * + * \return 0 if success + */ +static int __init init(void) +{ + int rc; + + /* probe by device system */ + rc = driver_register(&udc_au1xxx_driver); + + return rc; +} +module_init (init); + +/** + * Cleans driver + */ +static void __exit cleanup(void) +{ + /* unregister at device system */ + driver_unregister(&udc_au1xxx_driver); + +} +module_exit (cleanup); + diff --git a/drivers/usb/gadget/au1200_udc.h b/drivers/usb/gadget/au1200_udc.h new file mode 100644 index 0000000..a1f8649 --- /dev/null +++ b/drivers/usb/gadget/au1200_udc.h @@ -0,0 +1,869 @@ +/* + * Header for driver for RMI Au1200 UDC high/full speed USB device controller + */ +/* + * Copyright (C) 2008 RMI Corporation (http://www.rmicorp.com) + * Author: Kevin Hickey (khickey@rmicorp.com) + * + * Adapted from the AMD5536 UDC module. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef AU1200UDC_H +#define AU1200UDC_H + +/***************************************************************************** +* Constants +*****************************************************************************/ + +/* Driver constants -------------------------------------------------------*/ +#define DRIVER_NAME_FOR_PRINT "au1200_udc" + +/* PCI constants -----------------------------------------------------------*/ +// TODO: Change to the correct Vendor and Device IDs +#define UDC_PCI_VENID 0x1022 +#define UDC_PCI_DEVID 0x2096 +#define UDC_PCI_CLASS ((PCI_CLASS_SERIAL_USB << 8) | 0xfe) +#define UDC_PCI_CLASS_MASK 0xffffffff + +/* Platform specific -------------------------------------------------------*/ +#define UDC_PCIPOOL_ALIGN 32 +#define UDC_PCIPOOL_CROSS 4096 +#define UDC_PCIPOOL_GFP_STP (GFP_ATOMIC | GFP_DMA) + +/* temp define for AU1200, will live in au1000.h normally */ +// TODO: Are these defined elsewhere? Can they be in au1000.h? +#ifndef USB_UDC_BASE +#define USB_UDC_BASE 0x14022000 +#define USB_UDC_LEN 0x2000 +#define USB_MSR_BASE 0xB4020000 +#define USB_MSR_MCFG 4 +#define USBMSRMCFG_DMEMEN 4 +#define USBMSRMCFG_DBMEN 5 +#define USBMSRMCFG_UDCCLKEN 18 +#define USBMSRMCFG_PHYPLLEN 19 +#define USBMSRMCFG_RDCOMB 30 +#define USBMSRMCFG_PFEN 31 +#define AU1200_USB_INT 29 +#endif +#ifndef USBMSRMCFG_UCAM +#define USBMSRMCFG_UCAM 7 +#endif +#define USBMSRMCFG_DEFAULT 0x00d02000 + +/* other constants */ +#define UDC_RDE_TIMER_SECONDS 1 +#define UDC_RDE_TIMER_DIV 10 +#define UDC_POLLSTALL_TIMER_USECONDS 500 + +/* Special optimization for certain gadgets ------------------------------- */ +#define UDC_SMALL_PACKET 9 + +/* Au1200 rev. */ +#define UDC_AUAB_REV 0 +#define UDC_AUAC_REV 1 +#define UDC_AUA0 0 + +/* SETUP usb commands +* needed, because some SETUP's are handled in hw, but must be passed to +* gadget driver above -----------------------------------------------------*/ +/* SET_CONFIG */ +#define UDC_SETCONFIG_DWORD0 0x00000900 +#define UDC_SETCONFIG_DWORD0_VALUE_MASK 0xffff0000 +#define UDC_SETCONFIG_DWORD0_VALUE_OFS 16 + +#define UDC_SETCONFIG_DWORD1 0x00000000 + +/* SET_INTERFACE */ +#define UDC_SETINTF_DWORD0 0x00000b00 +#define UDC_SETINTF_DWORD0_ALT_MASK 0xffff0000 +#define UDC_SETINTF_DWORD0_ALT_OFS 16 + +#define UDC_SETINTF_DWORD1 0x00000000 +#define UDC_SETINTF_DWORD1_INTF_MASK 0x0000ffff +#define UDC_SETINTF_DWORD1_INTF_OFS 0 + +/* Mass storage reset */ +#define UDC_MSCRES_DWORD0 0x0000ff21 +#define UDC_MSCRES_DWORD1 0x00000000 + +/* Global CSR's -------------------------------------------------------------*/ +/* UDC CSR's */ +#define UDC_CSR_ADDR 0x500 + +/* EP NE bits */ +/* EP number */ +#define UDC_CSR_NE_NUM_MASK 0x0000000f +#define UDC_CSR_NE_NUM_OFS 0 +/* EP direction */ +#define UDC_CSR_NE_DIR_MASK 0x00000010 +#define UDC_CSR_NE_DIR_OFS 4 +/* EP type */ +#define UDC_CSR_NE_TYPE_MASK 0x00000060 +#define UDC_CSR_NE_TYPE_OFS 5 +/* EP config number */ +#define UDC_CSR_NE_CFG_MASK 0x00000780 +#define UDC_CSR_NE_CFG_OFS 7 +/* EP interface number */ +#define UDC_CSR_NE_INTF_MASK 0x00007800 +#define UDC_CSR_NE_INTF_OFS 11 +/* EP alt setting */ +#define UDC_CSR_NE_ALT_MASK 0x00078000 +#define UDC_CSR_NE_ALT_OFS 15 + +/* max pkt */ +#define UDC_CSR_NE_MAX_PKT_MASK 0x3ff80000 +#define UDC_CSR_NE_MAX_PKT_OFS 19 + +/* Device Config Register ---------------------------------------------------*/ +#define UDC_DEVCFG_ADDR 0x400 + +#define UDC_DEVCFG_SOFTRESET 31 +#define UDC_DEVCFG_HNPSFEN 30 +#define UDC_DEVCFG_DMARST 29 +#define UDC_DEVCFG_SET_DESC 18 +#define UDC_DEVCFG_CSR_PRG 17 +#define UDC_DEVCFG_STATUS 7 +#define UDC_DEVCFG_DIR 6 +#define UDC_DEVCFG_PI 5 +#define UDC_DEVCFG_SS 4 +#define UDC_DEVCFG_SP 3 +#define UDC_DEVCFG_RWKP 2 + +#define UDC_DEVCFG_SPD_MASK 0x3 +#define UDC_DEVCFG_SPD_OFS 0 +#define UDC_DEVCFG_SPD_HS 0x0 +#define UDC_DEVCFG_SPD_FS 0x1 +#define UDC_DEVCFG_SPD_LS 0x2 +/*#define UDC_DEVCFG_SPD_FS 0x3*/ + + +/* Device Control Register --------------------------------------------------*/ +#define UDC_DEVCTL_ADDR 0x404 + +#define UDC_DEVCTL_THLEN_MASK 0xff000000 +#define UDC_DEVCTL_THLEN_OFS 24 + +#define UDC_DEVCTL_BRLEN_MASK 0x00ff0000 +#define UDC_DEVCTL_BRLEN_OFS 16 + +#define UDC_DEVCTL_CSR_DONE 13 +#define UDC_DEVCTL_DEVNAK 12 +#define UDC_DEVCTL_SD 10 +#define UDC_DEVCTL_MODE 9 +#define UDC_DEVCTL_BREN 8 +#define UDC_DEVCTL_THE 7 +#define UDC_DEVCTL_BF 6 +#define UDC_DEVCTL_BE 5 +#define UDC_DEVCTL_DU 4 +#define UDC_DEVCTL_TDE 3 +#define UDC_DEVCTL_RDE 2 +#define UDC_DEVCTL_RES 0 + + +/* Device Status Register ---------------------------------------------------*/ +#define UDC_DEVSTS_ADDR 0x408 + +#define UDC_DEVSTS_TS_MASK 0xfffc0000 +#define UDC_DEVSTS_TS_OFS 18 + +#define UDC_DEVSTS_SESSVLD 17 +#define UDC_DEVSTS_PHY_ERROR 16 +#define UDC_DEVSTS_RXFIFO_EMPTY 15 + +#define UDC_DEVSTS_ENUM_SPEED_MASK 0x00006000 +#define UDC_DEVSTS_ENUM_SPEED_OFS 13 +#define UDC_DEVSTS_ENUM_SPEED_FULL 1 +#define UDC_DEVSTS_ENUM_SPEED_HIGH 0 + +#define UDC_DEVSTS_SUSP 12 + +#define UDC_DEVSTS_ALT_MASK 0x00000f00 +#define UDC_DEVSTS_ALT_OFS 8 + +#define UDC_DEVSTS_INTF_MASK 0x000000f0 +#define UDC_DEVSTS_INTF_OFS 4 + +#define UDC_DEVSTS_CFG_MASK 0x0000000f +#define UDC_DEVSTS_CFG_OFS 0 + + +/* Device Interrupt Register ------------------------------------------------*/ +#define UDC_DEVINT_ADDR 0x40c + +#define UDC_DEVINT_ENUM 6 +#define UDC_DEVINT_SOF 5 +#define UDC_DEVINT_US 4 +#define UDC_DEVINT_UR 3 +#define UDC_DEVINT_ES 2 +#define UDC_DEVINT_SI 1 +#define UDC_DEVINT_SC 0 + +/* Device Interrupt Mask Register -------------------------------------------*/ +#define UDC_DEVINT_MSK_ADDR 0x410 + +#define UDC_DEVINT_MSK 0x3f + +/* Endpoint Interrupt Register ----------------------------------------------*/ +#define UDC_EPINT_ADDR 0x414 + +#define UDC_EPINT_OUT_MASK 0xffff0000 +#define UDC_EPINT_OUT_OFS 16 +#define UDC_EPINT_IN_MASK 0x0000ffff +#define UDC_EPINT_IN_OFS 0 + +#define UDC_EPINT_IN_EP0 0 +#define UDC_EPINT_IN_EP1 1 +#define UDC_EPINT_IN_EP2 2 +#define UDC_EPINT_IN_EP3 3 +#define UDC_EPINT_OUT_EP0 16 +#define UDC_EPINT_OUT_EP1 17 +#define UDC_EPINT_OUT_EP2 18 +#define UDC_EPINT_OUT_EP3 19 + +#define UDC_EPINT_EP0_ENABLE_MSK 0x001e001e + +/* Endpoint Interrupt Mask Register -----------------------------------------*/ +#define UDC_EPINT_MSK_ADDR 0x418 + +#define UDC_EPINT_OUT_MSK_MASK 0xffff0000 +#define UDC_EPINT_OUT_MSK_OFS 16 +#define UDC_EPINT_IN_MSK_MASK 0x0000ffff +#define UDC_EPINT_IN_MSK_OFS 0 + +#define UDC_EPINT_MSK_DISABLE_ALL (UDC_EPINT_OUT_MASK | UDC_EPINT_IN_MASK) +/* mask non-EP0 endpoints */ +#define UDC_EPDATAINT_MSK_DISABLE 0xfffefffe +/* mask all dev interrupts */ +#define UDC_DEV_MSK_DISABLE 0x7f + +/* Endpoint-specific CSR's --------------------------------------------------*/ +/* Endpoint Control Registers -----------------------------------------------*/ +#define UDC_EPREGS_ADDR 0x0 +#define UDC_EPIN_REGS_ADDR 0x0 +#define UDC_EPOUT_REGS_ADDR 0x200 + +#define UDC_EPCTL_ADDR 0x0 + +#define UDC_EPCTL_RRDY 9 +#define UDC_EPCTL_CNAK 8 +#define UDC_EPCTL_SNAK 7 +#define UDC_EPCTL_NAK 6 + +#define UDC_EPCTL_ET_MASK 0x00000030 +#define UDC_EPCTL_ET_OFS 4 +#define UDC_EPCTL_ET_CONTROL 0 +#define UDC_EPCTL_ET_ISO 1 +#define UDC_EPCTL_ET_BULK 2 +#define UDC_EPCTL_ET_INTERRUPT 3 + +#define UDC_EPCTL_P 3 +#define UDC_EPCTL_SN 2 +#define UDC_EPCTL_F 1 +#define UDC_EPCTL_S 0 + +/* Endpoint Status Registers ------------------------------------------------*/ +#define UDC_EPSTS_ADDR 0x4 + +#define UDC_EPSTS_RX_PKT_SIZE_MASK 0x007ff800 +#define UDC_EPSTS_RX_PKT_SIZE_OFS 11 + +#define UDC_EPSTS_TDC 10 +#define UDC_EPSTS_HE 9 +#define UDC_EPSTS_BNA 7 +#define UDC_EPSTS_IN 6 + +#define UDC_EPSTS_OUT_MASK 0x00000030 +#define UDC_EPSTS_OUT_OFS 4 +#define UDC_EPSTS_OUT_DATA 1 +#define UDC_EPSTS_OUT_DATA_CLEAR 0x10 +#define UDC_EPSTS_OUT_SETUP 2 +#define UDC_EPSTS_OUT_SETUP_CLEAR 0x20 +#define UDC_EPSTS_OUT_CLEAR 0x30 + +/* Endpoint Buffer Size IN/ Receive Packet Frame Number OUT Registers ------*/ +#define UDC_EPIN_BUFF_SIZE_ADDR 0x8 +#define UDC_EPOUT_FRAME_NUMBER_ADDR 0x8 + +#define UDC_EPIN_BUFF_SIZE_MASK 0x0000ffff +#define UDC_EPIN_BUFF_SIZE_OFS 0 +/* EP0in txfifo = 128 bytes*/ +#define UDC_EPIN0_BUFF_SIZE 32 +/* EP0in fullspeed txfifo = 128 bytes*/ +#define UDC_FS_EPIN0_BUFF_SIZE 32 + +/* fifo size mult = fifo size / max packet */ +#define UDC_EPIN_BUFF_SIZE_MULT 2 + +/* EPin data fifo size = 1024 bytes DOUBLE BUFFERING */ +#define UDC_EPIN_BUFF_SIZE 256 +/* EPin small INT data fifo size = 128 bytes */ +#define UDC_EPIN_SMALLINT_BUFF_SIZE 32 + +/* EPin fullspeed data fifo size = 128 bytes DOUBLE BUFFERING */ +#define UDC_FS_EPIN_BUFF_SIZE 32 + +#define UDC_EPOUT_FRAME_NUMBER_MASK 0x0000ffff +#define UDC_EPOUT_FRAME_NUMBER_OFS 0 + +/* Endpoint Buffer Size OUT/Max Packet Size Registers -----------------------*/ +#define UDC_EPOUT_BUFF_SIZE_ADDR 0x0c +#define UDC_EP_MAX_PKT_SIZE_ADDR 0x0c + +#define UDC_EPOUT_BUFF_SIZE_MASK 0xffff0000 +#define UDC_EPOUT_BUFF_SIZE_OFS 16 +#define UDC_EP_MAX_PKT_SIZE_MASK 0x0000ffff +#define UDC_EP_MAX_PKT_SIZE_OFS 0 +/* EP0in max packet size = 64 bytes */ +#define UDC_EP0IN_MAX_PKT_SIZE 64 +/* EP0out max packet size = 64 bytes */ +#define UDC_EP0OUT_MAX_PKT_SIZE 64 +/* EP0in fullspeed max packet size = 64 bytes */ +#define UDC_FS_EP0IN_MAX_PKT_SIZE 64 +/* EP0out fullspeed max packet size = 64 bytes */ +#define UDC_FS_EP0OUT_MAX_PKT_SIZE 64 + +/* Endpoint dma descriptors ------------------------------------------------*/ +/* Setup data */ +/* Status dword */ +#define UDC_DMA_STP_STS_CFG_MASK 0x0fff0000 +#define UDC_DMA_STP_STS_CFG_OFS 16 +#define UDC_DMA_STP_STS_CFG_ALT_MASK 0x000f0000 +#define UDC_DMA_STP_STS_CFG_ALT_OFS 16 +#define UDC_DMA_STP_STS_CFG_INTF_MASK 0x00f00000 +#define UDC_DMA_STP_STS_CFG_INTF_OFS 20 +#define UDC_DMA_STP_STS_CFG_NUM_MASK 0x0f000000 +#define UDC_DMA_STP_STS_CFG_NUM_OFS 24 +#define UDC_DMA_STP_STS_RX_MASK 0x30000000 +#define UDC_DMA_STP_STS_RX_OFS 28 +#define UDC_DMA_STP_STS_BS_MASK 0xc0000000 +#define UDC_DMA_STP_STS_BS_OFS 30 +#define UDC_DMA_STP_STS_BS_HOST_READY 0 +#define UDC_DMA_STP_STS_BS_DMA_BUSY 1 +#define UDC_DMA_STP_STS_BS_DMA_DONE 2 +#define UDC_DMA_STP_STS_BS_HOST_BUSY 3 +/* IN data */ +/* Status dword */ +#define UDC_DMA_IN_STS_TXBYTES_MASK 0x0000ffff +#define UDC_DMA_IN_STS_TXBYTES_OFS 0 +#define UDC_DMA_IN_STS_FRAMENUM_MASK 0x07ff0000 +#define UDC_DMA_IN_STS_FRAMENUM_OFS 0 +#define UDC_DMA_IN_STS_L 27 +#define UDC_DMA_IN_STS_TX_MASK 0x30000000 +#define UDC_DMA_IN_STS_TX_OFS 28 +#define UDC_DMA_IN_STS_BS_MASK 0xc0000000 +#define UDC_DMA_IN_STS_BS_OFS 30 +#define UDC_DMA_IN_STS_BS_HOST_READY 0 +#define UDC_DMA_IN_STS_BS_DMA_BUSY 1 +#define UDC_DMA_IN_STS_BS_DMA_DONE 2 +#define UDC_DMA_IN_STS_BS_HOST_BUSY 3 +/* OUT data */ +/* Status dword */ +#define UDC_DMA_OUT_STS_RXBYTES_MASK 0x0000ffff +#define UDC_DMA_OUT_STS_RXBYTES_OFS 0 +#define UDC_DMA_OUT_STS_FRAMENUM_MASK 0x07ff0000 +#define UDC_DMA_OUT_STS_FRAMENUM_OFS 0 +#define UDC_DMA_OUT_STS_L 27 +#define UDC_DMA_OUT_STS_RX_MASK 0x30000000 +#define UDC_DMA_OUT_STS_RX_OFS 28 +#define UDC_DMA_OUT_STS_BS_MASK 0xc0000000 +#define UDC_DMA_OUT_STS_BS_OFS 30 +#define UDC_DMA_OUT_STS_BS_HOST_READY 0 +#define UDC_DMA_OUT_STS_BS_DMA_BUSY 1 +#define UDC_DMA_OUT_STS_BS_DMA_DONE 2 +#define UDC_DMA_OUT_STS_BS_HOST_BUSY 3 +/* other constants */ +/* max ep0in packet */ +#define UDC_EP0IN_MAXPACKET 1000 +/* max dma packet */ +#define UDC_DMA_MAXPACKET 65536 +/* DMA buffer len for temp request, should be the same as the upper +layer gadget is using */ +#define UDC_DMA_TEMP_BUFFER_LEN 4096 +/* un-usable DMA address */ +#define DMA_DONT_USE (~(dma_addr_t) 0 ) + +/* other Endpoint register addresses and values-----------------------------*/ +#define UDC_EP_SUBPTR_ADDR 0x10 +#define UDC_EP_DESPTR_ADDR 0x14 +#define UDC_EP_WRITE_CONFIRM_ADDR 0x1c + +/* EP number as layouted in AHB space */ +#define UDC_EP_NUM 32 +#define UDC_EPIN_NUM 16 +#define UDC_EPIN_NUM_USED 5 +#define UDC_EPOUT_NUM 16 +/* EP number of EP's really used = EP0 + 8 data EP's */ +#define UDC_USED_EP_NUM 9 +/* UDC CSR regs are aligned but AHB regs not - offset for OUT EP's */ +#define UDC_CSR_EP_OUT_IX_OFS 12 + +#define UDC_EP0OUT_IX 16 +#define UDC_EP0IN_IX 0 + +/* max packet */ +#define UDC_HS_BULK_MAXPKT 512 + +/* Rx fifo address and size = 1k -------------------------------------------*/ +#define UDC_RXFIFO_ADDR 0x800 +#define UDC_RXFIFO_SIZE 0x400 + +/* Tx fifo address and size = 1.5k -----------------------------------------*/ +#define UDC_TXFIFO_ADDR 0xc00 +#define UDC_TXFIFO_SIZE 0x600 + +/* default data endpoints --------------------------------------------------*/ +#define UDC_EPIN_STATUS_IX 1 +#define UDC_EPIN_IX 2 +#define UDC_EPOUT_IX 18 + +/* general constants -------------------------------------------------------*/ +#define UDC_DWORD_BYTES 4 +#define UDC_BITS_PER_BYTE_SHIFT 3 +#define UDC_BYTE_MASK 0xff +#define UDC_BITS_PER_BYTE 8 + +/* char device constants ---------------------------------------------------*/ +/* names */ +#ifdef UDC_DEBUG +#ifdef UDC_DRIVER_NAME +#define UDC_DEVICE_NAME UDC_DRIVER_NAME +#else +#define UDC_DEVICE_NAME "amd5536udc" +#endif +#define UDC_DEVICE_FILE_NAME "amd5536udc_dev" +#define UDC_DEVICE_FILE_INODE "/dev/amd5536udc_dev" +/* major number */ +#define UDC_MAJOR_NUM 240 +#endif + +#ifdef __KERNEL__ +/* kernel wrappers */ +#define device_create_file(x,y) do {} while (0) +#define device_remove_file device_create_file + +#ifndef WARN_ON +#define WARN_ON(a) do {} while (0) +#endif + +#ifndef BUG_ON +#define BUG_ON(cond)do {if (unlikely((cond) != 0)) BUG();} while(0) +#endif + +#ifndef likely +#define likely(a) (a) +#define unlikely(a) (a) +#endif + +#ifndef container_of +#define container_of list_entry +#endif + +#ifndef IRQ_NONE +typedef void irqreturn_t; +#define IRQ_HANDLED +#define IRQ_NONE +#define IRQ_RETVAL(a) +#endif +#endif + +/* MIPS specific -----------------------------------------------------------*/ + +/***************************************************************************** +* Includes +*****************************************************************************/ +#include "au1200_otg.h" + +/***************************************************************************** +* Types +*****************************************************************************/ + +/* UDC CSR's */ +struct udc_csrs { + + /* sca - setup command address */ + u32 sca; + + /* ep ne's */ + u32 ne[UDC_USED_EP_NUM]; +} __attribute__ ((packed)); + +/* AHB subsystem CSR registers */ +struct udc_regs { + + /* device configuration */ + u32 cfg; + + /* device control */ + u32 ctl; + + /* device status */ + u32 sts; + + /* device interrupt */ + u32 irqsts; + + /* device interrupt mask */ + u32 irqmsk; + + /* endpoint interrupt */ + u32 ep_irqsts; + + /* endpoint interrupt mask */ + u32 ep_irqmsk; +} __attribute__ ((packed)); + +/* endpoint specific registers */ +struct udc_ep_regs { + + /* endpoint control */ + u32 ctl; + + /* endpoint status */ + u32 sts; + + /* endpoint buffer size in/ receive packet frame number out */ + u32 bufin_framenum; + + /* endpoint buffer size out/max packet size */ + u32 bufout_maxpkt; + + /* endpoint setup buffer pointer */ + u32 subptr; + + /* endpoint data descriptor pointer */ + u32 desptr; + + /* reserverd */ + u32 reserved; + + /* write/read confirmation */ + u32 confirm; + +} __attribute__ ((packed)); + +#ifdef __KERNEL__ +/* control data DMA desc */ +struct udc_stp_dma { + /* status quadlet */ + u32 status; + /* reserved */ + u32 _reserved; + /* first setup word */ + u32 data12; + /* second setup word */ + u32 data34; +} __attribute__ ((aligned (16))); + +/* normal data DMA desc */ +struct udc_data_dma { + /* status quadlet */ + u32 status; + /* reserved */ + u32 _reserved; + /* buffer pointer */ + u32 bufptr; + /* next descriptor pointer */ + u32 next; +} __attribute__ ((aligned (16))); + +/* request packet */ +struct udc_request { + /* embedded gadget ep */ + struct usb_request req; + + /* flags */ + unsigned dma_going : 1, + dma_mapping : 1, + dma_done : 1; + /* phys. address */ + dma_addr_t td_phys; + /* first dma desc. of chain */ + struct udc_data_dma *td_data; + /* last dma desc. of chain */ + struct udc_data_dma *td_data_last; + /* next pointer of broken chain */ + dma_addr_t td_data_last_next; + + struct list_head queue; + + /* chain length */ + unsigned chain_len; + +}; + +/* UDC specific endpoint parameters */ +struct udc_ep { + struct usb_ep ep; + struct udc_ep_regs *regs; + u32 *txfifo; + u32* dma; + dma_addr_t td_phys; + dma_addr_t td_stp_dma; + struct udc_stp_dma *td_stp; + struct udc_data_dma *td; + /* temp request */ + struct udc_request *req; + unsigned req_used; + unsigned req_completed; + /* dummy DMA desc for BNA dummy */ + struct udc_request *bna_dummy_req; + unsigned bna_occurred; + + /* NAK state */ + unsigned naking; + + struct udc *dev; + + /* queue for requests */ + struct list_head queue; + const struct usb_endpoint_descriptor *desc; + unsigned halted; + unsigned num : 5, + fifo_depth : 14, + in : 1; +}; + +/* device struct */ +struct udc { + struct usb_gadget gadget; + spinlock_t lock; + /* all endpoints */ + struct udc_ep ep[UDC_EP_NUM]; + struct usb_gadget_driver *driver; + struct otg_transceiver *otg_transceiver; + struct usb_otg_gadget_extension *otg_driver; + /* operational flags */ + unsigned active : 1, + stall_ep0in : 1, + waiting_zlp_ack_ep0in : 1, + set_cfg_not_acked : 1, + irq_registered : 1, + otg_supported : 1, + data_ep_enabled : 1, + data_ep_queued : 1, + mem_region : 1, + selfpowered : 1, + sys_suspended : 1, + connected; + + u16 chiprev; + + /* registers */ + struct device *pdev; + struct udc_csrs *csr; + struct udc_regs *regs; + struct udc_ep_regs *ep_regs; + u32* rxfifo; + u32* txfifo; + + /* DMA desc pools */ + struct dma_pool *data_requests; + struct dma_pool *stp_requests; + + /* device data */ + unsigned long phys_addr; + void* virt_addr; + unsigned irq; + + /* states */ + u16 cur_config; + u16 cur_intf; + u16 cur_alt; +}; + +/* setup request data */ +union udc_setup_data { + u32 data[2]; + struct usb_ctrlrequest request; +}; +#endif /*__KERNEL__*/ + +/***************************************************************************** +* Macros +*****************************************************************************/ + +/*************************************** +* SET and GET bitfields in u32 values +* via constants for mask/offset: +* is the text between +* UDC_ and _MASK|_OFS of appropiate +* constant +****************************************/ +/* set bitfield value in u32 u32Val */ +#define UDC_ADDBITS(u32Val, bitfield_val, bitfield_stub_name)\ + (((u32Val) & (((u32) ~((u32) bitfield_stub_name##_MASK))))\ + |(((bitfield_val) << ((u32) bitfield_stub_name##_OFS))\ + & ((u32) bitfield_stub_name##_MASK))) + +/* set bitfield value in zero-initialized u32 u32Val */ +/* => bitfield bits in u32Val are all zero */ +#define UDC_INIT_SETBITS(u32Val, bitfield_val, bitfield_stub_name)\ + ((u32Val)\ + |(((bitfield_val) << ((u32) bitfield_stub_name##_OFS))\ + &((u32) bitfield_stub_name##_MASK))) + +/* get bitfield value from u32 u32Val */ +#define UDC_GETBITS(u32Val, bitfield_stub_name)\ + ((u32Val & ((u32) bitfield_stub_name##_MASK))\ + >> ((u32) bitfield_stub_name##_OFS)) + +/* SET and GET bits in u32 values ------------------------------------------*/ +#define UDC_BIT(bit_stub_name) (1 << bit_stub_name) +#define UDC_UNMASK_BIT(bit_stub_name) (~UDC_BIT(bit_stub_name)) +#define UDC_CLEAR_BIT(bit_stub_name) (~UDC_BIT(bit_stub_name)) + +/* misc --------------------------------------------------------------------*/ +#define DIR_STRING(bAddress) (((bAddress) & USB_DIR_IN) ? "in" : "out") + +/* UDC specific macros -----------------------------------------------------*/ +#ifdef UDC_DMARST_AVAIL +#define UDC_DMARST(tmp, dev) \ + DBG("DMA machine reset\n"); \ + tmp = readl(&dev->regs->cfg); \ + writel(tmp | UDC_BIT(UDC_DEVCFG_DMARST), &dev->regs->cfg); \ + writel(tmp, &dev->regs->cfg); +#else +#define UDC_DMARST(tmp, dev) {} +#endif + +/* print macros ------------------------------------------------------------*/ + +#ifdef UDC_VERBOSE +#ifndef UDC_DEBUG +#define UDC_DEBUG +#endif +#endif + +/** + * \brief + * Macro for printing information in drivers + * + * This macro is used for printing kernel messages in driver source code. + * It should be used for printing useful information about states and called + * functions for normal operation (not for errors and warnings). + * + * \param fmt is format string for printk + * \param args... are arguments given to printk (number depends on ) + * \return code from printk + */ +#define INFO(args...) \ + printk(KERN_INFO DRIVER_NAME_FOR_PRINT ": " args) + +/** + * \brief + * Macro for printing warnings in drivers + * + * This macro is used for printing kernel messages in driver source code. + * It should be used for printing warnings. + * + * \param fmt is format string for printk + * \param args... are arguments given to printk (number depends on ) + * \return code from printk + */ +#ifdef WARN +#undef WARN +#endif +#define WARN(args...) \ + printk(KERN_WARNING DRIVER_NAME_FOR_PRINT " warning: " args) + +/** + * \brief + * Macro for printing errors in drivers + * + * This macro is used for printing kernel messages in driver source code. + * It should be used for printing errors. + * + * \param fmt is format string for printk + * \param args... are arguments given to printk (number depends on ) + * \return code from printk + */ +#define ERR(args...) \ + printk(KERN_ERR DRIVER_NAME_FOR_PRINT " error: " args) + +/** + * \brief + * Macro for printing debug messages in drivers + * + * This macro is used for printing kernel messages in driver source code + * when UDC_DEBUG is defined + * It should be used for printing debug messages. + * + * \param fmt is format string for printk + * \param args... are arguments given to printk (number depends on ) + * \return code from printk + */ +//#ifdef UDC_DEBUG +#define DBG(args...) \ + printk(KERN_DEBUG DRIVER_NAME_FOR_PRINT " debug: " args) +//#else + +/* +#define DBG(args...) \ + do {} while (0) +#endif +*/ + +/** + * \brief + * Macro for printing verbose debug messages in drivers + * + * This macro is used for printing kernel messages in driver source code + * when UDC_DEBUG and UDC_VERBOSE is defined + * It should be used for printing debug messages. + * + * \param fmt is format string for printk + * \param args... are arguments given to printk (number depends on ) + * \return code from printk + */ +#ifdef UDC_VERBOSE +#define VDBG DBG +#else +#define VDBG(args...) \ + do {} while (0) +#endif + +/***************************************************************************** +* Data +*****************************************************************************/ +#ifdef __cplusplus +extern "C" +{ +#endif + + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +/***************************************************************************** +* Functions +*****************************************************************************/ +#ifdef __cplusplus +extern "C" +{ +#endif + + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +/***************************************************************************** +* Inline Functions +*****************************************************************************/ + +#endif /* #ifdef AU1200UDC_H */ diff --git a/drivers/usb/gadget/au1200_uoc.h b/drivers/usb/gadget/au1200_uoc.h new file mode 100644 index 0000000..f5bafe8 --- /dev/null +++ b/drivers/usb/gadget/au1200_uoc.h @@ -0,0 +1,1265 @@ +/* + * AMD 5536 USB OTG controller driver + */ + +/* + * Copyright (C) 2005 AMD (http://www.amd.com) + * Author: Karsten Boge + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ +#ifndef AU1200_UOC_H +#define AU1200_UOC_H + + +/***************************************************************************** +* Config options +*****************************************************************************/ + +#ifndef OTG_HSA0_HNP_WA +#define OTG_HSA0_HNP_WA +#endif + +#ifdef VERBOSE +#ifndef DEBUG +#define DEBUG +#endif +#endif + + +/***************************************************************************** +* Constants +*****************************************************************************/ + +#define OTG_DRIVER_NAME "au1200_otg" + +#define OTG_CHIPREV 0 + +#define OTG_FLAGS_ACTIV (1<<19) /* full OTG functionality is activ */ + +#define GPIO_2_BASE 200 +#define GPIO_215 215 +#define SYS_PINFUNC_P0A_GPIO (2<<17) +#ifdef CONFIG_MIPS_PB1200 +#define USB_VBUS_GPIO 3 /* AU1000_GPIO_3 */ +#endif +#ifdef CONFIG_MIPS_DB1200 +#define USB_VBUS_GPIO GPIO_215 +#endif +#if !(defined(CONFIG_MIPS_PB1200) || defined(CONFIG_MIPS_DB1200)) +#error "!!! UNKNOWN AU1200 BOARD !!!" +#endif + + +/********************************** +* CS5536UOC Register definitions +**********************************/ + +/* capabilities */ +#define OTG_CAP_APU (1<<15) /* automatic pull-up enable */ + +/* multiplexer */ +#define OTG_MUX_DISABLE_ALL 0 /* not assigned */ +#define OTG_MUX_ENABLE_UHC (2<<0) /* assigned to host */ +#define OTG_MUX_ENABLE_UDC (3<<0) /* assigned to device */ +#define OTG_MUX_PUEN (1<<2) /* pull-up enable */ +#define OTG_MUX_VBUSVLD (1<<8) /* VBus valid */ + +/* status */ +#define OTG_STS_ID (1<<0) /* ID pin status */ +#define OTG_STS_VBUSVLD (1<<1) /* VBus valid */ +#define OTG_STS_SESSVLD (1<<2) /* Session valid */ +#define OTG_STS_SESSEND (1<<3) /* Session end */ +#define OTG_STS_LST (3<<4) /* Line state */ +#define OTG_STS_LST_J (1<<4) /* Line state */ +#define OTG_STS_LST_K (2<<4) /* Line state */ +#define OTG_STS_PSPD (3<<6) /* Port speed */ +#define OTG_STS_PSPD_LS (1<<7) /* Port speed */ +#define OTG_STS_PSPD_FS (2<<7) /* Port speed */ +#define OTG_STS_FSOE (1<<8) /* FS output enable (OHC) */ +#define OTG_STS_PCON (1<<9) /* Port connected */ +#define OTG_STS_PSUS (1<<10) /* Port suspended */ +#define OTG_STS_TMH (1<<11) /* Timer halted */ +#define OTG_STS_HNP_EN (1<<12) /* HNP enabled for B-dev */ +#define OTG_STS_HNP_SUPP (1<<13) /* A-host supports HNP */ +#define OTG_STS_HNP_ALTSUPP (1<<14) /* A-host supports alt. HNP */ +#define OTG_STS_HNPSTS (OTG_STS_HNP_EN | OTG_STS_HNP_SUPP | \ + OTG_STS_HNP_ALTSUPP) +#define OTG_STS_OC (1<<15) /* over-current */ +#define OTG_STS_DPR (1<<16) /* Downstream port reset */ + +/* control */ +#define OTG_CTL_DISABLE_ALL 0 /* not assigned */ +#define OTG_CTL_ENABLE_UHC (2<<0) /* assigned to host */ +#define OTG_CTL_ENABLE_UDC (3<<0) /* assigned to device */ +#define OTG_CTL_MUX_MASK (3<<0) /* port mux mask */ +#define OTG_CTL_PPWR (1<<2) /* port power switch */ +#define OTG_CTL_PPO (1<<3) /* port power override */ +#define OTG_CTL_CHRG (1<<4) /* charge VBus */ +#define OTG_CTL_DISCHRG (1<<5) /* discharge VBus */ +#define OTG_CTL_IDSNSEN (1<<6) /* ID sense enable, ID-PU */ +#define OTG_CTL_PADEN (1<<7) +#define OTG_CTL_PUEN (1<<8) /* pull-up enable */ +#define OTG_CTL_DMPDEN (1<<9) /* pull-down enable */ +#define OTG_CTL_HNPSFEN (1<<10) /* HNP SET_FEATURE enable */ +#define OTG_CTL_WPCS_DEAS (2<<16) /* deassert port connect */ +#define OTG_CTL_WPCS_ASRT (3<<16) /* assert port connect */ +#define OTG_CTL_WPSS_DEAS (2<<18) /* deassert port suspend */ +#define OTG_CTL_WPSS_ASRT (3<<18) /* assert port suspend */ +/* timer conditions */ +#define OTG_CTL_TMR_RLP (1<<28) /* timer reload policy */ +#define OTG_CTL_TMR_ALL (0xf<<24) /* stop timer */ +#define OTG_CTL_TMR_STOP 0 /* timer disabled */ +#define OTG_CTL_TMR_UNCOND (1<<24) /* count unconditionally */ +#define OTG_CTL_TMR_SE0 (2<<24) /* count if LSt = FS-SE0 */ +#define OTG_CTL_TMR_FSJ (3<<24) /* count if LSt = FS-J */ +#define OTG_CTL_TMR_FSK (4<<24) /* count if LSt = FS-K */ +#define OTG_CTL_TMR_NOSE0 (5<<24) /* count if LSt <> FS-SE0 */ +#define OTG_CTL_TMR_NORX (6<<24) /* count if Rx inactiv */ +#define OTG_CTL_TMR_ID (7<<24) /* count if ID = 0 */ + +/* interrupts */ +#define OTG_INT_GLOBAL (1<<31) /* global interrupt enable */ +#define OTG_INT_ENALL 0x7fff /* enable all */ +#define OTG_INT_DISALL 0 /* disable all */ +#define OTG_INT_IDC (1<<0) /* ID pin change */ +#define OTG_INT_VBVC (1<<1) /* VBUS valid change */ +#define OTG_INT_SVC (1<<2) /* Session valid change */ +#define OTG_INT_SEC (1<<3) /* Session end change */ +#define OTG_INT_LSTC (1<<4) /* Line state change */ +#define OTG_INT_PSPDC (1<<5) /* Port speed change */ +#define OTG_INT_FSOEC (1<<6) /* FS/LS OE change */ +#define OTG_INT_HSDD (1<<7) /* HS disconnect detected */ +#define OTG_INT_RXACT (1<<8) /* Rx activity detected */ +#define OTG_INT_PCC (1<<9) /* Port connect change */ +#define OTG_INT_PSC (1<<10) /* Port suspend change */ +#define OTG_INT_TMX (1<<11) /* Timer expired */ +#define OTG_INT_HNPFC (1<<12) /* HNP feature change */ +#define OTG_INT_OCD (1<<13) /* over current detected */ +#define OTG_INT_DPRC (1<<14) /* Downstream port reset change */ + +/*** HS-A0 WA: BUG-3885: VB_SESS_VLD value too high ***/ +/*** HS-A0 WA: BUG-3950: gadget SV notification ***/ +#define OTG_INT_ADDS OTG_INT_SVC + +/********************************** +* OTG state dependend data +**********************************/ + +/* + * generic + */ +#define OTG_CTL_DEFAULT (OTG_CTL_PADEN | \ + OTG_CTL_IDSNSEN) +#define OTG_CTL_HOST_DEFAULT (OTG_CTL_DEFAULT | \ + OTG_CTL_ENABLE_UHC) +#ifdef CONFIG_USB_OTG +#define OTG_CTL_PERIPHERAL_DEFAULT (OTG_CTL_DEFAULT | \ + OTG_CTL_HNPSFEN | \ + OTG_CTL_ENABLE_UDC | \ + OTG_CTL_PPO | OTG_CTL_PUEN) +#else +#define OTG_CTL_PERIPHERAL_DEFAULT (OTG_CTL_DEFAULT | \ + OTG_CTL_ENABLE_UDC | \ + OTG_CTL_PPO | OTG_CTL_PUEN) +#endif + +#define OTG_INT_DEFAULT OTG_INT_IDC + +/* + * OTG_STATE_UNDEFINED + */ +#define OTG_STATE_UNDEFINED_CONTROL (OTG_CTL_DEFAULT | OTG_CTL_PPO | \ + OTG_CTL_TMR_UNCOND) +#define OTG_STATE_UNDEFINED_STATUS 0 +#define OTG_STATE_UNDEFINED_STATUS_MASK 0 +#define OTG_STATE_UNDEFINED_INTERRUPTS OTG_INT_TMX + +/* + * OTG_STATE_NO_B_DEVICE_A + */ +#define OTG_STATE_NO_B_DEVICE_A_CONTROL OTG_CTL_HOST_DEFAULT +#define OTG_STATE_NO_B_DEVICE_A_STATUS 0 +#define OTG_STATE_NO_B_DEVICE_A_STATUS_MASK 0 +#define OTG_STATE_NO_B_DEVICE_A_INTERRUPTS OTG_INT_DEFAULT + +/* + * OTG_STATE_NO_B_DEVICE_B + */ +#define OTG_STATE_NO_B_DEVICE_B_CONTROL (OTG_CTL_DEFAULT | OTG_CTL_PPO) +#define OTG_STATE_NO_B_DEVICE_B_STATUS 0 +#define OTG_STATE_NO_B_DEVICE_B_STATUS_MASK 0 +#define OTG_STATE_NO_B_DEVICE_B_INTERRUPTS OTG_INT_DEFAULT + +/* + * OTG_STATE_A_IDLE + */ +#define OTG_STATE_A_IDLE_CONTROL (OTG_CTL_DEFAULT | OTG_CTL_PPO) +#define OTG_STATE_A_IDLE_STATUS 0 +#define OTG_STATE_A_IDLE_STATUS_MASK 0 +#define OTG_STATE_A_IDLE_INTERRUPTS (OTG_INT_DEFAULT | OTG_INT_SVC | \ + OTG_INT_LSTC) + +/* + * OTG_STATE_A_IDLE_WAIT_DP + */ +#define OTG_STATE_A_IDLE_WAIT_DP_CONTROL (OTG_STATE_A_IDLE_CONTROL | \ + OTG_CTL_TMR_UNCOND) +#define OTG_STATE_A_IDLE_WAIT_DP_STATUS 0 +#define OTG_STATE_A_IDLE_WAIT_DP_STATUS_MASK 0 +#define OTG_STATE_A_IDLE_WAIT_DP_INTERRUPTS (OTG_STATE_A_IDLE_INTERRUPTS | \ + OTG_INT_TMX) + +/* + * OTG_STATE_A_IDLE_WAIT_VP + */ +#define OTG_STATE_A_IDLE_WAIT_VP_CONTROL (OTG_STATE_A_IDLE_CONTROL | \ + OTG_CTL_TMR_UNCOND) +#define OTG_STATE_A_IDLE_WAIT_VP_STATUS 0 +#define OTG_STATE_A_IDLE_WAIT_VP_STATUS_MASK 0 +#define OTG_STATE_A_IDLE_WAIT_VP_INTERRUPTS (OTG_STATE_A_IDLE_INTERRUPTS | \ + OTG_INT_TMX) + +/* + * OTG_STATE_A_IDLE_WAIT_MP + */ +#define OTG_STATE_A_IDLE_WAIT_MP_CONTROL (OTG_STATE_A_IDLE_CONTROL | \ + OTG_CTL_TMR_UNCOND) +#define OTG_STATE_A_IDLE_WAIT_MP_STATUS 0 +#define OTG_STATE_A_IDLE_WAIT_MP_STATUS_MASK 0 +#define OTG_STATE_A_IDLE_WAIT_MP_INTERRUPTS (OTG_STATE_A_IDLE_INTERRUPTS | \ + OTG_INT_TMX) + +/* + * OTG_STATE_A_IDLE_WAIT_DV + */ +#define OTG_STATE_A_IDLE_WAIT_DV_CONTROL (OTG_STATE_A_IDLE_CONTROL | \ + OTG_CTL_TMR_UNCOND) +#define OTG_STATE_A_IDLE_WAIT_DV_STATUS 0 +#define OTG_STATE_A_IDLE_WAIT_DV_STATUS_MASK 0 +#define OTG_STATE_A_IDLE_WAIT_DV_INTERRUPTS (OTG_STATE_A_IDLE_INTERRUPTS | \ + OTG_INT_TMX) + +/* + * OTG_STATE_A_WAIT_VRISE + */ +#define OTG_STATE_A_WAIT_VRISE_CONTROL (OTG_CTL_HOST_DEFAULT | \ + OTG_CTL_TMR_UNCOND) +#define OTG_STATE_A_WAIT_VRISE_STATUS 0 +#define OTG_STATE_A_WAIT_VRISE_STATUS_MASK 0 +#define OTG_STATE_A_WAIT_VRISE_INTERRUPTS (OTG_INT_DEFAULT | OTG_INT_TMX | \ + OTG_INT_VBVC) + +/* + * OTG_STATE_A_WAIT_BCON + */ +#define OTG_STATE_A_WAIT_BCON_CONTROL OTG_CTL_HOST_DEFAULT +#define OTG_STATE_A_WAIT_BCON_STATUS 0 +#define OTG_STATE_A_WAIT_BCON_STATUS_MASK 0 +#define OTG_STATE_A_WAIT_BCON_INTERRUPTS (OTG_INT_DEFAULT | OTG_INT_TMX | \ + OTG_INT_VBVC | OTG_INT_PCC) + +/* + * OTG_STATE_A_WAIT_BCON_VB + */ +#define OTG_STATE_A_WAIT_BCON_VB_CONTROL (OTG_STATE_A_WAIT_BCON_CONTROL | \ + OTG_CTL_TMR_UNCOND) +#define OTG_STATE_A_WAIT_BCON_VB_STATUS 0 +#define OTG_STATE_A_WAIT_BCON_VB_STATUS_MASK 0 +#define OTG_STATE_A_WAIT_BCON_VB_INTERRUPTS OTG_STATE_A_WAIT_BCON_INTERRUPTS + +/* + * OTG_STATE_A_HOST + */ +#define OTG_STATE_A_HOST_CONTROL OTG_CTL_HOST_DEFAULT +#define OTG_STATE_A_HOST_STATUS 0 +#define OTG_STATE_A_HOST_STATUS_MASK 0 +#ifdef CONFIG_USB_OTG +#ifndef VERBOSE +#define OTG_STATE_A_HOST_INTERRUPTS (OTG_INT_DEFAULT | \ + OTG_INT_VBVC | OTG_INT_DPRC | \ + OTG_INT_PCC | OTG_INT_PSC) +#else +#define OTG_STATE_A_HOST_INTERRUPTS (OTG_INT_DEFAULT | \ + OTG_INT_VBVC | OTG_INT_DPRC | \ + OTG_INT_PCC | OTG_INT_PSC | \ + OTG_INT_PSPDC) + /* OTG_INT_LSTC */ +#endif +#else + /* IDPIN mode only */ +#define OTG_STATE_A_HOST_INTERRUPTS OTG_INT_IDC +#endif + +/* + * OTG_STATE_A_SUSPEND + */ +#define OTG_STATE_A_SUSPEND_CONTROL (OTG_CTL_HOST_DEFAULT | \ + OTG_CTL_TMR_UNCOND) +#define OTG_STATE_A_SUSPEND_STATUS 0 +#define OTG_STATE_A_SUSPEND_STATUS_MASK 0 +#define OTG_STATE_A_SUSPEND_INTERRUPTS (OTG_INT_DEFAULT | OTG_INT_TMX | \ + OTG_INT_VBVC | OTG_INT_DPRC | \ + OTG_INT_PCC | OTG_INT_PSC) + +/* + * OTG_STATE_A_PERIPHERAL + */ +#define OTG_STATE_A_PERIPHERAL_CONTROL (OTG_CTL_PERIPHERAL_DEFAULT | \ + OTG_CTL_PPWR | OTG_CTL_DMPDEN) +#define OTG_STATE_A_PERIPHERAL_STATUS 0 +#define OTG_STATE_A_PERIPHERAL_STATUS_MASK 0 +#ifndef VERBOSE +#define OTG_STATE_A_PERIPHERAL_INTERRUPTS (OTG_INT_DEFAULT | \ + OTG_INT_VBVC | OTG_INT_OCD | \ + OTG_INT_PCC | OTG_INT_PSC) +#else +#define OTG_STATE_A_PERIPHERAL_INTERRUPTS (OTG_INT_DEFAULT | \ + OTG_INT_VBVC | OTG_INT_OCD | \ + OTG_INT_PCC | OTG_INT_PSC | \ + OTG_INT_PSPDC) + /* OTG_INT_LSTC */ +#endif + +/* + * OTG_STATE_A_VBUS_ERR + */ +#define OTG_STATE_A_VBUS_ERR_CONTROL (OTG_CTL_HOST_DEFAULT | \ + OTG_CTL_PPO | OTG_CTL_DISCHRG) +#define OTG_STATE_A_VBUS_ERR_STATUS 0 +#define OTG_STATE_A_VBUS_ERR_STATUS_MASK 0 +#define OTG_STATE_A_VBUS_ERR_INTERRUPTS OTG_INT_DEFAULT + +/* + * OTG_STATE_A_WAIT_VFALL + */ +#define OTG_STATE_A_WAIT_VFALL_CONTROL (OTG_CTL_HOST_DEFAULT | \ + OTG_CTL_PPO) +#define OTG_STATE_A_WAIT_VFALL_STATUS 0 +#define OTG_STATE_A_WAIT_VFALL_STATUS_MASK 0 +#define OTG_STATE_A_WAIT_VFALL_INTERRUPTS (OTG_INT_DEFAULT | OTG_INT_SEC) + +/* + * OTG_STATE_A_WAIT_VFALL_DN + */ +#define OTG_STATE_A_WAIT_VFALL_DN_CONTROL (OTG_STATE_A_WAIT_VFALL_CONTROL | \ + OTG_CTL_DISCHRG) +#define OTG_STATE_A_WAIT_VFALL_DN_STATUS 0 +#define OTG_STATE_A_WAIT_VFALL_DN_STATUS_MASK 0 +#define OTG_STATE_A_WAIT_VFALL_DN_INTERRUPTS OTG_STATE_A_WAIT_VFALL_INTERRUPTS + +/* + * OTG_STATE_A_WAIT_BDISCON + */ +#define OTG_STATE_A_WAIT_BDISCON_CONTROL (OTG_CTL_DEFAULT | \ + OTG_CTL_PPO | OTG_CTL_PPWR | \ + OTG_CTL_TMR_UNCOND) +#define OTG_STATE_A_WAIT_BDISCON_STATUS 0 +#define OTG_STATE_A_WAIT_BDISCON_STATUS_MASK 0 +#define OTG_STATE_A_WAIT_BDISCON_INTERRUPTS (OTG_INT_DEFAULT | OTG_INT_TMX | \ + OTG_INT_VBVC | OTG_INT_OCD | \ + OTG_INT_PSPDC | OTG_INT_LSTC) + +/* + * OTG_STATE_B_IDLE + */ +/*** HS-A0 WA: BUG-3885: VB_SESS_VLD value too high ***/ +/*** HS-A0 WA: BUG-3943: gadget suspend issue ***/ +#define OTG_STATE_B_IDLE_CONTROL (OTG_CTL_PERIPHERAL_DEFAULT & \ + ~((u32) (OTG_CTL_PUEN | \ + OTG_CTL_ENABLE_UDC))) +#define OTG_STATE_B_IDLE_STATUS 0 +#define OTG_STATE_B_IDLE_STATUS_MASK 0 +#ifdef CONFIG_USB_OTG +#define OTG_STATE_B_IDLE_INTERRUPTS (OTG_INT_DEFAULT | OTG_INT_SVC) +#else +#ifdef CONFIG_USB_OTGMUX_IDPIN + /* IDPIN mode */ +#define OTG_STATE_B_IDLE_INTERRUPTS (OTG_INT_IDC | OTG_INT_SVC) +#else + /* gadget mode */ +#define OTG_STATE_B_IDLE_INTERRUPTS OTG_INT_SVC +#endif +#endif + +/* + * OTG_STATE_B_PERIPHERAL + */ +#define OTG_STATE_B_PERIPHERAL_CONTROL (OTG_CTL_PERIPHERAL_DEFAULT | \ + OTG_CTL_DMPDEN) +#define OTG_STATE_B_PERIPHERAL_STATUS 0 +#define OTG_STATE_B_PERIPHERAL_STATUS_MASK 0 +#ifdef CONFIG_USB_OTG +#ifndef VERBOSE +#define OTG_STATE_B_PERIPHERAL_INTERRUPTS (OTG_INT_DEFAULT | OTG_INT_SVC | \ + OTG_INT_PCC | OTG_INT_PSC | \ + OTG_INT_HNPFC) +#else +#define OTG_STATE_B_PERIPHERAL_INTERRUPTS (OTG_INT_DEFAULT | OTG_INT_SVC | \ + OTG_INT_PCC | OTG_INT_PSC | \ + OTG_INT_HNPFC | OTG_INT_PSPDC) + /* OTG_INT_LSTC */ +#endif +#else +#ifdef CONFIG_USB_OTGMUX_IDPIN + /* IDPIN mode */ +#define OTG_STATE_B_PERIPHERAL_INTERRUPTS (OTG_INT_IDC | OTG_INT_SVC) +#else + /* gadget mode */ +#define OTG_STATE_B_PERIPHERAL_INTERRUPTS OTG_INT_SVC +#endif +#endif + +/* + * OTG_STATE_B_PERIPHERAL_WT + */ +#define OTG_STATE_B_PERIPHERAL_WT_CONTROL (OTG_STATE_B_PERIPHERAL_CONTROL | \ + OTG_CTL_PPO | OTG_CTL_TMR_UNCOND) +#define OTG_STATE_B_PERIPHERAL_WT_STATUS 0 +#define OTG_STATE_B_PERIPHERAL_WT_STATUS_MASK 0 +#define OTG_STATE_B_PERIPHERAL_WT_INTERRUPTS (OTG_STATE_B_PERIPHERAL_INTERRUPTS \ + | OTG_INT_TMX) + +/* + * OTG_STATE_B_PERIPHERAL_DC + */ +#define OTG_STATE_B_PERIPHERAL_DC_CONTROL (OTG_CTL_HOST_DEFAULT | \ + OTG_CTL_PPO | OTG_CTL_DMPDEN | \ + OTG_CTL_TMR_UNCOND) +#define OTG_STATE_B_PERIPHERAL_DC_STATUS 0 +#define OTG_STATE_B_PERIPHERAL_DC_STATUS_MASK 0 +#define OTG_STATE_B_PERIPHERAL_DC_INTERRUPTS (OTG_STATE_B_PERIPHERAL_INTERRUPTS \ + | OTG_INT_TMX | OTG_INT_LSTC) + +/* + * OTG_STATE_B_WAIT_ACON + */ +#define OTG_STATE_B_WAIT_ACON_CONTROL (OTG_CTL_HOST_DEFAULT | \ + OTG_CTL_PPO | OTG_CTL_TMR_UNCOND) +#define OTG_STATE_B_WAIT_ACON_STATUS 0 +#define OTG_STATE_B_WAIT_ACON_STATUS_MASK 0 +#define OTG_STATE_B_WAIT_ACON_INTERRUPTS (OTG_INT_DEFAULT | OTG_INT_SVC | \ + OTG_INT_PCC | OTG_INT_PSC | \ + OTG_INT_HNPFC | OTG_INT_TMX) + +/* + * OTG_STATE_B_HOST + */ +#define OTG_STATE_B_HOST_CONTROL (OTG_CTL_HOST_DEFAULT | \ + OTG_CTL_PPO) +#define OTG_STATE_B_HOST_STATUS 0 +#define OTG_STATE_B_HOST_STATUS_MASK 0 +#ifndef VERBOSE +#define OTG_STATE_B_HOST_INTERRUPTS (OTG_INT_DEFAULT | OTG_INT_SVC | \ + OTG_INT_PCC) +#else +#define OTG_STATE_B_HOST_INTERRUPTS (OTG_INT_DEFAULT | OTG_INT_SVC | \ + OTG_INT_PCC | OTG_INT_SVC | \ + OTG_INT_PSPDC) + /* OTG_INT_LSTC */ +#endif + +/* + * OTG_STATE_B_HOST_WT + */ +#define OTG_STATE_B_HOST_WT_CONTROL (OTG_STATE_B_HOST_CONTROL | \ + OTG_CTL_TMR_UNCOND) +#define OTG_STATE_B_HOST_WT_STATUS 0 +#define OTG_STATE_B_HOST_WT_STATUS_MASK 0 +#ifndef VERBOSE +#define OTG_STATE_B_HOST_WT_INTERRUPTS (OTG_INT_DEFAULT | OTG_INT_SVC | \ + OTG_INT_PCC | OTG_INT_TMX) +#else +#define OTG_STATE_B_HOST_WT_INTERRUPTS (OTG_STATE_B_HOST_INTERRUPTS | \ + OTG_INT_TMX) +/* +#define OTG_STATE_B_HOST_WT_INTERRUPTS (OTG_INT_DEFAULT | OTG_INT_SVC | \ + OTG_INT_PCC | OTG_INT_DPRC | \ + OTG_INT_TMX | OTG_INT_PSPDC) */ + /* OTG_INT_LSTC */ +#endif + +/* + * OTG_STATE_B_SRP_INIT + */ +#define OTG_STATE_B_SRP_INIT_CONTROL OTG_STATE_B_IDLE_CONTROL +#define OTG_STATE_B_SRP_INIT_STATUS 0 +#define OTG_STATE_B_SRP_INIT_STATUS_MASK 0 +#define OTG_STATE_B_SRP_INIT_INTERRUPTS OTG_INT_DEFAULT + +/* + * OTG_STATE_B_SRP_WTSE0 + */ +#define OTG_STATE_B_SRP_WAIT_SE0_CONTROL (OTG_STATE_B_SRP_INIT_CONTROL | \ + OTG_CTL_TMR_UNCOND) +#define OTG_STATE_B_SRP_WAIT_SE0_STATUS 0 +#define OTG_STATE_B_SRP_WAIT_SE0_STATUS_MASK 0 +#define OTG_STATE_B_SRP_WAIT_SE0_INTERRUPTS (OTG_STATE_B_SRP_INIT_INTERRUPTS \ + | OTG_INT_TMX | OTG_INT_LSTC) + +/* + * OTG_STATE_B_SRP_D_PLS + * + * note: changing to this state requires an additional call: + * set_srp_conditions (dev); + * reset_srp_conditions (dev) is required for the next state + */ +#define OTG_STATE_B_SRP_D_PULSE_CONTROL (OTG_CTL_PERIPHERAL_DEFAULT | \ + OTG_CTL_PUEN | \ + OTG_CTL_TMR_UNCOND) +#define OTG_STATE_B_SRP_D_PULSE_STATUS 0 +#define OTG_STATE_B_SRP_D_PULSE_STATUS_MASK 0 +#define OTG_STATE_B_SRP_D_PULSE_INTERRUPTS (OTG_STATE_B_SRP_INIT_INTERRUPTS \ + | OTG_INT_SEC | OTG_INT_TMX) + +/* + * OTG_STATE_B_SRP_V_PLS + */ +#define OTG_STATE_B_SRP_V_PULSE_CONTROL (OTG_STATE_B_SRP_INIT_CONTROL | \ + OTG_CTL_CHRG | \ + OTG_CTL_TMR_UNCOND) +#define OTG_STATE_B_SRP_V_PULSE_STATUS 0 +#define OTG_STATE_B_SRP_V_PULSE_STATUS_MASK 0 +#define OTG_STATE_B_SRP_V_PULSE_INTERRUPTS (OTG_STATE_B_SRP_INIT_INTERRUPTS \ + | OTG_INT_TMX) + +/* + * OTG_STATE_B_SRP_V_DCG + */ +#define OTG_STATE_B_SRP_V_DCHRG_CONTROL (OTG_STATE_B_SRP_INIT_CONTROL | \ + OTG_CTL_DISCHRG | \ + OTG_CTL_TMR_UNCOND) +#define OTG_STATE_B_SRP_V_DCHRG_STATUS 0 +#define OTG_STATE_B_SRP_V_DCHRG_STATUS_MASK 0 +#define OTG_STATE_B_SRP_V_DCHRG_INTERRUPTS (OTG_STATE_B_SRP_INIT_INTERRUPTS \ + | OTG_INT_TMX) + +/* + * OTG_STATE_B_SRP_WTVB + */ +#define OTG_STATE_B_SRP_WAIT_VBUS_CONTROL (OTG_STATE_B_SRP_INIT_CONTROL | \ + OTG_CTL_TMR_UNCOND) +#define OTG_STATE_B_SRP_WAIT_VBUS_STATUS 0 +#define OTG_STATE_B_SRP_WAIT_VBUS_STATUS_MASK 0 +#define OTG_STATE_B_SRP_WAIT_VBUS_INTERRUPTS (OTG_STATE_B_SRP_INIT_INTERRUPTS \ + | OTG_INT_SVC | OTG_INT_TMX) + +/*********************************/ + +/* other */ + +#define OTG_APP_REQ_ACK 0 + + +/***************************************************************************** +* Types +*****************************************************************************/ + + +/***************************************************************************** +* Macros +*****************************************************************************/ + +/* printing messages */ + +#define INFO(args...) \ + printk(KERN_INFO DRIVER_NAME_FOR_PRINT ": " args) + +#ifdef WARN +#undef WARN +#endif + +#define WARN(args...) \ + printk(KERN_WARNING DRIVER_NAME_FOR_PRINT " warning: " args) + +#define ERR(args...) \ + printk(KERN_ERR DRIVER_NAME_FOR_PRINT " error: " args) + +#ifdef DEBUG +#define DBG(args...) \ + printk(KERN_DEBUG DRIVER_NAME_FOR_PRINT " debug: " args) +#else +#define DBG(args...) \ + do {} while (0) +#endif + +#ifdef VERBOSE +#define VDBG DBG +#else +#define VDBG(args...) \ + do { } while (0) +#endif + +/****************************************************************************/ + +/* this should always return "1" and print something in verbose mode */ +#ifdef VERBOSE +#define VDBG_SPC(fmt,args...) \ + (VDBG (fmt, args) ? 1 : 1) +#else +#define VDBG_SPC(fmt,args...) 1 +#endif + +/* query bit(s) (long: 32-bit access) */ +#define IS_BIT_RES(data, code) \ + (!((data) & (code)) ? \ + (VDBG_SPC (" OTG HW status: %s is reset\n", #data)) : 0) + +#define IS_BIT_SET(data, code) \ + (((data) & (code)) ? \ + (VDBG_SPC (" OTG HW status: %s is set\n", #data)) : 0) + +/* query SW flag(s) */ +#define IS_FLAG_RES(dev, data) \ + (!((data) & (dev)->transceiver.params) ? \ + (VDBG_SPC (" OTG SW status: %s is reset\n", #data)) : 0) + +#define IS_FLAG_SET(dev, data) \ + (((data) & (dev)->transceiver.params) ? \ + (VDBG_SPC (" OTG SW status: %s is set\n", #data)) : 0) + +/* query event bit(s) */ +#define GOT_EVENT(data, code) \ + (((data) & (code)) ? \ + (VDBG_SPC (" OTG event: %s\n", #data)) : 0) + +/* set SW flag */ +#ifdef VERBOSE +#define SET_FLAG(dev, data) \ + if (!((data) & (dev)->transceiver.params)) \ + DBG (" OTG SW status change: set flag %s\n", #data); \ + (dev)->transceiver.params |= (data) +#else +#define SET_FLAG(dev, data) \ + (dev)->transceiver.params |= (data) +#endif + +/* reset SW flag */ +#ifdef VERBOSE +#define RES_FLAG(dev, data) \ + if ((data) & (dev)->transceiver.params) \ + DBG (" OTG SW status change: reset flag %s\n", #data); \ + (dev)->transceiver.params &= ~((u32) (data)) +#else +#define RES_FLAG(dev, data) \ + (dev)->transceiver.params &= ~((u32) (data)) +#endif + +/* reset event bit */ +#define RES_EVENT(data, code) \ + (code) &= ~((u32) (data)) +/* NOTE: this is not really needed so far, might be replaced with */ +/* #define RES_EVENT(data, code) \ */ +/* do {} while (0) */ + +/* change OTG state */ +#ifdef CONFIG_USB_OTG +#define PREPARE_STATE_CHANGE_1ST(dev, new_state) \ + switch ((new_state) & OTG_STATE_MASK) { \ + case OTG_STATE_UNDEFINED: \ + set_undef_state_defaults((dev)); \ + break; \ + case OTG_STATE_A_IDLE: \ + set_a_state_defaults((dev)); \ + break; \ + case OTG_STATE_B_IDLE: \ + set_b_state_defaults((dev)); \ + break; \ + default: \ + break; \ + } \ + do {} while (0) +#else +#define PREPARE_STATE_CHANGE_1ST(dev, new_state) \ + do {} while (0) +#endif + +#ifdef CONFIG_SOC_AU1200 + +#if (USB_VBUS_GPIO < GPIO_2_BASE) +#define AU1000GPIO_SET_BIT(data) \ + au1000gpio_bit_set (data) +#define AU1000GPIO_CLR_BIT(data) \ + au1000gpio_bit_clear (data) +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,59) +#define AU1000GPIO_INIT_BIT(data) \ + au1000gpio_bit_init (data, &init_usb_vbus_switch) +#define AU1000GPIO_TERM_BIT(data) \ + au1000gpio_bit_term (data, &init_usb_vbus_switch) +#else +#define AU1000GPIO_INIT_BIT(data) \ + au1000gpio_bit_init (data) +#define AU1000GPIO_TERM_BIT(data) \ + au1000gpio_bit_term (data) +#endif +#else +#define AU1000GPIO_SET_BIT(data) \ + au1000gpio2_bit_set (data) +#define AU1000GPIO_CLR_BIT(data) \ + au1000gpio2_bit_clear (data) +#define AU1000GPIO_INIT_BIT(data) \ + au1000gpio2_bit_init (data) +#define AU1000GPIO_TERM_BIT(data) \ + au1000gpio2_bit_term (data) +#endif + +#define PREPARE_STATE_CHANGE_2ND(new_state_control) \ + if (((new_state_control) & OTG_CTL_PPO) && \ + (~(new_state_control) & OTG_CTL_PPWR)) \ + AU1000GPIO_SET_BIT(USB_VBUS_GPIO); \ + else \ + AU1000GPIO_CLR_BIT(USB_VBUS_GPIO) +#else +#define PREPARE_STATE_CHANGE_2ND(new_state_control) \ + do {} while (0) +#endif + +#define CHANGE_STATE(dev, new_state, pMask) \ + PREPARE_STATE_CHANGE_1ST(dev, new_state); \ + PREPARE_STATE_CHANGE_2ND(new_state##_CONTROL); \ + writel ((new_state##_CONTROL), &(dev)->regs->ctl); \ + *(pMask) = (new_state##_INTERRUPTS); \ + (dev)->transceiver.state = (new_state); \ + DBG ("OTG new state: %s\n", #new_state) + +/* verify OTG state */ +#ifndef CONFIG_OTG_TEST_MODE + +#define CHECK_STATE(dev, act_state, pMask) \ + *(pMask) = (act_state##_INTERRUPTS); \ + (dev)->transceiver.prv_state = (act_state); \ + VDBG ("OTG state: %s\n", #act_state) +#else +#define CHECK_STATE(dev, act_state, pMask) \ + *(pMask) = (act_state##_INTERRUPTS); \ + (dev)->transceiver.prv_state = (act_state); \ + if (((readl (&(dev)->regs->sts) ^ (act_state##_STATUS))) & \ + act_state##_STATUS_MASK) \ + WARN ("OTG warning: incorrect status\n"); \ + VDBG ("OTG state: %s\n", #act_state) +#endif + +/* set timer */ +#define SET_OTG_TIMER(dev, val) \ + set_timer ((dev), ((OTG_TMR_##val) * 100)) + +/* set timer ( <1ms ) */ +#define SET_OTG_TIMER_SHORT(dev, val) \ + set_timer ((dev), ((OTG_TMR_##val) / 10)) + +/* set timer ( >10ms ) */ +#define SET_OTG_TIMER_LONG(dev, val) \ + set_timer_long ((dev), ((OTG_TMR_##val) / 10)) + +#ifdef VERBOSE +#define HS_DISCON_WARNING() \ + if (!(OTG_CTL_ENABLE_UHC ^ \ + (OTG_CTL_MUX_MASK & readl (&dev->regs->ctl))) && \ + !(OTG_STS_PSPD & readl (&dev->regs->sts))) \ + DBG (" OTG warning: disable UHC from HS-mode\n") +#else +#define HS_DISCON_WARNING() \ + do { } while (0) +#endif + + +/***************************************************************************** +* Data +*****************************************************************************/ +#ifdef __cplusplus +extern "C" +{ +#endif + +struct otg_regs { + u32 cap; /* capabilities */ + u32 mux; /* mux */ + u32 sts; /* status */ + u32 ctl; /* control */ + u32 tmr; /* timer */ + u32 intr; /* interrupt request */ + u32 inten; /* interrupt enable */ +} __attribute__ ((packed)); + + +struct otg { + spinlock_t lock; + unsigned enabled : 1, + got_irq : 1, + region : 1; + u16 chiprev; + +#ifdef CONFIG_SOC_AU1200 +#ifdef USE_AU1200_PCI_DUMMY + + struct pci_dev *pdev; +#else + struct platform_device *pdev; +#endif +#else + struct pci_dev *pdev; +#endif + struct otg_regs *regs; + struct otg_transceiver transceiver; +}; +#define otg_transceiver_to_otg(pTransceiver) \ + container_of (otg, struct otg, pTransceiver) +#define otg_to_transceiver(pOtg) \ + &pOtg->transceiver + +#ifdef __KERNEL__ + +/* 2.5 and 2.4.older portability changes ... */ + +#ifndef container_of +#define container_of list_entry +#endif + +#ifndef likely +#define likely(x) (x) +#define unlikely(x) (x) +#endif + +#ifndef BUG_ON +#define BUG_ON(condition) do { if (unlikely((condition)!=0)) BUG(); } while(0) +#endif + +#ifndef WARN_ON +#define WARN_ON(x) do { } while (0) +#endif + +#endif /* __KERNEL__ */ + +#ifdef __cplusplus +} /* extern "C" */ +#endif + + +/***************************************************************************** +* Functions +*****************************************************************************/ +#ifdef __cplusplus +extern "C" +{ +#endif + +extern int usb_gadget_register_otg (struct otg_transceiver * ( + *get_transceiver)(void)); +extern int usb_gadget_unregister_otg (void); + +void otg_init_state (struct otg *); +int otg_exit_state (struct otg *); + +#ifdef DEBUG +static void print_regs (struct otg *); +#endif /* DEBUG */ + +#ifdef __cplusplus +} /* extern "C" */ +#endif + + +/***************************************************************************** +* Inline Functions +*****************************************************************************/ + +extern u32 otg_tmr_high_count; +extern struct otg_ctl *otg_ctl; + +#ifdef CONFIG_USB_OTG +/** + * \brief + * set neutral state information + * + * \param dev OTG controller info + * + * \return void + */ +static inline void set_undef_state_defaults (struct otg *dev) +{ + dev->transceiver.default_a = 0; + if (dev->transceiver.host) { + dev->transceiver.host->is_b_host = 0; + } + if (dev->transceiver.gadget) { + dev->transceiver.gadget->is_a_peripheral = 0; + } +} + +/** + * \brief + * set A state information + * + * \param dev OTG controller info + * + * \return void + */ +static inline void set_a_state_defaults (struct otg *dev) +{ + dev->transceiver.default_a = 1; + if (dev->transceiver.host) { + dev->transceiver.host->is_b_host = 0; + } + if (dev->transceiver.gadget) { + dev->transceiver.gadget->is_a_peripheral = 1; + } +} + +/** + * \brief + * set B state information + * + * \param dev OTG controller info + * + * \return void + */ +static inline void set_b_state_defaults (struct otg *dev) +{ + dev->transceiver.default_a = 0; + if (dev->transceiver.host) { + dev->transceiver.host->is_b_host = 1; + } + if (dev->transceiver.gadget) { + dev->transceiver.gadget->is_a_peripheral = 0; + } +} + +/** + * \brief + * set B state information + * + * \param dev OTG controller info + * + * \return void + */ +static inline void reset_b_hnp_enable (struct otg *dev) +{ + if (dev->transceiver.host) { + dev->transceiver.host->b_hnp_enable = 0; + } + VDBG (" OTG action: HNP disabled in B-device\n"); +} + +/** + * \brief + * set B state information + * + * \param dev OTG controller info + * + * \return void + */ +static inline int is_b_hnp_enabled (struct otg *dev) +{ + int retVal = 0; + + if (dev->transceiver.host && + dev->transceiver.host->b_hnp_enable) { + VDBG (" OTG status: HNP is enabled in HS-B-device\n"); + retVal = 1; + } +#ifdef VERBOSE + else { + DBG (" OTG status: HNP is disabled in B-device\n"); + } +#endif + return retVal; +} +#endif + +/** + * \brief + * Read the status register + * + * \param dev OTG controller info + * + * \return status + */ +static inline u32 get_status (struct otg *dev) +{ + return (readl (&dev->regs->sts)); +} + +/** + * \brief + * Load and start the timer for an unconditional run + * + * \param dev OTG controller info + * \param val Value to load + * + * \return void + */ +static inline void set_timer (struct otg *dev, u32 val) +{ + otg_tmr_high_count = 0; + + writel ((val), &dev->regs->tmr); + VDBG (" OTG action: start timer: %d0 us\n", val); +} + +/** + * \brief + * Load and start the timer for an unconditional run + * + * \param dev OTG controller info + * \param val Value to load + * + * \return void + */ +static inline void set_timer_long (struct otg *dev, u32 val) +{ + otg_tmr_high_count = val - 1; + + writel (TIMER_PERIOD, &dev->regs->tmr); + VDBG (" OTG action: start timer: %d0 ms\n", val); +} + +/** + * \brief + * Re-start the timer (value already loaded) + * + * \param dev OTG controller info + * + * \return void + */ +static inline void restart_timer (struct otg *dev) +{ + writel ((readl (&dev->regs->ctl) | OTG_CTL_TMR_UNCOND), + &dev->regs->ctl); +} + +/** + * \brief + * Reset the timer while running (value already loaded) + * + * \param dev OTG controller info + * + * \return void + */ +static inline void reset_timer (struct otg *dev) +{ + u32 temp; + + temp = readl (&dev->regs->ctl); + writel ((temp & ~((u32) OTG_CTL_TMR_ALL)), &dev->regs->ctl); + writel (temp, &dev->regs->ctl); + VDBG (" OTG action: re-start timer\n"); +} + +/** + * \brief + * Prepare the D-pulse + * + * \param dev OTG controller info + * + * \return void + */ +static inline void set_srp_conditions (struct otg *dev) +{ + VDBG (" OTG action: SRP init: no action needed due to A0 WAs\n"); +} + +/** + * \brief + * Reset conditions after SRP + * + * activates the auto-pull-up feature so after SRP the host + * will detect a device connect after calling this function + * + * \param dev OTG controller info + * + * \return void + */ +static inline void reset_srp_conditions (struct otg *dev) +{ + VDBG (" OTG action: SRP done: no action needed due to A0 WAs\n"); +} + +/** + * \brief + * enable HNP for both devices + * + * \param dev OTG controller info + * + * \return success + */ +static inline int otg_enable_hnp (struct otg *dev) +{ + int retVal = 0; + return retVal; +} + +#ifdef DEBUG +/** + * \brief + * Print OTG controller registers (debug mode only) + * + * \param dev OTG controller info + * + * \return void + */ +static inline void print_regs (struct otg *dev) +{ + DBG( "-- UOC registers ---\n"); + DBG( "otg cap = %08x\n", readl (&dev->regs->cap)); + DBG( "otg mux = %08x\n", readl (&dev->regs->mux)); + DBG( "otg sts = %08x\n", readl (&dev->regs->sts)); + DBG( "otg ctl = %08x\n", readl (&dev->regs->ctl)); + DBG( "otg tmr = %08x\n", readl (&dev->regs->tmr)); + DBG( "otg intr = %08x\n", readl (&dev->regs->intr)); + DBG( "otg inten = %08x\n", readl (&dev->regs->inten)); + DBG( "--------------------\n"); +} +#endif /* DEBUG */ + +/** + * \brief + * GPIO functions (Au1200 only) + * + * \param data pin info + * + * \return success + */ +static inline int au1000gpio_bit_get (u32 data) +{ + return (au_readl ((SYS_PINSTATERD & (1 << data)) ? 1 : 0)); +} + +#ifdef CONFIG_AU1X00_GPIO + + /* GPIO functions are defined in drivers/char/au1000_gpio.c */ + +#else + +static inline int au1000gpio_bit_tristate (u32 data) +{ + au_writel ((1 << data), SYS_TRIOUTCLR); + return 0; +} + +static inline int au1000gpio_bit_set (u32 data) +{ + au_writel ((1 << data), SYS_OUTPUTSET); + return 0; +} + +static inline int au1000gpio_bit_clear (u32 data) +{ + au_writel ((1 << data), SYS_OUTPUTCLR); + return 0; +} + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,59) +static inline int au1000gpio_bit_init (u32 data, au1x00_gpio_bit_ctl *opt) +{ + if (opt->direction) { + + if (opt->data) { + return (au1000gpio_bit_set (data)); + } + else { + return (au1000gpio_bit_clear (data)); + } + } + else { + au_writel ((~au_readl (SYS_TRIOUTRD) | (1 << data)), + SYS_TRIOUTCLR); + } + return 0; +} + +static inline int au1000gpio_bit_term (u32 data, au1x00_gpio_bit_ctl *opt) +{ + if (opt->direction) { + + if (opt->data < 0) { + return (au1000gpio_bit_tristate (data)); + } + else { + if (opt->data) { + return (au1000gpio_bit_set (data)); + } + else { + return (au1000gpio_bit_clear (data)); + } + } + } + return 0; +} +#else + +static inline int au1000gpio_bit_init (u32 data) +{ + return au1000gpio_bit_set (data); +} + +static inline int au1000gpio_bit_term (u32 data) +{ + return au1000gpio_bit_set (data); +} +#endif + +static inline int au1000gpio2_bit_set (u32 data) +{ + au_writel (((1 << (data - GPIO_2_BASE)) | + (1 << (data - GPIO_2_BASE + 0x10))), GPIO2_OUTPUT); + au_sync(); + return 0; +} + +static inline int au1000gpio2_bit_clear (u32 data) +{ + au_writel ((1 << (data - GPIO_2_BASE + 0x10)), GPIO2_OUTPUT); + au_sync(); + return 0; +} + +static inline int au1000gpio2_bit_init (u32 data) +{ + u32 temp = au_readl (GPIO2_ENABLE); + + if (!(temp | 1)) { + au_writel (temp | 1, GPIO2_ENABLE); + au_readl (GPIO2_ENABLE); + udelay (20); + } + if (temp | 2) { + au_writel (((temp & 0xfffffffd) | 1), GPIO2_ENABLE); + au_readl (GPIO2_ENABLE); + } + + /* FIXME: check the system impact of the P0A setting */ + /* DbAu1200 pin (GPIO_215) pin is shared w/ PSC0 functions */ + /* setting this field to GPIO affects also GPIO_16, GPIO_31 */ + + if (data == GPIO_215) { + au_writel (((au_readl (SYS_PINFUNC) & + ~((u32) SYS_PINFUNC_P0A)) | SYS_PINFUNC_P0A_GPIO), + SYS_PINFUNC); + } + au_writel (au_readl (GPIO2_INTENABLE) & ~(1 << (data - GPIO_2_BASE)), + GPIO2_INTENABLE); + au_writel (au_readl (GPIO2_DIR) | (1 << (data - GPIO_2_BASE)), + GPIO2_DIR); + au_sync(); + return 0; +} + +static inline int au1000gpio2_bit_term (u32 data) +{ + return au1000gpio2_bit_set (data); +} +#endif + +#endif /* AU1200_UOC_H */ diff --git a/drivers/usb/gadget/gadget_chips.h b/drivers/usb/gadget/gadget_chips.h index 5246e8f..7446dd8 100644 --- a/drivers/usb/gadget/gadget_chips.h +++ b/drivers/usb/gadget/gadget_chips.h @@ -74,6 +74,12 @@ #define gadget_is_omap(g) 0 #endif +#ifdef CONFIG_USB_GADGET_AU1200 +#define gadget_is_au1200(g) !strcmp("au1200_udc", (g)->name) +#else +#define gadget_is_au1200(g) 0 +#endif + /* not yet ported 2.4 --> 2.6 */ #ifdef CONFIG_USB_GADGET_N9604 #define gadget_is_n9604(g) !strcmp("n9604_udc", (g)->name) diff --git a/include/linux/usb/otg.h b/include/linux/usb/otg.h index 1db25d1..5b88c43 100644 --- a/include/linux/usb/otg.h +++ b/include/linux/usb/otg.h @@ -45,7 +45,12 @@ struct otg_transceiver { u8 default_a; enum usb_otg_state state; - +#ifdef CONFIG_USB_PORT_AU1200OTG + u8 prv_state; + u32 params; + void *otg_priv; + u8 hostcount; +#endif struct usb_bus *host; struct usb_gadget *gadget; -- 1.5.4.3 From khickey@rmicorp.com Mon Aug 4 21:20:24 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 04 Aug 2008 21:20:28 +0100 (BST) Received: from mx1.razamicroelectronics.com ([63.111.213.197]:24498 "EHLO hq-ex-mb01.razamicroelectronics.com") by ftp.linux-mips.org with ESMTP id S20043940AbYHDUUY convert rfc822-to-8bit (ORCPT ); Mon, 4 Aug 2008 21:20:24 +0100 Received: from 10.8.0.25 ([10.8.0.25]) by hq-ex-mb01.razamicroelectronics.com ([10.1.1.40]) via Exchange Front-End Server webmail.razamicroelectronics.com ([10.1.1.41]) with Microsoft Exchange Server HTTP-DAV ; Mon, 4 Aug 2008 20:20:15 +0000 Received: from kh-ubuntu by webmail.razamicroelectronics.com; 04 Aug 2008 15:20:31 -0500 Subject: Re: [PATCH] [MIPS] Add USB device (OTG) support for Au1200 and Au1250 From: Kevin Hickey To: linux-mips@linux-mips.org Cc: ralf@linux-mips.org In-Reply-To: <1217881052-18797-2-git-send-email-khickey@rmicorp.com> References: <> <1217881052-18797-1-git-send-email-khickey@rmicorp.com> <1217881052-18797-2-git-send-email-khickey@rmicorp.com> Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8BIT Date: Mon, 04 Aug 2008 15:20:31 -0500 Message-Id: <1217881231.19819.26.camel@kh-ubuntu.razamicroelectronics.com> Mime-Version: 1.0 X-Mailer: Evolution 2.22.3.1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20092 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: khickey@rmicorp.com Precedence: bulk X-list: linux-mips I intended there to be an introductory email that said: The following is a patch adding preliminary device-only OTG support for the Au1200 and Au1250. It is made largely of code that I inherited that was never published. This is the largest patch I have submitted thus far, and the first one including a new driver. I welcome comments on anything in the code, as well as the format and presentation of the patch. I will happily rev this to meet the community's standards. Thanks. (I'm clearly still getting the hang of git-send-email) -- Kevin Hickey Alchemy Solutions RMI Corporation khickey@RMICorp.com P: 512.691.8044 From tanzy@gmx.de Mon Aug 4 21:29:49 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 04 Aug 2008 21:29:59 +0100 (BST) Received: from mail.gmx.net ([213.165.64.20]:39040 "HELO mail.gmx.net") by ftp.linux-mips.org with SMTP id S20044743AbYHDU3t (ORCPT ); Mon, 4 Aug 2008 21:29:49 +0100 Received: (qmail invoked by alias); 04 Aug 2008 20:29:42 -0000 Received: from p548B1C75.dip0.t-ipconnect.de (EHLO [192.168.120.22]) [84.139.28.117] by mail.gmx.net (mp057) with SMTP; 04 Aug 2008 22:29:42 +0200 X-Authenticated: #16080105 X-Provags-ID: V01U2FsdGVkX19bqGMIjW5bUMys+u1FgMvC20/wjz8tIrJ1/v45oF O7Zdi8xqndMFea Message-ID: <489766BB.5090607@gmx.de> Date: Mon, 04 Aug 2008 22:29:47 +0200 From: Johannes Dickgreber User-Agent: Thunderbird 2.0.0.6 (X11/20070801) MIME-Version: 1.0 To: Kumba CC: Linux MIPS List Subject: Re: [PATCH/RFC]: SGI Octane (IP30) Patches, Part two, Octane core References: <48914C74.6090309@gentoo.org> In-Reply-To: <48914C74.6090309@gentoo.org> X-Enigmail-Version: 0.95.3 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Y-GMX-Trusted: 0 X-FuHaFi: 0.57 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20093 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: tanzy@gmx.de Precedence: bulk X-list: linux-mips Kumba schrieb: > > The second part is the actual IP30 Patch that makes these beasts boot. > Assuming you've already lit incense candles and sacrificed a PC to the > MIPS Gods above. > > There's one change that probably needs good scrutiny, as it changes a > value in dma-default.c, and this'll affect other systems: > > diff -Naurp linux-2.6.26.orig/arch/mips/mm/dma-default.c > linux-2.6.26/arch/mips/mm/dma-default.c > --- linux-2.6.26.orig/arch/mips/mm/dma-default.c 2008-07-13 > 17:51:29.000000000 -0400 > +++ linux-2.6.26/arch/mips/mm/dma-default.c 2008-07-25 > 03:14:40.000000000 -0400 > @@ -209,7 +209,7 @@ dma_addr_t dma_map_page(struct device *d > dma_cache_wback_inv(addr, size); > } > > - return plat_map_dma_mem_page(dev, page) + offset; > + return plat_map_dma_mem_page(dev, page, size) + offset; > } > I dont think that is needed. IMHO This function schould map a whole page, offset and size are only used for a part of that page. So i am using PAGE_SIZE in plat_map_dma_mem_page. your version +static dma_addr_t plat_map_dma_mem_page(struct device *dev, struct page *page, + size_t size) +{ + dma_addr_t pa = dev_to_baddr(dev, page_to_phys(page), 0, size); + + return pa; +} + my version +static dma_addr_t plat_map_dma_mem_page(struct device *dev, struct page *page, + size_t size) +{ + dma_addr_t pa = dev_to_baddr(dev, page_to_phys(page), 0, PAGE_SIZE); + + return pa; +} Maybe it is only working, because the function dma_map_page is never used in my kernel. > Thanks!, > > > --Kumba > From tanzy@gmx.de Mon Aug 4 21:54:31 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 04 Aug 2008 21:54:38 +0100 (BST) Received: from mail.gmx.net ([213.165.64.20]:3457 "HELO mail.gmx.net") by ftp.linux-mips.org with SMTP id S20046740AbYHDUyb (ORCPT ); Mon, 4 Aug 2008 21:54:31 +0100 Received: (qmail invoked by alias); 04 Aug 2008 20:54:24 -0000 Received: from p548B1C75.dip0.t-ipconnect.de (EHLO [192.168.120.22]) [84.139.28.117] by mail.gmx.net (mp040) with SMTP; 04 Aug 2008 22:54:24 +0200 X-Authenticated: #16080105 X-Provags-ID: V01U2FsdGVkX19B8IhoX95BKDmGgssO+/jAFT6CLhyyYDvoyHgrRr 34rnhaY8ZtMxp7 Message-ID: <48976C86.60701@gmx.de> Date: Mon, 04 Aug 2008 22:54:30 +0200 From: Johannes Dickgreber User-Agent: Thunderbird 2.0.0.6 (X11/20070801) MIME-Version: 1.0 To: Kumba CC: Linux MIPS List Subject: Re: [PATCH/RFC]: SGI Octane (IP30) Patches, Part two, Octane core References: <48914C74.6090309@gentoo.org> In-Reply-To: <48914C74.6090309@gentoo.org> X-Enigmail-Version: 0.95.3 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Y-GMX-Trusted: 0 X-FuHaFi: 0.57 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20094 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: tanzy@gmx.de Precedence: bulk X-list: linux-mips Kumba schrieb: > > The second part is the actual IP30 Patch that makes these beasts boot. > Assuming you've already lit incense candles and sacrificed a PC to the > MIPS Gods above. > > That's just one example, though. There's probably more, but I've mostly > done forward ports, and haven't really messed with re-writing much. > Hence why I'd like to ask others to look, poke, prod, compile, and boot, > and see if they have other suggestions for improving and fixing this up. I think there is a problem on SMP kernels. In include/asm-mips/mach-ip30/heart.h > +/* HEART internal register space */ > +#define HEART_PIU_BASE 0x900000000ff00000 > + > +/* full addresses */ > +#define HEART_MODE ((volatile ulong *)0x900000000ff00000) > +#define HEART_SDRAM_MODE ((volatile ulong *)0x900000000ff00008) > +#define HEART_MEM_REF ((volatile ulong *)0x900000000ff00010) > +#define HEART_MEM_REQ_ARB ((volatile ulong *)0x900000000ff00018) > +#define HEART_MEMCFG0 ((volatile ulong *)0x900000000ff00020) > +#define HEART_MEMCFG1 ((volatile ulong *)0x900000000ff00028) > +#define HEART_MEMCFG2 ((volatile ulong *)0x900000000ff00030) > +#define HEART_MEMCFG3 ((volatile ulong *)0x900000000ff00038) > +#define HEART_FC_MODE ((volatile ulong *)0x900000000ff00040) > +#define HEART_FC_TIMER_LIMIT ((volatile ulong *)0x900000000ff00048) > +#define HEART_FC0_ADDR ((volatile ulong *)0x900000000ff00050) > +#define HEART_FC1_ADDR ((volatile ulong *)0x900000000ff00058) > +#define HEART_FC0_CR_CNT ((volatile ulong *)0x900000000ff00060) > +#define HEART_FC1_CR_CNT ((volatile ulong *)0x900000000ff00068) > +#define HEART_FC0_TIMER ((volatile ulong *)0x900000000ff00070) > +#define HEART_FC1_TIMER ((volatile ulong *)0x900000000ff00078) > +#define HEART_STATUS ((volatile ulong *)0x900000000ff00080) > +#define HEART_BERR_ADDR ((volatile ulong *)0x900000000ff00088) > +#define HEART_BERR_MISC ((volatile ulong *)0x900000000ff00090) > +#define HEART_MEMERR_ADDR ((volatile ulong *)0x900000000ff00098) > +#define HEART_MEMERR_DATA ((volatile ulong *)0x900000000ff000a0) > +#define HEART_PIUR_ACC_ERR ((volatile ulong *)0x900000000ff000a8) > +#define HEART_MLAN_CLK_DIV ((volatile ulong *)0x900000000ff000b0) > +#define HEART_MLAN_CTL ((volatile ulong *)0x900000000ff000b8) > +#define HEART_IMR(x) ((volatile ulong *)0x900000000ff10000 + (8 * (x))) This gives a wrong address for the second IRQ Mask Register. I schould be. #define HEART_IMR(x) ((volatile ulong *)(0x900000000ff10000 + (8 * (x)))) . . this two braces more , because without it 8*8*(x) was added to the base addr. checked in the assembler and on a DUAL IP30. without it it got stopped early with no output. with it it stopped much later. sometimes i got a starting and then stopped init. now it goes until initcall genl_init wich is generic netlink init. a smp kernel fully works with only one cpu in both versions. a patch for a 2.6.20 kernel was more like my versions too. > +#define HEART_SET_ISR ((volatile ulong *)0x900000000ff10020) > +#define HEART_CLR_ISR ((volatile ulong *)0x900000000ff10028) > +#define HEART_ISR ((volatile ulong *)0x900000000ff10030) > +#define HEART_IMSR ((volatile ulong *)0x900000000ff10038) > +#define HEART_CAUSE ((volatile ulong *)0x900000000ff10040) > +#define HEART_COUNT ((volatile ulong *)0x900000000ff20000) /* 52-bit counter */ > +#define HEART_COMPARE ((volatile ulong *)0x900000000ff30000) /* 24-bit compare */ > +#define HEART_TRIGGER ((volatile ulong *)0x900000000ff40000) > +#define HEART_PRID ((volatile ulong *)0x900000000ff50000) > +#define HEART_SYNC ((volatile ulong *)0x900000000ff60000) > Thanks!, > > > --Kumba > From tanzy@gmx.de Mon Aug 4 22:26:53 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 04 Aug 2008 22:27:00 +0100 (BST) Received: from mail.gmx.net ([213.165.64.20]:9123 "HELO mail.gmx.net") by ftp.linux-mips.org with SMTP id S20045465AbYHDV0x (ORCPT ); Mon, 4 Aug 2008 22:26:53 +0100 Received: (qmail invoked by alias); 04 Aug 2008 21:26:45 -0000 Received: from p548B1C75.dip0.t-ipconnect.de (EHLO [192.168.120.22]) [84.139.28.117] by mail.gmx.net (mp053) with SMTP; 04 Aug 2008 23:26:45 +0200 X-Authenticated: #16080105 X-Provags-ID: V01U2FsdGVkX1+ZZZQxuKaZYa3U03AHcAYiDgBqaLbTksM7lVOL+M 80vm3mkbAj3UHB Message-ID: <4897741C.1090300@gmx.de> Date: Mon, 04 Aug 2008 23:26:52 +0200 From: Johannes Dickgreber User-Agent: Thunderbird 2.0.0.6 (X11/20070801) MIME-Version: 1.0 To: Kumba CC: Linux MIPS List Subject: Re: [PATCH/RFC]: SGI Octane (IP30) Patches, Part two, Octane core References: <48914C74.6090309@gentoo.org> In-Reply-To: <48914C74.6090309@gentoo.org> X-Enigmail-Version: 0.95.3 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Y-GMX-Trusted: 0 X-FuHaFi: 0.42 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20095 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: tanzy@gmx.de Precedence: bulk X-list: linux-mips Kumba schrieb: > > The second part is the actual IP30 Patch that makes these beasts boot. > Assuming you've already lit incense candles and sacrificed a PC to the > MIPS Gods above. > > Thanks!, > > > --Kumba > > diff -Naurp linux-2.6.26.orig/arch/mips/kernel/cevt-r4k.c linux-2.6.26/arch/mips/kernel/cevt-r4k.c > --- linux-2.6.26.orig/arch/mips/kernel/cevt-r4k.c 2008-07-13 17:51:29.000000000 -0400 > +++ linux-2.6.26/arch/mips/kernel/cevt-r4k.c 2008-07-25 03:14:40.000000000 -0400 > @@ -251,7 +251,6 @@ int __cpuinit mips_clockevent_init(void) > irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq; > if (get_c0_compare_int) > irq = get_c0_compare_int(); > - > cd = &per_cpu(mips_clockevent_device, cpu); > > cd->name = "MIPS"; I dont think this is needed > diff -Naurp linux-2.6.26.orig/arch/mips/kernel/setup.c linux-2.6.26/arch/mips/kernel/setup.c > --- linux-2.6.26.orig/arch/mips/kernel/setup.c 2008-07-13 17:51:29.000000000 -0400 > +++ linux-2.6.26/arch/mips/kernel/setup.c 2008-07-25 03:14:40.000000000 -0400 > @@ -481,6 +481,10 @@ static void __init arch_mem_init(char ** > printk("Determined physical RAM map:\n"); > print_memory_map(); > > +#ifdef CONFIG_CMDLINE > + if (strlen(CONFIG_CMDLINE)) > + strlcpy(arcs_cmdline, CONFIG_CMDLINE, sizeof(command_line)); > +#endif > strlcpy(command_line, arcs_cmdline, sizeof(command_line)); > strlcpy(boot_command_line, command_line, COMMAND_LINE_SIZE); > > @@ -575,7 +579,6 @@ void __init setup_arch(char **cmdline_p) > #endif > > arch_mem_init(cmdline_p); > - > resource_init(); > plat_smp_setup(); > } arcs_cmdline is initialisiert with CONFIG_CMDLINE earlier in this file, so i think this is not needed. > diff -Naurp linux-2.6.26.orig/arch/mips/mm/dma-default.c linux-2.6.26/arch/mips/mm/dma-default.c > --- linux-2.6.26.orig/arch/mips/mm/dma-default.c 2008-07-13 17:51:29.000000000 -0400 > +++ linux-2.6.26/arch/mips/mm/dma-default.c 2008-07-25 03:14:40.000000000 -0400 > @@ -209,7 +209,7 @@ dma_addr_t dma_map_page(struct device *d > dma_cache_wback_inv(addr, size); > } > > - return plat_map_dma_mem_page(dev, page) + offset; > + return plat_map_dma_mem_page(dev, page, size) + offset; > } > > EXPORT_SYMBOL(dma_map_page); see other mail > diff -Naurp linux-2.6.26.orig/drivers/usb/host/pci-quirks.c linux-2.6.26/drivers/usb/host/pci-quirks.c > --- linux-2.6.26.orig/drivers/usb/host/pci-quirks.c 2008-07-13 17:51:29.000000000 -0400 > +++ linux-2.6.26/drivers/usb/host/pci-quirks.c 2008-07-25 03:14:40.000000000 -0400 > @@ -147,6 +147,9 @@ static void __devinit quirk_usb_handoff_ > unsigned long base = 0; > int i; > > + if (!pci_enable_device(pdev)) > + return; > + > if (!pio_enabled(pdev)) > return; > I am not using this, but i dont have any usb stuff at my Octane > diff -Naurp linux-2.6.26.orig/include/asm-mips/addrspace.h linux-2.6.26/include/asm-mips/addrspace.h > --- linux-2.6.26.orig/include/asm-mips/addrspace.h 2008-07-13 17:51:29.000000000 -0400 > +++ linux-2.6.26/include/asm-mips/addrspace.h 2008-07-25 03:14:40.000000000 -0400 > @@ -54,6 +54,14 @@ > #define XPHYSADDR(a) ((_ACAST64_(a)) & \ > _CONST64_(0x000000ffffffffff)) > > +#ifndef __ASSEMBLY__ > +#ifdef CONFIG_64BIT > +unsigned long kernel_physaddr(unsigned long); > +#else > +#define kernel_physaddr CPHYSADDR > +#endif > +#endif > + > #ifdef CONFIG_64BIT > > /* is this used anyware, i dont have it in my kernel. > diff -Naurp linux-2.6.26.orig/include/asm-mips/mach-ip30/dma-coherence.h linux-2.6.26/include/asm-mips/mach-ip30/dma-coherence.h > --- linux-2.6.26.orig/include/asm-mips/mach-ip30/dma-coherence.h 1969-12-31 19:00:00.000000000 -0500 > +++ linux-2.6.26/include/asm-mips/mach-ip30/dma-coherence.h 2008-07-25 03:14:40.000000000 -0400 > @@ -0,0 +1,90 @@ > +/* > + * This file is subject to the terms and conditions of the GNU General Public > + * License. See the file "COPYING" in the main directory of this archive > + * for more details. > + * > + * Copyright (C) 2006 Ralf Baechle > + * 2007 Joshua Kinard > + * > + * derived from include/asm-mips/mach-ip27/dma-coherence.h > + * and based on code found in the old dma-ip30.c, which is > + * Copyright (C) 2004-2007 Stanislaw Skowronek > + */ > +#ifndef __ASM_MACH_IP30_DMA_COHERENCE_H > +#define __ASM_MACH_IP30_DMA_COHERENCE_H > + > +#include > +#include > + > +#include > + > +static inline dma_addr_t pdev_to_baddr(struct pci_dev *dev, dma_addr_t addr, > + int virt, int size) > +{ > + if(dev->dma_mask == DMA_64BIT_MASK) { > + if(virt) > + return (BRIDGE_CONTROLLER(dev->bus)->baddr + addr) | > + PCI64_ATTR_VIRTUAL; > + > + if(size >= 0x200) > + return (BRIDGE_CONTROLLER(dev->bus)->baddr + addr) | > + PCI64_ATTR_PREF; > + > + if(addr >= 0x20000000 || addr < 0xA0000000) > + return (PCI32_DIRECT_BASE + addr - 0x20000000); > + > + return (BRIDGE_CONTROLLER(dev->bus)->baddr + addr); > + } > + > + if(addr < 0x20000000 || addr >= 0xA0000000) { > + printk(KERN_ERR > + "BRIDGE: Mapping can't be realized in direct DMA.\n"); > + return -1; > + } > + > + return (PCI32_DIRECT_BASE + addr - 0x20000000); > +} > + > +static inline dma_addr_t dev_to_baddr(struct device *dev, dma_addr_t addr, > + int virt, int size) > +{ > + if(dev) > + return pdev_to_baddr(to_pci_dev(dev), addr, virt, size); > + return addr; > +} > + > +struct device; > + > +static inline dma_addr_t plat_map_dma_mem(struct device *dev, void *addr, > + size_t size) > +{ > + dma_addr_t pa = dev_to_baddr(dev, virt_to_phys(addr), 1, size); > + > + return pa; > +} > + > +static dma_addr_t plat_map_dma_mem_page(struct device *dev, struct page *page, > + size_t size) > +{ > + dma_addr_t pa = dev_to_baddr(dev, page_to_phys(page), 0, size); > + > + return pa; > +} > + > +static unsigned long plat_dma_addr_to_phys(dma_addr_t dma_addr) > +{ > + return dma_addr & (0xffUL << 56); > +} > + > +static inline void plat_unmap_dma_mem(dma_addr_t dma_addr) > +{ > + /* Empty */ > +} > + > +static inline int plat_device_is_coherent(struct device *dev) > +{ > + return 1; /* IP30 non-cohernet mode is unsupported > + * (does it even have one?) */ > +} > + > +#endif /* __ASM_MACH_IP30_DMA_COHERENCE_H */ see other mail for the size in plat_map_dma_mem_page wich IMHO schould be PAGE_SIZE bye tanzy From anemo@mba.ocn.ne.jp Tue Aug 5 01:33:14 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 05 Aug 2008 01:33:24 +0100 (BST) Received: from topsns2.toshiba-tops.co.jp ([202.230.225.126]:11316 "EHLO topsns2.toshiba-tops.co.jp") by ftp.linux-mips.org with ESMTP id S20040155AbYHEAdO (ORCPT ); Tue, 5 Aug 2008 01:33:14 +0100 Received: from no.name.available by topsns2.toshiba-tops.co.jp via smtpd (for ftp.linux-mips.org [213.58.128.207]) with ESMTP; Tue, 5 Aug 2008 09:33:12 +0900 Received: from topsms.toshiba-tops.co.jp (localhost.localdomain [127.0.0.1]) by localhost.toshiba-tops.co.jp (Postfix) with ESMTP id 4D292448F3; Tue, 5 Aug 2008 09:33:07 +0900 (JST) Received: from srd2sd.toshiba-tops.co.jp (srd2sd.toshiba-tops.co.jp [172.17.28.2]) by topsms.toshiba-tops.co.jp (Postfix) with ESMTP id 385F544416; Tue, 5 Aug 2008 09:33:07 +0900 (JST) Received: from localhost (fragile [172.17.28.65]) by srd2sd.toshiba-tops.co.jp (8.12.10/8.12.10) with ESMTP id m750X6fl054861; Tue, 5 Aug 2008 09:33:06 +0900 (JST) (envelope-from anemo@mba.ocn.ne.jp) Date: Tue, 05 Aug 2008 09:33:05 +0900 (JST) Message-Id: <20080805.093305.233543912.nemoto@toshiba-tops.co.jp> To: tsbogend@alpha.franken.de Cc: linux-mips@linux-mips.org, ralf@linux-mips.org Subject: Re: [PATCH v2] IP27: Switch over to RTC class driver From: Atsushi Nemoto In-Reply-To: <20080804170021.AAE18C2EAA@solo.franken.de> References: <20080804170021.AAE18C2EAA@solo.franken.de> X-Fingerprint: 6ACA 1623 39BD 9A94 9B1A B746 CA77 FE94 2874 D52F X-Pgp-Public-Key: http://wwwkeys.pgp.net/pks/lookup?op=get&search=0x2874D52F X-Mailer: Mew version 6.1 on Emacs 22.2 / Mule 5.0 (SAKAKI) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20096 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anemo@mba.ocn.ne.jp Precedence: bulk X-list: linux-mips On Mon, 4 Aug 2008 19:00:21 +0200 (CEST), Thomas Bogendoerfer wrote: > + res.start = XPHYSADDR(KL_CONFIG_CH_CONS_INFO(master_nasid)->memory_base + > + IOC3_BYTEBUS_DEV0); > + res.end = res.start + 32768; res.end should be res.start + 32767 ? From tsbogend@alpha.franken.de Tue Aug 5 09:52:33 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 05 Aug 2008 09:52:43 +0100 (BST) Received: from elvis.franken.de ([193.175.24.41]:8402 "EHLO elvis.franken.de") by ftp.linux-mips.org with ESMTP id S20022091AbYHEIwd (ORCPT ); Tue, 5 Aug 2008 09:52:33 +0100 Received: from uucp (helo=solo.franken.de) by elvis.franken.de with local-bsmtp (Exim 3.36 #1) id 1KQIHO-00074E-00; Tue, 05 Aug 2008 10:52:30 +0200 Received: by solo.franken.de (Postfix, from userid 1000) id 2ED7CC3160; Tue, 5 Aug 2008 10:52:23 +0200 (CEST) Date: Tue, 5 Aug 2008 10:52:23 +0200 To: Atsushi Nemoto Cc: linux-mips@linux-mips.org, ralf@linux-mips.org Subject: Re: [PATCH v2] IP27: Switch over to RTC class driver Message-ID: <20080805085222.GA6808@alpha.franken.de> References: <20080804170021.AAE18C2EAA@solo.franken.de> <20080805.093305.233543912.nemoto@toshiba-tops.co.jp> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20080805.093305.233543912.nemoto@toshiba-tops.co.jp> User-Agent: Mutt/1.5.13 (2006-08-11) From: tsbogend@alpha.franken.de (Thomas Bogendoerfer) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20097 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: tsbogend@alpha.franken.de Precedence: bulk X-list: linux-mips On Tue, Aug 05, 2008 at 09:33:05AM +0900, Atsushi Nemoto wrote: > On Mon, 4 Aug 2008 19:00:21 +0200 (CEST), Thomas Bogendoerfer wrote: > > + res.start = XPHYSADDR(KL_CONFIG_CH_CONS_INFO(master_nasid)->memory_base + > > + IOC3_BYTEBUS_DEV0); > > + res.end = res.start + 32768; > > res.end should be res.start + 32767 ? correct, I'll fix that. Thomas. -- Crap can work. Given enough thrust pigs will fly, but it's not necessary a good idea. [ RFC1925, 2.3 ] From mano@roarinelk.homelinux.net Tue Aug 5 10:38:36 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 05 Aug 2008 10:38:42 +0100 (BST) Received: from fnoeppeil43.netpark.at ([217.175.205.171]:20680 "EHLO roarinelk.homelinux.net") by ftp.linux-mips.org with ESMTP id S20045206AbYHEJig (ORCPT ); Tue, 5 Aug 2008 10:38:36 +0100 Received: (qmail 26310 invoked from network); 5 Aug 2008 11:38:32 +0200 Received: from flagship.roarinelk.net (HELO ?192.168.0.197?) (192.168.0.197) by fnoeppeil43.netpark.at with SMTP; 5 Aug 2008 11:38:32 +0200 Message-ID: <48981F96.5040907@roarinelk.homelinux.net> Date: Tue, 05 Aug 2008 11:38:30 +0200 From: Manuel Lauss Organization: Private User-Agent: Thunderbird 2.0.0.16 (X11/20080726) MIME-Version: 1.0 To: Kevin Hickey CC: linux-mips@linux-mips.org, ralf@linux-mips.org Subject: Re: [PATCH] [MIPS] Add USB device (OTG) support for Au1200 and Au1250 References: <> <1217881052-18797-1-git-send-email-khickey@rmicorp.com> <1217881052-18797-2-git-send-email-khickey@rmicorp.com> In-Reply-To: <1217881052-18797-2-git-send-email-khickey@rmicorp.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20098 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mano@roarinelk.homelinux.net Precedence: bulk X-list: linux-mips Hi Kevin, Kevin Hickey wrote: > This patch adds support for the USB Device controller on the Au1200 and Au1250. Awesome! > With this patch, only basic device mode is supported; full On-The-Go > functionality will be completed in a later release. Two new drivers are > included; au1200_udc is the USB Device Controller driver and au1200_otg is the > portmux driver. The portmux driver determines the mode of operation for the > port based on software and hardware selectors. Currently, it only supports > device mode. > > These drivers have been tested on a DB1200 board using the g_file_storage gadget. Apart from the usual condingstyle nits (run it through scripts/checkpatch.pl please), there's one thing: The GPIO code in the uoc header must go away. Pass function pointers to enable/disable VBUS through platform data, but don't modify GPIOs directly (i.e. get rid of all code which assumes its running on DB1200). You should also CC linux-usb ML. Thanks, Manuel Lauss From ricmm@gentoo.org Tue Aug 5 11:37:31 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 05 Aug 2008 11:37:39 +0100 (BST) Received: from smtp.gentoo.org ([140.211.166.183]:31695 "EHLO smtp.gentoo.org") by ftp.linux-mips.org with ESMTP id S20021826AbYHEKhb (ORCPT ); Tue, 5 Aug 2008 11:37:31 +0100 Received: by smtp.gentoo.org (Postfix, from userid 2204) id 7369A67343; Tue, 5 Aug 2008 10:37:28 +0000 (UTC) Date: Tue, 5 Aug 2008 10:37:28 +0000 From: Ricardo Mendoza To: linux-mips@linux-mips.org Cc: ralf@linux-mips.org, yoichi_yuasa@tripeaks.co.jp, ricmm@gentoo.org Subject: [PATCH] cevt-r4k.c irq ack optimization Message-ID: <20080805103728.GA4628@woodpecker.gentoo.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline User-Agent: Mutt/1.5.16 (2007-06-09) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20099 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ricmm@gentoo.org Precedence: bulk X-list: linux-mips Hello Ralf, Whereas current implementation works, the modification below can protect us from problems such as the pipeline hazards in vr41xx cpus without any added extra code length. Also, I beleive Yoichi posted something similar a few months ago. Please apply. Ricardo --- Ack the IRQ by writing to c0_compare it's own value rather than the c0_count value. This prevents issues caused by pipeline hazards, on vr41xx for example. Signed-off-by: Ricardo Mendoza --- arch/mips/kernel/cevt-r4k.c | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/mips/kernel/cevt-r4k.c b/arch/mips/kernel/cevt-r4k.c index 24a2d90..16e079c 100644 --- a/arch/mips/kernel/cevt-r4k.c +++ b/arch/mips/kernel/cevt-r4k.c @@ -186,7 +186,7 @@ static int c0_compare_int_usable(void) * IP7 already pending? Try to clear it by acking the timer. */ if (c0_compare_int_pending()) { - write_c0_compare(read_c0_count()); + c0_timer_ack(); irq_disable_hazard(); if (c0_compare_int_pending()) return 0; @@ -208,7 +208,7 @@ static int c0_compare_int_usable(void) if (!c0_compare_int_pending()) return 0; - write_c0_compare(read_c0_count()); + c0_timer_ack(); irq_disable_hazard(); if (c0_compare_int_pending()) return 0; From ricmm@gentoo.org Tue Aug 5 11:43:17 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 05 Aug 2008 11:43:19 +0100 (BST) Received: from smtp.gentoo.org ([140.211.166.183]:3276 "EHLO smtp.gentoo.org") by ftp.linux-mips.org with ESMTP id S20021597AbYHEKnR (ORCPT ); Tue, 5 Aug 2008 11:43:17 +0100 Received: by smtp.gentoo.org (Postfix, from userid 2204) id 5FB1D67445; Tue, 5 Aug 2008 10:43:14 +0000 (UTC) Date: Tue, 5 Aug 2008 10:43:14 +0000 From: Ricardo Mendoza To: linux-mips@linux-mips.org Cc: yoichi_yuasa@tripeaks.co.jp, ralf@linux-mips.org, ricmm@gentoo.org Subject: [PATCH] vr41xx: fix problem with vr41xx_cpu_wait Message-ID: <20080805104314.GB4628@woodpecker.gentoo.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline User-Agent: Mutt/1.5.16 (2007-06-09) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20100 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ricmm@gentoo.org Precedence: bulk X-list: linux-mips Hello, Yoichi, please correct me if I am wrong but I think that the "standby" instruction does not set IE bit on its own, so calling it with interrupts disabled will loop the cpu away forever on standby state being unable to come back due to no interrupts getting through. Please ack the patch if you consider it correct. Please apply afterwards, Ralf. Ricardo --- Standby instruction can't be called with interrupts disabled as it doesn't set IE bit on it's own. Signed-off-by: Ricardo Mendoza --- arch/mips/vr41xx/common/pmu.c | 6 ------ 1 files changed, 0 insertions(+), 6 deletions(-) diff --git a/arch/mips/vr41xx/common/pmu.c b/arch/mips/vr41xx/common/pmu.c index 028aaf7..6d651ec 100644 --- a/arch/mips/vr41xx/common/pmu.c +++ b/arch/mips/vr41xx/common/pmu.c @@ -48,14 +48,8 @@ static void __iomem *pmu_base; static void vr41xx_cpu_wait(void) { - local_irq_disable(); if (!need_resched()) - /* - * "standby" sets IE bit of the CP0_STATUS to 1. - */ __asm__("standby;\n"); - else - local_irq_enable(); } static inline void software_reset(void) From mano@roarinelk.homelinux.net Tue Aug 5 13:42:24 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 05 Aug 2008 13:42:28 +0100 (BST) Received: from fnoeppeil43.netpark.at ([217.175.205.171]:54976 "EHLO roarinelk.homelinux.net") by ftp.linux-mips.org with ESMTP id S20022938AbYHEMmY (ORCPT ); Tue, 5 Aug 2008 13:42:24 +0100 Received: (qmail 27505 invoked by uid 1000); 5 Aug 2008 14:42:21 +0200 Date: Tue, 5 Aug 2008 14:42:21 +0200 From: Manuel Lauss To: linux-fbdev-devel@lists.sf.net Cc: Kevin Hickey , L-M-O Subject: [PATCH] au1200fb: fixup PM support. Message-ID: <20080805124221.GA27469@roarinelk.homelinux.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline User-Agent: Mutt/1.5.16 (2007-06-09) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20101 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mano@roarinelk.homelinux.net Precedence: bulk X-list: linux-mips Remove last traces of the custom Alchemy linux-2.4 PM code, implement suspend/resume callbacks. Signed-off-by: Manuel Lauss --- drivers/video/au1200fb.c | 164 ++++++++++++---------------------------------- 1 files changed, 41 insertions(+), 123 deletions(-) diff --git a/drivers/video/au1200fb.c b/drivers/video/au1200fb.c index 03e57ef..be945ab 100644 --- a/drivers/video/au1200fb.c +++ b/drivers/video/au1200fb.c @@ -45,10 +45,6 @@ #include #include "au1200fb.h" -#ifdef CONFIG_PM -#include -#endif - #ifndef CONFIG_FB_AU1200_DEVS #define CONFIG_FB_AU1200_DEVS 4 #endif @@ -204,12 +200,6 @@ struct window_settings { extern int board_au1200fb_panel_init (void); extern int board_au1200fb_panel_shutdown (void); -#ifdef CONFIG_PM -int au1200fb_pm_callback(au1xxx_power_dev_t *dev, - au1xxx_request_t request, void *data); -au1xxx_power_dev_t *LCD_pm_dev; -#endif - /* * Default window configurations */ @@ -651,25 +641,6 @@ static struct panel_settings known_lcd_panels[] = /********************************************************************/ -#ifdef CONFIG_PM -static int set_brightness(unsigned int brightness) -{ - unsigned int hi1, divider; - - /* limit brightness pwm duty to >= 30/1600 */ - if (brightness < 30) { - brightness = 30; - } - divider = (lcd->pwmdiv & 0x3FFFF) + 1; - hi1 = (lcd->pwmhi >> 16) + 1; - hi1 = (((brightness & 0xFF) + 1) * divider >> 8); - lcd->pwmhi &= 0xFFFF; - lcd->pwmhi |= (hi1 << 16); - - return brightness; -} -#endif /* CONFIG_PM */ - static int winbpp (unsigned int winctrl1) { int bits = 0; @@ -1247,10 +1218,6 @@ static int au1200fb_fb_mmap(struct fb_info *info, struct vm_area_struct *vma) unsigned long start=0, off; struct au1200fb_device *fbdev = (struct au1200fb_device *) info; -#ifdef CONFIG_PM - au1xxx_pm_access(LCD_pm_dev); -#endif - if (vma->vm_pgoff > (~0UL >> PAGE_SHIFT)) { return -EINVAL; } @@ -1460,10 +1427,6 @@ static int au1200fb_ioctl(struct fb_info *info, unsigned int cmd, int plane; int val; -#ifdef CONFIG_PM - au1xxx_pm_access(LCD_pm_dev); -#endif - plane = fbinfo2index(info); print_dbg("au1200fb: ioctl %d on plane %d\n", cmd, plane); @@ -1622,14 +1585,14 @@ static int au1200fb_init_fbinfo(struct au1200fb_device *fbdev) /* AU1200 LCD controller device driver */ -static int au1200fb_drv_probe(struct device *dev) +static int au1200fb_drv_probe(struct platform_device *pdev) { struct au1200fb_device *fbdev; unsigned long page; int bpp, plane, ret; - if (!dev) - return -EINVAL; + /* Kickstart the panel */ + au1200_setpanel(panel); for (plane = 0; plane < CONFIG_FB_AU1200_DEVS; ++plane) { bpp = winbpp(win->w[plane].mode_winctrl1); @@ -1645,7 +1608,7 @@ static int au1200fb_drv_probe(struct device *dev) /* Allocate the framebuffer to the maximum screen size */ fbdev->fb_len = (win->w[plane].xres * win->w[plane].yres * bpp) / 8; - fbdev->fb_mem = dma_alloc_noncoherent(dev, + fbdev->fb_mem = dma_alloc_noncoherent(&pdev->dev, PAGE_ALIGN(fbdev->fb_len), &fbdev->fb_phys, GFP_KERNEL); if (!fbdev->fb_mem) { @@ -1693,7 +1656,7 @@ static int au1200fb_drv_probe(struct device *dev) /* Now hook interrupt too */ if ((ret = request_irq(AU1200_LCD_INT, au1200fb_handle_irq, - IRQF_DISABLED | IRQF_SHARED, "lcd", (void *)dev)) < 0) { + IRQF_DISABLED | IRQF_SHARED, "lcd", (void *)pdev)) < 0) { print_err("fail to request interrupt line %d (err: %d)", AU1200_LCD_INT, ret); goto failed; @@ -1704,25 +1667,22 @@ static int au1200fb_drv_probe(struct device *dev) failed: /* NOTE: This only does the current plane/window that failed; others are still active */ if (fbdev->fb_mem) - dma_free_noncoherent(dev, PAGE_ALIGN(fbdev->fb_len), + dma_free_noncoherent(&pdev->dev, PAGE_ALIGN(fbdev->fb_len), fbdev->fb_mem, fbdev->fb_phys); if (fbdev->fb_info.cmap.len != 0) fb_dealloc_cmap(&fbdev->fb_info.cmap); if (fbdev->fb_info.pseudo_palette) kfree(fbdev->fb_info.pseudo_palette); if (plane == 0) - free_irq(AU1200_LCD_INT, (void*)dev); + free_irq(AU1200_LCD_INT, (void *)pdev); return ret; } -static int au1200fb_drv_remove(struct device *dev) +static int au1200fb_drv_remove(struct platform_device *pdev) { struct au1200fb_device *fbdev; int plane; - if (!dev) - return -ENODEV; - /* Turn off the panel */ au1200_setpanel(NULL); @@ -1733,7 +1693,8 @@ static int au1200fb_drv_remove(struct device *dev) /* Clean up all probe data */ unregister_framebuffer(&fbdev->fb_info); if (fbdev->fb_mem) - dma_free_noncoherent(dev, PAGE_ALIGN(fbdev->fb_len), + dma_free_noncoherent(&pdev->dev, + PAGE_ALIGN(fbdev->fb_len), fbdev->fb_mem, fbdev->fb_phys); if (fbdev->fb_info.cmap.len != 0) fb_dealloc_cmap(&fbdev->fb_info.cmap); @@ -1741,34 +1702,52 @@ static int au1200fb_drv_remove(struct device *dev) kfree(fbdev->fb_info.pseudo_palette); } - free_irq(AU1200_LCD_INT, (void *)dev); + free_irq(AU1200_LCD_INT, (void *)pdev); return 0; } #ifdef CONFIG_PM -static int au1200fb_drv_suspend(struct device *dev, u32 state, u32 level) -{ - /* TODO */ +static int au1200fb_drv_suspend(struct platform_device *pdev, + pm_message_t state) + { + au1200_setpanel(NULL); + + lcd->outmask = 0; + au_sync(); + return 0; } -static int au1200fb_drv_resume(struct device *dev, u32 level) +static int au1200fb_drv_resume(struct platform_device *pdev) { - /* TODO */ + struct au1200fb_device *fbdev; + int i; + + /* Kickstart the panel */ + au1200_setpanel(panel); + + for (i = 0; i < CONFIG_FB_AU1200_DEVS; i++) { + fbdev = &_au1200fb_devices[i]; + au1200fb_fb_set_par(&fbdev->fb_info); + } + return 0; } +#else +#define au1200fb_drv_suspend NULL +#define au1200fb_drv_resume NULL #endif /* CONFIG_PM */ -static struct device_driver au1200fb_driver = { - .name = "au1200-lcd", - .bus = &platform_bus_type, +static struct platform_driver au1200fb_driver = { + .driver = { + .name = "au1200-lcd", + .owner = THIS_MODULE, + }, .probe = au1200fb_drv_probe, .remove = au1200fb_drv_remove, -#ifdef CONFIG_PM .suspend = au1200fb_drv_suspend, .resume = au1200fb_drv_resume, -#endif }; /*-------------------------------------------------------------------------*/ @@ -1831,56 +1810,6 @@ static void au1200fb_setup(void) } } -#ifdef CONFIG_PM -static int au1200fb_pm_callback(au1xxx_power_dev_t *dev, - au1xxx_request_t request, void *data) { - int retval = -1; - unsigned int d = 0; - unsigned int brightness = 0; - - if (request == AU1XXX_PM_SLEEP) { - board_au1200fb_panel_shutdown(); - } - else if (request == AU1XXX_PM_WAKEUP) { - if(dev->prev_state == SLEEP_STATE) - { - int plane; - au1200_setpanel(panel); - for (plane = 0; plane < CONFIG_FB_AU1200_DEVS; ++plane) { - struct au1200fb_device *fbdev; - fbdev = &_au1200fb_devices[plane]; - au1200fb_fb_set_par(&fbdev->fb_info); - } - } - - d = *((unsigned int*)data); - if(d <=10) brightness = 26; - else if(d<=20) brightness = 51; - else if(d<=30) brightness = 77; - else if(d<=40) brightness = 102; - else if(d<=50) brightness = 128; - else if(d<=60) brightness = 153; - else if(d<=70) brightness = 179; - else if(d<=80) brightness = 204; - else if(d<=90) brightness = 230; - else brightness = 255; - set_brightness(brightness); - } else if (request == AU1XXX_PM_GETSTATUS) { - return dev->cur_state; - } else if (request == AU1XXX_PM_ACCESS) { - if (dev->cur_state != SLEEP_STATE) - return retval; - else { - au1200_setpanel(panel); - } - } else if (request == AU1XXX_PM_IDLE) { - } else if (request == AU1XXX_PM_CLEANUP) { - } - - return retval; -} -#endif - static int __init au1200fb_init(void) { print_info("" DRIVER_DESC ""); @@ -1895,23 +1824,12 @@ static int __init au1200fb_init(void) printk(DRIVER_NAME ": Panel %d %s\n", panel_index, panel->name); printk(DRIVER_NAME ": Win %d %s\n", window_index, win->name); - /* Kickstart the panel, the framebuffers/windows come soon enough */ - au1200_setpanel(panel); - - #ifdef CONFIG_PM - LCD_pm_dev = new_au1xxx_power_device("LCD", &au1200fb_pm_callback, NULL); - if ( LCD_pm_dev == NULL) - printk(KERN_INFO "Unable to create a power management device entry for the au1200fb.\n"); - else - printk(KERN_INFO "Power management device entry for the au1200fb loaded.\n"); - #endif - - return driver_register(&au1200fb_driver); + return platform_driver_register(&au1200fb_driver); } static void __exit au1200fb_cleanup(void) { - driver_unregister(&au1200fb_driver); + platform_driver_unregister(&au1200fb_driver); } module_init(au1200fb_init); -- 1.5.6.4 From mano@roarinelk.homelinux.net Tue Aug 5 13:45:25 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 05 Aug 2008 13:45:31 +0100 (BST) Received: from fnoeppeil43.netpark.at ([217.175.205.171]:58527 "EHLO roarinelk.homelinux.net") by ftp.linux-mips.org with ESMTP id S20021808AbYHEMpZ (ORCPT ); Tue, 5 Aug 2008 13:45:25 +0100 Received: (qmail 27546 invoked by uid 1000); 5 Aug 2008 14:45:22 +0200 Date: Tue, 5 Aug 2008 14:45:22 +0200 From: Manuel Lauss To: linux-fbdev-devel@lists.sf.net Cc: Kevin Hickey , L-M-O Subject: [PATCH] au1200fb: make framebuffer config runtime selectable. Message-ID: <20080805124522.GB27469@roarinelk.homelinux.net> References: <20080805124221.GA27469@roarinelk.homelinux.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20080805124221.GA27469@roarinelk.homelinux.net> User-Agent: Mutt/1.5.16 (2007-06-09) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20102 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mano@roarinelk.homelinux.net Precedence: bulk X-list: linux-mips Make the number of framebuffer windows and the window configuration selectable at the kernel commandline instead of hardcoding it in the kernel config. This patch does not directly depend on the previous one ("au1200fb: fixup PM support"), but it only applies cleanly on top of it. Signed-off-by: Manuel Lauss --- drivers/video/au1200fb.c | 55 ++++++++++++++++++++++++++++++++++----------- 1 files changed, 41 insertions(+), 14 deletions(-) diff --git a/drivers/video/au1200fb.c b/drivers/video/au1200fb.c index be945ab..7127aa7 100644 --- a/drivers/video/au1200fb.c +++ b/drivers/video/au1200fb.c @@ -45,10 +45,6 @@ #include #include "au1200fb.h" -#ifndef CONFIG_FB_AU1200_DEVS -#define CONFIG_FB_AU1200_DEVS 4 -#endif - #define DRIVER_NAME "au1200fb" #define DRIVER_DESC "LCD controller driver for AU1200 processors" @@ -153,7 +149,7 @@ struct au1200fb_device { dma_addr_t fb_phys; }; -static struct au1200fb_device _au1200fb_devices[CONFIG_FB_AU1200_DEVS]; +static struct au1200fb_device _au1200fb_devices[4]; /********************************************************************/ /* LCD controller restrictions */ @@ -166,10 +162,17 @@ static struct au1200fb_device _au1200fb_devices[CONFIG_FB_AU1200_DEVS]; /* Default number of visible screen buffer to allocate */ #define AU1200FB_NBR_VIDEO_BUFFERS 1 +/* Default number of fb devices to create */ +#define DEFAULT_DEVICE_COUNT 4 + +/* Default window configuration entry to use (see windows[]) */ +#define DEFAULT_WINDOW_INDEX 2 + /********************************************************************/ static struct au1200_lcd *lcd = (struct au1200_lcd *) AU1200_LCD_ADDR; -static int window_index = 2; /* default is zero */ +static int device_count = DEFAULT_DEVICE_COUNT; /* number of fb devices to create */ +static int window_index = DEFAULT_WINDOW_INDEX; /* default is zero */ static int panel_index = 2; /* default is zero */ static struct window_settings *win; static struct panel_settings *panel; @@ -682,7 +685,7 @@ static int fbinfo2index (struct fb_info *fb_info) { int i; - for (i = 0; i < CONFIG_FB_AU1200_DEVS; ++i) { + for (i = 0; i < device_count; ++i) { if (fb_info == (struct fb_info *)(&_au1200fb_devices[i].fb_info)) return i; } @@ -1594,7 +1597,7 @@ static int au1200fb_drv_probe(struct platform_device *pdev) /* Kickstart the panel */ au1200_setpanel(panel); - for (plane = 0; plane < CONFIG_FB_AU1200_DEVS; ++plane) { + for (plane = 0; plane < device_count; ++plane) { bpp = winbpp(win->w[plane].mode_winctrl1); if (win->w[plane].xres == 0) win->w[plane].xres = panel->Xres; @@ -1686,7 +1689,7 @@ static int au1200fb_drv_remove(struct platform_device *pdev) /* Turn off the panel */ au1200_setpanel(NULL); - for (plane = 0; plane < CONFIG_FB_AU1200_DEVS; ++plane) + for (plane = 0; plane < device_count; ++plane) { fbdev = &_au1200fb_devices[plane]; @@ -1727,7 +1730,7 @@ static int au1200fb_drv_resume(struct platform_device *pdev) /* Kickstart the panel */ au1200_setpanel(panel); - for (i = 0; i < CONFIG_FB_AU1200_DEVS; i++) { + for (i = 0; i < device_count; i++) { fbdev = &_au1200fb_devices[i]; au1200fb_fb_set_par(&fbdev->fb_info); } @@ -1754,10 +1757,10 @@ static struct platform_driver au1200fb_driver = { /* Kernel driver */ -static void au1200fb_setup(void) +static int au1200fb_setup(void) { - char* options = NULL; - char* this_opt; + char *options = NULL; + char *this_opt, *endptr; int num_panels = ARRAY_SIZE(known_lcd_panels); int panel_idx = -1; @@ -1802,12 +1805,29 @@ static void au1200fb_setup(void) nohwcursor = 1; } + else if (strncmp(this_opt, "devices:", 8) == 0) { + this_opt += 8; + device_count = simple_strtol(this_opt, &endptr, 0); + if ((device_count < 0) || (device_count > 4)) + device_count = DEFAULT_DEVICE_COUNT; + } + + else if (strncmp(this_opt, "wincfg:", 7) == 0) { + this_opt += 7; + window_index = simple_strtol(this_opt, &endptr, 0); + if ((window_index < 0) || (window_index >= ARRAY_SIZE(windows))) + window_index = DEFAULT_WINDOW_INDEX; + } + + else if (strncmp(this_opt, "off", 3) == 0) + return 1; /* Unsupported option */ else { print_warn("Unsupported option \"%s\"", this_opt); } } } + return 0; } static int __init au1200fb_init(void) @@ -1815,7 +1835,14 @@ static int __init au1200fb_init(void) print_info("" DRIVER_DESC ""); /* Setup driver with options */ - au1200fb_setup(); + if (au1200fb_setup()) + return -ENODEV; + + if ((device_count < 0) || (device_count > 4)) + device_count = DEFAULT_DEVICE_COUNT; + + if ((window_index < 0) || (window_index >= ARRAY_SIZE(windows))) + window_index = DEFAULT_WINDOW_INDEX; /* Point to the panel selected */ panel = &known_lcd_panels[panel_index]; -- 1.5.6.4 From lists@nabble.com Tue Aug 5 14:10:10 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 05 Aug 2008 14:10:16 +0100 (BST) Received: from kuber.nabble.com ([216.139.236.158]:38124 "EHLO kuber.nabble.com") by ftp.linux-mips.org with ESMTP id S20023701AbYHENKK (ORCPT ); Tue, 5 Aug 2008 14:10:10 +0100 Received: from isper.nabble.com ([192.168.236.156]) by kuber.nabble.com with esmtp (Exim 4.63) (envelope-from ) id 1KQMIi-0006cn-Gd for linux-mips@linux-mips.org; Tue, 05 Aug 2008 06:10:08 -0700 Message-ID: <18830812.post@talk.nabble.com> Date: Tue, 5 Aug 2008 06:10:08 -0700 (PDT) From: TriKri To: linux-mips@linux-mips.org Subject: Debugging MIPS cpu with a probe, how? MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Nabble-From: kristoferkrus@hotmail.com Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20103 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: kristoferkrus@hotmail.com Precedence: bulk X-list: linux-mips Hello! I have an embedded system, a box, with a MIPS processor on it, which I need to debug (stop and start the processor, tell what instructions it has previously executed, etc.). I also have an EJTAG probe, which I have connected between the computer's usb and the box, and written software for it. The software can communicate with the probe, which in its own turn can communicate with the box through the tap (test access port), by giving the tap certain instructions. It can also, through the tap, feed the MIPS processor with instructions, and read/write data from processor registers. The question is now, how can debug the processor? How do I stop it, do I have to send any certain instructions to it? How can I set a breakpoint (which I understand is a quite crucial point)? Can I use GDB with my software to help debug the processor and how do I do that? Thank you in advance! /Kristofer Krus -- View this message in context: http://www.nabble.com/Debugging-MIPS-cpu-with-a-probe%2C-how--tp18830812p18830812.html Sent from the linux-mips main mailing list archive at Nabble.com. From anemo@mba.ocn.ne.jp Tue Aug 5 15:45:21 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 05 Aug 2008 15:45:27 +0100 (BST) Received: from mba.ocn.ne.jp ([122.1.235.107]:51411 "HELO smtp.mba.ocn.ne.jp") by ftp.linux-mips.org with SMTP id S20021374AbYHEOpV (ORCPT ); Tue, 5 Aug 2008 15:45:21 +0100 Received: from localhost (p2220-ipad303funabasi.chiba.ocn.ne.jp [123.217.148.220]) by smtp.mba.ocn.ne.jp (Postfix) with ESMTP id A2E70A9FF; Tue, 5 Aug 2008 23:45:13 +0900 (JST) Date: Tue, 05 Aug 2008 23:45:14 +0900 (JST) Message-Id: <20080805.234514.39153536.anemo@mba.ocn.ne.jp> To: linux-mips@linux-mips.org Cc: ralf@linux-mips.org Subject: [PATCH] vmlinux.lds.S: handle .text.* From: Atsushi Nemoto X-Fingerprint: 6ACA 1623 39BD 9A94 9B1A B746 CA77 FE94 2874 D52F X-Pgp-Public-Key: http://wwwkeys.pgp.net/pks/lookup?op=get&search=0x2874D52F X-Mailer: Mew version 5.2 on Emacs 21.4 / Mule 5.0 (SAKAKI) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20104 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anemo@mba.ocn.ne.jp Precedence: bulk X-list: linux-mips The -ffunction-sections puts each text in .text.function_name section. Without this patch, most functions are placed outside _text..._etext area and it breaks show_stacktrace(), etc. Signed-off-by: Atsushi Nemoto --- diff --git a/arch/mips/kernel/vmlinux.lds.S b/arch/mips/kernel/vmlinux.lds.S index b5470ce..afb119f 100644 --- a/arch/mips/kernel/vmlinux.lds.S +++ b/arch/mips/kernel/vmlinux.lds.S @@ -36,6 +36,7 @@ SECTIONS SCHED_TEXT LOCK_TEXT KPROBES_TEXT + *(.text.*) *(.fixup) *(.gnu.warning) } :text = 0 From krzysztof.h1@poczta.fm Tue Aug 5 16:16:38 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 05 Aug 2008 16:16:44 +0100 (BST) Received: from smtp239.poczta.interia.pl ([217.74.64.239]:56378 "EHLO smtp239.poczta.interia.pl") by ftp.linux-mips.org with ESMTP id S20022355AbYHEPQi (ORCPT ); Tue, 5 Aug 2008 16:16:38 +0100 Received: by smtp239.poczta.interia.pl (INTERIA.PL, from userid 502) id E65DD296F7E; Tue, 5 Aug 2008 17:16:35 +0200 (CEST) Received: from poczta.interia.pl (mi06.poczta.interia.pl [10.217.12.6]) by smtp239.poczta.interia.pl (INTERIA.PL) with ESMTP id EFEE6296462; Tue, 5 Aug 2008 17:16:32 +0200 (CEST) Received: by poczta.interia.pl (INTERIA.PL, from userid 502) id AC7D51324F9; Tue, 5 Aug 2008 17:16:32 +0200 (CEST) Received: from krzysio.net (host-87-99-61-239.lanet.net.pl [87.99.61.239]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by www.poczta.fm (INTERIA.PL) with ESMTP id 2147B1324E4; Tue, 5 Aug 2008 17:16:27 +0200 (CEST) Date: Tue, 5 Aug 2008 17:22:00 +0200 From: Krzysztof Helt To: Manuel Lauss Cc: linux-fbdev-devel@lists.sf.net, L-M-O , Kevin Hickey Subject: Re: [Linux-fbdev-devel] [PATCH] au1200fb: fixup PM support. Message-Id: <20080805172200.4f52ca12.krzysztof.h1@poczta.fm> In-Reply-To: <20080805124221.GA27469@roarinelk.homelinux.net> References: <20080805124221.GA27469@roarinelk.homelinux.net> X-Mailer: Sylpheed 2.4.3 (GTK+ 2.11.0; i686-pc-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-EMID: 8ce2b138 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20105 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: krzysztof.h1@poczta.fm Precedence: bulk X-list: linux-mips On Tue, 5 Aug 2008 14:42:21 +0200 Manuel Lauss wrote: > Remove last traces of the custom Alchemy linux-2.4 PM code, implement > suspend/resume callbacks. > > Signed-off-by: Manuel Lauss > --- > drivers/video/au1200fb.c | 164 ++++++++++++---------------------------------- > 1 files changed, 41 insertions(+), 123 deletions(-) > Acked-by: Krzysztof Helt If you don't want to push this patch through the mips tree you may post this patch to Andrew Morton with my acked-by. Regards, Krzysztof ---------------------------------------------------------------------- Te newsy nakreca Cie na caly dzien! Sprawdz >>> http://link.interia.pl/f1e94 From krzysztof.h1@poczta.fm Tue Aug 5 16:20:22 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 05 Aug 2008 16:20:28 +0100 (BST) Received: from smtp239.poczta.interia.pl ([217.74.64.239]:36020 "EHLO smtp239.poczta.interia.pl") by ftp.linux-mips.org with ESMTP id S20022262AbYHEPUW (ORCPT ); Tue, 5 Aug 2008 16:20:22 +0100 Received: by smtp239.poczta.interia.pl (INTERIA.PL, from userid 502) id 535EB296B48; Tue, 5 Aug 2008 17:20:21 +0200 (CEST) Received: from poczta.interia.pl (mi02.poczta.interia.pl [10.217.12.2]) by smtp239.poczta.interia.pl (INTERIA.PL) with ESMTP id 9495129645E; Tue, 5 Aug 2008 17:20:20 +0200 (CEST) Received: by poczta.interia.pl (INTERIA.PL, from userid 502) id 90BA62BC175; Tue, 5 Aug 2008 17:20:20 +0200 (CEST) Received: from krzysio.net (host-87-99-61-239.lanet.net.pl [87.99.61.239]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by www.poczta.fm (INTERIA.PL) with ESMTP id 0CF7C2BC150; Tue, 5 Aug 2008 17:20:14 +0200 (CEST) Date: Tue, 5 Aug 2008 17:25:47 +0200 From: Krzysztof Helt To: Manuel Lauss Cc: linux-fbdev-devel@lists.sf.net, L-M-O , Kevin Hickey Subject: Re: [Linux-fbdev-devel] [PATCH] au1200fb: make framebuffer config runtime selectable. Message-Id: <20080805172547.e81c35d3.krzysztof.h1@poczta.fm> In-Reply-To: <20080805124522.GB27469@roarinelk.homelinux.net> References: <20080805124221.GA27469@roarinelk.homelinux.net> <20080805124522.GB27469@roarinelk.homelinux.net> X-Mailer: Sylpheed 2.4.3 (GTK+ 2.11.0; i686-pc-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-EMID: 5ae2b138 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20106 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: krzysztof.h1@poczta.fm Precedence: bulk X-list: linux-mips On Tue, 5 Aug 2008 14:45:22 +0200 Manuel Lauss wrote: > Make the number of framebuffer windows and the window configuration > selectable at the kernel commandline instead of hardcoding it > in the kernel config. > > This patch does not directly depend on the previous one ("au1200fb: fixup PM > support"), but it only applies cleanly on top of it. > > Signed-off-by: Manuel Lauss > --- > drivers/video/au1200fb.c | 55 ++++++++++++++++++++++++++++++++++----------- > 1 files changed, 41 insertions(+), 14 deletions(-) > > diff --git a/drivers/video/au1200fb.c b/drivers/video/au1200fb.c > index be945ab..7127aa7 100644 > --- a/drivers/video/au1200fb.c > +++ b/drivers/video/au1200fb.c > @@ -45,10 +45,6 @@ > #include > #include "au1200fb.h" > > -#ifndef CONFIG_FB_AU1200_DEVS > -#define CONFIG_FB_AU1200_DEVS 4 > -#endif > - > #define DRIVER_NAME "au1200fb" > #define DRIVER_DESC "LCD controller driver for AU1200 processors" > > @@ -153,7 +149,7 @@ struct au1200fb_device { > dma_addr_t fb_phys; > }; > > -static struct au1200fb_device _au1200fb_devices[CONFIG_FB_AU1200_DEVS]; > +static struct au1200fb_device _au1200fb_devices[4]; Please use the constant here. > /********************************************************************/ > > /* LCD controller restrictions */ > @@ -166,10 +162,17 @@ static struct au1200fb_device _au1200fb_devices[CONFIG_FB_AU1200_DEVS]; > /* Default number of visible screen buffer to allocate */ > #define AU1200FB_NBR_VIDEO_BUFFERS 1 > > +/* Default number of fb devices to create */ > +#define DEFAULT_DEVICE_COUNT 4 > + This one can be renamed to MAX_DEVICE_COUNT and used in the declaration above and various checks. There is nothing wrong with the default value being the maximum value. > +/* Default window configuration entry to use (see windows[]) */ > +#define DEFAULT_WINDOW_INDEX 2 > + > /********************************************************************/ > > static struct au1200_lcd *lcd = (struct au1200_lcd *) AU1200_LCD_ADDR; > -static int window_index = 2; /* default is zero */ > +static int device_count = DEFAULT_DEVICE_COUNT; /* number of fb devices to create */ > +static int window_index = DEFAULT_WINDOW_INDEX; /* default is zero */ > static int panel_index = 2; /* default is zero */ > static struct window_settings *win; > static struct panel_settings *panel; > @@ -682,7 +685,7 @@ static int fbinfo2index (struct fb_info *fb_info) > { > int i; > > - for (i = 0; i < CONFIG_FB_AU1200_DEVS; ++i) { > + for (i = 0; i < device_count; ++i) { > if (fb_info == (struct fb_info *)(&_au1200fb_devices[i].fb_info)) > return i; > } > @@ -1594,7 +1597,7 @@ static int au1200fb_drv_probe(struct platform_device *pdev) > /* Kickstart the panel */ > au1200_setpanel(panel); > > - for (plane = 0; plane < CONFIG_FB_AU1200_DEVS; ++plane) { > + for (plane = 0; plane < device_count; ++plane) { > bpp = winbpp(win->w[plane].mode_winctrl1); > if (win->w[plane].xres == 0) > win->w[plane].xres = panel->Xres; > @@ -1686,7 +1689,7 @@ static int au1200fb_drv_remove(struct platform_device *pdev) > /* Turn off the panel */ > au1200_setpanel(NULL); > > - for (plane = 0; plane < CONFIG_FB_AU1200_DEVS; ++plane) > + for (plane = 0; plane < device_count; ++plane) > { > fbdev = &_au1200fb_devices[plane]; > > @@ -1727,7 +1730,7 @@ static int au1200fb_drv_resume(struct platform_device *pdev) > /* Kickstart the panel */ > au1200_setpanel(panel); > > - for (i = 0; i < CONFIG_FB_AU1200_DEVS; i++) { > + for (i = 0; i < device_count; i++) { > fbdev = &_au1200fb_devices[i]; > au1200fb_fb_set_par(&fbdev->fb_info); > } > @@ -1754,10 +1757,10 @@ static struct platform_driver au1200fb_driver = { > > /* Kernel driver */ > > -static void au1200fb_setup(void) > +static int au1200fb_setup(void) > { > - char* options = NULL; > - char* this_opt; > + char *options = NULL; > + char *this_opt, *endptr; > int num_panels = ARRAY_SIZE(known_lcd_panels); > int panel_idx = -1; > > @@ -1802,12 +1805,29 @@ static void au1200fb_setup(void) > nohwcursor = 1; > } > > + else if (strncmp(this_opt, "devices:", 8) == 0) { > + this_opt += 8; > + device_count = simple_strtol(this_opt, &endptr, 0); > + if ((device_count < 0) || (device_count > 4)) > + device_count = DEFAULT_DEVICE_COUNT; > + } > + > + else if (strncmp(this_opt, "wincfg:", 7) == 0) { > + this_opt += 7; > + window_index = simple_strtol(this_opt, &endptr, 0); > + if ((window_index < 0) || (window_index >= ARRAY_SIZE(windows))) > + window_index = DEFAULT_WINDOW_INDEX; > + } > + > + else if (strncmp(this_opt, "off", 3) == 0) > + return 1; > /* Unsupported option */ > else { > print_warn("Unsupported option \"%s\"", this_opt); > } > } > } > + return 0; > } > > static int __init au1200fb_init(void) > @@ -1815,7 +1835,14 @@ static int __init au1200fb_init(void) > print_info("" DRIVER_DESC ""); > > /* Setup driver with options */ > - au1200fb_setup(); > + if (au1200fb_setup()) > + return -ENODEV; > + > + if ((device_count < 0) || (device_count > 4)) > + device_count = DEFAULT_DEVICE_COUNT; > + The au1200fb_setup does this check before so it is not needed to repeat it. The patch looks fine otherwise. Kind regards, Krzysztof ---------------------------------------------------------------------- Te newsy nakreca Cie na caly dzien! Sprawdz >>> http://link.interia.pl/f1e94 From sfr@canb.auug.org.au Tue Aug 5 16:24:10 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 05 Aug 2008 16:24:15 +0100 (BST) Received: from chilli.pcug.org.au ([203.10.76.44]:11708 "EHLO smtps.tip.net.au") by ftp.linux-mips.org with ESMTP id S20021987AbYHEPYK (ORCPT ); Tue, 5 Aug 2008 16:24:10 +0100 Received: from ash.ozlabs.ibm.com (ta-1-1.tip.net.au [203.11.71.1]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by smtps.tip.net.au (Postfix) with ESMTP id A8A7436800E; Wed, 6 Aug 2008 01:24:03 +1000 (EST) Date: Wed, 6 Aug 2008 01:23:57 +1000 From: Stephen Rothwell To: Mauro Carvalho Chehab Cc: LKML , v4l-dvb-maintainer@linuxtv.org, video4linux-list@redhat.com, Ralf Baechle , linux-mips@linux-mips.org Subject: v4l/mips build problem Message-Id: <20080806012357.55625daf.sfr@canb.auug.org.au> X-Mailer: Sylpheed 2.5.0 (GTK+ 2.12.11; i486-pc-linux-gnu) Mime-Version: 1.0 Content-Type: multipart/signed; protocol="application/pgp-signature"; micalg="PGP-SHA1"; boundary="Signature=_Wed__6_Aug_2008_01_23_57_+1000_i2JVJ6yLmX47_gw6" Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20107 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sfr@canb.auug.org.au Precedence: bulk X-list: linux-mips --Signature=_Wed__6_Aug_2008_01_23_57_+1000_i2JVJ6yLmX47_gw6 Content-Type: text/plain; charset=US-ASCII Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Hi all, Linus' current tree gets the following error during a mips allmodconfig build: drivers/media/video/vino.c:4364: error: implicit declaration of function `v= ideo_usercopy' --=20 Cheers, Stephen Rothwell sfr@canb.auug.org.au http://www.canb.auug.org.au/~sfr/ --Signature=_Wed__6_Aug_2008_01_23_57_+1000_i2JVJ6yLmX47_gw6 Content-Type: application/pgp-signature -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.9 (GNU/Linux) iEUEARECAAYFAkiYcI0ACgkQjjKRsyhoI8wamgCgkcSKgbNYkPosFeczVlj/wZ4I GQsAl3J1/Z+woSBs6uTe8k2rPPfAD+0= =HFni -----END PGP SIGNATURE----- --Signature=_Wed__6_Aug_2008_01_23_57_+1000_i2JVJ6yLmX47_gw6-- From bunk@kernel.org Tue Aug 5 16:42:47 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 05 Aug 2008 16:42:54 +0100 (BST) Received: from smtp6.pp.htv.fi ([213.243.153.40]:9884 "EHLO smtp6.pp.htv.fi") by ftp.linux-mips.org with ESMTP id S20032155AbYHEPmr (ORCPT ); Tue, 5 Aug 2008 16:42:47 +0100 Received: from cs181140183.pp.htv.fi (cs181140183.pp.htv.fi [82.181.140.183]) by smtp6.pp.htv.fi (Postfix) with ESMTP id 8A61B5BC023; Tue, 5 Aug 2008 18:42:44 +0300 (EEST) Date: Tue, 5 Aug 2008 18:41:22 +0300 From: Adrian Bunk To: Stephen Rothwell Cc: Mauro Carvalho Chehab , LKML , v4l-dvb-maintainer@linuxtv.org, video4linux-list@redhat.com, Ralf Baechle , linux-mips@linux-mips.org, Andrew Morton Subject: Re: v4l/mips build problem Message-ID: <20080805154122.GC22895@cs181140183.pp.htv.fi> References: <20080806012357.55625daf.sfr@canb.auug.org.au> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <20080806012357.55625daf.sfr@canb.auug.org.au> User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20108 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: bunk@kernel.org Precedence: bulk X-list: linux-mips On Wed, Aug 06, 2008 at 01:23:57AM +1000, Stephen Rothwell wrote: > Hi all, > > Linus' current tree gets the following error during a mips allmodconfig > build: > > drivers/media/video/vino.c:4364: error: implicit declaration of function `video_usercopy' Andrew fixed it with drivers-media-video-vinoc-needs-v4l2-ioctlh.patch in -mm. cu Adrian -- "Is there not promise of rain?" Ling Tan asked suddenly out of the darkness. There had been need of rain for many days. "Only a promise," Lao Er said. Pearl S. Buck - Dragon Seed From khickey@rmicorp.com Tue Aug 5 17:02:05 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 05 Aug 2008 17:02:12 +0100 (BST) Received: from mx1.razamicroelectronics.com ([63.111.213.197]:55630 "EHLO hq-ex-mb01.razamicroelectronics.com") by ftp.linux-mips.org with ESMTP id S20023932AbYHEQCF convert rfc822-to-8bit (ORCPT ); Tue, 5 Aug 2008 17:02:05 +0100 Received: from 10.8.0.25 ([10.8.0.25]) by hq-ex-mb01.razamicroelectronics.com ([10.1.1.40]) via Exchange Front-End Server webmail.razamicroelectronics.com ([10.1.1.41]) with Microsoft Exchange Server HTTP-DAV ; Tue, 5 Aug 2008 16:01:57 +0000 Received: from kh-ubuntu by webmail.razamicroelectronics.com; 05 Aug 2008 11:02:17 -0500 Subject: Re: [PATCH] au1200fb: fixup PM support. From: Kevin Hickey To: Manuel Lauss Cc: linux-fbdev-devel@lists.sf.net, L-M-O In-Reply-To: <20080805124221.GA27469@roarinelk.homelinux.net> References: <20080805124221.GA27469@roarinelk.homelinux.net> Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8BIT Date: Tue, 05 Aug 2008 11:02:17 -0500 Message-Id: <1217952137.23188.2.camel@kh-ubuntu.razamicroelectronics.com> Mime-Version: 1.0 X-Mailer: Evolution 2.22.3.1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20109 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: khickey@rmicorp.com Precedence: bulk X-list: linux-mips On Tue, 2008-08-05 at 14:42 +0200, Manuel Lauss wrote: > Remove last traces of the custom Alchemy linux-2.4 PM code, implement > suspend/resume callbacks. > > Signed-off-by: Manuel Lauss > --- > drivers/video/au1200fb.c | 164 ++++++++++++---------------------------------- > 1 files changed, 41 insertions(+), 123 deletions(-) > This looks good. It applied to my tree and appears functional on my board. One question: what about dynamic brightness? It was part of the old PM interface and you seem to have removed it. Any ideas about re-integrating that into the current PM model? Acked-by: Kevin Hickey -- Kevin Hickey Alchemy Solutions RMI Corporation khickey@RMICorp.com P: 512.691.8044 From sfr@canb.auug.org.au Tue Aug 5 17:06:58 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 05 Aug 2008 17:07:06 +0100 (BST) Received: from chilli.pcug.org.au ([203.10.76.44]:11477 "EHLO smtps.tip.net.au") by ftp.linux-mips.org with ESMTP id S20022066AbYHEQG6 (ORCPT ); Tue, 5 Aug 2008 17:06:58 +0100 Received: from ash.ozlabs.ibm.com (ta-1-1.tip.net.au [203.11.71.1]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by smtps.tip.net.au (Postfix) with ESMTP id CD2D7368003; Wed, 6 Aug 2008 02:06:52 +1000 (EST) Date: Wed, 6 Aug 2008 02:06:47 +1000 From: Stephen Rothwell To: Adrian Bunk Cc: Mauro Carvalho Chehab , LKML , v4l-dvb-maintainer@linuxtv.org, video4linux-list@redhat.com, Ralf Baechle , linux-mips@linux-mips.org, Andrew Morton Subject: Re: v4l/mips build problem Message-Id: <20080806020647.2cf11a2b.sfr@canb.auug.org.au> In-Reply-To: <20080805154122.GC22895@cs181140183.pp.htv.fi> References: <20080806012357.55625daf.sfr@canb.auug.org.au> <20080805154122.GC22895@cs181140183.pp.htv.fi> X-Mailer: Sylpheed 2.5.0 (GTK+ 2.12.11; i486-pc-linux-gnu) Mime-Version: 1.0 Content-Type: multipart/signed; protocol="application/pgp-signature"; micalg="PGP-SHA1"; boundary="Signature=_Wed__6_Aug_2008_02_06_47_+1000_hXNUOzlXW0oxCw40" Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20110 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sfr@canb.auug.org.au Precedence: bulk X-list: linux-mips --Signature=_Wed__6_Aug_2008_02_06_47_+1000_hXNUOzlXW0oxCw40 Content-Type: text/plain; charset=US-ASCII Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Tue, 5 Aug 2008 18:41:22 +0300 Adrian Bunk wrote: > > On Wed, Aug 06, 2008 at 01:23:57AM +1000, Stephen Rothwell wrote: > > Hi all, > >=20 > > Linus' current tree gets the following error during a mips allmodconfig > > build: > >=20 > > drivers/media/video/vino.c:4364: error: implicit declaration of functio= n `video_usercopy' >=20 > Andrew fixed it with drivers-media-video-vinoc-needs-v4l2-ioctlh.patch=20 > in -mm. Maybe we should send that one Linusward ... --=20 Cheers, Stephen Rothwell sfr@canb.auug.org.au http://www.canb.auug.org.au/~sfr/ --Signature=_Wed__6_Aug_2008_02_06_47_+1000_hXNUOzlXW0oxCw40 Content-Type: application/pgp-signature -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.9 (GNU/Linux) iEYEARECAAYFAkiYepcACgkQjjKRsyhoI8wMRgCggFHLNyfoQrKrKjpkSIGfIEcX F1oAoIERan3FacdwFgwxh5JPDSswWwkm =olAO -----END PGP SIGNATURE----- --Signature=_Wed__6_Aug_2008_02_06_47_+1000_hXNUOzlXW0oxCw40-- From mano@roarinelk.homelinux.net Tue Aug 5 17:08:43 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 05 Aug 2008 17:08:50 +0100 (BST) Received: from fnoeppeil43.netpark.at ([217.175.205.171]:48296 "EHLO roarinelk.homelinux.net") by ftp.linux-mips.org with ESMTP id S20021987AbYHEQIn (ORCPT ); Tue, 5 Aug 2008 17:08:43 +0100 Received: (qmail 28927 invoked from network); 5 Aug 2008 18:08:39 +0200 Received: from flagship.roarinelk.net (HELO ?192.168.0.197?) (192.168.0.197) by fnoeppeil43.netpark.at with SMTP; 5 Aug 2008 18:08:39 +0200 Message-ID: <48987B07.80502@roarinelk.homelinux.net> Date: Tue, 05 Aug 2008 18:08:39 +0200 From: Manuel Lauss Organization: Private User-Agent: Thunderbird 2.0.0.16 (X11/20080726) MIME-Version: 1.0 To: Kevin Hickey CC: linux-fbdev-devel@lists.sf.net, L-M-O Subject: Re: [PATCH] au1200fb: fixup PM support. References: <20080805124221.GA27469@roarinelk.homelinux.net> <1217952137.23188.2.camel@kh-ubuntu.razamicroelectronics.com> In-Reply-To: <1217952137.23188.2.camel@kh-ubuntu.razamicroelectronics.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20111 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mano@roarinelk.homelinux.net Precedence: bulk X-list: linux-mips Kevin Hickey wrote: > On Tue, 2008-08-05 at 14:42 +0200, Manuel Lauss wrote: >> Remove last traces of the custom Alchemy linux-2.4 PM code, implement >> suspend/resume callbacks. >> >> Signed-off-by: Manuel Lauss >> --- >> drivers/video/au1200fb.c | 164 ++++++++++++---------------------------------- >> 1 files changed, 41 insertions(+), 123 deletions(-) >> > This looks good. It applied to my tree and appears functional on my > board. One question: what about dynamic brightness? It was part of the > old PM interface and you seem to have removed it. Any ideas about > re-integrating that into the current PM model? Hm, good point. Let me see if I can hook the 2 PWMs into the backlight framework somehow... I'll repost once this works. > Acked-by: Kevin Hickey MfG, Manuel Lauss From akpm@linux-foundation.org Tue Aug 5 17:27:56 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 05 Aug 2008 17:28:03 +0100 (BST) Received: from smtp1.linux-foundation.org ([140.211.169.13]:64236 "EHLO smtp1.linux-foundation.org") by ftp.linux-mips.org with ESMTP id S20024580AbYHEQ14 (ORCPT ); Tue, 5 Aug 2008 17:27:56 +0100 Received: from imap1.linux-foundation.org (imap1.linux-foundation.org [140.211.169.55]) by smtp1.linux-foundation.org (8.14.2/8.13.5/Debian-3ubuntu1.1) with ESMTP id m75GQqZ2016897 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Tue, 5 Aug 2008 09:26:53 -0700 Received: from y.localdomain (localhost [127.0.0.1]) by imap1.linux-foundation.org (8.13.5.20060308/8.13.5/Debian-3ubuntu1.1) with SMTP id m75GQoOg011805; Tue, 5 Aug 2008 09:26:50 -0700 Date: Tue, 5 Aug 2008 09:26:50 -0700 From: Andrew Morton To: Stephen Rothwell Cc: Adrian Bunk , Mauro Carvalho Chehab , LKML , v4l-dvb-maintainer@linuxtv.org, video4linux-list@redhat.com, Ralf Baechle , linux-mips@linux-mips.org Subject: Re: v4l/mips build problem Message-Id: <20080805092650.af88364a.akpm@linux-foundation.org> In-Reply-To: <20080806020647.2cf11a2b.sfr@canb.auug.org.au> References: <20080806012357.55625daf.sfr@canb.auug.org.au> <20080805154122.GC22895@cs181140183.pp.htv.fi> <20080806020647.2cf11a2b.sfr@canb.auug.org.au> X-Mailer: Sylpheed 2.4.8 (GTK+ 2.12.5; x86_64-redhat-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-MIMEDefang-Filter: lf$Revision: 1.188 $ X-Scanned-By: MIMEDefang 2.63 on 140.211.169.13 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20112 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: akpm@linux-foundation.org Precedence: bulk X-list: linux-mips On Wed, 6 Aug 2008 02:06:47 +1000 Stephen Rothwell wrote: > On Tue, 5 Aug 2008 18:41:22 +0300 Adrian Bunk wrote: > > > > On Wed, Aug 06, 2008 at 01:23:57AM +1000, Stephen Rothwell wrote: > > > Hi all, > > > > > > Linus' current tree gets the following error during a mips allmodconfig > > > build: > > > > > > drivers/media/video/vino.c:4364: error: implicit declaration of function `video_usercopy' > > > > Andrew fixed it with drivers-media-video-vinoc-needs-v4l2-ioctlh.patch > > in -mm. > > Maybe we should send that one Linusward ... > yup, I'll send it in unless it turned up in today's linux-next. From sfr@canb.auug.org.au Tue Aug 5 17:39:16 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 05 Aug 2008 17:39:23 +0100 (BST) Received: from chilli.pcug.org.au ([203.10.76.44]:26781 "EHLO smtps.tip.net.au") by ftp.linux-mips.org with ESMTP id S20022440AbYHEQjQ (ORCPT ); Tue, 5 Aug 2008 17:39:16 +0100 Received: from ash.ozlabs.ibm.com (ta-1-1.tip.net.au [203.11.71.1]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by smtps.tip.net.au (Postfix) with ESMTP id 849FE368003; Wed, 6 Aug 2008 02:39:11 +1000 (EST) Date: Wed, 6 Aug 2008 02:39:06 +1000 From: Stephen Rothwell To: Andrew Morton Cc: Adrian Bunk , Mauro Carvalho Chehab , LKML , v4l-dvb-maintainer@linuxtv.org, video4linux-list@redhat.com, Ralf Baechle , linux-mips@linux-mips.org Subject: Re: v4l/mips build problem Message-Id: <20080806023906.c2f919b4.sfr@canb.auug.org.au> In-Reply-To: <20080805092650.af88364a.akpm@linux-foundation.org> References: <20080806012357.55625daf.sfr@canb.auug.org.au> <20080805154122.GC22895@cs181140183.pp.htv.fi> <20080806020647.2cf11a2b.sfr@canb.auug.org.au> <20080805092650.af88364a.akpm@linux-foundation.org> X-Mailer: Sylpheed 2.5.0 (GTK+ 2.12.11; i486-pc-linux-gnu) Mime-Version: 1.0 Content-Type: multipart/signed; protocol="application/pgp-signature"; micalg="PGP-SHA1"; boundary="Signature=_Wed__6_Aug_2008_02_39_06_+1000_M_RXau64tb.9uS=6" Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20113 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sfr@canb.auug.org.au Precedence: bulk X-list: linux-mips --Signature=_Wed__6_Aug_2008_02_39_06_+1000_M_RXau64tb.9uS=6 Content-Type: text/plain; charset=US-ASCII Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Hi Andrew, On Tue, 5 Aug 2008 09:26:50 -0700 Andrew Morton = wrote: > > yup, I'll send it in unless it turned up in today's linux-next. Which I think is unlikely: the v4l/dvb tree has been unmergable since 29/7 and I haven't heard from Mauro since then. Thanks. --=20 Cheers, Stephen Rothwell sfr@canb.auug.org.au http://www.canb.auug.org.au/~sfr/ --Signature=_Wed__6_Aug_2008_02_39_06_+1000_M_RXau64tb.9uS=6 Content-Type: application/pgp-signature -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.9 (GNU/Linux) iEYEARECAAYFAkiYgioACgkQjjKRsyhoI8yIwgCgutmaaba2Ti6yX3YpGXHvuIYY MccAoJz1MWwR6EXHcnjGVClR49Ln2aZL =Lz21 -----END PGP SIGNATURE----- --Signature=_Wed__6_Aug_2008_02_39_06_+1000_M_RXau64tb.9uS=6-- From SRS0+84df8e96b69946864cad+1808+infradead.org+mchehab@bombadil.srs.infradead.org Tue Aug 5 18:21:27 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 05 Aug 2008 18:21:33 +0100 (BST) Received: from bombadil.infradead.org ([18.85.46.34]:57523 "EHLO bombadil.infradead.org") by ftp.linux-mips.org with ESMTP id S20023138AbYHERV1 (ORCPT ); Tue, 5 Aug 2008 18:21:27 +0100 Received: from localhost ([127.0.0.1]) by bombadil.infradead.org with esmtps (Exim 4.68 #1 (Red Hat Linux)) id 1KQQCE-0007a3-LJ; Tue, 05 Aug 2008 17:19:42 +0000 Date: Tue, 5 Aug 2008 13:19:42 -0400 (EDT) From: Mauro Carvalho Chehab To: Stephen Rothwell cc: Andrew Morton , Adrian Bunk , LKML , v4l-dvb-maintainer@linuxtv.org, video4linux-list@redhat.com, Ralf Baechle , linux-mips@linux-mips.org Subject: Re: v4l/mips build problem In-Reply-To: <20080806023906.c2f919b4.sfr@canb.auug.org.au> Message-ID: References: <20080806012357.55625daf.sfr@canb.auug.org.au> <20080805154122.GC22895@cs181140183.pp.htv.fi> <20080806020647.2cf11a2b.sfr@canb.auug.org.au> <20080805092650.af88364a.akpm@linux-foundation.org> <20080806023906.c2f919b4.sfr@canb.auug.org.au> User-Agent: Alpine 1.10 (LFD 962 2008-03-14) MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII; format=flowed X-SRS-Rewrite: SMTP reverse-path rewritten from by bombadil.infradead.org See http://www.infradead.org/rpr.html Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20114 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mchehab@infradead.org Precedence: bulk X-list: linux-mips On Wed, 6 Aug 2008, Stephen Rothwell wrote: > Hi Andrew, > > On Tue, 5 Aug 2008 09:26:50 -0700 Andrew Morton wrote: >> >> yup, I'll send it in unless it turned up in today's linux-next. > > Which I think is unlikely: the v4l/dvb tree has been unmergable since > 29/7 and I haven't heard from Mauro since then. Too busy during those days. I don't mind if Andrew prefer to forward this directly, but I have another bunch of patches to send Linus probably today. I did some changes on the procedures I use for sending patches upstream, but I want to do some additional tests here to be sure that everything is all right. The idea is never rebase my main branches again. -- Cheers, Mauro Carvalho Chehab http://linuxtv.org mchehab@infradead.org From mano@roarinelk.homelinux.net Tue Aug 5 18:51:30 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 05 Aug 2008 18:51:37 +0100 (BST) Received: from fnoeppeil43.netpark.at ([217.175.205.171]:53187 "EHLO roarinelk.homelinux.net") by ftp.linux-mips.org with ESMTP id S20022964AbYHERva (ORCPT ); Tue, 5 Aug 2008 18:51:30 +0100 Received: (qmail 29767 invoked by uid 1000); 5 Aug 2008 19:51:26 +0200 Date: Tue, 5 Aug 2008 19:51:26 +0200 From: Manuel Lauss To: Ralf Baechle Cc: linux-mips@linux-mips.org Subject: [PATCH] Alchemy: register mmc platform device for db1200/pb1200 boards Message-ID: <20080805175126.GA29618@roarinelk.homelinux.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline User-Agent: Mutt/1.5.16 (2007-06-09) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20115 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mano@roarinelk.homelinux.net Precedence: bulk X-list: linux-mips Hi Ralf, Please apply this patch, it is the last missing piece of the au1xmmc updates, which lets db1200/pb1200 use MMC/SD cards. Tested on DB1200. Thanks! Manuel Lauss --- Add au1xmmc platform data for PB1200/DB1200 boards, and wire up the 2 SD controllers for them. Signed-off-by: Manuel Lauss --- arch/mips/au1000/common/platform.c | 98 +++++++++++++++++++++++++++--------- arch/mips/au1000/pb1200/platform.c | 81 +++++++++++++++++++++++++++++ 2 files changed, 155 insertions(+), 24 deletions(-) diff --git a/arch/mips/au1000/common/platform.c b/arch/mips/au1000/common/platform.c index dc8a67e..5c76c64 100644 --- a/arch/mips/au1000/common/platform.c +++ b/arch/mips/au1000/common/platform.c @@ -17,6 +17,8 @@ #include #include +#include +#include #define PORT(_base, _irq) \ { \ @@ -163,24 +165,6 @@ static struct resource au1xxx_usb_gdt_resources[] = { }, }; -static struct resource au1xxx_mmc_resources[] = { - [0] = { - .start = SD0_PHYS_ADDR, - .end = SD0_PHYS_ADDR + 0x7ffff, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = SD1_PHYS_ADDR, - .end = SD1_PHYS_ADDR + 0x7ffff, - .flags = IORESOURCE_MEM, - }, - [2] = { - .start = AU1200_SD_INT, - .end = AU1200_SD_INT, - .flags = IORESOURCE_IRQ, - } -}; - static u64 udc_dmamask = DMA_32BIT_MASK; static struct platform_device au1xxx_usb_gdt_device = { @@ -249,16 +233,79 @@ static struct platform_device au1200_lcd_device = { static u64 au1xxx_mmc_dmamask = DMA_32BIT_MASK; -static struct platform_device au1xxx_mmc_device = { +extern struct au1xmmc_platform_data au1xmmc_platdata[2]; + +static struct resource au1200_mmc0_resources[] = { + [0] = { + .start = SD0_PHYS_ADDR, + .end = SD0_PHYS_ADDR + 0x7ffff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AU1200_SD_INT, + .end = AU1200_SD_INT, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = DSCR_CMD0_SDMS_TX0, + .end = DSCR_CMD0_SDMS_TX0, + .flags = IORESOURCE_DMA, + }, + [3] = { + .start = DSCR_CMD0_SDMS_RX0, + .end = DSCR_CMD0_SDMS_RX0, + .flags = IORESOURCE_DMA, + } +}; + +static struct platform_device au1200_mmc0_device = { .name = "au1xxx-mmc", .id = 0, .dev = { - .dma_mask = &au1xxx_mmc_dmamask, - .coherent_dma_mask = DMA_32BIT_MASK, + .dma_mask = &au1xxx_mmc_dmamask, + .coherent_dma_mask = DMA_32BIT_MASK, + .platform_data = &au1xmmc_platdata[0], }, - .num_resources = ARRAY_SIZE(au1xxx_mmc_resources), - .resource = au1xxx_mmc_resources, + .num_resources = ARRAY_SIZE(au1200_mmc0_resources), + .resource = au1200_mmc0_resources, }; + +#ifndef CONFIG_MIPS_DB1200 +static struct resource au1200_mmc1_resources[] = { + [0] = { + .start = SD1_PHYS_ADDR, + .end = SD1_PHYS_ADDR + 0x7ffff, + .flags = IORESOURCE_MEM, + }, + [1] = { + .start = AU1200_SD_INT, + .end = AU1200_SD_INT, + .flags = IORESOURCE_IRQ, + }, + [2] = { + .start = DSCR_CMD0_SDMS_TX1, + .end = DSCR_CMD0_SDMS_TX1, + .flags = IORESOURCE_DMA, + }, + [3] = { + .start = DSCR_CMD0_SDMS_RX1, + .end = DSCR_CMD0_SDMS_RX1, + .flags = IORESOURCE_DMA, + } +}; + +static struct platform_device au1200_mmc1_device = { + .name = "au1xxx-mmc", + .id = 1, + .dev = { + .dma_mask = &au1xxx_mmc_dmamask, + .coherent_dma_mask = DMA_32BIT_MASK, + .platform_data = &au1xmmc_platdata[1], + }, + .num_resources = ARRAY_SIZE(au1200_mmc1_resources), + .resource = au1200_mmc1_resources, +}; +#endif /* #ifndef CONFIG_MIPS_DB1200 */ #endif /* #ifdef CONFIG_SOC_AU1200 */ static struct platform_device au1x00_pcmcia_device = { @@ -296,7 +343,10 @@ static struct platform_device *au1xxx_platform_devices[] __initdata = { &au1xxx_usb_gdt_device, &au1xxx_usb_otg_device, &au1200_lcd_device, - &au1xxx_mmc_device, + &au1200_mmc0_device, +#ifndef CONFIG_MIPS_DB1200 + &au1200_mmc1_device, +#endif #endif #ifdef SMBUS_PSC_BASE &pbdb_smbus_device, diff --git a/arch/mips/au1000/pb1200/platform.c b/arch/mips/au1000/pb1200/platform.c index f8fb0ae..9530329 100644 --- a/arch/mips/au1000/pb1200/platform.c +++ b/arch/mips/au1000/pb1200/platform.c @@ -20,9 +20,90 @@ #include #include +#include #include #include +#include + +static int mmc_activity; + +static void pb1200mmc0_set_power(void *mmc_host, int state) +{ + if (state) + bcsr->board |= BCSR_BOARD_SD0PWR; + else + bcsr->board &= ~BCSR_BOARD_SD0PWR; + + au_sync_delay(1); +} + +static int pb1200mmc0_card_readonly(void *mmc_host) +{ + return (bcsr->status & BCSR_STATUS_SD0WP) ? 1 : 0; +} + +static int pb1200mmc0_card_inserted(void *mmc_host) +{ + return (bcsr->sig_status & BCSR_INT_SD0INSERT) ? 1 : 0; +} + +static void pb1200_mmcled_set(struct led_classdev *led, + enum led_brightness brightness) +{ + if (brightness != LED_OFF) { + if (++mmc_activity == 1) + bcsr->disk_leds &= ~(1 << 8); + } else { + if (--mmc_activity == 0) + bcsr->disk_leds |= (1 << 8); + } +} + +static struct led_classdev pb1200mmc_led = { + .brightness_set = pb1200_mmcled_set, +}; + +#ifndef CONFIG_MIPS_DB1200 +static void pb1200mmc1_set_power(void *mmc_host, int state) +{ + if (state) + bcsr->board |= BCSR_BOARD_SD1PWR; + else + bcsr->board &= ~BCSR_BOARD_SD1PWR; + + au_sync_delay(1); +} + +static int pb1200mmc1_card_readonly(void *mmc_host) +{ + return (bcsr->status & BCSR_STATUS_SD1WP) ? 1 : 0; +} + +static int pb1200mmc1_card_inserted(void *mmc_host) +{ + return (bcsr->sig_status & BCSR_INT_SD1INSERT) ? 1 : 0; +} +#endif + +const struct au1xmmc_platform_data au1xmmc_platdata[2] = { + [0] = { + .set_power = pb1200mmc0_set_power, + .card_inserted = pb1200mmc0_card_inserted, + .card_readonly = pb1200mmc0_card_readonly, + .cd_setup = NULL, /* use poll-timer in driver */ + .led = &pb1200mmc_led, + }, +#ifndef CONFIG_MIPS_DB1200 + [1] = { + .set_power = pb1200mmc1_set_power, + .card_inserted = pb1200mmc1_card_inserted, + .card_readonly = pb1200mmc1_card_readonly, + .cd_setup = NULL, /* use poll-timer in driver */ + .led = &pb1200mmc_led, + }, +#endif +}; static struct resource ide_resources[] = { [0] = { -- 1.5.6.4 From CFRIESEN@nortel.com Tue Aug 5 19:25:17 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 05 Aug 2008 19:25:25 +0100 (BST) Received: from zrtps0kp.nortel.com ([47.140.192.56]:18062 "EHLO zrtps0kp.nortel.com") by ftp.linux-mips.org with ESMTP id S20024104AbYHESZR (ORCPT ); Tue, 5 Aug 2008 19:25:17 +0100 Received: from zcarhxs1.corp.nortel.com (zcarhxs1.corp.nortel.com [47.129.230.89]) by zrtps0kp.nortel.com (Switch-2.2.6/Switch-2.2.0) with ESMTP id m75IP8X09787; Tue, 5 Aug 2008 18:25:09 GMT Received: from [47.130.64.132] ([47.130.64.132] RDNS failed) by zcarhxs1.corp.nortel.com with Microsoft SMTPSVC(6.0.3790.3959); Tue, 5 Aug 2008 14:25:06 -0400 Message-ID: <48989AFE.5000500@nortel.com> Date: Tue, 05 Aug 2008 12:25:02 -0600 From: "Chris Friesen" User-Agent: Mozilla Thunderbird 1.0.2-6 (X11/20050513) X-Accept-Language: en-us, en MIME-Version: 1.0 To: linux-mips@linux-mips.org, ralf@linux-mips.org Subject: looking for help interpreting softlockup/stack trace Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 05 Aug 2008 18:25:06.0463 (UTC) FILETIME=[95D5D2F0:01C8F728] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20116 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: cfriesen@nortel.com Precedence: bulk X-list: linux-mips I've run into an interesting issue with an Octeon-based board, where it just seems to hang. I suspect we're hitting some kind of locking bug, and I'm trying to track it down. If it matters, the kernel is quite old (heavily patched 2.6.14) and I've got no chance of upgrading it. (The usual embedded scenario.) I've added some scheduler instrumentation, as well as adding a stack dump to the output of the softlockup code. In the trace below, is "epc" the program counter at the time of the timer interrupt? How does "ra" fit into this, given that the function whose address it contains isn't seen in the stack trace until quite a ways down? Any insights are greatly appreciated... Chris cpu9: jiffies: 4295366417, hrtime: 552015654907, 500 ms without calling schedule() since scheduler requested cpu1: jiffies: 4295366418, hrtime: 552016450325, 500 ms without calling schedule() since scheduler requested cpu3: jiffies: 4295366442, hrtime: 552034584838, 500 ms without calling schedule() since scheduler requested cpu9: jiffies: 4295367258, hrtime: 552646827014, 841 ms between scheduler_tick() calls BUG: soft lockup detected on CPU#0! Cpu 0 $ 0 : 0000000000000000 0000000000000000 ffffffff80000000 ffffffff00000000 $ 4 : a8000000db3ce808 0000000000000084 a8000000d34cb1ea a8000000d34cb1ea $ 8 : 0000000045000084 0000000000000002 0000000000000001 ffffffff8165e1e0 $12 : 0000000000000000 ffffffff812dedac 0000500000008000 0000100000000000 $16 : a8000000d3a40b68 a8000000db3ce580 a8000000d3a40b00 ffffffff8151e448 $20 : a8000000db3ce808 ffffffff81593808 a8000000d3a40b00 0000000000000000 $24 : 0000000000000030 c000000001ae1820 $28 : ffffffff81590000 ffffffff81593680 ffffffff81593810 c000000001b4ab9c Hi : 0000000000000000 Lo : 0000000000000000 epc : ffffffff8151e44c _read_lock+0x4/0x20 Tainted: P ra : c000000001b4ab9c $LBB378+0x0/0x18 [vnb] Status: 1000ffe3 KX SX UX KERNEL EXL IE Cause : 40808000 PrId : 000d0301 Call Trace: [] softlockup_tick+0x12c/0x158 [] timer_interrupt+0xd4/0x4c8 [] timer_interrupt+0x288/0x4c8 [] octeon_main_timer_interrupt+0x78/0x90 [] handle_IRQ_event+0x45c/0x1528 [] __do_IRQ+0xd4/0x230 [] _read_lock+0x0/0x20 [] do_IRQ+0x440/0x1520 [] neigh_lookup+0xb4/0x128 [] _read_lock+0x0/0x20 [] ret_from_irq+0x0/0x10 [] __wake_up_common+0x6c/0xb8 [] memset_partial+0x48/0x60 [] _read_lock+0x0/0x20 [] $Ltext0+0x0/0x4 [vnb] [] _read_unlock+0x0/0x20 [] $LBB378+0x0/0x18 [vnb] [] _read_lock+0x4/0x20 [] arp_rcv+0x18c/0x258 [] netif_dispatch_skb+0x18c/0x2d0 [] $LBE370+0x0/0x10 [cavium_ethernet] [] $L396+0x0/0x1c [vnb] [] $LCFI35+0x8c/0x9c [vnb] [] $L1193+0x2c/0x48 [vnb] [] $L1047+0x28/0xd0 [vnb] [] $LBB344+0x2c/0x34 [vnb] [] activate_task+0x98/0x108 [] $L1215+0x2c/0x30 [vnb] [] $L1273+0x0/0x18 [vnb] [] $L28+0x24/0x4c [vnb] [] netif_receive_skb+0x300/0x730 [] __alloc_skb+0x84/0x1a8 [] $L620+0x20/0x28 [cavium_ethernet] [] process_timeout+0x0/0xb08 [] do_gettimeofday+0xa8/0x220 [] tasklet_action+0x684/0x1950 [] hrtimer_run_queues+0x84/0x1a0 [] cvm_oct_tasklet_rx+0x0/0x4 [cavium_ethernet] [] run_timer_softirq+0x20c/0xce0 [] cvm_oct_tasklet_rx+0x0/0x4 [cavium_ethernet] [] timer_interrupt+0x288/0x4c8 [] __do_softirq+0x56c/0x1818 [] do_softirq+0x98/0xb8 [] do_IRQ+0x80c/0x1520 [] kernel_thread+0xa0/0xbf8 [] ret_from_irq+0x0/0x10 [] schedule+0xd4c/0x1a98 [] r4k_wait+0x0/0x10 [] datagram_poll+0x0/0x140 [] cpu_idle+0x44/0x60 [] r4k_wait+0x8/0x10 [] start_kernel+0x460/0x4f8 [] start_kernel+0x458/0x4f8 [] kernel_entry+0x0/0x4c From KKylheku@zeugmasystems.com Tue Aug 5 20:11:45 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 05 Aug 2008 20:11:54 +0100 (BST) Received: from mail.zeugmasystems.com ([192.139.122.66]:16446 "EHLO zeugmasystems.com") by ftp.linux-mips.org with ESMTP id S20029049AbYHETLp convert rfc822-to-8bit (ORCPT ); Tue, 5 Aug 2008 20:11:45 +0100 Content-class: urn:content-classes:message MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT Subject: RE: looking for help interpreting softlockup/stack trace X-MimeOLE: Produced By Microsoft Exchange V6.5 Date: Tue, 5 Aug 2008 12:11:34 -0700 Message-ID: In-Reply-To: <48989AFE.5000500@nortel.com> X-MS-Has-Attach: X-MS-TNEF-Correlator: Thread-Topic: looking for help interpreting softlockup/stack trace Thread-Index: Acj3KLiOCwuA6I93R8Kpre/ka5hwhwAAze7g From: "Kaz Kylheku" To: "Chris Friesen" , , Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20117 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: KKylheku@zeugmasystems.com Precedence: bulk X-list: linux-mips Chris Friesem wrote: > I've run into an interesting issue with an Octeon-based > board, where it > just seems to hang. I suspect we're hitting some kind of > locking bug, > and I'm trying to track it down. If it matters, the kernel > is quite old > (heavily patched 2.6.14) and I've got no chance of upgrading > it. (The > usual embedded scenario.) > > I've added some scheduler instrumentation, as well as adding a stack > dump to the output of the softlockup code. > > In the trace below, is "epc" the program counter at the time of the > timer interrupt? How does "ra" fit into this, given that the function > whose address it contains isn't seen in the stack trace until quite a > ways down? Hi Chris The contents of RA may or may not be useful. RA is used to hold the return address when some branch instructions are executed. The contents of RA may provide some kind of clue about what the processor was doing previously. Often, RA can give you the parent function, but not always. Here it looks it does give the parent function; it is apparently inside a kernel module called "vnb", which called _read_lock and got stuck there. Mind you, these Linux MIPS stack traces are not completely trustworthy; the routine just walks the stack one word at a time and prints out anything that looks like the address of code. So the stack trace may include stale stack data from previous call chains that have already returned. It also might not include the full call chain, because the return address is not always stored on the stack. For instance, here it looks like RA is pointing into a kernel module. But you don't actually see this in the fake stack trace. Nowhere in the stack trace do you see _read_lock being called by c000000001b4ab9c. I would proceed by inspecting this vnb module and its use of locks. > > Any insights are greatly appreciated... > > Chris > > cpu9: jiffies: 4295366417, hrtime: 552015654907, 500 ms > without calling > schedule() since scheduler requested > cpu1: jiffies: 4295366418, hrtime: 552016450325, 500 ms > without calling > schedule() since scheduler requested > cpu3: jiffies: 4295366442, hrtime: 552034584838, 500 ms > without calling > schedule() since scheduler requested > cpu9: jiffies: 4295367258, hrtime: 552646827014, 841 ms between > scheduler_tick() calls BUG: soft lockup detected on CPU#0! > Cpu 0 > $ 0 : 0000000000000000 0000000000000000 ffffffff80000000 > ffffffff00000000 $ 4 : a8000000db3ce808 0000000000000084 > a8000000d34cb1ea a8000000d34cb1ea $ 8 : 0000000045000084 > 0000000000000002 0000000000000001 ffffffff8165e1e0 $12 : > 0000000000000000 ffffffff812dedac 0000500000008000 0000100000000000 > $16 : a8000000d3a40b68 a8000000db3ce580 a8000000d3a40b00 > ffffffff8151e448 $20 : a8000000db3ce808 ffffffff81593808 > a8000000d3a40b00 0000000000000000 $24 : 0000000000000030 > c000000001ae1820 $28 : ffffffff81590000 ffffffff81593680 > ffffffff81593810 c000000001b4ab9c Hi : 0000000000000000 > Lo : 0000000000000000 > epc : ffffffff8151e44c _read_lock+0x4/0x20 Tainted: P > ra : c000000001b4ab9c $LBB378+0x0/0x18 [vnb] > Status: 1000ffe3 KX SX UX KERNEL EXL IE > Cause : 40808000 > PrId : 000d0301 > Call Trace: > [] softlockup_tick+0x12c/0x158 > [] timer_interrupt+0xd4/0x4c8 > [] timer_interrupt+0x288/0x4c8 > [] octeon_main_timer_interrupt+0x78/0x90 > [] handle_IRQ_event+0x45c/0x1528 > [] __do_IRQ+0xd4/0x230 > [] _read_lock+0x0/0x20 This read lock is almost certainly a red herring; it's stuff left over on the stack that hasn't been overwritten by new activation chains. > [] do_IRQ+0x440/0x1520 This is the timer interrupt going off, which ends up detecting the lockup. So the problem is above here. > [] neigh_lookup+0xb4/0x128 This may also be garbage. Basically, the stack trace is not that useful, except that it provides some additional circumstantial evidence implicating the vnb module. From ralf@linux-mips.org Tue Aug 5 20:16:21 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 05 Aug 2008 20:16:27 +0100 (BST) Received: from ditditdahdahdah-dahdahdahditdit.dl5rb.org.uk ([217.169.26.28]:65431 "EHLO ditditdahdahdah-dahdahdahditdit.dl5rb.org.uk") by ftp.linux-mips.org with ESMTP id S20033084AbYHETQV (ORCPT ); Tue, 5 Aug 2008 20:16:21 +0100 Received: from denk.linux-mips.net (denk.linux-mips.net [127.0.0.1]) by ditditdahdahdah-dahdahdahditdit.dl5rb.org.uk (8.14.2/8.14.1) with ESMTP id m75JGKqa011206; Tue, 5 Aug 2008 20:16:20 +0100 Received: (from ralf@localhost) by denk.linux-mips.net (8.14.2/8.14.2/Submit) id m75JGJfD011204; Tue, 5 Aug 2008 20:16:19 +0100 Date: Tue, 5 Aug 2008 20:16:19 +0100 From: Ralf Baechle To: Chris Friesen Cc: linux-mips@linux-mips.org Subject: Re: looking for help interpreting softlockup/stack trace Message-ID: <20080805191618.GB8629@linux-mips.org> References: <48989AFE.5000500@nortel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <48989AFE.5000500@nortel.com> User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20118 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Tue, Aug 05, 2008 at 12:25:02PM -0600, Chris Friesen wrote: > I've run into an interesting issue with an Octeon-based board, where it > just seems to hang. I suspect we're hitting some kind of locking bug, > and I'm trying to track it down. If it matters, the kernel is quite old > (heavily patched 2.6.14) and I've got no chance of upgrading it. (The > usual embedded scenario.) > > I've added some scheduler instrumentation, as well as adding a stack > dump to the output of the softlockup code. > > In the trace below, is "epc" the program counter at the time of the > timer interrupt? How does "ra" fit into this, given that the function > whose address it contains isn't seen in the stack trace until quite a > ways down? $LBB378 is an internal symbol. The value of RA may not be very informative if it was overwritten by a random subroutine call. > Any insights are greatly appreciated... You may also try lockdep; it gives much more detailed information though it's more heavyweight. Ralf From Kenneth.Reese@caviumnetworks.com Tue Aug 5 21:28:25 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 05 Aug 2008 21:28:33 +0100 (BST) Received: from mail3.caviumnetworks.com ([12.108.191.235]:4164 "EHLO mail3.caviumnetworks.com") by ftp.linux-mips.org with ESMTP id S20043313AbYHEU2Z (ORCPT ); Tue, 5 Aug 2008 21:28:25 +0100 Received: from exch4.caveonetworks.com (Not Verified[192.168.16.23]) by mail3.caviumnetworks.com with MailMarshal (v6,2,2,3503) id ; Tue, 05 Aug 2008 16:28:17 -0400 Received: from exch4.caveonetworks.com ([192.168.16.23]) by exch4.caveonetworks.com with Microsoft SMTPSVC(6.0.3790.3959); Tue, 5 Aug 2008 13:28:13 -0700 Received: from [192.168.162.106] ([64.169.86.201]) by exch4.caveonetworks.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.3959); Tue, 5 Aug 2008 13:28:13 -0700 Message-ID: <4898B7DD.6090402@caviumnetworks.com> Date: Tue, 05 Aug 2008 13:28:13 -0700 From: Chad Reese User-Agent: Mozilla/5.0 (X11; U; Linux x86_64; en-US; rv:1.8.0.14eol) Gecko/20070505 Iceape/1.0.9 (Debian-1.0.13~pre080323b-0etch3) MIME-Version: 1.0 To: Chris Friesen CC: linux-mips@linux-mips.org, ralf@linux-mips.org Subject: Re: looking for help interpreting softlockup/stack trace References: <48989AFE.5000500@nortel.com> In-Reply-To: <48989AFE.5000500@nortel.com> Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 05 Aug 2008 20:28:13.0852 (UTC) FILETIME=[C90FEDC0:01C8F739] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20119 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: kreese@caviumnetworks.com Precedence: bulk X-list: linux-mips I assume this is happening under high network load. Some early Octeon ethernet drivers had a problem where they could starve the rest of the system processing incoming packets. The message you are getting is the kernel warning you that userspace hasn't been given any processing time. What is probably happening is the cavium_ethernet driver is spending all its time in a receive tasklet getting packets and then dropping them. This has been fixed in a later cavium SDK, but it looks like you are running an ancient kernel. A newer kernel is available on the cavium support site. The cavium ethernet driver doesn't use the standard NAPI interface since it doesn't support multicore receive for a single port. Chad Chris Friesen wrote: > I've run into an interesting issue with an Octeon-based board, where it > just seems to hang. I suspect we're hitting some kind of locking bug, > and I'm trying to track it down. If it matters, the kernel is quite old > (heavily patched 2.6.14) and I've got no chance of upgrading it. (The > usual embedded scenario.) > > I've added some scheduler instrumentation, as well as adding a stack > dump to the output of the softlockup code. > > In the trace below, is "epc" the program counter at the time of the > timer interrupt? How does "ra" fit into this, given that the function > whose address it contains isn't seen in the stack trace until quite a > ways down? > > Any insights are greatly appreciated... > > Chris > > cpu9: jiffies: 4295366417, hrtime: 552015654907, 500 ms without calling > schedule() since scheduler requested > cpu1: jiffies: 4295366418, hrtime: 552016450325, 500 ms without calling > schedule() since scheduler requested > cpu3: jiffies: 4295366442, hrtime: 552034584838, 500 ms without calling > schedule() since scheduler requested > cpu9: jiffies: 4295367258, hrtime: 552646827014, 841 ms between > scheduler_tick() calls > BUG: soft lockup detected on CPU#0! > Cpu 0 > $ 0 : 0000000000000000 0000000000000000 ffffffff80000000 ffffffff00000000 > $ 4 : a8000000db3ce808 0000000000000084 a8000000d34cb1ea a8000000d34cb1ea > $ 8 : 0000000045000084 0000000000000002 0000000000000001 ffffffff8165e1e0 > $12 : 0000000000000000 ffffffff812dedac 0000500000008000 0000100000000000 > $16 : a8000000d3a40b68 a8000000db3ce580 a8000000d3a40b00 ffffffff8151e448 > $20 : a8000000db3ce808 ffffffff81593808 a8000000d3a40b00 0000000000000000 > $24 : 0000000000000030 c000000001ae1820 > $28 : ffffffff81590000 ffffffff81593680 ffffffff81593810 c000000001b4ab9c > Hi : 0000000000000000 > Lo : 0000000000000000 > epc : ffffffff8151e44c _read_lock+0x4/0x20 Tainted: P > ra : c000000001b4ab9c $LBB378+0x0/0x18 [vnb] > Status: 1000ffe3 KX SX UX KERNEL EXL IE > Cause : 40808000 > PrId : 000d0301 > Call Trace: > [] softlockup_tick+0x12c/0x158 > [] timer_interrupt+0xd4/0x4c8 > [] timer_interrupt+0x288/0x4c8 > [] octeon_main_timer_interrupt+0x78/0x90 > [] handle_IRQ_event+0x45c/0x1528 > [] __do_IRQ+0xd4/0x230 > [] _read_lock+0x0/0x20 > [] do_IRQ+0x440/0x1520 > [] neigh_lookup+0xb4/0x128 > [] _read_lock+0x0/0x20 > [] ret_from_irq+0x0/0x10 > [] __wake_up_common+0x6c/0xb8 > [] memset_partial+0x48/0x60 > [] _read_lock+0x0/0x20 > [] $Ltext0+0x0/0x4 [vnb] > [] _read_unlock+0x0/0x20 > [] $LBB378+0x0/0x18 [vnb] > [] _read_lock+0x4/0x20 > [] arp_rcv+0x18c/0x258 > [] netif_dispatch_skb+0x18c/0x2d0 > [] $LBE370+0x0/0x10 [cavium_ethernet] > [] $L396+0x0/0x1c [vnb] > [] $LCFI35+0x8c/0x9c [vnb] > [] $L1193+0x2c/0x48 [vnb] > [] $L1047+0x28/0xd0 [vnb] > [] $LBB344+0x2c/0x34 [vnb] > [] activate_task+0x98/0x108 > [] $L1215+0x2c/0x30 [vnb] > [] $L1273+0x0/0x18 [vnb] > [] $L28+0x24/0x4c [vnb] > [] netif_receive_skb+0x300/0x730 > [] __alloc_skb+0x84/0x1a8 > [] $L620+0x20/0x28 [cavium_ethernet] > [] process_timeout+0x0/0xb08 > [] do_gettimeofday+0xa8/0x220 > [] tasklet_action+0x684/0x1950 > [] hrtimer_run_queues+0x84/0x1a0 > [] cvm_oct_tasklet_rx+0x0/0x4 [cavium_ethernet] > [] run_timer_softirq+0x20c/0xce0 > [] cvm_oct_tasklet_rx+0x0/0x4 [cavium_ethernet] > [] timer_interrupt+0x288/0x4c8 > [] __do_softirq+0x56c/0x1818 > [] do_softirq+0x98/0xb8 > [] do_IRQ+0x80c/0x1520 > [] kernel_thread+0xa0/0xbf8 > [] ret_from_irq+0x0/0x10 > [] schedule+0xd4c/0x1a98 > [] r4k_wait+0x0/0x10 > [] datagram_poll+0x0/0x140 > [] cpu_idle+0x44/0x60 > [] r4k_wait+0x8/0x10 > [] start_kernel+0x460/0x4f8 > [] start_kernel+0x458/0x4f8 > [] kernel_entry+0x0/0x4c > -- Chad Reese Cavium Networks From CFRIESEN@nortel.com Tue Aug 5 21:46:42 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 05 Aug 2008 21:46:48 +0100 (BST) Received: from zrtps0kn.nortel.com ([47.140.192.55]:20443 "EHLO zrtps0kn.nortel.com") by ftp.linux-mips.org with ESMTP id S20022316AbYHEUqm (ORCPT ); Tue, 5 Aug 2008 21:46:42 +0100 Received: from zcarhxs1.corp.nortel.com (zcarhxs1.corp.nortel.com [47.129.230.89]) by zrtps0kn.nortel.com (Switch-2.2.6/Switch-2.2.0) with ESMTP id m75KkVh02902; Tue, 5 Aug 2008 20:46:31 GMT Received: from [47.130.64.132] ([47.130.64.132] RDNS failed) by zcarhxs1.corp.nortel.com with Microsoft SMTPSVC(6.0.3790.3959); Tue, 5 Aug 2008 16:46:30 -0400 Message-ID: <4898BC23.6050704@nortel.com> Date: Tue, 05 Aug 2008 14:46:27 -0600 From: "Chris Friesen" User-Agent: Mozilla Thunderbird 1.0.2-6 (X11/20050513) X-Accept-Language: en-us, en MIME-Version: 1.0 To: Chad Reese CC: linux-mips@linux-mips.org, ralf@linux-mips.org Subject: Re: looking for help interpreting softlockup/stack trace References: <48989AFE.5000500@nortel.com> <4898B7DD.6090402@caviumnetworks.com> In-Reply-To: <4898B7DD.6090402@caviumnetworks.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 05 Aug 2008 20:46:30.0636 (UTC) FILETIME=[56CBE2C0:01C8F73C] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20120 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: cfriesen@nortel.com Precedence: bulk X-list: linux-mips Chad Reese wrote: > I assume this is happening under high network load. Some early Octeon > ethernet drivers had a problem where they could starve the rest of the > system processing incoming packets. The message you are getting is the > kernel warning you that userspace hasn't been given any processing time. > What is probably happening is the cavium_ethernet driver is spending all > its time in a receive tasklet getting packets and then dropping them. > This has been fixed in a later cavium SDK, but it looks like you are > running an ancient kernel. A newer kernel is available on the cavium > support site. It seems unlikely it's due to cpu load. It's only receiving around 30000 packets/sec total, and before the problem shows up "top" shows some cores at around 25% and others totally idle. The only symptom of the problem is that the system simply stops responding. You wouldn't happen to know which versions fixed the problem you described above, would you? Upgrading the kernel isn't an option, but it wouldn't be the first time we've had to backport things. > The cavium ethernet driver doesn't use the standard NAPI interface since > it doesn't support multicore receive for a single port. Ah...I was wondering about that. Chris From CFRIESEN@nortel.com Tue Aug 5 22:38:44 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 05 Aug 2008 22:38:50 +0100 (BST) Received: from zrtps0kn.nortel.com ([47.140.192.55]:48869 "EHLO zrtps0kn.nortel.com") by ftp.linux-mips.org with ESMTP id S20043350AbYHEVio (ORCPT ); Tue, 5 Aug 2008 22:38:44 +0100 Received: from zcarhxs1.corp.nortel.com (zcarhxs1.corp.nortel.com [47.129.230.89]) by zrtps0kn.nortel.com (Switch-2.2.6/Switch-2.2.0) with ESMTP id m75LcVh08078; Tue, 5 Aug 2008 21:38:31 GMT Received: from [47.130.64.132] ([47.130.64.132] RDNS failed) by zcarhxs1.corp.nortel.com with Microsoft SMTPSVC(6.0.3790.3959); Tue, 5 Aug 2008 17:38:16 -0400 Message-ID: <4898C845.1060903@nortel.com> Date: Tue, 05 Aug 2008 15:38:13 -0600 From: "Chris Friesen" User-Agent: Mozilla Thunderbird 1.0.2-6 (X11/20050513) X-Accept-Language: en-us, en MIME-Version: 1.0 To: Kaz Kylheku CC: linux-mips@linux-mips.org, ralf@linux-mips.org Subject: Re: looking for help interpreting softlockup/stack trace References: In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 05 Aug 2008 21:38:17.0104 (UTC) FILETIME=[92654900:01C8F743] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20121 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: cfriesen@nortel.com Precedence: bulk X-list: linux-mips Kaz Kylheku wrote: > Chris Friesem wrote: >>In the trace below, is "epc" the program counter at the time of the >>timer interrupt? How does "ra" fit into this, given that the function >>whose address it contains isn't seen in the stack trace until quite a >>ways down? > Mind you, these Linux MIPS stack traces are not completely > trustworthy; the routine just walks the stack one word at a time > and prints out anything that looks like the address of code. > So the stack trace may include stale stack data from previous > call chains that have already returned. It also might not > include the full call chain, because the return address is not > always stored on the stack. For instance, here it looks like > RA is pointing into a kernel module. But you don't actually > see this in the fake stack trace. Nowhere in the stack trace > do you see _read_lock being called by c000000001b4ab9c. Right...but it does look like it calls _read_unlock(). > I would proceed by inspecting this vnb module and its use of locks. Yeah...I'll do that. >>scheduler_tick() calls BUG: soft lockup detected on CPU#0! One thing I've noticed, all the softlockups are on cpu0 even though other cpus are also complaining about scheduling delays. Is there something special about cpu0? >>Call Trace: >> [] softlockup_tick+0x12c/0x158 >> [] timer_interrupt+0xd4/0x4c8 >> [] timer_interrupt+0x288/0x4c8 >> [] octeon_main_timer_interrupt+0x78/0x90 >> [] handle_IRQ_event+0x45c/0x1528 >> [] __do_IRQ+0xd4/0x230 >> [] _read_lock+0x0/0x20 > > > This read lock is almost certainly a red herring; it's > stuff left over on the stack that hasn't been overwritten > by new activation chains. Wouldn't it be part of the do_IRQ call below? >> [] do_IRQ+0x440/0x1520 > > > This is the timer interrupt going off, which ends up > detecting the lockup. So the problem is above here. I assume you mean "above" in terms of chronological order, since in terms of the call trace the problem would be below. >> [] neigh_lookup+0xb4/0x128 > > > This may also be garbage. Basically, the stack > trace is not that useful, except that it provides > some additional circumstantial evidence implicating > the vnb module. It's unfortunate that the call trace isn't accurate. Thanks for the help, Chris From dvomlehn@cisco.com Wed Aug 6 00:16:32 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 06 Aug 2008 00:16:41 +0100 (BST) Received: from sj-iport-1.cisco.com ([171.71.176.70]:52803 "EHLO sj-iport-1.cisco.com") by ftp.linux-mips.org with ESMTP id S20040752AbYHEXQc (ORCPT ); Wed, 6 Aug 2008 00:16:32 +0100 X-IronPort-AV: E=Sophos;i="4.31,312,1215388800"; d="scan'208";a="61959677" Received: from sj-dkim-4.cisco.com ([171.71.179.196]) by sj-iport-1.cisco.com with ESMTP; 05 Aug 2008 23:16:23 +0000 Received: from sj-core-5.cisco.com (sj-core-5.cisco.com [171.71.177.238]) by sj-dkim-4.cisco.com (8.12.11/8.12.11) with ESMTP id m75NGNcc016959 for ; Tue, 5 Aug 2008 16:16:23 -0700 Received: from sausatlsmtp2.sciatl.com ([192.133.217.159]) by sj-core-5.cisco.com (8.13.8/8.13.8) with ESMTP id m75NGMEV021417 for ; Tue, 5 Aug 2008 23:16:23 GMT Received: from default.com ([192.133.217.159]) by sausatlsmtp2.sciatl.com with Microsoft SMTPSVC(6.0.3790.3959); Tue, 5 Aug 2008 19:16:22 -0400 Received: from sausatlbhs01.corp.sa.net ([192.133.216.76]) by sausatlsmtp2.sciatl.com with Microsoft SMTPSVC(6.0.3790.3959); Tue, 5 Aug 2008 19:16:21 -0400 Received: from cuplxvomd02.corp.sa.net ([64.101.20.155]) by sausatlbhs01.corp.sa.net with Microsoft SMTPSVC(6.0.3790.3959); Tue, 5 Aug 2008 19:16:20 -0400 Message-ID: <4898DF3C.5010000@cisco.com> Date: Tue, 05 Aug 2008 16:16:12 -0700 From: David VomLehn Reply-To: dvomlehn@cisco.com User-Agent: Thunderbird 2.0.0.14 (X11/20080501) MIME-Version: 1.0 To: linux-mips@linux-mips.org Subject: [PATCH 1/1]MIPS: Support DMA mapping of all kernel "unmapped" virtual address segments Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 05 Aug 2008 23:16:20.0439 (UTC) FILETIME=[4522F670:01C8F751] X-ST-MF-Message-Resent: 8/5/2008 19:16 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; l=3202; t=1217978183; x=1218842183; c=relaxed/simple; s=sjdkim4002; h=Content-Type:From:Subject:Content-Transfer-Encoding:MIME-Version; d=cisco.com; i=dvomlehn@cisco.com; z=From:=20David=20VomLehn=20 |Subject:=20[PATCH=201/1]MIPS=3A=20Support=20DMA=20mapping= 20of=20all=20kernel=20=22unmapped=22=20virtual=0A=20address= 20segments |Sender:=20; bh=u9O6QVjt+fhtTs68SfweRTaZ2X9KGBndJ9XlYiKuv/E=; b=kjzrSlQG0i0OHX2zjKj91fe67MWdg8VWj1508b9u1hN+z/m0vZOWWhJgUV kg65gMEtNZF6vQMFdLx79xgHhCF7WMbbNklwmj1pcoeeyzrnf6HWPkxaxvIM TX2jx/Hyr+; Authentication-Results: sj-dkim-4; header.From=dvomlehn@cisco.com; dkim=pass ( sig from cisco.com/sjdkim4002 verified; ); Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20122 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dvomlehn@cisco.com Precedence: bulk X-list: linux-mips Support DMA mapping of all kernel "unmapped" virtual address segments to the corresponding physical addresses for 32- and 64-bit architectures. Signed-off-by: David VomLehn --- The current virt_to_phys function does not map KSEG1 address to the correct physical address, nor will it map most of the XKPHYS addresses correctly. This patch addresses this problem. Unfortunately, I don't have access to a 64-bit system, so I need to ask for someone to perform additional verification. Any volunteers? addrspace.h | 18 +++++++++++------- io.h | 2 +- 2 files changed, 12 insertions(+), 8 deletions(-) Index: linux/include/asm-mips/addrspace.h =================================================================== --- linux.orig/include/asm-mips/addrspace.h +++ linux/include/asm-mips/addrspace.h @@ -75,6 +75,12 @@ #define CKSEG2ADDR(a) (CPHYSADDR(a) | CKSEG2) #define CKSEG3ADDR(a) (CPHYSADDR(a) | CKSEG3) +/* + * The ultimate limited of the 64-bit MIPS architecture: 2 bits for selecting + * the region, 3 bits for the CCA mode. This leaves 59 bits of which the + * R8000 implements most with its 48-bit physical address space. + */ +#define TO_PHYS_MASK _CONST64_(0x07ffffffffffffff) /* 2^59 - 1 */ #else #define CKSEG0ADDR(a) (CPHYSADDR(a) | KSEG0) @@ -106,6 +112,11 @@ #define CKSEG2 0xc0000000 #define CKSEG3 0xe0000000 +/* + * The ultimate limit of the 32-bit MIPS architecture. 3 bits for selecting + * the region, leaving 29 bits for the physical address spaces + */ +#define TO_PHYS_MASK 0x1fffffffl /* 2^29 - 1 */ #endif /* @@ -129,13 +140,6 @@ #define PHYS_TO_XKPHYS(cm, a) (_CONST64_(0x8000000000000000) | \ ((cm)<<59) | (a)) -/* - * The ultimate limited of the 64-bit MIPS architecture: 2 bits for selecting - * the region, 3 bits for the CCA mode. This leaves 59 bits of which the - * R8000 implements most with its 48-bit physical address space. - */ -#define TO_PHYS_MASK _CONST64_(0x07ffffffffffffff) /* 2^^59 - 1 */ - #ifndef CONFIG_CPU_R8000 /* Index: linux/include/asm-mips/io.h =================================================================== --- linux.orig/include/asm-mips/io.h +++ linux/include/asm-mips/io.h @@ -118,7 +118,7 @@ static inline void set_io_port_base(unsi */ static inline unsigned long virt_to_phys(volatile const void *address) { - return (unsigned long)address - PAGE_OFFSET + PHYS_OFFSET; + return (unsigned long)address & TO_PHYS_MASK; } /* - - - - - Cisco - - - - - This e-mail and any attachments may contain information which is confidential, proprietary, privileged or otherwise protected by law. The information is solely intended for the named addressee (or a person responsible for delivering it to the addressee). If you are not the intended recipient of this message, you are not authorized to read, print, retain, copy or disseminate this message or any part of it. If you have received this e-mail in error, please notify the sender immediately by return e-mail and delete it from your computer. From yoichi_yuasa@tripeaks.co.jp Wed Aug 6 02:47:23 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 06 Aug 2008 02:47:34 +0100 (BST) Received: from mo31.po.2iij.NET ([210.128.50.54]:8495 "EHLO mo31.po.2iij.net") by ftp.linux-mips.org with ESMTP id S20042817AbYHFBrX (ORCPT ); Wed, 6 Aug 2008 02:47:23 +0100 Received: by mo.po.2iij.net (mo31) id m761l9DH046926; Wed, 6 Aug 2008 10:47:09 +0900 (JST) Received: from rally.tokyo.tripeaks.co.jp (65.126.232.202.bf.2iij.net [202.232.126.65]) by mbox.po.2iij.net (po-mbox303) id m761l4Is022564 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NOT); Wed, 6 Aug 2008 10:47:04 +0900 Message-Id: <200808060147.m761l4Is022564@po-mbox303.hop.2iij.net> Date: Wed, 6 Aug 2008 10:49:01 +0900 From: Yoichi Yuasa To: Ricardo Mendoza Cc: yoichi_yuasa@tripeaks.co.jp, linux-mips@linux-mips.org, ralf@linux-mips.org Subject: Re: [PATCH] vr41xx: fix problem with vr41xx_cpu_wait In-Reply-To: <20080805104314.GB4628@woodpecker.gentoo.org> References: <20080805104314.GB4628@woodpecker.gentoo.org> Organization: TriPeaks Corporation X-Mailer: Sylpheed version 2.3.0beta5 (GTK+ 2.8.20; i486-pc-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20123 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: yoichi_yuasa@tripeaks.co.jp Precedence: bulk X-list: linux-mips Hi Ricardo, On Tue, 5 Aug 2008 10:43:14 +0000 Ricardo Mendoza wrote: > Hello, > > Yoichi, please correct me if I am wrong but I think that the "standby" > instruction does not set IE bit on its own, so calling it with > interrupts disabled will loop the cpu away forever on standby state > being unable to come back due to no interrupts getting through. In VR4100 series User's Manual, it's being written "IE bit of the Status register in the CP0 is also set to 1". Do you have any problem on your board? Yoichi From ricmm@gentoo.org Wed Aug 6 03:08:21 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 06 Aug 2008 03:08:28 +0100 (BST) Received: from smtp.gentoo.org ([140.211.166.183]:52942 "EHLO smtp.gentoo.org") by ftp.linux-mips.org with ESMTP id S20041962AbYHFCIV (ORCPT ); Wed, 6 Aug 2008 03:08:21 +0100 Received: by smtp.gentoo.org (Postfix, from userid 2204) id CBD9966184; Wed, 6 Aug 2008 02:08:18 +0000 (UTC) Date: Wed, 6 Aug 2008 02:08:18 +0000 From: Ricardo Mendoza To: Yoichi Yuasa Cc: linux-mips@linux-mips.org, ralf@linux-mips.org Subject: Re: [PATCH] vr41xx: fix problem with vr41xx_cpu_wait Message-ID: <20080806020818.GA10184@woodpecker.gentoo.org> References: <20080805104314.GB4628@woodpecker.gentoo.org> <200808060147.m761l4Is022564@po-mbox303.hop.2iij.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <200808060147.m761l4Is022564@po-mbox303.hop.2iij.net> User-Agent: Mutt/1.5.16 (2007-06-09) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20124 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ricmm@gentoo.org Precedence: bulk X-list: linux-mips On Wed, Aug 06, 2008 at 10:49:01AM +0900, Yoichi Yuasa wrote: > In VR4100 series User's Manual, it's being written > "IE bit of the Status register in the CP0 is also set to 1". > > Do you have any problem on your board? Hello Yoichi, Just now I got my hands on the manual, I can see that the standby instruction sets IE bit to 1 but only on Vr4131 and Vr4181A cores, all others (such as my Vr4121) need to have interrupts enabled before going into standby. The patch will make it work on all Vr4100 derivates, or we could also add code to build the function depending on CPU type. What do you think? Ricardo From yoichi_yuasa@tripeaks.co.jp Wed Aug 6 05:40:26 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 06 Aug 2008 05:40:34 +0100 (BST) Received: from mo30.po.2iij.net ([210.128.50.53]:8217 "EHLO mo30.po.2iij.net") by ftp.linux-mips.org with ESMTP id S20022654AbYHFEk0 (ORCPT ); Wed, 6 Aug 2008 05:40:26 +0100 Received: by mo.po.2iij.net (mo30) id m764eHH1021767; Wed, 6 Aug 2008 13:40:17 +0900 (JST) Received: from rally.tokyo.tripeaks.co.jp (65.126.232.202.bf.2iij.net [202.232.126.65]) by mbox.po.2iij.net (po-mbox303) id m764eF9I021783 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NOT); Wed, 6 Aug 2008 13:40:16 +0900 Message-Id: <200808060440.m764eF9I021783@po-mbox303.hop.2iij.net> Date: Wed, 6 Aug 2008 13:42:13 +0900 From: Yoichi Yuasa To: Ricardo Mendoza Cc: yoichi_yuasa@tripeaks.co.jp, linux-mips@linux-mips.org, ralf@linux-mips.org Subject: Re: [PATCH] vr41xx: fix problem with vr41xx_cpu_wait In-Reply-To: <20080806020818.GA10184@woodpecker.gentoo.org> References: <20080805104314.GB4628@woodpecker.gentoo.org> <200808060147.m761l4Is022564@po-mbox303.hop.2iij.net> <20080806020818.GA10184@woodpecker.gentoo.org> Organization: TriPeaks Corporation X-Mailer: Sylpheed version 2.3.0beta5 (GTK+ 2.8.20; i486-pc-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20125 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: yoichi_yuasa@tripeaks.co.jp Precedence: bulk X-list: linux-mips Hello Ricardo, On Wed, 6 Aug 2008 02:08:18 +0000 Ricardo Mendoza wrote: > On Wed, Aug 06, 2008 at 10:49:01AM +0900, Yoichi Yuasa wrote: > > > In VR4100 series User's Manual, it's being written > > "IE bit of the Status register in the CP0 is also set to 1". > > > > Do you have any problem on your board? > > Hello Yoichi, > > Just now I got my hands on the manual, I can see that the standby > instruction sets IE bit to 1 but only on Vr4131 and Vr4181A cores, all > others (such as my Vr4121) need to have interrupts enabled before going > into standby. > > The patch will make it work on all Vr4100 derivates, or we could also > add code to build the function depending on CPU type. What do you think? local_irq_disable() is included in the sample code on the User's Manul. I think the following patch is good way of this. Signed-off-by: Yoichi Yuasa diff -pruN -X /home/yuasa/Memo/dontdiff linux-orig/arch/mips/vr41xx/common/pmu.c linux/arch/mips/vr41xx/common/pmu.c --- linux-orig/arch/mips/vr41xx/common/pmu.c 2008-08-06 13:23:55.437185676 +0900 +++ linux/arch/mips/vr41xx/common/pmu.c 2008-08-06 13:32:56.744032999 +0900 @@ -46,11 +46,17 @@ static void __iomem *pmu_base; #define pmu_read(offset) readw(pmu_base + (offset)) #define pmu_write(offset, value) writew((value), pmu_base + (offset)) +static void old_vr41xx_cpu_wait(void) +{ + __asm__("standby;\n"); +} + static void vr41xx_cpu_wait(void) { local_irq_disable(); if (!need_resched()) /* + * VR4181A, VR4131 and later, * "standby" sets IE bit of the CP0_STATUS to 1. */ __asm__("standby;\n"); @@ -124,7 +130,17 @@ static int __init vr41xx_pmu_init(void) return -EBUSY; } - cpu_wait = vr41xx_cpu_wait; + switch (current_cpu_type()) { + case CPU_VR4111: + case CPU_VR4121: + case CPU_VR4122: + cpu_wait = old_vr41xx_cpu_wait; + break; + default: + cpu_wait = vr41xx_cpu_wait; + break; + } + _machine_restart = vr41xx_restart; _machine_halt = vr41xx_halt; pm_power_off = vr41xx_halt; From anemo@mba.ocn.ne.jp Wed Aug 6 14:30:38 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 06 Aug 2008 14:30:41 +0100 (BST) Received: from mba.ocn.ne.jp ([122.1.235.107]:55548 "HELO smtp.mba.ocn.ne.jp") by ftp.linux-mips.org with SMTP id S28576009AbYHFNai (ORCPT ); Wed, 6 Aug 2008 14:30:38 +0100 Received: from localhost (p7186-ipad213funabasi.chiba.ocn.ne.jp [124.85.72.186]) by smtp.mba.ocn.ne.jp (Postfix) with ESMTP id 0074DADA6; Wed, 6 Aug 2008 22:30:32 +0900 (JST) Date: Wed, 06 Aug 2008 22:30:33 +0900 (JST) Message-Id: <20080806.223033.128619389.anemo@mba.ocn.ne.jp> To: yoichi_yuasa@tripeaks.co.jp Cc: ricmm@gentoo.org, linux-mips@linux-mips.org, ralf@linux-mips.org Subject: Re: [PATCH] vr41xx: fix problem with vr41xx_cpu_wait From: Atsushi Nemoto In-Reply-To: <200808060440.m764eF9I021783@po-mbox303.hop.2iij.net> References: <200808060147.m761l4Is022564@po-mbox303.hop.2iij.net> <20080806020818.GA10184@woodpecker.gentoo.org> <200808060440.m764eF9I021783@po-mbox303.hop.2iij.net> X-Fingerprint: 6ACA 1623 39BD 9A94 9B1A B746 CA77 FE94 2874 D52F X-Pgp-Public-Key: http://wwwkeys.pgp.net/pks/lookup?op=get&search=0x2874D52F X-Mailer: Mew version 5.2 on Emacs 21.4 / Mule 5.0 (SAKAKI) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20126 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anemo@mba.ocn.ne.jp Precedence: bulk X-list: linux-mips On Wed, 6 Aug 2008 13:42:13 +0900, Yoichi Yuasa wrote: > > Just now I got my hands on the manual, I can see that the standby > > instruction sets IE bit to 1 but only on Vr4131 and Vr4181A cores, all > > others (such as my Vr4121) need to have interrupts enabled before going > > into standby. > > > > The patch will make it work on all Vr4100 derivates, or we could also > > add code to build the function depending on CPU type. What do you think? > > local_irq_disable() is included in the sample code on the User's Manul. > I think the following patch is good way of this. ... > +static void old_vr41xx_cpu_wait(void) > +{ > + __asm__("standby;\n"); > +} Then, old vr41 CPUs have potential latency problem as like as other CPUs with WAIT instruction. Please refer "WAIT vs. tickless kernel" thread on linux-mips ML archive for details. I don't complain about this patch itself. --- Atsushi Nemoto From ricmm@gentoo.org Wed Aug 6 17:17:14 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 06 Aug 2008 17:17:21 +0100 (BST) Received: from smtp.gentoo.org ([140.211.166.183]:49340 "EHLO smtp.gentoo.org") by ftp.linux-mips.org with ESMTP id S28575897AbYHFQRO (ORCPT ); Wed, 6 Aug 2008 17:17:14 +0100 Received: by smtp.gentoo.org (Postfix, from userid 2204) id 3F91065879; Wed, 6 Aug 2008 16:17:10 +0000 (UTC) Date: Wed, 6 Aug 2008 16:17:10 +0000 From: Ricardo Mendoza To: Atsushi Nemoto Cc: yoichi_yuasa@tripeaks.co.jp, linux-mips@linux-mips.org, ralf@linux-mips.org Subject: Re: [PATCH] vr41xx: fix problem with vr41xx_cpu_wait Message-ID: <20080806161710.GA22957@woodpecker.gentoo.org> References: <200808060147.m761l4Is022564@po-mbox303.hop.2iij.net> <20080806020818.GA10184@woodpecker.gentoo.org> <200808060440.m764eF9I021783@po-mbox303.hop.2iij.net> <20080806.223033.128619389.anemo@mba.ocn.ne.jp> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20080806.223033.128619389.anemo@mba.ocn.ne.jp> User-Agent: Mutt/1.5.16 (2007-06-09) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20127 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ricmm@gentoo.org Precedence: bulk X-list: linux-mips On Wed, Aug 06, 2008 at 10:30:33PM +0900, Atsushi Nemoto wrote: > > local_irq_disable() is included in the sample code on the User's Manul. > > I think the following patch is good way of this. > ... > > +static void old_vr41xx_cpu_wait(void) > > +{ > > + __asm__("standby;\n"); > > +} > > Then, old vr41 CPUs have potential latency problem as like as other > CPUs with WAIT instruction. > > Please refer "WAIT vs. tickless kernel" thread on linux-mips ML > archive for details. > > I don't complain about this patch itself. I see, I hadn't read that thread before. Yoichi's rev of the patch should go in but we should put some effort in finding a better route for CPUs that are not forcefully aware by hardware of interrupts in their wait call. Was some work ever done on Ralf's idea in the "WAIT vs. tickless kernel" ML thread? Regarding patching the return from exception code to contain a check for this particular loop. Ricardo From anemo@mba.ocn.ne.jp Wed Aug 6 18:11:03 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 06 Aug 2008 18:11:09 +0100 (BST) Received: from mba.ocn.ne.jp ([122.1.235.107]:31971 "HELO smtp.mba.ocn.ne.jp") by ftp.linux-mips.org with SMTP id S28576014AbYHFRLD (ORCPT ); Wed, 6 Aug 2008 18:11:03 +0100 Received: from localhost (p7186-ipad213funabasi.chiba.ocn.ne.jp [124.85.72.186]) by smtp.mba.ocn.ne.jp (Postfix) with ESMTP id 85C55AC02; Thu, 7 Aug 2008 02:10:56 +0900 (JST) Date: Thu, 07 Aug 2008 02:10:57 +0900 (JST) Message-Id: <20080807.021057.59650770.anemo@mba.ocn.ne.jp> To: ricmm@gentoo.org Cc: yoichi_yuasa@tripeaks.co.jp, linux-mips@linux-mips.org, ralf@linux-mips.org Subject: Re: [PATCH] vr41xx: fix problem with vr41xx_cpu_wait From: Atsushi Nemoto In-Reply-To: <20080806161710.GA22957@woodpecker.gentoo.org> References: <200808060440.m764eF9I021783@po-mbox303.hop.2iij.net> <20080806.223033.128619389.anemo@mba.ocn.ne.jp> <20080806161710.GA22957@woodpecker.gentoo.org> X-Fingerprint: 6ACA 1623 39BD 9A94 9B1A B746 CA77 FE94 2874 D52F X-Pgp-Public-Key: http://wwwkeys.pgp.net/pks/lookup?op=get&search=0x2874D52F X-Mailer: Mew version 5.2 on Emacs 21.4 / Mule 5.0 (SAKAKI) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20128 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anemo@mba.ocn.ne.jp Precedence: bulk X-list: linux-mips On Wed, 6 Aug 2008 16:17:10 +0000, Ricardo Mendoza wrote: > I see, I hadn't read that thread before. Yoichi's rev of the patch > should go in but we should put some effort in finding a better route for > CPUs that are not forcefully aware by hardware of interrupts in their > wait call. > > Was some work ever done on Ralf's idea in the "WAIT vs. tickless kernel" > ML thread? Regarding patching the return from exception code to contain > a check for this particular loop. Yes. My last proposal is: http://www.linux-mips.org/archives/linux-mips/2007-11/msg00123.html To support vr41's standby instruction in same way, we might have to synthesise rollback_handle_int, etc. or r4k_wait at runtime... --- Atsushi Nemoto From ralf@linux-mips.org Wed Aug 6 18:15:47 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 06 Aug 2008 18:15:53 +0100 (BST) Received: from ditditdahdahdah-dahdahdahditdit.dl5rb.org.uk ([217.169.26.28]:406 "EHLO ditditdahdahdah-dahdahdahditdit.dl5rb.org.uk") by ftp.linux-mips.org with ESMTP id S28576284AbYHFRPr (ORCPT ); Wed, 6 Aug 2008 18:15:47 +0100 Received: from denk.linux-mips.net (denk.linux-mips.net [127.0.0.1]) by ditditdahdahdah-dahdahdahditdit.dl5rb.org.uk (8.14.2/8.14.1) with ESMTP id m76HFYHo005907; Wed, 6 Aug 2008 18:15:34 +0100 Received: (from ralf@localhost) by denk.linux-mips.net (8.14.2/8.14.2/Submit) id m76HFV87005905; Wed, 6 Aug 2008 18:15:31 +0100 Date: Wed, 6 Aug 2008 18:15:31 +0100 From: Ralf Baechle To: Atsushi Nemoto Cc: ricmm@gentoo.org, yoichi_yuasa@tripeaks.co.jp, linux-mips@linux-mips.org Subject: Re: [PATCH] vr41xx: fix problem with vr41xx_cpu_wait Message-ID: <20080806171531.GA5848@linux-mips.org> References: <200808060440.m764eF9I021783@po-mbox303.hop.2iij.net> <20080806.223033.128619389.anemo@mba.ocn.ne.jp> <20080806161710.GA22957@woodpecker.gentoo.org> <20080807.021057.59650770.anemo@mba.ocn.ne.jp> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20080807.021057.59650770.anemo@mba.ocn.ne.jp> User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20129 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Thu, Aug 07, 2008 at 02:10:57AM +0900, Atsushi Nemoto wrote: > http://www.linux-mips.org/archives/linux-mips/2007-11/msg00123.html > > To support vr41's standby instruction in same way, we might have to > synthesise rollback_handle_int, etc. or r4k_wait at runtime... The infrastructure for that is now there :-) Another question of course is if that stuff really deserve this ultimate degree of optimization. Ralf From CFRIESEN@nortel.com Wed Aug 6 19:36:29 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 06 Aug 2008 19:36:37 +0100 (BST) Received: from zrtps0kp.nortel.com ([47.140.192.56]:28856 "EHLO zrtps0kp.nortel.com") by ftp.linux-mips.org with ESMTP id S28575446AbYHFSg3 (ORCPT ); Wed, 6 Aug 2008 19:36:29 +0100 Received: from zcarhxs1.corp.nortel.com (zcarhxs1.corp.nortel.com [47.129.230.89]) by zrtps0kp.nortel.com (Switch-2.2.6/Switch-2.2.0) with ESMTP id m76IaJI02096; Wed, 6 Aug 2008 18:36:20 GMT Received: from [47.130.64.42] ([47.130.64.42] RDNS failed) by zcarhxs1.corp.nortel.com with Microsoft SMTPSVC(6.0.3790.3959); Wed, 6 Aug 2008 14:36:16 -0400 Message-ID: <4899EF0E.705@nortel.com> Date: Wed, 06 Aug 2008 12:35:58 -0600 From: "Chris Friesen" User-Agent: Mozilla Thunderbird 1.0.2-6 (X11/20050513) X-Accept-Language: en-us, en MIME-Version: 1.0 To: Ralf Baechle CC: linux-mips@linux-mips.org Subject: Re: looking for help interpreting softlockup/stack trace References: <48989AFE.5000500@nortel.com> <20080805191618.GB8629@linux-mips.org> In-Reply-To: <20080805191618.GB8629@linux-mips.org> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 06 Aug 2008 18:36:17.0773 (UTC) FILETIME=[506159D0:01C8F7F3] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20130 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: cfriesen@nortel.com Precedence: bulk X-list: linux-mips Ralf Baechle wrote: > $LBB378 is an internal symbol. The value of RA may not be very informative > if it was overwritten by a random subroutine call. What determines which function names get compiled into the object file, and which ones get these numerical symbols? > You may also try lockdep; it gives much more detailed information though > it's more heavyweight. I would love to be able to use lockdep...however I'm stuck on an old kernel. Chris From ddaney@avtrex.com Wed Aug 6 19:57:47 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 06 Aug 2008 19:57:51 +0100 (BST) Received: from smtp1.dnsmadeeasy.com ([205.234.170.134]:42724 "EHLO smtp1.dnsmadeeasy.com") by ftp.linux-mips.org with ESMTP id S28575597AbYHFS5r (ORCPT ); Wed, 6 Aug 2008 19:57:47 +0100 Received: from smtp1.dnsmadeeasy.com (localhost [127.0.0.1]) by smtp1.dnsmadeeasy.com (Postfix) with ESMTP id C707F320413; Wed, 6 Aug 2008 18:57:47 +0000 (UTC) X-Authenticated-Name: js.dnsmadeeasy X-Transit-System: In case of SPAM please contact abuse@dnsmadeeasy.com Received: from avtrex.com (unknown [67.116.42.147]) by smtp1.dnsmadeeasy.com (Postfix) with ESMTP; Wed, 6 Aug 2008 18:57:47 +0000 (UTC) Received: from dl2.hq2.avtrex.com ([192.168.7.26]) by avtrex.com with Microsoft SMTPSVC(6.0.3790.1830); Wed, 6 Aug 2008 11:57:33 -0700 Message-ID: <4899F41C.5070401@avtrex.com> Date: Wed, 06 Aug 2008 11:57:32 -0700 From: David Daney User-Agent: Thunderbird 2.0.0.14 (X11/20080501) MIME-Version: 1.0 To: Ralf Baechle Cc: Chris Friesen , linux-mips@linux-mips.org Subject: Re: looking for help interpreting softlockup/stack trace References: <48989AFE.5000500@nortel.com> <20080805191618.GB8629@linux-mips.org> In-Reply-To: <20080805191618.GB8629@linux-mips.org> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 06 Aug 2008 18:57:33.0607 (UTC) FILETIME=[48D62B70:01C8F7F6] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20131 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@avtrex.com Precedence: bulk X-list: linux-mips Ralf Baechle wrote: > On Tue, Aug 05, 2008 at 12:25:02PM -0600, Chris Friesen wrote: > >> I've run into an interesting issue with an Octeon-based board, where it >> just seems to hang. I suspect we're hitting some kind of locking bug, >> and I'm trying to track it down. If it matters, the kernel is quite old >> (heavily patched 2.6.14) and I've got no chance of upgrading it. (The >> usual embedded scenario.) >> >> I've added some scheduler instrumentation, as well as adding a stack >> dump to the output of the softlockup code. >> >> In the trace below, is "epc" the program counter at the time of the >> timer interrupt? How does "ra" fit into this, given that the function >> whose address it contains isn't seen in the stack trace until quite a >> ways down? > > $LBB378 is an internal symbol. The value of RA may not be very informative > if it was overwritten by a random subroutine call. > I have thought about eliminating these internal labels when the module's symbols are read. Would this make any sense? David Daney From khickey@rmicorp.com Wed Aug 6 20:50:18 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 06 Aug 2008 20:50:21 +0100 (BST) Received: from mx1.razamicroelectronics.com ([63.111.213.197]:51228 "EHLO hq-ex-mb01.razamicroelectronics.com") by ftp.linux-mips.org with ESMTP id S28576913AbYHFTuS convert rfc822-to-8bit (ORCPT ); Wed, 6 Aug 2008 20:50:18 +0100 Received: from 10.8.0.25 ([10.8.0.25]) by hq-ex-mb01.razamicroelectronics.com ([10.1.1.40]) via Exchange Front-End Server webmail.razamicroelectronics.com ([10.1.1.41]) with Microsoft Exchange Server HTTP-DAV ; Wed, 6 Aug 2008 19:50:10 +0000 Received: from kh-ubuntu by webmail.razamicroelectronics.com; 06 Aug 2008 14:50:35 -0500 Subject: Re: [PATCH] Alchemy: register mmc platform device for db1200/pb1200 boards From: Kevin Hickey To: Manuel Lauss Cc: Ralf Baechle , linux-mips@linux-mips.org In-Reply-To: <20080805175126.GA29618@roarinelk.homelinux.net> References: <20080805175126.GA29618@roarinelk.homelinux.net> Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8BIT Date: Wed, 06 Aug 2008 14:50:33 -0500 Message-Id: <1218052233.3808.3.camel@kh-ubuntu.razamicroelectronics.com> Mime-Version: 1.0 X-Mailer: Evolution 2.22.3.1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20132 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: khickey@rmicorp.com Precedence: bulk X-list: linux-mips On Tue, 2008-08-05 at 19:51 +0200, Manuel Lauss wrote: > Add au1xmmc platform data for PB1200/DB1200 boards, and wire up > the 2 SD controllers for them. > > Signed-off-by: Manuel Lauss This one looks good to me, especially combined with the "au1xmmc: raise segment size limit" patch that Manuel submitted on July 29. Acked-by: Kevin Hickey -- Kevin Hickey Alchemy Solutions RMI Corporation khickey@RMICorp.com P: 512.691.8044 From khickey@rmicorp.com Wed Aug 6 20:52:24 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 06 Aug 2008 20:52:31 +0100 (BST) Received: from mx1.razamicroelectronics.com ([63.111.213.197]:286 "EHLO hq-ex-mb01.razamicroelectronics.com") by ftp.linux-mips.org with ESMTP id S28576983AbYHFTwY convert rfc822-to-8bit (ORCPT ); Wed, 6 Aug 2008 20:52:24 +0100 Received: from 10.8.0.25 ([10.8.0.25]) by hq-ex-mb01.razamicroelectronics.com ([10.1.1.40]) via Exchange Front-End Server webmail.razamicroelectronics.com ([10.1.1.41]) with Microsoft Exchange Server HTTP-DAV ; Wed, 6 Aug 2008 19:52:13 +0000 Received: from kh-ubuntu by webmail.razamicroelectronics.com; 06 Aug 2008 14:52:39 -0500 Subject: Re: [PATCH v2] au1xmmc: raise segment size limit. From: Kevin Hickey To: Manuel Lauss Cc: Pierre Ossman , Sergei Shtylyov , linux-mips@linux-mips.org In-Reply-To: <20080729081049.GB3908@roarinelk.homelinux.net> References: <20080729081049.GB3908@roarinelk.homelinux.net> Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8BIT Date: Wed, 06 Aug 2008 14:52:35 -0500 Message-Id: <1218052355.3808.4.camel@kh-ubuntu.razamicroelectronics.com> Mime-Version: 1.0 X-Mailer: Evolution 2.22.3.1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20133 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: khickey@rmicorp.com Precedence: bulk X-list: linux-mips On Tue, 2008-07-29 at 10:10 +0200, Manuel Lauss wrote: > --- > > Raise the DMA block size limit from 2048 bytes to the maximum supported > by the DMA controllers on the chip (64KB on Au1100, 4MB on Au1200). > > This gives a very small performance boost and apparently fixes an oops > when MMC-DMA and network traffic are active at the same time. > > Signed-off-by: Manuel Lauss I tested this in conjunction with "Alchemy: register platform device for db1200..." successfully. Acked-by: Kevin Hickey -- Kevin Hickey Alchemy Solutions RMI Corporation khickey@RMICorp.com P: 512.691.8044 From khickey@rmicorp.com Wed Aug 6 21:38:47 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 06 Aug 2008 21:38:50 +0100 (BST) Received: from mx1.razamicroelectronics.com ([63.111.213.197]:11590 "EHLO hq-ex-mb01.razamicroelectronics.com") by ftp.linux-mips.org with ESMTP id S28577097AbYHFUir convert rfc822-to-8bit (ORCPT ); Wed, 6 Aug 2008 21:38:47 +0100 Received: from 10.8.0.25 ([10.8.0.25]) by hq-ex-mb01.razamicroelectronics.com ([10.1.1.40]) via Exchange Front-End Server webmail.razamicroelectronics.com ([10.1.1.41]) with Microsoft Exchange Server HTTP-DAV ; Wed, 6 Aug 2008 20:38:38 +0000 Received: from kh-ubuntu by webmail.razamicroelectronics.com; 06 Aug 2008 15:39:04 -0500 Subject: Re: [PATCH v4 0/10] Alchemy updates. From: Kevin Hickey To: Manuel Lauss Cc: linux-mips@linux-mips.org In-Reply-To: <20080729165853.GB8784@roarinelk.homelinux.net> References: <20080729165853.GB8784@roarinelk.homelinux.net> Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8BIT Date: Wed, 06 Aug 2008 15:39:03 -0500 Message-Id: <1218055143.3808.9.camel@kh-ubuntu.razamicroelectronics.com> Mime-Version: 1.0 X-Mailer: Evolution 2.22.3.1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20134 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: khickey@rmicorp.com Precedence: bulk X-list: linux-mips Manuel et al., I've tested these patches on a DB1200 board and they look good. I have an Au1xxx IDE power management patch that depends on them that I can release after they've been applied. One catch - these no longer apply to the latest HEAD. Manuel, can you re-spin and re-post them one more time? -Kevin On Tue, 2008-07-29 at 18:58 +0200, Manuel Lauss wrote: > Hello, > > Here's again a new set of patches to modernize Alchemy setup and PM code. > All patches have been compile-tested with db1100 and db1200 defconfigs, > and have been runnning on a few custom Au1250 boards for now more than > 5 weeks. I've suspended and resumed a few hundred times while stressing > the system (continuous SD + CF reads while playing some wave files and > compiling sources). > > #1 removes unused functions > #2 removes the cpu_table and replaces it with simpler code (IMHO of course) > #3 enables use of cp0 counter as a fallback, > #4 clockevent/clocksource support using one of the 2 counters of the Au1xxx > this also enables the use of the 'wait' instruction; depends on #3 > #5 cleanup made possible with #4 > #7 and #8 fix suspend/resume. > #9 adds DBDMA suspend/resume support. > #10 replaces sysctl suspend interface with something better (IMO). > > All patches depend on each other, have been run-tested on a custom AU1200 > system and compile-tested with a minimal config on db1100 and db1200. > > Changes V3->V4: > - rediffed against 2.6.27-rc1 > - add patch #10. > > Changes V2->V3: > - swap patches 1 and 2 > - minor refinements, no function changes. > > Changes V1->V2: > - address Sergei's comments wrt. config[OD] handling > - change TOY clocksource to RTC clocksource > - add another patch (#5) > > > arch/mips/Kconfig | 8 > arch/mips/au1000/Kconfig | 4 > arch/mips/au1000/common/Makefile | 4 > arch/mips/au1000/common/clocks.c | 65 +++-- > arch/mips/au1000/common/cputable.c | 52 ---- > arch/mips/au1000/common/dbdma.c | 65 +++++ > arch/mips/au1000/common/dbg_io.c | 4 > arch/mips/au1000/common/irq.c | 57 ---- > arch/mips/au1000/common/platform.c | 257 ++++++++++++++++++++ > arch/mips/au1000/common/power.c | 421 ++++++---------------------------- > arch/mips/au1000/common/setup.c | 39 --- > arch/mips/au1000/common/sleeper.S | 121 +++++---- > arch/mips/au1000/common/time.c | 305 ++++++++---------------- > arch/mips/au1000/db1x00/Makefile | 1 > arch/mips/au1000/mtx-1/Makefile | 2 > arch/mips/au1000/pb1000/Makefile | 1 > arch/mips/au1000/pb1100/Makefile | 1 > arch/mips/au1000/pb1200/Makefile | 2 > arch/mips/au1000/pb1500/Makefile | 1 > arch/mips/au1000/pb1550/Makefile | 1 > arch/mips/au1000/xxs1500/Makefile | 1 > arch/mips/kernel/Makefile | 4 > arch/mips/kernel/cevt-r4k.c | 2 > arch/mips/kernel/csrc-r4k.c | 2 > include/asm-mips/mach-au1x00/au1000.h | 64 +++-- > include/asm-mips/time.h | 24 + > 26 files changed, 719 insertions(+), 789 deletions(-) > > Thanks, > Manuel Lauss > -- Kevin Hickey Alchemy Solutions RMI Corporation khickey@RMICorp.com P: 512.691.8044 From drzeus@drzeus.cx Wed Aug 6 21:53:01 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 06 Aug 2008 21:53:09 +0100 (BST) Received: from server.drzeus.cx ([85.8.24.28]:56497 "EHLO smtp.drzeus.cx") by ftp.linux-mips.org with ESMTP id S28577396AbYHFUxB (ORCPT ); Wed, 6 Aug 2008 21:53:01 +0100 Received: from mjolnir.drzeus.cx (gateway.teknikservice.nu [::ffff:213.134.106.48]) (AUTH: LOGIN drzeus, TLS: TLSv1/SSLv3,256bits,AES256-SHA) by smtp.drzeus.cx with esmtp; Wed, 06 Aug 2008 22:52:45 +0200 id 0000000000130003.00000000489A0F1E.000058A8 Date: Wed, 6 Aug 2008 22:52:29 +0200 From: Pierre Ossman To: "Kevin Hickey" Cc: "Manuel Lauss" , "Sergei Shtylyov" , linux-mips@linux-mips.org Subject: Re: [PATCH v2] au1xmmc: raise segment size limit. Message-ID: <20080806225229.7914d736@mjolnir.drzeus.cx> In-Reply-To: <1218052355.3808.4.camel@kh-ubuntu.razamicroelectronics.com> References: <20080729081049.GB3908@roarinelk.homelinux.net> <1218052355.3808.4.camel@kh-ubuntu.razamicroelectronics.com> X-Mailer: Claws Mail 3.4.0 (GTK+ 2.13.5; i386-redhat-linux-gnu) Mime-Version: 1.0 Content-Type: multipart/signed; protocol="application/pgp-signature"; micalg=PGP-SHA1; boundary="=_freyr.drzeus.cx-22696-1218055969-0001-2" Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20135 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: drzeus@drzeus.cx Precedence: bulk X-list: linux-mips This is a MIME-formatted message. If you see this text it means that your E-mail software does not support MIME-formatted messages. --=_freyr.drzeus.cx-22696-1218055969-0001-2 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: quoted-printable On Wed, 6 Aug 2008 12:52:35 -0700 "Kevin Hickey" wrote: > On Tue, 2008-07-29 at 10:10 +0200, Manuel Lauss wrote: > > ---=20 > >=20 > > Raise the DMA block size limit from 2048 bytes to the maximum supported > > by the DMA controllers on the chip (64KB on Au1100, 4MB on Au1200). > >=20 > > This gives a very small performance boost and apparently fixes an oops > > when MMC-DMA and network traffic are active at the same time. > >=20 > > Signed-off-by: Manuel Lauss > I tested this in conjunction with "Alchemy: register platform device for > db1200..." successfully. >=20 > Acked-by: Kevin Hickey You're about a week too late ;) --=20 -- Pierre Ossman WARNING: This correspondence is being monitored by the Swedish government. Make sure your server uses encryption for SMTP traffic and consider using PGP for end-to-end encryption. --=_freyr.drzeus.cx-22696-1218055969-0001-2 Content-Type: application/pgp-signature; name="signature.asc" Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename=signature.asc -----BEGIN PGP SIGNATURE----- Version: GnuPG v2.0.9 (GNU/Linux) iEYEARECAAYFAkiaDxAACgkQ7b8eESbyJLj2iwCgky1fYPgGVlFjn5Wiv3sGJxZF J74AnjHo4SjnoQynD1MHQ3bVYgxv6SZq =+HL8 -----END PGP SIGNATURE----- --=_freyr.drzeus.cx-22696-1218055969-0001-2-- From khickey@rmicorp.com Wed Aug 6 22:07:50 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 06 Aug 2008 22:07:57 +0100 (BST) Received: from mx1.razamicroelectronics.com ([63.111.213.197]:55902 "EHLO hq-ex-mb01.razamicroelectronics.com") by ftp.linux-mips.org with ESMTP id S28576560AbYHFVHu (ORCPT ); Wed, 6 Aug 2008 22:07:50 +0100 Received: from 10.8.0.25 ([10.8.0.25]) by hq-ex-mb01.razamicroelectronics.com ([10.1.1.40]) via Exchange Front-End Server webmail.razamicroelectronics.com ([10.1.1.41]) with Microsoft Exchange Server HTTP-DAV ; Wed, 6 Aug 2008 21:07:42 +0000 Received: from kh-ubuntu by webmail.razamicroelectronics.com; 06 Aug 2008 16:08:08 -0500 Subject: Re: [PATCH v2] au1xmmc: raise segment size limit. From: Kevin Hickey To: Pierre Ossman Cc: Manuel Lauss , Sergei Shtylyov , linux-mips@linux-mips.org In-Reply-To: <20080806225229.7914d736@mjolnir.drzeus.cx> References: <20080729081049.GB3908@roarinelk.homelinux.net> <1218052355.3808.4.camel@kh-ubuntu.razamicroelectronics.com> <20080806225229.7914d736@mjolnir.drzeus.cx> Content-Type: text/plain Content-Transfer-Encoding: 7bit Date: Wed, 06 Aug 2008 16:08:08 -0500 Message-Id: <1218056888.3808.10.camel@kh-ubuntu.razamicroelectronics.com> Mime-Version: 1.0 X-Mailer: Evolution 2.22.3.1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20136 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: khickey@rmicorp.com Precedence: bulk X-list: linux-mips Has this been applied? If so, where? I don't see it in the LMO master tree... (though I have been known to experience temporary blindness...) -Kevin On Wed, 2008-08-06 at 22:52 +0200, Pierre Ossman wrote: > On Wed, 6 Aug 2008 12:52:35 -0700 > "Kevin Hickey" wrote: > > > On Tue, 2008-07-29 at 10:10 +0200, Manuel Lauss wrote: > > > --- > > > > > > Raise the DMA block size limit from 2048 bytes to the maximum supported > > > by the DMA controllers on the chip (64KB on Au1100, 4MB on Au1200). > > > > > > This gives a very small performance boost and apparently fixes an oops > > > when MMC-DMA and network traffic are active at the same time. > > > > > > Signed-off-by: Manuel Lauss > > I tested this in conjunction with "Alchemy: register platform device for > > db1200..." successfully. > > > > Acked-by: Kevin Hickey > > You're about a week too late ;) From drzeus@drzeus.cx Wed Aug 6 22:40:33 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 06 Aug 2008 22:40:40 +0100 (BST) Received: from server.drzeus.cx ([85.8.24.28]:53377 "EHLO smtp.drzeus.cx") by ftp.linux-mips.org with ESMTP id S28576846AbYHFVkd (ORCPT ); Wed, 6 Aug 2008 22:40:33 +0100 Received: from mjolnir.drzeus.cx (gateway.teknikservice.nu [::ffff:213.134.106.48]) (AUTH: LOGIN drzeus, TLS: TLSv1/SSLv3,256bits,AES256-SHA) by smtp.drzeus.cx with esmtp; Wed, 06 Aug 2008 23:40:30 +0200 id 0000000000130003.00000000489A1A4E.00005A50 Date: Wed, 6 Aug 2008 23:40:23 +0200 From: Pierre Ossman To: Kevin Hickey Cc: Manuel Lauss , Sergei Shtylyov , linux-mips@linux-mips.org Subject: Re: [PATCH v2] au1xmmc: raise segment size limit. Message-ID: <20080806234023.4394a790@mjolnir.drzeus.cx> In-Reply-To: <1218056888.3808.10.camel@kh-ubuntu.razamicroelectronics.com> References: <20080729081049.GB3908@roarinelk.homelinux.net> <1218052355.3808.4.camel@kh-ubuntu.razamicroelectronics.com> <20080806225229.7914d736@mjolnir.drzeus.cx> <1218056888.3808.10.camel@kh-ubuntu.razamicroelectronics.com> X-Mailer: Claws Mail 3.4.0 (GTK+ 2.13.5; i386-redhat-linux-gnu) Mime-Version: 1.0 Content-Type: multipart/signed; protocol="application/pgp-signature"; micalg=PGP-SHA1; boundary="=_freyr.drzeus.cx-23120-1218058831-0001-2" Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20137 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: drzeus@drzeus.cx Precedence: bulk X-list: linux-mips This is a MIME-formatted message. If you see this text it means that your E-mail software does not support MIME-formatted messages. --=_freyr.drzeus.cx-23120-1218058831-0001-2 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: quoted-printable On Wed, 06 Aug 2008 16:08:08 -0500 Kevin Hickey wrote: > Has this been applied? If so, where? I don't see it in the LMO master > tree... (though I have been known to experience temporary blindness...) >=20 http://git.kernel.org/?p=3Dlinux/kernel/git/torvalds/linux-2.6.git;a=3Dcomm= it;h=3De491d230fd398bb730e3c2dd734c5447463b9d38 --=20 -- Pierre Ossman WARNING: This correspondence is being monitored by the Swedish government. Make sure your server uses encryption for SMTP traffic and consider using PGP for end-to-end encryption. --=_freyr.drzeus.cx-23120-1218058831-0001-2 Content-Type: application/pgp-signature; name="signature.asc" Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename=signature.asc -----BEGIN PGP SIGNATURE----- Version: GnuPG v2.0.9 (GNU/Linux) iEYEARECAAYFAkiaGksACgkQ7b8eESbyJLip5wCeNcmbbvECTQOBxfxUN/xeCdpU wDcAoNricAP06Qv6xGUt890bBCnnHrH8 =fNDW -----END PGP SIGNATURE----- --=_freyr.drzeus.cx-23120-1218058831-0001-2-- From khickey@rmicorp.com Wed Aug 6 22:48:44 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 06 Aug 2008 22:48:54 +0100 (BST) Received: from mx1.razamicroelectronics.com ([63.111.213.197]:3721 "EHLO hq-ex-mb01.razamicroelectronics.com") by ftp.linux-mips.org with ESMTP id S28577327AbYHFVso convert rfc822-to-8bit (ORCPT ); Wed, 6 Aug 2008 22:48:44 +0100 Received: from 10.8.0.25 ([10.8.0.25]) by hq-ex-mb01.razamicroelectronics.com ([10.1.1.40]) via Exchange Front-End Server webmail.razamicroelectronics.com ([10.1.1.41]) with Microsoft Exchange Server HTTP-DAV ; Wed, 6 Aug 2008 21:48:35 +0000 Received: from kh-ubuntu by webmail.razamicroelectronics.com; 06 Aug 2008 16:49:01 -0500 Subject: Re: [PATCH v2] au1xmmc: raise segment size limit. From: Kevin Hickey To: Pierre Ossman Cc: Manuel Lauss , Sergei Shtylyov , linux-mips@linux-mips.org In-Reply-To: <20080806234023.4394a790@mjolnir.drzeus.cx> References: <20080729081049.GB3908@roarinelk.homelinux.net> <1218052355.3808.4.camel@kh-ubuntu.razamicroelectronics.com> <20080806225229.7914d736@mjolnir.drzeus.cx> <1218056888.3808.10.camel@kh-ubuntu.razamicroelectronics.com> <20080806234023.4394a790@mjolnir.drzeus.cx> Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8BIT Date: Wed, 06 Aug 2008 16:49:01 -0500 Message-Id: <1218059341.3808.12.camel@kh-ubuntu.razamicroelectronics.com> Mime-Version: 1.0 X-Mailer: Evolution 2.22.3.1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20138 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: khickey@rmicorp.com Precedence: bulk X-list: linux-mips I see... Thanks. On Wed, 2008-08-06 at 23:40 +0200, Pierre Ossman wrote: > On Wed, 06 Aug 2008 16:08:08 -0500 > Kevin Hickey wrote: > > > Has this been applied? If so, where? I don't see it in the LMO master > > tree... (though I have been known to experience temporary blindness...) > > > > http://git.kernel.org/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commit;h=e491d230fd398bb730e3c2dd734c5447463b9d38 > -- Kevin Hickey Alchemy Solutions RMI Corporation khickey@RMICorp.com P: 512.691.8044 From dvomlehn@cisco.com Thu Aug 7 03:10:14 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 07 Aug 2008 03:10:19 +0100 (BST) Received: from rtp-iport-2.cisco.com ([64.102.122.149]:8217 "EHLO rtp-iport-2.cisco.com") by ftp.linux-mips.org with ESMTP id S28578001AbYHGCKO (ORCPT ); Thu, 7 Aug 2008 03:10:14 +0100 X-IronPort-AV: E=Sophos;i="4.31,318,1215388800"; d="scan'208";a="16723693" Received: from rtp-dkim-2.cisco.com ([64.102.121.159]) by rtp-iport-2.cisco.com with ESMTP; 07 Aug 2008 02:10:02 +0000 Received: from rtp-core-1.cisco.com (rtp-core-1.cisco.com [64.102.124.12]) by rtp-dkim-2.cisco.com (8.12.11/8.12.11) with ESMTP id m772A2aM000377 for ; Wed, 6 Aug 2008 22:10:02 -0400 Received: from sausatlsmtp1.sciatl.com ([192.133.217.33]) by rtp-core-1.cisco.com (8.13.8/8.13.8) with ESMTP id m772A1db012154 for ; Thu, 7 Aug 2008 02:10:01 GMT Received: from default.com ([192.133.217.33]) by sausatlsmtp1.sciatl.com with Microsoft SMTPSVC(6.0.3790.3959); Wed, 6 Aug 2008 22:10:01 -0400 Received: from sausatlbhs01.corp.sa.net ([192.133.216.76]) by sausatlsmtp1.sciatl.com with Microsoft SMTPSVC(6.0.3790.3959); Wed, 6 Aug 2008 22:10:00 -0400 Received: from [127.0.0.1] ([64.101.20.200]) by sausatlbhs01.corp.sa.net with Microsoft SMTPSVC(6.0.3790.3959); Wed, 6 Aug 2008 22:09:59 -0400 Message-ID: <489A5975.1000401@cisco.com> Date: Wed, 06 Aug 2008 19:09:57 -0700 From: David VomLehn User-Agent: Thunderbird 2.0.0.16 (Windows/20080708) MIME-Version: 1.0 To: "linux-mips@linux-mips.org" Subject: Anyone noticed that there are a lot of cache flushes after kunmap/kunmap_atomic is called? Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 07 Aug 2008 02:09:59.0606 (UTC) FILETIME=[B1DB6D60:01C8F832] X-ST-MF-Message-Resent: 8/6/2008 22:10 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; l=1390; t=1218075002; x=1218939002; c=relaxed/simple; s=rtpdkim2001; h=Content-Type:From:Subject:Content-Transfer-Encoding:MIME-Version; d=cisco.com; i=dvomlehn@cisco.com; z=From:=20David=20VomLehn=20 |Subject:=20Anyone=20noticed=20that=20there=20are=20a=20lot =20of=20cache=20flushes=20after=20kunmap/kunmap_atomic=0A=20 is=20called? |Sender:=20 |To:=20=22linux-mips@linux-mips.org=22=20; bh=NR4um0HgShbaVpa8cIkzGCo8j7OVzDPWzr9KJ+kmyDU=; b=xxn0K8LLtTip2Qpbd9QXnrum6JNI7Y1RzeGLbBfScZoyn1uzaGvBS5H9Iy rVR8xh+hbU5Arssh4NqqCSXMaioUMevK6ozYu7CyVMc8fbmKEMhAUXu3otvZ z63jSKxky9; Authentication-Results: rtp-dkim-2; header.From=dvomlehn@cisco.com; dkim=pass ( sig from cisco.com/rtpdkim2001 verified; ); Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20139 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dvomlehn@cisco.com Precedence: bulk X-list: linux-mips On the MIPS processor, cache flushing is done based on virtual addresses. However, in the Linux kernel, there are a lot of places where memory is mapped with kmap or kmap_atomic, then unmapped with the corresponding kunmap or kunmap_atomic and only *then* is the cache flushed. In other words, we only flush the cache after we have dropped the mapping of memory into a virtual address. I think this is generally wrong. This may really only affect those of us who have enabled high memory, but it's pretty prevalent in kernel code. We noted this before, but have apparently just been bitten by it. Is it just me or is there a fairly widespread problem for processors that flush the cache using virtual addresses? - - - - - Cisco - - - - - This e-mail and any attachments may contain information which is confidential, proprietary, privileged or otherwise protected by law. The information is solely intended for the named addressee (or a person responsible for delivering it to the addressee). If you are not the intended recipient of this message, you are not authorized to read, print, retain, copy or disseminate this message or any part of it. If you have received this e-mail in error, please notify the sender immediately by return e-mail and delete it from your computer. From maowy@avit.org.cn Thu Aug 7 05:19:46 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 07 Aug 2008 05:19:54 +0100 (BST) Received: from ws02.shaidc.com ([218.78.208.152]:38637 "HELO ws01.shaidc.com") by ftp.linux-mips.org with SMTP id S20023167AbYHGETq convert rfc822-to-8bit (ORCPT ); Thu, 7 Aug 2008 05:19:46 +0100 X-Lasthop: 222.66.84.134 Received: from unknown (helo GHOST-E2417EF88)(unknown@222.66.84.134) by ws01.shaidc.com with SMTP; Thu, 07 Aug 2008 04:40:46 +0000 From: "maowy" To: borasah@netone.com.tr CC: linux-mips-bounce@linux-mips.org , linux-mips@linux-mips.org Subject: Au1550 Nandflash X-mailer: Foxmail 4.2 [cn] Mime-Version: 1.0 Content-Type: text/plain; charset="GB2312" Content-Transfer-Encoding: 8BIT Date: Thu, 7 Aug 2008 12:16:19 +0800 Message-Id: Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20140 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: maowy@avit.org.cn Precedence: bulk X-list: linux-mips borasahã I have the same problem with you when using nandflash. Our kernel can recognize nandflash but it seems to be all bad block. How dou you successfully solve this problem of nandflash . Can you tell how to solve this problem. Hope to receive your letter as soon as possible.Thanks. our platform:AU1550 OS:linux-2.6.13 Our kernel information is following: Kernel command line: root=/dev/nfs rw nfsroot=192.168.15.6:/nfs noinitrd init=/linuxrc ip=192.168.15.4::192.168.15.254:255.255.255.0:DVR:eth0:off console=ttyS0,115200 Primary instruction cache 16kB, physically tagged, 4-way, linesize 32 bytes. Primary data cache 16kB, 4-way, linesize 32 bytes. Synthesized TLB refill handler (17 instructions). Synthesized TLB load handler fastpath (34 instructions). Synthesized TLB store handler fastpath (34 instructions). Synthesized TLB modify handler fastpath (33 instructions). PID hash table entries: 512 (order: 9, 8192 bytes) calculating r4koff... 00060ae0(396000) Using 396.000 MHz high precision timer. Console: colour dummy device 80x25 Dentry cache hash table entries: 16384 (order: 4, 65536 bytes) Inode-cache hash table entries: 8192 (order: 3, 32768 bytes) Memory: 59520k/65536k available (3296k kernel code, 5948k reserved, 704k data, 148k init, 0k highmem) Mount-cache hash table entries: 512 (order: 0, 4096 bytes) Checking for 'wait' instruction... unavailable. NET: Registered protocol family 16 virt_io_addr = 0xc0000000 mhd : start AUTO SCAN !!!!!!!!!!!!!!!!!!!!!!!!! mhd : test is test by mhd! Autoconfig PCI channel 0x804c1f5c Scanning bus 00, I/O 0x00001000:0x00100000, Mem 0x40000000:0x50000000 MHD : Scanning bus 00 .... Liqiang: pci configuration space read devfn = 00, vendor id = ffff Liqiang: pci configuration space read devfn = 08, vendor id = ffff Liqiang: pci configuration space read devfn = 10, vendor id = ffff Liqiang: pci configuration space read devfn = 18, vendor id = ffff Liqiang: pci configuration space read devfn = 20, vendor id = ffff Liqiang: pci configuration space read devfn = 28, vendor id = ffff Liqiang: pci configuration space read devfn = 30, vendor id = ffff Liqiang: pci configuration space read devfn = 38, vendor id = ffff Liqiang: pci configuration space read devfn = 40, vendor id = ffff Liqiang: pci configuration space read devfn = 48, vendor id = ffff Liqiang: pci configuration space read devfn = 50, vendor id = ffff Liqiang: pci configuration space read devfn = 58, vendor id = ffff Liqiang: pci configuration space read devfn = 60, vendor id = 16f4 00:0c.0 Class 0400: 16f4:8000 Mem at 0x40000000 [size=0x20000] Mem at 0x40020000 [size=0x1000] Mem at 0x40021000 [size=0x1000] Liqiang: pci configuration space read devfn = 68, vendor id = ffff Liqiang: pci configuration space read devfn = 70, vendor id = ffff Liqiang: pci configuration space read devfn = 78, vendor id = ffff Liqiang: pci configuration space read devfn = 80, vendor id = ffff Liqiang: pci configuration space read devfn = 88, vendor id = ffff Liqiang: pci configuration space read devfn = 90, vendor id = ffff mhd : AUTO SCAN FINISHED!!!!!!!!!!!!!!!!!!!!!!!!! Scanning bus 00 Found 00:60 [16f4/8000] 000400 00 Fixups for bus 00 Bus scan for 00 returning with max=00 mhd : pin=0x1, slot=0xc PCI fixup irq: (0000:00:0c.0) got 1 Au1XXX Real Time Clock Driver v1.0 Installing knfsd (copyright (C) 1996 okir@monad.swb.de). JFFS2 version 2.2. (C) 2001-2003 Red Hat, Inc. SGI XFS with no debug enabled yaffs Jul 30 2008 15:35:27 Installing. Initializing Cryptographic API pci_hotplug: PCI Hot Plug PCI Core version: 0.5 i2c /dev entries driver Au1550 I2C: <7>i2c_adapter i2c-0: Registered as minor 0 Au1550 I2C initialized. Serial: Au1x00 driver ttyS0 at I/O 0xb1100000 (irq = 0) is a AU1X00_UART ttyS1 at I/O 0xb1200000 (irq = 8) is a AU1X00_UART ttyS2 at I/O 0xb1400000 (irq = 9) is a AU1X00_UART io scheduler noop registered io scheduler anticipatory registered io scheduler deadline registered io scheduler cfq registered RAMDISK driver initialized: 16 RAM disks of 16384K size 1024 blocksize loop: loaded (max 8 devices) au1000eth version 1.5 Pete Popov eth0: Au1x Ethernet found at 0xb0500000, irq 27 mhd: get PHY ID = 0 8201 eth0: REALTEK RTL8201CP 10/1000 BaseT PHY at phy address 1 begin to init the network-mac0 and mac1 Mac0_MII_CONTROL_phy_addr: 00000001 Mac0_MII_CONTROL_val_before_write: 00003100 Mac0_MII_CONTROL_value_after_write: 00002100 Mac0_10/100 and Half/Full duplex val_before wrtie: 000001e1 Mac0_10/100 and Half/Full duplex val_after write: 000001e1 Mac0_Restart auto-negotiatio val before berfore write: 00002100 Mac0_Restart auto-negotiatio val before write: 00002100 Mac0_Restart auto-negotiation val_after write: 00002100 eth0: Using REALTEK RTL8201CP 10/1000 BaseT PHY as default eth1: Au1x Ethernet found at 0xb0510000, irq 28 mhd: get PHY ID = 0 8201 eth1: REALTEK RTL8201CP 10/1000 BaseT PHY at phy address 2 begin to init the network-mac0 and mac1 Mac0_MII_CONTROL_phy_addr: 00000002 Mac0_MII_CONTROL_val_before_write: 00003000 Mac0_MII_CONTROL_value_after_write: 00002000 Mac0_10/100 and Half/Full duplex val_before wrtie: 000001e1 Mac0_10/100 and Half/Full duplex val_after write: 000001e1 Mac0_Restart auto-negotiatio val before berfore write: 00002000 Mac0_Restart auto-negotiatio val before write: 00002100 Mac0_Restart auto-negotiation val_after write: 00002100 eth1: Using REALTEK RTL8201CP 10/1000 BaseT PHY as default INFTL: inftlcore.c $Revision: 1.18 $, inftlmount.c $Revision: 1.16 $ mhd MTD: probing 32-bit flash bus Db1550 Flash: Found 2 x16 devices at 0x0 in 32-bit bank Amd/Fujitsu Extended Query Table at 0x0040 Db1550 Flash: CFI does not contain boot bank location. Assuming top. number of CFI chips: 1 cfi_cmdset_0002: Disabling erase-suspend-program due to code brokenness. Creating 5 MTD partitions on "Db1550 Flash": 0x00000000-0x00600000 : "Kernel" 0x00600000-0x01600000 : "Ramdisk" 0x01600000-0x01b00000 : "User Fs" 0x01b00000-0x01c00000 : "Fs Bak" 0x01c00000-0x02000000 : "YAMON Bootloader" NAND device: Manufacturer ID: 0xec, Chip ID: 0xd3 (Samsung NAND 1GiB 3,3V 8-bit) Scanning device for bad blocks Bad eraseblock 0 at 0x00000000 Bad eraseblock 1 at 0x00020000 Bad eraseblock 2 at 0x00040000 Bad eraseblock 3 at 0x00060000 Bad eraseblock 4 at 0x00080000 Bad eraseblock 5 at 0x000a0000 Bad eraseblock 6 at 0x000c0000 Bad eraseblock 7 at 0x000e0000 ........ maowy maowy@avit.org.cn 2008-08-07 ******************************************* maowy(ëΰ) ϺϢι˾ Shanghai Accurate Video Info_Tech Co.,Ltd. ַ:Ϻɽ·331¥306 ADD:Room 306,No.1 Building,No.33 Leshan Rd.,Shanghai ʱ:200030 绰:021-51556408/09ת17ֻ :021-51556407 Mail:maowy@avit.org.cn ַ:http://www.avit.org.cn ******************************************** From kevink@paralogos.com Thu Aug 7 05:58:59 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 07 Aug 2008 05:59:07 +0100 (BST) Received: from fed1rmmtao105.cox.net ([68.230.241.41]:26035 "EHLO fed1rmmtao105.cox.net") by ftp.linux-mips.org with ESMTP id S20022506AbYHGE67 (ORCPT ); Thu, 7 Aug 2008 05:58:59 +0100 Received: from fed1rmimpo01.cox.net ([70.169.32.71]) by fed1rmmtao105.cox.net (InterMail vM.7.08.02.01 201-2186-121-102-20070209) with ESMTP id <20080807045852.OIFZ774.fed1rmmtao105.cox.net@fed1rmimpo01.cox.net>; Thu, 7 Aug 2008 00:58:52 -0400 Received: from [192.168.1.100] ([68.13.125.212]) by fed1rmimpo01.cox.net with bizsmtp id zGyq1Z00M4b4U6U03GyruM; Thu, 07 Aug 2008 00:58:51 -0400 Message-ID: <489A810B.8030301@paralogos.com> Date: Wed, 06 Aug 2008 23:58:51 -0500 From: "Kevin D. Kissell" User-Agent: Thunderbird 2.0.0.16 (Windows/20080708) MIME-Version: 1.0 To: Chung-Chi Lo CC: linux-mips@linux-mips.org Subject: Re: Config7.WII and IPI mechanism in SMTC linux References: <3f696b20807302341n39d53172q39adf8e10c6249bb@mail.gmail.com> In-Reply-To: <3f696b20807302341n39d53172q39adf8e10c6249bb@mail.gmail.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20141 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: kevink@paralogos.com Precedence: bulk X-list: linux-mips The original SMTC code was written for MIPS kernels which guaranteed that interrupts were never disabled when the WAIT instruction is executed. It was later noted that going into WAIT with interrupts disabled is desirable in most MIPS implementations, and a patch was propagated which did this, but also broke SMTC. There is a way to make SMTC work in spite of this, and I had thought that it had been implemented, at least internally to MIPS, but it may be that the necessary patch hasn't yet been written or published. The last time I checked, the WAIT-with-interrupts-off behavior was a configuration option. If that's true in the sources you're using, turn it off if you're building for SMTC. If you want further assistance, contact me by direct email. Regards, Kevin K. Chung-Chi Lo wrote: > Hello, > > My platform is MIPS 34K cpu core and Config7.WII=1. > > If Config7.WII=1 and a TC is idle, the TC will execute "wait" > instruction with TCSTATUS.IXMT=1 > to disable interrupt. > > But in 34K, interrupts are not TC-specific. So some TCs will not get > real interrupts to break "wait" > instruction. Even in SMTC's IPI mechanism, the IPI mechanism is to > program TCRestart if target > TC is in the same VPE. > > In function smtc_send_ipi, it detects if TC's interrupt is disabled, > then enqueue IPI message to > target TC's queue. So some TCs are always idle and cannot break "wait" > instruction. I don't know > if I miss something and please comment on this problem. Thanks. > > if ((tcstatus & TCSTATUS_IXMT) != 0) { > /* > * Spin-waiting here can deadlock, > * so we queue the message for the target TC. > */ > write_tc_c0_tchalt(0); > UNLOCK_CORE_PRA(); > ..... > smtc_ipi_nq(&IPIQ[cpu], pipi); > } > > -- > Lino, Chung-Chi Lo > > > From jgarzik@pobox.com Thu Aug 7 07:12:29 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 07 Aug 2008 07:12:35 +0100 (BST) Received: from srv5.dvmed.net ([207.36.208.214]:12483 "EHLO mail.dvmed.net") by ftp.linux-mips.org with ESMTP id S20022127AbYHGGM3 (ORCPT ); Thu, 7 Aug 2008 07:12:29 +0100 Received: from cpe-069-134-153-115.nc.res.rr.com ([69.134.153.115] helo=core.yyz.us) by mail.dvmed.net with esmtpsa (Exim 4.69 #1 (Red Hat Linux)) id 1KQyjW-0002Zq-6c; Thu, 07 Aug 2008 06:12:24 +0000 Message-ID: <489A9245.4070105@pobox.com> Date: Thu, 07 Aug 2008 02:12:21 -0400 From: Jeff Garzik User-Agent: Thunderbird 2.0.0.14 (X11/20080501) MIME-Version: 1.0 To: Thomas Bogendoerfer CC: netdev@vger.kernel.org, linux-mips@linux-mips.org, ralf@linux-mips.org Subject: Re: [PATCH] METH: fix MAC address setup References: <20080730231424.CD5E8DEBB8@solo.franken.de> In-Reply-To: <20080730231424.CD5E8DEBB8@solo.franken.de> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20142 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jgarzik@pobox.com Precedence: bulk X-list: linux-mips Thomas Bogendoerfer wrote: > Setup of the mac filter lost the upper 16bit of the mac address. This > bug got unconvered by a patch, which fixed the promiscous handling. > > Signed-off-by: Thomas Bogendoerfer > --- > > drivers/net/meth.c | 2 +- > 1 files changed, 1 insertions(+), 1 deletions(-) > > diff --git a/drivers/net/meth.c b/drivers/net/meth.c > index 4cb364e..0a97c26 100644 > --- a/drivers/net/meth.c > +++ b/drivers/net/meth.c > @@ -100,7 +100,7 @@ static inline void load_eaddr(struct net_device *dev) > DPRINTK("Loading MAC Address: %s\n", print_mac(mac, dev->dev_addr)); > macaddr = 0; > for (i = 0; i < 6; i++) > - macaddr |= dev->dev_addr[i] << ((5 - i) * 8); > + macaddr |= (u64)dev->dev_addr[i] << ((5 - i) * 8); applied From mano@roarinelk.homelinux.net Thu Aug 7 07:45:51 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 07 Aug 2008 07:45:58 +0100 (BST) Received: from fnoeppeil48.netpark.at ([217.175.205.176]:64678 "EHLO roarinelk.homelinux.net") by ftp.linux-mips.org with ESMTP id S20027443AbYHGGpv (ORCPT ); Thu, 7 Aug 2008 07:45:51 +0100 Received: (qmail 12184 invoked from network); 7 Aug 2008 08:45:47 +0200 Received: from unknown (HELO scarran) (192.168.0.242) by fnoeppeil48.netpark.at with SMTP; 7 Aug 2008 08:45:47 +0200 Date: Thu, 7 Aug 2008 08:45:47 +0200 From: Manuel Lauss To: "maowy" Cc: borasah@netone.com.tr , L-M-O , linux-mips@linux-mips.org Subject: Re: Au1550 Nandflash Message-ID: <20080807084547.243d803a@scarran> In-Reply-To: References: Organization: Private X-Mailer: Claws Mail 3.5.0 (GTK+ 2.12.11; i686-pc-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20143 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mano@roarinelk.homelinux.net Precedence: bulk X-list: linux-mips On Thu, 7 Aug 2008 12:16:19 +0800 "maowy" wrote: > borasah____________ > I have the same problem with you when using nandflash. > Our kernel can recognize nandflash but it seems to be all bad block. > How dou you successfully solve this problem of nandflash . > Can you tell how to solve this problem. > Hope to receive your letter as soon as possible.Thanks. > > > our platform:AU1550 > OS:linux-2.6.13 Please give the "gen_nand" driver a try. I ran into identical problems on Au1200; the in-kernel au1550nd.c code seems to be explicitly tailored for small-page nands on the PB1550/DB1200 boards and doesn't seem to work anywhere else. FWIW, here's a snippet I use on Au1200 which you can paste into your board setup code; it should work on Au1550 too since the NAND parts are identical. ---------- 8< --------------------- 8< ----------------- #include #include #include #include #include static void au1200_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl) { struct nand_chip *this = mtd->priv; unsigned long ioaddr = (unsigned long)this->IO_ADDR_W; ioaddr &= 0xffffff00; if (ctrl & NAND_CLE) { ioaddr += MEM_STNAND_CMD; } else if (ctrl & NAND_ALE) { ioaddr += MEM_STNAND_ADDR; } else { /* assume we want to r/w real data by default */ ioaddr += MEM_STNAND_DATA; } this->IO_ADDR_R = this->IO_ADDR_W = (void __iomem *)ioaddr; if (cmd != NAND_CMD_NONE) { au_writeb(cmd, ioaddr); au_sync(); } } static int au1200_nand_device_ready(struct mtd_info *mtd) { int ret = (au_readl(MEM_STSTAT) & 1); au_sync(); return ret; } static const char *au1200_part_probes[] = { "cmdlinepart", NULL }; static struct mtd_partition au1200_nand_parts[] = { [0] = { .name = "NAND FS 0", .offset = 0, .size = MTDPART_SIZ_FULL, }, }; struct platform_nand_data au1200_nand_platdata = { .chip = { .nr_chips = 1, .chip_offset = 0, .nr_partitions = ARRAY_SIZE(au1200_nand_parts), .partitions = au1200_nand_parts, .chip_delay = 20, .part_probe_types = au1200_part_probes, }, .ctrl = { .hwcontrol = 0, .dev_ready = au1200_nand_device_ready, .select_chip = 0, .cmd_ctrl = au1200_nand_cmd_ctrl, }, }; static struct resource au1200_nand_res[] = { [0] = { .start = 0x20000000, .end = 0x200000ff, .flags = IORESOURCE_MEM, }, }; static struct platform_device au1200_nand_dev = { .name = "gen_nand", .num_resources = ARRAY_SIZE(au1200_nand_res), .resource = au1200_nand_res, .id = -1, .dev = { .platform_data = &au1200_nand_platdata, } }; ---------- 8< --------------------- 8< ----------------- Best regards, Manuel Lauss From alessandro.zummo@towertech.it Thu Aug 7 09:52:53 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 07 Aug 2008 09:53:03 +0100 (BST) Received: from mx0.towertech.it ([213.215.222.73]:5785 "HELO mx0.towertech.it") by ftp.linux-mips.org with SMTP id S20033281AbYHGIwx (ORCPT ); Thu, 7 Aug 2008 09:52:53 +0100 Received: (qmail 8034 invoked from network); 7 Aug 2008 10:52:50 +0200 Received: from unknown (HELO i1501.lan.towertech.it) (81.208.60.204) by mx0.towertech.it with SMTP; 7 Aug 2008 10:52:50 +0200 Date: Thu, 7 Aug 2008 10:52:49 +0200 From: Alessandro Zummo To: Thomas Bogendoerfer Cc: rtc-linux@googlegroups.com, linux-mips@linux-mips.org, ralf@linux-mips.org Subject: Re: [PATCH] DS1286: new RTC driver Message-ID: <20080807105249.50d6e777@i1501.lan.towertech.it> In-Reply-To: <20080803174137.AF8071DA6F4@solo.franken.de> References: <20080803174137.AF8071DA6F4@solo.franken.de> Organization: Tower Technologies X-Mailer: Sylpheed X-This-Is-A-Real-Message: Yes Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20144 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: alessandro.zummo@towertech.it Precedence: bulk X-list: linux-mips On Sun, 3 Aug 2008 19:41:37 +0200 (CEST) Thomas Bogendoerfer wrote: A few comments below... > This driver replaces the broken DS1286 driver in drivers/char and > gives back RTC support for SGI IP22 and IP28 machines. > > Signed-off-by: Thomas Bogendoerfer > --- > > drivers/rtc/Kconfig | 6 + > drivers/rtc/Makefile | 1 + > drivers/rtc/rtc-ds1286.c | 425 ++++++++++++++++++++++++++++++++++++++++++++++ > 3 files changed, 432 insertions(+), 0 deletions(-) > > diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig > index 90ab738..934f630 100644 > --- a/drivers/rtc/Kconfig > +++ b/drivers/rtc/Kconfig > @@ -352,6 +352,12 @@ config RTC_DRV_DS1216 > help > If you say yes here you get support for the Dallas DS1216 RTC chips. > > +config RTC_DRV_DS1286 > + tristate "Dallas DS1286" > + depends on SGI_HAS_DS1286 > + help > + If you say yes here you get support for the Dallas DS1286 RTC chips. > + > config RTC_DRV_DS1302 > tristate "Dallas DS1302" > depends on SH_SECUREEDGE5410 > diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile > index 18622ef..e060802 100644 > --- a/drivers/rtc/Makefile > +++ b/drivers/rtc/Makefile > @@ -23,6 +23,7 @@ obj-$(CONFIG_RTC_DRV_AT91SAM9) += rtc-at91sam9.o > obj-$(CONFIG_RTC_DRV_BFIN) += rtc-bfin.o > obj-$(CONFIG_RTC_DRV_CMOS) += rtc-cmos.o > obj-$(CONFIG_RTC_DRV_DS1216) += rtc-ds1216.o > +obj-$(CONFIG_RTC_DRV_DS1286) += rtc-ds1286.o > obj-$(CONFIG_RTC_DRV_DS1302) += rtc-ds1302.o > obj-$(CONFIG_RTC_DRV_DS1305) += rtc-ds1305.o > obj-$(CONFIG_RTC_DRV_DS1307) += rtc-ds1307.o > diff --git a/drivers/rtc/rtc-ds1286.c b/drivers/rtc/rtc-ds1286.c > new file mode 100644 > index 0000000..2f6def0 > --- /dev/null > +++ b/drivers/rtc/rtc-ds1286.c > @@ -0,0 +1,425 @@ > +/* > + * DS1286 Real Time Clock interface for Linux > + * > + * Copyright (C) 1998, 1999, 2000 Ralf Baechle > + * Copyright (C) 2008 Thomas Bogendoerfer > + * > + * Based on code written by Paul Gortmaker. > + * > + * This program is free software; you can redistribute it and/or modify it > + * under the terms of the GNU General Public License as published by the > + * Free Software Foundation; either version 2 of the License, or (at your > + * option) any later version. > + */ > + > +#include > +#include > +#include > +#include > +#include > + > +#define DRV_VERSION "1.0" > + > +struct ds1286_priv { > + struct rtc_device *rtc; > + u32 __iomem *rtcregs; > + size_t size; > + unsigned long baseaddr; > + spinlock_t lock; > +}; > + > +static unsigned char days_in_mo[] = { > + 0, 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 > +}; > + > +static inline u8 ds1286_rtc_read(struct ds1286_priv *priv, int reg) > +{ > + return __raw_readl(&priv->rtcregs[reg]) & 0xff; > +} > + > +static inline void ds1286_rtc_write(struct ds1286_priv *priv, u8 data, int reg) > +{ > + __raw_writel(data, &priv->rtcregs[reg]); > +} > + > +#ifdef CONFIG_RTC_INTF_DEV > + > +static int ds1286_ioctl(struct device *dev, unsigned int cmd, unsigned long arg) > +{ > + struct ds1286_priv *priv = dev_get_drvdata(dev); > + unsigned long flags; > + unsigned char val; > + > + switch (cmd) { > + case RTC_AIE_OFF: > + /* Mask alarm int. enab. bit */ > + spin_lock_irqsave(&priv->lock, flags); > + val = ds1286_rtc_read(priv, RTC_CMD); > + val |= RTC_TDM; > + ds1286_rtc_write(priv, val, RTC_CMD); > + spin_unlock_irqrestore(&priv->lock, flags); > + break; > + case RTC_AIE_ON: > + /* Allow alarm interrupts. */ > + spin_lock_irqsave(&priv->lock, flags); > + val = ds1286_rtc_read(priv, RTC_CMD); > + val &= ~RTC_TDM; > + ds1286_rtc_write(priv, val, RTC_CMD); > + spin_unlock_irqrestore(&priv->lock, flags); > + break; > + case RTC_WIE_OFF: > + /* Mask watchdog int. enab. bit */ > + spin_lock_irqsave(&priv->lock, flags); > + val = ds1286_rtc_read(priv, RTC_CMD); > + val |= RTC_WAM; > + ds1286_rtc_write(priv, val, RTC_CMD); > + spin_unlock_irqrestore(&priv->lock, flags); > + break; > + case RTC_WIE_ON: > + /* Allow watchdog interrupts. */ > + spin_lock_irqsave(&priv->lock, flags); > + val = ds1286_rtc_read(priv, RTC_CMD); > + val &= ~RTC_WAM; > + ds1286_rtc_write(priv, val, RTC_CMD); > + spin_unlock_irqrestore(&priv->lock, flags); > + break; > + default: > + return -ENOIOCTLCMD; > + } > + return 0; > +} > + > +#else > +#define ds1286_ioctl NULL > +#endif > + > +#ifdef CONFIG_PROC_FS > + > +static int ds1286_proc(struct device *dev, struct seq_file *seq) > +{ > + struct ds1286_priv *priv = dev_get_drvdata(dev); > + unsigned char month, cmd, amode; > + const char *s; > + > + month = ds1286_rtc_read(priv, RTC_MONTH); > + seq_printf(seq, > + "oscillator\t: %s\n" > + "square_wave\t: %s\n", > + (month & RTC_EOSC) ? "disabled" : "enabled", > + (month & RTC_ESQW) ? "disabled" : "enabled"); > + > + amode = ((ds1286_rtc_read(priv, RTC_MINUTES_ALARM) & 0x80) >> 5) | > + ((ds1286_rtc_read(priv, RTC_HOURS_ALARM) & 0x80) >> 6) | > + ((ds1286_rtc_read(priv, RTC_DAY_ALARM) & 0x80) >> 7); > + switch (amode) { > + case 7: > + s = "each minute"; > + break; > + case 3: > + s = "minutes match"; > + break; > + case 1: > + s = "hours and minutes match"; > + break; > + case 0: > + s = "days, hours and minutes match"; > + break; > + default: > + s = "invalid"; > + break; > + } > + seq_printf(seq, "alarm_mode\t: %s\n", s); > + > + cmd = ds1286_rtc_read(priv, RTC_CMD); > + seq_printf(seq, > + "alarm_enable\t: %s\n" > + "wdog_alarm\t: %s\n" > + "alarm_mask\t: %s\n" > + "wdog_alarm_mask\t: %s\n" > + "interrupt_mode\t: %s\n" > + "INTB_mode\t: %s_active\n" > + "interrupt_pins\t: %s\n", > + (cmd & RTC_TDF) ? "yes" : "no", > + (cmd & RTC_WAF) ? "yes" : "no", > + (cmd & RTC_TDM) ? "disabled" : "enabled", > + (cmd & RTC_WAM) ? "disabled" : "enabled", > + (cmd & RTC_PU_LVL) ? "pulse" : "level", > + (cmd & RTC_IBH_LO) ? "low" : "high", > + (cmd & RTC_IPSW) ? "unswapped" : "swapped"); > + return 0; > +} > + > +#else > +#define ds1286_proc NULL > +#endif > + > +static int ds1286_read_time(struct device *dev, struct rtc_time *tm) > +{ > + struct ds1286_priv *priv = dev_get_drvdata(dev); > + unsigned char save_control; > + unsigned long flags; > + unsigned long uip_watchdog = jiffies; > + > + /* > + * read RTC once any update in progress is done. The update > + * can take just over 2ms. We wait 10 to 20ms. There is no need to > + * to poll-wait (up to 1s - eeccch) for the falling edge of RTC_UIP. > + * If you need to know *exactly* when a second has started, enable > + * periodic update complete interrupts, (via ioctl) and then > + * immediately read /dev/rtc which will block until you get the IRQ. > + * Once the read clears, read the RTC time (again via ioctl). Easy. > + */ > + > + if (ds1286_rtc_read(priv, RTC_CMD) & RTC_TE) > + while (time_before(jiffies, uip_watchdog + 2*HZ/100)) > + barrier(); > + > + /* > + * Only the values that we read from the RTC are set. We leave > + * tm_wday, tm_yday and tm_isdst untouched. Even though the > + * RTC has RTC_DAY_OF_WEEK, we ignore it, as it is only updated > + * by the RTC when initially set to a non-zero value. > + */ > + spin_lock_irqsave(&priv->lock, flags); > + save_control = ds1286_rtc_read(priv, RTC_CMD); > + ds1286_rtc_write(priv, (save_control|RTC_TE), RTC_CMD); > + > + tm->tm_sec = ds1286_rtc_read(priv, RTC_SECONDS); > + tm->tm_min = ds1286_rtc_read(priv, RTC_MINUTES); > + tm->tm_hour = ds1286_rtc_read(priv, RTC_HOURS) & 0x3f; > + tm->tm_mday = ds1286_rtc_read(priv, RTC_DATE); > + tm->tm_mon = ds1286_rtc_read(priv, RTC_MONTH) & 0x1f; > + tm->tm_year = ds1286_rtc_read(priv, RTC_YEAR); > + > + ds1286_rtc_write(priv, save_control, RTC_CMD); > + spin_unlock_irqrestore(&priv->lock, flags); > + > + BCD_TO_BIN(tm->tm_sec); > + BCD_TO_BIN(tm->tm_min); > + BCD_TO_BIN(tm->tm_hour); > + BCD_TO_BIN(tm->tm_mday); > + BCD_TO_BIN(tm->tm_mon); > + BCD_TO_BIN(tm->tm_year); > + > + /* > + * Account for differences between how the RTC uses the values > + * and how they are defined in a struct rtc_time; > + */ > + if (tm->tm_year < 45) > + tm->tm_year += 30; > + tm->tm_year += 40; > + if (tm->tm_year < 70) > + tm->tm_year += 100; > + > + tm->tm_mon--; > + > + return rtc_valid_tm(tm); > +} > + > +static int ds1286_set_time(struct device *dev, struct rtc_time *tm) > +{ > + struct ds1286_priv *priv = dev_get_drvdata(dev); > + unsigned char mon, day, hrs, min, sec, leap_yr; > + unsigned char save_control; > + unsigned int yrs; > + unsigned long flags; > + > + > + yrs = tm->tm_year + 1900; > + mon = tm->tm_mon + 1; /* tm_mon starts at zero */ > + day = tm->tm_mday; > + hrs = tm->tm_hour; > + min = tm->tm_min; > + sec = tm->tm_sec; > + > + if (yrs < 1970) > + return -EINVAL; > + > + leap_yr = ((!(yrs % 4) && (yrs % 100)) || !(yrs % 400)); > + > + if ((mon > 12) || (day == 0)) > + return -EINVAL; > + > + if (day > (days_in_mo[mon] + ((mon == 2) && leap_yr))) > + return -EINVAL; > + > + if ((hrs >= 24) || (min >= 60) || (sec >= 60)) > + return -EINVAL; > + > + yrs -= 1940; > + if (yrs > 255) /* They are unsigned */ > + return -EINVAL; please check rtc-lib.c . there are functions that might help you to verify boundaries. > + if (yrs >= 100) > + yrs -= 100; > + > + BIN_TO_BCD(sec); > + BIN_TO_BCD(min); > + BIN_TO_BCD(hrs); > + BIN_TO_BCD(day); > + BIN_TO_BCD(mon); > + BIN_TO_BCD(yrs); > + > + spin_lock_irqsave(&priv->lock, flags); > + save_control = ds1286_rtc_read(priv, RTC_CMD); > + ds1286_rtc_write(priv, (save_control|RTC_TE), RTC_CMD); > + > + ds1286_rtc_write(priv, yrs, RTC_YEAR); > + ds1286_rtc_write(priv, mon, RTC_MONTH); > + ds1286_rtc_write(priv, day, RTC_DATE); > + ds1286_rtc_write(priv, hrs, RTC_HOURS); > + ds1286_rtc_write(priv, min, RTC_MINUTES); > + ds1286_rtc_write(priv, sec, RTC_SECONDS); > + ds1286_rtc_write(priv, 0, RTC_HUNDREDTH_SECOND); > + > + ds1286_rtc_write(priv, save_control, RTC_CMD); > + spin_unlock_irqrestore(&priv->lock, flags); > + return 0; > +} > + > +static int ds1286_read_alarm(struct device *dev, struct rtc_wkalrm *alm) > +{ > + struct ds1286_priv *priv = dev_get_drvdata(dev); > + unsigned char cmd; > + unsigned long flags; > + > + /* > + * Only the values that we read from the RTC are set. That > + * means only tm_wday, tm_hour, tm_min. > + */ > + spin_lock_irqsave(&priv->lock, flags); > + alm->time.tm_min = ds1286_rtc_read(priv, RTC_MINUTES_ALARM) & 0x7f; > + alm->time.tm_hour = ds1286_rtc_read(priv, RTC_HOURS_ALARM) & 0x1f; > + alm->time.tm_wday = ds1286_rtc_read(priv, RTC_DAY_ALARM) & 0x07; > + cmd = ds1286_rtc_read(priv, RTC_CMD); > + spin_unlock_irqrestore(&priv->lock, flags); > + > + BCD_TO_BIN(alm->time.tm_min); > + BCD_TO_BIN(alm->time.tm_hour); > + alm->time.tm_sec = 0; > + return 0; > +} > + > +static int ds1286_set_alarm(struct device *dev, struct rtc_wkalrm *alm) > +{ > + struct ds1286_priv *priv = dev_get_drvdata(dev); > + unsigned char hrs, min, sec; > + > + hrs = alm->time.tm_hour; > + min = alm->time.tm_min; > + sec = alm->time.tm_sec; > + > + if (hrs >= 24) > + hrs = 0xff; > + > + if (min >= 60) > + min = 0xff; > + > + if (sec != 0) > + return -EINVAL; > + > + min = BIN2BCD(min); > + hrs = BIN2BCD(hrs); > + > + spin_lock(&priv->lock); > + ds1286_rtc_write(priv, hrs, RTC_HOURS_ALARM); > + ds1286_rtc_write(priv, min, RTC_MINUTES_ALARM); > + spin_unlock(&priv->lock); > + > + return 0; > +} > + > +static const struct rtc_class_ops ds1286_ops = { > + .ioctl = ds1286_ioctl, > + .proc = ds1286_proc, > + .read_time = ds1286_read_time, > + .set_time = ds1286_set_time, > + .read_alarm = ds1286_read_alarm, > + .set_alarm = ds1286_set_alarm, > +}; > + > +static int __devinit ds1286_probe(struct platform_device *pdev) > +{ > + struct rtc_device *rtc; > + struct resource *res; > + struct ds1286_priv *priv; > + int ret = 0; > + > + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); > + if (!res) > + return -ENODEV; > + priv = kzalloc(sizeof *priv, GFP_KERNEL); sizeof(struct ds1286_priv) is a little bit cleaner. > + if (!priv) > + return -ENOMEM; > + > + priv->size = res->end - res->start + 1; > + if (!request_mem_region(res->start, priv->size, pdev->name)) { > + ret = -EBUSY; > + goto out; > + } > + priv->baseaddr = res->start; > + priv->rtcregs = ioremap(priv->baseaddr, priv->size); > + if (!priv->rtcregs) { > + ret = -ENOMEM; > + goto out; > + } > + spin_lock_init(&priv->lock); > + rtc = rtc_device_register("ds1286", &pdev->dev, > + &ds1286_ops, THIS_MODULE); > + if (IS_ERR(rtc)) { > + ret = PTR_ERR(rtc); > + goto out; > + } > + priv->rtc = rtc; > + platform_set_drvdata(pdev, priv); > + return 0; > + > +out: > + if (priv->rtc) > + rtc_device_unregister(priv->rtc); > + if (priv->rtcregs) > + iounmap(priv->rtcregs); > + if (priv->baseaddr) > + release_mem_region(priv->baseaddr, priv->size); > + kfree(priv); > + return ret; > +} > + > +static int __devexit ds1286_remove(struct platform_device *pdev) > +{ > + struct ds1286_priv *priv = platform_get_drvdata(pdev); > + > + rtc_device_unregister(priv->rtc); > + iounmap(priv->rtcregs); > + release_mem_region(priv->baseaddr, priv->size); > + kfree(priv); > + return 0; > +} > + > +static struct platform_driver ds1286_platform_driver = { > + .driver = { > + .name = "rtc-ds1286", > + .owner = THIS_MODULE, > + }, > + .probe = ds1286_probe, > + .remove = __devexit_p(ds1286_remove), > +}; > + > +static int __init ds1286_init(void) > +{ > + return platform_driver_register(&ds1286_platform_driver); > +} > + > +static void __exit ds1286_exit(void) > +{ > + platform_driver_unregister(&ds1286_platform_driver); > +} > + > +MODULE_AUTHOR("Thomas Bogendoerfer "); > +MODULE_DESCRIPTION("DS1286 RTC driver"); > +MODULE_LICENSE("GPL"); > +MODULE_VERSION(DRV_VERSION); > +MODULE_ALIAS("platform:rtc-ds1286"); > + > +module_init(ds1286_init); > +module_exit(ds1286_exit); -- Best regards, Alessandro Zummo, Tower Technologies - Torino, Italy http://www.towertech.it From alessandro.zummo@towertech.it Thu Aug 7 09:55:57 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 07 Aug 2008 09:56:04 +0100 (BST) Received: from mx0.towertech.it ([213.215.222.73]:15247 "HELO mx0.towertech.it") by ftp.linux-mips.org with SMTP id S20022912AbYHGIz5 (ORCPT ); Thu, 7 Aug 2008 09:55:57 +0100 Received: (qmail 8148 invoked from network); 7 Aug 2008 10:55:55 +0200 Received: from unknown (HELO i1501.lan.towertech.it) (81.208.60.204) by mx0.towertech.it with SMTP; 7 Aug 2008 10:55:55 +0200 Date: Thu, 7 Aug 2008 10:55:55 +0200 From: Alessandro Zummo To: Thomas Bogendoerfer Cc: rtc-linux@googlegroups.com, linux-mips@linux-mips.org, ralf@linux-mips.org Subject: Re: [PATCH v2] M48T35: new RTC driver Message-ID: <20080807105555.56d38c76@i1501.lan.towertech.it> In-Reply-To: <20080804170025.CBA97C2EAC@solo.franken.de> References: <20080804170025.CBA97C2EAC@solo.franken.de> Organization: Tower Technologies X-Mailer: Sylpheed X-This-Is-A-Real-Message: Yes Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20145 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: alessandro.zummo@towertech.it Precedence: bulk X-list: linux-mips On Mon, 4 Aug 2008 19:00:25 +0200 (CEST) Thomas Bogendoerfer wrote: seems ok, please fix that one liner and you can send it to andrew with my Acked-by: Alessandro Zummo thanks! > This driver replaces the broken ip27-rtc driver in drivers/char and > gives back RTC support for SGI IP27 machines. > > Signed-off-by: Thomas Bogendoerfer > --- > > Changes in v2: > > - don't depend on SGI_IP27 > - use rtc_valid_tm() for tm validation > - resource is now a physical address and is ioremapped now > - added kludge to workaround current ioc3 resource conflict > > drivers/rtc/Kconfig | 9 ++ > drivers/rtc/Makefile | 1 + > drivers/rtc/rtc-m48t35.c | 237 ++++++++++++++++++++++++++++++++++++++++++++++ > 3 files changed, 247 insertions(+), 0 deletions(-) > > diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig > index 90ab738..2e5a578 100644 > --- a/drivers/rtc/Kconfig > +++ b/drivers/rtc/Kconfig > @@ -405,6 +405,15 @@ config RTC_DRV_M48T86 > This driver can also be built as a module. If so, the module > will be called rtc-m48t86. > > +config RTC_DRV_M48T35 > + tristate "ST M48T35" > + help > + If you say Y here you will get support for the > + ST M48T35 RTC chip. > + > + This driver can also be built as a module, if so, the module > + will be called "rtc-m48t35". > + > config RTC_DRV_M48T59 > tristate "ST M48T59" > help > diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile > index 18622ef..7d10cc0 100644 > --- a/drivers/rtc/Makefile > +++ b/drivers/rtc/Makefile > @@ -36,6 +36,7 @@ obj-$(CONFIG_RTC_DRV_FM3130) += rtc-fm3130.o > obj-$(CONFIG_RTC_DRV_ISL1208) += rtc-isl1208.o > obj-$(CONFIG_RTC_DRV_M41T80) += rtc-m41t80.o > obj-$(CONFIG_RTC_DRV_M41T94) += rtc-m41t94.o > +obj-$(CONFIG_RTC_DRV_M48T35) += rtc-m48t35.o > obj-$(CONFIG_RTC_DRV_M48T59) += rtc-m48t59.o > obj-$(CONFIG_RTC_DRV_M48T86) += rtc-m48t86.o > obj-$(CONFIG_RTC_DRV_MAX6900) += rtc-max6900.o > diff --git a/drivers/rtc/rtc-m48t35.c b/drivers/rtc/rtc-m48t35.c > new file mode 100644 > index 0000000..e618b9a > --- /dev/null > +++ b/drivers/rtc/rtc-m48t35.c > @@ -0,0 +1,237 @@ > +/* > + * Driver for the SGS-Thomson M48T35 Timekeeper RAM chip > + * > + * Copyright (C) 2000 Silicon Graphics, Inc. > + * Written by Ulf Carlsson (ulfc@engr.sgi.com) > + * > + * Copyright (C) 2008 Thomas Bogendoerfer > + * > + * Based on code written by Paul Gortmaker. > + * > + * This program is free software; you can redistribute it and/or modify it > + * under the terms of the GNU General Public License as published by the > + * Free Software Foundation; either version 2 of the License, or (at your > + * option) any later version. > + */ > + > +#include > +#include > +#include > +#include > + > +#define DRV_VERSION "1.0" > + > +struct m48t35_rtc { > + u8 pad[0x7ff8]; /* starts at 0x7ff8 */ > + u8 control; > + u8 sec; > + u8 min; > + u8 hour; > + u8 day; > + u8 date; > + u8 month; > + u8 year; > +}; > + > +#define M48T35_RTC_SET 0x80 > +#define M48T35_RTC_READ 0x40 > + > +struct m48t35_priv { > + struct rtc_device *rtc; > + struct m48t35_rtc __iomem *reg; > + size_t size; > + unsigned long baseaddr; > + spinlock_t lock; > +}; > + > +static int m48t35_read_time(struct device *dev, struct rtc_time *tm) > +{ > + struct m48t35_priv *priv = dev_get_drvdata(dev); > + u8 control; > + > + /* > + * Only the values that we read from the RTC are set. We leave > + * tm_wday, tm_yday and tm_isdst untouched. Even though the > + * RTC has RTC_DAY_OF_WEEK, we ignore it, as it is only updated > + * by the RTC when initially set to a non-zero value. > + */ > + spin_lock_irq(&priv->lock); > + control = readb(&priv->reg->control); > + writeb(control | M48T35_RTC_READ, &priv->reg->control); > + tm->tm_sec = readb(&priv->reg->sec); > + tm->tm_min = readb(&priv->reg->min); > + tm->tm_hour = readb(&priv->reg->hour); > + tm->tm_mday = readb(&priv->reg->date); > + tm->tm_mon = readb(&priv->reg->month); > + tm->tm_year = readb(&priv->reg->year); > + writeb(control, &priv->reg->control); > + spin_unlock_irq(&priv->lock); > + > + tm->tm_sec = BCD2BIN(tm->tm_sec); > + tm->tm_min = BCD2BIN(tm->tm_min); > + tm->tm_hour = BCD2BIN(tm->tm_hour); > + tm->tm_mday = BCD2BIN(tm->tm_mday); > + tm->tm_mon = BCD2BIN(tm->tm_mon); > + tm->tm_year = BCD2BIN(tm->tm_year); > + > + /* > + * Account for differences between how the RTC uses the values > + * and how they are defined in a struct rtc_time; > + */ > + tm->tm_year += 70; > + if (tm->tm_year <= 69) > + tm->tm_year += 100; > + > + tm->tm_mon--; > + return rtc_valid_tm(tm); > +} > + > +static int m48t35_set_time(struct device *dev, struct rtc_time *tm) > +{ > + struct m48t35_priv *priv = dev_get_drvdata(dev); > + unsigned char mon, day, hrs, min, sec; > + unsigned int yrs; > + u8 control; > + > + yrs = tm->tm_year + 1900; > + mon = tm->tm_mon + 1; /* tm_mon starts at zero */ > + day = tm->tm_mday; > + hrs = tm->tm_hour; > + min = tm->tm_min; > + sec = tm->tm_sec; > + > + if (!rtc_valid_tm(tm)) > + return -EINVAL; > + > + if (yrs < 1970) > + return -EINVAL; > + > + yrs -= 1970; > + if (yrs > 255) /* They are unsigned */ > + return -EINVAL; > + > + if (yrs > 169) > + return -EINVAL; > + > + if (yrs >= 100) > + yrs -= 100; > + > + sec = BIN2BCD(sec); > + min = BIN2BCD(min); > + hrs = BIN2BCD(hrs); > + day = BIN2BCD(day); > + mon = BIN2BCD(mon); > + yrs = BIN2BCD(yrs); > + > + spin_lock_irq(&priv->lock); > + control = readb(&priv->reg->control); > + writeb(control | M48T35_RTC_SET, &priv->reg->control); > + writeb(yrs, &priv->reg->year); > + writeb(mon, &priv->reg->month); > + writeb(day, &priv->reg->date); > + writeb(hrs, &priv->reg->hour); > + writeb(min, &priv->reg->min); > + writeb(sec, &priv->reg->sec); > + writeb(control, &priv->reg->control); > + spin_unlock_irq(&priv->lock); > + return 0; > +} > + > +static const struct rtc_class_ops m48t35_ops = { > + .read_time = m48t35_read_time, > + .set_time = m48t35_set_time, > +}; > + > +static int __devinit m48t35_probe(struct platform_device *pdev) > +{ > + struct rtc_device *rtc; > + struct resource *res; > + struct m48t35_priv *priv; > + int ret = 0; > + > + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); > + if (!res) > + return -ENODEV; > + priv = kzalloc(sizeof *priv, GFP_KERNEL); same as the other patch :) > + if (!priv) > + return -ENOMEM; > + > + priv->size = res->end - res->start + 1; > + /* > + * kludge: remove the #ifndef after ioc3 resource > + * conflicts are resolved > + */ > +#ifndef CONFIG_SGI_IP27 > + if (!request_mem_region(res->start, priv->size, pdev->name)) { > + ret = -EBUSY; > + goto out; > + } > +#endif > + priv->baseaddr = res->start; > + priv->reg = ioremap(priv->baseaddr, priv->size); > + if (!priv->reg) { > + ret = -ENOMEM; > + goto out; > + } > + spin_lock_init(&priv->lock); > + rtc = rtc_device_register("m48t35", &pdev->dev, > + &m48t35_ops, THIS_MODULE); > + if (IS_ERR(rtc)) { > + ret = PTR_ERR(rtc); > + goto out; > + } > + priv->rtc = rtc; > + platform_set_drvdata(pdev, priv); > + return 0; > + > +out: > + if (priv->rtc) > + rtc_device_unregister(priv->rtc); > + if (priv->reg) > + iounmap(priv->reg); > + if (priv->baseaddr) > + release_mem_region(priv->baseaddr, priv->size); > + kfree(priv); > + return ret; > +} > + > +static int __devexit m48t35_remove(struct platform_device *pdev) > +{ > + struct m48t35_priv *priv = platform_get_drvdata(pdev); > + > + rtc_device_unregister(priv->rtc); > + iounmap(priv->reg); > +#ifndef CONFIG_SGI_IP27 > + release_mem_region(priv->baseaddr, priv->size); > +#endif > + kfree(priv); > + return 0; > +} > + > +static struct platform_driver m48t35_platform_driver = { > + .driver = { > + .name = "rtc-m48t35", > + .owner = THIS_MODULE, > + }, > + .probe = m48t35_probe, > + .remove = __devexit_p(m48t35_remove), > +}; > + > +static int __init m48t35_init(void) > +{ > + return platform_driver_register(&m48t35_platform_driver); > +} > + > +static void __exit m48t35_exit(void) > +{ > + platform_driver_unregister(&m48t35_platform_driver); > +} > + > +MODULE_AUTHOR("Thomas Bogendoerfer "); > +MODULE_DESCRIPTION("M48T35 RTC driver"); > +MODULE_LICENSE("GPL"); > +MODULE_VERSION(DRV_VERSION); > +MODULE_ALIAS("platform:rtc-m48t35"); > + > +module_init(m48t35_init); > +module_exit(m48t35_exit); -- Best regards, Alessandro Zummo, Tower Technologies - Torino, Italy http://www.towertech.it From geert@linux-m68k.org Thu Aug 7 10:03:10 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 07 Aug 2008 10:03:19 +0100 (BST) Received: from harold.telenet-ops.be ([195.130.133.65]:31940 "EHLO harold.telenet-ops.be") by ftp.linux-mips.org with ESMTP id S20023547AbYHGJDK (ORCPT ); Thu, 7 Aug 2008 10:03:10 +0100 Received: from localhost (localhost.localdomain [127.0.0.1]) by harold.telenet-ops.be (Postfix) with SMTP id 0512B30062; Thu, 7 Aug 2008 11:03:09 +0200 (CEST) Received: from anakin.of.borg (78-21-204-88.access.telenet.be [78.21.204.88]) by harold.telenet-ops.be (Postfix) with ESMTP id CC3463003B; Thu, 7 Aug 2008 11:03:08 +0200 (CEST) Received: from anakin.of.borg (localhost [127.0.0.1]) by anakin.of.borg (8.14.3/8.14.3/Debian-5) with ESMTP id m77938cG024062 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NOT); Thu, 7 Aug 2008 11:03:08 +0200 Received: from localhost (geert@localhost) by anakin.of.borg (8.14.3/8.14.3/Submit) with ESMTP id m77938F8024059; Thu, 7 Aug 2008 11:03:08 +0200 X-Authentication-Warning: anakin.of.borg: geert owned process doing -bs Date: Thu, 7 Aug 2008 11:03:07 +0200 (CEST) From: Geert Uytterhoeven To: Alessandro Zummo cc: Thomas Bogendoerfer , rtc-linux@googlegroups.com, linux-mips@linux-mips.org, ralf@linux-mips.org Subject: Re: [PATCH] DS1286: new RTC driver In-Reply-To: <20080807105249.50d6e777@i1501.lan.towertech.it> Message-ID: References: <20080803174137.AF8071DA6F4@solo.franken.de> <20080807105249.50d6e777@i1501.lan.towertech.it> MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20146 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: geert@linux-m68k.org Precedence: bulk X-list: linux-mips On Thu, 7 Aug 2008, Alessandro Zummo wrote: > On Sun, 3 Aug 2008 19:41:37 +0200 (CEST) > Thomas Bogendoerfer wrote: > > +static int __devinit ds1286_probe(struct platform_device *pdev) > > +{ > > + struct rtc_device *rtc; > > + struct resource *res; > > + struct ds1286_priv *priv; > > + int ret = 0; > > + > > + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); > > + if (!res) > > + return -ENODEV; > > + priv = kzalloc(sizeof *priv, GFP_KERNEL); > > sizeof(struct ds1286_priv) is a little bit cleaner. What if the type of priv changes? Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds From alessandro.zummo@towertech.it Thu Aug 7 10:12:41 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 07 Aug 2008 10:12:49 +0100 (BST) Received: from mx0.towertech.it ([213.215.222.73]:46744 "HELO mx0.towertech.it") by ftp.linux-mips.org with SMTP id S20024994AbYHGJMl (ORCPT ); Thu, 7 Aug 2008 10:12:41 +0100 Received: (qmail 8690 invoked from network); 7 Aug 2008 11:12:39 +0200 Received: from unknown (HELO i1501.lan.towertech.it) (81.208.60.204) by mx0.towertech.it with SMTP; 7 Aug 2008 11:12:39 +0200 Date: Thu, 7 Aug 2008 11:12:38 +0200 From: Alessandro Zummo To: Geert Uytterhoeven Cc: Thomas Bogendoerfer , rtc-linux@googlegroups.com, linux-mips@linux-mips.org, ralf@linux-mips.org Subject: Re: [PATCH] DS1286: new RTC driver Message-ID: <20080807111238.69e7e46e@i1501.lan.towertech.it> In-Reply-To: References: <20080803174137.AF8071DA6F4@solo.franken.de> <20080807105249.50d6e777@i1501.lan.towertech.it> Organization: Tower Technologies X-Mailer: Sylpheed X-This-Is-A-Real-Message: Yes Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20147 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: alessandro.zummo@towertech.it Precedence: bulk X-list: linux-mips On Thu, 7 Aug 2008 11:03:07 +0200 (CEST) Geert Uytterhoeven wrote: > > sizeof(struct ds1286_priv) is a little bit cleaner. > > What if the type of priv changes? It shouldn't in such a small context . however, it is not required, is just my personal preference about readability. parentheses around the sizeof are, ont he other side, required. -- Best regards, Alessandro Zummo, Tower Technologies - Torino, Italy http://www.towertech.it From ralf@linux-mips.org Thu Aug 7 10:13:06 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 07 Aug 2008 10:13:12 +0100 (BST) Received: from ditditdahdahdah-dahdahdahditdit.dl5rb.org.uk ([217.169.26.28]:5816 "EHLO ditditdahdahdah-dahdahdahditdit.dl5rb.org.uk") by ftp.linux-mips.org with ESMTP id S20023944AbYHGJMr (ORCPT ); Thu, 7 Aug 2008 10:12:47 +0100 Received: from denk.linux-mips.net (denk.linux-mips.net [127.0.0.1]) by ditditdahdahdah-dahdahdahditdit.dl5rb.org.uk (8.14.2/8.14.1) with ESMTP id m779CYvg010436; Thu, 7 Aug 2008 10:12:37 +0100 Received: (from ralf@localhost) by denk.linux-mips.net (8.14.2/8.14.2/Submit) id m779CXIw010434; Thu, 7 Aug 2008 10:12:33 +0100 Date: Thu, 7 Aug 2008 10:12:33 +0100 From: Ralf Baechle To: Geert Uytterhoeven Cc: Alessandro Zummo , Thomas Bogendoerfer , rtc-linux@googlegroups.com, linux-mips@linux-mips.org Subject: Re: [PATCH] DS1286: new RTC driver Message-ID: <20080807091233.GA10389@linux-mips.org> References: <20080803174137.AF8071DA6F4@solo.franken.de> <20080807105249.50d6e777@i1501.lan.towertech.it> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20148 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Thu, Aug 07, 2008 at 11:03:07AM +0200, Geert Uytterhoeven wrote: > > > + priv = kzalloc(sizeof *priv, GFP_KERNEL); > > > > sizeof(struct ds1286_priv) is a little bit cleaner. > > What if the type of priv changes? Then this code will more changes anyway ... Ralf From markus.gothe@27m.se Thu Aug 7 13:48:27 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 07 Aug 2008 13:48:35 +0100 (BST) Received: from mail.lysator.liu.se ([130.236.254.3]:151 "EHLO mail.lysator.liu.se") by ftp.linux-mips.org with ESMTP id S20025199AbYHGMs1 (ORCPT ); Thu, 7 Aug 2008 13:48:27 +0100 Received: from localhost (localhost.localdomain [127.0.0.1]) by mail.lysator.liu.se (Postfix) with ESMTP id ADF67201B2EC; Thu, 7 Aug 2008 14:48:23 +0200 (CEST) Received: from mail.lysator.liu.se ([127.0.0.1]) by localhost (lenin.lysator.liu.se [127.0.0.1]) (amavisd-new, port 10024) with LMTP id 25068-01; Thu, 7 Aug 2008 14:48:23 +0200 (CEST) Received: from [192.168.27.166] (152-186-96-87.cust.blixtvik.se [87.96.186.152]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mail.lysator.liu.se (Postfix) with ESMTP id 3481B201B2E4; Thu, 7 Aug 2008 14:48:23 +0200 (CEST) Message-ID: <489AEEF1.60403@27m.se> Date: Thu, 07 Aug 2008 14:47:45 +0200 From: Markus Gothe User-Agent: Thunderbird 2.0.0.16 (X11/20080724) MIME-Version: 1.0 To: TriKri Cc: linux-mips@linux-mips.org Subject: Re: Debugging MIPS cpu with a probe, how? References: <18830812.post@talk.nabble.com> In-Reply-To: <18830812.post@talk.nabble.com> X-Enigmail-Version: 0.95.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Virus-Scanned: by amavisd-new-20030616-p10 (Debian) at lysator.liu.se Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20149 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: markus.gothe@27m.se Precedence: bulk X-list: linux-mips -----BEGIN PGP SIGNED MESSAGE----- Hash: SHA256 See: http://www.linux-mips.org/wiki/JTAG for references... //Markus TriKri wrote: > Hello! > > I have an embedded system, a box, with a MIPS processor on it, > which I need to debug (stop and start the processor, tell what > instructions it has previously executed, etc.). I also have an > EJTAG probe, which I have connected between the computer's usb and > the box, and written software for it. The software can communicate > with the probe, which in its own turn can communicate with the box > through the tap (test access port), by giving the tap certain > instructions. It can also, through the tap, feed the MIPS processor > with instructions, and read/write data from processor registers. > > The question is now, how can debug the processor? How do I stop it, > do I have to send any certain instructions to it? How can I set a > breakpoint (which I understand is a quite crucial point)? Can I use > GDB with my software to help debug the processor and how do I do > that? > > Thank you in advance! /Kristofer Krus - -- _______________________________________ Mr Markus Gothe Software Engineer Phone: +46 (0)13 21 81 20 (ext. 1046) Fax: +46 (0)13 21 21 15 Mobile: +46 (0)70 348 44 35 Diskettgatan 11, SE-583 35 Linköping, Sweden www.27m.com -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.6 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org iD8DBQFImu7o6I0XmJx2NrwRCNBvAKCeiyR2G28PHsrHdfgijKwKFzu4MgCffxzZ Elrh0qJUHc3TbfeeOtvgOBk= =2Jjo -----END PGP SIGNATURE----- From js@sig21.net Thu Aug 7 14:35:09 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 07 Aug 2008 14:35:16 +0100 (BST) Received: from xen.sig21.net ([88.198.19.73]:9410 "EHLO bar.sig21.net") by ftp.linux-mips.org with ESMTP id S20021608AbYHGNfJ (ORCPT ); Thu, 7 Aug 2008 14:35:09 +0100 Received: from [88.198.146.81] (helo=void.local) by bar.sig21.net with esmtpsa (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.63) (envelope-from ) id 1KR5dq-00064p-Qk for linux-mips@linux-mips.org; Thu, 07 Aug 2008 15:35:05 +0200 Received: from js by void.local with local (Exim 4.69) (envelope-from ) id 1KR5dq-0004MK-21 for linux-mips@linux-mips.org; Thu, 07 Aug 2008 15:34:58 +0200 Date: Thu, 7 Aug 2008 15:34:58 +0200 From: Johannes Stezenbach To: linux-mips@linux-mips.org Subject: Re: Debugging MIPS cpu with a probe, how? Message-ID: <20080807133458.GA16456@linuxtv.org> References: <18830812.post@talk.nabble.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <18830812.post@talk.nabble.com> User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20150 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: js@linuxtv.org Precedence: bulk X-list: linux-mips On Tue, Aug 05, 2008, TriKri wrote: > > I have an embedded system, a box, with a MIPS processor on it, which I need > to debug (stop and start the processor, tell what instructions it has > previously executed, etc.). I also have an EJTAG probe, which I have > connected between the computer's usb and the box, and written software for > it. The software can communicate with the probe, which in its own turn can > communicate with the box through the tap (test access port), by giving the > tap certain instructions. It can also, through the tap, feed the MIPS > processor with instructions, and read/write data from processor registers. > > The question is now, how can debug the processor? How do I stop it, do I > have to send any certain instructions to it? How can I set a breakpoint > (which I understand is a quite crucial point)? Can I use GDB with my > software to help debug the processor and how do I do that? I looked for Open Source EJTAG software a while ago and found two projects which may be of interest to you: http://svn.berlios.de/svnroot/repos/openocd/branches/mips/ http://www.totalembedded.com/open_source/jtag/mips32_ejtag/ But I didn't try to use any of it so far. Johannes From ralf@linux-mips.org Thu Aug 7 14:43:32 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 07 Aug 2008 14:43:39 +0100 (BST) Received: from ditditdahdahdah-dahdahdahditdit.dl5rb.org.uk ([217.169.26.28]:18843 "EHLO ditditdahdahdah-dahdahdahditdit.dl5rb.org.uk") by ftp.linux-mips.org with ESMTP id S20022944AbYHGNnc (ORCPT ); Thu, 7 Aug 2008 14:43:32 +0100 Received: from denk.linux-mips.net (denk.linux-mips.net [127.0.0.1]) by ditditdahdahdah-dahdahdahditdit.dl5rb.org.uk (8.14.2/8.14.1) with ESMTP id m77DhO0u016257; Thu, 7 Aug 2008 14:43:26 +0100 Received: (from ralf@localhost) by denk.linux-mips.net (8.14.2/8.14.2/Submit) id m77DhNNB016255; Thu, 7 Aug 2008 14:43:23 +0100 Date: Thu, 7 Aug 2008 14:43:23 +0100 From: Ralf Baechle To: David Daney Cc: Chris Friesen , linux-mips@linux-mips.org, Thiemo Seufer Subject: Re: looking for help interpreting softlockup/stack trace Message-ID: <20080807134323.GA15703@linux-mips.org> References: <48989AFE.5000500@nortel.com> <20080805191618.GB8629@linux-mips.org> <4899F41C.5070401@avtrex.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <4899F41C.5070401@avtrex.com> User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20151 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Wed, Aug 06, 2008 at 11:57:32AM -0700, David Daney wrote: >>> In the trace below, is "epc" the program counter at the time of the >>> timer interrupt? How does "ra" fit into this, given that the >>> function whose address it contains isn't seen in the stack trace >>> until quite a ways down? >> >> $LBB378 is an internal symbol. The value of RA may not be very informative >> if it was overwritten by a random subroutine call. >> > > I have thought about eliminating these internal labels when the module's symbols are read. Would this make any sense? I think so. Maybe that could even be done when the module is linked. I don't think there are ever any relocations against these local symbols. Thiemo? Ralf From ths@networkno.de Thu Aug 7 15:19:23 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 07 Aug 2008 15:19:30 +0100 (BST) Received: from relay01.mx.bawue.net ([193.7.176.67]:48365 "EHLO relay01.mx.bawue.net") by ftp.linux-mips.org with ESMTP id S20024198AbYHGOTX (ORCPT ); Thu, 7 Aug 2008 15:19:23 +0100 Received: from lagash (p549ADE1B.dip.t-dialin.net [84.154.222.27]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (No client certificate requested) by relay01.mx.bawue.net (Postfix) with ESMTP id C6F5C48919; Thu, 7 Aug 2008 16:19:21 +0200 (CEST) Received: from ths by lagash with local (Exim 4.69) (envelope-from ) id 1KR6Km-0000Fa-JJ; Thu, 07 Aug 2008 16:19:20 +0200 Date: Thu, 7 Aug 2008 16:19:20 +0200 From: Thiemo Seufer To: Ralf Baechle Cc: David Daney , Chris Friesen , linux-mips@linux-mips.org Subject: Re: looking for help interpreting softlockup/stack trace Message-ID: <20080807141920.GA27494@networkno.de> References: <48989AFE.5000500@nortel.com> <20080805191618.GB8629@linux-mips.org> <4899F41C.5070401@avtrex.com> <20080807134323.GA15703@linux-mips.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20080807134323.GA15703@linux-mips.org> User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20152 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ths@networkno.de Precedence: bulk X-list: linux-mips Ralf Baechle wrote: > On Wed, Aug 06, 2008 at 11:57:32AM -0700, David Daney wrote: > > >>> In the trace below, is "epc" the program counter at the time of the > >>> timer interrupt? How does "ra" fit into this, given that the > >>> function whose address it contains isn't seen in the stack trace > >>> until quite a ways down? > >> > >> $LBB378 is an internal symbol. The value of RA may not be very informative > >> if it was overwritten by a random subroutine call. > >> > > > > I have thought about eliminating these internal labels when the module's symbols are read. Would this make any sense? > > I think so. Maybe that could even be done when the module is linked. I > don't think there are ever any relocations against these local symbols. > Thiemo? AFAIR all such symbols are branch labels or debug info labels, the module loader should never use them. (But I don't know if kgdb uses them.) Thiemo From tsbogend@alpha.franken.de Thu Aug 7 21:38:10 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 07 Aug 2008 21:38:16 +0100 (BST) Received: from elvis.franken.de ([193.175.24.41]:48792 "EHLO elvis.franken.de") by ftp.linux-mips.org with ESMTP id S28577857AbYHGUiK (ORCPT ); Thu, 7 Aug 2008 21:38:10 +0100 Received: from uucp (helo=solo.franken.de) by elvis.franken.de with local-bsmtp (Exim 3.36 #1) id 1KRCFN-0004nb-00; Thu, 07 Aug 2008 22:38:09 +0200 Received: by solo.franken.de (Postfix, from userid 1000) id C3E91C315C; Thu, 7 Aug 2008 22:38:06 +0200 (CEST) Date: Thu, 7 Aug 2008 22:38:06 +0200 To: Alessandro Zummo Cc: rtc-linux@googlegroups.com, linux-mips@linux-mips.org, ralf@linux-mips.org Subject: Re: [PATCH v2] M48T35: new RTC driver Message-ID: <20080807203806.GA13369@alpha.franken.de> References: <20080804170025.CBA97C2EAC@solo.franken.de> <20080807105555.56d38c76@i1501.lan.towertech.it> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20080807105555.56d38c76@i1501.lan.towertech.it> User-Agent: Mutt/1.5.13 (2006-08-11) From: tsbogend@alpha.franken.de (Thomas Bogendoerfer) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20153 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: tsbogend@alpha.franken.de Precedence: bulk X-list: linux-mips On Thu, Aug 07, 2008 at 10:55:55AM +0200, Alessandro Zummo wrote: > On Mon, 4 Aug 2008 19:00:25 +0200 (CEST) > Thomas Bogendoerfer wrote: > > seems ok, please fix that one liner and you can > send it to andrew with my > > Acked-by: Alessandro Zummo excellent, is it okay to pass this through the MIPS tree together with the MIPS specific part ? Thomas. -- Crap can work. Given enough thrust pigs will fly, but it's not necessary a good idea. [ RFC1925, 2.3 ] From alessandro.zummo@towertech.it Thu Aug 7 21:39:48 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 07 Aug 2008 21:39:55 +0100 (BST) Received: from mx0.towertech.it ([213.215.222.73]:56012 "HELO mx0.towertech.it") by ftp.linux-mips.org with SMTP id S28577911AbYHGUjs (ORCPT ); Thu, 7 Aug 2008 21:39:48 +0100 Received: (qmail 31287 invoked from network); 7 Aug 2008 22:39:46 +0200 Received: from unknown (HELO i1501.lan.towertech.it) (81.208.60.204) by mx0.towertech.it with SMTP; 7 Aug 2008 22:39:46 +0200 Date: Thu, 7 Aug 2008 22:39:45 +0200 From: Alessandro Zummo To: tsbogend@alpha.franken.de (Thomas Bogendoerfer) Cc: rtc-linux@googlegroups.com, linux-mips@linux-mips.org, ralf@linux-mips.org Subject: Re: [PATCH v2] M48T35: new RTC driver Message-ID: <20080807223945.0f7c94a7@i1501.lan.towertech.it> In-Reply-To: <20080807203806.GA13369@alpha.franken.de> References: <20080804170025.CBA97C2EAC@solo.franken.de> <20080807105555.56d38c76@i1501.lan.towertech.it> <20080807203806.GA13369@alpha.franken.de> Organization: Tower Technologies X-Mailer: Sylpheed X-This-Is-A-Real-Message: Yes Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20154 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: alessandro.zummo@towertech.it Precedence: bulk X-list: linux-mips On Thu, 7 Aug 2008 22:38:06 +0200 tsbogend@alpha.franken.de (Thomas Bogendoerfer) wrote: > On Thu, Aug 07, 2008 at 10:55:55AM +0200, Alessandro Zummo wrote: > > On Mon, 4 Aug 2008 19:00:25 +0200 (CEST) > > Thomas Bogendoerfer wrote: > > > > seems ok, please fix that one liner and you can > > send it to andrew with my > > > > Acked-by: Alessandro Zummo > > excellent, is it okay to pass this through the MIPS tree together > with the MIPS specific part ? sure! -- Best regards, Alessandro Zummo, Tower Technologies - Torino, Italy http://www.towertech.it From ddaney@avtrex.com Thu Aug 7 22:58:05 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Thu, 07 Aug 2008 22:58:12 +0100 (BST) Received: from smtp1.dnsmadeeasy.com ([205.234.170.134]:19937 "EHLO smtp1.dnsmadeeasy.com") by ftp.linux-mips.org with ESMTP id S28578195AbYHGV6F (ORCPT ); Thu, 7 Aug 2008 22:58:05 +0100 Received: from smtp1.dnsmadeeasy.com (localhost [127.0.0.1]) by smtp1.dnsmadeeasy.com (Postfix) with ESMTP id E6B9A320024; Thu, 7 Aug 2008 21:58:09 +0000 (UTC) X-Authenticated-Name: js.dnsmadeeasy X-Transit-System: In case of SPAM please contact abuse@dnsmadeeasy.com Received: from avtrex.com (unknown [67.116.42.147]) by smtp1.dnsmadeeasy.com (Postfix) with ESMTP; Thu, 7 Aug 2008 21:58:09 +0000 (UTC) Received: from dl2.hq2.avtrex.com ([192.168.7.26]) by avtrex.com with Microsoft SMTPSVC(6.0.3790.1830); Thu, 7 Aug 2008 14:57:53 -0700 Message-ID: <489B6FDF.9070900@avtrex.com> Date: Thu, 07 Aug 2008 14:57:51 -0700 From: David Daney User-Agent: Thunderbird 2.0.0.14 (X11/20080501) MIME-Version: 1.0 To: Ralf Baechle Cc: Chris Friesen , linux-mips@linux-mips.org, Thiemo Seufer Subject: Re: looking for help interpreting softlockup/stack trace References: <48989AFE.5000500@nortel.com> <20080805191618.GB8629@linux-mips.org> <4899F41C.5070401@avtrex.com> <20080807134323.GA15703@linux-mips.org> In-Reply-To: <20080807134323.GA15703@linux-mips.org> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 07 Aug 2008 21:57:53.0128 (UTC) FILETIME=[A42FCE80:01C8F8D8] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20155 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ddaney@avtrex.com Precedence: bulk X-list: linux-mips Ralf Baechle wrote: > On Wed, Aug 06, 2008 at 11:57:32AM -0700, David Daney wrote: > >>>> In the trace below, is "epc" the program counter at the time of the >>>> timer interrupt? How does "ra" fit into this, given that the >>>> function whose address it contains isn't seen in the stack trace >>>> until quite a ways down? >>> $LBB378 is an internal symbol. The value of RA may not be very informative >>> if it was overwritten by a random subroutine call. >>> >> I have thought about eliminating these internal labels when the module's symbols are read. Would this make any sense? > > I think so. Maybe that could even be done when the module is linked. I > don't think there are ever any relocations against these local symbols. > Thiemo? > I take it back. Most of the $LC... symbols (typically string constants) are needed for relocations. Currently I cannot find in my builds any $LB... symbols. I wonder if gcc-4.3 eliminates these. I think the reason they show up in stack traces is that they are data pointers that have been stored on the stack that are misinterpreted as function return addresses. I wonder what would happen if we compiled all the code with -funwind-tables and had a small DWARF2 unwinder ala GCC's C++ exception handling mechanism. That would allow exact stack traces with no runtime overhead. David Daney From ralf@linux-mips.org Fri Aug 8 09:24:17 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 08 Aug 2008 09:24:26 +0100 (BST) Received: from ditditdahdahdah-dahdahdahditdit.dl5rb.org.uk ([217.169.26.28]:4536 "EHLO ditditdahdahdah-dahdahdahditdit.dl5rb.org.uk") by ftp.linux-mips.org with ESMTP id S20033237AbYHHIYR (ORCPT ); Fri, 8 Aug 2008 09:24:17 +0100 Received: from denk.linux-mips.net (denk.linux-mips.net [127.0.0.1]) by ditditdahdahdah-dahdahdahditdit.dl5rb.org.uk (8.14.2/8.14.1) with ESMTP id m788O6ja011509; Fri, 8 Aug 2008 09:24:09 +0100 Received: (from ralf@localhost) by denk.linux-mips.net (8.14.2/8.14.2/Submit) id m788O4lk011506; Fri, 8 Aug 2008 09:24:04 +0100 Date: Fri, 8 Aug 2008 09:24:04 +0100 From: Ralf Baechle To: David VomLehn Cc: "linux-mips@linux-mips.org" Subject: Re: Anyone noticed that there are a lot of cache flushes after kunmap/kunmap_atomic is called? Message-ID: <20080808082404.GA27519@linux-mips.org> References: <489A5975.1000401@cisco.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <489A5975.1000401@cisco.com> User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20156 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips On Wed, Aug 06, 2008 at 07:09:57PM -0700, David VomLehn wrote: > On the MIPS processor, cache flushing is done based on virtual addresses. > However, in the Linux kernel, there are a lot of places where memory is > mapped with kmap or kmap_atomic, then unmapped with the corresponding > kunmap or kunmap_atomic and only *then* is the cache flushed. In other > words, we only flush the cache after we have dropped the mapping of > memory into a virtual address. I think this is generally wrong. > > This may really only affect those of us who have enabled high memory, but > it's pretty prevalent in kernel code. We noted this before, but have > apparently just been bitten by it. Is it just me or is there a fairly > widespread problem for processors that flush the cache using virtual > addresses? Not all MIPS processors have virtually indexed caches; some have physically indexed caches or caches which behave effectivly like physically indexed and MIPS highmem only tries to support the latter kinds of caches. Which means most of the cache flushes turn into nops anyway. Ralf From jfraser@broadcom.com Fri Aug 8 15:41:59 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 08 Aug 2008 15:42:08 +0100 (BST) Received: from mms1.broadcom.com ([216.31.210.17]:265 "EHLO mms1.broadcom.com") by ftp.linux-mips.org with ESMTP id S28579059AbYHHOl7 (ORCPT ); Fri, 8 Aug 2008 15:41:59 +0100 Received: from [10.11.16.99] by mms1.broadcom.com with ESMTP (Broadcom SMTP Relay (Email Firewall v6.3.2)); Fri, 08 Aug 2008 07:41:43 -0700 X-Server-Uuid: 02CED230-5797-4B57-9875-D5D2FEE4708A Received: by mail-irva-10.broadcom.com (Postfix, from userid 47) id 0C49A2B1; Fri, 8 Aug 2008 07:41:43 -0700 (PDT) Received: from mail-irva-8.broadcom.com (mail-irva-8 [10.11.18.52]) by mail-irva-10.broadcom.com (Postfix) with ESMTP id EBA1F2B0; Fri, 8 Aug 2008 07:41:42 -0700 (PDT) Received: from mail-irva-13.broadcom.com (mail-irva-13.broadcom.com [10.11.16.103]) by mail-irva-8.broadcom.com (MOS 3.7.5a-GA) with ESMTP id HBH95486; Fri, 8 Aug 2008 07:41:42 -0700 (PDT) Received: from [10.28.6.13] (lab-mhtb-013.ne.broadcom.com [10.28.6.13]) by mail-irva-13.broadcom.com (Postfix) with ESMTP id 47DD274D00; Fri, 8 Aug 2008 07:41:41 -0700 (PDT) Subject: Re: Anyone noticed that there are a lot of cache flushes after kunmap/kunmap_atomic is called? From: "Jon Fraser" Reply-to: jfraser@broadcom.com To: "Ralf Baechle" cc: "David VomLehn" , "linux-mips@linux-mips.org" In-Reply-To: <20080808082404.GA27519@linux-mips.org> References: <489A5975.1000401@cisco.com> <20080808082404.GA27519@linux-mips.org> Organization: Broadcom Date: Fri, 08 Aug 2008 10:41:39 -0400 Message-ID: <1218206499.20791.152.camel@chaos.ne.broadcom.com> MIME-Version: 1.0 X-Mailer: Evolution 2.12.3 (2.12.3-3.fc8) X-WSS-ID: 648284AD4E0109962554-01-01 Content-Type: text/plain Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20157 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jfraser@broadcom.com Precedence: bulk X-list: linux-mips David, I'm battling this now. Our mips 24k has a virtually indexed cache. We're definitely seeing issues where the cache hasn't been flushed for highmem pages. I thought I had this fixed, but I'm still seeing some problems. Jon On Fri, 2008-08-08 at 09:24 +0100, Ralf Baechle wrote: > On Wed, Aug 06, 2008 at 07:09:57PM -0700, David VomLehn wrote: > > > On the MIPS processor, cache flushing is done based on virtual addresses. > > However, in the Linux kernel, there are a lot of places where memory is > > mapped with kmap or kmap_atomic, then unmapped with the corresponding > > kunmap or kunmap_atomic and only *then* is the cache flushed. In other > > words, we only flush the cache after we have dropped the mapping of > > memory into a virtual address. I think this is generally wrong. > > > > This may really only affect those of us who have enabled high memory, but > > it's pretty prevalent in kernel code. We noted this before, but have > > apparently just been bitten by it. Is it just me or is there a fairly > > widespread problem for processors that flush the cache using virtual > > addresses? > > Not all MIPS processors have virtually indexed caches; some have physically > indexed caches or caches which behave effectivly like physically indexed > and MIPS highmem only tries to support the latter kinds of caches. Which > means most of the cache flushes turn into nops anyway. > > Ralf > > From bunk@kernel.org Fri Aug 8 16:20:22 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 08 Aug 2008 16:20:31 +0100 (BST) Received: from smtp5.pp.htv.fi ([213.243.153.39]:47340 "EHLO smtp5.pp.htv.fi") by ftp.linux-mips.org with ESMTP id S28577907AbYHHPUW (ORCPT ); Fri, 8 Aug 2008 16:20:22 +0100 Received: from cs181140183.pp.htv.fi (cs181140183.pp.htv.fi [82.181.140.183]) by smtp5.pp.htv.fi (Postfix) with ESMTP id 6B8455BC048; Fri, 8 Aug 2008 18:20:19 +0300 (EEST) Date: Fri, 8 Aug 2008 18:18:46 +0300 From: Adrian Bunk To: Alan Cox , Wim Van Sebroeck Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, Andrew Morton Subject: [2.6 patch] fix watchdog/txx9wdt.c compilation Message-ID: <20080808151846.GA14495@cs181140183.pp.htv.fi> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20158 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: bunk@kernel.org Precedence: bulk X-list: linux-mips This patch fixes the following compile error caused by commit 8dc244f7deac4c0e95ce0ffd26f494bb6e1534c0 ([WATCHDOG 48/57] txx9: Fix locking, switch to unlocked_ioctl): <-- snip --> ... CC drivers/watchdog/txx9wdt.o txx9wdt.c:48: warning: type defaults to 'int' in declaration of txx9wdt.c:48: warning: parameter names (without types) in function txx9wdt.c: In function 'txx9wdt_ping': txx9wdt.c:52: error: 'txx9_lock' undeclared (first use in this function) txx9wdt.c:52: error: (Each undeclared identifier is reported only once txx9wdt.c:52: error: for each function it appears in.) txx9wdt.c: In function 'txx9wdt_start': txx9wdt.c:59: error: 'txx9_lock' undeclared (first use in this function) txx9wdt.c: In function 'txx9wdt_stop': txx9wdt.c:71: error: 'txx9_lock' undeclared (first use in this function) make[3]: *** [drivers/watchdog/txx9wdt.o] Error 1 <-- snip --> Reported-by: Adrian Bunk Signed-off-by: Adrian Bunk --- b29c2476cf814321b4ece7e359248b9a3046fc38 diff --git a/drivers/watchdog/txx9wdt.c b/drivers/watchdog/txx9wdt.c index dbbc018..6adab77 100644 --- a/drivers/watchdog/txx9wdt.c +++ b/drivers/watchdog/txx9wdt.c @@ -45,7 +45,7 @@ static unsigned long txx9wdt_alive; static int expect_close; static struct txx9_tmr_reg __iomem *txx9wdt_reg; static struct clk *txx9_imclk; -static DECLARE_LOCK(txx9_lock); +static DEFINE_SPINLOCK(txx9_lock); static void txx9wdt_ping(void) { From bunk@kernel.org Fri Aug 8 17:36:26 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 08 Aug 2008 17:36:35 +0100 (BST) Received: from smtp4.pp.htv.fi ([213.243.153.38]:64962 "EHLO smtp4.pp.htv.fi") by ftp.linux-mips.org with ESMTP id S28579198AbYHHQg0 (ORCPT ); Fri, 8 Aug 2008 17:36:26 +0100 Received: from cs181140183.pp.htv.fi (cs181140183.pp.htv.fi [82.181.140.183]) by smtp4.pp.htv.fi (Postfix) with ESMTP id DBD4E5BC02D; Fri, 8 Aug 2008 19:36:23 +0300 (EEST) Date: Fri, 8 Aug 2008 19:34:50 +0300 From: Adrian Bunk To: ralf@linux-mips.org Cc: linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, Andrew Morton , David Brownell Subject: [10/17] mips: use bcd2bin/bin2bcd Message-ID: <20080808163450.GQ14495@cs181140183.pp.htv.fi> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20159 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: bunk@kernel.org Precedence: bulk X-list: linux-mips This patch changes to use the new bcd2bin/bin2bcd functions instead of the obsolete BCD_TO_BIN/BIN_TO_BCD/BCD2BIN/BIN2BCD macros. Signed-off-by: Adrian Bunk --- arch/mips/dec/time.c | 18 +++++++-------- arch/mips/pmc-sierra/yosemite/setup.c | 30 ++++++++++++------------- arch/mips/sgi-ip22/ip22-time.c | 24 ++++++++++---------- arch/mips/sgi-ip27/ip27-timer.c | 18 +++++++-------- arch/mips/sibyte/swarm/rtc_m41t81.c | 26 ++++++++++----------- arch/mips/sibyte/swarm/rtc_xicor1241.c | 26 ++++++++++----------- include/asm-mips/mc146818-time.h | 18 +++++++-------- 7 files changed, 80 insertions(+), 80 deletions(-) ed015dd05f562b841288c18297f579191d652da9 diff --git a/arch/mips/dec/time.c b/arch/mips/dec/time.c index 3965fda..1359c03 100644 --- a/arch/mips/dec/time.c +++ b/arch/mips/dec/time.c @@ -45,12 +45,12 @@ unsigned long read_persistent_clock(void) spin_unlock_irqrestore(&rtc_lock, flags); if (!(CMOS_READ(RTC_CONTROL) & RTC_DM_BINARY) || RTC_ALWAYS_BCD) { - sec = BCD2BIN(sec); - min = BCD2BIN(min); - hour = BCD2BIN(hour); - day = BCD2BIN(day); - mon = BCD2BIN(mon); - year = BCD2BIN(year); + sec = bcd2bin(sec); + min = bcd2bin(min); + hour = bcd2bin(hour); + day = bcd2bin(day); + mon = bcd2bin(mon); + year = bcd2bin(year); } year += real_year - 72 + 2000; @@ -83,7 +83,7 @@ int rtc_mips_set_mmss(unsigned long nowtime) cmos_minutes = CMOS_READ(RTC_MINUTES); if (!(save_control & RTC_DM_BINARY) || RTC_ALWAYS_BCD) - cmos_minutes = BCD2BIN(cmos_minutes); + cmos_minutes = bcd2bin(cmos_minutes); /* * since we're only adjusting minutes and seconds, @@ -99,8 +99,8 @@ int rtc_mips_set_mmss(unsigned long nowtime) if (abs(real_minutes - cmos_minutes) < 30) { if (!(save_control & RTC_DM_BINARY) || RTC_ALWAYS_BCD) { - real_seconds = BIN2BCD(real_seconds); - real_minutes = BIN2BCD(real_minutes); + real_seconds = bin2bcd(real_seconds); + real_minutes = bin2bcd(real_minutes); } CMOS_WRITE(real_seconds, RTC_SECONDS); CMOS_WRITE(real_minutes, RTC_MINUTES); diff --git a/arch/mips/pmc-sierra/yosemite/setup.c b/arch/mips/pmc-sierra/yosemite/setup.c index 6537d90..2d3c0dc 100644 --- a/arch/mips/pmc-sierra/yosemite/setup.c +++ b/arch/mips/pmc-sierra/yosemite/setup.c @@ -79,14 +79,14 @@ unsigned long read_persistent_clock(void) /* Stop the update to the time */ m48t37_base->control = 0x40; - year = BCD2BIN(m48t37_base->year); - year += BCD2BIN(m48t37_base->century) * 100; + year = bcd2bin(m48t37_base->year); + year += bcd2bin(m48t37_base->century) * 100; - month = BCD2BIN(m48t37_base->month); - day = BCD2BIN(m48t37_base->date); - hour = BCD2BIN(m48t37_base->hour); - min = BCD2BIN(m48t37_base->min); - sec = BCD2BIN(m48t37_base->sec); + month = bcd2bin(m48t37_base->month); + day = bcd2bin(m48t37_base->date); + hour = bcd2bin(m48t37_base->hour); + min = bcd2bin(m48t37_base->min); + sec = bcd2bin(m48t37_base->sec); /* Start the update to the time again */ m48t37_base->control = 0x00; @@ -113,22 +113,22 @@ int rtc_mips_set_time(unsigned long tim) m48t37_base->control = 0x80; /* year */ - m48t37_base->year = BIN2BCD(tm.tm_year % 100); - m48t37_base->century = BIN2BCD(tm.tm_year / 100); + m48t37_base->year = bin2bcd(tm.tm_year % 100); + m48t37_base->century = bin2bcd(tm.tm_year / 100); /* month */ - m48t37_base->month = BIN2BCD(tm.tm_mon); + m48t37_base->month = bin2bcd(tm.tm_mon); /* day */ - m48t37_base->date = BIN2BCD(tm.tm_mday); + m48t37_base->date = bin2bcd(tm.tm_mday); /* hour/min/sec */ - m48t37_base->hour = BIN2BCD(tm.tm_hour); - m48t37_base->min = BIN2BCD(tm.tm_min); - m48t37_base->sec = BIN2BCD(tm.tm_sec); + m48t37_base->hour = bin2bcd(tm.tm_hour); + m48t37_base->min = bin2bcd(tm.tm_min); + m48t37_base->sec = bin2bcd(tm.tm_sec); /* day of week -- not really used, but let's keep it up-to-date */ - m48t37_base->day = BIN2BCD(tm.tm_wday + 1); + m48t37_base->day = bin2bcd(tm.tm_wday + 1); /* disable writing */ m48t37_base->control = 0x00; diff --git a/arch/mips/sgi-ip22/ip22-time.c b/arch/mips/sgi-ip22/ip22-time.c index 10e5054..90de2bc 100644 --- a/arch/mips/sgi-ip22/ip22-time.c +++ b/arch/mips/sgi-ip22/ip22-time.c @@ -43,12 +43,12 @@ unsigned long read_persistent_clock(void) save_control = hpc3c0->rtcregs[RTC_CMD] & 0xff; hpc3c0->rtcregs[RTC_CMD] = save_control | RTC_TE; - sec = BCD2BIN(hpc3c0->rtcregs[RTC_SECONDS] & 0xff); - min = BCD2BIN(hpc3c0->rtcregs[RTC_MINUTES] & 0xff); - hrs = BCD2BIN(hpc3c0->rtcregs[RTC_HOURS] & 0x3f); - day = BCD2BIN(hpc3c0->rtcregs[RTC_DATE] & 0xff); - mon = BCD2BIN(hpc3c0->rtcregs[RTC_MONTH] & 0x1f); - yrs = BCD2BIN(hpc3c0->rtcregs[RTC_YEAR] & 0xff); + sec = bcd2bin(hpc3c0->rtcregs[RTC_SECONDS] & 0xff); + min = bcd2bin(hpc3c0->rtcregs[RTC_MINUTES] & 0xff); + hrs = bcd2bin(hpc3c0->rtcregs[RTC_HOURS] & 0x3f); + day = bcd2bin(hpc3c0->rtcregs[RTC_DATE] & 0xff); + mon = bcd2bin(hpc3c0->rtcregs[RTC_MONTH] & 0x1f); + yrs = bcd2bin(hpc3c0->rtcregs[RTC_YEAR] & 0xff); hpc3c0->rtcregs[RTC_CMD] = save_control; spin_unlock_irqrestore(&rtc_lock, flags); @@ -78,12 +78,12 @@ int rtc_mips_set_time(unsigned long tim) save_control = hpc3c0->rtcregs[RTC_CMD] & 0xff; hpc3c0->rtcregs[RTC_CMD] = save_control | RTC_TE; - hpc3c0->rtcregs[RTC_YEAR] = BIN2BCD(tm.tm_year); - hpc3c0->rtcregs[RTC_MONTH] = BIN2BCD(tm.tm_mon); - hpc3c0->rtcregs[RTC_DATE] = BIN2BCD(tm.tm_mday); - hpc3c0->rtcregs[RTC_HOURS] = BIN2BCD(tm.tm_hour); - hpc3c0->rtcregs[RTC_MINUTES] = BIN2BCD(tm.tm_min); - hpc3c0->rtcregs[RTC_SECONDS] = BIN2BCD(tm.tm_sec); + hpc3c0->rtcregs[RTC_YEAR] = bin2bcd(tm.tm_year); + hpc3c0->rtcregs[RTC_MONTH] = bin2bcd(tm.tm_mon); + hpc3c0->rtcregs[RTC_DATE] = bin2bcd(tm.tm_mday); + hpc3c0->rtcregs[RTC_HOURS] = bin2bcd(tm.tm_hour); + hpc3c0->rtcregs[RTC_MINUTES] = bin2bcd(tm.tm_min); + hpc3c0->rtcregs[RTC_SECONDS] = bin2bcd(tm.tm_sec); hpc3c0->rtcregs[RTC_HUNDREDTH_SECOND] = 0; hpc3c0->rtcregs[RTC_CMD] = save_control; diff --git a/arch/mips/sgi-ip27/ip27-timer.c b/arch/mips/sgi-ip27/ip27-timer.c index 8b4e854..d162812 100644 --- a/arch/mips/sgi-ip27/ip27-timer.c +++ b/arch/mips/sgi-ip27/ip27-timer.c @@ -41,7 +41,7 @@ static int set_rtc_mmss(unsigned long nowtime) IOC3_BYTEBUS_DEV0); rtc->control |= M48T35_RTC_READ; - cmos_minutes = BCD2BIN(rtc->min); + cmos_minutes = bcd2bin(rtc->min); rtc->control &= ~M48T35_RTC_READ; /* @@ -56,8 +56,8 @@ static int set_rtc_mmss(unsigned long nowtime) real_minutes %= 60; if (abs(real_minutes - cmos_minutes) < 30) { - real_seconds = BIN2BCD(real_seconds); - real_minutes = BIN2BCD(real_minutes); + real_seconds = bin2bcd(real_seconds); + real_minutes = bin2bcd(real_minutes); rtc->control |= M48T35_RTC_SET; rtc->sec = real_seconds; rtc->min = real_minutes; @@ -99,12 +99,12 @@ unsigned long read_persistent_clock(void) year = rtc->year; rtc->control &= ~M48T35_RTC_READ; - sec = BCD2BIN(sec); - min = BCD2BIN(min); - hour = BCD2BIN(hour); - date = BCD2BIN(date); - month = BCD2BIN(month); - year = BCD2BIN(year); + sec = bcd2bin(sec); + min = bcd2bin(min); + hour = bcd2bin(hour); + date = bcd2bin(date); + month = bcd2bin(month); + year = bcd2bin(year); year += 1970; diff --git a/arch/mips/sibyte/swarm/rtc_m41t81.c b/arch/mips/sibyte/swarm/rtc_m41t81.c index 26fbff4..b732600 100644 --- a/arch/mips/sibyte/swarm/rtc_m41t81.c +++ b/arch/mips/sibyte/swarm/rtc_m41t81.c @@ -156,32 +156,32 @@ int m41t81_set_time(unsigned long t) */ spin_lock_irqsave(&rtc_lock, flags); - tm.tm_sec = BIN2BCD(tm.tm_sec); + tm.tm_sec = bin2bcd(tm.tm_sec); m41t81_write(M41T81REG_SC, tm.tm_sec); - tm.tm_min = BIN2BCD(tm.tm_min); + tm.tm_min = bin2bcd(tm.tm_min); m41t81_write(M41T81REG_MN, tm.tm_min); - tm.tm_hour = BIN2BCD(tm.tm_hour); + tm.tm_hour = bin2bcd(tm.tm_hour); tm.tm_hour = (tm.tm_hour & 0x3f) | (m41t81_read(M41T81REG_HR) & 0xc0); m41t81_write(M41T81REG_HR, tm.tm_hour); /* tm_wday starts from 0 to 6 */ if (tm.tm_wday == 0) tm.tm_wday = 7; - tm.tm_wday = BIN2BCD(tm.tm_wday); + tm.tm_wday = bin2bcd(tm.tm_wday); m41t81_write(M41T81REG_DY, tm.tm_wday); - tm.tm_mday = BIN2BCD(tm.tm_mday); + tm.tm_mday = bin2bcd(tm.tm_mday); m41t81_write(M41T81REG_DT, tm.tm_mday); /* tm_mon starts from 0, *ick* */ tm.tm_mon ++; - tm.tm_mon = BIN2BCD(tm.tm_mon); + tm.tm_mon = bin2bcd(tm.tm_mon); m41t81_write(M41T81REG_MO, tm.tm_mon); /* we don't do century, everything is beyond 2000 */ tm.tm_year %= 100; - tm.tm_year = BIN2BCD(tm.tm_year); + tm.tm_year = bin2bcd(tm.tm_year); m41t81_write(M41T81REG_YR, tm.tm_year); spin_unlock_irqrestore(&rtc_lock, flags); @@ -209,12 +209,12 @@ unsigned long m41t81_get_time(void) year = m41t81_read(M41T81REG_YR); spin_unlock_irqrestore(&rtc_lock, flags); - sec = BCD2BIN(sec); - min = BCD2BIN(min); - hour = BCD2BIN(hour); - day = BCD2BIN(day); - mon = BCD2BIN(mon); - year = BCD2BIN(year); + sec = bcd2bin(sec); + min = bcd2bin(min); + hour = bcd2bin(hour); + day = bcd2bin(day); + mon = bcd2bin(mon); + year = bcd2bin(year); year += 2000; diff --git a/arch/mips/sibyte/swarm/rtc_xicor1241.c b/arch/mips/sibyte/swarm/rtc_xicor1241.c index ff3e5da..4438b21 100644 --- a/arch/mips/sibyte/swarm/rtc_xicor1241.c +++ b/arch/mips/sibyte/swarm/rtc_xicor1241.c @@ -124,18 +124,18 @@ int xicor_set_time(unsigned long t) xicor_write(X1241REG_SR, X1241REG_SR_WEL | X1241REG_SR_RWEL); /* trivial ones */ - tm.tm_sec = BIN2BCD(tm.tm_sec); + tm.tm_sec = bin2bcd(tm.tm_sec); xicor_write(X1241REG_SC, tm.tm_sec); - tm.tm_min = BIN2BCD(tm.tm_min); + tm.tm_min = bin2bcd(tm.tm_min); xicor_write(X1241REG_MN, tm.tm_min); - tm.tm_mday = BIN2BCD(tm.tm_mday); + tm.tm_mday = bin2bcd(tm.tm_mday); xicor_write(X1241REG_DT, tm.tm_mday); /* tm_mon starts from 0, *ick* */ tm.tm_mon ++; - tm.tm_mon = BIN2BCD(tm.tm_mon); + tm.tm_mon = bin2bcd(tm.tm_mon); xicor_write(X1241REG_MO, tm.tm_mon); /* year is split */ @@ -148,7 +148,7 @@ int xicor_set_time(unsigned long t) tmp = xicor_read(X1241REG_HR); if (tmp & X1241REG_HR_MIL) { /* 24 hour format */ - tm.tm_hour = BIN2BCD(tm.tm_hour); + tm.tm_hour = bin2bcd(tm.tm_hour); tmp = (tmp & ~0x3f) | (tm.tm_hour & 0x3f); } else { /* 12 hour format, with 0x2 for pm */ @@ -157,7 +157,7 @@ int xicor_set_time(unsigned long t) tmp |= 0x20; tm.tm_hour -= 12; } - tm.tm_hour = BIN2BCD(tm.tm_hour); + tm.tm_hour = bin2bcd(tm.tm_hour); tmp |= tm.tm_hour; } xicor_write(X1241REG_HR, tmp); @@ -191,13 +191,13 @@ unsigned long xicor_get_time(void) y2k = xicor_read(X1241REG_Y2K); spin_unlock_irqrestore(&rtc_lock, flags); - sec = BCD2BIN(sec); - min = BCD2BIN(min); - hour = BCD2BIN(hour); - day = BCD2BIN(day); - mon = BCD2BIN(mon); - year = BCD2BIN(year); - y2k = BCD2BIN(y2k); + sec = bcd2bin(sec); + min = bcd2bin(min); + hour = bcd2bin(hour); + day = bcd2bin(day); + mon = bcd2bin(mon); + year = bcd2bin(year); + y2k = bcd2bin(y2k); year += (y2k * 100); diff --git a/include/asm-mips/mc146818-time.h b/include/asm-mips/mc146818-time.h index cdc379a..199b457 100644 --- a/include/asm-mips/mc146818-time.h +++ b/include/asm-mips/mc146818-time.h @@ -44,7 +44,7 @@ static inline int mc146818_set_rtc_mmss(unsigned long nowtime) cmos_minutes = CMOS_READ(RTC_MINUTES); if (!(save_control & RTC_DM_BINARY) || RTC_ALWAYS_BCD) - BCD_TO_BIN(cmos_minutes); + cmos_minutes = bcd2bin(cmos_minutes); /* * since we're only adjusting minutes and seconds, @@ -60,8 +60,8 @@ static inline int mc146818_set_rtc_mmss(unsigned long nowtime) if (abs(real_minutes - cmos_minutes) < 30) { if (!(save_control & RTC_DM_BINARY) || RTC_ALWAYS_BCD) { - BIN_TO_BCD(real_seconds); - BIN_TO_BCD(real_minutes); + real_seconds = bin2bcd(real_seconds); + real_minutes = bin2bcd(real_minutes); } CMOS_WRITE(real_seconds, RTC_SECONDS); CMOS_WRITE(real_minutes, RTC_MINUTES); @@ -103,12 +103,12 @@ static inline unsigned long mc146818_get_cmos_time(void) } while (sec != CMOS_READ(RTC_SECONDS)); if (!(CMOS_READ(RTC_CONTROL) & RTC_DM_BINARY) || RTC_ALWAYS_BCD) { - BCD_TO_BIN(sec); - BCD_TO_BIN(min); - BCD_TO_BIN(hour); - BCD_TO_BIN(day); - BCD_TO_BIN(mon); - BCD_TO_BIN(year); + sec = bcd2bin(sec); + min = bcd2bin(min); + hour = bcd2bin(hour); + day = bcd2bin(day); + mon = bcd2bin(mon); + year = bcd2bin(year); } spin_unlock_irqrestore(&rtc_lock, flags); year = mc146818_decode_year(year); From wim@iguana.be Fri Aug 8 18:56:11 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Fri, 08 Aug 2008 18:56:20 +0100 (BST) Received: from mailrelay002.isp.belgacom.be ([195.238.6.175]:54332 "EHLO mailrelay002.isp.belgacom.be") by ftp.linux-mips.org with ESMTP id S28580793AbYHHR4L (ORCPT ); Fri, 8 Aug 2008 18:56:11 +0100 X-Belgacom-Dynamic: yes X-IronPort-Anti-Spam-Filtered: true X-IronPort-Anti-Spam-Result: AnkFAJ8lnEhR8DtG/2dsb2JhbACBXKs6 Received: from 70.59-240-81.adsl-dyn.isp.belgacom.be (HELO infomag.iguana.be) ([81.240.59.70]) by relay.skynet.be with ESMTP; 08 Aug 2008 19:56:05 +0200 Received: from infomag.iguana.be (localhost.localdomain [127.0.0.1]) by infomag.iguana.be (8.13.8/8.12.11) with ESMTP id m78Hu54s013247; Fri, 8 Aug 2008 19:56:05 +0200 Received: (from wim@localhost) by infomag.iguana.be (8.13.8/8.13.8/Submit) id m78Hu5ZJ013246; Fri, 8 Aug 2008 19:56:05 +0200 Date: Fri, 8 Aug 2008 19:56:05 +0200 From: Wim Van Sebroeck To: Adrian Bunk Cc: Alan Cox , linux-mips@linux-mips.org, linux-kernel@vger.kernel.org, Andrew Morton Subject: Re: [2.6 patch] fix watchdog/txx9wdt.c compilation Message-ID: <20080808175605.GE2773@infomag.infomag.iguana.be> References: <20080808151846.GA14495@cs181140183.pp.htv.fi> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20080808151846.GA14495@cs181140183.pp.htv.fi> User-Agent: Mutt/1.4.2.1i Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20160 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: wim@iguana.be Precedence: bulk X-list: linux-mips Hi Adrian, > This patch fixes the following compile error caused by > commit 8dc244f7deac4c0e95ce0ffd26f494bb6e1534c0 > ([WATCHDOG 48/57] txx9: Fix locking, switch to unlocked_ioctl): Will also be added. Kind regards, Wim. From tsbogend@alpha.franken.de Sat Aug 9 11:25:49 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 09 Aug 2008 11:25:53 +0100 (BST) Received: from elvis.franken.de ([193.175.24.41]:46985 "EHLO elvis.franken.de") by ftp.linux-mips.org with ESMTP id S20045367AbYHIKZt (ORCPT ); Sat, 9 Aug 2008 11:25:49 +0100 Received: from uucp (helo=solo.franken.de) by elvis.franken.de with local-bsmtp (Exim 3.36 #1) id 1KRldr-000090-01; Sat, 09 Aug 2008 12:25:47 +0200 Received: by solo.franken.de (Postfix, from userid 1000) id 897DEC3163; Sat, 9 Aug 2008 12:25:33 +0200 (CEST) From: Thomas Bogendoerfer Subject: [PATCH v2] IP22/28: Switch over to RTC class driver To: linux-mips@linux-mips.org cc: ralf@linux-mips.org Message-Id: <20080809102533.897DEC3163@solo.franken.de> Date: Sat, 9 Aug 2008 12:25:33 +0200 (CEST) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20161 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: tsbogend@alpha.franken.de Precedence: bulk X-list: linux-mips This patchset removes some dead code and creates a platform device for the RTC class driver. Signed-off-by: Thomas Bogendoerfer --- Changes in v2: - corrected rtc resource end arch/mips/sgi-ip22/ip22-platform.c | 15 ++++++++ arch/mips/sgi-ip22/ip22-setup.c | 1 - arch/mips/sgi-ip22/ip22-time.c | 64 ----------------------------------- include/asm-mips/mach-ip22/ds1286.h | 18 ---------- include/asm-mips/mach-ip28/ds1286.h | 4 -- include/linux/ds1286.h | 2 - 6 files changed, 15 insertions(+), 89 deletions(-) diff --git a/arch/mips/sgi-ip22/ip22-platform.c b/arch/mips/sgi-ip22/ip22-platform.c index 6014123..9bbb90b 100644 --- a/arch/mips/sgi-ip22/ip22-platform.c +++ b/arch/mips/sgi-ip22/ip22-platform.c @@ -192,3 +192,18 @@ static int __init sgi_button_devinit(void) } device_initcall(sgi_button_devinit); + +static int __init sgi_ds1286_devinit(void) +{ + struct resource res; + + memset(&res, 0, sizeof(res)); + res.start = HPC3_CHIP0_BASE + offsetof(struct hpc3_regs, rtcregs); + res.end = res.start + sizeof(hpc3c0->rtcregs) - 1; + res.flags = IORESOURCE_MEM; + + return IS_ERR(platform_device_register_simple("rtc-ds1286", -1, + &res, 1)); +} + +device_initcall(sgi_ds1286_devinit); diff --git a/arch/mips/sgi-ip22/ip22-setup.c b/arch/mips/sgi-ip22/ip22-setup.c index 896a1ef..b9a9313 100644 --- a/arch/mips/sgi-ip22/ip22-setup.c +++ b/arch/mips/sgi-ip22/ip22-setup.c @@ -4,7 +4,6 @@ * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) * Copyright (C) 1997, 1998 Ralf Baechle (ralf@gnu.org) */ -#include #include #include #include diff --git a/arch/mips/sgi-ip22/ip22-time.c b/arch/mips/sgi-ip22/ip22-time.c index 10e5054..3dcb27e 100644 --- a/arch/mips/sgi-ip22/ip22-time.c +++ b/arch/mips/sgi-ip22/ip22-time.c @@ -10,7 +10,6 @@ * Copyright (C) 2003, 06 Ralf Baechle (ralf@linux-mips.org) */ #include -#include #include #include #include @@ -29,69 +28,6 @@ #include #include -/* - * Note that mktime uses month from 1 to 12 while rtc_time_to_tm - * uses 0 to 11. - */ -unsigned long read_persistent_clock(void) -{ - unsigned int yrs, mon, day, hrs, min, sec; - unsigned int save_control; - unsigned long flags; - - spin_lock_irqsave(&rtc_lock, flags); - save_control = hpc3c0->rtcregs[RTC_CMD] & 0xff; - hpc3c0->rtcregs[RTC_CMD] = save_control | RTC_TE; - - sec = BCD2BIN(hpc3c0->rtcregs[RTC_SECONDS] & 0xff); - min = BCD2BIN(hpc3c0->rtcregs[RTC_MINUTES] & 0xff); - hrs = BCD2BIN(hpc3c0->rtcregs[RTC_HOURS] & 0x3f); - day = BCD2BIN(hpc3c0->rtcregs[RTC_DATE] & 0xff); - mon = BCD2BIN(hpc3c0->rtcregs[RTC_MONTH] & 0x1f); - yrs = BCD2BIN(hpc3c0->rtcregs[RTC_YEAR] & 0xff); - - hpc3c0->rtcregs[RTC_CMD] = save_control; - spin_unlock_irqrestore(&rtc_lock, flags); - - if (yrs < 45) - yrs += 30; - if ((yrs += 40) < 70) - yrs += 100; - - return mktime(yrs + 1900, mon, day, hrs, min, sec); -} - -int rtc_mips_set_time(unsigned long tim) -{ - struct rtc_time tm; - unsigned int save_control; - unsigned long flags; - - rtc_time_to_tm(tim, &tm); - - tm.tm_mon += 1; /* tm_mon starts at zero */ - tm.tm_year -= 40; - if (tm.tm_year >= 100) - tm.tm_year -= 100; - - spin_lock_irqsave(&rtc_lock, flags); - save_control = hpc3c0->rtcregs[RTC_CMD] & 0xff; - hpc3c0->rtcregs[RTC_CMD] = save_control | RTC_TE; - - hpc3c0->rtcregs[RTC_YEAR] = BIN2BCD(tm.tm_year); - hpc3c0->rtcregs[RTC_MONTH] = BIN2BCD(tm.tm_mon); - hpc3c0->rtcregs[RTC_DATE] = BIN2BCD(tm.tm_mday); - hpc3c0->rtcregs[RTC_HOURS] = BIN2BCD(tm.tm_hour); - hpc3c0->rtcregs[RTC_MINUTES] = BIN2BCD(tm.tm_min); - hpc3c0->rtcregs[RTC_SECONDS] = BIN2BCD(tm.tm_sec); - hpc3c0->rtcregs[RTC_HUNDREDTH_SECOND] = 0; - - hpc3c0->rtcregs[RTC_CMD] = save_control; - spin_unlock_irqrestore(&rtc_lock, flags); - - return 0; -} - static unsigned long dosample(void) { u32 ct0, ct1; diff --git a/include/asm-mips/mach-ip22/ds1286.h b/include/asm-mips/mach-ip22/ds1286.h deleted file mode 100644 index f19f1ea..0000000 --- a/include/asm-mips/mach-ip22/ds1286.h +++ /dev/null @@ -1,18 +0,0 @@ -/* - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1998, 2001, 03 by Ralf Baechle - * - * RTC routines for PC style attached Dallas chip. - */ -#ifndef __ASM_MACH_IP22_DS1286_H -#define __ASM_MACH_IP22_DS1286_H - -#include - -#define rtc_read(reg) (hpc3c0->rtcregs[(reg)] & 0xff) -#define rtc_write(data, reg) do { hpc3c0->rtcregs[(reg)] = (data); } while(0) - -#endif /* __ASM_MACH_IP22_DS1286_H */ diff --git a/include/asm-mips/mach-ip28/ds1286.h b/include/asm-mips/mach-ip28/ds1286.h deleted file mode 100644 index 471bb9a..0000000 --- a/include/asm-mips/mach-ip28/ds1286.h +++ /dev/null @@ -1,4 +0,0 @@ -#ifndef __ASM_MACH_IP28_DS1286_H -#define __ASM_MACH_IP28_DS1286_H -#include -#endif /* __ASM_MACH_IP28_DS1286_H */ diff --git a/include/linux/ds1286.h b/include/linux/ds1286.h index d898986..45ea0aa 100644 --- a/include/linux/ds1286.h +++ b/include/linux/ds1286.h @@ -8,8 +8,6 @@ #ifndef __LINUX_DS1286_H #define __LINUX_DS1286_H -#include - /********************************************************************** * register summary **********************************************************************/ From tsbogend@alpha.franken.de Sat Aug 9 11:26:10 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 09 Aug 2008 11:26:16 +0100 (BST) Received: from elvis.franken.de ([193.175.24.41]:47241 "EHLO elvis.franken.de") by ftp.linux-mips.org with ESMTP id S20045372AbYHIKZt (ORCPT ); Sat, 9 Aug 2008 11:25:49 +0100 Received: from uucp (helo=solo.franken.de) by elvis.franken.de with local-bsmtp (Exim 3.36 #1) id 1KRldr-000090-02; Sat, 09 Aug 2008 12:25:47 +0200 Received: by solo.franken.de (Postfix, from userid 1000) id 18C55C3163; Sat, 9 Aug 2008 12:25:39 +0200 (CEST) From: Thomas Bogendoerfer Subject: [PATCH v3] IP27: Switch over to RTC class driver To: linux-mips@linux-mips.org cc: ralf@linux-mips.org Message-Id: <20080809102539.18C55C3163@solo.franken.de> Date: Sat, 9 Aug 2008 12:25:39 +0200 (CEST) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20162 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: tsbogend@alpha.franken.de Precedence: bulk X-list: linux-mips This patchset removes some dead code and creates a platform device for the RTC class driver. Signed-off-by: Thomas Bogendoerfer --- Changes in v3: - correct rtc resource end Changes in v2: - use physical address for resource setup - use late_initcall until ioc3 resource conflict is resolved arch/mips/sgi-ip27/ip27-timer.c | 99 +++++++++------------------------------ 1 files changed, 22 insertions(+), 77 deletions(-) diff --git a/arch/mips/sgi-ip27/ip27-timer.c b/arch/mips/sgi-ip27/ip27-timer.c index 8b4e854..1327c27 100644 --- a/arch/mips/sgi-ip27/ip27-timer.c +++ b/arch/mips/sgi-ip27/ip27-timer.c @@ -13,12 +13,12 @@ #include #include #include +#include #include #include #include #include -#include #include #include #include @@ -28,51 +28,6 @@ #define TICK_SIZE (tick_nsec / 1000) -#if 0 -static int set_rtc_mmss(unsigned long nowtime) -{ - int retval = 0; - int real_seconds, real_minutes, cmos_minutes; - struct m48t35_rtc *rtc; - nasid_t nid; - - nid = get_nasid(); - rtc = (struct m48t35_rtc *)(KL_CONFIG_CH_CONS_INFO(nid)->memory_base + - IOC3_BYTEBUS_DEV0); - - rtc->control |= M48T35_RTC_READ; - cmos_minutes = BCD2BIN(rtc->min); - rtc->control &= ~M48T35_RTC_READ; - - /* - * Since we're only adjusting minutes and seconds, don't interfere with - * hour overflow. This avoids messing with unknown time zones but - * requires your RTC not to be off by more than 15 minutes - */ - real_seconds = nowtime % 60; - real_minutes = nowtime / 60; - if (((abs(real_minutes - cmos_minutes) + 15)/30) & 1) - real_minutes += 30; /* correct for half hour time zone */ - real_minutes %= 60; - - if (abs(real_minutes - cmos_minutes) < 30) { - real_seconds = BIN2BCD(real_seconds); - real_minutes = BIN2BCD(real_minutes); - rtc->control |= M48T35_RTC_SET; - rtc->sec = real_seconds; - rtc->min = real_minutes; - rtc->control &= ~M48T35_RTC_SET; - } else { - printk(KERN_WARNING - "set_rtc_mmss: can't update from %d to %d\n", - cmos_minutes, real_minutes); - retval = -1; - } - - return retval; -} -#endif - /* Includes for ioc3_init(). */ #include #include @@ -80,37 +35,6 @@ static int set_rtc_mmss(unsigned long nowtime) #include #include -unsigned long read_persistent_clock(void) -{ - unsigned int year, month, date, hour, min, sec; - struct m48t35_rtc *rtc; - nasid_t nid; - - nid = get_nasid(); - rtc = (struct m48t35_rtc *)(KL_CONFIG_CH_CONS_INFO(nid)->memory_base + - IOC3_BYTEBUS_DEV0); - - rtc->control |= M48T35_RTC_READ; - sec = rtc->sec; - min = rtc->min; - hour = rtc->hour; - date = rtc->date; - month = rtc->month; - year = rtc->year; - rtc->control &= ~M48T35_RTC_READ; - - sec = BCD2BIN(sec); - min = BCD2BIN(min); - hour = BCD2BIN(hour); - date = BCD2BIN(date); - month = BCD2BIN(month); - year = BCD2BIN(year); - - year += 1970; - - return mktime(year, month, date, hour, min, sec); -} - static void enable_rt_irq(unsigned int irq) { } @@ -286,6 +210,7 @@ void __cpuinit cpu_time_init(void) void __cpuinit hub_rtc_init(cnodeid_t cnode) { + /* * We only need to initialize the current node. * If this is not the current node then it is a cpuless @@ -301,3 +226,23 @@ void __cpuinit hub_rtc_init(cnodeid_t cnode) LOCAL_HUB_S(PI_RT_PEND_B, 0); } } + +static int __init sgi_ip27_rtc_devinit(void) +{ + struct resource res; + + memset(&res, 0, sizeof(res)); + res.start = XPHYSADDR(KL_CONFIG_CH_CONS_INFO(master_nasid)->memory_base + + IOC3_BYTEBUS_DEV0); + res.end = res.start + 32767; + res.flags = IORESOURCE_MEM; + + return IS_ERR(platform_device_register_simple("rtc-m48t35", -1, + &res, 1)); +} + +/* + * kludge make this a device_initcall after ioc3 resource conflicts + * are resolved + */ +late_initcall(sgi_ip27_rtc_devinit); From tsbogend@alpha.franken.de Sat Aug 9 11:26:33 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 09 Aug 2008 11:26:40 +0100 (BST) Received: from elvis.franken.de ([193.175.24.41]:48777 "EHLO elvis.franken.de") by ftp.linux-mips.org with ESMTP id S20045371AbYHIKZt (ORCPT ); Sat, 9 Aug 2008 11:25:49 +0100 Received: from uucp (helo=solo.franken.de) by elvis.franken.de with local-bsmtp (Exim 3.36 #1) id 1KRldr-000090-03; Sat, 09 Aug 2008 12:25:47 +0200 Received: by solo.franken.de (Postfix, from userid 1000) id F3F38C3163; Sat, 9 Aug 2008 12:25:41 +0200 (CEST) From: Thomas Bogendoerfer Subject: [PATCH v3] M48T35: new RTC driver To: rtc-linux@googlegroups.com, linux-mips@linux-mips.org cc: a.zummo@towertech.it, ralf@linux-mips.org Message-Id: <20080809102541.F3F38C3163@solo.franken.de> Date: Sat, 9 Aug 2008 12:25:41 +0200 (CEST) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20163 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: tsbogend@alpha.franken.de Precedence: bulk X-list: linux-mips This driver replaces the broken ip27-rtc driver in drivers/char and gives back RTC support for SGI IP27 machines. Signed-off-by: Thomas Bogendoerfer --- Changes in v3: - switch to bcd2bin/bin2bcd - do kzalloc with sizeof(struct m48t35_priv) Changes in v2: - don't depend on SGI_IP27 - use rtc_valid_tm() for tm validation - resource is now a physical address and is ioremapped now - added kludge to workaround current ioc3 resource conflict drivers/rtc/Kconfig | 9 ++ drivers/rtc/Makefile | 1 + drivers/rtc/rtc-m48t35.c | 237 ++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 247 insertions(+), 0 deletions(-) diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig index 90ab738..2e5a578 100644 --- a/drivers/rtc/Kconfig +++ b/drivers/rtc/Kconfig @@ -405,6 +405,15 @@ config RTC_DRV_M48T86 This driver can also be built as a module. If so, the module will be called rtc-m48t86. +config RTC_DRV_M48T35 + tristate "ST M48T35" + help + If you say Y here you will get support for the + ST M48T35 RTC chip. + + This driver can also be built as a module, if so, the module + will be called "rtc-m48t35". + config RTC_DRV_M48T59 tristate "ST M48T59" help diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile index 18622ef..7d10cc0 100644 --- a/drivers/rtc/Makefile +++ b/drivers/rtc/Makefile @@ -36,6 +36,7 @@ obj-$(CONFIG_RTC_DRV_FM3130) += rtc-fm3130.o obj-$(CONFIG_RTC_DRV_ISL1208) += rtc-isl1208.o obj-$(CONFIG_RTC_DRV_M41T80) += rtc-m41t80.o obj-$(CONFIG_RTC_DRV_M41T94) += rtc-m41t94.o +obj-$(CONFIG_RTC_DRV_M48T35) += rtc-m48t35.o obj-$(CONFIG_RTC_DRV_M48T59) += rtc-m48t59.o obj-$(CONFIG_RTC_DRV_M48T86) += rtc-m48t86.o obj-$(CONFIG_RTC_DRV_MAX6900) += rtc-max6900.o diff --git a/drivers/rtc/rtc-m48t35.c b/drivers/rtc/rtc-m48t35.c new file mode 100644 index 0000000..5317900 --- /dev/null +++ b/drivers/rtc/rtc-m48t35.c @@ -0,0 +1,237 @@ +/* + * Driver for the SGS-Thomson M48T35 Timekeeper RAM chip + * + * Copyright (C) 2000 Silicon Graphics, Inc. + * Written by Ulf Carlsson (ulfc@engr.sgi.com) + * + * Copyright (C) 2008 Thomas Bogendoerfer + * + * Based on code written by Paul Gortmaker. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include +#include +#include +#include + +#define DRV_VERSION "1.0" + +struct m48t35_rtc { + u8 pad[0x7ff8]; /* starts at 0x7ff8 */ + u8 control; + u8 sec; + u8 min; + u8 hour; + u8 day; + u8 date; + u8 month; + u8 year; +}; + +#define M48T35_RTC_SET 0x80 +#define M48T35_RTC_READ 0x40 + +struct m48t35_priv { + struct rtc_device *rtc; + struct m48t35_rtc __iomem *reg; + size_t size; + unsigned long baseaddr; + spinlock_t lock; +}; + +static int m48t35_read_time(struct device *dev, struct rtc_time *tm) +{ + struct m48t35_priv *priv = dev_get_drvdata(dev); + u8 control; + + /* + * Only the values that we read from the RTC are set. We leave + * tm_wday, tm_yday and tm_isdst untouched. Even though the + * RTC has RTC_DAY_OF_WEEK, we ignore it, as it is only updated + * by the RTC when initially set to a non-zero value. + */ + spin_lock_irq(&priv->lock); + control = readb(&priv->reg->control); + writeb(control | M48T35_RTC_READ, &priv->reg->control); + tm->tm_sec = readb(&priv->reg->sec); + tm->tm_min = readb(&priv->reg->min); + tm->tm_hour = readb(&priv->reg->hour); + tm->tm_mday = readb(&priv->reg->date); + tm->tm_mon = readb(&priv->reg->month); + tm->tm_year = readb(&priv->reg->year); + writeb(control, &priv->reg->control); + spin_unlock_irq(&priv->lock); + + tm->tm_sec = bcd2bin(tm->tm_sec); + tm->tm_min = bcd2bin(tm->tm_min); + tm->tm_hour = bcd2bin(tm->tm_hour); + tm->tm_mday = bcd2bin(tm->tm_mday); + tm->tm_mon = bcd2bin(tm->tm_mon); + tm->tm_year = bcd2bin(tm->tm_year); + + /* + * Account for differences between how the RTC uses the values + * and how they are defined in a struct rtc_time; + */ + tm->tm_year += 70; + if (tm->tm_year <= 69) + tm->tm_year += 100; + + tm->tm_mon--; + return rtc_valid_tm(tm); +} + +static int m48t35_set_time(struct device *dev, struct rtc_time *tm) +{ + struct m48t35_priv *priv = dev_get_drvdata(dev); + unsigned char mon, day, hrs, min, sec; + unsigned int yrs; + u8 control; + + yrs = tm->tm_year + 1900; + mon = tm->tm_mon + 1; /* tm_mon starts at zero */ + day = tm->tm_mday; + hrs = tm->tm_hour; + min = tm->tm_min; + sec = tm->tm_sec; + + if (!rtc_valid_tm(tm)) + return -EINVAL; + + if (yrs < 1970) + return -EINVAL; + + yrs -= 1970; + if (yrs > 255) /* They are unsigned */ + return -EINVAL; + + if (yrs > 169) + return -EINVAL; + + if (yrs >= 100) + yrs -= 100; + + sec = bin2bcd(sec); + min = bin2bcd(min); + hrs = bin2bcd(hrs); + day = bin2bcd(day); + mon = bin2bcd(mon); + yrs = bin2bcd(yrs); + + spin_lock_irq(&priv->lock); + control = readb(&priv->reg->control); + writeb(control | M48T35_RTC_SET, &priv->reg->control); + writeb(yrs, &priv->reg->year); + writeb(mon, &priv->reg->month); + writeb(day, &priv->reg->date); + writeb(hrs, &priv->reg->hour); + writeb(min, &priv->reg->min); + writeb(sec, &priv->reg->sec); + writeb(control, &priv->reg->control); + spin_unlock_irq(&priv->lock); + return 0; +} + +static const struct rtc_class_ops m48t35_ops = { + .read_time = m48t35_read_time, + .set_time = m48t35_set_time, +}; + +static int __devinit m48t35_probe(struct platform_device *pdev) +{ + struct rtc_device *rtc; + struct resource *res; + struct m48t35_priv *priv; + int ret = 0; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) + return -ENODEV; + priv = kzalloc(sizeof(struct m48t35_priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->size = res->end - res->start + 1; + /* + * kludge: remove the #ifndef after ioc3 resource + * conflicts are resolved + */ +#ifndef CONFIG_SGI_IP27 + if (!request_mem_region(res->start, priv->size, pdev->name)) { + ret = -EBUSY; + goto out; + } +#endif + priv->baseaddr = res->start; + priv->reg = ioremap(priv->baseaddr, priv->size); + if (!priv->reg) { + ret = -ENOMEM; + goto out; + } + spin_lock_init(&priv->lock); + rtc = rtc_device_register("m48t35", &pdev->dev, + &m48t35_ops, THIS_MODULE); + if (IS_ERR(rtc)) { + ret = PTR_ERR(rtc); + goto out; + } + priv->rtc = rtc; + platform_set_drvdata(pdev, priv); + return 0; + +out: + if (priv->rtc) + rtc_device_unregister(priv->rtc); + if (priv->reg) + iounmap(priv->reg); + if (priv->baseaddr) + release_mem_region(priv->baseaddr, priv->size); + kfree(priv); + return ret; +} + +static int __devexit m48t35_remove(struct platform_device *pdev) +{ + struct m48t35_priv *priv = platform_get_drvdata(pdev); + + rtc_device_unregister(priv->rtc); + iounmap(priv->reg); +#ifndef CONFIG_SGI_IP27 + release_mem_region(priv->baseaddr, priv->size); +#endif + kfree(priv); + return 0; +} + +static struct platform_driver m48t35_platform_driver = { + .driver = { + .name = "rtc-m48t35", + .owner = THIS_MODULE, + }, + .probe = m48t35_probe, + .remove = __devexit_p(m48t35_remove), +}; + +static int __init m48t35_init(void) +{ + return platform_driver_register(&m48t35_platform_driver); +} + +static void __exit m48t35_exit(void) +{ + platform_driver_unregister(&m48t35_platform_driver); +} + +MODULE_AUTHOR("Thomas Bogendoerfer "); +MODULE_DESCRIPTION("M48T35 RTC driver"); +MODULE_LICENSE("GPL"); +MODULE_VERSION(DRV_VERSION); +MODULE_ALIAS("platform:rtc-m48t35"); + +module_init(m48t35_init); +module_exit(m48t35_exit); From tsbogend@alpha.franken.de Sat Aug 9 11:26:56 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 09 Aug 2008 11:27:02 +0100 (BST) Received: from elvis.franken.de ([193.175.24.41]:48009 "EHLO elvis.franken.de") by ftp.linux-mips.org with ESMTP id S20045370AbYHIKZt (ORCPT ); Sat, 9 Aug 2008 11:25:49 +0100 Received: from uucp (helo=solo.franken.de) by elvis.franken.de with local-bsmtp (Exim 3.36 #1) id 1KRldr-000090-00; Sat, 09 Aug 2008 12:25:47 +0200 Received: by solo.franken.de (Postfix, from userid 1000) id 49CDBC315E; Sat, 9 Aug 2008 12:25:28 +0200 (CEST) From: Thomas Bogendoerfer Subject: [PATCH v2] DS1286: new RTC driver To: rtc-linux@googlegroups.com, linux-mips@linux-mips.org cc: a.zummo@towertech.it, ralf@linux-mips.org Message-Id: <20080809102528.49CDBC315E@solo.franken.de> Date: Sat, 9 Aug 2008 12:25:28 +0200 (CEST) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20164 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: tsbogend@alpha.franken.de Precedence: bulk X-list: linux-mips This driver replaces the broken DS1286 driver in drivers/char and gives back RTC support for SGI IP22 and IP28 machines. Signed-off-by: Thomas Bogendoerfer --- Changes in v2: - switch to bcd2bin/bin2bcd - do kzalloc with sizeof(struct ds1286_priv) - don't depend on SGI_HAS_DS1286 - use rtc_valid_tm() for tm validation drivers/rtc/Kconfig | 5 + drivers/rtc/Makefile | 1 + drivers/rtc/rtc-ds1286.c | 413 ++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 419 insertions(+), 0 deletions(-) diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig index 90ab738..ad4539a 100644 --- a/drivers/rtc/Kconfig +++ b/drivers/rtc/Kconfig @@ -352,6 +352,11 @@ config RTC_DRV_DS1216 help If you say yes here you get support for the Dallas DS1216 RTC chips. +config RTC_DRV_DS1286 + tristate "Dallas DS1286" + help + If you say yes here you get support for the Dallas DS1286 RTC chips. + config RTC_DRV_DS1302 tristate "Dallas DS1302" depends on SH_SECUREEDGE5410 diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile index 18622ef..e060802 100644 --- a/drivers/rtc/Makefile +++ b/drivers/rtc/Makefile @@ -23,6 +23,7 @@ obj-$(CONFIG_RTC_DRV_AT91SAM9) += rtc-at91sam9.o obj-$(CONFIG_RTC_DRV_BFIN) += rtc-bfin.o obj-$(CONFIG_RTC_DRV_CMOS) += rtc-cmos.o obj-$(CONFIG_RTC_DRV_DS1216) += rtc-ds1216.o +obj-$(CONFIG_RTC_DRV_DS1286) += rtc-ds1286.o obj-$(CONFIG_RTC_DRV_DS1302) += rtc-ds1302.o obj-$(CONFIG_RTC_DRV_DS1305) += rtc-ds1305.o obj-$(CONFIG_RTC_DRV_DS1307) += rtc-ds1307.o diff --git a/drivers/rtc/rtc-ds1286.c b/drivers/rtc/rtc-ds1286.c new file mode 100644 index 0000000..8a47855 --- /dev/null +++ b/drivers/rtc/rtc-ds1286.c @@ -0,0 +1,413 @@ +/* + * DS1286 Real Time Clock interface for Linux + * + * Copyright (C) 1998, 1999, 2000 Ralf Baechle + * Copyright (C) 2008 Thomas Bogendoerfer + * + * Based on code written by Paul Gortmaker. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#include +#include +#include +#include +#include + +#define DRV_VERSION "1.0" + +struct ds1286_priv { + struct rtc_device *rtc; + u32 __iomem *rtcregs; + size_t size; + unsigned long baseaddr; + spinlock_t lock; +}; + +static inline u8 ds1286_rtc_read(struct ds1286_priv *priv, int reg) +{ + return __raw_readl(&priv->rtcregs[reg]) & 0xff; +} + +static inline void ds1286_rtc_write(struct ds1286_priv *priv, u8 data, int reg) +{ + __raw_writel(data, &priv->rtcregs[reg]); +} + +#ifdef CONFIG_RTC_INTF_DEV + +static int ds1286_ioctl(struct device *dev, unsigned int cmd, unsigned long arg) +{ + struct ds1286_priv *priv = dev_get_drvdata(dev); + unsigned long flags; + unsigned char val; + + switch (cmd) { + case RTC_AIE_OFF: + /* Mask alarm int. enab. bit */ + spin_lock_irqsave(&priv->lock, flags); + val = ds1286_rtc_read(priv, RTC_CMD); + val |= RTC_TDM; + ds1286_rtc_write(priv, val, RTC_CMD); + spin_unlock_irqrestore(&priv->lock, flags); + break; + case RTC_AIE_ON: + /* Allow alarm interrupts. */ + spin_lock_irqsave(&priv->lock, flags); + val = ds1286_rtc_read(priv, RTC_CMD); + val &= ~RTC_TDM; + ds1286_rtc_write(priv, val, RTC_CMD); + spin_unlock_irqrestore(&priv->lock, flags); + break; + case RTC_WIE_OFF: + /* Mask watchdog int. enab. bit */ + spin_lock_irqsave(&priv->lock, flags); + val = ds1286_rtc_read(priv, RTC_CMD); + val |= RTC_WAM; + ds1286_rtc_write(priv, val, RTC_CMD); + spin_unlock_irqrestore(&priv->lock, flags); + break; + case RTC_WIE_ON: + /* Allow watchdog interrupts. */ + spin_lock_irqsave(&priv->lock, flags); + val = ds1286_rtc_read(priv, RTC_CMD); + val &= ~RTC_WAM; + ds1286_rtc_write(priv, val, RTC_CMD); + spin_unlock_irqrestore(&priv->lock, flags); + break; + default: + return -ENOIOCTLCMD; + } + return 0; +} + +#else +#define ds1286_ioctl NULL +#endif + +#ifdef CONFIG_PROC_FS + +static int ds1286_proc(struct device *dev, struct seq_file *seq) +{ + struct ds1286_priv *priv = dev_get_drvdata(dev); + unsigned char month, cmd, amode; + const char *s; + + month = ds1286_rtc_read(priv, RTC_MONTH); + seq_printf(seq, + "oscillator\t: %s\n" + "square_wave\t: %s\n", + (month & RTC_EOSC) ? "disabled" : "enabled", + (month & RTC_ESQW) ? "disabled" : "enabled"); + + amode = ((ds1286_rtc_read(priv, RTC_MINUTES_ALARM) & 0x80) >> 5) | + ((ds1286_rtc_read(priv, RTC_HOURS_ALARM) & 0x80) >> 6) | + ((ds1286_rtc_read(priv, RTC_DAY_ALARM) & 0x80) >> 7); + switch (amode) { + case 7: + s = "each minute"; + break; + case 3: + s = "minutes match"; + break; + case 1: + s = "hours and minutes match"; + break; + case 0: + s = "days, hours and minutes match"; + break; + default: + s = "invalid"; + break; + } + seq_printf(seq, "alarm_mode\t: %s\n", s); + + cmd = ds1286_rtc_read(priv, RTC_CMD); + seq_printf(seq, + "alarm_enable\t: %s\n" + "wdog_alarm\t: %s\n" + "alarm_mask\t: %s\n" + "wdog_alarm_mask\t: %s\n" + "interrupt_mode\t: %s\n" + "INTB_mode\t: %s_active\n" + "interrupt_pins\t: %s\n", + (cmd & RTC_TDF) ? "yes" : "no", + (cmd & RTC_WAF) ? "yes" : "no", + (cmd & RTC_TDM) ? "disabled" : "enabled", + (cmd & RTC_WAM) ? "disabled" : "enabled", + (cmd & RTC_PU_LVL) ? "pulse" : "level", + (cmd & RTC_IBH_LO) ? "low" : "high", + (cmd & RTC_IPSW) ? "unswapped" : "swapped"); + return 0; +} + +#else +#define ds1286_proc NULL +#endif + +static int ds1286_read_time(struct device *dev, struct rtc_time *tm) +{ + struct ds1286_priv *priv = dev_get_drvdata(dev); + unsigned char save_control; + unsigned long flags; + unsigned long uip_watchdog = jiffies; + + /* + * read RTC once any update in progress is done. The update + * can take just over 2ms. We wait 10 to 20ms. There is no need to + * to poll-wait (up to 1s - eeccch) for the falling edge of RTC_UIP. + * If you need to know *exactly* when a second has started, enable + * periodic update complete interrupts, (via ioctl) and then + * immediately read /dev/rtc which will block until you get the IRQ. + * Once the read clears, read the RTC time (again via ioctl). Easy. + */ + + if (ds1286_rtc_read(priv, RTC_CMD) & RTC_TE) + while (time_before(jiffies, uip_watchdog + 2*HZ/100)) + barrier(); + + /* + * Only the values that we read from the RTC are set. We leave + * tm_wday, tm_yday and tm_isdst untouched. Even though the + * RTC has RTC_DAY_OF_WEEK, we ignore it, as it is only updated + * by the RTC when initially set to a non-zero value. + */ + spin_lock_irqsave(&priv->lock, flags); + save_control = ds1286_rtc_read(priv, RTC_CMD); + ds1286_rtc_write(priv, (save_control|RTC_TE), RTC_CMD); + + tm->tm_sec = ds1286_rtc_read(priv, RTC_SECONDS); + tm->tm_min = ds1286_rtc_read(priv, RTC_MINUTES); + tm->tm_hour = ds1286_rtc_read(priv, RTC_HOURS) & 0x3f; + tm->tm_mday = ds1286_rtc_read(priv, RTC_DATE); + tm->tm_mon = ds1286_rtc_read(priv, RTC_MONTH) & 0x1f; + tm->tm_year = ds1286_rtc_read(priv, RTC_YEAR); + + ds1286_rtc_write(priv, save_control, RTC_CMD); + spin_unlock_irqrestore(&priv->lock, flags); + + tm->tm_sec = bcd2bin(tm->tm_sec); + tm->tm_min = bcd2bin(tm->tm_min); + tm->tm_hour = bcd2bin(tm->tm_hour); + tm->tm_mday = bcd2bin(tm->tm_mday); + tm->tm_mon = bcd2bin(tm->tm_mon); + tm->tm_year = bcd2bin(tm->tm_year); + + /* + * Account for differences between how the RTC uses the values + * and how they are defined in a struct rtc_time; + */ + if (tm->tm_year < 45) + tm->tm_year += 30; + tm->tm_year += 40; + if (tm->tm_year < 70) + tm->tm_year += 100; + + tm->tm_mon--; + + return rtc_valid_tm(tm); +} + +static int ds1286_set_time(struct device *dev, struct rtc_time *tm) +{ + struct ds1286_priv *priv = dev_get_drvdata(dev); + unsigned char mon, day, hrs, min, sec; + unsigned char save_control; + unsigned int yrs; + unsigned long flags; + + + if (!rtc_valid_tm(tm)) + return -EINVAL; + + yrs = tm->tm_year + 1900; + mon = tm->tm_mon + 1; /* tm_mon starts at zero */ + day = tm->tm_mday; + hrs = tm->tm_hour; + min = tm->tm_min; + sec = tm->tm_sec; + + if (yrs < 1970) + return -EINVAL; + + yrs -= 1940; + if (yrs > 255) /* They are unsigned */ + return -EINVAL; + + if (yrs >= 100) + yrs -= 100; + + sec = bin2bcd(sec); + min = bin2bcd(min); + hrs = bin2bcd(hrs); + day = bin2bcd(day); + mon = bin2bcd(mon); + yrs = bin2bcd(yrs); + + spin_lock_irqsave(&priv->lock, flags); + save_control = ds1286_rtc_read(priv, RTC_CMD); + ds1286_rtc_write(priv, (save_control|RTC_TE), RTC_CMD); + + ds1286_rtc_write(priv, yrs, RTC_YEAR); + ds1286_rtc_write(priv, mon, RTC_MONTH); + ds1286_rtc_write(priv, day, RTC_DATE); + ds1286_rtc_write(priv, hrs, RTC_HOURS); + ds1286_rtc_write(priv, min, RTC_MINUTES); + ds1286_rtc_write(priv, sec, RTC_SECONDS); + ds1286_rtc_write(priv, 0, RTC_HUNDREDTH_SECOND); + + ds1286_rtc_write(priv, save_control, RTC_CMD); + spin_unlock_irqrestore(&priv->lock, flags); + return 0; +} + +static int ds1286_read_alarm(struct device *dev, struct rtc_wkalrm *alm) +{ + struct ds1286_priv *priv = dev_get_drvdata(dev); + unsigned char cmd; + unsigned long flags; + + /* + * Only the values that we read from the RTC are set. That + * means only tm_wday, tm_hour, tm_min. + */ + spin_lock_irqsave(&priv->lock, flags); + alm->time.tm_min = ds1286_rtc_read(priv, RTC_MINUTES_ALARM) & 0x7f; + alm->time.tm_hour = ds1286_rtc_read(priv, RTC_HOURS_ALARM) & 0x1f; + alm->time.tm_wday = ds1286_rtc_read(priv, RTC_DAY_ALARM) & 0x07; + cmd = ds1286_rtc_read(priv, RTC_CMD); + spin_unlock_irqrestore(&priv->lock, flags); + + alm->time.tm_min = bcd2bin(alm->time.tm_min); + alm->time.tm_hour = bcd2bin(alm->time.tm_hour); + alm->time.tm_sec = 0; + return 0; +} + +static int ds1286_set_alarm(struct device *dev, struct rtc_wkalrm *alm) +{ + struct ds1286_priv *priv = dev_get_drvdata(dev); + unsigned char hrs, min, sec; + + hrs = alm->time.tm_hour; + min = alm->time.tm_min; + sec = alm->time.tm_sec; + + if (hrs >= 24) + hrs = 0xff; + + if (min >= 60) + min = 0xff; + + if (sec != 0) + return -EINVAL; + + min = bin2bcd(min); + hrs = bin2bcd(hrs); + + spin_lock(&priv->lock); + ds1286_rtc_write(priv, hrs, RTC_HOURS_ALARM); + ds1286_rtc_write(priv, min, RTC_MINUTES_ALARM); + spin_unlock(&priv->lock); + + return 0; +} + +static const struct rtc_class_ops ds1286_ops = { + .ioctl = ds1286_ioctl, + .proc = ds1286_proc, + .read_time = ds1286_read_time, + .set_time = ds1286_set_time, + .read_alarm = ds1286_read_alarm, + .set_alarm = ds1286_set_alarm, +}; + +static int __devinit ds1286_probe(struct platform_device *pdev) +{ + struct rtc_device *rtc; + struct resource *res; + struct ds1286_priv *priv; + int ret = 0; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) + return -ENODEV; + priv = kzalloc(sizeof(struct ds1286_priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->size = res->end - res->start + 1; + if (!request_mem_region(res->start, priv->size, pdev->name)) { + ret = -EBUSY; + goto out; + } + priv->baseaddr = res->start; + priv->rtcregs = ioremap(priv->baseaddr, priv->size); + if (!priv->rtcregs) { + ret = -ENOMEM; + goto out; + } + spin_lock_init(&priv->lock); + rtc = rtc_device_register("ds1286", &pdev->dev, + &ds1286_ops, THIS_MODULE); + if (IS_ERR(rtc)) { + ret = PTR_ERR(rtc); + goto out; + } + priv->rtc = rtc; + platform_set_drvdata(pdev, priv); + return 0; + +out: + if (priv->rtc) + rtc_device_unregister(priv->rtc); + if (priv->rtcregs) + iounmap(priv->rtcregs); + if (priv->baseaddr) + release_mem_region(priv->baseaddr, priv->size); + kfree(priv); + return ret; +} + +static int __devexit ds1286_remove(struct platform_device *pdev) +{ + struct ds1286_priv *priv = platform_get_drvdata(pdev); + + rtc_device_unregister(priv->rtc); + iounmap(priv->rtcregs); + release_mem_region(priv->baseaddr, priv->size); + kfree(priv); + return 0; +} + +static struct platform_driver ds1286_platform_driver = { + .driver = { + .name = "rtc-ds1286", + .owner = THIS_MODULE, + }, + .probe = ds1286_probe, + .remove = __devexit_p(ds1286_remove), +}; + +static int __init ds1286_init(void) +{ + return platform_driver_register(&ds1286_platform_driver); +} + +static void __exit ds1286_exit(void) +{ + platform_driver_unregister(&ds1286_platform_driver); +} + +MODULE_AUTHOR("Thomas Bogendoerfer "); +MODULE_DESCRIPTION("DS1286 RTC driver"); +MODULE_LICENSE("GPL"); +MODULE_VERSION(DRV_VERSION); +MODULE_ALIAS("platform:rtc-ds1286"); + +module_init(ds1286_init); +module_exit(ds1286_exit); From mano@roarinelk.homelinux.net Sat Aug 9 15:14:07 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 09 Aug 2008 15:14:15 +0100 (BST) Received: from fnoeppeil48.netpark.at ([217.175.205.176]:42203 "EHLO roarinelk.homelinux.net") by ftp.linux-mips.org with ESMTP id S28583142AbYHIOOH (ORCPT ); Sat, 9 Aug 2008 15:14:07 +0100 Received: (qmail 400 invoked from network); 9 Aug 2008 16:14:03 +0200 Received: from flagship.roarinelk.net (192.168.0.197) by fnoeppeil48.netpark.at with SMTP; 9 Aug 2008 16:14:03 +0200 Date: Sat, 9 Aug 2008 16:14:02 +0200 From: Manuel Lauss To: rtc-linux@googlegroups.com, Linux-MIPS Cc: Kevin Hickey Subject: [RFC PATCH] Au1xxx on-chip counter-as-RTC driver Message-ID: <20080809161402.15e24b2e@flagship.roarinelk.net> Organization: Private X-Mailer: Claws Mail 3.5.0 (GTK+ 2.12.11; x86_64-pc-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20165 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mano@roarinelk.homelinux.net Precedence: bulk X-list: linux-mips Hello, Here's a very simple patch which implements an RTC using the TOY counter (counter0) on the Au1000 family of SoCs. It works so far on the DB1200 board; however it takes up to 5 seconds until the written value actually hits the register, so the hardware clock is always off (the minimum seems to be 3 seconds on the DB1200). I'd like to get some feedback on how to work around this "anomaly". Patch applies on top of the Au1xxx update patches posted here: http://marc.info/?l=linux-mips&m=121735077313715&w=2 and current -git. Thanks! Manuel Lauss --- From: Manuel Lauss Subject: [PATCH] RTC: Au1000 On-Chip Counter0-as-RTC driver. This simple driver uses Counter0 of the Au1xxx SoC as a Real Time Clock. Currently it only supports setting and retrieving time. Signed-off-by: Manuel Lauss --- arch/mips/au1000/common/platform.c | 8 -- arch/mips/au1000/pb1200/platform.c | 6 + drivers/rtc/Kconfig | 9 ++ drivers/rtc/Makefile | 1 + drivers/rtc/rtc-au1xxx.c | 188 ++++++++++++++++++++++++++++++++++++ 5 files changed, 204 insertions(+), 8 deletions(-) create mode 100644 drivers/rtc/rtc-au1xxx.c diff --git a/arch/mips/au1000/common/platform.c b/arch/mips/au1000/common/platform.c index 9d12e6b..f29930e 100644 --- a/arch/mips/au1000/common/platform.c +++ b/arch/mips/au1000/common/platform.c @@ -616,14 +616,6 @@ static struct attribute_group db1x_pmattr_group = { */ static int __init pm_init(void) { - /* init TOY to tick at 1Hz. No need to wait for access bits - * since there's plenty of time between here and the first - * suspend cycle. - */ - au_writel(32767, SYS_TOYTRIM); - au_writel(0, SYS_TOYWRITE); - au_sync(); - db1x_pm_last_wakesrc = au_readl(SYS_WAKESRC); au_writel(0, SYS_WAKESRC); diff --git a/arch/mips/au1000/pb1200/platform.c b/arch/mips/au1000/pb1200/platform.c index 9530329..1a5b160 100644 --- a/arch/mips/au1000/pb1200/platform.c +++ b/arch/mips/au1000/pb1200/platform.c @@ -152,7 +152,13 @@ static struct platform_device smc91c111_device = { .resource = smc91c111_resources }; +static struct platform_device rtc_device = { + .name = "rtc-au1xxx", + .id = -1, +}; + static struct platform_device *board_platform_devices[] __initdata = { + &rtc_device, &ide_device, &smc91c111_device }; diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig index 90ab738..8747a66 100644 --- a/drivers/rtc/Kconfig +++ b/drivers/rtc/Kconfig @@ -559,6 +559,15 @@ config RTC_DRV_AT91SAM9_GPBR will be used. The default of zero is normally OK to use, but on some systems other software needs to use that register. +config RTC_DRV_AU1XXX + tristate "Au1xxx TOY-as-RTC support" + depends on SOC_AU1X00 + help + This driver uses Au1000 on-chip Counter0 as a Real Time Clock. + + This driver can also be built as a module. If so, the module + will be called rtc-au1xxx. + config RTC_DRV_BFIN tristate "Blackfin On-Chip RTC" depends on BLACKFIN diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile index 18622ef..6a33a18 100644 --- a/drivers/rtc/Makefile +++ b/drivers/rtc/Makefile @@ -20,6 +20,7 @@ rtc-core-$(CONFIG_RTC_INTF_SYSFS) += rtc-sysfs.o obj-$(CONFIG_RTC_DRV_AT32AP700X)+= rtc-at32ap700x.o obj-$(CONFIG_RTC_DRV_AT91RM9200)+= rtc-at91rm9200.o obj-$(CONFIG_RTC_DRV_AT91SAM9) += rtc-at91sam9.o +obj-$(CONFIG_RTC_DRV_AU1XXX) += rtc-au1xxx.o obj-$(CONFIG_RTC_DRV_BFIN) += rtc-bfin.o obj-$(CONFIG_RTC_DRV_CMOS) += rtc-cmos.o obj-$(CONFIG_RTC_DRV_DS1216) += rtc-ds1216.o diff --git a/drivers/rtc/rtc-au1xxx.c b/drivers/rtc/rtc-au1xxx.c new file mode 100644 index 0000000..0b67832 --- /dev/null +++ b/drivers/rtc/rtc-au1xxx.c @@ -0,0 +1,188 @@ +/* + * Au1xxx On-Chip Counters Real Time Clock interface driver. + * + * Copyright (C) 2008 Manuel Lauss + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ + +/* All currently known (to me at least) Au1xxx chips have 2 counters with + * programmable dividers, fed by an external 32.768 kHz clocksource. + * Counter 0, which keeps counting during sleep/powerdown, is used here + * as a simple 1Hz counter which stores the current date as the time in + * seconds since the dawn of the UNIX epoch. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +/* 32kHz clock enabled and detected */ +#define CNTR_OK (SYS_CNTRL_E0 | SYS_CNTRL_32S) + +struct au1xtoy_rtc { + struct rtc_device *rtc_dev; + spinlock_t lock; +}; + +static int au1xtoy_rtc_read_time(struct device *dev, struct rtc_time *tm) +{ + struct platform_device *pdev = to_platform_device(dev); + struct au1xtoy_rtc *rtc = platform_get_drvdata(pdev); + unsigned long t; + + spin_lock_irq(&rtc->lock); + + t = au_readl(SYS_TOYREAD); + rtc_time_to_tm(t, tm); + + if (rtc_valid_tm(tm) < 0) { + dev_err(dev, "invalid date\n"); + rtc_time_to_tm(0, tm); + } + + spin_unlock_irq(&rtc->lock); + + return 0; +} + +static int au1xtoy_rtc_set_time(struct device *dev, struct rtc_time *tm) +{ + struct platform_device *pdev = to_platform_device(dev); + struct au1xtoy_rtc *rtc = platform_get_drvdata(pdev); + unsigned long t; + + rtc_tm_to_time(tm, &t); + + spin_lock_irq(&rtc->lock); + + au_writel(t, SYS_TOYWRITE); + au_sync(); + + /* wait until the hardware again allows writes to the TOY counter */ + while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C0S) + asm volatile ("nop"); + + spin_unlock_irq(&rtc->lock); + + return 0; +} + +static struct rtc_class_ops au1xtoy_rtc_ops = { + .read_time = au1xtoy_rtc_read_time, + .set_time = au1xtoy_rtc_set_time, +}; + +static int __devinit au1xtoy_rtc_probe(struct platform_device *pdev) +{ + struct au1xtoy_rtc *rtc; + unsigned long u, to; + int ret; + + rtc = kzalloc(sizeof(struct au1xtoy_rtc), GFP_KERNEL); + if (unlikely(!rtc)) + return -ENOMEM; + + spin_lock_init(&rtc->lock); + + /* In Firmware We Trust(TM): if the firmware has enabled the + * counters and hardware says 32kHz clock is detected, then + * we can consider the counters usable. + */ + u = au_readl(SYS_COUNTER_CNTRL); + if (!(u & CNTR_OK)) { + dev_err(&pdev->dev, "counters disabled by firmware\n"); + ret = -ENODEV; + goto out_err; + } + + ret = -ETIMEDOUT; + + /* wait until hardware gives access to TRIM register */ + to = 0x00100000; + while ((au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T0S) && to--) + asm volatile ("nop"); + + if (!to) { + /* timed out waiting for register access. Counters may + * be unusable, so bail out. + */ + dev_err(&pdev->dev, "timed out waiting for reg access\n"); + goto out_err; + } + + /* set 1Hz TOY tick rate */ + au_writel(32767, SYS_TOYTRIM); + au_sync(); + + /* wait until the hardware allows writes to the TOY counter, so + * that the first write succeeds immediately. + */ + while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C0S) + asm volatile ("nop"); + + rtc->rtc_dev = rtc_device_register("rtc-au1xxx", &pdev->dev, + &au1xtoy_rtc_ops, THIS_MODULE); + if (IS_ERR(rtc->rtc_dev)) { + ret = PTR_ERR(rtc->rtc_dev); + goto out_err; + } + + platform_set_drvdata(pdev, rtc); + + printk(KERN_INFO "Au1000 TOY-based Real Time Clock installed.\n"); + + return 0; + +out_err: + kfree(rtc); + return ret; +} + +static int __devexit au1xtoy_rtc_remove(struct platform_device *pdev) +{ + struct au1xtoy_rtc *rtc = platform_get_drvdata(pdev); + + if (likely(rtc->rtc_dev)) + rtc_device_unregister(rtc->rtc_dev); + + platform_set_drvdata(pdev, NULL); + + kfree(rtc); + + return 0; +} + +static struct platform_driver au1xtoy_rtc_platform_driver = { + .driver = { + .name = "rtc-au1xxx", + .owner = THIS_MODULE, + }, + .probe = au1xtoy_rtc_probe, + .remove = __devexit_p(au1xtoy_rtc_remove), +}; + +static int __init au1xtoy_rtc_init(void) +{ + return platform_driver_register(&au1xtoy_rtc_platform_driver); +} + +static void __exit au1xtoy_rtc_exit(void) +{ + platform_driver_unregister(&au1xtoy_rtc_platform_driver); +} + +module_init(au1xtoy_rtc_init); +module_exit(au1xtoy_rtc_exit); + +MODULE_DESCRIPTION("Au1xxx On-Chip counter RTC driver"); +MODULE_AUTHOR("Manuel Lauss"); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform:rtc-au1xxx"); -- 1.5.6.4 From glynastill@yahoo.co.uk Sat Aug 9 17:26:09 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Sat, 09 Aug 2008 17:26:20 +0100 (BST) Received: from web25805.mail.ukl.yahoo.com ([217.12.10.190]:34717 "HELO web25805.mail.ukl.yahoo.com") by ftp.linux-mips.org with SMTP id S28584559AbYHIQ0J convert rfc822-to-8bit (ORCPT ); Sat, 9 Aug 2008 17:26:09 +0100 Received: (qmail 65598 invoked by uid 60001); 9 Aug 2008 16:26:01 -0000 DomainKey-Signature: a=rsa-sha1; q=dns; c=nofws; s=s1024; d=yahoo.co.uk; h=Received:X-Mailer:Date:From:Reply-To:Subject:To:MIME-Version:Content-Type:Content-Transfer-Encoding:Message-ID; b=FbLi83cMXvdSsavLvgMzFbQ92z5vqlEGqtPX3hP/JRv23+wSGAsz8dfWE4ikfJfejAAQwBQFjBm7oBFlX0IVgYD+QCqDEvaeXvnMtwdHHJkYDIX2aMaYTzJJ2cft1/a4/m6lJnx2Ky86iiomeQ0HN8RK/l2m7/tib6HDWOoUuPc=; Received: from [87.114.137.160] by web25805.mail.ukl.yahoo.com via HTTP; Sat, 09 Aug 2008 16:26:01 GMT X-Mailer: YahooMailWebService/0.7.218 Date: Sat, 9 Aug 2008 16:26:01 +0000 (GMT) From: Glyn Astill Reply-To: glynastill@yahoo.co.uk Subject: debian binutils package To: linux-mips@linux-mips.org MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8BIT Message-ID: <715357.65421.qm@web25805.mail.ukl.yahoo.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20166 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: glynastill@yahoo.co.uk Precedence: bulk X-list: linux-mips Running debian etch on a cobalt qube, having trouble compiling postgres. It appears my issue is something to do with the as or ld commands from binutils. Switching from the latest postgres release to the latest cvs head which links differently works. The chaps on the netbsd list seem to have observed similar too. __________________________________________________________ Not happy with your email address?. Get the one you really want - millions of new email addresses available now at Yahoo! http://uk.docs.yahoo.com/ymail/new.html From rpjday@crashcourse.ca Sun Aug 10 17:26:55 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Sun, 10 Aug 2008 17:27:01 +0100 (BST) Received: from astoria.ccjclearline.com ([64.235.106.9]:54740 "EHLO astoria.ccjclearline.com") by ftp.linux-mips.org with ESMTP id S28588739AbYHJQ0z (ORCPT ); Sun, 10 Aug 2008 17:26:55 +0100 Received: from cpe00142a336e11-cm001ac318e826.cpe.net.cable.rogers.com ([72.140.150.221] helo=crashcourse.ca) by astoria.ccjclearline.com with esmtpsa (TLSv1:AES256-SHA:256) (Exim 4.69) (envelope-from ) id 1KSDkp-000715-KN for linux-mips@linux-mips.org; Sun, 10 Aug 2008 12:26:51 -0400 Date: Sun, 10 Aug 2008 12:25:06 -0400 (EDT) From: "Robert P. J. Day" X-X-Sender: rpjday@localhost.localdomain To: linux-mips@linux-mips.org Subject: update: MIPS-related unused config vars in kernel tree Message-ID: User-Agent: Alpine 1.10 (LFD 962 2008-03-14) MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII X-AntiAbuse: This header was added to track abuse, please include it with any abuse report X-AntiAbuse: Primary Hostname - astoria.ccjclearline.com X-AntiAbuse: Original Domain - linux-mips.org X-AntiAbuse: Originator/Caller UID/GID - [47 12] / [47 12] X-AntiAbuse: Sender Address Domain - crashcourse.ca X-Source: X-Source-Args: X-Source-Dir: Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20167 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: rpjday@crashcourse.ca Precedence: bulk X-list: linux-mips the output from the latest scan: ===== BLK_DEV_IDE_AU1XXX_SEQTS_PER_RQ Documentation/mips/AU1xxx_IDE.README:61: CONFIG_BLK_DEV_IDE_AU1XXX_SEQTS_PER_RQ - maximum transfer size Documentation/mips/AU1xxx_IDE.README:90:CONFIG_BLK_DEV_IDE_AU1XXX_SEQTS_PER_RQ=128 Documentation/mips/AU1xxx_IDE.README:108:CONFIG_BLK_DEV_IDE_AU1XXX_SEQTS_PER_RQ=128 drivers/ide/Kconfig:803:config BLK_DEV_IDE_AU1XXX_SEQTS_PER_RQ rday -- ======================================================================== Robert P. J. Day Linux Consulting, Training and Annoying Kernel Pedantry: Have classroom, will lecture. http://crashcourse.ca Waterloo, Ontario, CANADA ======================================================================== From anemo@mba.ocn.ne.jp Mon Aug 11 15:05:37 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 11 Aug 2008 15:05:45 +0100 (BST) Received: from mba.ocn.ne.jp ([122.1.235.107]:5077 "HELO smtp.mba.ocn.ne.jp") by ftp.linux-mips.org with SMTP id S20029867AbYHKOFh (ORCPT ); Mon, 11 Aug 2008 15:05:37 +0100 Received: from localhost (p7054-ipad312funabasi.chiba.ocn.ne.jp [123.217.225.54]) by smtp.mba.ocn.ne.jp (Postfix) with ESMTP id 03C49A9A3; Mon, 11 Aug 2008 23:05:31 +0900 (JST) Date: Mon, 11 Aug 2008 23:05:35 +0900 (JST) Message-Id: <20080811.230535.25909452.anemo@mba.ocn.ne.jp> To: linux-mips@linux-mips.org Cc: Jason Wessel , ralf@linux-mips.org Subject: [PATCH] kgdb: Do not call fixup_exception From: Atsushi Nemoto X-Fingerprint: 6ACA 1623 39BD 9A94 9B1A B746 CA77 FE94 2874 D52F X-Pgp-Public-Key: http://wwwkeys.pgp.net/pks/lookup?op=get&search=0x2874D52F X-Mailer: Mew version 5.2 on Emacs 21.4 / Mule 5.0 (SAKAKI) Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20169 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: anemo@mba.ocn.ne.jp Precedence: bulk X-list: linux-mips Content-Length: 728 Lines: 22 kgdb_mips_notify is called on IBE/DBE/FPE/BP/TRAP/RI exception. None of them need fixup. And doing fixup for a breakpoint exception will confuse gdb. Signed-off-by: Atsushi Nemoto --- This is a patch against current kernel.org git tree. diff --git a/arch/mips/kernel/kgdb.c b/arch/mips/kernel/kgdb.c index c5a8b2d..cdaa4e3 100644 --- a/arch/mips/kernel/kgdb.c +++ b/arch/mips/kernel/kgdb.c @@ -190,9 +190,6 @@ static int kgdb_mips_notify(struct notifier_block *self, unsigned long cmd, struct pt_regs *regs = args->regs; int trap = (regs->cp0_cause & 0x7c) >> 2; - if (fixup_exception(regs)) - return NOTIFY_DONE; - /* Userpace events, ignore. */ if (user_mode(regs)) return NOTIFY_DONE; From ralf@linux-mips.org Mon Aug 11 15:42:58 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Mon, 11 Aug 2008 15:43:07 +0100 (BST) Received: from ditditdahdahdah-dahditditditdit.dl5rb.org.uk ([217.169.26.26]:31707 "EHLO ditditdahdahdah-dahdahdahditdit.dl5rb.org.uk") by ftp.linux-mips.org with ESMTP id S20029352AbYHKOm6 (ORCPT ); Mon, 11 Aug 2008 15:42:58 +0100 Received: from denk.linux-mips.net (denk.linux-mips.net [127.0.0.1]) by ditditdahdahdah-dahdahdahditdit.dl5rb.org.uk (8.14.2/8.14.1) with ESMTP id m7BEgqZU029841; Mon, 11 Aug 2008 15:42:55 +0100 Received: (from ralf@localhost) by denk.linux-mips.net (8.14.2/8.14.2/Submit) id m7BEgp52029839; Mon, 11 Aug 2008 15:42:51 +0100 Date: Mon, 11 Aug 2008 15:42:51 +0100 From: Ralf Baechle To: Atsushi Nemoto Cc: linux-mips@linux-mips.org, Jason Wessel Subject: Re: [PATCH] kgdb: Do not call fixup_exception Message-ID: <20080811144251.GA29441@linux-mips.org> References: <20080811.230535.25909452.anemo@mba.ocn.ne.jp> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20080811.230535.25909452.anemo@mba.ocn.ne.jp> User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20170 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Content-Length: 249 Lines: 9 On Mon, Aug 11, 2008 at 11:05:35PM +0900, Atsushi Nemoto wrote: > kgdb_mips_notify is called on IBE/DBE/FPE/BP/TRAP/RI exception. None > of them need fixup. And doing fixup for a breakpoint exception will > confuse gdb. Thanks, applied. Ralf From dvomlehn@cisco.com Tue Aug 12 00:19:24 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 12 Aug 2008 00:19:29 +0100 (BST) Received: from sj-iport-2.cisco.com ([171.71.176.71]:28641 "EHLO sj-iport-2.cisco.com") by ftp.linux-mips.org with ESMTP id S28591036AbYHKXTY (ORCPT ); Tue, 12 Aug 2008 00:19:24 +0100 X-IronPort-AV: E=Sophos;i="4.32,192,1217808000"; d="scan'208";a="74204059" Received: from sj-dkim-4.cisco.com ([171.71.179.196]) by sj-iport-2.cisco.com with ESMTP; 11 Aug 2008 23:19:05 +0000 Received: from sj-core-3.cisco.com (sj-core-3.cisco.com [171.68.223.137]) by sj-dkim-4.cisco.com (8.12.11/8.12.11) with ESMTP id m7BNJ5XA021386; Mon, 11 Aug 2008 16:19:05 -0700 Received: from cliff.cisco.com (cliff.cisco.com [171.69.11.141]) by sj-core-3.cisco.com (8.13.8/8.13.8) with ESMTP id m7BNJ5Kq010693; Mon, 11 Aug 2008 23:19:05 GMT Received: from [127.0.0.1] ([64.101.20.200]) by cliff.cisco.com (8.6.12/8.6.5) with ESMTP id XAA00764; Mon, 11 Aug 2008 23:19:04 GMT Message-ID: <48A0C8E7.6080506@cisco.com> Date: Mon, 11 Aug 2008 16:19:03 -0700 From: David VomLehn User-Agent: Thunderbird 2.0.0.16 (Windows/20080708) MIME-Version: 1.0 To: jfraser@broadcom.com CC: Ralf Baechle , linux-mips@linux-mips.org, michael.sundius@sciatl.com Subject: Re: Anyone noticed that there are a lot of cache flushes after kunmap/kunmap_atomic is called? References: <489A5975.1000401@cisco.com> <20080808082404.GA27519@linux-mips.org> <1218206499.20791.152.camel@chaos.ne.broadcom.com> In-Reply-To: <1218206499.20791.152.camel@chaos.ne.broadcom.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; l=811; t=1218496745; x=1219360745; c=relaxed/simple; s=sjdkim4002; h=Content-Type:From:Subject:Content-Transfer-Encoding:MIME-Version; d=cisco.com; i=dvomlehn@cisco.com; z=From:=20David=20VomLehn=20 |Subject:=20Re=3A=20Anyone=20noticed=20that=20there=20are=2 0a=20lot=20of=20cache=20flushes=20after=20kunmap/kunmap_atom ic=0A=20is=20called? |Sender:=20; bh=YWJB99ODmosBVmb5EqmSa6QtO8Rq8I+sc/suC7/NWb4=; b=D538ufA7PLxROvSp4JKKuoz5Fo8EmgiYg87UBhi6711wBif+cajnzuWwRy +k3uaxVZJ6ThjWvoMKgFCvMaP0mrmBaKxzbRZFYjOLW5Ng08hGB1BkbFlKMX m/wCqdF5tL; Authentication-Results: sj-dkim-4; header.From=dvomlehn@cisco.com; dkim=pass ( sig from cisco.com/sjdkim4002 verified; ); Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20171 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: dvomlehn@cisco.com Precedence: bulk X-list: linux-mips Content-Length: 792 Lines: 21 Jon Fraser wrote: > David, > > I'm battling this now. Our mips 24k has a virtually indexed cache. > We're definitely seeing issues where the cache hasn't been flushed > for highmem pages. I thought I had this fixed, but I'm still seeing > some problems. As I understand it, you have the most difficult combination of things: o You are using high memory o You have a virtually indexed cache o You have data cache aliases Fortunately, we have only the first two of those in our system. We should probably put together a coherent set of patches for people who want high memory. So far as I can tell, the 32-bit MIPS architecture has a long way to go before it runs out of steam in the embedded world. I expect more people will need MIPS highmem support in the next few years. David From jfraser@broadcom.com Tue Aug 12 01:49:29 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 12 Aug 2008 01:49:36 +0100 (BST) Received: from mms3.broadcom.com ([216.31.210.19]:2057 "EHLO MMS3.broadcom.com") by ftp.linux-mips.org with ESMTP id S28591285AbYHLAt3 (ORCPT ); Tue, 12 Aug 2008 01:49:29 +0100 Received: from [10.11.16.99] by MMS3.broadcom.com with ESMTP (Broadcom SMTP Relay (Email Firewall v6.3.2)); Mon, 11 Aug 2008 17:49:11 -0700 X-Server-Uuid: B55A25B1-5D7D-41F8-BC53-C57E7AD3C201 Received: by mail-irva-10.broadcom.com (Postfix, from userid 47) id DC32A2B1; Mon, 11 Aug 2008 17:49:11 -0700 (PDT) Received: from mail-irva-8.broadcom.com (mail-irva-8 [10.11.18.52]) by mail-irva-10.broadcom.com (Postfix) with ESMTP id C6E4E2B0; Mon, 11 Aug 2008 17:49:11 -0700 (PDT) Received: from mail-irva-13.broadcom.com (mail-irva-13.broadcom.com [10.11.16.103]) by mail-irva-8.broadcom.com (MOS 3.7.5a-GA) with ESMTP id HBM54968; Mon, 11 Aug 2008 17:49:11 -0700 (PDT) Received: from [10.28.6.13] (lab-mhtb-013.ne.broadcom.com [10.28.6.13]) by mail-irva-13.broadcom.com (Postfix) with ESMTP id 235B774CFE; Mon, 11 Aug 2008 17:49:10 -0700 (PDT) Subject: Re: Anyone noticed that there are a lot of cache flushes after kunmap/kunmap_atomic is called? From: "Jon Fraser" Reply-to: jfraser@broadcom.com To: "David VomLehn" cc: "Ralf Baechle" , linux-mips@linux-mips.org, michael.sundius@sciatl.com In-Reply-To: <48A0C8E7.6080506@cisco.com> References: <489A5975.1000401@cisco.com> <20080808082404.GA27519@linux-mips.org> <1218206499.20791.152.camel@chaos.ne.broadcom.com> <48A0C8E7.6080506@cisco.com> Organization: Broadcom Date: Mon, 11 Aug 2008 20:49:08 -0400 Message-ID: <1218502148.20791.250.camel@chaos.ne.broadcom.com> MIME-Version: 1.0 X-Mailer: Evolution 2.12.3 (2.12.3-3.fc8) X-WSS-ID: 64BE018D4YK52586-01-01 Content-Type: text/plain Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20172 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jfraser@broadcom.com Precedence: bulk X-list: linux-mips Content-Length: 986 Lines: 33 David, I agree. It's my number one work item this week. Well, so far, anyway :-) Jon On Mon, 2008-08-11 at 16:19 -0700, David VomLehn wrote: > Jon Fraser wrote: > > David, > > > > I'm battling this now. Our mips 24k has a virtually indexed cache. > > We're definitely seeing issues where the cache hasn't been flushed > > for highmem pages. I thought I had this fixed, but I'm still seeing > > some problems. > > As I understand it, you have the most difficult combination of things: > o You are using high memory > o You have a virtually indexed cache > o You have data cache aliases > > Fortunately, we have only the first two of those in our system. We should > probably put together a coherent set of patches for people who want high memory. > So far as I can tell, the 32-bit MIPS architecture has a long way to go before it > runs out of steam in the embedded world. I expect more people will need MIPS > highmem support in the next few years. > > David > > From skuribay@ruby.dti.ne.jp Tue Aug 12 06:48:25 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 12 Aug 2008 06:48:32 +0100 (BST) Received: from smtp14.dti.ne.jp ([202.216.231.189]:25291 "EHLO smtp14.dti.ne.jp") by ftp.linux-mips.org with ESMTP id S20024455AbYHLFsZ (ORCPT ); Tue, 12 Aug 2008 06:48:25 +0100 Received: from [192.168.1.3] (PPPax964.tokyo-ip.dti.ne.jp [210.159.155.214]) by smtp14.dti.ne.jp (3.11s) with ESMTP AUTH id m7C5mGbb010822 for ; Tue, 12 Aug 2008 14:48:20 +0900 (JST) Message-ID: <48A12420.9090904@ruby.dti.ne.jp> Date: Tue, 12 Aug 2008 14:48:16 +0900 From: Shinya Kuribayashi User-Agent: Thunderbird 2.0.0.16 (X11/20080707) MIME-Version: 1.0 To: linux-mips@linux-mips.org Subject: [MIPS] Add missing GPL references of some asm headers Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20173 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: skuribay@ruby.dti.ne.jp Precedence: bulk X-list: linux-mips Content-Length: 9460 Lines: 268 Signed-off-by: Shinya Kuribayashi --- Hi list, I don't want to be a nitpicker, nor don't have the right to mention the header licenses, but I have trouble with some asm headers not having GPL reference. For example, I was going to make use of in U-Boot project, but the patch was rejected due to the lack of GPL references. I've looked closely into all files, it seems there're lots of headers without GPL reference. Basically, I'm not going to talk about all of them. Some are board-dependent, some are used as pipe- or proxy-method, etc. These headers might not be worth doing so. However, some asm headers which include core MIPS defines, useful macros, useful inline assemblers, etc. will be also useful for other projects than Linux. And it's highly appreciated if such header has proper GPL referense in it. I've created the following patch for an example. Is there any chance such changes are accepted? Any comments are appreciated. Thanks in advance, Shinya include/asm-mips/asmmacro-32.h | 4 ++++ include/asm-mips/asmmacro-64.h | 4 ++++ include/asm-mips/bugs.h | 4 ++++ include/asm-mips/cmp.h | 10 +++++++--- include/asm-mips/cpu.h | 4 ++++ include/asm-mips/dma.h | 4 ++++ include/asm-mips/highmem.h | 4 ++++ include/asm-mips/mips_mt.h | 4 ++++ include/asm-mips/mipsmtregs.h | 5 +++++ include/asm-mips/smtc.h | 9 ++++++--- include/asm-mips/smtc_ipi.h | 4 ++++ include/asm-mips/smtc_proc.h | 5 +++++ include/asm-mips/smvp.h | 10 +++++++--- include/asm-mips/thread_info.h | 7 ++++++- 14 files changed, 68 insertions(+), 10 deletions(-) diff --git a/include/asm-mips/asmmacro-32.h b/include/asm-mips/asmmacro-32.h index 5de3963..8ac6703 100644 --- a/include/asm-mips/asmmacro-32.h +++ b/include/asm-mips/asmmacro-32.h @@ -1,6 +1,10 @@ /* * asmmacro.h: Assembler macros to make things easier to read. * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) * Copyright (C) 1998, 1999, 2003 Ralf Baechle */ diff --git a/include/asm-mips/asmmacro-64.h b/include/asm-mips/asmmacro-64.h index 225feef..ab821ba 100644 --- a/include/asm-mips/asmmacro-64.h +++ b/include/asm-mips/asmmacro-64.h @@ -1,6 +1,10 @@ /* * asmmacro.h: Assembler macros to make things easier to read. * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) * Copyright (C) 1998, 1999 Ralf Baechle * Copyright (C) 1999 Silicon Graphics, Inc. diff --git a/include/asm-mips/bugs.h b/include/asm-mips/bugs.h index 9dc10df..fb33373 100644 --- a/include/asm-mips/bugs.h +++ b/include/asm-mips/bugs.h @@ -1,6 +1,10 @@ /* * This is included by init/main.c to check for architecture-dependent bugs. * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * * Copyright (C) 2007 Maciej W. Rozycki * * Needs: diff --git a/include/asm-mips/cmp.h b/include/asm-mips/cmp.h index 89a73fb..88f6861 100644 --- a/include/asm-mips/cmp.h +++ b/include/asm-mips/cmp.h @@ -1,9 +1,13 @@ -#ifndef _ASM_CMP_H -#define _ASM_CMP_H - /* * Definitions for CMP multitasking on MIPS cores + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. */ +#ifndef _ASM_CMP_H +#define _ASM_CMP_H + struct task_struct; extern void cmp_smp_setup(void); diff --git a/include/asm-mips/cpu.h b/include/asm-mips/cpu.h index 229a786..dc2db1b 100644 --- a/include/asm-mips/cpu.h +++ b/include/asm-mips/cpu.h @@ -2,6 +2,10 @@ * cpu.h: Values of the PRId register used to match up * various MIPS cpu types. * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com) * Copyright (C) 2004 Maciej W. Rozycki */ diff --git a/include/asm-mips/dma.h b/include/asm-mips/dma.h index 1353c81..864f24a 100644 --- a/include/asm-mips/dma.h +++ b/include/asm-mips/dma.h @@ -4,6 +4,10 @@ * High DMA channel support & info by Hannu Savolainen * and John Boyd, Nov. 1992. * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * * NOTE: all this is true *only* for ISA/EISA expansions on Mips boards * and can only be used for expansion cards. Onboard DMA controllers, such * as the R4030 on Jazz boards behave totally different! diff --git a/include/asm-mips/highmem.h b/include/asm-mips/highmem.h index 4374ab2..6f65131 100644 --- a/include/asm-mips/highmem.h +++ b/include/asm-mips/highmem.h @@ -1,6 +1,10 @@ /* * highmem.h: virtual kernel memory mappings for high memory * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * * Used in CONFIG_HIGHMEM systems for memory pages which * are not addressable by direct kernel virtual addresses. * diff --git a/include/asm-mips/mips_mt.h b/include/asm-mips/mips_mt.h index ac79352..d996a42 100644 --- a/include/asm-mips/mips_mt.h +++ b/include/asm-mips/mips_mt.h @@ -2,6 +2,10 @@ * Definitions and decalrations for MIPS MT support * that are common between SMTC, VSMP, and/or AP/SP * kernel models. + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. */ #ifndef __ASM_MIPS_MT_H #define __ASM_MIPS_MT_H diff --git a/include/asm-mips/mipsmtregs.h b/include/asm-mips/mipsmtregs.h index c9420aa..2e64af4 100644 --- a/include/asm-mips/mipsmtregs.h +++ b/include/asm-mips/mipsmtregs.h @@ -1,5 +1,10 @@ /* * MT regs definitions, follows on from mipsregs.h + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * * Copyright (C) 2004 - 2005 MIPS Technologies, Inc. All rights reserved. * Elizabeth Clarke et. al. * diff --git a/include/asm-mips/smtc.h b/include/asm-mips/smtc.h index 3639b28..63ad742 100644 --- a/include/asm-mips/smtc.h +++ b/include/asm-mips/smtc.h @@ -1,9 +1,12 @@ -#ifndef _ASM_SMTC_MT_H -#define _ASM_SMTC_MT_H - /* * Definitions for SMTC multitasking on MIPS MT cores + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. */ +#ifndef _ASM_SMTC_MT_H +#define _ASM_SMTC_MT_H #include diff --git a/include/asm-mips/smtc_ipi.h b/include/asm-mips/smtc_ipi.h index 8ce5175..eaf154a 100644 --- a/include/asm-mips/smtc_ipi.h +++ b/include/asm-mips/smtc_ipi.h @@ -1,5 +1,9 @@ /* * Definitions used in MIPS MT SMTC "Interprocessor Interrupt" code. + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. */ #ifndef __ASM_SMTC_IPI_H #define __ASM_SMTC_IPI_H diff --git a/include/asm-mips/smtc_proc.h b/include/asm-mips/smtc_proc.h index 25da651..9788f71 100644 --- a/include/asm-mips/smtc_proc.h +++ b/include/asm-mips/smtc_proc.h @@ -1,5 +1,10 @@ /* * Definitions for SMTC /proc entries + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * * Copyright(C) 2005 MIPS Technologies Inc. */ #ifndef __ASM_SMTC_PROC_H diff --git a/include/asm-mips/smvp.h b/include/asm-mips/smvp.h index 0d0e80a..a8ba14b 100644 --- a/include/asm-mips/smvp.h +++ b/include/asm-mips/smvp.h @@ -1,9 +1,13 @@ -#ifndef _ASM_SMVP_H -#define _ASM_SMVP_H - /* * Definitions for SMVP multitasking on MIPS MT cores + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. */ +#ifndef _ASM_SMVP_H +#define _ASM_SMVP_H + struct task_struct; extern void smvp_smp_setup(void); diff --git a/include/asm-mips/thread_info.h b/include/asm-mips/thread_info.h index bb30606..6c06478 100644 --- a/include/asm-mips/thread_info.h +++ b/include/asm-mips/thread_info.h @@ -1,4 +1,9 @@ -/* thread_info.h: MIPS low-level thread information +/* + * thread_info.h: MIPS low-level thread information + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. * * Copyright (C) 2002 David Howells (dhowells@redhat.com) * - Incorporating suggestions made by Linus Torvalds and Dave Miller From freddy@dusktilldawn.nl Tue Aug 12 09:42:27 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 12 Aug 2008 09:42:33 +0100 (BST) Received: from minnie.intcom.nl ([217.115.199.145]:65233 "EHLO minnie.intcom.nl") by ftp.linux-mips.org with ESMTP id S20028879AbYHLIm1 (ORCPT ); Tue, 12 Aug 2008 09:42:27 +0100 Received: from localhost (minnie.intcom.nl [127.0.0.1]) by minnie.intcom.nl (Postfix) with ESMTP id 52267374848; Tue, 12 Aug 2008 10:42:26 +0200 (CEST) X-Virus-Scanned: IntCom scan amavisd-new at minnie.intcom.nl Received: from minnie.intcom.nl ([127.0.0.1]) by localhost (minnie.intcom.nl [127.0.0.1]) (amavisd-new, port 10024) with LMTP id kzsmsL-ExgrH; Tue, 12 Aug 2008 10:42:25 +0200 (CEST) Received: by minnie.intcom.nl (Postfix, from userid 1000) id 457993748D8; Tue, 12 Aug 2008 10:42:25 +0200 (CEST) Date: Tue, 12 Aug 2008 10:42:25 +0200 From: Freddy Spierenburg To: linux-mips@linux-mips.org Cc: Antonino Daplas , source@embeddedalley.com Subject: Re: [PATCH] Fixes small option parsing bug in au1100fb.c. Message-ID: <20080812084225.GA5879@dusktilldawn.nl> References: <20080108113944.GG31548@dusktilldawn.nl> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="xXmbgvnjoT4axfJE" Content-Disposition: inline In-Reply-To: <20080108113944.GG31548@dusktilldawn.nl> X-User-Agent-Feature: All mail clients suck. This one just sucks less. X-GPG-Key: http://snarl.nl/~freddy/keys/freddyPublicKey.gpg User-Agent: Mutt/1.5.17+20080114 (2008-01-14) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20174 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: freddy@dusktilldawn.nl Precedence: bulk X-list: linux-mips Content-Length: 2366 Lines: 75 --xXmbgvnjoT4axfJE Content-Type: multipart/mixed; boundary="cWoXeonUoKmBZSoM" Content-Disposition: inline --cWoXeonUoKmBZSoM Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Hi, On Tue, Jan 08, 2008 at 12:39:45PM +0100, Freddy Spierenburg wrote: > I've noticed that drivers/video/au1100fb.c contains a small time > option parsing bug. In the middle of an if...else if... > construction was inserted a lonesome if on it's own. This is > causing an incorrect 'unsupported option' warning, while the > option itself is parsed successfully. >=20 > This patch makes the lonesome if part of the whole if...else > if... construction, like it should be. No longer the incorrect > warning message will be displayed. >=20 >=20 > Signed-off-by: Freddy Spierenburg The email above I wrote last january. Unfortunately 2.6.26.2 still does not feature this correction. I tested it today and the patch still applies cleanly. I myself use this patch and can confirm it works. Can anybody please apply? --=20 $ cat ~/.signature Freddy Spierenburg http://freddy.snarl.nl/ GnuPG: 0x7941D1E1=3DC948 5851 26D2 FA5C 39F1 E588 6F17 FD5D 7941 D1E1 $ # Please read http://www.ietf.org/rfc/rfc2015.txt before complain! --cWoXeonUoKmBZSoM Content-Type: text/plain; charset=us-ascii Content-Disposition: attachment; filename="au1100fb.c-patch" diff -Naur linux-2.6.23-orig/drivers/video/au1100fb.c linux-2.6.23/drivers/video/au1100fb.c --- linux-2.6.23-orig/drivers/video/au1100fb.c 2008-01-08 11:07:13.000000000 +0000 +++ linux-2.6.23/drivers/video/au1100fb.c 2008-01-08 11:13:37.000000000 +0000 @@ -707,7 +707,8 @@ print_warn("Panel %s not supported!", this_opt); } } - if (!strncmp(this_opt, "nocursor", 8)) { + /* No cursor option */ + else if (!strncmp(this_opt, "nocursor", 8)) { this_opt += 8; nocursor = 1; print_info("Cursor disabled"); --cWoXeonUoKmBZSoM-- --xXmbgvnjoT4axfJE Content-Type: application/pgp-signature; name="signature.asc" Content-Description: Digital signature Content-Disposition: inline -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.6 (GNU/Linux) iD8DBQFIoUzxbxf9XXlB0eERAiAYAJ9I30Iype909AtJnQ+Pbr3jnS4OSQCgilFg 7haSYwnpiqXJ12fCog3ycX0= =9te/ -----END PGP SIGNATURE----- --xXmbgvnjoT4axfJE-- From kevink@paralogos.com Tue Aug 12 10:56:06 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 12 Aug 2008 10:56:14 +0100 (BST) Received: from aux-209-217-49-36.oklahoma.net ([209.217.49.36]:17166 "EHLO proteus.paralogos.com") by ftp.linux-mips.org with ESMTP id S20030019AbYHLJ4G (ORCPT ); Tue, 12 Aug 2008 10:56:06 +0100 Received: from [127.0.0.1] ([217.109.65.213]) by proteus.paralogos.com (8.9.3/8.9.3) with ESMTP id FAA13209; Tue, 12 Aug 2008 05:27:17 -0500 Message-ID: <48A15E97.1070207@paralogos.com> Date: Tue, 12 Aug 2008 11:57:43 +0200 From: "Kevin D. Kissell" User-Agent: Thunderbird 2.0.0.16 (Windows/20080708) MIME-Version: 1.0 To: David VomLehn CC: "linux-mips@linux-mips.org" Subject: Re: Anyone noticed that there are a lot of cache flushes after kunmap/kunmap_atomic is called? References: <489A5975.1000401@cisco.com> In-Reply-To: <489A5975.1000401@cisco.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20175 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: kevink@paralogos.com Precedence: bulk X-list: linux-mips Content-Length: 2063 Lines: 45 I remember dealing with analgous situations in System V many many years ago. If the cache flushes are virtual, then either there must be bullet-proof protection (hardware or software) against virtual aliasing, or they must be flushed on deallocation, before the mapping is destroyed. The good news is that, provided that DMA buffer management is done correctly, one should be able to use hit-invalidate instead of hit-writeback-invalidate on the deallocated pages. That won't save that many CPU cycles, but it will save some number of memory cycles and milliwatts. Regards, Kevin K. David VomLehn wrote: > On the MIPS processor, cache flushing is done based on virtual > addresses. However, in the Linux kernel, there are a lot of places > where memory is mapped with kmap or kmap_atomic, then unmapped with > the corresponding kunmap or kunmap_atomic and only *then* is the cache > flushed. In other words, we only flush the cache after we have dropped > the mapping of memory into a virtual address. I think this is > generally wrong. > > This may really only affect those of us who have enabled high memory, > but it's pretty prevalent in kernel code. We noted this before, but > have apparently just been bitten by it. Is it just me or is there a > fairly widespread problem for processors that flush the cache using > virtual addresses? > > > > > - - - - - > Cisco - - - - - This e-mail and any > attachments may contain information which is confidential, > proprietary, privileged or otherwise protected by law. The information > is solely intended for the named addressee (or a person responsible > for delivering it to the addressee). If you are not the intended > recipient of this message, you are not authorized to read, print, > retain, copy or disseminate this message or any part of it. If you > have received this e-mail in error, please notify the sender > immediately by return e-mail and delete it from your computer. > > > From lists@nabble.com Tue Aug 12 14:46:40 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 12 Aug 2008 14:46:49 +0100 (BST) Received: from kuber.nabble.com ([216.139.236.158]:24020 "EHLO kuber.nabble.com") by ftp.linux-mips.org with ESMTP id S20031612AbYHLNqk (ORCPT ); Tue, 12 Aug 2008 14:46:40 +0100 Received: from isper.nabble.com ([192.168.236.156]) by kuber.nabble.com with esmtp (Exim 4.63) (envelope-from ) id 1KStqv-00050O-SP for linux-mips@linux-mips.org; Tue, 12 Aug 2008 06:23:57 -0700 Message-ID: <18944199.post@talk.nabble.com> Date: Tue, 12 Aug 2008 06:23:57 -0700 (PDT) From: TriKri To: linux-mips@linux-mips.org Subject: Debugging the MIPS processor using GDB MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-Nabble-From: kristoferkrus@hotmail.com Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20176 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: kristoferkrus@hotmail.com Precedence: bulk X-list: linux-mips Content-Length: 1697 Lines: 36 The questions are many, and I don't really know where to begin, but I shall make a try. I am developing software to debug a MIPS processor in an embedded system using an EJTAG probe. Currently I have software to tell the processor to perform certain instructions, and read/write from/to certain register addresses. Now, I don't really know how to continue from here; I'm trying to find out how to make GDB benefit from these functions in order to be able to debug the processor. I know that GDB needs a gdb-stub, but I don't really know what it is and what it does, or why GDB needs it. The GDB manual suggests taking a look at sparc-stub.c coming along with GDB, since it's the best organized. Not finding any main function in it, I'm having a hard time figuring out to what it does. How should this stub be implemented and how do I know what to write in the stub file I'm going to write? There is also something called gdb-hook, which I don't really know what it is either. Do I need it? Finally, there's a program called gdbserver, which comes with GDB. If I write a remote stub, do I need this program? Where should it be run? Where should my program be run? Since the stub is a c file, but lacks of a main function, how do I compile it? There are just so many unanswered questions, I don't know where to start working or where to start looking for information. I haven't used GDB before either, possibly contributing to some of the confusion; I hope I'll get this straight soon, though. /Kristofer -- View this message in context: http://www.nabble.com/Debugging-the-MIPS-processor-using-GDB-tp18944199p18944199.html Sent from the linux-mips main mailing list archive at Nabble.com. From martin.gebert@alpha-bit.de Tue Aug 12 15:14:48 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 12 Aug 2008 15:14:51 +0100 (BST) Received: from alpha-bit.de ([217.160.213.225]:53949 "EHLO p15137410.pureserver.info") by ftp.linux-mips.org with ESMTP id S20035157AbYHLOOs (ORCPT ); Tue, 12 Aug 2008 15:14:48 +0100 Received: from Porsche (DSL01.83.171.162.173.ip-pool.NEFkom.net [83.171.162.173]) by p15137410.pureserver.info (Postfix) with ESMTP id C9E0C80DA19; Tue, 12 Aug 2008 16:14:26 +0200 (CEST) X-KENId: 00004772KEN3F896519 X-KENRelayed: 00004772KEN3F896519@Porsche Received: from [192.168.0.160] by KEN (4.00.93-v070725) with SMTP ; Tue, 12 Aug 2008 16:14:27 +0200 Date: Tue, 12 Aug 2008 16:14:22 +0200 From: Martin Gebert Subject: Re: Debugging the MIPS processor using GDB To: TriKri Cc: linux-mips@linux-mips.org Message-Id: <48A19ABE.5060104@alpha-bit.de> In-Reply-To: <18944199.post@talk.nabble.com> References: <18944199.post@talk.nabble.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed X-KENRecTime: 1218550467 Content-Transfer-Encoding: 7bit User-Agent: Thunderbird 2.0.0.16 (X11/20080730) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20177 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: martin.gebert@alpha-bit.de Precedence: bulk X-list: linux-mips Content-Length: 563 Lines: 18 > Finally, there's a program called gdbserver, which comes with GDB. If I > write a remote stub, do I need this program? Where should it be run? Where > should my program be run? Since the stub is a c file, but lacks of a main > function, how do I compile it? > At least this I can answer. In short, you need to call gdbserver on your target machine in order to do remote debugging from your workstation. The first Google match for "using gdbserver" reveals this: http://www.redhat.com/docs/manuals/enterprise/RHEL-4-Manual/gdb/server.html HTH Martin From blf.ireland@gmail.com Tue Aug 12 15:37:43 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 12 Aug 2008 15:37:48 +0100 (BST) Received: from fg-out-1718.google.com ([72.14.220.157]:34834 "EHLO fg-out-1718.google.com") by ftp.linux-mips.org with ESMTP id S20030844AbYHLOhn convert rfc822-to-8bit (ORCPT ); Tue, 12 Aug 2008 15:37:43 +0100 Received: by fg-out-1718.google.com with SMTP id d23so1253756fga.32 for ; Tue, 12 Aug 2008 07:37:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:reply-to:to:subject:date :user-agent:cc:references:in-reply-to:mime-version:content-type :content-transfer-encoding:content-disposition:message-id:sender; bh=IBrseEaWfh9qTfT/eVHBroPY0NF+C4el6CDqnoU0YIk=; b=dPawph0/7QRY8JMInYAzO5K6LcAKSE0jerOOBfKv/3CvDsfkTQYtfWyrgi8fkzjRCM a1iRXVw3VxQSy/0/X7EY+pL/+GK54MOiLYfH9+M/qsozo7AMQcJ/oTeBbxYjHh8C9Ccv a95P/TBtJFS3aBujsoi9nGUITZIqoXVdLYpD0= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:reply-to:to:subject:date:user-agent:cc:references:in-reply-to :mime-version:content-type:content-transfer-encoding :content-disposition:message-id:sender; b=UTGH/QsUHPOaFbzUatXDI+MUSLFcyx28clxPNAi3xadwSP+9adbirA3LcINuD4d4US 6ZG0NbtqiByogHkW1TPh773UJK1oODWxjsAla9iU2cCFEUF66puZZL8aU9M+HMQo/n56 OIoug0RXP11j0r8458usBwFITZoeYJPRggWWs= Received: by 10.86.95.8 with SMTP id s8mr7218470fgb.6.1218551862019; Tue, 12 Aug 2008 07:37:42 -0700 (PDT) Received: from innova-card.com ( [81.252.61.1]) by mx.google.com with ESMTPS id l12sm5196442fgb.6.2008.08.12.07.37.39 (version=TLSv1/SSLv3 cipher=RC4-MD5); Tue, 12 Aug 2008 07:37:41 -0700 (PDT) From: Brian Foster Reply-To: Brian Foster To: linux-mips@linux-mips.org Subject: Re: Debugging the MIPS processor using GDB Date: Tue, 12 Aug 2008 16:37:41 +0200 User-Agent: KMail/1.9.6 (enterprise 0.20070907.709405) Cc: Martin Gebert , TriKri References: <18944199.post@talk.nabble.com> <48A19ABE.5060104@alpha-bit.de> In-Reply-To: <48A19ABE.5060104@alpha-bit.de> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8BIT Content-Disposition: inline Message-Id: <200808121637.42148.brian.foster@innova-card.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20178 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: brian.foster@innova-card.com Precedence: bulk X-list: linux-mips Content-Length: 1629 Lines: 35 On Tuesday 12 August 2008 16:14:22 Martin Gebert wrote: > > Finally, there's a program called gdbserver, which comes with GDB. If I > > write a remote stub, do I need this program? Where should it be run? Where > > should my program be run? Since the stub is a c file, but lacks of a main > > function, how do I compile it? > > At least this I can answer. In short, you need to call gdbserver on your > target machine in order to do remote debugging from your workstation. > The first Google match for "using gdbserver" reveals this: > > http://www.redhat.com/docs/manuals/enterprise/RHEL-4-Manual/gdb/server.html To the best of my knowledge, ‘gdbserver’ itself is not normally used with (E)JTAG probes; it's mostly for debugging userland code on a remote target machine whilst running ‘gdb’ itself on a local host workstation. I'm using the commercial FS² (First Silicon Systems, now owned by MIPS) EJTAG probe. The local ‘gdb’ on the workstation talks to the local FS² software on the workstation, which talks to the probe (in my case, over USB, but there is also an Ethernet model). There is no ‘gdbserver’ in this setup per se, albeit I suppose the protocol between ‘gdb’ and the FS² software (which is called something like ‘jnetserver’?) might be similar/identical (I have no idea!). cheers! -blf- -- “How many surrealists does it take to | Brian Foster change a lightbulb? Three. One calms | somewhere in south of France the warthog, and two fill the bathtub | Stop E$$o (ExxonMobil)! with brightly-coloured machine tools.” | http://www.stopesso.com From macro@linux-mips.org Tue Aug 12 17:28:01 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 12 Aug 2008 17:28:07 +0100 (BST) Received: from kirk.serum.com.pl ([213.77.9.205]:61940 "EHLO serum.com.pl") by ftp.linux-mips.org with ESMTP id S20023184AbYHLQ2B (ORCPT ); Tue, 12 Aug 2008 17:28:01 +0100 Received: from serum.com.pl (IDENT:macro@localhost [127.0.0.1]) by serum.com.pl (8.12.11/8.12.11) with ESMTP id m7CGRsRb026962; Tue, 12 Aug 2008 18:27:54 +0200 Received: from localhost (macro@localhost) by serum.com.pl (8.12.11/8.12.11/Submit) with ESMTP id m7CGRgn3026952; Tue, 12 Aug 2008 17:27:46 +0100 Date: Tue, 12 Aug 2008 17:27:42 +0100 (BST) From: "Maciej W. Rozycki" To: Brian Foster cc: linux-mips@linux-mips.org, Martin Gebert , TriKri Subject: Re: Debugging the MIPS processor using GDB In-Reply-To: <200808121637.42148.brian.foster@innova-card.com> Message-ID: References: <18944199.post@talk.nabble.com> <48A19ABE.5060104@alpha-bit.de> <200808121637.42148.brian.foster@innova-card.com> MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20179 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: macro@linux-mips.org Precedence: bulk X-list: linux-mips Content-Length: 792 Lines: 17 On Tue, 12 Aug 2008, Brian Foster wrote: > I'm using the commercial FS² (First Silicon Systems, now owned > by MIPS) EJTAG probe. The local ‘gdb’ on the workstation talks > to the local FS² software on the workstation, which talks to the > probe (in my case, over USB, but there is also an Ethernet model). > There is no ‘gdbserver’ in this setup per se, albeit I suppose > the protocol between ‘gdb’ and the FS² software (which is called > something like ‘jnetserver’?) might be similar/identical (I have > no idea!). Not really -- it uses a C API called MDI -- the spec is available from MIPS Technologies. I am happy to read somebody finds it useful. :) Debugging the Linux kernel with GDB and this piece of hardware is certainly a lot of fun. Maciej From mano@roarinelk.homelinux.net Tue Aug 12 18:42:54 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 12 Aug 2008 18:43:01 +0100 (BST) Received: from fnoeppeil48.netpark.at ([217.175.205.176]:1734 "EHLO roarinelk.homelinux.net") by ftp.linux-mips.org with ESMTP id S28592142AbYHLRmy (ORCPT ); Tue, 12 Aug 2008 18:42:54 +0100 Received: (qmail 9083 invoked from network); 12 Aug 2008 19:42:52 +0200 Received: from flagship.roarinelk.net (HELO localhost.localdomain) (192.168.0.197) by 192.168.0.1 with SMTP; 12 Aug 2008 19:42:52 +0200 From: Manuel Lauss To: Ralf Baechle Cc: Kevin Hickey , Linux-MIPS , Manuel Lauss Subject: [PATCH 00/10] Alchemy updates v5 Date: Tue, 12 Aug 2008 19:42:41 +0200 Message-Id: X-Mailer: git-send-email 1.5.6.4 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20180 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mano@roarinelk.homelinux.net Precedence: bulk X-list: linux-mips Content-Length: 3782 Lines: 90 [Ralf: Please consider this series for 2.6.27 inclusion if it is still possible to sneak them in] Hello, Here's again a new set of patches to modernize Alchemy setup and PM code. All patches have been compile-tested with db1100 and db1200 defconfigs, and have been runnning on a few custom Au1250 boards for now more than 5 weeks. I've suspended and resumed a few hundred times while stressing the system (continuous SD + CF reads while playing some wave files and compiling sources). #1 removes unused functions #2 removes the cpu_table and replaces it with simpler code (IMHO of course) #3 enables use of cp0 counter as a fallback, #4 clockevent/clocksource support using one of the 2 counters of the Au1xxx this also enables the use of the 'wait' instruction; depends on #3 #5 cleanup made possible with #4 #6 don't unconditionally include the platform.c file. Not all boards may want all the devices registered in there, and its existence makes adding platform data to certain drivers needlessly ugly. #7 and #8 fix suspend/resume. #9 adds DBDMA suspend/resume support. #10 replaces sysctl suspend interface with something better (IMO). It's not perfect but a step in the right direction. If the need for changes arises (it works fine for the demoboards) it can be done on top of this patch. All patches depend on each other, have been run-tested on db1200 and custom au1200 boards as well as compile-tested with a minimal config for db1100. Changes V4->V5: - rediffed against 2.6.27-rc2+ - again minor refinements. Changes V3->V4: - rediffed against 2.6.27-rc1 - add patch #10. Changes V2->V3: - swap patches 1 and 2 - minor refinements, no function changes. Changes V1->V2: - address Sergei's comments wrt. config[OD] handling - change TOY clocksource to RTC clocksource - add another patch (#5) Manuel Lauss (10): Alchemy: remove get/set_au1x00_lcd_clock(). Alchemy: remove cpu_table. MIPS: make cp0 counter clocksource/event usable as fallback. Alchemy: RTC counter clocksource / clockevent support. Alchemy: move calc_clock function. Alchemy: compile platform.c only when building for a demoboard. Alchemy: split core PM code from sysctl parts. Alchemy: Fix PM code for Au1200/Au1550. Alchemy: dbdma suspend/resume support. Alchemy: new demoboard userspace suspend interface. arch/mips/Kconfig | 8 + arch/mips/au1000/Kconfig | 4 +- arch/mips/au1000/common/Makefile | 4 +- arch/mips/au1000/common/clocks.c | 65 ++++-- arch/mips/au1000/common/cputable.c | 52 ---- arch/mips/au1000/common/dbdma.c | 65 +++++ arch/mips/au1000/common/irq.c | 57 +---- arch/mips/au1000/common/platform.c | 258 ++++++++++++++++++++- arch/mips/au1000/common/power.c | 421 +++++++-------------------------- arch/mips/au1000/common/setup.c | 39 +--- arch/mips/au1000/common/sleeper.S | 121 ++++++---- arch/mips/au1000/common/time.c | 305 ++++++++---------------- arch/mips/au1000/db1x00/Makefile | 1 + arch/mips/au1000/mtx-1/Makefile | 2 +- arch/mips/au1000/pb1000/Makefile | 1 + arch/mips/au1000/pb1100/Makefile | 1 + arch/mips/au1000/pb1200/Makefile | 2 +- arch/mips/au1000/pb1500/Makefile | 1 + arch/mips/au1000/pb1550/Makefile | 1 + arch/mips/au1000/xxs1500/Makefile | 1 + arch/mips/kernel/Makefile | 4 +- arch/mips/kernel/cevt-r4k.c | 2 +- arch/mips/kernel/csrc-r4k.c | 2 +- include/asm-mips/mach-au1x00/au1000.h | 64 ++++-- include/asm-mips/time.h | 24 ++- 25 files changed, 718 insertions(+), 787 deletions(-) delete mode 100644 arch/mips/au1000/common/cputable.c From mano@roarinelk.homelinux.net Tue Aug 12 18:43:18 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 12 Aug 2008 18:43:27 +0100 (BST) Received: from fnoeppeil48.netpark.at ([217.175.205.176]:11462 "EHLO roarinelk.homelinux.net") by ftp.linux-mips.org with ESMTP id S28592141AbYHLRmy (ORCPT ); Tue, 12 Aug 2008 18:42:54 +0100 Received: (qmail 9096 invoked from network); 12 Aug 2008 19:42:52 +0200 Received: from flagship.roarinelk.net (HELO localhost.localdomain) (192.168.0.197) by 192.168.0.1 with SMTP; 12 Aug 2008 19:42:52 +0200 From: Manuel Lauss To: Ralf Baechle Cc: Kevin Hickey , Linux-MIPS , Manuel Lauss Subject: [PATCH 03/10] MIPS: make cp0 counter clocksource/event usable as fallback. Date: Tue, 12 Aug 2008 19:42:44 +0200 Message-Id: X-Mailer: git-send-email 1.5.6.4 In-Reply-To: References: In-Reply-To: References: Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20181 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mano@roarinelk.homelinux.net Precedence: bulk X-list: linux-mips Content-Length: 4178 Lines: 148 The current mips clock build infrastructure lets a system only use either the MIPS cp0 counter or a SoC specific timer as a clocksource / clockevent device. This patch renames the core cp0 counter clocksource / clockevent functions from mips_* to r4k_* and updates the wrappers in asm-mips/time.h to call these renamed functions instead. Chips which can detect whether it is safe to use a chip-specific timer can now fall back on the cp0 counter if necessary and possible (e.g. au1xxx). Existing behaviour is not changed in any way. Signed-off-by: Manuel Lauss --- arch/mips/Kconfig | 8 ++++++++ arch/mips/kernel/Makefile | 4 ++-- arch/mips/kernel/cevt-r4k.c | 2 +- arch/mips/kernel/csrc-r4k.c | 2 +- include/asm-mips/time.h | 24 ++++++++++++++++-------- 5 files changed, 28 insertions(+), 12 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 4da736e..45e4c56 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -686,7 +686,11 @@ config CEVT_DS1287 config CEVT_GT641XX bool +config CEVT_R4K_LIB + bool + config CEVT_R4K + select CEVT_R4K_LIB bool config CEVT_SB1250 @@ -701,7 +705,11 @@ config CSRC_BCM1480 config CSRC_IOASIC bool +config CSRC_R4K_LIB + bool + config CSRC_R4K + select CSRC_R4K_LIB bool config CSRC_SB1250 diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile index 706f939..dff667c 100644 --- a/arch/mips/kernel/Makefile +++ b/arch/mips/kernel/Makefile @@ -9,14 +9,14 @@ obj-y += cpu-probe.o branch.o entry.o genex.o irq.o process.o \ time.o topology.o traps.o unaligned.o obj-$(CONFIG_CEVT_BCM1480) += cevt-bcm1480.o -obj-$(CONFIG_CEVT_R4K) += cevt-r4k.o +obj-$(CONFIG_CEVT_R4K_LIB) += cevt-r4k.o obj-$(CONFIG_CEVT_DS1287) += cevt-ds1287.o obj-$(CONFIG_CEVT_GT641XX) += cevt-gt641xx.o obj-$(CONFIG_CEVT_SB1250) += cevt-sb1250.o obj-$(CONFIG_CEVT_TXX9) += cevt-txx9.o obj-$(CONFIG_CSRC_BCM1480) += csrc-bcm1480.o obj-$(CONFIG_CSRC_IOASIC) += csrc-ioasic.o -obj-$(CONFIG_CSRC_R4K) += csrc-r4k.o +obj-$(CONFIG_CSRC_R4K_LIB) += csrc-r4k.o obj-$(CONFIG_CSRC_SB1250) += csrc-sb1250.o obj-$(CONFIG_SYNC_R4K) += sync-r4k.o diff --git a/arch/mips/kernel/cevt-r4k.c b/arch/mips/kernel/cevt-r4k.c index 24a2d90..70f6343 100644 --- a/arch/mips/kernel/cevt-r4k.c +++ b/arch/mips/kernel/cevt-r4k.c @@ -219,7 +219,7 @@ static int c0_compare_int_usable(void) return 1; } -int __cpuinit mips_clockevent_init(void) +int __cpuinit r4k_clockevent_init(void) { uint64_t mips_freq = mips_hpt_frequency; unsigned int cpu = smp_processor_id(); diff --git a/arch/mips/kernel/csrc-r4k.c b/arch/mips/kernel/csrc-r4k.c index 86e026f..8dc1235 100644 --- a/arch/mips/kernel/csrc-r4k.c +++ b/arch/mips/kernel/csrc-r4k.c @@ -22,7 +22,7 @@ static struct clocksource clocksource_mips = { .flags = CLOCK_SOURCE_IS_CONTINUOUS, }; -int __init init_mips_clocksource(void) +int __init init_r4k_clocksource(void) { if (!cpu_has_counter || !mips_hpt_frequency) return -ENXIO; diff --git a/include/asm-mips/time.h b/include/asm-mips/time.h index d3bd5c5..01a4c93 100644 --- a/include/asm-mips/time.h +++ b/include/asm-mips/time.h @@ -50,27 +50,35 @@ extern int (*perf_irq)(void); /* * Initialize the calling CPU's compare interrupt as clockevent device */ -#ifdef CONFIG_CEVT_R4K -extern int mips_clockevent_init(void); +#ifdef CONFIG_CEVT_R4K_LIB extern unsigned int __weak get_c0_compare_int(void); -#else +extern int r4k_clockevent_init(void); +#endif + static inline int mips_clockevent_init(void) { +#ifdef CONFIG_CEVT_R4K + return r4k_clockevent_init(); +#else return -ENXIO; -} #endif +} /* * Initialize the count register as a clocksource */ -#ifdef CONFIG_CEVT_R4K -extern int init_mips_clocksource(void); -#else +#ifdef CONFIG_CSRC_R4K_LIB +extern int init_r4k_clocksource(void); +#endif + static inline int init_mips_clocksource(void) { +#ifdef CONFIG_CSRC_R4K + return init_r4k_clocksource(void); +#else return 0; -} #endif +} extern void clocksource_set_clock(struct clocksource *cs, unsigned int clock); extern void clockevent_set_clock(struct clock_event_device *cd, -- 1.5.6.4 From mano@roarinelk.homelinux.net Tue Aug 12 18:43:44 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 12 Aug 2008 18:43:51 +0100 (BST) Received: from fnoeppeil48.netpark.at ([217.175.205.176]:1945 "EHLO roarinelk.homelinux.net") by ftp.linux-mips.org with ESMTP id S28592146AbYHLRmy (ORCPT ); Tue, 12 Aug 2008 18:42:54 +0100 Received: (qmail 9084 invoked from network); 12 Aug 2008 19:42:52 +0200 Received: from flagship.roarinelk.net (HELO localhost.localdomain) (192.168.0.197) by 192.168.0.1 with SMTP; 12 Aug 2008 19:42:52 +0200 From: Manuel Lauss To: Ralf Baechle Cc: Kevin Hickey , Linux-MIPS , Manuel Lauss Subject: [PATCH 01/10] Alchemy: remove get/set_au1x00_lcd_clock(). Date: Tue, 12 Aug 2008 19:42:42 +0200 Message-Id: <47b66e397e2bb36b5e9004591017596a29f5eb08.1218561745.git.mano@roarinelk.homelinux.net> X-Mailer: git-send-email 1.5.6.4 In-Reply-To: References: In-Reply-To: References: Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20182 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mano@roarinelk.homelinux.net Precedence: bulk X-list: linux-mips Content-Length: 2723 Lines: 83 There are no in-tree users, so remove them. Signed-off-by: Manuel Lauss --- arch/mips/au1000/common/clocks.c | 31 ------------------------------- arch/mips/au1000/common/time.c | 1 - include/asm-mips/mach-au1x00/au1000.h | 2 -- 3 files changed, 0 insertions(+), 34 deletions(-) diff --git a/arch/mips/au1000/common/clocks.c b/arch/mips/au1000/common/clocks.c index 043429d..a8170fd 100644 --- a/arch/mips/au1000/common/clocks.c +++ b/arch/mips/au1000/common/clocks.c @@ -30,7 +30,6 @@ #include static unsigned int au1x00_clock; /* Hz */ -static unsigned int lcd_clock; /* KHz */ static unsigned long uart_baud_base; /* @@ -61,33 +60,3 @@ void set_au1x00_uart_baud_base(unsigned long new_baud_base) { uart_baud_base = new_baud_base; } - -/* - * Calculate the Au1x00's LCD clock based on the current - * cpu clock and the system bus clock, and try to keep it - * below 40 MHz (the Pb1000 board can lock-up if the LCD - * clock is over 40 MHz). - */ -void set_au1x00_lcd_clock(void) -{ - unsigned int static_cfg0; - unsigned int sys_busclk = (get_au1x00_speed() / 1000) / - ((int)(au_readl(SYS_POWERCTRL) & 0x03) + 2); - - static_cfg0 = au_readl(MEM_STCFG0); - - if (static_cfg0 & (1 << 11)) - lcd_clock = sys_busclk / 5; /* note: BCLK switching fails with D5 */ - else - lcd_clock = sys_busclk / 4; - - if (lcd_clock > 50000) /* Epson MAX */ - printk(KERN_WARNING "warning: LCD clock too high (%u KHz)\n", - lcd_clock); -} - -unsigned int get_au1x00_lcd_clock(void) -{ - return lcd_clock; -} -EXPORT_SYMBOL(get_au1x00_lcd_clock); diff --git a/arch/mips/au1000/common/time.c b/arch/mips/au1000/common/time.c index 563d939..68d7142 100644 --- a/arch/mips/au1000/common/time.c +++ b/arch/mips/au1000/common/time.c @@ -224,7 +224,6 @@ void __init plat_time_init(void) printk(KERN_INFO "CPU frequency %u.%02u MHz\n", est_freq / 1000000, ((est_freq % 1000000) * 100) / 1000000); set_au1x00_speed(est_freq); - set_au1x00_lcd_clock(); /* program the LCD clock */ #ifdef CONFIG_PM /* diff --git a/include/asm-mips/mach-au1x00/au1000.h b/include/asm-mips/mach-au1x00/au1000.h index 0d302ba..8d2ced6 100644 --- a/include/asm-mips/mach-au1x00/au1000.h +++ b/include/asm-mips/mach-au1x00/au1000.h @@ -97,8 +97,6 @@ extern void set_au1x00_speed(unsigned int new_freq); extern unsigned int get_au1x00_speed(void); extern void set_au1x00_uart_baud_base(unsigned long new_baud_base); extern unsigned long get_au1x00_uart_baud_base(void); -extern void set_au1x00_lcd_clock(void); -extern unsigned int get_au1x00_lcd_clock(void); /* * Every board describes its IRQ mapping with this table. -- 1.5.6.4 From mano@roarinelk.homelinux.net Tue Aug 12 18:44:07 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 12 Aug 2008 18:44:13 +0100 (BST) Received: from fnoeppeil48.netpark.at ([217.175.205.176]:12231 "EHLO roarinelk.homelinux.net") by ftp.linux-mips.org with ESMTP id S28592147AbYHLRmy (ORCPT ); Tue, 12 Aug 2008 18:42:54 +0100 Received: (qmail 9102 invoked from network); 12 Aug 2008 19:42:52 +0200 Received: from flagship.roarinelk.net (HELO localhost.localdomain) (192.168.0.197) by 192.168.0.1 with SMTP; 12 Aug 2008 19:42:52 +0200 From: Manuel Lauss To: Ralf Baechle Cc: Kevin Hickey , Linux-MIPS , Manuel Lauss Subject: [PATCH 04/10] Alchemy: RTC counter clocksource / clockevent support. Date: Tue, 12 Aug 2008 19:42:45 +0200 Message-Id: X-Mailer: git-send-email 1.5.6.4 In-Reply-To: References: In-Reply-To: References: Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20183 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mano@roarinelk.homelinux.net Precedence: bulk X-list: linux-mips Content-Length: 12758 Lines: 432 Add support for the 32 kHz counter1 (RTC) as clocksource / clockevent device. As a nice side effect, this also enables use of the 'wait' instruction for runtime idle power savings. If the counters aren't enabled/working properly, fall back on the cp0 counter clock code. Signed-off-by: Manuel Lauss --- arch/mips/au1000/Kconfig | 4 +- arch/mips/au1000/common/power.c | 16 ++- arch/mips/au1000/common/setup.c | 6 - arch/mips/au1000/common/time.c | 282 ++++++++++++++++----------------------- 4 files changed, 132 insertions(+), 176 deletions(-) diff --git a/arch/mips/au1000/Kconfig b/arch/mips/au1000/Kconfig index e4a057d..18ccaae 100644 --- a/arch/mips/au1000/Kconfig +++ b/arch/mips/au1000/Kconfig @@ -128,8 +128,8 @@ config SOC_AU1200 config SOC_AU1X00 bool select 64BIT_PHYS_ADDR - select CEVT_R4K - select CSRC_R4K + select CEVT_R4K_LIB + select CSRC_R4K_LIB select IRQ_CPU select SYS_HAS_CPU_MIPS32_R1 select SYS_SUPPORTS_32BIT_KERNEL diff --git a/arch/mips/au1000/common/power.c b/arch/mips/au1000/common/power.c index bd854a6..7812ebf 100644 --- a/arch/mips/au1000/common/power.c +++ b/arch/mips/au1000/common/power.c @@ -86,7 +86,11 @@ static unsigned int sleep_static_memctlr[4][3]; #define SLEEP_TEST_TIMEOUT 1 #ifdef SLEEP_TEST_TIMEOUT static int sleep_ticks; -void wakeup_counter0_set(int ticks); +static void wakeup_counter0_set(int ticks) +{ + au_writel(au_readl(SYS_TOYREAD) + ticks, SYS_TOYMATCH2); + au_sync(); +} #endif static void save_core_regs(void) @@ -184,7 +188,6 @@ static void restore_core_regs(void) } restore_au1xxx_intctl(); - wakeup_counter0_adjust(); } unsigned long suspend_mode; @@ -409,6 +412,15 @@ static struct ctl_table pm_dir_table[] = { */ static int __init pm_init(void) { + /* init TOY to tick at 1Hz. No need to wait for access bits + * since there's plenty of time between here and the first + * suspend cycle. + */ + if (au_readl(SYS_TOYTRIM) != 32767) { + au_writel(32767, SYS_TOYTRIM); + au_sync(); + } + register_sysctl_table(pm_dir_table); return 0; } diff --git a/arch/mips/au1000/common/setup.c b/arch/mips/au1000/common/setup.c index 8f06440..b6242c6 100644 --- a/arch/mips/au1000/common/setup.c +++ b/arch/mips/au1000/common/setup.c @@ -89,12 +89,6 @@ void __init plat_mem_setup(void) ioport_resource.end = IOPORT_RESOURCE_END; iomem_resource.start = IOMEM_RESOURCE_START; iomem_resource.end = IOMEM_RESOURCE_END; - - while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_E0S); - au_writel(SYS_CNTRL_E0 | SYS_CNTRL_EN0, SYS_COUNTER_CNTRL); - au_sync(); - while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T0S); - au_writel(0, SYS_TOYTRIM); } #if defined(CONFIG_64BIT_PHYS_ADDR) diff --git a/arch/mips/au1000/common/time.c b/arch/mips/au1000/common/time.c index 1518570..fe859c1 100644 --- a/arch/mips/au1000/common/time.c +++ b/arch/mips/au1000/common/time.c @@ -23,131 +23,32 @@ * * ######################################################################## * - * Setting up the clock on the MIPS boards. + * Clocksource/event using the Au1000 counter1. + * Compared to the C0 timer, the Au1000 counters are a very lousy clock- + * source and hrtimers are definitely unusable with them; but they + * enable the use of the 'wait' instructions for some power-savings + * during idle times. Counter1 is used because unlike counter 0 (TOY) + * it doesn't continue counting during sleep/hibernate, which is perfectly + * acceptable. * - * We provide the clock interrupt processing and the timer offset compute - * functions. If CONFIG_PM is selected, we also ensure the 32KHz timer is - * available. -- Dan + * CP0 counter clocksource will be used if no 32kHz source is available. */ -#include -#include +#include +#include +#include #include -#include #include #include -static int no_au1xxx_32khz; -extern int allow_au1k_wait; /* default off for CP0 Counter */ +/* 32kHz clock enabled and detected */ +#define CNTR_OK (SYS_CNTRL_E0 | SYS_CNTRL_32S) -#ifdef CONFIG_PM -#if HZ < 100 || HZ > 1000 -#error "unsupported HZ value! Must be in [100,1000]" -#endif -#define MATCH20_INC (328 * 100 / HZ) /* magic number 328 is for HZ=100... */ -static unsigned long last_pc0, last_match20; -#endif +extern int allow_au1k_wait; /* default off for CP0 Counter */ static DEFINE_SPINLOCK(time_lock); -unsigned long wtimer; - -#ifdef CONFIG_PM -static irqreturn_t counter0_irq(int irq, void *dev_id) -{ - unsigned long pc0; - int time_elapsed; - static int jiffie_drift; - - if (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M20) { - /* should never happen! */ - printk(KERN_WARNING "counter 0 w status error\n"); - return IRQ_NONE; - } - - pc0 = au_readl(SYS_TOYREAD); - if (pc0 < last_match20) - /* counter overflowed */ - time_elapsed = (0xffffffff - last_match20) + pc0; - else - time_elapsed = pc0 - last_match20; - - while (time_elapsed > 0) { - do_timer(1); -#ifndef CONFIG_SMP - update_process_times(user_mode(get_irq_regs())); -#endif - time_elapsed -= MATCH20_INC; - last_match20 += MATCH20_INC; - jiffie_drift++; - } - - last_pc0 = pc0; - au_writel(last_match20 + MATCH20_INC, SYS_TOYMATCH2); - au_sync(); - - /* - * Our counter ticks at 10.009765625 ms/tick, we we're running - * almost 10 uS too slow per tick. - */ - - if (jiffie_drift >= 999) { - jiffie_drift -= 999; - do_timer(1); /* increment jiffies by one */ -#ifndef CONFIG_SMP - update_process_times(user_mode(get_irq_regs())); -#endif - } - - return IRQ_HANDLED; -} - -struct irqaction counter0_action = { - .handler = counter0_irq, - .flags = IRQF_DISABLED, - .name = "alchemy-toy", - .dev_id = NULL, -}; - -/* When we wakeup from sleep, we have to "catch up" on all of the - * timer ticks we have missed. - */ -void wakeup_counter0_adjust(void) -{ - unsigned long pc0; - int time_elapsed; - - pc0 = au_readl(SYS_TOYREAD); - if (pc0 < last_match20) - /* counter overflowed */ - time_elapsed = (0xffffffff - last_match20) + pc0; - else - time_elapsed = pc0 - last_match20; - - while (time_elapsed > 0) { - time_elapsed -= MATCH20_INC; - last_match20 += MATCH20_INC; - } - - last_pc0 = pc0; - au_writel(last_match20 + MATCH20_INC, SYS_TOYMATCH2); - au_sync(); - -} - -/* This is just for debugging to set the timer for a sleep delay. */ -void wakeup_counter0_set(int ticks) -{ - unsigned long pc0; - - pc0 = au_readl(SYS_TOYREAD); - last_pc0 = pc0; - au_writel(last_match20 + (MATCH20_INC * ticks), SYS_TOYMATCH2); - au_sync(); -} -#endif - /* * I haven't found anyone that doesn't use a 12 MHz source clock, * but just in case..... @@ -162,37 +63,15 @@ void wakeup_counter0_set(int ticks) * this advertised speed will introduce error and sometimes not work * properly. This function is futher convoluted to still allow configurations * to do that in case they have really, really old silicon with a - * write-only PLL register, that we need the 32 KHz when power management - * "wait" is enabled, and we need to detect if the 32 KHz isn't present - * but requested......got it? :-) -- Dan + * write-only PLL register. -- Dan */ unsigned long calc_clock(void) { unsigned long cpu_speed; unsigned long flags; - unsigned long counter; spin_lock_irqsave(&time_lock, flags); - /* Power management cares if we don't have a 32 KHz counter. */ - no_au1xxx_32khz = 0; - counter = au_readl(SYS_COUNTER_CNTRL); - if (counter & SYS_CNTRL_E0) { - int trim_divide = 16; - - au_writel(counter | SYS_CNTRL_EN1, SYS_COUNTER_CNTRL); - - while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T1S); - /* RTC now ticks at 32.768/16 kHz */ - au_writel(trim_divide - 1, SYS_RTCTRIM); - while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T1S); - - while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S); - au_writel(0, SYS_TOYWRITE); - while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S); - } else - no_au1xxx_32khz = 1; - /* * On early Au1000, sys_cpupll was write-only. Since these * silicon versions of Au1000 are not sold by AMD, we don't bend @@ -215,8 +94,60 @@ unsigned long calc_clock(void) return cpu_speed; } +static cycle_t au1x_counter1_read(void) +{ + return au_readl(SYS_RTCREAD); +} + +static struct clocksource au1x_counter1_clocksource = { + .name = "au1000-counter1", + .read = au1x_counter1_read, + .mask = CLOCKSOURCE_MASK(32), + .flags = CLOCK_SOURCE_IS_CONTINUOUS, + .rating = 100, +}; + +static int au1x_rtcmatch2_set_next_event(unsigned long delta, + struct clock_event_device *cd) +{ + au_writel(au_readl(SYS_RTCREAD) + delta, SYS_RTCMATCH2); + au_sync(); + return 0; +} + +static void au1x_rtcmatch2_set_mode(enum clock_event_mode mode, + struct clock_event_device *cd) +{ +} + +static irqreturn_t au1x_rtcmatch2_irq(int irq, void *dev_id) +{ + struct clock_event_device *cd = dev_id; + cd->event_handler(cd); + return IRQ_HANDLED; +} + +static struct clock_event_device au1x_rtcmatch2_clockdev = { + .name = "rtcmatch2", + .features = CLOCK_EVT_FEAT_ONESHOT, + .rating = 100, + .irq = AU1000_RTC_MATCH2_INT, + .set_next_event = au1x_rtcmatch2_set_next_event, + .set_mode = au1x_rtcmatch2_set_mode, + .cpumask = CPU_MASK_ALL, +}; + +static struct irqaction au1x_rtcmatch2_irqaction = { + .handler = au1x_rtcmatch2_irq, + .flags = IRQF_DISABLED, + .name = "rtcmatch2", + .dev_id = &au1x_rtcmatch2_clockdev, +}; + void __init plat_time_init(void) { + struct clock_event_device *cd = &au1x_rtcmatch2_clockdev; + unsigned long t; unsigned int est_freq = calc_clock(); est_freq += 5000; /* round */ @@ -225,41 +156,60 @@ void __init plat_time_init(void) est_freq / 1000000, ((est_freq % 1000000) * 100) / 1000000); set_au1x00_speed(est_freq); -#ifdef CONFIG_PM - /* - * setup counter 0, since it keeps ticking after a - * 'wait' instruction has been executed. The CP0 timer and - * counter 1 do NOT continue running after 'wait' - * - * It's too early to call request_irq() here, so we handle - * counter 0 interrupt as a special irq and it doesn't show - * up under /proc/interrupts. - * - * Check to ensure we really have a 32 KHz oscillator before - * we do this. + /* Check if firmware (YAMON, ...) has enabled 32kHz and clock + * has been detected. If so install the rtcmatch2 clocksource, + * otherwise don't bother. Note that both bits being set is by + * no means a definite guarantee that the counters actually work + * (the 32S bit seems to be stuck set to 1 once a single clock- + * edge is detected, hence the timeouts). */ - if (no_au1xxx_32khz) - printk(KERN_WARNING "WARNING: no 32KHz clock found.\n"); - else { - while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C0S); - au_writel(0, SYS_TOYWRITE); - while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C0S); - - au_writel(au_readl(SYS_WAKEMSK) | (1 << 8), SYS_WAKEMSK); - au_writel(~0, SYS_WAKESRC); + if (CNTR_OK == (au_readl(SYS_COUNTER_CNTRL) & CNTR_OK)) { + /* + * setup counter 1 (RTC) to tick at full speed + */ + t = 0xffffff; + while ((au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T1S) && t--) + asm volatile ("nop"); + if (!t) + goto cntr_err; + + au_writel(0, SYS_RTCTRIM); /* 32.768 kHz */ au_sync(); - while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M20); - /* Setup match20 to interrupt once every HZ */ - last_pc0 = last_match20 = au_readl(SYS_TOYREAD); - au_writel(last_match20 + MATCH20_INC, SYS_TOYMATCH2); + t = 0xffffff; + while ((au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S) && t--) + asm volatile ("nop"); + if (!t) + goto cntr_err; + au_writel(0, SYS_RTCWRITE); au_sync(); - while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M20); - setup_irq(AU1000_TOY_MATCH2_INT, &counter0_action); - /* We can use the real 'wait' instruction. */ + t = 0xffffff; + while ((au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S) && t--) + asm volatile ("nop"); + if (!t) + goto cntr_err; + + /* register counter1 clocksource and event device */ + cd->mult = div_sc(32768, NSEC_PER_SEC, 32); + cd->shift = 32; + cd->max_delta_ns = clockevent_delta2ns(0x7fffffff, cd); + cd->min_delta_ns = clockevent_delta2ns(0x140, cd); + clockevents_register_device(cd); + setup_irq(AU1000_RTC_MATCH2_INT, &au1x_rtcmatch2_irqaction); + + clocksource_set_clock(&au1x_counter1_clocksource, 32768); + clocksource_register(&au1x_counter1_clocksource); + + printk(KERN_INFO "Au1x RTCMATCH2 clocksource installed\n"); + + /* can now use 'wait' */ allow_au1k_wait = 1; + } else { +cntr_err: + /* counters unusable, use CP0 counter */ + r4k_clockevent_init(); + init_r4k_clocksource(); + allow_au1k_wait = 0; } - -#endif } -- 1.5.6.4 From mano@roarinelk.homelinux.net Tue Aug 12 18:44:30 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 12 Aug 2008 18:44:38 +0100 (BST) Received: from fnoeppeil48.netpark.at ([217.175.205.176]:22965 "EHLO roarinelk.homelinux.net") by ftp.linux-mips.org with ESMTP id S28592148AbYHLRmy (ORCPT ); Tue, 12 Aug 2008 18:42:54 +0100 Received: (qmail 9090 invoked from network); 12 Aug 2008 19:42:52 +0200 Received: from flagship.roarinelk.net (HELO localhost.localdomain) (192.168.0.197) by 192.168.0.1 with SMTP; 12 Aug 2008 19:42:52 +0200 From: Manuel Lauss To: Ralf Baechle Cc: Kevin Hickey , Linux-MIPS , Manuel Lauss Subject: [PATCH 02/10] Alchemy: remove cpu_table. Date: Tue, 12 Aug 2008 19:42:43 +0200 Message-Id: <4a70afabbc14950dfcb583fb247afa4dad1273fa.1218561745.git.mano@roarinelk.homelinux.net> X-Mailer: git-send-email 1.5.6.4 In-Reply-To: References: In-Reply-To: References: Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20184 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mano@roarinelk.homelinux.net Precedence: bulk X-list: linux-mips Content-Length: 7604 Lines: 233 Remove the cpu_table: - move detection of whether c0_config[OD] is read-only and should be set to fix various chip errata to au1000 headers. - move detection of write-only sys_cpupll to au1000 headers. - remove the BCLK switching code: Activation of this features should be left to the boards using the chips since it also affects external devices tied to BCLK, and only the board designers know whether it is safe to enable. Signed-off-by: Manuel Lauss --- arch/mips/au1000/common/Makefile | 2 +- arch/mips/au1000/common/cputable.c | 52 ----------------------------- arch/mips/au1000/common/setup.c | 26 +-------------- arch/mips/au1000/common/time.c | 4 +- include/asm-mips/mach-au1x00/au1000.h | 58 +++++++++++++++++++++----------- 5 files changed, 42 insertions(+), 100 deletions(-) delete mode 100644 arch/mips/au1000/common/cputable.c diff --git a/arch/mips/au1000/common/Makefile b/arch/mips/au1000/common/Makefile index df48fd6..27bf73d 100644 --- a/arch/mips/au1000/common/Makefile +++ b/arch/mips/au1000/common/Makefile @@ -7,7 +7,7 @@ obj-y += prom.o irq.o puts.o time.o reset.o \ au1xxx_irqmap.o clocks.o platform.o power.o setup.o \ - sleeper.o cputable.o dma.o dbdma.o gpio.o + sleeper.o dma.o dbdma.o gpio.o obj-$(CONFIG_PCI) += pci.o diff --git a/arch/mips/au1000/common/cputable.c b/arch/mips/au1000/common/cputable.c deleted file mode 100644 index ba6430b..0000000 --- a/arch/mips/au1000/common/cputable.c +++ /dev/null @@ -1,52 +0,0 @@ -/* - * arch/mips/au1000/common/cputable.c - * - * Copyright (C) 2004 Dan Malek (dan@embeddededge.com) - * Copied from PowerPC and updated for Alchemy Au1xxx processors. - * - * Copyright (C) 2001 Ben. Herrenschmidt (benh@kernel.crashing.org) - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * as published by the Free Software Foundation; either version - * 2 of the License, or (at your option) any later version. - */ - -#include - -struct cpu_spec *cur_cpu_spec[NR_CPUS]; - -/* With some thought, we can probably use the mask to reduce the - * size of the table. - */ -struct cpu_spec cpu_specs[] = { - { 0xffffffff, 0x00030100, "Au1000 DA", 1, 0, 1 }, - { 0xffffffff, 0x00030201, "Au1000 HA", 1, 0, 1 }, - { 0xffffffff, 0x00030202, "Au1000 HB", 1, 0, 1 }, - { 0xffffffff, 0x00030203, "Au1000 HC", 1, 1, 0 }, - { 0xffffffff, 0x00030204, "Au1000 HD", 1, 1, 0 }, - { 0xffffffff, 0x01030200, "Au1500 AB", 1, 1, 0 }, - { 0xffffffff, 0x01030201, "Au1500 AC", 0, 1, 0 }, - { 0xffffffff, 0x01030202, "Au1500 AD", 0, 1, 0 }, - { 0xffffffff, 0x02030200, "Au1100 AB", 1, 1, 0 }, - { 0xffffffff, 0x02030201, "Au1100 BA", 1, 1, 0 }, - { 0xffffffff, 0x02030202, "Au1100 BC", 1, 1, 0 }, - { 0xffffffff, 0x02030203, "Au1100 BD", 0, 1, 0 }, - { 0xffffffff, 0x02030204, "Au1100 BE", 0, 1, 0 }, - { 0xffffffff, 0x03030200, "Au1550 AA", 0, 1, 0 }, - { 0xffffffff, 0x04030200, "Au1200 AB", 0, 0, 0 }, - { 0xffffffff, 0x04030201, "Au1200 AC", 1, 0, 0 }, - { 0x00000000, 0x00000000, "Unknown Au1xxx", 1, 0, 0 } -}; - -void set_cpuspec(void) -{ - struct cpu_spec *sp; - u32 prid; - - prid = read_c0_prid(); - sp = cpu_specs; - while ((prid & sp->prid_mask) != sp->prid_value) - sp++; - cur_cpu_spec[0] = sp; -} diff --git a/arch/mips/au1000/common/setup.c b/arch/mips/au1000/common/setup.c index 1ac6b06..8f06440 100644 --- a/arch/mips/au1000/common/setup.c +++ b/arch/mips/au1000/common/setup.c @@ -41,38 +41,14 @@ extern void __init board_setup(void); extern void au1000_restart(char *); extern void au1000_halt(void); extern void au1000_power_off(void); -extern void set_cpuspec(void); void __init plat_mem_setup(void) { - struct cpu_spec *sp; char *argptr; - unsigned long prid, cpufreq, bclk; - - set_cpuspec(); - sp = cur_cpu_spec[0]; board_setup(); /* board specific setup */ - prid = read_c0_prid(); - if (sp->cpu_pll_wo) -#ifdef CONFIG_SOC_AU1000_FREQUENCY - cpufreq = CONFIG_SOC_AU1000_FREQUENCY / 1000000; -#else - cpufreq = 396; -#endif - else - cpufreq = (au_readl(SYS_CPUPLL) & 0x3F) * 12; - printk(KERN_INFO "(PRID %08lx) @ %ld MHz\n", prid, cpufreq); - - if (sp->cpu_bclk) { - /* Enable BCLK switching */ - bclk = au_readl(SYS_POWERCTRL); - au_writel(bclk | 0x60, SYS_POWERCTRL); - printk(KERN_INFO "BCLK switching enabled!\n"); - } - - if (sp->cpu_od) + if (au1xxx_cpu_needs_config_od()) /* Various early Au1xx0 errata corrected by this */ set_c0_config(1 << 19); /* Set Config[OD] */ else diff --git a/arch/mips/au1000/common/time.c b/arch/mips/au1000/common/time.c index 68d7142..1518570 100644 --- a/arch/mips/au1000/common/time.c +++ b/arch/mips/au1000/common/time.c @@ -198,7 +198,7 @@ unsigned long calc_clock(void) * silicon versions of Au1000 are not sold by AMD, we don't bend * over backwards trying to determine the frequency. */ - if (cur_cpu_spec[0]->cpu_pll_wo) + if (au1xxx_cpu_has_pll_wo()) #ifdef CONFIG_SOC_AU1000_FREQUENCY cpu_speed = CONFIG_SOC_AU1000_FREQUENCY; #else @@ -221,7 +221,7 @@ void __init plat_time_init(void) est_freq += 5000; /* round */ est_freq -= est_freq%10000; - printk(KERN_INFO "CPU frequency %u.%02u MHz\n", + printk(KERN_INFO "(PRId %08x) @ %u.%02u MHz\n", read_c0_prid(), est_freq / 1000000, ((est_freq % 1000000) * 100) / 1000000); set_au1x00_speed(est_freq); diff --git a/include/asm-mips/mach-au1x00/au1000.h b/include/asm-mips/mach-au1x00/au1000.h index 8d2ced6..7245960 100644 --- a/include/asm-mips/mach-au1x00/au1000.h +++ b/include/asm-mips/mach-au1x00/au1000.h @@ -91,6 +91,44 @@ static inline u32 au_readl(unsigned long reg) return *(volatile u32 *)reg; } +/* Early Au1000 have a write-only SYS_CPUPLL register. */ +static inline int au1xxx_cpu_has_pll_wo(void) +{ + switch (read_c0_prid()) { + case 0x00030100: /* Au1000 DA */ + case 0x00030201: /* Au1000 HA */ + case 0x00030202: /* Au1000 HB */ + return 1; + } + return 0; +} + +/* does CPU need CONFIG[OD] set to fix tons of errata? */ +static inline int au1xxx_cpu_needs_config_od(void) +{ + /* + * c0_config.od (bit 19) was write only (and read as 0) on the + * early revisions of Alchemy SOCs. It disables the bus trans- + * action overlapping and needs to be set to fix various errata. + */ + switch (read_c0_prid()) { + case 0x00030100: /* Au1000 DA */ + case 0x00030201: /* Au1000 HA */ + case 0x00030202: /* Au1000 HB */ + case 0x01030200: /* Au1500 AB */ + /* + * Au1100/Au1200 errata actually keep silence about this bit, + * so we set it just in case for those revisions that require + * it to be set according to the (now gone) cpu_table. + */ + case 0x02030200: /* Au1100 AB */ + case 0x02030201: /* Au1100 BA */ + case 0x02030202: /* Au1100 BC */ + case 0x04030201: /* Au1200 AC */ + return 1; + } + return 0; +} /* arch/mips/au1000/common/clocks.c */ extern void set_au1x00_speed(unsigned int new_freq); @@ -1747,24 +1785,4 @@ static AU1X00_SYS * const sys = (AU1X00_SYS *)SYS_BASE; #endif -/* - * Processor information based on PRID. - * Copied from PowerPC. - */ -#ifndef _LANGUAGE_ASSEMBLY -struct cpu_spec { - /* CPU is matched via (PRID & prid_mask) == prid_value */ - unsigned int prid_mask; - unsigned int prid_value; - - char *cpu_name; - unsigned char cpu_od; /* Set Config[OD] */ - unsigned char cpu_bclk; /* Enable BCLK switching */ - unsigned char cpu_pll_wo; /* sys_cpupll reg. write-only */ -}; - -extern struct cpu_spec cpu_specs[]; -extern struct cpu_spec *cur_cpu_spec[]; -#endif - #endif -- 1.5.6.4 From mano@roarinelk.homelinux.net Tue Aug 12 18:44:54 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 12 Aug 2008 18:45:02 +0100 (BST) Received: from fnoeppeil48.netpark.at ([217.175.205.176]:17565 "EHLO roarinelk.homelinux.net") by ftp.linux-mips.org with ESMTP id S28591387AbYHLRmz (ORCPT ); Tue, 12 Aug 2008 18:42:55 +0100 Received: (qmail 9114 invoked from network); 12 Aug 2008 19:42:53 +0200 Received: from flagship.roarinelk.net (HELO localhost.localdomain) (192.168.0.197) by 192.168.0.1 with SMTP; 12 Aug 2008 19:42:53 +0200 From: Manuel Lauss To: Ralf Baechle Cc: Kevin Hickey , Linux-MIPS , Manuel Lauss Subject: [PATCH 06/10] Alchemy: compile platform.c only when building for a demoboard. Date: Tue, 12 Aug 2008 19:42:47 +0200 Message-Id: <951b44bafad51280397ccb3bb6d855b9b7ffbf94.1218561745.git.mano@roarinelk.homelinux.net> X-Mailer: git-send-email 1.5.6.4 In-Reply-To: References: In-Reply-To: References: Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20185 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mano@roarinelk.homelinux.net Precedence: bulk X-list: linux-mips Content-Length: 4689 Lines: 140 The platform.c registers devices not all boards might need/want, and it makes adding platform data to drivers needlessly ugly and complicated. Most (all?) in-kernel users of Au1xxx are demoboards, and the file in question somewhat reflects that. Remove the platform.c from the common Alchemy Makefile and add it to the Makefiles of the boards. Existing behavior of all in-kernel boards is not changed in any way. Signed-off-by: Manuel Lauss --- arch/mips/au1000/common/Makefile | 2 +- arch/mips/au1000/common/platform.c | 7 ++++++- arch/mips/au1000/db1x00/Makefile | 1 + arch/mips/au1000/mtx-1/Makefile | 2 +- arch/mips/au1000/pb1000/Makefile | 1 + arch/mips/au1000/pb1100/Makefile | 1 + arch/mips/au1000/pb1200/Makefile | 2 +- arch/mips/au1000/pb1500/Makefile | 1 + arch/mips/au1000/pb1550/Makefile | 1 + arch/mips/au1000/xxs1500/Makefile | 1 + 10 files changed, 15 insertions(+), 4 deletions(-) diff --git a/arch/mips/au1000/common/Makefile b/arch/mips/au1000/common/Makefile index 27bf73d..7265109 100644 --- a/arch/mips/au1000/common/Makefile +++ b/arch/mips/au1000/common/Makefile @@ -6,7 +6,7 @@ # obj-y += prom.o irq.o puts.o time.o reset.o \ - au1xxx_irqmap.o clocks.o platform.o power.o setup.o \ + au1xxx_irqmap.o clocks.o power.o setup.o \ sleeper.o dma.o dbdma.o gpio.o obj-$(CONFIG_PCI) += pci.o diff --git a/arch/mips/au1000/common/platform.c b/arch/mips/au1000/common/platform.c index dc8a67e..66d6770 100644 --- a/arch/mips/au1000/common/platform.c +++ b/arch/mips/au1000/common/platform.c @@ -1,5 +1,5 @@ /* - * Platform device support for Au1x00 SoCs. + * Common device support for Au1x00 demoboards. * * Copyright 2004, Matt Porter * @@ -9,6 +9,11 @@ * This file is licensed under the terms of the GNU General Public * License version 2. This program is licensed "as is" without any * warranty of any kind, whether express or implied. + * + * This file is intended to be included by all db1xxx/pb1xxx demoboards, + * and is currently used by all the in-tree ones. If your system does + * not want/need all the devices registered in here (like mine) then + * simply don't include it in your Makefile ;-) */ #include diff --git a/arch/mips/au1000/db1x00/Makefile b/arch/mips/au1000/db1x00/Makefile index 274db3b..3bfec10 100644 --- a/arch/mips/au1000/db1x00/Makefile +++ b/arch/mips/au1000/db1x00/Makefile @@ -6,3 +6,4 @@ # lib-y := init.o board_setup.o irqmap.o +obj-y := ../common/platform.o diff --git a/arch/mips/au1000/mtx-1/Makefile b/arch/mips/au1000/mtx-1/Makefile index 7c67b3d..ef98975 100644 --- a/arch/mips/au1000/mtx-1/Makefile +++ b/arch/mips/au1000/mtx-1/Makefile @@ -7,6 +7,6 @@ # lib-y := init.o board_setup.o irqmap.o -obj-y := platform.o +obj-y := platform.o ../common/platform.o EXTRA_CFLAGS += -Werror diff --git a/arch/mips/au1000/pb1000/Makefile b/arch/mips/au1000/pb1000/Makefile index 99bbec0..41a09be 100644 --- a/arch/mips/au1000/pb1000/Makefile +++ b/arch/mips/au1000/pb1000/Makefile @@ -6,3 +6,4 @@ # lib-y := init.o board_setup.o irqmap.o +obj-y := ../common/platform.o diff --git a/arch/mips/au1000/pb1100/Makefile b/arch/mips/au1000/pb1100/Makefile index 793e97c..1a8cd71 100644 --- a/arch/mips/au1000/pb1100/Makefile +++ b/arch/mips/au1000/pb1100/Makefile @@ -6,3 +6,4 @@ # lib-y := init.o board_setup.o irqmap.o +obj-y := ../common/platform.o diff --git a/arch/mips/au1000/pb1200/Makefile b/arch/mips/au1000/pb1200/Makefile index d678adf..7b9f2f5 100644 --- a/arch/mips/au1000/pb1200/Makefile +++ b/arch/mips/au1000/pb1200/Makefile @@ -3,6 +3,6 @@ # lib-y := init.o board_setup.o irqmap.o -obj-y += platform.o +obj-y += platform.o ../common/platform.o EXTRA_CFLAGS += -Werror diff --git a/arch/mips/au1000/pb1500/Makefile b/arch/mips/au1000/pb1500/Makefile index 602f38d..c12e1bd 100644 --- a/arch/mips/au1000/pb1500/Makefile +++ b/arch/mips/au1000/pb1500/Makefile @@ -6,3 +6,4 @@ # lib-y := init.o board_setup.o irqmap.o +obj-y := ../common/platform.o diff --git a/arch/mips/au1000/pb1550/Makefile b/arch/mips/au1000/pb1550/Makefile index 7d8beca..8df0890 100644 --- a/arch/mips/au1000/pb1550/Makefile +++ b/arch/mips/au1000/pb1550/Makefile @@ -6,3 +6,4 @@ # lib-y := init.o board_setup.o irqmap.o +obj-y := ../common/platform.o diff --git a/arch/mips/au1000/xxs1500/Makefile b/arch/mips/au1000/xxs1500/Makefile index db3c526..86db0f7 100644 --- a/arch/mips/au1000/xxs1500/Makefile +++ b/arch/mips/au1000/xxs1500/Makefile @@ -6,3 +6,4 @@ # lib-y := init.o board_setup.o irqmap.o +obj-y := ../common/platform.o -- 1.5.6.4 From mano@roarinelk.homelinux.net Tue Aug 12 18:45:18 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 12 Aug 2008 18:45:26 +0100 (BST) Received: from fnoeppeil48.netpark.at ([217.175.205.176]:29924 "EHLO roarinelk.homelinux.net") by ftp.linux-mips.org with ESMTP id S28592151AbYHLRm4 (ORCPT ); Tue, 12 Aug 2008 18:42:56 +0100 Received: (qmail 9120 invoked from network); 12 Aug 2008 19:42:53 +0200 Received: from flagship.roarinelk.net (HELO localhost.localdomain) (192.168.0.197) by 192.168.0.1 with SMTP; 12 Aug 2008 19:42:53 +0200 From: Manuel Lauss To: Ralf Baechle Cc: Kevin Hickey , Linux-MIPS , Manuel Lauss Subject: [PATCH 07/10] Alchemy: split core PM code from sysctl parts. Date: Tue, 12 Aug 2008 19:42:48 +0200 Message-Id: <77b567274fbc6df7667b6e59be2a52ee9357b0e4.1218561746.git.mano@roarinelk.homelinux.net> X-Mailer: git-send-email 1.5.6.4 In-Reply-To: References: In-Reply-To: References: Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20186 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mano@roarinelk.homelinux.net Precedence: bulk X-list: linux-mips Content-Length: 18435 Lines: 703 The Alchemy power.c file contains both core suspend/resume code, which is processor specific, and leftovers of the 2.4 PM userspace interface (sysctls). This patch moves the userspace interface to the platform.c file and leaves the core board-independent suspend/resume parts which should be usable for all Alchemy-based systems intact. Signed-off-by: Manuel Lauss --- arch/mips/au1000/common/platform.c | 305 ++++++++++++++++++++++++++++++++++- arch/mips/au1000/common/power.c | 318 +----------------------------------- 2 files changed, 306 insertions(+), 317 deletions(-) diff --git a/arch/mips/au1000/common/platform.c b/arch/mips/au1000/common/platform.c index 66d6770..8d0f05a 100644 --- a/arch/mips/au1000/common/platform.c +++ b/arch/mips/au1000/common/platform.c @@ -6,6 +6,9 @@ * (C) Copyright Embedded Alley Solutions, Inc 2005 * Author: Pantelis Antoniou * + * Some of the routines are right out of init/main.c, whose + * copyrights apply here. + * * This file is licensed under the terms of the GNU General Public * License version 2. This program is licensed "as is" without any * warranty of any kind, whether express or implied. @@ -19,7 +22,11 @@ #include #include #include -#include +#include +#include +#include +#include +#include #include @@ -322,3 +329,299 @@ static int __init au1xxx_platform_init(void) } arch_initcall(au1xxx_platform_init); + + +/*********************************************************************/ + + +#ifdef CONFIG_PM + +static DEFINE_SPINLOCK(pm_lock); + +extern unsigned long save_local_and_disable(int controller); +extern void restore_local_and_enable(int controller, unsigned long mask); +extern void local_enable_irq(unsigned int irq_nr); +extern void au_sleep(void); + +/* + * Define this to cause the value you write to /proc/sys/pm/sleep to + * set the TOY timer for the amount of time you want to sleep. + * This is done mainly for testing, but may be useful in other cases. + * The value is number of 32KHz ticks to sleep. + */ +#define SLEEP_TEST_TIMEOUT 1 +#ifdef SLEEP_TEST_TIMEOUT +static int sleep_ticks; +static void wakeup_counter0_set(int ticks) +{ + au_writel(au_readl(SYS_TOYREAD) + ticks, SYS_TOYMATCH2); + au_sync(); +} +#endif + +static int pm_do_sleep(ctl_table *ctl, int write, struct file *file, + void __user *buffer, size_t *len, loff_t *ppos) +{ + unsigned long wakeup, flags; +#ifdef SLEEP_TEST_TIMEOUT +#define TMPBUFLEN2 16 + char buf[TMPBUFLEN2], *p; +#endif + + spin_lock_irqsave(&pm_lock, flags); + + if (!write) { + *len = 0; + spin_unlock_irqrestore(&pm_lock, flags); + return 0; + } + +#ifdef SLEEP_TEST_TIMEOUT + if (*len > TMPBUFLEN2 - 1) + return -EFAULT; + if (copy_from_user(buf, buffer, *len)) + return -EFAULT; + buf[*len] = 0; + p = buf; + sleep_ticks = simple_strtoul(p, &p, 0); +#endif + + /** + ** The code below is all system dependent and we should probably + ** have a function call out of here to set this up. You need + ** to configure the GPIO or timer interrupts that will bring + ** you out of sleep. + ** For testing, the TOY counter wakeup is useful. + **/ +#if 0 + au_writel(au_readl(SYS_PINSTATERD) & ~(1 << 11), SYS_PINSTATERD); + + /* GPIO 6 can cause a wake up event */ + wakeup = au_readl(SYS_WAKEMSK); + wakeup &= ~(1 << 8); /* turn off match20 wakeup */ + wakeup |= 1 << 6; /* turn on GPIO 6 wakeup */ +#else + /* For testing, allow match20 to wake us up. */ +#ifdef SLEEP_TEST_TIMEOUT + wakeup_counter0_set(sleep_ticks); +#endif + wakeup = 1 << 8; /* turn on match20 wakeup */ +#endif + au_writel(1, SYS_WAKESRC); /* clear cause */ + au_sync(); + au_writel(wakeup, SYS_WAKEMSK); + au_sync(); + + au_sleep(); + + spin_unlock_irqrestore(&pm_lock, flags); + + return 0; +} + +/* + * This is the number of bits of precision for the loops_per_jiffy. + * Each bit takes on average 1.5/HZ seconds. This (like the original) + * is a little better than 1%. + */ +#define LPS_PREC 8 + +static void au1000_calibrate_delay(void) +{ + unsigned long ticks, loopbit; + int lps_precision = LPS_PREC; + + loops_per_jiffy = 1 << 12; + + while (loops_per_jiffy <<= 1) { + /* Wait for "start of" clock tick */ + ticks = jiffies; + while (ticks == jiffies) + /* nothing */ ; + /* Go ... */ + ticks = jiffies; + __delay(loops_per_jiffy); + ticks = jiffies - ticks; + if (ticks) + break; + } + + /* + * Do a binary approximation to get loops_per_jiffy set to be equal + * one clock (up to lps_precision bits) + */ + loops_per_jiffy >>= 1; + loopbit = loops_per_jiffy; + while (lps_precision-- && (loopbit >>= 1)) { + loops_per_jiffy |= loopbit; + ticks = jiffies; + while (ticks == jiffies); + ticks = jiffies; + __delay(loops_per_jiffy); + if (jiffies != ticks) /* longer than 1 tick */ + loops_per_jiffy &= ~loopbit; + } +} + +static int pm_do_freq(ctl_table *ctl, int write, struct file *file, + void __user *buffer, size_t *len, loff_t *ppos) +{ + int retval = 0, i; + unsigned long val, pll; +#define TMPBUFLEN 64 +#define MAX_CPU_FREQ 396 + char buf[TMPBUFLEN], *p; + unsigned long flags, intc0_mask, intc1_mask; + unsigned long old_baud_base, old_cpu_freq, old_clk, old_refresh; + unsigned long new_baud_base, new_cpu_freq, new_clk, new_refresh; + unsigned long baud_rate; + + spin_lock_irqsave(&pm_lock, flags); + if (!write) + *len = 0; + else { + /* Parse the new frequency */ + if (*len > TMPBUFLEN - 1) { + spin_unlock_irqrestore(&pm_lock, flags); + return -EFAULT; + } + if (copy_from_user(buf, buffer, *len)) { + spin_unlock_irqrestore(&pm_lock, flags); + return -EFAULT; + } + buf[*len] = 0; + p = buf; + val = simple_strtoul(p, &p, 0); + if (val > MAX_CPU_FREQ) { + spin_unlock_irqrestore(&pm_lock, flags); + return -EFAULT; + } + + pll = val / 12; + if ((pll > 33) || (pll < 7)) { /* 396 MHz max, 84 MHz min */ + /* Revisit this for higher speed CPUs */ + spin_unlock_irqrestore(&pm_lock, flags); + return -EFAULT; + } + + old_baud_base = get_au1x00_uart_baud_base(); + old_cpu_freq = get_au1x00_speed(); + + new_cpu_freq = pll * 12 * 1000000; + new_baud_base = (new_cpu_freq / (2 * ((int)(au_readl(SYS_POWERCTRL) + & 0x03) + 2) * 16)); + set_au1x00_speed(new_cpu_freq); + set_au1x00_uart_baud_base(new_baud_base); + + old_refresh = au_readl(MEM_SDREFCFG) & 0x1ffffff; + new_refresh = ((old_refresh * new_cpu_freq) / old_cpu_freq) | + (au_readl(MEM_SDREFCFG) & ~0x1ffffff); + + au_writel(pll, SYS_CPUPLL); + au_sync_delay(1); + au_writel(new_refresh, MEM_SDREFCFG); + au_sync_delay(1); + + for (i = 0; i < 4; i++) + if (au_readl(UART_BASE + UART_MOD_CNTRL + + i * 0x00100000) == 3) { + old_clk = au_readl(UART_BASE + UART_CLK + + i * 0x00100000); + baud_rate = old_baud_base / old_clk; + /* + * We won't get an exact baud rate and the error + * could be significant enough that our new + * calculation will result in a clock that will + * give us a baud rate that's too far off from + * what we really want. + */ + if (baud_rate > 100000) + baud_rate = 115200; + else if (baud_rate > 50000) + baud_rate = 57600; + else if (baud_rate > 30000) + baud_rate = 38400; + else if (baud_rate > 17000) + baud_rate = 19200; + else + baud_rate = 9600; + new_clk = new_baud_base / baud_rate; + au_writel(new_clk, UART_BASE + UART_CLK + + i * 0x00100000); + au_sync_delay(10); + } + } + + /* + * We don't want _any_ interrupts other than match20. Otherwise our + * au1000_calibrate_delay() calculation will be off, potentially a lot. + */ + intc0_mask = save_local_and_disable(0); + intc1_mask = save_local_and_disable(1); + local_enable_irq(AU1000_TOY_MATCH2_INT); + spin_unlock_irqrestore(&pm_lock, flags); + au1000_calibrate_delay(); + restore_local_and_enable(0, intc0_mask); + restore_local_and_enable(1, intc1_mask); + + return retval; +} + + +static struct ctl_table pm_table[] = { + { + .ctl_name = CTL_UNNUMBERED, + .procname = "sleep", + .data = NULL, + .maxlen = 0, + .mode = 0600, + .proc_handler = &pm_do_sleep + }, + { + .ctl_name = CTL_UNNUMBERED, + .procname = "freq", + .data = NULL, + .maxlen = 0, + .mode = 0600, + .proc_handler = &pm_do_freq + }, + {} +}; + +static struct ctl_table pm_dir_table[] = { + { + .ctl_name = CTL_UNNUMBERED, + .procname = "pm", + .mode = 0555, + .child = pm_table + }, + {} +}; + +/* + * Initialize power interface + */ +static int __init pm_init(void) +{ + /* init TOY to tick at 1Hz. No need to wait for access bits + * since there's plenty of time between here and the first + * suspend cycle. + */ + if (au_readl(SYS_TOYTRIM) != 32767) { + au_writel(32767, SYS_TOYTRIM); + au_sync(); + } + + au_writel(0, SYS_WAKESRC); + au_sync(); + au_writel(0, SYS_WAKEMSK); + au_sync(); + + register_sysctl_table(pm_dir_table); + + return 0; +} + +__initcall(pm_init); + +#endif /* CONFIG_PM */ diff --git a/arch/mips/au1000/common/power.c b/arch/mips/au1000/common/power.c index 7812ebf..4b0f6a1 100644 --- a/arch/mips/au1000/common/power.c +++ b/arch/mips/au1000/common/power.c @@ -5,9 +5,6 @@ * Copyright 2001, 2008 MontaVista Software Inc. * Author: MontaVista Software, Inc. * - * Some of the routines are right out of init/main.c, whose - * copyrights apply here. - * * This program is free software; you can redistribute it and/or modify it * under the terms of the GNU General Public License as published by the * Free Software Foundation; either version 2 of the License, or (at your @@ -30,30 +27,12 @@ */ #include -#include -#include -#include - -#include #include #include #ifdef CONFIG_PM -#define DEBUG 1 -#ifdef DEBUG -#define DPRINTK(fmt, args...) printk(KERN_DEBUG "%s: " fmt, __func__, ## args) -#else -#define DPRINTK(fmt, args...) -#endif - -static void au1000_calibrate_delay(void); - -extern unsigned long save_local_and_disable(int controller); -extern void restore_local_and_enable(int controller, unsigned long mask); -extern void local_enable_irq(unsigned int irq_nr); - -static DEFINE_SPINLOCK(pm_lock); +extern void save_and_sleep(void); /* * We need to save/restore a bunch of core registers that are @@ -77,22 +56,6 @@ static unsigned int sleep_usbhost_enable; static unsigned int sleep_usbdev_enable; static unsigned int sleep_static_memctlr[4][3]; -/* - * Define this to cause the value you write to /proc/sys/pm/sleep to - * set the TOY timer for the amount of time you want to sleep. - * This is done mainly for testing, but may be useful in other cases. - * The value is number of 32KHz ticks to sleep. - */ -#define SLEEP_TEST_TIMEOUT 1 -#ifdef SLEEP_TEST_TIMEOUT -static int sleep_ticks; -static void wakeup_counter0_set(int ticks) -{ - au_writel(au_readl(SYS_TOYREAD) + ticks, SYS_TOYMATCH2); - au_sync(); -} -#endif - static void save_core_regs(void) { extern void save_au1xxx_intctl(void); @@ -190,288 +153,11 @@ static void restore_core_regs(void) restore_au1xxx_intctl(); } -unsigned long suspend_mode; - -void wakeup_from_suspend(void) -{ - suspend_mode = 0; -} - -int au_sleep(void) +void au_sleep(void) { - unsigned long wakeup, flags; - extern void save_and_sleep(void); - - spin_lock_irqsave(&pm_lock, flags); - save_core_regs(); - flush_cache_all(); - - /** - ** The code below is all system dependent and we should probably - ** have a function call out of here to set this up. You need - ** to configure the GPIO or timer interrupts that will bring - ** you out of sleep. - ** For testing, the TOY counter wakeup is useful. - **/ -#if 0 - au_writel(au_readl(SYS_PINSTATERD) & ~(1 << 11), SYS_PINSTATERD); - - /* GPIO 6 can cause a wake up event */ - wakeup = au_readl(SYS_WAKEMSK); - wakeup &= ~(1 << 8); /* turn off match20 wakeup */ - wakeup |= 1 << 6; /* turn on GPIO 6 wakeup */ -#else - /* For testing, allow match20 to wake us up. */ -#ifdef SLEEP_TEST_TIMEOUT - wakeup_counter0_set(sleep_ticks); -#endif - wakeup = 1 << 8; /* turn on match20 wakeup */ - wakeup = 0; -#endif - au_writel(1, SYS_WAKESRC); /* clear cause */ - au_sync(); - au_writel(wakeup, SYS_WAKEMSK); - au_sync(); - save_and_sleep(); - - /* - * After a wakeup, the cpu vectors back to 0x1fc00000, so - * it's up to the boot code to get us back here. - */ restore_core_regs(); - spin_unlock_irqrestore(&pm_lock, flags); - return 0; -} - -static int pm_do_sleep(ctl_table *ctl, int write, struct file *file, - void __user *buffer, size_t *len, loff_t *ppos) -{ -#ifdef SLEEP_TEST_TIMEOUT -#define TMPBUFLEN2 16 - char buf[TMPBUFLEN2], *p; -#endif - - if (!write) - *len = 0; - else { -#ifdef SLEEP_TEST_TIMEOUT - if (*len > TMPBUFLEN2 - 1) - return -EFAULT; - if (copy_from_user(buf, buffer, *len)) - return -EFAULT; - buf[*len] = 0; - p = buf; - sleep_ticks = simple_strtoul(p, &p, 0); -#endif - - au_sleep(); - } - return 0; -} - -static int pm_do_freq(ctl_table *ctl, int write, struct file *file, - void __user *buffer, size_t *len, loff_t *ppos) -{ - int retval = 0, i; - unsigned long val, pll; -#define TMPBUFLEN 64 -#define MAX_CPU_FREQ 396 - char buf[TMPBUFLEN], *p; - unsigned long flags, intc0_mask, intc1_mask; - unsigned long old_baud_base, old_cpu_freq, old_clk, old_refresh; - unsigned long new_baud_base, new_cpu_freq, new_clk, new_refresh; - unsigned long baud_rate; - - spin_lock_irqsave(&pm_lock, flags); - if (!write) - *len = 0; - else { - /* Parse the new frequency */ - if (*len > TMPBUFLEN - 1) { - spin_unlock_irqrestore(&pm_lock, flags); - return -EFAULT; - } - if (copy_from_user(buf, buffer, *len)) { - spin_unlock_irqrestore(&pm_lock, flags); - return -EFAULT; - } - buf[*len] = 0; - p = buf; - val = simple_strtoul(p, &p, 0); - if (val > MAX_CPU_FREQ) { - spin_unlock_irqrestore(&pm_lock, flags); - return -EFAULT; - } - - pll = val / 12; - if ((pll > 33) || (pll < 7)) { /* 396 MHz max, 84 MHz min */ - /* Revisit this for higher speed CPUs */ - spin_unlock_irqrestore(&pm_lock, flags); - return -EFAULT; - } - - old_baud_base = get_au1x00_uart_baud_base(); - old_cpu_freq = get_au1x00_speed(); - - new_cpu_freq = pll * 12 * 1000000; - new_baud_base = (new_cpu_freq / (2 * ((int)(au_readl(SYS_POWERCTRL) - & 0x03) + 2) * 16)); - set_au1x00_speed(new_cpu_freq); - set_au1x00_uart_baud_base(new_baud_base); - - old_refresh = au_readl(MEM_SDREFCFG) & 0x1ffffff; - new_refresh = ((old_refresh * new_cpu_freq) / old_cpu_freq) | - (au_readl(MEM_SDREFCFG) & ~0x1ffffff); - - au_writel(pll, SYS_CPUPLL); - au_sync_delay(1); - au_writel(new_refresh, MEM_SDREFCFG); - au_sync_delay(1); - - for (i = 0; i < 4; i++) - if (au_readl(UART_BASE + UART_MOD_CNTRL + - i * 0x00100000) == 3) { - old_clk = au_readl(UART_BASE + UART_CLK + - i * 0x00100000); - baud_rate = old_baud_base / old_clk; - /* - * We won't get an exact baud rate and the error - * could be significant enough that our new - * calculation will result in a clock that will - * give us a baud rate that's too far off from - * what we really want. - */ - if (baud_rate > 100000) - baud_rate = 115200; - else if (baud_rate > 50000) - baud_rate = 57600; - else if (baud_rate > 30000) - baud_rate = 38400; - else if (baud_rate > 17000) - baud_rate = 19200; - else - baud_rate = 9600; - new_clk = new_baud_base / baud_rate; - au_writel(new_clk, UART_BASE + UART_CLK + - i * 0x00100000); - au_sync_delay(10); - } - } - - /* - * We don't want _any_ interrupts other than match20. Otherwise our - * au1000_calibrate_delay() calculation will be off, potentially a lot. - */ - intc0_mask = save_local_and_disable(0); - intc1_mask = save_local_and_disable(1); - local_enable_irq(AU1000_TOY_MATCH2_INT); - spin_unlock_irqrestore(&pm_lock, flags); - au1000_calibrate_delay(); - restore_local_and_enable(0, intc0_mask); - restore_local_and_enable(1, intc1_mask); - - return retval; -} - - -static struct ctl_table pm_table[] = { - { - .ctl_name = CTL_UNNUMBERED, - .procname = "sleep", - .data = NULL, - .maxlen = 0, - .mode = 0600, - .proc_handler = &pm_do_sleep - }, - { - .ctl_name = CTL_UNNUMBERED, - .procname = "freq", - .data = NULL, - .maxlen = 0, - .mode = 0600, - .proc_handler = &pm_do_freq - }, - {} -}; - -static struct ctl_table pm_dir_table[] = { - { - .ctl_name = CTL_UNNUMBERED, - .procname = "pm", - .mode = 0555, - .child = pm_table - }, - {} -}; - -/* - * Initialize power interface - */ -static int __init pm_init(void) -{ - /* init TOY to tick at 1Hz. No need to wait for access bits - * since there's plenty of time between here and the first - * suspend cycle. - */ - if (au_readl(SYS_TOYTRIM) != 32767) { - au_writel(32767, SYS_TOYTRIM); - au_sync(); - } - - register_sysctl_table(pm_dir_table); - return 0; -} - -__initcall(pm_init); - -/* - * This is right out of init/main.c - */ - -/* - * This is the number of bits of precision for the loops_per_jiffy. - * Each bit takes on average 1.5/HZ seconds. This (like the original) - * is a little better than 1%. - */ -#define LPS_PREC 8 - -static void au1000_calibrate_delay(void) -{ - unsigned long ticks, loopbit; - int lps_precision = LPS_PREC; - - loops_per_jiffy = 1 << 12; - - while (loops_per_jiffy <<= 1) { - /* Wait for "start of" clock tick */ - ticks = jiffies; - while (ticks == jiffies) - /* nothing */ ; - /* Go ... */ - ticks = jiffies; - __delay(loops_per_jiffy); - ticks = jiffies - ticks; - if (ticks) - break; - } - - /* - * Do a binary approximation to get loops_per_jiffy set to be equal - * one clock (up to lps_precision bits) - */ - loops_per_jiffy >>= 1; - loopbit = loops_per_jiffy; - while (lps_precision-- && (loopbit >>= 1)) { - loops_per_jiffy |= loopbit; - ticks = jiffies; - while (ticks == jiffies); - ticks = jiffies; - __delay(loops_per_jiffy); - if (jiffies != ticks) /* longer than 1 tick */ - loops_per_jiffy &= ~loopbit; - } } #endif /* CONFIG_PM */ -- 1.5.6.4 From mano@roarinelk.homelinux.net Tue Aug 12 18:45:43 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 12 Aug 2008 18:45:51 +0100 (BST) Received: from fnoeppeil48.netpark.at ([217.175.205.176]:2200 "EHLO roarinelk.homelinux.net") by ftp.linux-mips.org with ESMTP id S28592154AbYHLRm4 (ORCPT ); Tue, 12 Aug 2008 18:42:56 +0100 Received: (qmail 9125 invoked from network); 12 Aug 2008 19:42:53 +0200 Received: from flagship.roarinelk.net (HELO localhost.localdomain) (192.168.0.197) by 192.168.0.1 with SMTP; 12 Aug 2008 19:42:53 +0200 From: Manuel Lauss To: Ralf Baechle Cc: Kevin Hickey , Linux-MIPS , Manuel Lauss Subject: [PATCH 08/10] Alchemy: Fix PM code for Au1200/Au1550. Date: Tue, 12 Aug 2008 19:42:49 +0200 Message-Id: X-Mailer: git-send-email 1.5.6.4 In-Reply-To: References: In-Reply-To: References: Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20187 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mano@roarinelk.homelinux.net Precedence: bulk X-list: linux-mips Content-Length: 11341 Lines: 418 Alchemy PM code doesn't compile on Au1200. Copy the Au1200/Au1550 sleep code over from 2.4. Tested on Au1200. Signed-off-by: Manuel Lauss --- arch/mips/au1000/common/platform.c | 5 +- arch/mips/au1000/common/power.c | 111 +++++++++++++++++++++------------ arch/mips/au1000/common/sleeper.S | 121 ++++++++++++++++++++++-------------- 3 files changed, 150 insertions(+), 87 deletions(-) diff --git a/arch/mips/au1000/common/platform.c b/arch/mips/au1000/common/platform.c index 8d0f05a..b5ff42a 100644 --- a/arch/mips/au1000/common/platform.c +++ b/arch/mips/au1000/common/platform.c @@ -419,6 +419,7 @@ static int pm_do_sleep(ctl_table *ctl, int write, struct file *file, return 0; } +#if !defined(CONFIG_SOC_AU1200) && !defined(CONFIG_SOC_AU1550) /* * This is the number of bits of precision for the loops_per_jiffy. * Each bit takes on average 1.5/HZ seconds. This (like the original) @@ -566,7 +567,7 @@ static int pm_do_freq(ctl_table *ctl, int write, struct file *file, return retval; } - +#endif static struct ctl_table pm_table[] = { { @@ -577,6 +578,7 @@ static struct ctl_table pm_table[] = { .mode = 0600, .proc_handler = &pm_do_sleep }, +#if !defined(CONFIG_SOC_AU1200) && !defined(CONFIG_SOC_AU1550) { .ctl_name = CTL_UNNUMBERED, .procname = "freq", @@ -585,6 +587,7 @@ static struct ctl_table pm_table[] = { .mode = 0600, .proc_handler = &pm_do_freq }, +#endif {} }; diff --git a/arch/mips/au1000/common/power.c b/arch/mips/au1000/common/power.c index 4b0f6a1..ba4c946 100644 --- a/arch/mips/au1000/common/power.c +++ b/arch/mips/au1000/common/power.c @@ -26,13 +26,13 @@ * 675 Mass Ave, Cambridge, MA 02139, USA. */ -#include -#include -#include - #ifdef CONFIG_PM +#include + extern void save_and_sleep(void); +extern void save_au1xxx_intctl(void); +extern void restore_au1xxx_intctl(void); /* * We need to save/restore a bunch of core registers that are @@ -44,23 +44,18 @@ extern void save_and_sleep(void); * We only have to save/restore registers that aren't otherwise * done as part of a driver pm_* function. */ -static unsigned int sleep_aux_pll_cntrl; -static unsigned int sleep_cpu_pll_cntrl; -static unsigned int sleep_pin_function; -static unsigned int sleep_uart0_inten; -static unsigned int sleep_uart0_fifoctl; -static unsigned int sleep_uart0_linectl; -static unsigned int sleep_uart0_clkdiv; -static unsigned int sleep_uart0_enable; -static unsigned int sleep_usbhost_enable; -static unsigned int sleep_usbdev_enable; -static unsigned int sleep_static_memctlr[4][3]; +static unsigned int sleep_uart0_inten; +static unsigned int sleep_uart0_fifoctl; +static unsigned int sleep_uart0_linectl; +static unsigned int sleep_uart0_clkdiv; +static unsigned int sleep_uart0_enable; +static unsigned int sleep_usb[2]; +static unsigned int sleep_sys_clocks[5]; +static unsigned int sleep_sys_pinfunc; +static unsigned int sleep_static_memctlr[4][3]; static void save_core_regs(void) { - extern void save_au1xxx_intctl(void); - extern void pm_eth0_shutdown(void); - /* * Do the serial ports.....these really should be a pm_* * registered function by the driver......but of course the @@ -72,31 +67,45 @@ static void save_core_regs(void) sleep_uart0_linectl = au_readl(UART0_ADDR + UART_LCR); sleep_uart0_clkdiv = au_readl(UART0_ADDR + UART_CLK); sleep_uart0_enable = au_readl(UART0_ADDR + UART_MOD_CNTRL); + au_sync(); +#ifndef CONFIG_SOC_AU1200 /* Shutdown USB host/device. */ - sleep_usbhost_enable = au_readl(USB_HOST_CONFIG); + sleep_usb[0] = au_readl(USB_HOST_CONFIG); /* There appears to be some undocumented reset register.... */ - au_writel(0, 0xb0100004); au_sync(); - au_writel(0, USB_HOST_CONFIG); au_sync(); + au_writel(0, 0xb0100004); + au_sync(); + au_writel(0, USB_HOST_CONFIG); + au_sync(); + + sleep_usb[1] = au_readl(USBD_ENABLE); + au_writel(0, USBD_ENABLE); + au_sync(); - sleep_usbdev_enable = au_readl(USBD_ENABLE); - au_writel(0, USBD_ENABLE); au_sync(); +#else /* AU1200 */ + + /* enable access to OTG mmio so we can save OTG CAP/MUX. + * FIXME: write an OTG driver and move this stuff there! + */ + au_writel(au_readl(USB_MSR_BASE + 4) | (1 << 6), USB_MSR_BASE + 4); + au_sync(); + sleep_usb[0] = au_readl(0xb4020020); /* OTG_CAP */ + sleep_usb[1] = au_readl(0xb4020024); /* OTG_MUX */ +#endif /* Save interrupt controller state. */ save_au1xxx_intctl(); /* Clocks and PLLs. */ - sleep_aux_pll_cntrl = au_readl(SYS_AUXPLL); - - /* - * We don't really need to do this one, but unless we - * write it again it won't have a valid value if we - * happen to read it. - */ - sleep_cpu_pll_cntrl = au_readl(SYS_CPUPLL); + sleep_sys_clocks[0] = au_readl(SYS_FREQCTRL0); + sleep_sys_clocks[1] = au_readl(SYS_FREQCTRL1); + sleep_sys_clocks[2] = au_readl(SYS_CLKSRC); + sleep_sys_clocks[3] = au_readl(SYS_CPUPLL); + sleep_sys_clocks[4] = au_readl(SYS_AUXPLL); - sleep_pin_function = au_readl(SYS_PINFUNC); + /* pin mux config */ + sleep_sys_pinfunc = au_readl(SYS_PINFUNC); /* Save the static memory controller configuration. */ sleep_static_memctlr[0][0] = au_readl(MEM_STCFG0); @@ -115,12 +124,37 @@ static void save_core_regs(void) static void restore_core_regs(void) { - extern void restore_au1xxx_intctl(void); - extern void wakeup_counter0_adjust(void); - - au_writel(sleep_aux_pll_cntrl, SYS_AUXPLL); au_sync(); - au_writel(sleep_cpu_pll_cntrl, SYS_CPUPLL); au_sync(); - au_writel(sleep_pin_function, SYS_PINFUNC); au_sync(); + /* restore clock configuration. Writing CPUPLL last will + * stall a bit and stabilize other clocks (unless this is + * one of those Au1000 with a write-only PLL, where we dont + * have a valid value) + */ + au_writel(sleep_sys_clocks[0], SYS_FREQCTRL0); + au_writel(sleep_sys_clocks[1], SYS_FREQCTRL1); + au_writel(sleep_sys_clocks[2], SYS_CLKSRC); + au_writel(sleep_sys_clocks[4], SYS_AUXPLL); + if (!au1xxx_cpu_has_pll_wo()) + au_writel(sleep_sys_clocks[3], SYS_CPUPLL); + au_sync(); + + au_writel(sleep_sys_pinfunc, SYS_PINFUNC); + au_sync(); + +#ifndef CONFIG_SOC_AU1200 + au_writel(sleep_usb[0], USB_HOST_CONFIG); + au_writel(sleep_usb[1], USBD_ENABLE); + au_sync(); +#else + /* enable accces to OTG memory */ + au_writel(au_readl(USB_MSR_BASE + 4) | (1 << 6), USB_MSR_BASE + 4); + au_sync(); + + /* restore OTG caps and port mux. */ + au_writel(sleep_usb[0], 0xb4020020 + 0); /* OTG_CAP */ + au_sync(); + au_writel(sleep_usb[1], 0xb4020020 + 4); /* OTG_MUX */ + au_sync(); +#endif /* Restore the static memory controller configuration. */ au_writel(sleep_static_memctlr[0][0], MEM_STCFG0); @@ -156,7 +190,6 @@ static void restore_core_regs(void) void au_sleep(void) { save_core_regs(); - flush_cache_all(); save_and_sleep(); restore_core_regs(); } diff --git a/arch/mips/au1000/common/sleeper.S b/arch/mips/au1000/common/sleeper.S index 4b3cf02..76506aa 100644 --- a/arch/mips/au1000/common/sleeper.S +++ b/arch/mips/au1000/common/sleeper.S @@ -15,9 +15,11 @@ #include #include + .extern __flush_cache_all + .text - .set macro - .set noat + .set noreorder + .set noat .align 5 /* Save all of the processor general registers and go to sleep. @@ -33,14 +35,6 @@ LEAF(save_and_sleep) sw $5, PT_R5(sp) sw $6, PT_R6(sp) sw $7, PT_R7(sp) - sw $8, PT_R8(sp) - sw $9, PT_R9(sp) - sw $10, PT_R10(sp) - sw $11, PT_R11(sp) - sw $12, PT_R12(sp) - sw $13, PT_R13(sp) - sw $14, PT_R14(sp) - sw $15, PT_R15(sp) sw $16, PT_R16(sp) sw $17, PT_R17(sp) sw $18, PT_R18(sp) @@ -49,12 +43,9 @@ LEAF(save_and_sleep) sw $21, PT_R21(sp) sw $22, PT_R22(sp) sw $23, PT_R23(sp) - sw $24, PT_R24(sp) - sw $25, PT_R25(sp) sw $26, PT_R26(sp) sw $27, PT_R27(sp) sw $28, PT_R28(sp) - sw $29, PT_R29(sp) sw $30, PT_R30(sp) sw $31, PT_R31(sp) mfc0 k0, CP0_STATUS @@ -66,44 +57,89 @@ LEAF(save_and_sleep) mfc0 k0, CP0_CONFIG sw k0, 0x14(sp) + /* flush caches to make sure context is in memory */ + la t1, __flush_cache_all + lw t0, 0(t1) + jal t0 + nop + /* Now set up the scratch registers so the boot rom will * return to this point upon wakeup. + * sys_scratch0 : SP + * sys_scratch1 : RA */ - la k0, 1f - lui k1, 0xb190 - ori k1, 0x18 - sw sp, 0(k1) - ori k1, 0x1c - sw k0, 0(k1) - -/* Put SDRAM into self refresh. Preload instructions into cache, - * issue a precharge, then auto refresh, then sleep commands to it. - */ - la t0, sdsleep + li t3, 0xb1900000 /* sys_xxx */ + sw sp, 0x0018(t3) + la k0, resume_from_sleep + sw k0, 0x001c(t3) + + /* Put SDRAM into self refresh. Preload instructions into cache, + * issue a precharge, then auto refresh, then sleep commands to it. + */ + la t0, sdsleep .set mips3 - cache 0x14, 0(t0) - cache 0x14, 32(t0) - cache 0x14, 64(t0) - cache 0x14, 96(t0) + cache 0x14, 0(t0) + cache 0x14, 32(t0) + cache 0x14, 64(t0) + cache 0x14, 96(t0) .set mips0 sdsleep: - lui k0, 0xb400 - sw zero, 0x001c(k0) /* Precharge */ - sw zero, 0x0020(k0) /* Auto refresh */ - sw zero, 0x0030(k0) /* SDRAM sleep */ + li a0, 0xb4000000 /* mem_xxx */ +#if defined(CONFIG_SOC_AU1000) || defined(CONFIG_SOC_AU1100) || \ + defined(CONFIG_SOC_AU1500) + sw zero, 0x001c(a0) /* Precharge */ + sync + sw zero, 0x0020(a0) /* Auto Refresh */ + sync + sw zero, 0x0030(a0) /* Sleep */ sync +#endif - lui k1, 0xb190 - sw zero, 0x0078(k1) /* get ready to sleep */ +#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) + sw zero, 0x08c0(a0) /* Precharge */ sync - sw zero, 0x007c(k1) /* Put processor to sleep */ + sw zero, 0x08d0(a0) /* Self Refresh */ sync + /* wait for sdram to enter self-refresh mode */ + li t0, 0x01000000 +sref_wait_loop: + lw t1, 0x0850(a0) /* mem_sdstat */ + and t2, t1, t0 + beq t2, zero, sref_wait_loop + nop + + /* Disable SDRAM clocks */ + li t0, ~0x30000000 + lw t1, 0x0840(a0) /* mem_sdconfiga */ + and t1, t0, t1 /* clear CE[1:0] */ + sw t1, 0x0840(a0) /* mem_sdconfiga */ + sync +#endif + + /* put power supply and processor to sleep */ + sw zero, 0x0078(t3) /* sys_slppwr */ + sync + sw zero, 0x007c(t3) /* sys_sleep */ + sync + nop + nop + nop + nop + nop + nop + nop + nop + /* This is where we return upon wakeup. * Reload all of the registers and return. */ -1: nop +resume_from_sleep: + nop + .set nomacro + .set noat + lw k0, 0x20(sp) mtc0 k0, CP0_STATUS lw k0, 0x1c(sp) @@ -117,6 +153,7 @@ sdsleep: * the write-only Config[OD] bit and set it back to one... */ jal au1x00_fixup_config_od + nop lw $1, PT_R1(sp) lw $2, PT_R2(sp) lw $3, PT_R3(sp) @@ -124,14 +161,6 @@ sdsleep: lw $5, PT_R5(sp) lw $6, PT_R6(sp) lw $7, PT_R7(sp) - lw $8, PT_R8(sp) - lw $9, PT_R9(sp) - lw $10, PT_R10(sp) - lw $11, PT_R11(sp) - lw $12, PT_R12(sp) - lw $13, PT_R13(sp) - lw $14, PT_R14(sp) - lw $15, PT_R15(sp) lw $16, PT_R16(sp) lw $17, PT_R17(sp) lw $18, PT_R18(sp) @@ -140,15 +169,13 @@ sdsleep: lw $21, PT_R21(sp) lw $22, PT_R22(sp) lw $23, PT_R23(sp) - lw $24, PT_R24(sp) - lw $25, PT_R25(sp) lw $26, PT_R26(sp) lw $27, PT_R27(sp) lw $28, PT_R28(sp) - lw $29, PT_R29(sp) lw $30, PT_R30(sp) lw $31, PT_R31(sp) addiu sp, PT_SIZE jr ra + nop END(save_and_sleep) -- 1.5.6.4 From mano@roarinelk.homelinux.net Tue Aug 12 18:46:08 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 12 Aug 2008 18:46:16 +0100 (BST) Received: from fnoeppeil48.netpark.at ([217.175.205.176]:31617 "EHLO roarinelk.homelinux.net") by ftp.linux-mips.org with ESMTP id S28591436AbYHLRm4 (ORCPT ); Tue, 12 Aug 2008 18:42:56 +0100 Received: (qmail 9129 invoked from network); 12 Aug 2008 19:42:53 +0200 Received: from flagship.roarinelk.net (HELO localhost.localdomain) (192.168.0.197) by 192.168.0.1 with SMTP; 12 Aug 2008 19:42:53 +0200 From: Manuel Lauss To: Ralf Baechle Cc: Kevin Hickey , Linux-MIPS , Manuel Lauss Subject: [PATCH 09/10] Alchemy: dbdma suspend/resume support. Date: Tue, 12 Aug 2008 19:42:50 +0200 Message-Id: <46ed1e347f8a291f4d48762f12e19f6ac96b7963.1218561746.git.mano@roarinelk.homelinux.net> X-Mailer: git-send-email 1.5.6.4 In-Reply-To: References: In-Reply-To: References: Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20188 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mano@roarinelk.homelinux.net Precedence: bulk X-list: linux-mips Content-Length: 4068 Lines: 129 Implement suspend/resume for DBDMA controller and its channels. Signed-off-by: Manuel Lauss --- arch/mips/au1000/common/dbdma.c | 65 +++++++++++++++++++++++++++++++++++++++ arch/mips/au1000/common/power.c | 12 +++++++ 2 files changed, 77 insertions(+), 0 deletions(-) diff --git a/arch/mips/au1000/common/dbdma.c b/arch/mips/au1000/common/dbdma.c index 601ee91..3ab6d80 100644 --- a/arch/mips/au1000/common/dbdma.c +++ b/arch/mips/au1000/common/dbdma.c @@ -174,6 +174,11 @@ static dbdev_tab_t dbdev_tab[] = { #define DBDEV_TAB_SIZE ARRAY_SIZE(dbdev_tab) +#ifdef CONFIG_PM +static u32 au1xxx_dbdma_pm_regs[NUM_DBDMA_CHANS + 1][8]; +#endif + + static chan_tab_t *chan_tab_ptr[NUM_DBDMA_CHANS]; static dbdev_tab_t *find_dbdev_id(u32 id) @@ -975,4 +980,64 @@ u32 au1xxx_dbdma_put_dscr(u32 chanid, au1x_ddma_desc_t *dscr) return nbytes; } +#ifdef CONFIG_PM +void au1xxx_dbdma_suspend(void) +{ + int i; + u32 addr; + + addr = DDMA_GLOBAL_BASE; + au1xxx_dbdma_pm_regs[0][0] = au_readl(addr + 0x00); + au1xxx_dbdma_pm_regs[0][1] = au_readl(addr + 0x04); + au1xxx_dbdma_pm_regs[0][2] = au_readl(addr + 0x08); + au1xxx_dbdma_pm_regs[0][3] = au_readl(addr + 0x0c); + + /* save channel configurations */ + for (i = 1, addr = DDMA_CHANNEL_BASE; i < NUM_DBDMA_CHANS; i++) { + au1xxx_dbdma_pm_regs[i][0] = au_readl(addr + 0x00); + au1xxx_dbdma_pm_regs[i][1] = au_readl(addr + 0x04); + au1xxx_dbdma_pm_regs[i][2] = au_readl(addr + 0x08); + au1xxx_dbdma_pm_regs[i][3] = au_readl(addr + 0x0c); + au1xxx_dbdma_pm_regs[i][4] = au_readl(addr + 0x10); + au1xxx_dbdma_pm_regs[i][5] = au_readl(addr + 0x14); + au1xxx_dbdma_pm_regs[i][6] = au_readl(addr + 0x18); + + /* halt channel */ + au_writel(au1xxx_dbdma_pm_regs[i][0] & ~1, addr + 0x00); + au_sync(); + while (!(au_readl(addr + 0x14) & 1)) + au_sync(); + + addr += 0x100; /* next channel base */ + } + /* disable channel interrupts */ + au_writel(0, DDMA_GLOBAL_BASE + 0x0c); + au_sync(); +} + +void au1xxx_dbdma_resume(void) +{ + int i; + u32 addr; + + addr = DDMA_GLOBAL_BASE; + au_writel(au1xxx_dbdma_pm_regs[0][0], addr + 0x00); + au_writel(au1xxx_dbdma_pm_regs[0][1], addr + 0x04); + au_writel(au1xxx_dbdma_pm_regs[0][2], addr + 0x08); + au_writel(au1xxx_dbdma_pm_regs[0][3], addr + 0x0c); + + /* restore channel configurations */ + for (i = 1, addr = DDMA_CHANNEL_BASE; i < NUM_DBDMA_CHANS; i++) { + au_writel(au1xxx_dbdma_pm_regs[i][0], addr + 0x00); + au_writel(au1xxx_dbdma_pm_regs[i][1], addr + 0x04); + au_writel(au1xxx_dbdma_pm_regs[i][2], addr + 0x08); + au_writel(au1xxx_dbdma_pm_regs[i][3], addr + 0x0c); + au_writel(au1xxx_dbdma_pm_regs[i][4], addr + 0x10); + au_writel(au1xxx_dbdma_pm_regs[i][5], addr + 0x14); + au_writel(au1xxx_dbdma_pm_regs[i][6], addr + 0x18); + au_sync(); + addr += 0x100; /* next channel base */ + } +} +#endif /* CONFIG_PM */ #endif /* defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) */ diff --git a/arch/mips/au1000/common/power.c b/arch/mips/au1000/common/power.c index ba4c946..1057a73 100644 --- a/arch/mips/au1000/common/power.c +++ b/arch/mips/au1000/common/power.c @@ -33,6 +33,10 @@ extern void save_and_sleep(void); extern void save_au1xxx_intctl(void); extern void restore_au1xxx_intctl(void); +#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) +extern void au1xxx_dbdma_suspend(void); +extern void au1xxx_dbdma_resume(void); +#endif /* * We need to save/restore a bunch of core registers that are @@ -120,6 +124,10 @@ static void save_core_regs(void) sleep_static_memctlr[3][0] = au_readl(MEM_STCFG3); sleep_static_memctlr[3][1] = au_readl(MEM_STTIME3); sleep_static_memctlr[3][2] = au_readl(MEM_STADDR3); + +#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) + au1xxx_dbdma_suspend(); +#endif } static void restore_core_regs(void) @@ -185,6 +193,10 @@ static void restore_core_regs(void) } restore_au1xxx_intctl(); + +#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) + au1xxx_dbdma_resume(); +#endif } void au_sleep(void) -- 1.5.6.4 From mano@roarinelk.homelinux.net Tue Aug 12 18:46:33 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 12 Aug 2008 18:46:40 +0100 (BST) Received: from fnoeppeil48.netpark.at ([217.175.205.176]:18592 "EHLO roarinelk.homelinux.net") by ftp.linux-mips.org with ESMTP id S28591739AbYHLRm7 (ORCPT ); Tue, 12 Aug 2008 18:42:59 +0100 Received: (qmail 9108 invoked from network); 12 Aug 2008 19:42:52 +0200 Received: from flagship.roarinelk.net (HELO localhost.localdomain) (192.168.0.197) by 192.168.0.1 with SMTP; 12 Aug 2008 19:42:52 +0200 From: Manuel Lauss To: Ralf Baechle Cc: Kevin Hickey , Linux-MIPS , Manuel Lauss Subject: [PATCH 05/10] Alchemy: move calc_clock function. Date: Tue, 12 Aug 2008 19:42:46 +0200 Message-Id: X-Mailer: git-send-email 1.5.6.4 In-Reply-To: References: In-Reply-To: References: Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20189 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mano@roarinelk.homelinux.net Precedence: bulk X-list: linux-mips Content-Length: 5977 Lines: 185 Now that nothing in time.c depends on calc_clock, it can be moved to clocks.c where it belongs. While at it, give it a better non-generic name and call it as soon as possible in plat_mem_init. Signed-off-by: Manuel Lauss --- arch/mips/au1000/common/clocks.c | 54 ++++++++++++++++++++++++++++++++++++++ arch/mips/au1000/common/setup.c | 9 ++++++ arch/mips/au1000/common/time.c | 54 -------------------------------------- 3 files changed, 63 insertions(+), 54 deletions(-) diff --git a/arch/mips/au1000/common/clocks.c b/arch/mips/au1000/common/clocks.c index a8170fd..d899185 100644 --- a/arch/mips/au1000/common/clocks.c +++ b/arch/mips/au1000/common/clocks.c @@ -27,11 +27,21 @@ */ #include +#include +#include #include +/* + * I haven't found anyone that doesn't use a 12 MHz source clock, + * but just in case..... + */ +#define AU1000_SRC_CLK 12000000 + static unsigned int au1x00_clock; /* Hz */ static unsigned long uart_baud_base; +static DEFINE_SPINLOCK(time_lock); + /* * Set the au1000_clock */ @@ -60,3 +70,47 @@ void set_au1x00_uart_baud_base(unsigned long new_baud_base) { uart_baud_base = new_baud_base; } + +/* + * We read the real processor speed from the PLL. This is important + * because it is more accurate than computing it from the 32 KHz + * counter, if it exists. If we don't have an accurate processor + * speed, all of the peripherals that derive their clocks based on + * this advertised speed will introduce error and sometimes not work + * properly. This function is futher convoluted to still allow configurations + * to do that in case they have really, really old silicon with a + * write-only PLL register. -- Dan + */ +unsigned long au1xxx_calc_clock(void) +{ + unsigned long cpu_speed; + unsigned long flags; + + spin_lock_irqsave(&time_lock, flags); + + /* + * On early Au1000, sys_cpupll was write-only. Since these + * silicon versions of Au1000 are not sold by AMD, we don't bend + * over backwards trying to determine the frequency. + */ + if (au1xxx_cpu_has_pll_wo()) +#ifdef CONFIG_SOC_AU1000_FREQUENCY + cpu_speed = CONFIG_SOC_AU1000_FREQUENCY; +#else + cpu_speed = 396000000; +#endif + else + cpu_speed = (au_readl(SYS_CPUPLL) & 0x0000003f) * AU1000_SRC_CLK; + + /* On Alchemy CPU:counter ratio is 1:1 */ + mips_hpt_frequency = cpu_speed; + /* Equation: Baudrate = CPU / (SD * 2 * CLKDIV * 16) */ + set_au1x00_uart_baud_base(cpu_speed / (2 * ((int)(au_readl(SYS_POWERCTRL) + & 0x03) + 2) * 16)); + + spin_unlock_irqrestore(&time_lock, flags); + + set_au1x00_speed(cpu_speed); + + return cpu_speed; +} diff --git a/arch/mips/au1000/common/setup.c b/arch/mips/au1000/common/setup.c index b6242c6..c5bd251 100644 --- a/arch/mips/au1000/common/setup.c +++ b/arch/mips/au1000/common/setup.c @@ -41,10 +41,19 @@ extern void __init board_setup(void); extern void au1000_restart(char *); extern void au1000_halt(void); extern void au1000_power_off(void); +extern unsigned long au1xxx_calc_clock(void); void __init plat_mem_setup(void) { char *argptr; + unsigned long est_freq; + + /* determine core clock */ + est_freq = au1xxx_calc_clock(); + est_freq += 5000; /* round */ + est_freq -= est_freq % 10000; + printk(KERN_INFO "(PRId %08x) @ %lu.%02lu MHz\n", read_c0_prid(), + est_freq / 1000000, ((est_freq % 1000000) * 100) / 1000000); board_setup(); /* board specific setup */ diff --git a/arch/mips/au1000/common/time.c b/arch/mips/au1000/common/time.c index fe859c1..0de9a43 100644 --- a/arch/mips/au1000/common/time.c +++ b/arch/mips/au1000/common/time.c @@ -47,53 +47,6 @@ extern int allow_au1k_wait; /* default off for CP0 Counter */ -static DEFINE_SPINLOCK(time_lock); - -/* - * I haven't found anyone that doesn't use a 12 MHz source clock, - * but just in case..... - */ -#define AU1000_SRC_CLK 12000000 - -/* - * We read the real processor speed from the PLL. This is important - * because it is more accurate than computing it from the 32 KHz - * counter, if it exists. If we don't have an accurate processor - * speed, all of the peripherals that derive their clocks based on - * this advertised speed will introduce error and sometimes not work - * properly. This function is futher convoluted to still allow configurations - * to do that in case they have really, really old silicon with a - * write-only PLL register. -- Dan - */ -unsigned long calc_clock(void) -{ - unsigned long cpu_speed; - unsigned long flags; - - spin_lock_irqsave(&time_lock, flags); - - /* - * On early Au1000, sys_cpupll was write-only. Since these - * silicon versions of Au1000 are not sold by AMD, we don't bend - * over backwards trying to determine the frequency. - */ - if (au1xxx_cpu_has_pll_wo()) -#ifdef CONFIG_SOC_AU1000_FREQUENCY - cpu_speed = CONFIG_SOC_AU1000_FREQUENCY; -#else - cpu_speed = 396000000; -#endif - else - cpu_speed = (au_readl(SYS_CPUPLL) & 0x0000003f) * AU1000_SRC_CLK; - /* On Alchemy CPU:counter ratio is 1:1 */ - mips_hpt_frequency = cpu_speed; - /* Equation: Baudrate = CPU / (SD * 2 * CLKDIV * 16) */ - set_au1x00_uart_baud_base(cpu_speed / (2 * ((int)(au_readl(SYS_POWERCTRL) - & 0x03) + 2) * 16)); - spin_unlock_irqrestore(&time_lock, flags); - return cpu_speed; -} - static cycle_t au1x_counter1_read(void) { return au_readl(SYS_RTCREAD); @@ -148,13 +101,6 @@ void __init plat_time_init(void) { struct clock_event_device *cd = &au1x_rtcmatch2_clockdev; unsigned long t; - unsigned int est_freq = calc_clock(); - - est_freq += 5000; /* round */ - est_freq -= est_freq%10000; - printk(KERN_INFO "(PRId %08x) @ %u.%02u MHz\n", read_c0_prid(), - est_freq / 1000000, ((est_freq % 1000000) * 100) / 1000000); - set_au1x00_speed(est_freq); /* Check if firmware (YAMON, ...) has enabled 32kHz and clock * has been detected. If so install the rtcmatch2 clocksource, -- 1.5.6.4 From mano@roarinelk.homelinux.net Tue Aug 12 18:46:57 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 12 Aug 2008 18:47:06 +0100 (BST) Received: from fnoeppeil48.netpark.at ([217.175.205.176]:16063 "EHLO roarinelk.homelinux.net") by ftp.linux-mips.org with ESMTP id S28592163AbYHLRm7 (ORCPT ); Tue, 12 Aug 2008 18:42:59 +0100 Received: (qmail 9132 invoked from network); 12 Aug 2008 19:42:53 +0200 Received: from flagship.roarinelk.net (HELO localhost.localdomain) (192.168.0.197) by 192.168.0.1 with SMTP; 12 Aug 2008 19:42:53 +0200 From: Manuel Lauss To: Ralf Baechle Cc: Kevin Hickey , Linux-MIPS , Manuel Lauss Subject: [PATCH 10/10] Alchemy: new demoboard userspace suspend interface. Date: Tue, 12 Aug 2008 19:42:51 +0200 Message-Id: X-Mailer: git-send-email 1.5.6.4 In-Reply-To: References: In-Reply-To: References: Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20190 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mano@roarinelk.homelinux.net Precedence: bulk X-list: linux-mips Content-Length: 18296 Lines: 674 Replace the current sysctl-based suspend interface with a new sysfs- based one which also uses the Linux-2.6 suspend model. To configure wakeup sources, a subtree for the demoboards is created under /sys/power/db1x: sys/ `-- power `-- db1x |-- gpio0 |-- gpio1 |-- gpio2 |-- gpio3 |-- gpio4 |-- gpio5 |-- gpio6 |-- gpio7 |-- timer |-- timer_timeout |-- uptime |-- wakemsk `-- wakesrc The nodes 'gpio[0-7]' and 'timer' configure the GPIO0..7 and M2 bits of the SYS_WAKEMSK (wakeup source enable) register. Writing '1' enables a wakesource, 0 disables it. The 'timer_timeout' node holds the timeout in seconds after which the TOYMATCH2 event should wake the system. The 'wakesrc' node holds the SYS_WAKESRC register after wakeup (in hex), the 'wakemsk' node can be used to get/set the wakeup mask directly. 'uptime' gives access to the TOY counter value; it can be used for example to track total time in seconds since last kernel boot. For example, to have the timer wake the system after 10 seconds of sleep, the following must be done in userspace: echo 10 > /sys/power/db1x/timer_timeout echo 1 > /sys/power/db1x/timer echo mem > /sys/power/sleep This patch also removes the homebrew CPU frequency switching code. I don't understand how it could have ever worked reliably; it does not communicate the clock changes to other devices tied to BCLK and does not adjust memory controller timings (which is not a problem when the CPU is never clocked higher than what was set by the bootloader). Signed-off-by: Manuel Lauss --- arch/mips/au1000/common/irq.c | 57 +---- arch/mips/au1000/common/platform.c | 423 ++++++++++++++------------------- include/asm-mips/mach-au1x00/au1000.h | 4 + 3 files changed, 193 insertions(+), 291 deletions(-) diff --git a/arch/mips/au1000/common/irq.c b/arch/mips/au1000/common/irq.c index 40c6cec..f5489c3 100644 --- a/arch/mips/au1000/common/irq.c +++ b/arch/mips/au1000/common/irq.c @@ -44,8 +44,6 @@ void (*board_init_irq)(void) __initdata = NULL; -static DEFINE_SPINLOCK(irq_lock); - #ifdef CONFIG_PM /* @@ -130,7 +128,7 @@ void restore_au1xxx_intctl(void) #endif /* CONFIG_PM */ -inline void local_enable_irq(unsigned int irq_nr) +static void local_enable_irq(unsigned int irq_nr) { unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE; @@ -145,7 +143,7 @@ inline void local_enable_irq(unsigned int irq_nr) } -inline void local_disable_irq(unsigned int irq_nr) +static void local_disable_irq(unsigned int irq_nr) { unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE; @@ -160,7 +158,7 @@ inline void local_disable_irq(unsigned int irq_nr) } -static inline void mask_and_ack_rise_edge_irq(unsigned int irq_nr) +static void mask_and_ack_rise_edge_irq(unsigned int irq_nr) { unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE; @@ -175,7 +173,7 @@ static inline void mask_and_ack_rise_edge_irq(unsigned int irq_nr) } -static inline void mask_and_ack_fall_edge_irq(unsigned int irq_nr) +static void mask_and_ack_fall_edge_irq(unsigned int irq_nr) { unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE; @@ -190,7 +188,7 @@ static inline void mask_and_ack_fall_edge_irq(unsigned int irq_nr) } -static inline void mask_and_ack_either_edge_irq(unsigned int irq_nr) +static void mask_and_ack_either_edge_irq(unsigned int irq_nr) { unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE; @@ -210,7 +208,7 @@ static inline void mask_and_ack_either_edge_irq(unsigned int irq_nr) au_sync(); } -static inline void mask_and_ack_level_irq(unsigned int irq_nr) +static void mask_and_ack_level_irq(unsigned int irq_nr) { local_disable_irq(irq_nr); au_sync(); @@ -235,49 +233,6 @@ static void end_irq(unsigned int irq_nr) #endif } -unsigned long save_local_and_disable(int controller) -{ - int i; - unsigned long flags, mask; - - spin_lock_irqsave(&irq_lock, flags); - if (controller) { - mask = au_readl(IC1_MASKSET); - for (i = 32; i < 64; i++) - local_disable_irq(i); - } else { - mask = au_readl(IC0_MASKSET); - for (i = 0; i < 32; i++) - local_disable_irq(i); - } - spin_unlock_irqrestore(&irq_lock, flags); - - return mask; -} - -void restore_local_and_enable(int controller, unsigned long mask) -{ - int i; - unsigned long flags, new_mask; - - spin_lock_irqsave(&irq_lock, flags); - for (i = 0; i < 32; i++) - if (mask & (1 << i)) { - if (controller) - local_enable_irq(i + 32); - else - local_enable_irq(i); - } - - if (controller) - new_mask = au_readl(IC1_MASKSET); - else - new_mask = au_readl(IC0_MASKSET); - - spin_unlock_irqrestore(&irq_lock, flags); -} - - static struct irq_chip rise_edge_irq_type = { .name = "Au1000 Rise Edge", .ack = mask_and_ack_rise_edge_irq, diff --git a/arch/mips/au1000/common/platform.c b/arch/mips/au1000/common/platform.c index b5ff42a..e4c2c31 100644 --- a/arch/mips/au1000/common/platform.c +++ b/arch/mips/au1000/common/platform.c @@ -23,10 +23,6 @@ #include #include #include -#include -#include -#include -#include #include @@ -336,269 +332,214 @@ arch_initcall(au1xxx_platform_init); #ifdef CONFIG_PM -static DEFINE_SPINLOCK(pm_lock); +/* + * Generic suspend for db1x. + * This codes exports a few sysfs nodes under /sys/power/db1x/ + * which can be used by userspace to en/disable certain wakeup sources + * and configure the timeout after which the the TOYMATCH2 irq is to + * trigger a wakeup. + */ + +#include +#include +#include -extern unsigned long save_local_and_disable(int controller); -extern void restore_local_and_enable(int controller, unsigned long mask); -extern void local_enable_irq(unsigned int irq_nr); extern void au_sleep(void); -/* - * Define this to cause the value you write to /proc/sys/pm/sleep to - * set the TOY timer for the amount of time you want to sleep. - * This is done mainly for testing, but may be useful in other cases. - * The value is number of 32KHz ticks to sleep. - */ -#define SLEEP_TEST_TIMEOUT 1 -#ifdef SLEEP_TEST_TIMEOUT -static int sleep_ticks; -static void wakeup_counter0_set(int ticks) -{ - au_writel(au_readl(SYS_TOYREAD) + ticks, SYS_TOYMATCH2); - au_sync(); -} -#endif +static unsigned long db1x_pm_sleep_secs; +static unsigned long db1x_pm_wakemsk; +static unsigned long db1x_pm_last_wakesrc; -static int pm_do_sleep(ctl_table *ctl, int write, struct file *file, - void __user *buffer, size_t *len, loff_t *ppos) +static int db1x_pm_enter(suspend_state_t state) { - unsigned long wakeup, flags; -#ifdef SLEEP_TEST_TIMEOUT -#define TMPBUFLEN2 16 - char buf[TMPBUFLEN2], *p; -#endif + /* enable GPIO based wakeup */ + au_writel(1, SYS_PININPUTEN); + au_sync(); - spin_lock_irqsave(&pm_lock, flags); + /* clear and setup wake cause and source */ + au_writel(0, SYS_WAKEMSK); + au_sync(); + au_writel(0, SYS_WAKESRC); + au_sync(); - if (!write) { - *len = 0; - spin_unlock_irqrestore(&pm_lock, flags); - return 0; - } + au_writel(db1x_pm_wakemsk, SYS_WAKEMSK); + au_sync(); -#ifdef SLEEP_TEST_TIMEOUT - if (*len > TMPBUFLEN2 - 1) - return -EFAULT; - if (copy_from_user(buf, buffer, *len)) - return -EFAULT; - buf[*len] = 0; - p = buf; - sleep_ticks = simple_strtoul(p, &p, 0); -#endif + /* setup 1Hz-timer-based wakeup */ + while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M20) + asm volatile ("nop"); - /** - ** The code below is all system dependent and we should probably - ** have a function call out of here to set this up. You need - ** to configure the GPIO or timer interrupts that will bring - ** you out of sleep. - ** For testing, the TOY counter wakeup is useful. - **/ -#if 0 - au_writel(au_readl(SYS_PINSTATERD) & ~(1 << 11), SYS_PINSTATERD); - - /* GPIO 6 can cause a wake up event */ - wakeup = au_readl(SYS_WAKEMSK); - wakeup &= ~(1 << 8); /* turn off match20 wakeup */ - wakeup |= 1 << 6; /* turn on GPIO 6 wakeup */ -#else - /* For testing, allow match20 to wake us up. */ -#ifdef SLEEP_TEST_TIMEOUT - wakeup_counter0_set(sleep_ticks); -#endif - wakeup = 1 << 8; /* turn on match20 wakeup */ -#endif - au_writel(1, SYS_WAKESRC); /* clear cause */ - au_sync(); - au_writel(wakeup, SYS_WAKEMSK); + au_writel(au_readl(SYS_TOYREAD) + db1x_pm_sleep_secs, SYS_TOYMATCH2); au_sync(); - au_sleep(); + while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M20) + asm volatile ("nop"); - spin_unlock_irqrestore(&pm_lock, flags); + /* ...and now the sandman can come! */ + au_sleep(); return 0; } -#if !defined(CONFIG_SOC_AU1200) && !defined(CONFIG_SOC_AU1550) -/* - * This is the number of bits of precision for the loops_per_jiffy. - * Each bit takes on average 1.5/HZ seconds. This (like the original) - * is a little better than 1%. - */ -#define LPS_PREC 8 - -static void au1000_calibrate_delay(void) +static int db1x_pm_begin(suspend_state_t state) { - unsigned long ticks, loopbit; - int lps_precision = LPS_PREC; - - loops_per_jiffy = 1 << 12; - - while (loops_per_jiffy <<= 1) { - /* Wait for "start of" clock tick */ - ticks = jiffies; - while (ticks == jiffies) - /* nothing */ ; - /* Go ... */ - ticks = jiffies; - __delay(loops_per_jiffy); - ticks = jiffies - ticks; - if (ticks) - break; + if (!db1x_pm_wakemsk) { + printk(KERN_ERR "db1x: no wakeup source activated!\n"); + return -EINVAL; } - /* - * Do a binary approximation to get loops_per_jiffy set to be equal - * one clock (up to lps_precision bits) + return 0; +} + +static void db1x_pm_end(void) +{ + /* read and store wakeup source, the clear the register. To + * be able to clear it, WAKEMSK must be cleared first. */ - loops_per_jiffy >>= 1; - loopbit = loops_per_jiffy; - while (lps_precision-- && (loopbit >>= 1)) { - loops_per_jiffy |= loopbit; - ticks = jiffies; - while (ticks == jiffies); - ticks = jiffies; - __delay(loops_per_jiffy); - if (jiffies != ticks) /* longer than 1 tick */ - loops_per_jiffy &= ~loopbit; - } + db1x_pm_last_wakesrc = au_readl(SYS_WAKESRC); + + au_writel(0, SYS_WAKEMSK); + au_writel(0, SYS_WAKESRC); + au_sync(); + } -static int pm_do_freq(ctl_table *ctl, int write, struct file *file, - void __user *buffer, size_t *len, loff_t *ppos) +static struct platform_suspend_ops db1x_pm_ops = { + .valid = suspend_valid_only_mem, + .begin = db1x_pm_begin, + .enter = db1x_pm_enter, + .end = db1x_pm_end, +}; + +#define ATTRCMP(x) (0 == strcmp(attr->attr.name, #x)) + +static ssize_t db1x_pmattr_show(struct kobject *kobj, + struct kobj_attribute *attr, + char *buf) { - int retval = 0, i; - unsigned long val, pll; -#define TMPBUFLEN 64 -#define MAX_CPU_FREQ 396 - char buf[TMPBUFLEN], *p; - unsigned long flags, intc0_mask, intc1_mask; - unsigned long old_baud_base, old_cpu_freq, old_clk, old_refresh; - unsigned long new_baud_base, new_cpu_freq, new_clk, new_refresh; - unsigned long baud_rate; - - spin_lock_irqsave(&pm_lock, flags); - if (!write) - *len = 0; - else { - /* Parse the new frequency */ - if (*len > TMPBUFLEN - 1) { - spin_unlock_irqrestore(&pm_lock, flags); - return -EFAULT; - } - if (copy_from_user(buf, buffer, *len)) { - spin_unlock_irqrestore(&pm_lock, flags); - return -EFAULT; - } - buf[*len] = 0; - p = buf; - val = simple_strtoul(p, &p, 0); - if (val > MAX_CPU_FREQ) { - spin_unlock_irqrestore(&pm_lock, flags); - return -EFAULT; - } - - pll = val / 12; - if ((pll > 33) || (pll < 7)) { /* 396 MHz max, 84 MHz min */ - /* Revisit this for higher speed CPUs */ - spin_unlock_irqrestore(&pm_lock, flags); - return -EFAULT; - } - - old_baud_base = get_au1x00_uart_baud_base(); - old_cpu_freq = get_au1x00_speed(); - - new_cpu_freq = pll * 12 * 1000000; - new_baud_base = (new_cpu_freq / (2 * ((int)(au_readl(SYS_POWERCTRL) - & 0x03) + 2) * 16)); - set_au1x00_speed(new_cpu_freq); - set_au1x00_uart_baud_base(new_baud_base); - - old_refresh = au_readl(MEM_SDREFCFG) & 0x1ffffff; - new_refresh = ((old_refresh * new_cpu_freq) / old_cpu_freq) | - (au_readl(MEM_SDREFCFG) & ~0x1ffffff); - - au_writel(pll, SYS_CPUPLL); - au_sync_delay(1); - au_writel(new_refresh, MEM_SDREFCFG); - au_sync_delay(1); - - for (i = 0; i < 4; i++) - if (au_readl(UART_BASE + UART_MOD_CNTRL + - i * 0x00100000) == 3) { - old_clk = au_readl(UART_BASE + UART_CLK + - i * 0x00100000); - baud_rate = old_baud_base / old_clk; - /* - * We won't get an exact baud rate and the error - * could be significant enough that our new - * calculation will result in a clock that will - * give us a baud rate that's too far off from - * what we really want. - */ - if (baud_rate > 100000) - baud_rate = 115200; - else if (baud_rate > 50000) - baud_rate = 57600; - else if (baud_rate > 30000) - baud_rate = 38400; - else if (baud_rate > 17000) - baud_rate = 19200; - else - baud_rate = 9600; - new_clk = new_baud_base / baud_rate; - au_writel(new_clk, UART_BASE + UART_CLK + - i * 0x00100000); - au_sync_delay(10); - } + int idx; + + if (ATTRCMP(timer_timeout)) + return sprintf(buf, "%lu\n", db1x_pm_sleep_secs); + + else if (ATTRCMP(timer)) + return sprintf(buf, "%u\n", + !!(db1x_pm_wakemsk & SYS_WAKEMSK_M2)); + + else if (ATTRCMP(wakesrc)) + return sprintf(buf, "%lu\n", db1x_pm_last_wakesrc); + + else if (ATTRCMP(uptime)) + return sprintf(buf, "%lu\n", + (unsigned long)au_readl(SYS_TOYREAD)); + + else if (ATTRCMP(gpio0) || ATTRCMP(gpio1) || ATTRCMP(gpio2) || + ATTRCMP(gpio3) || ATTRCMP(gpio4) || ATTRCMP(gpio5) || + ATTRCMP(gpio6) || ATTRCMP(gpio7)) { + idx = (attr->attr.name)[4] - '0'; + return sprintf(buf, "%d\n", + !!(db1x_pm_wakemsk & SYS_WAKEMSK_GPIO(idx))); + + } else if (ATTRCMP(wakemsk)) { + return sprintf(buf, "%08lx\n", db1x_pm_wakemsk); } - /* - * We don't want _any_ interrupts other than match20. Otherwise our - * au1000_calibrate_delay() calculation will be off, potentially a lot. - */ - intc0_mask = save_local_and_disable(0); - intc1_mask = save_local_and_disable(1); - local_enable_irq(AU1000_TOY_MATCH2_INT); - spin_unlock_irqrestore(&pm_lock, flags); - au1000_calibrate_delay(); - restore_local_and_enable(0, intc0_mask); - restore_local_and_enable(1, intc1_mask); - - return retval; + return -ENOENT; } -#endif -static struct ctl_table pm_table[] = { - { - .ctl_name = CTL_UNNUMBERED, - .procname = "sleep", - .data = NULL, - .maxlen = 0, - .mode = 0600, - .proc_handler = &pm_do_sleep - }, -#if !defined(CONFIG_SOC_AU1200) && !defined(CONFIG_SOC_AU1550) - { - .ctl_name = CTL_UNNUMBERED, - .procname = "freq", - .data = NULL, - .maxlen = 0, - .mode = 0600, - .proc_handler = &pm_do_freq - }, -#endif - {} +static ssize_t db1x_pmattr_store(struct kobject *kobj, + struct kobj_attribute *attr, + const char *instr, + size_t bytes) +{ + unsigned long l; + int tmp; + + if (ATTRCMP(timer_timeout)) { + tmp = strict_strtoul(instr, 0, &l); + if (tmp) + return tmp; + + db1x_pm_sleep_secs = l; + + } else if (ATTRCMP(timer)) { + if (instr[0] != '0') + db1x_pm_wakemsk |= SYS_WAKEMSK_M2; + else + db1x_pm_wakemsk &= ~SYS_WAKEMSK_M2; + + } else if (ATTRCMP(gpio0) || ATTRCMP(gpio1) || ATTRCMP(gpio2) || + ATTRCMP(gpio3) || ATTRCMP(gpio4) || ATTRCMP(gpio5) || + ATTRCMP(gpio6) || ATTRCMP(gpio7)) { + tmp = (attr->attr.name)[4] - '0'; + if (instr[0] != '0') + db1x_pm_wakemsk |= SYS_WAKEMSK_GPIO(tmp); + else + db1x_pm_wakemsk &= ~SYS_WAKEMSK_GPIO(tmp); + + } else if (ATTRCMP(uptime)) { + tmp = strict_strtoul(instr, 0, &l); + if (tmp) + return tmp; + + while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C0S) + asm volatile ("nop"); + au_writel(l, SYS_TOYWRITE); + au_sync(); + + } else if (ATTRCMP(wakemsk)) { + tmp = strict_strtoul(instr, 0, &l); + if (tmp) + return tmp; + + db1x_pm_wakemsk = l & 0x0000003f; + + } else + bytes = -ENOENT; + + return bytes; +} + +#define ATTR(x) \ + static struct kobj_attribute x##_attribute = \ + __ATTR(x, 0664, db1x_pmattr_show, \ + db1x_pmattr_store); + +ATTR(gpio0) /* GPIO-based wakeup enable */ +ATTR(gpio1) +ATTR(gpio2) +ATTR(gpio3) +ATTR(gpio4) +ATTR(gpio5) +ATTR(gpio6) +ATTR(gpio7) +ATTR(timer) /* TOYMATCH2-based wakeup enable */ +ATTR(timer_timeout) /* timer-based wakeup timeout value, in seconds */ +ATTR(uptime) /* contents of SYS_TOYREAD */ +ATTR(wakesrc) /* contents of SYS_WAKESRC after last wakeup */ +ATTR(wakemsk) /* direct access to SYS_WAKEMSK */ + +#define ATTR_LIST(x) & x ## _attribute.attr +static struct attribute *db1x_pmattrs[] = { + ATTR_LIST(gpio0), + ATTR_LIST(gpio1), + ATTR_LIST(gpio2), + ATTR_LIST(gpio3), + ATTR_LIST(gpio4), + ATTR_LIST(gpio5), + ATTR_LIST(gpio6), + ATTR_LIST(gpio7), + ATTR_LIST(timer), + ATTR_LIST(timer_timeout), + ATTR_LIST(uptime), + ATTR_LIST(wakesrc), + ATTR_LIST(wakemsk), + NULL, /* terminator */ }; -static struct ctl_table pm_dir_table[] = { - { - .ctl_name = CTL_UNNUMBERED, - .procname = "pm", - .mode = 0555, - .child = pm_table - }, - {} +static struct attribute_group db1x_pmattr_group = { + .name = "db1x", + .attrs = db1x_pmattrs, }; /* @@ -615,14 +556,16 @@ static int __init pm_init(void) au_sync(); } + db1x_pm_last_wakesrc = au_readl(SYS_WAKESRC); + au_writel(0, SYS_WAKESRC); au_sync(); au_writel(0, SYS_WAKEMSK); au_sync(); - register_sysctl_table(pm_dir_table); + suspend_set_ops(&db1x_pm_ops); - return 0; + return sysfs_create_group(power_kobj, &db1x_pmattr_group); } __initcall(pm_init); diff --git a/include/asm-mips/mach-au1x00/au1000.h b/include/asm-mips/mach-au1x00/au1000.h index 7245960..639480e 100644 --- a/include/asm-mips/mach-au1x00/au1000.h +++ b/include/asm-mips/mach-au1x00/au1000.h @@ -1561,6 +1561,10 @@ enum soc_au1200_ints { #define SYS_SLPPWR 0xB1900078 #define SYS_SLEEP 0xB190007C +#define SYS_WAKEMSK_D2 (1 << 9) +#define SYS_WAKEMSK_M2 (1 << 8) +#define SYS_WAKEMSK_GPIO(x) (1 << (x)) + /* Clock Controller */ #define SYS_FREQCTRL0 0xB1900020 # define SYS_FC_FRDIV2_BIT 22 -- 1.5.6.4 From khickey@rmicorp.com Tue Aug 12 20:08:09 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 12 Aug 2008 20:08:16 +0100 (BST) Received: from mx1.razamicroelectronics.com ([63.111.213.197]:17002 "EHLO hq-ex-mb01.razamicroelectronics.com") by ftp.linux-mips.org with ESMTP id S28591897AbYHLTIJ (ORCPT ); Tue, 12 Aug 2008 20:08:09 +0100 Received: from 10.8.0.25 ([10.8.0.25]) by hq-ex-mb01.razamicroelectronics.com ([10.1.1.40]) via Exchange Front-End Server webmail.razamicroelectronics.com ([10.1.1.41]) with Microsoft Exchange Server HTTP-DAV ; Tue, 12 Aug 2008 19:07:59 +0000 Received: from kh-ubuntu by webmail.razamicroelectronics.com; 12 Aug 2008 14:08:23 -0500 Subject: Re: [PATCH 00/10] Alchemy updates v5 From: Kevin Hickey To: Manuel Lauss Cc: Ralf Baechle , Linux-MIPS In-Reply-To: References: Content-Type: text/plain Content-Transfer-Encoding: 7bit Date: Tue, 12 Aug 2008 14:08:23 -0500 Message-Id: <1218568103.18180.6.camel@kh-ubuntu.razamicroelectronics.com> Mime-Version: 1.0 X-Mailer: Evolution 2.22.3.1 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20191 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: khickey@rmicorp.com Precedence: bulk X-list: linux-mips Content-Length: 521 Lines: 19 Ralf et al., On Tue, 2008-08-12 at 19:42 +0200, Manuel Lauss wrote: > [Ralf: Please consider this series for 2.6.27 inclusion if it is still > possible to sneak them in] I'd like to second this request. I have some work that I would like to do that depends on these patches. I've tested them on my system and they appear solid. Feel free to add my Acked-By line to them: Acked-by: Kevin Hickey Thanks. > -- Kevin Hickey Alchemy Solutions RMI Corporation khickey@RMICorp.com P: 512.691.8044 From mano@roarinelk.homelinux.net Tue Aug 12 20:21:25 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 12 Aug 2008 20:21:32 +0100 (BST) Received: from fnoeppeil48.netpark.at ([217.175.205.176]:38626 "EHLO roarinelk.homelinux.net") by ftp.linux-mips.org with ESMTP id S28591902AbYHLTVZ (ORCPT ); Tue, 12 Aug 2008 20:21:25 +0100 Received: (qmail 9777 invoked from network); 12 Aug 2008 21:21:22 +0200 Received: from scarran.roarinelk.net (HELO localhost.localdomain) (192.168.0.242) by 192.168.0.1 with SMTP; 12 Aug 2008 21:21:22 +0200 From: Manuel Lauss To: Ralf Baechle Cc: Kevin Hickey , linux-mips@linux-mips.org, Manuel Lauss Subject: [PATCH] Alchemy: modernize Pb1200 IRQ cascade handling code. Date: Tue, 12 Aug 2008 21:21:21 +0200 Message-Id: <1218568881-3544-2-git-send-email-mano@roarinelk.homelinux.net> X-Mailer: git-send-email 1.5.6.4 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20192 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mano@roarinelk.homelinux.net Precedence: bulk X-list: linux-mips Content-Length: 3439 Lines: 121 Signed-off-by: Manuel Lauss --- arch/mips/au1000/pb1200/irqmap.c | 75 +++++++++----------------------------- 1 files changed, 18 insertions(+), 57 deletions(-) diff --git a/arch/mips/au1000/pb1200/irqmap.c b/arch/mips/au1000/pb1200/irqmap.c index 2a505ad..7229f30 100644 --- a/arch/mips/au1000/pb1200/irqmap.c +++ b/arch/mips/au1000/pb1200/irqmap.c @@ -48,62 +48,26 @@ int __initdata au1xxx_nr_irqs = ARRAY_SIZE(au1xxx_irq_map); /* * Support for External interrupts on the Pb1200 Development platform. */ -static volatile int pb1200_cascade_en; -irqreturn_t pb1200_cascade_handler(int irq, void *dev_id) +static void pb1200_cascade_handler(unsigned int irq, struct irq_desc *desc) { unsigned short bisr = bcsr->int_status; - int extirq_nr = 0; - - /* Clear all the edge interrupts. This has no effect on level. */ - bcsr->int_status = bisr; - for ( ; bisr; bisr &= bisr - 1) { - extirq_nr = PB1200_INT_BEGIN + __ffs(bisr); - /* Ack and dispatch IRQ */ - do_IRQ(extirq_nr); - } - return IRQ_RETVAL(1); + for ( ; bisr; bisr &= bisr - 1) + generic_handle_irq(PB1200_INT_BEGIN + __ffs(bisr)); } -inline void pb1200_enable_irq(unsigned int irq_nr) +static void pb1200_unmask_irq(unsigned int irq_nr) { bcsr->intset_mask = 1 << (irq_nr - PB1200_INT_BEGIN); bcsr->intset = 1 << (irq_nr - PB1200_INT_BEGIN); } -inline void pb1200_disable_irq(unsigned int irq_nr) +static void pb1200_maskack_irq(unsigned int irq_nr) { bcsr->intclr_mask = 1 << (irq_nr - PB1200_INT_BEGIN); bcsr->intclr = 1 << (irq_nr - PB1200_INT_BEGIN); -} - -static unsigned int pb1200_setup_cascade(void) -{ - return request_irq(AU1000_GPIO_7, &pb1200_cascade_handler, - 0, "Pb1200 Cascade", &pb1200_cascade_handler); -} - -static unsigned int pb1200_startup_irq(unsigned int irq) -{ - if (++pb1200_cascade_en == 1) { - int res; - - res = pb1200_setup_cascade(); - if (res) - return res; - } - - pb1200_enable_irq(irq); - - return 0; -} - -static void pb1200_shutdown_irq(unsigned int irq) -{ - pb1200_disable_irq(irq); - if (--pb1200_cascade_en == 0) - free_irq(AU1000_GPIO_7, &pb1200_cascade_handler); + bcsr->int_status = 1 << (irq_nr - PB1200_INT_BEGIN); /* ack */ } static struct irq_chip external_irq_type = { @@ -113,12 +77,9 @@ static struct irq_chip external_irq_type = { #ifdef CONFIG_MIPS_DB1200 .name = "Db1200 Ext", #endif - .startup = pb1200_startup_irq, - .shutdown = pb1200_shutdown_irq, - .ack = pb1200_disable_irq, - .mask = pb1200_disable_irq, - .mask_ack = pb1200_disable_irq, - .unmask = pb1200_enable_irq, + .mask = pb1200_maskack_irq, + .mask_ack = pb1200_maskack_irq, + .unmask = pb1200_unmask_irq, }; void _board_init_irq(void) @@ -147,14 +108,14 @@ void _board_init_irq(void) } #endif - for (irq = PB1200_INT_BEGIN; irq <= PB1200_INT_END; irq++) { - set_irq_chip_and_handler(irq, &external_irq_type, - handle_level_irq); - pb1200_disable_irq(irq); - } + /* mask & disable & ack all */ + bcsr->intclr_mask = 0xffff; + bcsr->intclr = 0xffff; + bcsr->int_status = 0xffff; + + for (irq = PB1200_INT_BEGIN; irq <= PB1200_INT_END; irq++) + set_irq_chip_and_handler_name(irq, &external_irq_type, + handle_level_irq, "level"); - /* - * GPIO_7 can not be hooked here, so it is hooked upon first - * request of any source attached to the cascade. - */ + set_irq_chained_handler(AU1000_GPIO_7, pb1200_cascade_handler); } -- 1.5.6.4 From mano@roarinelk.homelinux.net Tue Aug 12 20:21:48 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Tue, 12 Aug 2008 20:21:54 +0100 (BST) Received: from fnoeppeil48.netpark.at ([217.175.205.176]:26853 "EHLO roarinelk.homelinux.net") by ftp.linux-mips.org with ESMTP id S28591923AbYHLTVZ (ORCPT ); Tue, 12 Aug 2008 20:21:25 +0100 Received: (qmail 9776 invoked from network); 12 Aug 2008 21:21:22 +0200 Received: from scarran.roarinelk.net (HELO localhost.localdomain) (192.168.0.242) by 192.168.0.1 with SMTP; 12 Aug 2008 21:21:22 +0200 From: Manuel Lauss To: Ralf Baechle Cc: Kevin Hickey , linux-mips@linux-mips.org, Manuel Lauss Subject: [PATCH] Alchemy: rework DBDMA init sequence. Date: Tue, 12 Aug 2008 21:21:20 +0200 Message-Id: <1218568881-3544-1-git-send-email-mano@roarinelk.homelinux.net> X-Mailer: git-send-email 1.5.6.4 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20193 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mano@roarinelk.homelinux.net Precedence: bulk X-list: linux-mips Content-Length: 1962 Lines: 67 Signed-off-by: Manuel Lauss --- arch/mips/au1000/common/dbdma.c | 25 +++++++++---------------- 1 files changed, 9 insertions(+), 16 deletions(-) diff --git a/arch/mips/au1000/common/dbdma.c b/arch/mips/au1000/common/dbdma.c index 601ee91..c1f0a3c 100644 --- a/arch/mips/au1000/common/dbdma.c +++ b/arch/mips/au1000/common/dbdma.c @@ -57,8 +57,6 @@ static DEFINE_SPINLOCK(au1xxx_dbdma_spin_lock); #define ALIGN_ADDR(x, a) ((((u32)(x)) + (a-1)) & ~(a-1)) static dbdma_global_t *dbdma_gptr = (dbdma_global_t *)DDMA_GLOBAL_BASE; -static int dbdma_initialized; -static void au1xxx_dbdma_init(void); static dbdev_tab_t dbdev_tab[] = { #ifdef CONFIG_SOC_AU1550 @@ -239,15 +237,6 @@ u32 au1xxx_dbdma_chan_alloc(u32 srcid, u32 destid, chan_tab_t *ctp; au1x_dma_chan_t *cp; - /* - * We do the intialization on the first channel allocation. - * We have to wait because of the interrupt handler initialization - * which can't be done successfully during board set up. - */ - if (!dbdma_initialized) - au1xxx_dbdma_init(); - dbdma_initialized = 1; - stp = find_dbdev_id(srcid); if (stp == NULL) return 0; @@ -863,9 +852,9 @@ static irqreturn_t dbdma_interrupt(int irq, void *dev_id) return IRQ_RETVAL(1); } -static void au1xxx_dbdma_init(void) +static int __init au1xxx_dbdma_init(void) { - int irq_nr; + int irq_nr, ret; dbdma_gptr->ddma_config = 0; dbdma_gptr->ddma_throttle = 0; @@ -880,10 +869,14 @@ static void au1xxx_dbdma_init(void) #error Unknown Au1x00 SOC #endif - if (request_irq(irq_nr, dbdma_interrupt, IRQF_DISABLED, - "Au1xxx dbdma", (void *)dbdma_gptr)) - printk(KERN_ERR "Can't get 1550 dbdma irq"); + ret = request_irq(irq_nr, dbdma_interrupt, IRQF_DISABLED, + "Au1xxx dbdma", (void *)dbdma_gptr); + if (ret) + printk(KERN_ERR "Au1xxx dbdma: cannot get IRQ\n"); + + return ret; } +subsys_initcall(au1xxx_dbdma_init); void au1xxx_dbdma_dump(u32 chanid) { -- 1.5.6.4 From fahim@redback.com Wed Aug 13 00:44:09 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 13 Aug 2008 00:44:20 +0100 (BST) Received: from prattle.redback.com ([155.53.12.9]:39641 "EHLO prattle.redback.com") by ftp.linux-mips.org with ESMTP id S28593169AbYHLXoJ (ORCPT ); Wed, 13 Aug 2008 00:44:09 +0100 Received: from localhost (localhost [127.0.0.1]) by prattle.redback.com (Postfix) with ESMTP id 5992743274 for ; Tue, 12 Aug 2008 16:44:06 -0700 (PDT) Received: from prattle.redback.com ([127.0.0.1]) by localhost (prattle [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 05460-08 for ; Tue, 12 Aug 2008 16:44:06 -0700 (PDT) Received: from [155.53.46.182] (provo.redback.com [155.53.46.182]) by prattle.redback.com (Postfix) with ESMTP id 452B343272 for ; Tue, 12 Aug 2008 16:44:05 -0700 (PDT) Message-ID: <48A22045.4060503@redback.com> Date: Tue, 12 Aug 2008 16:44:05 -0700 From: Fahim Ansari User-Agent: Thunderbird 2.0.0.6 (X11/20070728) MIME-Version: 1.0 To: linux-mips@linux-mips.org Subject: Cavium support Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-Virus-Scanned: by amavisd-new at redback.com Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20194 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: fahim@redback.com Precedence: bulk X-list: linux-mips Content-Length: 231 Lines: 7 I want to build a kernel that will boot on a cavium octeon board. Is the cavium octeon cpuset supported for the linux kernels available at linux-mips.org. Or is such a kernel available at any other git repository? Thanks, Fahim From james@loowit.net Wed Aug 13 01:23:55 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 13 Aug 2008 01:24:02 +0100 (BST) Received: from mail.windriver.com ([147.11.1.11]:41983 "EHLO mail.wrs.com") by ftp.linux-mips.org with ESMTP id S28593019AbYHMAXz (ORCPT ); Wed, 13 Aug 2008 01:23:55 +0100 Received: from ALA-MAIL03.corp.ad.wrs.com (ala-mail03 [147.11.57.144]) by mail.wrs.com (8.13.6/8.13.6) with ESMTP id m7D0NiTF011332; Tue, 12 Aug 2008 17:23:45 -0700 (PDT) Received: from ala-mail06.corp.ad.wrs.com ([147.11.57.147]) by ALA-MAIL03.corp.ad.wrs.com with Microsoft SMTPSVC(6.0.3790.1830); Tue, 12 Aug 2008 17:23:44 -0700 Received: from [147.11.222.75] ([147.11.222.75]) by ala-mail06.corp.ad.wrs.com with Microsoft SMTPSVC(6.0.3790.1830); Tue, 12 Aug 2008 17:23:44 -0700 Message-ID: <48A2298F.6020601@loowit.net> Date: Tue, 12 Aug 2008 17:23:43 -0700 From: James Perkins User-Agent: Thunderbird 2.0.0.14 (X11/20080501) MIME-Version: 1.0 To: Fahim Ansari CC: linux-mips@linux-mips.org Subject: Re: Cavium support References: <48A22045.4060503@redback.com> In-Reply-To: <48A22045.4060503@redback.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit X-OriginalArrivalTime: 13 Aug 2008 00:23:44.0559 (UTC) FILETIME=[D882F3F0:01C8FCDA] Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20195 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: james@loowit.net Precedence: bulk X-list: linux-mips Content-Length: 616 Lines: 15 Fahim Ansari wrote: > I want to build a kernel that will boot on a cavium octeon board. Is the > cavium octeon cpuset supported for the linux kernels available at > linux-mips.org. > Or is such a kernel available at any other git repository? I'm not aware of any public git repositories tracking OCTEON at present. The current linux-mips.org project has no support for Cavium Networks OCTEON. There are commercial ports available: Cavium's SDK, and in embedded Linux distributions from Wind River and Montavista. You may want to try contacting Cavium at their website. Cheers, James Perkins james@loowit.net From blf.ireland@gmail.com Wed Aug 13 08:05:55 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 13 Aug 2008 08:06:00 +0100 (BST) Received: from fg-out-1718.google.com ([72.14.220.155]:14443 "EHLO fg-out-1718.google.com") by ftp.linux-mips.org with ESMTP id S20037176AbYHMHFz convert rfc822-to-8bit (ORCPT ); Wed, 13 Aug 2008 08:05:55 +0100 Received: by fg-out-1718.google.com with SMTP id d23so1455070fga.32 for ; Wed, 13 Aug 2008 00:05:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:reply-to:to:subject:date :user-agent:cc:references:in-reply-to:mime-version:content-type :content-transfer-encoding:content-disposition:message-id:sender; bh=2GNKLrcW+kIAAi6ibQRaGJKcht0cF3WDmD4e2bTR3nk=; b=FOTgmWDKGW52EE5DtZNqi9dwt3VrUzxEJmg+5mAPFljTPMKqIHvqptOtx5pSOBe47l F+8L4RzYDQAly/rakSwg01uLF5W2DFavDmHCFbEqkwvLJ8EHzjQ+EnxyaTQrdYgR0OoR HTy9rAcuAdx4Qrmi6L941hbmfRsKWGnk4imH8= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:reply-to:to:subject:date:user-agent:cc:references:in-reply-to :mime-version:content-type:content-transfer-encoding :content-disposition:message-id:sender; b=kBt+MB6XyOTRRCKQfwZsgahuVssPJU8CeUAws5Zi2CTg1YZvP9Ql7gXjETlvQzKTVO w02olGCtxtBbxCMxFHjAWblGo9CjiuqA7CpGhXmPw1iq6E5f8WT/7wvNAoB60D/Mhi+5 EvtEDA3cV7tOg+ihoMyhwogJ3I9q8Y8UYF/o8= Received: by 10.86.58.3 with SMTP id g3mr11811941fga.21.1218611153823; Wed, 13 Aug 2008 00:05:53 -0700 (PDT) Received: from innova-card.com ( [81.252.61.1]) by mx.google.com with ESMTPS id 4sm7522754fgg.4.2008.08.13.00.05.51 (version=TLSv1/SSLv3 cipher=RC4-MD5); Wed, 13 Aug 2008 00:05:52 -0700 (PDT) From: Brian Foster Reply-To: Brian Foster To: linux-mips@linux-mips.org Subject: Re: Debugging the MIPS processor using GDB Date: Wed, 13 Aug 2008 09:05:53 +0200 User-Agent: KMail/1.9.6 (enterprise 0.20070907.709405) Cc: "Maciej W. Rozycki" , Martin Gebert , TriKri References: <18944199.post@talk.nabble.com> <200808121637.42148.brian.foster@innova-card.com> In-Reply-To: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8BIT Content-Disposition: inline Message-Id: <200808130905.53671.brian.foster@innova-card.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20196 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: brian.foster@innova-card.com Precedence: bulk X-list: linux-mips Content-Length: 2047 Lines: 49 On Tuesday 12 August 2008 18:27:42 Maciej W. Rozycki wrote: > On Tue, 12 Aug 2008, Brian Foster wrote: > > I'm using the commercial FS² (First Silicon Systems, now owned > > by MIPS) EJTAG probe. [ ... ] There is no ‘gdbserver’ in this > > setup per se, albeit I suppose the protocol between ‘gdb’ and > > the FS² software [ ... ] might be similar/identical[?] > > Not really -- it uses a C API called MDI -- the spec is available from > MIPS Technologies. I am happy to read somebody finds it useful. :) > Debugging the Linux kernel with GDB and this piece of hardware is > certainly a lot of fun. Maciej, Thanks for the clarification. I didn't know if MDI was related to the remote-‘gdbserver’ stuff or not. Re the FS²: When it works, my (somewhat limited) experience to-date is it works Ok. And the use of TCL on the Host workstation side allows some neat tricks. However, at least one thing doesn't work reliably for me, albeit I've never investigated: Breakpoints in the Linux kernel. They do detonate. Then, sometimes, I can ‘c’(ontinue) or ‘s’(tep) Ok. But other times, when I ‘c’ or ‘s’, the breakpoint detonates again and I'm stuck. I cannot proceed. (The same breakpoint might even work once or twice and then fail.) Any ideas? AFAICR, this can also happen if I try to use the ‘sysnav’ console instead of ‘gdb’. I understand my predecessor in my job I gave up on the FS² (very possibly because of this breakpoint issue?) and used a competing (E?)JTAG probe. Weirdly, I've only seen this effect with the Linux kernel — other kernel-mode software (e.g., the trivial custom bootloader) — doesn't seem to suffer from these “flakey FS² breakpoints”? cheers! -blf- -- “How many surrealists does it take to | Brian Foster change a lightbulb? Three. One calms | somewhere in south of France the warthog, and two fill the bathtub | Stop E$$o (ExxonMobil)! with brightly-coloured machine tools.” | http://www.stopesso.com From sshtylyov@ru.mvista.com Wed Aug 13 13:34:28 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 13 Aug 2008 13:34:38 +0100 (BST) Received: from h155.mvista.com ([63.81.120.155]:49328 "EHLO imap.sh.mvista.com") by ftp.linux-mips.org with ESMTP id S20037423AbYHMMe2 (ORCPT ); Wed, 13 Aug 2008 13:34:28 +0100 Received: from [127.0.0.1] (unknown [10.150.0.9]) by imap.sh.mvista.com (Postfix) with ESMTP id DC0D63EC9; Wed, 13 Aug 2008 05:34:22 -0700 (PDT) Message-ID: <48A2D4CB.1030901@ru.mvista.com> Date: Wed, 13 Aug 2008 16:34:19 +0400 From: Sergei Shtylyov User-Agent: Thunderbird 2.0.0.16 (Windows/20080708) MIME-Version: 1.0 To: Manuel Lauss Cc: Ralf Baechle , Kevin Hickey , linux-mips@linux-mips.org Subject: Re: [PATCH] Alchemy: modernize Pb1200 IRQ cascade handling code. References: <1218568881-3544-2-git-send-email-mano@roarinelk.homelinux.net> In-Reply-To: <1218568881-3544-2-git-send-email-mano@roarinelk.homelinux.net> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20197 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: sshtylyov@ru.mvista.com Precedence: bulk X-list: linux-mips Content-Length: 3171 Lines: 106 Hello. Manuel Lauss wrote: > Signed-off-by: Manuel Lauss > [...] > diff --git a/arch/mips/au1000/pb1200/irqmap.c b/arch/mips/au1000/pb1200/irqmap.c > index 2a505ad..7229f30 100644 > --- a/arch/mips/au1000/pb1200/irqmap.c > +++ b/arch/mips/au1000/pb1200/irqmap.c > @@ -48,62 +48,26 @@ int __initdata au1xxx_nr_irqs = ARRAY_SIZE(au1xxx_irq_map); > /* > * Support for External interrupts on the Pb1200 Development platform. > */ > -static volatile int pb1200_cascade_en; > > -irqreturn_t pb1200_cascade_handler(int irq, void *dev_id) > +static void pb1200_cascade_handler(unsigned int irq, struct irq_desc *desc) > { > unsigned short bisr = bcsr->int_status; > - int extirq_nr = 0; > - > - /* Clear all the edge interrupts. This has no effect on level. */ > Note this comment... > - bcsr->int_status = bisr; > - for ( ; bisr; bisr &= bisr - 1) { > - extirq_nr = PB1200_INT_BEGIN + __ffs(bisr); > - /* Ack and dispatch IRQ */ > - do_IRQ(extirq_nr); > - } > > - return IRQ_RETVAL(1); > + for ( ; bisr; bisr &= bisr - 1) > + generic_handle_irq(PB1200_INT_BEGIN + __ffs(bisr)); > } > > -inline void pb1200_enable_irq(unsigned int irq_nr) > +static void pb1200_unmask_irq(unsigned int irq_nr) > { > bcsr->intset_mask = 1 << (irq_nr - PB1200_INT_BEGIN); > bcsr->intset = 1 << (irq_nr - PB1200_INT_BEGIN); > } > > -inline void pb1200_disable_irq(unsigned int irq_nr) > +static void pb1200_maskack_irq(unsigned int irq_nr) > { > bcsr->intclr_mask = 1 << (irq_nr - PB1200_INT_BEGIN); > bcsr->intclr = 1 << (irq_nr - PB1200_INT_BEGIN); > I wonder what's the difference between int{clr|set} and int{clr|set}_mask registers... [...] > + bcsr->int_status = 1 << (irq_nr - PB1200_INT_BEGIN); /* ack */ > The above comment said that writing to this register has no effect on the level-triggered interrupts, so this statement doesn't seem to make sense since you're treating all interrupts as level-triggered below. > @@ -113,12 +77,9 @@ static struct irq_chip external_irq_type = { > #ifdef CONFIG_MIPS_DB1200 > .name = "Db1200 Ext", > #endif > - .startup = pb1200_startup_irq, > - .shutdown = pb1200_shutdown_irq, > - .ack = pb1200_disable_irq, > - .mask = pb1200_disable_irq, > - .mask_ack = pb1200_disable_irq, > - .unmask = pb1200_enable_irq, > + .mask = pb1200_maskack_irq, > + .mask_ack = pb1200_maskack_irq, > You can use the same function for the mask() and mask_ack() methods but it only should be masking IRQ, as clearing it doesn't make sense... > @@ -147,14 +108,14 @@ void _board_init_irq(void) > } > #endif > > - for (irq = PB1200_INT_BEGIN; irq <= PB1200_INT_END; irq++) { > - set_irq_chip_and_handler(irq, &external_irq_type, > - handle_level_irq); > - pb1200_disable_irq(irq); > - } > + /* mask & disable & ack all */ > + bcsr->intclr_mask = 0xffff; > + bcsr->intclr = 0xffff; > + bcsr->int_status = 0xffff; > + > + for (irq = PB1200_INT_BEGIN; irq <= PB1200_INT_END; irq++) > + set_irq_chip_and_handler_name(irq, &external_irq_type, > + handle_level_irq, "level"); > Are all those IRQs indeed level-triggered? WBR, Sergei From mano@roarinelk.homelinux.net Wed Aug 13 13:59:26 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 13 Aug 2008 13:59:33 +0100 (BST) Received: from fnoeppeil48.netpark.at ([217.175.205.176]:11467 "EHLO roarinelk.homelinux.net") by ftp.linux-mips.org with ESMTP id S20036895AbYHMM70 (ORCPT ); Wed, 13 Aug 2008 13:59:26 +0100 Received: (qmail 16477 invoked from network); 13 Aug 2008 14:59:23 +0200 Received: from unknown (HELO scarran) (192.168.0.242) by fnoeppeil48.netpark.at with SMTP; 13 Aug 2008 14:59:23 +0200 Date: Wed, 13 Aug 2008 14:59:21 +0200 From: Manuel Lauss To: Sergei Shtylyov Cc: Ralf Baechle , Kevin Hickey , linux-mips@linux-mips.org Subject: Re: [PATCH] Alchemy: modernize Pb1200 IRQ cascade handling code. Message-ID: <20080813145921.159b2180@scarran> In-Reply-To: <48A2D4CB.1030901@ru.mvista.com> References: <1218568881-3544-2-git-send-email-mano@roarinelk.homelinux.net> <48A2D4CB.1030901@ru.mvista.com> Organization: Private X-Mailer: Claws Mail 3.5.0 (GTK+ 2.12.11; i686-pc-linux-gnu) Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20198 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: mano@roarinelk.homelinux.net Precedence: bulk X-list: linux-mips Content-Length: 2872 Lines: 83 On Wed, 13 Aug 2008 16:34:19 +0400 Sergei Shtylyov wrote: > > -inline void pb1200_enable_irq(unsigned int irq_nr) > > +static void pb1200_unmask_irq(unsigned int irq_nr) > > { > > bcsr->intset_mask = 1 << (irq_nr - PB1200_INT_BEGIN); > > bcsr->intset = 1 << (irq_nr - PB1200_INT_BEGIN); > > } > > > > -inline void pb1200_disable_irq(unsigned int irq_nr) > > +static void pb1200_maskack_irq(unsigned int irq_nr) > > { > > bcsr->intclr_mask = 1 << (irq_nr - PB1200_INT_BEGIN); > > bcsr->intclr = 1 << (irq_nr - PB1200_INT_BEGIN); > > > > I wonder what's the difference between int{clr|set} and > int{clr|set}_mask registers... The irq assertion equation in the CPLD is: int_condition = inten & intmask & int_input_pin; In theory, the ->startup() and ->shutdown() methods should fiddle with the enable bits; the ->mask()/->unmask() methods should modfiy the mask bits. In practice, at least on my DB1200, if not BOTH of the enable and mask bits are cleared, the CPLD triggers tons of spurious interrupts. I read through the verilog sources but could not find a reason for this... > [...] > > + bcsr->int_status = 1 << (irq_nr - PB1200_INT_BEGIN); /* ack */ > > > > The above comment said that writing to this register has no effect on > the level-triggered interrupts, so this statement doesn't seem to make > sense since you're treating all interrupts as level-triggered below. They _all_ behave level-triggered, even the ones that should be edge. Again, looking at the verilog code, no edge detection or similar is implemented; for instance the SD card insert/eject irqs should be edge-triggered, but behave differently: the insert irq stays asserted as long as a card is in the socket, the eject irq is asserted as long as no card is present. The PCMCIA carrdetect irqs exhibit identical behaviour. > > @@ -113,12 +77,9 @@ static struct irq_chip external_irq_type = { > > #ifdef CONFIG_MIPS_DB1200 > > .name = "Db1200 Ext", > > #endif > > - .startup = pb1200_startup_irq, > > - .shutdown = pb1200_shutdown_irq, > > - .ack = pb1200_disable_irq, > > - .mask = pb1200_disable_irq, > > - .mask_ack = pb1200_disable_irq, > > - .unmask = pb1200_enable_irq, > > + .mask = pb1200_maskack_irq, > > + .mask_ack = pb1200_maskack_irq, > > > > You can use the same function for the mask() and mask_ack() methods > but it only should be masking IRQ, as clearing it doesn't make sense... It doesn't make a difference in practice, but I'll create a separate ->mask() method without the acking part of the supposedly-edge ints ;-) > > + for (irq = PB1200_INT_BEGIN; irq <= PB1200_INT_END; irq++) > > + set_irq_chip_and_handler_name(irq, &external_irq_type, > > + handle_level_irq, "level"); > > > > Are all those IRQs indeed level-triggered? See above. Thanks, Manuel Lauss From tbm@cyrius.com Wed Aug 13 14:00:18 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 13 Aug 2008 14:00:23 +0100 (BST) Received: from sorrow.cyrius.com ([65.19.161.204]:1542 "EHLO sorrow.cyrius.com") by ftp.linux-mips.org with ESMTP id S20037605AbYHMNAS (ORCPT ); Wed, 13 Aug 2008 14:00:18 +0100 Received: by sorrow.cyrius.com (Postfix, from userid 10) id 971DDD8DF; Wed, 13 Aug 2008 13:00:15 +0000 (UTC) Received: by deprecation.cyrius.com (Postfix, from userid 1000) id 2AF4A150670; Wed, 13 Aug 2008 15:59:55 +0300 (IDT) Date: Wed, 13 Aug 2008 15:59:55 +0300 From: Martin Michlmayr To: Thomas Bogendoerfer Cc: linux-mips@linux-mips.org Subject: "indy_volume_button" [sound/oss/hal2.ko] undefined Message-ID: <20080813125954.GA3203@deprecation.cyrius.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20199 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: tbm@cyrius.com Precedence: bulk X-list: linux-mips Content-Length: 199 Lines: 7 sound/oss/hal2.ko fails to build because indy_volume_button was removed from the IP22 code. Is sound/oss/hal2o going to be removed before 2.6.27 is out? -- Martin Michlmayr http://www.cyrius.com/ From ralf@linux-mips.org Wed Aug 13 14:05:15 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 13 Aug 2008 14:05:21 +0100 (BST) Received: from ditditdahdahdah-dahditditditdit.dl5rb.org.uk ([217.169.26.26]:56506 "EHLO ditditdahdahdah-dahdahdahditdit.dl5rb.org.uk") by ftp.linux-mips.org with ESMTP id S28593694AbYHMNFP (ORCPT ); Wed, 13 Aug 2008 14:05:15 +0100 Received: from denk.linux-mips.net (denk.linux-mips.net [127.0.0.1]) by ditditdahdahdah-dahdahdahditdit.dl5rb.org.uk (8.14.2/8.14.1) with ESMTP id m7DD577B027458; Wed, 13 Aug 2008 14:05:10 +0100 Received: (from ralf@localhost) by denk.linux-mips.net (8.14.2/8.14.2/Submit) id m7DD51IP027448; Wed, 13 Aug 2008 14:05:01 +0100 Date: Wed, 13 Aug 2008 14:05:01 +0100 From: Ralf Baechle To: James Perkins Cc: Fahim Ansari , linux-mips@linux-mips.org Subject: Re: Cavium support Message-ID: <20080813130501.GB27188@linux-mips.org> References: <48A22045.4060503@redback.com> <48A2298F.6020601@loowit.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <48A2298F.6020601@loowit.net> User-Agent: Mutt/1.5.18 (2008-05-17) Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20200 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: ralf@linux-mips.org Precedence: bulk X-list: linux-mips Content-Length: 727 Lines: 17 On Tue, Aug 12, 2008 at 05:23:43PM -0700, James Perkins wrote: > Fahim Ansari wrote: >> I want to build a kernel that will boot on a cavium octeon board. Is >> the cavium octeon cpuset supported for the linux kernels available at >> linux-mips.org. >> Or is such a kernel available at any other git repository? > > I'm not aware of any public git repositories tracking OCTEON at present. > The current linux-mips.org project has no support for Cavium Networks > OCTEON. There are commercial ports available: Cavium's SDK, and in > embedded Linux distributions from Wind River and Montavista. You may want > to try contacting Cavium at their website. I got a Cavium board now so I hopefully can change that :-) Ralf From macro@linux-mips.org Wed Aug 13 14:50:02 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 13 Aug 2008 14:50:13 +0100 (BST) Received: from kirk.serum.com.pl ([213.77.9.205]:61168 "EHLO serum.com.pl") by ftp.linux-mips.org with ESMTP id S28594489AbYHMNuC (ORCPT ); Wed, 13 Aug 2008 14:50:02 +0100 Received: from serum.com.pl (IDENT:macro@localhost [127.0.0.1]) by serum.com.pl (8.12.11/8.12.11) with ESMTP id m7DDnnEg000540; Wed, 13 Aug 2008 15:49:49 +0200 Received: from localhost (macro@localhost) by serum.com.pl (8.12.11/8.12.11/Submit) with ESMTP id m7DDnefC000536; Wed, 13 Aug 2008 14:49:48 +0100 Date: Wed, 13 Aug 2008 14:49:39 +0100 (BST) From: "Maciej W. Rozycki" To: Brian Foster cc: linux-mips@linux-mips.org, Martin Gebert , TriKri Subject: Re: Debugging the MIPS processor using GDB In-Reply-To: <200808130905.53671.brian.foster@innova-card.com> Message-ID: References: <18944199.post@talk.nabble.com> <200808121637.42148.brian.foster@innova-card.com> <200808130905.53671.brian.foster@innova-card.com> MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=ISO-8859-1 Content-Transfer-Encoding: 8BIT Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20201 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: macro@linux-mips.org Precedence: bulk X-list: linux-mips Content-Length: 1069 Lines: 23 On Wed, 13 Aug 2008, Brian Foster wrote: > Re the FS²: When it works, my (somewhat limited) > experience to-date is it works Ok. And the use of > TCL on the Host workstation side allows some neat > tricks. However, at least one thing doesn't work > reliably for me, albeit I've never investigated: > Breakpoints in the Linux kernel. They do detonate. > Then, sometimes, I can ‘c’(ontinue) or ‘s’(tep) Ok. > But other times, when I ‘c’ or ‘s’, the breakpoint > detonates again and I'm stuck. I cannot proceed. > (The same breakpoint might even work once or twice > and then fail.) Any ideas? AFAICR, this can also > happen if I try to use the ‘sysnav’ console instead > of ‘gdb’. Hmm, odd. It looks like a cache coherence issue. It could be a bug in your version of FS2 software -- did you raise the issue with them? Anyway, as a workaround try setting "coherent=on" (quoting from memory) in fs2.ini (just an idea -- it may not work and you will lose some performance though) or use hardware breakpoints. Maciej From jfraser@broadcom.com Wed Aug 13 15:42:02 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 13 Aug 2008 15:42:09 +0100 (BST) Received: from mms1.broadcom.com ([216.31.210.17]:30214 "EHLO mms1.broadcom.com") by ftp.linux-mips.org with ESMTP id S20028965AbYHMOmC convert rfc822-to-8bit (ORCPT ); Wed, 13 Aug 2008 15:42:02 +0100 Received: from [10.11.16.99] by mms1.broadcom.com with ESMTP (Broadcom SMTP Relay (Email Firewall v6.3.2)); Wed, 13 Aug 2008 07:41:45 -0700 X-Server-Uuid: 02CED230-5797-4B57-9875-D5D2FEE4708A Received: by mail-irva-10.broadcom.com (Postfix, from userid 47) id 7B7E72B1; Wed, 13 Aug 2008 07:41:45 -0700 (PDT) Received: from mail-irva-8.broadcom.com (mail-irva-8 [10.11.18.52]) by mail-irva-10.broadcom.com (Postfix) with ESMTP id 64E212B0; Wed, 13 Aug 2008 07:41:45 -0700 (PDT) Received: from mail-irva-13.broadcom.com (mail-irva-13.broadcom.com [10.11.16.103]) by mail-irva-8.broadcom.com (MOS 3.7.5a-GA) with ESMTP id HBP38896; Wed, 13 Aug 2008 07:41:36 -0700 (PDT) Received: from [10.28.6.13] (lab-mhtb-013.ne.broadcom.com [10.28.6.13]) by mail-irva-13.broadcom.com (Postfix) with ESMTP id 616A374CFE; Wed, 13 Aug 2008 07:41:35 -0700 (PDT) Subject: Re: Debugging the MIPS processor using GDB From: "Jon Fraser" Reply-to: jfraser@broadcom.com To: "Brian Foster" cc: linux-mips@linux-mips.org, "Maciej W. Rozycki" , "Martin Gebert" , TriKri In-Reply-To: <200808130905.53671.brian.foster@innova-card.com> References: <18944199.post@talk.nabble.com> <200808121637.42148.brian.foster@innova-card.com> <200808130905.53671.brian.foster@innova-card.com> Organization: Broadcom Date: Wed, 13 Aug 2008 10:41:34 -0400 Message-ID: <1218638494.21039.6.camel@chaos.ne.broadcom.com> MIME-Version: 1.0 X-Mailer: Evolution 2.12.3 (2.12.3-3.fc8) X-WSS-ID: 64BC2D234E0115004117-01-01 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8BIT Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20202 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: jfraser@broadcom.com Precedence: bulk X-list: linux-mips Content-Length: 2097 Lines: 58 FYI, I use the FS2 probe with sde-gdb on a nearly daily basis. Are you compiling your kernel with -g -O1 ? You can also try 'hbreak' instead of 'break' in sde-gdb. Jon On Wed, 2008-08-13 at 09:05 +0200, Brian Foster wrote: > On Tuesday 12 August 2008 18:27:42 Maciej W. Rozycki wrote: > > On Tue, 12 Aug 2008, Brian Foster wrote: > > > I'm using the commercial FS² (First Silicon Systems, now owned > > > by MIPS) EJTAG probe. [ ... ] There is no ‘gdbserver’ in this > > > setup per se, albeit I suppose the protocol between ‘gdb’ and > > > the FS² software [ ... ] might be similar/identical[?] > > > > Not really -- it uses a C API called MDI -- the spec is available from > > MIPS Technologies. I am happy to read somebody finds it useful. :) > > Debugging the Linux kernel with GDB and this piece of hardware is > > certainly a lot of fun. > > Maciej, > > Thanks for the clarification. I didn't know if MDI > was related to the remote-‘gdbserver’ stuff or not. > > Re the FS²: When it works, my (somewhat limited) > experience to-date is it works Ok. And the use of > TCL on the Host workstation side allows some neat > tricks. However, at least one thing doesn't work > reliably for me, albeit I've never investigated: > Breakpoints in the Linux kernel. They do detonate. > Then, sometimes, I can ‘c’(ontinue) or ‘s’(tep) Ok. > But other times, when I ‘c’ or ‘s’, the breakpoint > detonates again and I'm stuck. I cannot proceed. > (The same breakpoint might even work once or twice > and then fail.) Any ideas? AFAICR, this can also > happen if I try to use the ‘sysnav’ console instead > of ‘gdb’. > > I understand my predecessor in my job I gave up on > the FS² (very possibly because of this breakpoint > issue?) and used a competing (E?)JTAG probe. > > Weirdly, I've only seen this effect with the Linux > kernel — other kernel-mode software (e.g., the trivial > custom bootloader) — doesn't seem to suffer from these > “flakey FS² breakpoints”? > > cheers! > -blf- > From blf.ireland@gmail.com Wed Aug 13 16:07:27 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 13 Aug 2008 16:07:35 +0100 (BST) Received: from fg-out-1718.google.com ([72.14.220.154]:24346 "EHLO fg-out-1718.google.com") by ftp.linux-mips.org with ESMTP id S28593481AbYHMPH1 convert rfc822-to-8bit (ORCPT ); Wed, 13 Aug 2008 16:07:27 +0100 Received: by fg-out-1718.google.com with SMTP id d23so39780fga.32 for ; Wed, 13 Aug 2008 08:07:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:reply-to:to:subject:date :user-agent:cc:references:in-reply-to:mime-version:content-type :content-transfer-encoding:content-disposition:message-id:sender; bh=kUoGw88q050d3HOoa9ATJERfvra1w79e+irsG6UUEcg=; b=qCVD7YKcRiJYNh8fULi7tgy7nwtOcOVXWtzpdlZTgyizQoio4rGChWoCG5ZBOy/28l nxiJJGOrqUL88Ow4PEU/3hVvw28nx+nKsVanjKHTEscbAUtDdAlvFxIJQS7f7d3lck2R K15mMRuozzsWH4NKwmiVdbGAPY9C47QuYEBd4= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:reply-to:to:subject:date:user-agent:cc:references:in-reply-to :mime-version:content-type:content-transfer-encoding :content-disposition:message-id:sender; b=RGCe3DSBOM2jZLbTywMRHpQ6SkEmx2frsuD0YuHW0WV5hgwS7UgCVtFzn4IpKGdMYs gLeQZ1SRTmBIo5h65q0EQ/9me7+LtqSDnWL/5ollsBvQJfSUpjHV5KN+UbJcaNivazeV NHmcRB3pNaG5avTynp+Od503Er+UnTCu2BeKk= Received: by 10.86.52.6 with SMTP id z6mr134884fgz.18.1218640045636; Wed, 13 Aug 2008 08:07:25 -0700 (PDT) Received: from innova-card.com ( [81.252.61.1]) by mx.google.com with ESMTPS id d4sm1172063fga.8.2008.08.13.08.07.21 (version=TLSv1/SSLv3 cipher=RC4-MD5); Wed, 13 Aug 2008 08:07:24 -0700 (PDT) From: Brian Foster Reply-To: Brian Foster To: "Maciej W. Rozycki" Subject: Re: Debugging the MIPS processor using GDB Date: Wed, 13 Aug 2008 17:07:30 +0200 User-Agent: KMail/1.9.6 (enterprise 0.20070907.709405) Cc: linux-mips@linux-mips.org, Martin Gebert , TriKri References: <18944199.post@talk.nabble.com> <200808130905.53671.brian.foster@innova-card.com> In-Reply-To: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8BIT Content-Disposition: inline Message-Id: <200808131707.30570.brian.foster@innova-card.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20203 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: brian.foster@innova-card.com Precedence: bulk X-list: linux-mips Content-Length: 2619 Lines: 73 On Wednesday 13 August 2008 15:49:39 Maciej W. Rozycki wrote: > On Wed, 13 Aug 2008, Brian Foster wrote: > > > Re the FS²: [ ... ] at least one thing doesn't work > > reliably for me [ ... ]: Breakpoints in the Linux kernel. > > They do detonate. Then, sometimes, I can ‘c’(ontinue) or > > ‘s’(tep) Ok. But other times, when I ‘c’ or ‘s’, the > > breakpoint detonates again and I'm stuck. [ ... ] > > Hmm, odd. It looks like a cache coherence issue. Maciej, That would be my guess also. > It could be a bug in your version of FS2 software -- did you raise the issue with them? I've been trying to. (I cannot say more on this ATM, sorry!) I'm using the most recent FS² (2.4.4) with the most recent SDE-Lite from MIPS (V6.06.01). Older versions of FS²/SDE had the same(?) issue. (This is with a 4KSd core, running Little Endian.) What _might_ be an issue/cause is we're using our own home-grown ‘gdb’ scripts (to init the memory, load the kernel, etc.). I didn't write them, but I have looked them over, and they _look_ Ok to me. > Anyway, as a workaround try setting "coherent=on" (quoting from memory) > in fs2.ini (just an idea -- it may not work and you will lose some > performance though) or use hardware breakpoints. As it turns out, I _have_ been running Coherent On! So I tried turning if Off, just to see what would happen. No difference. The behavior I saw was: 1. gdb b xxx_open 2. target cat /dev/xxx 3. (breakpoint detonates) 4. gdb x/i $pc (all is Ok) 5. gdb c (Ok) 6. target cat /dev/xxx 7. (breakpoint detonates) 8. gdb x/i $pc (wrong! instruction is ‘sdbbp’.) I'm now stuck. Any attempt to ‘c’ or ‘s’ just hits the breakpoint again. I tried some “mdi cacheflush” at some plausible-seeming points, all to no effect. I also tried deleting the breakpoint (after step 8), which was a disaster: (From memory) when I then ‘c’(ontinued), ‘gdb’ hung, and the ‘sysnav’ went into an infinite loop of reporting a breakpoint. ;-( ( I seem to recall also having an issue with hardware breakpoints, but cannot recall for certain ATM; tests will have to wait until later .... ;-\ ) All ideas and suggestions are very welcome! cheers! -blf- -- “How many surrealists does it take to | Brian Foster change a lightbulb? Three. One calms | somewhere in south of France the warthog, and two fill the bathtub | Stop E$$o (ExxonMobil)! with brightly-coloured machine tools.” | http://www.stopesso.com From blf.ireland@gmail.com Wed Aug 13 16:12:29 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 13 Aug 2008 16:12:35 +0100 (BST) Received: from fg-out-1718.google.com ([72.14.220.157]:29729 "EHLO fg-out-1718.google.com") by ftp.linux-mips.org with ESMTP id S28593068AbYHMPM3 convert rfc822-to-8bit (ORCPT ); Wed, 13 Aug 2008 16:12:29 +0100 Received: by fg-out-1718.google.com with SMTP id d23so40890fga.32 for ; Wed, 13 Aug 2008 08:12:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:reply-to:to:subject:date :user-agent:cc:references:in-reply-to:mime-version:content-type :content-transfer-encoding:content-disposition:message-id:sender; bh=eXZSNNYkoMD9Hd5tzeJTtQzVia1VjeLal8Fi31EjVIE=; b=pK0qPf0wF5inUvCQOwD3qEBtJo9ZLMdM36iLCdVYm/SXcKGD5PKFh1ssT/kwUAKnIG SQpu7FDdKuYt1M0pVY3xmE4YqqpDtujRIzGoR63a+cyKPNShzj4VNDVkaDYK/XkkBbJB q0hMXwo7xmYp9owh3yex0OTs75e8IZLrJMRwU= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:reply-to:to:subject:date:user-agent:cc:references:in-reply-to :mime-version:content-type:content-transfer-encoding :content-disposition:message-id:sender; b=frYir0hMM7cxQrbwX7S30jDr6Cnxi+IhP90kY4GMDeD34ntrCgreQKlTOv2l/DUYqv vmeVUsgeg11sTGGdobySZzQUZ9iHjYFjQq2q5DTzLM6xvfwVaRRx/MHaKGkCVjwcJbbg FM3xr4OWNfma7Rm1AbNO29AWJ8TMBisX+CpsQ= Received: by 10.86.83.2 with SMTP id g2mr99565fgb.54.1218640347420; Wed, 13 Aug 2008 08:12:27 -0700 (PDT) Received: from innova-card.com ( [81.252.61.1]) by mx.google.com with ESMTPS id d4sm1181466fga.8.2008.08.13.08.12.26 (version=TLSv1/SSLv3 cipher=RC4-MD5); Wed, 13 Aug 2008 08:12:26 -0700 (PDT) From: Brian Foster Reply-To: Brian Foster To: jfraser@broadcom.com Subject: Re: Debugging the MIPS processor using GDB Date: Wed, 13 Aug 2008 17:12:34 +0200 User-Agent: KMail/1.9.6 (enterprise 0.20070907.709405) Cc: linux-mips@linux-mips.org, "Maciej W. Rozycki" , TriKri References: <18944199.post@talk.nabble.com> <200808130905.53671.brian.foster@innova-card.com> <1218638494.21039.6.camel@chaos.ne.broadcom.com> In-Reply-To: <1218638494.21039.6.camel@chaos.ne.broadcom.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8BIT Content-Disposition: inline Message-Id: <200808131712.34722.brian.foster@innova-card.com> Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20204 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: brian.foster@innova-card.com Precedence: bulk X-list: linux-mips Content-Length: 856 Lines: 24 On Wednesday 13 August 2008 16:41:34 Jon Fraser wrote: > I use the FS2 probe with sde-gdb on a nearly daily basis. > Are you compiling your kernel with -g -O1 ? Jon, ‘-g’, yes. ‘-O1’? Not sure, I will have to check when I get a chance. (But I don't see how either would have the effect on breakpoints I'm suffering from?) > You can also try 'hbreak' instead of 'break' in sde-gdb. I'll have to (re-)try that when I get a chance. I did try it once, and have (very! vague!!) memories of some issue, but now cannot recall anything useful. ;-\ cheers! -blf- -- “How many surrealists does it take to | Brian Foster change a lightbulb? Three. One calms | somewhere in south of France the warthog, and two fill the bathtub | Stop E$$o (ExxonMobil)! with brightly-coloured machine tools.” | http://www.stopesso.com From macro@linux-mips.org Wed Aug 13 16:16:52 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 13 Aug 2008 16:16:57 +0100 (BST) Received: from kirk.serum.com.pl ([213.77.9.205]:50418 "EHLO serum.com.pl") by ftp.linux-mips.org with ESMTP id S20023228AbYHMPQw (ORCPT ); Wed, 13 Aug 2008 16:16:52 +0100 Received: from serum.com.pl (IDENT:macro@localhost [127.0.0.1]) by serum.com.pl (8.12.11/8.12.11) with ESMTP id m7DFGkeB001127; Wed, 13 Aug 2008 17:16:46 +0200 Received: from localhost (macro@localhost) by serum.com.pl (8.12.11/8.12.11/Submit) with ESMTP id m7DFGfhL001121; Wed, 13 Aug 2008 16:16:46 +0100 Date: Wed, 13 Aug 2008 16:16:41 +0100 (BST) From: "Maciej W. Rozycki" To: Brian Foster cc: linux-mips@linux-mips.org, Martin Gebert , TriKri Subject: Re: Debugging the MIPS processor using GDB In-Reply-To: <200808131707.30570.brian.foster@innova-card.com> Message-ID: References: <18944199.post@talk.nabble.com> <200808130905.53671.brian.foster@innova-card.com> <200808131707.30570.brian.foster@innova-card.com> MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=utf-8 Content-Transfer-Encoding: 8BIT Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 20205 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: macro@linux-mips.org Precedence: bulk X-list: linux-mips Content-Length: 1082 Lines: 28 On Wed, 13 Aug 2008, Brian Foster wrote: > What _might_ be an issue/cause is we're using our own > home-grown ‘gdb’ scripts (to init the memory, load the > kernel, etc.). I didn't write them, but I have looked > them over, and they _look_ Ok to me. That should not matter. For example you could boot your system in the usual way provided by the firmware and attach to an already running kernel. The probe does not know or care about that. > I tried some “mdi cacheflush” at some plausible-seeming > points, all to no effect. I also tried deleting the > breakpoint (after step 8), which was a disaster: (From > memory) when I then ‘c’(ontinued), ‘gdb’ hung, and the > ‘sysnav’ went into an infinite loop of reporting a > breakpoint. ;-( > > ( I seem to recall also having an issue with hardware > breakpoints, but cannot recall for certain ATM; tests > will have to wait until later .... ;-\ ) > > All ideas and suggestions are very welcome! Your situation looks pretty miserable -- you should definitely pester FS2. Maciej From WilliaVi@cisco.com Wed Aug 13 20:21:49 2008 Received: with ECARTIS (v1.0.0; list linux-mips); Wed, 13 Aug 2008 20:21:58 +0100 (BST) Received: from sj-iport-6.cisco.com ([171.71.176.117]:13947 "EHLO sj-iport-6.cisco.com") by ftp.linux-mips.org with ESMTP id S28594360AbYHMTVt (ORCPT ); Wed, 13 Aug 2008 20:21:49 +0100 X-IronPort-AV: E=Sophos;i="4.32,202,1217808000"; d="scan'208,217";a="139639996" Received: from sj-dkim-2.cisco.com ([171.71.179.186]) by sj-iport-6.cisco.com with ESMTP; 13 Aug 2008 19:21:37 +0000 Received: from sj-core-1.cisco.com (sj-core-1.cisco.com [171.71.177.237]) by sj-dkim-2.cisco.com (8.12.11/8.12.11) with ESMTP id m7DJLa6V016767 for ; Wed, 13 Aug 2008 12:21:36 -0700 Received: from sausatlsmtp2.sciatl.com ([192.133.217.159]) by sj-core-1.cisco.com (8.13.8/8.13.8) with ESMTP id m7DJLaOU023949 for ; Wed, 13 Aug 2008 19:21:36 GMT Received: from default.com ([192.133.217.159]) by sausatlsmtp2.sciatl.com with Microsoft SMTPSVC(6.0.3790.3959); Wed, 13 Aug 2008 15:21:35 -0400 Received: from sausatlbhs02.corp.sa.net ([192.133.216.42]) by sausatlsmtp2.sciatl.com with Microsoft SMTPSVC(6.0.3790.3959); Wed, 13 Aug 2008 15:21:34 -0400 Received: from sausatlexch1.corp.sa.net ([192.133.216.10]) by sausatlbhs02.corp.sa.net with Microsoft SMTPSVC(6.0.3790.3959); Wed, 13 Aug 2008 15:21:34 -0400 X-MimeOLE: Produced By Microsoft Exchange V6.5 Content-class: urn:content-classes:message MIME-Version: 1.0 Content-Type: multipart/alternative; boundary="----_=_NextPart_001_01C8FD79.CCB9E124" Subject: [PATCH 1/1] MIPS: Fix "max_mapnr" assignment bug Date: Wed, 13 Aug 2008 15:21:37 -0400 Message-ID: X-MS-Has-Attach: X-MS-TNEF-Correlator: Thread-Topic: [PATCH 1/1] MIPS: Fix "max_mapnr" assignment bug thread-index: Acj9ec5SbgKHBAQgQEiMCICYlIRLGg== From: "Williams, Victor L." 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